diff --git a/hw/Makefile b/hw/Makefile index 75f401d0822..95540bccb30 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -1,3 +1,4 @@ +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -48,7 +49,7 @@ IPS ?= aes \ uart \ usbdev -TOPS ?= top_darjeeling top_earlgrey top_englishbreakfast +TOPS ?= top_darjeeling top_darjeeling_no_ibex top_earlgrey top_englishbreakfast USE_BUFFER ?= 0 diff --git a/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_part_pkg.sv.tpl b/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_part_pkg.sv.tpl index 999c9e271ba..d0368c63ede 100644 --- a/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_part_pkg.sv.tpl +++ b/hw/ip_templates/otp_ctrl/rtl/otp_ctrl_part_pkg.sv.tpl @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -225,9 +226,17 @@ package otp_ctrl_part_pkg; ${int(part["size"])*8}'({ % for item in part["items"][::-1]: % if offset != item['offset'] + item['size']: + % if (offset - item['size'] - item['offset']) * 8 >= 65536: + ${"{{{}'h{:0X}, {}'h{:0X}}}".format((offset - item['size'] - item['offset']) * 8 - 65536, 0, 65536, 0)}, // unallocated space<% offset = item['offset'] + item['size'] %> + % else: ${"{}'h{:0X}".format((offset - item['size'] - item['offset']) * 8, 0)}, // unallocated space<% offset = item['offset'] + item['size'] %> + % endif % endif + % if item["size"] * 8 >= 65536: + ${"{{{}'h{:0X}, {}'h{:0X}}}".format(item["size"] * 8 - 65536, item["inv_default"], 65536, item["inv_default"])}${("\n })," if k < len(otp_mmap["partitions"])-1 else "\n })});") if loop.last else ","}<% offset -= item['size'] %> + % else: ${"{}'h{:0X}".format(item["size"] * 8, item["inv_default"])}${("\n })," if k < len(otp_mmap["partitions"])-1 else "\n })});") if loop.last else ","}<% offset -= item['size'] %> + % endif % endfor % endfor diff --git a/hw/top_darjeeling/data/autogen/BUILD b/hw/top_darjeeling/data/autogen/BUILD index 0d618a755d6..5a1fd62df83 100644 --- a/hw/top_darjeeling/data/autogen/BUILD +++ b/hw/top_darjeeling/data/autogen/BUILD @@ -1,3 +1,4 @@ +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_darjeeling/data/autogen/defs.bzl b/hw/top_darjeeling/data/autogen/defs.bzl index db043093ba9..5ea80806a97 100644 --- a/hw/top_darjeeling/data/autogen/defs.bzl +++ b/hw/top_darjeeling/data/autogen/defs.bzl @@ -1,3 +1,4 @@ +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson index 07dd966eaae..9da8f936d9c 100644 --- a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson +++ b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson b/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson index b2b736f51d1..7a8a3c2322d 100644 --- a/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson +++ b/hw/top_darjeeling/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson index ee48f841f29..e6d46fa8b32 100644 --- a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson b/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson index 30769424d1b..52083292381 100644 --- a/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson +++ b/hw/top_darjeeling/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson index 9a5506d3fd6..dda4813ca41 100644 --- a/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson +++ b/hw/top_darjeeling/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv b/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv index f2218c38b8a..18393d859ba 100644 --- a/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv +++ b/hw/top_darjeeling/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -566,7 +567,7 @@ package otp_ctrl_part_pkg; 78784'({ 64'hC469C593E5DC0DA8, 5184'h0, // unallocated space - 73536'h0 + {8000'h0, 65536'h0} }), 8192'({ 8192'h0 diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv index ccf21aeb1f0..c2308658417 100644 --- a/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv +++ b/hw/top_darjeeling/rtl/autogen/top_darjeeling.sv @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_darjeeling/templates/toplevel.sv.tpl b/hw/top_darjeeling/templates/toplevel.sv.tpl index 8848b4c3500..88e696653a6 100644 --- a/hw/top_darjeeling/templates/toplevel.sv.tpl +++ b/hw/top_darjeeling/templates/toplevel.sv.tpl @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -17,6 +18,7 @@ top_has_alert_handler = lib.find_module(top['module'], 'alert_handler') is not N top_has_ast = lib.find_module(top['module'], 'ast') is not None top_has_rstmgr = lib.find_module(top['module'], 'rstmgr') is not None top_has_gpio = lib.find_module(top['module'], 'gpio') is not None +top_has_ibex = lib.find_module(top['module'], 'rv_core_ibex') is not None top_has_scan_en = False for m in top['module']: if not lib.is_inst(m): @@ -380,6 +382,7 @@ module top_${top["name"]} #( assign rsts_ast_o = ${top['resets'].hier_paths['top'][:-1]}; % endif +% if top_has_ibex: // ibex specific assignments // TODO: This should be further automated in the future. assign rv_core_ibex_irq_timer = intr_rv_timer_timer_expired_hart0_timer0; @@ -388,15 +391,16 @@ module top_${top["name"]} #( // Unconditionally disable the late debug feature and enable early debug assign rv_dm_otp_dis_rv_dm_late_debug = prim_mubi_pkg::MuBi8True; -% if 'rv_core_ibex_boot_addr' in (sig['signame'] for sig in top['inter_signal']['definitions']): - ## Not all top levels have a rom controller. - ## For those that do not, reference the ROM directly. -<% num_rom_ctrl = lib.num_rom_ctrl(top["module"]) %>\ - % if num_rom_ctrl != 0: - assign rv_core_ibex_boot_addr = ADDR_SPACE_ROM_CTRL0__ROM; - % else: - ## Not all top levels have - assign rv_core_ibex_boot_addr = ADDR_SPACE_ROM; + % if 'rv_core_ibex_boot_addr' in (sig['signame'] for sig in top['inter_signal']['definitions']): + ## Not all top levels have a rom controller. + ## For those that do not, reference the ROM directly. + <% num_rom_ctrl = lib.num_rom_ctrl(top["module"]) %>\ + % if num_rom_ctrl != 0: +assign rv_core_ibex_boot_addr = ADDR_SPACE_ROM_CTRL0__ROM; + % else: + ## Not all top levels have +assign rv_core_ibex_boot_addr = ADDR_SPACE_ROM; + % endif % endif % endif diff --git a/hw/top_darjeeling_no_ibex/data/autogen/BUILD b/hw/top_darjeeling_no_ibex/data/autogen/BUILD new file mode 100644 index 00000000000..8518abd8f1c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/autogen/BUILD @@ -0,0 +1,11 @@ +# Copyright zeroRISC Inc. +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------# +# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +# util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +# -o hw/top_darjeeling_no_ibex + +exports_files(["top_darjeeling_no_ibex.gen.hjson"]) diff --git a/hw/top_darjeeling_no_ibex/data/autogen/defs.bzl b/hw/top_darjeeling_no_ibex/data/autogen/defs.bzl new file mode 100644 index 00000000000..b64369b5c35 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/autogen/defs.bzl @@ -0,0 +1,77 @@ +# Copyright zeroRISC Inc. +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------# +# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +# util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +# -o hw/top_darjeeling_no_ibex + +load("//hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check:defs.bzl", "AC_RANGE_CHECK") +load("//hw/ip/aes:defs.bzl", "AES") +load("//hw/top_darjeeling_no_ibex/ip_autogen/alert_handler:defs.bzl", "ALERT_HANDLER") +load("//hw/ip/aon_timer:defs.bzl", "AON_TIMER") +load("//hw/top_darjeeling_no_ibex/ip/ast:defs.bzl", "AST") +load("//hw/top_darjeeling_no_ibex/ip_autogen/clkmgr:defs.bzl", "CLKMGR") +load("//hw/ip/csrng:defs.bzl", "CSRNG") +load("//hw/ip/dma:defs.bzl", "DMA") +load("//hw/ip/edn:defs.bzl", "EDN") +load("//hw/ip/entropy_src:defs.bzl", "ENTROPY_SRC") +load("//hw/top_darjeeling_no_ibex/ip_autogen/gpio:defs.bzl", "GPIO") +load("//hw/ip/hmac:defs.bzl", "HMAC") +load("//hw/ip/i2c:defs.bzl", "I2C") +load("//hw/ip/keymgr_dpe:defs.bzl", "KEYMGR_DPE") +load("//hw/ip/kmac:defs.bzl", "KMAC") +load("//hw/ip/lc_ctrl:defs.bzl", "LC_CTRL") +load("//hw/ip/mbx:defs.bzl", "MBX") +load("//hw/ip/otbn:defs.bzl", "OTBN") +load("//hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl:defs.bzl", "OTP_CTRL") +load("//hw/ip/otp_macro:defs.bzl", "OTP_MACRO") +load("//hw/top_darjeeling_no_ibex/ip_autogen/pinmux:defs.bzl", "PINMUX") +load("//hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr:defs.bzl", "PWRMGR") +load("//hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl:defs.bzl", "RACL_CTRL") +load("//hw/ip/rom_ctrl:defs.bzl", "ROM_CTRL") +load("//hw/top_darjeeling_no_ibex/ip_autogen/rstmgr:defs.bzl", "RSTMGR") +load("//hw/top_darjeeling_no_ibex/ip_autogen/rv_plic:defs.bzl", "RV_PLIC") +load("//hw/ip/soc_dbg_ctrl:defs.bzl", "SOC_DBG_CTRL") +load("//hw/top_darjeeling_no_ibex/ip/soc_proxy:defs.bzl", "SOC_PROXY") +load("//hw/ip/spi_device:defs.bzl", "SPI_DEVICE") +load("//hw/ip/spi_host:defs.bzl", "SPI_HOST") +load("//hw/ip/sram_ctrl:defs.bzl", "SRAM_CTRL") +load("//hw/ip/uart:defs.bzl", "UART") + +DARJEELING_NO_IBEX_IPS = [ + AC_RANGE_CHECK, + AES, + ALERT_HANDLER, + AON_TIMER, + AST, + CLKMGR, + CSRNG, + DMA, + EDN, + ENTROPY_SRC, + GPIO, + HMAC, + I2C, + KEYMGR_DPE, + KMAC, + LC_CTRL, + MBX, + OTBN, + OTP_CTRL, + OTP_MACRO, + PINMUX, + PWRMGR, + RACL_CTRL, + ROM_CTRL, + RSTMGR, + RV_PLIC, + SOC_DBG_CTRL, + SOC_PROXY, + SPI_DEVICE, + SPI_HOST, + SRAM_CTRL, + UART, +] diff --git a/hw/top_darjeeling_no_ibex/data/autogen/top_darjeeling_no_ibex.gen.hjson b/hw/top_darjeeling_no_ibex/data/autogen/top_darjeeling_no_ibex.gen.hjson new file mode 100644 index 00000000000..a9a17be7a8a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/autogen/top_darjeeling_no_ibex.gen.hjson @@ -0,0 +1,28232 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed 1017106219537032642877583828875051302543807092889754935647094601236425074047 +{ + name: darjeeling_no_ibex + type: top + rnd_cnst_seed: 1017106219537032642877583828875051302543807092889754935647094601236425074047 + datawidth: "32" + racl_config: racl/racl.hjson + power: + { + domains: + [ + Aon + "0" + ] + default: "0" + wait_for_external_reset: true + halt_ibex_via_rom_ctrl: true + } + unmanaged_clocks: {} + clocks: + { + hier_paths: + { + top: clkmgr_aon_clocks. + ext: "" + lpg: clkmgr_aon_cg_en. + } + srcs: + [ + { + name: main + aon: no + freq: "1000000000" + ref: false + } + { + name: io + aon: no + freq: "1000000000" + ref: false + } + { + name: aon + aon: yes + freq: "62500000" + ref: true + } + ] + derived_srcs: + [ + { + name: io_div2 + aon: no + freq: "500000000" + ref: false + div: "2" + src: io + } + { + name: io_div4 + aon: no + freq: "250000000" + ref: false + div: "4" + src: io + } + ] + groups: + [ + { + name: ast + src: ext + sw_cg: no + unique: no + clocks: + { + clk_main_i: main + clk_io_i: io + clk_aon_i: aon + } + } + { + name: powerup + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_powerup: io_div4 + clk_aon_powerup: aon + clk_main_powerup: main + clk_io_powerup: io + clk_io_div2_powerup: io_div2 + } + } + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_infra: io_div4 + clk_main_infra: main + clk_aon_infra: aon + } + } + { + name: secure + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_secure: io_div4 + clk_main_secure: main + } + } + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + } + } + { + name: timers + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_timers: io_div4 + clk_aon_timers: aon + } + } + ] + } + resets: + { + hier_paths: + { + top: rstmgr_aon_resets. + ext: "" + lpg: rstmgr_aon_rst_en. + } + nodes: + [ + { + name: por_aon + gen: false + type: top + domains: + [ + "0" + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_aon_n + clock: aon + } + { + name: lc_src + gen: false + type: int + domains: [] + shadowed: false + sw: false + path: "" + clock: io_div4 + } + { + name: sys_src + gen: false + type: int + domains: [] + shadowed: false + sw: false + path: "" + clock: io_div4 + } + { + name: por + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_n + parent: por_aon + clock: main + } + { + name: por_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_n + parent: por_aon + clock: io + } + { + name: por_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div2_n + parent: por_aon + clock: io_div2 + } + { + name: por_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div4_n + parent: por_aon + clock: io_div4 + } + { + name: lc + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_n + parent: lc_src + clock: main + } + { + name: lc_aon + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_aon_n + parent: lc_src + clock: aon + } + { + name: lc_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_n + parent: lc_src + clock: io + } + { + name: lc_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_div2_n + parent: lc_src + clock: io_div2 + } + { + name: lc_io_div4 + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_io_div4_n + parent: lc_src + clock: io_div4 + } + { + name: sys + gen: true + type: top + domains: [] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_n + parent: sys_src + clock: main + } + { + name: sys_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_io_div4_n + parent: sys_src + clock: io_div4 + } + { + name: spi_device + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_device_n + parent: lc_src + clock: io_div4 + } + { + name: spi_host0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_host0_n + parent: lc_src + clock: io_div4 + } + { + name: i2c0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_i2c0_n + parent: lc_src + clock: io_div4 + } + ] + } + reset_requests: + { + int: + [ + { + name: MainPwr + desc: main power glitch reset request + module: pwrmgr_aon + } + { + name: Esc + desc: escalation reset request + module: alert_handler + } + ] + peripheral: + [ + { + name: aon_timer_rst_req + width: "1" + module: aon_timer_aon + desc: Watchdog reset request. + } + { + name: rst_req_external + width: "1" + module: soc_proxy + desc: External reset request + } + ] + } + num_cores: "1" + interrupts: + { + default_plic: rv_plic + } + addr_spaces: + [ + { + name: hart + desc: The main address space, shared between the CPU and DM + subspaces: + [ + { + name: mmio + desc: + ''' + MMIO region excludes any memory that is separate from the module configuration + space, i.e. ROM, main SRAM, and mbx SRAM are excluded but retention SRAM or + spi_device are included. + ''' + nodes: + [ + uart0 + gpio + spi_device + i2c0 + otp_ctrl + lc_ctrl.regs + alert_handler + spi_host0 + pwrmgr_aon + rstmgr_aon + clkmgr_aon + pinmux_aon + aon_timer_aon + ast + soc_proxy.core + soc_dbg_ctrl.core + sram_ctrl_ret_aon + aes + hmac + otbn + keymgr_dpe + csrng + entropy_src + edn0 + edn1 + sram_ctrl_main.regs + sram_ctrl_mbox.regs + dma + ] + } + ] + } + { + name: soc_mbx + desc: SoC address space for mailbox access + } + { + name: soc_dbg + desc: SoC address space for debug module interfaces + } + ] + module: + [ + { + name: uart0 + type: uart + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: uart0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: uart0_lsio_trigger + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: uart0 + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: uart0 + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: uart0 + default: "" + end_idx: -1 + top_signame: uart0_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30010000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: gpio + type: gpio + template_type: gpio + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + } + param_decl: + { + GpioAsHwStrapsEn: "1" + GpioAsyncOn: "1" + } + ipgen_param: + { + num_inp_period_counters: 8 + } + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + } + memory: {} + param_list: + [ + { + name: GpioAsyncOn + desc: Instantiates 2-flop synchronizers on all GPIO inputs if set to 1. + type: bit + default: "1" + local: "false" + expose: "true" + name_top: GpioGpioAsyncOn + } + { + name: GpioAsHwStrapsEn + desc: Enable HW straps sampling logic for GPIO inputs at initial cold boot + type: bit + default: "1" + local: "false" + expose: "true" + name_top: GpioGpioAsHwStrapsEn + } + ] + inter_signal_list: + [ + { + name: strap_en + desc: + ''' + The strap enable signal tells gpio to take a snapshot of the input pins. + The behaviour of this signal after that event will have no effect. + ''' + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: gpio + package: "" + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: sampled_straps + desc: This vector contains the sampled strap values. + struct: gpio_straps + package: gpio_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: gpio + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: gpio + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: gpio + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: gpio + default: "" + end_idx: -1 + top_signame: gpio_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30000000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: spi_device + type: spi_device + clock_srcs: + { + clk_i: io_div4 + scan_clk_i: io_div2 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: spi_device + domain: "0" + } + } + param_decl: + { + SramType: spi_device_pkg::SramType1r1w + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + scan_clk_i: clkmgr_aon_clocks.clk_io_div2_peri + } + memory: {} + param_list: + [ + { + name: SramType + desc: Sram Entries. Word size is 32bit width. + type: spi_device_pkg::sram_type_e + default: spi_device_pkg::SramType1r1w + local: "false" + expose: "true" + name_top: SpiDeviceSramType + } + ] + inter_signal_list: + [ + { + name: ram_cfg_sys2spi + struct: ram_2p_cfg + package: prim_ram_2p_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_device + default: "" + external: true + top_signame: spi_device_ram_2p_cfg_sys2spi + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_sys2spi + struct: ram_2p_cfg_rsp + package: prim_ram_2p_pkg + type: uni + act: req + width: 1 + inst_name: spi_device + default: "" + external: true + top_signame: spi_device_ram_2p_cfg_rsp_sys2spi + conn_type: false + index: -1 + } + { + name: ram_cfg_spi2sys + struct: ram_2p_cfg + package: prim_ram_2p_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_device + default: "" + external: true + top_signame: spi_device_ram_2p_cfg_spi2sys + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_spi2sys + struct: ram_2p_cfg_rsp + package: prim_ram_2p_pkg + type: uni + act: req + width: 1 + inst_name: spi_device + default: "" + external: true + top_signame: spi_device_ram_2p_cfg_rsp_spi2sys + conn_type: false + index: -1 + } + { + name: passthrough + struct: passthrough + package: spi_device_pkg + type: req_rsp + act: req + width: 1 + inst_name: spi_device + default: "" + end_idx: -1 + top_signame: spi_device_passthrough + index: -1 + } + { + name: mbist_en + struct: logic + type: uni + act: rcv + width: 1 + inst_name: spi_device + index: -1 + } + { + name: sck_monitor + struct: logic + type: uni + act: req + width: 1 + inst_name: spi_device + default: "" + package: "" + external: true + top_signame: sck_monitor + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_device + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: spi_device + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_device + default: "" + end_idx: -1 + top_signame: spi_device_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30310000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: i2c0 + type: i2c + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: i2c0 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + } + param_decl: {} + memory: {} + param_list: + [ + { + name: InputDelayCycles + desc: + ''' + Maximum number of cycles of propagation delay between a change on the cio_scl_en_o or cio_sda_en_o pins and sensing the new values on the corresponding input pins, not including the rise/fall times. + For the purposes of this calculation, an input delay of 0 cycles means an output pin changing at the beginning of clock edge N will be sampled and observed on the input pins at clock edge N+1. + ''' + type: int + default: "0" + local: "false" + expose: "true" + name_top: I2c0InputDelayCycles + } + ] + inter_signal_list: + [ + { + name: ram_cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + default: "" + external: true + top_signame: i2c_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: i2c0 + default: "" + external: true + top_signame: i2c_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: i2c0_lsio_trigger + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: i2c0 + default: "" + end_idx: -1 + top_signame: i2c0_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30080000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: otp_ctrl + type: otp_ctrl + template_type: otp_ctrl + clock_srcs: + { + clk_i: io_div4 + clk_edn_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x30130000 + } + } + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + } + param_decl: {} + memory: {} + param_list: + [ + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: otp_ctrl_top_specific_pkg::lfsr_seed_t + randcount: 40 + randtype: data + name_top: RndCnstOtpCtrlLfsrSeed + default: 0xcda9a5fceb + randwidth: 40 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: otp_ctrl_top_specific_pkg::lfsr_perm_t + randcount: 40 + randtype: perm + name_top: RndCnstOtpCtrlLfsrPerm + default: 0x5ca7514df48895654290c14125e01884e99c12364f2d40c719b8903676a0 + randwidth: 240 + } + { + name: RndCnstScrmblKeyInit + desc: Compile-time random permutation for scrambling key/nonce register reset value + type: otp_ctrl_top_specific_pkg::scrmbl_key_init_t + randcount: 256 + randtype: data + name_top: RndCnstOtpCtrlScrmblKeyInit + default: 0x58fa9063ce216c0b412615d73f476529a96a1a8aca4b0bdcbe6b240c31095162 + randwidth: 256 + } + ] + inter_signal_list: + [ + { + name: edn + desc: Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation. + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otp_ctrl + default: "" + top_signame: edn0_edn + index: 1 + } + { + name: pwr_otp + desc: Initialization request/acknowledge from/to power manager. + struct: pwr_otp + package: pwrmgr_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: pwrmgr_aon_pwr_otp + index: -1 + } + { + name: lc_otp_program + desc: Life cycle state transition interface. + struct: lc_otp_program + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_otp_program + index: -1 + } + { + name: otp_lc_data + desc: + ''' + Life cycle state output holding the current life cycle state, + the value of the transition counter and the tokens needed for life cycle transitions. + ''' + struct: otp_lc_data + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: broadcast + top_signame: otp_ctrl_otp_lc_data + index: -1 + } + { + name: lc_escalate_en + desc: + ''' + Life cycle escalation enable coming from life cycle controller. + This signal moves all FSMs within OTP into the error state. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + desc: + ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + desc: + ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the OWNER_SEED. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_seed_hw_rd_en + desc: + ''' + Seed read enable coming from life cycle controller. + This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_check_byp_en + desc: + ''' + Life cycle partition check bypass signal. + This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: otp_keymgr_key + desc: Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + struct: otp_keymgr_key + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: broadcast + top_signame: otp_ctrl_otp_keymgr_key + index: -1 + } + { + name: sram_otp_key + desc: Array with key derivation interfaces for SRAM scrambling devices. + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 4 + default: "'0" + inst_name: otp_ctrl + end_idx: 3 + top_type: partial-one-to-N + top_signame: otp_ctrl_sram_otp_key + index: -1 + } + { + name: otbn_otp_key + desc: Key derivation interface for OTBN scrambling devices. + struct: otbn_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_signame: otp_ctrl_otbn_otp_key + index: -1 + } + { + name: otp_broadcast + desc: Output of the HW partitions with breakout data types. + struct: otp_broadcast + package: otp_ctrl_part_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: otp_ctrl_otp_broadcast + index: -1 + } + { + name: otp_macro + desc: Data interface for the OTP macro. + struct: otp_ctrl_macro + package: otp_ctrl_macro_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_signame: otp_ctrl_otp_macro + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otp_ctrl + default: "" + end_idx: -1 + top_signame: otp_ctrl_core_tl + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: otp_macro + type: otp_macro + clock_srcs: + { + clk_i: io_div4 + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + } + base_addrs: + { + prim: + { + hart: 0x30140000 + } + } + param_decl: + { + Width: otp_ctrl_macro_pkg::OtpWidth + Depth: otp_ctrl_macro_pkg::OtpDepth + SizeWidth: otp_ctrl_macro_pkg::OtpSizeWidth + VendorTestOffset: otp_ctrl_reg_pkg::VendorTestOffset + VendorTestSize: otp_ctrl_reg_pkg::VendorTestSize + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_secure + } + memory: {} + param_list: + [ + { + name: Width + desc: Size of storage words in bits + type: int + default: otp_ctrl_macro_pkg::OtpWidth + local: "false" + expose: "false" + name_top: OtpMacroWidth + } + { + name: Depth + desc: Number of words + type: int + default: otp_ctrl_macro_pkg::OtpDepth + local: "false" + expose: "false" + name_top: OtpMacroDepth + } + { + name: SizeWidth + desc: Number of words transferred per access + type: int + default: otp_ctrl_macro_pkg::OtpSizeWidth + local: "false" + expose: "false" + name_top: OtpMacroSizeWidth + } + { + name: MemInitFile + desc: "" + type: "" + default: '''""''' + local: "false" + expose: "true" + name_top: OtpMacroMemInitFile + } + { + name: VendorTestOffset + desc: "" + type: int + default: otp_ctrl_reg_pkg::VendorTestOffset + local: "false" + expose: "false" + name_top: OtpMacroVendorTestOffset + } + { + name: VendorTestSize + desc: "" + type: int + default: otp_ctrl_reg_pkg::VendorTestSize + local: "false" + expose: "false" + name_top: OtpMacroVendorTestSize + } + ] + inter_signal_list: + [ + { + name: obs_ctrl + desc: AST observability control signals. + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: otp_macro + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: otp_obs + desc: AST observability bus. + struct: logic + type: uni + act: req + width: 8 + inst_name: otp_macro + default: "" + package: "" + external: true + top_signame: otp_obs + conn_type: false + index: -1 + } + { + name: pwr_seq + desc: Power sequencing signals to AST (VDD domain). + struct: pwr_seq + package: otp_macro_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_macro + external: true + top_signame: otp_macro_pwr_seq + conn_type: false + index: -1 + } + { + name: pwr_seq_h + desc: Power sequencing signals coming from AST (VCC domain). + struct: pwr_seq + package: otp_macro_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: otp_macro + external: true + top_signame: otp_macro_pwr_seq_h + conn_type: false + index: -1 + } + { + name: ext_voltage_h + struct: "" + type: io + act: none + width: 1 + default: "'0" + inst_name: otp_macro + package: "" + external: true + top_signame: otp_ext_voltage_h + conn_type: false + index: -1 + } + { + name: lc_dft_en + desc: + ''' + Test enable qualifier coming from life cycle controller. + This signals enables the TL-UL access port. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_macro + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: test + desc: Vendor test control signals from/to the life cycle TAP. + struct: otp_test + package: otp_macro_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_macro + top_signame: lc_ctrl_lc_otp_vendor_test + index: -1 + } + { + name: otp + desc: Data interface for the OTP macro. + struct: otp_ctrl_macro + package: otp_ctrl_macro_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_macro + top_signame: otp_ctrl_otp_macro + index: -1 + } + { + name: cfg + struct: otp_cfg + package: otp_macro_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: otp_macro + external: true + top_signame: otp_cfg + conn_type: false + index: -1 + } + { + name: cfg_rsp + struct: otp_cfg_rsp + package: otp_macro_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_macro + external: true + top_signame: otp_cfg_rsp + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: otp_macro + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: otp_macro + index: -1 + } + { + name: prim_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otp_macro + default: "" + end_idx: -1 + top_signame: otp_macro_prim_tl + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: lc_ctrl + type: lc_ctrl + clock_srcs: + { + clk_i: io_div4 + clk_kmac_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_kmac_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + regs: + { + hart: 0x30150000 + } + dmi: + { + soc_dbg: 0x3000 + } + } + param_decl: + { + SecVolatileRawUnlockEn: top_pkg::SecVolatileRawUnlockEn + SiliconCreatorId: 16'h 4002 + ProductId: 16'h 4000 + RevisionId: 8'h 01 + UseDmiInterface: "1" + NumRmaAckSigs: "1" + EscNumSeverities: AlertHandlerEscNumSeverities + EscPingCountWidth: AlertHandlerEscPingCountWidth + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_kmac_i: clkmgr_aon_clocks.clk_main_secure + } + memory: {} + param_list: + [ + { + name: SecVolatileRawUnlockEn + desc: + ''' + Disable (0) or enable (1) volatile RAW UNLOCK capability. + If enabled, it is possible to perform a volatile RAW -> TEST_UNLOCKED0 transition + without programming the OTP. This is a useful fallback mode in case the OTP is + not working correctly. + + IMPORTANT NOTE: This should only be used in test chips. The parameter must be set + to 0 in production tapeouts since this weakens the security posture of the RAW + UNLOCK mechanism. + ''' + type: bit + default: top_pkg::SecVolatileRawUnlockEn + local: "false" + expose: "true" + name_top: SecLcCtrlVolatileRawUnlockEn + } + { + name: UseDmiInterface + desc: When 1, a TLUL-based DMI interface is used. When 0, a JTAG TAP is used. + type: bit + default: "1" + local: "false" + expose: "true" + name_top: LcCtrlUseDmiInterface + } + { + name: RndCnstLcKeymgrDivInvalid + desc: Diversification value used for all invalid life cycle states. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivInvalid + default: 0xe41bf99b2bc41e9edbb4685f7eb27eb3 + randwidth: 128 + } + { + name: RndCnstLcKeymgrDivTestUnlocked + desc: Diversification value used for the TEST_UNLOCKED* life cycle states. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivTestUnlocked + default: 0xb35f352752e34f64ce978305bfc3481a + randwidth: 128 + } + { + name: RndCnstLcKeymgrDivDev + desc: Diversification value used for the DEV life cycle state. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivDev + default: 0x2162ea2792b7508f1eab067af954dda5 + randwidth: 128 + } + { + name: RndCnstLcKeymgrDivProduction + desc: Diversification value used for the PROD/PROD_END life cycle states. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivProduction + default: 0x491439a9dde6320801fdcf25a4fba528 + randwidth: 128 + } + { + name: RndCnstLcKeymgrDivRma + desc: Diversification value used for the RMA life cycle state. + type: lc_ctrl_pkg::lc_keymgr_div_t + randcount: 128 + randtype: data + name_top: RndCnstLcCtrlLcKeymgrDivRma + default: 0x399117069e77c887f53dda6fb4ef8758 + randwidth: 128 + } + { + name: RndCnstInvalidTokens + desc: Compile-time random bits used for invalid tokens in the token mux + type: lc_ctrl_pkg::lc_token_mux_t + randcount: 1024 + randtype: data + name_top: RndCnstLcCtrlInvalidTokens + default: 0xb99027b6aa7468bc0bd8d70368e7cfb11a99675b146240619335a9e2d123834d18744778be5e63c087e36838b56b1a45f6fd312f5353fa7b2ce9fc83ddaf1dd8c5a42e2ad24fa02221b6ff5aad7a9c09d5d9fdd1cfcf512835c0cfae2ed0c69fa488685cea9bc1c89bfb7399aef5c6eb5d6e4e23416a0aa6d7ac7ec9c3304470 + randwidth: 1024 + } + { + name: SiliconCreatorId + desc: Chip generation number. + type: logic [15:0] + default: 16'h 4002 + local: "false" + expose: "true" + name_top: LcCtrlSiliconCreatorId + } + { + name: ProductId + desc: Chip revision number. + type: logic [15:0] + default: 16'h 4000 + local: "false" + expose: "true" + name_top: LcCtrlProductId + } + { + name: RevisionId + desc: Chip revision number. + type: logic [7:0] + default: 8'h 01 + local: "false" + expose: "true" + name_top: LcCtrlRevisionId + } + { + name: IdcodeValue + desc: JTAG ID code. + type: logic [31:0] + default: 32'h00000001 + local: "false" + expose: "true" + name_top: LcCtrlIdcodeValue + } + { + name: NumRmaAckSigs + desc: Number of Flash RMA wiping response signals + type: int + default: "1" + local: "true" + expose: "true" + name_top: LcCtrlNumRmaAckSigs + } + { + name: EscNumSeverities + desc: Number of escalation severities + type: int + default: AlertHandlerEscNumSeverities + local: "false" + expose: "false" + name_top: LcCtrlEscNumSeverities + } + { + name: EscPingCountWidth + desc: Width of ping count for the escalation receiver + type: int + default: AlertHandlerEscPingCountWidth + local: "false" + expose: "false" + name_top: LcCtrlEscPingCountWidth + } + ] + inter_signal_list: + [ + { + name: jtag + struct: jtag + package: jtag_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + index: -1 + } + { + name: esc_scrap_state0_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_tx + index: 0 + } + { + name: esc_scrap_state0_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_rx + index: 0 + } + { + name: esc_scrap_state1_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_tx + index: 1 + } + { + name: esc_scrap_state1_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_rx + index: 1 + } + { + name: pwr_lc + struct: pwr_lc + package: lc_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: pwrmgr_aon_pwr_lc + index: -1 + } + { + name: lc_otp_vendor_test + struct: otp_test + package: otp_macro_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_signame: lc_ctrl_lc_otp_vendor_test + index: -1 + } + { + name: otp_lc_data + struct: otp_lc_data + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT + inst_name: lc_ctrl + top_signame: otp_ctrl_otp_lc_data + index: -1 + } + { + name: lc_otp_program + struct: lc_otp_program + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_signame: lc_ctrl_lc_otp_program + index: -1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: kmac_app + index: 1 + } + { + name: lc_raw_test_rma + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_raw_test_rma + index: -1 + } + { + name: lc_dft_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_hw_debug_clr + desc: + ''' + Clear HW debug functionality. + This signal is On when `lc_hw_debug_en` turns Off outside a reset of `lc_ctrl`. + Flops storing the value of `lc_hw_debug_en` (see below) must be cleared when this signal is On. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_hw_debug_en + desc: + ''' + Enable HW debug functionality; see `HW_DEBUG_EN` in the Theory of Operation doc for details. + + This signal is Off while lc_ctrl is in reset. + In order to prevent a JTAG disconnect during non-debug-module (NDM) reset, this signal should be flopped outside the NDM reset domain. + Such a flop must be cleared when `lc_hw_debug_clr` is On; see above. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_cpu_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_keymgr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_keymgr_en + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_clk_byp_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_clk_byp_req + index: -1 + } + { + name: lc_clk_byp_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_clk_byp_ack + index: -1 + } + { + name: lc_flash_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_flash_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 2 + default: lc_ctrl_pkg::On + inst_name: lc_ctrl + top_signame: otbn_lc_rma_ack + index: -1 + } + { + name: lc_flash_rma_seed + struct: lc_flash_rma_seed + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + index: -1 + } + { + name: lc_check_byp_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_iso_part_sw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_iso_part_sw_wr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_seed_hw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_keymgr_div + struct: lc_keymgr_div + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_keymgr_div + index: -1 + } + { + name: otp_device_id + struct: otp_device_id + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: lc_ctrl_otp_device_id + index: -1 + } + { + name: otp_manuf_state + struct: otp_manuf_state + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: lc_ctrl_otp_manuf_state + index: -1 + } + { + name: hw_rev + struct: lc_hw_rev + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + index: -1 + } + { + name: strap_en_override + desc: + ''' + This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. + The signal stays at 1 until reset. + Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. + Otherwise this signal is tied off to 0. + ''' + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: lc_ctrl + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + end_idx: -1 + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: dmi_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + end_idx: -1 + top_signame: lc_ctrl_dmi_tl + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: alert_handler + type: alert_handler + template_type: alert_handler + clock_srcs: + { + clk_i: io_div4 + clk_edn_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + param_decl: + { + EscNumSeverities: "4" + EscPingCountWidth: "16" + } + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + } + memory: {} + param_list: + [ + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: alert_handler_pkg::lfsr_seed_t + randcount: 32 + randtype: data + name_top: RndCnstAlertHandlerLfsrSeed + default: 0xfbe505f9 + randwidth: 32 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: alert_handler_pkg::lfsr_perm_t + randcount: 32 + randtype: perm + name_top: RndCnstAlertHandlerLfsrPerm + default: 0x7ea97f41618db8619eaaee1c8209a5da7f3c824c + randwidth: 160 + } + { + name: EscNumSeverities + desc: Number of escalation severities as regular parameter + type: int + default: "4" + local: "false" + expose: "true" + name_top: AlertHandlerEscNumSeverities + } + { + name: EscPingCountWidth + desc: Width of ping counter as regular parameter + type: int + default: "16" + local: "false" + expose: "true" + name_top: AlertHandlerEscPingCountWidth + } + ] + inter_signal_list: + [ + { + name: crashdump + struct: alert_crashdump + package: alert_handler_pkg + type: uni + act: req + width: 1 + inst_name: alert_handler + default: "" + end_idx: -1 + top_type: broadcast + top_signame: alert_handler_crashdump + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: alert_handler + default: "" + top_signame: edn0_edn + index: 3 + } + { + name: esc_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: rcv + width: 4 + inst_name: alert_handler + default: "" + end_idx: 3 + top_type: partial-one-to-N + top_signame: alert_handler_esc_rx + index: -1 + } + { + name: esc_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: req + width: 4 + inst_name: alert_handler + default: "" + end_idx: 3 + top_type: partial-one-to-N + top_signame: alert_handler_esc_tx + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: alert_handler + default: "" + end_idx: -1 + top_signame: alert_handler_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30160000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: spi_host0 + type: spi_host + clock_srcs: + { + clk_i: io_div4 + } + clock_group: peri + reset_connections: + { + rst_ni: + { + name: spi_host0 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_peri + } + param_decl: {} + memory: {} + param_list: + [ + { + name: NumCS + desc: The number of active-low chip select (cs_n) lines to create. + type: int + default: "1" + local: "true" + expose: "true" + name_top: SpiHost0NumCS + } + ] + inter_signal_list: + [ + { + name: passthrough + struct: passthrough + package: spi_device_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_host0 + default: "" + top_signame: spi_device_passthrough + index: -1 + } + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: spi_host0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: spi_host0_lsio_trigger + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_host0 + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: spi_host0 + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_host0 + default: "" + end_idx: -1 + top_signame: spi_host0_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30300000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: pwrmgr_aon + type: pwrmgr + template_type: pwrmgr + clock_group: powerup + clock_srcs: + { + clk_i: io_div4 + clk_slow_i: aon + clk_lc_i: io_div4 + clk_esc_i: + { + clock: io_div4 + group: secure + } + } + reset_connections: + { + rst_ni: + { + name: por_io_div4 + domain: Aon + } + rst_main_ni: + { + name: por_aon + domain: "0" + } + rst_lc_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_esc_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_slow_ni: + { + name: por_aon + domain: Aon + } + } + domain: + [ + Aon + "0" + ] + param_decl: + { + EscNumSeverities: AlertHandlerEscNumSeverities + EscPingCountWidth: AlertHandlerEscPingCountWidth + } + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_slow_i: clkmgr_aon_clocks.clk_aon_powerup + clk_lc_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_esc_i: clkmgr_aon_clocks.clk_io_div4_secure + } + memory: {} + param_list: + [ + { + name: EscNumSeverities + desc: Number of escalation severities + type: int + default: AlertHandlerEscNumSeverities + local: "false" + expose: "false" + name_top: PwrmgrAonEscNumSeverities + } + { + name: EscPingCountWidth + desc: Width of ping count for the escalation receiver + type: int + default: AlertHandlerEscPingCountWidth + local: "false" + expose: "false" + name_top: PwrmgrAonEscPingCountWidth + } + ] + inter_signal_list: + [ + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_boot_status + index: -1 + external: true + conn_type: true + } + { + name: pwr_ast + struct: pwr_ast + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + external: true + top_signame: pwrmgr_ast + conn_type: false + index: -1 + } + { + name: pwr_rst + struct: pwr_rst + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_rst + index: -1 + } + { + name: pwr_clk + struct: pwr_clk + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_clk + index: -1 + } + { + name: pwr_otp + struct: pwr_otp + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_otp + index: -1 + } + { + name: pwr_lc + struct: pwr_lc + package: lc_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_lc + index: -1 + } + { + name: pwr_flash + struct: pwr_flash + package: pwrmgr_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: esc_rst_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: alert_handler_esc_tx + index: 2 + } + { + name: esc_rst_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: alert_handler_esc_rx + index: 2 + } + { + name: pwr_cpu + struct: cpu_pwrmgr + package: rv_core_ibex_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: wakeups + struct: logic + type: uni + act: rcv + width: 4 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_wakeups + index: -1 + } + { + name: rstreqs + struct: logic + type: uni + act: rcv + width: 2 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_rstreqs + index: -1 + } + { + name: ndmreset_req + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: strap + struct: logic + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: low_power + struct: logic + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: rom_ctrl + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: rcv + width: 3 + default: rom_ctrl_pkg::PWRMGR_DATA_DEFAULT + inst_name: pwrmgr_aon + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_rom_ctrl + index: -1 + } + { + name: fetch_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: lc_dft_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: sw_rst_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: rstmgr_aon_sw_rst_req + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30400000 + } + } + generate_dif: true + } + { + name: rstmgr_aon + type: rstmgr + template_type: rstmgr + clock_srcs: + { + clk_i: + { + clock: io_div4 + group: powerup + } + clk_por_i: io_div4 + clk_aon_i: aon + clk_main_i: main + clk_io_i: io + clk_io_div2_i: io_div2 + clk_io_div4_i: io_div4 + } + clock_group: powerup + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_por_ni: + { + name: por_io_div4 + domain: Aon + } + } + domain: + [ + Aon + "0" + ] + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_por_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup + clk_main_i: clkmgr_aon_clocks.clk_main_powerup + clk_io_i: clkmgr_aon_clocks.clk_io_powerup + clk_io_div2_i: clkmgr_aon_clocks.clk_io_div2_powerup + clk_io_div4_i: clkmgr_aon_clocks.clk_io_div4_powerup + } + param_decl: {} + memory: {} + param_list: + [ + { + name: SecCheck + desc: + ''' + When 1, enable rstmgr reset consistency checks. + When 0, there are no consistency checks. + ''' + type: bit + default: 1'b1 + local: "false" + expose: "true" + name_top: SecRstmgrAonCheck + } + { + name: SecMaxSyncDelay + desc: The maximum synchronization delay for parent / child reset checks. + type: int + default: "2" + local: "false" + expose: "true" + name_top: SecRstmgrAonMaxSyncDelay + } + ] + inter_signal_list: + [ + { + name: por_n + desc: + ''' + Root power on reset signals from ast. + There is one root reset signal for each core power domain. + ''' + struct: logic + type: uni + act: rcv + width: 2 + inst_name: rstmgr_aon + default: "" + package: "" + external: true + top_signame: por_n + conn_type: false + index: -1 + } + { + name: pwr + desc: + ''' + Reset request signals from power manager. + Power manager can request for specific domains of the lc/sys reset tree to assert. + ''' + struct: pwr_rst + type: req_rsp + act: rsp + width: 1 + inst_name: rstmgr_aon + default: "" + package: pwrmgr_pkg + top_signame: pwrmgr_aon_pwr_rst + index: -1 + } + { + name: resets + desc: Leaf resets fed to the system. + struct: rstmgr_out + package: rstmgr_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rstmgr_aon_resets + index: -1 + } + { + name: rst_en + desc: Low-power-group outputs used by alert handler. + struct: rstmgr_rst_en + package: rstmgr_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rstmgr_aon_rst_en + index: -1 + } + { + name: alert_dump + desc: Alert handler crash dump information. + struct: alert_crashdump + package: alert_handler_pkg + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: alert_handler_crashdump + index: -1 + } + { + name: cpu_dump + desc: Main processing element crash dump information. + struct: cpu_crash_dump + package: rv_core_ibex_pkg + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + index: -1 + } + { + name: sw_rst_req + desc: Software requested system reset to pwrmgr. + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: rstmgr_aon_sw_rst_req + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rstmgr_aon + default: "" + end_idx: -1 + top_signame: rstmgr_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30410000 + } + } + generate_dif: true + } + { + name: clkmgr_aon + type: clkmgr + template_type: clkmgr + clock_srcs: + { + clk_i: io_div4 + clk_main_i: + { + group: ast + clock: main + } + clk_io_i: + { + group: ast + clock: io + } + clk_aon_i: + { + group: ast + clock: aon + } + } + clock_group: powerup + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_aon_ni: + { + name: lc_aon + domain: Aon + } + rst_io_ni: + { + name: lc_io + domain: Aon + } + rst_io_div2_ni: + { + name: lc_io_div2 + domain: Aon + } + rst_io_div4_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_main_ni: + { + name: lc + domain: Aon + } + rst_root_ni: + { + name: por_io_div4 + domain: Aon + } + rst_root_io_ni: + { + name: por_io + domain: Aon + } + rst_root_io_div2_ni: + { + name: por_io_div2 + domain: Aon + } + rst_root_io_div4_ni: + { + name: por_io_div4 + domain: Aon + } + rst_root_main_ni: + { + name: por + domain: Aon + } + } + domain: + [ + Aon + ] + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_main_i: clk_main_i + clk_io_i: clk_io_i + clk_aon_i: clk_aon_i + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: clocks + struct: clkmgr_out + package: clkmgr_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: clkmgr_aon_clocks + index: -1 + } + { + name: cg_en + struct: clkmgr_cg_en + package: clkmgr_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: clkmgr_aon_cg_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: io_clk_byp_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: io_clk_byp_req + conn_type: false + index: -1 + } + { + name: io_clk_byp_ack + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: io_clk_byp_ack + conn_type: false + index: -1 + } + { + name: all_clk_byp_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: all_clk_byp_req + conn_type: false + index: -1 + } + { + name: all_clk_byp_ack + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: all_clk_byp_ack + conn_type: false + index: -1 + } + { + name: hi_speed_sel + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: hi_speed_sel + conn_type: false + index: -1 + } + { + name: div_step_down_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: div_step_down_req + conn_type: false + index: -1 + } + { + name: lc_clk_byp_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_clk_byp_req + index: -1 + } + { + name: lc_clk_byp_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_clk_byp_ack + index: -1 + } + { + name: jitter_en + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: clk_main_jitter_en + conn_type: false + index: -1 + } + { + name: pwr + struct: pwr_clk + type: req_rsp + act: rsp + width: 1 + inst_name: clkmgr_aon + default: "" + package: pwrmgr_pkg + top_signame: pwrmgr_aon_pwr_clk + index: -1 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 4 + inst_name: clkmgr_aon + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: clkmgr_aon_idle + index: -1 + } + { + name: calib_rdy + desc: Indicates clocks are calibrated and frequencies accurate + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi4True + inst_name: clkmgr_aon + external: true + top_signame: calib_rdy + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: clkmgr_aon + default: "" + end_idx: -1 + top_signame: clkmgr_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30420000 + } + } + generate_dif: true + } + { + name: pinmux_aon + type: pinmux + template_type: pinmux + clock_srcs: + { + clk_i: io_div4 + clk_aon_i: aon + } + clock_group: powerup + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_aon_ni: + { + name: lc_aon + domain: Aon + } + rst_sys_ni: + { + name: sys_io_div4 + domain: Aon + } + } + domain: + [ + Aon + ] + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_powerup + clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup + } + param_decl: {} + memory: {} + param_list: + [ + { + name: TargetCfg + desc: Target specific pinmux configuration. + type: pinmux_pkg::target_cfg_t + default: pinmux_pkg::DefaultTargetCfg + local: "false" + expose: "true" + name_top: PinmuxAonTargetCfg + } + ] + inter_signal_list: + [ + { + name: sleep_en + desc: Level signal that is asserted when the power manager enters sleep. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: pin_wkup_req + desc: Wakeup request from wakeup detectors, to the power manager, running on the AON clock. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 0 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: pinmux_aon + default: "" + end_idx: -1 + top_signame: pinmux_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30460000 + } + } + generate_dif: true + } + { + name: aon_timer_aon + type: aon_timer + clock_srcs: + { + clk_i: io_div4 + clk_aon_i: aon + } + clock_group: timers + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_aon_ni: + { + name: lc_aon + domain: Aon + } + } + domain: + [ + Aon + ] + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_timers + clk_aon_i: clkmgr_aon_clocks.clk_aon_timers + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: nmi_wdog_timer_bark + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + index: -1 + } + { + name: wkup_req + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 1 + } + { + name: aon_timer_rst_req + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + top_signame: pwrmgr_aon_rstreqs + index: 0 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: aon_timer_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: sleep_mode + struct: logic + type: uni + act: rcv + width: 1 + inst_name: aon_timer_aon + default: "" + package: "" + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: aon_timer_aon + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: aon_timer_aon + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: aon_timer_aon + default: "" + end_idx: -1 + top_signame: aon_timer_aon_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30470000 + } + } + generate_dif: true + } + { + name: ast + type: ast + clock_srcs: + { + clk_ast_tlul_i: + { + clock: io_div4 + group: infra + } + clk_ast_adc_i: + { + clock: aon + group: peri + } + clk_ast_alert_i: + { + clock: io_div4 + group: secure + } + clk_ast_rng_i: + { + clock: main + group: secure + } + } + clock_group: secure + reset_connections: + { + rst_ast_tlul_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_ast_adc_ni: + { + name: lc_aon + domain: Aon + } + rst_ast_alert_ni: + { + name: lc_io_div4 + domain: "0" + } + rst_ast_rng_ni: + { + name: lc + domain: "0" + } + } + domain: + [ + Aon + "0" + ] + attr: reggen_only + clock_connections: + { + clk_ast_tlul_i: clkmgr_aon_clocks.clk_io_div4_infra + clk_ast_adc_i: clkmgr_aon_clocks.clk_aon_peri + clk_ast_alert_i: clkmgr_aon_clocks.clk_io_div4_secure + clk_ast_rng_i: clkmgr_aon_clocks.clk_main_secure + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: ast + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x30480000 + } + } + generate_dif: true + } + { + name: soc_proxy + type: soc_proxy + clock_srcs: + { + clk_i: main + clk_aon_i: aon + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_por_ni: + { + name: por_io_div4 + domain: Aon + } + } + domain: + [ + Aon + "0" + ] + base_addrs: + { + core: + { + hart: 0x22030000 + } + ctn: + { + hart: 0x40000000 + } + } + attr: reggen_top + memory: + { + ctn: + { + label: ctn + swaccess: rw + data_intg_passthru: "true" + exec: True + byte_write: True + size: 0x40000000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + clk_aon_i: clkmgr_aon_clocks.clk_aon_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: dma_tl_h2d + desc: TL-UL host port for the DMA to egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_type: broadcast + top_signame: soc_proxy_dma_tl_h2d + index: -1 + } + { + name: dma_tl_d2h + desc: TL-UL host port for the DMA to egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_type: broadcast + top_signame: soc_proxy_dma_tl_d2h + index: -1 + } + { + name: misc_tl_h2d + desc: TL-UL host port for the MISC to egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + external: true + top_signame: ctn_misc_tl_h2d + conn_type: false + index: -1 + } + { + name: misc_tl_d2h + desc: TL-UL host port for the MISC to egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + external: true + top_signame: ctn_misc_tl_d2h + conn_type: false + index: -1 + } + { + name: wkup_internal_req + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 2 + } + { + name: wkup_external_req + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 3 + } + { + name: rst_req_external + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_rstreqs + index: 1 + } + { + name: ctn_tl_h2d + desc: TL-UL host port for egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_type: broadcast + top_signame: soc_proxy_ctn_tl_h2d + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL host port for egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_type: broadcast + top_signame: soc_proxy_ctn_tl_d2h + index: -1 + } + { + name: i2c_lsio_trigger + desc: LSIO trigger signal from I2C + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: i2c0_lsio_trigger + index: -1 + } + { + name: spi_host_lsio_trigger + desc: LSIO trigger signal from SPI Host + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: spi_host0_lsio_trigger + index: -1 + } + { + name: uart_lsio_trigger + desc: LSIO trigger signal from UART + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: uart0_lsio_trigger + index: -1 + } + { + name: soc_lsio_trigger + desc: LSIO trigger signal from SoC, synchronous + struct: logic + type: uni + act: rcv + width: 8 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_lsio_trigger + conn_type: false + index: -1 + } + { + name: dma_lsio_trigger + desc: Collated synchronous LSIO trigger signals for DMA + struct: lsio_trigger + package: dma_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + top_signame: dma_lsio_trigger + index: -1 + } + { + name: soc_fatal_alert + desc: Differential fatal alert from SoC, synchronous + struct: soc_alert + package: soc_proxy_pkg + type: req_rsp + act: rsp + width: 24 + inst_name: soc_proxy + default: "" + external: true + top_signame: soc_fatal_alert + conn_type: false + index: -1 + } + { + name: soc_recov_alert + desc: Differential recoverable alert from SoC, synchronous + struct: soc_alert + package: soc_proxy_pkg + type: req_rsp + act: rsp + width: 4 + inst_name: soc_proxy + default: "" + external: true + top_signame: soc_recov_alert + conn_type: false + index: -1 + } + { + name: soc_wkup_async + desc: Wakeup request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_wkup_async + conn_type: false + index: -1 + } + { + name: soc_rst_req_async + desc: Reset request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_rst_req_async + conn_type: false + index: -1 + } + { + name: soc_intr_async + desc: Interrupt request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 32 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_intr_async + conn_type: false + index: -1 + } + { + name: soc_gpi_async + desc: GPI from SoC, async + struct: logic + type: uni + act: req + width: 16 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_gpi_async + conn_type: false + index: -1 + } + { + name: soc_gpo_async + desc: GPO from SoC, async + struct: logic + type: uni + act: rcv + width: 16 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_gpo_async + conn_type: false + index: -1 + } + { + name: integrator_id + desc: Integrator ID signal used in BAT + struct: logic + type: uni + act: rcv + width: 4 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: integrator_id + conn_type: false + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_proxy + index: -1 + } + { + name: ctn_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_signame: soc_proxy_ctn_tl + index: -1 + } + ] + generate_dif: true + } + { + name: sram_ctrl_ret_aon + type: sram_ctrl + clock_srcs: + { + clk_i: io_div4 + clk_otp_i: io_div4 + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: Aon + } + rst_otp_ni: + { + name: lc_io_div4 + domain: Aon + } + } + domain: + [ + Aon + ] + param_decl: + { + InstrExec: "0" + InstSize: 4096 + } + base_addrs: + { + regs: + { + hart: 0x30500000 + } + ram: + { + hart: 0x30600000 + } + } + memory: + { + ram: + { + label: ram_ret_aon + swaccess: rw + data_intg_passthru: "true" + exec: True + byte_write: True + size: 0x1000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_infra + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra + } + param_list: + [ + { + name: RndCnstSramKey + desc: Compile-time random reset value for SRAM scrambling key. + type: otp_ctrl_pkg::sram_key_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlRetAonSramKey + default: 0x246c4264f37ec198201794adda1b1692 + randwidth: 128 + } + { + name: RndCnstSramNonce + desc: Compile-time random reset value for SRAM scrambling nonce. + type: otp_ctrl_pkg::sram_nonce_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlRetAonSramNonce + default: 0x9df5e06a56aaded443259ffb5736dd68 + randwidth: 128 + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: sram_ctrl_pkg::lfsr_seed_t + randcount: 64 + randtype: data + name_top: RndCnstSramCtrlRetAonLfsrSeed + default: 0x1215b98e162dcc0 + randwidth: 64 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: sram_ctrl_pkg::lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstSramCtrlRetAonLfsrPerm + default: 0xe2ac3b983855bd0b2d0a56636d210a1c08895b161fd1effd93cf817063cdcae51382b5e86b7d45a5d236cf944b3ba327 + randwidth: 384 + } + { + name: MemSizeRam + desc: Memory size of the RAM (in bytes). + type: int + name_top: MemSizeSramCtrlRetAonRam + default: 4096 + } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: 4096 + local: "false" + expose: "true" + name_top: SramCtrlRetAonInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlRetAonNumRamInst + } + { + name: InstrExec + desc: Support execution from SRAM + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlRetAonInstrExec + } + { + name: NumPrinceRoundsHalf + desc: Number of PRINCE half rounds for the SRAM scrambling feature + type: int + default: "3" + local: "false" + expose: "true" + name_top: SramCtrlRetAonNumPrinceRoundsHalf + } + { + name: Outstanding + desc: Number of outstanding TLUL transactions + type: int + default: "2" + local: "true" + expose: "true" + name_top: SramCtrlRetAonOutstanding + } + { + name: EccCorrection + desc: Enable single-bit error correction and error logging + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlRetAonEccCorrection + } + ] + inter_signal_list: + [ + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 1 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } + default: "'0" + inst_name: sram_ctrl_ret_aon + external: true + top_signame: sram_ctrl_ret_aon_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } + default: "'0" + inst_name: sram_ctrl_ret_aon + external: true + top_signame: sram_ctrl_ret_aon_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_ret_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: sram_rerror + desc: SRAM read error indicating correctable and uncorrectable ECC errors. + struct: sram_error_t + package: sram_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + end_idx: -1 + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + end_idx: -1 + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + ] + generate_dif: true + } + { + name: rv_plic + type: rv_plic + template_type: rv_plic + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + attr: ipgen + targets: + [ + rv_core_ibex + ] + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: irq + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + external: true + top_signame: no_ibex_irq + conn_type: false + index: -1 + } + { + name: irq_id + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + index: -1 + } + { + name: msip + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + external: true + top_signame: no_ibex_msip + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_plic + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x28000000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: aes + type: aes + clock_srcs: + { + clk_i: main + clk_edn_i: main + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + param_decl: + { + SecMasking: "1" + SecSBoxImpl: aes_pkg::SBoxImplDom + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_aes + clk_edn_i: clkmgr_aon_clocks.clk_main_aes + } + memory: {} + param_list: + [ + { + name: AES192Enable + desc: Disable (0) or enable (1) support for 192-bit key lengths (AES-192). + type: bit + default: 1'b1 + local: "false" + expose: "false" + name_top: AesAES192Enable + } + { + name: SecMasking + desc: + ''' + Disable (0) or enable (1) first-order masking of the AES cipher core. + Masking requires the use of a masked S-Box, see SecSBoxImpl parameter. + ''' + type: bit + default: "1" + local: "false" + expose: "true" + name_top: SecAesMasking + } + { + name: SecSBoxImpl + desc: Selection of the S-Box implementation. See aes_pkg.sv. + type: aes_pkg::sbox_impl_e + default: aes_pkg::SBoxImplDom + local: "false" + expose: "true" + name_top: SecAesSBoxImpl + } + { + name: SecStartTriggerDelay + desc: + ''' + Manual start trigger delay, useful for SCA measurements. + A value of e.g. 40 allows the processor to go into sleep before AES starts operation. + ''' + type: int unsigned + default: "0" + local: "false" + expose: "true" + name_top: SecAesStartTriggerDelay + } + { + name: SecAllowForcingMasks + desc: + ''' + Forbid (0) or allow (1) forcing the masking PRNG output to a constant value via FORCE_MASKS bit in the Auxiliary Control Register. + Useful for SCA measurements. + Meaningful only if masking is enabled. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecAesAllowForcingMasks + } + { + name: SecSkipPRNGReseeding + desc: + ''' + Perform (0) or skip (1) PRNG reseeding requests, useful for SCA measurements only. + The current SCA setup doesn't provide sufficient resources to implement the infrastructure required for PRNG reseeding (CSRNG, EDN). + To enable SCA resistance evaluations, we need to skip reseeding requests on the SCA platform. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecAesSkipPRNGReseeding + } + { + name: RndCnstClearingLfsrSeed + desc: Default seed of the PRNG used for register clearing. + type: aes_pkg::clearing_lfsr_seed_t + randcount: 64 + randtype: data + name_top: RndCnstAesClearingLfsrSeed + default: 0xdf6a55f0d23bb7dc + randwidth: 64 + } + { + name: RndCnstClearingLfsrPerm + desc: Permutation applied to the LFSR of the PRNG used for clearing. + type: aes_pkg::clearing_lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstAesClearingLfsrPerm + default: 0x3875e86196a6b9d9d3a5b3fbe042de8fe1764300a1af2b4119c939360cd4aaff3f496d4c7ca97dde223a01156cd09c43 + randwidth: 384 + } + { + name: RndCnstClearingSharePerm + desc: Permutation applied to the clearing PRNG output for clearing the second share of registers. + type: aes_pkg::clearing_lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstAesClearingSharePerm + default: 0x76b2231d488f580dc16307cdc7e56ed3aa939af33f29bb49f0e9255c52da0d9f42d767b2e3946ced01334a0a069dc869 + randwidth: 384 + } + { + name: RndCnstMaskingLfsrSeed + desc: Default seed of the PRNG used for masking. + type: aes_pkg::masking_lfsr_seed_t + randcount: 288 + randtype: data + name_top: RndCnstAesMaskingLfsrSeed + default: 0x4fb06b9ea47dbf441aa625f5ddf2dcb03c2b867024d54654c6e64e7aac13cb5dd2f3ddbb + randwidth: 288 + } + { + name: RndCnstMaskingLfsrPerm + desc: Permutation applied to the output of the PRNG used for masking. + type: aes_pkg::masking_lfsr_perm_t + randcount: 160 + randtype: perm + name_top: RndCnstAesMaskingLfsrPerm + default: 0x503d686108074c743356290c6d16323491532b2f181f4879172d990d3a0f609e202e8b5f6b808e414f058909397c1b0e73464a4b92025587434569968a124e9f253f867b6c19574d5993902c6e67981388651d72479d8c233e22703b8438421c515b7f01780a8376855c249b522a58115e213700267d1e4004449c82149a1a777a6a8d948f35816f757e0b623031063c4954636610150327365a955d64719728 + randwidth: 1280 + } + ] + inter_signal_list: + [ + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: aes + default: "" + top_signame: clkmgr_aon_idle + index: 0 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: aes + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: aes + default: "" + top_signame: edn0_edn + index: 4 + } + { + name: keymgr_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: aes + default: "" + top_signame: keymgr_dpe_aes_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: aes + default: "" + end_idx: -1 + top_signame: aes_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21100000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: hmac + type: hmac + clock_srcs: + { + clk_i: main + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_hmac + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: hmac + default: "" + top_signame: clkmgr_aon_idle + index: 1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: hmac + default: "" + end_idx: -1 + top_signame: hmac_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21110000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: kmac + type: kmac + param_decl: + { + EnMasking: "1" + NumAppIntf: 4 + AppCfg: + ''' + '{kmac_pkg::AppCfgKeyMgr, + kmac_pkg::AppCfgLcCtrl, + kmac_pkg::AppCfgRomCtrl, + kmac_pkg::AppCfgRomCtrl} + ''' + } + clock_srcs: + { + clk_i: main + clk_edn_i: main + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_kmac + clk_edn_i: clkmgr_aon_clocks.clk_main_kmac + } + memory: {} + param_list: + [ + { + name: EnMasking + desc: Disable(0) or enable(1) first-order masking of Keccak round. + type: bit + default: "1" + local: "false" + expose: "true" + name_top: KmacEnMasking + } + { + name: SwKeyMasked + desc: + ''' + Disable(0) or enable(1) software key masking in case masking is disabled (EnMasking == 0). + If masking is enabled, this parameter has no effect. + Mainly useful for software interface compatibility between the masked and unmasked design. + Mostly relevant for SCA measurements. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: KmacSwKeyMasked + } + { + name: SecCmdDelay + desc: + ''' + Command delay, useful for SCA measurements only. + A value of e.g. 40 allows the processor to go into sleep before KMAC starts operation. + If a value greater than 0 is chosen, software can pass two commands in series. + The second command is buffered internally and will be presented to the hardware SecCmdDelay number of cycles after the first one. + ''' + type: int + default: "0" + local: "false" + expose: "true" + name_top: SecKmacCmdDelay + } + { + name: SecIdleAcceptSwMsg + desc: + ''' + If enabled (1), software writes to the message FIFO before having received a START command are not ignored. + Disabled (0) by default. + Useful for SCA measurements only. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SecKmacIdleAcceptSwMsg + } + { + name: NumAppIntf + desc: Number of application interfaces + type: int + default: 4 + local: "false" + expose: "true" + name_top: KmacNumAppIntf + } + { + name: AppCfg + desc: + ''' + Application interface configuration. + Top-level connection to the application interface must follow this definition. + ''' + type: kmac_pkg::app_config_t + unpacked_dimensions: "[KmacNumAppIntf]" + default: + ''' + '{kmac_pkg::AppCfgKeyMgr, + kmac_pkg::AppCfgLcCtrl, + kmac_pkg::AppCfgRomCtrl, + kmac_pkg::AppCfgRomCtrl} + ''' + local: "false" + expose: "true" + name_top: KmacAppCfg + } + { + name: RndCnstLfsrSeed + desc: Compile-time random data for PRNG default seed + type: kmac_pkg::lfsr_seed_t + randcount: 288 + randtype: data + name_top: RndCnstKmacLfsrSeed + default: 0x452480a61092e8a80cdf267889e06a8a1ab5f6db8158aa7c98ddec2834fdd68225ac00e6 + randwidth: 288 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for PRNG output + type: kmac_pkg::lfsr_perm_t + randcount: 800 + randtype: perm + name_top: RndCnstKmacLfsrPerm + default: 0xa2269242199b14c0d6f316e1a90057190d034d1f02e4676d8a4b70b3f9946a0768e15649d5d14423a9e5a0bd47472d05db04226e1c487fbe8498d8339bd879ac9fbf2679fb1d1357b9b4719486705eb25797f6c87510150838a47e6d1b728b4e23d25182b9545bc50c760419281a2b4db68981baea93e1ba84cb2166684771cbbc385344bb68b9814ec4893932abcc7c55c605ead2fb5cc60b5a249347279f1383e65668636a4f48c6f6aa9208a8ce6806d616662a535171666d6ec7f1dca55bf560f9276b671d347f52a68c70296b1368bf3f0197fc54088e34cdb674b11140471e989909623a062bd3199cdcc991e185025c188e736bd26c3f86d52a66dead47956516052b7895c6a682a0ae8da29e624d3c91cee72c1ebaa2d9f47bc34842ddde43e22abf020d90a9064987dfbba2977a4301bacdb0f0855192092c2086a080cccb02854c5cf6bd0b39a4378c9e00aca1b2ba7895c21ad28c8d8199c47bcab9886face5f01c37664fabfd2689e093b43c1ddc32085a04820aecfd17e266b906422e07223fa455b03e3e729658a1834da3a9b9741325e55557a52ceafdb8837145924c738f27d83a5f68282e484926abdee78a650014e411a90751095e03d1a9ad6721ec6c524b31770a1169103b747c5a5a59c97722826886a33cd5a6a8a1580a25bd3f9e45350b15638b47aa9b2a14e7e9e546123c00d44540a4f48c518af5f869b06d7112a852d861144313ef2832d5018c2401d5700d73187e07d37bf967822a63aadb96caa985684956b1770f2669f6eef80ec329ecefaaeedc591293a06afae4b1465be52e53d512201175a711d1a1a18036799322c4e3894109e9c062340a6043357265c98055ed5c5b12559d1870c3c58d2ba772c27c8412b7acb5801d96424bbf4cb7d47d77d884a16aac104485f39d623b50fb3828c298d5465d30700c316e27a28364698c04e18f10d971bdb7e87004f6a785670487259d7010a04a41ba101d20d5fb3292b1c80a86b90231a80a814be5d9c1530d293025be46930520be450d2aba18b4de0366898c16e950e73ddee85a7f478dc394ff5b65662c8d9e144c24a7128cf21458791f1848c385df0ab43e4425391091525bc002155e5ab876e97431e93cf06d039344eb91660b2e553d563311073022b7b0ba8709ac2ad88b0782c5ac04105038d6b3d9898d0e72659a942cc38e9b1ae34ed3a829f405a516dcc7b66332d8c17f9a7775f8b9980324bd880df45e742b2ee5d6f54048fa3a395e9115b22e8ee7667df24c9b3120132ec42270812f02eab0737691b4f9f7375a66c20765892322373786828eb8502c4714b863cb350c2dc0d02c1ec966e96c15615c258a3e9d8bc28b20317457c80497a02f0a880d44d95a9184632359eb101adb995d4a + randwidth: 8000 + } + { + name: RndCnstBufferLfsrSeed + desc: Compile-time random data for PRNG buffer default seed + type: kmac_pkg::buffer_lfsr_seed_t + randcount: 800 + randtype: data + name_top: RndCnstKmacBufferLfsrSeed + default: 0x2246562dcceda3a423366a8096b121fa42246b6c385a5aa3b4fe9c0a8d1f2128e03e0b01632e027e34c81340bcfd0fd53473b5440b76763b45bca8166865fdaf59f386d5174cc7f5fd1f544b3a82c54e1481730f66854723d00560945b6c126ffec03bf1 + randwidth: 800 + } + { + name: RndCnstMsgPerm + desc: Compile-time random permutation for LFSR Message output + type: kmac_pkg::msg_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstKmacMsgPerm + default: 0xb9c2273f03a025ff456fab7c566bf4e474544fb598d7390234bddac6888c0de1b649940113e969fece0a7725eb8c086a + randwidth: 384 + } + ] + inter_signal_list: + [ + { + name: keymgr_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: kmac + default: "" + top_signame: keymgr_dpe_kmac_key + index: -1 + } + { + name: app + struct: app + package: kmac_pkg + type: req_rsp + act: rsp + width: + { + name: NumAppIntf + desc: Number of application interfaces + param_type: int + unpacked_dimensions: null + default: 3 + local: false + expose: true + name_top: KmacNumAppIntf + } + inst_name: kmac + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: kmac_app + index: -1 + } + { + name: entropy + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: kmac + default: "" + top_signame: edn0_edn + index: 2 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: kmac + default: "" + top_signame: clkmgr_aon_idle + index: 2 + } + { + name: en_masking + struct: logic + type: uni + act: req + width: 1 + inst_name: kmac + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: kmac_en_masking + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: kmac + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: kmac + default: "" + end_idx: -1 + top_signame: kmac_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21120000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: otbn + type: otbn + clock_srcs: + { + clk_i: + { + clock: main + group: trans + } + clk_edn_i: + { + clock: main + group: secure + } + clk_otp_i: + { + clock: io_div4 + group: secure + } + } + clock_group: trans + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + rst_otp_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_otbn + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure + } + param_decl: {} + memory: {} + param_list: + [ + { + name: Stub + desc: Stub out the core of Otbn logic + type: bit + default: "0" + local: "false" + expose: "true" + name_top: OtbnStub + } + { + name: RegFile + desc: Selection of the register file implementation. See otbn_pkg.sv. + type: otbn_pkg::regfile_e + default: otbn_pkg::RegFileFF + local: "false" + expose: "true" + name_top: OtbnRegFile + } + { + name: RndCnstUrndPrngSeed + desc: Default seed of the PRNG used for URND. + type: otbn_pkg::urnd_prng_seed_t + randcount: 256 + randtype: data + name_top: RndCnstOtbnUrndPrngSeed + default: 0xf8a394a094c63c8af070919cd8b168cab6a734a2a92b34ba17c531911e20c1a4 + randwidth: 256 + } + { + name: SecMuteUrnd + desc: + ''' + If enabled (1), URND is advanced only when data is needed. + Disabled (0) by default. + Useful for SCA measurements only. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SecOtbnMuteUrnd + } + { + name: SecSkipUrndReseedAtStart + desc: + ''' + If enabled (1), URND reseed is skipped at the start of an operation. + Disabled (0) by default. + Useful for SCA measurements only. + ''' + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SecOtbnSkipUrndReseedAtStart + } + { + name: RndCnstOtbnKey + desc: Compile-time random reset value for IMem/DMem scrambling key. + type: otp_ctrl_pkg::otbn_key_t + randcount: 128 + randtype: data + name_top: RndCnstOtbnOtbnKey + default: 0x96592784ac089e72877bdaf9f7954486 + randwidth: 128 + } + { + name: RndCnstOtbnNonce + desc: Compile-time random reset value for IMem/DMem scrambling nonce. + type: otp_ctrl_pkg::otbn_nonce_t + randcount: 64 + randtype: data + name_top: RndCnstOtbnOtbnNonce + default: 0x164b58ea68f9b7f6 + randwidth: 64 + } + ] + inter_signal_list: + [ + { + name: otbn_otp_key + struct: otbn_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: otbn + top_signame: otp_ctrl_otbn_otp_key + index: -1 + } + { + name: edn_rnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: edn1_edn + index: 0 + } + { + name: edn_urnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: edn0_edn + index: 5 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: clkmgr_aon_idle + index: 3 + } + { + name: ram_cfg_imem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + external: true + top_signame: otbn_imem_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: ram_cfg_dmem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + external: true + top_signame: otbn_dmem_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_imem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: otbn + default: "" + external: true + top_signame: otbn_imem_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_dmem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: otbn + default: "" + external: true + top_signame: otbn_dmem_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + end_idx: -1 + top_type: broadcast + top_signame: otbn_lc_rma_ack + index: -1 + } + { + name: keymgr_key + struct: otbn_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + top_signame: keymgr_dpe_otbn_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otbn + default: "" + end_idx: -1 + top_signame: otbn_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21130000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: keymgr_dpe + type: keymgr_dpe + clock_srcs: + { + clk_i: main + clk_edn_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_edn_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + clk_edn_i: clkmgr_aon_clocks.clk_main_secure + } + param_decl: {} + memory: {} + param_list: + [ + { + name: KmacEnMasking + desc: Flag indicating with kmac masking is enabled + type: bit + default: "1" + local: "false" + expose: "true" + name_top: KeymgrDpeKmacEnMasking + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: keymgr_pkg::lfsr_seed_t + randcount: 64 + randtype: data + name_top: RndCnstKeymgrDpeLfsrSeed + default: 0x47cdafc1c9a905a7 + randwidth: 64 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: keymgr_pkg::lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstKeymgrDpeLfsrPerm + default: 0xdfc0e31dc106c7301a9ece4cbd726063858dba46554f47f27928a122d3bad9b06b99da7f091d7028bf9094fa05f7b52a + randwidth: 384 + } + { + name: RndCnstRandPerm + desc: Compile-time random permutation for entropy used in share overriding + type: keymgr_pkg::rand_perm_t + randcount: 32 + randtype: perm + name_top: RndCnstKeymgrDpeRandPerm + default: 0x3f4d14a962f0303766ec09345b538ddca7f43e15 + randwidth: 160 + } + { + name: RndCnstRevisionSeed + desc: Compile-time random bits for revision seed + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeRevisionSeed + default: 0x6e77b99bf0a1bcd67fb8941c331a44277bc08f711d2d33e72bc40a36399d8364 + randwidth: 256 + } + { + name: RndCnstSoftOutputSeed + desc: Compile-time random bits for software generation seed + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeSoftOutputSeed + default: 0xdcd59508d525078e802f91d8583804fde71271f1738c1cac987a6b8a7758b762 + randwidth: 256 + } + { + name: RndCnstHardOutputSeed + desc: Compile-time random bits for hardware generation seed + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeHardOutputSeed + default: 0x216edd63070949c7834ab6ee6e7ad485ff3ca72c2242223ce6d70f17b4f4b328 + randwidth: 256 + } + { + name: RndCnstAesSeed + desc: Compile-time random bits for generation seed when aes destination selected + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeAesSeed + default: 0x18aa49d125b4defb1f3c0be8a29be065c26d23550bbc139ff6461763d7e966a8 + randwidth: 256 + } + { + name: RndCnstKmacSeed + desc: Compile-time random bits for generation seed when kmac destination selected + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeKmacSeed + default: 0xa7219eb2e8ef9f11a152e6c71aa23b8864416e750c01a3339c6c7aa11244ecd2 + randwidth: 256 + } + { + name: RndCnstOtbnSeed + desc: Compile-time random bits for generation seed when otbn destination selected + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeOtbnSeed + default: 0x8a62cb1b851078c2a5f18eee28d0b562043b7312efad871f92e7527da865d661 + randwidth: 256 + } + { + name: RndCnstNoneSeed + desc: Compile-time random bits for generation seed when no destination selected + type: keymgr_pkg::seed_t + randcount: 256 + randtype: data + name_top: RndCnstKeymgrDpeNoneSeed + default: 0x281fe98dfcd72e3c6d150a85d63009596f7966c5c68caedde4ab7c65fb8d5961 + randwidth: 256 + } + ] + inter_signal_list: + [ + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: edn0_edn + index: 0 + } + { + name: aes_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_aes_key + index: -1 + } + { + name: kmac_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_kmac_key + index: -1 + } + { + name: otbn_key + struct: otbn_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_otbn_key + index: -1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: kmac_app + index: 0 + } + { + name: otp_key + struct: otp_keymgr_key + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: otp_ctrl_otp_keymgr_key + index: -1 + } + { + name: otp_device_id + struct: otp_device_id + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: keymgr_dpe_otp_device_id + index: -1 + } + { + name: lc_keymgr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::On + inst_name: keymgr_dpe + top_signame: lc_ctrl_lc_keymgr_en + index: -1 + } + { + name: lc_keymgr_div + struct: lc_keymgr_div + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: lc_ctrl_lc_keymgr_div + index: -1 + } + { + name: rom_digest + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: rcv + width: 2 + default: rom_ctrl_pkg::KEYMGR_DATA_DEFAULT + inst_name: keymgr_dpe + end_idx: -1 + top_type: one-to-N + top_signame: keymgr_dpe_rom_digest + index: -1 + } + { + name: kmac_en_masking + struct: logic + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + package: "" + top_signame: kmac_en_masking + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_signame: keymgr_dpe_tl + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21140000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: csrng + type: csrng + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + param_decl: {} + memory: {} + param_list: + [ + { + name: RndCnstCsKeymgrDivNonProduction + desc: Compile-time random bits for csrng state group diversification value + type: csrng_pkg::cs_keymgr_div_t + randcount: 384 + randtype: data + name_top: RndCnstCsrngCsKeymgrDivNonProduction + default: 0x8284064d7194e4707ada81f8a6db14ca845beee60798289ad4fb0df1768296390152700e078ec5a951b627cf2ccd155d + randwidth: 384 + } + { + name: RndCnstCsKeymgrDivProduction + desc: Compile-time random bits for csrng state group diversification value + type: csrng_pkg::cs_keymgr_div_t + randcount: 384 + randtype: data + name_top: RndCnstCsrngCsKeymgrDivProduction + default: 0x84fdaced736e93362c8da83c5f4dd2093e4d2a70dd99dcf4ccac341a2f1a2704f5e21287fa168af251b370d034cda605 + randwidth: 384 + } + { + name: SBoxImpl + desc: Selection of the S-Box implementation. See aes_pkg.sv. + type: aes_pkg::sbox_impl_e + default: aes_pkg::SBoxImplCanright + local: "false" + expose: "true" + name_top: CsrngSBoxImpl + } + ] + inter_signal_list: + [ + { + name: csrng_cmd + struct: csrng + package: csrng_pkg + type: req_rsp + act: rsp + width: 2 + inst_name: csrng + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: csrng_csrng_cmd + index: -1 + } + { + name: entropy_src_hw_if + struct: entropy_src_hw_if + package: entropy_src_pkg + type: req_rsp + act: req + width: 1 + inst_name: csrng + default: "" + end_idx: -1 + top_signame: csrng_entropy_src_hw_if + index: -1 + } + { + name: cs_aes_halt + desc: + ''' + Coordinate activity between CSRNG's AES and Entropy Source's SHA3. + When CSRNG gets a request and its AES is not active, it acknowledges and until the request has dropped neither runs its AES nor drops the acknowledge. + ''' + struct: cs_aes_halt + package: entropy_src_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: csrng + default: "" + end_idx: -1 + top_signame: csrng_cs_aes_halt + index: -1 + } + { + name: otp_en_csrng_sw_app_read + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8True + inst_name: csrng + top_signame: csrng_otp_en_csrng_sw_app_read + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: csrng + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: csrng + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21150000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: entropy_src + type: entropy_src + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + param_decl: + { + RngBusWidth: "16" + RngBusBitSelWidth: "4" + HealthTestWindowWidth: "20" + DistrFifoDepth: "26" + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + memory: {} + param_list: + [ + { + name: RngBusWidth + desc: + ''' + Defines the bit-width of the noise source data. + Must be between 4 and 256 (inclusive) and divisible by 4. + The divisibility by 4 is a prerequisite for the bucket health test. + ''' + type: int + default: "16" + local: "false" + expose: "true" + name_top: EntropySrcRngBusWidth + } + { + name: RngBusBitSelWidth + desc: Explicit parameter defining the width of the RNG bit selection vector (log2(RngBusWidth)) + type: int + default: "4" + local: "false" + expose: "true" + name_top: EntropySrcRngBusBitSelWidth + } + { + name: HealthTestWindowWidth + desc: Explicit parameter defining the width of the health test window (16 + log2(RngBusWidth)) + type: int + default: "20" + local: "false" + expose: "true" + name_top: EntropySrcHealthTestWindowWidth + } + { + name: EsFifoDepth + desc: Number of 384-bit entries in the esfinal FIFO + type: int + default: "3" + local: "true" + expose: "true" + name_top: EntropySrcEsFifoDepth + } + { + name: DistrFifoDepth + desc: Number of 32-bit entries in the distr FIFO + type: int unsigned + default: "26" + local: "true" + expose: "true" + name_top: EntropySrcDistrFifoDepth + } + { + name: Stub + desc: Stub out the core of entropy_src logic + type: bit + default: "0" + local: "false" + expose: "true" + name_top: EntropySrcStub + } + ] + inter_signal_list: + [ + { + name: entropy_src_hw_if + struct: entropy_src_hw_if + package: entropy_src_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: entropy_src + default: "" + top_signame: csrng_entropy_src_hw_if + index: -1 + } + { + name: cs_aes_halt + desc: + ''' + Coordinate activity between CSRNG's AES and Entropy Source's SHA3. + The idea is that Entropy Source requests CSRNG's AES to halt and waits for CSRNG to acknowledge before it starts its SHA3. + While SHA3 runs, Entropy Source keeps the request high. + CSRNG may not drop the acknowledge before Entropy Source drops the request. + ''' + struct: cs_aes_halt + package: entropy_src_pkg + type: req_rsp + act: req + width: 1 + inst_name: entropy_src + default: "" + top_signame: csrng_cs_aes_halt + index: -1 + } + { + name: entropy_src_rng_enable + desc: + ''' + Signal through which entropy_src enables the noise source. + entropy_src will keep this signal high as long as it expects the noise source to operate. + This is *not* a flow control signal through which entropy_src would exert backpressure on the noise source; rather this signal stays high while entropy_src is enabled. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: entropy_src + default: "" + package: "" + external: true + top_signame: es_rng_enable + conn_type: false + index: -1 + } + { + name: entropy_src_rng_valid + desc: + ''' + Acknowledgement signal from the noise source. + When '1', it indicates that the `entropy_src_rng_bit` data is valid and ready to be consumed. + ''' + struct: logic + type: uni + act: rcv + width: 1 + inst_name: entropy_src + default: "" + package: "" + external: true + top_signame: es_rng_valid + conn_type: false + index: -1 + } + { + name: entropy_src_rng_bits + desc: + ''' + Output data bus carrying the raw entropy bits from the noise source. + These bits are valid when `entropy_src_rng_valid` is asserted. + The width is determined by `RngBusWidth` parametrization. + ''' + struct: logic + type: uni + act: rcv + width: + { + name: RngBusWidth + desc: + ''' + Defines the bit-width of the noise source data. + Must be between 4 and 256 (inclusive) and divisible by 4. + The divisibility by 4 is a prerequisite for the bucket health test. + ''' + param_type: int + unpacked_dimensions: null + default: 4 + local: false + expose: true + name_top: EntropySrcRngBusWidth + } + inst_name: entropy_src + default: "" + package: "" + external: true + top_signame: es_rng_bit + conn_type: false + index: -1 + } + { + name: entropy_src_xht_valid + desc: + ''' + Valid signal for the external health test interface. + When asserted, it indicates that `entropy_src_xht_bits`, `entropy_src_xht_bit_sel`, and `entropy_src_xht_meta` are valid for consumption by the external health test. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: entropy_src + index: -1 + } + { + name: entropy_src_xht_bits + desc: + ''' + Carries the raw entropy data from the entropy source to be consumed by the external health test module. + The data on this bus is valid when `entropy_src_xht_valid` is asserted. + The width is determined by `RngBusWidth` parametrization. + ''' + struct: logic + type: uni + act: req + width: + { + name: RngBusWidth + desc: + ''' + Defines the bit-width of the noise source data. + Must be between 4 and 256 (inclusive) and divisible by 4. + The divisibility by 4 is a prerequisite for the bucket health test. + ''' + param_type: int + unpacked_dimensions: null + default: 4 + local: false + expose: true + name_top: EntropySrcRngBusWidth + } + inst_name: entropy_src + index: -1 + } + { + name: entropy_src_xht_bit_sel + desc: + ''' + Provides bit selection information for the raw entropy data. + It specifies which specific bit or subset of bits from `entropy_src_xht_bit` should be used. + The width is determined by `RngBusBitSelWidth` parametrization. + ''' + struct: logic + type: uni + act: req + width: + { + name: RngBusBitSelWidth + desc: Explicit parameter defining the width of the RNG bit selection vector (log2(RngBusWidth)) + param_type: int + unpacked_dimensions: null + default: 2 + local: false + expose: true + name_top: EntropySrcRngBusBitSelWidth + } + inst_name: entropy_src + index: -1 + } + { + name: entropy_src_xht_health_test_window + desc: Provides the window size of the health in bits. + struct: logic + type: uni + act: req + width: + { + name: HealthTestWindowWidth + desc: Explicit parameter defining the width of the health test window (16 + log2(RngBusWidth)) + param_type: int + unpacked_dimensions: null + default: 18 + local: false + expose: true + name_top: EntropySrcHealthTestWindowWidth + } + inst_name: entropy_src + index: -1 + } + { + name: entropy_src_xht_meta + struct: entropy_src_xht_meta + package: entropy_src_pkg + type: req_rsp + act: req + width: 1 + inst_name: entropy_src + index: -1 + } + { + name: otp_en_entropy_src_fw_read + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8True + inst_name: entropy_src + index: -1 + } + { + name: otp_en_entropy_src_fw_over + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8True + inst_name: entropy_src + index: -1 + } + { + name: rng_fips + struct: logic + type: uni + act: req + width: 1 + inst_name: entropy_src + default: "" + package: "" + external: true + top_signame: es_rng_fips + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: entropy_src + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21160000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: edn0 + type: edn + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: csrng_cmd + desc: EDN supports a signal CSRNG application interface. + struct: csrng + package: csrng_pkg + type: req_rsp + act: req + width: 1 + inst_name: edn0 + default: "" + top_signame: csrng_csrng_cmd + index: 0 + } + { + name: edn + desc: + ''' + The collection of peripheral ports supported by edn. The width (4) + indicates the number of peripheral ports on a single instance. + Due to limitations in the parametrization of top-level interconnects + this value is not currently parameterizable. However, the number + of peripheral ports may change in a future revision. + ''' + struct: edn + package: edn_pkg + type: req_rsp + act: rsp + width: 8 + default: "'0" + inst_name: edn0 + end_idx: 6 + top_type: partial-one-to-N + top_signame: edn0_edn + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: edn0 + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21170000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: edn1 + type: edn + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: csrng_cmd + desc: EDN supports a signal CSRNG application interface. + struct: csrng + package: csrng_pkg + type: req_rsp + act: req + width: 1 + inst_name: edn1 + default: "" + top_signame: csrng_csrng_cmd + index: 1 + } + { + name: edn + desc: + ''' + The collection of peripheral ports supported by edn. The width (4) + indicates the number of peripheral ports on a single instance. + Due to limitations in the parametrization of top-level interconnects + this value is not currently parameterizable. However, the number + of peripheral ports may change in a future revision. + ''' + struct: edn + package: edn_pkg + type: req_rsp + act: rsp + width: 8 + default: "'0" + inst_name: edn1 + end_idx: 1 + top_type: partial-one-to-N + top_signame: edn1_edn + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: edn1 + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x21180000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: sram_ctrl_main + type: sram_ctrl + clock_srcs: + { + clk_i: main + clk_otp_i: io_div4 + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_otp_ni: + { + name: lc_io_div4 + domain: "0" + } + } + param_decl: + { + InstrExec: "1" + InstSize: 65536 + } + base_addrs: + { + regs: + { + hart: 0x211c0000 + } + ram: + { + hart: 0x10000000 + } + } + memory: + { + ram: + { + label: ram_main + swaccess: rw + data_intg_passthru: "true" + exec: True + byte_write: True + size: 0x10000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra + } + param_list: + [ + { + name: RndCnstSramKey + desc: Compile-time random reset value for SRAM scrambling key. + type: otp_ctrl_pkg::sram_key_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMainSramKey + default: 0x152662f4d11b3245d5943ea5fd2e4bea + randwidth: 128 + } + { + name: RndCnstSramNonce + desc: Compile-time random reset value for SRAM scrambling nonce. + type: otp_ctrl_pkg::sram_nonce_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMainSramNonce + default: 0x16b7911deaf01df742547371445d6e3 + randwidth: 128 + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: sram_ctrl_pkg::lfsr_seed_t + randcount: 64 + randtype: data + name_top: RndCnstSramCtrlMainLfsrSeed + default: 0x955145e3074d9ca9 + randwidth: 64 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: sram_ctrl_pkg::lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstSramCtrlMainLfsrPerm + default: 0x839f7f3c512a2a1af31add8c8b867c90b56872526c01350399f5913741debaf4317489c2dda61b3b5c328d74be07ba7a + randwidth: 384 + } + { + name: MemSizeRam + desc: Memory size of the RAM (in bytes). + type: int + name_top: MemSizeSramCtrlMainRam + default: 65536 + } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: 65536 + local: "false" + expose: "true" + name_top: SramCtrlMainInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlMainNumRamInst + } + { + name: InstrExec + desc: Support execution from SRAM + type: bit + default: "1" + local: "false" + expose: "true" + name_top: SramCtrlMainInstrExec + } + { + name: NumPrinceRoundsHalf + desc: Number of PRINCE half rounds for the SRAM scrambling feature + type: int + default: "3" + local: "false" + expose: "true" + name_top: SramCtrlMainNumPrinceRoundsHalf + } + { + name: Outstanding + desc: Number of outstanding TLUL transactions + type: int + default: "2" + local: "true" + expose: "true" + name_top: SramCtrlMainOutstanding + } + { + name: EccCorrection + desc: Enable single-bit error correction and error logging + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlMainEccCorrection + } + ] + inter_signal_list: + [ + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_main + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 0 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } + default: "'0" + inst_name: sram_ctrl_main + external: true + top_signame: sram_ctrl_main_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } + default: "'0" + inst_name: sram_ctrl_main + external: true + top_signame: sram_ctrl_main_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_main + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_main + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_main + top_signame: sram_ctrl_main_otp_en_sram_ifetch + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: sram_ctrl_main + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_main + index: -1 + } + { + name: sram_rerror + desc: SRAM read error indicating correctable and uncorrectable ECC errors. + struct: sram_error_t + package: sram_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_main + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_main + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_main + default: "" + end_idx: -1 + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: sram_ctrl_mbox + type: sram_ctrl + clock_srcs: + { + clk_i: main + clk_otp_i: io_div4 + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + rst_otp_ni: + { + name: lc_io_div4 + domain: "0" + } + } + param_decl: + { + InstrExec: "0" + InstSize: 4096 + } + base_addrs: + { + regs: + { + hart: 0x211d0000 + } + ram: + { + hart: 0x11000000 + } + } + memory: + { + ram: + { + label: ram_mbox + swaccess: rw + data_intg_passthru: "true" + exec: False + byte_write: True + size: 0x1000 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra + } + param_list: + [ + { + name: RndCnstSramKey + desc: Compile-time random reset value for SRAM scrambling key. + type: otp_ctrl_pkg::sram_key_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMboxSramKey + default: 0x29bd781efe2b4b06f4b349e0372b7394 + randwidth: 128 + } + { + name: RndCnstSramNonce + desc: Compile-time random reset value for SRAM scrambling nonce. + type: otp_ctrl_pkg::sram_nonce_t + randcount: 128 + randtype: data + name_top: RndCnstSramCtrlMboxSramNonce + default: 0xd415d937f3578cc1200dd1fb1d0ecf94 + randwidth: 128 + } + { + name: RndCnstLfsrSeed + desc: Compile-time random bits for initial LFSR seed + type: sram_ctrl_pkg::lfsr_seed_t + randcount: 64 + randtype: data + name_top: RndCnstSramCtrlMboxLfsrSeed + default: 0x8594bc831c3e0e1f + randwidth: 64 + } + { + name: RndCnstLfsrPerm + desc: Compile-time random permutation for LFSR output + type: sram_ctrl_pkg::lfsr_perm_t + randcount: 64 + randtype: perm + name_top: RndCnstSramCtrlMboxLfsrPerm + default: 0x392500f4625987fc175bb8f4ae86ec565810348753a6215ae4405f3d1ddc9ea7b8bb31fc90b2bad43b42c7662ffa6c8c + randwidth: 384 + } + { + name: MemSizeRam + desc: Memory size of the RAM (in bytes). + type: int + name_top: MemSizeSramCtrlMboxRam + default: 4096 + } + { + name: InstSize + desc: Memory size of a single RAM tile (in bytes). + type: int + default: 4096 + local: "false" + expose: "true" + name_top: SramCtrlMboxInstSize + } + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + type: int + default: 1 + local: "false" + expose: "true" + name_top: SramCtrlMboxNumRamInst + } + { + name: InstrExec + desc: Support execution from SRAM + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlMboxInstrExec + } + { + name: NumPrinceRoundsHalf + desc: Number of PRINCE half rounds for the SRAM scrambling feature + type: int + default: "3" + local: "false" + expose: "true" + name_top: SramCtrlMboxNumPrinceRoundsHalf + } + { + name: Outstanding + desc: Number of outstanding TLUL transactions + type: int + default: "2" + local: "true" + expose: "true" + name_top: SramCtrlMboxOutstanding + } + { + name: EccCorrection + desc: Enable single-bit error correction and error logging + type: bit + default: "0" + local: "false" + expose: "true" + name_top: SramCtrlMboxEccCorrection + } + ] + inter_signal_list: + [ + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_mbox + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 2 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } + default: "'0" + inst_name: sram_ctrl_mbox + external: true + top_signame: sram_ctrl_mbox_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } + default: "'0" + inst_name: sram_ctrl_mbox + external: true + top_signame: sram_ctrl_mbox_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_mbox + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: sram_rerror + desc: SRAM read error indicating correctable and uncorrectable ECC errors. + struct: sram_error_t + package: sram_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_mbox + default: "" + end_idx: -1 + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: rom_ctrl0 + type: rom_ctrl + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + rom: + { + hart: 0x00008000 + } + regs: + { + hart: 0x211e0000 + } + } + memory: + { + rom: + { + label: rom0 + swaccess: ro + data_intg_passthru: True + exec: True + byte_write: False + size: 0x8000 + } + } + param_decl: + { + SecDisableScrambling: 1'b0 + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_list: + [ + { + name: BootRomInitFile + desc: Contents of ROM + type: "" + default: '''""''' + local: "false" + expose: "true" + name_top: RomCtrl0BootRomInitFile + } + { + name: RndCnstScrNonce + desc: Fixed nonce used for address / data scrambling + type: bit [63:0] + randcount: 64 + randtype: data + name_top: RndCnstRomCtrl0ScrNonce + default: 0x435205ef40d4b50c + randwidth: 64 + } + { + name: RndCnstScrKey + desc: Randomised constant used as a scrambling key for ROM data + type: bit [127:0] + randcount: 128 + randtype: data + name_top: RndCnstRomCtrl0ScrKey + default: 0xbd86b4932d75cebe7060738efa203541 + randwidth: 128 + } + { + name: SecDisableScrambling + desc: + ''' + Disable scrambling and checking in rom_ctrl, turning the block into a + simple ROM wrapper. This isn't intended for real chips, but is useful + for small FPGA targets where there's not space for the PRINCE + primitives. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecRomCtrl0DisableScrambling + } + { + name: MemSizeRom + desc: Memory size of the ROM (in bytes). + type: int + name_top: MemSizeRomCtrl0Rom + default: 32768 + } + ] + inter_signal_list: + [ + { + name: rom_cfg + struct: rom_cfg + package: prim_rom_pkg + type: uni + act: rcv + width: 1 + inst_name: rom_ctrl0 + default: "" + external: true + top_signame: rom_ctrl0_cfg + conn_type: false + index: -1 + } + { + name: pwrmgr_data + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: 0 + } + { + name: keymgr_data + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: keymgr_dpe_rom_digest + index: 0 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: kmac_app + index: 2 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl0 + index: -1 + } + { + name: rom_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl0 + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: rom_ctrl1 + type: rom_ctrl + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + rom: + { + hart: 0x00020000 + } + regs: + { + hart: 0x211e1000 + } + } + memory: + { + rom: + { + label: rom1 + swaccess: ro + data_intg_passthru: True + exec: True + byte_write: False + size: 0x10000 + } + } + param_decl: + { + SecDisableScrambling: 1'b0 + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_list: + [ + { + name: BootRomInitFile + desc: Contents of ROM + type: "" + default: '''""''' + local: "false" + expose: "true" + name_top: RomCtrl1BootRomInitFile + } + { + name: RndCnstScrNonce + desc: Fixed nonce used for address / data scrambling + type: bit [63:0] + randcount: 64 + randtype: data + name_top: RndCnstRomCtrl1ScrNonce + default: 0x8082cfe96e5cc128 + randwidth: 64 + } + { + name: RndCnstScrKey + desc: Randomised constant used as a scrambling key for ROM data + type: bit [127:0] + randcount: 128 + randtype: data + name_top: RndCnstRomCtrl1ScrKey + default: 0xfbe2f2e323688bcc7ecbb1a7db7be4c + randwidth: 128 + } + { + name: SecDisableScrambling + desc: + ''' + Disable scrambling and checking in rom_ctrl, turning the block into a + simple ROM wrapper. This isn't intended for real chips, but is useful + for small FPGA targets where there's not space for the PRINCE + primitives. + ''' + type: bit + default: 1'b0 + local: "false" + expose: "true" + name_top: SecRomCtrl1DisableScrambling + } + { + name: MemSizeRom + desc: Memory size of the ROM (in bytes). + type: int + name_top: MemSizeRomCtrl1Rom + default: 65536 + } + ] + inter_signal_list: + [ + { + name: rom_cfg + struct: rom_cfg + package: prim_rom_pkg + type: uni + act: rcv + width: 1 + inst_name: rom_ctrl1 + default: "" + external: true + top_signame: rom_ctrl1_cfg + conn_type: false + index: -1 + } + { + name: pwrmgr_data + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: 1 + } + { + name: keymgr_data + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: keymgr_dpe_rom_digest + index: 1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: kmac_app + index: 3 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl1 + index: -1 + } + { + name: rom_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl1 + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: dma + type: dma + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + memory: {} + param_list: + [ + { + name: EnableDataIntgGen + desc: Compute integrity bits for A channel data on all TL-UL host ports + type: bit + default: 1'b1 + local: "false" + expose: "true" + name_top: DmaEnableDataIntgGen + } + { + name: EnableRspDataIntgCheck + desc: Enable integrity checks on the response TL-UL D channel + type: bit + default: 1'b1 + local: "false" + expose: "true" + name_top: DmaEnableRspDataIntgCheck + } + { + name: TlUserRsvd + desc: Value of `rsvd` field in A channel of all TL-UL host ports + type: logic [tlul_pkg::RsvdWidth-1:0] + default: "'0" + local: "false" + expose: "true" + name_top: DmaTlUserRsvd + } + { + name: SysRacl + desc: Value of `racl_vec` field in `sys` output + type: logic [dma_pkg::SYS_RACL_WIDTH-1:0] + default: "'0" + local: "false" + expose: "true" + name_top: DmaSysRacl + } + { + name: OtAgentId + desc: OT Agent ID + type: int unsigned + default: "0" + local: "false" + expose: "true" + name_top: DmaOtAgentId + } + ] + inter_signal_list: + [ + { + name: lsio_trigger + struct: lsio_trigger + package: dma_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + default: "" + end_idx: -1 + top_type: broadcast + top_signame: dma_lsio_trigger + index: -1 + } + { + name: sys + struct: sys + package: dma_pkg + type: req_rsp + act: req + width: 1 + inst_name: dma + default: "" + external: true + top_signame: dma_sys + conn_type: false + index: -1 + } + { + name: ctn_tl_h2d + desc: TL-UL host port for egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: dma + default: "" + top_signame: soc_proxy_dma_tl_h2d + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL host port for egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + default: "" + top_signame: soc_proxy_dma_tl_d2h + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: dma + index: -1 + } + { + name: host_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dma + default: "" + top_signame: main_tl_dma__host + index: -1 + } + { + name: tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: dma + index: -1 + } + ] + base_addrs: + { + null: + { + hart: 0x22010000 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx0 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000000 + } + soc: + { + soc_mbx: 0x01465000 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 0 + SOC_STATUS: 0 + SOC_DOE_INTR_MSG_ADDR: 0 + SOC_DOE_INTR_MSG_DATA: 0 + } + window_mapping: + { + WDATA: 0 + RDATA: 0 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx0 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx0 + default: "" + top_signame: racl_ctrl_racl_error + index: 0 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx0 + default: "" + top_signame: main_tl_mbx0__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx0 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx0 + default: "" + end_idx: -1 + top_signame: mbx0_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx1 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000100 + } + soc: + { + soc_mbx: 0x01465100 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 0 + SOC_STATUS: 0 + SOC_DOE_INTR_MSG_ADDR: 0 + SOC_DOE_INTR_MSG_DATA: 0 + } + window_mapping: + { + WDATA: 0 + RDATA: 0 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx1 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx1 + default: "" + top_signame: racl_ctrl_racl_error + index: 1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx1 + default: "" + top_signame: main_tl_mbx1__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx1 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx1 + default: "" + end_idx: -1 + top_signame: mbx1_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx2 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000200 + } + soc: + { + soc_mbx: 0x01465200 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 0 + SOC_STATUS: 0 + SOC_DOE_INTR_MSG_ADDR: 0 + SOC_DOE_INTR_MSG_DATA: 0 + } + window_mapping: + { + WDATA: 0 + RDATA: 0 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx2 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx2 + default: "" + top_signame: racl_ctrl_racl_error + index: 2 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx2 + default: "" + top_signame: main_tl_mbx2__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx2 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx2 + default: "" + end_idx: -1 + top_signame: mbx2_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx3 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000300 + } + soc: + { + soc_mbx: 0x01465300 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 0 + SOC_STATUS: 0 + SOC_DOE_INTR_MSG_ADDR: 0 + SOC_DOE_INTR_MSG_DATA: 0 + } + window_mapping: + { + WDATA: 0 + RDATA: 0 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx3 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx3 + default: "" + top_signame: racl_ctrl_racl_error + index: 3 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx3 + default: "" + top_signame: main_tl_mbx3__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx3 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx3 + default: "" + end_idx: -1 + top_signame: mbx3_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx4 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000400 + } + soc: + { + soc_mbx: 0x01465400 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 0 + SOC_STATUS: 0 + SOC_DOE_INTR_MSG_ADDR: 0 + SOC_DOE_INTR_MSG_DATA: 0 + } + window_mapping: + { + WDATA: 0 + RDATA: 0 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx4 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx4 + default: "" + top_signame: racl_ctrl_racl_error + index: 4 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx4 + default: "" + top_signame: main_tl_mbx4__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx4 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx4 + default: "" + end_idx: -1 + top_signame: mbx4_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx5 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000500 + } + soc: + { + soc_mbx: 0x01465500 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 0 + SOC_STATUS: 0 + SOC_DOE_INTR_MSG_ADDR: 0 + SOC_DOE_INTR_MSG_DATA: 0 + } + window_mapping: + { + WDATA: 0 + RDATA: 0 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx5 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx5 + default: "" + top_signame: racl_ctrl_racl_error + index: 5 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx5 + default: "" + top_signame: main_tl_mbx5__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx5 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx5 + default: "" + end_idx: -1 + top_signame: mbx5_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx6 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000600 + } + soc: + { + soc_mbx: 0x01496000 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 0 + SOC_STATUS: 0 + SOC_DOE_INTR_MSG_ADDR: 0 + SOC_DOE_INTR_MSG_DATA: 0 + } + window_mapping: + { + WDATA: 0 + RDATA: 0 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx6 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx6 + default: "" + top_signame: racl_ctrl_racl_error + index: 6 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx6 + default: "" + top_signame: main_tl_mbx6__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx6 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx6 + default: "" + end_idx: -1 + top_signame: mbx6_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx_jtag + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22000800 + } + soc: + { + soc_dbg: 0x2200 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 0 + SOC_STATUS: 0 + SOC_DOE_INTR_MSG_ADDR: 0 + SOC_DOE_INTR_MSG_DATA: 0 + } + window_mapping: + { + WDATA: 0 + RDATA: 0 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx_jtag + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx_jtag + default: "" + top_signame: racl_ctrl_racl_error + index: 7 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_jtag + default: "" + top_signame: main_tl_mbx_jtag__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_jtag + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_jtag + default: "" + end_idx: -1 + top_signame: mbx_jtag_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx_pcie0 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22040000 + } + soc: + { + soc_mbx: 0x01460100 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 2 + SOC_STATUS: 2 + SOC_DOE_INTR_MSG_ADDR: 2 + SOC_DOE_INTR_MSG_DATA: 2 + } + window_mapping: + { + WDATA: 2 + RDATA: 2 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx_pcie0 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx_pcie0 + default: "" + top_signame: racl_ctrl_racl_error + index: 8 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_pcie0 + default: "" + top_signame: main_tl_mbx_pcie0__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie0 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie0 + default: "" + end_idx: -1 + top_signame: mbx_pcie0_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: mbx_pcie1 + type: mbx + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x22040100 + } + soc: + { + soc_mbx: 0x01460200 + } + } + racl_mappings: + { + soc: + { + racl_group: Null + register_mapping: + { + SOC_CONTROL: 2 + SOC_STATUS: 2 + SOC_DOE_INTR_MSG_ADDR: 2 + SOC_DOE_INTR_MSG_DATA: 2 + } + window_mapping: + { + WDATA: 2 + RDATA: 2 + } + range_mapping: [] + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx_pcie1 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx_pcie1 + default: "" + top_signame: racl_ctrl_racl_error + index: 9 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_pcie1 + default: "" + top_signame: main_tl_mbx_pcie1__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie1 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie1 + default: "" + end_idx: -1 + top_signame: mbx_pcie1_soc_tl_d + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: soc_dbg_ctrl + type: soc_dbg_ctrl + clock_srcs: + { + clk_i: io_div4 + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc_io_div4 + domain: "0" + } + } + base_addrs: + { + core: + { + hart: 0x30170000 + } + jtag: + { + soc_dbg: 0x2300 + } + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_io_div4_secure + } + param_decl: {} + param_list: [] + inter_signal_list: + [ + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_dbg_ctrl + default: "" + top_signame: pwrmgr_aon_boot_status + index: -1 + } + { + name: soc_dbg_state + struct: soc_dbg_state + package: lc_ctrl_state_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_dbg_ctrl + default: "" + top_signame: soc_dbg_ctrl_soc_dbg_state + index: -1 + } + { + name: soc_dbg_policy_bus + struct: soc_dbg_policy + package: soc_dbg_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: soc_dbg_ctrl + default: "" + external: true + top_signame: soc_dbg_policy_bus + conn_type: false + index: -1 + } + { + name: lc_hw_debug_en + desc: Multibit life cycle hardware debug enable signal coming from life cycle controller, asserted when the hardware debug mechanisms are enabled in the system. + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: soc_dbg_ctrl + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_dft_en + desc: + ''' + Test enable qualifier coming from life cycle controller. + This signals enables TEST & RMA mode accesses. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: soc_dbg_ctrl + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_raw_test_rma + desc: + ''' + Test enable qualifier coming from life cycle controller. + This signals enables RAW, TEST and RMA mode accesses. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: soc_dbg_ctrl + top_signame: lc_ctrl_lc_raw_test_rma + index: -1 + } + { + name: halt_cpu_boot + desc: External request to halt the CPU until a JTAG command allows the boot process to continue. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_dbg_ctrl + default: "" + package: "" + external: true + top_signame: debug_halt_cpu_boot + conn_type: false + index: -1 + } + { + name: continue_cpu_boot + desc: Artificial ROM control input to the pwrmgr to halt the boot process. + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: soc_dbg_ctrl + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: 2 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_dbg_ctrl + default: "" + end_idx: -1 + top_signame: soc_dbg_ctrl_core_tl + index: -1 + } + { + name: jtag_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_dbg_ctrl + default: "" + end_idx: -1 + top_signame: soc_dbg_ctrl_jtag_tl + index: -1 + } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: racl_ctrl + type: racl_ctrl + template_type: racl_ctrl + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + param_decl: {} + memory: {} + param_list: + [ + { + name: NumSubscribingIps + desc: Number of subscribing RACL IPs + type: int + default: 11 + local: "true" + expose: "true" + name_top: RaclCtrlNumSubscribingIps + } + { + name: NumExternalSubscribingIps + desc: Number of external subscribing RACL IPs + type: int + default: 1 + local: "false" + expose: "true" + name_top: RaclCtrlNumExternalSubscribingIps + } + ] + inter_signal_list: + [ + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: racl_ctrl + default: "" + end_idx: -1 + top_type: broadcast + top_signame: racl_ctrl_racl_policies + index: -1 + external: true + conn_type: true + } + { + name: racl_error + desc: + ''' + Error log information from all IPs. + Only one IP can raise an error at a time. + ''' + struct: racl_error_log + package: top_racl_pkg + type: uni + act: rcv + width: + { + name: NumSubscribingIps + desc: Number of subscribing RACL IPs + param_type: int + unpacked_dimensions: null + default: 11 + local: true + expose: true + name_top: RaclCtrlNumSubscribingIps + } + inst_name: racl_ctrl + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: racl_ctrl_racl_error + index: -1 + } + { + name: racl_error_external + desc: + ''' + Error log information from all external IPs. + Only one IP can raise an error at a time. + ''' + struct: racl_error_log + package: top_racl_pkg + type: uni + act: rcv + width: + { + name: NumExternalSubscribingIps + desc: Number of external subscribing RACL IPs + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: RaclCtrlNumExternalSubscribingIps + } + inst_name: racl_ctrl + default: "" + external: true + top_signame: racl_error + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: racl_ctrl + default: "" + end_idx: -1 + top_signame: racl_ctrl_tl + index: -1 + } + ] + base_addrs: + { + null: + { + soc_mbx: 0x01461f00 + } + } + generate_dif: true + domain: + [ + "0" + ] + } + { + name: ac_range_check + type: ac_range_check + template_type: ac_range_check + clock_srcs: + { + clk_i: main + } + clock_group: secure + reset_connections: + { + rst_ni: + { + name: lc + domain: "0" + } + } + ipgen_param: + { + num_ranges: 32 + } + attr: ipgen + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_secure + } + param_decl: {} + memory: {} + param_list: + [ + { + name: RangeCheckErrorRsp + desc: + ''' + Error behavior on blocked requests: + 1: A denied request returns a TLUL error (.d_error = 1 on the response) + 0: Writes are dropped and reads return all-zero, without a TLUL error + ''' + type: bit + default: "1" + local: "false" + expose: "true" + name_top: AcRangeCheckRangeCheckErrorRsp + } + ] + inter_signal_list: + [ + { + name: range_check_overwrite + desc: Overwrites all ranges and let all requests pass through. + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: ac_range_check + default: "" + external: true + top_signame: ac_range_check_overwrite + conn_type: false + index: -1 + } + { + name: ctn_tl_h2d + desc: TL-UL input port (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: ac_range_check + default: "" + top_signame: soc_proxy_ctn_tl_h2d + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL input port (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: ac_range_check + default: "" + top_signame: soc_proxy_ctn_tl_d2h + index: -1 + } + { + name: ctn_filtered_tl_h2d + desc: Filtered TL-UL output port (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: ac_range_check + default: "" + external: true + top_signame: ctn_tl_h2d + conn_type: false + index: -1 + } + { + name: ctn_filtered_tl_d2h + desc: Filtered TL-UL output port (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: ac_range_check + default: "" + external: true + top_signame: ctn_tl_d2h + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: ac_range_check + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: ac_range_check + default: "" + top_signame: racl_ctrl_racl_error + index: 10 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: ac_range_check + default: "" + end_idx: -1 + top_signame: ac_range_check_tl + index: -1 + } + ] + base_addrs: + { + null: + { + soc_mbx: 0x01464000 + } + } + generate_dif: true + racl_mappings: + { + null: + { + racl_group: Null + register_mapping: + { + INTR_STATE: 2 + INTR_ENABLE: 2 + INTR_TEST: 2 + ALERT_TEST: 2 + ALERT_STATUS: 2 + LOG_CONFIG: 2 + LOG_STATUS: 2 + LOG_ADDRESS: 2 + RANGE_REGWEN_0: 2 + RANGE_REGWEN_1: 2 + RANGE_REGWEN_2: 2 + RANGE_REGWEN_3: 2 + RANGE_REGWEN_4: 2 + RANGE_REGWEN_5: 2 + RANGE_REGWEN_6: 2 + RANGE_REGWEN_7: 2 + RANGE_REGWEN_8: 2 + RANGE_REGWEN_9: 2 + RANGE_REGWEN_10: 2 + RANGE_REGWEN_11: 2 + RANGE_REGWEN_12: 2 + RANGE_REGWEN_13: 2 + RANGE_REGWEN_14: 2 + RANGE_REGWEN_15: 2 + RANGE_REGWEN_16: 2 + RANGE_REGWEN_17: 2 + RANGE_REGWEN_18: 2 + RANGE_REGWEN_19: 2 + RANGE_REGWEN_20: 2 + RANGE_REGWEN_21: 2 + RANGE_REGWEN_22: 2 + RANGE_REGWEN_23: 2 + RANGE_REGWEN_24: 2 + RANGE_REGWEN_25: 2 + RANGE_REGWEN_26: 2 + RANGE_REGWEN_27: 2 + RANGE_REGWEN_28: 2 + RANGE_REGWEN_29: 2 + RANGE_REGWEN_30: 2 + RANGE_REGWEN_31: 2 + RANGE_BASE_0: 2 + RANGE_BASE_1: 2 + RANGE_BASE_2: 2 + RANGE_BASE_3: 2 + RANGE_BASE_4: 2 + RANGE_BASE_5: 2 + RANGE_BASE_6: 2 + RANGE_BASE_7: 2 + RANGE_BASE_8: 2 + RANGE_BASE_9: 2 + RANGE_BASE_10: 2 + RANGE_BASE_11: 2 + RANGE_BASE_12: 2 + RANGE_BASE_13: 2 + RANGE_BASE_14: 2 + RANGE_BASE_15: 2 + RANGE_BASE_16: 2 + RANGE_BASE_17: 2 + RANGE_BASE_18: 2 + RANGE_BASE_19: 2 + RANGE_BASE_20: 2 + RANGE_BASE_21: 2 + RANGE_BASE_22: 2 + RANGE_BASE_23: 2 + RANGE_BASE_24: 2 + RANGE_BASE_25: 2 + RANGE_BASE_26: 2 + RANGE_BASE_27: 2 + RANGE_BASE_28: 2 + RANGE_BASE_29: 2 + RANGE_BASE_30: 2 + RANGE_BASE_31: 2 + RANGE_LIMIT_0: 2 + RANGE_LIMIT_1: 2 + RANGE_LIMIT_2: 2 + RANGE_LIMIT_3: 2 + RANGE_LIMIT_4: 2 + RANGE_LIMIT_5: 2 + RANGE_LIMIT_6: 2 + RANGE_LIMIT_7: 2 + RANGE_LIMIT_8: 2 + RANGE_LIMIT_9: 2 + RANGE_LIMIT_10: 2 + RANGE_LIMIT_11: 2 + RANGE_LIMIT_12: 2 + RANGE_LIMIT_13: 2 + RANGE_LIMIT_14: 2 + RANGE_LIMIT_15: 2 + RANGE_LIMIT_16: 2 + RANGE_LIMIT_17: 2 + RANGE_LIMIT_18: 2 + RANGE_LIMIT_19: 2 + RANGE_LIMIT_20: 2 + RANGE_LIMIT_21: 2 + RANGE_LIMIT_22: 2 + RANGE_LIMIT_23: 2 + RANGE_LIMIT_24: 2 + RANGE_LIMIT_25: 2 + RANGE_LIMIT_26: 2 + RANGE_LIMIT_27: 2 + RANGE_LIMIT_28: 2 + RANGE_LIMIT_29: 2 + RANGE_LIMIT_30: 2 + RANGE_LIMIT_31: 2 + RANGE_ATTR_0: 2 + RANGE_ATTR_1: 2 + RANGE_ATTR_2: 2 + RANGE_ATTR_3: 2 + RANGE_ATTR_4: 2 + RANGE_ATTR_5: 2 + RANGE_ATTR_6: 2 + RANGE_ATTR_7: 2 + RANGE_ATTR_8: 2 + RANGE_ATTR_9: 2 + RANGE_ATTR_10: 2 + RANGE_ATTR_11: 2 + RANGE_ATTR_12: 2 + RANGE_ATTR_13: 2 + RANGE_ATTR_14: 2 + RANGE_ATTR_15: 2 + RANGE_ATTR_16: 2 + RANGE_ATTR_17: 2 + RANGE_ATTR_18: 2 + RANGE_ATTR_19: 2 + RANGE_ATTR_20: 2 + RANGE_ATTR_21: 2 + RANGE_ATTR_22: 2 + RANGE_ATTR_23: 2 + RANGE_ATTR_24: 2 + RANGE_ATTR_25: 2 + RANGE_ATTR_26: 2 + RANGE_ATTR_27: 2 + RANGE_ATTR_28: 2 + RANGE_ATTR_29: 2 + RANGE_ATTR_30: 2 + RANGE_ATTR_31: 2 + RANGE_RACL_POLICY_SHADOWED_0: 2 + RANGE_RACL_POLICY_SHADOWED_1: 2 + RANGE_RACL_POLICY_SHADOWED_2: 2 + RANGE_RACL_POLICY_SHADOWED_3: 2 + RANGE_RACL_POLICY_SHADOWED_4: 2 + RANGE_RACL_POLICY_SHADOWED_5: 2 + RANGE_RACL_POLICY_SHADOWED_6: 2 + RANGE_RACL_POLICY_SHADOWED_7: 2 + RANGE_RACL_POLICY_SHADOWED_8: 2 + RANGE_RACL_POLICY_SHADOWED_9: 2 + RANGE_RACL_POLICY_SHADOWED_10: 2 + RANGE_RACL_POLICY_SHADOWED_11: 2 + RANGE_RACL_POLICY_SHADOWED_12: 2 + RANGE_RACL_POLICY_SHADOWED_13: 2 + RANGE_RACL_POLICY_SHADOWED_14: 2 + RANGE_RACL_POLICY_SHADOWED_15: 2 + RANGE_RACL_POLICY_SHADOWED_16: 2 + RANGE_RACL_POLICY_SHADOWED_17: 2 + RANGE_RACL_POLICY_SHADOWED_18: 2 + RANGE_RACL_POLICY_SHADOWED_19: 2 + RANGE_RACL_POLICY_SHADOWED_20: 2 + RANGE_RACL_POLICY_SHADOWED_21: 2 + RANGE_RACL_POLICY_SHADOWED_22: 2 + RANGE_RACL_POLICY_SHADOWED_23: 2 + RANGE_RACL_POLICY_SHADOWED_24: 2 + RANGE_RACL_POLICY_SHADOWED_25: 2 + RANGE_RACL_POLICY_SHADOWED_26: 2 + RANGE_RACL_POLICY_SHADOWED_27: 2 + RANGE_RACL_POLICY_SHADOWED_28: 2 + RANGE_RACL_POLICY_SHADOWED_29: 2 + RANGE_RACL_POLICY_SHADOWED_30: 2 + RANGE_RACL_POLICY_SHADOWED_31: 2 + } + window_mapping: {} + range_mapping: [] + } + } + domain: + [ + "0" + ] + } + ] + memory: [] + port: + [ + { + name: ast + inter_signal_list: + [ + { + struct: lc_tx + type: uni + name: lc_dft_en + act: req + package: lc_ctrl_pkg + inst_name: ast + width: 1 + default: "" + top_signame: lc_ctrl_lc_dft_en + index: -1 + external: true + conn_type: true + } + { + struct: lc_tx + type: uni + name: lc_hw_debug_en + act: req + package: lc_ctrl_pkg + inst_name: ast + width: 1 + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + external: true + conn_type: true + } + { + struct: ast_obs_ctrl + type: uni + name: obs_ctrl + act: rcv + package: ast_pkg + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_obs_ctrl + index: -1 + external: true + conn_type: true + } + ] + } + ] + inter_module: + { + connect: + { + ast.obs_ctrl: + [ + otp_macro.obs_ctrl + ] + alert_handler.crashdump: + [ + rstmgr_aon.alert_dump + ] + alert_handler.esc_rx: + [ + lc_ctrl.esc_scrap_state0_rx + lc_ctrl.esc_scrap_state1_rx + pwrmgr_aon.esc_rst_rx + ] + alert_handler.esc_tx: + [ + lc_ctrl.esc_scrap_state0_tx + lc_ctrl.esc_scrap_state1_tx + pwrmgr_aon.esc_rst_tx + ] + csrng.csrng_cmd: + [ + edn0.csrng_cmd + edn1.csrng_cmd + ] + csrng.entropy_src_hw_if: + [ + entropy_src.entropy_src_hw_if + ] + csrng.cs_aes_halt: + [ + entropy_src.cs_aes_halt + ] + otp_ctrl.sram_otp_key: + [ + sram_ctrl_main.sram_otp_key + sram_ctrl_ret_aon.sram_otp_key + sram_ctrl_mbox.sram_otp_key + ] + pwrmgr_aon.pwr_rst: + [ + rstmgr_aon.pwr + ] + pwrmgr_aon.pwr_clk: + [ + clkmgr_aon.pwr + ] + pwrmgr_aon.pwr_otp: + [ + otp_ctrl.pwr_otp + ] + pwrmgr_aon.pwr_lc: + [ + lc_ctrl.pwr_lc + ] + pwrmgr_aon.strap: + [ + gpio.strap_en + ] + pwrmgr_aon.low_power: + [ + pinmux_aon.sleep_en + aon_timer_aon.sleep_mode + ] + pwrmgr_aon.rom_ctrl: + [ + rom_ctrl0.pwrmgr_data + rom_ctrl1.pwrmgr_data + soc_dbg_ctrl.continue_cpu_boot + ] + pwrmgr_aon.boot_status: + [ + soc_dbg_ctrl.boot_status + ] + keymgr_dpe.rom_digest: + [ + rom_ctrl0.keymgr_data + rom_ctrl1.keymgr_data + ] + dma.lsio_trigger: + [ + soc_proxy.dma_lsio_trigger + ] + i2c0.lsio_trigger: + [ + soc_proxy.i2c_lsio_trigger + ] + spi_host0.lsio_trigger: + [ + soc_proxy.spi_host_lsio_trigger + ] + uart0.lsio_trigger: + [ + soc_proxy.uart_lsio_trigger + ] + lc_ctrl.lc_flash_rma_req: + [ + otbn.lc_rma_req + ] + otbn.lc_rma_ack: + [ + lc_ctrl.lc_flash_rma_ack + ] + edn0.edn: + [ + keymgr_dpe.edn + otp_ctrl.edn + kmac.entropy + alert_handler.edn + aes.edn + otbn.edn_urnd + ] + edn1.edn: + [ + otbn.edn_rnd + ] + otp_ctrl.otbn_otp_key: + [ + otbn.otbn_otp_key + ] + otp_ctrl.otp_keymgr_key: + [ + keymgr_dpe.otp_key + ] + keymgr_dpe.aes_key: + [ + aes.keymgr_key + ] + keymgr_dpe.kmac_key: + [ + kmac.keymgr_key + ] + keymgr_dpe.otbn_key: + [ + otbn.keymgr_key + ] + kmac.app: + [ + keymgr_dpe.kmac_data + lc_ctrl.kmac_data + rom_ctrl0.kmac_data + rom_ctrl1.kmac_data + ] + kmac.en_masking: + [ + keymgr_dpe.kmac_en_masking + ] + clkmgr_aon.idle: + [ + aes.idle + hmac.idle + kmac.idle + otbn.idle + ] + otp_ctrl.otp_lc_data: + [ + lc_ctrl.otp_lc_data + ] + lc_ctrl.lc_otp_program: + [ + otp_ctrl.lc_otp_program + ] + lc_ctrl.lc_otp_vendor_test: + [ + otp_macro.test + ] + lc_ctrl.lc_keymgr_div: + [ + keymgr_dpe.lc_keymgr_div + ] + lc_ctrl.lc_raw_test_rma: + [ + soc_dbg_ctrl.lc_raw_test_rma + ] + lc_ctrl.lc_dft_en: + [ + otp_macro.lc_dft_en + ast.lc_dft_en + pwrmgr_aon.lc_dft_en + soc_dbg_ctrl.lc_dft_en + ] + lc_ctrl.lc_hw_debug_en: + [ + sram_ctrl_main.lc_hw_debug_en + ast.lc_hw_debug_en + csrng.lc_hw_debug_en + clkmgr_aon.lc_hw_debug_en + pwrmgr_aon.lc_hw_debug_en + soc_dbg_ctrl.lc_hw_debug_en + ] + lc_ctrl.lc_keymgr_en: + [ + keymgr_dpe.lc_keymgr_en + ] + lc_ctrl.lc_escalate_en: + [ + aes.lc_escalate_en + kmac.lc_escalate_en + otbn.lc_escalate_en + otp_ctrl.lc_escalate_en + sram_ctrl_main.lc_escalate_en + sram_ctrl_ret_aon.lc_escalate_en + sram_ctrl_mbox.lc_escalate_en + aon_timer_aon.lc_escalate_en + ] + lc_ctrl.lc_check_byp_en: + [ + otp_ctrl.lc_check_byp_en + ] + lc_ctrl.lc_clk_byp_req: + [ + clkmgr_aon.lc_clk_byp_req + ] + lc_ctrl.lc_clk_byp_ack: + [ + clkmgr_aon.lc_clk_byp_ack + ] + lc_ctrl.lc_creator_seed_sw_rw_en: + [ + otp_ctrl.lc_creator_seed_sw_rw_en + ] + lc_ctrl.lc_owner_seed_sw_rw_en: + [ + otp_ctrl.lc_owner_seed_sw_rw_en + ] + lc_ctrl.lc_seed_hw_rd_en: + [ + otp_ctrl.lc_seed_hw_rd_en + ] + otp_ctrl.otp_macro: + [ + otp_macro.otp + ] + spi_device.passthrough: + [ + spi_host0.passthrough + ] + rstmgr_aon.sw_rst_req: + [ + pwrmgr_aon.sw_rst_req + ] + soc_proxy.dma_tl_h2d: + [ + dma.ctn_tl_h2d + ] + soc_proxy.dma_tl_d2h: + [ + dma.ctn_tl_d2h + ] + soc_proxy.ctn_tl_h2d: + [ + ac_range_check.ctn_tl_h2d + ] + soc_proxy.ctn_tl_d2h: + [ + ac_range_check.ctn_tl_d2h + ] + pwrmgr_aon.wakeups: + [ + pinmux_aon.pin_wkup_req + aon_timer_aon.wkup_req + soc_proxy.wkup_internal_req + soc_proxy.wkup_external_req + ] + pwrmgr_aon.rstreqs: + [ + aon_timer_aon.aon_timer_rst_req + soc_proxy.rst_req_external + ] + main.tl_peri: + [ + peri.tl_main + ] + soc_proxy.ctn_tl: + [ + main.tl_soc_proxy__ctn + ] + hmac.tl: + [ + main.tl_hmac + ] + kmac.tl: + [ + main.tl_kmac + ] + aes.tl: + [ + main.tl_aes + ] + otbn.tl: + [ + main.tl_otbn + ] + keymgr_dpe.tl: + [ + main.tl_keymgr_dpe + ] + sram_ctrl_main.ram_tl: + [ + main.tl_sram_ctrl_main__ram + ] + sram_ctrl_mbox.ram_tl: + [ + main.tl_sram_ctrl_mbox__ram + ] + main.tl_dma__host: + [ + dma.host_tl_h + ] + main.tl_mbx0__sram: + [ + mbx0.sram_tl_h + ] + main.tl_mbx1__sram: + [ + mbx1.sram_tl_h + ] + main.tl_mbx2__sram: + [ + mbx2.sram_tl_h + ] + main.tl_mbx3__sram: + [ + mbx3.sram_tl_h + ] + main.tl_mbx4__sram: + [ + mbx4.sram_tl_h + ] + main.tl_mbx5__sram: + [ + mbx5.sram_tl_h + ] + main.tl_mbx6__sram: + [ + mbx6.sram_tl_h + ] + main.tl_mbx_jtag__sram: + [ + mbx_jtag.sram_tl_h + ] + main.tl_mbx_pcie0__sram: + [ + mbx_pcie0.sram_tl_h + ] + main.tl_mbx_pcie1__sram: + [ + mbx_pcie1.sram_tl_h + ] + uart0.tl: + [ + peri.tl_uart0 + ] + i2c0.tl: + [ + peri.tl_i2c0 + ] + gpio.tl: + [ + peri.tl_gpio + ] + spi_host0.tl: + [ + peri.tl_spi_host0 + ] + spi_device.tl: + [ + peri.tl_spi_device + ] + pwrmgr_aon.tl: + [ + peri.tl_pwrmgr_aon + ] + rstmgr_aon.tl: + [ + peri.tl_rstmgr_aon + ] + clkmgr_aon.tl: + [ + peri.tl_clkmgr_aon + ] + pinmux_aon.tl: + [ + peri.tl_pinmux_aon + ] + otp_ctrl.core_tl: + [ + peri.tl_otp_ctrl__core + ] + otp_macro.prim_tl: + [ + peri.tl_otp_macro__prim + ] + lc_ctrl.regs_tl: + [ + peri.tl_lc_ctrl__regs + ] + alert_handler.tl: + [ + peri.tl_alert_handler + ] + sram_ctrl_ret_aon.regs_tl: + [ + peri.tl_sram_ctrl_ret_aon__regs + ] + sram_ctrl_ret_aon.ram_tl: + [ + peri.tl_sram_ctrl_ret_aon__ram + ] + aon_timer_aon.tl: + [ + peri.tl_aon_timer_aon + ] + soc_dbg_ctrl.core_tl: + [ + peri.tl_soc_dbg_ctrl__core + ] + mbx0.soc_tl_d: + [ + mbx.tl_mbx0__soc + ] + mbx1.soc_tl_d: + [ + mbx.tl_mbx1__soc + ] + mbx2.soc_tl_d: + [ + mbx.tl_mbx2__soc + ] + mbx3.soc_tl_d: + [ + mbx.tl_mbx3__soc + ] + mbx4.soc_tl_d: + [ + mbx.tl_mbx4__soc + ] + mbx5.soc_tl_d: + [ + mbx.tl_mbx5__soc + ] + mbx6.soc_tl_d: + [ + mbx.tl_mbx6__soc + ] + mbx_pcie0.soc_tl_d: + [ + mbx.tl_mbx_pcie0__soc + ] + mbx_pcie1.soc_tl_d: + [ + mbx.tl_mbx_pcie1__soc + ] + racl_ctrl.tl: + [ + mbx.tl_racl_ctrl + ] + ac_range_check.tl: + [ + mbx.tl_ac_range_check + ] + mbx_jtag.soc_tl_d: + [ + dbg.tl_mbx_jtag__soc + ] + lc_ctrl.dmi_tl: + [ + dbg.tl_lc_ctrl__dmi + ] + soc_dbg_ctrl.jtag_tl: + [ + dbg.tl_soc_dbg_ctrl__jtag + ] + racl_ctrl.racl_policies: + [ + mbx0.racl_policies + mbx1.racl_policies + mbx2.racl_policies + mbx3.racl_policies + mbx4.racl_policies + mbx5.racl_policies + mbx6.racl_policies + mbx_jtag.racl_policies + mbx_pcie0.racl_policies + mbx_pcie1.racl_policies + ac_range_check.racl_policies + ] + racl_ctrl.racl_error: + [ + mbx0.racl_error + mbx1.racl_error + mbx2.racl_error + mbx3.racl_error + mbx4.racl_error + mbx5.racl_error + mbx6.racl_error + mbx_jtag.racl_error + mbx_pcie0.racl_error + mbx_pcie1.racl_error + ac_range_check.racl_error + ] + } + top: + [ + clkmgr_aon.clocks + clkmgr_aon.cg_en + rstmgr_aon.resets + rstmgr_aon.rst_en + otp_ctrl.otp_broadcast + csrng.otp_en_csrng_sw_app_read + soc_dbg_ctrl.soc_dbg_state + lc_ctrl.otp_device_id + lc_ctrl.otp_manuf_state + keymgr_dpe.otp_device_id + sram_ctrl_main.otp_en_sram_ifetch + ] + external: + { + ast.lc_dft_en: "" + ast.lc_hw_debug_en: "" + ast.obs_ctrl: obs_ctrl + rom_ctrl0.rom_cfg: rom_ctrl0_cfg + rom_ctrl1.rom_cfg: rom_ctrl1_cfg + i2c0.ram_cfg: i2c_ram_1p_cfg + i2c0.ram_cfg_rsp: i2c_ram_1p_cfg_rsp + sram_ctrl_ret_aon.cfg: sram_ctrl_ret_aon_ram_1p_cfg + sram_ctrl_ret_aon.cfg_rsp: sram_ctrl_ret_aon_ram_1p_cfg_rsp + sram_ctrl_main.cfg: sram_ctrl_main_ram_1p_cfg + sram_ctrl_main.cfg_rsp: sram_ctrl_main_ram_1p_cfg_rsp + sram_ctrl_mbox.cfg: sram_ctrl_mbox_ram_1p_cfg + sram_ctrl_mbox.cfg_rsp: sram_ctrl_mbox_ram_1p_cfg_rsp + otbn.ram_cfg_imem: otbn_imem_ram_1p_cfg + otbn.ram_cfg_rsp_imem: otbn_imem_ram_1p_cfg_rsp + otbn.ram_cfg_dmem: otbn_dmem_ram_1p_cfg + otbn.ram_cfg_rsp_dmem: otbn_dmem_ram_1p_cfg_rsp + rv_plic.msip: no_ibex_msip + rv_plic.irq: no_ibex_irq + spi_device.ram_cfg_sys2spi: spi_device_ram_2p_cfg_sys2spi + spi_device.ram_cfg_rsp_sys2spi: spi_device_ram_2p_cfg_rsp_sys2spi + spi_device.ram_cfg_rsp_spi2sys: spi_device_ram_2p_cfg_rsp_spi2sys + spi_device.ram_cfg_spi2sys: spi_device_ram_2p_cfg_spi2sys + pwrmgr_aon.boot_status: pwrmgr_boot_status + clkmgr_aon.jitter_en: clk_main_jitter_en + clkmgr_aon.io_clk_byp_req: io_clk_byp_req + clkmgr_aon.io_clk_byp_ack: io_clk_byp_ack + clkmgr_aon.all_clk_byp_req: all_clk_byp_req + clkmgr_aon.all_clk_byp_ack: all_clk_byp_ack + clkmgr_aon.hi_speed_sel: hi_speed_sel + clkmgr_aon.div_step_down_req: div_step_down_req + clkmgr_aon.calib_rdy: calib_rdy + dma.sys: dma_sys + entropy_src.entropy_src_rng_enable: es_rng_enable + entropy_src.entropy_src_rng_valid: es_rng_valid + entropy_src.entropy_src_rng_bits: es_rng_bit + entropy_src.rng_fips: es_rng_fips + mbx.tl_mbx: mbx_tl + mbx0.doe_intr: mbx0_doe_intr + mbx0.doe_intr_en: mbx0_doe_intr_en + mbx0.doe_intr_support: mbx0_doe_intr_support + mbx0.doe_async_msg_support: mbx0_doe_async_msg_support + mbx1.doe_intr: mbx1_doe_intr + mbx1.doe_intr_en: mbx1_doe_intr_en + mbx1.doe_intr_support: mbx1_doe_intr_support + mbx1.doe_async_msg_support: mbx1_doe_async_msg_support + mbx2.doe_intr: mbx2_doe_intr + mbx2.doe_intr_en: mbx2_doe_intr_en + mbx2.doe_intr_support: mbx2_doe_intr_support + mbx2.doe_async_msg_support: mbx2_doe_async_msg_support + mbx3.doe_intr: mbx3_doe_intr + mbx3.doe_intr_en: mbx3_doe_intr_en + mbx3.doe_intr_support: mbx3_doe_intr_support + mbx3.doe_async_msg_support: mbx3_doe_async_msg_support + mbx4.doe_intr: mbx4_doe_intr + mbx4.doe_intr_en: mbx4_doe_intr_en + mbx4.doe_intr_support: mbx4_doe_intr_support + mbx4.doe_async_msg_support: mbx4_doe_async_msg_support + mbx5.doe_intr: mbx5_doe_intr + mbx5.doe_intr_en: mbx5_doe_intr_en + mbx5.doe_intr_support: mbx5_doe_intr_support + mbx5.doe_async_msg_support: mbx5_doe_async_msg_support + mbx6.doe_intr: mbx6_doe_intr + mbx6.doe_intr_en: mbx6_doe_intr_en + mbx6.doe_intr_support: mbx6_doe_intr_support + mbx6.doe_async_msg_support: mbx6_doe_async_msg_support + mbx_jtag.doe_intr: mbx_jtag_doe_intr + mbx_jtag.doe_intr_en: mbx_jtag_doe_intr_en + mbx_jtag.doe_intr_support: mbx_jtag_doe_intr_support + mbx_jtag.doe_async_msg_support: mbx_jtag_doe_async_msg_support + mbx_pcie0.doe_intr: mbx_pcie0_doe_intr + mbx_pcie0.doe_intr_en: mbx_pcie0_doe_intr_en + mbx_pcie0.doe_intr_support: mbx_pcie0_doe_intr_support + mbx_pcie0.doe_async_msg_support: mbx_pcie0_doe_async_msg_support + mbx_pcie1.doe_intr: mbx_pcie1_doe_intr + mbx_pcie1.doe_intr_en: mbx_pcie1_doe_intr_en + mbx_pcie1.doe_intr_support: mbx_pcie1_doe_intr_support + mbx_pcie1.doe_async_msg_support: mbx_pcie1_doe_async_msg_support + dbg.tl_dbg: dbg_tl + peri.tl_ast: ast_tl + pwrmgr_aon.pwr_ast: pwrmgr_ast + otp_macro.pwr_seq: "" + otp_macro.pwr_seq_h: "" + otp_macro.ext_voltage_h: otp_ext_voltage_h + otp_macro.otp_obs: otp_obs + otp_macro.cfg: otp_cfg + otp_macro.cfg_rsp: otp_cfg_rsp + rstmgr_aon.por_n: por_n + soc_proxy.misc_tl_h2d: ctn_misc_tl_h2d + soc_proxy.misc_tl_d2h: ctn_misc_tl_d2h + soc_proxy.soc_fatal_alert: soc_fatal_alert + soc_proxy.soc_recov_alert: soc_recov_alert + soc_proxy.soc_wkup_async: soc_wkup_async + soc_proxy.soc_rst_req_async: soc_rst_req_async + soc_proxy.soc_intr_async: soc_intr_async + soc_proxy.soc_lsio_trigger: soc_lsio_trigger + soc_proxy.soc_gpi_async: soc_gpi_async + soc_proxy.soc_gpo_async: soc_gpo_async + soc_proxy.integrator_id: integrator_id + spi_device.sck_monitor: sck_monitor + soc_dbg_ctrl.soc_dbg_policy_bus: soc_dbg_policy_bus + soc_dbg_ctrl.halt_cpu_boot: debug_halt_cpu_boot + racl_ctrl.racl_policies: racl_policies + racl_ctrl.racl_error_external: racl_error + ac_range_check.range_check_overwrite: ac_range_check_overwrite + ac_range_check.ctn_filtered_tl_h2d: ctn_tl_h2d + ac_range_check.ctn_filtered_tl_d2h: ctn_tl_d2h + } + } + xbar: + [ + { + name: main + clock_srcs: + { + clk_main_i: main + clk_fixed_i: io_div4 + } + clock_group: infra + reset: rst_main_ni + reset_connections: + { + rst_main_ni: + { + name: lc + domain: "0" + } + rst_fixed_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_main_i: clkmgr_aon_clocks.clk_main_infra + clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + dma.host: + [ + sram_ctrl_main.ram + sram_ctrl_mbox.ram + aes + hmac + otbn + keymgr_dpe + kmac + soc_proxy.ctn + peri + ] + mbx0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx1.sram: + [ + sram_ctrl_mbox.ram + ] + mbx2.sram: + [ + sram_ctrl_mbox.ram + ] + mbx3.sram: + [ + sram_ctrl_mbox.ram + ] + mbx4.sram: + [ + sram_ctrl_mbox.ram + ] + mbx5.sram: + [ + sram_ctrl_mbox.ram + ] + mbx6.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_jtag.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie1.sram: + [ + sram_ctrl_mbox.ram + ] + } + nodes: + [ + { + name: peri + type: device + clock: clk_fixed_i + reset: rst_fixed_ni + req_fifo_pass: false + rsp_fifo_pass: false + xbar: true + stub: false + pipeline: true + addr_space: hart + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x800000 + } + ] + } + { + name: soc_proxy.ctn + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: soc_proxy + addr_range: + [ + { + base_addrs: + { + hart: 0x40000000 + } + size_byte: 0x40000000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: hmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: hmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21110000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: kmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: kmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21120000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: aes + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: aes + addr_range: + [ + { + base_addrs: + { + hart: 0x21100000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: otbn + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: otbn + addr_range: + [ + { + base_addrs: + { + hart: 0x21130000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: keymgr_dpe + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: keymgr_dpe + addr_range: + [ + { + base_addrs: + { + hart: 0x21140000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: sram_ctrl_main.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x10000000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_mbox.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x11000000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: dma.host + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx2.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx3.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx4.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx5.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx6.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_jtag.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_main_i + type: xbar + inter_signal_list: + [ + { + name: tl_dma__host + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_dma__host + index: -1 + } + { + name: tl_mbx0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx0__sram + index: -1 + } + { + name: tl_mbx1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx1__sram + index: -1 + } + { + name: tl_mbx2__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx2__sram + index: -1 + } + { + name: tl_mbx3__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx3__sram + index: -1 + } + { + name: tl_mbx4__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx4__sram + index: -1 + } + { + name: tl_mbx5__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx5__sram + index: -1 + } + { + name: tl_mbx6__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx6__sram + index: -1 + } + { + name: tl_mbx_jtag__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx_jtag__sram + index: -1 + } + { + name: tl_mbx_pcie0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie0__sram + index: -1 + } + { + name: tl_mbx_pcie1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie1__sram + index: -1 + } + { + name: tl_peri + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_peri + index: -1 + } + { + name: tl_soc_proxy__ctn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: soc_proxy_ctn_tl + index: -1 + } + { + name: tl_hmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: hmac_tl + index: -1 + } + { + name: tl_kmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: kmac_tl + index: -1 + } + { + name: tl_aes + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: aes_tl + index: -1 + } + { + name: tl_otbn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: otbn_tl + index: -1 + } + { + name: tl_keymgr_dpe + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: keymgr_dpe_tl + index: -1 + } + { + name: tl_sram_ctrl_main__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + { + name: tl_sram_ctrl_mbox__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + ] + } + { + name: peri + clock_srcs: + { + clk_peri_i: io_div4 + } + clock_group: infra + reset: rst_peri_ni + reset_connections: + { + rst_peri_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + main: + [ + uart0 + i2c0 + gpio + spi_host0 + spi_device + pwrmgr_aon + rstmgr_aon + clkmgr_aon + pinmux_aon + otp_ctrl.core + otp_macro.prim + lc_ctrl.regs + alert_handler + ast + sram_ctrl_ret_aon.ram + sram_ctrl_ret_aon.regs + aon_timer_aon + soc_dbg_ctrl.core + ] + } + nodes: + [ + { + name: main + type: host + addr_space: hart + clock: clk_peri_i + reset: rst_peri_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: uart0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: uart + addr_range: + [ + { + base_addrs: + { + hart: 0x30010000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: i2c0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: i2c + addr_range: + [ + { + base_addrs: + { + hart: 0x30080000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: gpio + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: gpio + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_host0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_host + addr_range: + [ + { + base_addrs: + { + hart: 0x30300000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_device + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_device + addr_range: + [ + { + base_addrs: + { + hart: 0x30310000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pwrmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pwrmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30400000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: rstmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: rstmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30410000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: clkmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: clkmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30420000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pinmux_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pinmux + addr_range: + [ + { + base_addrs: + { + hart: 0x30460000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_ctrl.core + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30130000 + } + size_byte: 0x8000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_macro.prim + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_macro + addr_range: + [ + { + base_addrs: + { + hart: 0x30140000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: lc_ctrl.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: lc_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30150000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: alert_handler + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: alert_handler + addr_range: + [ + { + base_addrs: + { + hart: 0x30160000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30500000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.ram + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30600000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: aon_timer_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: aon_timer + addr_range: + [ + { + base_addrs: + { + hart: 0x30470000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: ast + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: ast + addr_range: + [ + { + base_addrs: + { + hart: 0x30480000 + } + size_byte: 0x400 + } + ] + xbar: false + stub: true + req_fifo_pass: true + } + { + name: soc_dbg_ctrl.core + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: soc_dbg_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30170000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_peri_i + type: xbar + inter_signal_list: + [ + { + name: tl_main + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: peri + width: 1 + default: "" + top_signame: main_tl_peri + index: -1 + } + { + name: tl_uart0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: uart0_tl + index: -1 + } + { + name: tl_i2c0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: i2c0_tl + index: -1 + } + { + name: tl_gpio + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: gpio_tl + index: -1 + } + { + name: tl_spi_host0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: spi_host0_tl + index: -1 + } + { + name: tl_spi_device + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: spi_device_tl + index: -1 + } + { + name: tl_pwrmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: pwrmgr_aon_tl + index: -1 + } + { + name: tl_rstmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: rstmgr_aon_tl + index: -1 + } + { + name: tl_clkmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: clkmgr_aon_tl + index: -1 + } + { + name: tl_pinmux_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: pinmux_aon_tl + index: -1 + } + { + name: tl_otp_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: otp_ctrl_core_tl + index: -1 + } + { + name: tl_otp_macro__prim + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: otp_macro_prim_tl + index: -1 + } + { + name: tl_lc_ctrl__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: tl_alert_handler + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: alert_handler_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + { + name: tl_aon_timer_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: aon_timer_aon_tl + index: -1 + } + { + name: tl_ast + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + external: true + top_signame: ast_tl + conn_type: false + index: -1 + } + { + name: tl_soc_dbg_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: soc_dbg_ctrl_core_tl + index: -1 + } + ] + } + { + name: mbx + clock_srcs: + { + clk_mbx_i: main + } + clock_group: infra + reset: rst_mbx_ni + reset_connections: + { + rst_mbx_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_mbx_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + connections: + { + mbx: + [ + mbx0.soc + mbx1.soc + mbx2.soc + mbx3.soc + mbx4.soc + mbx5.soc + mbx6.soc + mbx_pcie0.soc + mbx_pcie1.soc + racl_ctrl + ac_range_check + ] + } + nodes: + [ + { + name: mbx + type: host + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx0.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx1.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465100 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx2.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx3.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465300 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx4.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465400 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx5.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465500 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx6.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1496000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie0.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1460100 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie1.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1460200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: racl_ctrl + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: racl_ctrl + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1461f00 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: ac_range_check + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: ac_range_check + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1464000 + } + size_byte: 0x400 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + soc_mbx + ] + clock: clk_mbx_i + type: xbar + inter_signal_list: + [ + { + name: tl_mbx + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: mbx + width: 1 + default: "" + external: true + top_signame: mbx_tl + conn_type: false + index: -1 + } + { + name: tl_mbx0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx0_soc_tl_d + index: -1 + } + { + name: tl_mbx1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx1_soc_tl_d + index: -1 + } + { + name: tl_mbx2__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx2_soc_tl_d + index: -1 + } + { + name: tl_mbx3__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx3_soc_tl_d + index: -1 + } + { + name: tl_mbx4__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx4_soc_tl_d + index: -1 + } + { + name: tl_mbx5__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx5_soc_tl_d + index: -1 + } + { + name: tl_mbx6__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx6_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx_pcie0_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx_pcie1_soc_tl_d + index: -1 + } + { + name: tl_racl_ctrl + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: racl_ctrl_tl + index: -1 + } + { + name: tl_ac_range_check + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: ac_range_check_tl + index: -1 + } + ] + } + { + name: dbg + clock_srcs: + { + clk_dbg_i: main + clk_peri_i: io_div4 + } + clock_group: infra + reset: rst_dbg_ni + reset_connections: + { + rst_dbg_ni: + { + name: lc + domain: "0" + } + rst_peri_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_dbg_i: clkmgr_aon_clocks.clk_main_infra + clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + dbg: + [ + mbx_jtag.soc + lc_ctrl.dmi + soc_dbg_ctrl.jtag + ] + } + nodes: + [ + { + name: dbg + type: host + addr_space: soc_dbg + clock: clk_dbg_i + reset: rst_dbg_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_jtag.soc + type: device + clock: clk_dbg_i + reset: rst_dbg_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x2200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: lc_ctrl.dmi + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: lc_ctrl + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x3000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: soc_dbg_ctrl.jtag + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: soc_dbg_ctrl + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x2300 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + soc_dbg + ] + clock: clk_dbg_i + type: xbar + inter_signal_list: + [ + { + name: tl_dbg + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: dbg + width: 1 + default: "" + external: true + top_signame: dbg_tl + conn_type: false + index: -1 + } + { + name: tl_mbx_jtag__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: dbg + width: 1 + default: "" + top_signame: mbx_jtag_soc_tl_d + index: -1 + } + { + name: tl_lc_ctrl__dmi + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: dbg + width: 1 + default: "" + top_signame: lc_ctrl_dmi_tl + index: -1 + } + { + name: tl_soc_dbg_ctrl__jtag + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: dbg + width: 1 + default: "" + top_signame: soc_dbg_ctrl_jtag_tl + index: -1 + } + ] + } + ] + pinout: + { + banks: + [ + VIO + ] + pads: + [ + { + name: POR_N + type: InputStd + bank: VIO + connection: manual + desc: System reset + idx: 0 + port_type: inout + } + { + name: JTAG_TCK + type: InputStd + bank: VIO + connection: manual + desc: JTAG TCK signal + idx: 1 + port_type: inout + } + { + name: JTAG_TMS + type: InputStd + bank: VIO + connection: manual + desc: JTAG TMS signal + idx: 2 + port_type: inout + } + { + name: JTAG_TDI + type: InputStd + bank: VIO + connection: manual + desc: JTAG TDI signal + idx: 3 + port_type: inout + } + { + name: JTAG_TDO + type: BidirStd + bank: VIO + connection: manual + desc: JTAG TDO signal + idx: 4 + port_type: inout + } + { + name: JTAG_TRST_N + type: InputStd + bank: VIO + connection: manual + desc: JTAG TRST_N signal + idx: 5 + port_type: inout + } + { + name: OTP_EXT_VOLT + type: AnalogIn1 + bank: VIO + connection: manual + desc: OTP external voltage input + idx: 6 + port_type: inout + } + { + name: SPI_HOST_D0 + type: BidirStd + bank: VIO + connection: direct + desc: SPI host data + idx: 7 + port_type: inout + } + { + name: SPI_HOST_D1 + type: BidirStd + bank: VIO + connection: direct + desc: SPI host data + idx: 8 + port_type: inout + } + { + name: SPI_HOST_D2 + type: BidirStd + bank: VIO + connection: direct + desc: SPI host data + idx: 9 + port_type: inout + } + { + name: SPI_HOST_D3 + type: BidirStd + bank: VIO + connection: direct + desc: SPI host data + idx: 10 + port_type: inout + } + { + name: SPI_HOST_CLK + type: BidirStd + bank: VIO + connection: direct + desc: SPI host clock + idx: 11 + port_type: inout + } + { + name: SPI_HOST_CS_L + type: BidirStd + bank: VIO + connection: direct + desc: SPI host chip select + idx: 12 + port_type: inout + } + { + name: SPI_DEV_D0 + type: BidirStd + bank: VIO + connection: direct + desc: SPI device data + idx: 13 + port_type: inout + } + { + name: SPI_DEV_D1 + type: BidirStd + bank: VIO + connection: direct + desc: SPI device data + idx: 14 + port_type: inout + } + { + name: SPI_DEV_D2 + type: BidirStd + bank: VIO + connection: direct + desc: SPI device data + idx: 15 + port_type: inout + } + { + name: SPI_DEV_D3 + type: BidirStd + bank: VIO + connection: direct + desc: SPI device data + idx: 16 + port_type: inout + } + { + name: SPI_DEV_CLK + type: InputStd + bank: VIO + connection: direct + desc: SPI device clock + idx: 17 + port_type: inout + } + { + name: SPI_DEV_CS_L + type: InputStd + bank: VIO + connection: direct + desc: SPI device chip select + idx: 18 + port_type: inout + } + { + name: SPI_DEV_TPM_CS_L + type: InputStd + bank: VIO + connection: direct + desc: SPI device TPM chip select + idx: 19 + port_type: inout + } + { + name: UART_RX + type: InputStd + bank: VIO + connection: direct + desc: UART receive + idx: 20 + port_type: inout + } + { + name: UART_TX + type: BidirStd + bank: VIO + connection: direct + desc: UART transmit + idx: 21 + port_type: inout + } + { + name: I2C_SCL + type: BidirStd + bank: VIO + connection: direct + desc: I2C clock + idx: 22 + port_type: inout + } + { + name: I2C_SDA + type: BidirStd + bank: VIO + connection: direct + desc: I2C data + idx: 23 + port_type: inout + } + { + name: GPIO0 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 24 + port_type: inout + } + { + name: GPIO1 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 25 + port_type: inout + } + { + name: GPIO2 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 26 + port_type: inout + } + { + name: GPIO3 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 27 + port_type: inout + } + { + name: GPIO4 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 28 + port_type: inout + } + { + name: GPIO5 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 29 + port_type: inout + } + { + name: GPIO6 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 30 + port_type: inout + } + { + name: GPIO7 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 31 + port_type: inout + } + { + name: GPIO8 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 32 + port_type: inout + } + { + name: GPIO9 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 33 + port_type: inout + } + { + name: GPIO10 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 34 + port_type: inout + } + { + name: GPIO11 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 35 + port_type: inout + } + { + name: GPIO12 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 36 + port_type: inout + } + { + name: GPIO13 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 37 + port_type: inout + } + { + name: GPIO14 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 38 + port_type: inout + } + { + name: GPIO15 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 39 + port_type: inout + } + { + name: GPIO16 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 40 + port_type: inout + } + { + name: GPIO17 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 41 + port_type: inout + } + { + name: GPIO18 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 42 + port_type: inout + } + { + name: GPIO19 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 43 + port_type: inout + } + { + name: GPIO20 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 44 + port_type: inout + } + { + name: GPIO21 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 45 + port_type: inout + } + { + name: GPIO22 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 46 + port_type: inout + } + { + name: GPIO23 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 47 + port_type: inout + } + { + name: GPIO24 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 48 + port_type: inout + } + { + name: GPIO25 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 49 + port_type: inout + } + { + name: GPIO26 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 50 + port_type: inout + } + { + name: GPIO27 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 51 + port_type: inout + } + { + name: GPIO28 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 52 + port_type: inout + } + { + name: GPIO29 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 53 + port_type: inout + } + { + name: GPIO30 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 54 + port_type: inout + } + { + name: GPIO31 + type: BidirStd + bank: VIO + connection: direct + desc: GPIO pad + idx: 55 + port_type: inout + } + { + name: SOC_GPI0 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 56 + port_type: inout + } + { + name: SOC_GPI1 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 57 + port_type: inout + } + { + name: SOC_GPI2 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 58 + port_type: inout + } + { + name: SOC_GPI3 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 59 + port_type: inout + } + { + name: SOC_GPI4 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 60 + port_type: inout + } + { + name: SOC_GPI5 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 61 + port_type: inout + } + { + name: SOC_GPI6 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 62 + port_type: inout + } + { + name: SOC_GPI7 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 63 + port_type: inout + } + { + name: SOC_GPI8 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 64 + port_type: inout + } + { + name: SOC_GPI9 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 65 + port_type: inout + } + { + name: SOC_GPI10 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 66 + port_type: inout + } + { + name: SOC_GPI11 + type: InputStd + bank: VIO + connection: direct + desc: SoC general purpose input + idx: 67 + port_type: inout + } + { + name: SOC_GPO0 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 68 + port_type: inout + } + { + name: SOC_GPO1 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 69 + port_type: inout + } + { + name: SOC_GPO2 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 70 + port_type: inout + } + { + name: SOC_GPO3 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 71 + port_type: inout + } + { + name: SOC_GPO4 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 72 + port_type: inout + } + { + name: SOC_GPO5 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 73 + port_type: inout + } + { + name: SOC_GPO6 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 74 + port_type: inout + } + { + name: SOC_GPO7 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 75 + port_type: inout + } + { + name: SOC_GPO8 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 76 + port_type: inout + } + { + name: SOC_GPO9 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 77 + port_type: inout + } + { + name: SOC_GPO10 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 78 + port_type: inout + } + { + name: SOC_GPO11 + type: BidirStd + bank: VIO + connection: direct + desc: SoC general purpose output + idx: 79 + port_type: inout + } + { + name: MIO0 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 0 + port_type: inout + } + { + name: MIO1 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 1 + port_type: inout + } + { + name: MIO2 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 2 + port_type: inout + } + { + name: MIO3 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 3 + port_type: inout + } + { + name: MIO4 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 4 + port_type: inout + } + { + name: MIO5 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 5 + port_type: inout + } + { + name: MIO6 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 6 + port_type: inout + } + { + name: MIO7 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 7 + port_type: inout + } + { + name: MIO8 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 8 + port_type: inout + } + { + name: MIO9 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 9 + port_type: inout + } + { + name: MIO10 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 10 + port_type: inout + } + { + name: MIO11 + type: BidirStd + bank: VIO + connection: muxed + desc: Muxed IO pad + idx: 11 + port_type: inout + } + ] + } + pinmux: + { + signals: + [ + { + instance: spi_host0 + port: sck + connection: direct + pad: SPI_HOST_CLK + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: csb + connection: direct + pad: SPI_HOST_CS_L + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: sd[0] + connection: direct + pad: SPI_HOST_D0 + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: sd[1] + connection: direct + pad: SPI_HOST_D1 + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: sd[2] + connection: direct + pad: SPI_HOST_D2 + desc: "" + attr: BidirStd + } + { + instance: spi_host0 + port: sd[3] + connection: direct + pad: SPI_HOST_D3 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: sck + connection: direct + pad: SPI_DEV_CLK + desc: "" + attr: InputStd + } + { + instance: spi_device + port: csb + connection: direct + pad: SPI_DEV_CS_L + desc: "" + attr: InputStd + } + { + instance: spi_device + port: sd[0] + connection: direct + pad: SPI_DEV_D0 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: sd[1] + connection: direct + pad: SPI_DEV_D1 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: sd[2] + connection: direct + pad: SPI_DEV_D2 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: sd[3] + connection: direct + pad: SPI_DEV_D3 + desc: "" + attr: BidirStd + } + { + instance: spi_device + port: tpm_csb + connection: direct + pad: SPI_DEV_TPM_CS_L + desc: "" + attr: InputStd + } + { + instance: uart0 + port: rx + connection: direct + pad: UART_RX + desc: "" + attr: InputStd + } + { + instance: uart0 + port: tx + connection: direct + pad: UART_TX + desc: "" + attr: BidirStd + } + { + instance: i2c0 + port: scl + connection: direct + pad: I2C_SCL + desc: "" + attr: BidirStd + } + { + instance: i2c0 + port: sda + connection: direct + pad: I2C_SDA + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[0] + connection: direct + pad: GPIO0 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[1] + connection: direct + pad: GPIO1 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[2] + connection: direct + pad: GPIO2 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[3] + connection: direct + pad: GPIO3 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[4] + connection: direct + pad: GPIO4 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[5] + connection: direct + pad: GPIO5 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[6] + connection: direct + pad: GPIO6 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[7] + connection: direct + pad: GPIO7 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[8] + connection: direct + pad: GPIO8 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[9] + connection: direct + pad: GPIO9 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[10] + connection: direct + pad: GPIO10 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[11] + connection: direct + pad: GPIO11 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[12] + connection: direct + pad: GPIO12 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[13] + connection: direct + pad: GPIO13 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[14] + connection: direct + pad: GPIO14 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[15] + connection: direct + pad: GPIO15 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[16] + connection: direct + pad: GPIO16 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[17] + connection: direct + pad: GPIO17 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[18] + connection: direct + pad: GPIO18 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[19] + connection: direct + pad: GPIO19 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[20] + connection: direct + pad: GPIO20 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[21] + connection: direct + pad: GPIO21 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[22] + connection: direct + pad: GPIO22 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[23] + connection: direct + pad: GPIO23 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[24] + connection: direct + pad: GPIO24 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[25] + connection: direct + pad: GPIO25 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[26] + connection: direct + pad: GPIO26 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[27] + connection: direct + pad: GPIO27 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[28] + connection: direct + pad: GPIO28 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[29] + connection: direct + pad: GPIO29 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[30] + connection: direct + pad: GPIO30 + desc: "" + attr: BidirStd + } + { + instance: gpio + port: gpio[31] + connection: direct + pad: GPIO31 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpi[0] + connection: direct + pad: SOC_GPI0 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[1] + connection: direct + pad: SOC_GPI1 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[2] + connection: direct + pad: SOC_GPI2 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[3] + connection: direct + pad: SOC_GPI3 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[4] + connection: direct + pad: SOC_GPI4 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[5] + connection: direct + pad: SOC_GPI5 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[6] + connection: direct + pad: SOC_GPI6 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[7] + connection: direct + pad: SOC_GPI7 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[8] + connection: direct + pad: SOC_GPI8 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[9] + connection: direct + pad: SOC_GPI9 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[10] + connection: direct + pad: SOC_GPI10 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[11] + connection: direct + pad: SOC_GPI11 + desc: "" + attr: InputStd + } + { + instance: soc_proxy + port: soc_gpi[12] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpi[13] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpi[14] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpi[15] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpo[0] + connection: direct + pad: SOC_GPO0 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[1] + connection: direct + pad: SOC_GPO1 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[2] + connection: direct + pad: SOC_GPO2 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[3] + connection: direct + pad: SOC_GPO3 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[4] + connection: direct + pad: SOC_GPO4 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[5] + connection: direct + pad: SOC_GPO5 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[6] + connection: direct + pad: SOC_GPO6 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[7] + connection: direct + pad: SOC_GPO7 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[8] + connection: direct + pad: SOC_GPO8 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[9] + connection: direct + pad: SOC_GPO9 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[10] + connection: direct + pad: SOC_GPO10 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[11] + connection: direct + pad: SOC_GPO11 + desc: "" + attr: BidirStd + } + { + instance: soc_proxy + port: soc_gpo[12] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpo[13] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpo[14] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: soc_proxy + port: soc_gpo[15] + connection: muxed + pad: "" + desc: "" + attr: "" + } + { + instance: otp_macro + port: test[0] + connection: muxed + pad: "" + desc: "" + attr: "" + } + ] + num_wkup_detect: 8 + wkup_cnt_width: 8 + enable_usb_wakeup: false + enable_strap_sampling: false + ios: + [ + { + name: spi_host0_sd + width: 4 + type: inout + idx: 0 + pad: SPI_HOST_D0 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 0 + } + { + name: spi_host0_sd + width: 4 + type: inout + idx: 1 + pad: SPI_HOST_D1 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 1 + } + { + name: spi_host0_sd + width: 4 + type: inout + idx: 2 + pad: SPI_HOST_D2 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 2 + } + { + name: spi_host0_sd + width: 4 + type: inout + idx: 3 + pad: SPI_HOST_D3 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 3 + } + { + name: spi_device_sd + width: 4 + type: inout + idx: 0 + pad: SPI_DEV_D0 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 4 + } + { + name: spi_device_sd + width: 4 + type: inout + idx: 1 + pad: SPI_DEV_D1 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 5 + } + { + name: spi_device_sd + width: 4 + type: inout + idx: 2 + pad: SPI_DEV_D2 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 6 + } + { + name: spi_device_sd + width: 4 + type: inout + idx: 3 + pad: SPI_DEV_D3 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 7 + } + { + name: i2c0_scl + width: 1 + type: inout + idx: -1 + pad: I2C_SCL + attr: BidirStd + connection: direct + desc: "" + glob_idx: 8 + } + { + name: i2c0_sda + width: 1 + type: inout + idx: -1 + pad: I2C_SDA + attr: BidirStd + connection: direct + desc: "" + glob_idx: 9 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 0 + pad: GPIO0 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 10 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 1 + pad: GPIO1 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 11 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 2 + pad: GPIO2 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 12 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 3 + pad: GPIO3 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 13 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 4 + pad: GPIO4 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 14 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 5 + pad: GPIO5 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 15 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 6 + pad: GPIO6 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 16 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 7 + pad: GPIO7 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 17 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 8 + pad: GPIO8 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 18 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 9 + pad: GPIO9 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 19 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 10 + pad: GPIO10 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 20 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 11 + pad: GPIO11 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 21 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 12 + pad: GPIO12 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 22 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 13 + pad: GPIO13 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 23 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 14 + pad: GPIO14 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 24 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 15 + pad: GPIO15 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 25 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 16 + pad: GPIO16 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 26 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 17 + pad: GPIO17 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 27 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 18 + pad: GPIO18 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 28 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 19 + pad: GPIO19 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 29 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 20 + pad: GPIO20 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 30 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 21 + pad: GPIO21 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 31 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 22 + pad: GPIO22 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 32 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 23 + pad: GPIO23 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 33 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 24 + pad: GPIO24 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 34 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 25 + pad: GPIO25 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 35 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 26 + pad: GPIO26 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 36 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 27 + pad: GPIO27 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 37 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 28 + pad: GPIO28 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 38 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 29 + pad: GPIO29 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 39 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 30 + pad: GPIO30 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 40 + } + { + name: gpio_gpio + width: 32 + type: inout + idx: 31 + pad: GPIO31 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 41 + } + { + name: spi_device_sck + width: 1 + type: input + idx: -1 + pad: SPI_DEV_CLK + attr: InputStd + connection: direct + desc: "" + glob_idx: 42 + } + { + name: spi_device_csb + width: 1 + type: input + idx: -1 + pad: SPI_DEV_CS_L + attr: InputStd + connection: direct + desc: "" + glob_idx: 43 + } + { + name: spi_device_tpm_csb + width: 1 + type: input + idx: -1 + pad: SPI_DEV_TPM_CS_L + attr: InputStd + connection: direct + desc: "" + glob_idx: 44 + } + { + name: uart0_rx + width: 1 + type: input + idx: -1 + pad: UART_RX + attr: InputStd + connection: direct + desc: "" + glob_idx: 45 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 0 + pad: SOC_GPI0 + attr: InputStd + connection: direct + desc: "" + glob_idx: 46 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 1 + pad: SOC_GPI1 + attr: InputStd + connection: direct + desc: "" + glob_idx: 47 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 2 + pad: SOC_GPI2 + attr: InputStd + connection: direct + desc: "" + glob_idx: 48 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 3 + pad: SOC_GPI3 + attr: InputStd + connection: direct + desc: "" + glob_idx: 49 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 4 + pad: SOC_GPI4 + attr: InputStd + connection: direct + desc: "" + glob_idx: 50 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 5 + pad: SOC_GPI5 + attr: InputStd + connection: direct + desc: "" + glob_idx: 51 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 6 + pad: SOC_GPI6 + attr: InputStd + connection: direct + desc: "" + glob_idx: 52 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 7 + pad: SOC_GPI7 + attr: InputStd + connection: direct + desc: "" + glob_idx: 53 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 8 + pad: SOC_GPI8 + attr: InputStd + connection: direct + desc: "" + glob_idx: 54 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 9 + pad: SOC_GPI9 + attr: InputStd + connection: direct + desc: "" + glob_idx: 55 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 10 + pad: SOC_GPI10 + attr: InputStd + connection: direct + desc: "" + glob_idx: 56 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 11 + pad: SOC_GPI11 + attr: InputStd + connection: direct + desc: "" + glob_idx: 57 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 12 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 0 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 13 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 1 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 14 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 2 + } + { + name: soc_proxy_soc_gpi + width: 16 + type: input + idx: 15 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 3 + } + { + name: spi_host0_sck + width: 1 + type: output + idx: -1 + pad: SPI_HOST_CLK + attr: BidirStd + connection: direct + desc: "" + glob_idx: 58 + } + { + name: spi_host0_csb + width: 1 + type: output + idx: -1 + pad: SPI_HOST_CS_L + attr: BidirStd + connection: direct + desc: "" + glob_idx: 59 + } + { + name: uart0_tx + width: 1 + type: output + idx: -1 + pad: UART_TX + attr: BidirStd + connection: direct + desc: "" + glob_idx: 60 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 0 + pad: SOC_GPO0 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 61 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 1 + pad: SOC_GPO1 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 62 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 2 + pad: SOC_GPO2 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 63 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 3 + pad: SOC_GPO3 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 64 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 4 + pad: SOC_GPO4 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 65 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 5 + pad: SOC_GPO5 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 66 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 6 + pad: SOC_GPO6 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 67 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 7 + pad: SOC_GPO7 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 68 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 8 + pad: SOC_GPO8 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 69 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 9 + pad: SOC_GPO9 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 70 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 10 + pad: SOC_GPO10 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 71 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 11 + pad: SOC_GPO11 + attr: BidirStd + connection: direct + desc: "" + glob_idx: 72 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 12 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 0 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 13 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 1 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 14 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 2 + } + { + name: soc_proxy_soc_gpo + width: 16 + type: output + idx: 15 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 3 + } + { + name: otp_macro_test + width: 8 + type: output + idx: 0 + pad: "" + attr: "" + connection: muxed + desc: "" + glob_idx: 4 + } + ] + io_counts: + { + dedicated: + { + inouts: 42 + inputs: 16 + outputs: 15 + pads: 80 + } + muxed: + { + inouts: 0 + inputs: 4 + outputs: 5 + pads: 12 + } + } + } + targets: + [ + { + name: asic + pinout: + { + remove_ports: [] + remove_pads: [] + add_pads: [] + } + pinmux: + { + special_signals: + [ + { + name: tap0 + pad: MIO0 + desc: TAP strap signal. + idx: 0 + } + { + name: tap1 + pad: MIO1 + desc: TAP strap signal. + idx: 1 + } + { + name: dft0 + pad: MIO2 + desc: DFT strap signal. + idx: 2 + } + { + name: dft1 + pad: MIO3 + desc: DFT strap signal. + idx: 3 + } + { + name: tck + pad: MIO4 + desc: JTAG tck signal. + idx: 4 + } + { + name: tms + pad: MIO5 + desc: JTAG tms signal. + idx: 5 + } + { + name: trst_n + pad: MIO6 + desc: JTAG trst_n signal. + idx: 6 + } + { + name: tdi + pad: MIO7 + desc: JTAG tdi signal. + idx: 7 + } + { + name: tdo + pad: MIO8 + desc: JTAG tdo signal. + idx: 8 + } + ] + } + } + { + name: cw310 + pinout: + { + remove_ports: [] + remove_pads: + [ + OTP_EXT_VOLT + ] + add_pads: + [ + { + name: IO_CLK + type: InputStd + bank: VIO + connection: manual + desc: Extra clock input for FPGA target + port_type: inout + } + { + name: POR_BUTTON_N + type: InputStd + bank: VIO + connection: manual + desc: Power-on reset button input + port_type: inout + } + { + name: IO_CLKOUT + type: BidirStd + bank: VIO + connection: manual + desc: Manual clock output for SCA setup + port_type: inout + } + { + name: IO_TRIGGER + type: BidirStd + bank: VIO + connection: manual + desc: Manual trigger output for SCA setup + port_type: inout + } + ] + } + pinmux: + { + special_signals: + [ + { + name: tap0 + pad: MIO0 + desc: TAP strap signal. + idx: 0 + } + { + name: tap1 + pad: MIO1 + desc: TAP strap signal. + idx: 1 + } + { + name: dft0 + pad: MIO2 + desc: DFT strap signal. + idx: 2 + } + { + name: dft1 + pad: MIO3 + desc: DFT strap signal. + idx: 3 + } + { + name: tck + pad: MIO4 + desc: JTAG tck signal. + idx: 4 + } + { + name: tms + pad: MIO5 + desc: JTAG tms signal. + idx: 5 + } + { + name: trst_n + pad: MIO6 + desc: JTAG trst_n signal. + idx: 6 + } + { + name: tdi + pad: MIO7 + desc: JTAG tdi signal. + idx: 7 + } + { + name: tdo + pad: MIO8 + desc: JTAG tdo signal. + idx: 8 + } + ] + } + } + ] + incoming_alert: {} + incoming_interrupt: {} + exported_clks: {} + racl: + { + error_response: true + ctn_uid_bit_lsb: 0 + ctn_uid_bit_msb: 4 + role_bit_lsb: 5 + role_bit_msb: 8 + roles: + { + ROT: + { + role_id: 0 + } + ROLE1: + { + role_id: 1 + } + SOC: + { + role_id: 2 + } + } + policies: + { + Null: + [ + { + name: ALL_RD_WR + desc: Standard policies allowing all roles to access a register + allowed_rd: + [ + ROT + ROLE1 + SOC + ] + allowed_wr: + [ + ROT + ROLE1 + SOC + ] + rd_default: 7 + wr_default: 7 + } + { + name: ROT_PRIVATE + rot_private: true + desc: Standard policies allowing only the ROT role to access a register + allowed_rd: + [ + ROT + ] + allowed_wr: + [ + ROT + ] + rd_default: 1 + wr_default: 1 + } + { + name: SOC_ROT + desc: Custom policy + allowed_rd: + [ + ROT + SOC + ] + allowed_wr: + [ + ROT + SOC + ] + rd_default: 5 + wr_default: 5 + } + ] + } + nr_role_bits: 4 + nr_ctn_uid_bits: 5 + nr_policies: 3 + rot_private_policy_rd: 1 + rot_private_policy_wr: 1 + } + wakeups: + [ + { + name: pin_wkup_req + width: "1" + module: pinmux_aon + } + { + name: wkup_req + width: "1" + module: aon_timer_aon + } + { + name: wkup_internal_req + width: "1" + module: soc_proxy + } + { + name: wkup_external_req + width: "1" + module: soc_proxy + } + ] + unmanaged_resets: {} + exported_rsts: {} + alert: + [ + { + name: uart0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: uart0 + desc: uart0 fatal_fault alert + lpg_name: peri_lc_io_div4_0 + lpg_idx: 0 + } + { + name: gpio_fatal_fault + width: 1 + type: alert + async: "1" + module_name: gpio + desc: gpio fatal_fault alert + lpg_name: peri_lc_io_div4_0 + lpg_idx: 0 + } + { + name: spi_device_fatal_fault + width: 1 + type: alert + async: "1" + module_name: spi_device + desc: spi_device fatal_fault alert + lpg_name: peri_spi_device_0 + lpg_idx: 1 + } + { + name: i2c0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: i2c0 + desc: i2c0 fatal_fault alert + lpg_name: peri_i2c0_0 + lpg_idx: 2 + } + { + name: otp_ctrl_fatal_macro_error + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + desc: otp_ctrl fatal_macro_error alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: otp_ctrl_fatal_check_error + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + desc: otp_ctrl fatal_check_error alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: otp_ctrl_fatal_bus_integ_error + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + desc: otp_ctrl fatal_bus_integ_error alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: otp_ctrl_fatal_prim_otp_alert + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + desc: otp_ctrl fatal_prim_otp_alert alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: otp_ctrl_recov_prim_otp_alert + width: 1 + type: alert + async: "1" + module_name: otp_ctrl + desc: otp_ctrl recov_prim_otp_alert alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: lc_ctrl_fatal_prog_error + width: 1 + type: alert + async: "1" + module_name: lc_ctrl + desc: lc_ctrl fatal_prog_error alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: lc_ctrl_fatal_state_error + width: 1 + type: alert + async: "1" + module_name: lc_ctrl + desc: lc_ctrl fatal_state_error alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: lc_ctrl_fatal_bus_integ_error + width: 1 + type: alert + async: "1" + module_name: lc_ctrl + desc: lc_ctrl fatal_bus_integ_error alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: spi_host0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: spi_host0 + desc: spi_host0 fatal_fault alert + lpg_name: peri_spi_host0_0 + lpg_idx: 4 + } + { + name: pwrmgr_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: pwrmgr_aon + desc: pwrmgr_aon fatal_fault alert + lpg_name: powerup_por_io_div4_Aon + lpg_idx: 5 + } + { + name: rstmgr_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: rstmgr_aon + desc: rstmgr_aon fatal_fault alert + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 6 + } + { + name: rstmgr_aon_fatal_cnsty_fault + width: 1 + type: alert + async: "1" + module_name: rstmgr_aon + desc: rstmgr_aon fatal_cnsty_fault alert + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 6 + } + { + name: clkmgr_aon_recov_fault + width: 1 + type: alert + async: "1" + module_name: clkmgr_aon + desc: clkmgr_aon recov_fault alert + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 6 + } + { + name: clkmgr_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: clkmgr_aon + desc: clkmgr_aon fatal_fault alert + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 6 + } + { + name: pinmux_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: pinmux_aon + desc: pinmux_aon fatal_fault alert + lpg_name: powerup_lc_io_div4_Aon + lpg_idx: 6 + } + { + name: aon_timer_aon_fatal_fault + width: 1 + type: alert + async: "1" + module_name: aon_timer_aon + desc: aon_timer_aon fatal_fault alert + lpg_name: timers_lc_io_div4_Aon + lpg_idx: 7 + } + { + name: soc_proxy_fatal_alert_intg + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_intg alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_0 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_0 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_1 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_1 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_2 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_2 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_3 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_3 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_4 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_4 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_5 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_5 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_6 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_6 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_7 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_7 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_8 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_8 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_9 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_9 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_10 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_10 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_11 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_11 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_12 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_12 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_13 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_13 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_14 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_14 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_15 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_15 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_16 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_16 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_17 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_17 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_18 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_18 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_19 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_19 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_20 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_20 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_21 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_21 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_22 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_22 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_fatal_alert_external_23 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy fatal_alert_external_23 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_recov_alert_external_0 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy recov_alert_external_0 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_recov_alert_external_1 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy recov_alert_external_1 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_recov_alert_external_2 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy recov_alert_external_2 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_proxy_recov_alert_external_3 + width: 1 + type: alert + async: "1" + module_name: soc_proxy + desc: soc_proxy recov_alert_external_3 alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: sram_ctrl_ret_aon_fatal_error + width: 1 + type: alert + async: "1" + module_name: sram_ctrl_ret_aon + desc: sram_ctrl_ret_aon fatal_error alert + lpg_name: infra_lc_io_div4_Aon + lpg_idx: 10 + } + { + name: rv_plic_fatal_fault + width: 1 + type: alert + async: "1" + module_name: rv_plic + desc: rv_plic fatal_fault alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: aes_recov_ctrl_update_err + width: 1 + type: alert + async: "1" + module_name: aes + desc: aes recov_ctrl_update_err alert + lpg_name: aes_trans_lc_0 + lpg_idx: 12 + } + { + name: aes_fatal_fault + width: 1 + type: alert + async: "1" + module_name: aes + desc: aes fatal_fault alert + lpg_name: aes_trans_lc_0 + lpg_idx: 12 + } + { + name: hmac_fatal_fault + width: 1 + type: alert + async: "1" + module_name: hmac + desc: hmac fatal_fault alert + lpg_name: hmac_trans_lc_0 + lpg_idx: 13 + } + { + name: kmac_recov_operation_err + width: 1 + type: alert + async: "1" + module_name: kmac + desc: kmac recov_operation_err alert + lpg_name: kmac_trans_lc_0 + lpg_idx: 14 + } + { + name: kmac_fatal_fault_err + width: 1 + type: alert + async: "1" + module_name: kmac + desc: kmac fatal_fault_err alert + lpg_name: kmac_trans_lc_0 + lpg_idx: 14 + } + { + name: otbn_fatal + width: 1 + type: alert + async: "1" + module_name: otbn + desc: otbn fatal alert + lpg_name: otbn_trans_lc_0 + lpg_idx: 15 + } + { + name: otbn_recov + width: 1 + type: alert + async: "1" + module_name: otbn + desc: otbn recov alert + lpg_name: otbn_trans_lc_0 + lpg_idx: 15 + } + { + name: keymgr_dpe_recov_operation_err + width: 1 + type: alert + async: "1" + module_name: keymgr_dpe + desc: keymgr_dpe recov_operation_err alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: keymgr_dpe_fatal_fault_err + width: 1 + type: alert + async: "1" + module_name: keymgr_dpe + desc: keymgr_dpe fatal_fault_err alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: csrng_recov_alert + width: 1 + type: alert + async: "1" + module_name: csrng + desc: csrng recov_alert alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: csrng_fatal_alert + width: 1 + type: alert + async: "1" + module_name: csrng + desc: csrng fatal_alert alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: entropy_src_recov_alert + width: 1 + type: alert + async: "1" + module_name: entropy_src + desc: entropy_src recov_alert alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: entropy_src_fatal_alert + width: 1 + type: alert + async: "1" + module_name: entropy_src + desc: entropy_src fatal_alert alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: edn0_recov_alert + width: 1 + type: alert + async: "1" + module_name: edn0 + desc: edn0 recov_alert alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: edn0_fatal_alert + width: 1 + type: alert + async: "1" + module_name: edn0 + desc: edn0 fatal_alert alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: edn1_recov_alert + width: 1 + type: alert + async: "1" + module_name: edn1 + desc: edn1 recov_alert alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: edn1_fatal_alert + width: 1 + type: alert + async: "1" + module_name: edn1 + desc: edn1 fatal_alert alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: sram_ctrl_main_fatal_error + width: 1 + type: alert + async: "1" + module_name: sram_ctrl_main + desc: sram_ctrl_main fatal_error alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: sram_ctrl_mbox_fatal_error + width: 1 + type: alert + async: "1" + module_name: sram_ctrl_mbox + desc: sram_ctrl_mbox fatal_error alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: rom_ctrl0_fatal + width: 1 + type: alert + async: "1" + module_name: rom_ctrl0 + desc: rom_ctrl0 fatal alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: rom_ctrl1_fatal + width: 1 + type: alert + async: "1" + module_name: rom_ctrl1 + desc: rom_ctrl1 fatal alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: dma_fatal_fault + width: 1 + type: alert + async: "1" + module_name: dma + desc: dma fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx0 + desc: mbx0 fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx0_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx0 + desc: mbx0 recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx1_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx1 + desc: mbx1 fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx1_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx1 + desc: mbx1 recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx2_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx2 + desc: mbx2 fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx2_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx2 + desc: mbx2 recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx3_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx3 + desc: mbx3 fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx3_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx3 + desc: mbx3 recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx4_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx4 + desc: mbx4 fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx4_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx4 + desc: mbx4 recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx5_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx5 + desc: mbx5 fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx5_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx5 + desc: mbx5 recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx6_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx6 + desc: mbx6 fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx6_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx6 + desc: mbx6 recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx_jtag_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx_jtag + desc: mbx_jtag fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx_jtag_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx_jtag + desc: mbx_jtag recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx_pcie0_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx_pcie0 + desc: mbx_pcie0 fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx_pcie0_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx_pcie0 + desc: mbx_pcie0 recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx_pcie1_fatal_fault + width: 1 + type: alert + async: "1" + module_name: mbx_pcie1 + desc: mbx_pcie1 fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: mbx_pcie1_recov_fault + width: 1 + type: alert + async: "1" + module_name: mbx_pcie1 + desc: mbx_pcie1 recov_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: soc_dbg_ctrl_fatal_fault + width: 1 + type: alert + async: "1" + module_name: soc_dbg_ctrl + desc: soc_dbg_ctrl fatal_fault alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: soc_dbg_ctrl_recov_ctrl_update_err + width: 1 + type: alert + async: "1" + module_name: soc_dbg_ctrl + desc: soc_dbg_ctrl recov_ctrl_update_err alert + lpg_name: secure_lc_io_div4_0 + lpg_idx: 3 + } + { + name: racl_ctrl_fatal_fault + width: 1 + type: alert + async: "1" + module_name: racl_ctrl + desc: racl_ctrl fatal_fault alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: racl_ctrl_recov_ctrl_update_err + width: 1 + type: alert + async: "1" + module_name: racl_ctrl + desc: racl_ctrl recov_ctrl_update_err alert + lpg_name: infra_lc_0 + lpg_idx: 9 + } + { + name: ac_range_check_recov_ctrl_update_err + width: 1 + type: alert + async: "1" + module_name: ac_range_check + desc: ac_range_check recov_ctrl_update_err alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + { + name: ac_range_check_fatal_fault + width: 1 + type: alert + async: "1" + module_name: ac_range_check + desc: ac_range_check fatal_fault alert + lpg_name: secure_lc_0 + lpg_idx: 11 + } + ] + outgoing_alert: {} + interrupt: + [ + { + name: uart0_tx_watermark + width: 1 + type: interrupt + module_name: uart0 + desc: uart0 tx_watermark interrupt + intr_type: IntrType.Status + default_val: true + incoming: false + plic: rv_plic + outgoing: false + } + { + name: uart0_rx_watermark + width: 1 + type: interrupt + module_name: uart0 + desc: uart0 rx_watermark interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: uart0_tx_done + width: 1 + type: interrupt + module_name: uart0 + desc: uart0 tx_done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: uart0_rx_overflow + width: 1 + type: interrupt + module_name: uart0 + desc: uart0 rx_overflow interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: uart0_rx_frame_err + width: 1 + type: interrupt + module_name: uart0 + desc: uart0 rx_frame_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: uart0_rx_break_err + width: 1 + type: interrupt + module_name: uart0 + desc: uart0 rx_break_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: uart0_rx_timeout + width: 1 + type: interrupt + module_name: uart0 + desc: uart0 rx_timeout interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: uart0_rx_parity_err + width: 1 + type: interrupt + module_name: uart0 + desc: uart0 rx_parity_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: uart0_tx_empty + width: 1 + type: interrupt + module_name: uart0 + desc: uart0 tx_empty interrupt + intr_type: IntrType.Status + default_val: true + incoming: false + plic: rv_plic + outgoing: false + } + { + name: gpio_gpio + width: 32 + type: interrupt + module_name: gpio + desc: gpio gpio interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_device_upload_cmdfifo_not_empty + width: 1 + type: interrupt + module_name: spi_device + desc: spi_device upload_cmdfifo_not_empty interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_device_upload_payload_not_empty + width: 1 + type: interrupt + module_name: spi_device + desc: spi_device upload_payload_not_empty interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_device_upload_payload_overflow + width: 1 + type: interrupt + module_name: spi_device + desc: spi_device upload_payload_overflow interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_device_readbuf_watermark + width: 1 + type: interrupt + module_name: spi_device + desc: spi_device readbuf_watermark interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_device_readbuf_flip + width: 1 + type: interrupt + module_name: spi_device + desc: spi_device readbuf_flip interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_device_tpm_header_not_empty + width: 1 + type: interrupt + module_name: spi_device + desc: spi_device tpm_header_not_empty interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_device_tpm_rdfifo_cmd_end + width: 1 + type: interrupt + module_name: spi_device + desc: spi_device tpm_rdfifo_cmd_end interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_device_tpm_rdfifo_drop + width: 1 + type: interrupt + module_name: spi_device + desc: spi_device tpm_rdfifo_drop interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_fmt_threshold + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 fmt_threshold interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_rx_threshold + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 rx_threshold interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_acq_threshold + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 acq_threshold interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_rx_overflow + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 rx_overflow interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_controller_halt + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 controller_halt interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_scl_interference + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 scl_interference interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_sda_interference + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 sda_interference interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_stretch_timeout + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 stretch_timeout interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_sda_unstable + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 sda_unstable interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_cmd_complete + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 cmd_complete interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_tx_stretch + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 tx_stretch interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_tx_threshold + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 tx_threshold interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_acq_stretch + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 acq_stretch interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_unexp_stop + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 unexp_stop interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: i2c0_host_timeout + width: 1 + type: interrupt + module_name: i2c0 + desc: i2c0 host_timeout interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: otp_ctrl_otp_operation_done + width: 1 + type: interrupt + module_name: otp_ctrl + desc: otp_ctrl otp_operation_done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: otp_ctrl_otp_error + width: 1 + type: interrupt + module_name: otp_ctrl + desc: otp_ctrl otp_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: alert_handler_classa + width: 1 + type: interrupt + module_name: alert_handler + desc: alert_handler classa interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: alert_handler_classb + width: 1 + type: interrupt + module_name: alert_handler + desc: alert_handler classb interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: alert_handler_classc + width: 1 + type: interrupt + module_name: alert_handler + desc: alert_handler classc interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: alert_handler_classd + width: 1 + type: interrupt + module_name: alert_handler + desc: alert_handler classd interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_host0_error + width: 1 + type: interrupt + module_name: spi_host0 + desc: spi_host0 error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: spi_host0_spi_event + width: 1 + type: interrupt + module_name: spi_host0 + desc: spi_host0 spi_event interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: pwrmgr_aon_wakeup + width: 1 + type: interrupt + module_name: pwrmgr_aon + desc: pwrmgr_aon wakeup interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: aon_timer_aon_wkup_timer_expired + width: 1 + type: interrupt + module_name: aon_timer_aon + desc: aon_timer_aon wkup_timer_expired interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: aon_timer_aon_wdog_timer_bark + width: 1 + type: interrupt + module_name: aon_timer_aon + desc: aon_timer_aon wdog_timer_bark interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: soc_proxy_external + width: 32 + type: interrupt + module_name: soc_proxy + desc: soc_proxy external interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: hmac_hmac_done + width: 1 + type: interrupt + module_name: hmac + desc: hmac hmac_done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: hmac_fifo_empty + width: 1 + type: interrupt + module_name: hmac + desc: hmac fifo_empty interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: hmac_hmac_err + width: 1 + type: interrupt + module_name: hmac + desc: hmac hmac_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: kmac_kmac_done + width: 1 + type: interrupt + module_name: kmac + desc: kmac kmac_done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: kmac_fifo_empty + width: 1 + type: interrupt + module_name: kmac + desc: kmac fifo_empty interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: kmac_kmac_err + width: 1 + type: interrupt + module_name: kmac + desc: kmac kmac_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: otbn_done + width: 1 + type: interrupt + module_name: otbn + desc: otbn done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: keymgr_dpe_op_done + width: 1 + type: interrupt + module_name: keymgr_dpe + desc: keymgr_dpe op_done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: csrng_cs_cmd_req_done + width: 1 + type: interrupt + module_name: csrng + desc: csrng cs_cmd_req_done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: csrng_cs_entropy_req + width: 1 + type: interrupt + module_name: csrng + desc: csrng cs_entropy_req interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: csrng_cs_hw_inst_exc + width: 1 + type: interrupt + module_name: csrng + desc: csrng cs_hw_inst_exc interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: csrng_cs_fatal_err + width: 1 + type: interrupt + module_name: csrng + desc: csrng cs_fatal_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: entropy_src_es_entropy_valid + width: 1 + type: interrupt + module_name: entropy_src + desc: entropy_src es_entropy_valid interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: entropy_src_es_health_test_failed + width: 1 + type: interrupt + module_name: entropy_src + desc: entropy_src es_health_test_failed interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: entropy_src_es_observe_fifo_ready + width: 1 + type: interrupt + module_name: entropy_src + desc: entropy_src es_observe_fifo_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: entropy_src_es_fatal_err + width: 1 + type: interrupt + module_name: entropy_src + desc: entropy_src es_fatal_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: edn0_edn_cmd_req_done + width: 1 + type: interrupt + module_name: edn0 + desc: edn0 edn_cmd_req_done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: edn0_edn_fatal_err + width: 1 + type: interrupt + module_name: edn0 + desc: edn0 edn_fatal_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: edn1_edn_cmd_req_done + width: 1 + type: interrupt + module_name: edn1 + desc: edn1 edn_cmd_req_done interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: edn1_edn_fatal_err + width: 1 + type: interrupt + module_name: edn1 + desc: edn1 edn_fatal_err interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: dma_dma_done + width: 1 + type: interrupt + module_name: dma + desc: dma dma_done interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: dma_dma_chunk_done + width: 1 + type: interrupt + module_name: dma + desc: dma dma_chunk_done interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: dma_dma_error + width: 1 + type: interrupt + module_name: dma + desc: dma dma_error interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx0_mbx_ready + width: 1 + type: interrupt + module_name: mbx0 + desc: mbx0 mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx0_mbx_abort + width: 1 + type: interrupt + module_name: mbx0 + desc: mbx0 mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx0_mbx_error + width: 1 + type: interrupt + module_name: mbx0 + desc: mbx0 mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx1_mbx_ready + width: 1 + type: interrupt + module_name: mbx1 + desc: mbx1 mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx1_mbx_abort + width: 1 + type: interrupt + module_name: mbx1 + desc: mbx1 mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx1_mbx_error + width: 1 + type: interrupt + module_name: mbx1 + desc: mbx1 mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx2_mbx_ready + width: 1 + type: interrupt + module_name: mbx2 + desc: mbx2 mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx2_mbx_abort + width: 1 + type: interrupt + module_name: mbx2 + desc: mbx2 mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx2_mbx_error + width: 1 + type: interrupt + module_name: mbx2 + desc: mbx2 mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx3_mbx_ready + width: 1 + type: interrupt + module_name: mbx3 + desc: mbx3 mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx3_mbx_abort + width: 1 + type: interrupt + module_name: mbx3 + desc: mbx3 mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx3_mbx_error + width: 1 + type: interrupt + module_name: mbx3 + desc: mbx3 mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx4_mbx_ready + width: 1 + type: interrupt + module_name: mbx4 + desc: mbx4 mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx4_mbx_abort + width: 1 + type: interrupt + module_name: mbx4 + desc: mbx4 mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx4_mbx_error + width: 1 + type: interrupt + module_name: mbx4 + desc: mbx4 mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx5_mbx_ready + width: 1 + type: interrupt + module_name: mbx5 + desc: mbx5 mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx5_mbx_abort + width: 1 + type: interrupt + module_name: mbx5 + desc: mbx5 mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx5_mbx_error + width: 1 + type: interrupt + module_name: mbx5 + desc: mbx5 mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx6_mbx_ready + width: 1 + type: interrupt + module_name: mbx6 + desc: mbx6 mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx6_mbx_abort + width: 1 + type: interrupt + module_name: mbx6 + desc: mbx6 mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx6_mbx_error + width: 1 + type: interrupt + module_name: mbx6 + desc: mbx6 mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx_jtag_mbx_ready + width: 1 + type: interrupt + module_name: mbx_jtag + desc: mbx_jtag mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx_jtag_mbx_abort + width: 1 + type: interrupt + module_name: mbx_jtag + desc: mbx_jtag mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx_jtag_mbx_error + width: 1 + type: interrupt + module_name: mbx_jtag + desc: mbx_jtag mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx_pcie0_mbx_ready + width: 1 + type: interrupt + module_name: mbx_pcie0 + desc: mbx_pcie0 mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx_pcie0_mbx_abort + width: 1 + type: interrupt + module_name: mbx_pcie0 + desc: mbx_pcie0 mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx_pcie0_mbx_error + width: 1 + type: interrupt + module_name: mbx_pcie0 + desc: mbx_pcie0 mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx_pcie1_mbx_ready + width: 1 + type: interrupt + module_name: mbx_pcie1 + desc: mbx_pcie1 mbx_ready interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx_pcie1_mbx_abort + width: 1 + type: interrupt + module_name: mbx_pcie1 + desc: mbx_pcie1 mbx_abort interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: mbx_pcie1_mbx_error + width: 1 + type: interrupt + module_name: mbx_pcie1 + desc: mbx_pcie1 mbx_error interrupt + intr_type: IntrType.Event + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: racl_ctrl_racl_error + width: 1 + type: interrupt + module_name: racl_ctrl + desc: racl_ctrl racl_error interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + { + name: ac_range_check_deny_cnt_reached + width: 1 + type: interrupt + module_name: ac_range_check + desc: ac_range_check deny_cnt_reached interrupt + intr_type: IntrType.Status + default_val: false + incoming: false + plic: rv_plic + outgoing: false + } + ] + outgoing_interrupt: {} + alert_module: + [ + uart0 + gpio + spi_device + i2c0 + otp_ctrl + lc_ctrl + spi_host0 + pwrmgr_aon + rstmgr_aon + clkmgr_aon + pinmux_aon + aon_timer_aon + soc_proxy + sram_ctrl_ret_aon + rv_plic + aes + hmac + kmac + otbn + keymgr_dpe + csrng + entropy_src + edn0 + edn1 + sram_ctrl_main + sram_ctrl_mbox + rom_ctrl0 + rom_ctrl1 + dma + mbx0 + mbx1 + mbx2 + mbx3 + mbx4 + mbx5 + mbx6 + mbx_jtag + mbx_pcie0 + mbx_pcie1 + soc_dbg_ctrl + racl_ctrl + ac_range_check + ] + interrupt_module: + [ + uart0 + gpio + spi_device + i2c0 + otp_ctrl + alert_handler + spi_host0 + pwrmgr_aon + aon_timer_aon + soc_proxy + hmac + kmac + otbn + keymgr_dpe + csrng + entropy_src + edn0 + edn1 + dma + mbx0 + mbx1 + mbx2 + mbx3 + mbx4 + mbx5 + mbx6 + mbx_jtag + mbx_pcie0 + mbx_pcie1 + racl_ctrl + ac_range_check + ] + outgoing_alert_module: {} + outgoing_interrupt_module: {} + alert_lpgs: + [ + { + name: peri_lc_io_div4_0 + clock_group: + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_peri + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc_io_div4 + domain: "0" + } + } + { + name: peri_spi_device_0 + clock_group: + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_peri + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: spi_device + domain: "0" + } + } + { + name: peri_i2c0_0 + clock_group: + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_peri + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: i2c0 + domain: "0" + } + } + { + name: secure_lc_io_div4_0 + clock_group: + { + name: secure + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_secure: io_div4 + clk_main_secure: main + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_secure + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc_io_div4 + domain: "0" + } + } + { + name: peri_spi_host0_0 + clock_group: + { + name: peri + src: top + sw_cg: yes + unique: no + clocks: + { + clk_io_div4_peri: io_div4 + clk_io_div2_peri: io_div2 + clk_aon_peri: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_peri + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: spi_host0 + domain: "0" + } + } + { + name: powerup_por_io_div4_Aon + clock_group: + { + name: powerup + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_powerup: io_div4 + clk_aon_powerup: aon + clk_main_powerup: main + clk_io_powerup: io + clk_io_div2_powerup: io_div2 + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: por_io_div4 + domain: Aon + } + } + { + name: powerup_lc_io_div4_Aon + clock_group: + { + name: powerup + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_powerup: io_div4 + clk_aon_powerup: aon + clk_main_powerup: main + clk_io_powerup: io + clk_io_div2_powerup: io_div2 + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_powerup + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc_io_div4 + domain: Aon + } + } + { + name: timers_lc_io_div4_Aon + clock_group: + { + name: timers + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_timers: io_div4 + clk_aon_timers: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_timers + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc_io_div4 + domain: Aon + } + } + { + name: infra_lc_io_div4_0 + clock_group: + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_infra: io_div4 + clk_main_infra: main + clk_aon_infra: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_infra + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc_io_div4 + domain: "0" + } + } + { + name: infra_lc_0 + clock_group: + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_infra: io_div4 + clk_main_infra: main + clk_aon_infra: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_main_infra + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: infra_lc_io_div4_Aon + clock_group: + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_infra: io_div4 + clk_main_infra: main + clk_aon_infra: aon + } + } + clock_connection: clkmgr_aon_clocks.clk_io_div4_infra + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc_io_div4 + domain: Aon + } + } + { + name: secure_lc_0 + clock_group: + { + name: secure + src: top + sw_cg: no + unique: no + clocks: + { + clk_io_div4_secure: io_div4 + clk_main_secure: main + } + } + clock_connection: clkmgr_aon_clocks.clk_main_secure + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: aes_trans_lc_0 + clock_group: + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + clock_connection: clkmgr_aon_clocks.clk_main_aes + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: hmac_trans_lc_0 + clock_group: + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + clock_connection: clkmgr_aon_clocks.clk_main_hmac + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: kmac_trans_lc_0 + clock_group: + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + clock_connection: clkmgr_aon_clocks.clk_main_kmac + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc + domain: "0" + } + } + { + name: otbn_trans_lc_0 + clock_group: + { + name: trans + src: top + sw_cg: hint + unique: yes + clocks: + { + clk_main_aes: main + clk_main_hmac: main + clk_main_kmac: main + clk_main_otbn: main + } + } + clock_connection: clkmgr_aon_clocks.clk_main_otbn + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc + domain: "0" + } + } + ] + outgoing_alert_lpgs: {} + inter_signal: + { + signals: + [ + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: uart0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: uart0_lsio_trigger + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: uart0 + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: uart0 + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: uart0 + default: "" + end_idx: -1 + top_signame: uart0_tl + index: -1 + } + { + name: strap_en + desc: + ''' + The strap enable signal tells gpio to take a snapshot of the input pins. + The behaviour of this signal after that event will have no effect. + ''' + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: gpio + package: "" + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: sampled_straps + desc: This vector contains the sampled strap values. + struct: gpio_straps + package: gpio_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: gpio + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: gpio + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: gpio + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: gpio + default: "" + end_idx: -1 + top_signame: gpio_tl + index: -1 + } + { + name: ram_cfg_sys2spi + struct: ram_2p_cfg + package: prim_ram_2p_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_device + default: "" + external: true + top_signame: spi_device_ram_2p_cfg_sys2spi + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_sys2spi + struct: ram_2p_cfg_rsp + package: prim_ram_2p_pkg + type: uni + act: req + width: 1 + inst_name: spi_device + default: "" + external: true + top_signame: spi_device_ram_2p_cfg_rsp_sys2spi + conn_type: false + index: -1 + } + { + name: ram_cfg_spi2sys + struct: ram_2p_cfg + package: prim_ram_2p_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_device + default: "" + external: true + top_signame: spi_device_ram_2p_cfg_spi2sys + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_spi2sys + struct: ram_2p_cfg_rsp + package: prim_ram_2p_pkg + type: uni + act: req + width: 1 + inst_name: spi_device + default: "" + external: true + top_signame: spi_device_ram_2p_cfg_rsp_spi2sys + conn_type: false + index: -1 + } + { + name: passthrough + struct: passthrough + package: spi_device_pkg + type: req_rsp + act: req + width: 1 + inst_name: spi_device + default: "" + end_idx: -1 + top_signame: spi_device_passthrough + index: -1 + } + { + name: mbist_en + struct: logic + type: uni + act: rcv + width: 1 + inst_name: spi_device + index: -1 + } + { + name: sck_monitor + struct: logic + type: uni + act: req + width: 1 + inst_name: spi_device + default: "" + package: "" + external: true + top_signame: sck_monitor + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_device + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: spi_device + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_device + default: "" + end_idx: -1 + top_signame: spi_device_tl + index: -1 + } + { + name: ram_cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + default: "" + external: true + top_signame: i2c_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: i2c0 + default: "" + external: true + top_signame: i2c_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: i2c0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: i2c0_lsio_trigger + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: i2c0 + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: i2c0 + default: "" + end_idx: -1 + top_signame: i2c0_tl + index: -1 + } + { + name: edn + desc: Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation. + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otp_ctrl + default: "" + top_signame: edn0_edn + index: 1 + } + { + name: pwr_otp + desc: Initialization request/acknowledge from/to power manager. + struct: pwr_otp + package: pwrmgr_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: pwrmgr_aon_pwr_otp + index: -1 + } + { + name: lc_otp_program + desc: Life cycle state transition interface. + struct: lc_otp_program + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_otp_program + index: -1 + } + { + name: otp_lc_data + desc: + ''' + Life cycle state output holding the current life cycle state, + the value of the transition counter and the tokens needed for life cycle transitions. + ''' + struct: otp_lc_data + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: broadcast + top_signame: otp_ctrl_otp_lc_data + index: -1 + } + { + name: lc_escalate_en + desc: + ''' + Life cycle escalation enable coming from life cycle controller. + This signal moves all FSMs within OTP into the error state. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + desc: + ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + desc: + ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the OWNER_SEED. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_seed_hw_rd_en + desc: + ''' + Seed read enable coming from life cycle controller. + This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_check_byp_en + desc: + ''' + Life cycle partition check bypass signal. + This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_ctrl + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: otp_keymgr_key + desc: Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + struct: otp_keymgr_key + package: otp_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_type: broadcast + top_signame: otp_ctrl_otp_keymgr_key + index: -1 + } + { + name: sram_otp_key + desc: Array with key derivation interfaces for SRAM scrambling devices. + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 4 + default: "'0" + inst_name: otp_ctrl + end_idx: 3 + top_type: partial-one-to-N + top_signame: otp_ctrl_sram_otp_key + index: -1 + } + { + name: otbn_otp_key + desc: Key derivation interface for OTBN scrambling devices. + struct: otbn_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_signame: otp_ctrl_otbn_otp_key + index: -1 + } + { + name: otp_broadcast + desc: Output of the HW partitions with breakout data types. + struct: otp_broadcast + package: otp_ctrl_part_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + top_signame: otp_ctrl_otp_broadcast + index: -1 + } + { + name: otp_macro + desc: Data interface for the OTP macro. + struct: otp_ctrl_macro + package: otp_ctrl_macro_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: otp_ctrl + end_idx: -1 + top_signame: otp_ctrl_otp_macro + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otp_ctrl + default: "" + end_idx: -1 + top_signame: otp_ctrl_core_tl + index: -1 + } + { + name: obs_ctrl + desc: AST observability control signals. + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: otp_macro + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: otp_obs + desc: AST observability bus. + struct: logic + type: uni + act: req + width: 8 + inst_name: otp_macro + default: "" + package: "" + external: true + top_signame: otp_obs + conn_type: false + index: -1 + } + { + name: pwr_seq + desc: Power sequencing signals to AST (VDD domain). + struct: pwr_seq + package: otp_macro_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_macro + external: true + top_signame: otp_macro_pwr_seq + conn_type: false + index: -1 + } + { + name: pwr_seq_h + desc: Power sequencing signals coming from AST (VCC domain). + struct: pwr_seq + package: otp_macro_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: otp_macro + external: true + top_signame: otp_macro_pwr_seq_h + conn_type: false + index: -1 + } + { + name: ext_voltage_h + struct: "" + type: io + act: none + width: 1 + default: "'0" + inst_name: otp_macro + package: "" + external: true + top_signame: otp_ext_voltage_h + conn_type: false + index: -1 + } + { + name: lc_dft_en + desc: + ''' + Test enable qualifier coming from life cycle controller. + This signals enables the TL-UL access port. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otp_macro + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: test + desc: Vendor test control signals from/to the life cycle TAP. + struct: otp_test + package: otp_macro_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_macro + top_signame: lc_ctrl_lc_otp_vendor_test + index: -1 + } + { + name: otp + desc: Data interface for the OTP macro. + struct: otp_ctrl_macro + package: otp_ctrl_macro_pkg + type: req_rsp + act: rsp + width: 1 + default: "'0" + inst_name: otp_macro + top_signame: otp_ctrl_otp_macro + index: -1 + } + { + name: cfg + struct: otp_cfg + package: otp_macro_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: otp_macro + external: true + top_signame: otp_cfg + conn_type: false + index: -1 + } + { + name: cfg_rsp + struct: otp_cfg_rsp + package: otp_macro_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: otp_macro + external: true + top_signame: otp_cfg_rsp + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: otp_macro + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: otp_macro + index: -1 + } + { + name: prim_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otp_macro + default: "" + end_idx: -1 + top_signame: otp_macro_prim_tl + index: -1 + } + { + name: jtag + struct: jtag + package: jtag_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + index: -1 + } + { + name: esc_scrap_state0_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_tx + index: 0 + } + { + name: esc_scrap_state0_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_rx + index: 0 + } + { + name: esc_scrap_state1_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_tx + index: 1 + } + { + name: esc_scrap_state1_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: alert_handler_esc_rx + index: 1 + } + { + name: pwr_lc + struct: pwr_lc + package: lc_ctrl_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + top_signame: pwrmgr_aon_pwr_lc + index: -1 + } + { + name: lc_otp_vendor_test + struct: otp_test + package: otp_macro_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_signame: lc_ctrl_lc_otp_vendor_test + index: -1 + } + { + name: otp_lc_data + struct: otp_lc_data + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT + inst_name: lc_ctrl + top_signame: otp_ctrl_otp_lc_data + index: -1 + } + { + name: lc_otp_program + struct: lc_otp_program + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_signame: lc_ctrl_lc_otp_program + index: -1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: kmac_app + index: 1 + } + { + name: lc_raw_test_rma + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_raw_test_rma + index: -1 + } + { + name: lc_dft_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_hw_debug_clr + desc: + ''' + Clear HW debug functionality. + This signal is On when `lc_hw_debug_en` turns Off outside a reset of `lc_ctrl`. + Flops storing the value of `lc_hw_debug_en` (see below) must be cleared when this signal is On. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_hw_debug_en + desc: + ''' + Enable HW debug functionality; see `HW_DEBUG_EN` in the Theory of Operation doc for details. + + This signal is Off while lc_ctrl is in reset. + In order to prevent a JTAG disconnect during non-debug-module (NDM) reset, this signal should be flopped outside the NDM reset domain. + Such a flop must be cleared when `lc_hw_debug_clr` is On; see above. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_cpu_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_keymgr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_keymgr_en + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_clk_byp_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_clk_byp_req + index: -1 + } + { + name: lc_clk_byp_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_clk_byp_ack + index: -1 + } + { + name: lc_flash_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_flash_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 2 + default: lc_ctrl_pkg::On + inst_name: lc_ctrl + top_signame: otbn_lc_rma_ack + index: -1 + } + { + name: lc_flash_rma_seed + struct: lc_flash_rma_seed + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + index: -1 + } + { + name: lc_check_byp_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_check_byp_en + index: -1 + } + { + name: lc_creator_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_creator_seed_sw_rw_en + index: -1 + } + { + name: lc_owner_seed_sw_rw_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_owner_seed_sw_rw_en + index: -1 + } + { + name: lc_iso_part_sw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_iso_part_sw_wr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + index: -1 + } + { + name: lc_seed_hw_rd_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_seed_hw_rd_en + index: -1 + } + { + name: lc_keymgr_div + struct: lc_keymgr_div + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + end_idx: -1 + top_type: broadcast + top_signame: lc_ctrl_lc_keymgr_div + index: -1 + } + { + name: otp_device_id + struct: otp_device_id + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: lc_ctrl_otp_device_id + index: -1 + } + { + name: otp_manuf_state + struct: otp_manuf_state + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + default: "'0" + inst_name: lc_ctrl + top_signame: lc_ctrl_otp_manuf_state + index: -1 + } + { + name: hw_rev + struct: lc_hw_rev + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: "'0" + inst_name: lc_ctrl + index: -1 + } + { + name: strap_en_override + desc: + ''' + This signal transitions from 0 -> 1 by the lc_ctrl manager after volatile RAW_UNLOCK in order to re-sample the HW straps. + The signal stays at 1 until reset. + Note that this is only used in test chips when SecVolatileRawUnlockEn = 1. + Otherwise this signal is tied off to 0. + ''' + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: lc_ctrl + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + end_idx: -1 + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: dmi_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: lc_ctrl + default: "" + end_idx: -1 + top_signame: lc_ctrl_dmi_tl + index: -1 + } + { + name: crashdump + struct: alert_crashdump + package: alert_handler_pkg + type: uni + act: req + width: 1 + inst_name: alert_handler + default: "" + end_idx: -1 + top_type: broadcast + top_signame: alert_handler_crashdump + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: alert_handler + default: "" + top_signame: edn0_edn + index: 3 + } + { + name: esc_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: rcv + width: 4 + inst_name: alert_handler + default: "" + end_idx: 3 + top_type: partial-one-to-N + top_signame: alert_handler_esc_rx + index: -1 + } + { + name: esc_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: req + width: 4 + inst_name: alert_handler + default: "" + end_idx: 3 + top_type: partial-one-to-N + top_signame: alert_handler_esc_tx + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: alert_handler + default: "" + end_idx: -1 + top_signame: alert_handler_tl + index: -1 + } + { + name: passthrough + struct: passthrough + package: spi_device_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_host0 + default: "" + top_signame: spi_device_passthrough + index: -1 + } + { + name: lsio_trigger + desc: + ''' + Self-clearing status trigger for the DMA. + Set when RX or TX FIFOs are past their configured watermarks matching watermark interrupt behaviour. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: spi_host0 + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: spi_host0_lsio_trigger + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: spi_host0 + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: spi_host0 + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: spi_host0 + default: "" + end_idx: -1 + top_signame: spi_host0_tl + index: -1 + } + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_boot_status + index: -1 + external: true + conn_type: true + } + { + name: pwr_ast + struct: pwr_ast + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + external: true + top_signame: pwrmgr_ast + conn_type: false + index: -1 + } + { + name: pwr_rst + struct: pwr_rst + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_rst + index: -1 + } + { + name: pwr_clk + struct: pwr_clk + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_clk + index: -1 + } + { + name: pwr_otp + struct: pwr_otp + package: pwrmgr_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_otp + index: -1 + } + { + name: pwr_lc + struct: pwr_lc + package: lc_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_pwr_lc + index: -1 + } + { + name: pwr_flash + struct: pwr_flash + package: pwrmgr_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: esc_rst_tx + struct: esc_tx + package: prim_esc_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: alert_handler_esc_tx + index: 2 + } + { + name: esc_rst_rx + struct: esc_rx + package: prim_esc_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: alert_handler_esc_rx + index: 2 + } + { + name: pwr_cpu + struct: cpu_pwrmgr + package: rv_core_ibex_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: wakeups + struct: logic + type: uni + act: rcv + width: 4 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_wakeups + index: -1 + } + { + name: rstreqs + struct: logic + type: uni + act: rcv + width: 2 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_rstreqs + index: -1 + } + { + name: ndmreset_req + struct: logic + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: strap + struct: logic + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_strap + index: -1 + } + { + name: low_power + struct: logic + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: rom_ctrl + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: rcv + width: 3 + default: rom_ctrl_pkg::PWRMGR_DATA_DEFAULT + inst_name: pwrmgr_aon + end_idx: -1 + top_type: one-to-N + top_signame: pwrmgr_aon_rom_ctrl + index: -1 + } + { + name: fetch_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: pwrmgr_aon + index: -1 + } + { + name: lc_dft_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: sw_rst_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: pwrmgr_aon + default: "" + top_signame: rstmgr_aon_sw_rst_req + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: pwrmgr_aon + default: "" + end_idx: -1 + top_signame: pwrmgr_aon_tl + index: -1 + } + { + name: por_n + desc: + ''' + Root power on reset signals from ast. + There is one root reset signal for each core power domain. + ''' + struct: logic + type: uni + act: rcv + width: 2 + inst_name: rstmgr_aon + default: "" + package: "" + external: true + top_signame: por_n + conn_type: false + index: -1 + } + { + name: pwr + desc: + ''' + Reset request signals from power manager. + Power manager can request for specific domains of the lc/sys reset tree to assert. + ''' + struct: pwr_rst + type: req_rsp + act: rsp + width: 1 + inst_name: rstmgr_aon + default: "" + package: pwrmgr_pkg + top_signame: pwrmgr_aon_pwr_rst + index: -1 + } + { + name: resets + desc: Leaf resets fed to the system. + struct: rstmgr_out + package: rstmgr_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rstmgr_aon_resets + index: -1 + } + { + name: rst_en + desc: Low-power-group outputs used by alert handler. + struct: rstmgr_rst_en + package: rstmgr_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: rstmgr_aon_rst_en + index: -1 + } + { + name: alert_dump + desc: Alert handler crash dump information. + struct: alert_crashdump + package: alert_handler_pkg + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + default: "" + top_signame: alert_handler_crashdump + index: -1 + } + { + name: cpu_dump + desc: Main processing element crash dump information. + struct: cpu_crash_dump + package: rv_core_ibex_pkg + type: uni + act: rcv + width: 1 + inst_name: rstmgr_aon + index: -1 + } + { + name: sw_rst_req + desc: Software requested system reset to pwrmgr. + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: rstmgr_aon + default: "" + end_idx: -1 + top_type: broadcast + top_signame: rstmgr_aon_sw_rst_req + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rstmgr_aon + default: "" + end_idx: -1 + top_signame: rstmgr_aon_tl + index: -1 + } + { + name: clocks + struct: clkmgr_out + package: clkmgr_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: clkmgr_aon_clocks + index: -1 + } + { + name: cg_en + struct: clkmgr_cg_en + package: clkmgr_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: clkmgr_aon_cg_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: io_clk_byp_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: io_clk_byp_req + conn_type: false + index: -1 + } + { + name: io_clk_byp_ack + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: io_clk_byp_ack + conn_type: false + index: -1 + } + { + name: all_clk_byp_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: all_clk_byp_req + conn_type: false + index: -1 + } + { + name: all_clk_byp_ack + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: all_clk_byp_ack + conn_type: false + index: -1 + } + { + name: hi_speed_sel + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: hi_speed_sel + conn_type: false + index: -1 + } + { + name: div_step_down_req + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: div_step_down_req + conn_type: false + index: -1 + } + { + name: lc_clk_byp_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_clk_byp_req + index: -1 + } + { + name: lc_clk_byp_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + top_signame: lc_ctrl_lc_clk_byp_ack + index: -1 + } + { + name: jitter_en + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: clkmgr_aon + default: "" + external: true + top_signame: clk_main_jitter_en + conn_type: false + index: -1 + } + { + name: pwr + struct: pwr_clk + type: req_rsp + act: rsp + width: 1 + inst_name: clkmgr_aon + default: "" + package: pwrmgr_pkg + top_signame: pwrmgr_aon_pwr_clk + index: -1 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 4 + inst_name: clkmgr_aon + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: clkmgr_aon_idle + index: -1 + } + { + name: calib_rdy + desc: Indicates clocks are calibrated and frequencies accurate + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi4True + inst_name: clkmgr_aon + external: true + top_signame: calib_rdy + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: clkmgr_aon + default: "" + end_idx: -1 + top_signame: clkmgr_aon_tl + index: -1 + } + { + name: sleep_en + desc: Level signal that is asserted when the power manager enters sleep. + struct: logic + type: uni + act: rcv + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: pin_wkup_req + desc: Wakeup request from wakeup detectors, to the power manager, running on the AON clock. + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: pinmux_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 0 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: pinmux_aon + default: "" + end_idx: -1 + top_signame: pinmux_aon_tl + index: -1 + } + { + name: nmi_wdog_timer_bark + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + index: -1 + } + { + name: wkup_req + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + top_signame: pwrmgr_aon_wakeups + index: 1 + } + { + name: aon_timer_rst_req + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: aon_timer_aon + package: "" + top_signame: pwrmgr_aon_rstreqs + index: 0 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: aon_timer_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: sleep_mode + struct: logic + type: uni + act: rcv + width: 1 + inst_name: aon_timer_aon + default: "" + package: "" + top_signame: pwrmgr_aon_low_power + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: aon_timer_aon + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: aon_timer_aon + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: aon_timer_aon + default: "" + end_idx: -1 + top_signame: aon_timer_aon_tl + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: ast + index: -1 + } + { + name: dma_tl_h2d + desc: TL-UL host port for the DMA to egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_type: broadcast + top_signame: soc_proxy_dma_tl_h2d + index: -1 + } + { + name: dma_tl_d2h + desc: TL-UL host port for the DMA to egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_type: broadcast + top_signame: soc_proxy_dma_tl_d2h + index: -1 + } + { + name: misc_tl_h2d + desc: TL-UL host port for the MISC to egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + external: true + top_signame: ctn_misc_tl_h2d + conn_type: false + index: -1 + } + { + name: misc_tl_d2h + desc: TL-UL host port for the MISC to egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + external: true + top_signame: ctn_misc_tl_d2h + conn_type: false + index: -1 + } + { + name: wkup_internal_req + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 2 + } + { + name: wkup_external_req + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_wakeups + index: 3 + } + { + name: rst_req_external + struct: logic + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: pwrmgr_aon_rstreqs + index: 1 + } + { + name: ctn_tl_h2d + desc: TL-UL host port for egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_type: broadcast + top_signame: soc_proxy_ctn_tl_h2d + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL host port for egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_type: broadcast + top_signame: soc_proxy_ctn_tl_d2h + index: -1 + } + { + name: i2c_lsio_trigger + desc: LSIO trigger signal from I2C + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: i2c0_lsio_trigger + index: -1 + } + { + name: spi_host_lsio_trigger + desc: LSIO trigger signal from SPI Host + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: spi_host0_lsio_trigger + index: -1 + } + { + name: uart_lsio_trigger + desc: LSIO trigger signal from UART + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + top_signame: uart0_lsio_trigger + index: -1 + } + { + name: soc_lsio_trigger + desc: LSIO trigger signal from SoC, synchronous + struct: logic + type: uni + act: rcv + width: 8 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_lsio_trigger + conn_type: false + index: -1 + } + { + name: dma_lsio_trigger + desc: Collated synchronous LSIO trigger signals for DMA + struct: lsio_trigger + package: dma_pkg + type: uni + act: req + width: 1 + inst_name: soc_proxy + default: "" + top_signame: dma_lsio_trigger + index: -1 + } + { + name: soc_fatal_alert + desc: Differential fatal alert from SoC, synchronous + struct: soc_alert + package: soc_proxy_pkg + type: req_rsp + act: rsp + width: 24 + inst_name: soc_proxy + default: "" + external: true + top_signame: soc_fatal_alert + conn_type: false + index: -1 + } + { + name: soc_recov_alert + desc: Differential recoverable alert from SoC, synchronous + struct: soc_alert + package: soc_proxy_pkg + type: req_rsp + act: rsp + width: 4 + inst_name: soc_proxy + default: "" + external: true + top_signame: soc_recov_alert + conn_type: false + index: -1 + } + { + name: soc_wkup_async + desc: Wakeup request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_wkup_async + conn_type: false + index: -1 + } + { + name: soc_rst_req_async + desc: Reset request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_rst_req_async + conn_type: false + index: -1 + } + { + name: soc_intr_async + desc: Interrupt request from SoC, asynchronous, level-encoded + struct: logic + type: uni + act: rcv + width: 32 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_intr_async + conn_type: false + index: -1 + } + { + name: soc_gpi_async + desc: GPI from SoC, async + struct: logic + type: uni + act: req + width: 16 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_gpi_async + conn_type: false + index: -1 + } + { + name: soc_gpo_async + desc: GPO from SoC, async + struct: logic + type: uni + act: rcv + width: 16 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: soc_gpo_async + conn_type: false + index: -1 + } + { + name: integrator_id + desc: Integrator ID signal used in BAT + struct: logic + type: uni + act: rcv + width: 4 + inst_name: soc_proxy + default: "" + package: "" + external: true + top_signame: integrator_id + conn_type: false + index: -1 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_proxy + index: -1 + } + { + name: ctn_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_proxy + default: "" + end_idx: -1 + top_signame: soc_proxy_ctn_tl + index: -1 + } + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 1 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } + default: "'0" + inst_name: sram_ctrl_ret_aon + external: true + top_signame: sram_ctrl_ret_aon_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } + default: "'0" + inst_name: sram_ctrl_ret_aon + external: true + top_signame: sram_ctrl_ret_aon_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_ret_aon + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: sram_rerror + desc: SRAM read error indicating correctable and uncorrectable ECC errors. + struct: sram_error_t + package: sram_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_ret_aon + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + end_idx: -1 + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_ret_aon + default: "" + end_idx: -1 + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + { + name: irq + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + external: true + top_signame: no_ibex_irq + conn_type: false + index: -1 + } + { + name: irq_id + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + index: -1 + } + { + name: msip + struct: logic + type: uni + act: req + width: 1 + inst_name: rv_plic + default: "" + package: "" + external: true + top_signame: no_ibex_msip + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rv_plic + index: -1 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: aes + default: "" + top_signame: clkmgr_aon_idle + index: 0 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: aes + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: aes + default: "" + top_signame: edn0_edn + index: 4 + } + { + name: keymgr_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: aes + default: "" + top_signame: keymgr_dpe_aes_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: aes + default: "" + end_idx: -1 + top_signame: aes_tl + index: -1 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: hmac + default: "" + top_signame: clkmgr_aon_idle + index: 1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: hmac + default: "" + end_idx: -1 + top_signame: hmac_tl + index: -1 + } + { + name: keymgr_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: kmac + default: "" + top_signame: keymgr_dpe_kmac_key + index: -1 + } + { + name: app + struct: app + package: kmac_pkg + type: req_rsp + act: rsp + width: + { + name: NumAppIntf + desc: Number of application interfaces + param_type: int + unpacked_dimensions: null + default: 3 + local: false + expose: true + name_top: KmacNumAppIntf + } + inst_name: kmac + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: kmac_app + index: -1 + } + { + name: entropy + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: kmac + default: "" + top_signame: edn0_edn + index: 2 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: kmac + default: "" + top_signame: clkmgr_aon_idle + index: 2 + } + { + name: en_masking + struct: logic + type: uni + act: req + width: 1 + inst_name: kmac + default: "" + package: "" + end_idx: -1 + top_type: broadcast + top_signame: kmac_en_masking + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: kmac + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: kmac + default: "" + end_idx: -1 + top_signame: kmac_tl + index: -1 + } + { + name: otbn_otp_key + struct: otbn_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + default: "'0" + inst_name: otbn + top_signame: otp_ctrl_otbn_otp_key + index: -1 + } + { + name: edn_rnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: edn1_edn + index: 0 + } + { + name: edn_urnd + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: edn0_edn + index: 5 + } + { + name: idle + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: req + width: 1 + inst_name: otbn + default: "" + top_signame: clkmgr_aon_idle + index: 3 + } + { + name: ram_cfg_imem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + external: true + top_signame: otbn_imem_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: ram_cfg_dmem + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + external: true + top_signame: otbn_dmem_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_imem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: otbn + default: "" + external: true + top_signame: otbn_imem_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: ram_cfg_rsp_dmem + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: 1 + inst_name: otbn + default: "" + external: true + top_signame: otbn_dmem_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_rma_req + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + top_signame: lc_ctrl_lc_flash_rma_req + index: -1 + } + { + name: lc_rma_ack + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: req + width: 1 + default: lc_ctrl_pkg::Off + inst_name: otbn + end_idx: -1 + top_type: broadcast + top_signame: otbn_lc_rma_ack + index: -1 + } + { + name: keymgr_key + struct: otbn_key_req + package: keymgr_pkg + type: uni + act: rcv + width: 1 + inst_name: otbn + default: "" + top_signame: keymgr_dpe_otbn_key + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: otbn + default: "" + end_idx: -1 + top_signame: otbn_tl + index: -1 + } + { + name: edn + struct: edn + package: edn_pkg + type: req_rsp + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: edn0_edn + index: 0 + } + { + name: aes_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_aes_key + index: -1 + } + { + name: kmac_key + struct: hw_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_kmac_key + index: -1 + } + { + name: otbn_key + struct: otbn_key_req + package: keymgr_pkg + type: uni + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_type: broadcast + top_signame: keymgr_dpe_otbn_key + index: -1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: kmac_app + index: 0 + } + { + name: otp_key + struct: otp_keymgr_key + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: otp_ctrl_otp_keymgr_key + index: -1 + } + { + name: otp_device_id + struct: otp_device_id + package: otp_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: keymgr_dpe_otp_device_id + index: -1 + } + { + name: lc_keymgr_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::On + inst_name: keymgr_dpe + top_signame: lc_ctrl_lc_keymgr_en + index: -1 + } + { + name: lc_keymgr_div + struct: lc_keymgr_div + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + top_signame: lc_ctrl_lc_keymgr_div + index: -1 + } + { + name: rom_digest + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: rcv + width: 2 + default: rom_ctrl_pkg::KEYMGR_DATA_DEFAULT + inst_name: keymgr_dpe + end_idx: -1 + top_type: one-to-N + top_signame: keymgr_dpe_rom_digest + index: -1 + } + { + name: kmac_en_masking + struct: logic + type: uni + act: rcv + width: 1 + inst_name: keymgr_dpe + default: "" + package: "" + top_signame: kmac_en_masking + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: keymgr_dpe + default: "" + end_idx: -1 + top_signame: keymgr_dpe_tl + index: -1 + } + { + name: csrng_cmd + struct: csrng + package: csrng_pkg + type: req_rsp + act: rsp + width: 2 + inst_name: csrng + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: csrng_csrng_cmd + index: -1 + } + { + name: entropy_src_hw_if + struct: entropy_src_hw_if + package: entropy_src_pkg + type: req_rsp + act: req + width: 1 + inst_name: csrng + default: "" + end_idx: -1 + top_signame: csrng_entropy_src_hw_if + index: -1 + } + { + name: cs_aes_halt + desc: + ''' + Coordinate activity between CSRNG's AES and Entropy Source's SHA3. + When CSRNG gets a request and its AES is not active, it acknowledges and until the request has dropped neither runs its AES nor drops the acknowledge. + ''' + struct: cs_aes_halt + package: entropy_src_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: csrng + default: "" + end_idx: -1 + top_signame: csrng_cs_aes_halt + index: -1 + } + { + name: otp_en_csrng_sw_app_read + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8True + inst_name: csrng + top_signame: csrng_otp_en_csrng_sw_app_read + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: csrng + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: csrng + index: -1 + } + { + name: entropy_src_hw_if + struct: entropy_src_hw_if + package: entropy_src_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: entropy_src + default: "" + top_signame: csrng_entropy_src_hw_if + index: -1 + } + { + name: cs_aes_halt + desc: + ''' + Coordinate activity between CSRNG's AES and Entropy Source's SHA3. + The idea is that Entropy Source requests CSRNG's AES to halt and waits for CSRNG to acknowledge before it starts its SHA3. + While SHA3 runs, Entropy Source keeps the request high. + CSRNG may not drop the acknowledge before Entropy Source drops the request. + ''' + struct: cs_aes_halt + package: entropy_src_pkg + type: req_rsp + act: req + width: 1 + inst_name: entropy_src + default: "" + top_signame: csrng_cs_aes_halt + index: -1 + } + { + name: entropy_src_rng_enable + desc: + ''' + Signal through which entropy_src enables the noise source. + entropy_src will keep this signal high as long as it expects the noise source to operate. + This is *not* a flow control signal through which entropy_src would exert backpressure on the noise source; rather this signal stays high while entropy_src is enabled. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: entropy_src + default: "" + package: "" + external: true + top_signame: es_rng_enable + conn_type: false + index: -1 + } + { + name: entropy_src_rng_valid + desc: + ''' + Acknowledgement signal from the noise source. + When '1', it indicates that the `entropy_src_rng_bit` data is valid and ready to be consumed. + ''' + struct: logic + type: uni + act: rcv + width: 1 + inst_name: entropy_src + default: "" + package: "" + external: true + top_signame: es_rng_valid + conn_type: false + index: -1 + } + { + name: entropy_src_rng_bits + desc: + ''' + Output data bus carrying the raw entropy bits from the noise source. + These bits are valid when `entropy_src_rng_valid` is asserted. + The width is determined by `RngBusWidth` parametrization. + ''' + struct: logic + type: uni + act: rcv + width: + { + name: RngBusWidth + desc: + ''' + Defines the bit-width of the noise source data. + Must be between 4 and 256 (inclusive) and divisible by 4. + The divisibility by 4 is a prerequisite for the bucket health test. + ''' + param_type: int + unpacked_dimensions: null + default: 4 + local: false + expose: true + name_top: EntropySrcRngBusWidth + } + inst_name: entropy_src + default: "" + package: "" + external: true + top_signame: es_rng_bit + conn_type: false + index: -1 + } + { + name: entropy_src_xht_valid + desc: + ''' + Valid signal for the external health test interface. + When asserted, it indicates that `entropy_src_xht_bits`, `entropy_src_xht_bit_sel`, and `entropy_src_xht_meta` are valid for consumption by the external health test. + ''' + struct: logic + type: uni + act: req + width: 1 + inst_name: entropy_src + index: -1 + } + { + name: entropy_src_xht_bits + desc: + ''' + Carries the raw entropy data from the entropy source to be consumed by the external health test module. + The data on this bus is valid when `entropy_src_xht_valid` is asserted. + The width is determined by `RngBusWidth` parametrization. + ''' + struct: logic + type: uni + act: req + width: + { + name: RngBusWidth + desc: + ''' + Defines the bit-width of the noise source data. + Must be between 4 and 256 (inclusive) and divisible by 4. + The divisibility by 4 is a prerequisite for the bucket health test. + ''' + param_type: int + unpacked_dimensions: null + default: 4 + local: false + expose: true + name_top: EntropySrcRngBusWidth + } + inst_name: entropy_src + index: -1 + } + { + name: entropy_src_xht_bit_sel + desc: + ''' + Provides bit selection information for the raw entropy data. + It specifies which specific bit or subset of bits from `entropy_src_xht_bit` should be used. + The width is determined by `RngBusBitSelWidth` parametrization. + ''' + struct: logic + type: uni + act: req + width: + { + name: RngBusBitSelWidth + desc: Explicit parameter defining the width of the RNG bit selection vector (log2(RngBusWidth)) + param_type: int + unpacked_dimensions: null + default: 2 + local: false + expose: true + name_top: EntropySrcRngBusBitSelWidth + } + inst_name: entropy_src + index: -1 + } + { + name: entropy_src_xht_health_test_window + desc: Provides the window size of the health in bits. + struct: logic + type: uni + act: req + width: + { + name: HealthTestWindowWidth + desc: Explicit parameter defining the width of the health test window (16 + log2(RngBusWidth)) + param_type: int + unpacked_dimensions: null + default: 18 + local: false + expose: true + name_top: EntropySrcHealthTestWindowWidth + } + inst_name: entropy_src + index: -1 + } + { + name: entropy_src_xht_meta + struct: entropy_src_xht_meta + package: entropy_src_pkg + type: req_rsp + act: req + width: 1 + inst_name: entropy_src + index: -1 + } + { + name: otp_en_entropy_src_fw_read + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8True + inst_name: entropy_src + index: -1 + } + { + name: otp_en_entropy_src_fw_over + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8True + inst_name: entropy_src + index: -1 + } + { + name: rng_fips + struct: logic + type: uni + act: req + width: 1 + inst_name: entropy_src + default: "" + package: "" + external: true + top_signame: es_rng_fips + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: entropy_src + index: -1 + } + { + name: csrng_cmd + desc: EDN supports a signal CSRNG application interface. + struct: csrng + package: csrng_pkg + type: req_rsp + act: req + width: 1 + inst_name: edn0 + default: "" + top_signame: csrng_csrng_cmd + index: 0 + } + { + name: edn + desc: + ''' + The collection of peripheral ports supported by edn. The width (4) + indicates the number of peripheral ports on a single instance. + Due to limitations in the parametrization of top-level interconnects + this value is not currently parameterizable. However, the number + of peripheral ports may change in a future revision. + ''' + struct: edn + package: edn_pkg + type: req_rsp + act: rsp + width: 8 + default: "'0" + inst_name: edn0 + end_idx: 6 + top_type: partial-one-to-N + top_signame: edn0_edn + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: edn0 + index: -1 + } + { + name: csrng_cmd + desc: EDN supports a signal CSRNG application interface. + struct: csrng + package: csrng_pkg + type: req_rsp + act: req + width: 1 + inst_name: edn1 + default: "" + top_signame: csrng_csrng_cmd + index: 1 + } + { + name: edn + desc: + ''' + The collection of peripheral ports supported by edn. The width (4) + indicates the number of peripheral ports on a single instance. + Due to limitations in the parametrization of top-level interconnects + this value is not currently parameterizable. However, the number + of peripheral ports may change in a future revision. + ''' + struct: edn + package: edn_pkg + type: req_rsp + act: rsp + width: 8 + default: "'0" + inst_name: edn1 + end_idx: 1 + top_type: partial-one-to-N + top_signame: edn1_edn + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: edn1 + index: -1 + } + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_main + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 0 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } + default: "'0" + inst_name: sram_ctrl_main + external: true + top_signame: sram_ctrl_main_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } + default: "'0" + inst_name: sram_ctrl_main + external: true + top_signame: sram_ctrl_main_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_main + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_main + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_main + top_signame: sram_ctrl_main_otp_en_sram_ifetch + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: sram_ctrl_main + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_main + index: -1 + } + { + name: sram_rerror + desc: SRAM read error indicating correctable and uncorrectable ECC errors. + struct: sram_error_t + package: sram_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_main + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_main + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_main + default: "" + end_idx: -1 + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + { + name: sram_otp_key + struct: sram_otp_key + package: otp_ctrl_pkg + type: req_rsp + act: req + width: 1 + inst_name: sram_ctrl_mbox + default: "" + top_signame: otp_ctrl_sram_otp_key + index: 2 + } + { + name: cfg + struct: ram_1p_cfg + package: prim_ram_1p_pkg + type: uni + act: rcv + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } + default: "'0" + inst_name: sram_ctrl_mbox + external: true + top_signame: sram_ctrl_mbox_ram_1p_cfg + conn_type: false + index: -1 + } + { + name: cfg_rsp + struct: ram_1p_cfg_rsp + package: prim_ram_1p_pkg + type: uni + act: req + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } + default: "'0" + inst_name: sram_ctrl_mbox + external: true + top_signame: sram_ctrl_mbox_ram_1p_cfg_rsp + conn_type: false + index: -1 + } + { + name: lc_escalate_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_mbox + top_signame: lc_ctrl_lc_escalate_en + index: -1 + } + { + name: lc_hw_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: otp_en_sram_ifetch + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + default: prim_mubi_pkg::MuBi8False + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: sram_rerror + desc: SRAM read error indicating correctable and uncorrectable ECC errors. + struct: sram_error_t + package: sram_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_mbox + index: -1 + } + { + name: ram_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: sram_ctrl_mbox + default: "" + end_idx: -1 + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + { + name: rom_cfg + struct: rom_cfg + package: prim_rom_pkg + type: uni + act: rcv + width: 1 + inst_name: rom_ctrl0 + default: "" + external: true + top_signame: rom_ctrl0_cfg + conn_type: false + index: -1 + } + { + name: pwrmgr_data + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: 0 + } + { + name: keymgr_data + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: keymgr_dpe_rom_digest + index: 0 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: rom_ctrl0 + default: "" + top_signame: kmac_app + index: 2 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl0 + index: -1 + } + { + name: rom_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl0 + index: -1 + } + { + name: rom_cfg + struct: rom_cfg + package: prim_rom_pkg + type: uni + act: rcv + width: 1 + inst_name: rom_ctrl1 + default: "" + external: true + top_signame: rom_ctrl1_cfg + conn_type: false + index: -1 + } + { + name: pwrmgr_data + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: 1 + } + { + name: keymgr_data + struct: keymgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: keymgr_dpe_rom_digest + index: 1 + } + { + name: kmac_data + struct: app + package: kmac_pkg + type: req_rsp + act: req + width: 1 + inst_name: rom_ctrl1 + default: "" + top_signame: kmac_app + index: 3 + } + { + name: regs_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl1 + index: -1 + } + { + name: rom_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: rom_ctrl1 + index: -1 + } + { + name: lsio_trigger + struct: lsio_trigger + package: dma_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + default: "" + end_idx: -1 + top_type: broadcast + top_signame: dma_lsio_trigger + index: -1 + } + { + name: sys + struct: sys + package: dma_pkg + type: req_rsp + act: req + width: 1 + inst_name: dma + default: "" + external: true + top_signame: dma_sys + conn_type: false + index: -1 + } + { + name: ctn_tl_h2d + desc: TL-UL host port for egress into CTN (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: dma + default: "" + top_signame: soc_proxy_dma_tl_h2d + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL host port for egress into CTN (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + default: "" + top_signame: soc_proxy_dma_tl_d2h + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: dma + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: dma + index: -1 + } + { + name: host_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: dma + default: "" + top_signame: main_tl_dma__host + index: -1 + } + { + name: tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: dma + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx0 + package: "" + external: true + top_signame: mbx0_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx0 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx0 + default: "" + top_signame: racl_ctrl_racl_error + index: 0 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx0 + default: "" + top_signame: main_tl_mbx0__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx0 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx0 + default: "" + end_idx: -1 + top_signame: mbx0_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx1 + package: "" + external: true + top_signame: mbx1_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx1 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx1 + default: "" + top_signame: racl_ctrl_racl_error + index: 1 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx1 + default: "" + top_signame: main_tl_mbx1__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx1 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx1 + default: "" + end_idx: -1 + top_signame: mbx1_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx2 + package: "" + external: true + top_signame: mbx2_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx2 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx2 + default: "" + top_signame: racl_ctrl_racl_error + index: 2 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx2 + default: "" + top_signame: main_tl_mbx2__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx2 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx2 + default: "" + end_idx: -1 + top_signame: mbx2_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx3 + package: "" + external: true + top_signame: mbx3_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx3 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx3 + default: "" + top_signame: racl_ctrl_racl_error + index: 3 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx3 + default: "" + top_signame: main_tl_mbx3__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx3 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx3 + default: "" + end_idx: -1 + top_signame: mbx3_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx4 + package: "" + external: true + top_signame: mbx4_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx4 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx4 + default: "" + top_signame: racl_ctrl_racl_error + index: 4 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx4 + default: "" + top_signame: main_tl_mbx4__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx4 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx4 + default: "" + end_idx: -1 + top_signame: mbx4_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx5 + package: "" + external: true + top_signame: mbx5_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx5 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx5 + default: "" + top_signame: racl_ctrl_racl_error + index: 5 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx5 + default: "" + top_signame: main_tl_mbx5__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx5 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx5 + default: "" + end_idx: -1 + top_signame: mbx5_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx6 + package: "" + external: true + top_signame: mbx6_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx6 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx6 + default: "" + top_signame: racl_ctrl_racl_error + index: 6 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx6 + default: "" + top_signame: main_tl_mbx6__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx6 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx6 + default: "" + end_idx: -1 + top_signame: mbx6_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_jtag + package: "" + external: true + top_signame: mbx_jtag_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx_jtag + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx_jtag + default: "" + top_signame: racl_ctrl_racl_error + index: 7 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_jtag + default: "" + top_signame: main_tl_mbx_jtag__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_jtag + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_jtag + default: "" + end_idx: -1 + top_signame: mbx_jtag_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie0 + package: "" + external: true + top_signame: mbx_pcie0_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx_pcie0 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx_pcie0 + default: "" + top_signame: racl_ctrl_racl_error + index: 8 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_pcie0 + default: "" + top_signame: main_tl_mbx_pcie0__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie0 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie0 + default: "" + end_idx: -1 + top_signame: mbx_pcie0_soc_tl_d + index: -1 + } + { + name: doe_intr_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr_support + conn_type: false + index: -1 + } + { + name: doe_intr_en + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr_en + conn_type: false + index: -1 + } + { + name: doe_intr + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_intr + conn_type: false + index: -1 + } + { + name: doe_async_msg_support + struct: logic + type: uni + act: req + width: 1 + default: 1'b0 + inst_name: mbx_pcie1 + package: "" + external: true + top_signame: mbx_pcie1_doe_async_msg_support + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: mbx_pcie1 + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: mbx_pcie1 + default: "" + top_signame: racl_ctrl_racl_error + index: 9 + } + { + name: sram_tl_h + struct: tl + package: tlul_pkg + type: req_rsp + act: req + width: 1 + inst_name: mbx_pcie1 + default: "" + top_signame: main_tl_mbx_pcie1__sram + index: -1 + } + { + name: core_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie1 + index: -1 + } + { + name: soc_tl_d + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: mbx_pcie1 + default: "" + end_idx: -1 + top_signame: mbx_pcie1_soc_tl_d + index: -1 + } + { + name: boot_status + struct: pwr_boot_status + package: pwrmgr_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_dbg_ctrl + default: "" + top_signame: pwrmgr_aon_boot_status + index: -1 + } + { + name: soc_dbg_state + struct: soc_dbg_state + package: lc_ctrl_state_pkg + type: uni + act: rcv + width: 1 + inst_name: soc_dbg_ctrl + default: "" + top_signame: soc_dbg_ctrl_soc_dbg_state + index: -1 + } + { + name: soc_dbg_policy_bus + struct: soc_dbg_policy + package: soc_dbg_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: soc_dbg_ctrl + default: "" + external: true + top_signame: soc_dbg_policy_bus + conn_type: false + index: -1 + } + { + name: lc_hw_debug_en + desc: Multibit life cycle hardware debug enable signal coming from life cycle controller, asserted when the hardware debug mechanisms are enabled in the system. + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: soc_dbg_ctrl + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + } + { + name: lc_dft_en + desc: + ''' + Test enable qualifier coming from life cycle controller. + This signals enables TEST & RMA mode accesses. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: soc_dbg_ctrl + top_signame: lc_ctrl_lc_dft_en + index: -1 + } + { + name: lc_raw_test_rma + desc: + ''' + Test enable qualifier coming from life cycle controller. + This signals enables RAW, TEST and RMA mode accesses. + ''' + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + default: lc_ctrl_pkg::Off + inst_name: soc_dbg_ctrl + top_signame: lc_ctrl_lc_raw_test_rma + index: -1 + } + { + name: halt_cpu_boot + desc: External request to halt the CPU until a JTAG command allows the boot process to continue. + struct: logic + type: uni + act: rcv + width: 1 + inst_name: soc_dbg_ctrl + default: "" + package: "" + external: true + top_signame: debug_halt_cpu_boot + conn_type: false + index: -1 + } + { + name: continue_cpu_boot + desc: Artificial ROM control input to the pwrmgr to halt the boot process. + struct: pwrmgr_data + package: rom_ctrl_pkg + type: uni + act: req + width: 1 + inst_name: soc_dbg_ctrl + default: "" + top_signame: pwrmgr_aon_rom_ctrl + index: 2 + } + { + name: core_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_dbg_ctrl + default: "" + end_idx: -1 + top_signame: soc_dbg_ctrl_core_tl + index: -1 + } + { + name: jtag_tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: soc_dbg_ctrl + default: "" + end_idx: -1 + top_signame: soc_dbg_ctrl_jtag_tl + index: -1 + } + { + name: racl_policies + desc: Policy vector distributed to the subscribing RACL IPs. + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: racl_ctrl + default: "" + end_idx: -1 + top_type: broadcast + top_signame: racl_ctrl_racl_policies + index: -1 + external: true + conn_type: true + } + { + name: racl_error + desc: + ''' + Error log information from all IPs. + Only one IP can raise an error at a time. + ''' + struct: racl_error_log + package: top_racl_pkg + type: uni + act: rcv + width: + { + name: NumSubscribingIps + desc: Number of subscribing RACL IPs + param_type: int + unpacked_dimensions: null + default: 11 + local: true + expose: true + name_top: RaclCtrlNumSubscribingIps + } + inst_name: racl_ctrl + default: "" + end_idx: -1 + top_type: one-to-N + top_signame: racl_ctrl_racl_error + index: -1 + } + { + name: racl_error_external + desc: + ''' + Error log information from all external IPs. + Only one IP can raise an error at a time. + ''' + struct: racl_error_log + package: top_racl_pkg + type: uni + act: rcv + width: + { + name: NumExternalSubscribingIps + desc: Number of external subscribing RACL IPs + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: RaclCtrlNumExternalSubscribingIps + } + inst_name: racl_ctrl + default: "" + external: true + top_signame: racl_error + conn_type: false + index: -1 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: racl_ctrl + default: "" + end_idx: -1 + top_signame: racl_ctrl_tl + index: -1 + } + { + name: range_check_overwrite + desc: Overwrites all ranges and let all requests pass through. + struct: mubi8 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: ac_range_check + default: "" + external: true + top_signame: ac_range_check_overwrite + conn_type: false + index: -1 + } + { + name: ctn_tl_h2d + desc: TL-UL input port (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: ac_range_check + default: "" + top_signame: soc_proxy_ctn_tl_h2d + index: -1 + } + { + name: ctn_tl_d2h + desc: TL-UL input port (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: ac_range_check + default: "" + top_signame: soc_proxy_ctn_tl_d2h + index: -1 + } + { + name: ctn_filtered_tl_h2d + desc: Filtered TL-UL output port (request part), synchronous + struct: tl_h2d + package: tlul_pkg + type: uni + act: req + width: 1 + inst_name: ac_range_check + default: "" + external: true + top_signame: ctn_tl_h2d + conn_type: false + index: -1 + } + { + name: ctn_filtered_tl_d2h + desc: Filtered TL-UL output port (response part), synchronous + struct: tl_d2h + package: tlul_pkg + type: uni + act: rcv + width: 1 + inst_name: ac_range_check + default: "" + external: true + top_signame: ctn_tl_d2h + conn_type: false + index: -1 + } + { + name: racl_policies + desc: + ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + struct: racl_policy_vec + package: top_racl_pkg + type: uni + act: rcv + width: 1 + inst_name: ac_range_check + default: "" + top_signame: racl_ctrl_racl_policies + index: -1 + } + { + name: racl_error + desc: RACL error log information of this module. + struct: racl_error_log + package: top_racl_pkg + type: uni + act: req + width: 1 + inst_name: ac_range_check + default: "" + top_signame: racl_ctrl_racl_error + index: 10 + } + { + name: tl + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: ac_range_check + default: "" + end_idx: -1 + top_signame: ac_range_check_tl + index: -1 + } + { + name: tl_dma__host + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_dma__host + index: -1 + } + { + name: tl_mbx0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx0__sram + index: -1 + } + { + name: tl_mbx1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx1__sram + index: -1 + } + { + name: tl_mbx2__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx2__sram + index: -1 + } + { + name: tl_mbx3__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx3__sram + index: -1 + } + { + name: tl_mbx4__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx4__sram + index: -1 + } + { + name: tl_mbx5__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx5__sram + index: -1 + } + { + name: tl_mbx6__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx6__sram + index: -1 + } + { + name: tl_mbx_jtag__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx_jtag__sram + index: -1 + } + { + name: tl_mbx_pcie0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie0__sram + index: -1 + } + { + name: tl_mbx_pcie1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie1__sram + index: -1 + } + { + name: tl_peri + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_peri + index: -1 + } + { + name: tl_soc_proxy__ctn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: soc_proxy_ctn_tl + index: -1 + } + { + name: tl_hmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: hmac_tl + index: -1 + } + { + name: tl_kmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: kmac_tl + index: -1 + } + { + name: tl_aes + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: aes_tl + index: -1 + } + { + name: tl_otbn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: otbn_tl + index: -1 + } + { + name: tl_keymgr_dpe + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: keymgr_dpe_tl + index: -1 + } + { + name: tl_sram_ctrl_main__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + { + name: tl_sram_ctrl_mbox__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + { + name: tl_main + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: peri + width: 1 + default: "" + top_signame: main_tl_peri + index: -1 + } + { + name: tl_uart0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: uart0_tl + index: -1 + } + { + name: tl_i2c0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: i2c0_tl + index: -1 + } + { + name: tl_gpio + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: gpio_tl + index: -1 + } + { + name: tl_spi_host0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: spi_host0_tl + index: -1 + } + { + name: tl_spi_device + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: spi_device_tl + index: -1 + } + { + name: tl_pwrmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: pwrmgr_aon_tl + index: -1 + } + { + name: tl_rstmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: rstmgr_aon_tl + index: -1 + } + { + name: tl_clkmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: clkmgr_aon_tl + index: -1 + } + { + name: tl_pinmux_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: pinmux_aon_tl + index: -1 + } + { + name: tl_otp_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: otp_ctrl_core_tl + index: -1 + } + { + name: tl_otp_macro__prim + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: otp_macro_prim_tl + index: -1 + } + { + name: tl_lc_ctrl__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: tl_alert_handler + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: alert_handler_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + { + name: tl_aon_timer_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: aon_timer_aon_tl + index: -1 + } + { + name: tl_ast + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + external: true + top_signame: ast_tl + conn_type: false + index: -1 + } + { + name: tl_soc_dbg_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: soc_dbg_ctrl_core_tl + index: -1 + } + { + name: tl_mbx + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: mbx + width: 1 + default: "" + external: true + top_signame: mbx_tl + conn_type: false + index: -1 + } + { + name: tl_mbx0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx0_soc_tl_d + index: -1 + } + { + name: tl_mbx1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx1_soc_tl_d + index: -1 + } + { + name: tl_mbx2__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx2_soc_tl_d + index: -1 + } + { + name: tl_mbx3__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx3_soc_tl_d + index: -1 + } + { + name: tl_mbx4__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx4_soc_tl_d + index: -1 + } + { + name: tl_mbx5__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx5_soc_tl_d + index: -1 + } + { + name: tl_mbx6__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx6_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx_pcie0_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx_pcie1_soc_tl_d + index: -1 + } + { + name: tl_racl_ctrl + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: racl_ctrl_tl + index: -1 + } + { + name: tl_ac_range_check + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: ac_range_check_tl + index: -1 + } + { + name: tl_dbg + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: dbg + width: 1 + default: "" + external: true + top_signame: dbg_tl + conn_type: false + index: -1 + } + { + name: tl_mbx_jtag__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: dbg + width: 1 + default: "" + top_signame: mbx_jtag_soc_tl_d + index: -1 + } + { + name: tl_lc_ctrl__dmi + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: dbg + width: 1 + default: "" + top_signame: lc_ctrl_dmi_tl + index: -1 + } + { + name: tl_soc_dbg_ctrl__jtag + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: dbg + width: 1 + default: "" + top_signame: soc_dbg_ctrl_jtag_tl + index: -1 + } + { + struct: lc_tx + type: uni + name: lc_dft_en + act: req + package: lc_ctrl_pkg + inst_name: ast + width: 1 + default: "" + top_signame: lc_ctrl_lc_dft_en + index: -1 + external: true + conn_type: true + } + { + struct: lc_tx + type: uni + name: lc_hw_debug_en + act: req + package: lc_ctrl_pkg + inst_name: ast + width: 1 + default: "" + top_signame: lc_ctrl_lc_hw_debug_en + index: -1 + external: true + conn_type: true + } + { + struct: ast_obs_ctrl + type: uni + name: obs_ctrl + act: rcv + package: ast_pkg + inst_name: ast + width: 1 + default: "" + end_idx: -1 + top_type: broadcast + top_signame: ast_obs_ctrl + index: -1 + external: true + conn_type: true + } + ] + external: + [ + { + package: lc_ctrl_pkg + struct: lc_tx + signame: ast_lc_dft_en_o + width: 1 + type: uni + default: "" + direction: out + conn_type: true + index: -1 + netname: lc_ctrl_lc_dft_en + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: ast_lc_hw_debug_en_o + width: 1 + type: uni + default: "" + direction: out + conn_type: true + index: -1 + netname: lc_ctrl_lc_hw_debug_en + } + { + package: ast_pkg + struct: ast_obs_ctrl + signame: obs_ctrl_i + width: 1 + type: uni + default: "" + direction: in + conn_type: true + index: -1 + netname: ast_obs_ctrl + } + { + package: prim_rom_pkg + struct: rom_cfg + signame: rom_ctrl0_cfg_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: rom_ctrl0_cfg + } + { + package: prim_rom_pkg + struct: rom_cfg + signame: rom_ctrl1_cfg_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: rom_ctrl1_cfg + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: i2c_ram_1p_cfg_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: i2c_ram_1p_cfg + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg_rsp + signame: i2c_ram_1p_cfg_rsp_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: i2c_ram_1p_cfg_rsp + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: sram_ctrl_ret_aon_ram_1p_cfg_i + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: sram_ctrl_ret_aon_ram_1p_cfg + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg_rsp + signame: sram_ctrl_ret_aon_ram_1p_cfg_rsp_o + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlRetAonNumRamInst + } + type: uni + default: "'0" + direction: out + conn_type: false + index: -1 + netname: sram_ctrl_ret_aon_ram_1p_cfg_rsp + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: sram_ctrl_main_ram_1p_cfg_i + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: sram_ctrl_main_ram_1p_cfg + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg_rsp + signame: sram_ctrl_main_ram_1p_cfg_rsp_o + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMainNumRamInst + } + type: uni + default: "'0" + direction: out + conn_type: false + index: -1 + netname: sram_ctrl_main_ram_1p_cfg_rsp + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: sram_ctrl_mbox_ram_1p_cfg_i + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: sram_ctrl_mbox_ram_1p_cfg + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg_rsp + signame: sram_ctrl_mbox_ram_1p_cfg_rsp_o + width: + { + name: NumRamInst + desc: Number of internal RAM instances. Must be the same as ceil(MemSizeRam / InstSize) . + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: SramCtrlMboxNumRamInst + } + type: uni + default: "'0" + direction: out + conn_type: false + index: -1 + netname: sram_ctrl_mbox_ram_1p_cfg_rsp + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: otbn_imem_ram_1p_cfg_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: otbn_imem_ram_1p_cfg + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg_rsp + signame: otbn_imem_ram_1p_cfg_rsp_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: otbn_imem_ram_1p_cfg_rsp + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg + signame: otbn_dmem_ram_1p_cfg_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: otbn_dmem_ram_1p_cfg + } + { + package: prim_ram_1p_pkg + struct: ram_1p_cfg_rsp + signame: otbn_dmem_ram_1p_cfg_rsp_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: otbn_dmem_ram_1p_cfg_rsp + } + { + package: "" + struct: logic + signame: no_ibex_msip_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: no_ibex_msip + } + { + package: "" + struct: logic + signame: no_ibex_irq_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: no_ibex_irq + } + { + package: prim_ram_2p_pkg + struct: ram_2p_cfg + signame: spi_device_ram_2p_cfg_sys2spi_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: spi_device_ram_2p_cfg_sys2spi + } + { + package: prim_ram_2p_pkg + struct: ram_2p_cfg_rsp + signame: spi_device_ram_2p_cfg_rsp_sys2spi_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: spi_device_ram_2p_cfg_rsp_sys2spi + } + { + package: prim_ram_2p_pkg + struct: ram_2p_cfg_rsp + signame: spi_device_ram_2p_cfg_rsp_spi2sys_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: spi_device_ram_2p_cfg_rsp_spi2sys + } + { + package: prim_ram_2p_pkg + struct: ram_2p_cfg + signame: spi_device_ram_2p_cfg_spi2sys_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: spi_device_ram_2p_cfg_spi2sys + } + { + package: pwrmgr_pkg + struct: pwr_boot_status + signame: pwrmgr_boot_status_o + width: 1 + type: uni + default: "" + direction: out + conn_type: true + index: -1 + netname: pwrmgr_aon_boot_status + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: clk_main_jitter_en_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: clk_main_jitter_en + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: io_clk_byp_req_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: io_clk_byp_req + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: io_clk_byp_ack_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: io_clk_byp_ack + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: all_clk_byp_req_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: all_clk_byp_req + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: all_clk_byp_ack_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: all_clk_byp_ack + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: hi_speed_sel_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: hi_speed_sel + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: div_step_down_req_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: div_step_down_req + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: calib_rdy_i + width: 1 + type: uni + default: prim_mubi_pkg::MuBi4True + direction: in + conn_type: false + index: -1 + netname: calib_rdy + } + { + package: dma_pkg + struct: sys_req + signame: dma_sys_req_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: dma_sys_req + } + { + package: dma_pkg + struct: sys_rsp + signame: dma_sys_rsp_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: dma_sys_rsp + } + { + package: "" + struct: logic + signame: es_rng_enable_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: es_rng_enable + } + { + package: "" + struct: logic + signame: es_rng_valid_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: es_rng_valid + } + { + package: "" + struct: logic + signame: es_rng_bit_i + width: + { + name: RngBusWidth + desc: + ''' + Defines the bit-width of the noise source data. + Must be between 4 and 256 (inclusive) and divisible by 4. + The divisibility by 4 is a prerequisite for the bucket health test. + ''' + param_type: int + unpacked_dimensions: null + default: 4 + local: false + expose: true + name_top: EntropySrcRngBusWidth + } + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: es_rng_bit + } + { + package: "" + struct: logic + signame: es_rng_fips_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: es_rng_fips + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_tl_req_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: mbx_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_tl_rsp_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: mbx_tl_d2h + } + { + package: "" + struct: logic + signame: mbx0_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx0_doe_intr + } + { + package: "" + struct: logic + signame: mbx0_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx0_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx0_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx0_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx0_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx0_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx1_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx1_doe_intr + } + { + package: "" + struct: logic + signame: mbx1_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx1_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx1_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx1_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx1_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx1_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx2_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx2_doe_intr + } + { + package: "" + struct: logic + signame: mbx2_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx2_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx2_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx2_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx2_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx2_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx3_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx3_doe_intr + } + { + package: "" + struct: logic + signame: mbx3_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx3_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx3_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx3_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx3_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx3_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx4_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx4_doe_intr + } + { + package: "" + struct: logic + signame: mbx4_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx4_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx4_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx4_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx4_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx4_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx5_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx5_doe_intr + } + { + package: "" + struct: logic + signame: mbx5_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx5_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx5_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx5_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx5_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx5_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx6_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx6_doe_intr + } + { + package: "" + struct: logic + signame: mbx6_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx6_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx6_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx6_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx6_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx6_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx_jtag_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_jtag_doe_intr + } + { + package: "" + struct: logic + signame: mbx_jtag_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_jtag_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx_jtag_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_jtag_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx_jtag_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_jtag_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx_pcie0_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie0_doe_intr + } + { + package: "" + struct: logic + signame: mbx_pcie0_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie0_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx_pcie0_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie0_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx_pcie0_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie0_doe_async_msg_support + } + { + package: "" + struct: logic + signame: mbx_pcie1_doe_intr_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie1_doe_intr + } + { + package: "" + struct: logic + signame: mbx_pcie1_doe_intr_en_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie1_doe_intr_en + } + { + package: "" + struct: logic + signame: mbx_pcie1_doe_intr_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie1_doe_intr_support + } + { + package: "" + struct: logic + signame: mbx_pcie1_doe_async_msg_support_o + width: 1 + type: uni + default: 1'b0 + direction: out + conn_type: false + index: -1 + netname: mbx_pcie1_doe_async_msg_support + } + { + package: tlul_pkg + struct: tl_h2d + signame: dbg_tl_req_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: dbg_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: dbg_tl_rsp_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: dbg_tl_d2h + } + { + package: tlul_pkg + struct: tl_h2d + signame: ast_tl_req_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: ast_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: ast_tl_rsp_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: ast_tl_d2h + } + { + package: pwrmgr_pkg + struct: pwr_ast_req + signame: pwrmgr_ast_req_o + width: 1 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: pwrmgr_ast_req + } + { + package: pwrmgr_pkg + struct: pwr_ast_rsp + signame: pwrmgr_ast_rsp_i + width: 1 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: pwrmgr_ast_rsp + } + { + package: otp_macro_pkg + struct: pwr_seq + signame: otp_macro_pwr_seq_o + width: 1 + type: uni + default: "'0" + direction: out + conn_type: false + index: -1 + netname: otp_macro_pwr_seq + } + { + package: otp_macro_pkg + struct: pwr_seq + signame: otp_macro_pwr_seq_h_i + width: 1 + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: otp_macro_pwr_seq_h + } + { + package: "" + struct: "" + signame: otp_ext_voltage_h_io + width: 1 + type: io + default: "'0" + direction: inout + conn_type: false + index: -1 + netname: otp_ext_voltage_h + } + { + package: "" + struct: logic + signame: otp_obs_o + width: 8 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: otp_obs + } + { + package: otp_macro_pkg + struct: otp_cfg + signame: otp_cfg_i + width: 1 + type: uni + default: "'0" + direction: in + conn_type: false + index: -1 + netname: otp_cfg + } + { + package: otp_macro_pkg + struct: otp_cfg_rsp + signame: otp_cfg_rsp_o + width: 1 + type: uni + default: "'0" + direction: out + conn_type: false + index: -1 + netname: otp_cfg_rsp + } + { + package: "" + struct: logic + signame: por_n_i + width: 2 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: por_n + } + { + package: tlul_pkg + struct: tl_h2d + signame: ctn_misc_tl_h2d_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: ctn_misc_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: ctn_misc_tl_d2h_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: ctn_misc_tl_d2h + } + { + package: soc_proxy_pkg + struct: soc_alert_req + signame: soc_fatal_alert_req_i + width: 24 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_fatal_alert_req + } + { + package: soc_proxy_pkg + struct: soc_alert_rsp + signame: soc_fatal_alert_rsp_o + width: 24 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: soc_fatal_alert_rsp + } + { + package: soc_proxy_pkg + struct: soc_alert_req + signame: soc_recov_alert_req_i + width: 4 + type: req_rsp + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_recov_alert_req + } + { + package: soc_proxy_pkg + struct: soc_alert_rsp + signame: soc_recov_alert_rsp_o + width: 4 + type: req_rsp + default: "" + direction: out + conn_type: false + index: -1 + netname: soc_recov_alert_rsp + } + { + package: "" + struct: logic + signame: soc_wkup_async_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_wkup_async + } + { + package: "" + struct: logic + signame: soc_rst_req_async_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_rst_req_async + } + { + package: "" + struct: logic + signame: soc_intr_async_i + width: 32 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_intr_async + } + { + package: "" + struct: logic + signame: soc_lsio_trigger_i + width: 8 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_lsio_trigger + } + { + package: "" + struct: logic + signame: soc_gpi_async_o + width: 16 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: soc_gpi_async + } + { + package: "" + struct: logic + signame: soc_gpo_async_i + width: 16 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: soc_gpo_async + } + { + package: "" + struct: logic + signame: integrator_id_i + width: 4 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: integrator_id + } + { + package: "" + struct: logic + signame: sck_monitor_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: sck_monitor + } + { + package: soc_dbg_ctrl_pkg + struct: soc_dbg_policy + signame: soc_dbg_policy_bus_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: soc_dbg_policy_bus + } + { + package: "" + struct: logic + signame: debug_halt_cpu_boot_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: debug_halt_cpu_boot + } + { + package: top_racl_pkg + struct: racl_policy_vec + signame: racl_policies_o + width: 1 + type: uni + default: "" + direction: out + conn_type: true + index: -1 + netname: racl_ctrl_racl_policies + } + { + package: top_racl_pkg + struct: racl_error_log + signame: racl_error_i + width: + { + name: NumExternalSubscribingIps + desc: Number of external subscribing RACL IPs + param_type: int + unpacked_dimensions: null + default: 1 + local: false + expose: true + name_top: RaclCtrlNumExternalSubscribingIps + } + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: racl_error + } + { + package: prim_mubi_pkg + struct: mubi8 + signame: ac_range_check_overwrite_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: ac_range_check_overwrite + } + { + package: tlul_pkg + struct: tl_h2d + signame: ctn_tl_h2d_o + width: 1 + type: uni + default: "" + direction: out + conn_type: false + index: -1 + netname: ctn_tl_h2d + } + { + package: tlul_pkg + struct: tl_d2h + signame: ctn_tl_d2h_i + width: 1 + type: uni + default: "" + direction: in + conn_type: false + index: -1 + netname: ctn_tl_d2h + } + ] + definitions: + [ + { + package: ast_pkg + struct: ast_obs_ctrl + signame: ast_obs_ctrl + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: ast_pkg::AST_OBS_CTRL_DEFAULT + } + { + package: alert_handler_pkg + struct: alert_crashdump + signame: alert_handler_crashdump + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: alert_handler_pkg::ALERT_CRASHDUMP_DEFAULT + } + { + package: prim_esc_pkg + struct: esc_rx + signame: alert_handler_esc_rx + width: 4 + type: uni + end_idx: 3 + act: rcv + suffix: "" + default: prim_esc_pkg::ESC_RX_DEFAULT + } + { + package: prim_esc_pkg + struct: esc_tx + signame: alert_handler_esc_tx + width: 4 + type: uni + end_idx: 3 + act: req + suffix: "" + default: prim_esc_pkg::ESC_TX_DEFAULT + } + { + package: csrng_pkg + struct: csrng_req + signame: csrng_csrng_cmd_req + width: 2 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: csrng_pkg::CSRNG_REQ_DEFAULT + } + { + package: csrng_pkg + struct: csrng_rsp + signame: csrng_csrng_cmd_rsp + width: 2 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: entropy_src_pkg + struct: entropy_src_hw_if_req + signame: csrng_entropy_src_hw_if_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: entropy_src_pkg + struct: entropy_src_hw_if_rsp + signame: csrng_entropy_src_hw_if_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: entropy_src_pkg::ENTROPY_SRC_HW_IF_RSP_DEFAULT + } + { + package: entropy_src_pkg + struct: cs_aes_halt_req + signame: csrng_cs_aes_halt_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: entropy_src_pkg::CS_AES_HALT_REQ_DEFAULT + } + { + package: entropy_src_pkg + struct: cs_aes_halt_rsp + signame: csrng_cs_aes_halt_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: otp_ctrl_pkg + struct: sram_otp_key_req + signame: otp_ctrl_sram_otp_key_req + width: 4 + type: req_rsp + end_idx: 3 + act: rsp + suffix: req + default: "'0" + } + { + package: otp_ctrl_pkg + struct: sram_otp_key_rsp + signame: otp_ctrl_sram_otp_key_rsp + width: 4 + type: req_rsp + end_idx: 3 + act: rsp + suffix: rsp + default: "" + } + { + package: pwrmgr_pkg + struct: pwr_rst_req + signame: pwrmgr_aon_pwr_rst_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: pwrmgr_pkg + struct: pwr_rst_rsp + signame: pwrmgr_aon_pwr_rst_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: pwrmgr_pkg::PWR_RST_RSP_DEFAULT + } + { + package: pwrmgr_pkg + struct: pwr_clk_req + signame: pwrmgr_aon_pwr_clk_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: pwrmgr_pkg + struct: pwr_clk_rsp + signame: pwrmgr_aon_pwr_clk_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: pwrmgr_pkg::PWR_CLK_RSP_DEFAULT + } + { + package: pwrmgr_pkg + struct: pwr_otp_req + signame: pwrmgr_aon_pwr_otp_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: pwrmgr_pkg + struct: pwr_otp_rsp + signame: pwrmgr_aon_pwr_otp_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: pwrmgr_pkg::PWR_OTP_RSP_DEFAULT + } + { + package: lc_ctrl_pkg + struct: pwr_lc_req + signame: pwrmgr_aon_pwr_lc_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: lc_ctrl_pkg + struct: pwr_lc_rsp + signame: pwrmgr_aon_pwr_lc_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: lc_ctrl_pkg::PWR_LC_RSP_DEFAULT + } + { + package: "" + struct: logic + signame: pwrmgr_aon_strap + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: pwrmgr_aon_low_power + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: rom_ctrl_pkg + struct: pwrmgr_data + signame: pwrmgr_aon_rom_ctrl + width: 3 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: rom_ctrl_pkg::PWRMGR_DATA_DEFAULT + } + { + package: pwrmgr_pkg + struct: pwr_boot_status + signame: pwrmgr_aon_boot_status + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: pwrmgr_pkg::PWR_BOOT_STATUS_DEFAULT + } + { + package: rom_ctrl_pkg + struct: keymgr_data + signame: keymgr_dpe_rom_digest + width: 2 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: rom_ctrl_pkg::KEYMGR_DATA_DEFAULT + } + { + package: dma_pkg + struct: lsio_trigger + signame: dma_lsio_trigger + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: dma_pkg::LSIO_TRIGGER_DEFAULT + } + { + package: "" + struct: logic + signame: i2c0_lsio_trigger + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: spi_host0_lsio_trigger + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: uart0_lsio_trigger + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_flash_rma_req + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: otbn_lc_rma_ack + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: edn_pkg + struct: edn_req + signame: edn0_edn_req + width: 8 + type: req_rsp + end_idx: 6 + act: rsp + suffix: req + default: "'0" + } + { + package: edn_pkg + struct: edn_rsp + signame: edn0_edn_rsp + width: 8 + type: req_rsp + end_idx: 6 + act: rsp + suffix: rsp + default: "" + } + { + package: edn_pkg + struct: edn_req + signame: edn1_edn_req + width: 8 + type: req_rsp + end_idx: 1 + act: rsp + suffix: req + default: "'0" + } + { + package: edn_pkg + struct: edn_rsp + signame: edn1_edn_rsp + width: 8 + type: req_rsp + end_idx: 1 + act: rsp + suffix: rsp + default: "" + } + { + package: otp_ctrl_pkg + struct: otbn_otp_key_req + signame: otp_ctrl_otbn_otp_key_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: "'0" + } + { + package: otp_ctrl_pkg + struct: otbn_otp_key_rsp + signame: otp_ctrl_otbn_otp_key_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: otp_ctrl_pkg + struct: otp_keymgr_key + signame: otp_ctrl_otp_keymgr_key + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: keymgr_pkg + struct: hw_key_req + signame: keymgr_dpe_aes_key + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: keymgr_pkg::HW_KEY_REQ_DEFAULT + } + { + package: keymgr_pkg + struct: hw_key_req + signame: keymgr_dpe_kmac_key + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: keymgr_pkg::HW_KEY_REQ_DEFAULT + } + { + package: keymgr_pkg + struct: otbn_key_req + signame: keymgr_dpe_otbn_key + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: keymgr_pkg::OTBN_KEY_REQ_DEFAULT + } + { + package: kmac_pkg + struct: app_req + signame: kmac_app_req + width: + { + name: NumAppIntf + desc: Number of application interfaces + param_type: int + unpacked_dimensions: null + default: 3 + local: false + expose: true + name_top: KmacNumAppIntf + } + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: kmac_pkg::APP_REQ_DEFAULT + } + { + package: kmac_pkg + struct: app_rsp + signame: kmac_app_rsp + width: + { + name: NumAppIntf + desc: Number of application interfaces + param_type: int + unpacked_dimensions: null + default: 3 + local: false + expose: true + name_top: KmacNumAppIntf + } + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: "" + struct: logic + signame: kmac_en_masking + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: clkmgr_aon_idle + width: 4 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: prim_mubi_pkg::MUBI4_DEFAULT + } + { + package: otp_ctrl_pkg + struct: otp_lc_data + signame: otp_ctrl_otp_lc_data + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: otp_ctrl_pkg + struct: lc_otp_program_req + signame: lc_ctrl_lc_otp_program_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: otp_ctrl_pkg + struct: lc_otp_program_rsp + signame: lc_ctrl_lc_otp_program_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: "'0" + } + { + package: otp_macro_pkg + struct: otp_test_req + signame: lc_ctrl_lc_otp_vendor_test_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: otp_macro_pkg + struct: otp_test_rsp + signame: lc_ctrl_lc_otp_vendor_test_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: "'0" + } + { + package: lc_ctrl_pkg + struct: lc_keymgr_div + signame: lc_ctrl_lc_keymgr_div + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: "'0" + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_raw_test_rma + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_dft_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_hw_debug_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_keymgr_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_escalate_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_check_byp_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_clk_byp_req + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_clk_byp_ack + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_creator_seed_sw_rw_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_owner_seed_sw_rw_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: lc_ctrl_pkg + struct: lc_tx + signame: lc_ctrl_lc_seed_hw_rd_en + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: lc_ctrl_pkg::Off + } + { + package: otp_ctrl_macro_pkg + struct: otp_ctrl_macro_req + signame: otp_ctrl_otp_macro_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: otp_ctrl_macro_pkg + struct: otp_ctrl_macro_rsp + signame: otp_ctrl_otp_macro_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: "'0" + } + { + package: spi_device_pkg + struct: passthrough_req + signame: spi_device_passthrough_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: spi_device_pkg + struct: passthrough_rsp + signame: spi_device_passthrough_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: spi_device_pkg::PASSTHROUGH_RSP_DEFAULT + } + { + package: prim_mubi_pkg + struct: mubi4 + signame: rstmgr_aon_sw_rst_req + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: prim_mubi_pkg::MUBI4_DEFAULT + } + { + package: tlul_pkg + struct: tl_h2d + signame: soc_proxy_dma_tl_h2d + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: soc_proxy_dma_tl_d2h + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: tlul_pkg::TL_D2H_DEFAULT + } + { + package: tlul_pkg + struct: tl_h2d + signame: soc_proxy_ctn_tl_h2d + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: soc_proxy_ctn_tl_d2h + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: tlul_pkg::TL_D2H_DEFAULT + } + { + package: "" + struct: logic + signame: pwrmgr_aon_wakeups + width: 4 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: "'0" + } + { + package: "" + struct: logic + signame: pwrmgr_aon_rstreqs + width: 2 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: "'0" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_peri_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_peri_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: tlul_pkg::TL_D2H_DEFAULT + } + { + package: tlul_pkg + struct: tl_h2d + signame: soc_proxy_ctn_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: soc_proxy_ctn_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: hmac_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: hmac_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: kmac_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: kmac_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: aes_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: aes_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: otbn_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: otbn_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: keymgr_dpe_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: keymgr_dpe_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_main_ram_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_main_ram_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_mbox_ram_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_mbox_ram_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_dma__host_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_dma__host_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx0__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx0__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx1__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx1__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx2__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx2__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx3__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx3__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx4__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx4__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx5__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx5__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx6__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx6__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx_jtag__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx_jtag__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx_pcie0__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx_pcie0__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: main_tl_mbx_pcie1__sram_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: main_tl_mbx_pcie1__sram_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: uart0_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: uart0_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: i2c0_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: i2c0_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: gpio_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: gpio_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: spi_host0_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: spi_host0_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: spi_device_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: spi_device_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: pwrmgr_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: pwrmgr_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: rstmgr_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: rstmgr_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: clkmgr_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: clkmgr_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: pinmux_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: pinmux_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: otp_ctrl_core_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: otp_ctrl_core_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: otp_macro_prim_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: otp_macro_prim_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: lc_ctrl_regs_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: lc_ctrl_regs_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: alert_handler_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: alert_handler_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_ret_aon_regs_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_ret_aon_regs_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: sram_ctrl_ret_aon_ram_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: sram_ctrl_ret_aon_ram_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: aon_timer_aon_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: aon_timer_aon_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: soc_dbg_ctrl_core_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: soc_dbg_ctrl_core_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx0_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx0_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx1_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx1_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx2_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx2_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx3_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx3_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx4_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx4_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx5_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx5_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx6_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx6_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_pcie0_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_pcie0_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_pcie1_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_pcie1_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: racl_ctrl_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: racl_ctrl_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: ac_range_check_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: ac_range_check_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: mbx_jtag_soc_tl_d_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: mbx_jtag_soc_tl_d_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: lc_ctrl_dmi_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: lc_ctrl_dmi_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: tlul_pkg + struct: tl_h2d + signame: soc_dbg_ctrl_jtag_tl_req + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: req + default: tlul_pkg::TL_H2D_DEFAULT + } + { + package: tlul_pkg + struct: tl_d2h + signame: soc_dbg_ctrl_jtag_tl_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: rsp + suffix: rsp + default: "" + } + { + package: top_racl_pkg + struct: racl_policy_vec + signame: racl_ctrl_racl_policies + width: 1 + type: uni + end_idx: -1 + act: req + suffix: "" + default: top_racl_pkg::RACL_POLICY_VEC_DEFAULT + } + { + package: top_racl_pkg + struct: racl_error_log + signame: racl_ctrl_racl_error + width: + { + name: NumSubscribingIps + desc: Number of subscribing RACL IPs + param_type: int + unpacked_dimensions: null + default: 11 + local: true + expose: true + name_top: RaclCtrlNumSubscribingIps + } + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: top_racl_pkg::RACL_ERROR_LOG_DEFAULT + } + { + package: clkmgr_pkg + struct: clkmgr_out + signame: clkmgr_aon_clocks + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: clkmgr_pkg + struct: clkmgr_cg_en + signame: clkmgr_aon_cg_en + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: rstmgr_pkg + struct: rstmgr_out + signame: rstmgr_aon_resets + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: rstmgr_pkg + struct: rstmgr_rst_en + signame: rstmgr_aon_rst_en + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: otp_ctrl_part_pkg + struct: otp_broadcast + signame: otp_ctrl_otp_broadcast + width: 1 + type: uni + end_idx: -1 + default: "'0" + } + { + package: prim_mubi_pkg + struct: mubi8 + signame: csrng_otp_en_csrng_sw_app_read + width: 1 + type: uni + end_idx: -1 + default: prim_mubi_pkg::MuBi8True + } + { + package: lc_ctrl_state_pkg + struct: soc_dbg_state + signame: soc_dbg_ctrl_soc_dbg_state + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: otp_ctrl_pkg + struct: otp_device_id + signame: lc_ctrl_otp_device_id + width: 1 + type: uni + end_idx: -1 + default: "'0" + } + { + package: otp_ctrl_pkg + struct: otp_manuf_state + signame: lc_ctrl_otp_manuf_state + width: 1 + type: uni + end_idx: -1 + default: "'0" + } + { + package: otp_ctrl_pkg + struct: otp_device_id + signame: keymgr_dpe_otp_device_id + width: 1 + type: uni + end_idx: -1 + default: "" + } + { + package: prim_mubi_pkg + struct: mubi8 + signame: sram_ctrl_main_otp_en_sram_ifetch + width: 1 + type: uni + end_idx: -1 + default: prim_mubi_pkg::MuBi8False + } + ] + } +} diff --git a/hw/top_darjeeling_no_ibex/data/chip_cfg.hjson b/hw/top_darjeeling_no_ibex/data/chip_cfg.hjson new file mode 100644 index 00000000000..464d369a364 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/chip_cfg.hjson @@ -0,0 +1,20 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Override existing project defaults to supply chip-specific values. + overrides: [ + // Fusesoc core file directory hierarchy. + { + name: fusesoc_cores_root_dirs + value: ["--cores-root {proj_root}/util", + "--cores-root {proj_root}/hw/dv", + "--cores-root {proj_root}/hw/formal", + "--cores-root {proj_root}/hw/ip", + "--cores-root {proj_root}/hw/lint", + "--cores-root {proj_root}/hw/vendor", + "--cores-root {proj_root}/hw/top_darjeeling"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/chip_conn_testplan.hjson b/hw/top_darjeeling_no_ibex/data/chip_conn_testplan.hjson new file mode 100644 index 00000000000..e54af857456 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/chip_conn_testplan.hjson @@ -0,0 +1,1219 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: conn + testpoints: [ + + ///////////////////////// + // aon_timer_rst.csv // + ///////////////////////// + { + name: aon_timer_rst + desc: '''Verify rstmgr's resets_o is connected to aon_timer's reset port.''' + stage: V2 + tests: ["aon_timer_rst"] + tags: ["conn"] + } + { + name: aon_timer_rst_aon + desc: '''Verify rstmgr's resets_o is connected to aon_timer's aon-reset port.''' + stage: V2 + tests: ["aon_timer_rst_aon"] + tags: ["conn"] + } + + ///////////////////////// + // ast_clkmgr.csv // + ///////////////////////// + { + name: ast_clockmgr_clocks + desc: '''Verify the clock connectivity between AST and clock manager. + ''' + stage: V2 + tests: ["ast_clk_sys_out", + "ast_clk_aon_out", + "ast_clk_io_out", + "ast_all_byp_ack_out", + "ast_io_byp_ack_out", + "ast_clk_adc_in", + "ast_clk_alert_in", + "ast_clk_es_in", + "ast_clk_rng_in", + "ast_clk_tlul_in", + "ast_clk_sns_in", + "ast_clk_jen_in", + "ast_all_byp_ack_in", + "ast_io_byp_ack_in", + "ast_hispeed_sel_in"] + tags: ["conn"] + } + + ///////////////////////// + // pwrmgr_ast.csv // + ///////////////////////// + { + name: ast_pwrmgr_pok + desc: '''Verify the connectivity of power-related signals between AST and power manager. + ''' + stage: V2 + tests: ["ast_clk_sys_val_out", + "ast_clk_aon_val_out", + "ast_clk_io_val_out", + "ast_main_pok_out", + "ast_clk_sys_en_in", + "ast_clk_io_en_in"] + tags: ["conn"] + } + ///////////////////////// + // rstmgr_ast.csv // + ///////////////////////// + { + name: ast_rstmgr_resets + desc: '''Verify the reset connectivity between AST and reset manager. + ''' + stage: V2 + tests: ["ast_rst_adc_in", + "ast_rst_alert_in", + "ast_rst_es_in", + "ast_rst_rng_in", + "ast_rst_tlul_in", + "ast_rst_sns_in"] + tags: ["conn"] + } + + ///////////////////////// + // ast_infra.csv // + ///////////////////////// + { + name: ast_pad_shorts + desc: '''Verify pads that are directly shorted to pads + ''' + stage: V2 + tests: ["ast_pad0", + "ast_pad1"] + tags: ["conn"] + } + { + name: ast_pinmux + desc: '''Verify AST -> pinmux connectivity + ''' + stage: V2 + tests: ["ast_pinmux"] + tags: ["conn"] + } + { + name: ast_pad_inputs + desc: '''Verify pad inputs that are connected to AST + ''' + stage: V2 + tests: ["pad_ast"] + tags: ["conn"] + } + { + name: ast_other_clocks + desc: '''Verify clock connectivity between AST and other blocks in the system, + excluding clkmgr connections. + ''' + stage: V2 + tests: ["ast_clk_ext_in", "ast_clk_spi_sns_in"] + tags: ["conn"] + } + { + name: ast_other_resets + desc: '''Verify reset connectivity between AST and other blocks in the system, + excluding rstmgr connections. + ''' + stage: V2 + tests: ["ast_rst_por_in"] + tags: ["conn"] + } + { + name: ast_other_pok + desc: '''Verify the connectivity of power-related signals between AST and other blocks in + the system, excluding power manager. + ''' + stage: V2 + tests: ["ast_otp_pwr_seq_in", + "ast_main_pd_in", + "ast_main_iso_en_in", + "ast_otp_pwr_seq_out",] + tags: ["conn"] + } + + ///////////////////////// + // ast_mem_cfg.csv // + ///////////////////////// + { + name: ast_dft_ram_2p_cfg + desc: '''Verify ast model's dual port configuration bits are connected to the dual port RAMs + in the following blocks: + - spi_device + ''' + stage: V2 + tests: ["ast_dft_spi_device_ram_2p_cfg"] + tags: ["conn"] + } + { + name: ast_dft_ram_1p_cfg + desc: '''Verify ast model's single port configuration bits are connected to the single port + RAMs in the following blocks: + - otbn_imem + - otbn_dmem + - rv_core_ibex_tag0 + - rv_core_ibex_tag1 + - rv_core_ibex_data0 + - rv_core_ibex_data1 + - sram_main + - sram_retention + - rom + ''' + stage: V2 + tests: ["ast_dft_otbn_imem_ram_1p_cfg", + "ast_dft_otbn_dmem_ram_1p_cfg", + "ast_dft_rv_core_ibex_tag0_ram_1p_cfg", + "ast_dft_rv_core_ibex_tag1_ram_1p_cfg", + "ast_dft_rv_core_ibex_data0_ram_1p_cfg", + "ast_dft_rv_core_ibex_data1_ram_1p_cfg", + "ast_dft_sram_main_ram_1p_cfg", + "ast_dft_sram_ret_ram_1p_cfg", + "ast_dft_rom_cfg"] + tags: ["conn"] + } + + ///////////////////////// + // ast_scanmode.csv // + ///////////////////////// + { + name: scanmode_connections + desc: '''Verify the connectivity of scanmode to the following IPs: + - clkmgr + - flash_ctrl + - lc_ctrl + - otp_ctrl + - padring + - pinmux + - rstmgr + - rv_core_ibex + - rv_dm + - spi_device + - xbar_main + - xbar_peri + ''' + stage: V2 + tests: ["ast_scanmode_padring", "ast_scanmode_clkmgr", "ast_scanmode_flash_ctrl", + "ast_scanmode_lc_ctrl", "ast_scanmode_otp_ctrl", "ast_scanmode_pinmux", + "ast_scanmode_rstmgr", "ast_scanmode_rv_core_ibex", "ast_scanmode_rv_dm", + "ast_scanmode_spi_device", "ast_scanmode_xbar_main", "ast_scanmode_xbar_peri"] + tags: ["conn"] + } + + ////////////////////////////// + // otp_lc_vendor_test.csv // + ////////////////////////////// + { + name: vendor_test_connections + desc: '''Verify the connectivity of vendor_test IOs between otp_ctrl and lc_ctrl.''' + stage: V2 + tests: ["lc_otp_vendor_test_ctrl", "lc_otp_vendor_test_status"] + tags: ["conn"] + } + + + ////////////////////////// + // clkmgr_cg_en.csv // + ////////////////////////// + { + name: cg_en_io_peri + desc: '''Verify clkmgr's cg_en_o.io_peri is connected to alert_handler's lpg_cg_en[7].''' + stage: V2 + tests: ["clkmgr_io_peri_alert_7_cg_en"] + tags: ["conn"] + } + { + name: cg_en_io_div2_peri + desc: '''Verify clkmgr's cg_en_o.io_div2_peri is connected to alert_handler's lpg_cg_en[8].''' + stage: V2 + tests: ["clkmgr_io_div2_peri_alert_8_cg_en"] + tags: ["conn"] + } + { + name: cg_en_io_div4_infra + desc: '''Verify clkmgr's cg_en_o.io_div4_infra is connected to: + - alert_handler's lpg_cg_en_i[12] + - alert_handler's lpg_cg_en_i[16] + ''' + stage: V2 + tests: ["clkmgr_io_div2_infra_alert_12_cg_en", + "clkmgr_io_div4_infra_alert_16_cg_en"] + tags: ["conn"] + } + { + name: cg_en_io_div4_peri + desc: '''Verify clkmgr's cg_en_o.io_div4_peri is connected to the following: + - alert_handler's lpg_cg_en_i[4:0] + - alert_handler's lpg_cg_en_i[13] + ''' + stage: V2 + tests: ["clkmgr_io_div4_peri_alert_0_cg_en", + "clkmgr_io_div4_peri_alert_1_cg_en", + "clkmgr_io_div4_peri_alert_2_cg_en", + "clkmgr_io_div4_peri_alert_3_cg_en", + "clkmgr_io_div4_peri_alert_4_cg_en", + "clkmgr_io_div4_peri_alert_13_cg_en"] + tags: ["conn"] + } + { + name: cg_en_io_div4_powerup + desc: '''Verify clkmgr's cg_en_o.io_div4_powerup is connected to the following: + - alert_handler's lpg_cg_en_i[11:10] + - alert_handler's lpg_cg_en_i[14] + ''' + stage: V2 + tests: ["clkmgr_io_div4_powerup_alert_10_cg_en", + "clkmgr_io_div4_powerup_alert_11_cg_en", + "clkmgr_io_div4_powerup_alert_14_cg_en"] + tags: ["conn"] + } + { + name: cg_en_io_div4_secure + desc: '''Verify clkmgr's cg_en_o.io_div4_secure is connected to the following: + - alert_handler's lpg_cg_en_i[6] + - alert_handler's lpg_cg_en_i[17] + ''' + stage: V2 + tests: ["clkmgr_io_div4_secure_alert_6_cg_en", + "clkmgr_io_div4_secure_alert_17_cg_en"] + tags: ["conn"] + } + { + name: cg_en_io_div4_timers + desc: '''Verify clkmgr's cg_en_o.io_div4_timers is connected to the following: + - alert_handler's lpg_cg_en_i[5] + - alert_handler's lpg_cg_en_i[15] + ''' + stage: V2 + tests: ["clkmgr_io_div4_timers_alert_5_cg_en", + "clkmgr_io_div4_timers_alert_15_cg_en"] + tags: ["conn"] + } + { + name: cg_en_main_aes + desc: '''Verify clkmgr's cg_en_o.main_aes is connected to alert_handler's lpg_cg_en[21].''' + stage: V2 + tests: ["clkmgr_main_aes_alert_21_cg_en"] + tags: ["conn"] + } + { + name: cg_en_main_infra + desc: '''Verify clkmgr's cg_en_o.main_infra is connected to alert_handler's lpg_cg_en[19:18].''' + stage: V2 + tests: ["clkmgr_main_infra_alert_18_cg_en", + "clkmgr_main_infra_alert_19_cg_en"] + tags: ["conn"] + } + { + name: cg_en_main_secure + desc: '''Verify clkmgr's cg_en_o.main_secure is connected to alert_handler's lpg_cg_en[20].''' + stage: V2 + tests: ["clkmgr_main_secure_alert_20_cg_en"] + tags: ["conn"] + } + + ///////////////////////// + // clkmgr_idle.csv // + ///////////////////////// + { + name: clkmgr_idle + desc: '''Verify clkmgr's `idle_i` bits are connected to the following ports: + - index 0 to aes's `idle_o` + - index 1 to hmac's `idle_o` + - index 2 to kmac's `idle_o` + - index 3 to otbn's `idle_o` + ''' + stage: V2 + tests: ["clkmgr_idle0", "clkmgr_idle1", "clkmgr_idle2", "clkmgr_idle3"] + tags: ["conn"] + } + + ///////////////////////// + // clkmgr_infra.csv // + ///////////////////////// + { + name: clkmgr_clk_io_div4_infra + desc: '''Verify clkmgr's `clk_io_div4_infra` is connected to the following block's clock + input: + - flash_ctrl clk_otp_i + - sram_ctrl main clk_otp_i + - sram_ctrl retention clk_i + - sram_ctrl retention clk_otp_i + - xbar_main clk_fixed_i + - xbar_peri clk_peri_i + ''' + stage: V2 + tests: ["clkmgr_infra_clk_flash_ctrl_otp_clk", + "clkmgr_infra_clk_sram_ctrl_main_otp_clk", + "clkmgr_infra_clk_sram_ctrl_ret_clk", + "clkmgr_infra_clk_sram_ctrl_ret_otp_clk", + "clkmgr_infra_clk_xbar_main_fixed_clk", + "clkmgr_infra_clk_xbar_peri_peri_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_main_infra + desc: '''Verify clkmgr's `clk_main_infra` is connected to the following blocks' clock input: + - flash_ctrl clk_i + - rv_dm clk_i + - rom_ctrl clk_i + - rv_core_ibex clk_i + - rv_core_ibex clk_edn_i + - sram_ctrl main clk_i + - xbar_main clk_main_i + ''' + stage: V2 + tests: ["clkmgr_infra_clk_flash_ctrl_clk", + "clkmgr_infra_clk_rv_dm_clk", + "clkmgr_infra_clk_rom_clk", + "clkmgr_infra_clk_rv_core_ibex_clk", + "clkmgr_infra_clk_rv_core_ibex_edn_clk", + "clkmgr_infra_clk_sram_ctrl_main_clk", + "clkmgr_infra_clk_xbar_main_main_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_io_infra + desc: '''Verify clkmgr's `clk_io_infra` is connected to the following block's clock input: + - xbar_main's clk_spi_host0_i + ''' + stage: V2 + tests: ["clkmgr_infra_clk_xbar_main_spi_host0_clk"] + tags: ["conn"] + } + + ///////////////////////// + // clkmgr_peri.csv // + ///////////////////////// + { + name: clkmgr_clk_io_div4_peri + desc: '''Verify clkmgr's `clk_io_div4_peri` is connected to the following blocks' clock + input: + - adc_ctrl clk_i + - gpio clk_i + - spi_device clk_i + - i2c0 clk_i + - uart0 clk_i + ''' + stage: V2 + tests: ["clkmgr_peri_clk_adc_ctrl_aon_clk", + "clkmgr_peri_clk_gpio_clk", + "clkmgr_peri_clk_spi_device_clk", + "clkmgr_peri_clk_i2c0_clk", + "clkmgr_peri_clk_uart0_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_io_div2_peri + desc: '''Verify clkmgr's `clk_io_div2_peri` is connected to the following blocks' clock + input: + - spi_device's scan_clk_i + ''' + stage: V2 + tests: ["clkmgr_peri_clk_spi_device_scan_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_io_peri + desc: '''Verify clkmgr's `clk_io_peri` is connected to the following block's clock input: + - spi_host0's clk_i + ''' + stage: V2 + tests: ["clkmgr_peri_clk_spi_host0_clk"] + tags: ["conn"] + } + + ///////////////////////// + // clkmgr powerup // + ///////////////////////// + { + name: clkmgr_clk_io_div4_powerup + desc: '''Verify clkmgr's `clk_io_div4_powerup` is connected to the following blocks' clock + input: + - clkmgr clk_i + - pinmux clk_i + - pwrmgr clk_i + - rstmgr clk_i + - rstmgr clk_io_div4_i + ''' + stage: V2 + tests: ["clkmgr_powerup_clk_clkmgr_clk", + "clkmgr_powerup_clk_pinmux_clk", + "clkmgr_powerup_clk_pwrmgr_clk", + "clkmgr_powerup_clk_pwrmgr_lc_clk", + "clkmgr_powerup_clk_rstmgr_por_clk", + "clkmgr_powerup_clk_rstmgr_io4_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_aon_powerup + desc: '''Verify clkmgr's `clk_aon_powerup` is connected to the following blocks' clock input: + - pinmux's clk_aon_i + - pwrmgr clk_slow_i + - rstmgr clk_aon_i + ''' + stage: V2 + tests: ["clkmgr_powerup_clk_pinmux_aon_clk", + "clkmgr_powerup_clk_pwrmgr_slow_clk", + "clkmgr_powerup_clk_rstmgr_aon_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_main_powerup + desc: '''Verify clkmgr's `clk_main_powerup` is connected to the following block's clock + input: + - rstmgr's clk_main_i + ''' + stage: V2 + tests: ["clkmgr_powerup_clk_rstmgr_main_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_io_powerup + desc: '''Verify clkmgr's `clk_io_powerup` is connected to rstmgr's io clock.''' + stage: V2 + tests: ["clkmgr_powerup_clk_rstmgr_io_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_io_div2_powerup + desc: '''Verify clkmgr's `clk_io_div2_powerup` is connected to rstmgr's io_div2 clock.''' + stage: V2 + tests: ["clkmgr_powerup_clk_rstmgr_io2_clk"] + tags: ["conn"] + } + + ///////////////////////// + // clkmgr_secure.csv // + ///////////////////////// + { + name: clkmgr_clk_io_div4_secure + desc: '''Verify clkmgr's `clk_io_div4_secure` is connected to the following blocks' clock + input: + - alert_handler clk_i + - lc_ctrl clk_i + - otbn clk_otp_i + - otp_ctrl clk_i + - pwrmgr clk_lc_i + - rv_core_ibex clk_esc_i + - rv_core_ibex clk_otp_i + - sensor_ctrl clk_i + ''' + stage: V2 + tests: ["clkmgr_secure_clk_alert_handler_clk", + "clkmgr_secure_clk_lc_ctrl_clk", + "clkmgr_secure_clk_otbn_otp_clk", + "clkmgr_secure_clk_otp_ctrl_clk", + "clkmgr_secure_clk_rv_core_ibex_clk", + "clkmgr_secure_clk_rv_core_ibex_otp_clk", + "clkmgr_secure_clk_sensor_ctrl_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_main_secure + desc: '''Verify clkmgr's `clk_main_secure` is connected to the following blocks' clock input: + - alert_handler's clk_edn_i + - csrgn clk_i + - edn0 clk_i + - edn1 clk_i + - keymgr clk_i + - keymgr clk_edn_i + - lc_ctrl clk_kmac_i + - otbn clk_edn_i + - otp_ctrl clk_edn_i + - rv_plic clk_i + ''' + stage: V2 + tests: ["clkmgr_secure_clk_alert_handler_edn_clk", + "clkmgr_secure_clk_csrng_clk", + "clkmgr_secure_clk_edn0_clk", + "clkmgr_secure_clk_edn1_clk", + "clkmgr_secure_clk_keymgr_clk", + "clkmgr_secure_clk_keymgr_edn_clk", + "clkmgr_secure_clk_lc_ctrl_kmac_clk", + "clkmgr_secure_clk_otbn_edn_clk", + "clkmgr_secure_clk_otp_ctrl_edn_clk", + "clkmgr_secure_clk_rv_plic_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_aon_secure + desc: '''Verify clkmgr's `clk_aon_secure` is connected to the following blocks' clock input: + - sensor_ctrl clk_aon_i + ''' + stage: V2 + tests: ["clkmgr_secure_clk_sensor_ctrl_aon_clk"] + tags: ["conn"] + } + + ///////////////////////// + // clkmgr_timers.csv // + ///////////////////////// + { + name: clkmgr_clk_io_div4_timers + desc: '''Verify clkmgr's `clk_io_div4_timers` is connected to the following blocks' clock + input: + - aon_timer clk_i + - rv_timer clk_i + ''' + stage: V2 + tests: ["clkmgr_timers_clk_aon_timer_clk", "clkmgr_timers_clk_rv_timer_clk"] + tags: ["conn"] + } + { + name: clkmgr_clk_aon_timers + desc: '''Verify clkmgr's `clk_aon_timers` is connected to aon_timer's aon clock.''' + stage: V2 + tests: ["clkmgr_timers_clk_aon_timer_aon_clk"] + tags: ["conn"] + } + + ////////////////////// + // clkmgr_trans.csv // + ////////////////////// + { + name: clk_main_aes + desc: '''Verify clkmgr's clk_main_aes is connected to the following block's clocks: + - aes clk_i + - aes clk_edn_i + ''' + stage: V2 + tests: ["clkmgr_trans_aes", "clkmgr_trans_aes_edn"] + tags: ["conn"] + } + { + name: clk_main_hmac + desc: '''Verify clkmgr's clk_main_hmac is connected to hmac's clk_i.''' + stage: V2 + tests: ["clkmgr_trans_hmac"] + tags: ["conn"] + } + { + name: clk_main_kmac + desc: '''Verify clkmgr's clk_main_kmac is connected to kmac's clk_i and clk_edn_i.''' + stage: V2 + tests: ["clkmgr_trans_kmac", "clkmgr_trans_kmac_edn"] + tags: ["conn"] + } + { + name: clk_main_otbn + desc: '''Verify clkmgr's clk_main_otbn is connected to otbn's clk_i.''' + stage: V2 + tests: ["clkmgr_trans_otbn"] + tags: ["conn"] + } + + ///////////////////////// + // ast_flash.csv // + ///////////////////////// + { + name: ast_flash_ctrl + desc: '''Verify ast's flash signals are connected to the flash controller.''' + stage: V2 + tests: ["ast_flash_obs_ctrl", + "ast_flash_pwr_dwn_out", + "ast_flash_pwr_rdy_out", + "ast_flash_bist_en_out"] + tags: ["conn"] + } + ///////////////////////////// + // ast_csrng_cfg.csv // + ///////////////////////////// + { + name: chip_sw_csrng_ast_fips + desc: ''' + Verify the connectivity of AST and CSRNG. + ''' + stage: V2 + tests: ["ast_csrng_es_req", + "ast_csrng_es_rsp_es_ack", + "ast_csrng_es_rsp_es_bits", + "ast_csrng_es_rsp_es_fips"] + tags: ["conn"] + } + + ///////////////////////// + // jtag.csv // + ///////////////////////// + { + name: flash_jtag + desc: "Verify jtag interface is connected to flash_phy_req interface." + stage: V2 + tests: ["pinmux_flash_ctrl_tck", "pinmux_flash_ctrl_tms", "pinmux_flash_ctrl_tdi", + "pinmux_flash_ctrl_tdo", "pinmux_flash_ctrl_tdo_en"] + tags: ["conn"] + } + { + name: lc_jtag_trst + desc: "Verify jtag rst pin is connected to lc_ctrl interface." + stage: V2 + tests: ["pinmux_lc_ctrl_jtag_req", "pinmux_lc_ctrl_jtag_rsp"] + tags: ["conn"] + } + + ////////////////////////// + // lc_ctrl_broadcast.sv // + ////////////////////////// + { + name: lc_escalate_en + desc: '''Verify lc_ctrl's `lc_escalate_en_o` is connected to the following blocks' + `lc_escalate_en_i`: + - otp_ctrl + - aon_timer + - sram_ctrl main + - sram_ctrl retention + - flash_ctrl + - aes + - kmac + - otbn + ''' + stage: V2 + tests: ["lc_escalate_en_otp", + "lc_escalate_en_aon_timer", + "lc_escalate_en_sram_main", + "lc_escalate_en_sram_ret", + "lc_escalate_en_flash", + "lc_escalate_en_aes", + "lc_escalate_en_kmac", + "lc_escalate_en_otbn"] + tags: ["conn"] + } + { + name: lc_keymgr_en + desc: "Verify that lc_ctrl's keymanager enable signal and diversification value are correctly connected to the keymgr." + stage: V2 + tests: ["lc_keymgr_en_keymgr", + "lc_keymgr_div_keymgr"] + tags: ["conn"] + } + { + name: lc_nvm_debug_en + desc: "Verify lc_ctrl's lc_nvm_debug_en is connected correctly to flash_ctrl." + stage: V2 + tests: ["lc_nvm_debug_en_flash_ctrl"] + tags: ["conn"] + } + { + name: lc_cpu_en + desc: "Verify that the lc_ctrl's lc_cpu_en_o signal is correctly connected to rv_core_ibex." + stage: V2 + tests: ["lc_cpu_en_rv_core_ibex"] + tags: ["conn"] + } + { + name: lc_hw_debug_en + desc: "Verify that lc_ctrl's lc_hw_debug_en_o signal is correctly connected to IPs." + stage: V2 + tests: ["lc_hw_debug_en_pwrmgr", + "lc_hw_debug_en_clkmgr", + "lc_hw_debug_en_pinmux", + "lc_hw_debug_en_sram_ctrl_main", + "lc_hw_debug_en_rv_dm", + "lc_hw_debug_en_csrng"] + tags: ["conn"] + } + { + name: lc_hw_dft_en + desc: "Verify that lc_ctrl's lc_dft_en_o signal is correctly connected to IPs." + stage: V2 + tests: ["lc_dft_en_otp", + "lc_dft_en_pwrmgr", + "lc_dft_en_pinmux", + "lc_dft_en_ast"] + tags: ["conn"] + } + { + name: lc_flash_otbn_rma + desc: "Verify lc_ctrl's RMA request connections." + stage: V2 + tests: ["lc_rma_seed_flash_ctrl", + "lc_rma_req_flash_ctrl", + "flash_ctrl_rma_ack_otbn", + "otbn_rma_ack_lc"] + tags: ["conn"] + } + { + name: lc_clk_byp + desc: "Verify lc_ctrl's clock bypass request connections." + stage: V2 + tests: ["lc_clk_byp_req_clkmgr", + "clkmgr_clk_byp_ack_lc"] + tags: ["conn"] + } + { + name: lc_otp_check_byp + desc: "Verify lc_ctrl's check bypass signal is correctly connected to OTP (used when programming a life cycle transition)." + stage: V2 + tests: ["lc_check_byp_en_otp"] + tags: ["conn"] + } + { + name: lc_access_control + desc: "Verify lc_ctrl's access control modulation signals are correctly connected to flash and OTP." + stage: V2 + tests: ["lc_creator_seed_sw_rw_en_otp", + "lc_seed_hw_rd_en_otp", + "lc_creator_seed_sw_rw_en_flash", + "lc_seed_hw_rd_en_flash", + "lc_owner_seed_sw_rw_en_flash", + "lc_iso_part_sw_rd_en_flash", + "lc_iso_part_sw_wr_en_flash"] + tags: ["conn"] + } + ///////////////////////// + // pwrmgr_rstmgr.sv // + ///////////////////////// + { + name: pwrmgr_rst_lc_req + desc: '''Verify pwrmgr's `rst_lc_req` is connected to rstmgr's `rst_lc_req`.''' + stage: V2 + tests: ["pwrmgr_rst_lc_req"] + tags: ["conn"] + } + { + name: pwrmgr_rst_sys_req + desc: '''Verify pwrmgr's `rst_sys_req` is connected to rstmgr's `rst_sys_req`.''' + stage: V2 + tests: ["pwrmgr_rst_sys_req"] + tags: ["conn"] + } + { + name: rstmgr_rst_lc_src_n + desc: '''Verify rstmgr's `rst_lc_src_n` is connected to pwrmgr's `rst_lc_src_n`.''' + stage: V2 + tests: ["rstmgr_rst_lc_src_n"] + tags: ["conn"] + } + { + name: rstmgr_rst_sys_src_n + desc: '''Verify rstmgr's `rst_sys_src_n` is connected to rstmgr's `rst_sys_src_n`.''' + stage: V2 + tests: ["rstmgr_rst_sys_src_n"] + tags: ["conn"] + } + + ///////////////////////// + // rstmgr_resets_o.csv // + ///////////////////////// + { + name: rst_i2c0_n_d0 + desc: '''Verify rstmgr's rst_i2c0_n[1] is connected to i2c0's rst_ni.''' + stage: V2 + tests: ["rstmgr_i2c0_d0_i2c0_rst_ni"] + tags: ["conn"] + } + { + name: rst_lc_aon_aon + desc: '''Verify rstmgr's rst_lc_aon_n[0] is connected to the following: + - aon_timer's rst_aon_ni + - clkmgr's rst_aon_ni + - pinmux's rst_aon_ni + ''' + stage: V2 + tests: ["rstmgr_lc_aon_aon_aon_timer_rst_aon_ni", + "rstmgr_lc_aon_aon_clkmgr_rst_aon_ni", + "rstmgr_lc_aon_aon_pinmux_rst_aon_ni"] + tags: ["conn"] + } + + { + name: rst_lc_io_div2_n_aon + desc: '''Verify rstmgr's lc_io_div2_aon is connected to clkmgr's rst_io_div2_ni.''' + stage: V2 + tests: ["rstmgr_lc_io_div2_aon_clkmgr_rst_io_div2_ni"] + tags: ["conn"] + } + { + name: rst_lc_io_div4_aon + desc: '''Verify rstmgr's rst_lc_io_div4_n[0] is connected to the following: + - aon_timer's rst_ni + - clkmgr's rst_ni + - clkmgr's rst_io_div4_ni + - pinmux's rst_ni + - sram_ctrl_ret's rst_otp_ni + - rstmgr's rst_ni + ''' + stage: V2 + tests: ["rstmgr_lc_io_div4_aon_aon_timer_rst_ni", + "rstmgr_lc_io_div4_aon_clkmgr_rst_ni", + "rstmgr_lc_io_div4_aon_clkmgr_rst_io_div4_ni", + "rstmgr_lc_io_div4_aon_pwrmgr_rst_lc_ni", + "rstmgr_lc_io_div4_aon_pinmux_rst_ni", + "rstmgr_lc_io_div4_aon_sram_ctrl_ret_rst_otp_ni", + "rstmgr_lc_io_div4_aon_rstmgr_rst_ni"] + tags: ["conn"] + } + { + name: rst_lc_io_div4_d0 + desc: '''Verify rstmgr's rst_lc_io_div4_n[1] is connected to the following: + - alert_handler's rst_ni + - lc_ctrl's rst_ni + - otbn's rst_otp_ni + - otp_ctrl's rst_ni + - pwrmgr's rst_lc_ni + - rv_core_ibex's rst_esc_ni + - rv_core_ibex's rst_otp_ni + - sram_ctrl_main's rst_otp_ni + ''' + stage: V2 + tests: ["rstmgr_lc_io_div4_d0_alert_handler_rst_ni", + "rstmgr_lc_io_div4_d0_lc_ctrl_rst_ni", + "rstmgr_lc_io_div4_d0_otbn_rst_otp_ni", + "rstmgr_lc_io_div4_d0_otp_ctrl_rst_ni", + "rstmgr_lc_io_div4_d0_rv_core_ibex_rst_esc_ni", + "rstmgr_lc_io_div4_d0_rv_core_ibex_rst_otp_ni", + "rstmgr_lc_io_div4_d0_sram_ctrl_main_rst_otp_ni"] + tags: ["conn"] + } + { + name: rst_lc_io_div4_shadowed_aon + desc: '''Verify rstmgr's rst_lc_io_div4_shadowed_n[0] is connected to clkmgr's rst_shadowed_ni.''' + stage: V2 + tests: ["rstmgr_lc_io_div4_shadowed_aon_clkmgr_rst_shadowed_ni"] + tags: ["conn"] + } + { + name: rst_lc_io_div4_shadowed_d0 + desc: '''Verify rstmgr's rst_lc_io_div4_shadowed_n[1] is connected to alert_handler's rst_shadowed_ni.''' + stage: V2 + tests: ["rstmgr_lc_io_div4_shadowed_d0_alert_handler_rst_shadowed_ni"] + tags: ["conn"] + } + { + name: rst_lc_aon + desc: '''Verify rstmgr's rst_lc_n[0] is connected to clkmgr's rst_main_ni.''' + stage: V2 + tests: ["rstmgr_lc_aon_clkmgr_rst_main_ni"] + tags: ["conn"] + } + { + name: rst_lc_io_aon + desc: '''Verify rstmgr's rst_lc_io_n[0] is connected to clkmgr's rst_io_ni.''' + stage: V2 + tests: ["rstmgr_lc_io_aon_clkmgr_rst_io_ni"] + tags: ["conn"] + } + { + name: rst_por_aon_aon + desc: '''Verify rstmgr's rst_por_aon_n[0] is connected to pwrmgr's rst_slow_ni.''' + stage: V2 + tests: ["rstmgr_por_aon_aon_pwrmgr_rst_slow_ni"] + tags: ["conn"] + } + { + name: rst_por_aon_d0 + desc: '''Verify rstmgr's rst_por_aon_n[1] is connected to pwrmgr's rst_main_ni.''' + stage: V2 + tests: ["rstmgr_por_aon_d0_pwrmgr_rst_main_ni"] + tags: ["conn"] + } + { + name: rst_por_aon + desc: '''Verify rstmgr's rst_por_n[0] is connected to clkmgr's rst_root_main_ni.''' + stage: V2 + tests: ["rstmgr_por_aon_clkmgr_rst_root_main_ni"] + tags: ["conn"] + } + { + name: rst_por_io_aon + desc: '''Verify rstmgr's rst_por_io_n[0] is connected to clkmgr's rst_root_io_ni.''' + stage: V2 + tests: ["rstmgr_por_io_aon_clkmgr_rst_root_io_ni"] + tags: ["conn"] + } + { + name: rst_por_io_div2_aon + desc: '''Verify rstmgr's rst_por_io_div2_n[0] is connected to clkmgr's rst_root_io_div2_ni.''' + stage: V2 + tests: ["rstmgr_por_io_div2_aon_clkmgr_rst_root_io_div2_ni"] + tags: ["conn"] + } + { + name: rst_por_io_div4_aon + desc: '''Verify rstmgr's rst_por_io_div4_n[0] is connected to the following: + - clkmgr's rst_root_io_div4_ni + - clkmgr's rst_root_ni + - pwrmgr's rst_ni + - rstmgr's rst_por_ni + ''' + stage: V2 + tests: ["rstmgr_por_io_div4_aon_clkmgr_rst_root_io_div4_ni", + "rstmgr_por_io_div4_aon_clkmgr_rst_root_ni", + "rstmgr_por_io_div4_aon_pwrmgr_rst_ni", + "rstmgr_por_io_div4_aon_rstmgr_rst_ni"] + tags: ["conn"] + } + { + name: rst_spi_device_d0 + desc: '''Verify rstmgr's rst_spi_device_n[1] is connected to spi_device's rst_ni.''' + stage: V2 + tests: ["rstmgr_spi_device_d0_spi_device_rst_ni"] + tags: ["conn"] + } + { + name: rst_spi_host0_d0 + desc: '''Verify rstmgr's rst_spi_host0_n[1] is connected to spi_host0's rst_ni.''' + stage: V2 + tests: ["rstmgr_spi_host0_d0_spi_host0_rst_ni"] + tags: ["conn"] + } + { + name: rst_sys_aon_aon + desc: '''Verify rstmgr's rst_sys_aon_n[0] is connected to the following: + - adc_ctrl's rst_aon_ni + - sensor_ctrl's rst_aon_ni + ''' + stage: V2 + tests: ["rstmgr_sys_aon_aon_adc_ctrl_rst_aon_ni", + "rstmgr_sys_aon_aon_sensor_ctrl_rst_aon_ni"] + tags: ["conn"] + } + { + name: rst_sys_io_d0 + desc: '''Verify rstmgr's rst_sys_io_n[1] is connected to xbar_main's rst_spi_host0_ni.''' + stage: V2 + tests: ["rstmgr_sys_io_d0_xbar_main_rst_spi_host0_ni"] + tags: ["conn"] + } + { + name: rst_sys_io_div4_aon + desc: '''Verify rstmgr's rst_sys_io_div4_n[0] is connected to the following: + - adc_ctrl's rst_ni + - sensor_ctrl's rst_ni + - sram_ctrl_ret's rst_ni + ''' + stage: V2 + tests: ["rstmgr_sys_io_div4_aon_adc_ctrl_rst_ni", + "rstmgr_sys_io_div4_aon_sensor_ctrl_rst_ni", + "rstmgr_sys_io_div4_aon_sram_ctrl_ret_rst_ni"] + tags: ["conn"] + } + { + name: rst_sys_io_div4_d0 + desc: '''Verify rstmgr's rst_sys_io_div4_n[1] is connected to the following: + - flash_ctrl's rst_otp_ni + - gpio's rst_ni + - rv_timer's rst_ni + - uart0's rst_ni + - xbar_main's rst_fixed_ni + - xbar_peri's rst_peri_ni + ''' + stage: V2 + tests: ["rstmgr_sys_io_div4_d0_flash_ctrl_rst_otp_ni", + "rstmgr_sys_io_div4_d0_gpio_rst_ni", + "rstmgr_sys_io_div4_d0_rv_timer_rst_ni", + "rstmgr_sys_io_div4_d0_uart0_rst_ni", + "rstmgr_sys_io_div4_d0_xbar_main_rst_fixed_ni", + "rstmgr_sys_io_div4_d0_xbar_peri_rst_peri_ni"] + tags: ["conn"] + } + { + name: rst_sys_d0 + desc: '''Verify rstmgr's rst_sys_n[1] is connected to the following: + - aes's rst_edn_ni + - aes's rst_ni + - alert_handler's rst_edn_ni + - csrng's rst_ni + - edn0's rst_ni + - edn1's rst_ni + - flash_ctrl's rst_ni + - hmac's rst_ni + - keymgr's rst_edn_ni + - keymgr's rst_ni + - kmac's rst_edn_ni + - kmac's rst_ni + - otbn's rst_edn_ni + - otbn's rst_ni + - lc_ctrl's rst_kmac_ni + - otp_ctrl's rst_edn_ni + - rv_core_ibex's rst_edn_ni + - rv_core_ibex's rst_ni + - rv_plic's rst_ni + - sram_ctrl_main's rst_ni + - xbar_main's rst_main_ni + ''' + stage: V2 + tests: ["rstmgr_sys_d0_aes_rst_edn_ni", + "rstmgr_sys_d0_aes_rst_ni", + "rstmgr_sys_d0_alert_handler_rst_edn_ni", + "rstmgr_sys_d0_csrng_rst_ni", + "rstmgr_sys_d0_edn0_rst_ni", + "rstmgr_sys_d0_edn1_rst_ni", + "rstmgr_sys_d0_flash_ctrl_rst_ni", + "rstmgr_sys_d0_hmac_rst_ni", + "rstmgr_sys_d0_keymgr_rst_edn_ni", + "rstmgr_sys_d0_keymgr_rst_ni", + "rstmgr_sys_d0_kmac_rst_edn_ni", + "rstmgr_sys_d0_kmac_rst_ni", + "rstmgr_sys_d0_otbn_rst_edn_ni", + "rstmgr_sys_d0_otbn_rst_ni", + "rstmgr_sys_d0_lc_ctrl_rst_kmac_ni", + "rstmgr_sys_d0_otp_ctrl_rst_edn_ni", + "rstmgr_sys_d0_rv_core_ibex_rst_edn_ni", + "rstmgr_sys_d0_rv_core_ibex_rst_ni", + "rstmgr_sys_d0_rv_plic_rst_ni", + "rstmgr_sys_d0_sram_ctrl_main_rst_ni", + "rstmgr_sys_d0_xbar_main_rst_main_ni"] + tags: ["conn"] + } + { + name: rst_sys_shadowed_d0 + desc: '''Verify rstmgr's rst_sys_shadowed_n[1] is connected to the following: + - aes's rst_shadowed_ni + - flash_ctrl's rst_shadowed_ni + - keymgr's rst_shadowed_ni + - kmac's rst_shadowed_ni + ''' + stage: V2 + tests: ["rstmgr_sys_shadowed_d0_aes_rst_shadowed_ni", + "rstmgr_sys_shadowed_d0_flash_ctrl_rst_shadowed_ni", + "rstmgr_sys_shadowed_d0_keymgr_rst_shadowed_ni", + "rstmgr_sys_shadowed_d0_kmac_rst_shadowed_ni"] + tags: ["conn"] + } + /////////////////////// + // rstmgr_rst_en.csv // + /////////////////////// + { + name: rst_en_i2c0_d0 + desc: '''Verify rstmgr's rst_en_o.i2c0[1] connects to alert_handler's lpg_rst_en[2].''' + stage: V2 + tests: ["rstmgr_i2c0_d0_alert_2_rst_en"] + tags: ["conn"] + } + { + name: rst_en_lc_d0 + desc: '''Verify rstmgr's rst_en_o.lc[1] connects to alert_handler's lpg_rst_en[19].''' + stage: V2 + tests: ["rstmgr_lc_d0_alert_19_rst_en"] + tags: ["conn"] + } + { + name: rst_en_lc_io_div4_aon + desc: '''Verify rstmgr's rst_en_o.lc_io_div4[0] connects to the following: + - alert_handler's lpg_rst_en[11] + - alert_handler's lpg_rst_en[15] + ''' + stage: V2 + tests: ["rstmgr_lc_io_div4_aon_alert_11_rst_en", + "rstmgr_lc_io_div4_aon_alert_15_rst_en"] + tags: ["conn"] + } + { + name: rst_en_lc_io_div4_d0 + desc: '''Verify rstmgr's rst_en_o.lc_io_div4[1] connects to alert_handler's lpg_rst_en[6].''' + stage: V2 + tests: ["rstmgr_lc_io_div4_d0_alert_6_rst_en"] + tags: ["conn"] + } + { + name: rst_en_por_io_div4_d0 + desc: '''Verify rstmgr's rst_en_o.por_io_div4[1] connects to alert_handler's lpg_rst_en[10].''' + stage: V2 + tests: ["rstmgr_por_io_div4_d0_alert_10_rst_en"] + tags: ["conn"] + } + { + name: rst_en_spi_host0_d0 + desc: '''Verify rstmgr's rst_en_o.spi_host0[1] connects to alert_handler's lpg_rst_en[7].''' + stage: V2 + tests: ["rstmgr_spi_host0_d0_alert_7_rst_en"] + tags: ["conn"] + } + { + name: rst_en_spi_device_d0 + desc: '''Verify rstmgr's rst_en_o.spi_device[1] connects to alert_handler's lpg_rst_en[1].''' + stage: V2 + tests: ["rstmgr_spi_device_d0_alert_1_rst_en"] + tags: ["conn"] + } + { + name: rst_en_sys_d0 + desc: '''Verify rstmgr's rst_en_o.sys[1] connects to the following: + - alert_handler's lpg_rst_en[18] + - alert_handler's lpg_rst_en[20] + - alert_handler's lpg_rst_en[21] + ''' + stage: V2 + tests: ["rstmgr_sys_d0_alert_18_rst_en", + "rstmgr_sys_d0_alert_20_rst_en", + "rstmgr_sys_d0_alert_21_rst_en"] + tags: ["conn"] + } + { + name: rst_en_sys_io_div4_aon + desc: '''Verify rstmgr's rst_en_o.sys_io_div4[0] connects to the following: + - alert_handler's lpg_rst_en[12] + - alert_handler's lpg_rst_en[13] + - alert_handler's lpg_rst_en[14] + - alert_handler's lpg_rst_en[17] + ''' + stage: V2 + tests: ["rstmgr_sys_io_div4_aon_alert_12_rst_en", + "rstmgr_sys_io_div4_aon_alert_13_rst_en", + "rstmgr_sys_io_div4_aon_alert_14_rst_en", + "rstmgr_sys_io_div4_aon_alert_17_rst_en"] + tags: ["conn"] + } + { + name: rst_en_sys_io_div4_d0 + desc: '''Verify rstmgr's rst_en_o.sys_io_div4[1] connects to the following: + - alert_handler's lpg_rst_en[0] + - alert_handler's lpg_rst_en[5] + - alert_handler's lpg_rst_en[16] + ''' + stage: V2 + tests: ["rstmgr_sys_io_div4_d0_alert_0_rst_en", + "rstmgr_sys_io_div4_d0_alert_5_rst_en", + "rstmgr_sys_io_div4_d0_alert_16_rst_en"] + tags: ["conn"] + } + + ////////////////////////// + // rstmgr_crashdump.csv // + ////////////////////////// + { + name: rstmgr_crashdump + desc: '''Verify that the Ibex and alert_handler crashdump outputs are correctly connected to the rstmgr.''' + stage: V2 + tests: ["alert_handler_rstmgr_crashdump", + "rv_core_ibex_rstmgr_crashdump"] + tags: ["conn"] + } + + ///////////////////////// + // analog_sigs.csv // + ///////////////////////// + { + name: otp_ctrl_external_voltage + desc: "Verify the connectivity between the external voltage pad and otp_ctrl." + stage: V2 + tests: ["otp_ext_volt"] + tags: ["conn"] + } + { + name: flash_ctrl_test_voltage + desc: "Verify the connectivity between the test voltage pad and flash_ctrl." + stage: V2 + tests: ["flash_test_volt"] + tags: ["conn"] + } + { + name: flash_ctrl_test_mode + desc: "Verify the connectivity between the test mode pads and flash_ctrl." + stage: V2 + tests: ["flash_test_mode0", + "flash_test_mode1"] + tags: ["conn"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/chip_testplan.hjson b/hw/top_darjeeling_no_ibex/data/chip_testplan.hjson new file mode 100644 index 00000000000..f70ae758af6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/chip_testplan.hjson @@ -0,0 +1,3007 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "chip" + + // TODO: remove the common testplans if not applicable + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + // TODO #5484, comment these 2 lines out because spi host memory is dummy + // "hw/dv/tools/dvsim/testplans/mem_testplan.hjson", + // Integrity error is tested in a SW test. + "hw/dv/tools/dvsim/testplans/tl_device_access_types_wo_intg_testplan.hjson", + "hw/ip/tlul/data/tlul_testplan.hjson", + "sw/device/silicon_creator/rom/data/rom_e2e_testplan.hjson", + "hw/top_darjeeling/data/chip_conn_testplan.hjson"] + + testpoints: [ + ///////////////////////////////////////////////////////////// + // IO Peripherals // + // UART, GPIO, I2C, SPIDEV, SPIHOST, PINMUX & PADCTRL, MBX // + ///////////////////////////////////////////////////////////// + + // UART (pre-verified IP) integration tests: + { + name: chip_sw_uart_tx_rx + desc: '''Verify transmission of data over the TX and RX port. + + SW test sends a known payload over the TX port. The testbench, at the same time + sends a known payload over RX. On reception, both payloads are checked for integrity. + SW validates the reception of TX watermark, RX watermark, and the TX empty interrupts. + Choosing the max supported baud rate for the UART is sufficient. + ''' + stage: V1 + tests: ["chip_sw_uart_tx_rx"] + tags: ["gls"] + } + { + name: chip_sw_uart_rx_overflow + desc: '''Verify the RX overflow interrupt. + + The testbench sends a random payload of size greater than the RX fifo size (32). The SW + ignores the received the data to allow the RX overflow interrupt to assert. + ''' + stage: V1 + tests: ["chip_sw_uart_tx_rx"] + } + { + name: chip_sw_uart_rand_baudrate + desc: '''Verify UART transmission of data at various speeds. + + Randomly pick one of the UART instances and configure it to run with any of these baud + rates - 9600bps, 115200bps, 230400bps, 128Kbps, 256Kbps, 1Mkbps, 1.5Mkbps. + + ''' + stage: V1 + tests: ["chip_sw_uart_rand_baudrate"] + } + { + name: chip_sw_uart_tx_rx_alt_clk_freq + desc: '''Verify the transmission of UART via using external clock as uart core clock. + + Extend from chip_sw_uart_rand_baudrate with following added settings. + - Configure LC to RMA state, so that it allows clkmgr to use external clock. + - Configure clkmgr to select external clock. + - Randomize `HI_SPEED_SEL`, so that uart core clock frequency can be either + ext_clk_freq / 4 or ext_clk_freq / 2. + ''' + stage: V1 + tests: ["chip_sw_uart_tx_rx_alt_clk_freq", "chip_sw_uart_tx_rx_alt_clk_freq_low_speed"] + } + + // GPIO (pre-verified IP) integration tests: + { + name: chip_sw_gpio_out + desc: '''Verify GPIO outputs. + + SW test configures the GPIOs to be in the output mode. The test walks a 1 through the + pins. The testbench checks the value for correctness and verifies that there is no + aliasing between the pins. + ''' + stage: V1 + tests: ["chip_sw_gpio"] + } + { + name: chip_sw_gpio_in + desc: '''Verify GPIO inputs. + + The SW test configures the GPIOs to be in input mode. The testbench walks a 1 through + the pins. SW test ensures that the GPIO values read from the CSR is correct. + ''' + stage: V1 + tests: ["chip_sw_gpio"] + } + { + name: chip_sw_gpio_irq + desc: '''Verify GPIO interrupts. + + The SW test configures the GPIOs to be in input mode and enables all of them to generate + an interrupt. The testbench walks a 1 through the pins. SW test ensures that the + interrupt corresponding to the right pin is seen. + ''' + stage: V1 + tests: ["chip_sw_gpio"] + } + + // SPI_DEVICE (pre-verified IP) integration tests: + { + name: chip_sw_spi_device_flash_mode + desc: '''Verify the SPI device in flash mode. + + - SW puts the SPI device in flash mode + - Load a firmware image (bootstrap) through flash commands to the spi_device memory. + - SW verifies the integrity of the image upon reception by reading the spi_device + memory. + - Ensure the image is executed correctly + ''' + stage: V2 + tests: ["chip_sw_uart_tx_rx_bootstrap"] + } + { + name: chip_sw_spi_device_pass_through + desc: '''Verify the pass through mode from an end-to-end perspective. + + - Configure the SPI device and host in pass through mode. + - Program the cmd_filter_* CSRs to filter out random commands. + - Configure and enable spi_host0 + - Send a random flash commands over the SPI device interface (chip IOs) from the + testbench. + - Verify the flash commands which pass through spi_host0, are received on chip IOs. + - Verify that only the payloads that are not filtered show up on the SPI host interface + at chip IOs. + - Run with min (6MHz), typical (24Mhz) and max (30MHz) SPI clk frequencies. + - Run with single, dual and quad SPI modes. + - Testbench should test the following commands: + - Read Normal, Fast Read, Fast Dual, Fast Quad, Chip Erase, Program + ''' + stage: V2 + tests: ["chip_sw_spi_device_pass_through"] + } + + { + name: chip_sw_spi_device_pass_through_flash_model + desc: '''Verify the command filtering mechanism in passthrough mode. + + - Extend the chip_spi_device_pass_through test. + - Connect with a real flash model on spi_host + - Verify that the flash commands are received and interpreted correctly in the flash + model + ''' + stage: V3 + tests: [] + } + + { + name: chip_sw_spi_device_pass_through_collision + desc: '''Verify the collisions on driving spi_host is handled properly. + + - Enable upload related interrupts and configure the spi_device in passthrough mode. + - Configure a command slot to enable upload for a flash program/erase command. + - Excecute two parallel threads: + 1. SPI host agent. + - Send this command via an upstream SPI host agent, then the agent keeps sending + read_status to poll the busy bit. + - When the busy bit is low, issue a read command to read data from the downstream + SPI port, and check data correctness. + 2. A SW process. + - SW receives an upload interrupt and reads the command in the upload fifo to check. + - SW configures the SPI host that shows the same downstream port, to send the + uploaded command to the downstream SPI port. + - SW clears busy bit to allow the upstream SPI host to proceed to the next command. + ''' + stage: V2 + tests: ["chip_sw_spi_device_pass_through_collision"] + } + { + name: chip_sw_spi_device_tpm + desc: '''Verify the basic operation of the spi tpm mode. + + - The testbench sends a known payload over the chip's SPI device tpm input port. + - The testbench sends a read command. + - The software test should playback the data received in the write command as the read + response. + - The testbench should check if the written and read data match. + ''' + stage: V2 + tests: ["chip_sw_spi_device_tpm"] + } + + { + name: chip_sw_spi_device_output_when_disabled_or_sleeping + desc: '''Verify spi_device output values when spi_device is disabled or the chip is sleeping. + + SW needs to be able to set the SPI output value when spi_device is disabled or the + chip is sleeping, to either all-zeros or all-ones, depending on integration + requirements. The following scenarios have to be verified: + + After power-on reset: + - SW to configure pinmux retention logic so that the chip pins connected to + spi_device outputs are (a) always zero or (b) always one (SW needs to be able to + choose between a and b). + - DV environment to check that SPI outputs match configuration by SW. + + Going to sleep: + - SW to disable spi_device, wait until CSb is high, configure pinmux retention logic + as it would after POR, and put chip to sleep. + - DV environment to check that SPI outputs match configuration by SW. + + Wake up from sleep: + - DV environment to wake chip from sleep. + - SW to enable spi_device and disable retention logic. + - DV environment to check that SPI transactions work as usual. + ''' + stage: V3 + tests: [] + } + + // SPI_HOST (pre-verified IP) integration tests: + { + name: chip_sw_spi_host_tx_rx + desc: '''Verify the transmission of data on the chip's SPI host port. + + - Program the SPI host to send a known payload out of the chip on the SPI host ports. + - The testbench receives the payload and plays it back to the SPI host interface. + - The SW verifies the sent payload matches the read response and services SPI event + interrupts. + - Run with min and max SPI clk frequencies and with single, dual and quad SPI modes. + + Verify all SPI host instances in the chip. + ''' + stage: V2 + tests: ["chip_sw_spi_host_tx_rx"] + } + + // I2C (pre-verified IP) integration tests: + { + name: chip_sw_i2c_host_tx_rx + desc: '''Verify the transmission of data over the chip's I2C host interface. + + - Program the I2C to be in host mode. + - The SW test writes a known payload over the chip's I2C host interface, which is + received by the testbench. + - The testbench then loops this data back to the chip's I2C host and exercises the + read interface. + - SW validates the reception of FMT watermark and trans complete interrupts. + - SW validates that the data read matches the original data written. + - Verify the virtual / true open drain capability. + + Verify all instances of I2C in the chip. + ''' + stage: V2 + tests: ["chip_sw_i2c_host_tx_rx"] + } + { + name: chip_sw_i2c_device_tx_rx + desc: '''Verify the transmission of data over the chip's I2C device interface. + + - Program the I2C to be in device mode. + - The testbench writes a known payload over the chip's I2C device interface, which is + received and verified by the SW test for correctness. + - The testbench reads and verifies a known payload over the chip's I2C device interface, + - SW validates the reception of tx empty and trans complete interrupts. + - Verify the virtual / true open drain capability. + + Verify all instances of I2C in the chip. + ''' + stage: V2 + tests: ["chip_sw_i2c_device_tx_rx"] + } + + // PINMUX & PADRING (pre-verified IP) integration tests: + { + name: chip_pin_mux + desc: '''Verify the MIO muxing at input and output sides. + + - Enable `stub_cpu` mode. + - Add a forcing interface to pinmux's pad-facing DIO and MIO ports, including the output + enables; and a sampling interface for the peripheral facing DIO and MIO ports. + - Similarly, add a driving / sampling interface for all DIOs and MIOs at the chip pads. + - In the output direction: + - Program all MIO outsel and pad attribute registers to random values. + - Force the pad-facing pinmux MIO ports and output enables to random values. + - Verify all MIO pad values for correctness. + - For the input direction: + - Program all MIO insel and pad attribute registers to random values. + - Drive the MIO pads to random values. + - Probe and sample the peripheral facing MIO ports of the pinmux and verify the values + for correctness. + - Follow a similar testing procedure for DIOs. + ''' + stage: V2 + tests: ["chip_padctrl_attributes"] + } + { + name: chip_padctrl_attributes + desc: '''Verify pad attribute settings for all MIO and DIO pads. + + - Follow the same procedure as the `chip_pin_mux` test, ensuring the padctrl attribute + registers for all MIOs and DIOs are also randomized when verifying the outcomes. + - Verify weak pull enable, output inversion and virtual open drain and drive strength + (bit 0) signaling in the output direction. + - Verify weak pull enable and input inversion in the input direction. + - Verify multiple pad attributes for each pad set at the same time through + randomization. + + Cross-references the `chip_pin_mux` test. + ''' + stage: V2 + tests: ["chip_padctrl_attributes"] + } + { + name: chip_sw_sleep_pin_mio_dio_val + desc: '''Verify the MIO output values in any sleep states. + + - Pick between normal sleep and deep sleep randomly + - Pick between tie-0, tie-1, or High-Z randomly for all muxed, + dedicated outputs coming from non-AON IPs. + + SW programs the MIO OUTSEL CSRs to ensure that in sleep it randomly picks + between tie-0, tie-1 or hi-Z for all muxed outputs coming from non-AON IPs. If an AON + peripheral output is muxed, then that peripheral's output is selected to ensure in deep + sleep the peripheral can continue its signaling even in deep sleep. The testbench + verifies the correctness of the reflected values once the chip goes into deep sleep. + This is replicated for DIO pins as well. + + In this test, passthrough feature is not tested. + ''' + stage: V2 + tests: ["chip_sw_sleep_pin_mio_dio_val"] + } + { + name: chip_sw_sleep_pin_wake + desc: '''Verify pin wake up from any sleep states. + + Verify one of the 8 possible MIO or DIO pad inputs (randomly configured) can cause the + chip to wake up from sleep state. Verifying wake on posedge is sufficient for the chip + level integration testing. Upon wake up, SW reads the wake cause CSR to verify + correctness. + + For V3, enhance this test to configure all wakeup detectors rather than configure only + one, then have the host randomly pick one of the IOs configured for wakeup in one of + those detectors. Also, randomize and test all wakeup modes and enable debounce filter. + ''' + stage: V2 + tests: ["chip_sw_sleep_pin_wake"] + } + { + name: chip_sw_sleep_pin_retention + desc: '''Verify the retention logic in pinmux that is activated during deep sleep. + + - Pick a pin (such as GPIO0) and enable it in output mode. Set a known value to it (0 or + 1) and verify the correctless of the value on the chip IO. + - Program the pin's retention value during deep sleep to be opposite of the active power + value programmed in the previous step. + - Reuse an existing deep sleep / low power wake up test, such as + `chip_sw_sleep_pin_wake` test to enter low power. + - Once the chip enters the deep sleep state, verify that this pin holds the correct + retention value throughout the low power state. + - Wake up the chip from sleep using the chosen method. + - Verify the pin value at the chip IOs is no longer holding the retention value once the + chip is back in active power. + ''' + stage: V2 + tests: ["chip_sw_sleep_pin_retention"] + } + { + name: chip_sw_mbx_smoke + desc: '''Verify the mailbox integrations with a basic smoketest + + - Random-cyclicly select a mailbox to perform a req-rsp transaction with + - TB(requester) writes a message into the imbx, then awaits a response + - sw(responder) awaits the request, reads it then replies with a modified version + of the original message + - TB checks if the received response is as-expected + - Requester randomly selects between an irq or polling-based handler + - Responder polls the peripheral to await transaction completed + - Repeat process for all mailboxes in the system + ''' + stage: V2 + tests: ["chip_sw_mbx_smoke"] + } + + ////////////////////////////////////////////////////////////////////////////////////// + // System Peripherals // + // XBAR, RV_DM, RV_TIMER, AON_TIMER, PLIC, CLK/RST/PWR MGR, ALERT_HANDLER, LC_CTRL, // + ////////////////////////////////////////////////////////////////////////////////////// + + // XBAR (pre-verified IP) tests: + { + name: chip_sw_data_integrity + desc: ''' + Verify the alert signaling mechanism due to integrity violations of load ops. + + An SW test which performs the following on main and retention SRAMs to verify the memory + end-to-end integrity scheme: + - Corrupt a random data / integrity bit in the memory using SV force. + - SW reads that address and the corrupted data is sent to ibex. + - Verify that ibex detects the integrity violation and triggers an alert. + - Check the alert up to the NMI phase and make sure that the alert cause is from Ibex. + ''' + stage: V2 + tests: ["chip_sw_data_integrity_escalation"] + } + { + name: chip_sw_instruction_integrity + desc: ''' + Verify the alert signaling mechanism due to integrity violations of instruction fetches. + + An SW test which performs the following on main SRAM to verify the memory end-to-end + integrity scheme: + - Corrupt a data / integrity bit in a test function in the main SRAM using SV force. + - SW jumps to that test function in the main SRAM. + - Verify that ibex detects the integrity violation and triggers an alert. + - Check the alert up to the NMI phase and make sure that the alert cause is from Ibex. + ''' + stage: V2 + tests: ["chip_sw_data_integrity_escalation"] + } + + // RV_DM (JTAG) tests: + { + name: chip_jtag_csr_rw + desc: ''' + Verify accessibility of all the CSRs in the chip over JTAG. + + - Shuffle the list of CSRs first to remove the effect of ordering. + - Write all CSRs via JTAG interface with a random value. + - Shuffle the list of CSRs yet again. + - Read all CSRs back and check their values for correctness while adhering to the CSR's + access policies. + - Accesses to CSRs external to `rv_dm` go through RV_DM SBA interface into the `xbar`. + ''' + stage: V2 + tests: ["chip_jtag_csr_rw"] + } + { + name: chip_jtag_mem_access + desc: ''' + Verify accessibility of all the memories in the chip over JTAG. + + This test will target the following memories in the chip: + sram_main, sram_ret, otbn i|dmem, ROM + + - Shuffle the list of memories first to remove the effect of ordering. + - Write a location in a randomly chosen set of addresses within each memory via JTAG + interface with random values. + - For read-only memories, preload the memory with random data via backdoor. + - Shuffle the list of memories again. + - Read the previously written addresses in the memories back again and check the read + value for correctness. Pick some random addresses to verify in case of read-only + memories. + ''' + stage: V2 + tests: ["chip_jtag_mem_access"] + } + { + name: chip_rv_dm_perform_debug + desc: ''' + - X-ref'ed with rom_e2e_jtag_inject from rom testplan. + - X-ref'ed with chip_sw_flash_lc_iso_part_sw_wr_en. + - X-ref'ed with manuf_cp_device_info_flash_wr from manufacturing testplan. + - Using the sram injection mechanism from rom_e2e_jtag_inject, load a SRAM program that + writes to isolated flash partition while the device is in TEST_UNLOCKED state. + - After writing, verify that the test program cannot read back the written value. + + ''' + stage: V3 + tests: ["rom_e2e_jtag_debug_test_unlocked0", "rom_e2e_jtag_debug_dev", + "rom_e2e_jtag_debug_rma"] + } + { + name: chip_rv_dm_ndm_reset_req + desc: '''Verify non-debug reset request initiated from RV_DM when the chip is awake. + + - Program some CSRs / mem that are under life cycle reset tree and system reset tree. + - Configure RV_DM to send NDM reset request to reset sytem reset tree. + - While NDM reset is ongoing, ensure the RV_DM debug module registers can still be + accessed. + - Read the programmed CSRs / mem to ensure that everything under system reset tree is + reset to the original values, while values under life cycle reset will be preserved. + - Read CSRs / mem in the debug domain to ensure that the values survive the reset. + ''' + stage: V2 + tests: ["chip_rv_dm_ndm_reset_req"] + } + { + name: chip_sw_rv_dm_ndm_reset_req_when_cpu_halted + desc: '''Verify non-debug reset request initiated from RV_DM when the CPU is in halted state. + + - Initialize the DUT in a HW-debug enabled life cycle state. + - Activate the RISCV debug module. + - Run some SW test on the CPU. + - Initiate a CPU halt request via JTAG. + - Wait for the CPU to be in halted state via JTAG by polling dmstatus.anyhalted. + - Deassert the CPU haltreq and verify that we are still in halted state. + - (Optional) Using the abstract command, read the dcsr register to verify the cause + reflects the debug halt request. + - Issue an NDM reset request. All non-debug parts of the chip should reset. Read the + dmstatus.anyhalted / dvstatus.allhalted and verify that they are cleared. + - Verify that the debug logic is fully accessible during this time, while the NDM reset + is being processed and the chip is rebooted, by continuously accessing the DMI + register space in `rv_dm` over JTAG. + - De-assert the NDM reset request and wait for the CPU to reboot and finish the post-NDM + reset phase of the test. + ''' + stage: V2 + tests: ["chip_sw_rv_dm_ndm_reset_req_when_cpu_halted"] + } + { + name: chip_rv_dm_access_after_wakeup + desc: '''Verify RV_DM works after wakes up from sleep. + + - Put the chip into sleep mode and then wake up (both deep sleep and normal sleep). + - If waking up from normal sleep, an activation should not be required for RV_DM CSR + accesses to work. + - If waking up from deep sleep, an activation is required for RV_DM CSR accesses to work. + ''' + stage: V2 + tests: ["chip_sw_rv_dm_access_after_wakeup"] + } + { + name: chip_sw_rv_dm_access_after_hw_reset + desc: '''Verify RV_DM works after a watchdog or escalated reset. + + - Access some RV_DM CSRs both before and after resets. + - An activation would be required, and the tap strap would also be sampled again. + ''' + stage: V3 + tests: ["chip_sw_rv_dm_access_after_escalation_reset"] + } + { + name: chip_rv_dm_lc_disabled + desc: '''Verify that the debug capabilities are disabled in certain life cycle stages. + + - Put life cycle in a random life cycle state. + - Verify that the rv_dm bus device is inaccessible from the CPU as well as external + JTAG if the life cycle state is not in TEST_UNLOCKED*, DEV or RMA. + - The bus access check is performed by randomly reading or writing a CSR inside the + RV_DM and checking whether the TL-UL bus errors out. + - The JTAG access check is performed by writing and then reading a register that is + accessible via the TAP/DMI inside the RV_DM. If the JTAG wires are gated, it is + expected that the RV_DM returns all-zero instead of the written value. + - X-ref'ed with `chip_tap_strap_sampling` + ''' + stage: V2 + tests: ["chip_rv_dm_lc_disabled"] + } + + // RV_TIMER (pre-verified IP) integration tests: + { + name: chip_sw_timer + desc: '''Verify the timeout interrupt assertion. + + - Configure the RV_TIMER to generate interrupt after a set timeout. + - Issue a WFI to wait for the interrupt to trigger. + - Service the interrupt when it triggers; verify that it came from rv_timer. + - Verify that the interrupt triggered only after the timeout elapsed. + ''' + stage: V2 + tests: ["chip_sw_rv_timer_irq"] + } + + // AON_TIMER (pre-verified IP) integration tests: + { + name: chip_sw_aon_timer_wakeup_irq + desc: '''Verify the AON timer wake up interrupt in normal operating state. + + - Program the PLIC to let the AON timer wake up interrupt the CPU. + - Program the AON timer to generate the wake up timeout interrupt after some time. + - Issue a WFI to wait for the interrupt to trigger. + - Service the interrupt when it triggers; verify that it came from AON timer. + - Verify that the interrupt triggered only after the timeout elapsed. + ''' + stage: V2 + tests: ["chip_sw_aon_timer_irq"] + } + { + name: chip_sw_aon_timer_sleep_wakeup + desc: '''Verify that AON timer can wake up the chip from a deep sleep state. + + - Read the reset cause register in rstmgr to confirm that the SW is in the POR reset + phase. + - Program the pwrmgr to go to deep sleep state (clocks off, power off). + - Program the AON timer to wake up the chip in a reasonable amount of time. + - Have the CPU issue WFI to signal the pwrmgr to go into sleep state. + - Verify via assertion checks, the wake up request occurs after the timeout has elapsed. + - After reset followed by AON timer wake up, read the reset cause register to confirm + the AON timer wake up phase. + - After the test sequence is complete, read the wake up threshold register - it should + not be reset. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_smoketest"] + } + { + name: chip_sw_aon_timer_wdog_bark_irq + desc: '''Verify the watchdog bark reception in normal state. + + - Program the PLIC to let the wdog bark signal interrupt the CPU. + - Program the AON timer wdog to 'bark' after some time and enable the bark interrupt. + - Service the bark interrupt upon reception. + ''' + stage: V2 + tests: ["chip_sw_aon_timer_irq"] + } + { + name: chip_sw_aon_timer_wdog_lc_escalate + desc: '''Verify that the LC escalation signal disables the AON timer wdog. + + - Program the AON timer wdog to 'bark' after some time and enable the bark interrupt. + - Start the escalation process and fail the test in the interrupt handler in case the + bark interrupt is fired. + - Program the alert handler to escalate on alerts upto phase 2 (i.e. reset) but the + phase 1 (i.e. wipe secrets) should occur and last during the time the wdog is + programed to bark and bite. + - Trigger an alert to cause an escalation condition before the bark signal asserts. + - After the reset ensure that the reset cause was due to the escalation to prove that + the wdog was disabled. + ''' + stage: V2 + tests: ["chip_sw_aon_timer_wdog_lc_escalate"] + } + { + name: chip_sw_aon_timer_wdog_bite_reset + desc: '''Verify the watchdog bite causing reset in the normal state. + + - Read the reset cause register in rstmgr to confirm that the SW is in the POR reset + phase. + - Program the AON timer wdog to 'bark' after some time. + - Let the bark escalate to bite, which should result in a reset request. + - After reset, read the reset cause register in rstmgr to confirm that the SW is now in + the wdog reset phase. + ''' + stage: V2 + tests: ["chip_sw_aon_timer_wdog_bite_reset"] + } + { + name: chip_sw_aon_timer_sleep_wdog_bite_reset + desc: '''Verify the watchdog bite causing reset in sleep state. + + - Repeat the steps in chip_aon_timer_wdog_bite_reset test, but with following changes: + - Program the pwrmgr to go to deep sleep state (clocks off, power off). + - Issue a WFI after programming the wdog, so that the reset request due to bite occurs + during deep sleep state. + - After reset, read the reset cause register in rstmgr to confirm that the SW is now in + the wdog reset phase. + ''' + stage: V2 + tests: ["chip_sw_aon_timer_wdog_bite_reset"] + } + { + name: chip_sw_aon_timer_sleep_wdog_sleep_pause + desc: '''Verify that the wdog can be paused in sleep state. + + - Repeat the steps in chip_aon_timer_sleep_wakeup test, but with following changes: + - Program the wdog to 'bite' a little sooner than the AON timer wake up. + - Also, program the wdog to pause during sleep. + - Issue a WFI after programming the wdog, so that the reset request occurs during deep + sleep state. + - After reset followed by AON timer wake up, read the reset cause register to confirm + that the AON timer woke up the chip, not the wdog reset. + - Un-pause the wdog and service the bark interrupt. + ''' + stage: V2 + tests: ["chip_sw_aon_timer_sleep_wdog_sleep_pause"] + } + + // PLIC integration tests: + { + name: chip_sw_plic_all_irqs + desc: '''Verify all interrupts from all peripherals aggregated at the PLIC. + + The automated SW test enables all interrupts at the PLIC to interrupt the core. It uses + the `intr_test` CSR in each peripheral to mock assert an interrupt, looping through all + available interrupts in that peripheral. The ISR verifies that the right interrupt + occurred. This is used as a catch-all interrupt test for all peripheral integration + testing within which functionally asserting an interrupt is hard to achieve or not of + high value. + ''' + stage: V2 + tests: ["chip_plic_all_irqs"] + } + { + name: chip_sw_plic_sw_irq + desc: '''Verify the SW interrupt to the CPU. + + Enable all peripheral interrupts at PLIC. Enable all types of interrupt at the CPU core. + Write to the MSIP CSR to generate a SW interrupt to the CPU. Verify that the only + interrupt that is seen is the SW interrupt. + ''' + stage: V2 + tests: ["chip_sw_plic_sw_irq"] + } + { + name: chip_sw_plic_alerts + desc: '''Verify alerts from PLIC due to both, TL intg and reg WE onehot check faults. + + - Since PLIC is not pre-verified in a DV environment, we need to ensure these are tested + separately. + ''' + stage: V3 + tests: ["chip_sw_all_escalation_resets"] + } + + // CLKMGR tests: + { + name: chip_sw_clkmgr_idle_trans + desc: '''Verify the ability to turn off the transactional clock via SW. + + Ensure that the clock to transactional units will be turned off after any activity + completes in the transactional IP. Verify it is off via spinwait in hints_status CSR. + Verify that turning off this clock does not affect the other derived clocks. + ''' + stage: V2 + tests: ["chip_sw_aes_idle", + "chip_sw_hmac_enc_idle", + "chip_sw_kmac_idle", + "chip_sw_otbn_randomness"] + } + { + name: chip_sw_clkmgr_off_trans + desc: '''Verify the turned off transactional units. + + Verify CSR accesses do not complete in units that are off. Using the watchdog timers, + turn off a transactional unit's clock, issue a CSR access to that unit, verify a + watchdog event results, and verify the rstmgr crash dump info records the CSR address. + + A stretch goal is to check the PC corresponds to the code performing the CSR access + (stretch since it could be difficult to maintain this check). + ''' + stage: V2 + tests: ["chip_sw_clkmgr_off_aes_trans", + "chip_sw_clkmgr_off_hmac_trans", + "chip_sw_clkmgr_off_kmac_trans", + "chip_sw_clkmgr_off_otbn_trans"] + } + { + name: chip_sw_clkmgr_off_peri + desc: '''Verify the ability to turn off the peripheral clock via SW. + + Verify CSR accesses do not complete in peripherals that are off. Using the watchdog + timers, turn off a peripheral's clock, issue a CSR access to that peripheral, verify a + watchdog event results, and verify the rstmgr crash dump info records the CSR address. + ''' + stage: V2 + tests: ["chip_sw_clkmgr_off_peri"] + } + { + name: chip_sw_clkmgr_div + desc: '''Verify clk division logic is working correctly. + + The IP level checks the divided clocks via SVA, and these are also bound at chip level. + Connectivity tests check peripherals are connected to the clock they expect. + Use the clkmgr count measurement feature to verify clock division. + ''' + stage: V2 + tests: ["chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0", + "chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0", + "chip_sw_clkmgr_external_clk_src_for_sw_fast_dev", + "chip_sw_clkmgr_external_clk_src_for_sw_slow_dev", + "chip_sw_clkmgr_external_clk_src_for_sw_fast_rma", + "chip_sw_clkmgr_external_clk_src_for_sw_slow_rma", + "chip_sw_clkmgr_external_clk_src_for_lc"] + } + { + name: chip_sw_clkmgr_external_clk_src_for_lc + desc: '''Verify the clkmgr requests ext clk src during certain LC states. + + On POR lc asserts lc_clk_byp_req on some LC states, and de-asserts + it when lc_program completes. This also triggers divided clocks to step down. It may be + best to verify this via SVA, unless we implement clock cycle counters. + ''' + stage: V2 + tests: ["chip_sw_clkmgr_external_clk_src_for_lc"] + } + { + name: chip_sw_clkmgr_external_clk_src_for_sw + desc: '''Verify SW causes the clkmgr requests ext clk src during certain LC states. + + In RMA and TEST_UNLOCKED lc states the external clock is enabled in response to + `extclk_ctrl.sel` CSR writes. In addition `extclk_ctrl.hi_speed_sel` CSR causes the + divided clocks to step down. Verify this via SVA bound to clkmgr, and clock cycle + counters. + + Disable external clock source and verify the AST reliably falls back to the internal + clock. Ensure the chip operates normally. + X-ref with chip_sw_uart_tx_rx_alt_clk_freq, which needs to deal with this as well. + ''' + stage: V2 + tests: ["chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0", + "chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0", + "chip_sw_clkmgr_external_clk_src_for_sw_fast_dev", + "chip_sw_clkmgr_external_clk_src_for_sw_slow_dev", + "chip_sw_clkmgr_external_clk_src_for_sw_fast_rma", + "chip_sw_clkmgr_external_clk_src_for_sw_slow_rma"] + } + { + name: chip_sw_clkmgr_jitter + desc: '''Verify the clock jitter functionality. + + Enable clock jitter setting the clkmgr `jitter_enable` CSR high. This causes the + jitter_o clkmgr output to toggle. Verify this output is connected to AST's + clk_src_sys_jen_i input using formal. + + X-ref with various specific jitter enable tests. + ''' + stage: V2 + tests: ["chip_sw_clkmgr_jitter", + "chip_sw_otbn_ecdsa_op_irq_jitter_en", + "chip_sw_aes_enc_jitter_en", + "chip_sw_hmac_enc_jitter_en", + "chip_sw_keymgr_dpe_key_derivation_jitter_en", + "chip_sw_kmac_mode_kmac_jitter_en", + "chip_sw_sram_ctrl_scrambled_access_jitter_en", + "chip_sw_edn_entropy_reqs_jitter"] + } + { + name: chip_sw_clkmgr_extended_range + desc: '''Verify that the system can run at a reduced, calibrated clock frequency. + + This test should check that the system can run at a reduced, calibrated clock frequency + (70MHz) with jitter enabled (which can lower the frequency down to ~55 MHz + momentarily). This option is intended as a fall-back in case there are issues running + the system with at 100MHz (calibrated). + + This testpoint can be covered by extending the DV environment to support the extended + range clock option via a flag, and running several existing chip-level tests with that + option. + + Test the following functionalities with reduced clock: + + - AES, HMAC, KMAC and OTBN operations + - Keymgr key derivation + - Scramble-enabled access from the main SRAM + - Csrng edn concurrency + ''' + stage: V2 + tests: ["chip_sw_clkmgr_jitter_reduced_freq", + "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq", + "chip_sw_aes_enc_jitter_en_reduced_freq", + "chip_sw_hmac_enc_jitter_en_reduced_freq", + "chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq", + "chip_sw_kmac_mode_kmac_jitter_en_reduced_freq", + "chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq", + "chip_sw_csrng_edn_concurrency_reduced_freq"] + } + { + name: chip_sw_clkmgr_deep_sleep_frequency + desc: '''Verify the frequency measurement through deep sleep. + + Enable clock cycle counts. Put the chip in deep sleep. Upon wakeup reset the + clock measurements should be off, but the recoverable fault status should not + be cleared. + ''' + stage: V2 + tests: ["chip_sw_ast_clk_outputs"] + } + { + name: chip_sw_clkmgr_sleep_frequency + desc: '''Verify the frequency measurement through shallow sleep. + + Enable clock cycle counts. Put the chip in shallow sleep with pwrmgr's CONTROL CSR + keeping some clocks disabled. Upon wakeup the clock measurements should be on, and the + recoverable fault status should show no errors for the disabled clocks. + ''' + stage: V2 + tests: ["chip_sw_clkmgr_sleep_frequency"] + } + { + name: chip_sw_clkmgr_reset_frequency + desc: '''Verify the frequency measurement through reset. + + Enable clock cycle counts, configured to cause errors. Trigger a chip reset via SW. + After reset the clock measurements should be off and the recoverable fault status + should be cleared. + ''' + stage: V2 + tests: ["chip_sw_clkmgr_reset_frequency"] + } + { + name: chip_sw_clkmgr_escalation_reset + desc: '''Verify the clock manager resets to a clean state after an escalation reset. + + Trigger an internal fatal fault for the regfile onehot checker and let it escalate to + reset. Upon alert escalation reset, the internal status should be clear and clkmgr + should not attempt to send out more alerts. + ''' + stage: V2 + tests: ["chip_sw_all_escalation_resets"] + } + + // PWRMGR tests: + { + name: chip_sw_pwrmgr_external_full_reset + desc: '''Verify the cold boot sequence by wiggling of chip's `POR_N`. + + This ensures that both FSMs are properly reset on the POR signal. The check is that + the processor ends up running. Also verify, the rstmgr recorded POR in `reset_info` CSR + by checking retention SRAM for reset_reason. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_full_aon_reset"] + } + { + name: chip_sw_pwrmgr_random_sleep_all_wake_ups + desc: '''Verify that the chip can go into random low power states and be woken up by ALL wake + up sources. + + This verifies ALL wake up sources. This also verifies that the pwrmgr sequencing is + working correctly as expected. X-ref'ed with all individual IP tests. For each wakeup + source clear and enable `wake_info` CSR, enable the wakeup from that source with the + `wakeup_en` CSR, bring the chip to both normal and low power sleep, optionally + disabling the source's clock, have the source issue a wakeup event and verify + `wake_info` indicates the expected wakeup. + + Each test should perform a minimum of 2 low power transitions to ensure there are no + state dependent corner cases with wakeup interactions. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_random_sleep_all_wake_ups"] + } + { + name: chip_sw_pwrmgr_normal_sleep_all_wake_ups + desc: '''Verify that the chip can go into normal sleep state and be woken up by ALL wake up + sources. + + This verifies ALL wake up sources. This also verifies that the pwrmgr sequencing is + working correctly as expected. X-ref'ed with all individual IP tests. For each wakeup + source clear and enable `wake_info` CSR, enable the wakeup from that source with the + `wakeup_en` CSR, bring the chip to normal sleep, optionally disabling the source's + clock, have the source issue a wakeup event and verify `wake_info` indicates the + expected wakeup. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_normal_sleep_all_wake_ups"] + } + { + name: chip_sw_pwrmgr_sleep_all_reset_reqs + desc: '''Verify that the chip can go into normal sleep state and be reset by ALL reset req + sources. + + This verifies ALL reset sources. This also verifies that the pwrmgr sequencing is + working correctly as expected. X-ref'ed with all individual IP tests. For each reset + source, enable the source and bring the chip to low power, issue a reset, and verify the + rstmgr's `reset_info` indicated the expected reset by checking retention SRAM for + reset_reason. + ''' + stage: V2 + tests: ["chip_sw_aon_timer_wdog_bite_reset"] + } + { + name: chip_sw_pwrmgr_deep_sleep_all_wake_ups + desc: '''Verify that the chip can go into deep sleep state and be woken up by ALL wake up + sources. + + This verifies ALL wake up sources. This also verifies that the pwrmgr sequencing is + working correctly as expected. X-ref'ed with all individual IP tests. Similar to + chip_pwrmgr_sleep_all_wake_ups, except `control.main_pd_n` is set to 0. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_deep_sleep_all_wake_ups"] + } + { + name: chip_sw_pwrmgr_deep_sleep_all_reset_reqs + desc: '''Verify that the chip can go into deep sleep state and be reset up by ALL reset req + sources. + + This verifies ALL reset sources. + - 7 resets are generated randomly with deep sleeps + - POR (HW PAD) reset, SW POR, wdog timer reset, esc rst, SW req + - esc reset is followd by normal mode because it does not work with sleep mode + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_deep_sleep_all_reset_reqs"] + } + { + name: chip_sw_pwrmgr_normal_sleep_all_reset_reqs + desc: '''Verify that the chip can go into normal sleep state and be reset up by ALL reset req + sources. + + This verifies ALL reset sources. + - 7 resets are generated randomly with normal sleeps + - POR (HW PAD) reset, SW POR, wdog timer reset, esc rst, SW req + - esc reset is followed by normal mode and cleared by reset because it does not work + with sleep mode + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_normal_sleep_all_reset_reqs"] + } + { + name: chip_sw_pwrmgr_wdog_reset + desc: '''Verify that the chip can be reset by watchdog timer reset source. + + This verifies watchdog timer reset source. This also verifies that the pwrmgr sequencing + is working correctly as expected. X-ref'ed with all individual IP tests. Similar to + chip_pwrmgr_sleep_all_reset_reqs, except the chip is not put in low power mode. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_wdog_reset"] + } + { + name: chip_sw_pwrmgr_aon_power_glitch_reset + desc: '''Verify the cold boot sequence through an AON power glitch. + + + Pulsing the AST vcaon_supp_i input causes an AON power glitch which becomes a POR. + This ensures that both FSMs are properly reset on the POR signal. The check is that + the processor ends up running. Also verify, the rstmgr recorded POR in `reset_info` CSR + by checking retention SRAM for reset_reason. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_full_aon_reset"] + } + { + name: chip_sw_pwrmgr_main_power_glitch_reset + desc: '''Verify the effect of a glitch in main power rail. + + The vcmain_supp_i AST input is forced to drop once the test is running. This triggers + a MainPwr reset request, which is checked by reading retention SRAM's reset_reason to + see that the reset_info CSR's POR bit is not set when the test restarts. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_main_power_glitch_reset"] + } + { + name: chip_sw_pwrmgr_random_sleep_power_glitch_reset + desc: '''Verify the effect of a glitch in main power rail in random sleep states. + + The vcmain_supp_i AST input is forced to drop right after putting the chip in a random + sleep state. This triggers a MainPwr reset request, which is checked by reading + retention SRAM's reset_reason to show that the reset_info CSR's POR bit is not set when + the test restarts. + + Note: the glitch has to be sent in a very narrow window: + - If sent too early the chip won't have started to process deep sleep. + - If too late the hardware won't monitor main power okay so the glitch will have no + effect, and the test will timeout. + + Each test should perform a minimum of 2 low power transitions to ensure there are no + state dependent corner cases with power glitch handling. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_random_sleep_power_glitch_reset"] + } + { + name: chip_sw_pwrmgr_deep_sleep_power_glitch_reset + desc: '''Verify the effect of a glitch in main power rail in deep sleep. + + The vcmain_supp_i AST input is forced to drop right after putting the chip in deep + sleep. This triggers a MainPwr reset request, which is checked by reading retention + SRAM's reset_reason to show that the reset_info CSR's POR bit is not set when the test + restarts. + + Note: the glitch has to be sent in a very narrow window: + - If sent too early the chip won't have started to process deep sleep. + - If too late the hardware won't monitor main power okay so the glitch will have no + effect, and the test will timeout. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_deep_sleep_power_glitch_reset"] + } + { + name: chip_sw_pwrmgr_sleep_power_glitch_reset + desc: '''Verify the effect of a glitch in main power rail in shallow sleep. + + The vcmain_supp_i AST input is forced to drop after putting the chip in shallow sleep. + This triggers a MainPwr reset request, which is checked by reading the retention SRAM's + reset_reason shows that the reset_info CSR's POR bit is not set when the + test restarts. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_sleep_power_glitch_reset"] + } + { + name: chip_sw_pwrmgr_random_sleep_all_reset_reqs + desc: '''Verify that this chip can be reset by All available reset sources. + + - 12 resets are generated randomly with normal/deep sleeps + - POR (HW PAD) reset, SW POR, wdog timer reset, esc rst, SW req + - esc reset is followd by normal mode because it does not work with sleep mode + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_random_sleep_all_reset_reqs"] + } + // { + // name: chip_sw_pwrmgr_b2b_sleep_reset_req + // desc: '''Verify that the pwrmgr sequences sleep_req and reset req coming in almost at the same + // time, one after the other. Use POR_N PAD to trigger reset. + // ''' + // stage: V2 + // tests: ["chip_sw_pwrmgr_b2b_sleep_reset_req"] + // } + { + name: chip_sw_pwrmgr_sleep_disabled + desc: '''Verify that the chip does not go to sleep on WFI when low power hint is 0. + + This calls WFI with low_power_hint disabled and pwrmgr interrupts enabled, + and fails if the pwrmgr ISR is called. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_sleep_disabled"] + } + { + name: chip_sw_pwrmgr_escalation_reset + desc: '''Verify the power manager resets to a clean state after an escalation reset. + + Trigger an internal fatal fault for the regfile onehot checker and let it escalate to + reset. Upon alert escalation reset, the internal status should be clear and pwrmgr + should not attempt to send out more alerts. + ''' + stage: V2 + tests: ["chip_sw_all_escalation_resets"] + } + + // RSTMGR tests: + { + name: chip_sw_rstmgr_non_sys_reset_info + desc: '''Verify the `reset_info` CSR register for lc or higher resets. + + Generate the 5 types of reset at `lc` level or higher, and check the retention SRAM's + reset_reason to show that `reset_info` CSR is as expected. This and other rstmgr + testpoints that require different resets cross-reference the individual IP tests that + generate those resets, and this testpoint merely adds reset checks in them. Those IP + blocks are `pwrmgr`, `alert_handler` and `aon_timer`. + + This should also check the reset's destination IP to make sure some reset side-effect + is present. Setting some `intr_enable` CSR bit when the test starts and checking it + after reset seems suitable. The `spi_host` IPs receive multiple resets so they will + need special consideration. + TODO(maturana) Add specific tests once they are developed. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_smoketest"] + } + { + name: chip_sw_rstmgr_sys_reset_info + desc: '''Verify the `reset_info` CSR register for sys reset. + + Generate reset triggered by `rv_dm`, which results in a sys level reset, and check the + retention SRAM's reset_reason to show that the `reset_info` CSR is as expected. This + testpoint cross-reference the `rv_dm` tests that generate this reset, and this + testpoint merely adds reset checks in them. + + This should also check the reset's destination IP to make sure some reset side-effect + is present. Setting some `intr_enable` CSR bit when the test starts and checking it + after reset seems suitable. The `spi_host` IPs receive multiple resets so they will + need special consideration. + + X-ref with chip_rv_dm_ndm_reset_req. + + ''' + stage: V2 + tests: ["chip_rv_dm_ndm_reset_req"] + } + { + name: chip_sw_rstmgr_cpu_info + desc: '''Verify the expected values from the `cpu_info` CSR on reset. + + For some software induced resets we can predict the expected contents of `cpu_info`; + reads of writes to unmapped addresses for example. Generate these resets and verify + the `cpu_info` register contents when reset is handled. + Refer to `chip_*sys_rstmgr_reset_info`. + ''' + stage: V2 + tests: ["chip_sw_rstmgr_cpu_info"] + } + { + name: chip_sw_rstmgr_sw_req_reset + desc: '''Verify software requested device reset. + + Generate a reset request by directly writing the `reset_req` CSR. + The reset created should be identical to those caused by hardware sources. + After reset, the retention SRAM's reset_reason should show that the `reset_info` CSR + reflects that a software request was the reset cause. + ''' + stage: V2 + tests: ["chip_sw_rstmgr_sw_req"] + } + { + name: chip_sw_rstmgr_alert_info + desc: '''Verify the expected values from the `alert_info` CSR on reset. + + Various alerts can be created, for example, timeouts, and integrity errors, and at + least part of the `alert_info` CSR can be predicted. To cause some of these to + cause a reset, mask the relevant processor interrupts. Trigger these resets and + verify the `alert_info` register contents when reset is handled. + Refer to `chip_*sys_rstmgr_reset_info`. + ''' + stage: V2 + tests: ["chip_sw_rstmgr_alert_info"] + } + { + name: chip_sw_rstmgr_sw_rst + desc: '''Verify `sw_rst_ctrl_n` CSR resets individual peripherals. + + - Pick a rw type CSR in each peripheral and program arbitrary value + that does not cause any adverse side-effects. + - Pulse the reset to the peripheral via software. + - Read the resister after reset and verify it returns the reset value. + - Repeat these steps for each of these software resettable peripherals: + `spi_device`, `spi_host0`, `i2c0`. + + Notice the two `spi_host` IPs receive two different resets, `spi_host*`. + ''' + stage: V2 + tests: ["chip_sw_rstmgr_sw_rst"] + } + { + name: chip_sw_rstmgr_escalation_reset + desc: '''Verify the reset manager resets to a clean state after an escalation reset. + + Trigger an internal fatal fault for the regfile onehot checker and let it escalate to + reset. Upon alert escalation reset, the internal status should be clear and rstmgr + should not attempt to send out more alerts. + ''' + stage: V2 + tests: ["chip_sw_all_escalation_resets"] + } + + // ALERT_HANDLER (pre-verified IP) integration tests: + { + name: chip_sw_alert_handler_alerts + desc: '''Verify all alerts coming into the alert_handler. + + An automated SW test, which does the following (applies to all alerts in all IPs): + - Program the alert_test CSR in each block to trigger each alert one by one. + - Ensure that all alerts are properly connected to the alert handler and cause the + escalation paths to trigger. + ''' + stage: V2 + tests: ["chip_sw_alert_test"] + } + { + name: chip_sw_alert_handler_escalations + desc: '''Verify all alert escalation paths. + + Verify all escalation paths triggered by an alert. + - Verify the first escalation results in NMI interrupt serviced by the CPU. + - Verify the second results in device being put in scrap state, via the LC JTAG TAP. + - Verify the third results in chip reset. + - Ensure that all escalation handshakes complete without errors. + ''' + stage: V2 + tests: ["chip_sw_alert_handler_escalation"] + } + { + name: chip_sw_all_escalation_resets + desc: '''Verify escalation from all unit integrity errors. + + Inject integrity errors in any unit that has a one-hot checker for CSR register + writes, and verify escalation is triggered. Allow escalation to go through reset. + Use the rstmgr alert info and the unit's fault CSRs to check the alert cause is right. + Each run of the test randomly chooses some one-hot checker for the error to be injected. + Keep state across resets in flash to check the expected interrupts and the right number + of resets occur. + - Verify the integrity error results in a regular interrupt. + - Verify the first escalation results in NMI serviced by the CPU. + - Verify the alert id in both these interrupts. + - Verify the unit's fault CSR correctly captured the fault kind. + - Verify any timer interrupts are disabled by escalation. + - Verify after the escalation reset all faults are cleared, and that the alert + info captured the correct alert. + - Check that no additional resets occur. + ''' + stage: V2 + tests: ["chip_sw_all_escalation_resets"] + } + { + name: chip_sw_alert_handler_irqs + desc: '''Verify all classes of alert handler interrupts to the CPU. + + X-ref'ed with the automated PLIC test. + ''' + stage: V2 + tests: ["chip_plic_all_irqs"] + } + { + name: chip_sw_alert_handler_entropy + desc: '''Verify the alert handler entropy input to ensure pseudo-random ping timer. + + - Force `alert_handler_ping_timer` input signal `wait_cyc_mask_i` to `8'h07` to + shorten the simulation time. + - Verify that the alert_handler can request EDN to provide entropy. + - Ensure that the alert ping handshake to all alert sources and escalation receivers + complete without errors. + ''' + stage: V2 + tests: ["chip_sw_alert_handler_entropy"] + } + { + name: chip_sw_alert_handler_crashdump + desc: '''Verify the alert handler crashdump signal. + + When the chip resets due to alert escalating to cause the chip to reset, verify the + reset cause to verify the alert crashdump. + + Xref'ed with chip_sw_rstmgr_alert_info. + ''' + stage: V2 + tests: ["chip_sw_rstmgr_alert_info"] + } + { + name: chip_sw_alert_handler_ping_timeout + desc: '''Verify the alert senders' ping timeout. + + Set alert_handler's ping timeout cycle to 2 and enable alert_senders. Verify that + alert_handler detects the ping timeout and reflects it on the `loc_alert_cause` + register. + ''' + stage: V2 + tests: ["chip_sw_alert_handler_ping_timeout"] + } + { + name: chip_sw_alert_handler_lpg_sleep_mode_alerts + desc: '''Verify alert_handler can preserve alerts during low_power mode. + + - Trigger fatal alerts for all IPs but configure alert_handler so it won't trigger + reset. + - Randomly enter normal or deep sleep mode. + - Wait random cycles then wake up from the sleep mode. + - After wake up from normal sleep mode, clear all alert cause registers and check that + all alerts are still firing after waking up. + - Repeat the previous steps for random number of iterations. + - Fatal alerts from flash_ctrl, otp_ctrl, sram_ctrl, and lc_ctrl are omitted because + they disable the CPU and require a reset for the system to continue to function. + ''' + stage: V2 + tests: ["chip_sw_alert_handler_lpg_sleep_mode_alerts"] + } + { + name: chip_sw_alert_handler_lpg_sleep_mode_pings + desc: '''Verify alert_handler's ping mechanism works correctly during sleep and wake up. + + There are two scenarios to check: + - Configure alert_handler's ping timeout register to a reasonble value that won't cause + ping timeout in normal cases. + Then randomly enter and exit normal or deep sleep modes. + Check that no local alerts triggered in alert_handler. + This scenario ensures that ping mechanism won't send out spurious failure. + - Configure alert_handler's ping timeout register to a small value that will always + causes ping timeout. + Then randomly enter and exit normal or deep sleep modes. + Clear local alert cause register and check that alert ping timeout continue to fire + after wake up. + This scenario ensures the ping mechanism will continue to send out pings after waking + up from sleep modes. + ''' + stage: V2 + tests: ["chip_sw_alert_handler_lpg_sleep_mode_pings"] + } + { + name: chip_sw_alert_handler_lpg_clock_off + desc: '''Verify alert_handler's works correctly when sender clock is turned off. + + - Configure clkmgr to randomly turn off one of the IP's clock and check alert_handler + won't trigger a ping timeout error on that block. + ''' + stage: V2 + tests: ["chip_sw_alert_handler_lpg_clkoff"] + } + { + name: chip_sw_alert_handler_lpg_reset_toggle + desc: '''Verify alert_handler's works correctly when sender reset is toggled. + + - Configure rstmgr to randomly toggle one IP block's SW reset and check alert_handler + won't trigger a ping timeout error on that block. + ''' + stage: V2 + tests: ["chip_sw_alert_handler_lpg_reset_toggle"] + } + { + name: chip_sw_alert_handler_reverse_ping_in_deep_sleep + desc: '''Verify escalation reverse ping timer disabled in sleep mode. + + Check that escalation receivers located inside always-on blocks do not auto-escalate + due to the reverse ping feature while the system is in deep sleep. + + ## Reverse ping timeout calculation + + The reverse ping timeout calculation is done using the following formula available in + `prim_esc_receiver`: + + ``` + 4 * N_ESC_SEV * (2 * 2 * 2^PING_CNT_DW) + ``` + + `pwrmgr` is the only block consuming the `N_ESC_SEV` and `PING_CNT_DW` compile time + parameters: + + ``` + alert_handler_reg_pkg::N_ESC_SEV = 4 + alert_handler_reg_pkg::PING_CNT_DW = 16 + ``` + + The alert escalation responder inside `pwrmgr` is connected to the `io_div4` clock, + yielding a target 24MHz frequency. The result expected timeout based on the above + parameters is thus: + + ``` + reverse_ping_timeout = 0.175s = (4 * 4 ( 2 * 2 * 2^16)) / 24e6 + ``` + + ## Procedure + + - On POR reset: + - Enable all alerts assigning them to ClassA. + - Enable all local alerts and assign to ClassB. + - Set escalation configuration to trigger before test wake up time. + - Set ping timeout to a time less than wake up time. + - Lock alert configuration and enable ping mechanism. + - Wait for polling counters to cycle through by busy polling on Ibex for + `reverse_ping_timeout >> 2` usec. + - Configure AON to wake up device at a later time, making sure it is greater than the + `reverse_ping_timeout` calculated in the previous section. + - Enter deep sleep. + - On wake up from sleep: + - Ensure reset status is low power exit. A `kDifRstmgrResetInfoEscalation` signals + that there was a local escalation and should result in test failure. + - Disable AON timer. + - Check there are no flagged local alerts. + ''' + stage: V2 + tests: ["chip_sw_alert_handler_reverse_ping_in_deep_sleep"] + } + + // LC_CTRL (pre-verified IP) integration tests: + { + name: chip_sw_lc_ctrl_alert_handler_escalation + desc: '''Verify that the escalation signals from the alert handler are connected to LC ctrl. + + - Trigger an alert to initiate the escalations. + - Check that the escalation signals are connected to the LC ctrl: + - First escalation has no effect on the LC ctrl. Read LC_STATE CSR to confirm + this is the case. + - Second escalation should cause the `lc_escalation_en` output to be asserted and for + the LC_STATE to transition to scrap state. Confirm by reading the LC_STATE CSR + - Verify that all decoded outputs except for escalate_en are + disabled. X-ref'ed with the respective IP tests that consume these signals. + + X-ref'ed with chip_sw_lc_ctrl_broadcast test, which verifies the connectivity of the LC + decoded outputs to other IPs. + X-ref'ed with alert_handler's escalation test. + ''' + stage: V2 + tests: ["chip_sw_alert_handler_escalation"] + } + { + name: chip_sw_lc_ctrl_jtag_access + desc: '''Verify enable to access LC ctrl via JTAG. + + Using the JTAG agent, write and read LC ctrl CSRs, verify the read value for + correctness. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_transition"] + } + { + name: chip_sw_lc_ctrl_otp_hw_cfg + desc: '''Verify the device_ID and ID_state CSRs. + + - Preload the hw_cfg partition in OTP ctrl with random data. + - Read the device ID and the ID state CSRs to verify their correctness. + - Reset the chip and repeat the first 2 steps to verify a different set of values. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_otp_hw_cfg"] + } + { + name: chip_sw_lc_ctrl_init + desc: '''Verify the LC ctrl initialization on power up. + + Verify that the chip powers up correctly on POR. + - The pwrmgr initiates a handshake with OTP ctrl and later, with LC ctrl in subsequent + FSM states. Ensure that the whole power up sequence does not hang. + - Verify with connectivity assertion checks, the handshake signals are connected. + - Ensure that no interrupts or alerts are triggered. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_transition"] + } + { + name: chip_sw_lc_ctrl_transitions + desc: '''Verify the LC ctrl can transit from one state to another valid state with the + correct tokens. + + - Preload OTP image with a LC state and required tokens to transfer to next state. + - Initiate an LC ctrl state transition via SW if CPU is enabled, or via JTAG interface + if CPU is disable. + - Ensure that the LC program request is received by the OTP ctrl. + - Verify the updated data output from OTP ctrl to LC ctrl is correct. + - Ensure that there is no background or otp_init error. + - Verify that the LC ctrl has transitioned to the programmed state after a reboot. + Re-randomize the lc_transition tokens and repeat the sequence above. + + X-ref'ed chip_sw_otp_ctrl_program. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_transition"] + } + { + name: chip_sw_lc_ctrl_kmac_req + desc: '''Verify the token requested from KMAC. + + - For conditional transition, the LC ctrl will send out a token request to KMAC. + - Verify that the KMAC returns a hashed token, which should match one of the + transition token CSRs. + + X-ref'ed with chip_kmac_lc_req. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_transition"] + } + { + name: chip_sw_lc_ctrl_key_div + desc: '''Verify the keymgr div output to keymgr. + + - Verify in different LC states, LC ctrl outputs the correct `key_div_o` to keymgr. + - Verify that the keymgr uses the given `key_div_o` value to compute the keys. + ''' + stage: V2 + tests: ["chip_sw_keymgr_dpe_key_derivation_prod"] + } + { + name: chip_sw_lc_ctrl_broadcast + desc: '''Verify broadcast signals from lc_ctrl. + + - Preload the LC partition in the otp_ctrl with the following states: RMA, DEV, + TEST_LOCKED[N] & SCRAP. + - Verify that the following broadcast signals are having the right effect in the + respective IPs that consume them: + - lc_dft_en_o: impacts pinmux, pwrmgr, otp_ctrl, AST + - lc_hw_debug_en_o: impacts pinmux, pwrmgr, sram_ctrl (main and ret) & the rv_dm + - lc_keymgr_en_o: impacts keymgr + - lc_clk_byp_req_o: impacts clkmgr (handshake with lc_clk_byp_ack_i) + - lc_check_byp_en_o: impacts otp_ctrl + - lc_creator_seed_sw_rw_en_o: impacts otp_ctrl + - lc_seed_hw_rd_en_o: impacts otp_ctrl + - These outputs are enabled per the + [life cycle architecture spec](doc/security/specs/device_life_cycle/README.md#architecture). + + X-ref'ed with the respective IP tests that consume these signals. + + Note that the following signals are already verified with connectivity tests and SVAs: + - lc_dft_en_o (AST connection) + - lc_cpu_en_o (rv_core_ibex) + - lc_escalate_en_o (multiple) + ''' + stage: V2 + tests: [ + "chip_prim_tl_access", // lc_dft_en_o: otp_ctrl + "chip_sw_rom_ctrl_integrity_check", // lc_dft_en_o, lc_hw_debug_en_o: pwrmgr + "chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0", // lc_hw_debug_en_o: clkmgr + "chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0", // lc_hw_debug_en_o: clkmgr + "chip_sw_clkmgr_external_clk_src_for_sw_fast_dev", // lc_hw_debug_en_o: clkmgr + "chip_sw_clkmgr_external_clk_src_for_sw_slow_dev", // lc_hw_debug_en_o: clkmgr + "chip_sw_clkmgr_external_clk_src_for_sw_fast_rma", // lc_hw_debug_en_o: clkmgr + "chip_sw_clkmgr_external_clk_src_for_sw_slow_rma", // lc_hw_debug_en_o: clkmgr + "chip_sw_sram_ctrl_execution_main", // lc_hw_debug_en_o: sram_ctrl main + "chip_rv_dm_lc_disabled" // lc_hw_debug_en_o: rv_dm + "chip_sw_keymgr_dpe_key_derivation", // lc_keymgr_en_o: keymgr + "chip_sw_clkmgr_external_clk_src_for_lc", // lc_clk_byp_req_o: clkmgr + "chip_sw_lc_ctrl_transition", // lc_check_byp_en_o: otp_ctrl + "chip_sw_otp_ctrl_lc_signals_test_unlocked0", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl + "chip_sw_otp_ctrl_lc_signals_dev", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl + "chip_sw_otp_ctrl_lc_signals_prod", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl + "chip_sw_otp_ctrl_lc_signals_rma", // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, lc_keymgr_en_i: otp_ctrl + ] + } + { + name: chip_sw_lc_ctrl_kmac_error + desc: ''' + Verify the effect of KMAC returning an error during the hash generation of LC tokens. + + - Follow the steps in `chip_sw_lc_ctrl_kmac_req` test. + - While the KMAC is actively computing the digest, glitch the KMAC app sparse FSM to + trigger a fault. + - Verify that KMAC returns an error signal to the LC controller. + - TBD + ''' + stage: V3 + tests: [] + } + + /////////////////////////////////////////////////////// + // Security Peripherals // + // AES, HMAC, KMAC, CSRNG, ENTROPY_SRC, KEYMGR, OTBN // + /////////////////////////////////////////////////////// + + // AES (pre-verified IP) integration tests: + { + name: chip_sw_aes_enc + desc: '''Verify the AES operation. + + Write a 32-byte key and a 16-byte plain text to the AES registers and trigger the AES + computation to start. Wait for the AES operation to complete by polling the status + register. Check the digest registers for correctness against the expected digest value. + ''' + stage: V2 + tests: ["chip_sw_aes_enc", + "chip_sw_aes_enc_jitter_en"] + } + { + name: chip_sw_aes_entropy + desc: '''Verify the AES entropy input used by the internal PRNGs. + + - Write the initial key share, IV and data in CSRs (known combinations). + - Configure the entropy_src to generate entropy in LFSR mode. + - Write the PRNG_RESEED bit to reseed the internal state of the PRNG. + - Poll the status idle bit to ensure reseed operation is complete. + - Trigger the AES operation to run and wait for it to complete. + - Check the digest against the expected value. + - Write the KEY_IV_DATA_IN_CLEAR and DATA_OUT_CLEAR trigger bits to 1 and wait for it to + complete by polling the status idle bit. + - Read back the data out CSRs - they should all read garbage values. + - Assertion check verifies that the IV are also garbage, i.e. different from the + originally written values. + ''' + stage: V2 + tests: ["chip_sw_aes_entropy"] + } + { + name: chip_sw_aes_idle + desc: '''Verify AES idle signaling to clkmgr. + + - Write the AES clk hint to 0 within clkmgr to indicate AES clk can be gated and + verify that the AES clk hint status within clkmgr reads 0 (AES is disabled). + - Write the AES clk hint to 1 within clkmgr to indicate AES clk can be enabled. + - Initiate an AES operation with a known key, plain text and digest, write AES clk + hint to 0 and verify that the AES clk hint status within clkmgr now reads 1 (AES + is enabled), before the AES operation is complete. + - After the AES operation is complete verify that the AES clk hint status within + clkmgr now reads 0 again (AES is disabled). + - Write the AES clk hint to 1, read and check the AES output for correctness. + ''' + stage: V2 + tests: ["chip_sw_aes_idle"] + } + { + name: chip_sw_aes_sideload + desc: '''Verify the AES sideload mechanism. + + - Configure the keymgr to generate an aes key. + - Configure the AES to use the sideloaded key. + - Load the plaintext into the AES. + - Trigger the AES encryption and wait for it to complete. + - Verify that the ciphertext is different from the plaintext. + - Load the ciphertext into the AES. + - Trigger the AES decryption and wait for it to complete. + - Verify that the output is equal to the plain text. + - Clear the key in the keymgr and decrypt the ciphertext again. + - Verify that output is not equal to the plain text. + ''' + stage: V2 + tests: ["chip_sw_keymgr_sideload_aes"] + } + { + name: chip_sw_aes_masking_off + desc: '''Verify the AES masking off feature for ES. + + - Perform known-answer test using CSRNG SW application interface. + - Verify CSRNG produces the deterministic seed leading to an all-zero output of the AES + masking PRNG. + - Configure EDN to perform a CSRNG instantiate followed by repeated generate and reseed + commands using the maximum amount of additional data and no entropy input in automatic + mode. + - Let CSRNG produce and forward to EDN the deterministic seed leading to an all-zero + output of the AES masking PRNG. + - Initialize AES and set the force_masks configuration bit. + - Configure an AES key of which the second share is zero. + - Trigger a reseed operation of the masking PRNG inside AES to load the deterministic + seed produced by CSRNG and distributed by EDN. + - Verify that the masking PRNG outputs an all-zero vector. + - Encrypt a message of multiple blocks using AES. + - Verify that the second share of the initial, intermediate and output state is zero. + - Verify that the second share of the SubBytes input and output is zero. + - Verify that the produced cipher text is correct. + ''' + stage: V2S + tests: ["chip_sw_aes_masking_off"] + } + + // HMAC (pre-verified IP) integration tests: + { + name: chip_sw_hmac_enc + desc: '''Verify HMAC operation. + + SW test verifies an HMAC operation with a known key, plain text and digest (pick one of + the NIST vectors). SW test verifies the digest against the pre-computed value. Verify + the HMAC done and FIFO empty interrupts as a part of this test. + ''' + stage: V2 + tests: ["chip_sw_hmac_enc", + "chip_sw_hmac_enc_jitter_en"] + } + { + name: chip_sw_hmac_idle + desc: '''Verify the HMAC clk idle signal to clkmgr. + + - Write the HMAC clk hint to 0 within clkmgr to indicate HMAC clk can be gated and + verify that the HMAC clk hint status within clkmgr reads 0 (HMAC is disabled). + - Write the HMAC clk hint to 1 within clkmgr to indicate HMAC clk can be enabled. + Verify that the HMAC clk hint status within clkmgr reads 1 (HMAC is enabled). + - Initiate an HMAC operation with a known key, plain text and digest. + Write HMAC clock hint to 0 and verify the HMAC clk hint status within clkmgr reads 1 + (HMAC is enabled), before the HMAC operation is complete. + - After the HMAC operation is complete, verify the digest for correctness. Verify that + the HMAC clk hint status within clkmgr now reads 0 again (HMAC is disabled). + - This process is repeated for two hmac operations needed to verify the resulting hmac + digest. + ''' + stage: V2 + tests: ["chip_sw_hmac_enc_idle"] + } + + // KMAC pre-verified IP) integration tests: + { + name: chip_sw_kmac_enc + desc: '''Verify the SHA3 operation. + + SW test verifies SHA3 operation with a known key, plain text and digest (pick one of + the NIST vectors). SW validates the reception of kmac done and fifo empty interrupts. + ''' + stage: V2 + tests: ["chip_sw_kmac_mode_cshake", "chip_sw_kmac_mode_kmac", + "chip_sw_kmac_mode_kmac_jitter_en"] + } + { + name: chip_sw_kmac_app_keymgr + desc: '''Verify the keymgr interface to KMAC. + + - Configure the keymgr to start sending known message data to the KMAC. + - Keymgr should transmit a sideloaded key to the KMAC as well. + - KMAC should finish hashing successfully (not visible to SW) and return digest to + keymgr. + - This digest is compared against the known digest value for correctness. + - Verify that the keymgr has received valid output from the KMAC. + + X-ref'ed with keymgr test. + ''' + stage: V2 + tests: ["chip_sw_keymgr_dpe_key_derivation"] + } + { + name: chip_sw_kmac_app_lc + desc: '''Verify the LC interface to KMAC. + + - Configure the LC_CTRL to start a token hash using KMAC interface. + - KMAC should finish hashing successfully (not visible to SW) and return digest to + LC_CTRL. + + X-ref'ed with LC_CTRL test/env. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_transition"] + } + { + name: chip_sw_kmac_app_rom + desc: '''Verify the ROM interface to KMAC. + + - Backdoor initialize ROM memory immediately out of reset. + - ROM will send message to the KMAC containing its memory contents, + - KMAC will hash and return the digest to the ROM. + - ROM will compare received digest against its first 8 logical memory lines for + correctness. + + X-ref'ed with ROM_CTRL test/env. + ''' + stage: V2 + tests: ["chip_sw_kmac_app_rom"] + } + { + name: chip_sw_kmac_entropy + desc: '''Verify the EDN interface to KMAC. + + Requires `EnMasking` parameter to be enabled. + SW randomly configures the KMAC in any hashing mode/strength, and enable EDN mode. + Randomly enable/disable the `entropy_refresh`. + Randomly configure `wait_timer` values (zero for disable, non-zero for timer expire). + - Program `wait_timer` to a small value. + Check if EDN timeout error occurs after issuing the hashing op. + - Adjust `wait_timer` greater than expected EDN latency (with correct `prescaler` + too). Then check if Digest is correct. + KMAC should send EDN request after `entropy_ready` is set. + KMAC also should send out another request to EDN when either: + - kmac hash counter hits the configured threshold (assuming it is non-zero) + - Hash count exceeds the threshold. + SW verifies that KMAC produces the correct digest value. + + TODO: This is pending security review discussion. It is unclear if this feature will be + implemented. + + X-ref'ed with EDN test/env. + ''' + stage: V2 + tests: ["chip_sw_kmac_entropy"] + } + { + name: chip_sw_kmac_idle + desc: '''Verify the KMAC idle signaling to clkmgr. + + - Write the KMAC clk hint to 0 within clkmgr to indicate KMAC clk can be gated and + verify that the KMAC clk hint status within clkmgr reads 0 (KMAC is disabled). + - Write the KMAC clk hint to 1 within clkmgr to indicate KMAC clk can be enabled. + Verify that the KMAC clk hint status within clkmgr reads 1 (KMAC is enabled). + - Initiate a KMAC operation with a known key, plain text and digest. + Write KMAC clock hint to 0 and verify the KMAC clk hint status within clkmgr reads 1 + (KMAC is enabled), before the KMAC operation is complete. + - After the KMAC operation is complete, verify the digest for correctness. Verify that + the KMAC clk hint status within clkmgr now reads 0 again (KMAC is disabled). + ''' + stage: V2 + tests: ["chip_sw_kmac_idle"] + } + + // ENTROPY_SRC (pre-verified IP) integration tests: + { + name: chip_sw_entropy_src_csrng + desc: '''Verify the transfer of entropy bits to CSRNG. + + Verify the entropy valid interrupt. + At the CSRNG, validate the reception of entropy req interrupt. + + - Disable edn0, edn1, and csrng, as these are enabled by the test ROM. + - Enable csrng and enable the entropy request interrupt. + - Issue csrng instantiate and reseed commands. Check that for each csrng command, + there is a corresponding entropy request interrupt. + - Generate output and ensure the data output is valid, and that csrng is not reporting + any errors. + - Issue instantiate and reseed commands from edn0 and edn1. Check that for each + command, there is a corresponding entropy request interrupt. + ''' + stage: V2 + tests: ["chip_sw_entropy_src_csrng"] + } + + // CSRNG (pre-verified IP) integration tests: + { + name: chip_sw_csrng_edn_cmd + desc: '''Verify incoming command interface from EDN. + + - Have each EDN instance issue an instantiate, reseed and generate command to CSRNG. + - On each command done, verify the reception of edn cmd req done interrupt. + - Run OTBN randomness test to test the output from EDN0 and EDN1. + - Check the data returned to EDN via connectivity assertion checks. + ''' + stage: V2 + tests: ["chip_sw_entropy_src_csrng"] + } + { + name: chip_sw_csrng_fuse_en_sw_app_read + desc: '''Verify the fuse input to CSRNG. + + - Issue an instantiate command to request entropy. + - Verify that SW can read the internal state values. + + Note that this test has been simplified to just test the test_fuse_enable path, + since the HW has been updated to always hardwire the EN_CSRNG_SW_APP_READ + chicken switch to True. The chicken switch itself has been removed from OTP. + ''' + stage: V2 + tests: ["chip_sw_csrng_fuse_en_sw_app_read_test"] + } + { + name: chip_sw_csrng_known_answer_tests + desc: '''Verify our ability to run known-answer tests in SW. + + - Configure the software instance with the expected seed (as per + the NIST-specified test for CTR_DRBG operation). Compare the + DRBG internal K and V state against the test vector expected + values. + - Perform generate operations as required by the test vector. + - Compare the results to test expectations. + ''' + stage: V2 + tests: ["chip_sw_csrng_kat_test"] + } + { + name: chip_sw_csrng_edn_error + desc: '''Verify the outcome of an error response generated by CSRNG when processing an EDN + request. + + - Inject a fault in CSRNG while it is processing a request from EDN so that it returns + an error response to EDN. + - TODO(#16516): How does EDN respond to the error? + ''' + stage: V3 + tests: [] + } + + // EDN (pre-verified IP) integration tests: + { + name: chip_sw_edn_entropy_reqs + desc: '''Verify the entropy requests from all peripherals. + + Verify that there are no misconnects between each peripheral requesting entropy. + TODO: system level scenario: have all entropy sources request entropy in the same test + one after to show boot to post boot load, cycling all entropy blocks off and on again. + Ensure there are no deadlocks and everything works as expected. + X'ref'ed with each IP test that requsts entropy from EDN. + ''' + stage: V2 + tests: ["chip_sw_edn_entropy_reqs", + "chip_sw_csrng_edn_concurrency"] + } + + // KEYMGR_DPE (pre-verified IP) integration tests: + { + name: chip_sw_keymgr_dpe_key_derivation + desc: '''Verify the keymgr advances to all states and generate identity / SW output. + + - In the SW test, write fixed value to OTP for root_key and write creator and owner + seeds in flash. And then roboot the chip. + - In the SV sequence, backdoor read Device ID and ROM digest through CSRs. + - For HardwareRevisionSecret, use the constant values in design. + - Configure the keymgr and advance to `CreatorRootKey` and `OwnerIntermediateKey`. + - Check keymgr internal keys after advance operations. + - Generate identity / SW output for the Sealing CDI. + - No need to test the Attestation CDI in chip-level as the only difference is to + use another set of CSR values, and the rest of inputs are the same as the Sealing + CDI. + - KMAC should finish hashing successfully (not visible to SW) and return digest to + keymgr. + - Read keymgr CSRs `SW_SHARE*` and verify the return values. + - Advance to `Disabled` and verify keymgr enters the state successfully. + + - For each operation, wait for the interrupt `op_done` to be triggered and check CSR + `op_status` is `DONE_SUCCESS`. + + - Note: there are 3 ways of calculating the expected digest for comparison. Any of them + is acceptable. + - Use SW to calculate that, and it will also exercise the Ibex. + - SW sends all the keys through CSRs to KMAC to generate the degist data. + - DV calls C functions to generate and backdoor load to a specific memory location + for SW. (Adpot this approach.) + + X-ref'ed with kmac test. + ''' + stage: V2 + tests: ["chip_sw_keymgr_dpe_key_derivation", "chip_sw_keymgr_dpe_key_derivation_jitter_en"] + } + { + name: chip_sw_keymgr_sideload_kmac + desc: '''Verify the keymgr sideload interface to KMAC. + + - Configure the keymgr and advance to the `OwnerIntKey` state. + - Request keymgr to generate hw key for KMAC sideload key slot. + - Request KMAC operation with sideload key configuration. + - Verify the digest for correctness (should match the DV-side result). + - Clear keymer's KMAC sideload key slot. + - Request KMAC operation with sideload key configuration. + - Verify the digest value has changed. + - Request keymgr to derive the same key for the KMAC sideload key slot. + - Request KMAC operation with sideload key configuration. + - Verify the digest for correctness (should match the DV-side result again). + + X-ref'ed with chip_kmac_app_keymgr test. + ''' + stage: V2 + tests: ["chip_sw_keymgr_sideload_kmac"] + } + { + name: chip_sw_keymgr_sideload_aes + desc: '''Verify the keymgr sideload interface to AES. + + Same as `chip_keymgr_sideload_kmac`, except, sideload to AES. + ''' + stage: V2 + tests: ["chip_sw_keymgr_sideload_aes"] + } + { + name: chip_sw_keymgr_sideload_otbn + desc: '''Verify the keymgr sideload interface to OTBN. + + Load OTBN binary image, the rest is similar to `chip_keymgr_sideload_kmac`, except + sideloading to otbn. + + Clear the sideload key once done. + ''' + stage: V2 + tests: ["chip_sw_keymgr_sideload_otbn"] + } + { + name: chip_sw_keymgr_sideload_kmac_error + desc: ''' + Verify the effect of KMAC returning an error during a keymgr operation. + + - Configure keymgr to enter any of the 3 working states. + - Issue a keymgr operation. + - While the KMAC is actively computing the digest, glitch the KMAC app sparse FSM to + trigger a fault. + - Verify that KMAC returns an error signal to the keymgr via checking keymgr CSRs, when + the operation is done: + - Check `op_status` is set to `DONE_ERROR`. + - Check `fault_status.kmac_done` is set to 1. + ''' + stage: V3 + tests: [] + } + + // OTBN (pre-verified IP) integration tests: + { + name: chip_sw_otbn_op + desc: '''Verify an OTBN operation. + + - SW test directs the OTBN engine to perform an ECDSA operation. + - SW validates the reception of the otbn done interrupt once the operation is complete. + - SW verifies the correctness of the result with the expected value which is + pre-computed using a reference model. + ''' + stage: V2 + tests: ["chip_sw_otbn_ecdsa_op_irq", + "chip_sw_otbn_ecdsa_op_irq_jitter_en"] + } + { + name: chip_sw_otbn_rnd_entropy + desc: '''Verify OTBN can fetch RND numbers from the entropy src. + + - SW initializes the entropy subsystem to generate randomness. + - SW loads an OTBN app that executes instructions to read the RND bits. + - The OTBN app ensures that the values when read consequtively do not match, and its not + all 0s or all 1s, as a basic measure to ensure that the entropy subsystem is returning + some data. + ''' + stage: V2 + tests: ["chip_sw_otbn_randomness"] + } + { + name: chip_sw_otbn_urnd_entropy + desc: '''Verify OTBN can fetch URND numbers from the entropy src. + + - Similar to chip_otbn_rnd_entropy, but verifies the URND bits. + ''' + stage: V2 + tests: ["chip_sw_otbn_randomness"] + } + { + name: chip_sw_otbn_idle + desc: '''Verify the OTBN idle signal to clkmgr. + + - Write the OTBN clk hint to 0 within clkmgr to indicate OTBN clk can be gated + and verify that the OTBN clk hint status within clkmgr reads 0 (OTBN is disabled). + - Write the OTBN clk hint to 1 within clkmgr to indicate OTBN clk can be enabled. + Verify that the OTBN clk hint status within clkmgr reads 1 (OTBN is enabled). + - Start an OTBN operation, write the OTBN clk hint to 0 within clkmgr and verify that + the OTBN clk hint status within clkmgr reads 1 (OTBN is enabled) before the + OTBN operation is complete. + - After the OTBN operation is complete, verify that the OTBN clk hint status within + clkmgr now reads 0 again (OTBN is disabled). + - Write the OTBN clk hint to 1, read and check the OTBN output for correctness. + ''' + stage: V2 + tests: ["chip_sw_otbn_randomness"] + } + { + name: chip_sw_otbn_mem_scramble + desc: '''Verify the OTBN can receive keys from the OTP to scramble the OTBN imem and dmem. + + - Initialize the entropy_src subsystem to enable OTP_CTRL fetch random data (already + done by the test_rom startup code). + - Extract random address offsets from RV_CORE_IBEX_RND_DATA. + - Wait for OTBN to be idle. + - Write random address offsets in OTBN imem and dmem. + - Read back the written address offsets and compare against expected values. All values + must match, no integrity errors must be triggered. + - Have OTBN fetch new keys and nonces from the OTP_CTRL. + - Wait for OTBN to be idle. + - Read back the written address offsets. Most reads should trigger integrity errors. It + is possible that after re-scrambling the integrity bits are still valid. But this is + expected to happen rarely. If the number of observed integrity errors is below a + chosen threshold, the test fails. + - Verify the validity of EDN's output to OTP_CTRL via assertions + (unique, non-zero data). + ''' + stage: V2 + tests: ["chip_sw_otbn_mem_scramble"] + } + + ///////////////////////////////////////////////////// + // Memory & Controllers // + // ROM_CTRL, RAM, FLASH, FLASH_CTRL, OTP, OTP_CTRL // + ///////////////////////////////////////////////////// + + // ROM_CTRL (pre-verified IP) integration tests: + { + name: chip_sw_rom_access + desc: '''Verify that the CPU can access the rom contents. + + - Verify that the CPU can fetch instructions from the ROM. + ''' + stage: V2 + tests: ["chip_sw_rom_ctrl_integrity_check"] + } + { + name: chip_sw_rom_ctrl_integrity_check + desc: '''Verify that the ROM ctrl performs the integrity check of the ROM on power up. + + - In non-PROD LC state, the computed digest does not have to match the top 8 words in + the ROM. Verify that we can successfully power up the chip in this case. + - In PROD LC state, verify that the pwrmgr does not fully power up if the computed + digest does not match the top 8 words of the ROM. + ''' + stage: V2 + tests: ["chip_sw_rom_ctrl_integrity_check"] + } + { + name: chip_sw_rom_ctrl_kmac_error + desc: ''' + Verify the effect of KMAC reporting an error during ROM digest computation. + + - Backdoor load a valid test ROM image and bring the DUT out of reset. + - During the ROM checker pwrmgr FSM state, while the ROM controller is actively sending + data to KMAC for the digest computation, glitch the KMAC app sparse FSM to trigger a + fault. + - Verify that KMAC returns an error signal to the ROM controller. + - Verify that the ROM controller itself transitions to invalid state and the chip is + effectively dead. + ''' + stage: V3 + tests: [] + } + + // SRAM (pre-verified IP) integration tests: + { + name: chip_sw_sram_scrambled_access + desc: '''Verify scrambled memory accesses to both main and retention SRAMs. + + - Initialize the entropy_src subsystem to enable OTP_CTRL fetch random data (already + done by the test_rom startup code). + - Trigger both SRAMs to fetch a new key and nonce from the OTP_CTRL + - Drive the CPU to perform random accesses to both RAMs and verify these operations + complete successfully by using the backdoor interface + - Fetch a new key from the OTP_CTRL and ensure that the previous contents cannot be + read anymore. + - Verify the validity of EDN's output to OTP_CTRL via assertions + (unique, non-zero data). + ''' + stage: V2 + tests: ["chip_sw_sram_ctrl_scrambled_access", + "chip_sw_sram_ctrl_scrambled_access_jitter_en"] + } + { + name: chip_sw_sleep_sram_ret_contents + desc: '''Verify that the data within the retention SRAM survives low power entry-exit and reset. + + Ensure that the data within the retention SRAM survives as described in this table. + | Mode | Scrambled | Data Preserved | + |:----------------------------:|:---------:|:--------------:| + | Normal sleep | No | Yes | + | Deep sleep | No | Yes | + | Reset due to a reset request | No | Yes | + | Normal sleep | Yes | Yes | + | Deep sleep | Yes | Yes | + | Reset due to a reset request | Yes | No | + ''' + stage: V2 + tests: ["chip_sw_sleep_sram_ret_contents"] + } + { + name: chip_sw_sram_execution + desc: '''Verify that CPU can fetch instructions from SRAM if enabled. + + - Create the following combinations of 8 scenarios: + - The fetch enable bit in the HW_CFG1 partition of OTP controller set and not set. + - A life cycle state that enables (TEST_UNLOCKED, DEV or RMA) and disables (PROD) + hardware debug. + - The execution CSR programmed to be enabled and disabled. + + - For both, main and the retention SRAM in each of these 8 scenarios: + - Load instruction data into the SRAMs. + - If the instruction execution is enabled, verify that the CPU can fetch and execute + the instruction from the SRAM correctly. + - If the instruction execution is not enabled, verify that the SRAM throws an error + response via an exception handler. + + The following table indicates in which of these scenarios should the instruction + execution be enabled, for both, main and the retention SRAM instances. + + | OTP HW_CFG[IFETCH] | HW_DEBUG_EN via LC state | EXEC CSR | MAIN SRAM | RET SRAM | + |:------------------:|:------------------------:|:--------:|:---------:|:--------:| + | 0 | 0 | 0 | disabled | disabled | + | 0 | 0 | 1 | disabled | disabled | + | 0 | 1 | 0 | enabled | disabled | + | 0 | 1 | 1 | enabled | disabled | + | 1 | 0 | 0 | disabled | disabled | + | 1 | 0 | 1 | enabled | disabled | + | 1 | 1 | 0 | disabled | disabled | + | 1 | 1 | 1 | enabled | disabled | + + For the retention SRAM, instruction fetch is completely disabled via design parameter. + ''' + stage: V2 + tests: ["chip_sw_sram_ctrl_execution_main"] + } + { + name: chip_sw_sram_lc_escalation + desc: '''Verify the LC escalation path to the SRAMs. + + - Configure the LC_CTRL to trigger an escalation request to the SRAMs. + - Verify that the SRAMs stop accepting and responding to new memory requests. + - Reset the system to exit the terminal escalation state. + - Re-initialize the SRAMs and verify that they can now respond correctly to + any further memory requests. + + X-ref with chip_sw_all_escalation_resets and chip_sw_data_integrity. + ''' + stage: V2 + tests: ["chip_sw_all_escalation_resets", + "chip_sw_data_integrity_escalation"] + } + + // OTP (pre-verified IP) integration tests: + { + name: chip_otp_ctrl_init + desc: '''Verify the OTP ctrl initialization on chip power up. + + Verify that the chip powers up correctly on POR. + - The pwrmgr initiates a handshake with OTP ctrl and later, with LC ctrl in subsequent + FSM states. Ensure that the whole power up sequence does not hang. + - Verify with connectivity assertion checks, the handshake signals are connected. + - Ensure that no interrupts or alerts are triggered. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_transition"] + } + { + name: chip_sw_otp_ctrl_keys + desc: '''Verify the proliferation of keys to security peripherals. + + - Verify the correctness of keys provided to SRAM ctrl (main & ret), flash ctrl, keymgr, + (note that keymgr does not have handshake), OTBN and the CPU instruction cache. + - Ensure that the test requests a new key and verifies the previously written + data to an address now returns a garbage value. + + X-ref'ed with the following IP tests that consume these signals: + - chip_sw_sram_scrambled_access + - chip_sw_keymgr_key_derivation + - chip_sw_otbn_mem_scramble + ''' + stage: V2 + tests: [// Verifies both, main and retention SRAM scrambling. + "chip_sw_sram_ctrl_scrambled_access", + "chip_sw_keymgr_dpe_key_derivation", + "chip_sw_otbn_mem_scramble", + "chip_sw_rv_core_ibex_icache_invalidate"] + } + { + name: chip_sw_otp_ctrl_entropy + desc: '''Verify the entropy interface from OTP ctrl to EDN. + + This is X-ref'ed with the chip_otp_ctrl_keys test, which needs to handshake with the EDN + to receive some entropy bits before the keys for SRAM ctrl and OTBN are computed. + ''' + stage: V2 + tests: ["chip_sw_sram_ctrl_scrambled_access", + "chip_sw_keymgr_dpe_key_derivation", + "chip_sw_otbn_mem_scramble", + "chip_sw_rv_core_ibex_icache_invalidate"] + } + { + name: chip_sw_otp_ctrl_program + desc: '''Verify the program request from lc_ctrl. + + - Verify that upon an LC state transition request, LC ctrl signals the OTP ctrl with a + program request. + - Verify that the OTP ctrl generates the LC data output correctly and is sent to the LC + ctrl before it is reset. + - Verify that the `lc_check_byp_en_i` from LC ctrl is set. + - Ensure that the whole operation does not raise any interrupts or alerts or errors. + - After reset, verify that the LC state transition completed successfully by reading the + LC state and LC count CSRs. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_transition"] + } + { + name: chip_sw_otp_ctrl_program_error + desc: '''Verify the otp program error. + + - Initiate an illegal program request from LC ctrl to OTP ctrl by forcing the + `lc_otp_program_i`. + - Verify that the LC ctrl triggers an alert and escalation when the OTP ctrl responds back with the correct + fatal program error as expected. + - Allow escalation to go through reset. + - Use the rstmgr alert info and the fault CSRs to check the alert cause is right. + - Keep state across resets in flash to check that no NMI or regular ISR interrupt run + for kTopDarjeelingAlertIdLcCtrlFatalProgError. + - Verify that, after escalation reset, the alert handler cause and the fault register are cleared. + - Verify after the escalation reset that the alert info captured the correct alert. + ''' + + stage: V2 + tests: ["chip_sw_lc_ctrl_program_error"] + } + { + name: chip_sw_otp_ctrl_hw_cfg + desc: '''Verify the correctness of otp_hw_cfg bus in all peripherals that receive it. + + Preload the OTP ctrl's `hw_cfg` partition with random data and verify that all + consumers of the hardware configuration bits are receiving the correct values. + + Xref'ed with corresponding IP tests that receive these bits. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_otp_hw_cfg"] + } + { + name: chip_sw_otp_ctrl_lc_signals + desc: '''Verify the broadcast signals from LC ctrl. + + - `lc_creator_seed_sw_rw_en_i`: verify that the SECRET2 partition is locked. + - `lc_seed_hw_rd_en_i`: verify that the keymgr outputs a default value when enabled. + - `lc_dft_en_i`: verify that the test interface within OTP ctrl is accessible. + - `lc_check_byp_en_i`: verify that the background check during LC ctrl state + programming passes when enabled. + + Note that `lc_escalate_en_i` is verified via a connectivity test. + + The `lc_seed_hw_rd_en_i` signal can be tested by attempting a keymgr advance operation + into the CreatorRootKey state, which should fail since the root key will be tied off to + all-zero when the SECRET2 partition is not locked in OTP. + + X-ref'ed with chip_sw_lc_ctrl_broadcast test, which verifies the connectivity of the LC + decoded outputs to other IPs. + ''' + stage: V2 + tests: [ + // lc_dft_en_i + "chip_prim_tl_access", + // lc_check_byp_en_i + "chip_sw_lc_ctrl_transition", + // lc_seed_hw_rd_en_i, lc_creator_seed_sw_rw_en_i, also checks lc_keymgr_en_i since it uses + // the keymgr. + "chip_sw_otp_ctrl_lc_signals_test_unlocked0", + "chip_sw_otp_ctrl_lc_signals_dev", + "chip_sw_otp_ctrl_lc_signals_prod", + "chip_sw_otp_ctrl_lc_signals_rma", + ] + } + { + name: chip_sw_otp_prim_tl_access + desc: '''Verify that the SW can read / write the prim tlul interface. + + - The prim tlul interface is a open source placeholder for the closed source CSRs that + will be implemented in a translation 'shim'. + - Verify that when `lc_dft_en_i` is On, this region can be read / written to by the SW. + When `lc_dft_en_i` is Off, accessing this region will result in a TLUL error. + ''' + stage: V2 + tests: ["chip_prim_tl_access"] + } + { + name: chip_sw_otp_ctrl_vendor_test_csr_access + desc: ''' + Verify the vendor test control access in raw, test_*, dev, prod, and rma LC states. + + - Boot the chip successively in raw, test_*, dev, prod and rma LC states. + - Verify that the SW is able to access the vendor test control and status registers in + raw, test_* and rma LC states. + In open source environment, this check is implemented by probing the OTP_CTRL's + `lc_otp_vendor_test_i` port. + - Verify that in dev / prod LC states, the vendor status always reads back 0s regardless + of what is programmed into the vendor test control register. + ''' + stage: V3 + tests: ["chip_sw_otp_ctrl_vendor_test_csr_access"] + } + { + name: chip_sw_otp_ctrl_escalation + desc: '''Verify escalation from otp_ctrl macro fatal error. + + - Inject ECC fatal error into OTP macro's HW cfg partition, and read back this macro + via DAI interface. + - Because this fatal error will immediately turn off CPU, so the DV sequence will probe + the alert interface to make sure alert and escalation is triggered. + + X'ref with chip_sw_all_escalation_resets. + ''' + stage: V3 + tests: ["chip_sw_otp_ctrl_escalation"] + } + { + name: chip_sw_otp_ctrl_nvm_cnt + desc: '''Verify the NVM strike counter partition in otp_ctrl. + + - Check that the partition is all-zeroes first. + - Increment the strike counter by 1 multiple times around different count offsets, e.g.: + - start with offset zero, increment multiple times + - set counter to 30 (which is just before the first word boundary) and increment a few times + - set counter to a higher count close to a word boundary and increment a few times + - Test error cases by + - injecting errors that can be recovered by OR'ing the two counter copies. + - injecting errors that cannot be recovered by OR'ing the two counter copies. + - Set counter to a value close to the maximum and let it saturate. This will overwrite + previously corrupt encodings with all-ones, thus resulting in a consistent encoding. + - Reset the chip and check that the counter is still maximal. + ''' + stage: V2 + tests: ["chip_sw_otp_ctrl_nvm_cnt"] + } + { + name: chip_sw_otp_ctrl_sw_parts + desc: '''Verify that SW partitions can be programmed and read/write locked. + + This test operates on three representative SW partitions with + different attributes and we rely on block-level coverage for the + remaining partitions: + - OWNER_SW_CFG (read and write-lockable) + - OWNERSHIP_SLOT_STATE (only read-lockable) + - EXT_NVM (only read-lockable, no ECC) + + The test checks: + - That the first word of each partition is writable. + - That the dynamic read locks work for each partition. + - That the permanent write lock works for OWNER_SW_CFG only. + ''' + stage: V2 + tests: ["chip_sw_otp_ctrl_sw_parts"] + } + + //////////////////////// + // Analog Peripherals // + // AST, SENSOR_CTRL // + //////////////////////// + + // AST (pre-verified IP) integration tests: + { + name: chip_sw_ast_clk_outputs + desc: '''Verify that the AST generates the 4 clocks when requested by the clkmgr. + + Verify the clock frequencies are reasonably accurate. Bring the chip to deep sleep, + and verify that upon wakeup reset the clock counters are turned off, measure ctrl + regwen is enabled, and errors are not cleared. + ''' + stage: V2 + tests: ["chip_sw_ast_clk_outputs"] + } + { + name: chip_sw_ast_clk_rst_inputs + desc: '''Verify the clk and rst inputs to AST (from `clkmgr`). + + Create different scenarios that affect the clocks and resets and see that the AST features + (RNG, entropy, alert, ADC) that use those clocks/resets behave correctly. + sequence: + 1. Check that AST RNG generates data and fills the entropy source fifo + 2. Create AST alerts + 3. Activate ADC conversion + 4. EDN entropy supply to AST + Enter sleep/deep sleep/ stop IO clocks + Repeat 1-4 to check it is ok. + ''' + stage: V2 + tests: ["chip_sw_ast_clk_rst_inputs"] + } + { + name: chip_sw_ast_sys_clk_jitter + desc: '''Verify that the AST sys clk jitter control. + + X-ref with chip_sw_clkmgr_jitter + ''' + stage: V2 + tests: ["chip_sw_clkmgr_jitter", + "chip_sw_otbn_ecdsa_op_irq_jitter_en", + "chip_sw_aes_enc_jitter_en", + "chip_sw_hmac_enc_jitter_en", + "chip_sw_keymgr_dpe_key_derivation_jitter_en", + "chip_sw_kmac_mode_kmac_jitter_en", + "chip_sw_sram_ctrl_scrambled_access_jitter_en", + "chip_sw_edn_entropy_reqs_jitter"] + } + { + name: chip_sw_ast_alerts + desc: '''Verify the alerts from AST aggregating into the sensor_ctrl. + + X-ref'ed with `chip_sensor_ctrl_ast_alerts`. + ''' + stage: V2 + tests: ["chip_sw_sensor_ctrl_alert"] + } + + // SENSOR_CTRL tests: + { + name: chip_sw_sensor_ctrl_ast_alerts + desc: '''Verify the alerts from AST aggregating into the sensor_ctrl. + + Check that AST events can be triggered from sensor_ctrl and that + the resulting AST outputs are observed in both sensor_ctrl and + the alert_handler. + + For the alert handler case, make sure to test each alert configured + as either recoverable or fatal. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup", + "chip_sw_sensor_ctrl_alert"] + } + { + name: chip_sw_sensor_ctrl_ast_status + desc: '''Verify the io power ok status from AST. + + Check that when the IO POK status changes, an interrupt is triggered + from sensor_ctrl. After triggering, the IO status can be read + from a sensor_ctrl register. + ''' + stage: V2 + tests: ["chip_sw_sensor_ctrl_status"] + } + { + name: chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup + desc: '''Verify the sensor control is able to wake the device + from sleep mode when an alert event is triggered from + AST. X-ref'ed chip_sw_pwrmgr_sleep_all_wake_ups. + ''' + stage: V2 + tests: ["chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup"] + } + + // soc_proxy tests: + { + name: chip_sw_soc_proxy_external_reset_requests + desc: '''Verify that external reset requests reset (parts of) OT. + + - In DV env, trigger the external reset request. + - In DV env, ensure that the desired parts of OT get reset and the others don't. + - In SW, ensure that the reset request shows up in Reset Manager's RESET_INFO register. + ''' + stage: V2 + tests: ["chip_sw_soc_proxy_smoketest"] + } + { + name: chip_sw_soc_proxy_external_irqs + desc: '''Verify that external IRQs are forwarded to the PLIC. + + For each of the external IRQs: + - In DV env, trigger the external IRQ. + - In DV env, ensure that an internal wakeup is requested. + - In SW, ensure that the IRQ shows up in the respective *Interrupt Pending* register of the PLIC. + ''' + stage: V2 + tests: ["chip_sw_soc_proxy_smoketest"] + } + { + name: chip_sw_soc_proxy_external_alerts + desc: '''Verify that external alerts are forwarded to Alert Handler. + + For each of the external alerts (fatal and recoverable): + - In DV env, trigger the external alert. + - In DV env, ensure that an internal wakeup is requested. + Then: + - For recoverable alerts: + - In SW, ensure that the alert shows up in Alert Handler's registers. + - For fatal alerts: + - In DV env, ensure that Alert Handler escalates so that Power Manager triggers a reset. + - In SW, ensure that the reset cause is an escalation by Alert Handler. + ''' + stage: V2 + tests: ["chip_sw_soc_proxy_external_alerts"] + } + { + name: chip_sw_soc_proxy_external_wakeup_requests + desc: '''Verify that external wakeup requests are forwarded to Power Manager. + + - In SW, enable the wakeup in Power Manager. + - In DV env, trigger the wakeup request. + - In SW, ensure that the wakeup request shows up in Power Manager's `WAKE_STATUS` register. + ''' + stage: V2 + tests: ["chip_sw_soc_proxy_external_wakeup"] + } + { + name: chip_sw_soc_proxy_gpios + desc: '''Verify that GPI/Os of the SoC into/from OT are correctly connected to multiplexed I/Os. + + For each of the general-purpose outputs of the SoC into OT + - In SW, configure Pinmux MIO such that the pin is externally observable. + - In DV env, toggle the pin. + - In DV env, ensure that the pattern shows up on the configured pin. + + For each of the general-purpose inputs of the SoC from OT + - In SW, configure Pinmux MIO such that the pin is externally controllable. + - In DV env, toggle the pin. + - In DV env, ensure that the pattern shows up on the SoC input. + ''' + stage: V2 + tests: ["chip_sw_soc_proxy_gpios"] + } + + ////////////////// + // CPU // + // RV_CORE_IBEX // + ////////////////// + + { + name: chip_sw_nmi_irq + desc: '''Verify the NMI interrupt to the CPU and correctness of the cause. + + Randomly use these two methods (simultaneously or choose one of them) to trigger the + NMI interrupt: + - Trigger the alert_handler escalation pair that maps to NMI. + - Trigger a watchdog bark. + + Check rv_core_ibex's NMI interrupt register and clear the interrupt. + If the NMI interrupt is triggered by alert_handle and the `class_clr_regwen` register + is not locked, check that alert_handler can clear this NMI escalation stage. Then make + sure that the alert_handler won't move forward to the next escalation stage. + ''' + stage: V2 + tests: ["chip_sw_rv_core_ibex_nmi_irq"] + } + { + name: chip_sw_rv_core_ibex_rnd + desc: '''Verify the functionality of the random number generation CSRs. + + - Enable entropy complex so `RND_DATA` can get entropy. + - Perform multiple reads from `RND_DATA` polling `RND_STATUS` in + between to only read valid data. Check different random bits + are provided each time and that the random data is never zero or all ones. + - Ensure `RND_STATUS` indicate invalid data immediately after + `RND_DATA` read. + - Perform repeated reads from `RND_DATA` without `RND_STATUS` + polling to check read when invalid doesn't block. + ''' + stage: V2 + tests: ["chip_sw_rv_core_ibex_rnd"] + } + { + name: chip_sw_rv_core_ibex_address_translation + desc: '''Verify the simple address translation functionality. + + - Setup address translation for both slots on the I and D + side and check correct translation for I and D accesses. + - Switch address translation to use different regions that + overlap for both slots and check translation again. Ensure some + test accesses match both regions, where the lowest indexed one + takes priority. + - Turn off address translation and confirm regions are no longer + being remapped. + ''' + stage: V2 + tests: ["chip_sw_rv_core_ibex_address_translation"] + } + { + name: chip_sw_rv_core_ibex_icache_scrambled_access + desc: '''Verify scrambled memory accesses to CPU icache. + + - Initialize the entropy_src subsystem to enable OTP_CTRL fetch random data (already + done by the test_rom startup code). + - Execute the `fence` instruction to invalidate the icache. + - Verify using probes, that this resulted in a new scrambling key fetched from the OTP + ctrl. + ''' + stage: V2 + tests: ["chip_sw_rv_core_ibex_icache_invalidate"] + } + { + name: chip_sw_rv_core_ibex_fault_dump + desc: '''Verify the functionality of the ibex fault dump. + + - Purposely create an ibex exception during execution through reads to an ummapped + address. + - Ensure the rstmgr fault dump correctly captures the related addresses to the + exception. + ''' + stage: V2 + tests: ["chip_sw_rstmgr_cpu_info"] + } + { + name: chip_sw_rv_core_ibex_double_fault + desc: '''Verify the functionality of the ibex double fault dump. + + - Purposely create an ibex double exception during execution, by performing an + unmapped read and in the exception handler perform another unmapped read. + - Ensure the rstmgr fault dump correctly captures both dumps correctly and indicates + the previous dump is valid. + ''' + stage: V2 + tests: ["chip_sw_rstmgr_cpu_info"] + } + { + name: chip_sw_rv_core_ibex_lockstep_glitch + desc: '''Verify lockstep checking of the Ibex core. + + Ensure suitable alerts are triggered when: + - Outputs from the lockstep or the main core are corrupted. + - Inputs into the lockstep core are corrupted. + ''' + stage: V2S + tests: ["chip_sw_rv_core_ibex_lockstep_glitch"] + } + { + name: chip_sw_rv_core_ibex_alerts + desc: '''Inject and verify all available faults in rv_core_ibex / ibex_top. + + Inject faults in the following areas and verify the alert is fired leading to an + escalation. + + - Bus integrity error on the data and instruction TL interface (on the response channel) + - PC mismatch fault + - ECC error in the register file + ''' + stage: V3 + tests: [] + } + + //////////////////////////// + // System level scenarios // + //////////////////////////// + { + name: chip_sw_example_tests + desc: '''Provide example tests for different testing scenarios / needs. + + These tests do not verify the hardware. They are meant to serve as a guide for + developing actual tests under different testing scenarios. These example tests + demonstrate the capabilities of the DV infrastructure which enables these scenarios: + + 1. Implement test in the ROM stage itself + 2. Implement test in the flash stage, using test ROM + 3. Implement test in the flash stage, using production ROM + 4. Enable external maufacturer hooks in existing tests developed in the open source + 5. Enable concurrent threads in tests + ''' + stage: V1 + tests: ["chip_sw_example_rom", + "chip_sw_example_flash", + "chip_sw_uart_smoketest_signed", + "chip_sw_example_manufacturer", + "chip_sw_example_concurrency" + ] + } + { + name: chip_sw_smoketest + desc: '''Run smoke tests developed for each IP. + + The smoke tests are developed by the SW team to test each IP is + alive, and can be actuated by the DIF. We need to ensure that they + work in DV as well. + ''' + stage: V2 + tests: ["chip_sw_aes_smoketest", + "chip_sw_aon_timer_smoketest", + "chip_sw_clkmgr_smoketest", + "chip_sw_csrng_smoketest", + "chip_sw_gpio_smoketest", + "chip_sw_hmac_smoketest", + "chip_sw_kmac_smoketest", + "chip_sw_otbn_smoketest", + "chip_sw_otp_ctrl_smoketest", + "chip_sw_pwrmgr_smoketest", + "chip_sw_rv_plic_smoketest", + "chip_sw_rv_timer_smoketest", + "chip_sw_rstmgr_smoketest", + "chip_sw_sram_ctrl_smoketest", + "chip_sw_uart_smoketest", + ] + } + { + name: chip_sw_rom_functests + desc: '''Run some ROM functional tests with test ROM. + + ROM functional tests test ROM drivers and libraries by exercising + these components in the flash stage, launched via the test ROM. They + primarily are tested on the FPGA, however, we ensure they run in DV + as well. + ''' + stage: V2 + tests: ["rom_keymgr_functest"] + } + { + name: chip_sw_signed + desc: '''Run some chip-level tests with ROM. + + In addition to ROM E2E tests, we select at least one (or a few) + tests defined in this file to sign, and run via ROM instead of + test ROM. We need to ensure our test infrastructure and ROM can + boot and run one (or a few) of the same tests our test ROM can. + ''' + stage: V2 + tests: ["chip_sw_uart_smoketest_signed"] + } + { + name: chip_sw_coremark + desc: '''Run the coremark benchmark on the full chip.''' + stage: V3 + tests: ["chip_sw_coremark"] + } + { + name: chip_sw_boot + desc: '''Verify the full flash image download with bootstrap signal set. + + - SW puts the SPI device in firmware mode + - Load a firmware image (bootstrap) through spi input pin to the spi_device memory. + - SW verifies the integrity of the image upon reception by reading the spi_device + memory. + - Ensure the image is executed correctly + + Note: This flow will be replaced by using spi_device flash mode. + For detail, refer to chip_spi_device_flash_mode + ''' + stage: V2 + tests: ["chip_sw_uart_tx_rx_bootstrap"] + } + { + name: chip_sw_secure_boot + desc: '''Verify the secure boot flow. + + X-ref rom_e2e_smoke. + In reality this can be any rom based test, which requires secure boot. + ''' + stage: V2 + tests: ["base_rom_e2e_smoke"] + } + { + name: chip_lc_scrap + desc: '''Ensure it is possible to enter scrap state from every legal life cycle state. + + - Request transition to SCRAP state using the JTAG interface. + - It should be possible to transition from every legal state using external clock. + - Where it is allowed, transition using internal clocks should also be checked. + - After transition, verify that the device is in SCRAP state through LC read. + - Verify while in SCRAP state: + - RV JTAG interface is unavailable. + - Ibex is not executing. + - RV_DM is unreachable by the stub CPU. + + - X-ref'd with manuf_scrap from the manufacturing testplan. + - X-ref'd with chip_lc_test_locked. + - X-ref'd with chip_tap_strap_sampling + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_rand_to_scrap", + "chip_sw_lc_ctrl_raw_to_scrap", + "chip_sw_lc_ctrl_rma_to_scrap", + "chip_sw_lc_ctrl_test_locked0_to_scrap"] + } + { + name: chip_lc_test_locked + desc: '''Transition from TEST_UNLOCKED to TEST_LOCKED using LC JTAG interface. + + - Check in TEST_UNLOCKED RV JTAG interface is available. + - Verify When in TEST_LOCKED state: + - RV JTAG interface is unavailable. + - Ibex is not executing. + - RV_DM is unreachable by the stub CPU. + + - X-ref'd with manuf_cp_test_lock from the manufacturing testplan. + - X-ref'd with chip_lc_scrap. + - X-ref'd with chip_tap_strap_sampling + - X-ref'd with chip_sw_lc_walkthrough + - X-ref'd with chip_rv_dm_lc_disabled + ''' + stage: V2 + tests: ["chip_sw_lc_walkthrough_testunlocks", + "chip_rv_dm_lc_disabled"] + } + { + name: chip_sw_lc_walkthrough + desc: '''Walk through the life cycle stages from RAW state and reseting the chip each time. + + - Pre-load OTP image with RAW lc_state. + - Initiate the LC transition to one of the test unlock state. + - Program test_unlock_token, test_exit_token, rma_unlock_token into OTP partitions. + - Move forward to next valid LC states via JTAG interface or SW interface if CPU is + enabled. + Verify that the features that should indeed be disabled are indeed disabled. + ''' + stage: V2 + tests: ["chip_sw_lc_walkthrough_dev", + "chip_sw_lc_walkthrough_prod", + "chip_sw_lc_walkthrough_prodend", + "chip_sw_lc_walkthrough_rma", + "chip_sw_lc_walkthrough_testunlocks"] + } + { + name: chip_sw_lc_ctrl_volatile_raw_unlock + desc: '''Configure VOLATILE_RAW_UNLOCK via LC TAP interface and enable CPU execution. + + - Pre-load OTP image with RAW lc_state. + - Initiate the LC transition to test_unlocked0 state using the + VOLATILE_RAW_UNLOCK mode of operation. + - As part of the transition to test_unlocked0, switch the TAP interface to rv_dm. + - Enable ROM execution via rv_dm, and perform POR. + - Initiate a second transition to test_unlocked0 using VOLATILE_RAW_UNLOCK. + - Verify that the CPU is able to execute. + + Test ext_clk injection before enabling ROM execution. + ''' + stage: V2 + tests: ["chip_sw_lc_ctrl_volatile_raw_unlock", + "chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz", + "rom_volatile_raw_unlock"] + } + { + name: chip_sw_rom_raw_unlock + desc: '''Configure RAW_UNLOCK via LC TAP interface and enable CPU execution. + + This test characterizes the DUT initial state before RAW unlock operation, and + switches to external clock via clkmgr to ensure the system clock can be switched + right after transition into test_unlcoked0 state. The test also verifies that + AST is not initialized while CPU is executing code. + + - Pre-load OTP image with RAW lc_state. + - Initiate the LC transition to test_unlocked0 state using the + RAW_UNLOCK mode of operation. + - Switch TAP interface to rv_dm and configure the ROM_EXEC_EN OTP to enable ROM + execution. + - If running with the production ROM, enable signature verification via OTBN to + improve simulation time. + - Perform POR to apply OTP changes. + - With rv_dm TAP still selected, switch to external clock via clkmgr using extclk + slow mode configuration. + - Wait for ROM to start executing code. + - Check AST init done equal to 0 via sensor_ctrl. + ''' + stage: V2 + tests: ["rom_raw_unlock"] + } + { + name: chip_sw_power_max_load + desc: '''Concurrency test modeling maximum load conditions. + + This concurrency test runs multiple blocks at the same time, to simulate + maximum load ("power virus test"). Should be combined with low power + entry and exit scenarios. + + The test should be made configurable so that the type of power state and + the time spent in a particular power state can be configured via a + flag (or similar). This will make it easier to reuse the test for power + simulation and characterization later on. + + The test should set a GPIO (mapped to the IOA2 pin) to high while the power + state of interest is active. + + Blocks / functionality to run simulatenously in this test: + + - The ADC is continuously sampling new data + - Staggered activation of OTBN, aes, KMAC/HMAC. + - KMAC / aes would need to take turns being fed data + - KMAC activation should be a combination of otp background, key + manager background and software + - for OTBN, any signature verification / signing event is sufficient + - Entropy complex ongoing + - reseed / update operation ongoing + - Flash scramble ongoing (ideally both instruction and data, but data should be sufficient + for now) + - instruction scrambling gated by script availability + - Simultaneous IO toggling as defined below + - ideally for digital activity, UART / I2C modules should be activated + - for first pass simplicity can activate IO portion only for now through GPIO + - for dedicated pins, focus on SPI device quad activity + - Ongoing cpu activity (icache / SRAM scrambling both activated) + - servicing ongoing threads and random read/write data to memory + - icache needs to be activated, otherwise the system may spend most of its time fetching + code + - Background checks enabled wherever possible + - rstmgr background checks + - alert_handler ping checks + - OTP background checks + - The test should be run both with / without external clock + + This test should leverage the OTTF test framework for supporting + concurrency in a FreeRTOS environment. See also the design docs linked + in #14095 for more details on how to approach the implementation. + ''' + stage: V3 + tests: ["chip_sw_power_virus"] + } + { + name: chip_sw_exit_test_unlocked_bootstrap + desc: '''End to end test to ensure rom boot strap can be performed after + transitioning from TEST state to PROD state. + + - Pre-load the device into TEST_UNLOCKED state and ROM_EXEC_EN = 0. + - In the same power cycle, advance device to PROD, PROD_END or DEV through LC JTAG request and + set ROM_EXEC_EN in OTP to logically true. + - Reboot the device and perform boot strap of a simple image, (e.g Hello World). + - Ensure boot strap succeeds. + + X-ref'ed with manuf_ft_exit_token from manufacturing test plan. + ''' + stage: V2 + tests: ["chip_sw_exit_test_unlocked_bootstrap"] + } + + { + name: chip_sw_inject_scramble_seed + desc: '''End to end test to ensure boot strap can succeed after injecting scramble seeds. + + - Pre-load the device into PROD, PROD_END or DEV state. + - Backdoor load an unscrambled value into flash isolated partition. + - In the test program, populate the scramble seeds (flash / sram). + - In the test program, populate OTP entries to inform ROM to scramble flash upon next boot. + - Reboot the device and perform boot strap of the same test image, ROM should now program + the flash image with scramble enabled. + - Upon successful boot strap, ROM jumps to the newly programmed image and de-scrambles the + instructions. + - In the test program, check whether the OTP partition containing the scramble seeds is + locked. Also check that the unscrambled value progarmmed into flash isolated partition + can be correctly read back when the region is set to scramble disable. + - If either of the above checks is incorrect, return error. + + + X-ref'ed with manuf_ft_sku_individualization from manufacturing test plan. + ''' + stage: V2 + tests: ["chip_sw_inject_scramble_seed"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_creator_sw_cfg.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_creator_sw_cfg.hjson new file mode 100644 index 00000000000..a57cd0d6421 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_creator_sw_cfg.hjson @@ -0,0 +1,154 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "CREATOR_SW_CFG", + items: [ + { + name: "CREATOR_SW_CFG_DIGEST", + value: "0x0", + }, + { + name: "CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN", + // Use software mod_exp implementation for signature + // verification. See the definition of `hardened_bool_t` in + // sw/lib/sw/device/base/hardened.h. + value: "0x739", + }, + { + name: "CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN", + // Mark the first three keys as valid and remaining as + // invalid since we currently have only three keys. See the + // definition of `hardened_byte_bool_t` in + // sw/lib/sw/device/base/hardened.h. + value: "0x4ba5a5a5a5a5a5a5", + }, + { + name: "CREATOR_SW_CFG_SIGVERIFY_SPX_EN", + // Disable SPX+ signature verification. See the definitions + // of `kSigverifySpxDisabledOtp` and + // `kSigverifySpxEnabledOtp` in + // sw/lib/sw/device/silicon_creator/sigverify/spx_verify.h. + value: "0x8d6c8c17", + }, + { + name: "CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN", + // Mark the first three keys as valid and remaining as + // invalid since we currently have only three keys. See the + // definition of `hardened_byte_bool_t` in + // sw/lib/sw/device/base/hardened.h. + value: "0x4ba5a5a5a5a5a5a5", + }, + { + name: "CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG", + // Default values for flash scramble / ecc / he_en. This OTP + // word contains byte-aligned, packed, 4-bit mubi values. + // See the flash_ctrl driver bitfield definitions in + // sw/device/silicon_creator/lib/drivers/flash_ctrl.h. + value: "0x0", + }, + { + name: "CREATOR_SW_CFG_RNG_EN", + // Enable use of entropy for countermeasures. See the + // definition of `hardened_bool_t` in + // sw/lib/sw/device/base/hardened.h. + value: "0x739", + }, + { + name: "CREATOR_SW_CFG_ROM_EXEC_EN", + // ROM execution is enabled if this item is set to a + // non-zero value. + value: "0xffffffff", + }, + { + name: "CREATOR_SW_CFG_CPUCTRL", + // Value to write to the `cpuctrl` CSR in `rom_init()`. + // Note: Only bits 5:0 are written to the `cpuctrl` CSR. + // See: https://ibex-core.readthedocs.io/en/latest/03_reference/cs_registers.html#cpu-control-register-cpuctrl + value: "0x1", + }, + { + name: "CREATOR_SW_CFG_JITTER_EN", + value: "0x9", + }, + { + name: "CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT", + // Value of the min_security_version_rom_ext field of the + // default boot data. + value: "0x0", + }, + { + name: "CREATOR_SW_CFG_MIN_SEC_VER_BL0", + // Value of the min_security_version_bl0 field of the + // default boot data. + value: "0x0", + }, + { + name: "CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN", + // Enable the default boot data in PROD and PROD_END life + // cycle states. See the definition of `hardened_bool_t` in + // sw/lib/sw/device/base/hardened.h. + value: "0x739", + }, + { + name: "CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS", + value: "0xffffffff", + } + { + name: "CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS", + value: "0xffffffff", + } + { + name: "CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS", + value: "0xffffffff", + } + { + name: "CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS", + value: "0x0", + } + { + name: "CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS", + value: "0xffffffff", + } + { + name: "CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS", + value: "0xffffffff", + } + { + name: "CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS", + value: "0x0", + } + { + name: "CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS", + value: "0xffffffff", + } + { + name: "CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS", + value: "0x0", + } + { + name: "CREATOR_SW_CFG_RNG_ALERT_THRESHOLD", + value: "0xfffd0002", + } + { + name: "CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST", + value: "0x8264cf75", + } + { + // Using the default register reset value. Two consecutive + // failures trigger an alert. + name: "CREATOR_SW_CFG_RNG_ALERT_THRESHOLD", + value: "0xfffd0002", + } + ], + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_dev.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_dev.hjson new file mode 100644 index 00000000000..a417d342821 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_dev.hjson @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // 256 bit seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + // The default seed was generated using secrets.py module. + seed: 85452983286950371191603618368782861611109037138182535346147818831008789508651 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "SECRET0", + lock: "True", + items: [ + { + name: "TEST_UNLOCK_TOKEN", + value: "", + } + { + name: "TEST_EXIT_TOKEN", + value: "", + } + ], + } + { + name: "SECRET1", + lock: "True", + items: [ + { + name: "SRAM_DATA_KEY_SEED", + value: "", + } + ], + } + { + name: "SECRET2", + lock: "False", + items: [ + { + name: "RMA_TOKEN", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE0", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE1", + value: "", + } + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "DEV", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: "5" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_hw_cfg.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_hw_cfg.hjson new file mode 100644 index 00000000000..794a24132ab --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_hw_cfg.hjson @@ -0,0 +1,39 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "HW_CFG0", + // If set to true, this computes the HW digest value + // and locks the partition. + lock: "True", + items: [ + { + name: "DEVICE_ID", + value: "", + }, + ], + } + { + name: "HW_CFG1", + // If set to true, this computes the HW digest value + // and locks the partition. + lock: "True", + items: [ + { + // Cryptolib and chip-level tests require access to the + // CSRNG software interfaces. + name: "EN_CSRNG_SW_APP_READ", + value: true, + }, + ], + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_owner_sw_cfg.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_owner_sw_cfg.hjson new file mode 100644 index 00000000000..53ee59e8ded --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_owner_sw_cfg.hjson @@ -0,0 +1,245 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "OWNER_SW_CFG", + items: [ + { + name: "OWNER_SW_CFG_DIGEST", + value: "0x0", + }, + { + name: "OWNER_SW_CFG_ROM_BOOTSTRAP_DIS", + // Enable bootstrap. See `hardened_bool_t` in + // sw/lib/sw/device/base/hardened.h. + value: "0x1d4", + }, + { + name: "OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN", + // Set to 0x739 to use the ROM_EXT hash measurement as the + // key manager attestation binding value. + value: "0x0", + }, + { + name: "OWNER_SW_CFG_ROM_ALERT_CLASS_EN" + // Set the enables to kAlertEnableNone. + // See `alert_enable_t` + // in sw/device/silicon_creator/lib/drivers/alert.h + value: "0xa9a9a9a9", + }, + { + name: "OWNER_SW_CFG_ROM_ALERT_ESCALATION" + // Set the esclation policies to kAlertEscalateNone. + // See `alert_escalate_t` + // in sw/device/silicon_creator/lib/drivers/alert.h + value: "0xd1d1d1d1", + }, + { + name: "OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION" + // Set the classifiactions to kAlertClassX. + // See `alert_class_t` + // in sw/device/silicon_creator/lib/drivers/alert.h + value: [ + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + ], + }, + { + name: "OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION" + // Set the classifiactions to kAlertClassX. + // See `alert_class_t` + // in sw/device/silicon_creator/lib/drivers/alert.h + value: [ + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + "0x94949494", + ], + }, + { + name: "OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH" + // Set the alert accumulation thresholds to 0 per class. + value: [ + "0x00000000", + "0x00000000", + "0x00000000", + "0x00000000", + ], + }, + { + name: "OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES" + // Set the alert timeout cycles to 0 per class. + value: [ + "0x00000000", + "0x00000000", + "0x00000000", + "0x00000000", + ], + }, + { + name: "OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES" + // Set the alert phase cycles to 0,10,10,0xFFFFFFFF for + // classes A and B, and to all zeros for classes C and D. + value: [ + "0x0", "0xa", "0xa", "0xFFFFFFFF", + "0x0", "0xa", "0xa", "0xFFFFFFFF", + "0x0", "0x0", "0x0", "0x0", + "0x0", "0x0", "0x0", "0x0", + ], + }, + // Note, these values need updating whenever the top-specific + // alert_handler parameterization changes. To update the + // digests values, perform the following steps: + // + // 1. Make sure the alert_handler register map in + // + // sw/host/opentitanlib/src/otp/alert_handler_regs.rs + // + // is up to date. See also + // + // https://github.com/lowRISC/opentitan/issues/19501 + // + // 2. Run opentitantool + // + // opentitantool --rcfile="" otp alert-digest \ + // hw/top_darjeeling/data/otp/otp_ctrl_img_owner_sw_cfg.hjson + // + // and enter the new values in this file. + { + name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", + value: "0x8a12908b", + }, + { + name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", + value: "0xe4bab764", + }, + { + name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", + value: "0x10f153e1", + }, + { + name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", + value: "0x4ec41fc0", + } + ], + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_prod.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_prod.hjson new file mode 100644 index 00000000000..6ce105dd11c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_prod.hjson @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // 256 bit seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + // The default seed was generated using secrets.py module. + seed: 113517944176559405110937879233240229311794601727326023435899657066678782830485 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "SECRET0", + lock: "True", + items: [ + { + name: "TEST_UNLOCK_TOKEN", + value: "", + } + { + name: "TEST_EXIT_TOKEN", + value: "", + } + ], + } + { + name: "SECRET1", + lock: "True", + items: [ + { + name: "SRAM_DATA_KEY_SEED", + value: "", + } + ], + } + { + name: "SECRET2", + lock: "False", + items: [ + { + name: "RMA_TOKEN", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE0", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE1", + value: "", + } + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "PROD", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: "5" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_raw.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_raw.hjson new file mode 100644 index 00000000000..e5a94be7cab --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_raw.hjson @@ -0,0 +1,27 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // Seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + // The default seed was generated using secrets.py module. + seed: 52408960416235844780753299194502148156786072650816676092165912261205302331741 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "RAW", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: 0 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_rma.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_rma.hjson new file mode 100644 index 00000000000..4c13e6a865d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_rma.hjson @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // Seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + // The default seed was generated using secrets.py module. + seed: 52408960416235844780753299194502148156786072650816676092165912261205302331741 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "SECRET0", + lock: "True", + items: [ + { + name: "TEST_UNLOCK_TOKEN", + value: "", + } + { + name: "TEST_EXIT_TOKEN", + value: "", + } + ], + } + { + name: "SECRET1", + lock: "True", + items: [ + { + name: "SRAM_DATA_KEY_SEED", + value: "", + } + ], + } + { + name: "SECRET2", + lock: "False", + items: [ + { + name: "RMA_TOKEN", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE0", + value: "", + } + { + name: "CREATOR_ROOT_KEY_SHARE1", + value: "", + } + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "RMA", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: "8" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_locked0.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_locked0.hjson new file mode 100644 index 00000000000..9f93b53d48e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_locked0.hjson @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // Seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + seed: 52408960416235844780753299194502148156786072650816676092165912261205302331741 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "CREATOR_SW_CFG", + items: [ + { + name: "CREATOR_SW_CFG_ROM_EXEC_EN", + // ROM execution is enabled if this item is set to a + // non-zero value. + value: "0xffffffff", + }, + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "TEST_LOCKED0", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: 2 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_locked1.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_locked1.hjson new file mode 100644 index 00000000000..92c9da20054 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_locked1.hjson @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // Seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + seed: 52408960416235844780753299194502148156786072650816676092165912261205302331741 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "CREATOR_SW_CFG", + items: [ + { + name: "CREATOR_SW_CFG_ROM_EXEC_EN", + // ROM execution is enabled if this item is set to a + // mnon-zero value. + value: "0xffffffff", + }, + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "TEST_LOCKED1", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: 2 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_unlocked0.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_unlocked0.hjson new file mode 100644 index 00000000000..c6cd69f81e1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_unlocked0.hjson @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // Seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + seed: 52408960416235844780753299194502148156786072650816676092165912261205302331741 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "CREATOR_SW_CFG", + items: [ + { + name: "CREATOR_SW_CFG_ROM_EXEC_EN", + // ROM execution is enabled if this item is set to a + // non-zero value. + value: "0xffffffff", + }, + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "TEST_UNLOCKED0", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: 1 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_unlocked1.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_unlocked1.hjson new file mode 100644 index 00000000000..f8d5a975f69 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_unlocked1.hjson @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // Seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + seed: 52408960416235844780753299194502148156786072650816676092165912261205302331741 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "CREATOR_SW_CFG", + items: [ + { + name: "CREATOR_SW_CFG_ROM_EXEC_EN", + // ROM execution is enabled if this item is set to a + // non-zero value. + value: "0xffffffff", + }, + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "TEST_UNLOCKED1", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: 3 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_unlocked2.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_unlocked2.hjson new file mode 100644 index 00000000000..07228a53a45 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_img_test_unlocked2.hjson @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-img.py script to convert this configuration into +// a MEM file for preloading the OTP in FPGA synthesis or simulation. +// + +{ + // Seed to be used for generation of partition randomized values. + // Can be overridden on the command line with the --seed switch. + seed: 52408960416235844780753299194502148156786072650816676092165912261205302331741 + + // The partition and item names must correspond with the OTP memory map. + partitions: [ + { + name: "CREATOR_SW_CFG", + items: [ + { + name: "CREATOR_SW_CFG_ROM_EXEC_EN", + // ROM execution is enabled if this item is set to a + // non-zero value. + value: "0xffffffff", + }, + ], + } + { + name: "LIFE_CYCLE", + // Can be one of the following strings: + // RAW, TEST_UNLOCKED0-3, TEST_LOCKED0-2, DEV, PROD, PROD_END, RMA, SCRAP + state: "TEST_UNLOCKED2", + // Can range from 0 to 16. + // Note that a value of 0 is only permissible in RAW state. + count: 4 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_mmap.hjson b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_mmap.hjson new file mode 100644 index 00000000000..31c0cd3952f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/otp/otp_ctrl_mmap.hjson @@ -0,0 +1,1094 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Use the gen-otp-mmap.py script to update dependent files (like documentation +// tables the comportable hjson and metadata SV package): +// +// $ ./util/design/gen-otp-mmap.py +// +// Make sure to regenerate the CSRs after converting the memory map: +// +// $ cd ${PROJ_ROOT} +// $ make -C hw regs +// + +{ + // 256 bit seed to be used for generation of partition item default values. + // Can be overridden on the command line with the --seed switch. + seed: "36021179872380457113239299468132194022238108125576166239904535336103582949069" + + otp: { + width: "2", // bytes + depth: "8192" + } + + // Definition of scrambling and digest constants and keys. + scrambling: { + key_size: "16", + iv_size: "8", + cnst_size: "16", + keys: [ + { + name: "Secret0Key", + value: "", + } + { + name: "Secret1Key", + value: "", + } + { + name: "Secret2Key", + value: "", + } + { + name: "Secret3Key", + value: "", + } + ] + digests: [ + // This is the consistency digest used by all partitions. + { + name: "CnstyDigest", + iv_value: "", + cnst_value: "", + } + // The other digest configurations below are used for + // key derivation and token hashing. + { + name: "SramDataKey", + iv_value: "", + cnst_value: "", + } + ] + } + + // The enumeration order below defines the address map of the OTP controller, + // if the offsets are not defined explicitly via the "offset" key. + // Note that the digest items are added automatically to the address map. + partitions: [ + { + name: "VENDOR_TEST", + variant: "Unbuffered", + absorb: false, + size: "64", // in bytes + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: false, // Do not use integrity (ECC) on this partition. + bkout_type: false, // Do not generate a breakout type for this partition. + items: [ + { + name: "SCRATCH", + size: "56" + } + ], + desc: '''Vendor test partition. + This is reserved for manufacturing smoke checks. The OTP wrapper + control logic inside prim_otp is allowed to read/write to this + region. ECC uncorrectable errors seen on the functional prim_otp + interface will not lead to an alert for this partition. + Instead, such errors will be reported as correctable ECC errors. + ''' + } + { + name: "CREATOR_SW_CFG", + variant: "Unbuffered", + absorb: false, + size: "320", // in bytes + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, // Use integrity (ECC) on this partition. + bkout_type: false, // Do not generate a breakout type for this partition. + items: [ + { + name: "CREATOR_SW_CFG_AST_CFG", + size: "124" + } + { + name: "CREATOR_SW_CFG_AST_INIT_EN", + size: "4" + } + { + name: "CREATOR_SW_CFG_OVERRIDES", + size: "32" + } + { + name: "CREATOR_SW_CFG_ROM_EXT_SKU", + size: "4" + } + { + name: "CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN", + size: "4" + } + { + name: "CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN", + size: "8" + } + { + name: "CREATOR_SW_CFG_SIGVERIFY_SPX_EN", + size: "4" + } + { + name: "CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN", + size: "8" + } + { + name: "CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG", + size: "4" + } + { + name: "CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG", + size: "4" + } + { + name: "CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_EN", + size: "4" + } + { + name: "CREATOR_SW_CFG_JITTER_EN", + size: "4" + } + { + name: "CREATOR_SW_CFG_RET_RAM_RESET_MASK", + size: "4" + } + { + name: "CREATOR_SW_CFG_MANUF_STATE", + size: "4" + } + { + name: "CREATOR_SW_CFG_ROM_EXEC_EN", + size: "4" + } + { + name: "CREATOR_SW_CFG_CPUCTRL", + size: "4" + } + { + name: "CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT", + size: "4" + } + { + name: "CREATOR_SW_CFG_MIN_SEC_VER_BL0", + size: "4" + } + { + name: "CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN", + size: "4" + } + { + name: "CREATOR_SW_CFG_RMA_SPIN_EN", + size: "4" + } + { + name: "CREATOR_SW_CFG_RMA_SPIN_CYCLES", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_ALERT_THRESHOLD", + size: "4" + } + { + name: "CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST", + size: "4" + } + { + name: "CREATOR_SW_CFG_SRAM_KEY_RENEW_EN", + size: "4" + } + ], + desc: '''Software configuration partition. + This is for device-specific calibration data. For example, clock, + LDO, RNG. + ''' + } + { + name: "OWNER_SW_CFG", + variant: "Unbuffered", + absorb: false, + size: "632", // in bytes + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "OWNER_SW_CFG_ROM_ERROR_REPORTING", + size: "4" + } + { + name: "OWNER_SW_CFG_ROM_BOOTSTRAP_DIS", + size: "4" + } + { + name: "OWNER_SW_CFG_ROM_ALERT_CLASS_EN", + size: "4" + } + { + name: "OWNER_SW_CFG_ROM_ALERT_ESCALATION", + size: "4" + } + { + name: "OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION", + size: "400" + } + { + name: "OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION", + size: "64" + } + { + name: "OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH", + size: "16" + } + { + name: "OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES", + size: "16" + } + { + name: "OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES", + size: "64" + } + { + name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", + size: "4", + } + { + name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", + size: "4", + } + { + name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", + size: "4", + } + { + name: "OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", + size: "4", + } + { + name: "OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES", + size: "4" + } + { + name: "OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN", + size: "4" + } + { + name: "OWNER_SW_CFG_MANUF_STATE", + size: "4" + } + { + name: "OWNER_SW_CFG_ROM_RSTMGR_INFO_EN", + size: "4" + } + ], + desc: '''Software configuration partition. + This contains data that changes software behavior in the ROM, for + example enabling defensive features in ROM or selecting failure + modes if verification fails. + ''' + } + { + name: "OWNERSHIP_SLOT_STATE", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: false, + hw_digest: false, + write_lock: "None", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH", + size: "16" + desc: ''' Creator Ownership transfer state management + OWNERSHIP_ST_RAW: ownership not yet claimed (factory default) + OWNERSHIP_ST_LOCKED0: first ownership slot claimed + OWNERSHIP_ST_RELEASED0: first ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED1: second ownership slot claimed + OWNERSHIP_ST_SCRAPPED: scrap state - terminal + ''' + } + { + name: "OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH", + size: "16" + desc: ''' Creator Ownership transfer state management + OWNERSHIP_ST_RAW: ownership not yet claimed (factory default) + OWNERSHIP_ST_LOCKED0: first ownership slot claimed + OWNERSHIP_ST_RELEASED0: first ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED1: second ownership slot claimed + OWNERSHIP_ST_SCRAPPED: scrap state - terminal + ''' + } + { + name: "OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH", + size: "16" + desc: ''' Creator Ownership transfer state management + OWNERSHIP_ST_RAW: ownership not yet claimed (factory default) + OWNERSHIP_ST_LOCKED0: first ownership slot claimed + OWNERSHIP_ST_RELEASED0: first ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED1: second ownership slot claimed + OWNERSHIP_ST_RELEASED1: second ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED2: third ownership slot claimed + OWNERSHIP_ST_RELEASED2: third ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED3: fourth ownership slot claimed + OWNERSHIP_ST_SCRAPPED: scrap state - terminal + ''' + } + ] + desc: '''SW managed asset ownership states partition. + + Multibit enable value for the tracking the asset ownership states. + Note that the states can be written multiple times in a device lifetime. + The values to be written are engineered in the same way as the LC_CTRL + state encoding words so that the ECC encoding remains valid even after + updating the values. + + The constants can be found in the lc_ctrl_state_pkg.sv package. + + The programming order has to adhere to: + + OWNERSHIP_ST_RAW (factory all-zero state) -> + OWNERSHIP_ST_LOCKED0 -> + OWNERSHIP_ST_RELEASED0 -> + ... + OWNERSHIP_ST_SCRAPPED + + Note that if there are less than 4 slots available the higher slot states + become logically equivalent to OWNERSHIP_SCRAPPED (firmware has to handle + this correctly). + ''' + } + { + name: "ROT_CREATOR_AUTH", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY", + size: "160" + desc: ''' Pub Key used to verify the manufacturing provisioning Software container + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "ROT_CREATOR_AUTH_OWNERSHIP_STATE", + size: "4" + desc: ''' Creator Ownership transfer state management + UNLOCKED - ownership of ROT not yet claimed + LOCKED - ownership claimed and + RELEASED - Release ownership (assets have been cleared, ready to xfer) + ''' + } + { + name: "ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROM2 OTP based patch + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + OTP based key (instead of ROM) facilitates easy key rotation + ''' + } + { + name: "ROT_CREATOR_AUTH_KEYMANIFEST_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT CREATOR KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "ROT_CREATOR_AUTH_UNLOCK4XFER_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT CREATOR KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "ROT_CREATOR_AUTH_IDENTITY_CERT", + size: "768" + desc: ''' ROT Device Identity Certificate endorsed by Silicon Creator stable off device PKI + ''' + } + ], + desc: '''Software managed creator partition. + ''' + } + { + name: "ROT_OWNER_AUTH_SLOT0", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + ], + desc: '''Software managed owner slot 0 partition. + ''' + } + { + name: "ROT_OWNER_AUTH_SLOT1", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + ], + desc: '''Software managed owner slot 1 partition. + ''' + } + { + name: "PLAT_INTEG_AUTH_SLOT0", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + ], + desc: '''Software managed platform integrator slot 0 partition. + ''' + } + { + name: "PLAT_INTEG_AUTH_SLOT1", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + ], + desc: '''Software managed platform integrator slot 1 partition. + ''' + } + { + name: "PLAT_OWNER_AUTH_SLOT0", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + ], + desc: '''Software managed platform owner slot 0 partition. + ''' + } + { + name: "PLAT_OWNER_AUTH_SLOT1", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + ], + desc: '''Software managed platform owner slot 1 partition. + ''' + } + { + name: "PLAT_OWNER_AUTH_SLOT2", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + ], + desc: '''Software managed platform owner slot 2 partition. + ''' + } + { + name: "PLAT_OWNER_AUTH_SLOT3", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + { + name: "PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY", + size: "160" + desc: ''' Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + } + ], + desc: '''Software managed platform owner slot 3 partition. + ''' + } + { + name: "EXT_NVM", + variant: "Unbuffered", + absorb: false, + secret: false, + sw_digest: false, + hw_digest: false, + write_lock: "None", + read_lock: "CSR", + key_sel: "NoKey", + // This is a strike counter, hence we need to disable ECC integrity for this to work. + // Integrity is handled at a higher level by SW as described below. + integrity: false, + bkout_type: false, + items: [ + { + name: "EXT_NVM_ANTIREPLAY_FRESHNESS_CNT", + size: "1024" + desc: ''' Fully SW managed patition + 1 bit (double bit allocated for redundancy - i.e. 2 physical bits for every logical bit) per day + assuming 10 year product lifecycle, allocating 8192 bits of freshness protection. + Implemented as thermometer encoding. Redundant bit programming & logical OR-ing managed by + software. Cannot be ECC protected since different bits in a fuse row are programmed at different times. + ''' + } + ], + desc: '''Anti-replay protection Strike Counters partition. + ''' + } + { + name: "ROM_PATCH", + variant: "Unbuffered", + absorb: true, + secret: false, + sw_digest: true, + hw_digest: false, + write_lock: "Digest", + read_lock: "CSR", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + { + name: "ROM_PATCH_DATA", + size: "9192" + desc: ''' Fully SW managed patition + ROM patch section + signed patch(es) + Each patch Contains header, signature, patch match/redirect configuration and patch code + Please refer to the ROM boot & patching specification for Integrated OT for more details + ''' + } + ], + desc: '''ROM Patch Code section. May contain multiple signed ROM2 patches. + ''' + } + { + name: "HW_CFG0", + variant: "Buffered", + secret: false, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "None", + key_sel: "NoKey", + integrity: true, + bkout_type: true, + items: [ + { + name: "DEVICE_ID", + size: "32", + // Default value to be output in case partition has not + // initialized or is in error state. If not specified, + // a value of '0 will be used. + inv_default: "", + }, + { + name: "MANUF_STATE", + size: "32", + inv_default: "", + } + ], + desc: '''Hardware configuration 0 partition. + This contains + - DEVICE_ID: Unique device identifier. + - MANUF_STATE: Vector for capturing the manufacturing status. + ''' + } + { + name: "HW_CFG1", + variant: "Buffered", + secret: false, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "None", + key_sel: "NoKey", + integrity: true, + bkout_type: true, + items: [ + { + name: "SOC_DBG_STATE", + size: "4", + inv_default: "0x0" + desc: '''Multibit enable value for the SOC debug authorization. + Encoding: + SOC_DBG_RAW: this value is all-zeroes and will be the NOP state; + the LC controller will take precedence. + SOC_DBG_PRE_PROD: this is where the ROT will be in PROD state + but SOC will be in the pre-production unlock state + SOC_DBG_PROD: this is the state where the SOC moves to production, + and the challenge-response based authentication protocol is + required to unlock SOC debug features + ''' + }, + { + name: "EN_CSRNG_SW_APP_READ", + size: "1", + ismubi: true, + inv_default: false, + desc: ''' + Enablement of CSRNG software application interface. A + kMultiBitBool8True value enables, while all other values + disable. Enablement is required to extract output from + CSRNG via software. + ''' + }, + { + name: "EN_SRAM_IFETCH", + size: "1", + ismubi: true, + inv_default: false + }, + ], + desc: '''Hardware configuration 1 partition. + This contains + EN_SRAM_IFETCH: Enable / disable execute from SRAM CSR switch. + SOC_DBG_STATE: Multibit enable value for the SOC debug authorization. + Note SOC_DBG_STATE will be written twice in a device lifetime. The + values to be written are engineered in the same way as the LC_CTRL + state encoding words: the ECC encoding remains valid even after + writing the second value on top of the first. + + The constants can be found in the lc_ctrl_state_pkg.sv package. + + The programming order has to adhere to: + + SOC_DBG_RAW -> SOC_DBG_PRE_PROD -> SOC_DBG_PROD. + ''' + } + { + name: "SECRET0", + variant: "Buffered", + secret: true, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "Digest", + key_sel: "Secret0Key", + integrity: true, + bkout_type: false, + items: [ + { + name: "TEST_UNLOCK_TOKEN", + // This will generate a random default to be output in + // case partition has not initialized or is in error state. + // If not specified, a value of '0 will be used. + inv_default: "", + size: "16" + } + { + name: "TEST_EXIT_TOKEN", + inv_default: "", + size: "16" + } + ], + desc: '''Secret partition 0. + This contains TEST lifecycle unlock tokens. + ''' + } + { + name: "SECRET1", + variant: "Buffered", + secret: true, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "Digest", + key_sel: "Secret1Key", + integrity: true, + bkout_type: false, + items: [ + { + name: "SRAM_DATA_KEY_SEED", + inv_default: "", + size: "16" + } + ], + desc: '''Secret partition 1. + This contains the SRAM scrambling key seed. + ''' + } + { + name: "SECRET2", + variant: "Buffered", + secret: true, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "Digest", + key_sel: "Secret2Key", + integrity: true, + bkout_type: false, + items: [ + { + name: "RMA_TOKEN", + inv_default: "", + size: "16" + } + { + name: "CREATOR_ROOT_KEY_SHARE0", + inv_default: "", + size: "32", + iskeymgr_creator: true + } + { + name: "CREATOR_ROOT_KEY_SHARE1", + inv_default: "", + size: "32" + iskeymgr_creator: true + } + { + name: "CREATOR_SEED", + inv_default: "", + size: "32", + iskeymgr_creator: true + } + ], + desc: '''Secret partition 2. + This contains RMA unlock token, creator root key, and creator seed. + ''' + } + { + name: "SECRET3", + variant: "Buffered", + secret: true, + sw_digest: false, + hw_digest: true, + write_lock: "Digest", + read_lock: "Digest", + key_sel: "Secret3Key", + integrity: true, + bkout_type: false, + items: [ + { + name: "OWNER_SEED", + inv_default: "", + size: "32", + iskeymgr_owner: true + } + ], + desc: '''Secret partition 3. + This contains the owner seed. + ''' + } + { + name: "LIFE_CYCLE", + variant: "LifeCycle", + secret: false, + sw_digest: false, + hw_digest: false, + write_lock: "None", + read_lock: "None", + key_sel: "NoKey", + integrity: true, + bkout_type: false, + items: [ + // The life cycle transition count is specified + // first such that any programming attempt of the life cycle + // partition through the LCI will always write the transition + // counter words first when programming an updated state vector. + // This is an additional safeguard, to the sequencing in the + // life cycle controller to ensure that the counter is always written + // before any state update. I.e., the life cycle controller + // already splits the counter and state updates into two + // supsequent requests through the LCI, where the first request + // only contains the updated transition counter, and the second + // request the updated transition counter and state. + { + name: "LC_TRANSITION_CNT", + inv_default: "", + size: "48" + } + { + name: "LC_STATE", + inv_default: "", + size: "40" + } + ], + desc: '''Lifecycle partition. + This contains lifecycle transition count and state. This partition + cannot be locked since the life cycle state needs to advance to RMA + in-field. Note that while this partition is not marked secret, it + is not readable nor writeable via the DAI. Only the LC controller + can access this partition, and even via the LC controller it is not + possible to read the raw manufacturing life cycle state in encoded + form, since that encoding is considered a netlist secret. The LC + controller only exposes a decoded version of this state. + ''' + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/racl/all_rd_wr_mapping.hjson b/hw/top_darjeeling_no_ibex/data/racl/all_rd_wr_mapping.hjson new file mode 100644 index 00000000000..94f8f5b92a0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/racl/all_rd_wr_mapping.hjson @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ + Null: { + registers: { + "*": "ALL_RD_WR" + } + windows: { + "*": "ALL_RD_WR" + } + } +} diff --git a/hw/top_darjeeling_no_ibex/data/racl/racl.hjson b/hw/top_darjeeling_no_ibex/data/racl/racl.hjson new file mode 100644 index 00000000000..94e21bc10d5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/racl/racl.hjson @@ -0,0 +1,39 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ + // error_response controls whether to return TLUL error on RACL errors + error_response: true + // The CTN UID is transfered via the TLUL reserved user bits: rsvd[ctn_uid_bit_msb:ctn_uid_bit_lsb] + ctn_uid_bit_lsb: 0 + ctn_uid_bit_msb: 4 + // The RACL role is transfered via the TLUL reserved user bits: rsvd[role_bit_msb:role_bit_lsb] + role_bit_lsb: 5 + role_bit_msb: 8 + roles: { + "ROT" : { role_id: 0 } + "ROLE1": { role_id: 1 } + "SOC": { role_id: 2 } + } + policies: { + Null: [ + { name: "ALL_RD_WR" + desc: "Standard policies allowing all roles to access a register" + allowed_rd: [ "ROT", "ROLE1", "SOC" ] + allowed_wr: [ "ROT", "ROLE1", "SOC" ] + } + { name: "ROT_PRIVATE" + rot_private: true + desc: "Standard policies allowing only the ROT role to access a register" + allowed_rd: [ "ROT" ] + allowed_wr: [ "ROT" ] + } + { name: "SOC_ROT" + desc: "Custom policy" + allowed_rd: [ "ROT", "SOC" ] + allowed_wr: [ "ROT", "SOC" ] + } + ] + } +} diff --git a/hw/top_darjeeling_no_ibex/data/racl/soc_rot_mapping.hjson b/hw/top_darjeeling_no_ibex/data/racl/soc_rot_mapping.hjson new file mode 100644 index 00000000000..25dd3e0cee4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/racl/soc_rot_mapping.hjson @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ + Null: { + registers: { + "*": "SOC_ROT" + } + windows: { + "*": "SOC_ROT" + } + } +} diff --git a/hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson b/hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson new file mode 100644 index 00000000000..e998bae4137 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson @@ -0,0 +1,1764 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// TOP Darjeeling configuration +{ name: "darjeeling_no_ibex", + type: "top", + + ///////////////////////////////////////////////////////////// + // 256 bit seed for compile-time random constants // + // NOTE: REPLACE THIS WITH A NEW VALUE BEFORE THE TAPEOUT // + ///////////////////////////////////////////////////////////// + rnd_cnst_seed: 1017106219537032642877583828875051302543807092889754935647094601236425074047, + + // 32-bit datawidth + datawidth: "32", + + // Enable RACL on Darjeeling based on the following configuration + racl_config: 'racl/racl.hjson' + + // Power information for the design + power: { + // Power domains supported by the design + // Aon represents domain aon + // 0 represents domain 0 + domains: ["Aon", "0"], + + // Default power domain used for the design + default: "0" + + // Wait for external resets for integrated OpenTitan + wait_for_external_reset: true + + // Ibex halt feature via additional ROM Control input + halt_ibex_via_rom_ctrl: true // NOTE: This section basically increases the number of ROM control inputs. + // If it's set to 0 it will result in failure + }, + + // List of unmanaged external clocks + unmanaged_clocks: [ + // { name: "my_ext" } + ] + + // This is the clock data structure of the design. + // The hier path refers to the clock reference path (struct / port) + // - The top/ext desgination follows the same scheme as inter-module + // The src key indicates the raw clock sources in the design + // The groups key indicates the various clock groupings in the design + clocks: { + + hier_paths: { + top: "clkmgr_aon_clocks.", // top level is a struct + ext: "", // ext is a port of the clock name + lpg: "clkmgr_aon_cg_en.", // top level struct for alert lpg reset enables + }, + + // Clock Source attributes + // name: Name of group. + // aon: Whether the clock is free running all the time. + // If it is, the clock is not hanlded by clkmgr. + // freq: Absolute frequency of clk in Hz + // ref: indicates the clock is used as a reference for measurement. + srcs: [ + { name: "main", aon: "no", freq: "1000000000" } + { name: "io", aon: "no", freq: "1000000000" } + { name: "aon", aon: "yes", freq: "62500000", ref: true} + ], + + // Derived clock source attributes + // name: Name of group. + // aon: Whether the clock is free running all the time. + // If it is, the clock is not hanlded by clkmgr. + // freq: Absolute frequency of clk in Hz + // src: From which clock source is the clock derived + // div: Ratio between derived clock and source clock + derived_srcs: [ + { name: "io_div2", aon: "no", div: 2, src: "io", freq: "500000000" } + { name: "io_div4", aon: "no", div: 4, src: "io", freq: "250000000" } + ], + + // Clock Group attributes + // name: name of group. + // + // src: The hierarchical source of the clock + // "ext" - clock is supplied from a port of the top module + // "top" - clock is supplied from a net inside the top module + // + // sw_cg: whether software is allowed to gate the clock + // "no" - software is not allowed to gate clocks + // "yes" - software is allowed to gate clocks + // "hint" - software can provide a hint, and hw controls the rest + // + // unique: whether each module in the group can be separately gated + // if sw_cg is "no", this field has no meaning + // "yes" - each clock is individually controlled + // "no" - the group is controlled as one single unit + // + // The powerup and proc groups are unique. + // The powerup group of clocks do not feed through the clock + // controller as they manage clock controller behavior + // The proc group is not peripheral, and directly hardwired + + groups: [ + // the powerup group is used exclusively by clk/pwr/rstmgr/pinmux + { name: "ast", src:"ext", sw_cg: "no" } + { name: "powerup", src:"top", sw_cg: "no" } + { name: "trans", src:"top", sw_cg: "hint", unique: "yes", } + { name: "infra", src:"top", sw_cg: "no", } + { name: "secure", src:"top", sw_cg: "no" } + { name: "peri", src:"top", sw_cg: "yes", unique: "no" } + { name: "timers", src:"top", sw_cg: "no" } + ], + }, + + // This is the reset data structure of the design. + // The hier path refers to the reset reference path (struct / port) + // - The top/ext desgination follows the same scheme as inter-module + // The node key represents all the known resets in the design + resets: { + // Discrete OpenTitan does not need to wait for external resets + wait_for_external_reset: false, + + hier_paths: { + top: "rstmgr_aon_resets.", // top level is a struct + ext: "", // ext is a port of the clock name + lpg: "rstmgr_aon_rst_en.", // top level struct for alert lpg reset enables + }, + + // Reset node attributes + // name: name of reset. + // + // gen: whether the reset is generated + // true: it is a generated reset inside rstmgr + // false: it is a hardwired design reset inside rstmgr (roots and por) + // For non-generated resets, the parent / domain definitions have no meaning. + // + // type: the reset type [ext, top] + // ext: the reset is coming in from the ports, external to darjeeling + // int: the reset is only used inside rstmgr + // top: the reset is output from rstmgr to top level struct + // + // parent: The parent reset + // If type is "ext", there is no root, since it is external + // + // domains: The power domains of a particular reset + // This is a list of the supported power domains. + // Valid values are Aon and (power domain)0 ~ (power domain)1. + // If no value is supplied, the default is specified by the power configuration. + // + // clk: related clock domain for synchronous release + // If type is "por", there is not related clock, since it is + // likely external or generated from a voltage comparator + // + nodes: [ + { name: "por_aon", gen: false, type: "top", clock: "aon" } + { name: "lc_src", gen: false, type: "int", clock: "io_div4" } + { name: "sys_src", gen: false, type: "int", clock: "io_div4" } + { name: "por", gen: true, type: "top", parent: "por_aon", clock: "main" } + { name: "por_io", gen: true, type: "top", parent: "por_aon", clock: "io" } + { name: "por_io_div2", gen: true , type: "top", parent: "por_aon", clock: "io_div2" } + { name: "por_io_div4", gen: true , type: "top", parent: "por_aon", clock: "io_div4" } + { name: "lc", gen: true, type: "top", parent: "lc_src", clock: "main" } + { name: "lc_aon", gen: true, type: "top", parent: "lc_src", clock: "aon" } + { name: "lc_io", gen: true, type: "top", parent: "lc_src", clock: "io" } + { name: "lc_io_div2", gen: true, type: "top", parent: "lc_src", clock: "io_div2" } + { name: "lc_io_div4", gen: true, type: "top", parent: "lc_src", clock: "io_div4" } + { name: "sys", gen: true, type: "top", parent: "sys_src", clock: "main" } + { name: "sys_io_div4", gen: true, type: "top", parent: "sys_src", clock: "io_div4" } + { name: "spi_device", gen: true, type: "top", parent: "lc_src", clock: "io_div4", sw: true } + { name: "spi_host0", gen: true, type: "top", parent: "lc_src", clock: "io_div4", sw: true } + { name: "i2c0", gen: true, type: "top", parent: "lc_src", clock: "io_div4", sw: true }, + ] + } + // The reset requests: peripherals are deduced, but internal and debug need + // to be configure in hjson file. + reset_requests: { + int: [ + { + "name": "MainPwr", + "desc": "main power glitch reset request", + "module": "pwrmgr_aon" + }, + { + "name": "Esc", + "desc": "escalation reset request", + "module": "alert_handler" + } + ], + }, + + // Number of cores: used in rv_plic and timer + num_cores: "1", + + // Interrupt handler information for the design + interrupts: { + // Any module with interrupts that doesn't specify plic + // will have its interrupts sent here + default_plic: "rv_plic" + } + + // `addr_spaces` names the distinct address spaces present in the device. + // All hosts in the same address space share the same base addresses for + // all peripherals, though not every peripheral will be accessible to every + // host in that address space--Access privileges are separate from addresses. + addr_spaces: [ + { name: "hart" + desc: "The main address space, shared between the CPU and DM" + subspaces: [ + { name: "mmio", + desc: ''' + MMIO region excludes any memory that is separate from the module configuration + space, i.e. ROM, main SRAM, and mbx SRAM are excluded but retention SRAM or + spi_device are included. + ''' + nodes: [ + "uart0", + "gpio", + "spi_device", + "i2c0", + "otp_ctrl", + "lc_ctrl.regs", + "alert_handler", + "spi_host0", + "pwrmgr_aon", + "rstmgr_aon", + "clkmgr_aon", + "pinmux_aon", + "aon_timer_aon", + "ast" + "soc_proxy.core", + "soc_dbg_ctrl.core", + "sram_ctrl_ret_aon", + "aes", + "hmac", + "otbn", + "keymgr_dpe" + "csrng", + "entropy_src", + "edn0", + "edn1", + "sram_ctrl_main.regs", + "sram_ctrl_mbox.regs", + "dma", + ], + }, + ] + } + { name: "soc_mbx", desc: "SoC address space for mailbox access"}, + { name: "soc_dbg", desc: "SoC address space for debug module interfaces"}, + ] + + // `module` defines the peripherals. + // Details are coming from each modules' config file `ip.hjson` + // TODO: Define parameter here + // attr: There are a few types of modules supported + // normal(default): Normal, non-templated modules that will be instantiated + // templated: These modules are templated and must be run through topgen + // ipgen: These modules are the same as templated but use the new ipgen flow + // reggen_top: These modules are not templated, but need to have reggen run + // because they live exclusively in hw/top_* instead of hw/ip_*. + // These modules are also instantiated in the top level. + // reggen_only: Similar to reggen_top, but are not instantiated in the top level. + module: [ + { name: "uart0", // instance name + type: "uart", // Must be matched to the ip name in `ip.hson` (_reg, _cfg permitted) + // and `hw/ip/{type}` + + // clock connections defines the port to top level clock connection + // the ip.hjson will declare the clock port names + // If none are defined at ip.hjson, clk_i is used by default + clock_srcs: {clk_i: "io_div4"}, + clock_group: "peri", + // reset connections defines the port to top level reset connection + // the ip.hjson will declare the reset port names + // If none are defined at ip.hjson, rst_ni is used by default + reset_connections: {rst_ni: "lc_io_div4"}, + base_addr: { + hart: "0x30010000", + }, + }, + { name: "gpio", + type: "gpio", + template_type: "gpio", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "peri", + reset_connections: {rst_ni: "lc_io_div4"}, + base_addr: { + hart: "0x30000000", + }, + param_decl: { + GpioAsHwStrapsEn: "1", + GpioAsyncOn: "1" + }, + ipgen_param: { + num_inp_period_counters: 8 + } + attr: "ipgen" + }, + { name: "spi_device", + type: "spi_device", + clock_srcs: {clk_i: "io_div4", scan_clk_i: "io_div2"}, + clock_group: "peri", + reset_connections: {rst_ni: "spi_device"}, + base_addr: { + hart: "0x30310000", + }, + param_decl: { + "SramType": "spi_device_pkg::SramType1r1w" + } + }, + { name: "i2c0", + type: "i2c", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "peri", + reset_connections: {rst_ni: "i2c0"}, + base_addr: { + hart: "0x30080000", + }, + }, + { name: "otp_ctrl", + type: "otp_ctrl", + template_type: "otp_ctrl", + clock_srcs: {clk_i: "io_div4", clk_edn_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc_io_div4", rst_edn_ni: "lc"}, + base_addrs: { + core: {hart: "0x30130000"}, + } + attr: "ipgen", + }, + { + name: "otp_macro", + type: "otp_macro", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc_io_div4"}, + base_addrs: { + prim: {hart: "0x30140000"}, + }, + param_decl: { + Width: "otp_ctrl_macro_pkg::OtpWidth", + Depth: "otp_ctrl_macro_pkg::OtpDepth", + SizeWidth: "otp_ctrl_macro_pkg::OtpSizeWidth", + VendorTestOffset: "otp_ctrl_reg_pkg::VendorTestOffset", + VendorTestSize: "otp_ctrl_reg_pkg::VendorTestSize", + }, + }, + { name: "lc_ctrl", + type: "lc_ctrl", + clock_srcs: {clk_i: "io_div4", clk_kmac_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc_io_div4", rst_kmac_ni: "lc"}, + base_addrs: { + regs: {hart: "0x30150000"}, + dmi: {soc_dbg: "0x3000"}, + }, + param_decl: { + // NOTE THAT THIS IS A FEATURE FOR TEST CHIPS ONLY TO MITIGATE + // THE RISK OF A BROKEN OTP MACRO. THIS WILL BE DISABLED FOR + // PRODUCTION DEVICES. + SecVolatileRawUnlockEn: "top_pkg::SecVolatileRawUnlockEn", + // The following three values get exposed in the life cycle CSRs + // that are also readable via the TAP. + SiliconCreatorId: "16'h 4002", // Darjeeling integration with Rivos + ProductId: "16'h 4000", // Darjeeling + RevisionId: "8'h 01", // First tapeout + // Use TL-UL based DMI + UseDmiInterface: "1", + // Only use 1 RMI interface + NumRmaAckSigs: "1" + EscNumSeverities: "AlertHandlerEscNumSeverities", + EscPingCountWidth: "AlertHandlerEscPingCountWidth", + }, + }, + { name: "alert_handler", + type: "alert_handler", + template_type: "alert_handler", + clock_srcs: {clk_i: "io_div4", clk_edn_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc_io_div4", rst_edn_ni: "lc"}, + base_addr: { + hart: "0x30160000", + }, + param_decl: { + EscNumSeverities: "4", + EscPingCountWidth: "16" + }, + attr: "ipgen", + }, + { name: "spi_host0", + type: "spi_host", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "peri", + reset_connections: {rst_ni: "spi_host0"}, + base_addr: { + hart: "0x30300000", + }, + }, + { name: "pwrmgr_aon", + type: "pwrmgr", + template_type: "pwrmgr", + // TODO: RS, fix after pwrmgr fix is merged + // param_decl: { + // PwrFsmWaitForExtRst: "1" + // } + clock_group: "powerup", + clock_srcs: { + clk_i: "io_div4", + clk_slow_i: "aon", + clk_lc_i: "io_div4", + clk_esc_i: { + clock: "io_div4", + group: "secure" + } + }, + reset_connections: { + rst_ni: { + name: "por_io_div4", + domain: "Aon" + }, + rst_main_ni: { + name: "por_aon", + domain: "0" + }, + rst_lc_ni: { + name: "lc_io_div4", + domain: "Aon" + }, + rst_esc_ni: { + name: "lc_io_div4", + domain: "Aon" + }, + rst_slow_ni: { + name: "por_aon", + domain: "Aon", + }, + } + domain: ["Aon", "0"], + base_addr: { + hart: "0x30400000", + }, + param_decl: { + EscNumSeverities: "AlertHandlerEscNumSeverities", + EscPingCountWidth: "AlertHandlerEscPingCountWidth", + }, + attr: "ipgen", + + }, + { name: "rstmgr_aon", + type: "rstmgr", + template_type: "rstmgr", + clock_srcs: { + clk_i: { + clock: "io_div4", + group: "powerup" + }, + clk_por_i: "io_div4", clk_aon_i: "aon", clk_main_i: "main", clk_io_i: "io", + clk_io_div2_i: "io_div2", clk_io_div4_i: "io_div4" + }, + clock_group: "powerup", + reset_connections: { + rst_ni: { + name: "lc_io_div4", + domain: "Aon" + }, + rst_por_ni: { + name: "por_io_div4", + domain: "Aon" + }, + } + domain: ["Aon", "0"], + base_addr: { + hart: "0x30410000", + }, + attr: "ipgen", + }, + { name: "clkmgr_aon", + type: "clkmgr", + template_type: "clkmgr", + clock_srcs: { + clk_i: "io_div4", + clk_main_i: { + group: "ast", + clock: "main" + }, + clk_io_i: { + group: "ast", + clock: "io" + }, + clk_aon_i: { + group: "ast", + clock: "aon" + } + }, + clock_group: "powerup", + reset_connections: {rst_ni: "lc_io_div4", + rst_aon_ni: "lc_aon" + rst_io_ni: "lc_io", + rst_io_div2_ni: "lc_io_div2", + rst_io_div4_ni: "lc_io_div4", + rst_main_ni: "lc", + rst_root_ni: "por_io_div4", + rst_root_io_ni: "por_io", + rst_root_io_div2_ni: "por_io_div2", + rst_root_io_div4_ni: "por_io_div4", + rst_root_main_ni: "por", + }, + domain: ["Aon"], + base_addr: { + hart: "0x30420000", + }, + attr: "ipgen", + }, + { name: "pinmux_aon", + type: "pinmux", + template_type: "pinmux", + clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"}, + clock_group: "powerup", + reset_connections: {rst_ni: "lc_io_div4", + rst_aon_ni: "lc_aon", + rst_sys_ni: "sys_io_div4" + }, + domain: ["Aon"], + base_addr: { + hart: "0x30460000", + }, + attr: "ipgen", + }, + { name: "aon_timer_aon", + type: "aon_timer", + clock_srcs: {clk_i: "io_div4", clk_aon_i: "aon"}, + clock_group: "timers", + reset_connections: {rst_ni: "lc_io_div4", rst_aon_ni: "lc_aon"}, + domain: ["Aon"], + base_addr: { + hart: "0x30470000", + }, + }, + { name: "ast", + type: "ast", + clock_srcs: { + clk_ast_tlul_i: { + clock: "io_div4", + group: "infra" + }, + clk_ast_adc_i: { + clock: "aon", + group: "peri" + }, + clk_ast_alert_i: { + clock: "io_div4", + group: "secure" + } + clk_ast_rng_i: { + clock: "main", + group: "secure" + } + }, + clock_group: "secure", + reset_connections: { + rst_ast_tlul_ni: { + name: "lc_io_div4", + domain: "0", + } + rst_ast_adc_ni: { + name: "lc_aon", + domain: "Aon" + }, + rst_ast_alert_ni: { + name: "lc_io_div4", + domain: "0", + }, + rst_ast_rng_ni: { + name: "lc", + domain: "0", + }, + }, + domain: ["Aon", "0"], + base_addr: { + hart: "0x30480000", + }, + attr: "reggen_only", + }, + { name: "soc_proxy", + type: "soc_proxy", + clock_srcs: {clk_i: "main", clk_aon_i: "aon"}, + clock_group: "infra", + reset_connections: { + rst_ni: { + name: "lc", + domain: "0", + }, + rst_por_ni: { + name: "por_io_div4", + domain: "Aon", + }, + }, + domain: ["Aon", "0"], + base_addrs: { + core: {hart: "0x22030000"}, + ctn: {hart: "0x40000000"}, + }, + attr: "reggen_top", + memory: { + ctn: { + label: "ctn", + swaccess: "rw", + data_intg_passthru: "true", + exec: "True", + byte_write: "True", + size: "0x40000000", + } + } + }, + { name: "sram_ctrl_ret_aon", + type: "sram_ctrl", + clock_srcs: {clk_i: "io_div4", clk_otp_i: "io_div4"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc_io_div4", rst_otp_ni: "lc_io_div4"} + domain: ["Aon"], + param_decl: { + InstrExec: "0", + InstSize: 4096 + } + base_addrs: { + regs: {hart: "0x30500000"}, + ram: {hart: "0x30600000"}, + }, + // Memory regions must be associated with a dedicated + // TL-UL device interface. + memory: { + ram: { + label: "ram_ret_aon", + swaccess: "rw", + data_intg_passthru: "true", + exec: "True", + byte_write: "True", + size: "0x1000" + } + } + }, + { name: "rv_plic", + type: "rv_plic", + template_type: "rv_plic", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x28000000", + }, + attr: "ipgen", + targets: ["rv_core_ibex"] + } + { name: "aes", + type: "aes", + clock_srcs: {clk_i: "main", clk_edn_i: "main"}, + clock_group: "trans", + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc"}, + param_decl: { + SecMasking: "1", + SecSBoxImpl: "aes_pkg::SBoxImplDom" + } + base_addr: { + hart: "0x21100000", + }, + }, + { name: "hmac", + type: "hmac", + clock_srcs: {clk_i: "main"}, + clock_group: "trans", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x21110000", + }, + }, + { name: "kmac", + type: "kmac", + param_decl: { + EnMasking: "1", + NumAppIntf: 4, + AppCfg: "'{kmac_pkg::AppCfgKeyMgr,\n kmac_pkg::AppCfgLcCtrl,\n kmac_pkg::AppCfgRomCtrl,\n kmac_pkg::AppCfgRomCtrl}" + } + clock_srcs: {clk_i: "main", clk_edn_i: "main"} + clock_group: "trans" + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc"} + base_addr: { + hart: "0x21120000", + } + }, + { name: "otbn", + type: "otbn", + clock_srcs: { + clk_i: { + clock: "main", + group: "trans" + }, + clk_edn_i: { + clock: "main", + group: "secure" + }, + clk_otp_i: { + clock: "io_div4", + group: "secure" + }, + }, + clock_group: "trans", + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc", rst_otp_ni: "lc_io_div4"}, + base_addr: { + hart: "0x21130000", + }, + }, + { name: "keymgr_dpe", + type: "keymgr_dpe", + clock_srcs: {clk_i: "main", clk_edn_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc", rst_edn_ni: "lc"}, + base_addr: { + hart: "0x21140000", + }, + }, + { name: "csrng", + type: "csrng", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x21150000", + }, + }, + { name: "entropy_src", + type: "entropy_src", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x21160000", + }, + param_decl: { + RngBusWidth: "16", + RngBusBitSelWidth: "4", + HealthTestWindowWidth: "20" + // On Darjeeling, in worst case, there is a new 16-bit entropy word from the RNG every 3 + // cycles. Based on the back pressure formula in the entropy_src, this yields a depth of 26. + DistrFifoDepth: "26", + }, + }, + { name: "edn0", + type: "edn", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x21170000", + }, + }, + { name: "edn1", + type: "edn", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x21180000", + }, + }, + { name: "sram_ctrl_main", + type: "sram_ctrl", + clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, + // Note that while it might be useful to allow execution from SRAM for early testing, it can + // later be permanently disabled using the EN_SRAM_IFETCH switch in OTP. + param_decl: { + InstrExec: "1", + InstSize: 65536 + } + base_addrs: { + regs: {hart: "0x211c0000"}, + ram: {hart: "0x10000000"}, + }, + // Memory regions must be associated with a dedicated + // TL-UL device interface. + memory: { + ram: { + label: "ram_main", + swaccess: "rw", + data_intg_passthru: "true", + exec: "True", + byte_write: "True", + size: "0x10000" + } + } + }, + { name: "sram_ctrl_mbox", + type: "sram_ctrl", + clock_srcs: {clk_i: "main", clk_otp_i: "io_div4"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, + param_decl: { + InstrExec: "0", + InstSize: 4096 + } + base_addrs: { + regs: {hart: "0x211d0000"}, + ram: {hart: "0x11000000"}, + }, + // Memory regions must be associated with a dedicated + // TL-UL device interface. + memory: { + ram: { + label: "ram_mbox", + swaccess: "rw", + data_intg_passthru: "true", + exec: "False", + byte_write: "True", + size: "0x1000" + } + } + }, + { name: "rom_ctrl0", + type: "rom_ctrl", + clock_srcs: {clk_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + rom: {hart: "0x00008000"}, + regs: {hart: "0x211e0000"}, + } + memory: { + rom: { + label: "rom0", + swaccess: "ro", + data_intg_passthru: "true", + exec: "True", + byte_write: "False", + size: "0x8000" + data_intg_passthru: "True" + } + }, + param_decl: { + SecDisableScrambling: "1'b0" + } + }, + { name: "rom_ctrl1", + type: "rom_ctrl", + clock_srcs: {clk_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + // TODO(opentitan-integrated/issues/251): + // This is not the final parameterization for Darjeeling. + base_addrs: { + rom: {hart: "0x00020000"}, + regs: {hart: "0x211e1000"}, + } + memory: { + rom: { + label: "rom1", + swaccess: "ro", + data_intg_passthru: "true", + exec: "True", + byte_write: "False", + size: "0x10000" + data_intg_passthru: "True" + } + }, + param_decl: { + SecDisableScrambling: "1'b0" + } + }, + { name: "dma", + type: "dma", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addr: {hart: "0x22010000"}, + }, + { name: "mbx0", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000000"}, + soc: {soc_mbx: "0x01465000"}, + }, + racl_mappings: { + soc: 'racl/all_rd_wr_mapping.hjson' + } + }, + { name: "mbx1", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000100"}, + soc: {soc_mbx: "0x01465100"}, + }, + racl_mappings: { + soc: 'racl/all_rd_wr_mapping.hjson' + } + }, + { name: "mbx2", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000200"}, + soc: {soc_mbx: "0x01465200"}, + }, + racl_mappings: { + soc: 'racl/all_rd_wr_mapping.hjson' + } + }, + { name: "mbx3", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000300"}, + soc: {soc_mbx: "0x01465300"}, + }, + racl_mappings: { + soc: 'racl/all_rd_wr_mapping.hjson' + } + }, + { name: "mbx4", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000400"}, + soc: {soc_mbx: "0x01465400"}, + }, + racl_mappings: { + soc: 'racl/all_rd_wr_mapping.hjson' + } + }, + { name: "mbx5", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000500"}, + soc: {soc_mbx: "0x01465500"}, + }, + racl_mappings: { + soc: 'racl/all_rd_wr_mapping.hjson' + } + }, + { name: "mbx6", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000600"}, + soc: {soc_mbx: "0x01496000"}, + }, + racl_mappings: { + soc: 'racl/all_rd_wr_mapping.hjson' + } + }, + { name: "mbx_jtag", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22000800"}, + soc: {soc_dbg: "0x2200"}, + }, + racl_mappings: { + soc: 'racl/all_rd_wr_mapping.hjson' + } + }, + { name: "mbx_pcie0", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22040000"}, + soc: {soc_mbx: "0x01460100"}, + }, + racl_mappings: { + soc: 'racl/soc_rot_mapping.hjson' + } + }, + { name: "mbx_pcie1", + type: "mbx", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addrs: { + core: {hart: "0x22040100"}, + soc: {soc_mbx: "0x01460200"}, + }, + racl_mappings: { + soc: 'racl/soc_rot_mapping.hjson' + } + }, + { name: "soc_dbg_ctrl", + type: "soc_dbg_ctrl", + clock_srcs: {clk_i: "io_div4"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc_io_div4"}, + base_addrs: { + core: {hart: "0x30170000"}, + jtag: {soc_dbg: "0x2300"}, + }, + }, + { name: "racl_ctrl", + type: "racl_ctrl", + template_type: "racl_ctrl", + clock_srcs: {clk_i: "main"} + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addr: { + soc_mbx: "0x01461f00", + }, + attr: "ipgen" + }, + { name: "ac_range_check", + type: "ac_range_check", + template_type: "ac_range_check", + clock_srcs: {clk_i: "main"}, + clock_group: "secure", + reset_connections: {rst_ni: "lc"}, + base_addr: { + soc_mbx: "0x01464000" + }, + ipgen_param: { + num_ranges: 32 + } + attr: "ipgen", + racl_mapping: 'racl/soc_rot_mapping.hjson' + } + ] + + // All memories wrapped up in relevant controllers + memory: [], + + // The port data structure is not something that should be used liberally. + // It is used specifically to assign special attributes to specific ports. + // For example, this allows us to designate a port as part of inter-module + // connections. + port: [ + { name: "ast", + inter_signal_list: [ + { struct: "lc_tx", + type: "uni", + name: "lc_dft_en", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_hw_debug_en", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + // The activity direction for a port inter-signal is "opposite" of + // what the external module actually needs. + act: "rcv", + package: "ast_pkg", + }, + ] + }, + ] + + // Inter-module Connection. + // format: + // requester: [ resp1, resp2, ... ], + // + // the field and value should be module_inst.port_name + // e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl] + inter_module: { + 'connect': { + 'ast.obs_ctrl' : ['otp_macro.obs_ctrl'] + 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'], + 'alert_handler.esc_rx' : ['lc_ctrl.esc_scrap_state0_rx', + 'lc_ctrl.esc_scrap_state1_rx' + 'pwrmgr_aon.esc_rst_rx'], + 'alert_handler.esc_tx' : ['lc_ctrl.esc_scrap_state0_tx', + 'lc_ctrl.esc_scrap_state1_tx', + 'pwrmgr_aon.esc_rst_tx'], + 'csrng.csrng_cmd' : ['edn0.csrng_cmd', 'edn1.csrng_cmd'], + 'csrng.entropy_src_hw_if' : ['entropy_src.entropy_src_hw_if'], + 'csrng.cs_aes_halt' : ['entropy_src.cs_aes_halt'], + 'otp_ctrl.sram_otp_key' : ['sram_ctrl_main.sram_otp_key', + 'sram_ctrl_ret_aon.sram_otp_key', + 'sram_ctrl_mbox.sram_otp_key'], + 'pwrmgr_aon.pwr_rst' : ['rstmgr_aon.pwr'], + 'pwrmgr_aon.pwr_clk' : ['clkmgr_aon.pwr'], + 'pwrmgr_aon.pwr_otp' : ['otp_ctrl.pwr_otp'], + 'pwrmgr_aon.pwr_lc' : ['lc_ctrl.pwr_lc'], + 'pwrmgr_aon.strap' : ['gpio.strap_en'], + 'pwrmgr_aon.low_power' : ['pinmux_aon.sleep_en', + 'aon_timer_aon.sleep_mode'], + 'pwrmgr_aon.rom_ctrl' : ['rom_ctrl0.pwrmgr_data', + 'rom_ctrl1.pwrmgr_data', + 'soc_dbg_ctrl.continue_cpu_boot'], + 'pwrmgr_aon.boot_status' : ['soc_dbg_ctrl.boot_status'], + 'keymgr_dpe.rom_digest' : ['rom_ctrl0.keymgr_data', + 'rom_ctrl1.keymgr_data'], + 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'], + + // DMA LSIO triggers + 'dma.lsio_trigger' : ['soc_proxy.dma_lsio_trigger'], + 'i2c0.lsio_trigger' : ['soc_proxy.i2c_lsio_trigger'], + 'spi_host0.lsio_trigger' : ['soc_proxy.spi_host_lsio_trigger'], + 'uart0.lsio_trigger' : ['soc_proxy.uart_lsio_trigger'], + + // LC RMA req/ack interface: LC -> OTBN + // Note: this RoT configuration has no embedded flash, hence + // the RMA request is just routed to OTBN directly. + 'lc_ctrl.lc_flash_rma_req' : ['otbn.lc_rma_req'], + 'otbn.lc_rma_ack' : ['lc_ctrl.lc_flash_rma_ack'], + + // Edn connections + 'edn0.edn' : ['keymgr_dpe.edn', 'otp_ctrl.edn', 'kmac.entropy', + 'alert_handler.edn', 'aes.edn', 'otbn.edn_urnd'], + 'edn1.edn' : ['otbn.edn_rnd'], + + // OTBN OTP scramble key + 'otp_ctrl.otbn_otp_key' : ['otbn.otbn_otp_key'], + + // KeyMgr Sideload & KDF function + 'otp_ctrl.otp_keymgr_key' : ['keymgr_dpe.otp_key'], + 'keymgr_dpe.aes_key' : ['aes.keymgr_key'], + 'keymgr_dpe.kmac_key' : ['kmac.keymgr_key'], + 'keymgr_dpe.otbn_key' : ['otbn.keymgr_key'], + + // KMAC Application Interface + // Note that arbitration is fixed priority top to bottom. + 'kmac.app' : ['keymgr_dpe.kmac_data', // Keymgr needs to be at index 0 + 'lc_ctrl.kmac_data', // LC needs to be at index 1 + 'rom_ctrl0.kmac_data', // ROM needs to be at index 2 or 3 + 'rom_ctrl1.kmac_data'], // ROM needs to be at index 2 or 3 + 'kmac.en_masking' : ['keymgr_dpe.kmac_en_masking'] + + // The idle connection is automatically connected through topgen. + // The user does not need to explicitly declare anything other than + // an empty list. + 'clkmgr_aon.idle' : [], + + // OTP LC interface + 'otp_ctrl.otp_lc_data' : ['lc_ctrl.otp_lc_data'], + 'lc_ctrl.lc_otp_program' : ['otp_ctrl.lc_otp_program'], + 'lc_ctrl.lc_otp_vendor_test' : ['otp_macro.test'], +// 'lc_ctrl.lc_otp_vendor_test' : ['otp_ctrl.lc_otp_vendor_test'], + + // Diversification constant coming from life cycle + 'lc_ctrl.lc_keymgr_div' : ['keymgr_dpe.lc_keymgr_div'], + + // LC function control signal broadcast + 'lc_ctrl.lc_raw_test_rma' : ['soc_dbg_ctrl.lc_raw_test_rma'] + 'lc_ctrl.lc_dft_en' : ['otp_macro.lc_dft_en', + 'ast.lc_dft_en', + 'pwrmgr_aon.lc_dft_en', + 'soc_dbg_ctrl.lc_dft_en' + ], + 'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en', + 'ast.lc_hw_debug_en', + 'csrng.lc_hw_debug_en', + 'clkmgr_aon.lc_hw_debug_en', + 'pwrmgr_aon.lc_hw_debug_en', + 'soc_dbg_ctrl.lc_hw_debug_en'], + 'lc_ctrl.lc_keymgr_en' : ['keymgr_dpe.lc_keymgr_en'], + 'lc_ctrl.lc_escalate_en' : ['aes.lc_escalate_en', + 'kmac.lc_escalate_en', + 'otbn.lc_escalate_en', + 'otp_ctrl.lc_escalate_en', + 'sram_ctrl_main.lc_escalate_en', + 'sram_ctrl_ret_aon.lc_escalate_en', + 'sram_ctrl_mbox.lc_escalate_en', + 'aon_timer_aon.lc_escalate_en'], + + 'lc_ctrl.lc_check_byp_en' : ['otp_ctrl.lc_check_byp_en'], + 'lc_ctrl.lc_clk_byp_req' : ['clkmgr_aon.lc_clk_byp_req'], + 'lc_ctrl.lc_clk_byp_ack' : ['clkmgr_aon.lc_clk_byp_ack'], + + // LC access control signal broadcast + 'lc_ctrl.lc_creator_seed_sw_rw_en' : ['otp_ctrl.lc_creator_seed_sw_rw_en'], + 'lc_ctrl.lc_owner_seed_sw_rw_en' : ['otp_ctrl.lc_owner_seed_sw_rw_en'], + 'lc_ctrl.lc_seed_hw_rd_en' : ['otp_ctrl.lc_seed_hw_rd_en'], + + // OTP PRIM_OTP connections + 'otp_ctrl.otp_macro' : ['otp_macro.otp'], + + // spi passthrough connection + 'spi_device.passthrough' : ['spi_host0.passthrough'] + + // Reset manager software reset request to pwrmgr + 'rstmgr_aon.sw_rst_req' : ['pwrmgr_aon.sw_rst_req'], + + // SOC Proxy TLUL Muxing + 'soc_proxy.dma_tl_h2d' : ['dma.ctn_tl_h2d'] + 'soc_proxy.dma_tl_d2h' : ['dma.ctn_tl_d2h'] + + 'soc_proxy.ctn_tl_h2d' : ['ac_range_check.ctn_tl_h2d'] + 'soc_proxy.ctn_tl_d2h' : ['ac_range_check.ctn_tl_d2h'] + } + + // top is to connect to top net/struct. + // It defines the signal in the top and connect from the module, + // use of the signal is up to top template + 'top': [ + // top level net for clocks + 'clkmgr_aon.clocks', + + // top level clock gating indications for alert subsystem + 'clkmgr_aon.cg_en', + + // top level net for reset + 'rstmgr_aon.resets', + + // top level reset asserted indications for alert subsystem + 'rstmgr_aon.rst_en', + + // OTP HW_CFG Broadcast signals. + // TODO(#6713): The actual struct breakout and mapping currently needs to + // be performed by hand in the toplevel template. + 'otp_ctrl.otp_broadcast', + 'csrng.otp_en_csrng_sw_app_read', + 'soc_dbg_ctrl.soc_dbg_state', + 'lc_ctrl.otp_device_id', + 'lc_ctrl.otp_manuf_state', + 'keymgr_dpe.otp_device_id', + 'sram_ctrl_main.otp_en_sram_ifetch', + ], + + // ext is to create port in the top. + 'external': { + 'ast.lc_dft_en' : '', + 'ast.lc_hw_debug_en' : '', + 'ast.obs_ctrl' : 'obs_ctrl', + 'rom_ctrl0.rom_cfg' : 'rom_ctrl0_cfg', + 'rom_ctrl1.rom_cfg' : 'rom_ctrl1_cfg', + 'i2c0.ram_cfg' : 'i2c_ram_1p_cfg', + 'i2c0.ram_cfg_rsp' : 'i2c_ram_1p_cfg_rsp', + 'sram_ctrl_ret_aon.cfg' : 'sram_ctrl_ret_aon_ram_1p_cfg', + 'sram_ctrl_ret_aon.cfg_rsp' : 'sram_ctrl_ret_aon_ram_1p_cfg_rsp', + 'sram_ctrl_main.cfg' : 'sram_ctrl_main_ram_1p_cfg', + 'sram_ctrl_main.cfg_rsp' : 'sram_ctrl_main_ram_1p_cfg_rsp', + 'sram_ctrl_mbox.cfg' : 'sram_ctrl_mbox_ram_1p_cfg', + 'sram_ctrl_mbox.cfg_rsp' : 'sram_ctrl_mbox_ram_1p_cfg_rsp', + 'otbn.ram_cfg_imem' : 'otbn_imem_ram_1p_cfg', + 'otbn.ram_cfg_rsp_imem' : 'otbn_imem_ram_1p_cfg_rsp', + 'otbn.ram_cfg_dmem' : 'otbn_dmem_ram_1p_cfg', + 'otbn.ram_cfg_rsp_dmem' : 'otbn_dmem_ram_1p_cfg_rsp', + // rv_plic connections + 'rv_plic.msip' : 'no_ibex_msip', + 'rv_plic.irq' : 'no_ibex_irq', + 'spi_device.ram_cfg_sys2spi' : 'spi_device_ram_2p_cfg_sys2spi', + 'spi_device.ram_cfg_rsp_sys2spi' : 'spi_device_ram_2p_cfg_rsp_sys2spi', + 'spi_device.ram_cfg_rsp_spi2sys' : 'spi_device_ram_2p_cfg_rsp_spi2sys', + 'spi_device.ram_cfg_spi2sys' : 'spi_device_ram_2p_cfg_spi2sys', + 'pwrmgr_aon.boot_status' : 'pwrmgr_boot_status', + 'clkmgr_aon.jitter_en' : 'clk_main_jitter_en', + 'clkmgr_aon.io_clk_byp_req' : 'io_clk_byp_req', + 'clkmgr_aon.io_clk_byp_ack' : 'io_clk_byp_ack', + 'clkmgr_aon.all_clk_byp_req' : 'all_clk_byp_req', + 'clkmgr_aon.all_clk_byp_ack' : 'all_clk_byp_ack', + 'clkmgr_aon.hi_speed_sel' : 'hi_speed_sel', + 'clkmgr_aon.div_step_down_req' : 'div_step_down_req', + 'clkmgr_aon.calib_rdy' : 'calib_rdy', + 'dma.sys' : 'dma_sys', + 'entropy_src.entropy_src_rng_enable' : 'es_rng_enable', + 'entropy_src.entropy_src_rng_valid' : 'es_rng_valid', + 'entropy_src.entropy_src_rng_bits' : 'es_rng_bit', + 'entropy_src.rng_fips' : 'es_rng_fips', + 'mbx.tl_mbx' : 'mbx_tl', + 'mbx0.doe_intr' : 'mbx0_doe_intr', + 'mbx0.doe_intr_en' : 'mbx0_doe_intr_en', + 'mbx0.doe_intr_support' : 'mbx0_doe_intr_support', + 'mbx0.doe_async_msg_support' : 'mbx0_doe_async_msg_support', + 'mbx1.doe_intr' : 'mbx1_doe_intr', + 'mbx1.doe_intr_en' : 'mbx1_doe_intr_en', + 'mbx1.doe_intr_support' : 'mbx1_doe_intr_support', + 'mbx1.doe_async_msg_support' : 'mbx1_doe_async_msg_support', + 'mbx2.doe_intr' : 'mbx2_doe_intr', + 'mbx2.doe_intr_en' : 'mbx2_doe_intr_en', + 'mbx2.doe_intr_support' : 'mbx2_doe_intr_support', + 'mbx2.doe_async_msg_support' : 'mbx2_doe_async_msg_support', + 'mbx3.doe_intr' : 'mbx3_doe_intr', + 'mbx3.doe_intr_en' : 'mbx3_doe_intr_en', + 'mbx3.doe_intr_support' : 'mbx3_doe_intr_support', + 'mbx3.doe_async_msg_support' : 'mbx3_doe_async_msg_support', + 'mbx4.doe_intr' : 'mbx4_doe_intr', + 'mbx4.doe_intr_en' : 'mbx4_doe_intr_en', + 'mbx4.doe_intr_support' : 'mbx4_doe_intr_support', + 'mbx4.doe_async_msg_support' : 'mbx4_doe_async_msg_support', + 'mbx5.doe_intr' : 'mbx5_doe_intr', + 'mbx5.doe_intr_en' : 'mbx5_doe_intr_en', + 'mbx5.doe_intr_support' : 'mbx5_doe_intr_support', + 'mbx5.doe_async_msg_support' : 'mbx5_doe_async_msg_support', + 'mbx6.doe_intr' : 'mbx6_doe_intr', + 'mbx6.doe_intr_en' : 'mbx6_doe_intr_en', + 'mbx6.doe_intr_support' : 'mbx6_doe_intr_support', + 'mbx6.doe_async_msg_support' : 'mbx6_doe_async_msg_support', + 'mbx_jtag.doe_intr' : 'mbx_jtag_doe_intr', + 'mbx_jtag.doe_intr_en' : 'mbx_jtag_doe_intr_en', + 'mbx_jtag.doe_intr_support' : 'mbx_jtag_doe_intr_support', + 'mbx_jtag.doe_async_msg_support' : 'mbx_jtag_doe_async_msg_support', + 'mbx_pcie0.doe_intr' : 'mbx_pcie0_doe_intr', + 'mbx_pcie0.doe_intr_en' : 'mbx_pcie0_doe_intr_en', + 'mbx_pcie0.doe_intr_support' : 'mbx_pcie0_doe_intr_support', + 'mbx_pcie0.doe_async_msg_support' : 'mbx_pcie0_doe_async_msg_support', + 'mbx_pcie1.doe_intr' : 'mbx_pcie1_doe_intr', + 'mbx_pcie1.doe_intr_en' : 'mbx_pcie1_doe_intr_en', + 'mbx_pcie1.doe_intr_support' : 'mbx_pcie1_doe_intr_support', + 'mbx_pcie1.doe_async_msg_support' : 'mbx_pcie1_doe_async_msg_support', + 'dbg.tl_dbg' : 'dbg_tl', + 'peri.tl_ast' : 'ast_tl', + 'pwrmgr_aon.pwr_ast' : 'pwrmgr_ast', + 'otp_macro.pwr_seq' : '', + 'otp_macro.pwr_seq_h' : '', + 'otp_macro.ext_voltage_h' : 'otp_ext_voltage_h', + 'otp_macro.otp_obs' : 'otp_obs', + 'otp_macro.cfg' : 'otp_cfg', + 'otp_macro.cfg_rsp' : 'otp_cfg_rsp', + 'rstmgr_aon.por_n' : 'por_n' + 'soc_proxy.misc_tl_h2d' : 'ctn_misc_tl_h2d', + 'soc_proxy.misc_tl_d2h' : 'ctn_misc_tl_d2h', + 'soc_proxy.soc_fatal_alert' : 'soc_fatal_alert', + 'soc_proxy.soc_recov_alert' : 'soc_recov_alert', + 'soc_proxy.soc_wkup_async' : 'soc_wkup_async', + 'soc_proxy.soc_rst_req_async' : 'soc_rst_req_async', + 'soc_proxy.soc_intr_async' : 'soc_intr_async', + 'soc_proxy.soc_lsio_trigger' : 'soc_lsio_trigger', + 'soc_proxy.soc_gpi_async' : 'soc_gpi_async', + 'soc_proxy.soc_gpo_async' : 'soc_gpo_async', + 'soc_proxy.integrator_id' : 'integrator_id', + 'spi_device.sck_monitor' : 'sck_monitor', + 'soc_dbg_ctrl.soc_dbg_policy_bus' : 'soc_dbg_policy_bus', + 'soc_dbg_ctrl.halt_cpu_boot' : 'debug_halt_cpu_boot', + 'racl_ctrl.racl_policies' : 'racl_policies', + 'racl_ctrl.racl_error_external' : 'racl_error', + 'ac_range_check.range_check_overwrite' : 'ac_range_check_overwrite', + 'ac_range_check.ctn_filtered_tl_h2d' : 'ctn_tl_h2d', + 'ac_range_check.ctn_filtered_tl_d2h' : 'ctn_tl_d2h' + }, + }, + + // Crossbars: having a top level crossbar + // This version assumes all crossbars are instantiated at the top. + // Assume xbar.hjson is located in the same directory of top.hjson + xbar: [ + { name: "main", + clock_srcs: {clk_main_i: "main", + clk_fixed_i: "io_div4"}, + clock_group: "infra", + reset: "lc", + reset_connections: {rst_main_ni: "lc", + rst_fixed_ni: "lc_io_div4"} + }, + { name: "peri", + clock_srcs: {clk_peri_i: "io_div4", }, + clock_group: "infra", + reset: "lc_io_div4", + reset_connections: {rst_peri_ni: "lc_io_div4"}, + }, + { name: "mbx", + clock_srcs: {clk_mbx_i: "main"}, + clock_group: "infra", + reset: "lc", + reset_connections: {rst_mbx_ni: "lc"}, + }, + { name: "dbg", + clock_srcs: {clk_dbg_i: "main", clk_peri_i: "io_div4"}, + clock_group: "infra", + reset: "lc", + reset_connections: {rst_dbg_ni: "lc", rst_peri_ni: "lc_io_div4"}, + }, + ], + + // ===== PINMUX & PINOUT ====================================================== + + pinout: { + // IO power bank declaration. + // This list defines the IO bank power domains on the ASIC. + // Each individual pad must be in one of the declared power domains. + banks: ['VIO'], + // Pad declaration. + // Each entry must have the following four keys: + // + // - name: Name of the pad (this will be exposed at the chiplevel). + // + // - type: Pad type (this maps to the pad types defined in prim_pad_wrapper_pkg.sv) + // + // - bank: Specifies in which of the IO power banks this pad lives. + // + // - connection: Can have either of the following values: + // + // 1) 'direct': This is a dedicated IO Pad that is directly connected to a peripheral. + // + // 2) 'manual': This is a dedicated IO signal that is not directly connected to a + // peripheral. It needs to be manually wired up in the template. + // + // 3) 'muxed': This is a muxed IO pad that will be connected to the pinmux. + // + // Optionally, each pad can also have a 'desc' field for further description, and a 'port_type' field + // to override the default 'inout wire' type (this is currently only used for simulating ADC connections + // where the ports have to be switched to a real type when the ANALOGSIM macro is defined). + pads: [ + // Special manually connected pads + { name: 'POR_N' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'System reset'}, + { name: 'JTAG_TCK' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TCK signal'}, + { name: 'JTAG_TMS' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TMS signal'}, + { name: 'JTAG_TDI' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TDI signal'}, + { name: 'JTAG_TDO' , type: 'BidirStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TDO signal'}, + { name: 'JTAG_TRST_N' , type: 'InputStd', bank: 'VIO' , connection: 'manual', desc: 'JTAG TRST_N signal'}, + { name: 'OTP_EXT_VOLT' , type: 'AnalogIn1', bank: 'VIO' , connection: 'manual', desc: 'OTP external voltage input'}, + // Dedicated IOs + { name: 'SPI_HOST_D0' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host data'}, + { name: 'SPI_HOST_D1' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host data'}, + { name: 'SPI_HOST_D2' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host data'}, + { name: 'SPI_HOST_D3' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host data'}, + { name: 'SPI_HOST_CLK' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host clock'}, + { name: 'SPI_HOST_CS_L' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI host chip select'}, + { name: 'SPI_DEV_D0' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI device data'}, + { name: 'SPI_DEV_D1' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI device data'}, + { name: 'SPI_DEV_D2' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI device data'}, + { name: 'SPI_DEV_D3' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SPI device data'}, + { name: 'SPI_DEV_CLK' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SPI device clock'}, + { name: 'SPI_DEV_CS_L' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SPI device chip select'}, + { name: 'SPI_DEV_TPM_CS_L', type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SPI device TPM chip select'}, + { name: 'UART_RX' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'UART receive'}, + { name: 'UART_TX' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'UART transmit'}, + { name: 'I2C_SCL' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'I2C clock'}, + { name: 'I2C_SDA' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'I2C data'}, + // RoT GPIO + { name: 'GPIO0' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO1' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO2' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO3' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO4' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO5' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO6' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO7' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO8' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO9' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO10' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO11' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO12' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO13' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO14' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO15' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO16' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO17' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO18' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO19' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO20' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO21' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO22' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO23' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO24' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO25' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO26' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO27' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO28' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO29' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO30' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + { name: 'GPIO31' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'GPIO pad'}, + // SOC GPIO + { name: 'SOC_GPI0' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI1' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI2' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI3' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI4' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI5' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI6' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI7' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI8' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI9' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI10' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPI11' , type: 'InputStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose input'}, + { name: 'SOC_GPO0' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO1' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO2' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO3' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO4' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO5' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO6' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO7' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO8' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO9' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO10' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + { name: 'SOC_GPO11' , type: 'BidirStd', bank: 'VIO', connection: 'direct', desc: 'SoC general purpose output'}, + // Muxed pads + { name: 'MIO0' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO1' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO2' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO3' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO4' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO5' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO6' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO7' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO8' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO9' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO10' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + { name: 'MIO11' , type: 'BidirStd', bank: 'VIO', connection: 'muxed' , desc: 'Muxed IO pad'}, + ] + } + + pinmux: { + // Signal to pinmux/pad mapping. + // Each entry in the list below must have the following two mandatory keys: + // + // - instance: This is the comportable IO instance name where the IO signal comes from. + // + // - connection: This key is similar to the connection key in the pinout/pad configuration and + // can have either of the following values: + // + // 1) 'direct': This is a dedicated IO signal that is directly connected to a pad. + // Such an IO signal must also specify the 'port' and 'pad' keys + // (see further below). + // + // 2) 'manual': This is a dedicated IO signal that is not directly connected to a pad. + // It needs to be manually wired up in the template. + // Such an IO signal may have a 'port' key, but no 'pad' key. + // + // 3) 'muxed': This is a muxed IO signal that will be connected to the pinmux. + // Such an IO signal may have a 'port' key, but no 'pad' key. + // + // Depending on the connection type specified, each entry may have the following optional keys: + // + // - port: Name of the available IO signal of the instance. + // This is required for 'direct' connections, but optional for the others. + // Individual signals of a bus IO signal must be indexed with square brackets, e.g. mybus[1]. + // Not specifying this key or setting it to an empty string acts as a wild card + // and includes all available IOs of this instance. + // + // - pad: Name of the pad the 'direct' connection should connect to. + // This is not required for 'muxed' and 'manual' connections. + // + // - desc: Optional description field. + // + // - attr: Manual direct IOs may specify an additional pad attr field. + // This is used to create the correct pad attribute CSR for that DIO channel (since the + // DIO is manual, there is no way to automatically infer the corresponding pad type). + // + signals: [ + // SPI Host0 + { instance: 'spi_host0', port: 'sck', connection: 'direct', pad: 'SPI_HOST_CLK' , desc: ''}, + { instance: 'spi_host0', port: 'csb', connection: 'direct', pad: 'SPI_HOST_CS_L' , desc: ''}, + { instance: 'spi_host0', port: 'sd[0]', connection: 'direct', pad: 'SPI_HOST_D0' , desc: ''}, + { instance: 'spi_host0', port: 'sd[1]', connection: 'direct', pad: 'SPI_HOST_D1' , desc: ''}, + { instance: 'spi_host0', port: 'sd[2]', connection: 'direct', pad: 'SPI_HOST_D2' , desc: ''}, + { instance: 'spi_host0', port: 'sd[3]', connection: 'direct', pad: 'SPI_HOST_D3' , desc: ''}, + // SPI Device + { instance: 'spi_device', port: 'sck', connection: 'direct', pad: 'SPI_DEV_CLK' , desc: ''}, + { instance: 'spi_device', port: 'csb', connection: 'direct', pad: 'SPI_DEV_CS_L' , desc: ''}, + { instance: 'spi_device', port: 'sd[0]', connection: 'direct', pad: 'SPI_DEV_D0' , desc: ''}, + { instance: 'spi_device', port: 'sd[1]', connection: 'direct', pad: 'SPI_DEV_D1' , desc: ''}, + { instance: 'spi_device', port: 'sd[2]', connection: 'direct', pad: 'SPI_DEV_D2' , desc: ''}, + { instance: 'spi_device', port: 'sd[3]', connection: 'direct', pad: 'SPI_DEV_D3' , desc: ''}, + { instance: "spi_device", port: 'tpm_csb', connection: 'direct', pad: 'SPI_DEV_TPM_CS_L' , desc: ''}, + // UART + { instance: "uart0", port: 'rx', connection: 'direct', pad: 'UART_RX' , desc: ''}, + { instance: "uart0", port: 'tx', connection: 'direct', pad: 'UART_TX' , desc: ''}, + // I2C + { instance: "i2c0", port: 'scl', connection: 'direct', pad: 'I2C_SCL' , desc: ''}, + { instance: "i2c0", port: 'sda', connection: 'direct', pad: 'I2C_SDA' , desc: ''}, + // RoT GPIO + { instance: "gpio", port: 'gpio[0]', connection: 'direct', pad: 'GPIO0' , desc: ''}, + { instance: "gpio", port: 'gpio[1]', connection: 'direct', pad: 'GPIO1' , desc: ''}, + { instance: "gpio", port: 'gpio[2]', connection: 'direct', pad: 'GPIO2' , desc: ''}, + { instance: "gpio", port: 'gpio[3]', connection: 'direct', pad: 'GPIO3' , desc: ''}, + { instance: "gpio", port: 'gpio[4]', connection: 'direct', pad: 'GPIO4' , desc: ''}, + { instance: "gpio", port: 'gpio[5]', connection: 'direct', pad: 'GPIO5' , desc: ''}, + { instance: "gpio", port: 'gpio[6]', connection: 'direct', pad: 'GPIO6' , desc: ''}, + { instance: "gpio", port: 'gpio[7]', connection: 'direct', pad: 'GPIO7' , desc: ''}, + { instance: "gpio", port: 'gpio[8]', connection: 'direct', pad: 'GPIO8' , desc: ''}, + { instance: "gpio", port: 'gpio[9]', connection: 'direct', pad: 'GPIO9' , desc: ''}, + { instance: "gpio", port: 'gpio[10]', connection: 'direct', pad: 'GPIO10' , desc: ''}, + { instance: "gpio", port: 'gpio[11]', connection: 'direct', pad: 'GPIO11' , desc: ''}, + { instance: "gpio", port: 'gpio[12]', connection: 'direct', pad: 'GPIO12' , desc: ''}, + { instance: "gpio", port: 'gpio[13]', connection: 'direct', pad: 'GPIO13' , desc: ''}, + { instance: "gpio", port: 'gpio[14]', connection: 'direct', pad: 'GPIO14' , desc: ''}, + { instance: "gpio", port: 'gpio[15]', connection: 'direct', pad: 'GPIO15' , desc: ''}, + { instance: "gpio", port: 'gpio[16]', connection: 'direct', pad: 'GPIO16' , desc: ''}, + { instance: "gpio", port: 'gpio[17]', connection: 'direct', pad: 'GPIO17' , desc: ''}, + { instance: "gpio", port: 'gpio[18]', connection: 'direct', pad: 'GPIO18' , desc: ''}, + { instance: "gpio", port: 'gpio[19]', connection: 'direct', pad: 'GPIO19' , desc: ''}, + { instance: "gpio", port: 'gpio[20]', connection: 'direct', pad: 'GPIO20' , desc: ''}, + { instance: "gpio", port: 'gpio[21]', connection: 'direct', pad: 'GPIO21' , desc: ''}, + { instance: "gpio", port: 'gpio[22]', connection: 'direct', pad: 'GPIO22' , desc: ''}, + { instance: "gpio", port: 'gpio[23]', connection: 'direct', pad: 'GPIO23' , desc: ''}, + { instance: "gpio", port: 'gpio[24]', connection: 'direct', pad: 'GPIO24' , desc: ''}, + { instance: "gpio", port: 'gpio[25]', connection: 'direct', pad: 'GPIO25' , desc: ''}, + { instance: "gpio", port: 'gpio[26]', connection: 'direct', pad: 'GPIO26' , desc: ''}, + { instance: "gpio", port: 'gpio[27]', connection: 'direct', pad: 'GPIO27' , desc: ''}, + { instance: "gpio", port: 'gpio[28]', connection: 'direct', pad: 'GPIO28' , desc: ''}, + { instance: "gpio", port: 'gpio[29]', connection: 'direct', pad: 'GPIO29' , desc: ''}, + { instance: "gpio", port: 'gpio[30]', connection: 'direct', pad: 'GPIO30' , desc: ''}, + { instance: "gpio", port: 'gpio[31]', connection: 'direct', pad: 'GPIO31' , desc: ''}, + // SoC GPIO + { instance: "soc_proxy", port: 'soc_gpi[0]', connection: 'direct', pad: 'SOC_GPI0' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[1]', connection: 'direct', pad: 'SOC_GPI1' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[2]', connection: 'direct', pad: 'SOC_GPI2' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[3]', connection: 'direct', pad: 'SOC_GPI3' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[4]', connection: 'direct', pad: 'SOC_GPI4' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[5]', connection: 'direct', pad: 'SOC_GPI5' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[6]', connection: 'direct', pad: 'SOC_GPI6' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[7]', connection: 'direct', pad: 'SOC_GPI7' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[8]', connection: 'direct', pad: 'SOC_GPI8' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[9]', connection: 'direct', pad: 'SOC_GPI9' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[10]', connection: 'direct', pad: 'SOC_GPI10' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[11]', connection: 'direct', pad: 'SOC_GPI11' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[12]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[13]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[14]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpi[15]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[0]', connection: 'direct', pad: 'SOC_GPO0' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[1]', connection: 'direct', pad: 'SOC_GPO1' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[2]', connection: 'direct', pad: 'SOC_GPO2' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[3]', connection: 'direct', pad: 'SOC_GPO3' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[4]', connection: 'direct', pad: 'SOC_GPO4' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[5]', connection: 'direct', pad: 'SOC_GPO5' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[6]', connection: 'direct', pad: 'SOC_GPO6' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[7]', connection: 'direct', pad: 'SOC_GPO7' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[8]', connection: 'direct', pad: 'SOC_GPO8' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[9]', connection: 'direct', pad: 'SOC_GPO9' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[10]', connection: 'direct', pad: 'SOC_GPO10' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[11]', connection: 'direct', pad: 'SOC_GPO11' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[12]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[13]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[14]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "soc_proxy", port: 'soc_gpo[15]', connection: 'muxed' , pad: '' , desc: ''}, + // Other MIOs + { instance: "otp_macro", port: 'test[0]', connection: 'muxed' , pad: '' , desc: ''}, + ], + + num_wkup_detect: 8 + wkup_cnt_width: 8 + // Disable USB wakeup and hardware strap sampling for integrated OpenTitan + enable_usb_wakeup: false + enable_strap_sampling: false + } + + // Implementation targets. + // This defines the configuration of the target-specific chip-levels to + // generate from the shared template. Each target uses the same base + // configuration for the pinmux and pinout as defined above, and the + // generated software constants for the pinmux DIF do not change among the + // implementation targets. However, in order to accommodate slight + // differences among the ASIC, FPGA emulation and simulation environments, + // it is possible to make very limited pinout changes below. In particular, + // it is possible to remove and tie-off specific pads, or add more 'manual' + // pads that need to be manually connected in the template. It is also possible + // to override the JTAG and strap locations indices, since the testing and DFT + // setups may differ among the targets. + targets: [ + { name: 'asic', + + // Pinout Changes. + pinout: { + // This is a list of port names to remove from the chip port list. + // The corresponding pad of a removed port will remain instantiated, + // and a wire net will be declared inside the chip-level hierarchy so + // that it can be manually connected as needed. + remove_ports: [], + + // This is a list of pad names to remove from the base pinout defined + // above. Removed pads will be stubbed off such that their inputs + // signals are driven with zero. Output signals and output enables + // will be left unconnected. If no changes are needed, this list can + // be left empty. + remove_pads: [], + + // This is a list of additional "manual" pads to add to the pinout. + // The pad entries have the same format as the pad entries in the pinout + // configuration above. However, the 'connection' key must always be set + // to 'manual' as it is not possible to connect these additional pads + // to the pinmux or peripherals. + add_pads: [], + }, + + pinmux: { + // Special signal positions. Each entry in the list below creates a + // target-specific pad position parameter in the chiplevel hierarchy + // that can be used to parameterize certain IPs like the pinmux or + // padring. This is mainly used to define the pad positions of special + // test and DFT signals such as the JTAG signals and the TAP and DFT + // straps. Straps in this context are special pads that get sampled at + // boot time during certain life cycle states in order to determine + // DFT modes and the TAP mux selection index (the JTAG signals can be + // muxed to either the lifecycle TAP, DFT TAP or RISC-V processor + // TAP). TODO: add more documentation to https://docs.opentitan.org/hw/ip/pinmux/doc/index.html + // Each entry must have the following two keys: + // + // - name: Basename for the SV parameter. + // + // - pad: The pad name that this special signal maps to. The generated + // parameter will be assigned the corresponding pad index. + // + // Each entry may have an optional 'desc' key for further description. + special_signals: [ + // Straps + { name: 'tap0', pad: 'MIO0', desc: 'TAP strap signal.' }, + { name: 'tap1', pad: 'MIO1', desc: 'TAP strap signal.' }, + { name: 'dft0', pad: 'MIO2', desc: 'DFT strap signal.' }, + { name: 'dft1', pad: 'MIO3', desc: 'DFT strap signal.' }, + // JTAG + { name: 'tck', pad: 'MIO4', desc: 'JTAG tck signal.' }, + { name: 'tms', pad: 'MIO5', desc: 'JTAG tms signal.' }, + { name: 'trst_n', pad: 'MIO6', desc: 'JTAG trst_n signal.' }, + { name: 'tdi', pad: 'MIO7', desc: 'JTAG tdi signal.' }, + { name: 'tdo', pad: 'MIO8', desc: 'JTAG tdo signal.' }, + ], + } + }, + { name: 'cw310', + + pinout: { + remove_ports: [], + remove_pads: [ + 'OTP_EXT_VOLT' + ], + + add_pads: [ + // Additional infrastructure pads + { name: 'IO_CLK', type: 'InputStd', bank: 'VIO', connection: 'manual', desc: 'Extra clock input for FPGA target'} + { name: 'POR_BUTTON_N', type: 'InputStd', bank: 'VIO', connection: 'manual', desc: 'Power-on reset button input'} + // ChipWhisperer IO + { name: 'IO_CLKOUT', type: 'BidirStd', bank: 'VIO', connection: 'manual', desc: 'Manual clock output for SCA setup'} + { name: 'IO_TRIGGER', type: 'BidirStd', bank: 'VIO', connection: 'manual', desc: 'Manual trigger output for SCA setup'} + ], + }, + + pinmux: { + special_signals: [ + // Straps + { name: 'tap0', pad: 'MIO0', desc: 'TAP strap signal.' }, + { name: 'tap1', pad: 'MIO1', desc: 'TAP strap signal.' }, + { name: 'dft0', pad: 'MIO2', desc: 'DFT strap signal.' }, + { name: 'dft1', pad: 'MIO3', desc: 'DFT strap signal.' }, + // JTAG + { name: 'tck', pad: 'MIO4', desc: 'JTAG tck signal.' }, + { name: 'tms', pad: 'MIO5', desc: 'JTAG tms signal.' }, + { name: 'trst_n', pad: 'MIO6', desc: 'JTAG trst_n signal.' }, + { name: 'tdi', pad: 'MIO7', desc: 'JTAG tdi signal.' }, + { name: 'tdo', pad: 'MIO8', desc: 'JTAG tdo signal.' }, + ], + } + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/data/xbar_dbg.hjson b/hw/top_darjeeling_no_ibex/data/xbar_dbg.hjson new file mode 100644 index 00000000000..b922f6bcaa5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/xbar_dbg.hjson @@ -0,0 +1,48 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "dbg", + type: "xbar", + clock_primary: "clk_dbg_i", // Main clock, used in sockets + other_clock_list: [ "clk_peri_i" ], // Secondary clocks used by specific nodes + reset_primary: "rst_dbg_ni", // Main reset, used in sockets + other_reset_list: [ "rst_peri_ni" ], // Secondary resets used by specific nodes + + nodes: [ + { name: "dbg", + type: "host", + addr_space: "soc_dbg", + clock: "clk_dbg_i", + reset: "rst_dbg_ni", + xbar: "true", + pipeline: false, + }, + { name: "mbx_jtag.soc", + type: "device", + clock: "clk_dbg_i", + reset: "rst_dbg_ni", + pipeline: false, + }, + { name: "lc_ctrl.dmi", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + } + { name: "soc_dbg_ctrl.jtag", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + } + ], + + connections: { + dbg: [ + "mbx_jtag.soc", + "lc_ctrl.dmi", + "soc_dbg_ctrl.jtag" + ], + }, +} diff --git a/hw/top_darjeeling_no_ibex/data/xbar_main.hjson b/hw/top_darjeeling_no_ibex/data/xbar_main.hjson new file mode 100644 index 00000000000..f05a82c51cc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/xbar_main.hjson @@ -0,0 +1,206 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "main", + type: "xbar", + clock_primary: "clk_main_i", // Main clock, used in sockets + other_clock_list: [ "clk_fixed_i"] // Secondary clocks used by specific nodes + reset_primary: "rst_main_ni", // Main reset, used in sockets + other_reset_list: [ "rst_fixed_ni"] // Secondary resets used by specific nodes + + // Rationale for pipeline and req/rsp_fifo_pass: + // For host interfaces that are used during production state (corei/cored), + // minimize the amount of host introduced latency. This is accomplished + // by setting pipeline to false. + // For host interfaces that are only used for debug, relax the timing by + // inserting a register slice and not allowing passthrough (more access + // latency. This is accomplished by setting `req/rsp_fifo_pass` to false, + // and implicitly using the default of pipeline true. + // + // For device interfaces, especially configuration registers, latency is + // not generally a concern, thus use `req/rsp_fifo_pass` false and pipeline + // true. + // For device accesses to memories (ram / rom / flash), performance is a concern, + // so use pipeline false where permissible by timing. If not, find a combination + // that works. + nodes: [ + { name: "peri", + type: "device", + clock: "clk_fixed_i", + reset: "rst_fixed_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "soc_proxy.ctn", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "hmac", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "kmac" + type: "device" + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + } + { name: "aes", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "otbn", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "keymgr_dpe", + type: "device", + clock: "clk_main_i" + reset: "rst_main_ni" + req_fifo_pass: false, + rsp_fifo_pass: false, + }, + { name: "sram_ctrl_main.ram", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + { name: "sram_ctrl_mbox.ram", + type: "device", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false + }, + { name: "dma.host", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx0.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx1.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx2.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx3.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx4.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx5.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx6.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx_jtag.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx_pcie0.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + { name: "mbx_pcie1.sram", + type: "host", + addr_space: "hart", + clock: "clk_main_i", + reset: "rst_main_ni", + pipeline: false, + }, + + ], + connections: { + // This is the same set of devices that rv_core_ibex.cored is connected to, + // but without ROM0/1 and RV_DM. + dma.host: [ + "sram_ctrl_main.ram", "sram_ctrl_mbox.ram", + "aes", "hmac", "otbn", "keymgr_dpe", "kmac", + "soc_proxy.ctn", "peri" + ], + mbx0.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx1.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx2.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx3.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx4.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx5.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx6.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx_jtag.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx_pcie0.sram: [ + "sram_ctrl_mbox.ram", + ], + mbx_pcie1.sram: [ + "sram_ctrl_mbox.ram", + ], + }, +} diff --git a/hw/top_darjeeling_no_ibex/data/xbar_mbx.hjson b/hw/top_darjeeling_no_ibex/data/xbar_mbx.hjson new file mode 100644 index 00000000000..44165c05407 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/xbar_mbx.hjson @@ -0,0 +1,106 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "mbx", + type: "xbar", + clock_primary: "clk_mbx_i", // Main clock, used in sockets + other_clock_list: [], // Secondary clocks used by specific nodes + reset_primary: "rst_mbx_ni", // Main reset, used in sockets + other_reset_list: [], // Secondary resets used by specific nodes + + nodes: [ + { name: "mbx", + type: "host", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + xbar: "true", + pipeline: false, + }, + { name: "mbx0.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx1.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx2.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx3.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx4.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx5.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx6.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx_pcie0.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "mbx_pcie1.soc", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "racl_ctrl", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + { name: "ac_range_check", + type: "device", + addr_space: "soc_mbx", + clock: "clk_mbx_i", + reset: "rst_mbx_ni", + pipeline: false, + }, + ], + + connections: { + mbx: [ + "mbx0.soc", "mbx1.soc", "mbx2.soc", "mbx3.soc", "mbx4.soc", "mbx5.soc", + "mbx6.soc", "mbx_pcie0.soc", "mbx_pcie1.soc", "racl_ctrl", "ac_range_check" + ], + }, +} diff --git a/hw/top_darjeeling_no_ibex/data/xbar_peri.hjson b/hw/top_darjeeling_no_ibex/data/xbar_peri.hjson new file mode 100644 index 00000000000..86bdc1f5939 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/data/xbar_peri.hjson @@ -0,0 +1,144 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ name: "peri", + type: "xbar", + clock_primary: "clk_peri_i", // Main clock, used in sockets + other_clock_list: [] // Secondary clocks used by specific nodes + reset_primary: "rst_peri_ni", // Main reset, used in sockets + other_reset_list: [] // Secondary resets used by specific nodes + + nodes: [ + { name: "main", + type: "host", + addr_space: "hart", + clock: "clk_peri_i", + reset: "rst_peri_ni", + xbar: "true", + pipeline: false + }, + { name: "uart0", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "i2c0", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "gpio", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "spi_host0", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "spi_device", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "pwrmgr_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "rstmgr_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "clkmgr_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "pinmux_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "otp_ctrl.core", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "otp_macro.prim", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "lc_ctrl.regs", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "alert_handler", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false, + }, + { name: "sram_ctrl_ret_aon.regs", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "sram_ctrl_ret_aon.ram", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + { name: "aon_timer_aon", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false, + }, + { name: "ast", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false, + }, + { name: "soc_dbg_ctrl.core", + type: "device", + clock: "clk_peri_i", + reset: "rst_peri_ni", + pipeline: false + }, + ], + connections: { + // Note that only the following masters have access to the peri + // crossbar: rv_dm.sba, rv_core_ibex.cored, TODO:dma_ctrl + // The ibex instruction fetch port does NOT have access to these + // peripherals. + main: [ + "uart0", "i2c0" + "gpio", "spi_host0", "spi_device", + "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon", + "otp_ctrl.core", "otp_macro.prim", "lc_ctrl.regs", + "alert_handler", "ast", "sram_ctrl_ret_aon.ram", "sram_ctrl_ret_aon.regs", + "aon_timer_aon", "soc_dbg_ctrl.core" + ], + }, +} diff --git a/hw/top_darjeeling_no_ibex/dv/autogen/rstmgr_tgl_excl.cfg b/hw/top_darjeeling_no_ibex/dv/autogen/rstmgr_tgl_excl.cfg new file mode 100644 index 00000000000..68b7e74120a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/dv/autogen/rstmgr_tgl_excl.cfg @@ -0,0 +1,30 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// rstmgr_tgl_excl.cfg generated by `topgen.py` tool +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +//========================================================= +// This file contains resets that are not used at top level +//========================================================= +-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div2_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_por_io_div4_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_aon_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_lc_io_div2_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_n[0] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_sys_io_div4_n[1] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_device_n[0] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_spi_host0_n[0] +-node tb.dut*.u_rstmgr_aon.resets_o.rst_i2c0_n[0] diff --git a/hw/top_darjeeling_no_ibex/dv/autogen/tb__alert_handler_connect.sv b/hw/top_darjeeling_no_ibex/dv/autogen/tb__alert_handler_connect.sv new file mode 100644 index 00000000000..3655dcc8139 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/dv/autogen/tb__alert_handler_connect.sv @@ -0,0 +1,105 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__alert_handler_connect.sv is auto-generated by `topgen.py` tool + +assign alert_if[0].alert_tx = `CHIP_HIER.u_uart0.alert_tx_o[0]; +assign alert_if[1].alert_tx = `CHIP_HIER.u_gpio.alert_tx_o[0]; +assign alert_if[2].alert_tx = `CHIP_HIER.u_spi_device.alert_tx_o[0]; +assign alert_if[3].alert_tx = `CHIP_HIER.u_i2c0.alert_tx_o[0]; +assign alert_if[4].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0]; +assign alert_if[5].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1]; +assign alert_if[6].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[2]; +assign alert_if[7].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[3]; +assign alert_if[8].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[4]; +assign alert_if[9].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0]; +assign alert_if[10].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1]; +assign alert_if[11].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2]; +assign alert_if[12].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0]; +assign alert_if[13].alert_tx = `CHIP_HIER.u_pwrmgr_aon.alert_tx_o[0]; +assign alert_if[14].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[0]; +assign alert_if[15].alert_tx = `CHIP_HIER.u_rstmgr_aon.alert_tx_o[1]; +assign alert_if[16].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[0]; +assign alert_if[17].alert_tx = `CHIP_HIER.u_clkmgr_aon.alert_tx_o[1]; +assign alert_if[18].alert_tx = `CHIP_HIER.u_pinmux_aon.alert_tx_o[0]; +assign alert_if[19].alert_tx = `CHIP_HIER.u_aon_timer_aon.alert_tx_o[0]; +assign alert_if[20].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[0]; +assign alert_if[21].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[1]; +assign alert_if[22].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[2]; +assign alert_if[23].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[3]; +assign alert_if[24].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[4]; +assign alert_if[25].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[5]; +assign alert_if[26].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[6]; +assign alert_if[27].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[7]; +assign alert_if[28].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[8]; +assign alert_if[29].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[9]; +assign alert_if[30].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[10]; +assign alert_if[31].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[11]; +assign alert_if[32].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[12]; +assign alert_if[33].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[13]; +assign alert_if[34].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[14]; +assign alert_if[35].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[15]; +assign alert_if[36].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[16]; +assign alert_if[37].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[17]; +assign alert_if[38].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[18]; +assign alert_if[39].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[19]; +assign alert_if[40].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[20]; +assign alert_if[41].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[21]; +assign alert_if[42].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[22]; +assign alert_if[43].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[23]; +assign alert_if[44].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[24]; +assign alert_if[45].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[25]; +assign alert_if[46].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[26]; +assign alert_if[47].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[27]; +assign alert_if[48].alert_tx = `CHIP_HIER.u_soc_proxy.alert_tx_o[28]; +assign alert_if[49].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0]; +assign alert_if[50].alert_tx = `CHIP_HIER.u_rv_plic.alert_tx_o[0]; +assign alert_if[51].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0]; +assign alert_if[52].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1]; +assign alert_if[53].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0]; +assign alert_if[54].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0]; +assign alert_if[55].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[1]; +assign alert_if[56].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0]; +assign alert_if[57].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1]; +assign alert_if[58].alert_tx = `CHIP_HIER.u_keymgr_dpe.alert_tx_o[0]; +assign alert_if[59].alert_tx = `CHIP_HIER.u_keymgr_dpe.alert_tx_o[1]; +assign alert_if[60].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0]; +assign alert_if[61].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[1]; +assign alert_if[62].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0]; +assign alert_if[63].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1]; +assign alert_if[64].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0]; +assign alert_if[65].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[1]; +assign alert_if[66].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0]; +assign alert_if[67].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[1]; +assign alert_if[68].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0]; +assign alert_if[69].alert_tx = `CHIP_HIER.u_sram_ctrl_mbox.alert_tx_o[0]; +assign alert_if[70].alert_tx = `CHIP_HIER.u_rom_ctrl0.alert_tx_o[0]; +assign alert_if[71].alert_tx = `CHIP_HIER.u_rom_ctrl1.alert_tx_o[0]; +assign alert_if[72].alert_tx = `CHIP_HIER.u_dma.alert_tx_o[0]; +assign alert_if[73].alert_tx = `CHIP_HIER.u_mbx0.alert_tx_o[0]; +assign alert_if[74].alert_tx = `CHIP_HIER.u_mbx0.alert_tx_o[1]; +assign alert_if[75].alert_tx = `CHIP_HIER.u_mbx1.alert_tx_o[0]; +assign alert_if[76].alert_tx = `CHIP_HIER.u_mbx1.alert_tx_o[1]; +assign alert_if[77].alert_tx = `CHIP_HIER.u_mbx2.alert_tx_o[0]; +assign alert_if[78].alert_tx = `CHIP_HIER.u_mbx2.alert_tx_o[1]; +assign alert_if[79].alert_tx = `CHIP_HIER.u_mbx3.alert_tx_o[0]; +assign alert_if[80].alert_tx = `CHIP_HIER.u_mbx3.alert_tx_o[1]; +assign alert_if[81].alert_tx = `CHIP_HIER.u_mbx4.alert_tx_o[0]; +assign alert_if[82].alert_tx = `CHIP_HIER.u_mbx4.alert_tx_o[1]; +assign alert_if[83].alert_tx = `CHIP_HIER.u_mbx5.alert_tx_o[0]; +assign alert_if[84].alert_tx = `CHIP_HIER.u_mbx5.alert_tx_o[1]; +assign alert_if[85].alert_tx = `CHIP_HIER.u_mbx6.alert_tx_o[0]; +assign alert_if[86].alert_tx = `CHIP_HIER.u_mbx6.alert_tx_o[1]; +assign alert_if[87].alert_tx = `CHIP_HIER.u_mbx_jtag.alert_tx_o[0]; +assign alert_if[88].alert_tx = `CHIP_HIER.u_mbx_jtag.alert_tx_o[1]; +assign alert_if[89].alert_tx = `CHIP_HIER.u_mbx_pcie0.alert_tx_o[0]; +assign alert_if[90].alert_tx = `CHIP_HIER.u_mbx_pcie0.alert_tx_o[1]; +assign alert_if[91].alert_tx = `CHIP_HIER.u_mbx_pcie1.alert_tx_o[0]; +assign alert_if[92].alert_tx = `CHIP_HIER.u_mbx_pcie1.alert_tx_o[1]; +assign alert_if[93].alert_tx = `CHIP_HIER.u_soc_dbg_ctrl.alert_tx_o[0]; +assign alert_if[94].alert_tx = `CHIP_HIER.u_soc_dbg_ctrl.alert_tx_o[1]; +assign alert_if[95].alert_tx = `CHIP_HIER.u_racl_ctrl.alert_tx_o[0]; +assign alert_if[96].alert_tx = `CHIP_HIER.u_racl_ctrl.alert_tx_o[1]; +assign alert_if[97].alert_tx = `CHIP_HIER.u_ac_range_check.alert_tx_o[0]; +assign alert_if[98].alert_tx = `CHIP_HIER.u_ac_range_check.alert_tx_o[1]; diff --git a/hw/top_darjeeling_no_ibex/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling_no_ibex/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 00000000000..8eb0eed575e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,186 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `topgen.py` tool + +// This file must be `included in `hw/top_/dv/tb/tb.sv. + +`define DRIVE_CHIP_TL_HOST_IF(tl_name, inst_name, sig_name) \ + force ``tl_name``_tl_if.d2h = dut.top_darjeeling_no_ibex.u_``inst_name``.``sig_name``_i; \ + force dut.top_darjeeling_no_ibex.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.h2d; \ + force dut.top_darjeeling_no_ibex.u_``inst_name``.clk_i = 0; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +`define DRIVE_CHIP_TL_DEVICE_IF(tl_name, inst_name, sig_name) \ + force ``tl_name``_tl_if.h2d = dut.top_darjeeling_no_ibex.u_``inst_name``.``sig_name``_i; \ + force dut.top_darjeeling_no_ibex.u_``inst_name``.``sig_name``_o = ``tl_name``_tl_if.d2h; \ + force dut.top_darjeeling_no_ibex.u_``inst_name``.clk_i = 0; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +`define DRIVE_CHIP_TL_EXT_DEVICE_IF(tl_name, inst_name, port_name) \ + force ``tl_name``_tl_if.h2d = dut.u_``inst_name``.``port_name``_i; \ + force dut.u_``inst_name``.``port_name``_o = ``tl_name``_tl_if.d2h; \ + uvm_config_db#(virtual tl_if)::set(null, $sformatf("*env.%0s_agent", `"tl_name`"), "vif", \ + ``tl_name``_tl_if); + +wire clk_main; +clk_rst_if clk_rst_if_main(.clk(clk_main), .rst_n(rst_n)); +wire clk_io_div4; +clk_rst_if clk_rst_if_io_div4(.clk(clk_io_div4), .rst_n(rst_n)); + +tl_if dma__host_tl_if(clk_main, rst_n); +tl_if mbx0__sram_tl_if(clk_main, rst_n); +tl_if mbx1__sram_tl_if(clk_main, rst_n); +tl_if mbx2__sram_tl_if(clk_main, rst_n); +tl_if mbx3__sram_tl_if(clk_main, rst_n); +tl_if mbx4__sram_tl_if(clk_main, rst_n); +tl_if mbx5__sram_tl_if(clk_main, rst_n); +tl_if mbx6__sram_tl_if(clk_main, rst_n); +tl_if mbx_jtag__sram_tl_if(clk_main, rst_n); +tl_if mbx_pcie0__sram_tl_if(clk_main, rst_n); +tl_if mbx_pcie1__sram_tl_if(clk_main, rst_n); + +tl_if soc_proxy__ctn_tl_if(clk_main, rst_n); +tl_if hmac_tl_if(clk_main, rst_n); +tl_if kmac_tl_if(clk_main, rst_n); +tl_if aes_tl_if(clk_main, rst_n); +tl_if otbn_tl_if(clk_main, rst_n); +tl_if keymgr_dpe_tl_if(clk_main, rst_n); +tl_if sram_ctrl_main__ram_tl_if(clk_main, rst_n); +tl_if sram_ctrl_mbox__ram_tl_if(clk_main, rst_n); +tl_if uart0_tl_if(clk_io_div4, rst_n); +tl_if i2c0_tl_if(clk_io_div4, rst_n); +tl_if gpio_tl_if(clk_io_div4, rst_n); +tl_if spi_host0_tl_if(clk_io_div4, rst_n); +tl_if spi_device_tl_if(clk_io_div4, rst_n); +tl_if pwrmgr_aon_tl_if(clk_io_div4, rst_n); +tl_if rstmgr_aon_tl_if(clk_io_div4, rst_n); +tl_if clkmgr_aon_tl_if(clk_io_div4, rst_n); +tl_if pinmux_aon_tl_if(clk_io_div4, rst_n); +tl_if otp_ctrl__core_tl_if(clk_io_div4, rst_n); +tl_if otp_macro__prim_tl_if(clk_io_div4, rst_n); +tl_if lc_ctrl__regs_tl_if(clk_io_div4, rst_n); +tl_if alert_handler_tl_if(clk_io_div4, rst_n); +tl_if sram_ctrl_ret_aon__regs_tl_if(clk_io_div4, rst_n); +tl_if sram_ctrl_ret_aon__ram_tl_if(clk_io_div4, rst_n); +tl_if aon_timer_aon_tl_if(clk_io_div4, rst_n); +tl_if ast_tl_if(clk_io_div4, rst_n); +tl_if soc_dbg_ctrl__core_tl_if(clk_io_div4, rst_n); +tl_if mbx0__soc_tl_if(clk_main, rst_n); +tl_if mbx1__soc_tl_if(clk_main, rst_n); +tl_if mbx2__soc_tl_if(clk_main, rst_n); +tl_if mbx3__soc_tl_if(clk_main, rst_n); +tl_if mbx4__soc_tl_if(clk_main, rst_n); +tl_if mbx5__soc_tl_if(clk_main, rst_n); +tl_if mbx6__soc_tl_if(clk_main, rst_n); +tl_if mbx_pcie0__soc_tl_if(clk_main, rst_n); +tl_if mbx_pcie1__soc_tl_if(clk_main, rst_n); +tl_if racl_ctrl_tl_if(clk_main, rst_n); +tl_if ac_range_check_tl_if(clk_main, rst_n); +tl_if mbx_jtag__soc_tl_if(clk_main, rst_n); +tl_if lc_ctrl__dmi_tl_if(clk_io_div4, rst_n); +tl_if soc_dbg_ctrl__jtag_tl_if(clk_io_div4, rst_n); + +initial begin + wait (xbar_mode !== 1'bx); + if (xbar_mode) begin + // only enable assertions in xbar as many pins are unconnected + $assertoff(0, tb); + $asserton(0, tb.dut.top_darjeeling_no_ibex.u_xbar_main); + $asserton(0, tb.dut.top_darjeeling_no_ibex.u_xbar_peri); + $asserton(0, tb.dut.top_darjeeling_no_ibex.u_xbar_mbx); + $asserton(0, tb.dut.top_darjeeling_no_ibex.u_xbar_dbg); + + + // These are all zero-time: anything that consumes time go at the end. + + // bypass clkmgr, force clocks directly + force tb.dut.top_darjeeling_no_ibex.u_xbar_main.clk_main_i = clk_main; + force tb.dut.top_darjeeling_no_ibex.u_xbar_main.clk_fixed_i = clk_io_div4; + force tb.dut.top_darjeeling_no_ibex.u_xbar_peri.clk_peri_i = clk_io_div4; + force tb.dut.top_darjeeling_no_ibex.u_xbar_mbx.clk_mbx_i = clk_main; + force tb.dut.top_darjeeling_no_ibex.u_xbar_dbg.clk_dbg_i = clk_main; + force tb.dut.top_darjeeling_no_ibex.u_xbar_dbg.clk_peri_i = clk_io_div4; + + // bypass rstmgr, force resets directly + force tb.dut.top_darjeeling_no_ibex.u_xbar_main.rst_main_ni = rst_n; + force tb.dut.top_darjeeling_no_ibex.u_xbar_main.rst_fixed_ni = rst_n; + force tb.dut.top_darjeeling_no_ibex.u_xbar_peri.rst_peri_ni = rst_n; + force tb.dut.top_darjeeling_no_ibex.u_xbar_mbx.rst_mbx_ni = rst_n; + force tb.dut.top_darjeeling_no_ibex.u_xbar_dbg.rst_dbg_ni = rst_n; + force tb.dut.top_darjeeling_no_ibex.u_xbar_dbg.rst_peri_ni = rst_n; + +`ifndef GATE_LEVEL + `DRIVE_CHIP_TL_DEVICE_IF(soc_proxy__ctn, soc_proxy, ctn_tl) + `DRIVE_CHIP_TL_DEVICE_IF(hmac, hmac, tl) + `DRIVE_CHIP_TL_DEVICE_IF(kmac, kmac, tl) + `DRIVE_CHIP_TL_DEVICE_IF(aes, aes, tl) + `DRIVE_CHIP_TL_DEVICE_IF(otbn, otbn, tl) + `DRIVE_CHIP_TL_DEVICE_IF(keymgr_dpe, keymgr_dpe, tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main__ram, sram_ctrl_main, ram_tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_mbox__ram, sram_ctrl_mbox, ram_tl) + `DRIVE_CHIP_TL_HOST_IF(dma__host, dma, host_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx0__sram, mbx0, sram_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx1__sram, mbx1, sram_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx2__sram, mbx2, sram_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx3__sram, mbx3, sram_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx4__sram, mbx4, sram_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx5__sram, mbx5, sram_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx6__sram, mbx6, sram_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx_jtag__sram, mbx_jtag, sram_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx_pcie0__sram, mbx_pcie0, sram_tl_h) + `DRIVE_CHIP_TL_HOST_IF(mbx_pcie1__sram, mbx_pcie1, sram_tl_h) + `DRIVE_CHIP_TL_DEVICE_IF(uart0, uart0, tl) + `DRIVE_CHIP_TL_DEVICE_IF(i2c0, i2c0, tl) + `DRIVE_CHIP_TL_DEVICE_IF(gpio, gpio, tl) + `DRIVE_CHIP_TL_DEVICE_IF(spi_host0, spi_host0, tl) + `DRIVE_CHIP_TL_DEVICE_IF(spi_device, spi_device, tl) + `DRIVE_CHIP_TL_DEVICE_IF(pwrmgr_aon, pwrmgr_aon, tl) + `DRIVE_CHIP_TL_DEVICE_IF(rstmgr_aon, rstmgr_aon, tl) + `DRIVE_CHIP_TL_DEVICE_IF(clkmgr_aon, clkmgr_aon, tl) + `DRIVE_CHIP_TL_DEVICE_IF(pinmux_aon, pinmux_aon, tl) + `DRIVE_CHIP_TL_DEVICE_IF(otp_ctrl__core, otp_ctrl, core_tl) + `DRIVE_CHIP_TL_DEVICE_IF(otp_macro__prim, otp_macro, prim_tl) + `DRIVE_CHIP_TL_DEVICE_IF(lc_ctrl__regs, lc_ctrl, regs_tl) + `DRIVE_CHIP_TL_DEVICE_IF(alert_handler, alert_handler, tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_ret_aon__regs, sram_ctrl_ret_aon, regs_tl) + `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_ret_aon__ram, sram_ctrl_ret_aon, ram_tl) + `DRIVE_CHIP_TL_DEVICE_IF(aon_timer_aon, aon_timer_aon, tl) + `DRIVE_CHIP_TL_EXT_DEVICE_IF(ast, ast, tl) + `DRIVE_CHIP_TL_DEVICE_IF(soc_dbg_ctrl__core, soc_dbg_ctrl, core_tl) + `DRIVE_CHIP_TL_DEVICE_IF(mbx0__soc, mbx0, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx1__soc, mbx1, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx2__soc, mbx2, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx3__soc, mbx3, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx4__soc, mbx4, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx5__soc, mbx5, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx6__soc, mbx6, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx_pcie0__soc, mbx_pcie0, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(mbx_pcie1__soc, mbx_pcie1, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(racl_ctrl, racl_ctrl, tl) + `DRIVE_CHIP_TL_DEVICE_IF(ac_range_check, ac_range_check, tl) + `DRIVE_CHIP_TL_DEVICE_IF(mbx_jtag__soc, mbx_jtag, soc_tl_d) + `DRIVE_CHIP_TL_DEVICE_IF(lc_ctrl__dmi, lc_ctrl, dmi_tl) + `DRIVE_CHIP_TL_DEVICE_IF(soc_dbg_ctrl__jtag, soc_dbg_ctrl, jtag_tl) +`endif + + // And this can consume time, so they go at the end of this block. + + // Wait for a negedge of rst_n, or else we will have clock edges before + // reset, which could capture 'X values. + xbar_clk_rst_if.wait_for_reset(.wait_posedge(1'b0)); + + clk_rst_if_main.set_active(.drive_rst_n_val(0)); + clk_rst_if_main.set_freq_khz(1000000000 / 1000); + clk_rst_if_io_div4.set_active(.drive_rst_n_val(0)); + clk_rst_if_io_div4.set_freq_khz(250000000 / 1000); + + end +end + +`undef DRIVE_CHIP_TL_HOST_IF +`undef DRIVE_CHIP_TL_DEVICE_IF +`undef DRIVE_CHIP_TL_EXT_DEVICE_IF diff --git a/hw/top_darjeeling_no_ibex/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling_no_ibex/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 00000000000..79892aecf60 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,190 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `topgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"soc_proxy__ctn", '{ + '{32'h40000000, 32'h7fffffff} + }}, + '{"hmac", '{ + '{32'h21110000, 32'h21111fff} + }}, + '{"kmac", '{ + '{32'h21120000, 32'h21120fff} + }}, + '{"aes", '{ + '{32'h21100000, 32'h211000ff} + }}, + '{"otbn", '{ + '{32'h21130000, 32'h2113ffff} + }}, + '{"keymgr_dpe", '{ + '{32'h21140000, 32'h211400ff} + }}, + '{"sram_ctrl_main__ram", '{ + '{32'h10000000, 32'h1000ffff} + }}, + '{"sram_ctrl_mbox__ram", '{ + '{32'h11000000, 32'h11000fff} + }}, + '{"uart0", '{ + '{32'h30010000, 32'h3001003f} + }}, + '{"i2c0", '{ + '{32'h30080000, 32'h3008007f} + }}, + '{"gpio", '{ + '{32'h30000000, 32'h300000ff} + }}, + '{"spi_host0", '{ + '{32'h30300000, 32'h3030003f} + }}, + '{"spi_device", '{ + '{32'h30310000, 32'h30311fff} + }}, + '{"pwrmgr_aon", '{ + '{32'h30400000, 32'h3040007f} + }}, + '{"rstmgr_aon", '{ + '{32'h30410000, 32'h3041007f} + }}, + '{"clkmgr_aon", '{ + '{32'h30420000, 32'h3042003f} + }}, + '{"pinmux_aon", '{ + '{32'h30460000, 32'h304607ff} + }}, + '{"otp_ctrl__core", '{ + '{32'h30130000, 32'h30137fff} + }}, + '{"otp_macro__prim", '{ + '{32'h30140000, 32'h3014001f} + }}, + '{"lc_ctrl__regs", '{ + '{32'h30150000, 32'h301500ff} + }}, + '{"alert_handler", '{ + '{32'h30160000, 32'h301607ff} + }}, + '{"sram_ctrl_ret_aon__regs", '{ + '{32'h30500000, 32'h3050003f} + }}, + '{"sram_ctrl_ret_aon__ram", '{ + '{32'h30600000, 32'h30600fff} + }}, + '{"aon_timer_aon", '{ + '{32'h30470000, 32'h3047003f} + }}, + '{"ast", '{ + '{32'h30480000, 32'h304803ff} + }}, + '{"soc_dbg_ctrl__core", '{ + '{32'h30170000, 32'h3017001f} + }}, + '{"mbx0__soc", '{ + '{32'h01465000, 32'h0146501f} + }}, + '{"mbx1__soc", '{ + '{32'h01465100, 32'h0146511f} + }}, + '{"mbx2__soc", '{ + '{32'h01465200, 32'h0146521f} + }}, + '{"mbx3__soc", '{ + '{32'h01465300, 32'h0146531f} + }}, + '{"mbx4__soc", '{ + '{32'h01465400, 32'h0146541f} + }}, + '{"mbx5__soc", '{ + '{32'h01465500, 32'h0146551f} + }}, + '{"mbx6__soc", '{ + '{32'h01496000, 32'h0149601f} + }}, + '{"mbx_pcie0__soc", '{ + '{32'h01460100, 32'h0146011f} + }}, + '{"mbx_pcie1__soc", '{ + '{32'h01460200, 32'h0146021f} + }}, + '{"racl_ctrl", '{ + '{32'h01461f00, 32'h01461fff} + }}, + '{"ac_range_check", '{ + '{32'h01464000, 32'h014643ff} + }}, + '{"mbx_jtag__soc", '{ + '{32'h00002200, 32'h0000221f} + }}, + '{"lc_ctrl__dmi", '{ + '{32'h00003000, 32'h00003fff} + }}, + '{"soc_dbg_ctrl__jtag", '{ + '{32'h00002300, 32'h0000231f} + }}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"dma__host", 0, '{ + "sram_ctrl_main__ram", + "sram_ctrl_mbox__ram", + "aes", + "hmac", + "otbn", + "keymgr_dpe", + "kmac", + "soc_proxy__ctn", + "uart0", + "i2c0", + "gpio", + "spi_host0", + "spi_device", + "pwrmgr_aon", + "rstmgr_aon", + "clkmgr_aon", + "pinmux_aon", + "otp_ctrl__core", + "otp_macro__prim", + "lc_ctrl__regs", + "alert_handler", + "ast", + "sram_ctrl_ret_aon__ram", + "sram_ctrl_ret_aon__regs", + "aon_timer_aon", + "soc_dbg_ctrl__core"}} + , + '{"mbx0__sram", 1, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx1__sram", 2, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx2__sram", 3, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx3__sram", 4, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx4__sram", 5, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx5__sram", 6, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx6__sram", 7, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_jtag__sram", 8, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie0__sram", 9, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie1__sram", 10, '{ + "sram_ctrl_mbox__ram"}} +}; diff --git a/hw/top_darjeeling_no_ibex/dv/autogen/xbar_tgl_excl.cfg b/hw/top_darjeeling_no_ibex/dv/autogen/xbar_tgl_excl.cfg new file mode 100644 index 00000000000..526adc30c51 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/dv/autogen/xbar_tgl_excl.cfg @@ -0,0 +1,196 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_tgl_excl.cfg generated by `topgen.py` tool + +// [UNSUPPORTED] Exclude unused TL port signals at all hierarchies, wherever port toggle coverage is +// enabled. Exercising these reserved signals will result in assertion errors thrown by the design. +-node tb.dut*.u_* *tl_*.a_param +-node tb.dut*.u_* *tl_*.a_user.rsvd +-node tb.dut*.u_* *tl_*.d_param +-node tb.dut*.u_* *tl_*.d_opcode[2:1] +-node tb.dut*.u_* *tl_*.a_source[7:6] +-node tb.dut*.u_* *tl_*.d_source[7:6] +-node tb.dut.top_darjeeling_no_ibex *tl_*.a_param +-node tb.dut.top_darjeeling_no_ibex *tl_*.a_user.rsvd +-node tb.dut.top_darjeeling_no_ibex *tl_*.d_param +-node tb.dut.top_darjeeling_no_ibex *tl_*.d_opcode[2:1] +-node tb.dut.top_darjeeling_no_ibex *tl_*.a_source[7:6] +-node tb.dut.top_darjeeling_no_ibex *tl_*.d_source[7:6] + +// [LOW_RISK] Exclude the full TL a_address signal on all pass-through hierarchies. We instead look +// at the full coverage of this signal directly at the host or at the device. +-node tb.dut.top_darjeeling_no_ibex *tl_*.a_address +-node tb.dut.top_darjeeling_no_ibex.u_xbar_* tl_*.a_address + +// [UNR] Exclude unused address bits based on IP address range. It is not possible to cover this. +-node tb.dut*.u_soc_proxy ctn_tl_*i.a_address[31:31] +-node tb.dut*.u_hmac tl_*i.a_address[15:13] +-node tb.dut*.u_hmac tl_*i.a_address[19:17] +-node tb.dut*.u_hmac tl_*i.a_address[23:21] +-node tb.dut*.u_hmac tl_*i.a_address[28:25] +-node tb.dut*.u_hmac tl_*i.a_address[31:30] +-node tb.dut*.u_kmac tl_*i.a_address[16:12] +-node tb.dut*.u_kmac tl_*i.a_address[19:18] +-node tb.dut*.u_kmac tl_*i.a_address[23:21] +-node tb.dut*.u_kmac tl_*i.a_address[28:25] +-node tb.dut*.u_kmac tl_*i.a_address[31:30] +-node tb.dut*.u_aes tl_*i.a_address[19:8] +-node tb.dut*.u_aes tl_*i.a_address[23:21] +-node tb.dut*.u_aes tl_*i.a_address[28:25] +-node tb.dut*.u_aes tl_*i.a_address[31:30] +-node tb.dut*.u_otbn tl_*i.a_address[19:18] +-node tb.dut*.u_otbn tl_*i.a_address[23:21] +-node tb.dut*.u_otbn tl_*i.a_address[28:25] +-node tb.dut*.u_otbn tl_*i.a_address[31:30] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[17:8] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[19:19] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[23:21] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[28:25] +-node tb.dut*.u_keymgr_dpe tl_*i.a_address[31:30] +-node tb.dut*.u_sram_ctrl_main ram_tl_*i.a_address[27:16] +-node tb.dut*.u_sram_ctrl_main ram_tl_*i.a_address[31:29] +-node tb.dut*.u_sram_ctrl_mbox ram_tl_*i.a_address[23:12] +-node tb.dut*.u_sram_ctrl_mbox ram_tl_*i.a_address[27:25] +-node tb.dut*.u_sram_ctrl_mbox ram_tl_*i.a_address[31:29] +-node tb.dut*.u_uart0 tl_*i.a_address[15:6] +-node tb.dut*.u_uart0 tl_*i.a_address[27:17] +-node tb.dut*.u_uart0 tl_*i.a_address[31:30] +-node tb.dut*.u_i2c0 tl_*i.a_address[18:7] +-node tb.dut*.u_i2c0 tl_*i.a_address[27:20] +-node tb.dut*.u_i2c0 tl_*i.a_address[31:30] +-node tb.dut*.u_gpio tl_*i.a_address[27:8] +-node tb.dut*.u_gpio tl_*i.a_address[31:30] +-node tb.dut*.u_spi_host0 tl_*i.a_address[19:6] +-node tb.dut*.u_spi_host0 tl_*i.a_address[27:22] +-node tb.dut*.u_spi_host0 tl_*i.a_address[31:30] +-node tb.dut*.u_spi_device tl_*i.a_address[15:13] +-node tb.dut*.u_spi_device tl_*i.a_address[19:17] +-node tb.dut*.u_spi_device tl_*i.a_address[27:22] +-node tb.dut*.u_spi_device tl_*i.a_address[31:30] +-node tb.dut*.u_pwrmgr_aon tl_*i.a_address[21:7] +-node tb.dut*.u_pwrmgr_aon tl_*i.a_address[27:23] +-node tb.dut*.u_pwrmgr_aon tl_*i.a_address[31:30] +-node tb.dut*.u_rstmgr_aon tl_*i.a_address[15:7] +-node tb.dut*.u_rstmgr_aon tl_*i.a_address[21:17] +-node tb.dut*.u_rstmgr_aon tl_*i.a_address[27:23] +-node tb.dut*.u_rstmgr_aon tl_*i.a_address[31:30] +-node tb.dut*.u_clkmgr_aon tl_*i.a_address[16:6] +-node tb.dut*.u_clkmgr_aon tl_*i.a_address[21:18] +-node tb.dut*.u_clkmgr_aon tl_*i.a_address[27:23] +-node tb.dut*.u_clkmgr_aon tl_*i.a_address[31:30] +-node tb.dut*.u_pinmux_aon tl_*i.a_address[16:11] +-node tb.dut*.u_pinmux_aon tl_*i.a_address[21:19] +-node tb.dut*.u_pinmux_aon tl_*i.a_address[27:23] +-node tb.dut*.u_pinmux_aon tl_*i.a_address[31:30] +-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[15:15] +-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[19:18] +-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[27:21] +-node tb.dut*.u_otp_ctrl core_tl_*i.a_address[31:30] +-node tb.dut*.u_otp_macro prim_tl_*i.a_address[17:5] +-node tb.dut*.u_otp_macro prim_tl_*i.a_address[19:19] +-node tb.dut*.u_otp_macro prim_tl_*i.a_address[27:21] +-node tb.dut*.u_otp_macro prim_tl_*i.a_address[31:30] +-node tb.dut*.u_lc_ctrl regs_tl_*i.a_address[15:8] +-node tb.dut*.u_lc_ctrl regs_tl_*i.a_address[17:17] +-node tb.dut*.u_lc_ctrl regs_tl_*i.a_address[19:19] +-node tb.dut*.u_lc_ctrl regs_tl_*i.a_address[27:21] +-node tb.dut*.u_lc_ctrl regs_tl_*i.a_address[31:30] +-node tb.dut*.u_alert_handler tl_*i.a_address[16:11] +-node tb.dut*.u_alert_handler tl_*i.a_address[19:19] +-node tb.dut*.u_alert_handler tl_*i.a_address[27:21] +-node tb.dut*.u_alert_handler tl_*i.a_address[31:30] +-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[19:6] +-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[21:21] +-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[27:23] +-node tb.dut*.u_sram_ctrl_ret_aon regs_tl_*i.a_address[31:30] +-node tb.dut*.u_sram_ctrl_ret_aon ram_tl_*i.a_address[20:12] +-node tb.dut*.u_sram_ctrl_ret_aon ram_tl_*i.a_address[27:23] +-node tb.dut*.u_sram_ctrl_ret_aon ram_tl_*i.a_address[31:30] +-node tb.dut*.u_aon_timer_aon tl_*i.a_address[15:6] +-node tb.dut*.u_aon_timer_aon tl_*i.a_address[21:19] +-node tb.dut*.u_aon_timer_aon tl_*i.a_address[27:23] +-node tb.dut*.u_aon_timer_aon tl_*i.a_address[31:30] +-node tb.dut*.u_ast tl_*i.a_address[18:10] +-node tb.dut*.u_ast tl_*i.a_address[21:20] +-node tb.dut*.u_ast tl_*i.a_address[27:23] +-node tb.dut*.u_ast tl_*i.a_address[31:30] +-node tb.dut*.u_soc_dbg_ctrl core_tl_*i.a_address[15:5] +-node tb.dut*.u_soc_dbg_ctrl core_tl_*i.a_address[19:19] +-node tb.dut*.u_soc_dbg_ctrl core_tl_*i.a_address[27:21] +-node tb.dut*.u_soc_dbg_ctrl core_tl_*i.a_address[31:30] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[11:5] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx0 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[7:5] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[11:9] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx1 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[8:5] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[11:10] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx2 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[7:5] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[11:10] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx3 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[9:5] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[11:11] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx4 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[7:5] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[9:9] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[11:11] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[13:13] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[16:15] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx5 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[12:5] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[15:15] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[18:17] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[21:20] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx6 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[7:5] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[16:9] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx_pcie0 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[8:5] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[16:10] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[21:19] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[23:23] +-node tb.dut*.u_mbx_pcie1 soc_tl_*i.a_address[31:25] +-node tb.dut*.u_racl_ctrl tl_*i.a_address[16:13] +-node tb.dut*.u_racl_ctrl tl_*i.a_address[21:19] +-node tb.dut*.u_racl_ctrl tl_*i.a_address[23:23] +-node tb.dut*.u_racl_ctrl tl_*i.a_address[31:25] +-node tb.dut*.u_ac_range_check tl_*i.a_address[13:10] +-node tb.dut*.u_ac_range_check tl_*i.a_address[16:15] +-node tb.dut*.u_ac_range_check tl_*i.a_address[21:19] +-node tb.dut*.u_ac_range_check tl_*i.a_address[23:23] +-node tb.dut*.u_ac_range_check tl_*i.a_address[31:25] +-node tb.dut*.u_mbx_jtag soc_tl_*i.a_address[8:5] +-node tb.dut*.u_mbx_jtag soc_tl_*i.a_address[12:10] +-node tb.dut*.u_mbx_jtag soc_tl_*i.a_address[31:14] +-node tb.dut*.u_lc_ctrl dmi_tl_*i.a_address[31:14] +-node tb.dut*.u_soc_dbg_ctrl jtag_tl_*i.a_address[7:5] +-node tb.dut*.u_soc_dbg_ctrl jtag_tl_*i.a_address[12:10] +-node tb.dut*.u_soc_dbg_ctrl jtag_tl_*i.a_address[31:14] diff --git a/hw/top_darjeeling_no_ibex/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_darjeeling_no_ibex/dv/env/autogen/chip_env_pkg__params.sv new file mode 100644 index 00000000000..07e88a335f1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/dv/env/autogen/chip_env_pkg__params.sv @@ -0,0 +1,108 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Generated by topgen.py + +parameter uint NUM_ALERTS = 99; +parameter string LIST_OF_ALERTS[NUM_ALERTS] = { + "uart0_fatal_fault", + "gpio_fatal_fault", + "spi_device_fatal_fault", + "i2c0_fatal_fault", + "otp_ctrl_fatal_macro_error", + "otp_ctrl_fatal_check_error", + "otp_ctrl_fatal_bus_integ_error", + "otp_ctrl_fatal_prim_otp_alert", + "otp_ctrl_recov_prim_otp_alert", + "lc_ctrl_fatal_prog_error", + "lc_ctrl_fatal_state_error", + "lc_ctrl_fatal_bus_integ_error", + "spi_host0_fatal_fault", + "pwrmgr_aon_fatal_fault", + "rstmgr_aon_fatal_fault", + "rstmgr_aon_fatal_cnsty_fault", + "clkmgr_aon_recov_fault", + "clkmgr_aon_fatal_fault", + "pinmux_aon_fatal_fault", + "aon_timer_aon_fatal_fault", + "soc_proxy_fatal_alert_intg", + "soc_proxy_fatal_alert_external_0", + "soc_proxy_fatal_alert_external_1", + "soc_proxy_fatal_alert_external_2", + "soc_proxy_fatal_alert_external_3", + "soc_proxy_fatal_alert_external_4", + "soc_proxy_fatal_alert_external_5", + "soc_proxy_fatal_alert_external_6", + "soc_proxy_fatal_alert_external_7", + "soc_proxy_fatal_alert_external_8", + "soc_proxy_fatal_alert_external_9", + "soc_proxy_fatal_alert_external_10", + "soc_proxy_fatal_alert_external_11", + "soc_proxy_fatal_alert_external_12", + "soc_proxy_fatal_alert_external_13", + "soc_proxy_fatal_alert_external_14", + "soc_proxy_fatal_alert_external_15", + "soc_proxy_fatal_alert_external_16", + "soc_proxy_fatal_alert_external_17", + "soc_proxy_fatal_alert_external_18", + "soc_proxy_fatal_alert_external_19", + "soc_proxy_fatal_alert_external_20", + "soc_proxy_fatal_alert_external_21", + "soc_proxy_fatal_alert_external_22", + "soc_proxy_fatal_alert_external_23", + "soc_proxy_recov_alert_external_0", + "soc_proxy_recov_alert_external_1", + "soc_proxy_recov_alert_external_2", + "soc_proxy_recov_alert_external_3", + "sram_ctrl_ret_aon_fatal_error", + "rv_plic_fatal_fault", + "aes_recov_ctrl_update_err", + "aes_fatal_fault", + "hmac_fatal_fault", + "kmac_recov_operation_err", + "kmac_fatal_fault_err", + "otbn_fatal", + "otbn_recov", + "keymgr_dpe_recov_operation_err", + "keymgr_dpe_fatal_fault_err", + "csrng_recov_alert", + "csrng_fatal_alert", + "entropy_src_recov_alert", + "entropy_src_fatal_alert", + "edn0_recov_alert", + "edn0_fatal_alert", + "edn1_recov_alert", + "edn1_fatal_alert", + "sram_ctrl_main_fatal_error", + "sram_ctrl_mbox_fatal_error", + "rom_ctrl0_fatal", + "rom_ctrl1_fatal", + "dma_fatal_fault", + "mbx0_fatal_fault", + "mbx0_recov_fault", + "mbx1_fatal_fault", + "mbx1_recov_fault", + "mbx2_fatal_fault", + "mbx2_recov_fault", + "mbx3_fatal_fault", + "mbx3_recov_fault", + "mbx4_fatal_fault", + "mbx4_recov_fault", + "mbx5_fatal_fault", + "mbx5_recov_fault", + "mbx6_fatal_fault", + "mbx6_recov_fault", + "mbx_jtag_fatal_fault", + "mbx_jtag_recov_fault", + "mbx_pcie0_fatal_fault", + "mbx_pcie0_recov_fault", + "mbx_pcie1_fatal_fault", + "mbx_pcie1_recov_fault", + "soc_dbg_ctrl_fatal_fault", + "soc_dbg_ctrl_recov_ctrl_update_err", + "racl_ctrl_fatal_fault", + "racl_ctrl_recov_ctrl_update_err", + "ac_range_check_recov_ctrl_update_err", + "ac_range_check_fatal_fault" +}; diff --git a/hw/top_darjeeling_no_ibex/ip/ast/BUILD b/hw/top_darjeeling_no_ibex/ip/ast/BUILD new file mode 100644 index 00000000000..3113b96ac0e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/BUILD @@ -0,0 +1,20 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]) + [ + "//hw/top_darjeeling/ip/ast/data:all_files", + ], +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.png", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip/ast/README.md b/hw/top_darjeeling_no_ibex/ip/ast/README.md new file mode 100644 index 00000000000..6996a799030 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/README.md @@ -0,0 +1,1165 @@ +# Analog Sensor Top Technical Specification +# Overview + +AST, also known as the analog sensor top, is the OpenTitan analog and +security companion. Within AST are various analog functions (such as +clocks, regulators, random number generators) needed to make the device +function, as well as physical security sensors necessary to protect the +device from physical attacks or manipulation. + +At a high level, AST communicates with a number of OpenTitan comportable +modules. See diagram below. + +![Analog Sensor Top Diagram](./doc/top_diagram.png) + +In the following sections, each family of connection is briefly +described and explained. Note, the analog connections to AST are not +shown in the diagram, but will be explained as well. + +# Interface Signals Table + +## Table notes + +### Signal naming conventions used in this document + +It complies with OpenTitan +[names](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#naming) +and +[suffixes](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#suffixes) +with some augmentations. + +- Clock signals start with clk_* + +- Inputs and outputs are marked with *_i/o + +- Analog signals are marked with *_a + +- Non-core level signals are marked with *_h + +- Dual and negative polarity signals are marked with *_p/n + +### Clock domains column + +- sys - system clock, mainly used for high performance and security + modules. Up to 100MHz + +- io - peripheral clock source, mainly used for peripherals and I/O + related functionality. Up to 96MHz (divided by 4 by the clock + manager) + +- usb - USB module source clock. 48MHz + +- aon - Always-on domain clock. The only active clock while chip is in + deep-sleep power state, 200KHz + +- async - when listed as async, it means it does not matter what domain + drives the signal + +- Input clocks: Each functional interface has a dedicated clock named + after the interface. + + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Signal Name & AffiliationI/O

Width/

+

Type/

+

Struct

Clock DomainDescription
Power Supplies
VCCI

VCC is the main power supply. It is driven from an external +source and is used to power the internal VCMAIN and VCAON power +domains.

+

VCC must always be present when the device is functioning; VCC is +also used to power a number of pads that must be always on when the +device is functioning.

AVCCIAnalog blocks power supply. AVCC and AGND are analog supply and +ground signals for the AST analog functions. They mainly serve for ADC +and USB clock functionality. AVCC is expected to be driven by the same +voltage regulator and have similar power availability as VCC. AVCC and +AGND have dedicated package balls/pins. In the future, package pins +sharing with VCC and GND may be considered based on post-silicon test +results.
VCMAINOMain core power, driven by internal capless voltage regulator
VCAONOCore voltage power for always-on domain (same voltage range as +VCMAIN)
VIOAIIO supply, powering a set of pads. Unlike VCC, the IO supplies can +be turned off by external components and the device will continue to +function, the unpowered pads however, become inoperable.
VIOBISame as VIOA, but for a different set of pads.
GNDIGround
AGNDIAnalog ground (see AVCC for further details)
Power Control and Reset
otp_power_seq_iI2asyncContains the power sequencing signals coming from the OTP +macro.
otp_power_seq_h_oO2asyncContains the power sequencing signals going to the OTP macro +(VCC domain).
flash_power_down_h_oO1asyncConnected to flash (VCC domain). Used for flash +power management.
flash_power_ready_h_oO1asyncConnected to flash (VCC domain). Used for flash +power management.

vcmain_pok

+

(aka vcmain_pok_o)

Oast_pwstasyncMain core power-exist indication. Used by the OpenTitan power +manager to determine the state of the main digital supply during power +up and power down sequencing.

vcaon_pok

+

(aka vcaon_pok_o)

Oast_pwstasyncAlways-on power-exist indication. Used by the OpenTitan power +manager for power-on reset root.

vioa_pok

+

(aka vioa_pok_o)

Oast_pwstasyncVIOA power-exist indications. Used as a power-OK status signal.

viob_pok

+

(aka viob_pok_o)

Oast_pwstasyncVIOB power-exist indication. Used as a power-OK status signal.
por_niI1asyncPower on reset input signal to AST. See Resets section for further details
main_pd_niI1aonPower down enable for main core power
+0: main core power is down (deep-sleep state)
+1: main core power is up
+It may take up to 200 uS from this signal transition to power switching +completion by AST (not including boot time and so). Note that flash must +be prepared for power down before this signal is asserted.
main_env_iso_en_iI1aon

Preliminary indication of VCMAIN isolation signal (main_iso_en) +assertion. It is used by AST logic to latch interface signals which may +no longer be valid after main_iso_en is active. This signal must be set +at least 30ns before main_iso_en is active and must remain active at +least 30ns after main_iso_en is no longer active.

+

Note that main_iso_en itself asserts ahead of main_pd_ni. ie, the +pwrmgr will set this signal to '1' before requesting the power be turned +off. Similar, on power-on, the isolation is only released after power is +restored and all powered off modules have been reset.

ast_init_done_oOmubi4tlulWhen set, it indicates that the AST initialization was performed. +Note that this signal may not be set while the chip is in TEST* or RMA +lifecycle states.
Clock Outputs
clk_src_sys_oO1sys100 MHz clock with jitter (main clock domain). Used as the main +system clock.
clk_src_sys_val_oO1asyncSystem clock valid. Used as "ack" signals for the power +manager
clk_src_sys_en_iI1aonSystem clock enable.
clk_src_sys_jen_iImubi4asyncSystem clock jitter enable
clk_src_aon_oO1aon200 KHz clock for always-on domain.
clk_src_aon_val_oO1asyncaon clock valid
clk_src_usb_oO1usb48 MHz clock for USB. To comply with USB full speed clock +specification, it supports frequency accuracy of +/-2500 ppm when +usb_ref_pulse_i is available and +/-3% otherwise. It may take up to 50 +ms for this clock to reach the accuracy target from the time +'usb_ref_pulse_i' is available. USB clock calibration interface is +further detailed here.
clk_src_usb_val_oO1asyncUSB clock valid
clk_src_usb_en_iI1aonUSB clock enable
usb_ref_pulse_iI1usbUSB reference pulse +/-500ppm. When valid, it is expected to pulse +for one usb clock cycle every 1ms.
usb_ref_val_iI1usbUSB reference valid. This bit serves as a valid signal for the +usb_ref_pulse_i signal. It is set to 1 after the first valid +usb_ref_pulse_i event is detected and remains high as long as +usb_ref_pulse_i continues to behave as expected (per usb_ref_pulse +description). Once usb_ref_pulse deviates from its expected behavior, +usb_ref_val_i immediately negates to 0 and remains 0 until after the +next valid usb_ref_val pulse.
clk_src_io_oO1io96 MHz clock with +/-3% frequency accuracy. Used for peripherals +that require a fixed frequency, for example SPI and UART
clk_src_io_val_oO1asyncI/O and timer clock valid. Used as "ack" signals for the Power +manager.
clk_src_io_en_iI1aonI/O and timer clock enable
clk_src_io_48m_oOmubi4aonClock frequency indicator. When set, it indicates that the +clk_src_io_o's frequency is 48 MHz; otherwise, it is 96 MHz.
Clock & Reset Inputs
clk_ast_adc_iI1adcADC interface clock input
clk_ast_rng_iI1rngRNG interface clock input
clk_ast_usb_iI1usbUSB reference interface clock input
clk_ast_es_iI1esEntropy source interface clock input
clk_ast_alert_iI1alertAlert interface clock input
clk_ast_tlul_iI1tlulTLUL bus interface clock input
rst_ast_adc_niI1adcADC interface reset (active low)
rst_ast_rng_niI1rngRNG interface reset (active low)
rst_ast_usb_niI1usbUSB reference interface reset (active low)
rst_ast_es_niI1esEntropy source interface reset (active low)
rst_ast_alert_niI1alertAlert interface interface reset (active low)
rst_ast_tlul_niI1tlulTLUL bus reference interface reset (active low)
Register Access Interface
tlulI/Otl_*tlulTLUL bus interface. Mainly used for configuration, calibration and +trimming. At boot time, data is copied from non-volatile storage into +AST registers by the SW boot entity. This interface has no further use +beyond this point. Runtime interaction with AST is performed by other +signals as described in this document.
Analog modules
adc_a0_aiIawireasyncADC analog input channels 0 to be measured.
+Signal type is awire (see ana_pkg.sv)
adc_a1_aiIawireasyncADC analog input channels 1 to be measured.
+Signal type is awire (see ana_pkg.sv)
adc_d_oO10adcADC digital data
adc_chnsel_iI2adcADC input channel select (one hot). No more than one channel should +be selected at a time. Any change in 'adc_chnsel_i' value must go +through all '0'. Changing 'adc_chnsel_i' from '0' value to non-'0' value +starts an ADC conversion.
adc_d_val_oO1adcADC digital data valid
adc_pd_iI1adcADC power down - for saving power during deep-sleep state between +measurements. When this signal is high, ADC module is in off state, +otherwise, it is in active state. For further description about adc_pd_i +usage, see ADC module description below.
entropy_req_oOedn_reqesRequest entropy from EDN
entropy_rsp_iIedn_rspesEDN entropy request acknowledgement and data.
rng_en_iI1rngInput from controller to enable RNG
rng_fips_iI1rngIndicates that the AST RNG module is requested to output FIPS +SP-800-90B grade RNG bits. This may, but not necessarily affect +bit-rate. This bit is a placeholder. The use of this signal inside AST +is TBD.
rng_val_oO1rngRNG bit valid. This is a per-transaction valid. rng_b_o can be +sampled whenever this bit is high.
rng_b_oO4rngRNG digital bit streams. The downstream controller of this signal +should sample the rng_b_o whenever rng_val_o is high.
Countermeasures and Alerts
alert_req_oOast_alert_reqalertAlert events. There are 11 such events. The alerts are associated +with countermeasures like Active shield, clock glitch detector, voltage +glitch detector, temperature sensor, and others.
alert_rsp_iIast_alert_rspalertThis structure contains acknowledge signals and force-trigger by +software signals for each alert event. The acknowledge signals are +assumed to be synchronous pulses.
Trimming Test and Debug
dft_scan_md_oOmubi4Scan mode indication signal. Controllable only when DFT features are +enabled (Test and RMA states). Otherwise, these signals are grounded to +0.
scan_shift_en_oO1Scan shift enable
scan_reset_noO1Scan reset
clk_ast_ext_iI1async

External clock. While AST generates most of its clocks on-die, it +still needs an external clock for clock calibration and first flash/OTP +programming.

+

Clock calibration: AST clock sources are inaccurate by default and +must be calibrated prior to use. The results of the calibration are +stored in OTP and reloaded by software upon system boot.

+

First Flash / OTP programming: AST clock sources are inaccurate by +default and may be out of range for initial flash and OTP programming. +In this situation, an external clock may be required for initial +programming such that a software image can be loaded to calibrate clocks +and advance life +cycle.

dft_strap_test_iIdft_strap_test_reqasyncStrap inputs for DFT selection
flash_bist_en_oOmubi4Flash BIST enable
vcc_supp_iI1asyncVCC Supply Test. (supply indication for DV purposes). In FPGA +Verilog view, the respective POK signal follows this signal. In other +Verilog views this signal should be connected to constant '1' and will +be disconnected inside the AST.
vcmain_supp_iI1asyncVCMAIN Supply Test. (supply indication for DV purposes). In FPGA +Verilog view, the respective POK signal follows this signal. In other +Verilog views this signal should be connected to constant '1' and will +be disconnected inside the AST.
vcaon_supp_iI1asyncVCAON Supply Test. (supply indication for DV purposes). In FPGA +Verilog view, the respective POK signal follows this signal. In other +Verilog views this signal should be connected to constant '1' and will +be disconnected inside the AST.
vioa_supp_iI1asyncVIOA Supply Test. (supply indication for DV purposes). In FPGA +Verilog view, the respective POK signal follows this signal. In other +Verilog views this signal should be connected to constant '1' and will +be disconnected inside the AST.
viob_supp_iI1asyncVIOB Supply Test. (supply indication for DV purposes). In FPGA +Verilog view, the respective POK signal follows this signal. In other +Verilog views this signal should be connected to constant '1' and will +be disconnected inside the AST.
ast2pad_t0_ao, ast2pad_t1_aoI/OasyncAnalog debug signals. These signals should be connected directly to +chip PADs. They can share PADs with functional signals but when they are +used for their analog debug function, the functional I/O must be in +tri-state.

dpram_rmf_o,

+

dpram_rml_o,

+

spram_rm_o,

+

sprgf_rm_o,

+

sprom_rm_o

Odpm_rmasyncRAM/ROM Read-write Margin Trimming
padmux2ast_iI6asyncDigital debug input signals (routed to pin mux). These signals are +controllable only when DFT features are enabled (Test and RMA states). +Otherwise, these signals are grounded to 0.
ast2padmux_oO9asyncDigital debug output signals (routed to pin mux). These signals are +only outputted when DFT features are enabled (Test and RMA states). +Otherwise, these signals are grounded to 0.
usb_io_pu_cal_oO20asyncUSB I/O calibration and trimming
io_clk_byp_req_iImubi4async

External clock mux override request for OTP bootstrap purposes. +AST responds to the request by setting io_clk_byp_ack_o to 'On'. When +this bit is set and ack was received, clk_ast_ext_i serves as the io_clk +clock root.

+

Note: When 'On' (after ack), clk_src_io_o clock max frequency is +limited to 50 MHz

io_clk_byp_ack_oOmubi4asyncAST response to io_clk_byp_req_i. The ack is set to 'On' after clock +switching function is performed.
all_clk_byp_req_iImubi4async

External clock mux override request for OTP bootstrap purposes. +AST responds to the request by setting io_clk_byp_ack_o to 'On'. When +this bit is set and ack was received, clk_ast_ext_i serves as the io_clk +clock root.

+

Note: When 'On' (after ack), clk_src_io_o clock max frequency is +limited to 50 MHz

all_clk_byp_ack_oOmubi4asyncAST response to io_clk_byp_req_i. The ack is set to 'On' after clock +switching function is performed.
ext_freq_is_96m_iImubi4asyncExternal clock frequency indication to AST. When set, it indicates +that the external clock is 96MHz.
lc_dft_en_iIlc_txasync

DFT enable

fla_obs_iI8asyncFlash observe bus for debug
otp_bos_iI8asyncOTP observe bus for debug
usb_obs_iI1asyncUSB differential receiver output observe for debug
otm_obs_iI8asyncOpenTitan modules observe bus for debug (optional)
obs_ctrl_oOast_obs_ctrlasyncObservability control structure. It contains observability module +selection, signal group selection and enable logic. Open source modules +may choose to use this infrastructure for selecting and gating +observability signals to be driven into otm_obs_i bus. Whether to +actually use this interface or not for open source modules observability +is a project decision.
sns_clks_iIclkmgr_outasyncClocks observability
sns_rst_iIrstmgr_out_tasyncResets observability
sns_spi_ext_clk_iI1asyncSPI external clock observability
+ +# Interfaces Description Note + +The information below augments the [Interface Signals +Table](#interface-signals-table). For further details, see the +corresponding signals description in the table. + +# Power Connectivity + +Note: Power signals may not appear in the verilog files, however, they +are described for completeness. + +## External Supplies + +AST has four external power supplies VCC, AVCC, VIOA and VIOB. VCC is +the main supply, AVCC is an analog VCC supply. VIOA and VIOB are two +additional I/O supplies. + +## Core Supplies + +The core supplies are generated from the VCC supply. There are two core +supply domains: VCMAIN and VCAON. VCAON, as its name implies, is the +always-on core supply used to power components that stay active during +device low power states. VCMAIN on the other hand, powers most chip +logic such as RISC-V processor, crypto modules and almost all memories +and peripherals. The VCMAIN supply can be turned off when requested, +VCAON on the other hand, is active whenever VCC is active. AST core +logic is powered by VCAON. + +# Power Control and Reset + +## Core Power Control and Indication + +VCMAIN is the only supply that can be directly influenced by OpenTitan. +The power manager can request VCMAIN to shutdown through main_pd_ni. The +state of VCMAIN is reflected by the vcmain_pok_o signal. + +## IO Power Indication + +IO power state is reflected to OpenTitan by vioa_pok_o and viob_pok_o +signals + +## Main (VCC) Power Detection and Flash Protection + +On VCC power-down detection, 'flash_power_ready_h_o', is +immediately negated. In addition, SYS clock, IO clock and USB clock are +stopped. This means that negation of the VCC supply always triggers the +flash brown-out (BOR) protection circuitry. + +When entering deep-sleep mode, 'flash_power_down_h_o' is +asserted before negating VCMAIN until VCMAIN is back up. + +## Resets + +The AST supports the generation of the root reset for the reset manager. +It is driven by 'vcaon_pok_o' which is generated inside AST. +The 'vcaon_pok_o' is activated when the following conditions +are met: VCC is detected, internal voltage regulator is active and +'por_ni' reset input is inactive. 'por_ni' is +driven by an external chip reset pin. The following table and diagrams +describe the AST sub-modules resets. + +| **Components** | **Reset by** | **Comments** | +|--------------------------------------------------------------|--------------------------|------------------------------------------------------------------------------------------------------------------------------------------| +| Regulators, 'power-OK' logic and always-on clock | self-start / vcaon_pok_o | These circuits come to life shortly after VCC crosses its detection threshold. vcaon_pok_o serves as their register configuration reset. | +| System/USB/IO clock generators | vcmain_pok_o | vcmain_pok_o is also fed by vcaon_pok_o and por_ni. | +| Interface functions | Input reset | Per the corresponding interface [clock domain reset input](#clock-and-reset-inputs). | + +# Clock Outputs + +AST generates four clocks: System clock, IO clock, USB clock and +Always-on clock. Most clocks have 'enable' inputs and a +corresponding 'valid' output. When the enable is +de-asserted, the corresponding clock stops and valid is dropped to 0. +When the enable is asserted, the clocks begin outputting in a +'glitchless' manner and the valid is raised to 1. Unless +noted otherwise, clocks duty cycle is 50% +/-5%. At boot time, clocks +start toggling at a different (typically slower) frequency than their +target. They are configured to their target frequency by the ROM code. +Once configured, their frequency is maintained within +/-3% of their +target as long as the chip remains in its intended operating conditions +until the next boot. + +The OpenTitan power and clock managers are responsible for manipulating +the enables and observing the valids to know when clocks can be safely +released to the system. + +## USB Clock Calibration + +The USB clock requires an accuracy that cannot be achieved by the AST +clocks natively. As a result, information from USB frames are used to +[calibrate the +clock](../../../ip/usbdev/README.md#clocking). + +# Clock and Reset Inputs + +The root clocks and resets are generated inside AST. However, the clocks +go through gating and optional division in the OpenTitan top level and +propagate back into AST as feedback clocks, each with associated +synchronized reset de-assertion to ensure it can synchronize with the +various comportable modules. The input resets are used for the different +AST interface functions. For further details about AST resets, see +[Resets](#resets) section. + +Note: There are several reasons for routing leaf clocks back into AST +instead of using the root clocks directly + +- The leaf clocks may be divided down from the root clock and that + frequency is used to drive the interface. For example, + clk_src_io_clk_o is 96MHz, but comportable modules use either 48MHz + or 24MHz. + +- The leaf clocks and root clocks have very different clock tree depths + and may be difficult for timing closure if they interacted directly. + +- Decouple AST internal design from OpenTitan top-level interfaces clock + and reset selection. + +# Register Access Interface + +AST registers can be accessed via TL-UL interface. These registers are +used for test and calibration purposes and are not required for runtime +operation. See the [Interface Signals +Table](#interface-signals-table) for more details. + +## AST registers initialization during boot. + +In PROD*/DEV Lifecycle states, the ROM code must copy all AST REGA +registers values from OTP to AST. During other Lifecycle states, the ROM +code may also copy all AST REGA registers. It is recommended for the +ROM code to condition the copy by a digest verification of the register +values. If such a digest is too complicated, a simple tag can be used to +condition the copy instead. The AST register copy operation must be +performed in order and must include all REGA registers (starting from +REGA0 and ending at the last REGA). AST sets the ast_init_done_o signal +after the copy completion. + +After the copy, ROM code can either poll for ast_init_done_o assertion +with 100 us timeout (in practice, it should take way less) or ignore it +and let the next SW layers handle it. It is recommended to set an OTP +field for determining the ROM code action. + +The boot code is expected to check all AST output alert signals before +handing over the control to the next code layer (ROM_EXT). The ROM code +response per alert should be defined in a dedicated OTP space. +Recommended response types (per alert): + +1. Do nothing and don't clear the event + +2. Do nothing (continue to the next SW layer) and clear the event + +3. Log the event in some NV space and halt + +4. Halt immediately + +Note that in TEST_UNLOCK*/RMA state, the booter should always act per +#1 regardless of the OTP setting. + +It is recommended to redundantly code the OTP fields that control the +ROM code branching and also to protect the branching code from fault +injection. + +# ADC + +AST contains an analog to digital converter that can be used to sample +various input signals. For OpenTitan this will primarily be used for +[debug cable detection](https://www.sparkfun.com/products/14746). +To activate the ADC, the corresponding [comportable +module](../../../ip/adc_ctrl/README.md) must first +activate the ADC through 'adc_pd_i'. Once activated, it should select +the channel to sample. Channel transition from zero to non-zero value +starts the ADC conversion. The ADC output is synchronous to the ADC +controller. + +## ADC Usage Flow + +1. Activate the ADC by negating 'adc_pd_i' + +2. Wait 30 uS for the ADC to wake up. + +3. Select an analog channel to measure by setting the corresponding bit + in 'adc_chnsel_i' bus. This triggers a measurement. + +4. Wait until 'adc_d_val' is set and read the result via + 'adc_d_o' + +5. Clear 'adc_chnsel_i' bus to 0. Note that adc_chnsel must + be cleared to 0 before a new channel is selected. + +6. Repeat steps 3-5 if more channels or more measurements are required + +7. Deactivate the ADC by setting 'adc_pd_i' to save power. + +```wavejson +{ signal: [ {node: '.a..b........', phase:0.2}, +{name: 'adc_pd_i' , wave: '10|..|.....|....|..1'}, {name: +'clk_ast_adc_i', wave: 'p.|..|.....|....|...'}, {name: +'adc_chnsel_i' , wave: '0.|.3|..04.|....|0..'}, {name: +'adc_d_val_o' , wave: '0.|..|.1.0.|.1..|.0.'}, {name: 'adc_d_o' , +wave: 'x.|..|.3.x.|.4..|.x.', data: ['ch0', 'ch1', 'ch1']}, ], +edge: [ 'a<->b wakeup time', ] } +``` + +# Random Number Generator + +AST contains an entropy source vendor IP block that generates random number +bitstreams, and performs health testing and conditioning of these random +numbers. The conditioned and FIPS compliant entropy bits are packed into +384-bit seeds and then fed into the [OpenTitan CSRNG +module](../../../ip/csrng/README.md). + + +# Entropy Consumption + +AST consumes entropy for defensive purposes. However, AST does not +consume its raw entropy directly. Instead, AST receives entropy from the +[Entropy Distribution Network +(EDN)](../../../ip/edn/README.md). Note +that entropy_ack and entropy_i are packed into enropy_rsp_i in the +interface. Also note that once entropy_req_o is set, it will remain set +until ack or until reset. + +```wavejson +{signal: [ + +{name: 'clk_ast_es_i' , wave: 'p.|..........'}, + +{name: 'entropy_req_o' , wave: '01|.0.1.....0'}, + +{name: 'entropy_ack_i' , wave: '0.|10.1.01..0'}, + +{name: 'entropy_i' , wave: 'xx|2x.22x222x'}, + +] } +``` + +# Countermeasures and Alerts + +## Alert Events + +AST's sensors and detectors, when triggered, output alert events +to a sensor controller. The event signals are level until acknowledged +by the controller. Further, the events are differentially encoded to +ensure they cannot be hard-wired or faulted to either '1' or +'0'. + + + +## Alert Signaling + +Outgoing alert events are level. Incoming event ack signals clear the +alert event (similar to an interrupt). Outgoing alert events should be +OR'd inside the sensor or power manager (depending on what level of deep +sleep support is needed) to generate wakeup, that way AST does not need +to do any additional handling for wakeups during low power mode. + +The AST defines each alert signal in both positive (P) and negative (N) +polarity (see ast_dif_t typedef with 'p' and 'n' +signals), however, the P and N signals are not necessarily fully +differential, for example, at times, it might occur that both P and N +are at the same value. For alert_o case, the correct way to treat it is +to propagate an alert signal if either P is high or N is low. + +## Countermeasures + +Most countermeasure enablement is controlled by Nuvoton via the +registers interface. Clock jitter is an exception because there is a +reasoning for dynamically turning it on and off (security/performance +tradeoff). Unless stated otherwise, countermeasures are active in all +modes but deep-sleep. diff --git a/hw/top_darjeeling_no_ibex/ip/ast/ast.core b/hw/top_darjeeling_no_ibex/ip/ast/ast.core new file mode 100644 index 00000000000..9c8c095518f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/ast.core @@ -0,0 +1,127 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:top_darjeeling_ast:0.1" +description: "Analog Sensor Top generic views" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:prim:clock_buf + - lowrisc:prim:clock_div + - lowrisc:prim:clock_gating + - lowrisc:prim:clock_inv + - lowrisc:prim:lc_dec + - lowrisc:prim:lfsr + - lowrisc:darjeeling_ip:pinmux_pkg + - lowrisc:prim:assert + - lowrisc:prim:prim_pkg + - lowrisc:prim:mubi + - lowrisc:prim:multibit_sync + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:ip:edn_pkg + - lowrisc:ip:entropy_src_pkg + - lowrisc:darjeeling_ip:alert_handler_pkg + - lowrisc:darjeeling_ip:clkmgr_pkg + - lowrisc:darjeeling_ip:rstmgr_pkg + - lowrisc:systems:top_darjeeling_ast_pkg + files: + - rtl/ast_reg_pkg.sv + - rtl/ast_bhv_pkg.sv + - rtl/ast.sv + - rtl/ast_reg_top.sv + - rtl/adc.sv + - rtl/adc_ana.sv + - rtl/vcc_pgd.sv + - rtl/vio_pgd.sv + - rtl/vcaon_pgd.sv + - rtl/vcmain_pgd.sv + - rtl/ast_alert.sv + - rtl/aon_clk.sv + - rtl/aon_osc.sv + - rtl/io_clk.sv + - rtl/io_osc.sv + - rtl/sys_clk.sv + - rtl/sys_osc.sv + - rtl/usb_clk.sv + - rtl/usb_osc.sv + - rtl/gfr_clk_mux2.sv + - rtl/ast_clks_byp.sv + - rtl/rglts_pdm_3p3v.sv + - rtl/ast_pulse_sync.sv + - rtl/ast_entropy.sv + - rtl/dev_entropy.sv + - rtl/rng.sv + - rtl/ast_dft.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/ast.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + files: + - lint/ast.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + AST_BYPASS_CLK: + datatype: bool + paramtype: vlogdefine + ANALOGSIM: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: ast + parameters: + - SYNTHESIS + - AST_BYPASS_CLK + - ANALOGSIM + + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" + + sim: + <<: *default_target + default_tool: vcs + filesets: + - files_rtl + tools: + vcs: + vcs_options: [-sverilog -ntb_opts uvm-1.2 -CFLAGS --std=c99 -CFLAGS -fno-extended-identifiers -CFLAGS --std=c++11 -timescale=1ns/1ps -l vcs.log] + toplevel: ast diff --git a/hw/top_darjeeling_no_ibex/ip/ast/ast_pkg.core b/hw/top_darjeeling_no_ibex/ip/ast/ast_pkg.core new file mode 100644 index 00000000000..73b63cd556e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/ast_pkg.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:top_darjeeling_ast_pkg" +description: "Analog sensor top (AST) wrapper package" +virtual: + - lowrisc:systems:ast_pkg + +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_constants:top_pkg + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/ast_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip/ast/ast_regs.html b/hw/top_darjeeling_no_ibex/ip/ast/ast_regs.html new file mode 100644 index 00000000000..0abde578251 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/ast_regs.html @@ -0,0 +1,52 @@ + + + + + +
+
ast.REVID @ 0x0
+

AST Revision Identification Register
+Reset: TLUL Reset

+
Reset default = 0x1, mask 0xff
+
+ + + +
31302928272625242322212019181716
 
1514131211109876543210
 REVID
BitsTypeResetNameDescription
7:0ro0x1REVID

Revision

+
+ + + + + +
+
ast.RWTYPE0 @ 0x4
+

RW type with one field

+
Reset default = 0xbc614e, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
RWTYPE0...
1514131211109876543210
...RWTYPE0
BitsTypeResetNameDescription
31:0rw0xbc614eRWTYPE0

field description

+
+ + + + + +
+
ast.RWTYPE1 @ 0x8
+

RW type +with long +description +and multiple fields

+
Reset default = 0x6411, mask 0xff13
+
+ + + + + + + +
31302928272625242322212019181716
 
1514131211109876543210
FIELD15_8 FIELD4 FIELD1FIELD0
BitsTypeResetNameDescription
0rw0x1FIELD0

field 0

1rw0x0FIELD1

field 1

3:2Reserved
4rw0x1FIELD4

field 4

7:5Reserved
15:8rw0x64FIELD15_8

field [15:8]

+
diff --git a/hw/top_darjeeling_no_ibex/ip/ast/data/BUILD b/hw/top_darjeeling_no_ibex/ip/ast/data/BUILD new file mode 100644 index 00000000000..dda56de039e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/data/BUILD @@ -0,0 +1,10 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/hw/top_darjeeling_no_ibex/ip/ast/data/ast.hjson b/hw/top_darjeeling_no_ibex/ip/ast/data/ast.hjson new file mode 100644 index 00000000000..3627de59d6f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/data/ast.hjson @@ -0,0 +1,507 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################# +// *Name: ast +// *Module Description: Analog Sensors Top Registers +//############################################################################# +{ name: "ast", + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "34", + design_spec: "../doc", + dv_doc: "", + hw_checklist: "", + sw_checklist: "", + version: "1.0.0", + life_stage: "L1", + design_stage: "D2", + verification_stage: "V2S", + dif_stage: "", + clocking: [ + { clock: "clk_ast_tlul_i", reset: "rst_ast_tlul_ni", primary: true }, + { clock: "clk_ast_adc_i", reset: "rst_ast_adc_ni"}, + { clock: "clk_ast_alert_i", reset: "rst_ast_alert_ni"}, + { clock: "clk_ast_rng_i", reset: "rst_ast_rng_ni"}, + ], + bus_interfaces: [ + { protocol: "tlul", + direction: "device" + } + ], + no_auto_alert_regs: "True", + param_list: [ + { name: "NumRegsB", + desc: "Number of registers in the Array-B", + type: "int", + default: "5", + local: "true", + }, + { name: "NumUsbBeaconPulses", + desc: "Number of USB valid beacon pulses for clock to re-calibrate", + type: "int", + default: "8", + local: "true" + }, + ], + regwidth: "32", + registers: [ + { name: "REGA0", + desc: "AST Register 0 for OTP/ROM Write Testing", + swaccess: "ro", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclAll" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x00", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA1", + desc: "AST 1 Register for OTP/ROM Write Testing", + swaccess: "ro", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclAll" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x01", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA2", + desc: "AST 2 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x02", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA3", + desc: "AST 3 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x03", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA4", + desc: "AST 4 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x04", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA5", + desc: "AST 5 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x05", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA6", + desc: "AST 6 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x06", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA7", + desc: "AST 7 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x07", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA8", + desc: "AST 8 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x08", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA9", + desc: "AST 9 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x09", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA10", + desc: "AST 10 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0A", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA11", + desc: "AST 11 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0B", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA12", + desc: "AST 13 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0C", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA13", + desc: "AST 13 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0D", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA14", + desc: "AST 14 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0E", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA15", + desc: "AST 15 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x0F", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA16", + desc: "AST 16 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x10", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA17", + desc: "AST 17 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x11", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA18", + desc: "AST 18 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x12", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA19", + desc: "AST 19 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x13", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA20", + desc: "AST 20 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x14", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA21", + desc: "AST 21 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x15", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA22", + desc: "AST 22 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x16", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA23", + desc: "AST 23 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x17", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA24", + desc: "AST 24 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x18", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA25", + desc: "AST 25 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x19", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA26", + desc: "AST 26 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1A", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA27", + desc: "AST 27 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1B", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA28", + desc: "AST 28 Register for OTP/ROM Write Testing", + swaccess: "ro", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1C", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGA29", + desc: "AST 29 Register for OTP/ROM Write Testing", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclWrite" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1D", + }, + ], + }, //---------------------------------------------------------------------- + { name: "REGAL", + desc: "AST Last Register for OTP/ROM Write Testing", + swaccess: "wo", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclAll" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0x1E", + }, + ], + }, //---------------------------------------------------------------------- + /////////////////////////////////////////////////////////////////////////// + { skipto: "0x200" } + /////////////////////////////////////////////////////////////////////////// + { multireg: + { + name: "REGB", + desc: "AST Registers Array-B to set address space size", + count: "NumRegsB", + cname: "REGB", + swaccess: "rw", + hwaccess: "hro", + tags: [ // don't write random data to any of the AST registers + "excl:CsrAllTests:CsrExclAll" ], + fields: [ + { bits: "31:0", + name: "reg32", + desc: "32-bit Register", + resval: "0", + }, + ], + }, + }, //---------------------------------------------------------------------- + ], +} diff --git a/hw/top_darjeeling_no_ibex/ip/ast/data/ast_cdc_abstract.sgdc b/hw/top_darjeeling_no_ibex/ip/ast/data/ast_cdc_abstract.sgdc new file mode 100644 index 00000000000..bbcfafd8b9a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/data/ast_cdc_abstract.sgdc @@ -0,0 +1,624 @@ +################################################################################ +# +# This file has been generated by SpyGlass: +# File Created by: ngotliv +# File Created on: Thu May 19 11:20:01 2022 +# Working Directory: /tanap1/proj_cd14/opentitan/ngotliv/nightly_220518/nuvoton/top/spyglass +# File Location : ./ast_cdc/ast/cdc/cdc_abstract/spyglass_reports/abstract_view/ast_AdcChannels_2_AdcDataWidth_10_Ast2PadOutWidth_9_Entro_1_cdc_abstract.sgdc +# SpyGlass Version : SpyGlass_vR-2020.12-1 +# Policy Name : clock-reset +# Comment : Generated by rule Ac_abstract01 +# +################################################################################ +if { $::sg_use_cdc_abstract_view == 1 } { + abstract_file -version 5.1.0 -scope cdc + + current_design "ast" -def_param + +################################################################# +# abstract_port constraints # +################################################################# + +abstract_port -path_logic combo -ports "otp_power_seq_h_o[0]" -related_ports otp_power_seq_i[0] +abstract_port -path_logic combo -ports "otp_power_seq_h_o[1]" -related_ports otp_power_seq_i[1] +abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][0]" -related_ports padmux2ast_i[4] +abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][1]" -related_ports padmux2ast_i[5] +abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][2]" -related_ports padmux2ast_i[6] +abstract_port -path_logic combo -ports "obs_ctrl_o[obmsl][3]" -related_ports padmux2ast_i[7] +abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][0]" -related_ports padmux2ast_i[0] +abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][1]" -related_ports padmux2ast_i[1] +abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][2]" -related_ports padmux2ast_i[2] +abstract_port -path_logic combo -ports "obs_ctrl_o[obgsl][3]" -related_ports padmux2ast_i[3] + +################################################################# +# clock constraints # +################################################################# + + +# Clock constraint is not generated. + + +################################################################# +# set_case_analysis constraints # +################################################################# + +set_case_analysis -name "tl_o[d_user][rsp_intg][6]" -value 0 +set_case_analysis -name "tl_o[d_sink][0]" -value 0 +set_case_analysis -name "tl_o[d_param][0]" -value 0 +set_case_analysis -name "tl_o[d_param][1]" -value 0 +set_case_analysis -name "tl_o[d_param][2]" -value 0 +set_case_analysis -name "tl_o[d_opcode][1]" -value 0 +set_case_analysis -name "tl_o[d_opcode][2]" -value 0 + +################################################################# +# reset constraints # +################################################################# + +reset -name "tl_o[a_ready]" -value 1 +reset -name "tl_o[d_valid]" -value 0 +reset -name "ast_pwst_o[main_pok]" -value 0 +reset -name "ast_pwst_o[vcc_pok]" -value 0 +reset -name "ast_pwst_h_o[main_pok]" -value 0 +reset -name "ast_pwst_h_o[vcc_pok]" -value 0 +reset -name "flash_power_ready_h_o" -value 0 + +# Synchronous reset constraint is not generated. + + +################################################################# +# quasi_static constraints # +################################################################# + +quasi_static -name "ast2padmux_o[0]" +quasi_static -name "ast2padmux_o[1]" +quasi_static -name "ast2padmux_o[2]" +quasi_static -name "ast2padmux_o[3]" +quasi_static -name "ast2padmux_o[4]" +quasi_static -name "ast2padmux_o[5]" +quasi_static -name "ast2padmux_o[6]" +quasi_static -name "ast2padmux_o[7]" +quasi_static -name "ast2padmux_o[8]" +quasi_static -name "ast2pad_t0_ao" +quasi_static -name "ast2pad_t1_ao" +quasi_static -name "dft_scan_md_o[0]" +quasi_static -name "dft_scan_md_o[1]" +quasi_static -name "dft_scan_md_o[2]" +quasi_static -name "dft_scan_md_o[3]" + +################################################################# +# abstract_port constraints # +################################################################# + +abstract_port -ports "adc_d_o" -scope cdc -clock "clk_ast_adc_i" -related_ports "adc_pd_i" "adc_chnsel_i" +abstract_port -ports "adc_d_val_o" -scope cdc -clock "clk_ast_adc_i" -related_ports "adc_pd_i" "adc_chnsel_i" +abstract_port -ports "alert_req_o[alerts][0][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][0][n]" "alert_rsp_i[alerts_ack][0][n]" +abstract_port -ports "alert_req_o[alerts][0][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][0][p]" "alert_rsp_i[alerts_ack][0][p]" +abstract_port -ports "alert_req_o[alerts][1][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][1][n]" "alert_rsp_i[alerts_ack][1][n]" +abstract_port -ports "alert_req_o[alerts][1][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][1][p]" "alert_rsp_i[alerts_ack][1][p]" +abstract_port -ports "alert_req_o[alerts][2][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][2][n]" "alert_rsp_i[alerts_ack][2][n]" +abstract_port -ports "alert_req_o[alerts][2][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][2][p]" "alert_rsp_i[alerts_ack][2][p]" +abstract_port -ports "alert_req_o[alerts][3][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][3][n]" "alert_rsp_i[alerts_ack][3][n]" +abstract_port -ports "alert_req_o[alerts][3][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][3][p]" "alert_rsp_i[alerts_ack][3][p]" +abstract_port -ports "alert_req_o[alerts][4][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][4][n]" "alert_rsp_i[alerts_ack][4][n]" +abstract_port -ports "alert_req_o[alerts][4][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][4][p]" "alert_rsp_i[alerts_ack][4][p]" +abstract_port -ports "alert_req_o[alerts][5][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][5][n]" "alert_rsp_i[alerts_ack][5][n]" +abstract_port -ports "alert_req_o[alerts][5][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][5][p]" "alert_rsp_i[alerts_ack][5][p]" +abstract_port -ports "alert_req_o[alerts][6][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][6][n]" "alert_rsp_i[alerts_ack][6][n]" +abstract_port -ports "alert_req_o[alerts][6][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][6][p]" "alert_rsp_i[alerts_ack][6][p]" +abstract_port -ports "alert_req_o[alerts][7][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][7][n]" "alert_rsp_i[alerts_ack][7][n]" +abstract_port -ports "alert_req_o[alerts][7][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][7][p]" "alert_rsp_i[alerts_ack][7][p]" +abstract_port -ports "alert_req_o[alerts][8][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][8][n]" "alert_rsp_i[alerts_ack][8][n]" +abstract_port -ports "alert_req_o[alerts][8][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][8][p]" "alert_rsp_i[alerts_ack][8][p]" +abstract_port -ports "alert_req_o[alerts][9][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][9][n]" "alert_rsp_i[alerts_ack][9][n]" +abstract_port -ports "alert_req_o[alerts][9][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][9][p]" "alert_rsp_i[alerts_ack][9][p]" +abstract_port -ports "alert_req_o[alerts][10][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][10][n]" "alert_rsp_i[alerts_ack][10][n]" +abstract_port -ports "alert_req_o[alerts][10][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][10][p]" "alert_rsp_i[alerts_ack][10][p]" +abstract_port -ports "alert_req_o[alerts][11][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][11][n]" "alert_rsp_i[alerts_ack][11][n]" +abstract_port -ports "alert_req_o[alerts][11][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][11][p]" "alert_rsp_i[alerts_ack][11][p]" +abstract_port -ports "alert_req_o[alerts][12][n]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][12][n]" "alert_rsp_i[alerts_ack][12][n]" +abstract_port -ports "alert_req_o[alerts][12][p]" -scope cdc -clock "clk_ast_alert_i" -related_ports "alert_rsp_i[alerts_trig][12][p]" "alert_rsp_i[alerts_ack][12][p]" +abstract_port -ports "entropy_req_o[edn_req]" -scope cdc -clock "clk_ast_es_i" -related_ports "entropy_rsp_i[edn_ack]" +abstract_port -ports "tl_o[a_ready]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_error]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][0]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][4]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][1]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][5]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][4]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_data][5]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][6]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" +abstract_port -ports "tl_o[d_data][7]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" +abstract_port -ports "tl_o[d_data][8]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][9]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][10]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][11]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][12]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][13]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][14]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][15]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][16]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][17]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][18]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][19]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][20]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][21]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][22]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][23]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][24]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][25]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][26]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][27]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][28]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][29]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][30]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_data][31]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][0]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][1]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][3]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][4]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][4]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][5]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][5]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][6]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][6]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_source][7]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_source][7]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_size][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][0]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_size][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_size][1]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_opcode][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_valid]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][data_intg][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][2]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][3]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][4]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][5]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "fla_alert_src_i[n]" "fla_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][data_intg][6]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" "otp_alert_src_i[n]" "otp_alert_src_i[p]" "dft_strap_test_i[straps][0]" "dft_strap_test_i[straps][1]" "dft_strap_test_i[valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "tl_o[d_user][rsp_intg][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "ast_init_done_o" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "usb_io_pu_cal_o" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmen][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmen][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmen][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmen][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmsl][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmsl][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmsl][2]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obmsl][3]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obgsl][0]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obgsl][1]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obgsl][2]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "obs_ctrl_o[obgsl][3]" -scope cdc -clock "clk_ast_tlul_i" -combo yes -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "flash_bist_en_o" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_b][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_b][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_b][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_b][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_en_b]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_a][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_a][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_a][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_a][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rmf_o[marg_en_a]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_b][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_b][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_b][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_b][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_en_b]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_a][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_a][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_a][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_a][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "dpram_rml_o[marg_en_a]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "spram_rm_o[marg_en]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprgf_rm_o[marg_en]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg][0]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg][1]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg][2]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg][3]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "sprom_rm_o[marg_en]" -scope cdc -clock "clk_ast_tlul_i" -related_ports "tl_i[d_ready]" "tl_i[a_user][data_intg][0]" "tl_i[a_user][data_intg][1]" "tl_i[a_user][data_intg][2]" "tl_i[a_user][data_intg][3]" "tl_i[a_user][data_intg][4]" "tl_i[a_user][data_intg][5]" "tl_i[a_user][data_intg][6]" "tl_i[a_user][cmd_intg][0]" "tl_i[a_user][cmd_intg][1]" "tl_i[a_user][cmd_intg][2]" "tl_i[a_user][cmd_intg][3]" "tl_i[a_user][cmd_intg][4]" "tl_i[a_user][cmd_intg][5]" "tl_i[a_user][cmd_intg][6]" "tl_i[a_user][instr_type][0]" "tl_i[a_user][instr_type][1]" "tl_i[a_user][instr_type][2]" "tl_i[a_user][instr_type][3]" "tl_i[a_data][0]" "tl_i[a_data][1]" "tl_i[a_data][2]" "tl_i[a_data][3]" "tl_i[a_data][4]" "tl_i[a_data][5]" "tl_i[a_data][6]" "tl_i[a_data][7]" "tl_i[a_data][8]" "tl_i[a_data][9]" "tl_i[a_data][10]" "tl_i[a_data][11]" "tl_i[a_data][12]" "tl_i[a_data][13]" "tl_i[a_data][14]" "tl_i[a_data][15]" "tl_i[a_data][16]" "tl_i[a_data][17]" "tl_i[a_data][18]" "tl_i[a_data][19]" "tl_i[a_data][20]" "tl_i[a_data][21]" "tl_i[a_data][22]" "tl_i[a_data][23]" "tl_i[a_data][24]" "tl_i[a_data][25]" "tl_i[a_data][26]" "tl_i[a_data][27]" "tl_i[a_data][28]" "tl_i[a_data][29]" "tl_i[a_data][30]" "tl_i[a_data][31]" "tl_i[a_mask][0]" "tl_i[a_mask][1]" "tl_i[a_mask][2]" "tl_i[a_mask][3]" "tl_i[a_address][0]" "tl_i[a_address][1]" "tl_i[a_address][2]" "tl_i[a_address][3]" "tl_i[a_address][4]" "tl_i[a_address][5]" "tl_i[a_address][6]" "tl_i[a_address][7]" "tl_i[a_address][8]" "tl_i[a_address][9]" "tl_i[a_address][10]" "tl_i[a_address][11]" "tl_i[a_address][12]" "tl_i[a_address][13]" "tl_i[a_address][14]" "tl_i[a_address][15]" "tl_i[a_address][16]" "tl_i[a_address][17]" "tl_i[a_address][18]" "tl_i[a_address][19]" "tl_i[a_address][20]" "tl_i[a_address][21]" "tl_i[a_address][22]" "tl_i[a_address][23]" "tl_i[a_address][24]" "tl_i[a_address][25]" "tl_i[a_address][26]" "tl_i[a_address][27]" "tl_i[a_address][28]" "tl_i[a_address][29]" "tl_i[a_address][30]" "tl_i[a_address][31]" "tl_i[a_size][0]" "tl_i[a_size][1]" "tl_i[a_opcode][0]" "tl_i[a_opcode][1]" "tl_i[a_opcode][2]" "tl_i[a_valid]" +abstract_port -ports "ast_pwst_o[vcc_pok]" -scope cdc -clock "clk_src_aon_o" +abstract_port -ports "ast_pwst_o[aon_pok]" -scope cdc -clock "clk_src_aon_o" -related_ports "main_pd_ni" +abstract_port -ports "ast_pwst_o[main_pok]" -scope cdc -clock "clk_src_aon_o" -combo yes -related_ports "main_pd_ni" +abstract_port -ports "ast_pwst_h_o[vcc_pok]" -scope cdc -clock "clk_src_aon_o" +abstract_port -ports "ast_pwst_h_o[aon_pok]" -scope cdc -clock "clk_src_aon_o" -related_ports "main_pd_ni" +abstract_port -ports "ast_pwst_h_o[main_pok]" -scope cdc -clock "clk_src_aon_o" -combo yes -related_ports "main_pd_ni" +abstract_port -ports "flash_power_down_h_o" -scope cdc -clock "clk_src_aon_o" +abstract_port -ports "otp_power_seq_h_o" -scope cdc -clock "clk_src_aon_o" +abstract_port -ports "clk_src_aon_val_o" -scope cdc -clock SG_VIRT_OUT_20 +abstract_port -ports "clk_src_sys_val_o" -scope cdc -clock SG_VIRT_OUT_83 +abstract_port -ports "clk_src_io_val_o" -scope cdc -clock SG_VIRT_OUT_84 +abstract_port -ports "clk_src_usb_val_o" -scope cdc -clock SG_VIRT_OUT_85 + + +################################################################# +#translating input constraints to abstract_port where it involves +#a sync crossing and apending -combo no # +################################################################# + +abstract_port -ports "clk_src_sys_en_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_ast_ext_i" +abstract_port -ports "clk_src_sys_jen_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_src_sys_o" +abstract_port -ports "clk_src_io_en_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_ast_ext_i" +abstract_port -ports "clk_src_usb_en_i" -scope cdc -clock "clk_src_aon_o" -combo no -combo_ifn "clk_ast_ext_i" +abstract_port -ports "rng_en_i" -scope cdc -clock "clk_src_sys_o" -combo no -combo_ifn "clk_ast_tlul_i" +abstract_port -ports "rng_fips_i" -scope cdc -clock "clk_src_sys_o" -combo no -combo_ifn "clk_ast_tlul_i" +abstract_port -ports "ext_freq_is_96m_i" -scope cdc -clock "clk_ast_tlul_i" -combo no +abstract_port -ports "all_clk_byp_req_i" -scope cdc -clock "clk_ast_tlul_i" -combo no +abstract_port -ports "io_clk_byp_req_i" -scope cdc -clock "clk_ast_tlul_i" -combo no + + +################################################################# +#Adding -combo no to abstract_port defined at input port# +#If it invloves a synchronized control crossing # +################################################################# + + +################################################################# +# qualifier constraints # +################################################################# + +#Port with -ignore constraint.Reason:Path is Hanging or Blocked# +abstract_port -ports "ast_pwst_o[io_pok][0]" -scope cdc -ignore -comment "blocked or hanging path" +###################################################### +#Port with -ignore constraint.Reason:Path is Hanging or Blocked# +abstract_port -ports "ast_pwst_o[io_pok][1]" -scope cdc -ignore -comment "blocked or hanging path" +###################################################### +#Port with -ignore constraint.Reason:Path is Hanging or Blocked# +abstract_port -ports "ast_pwst_h_o[io_pok][0]" -scope cdc -ignore -comment "blocked or hanging path" +###################################################### + +#Port with -ignore constraint.Reason:Path is Hanging or Blocked# +abstract_port -ports "ast_pwst_h_o[io_pok][1]" -scope cdc -ignore -comment "blocked or hanging path" +###################################################### +################################################################# +# virtual clock constraints # +################################################################# + +clock -tag SG_VIRT_OUT_20 -domain "domain20" +## "abstraction_new_domain_83" :: bbox_merged_domain_83 +clock -tag SG_VIRT_OUT_83 -domain "abstraction_new_domain_83" +## "abstraction_new_domain_84" :: bbox_merged_domain_84 +clock -tag SG_VIRT_OUT_84 -domain "abstraction_new_domain_84" +## "abstraction_new_domain_85" :: bbox_merged_domain_85 +clock -tag SG_VIRT_OUT_85 -domain "abstraction_new_domain_85" +################################################################# +# cdc_attribute constraints # +################################################################# + + +# cdc_attribute constraint is not generated. + + +################################################################# +# reset_filter_path constraints # +################################################################# + +reset_filter_path -type rdc -from_rst "tl_o[a_ready]" -to_rst "tl_o[d_valid]" "rst_ast_tlul_ni" +reset_filter_path -type rdc -from_rst "tl_o[d_valid]" -to_rst "tl_o[a_ready]" "rst_ast_tlul_ni" +reset_filter_path -type rdc -from_rst "rst_ast_tlul_ni" -to_rst "tl_o[a_ready]" "tl_o[d_valid]" +reset_filter_path -type rdc -from_rst "ast_pwst_o[main_pok]" -to_rst "ast_pwst_h_o[main_pok]" "ast_pwst_h_o[vcc_pok]" +reset_filter_path -type rdc -from_rst "ast_pwst_h_o[main_pok]" -to_rst "ast_pwst_o[main_pok]" "ast_pwst_h_o[vcc_pok]" +reset_filter_path -type rdc -from_rst "ast_pwst_h_o[vcc_pok]" -to_rst "ast_pwst_o[main_pok]" "ast_pwst_h_o[main_pok]" +reset_filter_path -type rdc -from_rst "obs_ctrl_o[obmsl][3]" -to_rst "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[0]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[1]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[2]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[4]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[5]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[6]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[6]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[7]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[7]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[8]" +reset_filter_path -type rdc -from_rst "ast2padmux_o[8]" -to_rst "obs_ctrl_o[obmsl][3]" "ast2padmux_o[0]" "ast2padmux_o[1]" "ast2padmux_o[2]" "ast2padmux_o[4]" "ast2padmux_o[5]" "ast2padmux_o[6]" "ast2padmux_o[7]" + +################################################################# +# Inferred abstract_port constraints # +################################################################# + + +abstract_port -ports "por_ni" -clock "clk_src_aon_o" -start +abstract_port -ports "fla_alert_src_i[n]" -clock "clk_ast_tlul_i" -combo no -start +abstract_port -ports "fla_alert_src_i[p]" -clock "clk_ast_tlul_i" -combo no -start +abstract_port -ports "otp_alert_src_i[n]" -clock "clk_ast_tlul_i" -combo no -start +abstract_port -ports "otp_alert_src_i[p]" -clock "clk_ast_tlul_i" -combo no -start +abstract_port -ports "sns_clks_i[clk_io_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_usb_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div2_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_timers]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_usb_secure]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_secure]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_secure]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div2_infra]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_infra]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_infra]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_infra]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_otbn]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_kmac]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_hmac]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_aes]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_aon_timers]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_aon_peri]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_aon_secure]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div2_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_usb_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_main_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_aon_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_clks_i[clk_io_div4_powerup]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c0_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_i2c0_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_usbif_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_usbif_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_usb_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_usb_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_host0_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_host0_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_device_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_spi_device_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_aon_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_aon_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_io_div4_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_io_div4_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_shadowed_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_sys_shadowed_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_aon_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_aon_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_io_div4_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_io_div4_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_io_div4_shadowed_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_io_div4_shadowed_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_shadowed_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_lc_shadowed_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_usb_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_usb_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div4_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div4_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div4_shadowed_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div4_shadowed_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div2_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_div2_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_io_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_aon_n][0]" -ignore -comment "hanging path" +abstract_port -ports "sns_rsts_i[rst_por_aon_n][1]" -ignore -comment "hanging path" +abstract_port -ports "sns_spi_ext_clk_i" -ignore -comment "hanging path" +abstract_port -ports "vcc_supp_i" -ignore -comment "hanging path" +abstract_port -ports "vcaon_supp_i" -ignore -comment "hanging path" +abstract_port -ports "vcmain_supp_i" -ignore -comment "hanging path" +abstract_port -ports "vioa_supp_i" -ignore -comment "hanging path" +abstract_port -ports "viob_supp_i" -ignore -comment "hanging path" +clock -tag SG_VCLK_1 + +################################################################# +# cdc_filter_coherency constraints # +################################################################# + + +# cdc_filter_coherency constraint is not generated. + + + +################################################################# +# clock_sense constraints # +################################################################# + + +################################################################# +# reset_sense constraints # +################################################################# + +# reset_sense constraint is not generated. Either no reset defined on input ports or no combinational path found from primary resets to output port. + +################################################################# +# block interface constraints # +################################################################# + +abstract_interface_param -name "AdcChannels" -value "2" +abstract_interface_param -name "AdcDataWidth" -value "10" +abstract_interface_param -name "EntropyStreams" -value "4" +abstract_interface_param -name "UsbCalibWidth" -value "20" +abstract_interface_param -name "Ast2PadOutWidth" -value "9" +abstract_interface_param -name "Pad2AstInWidth" -value "9" +abstract_interface_port -name "tl_i" -definition "input tlul_pkg :: tl_h2d_t tl_i;" +abstract_interface_port -name "tl_o" -definition "output tlul_pkg :: tl_d2h_t tl_o;" +abstract_interface_port -name "ast_init_done_o" -definition "output logic ast_init_done_o; " +abstract_interface_port -name "clk_ast_adc_i" -definition "input clk_ast_adc_i; " +abstract_interface_port -name "rst_ast_adc_ni" -definition "input rst_ast_adc_ni; " +abstract_interface_port -name "clk_ast_alert_i" -definition "input clk_ast_alert_i; " +abstract_interface_port -name "rst_ast_alert_ni" -definition "input rst_ast_alert_ni; " +abstract_interface_port -name "clk_ast_es_i" -definition "input clk_ast_es_i; " +abstract_interface_port -name "rst_ast_es_ni" -definition "input rst_ast_es_ni; " +abstract_interface_port -name "clk_ast_rng_i" -definition "input clk_ast_rng_i; " +abstract_interface_port -name "rst_ast_rng_ni" -definition "input rst_ast_rng_ni; " +abstract_interface_port -name "clk_ast_tlul_i" -definition "input clk_ast_tlul_i; " +abstract_interface_port -name "rst_ast_tlul_ni" -definition "input rst_ast_tlul_ni; " +abstract_interface_port -name "clk_ast_usb_i" -definition "input clk_ast_usb_i; " +abstract_interface_port -name "rst_ast_usb_ni" -definition "input rst_ast_usb_ni; " +abstract_interface_port -name "clk_ast_ext_i" -definition "input clk_ast_ext_i; " +abstract_interface_port -name "por_ni" -definition "input por_ni; " +abstract_interface_port -name "sns_clks_i" -definition "input clkmgr_pkg :: clkmgr_out_t sns_clks_i;" +abstract_interface_port -name "sns_rsts_i" -definition "input rstmgr_pkg :: rstmgr_out_t sns_rsts_i;" +abstract_interface_port -name "sns_spi_ext_clk_i" -definition "input sns_spi_ext_clk_i; " +abstract_interface_port -name "vcc_supp_i" -definition "input vcc_supp_i; " +abstract_interface_port -name "vcaon_supp_i" -definition "input vcaon_supp_i; " +abstract_interface_port -name "vcmain_supp_i" -definition "input vcmain_supp_i; " +abstract_interface_port -name "vioa_supp_i" -definition "input vioa_supp_i; " +abstract_interface_port -name "viob_supp_i" -definition "input viob_supp_i; " +abstract_interface_port -name "ast_pwst_o" -definition "output ast_pkg :: ast_pwst_t ast_pwst_o;" +abstract_interface_port -name "ast_pwst_h_o" -definition "output ast_pkg :: ast_pwst_t ast_pwst_h_o;" +abstract_interface_port -name "main_pd_ni" -definition "input main_pd_ni; " +abstract_interface_port -name "main_env_iso_en_i" -definition "input main_env_iso_en_i; " +abstract_interface_port -name "flash_power_down_h_o" -definition "output logic flash_power_down_h_o; " +abstract_interface_port -name "flash_power_ready_h_o" -definition "output logic flash_power_ready_h_o; " +abstract_interface_port -name "otp_power_seq_i" -definition "input [1:0] otp_power_seq_i; " +abstract_interface_port -name "otp_power_seq_h_o" -definition "output logic [1:0] otp_power_seq_h_o; " +abstract_interface_port -name "clk_src_sys_en_i" -definition "input clk_src_sys_en_i; " +abstract_interface_port -name "clk_src_sys_jen_i" -definition "input prim_mubi_pkg :: mubi4_t clk_src_sys_jen_i;" +abstract_interface_port -name "clk_src_sys_o" -definition "output logic clk_src_sys_o; " +abstract_interface_port -name "clk_src_sys_val_o" -definition "output logic clk_src_sys_val_o; " +abstract_interface_port -name "clk_src_aon_o" -definition "output logic clk_src_aon_o; " +abstract_interface_port -name "clk_src_aon_val_o" -definition "output logic clk_src_aon_val_o; " +abstract_interface_port -name "clk_src_io_en_i" -definition "input clk_src_io_en_i; " +abstract_interface_port -name "clk_src_io_o" -definition "output logic clk_src_io_o; " +abstract_interface_port -name "clk_src_io_val_o" -definition "output logic clk_src_io_val_o; " +abstract_interface_port -name "clk_src_io_48m_o" -definition "output prim_mubi_pkg :: mubi4_t clk_src_io_48m_o;" +abstract_interface_port -name "usb_ref_pulse_i" -definition "input usb_ref_pulse_i; " +abstract_interface_port -name "usb_ref_val_i" -definition "input usb_ref_val_i; " +abstract_interface_port -name "clk_src_usb_en_i" -definition "input clk_src_usb_en_i; " +abstract_interface_port -name "clk_src_usb_o" -definition "output logic clk_src_usb_o; " +abstract_interface_port -name "clk_src_usb_val_o" -definition "output logic clk_src_usb_val_o; " +abstract_interface_port -name "usb_io_pu_cal_o" -definition "output logic [(UsbCalibWidth - 1):0] usb_io_pu_cal_o; " +abstract_interface_port -name "adc_pd_i" -definition "input adc_pd_i; " +abstract_interface_port -name "adc_a0_ai" -definition "input ast_pkg :: awire_t adc_a0_ai;" +abstract_interface_port -name "adc_a1_ai" -definition "input ast_pkg :: awire_t adc_a1_ai;" +abstract_interface_port -name "adc_chnsel_i" -definition "input [(AdcChannels - 1):0] adc_chnsel_i; " +abstract_interface_port -name "adc_d_o" -definition "output [(AdcDataWidth - 1):0] adc_d_o; " +abstract_interface_port -name "adc_d_val_o" -definition "output adc_d_val_o; " +abstract_interface_port -name "rng_en_i" -definition "input rng_en_i; " +abstract_interface_port -name "rng_fips_i" -definition "input rng_fips_i; " +abstract_interface_port -name "rng_val_o" -definition "output logic rng_val_o; " +abstract_interface_port -name "rng_b_o" -definition "output logic [(EntropyStreams - 1):0] rng_b_o; " +abstract_interface_port -name "entropy_rsp_i" -definition "input edn_pkg :: edn_rsp_t entropy_rsp_i;" +abstract_interface_port -name "entropy_req_o" -definition "output edn_pkg :: edn_req_t entropy_req_o;" +abstract_interface_port -name "fla_alert_src_i" -definition "input ast_pkg :: ast_dif_t fla_alert_src_i;" +abstract_interface_port -name "otp_alert_src_i" -definition "input ast_pkg :: ast_dif_t otp_alert_src_i;" +abstract_interface_port -name "alert_rsp_i" -definition "input ast_pkg :: ast_alert_rsp_t alert_rsp_i;" +abstract_interface_port -name "alert_req_o" -definition "output ast_pkg :: ast_alert_req_t alert_req_o;" +abstract_interface_port -name "dft_strap_test_i" -definition "input pinmux_pkg :: dft_strap_test_req_t dft_strap_test_i;" +abstract_interface_port -name "lc_dft_en_i" -definition "input lc_ctrl_pkg :: lc_tx_t lc_dft_en_i;" +abstract_interface_port -name "fla_obs_i" -definition "input [(8 - 1):0] fla_obs_i; " +abstract_interface_port -name "otp_obs_i" -definition "input [(8 - 1):0] otp_obs_i; " +abstract_interface_port -name "otm_obs_i" -definition "input [(8 - 1):0] otm_obs_i; " +abstract_interface_port -name "usb_obs_i" -definition "input usb_obs_i; " +abstract_interface_port -name "obs_ctrl_o" -definition "output ast_pkg :: ast_obs_ctrl_t obs_ctrl_o;" +abstract_interface_port -name "padmux2ast_i" -definition "input [(Pad2AstInWidth - 1):0] padmux2ast_i; " +abstract_interface_port -name "ast2padmux_o" -definition "output logic [(Ast2PadOutWidth - 1):0] ast2padmux_o; " +abstract_interface_port -name "ast2pad_t0_ao" -definition "output ast2pad_t0_ao; " +abstract_interface_port -name "ast2pad_t1_ao" -definition "output ast2pad_t1_ao; " +abstract_interface_port -name "ext_freq_is_96m_i" -definition "input prim_mubi_pkg :: mubi4_t ext_freq_is_96m_i;" +abstract_interface_port -name "all_clk_byp_req_i" -definition "input prim_mubi_pkg :: mubi4_t all_clk_byp_req_i;" +abstract_interface_port -name "all_clk_byp_ack_o" -definition "output prim_mubi_pkg :: mubi4_t all_clk_byp_ack_o;" +abstract_interface_port -name "io_clk_byp_req_i" -definition "input prim_mubi_pkg :: mubi4_t io_clk_byp_req_i;" +abstract_interface_port -name "io_clk_byp_ack_o" -definition "output prim_mubi_pkg :: mubi4_t io_clk_byp_ack_o;" +abstract_interface_port -name "flash_bist_en_o" -definition "output prim_mubi_pkg :: mubi4_t flash_bist_en_o;" +abstract_interface_port -name "dpram_rmf_o" -definition "output ast_pkg :: dpm_rm_t dpram_rmf_o;" +abstract_interface_port -name "dpram_rml_o" -definition "output ast_pkg :: dpm_rm_t dpram_rml_o;" +abstract_interface_port -name "spram_rm_o" -definition "output ast_pkg :: spm_rm_t spram_rm_o;" +abstract_interface_port -name "sprgf_rm_o" -definition "output ast_pkg :: spm_rm_t sprgf_rm_o;" +abstract_interface_port -name "sprom_rm_o" -definition "output ast_pkg :: spm_rm_t sprom_rm_o;" +abstract_interface_port -name "dft_scan_md_o" -definition "output prim_mubi_pkg :: mubi4_t dft_scan_md_o;" +abstract_interface_port -name "scan_shift_en_o" -definition "output scan_shift_en_o; " +abstract_interface_port -name "scan_reset_no" -definition "output scan_reset_no; " +} + +if { $::sg_use_cdc_abstract_view == 1 } { + + + current_design "ast" -def_param +abstract_block_violation -name Propagate_Clocks -sev WARNING -count 1 +abstract_block_violation -name Setup_check01 -sev WARNING -count 16 +abstract_block_violation -name ErrorAnalyzeBBox -sev ERROR -count 1 -is_builtin +abstract_block_violation -name SYNTH_78 -sev WARNING -count 10 -is_builtin +abstract_block_violation -name SYNTH_89 -sev WARNING -count 4 -is_builtin +abstract_block_violation -name SYNTH_93 -sev WARNING -count 1 -is_builtin +abstract_block_violation -name SYNTH_1084 -sev ERROR -count 1 -is_builtin +abstract_block_violation -name WRN_1459 -sev WARNING -count 5 -is_builtin +abstract_block_violation -name WRN_1470 -sev WARNING -count 5 -is_builtin +abstract_block_violation -name checkCMD_dirfile03 -sev WARNING -count 29 -is_builtin +abstract_block_violation -name Propagate_Resets -sev WARNING -count 4 +abstract_block_violation -name Setup_blackbox01 -sev WARNING -count 13 +abstract_block_violation -name Clock_check07 -sev WARNING -count 27 + + +block_file_decompiled_start + + input -name "tl_i" -clock "ast.clk_ast_tlul_i" + input -name "ast.rst_ast_adc_ni" -clock "ast.clk_ast_adc_i" + input -name "ast.rst_ast_alert_ni" -clock "ast.clk_ast_alert_i" + input -name "ast.rst_ast_es_ni" -clock "ast.clk_ast_es_i" + input -name "ast.rst_ast_rng_ni" -clock "ast.clk_ast_rng_i" + input -name "ast.rst_ast_tlul_ni" -clock "ast.clk_ast_tlul_i" + input -name "ast.rst_ast_usb_ni" -clock "ast.clk_ast_usb_i" + input -name "ast.main_pd_ni" -clock "ast.clk_src_aon_o" + input -name "ast.main_env_iso_en_i" -clock "ast.clk_src_aon_o" + input -name "otp_power_seq_i" -clock "ast.clk_src_aon_o" + input -name "clk_src_sys_en_i" -clock "ast.clk_src_aon_o" + input -name "clk_src_sys_jen_i" -clock "ast.clk_src_aon_o" + input -name "clk_src_io_en_i" -clock "ast.clk_src_aon_o" + input -name "usb_ref_pulse_i" -clock "ast.clk_ast_usb_i" + input -name "usb_ref_val_i" -clock "ast.clk_ast_usb_i" + input -name "clk_src_usb_en_i" -clock "ast.clk_src_aon_o" + input -name "adc_pd_i" -clock "ast.clk_ast_adc_i" + input -name "adc_a0_ai" -clock "ast.clk_ast_adc_i" + input -name "adc_a1_ai" -clock "ast.clk_ast_adc_i" + input -name "adc_chnsel_i" -clock "ast.clk_ast_adc_i" + input -name "rng_en_i" -clock "ast.clk_src_sys_o" + input -name "rng_fips_i" -clock "ast.clk_src_sys_o" + input -name "entropy_rsp_i" -clock "ast.clk_ast_es_i" + input -name "alert_rsp_i" -clock "ast.clk_ast_alert_i" + input -name "dft_strap_test_i" -clock "ast.clk_ast_tlul_i" + input -name "lc_dft_en_i" -clock "ast.clk_ast_tlul_i" + input -name "fla_obs_i" -clock "ast.clk_ast_tlul_i" + input -name "otp_obs_i" -clock "ast.clk_ast_tlul_i" + input -name "otm_obs_i" -clock "ast.clk_ast_tlul_i" + input -name "usb_obs_i" -clock "ast.clk_ast_tlul_i" + input -name "ext_freq_is_96m_i" -clock "ast.clk_ast_tlul_i" + input -name "all_clk_byp_req_i" -clock "ast.clk_ast_tlul_i" + input -name "io_clk_byp_req_i" -clock "ast.clk_ast_tlul_i" + output -name "tl_o" -clock "ast.clk_ast_tlul_i" + output -name "ast_init_done_o" -clock "ast.clk_ast_tlul_i" + output -name "ast.flash_power_down_h_o" -clock "ast.clk_src_aon_o" + output -name "ast.flash_power_ready_h_o" -clock "ast.clk_src_aon_o" + output -name "ast.otp_power_seq_h_o" -clock "ast.clk_src_aon_o" + output -name "clk_src_sys_val_o" -clock "ast.clk_src_sys_o" + output -name "clk_src_aon_val_o" -clock "ast.clk_src_aon_o" + output -name "clk_src_io_val_o" -clock "ast.clk_src_io_o" + output -name "clk_src_io_48m_o" -clock "ast.clk_src_io_o" + output -name "clk_src_usb_val_o" -clock "ast.clk_src_usb_o" + output -name "usb_io_pu_cal_o" -clock "ast.clk_ast_tlul_i" + output -name "adc_d_o" -clock "ast.clk_ast_adc_i" + output -name "adc_d_val_o" -clock "ast.clk_ast_adc_i" + output -name "rng_val_o" -clock "ast.clk_ast_rng_i" + output -name "rng_b_o" -clock "ast.clk_ast_rng_i" + output -name "entropy_req_o" -clock "ast.clk_ast_es_i" + output -name "alert_req_o" -clock "ast.clk_ast_alert_i" + output -name "obs_ctrl_o" -clock "ast.clk_ast_tlul_i" + output -name "all_clk_byp_ack_o" -clock "ast.clk_src_io_o" + output -name "io_clk_byp_ack_o" -clock "ast.clk_src_io_o" + output -name "flash_bist_en_o" -clock "ast.clk_ast_tlul_i" + output -name "dpram_rmf_o" -clock "ast.clk_ast_tlul_i" + output -name "dpram_rml_o" -clock "ast.clk_ast_tlul_i" + output -name "spram_rm_o" -clock "ast.clk_ast_tlul_i" + output -name "sprgf_rm_o" -clock "ast.clk_ast_tlul_i" + output -name "sprom_rm_o" -clock "ast.clk_ast_tlul_i" + output -name "dft_scan_md_o" -clock "ast.clk_ast_tlul_i" + output -name "scan_shift_en_o" -clock "ast.clk_ast_tlul_i" + output -name "scan_reset_no" -clock "ast.clk_ast_tlul_i" + clock -name "clk_src_sys_o" -domain domain7 -tag SG_AUTO_TAG_7 + clock -name "clk_src_aon_o" -domain domain8 -tag SG_AUTO_TAG_8 + clock -name "clk_src_io_o" -domain domain_9 -tag SG_AUTO_TAG_9 + clock -name "clk_src_usb_o" -domain domain_10 -tag SG_AUTO_TAG_10 + reset -name "fla_alert_src_i" -value 0 + reset -name "otp_alert_src_i" -value 0 + quasi_static -name "padmux2ast_i" + quasi_static -name "ast2padmux_o" + quasi_static -name "ast2pad_t0_ao" + quasi_static -name "ast2pad_t1_ao" + +block_file_decompiled_end +} diff --git a/hw/top_darjeeling_no_ibex/ip/ast/defs.bzl b/hw/top_darjeeling_no_ibex/ip/ast/defs.bzl new file mode 100644 index 00000000000..1f742098ed3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/defs.bzl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +AST = opentitan_ip( + name = "ast", + hjson = "//hw/top_darjeeling/ip/ast/data:ast.hjson", +) diff --git a/hw/top_darjeeling_no_ibex/ip/ast/doc/ast_regs.html b/hw/top_darjeeling_no_ibex/ip/ast/doc/ast_regs.html new file mode 100644 index 00000000000..0d6a1a42854 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/doc/ast_regs.html @@ -0,0 +1,773 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Summary
Name Offset Length Description
ast.REGA0 0x0 4

AST Register 0 for OTP/ROM Write Testing
ast.REGA1 0x4 4

AST 1 Register for OTP/ROM Write Testing
ast.REGA2 0x8 4

AST 2 Register for OTP/ROM Write Testing
ast.REGA3 0xc 4

AST 3 Register for OTP/ROM Write Testing
ast.REGA4 0x10 4

AST 4 Register for OTP/ROM Write Testing
ast.REGA5 0x14 4

AST 5 Register for OTP/ROM Write Testing
ast.REGA6 0x18 4

AST 6 Register for OTP/ROM Write Testing
ast.REGA7 0x1c 4

AST 7 Register for OTP/ROM Write Testing
ast.REGA8 0x20 4

AST 8 Register for OTP/ROM Write Testing
ast.REGA9 0x24 4

AST 9 Register for OTP/ROM Write Testing
ast.REGA10 0x28 4

AST 10 Register for OTP/ROM Write Testing
ast.REGA11 0x2c 4

AST 11 Register for OTP/ROM Write Testing
ast.REGA12 0x30 4

AST 13 Register for OTP/ROM Write Testing
ast.REGA13 0x34 4

AST 13 Register for OTP/ROM Write Testing
ast.REGA14 0x38 4

AST 14 Register for OTP/ROM Write Testing
ast.REGA15 0x3c 4

AST 15 Register for OTP/ROM Write Testing
ast.REGA16 0x40 4

AST 16 Register for OTP/ROM Write Testing
ast.REGA17 0x44 4

AST 17 Register for OTP/ROM Write Testing
ast.REGA18 0x48 4

AST 18 Register for OTP/ROM Write Testing
ast.REGA19 0x4c 4

AST 19 Register for OTP/ROM Write Testing
ast.REGA20 0x50 4

AST 20 Register for OTP/ROM Write Testing
ast.REGA21 0x54 4

AST 21 Register for OTP/ROM Write Testing
ast.REGA22 0x58 4

AST 22 Register for OTP/ROM Write Testing
ast.REGA23 0x5c 4

AST 23 Register for OTP/ROM Write Testing
ast.REGA24 0x60 4

AST 24 Register for OTP/ROM Write Testing
ast.REGA25 0x64 4

AST 25 Register for OTP/ROM Write Testing
ast.REGA26 0x68 4

AST 26 Register for OTP/ROM Write Testing
ast.REGA27 0x6c 4

AST 27 Register for OTP/ROM Write Testing
ast.REGA28 0x70 4

AST 28 Register for OTP/ROM Write Testing
ast.REGA29 0x74 4

AST 29 Register for OTP/ROM Write Testing
ast.REGA30 0x78 4

AST 30 Register for OTP/ROM Write Testing
ast.REGA31 0x7c 4

AST 31 Register for OTP/ROM Write Testing
ast.REGA32 0x80 4

AST 32 Register for OTP/ROM Write Testing
ast.REGA33 0x84 4

AST 33 Register for OTP/ROM Write Testing
ast.REGA34 0x88 4

AST 34 Register for OTP/ROM Write Testing
ast.REGA35 0x8c 4

AST 35 Register for OTP/ROM Write Testing
ast.REGA36 0x90 4

AST 36 Register for OTP/ROM Write Testing
ast.REGA37 0x94 4

AST 37 Register for OTP/ROM Write Testing
ast.REGAL 0x98 4

AST Last Register for OTP/ROM Write Testing
ast.REGB_0 0x200 4

AST Registers Array-B to set address space size
ast.REGB_1 0x204 4

AST Registers Array-B to set address space size
ast.REGB_2 0x208 4

AST Registers Array-B to set address space size
ast.REGB_3 0x20c 4

AST Registers Array-B to set address space size
ast.REGB_4 0x210 4

AST Registers Array-B to set address space size
+ + + + +
+
ast.REGA0 @ 0x0
+

AST Register 0 for OTP/ROM Write Testing

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0ro0x0reg32

32-bit Register

+
+ + + + + +
+
ast.REGA1 @ 0x4
+

AST 1 Register for OTP/ROM Write Testing

+
Reset default = 0x1, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0ro0x1reg32

32-bit Register

+
+ + + + + +
+
ast.REGA2 @ 0x8
+

AST 2 Register for OTP/ROM Write Testing

+
Reset default = 0x2, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x2reg32

32-bit Register

+
+ + + + + +
+
ast.REGA3 @ 0xc
+

AST 3 Register for OTP/ROM Write Testing

+
Reset default = 0x3, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x3reg32

32-bit Register

+
+ + + + + +
+
ast.REGA4 @ 0x10
+

AST 4 Register for OTP/ROM Write Testing

+
Reset default = 0x4, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x4reg32

32-bit Register

+
+ + + + + +
+
ast.REGA5 @ 0x14
+

AST 5 Register for OTP/ROM Write Testing

+
Reset default = 0x5, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x5reg32

32-bit Register

+
+ + + + + +
+
ast.REGA6 @ 0x18
+

AST 6 Register for OTP/ROM Write Testing

+
Reset default = 0x6, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x6reg32

32-bit Register

+
+ + + + + +
+
ast.REGA7 @ 0x1c
+

AST 7 Register for OTP/ROM Write Testing

+
Reset default = 0x7, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x7reg32

32-bit Register

+
+ + + + + +
+
ast.REGA8 @ 0x20
+

AST 8 Register for OTP/ROM Write Testing

+
Reset default = 0x8, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x8reg32

32-bit Register

+
+ + + + + +
+
ast.REGA9 @ 0x24
+

AST 9 Register for OTP/ROM Write Testing

+
Reset default = 0x9, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x9reg32

32-bit Register

+
+ + + + + +
+
ast.REGA10 @ 0x28
+

AST 10 Register for OTP/ROM Write Testing

+
Reset default = 0xa, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xareg32

32-bit Register

+
+ + + + + +
+
ast.REGA11 @ 0x2c
+

AST 11 Register for OTP/ROM Write Testing

+
Reset default = 0xb, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xbreg32

32-bit Register

+
+ + + + + +
+
ast.REGA12 @ 0x30
+

AST 13 Register for OTP/ROM Write Testing

+
Reset default = 0xc, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xcreg32

32-bit Register

+
+ + + + + +
+
ast.REGA13 @ 0x34
+

AST 13 Register for OTP/ROM Write Testing

+
Reset default = 0xd, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xdreg32

32-bit Register

+
+ + + + + +
+
ast.REGA14 @ 0x38
+

AST 14 Register for OTP/ROM Write Testing

+
Reset default = 0xe, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xereg32

32-bit Register

+
+ + + + + +
+
ast.REGA15 @ 0x3c
+

AST 15 Register for OTP/ROM Write Testing

+
Reset default = 0xf, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0xfreg32

32-bit Register

+
+ + + + + +
+
ast.REGA16 @ 0x40
+

AST 16 Register for OTP/ROM Write Testing

+
Reset default = 0x10, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x10reg32

32-bit Register

+
+ + + + + +
+
ast.REGA17 @ 0x44
+

AST 17 Register for OTP/ROM Write Testing

+
Reset default = 0x11, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x11reg32

32-bit Register

+
+ + + + + +
+
ast.REGA18 @ 0x48
+

AST 18 Register for OTP/ROM Write Testing

+
Reset default = 0x12, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x12reg32

32-bit Register

+
+ + + + + +
+
ast.REGA19 @ 0x4c
+

AST 19 Register for OTP/ROM Write Testing

+
Reset default = 0x13, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x13reg32

32-bit Register

+
+ + + + + +
+
ast.REGA20 @ 0x50
+

AST 20 Register for OTP/ROM Write Testing

+
Reset default = 0x14, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x14reg32

32-bit Register

+
+ + + + + +
+
ast.REGA21 @ 0x54
+

AST 21 Register for OTP/ROM Write Testing

+
Reset default = 0x15, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x15reg32

32-bit Register

+
+ + + + + +
+
ast.REGA22 @ 0x58
+

AST 22 Register for OTP/ROM Write Testing

+
Reset default = 0x16, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x16reg32

32-bit Register

+
+ + + + + +
+
ast.REGA23 @ 0x5c
+

AST 23 Register for OTP/ROM Write Testing

+
Reset default = 0x17, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x17reg32

32-bit Register

+
+ + + + + +
+
ast.REGA24 @ 0x60
+

AST 24 Register for OTP/ROM Write Testing

+
Reset default = 0x18, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x18reg32

32-bit Register

+
+ + + + + +
+
ast.REGA25 @ 0x64
+

AST 25 Register for OTP/ROM Write Testing

+
Reset default = 0x19, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x19reg32

32-bit Register

+
+ + + + + +
+
ast.REGA26 @ 0x68
+

AST 26 Register for OTP/ROM Write Testing

+
Reset default = 0x1a, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1areg32

32-bit Register

+
+ + + + + +
+
ast.REGA27 @ 0x6c
+

AST 27 Register for OTP/ROM Write Testing

+
Reset default = 0x1b, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1breg32

32-bit Register

+
+ + + + + +
+
ast.REGA28 @ 0x70
+

AST 28 Register for OTP/ROM Write Testing

+
Reset default = 0x1c, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0ro0x1creg32

32-bit Register

+
+ + + + + +
+
ast.REGA29 @ 0x74
+

AST 29 Register for OTP/ROM Write Testing

+
Reset default = 0x1d, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1dreg32

32-bit Register

+
+ + + + + +
+
ast.REGA30 @ 0x78
+

AST 30 Register for OTP/ROM Write Testing

+
Reset default = 0x1e, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1ereg32

32-bit Register

+
+ + + + + +
+
ast.REGA31 @ 0x7c
+

AST 31 Register for OTP/ROM Write Testing

+
Reset default = 0x1f, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x1freg32

32-bit Register

+
+ + + + + +
+
ast.REGA32 @ 0x80
+

AST 32 Register for OTP/ROM Write Testing

+
Reset default = 0x20, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x20reg32

32-bit Register

+
+ + + + + +
+
ast.REGA33 @ 0x84
+

AST 33 Register for OTP/ROM Write Testing

+
Reset default = 0x21, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x21reg32

32-bit Register

+
+ + + + + +
+
ast.REGA34 @ 0x88
+

AST 34 Register for OTP/ROM Write Testing

+
Reset default = 0x22, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x22reg32

32-bit Register

+
+ + + + + +
+
ast.REGA35 @ 0x8c
+

AST 35 Register for OTP/ROM Write Testing

+
Reset default = 0x23, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x23reg32

32-bit Register

+
+ + + + + +
+
ast.REGA36 @ 0x90
+

AST 36 Register for OTP/ROM Write Testing

+
Reset default = 0x24, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x24reg32

32-bit Register

+
+ + + + + +
+
ast.REGA37 @ 0x94
+

AST 37 Register for OTP/ROM Write Testing

+
Reset default = 0x25, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0rw0x25reg32

32-bit Register

+
+ + + + + +
+
ast.REGAL @ 0x98
+

AST Last Register for OTP/ROM Write Testing

+
Reset default = 0x26, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32...
1514131211109876543210
...reg32
BitsTypeResetNameDescription
31:0wo0x26reg32

32-bit Register

+
+ + + + + +
+
ast.REGB_0 @ 0x200
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_0...
1514131211109876543210
...reg32_0
BitsTypeResetNameDescription
31:0rw0x0reg32_0

32-bit Register

+
+ + + + + +
+
ast.REGB_1 @ 0x204
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_1...
1514131211109876543210
...reg32_1
BitsTypeResetNameDescription
31:0rw0x0reg32_1

For REGB1

+
+ + + + + +
+
ast.REGB_2 @ 0x208
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_2...
1514131211109876543210
...reg32_2
BitsTypeResetNameDescription
31:0rw0x0reg32_2

For REGB2

+
+ + + + + +
+
ast.REGB_3 @ 0x20c
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_3...
1514131211109876543210
...reg32_3
BitsTypeResetNameDescription
31:0rw0x0reg32_3

For REGB3

+
+ + + + + +
+
ast.REGB_4 @ 0x210
+

AST Registers Array-B to set address space size

+
Reset default = 0x0, mask 0xffffffff
+
+ + +
31302928272625242322212019181716
reg32_4...
1514131211109876543210
...reg32_4
BitsTypeResetNameDescription
31:0rw0x0reg32_4

For REGB4

+
diff --git a/hw/top_darjeeling_no_ibex/ip/ast/doc/top_diagram.png b/hw/top_darjeeling_no_ibex/ip/ast/doc/top_diagram.png new file mode 100644 index 00000000000..6fbe3c831cc Binary files /dev/null and b/hw/top_darjeeling_no_ibex/ip/ast/doc/top_diagram.png differ diff --git a/hw/top_darjeeling_no_ibex/ip/ast/lib/ast.lib b/hw/top_darjeeling_no_ibex/ip/ast/lib/ast.lib new file mode 100644 index 00000000000..b00839d62c3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/lib/ast.lib @@ -0,0 +1,98919 @@ +brary("ast") { + + technology (cmos) ; + delay_model : table_lookup ; + library_features ( report_delay_calculation ) ; + date : "Mon Oct 3 13:12:25 2022" ; + revision : "P-2019.03-SP3" ; + nom_process : 1.000 ; + nom_voltage : 0.990 ; + nom_temperature : -40.000 ; + operating_conditions( "SSG0P99VN40C" ) { + process : 1.0000 ; + voltage : 0.9900 ; + temperature : -40.0000 ; + } /* current design opcond */ + default_operating_conditions : "SSG0P99VN40C" ; + voltage_unit : "1V" ; + time_unit : "1ns" ; + capacitive_load_unit (1.000000, pf); + slew_derate_from_library : 0.5000 ; + slew_lower_threshold_pct_rise : 30.0000 ; + slew_lower_threshold_pct_fall : 30.0000 ; + slew_upper_threshold_pct_rise : 70.0000 ; + slew_upper_threshold_pct_fall : 70.0000 ; + input_threshold_pct_rise : 50.0000 ; + input_threshold_pct_fall : 50.0000 ; + output_threshold_pct_rise : 50.0000 ; + output_threshold_pct_fall : 50.0000 ; + k_process_cell_rise : 0.000000; + k_process_cell_fall : 0.000000; + k_volt_cell_rise : 0.000000; + k_volt_cell_fall : 0.000000; + k_temp_cell_rise : 0.000000; + k_temp_cell_fall : 0.000000; + k_process_rise_transition : 0.000000; + k_process_fall_transition : 0.000000; + k_volt_rise_transition : 0.000000; + k_volt_fall_transition : 0.000000; + k_temp_rise_transition : 0.000000; + k_temp_fall_transition : 0.000000; + default_fanout_load : 1.000000; + default_inout_pin_cap : 1.000000; + default_input_pin_cap : 1.000000; + default_output_pin_cap : 0.000000; + current_unit : 1mA; + pulling_resistance_unit : "1kohm"; + comment : "PrimeTime extracted Model." ; + + define(min_delay_flag, timing, boolean); + define(internal_noise_peak_time_below_high, pin, float); + define(internal_noise_width_above_low, pin, float); + define(original_pin, pin, string); + define(internal_noise_peak_time_above_low, pin, float); + define(internal_noise_width_below_high, pin, float); + define(internal_noise_height_above_low, pin, float); + define(internal_noise_height_below_high, pin, float); + + + +/* SCALAR table template is built-in */ + +/* 2-D table template f(in_trans, out_cap) */ +lu_table_template( f_itrans_ocap ) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 (" 0.0000, 1.0000 "); + index_2 (" 0.0000, 1.0000 "); +} + +/* 2-D table template f(d_trans, c_trans) */ +lu_table_template( f_dtrans_ctrans ) { + variable_1 : constrained_pin_transition; + variable_2 : related_pin_transition; + index_1 (" 0.0000, 1.0000 "); + index_2 (" 0.0000, 1.0000 "); +} + +/* 3-D table template f(i_trans, o_cap, r_cap) */ +lu_table_template( f_itrans_ocap_rcap ) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + variable_3 : related_out_total_output_net_capacitance; + index_1 (" 0.0000, 1.0000 "); + index_2 (" 0.0000, 1.0000 "); + index_3 (" 0.0000, 1.0000 "); +} + +type ( BUS109_type0 ) { + base_type : array ; + data_type : bit ; + bit_width : 109 ; + bit_from : 108 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS66_type1 ) { + base_type : array ; + data_type : bit ; + bit_width : 66 ; + bit_from : 65 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS27_type2 ) { + base_type : array ; + data_type : bit ; + bit_width : 27 ; + bit_from : 26 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS56_type3 ) { + base_type : array ; + data_type : bit ; + bit_width : 56 ; + bit_from : 55 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS5_type4 ) { + base_type : array ; + data_type : bit ; + bit_width : 5 ; + bit_from : 4 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS2_type5 ) { + base_type : array ; + data_type : bit ; + bit_width : 2 ; + bit_from : 1 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS4_type6 ) { + base_type : array ; + data_type : bit ; + bit_width : 4 ; + bit_from : 3 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS20_type7 ) { + base_type : array ; + data_type : bit ; + bit_width : 20 ; + bit_from : 19 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS10_type8 ) { + base_type : array ; + data_type : bit ; + bit_width : 10 ; + bit_from : 9 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS34_type9 ) { + base_type : array ; + data_type : bit ; + bit_width : 34 ; + bit_from : 33 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS1_type10 ) { + base_type : array ; + data_type : bit ; + bit_width : 1 ; + bit_from : 0 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS52_type11 ) { + base_type : array ; + data_type : bit ; + bit_width : 52 ; + bit_from : 51 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS26_type12 ) { + base_type : array ; + data_type : bit ; + bit_width : 26 ; + bit_from : 25 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS3_type13 ) { + base_type : array ; + data_type : bit ; + bit_width : 3 ; + bit_from : 2 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS8_type14 ) { + base_type : array ; + data_type : bit ; + bit_width : 8 ; + bit_from : 7 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS12_type15 ) { + base_type : array ; + data_type : bit ; + bit_width : 12 ; + bit_from : 11 ; + bit_to : 0 ; +} /* end of type */ +type ( BUS9_type16 ) { + base_type : array ; + data_type : bit ; + bit_width : 9 ; + bit_from : 8 ; + bit_to : 0 ; +} /* end of type */ + +cell( ast ) { + area : 751665.937500 ; + dont_use : true ; + dont_touch : true ; + interface_timing : true; + timing_model_type : "extracted"; + is_macro_cell : true; + +short(tl_o[64], tl_o[63]); + +short(tl_o[64], tl_o[61]); + +short(tl_o[64], tl_o[60]); + +short(tl_o[64], tl_o[59]); + +short(tl_o[64], tl_o[48]); + +short(ast_pwst_o[3], ast_pwst_h_o[3]); + +short(ast_pwst_o[2], ast_pwst_h_o[2]); + +short(ast_pwst_o[1], ast_pwst_h_o[1]); + +short(ast_pwst_o[0], ast_pwst_h_o[0]); +bus ( tl_i ) { + + bus_type : BUS109_type0 ; + direction : input ; + +pin("tl_i[108]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001908 ; + + /* Other user defined attributes. */ + original_pin : tl_i[108]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.014905, 5.968750, 5.938533, 5.927176, 5.940784",\ + "6.095888, 6.049733, 6.019516, 6.008159, 6.021767",\ + "6.180377, 6.134222, 6.104005, 6.092648, 6.106256",\ + "6.321913, 6.275758, 6.245541, 6.234183, 6.247791",\ + "6.558708, 6.512553, 6.482336, 6.470979, 6.484587"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.829596, 4.783441, 4.753223, 4.741866, 4.755474",\ + "4.919121, 4.872966, 4.842749, 4.831391, 4.844999",\ + "5.021051, 4.974896, 4.944679, 4.933322, 4.946930",\ + "5.203711, 5.157556, 5.127338, 5.115981, 5.129589",\ + "5.532049, 5.485894, 5.455677, 5.444320, 5.457928"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[108]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.214260, -0.171883, -0.137304, -0.099668, 0.184188",\ + "-0.301086, -0.258709, -0.224129, -0.186494, 0.097363",\ + "-0.394315, -0.351937, -0.317358, -0.279723, 0.004134",\ + "-0.557199, -0.514821, -0.480242, -0.442607, -0.158750",\ + "-0.829713, -0.787336, -0.752757, -0.715121, -0.431265"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.264841, -0.198767, -0.140880, -0.098858, 0.121356",\ + "-0.356827, -0.290753, -0.232866, -0.190843, 0.029370",\ + "-0.463555, -0.397481, -0.339595, -0.297572, -0.077359",\ + "-0.650171, -0.584097, -0.526210, -0.484188, -0.239846",\ + "-0.884585, -0.842168, -0.807682, -0.768234, -0.461884"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[108]_hldr*/ + +} /* end of pin tl_i[108] */ + +pin("tl_i[107]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005151 ; + + /* Other user defined attributes. */ + original_pin : tl_i[107]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.052649, 5.006495, 4.976278, 4.964921, 4.978528",\ + "5.141132, 5.094977, 5.064761, 5.053403, 5.067011",\ + "5.243252, 5.197097, 5.166880, 5.155523, 5.169130",\ + "5.444744, 5.398589, 5.368372, 5.357015, 5.370623",\ + "5.884084, 5.837929, 5.807712, 5.796355, 5.809962"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.045798, 4.999643, 4.969427, 4.958069, 4.971677",\ + "5.140346, 5.094191, 5.063974, 5.052617, 5.066224",\ + "5.268656, 5.222501, 5.192284, 5.180927, 5.194534",\ + "5.518216, 5.472061, 5.441844, 5.430487, 5.444095",\ + "5.954391, 5.908237, 5.878020, 5.866663, 5.880270"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[107]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.187805, -0.145419, -0.110860, -0.072826, 0.215981",\ + "-0.265352, -0.222966, -0.188407, -0.150372, 0.138434",\ + "-0.358696, -0.316325, -0.281731, -0.244378, 0.035979",\ + "-0.536472, -0.494140, -0.459456, -0.423841, -0.165061",\ + "-0.854036, -0.811811, -0.776879, -0.746068, -0.546918"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.171733, -0.105842, -0.048217, -0.006266, 0.214402",\ + "-0.262898, -0.197007, -0.139383, -0.097431, 0.123236",\ + "-0.377606, -0.311610, -0.253836, -0.211843, 0.008564",\ + "-0.589409, -0.523083, -0.464836, -0.422715, -0.203127",\ + "-0.959255, -0.892271, -0.833079, -0.790704, -0.572752"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[107]_hldr*/ + +} /* end of pin tl_i[107] */ + +pin("tl_i[106]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004836 ; + + /* Other user defined attributes. */ + original_pin : tl_i[106]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.118081, 5.071926, 5.041709, 5.030352, 5.043960",\ + "5.207886, 5.161731, 5.131514, 5.120157, 5.133764",\ + "5.325253, 5.279098, 5.248881, 5.237524, 5.251131",\ + "5.541330, 5.495175, 5.464959, 5.453601, 5.467209",\ + "5.904454, 5.858299, 5.828083, 5.816725, 5.830333"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.110147, 5.063992, 5.033775, 5.022418, 5.036025",\ + "5.198250, 5.152095, 5.121878, 5.110521, 5.124128",\ + "5.332071, 5.285916, 5.255700, 5.244342, 5.257950",\ + "5.577984, 5.531829, 5.501612, 5.490255, 5.503862",\ + "5.995383, 5.949228, 5.919012, 5.907654, 5.921262"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[106]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.198447, -0.132584, -0.074998, -0.033057, 0.187678",\ + "-0.296196, -0.230332, -0.172747, -0.130806, 0.089930",\ + "-0.398836, -0.332973, -0.275387, -0.233446, -0.012711",\ + "-0.579500, -0.513636, -0.456051, -0.414110, -0.193375",\ + "-0.884380, -0.818360, -0.760550, -0.718548, -0.498201"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.292019, -0.249633, -0.215074, -0.177056, 0.111552",\ + "-0.374431, -0.332045, -0.297485, -0.259467, 0.029140",\ + "-0.488086, -0.445700, -0.411141, -0.373122, -0.084515",\ + "-0.684457, -0.642085, -0.607494, -0.570100, -0.289245",\ + "-1.001110, -0.958772, -0.924101, -0.888239, -0.626398"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[106]_hldr*/ + +} /* end of pin tl_i[106] */ + +pin("tl_i[105]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003624 ; + + /* Other user defined attributes. */ + original_pin : tl_i[105]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.863893, 4.817738, 4.787521, 4.776164, 4.789771",\ + "4.956792, 4.910637, 4.880420, 4.869063, 4.882670",\ + "5.049713, 5.003558, 4.973341, 4.961984, 4.975592",\ + "5.212534, 5.166379, 5.136162, 5.124805, 5.138412",\ + "5.493520, 5.447365, 5.417148, 5.405791, 5.419398"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.894609, 4.848454, 4.818238, 4.806880, 4.820488",\ + "4.991653, 4.945498, 4.915282, 4.903924, 4.917532",\ + "5.091967, 5.045812, 5.015595, 5.004238, 5.017845",\ + "5.268436, 5.222281, 5.192065, 5.180707, 5.194315",\ + "5.577918, 5.531763, 5.501546, 5.490189, 5.503797"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[105]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.191328, -0.125448, -0.067841, -0.025894, 0.194803",\ + "-0.284713, -0.218834, -0.161226, -0.119279, 0.101417",\ + "-0.376971, -0.311091, -0.253484, -0.211536, 0.009160",\ + "-0.536682, -0.470803, -0.413195, -0.371248, -0.150551",\ + "-0.807364, -0.741369, -0.683595, -0.641603, -0.421195"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.219051, -0.176666, -0.142105, -0.104110, 0.184210",\ + "-0.313450, -0.271065, -0.236504, -0.198509, 0.089812",\ + "-0.408426, -0.366041, -0.331480, -0.293485, -0.005164",\ + "-0.576090, -0.533704, -0.499144, -0.461149, -0.172828",\ + "-0.853410, -0.811045, -0.776438, -0.739355, -0.462356"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[105]_hldr*/ + +} /* end of pin tl_i[105] */ + +pin("tl_i[104]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[104]; +} /* end of pin tl_i[104] */ + +pin("tl_i[103]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[103]; +} /* end of pin tl_i[103] */ + +pin("tl_i[102]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[102]; +} /* end of pin tl_i[102] */ + +pin("tl_i[101]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002631 ; + + /* Other user defined attributes. */ + original_pin : tl_i[101]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.040158, 3.994009, 3.963793, 3.952436, 3.966046",\ + "4.127818, 4.081669, 4.051453, 4.040096, 4.053706",\ + "4.214727, 4.168579, 4.138362, 4.127005, 4.140615",\ + "4.367462, 4.321313, 4.291097, 4.279740, 4.293350",\ + "4.608571, 4.562422, 4.532206, 4.520849, 4.534459"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.240349, 4.194201, 4.163985, 4.152627, 4.166238",\ + "4.323653, 4.277504, 4.247288, 4.235931, 4.249541",\ + "4.439158, 4.393010, 4.362793, 4.351436, 4.365047",\ + "4.634571, 4.588422, 4.558206, 4.546849, 4.560459",\ + "4.954862, 4.908714, 4.878498, 4.867140, 4.880751"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[101]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[101]_hldr*/ + +} /* end of pin tl_i[101] */ + +pin("tl_i[100]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002123 ; + + /* Other user defined attributes. */ + original_pin : tl_i[100]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.031560, 3.985412, 3.955196, 3.943839, 3.957449",\ + "4.118053, 4.071905, 4.041688, 4.030331, 4.043941",\ + "4.209411, 4.163263, 4.133047, 4.121689, 4.135300",\ + "4.373650, 4.327502, 4.297286, 4.285928, 4.299539",\ + "4.639607, 4.593459, 4.563242, 4.551885, 4.565495"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.345016, 4.298868, 4.268651, 4.257294, 4.270905",\ + "4.436058, 4.389909, 4.359693, 4.348336, 4.361946",\ + "4.527231, 4.481082, 4.450866, 4.439509, 4.453119",\ + "4.689745, 4.643597, 4.613381, 4.602024, 4.615634",\ + "4.957426, 4.911277, 4.881061, 4.869704, 4.883314"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[100]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[100]_hldr*/ + +} /* end of pin tl_i[100] */ + +pin("tl_i[99]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[99]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[99]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[99]_hldr*/ + +} /* end of pin tl_i[99] */ + +pin("tl_i[98]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[98]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[98]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[98]_hldr*/ + +} /* end of pin tl_i[98] */ + +pin("tl_i[97]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[97]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[97]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[97]_hldr*/ + +} /* end of pin tl_i[97] */ + +pin("tl_i[96]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[96]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[96]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[96]_hldr*/ + +} /* end of pin tl_i[96] */ + +pin("tl_i[95]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[95]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[95]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[95]_hldr*/ + +} /* end of pin tl_i[95] */ + +pin("tl_i[94]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[94]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[94]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[94]_hldr*/ + +} /* end of pin tl_i[94] */ + +pin("tl_i[93]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[93]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[93]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[93]_hldr*/ + +} /* end of pin tl_i[93] */ + +pin("tl_i[92]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000562 ; + + /* Other user defined attributes. */ + original_pin : tl_i[92]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.202977, 0.157053, 0.126854, 0.115510, 0.129197",\ + "0.287655, 0.241731, 0.211532, 0.200188, 0.213875",\ + "0.378849, 0.332759, 0.302547, 0.291193, 0.304823",\ + "0.542220, 0.495729, 0.465486, 0.454109, 0.467602",\ + "0.818496, 0.771022, 0.740703, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.245106, 0.169786, 0.101633, 0.078675, 0.141673",\ + "0.333057, 0.257736, 0.189583, 0.166625, 0.229623",\ + "0.433433, 0.358121, 0.290014, 0.267131, 0.330810",\ + "0.619112, 0.543823, 0.475835, 0.453147, 0.518594",\ + "0.940670, 0.865438, 0.797763, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[92]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.058015, -0.018552, 0.287989",\ + "-0.219595, -0.177177, -0.142692, -0.103229, 0.203312",\ + "-0.310658, -0.268270, -0.233715, -0.195609, 0.094094",\ + "-0.473587, -0.431270, -0.396549, -0.361659, -0.111869",\ + "-0.749178, -0.707041, -0.671904, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.158345, -0.092411, -0.034724, 0.007245, 0.227804",\ + "-0.246288, -0.180354, -0.122667, -0.080698, 0.139861",\ + "-0.346722, -0.280644, -0.222751, -0.180726, 0.039476",\ + "-0.532525, -0.466073, -0.407644, -0.365475, -0.146201",\ + "-0.854381, -0.786954, -0.727126, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[92]_hldr*/ + +} /* end of pin tl_i[92] */ + +pin("tl_i[91]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001976 ; + + /* Other user defined attributes. */ + original_pin : tl_i[91]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.041809, 5.995654, 5.965437, 5.954080, 5.967688",\ + "6.129841, 6.083686, 6.053469, 6.042112, 6.055719",\ + "6.240180, 6.194025, 6.163808, 6.152451, 6.166058",\ + "6.431971, 6.385816, 6.355599, 6.344242, 6.357849",\ + "6.749926, 6.703771, 6.673554, 6.662197, 6.675805"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.036389, 5.990234, 5.960017, 5.948660, 5.962267",\ + "6.118236, 6.072081, 6.041864, 6.030507, 6.044114",\ + "6.243943, 6.197788, 6.167572, 6.156214, 6.169822",\ + "6.470764, 6.424609, 6.394392, 6.383035, 6.396643",\ + "6.863174, 6.817019, 6.786803, 6.775445, 6.789053"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[91]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.151672, -1.109295, -1.074716, -1.037080, -0.753224",\ + "-1.243671, -1.201294, -1.166714, -1.129079, -0.845222",\ + "-1.323829, -1.281452, -1.246872, -1.209237, -0.925380",\ + "-1.441613, -1.399235, -1.364656, -1.327021, -1.043164",\ + "-1.629556, -1.587178, -1.552599, -1.514964, -1.231107"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.146252, -1.103875, -1.069295, -1.031660, -0.747803",\ + "-1.232066, -1.189688, -1.155109, -1.117473, -0.833617",\ + "-1.316872, -1.274495, -1.239915, -1.202280, -0.918423",\ + "-1.462124, -1.419747, -1.385167, -1.347532, -1.063675",\ + "-1.705527, -1.663150, -1.628571, -1.590935, -1.307079"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[91]_hldr*/ + +} /* end of pin tl_i[91] */ + +pin("tl_i[90]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003090 ; + + /* Other user defined attributes. */ + original_pin : tl_i[90]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.559815, 5.513660, 5.483444, 5.472086, 5.485694",\ + "5.649643, 5.603488, 5.573271, 5.561914, 5.575521",\ + "5.741996, 5.695841, 5.665624, 5.654267, 5.667874",\ + "5.908573, 5.862418, 5.832201, 5.820844, 5.834452",\ + "6.303185, 6.257030, 6.226814, 6.215456, 6.229064"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.570656, 5.524501, 5.494284, 5.482927, 5.496534",\ + "5.661279, 5.615124, 5.584907, 5.573550, 5.587157",\ + "5.780371, 5.734216, 5.703999, 5.692642, 5.706249",\ + "6.016336, 5.970181, 5.939964, 5.928607, 5.942214",\ + "6.443535, 6.397380, 6.367163, 6.355806, 6.369413"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[90]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.123815, -1.081437, -1.046858, -1.009223, -0.725366",\ + "-1.217456, -1.175079, -1.140499, -1.102864, -0.819007",\ + "-1.332136, -1.289759, -1.255179, -1.217544, -0.933687",\ + "-1.517521, -1.475144, -1.440564, -1.402929, -1.119072",\ + "-1.805479, -1.763102, -1.728523, -1.690887, -1.407031"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.159454, -1.117077, -1.082498, -1.044862, -0.761006",\ + "-1.250402, -1.208025, -1.173445, -1.135810, -0.851953",\ + "-1.352041, -1.309663, -1.275084, -1.237449, -0.953592",\ + "-1.534891, -1.492514, -1.457935, -1.420299, -1.136443",\ + "-1.849478, -1.807101, -1.772522, -1.734886, -1.451030"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[90]_hldr*/ + +} /* end of pin tl_i[90] */ + +pin("tl_i[89]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002521 ; + + /* Other user defined attributes. */ + original_pin : tl_i[89]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.812771, 5.766616, 5.736399, 5.725042, 5.738649",\ + "5.898168, 5.852013, 5.821796, 5.810439, 5.824046",\ + "5.975654, 5.929499, 5.899282, 5.887925, 5.901533",\ + "6.119768, 6.073613, 6.043396, 6.032039, 6.045647",\ + "6.477526, 6.431371, 6.401154, 6.389797, 6.403404"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.809771, 5.763616, 5.733399, 5.722042, 5.735649",\ + "5.892390, 5.846235, 5.816019, 5.804661, 5.818269",\ + "6.004417, 5.958262, 5.928046, 5.916688, 5.930296",\ + "6.234746, 6.188591, 6.158375, 6.147017, 6.160625",\ + "6.638525, 6.592370, 6.562153, 6.550796, 6.564404"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[89]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.029578, -0.987200, -0.952621, -0.914986, -0.631129",\ + "-1.117165, -1.074787, -1.040208, -1.002573, -0.718716",\ + "-1.206337, -1.163960, -1.129380, -1.091745, -0.807888",\ + "-1.362213, -1.319836, -1.285257, -1.247621, -0.963765",\ + "-1.590532, -1.548155, -1.513575, -1.475940, -1.192083"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.059949, -1.017572, -0.982993, -0.945357, -0.661501",\ + "-1.159550, -1.117173, -1.082594, -1.044958, -0.761102",\ + "-1.261636, -1.219259, -1.184679, -1.147044, -0.863187",\ + "-1.441043, -1.398666, -1.364086, -1.326451, -1.042594",\ + "-1.748482, -1.706105, -1.671526, -1.633890, -1.350034"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[89]_hldr*/ + +} /* end of pin tl_i[89] */ + +pin("tl_i[88]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001007 ; + + /* Other user defined attributes. */ + original_pin : tl_i[88]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.471457, 5.425303, 5.395086, 5.383729, 5.397336",\ + "5.567654, 5.521499, 5.491282, 5.479925, 5.493532",\ + "5.669107, 5.622952, 5.592736, 5.581378, 5.594986",\ + "5.849272, 5.803117, 5.772900, 5.761543, 5.775150",\ + "6.163116, 6.116961, 6.086744, 6.075387, 6.088994"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.500805, 5.454650, 5.424433, 5.413076, 5.426683",\ + "5.598975, 5.552820, 5.522604, 5.511246, 5.524854",\ + "5.704100, 5.657945, 5.627728, 5.616371, 5.629978",\ + "5.884839, 5.838684, 5.808467, 5.797110, 5.810718",\ + "6.188713, 6.142558, 6.112341, 6.100984, 6.114592"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[88]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.083938, -1.041561, -1.006981, -0.969346, -0.685489",\ + "-1.181137, -1.138760, -1.104181, -1.066545, -0.782689",\ + "-1.281549, -1.239172, -1.204592, -1.166957, -0.883101",\ + "-1.453069, -1.410691, -1.376112, -1.338477, -1.054620",\ + "-1.733325, -1.690947, -1.656368, -1.618733, -1.334876"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.081498, -1.039121, -1.004542, -0.966906, -0.683050",\ + "-1.178693, -1.136315, -1.101736, -1.064101, -0.780244",\ + "-1.285877, -1.243499, -1.208920, -1.171285, -0.887428",\ + "-1.474000, -1.431623, -1.397043, -1.359408, -1.075551",\ + "-1.791995, -1.749618, -1.715039, -1.677403, -1.393547"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[88]_hldr*/ + +} /* end of pin tl_i[88] */ + +pin("tl_i[87]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001007 ; + + /* Other user defined attributes. */ + original_pin : tl_i[87]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.100426, 6.054271, 6.024055, 6.012697, 6.026305",\ + "6.196661, 6.150506, 6.120289, 6.108932, 6.122540",\ + "6.301589, 6.255434, 6.225217, 6.213860, 6.227468",\ + "6.487259, 6.441104, 6.410888, 6.399530, 6.413138",\ + "6.807995, 6.761840, 6.731623, 6.720266, 6.733873"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.124471, 6.078316, 6.048099, 6.036742, 6.050349",\ + "6.222617, 6.176462, 6.146245, 6.134888, 6.148495",\ + "6.331584, 6.285429, 6.255212, 6.243855, 6.257463",\ + "6.520377, 6.474222, 6.444005, 6.432648, 6.446256",\ + "6.841649, 6.795494, 6.765277, 6.753920, 6.767528"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[87]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.134100, -1.091722, -1.057143, -1.019508, -0.735651",\ + "-1.231353, -1.188975, -1.154396, -1.116761, -0.832904",\ + "-1.331896, -1.289519, -1.254940, -1.217304, -0.933448",\ + "-1.503641, -1.461264, -1.426684, -1.389049, -1.105192",\ + "-1.784290, -1.741913, -1.707334, -1.669698, -1.385842"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.132025, -1.089648, -1.055068, -1.017433, -0.733576",\ + "-1.229244, -1.186866, -1.152287, -1.114652, -0.830795",\ + "-1.336593, -1.294216, -1.259636, -1.222001, -0.938144",\ + "-1.525111, -1.482733, -1.448154, -1.410519, -1.126662",\ + "-1.844292, -1.801915, -1.767335, -1.729700, -1.445843"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[87]_hldr*/ + +} /* end of pin tl_i[87] */ + +pin("tl_i[86]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002623 ; + + /* Other user defined attributes. */ + original_pin : tl_i[86]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.848853, 5.802698, 5.772481, 5.761124, 5.774731",\ + "5.936358, 5.890203, 5.859987, 5.848629, 5.862237",\ + "6.023653, 5.977498, 5.947281, 5.935924, 5.949532",\ + "6.191101, 6.144946, 6.114729, 6.103372, 6.116980",\ + "6.582396, 6.536241, 6.506024, 6.494667, 6.508274"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.843520, 5.797365, 5.767148, 5.755791, 5.769399",\ + "5.932423, 5.886268, 5.856051, 5.844694, 5.858301",\ + "6.047498, 6.001343, 5.971126, 5.959769, 5.973376",\ + "6.285758, 6.239603, 6.209386, 6.198029, 6.211636",\ + "6.722472, 6.676317, 6.646101, 6.634743, 6.648351"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[86]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.087246, -1.044869, -1.010289, -0.972654, -0.688797",\ + "-1.172364, -1.129987, -1.095407, -1.057772, -0.773916",\ + "-1.269076, -1.226699, -1.192120, -1.154484, -0.870628",\ + "-1.437615, -1.395237, -1.360658, -1.323022, -1.039166",\ + "-1.686824, -1.644446, -1.609867, -1.572232, -1.288375"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.118792, -1.076414, -1.041835, -1.004200, -0.720343",\ + "-1.209484, -1.167107, -1.132527, -1.094892, -0.811035",\ + "-1.302947, -1.260570, -1.225991, -1.188355, -0.904499",\ + "-1.465349, -1.422972, -1.388392, -1.350757, -1.066900",\ + "-1.738277, -1.695899, -1.661320, -1.623685, -1.339828"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[86]_hldr*/ + +} /* end of pin tl_i[86] */ + +pin("tl_i[85]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003219 ; + + /* Other user defined attributes. */ + original_pin : tl_i[85]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.640028, 5.593873, 5.563656, 5.552299, 5.565907",\ + "5.724194, 5.678039, 5.647822, 5.636465, 5.650072",\ + "5.805078, 5.758923, 5.728706, 5.717349, 5.730957",\ + "5.946632, 5.900477, 5.870261, 5.858903, 5.872511",\ + "6.188352, 6.142197, 6.111980, 6.100623, 6.114231"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.625210, 5.579055, 5.548838, 5.537481, 5.551088",\ + "5.706786, 5.660631, 5.630414, 5.619057, 5.632665",\ + "5.812987, 5.766832, 5.736616, 5.725258, 5.738866",\ + "6.001375, 5.955220, 5.925003, 5.913646, 5.927253",\ + "6.317180, 6.271025, 6.240808, 6.229451, 6.243059"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[85]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.041623, -0.999245, -0.964666, -0.927031, -0.643174",\ + "-1.126700, -1.084323, -1.049744, -1.012108, -0.728252",\ + "-1.223403, -1.181025, -1.146446, -1.108811, -0.824954",\ + "-1.391917, -1.349539, -1.314960, -1.277325, -0.993468",\ + "-1.638337, -1.595960, -1.561380, -1.523745, -1.239888"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.073138, -1.030761, -0.996182, -0.958546, -0.674690",\ + "-1.161118, -1.118740, -1.084161, -1.046526, -0.762669",\ + "-1.257352, -1.214975, -1.180395, -1.142760, -0.858903",\ + "-1.419670, -1.377293, -1.342714, -1.305078, -1.021222",\ + "-1.692554, -1.650177, -1.615597, -1.577962, -1.294106"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[85]_hldr*/ + +} /* end of pin tl_i[85] */ + +pin("tl_i[84]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001002 ; + + /* Other user defined attributes. */ + original_pin : tl_i[84]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.863610, 5.817455, 5.787239, 5.775881, 5.789489",\ + "5.963272, 5.917117, 5.886900, 5.875543, 5.889151",\ + "6.072519, 6.026364, 5.996147, 5.984790, 5.998397",\ + "6.263348, 6.217193, 6.186976, 6.175619, 6.189227",\ + "6.585179, 6.539024, 6.508808, 6.497450, 6.511058"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.949015, 5.902860, 5.872643, 5.861286, 5.874893",\ + "6.048979, 6.002824, 5.972607, 5.961250, 5.974857",\ + "6.167165, 6.121010, 6.090793, 6.079436, 6.093043",\ + "6.365981, 6.319826, 6.289609, 6.278252, 6.291860",\ + "6.701097, 6.654942, 6.624725, 6.613368, 6.626975"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[84]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.056499, -1.014122, -0.979543, -0.941907, -0.658051",\ + "-1.146680, -1.104303, -1.069723, -1.032088, -0.748231",\ + "-1.259394, -1.217017, -1.182437, -1.144802, -0.860945",\ + "-1.443621, -1.401244, -1.366664, -1.329029, -1.045172",\ + "-1.712122, -1.669745, -1.635165, -1.597530, -1.313673"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.090162, -1.047785, -1.013205, -0.975570, -0.691713",\ + "-1.180082, -1.137704, -1.103125, -1.065490, -0.781633",\ + "-1.275585, -1.233208, -1.198629, -1.160993, -0.877137",\ + "-1.445900, -1.403523, -1.368944, -1.331308, -1.047452",\ + "-1.745297, -1.702920, -1.668340, -1.630705, -1.346848"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[84]_hldr*/ + +} /* end of pin tl_i[84] */ + +pin("tl_i[83]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003541 ; + + /* Other user defined attributes. */ + original_pin : tl_i[83]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.687950, 5.641795, 5.611578, 5.600221, 5.613829",\ + "5.774795, 5.728640, 5.698423, 5.687066, 5.700673",\ + "5.876379, 5.830224, 5.800007, 5.788650, 5.802258",\ + "6.080298, 6.034143, 6.003927, 5.992569, 6.006177",\ + "6.432961, 6.386806, 6.356589, 6.345232, 6.358839"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.703408, 5.657253, 5.627037, 5.615679, 5.629287",\ + "5.789980, 5.743825, 5.713608, 5.702251, 5.715858",\ + "5.917695, 5.871540, 5.841323, 5.829966, 5.843574",\ + "6.190283, 6.144128, 6.113912, 6.102554, 6.116162",\ + "6.660905, 6.614750, 6.584533, 6.573176, 6.586783"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[83]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.867726, -0.825349, -0.790770, -0.753134, -0.469278",\ + "-0.951320, -0.908943, -0.874363, -0.836728, -0.552871",\ + "-1.016544, -0.974167, -0.939588, -0.901952, -0.618096",\ + "-1.123735, -1.081358, -1.046778, -1.009143, -0.725286",\ + "-1.291921, -1.249544, -1.214964, -1.177329, -0.893472"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.911896, -0.869519, -0.833451, -0.791428, -0.513448",\ + "-1.012793, -0.970416, -0.921834, -0.879811, -0.614345",\ + "-1.095336, -1.052959, -1.000425, -0.958402, -0.696888",\ + "-1.226252, -1.183874, -1.131083, -1.089060, -0.827803",\ + "-1.440278, -1.397901, -1.344258, -1.302235, -1.041830"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[83]_hldr*/ + +} /* end of pin tl_i[83] */ + +pin("tl_i[82]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002444 ; + + /* Other user defined attributes. */ + original_pin : tl_i[82]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.708182, 5.662027, 5.631811, 5.620453, 5.634061",\ + "5.801434, 5.755279, 5.725062, 5.713705, 5.727312",\ + "5.894579, 5.848424, 5.818208, 5.806850, 5.820458",\ + "6.057735, 6.011580, 5.981363, 5.970006, 5.983613",\ + "6.337201, 6.291046, 6.260829, 6.249472, 6.263080"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.710078, 5.663923, 5.633707, 5.622349, 5.635957",\ + "5.807050, 5.760895, 5.730678, 5.719321, 5.732928",\ + "5.905420, 5.859265, 5.829048, 5.817691, 5.831298",\ + "6.075630, 6.029475, 5.999258, 5.987901, 6.001508",\ + "6.350610, 6.304455, 6.274238, 6.262881, 6.276488"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[82]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.931103, -0.888726, -0.854147, -0.816511, -0.532655",\ + "-1.016007, -0.973630, -0.939050, -0.901415, -0.617558",\ + "-1.106769, -1.064392, -1.029812, -0.992177, -0.708320",\ + "-1.260793, -1.218416, -1.183836, -1.146201, -0.862344",\ + "-1.523812, -1.481435, -1.446856, -1.409220, -1.125364"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.978443, -0.936065, -0.901486, -0.863851, -0.579994",\ + "-1.073078, -1.030701, -0.996121, -0.958486, -0.674629",\ + "-1.181049, -1.138672, -1.104093, -1.066457, -0.782601",\ + "-1.371690, -1.329313, -1.294734, -1.257098, -0.973242",\ + "-1.704884, -1.662507, -1.627928, -1.590292, -1.306436"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[82]_hldr*/ + +} /* end of pin tl_i[82] */ + +pin("tl_i[81]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002980 ; + + /* Other user defined attributes. */ + original_pin : tl_i[81]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.772726, 5.726571, 5.696354, 5.684997, 5.698605",\ + "5.867767, 5.821612, 5.791396, 5.780038, 5.793646",\ + "5.991376, 5.945221, 5.915004, 5.903647, 5.917254",\ + "6.241336, 6.195181, 6.164964, 6.153607, 6.167214",\ + "6.709605, 6.663450, 6.633233, 6.621876, 6.635483"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.760269, 5.714114, 5.683897, 5.672540, 5.686147",\ + "5.853128, 5.806973, 5.776756, 5.765399, 5.779006",\ + "5.986612, 5.940457, 5.910241, 5.898883, 5.912491",\ + "6.273496, 6.227341, 6.197124, 6.185767, 6.199374",\ + "6.818243, 6.772088, 6.741871, 6.730514, 6.744122"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[81]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.928193, -0.885816, -0.851236, -0.813601, -0.529744",\ + "-1.010898, -0.968521, -0.933941, -0.896306, -0.612449",\ + "-1.110272, -1.067895, -1.033316, -0.995680, -0.711824",\ + "-1.278434, -1.236057, -1.201477, -1.163842, -0.879985",\ + "-1.568159, -1.525781, -1.491202, -1.453566, -1.169710"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.972769, -0.930391, -0.895812, -0.858176, -0.574320",\ + "-1.064861, -1.022484, -0.987905, -0.950269, -0.666413",\ + "-1.170576, -1.128199, -1.093619, -1.055984, -0.772127",\ + "-1.359091, -1.316714, -1.282135, -1.244499, -0.960643",\ + "-1.694739, -1.652362, -1.617782, -1.580147, -1.296290"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[81]_hldr*/ + +} /* end of pin tl_i[81] */ + +pin("tl_i[80]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004096 ; + + /* Other user defined attributes. */ + original_pin : tl_i[80]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.423539, 5.377384, 5.347167, 5.335810, 5.349418",\ + "5.507660, 5.461505, 5.431288, 5.419931, 5.433538",\ + "5.588662, 5.542507, 5.512290, 5.500933, 5.514540",\ + "5.729993, 5.683838, 5.653621, 5.642264, 5.655871",\ + "5.971819, 5.925664, 5.895447, 5.884090, 5.897697"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.408631, 5.362476, 5.332260, 5.320902, 5.334510",\ + "5.490341, 5.444186, 5.413970, 5.402612, 5.416220",\ + "5.596552, 5.550397, 5.520180, 5.508823, 5.522430",\ + "5.784794, 5.738639, 5.708422, 5.697065, 5.710672",\ + "6.157783, 6.111628, 6.081411, 6.070054, 6.083661"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[80]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.991939, -0.949562, -0.914982, -0.877347, -0.593490",\ + "-1.074940, -1.032563, -0.997983, -0.960348, -0.676491",\ + "-1.172758, -1.130381, -1.095802, -1.058166, -0.774310",\ + "-1.338347, -1.295969, -1.261390, -1.223755, -0.939898",\ + "-1.624824, -1.582447, -1.547868, -1.510232, -1.226376"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.037009, -0.994632, -0.960053, -0.922417, -0.638561",\ + "-1.129460, -1.087082, -1.052503, -1.014868, -0.731011",\ + "-1.235564, -1.193187, -1.158608, -1.120972, -0.837116",\ + "-1.410576, -1.368199, -1.333619, -1.295984, -1.012127",\ + "-1.676313, -1.633936, -1.599356, -1.561721, -1.277864"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[80]_hldr*/ + +} /* end of pin tl_i[80] */ + +pin("tl_i[79]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001007 ; + + /* Other user defined attributes. */ + original_pin : tl_i[79]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.446656, 5.400501, 5.370284, 5.358927, 5.372534",\ + "5.547154, 5.500999, 5.470783, 5.459425, 5.473033",\ + "5.662600, 5.616445, 5.586228, 5.574871, 5.588478",\ + "5.873106, 5.826951, 5.796734, 5.785377, 5.798985",\ + "6.242186, 6.196031, 6.165814, 6.154457, 6.168064"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.480749, 5.434594, 5.404377, 5.393020, 5.406628",\ + "5.579840, 5.533685, 5.503468, 5.492111, 5.505718",\ + "5.703683, 5.657528, 5.627311, 5.615954, 5.629561",\ + "5.911795, 5.865640, 5.835423, 5.824066, 5.837673",\ + "6.265936, 6.219781, 6.189564, 6.178207, 6.191814"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[79]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.093242, -1.050865, -1.016285, -0.978650, -0.694793",\ + "-1.195110, -1.152733, -1.118154, -1.080518, -0.796662",\ + "-1.314294, -1.271917, -1.237338, -1.199702, -0.915846",\ + "-1.525733, -1.483356, -1.448776, -1.411141, -1.127284",\ + "-1.885126, -1.842748, -1.808169, -1.770533, -1.486677"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.071935, -1.029557, -0.994978, -0.957343, -0.673486",\ + "-1.171764, -1.129387, -1.094808, -1.057172, -0.773316",\ + "-1.298104, -1.255727, -1.221148, -1.183512, -0.899656",\ + "-1.517193, -1.474816, -1.440237, -1.402601, -1.118745",\ + "-1.889590, -1.847213, -1.812633, -1.774998, -1.491141"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[79]_hldr*/ + +} /* end of pin tl_i[79] */ + +pin("tl_i[78]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002174 ; + + /* Other user defined attributes. */ + original_pin : tl_i[78]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.182078, 5.135923, 5.105707, 5.094349, 5.107957",\ + "5.277516, 5.231361, 5.201145, 5.189787, 5.203395",\ + "5.400351, 5.354196, 5.323979, 5.312622, 5.326229",\ + "5.638412, 5.592257, 5.562040, 5.550683, 5.564290",\ + "6.058977, 6.012822, 5.982605, 5.971248, 5.984856"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.163897, 5.117742, 5.087525, 5.076168, 5.089776",\ + "5.262290, 5.216135, 5.185918, 5.174561, 5.188169",\ + "5.405017, 5.358862, 5.328645, 5.317288, 5.330895",\ + "5.691147, 5.644992, 5.614775, 5.603418, 5.617025",\ + "6.209457, 6.163302, 6.133085, 6.121728, 6.135335"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[78]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.808182, -0.765804, -0.731225, -0.693590, -0.409733",\ + "-0.891099, -0.848721, -0.814142, -0.776506, -0.492650",\ + "-0.960506, -0.918129, -0.883550, -0.845914, -0.562058",\ + "-1.077306, -1.034929, -1.000349, -0.962714, -0.678857",\ + "-1.260451, -1.218073, -1.183494, -1.145859, -0.862002"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.822461, -0.780084, -0.745505, -0.707869, -0.424013",\ + "-0.907616, -0.865238, -0.830659, -0.793024, -0.509167",\ + "-0.995187, -0.952809, -0.918230, -0.880595, -0.596738",\ + "-1.146480, -1.104103, -1.069523, -1.031888, -0.748031",\ + "-1.401185, -1.358808, -1.324229, -1.286593, -1.002737"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[78]_hldr*/ + +} /* end of pin tl_i[78] */ + +pin("tl_i[77]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001980 ; + + /* Other user defined attributes. */ + original_pin : tl_i[77]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.530322, 5.484167, 5.453950, 5.442593, 5.456201",\ + "5.617828, 5.571673, 5.541456, 5.530099, 5.543706",\ + "5.705123, 5.658968, 5.628751, 5.617394, 5.631001",\ + "5.872606, 5.826451, 5.796235, 5.784877, 5.798485",\ + "6.261807, 6.215652, 6.185436, 6.174078, 6.187686"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.524989, 5.478834, 5.448617, 5.437260, 5.450868",\ + "5.613892, 5.567737, 5.537520, 5.526163, 5.539771",\ + "5.728968, 5.682813, 5.652596, 5.641239, 5.654846",\ + "5.967242, 5.921087, 5.890870, 5.879513, 5.893120",\ + "6.403997, 6.357842, 6.327626, 6.316268, 6.329876"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[77]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.941463, -0.899085, -0.864506, -0.826870, -0.543014",\ + "-1.026243, -0.983865, -0.949286, -0.911651, -0.627794",\ + "-1.097818, -1.055441, -1.020861, -0.983226, -0.699369",\ + "-1.219287, -1.176910, -1.142331, -1.104695, -0.820839",\ + "-1.414036, -1.371659, -1.337079, -1.299444, -1.015587"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.962457, -0.920079, -0.885500, -0.847865, -0.564008",\ + "-1.048641, -1.006264, -0.971684, -0.934049, -0.650192",\ + "-1.136345, -1.093968, -1.059388, -1.021753, -0.737896",\ + "-1.287015, -1.244637, -1.210058, -1.172423, -0.888566",\ + "-1.540997, -1.498620, -1.464041, -1.426405, -1.142549"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[77]_hldr*/ + +} /* end of pin tl_i[77] */ + +pin("tl_i[76]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002121 ; + + /* Other user defined attributes. */ + original_pin : tl_i[76]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.188263, 5.142108, 5.111891, 5.100534, 5.114141",\ + "5.280335, 5.234180, 5.203964, 5.192606, 5.206214",\ + "5.390166, 5.344011, 5.313795, 5.302437, 5.316045",\ + "5.594857, 5.548702, 5.518486, 5.507128, 5.520736",\ + "5.971145, 5.924990, 5.894773, 5.883416, 5.897023"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.181033, 5.134878, 5.104661, 5.093304, 5.106912",\ + "5.279116, 5.232961, 5.202744, 5.191387, 5.204994",\ + "5.410749, 5.364594, 5.334378, 5.323020, 5.336628",\ + "5.655250, 5.609095, 5.578878, 5.567521, 5.581128",\ + "6.082715, 6.036560, 6.006343, 5.994986, 6.008594"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[76]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.873539, -0.831162, -0.796583, -0.758947, -0.475091",\ + "-0.958672, -0.916295, -0.881715, -0.844080, -0.560223",\ + "-1.055412, -1.013035, -0.978456, -0.940820, -0.656964",\ + "-1.223937, -1.181559, -1.146980, -1.109345, -0.825488",\ + "-1.471815, -1.429437, -1.394858, -1.357222, -1.073366"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.905092, -0.862715, -0.828135, -0.790500, -0.506643",\ + "-0.994562, -0.952185, -0.917606, -0.879970, -0.596114",\ + "-1.089293, -1.046916, -1.012336, -0.974701, -0.690844",\ + "-1.251651, -1.209274, -1.174694, -1.137059, -0.853202",\ + "-1.524578, -1.482201, -1.447622, -1.409986, -1.126130"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[76]_hldr*/ + +} /* end of pin tl_i[76] */ + +pin("tl_i[75]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002542 ; + + /* Other user defined attributes. */ + original_pin : tl_i[75]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.559262, 5.513107, 5.482891, 5.471533, 5.485141",\ + "5.649136, 5.602981, 5.572764, 5.561407, 5.575014",\ + "5.741644, 5.695489, 5.665273, 5.653915, 5.667523",\ + "5.907515, 5.861360, 5.831143, 5.819786, 5.833393",\ + "6.276364, 6.230209, 6.199993, 6.188635, 6.202243"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.570172, 5.524017, 5.493801, 5.482443, 5.496051",\ + "5.660883, 5.614728, 5.584512, 5.573154, 5.586762",\ + "5.779753, 5.733598, 5.703381, 5.692024, 5.705631",\ + "6.011688, 5.965533, 5.935317, 5.923959, 5.937567",\ + "6.423101, 6.376946, 6.346730, 6.335372, 6.348980"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[75]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.889999, -0.847622, -0.813043, -0.775407, -0.491551",\ + "-0.980238, -0.937861, -0.903281, -0.865646, -0.581789",\ + "-1.093020, -1.050642, -1.016063, -0.978428, -0.694571",\ + "-1.275653, -1.233275, -1.198696, -1.161060, -0.877204",\ + "-1.544115, -1.501738, -1.467158, -1.429523, -1.145666"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.923539, -0.881162, -0.846582, -0.808947, -0.525090",\ + "-1.013448, -0.971071, -0.936491, -0.898856, -0.614999",\ + "-1.108924, -1.066547, -1.031967, -0.994332, -0.710475",\ + "-1.279292, -1.236915, -1.202336, -1.164700, -0.880844",\ + "-1.578850, -1.536472, -1.501893, -1.464258, -1.180401"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[75]_hldr*/ + +} /* end of pin tl_i[75] */ + +pin("tl_i[74]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002632 ; + + /* Other user defined attributes. */ + original_pin : tl_i[74]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.253567, 5.207412, 5.177195, 5.165838, 5.179445",\ + "5.349404, 5.303249, 5.273033, 5.261675, 5.275283",\ + "5.476182, 5.430027, 5.399810, 5.388453, 5.402061",\ + "5.733068, 5.686913, 5.656696, 5.645339, 5.658946",\ + "6.219316, 6.173161, 6.142944, 6.131587, 6.145194"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.241081, 5.194926, 5.164710, 5.153352, 5.166960",\ + "5.334809, 5.288654, 5.258438, 5.247080, 5.260688",\ + "5.471406, 5.425251, 5.395034, 5.383677, 5.397285",\ + "5.764438, 5.718283, 5.688066, 5.676709, 5.690317",\ + "6.325636, 6.279481, 6.249264, 6.237907, 6.251514"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[74]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.935219, -0.892842, -0.858263, -0.820627, -0.536771",\ + "-1.028860, -0.986483, -0.951903, -0.914268, -0.630411",\ + "-1.143547, -1.101169, -1.066590, -1.028955, -0.745098",\ + "-1.326218, -1.283841, -1.249262, -1.211626, -0.927770",\ + "-1.614166, -1.571789, -1.537210, -1.499574, -1.215718"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.970892, -0.928514, -0.893935, -0.856300, -0.572443",\ + "-1.061820, -1.019442, -0.984863, -0.947227, -0.663371",\ + "-1.163435, -1.121057, -1.086478, -1.048843, -0.764986",\ + "-1.346292, -1.303915, -1.269336, -1.231700, -0.947844",\ + "-1.660875, -1.618498, -1.583918, -1.546283, -1.262426"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[74]_hldr*/ + +} /* end of pin tl_i[74] */ + +pin("tl_i[73]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002107 ; + + /* Other user defined attributes. */ + original_pin : tl_i[73]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.554523, 5.508368, 5.478152, 5.466794, 5.480402",\ + "5.649414, 5.603259, 5.573042, 5.561685, 5.575293",\ + "5.748847, 5.702692, 5.672475, 5.661118, 5.674726",\ + "5.924383, 5.878228, 5.848011, 5.836654, 5.850262",\ + "6.224755, 6.178600, 6.148384, 6.137026, 6.150634"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.589440, 5.543285, 5.513069, 5.501711, 5.515319",\ + "5.687266, 5.641111, 5.610895, 5.599537, 5.613145",\ + "5.793367, 5.747212, 5.716996, 5.705638, 5.719246",\ + "5.973481, 5.927326, 5.897110, 5.885752, 5.899360",\ + "6.270272, 6.224117, 6.193900, 6.182543, 6.196150"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[73]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.898724, -0.856347, -0.821768, -0.784132, -0.500276",\ + "-0.983802, -0.941425, -0.906845, -0.869210, -0.585353",\ + "-1.080504, -1.038127, -1.003548, -0.965912, -0.682056",\ + "-1.249018, -1.206641, -1.172062, -1.134426, -0.850570",\ + "-1.495438, -1.453061, -1.418482, -1.380846, -1.096990"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.930240, -0.887863, -0.853283, -0.815648, -0.531791",\ + "-1.018219, -0.975842, -0.941263, -0.903627, -0.619771",\ + "-1.114454, -1.072076, -1.037497, -0.999861, -0.716005",\ + "-1.276772, -1.234395, -1.199815, -1.162180, -0.878323",\ + "-1.549656, -1.507279, -1.472699, -1.435064, -1.151207"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[73]_hldr*/ + +} /* end of pin tl_i[73] */ + +pin("tl_i[72]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001514 ; + + /* Other user defined attributes. */ + original_pin : tl_i[72]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.995496, 4.949341, 4.919124, 4.907767, 4.921374",\ + "5.088820, 5.042665, 5.012448, 5.001091, 5.014698",\ + "5.200553, 5.154398, 5.124181, 5.112824, 5.126431",\ + "5.410159, 5.364004, 5.333787, 5.322430, 5.336038",\ + "5.770847, 5.724692, 5.694476, 5.683118, 5.696726"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.983222, 4.937068, 4.906851, 4.895494, 4.909101",\ + "5.083534, 5.037379, 5.007162, 4.995805, 5.009412",\ + "5.216234, 5.170079, 5.139863, 5.128505, 5.142113",\ + "5.462753, 5.416598, 5.386382, 5.375024, 5.388632",\ + "5.894033, 5.847878, 5.817662, 5.806304, 5.819912"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[72]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.828673, -0.786296, -0.751717, -0.714081, -0.430225",\ + "-0.916407, -0.874030, -0.839450, -0.801815, -0.517958",\ + "-1.009412, -0.967034, -0.932455, -0.894819, -0.610963",\ + "-1.161535, -1.119158, -1.084578, -1.046943, -0.763086",\ + "-1.413529, -1.371152, -1.336573, -1.298937, -1.015081"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.840436, -0.798058, -0.763479, -0.725843, -0.441987",\ + "-0.930307, -0.887930, -0.853350, -0.815715, -0.531858",\ + "-1.024595, -0.982218, -0.947639, -0.910003, -0.626147",\ + "-1.178880, -1.136502, -1.101923, -1.064288, -0.780431",\ + "-1.440355, -1.397978, -1.363399, -1.325763, -1.041907"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[72]_hldr*/ + +} /* end of pin tl_i[72] */ + +pin("tl_i[71]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002444 ; + + /* Other user defined attributes. */ + original_pin : tl_i[71]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.540210, 5.494055, 5.463838, 5.452481, 5.466088",\ + "5.637518, 5.591363, 5.561146, 5.549789, 5.563396",\ + "5.743839, 5.697684, 5.667468, 5.656110, 5.669718",\ + "5.935360, 5.889205, 5.858988, 5.847631, 5.861238",\ + "6.275519, 6.229364, 6.199148, 6.187790, 6.201398"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.544911, 5.498756, 5.468540, 5.457182, 5.470790",\ + "5.643330, 5.597175, 5.566958, 5.555601, 5.569208",\ + "5.758502, 5.712348, 5.682131, 5.670774, 5.684381",\ + "5.954805, 5.908650, 5.878434, 5.867076, 5.880684",\ + "6.290164, 6.244009, 6.213792, 6.202435, 6.216042"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[71]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.882892, -0.840514, -0.805935, -0.768299, -0.484443",\ + "-0.976532, -0.934155, -0.899575, -0.861940, -0.578083",\ + "-1.091232, -1.048855, -1.014276, -0.976640, -0.692784",\ + "-1.273476, -1.231099, -1.196519, -1.158884, -0.875027",\ + "-1.558704, -1.516327, -1.481747, -1.444112, -1.160255"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.918558, -0.876180, -0.841601, -0.803965, -0.520109",\ + "-1.009478, -0.967101, -0.932522, -0.894886, -0.611030",\ + "-1.111122, -1.068745, -1.034165, -0.996530, -0.712673",\ + "-1.293967, -1.251589, -1.217010, -1.179375, -0.895518",\ + "-1.608551, -1.566173, -1.531594, -1.493959, -1.210102"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[71]_hldr*/ + +} /* end of pin tl_i[71] */ + +pin("tl_i[70]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002521 ; + + /* Other user defined attributes. */ + original_pin : tl_i[70]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.558736, 5.512581, 5.482364, 5.471007, 5.484614",\ + "5.646551, 5.600396, 5.570179, 5.558822, 5.572429",\ + "5.751346, 5.705191, 5.674974, 5.663617, 5.677224",\ + "5.931952, 5.885797, 5.855580, 5.844223, 5.857830",\ + "6.227381, 6.181226, 6.151009, 6.139652, 6.153259"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.559927, 5.513772, 5.483556, 5.472198, 5.485806",\ + "5.643667, 5.597512, 5.567295, 5.555938, 5.569545",\ + "5.760825, 5.714670, 5.684453, 5.673096, 5.686704",\ + "5.980465, 5.934310, 5.904093, 5.892736, 5.906343",\ + "6.363138, 6.316983, 6.286767, 6.275409, 6.289017"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[70]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.108714, -1.066337, -1.031757, -0.994122, -0.710265",\ + "-1.197711, -1.155334, -1.120755, -1.083119, -0.799263",\ + "-1.273206, -1.230828, -1.196249, -1.158614, -0.874757",\ + "-1.400542, -1.358165, -1.323586, -1.285950, -1.002094",\ + "-1.588133, -1.545756, -1.511176, -1.473541, -1.189684"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.109905, -1.067528, -1.032949, -0.995313, -0.711457",\ + "-1.194827, -1.152450, -1.117871, -1.080235, -0.796379",\ + "-1.282685, -1.240308, -1.205728, -1.168093, -0.884236",\ + "-1.434258, -1.391881, -1.357301, -1.319666, -1.035809",\ + "-1.689183, -1.646805, -1.612226, -1.574591, -1.290734"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[70]_hldr*/ + +} /* end of pin tl_i[70] */ + +pin("tl_i[69]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003551 ; + + /* Other user defined attributes. */ + original_pin : tl_i[69]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.599169, 5.553014, 5.522797, 5.511440, 5.525047",\ + "5.692371, 5.646216, 5.615999, 5.604642, 5.618249",\ + "5.803999, 5.757844, 5.727628, 5.716270, 5.729878",\ + "6.013692, 5.967537, 5.937320, 5.925963, 5.939570",\ + "6.374660, 6.328505, 6.298288, 6.286931, 6.300539"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.586902, 5.540747, 5.510530, 5.499173, 5.512780",\ + "5.687091, 5.640936, 5.610719, 5.599362, 5.612969",\ + "5.819899, 5.773744, 5.743527, 5.732170, 5.745778",\ + "6.066907, 6.020752, 5.990536, 5.979178, 5.992786",\ + "6.499193, 6.453038, 6.422822, 6.411464, 6.425072"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[69]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.320298, -0.254656, -0.197381, -0.155524, 0.065753",\ + "-0.418767, -0.353125, -0.295851, -0.253993, -0.032716",\ + "-0.541359, -0.475718, -0.418443, -0.376585, -0.155308",\ + "-0.758841, -0.693200, -0.635925, -0.594067, -0.372790",\ + "-1.125992, -1.060351, -1.003076, -0.961219, -0.690840"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.551837, -0.504668, -0.447037, -0.405084, -0.122660",\ + "-0.642640, -0.595471, -0.537840, -0.495887, -0.213464",\ + "-0.748319, -0.701138, -0.643507, -0.601553, -0.319143",\ + "-0.935804, -0.888444, -0.830813, -0.788860, -0.506627",\ + "-1.256943, -1.209575, -1.151944, -1.109991, -0.827767"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[69]_hldr*/ + +} /* end of pin tl_i[69] */ + +pin("tl_i[68]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003064 ; + + /* Other user defined attributes. */ + original_pin : tl_i[68]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.192542, 5.146387, 5.116170, 5.104813, 5.118420",\ + "5.290967, 5.244812, 5.214595, 5.203238, 5.216846",\ + "5.401109, 5.354954, 5.324737, 5.313380, 5.326987",\ + "5.601238, 5.555083, 5.524867, 5.513509, 5.527117",\ + "5.960707, 5.914552, 5.884336, 5.872978, 5.886586"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.225666, 5.179511, 5.149294, 5.137937, 5.151545",\ + "5.325410, 5.279255, 5.249039, 5.237681, 5.251289",\ + "5.445796, 5.399642, 5.369425, 5.358068, 5.371675",\ + "5.657081, 5.610926, 5.580709, 5.569352, 5.582960",\ + "6.029737, 5.983582, 5.953365, 5.942008, 5.955616"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[68]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.383405, -0.317283, -0.259327, -0.217286, 0.002808",\ + "-0.476585, -0.410463, -0.352507, -0.310465, -0.090372",\ + "-0.609199, -0.543558, -0.486283, -0.444425, -0.212329",\ + "-0.768597, -0.702956, -0.645681, -0.603824, -0.382547",\ + "-1.029441, -0.963800, -0.906525, -0.864667, -0.643390"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.807548, -0.765101, -0.730685, -0.689878, -0.366659",\ + "-0.886339, -0.843892, -0.809476, -0.768669, -0.445450",\ + "-0.998027, -0.955579, -0.921164, -0.880357, -0.557138",\ + "-1.202545, -1.160097, -1.125682, -1.084875, -0.761656",\ + "-1.556186, -1.513738, -1.479323, -1.438516, -1.115297"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[68]_hldr*/ + +} /* end of pin tl_i[68] */ + +pin("tl_i[67]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004926 ; + + /* Other user defined attributes. */ + original_pin : tl_i[67]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.584554, 5.538399, 5.508182, 5.496825, 5.510432",\ + "5.677766, 5.631611, 5.601395, 5.590037, 5.603645",\ + "5.772066, 5.725911, 5.695694, 5.684337, 5.697944",\ + "5.938811, 5.892656, 5.862439, 5.851082, 5.864689",\ + "6.232008, 6.185853, 6.155637, 6.144279, 6.157887"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.609763, 5.563608, 5.533391, 5.522034, 5.535642",\ + "5.706739, 5.660584, 5.630367, 5.619010, 5.632617",\ + "5.807685, 5.761530, 5.731313, 5.719956, 5.733563",\ + "5.987043, 5.940888, 5.910672, 5.899314, 5.912922",\ + "6.348396, 6.302241, 6.272024, 6.260667, 6.274274"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[67]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.485126, -0.438062, -0.380431, -0.338477, -0.011156",\ + "-0.583825, -0.522452, -0.464496, -0.422454, -0.110899",\ + "-0.666073, -0.599951, -0.541995, -0.499953, -0.221634",\ + "-0.802234, -0.736112, -0.678156, -0.636114, -0.414195",\ + "-1.028199, -0.962077, -0.904121, -0.862080, -0.641986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.387383, -0.321742, -0.264467, -0.222610, -0.001333",\ + "-0.478290, -0.412648, -0.355373, -0.313516, -0.092239",\ + "-0.583616, -0.517975, -0.460700, -0.418842, -0.197565",\ + "-0.772257, -0.706615, -0.649340, -0.607483, -0.386206",\ + "-1.096755, -1.031114, -0.973839, -0.931981, -0.710704"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[67]_hldr*/ + +} /* end of pin tl_i[67] */ + +pin("tl_i[66]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005701 ; + + /* Other user defined attributes. */ + original_pin : tl_i[66]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.639438, 5.593283, 5.563066, 5.551709, 5.565317",\ + "5.733038, 5.686883, 5.656666, 5.645309, 5.658916",\ + "5.848727, 5.802572, 5.772356, 5.760998, 5.774606",\ + "6.068509, 6.022354, 5.992137, 5.980780, 5.994387",\ + "6.462988, 6.416833, 6.386617, 6.375259, 6.388867"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.621106, 5.574951, 5.544734, 5.533377, 5.546984",\ + "5.717392, 5.671237, 5.641021, 5.629663, 5.643271",\ + "5.853546, 5.807391, 5.777174, 5.765817, 5.779424",\ + "6.124442, 6.078287, 6.048070, 6.036713, 6.050320",\ + "6.621989, 6.575834, 6.545618, 6.534260, 6.547868"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[66]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.421962, -0.356320, -0.299045, -0.257188, -0.035911",\ + "-0.516417, -0.450775, -0.393500, -0.351643, -0.130366",\ + "-0.609921, -0.544280, -0.487005, -0.445147, -0.223870",\ + "-0.772065, -0.706424, -0.649149, -0.607291, -0.386014",\ + "-0.961881, -0.895759, -0.837803, -0.795761, -0.575668"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.486628, -0.441846, -0.402838, -0.353988, 0.043935",\ + "-0.578095, -0.533313, -0.494305, -0.445455, -0.047532",\ + "-0.684334, -0.639552, -0.600544, -0.551694, -0.153771",\ + "-0.874257, -0.829475, -0.790467, -0.741616, -0.343693",\ + "-1.203886, -1.159104, -1.120096, -1.071246, -0.673323"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[66]_hldr*/ + +} /* end of pin tl_i[66] */ + +pin("tl_i[65]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005716 ; + + /* Other user defined attributes. */ + original_pin : tl_i[65]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.459126, 5.412971, 5.382754, 5.371397, 5.385004",\ + "5.554200, 5.508045, 5.477829, 5.466471, 5.480079",\ + "5.677998, 5.631843, 5.601626, 5.590269, 5.603877",\ + "5.927989, 5.881835, 5.851618, 5.840261, 5.853868",\ + "6.397048, 6.350893, 6.320677, 6.309319, 6.322927"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.446668, 5.400513, 5.370296, 5.358939, 5.372547",\ + "5.539561, 5.493406, 5.463189, 5.451832, 5.465439",\ + "5.673235, 5.627080, 5.596863, 5.585506, 5.599113",\ + "5.960149, 5.913994, 5.883777, 5.872420, 5.886027",\ + "6.505686, 6.459531, 6.429315, 6.417957, 6.431565"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[65]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.425878, -0.360237, -0.302962, -0.261104, -0.039827",\ + "-0.522669, -0.457028, -0.399753, -0.357895, -0.136618",\ + "-0.621719, -0.556077, -0.498802, -0.456945, -0.235668",\ + "-0.791700, -0.725578, -0.667622, -0.625580, -0.405487",\ + "-0.986124, -0.920002, -0.862046, -0.820004, -0.599911"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.460052, -0.415270, -0.376262, -0.327412, 0.070511",\ + "-0.556623, -0.511841, -0.472833, -0.423982, -0.026060",\ + "-0.658589, -0.613808, -0.574799, -0.525949, -0.128026",\ + "-0.841385, -0.796603, -0.757595, -0.708745, -0.310822",\ + "-1.144313, -1.099531, -1.060523, -1.011673, -0.613750"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[65]_hldr*/ + +} /* end of pin tl_i[65] */ + +pin("tl_i[64]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004569 ; + + /* Other user defined attributes. */ + original_pin : tl_i[64]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.444655, 5.398500, 5.368283, 5.356926, 5.370533",\ + "5.543582, 5.497427, 5.467211, 5.455853, 5.469461",\ + "5.653337, 5.607182, 5.576965, 5.565608, 5.579216",\ + "5.851637, 5.805482, 5.775266, 5.763908, 5.777516",\ + "6.204331, 6.158176, 6.127959, 6.116602, 6.130209"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.478401, 5.432246, 5.402030, 5.390672, 5.404280",\ + "5.578437, 5.532282, 5.502066, 5.490708, 5.504316",\ + "5.698844, 5.652689, 5.622473, 5.611115, 5.624723",\ + "5.908003, 5.861848, 5.831632, 5.820274, 5.833882",\ + "6.273140, 6.226985, 6.196769, 6.185411, 6.199019"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[64]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.425314, -0.367605, -0.313198, -0.274713, -0.048281",\ + "-0.523194, -0.465485, -0.411079, -0.372594, -0.146162",\ + "-0.645804, -0.588095, -0.533688, -0.495204, -0.268772",\ + "-0.855838, -0.798129, -0.743723, -0.705238, -0.478806",\ + "-1.193156, -1.127033, -1.069077, -1.027036, -0.806943"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.376914, -0.311272, -0.253997, -0.212140, 0.059682",\ + "-0.475849, -0.410207, -0.352932, -0.311075, -0.039253",\ + "-0.593819, -0.528177, -0.470902, -0.429045, -0.157173",\ + "-0.797684, -0.732042, -0.674767, -0.632910, -0.360732",\ + "-1.142024, -1.076383, -1.019108, -0.977250, -0.703048"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[64]_hldr*/ + +} /* end of pin tl_i[64] */ + +pin("tl_i[63]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005918 ; + + /* Other user defined attributes. */ + original_pin : tl_i[63]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.634018, 5.587863, 5.557646, 5.546289, 5.559896",\ + "5.727260, 5.681105, 5.650888, 5.639531, 5.653139",\ + "5.821638, 5.775483, 5.745266, 5.733909, 5.747517",\ + "5.988543, 5.942388, 5.912171, 5.900814, 5.914422",\ + "6.282049, 6.235894, 6.205677, 6.194320, 6.207927"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.659294, 5.613139, 5.582922, 5.571565, 5.585172",\ + "5.756288, 5.710133, 5.679916, 5.668559, 5.682167",\ + "5.857348, 5.811193, 5.780976, 5.769619, 5.783226",\ + "6.036880, 5.990726, 5.960509, 5.949152, 5.962759",\ + "6.341727, 6.295572, 6.265355, 6.253998, 6.267605"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[63]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.425078, -0.367369, -0.312962, -0.274477, -0.048046",\ + "-0.523533, -0.465824, -0.411418, -0.372933, -0.146501",\ + "-0.649060, -0.591351, -0.536945, -0.498460, -0.272028",\ + "-0.863705, -0.805996, -0.751590, -0.713105, -0.486673",\ + "-1.108760, -1.042638, -0.984682, -0.942640, -0.722547"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.375262, -0.309621, -0.252346, -0.210488, 0.061380",\ + "-0.475435, -0.409794, -0.352519, -0.310661, -0.038785",\ + "-0.593964, -0.528323, -0.471048, -0.429190, -0.157265",\ + "-0.799253, -0.733611, -0.676336, -0.634479, -0.362291",\ + "-1.146486, -1.080845, -1.023570, -0.981712, -0.707386"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[63]_hldr*/ + +} /* end of pin tl_i[63] */ + +pin("tl_i[62]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005914 ; + + /* Other user defined attributes. */ + original_pin : tl_i[62]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.028421, 4.982266, 4.952050, 4.940692, 4.954300",\ + "5.115734, 5.069579, 5.039362, 5.028005, 5.041612",\ + "5.221791, 5.175636, 5.145419, 5.134062, 5.147669",\ + "5.411152, 5.364997, 5.334780, 5.323423, 5.337030",\ + "5.716925, 5.670770, 5.640553, 5.629196, 5.642803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.030477, 4.984322, 4.954105, 4.942748, 4.956356",\ + "5.112976, 5.066821, 5.036604, 5.025247, 5.038854",\ + "5.241773, 5.195618, 5.165401, 5.154044, 5.167651",\ + "5.477729, 5.431574, 5.401357, 5.390000, 5.403607",\ + "5.884023, 5.837868, 5.807651, 5.796294, 5.809901"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[62]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.310949, -0.245308, -0.188033, -0.146175, 0.125715",\ + "-0.408722, -0.343080, -0.285805, -0.243948, 0.028056",\ + "-0.525662, -0.460020, -0.402745, -0.360888, -0.087938",\ + "-0.729867, -0.664225, -0.606950, -0.565093, -0.287448",\ + "-1.073045, -1.007404, -0.950129, -0.908272, -0.621407"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.560733, -0.518534, -0.464760, -0.422807, -0.191354",\ + "-0.659844, -0.617645, -0.563872, -0.521919, -0.290465",\ + "-0.778888, -0.736689, -0.682928, -0.640975, -0.409521",\ + "-0.986411, -0.944213, -0.890754, -0.848801, -0.617348",\ + "-1.324035, -1.281784, -1.238624, -1.196671, -0.966234"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[62]_hldr*/ + +} /* end of pin tl_i[62] */ + +pin("tl_i[61]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004650 ; + + /* Other user defined attributes. */ + original_pin : tl_i[61]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.050911, 5.004756, 4.974539, 4.963182, 4.976789",\ + "5.138693, 5.092538, 5.062321, 5.050964, 5.064571",\ + "5.242861, 5.196706, 5.166489, 5.155132, 5.168739",\ + "5.438320, 5.392165, 5.361948, 5.350591, 5.364199",\ + "5.753279, 5.707124, 5.676907, 5.665550, 5.679157"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.054683, 5.008528, 4.978311, 4.966954, 4.980561",\ + "5.137789, 5.091634, 5.061417, 5.050060, 5.063667",\ + "5.257940, 5.211785, 5.181569, 5.170211, 5.183819",\ + "5.493972, 5.447817, 5.417600, 5.406243, 5.419850",\ + "5.883592, 5.837437, 5.807220, 5.795863, 5.809470"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[61]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.331346, -0.288929, -0.254443, -0.214995, 0.091355",\ + "-0.415000, -0.372583, -0.338097, -0.298649, 0.007701",\ + "-0.498520, -0.456102, -0.421616, -0.382169, -0.075818",\ + "-0.644671, -0.602253, -0.567767, -0.528320, -0.221969",\ + "-0.885228, -0.842810, -0.808325, -0.768877, -0.462526"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.495414, -0.429474, -0.371779, -0.329808, -0.077326",\ + "-0.577402, -0.511461, -0.453767, -0.411796, -0.165065",\ + "-0.669896, -0.603956, -0.546261, -0.504290, -0.256735",\ + "-0.831937, -0.776516, -0.718821, -0.676851, -0.409235",\ + "-1.083366, -1.040949, -1.006463, -0.967015, -0.660665"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[61]_hldr*/ + +} /* end of pin tl_i[61] */ + +pin("tl_i[60]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004493 ; + + /* Other user defined attributes. */ + original_pin : tl_i[60]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.075901, 5.029746, 4.999529, 4.988172, 5.001780",\ + "5.162810, 5.116655, 5.086439, 5.075081, 5.088689",\ + "5.262701, 5.216546, 5.186329, 5.174972, 5.188580",\ + "5.463603, 5.417448, 5.387231, 5.375874, 5.389482",\ + "5.887491, 5.841336, 5.811120, 5.799762, 5.813370"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.069137, 5.022982, 4.992765, 4.981408, 4.995015",\ + "5.162019, 5.115864, 5.085647, 5.074290, 5.087897",\ + "5.289857, 5.243702, 5.213485, 5.202128, 5.215735",\ + "5.547719, 5.501564, 5.471347, 5.459990, 5.473598",\ + "5.999206, 5.953051, 5.922834, 5.911477, 5.925084"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[60]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.331961, -0.289544, -0.255058, -0.215610, 0.090740",\ + "-0.416689, -0.374271, -0.339785, -0.300337, 0.006013",\ + "-0.501750, -0.459332, -0.424846, -0.385399, -0.079048",\ + "-0.650840, -0.608422, -0.573936, -0.534488, -0.228138",\ + "-0.898578, -0.856161, -0.821675, -0.782227, -0.475877"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.494855, -0.428915, -0.371220, -0.329249, -0.108704",\ + "-0.577203, -0.511263, -0.453568, -0.411597, -0.191052",\ + "-0.675131, -0.609191, -0.551496, -0.509525, -0.288980",\ + "-0.848911, -0.782971, -0.725276, -0.683305, -0.462760",\ + "-1.143176, -1.077236, -1.019541, -0.977570, -0.757025"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[60]_hldr*/ + +} /* end of pin tl_i[60] */ + +pin("tl_i[59]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004673 ; + + /* Other user defined attributes. */ + original_pin : tl_i[59]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.018675, 4.972520, 4.942304, 4.930946, 4.944554",\ + "5.111604, 5.065449, 5.035232, 5.023875, 5.037482",\ + "5.204963, 5.158808, 5.128592, 5.117234, 5.130842",\ + "5.368355, 5.322200, 5.291983, 5.280626, 5.294233",\ + "5.654718, 5.608563, 5.578346, 5.566989, 5.580596"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.048488, 5.002333, 4.972116, 4.960759, 4.974366",\ + "5.145526, 5.099371, 5.069155, 5.057797, 5.071405",\ + "5.246175, 5.200020, 5.169804, 5.158446, 5.172054",\ + "5.423032, 5.376877, 5.346661, 5.335303, 5.348911",\ + "5.720785, 5.674630, 5.644413, 5.633056, 5.646663"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[59]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.399850, -0.333910, -0.276215, -0.234244, -0.013699",\ + "-0.490388, -0.424448, -0.366753, -0.324782, -0.104237",\ + "-0.591764, -0.525824, -0.468129, -0.426158, -0.205613",\ + "-0.771660, -0.705720, -0.648025, -0.606054, -0.385509",\ + "-1.061324, -0.995383, -0.937689, -0.895718, -0.675172"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.408211, -0.365794, -0.331308, -0.291860, 0.014490",\ + "-0.495065, -0.452648, -0.418162, -0.378714, -0.072363",\ + "-0.606791, -0.564374, -0.529888, -0.490440, -0.184090",\ + "-0.793280, -0.750863, -0.716377, -0.676929, -0.370579",\ + "-1.099378, -1.056960, -1.022474, -0.983027, -0.676676"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[59]_hldr*/ + +} /* end of pin tl_i[59] */ + +pin("tl_i[58]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005086 ; + + /* Other user defined attributes. */ + original_pin : tl_i[58]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.907104, 4.860949, 4.830732, 4.819375, 4.832983",\ + "4.992526, 4.946371, 4.916154, 4.904797, 4.918404",\ + "5.070096, 5.023941, 4.993724, 4.982367, 4.995975",\ + "5.244753, 5.198598, 5.168381, 5.157024, 5.170631",\ + "5.599957, 5.553802, 5.523586, 5.512228, 5.525836"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.904143, 4.857988, 4.827772, 4.816414, 4.830022",\ + "4.986795, 4.940640, 4.910424, 4.899066, 4.912674",\ + "5.098862, 5.052707, 5.022491, 5.011133, 5.024741",\ + "5.327568, 5.281413, 5.251196, 5.239839, 5.253446",\ + "5.728967, 5.682812, 5.652596, 5.641238, 5.654846"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[58]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.409769, -0.343829, -0.286134, -0.244163, -0.023618",\ + "-0.498234, -0.432294, -0.374599, -0.332628, -0.112083",\ + "-0.599794, -0.533854, -0.476159, -0.434188, -0.213643",\ + "-0.781831, -0.715891, -0.658196, -0.616225, -0.395680",\ + "-1.087101, -1.021161, -0.963466, -0.921496, -0.700950"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.423427, -0.381010, -0.346524, -0.307076, -0.000726",\ + "-0.507266, -0.464848, -0.430363, -0.390915, -0.084564",\ + "-0.628312, -0.585894, -0.551408, -0.511960, -0.205610",\ + "-0.825686, -0.783269, -0.748783, -0.709335, -0.402985",\ + "-1.126419, -1.084002, -1.049516, -1.010068, -0.703718"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[58]_hldr*/ + +} /* end of pin tl_i[58] */ + +pin("tl_i[57]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004084 ; + + /* Other user defined attributes. */ + original_pin : tl_i[57]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.853275, 4.807120, 4.776903, 4.765546, 4.779153",\ + "4.941780, 4.895625, 4.865408, 4.854051, 4.867658",\ + "5.043512, 4.997357, 4.967141, 4.955783, 4.969391",\ + "5.245644, 5.199489, 5.169272, 5.157915, 5.171523",\ + "5.684921, 5.638766, 5.608549, 5.597192, 5.610799"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.846420, 4.800265, 4.770049, 4.758691, 4.772299",\ + "4.940993, 4.894838, 4.864621, 4.853264, 4.866871",\ + "5.069371, 5.023216, 4.992999, 4.981642, 4.995249",\ + "5.318837, 5.272682, 5.242465, 5.231108, 5.244716",\ + "5.754844, 5.708689, 5.678472, 5.667115, 5.680722"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[57]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.439430, -0.373490, -0.315795, -0.273825, -0.053279",\ + "-0.519622, -0.453682, -0.395987, -0.354016, -0.133471",\ + "-0.597395, -0.531455, -0.473760, -0.431789, -0.211244",\ + "-0.729801, -0.663861, -0.606166, -0.564195, -0.343650",\ + "-0.935990, -0.870050, -0.812355, -0.770384, -0.549839"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.409353, -0.366935, -0.332449, -0.293002, 0.013349",\ + "-0.497213, -0.454795, -0.420310, -0.380862, -0.074511",\ + "-0.585629, -0.543211, -0.508725, -0.469278, -0.162927",\ + "-0.741802, -0.699385, -0.664899, -0.625451, -0.319101",\ + "-0.995469, -0.953051, -0.918565, -0.879117, -0.572767"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[57]_hldr*/ + +} /* end of pin tl_i[57] */ + +pin("tl_i[56]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005633 ; + + /* Other user defined attributes. */ + original_pin : tl_i[56]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.771066, 4.724911, 4.694694, 4.683337, 4.696944",\ + "4.860967, 4.814812, 4.784595, 4.773238, 4.786846",\ + "4.953480, 4.907325, 4.877108, 4.865751, 4.879358",\ + "5.122646, 5.076491, 5.046274, 5.034917, 5.048524",\ + "5.508491, 5.462336, 5.432119, 5.420762, 5.434369"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.784305, 4.738150, 4.707933, 4.696576, 4.710184",\ + "4.872721, 4.826566, 4.796349, 4.784992, 4.798599",\ + "4.991727, 4.945572, 4.915355, 4.903998, 4.917605",\ + "5.265233, 5.219078, 5.188861, 5.177504, 5.191111",\ + "5.790774, 5.744619, 5.714402, 5.703045, 5.716652"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[56]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.441652, -0.375711, -0.318017, -0.276046, -0.055500",\ + "-0.524614, -0.458674, -0.400979, -0.359008, -0.138463",\ + "-0.607820, -0.541879, -0.484185, -0.442214, -0.221668",\ + "-0.753165, -0.687225, -0.629530, -0.587559, -0.367014",\ + "-0.987968, -0.922028, -0.864333, -0.822362, -0.601816"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.411476, -0.369059, -0.334573, -0.295125, 0.011225",\ + "-0.499637, -0.457219, -0.422733, -0.383285, -0.076935",\ + "-0.588334, -0.545917, -0.511431, -0.471983, -0.165633",\ + "-0.746601, -0.704183, -0.669698, -0.630250, -0.323899",\ + "-1.003694, -0.961277, -0.926791, -0.887343, -0.580993"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[56]_hldr*/ + +} /* end of pin tl_i[56] */ + +pin("tl_i[55]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.023564 ; + + /* Other user defined attributes. */ + original_pin : tl_i[55]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.825782, 5.779627, 5.749410, 5.738052, 5.751660",\ + "5.912527, 5.866372, 5.836155, 5.824798, 5.838405",\ + "6.021775, 5.975620, 5.945403, 5.934046, 5.947653",\ + "6.207016, 6.160861, 6.130644, 6.119287, 6.132894",\ + "6.502526, 6.456371, 6.426154, 6.414796, 6.428404"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.826127, 5.779972, 5.749755, 5.738398, 5.752005",\ + "5.912270, 5.866115, 5.835897, 5.824540, 5.838148",\ + "6.043355, 5.997200, 5.966982, 5.955625, 5.969233",\ + "6.273898, 6.227743, 6.197526, 6.186169, 6.199776",\ + "6.665429, 6.619274, 6.589057, 6.577700, 6.591307"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[55]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\ + "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[55]_hldr*/ + +} /* end of pin tl_i[55] */ + +pin("tl_i[54]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.024771 ; + + /* Other user defined attributes. */ + original_pin : tl_i[54]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.671892, 5.625737, 5.595520, 5.584163, 5.597770",\ + "5.766703, 5.720548, 5.690331, 5.678973, 5.692581",\ + "5.865909, 5.819754, 5.789536, 5.778179, 5.791787",\ + "6.041008, 5.994853, 5.964636, 5.953279, 5.966886",\ + "6.340645, 6.294490, 6.264273, 6.252915, 6.266523"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.706592, 5.660437, 5.630219, 5.618862, 5.632470",\ + "5.804386, 5.758231, 5.728014, 5.716657, 5.730264",\ + "5.910204, 5.864049, 5.833832, 5.822474, 5.836082",\ + "6.089930, 6.043775, 6.013557, 6.002200, 6.015808",\ + "6.385911, 6.339756, 6.309539, 6.298182, 6.311790"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[54]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\ + "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[54]_hldr*/ + +} /* end of pin tl_i[54] */ + +pin("tl_i[53]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025984 ; + + /* Other user defined attributes. */ + original_pin : tl_i[53]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.405560, 5.359406, 5.329188, 5.317831, 5.331439",\ + "5.489668, 5.443513, 5.413296, 5.401938, 5.415546",\ + "5.570677, 5.524522, 5.494305, 5.482947, 5.496555",\ + "5.711991, 5.665836, 5.635619, 5.624262, 5.637869",\ + "5.953867, 5.907712, 5.877495, 5.866138, 5.879745"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.390637, 5.344482, 5.314265, 5.302907, 5.316515",\ + "5.472354, 5.426199, 5.395982, 5.384624, 5.398232",\ + "5.578566, 5.532411, 5.502193, 5.490836, 5.504444",\ + "5.766796, 5.720641, 5.690423, 5.679066, 5.692674",\ + "6.084168, 6.038013, 6.007796, 5.996439, 6.010046"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[53]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\ + "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[53]_hldr*/ + +} /* end of pin tl_i[53] */ + +pin("tl_i[52]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.023928 ; + + /* Other user defined attributes. */ + original_pin : tl_i[52]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.851366, 5.805211, 5.774994, 5.763637, 5.777244",\ + "5.940992, 5.894837, 5.864620, 5.853263, 5.866870",\ + "6.046589, 6.000434, 5.970217, 5.958859, 5.972467",\ + "6.242908, 6.196754, 6.166536, 6.155179, 6.168787",\ + "6.655770, 6.609615, 6.579398, 6.568040, 6.581648"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.844427, 5.798272, 5.768054, 5.756697, 5.770305",\ + "5.940210, 5.894055, 5.863838, 5.852481, 5.866088",\ + "6.071230, 6.025075, 5.994858, 5.983501, 5.997108",\ + "6.314948, 6.268793, 6.238575, 6.227218, 6.240826",\ + "6.731011, 6.684856, 6.654639, 6.643281, 6.656889"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[52]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.412428, -0.355362, -0.313364, -0.040427",\ + "-0.701632, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[52]_hldr*/ + +} /* end of pin tl_i[52] */ + +pin("tl_i[51]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.024747 ; + + /* Other user defined attributes. */ + original_pin : tl_i[51]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.766789, 5.720634, 5.690417, 5.679060, 5.692667",\ + "5.856632, 5.810477, 5.780260, 5.768903, 5.782510",\ + "5.949137, 5.902982, 5.872765, 5.861408, 5.875015",\ + "6.115034, 6.068879, 6.038662, 6.027305, 6.040912",\ + "6.488516, 6.442361, 6.412144, 6.400786, 6.414394"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.777621, 5.731466, 5.701249, 5.689892, 5.703499",\ + "5.868374, 5.822219, 5.792002, 5.780644, 5.794252",\ + "5.987092, 5.940937, 5.910720, 5.899363, 5.912970",\ + "6.219129, 6.172974, 6.142756, 6.131399, 6.145007",\ + "6.630526, 6.584371, 6.554153, 6.542796, 6.556404"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[51]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.408918, -0.350984, -0.308948, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[51]_hldr*/ + +} /* end of pin tl_i[51] */ + +pin("tl_i[50]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.024706 ; + + /* Other user defined attributes. */ + original_pin : tl_i[50]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.432938, 5.386783, 5.356565, 5.345208, 5.358816",\ + "5.522908, 5.476753, 5.446536, 5.435179, 5.448786",\ + "5.615422, 5.569267, 5.539050, 5.527693, 5.541300",\ + "5.781178, 5.735023, 5.704806, 5.693449, 5.707057",\ + "6.151173, 6.105018, 6.074801, 6.063444, 6.077051"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.443795, 5.397640, 5.367423, 5.356066, 5.369673",\ + "5.534675, 5.488520, 5.458302, 5.446945, 5.460553",\ + "5.653760, 5.607605, 5.577388, 5.566031, 5.579638",\ + "5.885449, 5.839294, 5.809077, 5.797719, 5.811327",\ + "6.297242, 6.251087, 6.220870, 6.209512, 6.223120"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[50]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454534, -0.408918, -0.350984, -0.308948, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[50]_hldr*/ + +} /* end of pin tl_i[50] */ + +pin("tl_i[49]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.014215 ; + + /* Other user defined attributes. */ + original_pin : tl_i[49]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.612003, 5.565848, 5.535631, 5.524274, 5.537881",\ + "5.697372, 5.651217, 5.621000, 5.609643, 5.623250",\ + "5.774767, 5.728612, 5.698395, 5.687037, 5.700645",\ + "5.943757, 5.897602, 5.867384, 5.856027, 5.869635",\ + "6.302785, 6.256630, 6.226413, 6.215055, 6.228663"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.608959, 5.562804, 5.532587, 5.521230, 5.534837",\ + "5.691543, 5.645388, 5.615170, 5.603813, 5.617421",\ + "5.803527, 5.757372, 5.727155, 5.715797, 5.729405",\ + "6.034389, 5.988234, 5.958016, 5.946659, 5.960267",\ + "6.439312, 6.393157, 6.362939, 6.351582, 6.365190"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[49]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.042324, -0.000326, 0.287989",\ + "-0.219595, -0.177177, -0.128664, -0.086666, 0.203312",\ + "-0.307616, -0.265198, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.412253, -0.355362, -0.313364, -0.040427",\ + "-0.692896, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[49]_hldr*/ + +} /* end of pin tl_i[49] */ + +pin("tl_i[48]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.015924 ; + + /* Other user defined attributes. */ + original_pin : tl_i[48]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.342521, 5.296366, 5.266149, 5.254791, 5.268399",\ + "5.430000, 5.383845, 5.353628, 5.342271, 5.355878",\ + "5.517300, 5.471145, 5.440928, 5.429570, 5.443178",\ + "5.691890, 5.645735, 5.615518, 5.604160, 5.617768",\ + "6.098689, 6.052534, 6.022317, 6.010960, 6.024567"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.337069, 5.290914, 5.260696, 5.249339, 5.262947",\ + "5.426027, 5.379872, 5.349655, 5.338298, 5.351905",\ + "5.541069, 5.494914, 5.464697, 5.453340, 5.466947",\ + "5.778956, 5.732801, 5.702584, 5.691227, 5.704834",\ + "6.214471, 6.168316, 6.138099, 6.126742, 6.140349"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[48]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.095389, -0.053327, -0.019395, 0.003631, 0.287989",\ + "-0.178535, -0.136472, -0.102541, -0.079514, 0.203312",\ + "-0.262969, -0.220876, -0.186811, -0.163726, 0.115291",\ + "-0.399970, -0.357878, -0.323812, -0.300727, -0.040427",\ + "-0.613644, -0.571552, -0.537486, -0.514401, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.127054, -0.062200, -0.008166, 0.033833, 0.254201",\ + "-0.207506, -0.142652, -0.088847, -0.050549, 0.160177",\ + "-0.300279, -0.235482, -0.181379, -0.142982, 0.068969",\ + "-0.445930, -0.381133, -0.327029, -0.288632, -0.088057",\ + "-0.677823, -0.613026, -0.558922, -0.520525, -0.325394"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[48]_hldr*/ + +} /* end of pin tl_i[48] */ + +pin("tl_i[47]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.015093 ; + + /* Other user defined attributes. */ + original_pin : tl_i[47]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.720613, 5.674458, 5.644240, 5.632883, 5.646491",\ + "5.808302, 5.762147, 5.731930, 5.720572, 5.734180",\ + "5.909732, 5.863577, 5.833360, 5.822003, 5.835610",\ + "6.090167, 6.044012, 6.013794, 6.002437, 6.016045",\ + "6.375024, 6.328869, 6.298652, 6.287294, 6.300902"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.723861, 5.677706, 5.647489, 5.636132, 5.649739",\ + "5.806833, 5.760678, 5.730461, 5.719103, 5.732711",\ + "5.923954, 5.877799, 5.847582, 5.836225, 5.849832",\ + "6.142916, 6.096761, 6.066544, 6.055186, 6.068794",\ + "6.505251, 6.459096, 6.428879, 6.417521, 6.431129"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[47]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.412253, -0.355362, -0.313364, -0.040427",\ + "-0.692896, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[47]_hldr*/ + +} /* end of pin tl_i[47] */ + +pin("tl_i[46]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.015694 ; + + /* Other user defined attributes. */ + original_pin : tl_i[46]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.747210, 5.701055, 5.670837, 5.659480, 5.673088",\ + "5.834549, 5.788394, 5.758177, 5.746819, 5.760427",\ + "5.931758, 5.885603, 5.855386, 5.844028, 5.857636",\ + "6.119594, 6.073439, 6.043221, 6.031864, 6.045472",\ + "6.512118, 6.465963, 6.435746, 6.424389, 6.437996"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.740419, 5.694264, 5.664047, 5.652689, 5.666297",\ + "5.833758, 5.787603, 5.757386, 5.746029, 5.759636",\ + "5.958529, 5.912374, 5.882157, 5.870800, 5.884408",\ + "6.201867, 6.155712, 6.125495, 6.114138, 6.127745",\ + "6.619649, 6.573494, 6.543277, 6.531919, 6.545527"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[46]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.412253, -0.355362, -0.313364, -0.040427",\ + "-0.692896, -0.635483, -0.577488, -0.535436, -0.297932"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.725398, -0.659249, -0.601254, -0.559203, -0.339176"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[46]_hldr*/ + +} /* end of pin tl_i[46] */ + +pin("tl_i[45]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.017466 ; + + /* Other user defined attributes. */ + original_pin : tl_i[45]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.112432, 5.066278, 5.036060, 5.024703, 5.038311",\ + "5.197829, 5.151674, 5.121457, 5.110100, 5.123707",\ + "5.275316, 5.229161, 5.198944, 5.187587, 5.201194",\ + "5.419477, 5.373322, 5.343104, 5.331747, 5.345355",\ + "5.777201, 5.731046, 5.700829, 5.689471, 5.703079"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.109432, 5.063277, 5.033060, 5.021703, 5.035310",\ + "5.192052, 5.145897, 5.115680, 5.104322, 5.117930",\ + "5.304079, 5.257924, 5.227707, 5.216350, 5.229957",\ + "5.534409, 5.488254, 5.458036, 5.446679, 5.460287",\ + "5.938303, 5.892148, 5.861931, 5.850574, 5.864181"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[45]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.134918, -0.092500, -0.042324, -0.000326, 0.287989",\ + "-0.219595, -0.177177, -0.128664, -0.086666, 0.203312",\ + "-0.307616, -0.265198, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.408918, -0.350984, -0.308948, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[45]_hldr*/ + +} /* end of pin tl_i[45] */ + +pin("tl_i[44]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.016255 ; + + /* Other user defined attributes. */ + original_pin : tl_i[44]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.787257, 5.741102, 5.710885, 5.699527, 5.713135",\ + "5.887364, 5.841209, 5.810992, 5.799634, 5.813242",\ + "6.003266, 5.957111, 5.926894, 5.915536, 5.929144",\ + "6.212816, 6.166661, 6.136444, 6.125086, 6.138694",\ + "6.574124, 6.527969, 6.497752, 6.486395, 6.500002"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.833889, 5.787734, 5.757517, 5.746160, 5.759767",\ + "5.932858, 5.886703, 5.856485, 5.845128, 5.858736",\ + "6.056724, 6.010569, 5.980351, 5.968994, 5.982602",\ + "6.267234, 6.221079, 6.190862, 6.179505, 6.193112",\ + "6.625524, 6.579369, 6.549152, 6.537795, 6.551402"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[44]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.084700, -0.042324, -0.000326, 0.287989",\ + "-0.211450, -0.169345, -0.128664, -0.086666, 0.203312",\ + "-0.299321, -0.257215, -0.213787, -0.171789, 0.115291",\ + "-0.454448, -0.408918, -0.350984, -0.308948, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131974, -0.065963, -0.008166, 0.033833, 0.254201",\ + "-0.225998, -0.159987, -0.102190, -0.060192, 0.160177",\ + "-0.317206, -0.251195, -0.193398, -0.151400, 0.068969",\ + "-0.474232, -0.408221, -0.350424, -0.308425, -0.088057",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.274662"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[44]_hldr*/ + +} /* end of pin tl_i[44] */ + +pin("tl_i[43]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.018203 ; + + /* Other user defined attributes. */ + original_pin : tl_i[43]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.371556, 5.325401, 5.295184, 5.283827, 5.297434",\ + "5.461463, 5.415308, 5.385091, 5.373734, 5.387341",\ + "5.553976, 5.507821, 5.477604, 5.466247, 5.479854",\ + "5.719817, 5.673662, 5.643445, 5.632088, 5.645695",\ + "6.097318, 6.051163, 6.020946, 6.009588, 6.023196"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.382551, 5.336396, 5.306179, 5.294822, 5.308429",\ + "5.473218, 5.427063, 5.396846, 5.385489, 5.399096",\ + "5.592251, 5.546096, 5.515879, 5.504522, 5.518129",\ + "5.824078, 5.777923, 5.747705, 5.736348, 5.749956",\ + "6.235509, 6.189354, 6.159137, 6.147780, 6.161387"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[43]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[43]_hldr*/ + +} /* end of pin tl_i[43] */ + +pin("tl_i[42]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.019122 ; + + /* Other user defined attributes. */ + original_pin : tl_i[42]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.198272, 5.152117, 5.121900, 5.110542, 5.124150",\ + "5.294228, 5.248073, 5.217855, 5.206498, 5.220106",\ + "5.404464, 5.358309, 5.328092, 5.316734, 5.330342",\ + "5.594985, 5.548830, 5.518613, 5.507256, 5.520863",\ + "5.917032, 5.870877, 5.840660, 5.829302, 5.842910"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.190427, 5.144272, 5.114055, 5.102697, 5.116305",\ + "5.291961, 5.245806, 5.215589, 5.204232, 5.217839",\ + "5.417454, 5.371299, 5.341082, 5.329724, 5.343332",\ + "5.634560, 5.588405, 5.558187, 5.546830, 5.560438",\ + "6.000741, 5.954587, 5.924369, 5.913012, 5.926620"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[42]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[42]_hldr*/ + +} /* end of pin tl_i[42] */ + +pin("tl_i[41]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.022202 ; + + /* Other user defined attributes. */ + original_pin : tl_i[41]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.148859, 5.102704, 5.072487, 5.061130, 5.074737",\ + "5.233216, 5.187061, 5.156844, 5.145487, 5.159094",\ + "5.314116, 5.267961, 5.237743, 5.226386, 5.239994",\ + "5.455597, 5.409442, 5.379225, 5.367867, 5.381475",\ + "5.695938, 5.649783, 5.619565, 5.608208, 5.621816"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.134229, 5.088074, 5.057857, 5.046499, 5.060107",\ + "5.215816, 5.169661, 5.139443, 5.128086, 5.141694",\ + "5.322016, 5.275861, 5.245644, 5.234286, 5.247894",\ + "5.510269, 5.464114, 5.433897, 5.422539, 5.436147",\ + "5.825513, 5.779358, 5.749141, 5.737783, 5.751391"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[41]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[41]_hldr*/ + +} /* end of pin tl_i[41] */ + +pin("tl_i[40]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.021765 ; + + /* Other user defined attributes. */ + original_pin : tl_i[40]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.554589, 5.508434, 5.478217, 5.466860, 5.480467",\ + "5.642064, 5.595909, 5.565692, 5.554335, 5.567942",\ + "5.729364, 5.683209, 5.652992, 5.641635, 5.655242",\ + "5.918046, 5.871891, 5.841674, 5.830317, 5.843924",\ + "6.322921, 6.276766, 6.246549, 6.235191, 6.248799"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.549117, 5.502962, 5.472744, 5.461387, 5.474995",\ + "5.638085, 5.591930, 5.561713, 5.550356, 5.563963",\ + "5.753121, 5.706966, 5.676749, 5.665391, 5.678999",\ + "5.991310, 5.945155, 5.914938, 5.903581, 5.917188",\ + "6.427492, 6.381337, 6.351120, 6.339763, 6.353370"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[40]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.716436, -0.659249, -0.601254, -0.559203, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[40]_hldr*/ + +} /* end of pin tl_i[40] */ + +pin("tl_i[39]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.017624 ; + + /* Other user defined attributes. */ + original_pin : tl_i[39]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.869242, 4.823087, 4.792870, 4.781513, 4.795120",\ + "4.959149, 4.912994, 4.882777, 4.871420, 4.885027",\ + "5.051662, 5.005507, 4.975290, 4.963933, 4.977540",\ + "5.217504, 5.171349, 5.141131, 5.129774, 5.143382",\ + "5.606756, 5.560601, 5.530384, 5.519027, 5.532634"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.880238, 4.834083, 4.803865, 4.792508, 4.806116",\ + "4.970903, 4.924748, 4.894531, 4.883174, 4.896781",\ + "5.089937, 5.043782, 5.013565, 5.002208, 5.015815",\ + "5.321764, 5.275609, 5.245392, 5.234035, 5.247642",\ + "5.733193, 5.687038, 5.656821, 5.645464, 5.659071"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[39]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[39]_hldr*/ + +} /* end of pin tl_i[39] */ + +pin("tl_i[38]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.020036 ; + + /* Other user defined attributes. */ + original_pin : tl_i[38]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.623479, 5.577324, 5.547107, 5.535749, 5.549357",\ + "5.708911, 5.662756, 5.632539, 5.621181, 5.634789",\ + "5.786510, 5.740355, 5.710137, 5.698780, 5.712388",\ + "5.952927, 5.906772, 5.876554, 5.865197, 5.878805",\ + "6.305354, 6.259199, 6.228982, 6.217625, 6.231232"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.620534, 5.574379, 5.544162, 5.532805, 5.546412",\ + "5.703200, 5.657045, 5.626828, 5.615471, 5.629078",\ + "5.815276, 5.769121, 5.738904, 5.727547, 5.741154",\ + "6.045676, 5.999521, 5.969304, 5.957947, 5.971554",\ + "6.448150, 6.401995, 6.371778, 6.360420, 6.374028"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[38]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[38]_hldr*/ + +} /* end of pin tl_i[38] */ + +pin("tl_i[37]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.020927 ; + + /* Other user defined attributes. */ + original_pin : tl_i[37]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.583619, 5.537464, 5.507247, 5.495890, 5.509497",\ + "5.673532, 5.627377, 5.597160, 5.585803, 5.599410",\ + "5.766046, 5.719891, 5.689674, 5.678317, 5.691924",\ + "5.938797, 5.892642, 5.862425, 5.851068, 5.864676",\ + "6.323754, 6.277599, 6.247382, 6.236025, 6.249632"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.594629, 5.548474, 5.518257, 5.506900, 5.520507",\ + "5.685287, 5.639132, 5.608915, 5.597558, 5.611166",\ + "5.804349, 5.758194, 5.727977, 5.716619, 5.730227",\ + "6.036157, 5.990002, 5.959785, 5.948428, 5.962035",\ + "6.447590, 6.401435, 6.371218, 6.359861, 6.373468"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[37]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[37]_hldr*/ + +} /* end of pin tl_i[37] */ + +pin("tl_i[36]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.022013 ; + + /* Other user defined attributes. */ + original_pin : tl_i[36]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.660564, 5.614409, 5.584192, 5.572835, 5.586442",\ + "5.744962, 5.698807, 5.668590, 5.657232, 5.670840",\ + "5.825815, 5.779660, 5.749443, 5.738086, 5.751693",\ + "5.968822, 5.922667, 5.892449, 5.881092, 5.894700",\ + "6.227637, 6.181482, 6.151265, 6.139908, 6.153515"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.645984, 5.599829, 5.569612, 5.558254, 5.571862",\ + "5.727538, 5.681383, 5.651165, 5.639808, 5.653416",\ + "5.833738, 5.787583, 5.757366, 5.746009, 5.759616",\ + "6.023547, 5.977392, 5.947175, 5.935818, 5.949425",\ + "6.386638, 6.340483, 6.310266, 6.298908, 6.312516"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[36]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.304626",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.229475",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200783, -0.156045, -0.102190, -0.060192, 0.330579",\ + "-0.289959, -0.245221, -0.193398, -0.151400, 0.241403",\ + "-0.449366, -0.404628, -0.350424, -0.308425, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[36]_hldr*/ + +} /* end of pin tl_i[36] */ + +pin("tl_i[35]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.023123 ; + + /* Other user defined attributes. */ + original_pin : tl_i[35]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.051503, 5.005348, 4.975131, 4.963773, 4.977381",\ + "5.138166, 5.092011, 5.061794, 5.050437, 5.064044",\ + "5.251214, 5.205059, 5.174842, 5.163485, 5.177092",\ + "5.450928, 5.404773, 5.374556, 5.363198, 5.376806",\ + "5.780051, 5.733896, 5.703679, 5.692322, 5.705929"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.051780, 5.005625, 4.975408, 4.964050, 4.977658",\ + "5.133488, 5.087333, 5.057116, 5.045758, 5.059366",\ + "5.260558, 5.214403, 5.184186, 5.172829, 5.186436",\ + "5.487176, 5.441021, 5.410804, 5.399446, 5.413054",\ + "5.889712, 5.843557, 5.813340, 5.801982, 5.815590"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[35]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.060002, 0.003106, 0.047821, 0.287989",\ + "-0.211450, -0.142185, -0.078960, -0.034194, 0.203312",\ + "-0.299321, -0.228917, -0.165692, -0.120927, 0.115291",\ + "-0.454448, -0.386390, -0.323164, -0.278399, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.117131, -0.065963, -0.008166, 0.033833, 0.413435",\ + "-0.206406, -0.159987, -0.102190, -0.060192, 0.324160",\ + "-0.303102, -0.251195, -0.193398, -0.151400, 0.227464",\ + "-0.474232, -0.408221, -0.350424, -0.308425, 0.053358",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.246898"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[35]_hldr*/ + +} /* end of pin tl_i[35] */ + +pin("tl_i[34]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.023475 ; + + /* Other user defined attributes. */ + original_pin : tl_i[34]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.659205, 5.613050, 5.582833, 5.571476, 5.585083",\ + "5.746680, 5.700525, 5.670308, 5.658950, 5.672558",\ + "5.833981, 5.787826, 5.757608, 5.746251, 5.759859",\ + "6.007267, 5.961112, 5.930894, 5.919537, 5.933145",\ + "6.412266, 6.366111, 6.335894, 6.324536, 6.338144"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.653732, 5.607577, 5.577360, 5.566003, 5.579610",\ + "5.742702, 5.696547, 5.666329, 5.654972, 5.668580",\ + "5.857737, 5.811582, 5.781364, 5.770007, 5.783615",\ + "6.095998, 6.049843, 6.019626, 6.008269, 6.021876",\ + "6.532254, 6.486099, 6.455882, 6.444524, 6.458132"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[34]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.126806, -0.060002, 0.003106, 0.047821, 0.287989",\ + "-0.211450, -0.142185, -0.078960, -0.034194, 0.203312",\ + "-0.299321, -0.228917, -0.165692, -0.120927, 0.115291",\ + "-0.454448, -0.386390, -0.323164, -0.278399, -0.040427",\ + "-0.633444, -0.567337, -0.509403, -0.467367, -0.247237"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.117131, -0.065963, -0.008166, 0.033833, 0.413435",\ + "-0.206406, -0.159987, -0.102190, -0.060192, 0.324160",\ + "-0.303102, -0.251195, -0.193398, -0.151400, 0.227464",\ + "-0.474232, -0.408221, -0.350424, -0.308425, 0.053358",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.246898"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[34]_hldr*/ + +} /* end of pin tl_i[34] */ + +pin("tl_i[33]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.026365 ; + + /* Other user defined attributes. */ + original_pin : tl_i[33]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.415846, 5.369691, 5.339474, 5.328116, 5.341724",\ + "5.492352, 5.446198, 5.415980, 5.404623, 5.418231",\ + "5.597322, 5.551167, 5.520950, 5.509593, 5.523201",\ + "5.785541, 5.739386, 5.709168, 5.697811, 5.711419",\ + "6.094803, 6.048648, 6.018431, 6.007074, 6.020681"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.396865, 5.350710, 5.320493, 5.309135, 5.322743",\ + "5.469503, 5.423348, 5.393131, 5.381774, 5.395381",\ + "5.589046, 5.542892, 5.512674, 5.501317, 5.514925",\ + "5.798637, 5.752482, 5.722265, 5.710908, 5.724515",\ + "6.156535, 6.110380, 6.080163, 6.068806, 6.082413"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[33]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103109, -0.028958, 0.033565, 0.078027, 0.304632",\ + "-0.177282, -0.103131, -0.040609, 0.003854, 0.230458",\ + "-0.245176, -0.171025, -0.108503, -0.064040, 0.162564",\ + "-0.354010, -0.279859, -0.217337, -0.172874, 0.053730",\ + "-0.518682, -0.444530, -0.382008, -0.337546, -0.110941"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.065963, -0.008166, 0.033833, 0.418070",\ + "-0.200788, -0.156050, -0.102190, -0.060192, 0.330575",\ + "-0.289964, -0.245226, -0.193398, -0.151400, 0.241399",\ + "-0.449371, -0.404633, -0.350424, -0.308425, 0.081992",\ + "-0.653554, -0.594763, -0.536828, -0.494793, -0.185077"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[33]_hldr*/ + +} /* end of pin tl_i[33] */ + +pin("tl_i[32]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025030 ; + + /* Other user defined attributes. */ + original_pin : tl_i[32]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.608686, 5.562531, 5.532314, 5.520957, 5.534564",\ + "5.696244, 5.650089, 5.619872, 5.608514, 5.622122",\ + "5.806668, 5.760513, 5.730296, 5.718939, 5.732546",\ + "5.996225, 5.950070, 5.919853, 5.908495, 5.922103",\ + "6.308736, 6.262581, 6.232364, 6.221007, 6.234614"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.604916, 5.558761, 5.528543, 5.517186, 5.530794",\ + "5.686645, 5.640490, 5.610272, 5.598915, 5.612523",\ + "5.804552, 5.758397, 5.728179, 5.716822, 5.730430",\ + "6.035892, 5.989738, 5.959520, 5.948163, 5.961771",\ + "6.435390, 6.389235, 6.359018, 6.347661, 6.361268"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[32]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103109, -0.028958, 0.033565, 0.078027, 0.315276",\ + "-0.177282, -0.103131, -0.040609, 0.003854, 0.236790",\ + "-0.245176, -0.171025, -0.108503, -0.064040, 0.162564",\ + "-0.354010, -0.279859, -0.217337, -0.172874, 0.053730",\ + "-0.518682, -0.444530, -0.382008, -0.337546, -0.110941"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200788, -0.135648, -0.078368, -0.036508, 0.330575",\ + "-0.289964, -0.226296, -0.169017, -0.127157, 0.241399",\ + "-0.449371, -0.387089, -0.329810, -0.287949, 0.081992",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185077"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[32]_hldr*/ + +} /* end of pin tl_i[32] */ + +pin("tl_i[31]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025825 ; + + /* Other user defined attributes. */ + original_pin : tl_i[31]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.156651, 5.110496, 5.080278, 5.068921, 5.082529",\ + "5.240004, 5.193849, 5.163631, 5.152274, 5.165882",\ + "5.328885, 5.282730, 5.252513, 5.241156, 5.254763",\ + "5.512913, 5.466758, 5.436541, 5.425183, 5.438791",\ + "5.849318, 5.803163, 5.772945, 5.761588, 5.775196"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.160699, 5.114544, 5.084327, 5.072970, 5.086577",\ + "5.238642, 5.192487, 5.162270, 5.150913, 5.164520",\ + "5.344724, 5.298569, 5.268352, 5.256994, 5.270602",\ + "5.598361, 5.552207, 5.521989, 5.510632, 5.524240",\ + "6.070027, 6.023872, 5.993655, 5.982297, 5.995905"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[31]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[31]_hldr*/ + +} /* end of pin tl_i[31] */ + +pin("tl_i[30]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025050 ; + + /* Other user defined attributes. */ + original_pin : tl_i[30]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.361538, 5.315383, 5.285166, 5.273808, 5.287416",\ + "5.445924, 5.399769, 5.369552, 5.358194, 5.371802",\ + "5.526791, 5.480636, 5.450418, 5.439061, 5.452669",\ + "5.668298, 5.622143, 5.591926, 5.580568, 5.594176",\ + "5.912872, 5.866717, 5.836500, 5.825143, 5.838750"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.346942, 5.300787, 5.270570, 5.259213, 5.272820",\ + "5.428506, 5.382351, 5.352134, 5.340776, 5.354384",\ + "5.534707, 5.488552, 5.458334, 5.446977, 5.460585",\ + "5.723008, 5.676853, 5.646636, 5.635279, 5.648886",\ + "6.057394, 6.011239, 5.981022, 5.969665, 5.983272"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[30]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[30]_hldr*/ + +} /* end of pin tl_i[30] */ + +pin("tl_i[29]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.026087 ; + + /* Other user defined attributes. */ + original_pin : tl_i[29]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.397203, 5.351048, 5.320831, 5.309474, 5.323081",\ + "5.485135, 5.438980, 5.408763, 5.397406, 5.411013",\ + "5.586405, 5.540250, 5.510033, 5.498675, 5.512283",\ + "5.772069, 5.725914, 5.695697, 5.684340, 5.697948",\ + "6.070103, 6.023948, 5.993731, 5.982373, 5.995981"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.401423, 5.355268, 5.325051, 5.313694, 5.327301",\ + "5.484715, 5.438560, 5.408342, 5.396985, 5.410593",\ + "5.608980, 5.562825, 5.532608, 5.521251, 5.534858",\ + "5.841204, 5.795049, 5.764832, 5.753474, 5.767082",\ + "6.247406, 6.201252, 6.171034, 6.159677, 6.173285"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[29]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[29]_hldr*/ + +} /* end of pin tl_i[29] */ + +pin("tl_i[28]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025799 ; + + /* Other user defined attributes. */ + original_pin : tl_i[28]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.618461, 5.572306, 5.542089, 5.530732, 5.544339",\ + "5.717470, 5.671315, 5.641098, 5.629741, 5.643348",\ + "5.855001, 5.808846, 5.778629, 5.767272, 5.780879",\ + "6.129478, 6.083323, 6.053106, 6.041749, 6.055356",\ + "6.630586, 6.584431, 6.554214, 6.542856, 6.556464"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.605847, 5.559692, 5.529475, 5.518118, 5.531725",\ + "5.703081, 5.656926, 5.626709, 5.615352, 5.628959",\ + "5.850164, 5.804009, 5.773792, 5.762435, 5.776042",\ + "6.157188, 6.111033, 6.080816, 6.069459, 6.083066",\ + "6.726156, 6.680001, 6.649784, 6.638427, 6.652034"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[28]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.515343, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.384569, -0.318431, -0.272351, 0.081996",\ + "-0.607923, -0.533171, -0.467033, -0.420953, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[28]_hldr*/ + +} /* end of pin tl_i[28] */ + +pin("tl_i[27]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025120 ; + + /* Other user defined attributes. */ + original_pin : tl_i[27]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.422370, 5.376215, 5.345998, 5.334641, 5.348248",\ + "5.509055, 5.462900, 5.432683, 5.421326, 5.434933",\ + "5.606899, 5.560744, 5.530527, 5.519170, 5.532777",\ + "5.815886, 5.769731, 5.739513, 5.728156, 5.741764",\ + "6.259951, 6.213796, 6.183579, 6.172222, 6.185829"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.415630, 5.369475, 5.339258, 5.327900, 5.341508",\ + "5.508262, 5.462107, 5.431890, 5.420532, 5.434140",\ + "5.634383, 5.588228, 5.558011, 5.546654, 5.560261",\ + "5.884534, 5.838379, 5.808162, 5.796804, 5.810412",\ + "6.321214, 6.275059, 6.244842, 6.233485, 6.247092"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[27]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[27]_hldr*/ + +} /* end of pin tl_i[27] */ + +pin("tl_i[26]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.025620 ; + + /* Other user defined attributes. */ + original_pin : tl_i[26]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.634807, 5.588652, 5.558434, 5.547077, 5.560685",\ + "5.726879, 5.680724, 5.650507, 5.639150, 5.652757",\ + "5.836696, 5.790541, 5.760324, 5.748966, 5.762574",\ + "6.041320, 5.995165, 5.964948, 5.953590, 5.967198",\ + "6.417303, 6.371148, 6.340931, 6.329574, 6.343181"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.627578, 5.581423, 5.551206, 5.539848, 5.553456",\ + "5.725660, 5.679505, 5.649288, 5.637930, 5.651538",\ + "5.857279, 5.811124, 5.780907, 5.769550, 5.783157",\ + "6.101712, 6.055557, 6.025340, 6.013983, 6.027590",\ + "6.528873, 6.482718, 6.452501, 6.441144, 6.454751"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[26]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[26]_hldr*/ + +} /* end of pin tl_i[26] */ + +pin("tl_i[25]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.027861 ; + + /* Other user defined attributes. */ + original_pin : tl_i[25]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.587914, 5.541759, 5.511542, 5.500185, 5.513792",\ + "5.685092, 5.638937, 5.608720, 5.597363, 5.610970",\ + "5.791002, 5.744847, 5.714630, 5.703273, 5.716880",\ + "5.984866, 5.938711, 5.908494, 5.897137, 5.910744",\ + "6.350015, 6.303860, 6.273643, 6.262286, 6.275893"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.597159, 5.551004, 5.520787, 5.509430, 5.523037",\ + "5.695459, 5.649304, 5.619087, 5.607729, 5.621337",\ + "5.810205, 5.764050, 5.733832, 5.722475, 5.736083",\ + "6.008989, 5.962834, 5.932617, 5.921260, 5.934867",\ + "6.374745, 6.328590, 6.298373, 6.287016, 6.300623"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[25]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[25]_hldr*/ + +} /* end of pin tl_i[25] */ + +pin("tl_i[24]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.026383 ; + + /* Other user defined attributes. */ + original_pin : tl_i[24]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.563736, 5.517581, 5.487364, 5.476007, 5.489614",\ + "5.661705, 5.615550, 5.585332, 5.573975, 5.587583",\ + "5.767614, 5.721459, 5.691242, 5.679884, 5.693492",\ + "5.957180, 5.911025, 5.880808, 5.869451, 5.883058",\ + "6.288558, 6.242403, 6.212186, 6.200829, 6.214436"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.590299, 5.544144, 5.513927, 5.502569, 5.516177",\ + "5.689440, 5.643285, 5.613068, 5.601710, 5.615318",\ + "5.803774, 5.757619, 5.727402, 5.716045, 5.729652",\ + "5.994250, 5.948095, 5.917878, 5.906520, 5.920128",\ + "6.312450, 6.266295, 6.236078, 6.224721, 6.238328"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[24]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.103114, -0.028963, 0.033559, 0.078022, 0.315276",\ + "-0.178370, -0.104212, -0.041630, 0.002858, 0.236790",\ + "-0.246264, -0.172106, -0.109525, -0.065037, 0.161580",\ + "-0.355098, -0.280940, -0.218359, -0.173870, 0.052747",\ + "-0.519769, -0.445611, -0.383030, -0.338542, -0.111925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.112706, -0.048572, 0.008708, 0.050568, 0.418070",\ + "-0.200783, -0.135648, -0.078368, -0.036508, 0.330579",\ + "-0.289959, -0.226296, -0.169017, -0.127157, 0.241403",\ + "-0.449366, -0.387089, -0.329810, -0.287949, 0.081996",\ + "-0.660870, -0.594763, -0.536828, -0.494793, -0.185073"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[24]_hldr*/ + +} /* end of pin tl_i[24] */ + +pin("tl_i[23]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[23]; +} /* end of pin tl_i[23] */ + +pin("tl_i[22]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[22]; +} /* end of pin tl_i[22] */ + +pin("tl_i[21]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[21]; +} /* end of pin tl_i[21] */ + +pin("tl_i[20]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[20]; +} /* end of pin tl_i[20] */ + +pin("tl_i[19]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_i[19]; +} /* end of pin tl_i[19] */ + +pin("tl_i[18]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005233 ; + + /* Other user defined attributes. */ + original_pin : tl_i[18]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.846815, 5.800660, 5.770443, 5.759086, 5.772694",\ + "5.932193, 5.886038, 5.855821, 5.844464, 5.858071",\ + "6.009590, 5.963435, 5.933218, 5.921861, 5.935469",\ + "6.178617, 6.132463, 6.102246, 6.090889, 6.104496",\ + "6.537492, 6.491337, 6.461120, 6.449763, 6.463370"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.843783, 5.797628, 5.767412, 5.756054, 5.769662",\ + "5.926365, 5.880210, 5.849993, 5.838636, 5.852243",\ + "6.038355, 5.992200, 5.961983, 5.950626, 5.964233",\ + "6.269215, 6.223060, 6.192843, 6.181486, 6.195093",\ + "6.674184, 6.628029, 6.597812, 6.586455, 6.600062"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[18]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.329740, -0.287323, -0.252837, -0.213389, 0.092961",\ + "-0.415095, -0.372677, -0.338191, -0.298743, 0.007607",\ + "-0.499351, -0.456933, -0.422448, -0.383000, -0.076649",\ + "-0.641023, -0.598605, -0.564119, -0.524671, -0.218321",\ + "-0.860645, -0.818228, -0.783742, -0.744294, -0.437944"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.392665, -0.350247, -0.315761, -0.276314, 0.030037",\ + "-0.480853, -0.438436, -0.403950, -0.364502, -0.058152",\ + "-0.581004, -0.538587, -0.504101, -0.464653, -0.158303",\ + "-0.765285, -0.722867, -0.665898, -0.623927, -0.342583",\ + "-1.010030, -0.967612, -0.918979, -0.877008, -0.587328"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[18]_hldr*/ + +} /* end of pin tl_i[18] */ + +pin("tl_i[17]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.004306 ; + + /* Other user defined attributes. */ + original_pin : tl_i[17]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.132060, 6.085905, 6.055688, 6.044331, 6.057939",\ + "6.217465, 6.171310, 6.141094, 6.129736, 6.143344",\ + "6.294953, 6.248798, 6.218582, 6.207224, 6.220832",\ + "6.439157, 6.393003, 6.362786, 6.351429, 6.365036",\ + "6.796788, 6.750633, 6.720417, 6.709059, 6.722667"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.129071, 6.082916, 6.052700, 6.041342, 6.054950",\ + "6.211690, 6.165535, 6.135318, 6.123961, 6.137568",\ + "6.323722, 6.277567, 6.247350, 6.235993, 6.249600",\ + "6.554055, 6.507900, 6.477684, 6.466326, 6.479934",\ + "6.957980, 6.911825, 6.881608, 6.870251, 6.883859"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[17]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.329387, -0.286969, -0.252483, -0.213035, 0.093315",\ + "-0.413395, -0.370977, -0.336491, -0.297044, 0.009307",\ + "-0.496847, -0.454429, -0.419944, -0.380496, -0.074145",\ + "-0.636423, -0.594005, -0.559520, -0.520072, -0.213721",\ + "-0.849170, -0.806753, -0.772267, -0.732819, -0.426469"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.397874, -0.355456, -0.320970, -0.281523, 0.024828",\ + "-0.486065, -0.443648, -0.409162, -0.369714, -0.063364",\ + "-0.585801, -0.543384, -0.506390, -0.464420, -0.163100",\ + "-0.770163, -0.720512, -0.662817, -0.620846, -0.347461",\ + "-1.005635, -0.963218, -0.913955, -0.871984, -0.582934"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[17]_hldr*/ + +} /* end of pin tl_i[17] */ + +pin("tl_i[16]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003506 ; + + /* Other user defined attributes. */ + original_pin : tl_i[16]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.061040, 6.014885, 5.984668, 5.973311, 5.986918",\ + "6.154351, 6.108196, 6.077980, 6.066622, 6.080230",\ + "6.247583, 6.201428, 6.171212, 6.159854, 6.173462",\ + "6.410316, 6.364161, 6.333944, 6.322587, 6.336194",\ + "6.686312, 6.640157, 6.609940, 6.598583, 6.612190"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.018520, 5.972365, 5.942149, 5.930791, 5.944399",\ + "6.115014, 6.068859, 6.038642, 6.027285, 6.040893",\ + "6.214722, 6.168567, 6.138350, 6.126993, 6.140600",\ + "6.391147, 6.344992, 6.314775, 6.303418, 6.317025",\ + "6.683747, 6.637592, 6.607376, 6.596018, 6.609626"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[16]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.394478, -0.352061, -0.317575, -0.278127, 0.028223",\ + "-0.483595, -0.441177, -0.404014, -0.362043, -0.060893",\ + "-0.569978, -0.527561, -0.480614, -0.438644, -0.147277",\ + "-0.718308, -0.666396, -0.608701, -0.566730, -0.295606",\ + "-0.932373, -0.866433, -0.808738, -0.766767, -0.544592"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.386365, -0.343947, -0.309462, -0.270014, 0.036337",\ + "-0.468621, -0.426203, -0.391718, -0.352270, -0.045919",\ + "-0.564853, -0.522435, -0.487950, -0.448502, -0.142151",\ + "-0.726358, -0.683941, -0.649455, -0.610007, -0.303657",\ + "-0.988854, -0.946436, -0.911950, -0.872503, -0.566152"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[16]_hldr*/ + +} /* end of pin tl_i[16] */ + +pin("tl_i[15]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.003647 ; + + /* Other user defined attributes. */ + original_pin : tl_i[15]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.804135, 5.757980, 5.727764, 5.716406, 5.730014",\ + "5.902175, 5.856020, 5.825803, 5.814446, 5.828053",\ + "6.008589, 5.962434, 5.932217, 5.920860, 5.934467",\ + "6.199651, 6.153496, 6.123279, 6.111922, 6.125529",\ + "6.533928, 6.487773, 6.457556, 6.446199, 6.459806"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.811823, 5.765668, 5.735451, 5.724094, 5.737701",\ + "5.911395, 5.865240, 5.835023, 5.823666, 5.837274",\ + "6.026561, 5.980406, 5.950189, 5.938832, 5.952439",\ + "6.220825, 6.174670, 6.144454, 6.133096, 6.146704",\ + "6.548571, 6.502416, 6.472199, 6.460842, 6.474449"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[15]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.333549, -0.291131, -0.256645, -0.217198, 0.089153",\ + "-0.416355, -0.373937, -0.339451, -0.300003, 0.006347",\ + "-0.498092, -0.455675, -0.421189, -0.381741, -0.075391",\ + "-0.641500, -0.599082, -0.564596, -0.525149, -0.218798",\ + "-0.881493, -0.839075, -0.804590, -0.765142, -0.458791"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.367074, -0.324657, -0.290171, -0.250723, 0.055627",\ + "-0.454947, -0.412529, -0.378044, -0.338596, -0.032245",\ + "-0.540971, -0.498554, -0.464068, -0.424620, -0.118270",\ + "-0.691009, -0.648592, -0.614106, -0.574658, -0.268308",\ + "-0.937715, -0.895297, -0.860812, -0.821364, -0.515013"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[15]_hldr*/ + +} /* end of pin tl_i[15] */ + +pin("tl_i[14]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[14]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.880361, 5.834206, 5.803989, 5.792632, 5.806239",\ + "5.967889, 5.921734, 5.891517, 5.880160, 5.893767",\ + "6.055178, 6.009023, 5.978806, 5.967449, 5.981056",\ + "6.230941, 6.184786, 6.154569, 6.143212, 6.156819",\ + "6.640085, 6.593930, 6.563713, 6.552356, 6.565963"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.875138, 5.828983, 5.798766, 5.787409, 5.801016",\ + "5.963992, 5.917837, 5.887620, 5.876263, 5.889871",\ + "6.079109, 6.032954, 6.002738, 5.991380, 6.004988",\ + "6.317663, 6.271508, 6.241292, 6.229934, 6.243542",\ + "6.755099, 6.708944, 6.678727, 6.667370, 6.680977"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[14]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.456322, -1.413945, -1.379366, -1.341730, -1.057874",\ + "-1.546534, -1.504156, -1.469577, -1.431942, -1.148085",\ + "-1.659324, -1.616947, -1.582367, -1.544732, -1.260875",\ + "-1.878867, -1.836490, -1.801910, -1.764275, -1.480418",\ + "-2.185190, -2.142812, -2.108233, -2.070598, -1.786741"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.489696, -1.447319, -1.412740, -1.375104, -1.091248",\ + "-1.579588, -1.537211, -1.502631, -1.464996, -1.181139",\ + "-1.675047, -1.632670, -1.598091, -1.560455, -1.276599",\ + "-1.845432, -1.803055, -1.768476, -1.730840, -1.446984",\ + "-2.145069, -2.102692, -2.068113, -2.030477, -1.746621"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[14]_hldr*/ + +} /* end of pin tl_i[14] */ + +pin("tl_i[13]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[13]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.164994, 6.118839, 6.088623, 6.077265, 6.090873",\ + "6.252498, 6.206343, 6.176126, 6.164769, 6.178376",\ + "6.339791, 6.293636, 6.263420, 6.252062, 6.265670",\ + "6.496986, 6.450831, 6.420614, 6.409257, 6.422864",\ + "6.898607, 6.852452, 6.822236, 6.810878, 6.824486"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "6.159660, 6.113505, 6.083289, 6.071931, 6.085539",\ + "6.248568, 6.202413, 6.172196, 6.160839, 6.174446",\ + "6.363653, 6.317498, 6.287282, 6.275924, 6.289532",\ + "6.601918, 6.555763, 6.525547, 6.514189, 6.527797",\ + "7.038295, 6.992140, 6.961923, 6.950566, 6.964173"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[13]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.676593, -1.628499, -1.570612, -1.528590, -1.278144",\ + "-1.766810, -1.718717, -1.660830, -1.618807, -1.368362",\ + "-1.879585, -1.831491, -1.773605, -1.731582, -1.481137",\ + "-2.098712, -2.050618, -1.992732, -1.950709, -1.700264",\ + "-2.408059, -2.359965, -2.302078, -2.260055, -2.009610"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.710053, -1.661959, -1.604072, -1.562050, -1.311604",\ + "-1.799952, -1.751858, -1.693972, -1.651949, -1.401504",\ + "-1.895418, -1.847324, -1.789437, -1.747415, -1.496969",\ + "-2.065788, -2.017694, -1.959808, -1.917785, -1.667340",\ + "-2.365375, -2.317281, -2.259394, -2.217371, -1.966926"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[13]_hldr*/ + +} /* end of pin tl_i[13] */ + +pin("tl_i[12]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001105 ; + + /* Other user defined attributes. */ + original_pin : tl_i[12]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.508289, 5.462134, 5.431918, 5.420560, 5.434168",\ + "5.592647, 5.546492, 5.516275, 5.504918, 5.518525",\ + "5.673546, 5.627391, 5.597174, 5.585817, 5.599424",\ + "5.815136, 5.768981, 5.738764, 5.727407, 5.741014",\ + "6.052000, 6.005845, 5.975628, 5.964271, 5.977879"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.430960, 5.384805, 5.354588, 5.343231, 5.356838",\ + "5.522353, 5.476198, 5.445981, 5.434624, 5.448231",\ + "5.614760, 5.568605, 5.538389, 5.527031, 5.540639",\ + "5.776403, 5.730248, 5.700032, 5.688674, 5.702282",\ + "6.049640, 6.003485, 5.973268, 5.961911, 5.975518"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[12]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.265898, -1.223521, -1.188942, -1.151306, -0.867450",\ + "-1.350510, -1.308133, -1.273553, -1.235918, -0.952061",\ + "-1.430668, -1.388291, -1.353711, -1.316076, -1.032219",\ + "-1.572586, -1.530209, -1.495630, -1.457994, -1.174138",\ + "-1.810084, -1.767707, -1.733127, -1.695492, -1.411635"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.242763, -1.200386, -1.165807, -1.128171, -0.844315",\ + "-1.334117, -1.291740, -1.257160, -1.219525, -0.935668",\ + "-1.427063, -1.384685, -1.350106, -1.312471, -1.028614",\ + "-1.589313, -1.546936, -1.512356, -1.474721, -1.190864",\ + "-1.862213, -1.819836, -1.785256, -1.747621, -1.463764"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[12]_hldr*/ + +} /* end of pin tl_i[12] */ + +pin("tl_i[11]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[11]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.261997, 5.215842, 5.185626, 5.174268, 5.187876",\ + "5.353421, 5.307266, 5.277050, 5.265692, 5.279300",\ + "5.463365, 5.417210, 5.386993, 5.375636, 5.389243",\ + "5.679752, 5.633597, 5.603381, 5.592023, 5.605631",\ + "6.088896, 6.042741, 6.012525, 6.001167, 6.014775"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.323949, 5.277794, 5.247577, 5.236220, 5.249827",\ + "5.412804, 5.366649, 5.336432, 5.325075, 5.338682",\ + "5.527921, 5.481766, 5.451549, 5.440192, 5.453799",\ + "5.766475, 5.720320, 5.690103, 5.678746, 5.692353",\ + "6.203910, 6.157755, 6.127538, 6.116181, 6.129788"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[11]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.231498, -1.189121, -1.154542, -1.116906, -0.833050",\ + "-1.321710, -1.279333, -1.244753, -1.207118, -0.923261",\ + "-1.434500, -1.392123, -1.357543, -1.319908, -1.036052",\ + "-1.654043, -1.611666, -1.577086, -1.539451, -1.255594",\ + "-2.055035, -2.012658, -1.978078, -1.940443, -1.656586"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.277769, -1.235391, -1.200812, -1.163177, -0.879320",\ + "-1.368203, -1.325825, -1.291246, -1.253611, -0.969754",\ + "-1.482250, -1.439872, -1.405293, -1.367658, -1.083801",\ + "-1.702415, -1.660038, -1.625458, -1.587823, -1.303966",\ + "-2.095423, -2.053046, -2.018466, -1.980831, -1.696974"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[11]_hldr*/ + +} /* end of pin tl_i[11] */ + +pin("tl_i[10]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[10]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.688106, 5.641951, 5.611734, 5.600377, 5.613985",\ + "5.775612, 5.729457, 5.699240, 5.687883, 5.701490",\ + "5.862906, 5.816751, 5.786535, 5.775177, 5.788785",\ + "6.017570, 5.971415, 5.941198, 5.929841, 5.943448",\ + "6.285493, 6.239338, 6.209121, 6.197764, 6.211371"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.621125, 5.574970, 5.544754, 5.533396, 5.547004",\ + "5.711027, 5.664872, 5.634655, 5.623298, 5.636906",\ + "5.806498, 5.760343, 5.730126, 5.718769, 5.732377",\ + "5.976879, 5.930724, 5.900507, 5.889150, 5.902758",\ + "6.276484, 6.230330, 6.200113, 6.188756, 6.202363"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[10]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.488494, -1.446116, -1.411537, -1.373901, -1.090045",\ + "-1.576000, -1.533622, -1.499043, -1.461408, -1.177551",\ + "-1.663294, -1.620917, -1.586338, -1.548702, -1.264846",\ + "-1.817957, -1.775580, -1.741001, -1.703365, -1.419509",\ + "-2.085881, -2.043503, -2.008924, -1.971289, -1.687432"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.387740, -1.345363, -1.310783, -1.273148, -0.989291",\ + "-1.477641, -1.435264, -1.400684, -1.363049, -1.079192",\ + "-1.573112, -1.530735, -1.496156, -1.458520, -1.174664",\ + "-1.743494, -1.701116, -1.666537, -1.628902, -1.345045",\ + "-2.043099, -2.000721, -1.966142, -1.928507, -1.644650"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[10]_hldr*/ + +} /* end of pin tl_i[10] */ + +pin("tl_i[9]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.299526, 5.253371, 5.223155, 5.211797, 5.225405",\ + "5.387030, 5.340875, 5.310658, 5.299301, 5.312908",\ + "5.474324, 5.428169, 5.397952, 5.386595, 5.400202",\ + "5.628947, 5.582792, 5.552575, 5.541218, 5.554825",\ + "5.896894, 5.850739, 5.820522, 5.809165, 5.822773"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.267633, 5.221478, 5.191262, 5.179904, 5.193512",\ + "5.357825, 5.311670, 5.281454, 5.270096, 5.283704",\ + "5.453746, 5.407591, 5.377375, 5.366017, 5.379625",\ + "5.626006, 5.579851, 5.549634, 5.538277, 5.551885",\ + "5.922129, 5.875974, 5.845757, 5.834400, 5.848007"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[9]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.240064, -1.197687, -1.163107, -1.125472, -0.841615",\ + "-1.327747, -1.285370, -1.250791, -1.213155, -0.929299",\ + "-1.415402, -1.373024, -1.338445, -1.300810, -1.016953",\ + "-1.572242, -1.529865, -1.495286, -1.457650, -1.173794",\ + "-1.840724, -1.798346, -1.763767, -1.726132, -1.442275"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.220831, -1.178454, -1.143874, -1.106239, -0.822382",\ + "-1.310730, -1.268353, -1.233773, -1.196138, -0.912281",\ + "-1.406196, -1.363818, -1.329239, -1.291603, -1.007747",\ + "-1.576566, -1.534189, -1.499609, -1.461974, -1.178117",\ + "-1.876152, -1.833775, -1.799196, -1.761560, -1.477704"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[9]_hldr*/ + +} /* end of pin tl_i[9] */ + +pin("tl_i[8]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.306569, 5.260414, 5.230197, 5.218840, 5.232448",\ + "5.394075, 5.347920, 5.317704, 5.306346, 5.319954",\ + "5.481370, 5.435215, 5.404998, 5.393641, 5.407248",\ + "5.636033, 5.589878, 5.559661, 5.548304, 5.561912",\ + "5.903956, 5.857801, 5.827585, 5.816227, 5.829835"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.239589, 5.193434, 5.163217, 5.151860, 5.165467",\ + "5.329490, 5.283335, 5.253119, 5.241761, 5.255369",\ + "5.424961, 5.378806, 5.348589, 5.337232, 5.350840",\ + "5.595343, 5.549188, 5.518971, 5.507614, 5.521221",\ + "5.894948, 5.848793, 5.818576, 5.807219, 5.820827"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[8]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.339799, -1.297422, -1.262842, -1.225207, -0.941350",\ + "-1.427305, -1.384928, -1.350348, -1.312713, -1.028856",\ + "-1.514600, -1.472222, -1.437643, -1.400007, -1.116151",\ + "-1.669263, -1.626886, -1.592306, -1.554671, -1.270814",\ + "-1.937186, -1.894809, -1.860229, -1.822594, -1.538737"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.239045, -1.196668, -1.162088, -1.124453, -0.840596",\ + "-1.328946, -1.286569, -1.251990, -1.214354, -0.930498",\ + "-1.424418, -1.382040, -1.347461, -1.309826, -1.025969",\ + "-1.594799, -1.552422, -1.517842, -1.480207, -1.196350",\ + "-1.894404, -1.852027, -1.817448, -1.779812, -1.495956"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[8]_hldr*/ + +} /* end of pin tl_i[8] */ + +pin("tl_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.737750, 5.691595, 5.661378, 5.650021, 5.663628",\ + "5.825280, 5.779125, 5.748908, 5.737551, 5.751158",\ + "5.912570, 5.866415, 5.836198, 5.824841, 5.838448",\ + "6.086271, 6.040116, 6.009899, 5.998541, 6.012149",\ + "6.495438, 6.449283, 6.419065, 6.407708, 6.421316"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.732527, 5.686372, 5.656155, 5.644798, 5.658405",\ + "5.821378, 5.775223, 5.745006, 5.733648, 5.747256",\ + "5.936484, 5.890329, 5.860112, 5.848755, 5.862362",\ + "6.175041, 6.128886, 6.098669, 6.087312, 6.100919",\ + "6.612741, 6.566586, 6.536369, 6.525012, 6.538620"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[7]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.210458, -1.168081, -1.133501, -1.095866, -0.812009",\ + "-1.300683, -1.258306, -1.223726, -1.186091, -0.902234",\ + "-1.413495, -1.371118, -1.336539, -1.298903, -1.015047",\ + "-1.594716, -1.552338, -1.517759, -1.480124, -1.196267",\ + "-1.863199, -1.820821, -1.786242, -1.748607, -1.464750"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.243829, -1.201452, -1.166873, -1.129237, -0.845381",\ + "-1.333722, -1.291345, -1.256766, -1.219130, -0.935274",\ + "-1.429188, -1.386811, -1.352232, -1.314596, -1.030740",\ + "-1.599584, -1.557206, -1.522627, -1.484991, -1.201135",\ + "-1.899240, -1.856863, -1.822283, -1.784648, -1.500791"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[7]_hldr*/ + +} /* end of pin tl_i[7] */ + +pin("tl_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001034 ; + + /* Other user defined attributes. */ + original_pin : tl_i[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.368608, 5.322453, 5.292236, 5.280879, 5.294487",\ + "5.454073, 5.407918, 5.377701, 5.366343, 5.379951",\ + "5.531495, 5.485340, 5.455123, 5.443766, 5.457373",\ + "5.675749, 5.629594, 5.599377, 5.588020, 5.601627",\ + "6.027932, 5.981777, 5.951560, 5.940202, 5.953810"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.365854, 5.319699, 5.289482, 5.278125, 5.291732",\ + "5.448556, 5.402401, 5.372184, 5.360826, 5.374434",\ + "5.560353, 5.514198, 5.483981, 5.472623, 5.486231",\ + "5.789183, 5.743028, 5.712811, 5.701454, 5.715061",\ + "6.188337, 6.142182, 6.111965, 6.100607, 6.114215"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[6]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.925690, -0.883313, -0.848733, -0.811098, -0.527241",\ + "-1.010422, -0.968045, -0.933465, -0.895830, -0.611973",\ + "-1.117256, -1.074878, -1.040299, -1.002663, -0.718807",\ + "-1.269870, -1.227492, -1.192913, -1.155277, -0.871421",\ + "-1.497461, -1.455084, -1.420505, -1.382869, -1.099013"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.942127, -0.899750, -0.865171, -0.827535, -0.543679",\ + "-1.032129, -0.989751, -0.955172, -0.917537, -0.633680",\ + "-1.120122, -1.077745, -1.043165, -1.005530, -0.721673",\ + "-1.275255, -1.232878, -1.198298, -1.160663, -0.876806",\ + "-1.540632, -1.498255, -1.463676, -1.426040, -1.142184"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[6]_hldr*/ + +} /* end of pin tl_i[6] */ + +pin("tl_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.646876, 5.600721, 5.570504, 5.559147, 5.572754",\ + "5.734406, 5.688251, 5.658034, 5.646677, 5.660285",\ + "5.821696, 5.775541, 5.745324, 5.733967, 5.747574",\ + "5.997414, 5.951259, 5.921041, 5.909684, 5.923292",\ + "6.406565, 6.360410, 6.330193, 6.318835, 6.332443"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "5.641654, 5.595499, 5.565282, 5.553925, 5.567532",\ + "5.730504, 5.684349, 5.654132, 5.642775, 5.656382",\ + "5.845611, 5.799456, 5.769239, 5.757882, 5.771489",\ + "6.084159, 6.038004, 6.007787, 5.996430, 6.010037",\ + "6.521860, 6.475705, 6.445487, 6.434130, 6.447738"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[5]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.106780, -1.064402, -1.029823, -0.992188, -0.708331",\ + "-1.197005, -1.154628, -1.120048, -1.082413, -0.798556",\ + "-1.309817, -1.267440, -1.232860, -1.195225, -0.911368",\ + "-1.491037, -1.448660, -1.414081, -1.376445, -1.092589",\ + "-1.759520, -1.717143, -1.682564, -1.644928, -1.361072"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-1.140151, -1.097774, -1.063194, -1.025559, -0.741702",\ + "-1.230044, -1.187667, -1.153087, -1.115452, -0.831595",\ + "-1.325510, -1.283133, -1.248553, -1.210918, -0.927061",\ + "-1.495905, -1.453528, -1.418948, -1.381313, -1.097456",\ + "-1.795562, -1.753184, -1.718605, -1.680969, -1.397113"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[5]_hldr*/ + +} /* end of pin tl_i[5] */ + +pin("tl_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001034 ; + + /* Other user defined attributes. */ + original_pin : tl_i[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.980015, 4.933860, 4.903643, 4.892286, 4.905893",\ + "5.065440, 5.019285, 4.989068, 4.977711, 4.991318",\ + "5.143021, 5.096866, 5.066648, 5.055291, 5.068899",\ + "5.322774, 5.276619, 5.246402, 5.235044, 5.248652",\ + "5.675738, 5.629583, 5.599366, 5.588009, 5.601616"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.977059, 4.930904, 4.900687, 4.889330, 4.902937",\ + "5.059716, 5.013561, 4.983344, 4.971986, 4.985594",\ + "5.171787, 5.125632, 5.095415, 5.084057, 5.097665",\ + "5.401430, 5.355275, 5.325058, 5.313701, 5.327308",\ + "5.800714, 5.754560, 5.724342, 5.712985, 5.726593"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.891577, -0.849200, -0.814620, -0.776985, -0.493128",\ + "-0.976303, -0.933926, -0.899346, -0.861711, -0.577854",\ + "-1.083459, -1.041082, -1.006503, -0.968867, -0.685011",\ + "-1.234205, -1.191828, -1.157249, -1.119613, -0.835757",\ + "-1.461877, -1.419500, -1.384920, -1.347285, -1.063428"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.907849, -0.865472, -0.830893, -0.793257, -0.509401",\ + "-0.997841, -0.955464, -0.920885, -0.883249, -0.599393",\ + "-1.085765, -1.043387, -1.008808, -0.971172, -0.687316",\ + "-1.240999, -1.198622, -1.164043, -1.126407, -0.842551",\ + "-1.506646, -1.464268, -1.429689, -1.392054, -1.108197"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[4]_hldr*/ + +} /* end of pin tl_i[4] */ + +pin("tl_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000507 ; + + /* Other user defined attributes. */ + original_pin : tl_i[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.861817, 4.815662, 4.785445, 4.774088, 4.787695",\ + "4.949495, 4.903340, 4.873123, 4.861766, 4.875373",\ + "5.036715, 4.990560, 4.960342, 4.948985, 4.962593",\ + "5.207161, 5.161006, 5.130789, 5.119431, 5.133039",\ + "5.608678, 5.562523, 5.532306, 5.520948, 5.534556"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.856341, 4.810186, 4.779969, 4.768611, 4.782219",\ + "4.945419, 4.899264, 4.869047, 4.857689, 4.871297",\ + "5.060649, 5.014494, 4.984277, 4.972920, 4.986527",\ + "5.297888, 5.251733, 5.221516, 5.210158, 5.223766",\ + "5.732176, 5.686021, 5.655804, 5.644446, 5.658054"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.940665, -0.898288, -0.863709, -0.826073, -0.542217",\ + "-1.030843, -0.988466, -0.953887, -0.916251, -0.632395",\ + "-1.143556, -1.101179, -1.066599, -1.028964, -0.745108",\ + "-1.327817, -1.285440, -1.250861, -1.213225, -0.929369",\ + "-1.596320, -1.553943, -1.519363, -1.481728, -1.197871"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.974330, -0.931952, -0.897373, -0.859738, -0.575881",\ + "-1.064250, -1.021872, -0.987293, -0.949658, -0.665801",\ + "-1.159754, -1.117377, -1.082797, -1.045162, -0.761305",\ + "-1.330068, -1.287690, -1.253111, -1.215476, -0.931619",\ + "-1.629461, -1.587083, -1.552504, -1.514869, -1.231012"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[3]_hldr*/ + +} /* end of pin tl_i[3] */ + +pin("tl_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001034 ; + + /* Other user defined attributes. */ + original_pin : tl_i[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.870526, 4.824371, 4.794154, 4.782797, 4.796404",\ + "4.955990, 4.909835, 4.879618, 4.868261, 4.881868",\ + "5.033412, 4.987257, 4.957040, 4.945683, 4.959291",\ + "5.177666, 5.131511, 5.101294, 5.089936, 5.103544",\ + "5.529849, 5.483694, 5.453477, 5.442120, 5.455727"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.867772, 4.821617, 4.791399, 4.780042, 4.793650",\ + "4.950474, 4.904319, 4.874102, 4.862744, 4.876352",\ + "5.062271, 5.016116, 4.985898, 4.974541, 4.988149",\ + "5.291101, 5.244946, 5.214728, 5.203371, 5.216979",\ + "5.690255, 5.644100, 5.613883, 5.602525, 5.616133"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.870275, -0.827898, -0.793318, -0.755683, -0.471826",\ + "-0.955007, -0.912630, -0.878051, -0.840415, -0.556558",\ + "-1.061841, -1.019464, -0.984884, -0.947249, -0.663392",\ + "-1.214455, -1.172078, -1.137498, -1.099863, -0.816006",\ + "-1.442046, -1.399669, -1.365090, -1.327454, -1.043598"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.886713, -0.844335, -0.809756, -0.772120, -0.488264",\ + "-0.976714, -0.934337, -0.899757, -0.862122, -0.578265",\ + "-1.064707, -1.022330, -0.987750, -0.950115, -0.666258",\ + "-1.219840, -1.177463, -1.142883, -1.105248, -0.821391",\ + "-1.485218, -1.442840, -1.408261, -1.370625, -1.086769"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[2]_hldr*/ + +} /* end of pin tl_i[2] */ + +pin("tl_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001034 ; + + /* Other user defined attributes. */ + original_pin : tl_i[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.874022, 4.827868, 4.797650, 4.786293, 4.799901",\ + "4.959486, 4.913332, 4.883114, 4.871757, 4.885365",\ + "5.036908, 4.990753, 4.960536, 4.949179, 4.962786",\ + "5.181162, 5.135007, 5.104790, 5.093432, 5.107040",\ + "5.533345, 5.487190, 5.456973, 5.445615, 5.459223"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "4.871267, 4.825112, 4.794895, 4.783538, 4.797145",\ + "4.953969, 4.907815, 4.877597, 4.866240, 4.879848",\ + "5.065766, 5.019611, 4.989394, 4.978037, 4.991644",\ + "5.294597, 5.248442, 5.218225, 5.206867, 5.220475",\ + "5.693750, 5.647595, 5.617378, 5.606021, 5.619628"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.871744, -0.829367, -0.794788, -0.757152, -0.473296",\ + "-0.956476, -0.914099, -0.879520, -0.841884, -0.558028",\ + "-1.063310, -1.020933, -0.986354, -0.948718, -0.664862",\ + "-1.215924, -1.173547, -1.138968, -1.101332, -0.817476",\ + "-1.443516, -1.401139, -1.366559, -1.328924, -1.045067"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.888182, -0.845805, -0.811225, -0.773590, -0.489733",\ + "-0.978183, -0.935806, -0.901227, -0.863591, -0.579735",\ + "-1.066176, -1.023799, -0.989220, -0.951584, -0.667728",\ + "-1.221309, -1.178932, -1.144353, -1.106717, -0.822861",\ + "-1.486687, -1.444310, -1.409730, -1.372095, -1.088238"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[1]_hldr*/ + +} /* end of pin tl_i[1] */ + +pin("tl_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000516 ; + + /* Other user defined attributes. */ + original_pin : tl_i[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.175613, 0.100294, 0.032151, 0.009209, 0.072356",\ + "0.264638, 0.189339, 0.121299, 0.098527, 0.163209",\ + "0.360287, 0.285032, 0.217232, 0.194849, 0.263068",\ + "0.526788, 0.451609, 0.383810, 0.361643, 0.432490",\ + "0.806358, 0.731299, 0.662593, 0.639784, 0.707364"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.201785, 0.154982, 0.124714, 0.113318, 0.126704",\ + "0.285559, 0.238387, 0.208091, 0.196673, 0.209933",\ + "0.386189, 0.338377, 0.307866, 0.296333, 0.309292",\ + "0.553781, 0.505930, 0.474764, 0.462933, 0.475551",\ + "0.832990, 0.785063, 0.752603, 0.740184, 0.752132"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.088868, -0.022902, 0.034829, 0.076810, 0.297292",\ + "-0.178002, -0.111712, -0.053514, -0.011408, 0.208267",\ + "-0.273901, -0.206863, -0.147593, -0.105196, 0.112621",\ + "-0.440525, -0.372044, -0.311267, -0.268345, -0.051699",\ + "-0.719618, -0.648392, -0.585857, -0.542000, -0.322826"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.133037, -0.090779, -0.055923, -0.023644, 0.193736",\ + "-0.216520, -0.174329, -0.139318, -0.110044, 0.070036",\ + "-0.315601, -0.273256, -0.237974, -0.213810, -0.097198",\ + "-0.479066, -0.435673, -0.400366, -0.376078, -0.258082",\ + "-0.750133, -0.704672, -0.669317, -0.644785, -0.524056"); + } + + } /* end of arc clk_ast_tlul_i_tl_i[0]_hldr*/ + +} /* end of pin tl_i[0] */ +} /* end of bus tl_i */ +bus ( tl_o ) { + + bus_type : BUS66_type1 ; + direction : output ; + +pin("tl_o[65]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000991 ; + + /* Other user defined attributes. */ + original_pin : tl_o[65]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.044997, 0.199162, 0.375038, 0.698306, 1.344843",\ + "0.131049, 0.286337, 0.462145, 0.785022, 1.430777",\ + "0.213199, 0.374466, 0.550102, 0.872645, 1.517732",\ + "0.270183, 0.438865, 0.614219, 0.936559, 1.581241",\ + "0.564592, 0.788723, 0.964610, 1.285306, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.020343, 0.295887, 0.630096, 1.247585, 2.482563",\ + "0.025257, 0.296852, 0.632059, 1.247585, 2.482563",\ + "0.038535, 0.299143, 0.632095, 1.247585, 2.482563",\ + "0.050320, 0.302473, 0.632193, 1.247585, 2.482563",\ + "0.124837, 0.341325, 0.638465, 1.250160, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.064792, 0.171653, 0.283425, 0.487864, 0.896742",\ + "0.152284, 0.258972, 0.370706, 0.575169, 0.984096",\ + "0.232529, 0.339311, 0.450733, 0.655198, 1.064127",\ + "0.289052, 0.396859, 0.508277, 0.712443, 1.120775",\ + "0.581256, 0.700191, 0.811913, 1.015459, 1.422552"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.021933, 0.185126, 0.386052, 0.758836, 1.504404",\ + "0.021933, 0.185264, 0.386558, 0.758836, 1.504404",\ + "0.022969, 0.185264, 0.386558, 0.758836, 1.504404",\ + "0.025189, 0.185264, 0.386558, 0.758836, 1.504404",\ + "0.044032, 0.189320, 0.386558, 0.758836, 1.504684"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[65]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.044997, 0.199162, 0.375038, 0.698306, 1.344843",\ + "0.131049, 0.286337, 0.462145, 0.785022, 1.430777",\ + "0.213199, 0.374466, 0.550102, 0.872645, 1.517732",\ + "0.270183, 0.438865, 0.614219, 0.936559, 1.581241",\ + "0.564592, 0.788723, 0.964610, 1.285306, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.020343, 0.295887, 0.630096, 1.246366, 2.473547",\ + "0.025257, 0.296852, 0.632059, 1.246366, 2.473547",\ + "0.038535, 0.299143, 0.632095, 1.246442, 2.473547",\ + "0.050320, 0.302473, 0.632193, 1.247184, 2.473547",\ + "0.124837, 0.341325, 0.638465, 1.250160, 2.473547"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.064792, 0.171653, 0.283425, 0.487864, 0.896742",\ + "0.152284, 0.258972, 0.370706, 0.575169, 0.984096",\ + "0.232529, 0.339311, 0.450733, 0.655198, 1.064127",\ + "0.289052, 0.396859, 0.508277, 0.712443, 1.120775",\ + "0.581256, 0.700191, 0.811913, 1.015459, 1.422552"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.021933, 0.184336, 0.384548, 0.756608, 1.500727",\ + "0.021933, 0.184336, 0.384548, 0.756608, 1.500727",\ + "0.022969, 0.184336, 0.384548, 0.756608, 1.500727",\ + "0.025189, 0.184950, 0.385003, 0.757508, 1.502518",\ + "0.044032, 0.189320, 0.385072, 0.758276, 1.504684"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[65]_redg_min*/ + +} /* end of pin tl_o[65] */ + +pin("tl_o[64]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[64]; +} /* end of pin tl_o[64] */ + +pin("tl_o[63]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[63]; +} /* end of pin tl_o[63] */ + +pin("tl_o[62]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002088 ; + + /* Other user defined attributes. */ + original_pin : tl_o[62]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.048389, 0.201372, 0.376697, 0.699413, 1.344843",\ + "0.134717, 0.288547, 0.463802, 0.786127, 1.430777",\ + "0.217972, 0.376674, 0.551758, 0.873749, 1.517732",\ + "0.275938, 0.441068, 0.615873, 0.937662, 1.581241",\ + "0.576253, 0.790939, 0.966256, 1.286403, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.024378, 0.300079, 0.633266, 1.249698, 2.482563",\ + "0.028867, 0.301069, 0.635212, 1.249698, 2.482563",\ + "0.041784, 0.303321, 0.635248, 1.249698, 2.482563",\ + "0.053694, 0.306596, 0.635350, 1.249698, 2.482563",\ + "0.129380, 0.344908, 0.641605, 1.252253, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.068004, 0.173028, 0.284443, 0.488532, 0.896711",\ + "0.155415, 0.260346, 0.371724, 0.575838, 0.984064",\ + "0.235777, 0.340680, 0.451751, 0.655866, 1.064096",\ + "0.292479, 0.398229, 0.509294, 0.713111, 1.120744",\ + "0.586381, 0.701567, 0.812926, 1.016124, 1.422520"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.024753, 0.187586, 0.387908, 0.760055, 1.504347",\ + "0.024753, 0.187732, 0.388412, 0.760055, 1.504347",\ + "0.025828, 0.187732, 0.388412, 0.760055, 1.504347",\ + "0.027889, 0.187732, 0.388412, 0.760055, 1.504347",\ + "0.046464, 0.191695, 0.388412, 0.760055, 1.504627"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[62]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.048389, 0.201372, 0.376697, 0.699413, 1.344843",\ + "0.134717, 0.288547, 0.463802, 0.786127, 1.430777",\ + "0.217972, 0.376674, 0.551758, 0.873749, 1.517732",\ + "0.275938, 0.441068, 0.615873, 0.937662, 1.581241",\ + "0.576253, 0.790939, 0.966256, 1.286403, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.024378, 0.300079, 0.633266, 1.248468, 2.473548",\ + "0.028867, 0.301069, 0.635212, 1.248468, 2.473548",\ + "0.041784, 0.303321, 0.635248, 1.248544, 2.473548",\ + "0.053694, 0.306596, 0.635350, 1.249288, 2.473548",\ + "0.129380, 0.344908, 0.641605, 1.252253, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.068004, 0.173028, 0.284443, 0.488532, 0.896711",\ + "0.155415, 0.260346, 0.371724, 0.575838, 0.984064",\ + "0.235777, 0.340680, 0.451751, 0.655866, 1.064096",\ + "0.292479, 0.398229, 0.509294, 0.713111, 1.120744",\ + "0.586381, 0.701567, 0.812926, 1.016124, 1.422520"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.024753, 0.186786, 0.386401, 0.757824, 1.500670",\ + "0.024753, 0.186786, 0.386401, 0.757824, 1.500670",\ + "0.025828, 0.186786, 0.386401, 0.757824, 1.500670",\ + "0.027889, 0.187397, 0.386858, 0.758726, 1.502461",\ + "0.046464, 0.191695, 0.386930, 0.759496, 1.504627"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[62]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024378, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.218049, 0.171947, 0.141734, 0.130380, 0.144005",\ + "0.225343, 0.179241, 0.149028, 0.137673, 0.151299",\ + "0.298206, 0.252060, 0.221844, 0.210487, 0.224097",\ + "0.392136, 0.345682, 0.315442, 0.304067, 0.317572",\ + "0.819837, 0.772019, 0.741401, 0.729820, 0.742723"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.263674, 0.188357, 0.120223, 0.097297, 0.160585",\ + "0.270643, 0.195326, 0.127193, 0.104267, 0.167554",\ + "0.342134, 0.266818, 0.198684, 0.175758, 0.239045",\ + "0.448695, 0.373390, 0.305321, 0.282500, 0.346742",\ + "0.946962, 0.871764, 0.804107, 0.782042, 0.853404"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[62]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024378, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139030, -0.096614, -0.062124, -0.022751, 0.282672",\ + "-0.146290, -0.103874, -0.069385, -0.030012, 0.275412",\ + "-0.217578, -0.175163, -0.140673, -0.101300, 0.204124",\ + "-0.305582, -0.263210, -0.228618, -0.191228, 0.089586",\ + "-0.705049, -0.662905, -0.627627, -0.603487, -0.487141"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.129024, -0.063245, -0.005781, 0.036127, 0.257073",\ + "-0.136957, -0.071178, -0.013715, 0.028194, 0.249139",\ + "-0.213653, -0.147874, -0.090410, -0.048501, 0.172444",\ + "-0.315404, -0.249338, -0.191464, -0.149444, 0.070790",\ + "-0.774971, -0.707116, -0.646741, -0.604032, -0.387962"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[62]_hldr*/ + +} /* end of pin tl_o[62] */ + +pin("tl_o[61]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[61]; +} /* end of pin tl_o[61] */ + +pin("tl_o[60]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[60]; +} /* end of pin tl_o[60] */ + +pin("tl_o[59]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[59]; +} /* end of pin tl_o[59] */ + +pin("tl_o[58]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003360 ; + + /* Other user defined attributes. */ + original_pin : tl_o[58]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.051828, 0.203934, 0.378621, 0.700695, 1.344843",\ + "0.138345, 0.291109, 0.465724, 0.787408, 1.430777",\ + "0.222447, 0.379233, 0.553677, 0.875029, 1.517732",\ + "0.281266, 0.443623, 0.617791, 0.938941, 1.581241",\ + "0.586734, 0.793508, 0.968165, 1.287675, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.028994, 0.304939, 0.636940, 1.252148, 2.482564",\ + "0.033002, 0.305957, 0.638867, 1.252148, 2.482564",\ + "0.045411, 0.308165, 0.638904, 1.252148, 2.482564",\ + "0.057383, 0.311375, 0.639010, 1.252148, 2.482564",\ + "0.134005, 0.349063, 0.645245, 1.254679, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.070957, 0.174574, 0.285576, 0.489260, 0.896627",\ + "0.158358, 0.261892, 0.372857, 0.576565, 0.983980",\ + "0.238767, 0.342220, 0.452884, 0.656593, 1.064012",\ + "0.295587, 0.399770, 0.510425, 0.713837, 1.120660",\ + "0.590723, 0.703115, 0.814054, 1.016848, 1.422437"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.027799, 0.190353, 0.389974, 0.761380, 1.504194",\ + "0.027799, 0.190507, 0.390474, 0.761380, 1.504194",\ + "0.028742, 0.190507, 0.390474, 0.761380, 1.504194",\ + "0.030673, 0.190507, 0.390474, 0.761380, 1.504194",\ + "0.048664, 0.194365, 0.390474, 0.761380, 1.504474"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[58]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.051828, 0.203934, 0.378621, 0.700695, 1.344843",\ + "0.138345, 0.291109, 0.465724, 0.787408, 1.430777",\ + "0.222447, 0.379233, 0.553677, 0.875029, 1.517732",\ + "0.281266, 0.443623, 0.617791, 0.938941, 1.581241",\ + "0.586734, 0.793508, 0.968165, 1.287675, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.028994, 0.304939, 0.636940, 1.250905, 2.473548",\ + "0.033002, 0.305957, 0.638867, 1.250905, 2.473548",\ + "0.045411, 0.308165, 0.638904, 1.250981, 2.473548",\ + "0.057383, 0.311375, 0.639010, 1.251728, 2.473548",\ + "0.134005, 0.349063, 0.645245, 1.254679, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.070957, 0.174574, 0.285576, 0.489260, 0.896627",\ + "0.158358, 0.261892, 0.372857, 0.576565, 0.983980",\ + "0.238767, 0.342220, 0.452884, 0.656593, 1.064012",\ + "0.295587, 0.399770, 0.510425, 0.713837, 1.120660",\ + "0.590723, 0.703115, 0.814054, 1.016848, 1.422437"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.027799, 0.189542, 0.388462, 0.759147, 1.500517",\ + "0.027799, 0.189542, 0.388462, 0.759147, 1.500517",\ + "0.028742, 0.189542, 0.388462, 0.759147, 1.500517",\ + "0.030673, 0.190148, 0.388922, 0.760051, 1.502309",\ + "0.048664, 0.194365, 0.388998, 0.760823, 1.504474"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[58]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028994, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.218252, 0.172323, 0.142124, 0.130780, 0.144465",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027799, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252073, 0.176751, 0.108592, 0.085625, 0.148539",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[58]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028994, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.150180, -0.107763, -0.073276, -0.033852, 0.272195",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027799, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.165228, -0.099313, -0.041654, 0.000307, 0.220914",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[58]_hldr*/ + +} /* end of pin tl_o[58] */ + +pin("tl_o[57]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002160 ; + + /* Other user defined attributes. */ + original_pin : tl_o[57]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.048582, 0.201516, 0.376805, 0.699484, 1.344843",\ + "0.134920, 0.288690, 0.463910, 0.786199, 1.430777",\ + "0.218223, 0.376818, 0.551865, 0.873821, 1.517732",\ + "0.276237, 0.441212, 0.615981, 0.937734, 1.581241",\ + "0.576841, 0.791083, 0.966363, 1.286475, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.024637, 0.300352, 0.633472, 1.249836, 2.482563",\ + "0.029099, 0.301343, 0.635417, 1.249836, 2.482563",\ + "0.041988, 0.303593, 0.635453, 1.249836, 2.482563",\ + "0.053901, 0.306864, 0.635555, 1.249836, 2.482563",\ + "0.129639, 0.345141, 0.641809, 1.252389, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.068110, 0.173083, 0.284476, 0.488542, 0.896675",\ + "0.155520, 0.260402, 0.371756, 0.575847, 0.984028",\ + "0.235884, 0.340735, 0.451783, 0.655876, 1.064060",\ + "0.292590, 0.398284, 0.509326, 0.713120, 1.120708",\ + "0.586537, 0.701623, 0.812958, 1.016134, 1.422485"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.024862, 0.187685, 0.387967, 0.760072, 1.504282",\ + "0.024862, 0.187831, 0.388471, 0.760072, 1.504282",\ + "0.025932, 0.187831, 0.388471, 0.760072, 1.504282",\ + "0.027989, 0.187831, 0.388471, 0.760072, 1.504282",\ + "0.046543, 0.191790, 0.388471, 0.760072, 1.504562"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[57]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.048582, 0.201516, 0.376805, 0.699484, 1.344843",\ + "0.134920, 0.288690, 0.463910, 0.786199, 1.430777",\ + "0.218223, 0.376818, 0.551865, 0.873821, 1.517732",\ + "0.276237, 0.441212, 0.615981, 0.937734, 1.581241",\ + "0.576841, 0.791083, 0.966363, 1.286475, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.024637, 0.300352, 0.633472, 1.248605, 2.473548",\ + "0.029099, 0.301343, 0.635417, 1.248605, 2.473548",\ + "0.041988, 0.303593, 0.635453, 1.248680, 2.473548",\ + "0.053901, 0.306864, 0.635555, 1.249425, 2.473548",\ + "0.129639, 0.345141, 0.641809, 1.252389, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.068110, 0.173083, 0.284476, 0.488542, 0.896675",\ + "0.155520, 0.260402, 0.371756, 0.575847, 0.984028",\ + "0.235884, 0.340735, 0.451783, 0.655876, 1.064060",\ + "0.292590, 0.398284, 0.509326, 0.713120, 1.120708",\ + "0.586537, 0.701623, 0.812958, 1.016134, 1.422485"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.024862, 0.186885, 0.386460, 0.757841, 1.500604",\ + "0.024862, 0.186885, 0.386460, 0.757841, 1.500604",\ + "0.025932, 0.186885, 0.386460, 0.757841, 1.500604",\ + "0.027989, 0.187495, 0.386917, 0.758743, 1.502396",\ + "0.046543, 0.191790, 0.386989, 0.759514, 1.504562"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[57]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024637, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216235, 0.170306, 0.140106, 0.128763, 0.142448",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024862, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250736, 0.175414, 0.107255, 0.084288, 0.147202",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[57]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024637, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148162, -0.105745, -0.071258, -0.031835, 0.274212",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024862, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163891, -0.097976, -0.040317, 0.001644, 0.222251",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[57]_hldr*/ + +} /* end of pin tl_o[57] */ + +pin("tl_o[56]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[56]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[56]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[56]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[56]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[56]_hldr*/ + +} /* end of pin tl_o[56] */ + +pin("tl_o[55]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[55]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[55]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[55]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[55]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[55]_hldr*/ + +} /* end of pin tl_o[55] */ + +pin("tl_o[54]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[54]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[54]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[54]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[54]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[54]_hldr*/ + +} /* end of pin tl_o[54] */ + +pin("tl_o[53]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[53]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[53]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[53]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[53]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[53]_hldr*/ + +} /* end of pin tl_o[53] */ + +pin("tl_o[52]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[52]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[52]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[52]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[52]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[52]_hldr*/ + +} /* end of pin tl_o[52] */ + +pin("tl_o[51]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[51]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[51]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[51]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[51]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[51]_hldr*/ + +} /* end of pin tl_o[51] */ + +pin("tl_o[50]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[50]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[50]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[50]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[50]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[50]_hldr*/ + +} /* end of pin tl_o[50] */ + +pin("tl_o[49]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : tl_o[49]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.246634, 2.482563",\ + "0.023601, 0.294955, 0.630640, 1.246634, 2.482563",\ + "0.036987, 0.297263, 0.630676, 1.246634, 2.482563",\ + "0.048667, 0.300618, 0.630773, 1.246634, 2.482563",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.184048, 0.385247, 0.758318, 1.504460",\ + "0.020634, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.021564, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.023878, 0.184183, 0.385754, 0.758318, 1.504460",\ + "0.042695, 0.188280, 0.385754, 0.758318, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[49]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.043170, 0.198167, 0.374291, 0.697809, 1.344843",\ + "0.129019, 0.285342, 0.461399, 0.784525, 1.430777",\ + "0.210407, 0.373473, 0.549357, 0.872149, 1.517732",\ + "0.266777, 0.437873, 0.613474, 0.936063, 1.581241",\ + "0.557497, 0.787726, 0.963869, 1.284812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.018489, 0.294000, 0.628670, 1.245420, 2.473548",\ + "0.023601, 0.294955, 0.630640, 1.245420, 2.473548",\ + "0.036987, 0.297263, 0.630676, 1.245495, 2.473548",\ + "0.048667, 0.300618, 0.630773, 1.246236, 2.473548",\ + "0.122402, 0.339712, 0.637052, 1.249217, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.063051, 0.171050, 0.282984, 0.487580, 0.896773",\ + "0.150620, 0.258370, 0.370264, 0.574885, 0.984126",\ + "0.230770, 0.338711, 0.450291, 0.654914, 1.064158",\ + "0.287173, 0.396259, 0.507836, 0.712159, 1.120806",\ + "0.578289, 0.699588, 0.811473, 1.015176, 1.422582"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000498, 0.073496, 0.160876, 0.321254, 0.642011"); + values ( "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.020634, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.021564, 0.183263, 0.383745, 0.756091, 1.500782",\ + "0.023878, 0.183878, 0.384198, 0.756990, 1.502574",\ + "0.042695, 0.188280, 0.384266, 0.757757, 1.504740"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[49]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.213388, 0.167459, 0.137260, 0.125916, 0.139601",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.248811, 0.173490, 0.105331, 0.082363, 0.145277",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[49]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018489, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.145316, -0.102899, -0.068412, -0.028988, 0.277059",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020634, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.161967, -0.096052, -0.038393, 0.003568, 0.224175",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[49]_hldr*/ + +} /* end of pin tl_o[49] */ + +pin("tl_o[48]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.153409 ; + min_capacitance : 0.000000 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.009004 ; + + /* Other user defined attributes. */ + original_pin : tl_o[48]; +} /* end of pin tl_o[48] */ + +pin("tl_o[47]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002792 ; + + /* Other user defined attributes. */ + original_pin : tl_o[47]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.050293, 0.202790, 0.377762, 0.700122, 1.344843",\ + "0.136725, 0.289965, 0.464866, 0.786836, 1.430777",\ + "0.220450, 0.378091, 0.552820, 0.874457, 1.517732",\ + "0.278888, 0.442483, 0.616935, 0.938370, 1.581241",\ + "0.582056, 0.792362, 0.967313, 1.287108, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026933, 0.302770, 0.635300, 1.251054, 2.482563",\ + "0.031156, 0.303775, 0.637236, 1.251054, 2.482563",\ + "0.043792, 0.306003, 0.637272, 1.251054, 2.482563",\ + "0.055737, 0.309242, 0.637376, 1.251054, 2.482563",\ + "0.131941, 0.347209, 0.643620, 1.253596, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.069683, 0.173907, 0.285093, 0.488958, 0.896688",\ + "0.157089, 0.261225, 0.372374, 0.576263, 0.984041",\ + "0.237477, 0.341556, 0.452401, 0.656292, 1.064073",\ + "0.294246, 0.399105, 0.509943, 0.713536, 1.120720",\ + "0.588850, 0.702448, 0.813573, 1.016548, 1.422497"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026485, 0.189160, 0.389094, 0.760831, 1.504305",\ + "0.026485, 0.189310, 0.389596, 0.760831, 1.504305",\ + "0.027485, 0.189310, 0.389596, 0.760831, 1.504305",\ + "0.029472, 0.189310, 0.389596, 0.760831, 1.504305",\ + "0.047715, 0.193213, 0.389596, 0.760831, 1.504585"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[47]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.050293, 0.202790, 0.377762, 0.700122, 1.344843",\ + "0.136725, 0.289965, 0.464866, 0.786836, 1.430777",\ + "0.220450, 0.378091, 0.552820, 0.874457, 1.517732",\ + "0.278888, 0.442483, 0.616935, 0.938370, 1.581241",\ + "0.582056, 0.792362, 0.967313, 1.287108, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026933, 0.302770, 0.635300, 1.249818, 2.473548",\ + "0.031156, 0.303775, 0.637236, 1.249818, 2.473548",\ + "0.043792, 0.306003, 0.637272, 1.249893, 2.473548",\ + "0.055737, 0.309242, 0.637376, 1.250639, 2.473548",\ + "0.131941, 0.347209, 0.643620, 1.253596, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.069683, 0.173907, 0.285093, 0.488958, 0.896688",\ + "0.157089, 0.261225, 0.372374, 0.576263, 0.984041",\ + "0.237477, 0.341556, 0.452401, 0.656292, 1.064073",\ + "0.294246, 0.399105, 0.509943, 0.713536, 1.120720",\ + "0.588850, 0.702448, 0.813573, 1.016548, 1.422497"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026485, 0.188353, 0.387584, 0.758599, 1.500628",\ + "0.026485, 0.188353, 0.387584, 0.758599, 1.500628",\ + "0.027485, 0.188353, 0.387584, 0.758599, 1.500628",\ + "0.029472, 0.188961, 0.388043, 0.759501, 1.502419",\ + "0.047715, 0.193213, 0.388117, 0.760273, 1.504585"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[47]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026933, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213301, 0.167430, 0.137235, 0.125895, 0.139600",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026485, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266577, 0.191265, 0.123161, 0.100283, 0.164008",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[47]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026933, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141091, -0.098663, -0.064202, -0.024280, 0.287954",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026485, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174450, -0.108363, -0.050457, -0.008429, 0.211751",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[47]_hldr*/ + +} /* end of pin tl_o[47] */ + +pin("tl_o[46]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001816 ; + + /* Other user defined attributes. */ + original_pin : tl_o[46]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.249174, 2.482563",\ + "0.027983, 0.300023, 0.634430, 1.249174, 2.482563",\ + "0.041008, 0.302285, 0.634466, 1.249174, 2.482563",\ + "0.052904, 0.305573, 0.634567, 1.249174, 2.482563",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186982, 0.387454, 0.759758, 1.504368",\ + "0.024087, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.025192, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.027281, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.045983, 0.191111, 0.387958, 0.759758, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[46]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.247947, 2.473548",\ + "0.027983, 0.300023, 0.634430, 1.247947, 2.473548",\ + "0.041008, 0.302285, 0.634466, 1.248022, 2.473548",\ + "0.052904, 0.305573, 0.634567, 1.248766, 2.473548",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.025192, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.027281, 0.186796, 0.386404, 0.758430, 1.502482",\ + "0.045983, 0.191111, 0.386476, 0.759200, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[46]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211804, 0.165933, 0.135738, 0.124398, 0.138103",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265681, 0.190370, 0.122265, 0.099388, 0.163112",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[46]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139610, -0.097182, -0.062721, -0.022799, 0.289435",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173560, -0.107472, -0.049566, -0.007539, 0.212641",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[46]_hldr*/ + +} /* end of pin tl_o[46] */ + +pin("tl_o[45]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002729 ; + + /* Other user defined attributes. */ + original_pin : tl_o[45]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.050122, 0.202663, 0.377667, 0.700059, 1.344843",\ + "0.136545, 0.289838, 0.464771, 0.786773, 1.430777",\ + "0.220228, 0.377964, 0.552725, 0.874394, 1.517732",\ + "0.278624, 0.442356, 0.616840, 0.938307, 1.581241",\ + "0.581536, 0.792234, 0.967218, 1.287045, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.026704, 0.302529, 0.635118, 1.250933, 2.482563",\ + "0.030951, 0.303532, 0.637054, 1.250933, 2.482563",\ + "0.043612, 0.305763, 0.637091, 1.250933, 2.482563",\ + "0.055554, 0.309005, 0.637195, 1.250933, 2.482563",\ + "0.131711, 0.347003, 0.643440, 1.253476, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.069519, 0.173822, 0.285028, 0.488913, 0.896683",\ + "0.156925, 0.261140, 0.372309, 0.576218, 0.984036",\ + "0.237311, 0.341470, 0.452336, 0.656247, 1.064068",\ + "0.294074, 0.399020, 0.509878, 0.713491, 1.120715",\ + "0.588609, 0.702362, 0.813509, 1.016503, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.026316, 0.189006, 0.388975, 0.760749, 1.504296",\ + "0.026316, 0.189156, 0.389477, 0.760749, 1.504296",\ + "0.027323, 0.189156, 0.389477, 0.760749, 1.504296",\ + "0.029318, 0.189156, 0.389477, 0.760749, 1.504296",\ + "0.047593, 0.193065, 0.389477, 0.760749, 1.504576"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[45]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.050122, 0.202663, 0.377667, 0.700059, 1.344843",\ + "0.136545, 0.289838, 0.464771, 0.786773, 1.430777",\ + "0.220228, 0.377964, 0.552725, 0.874394, 1.517732",\ + "0.278624, 0.442356, 0.616840, 0.938307, 1.581241",\ + "0.581536, 0.792234, 0.967218, 1.287045, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.026704, 0.302529, 0.635118, 1.249697, 2.473548",\ + "0.030951, 0.303532, 0.637054, 1.249697, 2.473548",\ + "0.043612, 0.305763, 0.637091, 1.249772, 2.473548",\ + "0.055554, 0.309005, 0.637195, 1.250518, 2.473548",\ + "0.131711, 0.347003, 0.643440, 1.253476, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.069519, 0.173822, 0.285028, 0.488913, 0.896683",\ + "0.156925, 0.261140, 0.372309, 0.576218, 0.984036",\ + "0.237311, 0.341470, 0.452336, 0.656247, 1.064068",\ + "0.294074, 0.399020, 0.509878, 0.713491, 1.120715",\ + "0.588609, 0.702362, 0.813509, 1.016503, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.026316, 0.188200, 0.387466, 0.758517, 1.500619",\ + "0.026316, 0.188200, 0.387466, 0.758517, 1.500619",\ + "0.027323, 0.188200, 0.387466, 0.758517, 1.500619",\ + "0.029318, 0.188809, 0.387924, 0.759419, 1.502410",\ + "0.047593, 0.193065, 0.387998, 0.760191, 1.504576"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[45]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026704, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213204, 0.167333, 0.137138, 0.125798, 0.139503",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026316, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266513, 0.191202, 0.123098, 0.100220, 0.163945",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[45]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026704, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140996, -0.098567, -0.064106, -0.024184, 0.288050",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026316, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174387, -0.108300, -0.050394, -0.008366, 0.211814",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[45]_hldr*/ + +} /* end of pin tl_o[45] */ + +pin("tl_o[44]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002742 ; + + /* Other user defined attributes. */ + original_pin : tl_o[44]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.050158, 0.202690, 0.377687, 0.700072, 1.344843",\ + "0.136583, 0.289865, 0.464791, 0.786786, 1.430777",\ + "0.220274, 0.377991, 0.552745, 0.874407, 1.517732",\ + "0.278679, 0.442383, 0.616860, 0.938320, 1.581241",\ + "0.581645, 0.792261, 0.967238, 1.287058, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026752, 0.302579, 0.635156, 1.250959, 2.482563",\ + "0.030994, 0.303583, 0.637092, 1.250959, 2.482563",\ + "0.043650, 0.305813, 0.637129, 1.250959, 2.482563",\ + "0.055592, 0.309055, 0.637233, 1.250959, 2.482563",\ + "0.131760, 0.347046, 0.643478, 1.253501, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.069547, 0.173836, 0.285039, 0.488919, 0.896680",\ + "0.156953, 0.261154, 0.372320, 0.576224, 0.984034",\ + "0.237340, 0.341485, 0.452347, 0.656253, 1.064065",\ + "0.294104, 0.399034, 0.509889, 0.713497, 1.120713",\ + "0.588650, 0.702376, 0.813519, 1.016509, 1.422490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026345, 0.189032, 0.388994, 0.760760, 1.504292",\ + "0.026345, 0.189182, 0.389496, 0.760760, 1.504292",\ + "0.027351, 0.189182, 0.389496, 0.760760, 1.504292",\ + "0.029344, 0.189182, 0.389496, 0.760760, 1.504292",\ + "0.047614, 0.193091, 0.389496, 0.760760, 1.504572"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[44]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.050158, 0.202690, 0.377687, 0.700072, 1.344843",\ + "0.136583, 0.289865, 0.464791, 0.786786, 1.430777",\ + "0.220274, 0.377991, 0.552745, 0.874407, 1.517732",\ + "0.278679, 0.442383, 0.616860, 0.938320, 1.581241",\ + "0.581645, 0.792261, 0.967238, 1.287058, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026752, 0.302579, 0.635156, 1.249722, 2.473548",\ + "0.030994, 0.303583, 0.637092, 1.249722, 2.473548",\ + "0.043650, 0.305813, 0.637129, 1.249798, 2.473548",\ + "0.055592, 0.309055, 0.637233, 1.250543, 2.473548",\ + "0.131760, 0.347046, 0.643478, 1.253501, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.069547, 0.173836, 0.285039, 0.488919, 0.896680",\ + "0.156953, 0.261154, 0.372320, 0.576224, 0.984034",\ + "0.237340, 0.341485, 0.452347, 0.656253, 1.064065",\ + "0.294104, 0.399034, 0.509889, 0.713497, 1.120713",\ + "0.588650, 0.702376, 0.813519, 1.016509, 1.422490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026345, 0.188226, 0.387484, 0.758528, 1.500614",\ + "0.026345, 0.188226, 0.387484, 0.758528, 1.500614",\ + "0.027351, 0.188226, 0.387484, 0.758528, 1.500614",\ + "0.029344, 0.188835, 0.387943, 0.759431, 1.502406",\ + "0.047614, 0.193091, 0.388017, 0.760202, 1.504572"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[44]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026752, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213225, 0.167354, 0.137159, 0.125818, 0.139523",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026345, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266524, 0.191213, 0.123109, 0.100231, 0.163955",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[44]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026752, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141016, -0.098588, -0.064126, -0.024204, 0.288030",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026345, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174398, -0.108311, -0.050405, -0.008377, 0.211803",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[44]_hldr*/ + +} /* end of pin tl_o[44] */ + +pin("tl_o[43]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002272 ; + + /* Other user defined attributes. */ + original_pin : tl_o[43]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.048885, 0.201742, 0.376975, 0.699598, 1.344843",\ + "0.135240, 0.288916, 0.464080, 0.786312, 1.430777",\ + "0.218618, 0.377044, 0.552035, 0.873934, 1.517732",\ + "0.276707, 0.441437, 0.616150, 0.937847, 1.581241",\ + "0.577766, 0.791310, 0.966532, 1.286587, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025044, 0.300781, 0.633796, 1.250052, 2.482563",\ + "0.029464, 0.301774, 0.635740, 1.250052, 2.482563",\ + "0.042308, 0.304021, 0.635776, 1.250052, 2.482563",\ + "0.054226, 0.307286, 0.635878, 1.250052, 2.482563",\ + "0.130048, 0.345508, 0.642131, 1.252603, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.068436, 0.173254, 0.284610, 0.488640, 0.896702",\ + "0.155845, 0.260572, 0.371891, 0.575945, 0.984055",\ + "0.236214, 0.340905, 0.451917, 0.655974, 1.064087",\ + "0.292933, 0.398454, 0.509460, 0.713218, 1.120734",\ + "0.587016, 0.701794, 0.813092, 1.016232, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025198, 0.187991, 0.388212, 0.760251, 1.504330",\ + "0.025198, 0.188138, 0.388715, 0.760251, 1.504330",\ + "0.026254, 0.188138, 0.388715, 0.760251, 1.504330",\ + "0.028296, 0.188138, 0.388715, 0.760251, 1.504330",\ + "0.046785, 0.192085, 0.388715, 0.760251, 1.504610"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[43]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.048885, 0.201742, 0.376975, 0.699598, 1.344843",\ + "0.135240, 0.288916, 0.464080, 0.786312, 1.430777",\ + "0.218618, 0.377044, 0.552035, 0.873934, 1.517732",\ + "0.276707, 0.441437, 0.616150, 0.937847, 1.581241",\ + "0.577766, 0.791310, 0.966532, 1.286587, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025044, 0.300781, 0.633796, 1.248820, 2.473548",\ + "0.029464, 0.301774, 0.635740, 1.248820, 2.473548",\ + "0.042308, 0.304021, 0.635776, 1.248896, 2.473548",\ + "0.054226, 0.307286, 0.635878, 1.249640, 2.473548",\ + "0.130048, 0.345508, 0.642131, 1.252603, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.068436, 0.173254, 0.284610, 0.488640, 0.896702",\ + "0.155845, 0.260572, 0.371891, 0.575945, 0.984055",\ + "0.236214, 0.340905, 0.451917, 0.655974, 1.064087",\ + "0.292933, 0.398454, 0.509460, 0.713218, 1.120734",\ + "0.587016, 0.701794, 0.813092, 1.016232, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025198, 0.187189, 0.386704, 0.758020, 1.500653",\ + "0.025198, 0.187189, 0.386704, 0.758020, 1.500653",\ + "0.026254, 0.187189, 0.386704, 0.758020, 1.500653",\ + "0.028296, 0.187799, 0.387161, 0.758922, 1.502445",\ + "0.046785, 0.192085, 0.387234, 0.759693, 1.504610"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[43]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025044, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212503, 0.166632, 0.136437, 0.125097, 0.138801",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025198, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266096, 0.190785, 0.122680, 0.099803, 0.163527",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[43]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025044, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140302, -0.097874, -0.063412, -0.023490, 0.288744",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025198, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173972, -0.107885, -0.049979, -0.007951, 0.212229",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[43]_hldr*/ + +} /* end of pin tl_o[43] */ + +pin("tl_o[42]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002445 ; + + /* Other user defined attributes. */ + original_pin : tl_o[42]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\ + "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\ + "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\ + "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\ + "0.579196, 0.791661, 0.966792, 1.286761, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025674, 0.301444, 0.634297, 1.250386, 2.482563",\ + "0.030028, 0.302441, 0.636238, 1.250386, 2.482563",\ + "0.042803, 0.304681, 0.636274, 1.250386, 2.482563",\ + "0.054730, 0.307938, 0.636378, 1.250386, 2.482563",\ + "0.130679, 0.346075, 0.642627, 1.252934, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\ + "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\ + "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\ + "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\ + "0.587553, 0.701985, 0.813226, 1.016311, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025575, 0.188333, 0.388458, 0.760397, 1.504274",\ + "0.025575, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.026615, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.028641, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.047058, 0.192416, 0.388961, 0.760397, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[42]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\ + "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\ + "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\ + "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\ + "0.579196, 0.791661, 0.966792, 1.286761, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025674, 0.301444, 0.634297, 1.249153, 2.473548",\ + "0.030028, 0.302441, 0.636238, 1.249153, 2.473548",\ + "0.042803, 0.304681, 0.636274, 1.249228, 2.473548",\ + "0.054730, 0.307938, 0.636378, 1.249973, 2.473548",\ + "0.130679, 0.346075, 0.642627, 1.252934, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\ + "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\ + "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\ + "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\ + "0.587553, 0.701985, 0.813226, 1.016311, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.026615, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.028641, 0.188139, 0.387407, 0.759068, 1.502388",\ + "0.047058, 0.192416, 0.387481, 0.759838, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[42]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212769, 0.166898, 0.136703, 0.125363, 0.139067",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266237, 0.190925, 0.122821, 0.099943, 0.163668",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[42]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140565, -0.098137, -0.063675, -0.023754, 0.288480",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174112, -0.108025, -0.050119, -0.008091, 0.212089",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[42]_hldr*/ + +} /* end of pin tl_o[42] */ + +pin("tl_o[41]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002414 ; + + /* Other user defined attributes. */ + original_pin : tl_o[41]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\ + "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\ + "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\ + "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\ + "0.578938, 0.791597, 0.966745, 1.286729, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025560, 0.301324, 0.634207, 1.250326, 2.482563",\ + "0.029927, 0.302321, 0.636148, 1.250326, 2.482563",\ + "0.042713, 0.304562, 0.636184, 1.250326, 2.482563",\ + "0.054639, 0.307820, 0.636287, 1.250326, 2.482563",\ + "0.130565, 0.345973, 0.642537, 1.252874, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\ + "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\ + "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\ + "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\ + "0.587529, 0.701976, 0.813228, 1.016322, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025558, 0.188317, 0.388460, 0.760417, 1.504331",\ + "0.025558, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.026598, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.028625, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.047045, 0.192400, 0.388963, 0.760417, 1.504611"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[41]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\ + "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\ + "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\ + "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\ + "0.578938, 0.791597, 0.966745, 1.286729, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025560, 0.301324, 0.634207, 1.249093, 2.473548",\ + "0.029927, 0.302321, 0.636148, 1.249093, 2.473548",\ + "0.042713, 0.304562, 0.636184, 1.249168, 2.473548",\ + "0.054639, 0.307820, 0.636287, 1.249913, 2.473548",\ + "0.130565, 0.345973, 0.642537, 1.252874, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\ + "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\ + "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\ + "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\ + "0.587529, 0.701976, 0.813228, 1.016322, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.026598, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.028625, 0.188124, 0.387410, 0.759088, 1.502445",\ + "0.047045, 0.192400, 0.387483, 0.759859, 1.504611"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[41]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212721, 0.166850, 0.136655, 0.125315, 0.139019",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266230, 0.190919, 0.122815, 0.099937, 0.163661",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[41]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140517, -0.098089, -0.063628, -0.023706, 0.288528",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174106, -0.108018, -0.050112, -0.008085, 0.212095",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[41]_hldr*/ + +} /* end of pin tl_o[41] */ + +pin("tl_o[40]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001805 ; + + /* Other user defined attributes. */ + original_pin : tl_o[40]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\ + "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\ + "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\ + "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\ + "0.573921, 0.790368, 0.965832, 1.286120, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023351, 0.298998, 0.632448, 1.249153, 2.482563",\ + "0.027948, 0.299981, 0.634399, 1.249153, 2.482563",\ + "0.040978, 0.302244, 0.634435, 1.249153, 2.482563",\ + "0.052873, 0.305533, 0.634536, 1.249153, 2.482563",\ + "0.128351, 0.343984, 0.640795, 1.251713, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\ + "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\ + "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\ + "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\ + "0.585410, 0.701221, 0.812673, 1.015961, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.024071, 0.186967, 0.387445, 0.759756, 1.504378",\ + "0.024071, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.025176, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.027266, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.045971, 0.191097, 0.387949, 0.759756, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[40]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\ + "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\ + "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\ + "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\ + "0.573921, 0.790368, 0.965832, 1.286120, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023351, 0.298998, 0.632448, 1.247926, 2.473548",\ + "0.027948, 0.299981, 0.634399, 1.247926, 2.473548",\ + "0.040978, 0.302244, 0.634435, 1.248002, 2.473548",\ + "0.052873, 0.305533, 0.634536, 1.248745, 2.473548",\ + "0.128351, 0.343984, 0.640795, 1.251713, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\ + "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\ + "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\ + "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\ + "0.585410, 0.701221, 0.812673, 1.015961, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.025176, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.027266, 0.186781, 0.386395, 0.758427, 1.502492",\ + "0.045971, 0.191097, 0.386467, 0.759197, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[40]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211788, 0.165917, 0.135722, 0.124381, 0.138086",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265675, 0.190363, 0.122259, 0.099381, 0.163106",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[40]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139594, -0.097166, -0.062704, -0.022783, 0.289451",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173554, -0.107466, -0.049560, -0.007532, 0.212647",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[40]_hldr*/ + +} /* end of pin tl_o[40] */ + +pin("tl_o[39]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002265 ; + + /* Other user defined attributes. */ + original_pin : tl_o[39]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.048867, 0.201728, 0.376965, 0.699591, 1.344843",\ + "0.135221, 0.288903, 0.464069, 0.786305, 1.430777",\ + "0.218594, 0.377030, 0.552024, 0.873927, 1.517732",\ + "0.276679, 0.441423, 0.616140, 0.937840, 1.581241",\ + "0.577710, 0.791296, 0.966522, 1.286580, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025020, 0.300755, 0.633777, 1.250039, 2.482563",\ + "0.029442, 0.301748, 0.635720, 1.250039, 2.482563",\ + "0.042289, 0.303995, 0.635756, 1.250039, 2.482563",\ + "0.054207, 0.307260, 0.635859, 1.250039, 2.482563",\ + "0.130023, 0.345486, 0.642111, 1.252590, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.068420, 0.173246, 0.284604, 0.488637, 0.896702",\ + "0.155830, 0.260564, 0.371885, 0.575942, 0.984056",\ + "0.236199, 0.340897, 0.451912, 0.655970, 1.064088",\ + "0.292917, 0.398446, 0.509454, 0.713215, 1.120735",\ + "0.586994, 0.701786, 0.813086, 1.016228, 1.422512"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025182, 0.187976, 0.388201, 0.760245, 1.504332",\ + "0.025182, 0.188123, 0.388704, 0.760245, 1.504332",\ + "0.026239, 0.188123, 0.388704, 0.760245, 1.504332",\ + "0.028282, 0.188123, 0.388704, 0.760245, 1.504332",\ + "0.046774, 0.192071, 0.388704, 0.760245, 1.504612"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[39]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.048867, 0.201728, 0.376965, 0.699591, 1.344843",\ + "0.135221, 0.288903, 0.464069, 0.786305, 1.430777",\ + "0.218594, 0.377030, 0.552024, 0.873927, 1.517732",\ + "0.276679, 0.441423, 0.616140, 0.937840, 1.581241",\ + "0.577710, 0.791296, 0.966522, 1.286580, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025020, 0.300755, 0.633777, 1.248807, 2.473548",\ + "0.029442, 0.301748, 0.635720, 1.248807, 2.473548",\ + "0.042289, 0.303995, 0.635756, 1.248883, 2.473548",\ + "0.054207, 0.307260, 0.635859, 1.249627, 2.473548",\ + "0.130023, 0.345486, 0.642111, 1.252590, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.068420, 0.173246, 0.284604, 0.488637, 0.896702",\ + "0.155830, 0.260564, 0.371885, 0.575942, 0.984056",\ + "0.236199, 0.340897, 0.451912, 0.655970, 1.064088",\ + "0.292917, 0.398446, 0.509454, 0.713215, 1.120735",\ + "0.586994, 0.701786, 0.813086, 1.016228, 1.422512"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025182, 0.187175, 0.386693, 0.758014, 1.500654",\ + "0.025182, 0.187175, 0.386693, 0.758014, 1.500654",\ + "0.026239, 0.187175, 0.386693, 0.758014, 1.500654",\ + "0.028282, 0.187785, 0.387151, 0.758916, 1.502446",\ + "0.046774, 0.192071, 0.387224, 0.759686, 1.504612"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[39]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025020, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212492, 0.166621, 0.136427, 0.125086, 0.138791",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025182, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266090, 0.190779, 0.122675, 0.099797, 0.163521",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[39]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025020, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140291, -0.097863, -0.063402, -0.023480, 0.288754",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025182, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173966, -0.107879, -0.049973, -0.007945, 0.212235",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[39]_hldr*/ + +} /* end of pin tl_o[39] */ + +pin("tl_o[38]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002414 ; + + /* Other user defined attributes. */ + original_pin : tl_o[38]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\ + "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\ + "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\ + "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\ + "0.578938, 0.791597, 0.966745, 1.286729, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025560, 0.301324, 0.634207, 1.250326, 2.482563",\ + "0.029927, 0.302321, 0.636148, 1.250326, 2.482563",\ + "0.042713, 0.304562, 0.636184, 1.250326, 2.482563",\ + "0.054639, 0.307820, 0.636287, 1.250326, 2.482563",\ + "0.130565, 0.345973, 0.642537, 1.252874, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\ + "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\ + "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\ + "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\ + "0.587529, 0.701976, 0.813228, 1.016322, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025558, 0.188317, 0.388460, 0.760417, 1.504331",\ + "0.025558, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.026598, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.028625, 0.188465, 0.388963, 0.760417, 1.504331",\ + "0.047045, 0.192400, 0.388963, 0.760417, 1.504611"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[38]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049270, 0.202028, 0.377190, 0.699741, 1.344843",\ + "0.135646, 0.289203, 0.464294, 0.786455, 1.430777",\ + "0.219118, 0.377330, 0.552249, 0.874077, 1.517732",\ + "0.277303, 0.441723, 0.616364, 0.937990, 1.581241",\ + "0.578938, 0.791597, 0.966745, 1.286729, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025560, 0.301324, 0.634207, 1.249093, 2.473548",\ + "0.029927, 0.302321, 0.636148, 1.249093, 2.473548",\ + "0.042713, 0.304562, 0.636184, 1.249168, 2.473548",\ + "0.054639, 0.307820, 0.636287, 1.249913, 2.473548",\ + "0.130565, 0.345973, 0.642537, 1.252874, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.068784, 0.173437, 0.284746, 0.488731, 0.896702",\ + "0.156193, 0.260755, 0.372027, 0.576036, 0.984055",\ + "0.236567, 0.341087, 0.452054, 0.656065, 1.064087",\ + "0.293300, 0.398636, 0.509596, 0.713309, 1.120735",\ + "0.587529, 0.701976, 0.813228, 1.016322, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.025558, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.026598, 0.187514, 0.386952, 0.758186, 1.500654",\ + "0.028625, 0.188124, 0.387410, 0.759088, 1.502445",\ + "0.047045, 0.192400, 0.387483, 0.759859, 1.504611"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[38]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212721, 0.166850, 0.136655, 0.125315, 0.139019",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266230, 0.190919, 0.122815, 0.099937, 0.163661",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[38]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025560, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140517, -0.098089, -0.063628, -0.023706, 0.288528",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025558, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174106, -0.108018, -0.050112, -0.008085, 0.212095",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[38]_hldr*/ + +} /* end of pin tl_o[38] */ + +pin("tl_o[37]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002445 ; + + /* Other user defined attributes. */ + original_pin : tl_o[37]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\ + "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\ + "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\ + "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\ + "0.579196, 0.791661, 0.966792, 1.286761, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025674, 0.301444, 0.634297, 1.250386, 2.482563",\ + "0.030028, 0.302441, 0.636238, 1.250386, 2.482563",\ + "0.042803, 0.304681, 0.636274, 1.250386, 2.482563",\ + "0.054730, 0.307938, 0.636378, 1.250386, 2.482563",\ + "0.130679, 0.346075, 0.642627, 1.252934, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\ + "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\ + "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\ + "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\ + "0.587553, 0.701985, 0.813226, 1.016311, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025575, 0.188333, 0.388458, 0.760397, 1.504274",\ + "0.025575, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.026615, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.028641, 0.188481, 0.388961, 0.760397, 1.504274",\ + "0.047058, 0.192416, 0.388961, 0.760397, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[37]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.049354, 0.202091, 0.377237, 0.699773, 1.344843",\ + "0.135735, 0.289266, 0.464342, 0.786487, 1.430777",\ + "0.219229, 0.377393, 0.552297, 0.874108, 1.517732",\ + "0.277434, 0.441786, 0.616412, 0.938021, 1.581241",\ + "0.579196, 0.791661, 0.966792, 1.286761, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025674, 0.301444, 0.634297, 1.249153, 2.473548",\ + "0.030028, 0.302441, 0.636238, 1.249153, 2.473548",\ + "0.042803, 0.304681, 0.636274, 1.249228, 2.473548",\ + "0.054730, 0.307938, 0.636378, 1.249973, 2.473548",\ + "0.130679, 0.346075, 0.642627, 1.252934, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.068801, 0.173445, 0.284745, 0.488720, 0.896671",\ + "0.156209, 0.260764, 0.372026, 0.576025, 0.984024",\ + "0.236584, 0.341096, 0.452053, 0.656054, 1.064056",\ + "0.293318, 0.398645, 0.509595, 0.713298, 1.120704",\ + "0.587553, 0.701985, 0.813226, 1.016311, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.025575, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.026615, 0.187530, 0.386950, 0.758165, 1.500597",\ + "0.028641, 0.188139, 0.387407, 0.759068, 1.502388",\ + "0.047058, 0.192416, 0.387481, 0.759838, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[37]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212769, 0.166898, 0.136703, 0.125363, 0.139067",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266237, 0.190925, 0.122821, 0.099943, 0.163668",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[37]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025674, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140565, -0.098137, -0.063675, -0.023754, 0.288480",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174112, -0.108025, -0.050119, -0.008091, 0.212089",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[37]_hldr*/ + +} /* end of pin tl_o[37] */ + +pin("tl_o[36]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001816 ; + + /* Other user defined attributes. */ + original_pin : tl_o[36]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.249174, 2.482563",\ + "0.027983, 0.300023, 0.634430, 1.249174, 2.482563",\ + "0.041008, 0.302285, 0.634466, 1.249174, 2.482563",\ + "0.052904, 0.305573, 0.634567, 1.249174, 2.482563",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186982, 0.387454, 0.759758, 1.504368",\ + "0.024087, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.025192, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.027281, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.045983, 0.191111, 0.387958, 0.759758, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[36]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.247947, 2.473548",\ + "0.027983, 0.300023, 0.634430, 1.247947, 2.473548",\ + "0.041008, 0.302285, 0.634466, 1.248022, 2.473548",\ + "0.052904, 0.305573, 0.634567, 1.248766, 2.473548",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.025192, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.027281, 0.186796, 0.386404, 0.758430, 1.502482",\ + "0.045983, 0.191111, 0.386476, 0.759200, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[36]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211804, 0.165933, 0.135738, 0.124398, 0.138103",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265681, 0.190370, 0.122265, 0.099388, 0.163112",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[36]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139610, -0.097182, -0.062721, -0.022799, 0.289435",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173560, -0.107472, -0.049566, -0.007539, 0.212641",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[36]_hldr*/ + +} /* end of pin tl_o[36] */ + +pin("tl_o[35]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002254 ; + + /* Other user defined attributes. */ + original_pin : tl_o[35]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\ + "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\ + "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\ + "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\ + "0.577621, 0.791275, 0.966506, 1.286569, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.024980, 0.300714, 0.633745, 1.250018, 2.482564",\ + "0.029407, 0.301707, 0.635689, 1.250018, 2.482564",\ + "0.042258, 0.303954, 0.635725, 1.250018, 2.482564",\ + "0.054175, 0.307220, 0.635828, 1.250018, 2.482564",\ + "0.129984, 0.345451, 0.642080, 1.252569, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\ + "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\ + "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\ + "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\ + "0.586970, 0.701777, 0.813081, 1.016227, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.025166, 0.187961, 0.388192, 0.760242, 1.504342",\ + "0.025166, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.026223, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.028267, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.046762, 0.192057, 0.388695, 0.760242, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[35]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\ + "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\ + "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\ + "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\ + "0.577621, 0.791275, 0.966506, 1.286569, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.024980, 0.300714, 0.633745, 1.248787, 2.473548",\ + "0.029407, 0.301707, 0.635689, 1.248787, 2.473548",\ + "0.042258, 0.303954, 0.635725, 1.248862, 2.473548",\ + "0.054175, 0.307220, 0.635828, 1.249606, 2.473548",\ + "0.129984, 0.345451, 0.642080, 1.252569, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\ + "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\ + "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\ + "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\ + "0.586970, 0.701777, 0.813081, 1.016227, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.026223, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.028267, 0.187770, 0.387142, 0.758913, 1.502456",\ + "0.046762, 0.192057, 0.387215, 0.759684, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[35]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212476, 0.166605, 0.136410, 0.125070, 0.138775",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266084, 0.190773, 0.122668, 0.099790, 0.163515",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[35]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140275, -0.097847, -0.063386, -0.023464, 0.288770",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173960, -0.107873, -0.049967, -0.007939, 0.212241",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[35]_hldr*/ + +} /* end of pin tl_o[35] */ + +pin("tl_o[34]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001996 ; + + /* Other user defined attributes. */ + original_pin : tl_o[34]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.048141, 0.201187, 0.376558, 0.699320, 1.344843",\ + "0.134454, 0.288362, 0.463663, 0.786035, 1.430777",\ + "0.217649, 0.376489, 0.551619, 0.873657, 1.517732",\ + "0.275553, 0.440884, 0.615735, 0.937570, 1.581241",\ + "0.575495, 0.790754, 0.966118, 1.286311, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.024044, 0.299728, 0.633000, 1.249521, 2.482563",\ + "0.028569, 0.300716, 0.634948, 1.249521, 2.482563",\ + "0.041522, 0.302971, 0.634984, 1.249521, 2.482563",\ + "0.053427, 0.306251, 0.635086, 1.249521, 2.482563",\ + "0.129046, 0.344608, 0.641342, 1.252077, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.067740, 0.172889, 0.284335, 0.488454, 0.896691",\ + "0.155151, 0.260208, 0.371616, 0.575759, 0.984044",\ + "0.235509, 0.340542, 0.451643, 0.655787, 1.064076",\ + "0.292201, 0.398091, 0.509186, 0.713032, 1.120723",\ + "0.585993, 0.701429, 0.812818, 1.016046, 1.422500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.024480, 0.187339, 0.387711, 0.759911, 1.504310",\ + "0.024480, 0.187483, 0.388215, 0.759911, 1.504310",\ + "0.025567, 0.187483, 0.388215, 0.759911, 1.504310",\ + "0.027640, 0.187483, 0.388215, 0.759911, 1.504310",\ + "0.046267, 0.191456, 0.388215, 0.759911, 1.504590"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[34]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.048141, 0.201187, 0.376558, 0.699320, 1.344843",\ + "0.134454, 0.288362, 0.463663, 0.786035, 1.430777",\ + "0.217649, 0.376489, 0.551619, 0.873657, 1.517732",\ + "0.275553, 0.440884, 0.615735, 0.937570, 1.581241",\ + "0.575495, 0.790754, 0.966118, 1.286311, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.024044, 0.299728, 0.633000, 1.248292, 2.473548",\ + "0.028569, 0.300716, 0.634948, 1.248292, 2.473548",\ + "0.041522, 0.302971, 0.634984, 1.248368, 2.473548",\ + "0.053427, 0.306251, 0.635086, 1.249112, 2.473548",\ + "0.129046, 0.344608, 0.641342, 1.252077, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.067740, 0.172889, 0.284335, 0.488454, 0.896691",\ + "0.155151, 0.260208, 0.371616, 0.575759, 0.984044",\ + "0.235509, 0.340542, 0.451643, 0.655787, 1.064076",\ + "0.292201, 0.398091, 0.509186, 0.713032, 1.120723",\ + "0.585993, 0.701429, 0.812818, 1.016046, 1.422500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.024480, 0.186540, 0.386204, 0.757680, 1.500633",\ + "0.024480, 0.186540, 0.386204, 0.757680, 1.500633",\ + "0.025567, 0.186540, 0.386204, 0.757680, 1.500633",\ + "0.027640, 0.187150, 0.386661, 0.758582, 1.502424",\ + "0.046267, 0.191456, 0.386733, 0.759352, 1.504590"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[34]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024044, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212080, 0.166210, 0.136015, 0.124674, 0.138379",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024480, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265828, 0.190516, 0.122412, 0.099534, 0.163259",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[34]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024044, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139884, -0.097456, -0.062994, -0.023072, 0.289162",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024480, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173706, -0.107618, -0.049712, -0.007684, 0.212495",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[34]_hldr*/ + +} /* end of pin tl_o[34] */ + +pin("tl_o[33]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002863 ; + + /* Other user defined attributes. */ + original_pin : tl_o[33]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\ + "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\ + "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\ + "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\ + "0.582638, 0.792504, 0.967419, 1.287178, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027190, 0.303040, 0.635504, 1.251191, 2.482564",\ + "0.031386, 0.304046, 0.637439, 1.251191, 2.482564",\ + "0.043994, 0.306272, 0.637475, 1.251191, 2.482564",\ + "0.055941, 0.309507, 0.637579, 1.251191, 2.482564",\ + "0.132198, 0.347439, 0.643822, 1.253731, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\ + "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\ + "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\ + "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\ + "0.589089, 0.702533, 0.813636, 1.016588, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.026653, 0.189312, 0.389207, 0.760903, 1.504295",\ + "0.026653, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.027645, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.029626, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.047836, 0.193360, 0.389709, 0.760903, 1.504575"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[33]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\ + "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\ + "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\ + "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\ + "0.582638, 0.792504, 0.967419, 1.287178, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027190, 0.303040, 0.635504, 1.249953, 2.473548",\ + "0.031386, 0.304046, 0.637439, 1.249953, 2.473548",\ + "0.043994, 0.306272, 0.637475, 1.250028, 2.473548",\ + "0.055941, 0.309507, 0.637579, 1.250774, 2.473548",\ + "0.132198, 0.347439, 0.643822, 1.253731, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\ + "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\ + "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\ + "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\ + "0.589089, 0.702533, 0.813636, 1.016588, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.027645, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.029626, 0.189113, 0.388156, 0.759574, 1.502409",\ + "0.047836, 0.193360, 0.388231, 0.760346, 1.504575"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[33]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213409, 0.167538, 0.137343, 0.126003, 0.139708",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266639, 0.191328, 0.123224, 0.100346, 0.164070",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[33]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141198, -0.098770, -0.064309, -0.024387, 0.287847",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174512, -0.108425, -0.050519, -0.008491, 0.211689",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[33]_hldr*/ + +} /* end of pin tl_o[33] */ + +pin("tl_o[32]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003362 ; + + /* Other user defined attributes. */ + original_pin : tl_o[32]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\ + "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\ + "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\ + "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\ + "0.586756, 0.793514, 0.968169, 1.287678, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029003, 0.304950, 0.636948, 1.252153, 2.482563",\ + "0.033010, 0.305967, 0.638875, 1.252153, 2.482563",\ + "0.045419, 0.308176, 0.638911, 1.252153, 2.482563",\ + "0.057391, 0.311385, 0.639017, 1.252153, 2.482563",\ + "0.134015, 0.349072, 0.645253, 1.254684, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\ + "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\ + "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\ + "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\ + "0.590856, 0.703163, 0.814100, 1.016894, 1.422481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.027892, 0.190438, 0.390058, 0.761463, 1.504274",\ + "0.027892, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.028831, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.030758, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.048732, 0.194447, 0.390558, 0.761463, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[32]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\ + "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\ + "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\ + "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\ + "0.586756, 0.793514, 0.968169, 1.287678, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029003, 0.304950, 0.636948, 1.250910, 2.473548",\ + "0.033010, 0.305967, 0.638875, 1.250910, 2.473548",\ + "0.045419, 0.308176, 0.638911, 1.250986, 2.473548",\ + "0.057391, 0.311385, 0.639017, 1.251733, 2.473548",\ + "0.134015, 0.349072, 0.645253, 1.254684, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\ + "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\ + "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\ + "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\ + "0.590856, 0.703163, 0.814100, 1.016894, 1.422481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.028831, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.030758, 0.190232, 0.389006, 0.760134, 1.502388",\ + "0.048732, 0.194447, 0.389083, 0.760906, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[32]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.214175, 0.168305, 0.138110, 0.126769, 0.140474",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.267102, 0.191791, 0.123687, 0.100809, 0.164534",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[32]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141956, -0.099528, -0.065067, -0.025145, 0.287089",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174973, -0.108885, -0.050979, -0.008951, 0.211228",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[32]_hldr*/ + +} /* end of pin tl_o[32] */ + +pin("tl_o[31]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002343 ; + + /* Other user defined attributes. */ + original_pin : tl_o[31]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\ + "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\ + "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\ + "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\ + "0.578356, 0.791455, 0.966639, 1.286659, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025304, 0.301054, 0.634003, 1.250190, 2.482563",\ + "0.029697, 0.302049, 0.635945, 1.250190, 2.482563",\ + "0.042512, 0.304293, 0.635981, 1.250190, 2.482563",\ + "0.054434, 0.307555, 0.636084, 1.250190, 2.482563",\ + "0.130308, 0.345742, 0.642335, 1.252740, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\ + "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\ + "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\ + "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\ + "0.587289, 0.701891, 0.813166, 1.016283, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025390, 0.188165, 0.388347, 0.760345, 1.504341",\ + "0.025390, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.026437, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.028472, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.046924, 0.192253, 0.388850, 0.760345, 1.504621"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[31]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\ + "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\ + "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\ + "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\ + "0.578356, 0.791455, 0.966639, 1.286659, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025304, 0.301054, 0.634003, 1.248957, 2.473548",\ + "0.029697, 0.302049, 0.635945, 1.248957, 2.473548",\ + "0.042512, 0.304293, 0.635981, 1.249033, 2.473548",\ + "0.054434, 0.307555, 0.636084, 1.249777, 2.473548",\ + "0.130308, 0.345742, 0.642335, 1.252740, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\ + "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\ + "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\ + "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\ + "0.587289, 0.701891, 0.813166, 1.016283, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.026437, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.028472, 0.187972, 0.387296, 0.759016, 1.502455",\ + "0.046924, 0.192253, 0.387369, 0.759786, 1.504621"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[31]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212613, 0.166742, 0.136547, 0.125206, 0.138911",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266167, 0.190856, 0.122752, 0.099874, 0.163599",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[31]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140410, -0.097982, -0.063521, -0.023599, 0.288635",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174043, -0.107956, -0.050050, -0.008022, 0.212157",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[31]_hldr*/ + +} /* end of pin tl_o[31] */ + +pin("tl_o[30]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003362 ; + + /* Other user defined attributes. */ + original_pin : tl_o[30]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\ + "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\ + "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\ + "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\ + "0.586756, 0.793514, 0.968169, 1.287678, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029003, 0.304950, 0.636948, 1.252153, 2.482563",\ + "0.033010, 0.305967, 0.638875, 1.252153, 2.482563",\ + "0.045419, 0.308176, 0.638911, 1.252153, 2.482563",\ + "0.057391, 0.311385, 0.639017, 1.252153, 2.482563",\ + "0.134015, 0.349072, 0.645253, 1.254684, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\ + "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\ + "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\ + "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\ + "0.590856, 0.703163, 0.814100, 1.016894, 1.422481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.027892, 0.190438, 0.390058, 0.761463, 1.504274",\ + "0.027892, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.028831, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.030758, 0.190592, 0.390558, 0.761463, 1.504274",\ + "0.048732, 0.194447, 0.390558, 0.761463, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[30]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.051835, 0.203939, 0.378625, 0.700698, 1.344843",\ + "0.138352, 0.291114, 0.465728, 0.787411, 1.430777",\ + "0.222457, 0.379239, 0.553681, 0.875031, 1.517732",\ + "0.281277, 0.443628, 0.617795, 0.938944, 1.581241",\ + "0.586756, 0.793514, 0.968169, 1.287678, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029003, 0.304950, 0.636948, 1.250910, 2.473548",\ + "0.033010, 0.305967, 0.638875, 1.250910, 2.473548",\ + "0.045419, 0.308176, 0.638911, 1.250986, 2.473548",\ + "0.057391, 0.311385, 0.639017, 1.251733, 2.473548",\ + "0.134015, 0.349072, 0.645253, 1.254684, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.071047, 0.174622, 0.285622, 0.489305, 0.896671",\ + "0.158449, 0.261939, 0.372903, 0.576610, 0.984024",\ + "0.238859, 0.342267, 0.452930, 0.656639, 1.064056",\ + "0.295683, 0.399817, 0.510471, 0.713882, 1.120704",\ + "0.590856, 0.703163, 0.814100, 1.016894, 1.422481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.027892, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.028831, 0.189626, 0.388546, 0.759230, 1.500597",\ + "0.030758, 0.190232, 0.389006, 0.760134, 1.502388",\ + "0.048732, 0.194447, 0.389083, 0.760906, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[30]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.214175, 0.168305, 0.138110, 0.126769, 0.140474",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.267102, 0.191791, 0.123687, 0.100809, 0.164534",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[30]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029003, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141956, -0.099528, -0.065067, -0.025145, 0.287089",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027892, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174973, -0.108885, -0.050979, -0.008951, 0.211228",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[30]_hldr*/ + +} /* end of pin tl_o[30] */ + +pin("tl_o[29]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002863 ; + + /* Other user defined attributes. */ + original_pin : tl_o[29]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\ + "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\ + "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\ + "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\ + "0.582638, 0.792504, 0.967419, 1.287178, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027190, 0.303040, 0.635504, 1.251191, 2.482564",\ + "0.031386, 0.304046, 0.637439, 1.251191, 2.482564",\ + "0.043994, 0.306272, 0.637475, 1.251191, 2.482564",\ + "0.055941, 0.309507, 0.637579, 1.251191, 2.482564",\ + "0.132198, 0.347439, 0.643822, 1.253731, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\ + "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\ + "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\ + "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\ + "0.589089, 0.702533, 0.813636, 1.016588, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.026653, 0.189312, 0.389207, 0.760903, 1.504295",\ + "0.026653, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.027645, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.029626, 0.189463, 0.389709, 0.760903, 1.504295",\ + "0.047836, 0.193360, 0.389709, 0.760903, 1.504575"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[29]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.050484, 0.202933, 0.377869, 0.700194, 1.344843",\ + "0.136927, 0.290107, 0.464973, 0.786907, 1.430777",\ + "0.220698, 0.378233, 0.552927, 0.874529, 1.517732",\ + "0.279184, 0.442625, 0.617042, 0.938441, 1.581241",\ + "0.582638, 0.792504, 0.967419, 1.287178, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027190, 0.303040, 0.635504, 1.249953, 2.473548",\ + "0.031386, 0.304046, 0.637439, 1.249953, 2.473548",\ + "0.043994, 0.306272, 0.637475, 1.250028, 2.473548",\ + "0.055941, 0.309507, 0.637579, 1.250774, 2.473548",\ + "0.132198, 0.347439, 0.643822, 1.253731, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.069846, 0.173993, 0.285156, 0.488998, 0.896682",\ + "0.157251, 0.261310, 0.372437, 0.576303, 0.984036",\ + "0.237642, 0.341641, 0.452464, 0.656332, 1.064067",\ + "0.294418, 0.399190, 0.510006, 0.713575, 1.120715",\ + "0.589089, 0.702533, 0.813636, 1.016588, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.026653, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.027645, 0.188505, 0.387697, 0.758671, 1.500618",\ + "0.029626, 0.189113, 0.388156, 0.759574, 1.502409",\ + "0.047836, 0.193360, 0.388231, 0.760346, 1.504575"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[29]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213409, 0.167538, 0.137343, 0.126003, 0.139708",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266639, 0.191328, 0.123224, 0.100346, 0.164070",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[29]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027190, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141198, -0.098770, -0.064309, -0.024387, 0.287847",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026653, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174512, -0.108425, -0.050519, -0.008491, 0.211689",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[29]_hldr*/ + +} /* end of pin tl_o[29] */ + +pin("tl_o[28]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001816 ; + + /* Other user defined attributes. */ + original_pin : tl_o[28]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.249174, 2.482563",\ + "0.027983, 0.300023, 0.634430, 1.249174, 2.482563",\ + "0.041008, 0.302285, 0.634466, 1.249174, 2.482563",\ + "0.052904, 0.305573, 0.634567, 1.249174, 2.482563",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186982, 0.387454, 0.759758, 1.504368",\ + "0.024087, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.025192, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.027281, 0.187126, 0.387958, 0.759758, 1.504368",\ + "0.045983, 0.191111, 0.387958, 0.759758, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[28]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.047653, 0.200824, 0.376286, 0.699138, 1.344843",\ + "0.133940, 0.287998, 0.463391, 0.785853, 1.430777",\ + "0.217014, 0.376126, 0.551347, 0.873475, 1.517732",\ + "0.274798, 0.440522, 0.615463, 0.937389, 1.581241",\ + "0.574010, 0.790389, 0.965848, 1.286131, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.023390, 0.299039, 0.632479, 1.247947, 2.473548",\ + "0.027983, 0.300023, 0.634430, 1.247947, 2.473548",\ + "0.041008, 0.302285, 0.634466, 1.248022, 2.473548",\ + "0.052904, 0.305573, 0.634567, 1.248766, 2.473548",\ + "0.128390, 0.344019, 0.640826, 1.251733, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.067359, 0.172690, 0.284194, 0.488370, 0.896722",\ + "0.154772, 0.260009, 0.371475, 0.575675, 0.984076",\ + "0.235124, 0.340344, 0.451502, 0.655704, 1.064107",\ + "0.291800, 0.397892, 0.509045, 0.712948, 1.120755",\ + "0.585433, 0.701229, 0.812678, 1.015963, 1.422532"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.024087, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.025192, 0.186184, 0.385947, 0.757528, 1.500690",\ + "0.027281, 0.186796, 0.386404, 0.758430, 1.502482",\ + "0.045983, 0.191111, 0.386476, 0.759200, 1.504648"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[28]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211804, 0.165933, 0.135738, 0.124398, 0.138103",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265681, 0.190370, 0.122265, 0.099388, 0.163112",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[28]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139610, -0.097182, -0.062721, -0.022799, 0.289435",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024087, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173560, -0.107472, -0.049566, -0.007539, 0.212641",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[28]_hldr*/ + +} /* end of pin tl_o[28] */ + +pin("tl_o[27]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003525 ; + + /* Other user defined attributes. */ + original_pin : tl_o[27]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.052275, 0.204267, 0.378871, 0.700862, 1.344843",\ + "0.138817, 0.291442, 0.465974, 0.787575, 1.430777",\ + "0.223030, 0.379567, 0.553927, 0.875195, 1.517732",\ + "0.281960, 0.443955, 0.618041, 0.939108, 1.581241",\ + "0.588098, 0.793843, 0.968413, 1.287841, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.029595, 0.305572, 0.637418, 1.252467, 2.482563",\ + "0.033540, 0.306593, 0.639343, 1.252467, 2.482563",\ + "0.045883, 0.308796, 0.639379, 1.252467, 2.482563",\ + "0.057864, 0.311997, 0.639486, 1.252467, 2.482563",\ + "0.134607, 0.349604, 0.645719, 1.254995, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.071419, 0.174817, 0.285764, 0.489395, 0.896657",\ + "0.158819, 0.262134, 0.373045, 0.576700, 0.984010",\ + "0.239235, 0.342461, 0.453072, 0.656729, 1.064042",\ + "0.296074, 0.400011, 0.510613, 0.713972, 1.120690",\ + "0.591402, 0.703358, 0.814241, 1.016983, 1.422467"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.028276, 0.190786, 0.390316, 0.761627, 1.504248",\ + "0.028276, 0.190941, 0.390816, 0.761627, 1.504248",\ + "0.029198, 0.190941, 0.390816, 0.761627, 1.504248",\ + "0.031109, 0.190941, 0.390816, 0.761627, 1.504248",\ + "0.049009, 0.194783, 0.390816, 0.761627, 1.504528"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[27]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.052275, 0.204267, 0.378871, 0.700862, 1.344843",\ + "0.138817, 0.291442, 0.465974, 0.787575, 1.430777",\ + "0.223030, 0.379567, 0.553927, 0.875195, 1.517732",\ + "0.281960, 0.443955, 0.618041, 0.939108, 1.581241",\ + "0.588098, 0.793843, 0.968413, 1.287841, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.029595, 0.305572, 0.637418, 1.251222, 2.473548",\ + "0.033540, 0.306593, 0.639343, 1.251222, 2.473548",\ + "0.045883, 0.308796, 0.639379, 1.251298, 2.473548",\ + "0.057864, 0.311997, 0.639486, 1.252045, 2.473548",\ + "0.134607, 0.349604, 0.645719, 1.254995, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.071419, 0.174817, 0.285764, 0.489395, 0.896657",\ + "0.158819, 0.262134, 0.373045, 0.576700, 0.984010",\ + "0.239235, 0.342461, 0.453072, 0.656729, 1.064042",\ + "0.296074, 0.400011, 0.510613, 0.713972, 1.120690",\ + "0.591402, 0.703358, 0.814241, 1.016983, 1.422467"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.028276, 0.189973, 0.388804, 0.759393, 1.500571",\ + "0.028276, 0.189973, 0.388804, 0.759393, 1.500571",\ + "0.029198, 0.189973, 0.388804, 0.759393, 1.500571",\ + "0.031109, 0.190579, 0.389264, 0.760297, 1.502363",\ + "0.049009, 0.194783, 0.389341, 0.761070, 1.504528"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[27]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029595, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.214425, 0.168554, 0.138359, 0.127019, 0.140724",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028276, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.267246, 0.191934, 0.123830, 0.100952, 0.164677",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[27]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029595, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.142204, -0.099775, -0.065314, -0.025392, 0.286842",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028276, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.175115, -0.109028, -0.051122, -0.009094, 0.211086",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[27]_hldr*/ + +} /* end of pin tl_o[27] */ + +pin("tl_o[26]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002267 ; + + /* Other user defined attributes. */ + original_pin : tl_o[26]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.048874, 0.201733, 0.376968, 0.699593, 1.344843",\ + "0.135228, 0.288908, 0.464073, 0.786308, 1.430777",\ + "0.218603, 0.377035, 0.552028, 0.873930, 1.517732",\ + "0.276689, 0.441428, 0.616144, 0.937843, 1.581241",\ + "0.577730, 0.791301, 0.966525, 1.286583, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025028, 0.300764, 0.633784, 1.250043, 2.482563",\ + "0.029450, 0.301758, 0.635727, 1.250043, 2.482563",\ + "0.042296, 0.304004, 0.635763, 1.250043, 2.482563",\ + "0.054214, 0.307269, 0.635866, 1.250043, 2.482563",\ + "0.130032, 0.345494, 0.642118, 1.252595, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.068432, 0.173252, 0.284609, 0.488641, 0.896705",\ + "0.155842, 0.260570, 0.371890, 0.575946, 0.984059",\ + "0.236211, 0.340904, 0.451917, 0.655975, 1.064090",\ + "0.292930, 0.398452, 0.509460, 0.713219, 1.120738",\ + "0.587011, 0.701792, 0.813092, 1.016233, 1.422515"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025195, 0.187988, 0.388211, 0.760253, 1.504337",\ + "0.025195, 0.188134, 0.388714, 0.760253, 1.504337",\ + "0.026251, 0.188134, 0.388714, 0.760253, 1.504337",\ + "0.028293, 0.188134, 0.388714, 0.760253, 1.504337",\ + "0.046783, 0.192082, 0.388714, 0.760253, 1.504617"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[26]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.048874, 0.201733, 0.376968, 0.699593, 1.344843",\ + "0.135228, 0.288908, 0.464073, 0.786308, 1.430777",\ + "0.218603, 0.377035, 0.552028, 0.873930, 1.517732",\ + "0.276689, 0.441428, 0.616144, 0.937843, 1.581241",\ + "0.577730, 0.791301, 0.966525, 1.286583, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025028, 0.300764, 0.633784, 1.248812, 2.473548",\ + "0.029450, 0.301758, 0.635727, 1.248812, 2.473548",\ + "0.042296, 0.304004, 0.635763, 1.248887, 2.473548",\ + "0.054214, 0.307269, 0.635866, 1.249632, 2.473548",\ + "0.130032, 0.345494, 0.642118, 1.252595, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.068432, 0.173252, 0.284609, 0.488641, 0.896705",\ + "0.155842, 0.260570, 0.371890, 0.575946, 0.984059",\ + "0.236211, 0.340904, 0.451917, 0.655975, 1.064090",\ + "0.292930, 0.398452, 0.509460, 0.713219, 1.120738",\ + "0.587011, 0.701792, 0.813092, 1.016233, 1.422515"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025195, 0.187186, 0.386703, 0.758022, 1.500660",\ + "0.025195, 0.187186, 0.386703, 0.758022, 1.500660",\ + "0.026251, 0.187186, 0.386703, 0.758022, 1.500660",\ + "0.028293, 0.187796, 0.387161, 0.758924, 1.502451",\ + "0.046783, 0.192082, 0.387233, 0.759695, 1.504617"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[26]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025028, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212496, 0.166625, 0.136430, 0.125090, 0.138795",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025195, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266095, 0.190783, 0.122679, 0.099801, 0.163526",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[26]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025028, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140295, -0.097867, -0.063406, -0.023484, 0.288750",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025195, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173971, -0.107884, -0.049978, -0.007950, 0.212230",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[26]_hldr*/ + +} /* end of pin tl_o[26] */ + +pin("tl_o[25]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002846 ; + + /* Other user defined attributes. */ + original_pin : tl_o[25]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.050438, 0.202899, 0.377843, 0.700177, 1.344843",\ + "0.136878, 0.290073, 0.464947, 0.786890, 1.430777",\ + "0.220639, 0.378199, 0.552901, 0.874512, 1.517732",\ + "0.279113, 0.442591, 0.617016, 0.938424, 1.581241",\ + "0.582498, 0.792470, 0.967394, 1.287161, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.027128, 0.302975, 0.635455, 1.251158, 2.482563",\ + "0.031331, 0.303981, 0.637390, 1.251158, 2.482563",\ + "0.043946, 0.306208, 0.637426, 1.251158, 2.482563",\ + "0.055892, 0.309444, 0.637531, 1.251158, 2.482563",\ + "0.132136, 0.347384, 0.643774, 1.253699, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.069801, 0.173969, 0.285138, 0.488985, 0.896680",\ + "0.157206, 0.261287, 0.372419, 0.576290, 0.984034",\ + "0.237596, 0.341617, 0.452445, 0.656319, 1.064065",\ + "0.294370, 0.399166, 0.509987, 0.713563, 1.120713",\ + "0.589023, 0.702509, 0.813617, 1.016575, 1.422490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.026606, 0.189270, 0.389174, 0.760880, 1.504292",\ + "0.026606, 0.189420, 0.389676, 0.760880, 1.504292",\ + "0.027601, 0.189420, 0.389676, 0.760880, 1.504292",\ + "0.029583, 0.189420, 0.389676, 0.760880, 1.504292",\ + "0.047803, 0.193320, 0.389676, 0.760880, 1.504571"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[25]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.050438, 0.202899, 0.377843, 0.700177, 1.344843",\ + "0.136878, 0.290073, 0.464947, 0.786890, 1.430777",\ + "0.220639, 0.378199, 0.552901, 0.874512, 1.517732",\ + "0.279113, 0.442591, 0.617016, 0.938424, 1.581241",\ + "0.582498, 0.792470, 0.967394, 1.287161, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.027128, 0.302975, 0.635455, 1.249921, 2.473548",\ + "0.031331, 0.303981, 0.637390, 1.249921, 2.473548",\ + "0.043946, 0.306208, 0.637426, 1.249996, 2.473548",\ + "0.055892, 0.309444, 0.637531, 1.250742, 2.473548",\ + "0.132136, 0.347384, 0.643774, 1.253699, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.069801, 0.173969, 0.285138, 0.488985, 0.896680",\ + "0.157206, 0.261287, 0.372419, 0.576290, 0.984034",\ + "0.237596, 0.341617, 0.452445, 0.656319, 1.064065",\ + "0.294370, 0.399166, 0.509987, 0.713563, 1.120713",\ + "0.589023, 0.702509, 0.813617, 1.016575, 1.422490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.026606, 0.188463, 0.387664, 0.758648, 1.500614",\ + "0.026606, 0.188463, 0.387664, 0.758648, 1.500614",\ + "0.027601, 0.188463, 0.387664, 0.758648, 1.500614",\ + "0.029583, 0.189071, 0.388123, 0.759551, 1.502406",\ + "0.047803, 0.193320, 0.388198, 0.760322, 1.504571"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[25]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027128, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213383, 0.167512, 0.137317, 0.125977, 0.139682",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266622, 0.191311, 0.123207, 0.100329, 0.164053",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[25]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027128, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141173, -0.098745, -0.064283, -0.024362, 0.287872",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174495, -0.108408, -0.050502, -0.008474, 0.211706",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[25]_hldr*/ + +} /* end of pin tl_o[25] */ + +pin("tl_o[24]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003210 ; + + /* Other user defined attributes. */ + original_pin : tl_o[24]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.051424, 0.203633, 0.378395, 0.700544, 1.344843",\ + "0.137919, 0.290808, 0.465498, 0.787258, 1.430777",\ + "0.221922, 0.378933, 0.553452, 0.874879, 1.517732",\ + "0.280641, 0.443323, 0.617566, 0.938791, 1.581241",\ + "0.585504, 0.793207, 0.967941, 1.287526, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.028452, 0.304369, 0.636509, 1.251860, 2.482563",\ + "0.032517, 0.305383, 0.638438, 1.251860, 2.482563",\ + "0.044986, 0.307597, 0.638475, 1.251860, 2.482563",\ + "0.056951, 0.310815, 0.638580, 1.251860, 2.482563",\ + "0.133463, 0.348576, 0.644818, 1.254395, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.070659, 0.174419, 0.285469, 0.489200, 0.896663",\ + "0.158062, 0.261736, 0.372750, 0.576505, 0.984016",\ + "0.238466, 0.342065, 0.452777, 0.656534, 1.064048",\ + "0.295275, 0.399615, 0.510318, 0.713777, 1.120695",\ + "0.590286, 0.702959, 0.813947, 1.016789, 1.422472"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.027492, 0.190075, 0.389778, 0.761272, 1.504259",\ + "0.027492, 0.190228, 0.390279, 0.761272, 1.504259",\ + "0.028448, 0.190228, 0.390279, 0.761272, 1.504259",\ + "0.030393, 0.190228, 0.390279, 0.761272, 1.504259",\ + "0.048443, 0.194096, 0.390279, 0.761272, 1.504539"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[24]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.051424, 0.203633, 0.378395, 0.700544, 1.344843",\ + "0.137919, 0.290808, 0.465498, 0.787258, 1.430777",\ + "0.221922, 0.378933, 0.553452, 0.874879, 1.517732",\ + "0.280641, 0.443323, 0.617566, 0.938791, 1.581241",\ + "0.585504, 0.793207, 0.967941, 1.287526, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.028452, 0.304369, 0.636509, 1.250620, 2.473548",\ + "0.032517, 0.305383, 0.638438, 1.250620, 2.473548",\ + "0.044986, 0.307597, 0.638475, 1.250695, 2.473548",\ + "0.056951, 0.310815, 0.638580, 1.251441, 2.473548",\ + "0.133463, 0.348576, 0.644818, 1.254395, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.070659, 0.174419, 0.285469, 0.489200, 0.896663",\ + "0.158062, 0.261736, 0.372750, 0.576505, 0.984016",\ + "0.238466, 0.342065, 0.452777, 0.656534, 1.064048",\ + "0.295275, 0.399615, 0.510318, 0.713777, 1.120695",\ + "0.590286, 0.702959, 0.813947, 1.016789, 1.422472"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.027492, 0.189265, 0.388267, 0.759039, 1.500582",\ + "0.027492, 0.189265, 0.388267, 0.759039, 1.500582",\ + "0.028448, 0.189265, 0.388267, 0.759039, 1.500582",\ + "0.030393, 0.189871, 0.388727, 0.759942, 1.502373",\ + "0.048443, 0.194096, 0.388802, 0.760715, 1.504539"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[24]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213943, 0.168072, 0.137877, 0.126536, 0.140241",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027492, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266953, 0.191642, 0.123538, 0.100660, 0.164384",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[24]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141726, -0.099298, -0.064837, -0.024915, 0.287319",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027492, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174824, -0.108737, -0.050831, -0.008803, 0.211377",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[24]_hldr*/ + +} /* end of pin tl_o[24] */ + +pin("tl_o[23]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002308 ; + + /* Other user defined attributes. */ + original_pin : tl_o[23]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.048983, 0.201815, 0.377030, 0.699634, 1.344843",\ + "0.135344, 0.288990, 0.464134, 0.786349, 1.430777",\ + "0.218746, 0.377117, 0.552089, 0.873970, 1.517732",\ + "0.276859, 0.441510, 0.616205, 0.937884, 1.581241",\ + "0.578065, 0.791383, 0.966586, 1.286623, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.025176, 0.300919, 0.633901, 1.250122, 2.482564",\ + "0.029582, 0.301914, 0.635844, 1.250122, 2.482564",\ + "0.042411, 0.304159, 0.635880, 1.250122, 2.482564",\ + "0.054332, 0.307422, 0.635983, 1.250122, 2.482564",\ + "0.130180, 0.345627, 0.642234, 1.252672, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.068536, 0.173307, 0.284651, 0.488670, 0.896708",\ + "0.155945, 0.260625, 0.371931, 0.575975, 0.984061",\ + "0.236316, 0.340958, 0.451958, 0.656003, 1.064093",\ + "0.293039, 0.398507, 0.509501, 0.713248, 1.120741",\ + "0.587164, 0.701846, 0.813133, 1.016261, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.025302, 0.188085, 0.388286, 0.760305, 1.504342",\ + "0.025302, 0.188232, 0.388789, 0.760305, 1.504342",\ + "0.026353, 0.188232, 0.388789, 0.760305, 1.504342",\ + "0.028391, 0.188232, 0.388789, 0.760305, 1.504342",\ + "0.046861, 0.192176, 0.388789, 0.760305, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[23]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.048983, 0.201815, 0.377030, 0.699634, 1.344843",\ + "0.135344, 0.288990, 0.464134, 0.786349, 1.430777",\ + "0.218746, 0.377117, 0.552089, 0.873970, 1.517732",\ + "0.276859, 0.441510, 0.616205, 0.937884, 1.581241",\ + "0.578065, 0.791383, 0.966586, 1.286623, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.025176, 0.300919, 0.633901, 1.248890, 2.473548",\ + "0.029582, 0.301914, 0.635844, 1.248890, 2.473548",\ + "0.042411, 0.304159, 0.635880, 1.248965, 2.473548",\ + "0.054332, 0.307422, 0.635983, 1.249710, 2.473548",\ + "0.130180, 0.345627, 0.642234, 1.252672, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.068536, 0.173307, 0.284651, 0.488670, 0.896708",\ + "0.155945, 0.260625, 0.371931, 0.575975, 0.984061",\ + "0.236316, 0.340958, 0.451958, 0.656003, 1.064093",\ + "0.293039, 0.398507, 0.509501, 0.713248, 1.120741",\ + "0.587164, 0.701846, 0.813133, 1.016261, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.025302, 0.187283, 0.386778, 0.758074, 1.500664",\ + "0.025302, 0.187283, 0.386778, 0.758074, 1.500664",\ + "0.026353, 0.187283, 0.386778, 0.758074, 1.500664",\ + "0.028391, 0.187893, 0.387236, 0.758976, 1.502456",\ + "0.046861, 0.192176, 0.387309, 0.759746, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[23]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025176, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212558, 0.166688, 0.136493, 0.125152, 0.138857",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025302, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266135, 0.190823, 0.122719, 0.099841, 0.163566",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[23]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025176, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140357, -0.097929, -0.063467, -0.023545, 0.288689",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025302, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174011, -0.107923, -0.050017, -0.007990, 0.212190",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[23]_hldr*/ + +} /* end of pin tl_o[23] */ + +pin("tl_o[22]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002254 ; + + /* Other user defined attributes. */ + original_pin : tl_o[22]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\ + "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\ + "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\ + "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\ + "0.577621, 0.791275, 0.966506, 1.286569, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.024980, 0.300714, 0.633745, 1.250018, 2.482564",\ + "0.029407, 0.301707, 0.635689, 1.250018, 2.482564",\ + "0.042258, 0.303954, 0.635725, 1.250018, 2.482564",\ + "0.054175, 0.307220, 0.635828, 1.250018, 2.482564",\ + "0.129984, 0.345451, 0.642080, 1.252569, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\ + "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\ + "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\ + "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\ + "0.586970, 0.701777, 0.813081, 1.016227, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.025166, 0.187961, 0.388192, 0.760242, 1.504342",\ + "0.025166, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.026223, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.028267, 0.188108, 0.388695, 0.760242, 1.504342",\ + "0.046762, 0.192057, 0.388695, 0.760242, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[22]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048838, 0.201706, 0.376948, 0.699580, 1.344843",\ + "0.135190, 0.288881, 0.464053, 0.786294, 1.430777",\ + "0.218556, 0.377008, 0.552008, 0.873916, 1.517732",\ + "0.276634, 0.441402, 0.616124, 0.937829, 1.581241",\ + "0.577621, 0.791275, 0.966506, 1.286569, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.024980, 0.300714, 0.633745, 1.248787, 2.473548",\ + "0.029407, 0.301707, 0.635689, 1.248787, 2.473548",\ + "0.042258, 0.303954, 0.635725, 1.248862, 2.473548",\ + "0.054175, 0.307220, 0.635828, 1.249606, 2.473548",\ + "0.129984, 0.345451, 0.642080, 1.252569, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.068404, 0.173238, 0.284599, 0.488635, 0.896708",\ + "0.155814, 0.260556, 0.371880, 0.575940, 0.984061",\ + "0.236182, 0.340889, 0.451907, 0.655969, 1.064093",\ + "0.292900, 0.398438, 0.509450, 0.713213, 1.120741",\ + "0.586970, 0.701777, 0.813081, 1.016227, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.025166, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.026223, 0.187160, 0.386684, 0.758011, 1.500664",\ + "0.028267, 0.187770, 0.387142, 0.758913, 1.502456",\ + "0.046762, 0.192057, 0.387215, 0.759684, 1.504622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[22]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212476, 0.166605, 0.136410, 0.125070, 0.138775",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266084, 0.190773, 0.122668, 0.099790, 0.163515",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[22]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024980, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140275, -0.097847, -0.063386, -0.023464, 0.288770",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025166, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173960, -0.107873, -0.049967, -0.007939, 0.212241",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[22]_hldr*/ + +} /* end of pin tl_o[22] */ + +pin("tl_o[21]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003224 ; + + /* Other user defined attributes. */ + original_pin : tl_o[21]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.051460, 0.203660, 0.378415, 0.700558, 1.344843",\ + "0.137957, 0.290835, 0.465518, 0.787271, 1.430777",\ + "0.221969, 0.378960, 0.553472, 0.874892, 1.517732",\ + "0.280696, 0.443350, 0.617586, 0.938804, 1.581241",\ + "0.585613, 0.793234, 0.967961, 1.287539, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.028500, 0.304420, 0.636547, 1.251886, 2.482563",\ + "0.032560, 0.305434, 0.638476, 1.251886, 2.482563",\ + "0.045023, 0.307647, 0.638513, 1.251886, 2.482563",\ + "0.056989, 0.310864, 0.638618, 1.251886, 2.482563",\ + "0.133511, 0.348619, 0.644856, 1.254420, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.070687, 0.174433, 0.285479, 0.489206, 0.896660",\ + "0.158090, 0.261751, 0.372760, 0.576511, 0.984014",\ + "0.238494, 0.342080, 0.452787, 0.656540, 1.064045",\ + "0.295304, 0.399629, 0.510328, 0.713783, 1.120693",\ + "0.590327, 0.702974, 0.813957, 1.016795, 1.422470"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.027521, 0.190101, 0.389797, 0.761283, 1.504255",\ + "0.027521, 0.190254, 0.390298, 0.761283, 1.504255",\ + "0.028476, 0.190254, 0.390298, 0.761283, 1.504255",\ + "0.030419, 0.190254, 0.390298, 0.761283, 1.504255",\ + "0.048464, 0.194122, 0.390298, 0.761283, 1.504535"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[21]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.051460, 0.203660, 0.378415, 0.700558, 1.344843",\ + "0.137957, 0.290835, 0.465518, 0.787271, 1.430777",\ + "0.221969, 0.378960, 0.553472, 0.874892, 1.517732",\ + "0.280696, 0.443350, 0.617586, 0.938804, 1.581241",\ + "0.585613, 0.793234, 0.967961, 1.287539, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.028500, 0.304420, 0.636547, 1.250645, 2.473547",\ + "0.032560, 0.305434, 0.638476, 1.250645, 2.473547",\ + "0.045023, 0.307647, 0.638513, 1.250720, 2.473547",\ + "0.056989, 0.310864, 0.638618, 1.251467, 2.473547",\ + "0.133511, 0.348619, 0.644856, 1.254420, 2.473547"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.070687, 0.174433, 0.285479, 0.489206, 0.896660",\ + "0.158090, 0.261751, 0.372760, 0.576511, 0.984014",\ + "0.238494, 0.342080, 0.452787, 0.656540, 1.064045",\ + "0.295304, 0.399629, 0.510328, 0.713783, 1.120693",\ + "0.590327, 0.702974, 0.813957, 1.016795, 1.422470"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.027521, 0.189291, 0.388286, 0.759050, 1.500578",\ + "0.027521, 0.189291, 0.388286, 0.759050, 1.500578",\ + "0.028476, 0.189291, 0.388286, 0.759050, 1.500578",\ + "0.030419, 0.189897, 0.388745, 0.759953, 1.502369",\ + "0.048464, 0.194122, 0.388821, 0.760726, 1.504535"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[21]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028500, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.213963, 0.168092, 0.137897, 0.126557, 0.140261",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027521, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266964, 0.191653, 0.123548, 0.100670, 0.164395",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[21]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028500, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.141746, -0.099318, -0.064857, -0.024935, 0.287299",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027521, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174835, -0.108748, -0.050842, -0.008814, 0.211366",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[21]_hldr*/ + +} /* end of pin tl_o[21] */ + +pin("tl_o[20]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001805 ; + + /* Other user defined attributes. */ + original_pin : tl_o[20]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\ + "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\ + "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\ + "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\ + "0.573921, 0.790368, 0.965832, 1.286120, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023351, 0.298998, 0.632448, 1.249153, 2.482563",\ + "0.027948, 0.299981, 0.634399, 1.249153, 2.482563",\ + "0.040978, 0.302244, 0.634435, 1.249153, 2.482563",\ + "0.052873, 0.305533, 0.634536, 1.249153, 2.482563",\ + "0.128351, 0.343984, 0.640795, 1.251713, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\ + "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\ + "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\ + "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\ + "0.585410, 0.701221, 0.812673, 1.015961, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.024071, 0.186967, 0.387445, 0.759756, 1.504378",\ + "0.024071, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.025176, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.027266, 0.187111, 0.387949, 0.759756, 1.504378",\ + "0.045971, 0.191097, 0.387949, 0.759756, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[20]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.047624, 0.200802, 0.376269, 0.699127, 1.344843",\ + "0.133909, 0.287977, 0.463375, 0.785842, 1.430777",\ + "0.216976, 0.376105, 0.551331, 0.873464, 1.517732",\ + "0.274753, 0.440500, 0.615446, 0.937378, 1.581241",\ + "0.573921, 0.790368, 0.965832, 1.286120, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023351, 0.298998, 0.632448, 1.247926, 2.473548",\ + "0.027948, 0.299981, 0.634399, 1.247926, 2.473548",\ + "0.040978, 0.302244, 0.634435, 1.248002, 2.473548",\ + "0.052873, 0.305533, 0.634536, 1.248745, 2.473548",\ + "0.128351, 0.343984, 0.640795, 1.251713, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.067343, 0.172682, 0.284189, 0.488369, 0.896728",\ + "0.154756, 0.260000, 0.371470, 0.575674, 0.984081",\ + "0.235108, 0.340335, 0.451497, 0.655702, 1.064113",\ + "0.291783, 0.397884, 0.509040, 0.712947, 1.120760",\ + "0.585410, 0.701221, 0.812673, 1.015961, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.024071, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.025176, 0.186169, 0.385939, 0.757526, 1.500700",\ + "0.027266, 0.186781, 0.386395, 0.758427, 1.502492",\ + "0.045971, 0.191097, 0.386467, 0.759197, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[20]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211788, 0.165917, 0.135722, 0.124381, 0.138086",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265675, 0.190363, 0.122259, 0.099381, 0.163106",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[20]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023351, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139594, -0.097166, -0.062704, -0.022783, 0.289451",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024071, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173554, -0.107466, -0.049560, -0.007532, 0.212647",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[20]_hldr*/ + +} /* end of pin tl_o[20] */ + +pin("tl_o[19]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002405 ; + + /* Other user defined attributes. */ + original_pin : tl_o[19]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.049247, 0.202011, 0.377177, 0.699733, 1.344843",\ + "0.135622, 0.289186, 0.464282, 0.786447, 1.430777",\ + "0.219089, 0.377313, 0.552236, 0.874068, 1.517732",\ + "0.277267, 0.441706, 0.616352, 0.937981, 1.581241",\ + "0.578868, 0.791580, 0.966732, 1.286721, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.025529, 0.301292, 0.634182, 1.250309, 2.482563",\ + "0.029899, 0.302288, 0.636124, 1.250309, 2.482563",\ + "0.042689, 0.304530, 0.636160, 1.250309, 2.482563",\ + "0.054614, 0.307788, 0.636263, 1.250309, 2.482563",\ + "0.130534, 0.345945, 0.642513, 1.252858, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.068762, 0.173425, 0.284737, 0.488725, 0.896701",\ + "0.156170, 0.260743, 0.372018, 0.576030, 0.984055",\ + "0.236545, 0.341075, 0.452045, 0.656059, 1.064086",\ + "0.293277, 0.398624, 0.509587, 0.713303, 1.120734",\ + "0.587496, 0.701965, 0.813219, 1.016316, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.025535, 0.188296, 0.388444, 0.760406, 1.504329",\ + "0.025535, 0.188444, 0.388947, 0.760406, 1.504329",\ + "0.026576, 0.188444, 0.388947, 0.760406, 1.504329",\ + "0.028604, 0.188444, 0.388947, 0.760406, 1.504329",\ + "0.047029, 0.192380, 0.388947, 0.760406, 1.504609"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[19]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.049247, 0.202011, 0.377177, 0.699733, 1.344843",\ + "0.135622, 0.289186, 0.464282, 0.786447, 1.430777",\ + "0.219089, 0.377313, 0.552236, 0.874068, 1.517732",\ + "0.277267, 0.441706, 0.616352, 0.937981, 1.581241",\ + "0.578868, 0.791580, 0.966732, 1.286721, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.025529, 0.301292, 0.634182, 1.249076, 2.473548",\ + "0.029899, 0.302288, 0.636124, 1.249076, 2.473548",\ + "0.042689, 0.304530, 0.636160, 1.249152, 2.473548",\ + "0.054614, 0.307788, 0.636263, 1.249897, 2.473548",\ + "0.130534, 0.345945, 0.642513, 1.252858, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.068762, 0.173425, 0.284737, 0.488725, 0.896701",\ + "0.156170, 0.260743, 0.372018, 0.576030, 0.984055",\ + "0.236545, 0.341075, 0.452045, 0.656059, 1.064086",\ + "0.293277, 0.398624, 0.509587, 0.713303, 1.120734",\ + "0.587496, 0.701965, 0.813219, 1.016316, 1.422511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.025535, 0.187494, 0.386936, 0.758174, 1.500652",\ + "0.025535, 0.187494, 0.386936, 0.758174, 1.500652",\ + "0.026576, 0.187494, 0.386936, 0.758174, 1.500652",\ + "0.028604, 0.188103, 0.387393, 0.759077, 1.502444",\ + "0.047029, 0.192380, 0.387467, 0.759848, 1.504609"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[19]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025529, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212708, 0.166837, 0.136642, 0.125302, 0.139006",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025535, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266222, 0.190910, 0.122806, 0.099928, 0.163653",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[19]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025529, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140504, -0.098076, -0.063615, -0.023693, 0.288541",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025535, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174097, -0.108010, -0.050104, -0.008076, 0.212104",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[19]_hldr*/ + +} /* end of pin tl_o[19] */ + +pin("tl_o[18]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002343 ; + + /* Other user defined attributes. */ + original_pin : tl_o[18]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\ + "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\ + "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\ + "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\ + "0.578356, 0.791455, 0.966639, 1.286659, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025304, 0.301054, 0.634003, 1.250190, 2.482563",\ + "0.029697, 0.302049, 0.635945, 1.250190, 2.482563",\ + "0.042512, 0.304293, 0.635981, 1.250190, 2.482563",\ + "0.054434, 0.307555, 0.636084, 1.250190, 2.482563",\ + "0.130308, 0.345742, 0.642335, 1.252740, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\ + "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\ + "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\ + "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\ + "0.587289, 0.701891, 0.813166, 1.016283, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025390, 0.188165, 0.388347, 0.760345, 1.504341",\ + "0.025390, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.026437, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.028472, 0.188312, 0.388850, 0.760345, 1.504341",\ + "0.046924, 0.192253, 0.388850, 0.760345, 1.504621"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[18]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049079, 0.201886, 0.377083, 0.699670, 1.344843",\ + "0.135444, 0.289061, 0.464188, 0.786384, 1.430777",\ + "0.218870, 0.377188, 0.552143, 0.874006, 1.517732",\ + "0.277007, 0.441581, 0.616258, 0.937919, 1.581241",\ + "0.578356, 0.791455, 0.966639, 1.286659, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025304, 0.301054, 0.634003, 1.248957, 2.473548",\ + "0.029697, 0.302049, 0.635945, 1.248957, 2.473548",\ + "0.042512, 0.304293, 0.635981, 1.249033, 2.473548",\ + "0.054434, 0.307555, 0.636084, 1.249777, 2.473548",\ + "0.130308, 0.345742, 0.642335, 1.252740, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.068622, 0.173351, 0.284684, 0.488692, 0.896707",\ + "0.156030, 0.260670, 0.371965, 0.575997, 0.984061",\ + "0.236402, 0.341002, 0.451991, 0.656025, 1.064092",\ + "0.293129, 0.398551, 0.509534, 0.713269, 1.120740",\ + "0.587289, 0.701891, 0.813166, 1.016283, 1.422517"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.025390, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.026437, 0.187363, 0.386838, 0.758113, 1.500664",\ + "0.028472, 0.187972, 0.387296, 0.759016, 1.502455",\ + "0.046924, 0.192253, 0.387369, 0.759786, 1.504621"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[18]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.212613, 0.166742, 0.136547, 0.125206, 0.138911",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.266167, 0.190856, 0.122752, 0.099874, 0.163599",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[18]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025304, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.140410, -0.097982, -0.063521, -0.023599, 0.288635",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025390, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.174043, -0.107956, -0.050050, -0.008022, 0.212157",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[18]_hldr*/ + +} /* end of pin tl_o[18] */ + +pin("tl_o[17]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001292 ; + + /* Other user defined attributes. */ + original_pin : tl_o[17]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.046108, 0.199767, 0.375492, 0.698609, 1.344843",\ + "0.132284, 0.286942, 0.462599, 0.785325, 1.430777",\ + "0.214897, 0.375071, 0.550555, 0.872948, 1.517732",\ + "0.272255, 0.439468, 0.614671, 0.936861, 1.581241",\ + "0.568906, 0.789330, 0.965061, 1.285606, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.021470, 0.297034, 0.630964, 1.248164, 2.482563",\ + "0.026264, 0.298006, 0.632922, 1.248164, 2.482563",\ + "0.039476, 0.300287, 0.632958, 1.248164, 2.482563",\ + "0.051325, 0.303602, 0.633057, 1.248164, 2.482563",\ + "0.126317, 0.342305, 0.639325, 1.250732, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.065928, 0.172045, 0.283720, 0.488064, 0.896750",\ + "0.153370, 0.259364, 0.371001, 0.575369, 0.984104",\ + "0.233677, 0.339702, 0.451028, 0.655397, 1.064135",\ + "0.290278, 0.397250, 0.508572, 0.712642, 1.120783",\ + "0.583192, 0.700584, 0.812206, 1.015657, 1.422559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.022780, 0.185829, 0.386590, 0.759200, 1.504419",\ + "0.022780, 0.185969, 0.387096, 0.759200, 1.504419",\ + "0.023886, 0.185969, 0.387096, 0.759200, 1.504419",\ + "0.026044, 0.185969, 0.387096, 0.759200, 1.504419",\ + "0.044904, 0.189998, 0.387096, 0.759200, 1.504699"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[17]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.046108, 0.199767, 0.375492, 0.698609, 1.344843",\ + "0.132284, 0.286942, 0.462599, 0.785325, 1.430777",\ + "0.214897, 0.375071, 0.550555, 0.872948, 1.517732",\ + "0.272255, 0.439468, 0.614671, 0.936861, 1.581241",\ + "0.568906, 0.789330, 0.965061, 1.285606, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.021470, 0.297034, 0.630964, 1.246942, 2.473548",\ + "0.026264, 0.298006, 0.632922, 1.246942, 2.473548",\ + "0.039476, 0.300287, 0.632958, 1.247017, 2.473548",\ + "0.051325, 0.303602, 0.633057, 1.247760, 2.473548",\ + "0.126317, 0.342305, 0.639325, 1.250732, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.065928, 0.172045, 0.283720, 0.488064, 0.896750",\ + "0.153370, 0.259364, 0.371001, 0.575369, 0.984104",\ + "0.233677, 0.339702, 0.451028, 0.655397, 1.064135",\ + "0.290278, 0.397250, 0.508572, 0.712642, 1.120783",\ + "0.583192, 0.700584, 0.812206, 1.015657, 1.422559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.022780, 0.185036, 0.385085, 0.756971, 1.500741",\ + "0.022780, 0.185036, 0.385085, 0.756971, 1.500741",\ + "0.023886, 0.185036, 0.385085, 0.756971, 1.500741",\ + "0.026044, 0.185649, 0.385541, 0.757872, 1.502533",\ + "0.044904, 0.189998, 0.385611, 0.758640, 1.504699"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[17]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.021470, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.210993, 0.165122, 0.134927, 0.123587, 0.137292",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022780, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265192, 0.189881, 0.121777, 0.098899, 0.162623",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[17]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.021470, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.138808, -0.096380, -0.061918, -0.021997, 0.290238",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022780, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173074, -0.106987, -0.049081, -0.007053, 0.213127",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[17]_hldr*/ + +} /* end of pin tl_o[17] */ + +pin("tl_o[16]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001808 ; + + /* Other user defined attributes. */ + original_pin : tl_o[16]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.047630, 0.200806, 0.376273, 0.699130, 1.344843",\ + "0.133916, 0.287981, 0.463378, 0.785845, 1.430777",\ + "0.216984, 0.376109, 0.551334, 0.873467, 1.517732",\ + "0.274762, 0.440505, 0.615450, 0.937380, 1.581241",\ + "0.573940, 0.790372, 0.965835, 1.286123, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.023359, 0.299007, 0.632455, 1.249158, 2.482563",\ + "0.027955, 0.299990, 0.634405, 1.249158, 2.482563",\ + "0.040984, 0.302252, 0.634441, 1.249158, 2.482563",\ + "0.052879, 0.305541, 0.634542, 1.249158, 2.482563",\ + "0.128359, 0.343991, 0.640802, 1.251717, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.067337, 0.172678, 0.284185, 0.488364, 0.896721",\ + "0.154749, 0.259997, 0.371466, 0.575669, 0.984075",\ + "0.235101, 0.340332, 0.451493, 0.655697, 1.064106",\ + "0.291776, 0.397881, 0.509036, 0.712942, 1.120754",\ + "0.585400, 0.701218, 0.812669, 1.015956, 1.422531"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.024064, 0.186961, 0.387438, 0.759747, 1.504366",\ + "0.024064, 0.187105, 0.387942, 0.759747, 1.504366",\ + "0.025170, 0.187105, 0.387942, 0.759747, 1.504366",\ + "0.027260, 0.187105, 0.387942, 0.759747, 1.504366",\ + "0.045966, 0.191091, 0.387942, 0.759747, 1.504646"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[16]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.047630, 0.200806, 0.376273, 0.699130, 1.344843",\ + "0.133916, 0.287981, 0.463378, 0.785845, 1.430777",\ + "0.216984, 0.376109, 0.551334, 0.873467, 1.517732",\ + "0.274762, 0.440505, 0.615450, 0.937380, 1.581241",\ + "0.573940, 0.790372, 0.965835, 1.286123, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.023359, 0.299007, 0.632455, 1.247931, 2.473548",\ + "0.027955, 0.299990, 0.634405, 1.247931, 2.473548",\ + "0.040984, 0.302252, 0.634441, 1.248006, 2.473548",\ + "0.052879, 0.305541, 0.634542, 1.248749, 2.473548",\ + "0.128359, 0.343991, 0.640802, 1.251717, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.067337, 0.172678, 0.284185, 0.488364, 0.896721",\ + "0.154749, 0.259997, 0.371466, 0.575669, 0.984075",\ + "0.235101, 0.340332, 0.451493, 0.655697, 1.064106",\ + "0.291776, 0.397881, 0.509036, 0.712942, 1.120754",\ + "0.585400, 0.701218, 0.812669, 1.015956, 1.422531"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.024064, 0.186164, 0.385931, 0.757517, 1.500689",\ + "0.024064, 0.186164, 0.385931, 0.757517, 1.500689",\ + "0.025170, 0.186164, 0.385931, 0.757517, 1.500689",\ + "0.027260, 0.186775, 0.386388, 0.758419, 1.502481",\ + "0.045966, 0.191091, 0.386459, 0.759188, 1.504646"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[16]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.204621, 0.158750, 0.128555, 0.117215, 0.130920",\ + "0.211791, 0.165920, 0.135725, 0.124385, 0.138090",\ + "0.293024, 0.247053, 0.216850, 0.205504, 0.219174",\ + "0.388106, 0.341808, 0.311580, 0.300214, 0.313773",\ + "0.793561, 0.745754, 0.715310, 0.703809, 0.716803"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024064, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.259341, 0.184030, 0.115926, 0.093048, 0.156772",\ + "0.265672, 0.190361, 0.122257, 0.099379, 0.163103",\ + "0.344697, 0.269391, 0.201316, 0.178485, 0.242634",\ + "0.449796, 0.374511, 0.306547, 0.283898, 0.349697",\ + "0.899406, 0.824219, 0.756483, 0.734362, 0.805439"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[16]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.132553, -0.090125, -0.055664, -0.015742, 0.296492",\ + "-0.139597, -0.097169, -0.062708, -0.022786, 0.289448",\ + "-0.216780, -0.174368, -0.139869, -0.100670, 0.202593",\ + "-0.303076, -0.260711, -0.226103, -0.189037, 0.087742",\ + "-0.670076, -0.627993, -0.592717, -0.568584, -0.452318"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024064, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.167403, -0.101316, -0.043410, -0.001382, 0.218797",\ + "-0.173551, -0.107464, -0.049558, -0.007530, 0.212650",\ + "-0.248843, -0.182697, -0.124706, -0.082655, 0.137377",\ + "-0.346211, -0.279755, -0.221320, -0.179149, 0.040114",\ + "-0.760494, -0.692486, -0.632012, -0.589251, -0.373041"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[16]_hldr*/ + +} /* end of pin tl_o[16] */ + +pin("tl_o[15]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.035370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + function : "0" ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[15]; +} /* end of pin tl_o[15] */ + +pin("tl_o[14]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.154883 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[14]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.487261, 0.669190, 0.852549, 1.146075, 1.714279",\ + "0.520839, 0.702769, 0.886128, 1.179654, 1.747858",\ + "0.591826, 0.773756, 0.957115, 1.250640, 1.818845",\ + "0.846910, 1.028840, 1.212200, 1.505725, 2.073928",\ + "1.772164, 1.954093, 2.137452, 2.430978, 2.999182",\ + "0.574671, 0.756577, 0.940009, 1.233380, 1.801632",\ + "0.608250, 0.790156, 0.973588, 1.266959, 1.835211",\ + "0.679237, 0.861143, 1.044574, 1.337945, 1.906198",\ + "0.934321, 1.116227, 1.299660, 1.593030, 2.161281",\ + "1.859574, 2.041480, 2.224912, 2.518283, 3.086535",\ + "0.655541, 0.836911, 1.020036, 1.313408, 1.881664",\ + "0.689120, 0.870490, 1.053615, 1.346987, 1.915242",\ + "0.760107, 0.941477, 1.124601, 1.417974, 1.986230",\ + "1.015191, 1.196561, 1.379687, 1.673059, 2.241313",\ + "1.940444, 2.121814, 2.304939, 2.598311, 3.166567",\ + "0.713217, 0.894460, 1.077579, 1.370653, 1.938311",\ + "0.746796, 0.928038, 1.111158, 1.404232, 1.971890",\ + "0.817783, 0.999025, 1.182144, 1.475219, 2.042877",\ + "1.072867, 1.254110, 1.437230, 1.730303, 2.297960",\ + "1.998120, 2.179363, 2.362482, 2.655556, 3.223215",\ + "1.015892, 1.199670, 1.381211, 1.673666, 2.240149",\ + "1.049471, 1.233248, 1.414790, 1.707245, 2.273727",\ + "1.120458, 1.304235, 1.485777, 1.778232, 2.344714",\ + "1.375542, 1.559320, 1.740862, 2.033317, 2.599797",\ + "2.300795, 2.484573, 2.666114, 2.958570, 3.525052"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069353",\ + "0.200458, 0.200458, 0.200458, 0.200458, 0.200458",\ + "0.686693, 0.686693, 0.686693, 0.686694, 0.686697",\ + "2.458885, 2.458885, 2.458885, 2.458885, 2.458885"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.570397, 0.827870, 1.084327, 1.522623, 2.399216",\ + "0.611284, 0.868757, 1.125214, 1.563510, 2.440103",\ + "0.671440, 0.928913, 1.185369, 1.623666, 2.500259",\ + "0.840387, 1.097859, 1.354316, 1.792613, 2.669205",\ + "1.423797, 1.681270, 1.937729, 2.376020, 3.252604",\ + "0.658623, 0.915349, 1.171797, 1.609338, 2.485150",\ + "0.699510, 0.956236, 1.212684, 1.650225, 2.526037",\ + "0.759666, 1.016392, 1.272839, 1.710381, 2.586193",\ + "0.928613, 1.185339, 1.441786, 1.879327, 2.755138",\ + "1.512023, 1.768749, 2.025198, 2.462735, 3.338538",\ + "0.747341, 1.004170, 1.259759, 1.696960, 2.572105",\ + "0.788228, 1.045057, 1.300646, 1.737847, 2.612992",\ + "0.848383, 1.105212, 1.360802, 1.798002, 2.673148",\ + "1.017330, 1.274159, 1.529749, 1.966949, 2.842093",\ + "1.600740, 1.857569, 2.113161, 2.550357, 3.425493",\ + "0.810342, 1.069571, 1.323894, 1.760873, 2.635614",\ + "0.851229, 1.110458, 1.364781, 1.801760, 2.676501",\ + "0.911385, 1.170614, 1.424936, 1.861916, 2.736657",\ + "1.080332, 1.339561, 1.593883, 2.030862, 2.905602",\ + "1.663742, 1.922971, 2.177295, 2.614270, 3.489002",\ + "1.142661, 1.431230, 1.675450, 2.110093, 2.981070",\ + "1.183547, 1.472117, 1.716337, 2.150980, 3.021957",\ + "1.243703, 1.532272, 1.776492, 2.211136, 3.082113",\ + "1.412650, 1.701219, 1.945439, 2.380082, 3.251059",\ + "1.996059, 2.284630, 2.528851, 2.963490, 3.834458"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\ + "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\ + "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\ + "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974",\ + "0.042573, 0.042574, 0.042574, 0.042574, 0.042574",\ + "0.078573, 0.078573, 0.078573, 0.078574, 0.078575",\ + "0.154782, 0.154782, 0.154782, 0.154783, 0.154784",\ + "0.431097, 0.431097, 0.431098, 0.431098, 0.431098",\ + "1.494947, 1.494947, 1.494950, 1.494958, 1.494974"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[14]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.487261, 0.668812, 0.852015, 1.145595, 1.713488",\ + "0.520839, 0.702391, 0.885594, 1.179174, 1.747067",\ + "0.591826, 0.773378, 0.956580, 1.250161, 1.818054",\ + "0.846910, 1.028462, 1.211666, 1.505246, 2.073137",\ + "1.772164, 1.953715, 2.136918, 2.430498, 2.998391",\ + "0.574671, 0.756130, 0.939295, 1.232900, 1.800842",\ + "0.608250, 0.789709, 0.972874, 1.266479, 1.834420",\ + "0.679237, 0.860696, 1.043861, 1.337466, 1.905408",\ + "0.934321, 1.115781, 1.298946, 1.592551, 2.160491",\ + "1.859574, 2.041033, 2.224198, 2.517803, 3.085745",\ + "0.655541, 0.836464, 1.019322, 1.312929, 1.880873",\ + "0.689120, 0.870043, 1.052901, 1.346508, 1.914452",\ + "0.760107, 0.941030, 1.123888, 1.417494, 1.985439",\ + "1.015191, 1.196114, 1.378973, 1.672579, 2.240522",\ + "1.940444, 2.121367, 2.304225, 2.597832, 3.165776",\ + "0.713217, 0.894301, 1.077028, 1.370367, 1.937906",\ + "0.746796, 0.927880, 1.110607, 1.403946, 1.971485",\ + "0.817783, 0.998867, 1.181593, 1.474933, 2.042472",\ + "1.072867, 1.253952, 1.436679, 1.730018, 2.297555",\ + "1.998120, 2.179204, 2.361931, 2.655270, 3.222809",\ + "1.015892, 1.199670, 1.380685, 1.673546, 2.240149",\ + "1.049471, 1.233248, 1.414264, 1.707125, 2.273727",\ + "1.120458, 1.304235, 1.485251, 1.778112, 2.344714",\ + "1.375542, 1.559320, 1.740336, 2.033197, 2.599797",\ + "2.300795, 2.484573, 2.665588, 2.958449, 3.525052"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656",\ + "0.023781, 0.023781, 0.023781, 0.023781, 0.023781",\ + "0.069352, 0.069352, 0.069352, 0.069352, 0.069352",\ + "0.200457, 0.200457, 0.200457, 0.200457, 0.200457",\ + "0.686690, 0.686690, 0.686690, 0.686692, 0.686695",\ + "2.458656, 2.458656, 2.458656, 2.458656, 2.458656"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.570397, 0.827870, 1.084327, 1.522393, 2.397526",\ + "0.611284, 0.868757, 1.125214, 1.563280, 2.438413",\ + "0.671440, 0.928913, 1.185369, 1.623435, 2.498569",\ + "0.840387, 1.097859, 1.354316, 1.792382, 2.667514",\ + "1.423797, 1.681270, 1.937729, 2.375790, 3.250914",\ + "0.658623, 0.915349, 1.171797, 1.609107, 2.483460",\ + "0.699510, 0.956236, 1.212684, 1.649994, 2.524347",\ + "0.759666, 1.016392, 1.272839, 1.710150, 2.584503",\ + "0.928613, 1.185339, 1.441786, 1.879097, 2.753448",\ + "1.512023, 1.768749, 2.025198, 2.462505, 3.336848",\ + "0.747341, 1.004170, 1.259759, 1.696743, 2.570415",\ + "0.788228, 1.045057, 1.300646, 1.737630, 2.611302",\ + "0.848383, 1.105212, 1.360802, 1.797786, 2.671458",\ + "1.017330, 1.274159, 1.529749, 1.966733, 2.840403",\ + "1.600740, 1.857569, 2.113161, 2.550140, 3.423803",\ + "0.810342, 1.069571, 1.323894, 1.760796, 2.633924",\ + "0.851229, 1.110458, 1.364781, 1.801683, 2.674811",\ + "0.911385, 1.170614, 1.424936, 1.861839, 2.734967",\ + "1.080332, 1.339561, 1.593883, 2.030786, 2.903912",\ + "1.663742, 1.922971, 2.177295, 2.614193, 3.487312",\ + "1.142661, 1.431230, 1.675450, 2.110093, 2.979380",\ + "1.183547, 1.472117, 1.716337, 2.150980, 3.020267",\ + "1.243703, 1.532272, 1.776492, 2.211136, 3.080423",\ + "1.412650, 1.701219, 1.945439, 2.380082, 3.249368",\ + "1.996059, 2.284630, 2.528851, 2.963490, 3.832768"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\ + "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\ + "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\ + "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973",\ + "0.042570, 0.042570, 0.042570, 0.042570, 0.042570",\ + "0.078571, 0.078571, 0.078572, 0.078573, 0.078575",\ + "0.154780, 0.154780, 0.154781, 0.154782, 0.154784",\ + "0.431094, 0.431094, 0.431094, 0.431094, 0.431094",\ + "1.494932, 1.494932, 1.494936, 1.494948, 1.494973"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[14]_redg_min*/ + +} /* end of pin tl_o[14] */ + +pin("tl_o[13]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.035370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[13]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.284540, 0.564046, 0.863617, 1.380944, 2.415600",\ + "0.298686, 0.578104, 0.877668, 1.395235, 2.430368",\ + "0.322356, 0.601709, 0.901313, 1.419287, 2.455237",\ + "0.588425, 0.867068, 1.165530, 1.682108, 2.715266",\ + "1.177776, 1.456090, 1.753734, 2.268545, 3.298168",\ + "0.372946, 0.651675, 0.951331, 1.467657, 2.501533",\ + "0.387092, 0.665733, 0.965383, 1.481948, 2.516302",\ + "0.410761, 0.689337, 0.989029, 1.506001, 2.541171",\ + "0.676826, 0.954691, 1.253242, 1.768821, 2.801200",\ + "1.266174, 1.543712, 1.841440, 2.355258, 3.384101",\ + "0.462897, 0.740788, 1.039296, 1.555278, 2.588488",\ + "0.477041, 0.754844, 1.053348, 1.569568, 2.603257",\ + "0.500709, 0.778447, 1.076994, 1.593621, 2.628126",\ + "0.766761, 1.043790, 1.341207, 1.856442, 2.888155",\ + "1.356101, 1.632807, 1.929405, 2.442878, 3.471056",\ + "0.527359, 0.806612, 1.103444, 1.619190, 2.651997",\ + "0.541500, 0.820667, 1.117496, 1.633481, 2.666766",\ + "0.565168, 0.844269, 1.141142, 1.657534, 2.691635",\ + "0.831207, 1.109596, 1.405354, 1.920354, 2.951664",\ + "1.420539, 1.698606, 1.993552, 2.506791, 3.534565",\ + "0.868940, 1.173349, 1.455796, 1.968728, 2.997453",\ + "0.883067, 1.187384, 1.469851, 1.983020, 3.012222",\ + "0.906732, 1.210965, 1.493501, 2.007074, 3.037091",\ + "1.172689, 1.476110, 1.757699, 2.269889, 3.297120",\ + "1.761970, 2.065045, 2.345879, 2.856318, 3.880022"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.185739, 0.187595, 0.200176, 0.234510, 0.303179",\ + "0.203933, 0.205579, 0.217466, 0.250509, 0.316595",\ + "0.237929, 0.239084, 0.249124, 0.278309, 0.336679",\ + "0.816189, 0.816358, 0.816864, 0.818096, 0.820559",\ + "2.192673, 2.192673, 2.192836, 2.193388, 2.194490",\ + "0.185741, 0.187611, 0.200283, 0.234510, 0.303179",\ + "0.203935, 0.205594, 0.217569, 0.250509, 0.316595",\ + "0.237932, 0.239093, 0.249216, 0.278309, 0.336679",\ + "0.816190, 0.816359, 0.816868, 0.818096, 0.820559",\ + "2.192673, 2.192673, 2.192838, 2.193388, 2.194490",\ + "0.185746, 0.187647, 0.200285, 0.234510, 0.303179",\ + "0.203942, 0.205625, 0.217571, 0.250509, 0.316595",\ + "0.237941, 0.239114, 0.249217, 0.278309, 0.336679",\ + "0.816195, 0.816361, 0.816868, 0.818096, 0.820559",\ + "2.192673, 2.192673, 2.192838, 2.193388, 2.194490",\ + "0.185751, 0.187699, 0.200291, 0.234510, 0.303179",\ + "0.203948, 0.205670, 0.217577, 0.250509, 0.316595",\ + "0.237949, 0.239145, 0.249223, 0.278309, 0.336679",\ + "0.816200, 0.816364, 0.816869, 0.818096, 0.820559",\ + "2.192673, 2.192673, 2.192838, 2.193388, 2.194490",\ + "0.185783, 0.188312, 0.200639, 0.234651, 0.303179",\ + "0.203989, 0.206205, 0.217912, 0.250645, 0.316595",\ + "0.238001, 0.239502, 0.249518, 0.278429, 0.336679",\ + "0.816229, 0.816400, 0.816881, 0.818101, 0.820559",\ + "2.192673, 2.192673, 2.192844, 2.193390, 2.194490"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.374522, 0.561124, 0.780572, 1.136359, 1.826584",\ + "0.383805, 0.570576, 0.790645, 1.147661, 1.840366",\ + "0.399074, 0.586082, 0.807015, 1.165645, 1.861569",\ + "0.557633, 0.745097, 0.967701, 1.332699, 2.042731",\ + "0.898199, 1.085553, 1.307755, 1.673592, 2.385983",\ + "0.461924, 0.648520, 0.868125, 1.223665, 1.913938",\ + "0.471207, 0.657972, 0.878200, 1.234966, 1.927719",\ + "0.486476, 0.673478, 0.894572, 1.252950, 1.948923",\ + "0.645035, 0.832494, 1.055262, 1.420004, 2.130085",\ + "0.985600, 1.172950, 1.395316, 1.760897, 2.473337",\ + "0.542814, 0.728848, 0.948152, 1.303693, 1.993969",\ + "0.552097, 0.738300, 0.958227, 1.314994, 2.007751",\ + "0.567368, 0.753806, 0.974599, 1.332979, 2.028955",\ + "0.725929, 0.912822, 1.135289, 1.500032, 2.210116",\ + "1.066495, 1.253278, 1.475343, 1.840926, 2.553368",\ + "0.600620, 0.786398, 1.005694, 1.360937, 2.050617",\ + "0.609906, 0.795850, 1.015768, 1.372238, 2.064399",\ + "0.625179, 0.811356, 1.032140, 1.390222, 2.085602",\ + "0.783746, 0.970371, 1.192830, 1.557276, 2.266764",\ + "1.124310, 1.310827, 1.532884, 1.898169, 2.610016",\ + "0.904940, 1.091713, 1.309322, 1.663948, 2.352501",\ + "0.914244, 1.101169, 1.319397, 1.675249, 2.366283",\ + "0.929544, 1.116681, 1.335769, 1.693234, 2.387488",\ + "1.088161, 1.275707, 1.496459, 1.860287, 2.568655",\ + "1.428713, 1.616160, 1.836513, 2.201180, 2.911908"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.065408, 0.068159, 0.078360, 0.098953, 0.140695",\ + "0.068352, 0.070728, 0.079541, 0.099563, 0.141041",\ + "0.087647, 0.089359, 0.095706, 0.112588, 0.148436",\ + "0.381015, 0.381154, 0.381669, 0.388289, 0.403942",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\ + "0.065408, 0.068161, 0.078386, 0.098953, 0.140695",\ + "0.068352, 0.070731, 0.079564, 0.099563, 0.141041",\ + "0.087647, 0.089361, 0.095723, 0.112588, 0.148436",\ + "0.381015, 0.381154, 0.381670, 0.388289, 0.403942",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\ + "0.065424, 0.068161, 0.078386, 0.098953, 0.140695",\ + "0.068366, 0.070731, 0.079564, 0.099563, 0.141041",\ + "0.087657, 0.089361, 0.095723, 0.112588, 0.148436",\ + "0.381016, 0.381154, 0.381670, 0.388289, 0.403942",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\ + "0.065456, 0.068161, 0.078386, 0.098953, 0.140695",\ + "0.068394, 0.070731, 0.079564, 0.099563, 0.141041",\ + "0.087678, 0.089361, 0.095723, 0.112588, 0.148436",\ + "0.381018, 0.381154, 0.381670, 0.388289, 0.403942",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517",\ + "0.065761, 0.068226, 0.078386, 0.098953, 0.140710",\ + "0.068657, 0.070787, 0.079564, 0.099563, 0.141057",\ + "0.087867, 0.089401, 0.095723, 0.112588, 0.148450",\ + "0.381033, 0.381158, 0.381670, 0.388289, 0.403948",\ + "1.027611, 1.027611, 1.027611, 1.028167, 1.029517"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[13]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.284540, 0.564046, 0.863617, 1.380550, 2.412738",\ + "0.298686, 0.578104, 0.877668, 1.394840, 2.427504",\ + "0.322356, 0.601709, 0.901313, 1.418892, 2.452366",\ + "0.588425, 0.867068, 1.165530, 1.681715, 2.712415",\ + "1.177776, 1.456090, 1.753734, 2.268156, 3.295343",\ + "0.372946, 0.651675, 0.951331, 1.467263, 2.498672",\ + "0.387092, 0.665733, 0.965383, 1.481553, 2.513437",\ + "0.410761, 0.689337, 0.989029, 1.505605, 2.538300",\ + "0.676826, 0.954691, 1.253242, 1.768429, 2.798349",\ + "1.266174, 1.543712, 1.841440, 2.354868, 3.381277",\ + "0.462897, 0.740788, 1.039296, 1.554907, 2.585627",\ + "0.477041, 0.754844, 1.053348, 1.569197, 2.600392",\ + "0.500709, 0.778447, 1.076994, 1.593250, 2.625255",\ + "0.766761, 1.043790, 1.341207, 1.856073, 2.885304",\ + "1.356101, 1.632807, 1.929405, 2.442513, 3.468232",\ + "0.527359, 0.806612, 1.103444, 1.619057, 2.649136",\ + "0.541500, 0.820667, 1.117496, 1.633347, 2.663901",\ + "0.565168, 0.844269, 1.141142, 1.657400, 2.688764",\ + "0.831207, 1.109596, 1.405354, 1.920222, 2.948813",\ + "1.420539, 1.698606, 1.993552, 2.506659, 3.531741",\ + "0.868940, 1.173349, 1.455796, 1.968728, 2.994592",\ + "0.883067, 1.187384, 1.469851, 1.983020, 3.009357",\ + "0.906732, 1.210965, 1.493501, 2.007074, 3.034220",\ + "1.172689, 1.476110, 1.757699, 2.269889, 3.294269",\ + "1.761970, 2.065045, 2.345879, 2.856318, 3.877197"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.185739, 0.187595, 0.200176, 0.234441, 0.302676",\ + "0.203933, 0.205579, 0.217466, 0.250442, 0.316110",\ + "0.237929, 0.239084, 0.249124, 0.278250, 0.336252",\ + "0.816189, 0.816358, 0.816864, 0.818093, 0.820541",\ + "2.191667, 2.191667, 2.191920, 2.192775, 2.194479",\ + "0.185741, 0.187611, 0.200283, 0.234441, 0.302676",\ + "0.203935, 0.205594, 0.217569, 0.250442, 0.316110",\ + "0.237932, 0.239093, 0.249216, 0.278250, 0.336252",\ + "0.816190, 0.816359, 0.816868, 0.818093, 0.820541",\ + "2.191667, 2.191667, 2.191923, 2.192775, 2.194479",\ + "0.185746, 0.187647, 0.200285, 0.234445, 0.302676",\ + "0.203942, 0.205625, 0.217571, 0.250446, 0.316110",\ + "0.237941, 0.239114, 0.249217, 0.278254, 0.336252",\ + "0.816195, 0.816361, 0.816868, 0.818094, 0.820541",\ + "2.191667, 2.191667, 2.191923, 2.192775, 2.194479",\ + "0.185751, 0.187699, 0.200291, 0.234487, 0.302676",\ + "0.203948, 0.205670, 0.217577, 0.250486, 0.316110",\ + "0.237949, 0.239145, 0.249223, 0.278289, 0.336252",\ + "0.816200, 0.816364, 0.816869, 0.818095, 0.820541",\ + "2.191667, 2.191667, 2.191923, 2.192777, 2.194479",\ + "0.185783, 0.188312, 0.200639, 0.234651, 0.302676",\ + "0.203989, 0.206205, 0.217912, 0.250645, 0.316110",\ + "0.238001, 0.239502, 0.249518, 0.278429, 0.336252",\ + "0.816229, 0.816400, 0.816881, 0.818101, 0.820541",\ + "2.191667, 2.191667, 2.191932, 2.192781, 2.194479"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.374522, 0.560710, 0.779750, 1.135509, 1.825184",\ + "0.383805, 0.570161, 0.789818, 1.146803, 1.838953",\ + "0.399074, 0.585665, 0.806181, 1.164778, 1.860141",\ + "0.557633, 0.744678, 0.966854, 1.331789, 2.041233",\ + "0.898199, 1.085135, 1.306912, 1.672675, 2.384473",\ + "0.461924, 0.648027, 0.867031, 1.222814, 1.912538",\ + "0.471207, 0.657479, 0.877099, 1.234108, 1.926307",\ + "0.486476, 0.672983, 0.893462, 1.252083, 1.947495",\ + "0.645035, 0.831996, 1.054135, 1.419094, 2.128587",\ + "0.985600, 1.172452, 1.394193, 1.759980, 2.471827",\ + "0.542814, 0.728355, 0.947058, 1.302843, 1.992569",\ + "0.552097, 0.737807, 0.957126, 1.314137, 2.006338",\ + "0.567368, 0.753311, 0.973489, 1.332111, 2.027526",\ + "0.725929, 0.912324, 1.134162, 1.499123, 2.208618",\ + "1.066495, 1.252781, 1.474220, 1.840009, 2.551858",\ + "0.600620, 0.786214, 1.004849, 1.360430, 2.049899",\ + "0.609906, 0.795666, 1.014919, 1.371727, 2.063674",\ + "0.625179, 0.811172, 1.031284, 1.389706, 2.084870",\ + "0.783746, 0.970186, 1.191961, 1.556734, 2.265996",\ + "1.124310, 1.310642, 1.532018, 1.897623, 2.609242",\ + "0.904940, 1.091713, 1.308519, 1.663736, 2.352501",\ + "0.914244, 1.101169, 1.318589, 1.675035, 2.366283",\ + "0.929544, 1.116681, 1.334955, 1.693017, 2.387488",\ + "1.088161, 1.275707, 1.495632, 1.860060, 2.568655",\ + "1.428713, 1.616160, 1.835689, 2.200952, 2.911908"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.065408, 0.068145, 0.078282, 0.097416, 0.135633",\ + "0.068319, 0.070715, 0.079474, 0.098027, 0.135980",\ + "0.087624, 0.089350, 0.095658, 0.111069, 0.143404",\ + "0.381014, 0.381153, 0.381665, 0.388242, 0.403865",\ + "1.027072, 1.027072, 1.027072, 1.027705, 1.029249",\ + "0.065408, 0.068145, 0.078282, 0.097416, 0.135633",\ + "0.068319, 0.070715, 0.079474, 0.098027, 0.135980",\ + "0.087624, 0.089350, 0.095658, 0.111069, 0.143404",\ + "0.381014, 0.381153, 0.381665, 0.388242, 0.403865",\ + "1.027072, 1.027072, 1.027072, 1.027705, 1.029249",\ + "0.065424, 0.068145, 0.078282, 0.097416, 0.135633",\ + "0.068333, 0.070715, 0.079474, 0.098027, 0.135980",\ + "0.087634, 0.089350, 0.095658, 0.111069, 0.143404",\ + "0.381014, 0.381153, 0.381665, 0.388242, 0.403865",\ + "1.027072, 1.027072, 1.027072, 1.027705, 1.029249",\ + "0.065456, 0.068155, 0.078306, 0.097463, 0.135725",\ + "0.068362, 0.070724, 0.079494, 0.098073, 0.136072",\ + "0.087655, 0.089356, 0.095672, 0.111109, 0.143482",\ + "0.381016, 0.381154, 0.381666, 0.388261, 0.403903",\ + "1.027072, 1.027072, 1.027072, 1.027707, 1.029253",\ + "0.065761, 0.068226, 0.078310, 0.097503, 0.135836",\ + "0.068628, 0.070787, 0.079498, 0.098113, 0.136183",\ + "0.087847, 0.089401, 0.095675, 0.111142, 0.143576",\ + "0.381032, 0.381158, 0.381666, 0.388277, 0.403948",\ + "1.027072, 1.027072, 1.027072, 1.027708, 1.029258"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[13]_redg_min*/ + +} /* end of pin tl_o[13] */ + +pin("tl_o[12]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[12]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.475879, 0.665118, 0.888399, 1.250294, 1.951686",\ + "0.526872, 0.716033, 0.939041, 1.300629, 2.001501",\ + "0.604552, 0.793643, 1.016400, 1.377502, 2.077400",\ + "0.813681, 1.002691, 1.225160, 1.585609, 2.284153",\ + "1.367036, 1.556010, 1.778356, 2.138460, 2.836268",\ + "0.563289, 0.752511, 0.975963, 1.337600, 2.039039",\ + "0.614282, 0.803427, 1.026603, 1.387934, 2.088855",\ + "0.691962, 0.881036, 1.103961, 1.464807, 2.164753",\ + "0.901091, 1.090085, 1.312721, 1.672914, 2.371507",\ + "1.454446, 1.643404, 1.865916, 2.225765, 2.923622",\ + "0.644207, 0.832845, 1.055990, 1.417628, 2.119071",\ + "0.695200, 0.883761, 1.106630, 1.467962, 2.168886",\ + "0.772879, 0.961370, 1.183988, 1.544836, 2.244785",\ + "0.982008, 1.170418, 1.392748, 1.752943, 2.451539",\ + "1.535362, 1.723738, 1.945943, 2.305794, 3.003654",\ + "0.701978, 0.890394, 1.113533, 1.474873, 2.175719",\ + "0.752969, 0.941309, 1.164173, 1.525207, 2.225534",\ + "0.830648, 1.018919, 1.241531, 1.602080, 2.301433",\ + "1.039776, 1.227967, 1.450291, 1.810187, 2.508186",\ + "1.593130, 1.781286, 2.003486, 2.363039, 3.060301",\ + "1.005526, 1.195782, 1.417165, 1.777886, 2.477606",\ + "1.056509, 1.246695, 1.467805, 1.828220, 2.527421",\ + "1.134180, 1.324303, 1.545163, 1.905094, 2.603319",\ + "1.343298, 1.533349, 1.753923, 2.113201, 2.810072",\ + "1.896648, 2.086668, 2.307118, 2.666052, 3.362187"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.150008, 0.150413, 0.151867, 0.156224, 0.165642",\ + "0.237388, 0.237631, 0.238503, 0.240761, 0.245540",\ + "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873945, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\ + "0.150008, 0.150413, 0.151871, 0.156224, 0.165642",\ + "0.237388, 0.237631, 0.238506, 0.240761, 0.245540",\ + "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873945, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\ + "0.150011, 0.150413, 0.151871, 0.156224, 0.165642",\ + "0.237390, 0.237631, 0.238506, 0.240761, 0.245540",\ + "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873945, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\ + "0.150016, 0.150413, 0.151871, 0.156224, 0.165642",\ + "0.237393, 0.237631, 0.238506, 0.240761, 0.245540",\ + "0.400537, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873946, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920",\ + "0.150062, 0.150423, 0.151871, 0.156224, 0.165645",\ + "0.237420, 0.237637, 0.238506, 0.240761, 0.245542",\ + "0.400539, 0.400554, 0.400616, 0.401193, 0.402548",\ + "0.873947, 0.873960, 0.874011, 0.874292, 0.874933",\ + "2.149644, 2.149644, 2.149644, 2.149724, 2.149920"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.321064, 0.601616, 0.902007, 1.418205, 2.450602",\ + "0.356109, 0.636678, 0.937135, 1.453516, 2.486277",\ + "0.406657, 0.687216, 0.987647, 1.504000, 2.536706",\ + "0.536144, 0.816696, 1.117064, 1.633222, 2.665537",\ + "0.873984, 1.154534, 1.454850, 1.970856, 3.002866",\ + "0.409514, 0.689233, 0.989723, 1.504920, 2.536536",\ + "0.444559, 0.724295, 1.024851, 1.540230, 2.572211",\ + "0.495106, 0.774833, 1.075363, 1.590714, 2.622640",\ + "0.624593, 0.904313, 1.204779, 1.719936, 2.751471",\ + "0.962434, 1.242151, 1.542565, 2.057570, 3.088800",\ + "0.498914, 0.778364, 1.077690, 1.592542, 2.623491",\ + "0.533960, 0.813427, 1.112818, 1.627852, 2.659166",\ + "0.584508, 0.863965, 1.163329, 1.678336, 2.709595",\ + "0.713994, 0.993445, 1.292746, 1.807558, 2.838426",\ + "1.051835, 1.331282, 1.630532, 2.145192, 3.175755",\ + "0.562563, 0.844218, 1.141837, 1.656455, 2.687000",\ + "0.597610, 0.879281, 1.176965, 1.691765, 2.722675",\ + "0.648158, 0.929819, 1.227477, 1.742249, 2.773104",\ + "0.777645, 1.059298, 1.356893, 1.871471, 2.901935",\ + "1.115485, 1.397135, 1.694679, 2.209105, 3.239264",\ + "0.898997, 1.211173, 1.494183, 2.005997, 3.032455",\ + "0.934048, 1.246239, 1.529313, 2.041308, 3.068131",\ + "0.984598, 1.296772, 1.579825, 2.091792, 3.118560",\ + "1.114083, 1.426250, 1.709239, 2.221013, 3.247391",\ + "1.451924, 1.764086, 2.047024, 2.558647, 3.584720"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.072029, 0.072117, 0.072944, 0.075686, 0.081171",\ + "0.105035, 0.105045, 0.105444, 0.106815, 0.109557",\ + "0.191067, 0.191185, 0.191447, 0.191928, 0.192889",\ + "0.434550, 0.434818, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073593, 1.073946, 1.074653",\ + "0.072030, 0.072117, 0.072953, 0.075686, 0.081171",\ + "0.105035, 0.105045, 0.105449, 0.106815, 0.109557",\ + "0.191068, 0.191185, 0.191449, 0.191928, 0.192889",\ + "0.434555, 0.434819, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073594, 1.073946, 1.074653",\ + "0.072035, 0.072117, 0.072953, 0.075686, 0.081171",\ + "0.105035, 0.105045, 0.105449, 0.106815, 0.109557",\ + "0.191071, 0.191187, 0.191449, 0.191928, 0.192889",\ + "0.434567, 0.434821, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073594, 1.073946, 1.074653",\ + "0.072040, 0.072118, 0.072953, 0.075686, 0.081171",\ + "0.105036, 0.105045, 0.105449, 0.106815, 0.109557",\ + "0.191073, 0.191190, 0.191449, 0.191928, 0.192889",\ + "0.434578, 0.434825, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073594, 1.073946, 1.074653",\ + "0.072068, 0.072127, 0.072981, 0.075698, 0.081171",\ + "0.105040, 0.105046, 0.105463, 0.106821, 0.109557",\ + "0.191088, 0.191220, 0.191454, 0.191930, 0.192889",\ + "0.434649, 0.434864, 0.434976, 0.434976, 0.434976",\ + "1.073490, 1.073490, 1.073597, 1.073947, 1.074653"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[12]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.475879, 0.664703, 0.887555, 1.249416, 1.950237",\ + "0.526872, 0.715619, 0.938198, 1.299751, 2.000055",\ + "0.604552, 0.793229, 1.015559, 1.376628, 2.075958",\ + "0.813681, 1.002278, 1.224322, 1.584739, 2.282718",\ + "1.367036, 1.555598, 1.777518, 2.137592, 2.834837",\ + "0.563289, 0.752022, 0.974836, 1.336721, 2.037590",\ + "0.614282, 0.802938, 1.025479, 1.387056, 2.087408",\ + "0.691962, 0.880548, 1.102840, 1.463933, 2.163312",\ + "0.901091, 1.089596, 1.311603, 1.672044, 2.370072",\ + "1.454446, 1.642916, 1.864799, 2.224897, 2.922191",\ + "0.644207, 0.832355, 1.054863, 1.416749, 2.117622",\ + "0.695200, 0.883271, 1.105506, 1.467085, 2.167440",\ + "0.772879, 0.960881, 1.182867, 1.543961, 2.243343",\ + "0.982008, 1.169930, 1.391630, 1.752072, 2.450104",\ + "1.535362, 1.723250, 1.944826, 2.304926, 3.002222",\ + "0.701978, 0.890220, 1.112662, 1.474349, 2.174976",\ + "0.752969, 0.941136, 1.163305, 1.524684, 2.224792",\ + "0.830648, 1.018745, 1.240665, 1.601559, 2.300694",\ + "1.039776, 1.227793, 1.449427, 1.809669, 2.507451",\ + "1.593130, 1.781113, 2.002623, 2.362521, 3.059567",\ + "1.005526, 1.195782, 1.416335, 1.777666, 2.477606",\ + "1.056509, 1.246695, 1.466977, 1.828001, 2.527421",\ + "1.134180, 1.324303, 1.544337, 1.904875, 2.603319",\ + "1.343298, 1.533349, 1.753099, 2.112983, 2.810072",\ + "1.896648, 2.086668, 2.306295, 2.665835, 3.362187"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.150008, 0.150411, 0.151856, 0.156196, 0.165595",\ + "0.237385, 0.237630, 0.238497, 0.240747, 0.245517",\ + "0.400536, 0.400554, 0.400616, 0.401188, 0.402541",\ + "0.873945, 0.873960, 0.874011, 0.874290, 0.874930",\ + "2.149610, 2.149610, 2.149610, 2.149694, 2.149902",\ + "0.150008, 0.150411, 0.151856, 0.156196, 0.165595",\ + "0.237385, 0.237630, 0.238497, 0.240747, 0.245517",\ + "0.400536, 0.400554, 0.400616, 0.401188, 0.402541",\ + "0.873945, 0.873960, 0.874011, 0.874290, 0.874930",\ + "2.149610, 2.149610, 2.149610, 2.149694, 2.149902",\ + "0.150011, 0.150411, 0.151856, 0.156196, 0.165595",\ + "0.237387, 0.237630, 0.238497, 0.240747, 0.245517",\ + "0.400536, 0.400554, 0.400616, 0.401188, 0.402541",\ + "0.873945, 0.873960, 0.874011, 0.874290, 0.874930",\ + "2.149610, 2.149610, 2.149610, 2.149694, 2.149902",\ + "0.150016, 0.150412, 0.151859, 0.156208, 0.165618",\ + "0.237390, 0.237631, 0.238499, 0.240753, 0.245528",\ + "0.400537, 0.400554, 0.400616, 0.401190, 0.402544",\ + "0.873945, 0.873960, 0.874011, 0.874290, 0.874931",\ + "2.149610, 2.149610, 2.149610, 2.149695, 2.149903",\ + "0.150062, 0.150423, 0.151860, 0.156217, 0.165645",\ + "0.237418, 0.237637, 0.238499, 0.240757, 0.245542",\ + "0.400539, 0.400554, 0.400616, 0.401192, 0.402548",\ + "0.873947, 0.873960, 0.874011, 0.874291, 0.874933",\ + "2.149610, 2.149610, 2.149610, 2.149695, 2.149903"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.321064, 0.601616, 0.902007, 1.417819, 2.447771",\ + "0.356109, 0.636678, 0.937135, 1.453129, 2.483444",\ + "0.406657, 0.687216, 0.987647, 1.503613, 2.533873",\ + "0.536144, 0.816696, 1.117064, 1.632835, 2.662707",\ + "0.873984, 1.154534, 1.454850, 1.970470, 3.000039",\ + "0.409514, 0.689233, 0.989723, 1.504534, 2.533705",\ + "0.444559, 0.724295, 1.024851, 1.539844, 2.569378",\ + "0.495106, 0.774833, 1.075363, 1.590328, 2.619807",\ + "0.624593, 0.904313, 1.204779, 1.719550, 2.748641",\ + "0.962434, 1.242151, 1.542565, 2.057184, 3.085972",\ + "0.498914, 0.778364, 1.077690, 1.592179, 2.620660",\ + "0.533960, 0.813427, 1.112818, 1.627489, 2.656333",\ + "0.584508, 0.863965, 1.163329, 1.677973, 2.706762",\ + "0.713994, 0.993445, 1.292746, 1.807195, 2.835596",\ + "1.051835, 1.331282, 1.630532, 2.144830, 3.172927",\ + "0.562563, 0.844218, 1.141837, 1.656326, 2.684169",\ + "0.597610, 0.879281, 1.176965, 1.691636, 2.719842",\ + "0.648158, 0.929819, 1.227477, 1.742120, 2.770271",\ + "0.777645, 1.059298, 1.356893, 1.871342, 2.899105",\ + "1.115485, 1.397135, 1.694679, 2.208976, 3.236436",\ + "0.898997, 1.211173, 1.494183, 2.005997, 3.029625",\ + "0.934048, 1.246239, 1.529313, 2.041308, 3.065298",\ + "0.984598, 1.296772, 1.579825, 2.091792, 3.115727",\ + "1.114083, 1.426250, 1.709239, 2.221013, 3.244561",\ + "1.451924, 1.764086, 2.047024, 2.558647, 3.581892"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.072029, 0.072117, 0.072944, 0.075681, 0.081131",\ + "0.105035, 0.105045, 0.105444, 0.106813, 0.109537",\ + "0.191067, 0.191185, 0.191447, 0.191927, 0.192882",\ + "0.434550, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073125, 1.073633, 1.074646",\ + "0.072030, 0.072117, 0.072953, 0.075681, 0.081131",\ + "0.105035, 0.105045, 0.105449, 0.106813, 0.109537",\ + "0.191068, 0.191185, 0.191449, 0.191927, 0.192882",\ + "0.434554, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073126, 1.073633, 1.074646",\ + "0.072035, 0.072117, 0.072953, 0.075681, 0.081131",\ + "0.105035, 0.105045, 0.105449, 0.106813, 0.109537",\ + "0.191071, 0.191187, 0.191449, 0.191927, 0.192882",\ + "0.434564, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073126, 1.073633, 1.074646",\ + "0.072040, 0.072118, 0.072953, 0.075685, 0.081131",\ + "0.105036, 0.105045, 0.105449, 0.106814, 0.109537",\ + "0.191073, 0.191190, 0.191449, 0.191928, 0.192882",\ + "0.434574, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073127, 1.073634, 1.074646",\ + "0.072068, 0.072127, 0.072981, 0.075698, 0.081131",\ + "0.105040, 0.105046, 0.105463, 0.106821, 0.109537",\ + "0.191088, 0.191220, 0.191454, 0.191930, 0.192882",\ + "0.434635, 0.434688, 0.434688, 0.434688, 0.434688",\ + "1.072978, 1.072978, 1.073132, 1.073636, 1.074646"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[12]_redg_min*/ + +} /* end of pin tl_o[12] */ + +pin("tl_o[11]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.154883 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[11]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.480044, 0.757907, 1.049391, 1.544816, 2.535666",\ + "0.520846, 0.798709, 1.090193, 1.585618, 2.576470",\ + "0.596179, 0.874043, 1.165526, 1.660950, 2.651799",\ + "0.851223, 1.129087, 1.420574, 1.916010, 2.906884",\ + "1.776399, 2.054266, 2.345743, 2.841143, 3.831943",\ + "0.568493, 0.845495, 1.137043, 1.631531, 2.621600",\ + "0.609294, 0.886297, 1.177845, 1.672334, 2.662404",\ + "0.684628, 0.961631, 1.253178, 1.747665, 2.737732",\ + "0.939672, 1.216675, 1.508226, 2.002726, 2.992818",\ + "1.864848, 2.141854, 2.433396, 2.927858, 3.917876",\ + "0.657525, 0.934585, 1.225009, 1.719154, 2.708555",\ + "0.698327, 0.975387, 1.265811, 1.759956, 2.749359",\ + "0.773660, 1.050721, 1.341145, 1.835288, 2.824687",\ + "1.028704, 1.305765, 1.596192, 2.090348, 3.079773",\ + "1.953881, 2.230944, 2.521362, 3.015481, 4.004831",\ + "0.720671, 1.000379, 1.289153, 1.783067, 2.772064",\ + "0.761473, 1.041181, 1.329955, 1.823870, 2.812868",\ + "0.836807, 1.116515, 1.405289, 1.899202, 2.888196",\ + "1.091850, 1.371559, 1.660336, 2.154262, 3.143282",\ + "2.017027, 2.296738, 2.585506, 3.079395, 4.068340",\ + "1.053915, 1.366570, 1.641292, 2.132528, 3.117520",\ + "1.094717, 1.407372, 1.682094, 2.173331, 3.158324",\ + "1.170050, 1.482705, 1.757427, 2.248662, 3.233653",\ + "1.425094, 1.737749, 2.012475, 2.503723, 3.488738",\ + "2.350272, 2.662929, 2.937644, 3.428855, 4.413796"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\ + "2.469653, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\ + "2.469653, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\ + "2.469653, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691576, 0.691578, 0.691578, 0.691578",\ + "2.469654, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033098, 0.033098, 0.033098, 0.033098",\ + "0.082184, 0.082184, 0.082184, 0.082184, 0.082184",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691575, 0.691577, 0.691578, 0.691578, 0.691578",\ + "2.469654, 2.469654, 2.469654, 2.469654, 2.469654"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.577593, 0.759063, 0.958904, 1.285183, 1.919119",\ + "0.619104, 0.800573, 1.000415, 1.326696, 1.960636",\ + "0.678962, 0.860432, 1.060273, 1.386554, 2.020497",\ + "0.847206, 1.028676, 1.228518, 1.554798, 2.188738",\ + "1.428635, 1.610105, 1.809947, 2.136236, 2.770198",\ + "0.665008, 0.846447, 1.046407, 1.372488, 2.006473",\ + "0.706519, 0.887958, 1.087918, 1.414001, 2.047990",\ + "0.766377, 0.947816, 1.147776, 1.473860, 2.107850",\ + "0.934621, 1.116060, 1.316020, 1.642103, 2.276092",\ + "1.516050, 1.697490, 1.897449, 2.223541, 2.857552",\ + "0.745878, 0.926784, 1.126434, 1.452517, 2.086504",\ + "0.787388, 0.968295, 1.167944, 1.494029, 2.128021",\ + "0.847246, 1.028153, 1.227803, 1.553888, 2.187881",\ + "1.015491, 1.196397, 1.396047, 1.722131, 2.356123",\ + "1.596920, 1.777826, 1.977476, 2.303569, 2.937583",\ + "0.803511, 0.984332, 1.183978, 1.509762, 2.143152",\ + "0.845022, 1.025843, 1.225488, 1.551274, 2.184669",\ + "0.904880, 1.085701, 1.285347, 1.611133, 2.244529",\ + "1.073124, 1.253945, 1.453591, 1.779376, 2.412771",\ + "1.654553, 1.835374, 2.035020, 2.360815, 2.994231",\ + "1.105600, 1.289533, 1.487611, 1.812776, 2.445014",\ + "1.147110, 1.331044, 1.529122, 1.854289, 2.486530",\ + "1.206968, 1.390902, 1.588980, 1.914148, 2.546391",\ + "1.375213, 1.559146, 1.757225, 2.082391, 2.714632",\ + "1.956642, 2.140575, 2.338654, 2.663829, 3.296093"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\ + "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\ + "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\ + "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420",\ + "0.045173, 0.045173, 0.045173, 0.045173, 0.045173",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153692, 0.153692, 0.153692, 0.153692, 0.153692",\ + "0.429868, 0.429868, 0.429868, 0.429868, 0.429868",\ + "1.490308, 1.490308, 1.490308, 1.490340, 1.490420"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[11]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.480044, 0.757907, 1.049391, 1.544474, 2.533147",\ + "0.520846, 0.798709, 1.090193, 1.585276, 2.573951",\ + "0.596179, 0.874043, 1.165526, 1.660608, 2.649279",\ + "0.851223, 1.129087, 1.420574, 1.915668, 2.904364",\ + "1.776399, 2.054266, 2.345743, 2.840801, 3.829424",\ + "0.568493, 0.845495, 1.137043, 1.631189, 2.619081",\ + "0.609294, 0.886297, 1.177845, 1.671992, 2.659884",\ + "0.684628, 0.961631, 1.253178, 1.747323, 2.735213",\ + "0.939672, 1.216675, 1.508226, 2.002384, 2.990298",\ + "1.864848, 2.141854, 2.433396, 2.927516, 3.915357",\ + "0.657525, 0.934585, 1.225009, 1.718833, 2.706036",\ + "0.698327, 0.975387, 1.265811, 1.759635, 2.746840",\ + "0.773660, 1.050721, 1.341145, 1.834967, 2.822168",\ + "1.028704, 1.305765, 1.596192, 2.090027, 3.077253",\ + "1.953881, 2.230944, 2.521362, 3.015160, 4.002313",\ + "0.720671, 1.000379, 1.289153, 1.782954, 2.769545",\ + "0.761473, 1.041181, 1.329955, 1.823757, 2.810349",\ + "0.836807, 1.116515, 1.405289, 1.899088, 2.885677",\ + "1.091850, 1.371559, 1.660336, 2.154149, 3.140762",\ + "2.017027, 2.296738, 2.585506, 3.079281, 4.065822",\ + "1.053915, 1.366570, 1.641292, 2.132528, 3.115001",\ + "1.094717, 1.407372, 1.682094, 2.173331, 3.155805",\ + "1.170050, 1.482705, 1.757427, 2.248662, 3.231133",\ + "1.425094, 1.737749, 2.012475, 2.503723, 3.486218",\ + "2.350272, 2.662929, 2.937644, 3.428855, 4.411278"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469630, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469631, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469633, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469634, 2.469654, 2.469654, 2.469654, 2.469654",\ + "0.033097, 0.033097, 0.033097, 0.033097, 0.033097",\ + "0.082175, 0.082175, 0.082175, 0.082175, 0.082175",\ + "0.206840, 0.206841, 0.206841, 0.206841, 0.206842",\ + "0.691460, 0.691460, 0.691460, 0.691460, 0.691460",\ + "2.469645, 2.469654, 2.469654, 2.469654, 2.469654"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.577593, 0.758693, 0.958244, 1.284509, 1.918007",\ + "0.619104, 0.800204, 0.999755, 1.326021, 1.959524",\ + "0.678962, 0.860062, 1.059613, 1.385880, 2.019384",\ + "0.847206, 1.028306, 1.227857, 1.554123, 2.187625",\ + "1.428635, 1.609735, 1.809286, 2.135561, 2.769086",\ + "0.665008, 0.846012, 1.045525, 1.371814, 2.005360",\ + "0.706519, 0.887523, 1.087036, 1.413326, 2.046877",\ + "0.766377, 0.947381, 1.146894, 1.473185, 2.106737",\ + "0.934621, 1.115625, 1.315138, 1.641428, 2.274979",\ + "1.516050, 1.697054, 1.896567, 2.222867, 2.856439",\ + "0.745878, 0.926348, 1.125552, 1.451842, 2.085392",\ + "0.787388, 0.967859, 1.167063, 1.493355, 2.126909",\ + "0.847246, 1.027717, 1.226921, 1.553214, 2.186769",\ + "1.015491, 1.195961, 1.395165, 1.721457, 2.355011",\ + "1.596920, 1.777390, 1.976594, 2.302895, 2.936471",\ + "0.803511, 0.984182, 1.183296, 1.509360, 2.142581",\ + "0.845022, 1.025692, 1.224806, 1.550872, 2.184098",\ + "0.904880, 1.085551, 1.284665, 1.610731, 2.243959",\ + "1.073124, 1.253795, 1.452909, 1.778975, 2.412200",\ + "1.654553, 1.835224, 2.034338, 2.360413, 2.993660",\ + "1.105600, 1.289533, 1.486960, 1.812607, 2.445014",\ + "1.147110, 1.331044, 1.528471, 1.854120, 2.486530",\ + "1.206968, 1.390902, 1.588329, 1.913979, 2.546391",\ + "1.375213, 1.559146, 1.756574, 2.082222, 2.714632",\ + "1.956642, 2.140575, 2.338003, 2.663660, 3.296093"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490338, 1.490419",\ + "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490338, 1.490419",\ + "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490338, 1.490419",\ + "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490339, 1.490419",\ + "0.045164, 0.045164, 0.045164, 0.045164, 0.045164",\ + "0.078561, 0.078561, 0.078561, 0.078562, 0.078566",\ + "0.153612, 0.153612, 0.153612, 0.153612, 0.153612",\ + "0.429864, 0.429864, 0.429864, 0.429864, 0.429864",\ + "1.490306, 1.490306, 1.490306, 1.490339, 1.490420"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[11]_redg_min*/ + +} /* end of pin tl_o[11] */ + +pin("tl_o[10]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[10]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.364012, 0.625791, 0.912362, 1.416686, 2.425334",\ + "0.413794, 0.675738, 0.964329, 1.475067, 2.496546",\ + "0.489422, 0.751529, 1.041528, 1.556366, 2.586045",\ + "0.695293, 0.957830, 1.249004, 1.765727, 2.799173",\ + "1.246075, 1.508922, 1.800327, 2.315899, 3.347043",\ + "0.451427, 0.713333, 1.000043, 1.503402, 2.511267",\ + "0.501209, 0.763281, 1.052029, 1.561783, 2.582479",\ + "0.576836, 0.839074, 1.129242, 1.643082, 2.671978",\ + "0.782708, 1.045378, 1.336724, 1.852442, 2.885106",\ + "1.333490, 1.596474, 1.888044, 2.402615, 3.432977",\ + "0.533466, 0.802315, 1.088010, 1.591024, 2.598222",\ + "0.583252, 0.852266, 1.139997, 1.649405, 2.669434",\ + "0.658880, 0.928062, 1.217209, 1.730705, 2.758933",\ + "0.864753, 1.134376, 1.424692, 1.940065, 2.972061",\ + "1.415530, 1.685480, 1.976011, 2.490237, 3.519932",\ + "0.596367, 0.867953, 1.152155, 1.654938, 2.661731",\ + "0.646156, 0.917908, 1.204143, 1.713319, 2.732943",\ + "0.721785, 0.993709, 1.281356, 1.794618, 2.822442",\ + "0.927659, 1.200036, 1.488839, 2.003978, 3.035570",\ + "1.478432, 1.751152, 2.040158, 2.554151, 3.583441",\ + "0.928059, 1.232317, 1.504384, 2.004435, 3.007188",\ + "0.977868, 1.282318, 1.556437, 2.062843, 3.078399",\ + "1.053501, 1.358177, 1.633692, 2.144160, 3.167898",\ + "1.259380, 1.564660, 1.841193, 2.353528, 3.381027",\ + "1.810129, 2.115913, 2.392501, 2.903695, 3.928897"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.177438, 0.178519, 0.189473, 0.223901, 0.292757",\ + "0.251359, 0.253407, 0.263275, 0.290387, 0.344610",\ + "0.412697, 0.412697, 0.415313, 0.424472, 0.442790",\ + "0.885478, 0.885674, 0.886375, 0.887778, 0.890585",\ + "2.162748, 2.162748, 2.162938, 2.163605, 2.164938",\ + "0.177438, 0.178526, 0.189583, 0.223901, 0.292757",\ + "0.251359, 0.253420, 0.263361, 0.290387, 0.344610",\ + "0.412697, 0.412697, 0.415342, 0.424472, 0.442790",\ + "0.885478, 0.885676, 0.886379, 0.887778, 0.890585",\ + "2.162748, 2.162748, 2.162940, 2.163605, 2.164938",\ + "0.177475, 0.178542, 0.189585, 0.223901, 0.292757",\ + "0.251427, 0.253451, 0.263362, 0.290387, 0.344610",\ + "0.412697, 0.412697, 0.415343, 0.424472, 0.442790",\ + "0.885478, 0.885680, 0.886380, 0.887778, 0.890585",\ + "2.162748, 2.162748, 2.162940, 2.163605, 2.164938",\ + "0.177499, 0.178566, 0.189590, 0.223901, 0.292757",\ + "0.251473, 0.253495, 0.263367, 0.290387, 0.344610",\ + "0.412697, 0.412697, 0.415344, 0.424472, 0.442790",\ + "0.885478, 0.885687, 0.886380, 0.887778, 0.890585",\ + "2.162748, 2.162748, 2.162940, 2.163605, 2.164938",\ + "0.177651, 0.178840, 0.189940, 0.224044, 0.292757",\ + "0.251761, 0.254016, 0.263642, 0.290499, 0.344610",\ + "0.412697, 0.412697, 0.415437, 0.424510, 0.442790",\ + "0.885478, 0.885760, 0.886394, 0.887784, 0.890585",\ + "2.162748, 2.162748, 2.162947, 2.163608, 2.164938"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.312852, 0.568984, 0.862555, 1.382336, 2.421899",\ + "0.348118, 0.610654, 0.902338, 1.419180, 2.452865",\ + "0.406005, 0.669261, 0.960734, 1.473580, 2.499271",\ + "0.536962, 0.800144, 1.091137, 1.602535, 2.625331",\ + "0.874185, 1.136967, 1.427801, 1.940429, 2.965686",\ + "0.400266, 0.656542, 0.950284, 1.469051, 2.507832",\ + "0.435533, 0.698205, 0.990058, 1.505895, 2.538798",\ + "0.493420, 0.756819, 1.048442, 1.560295, 2.585205",\ + "0.624377, 0.887700, 1.178840, 1.689250, 2.711264",\ + "0.961600, 1.224520, 1.515508, 2.027145, 3.051620",\ + "0.481136, 0.745561, 1.038252, 1.556674, 2.594787",\ + "0.517546, 0.787210, 1.078026, 1.593518, 2.625753",\ + "0.575445, 0.845837, 1.136409, 1.647918, 2.672160",\ + "0.706398, 0.976717, 1.266807, 1.776872, 2.798219",\ + "1.043615, 1.313530, 1.603475, 2.114767, 3.138575",\ + "0.538770, 0.811253, 1.102400, 1.620588, 2.658296",\ + "0.580430, 0.852880, 1.142173, 1.657432, 2.689262",\ + "0.638337, 0.911526, 1.200556, 1.711832, 2.735669",\ + "0.769288, 1.042406, 1.330954, 1.840786, 2.861728",\ + "1.106500, 1.379207, 1.667622, 2.178681, 3.202084",\ + "0.869562, 1.176250, 1.454786, 1.970150, 3.003752",\ + "0.912016, 1.217620, 1.494529, 2.006981, 3.034719",\ + "0.969972, 1.276495, 1.552871, 2.061365, 3.081125",\ + "1.100910, 1.407358, 1.683254, 2.190313, 3.207185",\ + "1.438092, 1.744035, 2.019935, 2.528213, 3.547540"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.081554, 0.088992, 0.106415, 0.139136, 0.204579",\ + "0.124645, 0.129773, 0.146146, 0.179503, 0.246217",\ + "0.203924, 0.205651, 0.213739, 0.234366, 0.275621",\ + "0.443609, 0.443974, 0.447191, 0.457130, 0.477008",\ + "1.100873, 1.101320, 1.101850, 1.102085, 1.102555",\ + "0.081554, 0.089042, 0.106519, 0.139136, 0.204579",\ + "0.124645, 0.129815, 0.146252, 0.179503, 0.246217",\ + "0.203924, 0.205665, 0.213805, 0.234366, 0.275621",\ + "0.443609, 0.443976, 0.447223, 0.457130, 0.477008",\ + "1.100873, 1.101323, 1.101851, 1.102085, 1.102555",\ + "0.081568, 0.089158, 0.106521, 0.139136, 0.204579",\ + "0.124713, 0.129914, 0.146254, 0.179503, 0.246217",\ + "0.203955, 0.205697, 0.213806, 0.234366, 0.275621",\ + "0.443622, 0.443982, 0.447223, 0.457130, 0.477008",\ + "1.100888, 1.101329, 1.101851, 1.102085, 1.102555",\ + "0.081595, 0.089328, 0.106526, 0.139136, 0.204579",\ + "0.124759, 0.130058, 0.146259, 0.179503, 0.246217",\ + "0.203975, 0.205743, 0.213809, 0.234366, 0.275621",\ + "0.443630, 0.443990, 0.447225, 0.457130, 0.477008",\ + "1.100898, 1.101339, 1.101851, 1.102085, 1.102555",\ + "0.082871, 0.091307, 0.106858, 0.139272, 0.204579",\ + "0.125047, 0.131735, 0.146598, 0.179642, 0.246217",\ + "0.204103, 0.206281, 0.214019, 0.234452, 0.275621",\ + "0.443681, 0.444082, 0.447326, 0.457171, 0.477008",\ + "1.100961, 1.101453, 1.101854, 1.102086, 1.102555"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_2703*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.350851, 0.591855, 0.864128, 1.320281, 2.232588",\ + "0.400592, 0.641701, 0.915140, 1.374804, 2.294134",\ + "0.476229, 0.717426, 0.992120, 1.455680, 2.382801",\ + "0.682141, 0.923562, 1.199150, 1.664642, 2.595626",\ + "1.233045, 1.474598, 1.750161, 2.214853, 3.144235",\ + "0.438261, 0.679403, 0.951654, 1.406996, 2.318522",\ + "0.488002, 0.729251, 1.002677, 1.461519, 2.380068",\ + "0.563639, 0.804976, 1.079670, 1.542395, 2.468735",\ + "0.769551, 1.011115, 1.286705, 1.751357, 2.681560",\ + "1.320455, 1.562152, 1.837715, 2.301567, 3.230169",\ + "0.519097, 0.768378, 1.039617, 1.494618, 2.405477",\ + "0.568838, 0.818228, 1.090640, 1.549141, 2.467023",\ + "0.644474, 0.893955, 1.167633, 1.630017, 2.555690",\ + "0.850399, 1.100099, 1.374669, 1.838978, 2.768515",\ + "1.401325, 1.651139, 1.925678, 2.389189, 3.317124",\ + "0.576709, 0.834005, 1.103754, 1.558531, 2.468986",\ + "0.626450, 0.883858, 1.154778, 1.613054, 2.530532",\ + "0.702087, 0.959588, 1.231772, 1.693930, 2.619199",\ + "0.908034, 1.165738, 1.438808, 1.902892, 2.832024",\ + "1.459002, 1.716783, 1.989817, 2.453102, 3.380633",\ + "0.898537, 1.198301, 1.455491, 1.907824, 2.814442",\ + "0.948280, 1.248191, 1.506551, 1.962362, 2.875988",\ + "1.023916, 1.323954, 1.583584, 2.043254, 2.964655",\ + "1.229826, 1.530187, 1.790640, 2.252224, 3.177480",\ + "1.780725, 2.081283, 2.341641, 2.802431, 3.726089"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.177532, 0.178920, 0.189751, 0.222197, 0.287089",\ + "0.251535, 0.254167, 0.264114, 0.288993, 0.338750",\ + "0.412948, 0.412948, 0.415205, 0.423013, 0.438629",\ + "0.885646, 0.885671, 0.886007, 0.887039, 0.889103",\ + "2.163153, 2.163153, 2.163261, 2.163636, 2.164385",\ + "0.177532, 0.178929, 0.189854, 0.222197, 0.287089",\ + "0.251535, 0.254184, 0.264193, 0.288993, 0.338750",\ + "0.412948, 0.412948, 0.415229, 0.423013, 0.438629",\ + "0.885646, 0.885672, 0.886011, 0.887039, 0.889103",\ + "2.163153, 2.163153, 2.163263, 2.163636, 2.164385",\ + "0.177534, 0.178950, 0.189855, 0.222197, 0.287089",\ + "0.251540, 0.254224, 0.264194, 0.288993, 0.338750",\ + "0.412948, 0.412948, 0.415230, 0.423013, 0.438629",\ + "0.885646, 0.885672, 0.886011, 0.887039, 0.889103",\ + "2.163153, 2.163153, 2.163263, 2.163636, 2.164385",\ + "0.177539, 0.178981, 0.189861, 0.222197, 0.287089",\ + "0.251549, 0.254282, 0.264198, 0.288993, 0.338750",\ + "0.412948, 0.412948, 0.415231, 0.423013, 0.438629",\ + "0.885646, 0.885673, 0.886011, 0.887039, 0.889103",\ + "2.163153, 2.163153, 2.163263, 2.163636, 2.164385",\ + "0.177778, 0.179340, 0.190190, 0.222331, 0.287089",\ + "0.252003, 0.254964, 0.264451, 0.289096, 0.338750",\ + "0.412948, 0.412948, 0.415310, 0.423045, 0.438629",\ + "0.885646, 0.885682, 0.886021, 0.887043, 0.889103",\ + "2.163153, 2.163153, 2.163266, 2.163637, 2.164385"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.307193, 0.533242, 0.809521, 1.279856, 2.220526",\ + "0.336644, 0.576689, 0.852349, 1.318694, 2.251385",\ + "0.393241, 0.634932, 0.911048, 1.376848, 2.308447",\ + "0.524233, 0.765871, 1.043018, 1.512641, 2.451889",\ + "0.861499, 1.102901, 1.379688, 1.849255, 2.788391",\ + "0.394603, 0.620790, 0.897092, 1.366570, 2.306459",\ + "0.424054, 0.664240, 0.939907, 1.405409, 2.337319",\ + "0.480651, 0.722487, 0.998605, 1.463562, 2.394381",\ + "0.611643, 0.853426, 1.130586, 1.599356, 2.537823",\ + "0.948909, 1.190453, 1.467256, 1.935970, 2.874325",\ + "0.475519, 0.709763, 0.985056, 1.454192, 2.393414",\ + "0.504970, 0.753222, 1.027871, 1.493031, 2.424274",\ + "0.561503, 0.811478, 1.086568, 1.551184, 2.481336",\ + "0.692478, 0.942415, 1.218550, 1.686978, 2.624778",\ + "1.029784, 1.279438, 1.555220, 2.023592, 2.961280",\ + "0.533285, 0.775388, 1.049196, 1.518106, 2.456923",\ + "0.562736, 0.818858, 1.092010, 1.556944, 2.487783",\ + "0.619148, 0.877127, 1.150707, 1.615098, 2.544845",\ + "0.750090, 1.008062, 1.282690, 1.750891, 2.688287",\ + "1.087471, 1.345078, 1.619360, 2.087505, 3.024789",\ + "0.839984, 1.139662, 1.401077, 1.867458, 2.802380",\ + "0.883084, 1.183263, 1.443850, 1.906280, 2.833239",\ + "0.940909, 1.241684, 1.502542, 1.964431, 2.890301",\ + "1.071899, 1.372601, 1.634564, 2.100240, 3.033743",\ + "1.409163, 1.709532, 1.971233, 2.436854, 3.370245"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.079414, 0.084257, 0.099312, 0.127519, 0.183935",\ + "0.124385, 0.127318, 0.139681, 0.167608, 0.223461",\ + "0.203732, 0.204755, 0.210826, 0.226691, 0.258421",\ + "0.443641, 0.444109, 0.446299, 0.452176, 0.463930",\ + "1.100911, 1.101486, 1.102125, 1.102253, 1.102511",\ + "0.079414, 0.084301, 0.099401, 0.127519, 0.183935",\ + "0.124385, 0.127346, 0.139769, 0.167608, 0.223461",\ + "0.203732, 0.204765, 0.210876, 0.226691, 0.258421",\ + "0.443641, 0.444112, 0.446317, 0.452176, 0.463930",\ + "1.100911, 1.101489, 1.102125, 1.102253, 1.102511",\ + "0.079415, 0.084402, 0.099402, 0.127519, 0.183935",\ + "0.124385, 0.127408, 0.139771, 0.167608, 0.223461",\ + "0.203732, 0.204786, 0.210877, 0.226691, 0.258421",\ + "0.443642, 0.444120, 0.446318, 0.452176, 0.463930",\ + "1.100913, 1.101498, 1.102125, 1.102253, 1.102511",\ + "0.079417, 0.084547, 0.099407, 0.127519, 0.183935",\ + "0.124385, 0.127499, 0.139776, 0.167608, 0.223461",\ + "0.203733, 0.204818, 0.210879, 0.226691, 0.258421",\ + "0.443643, 0.444130, 0.446319, 0.452176, 0.463930",\ + "1.100914, 1.101511, 1.102125, 1.102253, 1.102511",\ + "0.079511, 0.086252, 0.099693, 0.127636, 0.183935",\ + "0.124397, 0.128559, 0.140059, 0.167723, 0.223461",\ + "0.203741, 0.205184, 0.211040, 0.226757, 0.258421",\ + "0.443724, 0.444251, 0.446378, 0.452200, 0.463930",\ + "1.101013, 1.101659, 1.102126, 1.102254, 1.102511"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_2585*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.331228, 0.527324, 0.786001, 1.224167, 2.100501",\ + "0.382369, 0.578501, 0.836813, 1.274472, 2.149791",\ + "0.460186, 0.652490, 0.910342, 1.347469, 2.221725",\ + "0.669327, 0.853217, 1.110120, 1.545833, 2.417260",\ + "1.222502, 1.402990, 1.654377, 2.088484, 2.956696",\ + "0.418630, 0.614835, 0.873467, 1.310880, 2.186435",\ + "0.469770, 0.666010, 0.924278, 1.361185, 2.235725",\ + "0.547588, 0.739998, 0.997805, 1.434183, 2.307659",\ + "0.756729, 0.940720, 1.197578, 1.632546, 2.503194",\ + "1.309904, 1.490380, 1.741831, 2.175197, 3.042630",\ + "0.499484, 0.703690, 0.961427, 1.398501, 2.273390",\ + "0.550625, 0.754862, 1.012238, 1.448806, 2.322680",\ + "0.628442, 0.828845, 1.085765, 1.521803, 2.394614",\ + "0.837583, 1.029560, 1.285538, 1.720167, 2.590149",\ + "1.390758, 1.574844, 1.829791, 2.262817, 3.129585",\ + "0.557217, 0.769141, 1.025562, 1.462414, 2.336899",\ + "0.608358, 0.820308, 1.076372, 1.512718, 2.386189",\ + "0.686176, 0.894284, 1.149899, 1.585716, 2.458123",\ + "0.895316, 1.094988, 1.349672, 1.784079, 2.653658",\ + "1.448492, 1.640260, 1.893925, 2.326730, 3.193094",\ + "0.860852, 1.131485, 1.377112, 1.811626, 2.682355",\ + "0.911997, 1.182598, 1.427917, 1.861928, 2.731645",\ + "0.989815, 1.256499, 1.501439, 1.934923, 2.803579",\ + "1.198957, 1.457069, 1.701197, 2.133281, 2.999114",\ + "1.752135, 2.002200, 2.245434, 2.675925, 3.538550"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.247574, 0.253107, 0.265836, 0.292486, 0.345785",\ + "0.313887, 0.316030, 0.323178, 0.341027, 0.376725",\ + "0.435753, 0.438083, 0.443130, 0.454659, 0.477717",\ + "0.887719, 0.887719, 0.887745, 0.887834, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\ + "0.247574, 0.253139, 0.265920, 0.292486, 0.345785",\ + "0.313887, 0.316042, 0.323234, 0.341027, 0.376725",\ + "0.435753, 0.438094, 0.443166, 0.454659, 0.477717",\ + "0.887719, 0.887719, 0.887746, 0.887834, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\ + "0.247586, 0.253211, 0.265921, 0.292486, 0.345785",\ + "0.313891, 0.316070, 0.323235, 0.341027, 0.376725",\ + "0.435759, 0.438118, 0.443167, 0.454659, 0.477717",\ + "0.887719, 0.887719, 0.887746, 0.887834, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\ + "0.247608, 0.253315, 0.265926, 0.292486, 0.345785",\ + "0.313900, 0.316110, 0.323238, 0.341027, 0.376725",\ + "0.435772, 0.438153, 0.443169, 0.454659, 0.477717",\ + "0.887719, 0.887719, 0.887746, 0.887834, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595",\ + "0.247822, 0.254533, 0.266196, 0.292595, 0.345785",\ + "0.313983, 0.316581, 0.323419, 0.341101, 0.376725",\ + "0.435894, 0.438565, 0.443286, 0.454706, 0.477717",\ + "0.887719, 0.887719, 0.887747, 0.887835, 0.888012",\ + "2.165595, 2.165595, 2.165595, 2.165595, 2.165595"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.262843, 0.528242, 0.786656, 1.223429, 2.096977",\ + "0.297860, 0.563309, 0.821748, 1.258583, 2.132253",\ + "0.348398, 0.613835, 0.872220, 1.308997, 2.182551",\ + "0.477894, 0.743312, 1.001644, 1.438265, 2.311508",\ + "0.815730, 1.081145, 1.339443, 1.775996, 2.649102",\ + "0.351215, 0.615754, 0.874118, 1.310142, 2.182910",\ + "0.386233, 0.650820, 0.909210, 1.345296, 2.218187",\ + "0.436771, 0.701346, 0.959682, 1.395710, 2.268485",\ + "0.566267, 0.830823, 1.089105, 1.524978, 2.397442",\ + "0.904103, 1.168656, 1.426904, 1.862709, 2.735036",\ + "0.441060, 0.704611, 0.962078, 1.397763, 2.269865",\ + "0.476082, 0.739678, 0.997171, 1.432917, 2.305142",\ + "0.526621, 0.790203, 1.047642, 1.483330, 2.355440",\ + "0.656116, 0.919680, 1.177066, 1.612599, 2.484397",\ + "0.993953, 1.257513, 1.514864, 1.950330, 2.821991",\ + "0.505420, 0.770065, 1.026212, 1.461676, 2.333374",\ + "0.540445, 0.805132, 1.061305, 1.496829, 2.368651",\ + "0.590985, 0.855656, 1.111776, 1.547243, 2.418949",\ + "0.720478, 0.985133, 1.241200, 1.676511, 2.547906",\ + "1.058316, 1.322965, 1.578998, 2.014242, 2.885500",\ + "0.846347, 1.132446, 1.377748, 1.810882, 2.678830",\ + "0.881392, 1.167515, 1.412841, 1.846036, 2.714107",\ + "0.931940, 1.218030, 1.463312, 1.896449, 2.764405",\ + "1.061427, 1.347505, 1.592734, 2.025717, 2.893362",\ + "1.399268, 1.685334, 1.930532, 2.363448, 3.230956"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.080673, 0.084979, 0.095299, 0.118135, 0.163806",\ + "0.121691, 0.122534, 0.126916, 0.139600, 0.164968",\ + "0.211121, 0.211686, 0.213778, 0.219384, 0.230596",\ + "0.447776, 0.448001, 0.448970, 0.451208, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\ + "0.080714, 0.085004, 0.095371, 0.118135, 0.163806",\ + "0.121700, 0.122539, 0.126956, 0.139600, 0.164968",\ + "0.211127, 0.211689, 0.213796, 0.219384, 0.230596",\ + "0.447776, 0.448003, 0.448977, 0.451208, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\ + "0.080840, 0.085056, 0.095372, 0.118135, 0.163806",\ + "0.121728, 0.122548, 0.126957, 0.139600, 0.164968",\ + "0.211145, 0.211695, 0.213796, 0.219384, 0.230596",\ + "0.447776, 0.448008, 0.448977, 0.451208, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\ + "0.080962, 0.085133, 0.095376, 0.118135, 0.163806",\ + "0.121755, 0.122562, 0.126959, 0.139600, 0.164968",\ + "0.211163, 0.211704, 0.213797, 0.219384, 0.230596",\ + "0.447776, 0.448014, 0.448977, 0.451208, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948",\ + "0.081743, 0.086029, 0.095607, 0.118229, 0.163806",\ + "0.121930, 0.122722, 0.127087, 0.139652, 0.164968",\ + "0.211276, 0.211814, 0.213854, 0.219407, 0.230596",\ + "0.447776, 0.448092, 0.449000, 0.451217, 0.455684",\ + "1.099948, 1.099948, 1.099948, 1.099948, 1.099948"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_2468*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.515413, 0.691814, 0.891527, 1.333812, 2.218381",\ + "0.561951, 0.738352, 0.942909, 1.385434, 2.270486",\ + "0.647617, 0.824017, 1.044838, 1.487336, 2.372332",\ + "0.870983, 1.047384, 1.281978, 1.724502, 2.609548",\ + "1.434991, 1.611392, 1.857594, 2.300149, 3.185259",\ + "0.602824, 0.779196, 0.979010, 1.420527, 2.304315",\ + "0.649362, 0.825734, 1.030392, 1.472149, 2.356420",\ + "0.735027, 0.911399, 1.132321, 1.574051, 2.458265",\ + "0.958394, 1.134766, 1.369462, 1.811216, 2.695482",\ + "1.522402, 1.698774, 1.945078, 2.386864, 3.271193",\ + "0.683657, 0.859530, 1.066972, 1.508148, 2.391270",\ + "0.730195, 0.906068, 1.118354, 1.559771, 2.443375",\ + "0.815861, 0.991733, 1.220284, 1.661672, 2.545220",\ + "1.039228, 1.215100, 1.457424, 1.898838, 2.782437",\ + "1.603236, 1.779108, 2.033040, 2.474486, 3.358148",\ + "0.741263, 0.917078, 1.131107, 1.572062, 2.454779",\ + "0.787801, 0.963617, 1.182490, 1.623684, 2.506884",\ + "0.873466, 1.049282, 1.284419, 1.725586, 2.608729",\ + "1.096833, 1.272649, 1.521559, 1.962752, 2.845946",\ + "1.660841, 1.842122, 2.097176, 2.538399, 3.421657",\ + "1.043307, 1.237664, 1.482704, 1.921298, 2.800235",\ + "1.089845, 1.288972, 1.534089, 1.972921, 2.852340",\ + "1.175511, 1.390910, 1.636018, 2.074823, 2.954185",\ + "1.398878, 1.628042, 1.873158, 2.311989, 3.191402",\ + "1.962886, 2.203649, 2.448775, 2.887636, 3.767113"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\ + "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\ + "2.162771, 2.162771, 2.162787, 2.162833, 2.162925",\ + "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\ + "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\ + "2.162771, 2.162771, 2.162787, 2.162833, 2.162925",\ + "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\ + "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\ + "2.162771, 2.162771, 2.162787, 2.162833, 2.162925",\ + "0.052252, 0.052252, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174387, 0.174377, 0.174356, 0.174314",\ + "0.378093, 0.378093, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885671, 0.885661, 0.885629, 0.885567",\ + "2.162771, 2.162772, 2.162787, 2.162833, 2.162925",\ + "0.052252, 0.052255, 0.052266, 0.052296, 0.052356",\ + "0.174387, 0.174384, 0.174376, 0.174356, 0.174314",\ + "0.378093, 0.378087, 0.378069, 0.378020, 0.377921",\ + "0.885671, 0.885670, 0.885660, 0.885629, 0.885567",\ + "2.162771, 2.162773, 2.162788, 2.162833, 2.162925"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.453647, 0.675841, 0.933001, 1.375582, 2.260746",\ + "0.507082, 0.698390, 0.955556, 1.398159, 2.283364",\ + "0.567945, 0.744346, 0.996821, 1.439418, 2.324611",\ + "0.702647, 0.879047, 1.118872, 1.561445, 2.446589",\ + "1.049097, 1.225497, 1.451556, 1.894090, 2.779158",\ + "0.541058, 0.763317, 1.020484, 1.462297, 2.346680",\ + "0.594493, 0.785866, 1.043040, 1.484873, 2.369298",\ + "0.655356, 0.831728, 1.084305, 1.526132, 2.410545",\ + "0.790057, 0.966429, 1.206356, 1.648159, 2.532523",\ + "1.136508, 1.312880, 1.539039, 1.980805, 2.865092",\ + "0.621891, 0.852130, 1.108447, 1.549919, 2.433635",\ + "0.675327, 0.874679, 1.131002, 1.572495, 2.456253",\ + "0.736189, 0.915945, 1.172267, 1.613754, 2.497500",\ + "0.870891, 1.046763, 1.294318, 1.735781, 2.619478",\ + "1.217341, 1.393214, 1.627002, 2.068427, 2.952047",\ + "0.679497, 0.917520, 1.172582, 1.613832, 2.497144",\ + "0.732932, 0.940069, 1.195138, 1.636409, 2.519762",\ + "0.793795, 0.981336, 1.236402, 1.677668, 2.561009",\ + "0.928497, 1.104312, 1.358454, 1.799695, 2.682987",\ + "1.274947, 1.450762, 1.691137, 2.132340, 3.015556",\ + "0.991265, 1.279047, 1.524182, 1.963070, 2.842600",\ + "1.034976, 1.301596, 1.546737, 1.985646, 2.865218",\ + "1.095839, 1.342862, 1.588002, 2.026905, 2.906465",\ + "1.230541, 1.464921, 1.710053, 2.148932, 3.028443",\ + "1.576991, 1.797617, 2.042736, 2.481577, 3.361012"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.060254, 0.060270, 0.060353, 0.060563, 0.060983",\ + "0.114289, 0.114310, 0.114425, 0.114712, 0.115288",\ + "0.199967, 0.199967, 0.200091, 0.200354, 0.200879",\ + "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\ + "0.060254, 0.060270, 0.060354, 0.060563, 0.060983",\ + "0.114289, 0.114310, 0.114425, 0.114712, 0.115288",\ + "0.199967, 0.199967, 0.200092, 0.200354, 0.200879",\ + "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\ + "0.060254, 0.060270, 0.060354, 0.060563, 0.060983",\ + "0.114289, 0.114311, 0.114426, 0.114712, 0.115288",\ + "0.199967, 0.199987, 0.200092, 0.200354, 0.200879",\ + "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\ + "0.060254, 0.060271, 0.060354, 0.060563, 0.060983",\ + "0.114289, 0.114311, 0.114426, 0.114712, 0.115288",\ + "0.199967, 0.199988, 0.200092, 0.200354, 0.200879",\ + "0.445518, 0.445518, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101422, 1.101415, 1.101402, 1.101375",\ + "0.060254, 0.060277, 0.060356, 0.060564, 0.060983",\ + "0.114289, 0.114319, 0.114428, 0.114714, 0.115288",\ + "0.199967, 0.199995, 0.200095, 0.200355, 0.200879",\ + "0.445518, 0.445521, 0.445532, 0.445561, 0.445620",\ + "1.101422, 1.101420, 1.101415, 1.101402, 1.101375"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.248860, 0.467650, 0.646178, 0.935763, 1.497723",\ + "0.314404, 0.533194, 0.711724, 1.001313, 1.563285",\ + "0.400894, 0.619685, 0.798218, 1.087823, 1.649829",\ + "0.616887, 0.835682, 1.014242, 1.303952, 1.866190",\ + "1.171447, 1.390243, 1.568813, 1.858561, 2.420885",\ + "0.337260, 0.554969, 0.733459, 1.023068, 1.585076",\ + "0.402804, 0.620513, 0.799004, 1.088619, 1.650638",\ + "0.489294, 0.707003, 0.885499, 1.175128, 1.737183",\ + "0.705288, 0.923001, 1.101523, 1.391257, 1.953543",\ + "1.259847, 1.477562, 1.656094, 1.945866, 2.508239",\ + "0.426158, 0.635305, 0.813486, 1.103096, 1.665108",\ + "0.491702, 0.700850, 0.879031, 1.168647, 1.730670",\ + "0.578191, 0.787340, 0.965526, 1.255157, 1.817214",\ + "0.794185, 1.003338, 1.181550, 1.471285, 2.033575",\ + "1.348745, 1.557899, 1.736121, 2.025895, 2.588270",\ + "0.489181, 0.693123, 0.871180, 1.160527, 1.722125",\ + "0.554726, 0.758668, 0.936725, 1.226078, 1.787687",\ + "0.641215, 0.845158, 1.023220, 1.312588, 1.874232",\ + "0.857210, 1.061156, 1.239244, 1.528717, 2.090593",\ + "1.411770, 1.615717, 1.793815, 2.083326, 2.645288",\ + "0.817972, 0.998369, 1.174837, 1.463701, 2.024349",\ + "0.883517, 1.063914, 1.240382, 1.529251, 2.089911",\ + "0.970006, 1.150404, 1.326877, 1.615761, 2.176455",\ + "1.186001, 1.366402, 1.542901, 1.831890, 2.392817",\ + "1.740560, 1.920963, 2.097472, 2.386500, 2.947513"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.135658, 0.135697, 0.135954, 0.136439, 0.137406",\ + "0.233360, 0.233354, 0.233337, 0.233240, 0.233017",\ + "0.397359, 0.397363, 0.397387, 0.397480, 0.397688",\ + "0.873501, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140095, 2.140101, 2.140141, 2.140298, 2.140647",\ + "0.135659, 0.135697, 0.135954, 0.136439, 0.137406",\ + "0.233360, 0.233354, 0.233337, 0.233240, 0.233017",\ + "0.397359, 0.397363, 0.397387, 0.397480, 0.397688",\ + "0.873501, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140095, 2.140101, 2.140141, 2.140298, 2.140647",\ + "0.135662, 0.135697, 0.135954, 0.136439, 0.137406",\ + "0.233359, 0.233354, 0.233337, 0.233240, 0.233017",\ + "0.397360, 0.397363, 0.397387, 0.397480, 0.397688",\ + "0.873500, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140095, 2.140101, 2.140141, 2.140298, 2.140647",\ + "0.135665, 0.135698, 0.135954, 0.136441, 0.137409",\ + "0.233359, 0.233354, 0.233337, 0.233240, 0.233016",\ + "0.397360, 0.397363, 0.397387, 0.397480, 0.397689",\ + "0.873500, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140096, 2.140101, 2.140141, 2.140298, 2.140648",\ + "0.135663, 0.135699, 0.135954, 0.136442, 0.137411",\ + "0.233359, 0.233354, 0.233337, 0.233240, 0.233016",\ + "0.397360, 0.397363, 0.397387, 0.397480, 0.397689",\ + "0.873500, 0.873500, 0.873498, 0.873489, 0.873469",\ + "2.140096, 2.140101, 2.140141, 2.140299, 2.140649"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.265941, 0.478440, 0.661761, 0.953483, 1.516542",\ + "0.295974, 0.514750, 0.693420, 0.983435, 1.546355",\ + "0.342294, 0.561099, 0.739726, 1.029692, 1.592503",\ + "0.466491, 0.685293, 0.863899, 1.153787, 1.716424",\ + "0.798732, 1.017531, 1.196112, 1.485904, 2.048326",\ + "0.354342, 0.565759, 0.749042, 1.040788, 1.603895",\ + "0.384375, 0.602069, 0.780701, 1.070740, 1.633708",\ + "0.430695, 0.648418, 0.827006, 1.116997, 1.679856",\ + "0.554892, 0.772612, 0.951180, 1.241092, 1.803777",\ + "0.887133, 1.104849, 1.283393, 1.573209, 2.135679",\ + "0.443241, 0.646096, 0.829069, 1.120816, 1.683927",\ + "0.473273, 0.682406, 0.860728, 1.150768, 1.713740",\ + "0.519593, 0.728755, 0.907033, 1.197025, 1.759888",\ + "0.643790, 0.852948, 1.031207, 1.321121, 1.883808",\ + "0.976031, 1.185186, 1.363420, 1.653237, 2.215711",\ + "0.506266, 0.703926, 0.886774, 1.178249, 1.740947",\ + "0.536299, 0.740226, 0.918422, 1.208200, 1.770759",\ + "0.582618, 0.786573, 0.964728, 1.254457, 1.816907",\ + "0.706815, 0.910767, 1.088901, 1.378552, 1.940827",\ + "1.039055, 1.243004, 1.421114, 1.710669, 2.272729",\ + "0.825950, 1.009259, 1.190433, 1.481423, 2.043174",\ + "0.864615, 1.045486, 1.222079, 1.511375, 2.072986",\ + "0.911409, 1.091819, 1.268385, 1.557632, 2.119133",\ + "1.035605, 1.216013, 1.392558, 1.681726, 2.243053",\ + "1.367846, 1.548250, 1.724771, 2.013843, 2.574954"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432608, 0.432613, 0.432644, 0.432766, 0.433037",\ + "1.067886, 1.067868, 1.067749, 1.067290, 1.066264",\ + "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432608, 0.432613, 0.432644, 0.432766, 0.433037",\ + "1.067886, 1.067868, 1.067749, 1.067290, 1.066264",\ + "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432609, 0.432613, 0.432644, 0.432766, 0.433037",\ + "1.067884, 1.067868, 1.067749, 1.067290, 1.066264",\ + "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432609, 0.432613, 0.432644, 0.432766, 0.433038",\ + "1.067883, 1.067868, 1.067749, 1.067289, 1.066261",\ + "0.067593, 0.067594, 0.067599, 0.067617, 0.067659",\ + "0.104760, 0.104760, 0.104762, 0.104772, 0.104794",\ + "0.190700, 0.190700, 0.190699, 0.190697, 0.190692",\ + "0.432609, 0.432613, 0.432644, 0.432766, 0.433039",\ + "1.067883, 1.067867, 1.067749, 1.067287, 1.066258"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min_2547*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.230530, 0.471836, 0.662565, 0.965687, 1.550670",\ + "0.296073, 0.537386, 0.728118, 1.031247, 1.616246",\ + "0.382561, 0.623892, 0.814634, 1.117786, 1.702834",\ + "0.598538, 0.839995, 1.030804, 1.334111, 1.919485",\ + "1.153092, 1.394595, 1.585429, 1.888794, 2.474288",\ + "0.318838, 0.559155, 0.749846, 1.052992, 1.638023",\ + "0.384382, 0.624704, 0.815398, 1.118552, 1.703600",\ + "0.470869, 0.711210, 0.901915, 1.205091, 1.790187",\ + "0.686851, 0.927314, 1.118085, 1.421416, 2.006838",\ + "1.241406, 1.481914, 1.672710, 1.976099, 2.561641",\ + "0.407830, 0.639488, 0.829873, 1.133020, 1.718055",\ + "0.473374, 0.705038, 0.895425, 1.198581, 1.783631",\ + "0.559863, 0.791544, 0.981942, 1.285120, 1.870219",\ + "0.775854, 1.007647, 1.198112, 1.501445, 2.086870",\ + "1.330413, 1.562247, 1.752737, 2.056127, 2.641673",\ + "0.471102, 0.697352, 0.887595, 1.190479, 1.775129",\ + "0.536647, 0.762902, 0.953148, 1.256040, 1.840706",\ + "0.623137, 0.849408, 1.039664, 1.342579, 1.927294",\ + "0.839138, 1.065512, 1.255835, 1.558905, 2.143945",\ + "1.393700, 1.620112, 1.810460, 2.113587, 2.698749",\ + "0.805138, 1.002911, 1.191255, 1.493676, 2.077422",\ + "0.870685, 1.068460, 1.256808, 1.559237, 2.142998",\ + "0.957184, 1.154967, 1.343324, 1.645776, 2.229586",\ + "1.173243, 1.371074, 1.559495, 1.862102, 2.446239",\ + "1.727827, 1.925676, 2.114120, 2.416785, 3.001042"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.135507, 0.136708, 0.137351, 0.137726, 0.138133",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397345, 0.397457, 0.397518, 0.397656, 0.397948",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140071, 2.140260, 2.140361, 2.140594, 2.141085",\ + "0.135540, 0.136708, 0.137351, 0.137726, 0.138133",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397348, 0.397457, 0.397518, 0.397656, 0.397948",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140076, 2.140260, 2.140361, 2.140594, 2.141085",\ + "0.135636, 0.136708, 0.137351, 0.137726, 0.138133",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397357, 0.397457, 0.397518, 0.397656, 0.397948",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140091, 2.140260, 2.140361, 2.140594, 2.141085",\ + "0.135724, 0.136712, 0.137353, 0.137727, 0.138134",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397365, 0.397458, 0.397518, 0.397657, 0.397949",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140105, 2.140261, 2.140362, 2.140594, 2.141086",\ + "0.136284, 0.136744, 0.137353, 0.137727, 0.138135",\ + "0.232782, 0.232782, 0.232782, 0.232782, 0.232782",\ + "0.397418, 0.397461, 0.397518, 0.397657, 0.397950",\ + "0.873409, 0.873409, 0.873409, 0.873409, 0.873409",\ + "2.140193, 2.140266, 2.140362, 2.140595, 2.141087"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.247536, 0.465909, 0.655111, 0.957872, 1.542809",\ + "0.277578, 0.504859, 0.694166, 0.997452, 1.583596",\ + "0.323906, 0.557991, 0.747485, 1.050859, 1.637228",\ + "0.448115, 0.688036, 0.877811, 1.181150, 1.767445",\ + "0.780371, 1.021927, 1.212790, 1.516219, 2.101851",\ + "0.335860, 0.553227, 0.742392, 1.045177, 1.630162",\ + "0.365901, 0.592177, 0.781447, 1.084757, 1.670949",\ + "0.412227, 0.645309, 0.834766, 1.138164, 1.724581",\ + "0.536433, 0.775355, 0.965092, 1.268455, 1.854799",\ + "0.868686, 1.109246, 1.300071, 1.603524, 2.189205",\ + "0.424900, 0.633561, 0.822419, 1.125205, 1.710194",\ + "0.454934, 0.672511, 0.861474, 1.164785, 1.750981",\ + "0.501255, 0.725643, 0.914793, 1.218192, 1.804613",\ + "0.625454, 0.855688, 1.045119, 1.348483, 1.934830",\ + "0.957698, 1.189579, 1.380097, 1.683553, 2.269236",\ + "0.488215, 0.691382, 0.880139, 1.182665, 1.767268",\ + "0.518244, 0.730333, 0.919194, 1.222246, 1.808058",\ + "0.564561, 0.783480, 0.972513, 1.275653, 1.861690",\ + "0.688753, 0.913547, 1.102839, 1.405944, 1.991908",\ + "1.020988, 1.247444, 1.437820, 1.741013, 2.326312",\ + "0.816645, 0.996641, 1.183799, 1.485862, 2.069561",\ + "0.852522, 1.035597, 1.222854, 1.525444, 2.110354",\ + "0.898812, 1.088847, 1.276173, 1.578852, 2.163987",\ + "1.022959, 1.219069, 1.406500, 1.709143, 2.294204",\ + "1.355140, 1.553009, 1.741481, 2.044211, 2.628607"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.067590, 0.067613, 0.067625, 0.067653, 0.067711",\ + "0.104758, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432590, 0.432736, 0.432815, 0.432996, 0.433377",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\ + "0.067591, 0.067613, 0.067625, 0.067653, 0.067711",\ + "0.104758, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432594, 0.432736, 0.432815, 0.432996, 0.433377",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\ + "0.067593, 0.067613, 0.067625, 0.067653, 0.067711",\ + "0.104759, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432605, 0.432736, 0.432815, 0.432996, 0.433377",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\ + "0.067594, 0.067613, 0.067625, 0.067653, 0.067711",\ + "0.104760, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432616, 0.432737, 0.432815, 0.432996, 0.433378",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080",\ + "0.067593, 0.067614, 0.067625, 0.067653, 0.067711",\ + "0.104766, 0.104770, 0.104776, 0.104791, 0.104822",\ + "0.190676, 0.190676, 0.190676, 0.190676, 0.190676",\ + "0.432685, 0.432741, 0.432815, 0.432997, 0.433379",\ + "1.063080, 1.063080, 1.063080, 1.063080, 1.063080"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.244473, 0.505671, 0.697935, 0.998174, 1.574785",\ + "0.300254, 0.556634, 0.748837, 1.048824, 1.624875",\ + "0.376032, 0.633972, 0.826223, 1.125987, 1.701451",\ + "0.578226, 0.841738, 1.034663, 1.334155, 1.908979",\ + "1.122810, 1.385726, 1.587938, 1.887184, 2.461388",\ + "0.332840, 0.592988, 0.785216, 1.085479, 1.662138",\ + "0.388618, 0.643952, 0.836118, 1.136129, 1.712228",\ + "0.464390, 0.721290, 0.913504, 1.213292, 1.788804",\ + "0.666574, 0.929242, 1.121944, 1.421460, 1.996333",\ + "1.211151, 1.473226, 1.675219, 1.974489, 2.548742",\ + "0.422672, 0.673316, 0.865243, 1.165508, 1.742170",\ + "0.478441, 0.724280, 0.916145, 1.216158, 1.792260",\ + "0.554191, 0.801618, 0.993531, 1.293321, 1.868836",\ + "0.756345, 1.010087, 1.201971, 1.501488, 2.076365",\ + "1.300900, 1.562060, 1.755246, 2.054518, 2.628773",\ + "0.487019, 0.731152, 0.922971, 1.222957, 1.799227",\ + "0.542778, 0.782116, 0.973873, 1.273607, 1.849315",\ + "0.618509, 0.859454, 1.051260, 1.350769, 1.925890",\ + "0.820633, 1.067923, 1.259699, 1.558936, 2.133417",\ + "1.365167, 1.621171, 1.812974, 2.111965, 2.685824",\ + "0.827863, 1.036490, 1.226631, 1.526145, 2.101498",\ + "0.883564, 1.087454, 1.277533, 1.576794, 2.151585",\ + "0.959165, 1.164792, 1.354919, 1.653956, 2.228158",\ + "1.161104, 1.373262, 1.563359, 1.862122, 2.435683",\ + "1.705499, 1.926510, 2.116634, 2.415150, 2.988089"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.150101, 0.150101, 0.150101, 0.151542, 0.155060",\ + "0.237371, 0.237371, 0.237371, 0.238239, 0.240357",\ + "0.400588, 0.400588, 0.400588, 0.400716, 0.401031",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.136242, 2.138523, 2.138971, 2.139329, 2.139329",\ + "0.150101, 0.150101, 0.150101, 0.151542, 0.155060",\ + "0.237371, 0.237371, 0.237371, 0.238239, 0.240357",\ + "0.400588, 0.400588, 0.400588, 0.400716, 0.401031",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.136282, 2.138528, 2.138971, 2.139329, 2.139329",\ + "0.150101, 0.150101, 0.150101, 0.151542, 0.155060",\ + "0.237371, 0.237371, 0.237371, 0.238239, 0.240357",\ + "0.400588, 0.400588, 0.400588, 0.400716, 0.401031",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.136409, 2.138540, 2.138971, 2.139329, 2.139329",\ + "0.150101, 0.150101, 0.150101, 0.151547, 0.155068",\ + "0.237371, 0.237371, 0.237371, 0.238242, 0.240362",\ + "0.400588, 0.400588, 0.400588, 0.400717, 0.401031",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.136531, 2.137884, 2.138973, 2.139329, 2.139329",\ + "0.150101, 0.150101, 0.150101, 0.151550, 0.155079",\ + "0.237371, 0.237371, 0.237371, 0.238244, 0.240369",\ + "0.400588, 0.400588, 0.400588, 0.400717, 0.401032",\ + "0.873603, 0.873603, 0.873603, 0.873603, 0.873603",\ + "2.137311, 2.137926, 2.138974, 2.139329, 2.139329"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.243871, 0.423733, 0.615818, 0.915684, 1.491530",\ + "0.279786, 0.459520, 0.651316, 0.952173, 1.530680",\ + "0.334281, 0.513862, 0.705260, 1.006477, 1.586195",\ + "0.467807, 0.647364, 0.838496, 1.139651, 1.719442",\ + "0.802494, 0.981904, 1.172736, 1.473617, 2.052986",\ + "0.331272, 0.511050, 0.703099, 1.002989, 1.578883",\ + "0.367188, 0.546838, 0.738597, 1.039478, 1.618034",\ + "0.421683, 0.601180, 0.792541, 1.093782, 1.673548",\ + "0.555208, 0.734681, 0.925777, 1.226957, 1.806796",\ + "0.889896, 1.069221, 1.260017, 1.560922, 2.140339",\ + "0.412125, 0.591378, 0.783126, 1.083017, 1.658915",\ + "0.448040, 0.627166, 0.818624, 1.119507, 1.698066",\ + "0.502534, 0.681508, 0.872568, 1.173811, 1.753580",\ + "0.636060, 0.815010, 1.005804, 1.306985, 1.886827",\ + "0.970746, 1.149549, 1.340044, 1.640951, 2.220371",\ + "0.469856, 0.649214, 0.840854, 1.140466, 1.715970",\ + "0.505769, 0.685001, 0.876351, 1.176959, 1.755127",\ + "0.560262, 0.739342, 0.930294, 1.231264, 1.810644",\ + "0.693787, 0.872844, 1.063529, 1.364439, 1.943892",\ + "1.028472, 1.207383, 1.397769, 1.698404, 2.277434",\ + "0.773472, 0.954547, 1.144514, 1.443653, 2.018239",\ + "0.809371, 0.990331, 1.180011, 1.480149, 2.057404",\ + "0.863847, 1.044668, 1.233954, 1.534456, 2.112924",\ + "0.997369, 1.178169, 1.367189, 1.667630, 2.246172",\ + "1.332038, 1.512705, 1.701428, 2.001595, 2.579713"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.071845, 0.072069, 0.072077, 0.072933, 0.075022",\ + "0.105010, 0.105036, 0.105037, 0.105381, 0.106219",\ + "0.190967, 0.191120, 0.191139, 0.191258, 0.191538",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063081, 1.064842, 1.065453, 1.065643, 1.065643",\ + "0.071845, 0.072069, 0.072077, 0.072933, 0.075022",\ + "0.105010, 0.105036, 0.105037, 0.105381, 0.106219",\ + "0.190967, 0.191120, 0.191139, 0.191258, 0.191538",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063081, 1.064842, 1.065453, 1.065643, 1.065643",\ + "0.071847, 0.072069, 0.072077, 0.072933, 0.075022",\ + "0.105010, 0.105036, 0.105037, 0.105381, 0.106219",\ + "0.190967, 0.191120, 0.191139, 0.191258, 0.191538",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063091, 1.064842, 1.065453, 1.065643, 1.065643",\ + "0.071849, 0.072070, 0.072077, 0.072936, 0.075027",\ + "0.105011, 0.105036, 0.105037, 0.105382, 0.106221",\ + "0.190969, 0.191121, 0.191139, 0.191259, 0.191539",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063112, 1.064849, 1.065454, 1.065643, 1.065643",\ + "0.071874, 0.072076, 0.072077, 0.072938, 0.075034",\ + "0.105014, 0.105037, 0.105037, 0.105382, 0.106223",\ + "0.190986, 0.191125, 0.191139, 0.191259, 0.191540",\ + "0.431534, 0.431534, 0.431534, 0.431534, 0.431534",\ + "1.063308, 1.064895, 1.065455, 1.065643, 1.065643"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min_2493*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.377825, 0.634223, 0.868848, 1.157402, 1.717689",\ + "0.428298, 0.684702, 0.914931, 1.203491, 1.763791",\ + "0.530100, 0.786503, 1.000029, 1.288605, 1.848942",\ + "0.768016, 1.024419, 1.221793, 1.510395, 2.070789",\ + "1.340420, 1.596824, 1.783889, 2.072520, 2.632977",\ + "0.466032, 0.721699, 0.956129, 1.244707, 1.805043",\ + "0.516506, 0.772177, 1.002212, 1.290796, 1.851145",\ + "0.618307, 0.873978, 1.087310, 1.375910, 1.936295",\ + "0.856223, 1.111895, 1.309074, 1.597700, 2.158142",\ + "1.428628, 1.684300, 1.871170, 2.159825, 2.720331",\ + "0.554696, 0.810512, 1.036155, 1.324735, 1.885074",\ + "0.605170, 0.860990, 1.082239, 1.370825, 1.931176",\ + "0.706971, 0.962791, 1.167337, 1.455939, 2.016327",\ + "0.944887, 1.200708, 1.389101, 1.677728, 2.238174",\ + "1.517292, 1.773113, 1.951197, 2.239853, 2.800363",\ + "0.617648, 0.875902, 1.093848, 1.382165, 1.942089",\ + "0.668122, 0.926381, 1.139932, 1.428254, 1.988191",\ + "0.769923, 1.028182, 1.225029, 1.513368, 2.073342",\ + "1.007839, 1.266098, 1.446793, 1.735158, 2.295189",\ + "1.580244, 1.831772, 2.008889, 2.297283, 2.857378",\ + "0.949653, 1.221972, 1.397504, 1.685336, 2.244309",\ + "1.000127, 1.268054, 1.443587, 1.731425, 2.290411",\ + "1.101928, 1.353148, 1.528685, 1.816540, 2.375562",\ + "1.339844, 1.574905, 1.750449, 2.038329, 2.597409",\ + "1.912249, 2.136994, 2.312545, 2.600454, 3.159598"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.041017, 0.041026, 0.041033, 0.041274, 0.041853",\ + "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\ + "0.374819, 0.374818, 0.374816, 0.374779, 0.374688",\ + "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\ + "0.041017, 0.041026, 0.041033, 0.041274, 0.041853",\ + "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\ + "0.374819, 0.374818, 0.374816, 0.374779, 0.374688",\ + "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\ + "0.041017, 0.041026, 0.041033, 0.041274, 0.041853",\ + "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\ + "0.374819, 0.374817, 0.374816, 0.374779, 0.374688",\ + "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\ + "0.041017, 0.041026, 0.041033, 0.041275, 0.041855",\ + "0.147926, 0.147927, 0.147928, 0.147959, 0.148033",\ + "0.374819, 0.374817, 0.374816, 0.374778, 0.374688",\ + "0.869171, 0.869170, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110",\ + "0.041017, 0.041017, 0.041033, 0.041276, 0.041856",\ + "0.147926, 0.147926, 0.147928, 0.147959, 0.148034",\ + "0.374819, 0.374819, 0.374816, 0.374778, 0.374687",\ + "0.869171, 0.869171, 0.869169, 0.869164, 0.869153",\ + "2.137120, 2.137120, 2.137119, 2.137116, 2.137110"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.419293, 0.629601, 0.807148, 1.095622, 1.655731",\ + "0.441693, 0.683002, 0.860568, 1.149118, 1.709396",\ + "0.483042, 0.739446, 0.921121, 1.209730, 1.770140",\ + "0.605027, 0.861431, 1.052488, 1.341094, 1.901499",\ + "0.936548, 1.192951, 1.389827, 1.678402, 2.238737",\ + "0.507500, 0.716919, 0.894429, 1.182927, 1.743084",\ + "0.529901, 0.770320, 0.947849, 1.236423, 1.796750",\ + "0.571249, 0.826922, 1.008402, 1.297035, 1.857493",\ + "0.693234, 0.948907, 1.139769, 1.428399, 1.988852",\ + "1.024755, 1.280427, 1.477108, 1.765707, 2.326091",\ + "0.596164, 0.797253, 0.974456, 1.262956, 1.823116",\ + "0.618565, 0.850654, 1.027876, 1.316451, 1.876781",\ + "0.659913, 0.911193, 1.088429, 1.377064, 1.937525",\ + "0.781898, 1.037719, 1.219796, 1.508428, 2.068884",\ + "1.113419, 1.369240, 1.557135, 1.845736, 2.406122",\ + "0.659116, 0.855070, 1.032148, 1.320385, 1.880130",\ + "0.681517, 0.908471, 1.085568, 1.373881, 1.933796",\ + "0.722865, 0.969009, 1.146121, 1.434493, 1.994540",\ + "0.844850, 1.100376, 1.277488, 1.565857, 2.125898",\ + "1.176371, 1.434630, 1.614827, 1.903165, 2.463137",\ + "0.981445, 1.160292, 1.335804, 1.623556, 2.182350",\ + "1.013522, 1.213693, 1.389224, 1.677052, 2.236016",\ + "1.054870, 1.274231, 1.449777, 1.737664, 2.296760",\ + "1.176855, 1.405599, 1.581144, 1.869029, 2.428119",\ + "1.508376, 1.742946, 1.918483, 2.206336, 2.765357"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\ + "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\ + "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\ + "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250",\ + "0.045770, 0.045770, 0.045769, 0.045752, 0.045711",\ + "0.091340, 0.091340, 0.091340, 0.091330, 0.091307",\ + "0.185791, 0.185791, 0.185790, 0.185786, 0.185775",\ + "0.432252, 0.432252, 0.432252, 0.432251, 0.432251",\ + "1.064249, 1.064249, 1.064249, 1.064249, 1.064250"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[10]_redg_min_2445*/ + +} /* end of pin tl_o[10] */ + +pin("tl_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.555398, 0.819461, 1.110403, 1.621818, 2.644648",\ + "0.601280, 0.865373, 1.156432, 1.668153, 2.691596",\ + "0.685796, 0.949972, 1.241371, 1.753978, 2.779193",\ + "0.906647, 1.170955, 1.462887, 1.976883, 3.004877",\ + "1.467724, 1.732179, 2.024706, 2.540253, 3.571347",\ + "0.642813, 0.907018, 1.198106, 1.708533, 2.730582",\ + "0.688695, 0.952929, 1.244136, 1.754869, 2.777529",\ + "0.773211, 1.037529, 1.329078, 1.840694, 2.865127",\ + "0.994062, 1.258512, 1.550598, 2.063599, 3.090810",\ + "1.555139, 1.819737, 2.112422, 2.626968, 3.657281",\ + "0.724929, 0.996034, 1.286073, 1.796156, 2.817537",\ + "0.770813, 1.041946, 1.332103, 1.842491, 2.864485",\ + "0.855331, 1.126547, 1.417045, 1.928316, 2.952082",\ + "1.076186, 1.347532, 1.638566, 2.151221, 3.177765",\ + "1.637269, 1.908760, 2.200390, 2.714591, 3.744236",\ + "0.787882, 1.061721, 1.350220, 1.860070, 2.881046",\ + "0.833767, 1.107633, 1.396250, 1.906405, 2.927994",\ + "0.918287, 1.192236, 1.481192, 1.992230, 3.015591",\ + "1.139145, 1.413225, 1.702713, 2.215135, 3.241274",\ + "1.700230, 1.974455, 2.264537, 2.778505, 3.807745",\ + "1.119904, 1.426659, 1.702520, 2.209597, 3.226502",\ + "1.165792, 1.472579, 1.748554, 2.255933, 3.273450",\ + "1.250324, 1.557204, 1.833505, 2.341762, 3.361047",\ + "1.471201, 1.778225, 2.055039, 2.564673, 3.586730",\ + "2.032307, 2.339493, 2.616879, 3.128049, 4.153201"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.051283, 0.051370, 0.051891, 0.053400, 0.056417",\ + "0.173670, 0.173612, 0.173379, 0.172770, 0.171552",\ + "0.376316, 0.376196, 0.375752, 0.374635, 0.372400",\ + "0.881676, 0.881670, 0.881647, 0.881590, 0.881477",\ + "2.159552, 2.159744, 2.159980, 2.159997, 2.160033",\ + "0.051283, 0.051370, 0.051896, 0.053400, 0.056417",\ + "0.173670, 0.173612, 0.173377, 0.172770, 0.171552",\ + "0.376316, 0.376195, 0.375749, 0.374635, 0.372400",\ + "0.881676, 0.881670, 0.881647, 0.881590, 0.881477",\ + "2.159552, 2.159745, 2.159980, 2.159997, 2.160033",\ + "0.051286, 0.051372, 0.051896, 0.053400, 0.056417",\ + "0.173668, 0.173611, 0.173377, 0.172770, 0.171552",\ + "0.376312, 0.376193, 0.375749, 0.374635, 0.372400",\ + "0.881675, 0.881670, 0.881647, 0.881590, 0.881477",\ + "2.159557, 2.159749, 2.159980, 2.159997, 2.160033",\ + "0.051287, 0.051374, 0.051896, 0.053400, 0.056417",\ + "0.173667, 0.173610, 0.173377, 0.172770, 0.171552",\ + "0.376309, 0.376191, 0.375749, 0.374635, 0.372400",\ + "0.881675, 0.881670, 0.881647, 0.881590, 0.881477",\ + "2.159559, 2.159753, 2.159980, 2.159997, 2.160033",\ + "0.051300, 0.051396, 0.051912, 0.053406, 0.056417",\ + "0.173659, 0.173595, 0.173370, 0.172767, 0.171552",\ + "0.376292, 0.376160, 0.375737, 0.374630, 0.372400",\ + "0.881675, 0.881668, 0.881646, 0.881590, 0.881477",\ + "2.159577, 2.159810, 2.159980, 2.159997, 2.160033"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.496610, 0.760268, 1.051112, 1.563657, 2.588749",\ + "0.547372, 0.811417, 1.102287, 1.613514, 2.635968",\ + "0.606137, 0.870487, 1.162590, 1.677032, 2.705914",\ + "0.741015, 1.005340, 1.297339, 1.811510, 2.839852",\ + "1.088533, 1.352702, 1.644074, 2.156609, 3.181679",\ + "0.584025, 0.847822, 1.138818, 1.650373, 2.674682",\ + "0.634786, 0.898974, 1.189989, 1.700229, 2.721902",\ + "0.693552, 0.958046, 1.250303, 1.763747, 2.791848",\ + "0.828430, 1.092898, 1.385051, 1.898225, 2.925786",\ + "1.175948, 1.440259, 1.731781, 2.243324, 3.267613",\ + "0.666128, 0.936832, 1.226786, 1.737995, 2.761637",\ + "0.716902, 0.987989, 1.277956, 1.787852, 2.808857",\ + "0.775678, 1.047066, 1.338270, 1.851369, 2.878803",\ + "0.910556, 1.181918, 1.473018, 1.985848, 3.012741",\ + "1.258068, 1.529277, 1.819748, 2.330947, 3.354568",\ + "0.729072, 1.002510, 1.290933, 1.801909, 2.825146",\ + "0.779855, 1.053676, 1.342103, 1.851766, 2.872366",\ + "0.838638, 1.112759, 1.402418, 1.915283, 2.942312",\ + "0.973515, 1.247610, 1.537165, 2.049762, 3.076250",\ + "1.321024, 1.594967, 1.883895, 2.394861, 3.418077",\ + "1.061036, 1.367345, 1.643245, 2.151441, 3.170603",\ + "1.111874, 1.418610, 1.694402, 2.201292, 3.217822",\ + "1.170700, 1.477770, 1.754749, 2.264823, 3.287768",\ + "1.305573, 1.612615, 1.889494, 2.399300, 3.421706",\ + "1.653060, 1.959932, 2.236207, 2.744392, 3.763533"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.056276, 0.056853, 0.059193, 0.065291, 0.077487",\ + "0.108806, 0.109601, 0.112826, 0.121230, 0.138038",\ + "0.194961, 0.195687, 0.198632, 0.206304, 0.221649",\ + "0.444958, 0.445039, 0.445369, 0.446227, 0.447944",\ + "1.101681, 1.101643, 1.101491, 1.101094, 1.100299",\ + "0.056276, 0.056857, 0.059213, 0.065291, 0.077487",\ + "0.108806, 0.109606, 0.112853, 0.121230, 0.138038",\ + "0.194961, 0.195692, 0.198656, 0.206304, 0.221649",\ + "0.444958, 0.445040, 0.445371, 0.446227, 0.447944",\ + "1.101681, 1.101643, 1.101490, 1.101094, 1.100299",\ + "0.056295, 0.056865, 0.059213, 0.065291, 0.077487",\ + "0.108832, 0.109618, 0.112853, 0.121230, 0.138038",\ + "0.194985, 0.195703, 0.198657, 0.206304, 0.221649",\ + "0.444961, 0.445041, 0.445371, 0.446227, 0.447944",\ + "1.101680, 1.101642, 1.101490, 1.101094, 1.100299",\ + "0.056308, 0.056878, 0.059214, 0.065291, 0.077487",\ + "0.108850, 0.109635, 0.112855, 0.121230, 0.138038",\ + "0.195002, 0.195719, 0.198658, 0.206304, 0.221649",\ + "0.444963, 0.445043, 0.445372, 0.446227, 0.447944",\ + "1.101679, 1.101642, 1.101490, 1.101094, 1.100299",\ + "0.056389, 0.057025, 0.059276, 0.065316, 0.077487",\ + "0.108962, 0.109837, 0.112940, 0.121265, 0.138038",\ + "0.195104, 0.195903, 0.198736, 0.206336, 0.221649",\ + "0.444974, 0.445063, 0.445380, 0.446231, 0.447944",\ + "1.101673, 1.101632, 1.101485, 1.101092, 1.100299"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_2686*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.541885, 0.785038, 1.063858, 1.534026, 2.474360",\ + "0.587770, 0.830960, 1.109901, 1.580353, 2.521255",\ + "0.672293, 0.915590, 1.194882, 1.666154, 2.608697",\ + "0.893156, 1.136622, 1.416462, 1.889021, 2.834138",\ + "1.454245, 1.697900, 1.978353, 2.452348, 3.400338",\ + "0.629296, 0.872602, 1.151428, 1.620740, 2.560294",\ + "0.675181, 0.918525, 1.197473, 1.667067, 2.607188",\ + "0.759703, 1.003156, 1.282456, 1.752868, 2.694631",\ + "0.980566, 1.224188, 1.504040, 1.975736, 2.920072",\ + "1.541656, 1.785468, 2.065936, 2.539063, 3.486272",\ + "0.710134, 0.961613, 1.239393, 1.708362, 2.647249",\ + "0.756019, 1.007537, 1.285437, 1.754689, 2.694144",\ + "0.840542, 1.092169, 1.370420, 1.840490, 2.781586",\ + "1.061405, 1.313204, 1.592004, 2.063357, 3.007027",\ + "1.622495, 1.874487, 2.153900, 2.626685, 3.573227",\ + "0.767752, 1.027293, 1.303532, 1.772275, 2.710758",\ + "0.813637, 1.073217, 1.349577, 1.818602, 2.757653",\ + "0.898160, 1.157852, 1.434560, 1.904403, 2.845095",\ + "1.119024, 1.378891, 1.656144, 2.127271, 3.070536",\ + "1.680114, 1.940177, 2.218040, 2.690598, 3.636736",\ + "1.089850, 1.392206, 1.655411, 2.121627, 3.056214",\ + "1.135741, 1.438139, 1.701459, 2.167955, 3.103108",\ + "1.220283, 1.522803, 1.786450, 2.253759, 3.190551",\ + "1.441176, 1.743885, 2.008048, 2.476632, 3.415992",\ + "2.002299, 2.305221, 2.569958, 3.039965, 3.982192"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.051290, 0.051402, 0.051767, 0.052622, 0.054331",\ + "0.173665, 0.173591, 0.173350, 0.172786, 0.171658",\ + "0.376306, 0.376151, 0.375734, 0.374850, 0.373082",\ + "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\ + "2.159523, 2.159652, 2.159853, 2.159909, 2.160021",\ + "0.051290, 0.051403, 0.051770, 0.052622, 0.054331",\ + "0.173665, 0.173591, 0.173349, 0.172786, 0.171658",\ + "0.376306, 0.376150, 0.375732, 0.374850, 0.373082",\ + "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\ + "2.159523, 2.159653, 2.159854, 2.159909, 2.160021",\ + "0.051290, 0.051405, 0.051770, 0.052622, 0.054331",\ + "0.173665, 0.173589, 0.173349, 0.172786, 0.171658",\ + "0.376305, 0.376148, 0.375732, 0.374850, 0.373082",\ + "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\ + "2.159523, 2.159656, 2.159854, 2.159909, 2.160021",\ + "0.051291, 0.051407, 0.051770, 0.052622, 0.054331",\ + "0.173665, 0.173588, 0.173348, 0.172786, 0.171658",\ + "0.376305, 0.376145, 0.375731, 0.374850, 0.373082",\ + "0.881676, 0.881673, 0.881655, 0.881609, 0.881516",\ + "2.159523, 2.159659, 2.159854, 2.159909, 2.160021",\ + "0.051310, 0.051436, 0.051779, 0.052625, 0.054331",\ + "0.173652, 0.173569, 0.173343, 0.172784, 0.171658",\ + "0.376278, 0.376105, 0.375722, 0.374847, 0.373082",\ + "0.881676, 0.881672, 0.881655, 0.881609, 0.881516",\ + "2.159524, 2.159705, 2.159854, 2.159909, 2.160021"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.483063, 0.725694, 1.002821, 1.469018, 2.401413",\ + "0.533858, 0.776987, 1.055733, 1.525727, 2.465714",\ + "0.592650, 0.836170, 1.116186, 1.589157, 2.535098",\ + "0.727526, 0.971013, 1.250922, 1.723643, 2.669083",\ + "1.075030, 1.318318, 1.597581, 2.068786, 3.011196",\ + "0.570473, 0.813255, 1.090379, 1.555733, 2.487347",\ + "0.621268, 0.864551, 1.143303, 1.612441, 2.551647",\ + "0.680060, 0.923737, 1.203766, 1.675871, 2.621032",\ + "0.814936, 1.058579, 1.338501, 1.810357, 2.755017",\ + "1.162440, 1.405883, 1.685155, 2.155501, 3.097130",\ + "0.651310, 0.902258, 1.178342, 1.643355, 2.574302",\ + "0.702106, 0.953562, 1.231267, 1.700063, 2.638602",\ + "0.760899, 1.012754, 1.291730, 1.763493, 2.707987",\ + "0.895775, 1.147596, 1.426465, 1.897979, 2.841972",\ + "1.243279, 1.494897, 1.773119, 2.243123, 3.184085",\ + "0.708926, 0.967926, 1.242482, 1.707268, 2.637811",\ + "0.759724, 1.019241, 1.295407, 1.763976, 2.702111",\ + "0.818518, 1.078441, 1.355870, 1.827407, 2.771496",\ + "0.953394, 1.213283, 1.490605, 1.961892, 2.905481",\ + "1.300897, 1.560579, 1.837259, 2.307036, 3.247594",\ + "1.030934, 1.332704, 1.594321, 2.056603, 2.983267",\ + "1.081818, 1.384149, 1.647285, 2.113327, 3.047567",\ + "1.140679, 1.443450, 1.707778, 2.176770, 3.116952",\ + "1.275549, 1.578283, 1.842510, 2.311255, 3.250937",\ + "1.623018, 1.925528, 2.189149, 2.656392, 3.593050"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.056326, 0.057067, 0.059477, 0.065125, 0.076422",\ + "0.108874, 0.109896, 0.113217, 0.121001, 0.136571",\ + "0.195024, 0.195957, 0.198988, 0.206096, 0.220310",\ + "0.444965, 0.445069, 0.445409, 0.446204, 0.447794",\ + "1.101678, 1.101629, 1.101472, 1.101105, 1.100369",\ + "0.056326, 0.057072, 0.059494, 0.065125, 0.076422",\ + "0.108874, 0.109903, 0.113241, 0.121001, 0.136571",\ + "0.195024, 0.195963, 0.199011, 0.206096, 0.220310",\ + "0.444965, 0.445070, 0.445411, 0.446204, 0.447794",\ + "1.101678, 1.101629, 1.101471, 1.101105, 1.100369",\ + "0.056327, 0.057083, 0.059495, 0.065125, 0.076422",\ + "0.108876, 0.109918, 0.113242, 0.121001, 0.136571",\ + "0.195025, 0.195977, 0.199011, 0.206096, 0.220310",\ + "0.444965, 0.445072, 0.445411, 0.446204, 0.447794",\ + "1.101678, 1.101628, 1.101471, 1.101105, 1.100369",\ + "0.056330, 0.057100, 0.059496, 0.065125, 0.076422",\ + "0.108880, 0.109941, 0.113243, 0.121001, 0.136571",\ + "0.195029, 0.195998, 0.199012, 0.206096, 0.220310",\ + "0.444966, 0.445074, 0.445411, 0.446204, 0.447794",\ + "1.101677, 1.101627, 1.101471, 1.101105, 1.100369",\ + "0.056457, 0.057292, 0.059553, 0.065149, 0.076422",\ + "0.109056, 0.110205, 0.113322, 0.121034, 0.136571",\ + "0.195189, 0.196239, 0.199085, 0.206125, 0.220310",\ + "0.444983, 0.445101, 0.445419, 0.446207, 0.447794",\ + "1.101669, 1.101615, 1.101467, 1.101103, 1.100369"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_2573*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.565069, 0.820938, 1.075987, 1.513367, 2.388129",\ + "0.610722, 0.866590, 1.121640, 1.559020, 2.433781",\ + "0.694431, 0.950300, 1.205350, 1.642730, 2.517491",\ + "0.914051, 1.169920, 1.424969, 1.862349, 2.737111",\ + "1.473307, 1.729176, 1.984225, 2.421606, 3.296367",\ + "0.653273, 0.908426, 1.163451, 1.600080, 2.474062",\ + "0.698926, 0.954078, 1.209104, 1.645733, 2.519715",\ + "0.782636, 1.037788, 1.292814, 1.729443, 2.603425",\ + "1.002255, 1.257407, 1.512433, 1.949062, 2.823044",\ + "1.561512, 1.816664, 2.071689, 2.508319, 3.382300",\ + "0.742600, 0.997231, 1.251411, 1.687701, 2.561017",\ + "0.788253, 1.042883, 1.297064, 1.733354, 2.606670",\ + "0.871963, 1.126593, 1.380774, 1.817064, 2.690380",\ + "1.091582, 1.346213, 1.600393, 2.036683, 2.909999",\ + "1.650838, 1.905469, 2.159649, 2.595939, 3.469255",\ + "0.806459, 1.062609, 1.315545, 1.751614, 2.624526",\ + "0.852112, 1.108261, 1.361198, 1.797266, 2.670179",\ + "0.935822, 1.191971, 1.444908, 1.880976, 2.753889",\ + "1.155441, 1.411591, 1.664527, 2.100595, 2.973508",\ + "1.714697, 1.970847, 2.223783, 2.659852, 3.532764",\ + "1.144184, 1.424102, 1.667087, 2.100822, 2.969982",\ + "1.189837, 1.469755, 1.712740, 2.146475, 3.015635",\ + "1.273547, 1.553465, 1.796450, 2.230185, 3.099345",\ + "1.493166, 1.773084, 2.016069, 2.449804, 3.318964",\ + "2.052423, 2.332341, 2.575326, 3.009061, 3.878221"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\ + "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\ + "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\ + "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378",\ + "0.051575, 0.051575, 0.051575, 0.051575, 0.051575",\ + "0.175957, 0.175957, 0.175957, 0.175957, 0.175957",\ + "0.378358, 0.378358, 0.378358, 0.378358, 0.378358",\ + "0.881680, 0.881680, 0.881680, 0.881680, 0.881680",\ + "2.159378, 2.159378, 2.159378, 2.159378, 2.159378"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.512229, 0.768098, 1.023147, 1.460527, 2.335289",\ + "0.557112, 0.812981, 1.068030, 1.505411, 2.380172",\ + "0.613030, 0.868899, 1.123949, 1.561329, 2.436090",\ + "0.748455, 1.004324, 1.259373, 1.696754, 2.571515",\ + "1.097588, 1.353456, 1.608506, 2.045886, 2.920648",\ + "0.600433, 0.855585, 1.110611, 1.547240, 2.421222",\ + "0.645316, 0.900469, 1.155494, 1.592124, 2.466105",\ + "0.701235, 0.956387, 1.211413, 1.648042, 2.522024",\ + "0.836659, 1.091812, 1.346837, 1.783467, 2.657449",\ + "1.185792, 1.440944, 1.695970, 2.132599, 3.006581",\ + "0.689760, 0.944391, 1.198571, 1.634861, 2.508177",\ + "0.734643, 0.989274, 1.243454, 1.679744, 2.553061",\ + "0.790562, 1.045192, 1.299373, 1.735663, 2.608979",\ + "0.925986, 1.180617, 1.434798, 1.871087, 2.744404",\ + "1.275119, 1.529750, 1.783930, 2.220220, 3.093536",\ + "0.753619, 1.009769, 1.262705, 1.698774, 2.571686",\ + "0.798502, 1.054652, 1.307589, 1.743657, 2.616570",\ + "0.854421, 1.110570, 1.363507, 1.799575, 2.672488",\ + "0.989845, 1.245995, 1.498932, 1.935000, 2.807913",\ + "1.338978, 1.595128, 1.848064, 2.284132, 3.157045",\ + "1.091344, 1.371262, 1.614247, 2.047982, 2.917142",\ + "1.136228, 1.416146, 1.659131, 2.092866, 2.962026",\ + "1.192146, 1.472064, 1.715049, 2.148784, 3.017944",\ + "1.327571, 1.607489, 1.850474, 2.284209, 3.153369",\ + "1.676703, 1.956621, 2.199606, 2.633341, 3.502501"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\ + "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\ + "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\ + "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794",\ + "0.047854, 0.047854, 0.047854, 0.047854, 0.047854",\ + "0.098249, 0.098249, 0.098249, 0.098249, 0.098249",\ + "0.188801, 0.188801, 0.188801, 0.188801, 0.188801",\ + "0.444112, 0.444112, 0.444112, 0.444112, 0.444112",\ + "1.101794, 1.101794, 1.101794, 1.101794, 1.101794"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_2453*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.405081, 0.661604, 0.918671, 1.360881, 2.245302",\ + "0.455961, 0.712483, 0.969534, 1.411694, 2.296014",\ + "0.533364, 0.789887, 1.046932, 1.489066, 2.373335",\ + "0.741794, 0.998316, 1.255349, 1.697444, 2.581634",\ + "1.295078, 1.551601, 1.808624, 2.250684, 3.134805",\ + "0.493291, 0.749080, 1.006153, 1.447596, 2.331236",\ + "0.544172, 0.799959, 1.057016, 1.498409, 2.381948",\ + "0.621574, 0.877363, 1.134413, 1.575781, 2.459269",\ + "0.830004, 1.085792, 1.342831, 1.784158, 2.667568",\ + "1.383288, 1.639076, 1.896105, 2.337399, 3.220738",\ + "0.581963, 0.837893, 1.094115, 1.535218, 2.418191",\ + "0.632844, 0.888772, 1.144979, 1.586031, 2.468903",\ + "0.710247, 0.966176, 1.222376, 1.663403, 2.546224",\ + "0.918676, 1.174605, 1.430793, 1.871780, 2.754523",\ + "1.471960, 1.727890, 1.984068, 2.425020, 3.307693",\ + "0.644923, 0.903284, 1.158251, 1.599131, 2.481700",\ + "0.695804, 0.954163, 1.209114, 1.649944, 2.532412",\ + "0.773206, 1.031567, 1.286511, 1.727316, 2.609733",\ + "0.981636, 1.239996, 1.494928, 1.935694, 2.818032",\ + "1.534920, 1.793280, 2.048203, 2.488934, 3.371202",\ + "0.976976, 1.264814, 1.509846, 1.948367, 2.827156",\ + "1.027857, 1.315693, 1.560709, 1.999180, 2.877868",\ + "1.105260, 1.393097, 1.638106, 2.076551, 2.955189",\ + "1.313689, 1.601526, 1.846523, 2.284929, 3.163488",\ + "1.866973, 2.154810, 2.399797, 2.838169, 3.716659"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.235856, 0.236036, 0.236876, 0.239059, 0.243424",\ + "0.297458, 0.297578, 0.298135, 0.299584, 0.302483",\ + "0.424282, 0.424361, 0.424727, 0.425678, 0.427582",\ + "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\ + "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\ + "0.235857, 0.236037, 0.236883, 0.239059, 0.243424",\ + "0.297459, 0.297578, 0.298140, 0.299584, 0.302483",\ + "0.424283, 0.424361, 0.424730, 0.425678, 0.427582",\ + "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\ + "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\ + "0.235860, 0.236040, 0.236883, 0.239059, 0.243424",\ + "0.297461, 0.297581, 0.298140, 0.299584, 0.302483",\ + "0.424284, 0.424363, 0.424730, 0.425678, 0.427582",\ + "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\ + "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\ + "0.235863, 0.236045, 0.236883, 0.239059, 0.243424",\ + "0.297463, 0.297583, 0.298140, 0.299584, 0.302483",\ + "0.424285, 0.424365, 0.424730, 0.425678, 0.427582",\ + "0.882507, 0.882519, 0.882580, 0.882733, 0.883038",\ + "2.159515, 2.159525, 2.159563, 2.159647, 2.159816",\ + "0.235880, 0.236097, 0.236905, 0.239068, 0.243424",\ + "0.297474, 0.297618, 0.298155, 0.299590, 0.302483",\ + "0.424293, 0.424387, 0.424740, 0.425682, 0.427582",\ + "0.882507, 0.882524, 0.882582, 0.882733, 0.883038",\ + "2.159515, 2.159528, 2.159564, 2.159647, 2.159816"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.367521, 0.579425, 0.836465, 1.278595, 2.162855",\ + "0.401633, 0.614821, 0.871879, 1.314094, 2.198523",\ + "0.451390, 0.668626, 0.925663, 1.367835, 2.252179",\ + "0.579943, 0.801765, 1.058753, 1.500789, 2.384860",\ + "0.915527, 1.146173, 1.403096, 1.844941, 2.728633",\ + "0.454931, 0.666901, 0.923947, 1.365310, 2.248789",\ + "0.489043, 0.702297, 0.959362, 1.400808, 2.284457",\ + "0.538801, 0.756101, 1.013145, 1.454550, 2.338113",\ + "0.667354, 0.889241, 1.146235, 1.587503, 2.470794",\ + "1.002937, 1.233649, 1.490577, 1.931656, 2.814567",\ + "0.535766, 0.755714, 1.011909, 1.452931, 2.335744",\ + "0.569878, 0.791110, 1.047324, 1.488430, 2.371412",\ + "0.619635, 0.844914, 1.101107, 1.542171, 2.425068",\ + "0.748188, 0.978053, 1.234197, 1.675125, 2.557749",\ + "1.083772, 1.322461, 1.578539, 2.019278, 2.901522",\ + "0.593373, 0.821105, 1.076045, 1.516845, 2.399253",\ + "0.627485, 0.856501, 1.111459, 1.552344, 2.434921",\ + "0.677243, 0.910304, 1.165242, 1.606085, 2.488577",\ + "0.805795, 1.043444, 1.298333, 1.739039, 2.621258",\ + "1.141379, 1.387851, 1.642674, 2.083191, 2.965031",\ + "0.895433, 1.182634, 1.427639, 1.866081, 2.744709",\ + "0.930201, 1.218028, 1.463055, 1.901580, 2.780377",\ + "0.984012, 1.271830, 1.516838, 1.955320, 2.834033",\ + "1.117159, 1.404967, 1.649927, 2.088274, 2.966714",\ + "1.461575, 1.749372, 1.994267, 2.432426, 3.310487"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.080902, 0.080967, 0.081775, 0.084238, 0.089162",\ + "0.117510, 0.117523, 0.117812, 0.118746, 0.120614",\ + "0.210641, 0.210651, 0.210781, 0.211182, 0.211986",\ + "0.448308, 0.448315, 0.448372, 0.448536, 0.448865",\ + "1.101372, 1.101392, 1.101478, 1.101676, 1.102071",\ + "0.080902, 0.080968, 0.081783, 0.084238, 0.089162",\ + "0.117510, 0.117523, 0.117815, 0.118746, 0.120614",\ + "0.210641, 0.210651, 0.210782, 0.211182, 0.211986",\ + "0.448308, 0.448315, 0.448373, 0.448536, 0.448865",\ + "1.101372, 1.101392, 1.101479, 1.101676, 1.102071",\ + "0.080902, 0.080970, 0.081783, 0.084238, 0.089162",\ + "0.117510, 0.117523, 0.117815, 0.118746, 0.120614",\ + "0.210641, 0.210651, 0.210782, 0.211182, 0.211986",\ + "0.448308, 0.448315, 0.448373, 0.448536, 0.448865",\ + "1.101372, 1.101393, 1.101479, 1.101676, 1.102071",\ + "0.080902, 0.080972, 0.081783, 0.084238, 0.089162",\ + "0.117510, 0.117524, 0.117815, 0.118746, 0.120614",\ + "0.210641, 0.210651, 0.210782, 0.211182, 0.211986",\ + "0.448308, 0.448315, 0.448373, 0.448536, 0.448865",\ + "1.101372, 1.101393, 1.101479, 1.101676, 1.102071",\ + "0.080902, 0.080995, 0.081808, 0.084248, 0.089162",\ + "0.117510, 0.117529, 0.117825, 0.118750, 0.120614",\ + "0.210641, 0.210655, 0.210786, 0.211184, 0.211986",\ + "0.448308, 0.448318, 0.448374, 0.448537, 0.448865",\ + "1.101372, 1.101400, 1.101481, 1.101677, 1.102071"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.350120, 0.565633, 0.746735, 1.037548, 1.600373",\ + "0.398981, 0.614494, 0.795596, 1.086408, 1.649232",\ + "0.501090, 0.716603, 0.897704, 1.188518, 1.751342",\ + "0.737189, 0.952702, 1.133804, 1.424618, 1.987443",\ + "1.308796, 1.524309, 1.705411, 1.996226, 2.559053",\ + "0.438515, 0.652951, 0.834015, 1.124853, 1.687726",\ + "0.487376, 0.701812, 0.882876, 1.173713, 1.736585",\ + "0.589485, 0.803921, 0.984985, 1.275823, 1.838695",\ + "0.825584, 1.040021, 1.221085, 1.511923, 2.074796",\ + "1.397191, 1.611628, 1.792692, 2.083531, 2.646406",\ + "0.527399, 0.733288, 0.914042, 1.204882, 1.767758",\ + "0.576260, 0.782149, 0.962903, 1.253742, 1.816617",\ + "0.678369, 0.884258, 1.065012, 1.355851, 1.918727",\ + "0.914468, 1.120357, 1.301112, 1.591951, 2.154828",\ + "1.486075, 1.691964, 1.872719, 2.163559, 2.726438",\ + "0.590410, 0.791118, 0.971742, 1.262314, 1.824777",\ + "0.639271, 0.839979, 1.020603, 1.311174, 1.873636",\ + "0.741380, 0.942088, 1.122712, 1.413283, 1.975746",\ + "0.977479, 1.178187, 1.358811, 1.649383, 2.211848",\ + "1.549087, 1.749794, 1.930419, 2.220991, 2.783457",\ + "0.913253, 1.096448, 1.275400, 1.565488, 2.127003",\ + "0.962113, 1.145308, 1.324261, 1.614348, 2.175863",\ + "1.064222, 1.247418, 1.426370, 1.716458, 2.277973",\ + "1.300322, 1.483517, 1.662469, 1.952558, 2.514074",\ + "1.871929, 2.055124, 2.234077, 2.524166, 3.085683"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\ + "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\ + "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\ + "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204",\ + "0.032791, 0.032791, 0.032792, 0.032797, 0.032808",\ + "0.150563, 0.150563, 0.150562, 0.150560, 0.150555",\ + "0.376248, 0.376248, 0.376248, 0.376247, 0.376244",\ + "0.869894, 0.869894, 0.869894, 0.869892, 0.869888",\ + "2.137202, 2.137202, 2.137202, 2.137203, 2.137204"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.373967, 0.592587, 0.771355, 1.061366, 1.624150",\ + "0.409637, 0.625150, 0.806253, 1.097068, 1.659896",\ + "0.450922, 0.666435, 0.847537, 1.138352, 1.701180",\ + "0.573066, 0.788579, 0.969681, 1.260496, 1.823323",\ + "0.905340, 1.120854, 1.301956, 1.592770, 2.155596",\ + "0.462362, 0.679906, 0.858636, 1.148671, 1.711503",\ + "0.498033, 0.712469, 0.893534, 1.184373, 1.747249",\ + "0.539317, 0.753753, 0.934818, 1.225657, 1.788534",\ + "0.661461, 0.875897, 1.056962, 1.347801, 1.910677",\ + "0.993736, 1.208172, 1.389236, 1.680075, 2.242949",\ + "0.551246, 0.760243, 0.938663, 1.228699, 1.791535",\ + "0.586916, 0.792806, 0.973560, 1.264401, 1.827281",\ + "0.628201, 0.834090, 1.014845, 1.305686, 1.868565",\ + "0.750345, 0.956234, 1.136989, 1.427829, 1.990708",\ + "1.082619, 1.288509, 1.469263, 1.760103, 2.322981",\ + "0.614257, 0.818060, 0.996357, 1.286131, 1.848554",\ + "0.649928, 0.850636, 1.031260, 1.321833, 1.884300",\ + "0.691212, 0.891920, 1.072545, 1.363118, 1.925585",\ + "0.813356, 1.014064, 1.194689, 1.485261, 2.047728",\ + "1.145631, 1.346339, 1.526963, 1.817535, 2.380001",\ + "0.943056, 1.123302, 1.300014, 1.589306, 2.150780",\ + "0.972770, 1.155965, 1.334918, 1.625008, 2.186526",\ + "1.014054, 1.197250, 1.376202, 1.666292, 2.227811",\ + "1.136198, 1.319394, 1.498346, 1.788436, 2.349954",\ + "1.468473, 1.651668, 1.830621, 2.120710, 2.682227"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\ + "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\ + "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\ + "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135",\ + "0.047453, 0.047453, 0.047453, 0.047451, 0.047447",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186056, 0.186055",\ + "0.432423, 0.432423, 0.432423, 0.432422, 0.432422",\ + "1.065140, 1.065140, 1.065140, 1.065138, 1.065135"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min_2531*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[57]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.331760, 0.553188, 0.742512, 1.045826, 1.632024",\ + "0.380621, 0.602049, 0.791372, 1.094686, 1.680882",\ + "0.482730, 0.704158, 0.893481, 1.196795, 1.782993",\ + "0.718830, 0.940258, 1.129582, 1.432896, 2.019095",\ + "1.290437, 1.511866, 1.701190, 2.004506, 2.590707",\ + "0.420081, 0.640507, 0.829793, 1.133131, 1.719378",\ + "0.468942, 0.689367, 0.878653, 1.181991, 1.768235",\ + "0.571051, 0.791476, 0.980762, 1.284101, 1.870346",\ + "0.807150, 1.027576, 1.216862, 1.520201, 2.106449",\ + "1.378757, 1.599184, 1.788471, 2.091811, 2.678061",\ + "0.509110, 0.720840, 0.909820, 1.213160, 1.799409",\ + "0.557971, 0.769701, 0.958680, 1.262019, 1.848267",\ + "0.660080, 0.871810, 1.060789, 1.364129, 1.950378",\ + "0.896179, 1.107910, 1.296889, 1.600230, 2.186480",\ + "1.467786, 1.679518, 1.868498, 2.171839, 2.758092",\ + "0.572416, 0.778663, 0.967540, 1.270620, 1.856487",\ + "0.621277, 0.827523, 1.016400, 1.319480, 1.905344",\ + "0.723386, 0.929632, 1.118510, 1.421590, 2.007455",\ + "0.959485, 1.165732, 1.354610, 1.657691, 2.243557",\ + "1.531092, 1.737340, 1.926218, 2.229300, 2.815169",\ + "0.903758, 1.083926, 1.271200, 1.573819, 2.158782",\ + "0.952619, 1.132786, 1.320060, 1.622678, 2.207640",\ + "1.054728, 1.234896, 1.422170, 1.724788, 2.309751",\ + "1.290827, 1.470996, 1.658270, 1.960889, 2.545854",\ + "1.862434, 2.042603, 2.229878, 2.532498, 3.117465"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.032790, 0.032796, 0.032799, 0.032806, 0.032822",\ + "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\ + "0.032790, 0.032796, 0.032799, 0.032806, 0.032822",\ + "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\ + "0.032791, 0.032796, 0.032799, 0.032806, 0.032822",\ + "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\ + "0.032791, 0.032796, 0.032799, 0.032806, 0.032822",\ + "0.150562, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204",\ + "0.032791, 0.032796, 0.032799, 0.032807, 0.032822",\ + "0.150563, 0.150560, 0.150559, 0.150556, 0.150549",\ + "0.376248, 0.376247, 0.376246, 0.376245, 0.376241",\ + "0.869894, 0.869894, 0.869894, 0.869893, 0.869890",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137204"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.355611, 0.590269, 0.779821, 1.083137, 1.669339",\ + "0.391278, 0.612708, 0.802032, 1.105348, 1.691551",\ + "0.432562, 0.653992, 0.843316, 1.146633, 1.732836",\ + "0.554706, 0.776136, 0.965460, 1.268776, 1.854978",\ + "0.886981, 1.108410, 1.297734, 1.601049, 2.187249",\ + "0.443930, 0.677587, 0.867102, 1.170442, 1.756692",\ + "0.479599, 0.700026, 0.889313, 1.192653, 1.778904",\ + "0.520883, 0.741310, 0.930597, 1.233938, 1.820189",\ + "0.643027, 0.863454, 1.052741, 1.356081, 1.942332",\ + "0.975302, 1.195728, 1.385015, 1.688354, 2.274603",\ + "0.532956, 0.757921, 0.947129, 1.250471, 1.836724",\ + "0.568627, 0.780360, 0.969340, 1.272682, 1.858936",\ + "0.609912, 0.821644, 1.010624, 1.313967, 1.900221",\ + "0.732056, 0.943788, 1.132768, 1.436110, 2.022363",\ + "1.064331, 1.276062, 1.465042, 1.768383, 2.354635",\ + "0.596259, 0.815760, 1.004849, 1.307931, 1.893801",\ + "0.631934, 0.838182, 1.027060, 1.330143, 1.916013",\ + "0.673218, 0.879466, 1.068345, 1.371427, 1.957298",\ + "0.795362, 1.001610, 1.190488, 1.493571, 2.079441",\ + "1.127637, 1.333884, 1.522762, 1.825843, 2.411712",\ + "0.930491, 1.121142, 1.308509, 1.611130, 2.196097",\ + "0.963275, 1.143445, 1.330720, 1.633341, 2.218309",\ + "1.004560, 1.184730, 1.372005, 1.674626, 2.259594",\ + "1.126704, 1.306873, 1.494148, 1.796769, 2.381737",\ + "1.458978, 1.639148, 1.826422, 2.129042, 2.714008"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002160, 0.075158, 0.162122, 0.322085, 0.642011"); + values ( "0.047454, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065141, 1.065139, 1.065138, 1.065135, 1.065130",\ + "0.047453, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065141, 1.065139, 1.065138, 1.065135, 1.065130",\ + "0.047453, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065140, 1.065139, 1.065138, 1.065135, 1.065130",\ + "0.047453, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065140, 1.065139, 1.065138, 1.065135, 1.065130",\ + "0.047452, 0.047451, 0.047450, 0.047447, 0.047442",\ + "0.092188, 0.092188, 0.092188, 0.092188, 0.092187",\ + "0.186056, 0.186056, 0.186056, 0.186055, 0.186055",\ + "0.432423, 0.432422, 0.432422, 0.432422, 0.432421",\ + "1.065140, 1.065139, 1.065138, 1.065135, 1.065130"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[58]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.441216, 0.635561, 0.817859, 1.110553, 1.677168",\ + "0.490035, 0.684380, 0.866679, 1.159372, 1.725988",\ + "0.592166, 0.786511, 0.968809, 1.261503, 1.828118",\ + "0.828311, 1.022655, 1.204954, 1.497648, 2.064263",\ + "1.399982, 1.594326, 1.776625, 2.069319, 2.635934",\ + "0.529420, 0.722878, 0.905140, 1.197858, 1.764521",\ + "0.578240, 0.771698, 0.953960, 1.246678, 1.813341",\ + "0.680371, 0.873829, 1.056091, 1.348809, 1.915472",\ + "0.916515, 1.109973, 1.292235, 1.584953, 2.151616",\ + "1.488186, 1.681644, 1.863906, 2.156624, 2.723287",\ + "0.618747, 0.803206, 0.985167, 1.277887, 1.844553",\ + "0.667567, 0.852026, 1.033987, 1.326706, 1.893373",\ + "0.769697, 0.954157, 1.136117, 1.428837, 1.995504",\ + "1.005842, 1.190301, 1.372262, 1.664981, 2.231648",\ + "1.577513, 1.761972, 1.943933, 2.236652, 2.803319",\ + "0.681460, 0.861042, 1.042871, 1.335324, 1.901586",\ + "0.730280, 0.909862, 1.091691, 1.384144, 1.950405",\ + "0.832411, 1.011993, 1.193822, 1.486274, 2.052536",\ + "1.068555, 1.248137, 1.429966, 1.722419, 2.288681",\ + "1.640226, 1.819808, 2.001637, 2.294090, 2.860352",\ + "0.985102, 1.166382, 1.346527, 1.638502, 2.203828",\ + "1.033922, 1.215202, 1.395347, 1.687321, 2.252647",\ + "1.136052, 1.317332, 1.497478, 1.789452, 2.354778",\ + "1.372197, 1.553477, 1.733622, 2.025596, 2.590923",\ + "1.943868, 2.125148, 2.305293, 2.597268, 3.162594"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\ + "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\ + "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\ + "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131",\ + "0.033216, 0.033216, 0.033216, 0.033216, 0.033216",\ + "0.150378, 0.150378, 0.150378, 0.150378, 0.150378",\ + "0.376160, 0.376160, 0.376160, 0.376160, 0.376160",\ + "0.870043, 0.870043, 0.870043, 0.870043, 0.870043",\ + "2.137131, 2.137131, 2.137131, 2.137131, 2.137131"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.478632, 0.663448, 0.845746, 1.138440, 1.705055",\ + "0.500859, 0.695203, 0.877502, 1.170196, 1.736811",\ + "0.542150, 0.736495, 0.918793, 1.211487, 1.778102",\ + "0.664276, 0.858621, 1.040919, 1.333613, 1.900228",\ + "0.996499, 1.190843, 1.373142, 1.665835, 2.232451",\ + "0.566836, 0.750765, 0.933027, 1.225745, 1.792408",\ + "0.589063, 0.782521, 0.964783, 1.257501, 1.824164",\ + "0.630354, 0.823812, 1.006074, 1.298792, 1.865455",\ + "0.752480, 0.945938, 1.128200, 1.420918, 1.987581",\ + "1.084703, 1.278161, 1.460423, 1.753141, 2.319804",\ + "0.651614, 0.831093, 1.013054, 1.305773, 1.872440",\ + "0.678390, 0.862849, 1.044810, 1.337529, 1.904196",\ + "0.719681, 0.904140, 1.086101, 1.378820, 1.945487",\ + "0.841807, 1.026266, 1.208227, 1.500947, 2.067613",\ + "1.174030, 1.358489, 1.540450, 1.833169, 2.399836",\ + "0.709347, 0.888930, 1.070759, 1.363211, 1.929473",\ + "0.741103, 0.920685, 1.102514, 1.394967, 1.961228",\ + "0.782394, 0.961976, 1.143806, 1.436258, 2.002520",\ + "0.904520, 1.084103, 1.265932, 1.558384, 2.124646",\ + "1.236743, 1.416325, 1.598154, 1.890607, 2.456868",\ + "1.012989, 1.194269, 1.374414, 1.666389, 2.231715",\ + "1.044745, 1.226025, 1.406170, 1.698144, 2.263471",\ + "1.086036, 1.267316, 1.447461, 1.739436, 2.304762",\ + "1.208162, 1.389442, 1.569587, 1.861562, 2.426888",\ + "1.540385, 1.721665, 1.901810, 2.193784, 2.759110"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003360, 0.076358, 0.163022, 0.322685, 0.642011"); + values ( "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\ + "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\ + "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\ + "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004",\ + "0.047293, 0.047293, 0.047293, 0.047293, 0.047293",\ + "0.092166, 0.092166, 0.092166, 0.092166, 0.092166",\ + "0.186036, 0.186036, 0.186036, 0.186036, 0.186036",\ + "0.432397, 0.432397, 0.432397, 0.432397, 0.432397",\ + "1.065004, 1.065004, 1.065004, 1.065004, 1.065004"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min_2476*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[62]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.348914, 0.525100, 0.702588, 0.991299, 1.552048",\ + "0.404496, 0.580679, 0.758142, 1.046740, 1.607235",\ + "0.479870, 0.656050, 0.833489, 1.121981, 1.682238",\ + "0.681478, 0.857653, 1.035056, 1.323386, 1.883276",\ + "1.225627, 1.401797, 1.579170, 1.867368, 2.426959",\ + "0.436324, 0.612419, 0.789869, 1.078604, 1.639402",\ + "0.491907, 0.667998, 0.845423, 1.134045, 1.694588",\ + "0.567281, 0.743368, 0.920770, 1.209286, 1.769591",\ + "0.768889, 0.944971, 1.122336, 1.410691, 1.970629",\ + "1.313037, 1.489116, 1.666451, 1.954674, 2.514312",\ + "0.517159, 0.692753, 0.869896, 1.158633, 1.719433",\ + "0.572742, 0.748332, 0.925450, 1.214074, 1.774620",\ + "0.648115, 0.823702, 1.000796, 1.289315, 1.849623",\ + "0.849723, 1.025305, 1.202363, 1.490720, 2.050661",\ + "1.393872, 1.569450, 1.746478, 2.034702, 2.594344",\ + "0.574766, 0.750569, 0.927588, 1.216063, 1.776449",\ + "0.630349, 0.806149, 0.983142, 1.271503, 1.831635",\ + "0.705722, 0.881519, 1.058488, 1.346744, 1.906637",\ + "0.907331, 1.083122, 1.260055, 1.548149, 2.107674",\ + "1.451479, 1.627266, 1.804170, 2.092131, 2.651357",\ + "0.876826, 1.055796, 1.231244, 1.519234, 2.078671",\ + "0.932408, 1.111374, 1.286798, 1.574675, 2.133856",\ + "1.007782, 1.186745, 1.362144, 1.649915, 2.208858",\ + "1.209389, 1.388348, 1.563711, 1.851319, 2.409893",\ + "1.753537, 1.932492, 2.107826, 2.395301, 2.953575"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243906",\ + "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\ + "2.138597, 2.138606, 2.138675, 2.138985, 2.139684",\ + "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243906",\ + "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\ + "2.138597, 2.138606, 2.138675, 2.138985, 2.139684",\ + "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243906",\ + "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\ + "2.138597, 2.138606, 2.138675, 2.138985, 2.139684",\ + "0.151029, 0.151029, 0.151029, 0.151092, 0.151248",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243907",\ + "0.409516, 0.409519, 0.409535, 0.409607, 0.409769",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874880",\ + "2.138597, 2.138606, 2.138675, 2.138986, 2.139686",\ + "0.151029, 0.151029, 0.151029, 0.151092, 0.151249",\ + "0.243808, 0.243808, 0.243808, 0.243837, 0.243907",\ + "0.409517, 0.409519, 0.409535, 0.409607, 0.409770",\ + "0.874760, 0.874761, 0.874769, 0.874803, 0.874881",\ + "2.138598, 2.138607, 2.138675, 2.138986, 2.139688"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.322905, 0.543708, 0.721197, 1.009915, 1.570680",\ + "0.358307, 0.577820, 0.755311, 1.044036, 1.604817",\ + "0.412119, 0.627577, 0.805068, 1.093794, 1.654579",\ + "0.545267, 0.756130, 0.933618, 1.222334, 1.783093",\ + "0.889685, 1.091714, 1.269206, 1.557937, 2.118731",\ + "0.411116, 0.631026, 0.808478, 1.097220, 1.658034",\ + "0.446518, 0.665138, 0.842591, 1.131341, 1.692170",\ + "0.500329, 0.714895, 0.892349, 1.181100, 1.741932",\ + "0.633477, 0.843448, 1.020899, 1.309639, 1.870447",\ + "0.977895, 1.179032, 1.356487, 1.645242, 2.206084",\ + "0.499788, 0.711360, 0.888505, 1.177248, 1.738065",\ + "0.535189, 0.745472, 0.922618, 1.211369, 1.772202",\ + "0.589001, 0.795229, 0.972376, 1.261128, 1.821964",\ + "0.722149, 0.923782, 1.100926, 1.389667, 1.950478",\ + "1.066566, 1.259366, 1.436514, 1.725270, 2.286115",\ + "0.562748, 0.769177, 0.946197, 1.234678, 1.795081",\ + "0.598149, 0.803289, 0.980311, 1.268799, 1.829218",\ + "0.651961, 0.853046, 1.030068, 1.318558, 1.878979",\ + "0.785108, 0.981599, 1.158618, 1.447097, 2.007494",\ + "1.129526, 1.317183, 1.494206, 1.782700, 2.343131",\ + "0.894800, 1.074403, 1.249853, 1.537850, 2.097302",\ + "0.929545, 1.108515, 1.283966, 1.571971, 2.131439",\ + "0.979303, 1.158272, 1.333724, 1.621730, 2.181201",\ + "1.107856, 1.286825, 1.462274, 1.750269, 2.309716",\ + "1.443439, 1.622409, 1.797862, 2.085872, 2.645353"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002088, 0.075087, 0.162069, 0.322049, 0.642011"); + values ( "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432555, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065609, 1.065728",\ + "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432555, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065609, 1.065728",\ + "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432554, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065609, 1.065728",\ + "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432554, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065610, 1.065728",\ + "0.073594, 0.073593, 0.073590, 0.073574, 0.073539",\ + "0.105770, 0.105770, 0.105771, 0.105778, 0.105792",\ + "0.191100, 0.191101, 0.191103, 0.191113, 0.191136",\ + "0.432554, 0.432553, 0.432541, 0.432487, 0.432365",\ + "1.065544, 1.065545, 1.065557, 1.065610, 1.065729"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[9]_redg_min_2427*/ + +} /* end of pin tl_o[9] */ + +pin("tl_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.154883 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.373916, 0.599728, 0.894574, 1.388503, 2.376363",\ + "0.415183, 0.640172, 0.934074, 1.428691, 2.417925",\ + "0.491066, 0.715879, 1.009866, 1.504530, 2.493859",\ + "0.745862, 0.970981, 1.264787, 1.759400, 2.748624",\ + "1.670986, 1.894752, 2.189083, 2.684630, 3.675724",\ + "0.461357, 0.687335, 0.982222, 1.475219, 2.462296",\ + "0.502624, 0.727773, 1.021724, 1.515406, 2.503859",\ + "0.578507, 0.803480, 1.097517, 1.591246, 2.579792",\ + "0.833304, 1.058581, 1.352438, 1.846115, 2.834558",\ + "1.758428, 1.982354, 2.276736, 2.771345, 3.761657",\ + "0.542237, 0.776480, 1.070189, 1.562842, 2.549252",\ + "0.583504, 0.816901, 1.109691, 1.603029, 2.590814",\ + "0.659387, 0.892609, 1.185483, 1.678869, 2.666748",\ + "0.914185, 1.147708, 1.440404, 1.933738, 2.921513",\ + "1.839308, 2.071485, 2.364703, 2.858968, 3.848613",\ + "0.599958, 0.842354, 1.134332, 1.626756, 2.612761",\ + "0.641225, 0.882751, 1.173835, 1.666943, 2.654323",\ + "0.717108, 0.958461, 1.249627, 1.742782, 2.730257",\ + "0.971907, 1.213556, 1.504548, 1.997652, 2.985022",\ + "1.897030, 2.137338, 2.428847, 2.922882, 3.912122",\ + "0.902648, 1.209455, 1.486456, 1.976211, 2.958217",\ + "0.943914, 1.249574, 1.525966, 2.016402, 2.999779",\ + "1.019797, 1.325301, 1.601758, 2.092241, 3.075712",\ + "1.274609, 1.580356, 1.856679, 2.347110, 3.330478",\ + "2.199727, 2.504201, 2.780987, 3.272345, 4.257577"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.034807, 0.034870, 0.035021, 0.035342, 0.035983",\ + "0.083278, 0.083283, 0.083326, 0.083445, 0.083683",\ + "0.208556, 0.208575, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692980, 0.693734, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\ + "0.034807, 0.034871, 0.035022, 0.035342, 0.035983",\ + "0.083278, 0.083283, 0.083327, 0.083445, 0.083683",\ + "0.208556, 0.208576, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692982, 0.693734, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\ + "0.034807, 0.034872, 0.035022, 0.035342, 0.035983",\ + "0.083278, 0.083284, 0.083327, 0.083445, 0.083683",\ + "0.208556, 0.208576, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692982, 0.693734, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\ + "0.034808, 0.034873, 0.035022, 0.035342, 0.035983",\ + "0.083278, 0.083284, 0.083327, 0.083445, 0.083683",\ + "0.208556, 0.208577, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692982, 0.693734, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403",\ + "0.034810, 0.034887, 0.035026, 0.035343, 0.035983",\ + "0.083278, 0.083286, 0.083328, 0.083446, 0.083683",\ + "0.208556, 0.208584, 0.208609, 0.208619, 0.208640",\ + "0.692765, 0.692765, 0.692990, 0.693737, 0.695242",\ + "2.477403, 2.477403, 2.477403, 2.477403, 2.477403"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.420490, 0.645190, 0.938944, 1.432430, 2.419402",\ + "0.461359, 0.686264, 0.979881, 1.473291, 2.460111",\ + "0.521542, 0.746363, 1.040033, 1.533430, 2.520226",\ + "0.690406, 0.915382, 1.209000, 1.702350, 2.689050",\ + "1.273072, 1.496794, 1.790318, 2.283708, 3.270487",\ + "0.507931, 0.732792, 1.026591, 1.519145, 2.505336",\ + "0.548801, 0.773865, 1.067528, 1.560006, 2.546045",\ + "0.608983, 0.833965, 1.127680, 1.620146, 2.606159",\ + "0.777848, 1.002983, 1.296647, 1.789066, 2.774984",\ + "1.360514, 1.584395, 1.877965, 2.370424, 3.356421",\ + "0.588811, 0.821923, 1.114557, 1.606768, 2.592291",\ + "0.629680, 0.862994, 1.155494, 1.647629, 2.633000",\ + "0.689863, 0.923095, 1.215646, 1.707769, 2.693114",\ + "0.858728, 1.092113, 1.384613, 1.876689, 2.861939",\ + "1.441395, 1.673523, 1.965932, 2.458046, 3.443376",\ + "0.646531, 0.887777, 1.178701, 1.670682, 2.655800",\ + "0.687400, 0.928846, 1.219638, 1.711543, 2.696509",\ + "0.747584, 0.988947, 1.279790, 1.771683, 2.756623",\ + "0.916448, 1.157964, 1.448757, 1.940602, 2.925448",\ + "1.499118, 1.739372, 2.030076, 2.521960, 3.506885",\ + "0.949211, 1.254642, 1.530820, 2.020136, 3.001256",\ + "0.990081, 1.295683, 1.571756, 2.060997, 3.041965",\ + "1.050271, 1.355798, 1.631908, 2.121136, 3.102079",\ + "1.219138, 1.524806, 1.800875, 2.290056, 3.270904",\ + "1.801826, 2.106188, 2.382194, 2.871414, 3.852341"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.042658, 0.042646, 0.042619, 0.042581, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155279, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431019, 0.430882, 0.430609",\ + "1.497229, 1.495745, 1.494360, 1.494360, 1.494360",\ + "0.042658, 0.042646, 0.042618, 0.042581, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155279, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431018, 0.430882, 0.430609",\ + "1.497229, 1.495736, 1.494360, 1.494360, 1.494360",\ + "0.042658, 0.042646, 0.042618, 0.042581, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155279, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431018, 0.430882, 0.430609",\ + "1.497225, 1.495716, 1.494360, 1.494360, 1.494360",\ + "0.042658, 0.042646, 0.042618, 0.042581, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155278, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431018, 0.430882, 0.430609",\ + "1.497218, 1.495687, 1.494360, 1.494360, 1.494360",\ + "0.042658, 0.042642, 0.042618, 0.042580, 0.042505",\ + "0.078946, 0.078946, 0.078946, 0.078946, 0.078946",\ + "0.155293, 0.155293, 0.155278, 0.155230, 0.155132",\ + "0.431058, 0.431058, 0.431017, 0.430882, 0.430609",\ + "1.497153, 1.495349, 1.494360, 1.494360, 1.494360"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2694*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.746021, 1.001665, 1.285647, 1.784442, 2.782033",\ + "0.780412, 1.036056, 1.320037, 1.818832, 2.816423",\ + "0.851654, 1.107299, 1.391280, 1.890076, 2.887667",\ + "1.105821, 1.361465, 1.645446, 2.144242, 3.141833",\ + "2.030393, 2.286036, 2.570016, 3.068810, 4.066399",\ + "0.833430, 1.089212, 1.373307, 1.871157, 2.867967",\ + "0.867821, 1.123603, 1.407697, 1.905547, 2.902357",\ + "0.939063, 1.194845, 1.478940, 1.976790, 2.973600",\ + "1.193229, 1.449012, 1.733106, 2.230957, 3.227767",\ + "2.117802, 2.373583, 2.657676, 3.155524, 4.152333",\ + "0.914308, 1.178178, 1.461272, 1.958778, 2.954922",\ + "0.948698, 1.212569, 1.495662, 1.993168, 2.989312",\ + "1.019941, 1.283811, 1.566905, 2.064412, 3.060555",\ + "1.274107, 1.537978, 1.821072, 2.318578, 3.314722",\ + "2.198680, 2.462549, 2.745641, 3.243146, 4.239288",\ + "0.974568, 1.243791, 1.525417, 2.022691, 3.018431",\ + "1.008959, 1.278181, 1.559807, 2.057082, 3.052821",\ + "1.080201, 1.349424, 1.631050, 2.128325, 3.124064",\ + "1.334368, 1.603591, 1.885216, 2.382491, 3.378231",\ + "2.258940, 2.528162, 2.809785, 3.307059, 4.302797",\ + "1.309682, 1.607944, 1.877586, 2.372160, 3.363887",\ + "1.344072, 1.642334, 1.911976, 2.406550, 3.398277",\ + "1.415315, 1.713577, 1.983219, 2.477793, 3.469521",\ + "1.669481, 1.967744, 2.237385, 2.731960, 3.723687",\ + "2.594053, 2.892314, 3.161954, 3.656528, 4.648253"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208405, 0.208405, 0.208405",\ + "0.692758, 0.692758, 0.692759, 0.692761, 0.692766",\ + "2.464359, 2.464359, 2.464359, 2.464359, 2.464359"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.777783, 1.033425, 1.317405, 1.816199, 2.813788",\ + "0.819535, 1.075178, 1.359157, 1.857951, 2.855540",\ + "0.879465, 1.135108, 1.419087, 1.917882, 2.915471",\ + "1.047583, 1.303225, 1.587205, 2.085999, 3.083588",\ + "1.629496, 1.885133, 2.169106, 2.667897, 3.665479",\ + "0.865191, 1.120972, 1.405064, 1.902913, 2.899722",\ + "0.906944, 1.162724, 1.446817, 1.944666, 2.941474",\ + "0.966874, 1.222655, 1.506747, 2.004596, 3.001405",\ + "1.134991, 1.390772, 1.674865, 2.172714, 3.169522",\ + "1.716905, 1.972680, 2.256766, 2.754611, 3.751413",\ + "0.946069, 1.209938, 1.493030, 1.990535, 2.986677",\ + "0.987822, 1.251690, 1.534782, 2.032288, 3.028429",\ + "1.047752, 1.311621, 1.594713, 2.092218, 3.088360",\ + "1.215869, 1.479738, 1.762830, 2.260335, 3.256477",\ + "1.797783, 2.061646, 2.344732, 2.842233, 3.838368",\ + "1.006330, 1.275551, 1.557174, 2.054448, 3.050186",\ + "1.048082, 1.317303, 1.598927, 2.096201, 3.091938",\ + "1.108012, 1.377234, 1.658857, 2.156131, 3.151869",\ + "1.276130, 1.545351, 1.826975, 2.324248, 3.319986",\ + "1.858043, 2.127259, 2.408876, 2.906147, 3.901877",\ + "1.341443, 1.639703, 1.909343, 2.403917, 3.395642",\ + "1.383195, 1.681456, 1.951096, 2.445669, 3.437394",\ + "1.443126, 1.741386, 2.011026, 2.505599, 3.497324",\ + "1.611243, 1.909503, 2.179143, 2.673717, 3.665442",\ + "2.193155, 2.491410, 2.761045, 3.255615, 4.247333"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2719*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.329434, 0.567970, 0.849310, 1.349062, 2.348564",\ + "0.370729, 0.609110, 0.889780, 1.387186, 2.381998",\ + "0.446657, 0.684926, 0.965184, 1.461121, 2.452996",\ + "0.702252, 0.940104, 1.219789, 1.715647, 2.707363",\ + "1.626635, 1.863892, 2.145200, 2.640602, 3.631406",\ + "0.416843, 0.655497, 0.936973, 1.435776, 2.434498",\ + "0.458138, 0.696638, 0.977436, 1.473900, 2.467931",\ + "0.534066, 0.772454, 1.052835, 1.547836, 2.538929",\ + "0.789661, 1.027628, 1.307440, 1.802361, 2.793297",\ + "1.714044, 1.951428, 2.232849, 2.727316, 3.717340",\ + "0.497703, 0.744421, 1.024939, 1.523398, 2.521453",\ + "0.538998, 0.785561, 1.065401, 1.561522, 2.554886",\ + "0.614927, 0.861378, 1.140800, 1.635457, 2.625884",\ + "0.870521, 1.116544, 1.395405, 1.889983, 2.880252",\ + "1.794904, 2.040369, 2.320814, 2.814938, 3.804295",\ + "0.555377, 0.809972, 1.089084, 1.587311, 2.584962",\ + "0.596671, 0.851113, 1.129546, 1.625435, 2.618395",\ + "0.672599, 0.926930, 1.204945, 1.699371, 2.689393",\ + "0.928193, 1.182084, 1.459549, 1.953896, 2.943761",\ + "1.852575, 2.105947, 2.384958, 2.878851, 3.867804",\ + "0.876916, 1.173402, 1.441262, 1.936784, 2.930418",\ + "0.918063, 1.214545, 1.481701, 1.974898, 2.963851",\ + "0.993829, 1.290365, 1.557085, 2.048828, 3.034849",\ + "1.249296, 1.545383, 1.811688, 2.303353, 3.289217",\ + "2.172819, 2.469679, 2.737093, 3.228306, 4.213260"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.035016, 0.035016, 0.035955, 0.039196, 0.045676",\ + "0.083549, 0.083549, 0.083885, 0.085044, 0.087361",\ + "0.208718, 0.208718, 0.208874, 0.209415, 0.210496",\ + "0.692609, 0.692819, 0.692927, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477148, 2.477552, 2.478359",\ + "0.035016, 0.035016, 0.035965, 0.039196, 0.045676",\ + "0.083549, 0.083549, 0.083888, 0.085044, 0.087361",\ + "0.208718, 0.208718, 0.208876, 0.209415, 0.210496",\ + "0.692609, 0.692820, 0.692927, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477552, 2.478359",\ + "0.035016, 0.035016, 0.035966, 0.039196, 0.045676",\ + "0.083549, 0.083549, 0.083888, 0.085044, 0.087361",\ + "0.208718, 0.208718, 0.208876, 0.209415, 0.210496",\ + "0.692610, 0.692821, 0.692927, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477552, 2.478359",\ + "0.035016, 0.035016, 0.035966, 0.039196, 0.045676",\ + "0.083549, 0.083549, 0.083889, 0.085044, 0.087361",\ + "0.208718, 0.208718, 0.208876, 0.209415, 0.210496",\ + "0.692612, 0.692822, 0.692927, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477552, 2.478359",\ + "0.035016, 0.035016, 0.035999, 0.039209, 0.045676",\ + "0.083549, 0.083549, 0.083900, 0.085048, 0.087361",\ + "0.208718, 0.208718, 0.208882, 0.209417, 0.210496",\ + "0.692711, 0.692838, 0.692929, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477154, 2.477553, 2.478359"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.376302, 0.614890, 0.892196, 1.378119, 2.349964",\ + "0.417201, 0.655792, 0.932845, 1.417492, 2.386786",\ + "0.477347, 0.716035, 0.992408, 1.474614, 2.439025",\ + "0.646325, 0.884988, 1.160689, 1.640497, 2.600112",\ + "1.229570, 1.466407, 1.742451, 2.222424, 3.182369",\ + "0.463711, 0.702417, 0.979816, 1.464833, 2.435898",\ + "0.504610, 0.743320, 1.020461, 1.504206, 2.472719",\ + "0.564756, 0.803563, 1.080016, 1.561328, 2.524959",\ + "0.733734, 0.972517, 1.248289, 1.727211, 2.686046",\ + "1.316979, 1.553937, 1.830052, 2.309139, 3.268303",\ + "0.544574, 0.791340, 1.067780, 1.552455, 2.522853",\ + "0.585473, 0.832245, 1.108425, 1.591828, 2.559674",\ + "0.645618, 0.892489, 1.167980, 1.648950, 2.611914",\ + "0.814594, 1.061442, 1.336253, 1.814833, 2.773001",\ + "1.397827, 1.642867, 1.918017, 2.396760, 3.355258",\ + "0.602253, 0.856891, 1.131923, 1.616368, 2.586362",\ + "0.643149, 0.897798, 1.172568, 1.655741, 2.623183",\ + "0.703295, 0.958043, 1.232122, 1.712863, 2.675423",\ + "0.872267, 1.126997, 1.400395, 1.878746, 2.836510",\ + "1.455475, 1.708427, 1.982158, 2.460673, 3.418767",\ + "0.923807, 1.220314, 1.483961, 1.965784, 2.931818",\ + "0.964736, 1.261250, 1.524593, 2.005152, 2.968639",\ + "1.024895, 1.321501, 1.584123, 2.062263, 3.020879",\ + "1.193870, 1.490460, 1.752371, 2.228136, 3.181966",\ + "1.775178, 2.071965, 2.334136, 2.810064, 3.764223"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.042685, 0.042788, 0.042938, 0.042938, 0.042938",\ + "0.078477, 0.079298, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042789, 0.042938, 0.042938, 0.042938",\ + "0.078477, 0.079299, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042791, 0.042938, 0.042938, 0.042938",\ + "0.078482, 0.079299, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042794, 0.042938, 0.042938, 0.042938",\ + "0.078491, 0.079301, 0.079365, 0.079365, 0.079365",\ + "0.155271, 0.155315, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042831, 0.042938, 0.042938, 0.042938",\ + "0.078956, 0.079318, 0.079365, 0.079365, 0.079365",\ + "0.155294, 0.155316, 0.155322, 0.155322, 0.155322",\ + "0.431182, 0.431182, 0.431182, 0.431182, 0.431182",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.731951, 0.980905, 1.256242, 1.719746, 2.646754",\ + "0.766341, 1.015295, 1.290632, 1.754136, 2.681144",\ + "0.837584, 1.086538, 1.361876, 1.825380, 2.752387",\ + "1.091750, 1.340704, 1.616042, 2.079546, 3.006554",\ + "2.016322, 2.265275, 2.540610, 3.004114, 3.931121",\ + "0.819353, 1.068475, 1.343788, 1.806459, 2.732687",\ + "0.853744, 1.102866, 1.378179, 1.840850, 2.767077",\ + "0.924986, 1.174109, 1.449422, 1.912093, 2.838321",\ + "1.179153, 1.428275, 1.703588, 2.166259, 3.092487",\ + "2.103725, 2.352845, 2.628156, 3.090827, 4.017055",\ + "0.900166, 1.157465, 1.431751, 1.894080, 2.819643",\ + "0.934556, 1.191856, 1.466141, 1.928470, 2.854033",\ + "1.005799, 1.263098, 1.537384, 1.999714, 2.925276",\ + "1.259965, 1.517265, 1.791550, 2.253880, 3.179442",\ + "2.184537, 2.441835, 2.716118, 3.178448, 4.104010",\ + "0.957806, 1.223112, 1.495889, 1.957993, 2.883152",\ + "0.992196, 1.257502, 1.530279, 1.992383, 2.917542",\ + "1.063439, 1.328745, 1.601523, 2.063626, 2.988785",\ + "1.317605, 1.582911, 1.855689, 2.317793, 3.242951",\ + "2.242177, 2.507481, 2.780257, 3.242361, 4.167519",\ + "1.292888, 1.587742, 1.847697, 2.307310, 3.228608",\ + "1.327278, 1.622132, 1.882087, 2.341700, 3.262998",\ + "1.398521, 1.693375, 1.953330, 2.412943, 3.334241",\ + "1.652687, 1.947541, 2.207496, 2.667110, 3.588408",\ + "2.577259, 2.872111, 3.132065, 3.591678, 4.512975"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083751",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692758, 0.692758, 0.692759, 0.692760, 0.692764",\ + "2.464354, 2.464354, 2.464354, 2.464354, 2.464354"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.763712, 1.012664, 1.287999, 1.751503, 2.678509",\ + "0.805464, 1.054416, 1.329752, 1.793255, 2.720262",\ + "0.865395, 1.114347, 1.389682, 1.853185, 2.780192",\ + "1.033512, 1.282464, 1.557799, 2.021303, 2.948309",\ + "1.615425, 1.864370, 2.139697, 2.603199, 3.530203",\ + "0.851115, 1.100234, 1.375545, 1.838216, 2.764443",\ + "0.892867, 1.141987, 1.417298, 1.879968, 2.806196",\ + "0.952797, 1.201917, 1.477228, 1.939899, 2.866126",\ + "1.120914, 1.370034, 1.645345, 2.108016, 3.034243",\ + "1.702827, 1.951940, 2.227243, 2.689913, 3.616137",\ + "0.931927, 1.189224, 1.463507, 1.925837, 2.851398",\ + "0.973680, 1.230977, 1.505260, 1.967589, 2.893151",\ + "1.033610, 1.290907, 1.565190, 2.027519, 2.953081",\ + "1.201727, 1.459024, 1.733307, 2.195637, 3.121198",\ + "1.783640, 2.040930, 2.315206, 2.777534, 3.703092",\ + "0.989567, 1.254871, 1.527646, 1.989749, 2.914907",\ + "1.031319, 1.296623, 1.569398, 2.031502, 2.956660",\ + "1.091250, 1.356553, 1.629329, 2.091432, 3.016590",\ + "1.259367, 1.524671, 1.797446, 2.259549, 3.184707",\ + "1.841280, 2.106576, 2.379344, 2.841446, 3.766601",\ + "1.324649, 1.619500, 1.879453, 2.339067, 3.260363",\ + "1.366401, 1.661253, 1.921206, 2.380819, 3.302116",\ + "1.426332, 1.721183, 1.981136, 2.440749, 3.362046",\ + "1.594449, 1.889300, 2.149253, 2.608866, 3.530163",\ + "2.176360, 2.471204, 2.731152, 3.190763, 4.112057"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2432*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.602525, 0.840752, 1.118848, 1.606867, 2.582905",\ + "0.636915, 0.875142, 1.153247, 1.641296, 2.617393",\ + "0.708158, 0.946386, 1.224478, 1.712482, 2.688491",\ + "0.962324, 1.200552, 1.478688, 1.966845, 2.943158",\ + "1.886897, 2.125118, 2.403212, 2.891220, 3.867236",\ + "0.689934, 0.928280, 1.206475, 1.693581, 2.668839",\ + "0.724325, 0.962670, 1.240873, 1.728010, 2.703327",\ + "0.795567, 1.033914, 1.312104, 1.799197, 2.774425",\ + "1.049734, 1.288080, 1.566315, 2.053559, 3.029092",\ + "1.974307, 2.212646, 2.490838, 2.977934, 3.953170",\ + "0.770795, 1.017206, 1.294439, 1.781203, 2.755794",\ + "0.805185, 1.051596, 1.328838, 1.815632, 2.790282",\ + "0.876428, 1.122840, 1.400069, 1.886818, 2.861380",\ + "1.130594, 1.377006, 1.654280, 2.141181, 3.116047",\ + "2.055167, 2.301572, 2.578803, 3.065556, 4.040125",\ + "0.828465, 1.082761, 1.358582, 1.845116, 2.819303",\ + "0.862855, 1.117151, 1.392981, 1.879545, 2.853791",\ + "0.934098, 1.188395, 1.464212, 1.950732, 2.924889",\ + "1.188264, 1.442561, 1.718422, 2.205094, 3.179556",\ + "2.112837, 2.367127, 2.642946, 3.129469, 4.103634",\ + "1.149414, 1.446227, 1.710642, 2.194541, 3.164759",\ + "1.183804, 1.480617, 1.745041, 2.228970, 3.199247",\ + "1.255047, 1.551860, 1.816271, 2.300156, 3.270345",\ + "1.509214, 1.806027, 2.070484, 2.554519, 3.525012",\ + "2.433782, 2.730593, 2.995005, 3.478894, 4.449090"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083749, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692757, 0.692767, 0.692798, 0.692859",\ + "2.464362, 2.464362, 2.464362, 2.464362, 2.464362"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.634287, 0.872507, 1.150200, 1.636823, 2.610071",\ + "0.676039, 0.914259, 1.192001, 1.678792, 2.652375",\ + "0.735970, 0.974190, 1.251983, 1.738955, 2.712900",\ + "0.904087, 1.142307, 1.420172, 1.907391, 2.881829",\ + "1.486003, 1.724197, 2.002198, 2.489875, 3.465229",\ + "0.721696, 0.960035, 1.237821, 1.723538, 2.696005",\ + "0.763449, 1.001787, 1.279623, 1.765507, 2.738309",\ + "0.823379, 1.061718, 1.339606, 1.825670, 2.798834",\ + "0.991496, 1.229835, 1.507796, 1.994106, 2.967763",\ + "1.573412, 1.811725, 2.089823, 2.576589, 3.551162",\ + "0.802557, 1.048961, 1.325786, 1.811159, 2.782960",\ + "0.844309, 1.090713, 1.367588, 1.853128, 2.825264",\ + "0.904240, 1.150644, 1.427571, 1.913292, 2.885789",\ + "1.072357, 1.318761, 1.595761, 2.081728, 3.054718",\ + "1.654273, 1.900651, 2.177788, 2.664211, 3.638118",\ + "0.860227, 1.114515, 1.389929, 1.875073, 2.846469",\ + "0.901979, 1.156268, 1.431731, 1.917042, 2.888773",\ + "0.961910, 1.216198, 1.491714, 1.977205, 2.949298",\ + "1.130027, 1.384316, 1.659903, 2.145641, 3.118227",\ + "1.711942, 1.966206, 2.241930, 2.728124, 3.701627",\ + "1.181171, 1.477981, 1.741974, 2.224492, 3.191925",\ + "1.222923, 1.519734, 1.783778, 2.266461, 3.234229",\ + "1.282854, 1.579664, 1.843763, 2.326625, 3.294754",\ + "1.450971, 1.747782, 2.011955, 2.495062, 3.463683",\ + "2.032870, 2.329673, 2.593987, 3.077547, 4.047082"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494119, 1.494120, 1.494126, 1.494136"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2526*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.555636, 0.806104, 1.084905, 1.584821, 2.584653",\ + "0.590029, 0.840498, 1.119303, 1.619235, 2.619098",\ + "0.661266, 0.911734, 1.190528, 1.690421, 2.690205",\ + "0.915433, 1.165901, 1.444770, 1.944926, 2.945236",\ + "1.840038, 2.090508, 2.369324, 2.869289, 3.869217",\ + "0.643048, 0.893609, 1.172570, 1.671536, 2.670587",\ + "0.677441, 0.928003, 1.206968, 1.705950, 2.705032",\ + "0.748679, 0.999240, 1.278193, 1.777135, 2.776139",\ + "1.002845, 1.253406, 1.532436, 2.031641, 3.031170",\ + "1.927450, 2.178014, 2.456990, 2.956004, 3.955151",\ + "0.723905, 0.982497, 1.260536, 1.759158, 2.757542",\ + "0.758298, 1.016890, 1.294935, 1.793572, 2.791987",\ + "0.829535, 1.088127, 1.366160, 1.864758, 2.863094",\ + "1.083702, 1.342294, 1.620402, 2.119263, 3.118125",\ + "2.008307, 2.266901, 2.544956, 3.043626, 4.042106",\ + "0.781799, 1.047996, 1.324681, 1.823071, 2.821051",\ + "0.816193, 1.082390, 1.359079, 1.857485, 2.855496",\ + "0.887430, 1.153626, 1.430304, 1.928671, 2.926603",\ + "1.141596, 1.407793, 1.684547, 2.183176, 3.181634",\ + "2.066201, 2.332401, 2.609101, 3.107539, 4.105615",\ + "1.114657, 1.410772, 1.676864, 2.172549, 3.166507",\ + "1.149050, 1.445166, 1.711262, 2.206963, 3.200952",\ + "1.220287, 1.516402, 1.782487, 2.278148, 3.272059",\ + "1.474454, 1.770569, 2.036732, 2.532654, 3.527090",\ + "2.399059, 2.695177, 2.961284, 3.457017, 4.451071"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466091, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465200, 2.466101, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083751, 0.083752, 0.083762, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692768, 0.692812, 0.692941, 0.693203",\ + "2.465173, 2.465210, 2.466131, 2.469072, 2.474999"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.587433, 0.837905, 1.116317, 1.614875, 2.611990",\ + "0.629185, 0.879656, 1.158119, 1.656853, 2.654322",\ + "0.689115, 0.939586, 1.218100, 1.717010, 2.714829",\ + "0.857231, 1.107703, 1.386286, 1.885441, 2.883749",\ + "1.439262, 1.689742, 1.968444, 2.467987, 3.467073",\ + "0.674846, 0.925410, 1.203978, 1.701590, 2.697924",\ + "0.716597, 0.967161, 1.245781, 1.743568, 2.740255",\ + "0.776528, 1.027092, 1.305762, 1.803725, 2.800763",\ + "0.944644, 1.195208, 1.473949, 1.972156, 2.969683",\ + "1.526675, 1.777247, 2.056108, 2.554702, 3.553007",\ + "0.755703, 1.014297, 1.291944, 1.789212, 2.784879",\ + "0.797454, 1.056048, 1.333747, 1.831190, 2.827210",\ + "0.857384, 1.115979, 1.393728, 1.891347, 2.887718",\ + "1.025501, 1.284095, 1.561916, 2.059778, 3.056638",\ + "1.607531, 1.866135, 2.144074, 2.642324, 3.639962",\ + "0.813597, 1.079797, 1.356089, 1.853126, 2.848388",\ + "0.855349, 1.121548, 1.397891, 1.895104, 2.890719",\ + "0.915279, 1.181478, 1.457873, 1.955260, 2.951227",\ + "1.083395, 1.349595, 1.626060, 2.123692, 3.120147",\ + "1.665427, 1.931634, 2.208219, 2.706238, 3.703471",\ + "1.146455, 1.442573, 1.708257, 2.202597, 3.193844",\ + "1.188207, 1.484324, 1.750062, 2.244576, 3.236176",\ + "1.248137, 1.544255, 1.810045, 2.304733, 3.296683",\ + "1.416253, 1.712371, 1.978235, 2.473166, 3.465603",\ + "1.998287, 2.294412, 2.560398, 3.055713, 4.048927"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045874, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155802, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2616*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.634427, 0.872697, 1.149292, 1.635475, 2.607842",\ + "0.668851, 0.907120, 1.183712, 1.669888, 2.642240",\ + "0.739833, 0.978100, 1.254713, 1.740957, 2.713446",\ + "0.993985, 1.232251, 1.508868, 1.995127, 2.967646",\ + "1.919059, 2.157313, 2.433878, 2.919960, 3.892124",\ + "0.721829, 0.960233, 1.236908, 1.722188, 2.693776",\ + "0.756252, 0.994656, 1.271329, 1.756601, 2.728174",\ + "0.827235, 1.065637, 1.342330, 1.827670, 2.799379",\ + "1.081387, 1.319787, 1.596485, 2.081840, 3.053579",\ + "2.006460, 2.244850, 2.521494, 3.006673, 3.978058",\ + "0.802677, 1.049143, 1.324872, 1.809809, 2.780731",\ + "0.837101, 1.083566, 1.359292, 1.844222, 2.815129",\ + "0.908083, 1.154546, 1.430293, 1.915291, 2.886334",\ + "1.162235, 1.408697, 1.684448, 2.169461, 3.140534",\ + "2.087309, 2.333760, 2.609457, 3.094293, 4.065013",\ + "0.860401, 1.114674, 1.389014, 1.873721, 2.844240",\ + "0.894825, 1.149096, 1.423434, 1.908134, 2.878638",\ + "0.965807, 1.220077, 1.494435, 1.979203, 2.949843",\ + "1.219959, 1.474228, 1.748591, 2.233373, 3.204043",\ + "2.145033, 2.399290, 2.673600, 3.158206, 4.128522",\ + "1.188527, 1.477957, 1.741051, 2.223131, 3.189696",\ + "1.222950, 1.512379, 1.775471, 2.257544, 3.224094",\ + "1.293931, 1.583360, 1.846473, 2.328613, 3.295300",\ + "1.548083, 1.837511, 2.100628, 2.582783, 3.549500",\ + "2.473149, 2.762573, 3.025636, 3.507615, 4.473978"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.034240, 0.034240, 0.034242, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083588, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.661467, 0.899737, 1.176348, 1.662586, 2.635063",\ + "0.703763, 0.942033, 1.218582, 1.704611, 2.676670",\ + "0.764325, 1.002595, 1.279082, 1.764899, 2.736534",\ + "0.933255, 1.171525, 1.447944, 1.933534, 2.904712",\ + "1.516509, 1.754779, 2.031088, 2.516304, 3.486737",\ + "0.748868, 0.987273, 1.263965, 1.749299, 2.720997",\ + "0.791164, 1.029569, 1.306198, 1.791324, 2.762603",\ + "0.851727, 1.090131, 1.366697, 1.851612, 2.822468",\ + "1.020657, 1.259062, 1.535559, 2.020247, 2.990646",\ + "1.603910, 1.842315, 2.118701, 2.603017, 3.572671",\ + "0.829717, 1.076183, 1.351928, 1.836920, 2.807952",\ + "0.872012, 1.118479, 1.394161, 1.878945, 2.849558",\ + "0.932575, 1.179041, 1.454660, 1.939233, 2.909423",\ + "1.101505, 1.347972, 1.623522, 2.107867, 3.077601",\ + "1.684759, 1.931225, 2.206665, 2.690638, 3.659626",\ + "0.887441, 1.141714, 1.416070, 1.900832, 2.871461",\ + "0.929737, 1.184009, 1.458303, 1.942857, 2.913067",\ + "0.990299, 1.244572, 1.518803, 2.003145, 2.972932",\ + "1.159229, 1.413502, 1.687665, 2.171780, 3.141110",\ + "1.742483, 1.996755, 2.270807, 2.754550, 3.723135",\ + "1.215567, 1.504997, 1.768108, 2.250242, 3.216917",\ + "1.257862, 1.547292, 1.810339, 2.292266, 3.258523",\ + "1.318425, 1.607855, 1.870836, 2.352553, 3.318388",\ + "1.487355, 1.776785, 2.039696, 2.521187, 3.486566",\ + "2.070609, 2.360038, 2.622834, 3.103956, 4.068591"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2722*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.584050, 0.834549, 1.112490, 1.609591, 2.603792",\ + "0.618482, 0.868982, 1.146923, 1.644024, 2.638226",\ + "0.689476, 0.939977, 1.217929, 1.715062, 2.709330",\ + "0.943640, 1.194143, 1.472115, 1.969317, 2.963722",\ + "1.868820, 2.119334, 2.397313, 2.894526, 3.888954",\ + "0.671463, 0.922054, 1.200147, 1.696306, 2.689726",\ + "0.705894, 0.956486, 1.234580, 1.730739, 2.724160",\ + "0.776888, 1.027482, 1.305585, 1.801777, 2.795263",\ + "1.031053, 1.281648, 1.559772, 2.056032, 3.049656",\ + "1.956232, 2.206839, 2.484970, 2.981241, 3.974888",\ + "0.752319, 1.010941, 1.288113, 1.783928, 2.776681",\ + "0.786751, 1.045373, 1.322546, 1.818361, 2.811115",\ + "0.857745, 1.116369, 1.393551, 1.889400, 2.882218",\ + "1.111909, 1.370534, 1.647738, 2.143654, 3.136611",\ + "2.037089, 2.295726, 2.572936, 3.068864, 4.061843",\ + "0.810059, 1.076439, 1.352257, 1.847842, 2.840190",\ + "0.844490, 1.110871, 1.386690, 1.882275, 2.874624",\ + "0.915485, 1.181867, 1.457695, 1.953313, 2.945727",\ + "1.169649, 1.436033, 1.711882, 2.207568, 3.200120",\ + "2.094831, 2.361224, 2.637080, 3.132777, 4.125352",\ + "1.143033, 1.439203, 1.704411, 2.197307, 3.185646",\ + "1.177464, 1.473635, 1.738844, 2.231740, 3.220080",\ + "1.248459, 1.544631, 1.809850, 2.302778, 3.291183",\ + "1.502625, 1.798797, 2.064037, 2.557034, 3.545576",\ + "2.427809, 2.723989, 2.989235, 3.482243, 4.470808"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\ + "0.083583, 0.083586, 0.083606, 0.083665, 0.083782",\ + "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470758, 2.470775, 2.471205, 2.472677, 2.475621",\ + "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\ + "0.083583, 0.083586, 0.083607, 0.083665, 0.083782",\ + "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470758, 2.470775, 2.471210, 2.472677, 2.475621",\ + "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\ + "0.083583, 0.083586, 0.083607, 0.083665, 0.083782",\ + "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470758, 2.470775, 2.471210, 2.472677, 2.475621",\ + "0.034240, 0.034241, 0.034251, 0.034278, 0.034331",\ + "0.083583, 0.083586, 0.083607, 0.083665, 0.083782",\ + "0.208067, 0.208069, 0.208085, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470760, 2.470775, 2.471210, 2.472677, 2.475621",\ + "0.034240, 0.034242, 0.034251, 0.034278, 0.034331",\ + "0.083584, 0.083587, 0.083607, 0.083665, 0.083782",\ + "0.208067, 0.208070, 0.208086, 0.208132, 0.208225",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470765, 2.470777, 2.471225, 2.472683, 2.475621"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.611087, 0.861585, 1.139535, 1.636665, 2.630925",\ + "0.653383, 0.903882, 1.181783, 1.678745, 2.672669",\ + "0.713946, 0.964444, 1.242285, 1.739034, 2.732533",\ + "0.882876, 1.133375, 1.411144, 1.907646, 2.900649",\ + "1.466128, 1.716626, 1.994359, 2.490734, 3.483483",\ + "0.698499, 0.949090, 1.227192, 1.723380, 2.716859",\ + "0.740795, 0.991387, 1.269439, 1.765460, 2.758603",\ + "0.801358, 1.051949, 1.329940, 1.825749, 2.818467",\ + "0.970289, 1.220880, 1.498799, 1.994361, 2.986582",\ + "1.553540, 1.804131, 2.082013, 2.577449, 3.569417",\ + "0.779356, 1.037977, 1.315158, 1.811002, 2.803814",\ + "0.821652, 1.080273, 1.357405, 1.853082, 2.845558",\ + "0.882215, 1.140836, 1.417906, 1.913371, 2.905422",\ + "1.051145, 1.309767, 1.586765, 2.081983, 3.073537",\ + "1.634397, 1.893018, 2.169979, 2.665071, 3.656372",\ + "0.837095, 1.103475, 1.379302, 1.874916, 2.867323",\ + "0.879392, 1.145772, 1.421550, 1.916996, 2.909067",\ + "0.939954, 1.206334, 1.482050, 1.977285, 2.968931",\ + "1.108885, 1.375265, 1.650909, 2.145896, 3.137046",\ + "1.692136, 1.958516, 2.234123, 2.728984, 3.719881",\ + "1.170069, 1.466239, 1.731456, 2.224381, 3.212779",\ + "1.212365, 1.508535, 1.773702, 2.266461, 3.254523",\ + "1.272928, 1.569098, 1.834201, 2.326749, 3.314387",\ + "1.441859, 1.738029, 2.003057, 2.495359, 3.482502",\ + "2.025110, 2.321280, 2.586270, 3.078447, 4.065337"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498064, 1.498063, 1.498061, 1.498051, 1.498033",\ + "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498064, 1.498063, 1.498060, 1.498051, 1.498033",\ + "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498064, 1.498063, 1.498060, 1.498051, 1.498033",\ + "0.045859, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498064, 1.498063, 1.498060, 1.498051, 1.498033",\ + "0.045858, 0.045858, 0.045856, 0.045847, 0.045830",\ + "0.079972, 0.079972, 0.079972, 0.079972, 0.079972",\ + "0.155685, 0.155685, 0.155683, 0.155678, 0.155666",\ + "0.431271, 0.431271, 0.431271, 0.431270, 0.431268",\ + "1.498063, 1.498063, 1.498060, 1.498051, 1.498033"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2499*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.576605, 0.831535, 1.088524, 1.527728, 2.406135",\ + "0.611028, 0.865958, 1.122948, 1.562156, 2.440572",\ + "0.682011, 0.936939, 1.193932, 1.633147, 2.511575",\ + "0.936163, 1.191091, 1.448086, 1.887307, 2.765749",\ + "1.861240, 2.116160, 2.373173, 2.812451, 3.691008",\ + "0.664013, 0.919020, 1.175996, 1.614442, 2.492069",\ + "0.698437, 0.953443, 1.210420, 1.648871, 2.526506",\ + "0.769419, 1.024424, 1.281404, 1.719861, 2.597509",\ + "1.023571, 1.278576, 1.535558, 1.974021, 2.851683",\ + "1.948648, 2.203645, 2.460645, 2.899166, 3.776942",\ + "0.751657, 1.007845, 1.263958, 1.702063, 2.579024",\ + "0.786080, 1.042268, 1.298382, 1.736492, 2.613461",\ + "0.857063, 1.113249, 1.369366, 1.807482, 2.684464",\ + "1.111215, 1.367401, 1.623520, 2.061643, 2.938638",\ + "2.036291, 2.292470, 2.548607, 2.986787, 3.863897",\ + "0.814841, 1.073252, 1.328092, 1.765976, 2.642533",\ + "0.849265, 1.107675, 1.362517, 1.800405, 2.676970",\ + "0.920247, 1.178657, 1.433500, 1.871395, 2.747973",\ + "1.174399, 1.432808, 1.687654, 2.125556, 3.002147",\ + "2.099474, 2.357878, 2.612742, 3.050700, 3.927406",\ + "1.148308, 1.435007, 1.679656, 2.115198, 2.987988",\ + "1.182731, 1.469430, 1.714081, 2.149627, 3.022426",\ + "1.253713, 1.540412, 1.785064, 2.220617, 3.093429",\ + "1.507865, 1.794564, 2.039218, 2.474777, 3.347603",\ + "2.432936, 2.719633, 2.964306, 3.399922, 4.272861"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208076, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470714, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470715, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693297, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470721, 2.471301, 2.472467"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.603644, 0.858574, 1.115563, 1.554765, 2.433169",\ + "0.645940, 0.900870, 1.157859, 1.597061, 2.475466",\ + "0.706502, 0.961433, 1.218421, 1.657624, 2.536028",\ + "0.875433, 1.130363, 1.387352, 1.826554, 2.704960",\ + "1.458686, 1.713616, 1.970605, 2.409806, 3.288209",\ + "0.691052, 0.946059, 1.203035, 1.641479, 2.519103",\ + "0.733348, 0.988355, 1.245331, 1.683775, 2.561400",\ + "0.793911, 1.048918, 1.305893, 1.744338, 2.621962",\ + "0.962841, 1.217848, 1.474824, 1.913269, 2.790894",\ + "1.546094, 1.801101, 2.058077, 2.496521, 3.374143",\ + "0.778696, 1.034884, 1.290997, 1.729101, 2.606058",\ + "0.820992, 1.077180, 1.333292, 1.771397, 2.648355",\ + "0.881555, 1.137743, 1.393855, 1.831960, 2.708917",\ + "1.050485, 1.306673, 1.562785, 2.000890, 2.877849",\ + "1.633738, 1.889926, 2.146038, 2.584142, 3.461098",\ + "0.841881, 1.100292, 1.355131, 1.793014, 2.669567",\ + "0.884176, 1.142587, 1.397427, 1.835310, 2.711864",\ + "0.944739, 1.203150, 1.457990, 1.895873, 2.772426",\ + "1.113669, 1.372080, 1.626920, 2.064803, 2.941358",\ + "1.696922, 1.955333, 2.210173, 2.648055, 3.524607",\ + "1.175348, 1.462047, 1.706695, 2.142236, 3.015023",\ + "1.217643, 1.504343, 1.748991, 2.184532, 3.057320",\ + "1.278206, 1.564905, 1.809554, 2.245094, 3.117882",\ + "1.447136, 1.733835, 1.978484, 2.414025, 3.286813",\ + "2.030389, 2.317089, 2.561737, 2.997277, 3.870063"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2578*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.703817, 0.965190, 1.250386, 1.755046, 2.764366",\ + "0.738210, 0.999583, 1.284779, 1.789440, 2.798762",\ + "0.809448, 1.070821, 1.356016, 1.860676, 2.869994",\ + "1.063614, 1.324987, 1.610183, 2.114842, 3.124160",\ + "1.988218, 2.249590, 2.534788, 3.039459, 4.048801",\ + "0.791226, 1.052733, 1.338065, 1.841760, 2.850300",\ + "0.825619, 1.087126, 1.372458, 1.876155, 2.884696",\ + "0.896857, 1.158363, 1.443695, 1.947390, 2.955927",\ + "1.151023, 1.412530, 1.697862, 2.201556, 3.210094",\ + "2.075627, 2.337133, 2.622467, 3.126173, 4.134735",\ + "0.874336, 1.141692, 1.426031, 1.929382, 2.937255",\ + "0.908729, 1.176085, 1.460424, 1.963776, 2.971651",\ + "0.979967, 1.247323, 1.531661, 2.035012, 3.042882",\ + "1.234133, 1.501489, 1.785827, 2.289178, 3.297049",\ + "2.158737, 2.426092, 2.710433, 3.213795, 4.221690",\ + "0.937775, 1.207295, 1.490176, 1.993295, 3.000764",\ + "0.972168, 1.241688, 1.524569, 2.027689, 3.035160",\ + "1.043406, 1.312926, 1.595807, 2.098925, 3.106391",\ + "1.297572, 1.567092, 1.849973, 2.353091, 3.360558",\ + "2.222176, 2.491695, 2.774579, 3.277709, 4.285199",\ + "1.272869, 1.571325, 1.842405, 2.342789, 3.346220",\ + "1.307262, 1.605718, 1.876798, 2.377183, 3.380616",\ + "1.378499, 1.676956, 1.948035, 2.448418, 3.451848",\ + "1.632666, 1.931122, 2.202202, 2.702585, 3.706014",\ + "2.557269, 2.855725, 3.126807, 3.627202, 4.630655"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\ + "2.465101, 2.465101, 2.465179, 2.465445, 2.465979",\ + "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\ + "2.465101, 2.465101, 2.465179, 2.465445, 2.465979",\ + "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\ + "2.465101, 2.465101, 2.465179, 2.465445, 2.465979",\ + "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692780, 0.692819, 0.692898",\ + "2.465101, 2.465101, 2.465180, 2.465445, 2.465979",\ + "0.034112, 0.034112, 0.034113, 0.034115, 0.034118",\ + "0.083750, 0.083751, 0.083754, 0.083762, 0.083778",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692765, 0.692780, 0.692820, 0.692898",\ + "2.465101, 2.465101, 2.465182, 2.465446, 2.465979"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.735613, 0.996985, 1.282184, 1.786857, 2.796203",\ + "0.777364, 1.038737, 1.323936, 1.828608, 2.837953",\ + "0.837295, 1.098667, 1.383866, 1.888539, 2.897883",\ + "1.005411, 1.266784, 1.551982, 2.056655, 3.065999",\ + "1.587437, 1.848807, 2.134015, 2.638729, 3.648157",\ + "0.823022, 1.084528, 1.369863, 1.873571, 2.882137",\ + "0.864774, 1.126280, 1.411614, 1.915322, 2.923887",\ + "0.924704, 1.186210, 1.471545, 1.975253, 2.983817",\ + "1.092821, 1.354327, 1.639661, 2.143369, 3.151933",\ + "1.674846, 1.936350, 2.221694, 2.725443, 3.734090",\ + "0.906132, 1.173487, 1.457829, 1.961193, 2.969092",\ + "0.947883, 1.215239, 1.499580, 2.002944, 3.010842",\ + "1.007814, 1.275169, 1.559510, 2.062875, 3.070772",\ + "1.175930, 1.443286, 1.727627, 2.230991, 3.238888",\ + "1.757956, 2.025309, 2.309659, 2.813065, 3.821045",\ + "0.969571, 1.239090, 1.521974, 2.025106, 3.032601",\ + "1.011322, 1.280842, 1.563726, 2.066857, 3.074351",\ + "1.071253, 1.340772, 1.623656, 2.126788, 3.134281",\ + "1.239369, 1.508889, 1.791773, 2.294904, 3.302397",\ + "1.821394, 2.090912, 2.373805, 2.876978, 3.884554",\ + "1.304665, 1.603120, 1.874203, 2.374600, 3.378057",\ + "1.346416, 1.644871, 1.915954, 2.416351, 3.419807",\ + "1.406347, 1.704802, 1.975885, 2.476281, 3.479737",\ + "1.574463, 1.872918, 2.144001, 2.644397, 3.647853",\ + "2.156488, 2.454941, 2.726034, 3.226472, 4.230011"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494123, 1.494129, 1.494143"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2448*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.689792, 0.930744, 1.201013, 1.654265, 2.560769",\ + "0.724185, 0.965137, 1.235406, 1.688659, 2.595164",\ + "0.795422, 1.036375, 1.306643, 1.759894, 2.666397",\ + "1.049588, 1.290541, 1.560810, 2.014061, 2.920563",\ + "1.974192, 2.215145, 2.485415, 2.938676, 3.845196",\ + "0.777198, 1.018294, 1.288529, 1.740979, 2.646702",\ + "0.811591, 1.052687, 1.322922, 1.775373, 2.681098",\ + "0.882828, 1.123924, 1.394159, 1.846608, 2.752330",\ + "1.136994, 1.378091, 1.648325, 2.100775, 3.006497",\ + "2.061598, 2.302694, 2.572931, 3.025389, 3.931130",\ + "0.858027, 1.107253, 1.376491, 1.828600, 2.733657",\ + "0.892420, 1.141646, 1.410884, 1.862994, 2.768053",\ + "0.963658, 1.212883, 1.482121, 1.934230, 2.839285",\ + "1.217824, 1.467050, 1.736287, 2.188396, 3.093452",\ + "2.142428, 2.391653, 2.660893, 3.113011, 4.018085",\ + "0.915670, 1.172855, 1.440628, 1.892513, 2.797166",\ + "0.950063, 1.207248, 1.475021, 1.926907, 2.831562",\ + "1.021300, 1.278486, 1.546258, 1.998143, 2.902794",\ + "1.275467, 1.532652, 1.800424, 2.252309, 3.156961",\ + "2.200070, 2.457256, 2.725030, 3.176924, 4.081594",\ + "1.241554, 1.536923, 1.792333, 2.241791, 3.142622",\ + "1.275947, 1.571316, 1.826726, 2.276185, 3.177018",\ + "1.347184, 1.642554, 1.897963, 2.347420, 3.248250",\ + "1.601351, 1.896721, 2.152130, 2.601587, 3.502417",\ + "2.525954, 2.821324, 3.076735, 3.526202, 4.427050"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692773, 0.692804, 0.692866",\ + "2.465102, 2.465102, 2.465164, 2.465378, 2.465806",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692774, 0.692804, 0.692866",\ + "2.465102, 2.465102, 2.465165, 2.465378, 2.465806",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692774, 0.692804, 0.692866",\ + "2.465102, 2.465102, 2.465165, 2.465378, 2.465806",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692774, 0.692804, 0.692866",\ + "2.465102, 2.465102, 2.465165, 2.465378, 2.465806",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083751, 0.083753, 0.083759, 0.083772",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692774, 0.692805, 0.692866",\ + "2.465102, 2.465102, 2.465167, 2.465379, 2.465806"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.721587, 0.962540, 1.232811, 1.686073, 2.592597",\ + "0.763339, 1.004291, 1.274563, 1.727824, 2.634348",\ + "0.823269, 1.064222, 1.334493, 1.787755, 2.694278",\ + "0.991386, 1.232338, 1.502609, 1.955871, 2.862394",\ + "1.573411, 1.814363, 2.084642, 2.537936, 3.444525",\ + "0.808993, 1.050089, 1.320327, 1.772787, 2.678531",\ + "0.850745, 1.091841, 1.362078, 1.814538, 2.720282",\ + "0.910675, 1.151771, 1.422008, 1.874469, 2.780212",\ + "1.078792, 1.319888, 1.590125, 2.042585, 2.948328",\ + "1.660817, 1.901912, 2.172157, 2.624650, 3.530459",\ + "0.889823, 1.139049, 1.408289, 1.860408, 2.765486",\ + "0.931575, 1.180800, 1.450040, 1.902159, 2.807237",\ + "0.991505, 1.240730, 1.509970, 1.962090, 2.867167",\ + "1.159622, 1.408847, 1.678087, 2.130206, 3.035283",\ + "1.741647, 1.990871, 2.260119, 2.712271, 3.617414",\ + "0.947466, 1.204651, 1.472426, 1.924321, 2.828995",\ + "0.989217, 1.246402, 1.514177, 1.966072, 2.870746",\ + "1.049147, 1.306333, 1.574107, 2.026003, 2.930676",\ + "1.217264, 1.474449, 1.742224, 2.194119, 3.098792",\ + "1.799289, 2.056473, 2.324256, 2.776184, 3.680923",\ + "1.273350, 1.568719, 1.824131, 2.273599, 3.174451",\ + "1.315101, 1.610470, 1.865882, 2.315350, 3.216202",\ + "1.375032, 1.670401, 1.925813, 2.375281, 3.276132",\ + "1.543148, 1.838517, 2.093929, 2.543397, 3.444248",\ + "2.125174, 2.420541, 2.675962, 3.125462, 4.026379"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494119, 1.494121, 1.494127, 1.494137",\ + "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494120, 1.494121, 1.494127, 1.494137",\ + "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494120, 1.494121, 1.494127, 1.494137",\ + "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494120, 1.494121, 1.494127, 1.494137",\ + "0.045877, 0.045876, 0.045872, 0.045863, 0.045844",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155803, 0.155801, 0.155793, 0.155779",\ + "0.431307, 0.431307, 0.431306, 0.431304, 0.431301",\ + "1.494119, 1.494120, 1.494121, 1.494127, 1.494137"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2742*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.554088, 0.796303, 1.062117, 1.540354, 2.496829",\ + "0.588520, 0.830735, 1.096550, 1.574794, 2.531283",\ + "0.659515, 0.901730, 1.167548, 1.645811, 2.602338",\ + "0.913680, 1.155895, 1.421738, 1.900092, 2.856801",\ + "1.838864, 2.081077, 2.346923, 2.825343, 3.782184",\ + "0.641494, 0.883776, 1.149711, 1.627068, 2.582762",\ + "0.675925, 0.918208, 1.184143, 1.661508, 2.617217",\ + "0.746920, 0.989202, 1.255142, 1.732525, 2.688272",\ + "1.001085, 1.243367, 1.509332, 1.986806, 2.942735",\ + "1.926270, 2.168550, 2.434517, 2.912057, 3.868118",\ + "0.722307, 0.972564, 1.237674, 1.714689, 2.669717",\ + "0.756739, 1.006995, 1.272107, 1.749129, 2.704172",\ + "0.827734, 1.077990, 1.343105, 1.820146, 2.775227",\ + "1.081899, 1.332155, 1.597295, 2.074427, 3.029690",\ + "2.007083, 2.257337, 2.522481, 2.999678, 3.955073",\ + "0.781255, 1.037917, 1.301816, 1.778602, 2.733226",\ + "0.815687, 1.072348, 1.336248, 1.813042, 2.767681",\ + "0.886682, 1.143343, 1.407246, 1.884059, 2.838736",\ + "1.140847, 1.397507, 1.661436, 2.138340, 3.093199",\ + "2.066033, 2.322690, 2.586622, 3.063591, 4.018582",\ + "1.116786, 1.399065, 1.653774, 2.127983, 3.078682",\ + "1.151218, 1.433496, 1.688207, 2.162423, 3.113137",\ + "1.222213, 1.504490, 1.759205, 2.233440, 3.184192",\ + "1.476379, 1.758654, 2.013396, 2.487721, 3.438655",\ + "2.401570, 2.683832, 2.938582, 3.412973, 4.364038"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.034240, 0.034243, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083624, 0.083701, 0.083855",\ + "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471502, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471509, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471509, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470764, 2.470782, 2.471510, 2.473964, 2.478889",\ + "0.034240, 0.034245, 0.034262, 0.034304, 0.034388",\ + "0.083583, 0.083594, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208075, 0.208100, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470774, 2.470782, 2.471535, 2.473974, 2.478889"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.581124, 0.823340, 1.089156, 1.567400, 2.523887",\ + "0.623421, 0.865636, 1.131410, 1.609509, 2.565706",\ + "0.683983, 0.926199, 1.191909, 1.669792, 2.625559",\ + "0.852914, 1.095129, 1.360763, 1.838384, 2.793625",\ + "1.436165, 1.678380, 1.944001, 2.421576, 3.376727",\ + "0.668530, 0.910813, 1.176750, 1.654113, 2.609821",\ + "0.710826, 0.953109, 1.219003, 1.696222, 2.651640",\ + "0.771389, 1.013672, 1.279502, 1.756506, 2.711493",\ + "0.940320, 1.182602, 1.448355, 1.925098, 2.879559",\ + "1.523571, 1.765853, 2.031593, 2.508290, 3.462660",\ + "0.749343, 0.999600, 1.264713, 1.741735, 2.696776",\ + "0.791640, 1.041896, 1.306967, 1.783844, 2.738595",\ + "0.852202, 1.102459, 1.367465, 1.844127, 2.798448",\ + "1.021133, 1.271390, 1.536319, 2.012719, 2.966514",\ + "1.604384, 1.854641, 2.119556, 2.595911, 3.549615",\ + "0.808291, 1.064953, 1.328854, 1.805647, 2.760285",\ + "0.850588, 1.107249, 1.371108, 1.847756, 2.802104",\ + "0.911150, 1.167812, 1.431607, 1.908040, 2.861957",\ + "1.080081, 1.336743, 1.600460, 2.076632, 3.030023",\ + "1.663332, 1.919994, 2.183697, 2.659824, 3.613124",\ + "1.143822, 1.426101, 1.680813, 2.155028, 3.105741",\ + "1.186118, 1.468397, 1.723065, 2.197137, 3.147560",\ + "1.246681, 1.528960, 1.783561, 2.257420, 3.207412",\ + "1.415612, 1.697891, 1.952412, 2.426010, 3.375479",\ + "1.998863, 2.281142, 2.535649, 3.009202, 3.958580"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045871, 0.045908, 0.045983",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_2612*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.306542, 0.508788, 0.717853, 1.042526, 1.663915",\ + "0.340106, 0.542413, 0.751464, 1.076125, 1.697497",\ + "0.411112, 0.613496, 0.822458, 1.147079, 1.768433",\ + "0.665955, 0.868524, 1.077364, 1.401917, 2.023216",\ + "1.591125, 1.794899, 2.003187, 2.327733, 2.949505",\ + "0.395283, 0.596107, 0.805134, 1.129831, 1.751269",\ + "0.428854, 0.629732, 0.838745, 1.163429, 1.784850",\ + "0.499862, 0.700815, 0.909738, 1.234384, 1.855787",\ + "0.754705, 0.955843, 1.164644, 1.489222, 2.110569",\ + "1.679862, 1.882218, 2.090468, 2.415038, 3.036858",\ + "0.484964, 0.676444, 0.885161, 1.209860, 1.831300",\ + "0.518558, 0.710069, 0.918772, 1.243458, 1.864882",\ + "0.589569, 0.781152, 0.989765, 1.314412, 1.935818",\ + "0.844412, 1.036181, 1.244671, 1.569251, 2.190600",\ + "1.769534, 1.962556, 2.170495, 2.495067, 3.116889",\ + "0.543833, 0.734313, 0.942926, 1.267362, 1.888460",\ + "0.577463, 0.767939, 0.976537, 1.300961, 1.922042",\ + "0.648577, 0.839021, 1.047530, 1.371915, 1.992978",\ + "0.903624, 1.094050, 1.302436, 1.626753, 2.247760",\ + "1.830206, 2.020424, 2.228258, 2.552570, 3.174051",\ + "0.846614, 1.039923, 1.246594, 1.570597, 2.190856",\ + "0.880244, 1.073548, 1.280205, 1.604196, 2.224438",\ + "0.951354, 1.144630, 1.351198, 1.675150, 2.295374",\ + "1.206399, 1.399658, 1.606104, 1.929988, 2.550156",\ + "2.132956, 2.326026, 2.531926, 2.855805, 3.476448"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.023786, 0.023786, 0.023786, 0.023810, 0.023868",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685151, 0.685311, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446667, 2.447885, 2.450424",\ + "0.023786, 0.023786, 0.023786, 0.023810, 0.023868",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685156, 0.685311, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446667, 2.447885, 2.450424",\ + "0.023786, 0.023786, 0.023786, 0.023810, 0.023868",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685169, 0.685311, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446667, 2.447885, 2.450424",\ + "0.023786, 0.023786, 0.023786, 0.023810, 0.023869",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069369",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685155, 0.685312, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446668, 2.447888, 2.450430",\ + "0.023786, 0.023786, 0.023786, 0.023810, 0.023869",\ + "0.069294, 0.069294, 0.069294, 0.069316, 0.069370",\ + "0.199985, 0.199985, 0.199985, 0.199985, 0.199985",\ + "0.685173, 0.685316, 0.685321, 0.685321, 0.685321",\ + "2.446158, 2.446158, 2.446668, 2.447891, 2.450438"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.300762, 0.504583, 0.713270, 1.038101, 1.660218",\ + "0.333089, 0.537036, 0.745749, 1.070675, 1.693005",\ + "0.383451, 0.587349, 0.796071, 1.121057, 1.743526",\ + "0.544532, 0.748090, 0.956809, 1.281806, 1.904306",\ + "1.125564, 1.330456, 1.540080, 1.865115, 2.486899",\ + "0.389512, 0.591901, 0.800551, 1.125406, 1.747571",\ + "0.421839, 0.624354, 0.833030, 1.157980, 1.780358",\ + "0.472201, 0.674668, 0.883352, 1.208362, 1.830879",\ + "0.633282, 0.835409, 1.044090, 1.369112, 1.991659",\ + "1.214288, 1.417775, 1.627361, 1.952420, 2.574253",\ + "0.479218, 0.672239, 0.880578, 1.205435, 1.827603",\ + "0.511548, 0.704692, 0.913057, 1.238009, 1.860390",\ + "0.561908, 0.755005, 0.963379, 1.288391, 1.910911",\ + "0.722989, 0.915746, 1.124117, 1.449140, 2.071691",\ + "1.303923, 1.498112, 1.707387, 2.032449, 2.654284",\ + "0.539760, 0.730108, 0.938342, 1.262939, 1.884765",\ + "0.572206, 0.762561, 0.970821, 1.295513, 1.917552",\ + "0.622521, 0.812874, 1.021143, 1.345895, 1.968074",\ + "0.783248, 0.973615, 1.181881, 1.506644, 2.128853",\ + "1.365347, 1.555982, 1.765154, 2.089952, 2.711445",\ + "0.842526, 1.035714, 1.242010, 1.566174, 2.187163",\ + "0.874973, 1.068167, 1.274489, 1.598749, 2.219951",\ + "0.925287, 1.118480, 1.324811, 1.649131, 2.270473",\ + "1.086016, 1.279222, 1.485549, 1.809880, 2.431253",\ + "1.668147, 1.861596, 2.068822, 2.393188, 3.013843"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.030099, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059380, 0.059246, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484352, 1.482541, 1.482428, 1.482428, 1.482428",\ + "0.030099, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059376, 0.059246, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484298, 1.482541, 1.482428, 1.482428, 1.482428",\ + "0.030098, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059366, 0.059246, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484152, 1.482541, 1.482428, 1.482428, 1.482428",\ + "0.030099, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059378, 0.059246, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484315, 1.482534, 1.482428, 1.482428, 1.482428",\ + "0.030098, 0.030091, 0.030091, 0.030077, 0.030045",\ + "0.059362, 0.059242, 0.059238, 0.059238, 0.059238",\ + "0.131641, 0.131636, 0.131630, 0.131627, 0.131627",\ + "0.418133, 0.418133, 0.418133, 0.418133, 0.418133",\ + "1.484105, 1.482485, 1.482428, 1.482428, 1.482428"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2559*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.534853, 0.754941, 0.932292, 1.220792, 1.781149",\ + "0.576549, 0.796638, 0.973989, 1.262489, 1.822845",\ + "0.652730, 0.872819, 1.050170, 1.338670, 1.899026",\ + "0.908126, 1.128215, 1.305566, 1.594066, 2.154422",\ + "1.832504, 2.052592, 2.229943, 2.518443, 3.078799",\ + "0.623250, 0.842260, 1.019573, 1.308098, 1.868502",\ + "0.664946, 0.883956, 1.061270, 1.349794, 1.910198",\ + "0.741127, 0.960137, 1.137451, 1.425975, 1.986380",\ + "0.996523, 1.215533, 1.392847, 1.681371, 2.241775",\ + "1.920900, 2.139910, 2.317224, 2.605748, 3.166152",\ + "0.712601, 0.922592, 1.099600, 1.388126, 1.948534",\ + "0.754297, 0.964289, 1.141297, 1.429822, 1.990230",\ + "0.830478, 1.040470, 1.217478, 1.506004, 2.066411",\ + "1.085874, 1.295865, 1.472873, 1.761399, 2.321807",\ + "2.010251, 2.220243, 2.397251, 2.685777, 3.246184",\ + "0.776250, 0.980408, 1.157292, 1.445555, 2.005549",\ + "0.817947, 1.022105, 1.198989, 1.487252, 2.047245",\ + "0.894128, 1.098286, 1.275170, 1.563433, 2.123426",\ + "1.149523, 1.353682, 1.530566, 1.818829, 2.378822",\ + "2.073901, 2.278059, 2.454943, 2.743206, 3.303199",\ + "1.107332, 1.285624, 1.460948, 1.748727, 2.307770",\ + "1.149029, 1.327321, 1.502644, 1.790423, 2.349466",\ + "1.225210, 1.403502, 1.578825, 1.866605, 2.425647",\ + "1.480606, 1.658898, 1.834221, 2.122000, 2.681043",\ + "2.404983, 2.583275, 2.758598, 3.046378, 3.605420"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685787",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.555098, 0.775186, 0.952537, 1.241037, 1.801394",\ + "0.587348, 0.807436, 0.984787, 1.273287, 1.833643",\ + "0.637660, 0.857748, 1.035099, 1.323599, 1.883955",\ + "0.798324, 1.018412, 1.195763, 1.484263, 2.044619",\ + "1.379457, 1.599546, 1.776897, 2.065397, 2.625753",\ + "0.643495, 0.862505, 1.039818, 1.328343, 1.888747",\ + "0.675744, 0.894754, 1.072068, 1.360592, 1.920997",\ + "0.726057, 0.945067, 1.122380, 1.410905, 1.971309",\ + "0.886720, 1.105730, 1.283044, 1.571568, 2.131973",\ + "1.467854, 1.686864, 1.864178, 2.152702, 2.713106",\ + "0.732846, 0.942837, 1.119845, 1.408371, 1.968779",\ + "0.765095, 0.975087, 1.152095, 1.440621, 2.001028",\ + "0.815408, 1.025399, 1.202407, 1.490933, 2.051341",\ + "0.976071, 1.186063, 1.363071, 1.651597, 2.212004",\ + "1.557205, 1.767197, 1.944205, 2.232730, 2.793138",\ + "0.796495, 1.000653, 1.177537, 1.465801, 2.025794",\ + "0.828745, 1.032903, 1.209787, 1.498050, 2.058043",\ + "0.879057, 1.083215, 1.260099, 1.548362, 2.108356",\ + "1.039721, 1.243879, 1.420763, 1.709026, 2.269019",\ + "1.620855, 1.825013, 2.001897, 2.290160, 2.850153",\ + "1.127577, 1.305869, 1.481193, 1.768972, 2.328015",\ + "1.159827, 1.338119, 1.513443, 1.801222, 2.360265",\ + "1.210139, 1.388431, 1.563755, 1.851534, 2.410577",\ + "1.370803, 1.549095, 1.724418, 2.012197, 2.571240",\ + "1.951937, 2.130229, 2.305552, 2.593331, 3.152374"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482977, 1.482976, 1.482976, 1.482976"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2577*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.256885, 0.492153, 0.681988, 0.987164, 1.577680",\ + "0.290472, 0.525767, 0.715632, 1.020810, 1.611303",\ + "0.361355, 0.596664, 0.786663, 1.091855, 1.682256",\ + "0.616370, 0.851426, 1.041598, 1.346846, 1.937220",\ + "1.541773, 1.775412, 1.968861, 2.274571, 2.863136",\ + "0.345363, 0.579471, 0.769269, 1.074469, 1.665033",\ + "0.378951, 0.613085, 0.802913, 1.108115, 1.698656",\ + "0.449834, 0.683983, 0.873944, 1.179160, 1.769609",\ + "0.704852, 0.938744, 1.128879, 1.434151, 2.024573",\ + "1.630270, 1.862731, 2.056142, 2.361876, 2.950490",\ + "0.434929, 0.659804, 0.849296, 1.154498, 1.745065",\ + "0.468520, 0.693418, 0.882940, 1.188143, 1.778688",\ + "0.539403, 0.764315, 0.953971, 1.259189, 1.849641",\ + "0.794431, 1.019077, 1.208906, 1.514180, 2.104605",\ + "1.719892, 1.943063, 2.136169, 2.441904, 3.030521",\ + "0.498770, 0.717639, 0.907017, 1.211964, 1.802153",\ + "0.532364, 0.751252, 0.940661, 1.245610, 1.835775",\ + "0.603247, 0.822149, 1.011693, 1.316654, 1.906729",\ + "0.858284, 1.076910, 1.266629, 1.571645, 2.161693",\ + "1.783785, 2.000890, 2.193899, 2.499368, 3.087604",\ + "0.836421, 1.022987, 1.210677, 1.515166, 2.104462",\ + "0.870034, 1.056600, 1.244321, 1.548812, 2.138084",\ + "0.940914, 1.127492, 1.315353, 1.619857, 2.209037",\ + "1.196012, 1.382245, 1.570289, 1.874848, 2.464001",\ + "2.121767, 2.306184, 2.497561, 2.802569, 3.389907"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454037, 2.454505, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454037, 2.454505, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454037, 2.454505, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454039, 2.454505, 2.455154",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454039, 2.454506, 2.455156"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.251684, 0.487150, 0.676755, 0.981685, 1.571796",\ + "0.284092, 0.519474, 0.709133, 1.014097, 1.604246",\ + "0.334486, 0.569802, 0.759438, 1.064423, 1.654643",\ + "0.495295, 0.730692, 0.920083, 1.225063, 1.815495",\ + "1.076466, 1.311284, 1.500832, 1.805703, 2.395659",\ + "0.340147, 0.574468, 0.764036, 1.068990, 1.659150",\ + "0.372555, 0.606792, 0.796414, 1.101402, 1.691600",\ + "0.422950, 0.657120, 0.846719, 1.151728, 1.741997",\ + "0.583764, 0.818010, 1.007364, 1.312368, 1.902848",\ + "1.164940, 1.398602, 1.588113, 1.893008, 2.483012",\ + "0.429671, 0.654801, 0.844063, 1.149019, 1.739182",\ + "0.462080, 0.687125, 0.876441, 1.181431, 1.771631",\ + "0.512476, 0.737453, 0.926746, 1.231757, 1.822028",\ + "0.673307, 0.898343, 1.087391, 1.392396, 1.982880",\ + "1.254498, 1.478935, 1.668140, 1.973037, 2.563044",\ + "0.493473, 0.712635, 0.901784, 1.206484, 1.796268",\ + "0.525883, 0.744960, 0.934162, 1.238896, 1.828718",\ + "0.576281, 0.795287, 0.984467, 1.289223, 1.879116",\ + "0.737126, 0.956178, 1.145111, 1.449862, 2.039968",\ + "1.318331, 1.536764, 1.725861, 2.030502, 2.620130",\ + "0.830874, 1.017982, 1.205444, 1.509686, 2.098576",\ + "0.863289, 1.050307, 1.237822, 1.542099, 2.131026",\ + "0.913697, 1.100635, 1.288127, 1.592425, 2.181424",\ + "1.074636, 1.261533, 1.448771, 1.753065, 2.342276",\ + "1.655932, 1.842073, 2.029521, 2.333704, 2.922437"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030171, 0.030364",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2320*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.514526, 0.752428, 0.939979, 1.239804, 1.819405",\ + "0.556223, 0.794124, 0.981676, 1.281500, 1.861101",\ + "0.632404, 0.870306, 1.057857, 1.357682, 1.937282",\ + "0.887800, 1.125701, 1.313253, 1.613077, 2.192678",\ + "1.812177, 2.050079, 2.237630, 2.537455, 3.117055",\ + "0.602829, 0.839746, 1.027260, 1.327109, 1.906758",\ + "0.644526, 0.881442, 1.068957, 1.368805, 1.948454",\ + "0.720707, 0.957623, 1.145138, 1.444987, 2.024636",\ + "0.976103, 1.213019, 1.400534, 1.700382, 2.280031",\ + "1.900480, 2.137396, 2.324911, 2.624760, 3.204408",\ + "0.692380, 0.920074, 1.107287, 1.407137, 1.986790",\ + "0.734076, 0.961771, 1.148984, 1.448834, 2.028486",\ + "0.810257, 1.037952, 1.225165, 1.525015, 2.104667",\ + "1.065653, 1.293347, 1.480561, 1.780411, 2.360063",\ + "1.990030, 2.217725, 2.404938, 2.704788, 3.284440",\ + "0.756421, 0.977914, 1.165004, 1.464591, 2.043853",\ + "0.798118, 1.019611, 1.206700, 1.506287, 2.085550",\ + "0.874299, 1.095792, 1.282882, 1.582469, 2.161731",\ + "1.129694, 1.351188, 1.538277, 1.837864, 2.417127",\ + "2.054072, 2.275565, 2.462655, 2.762241, 3.341504",\ + "1.095322, 1.283284, 1.468662, 1.767782, 2.346133",\ + "1.137018, 1.324980, 1.510358, 1.809478, 2.387829",\ + "1.213199, 1.401161, 1.586540, 1.885659, 2.464011",\ + "1.468595, 1.656557, 1.841935, 2.141055, 2.719406",\ + "2.392972, 2.580935, 2.766313, 3.065432, 3.643783"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.534772, 0.772673, 0.960224, 1.260049, 1.839650",\ + "0.567021, 0.804923, 0.992474, 1.292299, 1.871899",\ + "0.617333, 0.855235, 1.042786, 1.342611, 1.922212",\ + "0.777997, 1.015898, 1.203450, 1.503274, 2.082875",\ + "1.359131, 1.597032, 1.784584, 2.084409, 2.664009",\ + "0.623075, 0.859991, 1.047505, 1.347354, 1.927003",\ + "0.655324, 0.892240, 1.079755, 1.379604, 1.959253",\ + "0.705636, 0.942553, 1.130067, 1.429916, 2.009565",\ + "0.866300, 1.103216, 1.290731, 1.590580, 2.170229",\ + "1.447434, 1.684350, 1.871865, 2.171714, 2.751363",\ + "0.712625, 0.940319, 1.127532, 1.427382, 2.007035",\ + "0.744874, 0.972569, 1.159782, 1.459632, 2.039284",\ + "0.795187, 1.022881, 1.210094, 1.509944, 2.089597",\ + "0.955850, 1.183545, 1.370758, 1.670608, 2.250260",\ + "1.536984, 1.764679, 1.951892, 2.251742, 2.831394",\ + "0.776666, 0.998159, 1.185249, 1.484836, 2.064098",\ + "0.808916, 1.030409, 1.217499, 1.517086, 2.096348",\ + "0.859228, 1.080721, 1.267811, 1.567398, 2.146660",\ + "1.019892, 1.241385, 1.428475, 1.728061, 2.307324",\ + "1.601026, 1.822519, 2.009609, 2.309195, 2.888458",\ + "1.115567, 1.303529, 1.488907, 1.788027, 2.366378",\ + "1.147816, 1.335778, 1.521157, 1.820276, 2.398628",\ + "1.198129, 1.386091, 1.571469, 1.870589, 2.448940",\ + "1.358792, 1.546754, 1.732133, 2.031252, 2.609604",\ + "1.939926, 2.127888, 2.313267, 2.612386, 3.190738"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482977, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2351*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.430447, 0.665884, 0.855738, 1.160934, 1.751473",\ + "0.472143, 0.707581, 0.897435, 1.202631, 1.793169",\ + "0.548324, 0.783762, 0.973616, 1.278812, 1.869350",\ + "0.803720, 1.039157, 1.229011, 1.534208, 2.124746",\ + "1.728097, 1.963542, 2.153391, 2.458586, 3.049126",\ + "0.518928, 0.753203, 0.943019, 1.248240, 1.838826",\ + "0.560625, 0.794899, 0.984715, 1.289936, 1.880523",\ + "0.636806, 0.871080, 1.060897, 1.366117, 1.956704",\ + "0.892201, 1.126475, 1.316292, 1.621513, 2.212099",\ + "1.816579, 2.050861, 2.240672, 2.545891, 3.136479",\ + "0.608483, 0.833536, 1.023046, 1.328268, 1.918858",\ + "0.650179, 0.875232, 1.064742, 1.369964, 1.960554",\ + "0.726361, 0.951413, 1.140924, 1.446146, 2.036736",\ + "0.981756, 1.206808, 1.396319, 1.701541, 2.292131",\ + "1.906135, 2.131194, 2.320698, 2.625919, 3.216511",\ + "0.672303, 0.891371, 1.080767, 1.385734, 1.975946",\ + "0.713999, 0.933067, 1.122464, 1.427431, 2.017642",\ + "0.790181, 1.009248, 1.198645, 1.503612, 2.093823",\ + "1.045576, 1.264643, 1.454041, 1.759007, 2.349219",\ + "1.969955, 2.189029, 2.378420, 2.683385, 3.273599",\ + "1.009821, 1.196720, 1.384428, 1.688937, 2.278255",\ + "1.051517, 1.238416, 1.426124, 1.730633, 2.319951",\ + "1.127699, 1.314597, 1.502305, 1.806814, 2.396132",\ + "1.383094, 1.569992, 1.757701, 2.062210, 2.651528",\ + "2.307477, 2.494378, 2.682080, 2.986588, 3.575908"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199414, 0.199414, 0.199414, 0.199415, 0.199419",\ + "0.685786, 0.685786, 0.685786, 0.685787, 0.685790",\ + "2.455200, 2.455200, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.450692, 0.686130, 0.875983, 1.181180, 1.771718",\ + "0.482941, 0.718379, 0.908233, 1.213429, 1.803968",\ + "0.533254, 0.768692, 0.958545, 1.263741, 1.854280",\ + "0.693917, 0.929356, 1.119209, 1.424405, 2.014944",\ + "1.275051, 1.510488, 1.700342, 2.005539, 2.596077",\ + "0.539173, 0.773448, 0.963264, 1.268485, 1.859071",\ + "0.571423, 0.805697, 0.995514, 1.300734, 1.891321",\ + "0.621735, 0.856010, 1.045826, 1.351047, 1.941633",\ + "0.782399, 1.016674, 1.206490, 1.511710, 2.102297",\ + "1.363533, 1.597806, 1.787623, 2.092844, 2.683430",\ + "0.628728, 0.853781, 1.043291, 1.348513, 1.939103",\ + "0.660978, 0.886030, 1.075541, 1.380763, 1.971353",\ + "0.711290, 0.936343, 1.125853, 1.431075, 2.021665",\ + "0.871954, 1.097007, 1.286517, 1.591739, 2.182329",\ + "1.453087, 1.678139, 1.867650, 2.172873, 2.763462",\ + "0.692548, 0.911616, 1.101013, 1.405979, 1.996191",\ + "0.724798, 0.943865, 1.133262, 1.438229, 2.028440",\ + "0.775110, 0.994178, 1.183574, 1.488541, 2.078753",\ + "0.935774, 1.154842, 1.344238, 1.649205, 2.239417",\ + "1.516907, 1.735974, 1.925371, 2.230339, 2.820550",\ + "1.030066, 1.216965, 1.404673, 1.709182, 2.298500",\ + "1.062316, 1.249214, 1.436922, 1.741432, 2.330750",\ + "1.112628, 1.299527, 1.487235, 1.791744, 2.381062",\ + "1.273292, 1.460191, 1.647898, 1.952407, 2.541725",\ + "1.854424, 2.041323, 2.229032, 2.533541, 3.122859"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029706",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131486, 0.131486",\ + "0.419455, 0.419455, 0.419455, 0.419455, 0.419455",\ + "1.482976, 1.482976, 1.482976, 1.482977, 1.482979"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2670*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.408175, 0.641513, 0.827140, 1.126924, 1.707803",\ + "0.449871, 0.683209, 0.868836, 1.168620, 1.749499",\ + "0.526051, 0.759389, 0.945016, 1.244800, 1.825679",\ + "0.781441, 1.014779, 1.200407, 1.500191, 2.081069",\ + "1.705890, 1.939226, 2.124851, 2.424636, 3.005520",\ + "0.496580, 0.728832, 0.914421, 1.214229, 1.795156",\ + "0.538276, 0.770527, 0.956117, 1.255925, 1.836852",\ + "0.614456, 0.846708, 1.032297, 1.332105, 1.913032",\ + "0.869846, 1.102098, 1.287688, 1.587496, 2.168422",\ + "1.794296, 2.026545, 2.212132, 2.511941, 3.092873",\ + "0.585662, 0.809167, 0.994448, 1.294258, 1.875188",\ + "0.627357, 0.850863, 1.036144, 1.335954, 1.916884",\ + "0.703538, 0.927043, 1.112324, 1.412134, 1.993064",\ + "0.958928, 1.182433, 1.367714, 1.667524, 2.248454",\ + "1.883377, 2.106880, 2.292159, 2.591970, 3.172904",\ + "0.648932, 0.866998, 1.052159, 1.351712, 1.932252",\ + "0.690627, 0.908694, 1.093855, 1.393408, 1.973947",\ + "0.766807, 0.984874, 1.170035, 1.469588, 2.050128",\ + "1.022198, 1.240264, 1.425425, 1.724978, 2.305518",\ + "1.946647, 2.164711, 2.349869, 2.649424, 3.229968",\ + "0.982958, 1.172329, 1.355818, 1.654905, 2.234531",\ + "1.024654, 1.214025, 1.397514, 1.696600, 2.276227",\ + "1.100834, 1.290205, 1.473694, 1.772781, 2.352407",\ + "1.356225, 1.545595, 1.729084, 2.028171, 2.607797",\ + "2.280672, 2.470042, 2.653529, 2.952617, 3.532248"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.428422, 0.661761, 0.847388, 1.147172, 1.728051",\ + "0.460669, 0.694007, 0.879634, 1.179418, 1.760297",\ + "0.510985, 0.744323, 0.929950, 1.229734, 1.810613",\ + "0.671649, 0.904987, 1.090614, 1.390398, 1.971277",\ + "1.252766, 1.486104, 1.671732, 1.971516, 2.552394",\ + "0.516828, 0.749079, 0.934668, 1.234477, 1.815404",\ + "0.549074, 0.781326, 0.966915, 1.266723, 1.847650",\ + "0.599390, 0.831641, 1.017231, 1.317039, 1.897966",\ + "0.760054, 0.992305, 1.177894, 1.477703, 2.058630",\ + "1.341171, 1.573423, 1.759013, 2.058821, 2.639747",\ + "0.605909, 0.829414, 1.014695, 1.314505, 1.895436",\ + "0.638156, 0.861661, 1.046942, 1.346752, 1.927682",\ + "0.688472, 0.911977, 1.097257, 1.397068, 1.977998",\ + "0.849135, 1.072640, 1.257921, 1.557731, 2.138662",\ + "1.430253, 1.653758, 1.839040, 2.138849, 2.719779",\ + "0.669179, 0.887245, 1.072406, 1.371959, 1.952499",\ + "0.701426, 0.919492, 1.104653, 1.404206, 1.984746",\ + "0.751741, 0.969808, 1.154969, 1.454522, 2.035062",\ + "0.912405, 1.130471, 1.315632, 1.615185, 2.195725",\ + "1.493523, 1.711589, 1.896750, 2.196303, 2.776842",\ + "1.003206, 1.192577, 1.376065, 1.675152, 2.254779",\ + "1.035452, 1.224823, 1.408312, 1.707399, 2.287025",\ + "1.085768, 1.275139, 1.458628, 1.757715, 2.337341",\ + "1.246432, 1.435803, 1.619291, 1.918378, 2.498005",\ + "1.827550, 2.016920, 2.200410, 2.499496, 3.079122"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483047"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.454515, 0.687556, 0.876637, 1.181062, 1.770586",\ + "0.496240, 0.729281, 0.918362, 1.222787, 1.812311",\ + "0.572297, 0.805339, 0.994419, 1.298844, 1.888368",\ + "0.827855, 1.060896, 1.249979, 1.554404, 2.143927",\ + "1.752113, 1.985154, 2.174236, 2.478661, 3.068184",\ + "0.542959, 0.774874, 0.963918, 1.268367, 1.857939",\ + "0.584684, 0.816599, 1.005643, 1.310092, 1.899664",\ + "0.660741, 0.892656, 1.081700, 1.386149, 1.975721",\ + "0.916299, 1.148213, 1.337260, 1.641709, 2.231281",\ + "1.840557, 2.072472, 2.261517, 2.565966, 3.155538",\ + "0.633029, 0.855201, 1.043945, 1.348395, 1.937971",\ + "0.674754, 0.896927, 1.085670, 1.390121, 1.979696",\ + "0.750812, 0.972984, 1.161727, 1.466178, 2.055753",\ + "1.006370, 1.228541, 1.417287, 1.721738, 2.311312",\ + "1.930628, 2.152800, 2.341543, 2.645994, 3.235569",\ + "0.697606, 0.913035, 1.101665, 1.405861, 1.995059",\ + "0.739331, 0.954761, 1.143391, 1.447586, 2.036784",\ + "0.815389, 1.030818, 1.219448, 1.523643, 2.112841",\ + "1.070947, 1.286375, 1.475007, 1.779203, 2.368400",\ + "1.995205, 2.210634, 2.399264, 2.703460, 3.292657",\ + "1.037719, 1.218357, 1.405324, 1.709062, 2.297368",\ + "1.079444, 1.260083, 1.447049, 1.750787, 2.339093",\ + "1.155501, 1.336140, 1.523106, 1.826844, 2.415150",\ + "1.411059, 1.591697, 1.778666, 2.082405, 2.670709",\ + "2.335317, 2.515956, 2.702923, 3.006661, 3.594966"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452470, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452470, 2.452462, 2.452462, 2.452446, 2.452406"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.477114, 0.710155, 0.899236, 1.203661, 1.793185",\ + "0.509144, 0.742185, 0.931266, 1.235691, 1.825215",\ + "0.559532, 0.792574, 0.981654, 1.286079, 1.875603",\ + "0.720561, 0.953603, 1.142682, 1.447107, 2.036631",\ + "1.300536, 1.533577, 1.722657, 2.027082, 2.616606",\ + "0.565558, 0.797473, 0.986517, 1.290966, 1.880538",\ + "0.597588, 0.829503, 1.018547, 1.322996, 1.912568",\ + "0.647976, 0.879891, 1.068935, 1.373384, 1.962957",\ + "0.809005, 1.040920, 1.229963, 1.534412, 2.123985",\ + "1.388980, 1.620895, 1.809938, 2.114387, 2.703959",\ + "0.655628, 0.877800, 1.066544, 1.370995, 1.960570",\ + "0.687658, 0.909830, 1.098574, 1.403025, 1.992600",\ + "0.738047, 0.960219, 1.148962, 1.453413, 2.042988",\ + "0.899075, 1.121248, 1.309990, 1.614440, 2.204016",\ + "1.479050, 1.701223, 1.889965, 2.194416, 2.783991",\ + "0.720205, 0.935634, 1.124265, 1.428460, 2.017658",\ + "0.752235, 0.967664, 1.156295, 1.460490, 2.049688",\ + "0.802624, 1.018053, 1.206683, 1.510878, 2.100076",\ + "0.963652, 1.179082, 1.367711, 1.671906, 2.261104",\ + "1.543628, 1.759057, 1.947685, 2.251881, 2.841079",\ + "1.060318, 1.240956, 1.427923, 1.731662, 2.319967",\ + "1.092348, 1.272986, 1.459953, 1.763692, 2.351997",\ + "1.142736, 1.323375, 1.510341, 1.814080, 2.402385",\ + "1.303765, 1.484404, 1.671369, 1.975107, 2.563413",\ + "1.883740, 2.064379, 2.251344, 2.555082, 3.143388"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484493"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2361*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.425794, 0.659396, 0.844981, 1.144718, 1.725521",\ + "0.467517, 0.701119, 0.886704, 1.186441, 1.767244",\ + "0.543582, 0.777185, 0.962769, 1.262506, 1.843310",\ + "0.799075, 1.032669, 1.218262, 1.518000, 2.098799",\ + "1.723381, 1.956982, 2.142568, 2.442305, 3.023108",\ + "0.514202, 0.746714, 0.932262, 1.232023, 1.812875",\ + "0.555925, 0.788437, 0.973985, 1.273746, 1.854598",\ + "0.631990, 0.864504, 1.050050, 1.349811, 1.930663",\ + "0.887482, 1.119988, 1.305543, 1.605305, 2.186153",\ + "1.811789, 2.044301, 2.229849, 2.529610, 3.110461",\ + "0.603290, 0.827050, 1.012289, 1.312051, 1.892906",\ + "0.645013, 0.868772, 1.054012, 1.353774, 1.934629",\ + "0.721078, 0.944839, 1.130077, 1.429839, 2.010695",\ + "0.976570, 1.200323, 1.385570, 1.685334, 2.266185",\ + "1.900877, 2.124636, 2.309876, 2.609639, 3.190493",\ + "0.666566, 0.884881, 1.069999, 1.369505, 1.949970",\ + "0.708289, 0.926604, 1.111723, 1.411228, 1.991693",\ + "0.784354, 1.002670, 1.187788, 1.487293, 2.067758",\ + "1.039845, 1.258154, 1.443280, 1.742788, 2.323248",\ + "1.964153, 2.182467, 2.367587, 2.667093, 3.247556",\ + "1.000632, 1.190214, 1.373659, 1.672698, 2.252249",\ + "1.042355, 1.231937, 1.415382, 1.714421, 2.293972",\ + "1.118420, 1.308003, 1.491447, 1.790486, 2.370037",\ + "1.373908, 1.563487, 1.746940, 2.045980, 2.625527",\ + "2.298218, 2.487800, 2.671246, 2.970286, 3.549836"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199490, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452544, 2.452522, 2.452521, 2.452511, 2.452485",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199490, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452543, 2.452522, 2.452521, 2.452511, 2.452485",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199489, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452541, 2.452522, 2.452521, 2.452511, 2.452485",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199489, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452540, 2.452522, 2.452521, 2.452511, 2.452485",\ + "0.025353, 0.025353, 0.025353, 0.025353, 0.025353",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199485, 0.199485, 0.199485, 0.199485",\ + "0.686682, 0.686682, 0.686679, 0.686679, 0.686679",\ + "2.452530, 2.452522, 2.452521, 2.452511, 2.452485"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.448384, 0.681985, 0.867571, 1.167308, 1.748111",\ + "0.480409, 0.714010, 0.899596, 1.199333, 1.780136",\ + "0.530816, 0.764419, 0.950003, 1.249740, 1.830544",\ + "0.691874, 0.925480, 1.111061, 1.410797, 1.991603",\ + "1.271848, 1.505453, 1.691034, 1.990770, 2.571576",\ + "0.536792, 0.769304, 0.954852, 1.254613, 1.835465",\ + "0.568817, 0.801328, 0.986877, 1.286638, 1.867489",\ + "0.619224, 0.851737, 1.037284, 1.337045, 1.917897",\ + "0.780282, 1.012799, 1.198342, 1.498102, 2.078956",\ + "1.360255, 1.592772, 1.778315, 2.078075, 2.658929",\ + "0.625880, 0.849639, 1.034879, 1.334642, 1.915496",\ + "0.657905, 0.881663, 1.066904, 1.366667, 1.947521",\ + "0.708312, 0.932072, 1.117311, 1.417073, 1.997929",\ + "0.869371, 1.093134, 1.278369, 1.578131, 2.158988",\ + "1.449344, 1.673107, 1.858342, 2.158104, 2.738961",\ + "0.689156, 0.907470, 1.092590, 1.392096, 1.972560",\ + "0.721181, 0.939495, 1.124615, 1.424121, 2.004584",\ + "0.771588, 0.989904, 1.175022, 1.474527, 2.054992",\ + "0.932647, 1.150965, 1.336080, 1.635585, 2.216051",\ + "1.512620, 1.730939, 1.916053, 2.215558, 2.796025",\ + "1.023221, 1.212804, 1.396249, 1.695289, 2.274839",\ + "1.055246, 1.244828, 1.428274, 1.727314, 2.306864",\ + "1.105654, 1.295237, 1.478681, 1.777720, 2.357271",\ + "1.266715, 1.456299, 1.639739, 1.938777, 2.518331",\ + "1.846688, 2.036272, 2.219712, 2.518751, 3.098304"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417810, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484519, 1.484515, 1.484514, 1.484513, 1.484508",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417810, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484518, 1.484515, 1.484514, 1.484513, 1.484508",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417810, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484518, 1.484515, 1.484514, 1.484513, 1.484508",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131513, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417809, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484518, 1.484515, 1.484514, 1.484513, 1.484508",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059265",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417806, 0.417803, 0.417803, 0.417799, 0.417790",\ + "1.484516, 1.484515, 1.484514, 1.484513, 1.484508"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2707*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.411437, 0.641763, 0.827440, 1.121826, 1.689429",\ + "0.453163, 0.683488, 0.869165, 1.163551, 1.731154",\ + "0.529220, 0.759545, 0.945221, 1.239608, 1.807211",\ + "0.784777, 1.015107, 1.200787, 1.495173, 2.062773",\ + "1.709036, 1.939362, 2.125040, 2.419426, 2.987028",\ + "0.499750, 0.729081, 0.914721, 1.209131, 1.776782",\ + "0.541475, 0.770807, 0.956446, 1.250857, 1.818508",\ + "0.617533, 0.846863, 1.032502, 1.326913, 1.894564",\ + "0.873090, 1.102426, 1.288068, 1.582478, 2.150126",\ + "1.797349, 2.026680, 2.212321, 2.506731, 3.074381",\ + "0.588895, 0.809414, 0.994747, 1.289160, 1.856814",\ + "0.630620, 0.851139, 1.036473, 1.330885, 1.898539",\ + "0.706677, 0.927196, 1.112529, 1.406941, 1.974596",\ + "0.962234, 1.182758, 1.368095, 1.662507, 2.230158",\ + "1.886493, 2.107013, 2.292347, 2.586760, 3.154413",\ + "0.652369, 0.867238, 1.052459, 1.346598, 1.913847",\ + "0.694094, 0.908963, 1.094185, 1.388323, 1.955572",\ + "0.770151, 0.985020, 1.170241, 1.464380, 2.031629",\ + "1.025709, 1.240582, 1.425807, 1.719945, 2.287190",\ + "1.949967, 2.164837, 2.350059, 2.644198, 3.211446",\ + "0.987682, 1.172511, 1.356118, 1.649777, 2.216089",\ + "1.029408, 1.214237, 1.397843, 1.691502, 2.257815",\ + "1.105465, 1.290294, 1.473899, 1.767559, 2.333871",\ + "1.361025, 1.545856, 1.729465, 2.023124, 2.589433",\ + "2.285281, 2.470111, 2.653718, 2.947377, 3.513689"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686585, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452422"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.434036, 0.664363, 0.850040, 1.144426, 1.712028",\ + "0.466066, 0.696393, 0.882070, 1.176457, 1.744059",\ + "0.516455, 0.746780, 0.932457, 1.226843, 1.794446",\ + "0.677484, 0.907807, 1.093482, 1.387868, 1.955473",\ + "1.257459, 1.487782, 1.673457, 1.967843, 2.535448",\ + "0.522349, 0.751681, 0.937321, 1.231731, 1.799382",\ + "0.554379, 0.783711, 0.969351, 1.263762, 1.831412",\ + "0.604768, 0.834099, 1.019738, 1.314148, 1.881800",\ + "0.765797, 0.995125, 1.180763, 1.475173, 2.042827",\ + "1.345772, 1.575100, 1.760738, 2.055148, 2.622802",\ + "0.611494, 0.832013, 1.017348, 1.311760, 1.879413",\ + "0.643524, 0.864044, 1.049378, 1.343790, 1.911444",\ + "0.693912, 0.914431, 1.099764, 1.394177, 1.961831",\ + "0.854941, 1.075458, 1.260790, 1.555202, 2.122858",\ + "1.434916, 1.655433, 1.840765, 2.135177, 2.702833",\ + "0.674968, 0.889838, 1.075059, 1.369198, 1.936446",\ + "0.706998, 0.921868, 1.107090, 1.401229, 1.968477",\ + "0.757386, 0.972255, 1.157476, 1.451615, 2.018864",\ + "0.918415, 1.133282, 1.318501, 1.612640, 2.179891",\ + "1.498390, 1.713257, 1.898476, 2.192615, 2.759866",\ + "1.010282, 1.195111, 1.378718, 1.672377, 2.238689",\ + "1.042312, 1.227141, 1.410748, 1.704407, 2.270719",\ + "1.092700, 1.277529, 1.461135, 1.754794, 2.321106",\ + "1.253727, 1.438555, 1.622160, 1.915819, 2.482133",\ + "1.833702, 2.018530, 2.202135, 2.495794, 3.062109"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2292*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.506400, 0.723405, 0.901534, 1.190767, 1.752239",\ + "0.548095, 0.765101, 0.943229, 1.232462, 1.793935",\ + "0.624275, 0.841281, 1.019409, 1.308642, 1.870115",\ + "0.879665, 1.096670, 1.274799, 1.564032, 2.125504",\ + "1.804122, 2.021127, 2.199255, 2.488489, 3.049961",\ + "0.594776, 0.810723, 0.988814, 1.278072, 1.839592",\ + "0.636472, 0.852419, 1.030510, 1.319767, 1.881288",\ + "0.712652, 0.928599, 1.106690, 1.395947, 1.957468",\ + "0.968041, 1.183989, 1.362080, 1.651337, 2.212858",\ + "1.892498, 2.108445, 2.286536, 2.575794, 3.137315",\ + "0.684027, 0.891056, 1.068841, 1.358100, 1.919624",\ + "0.725722, 0.932752, 1.110537, 1.399796, 1.961320",\ + "0.801902, 1.008932, 1.186717, 1.475976, 2.037500",\ + "1.057292, 1.264322, 1.442107, 1.731366, 2.292889",\ + "1.981749, 2.188778, 2.366563, 2.655822, 3.217346",\ + "0.747566, 0.948873, 1.126535, 1.415531, 1.976642",\ + "0.789261, 0.990569, 1.168231, 1.457227, 2.018338",\ + "0.865441, 1.066749, 1.244411, 1.533407, 2.094518",\ + "1.120831, 1.322138, 1.499801, 1.788796, 2.349907",\ + "2.045288, 2.246595, 2.424257, 2.713253, 3.274364",\ + "1.075492, 1.254095, 1.430191, 1.718704, 2.278866",\ + "1.117188, 1.295791, 1.471887, 1.760399, 2.320562",\ + "1.193368, 1.371971, 1.548067, 1.836579, 2.396742",\ + "1.448757, 1.627361, 1.803456, 2.091969, 2.652131",\ + "2.373214, 2.551817, 2.727913, 3.016426, 3.576588"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199408, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.526648, 0.743653, 0.921781, 1.211015, 1.772487",\ + "0.558894, 0.775899, 0.954027, 1.243261, 1.804733",\ + "0.609210, 0.826215, 1.004344, 1.293577, 1.855049",\ + "0.769874, 0.986879, 1.165008, 1.454241, 2.015713",\ + "1.350989, 1.567995, 1.746123, 2.035356, 2.596828",\ + "0.615024, 0.830971, 1.009062, 1.298320, 1.859840",\ + "0.647270, 0.863217, 1.041308, 1.330566, 1.892087",\ + "0.697586, 0.913533, 1.091625, 1.380882, 1.942403",\ + "0.858250, 1.074197, 1.252288, 1.541546, 2.103066",\ + "1.439366, 1.655313, 1.833404, 2.122661, 2.684182",\ + "0.704275, 0.911304, 1.089089, 1.378348, 1.939872",\ + "0.736521, 0.943550, 1.121335, 1.410594, 1.972118",\ + "0.786837, 0.993866, 1.171651, 1.460910, 2.022434",\ + "0.947501, 1.154530, 1.332315, 1.621574, 2.183098",\ + "1.528616, 1.735646, 1.913431, 2.202690, 2.764214",\ + "0.767814, 0.969121, 1.146783, 1.435779, 1.996890",\ + "0.800060, 1.001367, 1.179029, 1.468025, 2.029136",\ + "0.850376, 1.051683, 1.229346, 1.518341, 2.079452",\ + "1.011040, 1.212347, 1.390009, 1.679005, 2.240116",\ + "1.592155, 1.793463, 1.971125, 2.260120, 2.821231",\ + "1.095740, 1.274343, 1.450439, 1.738951, 2.299114",\ + "1.127986, 1.306589, 1.482685, 1.771198, 2.331360",\ + "1.178302, 1.356906, 1.533001, 1.821514, 2.381676",\ + "1.338966, 1.517570, 1.693665, 1.982178, 2.542340",\ + "1.920082, 2.098685, 2.274781, 2.563293, 3.123456"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419485, 0.419485, 0.419484, 0.419483, 0.419481",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2480*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.487215, 0.727664, 0.917972, 1.220770, 1.805421",\ + "0.528910, 0.769360, 0.959668, 1.262466, 1.847117",\ + "0.605090, 0.845540, 1.035848, 1.338646, 1.923296",\ + "0.860480, 1.100929, 1.291238, 1.594035, 2.178686",\ + "1.784937, 2.025386, 2.215694, 2.518492, 3.103143",\ + "0.575514, 0.814982, 1.005253, 1.308075, 1.892774",\ + "0.617210, 0.856678, 1.046949, 1.349771, 1.934470",\ + "0.693390, 0.932858, 1.123129, 1.425951, 2.010650",\ + "0.948779, 1.188247, 1.378519, 1.681340, 2.266040",\ + "1.873236, 2.112704, 2.302975, 2.605797, 3.190496",\ + "0.664798, 0.895313, 1.085280, 1.388104, 1.972806",\ + "0.706493, 0.937009, 1.126976, 1.429799, 2.014502",\ + "0.782673, 1.013189, 1.203156, 1.505979, 2.090682",\ + "1.038063, 1.268578, 1.458545, 1.761369, 2.346071",\ + "1.962520, 2.193035, 2.383002, 2.685826, 3.270528",\ + "0.728479, 0.953177, 1.143002, 1.445563, 2.029881",\ + "0.770175, 0.994873, 1.184698, 1.487259, 2.071577",\ + "0.846355, 1.071053, 1.260878, 1.563439, 2.147756",\ + "1.101744, 1.326442, 1.516268, 1.818828, 2.403146",\ + "2.026201, 2.250899, 2.440724, 2.743285, 3.327603",\ + "1.065102, 1.258723, 1.446662, 1.748759, 2.332174",\ + "1.106798, 1.300419, 1.488358, 1.790455, 2.373869",\ + "1.182978, 1.376599, 1.564538, 1.866635, 2.450049",\ + "1.438367, 1.631989, 1.819927, 2.122025, 2.705439",\ + "2.362824, 2.556445, 2.744384, 3.046481, 3.629896"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199410, 0.199412",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.507462, 0.747912, 0.938220, 1.241018, 1.825669",\ + "0.539708, 0.780158, 0.970466, 1.273264, 1.857915",\ + "0.590025, 0.830474, 1.020782, 1.323580, 1.908231",\ + "0.750689, 0.991138, 1.181446, 1.484244, 2.068895",\ + "1.331804, 1.572254, 1.762562, 2.065360, 2.650010",\ + "0.595762, 0.835230, 1.025501, 1.328323, 1.913022",\ + "0.628008, 0.867476, 1.057747, 1.360569, 1.945268",\ + "0.678324, 0.917792, 1.108063, 1.410885, 1.995584",\ + "0.838988, 1.078456, 1.268727, 1.571549, 2.156248",\ + "1.420103, 1.659572, 1.849843, 2.152665, 2.737364",\ + "0.685045, 0.915561, 1.105528, 1.408352, 1.993054",\ + "0.717292, 0.947807, 1.137774, 1.440598, 2.025300",\ + "0.767608, 0.998123, 1.188090, 1.490914, 2.075616",\ + "0.928272, 1.158787, 1.348754, 1.651578, 2.236280",\ + "1.509387, 1.739902, 1.929870, 2.232693, 2.817395",\ + "0.748727, 0.973425, 1.163250, 1.465811, 2.050128",\ + "0.780973, 1.005671, 1.195496, 1.498057, 2.082375",\ + "0.831289, 1.055987, 1.245812, 1.548373, 2.132691",\ + "0.991953, 1.216651, 1.406476, 1.709037, 2.293355",\ + "1.573069, 1.797767, 1.987592, 2.290153, 2.874470",\ + "1.085350, 1.278971, 1.466910, 1.769007, 2.352422",\ + "1.117596, 1.311217, 1.499156, 1.801253, 2.384668",\ + "1.167912, 1.361534, 1.549472, 1.851569, 2.434984",\ + "1.328576, 1.522197, 1.710136, 2.012233, 2.595648",\ + "1.909692, 2.103313, 2.291251, 2.593349, 3.176763"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419485, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419484, 0.419484, 0.419483, 0.419481, 0.419478",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2458*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.401855, 0.617772, 0.797138, 1.086913, 1.648811",\ + "0.443578, 0.659495, 0.838861, 1.128636, 1.690534",\ + "0.519643, 0.735561, 0.914927, 1.204702, 1.766600",\ + "0.775133, 0.991049, 1.170417, 1.460191, 2.022084",\ + "1.699442, 1.915359, 2.094725, 2.384500, 2.946397",\ + "0.490138, 0.705090, 0.884419, 1.174218, 1.736165",\ + "0.531861, 0.746813, 0.926142, 1.215941, 1.777887",\ + "0.607927, 0.822879, 1.002208, 1.292007, 1.853954",\ + "0.863417, 1.078367, 1.257698, 1.547496, 2.109437",\ + "1.787725, 2.002677, 2.182006, 2.471805, 3.033750",\ + "0.579402, 0.785421, 0.964446, 1.254247, 1.816196",\ + "0.621125, 0.827144, 1.006169, 1.295970, 1.857919",\ + "0.697191, 0.903209, 1.082235, 1.372035, 1.933985",\ + "0.952680, 1.158697, 1.337725, 1.627524, 2.189469",\ + "1.876989, 2.083007, 2.262033, 2.551833, 3.113782",\ + "0.643076, 0.843251, 1.022143, 1.311678, 1.873216",\ + "0.684799, 0.884974, 1.063866, 1.353401, 1.914939",\ + "0.760865, 0.961040, 1.139932, 1.429467, 1.991005",\ + "1.016354, 1.216527, 1.395422, 1.684956, 2.246489",\ + "1.940663, 2.140838, 2.319730, 2.609265, 3.170802",\ + "0.967710, 1.148559, 1.325799, 1.614851, 2.175443",\ + "1.009433, 1.190282, 1.367522, 1.656574, 2.217166",\ + "1.085498, 1.266348, 1.443587, 1.732640, 2.293232",\ + "1.340988, 1.521835, 1.699077, 1.988128, 2.548716",\ + "2.265296, 2.446146, 2.623385, 2.912438, 3.473029"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.424445, 0.640362, 0.819728, 1.109503, 1.671400",\ + "0.456469, 0.672387, 0.851753, 1.141528, 1.703424",\ + "0.506877, 0.722795, 0.902161, 1.191936, 1.753834",\ + "0.667936, 0.883855, 1.063220, 1.352995, 1.914896",\ + "1.247909, 1.463828, 1.643193, 1.932969, 2.494869",\ + "0.512729, 0.727680, 0.907009, 1.196808, 1.758754",\ + "0.544753, 0.759704, 0.939034, 1.228833, 1.790778",\ + "0.595161, 0.810113, 0.989442, 1.279241, 1.841187",\ + "0.756220, 0.971173, 1.150501, 1.440300, 2.002249",\ + "1.336193, 1.551146, 1.730474, 2.020274, 2.582222",\ + "0.601992, 0.808011, 0.987036, 1.276837, 1.838785",\ + "0.634017, 0.840035, 1.019061, 1.308861, 1.870810",\ + "0.684425, 0.890443, 1.069469, 1.359269, 1.921219",\ + "0.845484, 1.051504, 1.230528, 1.520329, 2.082281",\ + "1.425457, 1.631477, 1.810501, 2.100302, 2.662254",\ + "0.665666, 0.865841, 1.044734, 1.334268, 1.895805",\ + "0.697691, 0.897865, 1.076758, 1.366293, 1.927830",\ + "0.748099, 0.948274, 1.127166, 1.416701, 1.978239",\ + "0.909158, 1.109334, 1.288225, 1.577760, 2.139301",\ + "1.489131, 1.689307, 1.868198, 2.157734, 2.719274",\ + "0.990300, 1.171149, 1.348389, 1.637441, 2.198032",\ + "1.022324, 1.203173, 1.380413, 1.669466, 2.230056",\ + "1.072732, 1.253582, 1.430821, 1.719874, 2.280466",\ + "1.233791, 1.414642, 1.591880, 1.880933, 2.441528",\ + "1.813765, 1.994615, 2.171854, 2.460907, 3.021501"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[8]_redg_min_2440*/ + +} /* end of pin tl_o[8] */ + +pin("tl_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.035370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.763083, 1.005361, 1.270323, 1.744250, 2.692104",\ + "0.776922, 1.019201, 1.284163, 1.758090, 2.705944",\ + "0.800433, 1.042711, 1.307673, 1.781600, 2.729455",\ + "1.069305, 1.311583, 1.576544, 2.050472, 2.998326",\ + "1.663833, 1.906111, 2.171072, 2.644999, 3.592854",\ + "0.850491, 1.092832, 1.357904, 1.830964, 2.778038",\ + "0.864331, 1.106672, 1.371744, 1.844804, 2.791878",\ + "0.887842, 1.130182, 1.395254, 1.868315, 2.815388",\ + "1.156713, 1.399054, 1.664126, 2.137186, 3.084260",\ + "1.751242, 1.993582, 2.258653, 2.731714, 3.678787",\ + "0.931306, 1.181626, 1.445868, 1.918586, 2.864993",\ + "0.945146, 1.195466, 1.459708, 1.932426, 2.878833",\ + "0.968656, 1.218976, 1.483218, 1.955936, 2.902343",\ + "1.237528, 1.487848, 1.752090, 2.224808, 3.171215",\ + "1.832057, 2.082376, 2.346617, 2.819335, 3.765743",\ + "0.989274, 1.246989, 1.510009, 1.982499, 2.928502",\ + "1.003114, 1.260829, 1.523849, 1.996339, 2.942342",\ + "1.026624, 1.284340, 1.547359, 2.019849, 2.965852",\ + "1.295496, 1.553211, 1.816230, 2.288721, 3.234724",\ + "1.890025, 2.147739, 2.410758, 2.883248, 3.829252",\ + "1.322822, 1.608220, 1.861925, 2.331865, 3.273958",\ + "1.336662, 1.622059, 1.875765, 2.345705, 3.287798",\ + "1.360173, 1.645570, 1.899276, 2.369215, 3.311308",\ + "1.629045, 1.914441, 2.168147, 2.638086, 3.580180",\ + "2.223573, 2.508969, 2.762674, 3.232614, 4.174707"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\ + "0.157856, 0.157859, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\ + "0.157856, 0.157859, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\ + "0.157856, 0.157860, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129969, 0.129995, 0.130055, 0.130175",\ + "0.157856, 0.157860, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203047, 0.203054, 0.203070, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129972, 0.129996, 0.130055, 0.130175",\ + "0.157856, 0.157861, 0.157877, 0.157917, 0.157996",\ + "0.203046, 0.203048, 0.203055, 0.203071, 0.203103",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.698169, 0.940449, 1.205412, 1.679339, 2.627193",\ + "0.711314, 0.953594, 1.218557, 1.692484, 2.640338",\ + "0.732465, 0.974745, 1.239707, 1.713634, 2.661488",\ + "0.908675, 1.150953, 1.415913, 1.889840, 2.837695",\ + "1.242989, 1.485267, 1.750227, 2.224154, 3.172009",\ + "0.785578, 1.027920, 1.292994, 1.766054, 2.713127",\ + "0.798723, 1.041065, 1.306139, 1.779198, 2.726272",\ + "0.819874, 1.062215, 1.327289, 1.800348, 2.747422",\ + "0.996084, 1.238424, 1.503495, 1.976555, 2.923629",\ + "1.330398, 1.572737, 1.837808, 2.310869, 3.257943",\ + "0.866392, 1.116714, 1.380958, 1.853675, 2.800082",\ + "0.879538, 1.129859, 1.394103, 1.866820, 2.813227",\ + "0.900689, 1.151010, 1.415252, 1.887970, 2.834377",\ + "1.076899, 1.327218, 1.591458, 2.064176, 3.010584",\ + "1.411212, 1.661532, 1.925772, 2.398490, 3.344898",\ + "0.924360, 1.182077, 1.445098, 1.917589, 2.863591",\ + "0.937505, 1.195222, 1.458243, 1.930733, 2.876736",\ + "0.958657, 1.216373, 1.479393, 1.951883, 2.897886",\ + "1.134866, 1.392581, 1.655599, 2.128089, 3.074093",\ + "1.469180, 1.726895, 1.989913, 2.462403, 3.408407",\ + "1.257909, 1.543308, 1.797015, 2.266954, 3.209047",\ + "1.271054, 1.556453, 1.810160, 2.280099, 3.222192",\ + "1.292205, 1.577603, 1.831310, 2.301249, 3.243342",\ + "1.468415, 1.753811, 2.007515, 2.477455, 3.419549",\ + "1.802729, 2.088125, 2.341829, 2.811769, 3.753863"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026304, 1.026307, 1.026312",\ + "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026305, 1.026307, 1.026312",\ + "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026305, 1.026307, 1.026312",\ + "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026305, 1.026307, 1.026312",\ + "0.086495, 0.086495, 0.086495, 0.086495, 0.086495",\ + "0.090876, 0.090876, 0.090876, 0.090876, 0.090876",\ + "0.110244, 0.110244, 0.110244, 0.110244, 0.110244",\ + "0.380767, 0.380767, 0.380767, 0.380768, 0.380769",\ + "1.026303, 1.026303, 1.026305, 1.026307, 1.026312"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2625*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.787208, 1.042240, 1.299016, 1.737737, 2.615179",\ + "0.801048, 1.056080, 1.312856, 1.751576, 2.629018",\ + "0.824558, 1.079590, 1.336366, 1.775087, 2.652528",\ + "1.093430, 1.348462, 1.605238, 2.043957, 2.921395",\ + "1.687959, 1.942991, 2.199766, 2.638483, 3.515917",\ + "0.874617, 1.129725, 1.386486, 1.824451, 2.701113",\ + "0.888456, 1.143564, 1.400326, 1.838291, 2.714952",\ + "0.911967, 1.167075, 1.423836, 1.861801, 2.738462",\ + "1.180839, 1.435947, 1.692708, 2.130671, 3.007329",\ + "1.775367, 2.030476, 2.287236, 2.725197, 3.601851",\ + "0.962301, 1.218548, 1.474448, 1.912073, 2.788068",\ + "0.976141, 1.232388, 1.488288, 1.925912, 2.801907",\ + "0.999652, 1.255898, 1.511798, 1.949423, 2.825417",\ + "1.268523, 1.524770, 1.780670, 2.218293, 3.094284",\ + "1.863052, 2.119299, 2.375198, 2.812819, 3.688806",\ + "1.025488, 1.283954, 1.538583, 1.975986, 2.851577",\ + "1.039328, 1.297794, 1.552423, 1.989825, 2.865416",\ + "1.062838, 1.321304, 1.575933, 2.013336, 2.888926",\ + "1.331710, 1.590176, 1.844805, 2.282206, 3.157793",\ + "1.926239, 2.184705, 2.439332, 2.876732, 3.752315",\ + "1.358969, 1.645690, 1.890142, 2.325206, 3.197033",\ + "1.372809, 1.659530, 1.903982, 2.339045, 3.210872",\ + "1.396320, 1.683041, 1.927492, 2.362556, 3.234382",\ + "1.665192, 1.951913, 2.196364, 2.631425, 3.503249",\ + "2.259720, 2.546442, 2.790892, 3.225951, 4.097771"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129962, 0.129962, 0.129971, 0.130001, 0.130060",\ + "0.157855, 0.157855, 0.157861, 0.157880, 0.157920",\ + "0.203046, 0.203046, 0.203048, 0.203056, 0.203072",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.722294, 0.977326, 1.234104, 1.672832, 2.550288",\ + "0.735440, 0.990472, 1.247249, 1.685975, 2.563427",\ + "0.756591, 1.011623, 1.268399, 1.707123, 2.584570",\ + "0.932801, 1.187833, 1.444607, 1.883322, 2.760752",\ + "1.267115, 1.522147, 1.778921, 2.217637, 3.095068",\ + "0.809702, 1.064811, 1.321574, 1.759546, 2.636222",\ + "0.822848, 1.077956, 1.334719, 1.772689, 2.649361",\ + "0.843999, 1.099107, 1.355870, 1.793837, 2.670504",\ + "1.020210, 1.275318, 1.532078, 1.970036, 2.846686",\ + "1.354523, 1.609631, 1.866392, 2.304351, 3.181002",\ + "0.897387, 1.153634, 1.409536, 1.847168, 2.723177",\ + "0.910533, 1.166780, 1.422681, 1.860311, 2.736316",\ + "0.931684, 1.187931, 1.443832, 1.881459, 2.757459",\ + "1.107894, 1.364141, 1.620039, 2.057658, 2.933641",\ + "1.442208, 1.698455, 1.954353, 2.391973, 3.267957",\ + "0.960574, 1.219040, 1.473671, 1.911081, 2.786686",\ + "0.973719, 1.232186, 1.486816, 1.924224, 2.799825",\ + "0.994870, 1.253337, 1.507966, 1.945372, 2.820968",\ + "1.171081, 1.429547, 1.684174, 2.121571, 2.997150",\ + "1.505394, 1.763861, 2.018488, 2.455886, 3.331466",\ + "1.294055, 1.580776, 1.825230, 2.260301, 3.132142",\ + "1.307201, 1.593922, 1.838375, 2.273444, 3.145281",\ + "1.328352, 1.615073, 1.859525, 2.294591, 3.166424",\ + "1.504562, 1.791284, 2.035733, 2.470791, 3.342606",\ + "1.838876, 2.125597, 2.370047, 2.805105, 3.676922"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\ + "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\ + "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\ + "0.086495, 0.086495, 0.086490, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307",\ + "0.086495, 0.086495, 0.086489, 0.086470, 0.086430",\ + "0.090877, 0.090877, 0.090872, 0.090854, 0.090818",\ + "0.110245, 0.110245, 0.110240, 0.110223, 0.110189",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026303, 1.026305, 1.026307"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2692*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.841286, 1.079720, 1.357044, 1.842422, 2.813178",\ + "0.855126, 1.093560, 1.370884, 1.856262, 2.827017",\ + "0.878637, 1.117071, 1.394394, 1.879772, 2.850528",\ + "1.147509, 1.385943, 1.663266, 2.148643, 3.119398",\ + "1.742037, 1.980471, 2.257795, 2.743171, 3.713924",\ + "0.928696, 1.167248, 1.444662, 1.929136, 2.899111",\ + "0.942536, 1.181088, 1.458502, 1.942976, 2.912951",\ + "0.966046, 1.204598, 1.482012, 1.966486, 2.936461",\ + "1.234918, 1.473470, 1.750884, 2.235358, 3.205331",\ + "1.829447, 2.067999, 2.345412, 2.829885, 3.799858",\ + "1.009558, 1.256174, 1.532627, 2.016758, 2.986066",\ + "1.023398, 1.270014, 1.546467, 2.030598, 2.999906",\ + "1.046908, 1.293524, 1.569977, 2.054108, 3.023416",\ + "1.315780, 1.562396, 1.838849, 2.322979, 3.292286",\ + "1.910309, 2.156925, 2.433377, 2.917507, 3.886813",\ + "1.067230, 1.321729, 1.596769, 2.080671, 3.049575",\ + "1.081070, 1.335569, 1.610609, 2.094511, 3.063415",\ + "1.104580, 1.359079, 1.634119, 2.118021, 3.086925",\ + "1.373452, 1.627951, 1.902991, 2.386893, 3.355795",\ + "1.967981, 2.222480, 2.497520, 2.981421, 3.950322",\ + "1.388249, 1.685192, 1.948802, 2.430085, 3.395031",\ + "1.402089, 1.699032, 1.962642, 2.443925, 3.408871",\ + "1.425600, 1.722542, 1.986153, 2.467435, 3.432381",\ + "1.694472, 1.991414, 2.255024, 2.736306, 3.701252",\ + "2.289001, 2.585943, 2.849553, 3.330834, 4.295778"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129963, 0.129966, 0.129976, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203046, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129963, 0.129963, 0.129966, 0.129977, 0.129998",\ + "0.157855, 0.157855, 0.157857, 0.157864, 0.157879",\ + "0.203046, 0.203046, 0.203047, 0.203049, 0.203055",\ + "0.823721, 0.823721, 0.823721, 0.823721, 0.823721",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.776372, 1.014807, 1.292131, 1.777511, 2.748272",\ + "0.789518, 1.027952, 1.305276, 1.790656, 2.761415",\ + "0.810669, 1.049103, 1.326427, 1.811806, 2.782563",\ + "0.986879, 1.225313, 1.502636, 1.988012, 2.958764",\ + "1.321193, 1.559627, 1.836950, 2.322326, 3.293078",\ + "0.863782, 1.102334, 1.379749, 1.864226, 2.834206",\ + "0.876927, 1.115480, 1.392894, 1.877370, 2.847349",\ + "0.898079, 1.136631, 1.414045, 1.898520, 2.868497",\ + "1.074289, 1.312841, 1.590254, 2.074727, 3.044697",\ + "1.408602, 1.647155, 1.924568, 2.409040, 3.379012",\ + "0.944644, 1.191260, 1.467714, 1.951848, 2.921161",\ + "0.957790, 1.204406, 1.480859, 1.964992, 2.934304",\ + "0.978941, 1.225557, 1.502010, 1.986142, 2.955452",\ + "1.155151, 1.401767, 1.678219, 2.162348, 3.131652",\ + "1.489465, 1.736081, 2.012533, 2.496662, 3.465967",\ + "1.002316, 1.256815, 1.531856, 2.015761, 2.984670",\ + "1.015462, 1.269960, 1.545001, 2.028905, 2.997813",\ + "1.036613, 1.291111, 1.566152, 2.050055, 3.018961",\ + "1.212823, 1.467322, 1.742362, 2.226262, 3.195161",\ + "1.547137, 1.801636, 2.076675, 2.560575, 3.529476",\ + "1.323336, 1.620278, 1.883889, 2.365174, 3.330126",\ + "1.336481, 1.633424, 1.897034, 2.378319, 3.343269",\ + "1.357632, 1.654575, 1.918185, 2.399469, 3.364417",\ + "1.533842, 1.830785, 2.094395, 2.575675, 3.540617",\ + "1.868156, 2.165099, 2.428709, 2.909989, 3.874932"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\ + "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\ + "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\ + "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305",\ + "0.086495, 0.086495, 0.086493, 0.086486, 0.086471",\ + "0.090877, 0.090877, 0.090875, 0.090868, 0.090855",\ + "0.110244, 0.110244, 0.110243, 0.110237, 0.110224",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380767",\ + "1.026303, 1.026303, 1.026303, 1.026304, 1.026305"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.798247, 1.048384, 1.323795, 1.814843, 2.796940",\ + "0.812087, 1.062224, 1.337635, 1.828683, 2.810778",\ + "0.835598, 1.085734, 1.361145, 1.852193, 2.834289",\ + "1.104470, 1.354606, 1.630016, 2.121061, 3.103152",\ + "1.698998, 1.949135, 2.224544, 2.715585, 3.697667",\ + "0.885653, 1.135896, 1.411429, 1.901557, 2.882874",\ + "0.899493, 1.149736, 1.425268, 1.915396, 2.896712",\ + "0.923003, 1.173246, 1.448779, 1.938907, 2.920223",\ + "1.191875, 1.442118, 1.717650, 2.207775, 3.189086",\ + "1.786403, 2.036647, 2.312177, 2.802298, 3.783601",\ + "0.966497, 1.224769, 1.499393, 1.989178, 2.969829",\ + "0.980337, 1.238609, 1.513233, 2.003017, 2.983667",\ + "1.003847, 1.262119, 1.536743, 2.026528, 3.007178",\ + "1.272719, 1.530991, 1.805614, 2.295396, 3.276041",\ + "1.867248, 2.125520, 2.400141, 2.889919, 3.870556",\ + "1.026473, 1.290246, 1.563536, 2.053091, 3.033338",\ + "1.040313, 1.304086, 1.577376, 2.066930, 3.047176",\ + "1.063823, 1.327596, 1.600886, 2.090441, 3.070687",\ + "1.332695, 1.596468, 1.869757, 2.359309, 3.339550",\ + "1.927224, 2.190996, 2.464285, 2.953832, 3.934065",\ + "1.363781, 1.652852, 1.915624, 2.402524, 3.378794",\ + "1.377621, 1.666692, 1.929464, 2.416363, 3.392632",\ + "1.401132, 1.690202, 1.952974, 2.439874, 3.416142",\ + "1.670003, 1.959074, 2.221846, 2.708742, 3.685006",\ + "2.264532, 2.553603, 2.816373, 3.303265, 4.279521"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.129964, 0.129964, 0.129977, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145",\ + "0.129964, 0.129964, 0.129978, 0.130025, 0.130119",\ + "0.157856, 0.157856, 0.157865, 0.157896, 0.157959",\ + "0.203046, 0.203046, 0.203050, 0.203062, 0.203088",\ + "0.823721, 0.823721, 0.823721, 0.823720, 0.823720",\ + "2.222145, 2.222145, 2.222145, 2.222145, 2.222145"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.733334, 0.983470, 1.258885, 1.749946, 2.732069",\ + "0.746479, 0.996616, 1.272029, 1.763087, 2.745203",\ + "0.767630, 1.017767, 1.293179, 1.784232, 2.766337",\ + "0.943840, 1.193977, 1.469384, 1.960422, 2.942497",\ + "1.278154, 1.528290, 1.803698, 2.294737, 3.276814",\ + "0.820739, 1.070982, 1.346519, 1.836660, 2.818002",\ + "0.833884, 1.084128, 1.359663, 1.849801, 2.831136",\ + "0.855036, 1.105279, 1.380813, 1.870946, 2.852271",\ + "1.031245, 1.281489, 1.557018, 2.047136, 3.028431",\ + "1.365559, 1.615803, 1.891332, 2.381451, 3.362748",\ + "0.901583, 1.159855, 1.434483, 1.924281, 2.904958",\ + "0.914729, 1.173001, 1.447627, 1.937422, 2.918091",\ + "0.935880, 1.194152, 1.468777, 1.958567, 2.939226",\ + "1.112090, 1.370362, 1.644982, 2.134757, 3.115386",\ + "1.446404, 1.704675, 1.979296, 2.469072, 3.449703",\ + "0.961559, 1.225332, 1.498626, 1.988194, 2.968467",\ + "0.974705, 1.238478, 1.511771, 2.001335, 2.981600",\ + "0.995856, 1.259629, 1.532920, 2.022480, 3.002735",\ + "1.172065, 1.435838, 1.709126, 2.198669, 3.178895",\ + "1.506379, 1.770152, 2.043440, 2.532985, 3.513212",\ + "1.298868, 1.587939, 1.850715, 2.337627, 3.313922",\ + "1.312013, 1.601084, 1.863859, 2.350768, 3.327056",\ + "1.333164, 1.622235, 1.885009, 2.371913, 3.348191",\ + "1.509374, 1.798445, 2.061214, 2.548103, 3.524351",\ + "1.843688, 2.132759, 2.395528, 2.882418, 3.858668"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\ + "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\ + "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\ + "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\ + "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\ + "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\ + "0.086494, 0.086494, 0.086484, 0.086448, 0.086375",\ + "0.090876, 0.090876, 0.090867, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110235, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310",\ + "0.086494, 0.086494, 0.086483, 0.086447, 0.086375",\ + "0.090876, 0.090876, 0.090866, 0.090834, 0.090768",\ + "0.110244, 0.110244, 0.110234, 0.110204, 0.110143",\ + "0.380767, 0.380767, 0.380767, 0.380767, 0.380768",\ + "1.026303, 1.026303, 1.026304, 1.026306, 1.026310"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2506*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.669029, 0.924047, 1.180422, 1.619320, 2.497118",\ + "0.682742, 0.937760, 1.194134, 1.633031, 2.510826",\ + "0.706267, 0.961286, 1.217660, 1.656557, 2.534352",\ + "0.974450, 1.229468, 1.485840, 1.924731, 2.802514",\ + "1.567911, 1.822930, 2.079299, 2.518181, 3.395944",\ + "0.756434, 1.011535, 1.267892, 1.706034, 2.583051",\ + "0.770147, 1.025247, 1.281604, 1.719745, 2.596760",\ + "0.793673, 1.048773, 1.305130, 1.743271, 2.620286",\ + "1.061855, 1.316955, 1.573310, 2.011445, 2.888448",\ + "1.655316, 1.910417, 2.166769, 2.604894, 3.481877",\ + "0.844902, 1.100352, 1.355853, 1.793655, 2.670006",\ + "0.858615, 1.114065, 1.369565, 1.807366, 2.683715",\ + "0.882141, 1.137591, 1.393091, 1.830892, 2.707241",\ + "1.150323, 1.405773, 1.661271, 2.099066, 2.975403",\ + "1.743784, 1.999234, 2.254730, 2.692515, 3.568832",\ + "0.908398, 1.165749, 1.419987, 1.857568, 2.733515",\ + "0.922111, 1.179461, 1.433699, 1.871279, 2.747224",\ + "0.945637, 1.202987, 1.457225, 1.894805, 2.770750",\ + "1.213819, 1.471169, 1.725405, 2.162979, 3.038912",\ + "1.807280, 2.064631, 2.318864, 2.756428, 3.632341",\ + "1.243831, 1.527415, 1.771546, 2.206786, 3.078971",\ + "1.257544, 1.541128, 1.785259, 2.220497, 3.092680",\ + "1.281070, 1.564654, 1.808785, 2.244023, 3.116206",\ + "1.549252, 1.832836, 2.076965, 2.512197, 3.384368",\ + "2.142714, 2.426297, 2.670424, 3.105646, 3.977798"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126072, 0.126070",\ + "0.155270, 0.155270, 0.155270, 0.155269, 0.155268",\ + "0.202000, 0.202000, 0.202000, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823663",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.607434, 0.862452, 1.118835, 1.557764, 2.435622",\ + "0.619657, 0.874676, 1.131056, 1.569977, 2.447818",\ + "0.639561, 0.894580, 1.150957, 1.589866, 2.467684",\ + "0.811812, 1.066830, 1.323197, 1.762070, 2.639816",\ + "1.146382, 1.401400, 1.657768, 2.096643, 2.974393",\ + "0.694839, 0.949939, 1.206305, 1.644478, 2.521555",\ + "0.707062, 0.962163, 1.218526, 1.656691, 2.533751",\ + "0.726967, 0.982067, 1.238427, 1.676580, 2.553618",\ + "0.899217, 1.154317, 1.410667, 1.848784, 2.725749",\ + "1.233787, 1.488888, 1.745238, 2.183357, 3.060327",\ + "0.783307, 1.038757, 1.294266, 1.732099, 2.608510",\ + "0.795531, 1.050981, 1.306487, 1.744312, 2.620707",\ + "0.815435, 1.070885, 1.326388, 1.764201, 2.640573",\ + "0.987685, 1.243135, 1.498628, 1.936405, 2.812705",\ + "1.322255, 1.577705, 1.833199, 2.270978, 3.147282",\ + "0.846803, 1.104153, 1.358401, 1.796012, 2.672019",\ + "0.859026, 1.116377, 1.370622, 1.808224, 2.684216",\ + "0.878930, 1.136281, 1.390523, 1.828114, 2.704082",\ + "1.051181, 1.308532, 1.562762, 2.000318, 2.876214",\ + "1.385751, 1.643102, 1.897333, 2.334891, 3.210791",\ + "1.182236, 1.465820, 1.709960, 2.145230, 3.017476",\ + "1.194460, 1.478043, 1.722182, 2.157442, 3.029672",\ + "1.214364, 1.497947, 1.742082, 2.177332, 3.049538",\ + "1.386614, 1.670198, 1.914322, 2.349535, 3.221670",\ + "1.721184, 2.004768, 2.248892, 2.684108, 3.556247"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.077163, 0.077163, 0.077138, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082398, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102308, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077163, 0.077163, 0.077137, 0.077052, 0.076882",\ + "0.082420, 0.082420, 0.082397, 0.082320, 0.082166",\ + "0.102329, 0.102329, 0.102307, 0.102236, 0.102091",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2663*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.646825, 0.888812, 1.155481, 1.637557, 2.601710",\ + "0.660538, 0.902524, 1.169192, 1.651265, 2.615411",\ + "0.684064, 0.926050, 1.192718, 1.674791, 2.638938",\ + "0.952246, 1.194231, 1.460892, 1.942948, 2.907060",\ + "1.545707, 1.787690, 2.054341, 2.536369, 3.500427",\ + "0.734227, 0.976289, 1.243085, 1.724270, 2.687644",\ + "0.747939, 0.990001, 1.256796, 1.737978, 2.701345",\ + "0.771465, 1.013527, 1.280322, 1.761504, 2.724872",\ + "1.039647, 1.281708, 1.548496, 2.029661, 2.992994",\ + "1.633109, 1.875167, 2.141944, 2.623083, 3.586361",\ + "0.815033, 1.065071, 1.331047, 1.811891, 2.774599",\ + "0.828746, 1.078784, 1.344759, 1.825599, 2.788300",\ + "0.852272, 1.102309, 1.368284, 1.849125, 2.811827",\ + "1.120454, 1.370490, 1.636458, 2.117281, 3.079949",\ + "1.713915, 1.963950, 2.229907, 2.710703, 3.673316",\ + "0.875218, 1.130416, 1.395189, 1.875803, 2.838108",\ + "0.888931, 1.144128, 1.408900, 1.889511, 2.851809",\ + "0.912457, 1.167654, 1.432426, 1.913038, 2.875336",\ + "1.180639, 1.435834, 1.700600, 2.181194, 3.143458",\ + "1.774100, 2.029294, 2.294049, 2.774616, 3.736825",\ + "1.213104, 1.491515, 1.747184, 2.225196, 3.183564",\ + "1.226817, 1.505228, 1.760895, 2.238904, 3.197265",\ + "1.250343, 1.528753, 1.784421, 2.262430, 3.220792",\ + "1.518525, 1.796934, 2.052595, 2.530586, 3.488914",\ + "2.111986, 2.390392, 2.646044, 3.124008, 4.082281"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126065, 0.126046, 0.126010",\ + "0.155268, 0.155268, 0.155265, 0.155253, 0.155228",\ + "0.201999, 0.201999, 0.201998, 0.201993, 0.201983",\ + "0.823664, 0.823664, 0.823664, 0.823662, 0.823659",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.585231, 0.827223, 1.093925, 1.576086, 2.540408",\ + "0.597454, 0.839445, 1.106138, 1.588275, 2.552550",\ + "0.617358, 0.859347, 1.126027, 1.608132, 2.572344",\ + "0.789607, 1.031589, 1.298230, 1.780235, 2.744245",\ + "1.124177, 1.366160, 1.632803, 2.114814, 3.078838",\ + "0.672632, 0.914701, 1.181530, 1.662799, 2.626341",\ + "0.684856, 0.926922, 1.193742, 1.674988, 2.638484",\ + "0.704759, 0.946824, 1.213631, 1.694846, 2.658278",\ + "0.877009, 1.119066, 1.385834, 1.866948, 2.830179",\ + "1.211579, 1.453637, 1.720407, 2.201528, 3.164772",\ + "0.753439, 1.003483, 1.269492, 1.750420, 2.713296",\ + "0.765663, 1.015705, 1.281705, 1.762609, 2.725439",\ + "0.785566, 1.035606, 1.301594, 1.782466, 2.745233",\ + "0.957816, 1.207848, 1.473796, 1.954568, 2.917134",\ + "1.292386, 1.542419, 1.808370, 2.289148, 3.251727",\ + "0.813624, 1.068828, 1.333634, 1.814332, 2.776805",\ + "0.825847, 1.081049, 1.345847, 1.826521, 2.788948",\ + "0.845751, 1.100950, 1.365736, 1.846379, 2.808742",\ + "1.018000, 1.273192, 1.537938, 2.018481, 2.980643",\ + "1.352571, 1.607763, 1.872511, 2.353061, 3.315236",\ + "1.151510, 1.429929, 1.685630, 2.163725, 3.122262",\ + "1.163733, 1.442150, 1.697842, 2.175914, 3.134404",\ + "1.183637, 1.462051, 1.717731, 2.195772, 3.154198",\ + "1.355886, 1.634290, 1.889933, 2.367873, 3.326099",\ + "1.690457, 1.968861, 2.224506, 2.702453, 3.660692"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.077160, 0.077143, 0.077050, 0.076813, 0.076339",\ + "0.082418, 0.082403, 0.082319, 0.082104, 0.081674",\ + "0.102327, 0.102313, 0.102234, 0.102033, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\ + "0.077160, 0.077143, 0.077050, 0.076813, 0.076339",\ + "0.082418, 0.082403, 0.082318, 0.082104, 0.081674",\ + "0.102327, 0.102313, 0.102234, 0.102033, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\ + "0.077160, 0.077143, 0.077050, 0.076813, 0.076339",\ + "0.082418, 0.082402, 0.082318, 0.082104, 0.081674",\ + "0.102327, 0.102313, 0.102234, 0.102033, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\ + "0.077160, 0.077142, 0.077050, 0.076813, 0.076339",\ + "0.082418, 0.082402, 0.082318, 0.082104, 0.081674",\ + "0.102327, 0.102312, 0.102234, 0.102033, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129",\ + "0.077160, 0.077137, 0.077047, 0.076812, 0.076339",\ + "0.082418, 0.082397, 0.082316, 0.082103, 0.081674",\ + "0.102327, 0.102307, 0.102232, 0.102032, 0.101631",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380732",\ + "1.026132, 1.026132, 1.026131, 1.026130, 1.026129"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2738*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.837009, 1.103664, 1.394023, 1.889858, 2.881526",\ + "0.850722, 1.117377, 1.407736, 1.903570, 2.895239",\ + "0.874247, 1.140903, 1.431262, 1.927096, 2.918765",\ + "1.142429, 1.409085, 1.699444, 2.195278, 3.186947",\ + "1.735891, 2.002547, 2.292906, 2.788740, 3.780409",\ + "0.924420, 1.191252, 1.481675, 1.976572, 2.967460",\ + "0.938133, 1.204965, 1.495388, 1.990285, 2.981173",\ + "0.961659, 1.228491, 1.518914, 2.013811, 3.004699",\ + "1.229841, 1.496673, 1.787096, 2.281993, 3.272881",\ + "1.823303, 2.090135, 2.380557, 2.875455, 3.866343",\ + "1.005339, 1.280324, 1.569641, 2.064194, 3.054415",\ + "1.019052, 1.294036, 1.583354, 2.077907, 3.068128",\ + "1.042578, 1.317562, 1.606879, 2.101433, 3.091654",\ + "1.310760, 1.585744, 1.875061, 2.369615, 3.359836",\ + "1.904221, 2.179206, 2.468523, 2.963077, 3.953298",\ + "1.066406, 1.346091, 1.633785, 2.128108, 3.117924",\ + "1.080119, 1.359803, 1.647498, 2.141821, 3.131637",\ + "1.103644, 1.383329, 1.671023, 2.165346, 3.155163",\ + "1.371826, 1.651511, 1.939205, 2.433528, 3.423345",\ + "1.965288, 2.244973, 2.532667, 3.026990, 4.016807",\ + "1.402561, 1.712010, 1.985925, 2.477567, 3.463380",\ + "1.416273, 1.725723, 1.999638, 2.491279, 3.477093",\ + "1.439799, 1.749248, 2.023164, 2.514805, 3.500619",\ + "1.707981, 2.017431, 2.291346, 2.782987, 3.768801",\ + "2.301443, 2.610892, 2.884808, 3.376449, 4.362263"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.775414, 1.042069, 1.332428, 1.828263, 2.819932",\ + "0.787637, 1.054293, 1.344652, 1.840486, 2.832155",\ + "0.807541, 1.074197, 1.364556, 1.860390, 2.852059",\ + "0.979792, 1.246447, 1.536806, 2.032640, 3.024309",\ + "1.314362, 1.581017, 1.871376, 2.367211, 3.358880",\ + "0.862825, 1.129657, 1.420080, 1.914977, 2.905865",\ + "0.875049, 1.141881, 1.432303, 1.927201, 2.918089",\ + "0.894953, 1.161785, 1.452208, 1.947105, 2.937993",\ + "1.067203, 1.334035, 1.624458, 2.119355, 3.110243",\ + "1.401773, 1.668605, 1.959028, 2.453925, 3.444813",\ + "0.943744, 1.218729, 1.508046, 2.002599, 2.992820",\ + "0.955968, 1.230952, 1.520269, 2.014823, 3.005044",\ + "0.975872, 1.250856, 1.540173, 2.034727, 3.024948",\ + "1.148122, 1.423107, 1.712424, 2.206977, 3.197198",\ + "1.482692, 1.757677, 2.046994, 2.541547, 3.531768",\ + "1.004811, 1.284495, 1.572190, 2.066513, 3.056329",\ + "1.017034, 1.296719, 1.584413, 2.078736, 3.068553",\ + "1.036938, 1.316623, 1.604317, 2.098640, 3.088457",\ + "1.209189, 1.488873, 1.776568, 2.270891, 3.260707",\ + "1.543759, 1.823443, 2.111138, 2.605461, 3.595277",\ + "1.340966, 1.650415, 1.924330, 2.415972, 3.401785",\ + "1.353189, 1.662638, 1.936553, 2.428195, 3.414009",\ + "1.373093, 1.682542, 1.956458, 2.448099, 3.433913",\ + "1.545344, 1.854793, 2.128708, 2.620349, 3.606163",\ + "1.879914, 2.189363, 2.463278, 2.954920, 3.940733"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2382*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.820636, 1.072596, 1.352895, 1.817949, 2.748057",\ + "0.834349, 1.086309, 1.366608, 1.831662, 2.761770",\ + "0.857874, 1.109835, 1.390133, 1.855188, 2.785295",\ + "1.126056, 1.378017, 1.658316, 2.123370, 3.053478",\ + "1.719518, 1.971479, 2.251777, 2.716831, 3.646940",\ + "0.908045, 1.160181, 1.440449, 1.904663, 2.833991",\ + "0.921758, 1.173894, 1.454162, 1.918376, 2.847703",\ + "0.945284, 1.197419, 1.477687, 1.941902, 2.871229",\ + "1.213466, 1.465601, 1.745869, 2.210084, 3.139411",\ + "1.806928, 2.059063, 2.339331, 2.803546, 3.732873",\ + "0.988950, 1.249236, 1.528412, 1.992285, 2.920946",\ + "1.002662, 1.262948, 1.542125, 2.005998, 2.934659",\ + "1.026188, 1.286474, 1.565651, 2.029524, 2.958184",\ + "1.294370, 1.554656, 1.833833, 2.297706, 3.226367",\ + "1.887832, 2.148118, 2.427295, 2.891167, 3.819828",\ + "1.046704, 1.314977, 1.592551, 2.056198, 2.984455",\ + "1.060416, 1.328690, 1.606264, 2.069911, 2.998168",\ + "1.083942, 1.352216, 1.629790, 2.093437, 3.021693",\ + "1.352124, 1.620398, 1.897972, 2.361619, 3.289876",\ + "1.945586, 2.213860, 2.491434, 2.955081, 3.883337",\ + "1.375818, 1.680630, 1.944378, 2.405528, 3.329911",\ + "1.389531, 1.694343, 1.958091, 2.419240, 3.343624",\ + "1.413056, 1.717869, 1.981617, 2.442766, 3.367149",\ + "1.681239, 1.986051, 2.249799, 2.710948, 3.635332",\ + "2.274700, 2.579513, 2.843261, 3.304410, 4.228793"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126073, 0.126073, 0.126073, 0.126073, 0.126073",\ + "0.155270, 0.155270, 0.155270, 0.155270, 0.155270",\ + "0.202000, 0.202000, 0.202000, 0.202000, 0.202000",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.759041, 1.011001, 1.291300, 1.756354, 2.686462",\ + "0.771264, 1.023225, 1.303523, 1.768578, 2.698686",\ + "0.791168, 1.043129, 1.323427, 1.788481, 2.718590",\ + "0.963419, 1.215379, 1.495678, 1.960732, 2.890840",\ + "1.297989, 1.549949, 1.830248, 2.295302, 3.225410",\ + "0.846450, 1.098586, 1.378854, 1.843068, 2.772396",\ + "0.858674, 1.110809, 1.391077, 1.855292, 2.784619",\ + "0.878578, 1.130713, 1.410981, 1.875196, 2.804523",\ + "1.050828, 1.302964, 1.583232, 2.047446, 2.976774",\ + "1.385398, 1.637534, 1.917802, 2.382016, 3.311344",\ + "0.927355, 1.187640, 1.466817, 1.930690, 2.859351",\ + "0.939578, 1.199864, 1.479041, 1.942914, 2.871574",\ + "0.959482, 1.219768, 1.498945, 1.962818, 2.891478",\ + "1.131733, 1.392018, 1.671195, 2.135068, 3.063729",\ + "1.466303, 1.726588, 2.005765, 2.469638, 3.398299",\ + "0.985108, 1.253382, 1.530956, 1.994603, 2.922860",\ + "0.997332, 1.265606, 1.543180, 2.006827, 2.935083",\ + "1.017236, 1.285510, 1.563084, 2.026731, 2.954987",\ + "1.189487, 1.457760, 1.735334, 2.198981, 3.127238",\ + "1.524057, 1.792330, 2.069904, 2.533551, 3.461808",\ + "1.314223, 1.619035, 1.882783, 2.343933, 3.268316",\ + "1.326446, 1.631259, 1.895007, 2.356156, 3.280540",\ + "1.346350, 1.651163, 1.914911, 2.376060, 3.300443",\ + "1.518601, 1.823413, 2.087161, 2.548311, 3.472694",\ + "1.853171, 2.157983, 2.421731, 2.882881, 3.807264"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132",\ + "0.077162, 0.077162, 0.077162, 0.077162, 0.077162",\ + "0.082420, 0.082420, 0.082420, 0.082420, 0.082420",\ + "0.102329, 0.102329, 0.102329, 0.102329, 0.102329",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026132"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2443*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.834699, 1.095622, 1.384637, 1.885838, 2.888237",\ + "0.848411, 1.109334, 1.398350, 1.899550, 2.901949",\ + "0.871937, 1.132860, 1.421876, 1.923076, 2.925475",\ + "1.140119, 1.401042, 1.690057, 2.191256, 3.193652",\ + "1.733580, 1.994503, 2.283517, 2.784714, 3.787106",\ + "0.922107, 1.183198, 1.472305, 1.972552, 2.974171",\ + "0.935819, 1.196910, 1.486017, 1.986264, 2.987883",\ + "0.959345, 1.220436, 1.509543, 2.009790, 3.011409",\ + "1.227527, 1.488618, 1.777724, 2.277970, 3.279586",\ + "1.820988, 2.082079, 2.371185, 2.871428, 3.873040",\ + "1.002997, 1.272227, 1.560270, 2.060173, 3.061126",\ + "1.016710, 1.285939, 1.573983, 2.073886, 3.074838",\ + "1.040236, 1.309465, 1.597508, 2.097411, 3.098364",\ + "1.308417, 1.577647, 1.865690, 2.365591, 3.366541",\ + "1.901878, 2.171108, 2.459150, 2.959049, 3.959995",\ + "1.063922, 1.337931, 1.624415, 2.124086, 3.124635",\ + "1.077635, 1.351643, 1.638128, 2.137799, 3.138347",\ + "1.101161, 1.375169, 1.661654, 2.161325, 3.161873",\ + "1.369342, 1.643351, 1.929835, 2.429504, 3.430050",\ + "1.962803, 2.236812, 2.523295, 3.022963, 4.023504",\ + "1.400271, 1.703161, 1.976608, 2.473565, 3.470091",\ + "1.413984, 1.716874, 1.990321, 2.487277, 3.483803",\ + "1.437509, 1.740399, 2.013846, 2.510803, 3.507329",\ + "1.705691, 2.008581, 2.282028, 2.778982, 3.775506",\ + "2.299152, 2.602042, 2.875488, 3.372441, 4.368960"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201998",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.773106, 1.034029, 1.323047, 1.824254, 2.826667",\ + "0.785329, 1.046252, 1.335269, 1.836474, 2.838884",\ + "0.805232, 1.066155, 1.355171, 1.856374, 2.858778",\ + "0.977479, 1.238403, 1.527417, 2.028611, 3.031000",\ + "1.312050, 1.572973, 1.861987, 2.363182, 3.365571",\ + "0.860514, 1.121605, 1.410714, 1.910968, 2.912601",\ + "0.872737, 1.133828, 1.422936, 1.923188, 2.924818",\ + "0.892640, 1.153731, 1.442839, 1.943088, 2.944712",\ + "1.064888, 1.325979, 1.615084, 2.115325, 3.116933",\ + "1.399458, 1.660549, 1.949654, 2.449896, 3.451505",\ + "0.941405, 1.210634, 1.498679, 1.998589, 2.999556",\ + "0.953628, 1.222857, 1.510902, 2.010810, 3.011773",\ + "0.973531, 1.242760, 1.530804, 2.030710, 3.031667",\ + "1.145778, 1.415007, 1.703049, 2.202947, 3.203888",\ + "1.480349, 1.749578, 2.037620, 2.537518, 3.538460",\ + "1.002329, 1.276338, 1.562824, 2.062502, 3.063065",\ + "1.014552, 1.288561, 1.575047, 2.074723, 3.075282",\ + "1.034455, 1.308464, 1.594949, 2.094623, 3.095176",\ + "1.206703, 1.480712, 1.767194, 2.266860, 3.267397",\ + "1.541273, 1.815282, 2.101765, 2.601431, 3.601969",\ + "1.338678, 1.641568, 1.915017, 2.411981, 3.408521",\ + "1.350901, 1.653791, 1.927240, 2.424201, 3.420738",\ + "1.370804, 1.673694, 1.947142, 2.444101, 3.440632",\ + "1.543052, 1.845942, 2.119387, 2.616338, 3.612854",\ + "1.877622, 2.180512, 2.453958, 2.950909, 3.947425"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077150, 0.077131, 0.077093",\ + "0.082414, 0.082414, 0.082409, 0.082392, 0.082357",\ + "0.102324, 0.102324, 0.102319, 0.102303, 0.102270",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2590*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.813664, 1.067787, 1.348972, 1.815159, 2.747532",\ + "0.827376, 1.081499, 1.362685, 1.828871, 2.761244",\ + "0.850902, 1.105025, 1.386211, 1.852397, 2.784770",\ + "1.119084, 1.373207, 1.654392, 2.120577, 3.052948",\ + "1.712545, 1.966668, 2.247853, 2.714036, 3.646404",\ + "0.901073, 1.155375, 1.436530, 1.901873, 2.833466",\ + "0.914786, 1.169088, 1.450242, 1.915586, 2.847178",\ + "0.938311, 1.192614, 1.473768, 1.939111, 2.870703",\ + "1.206493, 1.460795, 1.741949, 2.207292, 3.138882",\ + "1.799954, 2.054256, 2.335410, 2.800751, 3.732338",\ + "0.981887, 1.244438, 1.524493, 1.989495, 2.920421",\ + "0.995600, 1.258151, 1.538206, 2.003207, 2.934133",\ + "1.019126, 1.281676, 1.561732, 2.026733, 2.957659",\ + "1.287307, 1.549858, 1.829913, 2.294913, 3.225837",\ + "1.880768, 2.143319, 2.423373, 2.888372, 3.819293",\ + "1.039467, 1.310192, 1.588632, 2.053408, 2.983930",\ + "1.053180, 1.323904, 1.602345, 2.067121, 2.997642",\ + "1.076705, 1.347430, 1.625871, 2.090646, 3.021168",\ + "1.344887, 1.615612, 1.894052, 2.358827, 3.289346",\ + "1.938348, 2.209073, 2.487513, 2.952286, 3.882802",\ + "1.371275, 1.675984, 1.940471, 2.402742, 3.329386",\ + "1.384988, 1.689697, 1.954183, 2.416455, 3.343098",\ + "1.408514, 1.713222, 1.977709, 2.439981, 3.366623",\ + "1.676695, 1.981404, 2.245890, 2.708161, 3.634802",\ + "2.270156, 2.574865, 2.839351, 3.301620, 4.228258"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140",\ + "0.126070, 0.126070, 0.126070, 0.126069, 0.126068",\ + "0.155268, 0.155268, 0.155268, 0.155268, 0.155267",\ + "0.201999, 0.201999, 0.201999, 0.201999, 0.201999",\ + "0.823664, 0.823664, 0.823664, 0.823664, 0.823664",\ + "2.222140, 2.222140, 2.222140, 2.222140, 2.222140"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.752071, 1.006194, 1.287381, 1.753572, 2.685955",\ + "0.764294, 1.018417, 1.299603, 1.765793, 2.698174",\ + "0.784197, 1.038320, 1.319506, 1.785694, 2.718071",\ + "0.956445, 1.210568, 1.491752, 1.957934, 2.890299",\ + "1.291015, 1.545138, 1.826322, 2.292505, 3.224871",\ + "0.839480, 1.093783, 1.374938, 1.840287, 2.771889",\ + "0.851703, 1.106005, 1.387161, 1.852508, 2.784107",\ + "0.871606, 1.125909, 1.407063, 1.872409, 2.804004",\ + "1.043854, 1.298156, 1.579309, 2.044649, 2.976233",\ + "1.378424, 1.632726, 1.913880, 2.379220, 3.310805",\ + "0.920294, 1.182845, 1.462902, 1.927908, 2.858844",\ + "0.932517, 1.195068, 1.475124, 1.940130, 2.871062",\ + "0.952420, 1.214971, 1.495027, 1.960030, 2.890960",\ + "1.124668, 1.387219, 1.667273, 2.132271, 3.063188",\ + "1.459238, 1.721789, 2.001843, 2.466841, 3.397760",\ + "0.977874, 1.248599, 1.527041, 1.991822, 2.922353",\ + "0.990097, 1.260822, 1.539264, 2.004043, 2.934571",\ + "1.010000, 1.280725, 1.559166, 2.023944, 2.954468",\ + "1.182248, 1.452972, 1.731412, 2.196184, 3.126697",\ + "1.516818, 1.787543, 2.065982, 2.530755, 3.461269",\ + "1.309683, 1.614391, 1.878880, 2.341156, 3.267809",\ + "1.321906, 1.626614, 1.891102, 2.353377, 3.280027",\ + "1.341809, 1.646517, 1.911005, 2.373278, 3.299924",\ + "1.514056, 1.818765, 2.083251, 2.545518, 3.472153",\ + "1.848626, 2.153335, 2.417821, 2.880089, 3.806725"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077152, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131",\ + "0.077156, 0.077156, 0.077151, 0.077138, 0.077112",\ + "0.082414, 0.082414, 0.082410, 0.082398, 0.082374",\ + "0.102323, 0.102323, 0.102320, 0.102309, 0.102286",\ + "0.380733, 0.380733, 0.380733, 0.380733, 0.380733",\ + "1.026132, 1.026132, 1.026132, 1.026132, 1.026131"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2633*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.689280, 0.957537, 1.249948, 1.745707, 2.737226",\ + "0.703254, 0.971515, 1.263950, 1.759776, 2.751428",\ + "0.726748, 0.995009, 1.287441, 1.783259, 2.774894",\ + "0.996345, 1.264632, 1.557197, 2.053374, 3.045727",\ + "1.591995, 1.860324, 2.153094, 2.649826, 3.643289",\ + "0.776693, 1.045135, 1.337600, 1.832422, 2.823160",\ + "0.790666, 1.059113, 1.351603, 1.846491, 2.837361",\ + "0.814160, 1.082607, 1.375093, 1.869974, 2.860828",\ + "1.083757, 1.352230, 1.644851, 2.140089, 3.131661",\ + "1.679408, 1.947922, 2.240750, 2.736541, 3.729223",\ + "0.857617, 1.134236, 1.425566, 1.920044, 2.910115",\ + "0.871591, 1.148215, 1.439569, 1.934113, 2.924316",\ + "0.895085, 1.171708, 1.463060, 1.957596, 2.947783",\ + "1.164682, 1.441333, 1.732817, 2.227711, 3.218616",\ + "1.760333, 2.037025, 2.328716, 2.824163, 3.816178",\ + "0.918265, 1.200047, 1.489710, 1.983958, 2.973624",\ + "0.932239, 1.214026, 1.503713, 1.998027, 2.987825",\ + "0.955733, 1.237519, 1.527204, 2.021510, 3.011292",\ + "1.225332, 1.507144, 1.796961, 2.291625, 3.282125",\ + "1.820984, 2.102838, 2.392860, 2.888076, 3.879687",\ + "1.253788, 1.566464, 1.841850, 2.333418, 3.319080",\ + "1.267763, 1.580444, 1.855854, 2.347487, 3.333282",\ + "1.291257, 1.603937, 1.879344, 2.370970, 3.356748",\ + "1.560858, 1.873569, 2.149106, 2.641086, 3.627581",\ + "2.156515, 2.469274, 2.745010, 3.237540, 4.225142"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.130558, 0.130764, 0.132053, 0.135744, 0.143126",\ + "0.158251, 0.158388, 0.159397, 0.162380, 0.168346",\ + "0.203206, 0.203261, 0.203904, 0.205928, 0.209976",\ + "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\ + "0.130558, 0.130766, 0.132065, 0.135744, 0.143126",\ + "0.158251, 0.158389, 0.159406, 0.162380, 0.168346",\ + "0.203206, 0.203262, 0.203910, 0.205928, 0.209976",\ + "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\ + "0.130559, 0.130769, 0.132065, 0.135744, 0.143126",\ + "0.158251, 0.158391, 0.159406, 0.162380, 0.168346",\ + "0.203206, 0.203262, 0.203910, 0.205928, 0.209976",\ + "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\ + "0.130568, 0.130774, 0.132066, 0.135744, 0.143126",\ + "0.158257, 0.158394, 0.159407, 0.162380, 0.168346",\ + "0.203208, 0.203264, 0.203911, 0.205928, 0.209976",\ + "0.823780, 0.823782, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146",\ + "0.130591, 0.130830, 0.132103, 0.135759, 0.143126",\ + "0.158273, 0.158432, 0.159437, 0.162392, 0.168346",\ + "0.203215, 0.203279, 0.203931, 0.205936, 0.209976",\ + "0.823780, 0.823783, 0.823793, 0.823822, 0.823881",\ + "2.222146, 2.222146, 2.222146, 2.222146, 2.222146"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.620877, 0.889007, 1.180779, 1.674812, 2.662879",\ + "0.634992, 0.903157, 1.195106, 1.689619, 2.678645",\ + "0.657454, 0.925667, 1.217856, 1.713018, 2.703341",\ + "0.837827, 1.106191, 1.399143, 1.896364, 2.890807",\ + "1.171871, 1.440226, 1.733128, 2.230216, 3.224392",\ + "0.708289, 0.976604, 1.268425, 1.761527, 2.748812",\ + "0.722404, 0.990754, 1.282755, 1.776334, 2.764579",\ + "0.744867, 1.013264, 1.305507, 1.799733, 2.789275",\ + "0.925240, 1.193790, 1.486800, 1.983079, 2.976740",\ + "1.259284, 1.527824, 1.820785, 2.316931, 3.310326",\ + "0.789214, 1.065703, 1.356391, 1.849149, 2.835768",\ + "0.803329, 1.079854, 1.370721, 1.863956, 2.851534",\ + "0.825791, 1.102365, 1.393473, 1.887355, 2.876230",\ + "1.006165, 1.282894, 1.574766, 2.070702, 3.063695",\ + "1.340209, 1.616928, 1.908751, 2.404553, 3.397281",\ + "0.849857, 1.131511, 1.420535, 1.913063, 2.899276",\ + "0.863973, 1.145663, 1.434865, 1.927870, 2.915043",\ + "0.886438, 1.168175, 1.457617, 1.951269, 2.939739",\ + "1.066817, 1.348707, 1.638911, 2.134615, 3.127204",\ + "1.400861, 1.682741, 1.972895, 2.468467, 3.460790",\ + "1.185366, 1.497892, 1.772658, 2.262515, 3.244732",\ + "1.199486, 1.512054, 1.786992, 2.277325, 3.260499",\ + "1.221956, 1.534580, 1.809751, 2.300726, 3.285195",\ + "1.402352, 1.715153, 1.991066, 2.484081, 3.472661",\ + "1.736395, 2.049184, 2.325049, 2.817932, 3.806246"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.096307, 0.096664, 0.098460, 0.103314, 0.113023",\ + "0.099768, 0.100091, 0.101719, 0.106118, 0.114915",\ + "0.118566, 0.118869, 0.120392, 0.124509, 0.132743",\ + "0.380772, 0.380786, 0.381010, 0.381719, 0.383137",\ + "1.026329, 1.026338, 1.026379, 1.026486, 1.026699",\ + "0.096307, 0.096666, 0.098476, 0.103314, 0.113023",\ + "0.099768, 0.100093, 0.101733, 0.106118, 0.114915",\ + "0.118566, 0.118871, 0.120405, 0.124509, 0.132743",\ + "0.380772, 0.380786, 0.381012, 0.381719, 0.383137",\ + "1.026329, 1.026338, 1.026379, 1.026486, 1.026699",\ + "0.096307, 0.096672, 0.098476, 0.103314, 0.113023",\ + "0.099768, 0.100099, 0.101733, 0.106118, 0.114915",\ + "0.118566, 0.118876, 0.120406, 0.124509, 0.132743",\ + "0.380772, 0.380786, 0.381012, 0.381719, 0.383137",\ + "1.026329, 1.026339, 1.026379, 1.026486, 1.026699",\ + "0.096322, 0.096680, 0.098477, 0.103314, 0.113023",\ + "0.099782, 0.100106, 0.101734, 0.106118, 0.114915",\ + "0.118579, 0.118883, 0.120406, 0.124509, 0.132743",\ + "0.380772, 0.380787, 0.381012, 0.381719, 0.383137",\ + "1.026330, 1.026339, 1.026379, 1.026486, 1.026699",\ + "0.096361, 0.096780, 0.098526, 0.103335, 0.113023",\ + "0.099817, 0.100196, 0.101779, 0.106136, 0.114915",\ + "0.118612, 0.118967, 0.120448, 0.124526, 0.132743",\ + "0.380772, 0.380792, 0.381019, 0.381722, 0.383137",\ + "1.026331, 1.026341, 1.026381, 1.026486, 1.026699"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2683*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.195231, 0.463005, 0.734474, 1.195010, 2.116083",\ + "0.209369, 0.477311, 0.748785, 1.209873, 2.132048",\ + "0.233103, 0.501280, 0.772498, 1.233725, 2.156177",\ + "0.505445, 0.772942, 1.041862, 1.499718, 2.415430",\ + "1.101330, 1.368410, 1.636340, 2.092443, 3.004649",\ + "0.282639, 0.550544, 0.822013, 1.281725, 2.202017",\ + "0.296777, 0.564849, 0.836326, 1.296587, 2.217982",\ + "0.320749, 0.588817, 0.860040, 1.320439, 2.242111",\ + "0.593808, 0.860470, 1.129393, 1.586432, 2.501364",\ + "1.189691, 1.455935, 1.723865, 2.179157, 3.090583",\ + "0.371453, 0.639490, 0.909976, 1.369346, 2.288972",\ + "0.385884, 0.653793, 0.924289, 1.384209, 2.304937",\ + "0.410095, 0.677755, 0.948003, 1.408060, 2.329066",\ + "0.683117, 0.949390, 1.217355, 1.674054, 2.588319",\ + "1.278993, 1.544848, 1.811828, 2.266779, 3.177538",\ + "0.435127, 0.705073, 0.974115, 1.433259, 2.352481",\ + "0.449557, 0.719372, 0.988428, 1.448122, 2.368446",\ + "0.473764, 0.743329, 1.012141, 1.471974, 2.392575",\ + "0.746751, 1.014935, 1.281493, 1.737967, 2.651828",\ + "1.342621, 1.610383, 1.875965, 2.330692, 3.241047",\ + "0.771711, 1.068883, 1.325895, 1.782569, 2.697937",\ + "0.786132, 1.083144, 1.340213, 1.797434, 2.713902",\ + "0.810321, 1.107028, 1.363928, 1.821286, 2.738031",\ + "1.083085, 1.378307, 1.633246, 2.087266, 2.997284",\ + "1.678917, 1.973635, 2.227701, 2.679984, 3.586503"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.185659, 0.236480, 0.332306, 0.503768, 0.846690",\ + "0.203762, 0.251201, 0.346416, 0.519962, 0.867054",\ + "0.237818, 0.275998, 0.366817, 0.542132, 0.892761",\ + "0.823305, 0.824108, 0.854501, 0.958291, 1.165871",\ + "2.222180, 2.222247, 2.228687, 2.250859, 2.295203",\ + "0.185659, 0.236778, 0.332846, 0.503768, 0.846690",\ + "0.203762, 0.251491, 0.346963, 0.519962, 0.867054",\ + "0.238090, 0.276257, 0.367369, 0.542132, 0.892761",\ + "0.823322, 0.824110, 0.854828, 0.958291, 1.165871",\ + "2.222181, 2.222247, 2.228756, 2.250859, 2.295203",\ + "0.187582, 0.237448, 0.332856, 0.503768, 0.846690",\ + "0.205428, 0.252143, 0.346973, 0.519962, 0.867054",\ + "0.238891, 0.276838, 0.367379, 0.542132, 0.892761",\ + "0.823369, 0.824113, 0.854835, 0.958291, 1.165871",\ + "2.222186, 2.222247, 2.228758, 2.250859, 2.295203",\ + "0.188921, 0.238422, 0.332885, 0.503768, 0.846690",\ + "0.206588, 0.253091, 0.347002, 0.519962, 0.867054",\ + "0.239638, 0.277682, 0.367409, 0.542132, 0.892761",\ + "0.823414, 0.824119, 0.854852, 0.958291, 1.165871",\ + "2.222191, 2.222247, 2.228761, 2.250859, 2.295203",\ + "0.197449, 0.249827, 0.334624, 0.504477, 0.846690",\ + "0.213977, 0.264195, 0.348763, 0.520680, 0.867054",\ + "0.244398, 0.287568, 0.369187, 0.542857, 0.892761",\ + "0.823697, 0.824180, 0.855905, 0.958721, 1.165871",\ + "2.222221, 2.222247, 2.228986, 2.250950, 2.295203"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.199835, 0.394068, 0.663502, 1.119151, 2.030450",\ + "0.208748, 0.404375, 0.677456, 1.139816, 2.064535",\ + "0.223610, 0.421071, 0.699454, 1.171923, 2.116862",\ + "0.380613, 0.582386, 0.880612, 1.405667, 2.455778",\ + "0.716679, 0.922290, 1.228480, 1.784735, 2.897244",\ + "0.287243, 0.481603, 0.751025, 1.205865, 2.116384",\ + "0.296156, 0.491921, 0.765001, 1.226530, 2.150469",\ + "0.311018, 0.508632, 0.787030, 1.258637, 2.202796",\ + "0.468021, 0.669977, 0.968355, 1.492382, 2.541712",\ + "0.804087, 1.009874, 1.316321, 1.871449, 2.983178",\ + "0.368115, 0.570540, 0.838988, 1.293487, 2.203339",\ + "0.377029, 0.580882, 0.852964, 1.314152, 2.237424",\ + "0.391890, 0.597628, 0.874994, 1.346259, 2.289751",\ + "0.548893, 0.759039, 1.056321, 1.580003, 2.628667",\ + "0.884959, 1.098920, 1.404289, 1.959070, 3.070133",\ + "0.425818, 0.636109, 0.903125, 1.357400, 2.266848",\ + "0.434733, 0.646488, 0.917102, 1.378065, 2.300933",\ + "0.449593, 0.663284, 0.939134, 1.410172, 2.353260",\ + "0.606596, 0.824792, 1.120470, 1.643916, 2.692176",\ + "0.942662, 1.164649, 1.468444, 2.022984, 3.133642",\ + "0.728861, 0.999767, 1.254856, 1.706689, 2.612304",\ + "0.737784, 1.010567, 1.268901, 1.727382, 2.646389",\ + "0.752638, 1.027949, 1.291036, 1.759531, 2.698716",\ + "0.909639, 1.190589, 1.472905, 1.993493, 3.037632",\ + "1.245701, 1.530174, 1.821195, 2.372689, 3.479098"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.051713, 0.082206, 0.146667, 0.272496, 0.524154",\ + "0.059242, 0.084148, 0.146833, 0.273232, 0.526032",\ + "0.082676, 0.098099, 0.151707, 0.276480, 0.526025",\ + "0.382075, 0.382564, 0.407345, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042321, 1.092011, 1.191392",\ + "0.051713, 0.082387, 0.147063, 0.272496, 0.524154",\ + "0.059242, 0.084316, 0.147231, 0.273232, 0.526032",\ + "0.082676, 0.098212, 0.152100, 0.276480, 0.526025",\ + "0.382075, 0.382568, 0.407606, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042477, 1.092011, 1.191392",\ + "0.051782, 0.082793, 0.147071, 0.272496, 0.524154",\ + "0.059284, 0.084694, 0.147238, 0.273232, 0.526032",\ + "0.082697, 0.098465, 0.152108, 0.276480, 0.526025",\ + "0.382075, 0.382579, 0.407611, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042480, 1.092011, 1.191392",\ + "0.051916, 0.083384, 0.147092, 0.272496, 0.524154",\ + "0.059368, 0.085243, 0.147259, 0.273232, 0.526032",\ + "0.082738, 0.098832, 0.152128, 0.276480, 0.526025",\ + "0.382075, 0.382594, 0.407625, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042489, 1.092011, 1.191392",\ + "0.053133, 0.090301, 0.148368, 0.273016, 0.524154",\ + "0.060124, 0.091679, 0.148542, 0.273755, 0.526032",\ + "0.083110, 0.103136, 0.153394, 0.276996, 0.526025",\ + "0.382075, 0.382769, 0.408465, 0.490571, 0.655996",\ + "1.027888, 1.027888, 1.042993, 1.092217, 1.191392"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2504*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.107724, 0.368276, 0.625542, 1.061117, 1.932266",\ + "0.118290, 0.379979, 0.639987, 1.079831, 1.959519",\ + "0.141262, 0.402747, 0.664893, 1.109231, 1.997905",\ + "0.466405, 0.694370, 0.967258, 1.421195, 2.329069",\ + "1.080370, 1.299790, 1.592495, 2.085614, 3.071851",\ + "0.196001, 0.455768, 0.713003, 1.147831, 2.018200",\ + "0.206570, 0.467481, 0.727462, 1.166545, 2.045453",\ + "0.229522, 0.490254, 0.752382, 1.195945, 2.083839",\ + "0.553814, 0.781928, 1.054777, 1.507910, 2.415003",\ + "1.167779, 1.387403, 1.680137, 2.172328, 3.157785",\ + "0.284966, 0.544612, 0.800965, 1.235453, 2.105155",\ + "0.295543, 0.556347, 0.815424, 1.254167, 2.132408",\ + "0.318436, 0.579132, 0.840344, 1.283567, 2.170794",\ + "0.634637, 0.870922, 1.142740, 1.595531, 2.501958",\ + "1.248620, 1.476519, 1.768103, 2.259950, 3.244740",\ + "0.348239, 0.610047, 0.865099, 1.299366, 2.168664",\ + "0.358823, 0.621814, 0.879558, 1.318080, 2.195917",\ + "0.381662, 0.644617, 0.904480, 1.347480, 2.234303",\ + "0.692234, 0.936575, 1.206877, 1.659445, 2.565467",\ + "1.306252, 1.542352, 1.832246, 2.323863, 3.308249",\ + "0.682278, 0.972118, 1.216627, 1.648574, 2.514120",\ + "0.692910, 0.984256, 1.231130, 1.667306, 2.541373",\ + "0.715403, 1.007266, 1.256096, 1.696724, 2.579759",\ + "1.001252, 1.301193, 1.558591, 2.008728, 2.910923",\ + "1.608596, 1.909065, 2.184358, 2.673309, 3.653705"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.074735, 0.092677, 0.146088, 0.239899, 0.427522",\ + "0.102638, 0.120071, 0.176792, 0.284601, 0.500219",\ + "0.161882, 0.174744, 0.229174, 0.352169, 0.598157",\ + "0.823637, 0.823637, 0.866367, 1.013938, 1.309078",\ + "2.221941, 2.221941, 2.244685, 2.323231, 2.480325",\ + "0.074735, 0.092846, 0.146384, 0.239899, 0.427522",\ + "0.102638, 0.120235, 0.177132, 0.284601, 0.500219",\ + "0.161882, 0.174865, 0.229562, 0.352169, 0.598157",\ + "0.823637, 0.823637, 0.866833, 1.013938, 1.309078",\ + "2.221941, 2.221941, 2.244933, 2.323231, 2.480325",\ + "0.074735, 0.093227, 0.146389, 0.239899, 0.427522",\ + "0.102638, 0.120606, 0.177138, 0.284601, 0.500219",\ + "0.161882, 0.175138, 0.229569, 0.352169, 0.598157",\ + "0.823637, 0.823637, 0.866841, 1.013938, 1.309078",\ + "2.221941, 2.221941, 2.244937, 2.323231, 2.480325",\ + "0.074735, 0.093782, 0.146405, 0.239899, 0.427522",\ + "0.102638, 0.121144, 0.177156, 0.284601, 0.500219",\ + "0.161882, 0.175536, 0.229590, 0.352169, 0.598157",\ + "0.823637, 0.823637, 0.866866, 1.013938, 1.309078",\ + "2.221941, 2.221941, 2.244950, 2.323231, 2.480325",\ + "0.074735, 0.100272, 0.147356, 0.240288, 0.427522",\ + "0.102638, 0.127451, 0.178250, 0.285047, 0.500219",\ + "0.161882, 0.180189, 0.230838, 0.352678, 0.598157",\ + "0.823637, 0.823637, 0.868363, 1.014548, 1.309078",\ + "2.221941, 2.221941, 2.245747, 2.323557, 2.480325"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.140111, 0.321611, 0.507696, 0.851050, 1.569056",\ + "0.146136, 0.328572, 0.525511, 0.902870, 1.657587",\ + "0.156561, 0.339884, 0.570480, 0.970939, 1.771856",\ + "0.297184, 0.522021, 0.807737, 1.302651, 2.292479",\ + "0.634484, 0.861679, 1.151767, 1.684827, 2.750947",\ + "0.227520, 0.408999, 0.595163, 0.937764, 1.654990",\ + "0.233545, 0.415960, 0.612788, 0.989584, 1.743521",\ + "0.243970, 0.427273, 0.657830, 1.057653, 1.857790",\ + "0.384593, 0.609585, 0.895385, 1.389365, 2.378412",\ + "0.721893, 0.949200, 1.239535, 1.771541, 2.836881",\ + "0.308387, 0.489332, 0.675190, 1.025386, 1.741945",\ + "0.314418, 0.496293, 0.700747, 1.077206, 1.830476",\ + "0.324849, 0.509849, 0.745789, 1.145275, 1.944745",\ + "0.465472, 0.698592, 0.983351, 1.476987, 2.465368",\ + "0.802748, 1.038111, 1.327502, 1.859163, 2.923836",\ + "0.366068, 0.546880, 0.732732, 1.089299, 1.805454",\ + "0.372111, 0.553842, 0.764871, 1.141119, 1.893985",\ + "0.382553, 0.575066, 0.809918, 1.209188, 2.008254",\ + "0.523176, 0.764266, 1.047495, 1.540900, 2.528877",\ + "0.860406, 1.103644, 1.391653, 1.923076, 2.987345",\ + "0.668860, 0.879530, 1.082095, 1.438189, 2.150910",\ + "0.675009, 0.902838, 1.115808, 1.490086, 2.239441",\ + "0.685552, 0.934577, 1.161089, 1.558250, 2.353710",\ + "0.829810, 1.129123, 1.399624, 1.890354, 2.874332",\ + "1.174406, 1.466850, 1.744170, 2.272687, 3.332801"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.063168, 0.063168, 0.086358, 0.196253, 0.354186",\ + "0.068741, 0.068741, 0.139035, 0.228534, 0.407534",\ + "0.084603, 0.084603, 0.170977, 0.272661, 0.476028",\ + "0.381099, 0.384014, 0.432690, 0.586065, 0.892815",\ + "1.028844, 1.028844, 1.069535, 1.210064, 1.491123",\ + "0.063168, 0.063168, 0.086418, 0.196253, 0.354186",\ + "0.068741, 0.068741, 0.139317, 0.228534, 0.407534",\ + "0.084603, 0.084603, 0.171298, 0.272661, 0.476028",\ + "0.381099, 0.384041, 0.433173, 0.586065, 0.892815",\ + "1.028844, 1.028844, 1.069978, 1.210064, 1.491123",\ + "0.063168, 0.063168, 0.086418, 0.196253, 0.354186",\ + "0.068741, 0.068741, 0.139322, 0.228534, 0.407534",\ + "0.084603, 0.108427, 0.171304, 0.272661, 0.476028",\ + "0.381099, 0.384103, 0.433182, 0.586065, 0.892815",\ + "1.028844, 1.028844, 1.069987, 1.210064, 1.491123",\ + "0.063168, 0.063168, 0.086418, 0.196253, 0.354186",\ + "0.068741, 0.068741, 0.139337, 0.228534, 0.407534",\ + "0.084603, 0.109141, 0.171320, 0.272661, 0.476028",\ + "0.381099, 0.384193, 0.433208, 0.586065, 0.892815",\ + "1.028844, 1.028844, 1.070010, 1.210064, 1.491123",\ + "0.063168, 0.081229, 0.118354, 0.196580, 0.354186",\ + "0.068741, 0.094387, 0.140245, 0.228905, 0.407534",\ + "0.084603, 0.117503, 0.172352, 0.273082, 0.476028",\ + "0.381099, 0.385248, 0.434764, 0.586700, 0.892815",\ + "1.028844, 1.028844, 1.071436, 1.210646, 1.491123"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2464*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.666340, 0.928130, 1.212847, 1.689620, 2.643166",\ + "0.680315, 0.942109, 1.226845, 1.703665, 2.657306",\ + "0.703809, 0.965603, 1.250336, 1.727151, 2.680780",\ + "0.973410, 1.235228, 1.520067, 1.997139, 2.951283",\ + "1.569066, 1.830922, 2.115924, 2.593394, 3.548335",\ + "0.753746, 1.015729, 1.300436, 1.776334, 2.729100",\ + "0.767721, 1.029708, 1.314434, 1.790379, 2.743240",\ + "0.791215, 1.053202, 1.337926, 1.813865, 2.766714",\ + "1.060816, 1.322827, 1.607657, 2.083853, 3.037217",\ + "1.656472, 1.918522, 2.203516, 2.680108, 3.634269",\ + "0.834559, 1.104799, 1.388400, 1.863955, 2.816055",\ + "0.848533, 1.118778, 1.402398, 1.878000, 2.830195",\ + "0.872027, 1.142272, 1.425889, 1.901486, 2.853669",\ + "1.141628, 1.411898, 1.695621, 2.171474, 3.124172",\ + "1.737284, 2.007593, 2.291479, 2.767729, 3.721224",\ + "0.896255, 1.170562, 1.452541, 1.927868, 2.879564",\ + "0.910230, 1.184541, 1.466539, 1.941913, 2.893704",\ + "0.933724, 1.208035, 1.490030, 1.965399, 2.917178",\ + "1.203325, 1.477661, 1.759762, 2.235387, 3.187681",\ + "1.798983, 2.073358, 2.355620, 2.831642, 3.784733",\ + "1.233218, 1.536514, 1.804484, 2.277243, 3.225020",\ + "1.247192, 1.550495, 1.818483, 2.291289, 3.239160",\ + "1.270686, 1.573988, 1.841974, 2.314774, 3.262634",\ + "1.540289, 1.843622, 2.111709, 2.584763, 3.533137",\ + "2.135948, 2.439330, 2.707571, 3.181020, 4.130188"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.130524, 0.130598, 0.131270, 0.133249, 0.137207",\ + "0.158228, 0.158278, 0.158724, 0.160039, 0.162669",\ + "0.203197, 0.203217, 0.203397, 0.203929, 0.204993",\ + "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\ + "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\ + "0.130524, 0.130599, 0.131276, 0.133249, 0.137207",\ + "0.158228, 0.158278, 0.158728, 0.160039, 0.162669",\ + "0.203197, 0.203217, 0.203399, 0.203929, 0.204993",\ + "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\ + "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\ + "0.130525, 0.130600, 0.131276, 0.133249, 0.137207",\ + "0.158229, 0.158279, 0.158728, 0.160039, 0.162669",\ + "0.203197, 0.203217, 0.203399, 0.203929, 0.204993",\ + "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\ + "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\ + "0.130526, 0.130602, 0.131276, 0.133249, 0.137207",\ + "0.158229, 0.158280, 0.158728, 0.160039, 0.162669",\ + "0.203197, 0.203218, 0.203399, 0.203929, 0.204993",\ + "0.823780, 0.823782, 0.823791, 0.823812, 0.823854",\ + "2.222145, 2.222146, 2.222146, 2.222149, 2.222153",\ + "0.130530, 0.130626, 0.131296, 0.133257, 0.137207",\ + "0.158232, 0.158296, 0.158741, 0.160044, 0.162669",\ + "0.203198, 0.203224, 0.203404, 0.203931, 0.204993",\ + "0.823780, 0.823783, 0.823791, 0.823812, 0.823854",\ + "2.222146, 2.222146, 2.222146, 2.222149, 2.222153"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.597919, 0.859592, 1.143801, 1.619336, 2.570405",\ + "0.612039, 0.873744, 1.158095, 1.633973, 2.585731",\ + "0.634508, 0.896258, 1.180798, 1.657142, 2.609831",\ + "0.814903, 1.076792, 1.361938, 1.839759, 2.795403",\ + "1.148946, 1.410826, 1.695932, 2.173658, 3.129110",\ + "0.685326, 0.947190, 1.231387, 1.706050, 2.656339",\ + "0.699445, 0.961343, 1.245681, 1.720687, 2.671665",\ + "0.721914, 0.983856, 1.268386, 1.743856, 2.695765",\ + "0.902309, 1.164392, 1.449531, 1.926473, 2.881336",\ + "1.236352, 1.498426, 1.783525, 2.260372, 3.215044",\ + "0.766138, 1.036258, 1.319350, 1.793671, 2.743294",\ + "0.780258, 1.050411, 1.333645, 1.808309, 2.758620",\ + "0.802727, 1.072925, 1.356350, 1.831478, 2.782720",\ + "0.983121, 1.253464, 1.537494, 2.014095, 2.968292",\ + "1.317164, 1.587497, 1.871488, 2.347994, 3.301999",\ + "0.827832, 1.102018, 1.383491, 1.857584, 2.806803",\ + "0.841953, 1.116172, 1.397786, 1.872221, 2.822129",\ + "0.864423, 1.138688, 1.420491, 1.895391, 2.846229",\ + "1.044820, 1.319229, 1.601635, 2.078008, 3.031801",\ + "1.378863, 1.653263, 1.935629, 2.411906, 3.365508",\ + "1.164787, 1.467934, 1.735422, 2.206954, 3.152259",\ + "1.178910, 1.482098, 1.749720, 2.221593, 3.167585",\ + "1.201382, 1.504627, 1.772430, 2.244764, 3.191684",\ + "1.381788, 1.685212, 1.953590, 2.427387, 3.377256",\ + "1.715830, 2.019242, 2.287583, 2.761285, 3.710964"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.096357, 0.096687, 0.098113, 0.101595, 0.108560",\ + "0.099813, 0.100112, 0.101404, 0.104560, 0.110871",\ + "0.118608, 0.118888, 0.120098, 0.123051, 0.128958",\ + "0.380772, 0.380788, 0.380959, 0.381468, 0.382485",\ + "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\ + "0.096357, 0.096690, 0.098124, 0.101595, 0.108560",\ + "0.099813, 0.100115, 0.101414, 0.104560, 0.110871",\ + "0.118608, 0.118891, 0.120107, 0.123051, 0.128958",\ + "0.380772, 0.380788, 0.380960, 0.381468, 0.382485",\ + "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\ + "0.096357, 0.096696, 0.098124, 0.101595, 0.108560",\ + "0.099813, 0.100120, 0.101415, 0.104560, 0.110871",\ + "0.118609, 0.118896, 0.120107, 0.123051, 0.128958",\ + "0.380772, 0.380788, 0.380960, 0.381468, 0.382485",\ + "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\ + "0.096364, 0.096704, 0.098125, 0.101595, 0.108560",\ + "0.099820, 0.100128, 0.101415, 0.104560, 0.110871",\ + "0.118615, 0.118903, 0.120108, 0.123051, 0.128958",\ + "0.380772, 0.380789, 0.380961, 0.381468, 0.382485",\ + "1.026328, 1.026331, 1.026361, 1.026448, 1.026622",\ + "0.096383, 0.096806, 0.098160, 0.101610, 0.108560",\ + "0.099837, 0.100220, 0.101447, 0.104573, 0.110871",\ + "0.118631, 0.118989, 0.120138, 0.123064, 0.128958",\ + "0.380772, 0.380794, 0.380966, 0.381470, 0.382485",\ + "1.026328, 1.026332, 1.026362, 1.026448, 1.026622"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_2715*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.476785, 0.693340, 0.873015, 1.163119, 1.725535",\ + "0.496002, 0.712556, 0.892232, 1.182336, 1.744752",\ + "0.527650, 0.744204, 0.923880, 1.213984, 1.776400",\ + "0.818239, 1.034793, 1.214469, 1.504573, 2.066989",\ + "1.412242, 1.628797, 1.808472, 2.098576, 2.660992",\ + "0.565076, 0.780658, 0.960296, 1.250424, 1.812889",\ + "0.584292, 0.799874, 0.979512, 1.269641, 1.832105",\ + "0.615941, 0.831523, 1.011161, 1.301289, 1.863753",\ + "0.906530, 1.122112, 1.301750, 1.591878, 2.154342",\ + "1.500533, 1.716115, 1.895753, 2.185881, 2.748345",\ + "0.654117, 0.860991, 1.040323, 1.330453, 1.892920",\ + "0.673334, 0.880207, 1.059539, 1.349669, 1.912137",\ + "0.704982, 0.911855, 1.091188, 1.381318, 1.943785",\ + "0.995571, 1.202444, 1.381777, 1.671907, 2.234374",\ + "1.589574, 1.796447, 1.975780, 2.265910, 2.828377",\ + "0.717479, 0.918821, 1.098020, 1.387885, 1.949940",\ + "0.736695, 0.938038, 1.117237, 1.407101, 1.969157",\ + "0.768343, 0.969686, 1.148885, 1.438750, 2.000805",\ + "1.058932, 1.260275, 1.439474, 1.729339, 2.291394",\ + "1.652935, 1.854278, 2.033477, 2.323342, 2.885397",\ + "1.042371, 1.224140, 1.401676, 1.691058, 2.252168",\ + "1.061587, 1.243356, 1.420893, 1.710275, 2.271384",\ + "1.093235, 1.275004, 1.452541, 1.741923, 2.303032",\ + "1.383824, 1.565593, 1.743130, 2.032512, 2.593621",\ + "1.977827, 2.159596, 2.337133, 2.626515, 3.187624"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.489199, 0.705753, 0.885429, 1.175533, 1.737949",\ + "0.497006, 0.713560, 0.893235, 1.183340, 1.745756",\ + "0.510387, 0.726941, 0.906617, 1.196721, 1.759137",\ + "0.662333, 0.878887, 1.058563, 1.348667, 1.911083",\ + "0.995767, 1.212322, 1.391997, 1.682102, 2.244518",\ + "0.577490, 0.793071, 0.972710, 1.262838, 1.825302",\ + "0.585296, 0.800878, 0.980516, 1.270645, 1.833109",\ + "0.598678, 0.814260, 0.993898, 1.284026, 1.846490",\ + "0.750624, 0.966205, 1.145844, 1.435972, 1.998436",\ + "1.084058, 1.299640, 1.479278, 1.769407, 2.331871",\ + "0.666531, 0.873404, 1.052737, 1.342866, 1.905334",\ + "0.674337, 0.881211, 1.060543, 1.350673, 1.913141",\ + "0.687719, 0.894592, 1.073925, 1.364055, 1.926522",\ + "0.839665, 1.046538, 1.225871, 1.516001, 2.078468",\ + "1.173099, 1.379973, 1.559305, 1.849435, 2.411902",\ + "0.729892, 0.931235, 1.110434, 1.400298, 1.962354",\ + "0.737699, 0.939041, 1.118240, 1.408105, 1.970161",\ + "0.751080, 0.952423, 1.131622, 1.421487, 1.983542",\ + "0.903026, 1.104369, 1.283568, 1.573432, 2.135488",\ + "1.236461, 1.437803, 1.617002, 1.906867, 2.468923",\ + "1.054784, 1.236553, 1.414090, 1.703472, 2.264581",\ + "1.062591, 1.244360, 1.421896, 1.711279, 2.272388",\ + "1.075972, 1.257741, 1.435278, 1.724660, 2.285769",\ + "1.227918, 1.409687, 1.587224, 1.876606, 2.437715",\ + "1.561353, 1.743122, 1.920659, 2.210041, 2.771150"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2568*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.486016, 0.718373, 0.902601, 1.196441, 1.764052",\ + "0.505233, 0.737590, 0.921817, 1.215657, 1.783269",\ + "0.536881, 0.769238, 0.953465, 1.247305, 1.814917",\ + "0.827470, 1.059827, 1.244054, 1.537894, 2.105506",\ + "1.421473, 1.653830, 1.838057, 2.131897, 2.699509",\ + "0.574330, 0.805691, 0.989882, 1.283746, 1.851406",\ + "0.593546, 0.824908, 1.009098, 1.302962, 1.870622",\ + "0.625194, 0.856556, 1.040746, 1.334610, 1.902271",\ + "0.915783, 1.147145, 1.331335, 1.625199, 2.192860",\ + "1.509786, 1.741148, 1.925338, 2.219203, 2.786862",\ + "0.663471, 0.886024, 1.069909, 1.363774, 1.931437",\ + "0.682687, 0.905240, 1.089125, 1.382991, 1.950654",\ + "0.714335, 0.936888, 1.120773, 1.414639, 1.982302",\ + "1.004924, 1.227477, 1.411362, 1.705228, 2.272891",\ + "1.598927, 1.821480, 2.005365, 2.299231, 2.866894",\ + "0.726940, 0.943856, 1.127617, 1.421213, 1.988470",\ + "0.746156, 0.963072, 1.146833, 1.440429, 2.007687",\ + "0.777804, 0.994720, 1.178482, 1.472077, 2.039335",\ + "1.068393, 1.285309, 1.469070, 1.762666, 2.329924",\ + "1.662396, 1.879312, 2.063073, 2.356669, 2.923927",\ + "1.062221, 1.249183, 1.431275, 1.724391, 2.290713",\ + "1.081437, 1.268400, 1.450491, 1.743608, 2.309929",\ + "1.113086, 1.300048, 1.482139, 1.775256, 2.341578",\ + "1.403675, 1.590637, 1.772728, 2.065845, 2.632166",\ + "1.997678, 2.184640, 2.366731, 2.659848, 3.226169"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.498430, 0.730787, 0.915014, 1.208854, 1.776466",\ + "0.506236, 0.738593, 0.922821, 1.216661, 1.784272",\ + "0.519618, 0.751975, 0.936202, 1.230042, 1.797654",\ + "0.671564, 0.903921, 1.088148, 1.381988, 1.949600",\ + "1.004998, 1.237355, 1.421583, 1.715423, 2.283034",\ + "0.586743, 0.818105, 1.002295, 1.296159, 1.863819",\ + "0.594550, 0.825911, 1.010102, 1.303966, 1.871626",\ + "0.607931, 0.839293, 1.023483, 1.317347, 1.885008",\ + "0.759877, 0.991239, 1.175429, 1.469293, 2.036953",\ + "1.093312, 1.324673, 1.508864, 1.802728, 2.370388",\ + "0.675884, 0.898437, 1.082322, 1.376188, 1.943851",\ + "0.683691, 0.906244, 1.090129, 1.383994, 1.951658",\ + "0.697072, 0.919625, 1.103510, 1.397376, 1.965039",\ + "0.849018, 1.071571, 1.255456, 1.549322, 2.116985",\ + "1.182453, 1.405006, 1.588891, 1.882756, 2.450419",\ + "0.739353, 0.956269, 1.140030, 1.433626, 2.000884",\ + "0.747160, 0.964076, 1.147837, 1.441433, 2.008690",\ + "0.760541, 0.977457, 1.161218, 1.454814, 2.022072",\ + "0.912487, 1.129403, 1.313164, 1.606760, 2.174018",\ + "1.245922, 1.462838, 1.646599, 1.940195, 2.507452",\ + "1.074634, 1.261597, 1.443688, 1.736805, 2.303126",\ + "1.082441, 1.269403, 1.451495, 1.744612, 2.310933",\ + "1.095823, 1.282785, 1.464876, 1.757993, 2.324314",\ + "1.247769, 1.434731, 1.616822, 1.909939, 2.476260",\ + "1.581203, 1.768166, 1.950257, 2.243373, 2.809695"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2617*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.524148, 0.759556, 0.949466, 1.254683, 1.845217",\ + "0.543365, 0.778772, 0.968683, 1.273899, 1.864433",\ + "0.575013, 0.810420, 1.000331, 1.305547, 1.896082",\ + "0.865602, 1.101009, 1.290920, 1.596136, 2.186671",\ + "1.459605, 1.695012, 1.884923, 2.190139, 2.780674",\ + "0.612629, 0.846874, 1.036747, 1.341988, 1.932570",\ + "0.631845, 0.866090, 1.055964, 1.361204, 1.951787",\ + "0.663493, 0.897739, 1.087612, 1.392852, 1.983435",\ + "0.954082, 1.188328, 1.378201, 1.683442, 2.274024",\ + "1.548085, 1.782331, 1.972204, 2.277444, 2.868027",\ + "0.702172, 0.927207, 1.116774, 1.422016, 2.012602",\ + "0.721389, 0.946423, 1.135991, 1.441233, 2.031818",\ + "0.753037, 0.978072, 1.167639, 1.472881, 2.063467",\ + "1.043626, 1.268661, 1.458228, 1.763470, 2.354056",\ + "1.637629, 1.862664, 2.052231, 2.357473, 2.948059",\ + "0.765979, 0.985042, 1.174496, 1.479482, 2.069690",\ + "0.785195, 1.004258, 1.193712, 1.498699, 2.088906",\ + "0.816843, 1.035906, 1.225360, 1.530347, 2.120554",\ + "1.107432, 1.326495, 1.515949, 1.820936, 2.411143",\ + "1.701435, 1.920498, 2.109952, 2.414939, 3.005147",\ + "1.103410, 1.290390, 1.478156, 1.782685, 2.371999",\ + "1.122626, 1.309606, 1.497372, 1.801901, 2.391215",\ + "1.154274, 1.341254, 1.529020, 1.833550, 2.422863",\ + "1.444863, 1.631843, 1.819609, 2.124139, 2.713452",\ + "2.038866, 2.225846, 2.413612, 2.718142, 3.307455"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115267, 0.115267, 0.115267, 0.115267, 0.115267",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.536562, 0.771969, 0.961880, 1.267096, 1.857630",\ + "0.544368, 0.779776, 0.969686, 1.274903, 1.865437",\ + "0.557750, 0.793157, 0.983068, 1.288284, 1.878819",\ + "0.709696, 0.945103, 1.135014, 1.440230, 2.030764",\ + "1.043130, 1.278538, 1.468448, 1.773665, 2.364199",\ + "0.625042, 0.859287, 1.049161, 1.354401, 1.944984",\ + "0.632849, 0.867094, 1.056967, 1.362208, 1.952790",\ + "0.646230, 0.880476, 1.070349, 1.375589, 1.966172",\ + "0.798176, 1.032422, 1.222295, 1.527535, 2.118118",\ + "1.131611, 1.365856, 1.555729, 1.860970, 2.451552",\ + "0.714586, 0.939620, 1.129188, 1.434430, 2.025015",\ + "0.722392, 0.947427, 1.136994, 1.442236, 2.032822",\ + "0.735774, 0.960809, 1.150376, 1.455618, 2.046204",\ + "0.887720, 1.112755, 1.302322, 1.607564, 2.198149",\ + "1.221154, 1.446189, 1.635756, 1.940998, 2.531584",\ + "0.778392, 0.997455, 1.186909, 1.491896, 2.082103",\ + "0.786199, 1.005262, 1.194716, 1.499702, 2.089910",\ + "0.799580, 1.018643, 1.208097, 1.513084, 2.103292",\ + "0.951526, 1.170589, 1.360043, 1.665030, 2.255237",\ + "1.284961, 1.504024, 1.693478, 1.998464, 2.588672",\ + "1.115823, 1.302803, 1.490569, 1.795098, 2.384412",\ + "1.123630, 1.310610, 1.498376, 1.802905, 2.392219",\ + "1.137011, 1.323991, 1.511757, 1.816287, 2.405600",\ + "1.288957, 1.475937, 1.663703, 1.968233, 2.557546",\ + "1.622392, 1.809372, 1.997138, 2.301667, 2.890981"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.507236, 0.738300, 0.923184, 1.222269, 1.802199",\ + "0.526452, 0.757517, 0.942400, 1.241485, 1.821415",\ + "0.558100, 0.789165, 0.974048, 1.273133, 1.853063",\ + "0.848689, 1.079754, 1.264637, 1.563722, 2.143652",\ + "1.442692, 1.673757, 1.858641, 2.157725, 2.737655",\ + "0.595614, 0.825618, 1.010465, 1.309574, 1.889552",\ + "0.614831, 0.844835, 1.029681, 1.328790, 1.908768",\ + "0.646479, 0.876483, 1.061329, 1.360438, 1.940417",\ + "0.937068, 1.167072, 1.351918, 1.651027, 2.231006",\ + "1.531071, 1.761075, 1.945922, 2.245030, 2.825009",\ + "0.685193, 0.905949, 1.090492, 1.389602, 1.969584",\ + "0.704409, 0.925165, 1.109708, 1.408819, 1.988800",\ + "0.736058, 0.956813, 1.141356, 1.440467, 2.020448",\ + "1.026647, 1.247402, 1.431945, 1.731056, 2.311038",\ + "1.620650, 1.841405, 2.025949, 2.325059, 2.905041",\ + "0.749178, 0.963779, 1.148202, 1.447056, 2.026647",\ + "0.768394, 0.982995, 1.167418, 1.466272, 2.045864",\ + "0.800042, 1.014643, 1.199067, 1.497920, 2.077512",\ + "1.090631, 1.305233, 1.489656, 1.788509, 2.368101",\ + "1.684634, 1.899235, 2.083659, 2.382513, 2.962104",\ + "1.087729, 1.269086, 1.451859, 1.750247, 2.328927",\ + "1.106946, 1.288302, 1.471076, 1.769464, 2.348143",\ + "1.138594, 1.319950, 1.502724, 1.801112, 2.379791",\ + "1.429183, 1.610539, 1.793313, 2.091701, 2.670381",\ + "2.023186, 2.204542, 2.387316, 2.685704, 3.264384"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353",\ + "0.115268, 0.115268, 0.115268, 0.115268, 0.115268",\ + "0.141939, 0.141939, 0.141939, 0.141939, 0.141939",\ + "0.190556, 0.190556, 0.190556, 0.190556, 0.190556",\ + "0.817533, 0.817533, 0.817533, 0.817533, 0.817533",\ + "2.193353, 2.193353, 2.193353, 2.193353, 2.193353"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.519649, 0.750714, 0.935597, 1.234682, 1.814612",\ + "0.527456, 0.758521, 0.943404, 1.242489, 1.822419",\ + "0.540837, 0.771902, 0.956786, 1.255870, 1.835800",\ + "0.692783, 0.923848, 1.108731, 1.407816, 1.987746",\ + "1.026218, 1.257282, 1.442166, 1.741251, 2.321181",\ + "0.608028, 0.838032, 1.022878, 1.321987, 1.901966",\ + "0.615835, 0.845838, 1.030685, 1.329794, 1.909772",\ + "0.629216, 0.859220, 1.044067, 1.343176, 1.923154",\ + "0.781162, 1.011166, 1.196012, 1.495121, 2.075100",\ + "1.114597, 1.344600, 1.529447, 1.828556, 2.408534",\ + "0.697607, 0.918362, 1.102905, 1.402016, 1.981997",\ + "0.705413, 0.926169, 1.110712, 1.409823, 1.989804",\ + "0.718795, 0.939550, 1.124094, 1.423204, 2.003186",\ + "0.870741, 1.091496, 1.276039, 1.575150, 2.155131",\ + "1.204175, 1.424931, 1.609474, 1.908584, 2.488566",\ + "0.761591, 0.976192, 1.160616, 1.459469, 2.039061",\ + "0.769398, 0.983999, 1.168422, 1.467276, 2.046868",\ + "0.782779, 0.997381, 1.181804, 1.480658, 2.060249",\ + "0.934725, 1.149326, 1.333750, 1.632603, 2.212195",\ + "1.268160, 1.482761, 1.667184, 1.966038, 2.545630",\ + "1.100143, 1.281499, 1.464273, 1.762661, 2.341341",\ + "1.107950, 1.289306, 1.472080, 1.770468, 2.349147",\ + "1.121331, 1.302687, 1.485461, 1.783849, 2.362529",\ + "1.273277, 1.454633, 1.637407, 1.935795, 2.514474",\ + "1.606712, 1.788068, 1.970841, 2.269229, 2.847909"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262",\ + "0.049723, 0.049723, 0.049723, 0.049723, 0.049723",\ + "0.055443, 0.055443, 0.055443, 0.055443, 0.055443",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368589, 0.368589, 0.368589, 0.368589, 0.368589",\ + "1.002262, 1.002262, 1.002262, 1.002262, 1.002262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2419*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.424754, 0.655573, 0.839933, 1.133631, 1.700828",\ + "0.443986, 0.674805, 0.859165, 1.152863, 1.720060",\ + "0.475654, 0.706473, 0.890833, 1.184531, 1.751728",\ + "0.765910, 0.996730, 1.181089, 1.474787, 2.041985",\ + "1.359893, 1.590712, 1.775072, 2.068770, 2.635967",\ + "0.513060, 0.742891, 0.927214, 1.220936, 1.788182",\ + "0.532291, 0.762123, 0.946446, 1.240168, 1.807413",\ + "0.563959, 0.793791, 0.978114, 1.271836, 1.839081",\ + "0.854216, 1.084048, 1.268370, 1.562092, 2.129338",\ + "1.448198, 1.678030, 1.862353, 2.156075, 2.723320",\ + "0.602427, 0.823222, 1.007241, 1.300965, 1.868213",\ + "0.621658, 0.842453, 1.026473, 1.320196, 1.887445",\ + "0.653326, 0.874121, 1.058141, 1.351864, 1.919113",\ + "0.943583, 1.164378, 1.348397, 1.642121, 2.209370",\ + "1.537565, 1.758360, 1.942380, 2.236103, 2.803352",\ + "0.666215, 0.881051, 1.064950, 1.358403, 1.925246",\ + "0.685446, 0.900283, 1.084182, 1.377634, 1.944478",\ + "0.717114, 0.931951, 1.115850, 1.409302, 1.976146",\ + "1.007371, 1.222207, 1.406106, 1.699559, 2.266402",\ + "1.601353, 1.816190, 2.000089, 2.293541, 2.860385",\ + "1.003512, 1.186351, 1.368608, 1.661581, 2.227489",\ + "1.022744, 1.205583, 1.387839, 1.680812, 2.246720",\ + "1.054412, 1.237251, 1.419507, 1.712481, 2.278388",\ + "1.344668, 1.527507, 1.709764, 2.002737, 2.568645",\ + "1.938651, 2.121490, 2.303746, 2.596720, 3.162627"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.436529, 0.667348, 0.851708, 1.145406, 1.712603",\ + "0.444331, 0.675151, 0.859510, 1.153208, 1.720405",\ + "0.457727, 0.688547, 0.872906, 1.166604, 1.733801",\ + "0.609942, 0.840761, 1.025121, 1.318819, 1.886016",\ + "0.943575, 1.174394, 1.358754, 1.652452, 2.219649",\ + "0.524834, 0.754666, 0.938989, 1.232711, 1.799956",\ + "0.532637, 0.762468, 0.946791, 1.240513, 1.807759",\ + "0.546033, 0.775864, 0.960187, 1.253909, 1.821155",\ + "0.698247, 0.928079, 1.112402, 1.406124, 1.973369",\ + "1.031881, 1.261712, 1.446035, 1.739757, 2.307003",\ + "0.614201, 0.834996, 1.019016, 1.312739, 1.879988",\ + "0.622004, 0.842799, 1.026818, 1.320542, 1.887790",\ + "0.635400, 0.856195, 1.040214, 1.333938, 1.901186",\ + "0.787614, 1.008409, 1.192429, 1.486152, 2.053401",\ + "1.121248, 1.342043, 1.526062, 1.819786, 2.387034",\ + "0.677989, 0.892826, 1.076725, 1.370177, 1.937021",\ + "0.685792, 0.900628, 1.084527, 1.377980, 1.944823",\ + "0.699188, 0.914024, 1.097923, 1.391376, 1.958219",\ + "0.851402, 1.066239, 1.250138, 1.543590, 2.110434",\ + "1.185036, 1.399872, 1.583771, 1.877224, 2.444067",\ + "1.015287, 1.198126, 1.380382, 1.673356, 2.239263",\ + "1.023089, 1.205928, 1.388185, 1.681158, 2.247066",\ + "1.036485, 1.219324, 1.401581, 1.694554, 2.260462",\ + "1.188700, 1.371539, 1.553795, 1.846768, 2.412676",\ + "1.522333, 1.705172, 1.887429, 2.180402, 2.746310"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2319*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.417176, 0.631777, 0.810666, 1.100090, 1.661570",\ + "0.436407, 0.651008, 0.829897, 1.119321, 1.680801",\ + "0.468075, 0.682676, 0.861565, 1.150989, 1.712470",\ + "0.758331, 0.972932, 1.151822, 1.441245, 2.002726",\ + "1.352314, 1.566915, 1.745804, 2.035228, 2.596708",\ + "0.505449, 0.719094, 0.897947, 1.187395, 1.748923",\ + "0.524681, 0.738326, 0.917178, 1.206626, 1.768155",\ + "0.556349, 0.769994, 0.948847, 1.238294, 1.799823",\ + "0.846605, 1.060250, 1.239103, 1.528551, 2.090079",\ + "1.440588, 1.654232, 1.833085, 2.122533, 2.684062",\ + "0.594993, 0.799422, 0.977974, 1.267423, 1.828955",\ + "0.614224, 0.818654, 0.997205, 1.286655, 1.848186",\ + "0.645892, 0.850322, 1.028873, 1.318323, 1.879855",\ + "0.936148, 1.140578, 1.319129, 1.608579, 2.170111",\ + "1.530131, 1.734560, 1.913112, 2.202561, 2.764093",\ + "0.659061, 0.857252, 1.035670, 1.324854, 1.885975",\ + "0.678293, 0.876483, 1.054902, 1.344086, 1.905207",\ + "0.709961, 0.908151, 1.086570, 1.375754, 1.936875",\ + "1.000217, 1.198407, 1.376826, 1.666010, 2.227131",\ + "1.594199, 1.792390, 1.970809, 2.259993, 2.821113",\ + "0.982918, 1.162544, 1.339325, 1.628026, 2.188202",\ + "1.002150, 1.181776, 1.358556, 1.647258, 2.207434",\ + "1.033818, 1.213444, 1.390224, 1.678926, 2.239102",\ + "1.324074, 1.503700, 1.680480, 1.969182, 2.529358",\ + "1.918056, 2.097682, 2.274463, 2.563165, 3.123341"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.428949, 0.643550, 0.822439, 1.111863, 1.673344",\ + "0.436752, 0.651353, 0.830242, 1.119666, 1.681146",\ + "0.450148, 0.664749, 0.843638, 1.133062, 1.694542",\ + "0.602363, 0.816964, 0.995853, 1.285277, 1.846757",\ + "0.935996, 1.150597, 1.329487, 1.618910, 2.180391",\ + "0.517223, 0.730868, 0.909721, 1.199168, 1.760697",\ + "0.525026, 0.738670, 0.917523, 1.206971, 1.768500",\ + "0.538422, 0.752066, 0.930919, 1.220367, 1.781896",\ + "0.690637, 0.904281, 1.083134, 1.372582, 1.934110",\ + "1.024270, 1.237915, 1.416768, 1.706216, 2.267744",\ + "0.606766, 0.811196, 0.989747, 1.279197, 1.840729",\ + "0.614569, 0.818998, 0.997550, 1.286999, 1.848531",\ + "0.627965, 0.832394, 1.010946, 1.300395, 1.861927",\ + "0.780180, 0.984609, 1.163161, 1.452610, 2.014142",\ + "1.113814, 1.318243, 1.496794, 1.786244, 2.347776",\ + "0.670835, 0.869025, 1.047444, 1.336628, 1.897749",\ + "0.678637, 0.876828, 1.055247, 1.344431, 1.905551",\ + "0.692033, 0.890224, 1.068643, 1.357827, 1.918947",\ + "0.844248, 1.042439, 1.220857, 1.510042, 2.071162",\ + "1.177882, 1.376072, 1.554491, 1.843675, 2.404796",\ + "0.994692, 1.174318, 1.351099, 1.639800, 2.199976",\ + "1.002494, 1.182121, 1.358901, 1.647603, 2.207778",\ + "1.015890, 1.195517, 1.372297, 1.660999, 2.221174",\ + "1.168105, 1.347732, 1.524512, 1.813214, 2.373389",\ + "1.501739, 1.681365, 1.858145, 2.146847, 2.707023"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2377*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.566889, 0.778471, 0.964383, 1.255517, 1.814850",\ + "0.586120, 0.797703, 0.983615, 1.274748, 1.834081",\ + "0.617788, 0.829371, 1.015283, 1.306417, 1.865749",\ + "0.908045, 1.119627, 1.305539, 1.596673, 2.156006",\ + "1.502027, 1.713610, 1.899522, 2.190655, 2.749988",\ + "0.655251, 0.865790, 1.051664, 1.342822, 1.902203",\ + "0.674483, 0.885021, 1.070896, 1.362054, 1.921435",\ + "0.706151, 0.916689, 1.102564, 1.393722, 1.953103",\ + "0.996407, 1.206946, 1.392820, 1.683978, 2.243359",\ + "1.590390, 1.800928, 1.986803, 2.277961, 2.837342",\ + "0.744310, 0.946124, 1.131691, 1.422850, 1.982235",\ + "0.763542, 0.965355, 1.150923, 1.442082, 2.001466",\ + "0.795210, 0.997024, 1.182591, 1.473750, 2.033134",\ + "1.085467, 1.287280, 1.472847, 1.764007, 2.323391",\ + "1.679449, 1.881263, 2.066830, 2.357989, 2.917373",\ + "0.807605, 1.003952, 1.189403, 1.480278, 2.039247",\ + "0.826837, 1.023183, 1.208634, 1.499510, 2.058478",\ + "0.858505, 1.054851, 1.240302, 1.531178, 2.090147",\ + "1.148761, 1.345108, 1.530559, 1.821435, 2.380403",\ + "1.742744, 1.939090, 2.124541, 2.415417, 2.974385",\ + "1.127529, 1.309255, 1.493062, 1.783449, 2.341464",\ + "1.146761, 1.328487, 1.512293, 1.802681, 2.360695",\ + "1.178429, 1.360155, 1.543962, 1.834349, 2.392364",\ + "1.468686, 1.650411, 1.834218, 2.124605, 2.682620",\ + "2.062668, 2.244394, 2.428200, 2.718588, 3.276602"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.578663, 0.790246, 0.976158, 1.267292, 1.826624",\ + "0.586466, 0.798048, 0.983960, 1.275094, 1.834427",\ + "0.599862, 0.811444, 0.997356, 1.288490, 1.847823",\ + "0.752076, 0.963659, 1.149571, 1.440704, 2.000037",\ + "1.085710, 1.297292, 1.483204, 1.774338, 2.333671",\ + "0.667026, 0.877564, 1.063439, 1.354597, 1.913978",\ + "0.674828, 0.885367, 1.071241, 1.362399, 1.921780",\ + "0.688224, 0.898763, 1.084637, 1.375795, 1.935176",\ + "0.840439, 1.050977, 1.236852, 1.528010, 2.087391",\ + "1.174072, 1.384611, 1.570485, 1.861643, 2.421024",\ + "0.756085, 0.957898, 1.143466, 1.434625, 1.994009",\ + "0.763888, 0.965701, 1.151268, 1.442428, 2.001812",\ + "0.777284, 0.979097, 1.164664, 1.455824, 2.015208",\ + "0.929498, 1.131311, 1.316879, 1.608038, 2.167422",\ + "1.263131, 1.464945, 1.650512, 1.941671, 2.501056",\ + "0.819380, 1.015726, 1.201177, 1.492053, 2.051021",\ + "0.827182, 1.023529, 1.208980, 1.499856, 2.058824",\ + "0.840578, 1.036925, 1.222376, 1.513252, 2.072220",\ + "0.992793, 1.189139, 1.374590, 1.665466, 2.224434",\ + "1.326426, 1.522773, 1.708224, 1.999099, 2.558068",\ + "1.139304, 1.321030, 1.504837, 1.795224, 2.353239",\ + "1.147106, 1.328832, 1.512639, 1.803026, 2.361041",\ + "1.160502, 1.342228, 1.526035, 1.816422, 2.374437",\ + "1.312717, 1.494443, 1.678249, 1.968637, 2.526651",\ + "1.646350, 1.828076, 2.011883, 2.302270, 2.860285"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2596*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.541408, 0.751703, 0.928714, 1.212888, 1.762989",\ + "0.560640, 0.770935, 0.947946, 1.232119, 1.782221",\ + "0.592308, 0.802603, 0.979614, 1.263787, 1.813889",\ + "0.882565, 1.092860, 1.269870, 1.554044, 2.104145",\ + "1.476547, 1.686842, 1.863853, 2.148026, 2.698128",\ + "0.629685, 0.839022, 1.015995, 1.300193, 1.850343",\ + "0.648917, 0.858253, 1.035227, 1.319424, 1.869574",\ + "0.680585, 0.889921, 1.066895, 1.351092, 1.901242",\ + "0.970842, 1.180178, 1.357151, 1.641349, 2.191499",\ + "1.564824, 1.774160, 1.951134, 2.235331, 2.785481",\ + "0.718639, 0.919355, 1.096022, 1.380221, 1.930374",\ + "0.737870, 0.938586, 1.115254, 1.399453, 1.949606",\ + "0.769538, 0.970254, 1.146922, 1.431121, 1.981274",\ + "1.059795, 1.260511, 1.437178, 1.721377, 2.271530",\ + "1.653777, 1.854493, 2.031161, 2.315360, 2.865513",\ + "0.781897, 0.977177, 1.153713, 1.437638, 1.987364",\ + "0.801129, 0.996408, 1.172945, 1.456870, 2.006596",\ + "0.832797, 1.028076, 1.204613, 1.488538, 2.038264",\ + "1.123053, 1.318333, 1.494869, 1.778794, 2.328521",\ + "1.717036, 1.912315, 2.088852, 2.372777, 2.922503",\ + "1.102548, 1.282436, 1.457368, 1.740799, 2.289555",\ + "1.121780, 1.301668, 1.476600, 1.760030, 2.308787",\ + "1.153448, 1.333336, 1.508268, 1.791698, 2.340455",\ + "1.443705, 1.623593, 1.798525, 2.081955, 2.630712",\ + "2.037687, 2.217575, 2.392507, 2.675937, 3.224694"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227",\ + "0.112220, 0.112220, 0.112220, 0.112220, 0.112220",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189997, 0.189997, 0.189997, 0.189997, 0.189997",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194227, 2.194227, 2.194227, 2.194227, 2.194227"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.553183, 0.763478, 0.940489, 1.224662, 1.774764",\ + "0.560986, 0.771280, 0.948291, 1.232465, 1.782566",\ + "0.574382, 0.784676, 0.961687, 1.245861, 1.795962",\ + "0.726596, 0.936891, 1.113902, 1.398075, 1.948177",\ + "1.060230, 1.270525, 1.447535, 1.731709, 2.281810",\ + "0.641460, 0.850796, 1.027770, 1.311967, 1.862117",\ + "0.649263, 0.858599, 1.035572, 1.319770, 1.869920",\ + "0.662659, 0.871995, 1.048968, 1.333166, 1.883316",\ + "0.814873, 1.024209, 1.201183, 1.485380, 2.035530",\ + "1.148507, 1.357843, 1.534816, 1.819014, 2.369164",\ + "0.730413, 0.931129, 1.107797, 1.391996, 1.942149",\ + "0.738216, 0.938932, 1.115599, 1.399798, 1.949951",\ + "0.751612, 0.952328, 1.128995, 1.413194, 1.963347",\ + "0.903826, 1.104542, 1.281210, 1.565409, 2.115561",\ + "1.237460, 1.438176, 1.614843, 1.899042, 2.449195",\ + "0.793672, 0.988951, 1.165488, 1.449413, 1.999139",\ + "0.801474, 0.996754, 1.173290, 1.457215, 2.006941",\ + "0.814870, 1.010150, 1.186686, 1.470611, 2.020338",\ + "0.967085, 1.162364, 1.338901, 1.622826, 2.172552",\ + "1.300718, 1.495998, 1.672534, 1.956459, 2.506185",\ + "1.114323, 1.294211, 1.469143, 1.752573, 2.301330",\ + "1.122126, 1.302013, 1.476946, 1.760376, 2.309132",\ + "1.135522, 1.315410, 1.490342, 1.773772, 2.322528",\ + "1.287736, 1.467624, 1.642556, 1.925986, 2.474743",\ + "1.621369, 1.801257, 1.976189, 2.259620, 2.808376"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055489, 0.055489, 0.055489, 0.055489, 0.055489",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2653*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.563785, 0.784261, 0.961831, 1.250241, 1.810232",\ + "0.583017, 0.803492, 0.981063, 1.269472, 1.829463",\ + "0.614685, 0.835161, 1.012731, 1.301141, 1.861132",\ + "0.904941, 1.125417, 1.302987, 1.591397, 2.151388",\ + "1.498924, 1.719399, 1.896969, 2.185379, 2.745370",\ + "0.652174, 0.871579, 1.049112, 1.337546, 1.897585",\ + "0.671405, 0.890811, 1.068343, 1.356778, 1.916817",\ + "0.703073, 0.922479, 1.100012, 1.388446, 1.948485",\ + "0.993330, 1.212735, 1.390268, 1.678702, 2.238741",\ + "1.587312, 1.806717, 1.984250, 2.272684, 2.832724",\ + "0.741539, 0.951911, 1.129139, 1.417575, 1.977617",\ + "0.760771, 0.971143, 1.148370, 1.436806, 1.996849",\ + "0.792439, 1.002811, 1.180039, 1.468474, 2.028517",\ + "1.082695, 1.293067, 1.470295, 1.758730, 2.318773",\ + "1.676677, 1.887050, 2.064277, 2.352713, 2.912755",\ + "0.805219, 1.009732, 1.186831, 1.475004, 2.034631",\ + "0.824451, 1.028963, 1.206063, 1.494235, 2.053863",\ + "0.856119, 1.060631, 1.237731, 1.525903, 2.085531",\ + "1.146375, 1.350887, 1.527987, 1.816159, 2.375787",\ + "1.740357, 1.944870, 2.121970, 2.410142, 2.969770",\ + "1.135828, 1.314976, 1.490487, 1.778174, 2.336852",\ + "1.155060, 1.334207, 1.509718, 1.797406, 2.356083",\ + "1.186728, 1.365875, 1.541386, 1.829074, 2.387752",\ + "1.476984, 1.656131, 1.831642, 2.119330, 2.678008",\ + "2.070967, 2.250114, 2.425625, 2.713313, 3.271990"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.575559, 0.796035, 0.973605, 1.262015, 1.822006",\ + "0.583362, 0.803837, 0.981407, 1.269817, 1.829808",\ + "0.596758, 0.817233, 0.994803, 1.283213, 1.843204",\ + "0.748972, 0.969448, 1.147018, 1.435428, 1.995419",\ + "1.082606, 1.303082, 1.480652, 1.769062, 2.329053",\ + "0.663947, 0.883353, 1.060886, 1.349320, 1.909359",\ + "0.671750, 0.891155, 1.068688, 1.357122, 1.917162",\ + "0.685146, 0.904551, 1.082084, 1.370518, 1.930558",\ + "0.837361, 1.056766, 1.234299, 1.522733, 2.082772",\ + "1.170995, 1.390400, 1.567933, 1.856367, 2.416406",\ + "0.753313, 0.963685, 1.140913, 1.429348, 1.989391",\ + "0.761115, 0.971488, 1.148715, 1.437151, 1.997193",\ + "0.774511, 0.984884, 1.162111, 1.450547, 2.010589",\ + "0.926726, 1.137099, 1.314326, 1.602762, 2.162804",\ + "1.260360, 1.470732, 1.647960, 1.936395, 2.496438",\ + "0.816993, 1.021505, 1.198605, 1.486777, 2.046405",\ + "0.824796, 1.029308, 1.206408, 1.494580, 2.054208",\ + "0.838192, 1.042704, 1.219804, 1.507976, 2.067604",\ + "0.990406, 1.194919, 1.372019, 1.660191, 2.219819",\ + "1.324040, 1.528552, 1.705652, 1.993824, 2.553452",\ + "1.147602, 1.326749, 1.502260, 1.789948, 2.348625",\ + "1.155405, 1.334552, 1.510063, 1.797751, 2.356428",\ + "1.168801, 1.347948, 1.523459, 1.811147, 2.369824",\ + "1.321016, 1.500163, 1.675674, 1.963362, 2.522039",\ + "1.654649, 1.833796, 2.009307, 2.296995, 2.855672"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2304*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.537611, 0.765413, 0.949557, 1.244019, 1.813116",\ + "0.556843, 0.784645, 0.968788, 1.263250, 1.832347",\ + "0.588511, 0.816313, 1.000457, 1.294918, 1.864016",\ + "0.878767, 1.106569, 1.290713, 1.585174, 2.154272",\ + "1.472749, 1.700552, 1.884695, 2.179157, 2.748254",\ + "0.625940, 0.852732, 1.036838, 1.331324, 1.900469",\ + "0.645171, 0.871963, 1.056069, 1.350555, 1.919701",\ + "0.676839, 0.903631, 1.087738, 1.382223, 1.951369",\ + "0.967095, 1.193887, 1.377994, 1.672480, 2.241625",\ + "1.561078, 1.787870, 1.971976, 2.266462, 2.835608",\ + "0.715049, 0.933065, 1.116865, 1.411352, 1.980501",\ + "0.734280, 0.952296, 1.136096, 1.430584, 1.999732",\ + "0.765948, 0.983964, 1.167764, 1.462252, 2.031401",\ + "1.056204, 1.274220, 1.458020, 1.752508, 2.321657",\ + "1.650187, 1.868203, 2.052003, 2.346490, 2.915639",\ + "0.778454, 0.990889, 1.174573, 1.468792, 2.037537",\ + "0.797686, 1.010120, 1.193804, 1.488024, 2.056769",\ + "0.829354, 1.041789, 1.225472, 1.519692, 2.088437",\ + "1.119610, 1.332045, 1.515728, 1.809948, 2.378693",\ + "1.713592, 1.926027, 2.109711, 2.403930, 2.972675",\ + "1.113336, 1.296163, 1.478231, 1.771973, 2.339783",\ + "1.132567, 1.315395, 1.497462, 1.791204, 2.359015",\ + "1.164236, 1.347063, 1.529130, 1.822872, 2.390683",\ + "1.454492, 1.637319, 1.819386, 2.113128, 2.680939",\ + "2.048474, 2.231302, 2.413369, 2.707111, 3.274921"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229",\ + "0.112216, 0.112216, 0.112216, 0.112216, 0.112216",\ + "0.140967, 0.140967, 0.140967, 0.140967, 0.140967",\ + "0.189998, 0.189998, 0.189998, 0.189998, 0.189998",\ + "0.817613, 0.817613, 0.817613, 0.817613, 0.817613",\ + "2.194229, 2.194229, 2.194229, 2.194229, 2.194229"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.549385, 0.777187, 0.961331, 1.255792, 1.824890",\ + "0.557187, 0.784990, 0.969133, 1.263595, 1.832692",\ + "0.570583, 0.798386, 0.982529, 1.276991, 1.846088",\ + "0.722798, 0.950600, 1.134744, 1.429206, 1.998303",\ + "1.056432, 1.284234, 1.468378, 1.762839, 2.331937",\ + "0.637713, 0.864505, 1.048611, 1.343097, 1.912243",\ + "0.645516, 0.872308, 1.056414, 1.350900, 1.920045",\ + "0.658912, 0.885704, 1.069810, 1.364296, 1.933442",\ + "0.811127, 1.037919, 1.222025, 1.516511, 2.085656",\ + "1.144760, 1.371552, 1.555659, 1.850145, 2.419290",\ + "0.726822, 0.944838, 1.128638, 1.423126, 1.992275",\ + "0.734625, 0.952641, 1.136441, 1.430928, 2.000077",\ + "0.748021, 0.966037, 1.149837, 1.444324, 2.013473",\ + "0.900236, 1.118252, 1.302052, 1.596539, 2.165688",\ + "1.233869, 1.451885, 1.635685, 1.930173, 2.499322",\ + "0.790228, 1.002663, 1.186347, 1.480566, 2.049311",\ + "0.798030, 1.010465, 1.194149, 1.488369, 2.057113",\ + "0.811427, 1.023861, 1.207545, 1.501765, 2.070509",\ + "0.963641, 1.176076, 1.359760, 1.653979, 2.222724",\ + "1.297275, 1.509710, 1.693393, 1.987613, 2.556358",\ + "1.125110, 1.307937, 1.490004, 1.783746, 2.351557",\ + "1.132912, 1.315740, 1.497807, 1.791549, 2.359360",\ + "1.146308, 1.329136, 1.511203, 1.804945, 2.372756",\ + "1.298523, 1.481350, 1.663418, 1.957160, 2.524971",\ + "1.632157, 1.814984, 1.997051, 2.290793, 2.858604"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321",\ + "0.049540, 0.049540, 0.049540, 0.049540, 0.049540",\ + "0.055490, 0.055490, 0.055490, 0.055490, 0.055490",\ + "0.075307, 0.075307, 0.075307, 0.075307, 0.075307",\ + "0.368653, 0.368653, 0.368653, 0.368653, 0.368653",\ + "1.002321, 1.002321, 1.002321, 1.002321, 1.002321"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2347*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.452626, 0.644345, 0.833940, 1.131261, 1.702487",\ + "0.471843, 0.663562, 0.853157, 1.150478, 1.721704",\ + "0.503492, 0.695211, 0.884806, 1.182126, 1.753352",\ + "0.794073, 0.985792, 1.175388, 1.472708, 2.043935",\ + "1.388076, 1.579795, 1.769390, 2.066711, 2.637938",\ + "0.540843, 0.731664, 0.921221, 1.218566, 1.789840",\ + "0.560059, 0.750880, 0.940438, 1.237783, 1.809057",\ + "0.591708, 0.782529, 0.972087, 1.269431, 1.840706",\ + "0.882290, 1.073111, 1.262668, 1.560013, 2.131288",\ + "1.476292, 1.667113, 1.856671, 2.154016, 2.725291",\ + "0.629383, 0.811999, 1.001248, 1.298594, 1.869872",\ + "0.648600, 0.831216, 1.020465, 1.317811, 1.889089",\ + "0.680249, 0.862864, 1.052114, 1.349460, 1.920737",\ + "0.970830, 1.153446, 1.342695, 1.640042, 2.211320",\ + "1.564833, 1.747448, 1.936698, 2.234045, 2.805323",\ + "0.690888, 0.869827, 1.058969, 1.356037, 1.926912",\ + "0.710105, 0.889043, 1.078185, 1.375254, 1.946129",\ + "0.741754, 0.920692, 1.109834, 1.406902, 1.977778",\ + "1.032335, 1.211274, 1.400416, 1.697484, 2.268360",\ + "1.626338, 1.805276, 1.994418, 2.291487, 2.862363",\ + "0.993056, 1.175134, 1.362629, 1.659220, 2.229164",\ + "1.012272, 1.194351, 1.381846, 1.678436, 2.248380",\ + "1.043921, 1.226000, 1.413495, 1.710085, 2.280029",\ + "1.334502, 1.516581, 1.704077, 2.000667, 2.570611",\ + "1.928505, 2.110584, 2.298079, 2.594670, 3.164614"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\ + "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\ + "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\ + "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370",\ + "0.115198, 0.115198, 0.115199, 0.115202, 0.115208",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817535, 0.817534",\ + "2.193373, 2.193373, 2.193373, 2.193372, 2.193370"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.465025, 0.656744, 0.846340, 1.143661, 1.714888",\ + "0.472832, 0.664551, 0.854146, 1.151467, 1.722695",\ + "0.486213, 0.677933, 0.867528, 1.164849, 1.736077",\ + "0.638165, 0.829885, 1.019480, 1.316801, 1.888028",\ + "0.971605, 1.163324, 1.352919, 1.650240, 2.221466",\ + "0.553242, 0.744063, 0.933621, 1.230966, 1.802242",\ + "0.561048, 0.751869, 0.941427, 1.238772, 1.810048",\ + "0.574430, 0.765251, 0.954809, 1.252154, 1.823430",\ + "0.726382, 0.917203, 1.106761, 1.404106, 1.975381",\ + "1.059821, 1.250642, 1.440200, 1.737545, 2.308820",\ + "0.641782, 0.824398, 1.013648, 1.310994, 1.882273",\ + "0.649589, 0.832204, 1.021454, 1.318801, 1.890080",\ + "0.662971, 0.845586, 1.034836, 1.332183, 1.903462",\ + "0.814923, 0.997538, 1.186788, 1.484134, 2.055413",\ + "1.148362, 1.330977, 1.520227, 1.817573, 2.388851",\ + "0.703287, 0.882226, 1.071368, 1.368437, 1.939313",\ + "0.711094, 0.890032, 1.079175, 1.376243, 1.947120",\ + "0.724476, 0.903414, 1.092556, 1.389625, 1.960502",\ + "0.876427, 1.055366, 1.244508, 1.541577, 2.112453",\ + "1.209867, 1.388805, 1.577947, 1.875016, 2.445891",\ + "1.005455, 1.187533, 1.375029, 1.671620, 2.241565",\ + "1.013261, 1.195340, 1.382835, 1.679426, 2.249371",\ + "1.026643, 1.208722, 1.396217, 1.692808, 2.262753",\ + "1.178595, 1.360674, 1.548169, 1.844760, 2.414704",\ + "1.512034, 1.694113, 1.881608, 2.178198, 2.748142"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049719, 0.049719, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2394*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.181258, 0.362750, 0.559584, 0.877059, 1.491654",\ + "0.196091, 0.377154, 0.575199, 0.895881, 1.517263",\ + "0.221299, 0.401436, 0.600771, 0.925894, 1.556997",\ + "0.494050, 0.669272, 0.865120, 1.207435, 1.883536",\ + "1.086888, 1.260498, 1.453339, 1.802428, 2.497703",\ + "0.268666, 0.450068, 0.646865, 0.964364, 1.579007",\ + "0.283499, 0.464472, 0.662480, 0.983186, 1.604617",\ + "0.308707, 0.488754, 0.688052, 1.013199, 1.644350",\ + "0.581459, 0.756590, 0.952401, 1.294740, 1.970890",\ + "1.174296, 1.347816, 1.540620, 1.889733, 2.585056",\ + "0.349534, 0.530400, 0.726892, 1.044393, 1.659039",\ + "0.364365, 0.544804, 0.742507, 1.063215, 1.684648",\ + "0.389566, 0.569086, 0.768079, 1.093227, 1.724382",\ + "0.662286, 0.836922, 1.032428, 1.374768, 2.050921",\ + "1.255114, 1.428148, 1.620646, 1.969761, 2.665088",\ + "0.407230, 0.588238, 0.784630, 1.101888, 1.716185",\ + "0.422055, 0.602641, 0.800248, 1.120718, 1.741811",\ + "0.447245, 0.626919, 0.825823, 1.150743, 1.781568",\ + "0.719903, 0.894737, 1.090165, 1.432339, 2.108216",\ + "1.312710, 1.485957, 1.678376, 2.027355, 2.722429",\ + "0.710204, 0.893608, 1.088293, 1.405116, 2.018565",\ + "0.724980, 0.907999, 1.103911, 1.423953, 2.044210",\ + "0.750065, 0.932253, 1.129487, 1.453987, 2.083996",\ + "1.022164, 1.199940, 1.393827, 1.735630, 2.410775",\ + "1.614788, 1.791118, 1.982037, 2.330666, 3.025044"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126849, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149775, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195028, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194129, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126859, 0.127607, 0.133449, 0.151680, 0.191274",\ + "0.149782, 0.150311, 0.154660, 0.170585, 0.205820",\ + "0.195035, 0.195584, 0.198477, 0.210651, 0.237965",\ + "0.816155, 0.816256, 0.816260, 0.817810, 0.821601",\ + "2.194133, 2.194406, 2.194418, 2.195898, 2.199521",\ + "0.126945, 0.127627, 0.133451, 0.151721, 0.191389",\ + "0.149843, 0.150326, 0.154662, 0.170622, 0.205922",\ + "0.195098, 0.195599, 0.198478, 0.210679, 0.238045",\ + "0.816166, 0.816259, 0.816260, 0.817813, 0.821612",\ + "2.194165, 2.194413, 2.194418, 2.195902, 2.199532"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.117102, 0.379947, 0.573156, 0.882174, 1.479232",\ + "0.126091, 0.389068, 0.582472, 0.892519, 1.491929",\ + "0.141699, 0.404157, 0.597820, 0.909153, 1.511489",\ + "0.306945, 0.562483, 0.755606, 1.068523, 1.675209",\ + "0.649757, 0.897030, 1.089718, 1.401787, 2.006775",\ + "0.205481, 0.467265, 0.660437, 0.969479, 1.566586",\ + "0.214473, 0.476386, 0.669753, 0.979824, 1.579283",\ + "0.230076, 0.491475, 0.685100, 0.996458, 1.598842",\ + "0.395245, 0.649801, 0.842887, 1.155828, 1.762562",\ + "0.738017, 0.984348, 1.176999, 1.489092, 2.094129",\ + "0.294834, 0.547598, 0.740463, 1.049507, 1.646617",\ + "0.303840, 0.556719, 0.749780, 1.059852, 1.659314",\ + "0.319425, 0.571807, 0.765127, 1.076486, 1.678874",\ + "0.484368, 0.730134, 0.922914, 1.235856, 1.842594",\ + "0.827025, 1.064680, 1.257025, 1.569121, 2.174160",\ + "0.358511, 0.605438, 0.798193, 1.106982, 1.703722",\ + "0.367529, 0.614560, 0.807510, 1.117329, 1.716424",\ + "0.383098, 0.629648, 0.822858, 1.133967, 1.735991",\ + "0.547830, 0.787974, 0.980643, 1.293342, 1.899721",\ + "0.890379, 1.122520, 1.314754, 1.626604, 2.231284",\ + "0.695115, 0.910825, 1.101854, 1.410191, 2.006050",\ + "0.704209, 0.919948, 1.111171, 1.420541, 2.018759",\ + "0.719674, 0.935035, 1.126519, 1.437182, 2.038335",\ + "0.883062, 1.093358, 1.284304, 1.596561, 2.202077",\ + "1.224926, 1.427904, 1.618415, 1.929822, 2.533635"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.044794, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053408, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.044917, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053471, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.045280, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053656, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.045619, 0.049410, 0.054613, 0.068702, 0.098855",\ + "0.053828, 0.055759, 0.059110, 0.072274, 0.101681",\ + "0.075784, 0.075784, 0.078001, 0.088634, 0.112740",\ + "0.368045, 0.368045, 0.368835, 0.370660, 0.374443",\ + "1.001402, 1.001402, 1.001777, 1.002639, 1.004426",\ + "0.047777, 0.049532, 0.054615, 0.068733, 0.098943",\ + "0.054927, 0.055821, 0.059111, 0.072304, 0.101766",\ + "0.075784, 0.075784, 0.078002, 0.088659, 0.112810",\ + "0.368045, 0.368045, 0.368835, 0.370664, 0.374454",\ + "1.001402, 1.001402, 1.001777, 1.002641, 1.004432"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2316*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.098350, 0.258117, 0.412724, 0.663632, 1.151052",\ + "0.111306, 0.279646, 0.445289, 0.710490, 1.223646",\ + "0.138089, 0.311436, 0.490658, 0.774246, 1.320793",\ + "0.424991, 0.637508, 0.825514, 1.153509, 1.801342",\ + "1.020536, 1.249709, 1.439386, 1.764952, 2.405506",\ + "0.185759, 0.345435, 0.500005, 0.750937, 1.238405",\ + "0.198715, 0.366964, 0.532570, 0.797795, 1.310999",\ + "0.225498, 0.398754, 0.577939, 0.861551, 1.408146",\ + "0.513280, 0.724826, 0.912795, 1.240814, 1.888696",\ + "1.108868, 1.337027, 1.526667, 1.852257, 2.492859",\ + "0.266486, 0.425768, 0.580032, 0.830966, 1.318437",\ + "0.279498, 0.447297, 0.612597, 0.877824, 1.391031",\ + "0.306314, 0.479087, 0.657966, 0.941579, 1.488178",\ + "0.602279, 0.805159, 0.992822, 1.320843, 1.968727",\ + "1.197992, 1.417360, 1.606694, 1.932286, 2.572891",\ + "0.323899, 0.483524, 0.637672, 0.888307, 1.375276",\ + "0.337018, 0.505085, 0.670262, 0.935196, 1.447932",\ + "0.363897, 0.536894, 0.715662, 0.998992, 1.545160",\ + "0.665584, 0.862970, 1.050539, 1.378378, 2.025954",\ + "1.261413, 1.475185, 1.664415, 1.989812, 2.630099",\ + "0.624253, 0.788317, 0.941319, 1.191402, 1.677284",\ + "0.638351, 0.810106, 0.973913, 1.238318, 1.750015",\ + "0.665802, 0.842047, 1.019319, 1.302149, 1.847340",\ + "0.990853, 1.168154, 1.354199, 1.681640, 2.328429",\ + "1.596393, 1.780461, 1.968075, 2.293067, 2.932554"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.028418, 0.053830, 0.061535, 0.076150, 0.106328",\ + "0.053925, 0.080459, 0.084933, 0.098494, 0.128975",\ + "0.117469, 0.123739, 0.136658, 0.151484, 0.176772",\ + "0.813025, 0.813025, 0.813025, 0.814972, 0.819748",\ + "2.191689, 2.192946, 2.194005, 2.200700, 2.216248",\ + "0.028418, 0.053830, 0.061535, 0.076150, 0.106328",\ + "0.053925, 0.080459, 0.084933, 0.098494, 0.128975",\ + "0.117469, 0.123739, 0.136658, 0.151484, 0.176772",\ + "0.813025, 0.813025, 0.813025, 0.814972, 0.819748",\ + "2.191723, 2.192946, 2.194005, 2.200700, 2.216248",\ + "0.028584, 0.053830, 0.061535, 0.076150, 0.106328",\ + "0.054098, 0.080459, 0.084933, 0.098494, 0.128975",\ + "0.117510, 0.123739, 0.136658, 0.151484, 0.176772",\ + "0.813025, 0.813025, 0.813025, 0.814972, 0.819748",\ + "2.191823, 2.192946, 2.194005, 2.200700, 2.216248",\ + "0.028905, 0.053925, 0.061551, 0.076187, 0.106401",\ + "0.054433, 0.080559, 0.084941, 0.098531, 0.129049",\ + "0.117589, 0.123763, 0.136688, 0.151514, 0.176833",\ + "0.813025, 0.813025, 0.813025, 0.814978, 0.819760",\ + "2.191915, 2.192951, 2.194008, 2.200718, 2.216285",\ + "0.031805, 0.054598, 0.061553, 0.076218, 0.106489",\ + "0.057461, 0.081261, 0.084942, 0.098563, 0.129138",\ + "0.118304, 0.123929, 0.136693, 0.151541, 0.176907",\ + "0.813025, 0.813025, 0.813025, 0.814982, 0.819773",\ + "2.192503, 2.192984, 2.194008, 2.200735, 2.216331"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.069370, 0.283193, 0.491815, 0.800919, 1.367462",\ + "0.075632, 0.304498, 0.517002, 0.813952, 1.385072",\ + "0.088234, 0.333476, 0.530104, 0.830255, 1.407585",\ + "0.254611, 0.476253, 0.671078, 0.977854, 1.568006",\ + "0.593217, 0.801399, 0.995520, 1.304053, 1.898975",\ + "0.156902, 0.370515, 0.579033, 0.888224, 1.454816",\ + "0.163435, 0.391863, 0.604283, 0.901257, 1.472425",\ + "0.176298, 0.420901, 0.617385, 0.917560, 1.494938",\ + "0.342791, 0.563572, 0.758359, 1.065159, 1.655359",\ + "0.681370, 0.888717, 1.082801, 1.391358, 1.986328",\ + "0.243698, 0.458976, 0.666990, 0.968253, 1.534847",\ + "0.251018, 0.480422, 0.684310, 0.981285, 1.552457",\ + "0.264645, 0.506852, 0.697412, 0.997588, 1.574970",\ + "0.431471, 0.643905, 0.838386, 1.145188, 1.735391",\ + "0.769972, 0.969050, 1.162828, 1.471387, 2.066360",\ + "0.304960, 0.523854, 0.731112, 1.025689, 1.591878",\ + "0.313009, 0.545444, 0.742029, 1.038728, 1.609498",\ + "0.327344, 0.564695, 0.755135, 1.055038, 1.632026",\ + "0.494481, 0.701749, 0.896119, 1.202653, 1.792478",\ + "0.832908, 1.026881, 1.220559, 1.528858, 2.123458",\ + "0.626203, 0.851949, 1.035624, 1.328867, 1.894116",\ + "0.638895, 0.858887, 1.045689, 1.341910, 1.911750",\ + "0.657734, 0.870103, 1.058796, 1.358227, 1.934296",\ + "0.821978, 1.007166, 1.199781, 1.505856, 2.094786",\ + "1.150367, 1.332198, 1.524221, 1.832065, 2.425780"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.013843, 0.057624, 0.075770, 0.080313, 0.107471",\ + "0.025205, 0.064739, 0.067587, 0.083073, 0.115488",\ + "0.053856, 0.083413, 0.086593, 0.102413, 0.134994",\ + "0.368605, 0.368605, 0.369807, 0.373448, 0.381327",\ + "1.000406, 1.000406, 1.002130, 1.003829, 1.006481",\ + "0.014774, 0.057698, 0.075841, 0.080313, 0.107471",\ + "0.026141, 0.064772, 0.067587, 0.083073, 0.115488",\ + "0.054523, 0.083449, 0.086593, 0.102413, 0.134994",\ + "0.368605, 0.368605, 0.369807, 0.373448, 0.381327",\ + "1.000406, 1.000406, 1.002130, 1.003829, 1.006481",\ + "0.017481, 0.057867, 0.075842, 0.080313, 0.107471",\ + "0.028863, 0.064847, 0.067587, 0.083073, 0.115488",\ + "0.056460, 0.078305, 0.086593, 0.102413, 0.134994",\ + "0.368605, 0.368605, 0.369807, 0.373448, 0.381327",\ + "1.000406, 1.000406, 1.002130, 1.003829, 1.006481",\ + "0.019992, 0.058113, 0.075846, 0.080346, 0.107536",\ + "0.031388, 0.064955, 0.067602, 0.083112, 0.115566",\ + "0.058257, 0.078397, 0.086610, 0.102452, 0.135073",\ + "0.368605, 0.368605, 0.369809, 0.373458, 0.381346",\ + "1.000406, 1.000406, 1.002134, 1.003832, 1.006488",\ + "0.035969, 0.049040, 0.064123, 0.080374, 0.107616",\ + "0.047452, 0.060595, 0.067604, 0.083146, 0.115661",\ + "0.069690, 0.079044, 0.086613, 0.102486, 0.135168",\ + "0.368605, 0.368605, 0.369810, 0.373466, 0.381369",\ + "1.000406, 1.000406, 1.002134, 1.003835, 1.006495"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2285*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.431291, 0.619330, 0.796158, 1.080125, 1.629897",\ + "0.450507, 0.638547, 0.815375, 1.099342, 1.649114",\ + "0.482156, 0.670196, 0.847024, 1.130990, 1.680763",\ + "0.772737, 0.960778, 1.137606, 1.421573, 1.971346",\ + "1.366740, 1.554780, 1.731609, 2.015576, 2.565349",\ + "0.519710, 0.706648, 0.883439, 1.167430, 1.717251",\ + "0.538927, 0.725865, 0.902656, 1.186647, 1.736468",\ + "0.570576, 0.757514, 0.934305, 1.218296, 1.768116",\ + "0.861157, 1.048096, 1.224887, 1.508878, 2.058700",\ + "1.455159, 1.642098, 1.818890, 2.102881, 2.652703",\ + "0.609345, 0.786979, 0.963466, 1.247459, 1.797282",\ + "0.628561, 0.806196, 0.982683, 1.266675, 1.816499",\ + "0.660210, 0.837845, 1.014332, 1.298324, 1.848148",\ + "0.950791, 1.128427, 1.304914, 1.588907, 2.138731",\ + "1.544794, 1.722429, 1.898916, 2.182909, 2.732734",\ + "0.668670, 0.844800, 1.021158, 1.304875, 1.854273",\ + "0.687887, 0.864017, 1.040374, 1.324092, 1.873490",\ + "0.719535, 0.895665, 1.072023, 1.355741, 1.905138",\ + "1.010116, 1.186247, 1.362605, 1.646324, 2.195722",\ + "1.604119, 1.780250, 1.956608, 2.240326, 2.789725",\ + "0.971362, 1.150042, 1.324812, 1.608036, 2.156464",\ + "0.990578, 1.169258, 1.344029, 1.627252, 2.175681",\ + "1.022227, 1.200907, 1.375677, 1.658901, 2.207329",\ + "1.312808, 1.491489, 1.666260, 1.949484, 2.497913",\ + "1.906811, 2.085492, 2.260262, 2.543486, 3.091916"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\ + "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\ + "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\ + "0.115194, 0.115201, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367",\ + "0.115195, 0.115202, 0.115205, 0.115209, 0.115217",\ + "0.141976, 0.141976, 0.141976, 0.141975, 0.141974",\ + "0.190577, 0.190577, 0.190577, 0.190577, 0.190576",\ + "0.817535, 0.817535, 0.817535, 0.817534, 0.817534",\ + "2.193374, 2.193372, 2.193371, 2.193370, 2.193367"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.443689, 0.631730, 0.808559, 1.092526, 1.642300",\ + "0.451495, 0.639537, 0.816365, 1.100333, 1.650107",\ + "0.464877, 0.652918, 0.829747, 1.113715, 1.663489",\ + "0.616830, 0.804870, 0.981699, 1.265666, 1.815439",\ + "0.950269, 1.138309, 1.315137, 1.599104, 2.148877",\ + "0.532108, 0.719048, 0.895840, 1.179832, 1.729654",\ + "0.539915, 0.726855, 0.903646, 1.187638, 1.737461",\ + "0.553297, 0.740236, 0.917028, 1.201020, 1.750842",\ + "0.705249, 0.892188, 1.068980, 1.352971, 1.902793",\ + "1.038688, 1.225627, 1.402418, 1.686409, 2.236230",\ + "0.621743, 0.799379, 0.975867, 1.259860, 1.809685",\ + "0.629550, 0.807186, 0.983673, 1.267667, 1.817492",\ + "0.642931, 0.820567, 0.997055, 1.281049, 1.830874",\ + "0.794884, 0.972519, 1.149006, 1.432999, 1.982824",\ + "1.128323, 1.305958, 1.482445, 1.766438, 2.316262",\ + "0.681068, 0.857200, 1.033558, 1.317277, 1.866676",\ + "0.688875, 0.865006, 1.041365, 1.325083, 1.874483",\ + "0.702257, 0.878388, 1.054746, 1.338465, 1.887864",\ + "0.854209, 1.030340, 1.206698, 1.490416, 2.039815",\ + "1.187648, 1.363779, 1.540136, 1.823854, 2.373252",\ + "0.983760, 1.162441, 1.337212, 1.620437, 2.168867",\ + "0.991567, 1.170248, 1.345019, 1.628244, 2.176674",\ + "1.004948, 1.183630, 1.358401, 1.641625, 2.190056",\ + "1.156901, 1.335582, 1.510352, 1.793576, 2.342006",\ + "1.490340, 1.669020, 1.843791, 2.127015, 2.675444"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263",\ + "0.049719, 0.049719, 0.049720, 0.049720, 0.049720",\ + "0.055444, 0.055444, 0.055444, 0.055444, 0.055444",\ + "0.075302, 0.075302, 0.075302, 0.075302, 0.075302",\ + "0.368591, 0.368591, 0.368591, 0.368591, 0.368591",\ + "1.002263, 1.002263, 1.002263, 1.002263, 1.002263"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[7]_redg_min_2529*/ + +} /* end of pin tl_o[7] */ + +pin("tl_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.154883 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.555603, 0.806076, 1.084885, 1.584808, 2.584653",\ + "0.589996, 0.840470, 1.119283, 1.619221, 2.619098",\ + "0.661233, 0.911707, 1.190508, 1.690407, 2.690205",\ + "0.915400, 1.165873, 1.444750, 1.944912, 2.945236",\ + "1.840005, 2.090481, 2.369305, 2.869275, 3.869217",\ + "0.643016, 0.893581, 1.172550, 1.671522, 2.670587",\ + "0.677409, 0.927975, 1.206949, 1.705936, 2.705032",\ + "0.748646, 0.999212, 1.278174, 1.777122, 2.776139",\ + "1.002812, 1.253378, 1.532416, 2.031627, 3.031170",\ + "1.927417, 2.177986, 2.456970, 2.955990, 3.955151",\ + "0.723872, 0.982469, 1.260517, 1.759145, 2.757542",\ + "0.758265, 1.016862, 1.294915, 1.793559, 2.791987",\ + "0.829503, 1.088099, 1.366140, 1.864744, 2.863094",\ + "1.083669, 1.342266, 1.620383, 2.119249, 3.118125",\ + "2.008274, 2.266873, 2.544936, 3.043612, 4.042106",\ + "0.781752, 1.047969, 1.324661, 1.823058, 2.821051",\ + "0.816145, 1.082362, 1.359060, 1.857472, 2.855496",\ + "0.887382, 1.153599, 1.430285, 1.928658, 2.926603",\ + "1.141549, 1.407765, 1.684527, 2.183163, 3.181634",\ + "2.066154, 2.332373, 2.609081, 3.107526, 4.105615",\ + "1.114573, 1.410746, 1.676844, 2.172535, 3.166507",\ + "1.148966, 1.445139, 1.711242, 2.206949, 3.200952",\ + "1.220203, 1.516376, 1.782467, 2.278135, 3.272059",\ + "1.474370, 1.770542, 2.036712, 2.532641, 3.527090",\ + "2.398975, 2.695150, 2.961264, 3.457003, 4.451071"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466091, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465199, 2.466100, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083750, 0.083751, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692766, 0.692810, 0.692941, 0.693203",\ + "2.465173, 2.465200, 2.466101, 2.469060, 2.474999",\ + "0.034112, 0.034113, 0.034114, 0.034119, 0.034130",\ + "0.083751, 0.083752, 0.083761, 0.083790, 0.083849",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692761, 0.692768, 0.692812, 0.692941, 0.693203",\ + "2.465173, 2.465210, 2.466131, 2.469072, 2.474999"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.587400, 0.837877, 1.116297, 1.614862, 2.611990",\ + "0.629152, 0.879628, 1.158099, 1.656840, 2.654322",\ + "0.689082, 0.939558, 1.218080, 1.716996, 2.714829",\ + "0.857199, 1.107675, 1.386266, 1.885427, 2.883749",\ + "1.439229, 1.689714, 1.968424, 2.467974, 3.467073",\ + "0.674813, 0.925382, 1.203958, 1.701576, 2.697924",\ + "0.716564, 0.967133, 1.245761, 1.743555, 2.740255",\ + "0.776495, 1.027063, 1.305742, 1.803711, 2.800763",\ + "0.944611, 1.195180, 1.473930, 1.972142, 2.969683",\ + "1.526642, 1.777219, 2.056088, 2.554689, 3.553007",\ + "0.755670, 1.014269, 1.291924, 1.789199, 2.784879",\ + "0.797421, 1.056020, 1.333727, 1.831177, 2.827210",\ + "0.857352, 1.115951, 1.393708, 1.891333, 2.887718",\ + "1.025468, 1.284067, 1.561896, 2.059765, 3.056638",\ + "1.607499, 1.866107, 2.144055, 2.642311, 3.639962",\ + "0.813550, 1.079769, 1.356069, 1.853112, 2.848388",\ + "0.855301, 1.121520, 1.397871, 1.895091, 2.890719",\ + "0.915231, 1.181451, 1.457853, 1.955247, 2.951227",\ + "1.083348, 1.349567, 1.626040, 2.123678, 3.120147",\ + "1.665379, 1.931606, 2.208199, 2.706225, 3.703471",\ + "1.146371, 1.442547, 1.708238, 2.202584, 3.193844",\ + "1.188122, 1.484298, 1.750042, 2.244563, 3.236176",\ + "1.248053, 1.544228, 1.810025, 2.304720, 3.296683",\ + "1.416169, 1.712345, 1.978215, 2.473152, 3.465603",\ + "1.998202, 2.294386, 2.560378, 3.055700, 4.048927"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045875, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155803, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195",\ + "0.045876, 0.045874, 0.045861, 0.045821, 0.045741",\ + "0.079914, 0.079913, 0.079913, 0.079910, 0.079906",\ + "0.155804, 0.155802, 0.155792, 0.155761, 0.155698",\ + "0.431307, 0.431307, 0.431304, 0.431297, 0.431282",\ + "1.494119, 1.494120, 1.494128, 1.494150, 1.494195"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2615*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.674108, 0.912583, 1.208888, 1.707377, 2.704357",\ + "0.708540, 0.947015, 1.243320, 1.741811, 2.738792",\ + "0.779534, 1.018009, 1.314315, 1.812807, 2.809791",\ + "1.033699, 1.272174, 1.568481, 2.066974, 3.063961",\ + "1.958883, 2.197359, 2.493670, 2.992175, 3.989184",\ + "0.761549, 1.000192, 1.296551, 1.794093, 2.790291",\ + "0.795981, 1.034624, 1.330983, 1.828526, 2.824726",\ + "0.866976, 1.105618, 1.401978, 1.899523, 2.895725",\ + "1.121141, 1.359783, 1.656144, 2.153690, 3.149894",\ + "2.046324, 2.284967, 2.581333, 3.078891, 4.075118",\ + "0.842432, 1.089339, 1.384517, 1.881716, 2.877246",\ + "0.876864, 1.123771, 1.418950, 1.916149, 2.911681",\ + "0.947859, 1.194765, 1.489945, 1.987146, 2.982680",\ + "1.202024, 1.448930, 1.744111, 2.241313, 3.236850",\ + "2.127208, 2.374115, 2.669300, 3.166513, 4.162073",\ + "0.900159, 1.155216, 1.448662, 1.945630, 2.940755",\ + "0.934591, 1.189648, 1.483094, 1.980063, 2.975190",\ + "1.005585, 1.260643, 1.554090, 2.051059, 3.046189",\ + "1.259750, 1.514808, 1.808255, 2.305226, 3.300359",\ + "2.184934, 2.439992, 2.733444, 3.230427, 4.225582",\ + "1.202901, 1.522357, 1.800832, 2.295105, 3.286211",\ + "1.237333, 1.556789, 1.835264, 2.329538, 3.320646",\ + "1.308327, 1.627784, 1.906260, 2.400534, 3.391645",\ + "1.562492, 1.881949, 2.160425, 2.654701, 3.645814",\ + "2.487676, 2.807133, 3.085615, 3.579902, 4.571038"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\ + "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\ + "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\ + "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693282, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470761, 2.470771, 2.470795, 2.470844",\ + "0.034241, 0.034241, 0.034241, 0.034244, 0.034249",\ + "0.083584, 0.083584, 0.083586, 0.083591, 0.083602",\ + "0.208067, 0.208067, 0.208069, 0.208073, 0.208081",\ + "0.693279, 0.693283, 0.693285, 0.693285, 0.693285",\ + "2.470759, 2.470762, 2.470771, 2.470795, 2.470844"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.701144, 0.939619, 1.235924, 1.734413, 2.731392",\ + "0.743441, 0.981916, 1.278220, 1.776710, 2.773689",\ + "0.804003, 1.042478, 1.338783, 1.837273, 2.834251",\ + "0.972934, 1.211409, 1.507714, 2.006203, 3.003182",\ + "1.556185, 1.794660, 2.090965, 2.589454, 3.586433",\ + "0.788586, 1.027228, 1.323587, 1.821129, 2.817326",\ + "0.830882, 1.069525, 1.365883, 1.863425, 2.859622",\ + "0.891445, 1.130087, 1.426446, 1.923988, 2.920185",\ + "1.060375, 1.299018, 1.595377, 2.092919, 3.089116",\ + "1.643626, 1.882269, 2.178628, 2.676170, 3.672367",\ + "0.869469, 1.116375, 1.411554, 1.908752, 2.904281",\ + "0.911765, 1.158672, 1.453850, 1.951048, 2.946578",\ + "0.972328, 1.219234, 1.514413, 2.011611, 3.007140",\ + "1.141259, 1.388165, 1.683344, 2.180542, 3.176071",\ + "1.724510, 1.971416, 2.266594, 2.763793, 3.759322",\ + "0.927195, 1.182252, 1.475698, 1.972666, 2.967790",\ + "0.969492, 1.224549, 1.517995, 2.014962, 3.010087",\ + "1.030054, 1.285111, 1.578557, 2.075525, 3.070649",\ + "1.198985, 1.454042, 1.747488, 2.244456, 3.239580",\ + "1.782236, 2.037293, 2.330739, 2.827706, 3.822831",\ + "1.229937, 1.549393, 1.827868, 2.322140, 3.313246",\ + "1.272233, 1.591690, 1.870165, 2.364437, 3.355543",\ + "1.332796, 1.652252, 1.930727, 2.424999, 3.416105",\ + "1.501727, 1.821183, 2.099658, 2.593930, 3.585036",\ + "2.084978, 2.404434, 2.682909, 3.177181, 4.168287"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\ + "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\ + "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\ + "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498063, 1.498063, 1.498062",\ + "0.045859, 0.045859, 0.045858, 0.045858, 0.045857",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155685, 0.155685, 0.155685, 0.155685",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498063, 1.498063, 1.498063, 1.498062"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2662*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.445529, 0.709512, 0.994214, 1.487610, 2.474404",\ + "0.486774, 0.750744, 1.035473, 1.529006, 2.516072",\ + "0.562671, 0.826637, 1.111362, 1.604919, 2.592032",\ + "0.817960, 1.082041, 1.366717, 1.860078, 2.846800",\ + "1.742890, 2.007130, 2.292228, 2.786041, 3.773666",\ + "0.532938, 0.797075, 1.081856, 1.574325, 2.560338",\ + "0.574183, 0.838307, 1.123116, 1.615720, 2.602005",\ + "0.650079, 0.914199, 1.199006, 1.691633, 2.677966",\ + "0.905369, 1.169603, 1.454359, 1.946792, 2.932734",\ + "1.830298, 2.094694, 2.379872, 2.872755, 3.859600",\ + "0.616182, 0.886074, 1.169821, 1.661946, 2.647293",\ + "0.657426, 0.927306, 1.211081, 1.703342, 2.688961",\ + "0.733323, 1.003198, 1.286970, 1.779255, 2.764921",\ + "0.988623, 1.258602, 1.542324, 2.034413, 3.019689",\ + "1.913549, 2.183697, 2.467836, 2.960376, 3.946555",\ + "0.679766, 0.951735, 1.233965, 1.725859, 2.710802",\ + "0.721010, 0.992966, 1.275225, 1.767255, 2.752470",\ + "0.796907, 1.068859, 1.351114, 1.843168, 2.828430",\ + "1.052215, 1.324263, 1.606468, 2.098326, 3.083198",\ + "1.977138, 2.249364, 2.531980, 3.024289, 4.010064",\ + "1.015779, 1.316457, 1.586079, 2.075305, 3.056258",\ + "1.057021, 1.357686, 1.627340, 2.116701, 3.097925",\ + "1.132920, 1.433575, 1.703230, 2.192614, 3.173886",\ + "1.388277, 1.688981, 1.958581, 2.447772, 3.428654",\ + "2.313181, 2.614154, 2.884099, 3.373737, 4.355520"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.034901, 0.034921, 0.035051, 0.035499, 0.036393",\ + "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\ + "0.208547, 0.208578, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692580, 0.692833, 0.693579, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\ + "0.034901, 0.034921, 0.035053, 0.035499, 0.036393",\ + "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\ + "0.208547, 0.208579, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692580, 0.692835, 0.693579, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\ + "0.034903, 0.034921, 0.035053, 0.035499, 0.036393",\ + "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\ + "0.208547, 0.208579, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692581, 0.692835, 0.693579, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\ + "0.034905, 0.034921, 0.035053, 0.035499, 0.036393",\ + "0.083287, 0.083291, 0.083337, 0.083496, 0.083813",\ + "0.208547, 0.208580, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692581, 0.692835, 0.693579, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533",\ + "0.034914, 0.034921, 0.035057, 0.035500, 0.036393",\ + "0.083289, 0.083291, 0.083339, 0.083496, 0.083813",\ + "0.208549, 0.208590, 0.208621, 0.208624, 0.208631",\ + "0.692555, 0.692590, 0.692843, 0.693582, 0.695072",\ + "2.479533, 2.479533, 2.479533, 2.479533, 2.479533"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.491807, 0.755750, 1.040134, 1.532324, 2.516704",\ + "0.532692, 0.796638, 1.081002, 1.573128, 2.557379",\ + "0.593088, 0.857084, 1.141423, 1.633441, 2.617476",\ + "0.762034, 1.026038, 1.310351, 1.802328, 2.786283",\ + "1.345402, 1.609523, 1.893616, 2.385030, 3.367858",\ + "0.579215, 0.843313, 1.127773, 1.619038, 2.602638",\ + "0.620100, 0.884201, 1.168641, 1.659842, 2.643312",\ + "0.680497, 0.944646, 1.229061, 1.720155, 2.703410",\ + "0.849443, 1.113601, 1.397989, 1.889042, 2.872216",\ + "1.432811, 1.697085, 1.981253, 2.471745, 3.453792",\ + "0.662453, 0.932313, 1.215738, 1.706660, 2.689593",\ + "0.703338, 0.973200, 1.256606, 1.747463, 2.730268",\ + "0.763739, 1.033646, 1.317026, 1.807776, 2.790365",\ + "0.932687, 1.202600, 1.485954, 1.976664, 2.959171",\ + "1.516071, 1.786084, 2.069218, 2.559366, 3.540747",\ + "0.726033, 0.997974, 1.279881, 1.770573, 2.753102",\ + "0.766918, 1.038862, 1.320749, 1.811376, 2.793777",\ + "0.827322, 1.099308, 1.381169, 1.871690, 2.853874",\ + "0.996272, 1.268262, 1.550097, 2.040577, 3.022680",\ + "1.579666, 1.851744, 2.133361, 2.623279, 3.604256",\ + "1.062019, 1.362705, 1.631983, 2.120014, 3.098558",\ + "1.102906, 1.403592, 1.672850, 2.160817, 3.139233",\ + "1.163330, 1.464039, 1.733269, 2.221130, 3.199330",\ + "1.332287, 1.632990, 1.902197, 2.390017, 3.368136",\ + "1.915751, 2.216458, 2.485455, 2.972717, 3.949712"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\ + "1.494840, 1.494148, 1.493909, 1.493909, 1.493909",\ + "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\ + "1.494840, 1.494147, 1.493909, 1.493909, 1.493909",\ + "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\ + "1.494787, 1.494143, 1.493909, 1.493909, 1.493909",\ + "0.042675, 0.042675, 0.042652, 0.042575, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155277, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431011, 0.430859, 0.430555",\ + "1.494750, 1.494138, 1.493909, 1.493909, 1.493909",\ + "0.042675, 0.042675, 0.042651, 0.042574, 0.042419",\ + "0.078931, 0.078931, 0.078931, 0.078931, 0.078931",\ + "0.155291, 0.155291, 0.155276, 0.155229, 0.155132",\ + "0.431055, 0.431055, 0.431009, 0.430858, 0.430555",\ + "1.494514, 1.494079, 1.493909, 1.493909, 1.493909"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2660*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.327672, 0.566275, 0.848132, 1.348276, 2.348564",\ + "0.368967, 0.607415, 0.888608, 1.386404, 2.381997",\ + "0.444897, 0.683231, 0.964015, 1.460342, 2.452995",\ + "0.700493, 0.938416, 1.218620, 1.714868, 2.707363",\ + "1.624950, 1.862182, 2.144032, 2.639823, 3.631406",\ + "0.415085, 0.653799, 0.935798, 1.434991, 2.434498",\ + "0.456380, 0.694939, 0.976266, 1.473119, 2.467931",\ + "0.532309, 0.770755, 1.051669, 1.547057, 2.538929",\ + "0.787906, 1.025936, 1.306274, 1.801582, 2.793297",\ + "1.712363, 1.949714, 2.231684, 2.726538, 3.717340",\ + "0.495952, 0.742730, 1.023765, 1.522613, 2.521453",\ + "0.537247, 0.783870, 1.064233, 1.560741, 2.554886",\ + "0.613176, 0.859686, 1.139635, 1.634679, 2.625884",\ + "0.868772, 1.114859, 1.394240, 1.889205, 2.880252",\ + "1.793228, 2.038663, 2.319650, 2.814160, 3.804295",\ + "0.553602, 0.808292, 1.087909, 1.586527, 2.584962",\ + "0.594896, 0.849433, 1.128377, 1.624655, 2.618395",\ + "0.670825, 0.925249, 1.203779, 1.698593, 2.689393",\ + "0.926420, 1.180411, 1.458384, 1.953118, 2.943761",\ + "1.850875, 2.104251, 2.383794, 2.878074, 3.867804",\ + "0.871915, 1.171803, 1.440094, 1.936005, 2.930418",\ + "0.913062, 1.212946, 1.480538, 1.974123, 2.963851",\ + "0.988827, 1.288766, 1.555925, 2.048055, 3.034849",\ + "1.244293, 1.543790, 1.810529, 2.302580, 3.289217",\ + "2.167832, 2.468068, 2.735935, 3.227534, 4.213260"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.035017, 0.035017, 0.035948, 0.039191, 0.045676",\ + "0.083549, 0.083549, 0.083882, 0.085042, 0.087361",\ + "0.208718, 0.208718, 0.208873, 0.209414, 0.210496",\ + "0.692609, 0.692819, 0.692927, 0.693071, 0.693361",\ + "2.477031, 2.477031, 2.477147, 2.477551, 2.478359",\ + "0.035017, 0.035017, 0.035958, 0.039191, 0.045676",\ + "0.083549, 0.083549, 0.083886, 0.085042, 0.087361",\ + "0.208718, 0.208718, 0.208875, 0.209414, 0.210496",\ + "0.692609, 0.692819, 0.692927, 0.693071, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477551, 2.478359",\ + "0.035017, 0.035017, 0.035958, 0.039191, 0.045676",\ + "0.083549, 0.083549, 0.083886, 0.085042, 0.087361",\ + "0.208718, 0.208718, 0.208875, 0.209414, 0.210496",\ + "0.692610, 0.692820, 0.692927, 0.693071, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477551, 2.478359",\ + "0.035017, 0.035017, 0.035959, 0.039191, 0.045676",\ + "0.083549, 0.083549, 0.083886, 0.085042, 0.087361",\ + "0.208718, 0.208718, 0.208875, 0.209414, 0.210496",\ + "0.692612, 0.692821, 0.692927, 0.693071, 0.693361",\ + "2.477031, 2.477031, 2.477149, 2.477551, 2.478359",\ + "0.035017, 0.035017, 0.035992, 0.039204, 0.045676",\ + "0.083549, 0.083549, 0.083898, 0.085047, 0.087361",\ + "0.208718, 0.208718, 0.208880, 0.209416, 0.210496",\ + "0.692710, 0.692838, 0.692928, 0.693072, 0.693361",\ + "2.477031, 2.477031, 2.477153, 2.477553, 2.478359"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.374541, 0.613195, 0.891051, 1.377355, 2.349964",\ + "0.415440, 0.654096, 0.931703, 1.416730, 2.386785",\ + "0.475586, 0.714339, 0.991271, 1.473856, 2.439025",\ + "0.644564, 0.883292, 1.159558, 1.639742, 2.600112",\ + "1.227810, 1.464706, 1.741320, 2.221670, 3.182369",\ + "0.461954, 0.700719, 0.978673, 1.464070, 2.435898",\ + "0.502853, 0.741620, 1.019321, 1.503445, 2.472719",\ + "0.562998, 0.801863, 1.078882, 1.560571, 2.524959",\ + "0.731977, 0.970816, 1.247161, 1.726457, 2.686046",\ + "1.315223, 1.552233, 1.828923, 2.308385, 3.268303",\ + "0.542824, 0.789649, 1.066638, 1.551692, 2.522853",\ + "0.583722, 0.830553, 1.107287, 1.591067, 2.559674",\ + "0.643867, 0.890796, 1.166847, 1.648193, 2.611914",\ + "0.812844, 1.059749, 1.335126, 1.814080, 2.773001",\ + "1.396076, 1.641170, 1.916889, 2.396007, 3.355258",\ + "0.600479, 0.855211, 1.130781, 1.615606, 2.586362",\ + "0.641375, 0.896117, 1.171429, 1.654981, 2.623183",\ + "0.701520, 0.956361, 1.230989, 1.712107, 2.675423",\ + "0.870493, 1.125315, 1.399267, 1.877993, 2.836510",\ + "1.453700, 1.706742, 1.981030, 2.459920, 3.418767",\ + "0.918806, 1.218716, 1.482825, 1.965026, 2.931818",\ + "0.959736, 1.259650, 1.523460, 2.004396, 2.968639",\ + "1.019894, 1.319901, 1.582996, 2.061512, 3.020879",\ + "1.188870, 1.488860, 1.751250, 2.227388, 3.181966",\ + "1.770179, 2.070362, 2.333014, 2.809316, 3.764223"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.042685, 0.042786, 0.042938, 0.042938, 0.042938",\ + "0.078477, 0.079297, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042787, 0.042938, 0.042938, 0.042938",\ + "0.078477, 0.079298, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042789, 0.042938, 0.042938, 0.042938",\ + "0.078482, 0.079299, 0.079365, 0.079365, 0.079365",\ + "0.155270, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042792, 0.042938, 0.042938, 0.042938",\ + "0.078491, 0.079300, 0.079365, 0.079365, 0.079365",\ + "0.155271, 0.155314, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069",\ + "0.042685, 0.042830, 0.042938, 0.042938, 0.042938",\ + "0.078951, 0.079317, 0.079365, 0.079365, 0.079365",\ + "0.155294, 0.155316, 0.155322, 0.155322, 0.155322",\ + "0.431181, 0.431181, 0.431181, 0.431181, 0.431181",\ + "1.494069, 1.494069, 1.494069, 1.494069, 1.494069"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2717*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.430110, 0.674363, 0.945987, 1.398684, 2.304079",\ + "0.471359, 0.715604, 0.987211, 1.439891, 2.345252",\ + "0.547252, 0.791500, 1.063102, 1.515754, 2.421058",\ + "0.802426, 1.046828, 1.318547, 1.770909, 2.675633",\ + "1.727400, 1.971804, 2.243712, 2.696691, 3.602648",\ + "0.517512, 0.761931, 1.033499, 1.485397, 2.390012",\ + "0.558762, 0.803171, 1.074723, 1.526605, 2.431185",\ + "0.634655, 0.879067, 1.150614, 1.602467, 2.506991",\ + "0.889829, 1.134397, 1.406058, 1.857622, 2.761567",\ + "1.814803, 2.059373, 2.331226, 2.783404, 3.688582",\ + "0.598336, 0.850913, 1.121461, 1.573018, 2.476967",\ + "0.639585, 0.892153, 1.162685, 1.614225, 2.518140",\ + "0.715478, 0.968049, 1.238575, 1.690088, 2.593946",\ + "0.970652, 1.223382, 1.494019, 1.945243, 2.848522",\ + "1.895626, 2.148358, 2.419187, 2.871025, 3.775537",\ + "0.655998, 0.916548, 1.185597, 1.636931, 2.540476",\ + "0.697247, 0.957788, 1.226822, 1.678138, 2.581649",\ + "0.773140, 1.033684, 1.302712, 1.754000, 2.657455",\ + "1.028314, 1.289021, 1.558156, 2.009156, 2.912031",\ + "1.953288, 2.213997, 2.483324, 2.934937, 3.839046",\ + "0.986976, 1.281046, 1.537295, 1.986203, 2.885932",\ + "1.028225, 1.322284, 1.578519, 2.027411, 2.927105",\ + "1.104119, 1.398180, 1.654409, 2.103273, 3.002912",\ + "1.359298, 1.653568, 1.909851, 2.358427, 3.257487",\ + "2.284269, 2.578546, 2.835025, 3.284211, 4.184502"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.034880, 0.034905, 0.035033, 0.035354, 0.035995",\ + "0.083283, 0.083287, 0.083329, 0.083448, 0.083687",\ + "0.208545, 0.208582, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692841, 0.693640, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\ + "0.034880, 0.034906, 0.035034, 0.035354, 0.035995",\ + "0.083283, 0.083287, 0.083329, 0.083448, 0.083687",\ + "0.208545, 0.208582, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692844, 0.693640, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\ + "0.034880, 0.034906, 0.035034, 0.035354, 0.035995",\ + "0.083283, 0.083288, 0.083329, 0.083448, 0.083687",\ + "0.208545, 0.208582, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692844, 0.693640, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\ + "0.034880, 0.034907, 0.035034, 0.035354, 0.035995",\ + "0.083283, 0.083288, 0.083329, 0.083448, 0.083687",\ + "0.208546, 0.208583, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692844, 0.693640, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823",\ + "0.034881, 0.034915, 0.035037, 0.035355, 0.035995",\ + "0.083283, 0.083289, 0.083330, 0.083449, 0.083687",\ + "0.208552, 0.208592, 0.208618, 0.208622, 0.208628",\ + "0.692606, 0.692606, 0.692852, 0.693643, 0.695237",\ + "2.479823, 2.479823, 2.479823, 2.479823, 2.479823"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.476452, 0.720627, 0.992222, 1.445174, 2.351079",\ + "0.517334, 0.761513, 1.033104, 1.486024, 2.391864",\ + "0.577683, 0.821926, 1.093569, 1.546380, 2.452001",\ + "0.746610, 0.990875, 1.262519, 1.715235, 2.620666",\ + "1.329814, 1.574285, 1.846012, 2.298098, 3.202269",\ + "0.563855, 0.808193, 1.079735, 1.531888, 2.437013",\ + "0.604736, 0.849079, 1.120617, 1.572738, 2.477798",\ + "0.665086, 0.909493, 1.181081, 1.633093, 2.537935",\ + "0.834013, 1.078442, 1.350031, 1.801948, 2.706600",\ + "1.417216, 1.661854, 1.933522, 2.384811, 3.288203",\ + "0.644678, 0.897174, 1.167696, 1.619509, 2.523968",\ + "0.685559, 0.938060, 1.208579, 1.660358, 2.564753",\ + "0.745909, 0.998475, 1.269043, 1.720713, 2.624890",\ + "0.914836, 1.167425, 1.437993, 1.889569, 2.793555",\ + "1.498040, 1.750840, 2.021483, 2.472431, 3.375158",\ + "0.702340, 0.962807, 1.231833, 1.683421, 2.587477",\ + "0.743221, 1.003693, 1.272716, 1.724271, 2.628262",\ + "0.803571, 1.064109, 1.333179, 1.784626, 2.688399",\ + "0.972498, 1.233060, 1.502129, 1.953481, 2.857064",\ + "1.555702, 1.816481, 2.085620, 2.536344, 3.438667",\ + "1.033316, 1.327279, 1.583534, 2.032695, 2.932933",\ + "1.074197, 1.368167, 1.624416, 2.073545, 2.973718",\ + "1.134549, 1.428604, 1.684879, 2.133899, 3.033855",\ + "1.303477, 1.597562, 1.853827, 2.302754, 3.202520",\ + "1.886688, 2.181050, 2.437312, 2.885614, 3.784123"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\ + "0.431084, 0.431084, 0.431042, 0.430897, 0.430607",\ + "1.495395, 1.494888, 1.494241, 1.494241, 1.494241",\ + "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\ + "0.431084, 0.431084, 0.431041, 0.430897, 0.430607",\ + "1.495395, 1.494883, 1.494241, 1.494241, 1.494241",\ + "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\ + "0.431084, 0.431084, 0.431041, 0.430897, 0.430607",\ + "1.495394, 1.494874, 1.494241, 1.494241, 1.494241",\ + "0.042687, 0.042687, 0.042669, 0.042608, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155281, 0.155232, 0.155132",\ + "0.431084, 0.431084, 0.431041, 0.430897, 0.430607",\ + "1.495394, 1.494860, 1.494241, 1.494241, 1.494241",\ + "0.042687, 0.042687, 0.042668, 0.042607, 0.042485",\ + "0.078970, 0.078970, 0.078967, 0.078960, 0.078944",\ + "0.155296, 0.155296, 0.155280, 0.155231, 0.155132",\ + "0.431084, 0.431084, 0.431040, 0.430896, 0.430607",\ + "1.495370, 1.494698, 1.494241, 1.494241, 1.494241"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.554256, 0.796472, 1.062238, 1.540435, 2.496829",\ + "0.588688, 0.830904, 1.096670, 1.574875, 2.531283",\ + "0.659682, 0.901899, 1.167669, 1.645892, 2.602338",\ + "0.913848, 1.156064, 1.421858, 1.900173, 2.856801",\ + "1.839032, 2.081247, 2.347044, 2.825424, 3.782184",\ + "0.641661, 0.883946, 1.149831, 1.627148, 2.582762",\ + "0.676093, 0.918377, 1.184264, 1.661588, 2.617217",\ + "0.747088, 0.989372, 1.255262, 1.732605, 2.688272",\ + "1.001253, 1.243537, 1.509452, 1.986886, 2.942735",\ + "1.926437, 2.168720, 2.434638, 2.912138, 3.868118",\ + "0.722474, 0.972733, 1.237795, 1.714769, 2.669717",\ + "0.756906, 1.007164, 1.272227, 1.749209, 2.704172",\ + "0.827901, 1.078159, 1.343225, 1.820227, 2.775227",\ + "1.082066, 1.332324, 1.597415, 2.074507, 3.029690",\ + "2.007250, 2.257506, 2.522601, 2.999759, 3.955073",\ + "0.781555, 1.038084, 1.301936, 1.778682, 2.733226",\ + "0.815987, 1.072516, 1.336368, 1.813122, 2.767681",\ + "0.886982, 1.143511, 1.407367, 1.884140, 2.838736",\ + "1.141147, 1.397675, 1.661557, 2.138420, 3.093199",\ + "2.066333, 2.322857, 2.586742, 3.063672, 4.018582",\ + "1.117315, 1.399225, 1.653894, 2.128062, 3.078682",\ + "1.151748, 1.433656, 1.688326, 2.162502, 3.113137",\ + "1.222743, 1.504651, 1.759325, 2.233520, 3.184192",\ + "1.476909, 1.758815, 2.013515, 2.487801, 3.438655",\ + "2.402100, 2.683993, 2.938702, 3.413052, 4.364038"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.034240, 0.034243, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083624, 0.083701, 0.083855",\ + "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471502, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208072, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471510, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470761, 2.470782, 2.471510, 2.473964, 2.478889",\ + "0.034240, 0.034244, 0.034261, 0.034303, 0.034388",\ + "0.083583, 0.083591, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208073, 0.208099, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470764, 2.470782, 2.471510, 2.473964, 2.478889",\ + "0.034240, 0.034245, 0.034262, 0.034304, 0.034388",\ + "0.083583, 0.083594, 0.083625, 0.083701, 0.083855",\ + "0.208066, 0.208075, 0.208100, 0.208159, 0.208278",\ + "0.693300, 0.693300, 0.693300, 0.693300, 0.693300",\ + "2.470774, 2.470782, 2.471535, 2.473975, 2.478889"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.581292, 0.823509, 1.089276, 1.567480, 2.523887",\ + "0.623589, 0.865805, 1.131530, 1.609589, 2.565706",\ + "0.684151, 0.926368, 1.192030, 1.669873, 2.625559",\ + "0.853082, 1.095299, 1.360884, 1.838464, 2.793625",\ + "1.436333, 1.678550, 1.944122, 2.421657, 3.376727",\ + "0.668697, 0.910982, 1.176870, 1.654194, 2.609821",\ + "0.710994, 0.953278, 1.219123, 1.696303, 2.651640",\ + "0.771556, 1.013841, 1.279622, 1.756587, 2.711493",\ + "0.940487, 1.182772, 1.448475, 1.925178, 2.879559",\ + "1.523738, 1.766023, 2.031713, 2.508370, 3.462660",\ + "0.749510, 0.999769, 1.264833, 1.741815, 2.696776",\ + "0.791807, 1.042065, 1.307087, 1.783924, 2.738595",\ + "0.852369, 1.102628, 1.367586, 1.844208, 2.798448",\ + "1.021300, 1.271559, 1.536439, 2.012799, 2.966514",\ + "1.604551, 1.854810, 2.119677, 2.595992, 3.549615",\ + "0.808591, 1.065121, 1.328974, 1.805728, 2.760285",\ + "0.850888, 1.107417, 1.371228, 1.847837, 2.802104",\ + "0.911450, 1.167980, 1.431727, 1.908121, 2.861957",\ + "1.080381, 1.336911, 1.600580, 2.076712, 3.030023",\ + "1.663632, 1.920162, 2.183818, 2.659904, 3.613124",\ + "1.144351, 1.426262, 1.680932, 2.155108, 3.105741",\ + "1.186648, 1.468558, 1.723184, 2.197216, 3.147560",\ + "1.247211, 1.529121, 1.783681, 2.257499, 3.207412",\ + "1.416141, 1.698051, 1.952531, 2.426090, 3.375479",\ + "1.999392, 2.281302, 2.535769, 3.009282, 3.958580"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045870, 0.045908, 0.045983",\ + "0.079961, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064",\ + "0.045859, 0.045859, 0.045871, 0.045908, 0.045983",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155685, 0.155686, 0.155686, 0.155686, 0.155686",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498064, 1.498064, 1.498064, 1.498064, 1.498064"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2473*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.778393, 1.030571, 1.315131, 1.821345, 2.833774",\ + "0.812784, 1.064961, 1.349521, 1.855736, 2.868164",\ + "0.884026, 1.136204, 1.420765, 1.926979, 2.939408",\ + "1.138193, 1.390371, 1.674931, 2.181146, 3.193574",\ + "2.062764, 2.314940, 2.599499, 3.105713, 4.118140",\ + "0.865806, 1.118101, 1.402816, 1.908060, 2.919708",\ + "0.900196, 1.152491, 1.437207, 1.942451, 2.954098",\ + "0.971439, 1.223734, 1.508450, 2.013694, 3.025342",\ + "1.225605, 1.477901, 1.762616, 2.267860, 3.279508",\ + "2.150177, 2.402470, 2.687184, 3.192428, 4.204074",\ + "0.946677, 1.207046, 1.490783, 1.995683, 3.006663",\ + "0.981067, 1.241436, 1.525173, 2.030073, 3.041053",\ + "1.052310, 1.312679, 1.596416, 2.101316, 3.112297",\ + "1.306477, 1.566845, 1.850583, 2.355483, 3.366463",\ + "2.231048, 2.491415, 2.775151, 3.280050, 4.291029",\ + "1.005325, 1.272628, 1.554929, 2.059596, 3.070172",\ + "1.039716, 1.307018, 1.589319, 2.093987, 3.104562",\ + "1.110958, 1.378261, 1.660562, 2.165230, 3.175806",\ + "1.365125, 1.632428, 1.914729, 2.419396, 3.429972",\ + "2.289696, 2.556998, 2.839297, 3.343963, 4.354538",\ + "1.337288, 1.636376, 1.907175, 2.409100, 3.415628",\ + "1.371678, 1.670766, 1.941566, 2.443490, 3.450018",\ + "1.442921, 1.742009, 2.012809, 2.514733, 3.521262",\ + "1.697088, 1.996176, 2.266975, 2.768899, 3.775428",\ + "2.621658, 2.920745, 3.191543, 3.693467, 4.699994"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083750, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692761, 0.692767",\ + "2.464329, 2.464329, 2.464329, 2.464329, 2.464329"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.810153, 1.062330, 1.346888, 1.853102, 2.865529",\ + "0.851906, 1.104082, 1.388641, 1.894854, 2.907281",\ + "0.911836, 1.164013, 1.448571, 1.954785, 2.967211",\ + "1.079953, 1.332130, 1.616688, 2.122902, 3.135329",\ + "1.661862, 1.914034, 2.198587, 2.704797, 3.717218",\ + "0.897566, 1.149860, 1.434573, 1.939816, 2.951462",\ + "0.939318, 1.191612, 1.476326, 1.981569, 2.993215",\ + "0.999249, 1.251543, 1.536256, 2.041499, 3.053145",\ + "1.167366, 1.419660, 1.704374, 2.209617, 3.221262",\ + "1.749275, 2.001564, 2.286272, 2.791512, 3.803152",\ + "0.978437, 1.238804, 1.522540, 2.027439, 3.038417",\ + "1.020190, 1.280557, 1.564292, 2.069191, 3.080170",\ + "1.080120, 1.340487, 1.624223, 2.129122, 3.140100",\ + "1.248237, 1.508604, 1.792340, 2.297239, 3.308218",\ + "1.830146, 2.090508, 2.374238, 2.879134, 3.890107",\ + "1.037085, 1.304387, 1.586686, 2.091352, 3.101926",\ + "1.078838, 1.346139, 1.628438, 2.133105, 3.143679",\ + "1.138768, 1.406070, 1.688369, 2.193035, 3.203609",\ + "1.306885, 1.574187, 1.856486, 2.361152, 3.371727",\ + "1.888794, 2.156091, 2.438385, 2.943048, 3.953616",\ + "1.369048, 1.668134, 1.938932, 2.440856, 3.447382",\ + "1.410800, 1.709887, 1.980685, 2.482608, 3.489135",\ + "1.470731, 1.769817, 2.040615, 2.542538, 3.549065",\ + "1.638848, 1.937934, 2.208732, 2.710656, 3.717183",\ + "2.220756, 2.519837, 2.790631, 3.292551, 4.299072"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494120"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2603*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.769218, 1.013990, 1.288183, 1.753076, 2.682863",\ + "0.803608, 1.048380, 1.322573, 1.787467, 2.717253",\ + "0.874851, 1.119623, 1.393816, 1.858710, 2.788497",\ + "1.129017, 1.373789, 1.647983, 2.112876, 3.042663",\ + "2.053588, 2.298358, 2.572550, 3.037443, 3.967230",\ + "0.856623, 1.101544, 1.375734, 1.839790, 2.768797",\ + "0.891013, 1.135935, 1.410125, 1.874180, 2.803187",\ + "0.962256, 1.207178, 1.481368, 1.945424, 2.874431",\ + "1.216422, 1.461344, 1.735534, 2.199590, 3.128597",\ + "2.140993, 2.385913, 2.660101, 3.124157, 4.053164",\ + "0.937445, 1.190511, 1.463697, 1.927411, 2.855752",\ + "0.971835, 1.224902, 1.498087, 1.961801, 2.890142",\ + "1.043078, 1.296145, 1.569331, 2.033045, 2.961386",\ + "1.297244, 1.550311, 1.823497, 2.287211, 3.215552",\ + "2.221816, 2.474880, 2.748064, 3.211778, 4.140119",\ + "0.995080, 1.256125, 1.527836, 1.991324, 2.919261",\ + "1.029471, 1.290515, 1.562226, 2.025714, 2.953651",\ + "1.100714, 1.361758, 1.633469, 2.096957, 3.024895",\ + "1.354880, 1.615925, 1.887636, 2.351124, 3.279061",\ + "2.279451, 2.540493, 2.812203, 3.275691, 4.203628",\ + "1.324766, 1.620334, 1.879659, 2.340649, 3.264717",\ + "1.359156, 1.654725, 1.914049, 2.375039, 3.299107",\ + "1.430399, 1.725968, 1.985292, 2.446283, 3.370351",\ + "1.684566, 1.980134, 2.239459, 2.700449, 3.624517",\ + "2.609136, 2.904703, 3.164026, 3.625016, 4.549084"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034113",\ + "0.083750, 0.083750, 0.083750, 0.083751, 0.083752",\ + "0.208404, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692757, 0.692757, 0.692758, 0.692762, 0.692768",\ + "2.464326, 2.464326, 2.464326, 2.464326, 2.464326"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.800978, 1.045748, 1.319939, 1.784832, 2.714618",\ + "0.842730, 1.087500, 1.361691, 1.826584, 2.756371",\ + "0.902660, 1.147430, 1.421622, 1.886515, 2.816301",\ + "1.070778, 1.315548, 1.589739, 2.054632, 2.984419",\ + "1.652686, 1.897449, 2.171633, 2.636526, 3.566311",\ + "0.888383, 1.133302, 1.407490, 1.871546, 2.800552",\ + "0.930135, 1.175055, 1.449243, 1.913298, 2.842305",\ + "0.990066, 1.234985, 1.509173, 1.973228, 2.902235",\ + "1.158183, 1.403102, 1.677290, 2.141346, 3.070352",\ + "1.740091, 1.985004, 2.259185, 2.723239, 3.652244",\ + "0.969205, 1.222269, 1.495453, 1.959167, 2.887507",\ + "1.010957, 1.264022, 1.537205, 2.000919, 2.929260",\ + "1.070888, 1.323952, 1.597136, 2.060850, 2.989190",\ + "1.239005, 1.492069, 1.765253, 2.228967, 3.157307",\ + "1.820914, 2.073971, 2.347147, 2.810860, 3.739199",\ + "1.026840, 1.287883, 1.559592, 2.023079, 2.951016",\ + "1.068593, 1.329635, 1.601344, 2.064832, 2.992769",\ + "1.128523, 1.389565, 1.661275, 2.124762, 3.052699",\ + "1.296640, 1.557683, 1.829392, 2.292880, 3.220816",\ + "1.878549, 2.139584, 2.411286, 2.874773, 3.802708",\ + "1.356526, 1.652092, 1.911415, 2.372405, 3.296472",\ + "1.398278, 1.693844, 1.953167, 2.414157, 3.338225",\ + "1.458209, 1.753775, 2.013098, 2.474087, 3.398155",\ + "1.626326, 1.921892, 2.181215, 2.642205, 3.566272",\ + "2.208233, 2.503792, 2.763109, 3.224098, 4.148165"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121",\ + "0.045877, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494119, 1.494119, 1.494119, 1.494121"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2649*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.634427, 0.872697, 1.149292, 1.635475, 2.607842",\ + "0.668851, 0.907120, 1.183712, 1.669888, 2.642240",\ + "0.739833, 0.978100, 1.254713, 1.740957, 2.713446",\ + "0.993985, 1.232251, 1.508868, 1.995127, 2.967646",\ + "1.919059, 2.157313, 2.433878, 2.919960, 3.892124",\ + "0.721829, 0.960233, 1.236908, 1.722188, 2.693776",\ + "0.756252, 0.994656, 1.271329, 1.756601, 2.728174",\ + "0.827235, 1.065637, 1.342330, 1.827670, 2.799379",\ + "1.081387, 1.319787, 1.596485, 2.081840, 3.053579",\ + "2.006460, 2.244850, 2.521494, 3.006673, 3.978058",\ + "0.802677, 1.049143, 1.324872, 1.809809, 2.780731",\ + "0.837101, 1.083566, 1.359292, 1.844222, 2.815129",\ + "0.908083, 1.154546, 1.430293, 1.915291, 2.886334",\ + "1.162235, 1.408697, 1.684448, 2.169461, 3.140534",\ + "2.087309, 2.333760, 2.609457, 3.094293, 4.065013",\ + "0.860401, 1.114674, 1.389014, 1.873721, 2.844240",\ + "0.894825, 1.149096, 1.423434, 1.908134, 2.878638",\ + "0.965807, 1.220077, 1.494435, 1.979203, 2.949843",\ + "1.219959, 1.474228, 1.748591, 2.233373, 3.204043",\ + "2.145033, 2.399290, 2.673600, 3.158206, 4.128522",\ + "1.188527, 1.477957, 1.741051, 2.223131, 3.189696",\ + "1.222950, 1.512379, 1.775471, 2.257544, 3.224094",\ + "1.293931, 1.583360, 1.846473, 2.328613, 3.295300",\ + "1.548083, 1.837511, 2.100628, 2.582783, 3.549500",\ + "2.473149, 2.762573, 3.025636, 3.507615, 4.473978"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.034240, 0.034240, 0.034242, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083588, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532",\ + "0.034240, 0.034240, 0.034243, 0.034250, 0.034266",\ + "0.083583, 0.083583, 0.083589, 0.083605, 0.083639",\ + "0.208066, 0.208067, 0.208071, 0.208084, 0.208111",\ + "0.693291, 0.693291, 0.693291, 0.693291, 0.693291",\ + "2.470530, 2.470530, 2.470531, 2.470531, 2.470532"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.661467, 0.899737, 1.176348, 1.662586, 2.635063",\ + "0.703763, 0.942033, 1.218582, 1.704611, 2.676670",\ + "0.764325, 1.002595, 1.279082, 1.764899, 2.736534",\ + "0.933255, 1.171525, 1.447944, 1.933534, 2.904712",\ + "1.516509, 1.754779, 2.031088, 2.516304, 3.486737",\ + "0.748868, 0.987273, 1.263965, 1.749299, 2.720997",\ + "0.791164, 1.029569, 1.306198, 1.791324, 2.762603",\ + "0.851727, 1.090131, 1.366697, 1.851612, 2.822468",\ + "1.020657, 1.259062, 1.535559, 2.020247, 2.990646",\ + "1.603910, 1.842315, 2.118701, 2.603017, 3.572671",\ + "0.829717, 1.076183, 1.351928, 1.836920, 2.807952",\ + "0.872012, 1.118479, 1.394161, 1.878945, 2.849558",\ + "0.932575, 1.179041, 1.454660, 1.939233, 2.909423",\ + "1.101505, 1.347972, 1.623522, 2.107867, 3.077601",\ + "1.684759, 1.931225, 2.206665, 2.690638, 3.659626",\ + "0.887441, 1.141714, 1.416070, 1.900832, 2.871461",\ + "0.929737, 1.184009, 1.458303, 1.942857, 2.913067",\ + "0.990299, 1.244572, 1.518803, 2.003145, 2.972932",\ + "1.159229, 1.413502, 1.687665, 2.171780, 3.141110",\ + "1.742483, 1.996755, 2.270807, 2.754550, 3.723135",\ + "1.215567, 1.504997, 1.768108, 2.250242, 3.216917",\ + "1.257862, 1.547292, 1.810339, 2.292266, 3.258523",\ + "1.318425, 1.607855, 1.870836, 2.352553, 3.318388",\ + "1.487355, 1.776785, 2.039696, 2.521187, 3.486566",\ + "2.070609, 2.360038, 2.622834, 3.103956, 4.068591"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067",\ + "0.045862, 0.045862, 0.045862, 0.045862, 0.045862",\ + "0.079960, 0.079960, 0.079960, 0.079960, 0.079960",\ + "0.155688, 0.155688, 0.155688, 0.155688, 0.155688",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498067, 1.498067, 1.498067"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2302*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.679396, 0.938967, 1.226201, 1.725937, 2.725407",\ + "0.713789, 0.973360, 1.260594, 1.760331, 2.759802",\ + "0.785026, 1.044598, 1.331832, 1.831566, 2.831035",\ + "1.039193, 1.298764, 1.585998, 2.085732, 3.085201",\ + "1.963796, 2.223368, 2.510604, 3.010348, 4.009837",\ + "0.766804, 1.026534, 1.313864, 1.812651, 2.811341",\ + "0.801197, 1.060927, 1.348257, 1.847045, 2.845736",\ + "0.872434, 1.132165, 1.419494, 1.918280, 2.916969",\ + "1.126601, 1.386331, 1.673661, 2.172447, 3.171135",\ + "2.051204, 2.310935, 2.598267, 3.097062, 4.095771",\ + "0.847692, 1.115543, 1.401829, 1.900272, 2.898296",\ + "0.882085, 1.149936, 1.436222, 1.934666, 2.932691",\ + "0.953322, 1.221174, 1.507460, 2.005902, 3.003924",\ + "1.207489, 1.475340, 1.761626, 2.260068, 3.258090",\ + "2.132092, 2.399944, 2.686232, 3.184684, 4.182726",\ + "0.908548, 1.181219, 1.465974, 1.964185, 2.961805",\ + "0.942941, 1.215612, 1.500367, 1.998580, 2.996200",\ + "1.014178, 1.286850, 1.571604, 2.069815, 3.067433",\ + "1.268345, 1.541016, 1.825771, 2.323982, 3.321599",\ + "2.192948, 2.465620, 2.750377, 3.248597, 4.246235",\ + "1.244710, 1.546113, 1.818152, 2.313658, 3.307261",\ + "1.279103, 1.580506, 1.852545, 2.348052, 3.341656",\ + "1.350341, 1.651744, 1.923782, 2.419287, 3.412889",\ + "1.604507, 1.905910, 2.177949, 2.673453, 3.667055",\ + "2.529111, 2.830513, 3.102555, 3.598069, 4.591691"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\ + "2.465102, 2.465102, 2.465169, 2.465398, 2.465856",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\ + "2.465102, 2.465102, 2.465170, 2.465398, 2.465856",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\ + "2.465102, 2.465102, 2.465170, 2.465398, 2.465856",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083753, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692762, 0.692776, 0.692813, 0.692889",\ + "2.465102, 2.465102, 2.465170, 2.465398, 2.465856",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034117",\ + "0.083750, 0.083751, 0.083754, 0.083761, 0.083776",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692763, 0.692776, 0.692814, 0.692889",\ + "2.465102, 2.465102, 2.465172, 2.465399, 2.465856"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.711192, 0.970763, 1.257999, 1.757746, 2.757238",\ + "0.752943, 1.012514, 1.299751, 1.799497, 2.798988",\ + "0.812873, 1.072445, 1.359681, 1.859427, 2.858919",\ + "0.980990, 1.240561, 1.527798, 2.027544, 3.027034",\ + "1.563015, 1.822585, 2.109830, 2.609611, 3.609173",\ + "0.798600, 1.058330, 1.345662, 1.844460, 2.843172",\ + "0.840351, 1.100081, 1.387414, 1.886211, 2.884922",\ + "0.900282, 1.160012, 1.447344, 1.946141, 2.944853",\ + "1.068398, 1.328128, 1.615461, 2.114258, 3.112968",\ + "1.650424, 1.910152, 2.197493, 2.696325, 3.695107",\ + "0.879488, 1.147339, 1.433627, 1.932081, 2.930127",\ + "0.921239, 1.189090, 1.475379, 1.973832, 2.971877",\ + "0.981170, 1.249021, 1.535309, 2.033763, 3.031808",\ + "1.149286, 1.417137, 1.703426, 2.201879, 3.199923",\ + "1.731312, 1.999161, 2.285458, 2.783947, 3.782062",\ + "0.940344, 1.213015, 1.497772, 1.995995, 2.993636",\ + "0.982095, 1.254766, 1.539524, 2.037745, 3.035386",\ + "1.042026, 1.314697, 1.599454, 2.097676, 3.095317",\ + "1.210142, 1.482813, 1.767570, 2.265792, 3.263432",\ + "1.792167, 2.064837, 2.349603, 2.847860, 3.845571",\ + "1.276506, 1.577909, 1.849950, 2.345467, 3.339092",\ + "1.318258, 1.619660, 1.891702, 2.387218, 3.380842",\ + "1.378188, 1.679591, 1.951632, 2.447148, 3.440773",\ + "1.546304, 1.847707, 2.119749, 2.615264, 3.608888",\ + "2.128330, 2.429730, 2.701782, 3.197332, 4.191027"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141",\ + "0.045877, 0.045877, 0.045877, 0.045877, 0.045877",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155804, 0.155804, 0.155804, 0.155804, 0.155804",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494119, 1.494120, 1.494122, 1.494128, 1.494141"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2566*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.658633, 0.912014, 1.190716, 1.652421, 2.575833",\ + "0.693026, 0.946407, 1.225109, 1.686815, 2.610227",\ + "0.764264, 1.017644, 1.296346, 1.758051, 2.681462",\ + "1.018430, 1.271811, 1.550512, 2.012218, 2.935628",\ + "1.943034, 2.196414, 2.475117, 2.936828, 3.860250",\ + "0.746043, 0.999594, 1.278259, 1.739136, 2.661767",\ + "0.780436, 1.033988, 1.312652, 1.773529, 2.696161",\ + "0.851673, 1.105225, 1.383889, 1.844766, 2.767396",\ + "1.105840, 1.359391, 1.638056, 2.098932, 3.021562",\ + "2.030443, 2.283995, 2.562661, 3.023543, 3.946184",\ + "0.826857, 1.088640, 1.366222, 1.826758, 2.748722",\ + "0.861250, 1.123033, 1.400615, 1.861151, 2.783116",\ + "0.932488, 1.194270, 1.471853, 1.932387, 2.854351",\ + "1.186654, 1.448437, 1.726019, 2.186554, 3.108517",\ + "2.111258, 2.373040, 2.650624, 3.111165, 4.033139",\ + "0.884438, 1.154368, 1.430361, 1.890671, 2.812231",\ + "0.918831, 1.188761, 1.464754, 1.925064, 2.846625",\ + "0.990068, 1.259999, 1.535991, 1.996301, 2.917860",\ + "1.244235, 1.514165, 1.790157, 2.250467, 3.172026",\ + "2.168839, 2.438769, 2.714763, 3.175078, 4.096648",\ + "1.216287, 1.519868, 1.782153, 2.239986, 3.157687",\ + "1.250680, 1.554260, 1.816547, 2.274380, 3.192081",\ + "1.321917, 1.625498, 1.887784, 2.345616, 3.263316",\ + "1.576084, 1.879665, 2.141950, 2.599783, 3.517482",\ + "2.500688, 2.804268, 3.066556, 3.524393, 4.442104"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692760, 0.692769, 0.692798, 0.692856",\ + "2.465103, 2.465103, 2.465140, 2.465270, 2.465530",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692760, 0.692770, 0.692798, 0.692856",\ + "2.465103, 2.465103, 2.465141, 2.465270, 2.465530",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692760, 0.692770, 0.692798, 0.692856",\ + "2.465103, 2.465103, 2.465141, 2.465270, 2.465530",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692760, 0.692770, 0.692798, 0.692856",\ + "2.465103, 2.465103, 2.465141, 2.465270, 2.465530",\ + "0.034112, 0.034112, 0.034113, 0.034114, 0.034116",\ + "0.083750, 0.083750, 0.083752, 0.083758, 0.083770",\ + "0.208404, 0.208404, 0.208404, 0.208404, 0.208404",\ + "0.692760, 0.692761, 0.692770, 0.692799, 0.692856",\ + "2.465103, 2.465103, 2.465142, 2.465271, 2.465530"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.690429, 0.943810, 1.222513, 1.684225, 2.607649",\ + "0.732181, 0.985561, 1.264264, 1.725976, 2.649400",\ + "0.792111, 1.045491, 1.324195, 1.785906, 2.709330",\ + "0.960228, 1.213608, 1.492311, 1.954023, 2.877446",\ + "1.542253, 1.795633, 2.074341, 2.536073, 3.459536",\ + "0.777839, 1.031390, 1.310056, 1.770939, 2.693583",\ + "0.819590, 1.073142, 1.351808, 1.812690, 2.735333",\ + "0.879520, 1.133072, 1.411738, 1.872621, 2.795264",\ + "1.047637, 1.301189, 1.579854, 2.040737, 2.963380",\ + "1.629662, 1.883214, 2.161885, 2.622787, 3.545470",\ + "0.858653, 1.120436, 1.398020, 1.858561, 2.780538",\ + "0.900405, 1.162187, 1.439771, 1.900312, 2.822289",\ + "0.960335, 1.222118, 1.499701, 1.960243, 2.882219",\ + "1.128451, 1.390234, 1.667818, 2.128359, 3.050335",\ + "1.710477, 1.972259, 2.249848, 2.710409, 3.632425",\ + "0.916234, 1.186164, 1.462158, 1.922474, 2.844047",\ + "0.957985, 1.227916, 1.503910, 1.964226, 2.885798",\ + "1.017915, 1.287846, 1.563840, 2.024156, 2.945728",\ + "1.186032, 1.455963, 1.731956, 2.192272, 3.113844",\ + "1.768058, 2.037988, 2.313987, 2.774323, 3.695934",\ + "1.248083, 1.551663, 1.813951, 2.271790, 3.189503",\ + "1.289834, 1.593415, 1.855702, 2.313541, 3.231254",\ + "1.349765, 1.653345, 1.915633, 2.373471, 3.291184",\ + "1.517881, 1.821462, 2.083749, 2.541588, 3.459300",\ + "2.099906, 2.403486, 2.665780, 3.123638, 4.041390"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\ + "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\ + "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\ + "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135",\ + "0.045877, 0.045876, 0.045874, 0.045865, 0.045847",\ + "0.079914, 0.079914, 0.079913, 0.079913, 0.079912",\ + "0.155804, 0.155804, 0.155802, 0.155795, 0.155781",\ + "0.431307, 0.431307, 0.431306, 0.431305, 0.431302",\ + "1.494119, 1.494119, 1.494121, 1.494126, 1.494135"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2608*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.576605, 0.831535, 1.088524, 1.527728, 2.406135",\ + "0.611028, 0.865958, 1.122948, 1.562156, 2.440572",\ + "0.682011, 0.936939, 1.193932, 1.633147, 2.511575",\ + "0.936163, 1.191091, 1.448086, 1.887307, 2.765749",\ + "1.861240, 2.116160, 2.373173, 2.812451, 3.691008",\ + "0.664013, 0.919020, 1.175996, 1.614442, 2.492069",\ + "0.698437, 0.953443, 1.210420, 1.648871, 2.526506",\ + "0.769419, 1.024424, 1.281404, 1.719861, 2.597509",\ + "1.023571, 1.278576, 1.535558, 1.974021, 2.851683",\ + "1.948648, 2.203645, 2.460645, 2.899166, 3.776942",\ + "0.751657, 1.007845, 1.263958, 1.702063, 2.579024",\ + "0.786080, 1.042268, 1.298382, 1.736492, 2.613461",\ + "0.857063, 1.113249, 1.369366, 1.807482, 2.684464",\ + "1.111215, 1.367401, 1.623520, 2.061643, 2.938638",\ + "2.036291, 2.292470, 2.548607, 2.986787, 3.863897",\ + "0.814841, 1.073252, 1.328092, 1.765976, 2.642533",\ + "0.849265, 1.107675, 1.362517, 1.800405, 2.676970",\ + "0.920247, 1.178657, 1.433500, 1.871395, 2.747973",\ + "1.174399, 1.432808, 1.687654, 2.125556, 3.002147",\ + "2.099474, 2.357878, 2.612742, 3.050700, 3.927406",\ + "1.148308, 1.435007, 1.679656, 2.115198, 2.987988",\ + "1.182731, 1.469430, 1.714081, 2.149627, 3.022426",\ + "1.253713, 1.540412, 1.785064, 2.220617, 3.093429",\ + "1.507865, 1.794564, 2.039218, 2.474777, 3.347603",\ + "2.432936, 2.719633, 2.964306, 3.399922, 4.272861"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208076, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470714, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470715, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693296, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470716, 2.471298, 2.472467",\ + "0.034240, 0.034240, 0.034246, 0.034266, 0.034306",\ + "0.083583, 0.083583, 0.083596, 0.083639, 0.083725",\ + "0.208066, 0.208066, 0.208077, 0.208111, 0.208180",\ + "0.693294, 0.693297, 0.693300, 0.693300, 0.693300",\ + "2.470544, 2.470544, 2.470721, 2.471301, 2.472467"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.603644, 0.858574, 1.115563, 1.554765, 2.433169",\ + "0.645940, 0.900870, 1.157859, 1.597061, 2.475466",\ + "0.706502, 0.961433, 1.218421, 1.657624, 2.536028",\ + "0.875433, 1.130363, 1.387352, 1.826554, 2.704960",\ + "1.458686, 1.713616, 1.970605, 2.409806, 3.288209",\ + "0.691052, 0.946059, 1.203035, 1.641479, 2.519103",\ + "0.733348, 0.988355, 1.245331, 1.683775, 2.561400",\ + "0.793911, 1.048918, 1.305893, 1.744338, 2.621962",\ + "0.962841, 1.217848, 1.474824, 1.913269, 2.790894",\ + "1.546094, 1.801101, 2.058077, 2.496521, 3.374143",\ + "0.778696, 1.034884, 1.290997, 1.729101, 2.606058",\ + "0.820992, 1.077180, 1.333292, 1.771397, 2.648355",\ + "0.881555, 1.137743, 1.393855, 1.831960, 2.708917",\ + "1.050485, 1.306673, 1.562785, 2.000890, 2.877849",\ + "1.633738, 1.889926, 2.146038, 2.584142, 3.461098",\ + "0.841881, 1.100292, 1.355131, 1.793014, 2.669567",\ + "0.884176, 1.142587, 1.397427, 1.835310, 2.711864",\ + "0.944739, 1.203150, 1.457990, 1.895873, 2.772426",\ + "1.113669, 1.372080, 1.626920, 2.064803, 2.941358",\ + "1.696922, 1.955333, 2.210173, 2.648055, 3.524607",\ + "1.175348, 1.462047, 1.706695, 2.142236, 3.015023",\ + "1.217643, 1.504343, 1.748991, 2.184532, 3.057320",\ + "1.278206, 1.564905, 1.809554, 2.245094, 3.117882",\ + "1.447136, 1.733835, 1.978484, 2.414025, 3.286813",\ + "2.030389, 2.317089, 2.561737, 2.997277, 3.870063"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061",\ + "0.045862, 0.045862, 0.045861, 0.045860, 0.045856",\ + "0.079962, 0.079962, 0.079962, 0.079962, 0.079962",\ + "0.155688, 0.155688, 0.155687, 0.155686, 0.155684",\ + "0.431271, 0.431271, 0.431271, 0.431271, 0.431271",\ + "1.498067, 1.498067, 1.498066, 1.498065, 1.498061"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2536*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.746778, 1.007936, 1.300121, 1.808548, 2.825403",\ + "0.781168, 1.042326, 1.334511, 1.842939, 2.859794",\ + "0.852412, 1.113570, 1.405754, 1.914182, 2.931037",\ + "1.106578, 1.367736, 1.659921, 2.168348, 3.185203",\ + "2.031144, 2.292302, 2.584487, 3.092916, 4.109773",\ + "0.834191, 1.095510, 1.387813, 1.895263, 2.911337",\ + "0.868581, 1.129900, 1.422203, 1.929654, 2.945728",\ + "0.939824, 1.201144, 1.493447, 2.000897, 3.016971",\ + "1.193991, 1.455310, 1.747613, 2.255063, 3.271137",\ + "2.118557, 2.379876, 2.672179, 3.179631, 4.195706",\ + "0.915090, 1.184556, 1.475780, 1.982886, 2.998292",\ + "0.949480, 1.218946, 1.510170, 2.017276, 3.032683",\ + "1.020724, 1.290190, 1.581414, 2.088519, 3.103926",\ + "1.274890, 1.544356, 1.835580, 2.342686, 3.358092",\ + "2.199456, 2.468922, 2.760146, 3.267253, 4.282661",\ + "0.974724, 1.250286, 1.539926, 2.046799, 3.061801",\ + "1.009114, 1.284676, 1.574316, 2.081189, 3.096192",\ + "1.080358, 1.355919, 1.645560, 2.152433, 3.167435",\ + "1.334524, 1.610085, 1.899726, 2.406599, 3.421601",\ + "2.259090, 2.534652, 2.824292, 3.331166, 4.346170",\ + "1.308449, 1.615752, 1.892195, 2.396312, 3.407257",\ + "1.342839, 1.650142, 1.926585, 2.430702, 3.441648",\ + "1.414083, 1.721386, 1.997829, 2.501945, 3.512891",\ + "1.668249, 1.975552, 2.251995, 2.756112, 3.767057",\ + "2.592815, 2.900118, 3.176561, 3.680679, 4.691627"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464222, 2.464247, 2.464295",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692758, 0.692761",\ + "2.464216, 2.464216, 2.464223, 2.464247, 2.464295"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.778533, 1.039691, 1.331875, 1.840304, 2.857162",\ + "0.820286, 1.081443, 1.373628, 1.882057, 2.898914",\ + "0.880216, 1.141374, 1.433558, 1.941987, 2.958845",\ + "1.048333, 1.309491, 1.601676, 2.110105, 3.126962",\ + "1.630225, 1.891381, 2.183566, 2.692000, 3.708866",\ + "0.865946, 1.127265, 1.419568, 1.927019, 2.943096",\ + "0.907698, 1.169017, 1.461320, 1.968772, 2.984848",\ + "0.967629, 1.228948, 1.521251, 2.028702, 3.044779",\ + "1.135746, 1.397065, 1.689368, 2.196820, 3.212896",\ + "1.717638, 1.978955, 2.271259, 2.778715, 3.794800",\ + "0.946845, 1.216310, 1.507534, 2.014642, 3.030051",\ + "0.988598, 1.258063, 1.549287, 2.056394, 3.071803",\ + "1.048528, 1.317993, 1.609217, 2.116324, 3.131734",\ + "1.216645, 1.486111, 1.777335, 2.284442, 3.299851",\ + "1.798537, 2.068001, 2.359225, 2.866337, 3.881755",\ + "1.006479, 1.282040, 1.571681, 2.078555, 3.093560",\ + "1.048231, 1.323793, 1.613433, 2.120307, 3.135312",\ + "1.108162, 1.383723, 1.673364, 2.180238, 3.195243",\ + "1.276279, 1.551840, 1.841481, 2.348355, 3.363360",\ + "1.858171, 2.133730, 2.423372, 2.930250, 3.945264",\ + "1.340204, 1.647506, 1.923949, 2.428067, 3.439016",\ + "1.381956, 1.689259, 1.965702, 2.469820, 3.480768",\ + "1.441887, 1.749189, 2.025632, 2.529750, 3.540699",\ + "1.610004, 1.917307, 2.193750, 2.697868, 3.708816",\ + "2.191895, 2.499197, 2.775640, 3.279763, 4.290720"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2630*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.730000, 0.984087, 1.265833, 1.734427, 2.671616",\ + "0.764390, 1.018477, 1.300223, 1.768817, 2.706006",\ + "0.835634, 1.089720, 1.371467, 1.840061, 2.777249",\ + "1.089800, 1.343887, 1.625633, 2.094227, 3.031415",\ + "2.014367, 2.268453, 2.550199, 3.018794, 3.955984",\ + "0.817406, 1.071683, 1.353396, 1.821141, 2.757549",\ + "0.851796, 1.106073, 1.387787, 1.855531, 2.791939",\ + "0.923039, 1.177317, 1.459030, 1.926775, 2.863183",\ + "1.177206, 1.431483, 1.713197, 2.180941, 3.117349",\ + "2.101773, 2.356050, 2.637762, 3.105508, 4.041918",\ + "0.898242, 1.160744, 1.441359, 1.908762, 2.844504",\ + "0.932632, 1.195135, 1.475749, 1.943152, 2.878895",\ + "1.003876, 1.266378, 1.546993, 2.014396, 2.950138",\ + "1.258042, 1.520545, 1.801159, 2.268562, 3.204304",\ + "2.182609, 2.445111, 2.725725, 3.193129, 4.128873",\ + "0.955902, 1.226495, 1.505499, 1.972675, 2.908013",\ + "0.990292, 1.260885, 1.539889, 2.007065, 2.942404",\ + "1.061535, 1.332129, 1.611133, 2.078309, 3.013647",\ + "1.315702, 1.586295, 1.865299, 2.332475, 3.267813",\ + "2.240268, 2.510862, 2.789865, 3.257042, 4.192382",\ + "1.290536, 1.592309, 1.857360, 2.322016, 3.253469",\ + "1.324926, 1.626699, 1.891750, 2.356406, 3.287859",\ + "1.396169, 1.697943, 1.962993, 2.427649, 3.359103",\ + "1.650336, 1.952109, 2.217160, 2.681816, 3.613269",\ + "2.574903, 2.876675, 3.141726, 3.606383, 4.537838"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270",\ + "0.034112, 0.034112, 0.034112, 0.034112, 0.034112",\ + "0.083749, 0.083749, 0.083749, 0.083750, 0.083750",\ + "0.208405, 0.208405, 0.208405, 0.208405, 0.208405",\ + "0.692756, 0.692756, 0.692756, 0.692757, 0.692760",\ + "2.464221, 2.464222, 2.464226, 2.464241, 2.464270"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.761755, 1.015841, 1.297587, 1.766182, 2.703373",\ + "0.803508, 1.057594, 1.339340, 1.807935, 2.745125",\ + "0.863438, 1.117525, 1.399270, 1.867865, 2.805056",\ + "1.031556, 1.285642, 1.567388, 2.035983, 2.973173",\ + "1.613449, 1.867533, 2.149277, 2.617876, 3.555073",\ + "0.849161, 1.103438, 1.385151, 1.852896, 2.789307",\ + "0.890914, 1.145190, 1.426903, 1.894649, 2.831059",\ + "0.950844, 1.205121, 1.486834, 1.954579, 2.890990",\ + "1.118961, 1.373238, 1.654951, 2.122696, 3.059107",\ + "1.700854, 1.955129, 2.236841, 2.704590, 3.641007",\ + "0.929998, 1.192499, 1.473114, 1.940517, 2.876262",\ + "0.971750, 1.234252, 1.514866, 1.982270, 2.918014",\ + "1.031680, 1.294182, 1.574797, 2.042201, 2.977945",\ + "1.199798, 1.462299, 1.742914, 2.210318, 3.146062",\ + "1.781691, 2.044191, 2.324804, 2.792211, 3.727962",\ + "0.987657, 1.258250, 1.537253, 2.004430, 2.939771",\ + "1.029410, 1.300003, 1.579006, 2.046183, 2.981523",\ + "1.089340, 1.359933, 1.638936, 2.106113, 3.041454",\ + "1.257457, 1.528050, 1.807054, 2.274230, 3.209571",\ + "1.839350, 2.109941, 2.388943, 2.856124, 3.791471",\ + "1.322291, 1.624063, 1.889114, 2.353771, 3.285227",\ + "1.364043, 1.665816, 1.930866, 2.395524, 3.326979",\ + "1.423974, 1.725746, 1.990797, 2.455454, 3.386910",\ + "1.592091, 1.893864, 2.158914, 2.623571, 3.555027",\ + "2.173984, 2.475754, 2.740804, 3.205465, 4.136927"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119",\ + "0.045878, 0.045878, 0.045878, 0.045878, 0.045878",\ + "0.079914, 0.079914, 0.079914, 0.079914, 0.079914",\ + "0.155805, 0.155805, 0.155805, 0.155805, 0.155805",\ + "0.431307, 0.431307, 0.431307, 0.431307, 0.431307",\ + "1.494118, 1.494118, 1.494119, 1.494119, 1.494119"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_2588*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.408137, 0.641492, 0.827125, 1.126915, 1.707802",\ + "0.449833, 0.683188, 0.868821, 1.168611, 1.749498",\ + "0.526013, 0.759368, 0.945001, 1.244791, 1.825678",\ + "0.781403, 1.014758, 1.200392, 1.500182, 2.081068",\ + "1.705853, 1.939205, 2.124836, 2.424627, 3.005518",\ + "0.496543, 0.728810, 0.914406, 1.214220, 1.795155",\ + "0.538239, 0.770506, 0.956102, 1.255916, 1.836851",\ + "0.614419, 0.846686, 1.032282, 1.332096, 1.913031",\ + "0.869809, 1.102077, 1.287673, 1.587487, 2.168421",\ + "1.794258, 2.026523, 2.212117, 2.511932, 3.092872",\ + "0.585620, 0.809145, 0.994433, 1.294249, 1.875187",\ + "0.627316, 0.850841, 1.036129, 1.335945, 1.916883",\ + "0.703496, 0.927021, 1.112309, 1.412125, 1.993063",\ + "0.958887, 1.182412, 1.367700, 1.667515, 2.248453",\ + "1.883336, 2.106858, 2.292144, 2.591961, 3.172904",\ + "0.648884, 0.866977, 1.052144, 1.351703, 1.932250",\ + "0.690580, 0.908672, 1.093840, 1.393399, 1.973946",\ + "0.766760, 0.984852, 1.170020, 1.469579, 2.050126",\ + "1.022151, 1.240243, 1.425410, 1.724970, 2.305516",\ + "1.946599, 2.164690, 2.349855, 2.649415, 3.229967",\ + "0.982874, 1.172308, 1.355803, 1.654896, 2.234530",\ + "1.024570, 1.214004, 1.397499, 1.696592, 2.276226",\ + "1.100750, 1.290184, 1.473679, 1.772772, 2.352406",\ + "1.356140, 1.545574, 1.729069, 2.028162, 2.607796",\ + "2.280588, 2.470021, 2.653514, 2.952608, 3.532247"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070075, 0.070075, 0.070075, 0.070075, 0.070076",\ + "0.199411, 0.199411, 0.199411, 0.199411, 0.199413",\ + "0.685859, 0.685859, 0.685859, 0.685862, 0.685867",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.428385, 0.661739, 0.847373, 1.147163, 1.728050",\ + "0.460631, 0.693986, 0.879619, 1.179409, 1.760296",\ + "0.510947, 0.744302, 0.929935, 1.229725, 1.810612",\ + "0.671611, 0.904965, 1.090599, 1.390389, 1.971276",\ + "1.252728, 1.486083, 1.671717, 1.971507, 2.552392",\ + "0.516791, 0.749058, 0.934654, 1.234468, 1.815403",\ + "0.549037, 0.781304, 0.966900, 1.266714, 1.847649",\ + "0.599353, 0.831620, 1.017216, 1.317030, 1.897965",\ + "0.760017, 0.992284, 1.177880, 1.477694, 2.058629",\ + "1.341134, 1.573402, 1.758998, 2.058812, 2.639746",\ + "0.605868, 0.829393, 1.014680, 1.314497, 1.895434",\ + "0.638114, 0.861639, 1.046927, 1.346743, 1.927681",\ + "0.688430, 0.911955, 1.097243, 1.397059, 1.977997",\ + "0.849094, 1.072619, 1.257906, 1.557723, 2.138661",\ + "1.430211, 1.653737, 1.839025, 2.138841, 2.719778",\ + "0.669132, 0.887224, 1.072391, 1.371951, 1.952498",\ + "0.701378, 0.919471, 1.104638, 1.404197, 1.984744",\ + "0.751694, 0.969786, 1.154953, 1.454513, 2.035060",\ + "0.912358, 1.130450, 1.315617, 1.615177, 2.195724",\ + "1.493475, 1.711568, 1.896736, 2.196295, 2.776841",\ + "1.003122, 1.192555, 1.376050, 1.675143, 2.254777",\ + "1.035368, 1.224802, 1.408297, 1.707390, 2.287024",\ + "1.085684, 1.275118, 1.458613, 1.757706, 2.337340",\ + "1.246348, 1.435782, 1.619277, 1.918369, 2.498003",\ + "1.827465, 2.016899, 2.200395, 2.499487, 3.079121"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483046",\ + "0.029703, 0.029703, 0.029703, 0.029704, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419470, 0.419470, 0.419470, 0.419470, 0.419470",\ + "1.483040, 1.483040, 1.483040, 1.483042, 1.483047"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2478*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.516812, 0.720433, 0.930283, 1.259401, 1.891051",\ + "0.558535, 0.762156, 0.972006, 1.301124, 1.932775",\ + "0.634601, 0.838222, 1.048072, 1.377190, 2.008840",\ + "0.890090, 1.093710, 1.303558, 1.632676, 2.264330",\ + "1.814399, 2.018020, 2.227869, 2.556987, 3.188638",\ + "0.605540, 0.807752, 1.017564, 1.346706, 1.978405",\ + "0.647263, 0.849475, 1.059287, 1.388429, 2.020128",\ + "0.723329, 0.925541, 1.135353, 1.464495, 2.096194",\ + "0.978818, 1.181028, 1.390838, 1.719981, 2.351683",\ + "1.903127, 2.105338, 2.315150, 2.644292, 3.275992",\ + "0.695187, 0.888089, 1.097591, 1.426734, 2.058436",\ + "0.736910, 0.929812, 1.139314, 1.468457, 2.100160",\ + "0.812976, 1.005878, 1.215380, 1.544523, 2.176225",\ + "1.068465, 1.261366, 1.470865, 1.800010, 2.431715",\ + "1.992774, 2.185676, 2.395177, 2.724321, 3.356023",\ + "0.755223, 0.945959, 1.155358, 1.484250, 2.115621",\ + "0.796946, 0.987682, 1.197081, 1.525973, 2.157344",\ + "0.873011, 1.063748, 1.273147, 1.602039, 2.233410",\ + "1.128500, 1.319236, 1.528632, 1.857525, 2.488900",\ + "2.052809, 2.243546, 2.452944, 2.781836, 3.413208",\ + "1.058034, 1.251576, 1.459026, 1.787495, 2.418047",\ + "1.099757, 1.293299, 1.500749, 1.829218, 2.459770",\ + "1.175823, 1.369365, 1.576815, 1.905284, 2.535836",\ + "1.431312, 1.624853, 1.832301, 2.160770, 2.791326",\ + "2.355621, 2.549163, 2.756612, 3.085082, 3.715634"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\ + "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\ + "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\ + "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533",\ + "0.025354, 0.025354, 0.025354, 0.025354, 0.025354",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199485, 0.199485, 0.199485, 0.199486, 0.199488",\ + "0.686680, 0.686680, 0.686680, 0.686680, 0.686680",\ + "2.452500, 2.452500, 2.452512, 2.452522, 2.452533"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.539402, 0.743023, 0.952873, 1.281991, 1.913641",\ + "0.571427, 0.775047, 0.984897, 1.314015, 1.945666",\ + "0.621835, 0.825456, 1.035306, 1.364424, 1.996074",\ + "0.782894, 0.986516, 1.196367, 1.525485, 2.157133",\ + "1.362868, 1.566489, 1.776340, 2.105458, 2.737106",\ + "0.628130, 0.830342, 1.040154, 1.369296, 2.000995",\ + "0.660155, 0.862366, 1.072178, 1.401320, 2.033020",\ + "0.710563, 0.912774, 1.122587, 1.451729, 2.083427",\ + "0.871623, 1.073835, 1.283648, 1.612790, 2.244487",\ + "1.451596, 1.653808, 1.863621, 2.192763, 2.824460",\ + "0.717777, 0.910679, 1.120180, 1.449324, 2.081027",\ + "0.749802, 0.942704, 1.152205, 1.481349, 2.113051",\ + "0.800210, 0.993112, 1.202614, 1.531757, 2.163459",\ + "0.961270, 1.154172, 1.363675, 1.692818, 2.324518",\ + "1.541243, 1.734145, 1.943648, 2.272791, 2.904491",\ + "0.777813, 0.968549, 1.177947, 1.506840, 2.138211",\ + "0.809837, 1.000574, 1.209971, 1.538864, 2.170236",\ + "0.860245, 1.050982, 1.260381, 1.589273, 2.220644",\ + "1.021305, 1.212042, 1.421442, 1.750333, 2.381703",\ + "1.601278, 1.792015, 2.001415, 2.330307, 2.961676",\ + "1.080624, 1.274166, 1.481616, 1.810085, 2.440637",\ + "1.112649, 1.306190, 1.513640, 1.842109, 2.472662",\ + "1.163057, 1.356599, 1.564049, 1.892518, 2.523069",\ + "1.324117, 1.517659, 1.725110, 2.053579, 2.684129",\ + "1.904090, 2.097632, 2.305083, 2.633552, 3.264102"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059266, 0.059266, 0.059266, 0.059267, 0.059267",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131513",\ + "0.417796, 0.417796, 0.417800, 0.417803, 0.417807",\ + "1.484511, 1.484511, 1.484513, 1.484514, 1.484517"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2528*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.343347, 0.560733, 0.738878, 1.027873, 1.588767",\ + "0.376901, 0.594286, 0.772429, 1.061825, 1.623703",\ + "0.447931, 0.665317, 0.843465, 1.132863, 1.694739",\ + "0.702775, 0.920161, 1.098308, 1.387706, 1.949584",\ + "1.627697, 1.845075, 2.023177, 2.312590, 2.874544",\ + "0.431725, 0.648051, 0.826159, 1.115178, 1.676121",\ + "0.465279, 0.681604, 0.859710, 1.149130, 1.711057",\ + "0.536309, 0.752636, 0.930746, 1.220168, 1.782093",\ + "0.791152, 1.007479, 1.185589, 1.475011, 2.036938",\ + "1.716075, 1.932394, 2.110458, 2.399895, 2.961898",\ + "0.521054, 0.728383, 0.906186, 1.195207, 1.756152",\ + "0.554608, 0.761937, 0.939737, 1.229159, 1.791088",\ + "0.625638, 0.832968, 1.010773, 1.300196, 1.862124",\ + "0.880482, 1.087811, 1.265616, 1.555040, 2.116970",\ + "1.805404, 2.012726, 2.190485, 2.479923, 3.041929",\ + "0.584699, 0.786201, 0.963880, 1.252637, 1.813169",\ + "0.618252, 0.819754, 0.997431, 1.286590, 1.848107",\ + "0.689283, 0.890786, 1.068467, 1.357627, 1.919143",\ + "0.944126, 1.145629, 1.323310, 1.612471, 2.173989",\ + "1.869048, 2.070544, 2.248179, 2.537354, 3.098948",\ + "0.912898, 1.091426, 1.267535, 1.555809, 2.115392",\ + "0.946452, 1.124980, 1.301087, 1.589763, 2.150333",\ + "1.017482, 1.196011, 1.372123, 1.660800, 2.221369",\ + "1.272326, 1.450854, 1.626966, 1.915644, 2.476214",\ + "2.197247, 2.375769, 2.551834, 2.840528, 3.401175"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446888, 2.446896, 2.446897, 2.446897, 2.446897",\ + "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446888, 2.446896, 2.446897, 2.446897, 2.446897",\ + "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446889, 2.446896, 2.446897, 2.446897, 2.446897",\ + "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446889, 2.446896, 2.446897, 2.446897, 2.446897",\ + "0.023744, 0.023744, 0.023744, 0.023744, 0.023744",\ + "0.069296, 0.069296, 0.069296, 0.069296, 0.069296",\ + "0.200223, 0.200225, 0.200229, 0.200251, 0.200303",\ + "0.685855, 0.685857, 0.685864, 0.685915, 0.686035",\ + "2.446889, 2.446896, 2.446897, 2.446897, 2.446897"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.337578, 0.554964, 0.733111, 1.022508, 1.584385",\ + "0.369918, 0.587304, 0.765454, 1.054853, 1.616734",\ + "0.420270, 0.637656, 0.815804, 1.105202, 1.667081",\ + "0.581348, 0.798734, 0.976881, 1.266279, 1.828157",\ + "1.161863, 1.379232, 1.557282, 1.846629, 2.408468",\ + "0.425956, 0.642282, 0.820392, 1.109813, 1.671738",\ + "0.458296, 0.674622, 0.852735, 1.142159, 1.704088",\ + "0.508648, 0.724974, 0.903085, 1.192507, 1.754434",\ + "0.669726, 0.886052, 1.064162, 1.353584, 1.915510",\ + "1.250240, 1.466550, 1.644563, 1.933934, 2.495822",\ + "0.515285, 0.722614, 0.900419, 1.189842, 1.751770",\ + "0.547625, 0.754955, 0.932762, 1.222187, 1.784119",\ + "0.597977, 0.805307, 0.983111, 1.272535, 1.834466",\ + "0.759055, 0.966385, 1.144189, 1.433612, 1.995542",\ + "1.339568, 1.546883, 1.724590, 2.013963, 2.575853",\ + "0.578929, 0.780432, 0.958113, 1.247273, 1.808789",\ + "0.611270, 0.812772, 0.990456, 1.279618, 1.841138",\ + "0.661622, 0.863124, 1.040806, 1.329967, 1.891485",\ + "0.822700, 1.024202, 1.201883, 1.491044, 2.052561",\ + "1.403211, 1.604700, 1.782284, 2.071394, 2.632872",\ + "0.907129, 1.085657, 1.261768, 1.550446, 2.111014",\ + "0.939469, 1.117998, 1.294111, 1.582791, 2.143364",\ + "0.989821, 1.168350, 1.344461, 1.633139, 2.193710",\ + "1.150899, 1.329427, 1.505538, 1.794216, 2.354787",\ + "1.731412, 1.909925, 2.085939, 2.374567, 2.935098"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059305, 0.059302, 0.059288, 0.059276, 0.059261",\ + "0.131696, 0.131694, 0.131680, 0.131669, 0.131651",\ + "0.419114, 0.419122, 0.419145, 0.419266, 0.419546",\ + "1.483332, 1.483297, 1.483098, 1.482941, 1.482729",\ + "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059305, 0.059302, 0.059288, 0.059276, 0.059261",\ + "0.131696, 0.131694, 0.131680, 0.131669, 0.131651",\ + "0.419115, 0.419122, 0.419145, 0.419266, 0.419546",\ + "1.483331, 1.483297, 1.483098, 1.482941, 1.482729",\ + "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059305, 0.059302, 0.059288, 0.059276, 0.059261",\ + "0.131696, 0.131694, 0.131680, 0.131669, 0.131651",\ + "0.419115, 0.419122, 0.419145, 0.419266, 0.419546",\ + "1.483328, 1.483297, 1.483098, 1.482941, 1.482729",\ + "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059304, 0.059302, 0.059288, 0.059276, 0.059261",\ + "0.131695, 0.131694, 0.131680, 0.131668, 0.131651",\ + "0.419116, 0.419122, 0.419145, 0.419267, 0.419547",\ + "1.483325, 1.483297, 1.483097, 1.482941, 1.482729",\ + "0.030095, 0.030094, 0.030093, 0.030093, 0.030093",\ + "0.059305, 0.059302, 0.059288, 0.059276, 0.059260",\ + "0.131696, 0.131694, 0.131680, 0.131668, 0.131651",\ + "0.419115, 0.419122, 0.419145, 0.419267, 0.419548",\ + "1.483327, 1.483296, 1.483097, 1.482941, 1.482728"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2593*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.254656, 0.491006, 0.681199, 0.986728, 1.577708",\ + "0.288244, 0.524620, 0.714843, 1.020374, 1.611331",\ + "0.359123, 0.595519, 0.785873, 1.091419, 1.682284",\ + "0.614167, 0.850282, 1.040808, 1.346411, 1.937248",\ + "1.539512, 1.774279, 1.968056, 2.274137, 2.863164",\ + "0.343150, 0.578325, 0.768480, 1.074033, 1.665062",\ + "0.376740, 0.611939, 0.802124, 1.107679, 1.698684",\ + "0.447618, 0.682838, 0.873154, 1.178725, 1.769638",\ + "0.702665, 0.937601, 1.128089, 1.433716, 2.024602",\ + "1.628026, 1.861597, 2.055336, 2.361442, 2.950518",\ + "0.432477, 0.658660, 0.848507, 1.154062, 1.745093",\ + "0.466070, 0.692274, 0.882150, 1.187708, 1.778716",\ + "0.536949, 0.763173, 0.953181, 1.258753, 1.849669",\ + "0.792003, 1.017936, 1.208116, 1.513744, 2.104633",\ + "1.717412, 1.941932, 2.135364, 2.441470, 3.030550",\ + "0.495969, 0.716495, 0.906228, 1.211528, 1.802181",\ + "0.529564, 0.750109, 0.939872, 1.245174, 1.835804",\ + "0.600443, 0.821007, 1.010903, 1.316219, 1.906757",\ + "0.855505, 1.075769, 1.265838, 1.571210, 2.161721",\ + "1.780957, 1.999760, 2.193094, 2.498934, 3.087633",\ + "0.831401, 1.021856, 1.209889, 1.514732, 2.104490",\ + "0.865014, 1.055469, 1.243533, 1.548377, 2.138113",\ + "0.935893, 1.126362, 1.314564, 1.619422, 2.209066",\ + "1.191001, 1.381117, 1.569499, 1.874413, 2.464029",\ + "2.116730, 2.305066, 2.496756, 2.802135, 3.389936"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069342, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685011, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454035, 2.454504, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069342, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685011, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454035, 2.454504, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069342, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685011, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454035, 2.454504, 2.455152",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454036, 2.454505, 2.455154",\ + "0.023821, 0.023821, 0.023821, 0.023833, 0.023862",\ + "0.069303, 0.069303, 0.069343, 0.069357, 0.069357",\ + "0.199561, 0.199561, 0.199561, 0.199561, 0.199561",\ + "0.684891, 0.684891, 0.685012, 0.685055, 0.685055",\ + "2.453468, 2.453468, 2.454036, 2.454506, 2.455156"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.249454, 0.486004, 0.675967, 0.981250, 1.571825",\ + "0.281865, 0.518328, 0.708344, 1.013662, 1.604275",\ + "0.332260, 0.568655, 0.758650, 1.063988, 1.654672",\ + "0.493098, 0.729544, 0.919296, 1.224627, 1.815523",\ + "1.073988, 1.310152, 1.500044, 1.805268, 2.395687",\ + "0.337933, 0.573322, 0.763248, 1.068555, 1.659178",\ + "0.370344, 0.605646, 0.795625, 1.100967, 1.691628",\ + "0.420740, 0.655974, 0.845931, 1.151293, 1.742025",\ + "0.581582, 0.816862, 1.006577, 1.311932, 1.902877",\ + "1.162485, 1.397470, 1.587325, 1.892573, 2.483041",\ + "0.427218, 0.653657, 0.843275, 1.148583, 1.739210",\ + "0.459630, 0.685981, 0.875652, 1.180995, 1.771660",\ + "0.510027, 0.736309, 0.925958, 1.231322, 1.822057",\ + "0.670883, 0.897197, 1.086604, 1.391961, 1.982908",\ + "1.251823, 1.477805, 1.667352, 1.972602, 2.563072",\ + "0.490671, 0.711493, 0.900996, 1.206049, 1.796297",\ + "0.523083, 0.743816, 0.933373, 1.238461, 1.828747",\ + "0.573482, 0.794144, 0.983679, 1.288787, 1.879144",\ + "0.734351, 0.955034, 1.144324, 1.449427, 2.039996",\ + "1.315324, 1.535635, 1.725073, 2.030067, 2.620159",\ + "0.825858, 1.016851, 1.204656, 1.509252, 2.098604",\ + "0.858274, 1.049176, 1.237034, 1.541664, 2.131054",\ + "0.908682, 1.099504, 1.287340, 1.591990, 2.181452",\ + "1.069631, 1.260400, 1.447985, 1.752630, 2.342305",\ + "1.650816, 1.840953, 2.028734, 2.333270, 2.922466"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417989, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417989, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417989, 0.418302",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030363",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309",\ + "0.030092, 0.030092, 0.030092, 0.030170, 0.030364",\ + "0.059437, 0.059437, 0.059437, 0.059474, 0.059565",\ + "0.131608, 0.131608, 0.131661, 0.131712, 0.131790",\ + "0.417862, 0.417862, 0.417862, 0.417990, 0.418303",\ + "1.478309, 1.478309, 1.478309, 1.478309, 1.478309"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2636*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.325472, 0.549886, 0.736679, 1.035269, 1.612348",\ + "0.359026, 0.583502, 0.770294, 1.068882, 1.645956",\ + "0.430054, 0.654527, 0.841316, 1.139890, 1.716933",\ + "0.684897, 0.909477, 1.096261, 1.394816, 1.971817",\ + "1.609849, 1.835494, 2.022258, 2.320729, 2.897541",\ + "0.413759, 0.637204, 0.823960, 1.122574, 1.699702",\ + "0.447318, 0.670820, 0.857575, 1.156187, 1.733310",\ + "0.518346, 0.741845, 0.928597, 1.227195, 1.804287",\ + "0.773189, 0.996795, 1.183542, 1.482121, 2.059171",\ + "1.698136, 1.922812, 2.109539, 2.408034, 2.984894",\ + "0.503271, 0.717533, 0.903987, 1.202602, 1.779733",\ + "0.536839, 0.751148, 0.937602, 1.236216, 1.813341",\ + "0.607869, 0.822173, 1.008624, 1.307223, 1.884319",\ + "0.862712, 1.077123, 1.263569, 1.562150, 2.139202",\ + "1.787644, 2.003140, 2.189566, 2.488062, 3.064926",\ + "0.567278, 0.775354, 0.961702, 1.260053, 1.836791",\ + "0.600857, 0.808970, 0.995318, 1.293666, 1.870399",\ + "0.671888, 0.879995, 1.066339, 1.364674, 1.941376",\ + "0.926731, 1.134945, 1.321284, 1.619600, 2.196259",\ + "1.851648, 2.060962, 2.247281, 2.545512, 3.121983",\ + "0.902611, 1.080594, 1.265360, 1.563241, 2.139063",\ + "0.936228, 1.114210, 1.298975, 1.596854, 2.172671",\ + "1.007260, 1.185235, 1.369997, 1.667862, 2.243648",\ + "1.262219, 1.440184, 1.624942, 1.922788, 2.498532",\ + "2.188276, 2.366200, 2.550939, 2.848700, 3.424254"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446848, 2.446711, 2.446702, 2.446700, 2.446699",\ + "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446844, 2.446711, 2.446702, 2.446700, 2.446699",\ + "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446834, 2.446711, 2.446702, 2.446700, 2.446699",\ + "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446823, 2.446710, 2.446702, 2.446700, 2.446699",\ + "0.023797, 0.023797, 0.023797, 0.023789, 0.023770",\ + "0.069301, 0.069300, 0.069300, 0.069299, 0.069296",\ + "0.200200, 0.200200, 0.200200, 0.200200, 0.200200",\ + "0.685818, 0.685818, 0.685818, 0.685818, 0.685818",\ + "2.446830, 2.446707, 2.446702, 2.446700, 2.446699"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.319701, 0.545442, 0.732220, 1.030751, 1.607697",\ + "0.352039, 0.577906, 0.764685, 1.063221, 1.640180",\ + "0.402393, 0.628225, 0.815004, 1.113542, 1.690503",\ + "0.563471, 0.788964, 0.975744, 1.274281, 1.851241",\ + "1.144048, 1.371915, 1.558729, 1.857404, 2.434677",\ + "0.407993, 0.632759, 0.819501, 1.118056, 1.695051",\ + "0.440331, 0.665224, 0.851966, 1.150527, 1.727533",\ + "0.490684, 0.715542, 0.902285, 1.200847, 1.777857",\ + "0.651763, 0.876282, 1.063025, 1.361586, 1.938595",\ + "1.232329, 1.459233, 1.646010, 1.944710, 2.522030",\ + "0.497516, 0.713088, 0.899528, 1.198085, 1.775082",\ + "0.529855, 0.745552, 0.931993, 1.230555, 1.807565",\ + "0.580208, 0.795871, 0.982312, 1.280875, 1.857888",\ + "0.741286, 0.956611, 1.143052, 1.441614, 2.018626",\ + "1.321819, 1.539562, 1.726037, 2.024738, 2.602062",\ + "0.561534, 0.770909, 0.957244, 1.255535, 1.832140",\ + "0.593874, 0.803374, 0.989709, 1.288005, 1.864622",\ + "0.644226, 0.853692, 1.040028, 1.338326, 1.914946",\ + "0.805304, 1.014432, 1.200767, 1.499064, 2.075684",\ + "1.385806, 1.597383, 1.783752, 2.082189, 2.659120",\ + "0.898194, 1.076148, 1.260901, 1.558723, 2.134412",\ + "0.930657, 1.108613, 1.293366, 1.591193, 2.166894",\ + "0.980975, 1.158931, 1.343685, 1.641514, 2.217218",\ + "1.141715, 1.319671, 1.504425, 1.802253, 2.377955",\ + "1.724358, 1.902624, 2.087410, 2.385377, 2.961392"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059314, 0.059250, 0.059241, 0.059238, 0.059238",\ + "0.131704, 0.131646, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.483458, 1.482592, 1.482500, 1.482470, 1.482449",\ + "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059313, 0.059250, 0.059241, 0.059238, 0.059238",\ + "0.131703, 0.131646, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.483437, 1.482592, 1.482500, 1.482470, 1.482449",\ + "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059308, 0.059250, 0.059241, 0.059238, 0.059238",\ + "0.131698, 0.131646, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.483369, 1.482592, 1.482500, 1.482470, 1.482449",\ + "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059303, 0.059250, 0.059241, 0.059238, 0.059238",\ + "0.131694, 0.131646, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.483305, 1.482589, 1.482500, 1.482470, 1.482449",\ + "0.030095, 0.030095, 0.030095, 0.030095, 0.030095",\ + "0.059306, 0.059248, 0.059241, 0.059238, 0.059238",\ + "0.131697, 0.131645, 0.131637, 0.131633, 0.131629",\ + "0.418989, 0.418989, 0.418989, 0.418989, 0.418989",\ + "1.482893, 1.482566, 1.482500, 1.482470, 1.482448"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2688*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.402084, 0.617885, 0.797210, 1.086950, 1.648801",\ + "0.443807, 0.659608, 0.838933, 1.128673, 1.690524",\ + "0.519872, 0.735673, 0.914998, 1.204739, 1.766590",\ + "0.775363, 0.991161, 1.170488, 1.460228, 2.022074",\ + "1.699671, 1.915471, 2.094797, 2.384537, 2.946387",\ + "0.490367, 0.705202, 0.884491, 1.174255, 1.736155",\ + "0.532090, 0.746925, 0.926214, 1.215978, 1.777877",\ + "0.608155, 0.822991, 1.002279, 1.292044, 1.853944",\ + "0.863645, 1.078479, 1.257769, 1.547533, 2.109427",\ + "1.787954, 2.002789, 2.182077, 2.471842, 3.033741",\ + "0.579657, 0.785533, 0.964518, 1.254284, 1.816186",\ + "0.621380, 0.827256, 1.006241, 1.296007, 1.857909",\ + "0.697445, 0.903322, 1.082306, 1.372073, 1.933975",\ + "0.952935, 1.158809, 1.337796, 1.627561, 2.189459",\ + "1.877244, 2.083119, 2.262105, 2.551871, 3.113772",\ + "0.643368, 0.843363, 1.022215, 1.311715, 1.873206",\ + "0.685091, 0.885086, 1.063938, 1.353438, 1.914929",\ + "0.761157, 0.961152, 1.140003, 1.429504, 1.990995",\ + "1.016647, 1.216639, 1.395493, 1.684993, 2.246479",\ + "1.940955, 2.140950, 2.319802, 2.609302, 3.170792",\ + "0.967924, 1.148670, 1.325870, 1.614888, 2.175433",\ + "1.009647, 1.190393, 1.367593, 1.656611, 2.217156",\ + "1.085713, 1.266459, 1.443658, 1.732677, 2.293222",\ + "1.341202, 1.521946, 1.699148, 1.988165, 2.548706",\ + "2.265511, 2.446256, 2.623457, 2.912475, 3.473019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199488, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498",\ + "0.025354, 0.025353, 0.025353, 0.025353, 0.025352",\ + "0.070228, 0.070228, 0.070228, 0.070228, 0.070228",\ + "0.199487, 0.199487, 0.199487, 0.199486, 0.199483",\ + "0.686687, 0.686687, 0.686686, 0.686686, 0.686686",\ + "2.452523, 2.452519, 2.452519, 2.452513, 2.452498"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.424674, 0.640474, 0.819800, 1.109540, 1.671391",\ + "0.456699, 0.672499, 0.851824, 1.141565, 1.703415",\ + "0.507106, 0.722907, 0.902232, 1.191973, 1.753824",\ + "0.668165, 0.883968, 1.063291, 1.353033, 1.914886",\ + "1.248139, 1.463941, 1.643265, 1.933006, 2.494859",\ + "0.512957, 0.727792, 0.907081, 1.196846, 1.758744",\ + "0.544981, 0.759817, 0.939105, 1.228870, 1.790768",\ + "0.595389, 0.810225, 0.989513, 1.279278, 1.841177",\ + "0.756448, 0.971285, 1.150572, 1.440338, 2.002240",\ + "1.336421, 1.551259, 1.730546, 2.020311, 2.582213",\ + "0.602247, 0.808123, 0.987108, 1.276874, 1.838776",\ + "0.634272, 0.840147, 1.019132, 1.308898, 1.870800",\ + "0.684679, 0.890556, 1.069540, 1.359307, 1.921209",\ + "0.845739, 1.051616, 1.230599, 1.520366, 2.082271",\ + "1.425712, 1.631589, 1.810572, 2.100339, 2.662244",\ + "0.665958, 0.865953, 1.044805, 1.334306, 1.895796",\ + "0.697983, 0.897977, 1.076829, 1.366330, 1.927820",\ + "0.748391, 0.948386, 1.127237, 1.416738, 1.978229",\ + "0.909450, 1.109446, 1.288296, 1.577798, 2.139291",\ + "1.489423, 1.689419, 1.868270, 2.157771, 2.719264",\ + "0.990514, 1.171260, 1.348460, 1.637478, 2.198022",\ + "1.022539, 1.203284, 1.380485, 1.669502, 2.230046",\ + "1.072946, 1.253692, 1.430892, 1.719911, 2.280456",\ + "1.234006, 1.414753, 1.591951, 1.880970, 2.441518",\ + "1.813979, 1.994726, 2.171925, 2.460944, 3.021491"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510",\ + "0.029862, 0.029862, 0.029862, 0.029862, 0.029862",\ + "0.059267, 0.059267, 0.059267, 0.059266, 0.059266",\ + "0.131512, 0.131512, 0.131512, 0.131512, 0.131512",\ + "0.417803, 0.417802, 0.417802, 0.417800, 0.417795",\ + "1.484515, 1.484514, 1.484514, 1.484513, 1.484510"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2386*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.556345, 0.776897, 0.954428, 1.243066, 1.803585",\ + "0.598041, 0.818593, 0.996124, 1.284762, 1.845281",\ + "0.674223, 0.894775, 1.072306, 1.360943, 1.921462",\ + "0.929618, 1.150170, 1.327701, 1.616339, 2.176858",\ + "1.853996, 2.074548, 2.252079, 2.540716, 3.101235",\ + "0.644757, 0.864215, 1.041709, 1.330371, 1.890938",\ + "0.686453, 0.905912, 1.083405, 1.372067, 1.932634",\ + "0.762635, 0.982093, 1.159587, 1.448249, 2.008816",\ + "1.018030, 1.237489, 1.414982, 1.703644, 2.264211",\ + "1.942408, 2.161866, 2.339360, 2.628021, 3.188588",\ + "0.733857, 0.944551, 1.121736, 1.410399, 1.970970",\ + "0.775553, 0.986247, 1.163432, 1.452096, 2.012666",\ + "0.851735, 1.062428, 1.239614, 1.528277, 2.088847",\ + "1.107130, 1.317824, 1.495009, 1.783673, 2.344243",\ + "2.031507, 2.242201, 2.419386, 2.708050, 3.268620",\ + "0.797144, 1.002367, 1.179428, 1.467829, 2.027984",\ + "0.838840, 1.044064, 1.221124, 1.509525, 2.069680",\ + "0.915021, 1.120245, 1.297306, 1.585706, 2.145862",\ + "1.170417, 1.375641, 1.552701, 1.841102, 2.401258",\ + "2.094794, 2.300018, 2.477078, 2.765479, 3.325634",\ + "1.128157, 1.307597, 1.483084, 1.771000, 2.330204",\ + "1.169853, 1.349293, 1.524780, 1.812697, 2.371901",\ + "1.246035, 1.425474, 1.600962, 1.888878, 2.448082",\ + "1.501431, 1.680870, 1.856357, 2.144274, 2.703477",\ + "2.425808, 2.605247, 2.780735, 3.068651, 3.627855"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685787, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.576590, 0.797142, 0.974673, 1.263311, 1.823830",\ + "0.608840, 0.829392, 1.006923, 1.295561, 1.856079",\ + "0.659152, 0.879704, 1.057235, 1.345873, 1.906392",\ + "0.819816, 1.040368, 1.217899, 1.506536, 2.067055",\ + "1.400950, 1.621502, 1.799033, 2.087670, 2.648189",\ + "0.665002, 0.884461, 1.061954, 1.350616, 1.911183",\ + "0.697252, 0.916710, 1.094204, 1.382866, 1.943433",\ + "0.747564, 0.967022, 1.144516, 1.433178, 1.993745",\ + "0.908228, 1.127686, 1.305180, 1.593842, 2.154409",\ + "1.489362, 1.708820, 1.886313, 2.174975, 2.735543",\ + "0.754102, 0.964796, 1.141981, 1.430644, 1.991215",\ + "0.786352, 0.997045, 1.174231, 1.462894, 2.023464",\ + "0.836664, 1.047358, 1.224543, 1.513206, 2.073777",\ + "0.997328, 1.208021, 1.385207, 1.673870, 2.234440",\ + "1.578462, 1.789155, 1.966340, 2.255004, 2.815574",\ + "0.817389, 1.022612, 1.199673, 1.488074, 2.048229",\ + "0.849638, 1.054862, 1.231923, 1.520324, 2.080479",\ + "0.899951, 1.105174, 1.282235, 1.570636, 2.130791",\ + "1.060614, 1.265838, 1.442899, 1.731299, 2.291455",\ + "1.641748, 1.846972, 2.024032, 2.312433, 2.872589",\ + "1.148402, 1.327842, 1.503329, 1.791245, 2.350449",\ + "1.180652, 1.360092, 1.535579, 1.823495, 2.382699",\ + "1.230964, 1.410404, 1.585891, 1.873807, 2.433011",\ + "1.391628, 1.571068, 1.746555, 2.034471, 2.593675",\ + "1.972762, 2.152201, 2.327689, 2.615605, 3.174809"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.538673, 0.779387, 0.972430, 1.279750, 1.873102",\ + "0.580369, 0.821084, 1.014127, 1.321447, 1.914798",\ + "0.656550, 0.897265, 1.090308, 1.397628, 1.990980",\ + "0.911946, 1.152661, 1.345703, 1.653024, 2.246375",\ + "1.836323, 2.077038, 2.270081, 2.577401, 3.170752",\ + "0.626961, 0.866705, 1.059711, 1.367055, 1.960455",\ + "0.668657, 0.908401, 1.101408, 1.408752, 2.002152",\ + "0.744839, 0.984583, 1.177589, 1.484933, 2.078333",\ + "1.000234, 1.239979, 1.432984, 1.740329, 2.333729",\ + "1.924612, 2.164356, 2.357362, 2.664706, 3.258105",\ + "0.716276, 0.947035, 1.139738, 1.447084, 2.040487",\ + "0.757973, 0.988732, 1.181434, 1.488780, 2.082183",\ + "0.834154, 1.064913, 1.257616, 1.564962, 2.158365",\ + "1.089550, 1.320309, 1.513011, 1.820357, 2.413760",\ + "2.013927, 2.244686, 2.437389, 2.744734, 3.338137",\ + "0.780015, 1.004896, 1.197467, 1.504554, 2.097583",\ + "0.821712, 1.046593, 1.239163, 1.546250, 2.139279",\ + "0.897893, 1.122774, 1.315345, 1.622432, 2.215461",\ + "1.153289, 1.378170, 1.570740, 1.877827, 2.470857",\ + "2.077666, 2.302547, 2.495118, 2.802204, 3.395233",\ + "1.117001, 1.310416, 1.501127, 1.807759, 2.399902",\ + "1.158697, 1.352113, 1.542824, 1.849456, 2.441598",\ + "1.234879, 1.428294, 1.619005, 1.925637, 2.517779",\ + "1.490274, 1.683690, 1.874401, 2.181033, 2.773175",\ + "2.414652, 2.608067, 2.798778, 3.105409, 3.697551"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070068, 0.070068",\ + "0.199415, 0.199415, 0.199415, 0.199415, 0.199415",\ + "0.685787, 0.685787, 0.685787, 0.685786, 0.685786",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455201"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.558918, 0.799632, 0.992675, 1.299995, 1.893347",\ + "0.591168, 0.831882, 1.024925, 1.332245, 1.925597",\ + "0.641480, 0.882194, 1.075237, 1.382557, 1.975909",\ + "0.802143, 1.042858, 1.235901, 1.543221, 2.136573",\ + "1.383277, 1.623992, 1.817035, 2.124355, 2.717707",\ + "0.647206, 0.886950, 1.079956, 1.387300, 1.980700",\ + "0.679456, 0.919200, 1.112206, 1.419550, 2.012950",\ + "0.729768, 0.969512, 1.162518, 1.469862, 2.063262",\ + "0.890432, 1.130176, 1.323182, 1.630526, 2.223926",\ + "1.471565, 1.711310, 1.904316, 2.211660, 2.805060",\ + "0.736521, 0.967281, 1.159983, 1.467329, 2.060732",\ + "0.768771, 0.999530, 1.192233, 1.499579, 2.092982",\ + "0.819083, 1.049842, 1.242545, 1.549891, 2.143294",\ + "0.979747, 1.210506, 1.403209, 1.710555, 2.303958",\ + "1.560881, 1.791640, 1.984343, 2.291688, 2.885092",\ + "0.800261, 1.025141, 1.217712, 1.524799, 2.117828",\ + "0.832510, 1.057391, 1.249962, 1.557049, 2.150078",\ + "0.882822, 1.107703, 1.300274, 1.607361, 2.200390",\ + "1.043486, 1.268367, 1.460938, 1.768024, 2.361054",\ + "1.624620, 1.849501, 2.042072, 2.349159, 2.942188",\ + "1.137246, 1.330662, 1.521373, 1.828004, 2.420147",\ + "1.169496, 1.362911, 1.553622, 1.860254, 2.452396",\ + "1.219808, 1.413224, 1.603935, 1.910566, 2.502709",\ + "1.380472, 1.573887, 1.764598, 2.071230, 2.663373",\ + "1.961606, 2.155021, 2.345732, 2.652364, 3.244506"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131486, 0.131486, 0.131486, 0.131486, 0.131486",\ + "0.419471, 0.419471, 0.419471, 0.419471, 0.419471",\ + "1.482976, 1.482976, 1.482976, 1.482976, 1.482976"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2306*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.454515, 0.687556, 0.876637, 1.181062, 1.770586",\ + "0.496240, 0.729281, 0.918362, 1.222787, 1.812311",\ + "0.572297, 0.805339, 0.994419, 1.298844, 1.888368",\ + "0.827855, 1.060896, 1.249979, 1.554404, 2.143927",\ + "1.752113, 1.985154, 2.174236, 2.478661, 3.068184",\ + "0.542959, 0.774874, 0.963918, 1.268367, 1.857939",\ + "0.584684, 0.816599, 1.005643, 1.310092, 1.899664",\ + "0.660741, 0.892656, 1.081700, 1.386149, 1.975721",\ + "0.916299, 1.148213, 1.337260, 1.641709, 2.231281",\ + "1.840557, 2.072472, 2.261517, 2.565966, 3.155538",\ + "0.633029, 0.855201, 1.043945, 1.348395, 1.937971",\ + "0.674754, 0.896927, 1.085670, 1.390121, 1.979696",\ + "0.750812, 0.972984, 1.161727, 1.466178, 2.055753",\ + "1.006370, 1.228541, 1.417287, 1.721738, 2.311312",\ + "1.930628, 2.152800, 2.341543, 2.645994, 3.235569",\ + "0.697606, 0.913035, 1.101665, 1.405861, 1.995059",\ + "0.739331, 0.954761, 1.143391, 1.447586, 2.036784",\ + "0.815389, 1.030818, 1.219448, 1.523643, 2.112841",\ + "1.070947, 1.286375, 1.475007, 1.779203, 2.368400",\ + "1.995205, 2.210634, 2.399264, 2.703460, 3.292657",\ + "1.037719, 1.218357, 1.405324, 1.709062, 2.297368",\ + "1.079444, 1.260083, 1.447049, 1.750787, 2.339093",\ + "1.155501, 1.336140, 1.523106, 1.826844, 2.415150",\ + "1.411059, 1.591697, 1.778666, 2.082405, 2.670709",\ + "2.335317, 2.515956, 2.702923, 3.006661, 3.594966"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452471, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452470, 2.452462, 2.452462, 2.452446, 2.452406",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070222, 0.070222, 0.070222",\ + "0.199531, 0.199531, 0.199531, 0.199531, 0.199531",\ + "0.686584, 0.686584, 0.686584, 0.686584, 0.686584",\ + "2.452470, 2.452462, 2.452462, 2.452446, 2.452406"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.477114, 0.710155, 0.899236, 1.203661, 1.793185",\ + "0.509144, 0.742185, 0.931266, 1.235691, 1.825215",\ + "0.559532, 0.792574, 0.981654, 1.286079, 1.875603",\ + "0.720561, 0.953603, 1.142682, 1.447107, 2.036631",\ + "1.300536, 1.533577, 1.722657, 2.027082, 2.616606",\ + "0.565558, 0.797473, 0.986517, 1.290966, 1.880538",\ + "0.597588, 0.829503, 1.018547, 1.322996, 1.912568",\ + "0.647976, 0.879891, 1.068935, 1.373384, 1.962957",\ + "0.809005, 1.040920, 1.229963, 1.534412, 2.123985",\ + "1.388980, 1.620895, 1.809938, 2.114387, 2.703959",\ + "0.655628, 0.877800, 1.066544, 1.370995, 1.960570",\ + "0.687658, 0.909830, 1.098574, 1.403025, 1.992600",\ + "0.738047, 0.960219, 1.148962, 1.453413, 2.042988",\ + "0.899075, 1.121248, 1.309990, 1.614440, 2.204016",\ + "1.479050, 1.701223, 1.889965, 2.194416, 2.783991",\ + "0.720205, 0.935634, 1.124265, 1.428460, 2.017658",\ + "0.752235, 0.967664, 1.156295, 1.460490, 2.049688",\ + "0.802624, 1.018053, 1.206683, 1.510878, 2.100076",\ + "0.963652, 1.179082, 1.367711, 1.671906, 2.261104",\ + "1.543628, 1.759057, 1.947685, 2.251881, 2.841079",\ + "1.060318, 1.240956, 1.427923, 1.731662, 2.319967",\ + "1.092348, 1.272986, 1.459953, 1.763692, 2.351997",\ + "1.142736, 1.323375, 1.510341, 1.814080, 2.402385",\ + "1.303765, 1.484404, 1.671369, 1.975107, 2.563413",\ + "1.883740, 2.064379, 2.251344, 2.555082, 3.143388"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417786, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484506, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484494",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059265, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417785, 0.417783, 0.417783, 0.417777, 0.417763",\ + "1.484505, 1.484504, 1.484504, 1.484501, 1.484493"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2463*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[38]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.490508, 0.711036, 0.888618, 1.176984, 1.736809",\ + "0.532203, 0.752732, 0.930314, 1.218679, 1.778504",\ + "0.608383, 0.828912, 1.006494, 1.294859, 1.854684",\ + "0.863773, 1.084302, 1.261884, 1.550249, 2.110074",\ + "1.788229, 2.008758, 2.186340, 2.474705, 3.034531",\ + "0.578896, 0.798355, 0.975899, 1.264289, 1.824162",\ + "0.620592, 0.840050, 1.017595, 1.305984, 1.865858",\ + "0.696772, 0.916230, 1.093775, 1.382164, 1.942038",\ + "0.952161, 1.171620, 1.349165, 1.637554, 2.197427",\ + "1.876618, 2.096076, 2.273621, 2.562011, 3.121884",\ + "0.668261, 0.878687, 1.055926, 1.344317, 1.904194",\ + "0.709957, 0.920382, 1.097622, 1.386013, 1.945889",\ + "0.786137, 0.996562, 1.173802, 1.462193, 2.022069",\ + "1.041527, 1.251952, 1.429191, 1.717583, 2.277459",\ + "1.965983, 2.176409, 2.353648, 2.642039, 3.201916",\ + "0.731942, 0.936503, 1.113619, 1.401746, 1.961208",\ + "0.773637, 0.978198, 1.155315, 1.443442, 2.002903",\ + "0.849817, 1.054379, 1.231495, 1.519622, 2.079083",\ + "1.105207, 1.309768, 1.486884, 1.775012, 2.334473",\ + "2.029663, 2.234225, 2.411341, 2.699468, 3.258930",\ + "1.063585, 1.241717, 1.417274, 1.704917, 2.263427",\ + "1.105281, 1.283412, 1.458970, 1.746613, 2.305123",\ + "1.181460, 1.359592, 1.535150, 1.822793, 2.381303",\ + "1.436850, 1.614982, 1.790540, 2.078182, 2.636693",\ + "2.361307, 2.539439, 2.714996, 3.002639, 3.561149"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199409, 0.199409, 0.199409, 0.199409, 0.199410",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.510756, 0.731284, 0.908866, 1.197232, 1.757056",\ + "0.543002, 0.763530, 0.941112, 1.229478, 1.789302",\ + "0.593318, 0.813846, 0.991428, 1.279794, 1.839619",\ + "0.753982, 0.974510, 1.152092, 1.440458, 2.000283",\ + "1.335097, 1.555626, 1.733208, 2.021573, 2.581398",\ + "0.599144, 0.818602, 0.996147, 1.284537, 1.844410",\ + "0.631390, 0.850848, 1.028393, 1.316783, 1.876656",\ + "0.681706, 0.901165, 1.078709, 1.367099, 1.926972",\ + "0.842370, 1.061828, 1.239373, 1.527763, 2.087636",\ + "1.423486, 1.642944, 1.820489, 2.108878, 2.668751",\ + "0.688509, 0.898935, 1.076174, 1.364565, 1.924441",\ + "0.720755, 0.931181, 1.108420, 1.396811, 1.956687",\ + "0.771071, 0.981497, 1.158736, 1.447127, 2.007004",\ + "0.931735, 1.142161, 1.319400, 1.607791, 2.167668",\ + "1.512851, 1.723276, 1.900516, 2.188907, 2.748783",\ + "0.752190, 0.956751, 1.133867, 1.421994, 1.981456",\ + "0.784436, 0.988997, 1.166113, 1.454240, 2.013701",\ + "0.834752, 1.039313, 1.216429, 1.504556, 2.064018",\ + "0.995416, 1.199977, 1.377093, 1.665220, 2.224682",\ + "1.576531, 1.781092, 1.958208, 2.246336, 2.805797",\ + "1.083833, 1.261965, 1.437522, 1.725165, 2.283675",\ + "1.116079, 1.294211, 1.469768, 1.757411, 2.315921",\ + "1.166395, 1.344527, 1.520084, 1.807727, 2.366237",\ + "1.327059, 1.505191, 1.680748, 1.968391, 2.526901",\ + "1.908174, 2.086306, 2.261864, 2.549506, 3.108017"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029703",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419479, 0.419479, 0.419479, 0.419479, 0.419479",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2279*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.464141, 0.703934, 0.888128, 1.182401, 1.751067",\ + "0.505836, 0.745630, 0.929824, 1.224097, 1.792763",\ + "0.582016, 0.821810, 1.006004, 1.300277, 1.868943",\ + "0.837406, 1.077200, 1.261394, 1.555666, 2.124333",\ + "1.761863, 2.001656, 2.185850, 2.480123, 3.048789",\ + "0.552479, 0.791253, 0.975409, 1.269706, 1.838421",\ + "0.594175, 0.832948, 1.017105, 1.311402, 1.880116",\ + "0.670355, 0.909128, 1.093285, 1.387582, 1.956296",\ + "0.925745, 1.164518, 1.348675, 1.642971, 2.211686",\ + "1.850201, 2.088974, 2.273131, 2.567428, 3.136143",\ + "0.641618, 0.871586, 1.055436, 1.349735, 1.918452",\ + "0.683313, 0.913281, 1.097132, 1.391430, 1.960148",\ + "0.759493, 0.989461, 1.173312, 1.467610, 2.036328",\ + "1.014883, 1.244851, 1.428701, 1.723000, 2.291718",\ + "1.939340, 2.169307, 2.353158, 2.647456, 3.216174",\ + "0.705051, 0.929417, 1.113144, 1.407174, 1.975487",\ + "0.746746, 0.971112, 1.154840, 1.448870, 2.017183",\ + "0.822926, 1.047292, 1.231020, 1.525050, 2.093363",\ + "1.078316, 1.302682, 1.486409, 1.780439, 2.348753",\ + "2.002773, 2.227139, 2.410866, 2.704896, 3.273209",\ + "1.040106, 1.234739, 1.416802, 1.710354, 2.277733",\ + "1.081802, 1.276435, 1.458498, 1.752050, 2.319428",\ + "1.157982, 1.352615, 1.534678, 1.828230, 2.395608",\ + "1.413371, 1.608004, 1.790067, 2.083619, 2.650998",\ + "2.337828, 2.532461, 2.714524, 3.008076, 3.575455"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070076, 0.070076, 0.070076, 0.070076, 0.070076",\ + "0.199408, 0.199408, 0.199409, 0.199409, 0.199411",\ + "0.685874, 0.685874, 0.685874, 0.685874, 0.685874",\ + "2.455194, 2.455194, 2.455194, 2.455194, 2.455194"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.484389, 0.724182, 0.908376, 1.202649, 1.771315",\ + "0.516635, 0.756428, 0.940622, 1.234895, 1.803561",\ + "0.566951, 0.806745, 0.990938, 1.285211, 1.853878",\ + "0.727615, 0.967409, 1.151602, 1.445875, 2.014541",\ + "1.308730, 1.548524, 1.732718, 2.026990, 2.595657",\ + "0.572727, 0.811501, 0.995657, 1.289954, 1.858669",\ + "0.604973, 0.843747, 1.027903, 1.322200, 1.890915",\ + "0.655290, 0.894063, 1.078219, 1.372516, 1.941231",\ + "0.815953, 1.054727, 1.238883, 1.533180, 2.101895",\ + "1.397069, 1.635842, 1.819999, 2.114295, 2.683010",\ + "0.661866, 0.891834, 1.075684, 1.369982, 1.938700",\ + "0.694112, 0.924080, 1.107930, 1.402228, 1.970946",\ + "0.744428, 0.974396, 1.158246, 1.452545, 2.021263",\ + "0.905092, 1.135060, 1.318910, 1.613209, 2.181926",\ + "1.486207, 1.716175, 1.900026, 2.194324, 2.763042",\ + "0.725299, 0.949665, 1.133392, 1.427422, 1.995735",\ + "0.757545, 0.981911, 1.165638, 1.459668, 2.027981",\ + "0.807861, 1.032227, 1.215954, 1.509984, 2.078298",\ + "0.968525, 1.192891, 1.376618, 1.670648, 2.238961",\ + "1.549640, 1.774006, 1.957734, 2.251764, 2.820077",\ + "1.060354, 1.254987, 1.437050, 1.730602, 2.297981",\ + "1.092600, 1.287233, 1.469296, 1.762848, 2.330226",\ + "1.142916, 1.337549, 1.519612, 1.813164, 2.380543",\ + "1.303580, 1.498213, 1.680276, 1.973828, 2.541207",\ + "1.884696, 2.079328, 2.261392, 2.554944, 3.122322"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052",\ + "0.029703, 0.029703, 0.029703, 0.029703, 0.029704",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131484, 0.131484, 0.131484, 0.131485, 0.131485",\ + "0.419474, 0.419474, 0.419474, 0.419474, 0.419474",\ + "1.483052, 1.483052, 1.483052, 1.483052, 1.483052"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2323*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.411437, 0.641763, 0.827440, 1.121826, 1.689429",\ + "0.453163, 0.683488, 0.869165, 1.163551, 1.731154",\ + "0.529220, 0.759545, 0.945221, 1.239608, 1.807211",\ + "0.784777, 1.015107, 1.200787, 1.495173, 2.062773",\ + "1.709036, 1.939362, 2.125040, 2.419426, 2.987028",\ + "0.499750, 0.729081, 0.914721, 1.209131, 1.776782",\ + "0.541475, 0.770807, 0.956446, 1.250857, 1.818508",\ + "0.617533, 0.846863, 1.032502, 1.326913, 1.894564",\ + "0.873090, 1.102426, 1.288068, 1.582478, 2.150126",\ + "1.797349, 2.026680, 2.212321, 2.506731, 3.074381",\ + "0.588895, 0.809414, 0.994747, 1.289160, 1.856814",\ + "0.630620, 0.851139, 1.036473, 1.330885, 1.898539",\ + "0.706677, 0.927196, 1.112529, 1.406941, 1.974596",\ + "0.962234, 1.182758, 1.368095, 1.662507, 2.230158",\ + "1.886493, 2.107013, 2.292347, 2.586760, 3.154413",\ + "0.652369, 0.867238, 1.052459, 1.346598, 1.913847",\ + "0.694094, 0.908963, 1.094185, 1.388323, 1.955572",\ + "0.770151, 0.985020, 1.170241, 1.464380, 2.031629",\ + "1.025709, 1.240582, 1.425807, 1.719945, 2.287190",\ + "1.949967, 2.164837, 2.350059, 2.644198, 3.211446",\ + "0.987682, 1.172511, 1.356118, 1.649777, 2.216089",\ + "1.029408, 1.214237, 1.397843, 1.691502, 2.257815",\ + "1.105465, 1.290294, 1.473899, 1.767559, 2.333871",\ + "1.361025, 1.545856, 1.729465, 2.023124, 2.589433",\ + "2.285281, 2.470111, 2.653718, 2.947377, 3.513689"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686589, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070223, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686588, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452423",\ + "0.025366, 0.025366, 0.025366, 0.025366, 0.025366",\ + "0.070222, 0.070222, 0.070221, 0.070221, 0.070221",\ + "0.199530, 0.199530, 0.199530, 0.199530, 0.199530",\ + "0.686585, 0.686583, 0.686578, 0.686576, 0.686576",\ + "2.452462, 2.452462, 2.452462, 2.452450, 2.452422"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.434036, 0.664363, 0.850040, 1.144426, 1.712028",\ + "0.466066, 0.696393, 0.882070, 1.176457, 1.744059",\ + "0.516455, 0.746780, 0.932457, 1.226843, 1.794446",\ + "0.677484, 0.907807, 1.093482, 1.387868, 1.955473",\ + "1.257459, 1.487782, 1.673457, 1.967843, 2.535448",\ + "0.522349, 0.751681, 0.937321, 1.231731, 1.799382",\ + "0.554379, 0.783711, 0.969351, 1.263762, 1.831412",\ + "0.604768, 0.834099, 1.019738, 1.314148, 1.881800",\ + "0.765797, 0.995125, 1.180763, 1.475173, 2.042827",\ + "1.345772, 1.575100, 1.760738, 2.055148, 2.622802",\ + "0.611494, 0.832013, 1.017348, 1.311760, 1.879413",\ + "0.643524, 0.864044, 1.049378, 1.343790, 1.911444",\ + "0.693912, 0.914431, 1.099764, 1.394177, 1.961831",\ + "0.854941, 1.075458, 1.260790, 1.555202, 2.122858",\ + "1.434916, 1.655433, 1.840765, 2.135177, 2.702833",\ + "0.674968, 0.889838, 1.075059, 1.369198, 1.936446",\ + "0.706998, 0.921868, 1.107090, 1.401229, 1.968477",\ + "0.757386, 0.972255, 1.157476, 1.451615, 2.018864",\ + "0.918415, 1.133282, 1.318501, 1.612640, 2.179891",\ + "1.498390, 1.713257, 1.898476, 2.192615, 2.759866",\ + "1.010282, 1.195111, 1.378718, 1.672377, 2.238689",\ + "1.042312, 1.227141, 1.410748, 1.704407, 2.270719",\ + "1.092700, 1.277529, 1.461135, 1.754794, 2.321106",\ + "1.253727, 1.438555, 1.622160, 1.915819, 2.482133",\ + "1.833702, 2.018530, 2.202135, 2.495794, 3.062109"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496",\ + "0.029863, 0.029863, 0.029863, 0.029863, 0.029863",\ + "0.059264, 0.059264, 0.059264, 0.059264, 0.059262",\ + "0.131521, 0.131521, 0.131521, 0.131521, 0.131521",\ + "0.417782, 0.417782, 0.417782, 0.417778, 0.417769",\ + "1.484504, 1.484504, 1.484504, 1.484501, 1.484496"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2346*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.554942, 0.776691, 0.954630, 1.243547, 1.804386",\ + "0.596638, 0.818387, 0.996327, 1.285244, 1.846083",\ + "0.672820, 0.894569, 1.072508, 1.361425, 1.922264",\ + "0.928215, 1.149964, 1.327903, 1.616820, 2.177659",\ + "1.852598, 2.074347, 2.252286, 2.541204, 3.102043",\ + "0.643350, 0.864010, 1.041911, 1.330852, 1.891740",\ + "0.685047, 0.905706, 1.083608, 1.372549, 1.933436",\ + "0.761228, 0.981887, 1.159789, 1.448730, 2.009617",\ + "1.016623, 1.237282, 1.415184, 1.704125, 2.265012",\ + "1.941007, 2.161666, 2.339567, 2.628509, 3.189397",\ + "0.732441, 0.944345, 1.121938, 1.410881, 1.971771",\ + "0.774137, 0.986041, 1.163634, 1.452577, 2.013468",\ + "0.850318, 1.062222, 1.239816, 1.528758, 2.089649",\ + "1.105714, 1.317617, 1.495211, 1.784153, 2.345044",\ + "2.030097, 2.242001, 2.419594, 2.708537, 3.269428",\ + "0.795719, 1.002162, 1.179631, 1.468310, 2.028787",\ + "0.837415, 1.043858, 1.221328, 1.510007, 2.070483",\ + "0.913596, 1.120039, 1.297509, 1.586188, 2.146664",\ + "1.168992, 1.375434, 1.552904, 1.841583, 2.402059",\ + "2.093375, 2.299818, 2.477287, 2.765967, 3.326444",\ + "1.127968, 1.307390, 1.483287, 1.771482, 2.331008",\ + "1.169664, 1.349087, 1.524984, 1.813179, 2.372704",\ + "1.245846, 1.425268, 1.601165, 1.889360, 2.448885",\ + "1.501241, 1.680663, 1.856560, 2.144755, 2.704280",\ + "2.425624, 2.605047, 2.780944, 3.069139, 3.628665"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199414",\ + "0.685793, 0.685793, 0.685793, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.575187, 0.796936, 0.974876, 1.263793, 1.824632",\ + "0.607437, 0.829186, 1.007125, 1.296042, 1.856881",\ + "0.657749, 0.879498, 1.057438, 1.346354, 1.907194",\ + "0.818413, 1.040162, 1.218101, 1.507018, 2.067857",\ + "1.399546, 1.621294, 1.799234, 2.088151, 2.648989",\ + "0.663596, 0.884255, 1.062156, 1.351098, 1.911985",\ + "0.695845, 0.916504, 1.094406, 1.383347, 1.944234",\ + "0.746158, 0.966817, 1.144718, 1.433660, 1.994547",\ + "0.906821, 1.127481, 1.305382, 1.594323, 2.155211",\ + "1.487954, 1.708613, 1.886515, 2.175456, 2.736343",\ + "0.752686, 0.964590, 1.142183, 1.431126, 1.992017",\ + "0.784936, 0.996840, 1.174433, 1.463375, 2.024266",\ + "0.835248, 1.047152, 1.224745, 1.513688, 2.074579",\ + "0.995912, 1.207816, 1.385409, 1.674352, 2.235242",\ + "1.577044, 1.788948, 1.966541, 2.255484, 2.816375",\ + "0.815964, 1.022407, 1.199876, 1.488556, 2.049032",\ + "0.848214, 1.054656, 1.232126, 1.520805, 2.081281",\ + "0.898526, 1.104969, 1.282438, 1.571118, 2.131594",\ + "1.059190, 1.265632, 1.443102, 1.731781, 2.292258",\ + "1.640322, 1.846765, 2.024235, 2.312914, 2.873390",\ + "1.148213, 1.327636, 1.503533, 1.791728, 2.351253",\ + "1.180463, 1.359885, 1.535782, 1.823977, 2.383502",\ + "1.230775, 1.410198, 1.586095, 1.874290, 2.433815",\ + "1.391439, 1.570861, 1.746758, 2.034954, 2.594479",\ + "1.972571, 2.151994, 2.327891, 2.616086, 3.175611"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2465*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.533753, 0.762081, 0.946644, 1.241934, 1.812791",\ + "0.575449, 0.803777, 0.988340, 1.283630, 1.854487",\ + "0.651630, 0.879958, 1.064522, 1.359811, 1.930668",\ + "0.907026, 1.135353, 1.319917, 1.615206, 2.186064",\ + "1.831408, 2.059737, 2.244300, 2.539591, 3.110448",\ + "0.622078, 0.849399, 1.033925, 1.329239, 1.900144",\ + "0.663775, 0.891095, 1.075621, 1.370935, 1.941841",\ + "0.739956, 0.967276, 1.151803, 1.447117, 2.018022",\ + "0.995351, 1.222671, 1.407198, 1.702512, 2.273417",\ + "1.919734, 2.147055, 2.331581, 2.626896, 3.197802",\ + "0.711467, 0.929729, 1.113952, 1.409267, 1.980176",\ + "0.753164, 0.971426, 1.155648, 1.450964, 2.021872",\ + "0.829345, 1.047607, 1.231829, 1.527145, 2.098053",\ + "1.084740, 1.303002, 1.487225, 1.782540, 2.353448",\ + "2.009123, 2.227385, 2.411608, 2.706924, 3.277833",\ + "0.775260, 0.987553, 1.171661, 1.466710, 2.037218",\ + "0.816956, 1.029250, 1.213358, 1.508406, 2.078914",\ + "0.893137, 1.105431, 1.289539, 1.584587, 2.155095",\ + "1.148533, 1.360826, 1.544934, 1.839983, 2.410490",\ + "2.072916, 2.285210, 2.469318, 2.764367, 3.334875",\ + "1.112589, 1.292819, 1.475319, 1.769892, 2.339470",\ + "1.154285, 1.334515, 1.517015, 1.811588, 2.381167",\ + "1.230466, 1.410696, 1.593196, 1.887769, 2.457348",\ + "1.485862, 1.666091, 1.848592, 2.143165, 2.712743",\ + "2.410245, 2.590475, 2.772975, 3.067549, 3.637128"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200",\ + "0.025314, 0.025314, 0.025314, 0.025314, 0.025314",\ + "0.070068, 0.070068, 0.070068, 0.070069, 0.070069",\ + "0.199414, 0.199414, 0.199414, 0.199414, 0.199415",\ + "0.685793, 0.685793, 0.685794, 0.685794, 0.685795",\ + "2.455201, 2.455201, 2.455201, 2.455201, 2.455200"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.553998, 0.782326, 0.966889, 1.262179, 1.833036",\ + "0.586248, 0.814575, 0.999139, 1.294429, 1.865286",\ + "0.636560, 0.864888, 1.049451, 1.344741, 1.915598",\ + "0.797224, 1.025552, 1.210115, 1.505405, 2.076262",\ + "1.378356, 1.606684, 1.791247, 2.086537, 2.657394",\ + "0.642324, 0.869644, 1.054170, 1.349484, 1.920390",\ + "0.674573, 0.901893, 1.086420, 1.381734, 1.952639",\ + "0.724886, 0.952206, 1.136732, 1.432046, 2.002952",\ + "0.885549, 1.112870, 1.297396, 1.592710, 2.163615",\ + "1.466682, 1.694002, 1.878528, 2.173842, 2.744748",\ + "0.731713, 0.949975, 1.134197, 1.429513, 2.000421",\ + "0.763962, 0.982224, 1.166447, 1.461762, 2.032670",\ + "0.814275, 1.032536, 1.216759, 1.512075, 2.082983",\ + "0.974938, 1.193200, 1.377423, 1.672738, 2.243647",\ + "1.556071, 1.774333, 1.958555, 2.253871, 2.824779",\ + "0.795505, 1.007799, 1.191907, 1.486955, 2.057463",\ + "0.827755, 1.040048, 1.224156, 1.519205, 2.089712",\ + "0.878067, 1.090361, 1.274469, 1.569517, 2.140025",\ + "1.038731, 1.251024, 1.435133, 1.730181, 2.300689",\ + "1.619863, 1.832157, 2.016265, 2.311313, 2.881821",\ + "1.132834, 1.313064, 1.495564, 1.790137, 2.359716",\ + "1.165084, 1.345313, 1.527814, 1.822387, 2.391965",\ + "1.215396, 1.395626, 1.578126, 1.872699, 2.442278",\ + "1.376060, 1.556290, 1.738790, 2.033363, 2.602942",\ + "1.957192, 2.137422, 2.319922, 2.614495, 3.184073"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003215, 0.011703, 0.042600, 0.154883"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983",\ + "0.029705, 0.029705, 0.029705, 0.029705, 0.029705",\ + "0.059407, 0.059407, 0.059407, 0.059407, 0.059407",\ + "0.131485, 0.131485, 0.131485, 0.131485, 0.131485",\ + "0.419472, 0.419472, 0.419472, 0.419472, 0.419472",\ + "1.482982, 1.482982, 1.482982, 1.482983, 1.482983"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[6]_redg_min_2401*/ + +} /* end of pin tl_o[6] */ + +pin("tl_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.035370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.586415, 0.856406, 1.147453, 1.645288, 2.640958",\ + "0.600096, 0.870093, 1.161170, 1.659087, 2.654921",\ + "0.623625, 0.893621, 1.184696, 1.682603, 2.678417",\ + "0.891636, 1.161662, 1.452904, 1.951255, 2.947956",\ + "1.484832, 1.754906, 2.046407, 2.545443, 3.543516",\ + "0.673827, 0.943991, 1.235112, 1.732003, 2.726892",\ + "0.687508, 0.957678, 1.248830, 1.745802, 2.740855",\ + "0.711038, 0.981207, 1.272355, 1.769318, 2.764350",\ + "0.979048, 1.249249, 1.540565, 2.037970, 3.033889",\ + "1.572245, 1.842492, 2.134070, 2.632158, 3.629450",\ + "0.756613, 1.033065, 1.323078, 1.819625, 2.813847",\ + "0.770294, 1.046752, 1.336796, 1.833425, 2.827810",\ + "0.793824, 1.070281, 1.360321, 1.856940, 2.851305",\ + "1.061835, 1.338323, 1.628531, 2.125592, 3.120844",\ + "1.655032, 1.931567, 2.222036, 2.719780, 3.716405",\ + "0.819991, 1.098835, 1.387222, 1.883539, 2.877356",\ + "0.833672, 1.112521, 1.400940, 1.897338, 2.891319",\ + "0.857202, 1.136050, 1.424465, 1.920853, 2.914814",\ + "1.125213, 1.404093, 1.692675, 2.189505, 3.184353",\ + "1.718410, 1.997339, 2.286180, 2.783694, 3.779914",\ + "1.154701, 1.464769, 1.739384, 2.233007, 3.222812",\ + "1.168382, 1.478458, 1.753102, 2.246807, 3.236775",\ + "1.191912, 1.501987, 1.776627, 2.270322, 3.260271",\ + "1.459925, 1.770039, 2.044842, 2.538976, 3.529809",\ + "2.053125, 2.363301, 2.638354, 3.133168, 4.125370"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.122235, 0.122284, 0.123237, 0.126336, 0.132533",\ + "0.151847, 0.152077, 0.152973, 0.155170, 0.159564",\ + "0.201011, 0.201013, 0.201253, 0.202081, 0.203737",\ + "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\ + "0.122235, 0.122284, 0.123247, 0.126336, 0.132533",\ + "0.151847, 0.152079, 0.152980, 0.155170, 0.159564",\ + "0.201011, 0.201013, 0.201256, 0.202081, 0.203737",\ + "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\ + "0.122236, 0.122285, 0.123247, 0.126336, 0.132533",\ + "0.151853, 0.152082, 0.152980, 0.155170, 0.159564",\ + "0.201011, 0.201013, 0.201256, 0.202081, 0.203737",\ + "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\ + "0.122236, 0.122286, 0.123248, 0.126336, 0.132533",\ + "0.151856, 0.152088, 0.152981, 0.155170, 0.159564",\ + "0.201011, 0.201013, 0.201256, 0.202081, 0.203737",\ + "0.823650, 0.823653, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222134, 2.222136, 2.222140, 2.222148",\ + "0.122239, 0.122302, 0.123279, 0.126348, 0.132533",\ + "0.151880, 0.152153, 0.153003, 0.155179, 0.159564",\ + "0.201011, 0.201014, 0.201264, 0.202084, 0.203737",\ + "0.823651, 0.823654, 0.823667, 0.823703, 0.823775",\ + "2.222134, 2.222135, 2.222136, 2.222140, 2.222148"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.525645, 0.795489, 1.085730, 1.581432, 2.572836",\ + "0.537639, 0.807524, 1.097989, 1.594284, 2.586873",\ + "0.557233, 0.827173, 1.117941, 1.615037, 2.609230",\ + "0.728499, 0.998614, 1.290344, 1.789985, 2.789268",\ + "1.063132, 1.333237, 1.624904, 2.124381, 3.123334",\ + "0.613058, 0.883074, 1.173382, 1.668147, 2.658770",\ + "0.625052, 0.895109, 1.185643, 1.680999, 2.672807",\ + "0.644646, 0.914759, 1.205598, 1.701752, 2.695163",\ + "0.815911, 1.086201, 1.378008, 1.876700, 2.875202",\ + "1.150545, 1.420823, 1.712568, 2.211096, 3.209268",\ + "0.695842, 0.972144, 1.261348, 1.755769, 2.745725",\ + "0.707837, 0.984180, 1.273609, 1.768621, 2.759762",\ + "0.727431, 1.003831, 1.293564, 1.789375, 2.782119",\ + "0.898699, 1.175277, 1.465974, 1.964322, 2.962157",\ + "1.233333, 1.509899, 1.800534, 2.298718, 3.296223",\ + "0.759218, 1.037910, 1.325492, 1.819683, 2.809234",\ + "0.771213, 1.049947, 1.337753, 1.832534, 2.823271",\ + "0.790808, 1.069599, 1.357708, 1.853288, 2.845628",\ + "0.962077, 1.241050, 1.530119, 2.028236, 3.025666",\ + "1.296711, 1.575672, 1.864679, 2.362631, 3.359732",\ + "1.093920, 1.403797, 1.677632, 2.169142, 3.154690",\ + "1.105917, 1.415847, 1.689899, 2.181997, 3.168727",\ + "1.125515, 1.435517, 1.709862, 2.202754, 3.191083",\ + "1.296794, 1.607024, 1.882299, 2.377712, 3.371122",\ + "1.631427, 1.941643, 2.216857, 2.712107, 3.705188"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.074841, 0.075254, 0.077521, 0.083520, 0.095518",\ + "0.080316, 0.080691, 0.082745, 0.088181, 0.099053",\ + "0.100360, 0.100711, 0.102633, 0.107721, 0.117897",\ + "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\ + "1.025905, 1.025920, 1.025979, 1.026125, 1.026416",\ + "0.074841, 0.075258, 0.077540, 0.083520, 0.095518",\ + "0.080316, 0.080694, 0.082762, 0.088181, 0.099053",\ + "0.100360, 0.100714, 0.102649, 0.107721, 0.117897",\ + "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\ + "1.025905, 1.025920, 1.025980, 1.026125, 1.026416",\ + "0.074846, 0.075266, 0.077540, 0.083520, 0.095518",\ + "0.080321, 0.080701, 0.082762, 0.088181, 0.099053",\ + "0.100365, 0.100721, 0.102650, 0.107721, 0.117897",\ + "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\ + "1.025905, 1.025920, 1.025980, 1.026125, 1.026416",\ + "0.074850, 0.075277, 0.077541, 0.083520, 0.095518",\ + "0.080324, 0.080712, 0.082763, 0.088181, 0.099053",\ + "0.100368, 0.100730, 0.102651, 0.107721, 0.117897",\ + "0.380688, 0.380691, 0.380703, 0.380732, 0.380789",\ + "1.025905, 1.025921, 1.025980, 1.026125, 1.026416",\ + "0.074873, 0.075411, 0.077602, 0.083545, 0.095518",\ + "0.080345, 0.080833, 0.082819, 0.088203, 0.099053",\ + "0.100387, 0.100844, 0.102702, 0.107742, 0.117897",\ + "0.380688, 0.380692, 0.380703, 0.380732, 0.380789",\ + "1.025907, 1.025925, 1.025981, 1.026126, 1.026416"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2627*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.792764, 1.054507, 1.346593, 1.853632, 2.867709",\ + "0.806316, 1.068059, 1.360145, 1.867184, 2.881261",\ + "0.829846, 1.091589, 1.383675, 1.890714, 2.904791",\ + "1.097219, 1.358962, 1.651048, 2.158087, 3.172164",\ + "1.691027, 1.952770, 2.244857, 2.751895, 3.765972",\ + "0.880176, 1.142082, 1.434281, 1.940346, 2.953642",\ + "0.893728, 1.155634, 1.447833, 1.953899, 2.967195",\ + "0.917258, 1.179164, 1.471363, 1.977429, 2.990725",\ + "1.184632, 1.446538, 1.738737, 2.244802, 3.258098",\ + "1.778440, 2.040346, 2.332545, 2.838610, 3.851906",\ + "0.961078, 1.231132, 1.522248, 2.027969, 3.040597",\ + "0.974630, 1.244684, 1.535800, 2.041521, 3.054150",\ + "0.998160, 1.268215, 1.559330, 2.065051, 3.077680",\ + "1.265533, 1.535588, 1.826703, 2.332424, 3.345053",\ + "1.859341, 2.129396, 2.420511, 2.926232, 3.938861",\ + "1.020773, 1.296868, 1.586394, 2.091882, 3.104106",\ + "1.034325, 1.310420, 1.599946, 2.105434, 3.117659",\ + "1.057855, 1.333951, 1.623476, 2.128964, 3.141189",\ + "1.325228, 1.601324, 1.890849, 2.396338, 3.408562",\ + "1.919036, 2.195132, 2.484657, 2.990146, 4.002370",\ + "1.354614, 1.662408, 1.938648, 2.441389, 3.449563",\ + "1.368166, 1.675960, 1.952201, 2.454941, 3.463115",\ + "1.391696, 1.699491, 1.975731, 2.478471, 3.486645",\ + "1.659069, 1.966864, 2.243104, 2.745844, 3.754018",\ + "2.252877, 2.560672, 2.836912, 3.339653, 4.347826"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.760378, 1.022121, 1.314208, 1.821246, 2.835323",\ + "0.768321, 1.030064, 1.322150, 1.829189, 2.843266",\ + "0.781801, 1.043544, 1.335630, 1.842669, 2.856746",\ + "0.935753, 1.197497, 1.489583, 1.996622, 3.010698",\ + "1.275653, 1.537396, 1.829482, 2.336521, 3.350598",\ + "0.847791, 1.109697, 1.401896, 1.907961, 2.921257",\ + "0.855733, 1.117639, 1.409838, 1.915904, 2.929199",\ + "0.869213, 1.131119, 1.423318, 1.929384, 2.942679",\ + "1.023166, 1.285072, 1.577271, 2.083336, 3.096632",\ + "1.363066, 1.624972, 1.917171, 2.423236, 3.436532",\ + "0.928693, 1.198747, 1.489862, 1.995583, 3.008212",\ + "0.936635, 1.206689, 1.497805, 2.003526, 3.016155",\ + "0.950115, 1.220170, 1.511285, 2.017006, 3.029634",\ + "1.104068, 1.374122, 1.665238, 2.170959, 3.183587",\ + "1.443967, 1.714022, 2.005137, 2.510858, 3.523487",\ + "0.988388, 1.264483, 1.554008, 2.059497, 3.071721",\ + "0.996330, 1.272425, 1.561951, 2.067439, 3.079664",\ + "1.009810, 1.285905, 1.575431, 2.080919, 3.093143",\ + "1.163763, 1.439858, 1.729384, 2.234872, 3.247096",\ + "1.503662, 1.779758, 2.069283, 2.574772, 3.586996",\ + "1.322228, 1.630023, 1.906263, 2.409003, 3.417177",\ + "1.330171, 1.637965, 1.914206, 2.416946, 3.425119",\ + "1.343651, 1.651445, 1.927685, 2.430426, 3.438600",\ + "1.497604, 1.805398, 2.081638, 2.584379, 3.592552",\ + "1.837503, 2.145298, 2.421538, 2.924278, 3.932452"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2734*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.773575, 1.028253, 1.310824, 1.779371, 2.716465",\ + "0.787127, 1.041805, 1.324376, 1.792923, 2.730017",\ + "0.810657, 1.065335, 1.347906, 1.816453, 2.753547",\ + "1.078030, 1.332708, 1.615279, 2.083826, 3.020920",\ + "1.671839, 1.926517, 2.209088, 2.677635, 3.614729",\ + "0.860984, 1.115846, 1.398389, 1.866085, 2.802399",\ + "0.874536, 1.129398, 1.411941, 1.879637, 2.815951",\ + "0.898067, 1.152928, 1.435471, 1.903167, 2.839481",\ + "1.165440, 1.420301, 1.702844, 2.170541, 3.106854",\ + "1.759248, 2.014110, 2.296653, 2.764349, 3.700663",\ + "0.941840, 1.204919, 1.486352, 1.953707, 2.889354",\ + "0.955392, 1.218471, 1.499904, 1.967259, 2.902906",\ + "0.978923, 1.242001, 1.523435, 1.990789, 2.926436",\ + "1.246296, 1.509374, 1.790808, 2.258162, 3.193809",\ + "1.840104, 2.103183, 2.384616, 2.851971, 3.787618",\ + "0.999500, 1.270687, 1.550492, 2.017620, 2.952863",\ + "1.013052, 1.284239, 1.564044, 2.031172, 2.966415",\ + "1.036583, 1.307769, 1.587574, 2.054702, 2.989945",\ + "1.303956, 1.575142, 1.854947, 2.322075, 3.257318",\ + "1.897764, 2.168951, 2.448756, 2.915884, 3.851127",\ + "1.331207, 1.636652, 1.902354, 2.366964, 3.298319",\ + "1.344759, 1.650204, 1.915906, 2.380516, 3.311871",\ + "1.368289, 1.673734, 1.939437, 2.404047, 3.335401",\ + "1.635662, 1.941107, 2.206810, 2.671420, 3.602774",\ + "2.229471, 2.534916, 2.800618, 3.265228, 4.196583"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121333, 0.121333, 0.121333",\ + "0.151701, 0.151701, 0.151701, 0.151701, 0.151701",\ + "0.201129, 0.201129, 0.201129, 0.201129, 0.201129",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.741190, 0.995868, 1.278439, 1.746986, 2.684080",\ + "0.749133, 1.003811, 1.286381, 1.754929, 2.692023",\ + "0.762613, 1.017291, 1.299861, 1.768409, 2.705503",\ + "0.916565, 1.171243, 1.453814, 1.922361, 2.859455",\ + "1.256465, 1.511143, 1.793714, 2.262261, 3.199355",\ + "0.828600, 1.083461, 1.366004, 1.833700, 2.770014",\ + "0.836542, 1.091403, 1.373946, 1.841643, 2.777956",\ + "0.850022, 1.104883, 1.387426, 1.855123, 2.791436",\ + "1.003975, 1.258836, 1.541379, 2.009076, 2.945389",\ + "1.343874, 1.598736, 1.881279, 2.348975, 3.285289",\ + "0.909456, 1.172534, 1.453968, 1.921322, 2.856969",\ + "0.917398, 1.180476, 1.461910, 1.929265, 2.864911",\ + "0.930878, 1.193956, 1.475390, 1.942744, 2.878391",\ + "1.084831, 1.347909, 1.629343, 2.096697, 3.032344",\ + "1.424730, 1.687809, 1.969242, 2.436597, 3.372244",\ + "0.967116, 1.238302, 1.518107, 1.985235, 2.920478",\ + "0.975058, 1.246245, 1.526050, 1.993178, 2.928420",\ + "0.988538, 1.259725, 1.539530, 2.006658, 2.941900",\ + "1.142491, 1.413677, 1.693483, 2.160611, 3.095853",\ + "1.482390, 1.753577, 2.033382, 2.500510, 3.435753",\ + "1.298822, 1.604267, 1.869970, 2.334579, 3.265934",\ + "1.306764, 1.612210, 1.877912, 2.342522, 3.273876",\ + "1.320244, 1.625690, 1.891392, 2.356002, 3.287356",\ + "1.474197, 1.779642, 2.045345, 2.509955, 3.441309",\ + "1.814097, 2.119542, 2.385244, 2.849854, 3.781209"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895",\ + "0.061223, 0.061223, 0.061223, 0.061223, 0.061223",\ + "0.068571, 0.068571, 0.068571, 0.068571, 0.068571",\ + "0.090396, 0.090396, 0.090396, 0.090396, 0.090396",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025895"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.741012, 0.979467, 1.257014, 1.743332, 2.715968",\ + "0.754606, 0.993061, 1.270608, 1.756926, 2.729561",\ + "0.778146, 1.016601, 1.294148, 1.780466, 2.753102",\ + "1.045683, 1.284138, 1.561685, 2.048002, 3.020638",\ + "1.638147, 1.876602, 2.154149, 2.640466, 3.613101",\ + "0.828421, 1.066996, 1.344635, 1.830046, 2.801901",\ + "0.842015, 1.080589, 1.358228, 1.843640, 2.815495",\ + "0.865555, 1.104130, 1.381769, 1.867180, 2.839035",\ + "1.133092, 1.371667, 1.649306, 2.134717, 3.106571",\ + "1.725556, 1.964131, 2.241770, 2.727180, 3.699034",\ + "0.909283, 1.155921, 1.432599, 1.917668, 2.888856",\ + "0.922877, 1.169514, 1.446193, 1.931262, 2.902450",\ + "0.946417, 1.193055, 1.469733, 1.954802, 2.925990",\ + "1.213954, 1.460592, 1.737270, 2.222339, 3.193527",\ + "1.806418, 2.053056, 2.329734, 2.814802, 3.785990",\ + "0.966958, 1.221474, 1.496742, 1.981581, 2.952365",\ + "0.980552, 1.235068, 1.510336, 1.995175, 2.965959",\ + "1.004092, 1.258608, 1.533876, 2.018715, 2.989499",\ + "1.271629, 1.526145, 1.801413, 2.286252, 3.257035",\ + "1.864093, 2.118609, 2.393877, 2.878715, 3.849499",\ + "1.288363, 1.584928, 1.848784, 2.330998, 3.297822",\ + "1.301956, 1.598522, 1.862378, 2.344592, 3.311415",\ + "1.325497, 1.622062, 1.885918, 2.368132, 3.334955",\ + "1.593034, 1.889599, 2.153455, 2.635669, 3.602492",\ + "2.185498, 2.482063, 2.745919, 3.228132, 4.194955"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121484",\ + "0.152032, 0.152032, 0.152032, 0.152031, 0.152028",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.682520, 0.920976, 1.198522, 1.684841, 2.657480",\ + "0.693882, 0.932337, 1.209884, 1.696203, 2.668840",\ + "0.712620, 0.951075, 1.228621, 1.714940, 2.687577",\ + "0.881167, 1.119623, 1.397169, 1.883486, 2.856120",\ + "1.215977, 1.454432, 1.731979, 2.218296, 3.190930",\ + "0.769929, 1.008504, 1.286143, 1.771556, 2.743413",\ + "0.781291, 1.019865, 1.297505, 1.782917, 2.754774",\ + "0.800029, 1.038603, 1.316242, 1.801654, 2.773510",\ + "0.968576, 1.207151, 1.484790, 1.970200, 2.942054",\ + "1.303386, 1.541960, 1.819599, 2.305010, 3.276864",\ + "0.850791, 1.097429, 1.374108, 1.859177, 2.830368",\ + "0.862152, 1.108790, 1.385469, 1.870539, 2.841729",\ + "0.880890, 1.127528, 1.404207, 1.889276, 2.860465",\ + "1.049438, 1.296076, 1.572754, 2.057822, 3.029009",\ + "1.384248, 1.630886, 1.907564, 2.392632, 3.363819",\ + "0.908466, 1.162982, 1.438250, 1.923091, 2.893877",\ + "0.919828, 1.174344, 1.449612, 1.934452, 2.905238",\ + "0.938565, 1.193082, 1.468349, 1.953189, 2.923974",\ + "1.107113, 1.361629, 1.636897, 2.121735, 3.092518",\ + "1.441923, 1.696439, 1.971707, 2.456545, 3.427328",\ + "1.229871, 1.526436, 1.790293, 2.272508, 3.239333",\ + "1.241232, 1.537798, 1.801654, 2.283869, 3.250694",\ + "1.259970, 1.556535, 1.820392, 2.302606, 3.269430",\ + "1.428518, 1.725083, 1.988939, 2.471152, 3.437974",\ + "1.763328, 2.059893, 2.323749, 2.805962, 3.772784"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\ + "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\ + "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\ + "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917",\ + "0.068436, 0.068436, 0.068435, 0.068432, 0.068425",\ + "0.074512, 0.074512, 0.074511, 0.074509, 0.074503",\ + "0.094928, 0.094928, 0.094927, 0.094924, 0.094919",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025917"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2374*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.697898, 0.947965, 1.225734, 1.724852, 2.723087",\ + "0.711492, 0.961559, 1.239327, 1.738445, 2.736680",\ + "0.735032, 0.985099, 1.262868, 1.761985, 2.760221",\ + "1.002569, 1.252636, 1.530404, 2.029521, 3.027754",\ + "1.595033, 1.845100, 2.122868, 2.621982, 3.620212",\ + "0.785303, 1.035477, 1.313393, 1.811565, 2.809021",\ + "0.798897, 1.049071, 1.326987, 1.825159, 2.822614",\ + "0.822437, 1.072611, 1.350527, 1.848699, 2.846154",\ + "1.089974, 1.340148, 1.618063, 2.116235, 3.113688",\ + "1.682438, 1.932612, 2.210527, 2.708696, 3.706145",\ + "0.866148, 1.124350, 1.401358, 1.899186, 2.895976",\ + "0.879741, 1.137944, 1.414951, 1.912780, 2.909569",\ + "0.903282, 1.161484, 1.438491, 1.936320, 2.933109",\ + "1.170819, 1.429021, 1.706028, 2.203856, 3.200643",\ + "1.763283, 2.021485, 2.298491, 2.796317, 3.793100",\ + "0.926036, 1.189827, 1.465502, 1.963099, 2.959485",\ + "0.939630, 1.203421, 1.479096, 1.976693, 2.973078",\ + "0.963170, 1.226961, 1.502636, 2.000233, 2.996618",\ + "1.230707, 1.494498, 1.770173, 2.267768, 3.264152",\ + "1.823171, 2.086962, 2.362636, 2.860230, 3.856609",\ + "1.263356, 1.552433, 1.817672, 2.312566, 3.304941",\ + "1.276949, 1.566026, 1.831266, 2.326159, 3.318534",\ + "1.300490, 1.589567, 1.854806, 2.349699, 3.342074",\ + "1.568027, 1.857104, 2.122343, 2.617235, 3.609608",\ + "2.160491, 2.449568, 2.714806, 3.209696, 4.202065"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121483, 0.121479",\ + "0.152032, 0.152032, 0.152035, 0.152046, 0.152069",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823611",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.639406, 0.889474, 1.167244, 1.666367, 2.664614",\ + "0.650768, 0.900835, 1.178605, 1.677727, 2.675971",\ + "0.669506, 0.919573, 1.197342, 1.696462, 2.694701",\ + "0.838053, 1.088120, 1.365887, 1.865001, 2.863227",\ + "1.172863, 1.422930, 1.700697, 2.199811, 3.198038",\ + "0.726812, 0.976986, 1.254903, 1.753081, 2.750548",\ + "0.738173, 0.988347, 1.266264, 1.764440, 2.761904",\ + "0.756911, 1.007085, 1.285001, 1.783175, 2.780635",\ + "0.925458, 1.175632, 1.453547, 1.951714, 2.949161",\ + "1.260268, 1.510442, 1.788356, 2.286525, 3.283972",\ + "0.807656, 1.065858, 1.342867, 1.840702, 2.837503",\ + "0.819017, 1.077220, 1.354228, 1.852061, 2.848859",\ + "0.837755, 1.095958, 1.372966, 1.870796, 2.867590",\ + "1.006303, 1.264505, 1.541511, 2.039335, 3.036116",\ + "1.341113, 1.599315, 1.876321, 2.374146, 3.370927",\ + "0.867545, 1.131335, 1.407012, 1.904615, 2.901012",\ + "0.878906, 1.142697, 1.418373, 1.915974, 2.912368",\ + "0.897644, 1.161434, 1.437110, 1.934709, 2.931099",\ + "1.066191, 1.329982, 1.605656, 2.103248, 3.099625",\ + "1.401001, 1.664792, 1.940466, 2.438058, 3.434436",\ + "1.204864, 1.493941, 1.759182, 2.254081, 3.246468",\ + "1.216225, 1.505302, 1.770543, 2.265441, 3.257824",\ + "1.234963, 1.524040, 1.789280, 2.284176, 3.276555",\ + "1.403511, 1.692588, 1.957826, 2.452714, 3.445081",\ + "1.738321, 2.027398, 2.292636, 2.787525, 3.779892"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\ + "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\ + "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\ + "0.068435, 0.068435, 0.068431, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074508, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094924, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919",\ + "0.068435, 0.068435, 0.068430, 0.068415, 0.068383",\ + "0.074512, 0.074512, 0.074507, 0.074493, 0.074464",\ + "0.094928, 0.094928, 0.094923, 0.094910, 0.094883",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380691",\ + "1.025917, 1.025917, 1.025917, 1.025918, 1.025919"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2490*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.564894, 0.815791, 1.094396, 1.559341, 2.489231",\ + "0.578576, 0.829479, 1.108111, 1.573121, 2.503140",\ + "0.602105, 0.853007, 1.131636, 1.596638, 2.526642",\ + "0.870117, 1.121053, 1.399829, 1.865184, 2.795893",\ + "1.463316, 1.714304, 1.993307, 2.459207, 3.391007",\ + "0.652304, 0.903365, 1.181950, 1.646055, 2.575164",\ + "0.665985, 0.917053, 1.195665, 1.659835, 2.589074",\ + "0.689515, 0.940582, 1.219190, 1.683353, 2.612576",\ + "0.957527, 1.208627, 1.487384, 1.951898, 2.881827",\ + "1.550725, 1.801879, 2.080863, 2.545921, 3.476941",\ + "0.733136, 0.992396, 1.269913, 1.733677, 2.662119",\ + "0.746817, 1.006083, 1.283628, 1.747457, 2.676029",\ + "0.770346, 1.029612, 1.307153, 1.770974, 2.699531",\ + "1.038358, 1.297659, 1.575347, 2.039520, 2.968782",\ + "1.631557, 1.890911, 2.168827, 2.633543, 3.563896",\ + "0.790750, 1.058102, 1.334052, 1.797590, 2.725628",\ + "0.804431, 1.071790, 1.347767, 1.811370, 2.739538",\ + "0.827961, 1.095319, 1.371293, 1.834888, 2.763040",\ + "1.095973, 1.363366, 1.639486, 2.103433, 3.032291",\ + "1.689171, 1.956620, 2.232966, 2.697456, 3.627405",\ + "1.120458, 1.423346, 1.685878, 2.146919, 3.071084",\ + "1.134140, 1.437036, 1.699593, 2.160699, 3.084994",\ + "1.157669, 1.460564, 1.723119, 2.184217, 3.108496",\ + "1.425683, 1.728623, 1.991316, 2.452764, 3.377747",\ + "2.018884, 2.321894, 2.584802, 3.046790, 3.972861"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.122237, 0.122291, 0.122948, 0.124971, 0.129018",\ + "0.151797, 0.151880, 0.152446, 0.154040, 0.157229",\ + "0.201011, 0.201013, 0.201172, 0.201712, 0.202792",\ + "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\ + "0.122237, 0.122291, 0.122954, 0.124971, 0.129018",\ + "0.151797, 0.151881, 0.152451, 0.154040, 0.157229",\ + "0.201011, 0.201013, 0.201174, 0.201712, 0.202792",\ + "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\ + "0.122237, 0.122292, 0.122954, 0.124971, 0.129018",\ + "0.151797, 0.151883, 0.152451, 0.154040, 0.157229",\ + "0.201011, 0.201013, 0.201174, 0.201712, 0.202792",\ + "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\ + "0.122238, 0.122294, 0.122955, 0.124971, 0.129018",\ + "0.151797, 0.151885, 0.152452, 0.154040, 0.157229",\ + "0.201011, 0.201013, 0.201174, 0.201712, 0.202792",\ + "0.823650, 0.823653, 0.823665, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144",\ + "0.122241, 0.122311, 0.122975, 0.124980, 0.129018",\ + "0.151805, 0.151911, 0.152468, 0.154047, 0.157229",\ + "0.201012, 0.201014, 0.201180, 0.201714, 0.202792",\ + "0.823651, 0.823654, 0.823666, 0.823694, 0.823752",\ + "2.222134, 2.222134, 2.222135, 2.222138, 2.222144"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.504118, 0.754852, 1.032751, 1.495998, 2.422494",\ + "0.516114, 0.766894, 1.044988, 1.508707, 2.436146",\ + "0.535711, 0.786551, 1.064911, 1.529268, 2.457982",\ + "0.706984, 0.958018, 1.237222, 1.703603, 2.636367",\ + "1.041617, 1.292639, 1.571788, 2.038038, 2.970540",\ + "0.591527, 0.842425, 1.120299, 1.582713, 2.508428",\ + "0.603524, 0.854467, 1.132538, 1.595422, 2.522079",\ + "0.623120, 0.874125, 1.152463, 1.615983, 2.543916",\ + "0.794393, 1.045593, 1.324780, 1.790318, 2.722301",\ + "1.129027, 1.380214, 1.659346, 2.124753, 3.056474",\ + "0.672359, 0.931452, 1.208262, 1.670335, 2.595383",\ + "0.684355, 0.943495, 1.220501, 1.683044, 2.609035",\ + "0.703952, 0.963154, 1.240426, 1.703604, 2.630871",\ + "0.875225, 1.134627, 1.412743, 1.877940, 2.809256",\ + "1.209858, 1.469247, 1.747309, 2.212375, 3.143429",\ + "0.729973, 0.997154, 1.272401, 1.734248, 2.658892",\ + "0.741969, 1.009198, 1.284640, 1.746957, 2.672544",\ + "0.761566, 1.028859, 1.304565, 1.767518, 2.694380",\ + "0.932840, 1.200337, 1.476882, 1.941853, 2.872765",\ + "1.267473, 1.534957, 1.811448, 2.276288, 3.206938",\ + "1.059672, 1.362345, 1.624210, 2.083570, 3.004348",\ + "1.071671, 1.374403, 1.636453, 2.096281, 3.018000",\ + "1.091271, 1.394084, 1.656385, 2.116844, 3.039836",\ + "1.262555, 1.565626, 1.828723, 2.291188, 3.218221",\ + "1.597188, 1.900242, 2.163287, 2.625622, 3.552394"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.074860, 0.075317, 0.077304, 0.082076, 0.091621",\ + "0.080333, 0.080747, 0.082548, 0.086873, 0.095522",\ + "0.100376, 0.100764, 0.102449, 0.106497, 0.114592",\ + "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\ + "1.025901, 1.025907, 1.025944, 1.026050, 1.026262",\ + "0.074860, 0.075320, 0.077319, 0.082076, 0.091621",\ + "0.080333, 0.080751, 0.082562, 0.086873, 0.095522",\ + "0.100376, 0.100767, 0.102462, 0.106497, 0.114592",\ + "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\ + "1.025901, 1.025907, 1.025945, 1.026050, 1.026262",\ + "0.074860, 0.075329, 0.077319, 0.082076, 0.091621",\ + "0.080334, 0.080759, 0.082562, 0.086873, 0.095522",\ + "0.100376, 0.100774, 0.102462, 0.106497, 0.114592",\ + "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\ + "1.025901, 1.025907, 1.025945, 1.026050, 1.026262",\ + "0.074860, 0.075342, 0.077320, 0.082076, 0.091621",\ + "0.080334, 0.080770, 0.082563, 0.086873, 0.095522",\ + "0.100377, 0.100785, 0.102463, 0.106497, 0.114592",\ + "0.380687, 0.380688, 0.380696, 0.380717, 0.380759",\ + "1.025901, 1.025907, 1.025945, 1.026050, 1.026262",\ + "0.074886, 0.075492, 0.077368, 0.082096, 0.091621",\ + "0.080357, 0.080906, 0.082607, 0.086890, 0.095522",\ + "0.100399, 0.100912, 0.102504, 0.106513, 0.114592",\ + "0.380687, 0.380689, 0.380696, 0.380717, 0.380759",\ + "1.025902, 1.025909, 1.025946, 1.026050, 1.026262"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2519*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.601589, 0.856514, 1.112604, 1.552662, 2.432779",\ + "0.615142, 0.870066, 1.126156, 1.566215, 2.446333",\ + "0.638672, 0.893596, 1.149686, 1.589744, 2.469861",\ + "0.906045, 1.160969, 1.417061, 1.857126, 2.737255",\ + "1.499860, 1.754785, 2.010744, 2.450359, 3.329590",\ + "0.689139, 0.944005, 1.200076, 1.639375, 2.518713",\ + "0.702691, 0.957558, 1.213628, 1.652928, 2.532267",\ + "0.726222, 0.981088, 1.237158, 1.676457, 2.555795",\ + "0.993595, 1.248461, 1.504533, 1.943839, 2.823189",\ + "1.587410, 1.842276, 2.098214, 2.537072, 3.415524",\ + "0.778517, 1.032815, 1.288036, 1.726995, 2.605668",\ + "0.792069, 1.046367, 1.301588, 1.740548, 2.619222",\ + "0.815599, 1.069897, 1.325118, 1.764078, 2.642750",\ + "1.082972, 1.337270, 1.592493, 2.031459, 2.910144",\ + "1.676788, 1.931085, 2.186174, 2.624692, 3.502479",\ + "0.842460, 1.098198, 1.352170, 1.790908, 2.669177",\ + "0.856012, 1.111750, 1.365723, 1.804461, 2.682731",\ + "0.879542, 1.135280, 1.389253, 1.827990, 2.706259",\ + "1.146915, 1.402653, 1.656628, 2.095372, 2.973653",\ + "1.740730, 1.996469, 2.250309, 2.688605, 3.565988",\ + "1.180709, 1.459770, 1.703739, 2.140127, 3.014633",\ + "1.194261, 1.473322, 1.717291, 2.153680, 3.028187",\ + "1.217791, 1.496852, 1.740821, 2.177209, 3.051715",\ + "1.485164, 1.764225, 2.008196, 2.444591, 3.319109",\ + "2.078980, 2.358040, 2.601873, 3.037822, 3.911444"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201130, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121333, 0.121337, 0.121351, 0.121379",\ + "0.151701, 0.151701, 0.151700, 0.151698, 0.151693",\ + "0.201129, 0.201129, 0.201131, 0.201137, 0.201149",\ + "0.823409, 0.823409, 0.823407, 0.823401, 0.823387",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.569211, 0.824136, 1.079695, 1.517959, 2.394488",\ + "0.577154, 0.832078, 1.087637, 1.525902, 2.402431",\ + "0.590634, 0.845558, 1.101117, 1.539382, 2.415911",\ + "0.744587, 0.999511, 1.255305, 1.694361, 2.572475",\ + "1.084486, 1.339411, 1.594970, 2.033235, 2.909765",\ + "0.656761, 0.911627, 1.167161, 1.604672, 2.480422",\ + "0.664704, 0.919570, 1.175103, 1.612615, 2.488365",\ + "0.678184, 0.933050, 1.188583, 1.626095, 2.501845",\ + "0.832137, 1.087003, 1.342773, 1.781074, 2.658409",\ + "1.172036, 1.426902, 1.682436, 2.119948, 2.995698",\ + "0.746139, 1.000437, 1.255121, 1.692293, 2.567377",\ + "0.754081, 1.008379, 1.263063, 1.700235, 2.575320",\ + "0.767561, 1.021859, 1.276543, 1.713715, 2.588800",\ + "0.921514, 1.175812, 1.430733, 1.868695, 2.745364",\ + "1.261414, 1.515711, 1.770396, 2.207568, 3.082654",\ + "0.810081, 1.065820, 1.319255, 1.756205, 2.630886",\ + "0.818024, 1.073762, 1.327198, 1.764148, 2.638829",\ + "0.831504, 1.087242, 1.340678, 1.777627, 2.652309",\ + "0.985457, 1.241195, 1.494868, 1.932607, 2.808873",\ + "1.325356, 1.581095, 1.834530, 2.271481, 3.146163",\ + "1.148331, 1.427392, 1.670806, 2.105417, 2.976342",\ + "1.156273, 1.435334, 1.678748, 2.113359, 2.984285",\ + "1.169753, 1.448814, 1.692228, 2.126839, 2.997765",\ + "1.323706, 1.602767, 1.846426, 2.281822, 3.154329",\ + "1.663605, 1.942666, 2.186081, 2.620692, 3.491619"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\ + "0.068571, 0.068571, 0.068550, 0.068476, 0.068328",\ + "0.090396, 0.090396, 0.090388, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\ + "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\ + "0.068571, 0.068571, 0.068549, 0.068476, 0.068328",\ + "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\ + "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\ + "0.068571, 0.068571, 0.068549, 0.068476, 0.068328",\ + "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\ + "0.061223, 0.061223, 0.061191, 0.061085, 0.060871",\ + "0.068571, 0.068571, 0.068549, 0.068476, 0.068328",\ + "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894",\ + "0.061223, 0.061223, 0.061190, 0.061084, 0.060871",\ + "0.068571, 0.068571, 0.068549, 0.068475, 0.068328",\ + "0.090396, 0.090396, 0.090387, 0.090358, 0.090299",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025895, 1.025895, 1.025895, 1.025895, 1.025894"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2575*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.577162, 0.819115, 1.086143, 1.569512, 2.536249",\ + "0.590714, 0.832667, 1.099696, 1.583067, 2.549807",\ + "0.614244, 0.856197, 1.123226, 1.606594, 2.573331",\ + "0.881617, 1.123572, 1.390607, 1.873991, 2.840761",\ + "1.475569, 1.717569, 1.984519, 2.467402, 3.433167",\ + "0.664563, 0.906592, 1.173751, 1.656225, 2.622182",\ + "0.678115, 0.920144, 1.187304, 1.669780, 2.635741",\ + "0.701645, 0.943674, 1.210834, 1.693307, 2.659265",\ + "0.969019, 1.211049, 1.478215, 1.960705, 2.926694",\ + "1.562970, 1.805047, 2.072125, 2.554115, 3.519101",\ + "0.745370, 0.995374, 1.261714, 1.743845, 2.709137",\ + "0.758922, 1.008926, 1.275267, 1.757400, 2.722696",\ + "0.782452, 1.032456, 1.298797, 1.780928, 2.746220",\ + "1.049826, 1.299831, 1.566178, 2.048325, 3.013649",\ + "1.643777, 1.893830, 2.160089, 2.641735, 3.606056",\ + "0.805541, 1.060718, 1.325856, 1.807758, 2.772646",\ + "0.819093, 1.074270, 1.339409, 1.821313, 2.786205",\ + "0.842623, 1.097800, 1.362939, 1.844840, 2.809729",\ + "1.109996, 1.365175, 1.630320, 2.112238, 3.077158",\ + "1.703948, 1.959175, 2.224230, 2.705648, 3.669565",\ + "1.143425, 1.421812, 1.677865, 2.157156, 3.118103",\ + "1.156977, 1.435364, 1.691418, 2.170711, 3.131661",\ + "1.180507, 1.458894, 1.714947, 2.194238, 3.155185",\ + "1.447880, 1.726269, 1.982328, 2.461636, 3.422615",\ + "2.041832, 2.320285, 2.576234, 3.055044, 4.015021"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121336, 0.121350, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201136, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121333, 0.121337, 0.121351, 0.121386, 0.121458",\ + "0.151694, 0.151694, 0.151695, 0.151695, 0.151695",\ + "0.201129, 0.201130, 0.201137, 0.201152, 0.201184",\ + "0.823409, 0.823409, 0.823409, 0.823409, 0.823409",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.544918, 0.786919, 1.051943, 1.528303, 2.481022",\ + "0.552861, 0.794861, 1.060131, 1.537319, 2.491697",\ + "0.566341, 0.808341, 1.074013, 1.552566, 2.509672",\ + "0.720294, 0.962295, 1.229085, 1.711427, 2.676111",\ + "1.060194, 1.302195, 1.568545, 2.049397, 3.011100",\ + "0.632320, 0.874396, 1.139529, 1.615016, 2.566956",\ + "0.640262, 0.882339, 1.147719, 1.624032, 2.577631",\ + "0.653742, 0.895819, 1.161606, 1.639279, 2.595606",\ + "0.807696, 1.049772, 1.316690, 1.798140, 2.762045",\ + "1.147596, 1.389672, 1.656145, 2.136110, 3.097034",\ + "0.713127, 0.963179, 1.227492, 1.702637, 2.653911",\ + "0.721069, 0.971121, 1.235682, 1.711653, 2.664586",\ + "0.734549, 0.984601, 1.249569, 1.726900, 2.682561",\ + "0.888502, 1.138555, 1.404653, 1.885761, 2.849000",\ + "1.228403, 1.478455, 1.744108, 2.223730, 3.183989",\ + "0.773297, 1.028524, 1.291633, 1.766549, 2.717420",\ + "0.781240, 1.036467, 1.299823, 1.775565, 2.728095",\ + "0.794720, 1.049947, 1.313710, 1.790812, 2.746070",\ + "0.948673, 1.203900, 1.468795, 1.949673, 2.912509",\ + "1.288574, 1.543800, 1.808250, 2.287643, 3.247498",\ + "1.111181, 1.389635, 1.643570, 2.115918, 3.062876",\ + "1.119124, 1.397577, 1.651768, 2.124938, 3.073550",\ + "1.132604, 1.411057, 1.665669, 2.140191, 3.091526",\ + "1.286557, 1.565011, 1.820792, 2.299067, 3.257965",\ + "1.626457, 1.904911, 2.160232, 2.637031, 3.592954"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.061220, 0.061199, 0.061091, 0.060821, 0.060280",\ + "0.068569, 0.068555, 0.068480, 0.068293, 0.067919",\ + "0.090395, 0.090390, 0.090360, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\ + "0.061220, 0.061199, 0.061090, 0.060821, 0.060280",\ + "0.068569, 0.068555, 0.068480, 0.068293, 0.067919",\ + "0.090395, 0.090390, 0.090360, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\ + "0.061220, 0.061198, 0.061090, 0.060821, 0.060280",\ + "0.068569, 0.068554, 0.068480, 0.068293, 0.067919",\ + "0.090395, 0.090390, 0.090360, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\ + "0.061220, 0.061198, 0.061090, 0.060821, 0.060280",\ + "0.068569, 0.068554, 0.068479, 0.068293, 0.067919",\ + "0.090395, 0.090389, 0.090360, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886",\ + "0.061220, 0.061191, 0.061087, 0.060819, 0.060280",\ + "0.068569, 0.068549, 0.068478, 0.068292, 0.067919",\ + "0.090395, 0.090387, 0.090359, 0.090285, 0.090136",\ + "0.380686, 0.380686, 0.380686, 0.380685, 0.380684",\ + "1.025895, 1.025895, 1.025894, 1.025891, 1.025886"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2704*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.666137, 0.908208, 1.174611, 1.656033, 2.618876",\ + "0.679731, 0.921802, 1.188205, 1.669626, 2.632469",\ + "0.703271, 0.945343, 1.211745, 1.693166, 2.656009",\ + "0.970809, 1.212879, 1.479281, 1.960701, 2.923540",\ + "1.563272, 1.805343, 2.071744, 2.553161, 3.515995",\ + "0.753539, 0.995685, 1.262213, 1.742746, 2.704810",\ + "0.767133, 1.009279, 1.275807, 1.756339, 2.718403",\ + "0.790673, 1.032819, 1.299347, 1.779880, 2.741943",\ + "1.058210, 1.300356, 1.566883, 2.047414, 3.009474",\ + "1.650674, 1.892820, 2.159346, 2.639874, 3.601928",\ + "0.834346, 1.084466, 1.350176, 1.830367, 2.791765",\ + "0.847940, 1.098060, 1.363770, 1.843960, 2.805358",\ + "0.871480, 1.121600, 1.387310, 1.867500, 2.828898",\ + "1.139017, 1.389137, 1.654846, 2.135035, 3.096429",\ + "1.731481, 1.981601, 2.247309, 2.727494, 3.688883",\ + "0.894640, 1.149809, 1.414318, 1.894279, 2.855274",\ + "0.908234, 1.163403, 1.427911, 1.907872, 2.868867",\ + "0.931774, 1.186943, 1.451452, 1.931413, 2.892407",\ + "1.199311, 1.454480, 1.718988, 2.198947, 3.159938",\ + "1.791775, 2.046944, 2.311450, 2.791407, 3.752392",\ + "1.232542, 1.510890, 1.766306, 2.243669, 3.200730",\ + "1.246135, 1.524484, 1.779900, 2.257262, 3.214323",\ + "1.269676, 1.548024, 1.803440, 2.280803, 3.237863",\ + "1.537213, 1.815561, 2.070976, 2.548337, 3.505394",\ + "2.129677, 2.408025, 2.663439, 3.140797, 4.097848"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152043, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135",\ + "0.121485, 0.121485, 0.121485, 0.121485, 0.121485",\ + "0.152032, 0.152032, 0.152044, 0.152082, 0.152158",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222135"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.607646, 0.849717, 1.116124, 1.597554, 2.560414",\ + "0.619007, 0.861079, 1.127484, 1.608912, 2.571767",\ + "0.637745, 0.879816, 1.146220, 1.627645, 2.590494",\ + "0.806293, 1.048363, 1.314763, 1.796177, 2.759006",\ + "1.141102, 1.383173, 1.649573, 2.130988, 3.093818",\ + "0.695047, 0.937194, 1.203726, 1.684267, 2.646348",\ + "0.706409, 0.948555, 1.215086, 1.695625, 2.657701",\ + "0.725146, 0.967293, 1.233822, 1.714358, 2.676428",\ + "0.893694, 1.135840, 1.402365, 1.882890, 2.844940",\ + "1.228504, 1.470650, 1.737175, 2.217701, 3.179752",\ + "0.775854, 1.025975, 1.291688, 1.771888, 2.733303",\ + "0.787216, 1.037337, 1.303049, 1.783245, 2.744656",\ + "0.805953, 1.056074, 1.321785, 1.801978, 2.763383",\ + "0.974501, 1.224621, 1.490328, 1.970511, 2.931895",\ + "1.309311, 1.559431, 1.825138, 2.305322, 3.266707",\ + "0.836149, 1.091318, 1.355830, 1.835800, 2.796812",\ + "0.847510, 1.102679, 1.367190, 1.847158, 2.808165",\ + "0.866248, 1.121417, 1.385927, 1.865891, 2.826892",\ + "1.034796, 1.289964, 1.554469, 2.034424, 2.995404",\ + "1.369605, 1.624774, 1.889280, 2.369234, 3.330216",\ + "1.174050, 1.452400, 1.707819, 2.185190, 3.142268",\ + "1.185411, 1.463761, 1.719179, 2.196548, 3.153621",\ + "1.204149, 1.482498, 1.737915, 2.215281, 3.172348",\ + "1.372697, 1.651045, 1.906458, 2.383814, 3.340860",\ + "1.707507, 1.985855, 2.241268, 2.718624, 3.675672"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\ + "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\ + "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\ + "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925",\ + "0.068435, 0.068435, 0.068435, 0.068435, 0.068435",\ + "0.074512, 0.074512, 0.074512, 0.074512, 0.074512",\ + "0.094928, 0.094928, 0.094928, 0.094928, 0.094928",\ + "0.380690, 0.380690, 0.380690, 0.380691, 0.380692",\ + "1.025917, 1.025917, 1.025918, 1.025920, 1.025925"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2327*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.688394, 0.943298, 1.199532, 1.637805, 2.514353",\ + "0.701988, 0.956891, 1.213125, 1.651399, 2.527946",\ + "0.725528, 0.980432, 1.236665, 1.674939, 2.551486",\ + "0.993065, 1.247969, 1.504202, 1.942475, 2.819022",\ + "1.585529, 1.840433, 2.096666, 2.534938, 3.411482",\ + "0.775799, 1.030785, 1.286999, 1.724519, 2.600287",\ + "0.789393, 1.044379, 1.300593, 1.738113, 2.613880",\ + "0.812933, 1.067919, 1.324133, 1.761653, 2.637420",\ + "1.080470, 1.335456, 1.591670, 2.029189, 2.904955",\ + "1.672934, 1.927920, 2.184134, 2.621652, 3.497416",\ + "0.864143, 1.119604, 1.374960, 1.812140, 2.687242",\ + "0.877736, 1.133197, 1.388554, 1.825734, 2.700835",\ + "0.901277, 1.156737, 1.412094, 1.849274, 2.724375",\ + "1.168814, 1.424274, 1.679631, 2.116810, 2.991910",\ + "1.761278, 2.016739, 2.272095, 2.709273, 3.584371",\ + "0.927637, 1.185001, 1.439095, 1.876053, 2.750751",\ + "0.941231, 1.198595, 1.452689, 1.889647, 2.764344",\ + "0.964771, 1.222135, 1.476229, 1.913187, 2.787884",\ + "1.232308, 1.489672, 1.743766, 2.180723, 3.055419",\ + "1.824772, 2.082136, 2.336229, 2.773186, 3.647880",\ + "1.263060, 1.546678, 1.790648, 2.225268, 3.096207",\ + "1.276654, 1.560272, 1.804242, 2.238862, 3.109800",\ + "1.300194, 1.583812, 1.827782, 2.262402, 3.133340",\ + "1.567731, 1.851349, 2.095319, 2.529938, 3.400876",\ + "2.160195, 2.443813, 2.687783, 3.122401, 3.993336"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121485, 0.121485, 0.121485, 0.121484, 0.121482",\ + "0.152032, 0.152032, 0.152031, 0.152028, 0.152021",\ + "0.200984, 0.200984, 0.200984, 0.200984, 0.200984",\ + "0.823612, 0.823612, 0.823612, 0.823612, 0.823612",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.629902, 0.884806, 1.141041, 1.579317, 2.455871",\ + "0.641263, 0.896167, 1.152402, 1.590678, 2.467230",\ + "0.660001, 0.914905, 1.171139, 1.609414, 2.485964",\ + "0.828549, 1.083453, 1.339686, 1.777957, 2.654500",\ + "1.163359, 1.418263, 1.674496, 2.112767, 2.989310",\ + "0.717307, 0.972293, 1.228508, 1.666031, 2.541805",\ + "0.728669, 0.983655, 1.239870, 1.677392, 2.553164",\ + "0.747406, 1.002393, 1.258607, 1.696128, 2.571898",\ + "0.915954, 1.170941, 1.427154, 1.864671, 2.740433",\ + "1.250764, 1.505750, 1.761964, 2.199481, 3.075244",\ + "0.805651, 1.061112, 1.316469, 1.753652, 2.628760",\ + "0.817012, 1.072473, 1.327831, 1.765013, 2.640119",\ + "0.835750, 1.091211, 1.346568, 1.783749, 2.658853",\ + "1.004298, 1.259759, 1.515115, 1.952292, 2.827389",\ + "1.339108, 1.594568, 1.849925, 2.287102, 3.162199",\ + "0.869145, 1.126509, 1.380604, 1.817565, 2.692269",\ + "0.880507, 1.137871, 1.391965, 1.828925, 2.703628",\ + "0.899244, 1.156608, 1.410703, 1.847662, 2.722362",\ + "1.067792, 1.325156, 1.579249, 2.016205, 2.890898",\ + "1.402602, 1.659966, 1.914059, 2.351015, 3.225708",\ + "1.204568, 1.488186, 1.732157, 2.166780, 3.037725",\ + "1.215930, 1.499547, 1.743518, 2.178141, 3.049084",\ + "1.234668, 1.518285, 1.762256, 2.196877, 3.067818",\ + "1.403215, 1.686833, 1.930802, 2.365420, 3.236354",\ + "1.738025, 2.021643, 2.265612, 2.700230, 3.571164"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\ + "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\ + "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\ + "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916",\ + "0.068436, 0.068436, 0.068433, 0.068425, 0.068407",\ + "0.074512, 0.074512, 0.074510, 0.074502, 0.074487",\ + "0.094928, 0.094928, 0.094926, 0.094919, 0.094904",\ + "0.380690, 0.380690, 0.380690, 0.380690, 0.380690",\ + "1.025917, 1.025917, 1.025917, 1.025917, 1.025916"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2344*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.195231, 0.463005, 0.734474, 1.195010, 2.116083",\ + "0.209369, 0.477311, 0.748785, 1.209873, 2.132048",\ + "0.233103, 0.501280, 0.772498, 1.233725, 2.156177",\ + "0.505445, 0.772942, 1.041862, 1.499718, 2.415430",\ + "1.101330, 1.368410, 1.636340, 2.092443, 3.004649",\ + "0.282639, 0.550544, 0.822013, 1.281725, 2.202017",\ + "0.296777, 0.564849, 0.836326, 1.296587, 2.217982",\ + "0.320749, 0.588817, 0.860040, 1.320439, 2.242111",\ + "0.593808, 0.860470, 1.129393, 1.586432, 2.501364",\ + "1.189691, 1.455935, 1.723865, 2.179157, 3.090583",\ + "0.371453, 0.639490, 0.909976, 1.369346, 2.288972",\ + "0.385884, 0.653793, 0.924289, 1.384209, 2.304937",\ + "0.410095, 0.677755, 0.948003, 1.408060, 2.329066",\ + "0.683117, 0.949390, 1.217355, 1.674054, 2.588319",\ + "1.278993, 1.544848, 1.811828, 2.266779, 3.177538",\ + "0.435127, 0.705073, 0.974115, 1.433259, 2.352481",\ + "0.449557, 0.719372, 0.988428, 1.448122, 2.368446",\ + "0.473764, 0.743329, 1.012141, 1.471974, 2.392575",\ + "0.746751, 1.014935, 1.281493, 1.737967, 2.651828",\ + "1.342621, 1.610383, 1.875965, 2.330692, 3.241047",\ + "0.771711, 1.068883, 1.325895, 1.782569, 2.697937",\ + "0.786132, 1.083144, 1.340213, 1.797434, 2.713902",\ + "0.810321, 1.107028, 1.363928, 1.821286, 2.738031",\ + "1.083085, 1.378307, 1.633246, 2.087266, 2.997284",\ + "1.678917, 1.973635, 2.227701, 2.679984, 3.586503"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.185659, 0.236480, 0.332306, 0.503768, 0.846690",\ + "0.203762, 0.251201, 0.346416, 0.519962, 0.867054",\ + "0.237818, 0.275998, 0.366817, 0.542132, 0.892761",\ + "0.823305, 0.824108, 0.854501, 0.958291, 1.165871",\ + "2.222180, 2.222247, 2.228687, 2.250859, 2.295203",\ + "0.185659, 0.236778, 0.332846, 0.503768, 0.846690",\ + "0.203762, 0.251491, 0.346963, 0.519962, 0.867054",\ + "0.238090, 0.276257, 0.367369, 0.542132, 0.892761",\ + "0.823322, 0.824110, 0.854828, 0.958291, 1.165871",\ + "2.222181, 2.222247, 2.228756, 2.250859, 2.295203",\ + "0.187582, 0.237448, 0.332856, 0.503768, 0.846690",\ + "0.205428, 0.252143, 0.346973, 0.519962, 0.867054",\ + "0.238891, 0.276838, 0.367379, 0.542132, 0.892761",\ + "0.823369, 0.824113, 0.854835, 0.958291, 1.165871",\ + "2.222186, 2.222247, 2.228758, 2.250859, 2.295203",\ + "0.188921, 0.238422, 0.332885, 0.503768, 0.846690",\ + "0.206588, 0.253091, 0.347002, 0.519962, 0.867054",\ + "0.239638, 0.277682, 0.367409, 0.542132, 0.892761",\ + "0.823414, 0.824119, 0.854852, 0.958291, 1.165871",\ + "2.222191, 2.222247, 2.228761, 2.250859, 2.295203",\ + "0.197449, 0.249827, 0.334624, 0.504477, 0.846690",\ + "0.213977, 0.264195, 0.348763, 0.520680, 0.867054",\ + "0.244398, 0.287568, 0.369187, 0.542857, 0.892761",\ + "0.823697, 0.824180, 0.855905, 0.958721, 1.165871",\ + "2.222221, 2.222247, 2.228986, 2.250950, 2.295203"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.199835, 0.394068, 0.663502, 1.119151, 2.030450",\ + "0.208748, 0.404375, 0.677456, 1.139816, 2.064535",\ + "0.223610, 0.421071, 0.699454, 1.171923, 2.116862",\ + "0.380613, 0.582386, 0.880612, 1.405667, 2.455778",\ + "0.716679, 0.922290, 1.228480, 1.784735, 2.897244",\ + "0.287243, 0.481603, 0.751025, 1.205865, 2.116384",\ + "0.296156, 0.491921, 0.765001, 1.226530, 2.150469",\ + "0.311018, 0.508632, 0.787030, 1.258637, 2.202796",\ + "0.468021, 0.669977, 0.968355, 1.492382, 2.541712",\ + "0.804087, 1.009874, 1.316321, 1.871449, 2.983178",\ + "0.368115, 0.570540, 0.838988, 1.293487, 2.203339",\ + "0.377029, 0.580882, 0.852964, 1.314152, 2.237424",\ + "0.391890, 0.597628, 0.874994, 1.346259, 2.289751",\ + "0.548893, 0.759039, 1.056321, 1.580003, 2.628667",\ + "0.884959, 1.098920, 1.404289, 1.959070, 3.070133",\ + "0.425818, 0.636109, 0.903125, 1.357400, 2.266848",\ + "0.434733, 0.646488, 0.917102, 1.378065, 2.300933",\ + "0.449593, 0.663284, 0.939134, 1.410172, 2.353260",\ + "0.606596, 0.824792, 1.120470, 1.643916, 2.692176",\ + "0.942662, 1.164649, 1.468444, 2.022984, 3.133642",\ + "0.728861, 0.999767, 1.254856, 1.706689, 2.612304",\ + "0.737784, 1.010567, 1.268901, 1.727382, 2.646389",\ + "0.752638, 1.027949, 1.291036, 1.759531, 2.698716",\ + "0.909639, 1.190589, 1.472905, 1.993493, 3.037632",\ + "1.245701, 1.530174, 1.821195, 2.372689, 3.479098"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.051713, 0.082206, 0.146667, 0.272496, 0.524154",\ + "0.059242, 0.084148, 0.146833, 0.273232, 0.526032",\ + "0.082676, 0.098099, 0.151707, 0.276480, 0.526025",\ + "0.382075, 0.382564, 0.407345, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042321, 1.092011, 1.191392",\ + "0.051713, 0.082387, 0.147063, 0.272496, 0.524154",\ + "0.059242, 0.084316, 0.147231, 0.273232, 0.526032",\ + "0.082676, 0.098212, 0.152100, 0.276480, 0.526025",\ + "0.382075, 0.382568, 0.407606, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042477, 1.092011, 1.191392",\ + "0.051782, 0.082793, 0.147071, 0.272496, 0.524154",\ + "0.059284, 0.084694, 0.147238, 0.273232, 0.526032",\ + "0.082697, 0.098465, 0.152108, 0.276480, 0.526025",\ + "0.382075, 0.382579, 0.407611, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042480, 1.092011, 1.191392",\ + "0.051916, 0.083384, 0.147092, 0.272496, 0.524154",\ + "0.059368, 0.085243, 0.147259, 0.273232, 0.526032",\ + "0.082738, 0.098832, 0.152128, 0.276480, 0.526025",\ + "0.382075, 0.382594, 0.407625, 0.490228, 0.655996",\ + "1.027888, 1.027888, 1.042489, 1.092011, 1.191392",\ + "0.053133, 0.090301, 0.148368, 0.273016, 0.524154",\ + "0.060124, 0.091679, 0.148542, 0.273755, 0.526032",\ + "0.083110, 0.103136, 0.153394, 0.276996, 0.526025",\ + "0.382075, 0.382769, 0.408465, 0.490571, 0.655996",\ + "1.027888, 1.027888, 1.042993, 1.092217, 1.191392"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2530*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.737863, 1.003362, 1.291646, 1.782380, 2.763848",\ + "0.751415, 1.016914, 1.305198, 1.795933, 2.777400",\ + "0.774946, 1.040444, 1.328728, 1.819463, 2.800930",\ + "1.042319, 1.307818, 1.596103, 2.086838, 3.068308",\ + "1.636291, 1.901789, 2.190096, 2.680906, 3.662528",\ + "0.825276, 1.090943, 1.379283, 1.869095, 2.849782",\ + "0.838828, 1.104495, 1.392835, 1.882647, 2.863334",\ + "0.862358, 1.128025, 1.416365, 1.906177, 2.886864",\ + "1.129732, 1.395399, 1.683739, 2.173553, 3.154242",\ + "1.723704, 1.989370, 2.277732, 2.767621, 3.748461",\ + "0.906195, 1.180006, 1.467248, 1.956717, 2.936737",\ + "0.919747, 1.193558, 1.480801, 1.970270, 2.950289",\ + "0.943277, 1.217088, 1.504331, 1.993800, 2.973819",\ + "1.210651, 1.484462, 1.771705, 2.261175, 3.241197",\ + "1.804622, 2.078433, 2.365698, 2.855243, 3.835416",\ + "0.966681, 1.245760, 1.531392, 2.020631, 3.000246",\ + "0.980233, 1.259312, 1.544944, 2.034183, 3.013798",\ + "1.003763, 1.282842, 1.568474, 2.057713, 3.037328",\ + "1.271137, 1.550216, 1.835848, 2.325089, 3.304706",\ + "1.865109, 2.144188, 2.429842, 2.919157, 3.898925",\ + "1.301775, 1.611517, 1.883481, 2.370070, 3.345702",\ + "1.315328, 1.625069, 1.897033, 2.383622, 3.359254",\ + "1.338858, 1.648599, 1.920563, 2.407152, 3.382784",\ + "1.606231, 1.915973, 2.187937, 2.674527, 3.650162",\ + "2.200203, 2.509944, 2.781931, 3.268596, 4.244381"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121338, 0.121343",\ + "0.151694, 0.151694, 0.151693, 0.151692, 0.151690",\ + "0.201129, 0.201129, 0.201129, 0.201131, 0.201133",\ + "0.823409, 0.823409, 0.823408, 0.823407, 0.823404",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.705640, 0.971139, 1.259445, 1.750256, 2.731876",\ + "0.713583, 0.979081, 1.267388, 1.758198, 2.739818",\ + "0.727063, 0.992561, 1.280868, 1.771678, 2.753298",\ + "0.881016, 1.146515, 1.434821, 1.925632, 2.907252",\ + "1.220917, 1.486415, 1.774721, 2.265532, 3.247153",\ + "0.793053, 1.058720, 1.347082, 1.836970, 2.817810",\ + "0.800995, 1.066662, 1.355024, 1.844913, 2.825752",\ + "0.814475, 1.080142, 1.368504, 1.858393, 2.839232",\ + "0.968429, 1.234096, 1.522458, 2.012346, 2.993186",\ + "1.308329, 1.573996, 1.862358, 2.352247, 3.333086",\ + "0.873972, 1.147783, 1.435048, 1.924593, 2.904765",\ + "0.881914, 1.155725, 1.442990, 1.932535, 2.912707",\ + "0.895394, 1.169205, 1.456470, 1.946015, 2.926187",\ + "1.049348, 1.323159, 1.610423, 2.099968, 3.080141",\ + "1.389248, 1.663059, 1.950324, 2.439869, 3.420042",\ + "0.934458, 1.213537, 1.499191, 1.988506, 2.968274",\ + "0.942401, 1.221480, 1.507133, 1.996449, 2.976216",\ + "0.955880, 1.234959, 1.520613, 2.009929, 2.989696",\ + "1.109834, 1.388913, 1.674567, 2.163882, 3.143650",\ + "1.449734, 1.728813, 2.014467, 2.503783, 3.483551",\ + "1.269552, 1.579294, 1.851281, 2.337945, 3.313730",\ + "1.277495, 1.587236, 1.859223, 2.345888, 3.321672",\ + "1.290975, 1.600716, 1.872703, 2.359368, 3.335152",\ + "1.444928, 1.754670, 2.026657, 2.513321, 3.489106",\ + "1.784829, 2.094570, 2.366557, 2.853222, 3.829007"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.061214, 0.061214, 0.061208, 0.061187, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061214, 0.061214, 0.061207, 0.061187, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061214, 0.061214, 0.061207, 0.061187, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061214, 0.061214, 0.061207, 0.061187, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061214, 0.061214, 0.061207, 0.061186, 0.061144",\ + "0.068565, 0.068565, 0.068561, 0.068546, 0.068517",\ + "0.090394, 0.090394, 0.090392, 0.090386, 0.090375",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2668*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.109772, 0.369798, 0.626503, 1.061758, 1.932266",\ + "0.120352, 0.381519, 0.640958, 1.080478, 1.959519",\ + "0.143356, 0.404296, 0.665874, 1.109884, 1.997905",\ + "0.467994, 0.696012, 0.968260, 1.421863, 2.329069",\ + "1.081974, 1.301531, 1.593583, 2.086339, 3.071851",\ + "0.198042, 0.457293, 0.713962, 1.148472, 2.018200",\ + "0.208624, 0.469024, 0.728430, 1.167192, 2.045453",\ + "0.231607, 0.491807, 0.753360, 1.196598, 2.083839",\ + "0.555400, 0.783574, 1.055776, 1.508577, 2.415003",\ + "1.169380, 1.389148, 1.681223, 2.173053, 3.157785",\ + "0.287235, 0.546131, 0.801923, 1.236093, 2.105155",\ + "0.297824, 0.557883, 0.816391, 1.254813, 2.132408",\ + "0.320747, 0.580678, 0.841322, 1.284219, 2.170794",\ + "0.636219, 0.872561, 1.143739, 1.596198, 2.501958",\ + "1.250216, 1.478256, 1.769187, 2.260674, 3.244740",\ + "0.350832, 0.611557, 0.866057, 1.300006, 2.168664",\ + "0.361428, 0.623341, 0.880526, 1.318726, 2.195917",\ + "0.384293, 0.646153, 0.905457, 1.348132, 2.234303",\ + "0.693839, 0.938203, 1.207876, 1.660111, 2.565467",\ + "1.307871, 1.544076, 1.833331, 2.324587, 3.308249",\ + "0.686914, 0.973559, 1.217580, 1.649209, 2.514120",\ + "0.697552, 0.985713, 1.232092, 1.667947, 2.541373",\ + "0.720052, 1.008731, 1.257069, 1.697372, 2.579759",\ + "1.005905, 1.302737, 1.559584, 2.009390, 2.910923",\ + "1.610583, 1.910693, 2.185437, 2.674028, 3.653705"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.074635, 0.092924, 0.146295, 0.240037, 0.427522",\ + "0.102546, 0.120314, 0.177030, 0.284760, 0.500219",\ + "0.161902, 0.174975, 0.229446, 0.352350, 0.598157",\ + "0.823637, 0.823637, 0.866693, 1.014155, 1.309078",\ + "2.221941, 2.221941, 2.244858, 2.323347, 2.480325",\ + "0.074635, 0.093094, 0.146590, 0.240037, 0.427522",\ + "0.102546, 0.120480, 0.177368, 0.284760, 0.500219",\ + "0.161902, 0.175097, 0.229832, 0.352350, 0.598157",\ + "0.823637, 0.823637, 0.867157, 1.014155, 1.309078",\ + "2.221941, 2.221941, 2.245105, 2.323347, 2.480325",\ + "0.074635, 0.093474, 0.146595, 0.240037, 0.427522",\ + "0.102546, 0.120849, 0.177375, 0.284760, 0.500219",\ + "0.161902, 0.175368, 0.229839, 0.352350, 0.598157",\ + "0.823637, 0.823637, 0.867165, 1.014155, 1.309078",\ + "2.221941, 2.221941, 2.245110, 2.323347, 2.480325",\ + "0.074635, 0.094026, 0.146611, 0.240037, 0.427522",\ + "0.102546, 0.121384, 0.177393, 0.284760, 0.500219",\ + "0.161902, 0.175763, 0.229860, 0.352350, 0.598157",\ + "0.823637, 0.823637, 0.867190, 1.014155, 1.309078",\ + "2.221941, 2.221941, 2.245123, 2.323347, 2.480325",\ + "0.074635, 0.100491, 0.147562, 0.240424, 0.427522",\ + "0.102546, 0.127666, 0.178485, 0.285204, 0.500219",\ + "0.161902, 0.180384, 0.231107, 0.352857, 0.598157",\ + "0.823637, 0.823637, 0.868686, 1.014764, 1.309078",\ + "2.221941, 2.221941, 2.245919, 2.323671, 2.480325"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.141728, 0.322683, 0.508414, 0.851578, 1.569056",\ + "0.147760, 0.329649, 0.526344, 0.903425, 1.657587",\ + "0.158195, 0.340967, 0.571363, 0.971528, 1.771856",\ + "0.298823, 0.523674, 0.808829, 1.303379, 2.292479",\ + "0.636132, 0.863255, 1.152943, 1.685611, 2.750947",\ + "0.229134, 0.410071, 0.595881, 0.938291, 1.654990",\ + "0.235166, 0.417039, 0.613620, 0.990139, 1.743521",\ + "0.245601, 0.428357, 0.658712, 1.058241, 1.857790",\ + "0.386229, 0.611242, 0.896475, 1.390093, 2.378412",\ + "0.723538, 0.950780, 1.240708, 1.772325, 2.836881",\ + "0.309995, 0.490402, 0.675907, 1.025913, 1.741945",\ + "0.316032, 0.497370, 0.701577, 1.077760, 1.830476",\ + "0.326472, 0.511248, 0.746671, 1.145863, 1.944745",\ + "0.467101, 0.700242, 0.984439, 1.477714, 2.465368",\ + "0.804387, 1.039684, 1.328675, 1.859946, 2.923836",\ + "0.367698, 0.547951, 0.733450, 1.089826, 1.805454",\ + "0.373747, 0.554919, 0.765701, 1.141673, 1.893985",\ + "0.384198, 0.576458, 0.810799, 1.209776, 2.008254",\ + "0.524826, 0.765905, 1.048583, 1.541627, 2.528877",\ + "0.862067, 1.105206, 1.392825, 1.923859, 2.987345",\ + "0.670854, 0.880709, 1.082881, 1.438713, 2.150910",\ + "0.677008, 0.904085, 1.116634, 1.490636, 2.239441",\ + "0.687558, 0.935916, 1.161966, 1.558834, 2.353710",\ + "0.834408, 1.130676, 1.400707, 1.891076, 2.874332",\ + "1.178988, 1.468337, 1.745336, 2.273465, 3.332801"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.063168, 0.063168, 0.086452, 0.196369, 0.354186",\ + "0.068741, 0.068741, 0.139232, 0.228666, 0.407534",\ + "0.084603, 0.084603, 0.171201, 0.272810, 0.476028",\ + "0.381099, 0.384063, 0.433028, 0.586290, 0.892815",\ + "1.028844, 1.028844, 1.069845, 1.210271, 1.491123",\ + "0.063168, 0.063168, 0.086512, 0.196369, 0.354186",\ + "0.068741, 0.068741, 0.139513, 0.228666, 0.407534",\ + "0.084603, 0.084603, 0.171521, 0.272810, 0.476028",\ + "0.381099, 0.384091, 0.433510, 0.586290, 0.892815",\ + "1.028844, 1.028844, 1.070287, 1.210271, 1.491123",\ + "0.063168, 0.063168, 0.086512, 0.196369, 0.354186",\ + "0.068741, 0.068741, 0.139518, 0.228666, 0.407534",\ + "0.084603, 0.108819, 0.171527, 0.272810, 0.476028",\ + "0.381099, 0.384153, 0.433519, 0.586290, 0.892815",\ + "1.028844, 1.028844, 1.070295, 1.210271, 1.491123",\ + "0.063168, 0.063168, 0.086512, 0.196369, 0.354186",\ + "0.068741, 0.068741, 0.139534, 0.228666, 0.407534",\ + "0.084603, 0.109528, 0.171544, 0.272810, 0.476028",\ + "0.381099, 0.384242, 0.433545, 0.586290, 0.892815",\ + "1.028844, 1.028844, 1.070319, 1.210271, 1.491123",\ + "0.063168, 0.081414, 0.118527, 0.196695, 0.354186",\ + "0.068741, 0.094649, 0.140441, 0.229035, 0.407534",\ + "0.084603, 0.117839, 0.172574, 0.273230, 0.476028",\ + "0.381099, 0.385290, 0.435099, 0.586923, 0.892815",\ + "1.028844, 1.028844, 1.071743, 1.210851, 1.491123"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2709*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.715344, 0.975445, 1.253880, 1.716396, 2.641427",\ + "0.728896, 0.988997, 1.267432, 1.729948, 2.654979",\ + "0.752427, 1.012527, 1.290962, 1.753478, 2.678509",\ + "1.019800, 1.279901, 1.558336, 2.020853, 2.945885",\ + "1.613771, 1.873872, 2.152319, 2.614874, 3.539985",\ + "0.802750, 1.063030, 1.341425, 1.803109, 2.727360",\ + "0.816303, 1.076582, 1.354977, 1.816662, 2.740913",\ + "0.839833, 1.100112, 1.378507, 1.840192, 2.764443",\ + "1.107206, 1.367486, 1.645881, 2.107566, 3.031819",\ + "1.701178, 1.961458, 2.239864, 2.701588, 3.625918",\ + "0.883600, 1.152069, 1.429387, 1.890731, 2.814316",\ + "0.897153, 1.165621, 1.442940, 1.904283, 2.827868",\ + "0.920683, 1.189151, 1.466470, 1.927813, 2.851398",\ + "1.188056, 1.456525, 1.733844, 2.195188, 3.118774",\ + "1.782027, 2.050497, 2.327826, 2.789209, 3.712873",\ + "0.945225, 1.217787, 1.493526, 1.954644, 2.877825",\ + "0.958777, 1.231339, 1.507078, 1.968196, 2.891377",\ + "0.982307, 1.254869, 1.530608, 1.991726, 2.914907",\ + "1.249681, 1.522243, 1.797982, 2.259101, 3.182283",\ + "1.843652, 2.116215, 2.391965, 2.853122, 3.776382",\ + "1.282097, 1.583212, 1.845325, 2.303960, 3.223280",\ + "1.295649, 1.596764, 1.858877, 2.317512, 3.236833",\ + "1.319179, 1.620294, 1.882407, 2.341042, 3.260363",\ + "1.586553, 1.887668, 2.149781, 2.608417, 3.527739",\ + "2.180524, 2.481639, 2.743765, 3.202439, 4.121839"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134",\ + "0.121334, 0.121334, 0.121335, 0.121336, 0.121339",\ + "0.151694, 0.151694, 0.151694, 0.151693, 0.151692",\ + "0.201129, 0.201129, 0.201129, 0.201130, 0.201131",\ + "0.823409, 0.823409, 0.823409, 0.823408, 0.823406",\ + "2.222134, 2.222134, 2.222134, 2.222134, 2.222134"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.683121, 0.943222, 1.221668, 1.684223, 2.609334",\ + "0.691063, 0.951164, 1.229611, 1.692166, 2.617276",\ + "0.704543, 0.964644, 1.243091, 1.705646, 2.630756",\ + "0.858497, 1.118598, 1.397044, 1.859599, 2.784709",\ + "1.198397, 1.458498, 1.736945, 2.199500, 3.124610",\ + "0.770527, 1.030807, 1.309213, 1.770937, 2.695267",\ + "0.778469, 1.038749, 1.317156, 1.778880, 2.703210",\ + "0.791949, 1.052229, 1.330636, 1.792360, 2.716690",\ + "0.945903, 1.206183, 1.484589, 1.946313, 2.870643",\ + "1.285803, 1.546083, 1.824489, 2.286213, 3.210544",\ + "0.851377, 1.119846, 1.397176, 1.858559, 2.782223",\ + "0.859320, 1.127788, 1.405118, 1.866501, 2.790165",\ + "0.872799, 1.141268, 1.418598, 1.879981, 2.803645",\ + "1.026753, 1.295222, 1.572552, 2.033935, 2.957598",\ + "1.366653, 1.635122, 1.912452, 2.373835, 3.297499",\ + "0.913002, 1.185564, 1.461314, 1.922472, 2.845731",\ + "0.920944, 1.193506, 1.469257, 1.930414, 2.853674",\ + "0.934424, 1.206986, 1.482737, 1.943894, 2.867154",\ + "1.088378, 1.360940, 1.636690, 2.097847, 3.021107",\ + "1.428278, 1.700840, 1.976590, 2.437748, 3.361008",\ + "1.249874, 1.550989, 1.813114, 2.271788, 3.191187",\ + "1.257816, 1.558931, 1.821056, 2.279730, 3.199130",\ + "1.271296, 1.572411, 1.834536, 2.293210, 3.212610",\ + "1.425250, 1.726365, 1.988490, 2.447164, 3.366563",\ + "1.765150, 2.066265, 2.328390, 2.787064, 3.706464"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894",\ + "0.061213, 0.061213, 0.061210, 0.061198, 0.061174",\ + "0.068565, 0.068565, 0.068562, 0.068554, 0.068538",\ + "0.090394, 0.090394, 0.090393, 0.090389, 0.090383",\ + "0.380686, 0.380686, 0.380686, 0.380686, 0.380686",\ + "1.025894, 1.025894, 1.025894, 1.025894, 1.025894"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_2681*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.385362, 0.574573, 0.765319, 1.061205, 1.627908",\ + "0.404628, 0.593839, 0.784585, 1.080471, 1.647174",\ + "0.436306, 0.625517, 0.816263, 1.112149, 1.678852",\ + "0.725958, 0.915169, 1.105914, 1.401800, 1.968502",\ + "1.319903, 1.509114, 1.699858, 1.995744, 2.562446",\ + "0.473615, 0.661891, 0.852600, 1.148510, 1.715261",\ + "0.492881, 0.681157, 0.871866, 1.167776, 1.734527",\ + "0.524560, 0.712836, 0.903544, 1.199454, 1.766205",\ + "0.814212, 1.002488, 1.193195, 1.489105, 2.055855",\ + "1.408156, 1.596432, 1.787139, 2.083049, 2.649799",\ + "0.562261, 0.742226, 0.932626, 1.228538, 1.795292",\ + "0.581527, 0.761492, 0.951893, 1.247805, 1.814559",\ + "0.613206, 0.793171, 0.983571, 1.279483, 1.846237",\ + "0.902858, 1.082823, 1.273222, 1.569133, 2.135887",\ + "1.496802, 1.676767, 1.867166, 2.163077, 2.729831",\ + "0.620370, 0.800057, 0.990350, 1.285975, 1.852322",\ + "0.639636, 0.819323, 1.009616, 1.305241, 1.871588",\ + "0.671315, 0.851002, 1.041294, 1.336920, 1.903266",\ + "0.960967, 1.140654, 1.330945, 1.626570, 2.192916",\ + "1.554911, 1.734598, 1.924889, 2.220514, 2.786860",\ + "0.922623, 1.105385, 1.294011, 1.589153, 2.154560",\ + "0.941889, 1.124651, 1.313277, 1.608420, 2.173826",\ + "0.973567, 1.156330, 1.344955, 1.640098, 2.205504",\ + "1.263219, 1.445982, 1.634606, 1.929748, 2.495154",\ + "1.857164, 2.039926, 2.228550, 2.523692, 3.089098"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\ + "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\ + "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\ + "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568",\ + "0.107385, 0.107385, 0.107386, 0.107387, 0.107387",\ + "0.140617, 0.140617, 0.140617, 0.140618, 0.140619",\ + "0.189797, 0.189797, 0.189797, 0.189797, 0.189798",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195570, 2.195569, 2.195569, 2.195568"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.395642, 0.585187, 0.775931, 1.071620, 1.637841",\ + "0.403773, 0.592984, 0.783728, 1.079613, 1.646315",\ + "0.417192, 0.606403, 0.797147, 1.093032, 1.659734",\ + "0.569868, 0.759079, 0.949823, 1.245708, 1.812411",\ + "0.903831, 1.093042, 1.283787, 1.579672, 2.146375",\ + "0.483904, 0.672505, 0.863212, 1.158925, 1.725194",\ + "0.492026, 0.680302, 0.871009, 1.166918, 1.733668",\ + "0.505446, 0.693722, 0.884428, 1.180337, 1.747088",\ + "0.658121, 0.846397, 1.037104, 1.333013, 1.899764",\ + "0.992085, 1.180361, 1.371068, 1.666977, 2.233728",\ + "0.572576, 0.752841, 0.943239, 1.238954, 1.805226",\ + "0.580672, 0.760637, 0.951036, 1.246946, 1.813700",\ + "0.594092, 0.774057, 0.964455, 1.260366, 1.827119",\ + "0.746767, 0.926732, 1.117131, 1.413042, 1.979796",\ + "1.080731, 1.260696, 1.451095, 1.747006, 2.313760",\ + "0.630984, 0.810671, 1.000962, 1.296390, 1.862254",\ + "0.638781, 0.818468, 1.008759, 1.304383, 1.870729",\ + "0.652200, 0.831887, 1.022178, 1.317803, 1.884149",\ + "0.804876, 0.984563, 1.174854, 1.470479, 2.036825",\ + "1.138840, 1.318527, 1.508818, 1.804443, 2.370789",\ + "0.933237, 1.115999, 1.304623, 1.599568, 2.164490",\ + "0.941034, 1.123796, 1.312420, 1.607561, 2.172967",\ + "0.954453, 1.137215, 1.325839, 1.620981, 2.186387",\ + "1.107129, 1.289891, 1.478515, 1.773657, 2.339063",\ + "1.441092, 1.623855, 1.812479, 2.107621, 2.673027"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055580, 0.055580, 0.055580, 0.055580, 0.055580",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2495*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.535388, 0.757178, 0.935245, 1.224116, 1.784806",\ + "0.554760, 0.776550, 0.954617, 1.243488, 1.804178",\ + "0.586214, 0.808003, 0.986070, 1.274942, 1.835631",\ + "0.875148, 1.096938, 1.275005, 1.563877, 2.124566",\ + "1.469041, 1.690830, 1.868897, 2.157769, 2.718458",\ + "0.623792, 0.844496, 1.022526, 1.311421, 1.872159",\ + "0.643164, 0.863868, 1.041898, 1.330793, 1.891531",\ + "0.674618, 0.895322, 1.073351, 1.362247, 1.922985",\ + "0.963552, 1.184257, 1.362286, 1.651182, 2.211919",\ + "1.557444, 1.778149, 1.956178, 2.245074, 2.805811",\ + "0.712864, 0.924832, 1.102553, 1.391450, 1.952191",\ + "0.732236, 0.944203, 1.121924, 1.410822, 1.971563",\ + "0.763690, 0.975657, 1.153378, 1.442276, 2.003016",\ + "1.052624, 1.264592, 1.442313, 1.731210, 2.291951",\ + "1.646516, 1.858484, 2.036205, 2.325102, 2.885843",\ + "0.776122, 0.982654, 1.160246, 1.448879, 2.009206",\ + "0.795494, 1.002026, 1.179617, 1.468251, 2.028577",\ + "0.826948, 1.033479, 1.211071, 1.499705, 2.060031",\ + "1.115882, 1.322414, 1.500006, 1.788640, 2.348966",\ + "1.709774, 1.916306, 2.093898, 2.382532, 2.942858",\ + "1.107140, 1.287923, 1.463902, 1.752051, 2.311426",\ + "1.126512, 1.307295, 1.483274, 1.771423, 2.330798",\ + "1.157965, 1.338748, 1.514728, 1.802877, 2.362252",\ + "1.446900, 1.627683, 1.803662, 2.091812, 2.651186",\ + "2.040792, 2.221575, 2.397554, 2.685704, 3.245078"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.544632, 0.766422, 0.944489, 1.233360, 1.794050",\ + "0.552443, 0.774232, 0.952299, 1.241171, 1.801860",\ + "0.565862, 0.787651, 0.965718, 1.254590, 1.815279",\ + "0.718832, 0.940622, 1.118689, 1.407560, 1.968250",\ + "1.052901, 1.274690, 1.452757, 1.741629, 2.302318",\ + "0.633036, 0.853740, 1.031770, 1.320665, 1.881403",\ + "0.640847, 0.861551, 1.039580, 1.328476, 1.889213",\ + "0.654266, 0.874970, 1.052999, 1.341895, 1.902633",\ + "0.807236, 1.027940, 1.205970, 1.494865, 2.055603",\ + "1.141305, 1.362009, 1.540038, 1.828934, 2.389672",\ + "0.722108, 0.934075, 1.111796, 1.400694, 1.961435",\ + "0.729918, 0.941886, 1.119607, 1.408504, 1.969245",\ + "0.743338, 0.955305, 1.133026, 1.421923, 1.982664",\ + "0.896308, 1.108276, 1.285997, 1.574894, 2.135635",\ + "1.230376, 1.442344, 1.620065, 1.908962, 2.469703",\ + "0.785366, 0.991898, 1.169490, 1.458123, 2.018450",\ + "0.793177, 0.999708, 1.177300, 1.465934, 2.026260",\ + "0.806596, 1.013127, 1.190719, 1.479353, 2.039679",\ + "0.959566, 1.166098, 1.343690, 1.632324, 2.192650",\ + "1.293635, 1.500166, 1.677758, 1.966392, 2.526718",\ + "1.116384, 1.297167, 1.473146, 1.761295, 2.320670",\ + "1.124194, 1.304977, 1.480956, 1.769106, 2.328480",\ + "1.137613, 1.318397, 1.494376, 1.782525, 2.341900",\ + "1.290584, 1.471367, 1.647346, 1.935495, 2.494870",\ + "1.624652, 1.805435, 1.981414, 2.269564, 2.828938"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046250, 0.046250, 0.046250, 0.046250, 0.046250",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2650*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.511815, 0.739156, 0.923211, 1.217666, 1.786831",\ + "0.531187, 0.758528, 0.942583, 1.237038, 1.806203",\ + "0.562641, 0.789981, 0.974037, 1.268491, 1.837657",\ + "0.851575, 1.078916, 1.262971, 1.557426, 2.126591",\ + "1.445467, 1.672808, 1.856863, 2.151318, 2.720483",\ + "0.600144, 0.826474, 1.010492, 1.304971, 1.874184",\ + "0.619516, 0.845846, 1.029864, 1.324343, 1.893556",\ + "0.650970, 0.877300, 1.061317, 1.355796, 1.925010",\ + "0.939904, 1.166234, 1.350252, 1.644731, 2.213945",\ + "1.533796, 1.760126, 1.944144, 2.238623, 2.807837",\ + "0.689248, 0.906807, 1.090519, 1.384999, 1.954216",\ + "0.708620, 0.926179, 1.109891, 1.404371, 1.973588",\ + "0.740074, 0.957633, 1.141344, 1.435825, 2.005042",\ + "1.029009, 1.246567, 1.430279, 1.724759, 2.293976",\ + "1.622900, 1.840459, 2.024171, 2.318651, 2.887868",\ + "0.752647, 0.964632, 1.148227, 1.442439, 2.011252",\ + "0.772019, 0.984004, 1.167598, 1.461811, 2.030624",\ + "0.803473, 1.015458, 1.199052, 1.493265, 2.062078",\ + "1.092407, 1.304392, 1.487987, 1.782200, 2.351013",\ + "1.686299, 1.898284, 2.081879, 2.376091, 2.944905",\ + "1.087484, 1.269911, 1.451885, 1.745620, 2.313499",\ + "1.106856, 1.289283, 1.471256, 1.764992, 2.332871",\ + "1.138310, 1.320737, 1.502710, 1.796445, 2.364325",\ + "1.427244, 1.609671, 1.791645, 2.085380, 2.653259",\ + "2.021136, 2.203563, 2.385537, 2.679272, 3.247151"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.521059, 0.748400, 0.932455, 1.226910, 1.796075",\ + "0.528870, 0.756210, 0.940265, 1.234720, 1.803885",\ + "0.542289, 0.769629, 0.953685, 1.248139, 1.817305",\ + "0.695259, 0.922600, 1.106655, 1.401110, 1.970275",\ + "1.029328, 1.256668, 1.440723, 1.735178, 2.304343",\ + "0.609388, 0.835718, 1.019736, 1.314215, 1.883428",\ + "0.617199, 0.843528, 1.027546, 1.322025, 1.891239",\ + "0.630618, 0.856948, 1.040965, 1.335444, 1.904658",\ + "0.783588, 1.009918, 1.193936, 1.488415, 2.057629",\ + "1.117657, 1.343987, 1.528004, 1.822483, 2.391697",\ + "0.698492, 0.916051, 1.099763, 1.394243, 1.963460",\ + "0.706303, 0.923862, 1.107573, 1.402054, 1.971270",\ + "0.719722, 0.937281, 1.120992, 1.415473, 1.984690",\ + "0.872692, 1.090251, 1.273963, 1.568443, 2.137660",\ + "1.206761, 1.424320, 1.608031, 1.902512, 2.471728",\ + "0.761891, 0.973876, 1.157471, 1.451683, 2.020496",\ + "0.769701, 0.981686, 1.165281, 1.459494, 2.028307",\ + "0.783120, 0.995106, 1.178700, 1.472913, 2.041726",\ + "0.936091, 1.148076, 1.331671, 1.625883, 2.194696",\ + "1.270159, 1.482144, 1.665739, 1.959952, 2.528765",\ + "1.096728, 1.279155, 1.461128, 1.754864, 2.322743",\ + "1.104538, 1.286965, 1.468939, 1.762674, 2.330553",\ + "1.117958, 1.300385, 1.482358, 1.776093, 2.343972",\ + "1.270928, 1.453355, 1.635329, 1.929064, 2.496943",\ + "1.604996, 1.787423, 1.969397, 2.263132, 2.831011"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2744*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.459602, 0.694897, 0.884768, 1.189946, 1.780432",\ + "0.478889, 0.714184, 0.904055, 1.209233, 1.799719",\ + "0.510523, 0.745818, 0.935689, 1.240867, 1.831353",\ + "0.800033, 1.035329, 1.225199, 1.530377, 2.120863",\ + "1.393967, 1.629262, 1.819133, 2.124311, 2.714797",\ + "0.548080, 0.782215, 0.972049, 1.277251, 1.867785",\ + "0.567367, 0.801502, 0.991336, 1.296538, 1.887073",\ + "0.599001, 0.833136, 1.022970, 1.328172, 1.918707",\ + "0.888512, 1.122647, 1.312480, 1.617682, 2.208217",\ + "1.482446, 1.716581, 1.906414, 2.211616, 2.802151",\ + "0.637650, 0.862548, 1.052076, 1.357279, 1.947817",\ + "0.656937, 0.881835, 1.071363, 1.376566, 1.967104",\ + "0.688571, 0.913469, 1.102997, 1.408201, 1.998738",\ + "0.978081, 1.202980, 1.392507, 1.697711, 2.288249",\ + "1.572015, 1.796914, 1.986441, 2.291645, 2.882183",\ + "0.701494, 0.920383, 1.109797, 1.414745, 2.004905",\ + "0.720781, 0.939670, 1.129084, 1.434032, 2.024192",\ + "0.752415, 0.971304, 1.160718, 1.465667, 2.055826",\ + "1.041925, 1.260814, 1.450228, 1.755177, 2.345336",\ + "1.635859, 1.854748, 2.044163, 2.349111, 2.939270",\ + "1.039162, 1.225730, 1.413457, 1.717948, 2.307214",\ + "1.058449, 1.245017, 1.432744, 1.737235, 2.326501",\ + "1.090083, 1.276651, 1.464378, 1.768869, 2.358135",\ + "1.379594, 1.566161, 1.753889, 2.058379, 2.647645",\ + "1.973528, 2.160095, 2.347823, 2.652313, 3.241579"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.469945, 0.705240, 0.895111, 1.200289, 1.790776",\ + "0.477744, 0.713040, 0.902911, 1.208089, 1.798575",\ + "0.491164, 0.726459, 0.916330, 1.221508, 1.811994",\ + "0.643898, 0.879193, 1.069064, 1.374242, 1.964728",\ + "0.977882, 1.213178, 1.403048, 1.708226, 2.298713",\ + "0.558424, 0.792559, 0.982392, 1.287594, 1.878129",\ + "0.566223, 0.800358, 0.990192, 1.295394, 1.885928",\ + "0.579643, 0.813778, 1.003611, 1.308813, 1.899348",\ + "0.732376, 0.966511, 1.156345, 1.461547, 2.052081",\ + "1.066361, 1.300496, 1.490329, 1.795531, 2.386066",\ + "0.647993, 0.872891, 1.062419, 1.367623, 1.958161",\ + "0.655793, 0.880691, 1.070219, 1.375422, 1.965960",\ + "0.669212, 0.894110, 1.083638, 1.388842, 1.979379",\ + "0.821946, 1.046844, 1.236372, 1.541575, 2.132113",\ + "1.155930, 1.380829, 1.570356, 1.875560, 2.466098",\ + "0.711837, 0.930726, 1.120141, 1.425089, 2.015248",\ + "0.719636, 0.938526, 1.127940, 1.432888, 2.023048",\ + "0.733056, 0.951945, 1.141359, 1.446308, 2.036467",\ + "0.885790, 1.104679, 1.294093, 1.599041, 2.189201",\ + "1.219774, 1.438663, 1.628078, 1.933026, 2.523185",\ + "1.049506, 1.236073, 1.423800, 1.728291, 2.317557",\ + "1.057305, 1.243873, 1.431600, 1.736091, 2.325356",\ + "1.070724, 1.257292, 1.445019, 1.749510, 2.338776",\ + "1.223458, 1.410026, 1.597753, 1.902244, 2.491510",\ + "1.557443, 1.744010, 1.931738, 2.236228, 2.825494"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[25]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.443166, 0.674145, 0.859025, 1.158118, 1.738072",\ + "0.462453, 0.693432, 0.878312, 1.177405, 1.757359",\ + "0.494087, 0.725066, 0.909946, 1.209039, 1.788993",\ + "0.783598, 1.014576, 1.199456, 1.498549, 2.078503",\ + "1.377531, 1.608510, 1.793390, 2.092483, 2.672437",\ + "0.531545, 0.761463, 0.946306, 1.245423, 1.825425",\ + "0.550832, 0.780750, 0.965593, 1.264710, 1.844712",\ + "0.582466, 0.812384, 0.997227, 1.296344, 1.876346",\ + "0.871976, 1.101894, 1.286737, 1.585854, 2.165856",\ + "1.465910, 1.695828, 1.880671, 2.179788, 2.759790",\ + "0.621124, 0.841793, 1.026333, 1.325452, 1.905457",\ + "0.640411, 0.861080, 1.045620, 1.344739, 1.924744",\ + "0.672045, 0.892714, 1.077254, 1.376373, 1.956378",\ + "0.961555, 1.182224, 1.366764, 1.665883, 2.245888",\ + "1.555489, 1.776158, 1.960698, 2.259817, 2.839822",\ + "0.685109, 0.899623, 1.084043, 1.382905, 1.962520",\ + "0.704396, 0.918910, 1.103330, 1.402192, 1.981807",\ + "0.736030, 0.950545, 1.134964, 1.433826, 2.013442",\ + "1.025540, 1.240054, 1.424474, 1.723336, 2.302952",\ + "1.619474, 1.833988, 2.018408, 2.317270, 2.896885",\ + "1.023662, 1.204930, 1.387700, 1.686096, 2.264800",\ + "1.042949, 1.224217, 1.406987, 1.705384, 2.284087",\ + "1.074583, 1.255852, 1.438621, 1.737018, 2.315721",\ + "1.364093, 1.545362, 1.728131, 2.026528, 2.605231",\ + "1.958027, 2.139296, 2.322065, 2.620461, 3.199165"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.453509, 0.684488, 0.869368, 1.168461, 1.748415",\ + "0.461309, 0.692287, 0.877167, 1.176260, 1.756214",\ + "0.474728, 0.705707, 0.890586, 1.189680, 1.769634",\ + "0.627462, 0.858441, 1.043320, 1.342414, 1.922367",\ + "0.961447, 1.192425, 1.377305, 1.676398, 2.256352",\ + "0.541888, 0.771806, 0.956649, 1.255766, 1.835768",\ + "0.549688, 0.779605, 0.964448, 1.263565, 1.843568",\ + "0.563107, 0.793025, 0.977867, 1.276985, 1.856987",\ + "0.715841, 0.945758, 1.130601, 1.429719, 2.009721",\ + "1.049826, 1.279743, 1.464586, 1.763703, 2.343705",\ + "0.631467, 0.852136, 1.036675, 1.335794, 1.915800",\ + "0.639266, 0.859936, 1.044475, 1.343594, 1.923599",\ + "0.652686, 0.873355, 1.057894, 1.357013, 1.937019",\ + "0.805420, 1.026089, 1.210628, 1.509747, 2.089752",\ + "1.139404, 1.360074, 1.544613, 1.843732, 2.423737",\ + "0.695451, 0.909966, 1.094386, 1.393248, 1.972863",\ + "0.703251, 0.917766, 1.102185, 1.401047, 1.980663",\ + "0.716670, 0.931185, 1.115605, 1.414467, 1.994082",\ + "0.869404, 1.083919, 1.268338, 1.567201, 2.146816",\ + "1.203389, 1.417904, 1.602323, 1.901185, 2.480801",\ + "1.034004, 1.215273, 1.398043, 1.696439, 2.275143",\ + "1.041804, 1.223073, 1.405843, 1.704239, 2.282942",\ + "1.055223, 1.236492, 1.419262, 1.717658, 2.296362",\ + "1.207957, 1.389226, 1.571996, 1.870392, 2.449096",\ + "1.541942, 1.723211, 1.905981, 2.204377, 2.783080"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002846, 0.075844, 0.162637, 0.322428, 0.642011"); + values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2400*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.356883, 0.553789, 0.735718, 1.027079, 1.590482",\ + "0.376149, 0.573056, 0.754984, 1.046346, 1.609749",\ + "0.407828, 0.604733, 0.786661, 1.078023, 1.641427",\ + "0.697481, 0.894382, 1.076308, 1.367671, 1.931077",\ + "1.291425, 1.488327, 1.670252, 1.961614, 2.525021",\ + "0.445232, 0.641107, 0.822999, 1.114385, 1.677836",\ + "0.464498, 0.660374, 0.842265, 1.133651, 1.697102",\ + "0.496176, 0.692052, 0.873942, 1.165328, 1.728780",\ + "0.785829, 0.981701, 1.163589, 1.454976, 2.018430",\ + "1.379774, 1.575645, 1.757533, 2.048919, 2.612374",\ + "0.534400, 0.721441, 0.903025, 1.194413, 1.757867",\ + "0.553666, 0.740707, 0.922292, 1.213680, 1.777134",\ + "0.585345, 0.772385, 0.953969, 1.245357, 1.808812",\ + "0.874998, 1.062034, 1.243616, 1.535004, 2.098462",\ + "1.468942, 1.655978, 1.837560, 2.128948, 2.692406",\ + "0.597862, 0.779261, 0.960728, 1.251846, 1.814890",\ + "0.617128, 0.798528, 0.979995, 1.271113, 1.834156",\ + "0.648807, 0.830206, 1.011672, 1.302790, 1.865834",\ + "0.938459, 1.119855, 1.301319, 1.592437, 2.155484",\ + "1.532403, 1.713799, 1.895263, 2.186381, 2.749428",\ + "0.904924, 1.084513, 1.264385, 1.555021, 2.117120",\ + "0.924190, 1.103779, 1.283652, 1.574288, 2.136386",\ + "0.955869, 1.135457, 1.315329, 1.605965, 2.168064",\ + "1.245522, 1.425106, 1.604976, 1.895612, 2.457714",\ + "1.839466, 2.019050, 2.198920, 2.489556, 3.051658"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195571, 2.195567, 2.195565, 2.195564, 2.195564",\ + "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195571, 2.195567, 2.195565, 2.195564, 2.195564",\ + "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195571, 2.195567, 2.195565, 2.195564, 2.195564",\ + "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195570, 2.195567, 2.195565, 2.195564, 2.195564",\ + "0.107384, 0.107384, 0.107384, 0.107384, 0.107384",\ + "0.140617, 0.140617, 0.140617, 0.140617, 0.140617",\ + "0.189796, 0.189796, 0.189796, 0.189796, 0.189796",\ + "0.817737, 0.817737, 0.817737, 0.817737, 0.817737",\ + "2.195571, 2.195567, 2.195565, 2.195564, 2.195564"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.367499, 0.564398, 0.746322, 1.037684, 1.601092",\ + "0.375296, 0.572195, 0.754119, 1.045481, 1.608889",\ + "0.388715, 0.585614, 0.767538, 1.058901, 1.622309",\ + "0.541390, 0.738291, 0.920216, 1.211578, 1.774985",\ + "0.875354, 1.072255, 1.254180, 1.545543, 2.108949",\ + "0.455848, 0.651716, 0.833603, 1.124989, 1.688446",\ + "0.463644, 0.659513, 0.841400, 1.132786, 1.696243",\ + "0.477064, 0.672932, 0.854819, 1.146206, 1.709662",\ + "0.629739, 0.825609, 1.007497, 1.298883, 1.862338",\ + "0.963703, 1.159573, 1.341461, 1.632848, 2.196303",\ + "0.545016, 0.732049, 0.913630, 1.205018, 1.768477",\ + "0.552812, 0.739846, 0.921427, 1.212815, 1.776274",\ + "0.566232, 0.753265, 0.934846, 1.226234, 1.789694",\ + "0.718907, 0.905942, 1.087524, 1.378912, 1.942370",\ + "1.052871, 1.239906, 1.421488, 1.712876, 2.276334",\ + "0.608477, 0.789870, 0.971332, 1.262451, 1.825500",\ + "0.616274, 0.797667, 0.979129, 1.270248, 1.833297",\ + "0.629693, 0.811086, 0.992549, 1.283667, 1.846716",\ + "0.782368, 0.963763, 1.145226, 1.436345, 1.999392",\ + "1.116332, 1.297727, 1.479191, 1.770309, 2.333357",\ + "0.915539, 1.095121, 1.274990, 1.565626, 2.127729",\ + "0.923336, 1.102918, 1.282787, 1.573422, 2.135526",\ + "0.936756, 1.116337, 1.296206, 1.586842, 2.148946",\ + "1.089431, 1.269014, 1.448884, 1.739519, 2.301622",\ + "1.423395, 1.602978, 1.782848, 2.073484, 2.635586"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201",\ + "0.049251, 0.049251, 0.049251, 0.049251, 0.049251",\ + "0.055579, 0.055579, 0.055579, 0.055579, 0.055579",\ + "0.075314, 0.075314, 0.075314, 0.075314, 0.075314",\ + "0.368762, 0.368762, 0.368762, 0.368762, 0.368762",\ + "1.002200, 1.002200, 1.002200, 1.002200, 1.002201"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2447*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.379724, 0.609078, 0.793072, 1.086354, 1.652961",\ + "0.399096, 0.628450, 0.812444, 1.105726, 1.672333",\ + "0.430550, 0.659904, 0.843898, 1.137180, 1.703787",\ + "0.719484, 0.948838, 1.132833, 1.426114, 1.992722",\ + "1.313376, 1.542730, 1.726725, 2.020006, 2.586613",\ + "0.468018, 0.696395, 0.880353, 1.173659, 1.740315",\ + "0.487390, 0.715767, 0.899725, 1.193031, 1.759686",\ + "0.518844, 0.747221, 0.931179, 1.224485, 1.791140",\ + "0.807778, 1.036156, 1.220114, 1.513419, 2.080075",\ + "1.401670, 1.630048, 1.814005, 2.107311, 2.673967",\ + "0.557713, 0.776723, 0.960380, 1.253688, 1.820346",\ + "0.577085, 0.796095, 0.979752, 1.273059, 1.839718",\ + "0.608539, 0.827548, 1.011206, 1.304513, 1.871172",\ + "0.897473, 1.116483, 1.300140, 1.593448, 2.160107",\ + "1.491365, 1.710375, 1.894032, 2.187340, 2.753998",\ + "0.621964, 0.834551, 1.018089, 1.311125, 1.877379",\ + "0.641336, 0.853923, 1.037461, 1.330497, 1.896751",\ + "0.672790, 0.885376, 1.068915, 1.361951, 1.928205",\ + "0.961724, 1.174311, 1.357849, 1.650886, 2.217139",\ + "1.555616, 1.768203, 1.951741, 2.244777, 2.811031",\ + "0.960843, 1.139831, 1.321745, 1.614302, 2.179622",\ + "0.980214, 1.159203, 1.341117, 1.633674, 2.198994",\ + "1.011668, 1.190656, 1.372571, 1.665128, 2.230447",\ + "1.300603, 1.479591, 1.661506, 1.954063, 2.519382",\ + "1.894495, 2.073483, 2.255398, 2.547955, 3.113274"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880",\ + "0.108154, 0.108154, 0.108154, 0.108154, 0.108154",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194880, 2.194880, 2.194880, 2.194880, 2.194880"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.388968, 0.618322, 0.802316, 1.095598, 1.662205",\ + "0.396778, 0.626132, 0.810127, 1.103408, 1.670016",\ + "0.410197, 0.639552, 0.823546, 1.116827, 1.683435",\ + "0.563168, 0.792522, 0.976516, 1.269798, 1.836405",\ + "0.897236, 1.126590, 1.310585, 1.603866, 2.170474",\ + "0.477262, 0.705639, 0.889597, 1.182903, 1.749559",\ + "0.485072, 0.713450, 0.897408, 1.190713, 1.757369",\ + "0.498491, 0.726869, 0.910827, 1.204133, 1.770788",\ + "0.651462, 0.879839, 1.063797, 1.357103, 1.923759",\ + "0.985530, 1.213908, 1.397866, 1.691172, 2.257827",\ + "0.566957, 0.785967, 0.969624, 1.262932, 1.829590",\ + "0.574767, 0.793777, 0.977435, 1.270742, 1.837401",\ + "0.588187, 0.807196, 0.990854, 1.284161, 1.850820",\ + "0.741157, 0.960167, 1.143824, 1.437132, 2.003790",\ + "1.075225, 1.294235, 1.477893, 1.771200, 2.337859",\ + "0.631208, 0.843795, 1.027333, 1.320369, 1.886623",\ + "0.639018, 0.851605, 1.035143, 1.328180, 1.894433",\ + "0.652438, 0.865024, 1.048563, 1.341599, 1.907853",\ + "0.805408, 1.017995, 1.201533, 1.494569, 2.060823",\ + "1.139476, 1.352063, 1.535602, 1.828638, 2.394892",\ + "0.970087, 1.149075, 1.330989, 1.623546, 2.188866",\ + "0.977897, 1.156885, 1.338800, 1.631357, 2.196676",\ + "0.991316, 1.170304, 1.352219, 1.644776, 2.210095",\ + "1.144287, 1.323275, 1.505189, 1.797747, 2.363066",\ + "1.478355, 1.657343, 1.839258, 2.131815, 2.697134"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046251, 0.046251, 0.046251, 0.046251, 0.046251",\ + "0.051898, 0.051898, 0.051898, 0.051898, 0.051898",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368839, 0.368839, 0.368839, 0.368839, 0.368839",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2729*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[30]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.369185, 0.583807, 0.762700, 1.052121, 1.613591",\ + "0.388557, 0.603178, 0.782071, 1.071493, 1.632963",\ + "0.420011, 0.634632, 0.813526, 1.102947, 1.664417",\ + "0.708947, 0.923568, 1.102462, 1.391883, 1.953353",\ + "1.302839, 1.517461, 1.696354, 1.985775, 2.547245",\ + "0.457459, 0.671124, 0.849981, 1.139426, 1.700945",\ + "0.476830, 0.690496, 0.869353, 1.158798, 1.720316",\ + "0.508285, 0.721950, 0.900807, 1.190252, 1.751771",\ + "0.797221, 1.010886, 1.189743, 1.479188, 2.040707",\ + "1.391113, 1.604778, 1.783635, 2.073080, 2.634599",\ + "0.547002, 0.751452, 0.930008, 1.219455, 1.780976",\ + "0.566373, 0.770824, 0.949379, 1.238826, 1.800348",\ + "0.597828, 0.802278, 0.980834, 1.270281, 1.831802",\ + "0.886764, 1.091214, 1.269770, 1.559216, 2.120738",\ + "1.480656, 1.685106, 1.863662, 2.153109, 2.714630",\ + "0.611070, 0.809282, 0.987704, 1.276886, 1.837996",\ + "0.630442, 0.828653, 1.007076, 1.296257, 1.857368",\ + "0.661896, 0.860107, 1.038530, 1.327712, 1.888822",\ + "0.950832, 1.149043, 1.327466, 1.616648, 2.177758",\ + "1.544724, 1.742936, 1.921358, 2.210540, 2.771650",\ + "0.934949, 1.114574, 1.291359, 1.580058, 2.140224",\ + "0.954320, 1.133946, 1.310730, 1.599430, 2.159595",\ + "0.985774, 1.165400, 1.342185, 1.630884, 2.191050",\ + "1.274710, 1.454336, 1.631121, 1.919820, 2.479985",\ + "1.868603, 2.048229, 2.225013, 2.513712, 3.073878"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.378431, 0.593053, 0.771946, 1.061368, 1.622838",\ + "0.386242, 0.600863, 0.779757, 1.069178, 1.630648",\ + "0.399661, 0.614283, 0.793176, 1.082597, 1.644067",\ + "0.552631, 0.767253, 0.946146, 1.235567, 1.797037",\ + "0.886699, 1.101321, 1.280214, 1.569635, 2.131105",\ + "0.466705, 0.680371, 0.859227, 1.148673, 1.710191",\ + "0.474516, 0.688181, 0.867038, 1.156483, 1.718002",\ + "0.487935, 0.701600, 0.880457, 1.169902, 1.731421",\ + "0.640905, 0.854570, 1.033427, 1.322872, 1.884391",\ + "0.974973, 1.188638, 1.367495, 1.656940, 2.218459",\ + "0.556248, 0.760699, 0.939254, 1.228701, 1.790223",\ + "0.564059, 0.768509, 0.947065, 1.236512, 1.798033",\ + "0.577478, 0.781928, 0.960484, 1.249931, 1.811453",\ + "0.730448, 0.934898, 1.113454, 1.402901, 1.964422",\ + "1.064516, 1.268966, 1.447522, 1.736969, 2.298491",\ + "0.620317, 0.818528, 0.996951, 1.286133, 1.847243",\ + "0.628127, 0.826339, 1.004761, 1.293943, 1.855053",\ + "0.641546, 0.839758, 1.018181, 1.307362, 1.868473",\ + "0.794516, 0.992728, 1.171150, 1.460332, 2.021443",\ + "1.128584, 1.326796, 1.505219, 1.794400, 2.355511",\ + "0.944195, 1.123821, 1.300605, 1.589304, 2.149470",\ + "0.952006, 1.131631, 1.308416, 1.597115, 2.157280",\ + "0.965425, 1.145051, 1.321835, 1.610534, 2.170700",\ + "1.118395, 1.298021, 1.474805, 1.763504, 2.323670",\ + "1.452463, 1.632089, 1.808873, 2.097572, 2.657738"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046253, 0.046253, 0.046253, 0.046253, 0.046253",\ + "0.051900, 0.051900, 0.051900, 0.051900, 0.051900",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2349*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.417064, 0.631505, 0.810363, 1.099808, 1.661366",\ + "0.436351, 0.650792, 0.829650, 1.119095, 1.680653",\ + "0.467985, 0.682426, 0.861284, 1.150729, 1.712287",\ + "0.757495, 0.971936, 1.150794, 1.440239, 2.001797",\ + "1.351429, 1.565870, 1.744728, 2.034173, 2.595731",\ + "0.505338, 0.718823, 0.897644, 1.187113, 1.748719",\ + "0.524625, 0.738110, 0.916931, 1.206400, 1.768006",\ + "0.556259, 0.769744, 0.948565, 1.238034, 1.799640",\ + "0.845769, 1.059254, 1.238075, 1.527544, 2.089150",\ + "1.439703, 1.653188, 1.832009, 2.121478, 2.683084",\ + "0.594882, 0.799151, 0.977671, 1.267141, 1.828751",\ + "0.614169, 0.818438, 0.996958, 1.286428, 1.848038",\ + "0.645804, 0.850072, 1.028592, 1.318063, 1.879672",\ + "0.935313, 1.139582, 1.318102, 1.607573, 2.169182",\ + "1.529247, 1.733516, 1.912036, 2.201506, 2.763116",\ + "0.658952, 0.856980, 1.035367, 1.324573, 1.885771",\ + "0.678239, 0.876267, 1.054654, 1.343860, 1.905058",\ + "0.709873, 0.907901, 1.086289, 1.375494, 1.936692",\ + "0.999383, 1.197411, 1.375799, 1.665004, 2.226202",\ + "1.593317, 1.791345, 1.969732, 2.258938, 2.820136",\ + "0.982644, 1.162273, 1.339022, 1.627745, 2.187998",\ + "1.001931, 1.181560, 1.358309, 1.647032, 2.207285",\ + "1.033565, 1.213194, 1.389943, 1.678666, 2.238919",\ + "1.323075, 1.502704, 1.679453, 1.968176, 2.528430",\ + "1.917009, 2.096638, 2.273387, 2.562110, 3.122364"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.427407, 0.641848, 0.820706, 1.110151, 1.671709",\ + "0.435207, 0.649648, 0.828505, 1.117950, 1.679508",\ + "0.448626, 0.663067, 0.841925, 1.131369, 1.692927",\ + "0.601360, 0.815801, 0.994659, 1.284103, 1.845661",\ + "0.935344, 1.149785, 1.328643, 1.618088, 2.179646",\ + "0.515681, 0.729166, 0.907987, 1.197456, 1.759062",\ + "0.523481, 0.736965, 0.915786, 1.205255, 1.766862",\ + "0.536900, 0.750385, 0.929206, 1.218675, 1.780281",\ + "0.689634, 0.903118, 1.081940, 1.371408, 1.933015",\ + "1.023618, 1.237103, 1.415924, 1.705393, 2.266999",\ + "0.605225, 0.809494, 0.988014, 1.277484, 1.839094",\ + "0.613025, 0.817293, 0.995813, 1.285284, 1.846893",\ + "0.626444, 0.830712, 1.009233, 1.298703, 1.860313",\ + "0.779178, 0.983446, 1.161967, 1.451437, 2.013046",\ + "1.113163, 1.317431, 1.495951, 1.785421, 2.347031",\ + "0.669295, 0.867323, 1.045710, 1.334916, 1.896114",\ + "0.677094, 0.875123, 1.053510, 1.342715, 1.903913",\ + "0.690513, 0.888542, 1.066929, 1.356135, 1.917333",\ + "0.843247, 1.041276, 1.219663, 1.508868, 2.070067",\ + "1.177232, 1.375260, 1.553648, 1.842853, 2.404051",\ + "0.992987, 1.172616, 1.349365, 1.638088, 2.198341",\ + "1.000786, 1.180416, 1.357164, 1.645887, 2.206141",\ + "1.014206, 1.193835, 1.370584, 1.659307, 2.219560",\ + "1.166939, 1.346569, 1.523317, 1.812040, 2.372294",\ + "1.500924, 1.680553, 1.857302, 2.146025, 2.706279"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2494*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.423145, 0.655225, 0.838651, 1.132010, 1.699224",\ + "0.442432, 0.674512, 0.857938, 1.151296, 1.718511",\ + "0.474066, 0.706146, 0.889572, 1.182931, 1.750145",\ + "0.763577, 0.995656, 1.179082, 1.472441, 2.039655",\ + "1.357510, 1.589590, 1.773016, 2.066375, 2.633589",\ + "0.511451, 0.742543, 0.925932, 1.219315, 1.786577",\ + "0.530738, 0.761829, 0.945219, 1.238602, 1.805864",\ + "0.562372, 0.793464, 0.976853, 1.270236, 1.837498",\ + "0.851883, 1.082974, 1.266363, 1.559746, 2.127008",\ + "1.445816, 1.676908, 1.860297, 2.153680, 2.720942",\ + "0.600820, 0.822873, 1.005959, 1.299343, 1.866609",\ + "0.620107, 0.842160, 1.025246, 1.318630, 1.885896",\ + "0.651741, 0.873794, 1.056880, 1.350264, 1.917530",\ + "0.941251, 1.163304, 1.346390, 1.639775, 2.207040",\ + "1.535185, 1.757238, 1.940324, 2.233708, 2.800974",\ + "0.664609, 0.880707, 1.063666, 1.356781, 1.923642",\ + "0.683896, 0.899994, 1.082952, 1.376068, 1.942929",\ + "0.715530, 0.931628, 1.114587, 1.407702, 1.974563",\ + "1.005041, 1.221138, 1.404097, 1.697213, 2.264073",\ + "1.598974, 1.815072, 1.998031, 2.291147, 2.858007",\ + "1.001916, 1.186040, 1.367322, 1.659959, 2.225884",\ + "1.021203, 1.205327, 1.386609, 1.679246, 2.245171",\ + "1.052837, 1.236961, 1.418243, 1.710881, 2.276805",\ + "1.342347, 1.526471, 1.707754, 2.000391, 2.566315",\ + "1.936281, 2.120405, 2.301688, 2.594325, 3.160249"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434",\ + "0.107537, 0.107537, 0.107537, 0.107537, 0.107537",\ + "0.140565, 0.140565, 0.140565, 0.140565, 0.140565",\ + "0.189766, 0.189766, 0.189766, 0.189766, 0.189766",\ + "0.817728, 0.817728, 0.817728, 0.817728, 0.817728",\ + "2.195434, 2.195434, 2.195434, 2.195434, 2.195434"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.433489, 0.665568, 0.848994, 1.142353, 1.709567",\ + "0.441288, 0.673367, 0.856794, 1.150152, 1.717367",\ + "0.454707, 0.686787, 0.870213, 1.163572, 1.730786",\ + "0.607441, 0.839521, 1.022947, 1.316305, 1.883520",\ + "0.941426, 1.173505, 1.356931, 1.650290, 2.217504",\ + "0.521794, 0.752886, 0.936275, 1.229658, 1.796920",\ + "0.529594, 0.760685, 0.944075, 1.237458, 1.804720",\ + "0.543013, 0.774105, 0.957494, 1.250877, 1.818139",\ + "0.695747, 0.926838, 1.110228, 1.403611, 1.970873",\ + "1.029732, 1.260823, 1.444212, 1.737595, 2.304857",\ + "0.611163, 0.833216, 1.016302, 1.309687, 1.876952",\ + "0.618962, 0.841016, 1.024101, 1.317486, 1.884752",\ + "0.632382, 0.854435, 1.037521, 1.330905, 1.898171",\ + "0.785116, 1.007169, 1.190255, 1.483639, 2.050905",\ + "1.119100, 1.341153, 1.524239, 1.817624, 2.384889",\ + "0.674952, 0.891050, 1.074009, 1.367125, 1.933985",\ + "0.682752, 0.898850, 1.081808, 1.374924, 1.941785",\ + "0.696171, 0.912269, 1.095228, 1.388343, 1.955204",\ + "0.848905, 1.065003, 1.247962, 1.541077, 2.107938",\ + "1.182890, 1.398987, 1.581946, 1.875062, 2.441922",\ + "1.012259, 1.196383, 1.377666, 1.670303, 2.236228",\ + "1.020059, 1.204182, 1.385465, 1.678102, 2.244027",\ + "1.033478, 1.217602, 1.398885, 1.691522, 2.257446",\ + "1.186212, 1.370336, 1.551618, 1.844255, 2.410180",\ + "1.520197, 1.704320, 1.885603, 2.178240, 2.744164"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182",\ + "0.049261, 0.049261, 0.049261, 0.049261, 0.049261",\ + "0.055612, 0.055612, 0.055612, 0.055612, 0.055612",\ + "0.075309, 0.075309, 0.075309, 0.075309, 0.075309",\ + "0.368777, 0.368777, 0.368777, 0.368777, 0.368777",\ + "1.002182, 1.002182, 1.002182, 1.002182, 1.002182"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2512*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.181258, 0.362750, 0.559584, 0.877059, 1.491654",\ + "0.196091, 0.377154, 0.575199, 0.895881, 1.517263",\ + "0.221299, 0.401436, 0.600771, 0.925894, 1.556997",\ + "0.494050, 0.669272, 0.865120, 1.207435, 1.883536",\ + "1.086888, 1.260498, 1.453339, 1.802428, 2.497703",\ + "0.268666, 0.450068, 0.646865, 0.964364, 1.579007",\ + "0.283499, 0.464472, 0.662480, 0.983186, 1.604617",\ + "0.308707, 0.488754, 0.688052, 1.013199, 1.644350",\ + "0.581459, 0.756590, 0.952401, 1.294740, 1.970890",\ + "1.174296, 1.347816, 1.540620, 1.889733, 2.585056",\ + "0.349534, 0.530400, 0.726892, 1.044393, 1.659039",\ + "0.364365, 0.544804, 0.742507, 1.063215, 1.684648",\ + "0.389566, 0.569086, 0.768079, 1.093227, 1.724382",\ + "0.662286, 0.836922, 1.032428, 1.374768, 2.050921",\ + "1.255114, 1.428148, 1.620646, 1.969761, 2.665088",\ + "0.407230, 0.588238, 0.784630, 1.101888, 1.716185",\ + "0.422055, 0.602641, 0.800248, 1.120718, 1.741811",\ + "0.447245, 0.626919, 0.825823, 1.150743, 1.781568",\ + "0.719903, 0.894737, 1.090165, 1.432339, 2.108216",\ + "1.312710, 1.485957, 1.678376, 2.027355, 2.722429",\ + "0.710204, 0.893608, 1.088293, 1.405116, 2.018565",\ + "0.724980, 0.907999, 1.103911, 1.423953, 2.044210",\ + "0.750065, 0.932253, 1.129487, 1.453987, 2.083996",\ + "1.022164, 1.199940, 1.393827, 1.735630, 2.410775",\ + "1.614788, 1.791118, 1.982037, 2.330666, 3.025044"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126844, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149772, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195024, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194128, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126849, 0.127605, 0.133435, 0.151631, 0.191178",\ + "0.149775, 0.150309, 0.154650, 0.170542, 0.205735",\ + "0.195028, 0.195582, 0.198470, 0.210618, 0.237900",\ + "0.816153, 0.816255, 0.816260, 0.817805, 0.821592",\ + "2.194129, 2.194405, 2.194418, 2.195894, 2.199512",\ + "0.126859, 0.127607, 0.133449, 0.151680, 0.191274",\ + "0.149782, 0.150311, 0.154660, 0.170585, 0.205820",\ + "0.195035, 0.195584, 0.198477, 0.210651, 0.237965",\ + "0.816155, 0.816256, 0.816260, 0.817810, 0.821601",\ + "2.194133, 2.194406, 2.194418, 2.195898, 2.199521",\ + "0.126945, 0.127627, 0.133451, 0.151721, 0.191389",\ + "0.149843, 0.150326, 0.154662, 0.170622, 0.205922",\ + "0.195098, 0.195599, 0.198478, 0.210679, 0.238045",\ + "0.816166, 0.816259, 0.816260, 0.817813, 0.821612",\ + "2.194165, 2.194413, 2.194418, 2.195902, 2.199532"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.117102, 0.379947, 0.573156, 0.882174, 1.479232",\ + "0.126091, 0.389068, 0.582472, 0.892519, 1.491929",\ + "0.141699, 0.404157, 0.597820, 0.909153, 1.511489",\ + "0.306945, 0.562483, 0.755606, 1.068523, 1.675209",\ + "0.649757, 0.897030, 1.089718, 1.401787, 2.006775",\ + "0.205481, 0.467265, 0.660437, 0.969479, 1.566586",\ + "0.214473, 0.476386, 0.669753, 0.979824, 1.579283",\ + "0.230076, 0.491475, 0.685100, 0.996458, 1.598842",\ + "0.395245, 0.649801, 0.842887, 1.155828, 1.762562",\ + "0.738017, 0.984348, 1.176999, 1.489092, 2.094129",\ + "0.294834, 0.547598, 0.740463, 1.049507, 1.646617",\ + "0.303840, 0.556719, 0.749780, 1.059852, 1.659314",\ + "0.319425, 0.571807, 0.765127, 1.076486, 1.678874",\ + "0.484368, 0.730134, 0.922914, 1.235856, 1.842594",\ + "0.827025, 1.064680, 1.257025, 1.569121, 2.174160",\ + "0.358511, 0.605438, 0.798193, 1.106982, 1.703722",\ + "0.367529, 0.614560, 0.807510, 1.117329, 1.716424",\ + "0.383098, 0.629648, 0.822858, 1.133967, 1.735991",\ + "0.547830, 0.787974, 0.980643, 1.293342, 1.899721",\ + "0.890379, 1.122520, 1.314754, 1.626604, 2.231284",\ + "0.695115, 0.910825, 1.101854, 1.410191, 2.006050",\ + "0.704209, 0.919948, 1.111171, 1.420541, 2.018759",\ + "0.719674, 0.935035, 1.126519, 1.437182, 2.038335",\ + "0.883062, 1.093358, 1.284304, 1.596561, 2.202077",\ + "1.224926, 1.427904, 1.618415, 1.929822, 2.533635"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.044794, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053408, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.044917, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053471, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.045280, 0.049393, 0.054601, 0.068665, 0.098782",\ + "0.053656, 0.055750, 0.059102, 0.072238, 0.101610",\ + "0.075784, 0.075784, 0.077996, 0.088605, 0.112682",\ + "0.368045, 0.368045, 0.368833, 0.370655, 0.374434",\ + "1.001402, 1.001402, 1.001776, 1.002637, 1.004422",\ + "0.045619, 0.049410, 0.054613, 0.068702, 0.098855",\ + "0.053828, 0.055759, 0.059110, 0.072274, 0.101681",\ + "0.075784, 0.075784, 0.078001, 0.088634, 0.112740",\ + "0.368045, 0.368045, 0.368835, 0.370660, 0.374443",\ + "1.001402, 1.001402, 1.001777, 1.002639, 1.004426",\ + "0.047777, 0.049532, 0.054615, 0.068733, 0.098943",\ + "0.054927, 0.055821, 0.059111, 0.072304, 0.101766",\ + "0.075784, 0.075784, 0.078002, 0.088659, 0.112810",\ + "0.368045, 0.368045, 0.368835, 0.370664, 0.374454",\ + "1.001402, 1.001402, 1.001777, 1.002641, 1.004432"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2747*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.496413, 0.709649, 0.894786, 1.185670, 1.745053",\ + "0.515784, 0.729021, 0.914158, 1.205042, 1.764425",\ + "0.547238, 0.760475, 0.945612, 1.236496, 1.795879",\ + "0.836174, 1.049411, 1.234548, 1.525432, 2.084815",\ + "1.430066, 1.643303, 1.828440, 2.119324, 2.678707",\ + "0.584781, 0.796968, 0.982067, 1.272975, 1.832407",\ + "0.604153, 0.816339, 1.001439, 1.292347, 1.851778",\ + "0.635607, 0.847793, 1.032893, 1.323801, 1.883232",\ + "0.924543, 1.136729, 1.321829, 1.612737, 2.172168",\ + "1.518435, 1.730622, 1.915721, 2.206629, 2.766061",\ + "0.673752, 0.877303, 1.062094, 1.353004, 1.912438",\ + "0.693124, 0.896674, 1.081466, 1.372375, 1.931810",\ + "0.724578, 0.928128, 1.112920, 1.403829, 1.963264",\ + "1.013514, 1.217064, 1.401856, 1.692765, 2.252200",\ + "1.607406, 1.810957, 1.995748, 2.286657, 2.846092",\ + "0.736919, 0.935130, 1.119804, 1.410431, 1.969450",\ + "0.756291, 0.954502, 1.139176, 1.429803, 1.988822",\ + "0.787745, 0.985956, 1.170630, 1.461257, 2.020276",\ + "1.076681, 1.274892, 1.459566, 1.750193, 2.309212",\ + "1.670573, 1.868784, 2.053458, 2.344085, 2.903104",\ + "1.058360, 1.240438, 1.423463, 1.713602, 2.271667",\ + "1.077731, 1.259810, 1.442835, 1.732974, 2.291038",\ + "1.109185, 1.291264, 1.474289, 1.764428, 2.322492",\ + "1.398121, 1.580200, 1.763225, 2.053364, 2.611428",\ + "1.992013, 2.174092, 2.357117, 2.647256, 3.205320"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.505659, 0.718896, 0.904033, 1.194916, 1.754300",\ + "0.513469, 0.726706, 0.911843, 1.202727, 1.762110",\ + "0.526889, 0.740125, 0.925263, 1.216146, 1.775529",\ + "0.679859, 0.893095, 1.078233, 1.369116, 1.928499",\ + "1.013927, 1.227163, 1.412301, 1.703184, 2.262567",\ + "0.594028, 0.806214, 0.991314, 1.282222, 1.841653",\ + "0.601838, 0.814024, 0.999124, 1.290032, 1.849463",\ + "0.615257, 0.827444, 1.012543, 1.303451, 1.862883",\ + "0.768227, 0.980414, 1.165513, 1.456421, 2.015853",\ + "1.102295, 1.314482, 1.499582, 1.790489, 2.349921",\ + "0.682999, 0.886549, 1.071341, 1.362250, 1.921685",\ + "0.690809, 0.894360, 1.079151, 1.370060, 1.929495",\ + "0.704229, 0.907779, 1.092570, 1.383480, 1.942914",\ + "0.857199, 1.060749, 1.245540, 1.536450, 2.095884",\ + "1.191267, 1.394817, 1.579608, 1.870518, 2.429952",\ + "0.746166, 0.944377, 1.129050, 1.419678, 1.978696",\ + "0.753976, 0.952187, 1.136861, 1.427488, 1.986507",\ + "0.767395, 0.965607, 1.150280, 1.440908, 1.999926",\ + "0.920365, 1.118577, 1.303250, 1.593878, 2.152896",\ + "1.254433, 1.452645, 1.637318, 1.927946, 2.486964",\ + "1.067606, 1.249685, 1.432710, 1.722849, 2.280913",\ + "1.075416, 1.257495, 1.440520, 1.730659, 2.288723",\ + "1.088836, 1.270914, 1.453939, 1.744078, 2.302143",\ + "1.241806, 1.423884, 1.606909, 1.897048, 2.455113",\ + "1.575874, 1.757952, 1.940977, 2.231116, 2.789181"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2380*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.099932, 0.259054, 0.413318, 0.663965, 1.151026",\ + "0.112861, 0.280635, 0.445926, 0.710841, 1.223619",\ + "0.139635, 0.312455, 0.491350, 0.774619, 1.320764",\ + "0.427093, 0.638536, 0.826241, 1.153952, 1.801309",\ + "1.022612, 1.250759, 1.440120, 1.765390, 2.405472",\ + "0.187338, 0.346372, 0.500599, 0.751271, 1.238380",\ + "0.200267, 0.367953, 0.533207, 0.798146, 1.310972",\ + "0.227041, 0.399773, 0.578631, 0.861924, 1.408118",\ + "0.515372, 0.725854, 0.913522, 1.241257, 1.888662",\ + "1.110934, 1.338077, 1.527401, 1.852695, 2.492826",\ + "0.268065, 0.426703, 0.580626, 0.831299, 1.318411",\ + "0.281048, 0.448284, 0.613234, 0.878174, 1.391004",\ + "0.307853, 0.480104, 0.658657, 0.941953, 1.488149",\ + "0.604596, 0.806184, 0.993549, 1.321285, 1.968694",\ + "1.200284, 1.418408, 1.607428, 1.932723, 2.572857",\ + "0.325504, 0.484459, 0.638266, 0.888640, 1.375251",\ + "0.338594, 0.506071, 0.670899, 0.935546, 1.447905",\ + "0.365461, 0.537910, 0.716354, 0.999365, 1.545131",\ + "0.668221, 0.863995, 1.051266, 1.378821, 2.025920",\ + "1.264029, 1.476232, 1.665149, 1.990250, 2.630066",\ + "0.626239, 0.789242, 0.941912, 1.191734, 1.677259",\ + "0.640305, 0.811082, 0.974549, 1.238668, 1.749989",\ + "0.667742, 0.843054, 1.020009, 1.302522, 1.847312",\ + "0.992829, 1.169169, 1.354925, 1.682082, 2.328396",\ + "1.601053, 1.781498, 1.968808, 2.293504, 2.932521"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.028418, 0.053985, 0.061562, 0.076171, 0.106327",\ + "0.053853, 0.080619, 0.084946, 0.098515, 0.128974",\ + "0.117398, 0.123775, 0.136709, 0.151501, 0.176771",\ + "0.813025, 0.813025, 0.813025, 0.814975, 0.819748",\ + "2.191540, 2.192948, 2.194009, 2.200710, 2.216247",\ + "0.028418, 0.053985, 0.061562, 0.076171, 0.106327",\ + "0.053853, 0.080619, 0.084946, 0.098515, 0.128974",\ + "0.117398, 0.123775, 0.136709, 0.151501, 0.176771",\ + "0.813025, 0.813025, 0.813025, 0.814975, 0.819748",\ + "2.191577, 2.192948, 2.194009, 2.200710, 2.216247",\ + "0.028577, 0.053985, 0.061562, 0.076171, 0.106327",\ + "0.054019, 0.080619, 0.084946, 0.098515, 0.128974",\ + "0.117437, 0.123775, 0.136709, 0.151501, 0.176771",\ + "0.813025, 0.813025, 0.813025, 0.814975, 0.819748",\ + "2.191688, 2.192948, 2.194009, 2.200710, 2.216247",\ + "0.028892, 0.054081, 0.061577, 0.076207, 0.106399",\ + "0.054349, 0.080719, 0.084954, 0.098552, 0.129047",\ + "0.117516, 0.123799, 0.136740, 0.151532, 0.176832",\ + "0.813025, 0.813025, 0.813025, 0.814981, 0.819759",\ + "2.191792, 2.192953, 2.194012, 2.200729, 2.216285",\ + "0.031778, 0.054753, 0.061580, 0.076239, 0.106487",\ + "0.057369, 0.081423, 0.084955, 0.098584, 0.129136",\ + "0.118236, 0.123966, 0.136744, 0.151558, 0.176905",\ + "0.813025, 0.813025, 0.813025, 0.814986, 0.819773",\ + "2.192455, 2.192990, 2.194012, 2.200745, 2.216330"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.071387, 0.284408, 0.492606, 0.801306, 1.367433",\ + "0.077667, 0.305792, 0.517732, 0.814342, 1.385042",\ + "0.090238, 0.334877, 0.530841, 0.830649, 1.407555",\ + "0.256635, 0.477338, 0.671832, 0.978257, 1.567975",\ + "0.595228, 0.802461, 0.996271, 1.304460, 1.898944",\ + "0.158934, 0.371732, 0.579823, 0.888611, 1.454786",\ + "0.165476, 0.393159, 0.605013, 0.901647, 1.472395",\ + "0.178302, 0.422304, 0.618122, 0.917954, 1.494908",\ + "0.344810, 0.564656, 0.759113, 1.065562, 1.655329",\ + "0.683378, 0.889779, 1.083552, 1.391765, 1.986297",\ + "0.245972, 0.460189, 0.667780, 0.968640, 1.534818",\ + "0.253296, 0.481714, 0.685040, 0.981676, 1.552427",\ + "0.266884, 0.507931, 0.698149, 0.997983, 1.574940",\ + "0.433723, 0.644987, 0.839140, 1.145591, 1.735360",\ + "0.772213, 0.970110, 1.163579, 1.471793, 2.066329",\ + "0.307535, 0.525062, 0.731901, 1.026077, 1.591848",\ + "0.315597, 0.546729, 0.742759, 1.039118, 1.609468",\ + "0.329903, 0.565774, 0.755873, 1.055433, 1.631996",\ + "0.497055, 0.702831, 0.896872, 1.203056, 1.792447",\ + "0.835472, 1.027940, 1.221311, 1.529264, 2.123427",\ + "0.630646, 0.853005, 1.036340, 1.329254, 1.894087",\ + "0.643411, 0.859949, 1.046418, 1.342300, 1.911721",\ + "0.662302, 0.871170, 1.059532, 1.358621, 1.934267",\ + "0.824001, 1.008235, 1.200534, 1.506258, 2.094755",\ + "1.152404, 1.333245, 1.524972, 1.832471, 2.425749"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.014090, 0.057759, 0.075820, 0.080331, 0.107469",\ + "0.025180, 0.064799, 0.067612, 0.083095, 0.115487",\ + "0.053782, 0.083479, 0.086622, 0.102435, 0.134993",\ + "0.368605, 0.368605, 0.369812, 0.373454, 0.381327",\ + "1.000406, 1.000406, 1.002137, 1.003830, 1.006481",\ + "0.014987, 0.057834, 0.075890, 0.080331, 0.107469",\ + "0.026088, 0.064832, 0.067612, 0.083095, 0.115487",\ + "0.054430, 0.083516, 0.086622, 0.102435, 0.134993",\ + "0.368605, 0.368605, 0.369812, 0.373454, 0.381327",\ + "1.000406, 1.000406, 1.002137, 1.003830, 1.006481",\ + "0.017662, 0.058002, 0.075892, 0.080331, 0.107469",\ + "0.028799, 0.064906, 0.067612, 0.083095, 0.115487",\ + "0.056363, 0.078451, 0.086622, 0.102435, 0.134993",\ + "0.368605, 0.368605, 0.369812, 0.373454, 0.381327",\ + "1.000406, 1.000406, 1.002137, 1.003830, 1.006481",\ + "0.020186, 0.058246, 0.075896, 0.080364, 0.107535",\ + "0.031356, 0.065014, 0.067628, 0.083134, 0.115565",\ + "0.058188, 0.078544, 0.086639, 0.102475, 0.135071",\ + "0.368605, 0.368605, 0.369814, 0.373463, 0.381346",\ + "1.000406, 1.000406, 1.002141, 1.003834, 1.006488",\ + "0.036287, 0.049252, 0.064182, 0.080393, 0.107614",\ + "0.047669, 0.060805, 0.067630, 0.083168, 0.115659",\ + "0.069823, 0.079193, 0.086642, 0.102509, 0.135166",\ + "0.368605, 0.368605, 0.369815, 0.373471, 0.381369",\ + "1.000406, 1.000406, 1.002141, 1.003836, 1.006495"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2421*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.473885, 0.684615, 0.861464, 1.145505, 1.695445",\ + "0.493257, 0.703986, 0.880836, 1.164877, 1.714816",\ + "0.524711, 0.735440, 0.912290, 1.196331, 1.746270",\ + "0.813647, 1.024377, 1.201226, 1.485267, 2.035206",\ + "1.407539, 1.618269, 1.795118, 2.079159, 2.629098",\ + "0.562155, 0.771933, 0.948745, 1.232810, 1.782798",\ + "0.581527, 0.791304, 0.968117, 1.252182, 1.802170",\ + "0.612981, 0.822758, 0.999571, 1.283636, 1.833624",\ + "0.901917, 1.111694, 1.288507, 1.572572, 2.122560",\ + "1.495809, 1.705587, 1.882399, 2.166464, 2.716452",\ + "0.651344, 0.852264, 1.028772, 1.312839, 1.862830",\ + "0.670716, 0.871635, 1.048143, 1.332211, 1.882201",\ + "0.702170, 0.903089, 1.079598, 1.363665, 1.913656",\ + "0.991106, 1.192025, 1.368534, 1.652601, 2.202591",\ + "1.584998, 1.785918, 1.962426, 2.246493, 2.796484",\ + "0.714933, 0.910084, 1.086463, 1.370256, 1.919821",\ + "0.734305, 0.929456, 1.105835, 1.389627, 1.939192",\ + "0.765759, 0.960910, 1.137289, 1.421082, 1.970646",\ + "1.054695, 1.249846, 1.426225, 1.710018, 2.259583",\ + "1.648587, 1.843739, 2.020117, 2.303910, 2.853475",\ + "1.036585, 1.215328, 1.390118, 1.673416, 2.222012",\ + "1.055957, 1.234700, 1.409489, 1.692788, 2.241384",\ + "1.087411, 1.266154, 1.440943, 1.724242, 2.272838",\ + "1.376347, 1.555090, 1.729879, 2.013178, 2.561774",\ + "1.970239, 2.148982, 2.323771, 2.607070, 3.155666"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882",\ + "0.108153, 0.108153, 0.108153, 0.108153, 0.108153",\ + "0.141536, 0.141536, 0.141536, 0.141536, 0.141536",\ + "0.190539, 0.190539, 0.190539, 0.190539, 0.190539",\ + "0.817689, 0.817689, 0.817689, 0.817689, 0.817689",\ + "2.194882, 2.194882, 2.194882, 2.194882, 2.194882"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.483132, 0.693861, 0.870710, 1.154752, 1.704691",\ + "0.490942, 0.701672, 0.878521, 1.162562, 1.712502",\ + "0.504361, 0.715091, 0.891940, 1.175981, 1.725921",\ + "0.657331, 0.868061, 1.044910, 1.328951, 1.878891",\ + "0.991399, 1.202129, 1.378978, 1.663020, 2.212959",\ + "0.571402, 0.781179, 0.957991, 1.242057, 1.792045",\ + "0.579212, 0.788990, 0.965802, 1.249867, 1.799855",\ + "0.592631, 0.802409, 0.979221, 1.263286, 1.813274",\ + "0.745601, 0.955379, 1.132191, 1.416256, 1.966244",\ + "1.079669, 1.289447, 1.466259, 1.750325, 2.300312",\ + "0.660591, 0.861510, 1.038018, 1.322085, 1.872076",\ + "0.668401, 0.869320, 1.045829, 1.329896, 1.879887",\ + "0.681820, 0.882740, 1.059248, 1.343315, 1.893306",\ + "0.834790, 1.035710, 1.212218, 1.496285, 2.046276",\ + "1.168858, 1.369778, 1.546286, 1.830353, 2.380344",\ + "0.724180, 0.919331, 1.095710, 1.379503, 1.929067",\ + "0.731990, 0.927141, 1.103520, 1.387313, 1.936877",\ + "0.745409, 0.940561, 1.116939, 1.400732, 1.950297",\ + "0.898379, 1.093531, 1.269909, 1.553702, 2.103267",\ + "1.232447, 1.427599, 1.603977, 1.887770, 2.437335",\ + "1.045832, 1.224575, 1.399364, 1.682663, 2.231259",\ + "1.053642, 1.232385, 1.407174, 1.690473, 2.239069",\ + "1.067061, 1.245804, 1.420594, 1.703892, 2.252488",\ + "1.220031, 1.398774, 1.573564, 1.856862, 2.405458",\ + "1.554100, 1.732842, 1.907632, 2.190930, 2.739527"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000540, 0.001536, 0.012434, 0.035370"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959",\ + "0.046252, 0.046252, 0.046252, 0.046252, 0.046252",\ + "0.051899, 0.051899, 0.051899, 0.051899, 0.051899",\ + "0.075290, 0.075290, 0.075290, 0.075290, 0.075290",\ + "0.368838, 0.368838, 0.368838, 0.368838, 0.368838",\ + "1.000959, 1.000959, 1.000959, 1.000959, 1.000959"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[5]_redg_min_2516*/ + +} /* end of pin tl_o[5] */ + +pin("tl_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.778821, 1.003429, 1.297149, 1.790603, 2.777510",\ + "0.825348, 1.049956, 1.343676, 1.837130, 2.824038",\ + "0.910982, 1.135590, 1.429310, 1.922764, 2.909672",\ + "1.134301, 1.358909, 1.652629, 2.146083, 3.132991",\ + "1.698246, 1.922854, 2.216574, 2.710028, 3.696936",\ + "0.866262, 1.091031, 1.384796, 1.877318, 2.863444",\ + "0.912789, 1.137558, 1.431323, 1.923846, 2.909971",\ + "0.998423, 1.223192, 1.516957, 2.009480, 2.995605",\ + "1.221742, 1.446511, 1.740276, 2.232799, 3.218925",\ + "1.785687, 2.010456, 2.304221, 2.796744, 3.782870",\ + "0.947141, 1.180161, 1.472762, 1.964941, 2.950399",\ + "0.993669, 1.226688, 1.519289, 2.011468, 2.996926",\ + "1.079303, 1.312322, 1.604924, 2.097103, 3.082561",\ + "1.302622, 1.535641, 1.828242, 2.320421, 3.305880",\ + "1.866567, 2.099586, 2.392188, 2.884367, 3.869825",\ + "1.004861, 1.246014, 1.536906, 2.028855, 3.013908",\ + "1.051388, 1.292541, 1.583433, 2.075382, 3.060435",\ + "1.137022, 1.378175, 1.669067, 2.161016, 3.146070",\ + "1.360341, 1.601494, 1.892386, 2.384335, 3.369389",\ + "1.924286, 2.165440, 2.456331, 2.948280, 3.933334",\ + "1.307537, 1.612873, 1.889025, 2.378309, 3.359364",\ + "1.354064, 1.659401, 1.935552, 2.424836, 3.405891",\ + "1.439698, 1.745035, 2.021186, 2.510470, 3.491526",\ + "1.663017, 1.968354, 2.244505, 2.733789, 3.714845",\ + "2.226962, 2.532299, 2.808450, 3.297734, 4.278790"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163010, 2.163010, 2.163010, 2.163010"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.717206, 0.941815, 1.235535, 1.728989, 2.715896",\ + "0.770496, 0.995104, 1.288824, 1.782278, 2.769186",\ + "0.831244, 1.055852, 1.349573, 1.843026, 2.829934",\ + "0.965956, 1.190564, 1.484284, 1.977738, 2.964645",\ + "1.312464, 1.537072, 1.830792, 2.324246, 3.311154",\ + "0.804648, 1.029416, 1.323182, 1.815704, 2.801830",\ + "0.857937, 1.082706, 1.376471, 1.868994, 2.855119",\ + "0.918686, 1.143454, 1.437219, 1.929742, 2.915868",\ + "1.053397, 1.278166, 1.571931, 2.064453, 3.050579",\ + "1.399905, 1.624674, 1.918439, 2.410962, 3.397088",\ + "0.885527, 1.118547, 1.411148, 1.903327, 2.888785",\ + "0.938817, 1.171836, 1.464437, 1.956616, 2.942075",\ + "0.999565, 1.232585, 1.525186, 2.017365, 3.002823",\ + "1.134276, 1.367296, 1.659897, 2.152076, 3.137534",\ + "1.480785, 1.713804, 2.006406, 2.498585, 3.484043",\ + "0.943246, 1.184400, 1.475292, 1.967241, 2.952294",\ + "0.996536, 1.237689, 1.528581, 2.020530, 3.005584",\ + "1.057284, 1.298438, 1.589330, 2.081279, 3.066332",\ + "1.191995, 1.433149, 1.724041, 2.215990, 3.201043",\ + "1.538504, 1.779658, 2.070549, 2.562499, 3.547552",\ + "1.245923, 1.551259, 1.827411, 2.316695, 3.297750",\ + "1.299212, 1.604549, 1.880700, 2.369984, 3.351039",\ + "1.359961, 1.665297, 1.941449, 2.430732, 3.411788",\ + "1.494672, 1.800008, 2.076160, 2.565444, 3.546499",\ + "1.841180, 2.146517, 2.422668, 2.911952, 3.893008"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060037",\ + "0.113990, 0.113990, 0.113990, 0.113990, 0.113990",\ + "0.199694, 0.199694, 0.199694, 0.199694, 0.199694",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2677*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.619374, 0.887475, 1.180133, 1.686418, 2.698987",\ + "0.666474, 0.934595, 1.227354, 1.733911, 2.747024",\ + "0.753747, 1.021925, 1.314971, 1.822307, 2.836977",\ + "0.979596, 1.247862, 1.541350, 2.049887, 3.066961",\ + "1.546840, 1.815220, 2.109287, 2.619390, 3.639598",\ + "0.706782, 0.975064, 1.267816, 1.773132, 2.784921",\ + "0.753882, 1.022185, 1.315038, 1.820625, 2.832958",\ + "0.841156, 1.109515, 1.402658, 1.909021, 2.922911",\ + "1.067004, 1.335453, 1.629041, 2.136601, 3.152895",\ + "1.634248, 1.902812, 2.196982, 2.706105, 3.725532",\ + "0.790149, 1.064125, 1.355782, 1.860753, 2.871876",\ + "0.837250, 1.111246, 1.403004, 1.908246, 2.919913",\ + "0.924524, 1.198577, 1.490623, 1.996642, 3.009866",\ + "1.150375, 1.424515, 1.717007, 2.224223, 3.239850",\ + "1.717623, 1.991877, 2.284948, 2.793726, 3.812487",\ + "0.853818, 1.129875, 1.419928, 1.924667, 2.935385",\ + "0.900919, 1.176996, 1.467150, 1.972159, 2.983422",\ + "0.988195, 1.264329, 1.554770, 2.060555, 3.073375",\ + "1.214048, 1.490269, 1.781153, 2.288136, 3.303359",\ + "1.781297, 2.057633, 2.349094, 2.857639, 3.875996",\ + "1.190374, 1.495641, 1.772172, 2.274166, 3.280841",\ + "1.237478, 1.542768, 1.819397, 2.321660, 3.328878",\ + "1.324760, 1.630116, 1.907025, 2.410059, 3.418831",\ + "1.550623, 1.856080, 2.133420, 2.637645, 3.648815",\ + "2.117886, 2.423474, 2.701378, 3.207154, 4.221452"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.053871, 0.053928, 0.055014, 0.058545, 0.065606",\ + "0.173261, 0.173221, 0.173020, 0.172475, 0.171386",\ + "0.375447, 0.375353, 0.374960, 0.373952, 0.371937",\ + "0.885472, 0.885429, 0.885258, 0.884858, 0.884057",\ + "2.163064, 2.163128, 2.163351, 2.163842, 2.164825",\ + "0.053871, 0.053928, 0.055025, 0.058545, 0.065606",\ + "0.173261, 0.173221, 0.173019, 0.172475, 0.171386",\ + "0.375447, 0.375352, 0.374957, 0.373952, 0.371937",\ + "0.885472, 0.885428, 0.885257, 0.884858, 0.884057",\ + "2.163064, 2.163129, 2.163352, 2.163842, 2.164825",\ + "0.053872, 0.053929, 0.055025, 0.058545, 0.065606",\ + "0.173260, 0.173220, 0.173019, 0.172475, 0.171386",\ + "0.375444, 0.375351, 0.374957, 0.373952, 0.371937",\ + "0.885472, 0.885428, 0.885257, 0.884858, 0.884057",\ + "2.163065, 2.163130, 2.163352, 2.163842, 2.164825",\ + "0.053873, 0.053930, 0.055026, 0.058545, 0.065606",\ + "0.173259, 0.173219, 0.173019, 0.172475, 0.171386",\ + "0.375442, 0.375349, 0.374957, 0.373952, 0.371937",\ + "0.885471, 0.885427, 0.885257, 0.884858, 0.884057",\ + "2.163066, 2.163132, 2.163352, 2.163842, 2.164825",\ + "0.053880, 0.053946, 0.055062, 0.058559, 0.065606",\ + "0.173255, 0.173209, 0.173013, 0.172473, 0.171386",\ + "0.375432, 0.375324, 0.374946, 0.373948, 0.371937",\ + "0.885469, 0.885413, 0.885253, 0.884856, 0.884057",\ + "2.163070, 2.163151, 2.163357, 2.163844, 2.164825"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.549769, 0.817593, 1.110465, 1.618513, 2.634607",\ + "0.610729, 0.878819, 1.171421, 1.677554, 2.689819",\ + "0.677494, 0.945792, 1.239448, 1.748438, 2.766419",\ + "0.811699, 1.079980, 1.373547, 1.882297, 2.899797",\ + "1.155145, 1.423320, 1.716351, 2.223647, 3.238237",\ + "0.637177, 0.905181, 1.198154, 1.705227, 2.720541",\ + "0.698137, 0.966409, 1.259104, 1.764268, 2.775753",\ + "0.764902, 1.033383, 1.327140, 1.835153, 2.852353",\ + "0.899107, 1.167571, 1.461238, 1.969011, 2.985731",\ + "1.242554, 1.510911, 1.804038, 2.310361, 3.324171",\ + "0.720537, 0.994237, 1.286120, 1.792848, 2.807496",\ + "0.781504, 1.055469, 1.347070, 1.851890, 2.862708",\ + "0.848274, 1.122447, 1.415106, 1.922774, 2.939308",\ + "0.982479, 1.256634, 1.549204, 2.056633, 3.072686",\ + "1.325922, 1.599972, 1.892004, 2.397983, 3.411126",\ + "0.784201, 1.059981, 1.350266, 1.856762, 2.871005",\ + "0.845173, 1.121219, 1.411216, 1.915803, 2.926217",\ + "0.911947, 1.188202, 1.479252, 1.986687, 3.002817",\ + "1.046151, 1.322389, 1.613351, 2.120546, 3.136195",\ + "1.389593, 1.665724, 1.956150, 2.461896, 3.474635",\ + "1.120725, 1.425673, 1.702529, 2.206268, 3.216461",\ + "1.181728, 1.486982, 1.763459, 2.265301, 3.271673",\ + "1.248526, 1.554021, 1.831524, 2.336198, 3.348273",\ + "1.382729, 1.688203, 1.965620, 2.470056, 3.481651",\ + "1.726158, 2.031510, 2.308404, 2.811399, 3.820091"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.071629, 0.072032, 0.074063, 0.079575, 0.090597",\ + "0.129720, 0.130266, 0.133020, 0.140492, 0.155435",\ + "0.214056, 0.214554, 0.217069, 0.223890, 0.237532",\ + "0.447094, 0.447150, 0.447431, 0.448194, 0.449721",\ + "1.100693, 1.100667, 1.100537, 1.100183, 1.099477",\ + "0.071629, 0.072034, 0.074081, 0.079575, 0.090597",\ + "0.129720, 0.130270, 0.133044, 0.140492, 0.155435",\ + "0.214056, 0.214558, 0.217090, 0.223890, 0.237532",\ + "0.447094, 0.447150, 0.447434, 0.448194, 0.449721",\ + "1.100693, 1.100667, 1.100536, 1.100183, 1.099477",\ + "0.071640, 0.072041, 0.074081, 0.079575, 0.090597",\ + "0.129735, 0.130278, 0.133044, 0.140492, 0.155435",\ + "0.214069, 0.214565, 0.217091, 0.223890, 0.237532",\ + "0.447096, 0.447151, 0.447434, 0.448194, 0.449721",\ + "1.100692, 1.100666, 1.100536, 1.100183, 1.099477",\ + "0.071647, 0.072050, 0.074082, 0.079575, 0.090597",\ + "0.129745, 0.130291, 0.133046, 0.140492, 0.155435",\ + "0.214078, 0.214577, 0.217092, 0.223890, 0.237532",\ + "0.447097, 0.447152, 0.447434, 0.448194, 0.449721",\ + "1.100691, 1.100666, 1.100535, 1.100183, 1.099477",\ + "0.071694, 0.072157, 0.074138, 0.079598, 0.090597",\ + "0.129808, 0.130436, 0.133121, 0.140523, 0.155435",\ + "0.214136, 0.214709, 0.217161, 0.223918, 0.237532",\ + "0.447103, 0.447167, 0.447442, 0.448198, 0.449721",\ + "1.100688, 1.100659, 1.100532, 1.100182, 1.099477"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2675*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.603037, 0.850281, 1.131477, 1.604469, 2.550452",\ + "0.650138, 0.897409, 1.178701, 1.651927, 2.598380",\ + "0.737413, 0.984763, 1.266326, 1.740225, 2.688022",\ + "0.963264, 1.210735, 1.492718, 1.967654, 2.917526",\ + "1.530512, 1.778140, 2.060669, 2.536958, 3.489536",\ + "0.690439, 0.937872, 1.219053, 1.691182, 2.636385",\ + "0.737540, 0.985001, 1.266277, 1.738640, 2.684314",\ + "0.824816, 1.072355, 1.353904, 1.826938, 2.773956",\ + "1.050667, 1.298328, 1.580299, 2.054367, 3.003459",\ + "1.617915, 1.865734, 2.148256, 2.623672, 3.575470",\ + "0.771264, 1.026907, 1.307016, 1.778803, 2.723340",\ + "0.818366, 1.074036, 1.354240, 1.826261, 2.771269",\ + "0.905641, 1.161391, 1.441867, 1.914558, 2.860911",\ + "1.131493, 1.387366, 1.668262, 2.141988, 3.090415",\ + "1.698741, 1.954774, 2.236218, 2.711293, 3.662425",\ + "0.828931, 1.092619, 1.371156, 1.842715, 2.786849",\ + "0.876032, 1.139748, 1.418380, 1.890174, 2.834778",\ + "0.963308, 1.227105, 1.506008, 1.978471, 2.924420",\ + "1.189160, 1.453082, 1.732403, 2.205900, 3.153924",\ + "1.756409, 2.020493, 2.300359, 2.775205, 3.725934",\ + "1.160146, 1.458017, 1.723059, 2.192071, 3.132305",\ + "1.207253, 1.505153, 1.770286, 2.239531, 3.180234",\ + "1.294543, 1.592528, 1.857920, 2.327831, 3.269876",\ + "1.520419, 1.818533, 2.084326, 2.555264, 3.499380",\ + "2.087698, 2.385982, 2.652296, 3.124575, 4.071390"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.053872, 0.053951, 0.054623, 0.056651, 0.060707",\ + "0.173260, 0.173205, 0.173015, 0.172544, 0.171603",\ + "0.375444, 0.375315, 0.374890, 0.373861, 0.371802",\ + "0.885479, 0.885459, 0.885341, 0.885032, 0.884415",\ + "2.163055, 2.163084, 2.163257, 2.163712, 2.164621",\ + "0.053872, 0.053952, 0.054629, 0.056651, 0.060707",\ + "0.173260, 0.173205, 0.173013, 0.172544, 0.171603",\ + "0.375444, 0.375314, 0.374887, 0.373861, 0.371802",\ + "0.885479, 0.885459, 0.885340, 0.885032, 0.884415",\ + "2.163055, 2.163084, 2.163259, 2.163712, 2.164621",\ + "0.053873, 0.053953, 0.054629, 0.056651, 0.060707",\ + "0.173260, 0.173204, 0.173013, 0.172544, 0.171603",\ + "0.375443, 0.375312, 0.374887, 0.373861, 0.371802",\ + "0.885479, 0.885458, 0.885340, 0.885032, 0.884415",\ + "2.163055, 2.163085, 2.163259, 2.163712, 2.164621",\ + "0.053873, 0.053954, 0.054629, 0.056651, 0.060707",\ + "0.173259, 0.173203, 0.173013, 0.172544, 0.171603",\ + "0.375443, 0.375310, 0.374887, 0.373861, 0.371802",\ + "0.885479, 0.885458, 0.885340, 0.885032, 0.884415",\ + "2.163055, 2.163086, 2.163259, 2.163712, 2.164621",\ + "0.053888, 0.053973, 0.054650, 0.056659, 0.060707",\ + "0.173249, 0.173190, 0.173008, 0.172542, 0.171603",\ + "0.375418, 0.375279, 0.374876, 0.373857, 0.371802",\ + "0.885478, 0.885451, 0.885337, 0.885031, 0.884415",\ + "2.163055, 2.163095, 2.163263, 2.163714, 2.164621"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.533423, 0.780287, 1.060158, 1.529873, 2.469302",\ + "0.594392, 0.841621, 1.122764, 1.595624, 2.541345",\ + "0.661163, 0.908679, 1.190820, 1.666147, 2.616802",\ + "0.795368, 1.042860, 1.324916, 1.800036, 2.750276",\ + "1.138811, 1.386156, 1.667706, 2.141570, 3.089298",\ + "0.620825, 0.867875, 1.147723, 1.616586, 2.555236",\ + "0.681794, 0.929212, 1.210339, 1.682338, 2.627278",\ + "0.748566, 0.996272, 1.278403, 1.752861, 2.702736",\ + "0.882770, 1.130452, 1.412499, 1.886750, 2.836210",\ + "1.226213, 1.473748, 1.755284, 2.228283, 3.175232",\ + "0.701650, 0.956905, 1.235686, 1.704207, 2.642191",\ + "0.762619, 1.018247, 1.298302, 1.769958, 2.714233",\ + "0.829392, 1.085311, 1.366366, 1.840481, 2.789691",\ + "0.963596, 1.219491, 1.500462, 1.974370, 2.923165",\ + "1.307039, 1.562785, 1.843247, 2.315904, 3.262187",\ + "0.759315, 1.022609, 1.299826, 1.768119, 2.705700",\ + "0.820286, 1.083958, 1.362442, 1.833871, 2.777742",\ + "0.887059, 1.151028, 1.430506, 1.904394, 2.853200",\ + "1.021263, 1.285207, 1.564602, 2.038283, 2.986674",\ + "1.364706, 1.628498, 1.907387, 2.379816, 3.325696",\ + "1.090457, 1.387917, 1.651696, 2.117462, 3.051156",\ + "1.151498, 1.449352, 1.714345, 2.183227, 3.123199",\ + "1.218327, 1.516490, 1.782434, 2.253760, 3.198656",\ + "1.352526, 1.650664, 1.916528, 2.387648, 3.332130",\ + "1.695940, 1.993920, 2.259300, 2.729176, 3.671152"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.071642, 0.072195, 0.074119, 0.078878, 0.088395",\ + "0.129738, 0.130488, 0.133096, 0.139547, 0.152449",\ + "0.214072, 0.214757, 0.217138, 0.223027, 0.234806",\ + "0.447096, 0.447173, 0.447439, 0.448098, 0.449416",\ + "1.100692, 1.100656, 1.100533, 1.100228, 1.099618",\ + "0.071642, 0.072199, 0.074134, 0.078878, 0.088395",\ + "0.129738, 0.130493, 0.133116, 0.139547, 0.152449",\ + "0.214072, 0.214761, 0.217156, 0.223027, 0.234806",\ + "0.447096, 0.447173, 0.447441, 0.448098, 0.449416",\ + "1.100692, 1.100656, 1.100532, 1.100228, 1.099618",\ + "0.071643, 0.072206, 0.074135, 0.078878, 0.088395",\ + "0.129740, 0.130503, 0.133117, 0.139547, 0.152449",\ + "0.214073, 0.214770, 0.217157, 0.223027, 0.234806",\ + "0.447096, 0.447174, 0.447441, 0.448098, 0.449416",\ + "1.100692, 1.100656, 1.100532, 1.100228, 1.099618",\ + "0.071645, 0.072218, 0.074135, 0.078878, 0.088395",\ + "0.129742, 0.130518, 0.133118, 0.139547, 0.152449",\ + "0.214076, 0.214784, 0.217158, 0.223027, 0.234806",\ + "0.447096, 0.447176, 0.447441, 0.448098, 0.449416",\ + "1.100692, 1.100655, 1.100532, 1.100228, 1.099618",\ + "0.071752, 0.072348, 0.074184, 0.078897, 0.088395",\ + "0.129887, 0.130696, 0.133183, 0.139574, 0.152449",\ + "0.214208, 0.214946, 0.217217, 0.223052, 0.234806",\ + "0.447111, 0.447194, 0.447448, 0.448101, 0.449416",\ + "1.100685, 1.100646, 1.100529, 1.100227, 1.099618"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2280*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.240088, 0.510351, 0.797290, 1.285614, 2.262263",\ + "0.291602, 0.560872, 0.847259, 1.336249, 2.314227",\ + "0.366122, 0.638120, 0.923420, 1.410996, 2.386150",\ + "0.571697, 0.846754, 1.130217, 1.614147, 2.582006",\ + "1.124964, 1.399896, 1.682080, 2.162757, 3.124112",\ + "0.327497, 0.597936, 0.884917, 1.372329, 2.348197",\ + "0.379011, 0.648452, 0.934889, 1.422963, 2.400161",\ + "0.453531, 0.725696, 1.011044, 1.497711, 2.472083",\ + "0.660133, 0.934325, 1.217830, 1.700861, 2.667939",\ + "1.213404, 1.487464, 1.769683, 2.249471, 3.210046",\ + "0.411710, 0.686989, 0.972882, 1.459950, 2.435152",\ + "0.462735, 0.737494, 1.022853, 1.510585, 2.487116",\ + "0.540482, 0.814729, 1.099009, 1.585332, 2.559038",\ + "0.749582, 1.023346, 1.305795, 1.788483, 2.754894",\ + "1.302860, 1.576480, 1.857647, 2.337093, 3.297001",\ + "0.475438, 0.752729, 1.037025, 1.523864, 2.498661",\ + "0.526464, 0.803218, 1.086996, 1.574498, 2.550625",\ + "0.604208, 0.880438, 1.163152, 1.649246, 2.622547",\ + "0.813313, 1.089039, 1.369937, 1.852396, 2.818403",\ + "1.366598, 1.642166, 1.921789, 2.401006, 3.360510",\ + "0.812369, 1.118362, 1.389087, 1.873289, 2.844117",\ + "0.863397, 1.168668, 1.439066, 1.923926, 2.896081",\ + "0.941125, 1.245720, 1.515207, 1.998668, 2.968004",\ + "1.150264, 1.454128, 1.721955, 2.201803, 3.163859",\ + "1.703596, 2.007172, 2.273774, 2.750400, 3.705966"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.247846, 0.302431, 0.404057, 0.594296, 0.974773",\ + "0.313758, 0.345633, 0.434590, 0.626480, 1.010259",\ + "0.435716, 0.458123, 0.529642, 0.703929, 1.052501",\ + "0.888071, 0.889365, 0.917551, 1.014829, 1.209385",\ + "2.165074, 2.165320, 2.171775, 2.192811, 2.234884",\ + "0.247846, 0.302730, 0.404657, 0.594296, 0.974773",\ + "0.313758, 0.345847, 0.435195, 0.626480, 1.010259",\ + "0.435716, 0.458259, 0.530192, 0.703929, 1.052501",\ + "0.888105, 0.889365, 0.917858, 1.014829, 1.209385",\ + "2.165074, 2.165323, 2.171841, 2.192811, 2.234884",\ + "0.250151, 0.303407, 0.404668, 0.594296, 0.974773",\ + "0.314673, 0.346332, 0.435207, 0.626480, 1.010259",\ + "0.436528, 0.458564, 0.530202, 0.703929, 1.052501",\ + "0.888203, 0.889365, 0.917863, 1.014829, 1.209385",\ + "2.165074, 2.165328, 2.171843, 2.192811, 2.234884",\ + "0.251745, 0.304389, 0.404700, 0.594296, 0.974773",\ + "0.315306, 0.347037, 0.435239, 0.626480, 1.010259",\ + "0.437090, 0.459008, 0.530231, 0.703929, 1.052501",\ + "0.888293, 0.889365, 0.917880, 1.014829, 1.209385",\ + "2.165074, 2.165335, 2.171846, 2.192811, 2.234884",\ + "0.261887, 0.315894, 0.406630, 0.595083, 0.974773",\ + "0.319332, 0.355290, 0.437185, 0.627274, 1.010259",\ + "0.440663, 0.464208, 0.531999, 0.704650, 1.052501",\ + "0.888871, 0.889365, 0.918867, 1.015232, 1.209385",\ + "2.165074, 2.165424, 2.172060, 2.192898, 2.234884"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.240635, 0.424668, 0.712248, 1.199722, 2.174669",\ + "0.275706, 0.462604, 0.757879, 1.262184, 2.270793",\ + "0.326245, 0.516372, 0.817019, 1.338091, 2.380235",\ + "0.455748, 0.646142, 0.952035, 1.495042, 2.581054",\ + "0.793588, 0.988001, 1.296787, 1.858775, 2.982751",\ + "0.328044, 0.512258, 0.799873, 1.286436, 2.260602",\ + "0.363115, 0.550213, 0.845556, 1.348898, 2.356727",\ + "0.413654, 0.603984, 0.904750, 1.424805, 2.466169",\ + "0.543157, 0.733746, 1.039835, 1.581756, 2.666988",\ + "0.880997, 1.075589, 1.384646, 1.945489, 3.068685",\ + "0.408911, 0.601324, 0.887837, 1.374058, 2.347558",\ + "0.443982, 0.639320, 0.933522, 1.436520, 2.443682",\ + "0.494519, 0.693099, 0.992716, 1.512427, 2.553124",\ + "0.624023, 0.822845, 1.127803, 1.669378, 2.753943",\ + "0.961862, 1.164649, 1.472615, 2.033111, 3.155640",\ + "0.466595, 0.667083, 0.951980, 1.437971, 2.411067",\ + "0.501666, 0.705138, 0.997668, 1.500433, 2.507191",\ + "0.552202, 0.758927, 1.056865, 1.576340, 2.616633",\ + "0.681705, 0.888650, 1.191955, 1.733291, 2.817452",\ + "1.019543, 1.230399, 1.536770, 2.097024, 3.219149",\ + "0.769432, 1.032936, 1.304034, 1.787393, 2.756523",\ + "0.804503, 1.071688, 1.349892, 1.849925, 2.852647",\ + "0.855021, 1.125605, 1.409260, 1.925902, 2.962089",\ + "0.984519, 1.255053, 1.544572, 2.082943, 3.162908",\ + "1.322350, 1.596157, 1.889580, 2.446754, 3.564605"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.078325, 0.113595, 0.189416, 0.342002, 0.647174",\ + "0.120997, 0.134862, 0.194741, 0.345549, 0.647167",\ + "0.210707, 0.216021, 0.258625, 0.388109, 0.647078",\ + "0.448759, 0.449630, 0.471236, 0.541414, 0.681771",\ + "1.101439, 1.102394, 1.113437, 1.151551, 1.227780",\ + "0.078325, 0.113799, 0.189898, 0.342002, 0.647174",\ + "0.120997, 0.134966, 0.195216, 0.345549, 0.647167",\ + "0.210707, 0.216054, 0.259033, 0.388109, 0.647078",\ + "0.448759, 0.449638, 0.471457, 0.541414, 0.681771",\ + "1.101439, 1.102394, 1.113557, 1.151551, 1.227780",\ + "0.078410, 0.114258, 0.189906, 0.342002, 0.647174",\ + "0.121014, 0.135201, 0.195225, 0.345549, 0.647167",\ + "0.210718, 0.216128, 0.259041, 0.388109, 0.647078",\ + "0.448759, 0.449657, 0.471461, 0.541414, 0.681771",\ + "1.101445, 1.102394, 1.113560, 1.151551, 1.227780",\ + "0.078573, 0.114926, 0.189932, 0.342002, 0.647174",\ + "0.121047, 0.135543, 0.195250, 0.345549, 0.647167",\ + "0.210740, 0.216235, 0.259062, 0.388109, 0.647078",\ + "0.448759, 0.449684, 0.471473, 0.541414, 0.681771",\ + "1.101456, 1.102394, 1.113566, 1.151551, 1.227780",\ + "0.080054, 0.122746, 0.191480, 0.342634, 0.647174",\ + "0.121349, 0.139547, 0.196780, 0.346174, 0.647167",\ + "0.210939, 0.217494, 0.260376, 0.388645, 0.647078",\ + "0.448759, 0.449998, 0.472185, 0.541705, 0.681771",\ + "1.101560, 1.102394, 1.113953, 1.151709, 1.227780"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2359*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.197425, 0.431841, 0.691115, 1.132558, 2.015443",\ + "0.256864, 0.482200, 0.742850, 1.186401, 2.073503",\ + "0.340685, 0.558516, 0.820189, 1.263949, 2.151470",\ + "0.552702, 0.766228, 1.030335, 1.473577, 2.360062",\ + "1.106653, 1.318570, 1.585965, 2.032625, 2.925946",\ + "0.284828, 0.519347, 0.778592, 1.219271, 2.101377",\ + "0.344267, 0.569712, 0.830334, 1.273115, 2.159437",\ + "0.428088, 0.646034, 0.907673, 1.350662, 2.237404",\ + "0.640105, 0.853764, 1.117818, 1.560291, 2.445995",\ + "1.194056, 1.406120, 1.673459, 2.119339, 3.011880",\ + "0.365631, 0.608197, 0.866553, 1.306892, 2.188332",\ + "0.425081, 0.658572, 0.918295, 1.360735, 2.246392",\ + "0.508910, 0.734909, 0.995634, 1.438283, 2.324359",\ + "0.720937, 0.942676, 1.205779, 1.647911, 2.532950",\ + "1.274892, 1.495066, 1.761420, 2.206959, 3.098835",\ + "0.423252, 0.673639, 0.930688, 1.370805, 2.251841",\ + "0.482725, 0.724031, 0.982430, 1.424648, 2.309901",\ + "0.566569, 0.800388, 1.059769, 1.502196, 2.387868",\ + "0.778616, 1.008210, 1.269914, 1.711824, 2.596459",\ + "1.332580, 1.560649, 1.825555, 2.270872, 3.162344",\ + "0.752151, 1.035876, 1.282272, 1.720031, 2.597297",\ + "0.801570, 1.086457, 1.334035, 1.773883, 2.655357",\ + "0.877150, 1.163054, 1.411376, 1.851432, 2.733324",\ + "1.083205, 1.371523, 1.621516, 2.061058, 2.941916",\ + "1.635753, 1.924533, 2.177192, 2.620120, 3.507800"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.177313, 0.213491, 0.303378, 0.457569, 0.765950",\ + "0.250045, 0.279673, 0.356803, 0.520196, 0.846983",\ + "0.414565, 0.415724, 0.459633, 0.603345, 0.890769",\ + "0.887843, 0.887860, 0.923876, 1.046142, 1.290675",\ + "2.163223, 2.163223, 2.177277, 2.225018, 2.320500",\ + "0.177313, 0.213790, 0.303862, 0.457569, 0.765950",\ + "0.250045, 0.279868, 0.357315, 0.520196, 0.846983",\ + "0.414565, 0.415735, 0.460084, 0.603345, 0.890769",\ + "0.887843, 0.887860, 0.924259, 1.046142, 1.290675",\ + "2.163223, 2.163223, 2.177427, 2.225018, 2.320500",\ + "0.177336, 0.214442, 0.303871, 0.457569, 0.765950",\ + "0.250094, 0.280294, 0.357324, 0.520196, 0.846983",\ + "0.414565, 0.415758, 0.460092, 0.603345, 0.890769",\ + "0.887843, 0.887860, 0.924267, 1.046142, 1.290675",\ + "2.163223, 2.163223, 2.177430, 2.225018, 2.320500",\ + "0.177382, 0.215390, 0.303897, 0.457569, 0.765950",\ + "0.250194, 0.280912, 0.357352, 0.520196, 0.846983",\ + "0.414565, 0.415792, 0.460117, 0.603345, 0.890769",\ + "0.887843, 0.887860, 0.924288, 1.046142, 1.290675",\ + "2.163223, 2.163223, 2.177438, 2.225018, 2.320500",\ + "0.179822, 0.226518, 0.305460, 0.458204, 0.765950",\ + "0.255479, 0.288172, 0.359009, 0.520869, 0.846983",\ + "0.414565, 0.416193, 0.461574, 0.603937, 0.890769",\ + "0.887843, 0.887866, 0.925527, 1.046646, 1.290675",\ + "2.163223, 2.163223, 2.177922, 2.225215, 2.320500"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.186404, 0.372214, 0.626375, 1.055893, 1.914929",\ + "0.215796, 0.420104, 0.691914, 1.154775, 2.080498",\ + "0.262340, 0.480772, 0.763179, 1.249218, 2.221297",\ + "0.391105, 0.611507, 0.905161, 1.430325, 2.480653",\ + "0.735355, 0.947201, 1.248974, 1.808736, 2.928262",\ + "0.273807, 0.459710, 0.713814, 1.142606, 2.000863",\ + "0.303199, 0.507653, 0.779458, 1.241489, 2.166432",\ + "0.349742, 0.568345, 0.850795, 1.335931, 2.307231",\ + "0.478508, 0.699079, 0.992901, 1.517038, 2.566586",\ + "0.822757, 1.034759, 1.336822, 1.895450, 3.014196",\ + "0.354668, 0.548536, 0.801774, 1.230227, 2.087818",\ + "0.384060, 0.596593, 0.867420, 1.329109, 2.253387",\ + "0.430602, 0.657342, 0.938759, 1.423552, 2.394186",\ + "0.559360, 0.788071, 1.080866, 1.604659, 2.653542",\ + "0.903600, 1.123721, 1.424789, 1.983071, 3.101151",\ + "0.412406, 0.613944, 0.865907, 1.294139, 2.151327",\ + "0.441797, 0.662169, 0.931558, 1.393022, 2.316896",\ + "0.488337, 0.722997, 1.002901, 1.487465, 2.457695",\ + "0.617079, 0.853721, 1.145016, 1.668572, 2.717051",\ + "0.961302, 1.189327, 1.488945, 2.046983, 3.164660",\ + "0.716048, 0.975780, 1.217370, 1.643317, 2.496783",\ + "0.745435, 1.025964, 1.283359, 1.742337, 2.662352",\ + "0.795621, 1.087736, 1.354937, 1.836875, 2.803151",\ + "0.926531, 1.218392, 1.497448, 2.018143, 3.062507",\ + "1.264602, 1.553481, 1.841728, 2.396697, 3.510116"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.071183, 0.106867, 0.175274, 0.296411, 0.538686",\ + "0.120882, 0.144922, 0.213025, 0.350085, 0.624205",\ + "0.200934, 0.210784, 0.256174, 0.378831, 0.624145",\ + "0.444933, 0.444933, 0.478341, 0.591820, 0.818777",\ + "1.101084, 1.102468, 1.122484, 1.190474, 1.326455",\ + "0.071183, 0.107086, 0.175654, 0.296411, 0.538686",\ + "0.120882, 0.145109, 0.213454, 0.350085, 0.624205",\ + "0.200934, 0.210847, 0.256559, 0.378831, 0.624145",\ + "0.444933, 0.444933, 0.478697, 0.591820, 0.818777",\ + "1.101084, 1.102468, 1.122697, 1.190474, 1.326455",\ + "0.071251, 0.107567, 0.175661, 0.296411, 0.538686",\ + "0.120905, 0.145516, 0.213462, 0.350085, 0.624205",\ + "0.200952, 0.210983, 0.256566, 0.378831, 0.624145",\ + "0.444933, 0.444933, 0.478703, 0.591820, 0.818777",\ + "1.101092, 1.102468, 1.122701, 1.190474, 1.326455",\ + "0.071390, 0.108264, 0.175682, 0.296411, 0.538686",\ + "0.120951, 0.146107, 0.213486, 0.350085, 0.624205",\ + "0.200988, 0.211181, 0.256587, 0.378831, 0.624145",\ + "0.444933, 0.444933, 0.478723, 0.591820, 0.818777",\ + "1.101108, 1.102468, 1.122713, 1.190474, 1.326455",\ + "0.072681, 0.116454, 0.176910, 0.296910, 0.538686",\ + "0.121377, 0.153048, 0.214875, 0.350649, 0.624205",\ + "0.202909, 0.213502, 0.257831, 0.379336, 0.624145",\ + "0.444933, 0.444933, 0.479873, 0.592287, 0.818777",\ + "1.101257, 1.102468, 1.123402, 1.190754, 1.326455"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2411*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.553758, 0.808668, 1.064878, 1.505326, 2.386221",\ + "0.599911, 0.854821, 1.111032, 1.551482, 2.432382",\ + "0.684215, 0.939125, 1.195335, 1.635783, 2.516678",\ + "0.905378, 1.160288, 1.416497, 1.856937, 2.737819",\ + "1.466255, 1.721165, 1.977368, 2.417791, 3.298636",\ + "0.641291, 0.896159, 1.152351, 1.592039, 2.472155",\ + "0.687444, 0.942312, 1.198505, 1.638195, 2.518316",\ + "0.771748, 1.026616, 1.282809, 1.722496, 2.602612",\ + "0.992912, 1.247780, 1.503970, 1.943650, 2.823752",\ + "1.553789, 1.808657, 2.064841, 2.504504, 3.384570",\ + "0.730669, 0.984969, 1.240312, 1.679659, 2.559110",\ + "0.776822, 1.031122, 1.286465, 1.725815, 2.605271",\ + "0.861126, 1.115426, 1.370769, 1.810116, 2.689567",\ + "1.082289, 1.336589, 1.591930, 2.031271, 2.910707",\ + "1.643166, 1.897466, 2.152802, 2.592124, 3.471525",\ + "0.794611, 1.050352, 1.304446, 1.743572, 2.622619",\ + "0.840764, 1.096505, 1.350600, 1.789728, 2.668780",\ + "0.925068, 1.180809, 1.434903, 1.874029, 2.753076",\ + "1.146232, 1.401973, 1.656065, 2.095183, 2.974216",\ + "1.707109, 1.962849, 2.216936, 2.656037, 3.535034",\ + "1.132859, 1.411925, 1.656019, 2.092792, 2.968075",\ + "1.179013, 1.458078, 1.702173, 2.138948, 3.014236",\ + "1.263317, 1.542382, 1.786476, 2.223249, 3.098532",\ + "1.484480, 1.763546, 2.007637, 2.444404, 3.319673",\ + "2.045357, 2.324422, 2.568509, 3.005257, 3.880490"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\ + "0.380998, 0.380998, 0.381005, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\ + "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\ + "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\ + "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\ + "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\ + "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176984, 0.177041, 0.177156",\ + "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330",\ + "0.051937, 0.051937, 0.051947, 0.051981, 0.052048",\ + "0.176967, 0.176967, 0.176985, 0.177042, 0.177156",\ + "0.380998, 0.380998, 0.381006, 0.381032, 0.381085",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885971",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162330"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.540267, 0.795177, 1.050726, 1.488938, 2.365363",\ + "0.562618, 0.817528, 1.073077, 1.511289, 2.387713",\ + "0.603939, 0.858848, 1.114838, 1.554540, 2.433944",\ + "0.736907, 0.991817, 1.248027, 1.688475, 2.569372",\ + "1.086012, 1.340922, 1.597135, 2.037591, 2.918504",\ + "0.627801, 0.882669, 1.138192, 1.575651, 2.451297",\ + "0.650152, 0.905020, 1.160543, 1.598002, 2.473647",\ + "0.691472, 0.946340, 1.202309, 1.641253, 2.519878",\ + "0.824440, 1.079308, 1.335500, 1.775188, 2.655306",\ + "1.173546, 1.428414, 1.684608, 2.124305, 3.004438",\ + "0.717178, 0.971478, 1.226152, 1.663272, 2.538252",\ + "0.739529, 0.993829, 1.248503, 1.685622, 2.560602",\ + "0.780849, 1.035149, 1.290269, 1.728874, 2.606833",\ + "0.913818, 1.168118, 1.423461, 1.862809, 2.742261",\ + "1.262923, 1.517223, 1.772569, 2.211925, 3.091393",\ + "0.781121, 1.036862, 1.290286, 1.727184, 2.601761",\ + "0.803471, 1.059212, 1.312637, 1.749535, 2.624111",\ + "0.844792, 1.100533, 1.354404, 1.792786, 2.670342",\ + "0.977760, 1.233501, 1.487595, 1.926721, 2.805770",\ + "1.326866, 1.582607, 1.836703, 2.275837, 3.154902",\ + "1.119369, 1.398434, 1.641836, 2.076395, 2.947217",\ + "1.141720, 1.420785, 1.664187, 2.098746, 2.969567",\ + "1.183040, 1.462106, 1.705969, 2.142004, 3.015798",\ + "1.316008, 1.595074, 1.839168, 2.275942, 3.151226",\ + "1.665114, 1.944180, 2.188276, 2.625058, 3.500358"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\ + "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\ + "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\ + "0.048201, 0.048201, 0.048170, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098587, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794",\ + "0.048201, 0.048201, 0.048169, 0.048066, 0.047859",\ + "0.098620, 0.098620, 0.098586, 0.098478, 0.098260",\ + "0.188783, 0.188783, 0.188784, 0.188790, 0.188801",\ + "0.444126, 0.444126, 0.444125, 0.444121, 0.444113",\ + "1.101816, 1.101816, 1.101814, 1.101807, 1.101794"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2563*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.525875, 0.768087, 1.036195, 1.520933, 2.490408",\ + "0.572028, 0.814241, 1.082351, 1.567096, 2.536584",\ + "0.656332, 0.898544, 1.166652, 1.651390, 2.620866",\ + "0.877495, 1.119706, 1.387806, 1.872524, 2.841960",\ + "1.438372, 1.680579, 1.948659, 2.433326, 3.402659",\ + "0.613284, 0.855558, 1.123811, 1.607647, 2.576342",\ + "0.659437, 0.901712, 1.169967, 1.653810, 2.622518",\ + "0.743741, 0.986015, 1.254268, 1.738104, 2.706800",\ + "0.964904, 1.207177, 1.475422, 1.959238, 2.927894",\ + "1.525780, 1.768050, 2.036275, 2.520041, 3.488593",\ + "0.694098, 0.944352, 1.211775, 1.695269, 2.663297",\ + "0.740251, 0.990506, 1.257931, 1.741431, 2.709473",\ + "0.824555, 1.074809, 1.342232, 1.825726, 2.793755",\ + "1.045718, 1.295971, 1.563386, 2.046860, 3.014849",\ + "1.606595, 1.856844, 2.124239, 2.607662, 3.575548",\ + "0.752011, 1.009716, 1.275917, 1.759182, 2.726806",\ + "0.798164, 1.055869, 1.322073, 1.805345, 2.772982",\ + "0.882468, 1.140173, 1.406374, 1.889639, 2.857264",\ + "1.103631, 1.361335, 1.627528, 2.110773, 3.078358",\ + "1.664508, 1.922208, 2.188382, 2.671575, 3.639057",\ + "1.085549, 1.370949, 1.627944, 2.108593, 3.072262",\ + "1.131702, 1.417103, 1.674100, 2.154755, 3.118438",\ + "1.216006, 1.501406, 1.758401, 2.239050, 3.202720",\ + "1.437170, 1.722567, 1.979555, 2.460184, 3.423814",\ + "1.998046, 2.283439, 2.540407, 3.020985, 3.984513"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.051938, 0.051944, 0.051982, 0.052078, 0.052272",\ + "0.176969, 0.176980, 0.177043, 0.177207, 0.177534",\ + "0.380998, 0.381003, 0.381033, 0.381108, 0.381260",\ + "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051938, 0.051944, 0.051982, 0.052078, 0.052272",\ + "0.176969, 0.176980, 0.177044, 0.177207, 0.177534",\ + "0.380998, 0.381004, 0.381033, 0.381108, 0.381260",\ + "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051938, 0.051945, 0.051982, 0.052078, 0.052272",\ + "0.176969, 0.176980, 0.177044, 0.177207, 0.177534",\ + "0.380998, 0.381004, 0.381033, 0.381108, 0.381260",\ + "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051938, 0.051945, 0.051982, 0.052078, 0.052272",\ + "0.176969, 0.176981, 0.177044, 0.177207, 0.177534",\ + "0.380998, 0.381004, 0.381033, 0.381108, 0.381260",\ + "0.885971, 0.885971, 0.885971, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051938, 0.051947, 0.051983, 0.052079, 0.052272",\ + "0.176969, 0.176984, 0.177045, 0.177208, 0.177534",\ + "0.380998, 0.381006, 0.381034, 0.381109, 0.381260",\ + "0.885971, 0.885971, 0.885972, 0.885974, 0.885979",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.512519, 0.754762, 1.019445, 1.492217, 2.437761",\ + "0.534869, 0.777112, 1.043739, 1.523217, 2.482171",\ + "0.576190, 0.818433, 1.086345, 1.570253, 2.538069",\ + "0.709024, 0.951236, 1.219345, 1.704084, 2.673563",\ + "1.058130, 1.300344, 1.568461, 2.053223, 3.022748",\ + "0.599927, 0.842233, 1.107023, 1.578931, 2.523695",\ + "0.622278, 0.864583, 1.131338, 1.609931, 2.568105",\ + "0.663599, 0.905904, 1.173958, 1.656967, 2.624003",\ + "0.796432, 1.038707, 1.306960, 1.790798, 2.759497",\ + "1.145538, 1.387814, 1.656077, 2.139938, 3.108682",\ + "0.680742, 0.931028, 1.194987, 1.666553, 2.610650",\ + "0.703093, 0.953378, 1.219303, 1.697553, 2.655060",\ + "0.744413, 0.994699, 1.261922, 1.744589, 2.710958",\ + "0.877247, 1.127501, 1.394925, 1.878420, 2.846452",\ + "1.226353, 1.476609, 1.744041, 2.227559, 3.195637",\ + "0.738655, 0.996392, 1.259127, 1.730466, 2.674159",\ + "0.761006, 1.018743, 1.283444, 1.761466, 2.718569",\ + "0.802326, 1.060063, 1.326064, 1.808502, 2.774467",\ + "0.935160, 1.192865, 1.459067, 1.942333, 2.909961",\ + "1.284266, 1.541972, 1.808183, 2.291472, 3.259146",\ + "1.072193, 1.357636, 1.611032, 2.079827, 3.019615",\ + "1.094544, 1.379987, 1.635417, 2.110855, 3.064025",\ + "1.135864, 1.421307, 1.678082, 2.157909, 3.119923",\ + "1.268698, 1.554098, 1.811093, 2.291744, 3.255417",\ + "1.617804, 1.903206, 2.160210, 2.640883, 3.604602"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.048198, 0.048178, 0.048063, 0.047766, 0.047172",\ + "0.098616, 0.098596, 0.098475, 0.098162, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\ + "0.048198, 0.048178, 0.048062, 0.047766, 0.047172",\ + "0.098616, 0.098596, 0.098474, 0.098162, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\ + "0.048198, 0.048177, 0.048062, 0.047766, 0.047172",\ + "0.098616, 0.098595, 0.098474, 0.098162, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\ + "0.048198, 0.048177, 0.048062, 0.047766, 0.047172",\ + "0.098616, 0.098594, 0.098474, 0.098162, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750",\ + "0.048198, 0.048170, 0.048059, 0.047765, 0.047172",\ + "0.098616, 0.098587, 0.098471, 0.098161, 0.097537",\ + "0.188783, 0.188784, 0.188790, 0.188806, 0.188837",\ + "0.444126, 0.444125, 0.444121, 0.444109, 0.444085",\ + "1.101815, 1.101814, 1.101807, 1.101788, 1.101750"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.659689, 0.901731, 1.166165, 1.640730, 2.589860",\ + "0.706217, 0.948259, 1.212695, 1.687267, 2.636411",\ + "0.791853, 1.033895, 1.298337, 1.772929, 2.722115",\ + "1.015175, 1.257217, 1.521667, 1.996292, 2.945540",\ + "1.579124, 1.821166, 2.085628, 2.560294, 3.509625",\ + "0.747090, 0.989208, 1.253745, 1.727443, 2.675794",\ + "0.793618, 1.035736, 1.300275, 1.773980, 2.722345",\ + "0.879254, 1.121372, 1.385917, 1.859643, 2.808049",\ + "1.102576, 1.344694, 1.609248, 2.083005, 3.031474",\ + "1.666525, 1.908643, 2.173209, 2.647007, 3.595559",\ + "0.827897, 1.077990, 1.341708, 1.815064, 2.762749",\ + "0.874425, 1.124518, 1.388238, 1.861601, 2.809300",\ + "0.960061, 1.210154, 1.473880, 1.947263, 2.895004",\ + "1.183383, 1.433476, 1.697210, 2.170625, 3.118429",\ + "1.747332, 1.997425, 2.261171, 2.734627, 3.682514",\ + "0.888137, 1.143334, 1.405848, 1.878976, 2.826258",\ + "0.934665, 1.189862, 1.452378, 1.925513, 2.872809",\ + "1.020301, 1.275498, 1.538020, 2.011176, 2.958513",\ + "1.243623, 1.498820, 1.761351, 2.234538, 3.181938",\ + "1.807572, 2.062769, 2.325312, 2.798540, 3.746023",\ + "1.226031, 1.504429, 1.757767, 2.228338, 3.171714",\ + "1.272558, 1.550957, 1.804297, 2.274875, 3.218265",\ + "1.358195, 1.636593, 1.889939, 2.360538, 3.303969",\ + "1.581517, 1.859915, 2.113271, 2.583900, 3.527394",\ + "2.145466, 2.423864, 2.677232, 3.147902, 4.091479"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\ + "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\ + "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\ + "0.052222, 0.052222, 0.052228, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045",\ + "0.052222, 0.052222, 0.052229, 0.052249, 0.052290",\ + "0.174407, 0.174407, 0.174407, 0.174407, 0.174407",\ + "0.378141, 0.378141, 0.378141, 0.378141, 0.378141",\ + "0.885509, 0.885509, 0.885509, 0.885509, 0.885509",\ + "2.163010, 2.163011, 2.163015, 2.163025, 2.163045"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.598065, 0.840108, 1.104513, 1.578978, 2.527908",\ + "0.651364, 0.893406, 1.157839, 1.632400, 2.581522",\ + "0.712119, 0.954162, 1.218616, 1.693252, 2.642524",\ + "0.846830, 1.088872, 1.353324, 1.827954, 2.777214",\ + "1.193335, 1.435377, 1.699819, 2.174410, 3.123593",\ + "0.685466, 0.927585, 1.192093, 1.665691, 2.613842",\ + "0.738765, 0.980883, 1.245419, 1.719113, 2.667456",\ + "0.799521, 1.041639, 1.306196, 1.779965, 2.728458",\ + "0.934231, 1.176349, 1.440905, 1.914667, 2.863148",\ + "1.280736, 1.522854, 1.787399, 2.261123, 3.209527",\ + "0.766273, 1.016367, 1.280056, 1.753312, 2.700797",\ + "0.819572, 1.069665, 1.333382, 1.806733, 2.754411",\ + "0.880328, 1.130420, 1.394158, 1.867585, 2.815413",\ + "1.015038, 1.265131, 1.528867, 2.002288, 2.950103",\ + "1.361543, 1.611636, 1.875361, 2.348744, 3.296482",\ + "0.826513, 1.081711, 1.344196, 1.817225, 2.764306",\ + "0.879812, 1.135009, 1.397522, 1.870646, 2.817920",\ + "0.940568, 1.195765, 1.458299, 1.931498, 2.878922",\ + "1.075278, 1.330475, 1.593008, 2.066200, 3.013612",\ + "1.421783, 1.676980, 1.939502, 2.412656, 3.359991",\ + "1.164407, 1.442806, 1.696114, 2.166586, 3.109762",\ + "1.217705, 1.496104, 1.749441, 2.220008, 3.163376",\ + "1.278461, 1.556859, 1.810219, 2.280860, 3.224378",\ + "1.413172, 1.691570, 1.944927, 2.415563, 3.359068",\ + "1.759677, 2.038075, 2.291421, 2.762018, 3.705447"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.060051, 0.060051, 0.060093, 0.060235, 0.060520",\ + "0.114009, 0.114009, 0.114066, 0.114262, 0.114654",\ + "0.199711, 0.199711, 0.199764, 0.199943, 0.200301",\ + "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\ + "0.060051, 0.060051, 0.060094, 0.060235, 0.060520",\ + "0.114009, 0.114009, 0.114067, 0.114262, 0.114654",\ + "0.199711, 0.199711, 0.199765, 0.199943, 0.200301",\ + "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\ + "0.060051, 0.060051, 0.060094, 0.060235, 0.060520",\ + "0.114009, 0.114009, 0.114067, 0.114262, 0.114654",\ + "0.199711, 0.199711, 0.199765, 0.199943, 0.200301",\ + "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\ + "0.060051, 0.060051, 0.060094, 0.060235, 0.060520",\ + "0.114009, 0.114009, 0.114067, 0.114262, 0.114654",\ + "0.199711, 0.199711, 0.199765, 0.199943, 0.200301",\ + "0.445489, 0.445489, 0.445495, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435",\ + "0.060051, 0.060051, 0.060095, 0.060236, 0.060520",\ + "0.114009, 0.114009, 0.114069, 0.114263, 0.114654",\ + "0.199711, 0.199711, 0.199767, 0.199944, 0.200301",\ + "0.445489, 0.445489, 0.445496, 0.445515, 0.445555",\ + "1.101435, 1.101435, 1.101435, 1.101435, 1.101435"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2315*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.689570, 0.955359, 1.243359, 1.733584, 2.714034",\ + "0.735723, 1.001512, 1.289513, 1.779738, 2.760189",\ + "0.820027, 1.085816, 1.373816, 1.864041, 2.844491",\ + "1.041190, 1.306978, 1.594979, 2.085202, 3.065649",\ + "1.602065, 1.867854, 2.155853, 2.646073, 3.626513",\ + "0.776981, 1.042942, 1.330993, 1.820299, 2.799968",\ + "0.823135, 1.089095, 1.377147, 1.866453, 2.846122",\ + "0.907439, 1.173399, 1.461450, 1.950756, 2.930425",\ + "1.128601, 1.394562, 1.682613, 2.171917, 3.151583",\ + "1.689477, 1.955437, 2.243487, 2.732788, 3.712447",\ + "0.857898, 1.132003, 1.418959, 1.907921, 2.886923",\ + "0.904051, 1.178156, 1.465112, 1.954075, 2.933077",\ + "0.988355, 1.262460, 1.549416, 2.038378, 3.017380",\ + "1.209518, 1.483622, 1.770578, 2.259539, 3.238538",\ + "1.770393, 2.044498, 2.331453, 2.820410, 3.799402",\ + "0.918904, 1.197754, 1.483102, 1.971834, 2.950432",\ + "0.965057, 1.243907, 1.529255, 2.017988, 2.996586",\ + "1.049361, 1.328211, 1.613559, 2.102291, 3.080889",\ + "1.270524, 1.549374, 1.834721, 2.323452, 3.302047",\ + "1.831399, 2.110249, 2.395596, 2.884323, 3.862911",\ + "1.254896, 1.563490, 1.835185, 2.321270, 3.295888",\ + "1.301049, 1.609643, 1.881339, 2.367424, 3.342042",\ + "1.385353, 1.693947, 1.965642, 2.451727, 3.426345",\ + "1.606516, 1.915110, 2.186805, 2.672888, 3.647503",\ + "2.167391, 2.475986, 2.747679, 3.233759, 4.208367"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051942, 0.051949, 0.051962",\ + "0.176972, 0.176972, 0.176976, 0.176987, 0.177010",\ + "0.381000, 0.381000, 0.381002, 0.381007, 0.381017",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.676230, 0.942019, 1.230037, 1.720324, 2.700896",\ + "0.698581, 0.964369, 1.252388, 1.742674, 2.723247",\ + "0.739901, 1.005690, 1.293708, 1.783995, 2.764567",\ + "0.872719, 1.138507, 1.426508, 1.916733, 2.897183",\ + "1.221825, 1.487614, 1.775615, 2.265841, 3.246295",\ + "0.763642, 1.029602, 1.317671, 1.807038, 2.786830",\ + "0.785992, 1.051952, 1.340022, 1.829389, 2.809181",\ + "0.827313, 1.093273, 1.381342, 1.870709, 2.850501",\ + "0.960130, 1.226091, 1.514142, 2.003448, 2.983117",\ + "1.309237, 1.575197, 1.863249, 2.352556, 3.332229",\ + "0.844558, 1.118663, 1.405637, 1.894660, 2.873785",\ + "0.866909, 1.141013, 1.427987, 1.917011, 2.896136",\ + "0.908229, 1.182334, 1.469308, 1.958331, 2.937456",\ + "1.041047, 1.315151, 1.602108, 2.091070, 3.070072",\ + "1.390153, 1.664258, 1.951214, 2.440178, 3.419184",\ + "0.905564, 1.184414, 1.469780, 1.958574, 2.937294",\ + "0.927915, 1.206764, 1.492131, 1.980924, 2.959645",\ + "0.969235, 1.248085, 1.533451, 2.022245, 3.000965",\ + "1.102053, 1.380903, 1.666251, 2.154983, 3.133581",\ + "1.451159, 1.730009, 2.015357, 2.504092, 3.482693",\ + "1.241556, 1.550150, 1.821864, 2.308010, 3.282750",\ + "1.263907, 1.572501, 1.844214, 2.330360, 3.305101",\ + "1.305227, 1.613822, 1.885535, 2.371680, 3.346421",\ + "1.438045, 1.746639, 2.018334, 2.504419, 3.479037",\ + "1.787151, 2.095746, 2.367441, 2.853527, 3.828149"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\ + "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\ + "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\ + "0.048192, 0.048192, 0.048186, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811",\ + "0.048192, 0.048192, 0.048185, 0.048165, 0.048124",\ + "0.098610, 0.098610, 0.098604, 0.098582, 0.098538",\ + "0.188783, 0.188783, 0.188784, 0.188785, 0.188787",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444123",\ + "1.101815, 1.101815, 1.101815, 1.101813, 1.101811"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2360*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.664659, 0.924878, 1.203873, 1.666613, 2.592093",\ + "0.710813, 0.971031, 1.250026, 1.712767, 2.638247",\ + "0.795116, 1.055335, 1.334330, 1.797070, 2.722549",\ + "1.016279, 1.276498, 1.555493, 2.018232, 2.943710",\ + "1.577155, 1.837373, 2.116368, 2.579105, 3.504579",\ + "0.752069, 1.012459, 1.291420, 1.753327, 2.678026",\ + "0.798222, 1.058612, 1.337573, 1.799481, 2.724180",\ + "0.882526, 1.142916, 1.421877, 1.883784, 2.808483",\ + "1.103689, 1.364079, 1.643039, 2.104946, 3.029644",\ + "1.664564, 1.924954, 2.203914, 2.665819, 3.590512",\ + "0.832929, 1.101504, 1.379383, 1.840949, 2.764981",\ + "0.879082, 1.147657, 1.425536, 1.887103, 2.811135",\ + "0.963386, 1.231961, 1.509840, 1.971406, 2.895438",\ + "1.184549, 1.453124, 1.731003, 2.192568, 3.116599",\ + "1.745424, 2.013999, 2.291878, 2.753441, 3.677467",\ + "0.893718, 1.167232, 1.443522, 1.904862, 2.828490",\ + "0.939871, 1.213386, 1.489675, 1.951016, 2.874644",\ + "1.024175, 1.297689, 1.573979, 2.035319, 2.958947",\ + "1.245338, 1.518852, 1.795141, 2.256481, 3.180108",\ + "1.806213, 2.079728, 2.356016, 2.817354, 3.740976",\ + "1.228556, 1.532729, 1.795325, 2.254182, 3.173946",\ + "1.274709, 1.578882, 1.841479, 2.300336, 3.220100",\ + "1.359013, 1.663186, 1.925782, 2.384639, 3.304403",\ + "1.580175, 1.884349, 2.146945, 2.605801, 3.525564",\ + "2.141051, 2.445224, 2.707820, 3.166674, 4.086432"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330",\ + "0.051940, 0.051940, 0.051941, 0.051945, 0.051952",\ + "0.176973, 0.176973, 0.176974, 0.176981, 0.176994",\ + "0.381000, 0.381000, 0.381001, 0.381004, 0.381010",\ + "0.885971, 0.885971, 0.885971, 0.885971, 0.885971",\ + "2.162330, 2.162330, 2.162330, 2.162330, 2.162330"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.651319, 0.911538, 1.190542, 1.653312, 2.578852",\ + "0.673670, 0.933888, 1.212892, 1.675662, 2.601202",\ + "0.714990, 0.975209, 1.254213, 1.716983, 2.642523",\ + "0.847808, 1.108027, 1.387022, 1.849762, 2.775242",\ + "1.196915, 1.457133, 1.736129, 2.198870, 3.124351",\ + "0.738728, 0.999118, 1.278088, 1.740026, 2.664785",\ + "0.761079, 1.021469, 1.300439, 1.762377, 2.687136",\ + "0.802400, 1.062789, 1.341759, 1.803697, 2.728456",\ + "0.935218, 1.195608, 1.474569, 1.936476, 2.861175",\ + "1.284324, 1.544714, 1.823675, 2.285584, 3.210285",\ + "0.819588, 1.088164, 1.366052, 1.827648, 2.751740",\ + "0.841939, 1.110514, 1.388402, 1.849998, 2.774091",\ + "0.883259, 1.151835, 1.429723, 1.891319, 2.815412",\ + "1.016078, 1.284653, 1.562532, 2.024098, 2.948130",\ + "1.365184, 1.633759, 1.911639, 2.373206, 3.297240",\ + "0.880378, 1.153892, 1.430190, 1.891561, 2.815249",\ + "0.902728, 1.176243, 1.452541, 1.913912, 2.837600",\ + "0.944049, 1.217563, 1.493861, 1.955232, 2.878921",\ + "1.076867, 1.350381, 1.626671, 2.088011, 3.011639",\ + "1.425974, 1.699488, 1.975777, 2.437119, 3.360749",\ + "1.215215, 1.519388, 1.781994, 2.240881, 3.160706",\ + "1.237566, 1.541739, 1.804345, 2.263232, 3.183056",\ + "1.278886, 1.583060, 1.845665, 2.304552, 3.224377",\ + "1.411705, 1.715878, 1.978474, 2.437331, 3.357095",\ + "1.760811, 2.064984, 2.327581, 2.786439, 3.706205"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\ + "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\ + "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\ + "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813",\ + "0.048191, 0.048191, 0.048188, 0.048176, 0.048153",\ + "0.098610, 0.098610, 0.098606, 0.098594, 0.098570",\ + "0.188783, 0.188783, 0.188783, 0.188784, 0.188785",\ + "0.444126, 0.444126, 0.444126, 0.444125, 0.444124",\ + "1.101815, 1.101815, 1.101815, 1.101814, 1.101813"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2403*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.748501, 1.009671, 1.301852, 1.810246, 2.827035",\ + "0.794654, 1.055824, 1.348005, 1.856399, 2.873188",\ + "0.878958, 1.140128, 1.432309, 1.940704, 2.957492",\ + "1.100121, 1.361291, 1.653472, 2.161867, 3.178656",\ + "1.660998, 1.922168, 2.214350, 2.722744, 3.739532",\ + "0.835913, 1.097245, 1.389544, 1.896961, 2.912969",\ + "0.882066, 1.143398, 1.435697, 1.943114, 2.959122",\ + "0.966370, 1.227702, 1.520001, 2.027418, 3.043426",\ + "1.187534, 1.448865, 1.741165, 2.248582, 3.264589",\ + "1.748411, 2.009742, 2.302042, 2.809459, 3.825466",\ + "0.916813, 1.186291, 1.477511, 1.984584, 2.999924",\ + "0.962966, 1.232444, 1.523664, 2.030737, 3.046077",\ + "1.047270, 1.316748, 1.607968, 2.115041, 3.130381",\ + "1.268433, 1.537911, 1.829131, 2.336204, 3.351544",\ + "1.829310, 2.098788, 2.390008, 2.897081, 3.912421",\ + "0.976448, 1.252020, 1.541657, 2.048497, 3.063433",\ + "1.022601, 1.298173, 1.587810, 2.094650, 3.109586",\ + "1.106905, 1.382477, 1.672114, 2.178954, 3.193890",\ + "1.328068, 1.603641, 1.893278, 2.400118, 3.415053",\ + "1.888945, 2.164518, 2.454154, 2.960994, 3.975930",\ + "1.310176, 1.617488, 1.893926, 2.398009, 3.408889",\ + "1.356329, 1.663641, 1.940079, 2.444162, 3.455042",\ + "1.440634, 1.747945, 2.024383, 2.528466, 3.539346",\ + "1.661797, 1.969109, 2.245546, 2.749630, 3.760509",\ + "2.222674, 2.529986, 2.806423, 3.310507, 4.321386"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.735004, 0.996174, 1.288355, 1.796750, 2.813539",\ + "0.757355, 1.018525, 1.310706, 1.819101, 2.835889",\ + "0.798676, 1.059846, 1.352027, 1.860421, 2.877210",\ + "0.931650, 1.192820, 1.485001, 1.993395, 3.010184",\ + "1.280755, 1.541925, 1.834106, 2.342501, 3.359290",\ + "0.822417, 1.083748, 1.376048, 1.883465, 2.899472",\ + "0.844768, 1.106099, 1.398399, 1.905816, 2.921823",\ + "0.886088, 1.147419, 1.439719, 1.947136, 2.963144",\ + "1.019062, 1.280394, 1.572693, 2.080110, 3.096118",\ + "1.368168, 1.629499, 1.921799, 2.429216, 3.445223",\ + "0.903316, 1.172794, 1.464014, 1.971087, 2.986427",\ + "0.925667, 1.195145, 1.486365, 1.993438, 3.008778",\ + "0.966988, 1.236465, 1.527686, 2.034758, 3.050099",\ + "1.099962, 1.369439, 1.660660, 2.167732, 3.183073",\ + "1.449067, 1.718545, 2.009765, 2.516838, 3.532178",\ + "0.962951, 1.238524, 1.528160, 2.035001, 3.049936",\ + "0.985302, 1.260875, 1.550511, 2.057351, 3.072287",\ + "1.026623, 1.302195, 1.591832, 2.098672, 3.113608",\ + "1.159597, 1.435169, 1.724806, 2.231646, 3.246582",\ + "1.508702, 1.784275, 2.073912, 2.580752, 3.595687",\ + "1.296680, 1.603992, 1.880429, 2.384513, 3.395392",\ + "1.319031, 1.626343, 1.902780, 2.406864, 3.417743",\ + "1.360351, 1.667663, 1.944100, 2.448184, 3.459064",\ + "1.493325, 1.800637, 2.077075, 2.581158, 3.592038",\ + "1.842431, 2.149743, 2.426180, 2.930264, 3.941144"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2467*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.730463, 0.984563, 1.266812, 1.735637, 2.673288",\ + "0.776616, 1.030716, 1.312965, 1.781790, 2.719441",\ + "0.860920, 1.115021, 1.397269, 1.866094, 2.803746",\ + "1.082084, 1.336184, 1.618432, 2.087258, 3.024909",\ + "1.642961, 1.897061, 2.179309, 2.648135, 3.585786",\ + "0.817871, 1.072157, 1.354377, 1.822352, 2.759222",\ + "0.864024, 1.118310, 1.400530, 1.868505, 2.805375",\ + "0.948328, 1.202614, 1.484834, 1.952809, 2.889679",\ + "1.169492, 1.423777, 1.705998, 2.173972, 3.110843",\ + "1.730369, 1.984654, 2.266875, 2.734849, 3.671720",\ + "0.898712, 1.161224, 1.442341, 1.909973, 2.846177",\ + "0.944865, 1.207377, 1.488494, 1.956126, 2.892330",\ + "1.029169, 1.291681, 1.572798, 2.040430, 2.976635",\ + "1.250332, 1.512845, 1.793961, 2.261594, 3.197798",\ + "1.811209, 2.073722, 2.354838, 2.822471, 3.758675",\ + "0.956353, 1.226984, 1.506480, 1.973886, 2.909686",\ + "1.002506, 1.273137, 1.552633, 2.020039, 2.955839",\ + "1.086810, 1.357441, 1.636937, 2.104343, 3.040143",\ + "1.307973, 1.578604, 1.858101, 2.325507, 3.261307",\ + "1.868850, 2.139482, 2.418978, 2.886384, 3.822184",\ + "1.288825, 1.592869, 1.858345, 2.323230, 3.255142",\ + "1.334978, 1.639022, 1.904498, 2.369383, 3.301295",\ + "1.419282, 1.723326, 1.988802, 2.453687, 3.385599",\ + "1.640445, 1.944490, 2.209965, 2.674851, 3.606763",\ + "2.201322, 2.505367, 2.770842, 3.235728, 4.167640"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331",\ + "0.051937, 0.051937, 0.051937, 0.051937, 0.051937",\ + "0.176967, 0.176967, 0.176967, 0.176967, 0.176967",\ + "0.380998, 0.380998, 0.380998, 0.380998, 0.380998",\ + "0.885970, 0.885970, 0.885970, 0.885970, 0.885970",\ + "2.162331, 2.162331, 2.162331, 2.162331, 2.162331"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.716967, 0.971067, 1.253316, 1.722141, 2.659792",\ + "0.739318, 0.993418, 1.275667, 1.744492, 2.682143",\ + "0.780639, 1.034739, 1.316987, 1.785813, 2.723464",\ + "0.913612, 1.167712, 1.449961, 1.918786, 2.856437",\ + "1.262718, 1.516818, 1.799066, 2.267892, 3.205543",\ + "0.804375, 1.058661, 1.340881, 1.808856, 2.745726",\ + "0.826726, 1.081012, 1.363232, 1.831207, 2.768077",\ + "0.868047, 1.122332, 1.404552, 1.872527, 2.809398",\ + "1.001020, 1.255306, 1.537526, 2.005501, 2.942371",\ + "1.350126, 1.604411, 1.886632, 2.354606, 3.291477",\ + "0.885216, 1.147728, 1.428845, 1.896477, 2.832681",\ + "0.907567, 1.170079, 1.451195, 1.918828, 2.855032",\ + "0.948887, 1.211399, 1.492516, 1.960149, 2.896353",\ + "1.081861, 1.344373, 1.625489, 2.093122, 3.029326",\ + "1.430966, 1.693479, 1.974595, 2.442228, 3.378432",\ + "0.942857, 1.213488, 1.492984, 1.960390, 2.896190",\ + "0.965208, 1.235839, 1.515335, 1.982741, 2.918541",\ + "1.006528, 1.277159, 1.556656, 2.024062, 2.959862",\ + "1.139502, 1.410133, 1.689629, 2.157035, 3.092835",\ + "1.488607, 1.759238, 2.038735, 2.506141, 3.441941",\ + "1.275329, 1.579373, 1.844849, 2.309734, 3.241646",\ + "1.297680, 1.601724, 1.867200, 2.332085, 3.263997",\ + "1.339000, 1.643044, 1.908520, 2.373406, 3.305318",\ + "1.471974, 1.776018, 2.041493, 2.506379, 3.438291",\ + "1.821079, 2.125124, 2.390599, 2.855485, 3.787397"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816",\ + "0.048201, 0.048201, 0.048201, 0.048201, 0.048201",\ + "0.098620, 0.098620, 0.098620, 0.098620, 0.098620",\ + "0.188783, 0.188783, 0.188783, 0.188783, 0.188783",\ + "0.444126, 0.444126, 0.444126, 0.444126, 0.444126",\ + "1.101816, 1.101816, 1.101816, 1.101816, 1.101816"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2517*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.732857, 0.971343, 1.249163, 1.734893, 2.706354",\ + "0.779384, 1.017870, 1.295690, 1.781420, 2.752881",\ + "0.865018, 1.103504, 1.381324, 1.867054, 2.838515",\ + "1.088337, 1.326823, 1.604643, 2.090373, 3.061833",\ + "1.652282, 1.890768, 2.168588, 2.654318, 3.625778",\ + "0.820269, 1.058867, 1.336783, 1.821608, 2.792287",\ + "0.866797, 1.105394, 1.383311, 1.868135, 2.838814",\ + "0.952431, 1.191029, 1.468945, 1.953769, 2.924448",\ + "1.175750, 1.414347, 1.692263, 2.177088, 3.147767",\ + "1.739695, 1.978293, 2.256209, 2.741033, 3.711712",\ + "0.901137, 1.147799, 1.424749, 1.909230, 2.879242",\ + "0.947664, 1.194327, 1.471276, 1.955757, 2.925770",\ + "1.033299, 1.279961, 1.556910, 2.041391, 3.011404",\ + "1.256617, 1.503280, 1.780229, 2.264710, 3.234722",\ + "1.820563, 2.067225, 2.344174, 2.828655, 3.798667",\ + "0.958789, 1.213364, 1.488891, 1.973144, 2.942751",\ + "1.005316, 1.259891, 1.535418, 2.019671, 2.989279",\ + "1.090950, 1.345525, 1.621053, 2.105305, 3.074913",\ + "1.314269, 1.568844, 1.844371, 2.328624, 3.298231",\ + "1.878214, 2.132789, 2.408317, 2.892569, 3.862176",\ + "1.276921, 1.576900, 1.840930, 2.322562, 3.288208",\ + "1.323448, 1.623428, 1.887457, 2.369089, 3.334734",\ + "1.409082, 1.709062, 1.973091, 2.454723, 3.420369",\ + "1.632401, 1.932381, 2.196410, 2.678042, 3.643687",\ + "2.196346, 2.496326, 2.760355, 3.241987, 4.207632"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014",\ + "0.052220, 0.052220, 0.052220, 0.052220, 0.052220",\ + "0.174408, 0.174408, 0.174408, 0.174408, 0.174408",\ + "0.378144, 0.378144, 0.378144, 0.378144, 0.378144",\ + "0.885509, 0.885509, 0.885509, 0.885508, 0.885506",\ + "2.163010, 2.163010, 2.163010, 2.163012, 2.163014"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.671243, 0.909729, 1.187549, 1.673279, 2.644740",\ + "0.724532, 0.963018, 1.240838, 1.726568, 2.698029",\ + "0.785280, 1.023767, 1.301586, 1.787316, 2.758777",\ + "0.919992, 1.158478, 1.436297, 1.922028, 2.893488",\ + "1.266500, 1.504986, 1.782806, 2.268536, 3.239997",\ + "0.758655, 0.997253, 1.275169, 1.759994, 2.730674",\ + "0.811945, 1.050542, 1.328459, 1.813283, 2.783962",\ + "0.872693, 1.111291, 1.389207, 1.874031, 2.844710",\ + "1.007404, 1.246002, 1.523918, 2.008743, 2.979422",\ + "1.353913, 1.592511, 1.870427, 2.355251, 3.325931",\ + "0.839523, 1.086185, 1.363135, 1.847616, 2.817629",\ + "0.892813, 1.139475, 1.416424, 1.900905, 2.870918",\ + "0.953561, 1.200223, 1.477172, 1.961653, 2.931665",\ + "1.088272, 1.334934, 1.611884, 2.096365, 3.066377",\ + "1.434781, 1.681443, 1.958392, 2.442873, 3.412886",\ + "0.897175, 1.151750, 1.427277, 1.911530, 2.881138",\ + "0.950464, 1.205039, 1.480567, 1.964819, 2.934427",\ + "1.011212, 1.265788, 1.541315, 2.025567, 2.995174",\ + "1.145923, 1.400499, 1.676026, 2.160278, 3.129886",\ + "1.492432, 1.747007, 2.022535, 2.506787, 3.476395",\ + "1.215307, 1.515286, 1.779316, 2.260948, 3.226594",\ + "1.268596, 1.568576, 1.832605, 2.314237, 3.279882",\ + "1.329345, 1.629324, 1.893353, 2.374985, 3.340631",\ + "1.464056, 1.764035, 2.028064, 2.509696, 3.475342",\ + "1.810564, 2.110544, 2.374573, 2.856205, 3.821851"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436",\ + "0.060037, 0.060037, 0.060037, 0.060037, 0.060036",\ + "0.113989, 0.113989, 0.113989, 0.113989, 0.113988",\ + "0.199694, 0.199694, 0.199694, 0.199693, 0.199693",\ + "0.445487, 0.445487, 0.445487, 0.445487, 0.445487",\ + "1.101436, 1.101436, 1.101436, 1.101436, 1.101436"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2654*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.687805, 0.938142, 1.214956, 1.708122, 2.694454",\ + "0.734333, 0.984670, 1.261485, 1.754655, 2.740993",\ + "0.819969, 1.070307, 1.347124, 1.840302, 2.826659",\ + "1.043291, 1.293629, 1.570450, 2.063643, 3.050026",\ + "1.607241, 1.857579, 2.134405, 2.627615, 3.614036",\ + "0.775217, 1.025647, 1.302601, 1.794837, 2.780388",\ + "0.821745, 1.072175, 1.349129, 1.841369, 2.826927",\ + "0.907382, 1.157812, 1.434768, 1.927017, 2.912592",\ + "1.130704, 1.381134, 1.658095, 2.150357, 3.135960",\ + "1.694654, 1.945083, 2.222049, 2.714330, 3.699970",\ + "0.856074, 1.114534, 1.390566, 1.882460, 2.867343",\ + "0.902602, 1.161062, 1.437095, 1.928992, 2.913882",\ + "0.988238, 1.246698, 1.522734, 2.014640, 2.999547",\ + "1.211560, 1.470021, 1.746060, 2.237980, 3.222915",\ + "1.775510, 2.033970, 2.310015, 2.801953, 3.786925",\ + "0.913872, 1.180032, 1.454710, 1.946373, 2.930852",\ + "0.960400, 1.226560, 1.501239, 1.992905, 2.977391",\ + "1.046036, 1.312197, 1.586878, 2.078553, 3.063056",\ + "1.269358, 1.535519, 1.810204, 2.301893, 3.286424",\ + "1.833308, 2.099468, 2.374159, 2.865866, 3.850434",\ + "1.246728, 1.542797, 1.806824, 2.295822, 3.276308",\ + "1.293256, 1.589325, 1.853353, 2.342354, 3.322847",\ + "1.378892, 1.674961, 1.938992, 2.428002, 3.408513",\ + "1.602214, 1.898283, 2.162318, 2.651342, 3.631880",\ + "2.166164, 2.462233, 2.726274, 3.215315, 4.195890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\ + "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\ + "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\ + "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031",\ + "0.052222, 0.052222, 0.052225, 0.052234, 0.052252",\ + "0.174407, 0.174407, 0.174405, 0.174399, 0.174386",\ + "0.378140, 0.378140, 0.378136, 0.378121, 0.378092",\ + "0.885509, 0.885509, 0.885508, 0.885504, 0.885495",\ + "2.163010, 2.163010, 2.163012, 2.163018, 2.163031"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.626180, 0.876518, 1.153319, 1.646441, 2.632685",\ + "0.679480, 0.929817, 1.206631, 1.699795, 2.686123",\ + "0.740236, 0.990574, 1.267397, 1.760594, 2.746988",\ + "0.874947, 1.125284, 1.402106, 1.895301, 2.881690",\ + "1.221451, 1.471789, 1.748606, 2.241784, 3.228139",\ + "0.713593, 0.964022, 1.240963, 1.733156, 2.718619",\ + "0.766892, 1.017322, 1.294275, 1.786510, 2.772057",\ + "0.827649, 1.078079, 1.355041, 1.847309, 2.832922",\ + "0.962359, 1.212789, 1.489751, 1.982016, 2.967624",\ + "1.308864, 1.559294, 1.836250, 2.328499, 3.314073",\ + "0.794449, 1.052909, 1.328929, 1.820778, 2.805574",\ + "0.847749, 1.106209, 1.382241, 1.874132, 2.859012",\ + "0.908505, 1.166965, 1.443007, 1.934931, 2.919877",\ + "1.043216, 1.301676, 1.577716, 2.069638, 3.054579",\ + "1.389720, 1.648180, 1.924216, 2.416121, 3.401028",\ + "0.852247, 1.118408, 1.393072, 1.884692, 2.869083",\ + "0.905546, 1.171707, 1.446384, 1.938046, 2.922521",\ + "0.966303, 1.232464, 1.507150, 1.998845, 2.983386",\ + "1.101013, 1.367174, 1.641860, 2.133552, 3.118088",\ + "1.447518, 1.713679, 1.988360, 2.480035, 3.464537",\ + "1.185103, 1.481172, 1.745186, 2.234141, 3.214539",\ + "1.238403, 1.534472, 1.798498, 2.287495, 3.267977",\ + "1.299159, 1.595228, 1.859265, 2.348294, 3.328842",\ + "1.433870, 1.729939, 1.993974, 2.483001, 3.463544",\ + "1.780374, 2.076443, 2.340474, 2.829484, 3.809993"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\ + "0.114010, 0.114010, 0.114035, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\ + "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\ + "0.114010, 0.114010, 0.114035, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\ + "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\ + "0.114010, 0.114010, 0.114035, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\ + "0.060053, 0.060053, 0.060071, 0.060133, 0.060259",\ + "0.114010, 0.114010, 0.114036, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199736, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422",\ + "0.060053, 0.060053, 0.060071, 0.060134, 0.060259",\ + "0.114010, 0.114010, 0.114036, 0.114122, 0.114295",\ + "0.199713, 0.199713, 0.199737, 0.199815, 0.199972",\ + "0.445490, 0.445490, 0.445492, 0.445501, 0.445519",\ + "1.101435, 1.101435, 1.101434, 1.101430, 1.101422"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_2645*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[17]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.486994, 0.689024, 0.898048, 1.222707, 1.844099",\ + "0.536854, 0.738884, 0.947908, 1.272568, 1.893960",\ + "0.638722, 0.840752, 1.049776, 1.374436, 1.995828",\ + "0.876584, 1.078614, 1.287637, 1.612297, 2.233689",\ + "1.448904, 1.650934, 1.859958, 2.184618, 2.806009",\ + "0.575735, 0.776343, 0.985328, 1.310012, 1.931453",\ + "0.625596, 0.826203, 1.035189, 1.359873, 1.981313",\ + "0.727464, 0.928071, 1.137057, 1.461741, 2.083181",\ + "0.965325, 1.165933, 1.374918, 1.699602, 2.321043",\ + "1.537645, 1.738253, 1.947239, 2.271923, 2.893363",\ + "0.665418, 0.856680, 1.065355, 1.390041, 2.011484",\ + "0.715279, 0.906541, 1.115216, 1.439901, 2.061345",\ + "0.817147, 1.008409, 1.217084, 1.541770, 2.163213",\ + "1.055008, 1.246270, 1.454945, 1.779631, 2.401074",\ + "1.627329, 1.818590, 2.027266, 2.351951, 2.973394",\ + "0.724126, 0.914549, 1.123120, 1.447544, 2.068644",\ + "0.773987, 0.964410, 1.172981, 1.497404, 2.118505",\ + "0.875855, 1.066278, 1.274849, 1.599272, 2.220373",\ + "1.113716, 1.304139, 1.512710, 1.837134, 2.458234",\ + "1.686036, 1.876459, 2.085031, 2.409454, 3.030555",\ + "1.026901, 1.220157, 1.426788, 1.750778, 2.371040",\ + "1.076761, 1.270018, 1.476649, 1.800639, 2.420901",\ + "1.178629, 1.371886, 1.578517, 1.902507, 2.522769",\ + "1.416491, 1.609747, 1.816378, 2.140368, 2.760630",\ + "1.988811, 2.182067, 2.388699, 2.712689, 3.332951"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.527722, 0.729752, 0.938776, 1.263436, 1.884828",\ + "0.550072, 0.752102, 0.961126, 1.285786, 1.907177",\ + "0.591435, 0.793465, 1.002489, 1.327149, 1.948541",\ + "0.713471, 0.915501, 1.124525, 1.449185, 2.070576",\ + "1.045084, 1.247114, 1.456138, 1.780797, 2.402189",\ + "0.616463, 0.817071, 1.026057, 1.350741, 1.972181",\ + "0.638813, 0.839421, 1.048407, 1.373091, 1.994531",\ + "0.680177, 0.880784, 1.089770, 1.414454, 2.035894",\ + "0.802212, 1.002820, 1.211806, 1.536490, 2.157930",\ + "1.133825, 1.334433, 1.543419, 1.868103, 2.489543",\ + "0.706147, 0.897409, 1.106084, 1.430769, 2.052213",\ + "0.728497, 0.919758, 1.128434, 1.453119, 2.074563",\ + "0.769860, 0.961122, 1.169797, 1.494483, 2.115926",\ + "0.891896, 1.083158, 1.291833, 1.616518, 2.237962",\ + "1.223509, 1.414770, 1.623446, 1.948131, 2.569574",\ + "0.764855, 0.955278, 1.163849, 1.488272, 2.109373",\ + "0.787204, 0.977627, 1.186199, 1.510622, 2.131722",\ + "0.828568, 1.018991, 1.227562, 1.551985, 2.173086",\ + "0.950603, 1.141026, 1.349598, 1.674021, 2.295122",\ + "1.282216, 1.472639, 1.681211, 2.005634, 2.626734",\ + "1.067629, 1.260886, 1.467517, 1.791507, 2.411769",\ + "1.089979, 1.283235, 1.489867, 1.813857, 2.434119",\ + "1.131342, 1.324599, 1.531230, 1.855220, 2.475482",\ + "1.253378, 1.446635, 1.653266, 1.977256, 2.597517",\ + "1.584991, 1.778247, 1.984879, 2.308869, 2.929131"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001292, 0.074290, 0.161471, 0.321651, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2543*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[19]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.402983, 0.589298, 0.781819, 1.078308, 1.645139",\ + "0.452846, 0.639161, 0.831682, 1.128171, 1.695002",\ + "0.554714, 0.741029, 0.933550, 1.230039, 1.796870",\ + "0.792575, 0.978890, 1.171412, 1.467901, 2.034731",\ + "1.364896, 1.551211, 1.743732, 2.040221, 2.607052",\ + "0.491182, 0.676616, 0.869099, 1.165613, 1.732492",\ + "0.541046, 0.726479, 0.918963, 1.215477, 1.782355",\ + "0.642913, 0.828347, 1.020831, 1.317344, 1.884223",\ + "0.880775, 1.066208, 1.258693, 1.555206, 2.122085",\ + "1.453095, 1.638529, 1.831013, 2.127527, 2.694405",\ + "0.578213, 0.756948, 0.949126, 1.245641, 1.812524",\ + "0.628077, 0.806812, 0.998990, 1.295505, 1.862387",\ + "0.729944, 0.908679, 1.100858, 1.397373, 1.964255",\ + "0.967806, 1.146541, 1.338719, 1.635234, 2.202116",\ + "1.540126, 1.718862, 1.911040, 2.207555, 2.774437",\ + "0.635881, 0.814778, 1.006854, 1.303079, 1.869555",\ + "0.685744, 0.864642, 1.056718, 1.352942, 1.919418",\ + "0.787612, 0.966509, 1.158586, 1.454810, 2.021286",\ + "1.025473, 1.204371, 1.396447, 1.692672, 2.259147",\ + "1.597794, 1.776692, 1.968768, 2.264992, 2.831468",\ + "0.938596, 1.120091, 1.310515, 1.606257, 2.171795",\ + "0.988459, 1.169954, 1.360379, 1.656120, 2.221658",\ + "1.090327, 1.271822, 1.462247, 1.757988, 2.323526",\ + "1.328188, 1.509683, 1.700108, 1.995849, 2.561387",\ + "1.900509, 2.082004, 2.272429, 2.568170, 3.133708"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039806, 0.039806, 0.039806, 0.039805, 0.039804",\ + "0.147771, 0.147771, 0.147771, 0.147771, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.423040, 0.630029, 0.815796, 1.107776, 1.669457",\ + "0.466065, 0.652380, 0.844901, 1.141390, 1.708220",\ + "0.507428, 0.693743, 0.886264, 1.182753, 1.749583",\ + "0.629463, 0.815778, 1.008300, 1.304789, 1.871619",\ + "0.961076, 1.147391, 1.339912, 1.636401, 2.203231",\ + "0.511411, 0.717348, 0.903077, 1.195081, 1.756810",\ + "0.554264, 0.739698, 0.932182, 1.228695, 1.795574",\ + "0.595627, 0.781061, 0.973545, 1.270058, 1.836937",\ + "0.717663, 0.903096, 1.095581, 1.392094, 1.958972",\ + "1.049275, 1.234709, 1.427193, 1.723706, 2.290585",\ + "0.600722, 0.797680, 0.983104, 1.275110, 1.836842",\ + "0.641295, 0.820030, 1.012209, 1.308724, 1.875605",\ + "0.682658, 0.861393, 1.053572, 1.350087, 1.916969",\ + "0.804694, 0.983429, 1.175608, 1.472122, 2.039004",\ + "1.136306, 1.315041, 1.507220, 1.803735, 2.370616",\ + "0.664349, 0.855510, 1.040816, 1.332541, 1.893861",\ + "0.698963, 0.877860, 1.069937, 1.366161, 1.932636",\ + "0.740326, 0.919223, 1.111300, 1.407524, 1.974000",\ + "0.862361, 1.041259, 1.233335, 1.529560, 2.096035",\ + "1.193974, 1.372871, 1.564948, 1.861172, 2.427648",\ + "0.979328, 1.160823, 1.344474, 1.635713, 2.196086",\ + "1.001678, 1.183173, 1.373598, 1.669339, 2.234876",\ + "1.043041, 1.224536, 1.414961, 1.710702, 2.276240",\ + "1.165076, 1.346571, 1.536997, 1.832738, 2.398275",\ + "1.496689, 1.678184, 1.868609, 2.164350, 2.729888"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002405, 0.075404, 0.162307, 0.322208, 0.642011"); + values ( "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045855",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2604*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.374729, 0.574327, 0.761134, 1.059803, 1.637058",\ + "0.424592, 0.624191, 0.810999, 1.109666, 1.686921",\ + "0.526460, 0.726059, 0.912867, 1.211534, 1.788789",\ + "0.764322, 0.963920, 1.150728, 1.449396, 2.026650",\ + "1.336642, 1.536241, 1.723049, 2.021717, 2.598970",\ + "0.463046, 0.661644, 0.848415, 1.147108, 1.724412",\ + "0.512909, 0.711509, 0.898280, 1.196972, 1.774274",\ + "0.614777, 0.813377, 1.000148, 1.298839, 1.876142",\ + "0.852638, 1.051238, 1.238009, 1.536701, 2.114003",\ + "1.424959, 1.623559, 1.810330, 2.109022, 2.686324",\ + "0.552645, 0.741973, 0.928442, 1.227136, 1.804443",\ + "0.602508, 0.791838, 0.978307, 1.277000, 1.854306",\ + "0.704376, 0.893705, 1.080175, 1.378868, 1.956174",\ + "0.942238, 1.131567, 1.318036, 1.616729, 2.194035",\ + "1.514558, 1.703888, 1.890357, 2.189050, 2.766356",\ + "0.616737, 0.799794, 0.986158, 1.284587, 1.861501",\ + "0.666600, 0.849659, 1.036023, 1.334451, 1.911364",\ + "0.768468, 0.951526, 1.137890, 1.436318, 2.013232",\ + "1.006329, 1.189388, 1.375752, 1.674180, 2.251093",\ + "1.578650, 1.761709, 1.948073, 2.246500, 2.823413",\ + "0.927115, 1.105032, 1.289816, 1.587775, 2.163774",\ + "0.976978, 1.154897, 1.339680, 1.637639, 2.213636",\ + "1.078846, 1.256764, 1.441548, 1.739507, 2.315504",\ + "1.316707, 1.494626, 1.679409, 1.977368, 2.553366",\ + "1.889028, 2.066947, 2.251730, 2.549689, 3.125686"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039798, 0.039798, 0.039798, 0.039798, 0.039798",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375008, 0.375008, 0.375009, 0.375009, 0.375009",\ + "0.869292, 0.869292, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.405230, 0.615060, 0.801868, 1.100535, 1.677789",\ + "0.437811, 0.637410, 0.824218, 1.122885, 1.700139",\ + "0.479174, 0.678774, 0.865581, 1.164248, 1.741502",\ + "0.601210, 0.800809, 0.987617, 1.286284, 1.863538",\ + "0.932822, 1.132421, 1.319229, 1.617896, 2.195150",\ + "0.493512, 0.702378, 0.889149, 1.187840, 1.765142",\ + "0.526127, 0.724728, 0.911499, 1.210190, 1.787492",\ + "0.567491, 0.766091, 0.952862, 1.251554, 1.828856",\ + "0.689526, 0.888126, 1.074898, 1.373589, 1.950891",\ + "1.021139, 1.219739, 1.406510, 1.705201, 2.282504",\ + "0.583007, 0.782706, 0.969176, 1.267869, 1.845174",\ + "0.615727, 0.805056, 0.991526, 1.290219, 1.867524",\ + "0.657090, 0.846420, 1.032889, 1.331582, 1.908887",\ + "0.779126, 0.968455, 1.154925, 1.453618, 2.030923",\ + "1.110738, 1.300067, 1.486537, 1.785230, 2.362535",\ + "0.646999, 0.840528, 1.026891, 1.325319, 1.902232",\ + "0.679819, 0.862878, 1.049241, 1.347669, 1.924582",\ + "0.721182, 0.904241, 1.090605, 1.389032, 1.965945",\ + "0.843217, 1.026276, 1.212640, 1.511068, 2.087981",\ + "1.174830, 1.357889, 1.544252, 1.842680, 2.419593",\ + "0.967847, 1.145766, 1.330549, 1.628508, 2.204504",\ + "0.990197, 1.168116, 1.352899, 1.650858, 2.226855",\ + "1.031560, 1.209479, 1.394262, 1.692221, 2.268218",\ + "1.153596, 1.331514, 1.516298, 1.814256, 2.390253",\ + "1.485208, 1.663126, 1.847910, 2.145869, 2.721866"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045855, 0.045855, 0.045855, 0.045855, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2705*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[23]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.222114, 0.403093, 0.604570, 0.931647, 1.565679",\ + "0.278140, 0.457431, 0.657946, 0.989844, 1.636478",\ + "0.353958, 0.531643, 0.731437, 1.068535, 1.728488",\ + "0.556156, 0.731457, 0.928039, 1.271464, 1.949653",\ + "1.100796, 1.274143, 1.466860, 1.814002, 2.504620",\ + "0.309523, 0.490411, 0.691851, 1.018952, 1.653032",\ + "0.365549, 0.544749, 0.745227, 1.077150, 1.723831",\ + "0.441367, 0.618961, 0.818717, 1.155840, 1.815842",\ + "0.643566, 0.818775, 1.015320, 1.358769, 2.037007",\ + "1.188205, 1.361462, 1.554141, 1.901307, 2.591974",\ + "0.390388, 0.570744, 0.771878, 1.098981, 1.733064",\ + "0.446403, 0.625082, 0.825254, 1.157178, 1.803863",\ + "0.522211, 0.699294, 0.898744, 1.235869, 1.895873",\ + "0.724394, 0.899108, 1.095347, 1.438797, 2.117038",\ + "1.269020, 1.441795, 1.634168, 1.981336, 2.672005",\ + "0.448070, 0.628579, 0.829627, 1.156500, 1.790257",\ + "0.504064, 0.682912, 0.883001, 1.214712, 1.861086",\ + "0.579852, 0.757117, 0.956490, 1.293419, 1.953129",\ + "0.782005, 0.956923, 1.153085, 1.496370, 2.174338",\ + "1.326607, 1.499602, 1.691897, 2.038924, 2.729335",\ + "0.750884, 0.933934, 1.133292, 1.459748, 2.092693",\ + "0.806686, 0.988222, 1.186665, 1.517973, 2.163558",\ + "0.882290, 1.062385, 1.260154, 1.596694, 2.255640",\ + "1.084171, 1.262128, 1.456748, 1.799664, 2.476902",\ + "1.628551, 1.804755, 1.995558, 2.342230, 3.031935"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.149901, 0.149901, 0.154272, 0.175587, 0.224039",\ + "0.237266, 0.237266, 0.240202, 0.254165, 0.285843",\ + "0.399712, 0.400490, 0.400737, 0.406993, 0.422155",\ + "0.873536, 0.873536, 0.873536, 0.874623, 0.877289",\ + "2.137324, 2.139116, 2.139203, 2.139986, 2.141907",\ + "0.149901, 0.149901, 0.154272, 0.175587, 0.224039",\ + "0.237266, 0.237266, 0.240202, 0.254165, 0.285843",\ + "0.399712, 0.400490, 0.400737, 0.406993, 0.422155",\ + "0.873536, 0.873536, 0.873536, 0.874623, 0.877289",\ + "2.137324, 2.139116, 2.139203, 2.139986, 2.141907",\ + "0.149901, 0.149901, 0.154272, 0.175587, 0.224039",\ + "0.237266, 0.237266, 0.240202, 0.254165, 0.285843",\ + "0.399717, 0.400490, 0.400737, 0.406993, 0.422155",\ + "0.873536, 0.873536, 0.873536, 0.874623, 0.877289",\ + "2.137336, 2.139116, 2.139203, 2.139986, 2.141907",\ + "0.149901, 0.149901, 0.154282, 0.175646, 0.224156",\ + "0.237266, 0.237266, 0.240209, 0.254204, 0.285920",\ + "0.399727, 0.400493, 0.400738, 0.407012, 0.422192",\ + "0.873536, 0.873536, 0.873536, 0.874626, 0.877296",\ + "2.137358, 2.139123, 2.139203, 2.139988, 2.141912",\ + "0.149901, 0.149901, 0.154284, 0.175697, 0.224297",\ + "0.237266, 0.237266, 0.240210, 0.254237, 0.286012",\ + "0.399816, 0.400514, 0.400738, 0.407027, 0.422236",\ + "0.873536, 0.873536, 0.873536, 0.874629, 0.877303",\ + "2.137563, 2.139170, 2.139203, 2.139990, 2.141917"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.146813, 0.421543, 0.619073, 0.936497, 1.550523",\ + "0.182955, 0.455962, 0.653305, 0.972716, 1.591584",\ + "0.237642, 0.505732, 0.702816, 1.023104, 1.644353",\ + "0.371091, 0.634162, 0.830900, 1.151008, 1.772115",\ + "0.705966, 0.969914, 1.166368, 1.485322, 2.103856",\ + "0.235216, 0.509090, 0.706354, 1.023802, 1.637876",\ + "0.271333, 0.543280, 0.740586, 1.060021, 1.678937",\ + "0.325990, 0.593050, 0.790097, 1.110409, 1.731706",\ + "0.459423, 0.721480, 0.918180, 1.238313, 1.859468",\ + "0.794276, 1.057232, 1.253649, 1.572627, 2.191210",\ + "0.324565, 0.589422, 0.786381, 1.103830, 1.717908",\ + "0.360611, 0.623613, 0.820613, 1.140050, 1.758969",\ + "0.415179, 0.673383, 0.870124, 1.190438, 1.811738",\ + "0.548565, 0.801813, 0.998207, 1.318341, 1.939500",\ + "0.883356, 1.137565, 1.333676, 1.652655, 2.271241",\ + "0.388205, 0.647259, 0.844120, 1.161325, 1.775052",\ + "0.424183, 0.681450, 0.878352, 1.197550, 1.816125",\ + "0.478670, 0.731220, 0.927863, 1.247941, 1.868900",\ + "0.612012, 0.859650, 1.055945, 1.375844, 1.996662",\ + "0.946745, 1.195402, 1.391413, 1.710155, 2.328397",\ + "0.724572, 0.952620, 1.147783, 1.464552, 2.077430",\ + "0.760125, 0.986813, 1.182015, 1.500782, 2.118517",\ + "0.814091, 1.036585, 1.231526, 1.551176, 2.171298",\ + "0.947154, 1.165011, 1.359608, 1.679079, 2.299060",\ + "1.281518, 1.500770, 1.695075, 2.013387, 2.630787"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002308, 0.075306, 0.162234, 0.322159, 0.642011"); + values ( "0.071550, 0.074340, 0.076398, 0.092998, 0.129684",\ + "0.104996, 0.104996, 0.106760, 0.117958, 0.143880",\ + "0.191043, 0.191210, 0.191730, 0.197481, 0.211138",\ + "0.431517, 0.431517, 0.431517, 0.433284, 0.437618",\ + "1.064302, 1.065326, 1.065376, 1.065376, 1.065376",\ + "0.071556, 0.071791, 0.076398, 0.092998, 0.129684",\ + "0.104996, 0.104996, 0.106760, 0.117958, 0.143880",\ + "0.191048, 0.191210, 0.191730, 0.197481, 0.211138",\ + "0.431517, 0.431517, 0.431517, 0.433284, 0.437618",\ + "1.064330, 1.065326, 1.065376, 1.065376, 1.065376",\ + "0.071575, 0.071791, 0.076398, 0.092998, 0.129684",\ + "0.104996, 0.104996, 0.106760, 0.117958, 0.143880",\ + "0.191061, 0.191210, 0.191730, 0.197481, 0.211138",\ + "0.431517, 0.431517, 0.431517, 0.433284, 0.437618",\ + "1.064411, 1.065326, 1.065376, 1.065376, 1.065376",\ + "0.071593, 0.071792, 0.076409, 0.093042, 0.129773",\ + "0.104996, 0.104996, 0.106764, 0.117989, 0.143943",\ + "0.191073, 0.191211, 0.191731, 0.197497, 0.211171",\ + "0.431517, 0.431517, 0.431517, 0.433289, 0.437628",\ + "1.064486, 1.065330, 1.065376, 1.065376, 1.065376",\ + "0.071706, 0.071799, 0.076411, 0.093080, 0.129880",\ + "0.104996, 0.104996, 0.106764, 0.118016, 0.144018",\ + "0.191152, 0.191215, 0.191732, 0.197512, 0.211211",\ + "0.431517, 0.431517, 0.431517, 0.433294, 0.437641",\ + "1.064965, 1.065357, 1.065376, 1.065376, 1.065376"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.170538, 0.344791, 0.534395, 0.834671, 1.413373",\ + "0.220382, 0.410357, 0.608123, 0.926913, 1.543930",\ + "0.296720, 0.496999, 0.695612, 1.028145, 1.678018",\ + "0.503635, 0.714092, 0.910615, 1.258034, 1.946089",\ + "1.056522, 1.269056, 1.463869, 1.813497, 2.508420",\ + "0.258747, 0.432108, 0.621676, 0.921976, 1.500726",\ + "0.308608, 0.497675, 0.695404, 1.014218, 1.631283",\ + "0.384956, 0.584317, 0.782893, 1.115450, 1.765372",\ + "0.591859, 0.801410, 0.997896, 1.345339, 2.033442",\ + "1.144699, 1.356374, 1.551150, 1.900803, 2.595773",\ + "0.340253, 0.512437, 0.701702, 1.002005, 1.580758",\ + "0.397921, 0.578003, 0.775430, 1.094246, 1.711315",\ + "0.474302, 0.664646, 0.862920, 1.195478, 1.845403",\ + "0.681166, 0.881738, 1.077923, 1.425368, 2.113474",\ + "1.233862, 1.436702, 1.631177, 1.980831, 2.675804",\ + "0.397891, 0.570245, 0.759425, 1.059457, 1.637819",\ + "0.461736, 0.635815, 0.833172, 1.151745, 1.768469",\ + "0.538147, 0.722460, 0.920664, 1.253017, 1.902637",\ + "0.744974, 0.939560, 1.135661, 1.482953, 2.170799",\ + "1.297532, 1.494526, 1.688912, 2.038425, 2.733147",\ + "0.700600, 0.875392, 1.063084, 1.362647, 1.940096",\ + "0.765324, 0.940987, 1.136834, 1.454975, 2.070858",\ + "0.851439, 1.027647, 1.224326, 1.556282, 2.205122",\ + "1.066882, 1.244797, 1.439323, 1.786257, 2.473396",\ + "1.621173, 1.799784, 1.992573, 2.341736, 3.035763"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.138974, 0.138974, 0.138974, 0.148689, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872442, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139574, 2.140537, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148689, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872465, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139599, 2.140537, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148689, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872537, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139673, 2.140537, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148718, 0.172471",\ + "0.231167, 0.231167, 0.231167, 0.238044, 0.254807",\ + "0.397287, 0.397287, 0.397287, 0.400384, 0.407935",\ + "0.872606, 0.873372, 0.873689, 0.874396, 0.875879",\ + "2.139745, 2.140541, 2.140572, 2.140673, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148743, 0.172540",\ + "0.231167, 0.231167, 0.231167, 0.238062, 0.254856",\ + "0.397287, 0.397287, 0.397287, 0.400392, 0.407957",\ + "0.872562, 0.873396, 0.873689, 0.874398, 0.875884",\ + "2.139699, 2.140566, 2.140572, 2.140673, 2.140919"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.114471, 0.367066, 0.558465, 0.861628, 1.446142",\ + "0.150570, 0.396419, 0.587661, 0.892759, 1.482112",\ + "0.204674, 0.442227, 0.633125, 0.939020, 1.530584",\ + "0.336064, 0.565592, 0.755956, 1.061790, 1.653617",\ + "0.673293, 0.896815, 1.086094, 1.390763, 1.980611",\ + "0.202627, 0.454384, 0.645746, 0.948933, 1.533495",\ + "0.238831, 0.483737, 0.674942, 0.980064, 1.569466",\ + "0.292913, 0.529545, 0.720406, 1.026325, 1.617937",\ + "0.424271, 0.652910, 0.843237, 1.149095, 1.740970",\ + "0.761475, 0.984133, 1.173375, 1.478068, 2.067965",\ + "0.291726, 0.534712, 0.725773, 1.028962, 1.613527",\ + "0.328254, 0.564066, 0.754969, 1.060092, 1.649498",\ + "0.382266, 0.609874, 0.800433, 1.106354, 1.697969",\ + "0.513528, 0.733239, 0.923264, 1.229123, 1.821002",\ + "0.850652, 1.064461, 1.253402, 1.558096, 2.147996",\ + "0.355336, 0.592555, 0.783499, 1.086421, 1.670602",\ + "0.392174, 0.621907, 0.812695, 1.117557, 1.706585",\ + "0.446119, 0.667711, 0.858158, 1.163821, 1.755061",\ + "0.577288, 0.791071, 0.980987, 1.286592, 1.878095",\ + "0.914335, 1.122288, 1.311124, 1.615562, 2.205085",\ + "0.691472, 0.897945, 1.087159, 1.389617, 1.972896",\ + "0.730295, 0.927282, 1.116354, 1.420759, 2.008893",\ + "0.783810, 0.973061, 1.161817, 1.467025, 2.057376",\ + "0.914389, 1.096386, 1.284647, 1.589795, 2.180410",\ + "1.248447, 1.427560, 1.614782, 1.918764, 2.507394"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.055015, 0.067356, 0.073976, 0.088784, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432838, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.055327, 0.067356, 0.073976, 0.088784, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432865, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.056284, 0.067356, 0.073976, 0.088784, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432950, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.057202, 0.067402, 0.073991, 0.088822, 0.119782",\ + "0.104870, 0.104870, 0.106673, 0.116322, 0.138328",\ + "0.190674, 0.190674, 0.191256, 0.196143, 0.207567",\ + "0.433032, 0.433938, 0.434140, 0.435065, 0.437181",\ + "1.062723, 1.062723, 1.063224, 1.064132, 1.065926",\ + "0.063072, 0.067724, 0.073993, 0.088854, 0.119873",\ + "0.104870, 0.104870, 0.106674, 0.116345, 0.138392",\ + "0.190674, 0.190674, 0.191256, 0.196155, 0.207600",\ + "0.433553, 0.433966, 0.434140, 0.435067, 0.437187",\ + "1.062723, 1.062723, 1.063224, 1.064134, 1.065932"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2340*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.337877, 0.567396, 0.751267, 1.044506, 1.611115",\ + "0.385816, 0.615335, 0.799206, 1.092445, 1.659054",\ + "0.487851, 0.717370, 0.901241, 1.194480, 1.761089",\ + "0.725267, 0.954786, 1.138657, 1.431895, 1.998505",\ + "1.296926, 1.526444, 1.710315, 2.003554, 2.570163",\ + "0.426171, 0.654713, 0.838548, 1.131811, 1.698468",\ + "0.474110, 0.702653, 0.886487, 1.179750, 1.746408",\ + "0.576145, 0.804687, 0.988522, 1.281785, 1.848443",\ + "0.813561, 1.042103, 1.225938, 1.519201, 2.085858",\ + "1.385220, 1.613762, 1.797596, 2.090859, 2.657517",\ + "0.515866, 0.735041, 0.918575, 1.211839, 1.778500",\ + "0.563806, 0.782980, 0.966514, 1.259778, 1.826439",\ + "0.665841, 0.885015, 1.068549, 1.361813, 1.928474",\ + "0.903256, 1.122430, 1.305965, 1.599229, 2.165890",\ + "1.474915, 1.694089, 1.877623, 2.170888, 2.737548",\ + "0.580118, 0.792869, 0.976284, 1.269277, 1.835533",\ + "0.628057, 0.840809, 1.024223, 1.317216, 1.883472",\ + "0.730092, 0.942843, 1.126258, 1.419251, 1.985507",\ + "0.967507, 1.180259, 1.363673, 1.656667, 2.222923",\ + "1.539166, 1.751918, 1.935332, 2.228325, 2.794581",\ + "0.919018, 1.098154, 1.279940, 1.572454, 2.137775",\ + "0.966958, 1.146093, 1.327879, 1.620393, 2.185715",\ + "1.068992, 1.248128, 1.429914, 1.722428, 2.287750",\ + "1.306408, 1.485543, 1.667330, 1.959844, 2.525165",\ + "1.878067, 2.057202, 2.238988, 2.531503, 3.096824"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.372253, 0.601881, 0.784032, 1.076595, 1.643049",\ + "0.397511, 0.627029, 0.810901, 1.104139, 1.670748",\ + "0.438896, 0.668415, 0.852286, 1.145524, 1.712134",\ + "0.561215, 0.790734, 0.974605, 1.267843, 1.834453",\ + "0.893448, 1.122967, 1.306838, 1.600076, 2.166686",\ + "0.460528, 0.689198, 0.871313, 1.163900, 1.730402",\ + "0.485805, 0.714347, 0.898181, 1.191444, 1.758102",\ + "0.527190, 0.755732, 0.939567, 1.232830, 1.799487",\ + "0.649509, 0.878051, 1.061886, 1.355149, 1.921806",\ + "0.981742, 1.210284, 1.394119, 1.687381, 2.254039",\ + "0.550165, 0.769525, 0.951340, 1.243928, 1.810434",\ + "0.575500, 0.794674, 0.978208, 1.271473, 1.838133",\ + "0.616885, 0.836059, 1.019594, 1.312858, 1.879519",\ + "0.739204, 0.958378, 1.141913, 1.435177, 2.001838",\ + "1.071437, 1.290611, 1.474146, 1.767410, 2.334071",\ + "0.614360, 0.827361, 1.009044, 1.301366, 1.867467",\ + "0.639751, 0.852503, 1.035917, 1.328910, 1.895166",\ + "0.681136, 0.893888, 1.077302, 1.370296, 1.936552",\ + "0.803456, 1.016207, 1.199622, 1.492615, 2.058871",\ + "1.135688, 1.348440, 1.531854, 1.824847, 2.391104",\ + "0.951814, 1.132696, 1.312700, 1.604543, 2.169709",\ + "0.978652, 1.157787, 1.339573, 1.632088, 2.197409",\ + "1.020037, 1.199172, 1.380959, 1.673473, 2.238794",\ + "1.142356, 1.321491, 1.503278, 1.795792, 2.361114",\ + "1.474589, 1.653724, 1.835510, 2.128025, 2.693346"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2710*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.323167, 0.539803, 0.719494, 1.009588, 1.571964",\ + "0.371106, 0.587742, 0.767433, 1.057527, 1.619903",\ + "0.473141, 0.689777, 0.869468, 1.159562, 1.721938",\ + "0.710557, 0.927193, 1.106884, 1.396978, 1.959354",\ + "1.282216, 1.498852, 1.678543, 1.968637, 2.531013",\ + "0.411457, 0.627121, 0.806775, 1.096893, 1.659318",\ + "0.459396, 0.675060, 0.854714, 1.144832, 1.707257",\ + "0.561431, 0.777095, 0.956749, 1.246867, 1.809292",\ + "0.798847, 1.014511, 1.194165, 1.484283, 2.046708",\ + "1.370506, 1.586170, 1.765824, 2.055942, 2.618367",\ + "0.500498, 0.707454, 0.886802, 1.176922, 1.739349",\ + "0.548437, 0.755393, 0.934741, 1.224860, 1.787288",\ + "0.650472, 0.857428, 1.036776, 1.326895, 1.889323",\ + "0.887888, 1.094844, 1.274192, 1.564311, 2.126739",\ + "1.459547, 1.666503, 1.845851, 2.135971, 2.698398",\ + "0.563859, 0.765284, 0.944499, 1.234353, 1.796369",\ + "0.611798, 0.813223, 0.992438, 1.282292, 1.844308",\ + "0.713833, 0.915258, 1.094473, 1.384327, 1.946343",\ + "0.951249, 1.152674, 1.331889, 1.621743, 2.183759",\ + "1.522908, 1.724333, 1.903548, 2.193402, 2.755418",\ + "0.888835, 1.070603, 1.248155, 1.537527, 2.098596",\ + "0.936774, 1.118542, 1.296094, 1.585466, 2.146535",\ + "1.038809, 1.220577, 1.398129, 1.687501, 2.248570",\ + "1.276225, 1.457993, 1.635545, 1.924917, 2.485986",\ + "1.847884, 2.029652, 2.207204, 2.496576, 3.057645"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871095, 0.871095, 0.871095, 0.871095, 0.871095",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.360736, 0.577372, 0.757063, 1.047157, 1.609533",\ + "0.382801, 0.599437, 0.779128, 1.069222, 1.631598",\ + "0.424186, 0.640822, 0.820514, 1.110608, 1.672984",\ + "0.546505, 0.763141, 0.942833, 1.232926, 1.795303",\ + "0.878738, 1.095374, 1.275065, 1.565159, 2.127535",\ + "0.449026, 0.664690, 0.844344, 1.134462, 1.696887",\ + "0.471091, 0.686755, 0.866409, 1.156527, 1.718952",\ + "0.512477, 0.728141, 0.907795, 1.197913, 1.760337",\ + "0.634796, 0.850460, 1.030114, 1.320232, 1.882656",\ + "0.967028, 1.182692, 1.362346, 1.652464, 2.214889",\ + "0.538067, 0.745023, 0.924371, 1.214491, 1.776918",\ + "0.560132, 0.767088, 0.946436, 1.236556, 1.798984",\ + "0.601517, 0.808473, 0.987821, 1.277941, 1.840369",\ + "0.723837, 0.930792, 1.110141, 1.400260, 1.962688",\ + "1.056069, 1.263025, 1.442373, 1.732492, 2.294920",\ + "0.601428, 0.802853, 0.982068, 1.271922, 1.833938",\ + "0.623493, 0.824919, 1.004133, 1.293988, 1.856004",\ + "0.664878, 0.866304, 1.045519, 1.335373, 1.897389",\ + "0.787198, 0.988623, 1.167838, 1.457692, 2.019708",\ + "1.119430, 1.320855, 1.500070, 1.789924, 2.351940",\ + "0.926404, 1.108172, 1.285724, 1.575096, 2.136165",\ + "0.948469, 1.130237, 1.307790, 1.597161, 2.158231",\ + "0.989855, 1.171622, 1.349175, 1.638546, 2.199616",\ + "1.112174, 1.293941, 1.471494, 1.760865, 2.321935",\ + "1.444406, 1.626174, 1.803726, 2.093098, 2.654167"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2399*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[32]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.393798, 0.608317, 0.787191, 1.076625, 1.638145",\ + "0.443659, 0.658178, 0.837052, 1.126486, 1.688006",\ + "0.545527, 0.760046, 0.938920, 1.228354, 1.789874",\ + "0.783388, 0.997908, 1.176781, 1.466215, 2.027735",\ + "1.355708, 1.570228, 1.749101, 2.038536, 2.600056",\ + "0.482072, 0.695635, 0.874472, 1.163930, 1.725499",\ + "0.531933, 0.745496, 0.924333, 1.213791, 1.775360",\ + "0.633801, 0.847364, 1.026201, 1.315659, 1.877228",\ + "0.871662, 1.085225, 1.264062, 1.553521, 2.115089",\ + "1.443982, 1.657546, 1.836382, 2.125841, 2.687409",\ + "0.571616, 0.775963, 0.954499, 1.243959, 1.805530",\ + "0.621477, 0.825824, 1.004360, 1.293820, 1.855391",\ + "0.723345, 0.927692, 1.106228, 1.395688, 1.957259",\ + "0.961206, 1.165553, 1.344089, 1.633549, 2.195120",\ + "1.533526, 1.737874, 1.916409, 2.205869, 2.767441",\ + "0.635684, 0.833793, 1.012195, 1.301390, 1.862550",\ + "0.685545, 0.883654, 1.062056, 1.351251, 1.912411",\ + "0.787413, 0.985522, 1.163924, 1.453119, 2.014279",\ + "1.025275, 1.223383, 1.401785, 1.690980, 2.252141",\ + "1.597595, 1.795703, 1.974106, 2.263301, 2.824461",\ + "0.959458, 1.139086, 1.315850, 1.604562, 2.164778",\ + "1.009318, 1.188946, 1.365711, 1.654423, 2.214639",\ + "1.111187, 1.290814, 1.467579, 1.756291, 2.316507",\ + "1.349048, 1.528676, 1.705440, 1.994153, 2.554368",\ + "1.921368, 2.100996, 2.277760, 2.566473, 3.126688"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.434527, 0.649046, 0.827920, 1.117354, 1.678874",\ + "0.456877, 0.671396, 0.850269, 1.139704, 1.701224",\ + "0.498240, 0.712759, 0.891633, 1.181067, 1.742587",\ + "0.620276, 0.834795, 1.013668, 1.303103, 1.864623",\ + "0.951889, 1.166408, 1.345281, 1.634716, 2.196236",\ + "0.522801, 0.736364, 0.915201, 1.204659, 1.766227",\ + "0.545151, 0.758714, 0.937550, 1.227009, 1.788577",\ + "0.586514, 0.800077, 0.978914, 1.268372, 1.829941",\ + "0.708550, 0.922113, 1.100950, 1.390408, 1.951976",\ + "1.040162, 1.253726, 1.432562, 1.722021, 2.283589",\ + "0.612344, 0.816692, 0.995228, 1.284688, 1.846259",\ + "0.634694, 0.839042, 1.017577, 1.307038, 1.868609",\ + "0.676058, 0.880405, 1.058941, 1.348401, 1.909972",\ + "0.798093, 1.002441, 1.180976, 1.470437, 2.032008",\ + "1.129706, 1.334054, 1.512589, 1.802049, 2.363621",\ + "0.676413, 0.874521, 1.052924, 1.342119, 1.903279",\ + "0.698763, 0.896871, 1.075274, 1.364469, 1.925629",\ + "0.740127, 0.938235, 1.116637, 1.405832, 1.966993",\ + "0.862162, 1.060270, 1.238673, 1.527868, 2.089028",\ + "1.193775, 1.391883, 1.570286, 1.859481, 2.420641",\ + "1.000186, 1.179814, 1.356578, 1.645291, 2.205507",\ + "1.022536, 1.202164, 1.378928, 1.667641, 2.227856",\ + "1.063900, 1.243527, 1.420292, 1.709004, 2.269220",\ + "1.185935, 1.365563, 1.542327, 1.831040, 2.391255",\ + "1.517548, 1.697176, 1.873940, 2.162653, 2.722868"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003362, 0.076361, 0.163024, 0.322686, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2477*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.454939, 0.667221, 0.852612, 1.143493, 1.702667",\ + "0.502878, 0.715160, 0.900551, 1.191432, 1.750605",\ + "0.604913, 0.817195, 1.002586, 1.293467, 1.852640",\ + "0.842329, 1.054611, 1.240002, 1.530883, 2.090056",\ + "1.413988, 1.626270, 1.811661, 2.102542, 2.661716",\ + "0.543302, 0.754540, 0.939893, 1.230798, 1.790020",\ + "0.591241, 0.802479, 0.987832, 1.278737, 1.837959",\ + "0.693276, 0.904514, 1.089867, 1.380772, 1.939994",\ + "0.930692, 1.141930, 1.327283, 1.618188, 2.177410",\ + "1.502351, 1.713589, 1.898942, 2.189847, 2.749069",\ + "0.632361, 0.834874, 1.019920, 1.310827, 1.870051",\ + "0.680300, 0.882813, 1.067859, 1.358765, 1.917990",\ + "0.782335, 0.984848, 1.169894, 1.460800, 2.020025",\ + "1.019751, 1.222264, 1.407310, 1.698216, 2.257441",\ + "1.591410, 1.793923, 1.978969, 2.269875, 2.829100",\ + "0.695656, 0.892702, 1.077631, 1.368254, 1.927063",\ + "0.743595, 0.940641, 1.125570, 1.416193, 1.975002",\ + "0.845629, 1.042676, 1.227605, 1.518228, 2.077037",\ + "1.083045, 1.280092, 1.465021, 1.755644, 2.314453",\ + "1.654704, 1.851751, 2.036680, 2.327303, 2.886112",\ + "1.016280, 1.198005, 1.381290, 1.671425, 2.229280",\ + "1.064219, 1.245944, 1.429229, 1.719364, 2.277219",\ + "1.166254, 1.347979, 1.531264, 1.821398, 2.379254",\ + "1.403669, 1.585395, 1.768679, 2.058815, 2.616670",\ + "1.975328, 2.157054, 2.340338, 2.630474, 3.188329"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.492508, 0.704790, 0.890181, 1.181062, 1.740236",\ + "0.514573, 0.726856, 0.912247, 1.203127, 1.762301",\ + "0.555959, 0.768241, 0.953632, 1.244512, 1.803686",\ + "0.678278, 0.890560, 1.075951, 1.366831, 1.926005",\ + "1.010510, 1.222792, 1.408183, 1.699064, 2.258237",\ + "0.580871, 0.792109, 0.977462, 1.268367, 1.827589",\ + "0.602936, 0.814174, 0.999527, 1.290432, 1.849654",\ + "0.644321, 0.855559, 1.040913, 1.331817, 1.891039",\ + "0.766640, 0.977878, 1.163232, 1.454136, 2.013358",\ + "1.098873, 1.310111, 1.495464, 1.786369, 2.345591",\ + "0.669930, 0.872443, 1.057489, 1.348396, 1.907620",\ + "0.691995, 0.894508, 1.079554, 1.370461, 1.929686",\ + "0.733381, 0.935894, 1.120940, 1.411846, 1.971071",\ + "0.855700, 1.058213, 1.243259, 1.534165, 2.093390",\ + "1.187932, 1.390445, 1.575491, 1.866397, 2.425622",\ + "0.733225, 0.930271, 1.115200, 1.405823, 1.964632",\ + "0.755290, 0.952336, 1.137265, 1.427888, 1.986697",\ + "0.796675, 0.993721, 1.178650, 1.469274, 2.028083",\ + "0.918994, 1.116040, 1.300969, 1.591593, 2.150402",\ + "1.251227, 1.448273, 1.633202, 1.923825, 2.482634",\ + "1.053849, 1.235574, 1.418859, 1.708994, 2.266849",\ + "1.075914, 1.257639, 1.440924, 1.731059, 2.288914",\ + "1.117299, 1.299025, 1.482309, 1.772444, 2.330299",\ + "1.239618, 1.421344, 1.604628, 1.894763, 2.452619",\ + "1.571851, 1.753576, 1.936861, 2.226995, 2.784851"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089555, 0.089555, 0.089555, 0.089555, 0.089555",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2561*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.429494, 0.640486, 0.817408, 1.101335, 1.650898",\ + "0.477433, 0.688425, 0.865347, 1.149274, 1.698837",\ + "0.579467, 0.790460, 0.967382, 1.251309, 1.800872",\ + "0.816883, 1.027876, 1.204798, 1.488725, 2.038288",\ + "1.388543, 1.599535, 1.776457, 2.060384, 2.609947",\ + "0.517769, 0.727804, 0.904689, 1.188640, 1.738251",\ + "0.565708, 0.775743, 0.952628, 1.236579, 1.786190",\ + "0.667743, 0.877778, 1.054663, 1.338614, 1.888225",\ + "0.905159, 1.115194, 1.292079, 1.576030, 2.125641",\ + "1.476818, 1.686853, 1.863738, 2.147689, 2.697300",\ + "0.606719, 0.808137, 0.984716, 1.268669, 1.818283",\ + "0.654658, 0.856076, 1.032655, 1.316607, 1.866222",\ + "0.756693, 0.958111, 1.134690, 1.418642, 1.968257",\ + "0.994109, 1.195527, 1.372106, 1.656058, 2.205673",\ + "1.565768, 1.767186, 1.943765, 2.227717, 2.777332",\ + "0.669974, 0.865958, 1.042407, 1.326085, 1.875272",\ + "0.717913, 0.913897, 1.090346, 1.374024, 1.923211",\ + "0.819948, 1.015932, 1.192381, 1.476059, 2.025246",\ + "1.057364, 1.253348, 1.429797, 1.713475, 2.262662",\ + "1.629023, 1.825007, 2.001456, 2.285134, 2.834321",\ + "0.991556, 1.171211, 1.346062, 1.629245, 2.177461",\ + "1.039495, 1.219150, 1.394001, 1.677184, 2.225400",\ + "1.141530, 1.321185, 1.496036, 1.779219, 2.327435",\ + "1.378946, 1.558601, 1.733452, 2.016635, 2.564851",\ + "1.950605, 2.130260, 2.305111, 2.588294, 3.136510"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032953, 0.032953, 0.032953, 0.032953, 0.032953",\ + "0.148289, 0.148289, 0.148289, 0.148289, 0.148289",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.467063, 0.678055, 0.854977, 1.138904, 1.688467",\ + "0.489128, 0.700120, 0.877042, 1.160969, 1.710532",\ + "0.530513, 0.741505, 0.918428, 1.202354, 1.751917",\ + "0.652832, 0.863824, 1.040747, 1.324673, 1.874236",\ + "0.985064, 1.196057, 1.372979, 1.656906, 2.206469",\ + "0.555338, 0.765373, 0.942258, 1.226209, 1.775820",\ + "0.577403, 0.787438, 0.964323, 1.248274, 1.797885",\ + "0.618789, 0.828824, 1.005709, 1.289660, 1.839271",\ + "0.741108, 0.951143, 1.128028, 1.411978, 1.961590",\ + "1.073340, 1.283375, 1.460260, 1.744211, 2.293822",\ + "0.644288, 0.845706, 1.022285, 1.306238, 1.855852",\ + "0.666353, 0.867771, 1.044350, 1.328303, 1.877917",\ + "0.707738, 0.909157, 1.085736, 1.369688, 1.919302",\ + "0.830057, 1.031476, 1.208055, 1.492007, 2.041621",\ + "1.162290, 1.363708, 1.540287, 1.824239, 2.373854",\ + "0.707543, 0.903527, 1.079976, 1.363654, 1.912841",\ + "0.729608, 0.925592, 1.102041, 1.385719, 1.934906",\ + "0.770994, 0.966978, 1.143427, 1.427104, 1.976291",\ + "0.893313, 1.089297, 1.265746, 1.549423, 2.098610",\ + "1.225545, 1.421529, 1.597978, 1.881656, 2.430843",\ + "1.029125, 1.208780, 1.383631, 1.666814, 2.215030",\ + "1.051190, 1.230845, 1.405696, 1.688879, 2.237095",\ + "1.092575, 1.272231, 1.447082, 1.730264, 2.278481",\ + "1.214894, 1.394550, 1.569401, 1.852583, 2.400800",\ + "1.547127, 1.726782, 1.901633, 2.184816, 2.733032"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030",\ + "0.039651, 0.039651, 0.039651, 0.039651, 0.039651",\ + "0.089556, 0.089556, 0.089556, 0.089556, 0.089556",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065030, 1.065030, 1.065030, 1.065030, 1.065030"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2624*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.495805, 0.717554, 0.895492, 1.184407, 1.745240",\ + "0.543744, 0.765493, 0.943432, 1.232346, 1.793180",\ + "0.645779, 0.867528, 1.045467, 1.334381, 1.895214",\ + "0.883194, 1.104943, 1.282882, 1.571797, 2.132630",\ + "1.454853, 1.676602, 1.854541, 2.143455, 2.704289",\ + "0.584213, 0.804872, 0.982773, 1.271712, 1.832594",\ + "0.632152, 0.852811, 1.030712, 1.319651, 1.880533",\ + "0.734187, 0.954846, 1.132747, 1.421686, 1.982568",\ + "0.971603, 1.192262, 1.370163, 1.659102, 2.219983",\ + "1.543261, 1.763920, 1.941822, 2.230760, 2.791642",\ + "0.673303, 0.885207, 1.062800, 1.351740, 1.912625",\ + "0.721243, 0.933146, 1.110739, 1.399680, 1.960565",\ + "0.823277, 1.035181, 1.212774, 1.501714, 2.062599",\ + "1.060693, 1.272597, 1.450190, 1.739130, 2.300015",\ + "1.632352, 1.844256, 2.021849, 2.310789, 2.871674",\ + "0.736581, 0.943024, 1.120493, 1.409170, 1.969641",\ + "0.784520, 0.990963, 1.168432, 1.457109, 2.017580",\ + "0.886555, 1.092998, 1.270467, 1.559144, 2.119615",\ + "1.123971, 1.330414, 1.507883, 1.796560, 2.357030",\ + "1.695630, 1.902072, 2.079542, 2.368218, 2.928689",\ + "1.068830, 1.248253, 1.424150, 1.712342, 2.271862",\ + "1.116770, 1.296192, 1.472089, 1.760281, 2.319801",\ + "1.218804, 1.398227, 1.574124, 1.862316, 2.421836",\ + "1.456220, 1.635643, 1.811539, 2.099732, 2.659251",\ + "2.027879, 2.207301, 2.383198, 2.671391, 3.230910"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.529176, 0.750903, 0.928871, 1.217786, 1.778615",\ + "0.555438, 0.777187, 0.955126, 1.244040, 1.804874",\ + "0.596823, 0.818572, 0.996511, 1.285426, 1.846259",\ + "0.719142, 0.940891, 1.118830, 1.407745, 1.968578",\ + "1.051375, 1.273124, 1.451063, 1.739977, 2.300811",\ + "0.617584, 0.838221, 1.016152, 1.305091, 1.865968",\ + "0.643846, 0.864506, 1.042407, 1.331345, 1.892227",\ + "0.685232, 0.905891, 1.083792, 1.372731, 1.933612",\ + "0.807551, 1.028210, 1.206111, 1.495050, 2.055932",\ + "1.139784, 1.360443, 1.538344, 1.827282, 2.388164",\ + "0.706675, 0.918556, 1.096179, 1.385120, 1.946000",\ + "0.732937, 0.944841, 1.122434, 1.411374, 1.972259",\ + "0.774322, 0.986226, 1.163819, 1.452759, 2.013644",\ + "0.896641, 1.108545, 1.286138, 1.575078, 2.135963",\ + "1.228874, 1.440778, 1.618371, 1.907311, 2.468196",\ + "0.769953, 0.976375, 1.153872, 1.442550, 2.003015",\ + "0.796215, 1.002657, 1.180127, 1.468804, 2.029274",\ + "0.837600, 1.044043, 1.221512, 1.510189, 2.070659",\ + "0.959919, 1.166362, 1.343831, 1.632508, 2.192978",\ + "1.292152, 1.498595, 1.676064, 1.964741, 2.525211",\ + "1.101828, 1.281614, 1.457528, 1.745722, 2.305236",\ + "1.128464, 1.307886, 1.483783, 1.771976, 2.331495",\ + "1.169849, 1.349272, 1.525168, 1.813361, 2.372880",\ + "1.292168, 1.471591, 1.647487, 1.935680, 2.495200",\ + "1.624401, 1.803824, 1.979720, 2.267913, 2.827432"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2674*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.473135, 0.702103, 0.886918, 1.182452, 1.753613",\ + "0.521074, 0.750043, 0.934857, 1.230392, 1.801553",\ + "0.623109, 0.852077, 1.036892, 1.332426, 1.903588",\ + "0.860525, 1.089493, 1.274307, 1.569842, 2.141003",\ + "1.432183, 1.661152, 1.845966, 2.141501, 2.712662",\ + "0.561467, 0.789422, 0.974199, 1.269758, 1.840967",\ + "0.609406, 0.837361, 1.022138, 1.317697, 1.888906",\ + "0.711441, 0.939396, 1.124173, 1.419731, 1.990941",\ + "0.948857, 1.176811, 1.361588, 1.657147, 2.228357",\ + "1.520515, 1.748470, 1.933247, 2.228806, 2.800015",\ + "0.650685, 0.869754, 1.054226, 1.349786, 1.920998",\ + "0.698624, 0.917693, 1.102165, 1.397725, 1.968938",\ + "0.800659, 1.019728, 1.204200, 1.499760, 2.070972",\ + "1.038074, 1.257143, 1.441615, 1.737176, 2.308388",\ + "1.609733, 1.828802, 2.013274, 2.308835, 2.880047",\ + "0.714235, 0.927578, 1.111935, 1.407229, 1.978040",\ + "0.762174, 0.975517, 1.159875, 1.455168, 2.025979",\ + "0.864209, 1.077552, 1.261909, 1.557203, 2.128014",\ + "1.101624, 1.314968, 1.499325, 1.794618, 2.365430",\ + "1.673283, 1.886627, 2.070984, 2.366277, 2.937088",\ + "1.050030, 1.232851, 1.415593, 1.710411, 2.280293",\ + "1.097969, 1.280791, 1.463533, 1.758350, 2.328232",\ + "1.200004, 1.382825, 1.565567, 1.860385, 2.430267",\ + "1.437420, 1.620241, 1.802983, 2.097801, 2.667683",\ + "2.009078, 2.191900, 2.374642, 2.669460, 3.239341"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637",\ + "0.032950, 0.032950, 0.032950, 0.032950, 0.032950",\ + "0.148290, 0.148290, 0.148290, 0.148290, 0.148290",\ + "0.376177, 0.376177, 0.376177, 0.376177, 0.376177",\ + "0.871096, 0.871096, 0.871096, 0.871096, 0.871096",\ + "2.136637, 2.136637, 2.136637, 2.136637, 2.136637"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.506490, 0.734939, 0.919745, 1.215248, 1.786338",\ + "0.532768, 0.761737, 0.946551, 1.242086, 1.813247",\ + "0.574154, 0.803122, 0.987937, 1.283471, 1.854632",\ + "0.696473, 0.925441, 1.110256, 1.405790, 1.976951",\ + "1.028706, 1.257674, 1.442488, 1.738023, 2.309184",\ + "0.594824, 0.822257, 1.007026, 1.302553, 1.873691",\ + "0.621100, 0.849055, 1.033832, 1.329391, 1.900600",\ + "0.662486, 0.890440, 1.075217, 1.370776, 1.941986",\ + "0.784805, 1.012759, 1.197537, 1.493095, 2.064305",\ + "1.117038, 1.344992, 1.529769, 1.825328, 2.396538",\ + "0.684045, 0.902590, 1.087053, 1.382582, 1.953723",\ + "0.710318, 0.929387, 1.113859, 1.409419, 1.980632",\ + "0.751704, 0.970773, 1.155244, 1.450805, 2.022017",\ + "0.874023, 1.093092, 1.277564, 1.573124, 2.144336",\ + "1.206255, 1.425324, 1.609796, 1.905357, 2.476569",\ + "0.747598, 0.960414, 1.144763, 1.440024, 2.010764",\ + "0.773868, 0.987212, 1.171569, 1.466862, 2.037673",\ + "0.815253, 1.028597, 1.212954, 1.508247, 2.079059",\ + "0.937573, 1.150916, 1.335273, 1.630566, 2.201378",\ + "1.269805, 1.483149, 1.667506, 1.962799, 2.533611",\ + "1.083412, 1.265686, 1.448421, 1.743207, 2.313017",\ + "1.109663, 1.292485, 1.475227, 1.770045, 2.339926",\ + "1.151049, 1.333870, 1.516612, 1.811430, 2.381312",\ + "1.273368, 1.456189, 1.638931, 1.933749, 2.503631",\ + "1.605601, 1.788422, 1.971164, 2.265982, 2.835864"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031",\ + "0.039649, 0.039649, 0.039649, 0.039649, 0.039649",\ + "0.089554, 0.089554, 0.089554, 0.089554, 0.089554",\ + "0.186013, 0.186013, 0.186013, 0.186013, 0.186013",\ + "0.432402, 0.432402, 0.432402, 0.432402, 0.432402",\ + "1.065031, 1.065031, 1.065031, 1.065031, 1.065031"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2733*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[40]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.434817, 0.671194, 0.861423, 1.166955, 1.757904",\ + "0.484677, 0.721055, 0.911284, 1.216816, 1.807764",\ + "0.586545, 0.822923, 1.013152, 1.318684, 1.909632",\ + "0.824407, 1.060784, 1.251013, 1.556545, 2.147494",\ + "1.396727, 1.633105, 1.823334, 2.128865, 2.719814",\ + "0.523312, 0.758513, 0.948704, 1.254260, 1.845257",\ + "0.573172, 0.808374, 0.998565, 1.304121, 1.895118",\ + "0.675041, 0.910242, 1.100433, 1.405989, 1.996986",\ + "0.912902, 1.148103, 1.338294, 1.643850, 2.234847",\ + "1.485222, 1.720423, 1.910614, 2.216170, 2.807168",\ + "0.612642, 0.838848, 1.028731, 1.334289, 1.925289",\ + "0.662503, 0.888709, 1.078592, 1.384149, 1.975149",\ + "0.764371, 0.990577, 1.180460, 1.486017, 2.077017",\ + "1.002232, 1.228438, 1.418321, 1.723879, 2.314878",\ + "1.574552, 1.800758, 1.990641, 2.296199, 2.887199",\ + "0.676136, 0.896683, 1.086453, 1.391755, 1.982376",\ + "0.725997, 0.946544, 1.136314, 1.441616, 2.032237",\ + "0.827865, 1.048412, 1.238182, 1.543484, 2.134105",\ + "1.065726, 1.286273, 1.476043, 1.781345, 2.371966",\ + "1.638046, 1.858593, 2.048363, 2.353665, 2.944287",\ + "1.011585, 1.202042, 1.390114, 1.694958, 2.284685",\ + "1.061446, 1.251903, 1.439975, 1.744819, 2.334546",\ + "1.163314, 1.353770, 1.541843, 1.846687, 2.436414",\ + "1.401175, 1.591632, 1.779704, 2.084548, 2.674275",\ + "1.973496, 2.163952, 2.352024, 2.656868, 3.246596"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039800, 0.039800, 0.039800, 0.039800, 0.039800",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.475545, 0.711923, 0.902152, 1.207684, 1.798632",\ + "0.497895, 0.734273, 0.924502, 1.230033, 1.820982",\ + "0.539258, 0.775636, 0.965865, 1.271397, 1.862345",\ + "0.661294, 0.897672, 1.087901, 1.393432, 1.984381",\ + "0.992907, 1.229285, 1.419514, 1.725045, 2.315994",\ + "0.564040, 0.799242, 0.989433, 1.294989, 1.885986",\ + "0.586390, 0.821591, 1.011783, 1.317338, 1.908335",\ + "0.627753, 0.862955, 1.053146, 1.358702, 1.949699",\ + "0.749789, 0.984990, 1.175182, 1.480737, 2.071735",\ + "1.081402, 1.316603, 1.506794, 1.812350, 2.403347",\ + "0.653370, 0.879577, 1.069460, 1.375017, 1.966017",\ + "0.675720, 0.901927, 1.091810, 1.397367, 1.988367",\ + "0.717084, 0.943290, 1.133173, 1.438730, 2.029730",\ + "0.839119, 1.065326, 1.255209, 1.560766, 2.151766",\ + "1.170732, 1.396938, 1.586821, 1.892379, 2.483379",\ + "0.716865, 0.937412, 1.127182, 1.432483, 2.023105",\ + "0.739214, 0.959762, 1.149531, 1.454833, 2.045455",\ + "0.780578, 1.001125, 1.190895, 1.496197, 2.086818",\ + "0.902614, 1.123161, 1.312930, 1.618232, 2.208854",\ + "1.234226, 1.454773, 1.644543, 1.949845, 2.540467",\ + "1.052314, 1.242770, 1.430842, 1.735687, 2.325414",\ + "1.074664, 1.265120, 1.453192, 1.758036, 2.347764",\ + "1.116027, 1.306484, 1.494555, 1.799400, 2.389127",\ + "1.238063, 1.428519, 1.616591, 1.921436, 2.511163",\ + "1.569676, 1.760132, 1.948204, 2.253048, 2.842776"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2365*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.415362, 0.648627, 0.834270, 1.134053, 1.714917",\ + "0.465223, 0.698488, 0.884131, 1.183914, 1.764778",\ + "0.567091, 0.800357, 0.985999, 1.285782, 1.866646",\ + "0.804953, 1.038218, 1.223860, 1.523643, 2.104508",\ + "1.377273, 1.610538, 1.796180, 2.095963, 2.676828",\ + "0.503768, 0.735946, 0.921550, 1.221358, 1.802271",\ + "0.553629, 0.785807, 0.971411, 1.271219, 1.852132",\ + "0.655497, 0.887675, 1.073280, 1.373087, 1.954000",\ + "0.893359, 1.125536, 1.311141, 1.610948, 2.191861",\ + "1.465679, 1.697857, 1.883461, 2.183269, 2.764181",\ + "0.592852, 0.816281, 1.001577, 1.301386, 1.882302",\ + "0.642713, 0.866142, 1.051438, 1.351248, 1.932163",\ + "0.744581, 0.968010, 1.153306, 1.453116, 2.034031",\ + "0.982442, 1.205871, 1.391168, 1.690977, 2.271893",\ + "1.554763, 1.778192, 1.963488, 2.263297, 2.844213",\ + "0.656124, 0.874112, 1.059288, 1.358840, 1.939366",\ + "0.705985, 0.923973, 1.109149, 1.408702, 1.989227",\ + "0.807853, 1.025841, 1.211017, 1.510570, 2.091095",\ + "1.045714, 1.263703, 1.448879, 1.748431, 2.328956",\ + "1.618035, 1.836023, 2.021199, 2.320751, 2.901277",\ + "0.990163, 1.179444, 1.362947, 1.662033, 2.241645",\ + "1.040024, 1.229305, 1.412809, 1.711895, 2.291506",\ + "1.141892, 1.331173, 1.514677, 1.813762, 2.393374",\ + "1.379753, 1.569034, 1.752538, 2.051624, 2.631236",\ + "1.952073, 2.141355, 2.324858, 2.623944, 3.203556"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202",\ + "0.039801, 0.039801, 0.039801, 0.039801, 0.039801",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375010, 0.375010, 0.375010, 0.375010, 0.375010",\ + "0.869309, 0.869309, 0.869309, 0.869309, 0.869309",\ + "2.137202, 2.137202, 2.137202, 2.137202, 2.137202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.456091, 0.689356, 0.874999, 1.174782, 1.755646",\ + "0.478441, 0.711706, 0.897348, 1.197132, 1.777996",\ + "0.519805, 0.753070, 0.938712, 1.238495, 1.819360",\ + "0.641840, 0.875105, 1.060748, 1.360531, 1.941395",\ + "0.973453, 1.206718, 1.392360, 1.692143, 2.273008",\ + "0.544497, 0.776675, 0.962279, 1.262087, 1.843000",\ + "0.566847, 0.799025, 0.984629, 1.284437, 1.865350",\ + "0.608211, 0.840388, 1.025993, 1.325800, 1.906713",\ + "0.730246, 0.962424, 1.148028, 1.447836, 2.028749",\ + "1.061859, 1.294037, 1.479641, 1.779449, 2.360361",\ + "0.633581, 0.857010, 1.042306, 1.342116, 1.923031",\ + "0.655931, 0.879360, 1.064656, 1.364465, 1.945381",\ + "0.697294, 0.920723, 1.106020, 1.405829, 1.986745",\ + "0.819330, 1.042759, 1.228055, 1.527864, 2.108780",\ + "1.150943, 1.374372, 1.559668, 1.859477, 2.440393",\ + "0.696853, 0.914841, 1.100017, 1.399570, 1.980095",\ + "0.719203, 0.937191, 1.122367, 1.421919, 2.002445",\ + "0.760566, 0.978555, 1.163731, 1.463283, 2.043808",\ + "0.882602, 1.100590, 1.285766, 1.585318, 2.165844",\ + "1.214215, 1.432203, 1.617379, 1.916931, 2.497457",\ + "1.030892, 1.220173, 1.403677, 1.702762, 2.282374",\ + "1.053242, 1.242523, 1.426026, 1.725112, 2.304724",\ + "1.094605, 1.283886, 1.467390, 1.766476, 2.346087",\ + "1.216641, 1.405922, 1.589425, 1.888511, 2.468123",\ + "1.548254, 1.737535, 1.921038, 2.220124, 2.799736"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[4]_redg_min_2479*/ + +} /* end of pin tl_o[4] */ + +pin("tl_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.034401 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.510374, 0.770025, 1.057985, 1.558099, 2.558328",\ + "0.560483, 0.820133, 1.108094, 1.608212, 2.608449",\ + "0.649192, 0.908842, 1.196806, 1.696939, 2.697205",\ + "0.873358, 1.133008, 1.420973, 1.921111, 2.921387",\ + "1.425993, 1.685643, 1.973609, 2.473750, 3.474032",\ + "0.597787, 0.857587, 1.145651, 1.644814, 2.644262",\ + "0.647895, 0.907696, 1.195760, 1.694927, 2.694383",\ + "0.736605, 0.996405, 1.284473, 1.783654, 2.783139",\ + "0.960770, 1.220570, 1.508639, 2.007826, 3.007321",\ + "1.513405, 1.773205, 2.061275, 2.560465, 3.559966",\ + "0.678684, 0.946606, 1.233617, 1.732436, 2.731217",\ + "0.728793, 0.996715, 1.283726, 1.782550, 2.781338",\ + "0.817502, 1.085424, 1.372439, 1.871277, 2.870094",\ + "1.041668, 1.309589, 1.596606, 2.095448, 3.094276",\ + "1.594303, 1.862224, 2.149241, 2.648087, 3.646921",\ + "0.738268, 1.012297, 1.297762, 1.796350, 2.794726",\ + "0.788377, 1.062406, 1.347871, 1.846463, 2.844847",\ + "0.877086, 1.151115, 1.436584, 1.935190, 2.933603",\ + "1.101252, 1.375280, 1.660750, 2.159362, 3.157785",\ + "1.653887, 1.927915, 2.213386, 2.712001, 3.710430",\ + "1.071814, 1.377311, 1.649946, 2.145828, 3.140182",\ + "1.121922, 1.427420, 1.700056, 2.195941, 3.190303",\ + "1.210632, 1.516129, 1.788768, 2.284668, 3.279059",\ + "1.434798, 1.740294, 2.012935, 2.508840, 3.503241",\ + "1.987432, 2.292929, 2.565571, 3.061479, 4.055886"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\ + "2.185958, 2.185963, 2.186002, 2.186108, 2.186319",\ + "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\ + "2.185958, 2.185964, 2.186003, 2.186108, 2.186319",\ + "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\ + "2.185958, 2.185964, 2.186003, 2.186108, 2.186319",\ + "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324733, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855427, 0.855504, 0.855712, 0.856129",\ + "2.185958, 2.185964, 2.186003, 2.186108, 2.186319",\ + "0.046974, 0.046974, 0.046974, 0.046974, 0.046974",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324731, 0.324734, 0.324746, 0.324779, 0.324846",\ + "0.855415, 0.855432, 0.855507, 0.855713, 0.856129",\ + "2.185958, 2.185966, 2.186004, 2.186108, 2.186319"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.546335, 0.805984, 1.093953, 1.594109, 2.594421",\ + "0.568030, 0.827679, 1.115650, 1.615810, 2.616129",\ + "0.609553, 0.869202, 1.157173, 1.657335, 2.657660",\ + "0.742836, 1.002485, 1.290455, 1.790615, 2.790934",\ + "1.091714, 1.351363, 1.639332, 2.139487, 3.139795",\ + "0.633748, 0.893546, 1.181620, 1.680824, 2.680355",\ + "0.655443, 0.915241, 1.203316, 1.702524, 2.702063",\ + "0.696966, 0.956764, 1.244839, 1.744050, 2.743593",\ + "0.830248, 1.090047, 1.378121, 1.877330, 2.876868",\ + "1.179126, 1.438925, 1.726998, 2.226201, 3.225729",\ + "0.714645, 0.982566, 1.269586, 1.768446, 2.767310",\ + "0.736340, 1.004261, 1.291282, 1.790147, 2.789018",\ + "0.777863, 1.045783, 1.332805, 1.831672, 2.830549",\ + "0.911146, 1.179066, 1.466088, 1.964952, 2.963823",\ + "1.260024, 1.527944, 1.814965, 2.313824, 3.312684",\ + "0.774229, 1.048256, 1.333731, 1.832360, 2.830819",\ + "0.795924, 1.069952, 1.355427, 1.854060, 2.852527",\ + "0.837447, 1.111474, 1.396950, 1.895586, 2.894058",\ + "0.970730, 1.244757, 1.530232, 2.028866, 3.027332",\ + "1.319608, 1.593635, 1.879110, 2.377737, 3.376193",\ + "1.107775, 1.413270, 1.685916, 2.181838, 3.176275",\ + "1.129470, 1.434965, 1.707612, 2.203538, 3.197983",\ + "1.170993, 1.476488, 1.749135, 2.245064, 3.239513",\ + "1.304275, 1.609771, 1.882417, 2.378344, 3.372788",\ + "1.653153, 1.958649, 2.231294, 2.727215, 3.721649"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.045624, 0.045624, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\ + "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\ + "0.045624, 0.045624, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\ + "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\ + "0.045624, 0.045624, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\ + "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\ + "0.045624, 0.045625, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455143, 0.455182, 0.455287, 0.455497",\ + "1.170722, 1.170724, 1.170739, 1.170779, 1.170860",\ + "0.045624, 0.045625, 0.045626, 0.045626, 0.045626",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171713, 0.171715, 0.171723, 0.171737",\ + "0.455137, 0.455145, 0.455183, 0.455287, 0.455497",\ + "1.170722, 1.170725, 1.170740, 1.170779, 1.170860"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2748*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.491611, 0.745113, 1.023814, 1.485459, 2.408749",\ + "0.541720, 0.795222, 1.073923, 1.535570, 2.458864",\ + "0.630429, 0.883931, 1.162634, 1.624290, 2.547600",\ + "0.854595, 1.108097, 1.386801, 1.848459, 2.771775",\ + "1.407230, 1.660732, 1.939436, 2.401096, 3.324415",\ + "0.579020, 0.832694, 1.111357, 1.572173, 2.494682",\ + "0.629129, 0.882803, 1.161466, 1.622284, 2.544798",\ + "0.717839, 0.971512, 1.250178, 1.711004, 2.633534",\ + "0.942004, 1.195678, 1.474344, 1.935173, 2.857708",\ + "1.494639, 1.748312, 2.026979, 2.487810, 3.410349",\ + "0.659835, 0.921740, 1.199320, 1.659795, 2.581637",\ + "0.709944, 0.971848, 1.249429, 1.709906, 2.631753",\ + "0.798653, 1.060558, 1.338141, 1.798626, 2.720489",\ + "1.022819, 1.284723, 1.562307, 2.022795, 2.944664",\ + "1.575454, 1.837358, 2.114943, 2.575432, 3.497304",\ + "0.717415, 0.987469, 1.263459, 1.723708, 2.645146",\ + "0.767524, 1.037577, 1.313568, 1.773819, 2.695262",\ + "0.856233, 1.126287, 1.402279, 1.862539, 2.783998",\ + "1.080399, 1.350452, 1.626446, 2.086708, 3.008173",\ + "1.633034, 1.903087, 2.179081, 2.639345, 3.560813",\ + "1.049306, 1.352971, 1.615251, 2.073024, 2.990602",\ + "1.099415, 1.403079, 1.665360, 2.123135, 3.040718",\ + "1.188124, 1.491788, 1.754072, 2.211854, 3.129454",\ + "1.412290, 1.715954, 1.978238, 2.436024, 3.353629",\ + "1.964925, 2.268589, 2.530873, 2.988661, 3.906269"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\ + "2.185958, 2.185959, 2.185984, 2.186066, 2.186228",\ + "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\ + "2.185958, 2.185959, 2.185985, 2.186066, 2.186228",\ + "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\ + "2.185958, 2.185959, 2.185985, 2.186066, 2.186228",\ + "0.046974, 0.046972, 0.046943, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855418, 0.855468, 0.855628, 0.855950",\ + "2.185958, 2.185959, 2.185985, 2.186066, 2.186228",\ + "0.046974, 0.046972, 0.046942, 0.046848, 0.046659",\ + "0.140333, 0.140333, 0.140330, 0.140323, 0.140308",\ + "0.324732, 0.324732, 0.324740, 0.324766, 0.324817",\ + "0.855415, 0.855419, 0.855470, 0.855629, 0.855950",\ + "2.185958, 2.185960, 2.185985, 2.186066, 2.186228"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.527572, 0.781074, 1.059780, 1.521448, 2.444784",\ + "0.549267, 0.802769, 1.081476, 1.543146, 2.466486",\ + "0.590790, 0.844292, 1.122999, 1.584671, 2.508013",\ + "0.724072, 0.977574, 1.256281, 1.717952, 2.641292",\ + "1.072951, 1.326452, 1.605159, 2.066826, 2.990160",\ + "0.614981, 0.868654, 1.147323, 1.608162, 2.530717",\ + "0.636677, 0.890350, 1.169019, 1.629860, 2.552420",\ + "0.678199, 0.931872, 1.210542, 1.671385, 2.593947",\ + "0.811482, 1.065155, 1.343825, 1.804666, 2.727225",\ + "1.160360, 1.414033, 1.692702, 2.153540, 3.076094",\ + "0.695796, 0.957700, 1.235286, 1.695784, 2.617672",\ + "0.717491, 0.979395, 1.256982, 1.717482, 2.639375",\ + "0.759014, 1.020918, 1.298506, 1.759007, 2.680902",\ + "0.892296, 1.154201, 1.431788, 1.892287, 2.814180",\ + "1.241175, 1.503079, 1.780665, 2.241162, 3.163049",\ + "0.753376, 1.023429, 1.299425, 1.759697, 2.681181",\ + "0.775071, 1.045124, 1.321121, 1.781395, 2.702884",\ + "0.816594, 1.086647, 1.362644, 1.822920, 2.744411",\ + "0.949877, 1.219929, 1.495926, 1.956201, 2.877689",\ + "1.298755, 1.568808, 1.844804, 2.305075, 3.226558",\ + "1.085267, 1.388931, 1.651218, 2.109013, 3.026638",\ + "1.106962, 1.410626, 1.672914, 2.130711, 3.048340",\ + "1.148485, 1.452149, 1.714437, 2.172235, 3.089867",\ + "1.281768, 1.585431, 1.847719, 2.305516, 3.223145",\ + "1.630646, 1.934309, 2.196596, 2.654391, 3.572014"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455138, 0.455163, 0.455244, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\ + "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455138, 0.455164, 0.455244, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\ + "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455138, 0.455164, 0.455244, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\ + "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455138, 0.455164, 0.455244, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825",\ + "0.045624, 0.045624, 0.045624, 0.045624, 0.045624",\ + "0.082731, 0.082731, 0.082731, 0.082731, 0.082731",\ + "0.171712, 0.171712, 0.171714, 0.171720, 0.171731",\ + "0.455137, 0.455139, 0.455164, 0.455245, 0.455407",\ + "1.170722, 1.170722, 1.170732, 1.170763, 1.170825"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2324*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.570251, 0.828412, 1.116558, 1.622590, 2.634653",\ + "0.620360, 0.878521, 1.166668, 1.672702, 2.684771",\ + "0.709070, 0.967232, 1.255383, 1.761428, 2.773518",\ + "0.933236, 1.191399, 1.479551, 1.985599, 2.997696",\ + "1.485871, 1.744034, 2.032187, 2.538238, 3.550339",\ + "0.657660, 0.915972, 1.204241, 1.709304, 2.720587",\ + "0.707769, 0.966081, 1.254351, 1.759417, 2.770705",\ + "0.796479, 1.054792, 1.343066, 1.848142, 2.859451",\ + "1.020645, 1.278959, 1.567234, 2.072314, 3.083630",\ + "1.573280, 1.831594, 2.119870, 2.624952, 3.636273",\ + "0.738545, 1.004968, 1.292206, 1.796926, 2.807542",\ + "0.788654, 1.055077, 1.342316, 1.847038, 2.857660",\ + "0.877364, 1.143789, 1.431032, 1.935764, 2.946406",\ + "1.101530, 1.367955, 1.655199, 2.159935, 3.170585",\ + "1.654165, 1.920590, 2.207835, 2.712574, 3.723228",\ + "0.799029, 1.070625, 1.356352, 1.860839, 2.871051",\ + "0.849138, 1.120734, 1.406462, 1.910952, 2.921169",\ + "0.937848, 1.209445, 1.495178, 1.999677, 3.009915",\ + "1.162014, 1.433611, 1.719345, 2.223849, 3.234094",\ + "1.714649, 1.986246, 2.271981, 2.776487, 3.786737",\ + "1.134610, 1.435289, 1.708595, 2.210337, 3.216507",\ + "1.184719, 1.485398, 1.758705, 2.260450, 3.266625",\ + "1.273429, 1.574110, 1.847420, 2.349176, 3.355371",\ + "1.497595, 1.798276, 2.071588, 2.573347, 3.579550",\ + "2.050230, 2.350911, 2.624224, 3.125986, 4.132193"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\ + "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\ + "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\ + "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\ + "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\ + "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\ + "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855431, 0.855470, 0.855580, 0.855800",\ + "2.185963, 2.185966, 2.185986, 2.186041, 2.186152",\ + "0.046967, 0.046968, 0.046968, 0.046968, 0.046968",\ + "0.140332, 0.140332, 0.140332, 0.140332, 0.140332",\ + "0.324733, 0.324734, 0.324740, 0.324758, 0.324793",\ + "0.855426, 0.855433, 0.855471, 0.855580, 0.855800",\ + "2.185963, 2.185967, 2.185986, 2.186041, 2.186152"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.606214, 0.864377, 1.152534, 1.658596, 2.670718",\ + "0.627909, 0.886073, 1.174231, 1.680295, 2.692423",\ + "0.669432, 0.927596, 1.215755, 1.721821, 2.733952",\ + "0.802715, 1.060879, 1.349037, 1.855101, 2.867229",\ + "1.151593, 1.409756, 1.697913, 2.203973, 3.216093",\ + "0.693623, 0.951938, 1.240217, 1.745310, 2.756651",\ + "0.715318, 0.973633, 1.261914, 1.767010, 2.778357",\ + "0.756841, 1.015157, 1.303438, 1.808535, 2.819886",\ + "0.890124, 1.148439, 1.436720, 1.941815, 2.953162",\ + "1.239002, 1.497316, 1.785596, 2.290687, 3.302027",\ + "0.774507, 1.040934, 1.328183, 1.832932, 2.843606",\ + "0.796203, 1.062629, 1.349880, 1.854631, 2.865312",\ + "0.837726, 1.104153, 1.391404, 1.896157, 2.906841",\ + "0.971008, 1.237435, 1.524685, 2.029437, 3.040117",\ + "1.319886, 1.586312, 1.873561, 2.378309, 3.388982",\ + "0.834992, 1.106590, 1.392329, 1.896845, 2.907115",\ + "0.856687, 1.128286, 1.414026, 1.918545, 2.928821",\ + "0.898210, 1.169809, 1.455549, 1.960070, 2.970350",\ + "1.031493, 1.303092, 1.588831, 2.093350, 3.103626",\ + "1.380370, 1.651969, 1.937707, 2.442222, 3.452491",\ + "1.170573, 1.471255, 1.744571, 2.246343, 3.252572",\ + "1.192269, 1.492951, 1.766268, 2.268043, 3.274277",\ + "1.233792, 1.534474, 1.807792, 2.309569, 3.315806",\ + "1.367074, 1.667757, 1.941074, 2.442849, 3.449082",\ + "1.715952, 2.016634, 2.289950, 2.791721, 3.797947"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\ + "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\ + "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\ + "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455145, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170732, 1.170754, 1.170796",\ + "0.045622, 0.045622, 0.045622, 0.045622, 0.045622",\ + "0.082730, 0.082730, 0.082730, 0.082730, 0.082730",\ + "0.171713, 0.171713, 0.171714, 0.171718, 0.171726",\ + "0.455143, 0.455146, 0.455165, 0.455220, 0.455331",\ + "1.170724, 1.170725, 1.170733, 1.170754, 1.170796"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2270*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.553742, 0.804842, 1.083529, 1.550229, 2.483630",\ + "0.603850, 0.854951, 1.133639, 1.600341, 2.533747",\ + "0.692561, 0.943663, 1.222354, 1.689065, 2.622488",\ + "0.916727, 1.167829, 1.446522, 1.913236, 2.846664",\ + "1.469362, 1.720464, 1.999158, 2.465874, 3.399306",\ + "0.641147, 0.892423, 1.171086, 1.636943, 2.569564",\ + "0.691255, 0.942532, 1.221196, 1.687055, 2.619680",\ + "0.779966, 1.031244, 1.309911, 1.775779, 2.708421",\ + "1.004132, 1.255410, 1.534079, 1.999949, 2.932598",\ + "1.556767, 1.808045, 2.086715, 2.552587, 3.485240",\ + "0.721960, 0.981448, 1.259048, 1.724564, 2.656519",\ + "0.772069, 1.031557, 1.309159, 1.774676, 2.706635",\ + "0.860779, 1.120269, 1.397874, 1.863400, 2.795376",\ + "1.084945, 1.344435, 1.622041, 2.087571, 3.019553",\ + "1.637580, 1.897070, 2.174678, 2.640208, 3.572195",\ + "0.779579, 1.047145, 1.323188, 1.788477, 2.720028",\ + "0.829687, 1.097255, 1.373298, 1.838589, 2.770144",\ + "0.918398, 1.185966, 1.462013, 1.927313, 2.858885",\ + "1.142564, 1.410133, 1.686181, 2.151483, 3.083062",\ + "1.695199, 1.962768, 2.238817, 2.704121, 3.635704",\ + "1.113274, 1.412343, 1.675029, 2.137809, 3.065484",\ + "1.163383, 1.462452, 1.725139, 2.187922, 3.115601",\ + "1.252093, 1.551164, 1.813854, 2.276645, 3.204341",\ + "1.476259, 1.775330, 2.038022, 2.500816, 3.428518",\ + "2.028894, 2.327965, 2.590658, 3.053454, 3.981160"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\ + "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\ + "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\ + "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855457, 0.855540, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105",\ + "0.046966, 0.046965, 0.046949, 0.046900, 0.046802",\ + "0.140332, 0.140332, 0.140331, 0.140327, 0.140319",\ + "0.324733, 0.324734, 0.324738, 0.324752, 0.324778",\ + "0.855428, 0.855430, 0.855458, 0.855541, 0.855707",\ + "2.185964, 2.185965, 2.185979, 2.186021, 2.186105"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.589705, 0.840809, 1.119505, 1.586230, 2.519679",\ + "0.611400, 0.862504, 1.141202, 1.607929, 2.541383",\ + "0.652923, 0.904028, 1.182726, 1.649454, 2.582911",\ + "0.786206, 1.037310, 1.316008, 1.782735, 2.716188",\ + "1.135083, 1.386187, 1.664884, 2.131607, 3.065055",\ + "0.677110, 0.928390, 1.207063, 1.672943, 2.605613",\ + "0.698805, 0.950085, 1.228760, 1.694643, 2.627316",\ + "0.740328, 0.991609, 1.270283, 1.736168, 2.668845",\ + "0.873611, 1.124891, 1.403565, 1.869448, 2.802122",\ + "1.222489, 1.473768, 1.752441, 2.218321, 3.150989",\ + "0.757923, 1.017414, 1.295025, 1.760565, 2.692568",\ + "0.779619, 1.039110, 1.316722, 1.782264, 2.714272",\ + "0.821142, 1.080633, 1.358246, 1.823789, 2.755800",\ + "0.954424, 1.213916, 1.491528, 1.957069, 2.889077",\ + "1.303302, 1.562793, 1.840404, 2.305942, 3.237944",\ + "0.815542, 1.083112, 1.359165, 1.824477, 2.756077",\ + "0.837237, 1.104808, 1.380862, 1.846177, 2.777781",\ + "0.878760, 1.146331, 1.422385, 1.887702, 2.819309",\ + "1.012043, 1.279613, 1.555667, 2.020982, 2.952586",\ + "1.360920, 1.628491, 1.904543, 2.369855, 3.301453",\ + "1.149238, 1.448310, 1.711006, 2.173810, 3.101533",\ + "1.170933, 1.470006, 1.732703, 2.195509, 3.123237",\ + "1.212456, 1.511529, 1.774227, 2.237035, 3.164765",\ + "1.345739, 1.644811, 1.907508, 2.370315, 3.298042",\ + "1.694616, 1.993689, 2.256384, 2.719187, 3.646909"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\ + "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\ + "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\ + "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455144, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779",\ + "0.045622, 0.045620, 0.045614, 0.045600, 0.045572",\ + "0.082730, 0.082730, 0.082728, 0.082724, 0.082717",\ + "0.171713, 0.171713, 0.171714, 0.171717, 0.171723",\ + "0.455143, 0.455145, 0.455158, 0.455200, 0.455284",\ + "1.170724, 1.170725, 1.170730, 1.170746, 1.170779"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2356*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.451072, 0.689495, 0.967641, 1.455853, 2.432276",\ + "0.493930, 0.732354, 1.010260, 1.497643, 2.472409",\ + "0.570383, 0.808808, 1.086665, 1.573880, 2.548310",\ + "0.793657, 1.032083, 1.309620, 1.795731, 2.767951",\ + "1.356346, 1.594772, 1.872207, 2.357962, 3.329473",\ + "0.538482, 0.777023, 1.055268, 1.542567, 2.518210",\ + "0.581340, 0.819882, 1.097884, 1.584358, 2.558343",\ + "0.657793, 0.896336, 1.174289, 1.660595, 2.634244",\ + "0.881067, 1.119611, 1.397241, 1.882445, 2.853885",\ + "1.443756, 1.682300, 1.959826, 2.444677, 3.415407",\ + "0.619344, 0.865949, 1.143233, 1.630189, 2.605165",\ + "0.662202, 0.908808, 1.185849, 1.671979, 2.645298",\ + "0.738655, 0.985262, 1.262254, 1.748217, 2.721199",\ + "0.961929, 1.208537, 1.485206, 1.970067, 2.940840",\ + "1.524618, 1.771226, 2.047791, 2.532299, 3.502362",\ + "0.677016, 0.931504, 1.207376, 1.694102, 2.668674",\ + "0.719874, 0.974362, 1.249992, 1.735892, 2.708807",\ + "0.796327, 1.050816, 1.326397, 1.812130, 2.784708",\ + "1.019601, 1.274091, 1.549348, 2.033980, 3.004349",\ + "1.582290, 1.836781, 2.111933, 2.596212, 3.565871",\ + "0.998045, 1.294967, 1.559438, 2.043528, 3.014130",\ + "1.040903, 1.337826, 1.602045, 2.085314, 3.054263",\ + "1.117357, 1.414280, 1.678448, 2.161551, 3.130164",\ + "1.340631, 1.637555, 1.901389, 2.383397, 3.349805",\ + "1.903320, 2.200244, 2.463970, 2.945627, 3.911327"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\ + "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\ + "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\ + "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891",\ + "0.072525, 0.072525, 0.072525, 0.072525, 0.072526",\ + "0.151107, 0.151107, 0.151107, 0.151107, 0.151107",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855550, 0.855550, 0.855550, 0.855551",\ + "2.186890, 2.186890, 2.186890, 2.186890, 2.186891"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.463085, 0.701506, 0.978942, 1.464699, 2.436214",\ + "0.490745, 0.729166, 1.006601, 1.492359, 2.463874",\ + "0.539949, 0.778370, 1.055805, 1.541563, 2.513078",\ + "0.680533, 0.918956, 1.196391, 1.682148, 2.653661",\ + "1.033170, 1.271589, 1.549246, 2.035768, 3.008812",\ + "0.550495, 0.789034, 1.066561, 1.551413, 2.522148",\ + "0.578155, 0.816694, 1.094220, 1.579073, 2.549807",\ + "0.627359, 0.865897, 1.143424, 1.628277, 2.599012",\ + "0.767943, 1.006484, 1.284010, 1.768862, 2.739595",\ + "1.120580, 1.359117, 1.636868, 2.122482, 3.094745",\ + "0.631357, 0.877960, 1.154525, 1.639035, 2.609103",\ + "0.659017, 0.905619, 1.182185, 1.666695, 2.636762",\ + "0.708221, 0.954823, 1.231389, 1.715899, 2.685967",\ + "0.848805, 1.095410, 1.371975, 1.856484, 2.826550",\ + "1.201442, 1.448043, 1.724832, 2.210104, 3.181700",\ + "0.689029, 0.943515, 1.218668, 1.702948, 2.672612",\ + "0.716689, 0.971174, 1.246328, 1.730608, 2.700271",\ + "0.765893, 1.020378, 1.295531, 1.779812, 2.749476",\ + "0.906477, 1.160964, 1.436117, 1.920397, 2.890059",\ + "1.259114, 1.513598, 1.788975, 2.274017, 3.245209",\ + "1.010056, 1.306978, 1.570705, 2.052364, 3.018068",\ + "1.037716, 1.334638, 1.598365, 2.080023, 3.045727",\ + "1.086920, 1.383842, 1.647568, 2.129227, 3.094932",\ + "1.227505, 1.524428, 1.788154, 2.269813, 3.235515",\ + "1.580140, 1.877061, 2.141020, 2.623435, 3.590666"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.031044, 0.031047, 0.031141, 0.031458, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\ + "0.031044, 0.031047, 0.031142, 0.031458, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\ + "0.031044, 0.031047, 0.031142, 0.031458, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\ + "0.031044, 0.031047, 0.031142, 0.031458, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169261, 1.169280, 1.169343, 1.169468",\ + "0.031045, 0.031048, 0.031146, 0.031459, 0.032092",\ + "0.078404, 0.078404, 0.078413, 0.078441, 0.078497",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169261, 1.169262, 1.169281, 1.169343, 1.169468"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2423*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.549373, 0.808602, 1.094677, 1.588458, 2.576021",\ + "0.599470, 0.858699, 1.144772, 1.638553, 2.626115",\ + "0.688134, 0.947361, 1.233431, 1.727210, 2.714768",\ + "0.912284, 1.171509, 1.457578, 1.951357, 2.938914",\ + "1.464909, 1.724133, 2.010202, 2.503980, 3.491537",\ + "0.636786, 0.896164, 1.182323, 1.675173, 2.661954",\ + "0.686883, 0.946261, 1.232418, 1.725268, 2.712049",\ + "0.775547, 1.034922, 1.321077, 1.813925, 2.800702",\ + "0.999696, 1.259071, 1.545225, 2.038072, 3.024848",\ + "1.552321, 1.811695, 2.097848, 2.590695, 3.577471",\ + "0.717681, 0.985182, 1.270288, 1.762795, 2.748909",\ + "0.767778, 1.035279, 1.320384, 1.812890, 2.799004",\ + "0.856442, 1.123940, 1.409043, 1.901547, 2.887657",\ + "1.080592, 1.348089, 1.633190, 2.125694, 3.111803",\ + "1.633216, 1.900714, 2.185814, 2.678318, 3.664426",\ + "0.777205, 1.050872, 1.334432, 1.826709, 2.812418",\ + "0.827302, 1.100968, 1.384528, 1.876804, 2.862513",\ + "0.915966, 1.189630, 1.473186, 1.965461, 2.951166",\ + "1.140115, 1.413779, 1.697334, 2.189608, 3.175312",\ + "1.692740, 1.966403, 2.249958, 2.742231, 3.727935",\ + "1.110638, 1.415870, 1.686553, 2.176160, 3.157875",\ + "1.160735, 1.465966, 1.736648, 2.226255, 3.207969",\ + "1.249399, 1.554628, 1.825307, 2.314913, 3.296622",\ + "1.473549, 1.778776, 2.049454, 2.539060, 3.520768",\ + "2.026173, 2.331400, 2.602078, 3.091683, 4.073391"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855404, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\ + "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855404, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\ + "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855404, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\ + "0.046980, 0.046981, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140333, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855405, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970",\ + "0.046980, 0.046982, 0.046983, 0.046983, 0.046983",\ + "0.140333, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324730, 0.324730, 0.324730, 0.324732, 0.324735",\ + "0.855405, 0.855405, 0.855408, 0.855419, 0.855440",\ + "2.185952, 2.185953, 2.185954, 2.185960, 2.185970"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.585206, 0.844429, 1.130494, 1.624271, 2.611824",\ + "0.606889, 0.866111, 1.152175, 1.645951, 2.633503",\ + "0.648404, 0.907626, 1.193689, 1.687465, 2.675017",\ + "0.781694, 1.040916, 1.326981, 1.820757, 2.808309",\ + "1.130589, 1.389812, 1.675878, 2.169654, 3.157208",\ + "0.672619, 0.931991, 1.218140, 1.710986, 2.697757",\ + "0.694301, 0.953673, 1.239821, 1.732666, 2.719437",\ + "0.735816, 0.995187, 1.281336, 1.774180, 2.760951",\ + "0.869107, 1.128478, 1.414627, 1.907472, 2.894243",\ + "1.218002, 1.477374, 1.763524, 2.256369, 3.243142",\ + "0.753514, 1.021009, 1.306106, 1.798608, 2.784713",\ + "0.775196, 1.042691, 1.327787, 1.820288, 2.806392",\ + "0.816712, 1.084206, 1.369301, 1.861803, 2.847906",\ + "0.950002, 1.217496, 1.502593, 1.995094, 2.981198",\ + "1.298897, 1.566392, 1.851490, 2.343992, 3.330097",\ + "0.813038, 1.086698, 1.370250, 1.862521, 2.848222",\ + "0.834720, 1.108380, 1.391931, 1.884202, 2.869901",\ + "0.876235, 1.149895, 1.433445, 1.925716, 2.911415",\ + "1.009526, 1.283186, 1.566736, 2.059008, 3.044707",\ + "1.358421, 1.632081, 1.915633, 2.407905, 3.393606",\ + "1.146470, 1.451694, 1.722370, 2.211973, 3.193677",\ + "1.168153, 1.473376, 1.744051, 2.233654, 3.215357",\ + "1.209668, 1.514891, 1.785565, 2.275168, 3.256871",\ + "1.342959, 1.648182, 1.918857, 2.408459, 3.390163",\ + "1.691854, 1.997078, 2.267754, 2.757357, 3.739062"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\ + "0.082751, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\ + "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\ + "0.082751, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\ + "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\ + "0.082751, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\ + "0.045699, 0.045703, 0.045708, 0.045711, 0.045717",\ + "0.082752, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727",\ + "0.045700, 0.045704, 0.045708, 0.045711, 0.045717",\ + "0.082752, 0.082753, 0.082754, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171713",\ + "0.455132, 0.455132, 0.455133, 0.455139, 0.455149",\ + "1.170720, 1.170720, 1.170720, 1.170722, 1.170727"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2482*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.531759, 0.784650, 1.063366, 1.526559, 2.452945",\ + "0.581856, 0.834746, 1.113461, 1.576654, 2.503039",\ + "0.670520, 0.923407, 1.202119, 1.665310, 2.591694",\ + "0.894669, 1.147555, 1.426266, 1.889457, 2.815840",\ + "1.447294, 1.700179, 1.978889, 2.442080, 3.368464",\ + "0.619167, 0.872231, 1.150913, 1.613273, 2.538878",\ + "0.669264, 0.922327, 1.201009, 1.663368, 2.588973",\ + "0.757928, 1.010988, 1.289666, 1.752025, 2.677628",\ + "0.982077, 1.235136, 1.513813, 1.976171, 2.901774",\ + "1.534702, 1.787760, 2.066437, 2.528795, 3.454397",\ + "0.699981, 0.961270, 1.238877, 1.700895, 2.625834",\ + "0.750078, 1.011366, 1.288972, 1.750990, 2.675928",\ + "0.838742, 1.100027, 1.377629, 1.839646, 2.764583",\ + "1.062892, 1.324176, 1.601776, 2.063793, 2.988729",\ + "1.615517, 1.876800, 2.154400, 2.616416, 3.541352",\ + "0.757572, 1.026990, 1.303015, 1.764808, 2.689342",\ + "0.807669, 1.077086, 1.353110, 1.814903, 2.739437",\ + "0.896333, 1.165747, 1.441768, 1.903559, 2.828092",\ + "1.120482, 1.389895, 1.665915, 2.127706, 3.052238",\ + "1.673107, 1.942519, 2.218538, 2.680329, 3.604861",\ + "1.090182, 1.392406, 1.654823, 2.114129, 3.034798",\ + "1.140279, 1.442501, 1.704918, 2.164223, 3.084893",\ + "1.228943, 1.531161, 1.793575, 2.252880, 3.173548",\ + "1.453092, 1.755309, 2.017722, 2.477027, 3.397694",\ + "2.005717, 2.307933, 2.570345, 3.029650, 3.950317"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\ + "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\ + "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\ + "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855405, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959",\ + "0.046980, 0.046980, 0.046980, 0.046980, 0.046980",\ + "0.140333, 0.140333, 0.140333, 0.140333, 0.140333",\ + "0.324730, 0.324730, 0.324730, 0.324731, 0.324732",\ + "0.855404, 0.855404, 0.855406, 0.855410, 0.855418",\ + "2.185952, 2.185952, 2.185953, 2.185955, 2.185959"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.567591, 0.820473, 1.099180, 1.562370, 2.488752",\ + "0.589274, 0.842155, 1.120860, 1.584051, 2.510432",\ + "0.630789, 0.883670, 1.162374, 1.625565, 2.551946",\ + "0.764080, 1.016961, 1.295666, 1.758857, 2.685237",\ + "1.112975, 1.365857, 1.644563, 2.107754, 3.034136",\ + "0.655000, 0.908054, 1.186727, 1.649085, 2.574686",\ + "0.676682, 0.929736, 1.208408, 1.670765, 2.596366",\ + "0.718198, 0.971251, 1.249922, 1.712279, 2.637879",\ + "0.851488, 1.104542, 1.383214, 1.845571, 2.771171",\ + "1.200383, 1.453438, 1.732111, 2.194468, 3.120070",\ + "0.735814, 0.997094, 1.274690, 1.736706, 2.661641",\ + "0.757496, 1.018775, 1.296371, 1.758387, 2.683321",\ + "0.799012, 1.060290, 1.337885, 1.799901, 2.724834",\ + "0.932302, 1.193581, 1.471177, 1.933192, 2.858126",\ + "1.281197, 1.542477, 1.820074, 2.282090, 3.207025",\ + "0.793404, 1.062813, 1.338829, 1.800619, 2.725150",\ + "0.815087, 1.084495, 1.360510, 1.822300, 2.746830",\ + "0.856602, 1.126010, 1.402024, 1.863814, 2.788343",\ + "0.989893, 1.259301, 1.535315, 1.997105, 2.921635",\ + "1.338787, 1.608197, 1.884213, 2.346003, 3.270534",\ + "1.126013, 1.428226, 1.690636, 2.149940, 3.070606",\ + "1.147696, 1.449908, 1.712317, 2.171620, 3.092286",\ + "1.189211, 1.491422, 1.753831, 2.213135, 3.133800",\ + "1.322502, 1.624713, 1.887123, 2.346426, 3.267091",\ + "1.671397, 1.973610, 2.236020, 2.695324, 3.615990"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\ + "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\ + "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\ + "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\ + "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\ + "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\ + "0.045699, 0.045705, 0.045710, 0.045712, 0.045714",\ + "0.082751, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722",\ + "0.045700, 0.045706, 0.045710, 0.045712, 0.045714",\ + "0.082752, 0.082753, 0.082755, 0.082755, 0.082756",\ + "0.171712, 0.171712, 0.171712, 0.171712, 0.171712",\ + "0.455131, 0.455131, 0.455132, 0.455134, 0.455138",\ + "1.170720, 1.170720, 1.170720, 1.170721, 1.170722"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2546*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.406169, 0.656592, 0.934420, 1.432277, 2.427991",\ + "0.449017, 0.699439, 0.977034, 1.474087, 2.468193",\ + "0.525461, 0.775882, 1.053428, 1.550312, 2.544081",\ + "0.748731, 0.999151, 1.276378, 1.772159, 2.763722",\ + "1.311413, 1.561833, 1.838149, 2.330786, 3.316060",\ + "0.493579, 0.744100, 1.022078, 1.518992, 2.513925",\ + "0.536427, 0.786947, 1.064689, 1.560801, 2.554126",\ + "0.612871, 0.863390, 1.141083, 1.637027, 2.630014",\ + "0.836140, 1.086659, 1.364029, 1.858874, 2.849656",\ + "1.398823, 1.649341, 1.925790, 2.417500, 3.401994",\ + "0.574430, 0.832981, 1.110043, 1.606613, 2.600880",\ + "0.617278, 0.875827, 1.152654, 1.648423, 2.641081",\ + "0.693722, 0.952271, 1.229048, 1.724649, 2.716969",\ + "0.916992, 1.175540, 1.451994, 1.946496, 2.936611",\ + "1.479674, 1.738222, 2.013755, 2.505122, 3.488949",\ + "0.633136, 0.898470, 1.174188, 1.670527, 2.664389",\ + "0.675984, 0.941316, 1.216799, 1.712336, 2.704590",\ + "0.752428, 1.017760, 1.293192, 1.788562, 2.780478",\ + "0.975698, 1.241029, 1.516138, 2.010409, 3.000120",\ + "1.538380, 1.803711, 2.077899, 2.569036, 3.552458",\ + "0.968049, 1.261165, 1.526347, 2.019992, 3.009845",\ + "1.010896, 1.304012, 1.568950, 2.061798, 3.050046",\ + "1.087340, 1.380455, 1.645342, 2.138023, 3.125935",\ + "1.310609, 1.603724, 1.868277, 2.359865, 3.345576",\ + "1.873291, 2.166406, 2.430006, 2.918479, 3.897913"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.072784, 0.072803, 0.073020, 0.073739, 0.075177",\ + "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855741, 0.855755, 0.855915, 0.856445, 0.857505",\ + "2.187214, 2.187237, 2.187508, 2.188406, 2.190202",\ + "0.072784, 0.072803, 0.073022, 0.073739, 0.075177",\ + "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855741, 0.855755, 0.855917, 0.856445, 0.857505",\ + "2.187214, 2.187237, 2.187511, 2.188406, 2.190202",\ + "0.072785, 0.072803, 0.073022, 0.073739, 0.075177",\ + "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855742, 0.855755, 0.855917, 0.856445, 0.857505",\ + "2.187214, 2.187238, 2.187511, 2.188406, 2.190202",\ + "0.072787, 0.072803, 0.073023, 0.073739, 0.075177",\ + "0.151157, 0.151161, 0.151203, 0.151342, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855743, 0.855755, 0.855917, 0.856445, 0.857505",\ + "2.187217, 2.187238, 2.187511, 2.188406, 2.190202",\ + "0.072792, 0.072806, 0.073030, 0.073742, 0.075177",\ + "0.151158, 0.151161, 0.151205, 0.151343, 0.151621",\ + "0.326364, 0.326364, 0.326365, 0.326368, 0.326373",\ + "0.855747, 0.855757, 0.855922, 0.856447, 0.857505",\ + "2.187224, 2.187241, 2.187521, 2.188410, 2.190202"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.418201, 0.668626, 0.943179, 1.429721, 2.402805",\ + "0.445861, 0.696286, 0.970980, 1.458010, 2.432069",\ + "0.495070, 0.745495, 1.020403, 1.508166, 2.483693",\ + "0.635634, 0.886057, 1.161631, 1.651703, 2.631847",\ + "0.988299, 1.238725, 1.516052, 2.012175, 3.004421",\ + "0.505610, 0.756134, 1.030800, 1.516435, 2.488739",\ + "0.533270, 0.783794, 1.058603, 1.544724, 2.518003",\ + "0.582480, 0.833003, 1.108028, 1.594880, 2.569627",\ + "0.723043, 0.973565, 1.249264, 1.738417, 2.717781",\ + "1.075708, 1.326233, 1.603704, 2.098890, 3.090355",\ + "0.586462, 0.845014, 1.118765, 1.604057, 2.575694",\ + "0.614122, 0.872674, 1.146568, 1.632346, 2.604958",\ + "0.663331, 0.921884, 1.195993, 1.682502, 2.656582",\ + "0.803894, 1.062445, 1.337229, 1.826039, 2.804736",\ + "1.156560, 1.415114, 1.691670, 2.186512, 3.177310",\ + "0.645168, 0.910503, 1.182908, 1.667970, 2.639203",\ + "0.672828, 0.938163, 1.210711, 1.696259, 2.668467",\ + "0.722037, 0.987373, 1.260136, 1.746415, 2.720091",\ + "0.862600, 1.127934, 1.401372, 1.889952, 2.868245",\ + "1.215266, 1.480603, 1.755814, 2.250425, 3.240819",\ + "0.980081, 1.273199, 1.534953, 2.017389, 2.984659",\ + "1.007741, 1.300859, 1.562760, 2.045680, 3.013923",\ + "1.056951, 1.350069, 1.612193, 2.095839, 3.065547",\ + "1.197513, 1.490629, 1.753453, 2.239386, 3.213701",\ + "1.550180, 1.843298, 2.107956, 2.599883, 3.586275"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.031046, 0.031099, 0.031481, 0.032572, 0.034755",\ + "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\ + "0.457144, 0.457135, 0.457066, 0.456868, 0.456473",\ + "1.169261, 1.169272, 1.169347, 1.169562, 1.169994",\ + "0.031046, 0.031099, 0.031484, 0.032572, 0.034755",\ + "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\ + "0.457144, 0.457135, 0.457065, 0.456868, 0.456473",\ + "1.169261, 1.169272, 1.169348, 1.169562, 1.169994",\ + "0.031046, 0.031100, 0.031484, 0.032572, 0.034755",\ + "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\ + "0.457144, 0.457134, 0.457065, 0.456868, 0.456473",\ + "1.169261, 1.169272, 1.169348, 1.169562, 1.169994",\ + "0.031048, 0.031101, 0.031484, 0.032572, 0.034755",\ + "0.078404, 0.078409, 0.078443, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173444, 0.173357",\ + "0.457144, 0.457134, 0.457065, 0.456868, 0.456473",\ + "1.169261, 1.169272, 1.169348, 1.169562, 1.169994",\ + "0.031051, 0.031118, 0.031495, 0.032577, 0.034755",\ + "0.078405, 0.078410, 0.078444, 0.078540, 0.078733",\ + "0.173504, 0.173502, 0.173487, 0.173443, 0.173357",\ + "0.457143, 0.457131, 0.457063, 0.456867, 0.456473",\ + "1.169262, 1.169275, 1.169350, 1.169563, 1.169994"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2619*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.553465, 0.819964, 1.109829, 1.605668, 2.597345",\ + "0.603560, 0.870058, 1.159923, 1.655763, 2.647441",\ + "0.692214, 0.958711, 1.248576, 1.744417, 2.736099",\ + "0.916360, 1.182856, 1.472721, 1.968563, 2.960246",\ + "1.468983, 1.735479, 2.025344, 2.521186, 3.512870",\ + "0.640874, 0.907555, 1.197480, 1.692382, 2.683279",\ + "0.690968, 0.957649, 1.247574, 1.742477, 2.733375",\ + "0.779622, 1.046302, 1.336226, 1.831131, 2.822032",\ + "1.003768, 1.270447, 1.560372, 2.055277, 3.046180",\ + "1.556391, 1.823070, 2.112994, 2.607900, 3.598804",\ + "0.721784, 0.996619, 1.285445, 1.780004, 2.770234",\ + "0.771879, 1.046713, 1.335539, 1.830098, 2.820330",\ + "0.860533, 1.135366, 1.424191, 1.918753, 2.908988",\ + "1.084679, 1.359511, 1.648337, 2.142899, 3.133135",\ + "1.637302, 1.912134, 2.200959, 2.695522, 3.685759",\ + "0.783629, 1.062374, 1.349589, 1.843917, 2.833743",\ + "0.833723, 1.112468, 1.399683, 1.894011, 2.883839",\ + "0.922377, 1.201121, 1.488336, 1.982666, 2.972497",\ + "1.146523, 1.425267, 1.712481, 2.206812, 3.196644",\ + "1.699146, 1.977889, 2.265103, 2.759435, 3.749268",\ + "1.121586, 1.428200, 1.701728, 2.193373, 3.179199",\ + "1.171680, 1.478294, 1.751822, 2.243467, 3.229295",\ + "1.260334, 1.566947, 1.840474, 2.332122, 3.317953",\ + "1.484480, 1.791093, 2.064620, 2.556268, 3.542100",\ + "2.037102, 2.343715, 2.617242, 3.108891, 4.094724"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324730, 0.324733",\ + "0.855392, 0.855392, 0.855394, 0.855403, 0.855422",\ + "2.185946, 2.185946, 2.185947, 2.185952, 2.185961"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.589270, 0.855765, 1.145630, 1.641474, 2.633161",\ + "0.610950, 0.877444, 1.167309, 1.663153, 2.654842",\ + "0.652464, 0.918958, 1.208822, 1.704667, 2.696356",\ + "0.785756, 1.052250, 1.342115, 1.837959, 2.829648",\ + "1.134654, 1.401149, 1.691014, 2.186858, 3.178545",\ + "0.676679, 0.943356, 1.233280, 1.728188, 2.719095",\ + "0.698358, 0.965036, 1.254959, 1.749868, 2.740776",\ + "0.739872, 1.006549, 1.296473, 1.791381, 2.782290",\ + "0.873164, 1.139841, 1.429765, 1.924673, 2.915581",\ + "1.222063, 1.488740, 1.778664, 2.273572, 3.264479",\ + "0.757589, 1.032420, 1.321245, 1.815809, 2.806050",\ + "0.779269, 1.054100, 1.342925, 1.837489, 2.827731",\ + "0.820783, 1.095613, 1.384438, 1.879003, 2.869245",\ + "0.954075, 1.228905, 1.517730, 2.012295, 3.002537",\ + "1.302974, 1.577804, 1.866629, 2.361193, 3.351434",\ + "0.819433, 1.098175, 1.385389, 1.879722, 2.869559",\ + "0.841113, 1.119855, 1.407069, 1.901402, 2.891240",\ + "0.882627, 1.161368, 1.448582, 1.942916, 2.932754",\ + "1.015919, 1.294661, 1.581874, 2.076208, 3.066046",\ + "1.364817, 1.643559, 1.930773, 2.425107, 3.414943",\ + "1.157390, 1.464001, 1.737528, 2.229178, 3.215015",\ + "1.179069, 1.485680, 1.759207, 2.250858, 3.236696",\ + "1.220583, 1.527194, 1.800721, 2.292372, 3.278210",\ + "1.353875, 1.660486, 1.934013, 2.425664, 3.411501",\ + "1.702774, 2.009385, 2.282912, 2.774562, 3.760399"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045715, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\ + "0.045715, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\ + "0.045715, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\ + "0.045716, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723",\ + "0.045716, 0.045718, 0.045719, 0.045719, 0.045719",\ + "0.082756, 0.082757, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455131, 0.455140",\ + "1.170717, 1.170717, 1.170718, 1.170720, 1.170723"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2551*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.535912, 0.788172, 1.068241, 1.533239, 2.463234",\ + "0.586006, 0.838266, 1.118335, 1.583333, 2.513329",\ + "0.674661, 0.926920, 1.206988, 1.671987, 2.601985",\ + "0.898807, 1.151066, 1.431133, 1.896132, 2.826131",\ + "1.451430, 1.703688, 1.983755, 2.448755, 3.378754",\ + "0.623320, 0.875758, 1.155794, 1.619953, 2.549168",\ + "0.673414, 0.925853, 1.205888, 1.670047, 2.599263",\ + "0.762069, 1.014506, 1.294541, 1.758701, 2.687918",\ + "0.986215, 1.238652, 1.518686, 1.982847, 2.912065",\ + "1.538838, 1.791275, 2.071309, 2.535469, 3.464688",\ + "0.704222, 0.964810, 1.243757, 1.707574, 2.636123",\ + "0.754316, 1.014904, 1.293851, 1.757668, 2.686218",\ + "0.842971, 1.103558, 1.382504, 1.846323, 2.774873",\ + "1.067117, 1.327704, 1.606649, 2.070468, 2.999020",\ + "1.619740, 1.880326, 2.159272, 2.623091, 3.551643",\ + "0.761984, 1.030547, 1.307896, 1.771487, 2.699632",\ + "0.812078, 1.080642, 1.357990, 1.821582, 2.749727",\ + "0.900733, 1.169295, 1.446643, 1.910236, 2.838382",\ + "1.124879, 1.393441, 1.670788, 2.134381, 3.062529",\ + "1.677502, 1.946064, 2.223411, 2.687004, 3.615152",\ + "1.092601, 1.396168, 1.659722, 2.120816, 3.045088",\ + "1.142695, 1.446262, 1.709816, 2.170910, 3.095183",\ + "1.231350, 1.534915, 1.798469, 2.259564, 3.183838",\ + "1.455496, 1.759061, 2.022614, 2.483710, 3.407985",\ + "2.008119, 2.311684, 2.575236, 3.036332, 3.960608"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954",\ + "0.046988, 0.046989, 0.046990, 0.046990, 0.046990",\ + "0.140334, 0.140334, 0.140334, 0.140334, 0.140334",\ + "0.324728, 0.324728, 0.324728, 0.324729, 0.324730",\ + "0.855391, 0.855391, 0.855393, 0.855398, 0.855408",\ + "2.185946, 2.185946, 2.185946, 2.185949, 2.185954"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.571718, 0.823975, 1.104042, 1.569042, 2.499043",\ + "0.593398, 0.845655, 1.125721, 1.590722, 2.520724",\ + "0.634911, 0.887169, 1.167235, 1.632236, 2.562238",\ + "0.768203, 1.020461, 1.300527, 1.765528, 2.695529",\ + "1.117102, 1.369359, 1.649426, 2.114426, 3.044427",\ + "0.659126, 0.911562, 1.191595, 1.655756, 2.584977",\ + "0.680806, 0.933241, 1.213274, 1.677436, 2.606658",\ + "0.722320, 0.974755, 1.254788, 1.718950, 2.648171",\ + "0.855612, 1.108047, 1.388080, 1.852242, 2.781463",\ + "1.204510, 1.456946, 1.736979, 2.201141, 3.130361",\ + "0.740028, 1.000613, 1.279558, 1.743378, 2.671932",\ + "0.761708, 1.022293, 1.301237, 1.765058, 2.693613",\ + "0.803222, 1.063807, 1.342751, 1.806571, 2.735126",\ + "0.936514, 1.197099, 1.476043, 1.939863, 2.868418",\ + "1.285412, 1.545998, 1.824942, 2.288762, 3.217316",\ + "0.797790, 1.066351, 1.343697, 1.807291, 2.735441",\ + "0.819470, 1.088030, 1.365376, 1.828971, 2.757122",\ + "0.860984, 1.129544, 1.406890, 1.870484, 2.798635",\ + "0.994276, 1.262836, 1.540182, 2.003777, 2.931927",\ + "1.343174, 1.611735, 1.889081, 2.352675, 3.280825",\ + "1.128407, 1.431970, 1.695523, 2.156619, 3.080897",\ + "1.150087, 1.453650, 1.717202, 2.178299, 3.102577",\ + "1.191600, 1.495163, 1.758715, 2.219813, 3.144091",\ + "1.324893, 1.628456, 1.892008, 2.353105, 3.277383",\ + "1.673791, 1.977355, 2.240907, 2.702003, 3.626281"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\ + "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\ + "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\ + "0.045715, 0.045716, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720",\ + "0.045715, 0.045717, 0.045718, 0.045718, 0.045718",\ + "0.082756, 0.082756, 0.082757, 0.082757, 0.082757",\ + "0.171711, 0.171711, 0.171711, 0.171712, 0.171712",\ + "0.455125, 0.455125, 0.455126, 0.455128, 0.455133",\ + "1.170717, 1.170717, 1.170717, 1.170718, 1.170720"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2487*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.552964, 0.814309, 1.099442, 1.604025, 2.613190",\ + "0.595811, 0.857156, 1.142289, 1.646869, 2.656030",\ + "0.672254, 0.933599, 1.218732, 1.723310, 2.732467",\ + "0.895523, 1.156868, 1.442001, 1.946579, 2.955732",\ + "1.458204, 1.719550, 2.004683, 2.509259, 3.518410",\ + "0.640373, 0.901851, 1.187121, 1.690739, 2.699123",\ + "0.683220, 0.944698, 1.229968, 1.733584, 2.741963",\ + "0.759663, 1.021142, 1.306411, 1.810025, 2.818400",\ + "0.982932, 1.244411, 1.529680, 2.033293, 3.041666",\ + "1.545614, 1.807093, 2.092361, 2.595973, 3.604344",\ + "0.723483, 0.990810, 1.275087, 1.778361, 2.786078",\ + "0.766329, 1.033657, 1.317933, 1.821205, 2.828918",\ + "0.842772, 1.110100, 1.394377, 1.897646, 2.905355",\ + "1.066041, 1.333369, 1.617646, 2.120914, 3.128621",\ + "1.628723, 1.896051, 2.180327, 2.683595, 3.691299",\ + "0.786922, 1.056412, 1.339232, 1.842274, 2.849587",\ + "0.829768, 1.099259, 1.382079, 1.885119, 2.892427",\ + "0.906211, 1.175702, 1.458522, 1.961560, 2.968864",\ + "1.129480, 1.398971, 1.681791, 2.184828, 3.192130",\ + "1.692162, 1.961653, 2.244473, 2.747508, 3.754808",\ + "1.122015, 1.420432, 1.691460, 2.191767, 3.195044",\ + "1.164862, 1.463279, 1.734307, 2.234612, 3.237884",\ + "1.241305, 1.539723, 1.810750, 2.311053, 3.314321",\ + "1.464574, 1.762992, 2.034019, 2.534321, 3.537586",\ + "2.027255, 2.325674, 2.596701, 3.097001, 4.100264"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.072811, 0.072811, 0.072826, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187266, 2.187333, 2.187467",\ + "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187267, 2.187333, 2.187467",\ + "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187267, 2.187333, 2.187467",\ + "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855772, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187267, 2.187333, 2.187467",\ + "0.072811, 0.072811, 0.072827, 0.072880, 0.072987",\ + "0.151162, 0.151162, 0.151165, 0.151176, 0.151196",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855773, 0.855812, 0.855891",\ + "2.187247, 2.187247, 2.187267, 2.187334, 2.187467"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.564998, 0.826343, 1.111477, 1.616063, 2.625237",\ + "0.592658, 0.854002, 1.139137, 1.643723, 2.652897",\ + "0.641868, 0.903212, 1.188347, 1.692935, 2.702110",\ + "0.782429, 1.043773, 1.328907, 1.833490, 2.842657",\ + "1.135098, 1.396442, 1.681576, 2.186166, 3.195345",\ + "0.652408, 0.913885, 1.199155, 1.702778, 2.711171",\ + "0.680068, 0.941545, 1.226815, 1.730438, 2.738831",\ + "0.729278, 0.990755, 1.276025, 1.779649, 2.788044",\ + "0.869838, 1.131316, 1.416586, 1.920205, 2.928591",\ + "1.222507, 1.483984, 1.769255, 2.272880, 3.281279",\ + "0.735517, 1.002843, 1.287121, 1.790400, 2.798126",\ + "0.763177, 1.030503, 1.314781, 1.818060, 2.825786",\ + "0.812387, 1.079713, 1.363991, 1.867271, 2.874999",\ + "0.952947, 1.220274, 1.504552, 2.007827, 3.015546",\ + "1.305617, 1.572943, 1.857221, 2.360502, 3.368234",\ + "0.798956, 1.068446, 1.351267, 1.854313, 2.861635",\ + "0.826616, 1.096106, 1.378927, 1.881973, 2.889295",\ + "0.875826, 1.145315, 1.428137, 1.931184, 2.938508",\ + "1.016386, 1.285877, 1.568697, 2.071740, 3.079055",\ + "1.369056, 1.638545, 1.921366, 2.424415, 3.431743",\ + "1.134049, 1.432466, 1.703495, 2.203806, 3.207091",\ + "1.161709, 1.460126, 1.731154, 2.231466, 3.234751",\ + "1.210919, 1.509335, 1.780365, 2.280677, 3.283964",\ + "1.351480, 1.649897, 1.920925, 2.421233, 3.424510",\ + "1.704149, 2.002565, 2.273594, 2.773909, 3.777199"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.031035, 0.031069, 0.031220, 0.031570, 0.032271",\ + "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169266, 1.169295, 1.169365, 1.169503",\ + "0.031035, 0.031069, 0.031221, 0.031570, 0.032271",\ + "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169266, 1.169296, 1.169365, 1.169503",\ + "0.031035, 0.031070, 0.031221, 0.031570, 0.032271",\ + "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169266, 1.169296, 1.169365, 1.169503",\ + "0.031035, 0.031071, 0.031221, 0.031570, 0.032271",\ + "0.078403, 0.078406, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169266, 1.169296, 1.169365, 1.169503",\ + "0.031035, 0.031083, 0.031224, 0.031571, 0.032271",\ + "0.078403, 0.078407, 0.078420, 0.078451, 0.078513",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169268, 1.169296, 1.169365, 1.169503"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.538940, 0.779876, 1.050099, 1.503272, 2.409617",\ + "0.581786, 0.822723, 1.092946, 1.546117, 2.452459",\ + "0.658229, 0.899166, 1.169389, 1.622558, 2.528897",\ + "0.881498, 1.122435, 1.392658, 1.845826, 2.752164",\ + "1.444180, 1.685117, 1.955339, 2.408507, 3.314842",\ + "0.626346, 0.867426, 1.137614, 1.589986, 2.495551",\ + "0.669192, 0.910272, 1.180461, 1.632831, 2.538393",\ + "0.745635, 0.986716, 1.256904, 1.709272, 2.614831",\ + "0.968904, 1.209985, 1.480173, 1.932540, 2.838098",\ + "1.531586, 1.772666, 2.042854, 2.495221, 3.400776",\ + "0.707175, 0.956384, 1.225576, 1.677607, 2.582506",\ + "0.750022, 0.999231, 1.268423, 1.720452, 2.625348",\ + "0.826465, 1.075674, 1.344866, 1.796893, 2.701786",\ + "1.049734, 1.298944, 1.568135, 2.020162, 2.925053",\ + "1.612416, 1.861625, 2.130816, 2.582842, 3.487731",\ + "0.764818, 1.021986, 1.289713, 1.741520, 2.646015",\ + "0.807664, 1.064833, 1.332560, 1.784365, 2.688857",\ + "0.884107, 1.141276, 1.409003, 1.860806, 2.765295",\ + "1.107376, 1.364545, 1.632272, 2.084074, 2.988562",\ + "1.670058, 1.927227, 2.194953, 2.646755, 3.551240",\ + "1.090702, 1.386049, 1.641418, 2.090797, 2.991471",\ + "1.133548, 1.428896, 1.684264, 2.133642, 3.034313",\ + "1.209992, 1.505339, 1.760707, 2.210084, 3.110751",\ + "1.433261, 1.728608, 1.983976, 2.433352, 3.334018",\ + "1.995942, 2.291290, 2.546658, 2.996032, 3.896696"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\ + "0.151162, 0.151162, 0.151164, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187262, 2.187313, 2.187414",\ + "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\ + "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187262, 2.187313, 2.187414",\ + "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\ + "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187262, 2.187313, 2.187414",\ + "0.072811, 0.072811, 0.072823, 0.072863, 0.072944",\ + "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187263, 2.187313, 2.187414",\ + "0.072811, 0.072811, 0.072824, 0.072864, 0.072944",\ + "0.151162, 0.151162, 0.151165, 0.151172, 0.151188",\ + "0.326364, 0.326364, 0.326364, 0.326364, 0.326365",\ + "0.855761, 0.855761, 0.855770, 0.855800, 0.855859",\ + "2.187248, 2.187248, 2.187263, 2.187313, 2.187414"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.550974, 0.791910, 1.062134, 1.515310, 2.421661",\ + "0.578634, 0.819570, 1.089794, 1.542970, 2.449322",\ + "0.627844, 0.868780, 1.139004, 1.592180, 2.498534",\ + "0.768404, 1.009341, 1.279564, 1.732737, 2.639084",\ + "1.121073, 1.362010, 1.632233, 2.085412, 2.991768",\ + "0.638380, 0.879460, 1.149649, 1.602023, 2.507595",\ + "0.666040, 0.907120, 1.177309, 1.629683, 2.535255",\ + "0.715250, 0.956330, 1.226519, 1.678894, 2.584468",\ + "0.855810, 1.096890, 1.367079, 1.819451, 2.725018",\ + "1.208480, 1.449559, 1.719748, 2.172125, 3.077702",\ + "0.719210, 0.968418, 1.237611, 1.689645, 2.594550",\ + "0.746870, 0.996078, 1.265271, 1.717305, 2.622211",\ + "0.796080, 1.045288, 1.314481, 1.766516, 2.671423",\ + "0.936640, 1.185849, 1.455041, 1.907072, 2.811973",\ + "1.289309, 1.538518, 1.807710, 2.259747, 3.164657",\ + "0.776852, 1.034020, 1.301748, 1.753558, 2.658059",\ + "0.804512, 1.061680, 1.329408, 1.781218, 2.685719",\ + "0.853722, 1.110890, 1.378618, 1.830429, 2.734932",\ + "0.994283, 1.251451, 1.519178, 1.970985, 2.875482",\ + "1.346952, 1.604120, 1.871847, 2.323660, 3.228166",\ + "1.102736, 1.398083, 1.653452, 2.102835, 3.003515",\ + "1.130396, 1.425743, 1.681112, 2.130495, 3.031176",\ + "1.179606, 1.474952, 1.730322, 2.179706, 3.080388",\ + "1.320167, 1.615513, 1.870883, 2.320263, 3.220938",\ + "1.672836, 1.968182, 2.223552, 2.672937, 3.573622"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.031036, 0.031054, 0.031161, 0.031438, 0.031991",\ + "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\ + "0.031036, 0.031055, 0.031162, 0.031438, 0.031991",\ + "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\ + "0.031036, 0.031055, 0.031162, 0.031438, 0.031991",\ + "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\ + "0.031036, 0.031055, 0.031162, 0.031438, 0.031991",\ + "0.078403, 0.078405, 0.078414, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169263, 1.169284, 1.169338, 1.169448",\ + "0.031036, 0.031062, 0.031165, 0.031439, 0.031991",\ + "0.078403, 0.078406, 0.078415, 0.078439, 0.078488",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457146, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169259, 1.169264, 1.169285, 1.169339, 1.169448"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2727*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.564410, 0.823611, 1.109689, 1.603513, 2.591161",\ + "0.607267, 0.866469, 1.152547, 1.646371, 2.634019",\ + "0.683720, 0.942922, 1.229000, 1.722825, 2.710474",\ + "0.906994, 1.166196, 1.452275, 1.946099, 2.933748",\ + "1.469683, 1.728885, 2.014963, 2.508788, 3.496438",\ + "0.651822, 0.911173, 1.197335, 1.690228, 2.677094",\ + "0.694680, 0.954031, 1.240193, 1.733086, 2.719953",\ + "0.771133, 1.030483, 1.316646, 1.809540, 2.796407",\ + "0.994407, 1.253758, 1.539921, 2.032814, 3.019682",\ + "1.557095, 1.816446, 2.102610, 2.595503, 3.582371",\ + "0.732717, 1.000191, 1.285301, 1.777850, 2.764050",\ + "0.775575, 1.043049, 1.328159, 1.820708, 2.806908",\ + "0.852028, 1.119502, 1.404612, 1.897162, 2.883362",\ + "1.075302, 1.342776, 1.627887, 2.120436, 3.106637",\ + "1.637990, 1.905464, 2.190576, 2.683125, 3.669326",\ + "0.792238, 1.065880, 1.349444, 1.841763, 2.827559",\ + "0.835095, 1.108738, 1.392303, 1.884622, 2.870417",\ + "0.911548, 1.185191, 1.468756, 1.961075, 2.946871",\ + "1.134822, 1.408465, 1.692031, 2.184350, 3.170146",\ + "1.697511, 1.971154, 2.254719, 2.747039, 3.732835",\ + "1.125661, 1.430876, 1.701565, 2.191215, 3.173015",\ + "1.168519, 1.473734, 1.744423, 2.234074, 3.215873",\ + "1.244972, 1.550187, 1.820877, 2.310527, 3.292327",\ + "1.468246, 1.773462, 2.044151, 2.533802, 3.515602",\ + "2.030934, 2.336150, 2.606840, 3.096491, 4.078291"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151106, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\ + "2.186892, 2.186883, 2.186870, 2.186864, 2.186852",\ + "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\ + "2.186892, 2.186883, 2.186870, 2.186864, 2.186852",\ + "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\ + "2.186892, 2.186882, 2.186870, 2.186864, 2.186852",\ + "0.072526, 0.072519, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855546, 0.855538, 0.855535, 0.855527",\ + "2.186892, 2.186882, 2.186870, 2.186864, 2.186852",\ + "0.072525, 0.072517, 0.072509, 0.072504, 0.072494",\ + "0.151107, 0.151105, 0.151104, 0.151103, 0.151101",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855544, 0.855538, 0.855535, 0.855527",\ + "2.186891, 2.186880, 2.186870, 2.186864, 2.186852"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.576423, 0.835624, 1.121701, 1.615525, 2.603172",\ + "0.604083, 0.863284, 1.149361, 1.643184, 2.630832",\ + "0.653288, 0.912488, 1.198565, 1.692388, 2.680036",\ + "0.793871, 1.053072, 1.339149, 1.832974, 2.820621",\ + "1.146508, 1.405709, 1.691785, 2.185609, 3.173255",\ + "0.663836, 0.923186, 1.209347, 1.702240, 2.689106",\ + "0.691496, 0.950845, 1.237007, 1.729899, 2.716765",\ + "0.740700, 1.000050, 1.286211, 1.779103, 2.765969",\ + "0.881284, 1.140634, 1.426796, 1.919688, 2.906555",\ + "1.233921, 1.493270, 1.779431, 2.272324, 3.259189",\ + "0.744731, 1.012204, 1.297313, 1.789862, 2.776061",\ + "0.772390, 1.039863, 1.324972, 1.817521, 2.803720",\ + "0.821595, 1.089068, 1.374177, 1.866726, 2.852924",\ + "0.962178, 1.229652, 1.514761, 2.007311, 2.993510",\ + "1.314816, 1.582289, 1.867397, 2.359946, 3.346144",\ + "0.804251, 1.077893, 1.361457, 1.853775, 2.839570",\ + "0.831911, 1.105553, 1.389116, 1.881435, 2.867229",\ + "0.881115, 1.154757, 1.438321, 1.930639, 2.916433",\ + "1.021699, 1.295341, 1.578905, 2.071224, 3.057019",\ + "1.374336, 1.647978, 1.931541, 2.423859, 3.409653",\ + "1.137675, 1.442889, 1.713577, 2.203227, 3.185026",\ + "1.165335, 1.470549, 1.741237, 2.230887, 3.212686",\ + "1.214539, 1.519753, 1.790441, 2.280091, 3.261889",\ + "1.355123, 1.660337, 1.931026, 2.420676, 3.402475",\ + "1.707760, 2.012974, 2.283661, 2.773311, 3.755109"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\ + "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\ + "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\ + "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281",\ + "0.031042, 0.031042, 0.031051, 0.031083, 0.031146",\ + "0.078404, 0.078404, 0.078405, 0.078407, 0.078413",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457146, 0.457146, 0.457146, 0.457146",\ + "1.169260, 1.169260, 1.169262, 1.169268, 1.169281"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2658*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.548070, 0.800917, 1.079123, 1.542119, 2.468112",\ + "0.590927, 0.843775, 1.121981, 1.584977, 2.510970",\ + "0.667380, 0.920228, 1.198434, 1.661431, 2.587423",\ + "0.890654, 1.143502, 1.421709, 1.884705, 2.810698",\ + "1.453343, 1.706191, 1.984398, 2.447394, 3.373387",\ + "0.635475, 0.888501, 1.166668, 1.628833, 2.554045",\ + "0.678333, 0.931359, 1.209527, 1.671691, 2.596904",\ + "0.754786, 1.007812, 1.285980, 1.748145, 2.673357",\ + "0.978060, 1.231086, 1.509255, 1.971419, 2.896632",\ + "1.540748, 1.793775, 2.071944, 2.534108, 3.459321",\ + "0.716287, 0.977534, 1.254631, 1.716454, 2.641000",\ + "0.759144, 1.020392, 1.297489, 1.759312, 2.683859",\ + "0.835597, 1.096845, 1.373943, 1.835766, 2.760312",\ + "1.058871, 1.320120, 1.597218, 2.059040, 2.983587",\ + "1.621560, 1.882808, 2.159906, 2.621729, 3.546276",\ + "0.773896, 1.043245, 1.318770, 1.780367, 2.704509",\ + "0.816754, 1.086103, 1.361628, 1.823225, 2.747368",\ + "0.893206, 1.162556, 1.438081, 1.899679, 2.823821",\ + "1.116481, 1.385830, 1.661356, 2.122953, 3.047096",\ + "1.679169, 1.948519, 2.224045, 2.685642, 3.609785",\ + "1.108670, 1.408584, 1.670573, 2.129684, 3.049965",\ + "1.151528, 1.451442, 1.713432, 2.172543, 3.092824",\ + "1.227981, 1.527896, 1.789885, 2.248996, 3.169277",\ + "1.451255, 1.751170, 2.013160, 2.472271, 3.392552",\ + "2.013944, 2.313859, 2.575849, 3.034960, 3.955241"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.072526, 0.072516, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\ + "2.186892, 2.186879, 2.186865, 2.186863, 2.186859",\ + "0.072526, 0.072516, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\ + "2.186892, 2.186878, 2.186865, 2.186863, 2.186859",\ + "0.072526, 0.072515, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\ + "2.186892, 2.186878, 2.186865, 2.186863, 2.186859",\ + "0.072526, 0.072515, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151105, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855551, 0.855543, 0.855535, 0.855534, 0.855532",\ + "2.186892, 2.186878, 2.186865, 2.186863, 2.186859",\ + "0.072524, 0.072513, 0.072505, 0.072503, 0.072500",\ + "0.151107, 0.151104, 0.151103, 0.151102, 0.151102",\ + "0.326363, 0.326363, 0.326363, 0.326363, 0.326363",\ + "0.855550, 0.855541, 0.855535, 0.855534, 0.855532",\ + "2.186889, 2.186875, 2.186865, 2.186863, 2.186859"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.560083, 0.812930, 1.091135, 1.554131, 2.480123",\ + "0.587743, 0.840589, 1.118794, 1.581790, 2.507782",\ + "0.636947, 0.889794, 1.167998, 1.630994, 2.556986",\ + "0.777531, 1.030378, 1.308583, 1.771580, 2.697572",\ + "1.130168, 1.383014, 1.661218, 2.124214, 3.050207",\ + "0.647489, 0.900513, 1.178680, 1.640844, 2.566057",\ + "0.675148, 0.928173, 1.206340, 1.668504, 2.593716",\ + "0.724353, 0.977377, 1.255544, 1.717708, 2.642920",\ + "0.864936, 1.117962, 1.396129, 1.858294, 2.783506",\ + "1.217574, 1.470598, 1.748764, 2.210928, 3.136140",\ + "0.728300, 0.989547, 1.266643, 1.728466, 2.653012",\ + "0.755960, 1.017207, 1.294303, 1.756125, 2.680671",\ + "0.805164, 1.066411, 1.343507, 1.805329, 2.729875",\ + "0.945748, 1.206995, 1.484092, 1.945915, 2.870461",\ + "1.298385, 1.559631, 1.836727, 2.298549, 3.223095",\ + "0.785910, 1.055257, 1.330781, 1.792379, 2.716521",\ + "0.813569, 1.082917, 1.358441, 1.820038, 2.744180",\ + "0.862774, 1.132121, 1.407645, 1.869242, 2.793384",\ + "1.003357, 1.272706, 1.548230, 2.009828, 2.933970",\ + "1.355995, 1.625342, 1.900865, 2.362462, 3.286604",\ + "1.120684, 1.420597, 1.682585, 2.141696, 3.061977",\ + "1.148343, 1.448256, 1.710245, 2.169356, 3.089636",\ + "1.197548, 1.497461, 1.759449, 2.218560, 3.138840",\ + "1.338132, 1.638045, 1.900034, 2.359145, 3.279426",\ + "1.690769, 1.990681, 2.252669, 2.711780, 3.632061"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\ + "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\ + "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\ + "0.031042, 0.031042, 0.031047, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273",\ + "0.031042, 0.031042, 0.031048, 0.031067, 0.031107",\ + "0.078404, 0.078404, 0.078404, 0.078406, 0.078410",\ + "0.173505, 0.173505, 0.173505, 0.173505, 0.173505",\ + "0.457145, 0.457145, 0.457145, 0.457145, 0.457145",\ + "1.169260, 1.169260, 1.169261, 1.169265, 1.169273"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_2601*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[20]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.380795, 0.602668, 0.780712, 1.069465, 1.629809",\ + "0.415064, 0.636936, 0.814980, 1.103733, 1.664078",\ + "0.488546, 0.710419, 0.888463, 1.177216, 1.737561",\ + "0.709765, 0.931638, 1.109681, 1.398435, 1.958779",\ + "1.271568, 1.493441, 1.671484, 1.960238, 2.520582",\ + "0.469199, 0.689987, 0.867992, 1.156770, 1.717163",\ + "0.503468, 0.724255, 0.902261, 1.191038, 1.751431",\ + "0.576950, 0.797738, 0.975743, 1.264521, 1.824914",\ + "0.798169, 1.018957, 1.196962, 1.485740, 2.046133",\ + "1.359972, 1.580759, 1.758765, 2.047543, 2.607936",\ + "0.558271, 0.770322, 0.948019, 1.236798, 1.797194",\ + "0.592539, 0.804590, 0.982288, 1.271067, 1.831463",\ + "0.666022, 0.878073, 1.055770, 1.344549, 1.904946",\ + "0.887241, 1.099292, 1.276989, 1.565768, 2.126164",\ + "1.449044, 1.661095, 1.838792, 2.127571, 2.687967",\ + "0.621529, 0.828138, 1.005713, 1.294227, 1.854208",\ + "0.655798, 0.862407, 1.039981, 1.328496, 1.888477",\ + "0.729280, 0.935889, 1.113464, 1.401978, 1.961960",\ + "0.950499, 1.157108, 1.334682, 1.623197, 2.183178",\ + "1.512302, 1.718911, 1.896485, 2.185000, 2.744981",\ + "0.953935, 1.133367, 1.309369, 1.597399, 2.156428",\ + "0.988204, 1.167636, 1.343637, 1.631667, 2.190696",\ + "1.061687, 1.241118, 1.417120, 1.705150, 2.264179",\ + "1.282905, 1.462337, 1.638339, 1.926369, 2.485398",\ + "1.844708, 2.024140, 2.200142, 2.488172, 3.047201"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\ + "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\ + "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\ + "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889",\ + "0.027358, 0.027358, 0.027358, 0.027363, 0.027374",\ + "0.129497, 0.129497, 0.129497, 0.129497, 0.129497",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831905, 0.831905, 0.831905, 0.831905, 0.831908",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131889"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.351941, 0.573814, 0.751857, 1.040610, 1.600955",\ + "0.377860, 0.599733, 0.777776, 1.066529, 1.626874",\ + "0.432503, 0.654375, 0.832419, 1.121172, 1.681517",\ + "0.582379, 0.804252, 0.982296, 1.271049, 1.831393",\ + "0.955531, 1.177403, 1.355447, 1.644200, 2.204545",\ + "0.440345, 0.661132, 0.839138, 1.127915, 1.688308",\ + "0.466264, 0.687051, 0.865057, 1.153834, 1.714228",\ + "0.520907, 0.741694, 0.919700, 1.208477, 1.768870",\ + "0.670783, 0.891571, 1.069576, 1.358354, 1.918747",\ + "1.043935, 1.264722, 1.442728, 1.731505, 2.291898",\ + "0.529417, 0.741468, 0.919165, 1.207944, 1.768340",\ + "0.555336, 0.767386, 0.945084, 1.233863, 1.794259",\ + "0.609978, 0.822029, 0.999727, 1.288506, 1.848902",\ + "0.759855, 0.971906, 1.149603, 1.438382, 1.998778",\ + "1.133006, 1.345057, 1.522755, 1.811534, 2.371930",\ + "0.592675, 0.799284, 0.976858, 1.265373, 1.825354",\ + "0.618594, 0.825203, 1.002777, 1.291292, 1.851273",\ + "0.673236, 0.879846, 1.057420, 1.345935, 1.905916",\ + "0.823113, 1.029722, 1.207296, 1.495811, 2.055792",\ + "1.196265, 1.402874, 1.580448, 1.868963, 2.428944",\ + "0.925081, 1.104513, 1.280515, 1.568545, 2.127573",\ + "0.951000, 1.130432, 1.306434, 1.594464, 2.153493",\ + "1.005643, 1.185075, 1.361076, 1.649106, 2.208135",\ + "1.155519, 1.334951, 1.510953, 1.798983, 2.358012",\ + "1.528671, 1.708103, 1.884104, 2.172134, 2.731164"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001805, 0.074804, 0.161857, 0.321908, 0.642011"); + values ( "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122213, 1.122213, 1.122213, 1.122213, 1.122214"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2664*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[22]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.357049, 0.595251, 0.779226, 1.073282, 1.641542",\ + "0.391318, 0.630694, 0.814727, 1.108794, 1.677077",\ + "0.464801, 0.704176, 0.888210, 1.182277, 1.750560",\ + "0.686019, 0.925396, 1.109429, 1.403496, 1.971779",\ + "1.247822, 1.487198, 1.671232, 1.965299, 2.533582",\ + "0.445388, 0.682569, 0.866506, 1.160588, 1.728896",\ + "0.479656, 0.718012, 0.902008, 1.196099, 1.764431",\ + "0.553139, 0.791495, 0.975491, 1.269582, 1.837914",\ + "0.774358, 1.012714, 1.196710, 1.490801, 2.059132",\ + "1.336161, 1.574517, 1.758512, 2.052604, 2.620935",\ + "0.534519, 0.762902, 0.946533, 1.240616, 1.808927",\ + "0.568788, 0.798345, 0.982035, 1.276128, 1.844462",\ + "0.642270, 0.871828, 1.055518, 1.349610, 1.917945",\ + "0.863489, 1.093047, 1.276737, 1.570829, 2.139164",\ + "1.425292, 1.654850, 1.838539, 2.132632, 2.700967",\ + "0.597943, 0.820727, 1.004241, 1.298055, 1.865961",\ + "0.632211, 0.856174, 1.039743, 1.333567, 1.901497",\ + "0.705694, 0.929657, 1.113225, 1.407049, 1.974979",\ + "0.926913, 1.150876, 1.334444, 1.628268, 2.196198",\ + "1.488716, 1.712679, 1.896247, 2.190071, 2.758001",\ + "0.932941, 1.126006, 1.307899, 1.601235, 2.168205",\ + "0.967209, 1.161484, 1.343401, 1.636746, 2.203741",\ + "1.040692, 1.234967, 1.416883, 1.710229, 2.277223",\ + "1.261911, 1.456186, 1.638102, 1.931448, 2.498442",\ + "1.823713, 2.017988, 2.199905, 2.493251, 3.060245"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\ + "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\ + "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\ + "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891",\ + "0.027366, 0.027366, 0.027366, 0.027374, 0.027393",\ + "0.129494, 0.129494, 0.129494, 0.129494, 0.129494",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314624",\ + "0.831904, 0.831904, 0.831904, 0.831906, 0.831910",\ + "2.131887, 2.131887, 2.131887, 2.131888, 2.131891"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.328195, 0.567571, 0.751605, 1.045671, 1.613954",\ + "0.354114, 0.593490, 0.777524, 1.071590, 1.639874",\ + "0.408757, 0.648133, 0.832166, 1.126233, 1.694516",\ + "0.558634, 0.798009, 0.982043, 1.276110, 1.844393",\ + "0.931785, 1.171161, 1.355194, 1.649261, 2.217544",\ + "0.416534, 0.654889, 0.838885, 1.132977, 1.701308",\ + "0.442453, 0.680808, 0.864804, 1.158895, 1.727227",\ + "0.497095, 0.735451, 0.919447, 1.213538, 1.781870",\ + "0.646972, 0.885328, 1.069324, 1.363415, 1.931746",\ + "1.020123, 1.258479, 1.442475, 1.736566, 2.304898",\ + "0.505665, 0.735223, 0.918912, 1.213005, 1.781339",\ + "0.531584, 0.761142, 0.944831, 1.238924, 1.807259",\ + "0.586226, 0.815784, 0.999474, 1.293567, 1.861901",\ + "0.736103, 0.965661, 1.149351, 1.443443, 2.011778",\ + "1.109254, 1.338812, 1.522502, 1.816595, 2.384929",\ + "0.569089, 0.793052, 0.976620, 1.270444, 1.838374",\ + "0.595008, 0.818971, 1.002539, 1.296363, 1.864293",\ + "0.649650, 0.873613, 1.057182, 1.351006, 1.918935",\ + "0.799527, 1.023490, 1.207058, 1.500882, 2.068812",\ + "1.172678, 1.396641, 1.580210, 1.874034, 2.441963",\ + "0.904086, 1.098361, 1.280278, 1.573624, 2.140618",\ + "0.930005, 1.124280, 1.306197, 1.599543, 2.166537",\ + "0.984648, 1.178923, 1.360839, 1.654185, 2.221179",\ + "1.134525, 1.328800, 1.510716, 1.804062, 2.371056",\ + "1.507676, 1.701951, 1.883868, 2.177213, 2.744207"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215",\ + "0.015511, 0.015511, 0.015511, 0.015511, 0.015512",\ + "0.067734, 0.067734, 0.067734, 0.067734, 0.067734",\ + "0.170292, 0.170292, 0.170292, 0.170292, 0.170293",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122212, 1.122212, 1.122212, 1.122213, 1.122215"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.439056, 0.659338, 0.836735, 1.125199, 1.685426",\ + "0.473321, 0.693604, 0.871000, 1.159464, 1.719692",\ + "0.546805, 0.767087, 0.944484, 1.232948, 1.793175",\ + "0.768026, 0.988308, 1.165705, 1.454169, 2.014396",\ + "1.329834, 1.550117, 1.727513, 2.015977, 2.576204",\ + "0.527452, 0.746657, 0.924016, 1.212504, 1.772779",\ + "0.561718, 0.780922, 0.958281, 1.246769, 1.807045",\ + "0.635202, 0.854406, 1.031765, 1.320253, 1.880529",\ + "0.856422, 1.075626, 1.252986, 1.541474, 2.101749",\ + "1.418231, 1.637435, 1.814794, 2.103282, 2.663558",\ + "0.616803, 0.826989, 1.004043, 1.292532, 1.852811",\ + "0.651068, 0.861255, 1.038308, 1.326798, 1.887077",\ + "0.724552, 0.934738, 1.111792, 1.400281, 1.960560",\ + "0.945773, 1.155959, 1.333013, 1.621502, 2.181781",\ + "1.507581, 1.717768, 1.894821, 2.183311, 2.743589",\ + "0.680452, 0.884805, 1.061735, 1.349962, 1.909826",\ + "0.714717, 0.919071, 1.096000, 1.384227, 1.944092",\ + "0.788201, 0.992554, 1.169484, 1.457711, 2.017575",\ + "1.009422, 1.213775, 1.390705, 1.678931, 2.238796",\ + "1.571230, 1.775584, 1.952513, 2.240740, 2.800604",\ + "1.011732, 1.190021, 1.365390, 1.653133, 2.212047",\ + "1.045997, 1.224287, 1.399656, 1.687398, 2.246312",\ + "1.119481, 1.297770, 1.473139, 1.760882, 2.319796",\ + "1.340702, 1.518991, 1.694360, 1.982103, 2.541017",\ + "1.902511, 2.080800, 2.256169, 2.543911, 3.102825"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027424, 0.027425, 0.027426, 0.027427",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831916, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.410231, 0.630513, 0.807909, 1.096372, 1.656599",\ + "0.436125, 0.656408, 0.833804, 1.122268, 1.682495",\ + "0.490769, 0.711051, 0.888448, 1.176911, 1.737139",\ + "0.640645, 0.860927, 1.038324, 1.326787, 1.887015",\ + "1.013797, 1.234079, 1.411476, 1.699939, 2.260167",\ + "0.498627, 0.717831, 0.895190, 1.183677, 1.743952",\ + "0.524522, 0.743726, 0.921085, 1.209573, 1.769848",\ + "0.579165, 0.798369, 0.975729, 1.264216, 1.824492",\ + "0.729041, 0.948246, 1.125605, 1.414093, 1.974368",\ + "1.102193, 1.321398, 1.498757, 1.787244, 2.347520",\ + "0.587977, 0.798164, 0.975217, 1.263706, 1.823984",\ + "0.613872, 0.824059, 1.001112, 1.289602, 1.849880",\ + "0.668516, 0.878702, 1.055755, 1.344245, 1.904523",\ + "0.818392, 1.028578, 1.205631, 1.494121, 2.054400",\ + "1.191543, 1.401730, 1.578784, 1.867273, 2.427552",\ + "0.651626, 0.855980, 1.032909, 1.321135, 1.880999",\ + "0.677521, 0.881875, 1.058804, 1.347031, 1.906895",\ + "0.732164, 0.936518, 1.113448, 1.401674, 1.961538",\ + "0.882041, 1.086394, 1.263324, 1.551550, 2.111415",\ + "1.255192, 1.459546, 1.636476, 1.924702, 2.484566",\ + "0.982907, 1.161196, 1.336565, 1.624306, 2.183219",\ + "1.008801, 1.187091, 1.362460, 1.650202, 2.209116",\ + "1.063445, 1.241734, 1.417103, 1.704845, 2.263759",\ + "1.213321, 1.391610, 1.566979, 1.854722, 2.413635",\ + "1.586473, 1.764762, 1.940131, 2.227873, 2.786787"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015464, 0.015465, 0.015465, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2417*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.416720, 0.653678, 0.840231, 1.138631, 1.715459",\ + "0.450985, 0.687943, 0.874496, 1.172896, 1.749724",\ + "0.524469, 0.761427, 0.947980, 1.246380, 1.823208",\ + "0.745690, 0.982648, 1.169201, 1.467601, 2.044429",\ + "1.307499, 1.544456, 1.731009, 2.029409, 2.606237",\ + "0.505034, 0.740996, 0.927512, 1.225936, 1.802812",\ + "0.539300, 0.775261, 0.961777, 1.260202, 1.837078",\ + "0.612783, 0.848745, 1.035261, 1.333685, 1.910561",\ + "0.834004, 1.069966, 1.256482, 1.554906, 2.131782",\ + "1.395813, 1.631774, 1.818290, 2.116714, 2.693590",\ + "0.594427, 0.821326, 1.007539, 1.305964, 1.882844",\ + "0.628693, 0.855591, 1.041804, 1.340230, 1.917109",\ + "0.702176, 0.929075, 1.115288, 1.413714, 1.990593",\ + "0.923397, 1.150296, 1.336509, 1.634935, 2.211814",\ + "1.485206, 1.712105, 1.898317, 2.196743, 2.773622",\ + "0.658240, 0.879157, 1.065253, 1.363414, 1.939900",\ + "0.692506, 0.913422, 1.099519, 1.397680, 1.974165",\ + "0.765989, 0.986906, 1.173002, 1.471163, 2.047649",\ + "0.987210, 1.208127, 1.394223, 1.692384, 2.268870",\ + "1.549019, 1.769935, 1.956032, 2.254193, 2.830678",\ + "0.995697, 1.184467, 1.368911, 1.666602, 2.242170",\ + "1.029963, 1.218732, 1.403177, 1.700868, 2.276436",\ + "1.103446, 1.292216, 1.476660, 1.774352, 2.349919",\ + "1.324667, 1.513437, 1.697881, 1.995573, 2.571140",\ + "1.886476, 2.075245, 2.259690, 2.557381, 3.132948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027423, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895",\ + "0.027424, 0.027425, 0.027425, 0.027426, 0.027428",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314624, 0.314624, 0.314624, 0.314623",\ + "0.831916, 0.831916, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131895"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.387894, 0.624852, 0.811405, 1.109804, 1.686631",\ + "0.413789, 0.650747, 0.837300, 1.135700, 1.712528",\ + "0.468433, 0.705391, 0.891944, 1.190343, 1.767171",\ + "0.618309, 0.855267, 1.041820, 1.340220, 1.917047",\ + "0.991461, 1.228418, 1.414971, 1.713371, 2.290199",\ + "0.476209, 0.712170, 0.898686, 1.197109, 1.773985",\ + "0.502103, 0.738065, 0.924581, 1.223005, 1.799881",\ + "0.556747, 0.792708, 0.979225, 1.277649, 1.854524",\ + "0.706623, 0.942585, 1.129101, 1.427525, 2.004401",\ + "1.079775, 1.315736, 1.502252, 1.800677, 2.377553",\ + "0.565602, 0.792500, 0.978712, 1.277138, 1.854016",\ + "0.591497, 0.818395, 1.004608, 1.303034, 1.879913",\ + "0.646140, 0.873039, 1.059251, 1.357677, 1.934556",\ + "0.796016, 1.022915, 1.209128, 1.507553, 2.084432",\ + "1.169168, 1.396067, 1.582279, 1.880705, 2.457584",\ + "0.629415, 0.850331, 1.036427, 1.334588, 1.911072",\ + "0.655310, 0.876226, 1.062322, 1.360483, 1.936969",\ + "0.709953, 0.930869, 1.116966, 1.415127, 1.991612",\ + "0.859829, 1.080746, 1.266842, 1.565003, 2.141489",\ + "1.232981, 1.453897, 1.639994, 1.938155, 2.514640",\ + "0.966871, 1.155640, 1.340085, 1.637776, 2.213343",\ + "0.992766, 1.181536, 1.365980, 1.663672, 2.239239",\ + "1.047410, 1.236179, 1.420624, 1.718315, 2.293883",\ + "1.197286, 1.386055, 1.570500, 1.868191, 2.443759",\ + "1.570438, 1.759207, 1.943652, 2.241343, 2.816911"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015464, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122217, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015465, 0.015465, 0.015465, 0.015466, 0.015467",\ + "0.067728, 0.067728, 0.067728, 0.067728, 0.067729",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2525*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[35]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.317807, 0.553382, 0.743028, 1.048041, 1.638313",\ + "0.360716, 0.596291, 0.785937, 1.090950, 1.681222",\ + "0.437216, 0.672790, 0.862436, 1.167450, 1.757720",\ + "0.660515, 0.896090, 1.085736, 1.390749, 1.981019",\ + "1.219139, 1.454558, 1.644426, 1.949632, 2.540179",\ + "0.406273, 0.640700, 0.830308, 1.135346, 1.725666",\ + "0.449182, 0.683609, 0.873218, 1.178255, 1.768575",\ + "0.525681, 0.760108, 0.949717, 1.254755, 1.845074",\ + "0.748981, 0.983408, 1.173017, 1.478054, 2.068373",\ + "1.307619, 1.541876, 1.731707, 2.036937, 2.627532",\ + "0.495773, 0.721033, 0.910335, 1.215375, 1.805698",\ + "0.538682, 0.763942, 0.953244, 1.258284, 1.848607",\ + "0.615182, 0.840441, 1.029744, 1.334783, 1.925105",\ + "0.838481, 1.063741, 1.253043, 1.558083, 2.148405",\ + "1.397163, 1.622209, 1.811734, 2.116965, 2.707564",\ + "0.559539, 0.778868, 0.968056, 1.272841, 1.862785",\ + "0.602449, 0.821777, 1.010965, 1.315750, 1.905694",\ + "0.678948, 0.898276, 1.087465, 1.392249, 1.982193",\ + "0.902248, 1.121576, 1.310764, 1.615548, 2.205492",\ + "1.460969, 1.680044, 1.869455, 2.174432, 2.764652",\ + "0.896716, 1.084217, 1.271716, 1.576043, 2.165093",\ + "0.939625, 1.127126, 1.314625, 1.618952, 2.208002",\ + "1.016124, 1.203625, 1.391125, 1.695451, 2.284501",\ + "1.239424, 1.426925, 1.614424, 1.918751, 2.507800",\ + "1.798400, 1.985393, 2.173115, 2.477634, 3.066961"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136074, 0.136074, 0.136074, 0.136074, 0.136074",\ + "0.314166, 0.314166, 0.314166, 0.314166, 0.314166",\ + "0.833609, 0.833609, 0.833609, 0.833609, 0.833609",\ + "2.135110, 2.135110, 2.135110, 2.135111, 2.135114"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.305217, 0.540636, 0.730505, 1.035711, 1.626258",\ + "0.334877, 0.570296, 0.760166, 1.065372, 1.655918",\ + "0.386817, 0.622236, 0.812106, 1.117312, 1.707858",\ + "0.535277, 0.770695, 0.960565, 1.265772, 1.856318",\ + "0.899736, 1.135311, 1.324957, 1.629971, 2.220244",\ + "0.393698, 0.627954, 0.817786, 1.123016, 1.713611",\ + "0.423358, 0.657614, 0.847447, 1.152677, 1.743272",\ + "0.475298, 0.709554, 0.899387, 1.204617, 1.795212",\ + "0.623757, 0.858014, 1.047846, 1.353077, 1.943671",\ + "0.988201, 1.222629, 1.412238, 1.717276, 2.307598",\ + "0.483241, 0.708287, 0.897813, 1.203045, 1.793643",\ + "0.512901, 0.737947, 0.927473, 1.232705, 1.823303",\ + "0.564842, 0.789887, 0.979414, 1.284645, 1.875243",\ + "0.713301, 0.938347, 1.127873, 1.433105, 2.023703",\ + "1.077702, 1.302962, 1.492265, 1.797305, 2.387629",\ + "0.547048, 0.766122, 0.955534, 1.260511, 1.850731",\ + "0.576708, 0.795782, 0.985195, 1.290171, 1.880391",\ + "0.628648, 0.847722, 1.037135, 1.342111, 1.932331",\ + "0.777107, 0.996181, 1.185595, 1.490571, 2.080791",\ + "1.141469, 1.360797, 1.549985, 1.854770, 2.444716",\ + "0.884478, 1.071471, 1.259194, 1.563713, 2.153039",\ + "0.914138, 1.101131, 1.288855, 1.593374, 2.182700",\ + "0.966078, 1.153071, 1.340795, 1.645314, 2.234640",\ + "1.114538, 1.301530, 1.489255, 1.793774, 2.383100",\ + "1.478645, 1.666146, 1.853645, 2.157973, 2.747025"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002254, 0.075253, 0.162193, 0.322132, 0.642011"); + values ( "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119158, 1.119160, 1.119160, 1.119170, 1.119193",\ + "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119158, 1.119160, 1.119160, 1.119170, 1.119193",\ + "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119158, 1.119160, 1.119160, 1.119170, 1.119193",\ + "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119159, 1.119160, 1.119160, 1.119170, 1.119193",\ + "0.026620, 0.026620, 0.026620, 0.026620, 0.026620",\ + "0.075782, 0.075782, 0.075782, 0.075782, 0.075782",\ + "0.169298, 0.169298, 0.169298, 0.169298, 0.169298",\ + "0.439562, 0.439563, 0.439563, 0.439565, 0.439573",\ + "1.119160, 1.119160, 1.119160, 1.119170, 1.119193"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2639*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[36]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.385015, 0.606699, 0.784745, 1.073680, 1.634527",\ + "0.435014, 0.656698, 0.834744, 1.123679, 1.684526",\ + "0.515571, 0.737187, 0.915297, 1.204231, 1.765078",\ + "0.736804, 0.958420, 1.136530, 1.425464, 1.986311",\ + "1.298648, 1.520264, 1.698375, 1.987309, 2.548156",\ + "0.473424, 0.694018, 0.872026, 1.160985, 1.721881",\ + "0.523423, 0.744017, 0.922025, 1.210984, 1.771880",\ + "0.603979, 0.824505, 1.002578, 1.291536, 1.852431",\ + "0.825212, 1.045738, 1.223811, 1.512769, 2.073665",\ + "1.387057, 1.607583, 1.785656, 2.074614, 2.635510",\ + "0.562514, 0.774353, 0.952053, 1.241014, 1.801912",\ + "0.612513, 0.824352, 1.002052, 1.291013, 1.851911",\ + "0.693070, 0.904840, 1.082605, 1.371564, 1.932463",\ + "0.914303, 1.126073, 1.303838, 1.592798, 2.153697",\ + "1.476147, 1.687918, 1.865683, 2.154643, 2.715541",\ + "0.625792, 0.832174, 1.009746, 1.298444, 1.858928",\ + "0.675791, 0.882173, 1.059745, 1.348443, 1.908927",\ + "0.756348, 0.962666, 1.140298, 1.428994, 1.989478",\ + "0.977581, 1.183899, 1.361531, 1.650227, 2.210711",\ + "1.539425, 1.745744, 1.923376, 2.212072, 2.772557",\ + "0.956955, 1.137434, 1.313402, 1.601616, 2.161149",\ + "1.006954, 1.187433, 1.363401, 1.651615, 2.211148",\ + "1.086373, 1.267959, 1.443954, 1.732166, 2.291699",\ + "1.307606, 1.489192, 1.665187, 1.953399, 2.512933",\ + "1.869451, 2.051037, 2.227032, 2.515244, 3.074778"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027446, 0.027446, 0.027446, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.379185, 0.600800, 0.778912, 1.067847, 1.628695",\ + "0.404931, 0.626547, 0.804658, 1.093592, 1.654439",\ + "0.459580, 0.681196, 0.859307, 1.148241, 1.709088",\ + "0.609453, 0.831069, 1.009180, 1.298114, 1.858961",\ + "0.965195, 1.186879, 1.364924, 1.653859, 2.214706",\ + "0.467593, 0.688119, 0.866193, 1.155152, 1.716048",\ + "0.493340, 0.713866, 0.891939, 1.180897, 1.741792",\ + "0.547989, 0.768515, 0.946587, 1.235546, 1.796441",\ + "0.697862, 0.918388, 1.096461, 1.385419, 1.946315",\ + "1.053603, 1.274197, 1.452205, 1.741164, 2.302060",\ + "0.556683, 0.768454, 0.946220, 1.235180, 1.796080",\ + "0.582430, 0.794201, 0.971965, 1.260925, 1.821824",\ + "0.637079, 0.848850, 1.026614, 1.315574, 1.876473",\ + "0.786952, 0.998723, 1.176488, 1.465447, 2.026346",\ + "1.142694, 1.354532, 1.532232, 1.821193, 2.382091",\ + "0.619961, 0.826280, 1.003913, 1.292610, 1.853095",\ + "0.645708, 0.852026, 1.029659, 1.318355, 1.878839",\ + "0.700357, 0.906675, 1.084307, 1.373004, 1.933488",\ + "0.850230, 1.056549, 1.234181, 1.522877, 2.083362",\ + "1.205971, 1.412353, 1.589925, 1.878623, 2.439106",\ + "0.949987, 1.131573, 1.307569, 1.595782, 2.155316",\ + "0.975733, 1.157320, 1.333315, 1.621527, 2.181061",\ + "1.030382, 1.211969, 1.387964, 1.676176, 2.235709",\ + "1.180256, 1.361842, 1.537837, 1.826049, 2.385583",\ + "1.537134, 1.717614, 1.893581, 2.181795, 2.741328"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015175, 0.015175, 0.015173, 0.015172, 0.015170",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2690*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[37]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.362229, 0.589916, 0.774631, 1.069784, 1.640082",\ + "0.412228, 0.639915, 0.824630, 1.119783, 1.690081",\ + "0.492795, 0.719167, 0.903893, 1.199092, 1.769493",\ + "0.714028, 0.940400, 1.125127, 1.420325, 1.990727",\ + "1.275872, 1.502245, 1.686972, 1.982170, 2.552572",\ + "0.450567, 0.677234, 0.861912, 1.157089, 1.727435",\ + "0.500567, 0.727233, 0.911911, 1.207088, 1.777434",\ + "0.581133, 0.806485, 0.991174, 1.286397, 1.856847",\ + "0.802366, 1.027718, 1.212408, 1.507630, 2.078080",\ + "1.364210, 1.589563, 1.774253, 2.069476, 2.639925",\ + "0.539804, 0.757567, 0.941939, 1.237118, 1.807467",\ + "0.589803, 0.807566, 0.991938, 1.287117, 1.857466",\ + "0.670367, 0.886817, 1.071201, 1.366425, 1.936878",\ + "0.891600, 1.108051, 1.292434, 1.587659, 2.158112",\ + "1.453444, 1.669896, 1.854280, 2.149504, 2.719957",\ + "0.603371, 0.815390, 0.999649, 1.294559, 1.864506",\ + "0.653370, 0.865389, 1.049648, 1.344558, 1.914505",\ + "0.733934, 0.944641, 1.128911, 1.423867, 1.993918",\ + "0.955166, 1.165874, 1.350144, 1.645100, 2.215151",\ + "1.517011, 1.727719, 1.911989, 2.206946, 2.776997",\ + "0.939278, 1.120654, 1.303307, 1.597741, 2.166757",\ + "0.989277, 1.170653, 1.353306, 1.647740, 2.216756",\ + "1.069831, 1.249906, 1.432569, 1.727049, 2.296169",\ + "1.291064, 1.471139, 1.653802, 1.948282, 2.517402",\ + "1.852909, 2.032984, 2.215647, 2.510128, 3.079247"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.027448, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027448, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027447, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027447, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897",\ + "0.027446, 0.027445, 0.027445, 0.027445, 0.027445",\ + "0.129491, 0.129491, 0.129491, 0.129491, 0.129491",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831920, 0.831920, 0.831920, 0.831920, 0.831920",\ + "2.131897, 2.131897, 2.131897, 2.131897, 2.131897"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.356406, 0.582783, 0.767510, 1.062709, 1.633111",\ + "0.382155, 0.608528, 0.793254, 1.088453, 1.658855",\ + "0.436803, 0.663177, 0.847903, 1.143102, 1.713504",\ + "0.586677, 0.813050, 0.997777, 1.292975, 1.863377",\ + "0.942409, 1.170095, 1.354810, 1.649963, 2.220260",\ + "0.444744, 0.670102, 0.854791, 1.150014, 1.720465",\ + "0.470493, 0.695846, 0.880535, 1.175758, 1.746208",\ + "0.525141, 0.750495, 0.935184, 1.230407, 1.800857",\ + "0.675015, 0.900368, 1.085058, 1.380280, 1.950730",\ + "1.030747, 1.257413, 1.442091, 1.737268, 2.307614",\ + "0.533979, 0.750434, 0.934818, 1.230043, 1.800496",\ + "0.559727, 0.776178, 0.960562, 1.255787, 1.826240",\ + "0.614376, 0.830827, 1.015211, 1.310436, 1.880889",\ + "0.764250, 0.980701, 1.165085, 1.460309, 2.030762",\ + "1.119983, 1.337745, 1.522118, 1.817296, 2.387645",\ + "0.597545, 0.808257, 0.992528, 1.287485, 1.857536",\ + "0.623294, 0.834002, 1.018272, 1.313228, 1.883280",\ + "0.677942, 0.888651, 1.072921, 1.367877, 1.937928",\ + "0.827816, 1.038524, 1.222794, 1.517751, 2.087802",\ + "1.183551, 1.395569, 1.579828, 1.874738, 2.444685",\ + "0.933445, 1.113522, 1.296186, 1.590666, 2.159787",\ + "0.959191, 1.139267, 1.321930, 1.616410, 2.185530",\ + "1.013840, 1.193916, 1.376579, 1.671059, 2.240179",\ + "1.163714, 1.343789, 1.526452, 1.820932, 2.390052",\ + "1.519457, 1.700833, 1.883486, 2.177920, 2.746935"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.015179, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015179, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015178, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015177, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067695, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219",\ + "0.015173, 0.015170, 0.015169, 0.015169, 0.015168",\ + "0.067694, 0.067694, 0.067694, 0.067694, 0.067694",\ + "0.170296, 0.170296, 0.170296, 0.170296, 0.170296",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122219, 1.122219, 1.122219, 1.122219, 1.122219"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2258*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[39]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.309159, 0.541794, 0.727047, 1.026481, 1.606878",\ + "0.349227, 0.581863, 0.767115, 1.066549, 1.646947",\ + "0.425113, 0.657750, 0.843001, 1.142434, 1.722832",\ + "0.644749, 0.877387, 1.062637, 1.362070, 1.942469",\ + "1.197363, 1.430001, 1.615251, 1.914684, 2.495083",\ + "0.397555, 0.629112, 0.814328, 1.113786, 1.694232",\ + "0.437623, 0.669181, 0.854396, 1.153854, 1.734300",\ + "0.513508, 0.745068, 0.930282, 1.229739, 1.810186",\ + "0.733145, 0.964705, 1.149918, 1.449375, 2.029822",\ + "1.285759, 1.517319, 1.702532, 2.001989, 2.582437",\ + "0.486858, 0.709445, 0.894355, 1.193814, 1.774263",\ + "0.526927, 0.749514, 0.934423, 1.233882, 1.814332",\ + "0.602812, 0.825401, 1.010309, 1.309767, 1.890217",\ + "0.822449, 1.045038, 1.229945, 1.529404, 2.109854",\ + "1.375063, 1.597652, 1.782559, 2.082017, 2.662468",\ + "0.550445, 0.767276, 0.952066, 1.251268, 1.831326",\ + "0.590513, 0.807345, 0.992134, 1.291336, 1.871395",\ + "0.666399, 0.883232, 1.068019, 1.367221, 1.947281",\ + "0.886036, 1.102869, 1.287656, 1.586857, 2.166918",\ + "1.438650, 1.655483, 1.840269, 2.139471, 2.719532",\ + "0.886476, 1.072598, 1.255724, 1.554460, 2.133606",\ + "0.926545, 1.112668, 1.295792, 1.594528, 2.173675",\ + "1.002432, 1.188554, 1.371677, 1.670413, 2.249560",\ + "1.222068, 1.408191, 1.591314, 1.890050, 2.469197",\ + "1.774683, 1.960806, 2.143928, 2.442663, 3.021811"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\ + "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\ + "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\ + "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317",\ + "0.048599, 0.048599, 0.048599, 0.048599, 0.048600",\ + "0.136046, 0.136046, 0.136046, 0.136046, 0.136046",\ + "0.314136, 0.314136, 0.314136, 0.314136, 0.314136",\ + "0.833556, 0.833556, 0.833556, 0.833556, 0.833556",\ + "2.135299, 2.135299, 2.135299, 2.135304, 2.135317"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.283419, 0.516054, 0.701307, 1.000741, 1.581138",\ + "0.313066, 0.545699, 0.730954, 1.030388, 1.610784",\ + "0.365001, 0.597634, 0.782889, 1.082323, 1.662719",\ + "0.513456, 0.746088, 0.931344, 1.230778, 1.811174",\ + "0.885857, 1.118488, 1.303746, 1.603180, 2.183575",\ + "0.371815, 0.603373, 0.788588, 1.088046, 1.668492",\ + "0.401461, 0.633018, 0.818235, 1.117693, 1.698138",\ + "0.453396, 0.684952, 0.870170, 1.169628, 1.750072",\ + "0.601851, 0.833406, 1.018625, 1.318083, 1.898527",\ + "0.974253, 1.205806, 1.391027, 1.690485, 2.270928",\ + "0.461119, 0.683706, 0.868615, 1.168074, 1.748523",\ + "0.490765, 0.713351, 0.898262, 1.197721, 1.778169",\ + "0.542700, 0.765285, 0.950197, 1.249656, 1.830104",\ + "0.691155, 0.913739, 1.098652, 1.398111, 1.978559",\ + "1.063556, 1.286139, 1.471054, 1.770513, 2.350960",\ + "0.524705, 0.741537, 0.926326, 1.225528, 1.805587",\ + "0.554351, 0.771182, 0.955972, 1.255175, 1.835233",\ + "0.606286, 0.823116, 1.007907, 1.307110, 1.887167",\ + "0.754741, 0.971570, 1.156362, 1.455565, 2.035622",\ + "1.127142, 1.343970, 1.528764, 1.827967, 2.408023",\ + "0.860737, 1.046859, 1.229984, 1.528720, 2.107866",\ + "0.890382, 1.076504, 1.259631, 1.558367, 2.137512",\ + "0.942317, 1.128438, 1.311566, 1.610302, 2.189447",\ + "1.090771, 1.276893, 1.460021, 1.758757, 2.337902",\ + "1.463172, 1.649293, 1.832423, 2.131159, 2.710303"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002265, 0.075263, 0.162201, 0.322138, 0.642011"); + values ( "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\ + "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\ + "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\ + "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143",\ + "0.026622, 0.026622, 0.026622, 0.026622, 0.026622",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439546, 0.439546, 0.439546, 0.439549, 0.439556",\ + "1.119113, 1.119113, 1.119113, 1.119121, 1.119143"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2336*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.409726, 0.620265, 0.806005, 1.096897, 1.655910",\ + "0.459725, 0.670264, 0.856003, 1.146896, 1.705909",\ + "0.539627, 0.750535, 0.935997, 1.226788, 1.785793",\ + "0.760860, 0.971768, 1.157229, 1.448020, 2.007025",\ + "1.322703, 1.533611, 1.719072, 2.009862, 2.568867",\ + "0.498079, 0.707583, 0.893286, 1.184203, 1.743264",\ + "0.548078, 0.757582, 0.943284, 1.234201, 1.793262",\ + "0.627981, 0.837853, 1.023278, 1.314093, 1.873147",\ + "0.849213, 1.059086, 1.244510, 1.535325, 2.094379",\ + "1.411056, 1.620929, 1.806353, 2.097167, 2.656221",\ + "0.587342, 0.787916, 0.973312, 1.264231, 1.823296",\ + "0.637340, 0.837914, 1.023311, 1.314230, 1.873294",\ + "0.717243, 0.918186, 1.103305, 1.394121, 1.953178",\ + "0.938476, 1.139418, 1.324537, 1.615354, 2.174411",\ + "1.500319, 1.701261, 1.886380, 2.177196, 2.736252",\ + "0.650926, 0.845743, 1.031024, 1.321659, 1.880308",\ + "0.700925, 0.895741, 1.081023, 1.371658, 1.930306",\ + "0.780828, 0.976013, 1.161016, 1.451549, 2.010190",\ + "1.002060, 1.197245, 1.382248, 1.672781, 2.231423",\ + "1.563903, 1.759089, 1.944091, 2.234624, 2.793264",\ + "0.970227, 1.151036, 1.334683, 1.624829, 2.182525",\ + "1.020226, 1.201034, 1.384681, 1.674827, 2.232523",\ + "1.100497, 1.281306, 1.464674, 1.754719, 2.312408",\ + "1.321730, 1.502538, 1.685907, 1.975951, 2.533640",\ + "1.883573, 2.064381, 2.247749, 2.537794, 3.095482"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027428, 0.027429, 0.027429, 0.027431",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314623, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831917",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.403233, 0.614141, 0.799601, 1.090390, 1.649393",\ + "0.428986, 0.639894, 0.825355, 1.116146, 1.675151",\ + "0.483635, 0.694543, 0.880004, 1.170794, 1.729799",\ + "0.633508, 0.844416, 1.029877, 1.320668, 1.879673",\ + "0.989900, 1.200439, 1.386178, 1.677071, 2.236084",\ + "0.491587, 0.701459, 0.886882, 1.177695, 1.736746",\ + "0.517340, 0.727212, 0.912636, 1.203451, 1.762504",\ + "0.571988, 0.781861, 0.967285, 1.258099, 1.817153",\ + "0.721862, 0.931734, 1.117158, 1.407973, 1.967026",\ + "1.078253, 1.287757, 1.473459, 1.764376, 2.323438",\ + "0.580849, 0.781792, 0.966909, 1.257724, 1.816778",\ + "0.606602, 0.807544, 0.992663, 1.283479, 1.842536",\ + "0.661251, 0.862193, 1.047312, 1.338128, 1.897184",\ + "0.811124, 1.012067, 1.197185, 1.488001, 2.047058",\ + "1.167515, 1.368089, 1.553486, 1.844405, 2.403470",\ + "0.644433, 0.839619, 1.024620, 1.315152, 1.873790",\ + "0.670186, 0.865372, 1.050374, 1.340907, 1.899548",\ + "0.724835, 0.920020, 1.105023, 1.395556, 1.954196",\ + "0.874709, 1.069894, 1.254896, 1.545429, 2.104070",\ + "1.231100, 1.425916, 1.611198, 1.901833, 2.460482",\ + "0.964103, 1.144912, 1.328278, 1.618321, 2.176007",\ + "0.989856, 1.170664, 1.354033, 1.644077, 2.201765",\ + "1.044504, 1.225313, 1.408681, 1.698726, 2.256414",\ + "1.194378, 1.375186, 1.558555, 1.848599, 2.406287",\ + "1.550400, 1.731209, 1.914856, 2.205003, 2.762699"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015187, 0.015187, 0.015189, 0.015192, 0.015197",\ + "0.067696, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2358*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.383225, 0.593036, 0.770038, 1.054268, 1.604513",\ + "0.433223, 0.643035, 0.820037, 1.104266, 1.654512",\ + "0.513146, 0.723307, 0.900324, 1.184595, 1.734933",\ + "0.734379, 0.944539, 1.121556, 1.405827, 1.956165",\ + "1.296223, 1.506382, 1.683399, 1.967670, 2.518007",\ + "0.471502, 0.680354, 0.857319, 1.141573, 1.691867",\ + "0.521500, 0.730353, 0.907318, 1.191571, 1.741865",\ + "0.601422, 0.810625, 0.987605, 1.271900, 1.822286",\ + "0.822655, 1.031858, 1.208837, 1.493132, 2.043518",\ + "1.384499, 1.593700, 1.770680, 2.054975, 2.605360",\ + "0.560557, 0.760687, 0.937346, 1.221601, 1.771898",\ + "0.610556, 0.810685, 0.987345, 1.271600, 1.821897",\ + "0.690474, 0.890957, 1.067632, 1.351929, 1.902318",\ + "0.911707, 1.112190, 1.288864, 1.573161, 2.123550",\ + "1.473551, 1.674033, 1.850707, 2.135003, 2.685391",\ + "0.623957, 0.818509, 0.995037, 1.279018, 1.828889",\ + "0.673955, 0.868507, 1.045036, 1.329017, 1.878888",\ + "0.753870, 0.948779, 1.125323, 1.409346, 1.959309",\ + "0.975103, 1.170012, 1.346555, 1.630578, 2.180541",\ + "1.536947, 1.731855, 1.908398, 2.192420, 2.742383",\ + "0.944232, 1.123764, 1.298692, 1.582179, 2.131082",\ + "0.994231, 1.173763, 1.348691, 1.632178, 2.181080",\ + "1.074451, 1.254037, 1.428978, 1.712507, 2.261501",\ + "1.295684, 1.475269, 1.650211, 1.933739, 2.482733",\ + "1.857528, 2.037112, 2.212053, 2.495582, 3.044575"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.027427, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027427, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896",\ + "0.027428, 0.027429, 0.027430, 0.027431, 0.027432",\ + "0.129493, 0.129493, 0.129493, 0.129493, 0.129493",\ + "0.314624, 0.314623, 0.314623, 0.314623, 0.314623",\ + "0.831917, 0.831917, 0.831917, 0.831917, 0.831918",\ + "2.131895, 2.131895, 2.131895, 2.131895, 2.131896"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.376757, 0.586911, 0.763927, 1.048197, 1.598532",\ + "0.402506, 0.612665, 0.789682, 1.073953, 1.624290",\ + "0.457155, 0.667314, 0.844331, 1.128602, 1.678938",\ + "0.607028, 0.817188, 0.994204, 1.278475, 1.828812",\ + "0.963398, 1.173210, 1.350212, 1.634442, 2.184688",\ + "0.465033, 0.674229, 0.851208, 1.135502, 1.685885",\ + "0.490782, 0.699983, 0.876963, 1.161258, 1.711643",\ + "0.545431, 0.754632, 0.931612, 1.215907, 1.766292",\ + "0.695304, 0.904506, 1.081485, 1.365780, 1.916165",\ + "1.051675, 1.260528, 1.437493, 1.721747, 2.272042",\ + "0.554085, 0.754561, 0.931235, 1.215531, 1.765917",\ + "0.579834, 0.780316, 0.956990, 1.241287, 1.791675",\ + "0.634483, 0.834964, 1.011639, 1.295935, 1.846323",\ + "0.784356, 0.984838, 1.161512, 1.445809, 1.996197",\ + "1.140731, 1.340860, 1.517520, 1.801775, 2.352073",\ + "0.617480, 0.812384, 0.988926, 1.272948, 1.822908",\ + "0.643230, 0.838138, 1.014681, 1.298704, 1.848666",\ + "0.697878, 0.892787, 1.069330, 1.353353, 1.903315",\ + "0.847752, 1.042660, 1.219203, 1.503226, 2.053188",\ + "1.204130, 1.398682, 1.575211, 1.859193, 2.409064",\ + "0.938061, 1.117640, 1.292582, 1.576109, 2.125101",\ + "0.963811, 1.143395, 1.318336, 1.601865, 2.150858",\ + "1.018459, 1.198044, 1.372985, 1.656513, 2.205507",\ + "1.168333, 1.347917, 1.522858, 1.806387, 2.355381",\ + "1.524406, 1.703938, 1.878866, 2.162354, 2.711256"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.015179, 0.015189, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015179, 0.015189, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015180, 0.015189, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015181, 0.015190, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218",\ + "0.015181, 0.015190, 0.015191, 0.015192, 0.015197",\ + "0.067695, 0.067696, 0.067696, 0.067696, 0.067697",\ + "0.170295, 0.170295, 0.170295, 0.170295, 0.170295",\ + "0.440750, 0.440750, 0.440750, 0.440750, 0.440750",\ + "1.122218, 1.122218, 1.122218, 1.122218, 1.122218"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2303*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[43]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.405550, 0.622555, 0.800684, 1.089918, 1.651394",\ + "0.445619, 0.662624, 0.840753, 1.129987, 1.691463",\ + "0.521505, 0.738510, 0.916639, 1.205873, 1.767349",\ + "0.741141, 0.958147, 1.136276, 1.425510, 1.986986",\ + "1.293756, 1.510761, 1.688890, 1.978124, 2.539600",\ + "0.493926, 0.709873, 0.887965, 1.177224, 1.738747",\ + "0.533995, 0.749942, 0.928034, 1.217292, 1.778816",\ + "0.609881, 0.825828, 1.003920, 1.293178, 1.854702",\ + "0.829518, 1.045465, 1.223557, 1.512815, 2.074339",\ + "1.382132, 1.598079, 1.776171, 2.065429, 2.626953",\ + "0.583177, 0.790206, 0.967992, 1.257252, 1.818779",\ + "0.623246, 0.830275, 1.008061, 1.297321, 1.858848",\ + "0.699132, 0.906161, 1.083947, 1.373207, 1.934734",\ + "0.918768, 1.125798, 1.303584, 1.592844, 2.154371",\ + "1.471382, 1.678412, 1.856198, 2.145458, 2.706985",\ + "0.646716, 0.848023, 1.025686, 1.314683, 1.875797",\ + "0.686785, 0.888092, 1.065755, 1.354752, 1.915866",\ + "0.762671, 0.963978, 1.141641, 1.430638, 1.991752",\ + "0.982307, 1.183615, 1.361278, 1.650275, 2.211389",\ + "1.534921, 1.736229, 1.913892, 2.202889, 2.764003",\ + "0.974642, 1.153245, 1.329341, 1.617855, 2.178021",\ + "1.014711, 1.193314, 1.369410, 1.657924, 2.218090",\ + "1.090597, 1.269200, 1.445296, 1.733810, 2.293976",\ + "1.310234, 1.488837, 1.664933, 1.953447, 2.513613",\ + "1.862848, 2.041451, 2.217547, 2.506061, 3.066227"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833559, 0.833558",\ + "2.135322, 2.135322, 2.135323, 2.135323, 2.135323"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.379810, 0.596815, 0.774944, 1.064179, 1.625654",\ + "0.409456, 0.626461, 0.804590, 1.093824, 1.655300",\ + "0.461390, 0.678396, 0.856524, 1.145759, 1.707235",\ + "0.609845, 0.826850, 1.004979, 1.294214, 1.855689",\ + "0.982246, 1.199251, 1.377380, 1.666614, 2.228090",\ + "0.468186, 0.684134, 0.862225, 1.151484, 1.713008",\ + "0.497832, 0.713779, 0.891871, 1.181129, 1.742653",\ + "0.549766, 0.765714, 0.943805, 1.233064, 1.794588",\ + "0.698221, 0.914169, 1.092260, 1.381519, 1.943043",\ + "1.070622, 1.286569, 1.464661, 1.753919, 2.315443",\ + "0.557437, 0.764467, 0.942252, 1.231513, 1.793039",\ + "0.587083, 0.794112, 0.971898, 1.261158, 1.822685",\ + "0.639017, 0.846047, 1.023832, 1.313093, 1.874619",\ + "0.787472, 0.994502, 1.172287, 1.461547, 2.023074",\ + "1.159873, 1.366902, 1.544688, 1.833948, 2.395475",\ + "0.620976, 0.822284, 0.999946, 1.288943, 1.850057",\ + "0.650622, 0.851929, 1.029592, 1.318589, 1.879703",\ + "0.702556, 0.903864, 1.081526, 1.370523, 1.931637",\ + "0.851011, 1.052318, 1.229981, 1.518978, 2.080092",\ + "1.223412, 1.424719, 1.602382, 1.891379, 2.452493",\ + "0.948902, 1.127506, 1.303602, 1.592116, 2.152281",\ + "0.978548, 1.157151, 1.333247, 1.621761, 2.181927",\ + "1.030483, 1.209086, 1.385182, 1.673696, 2.233861",\ + "1.178937, 1.357541, 1.533637, 1.822151, 2.382316",\ + "1.551338, 1.729941, 1.906037, 2.194551, 2.754717"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002272, 0.075270, 0.162206, 0.322141, 0.642011"); + values ( "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026625",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439544, 0.439544, 0.439546, 0.439549",\ + "1.119108, 1.119108, 1.119109, 1.119113, 1.119123"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2271*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[44]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.386364, 0.626816, 0.817125, 1.119925, 1.704580",\ + "0.426433, 0.666885, 0.857194, 1.159994, 1.744649",\ + "0.502319, 0.742771, 0.933080, 1.235880, 1.820535",\ + "0.721956, 0.962408, 1.152717, 1.455517, 2.040172",\ + "1.274570, 1.515022, 1.705331, 2.008131, 2.592786",\ + "0.474664, 0.714134, 0.904406, 1.207230, 1.791934",\ + "0.514733, 0.754203, 0.944475, 1.247299, 1.832002",\ + "0.590619, 0.830089, 1.020361, 1.323185, 1.907888",\ + "0.810256, 1.049726, 1.239998, 1.542822, 2.127525",\ + "1.362870, 1.602340, 1.792612, 2.095436, 2.680139",\ + "0.563948, 0.794465, 0.984433, 1.287259, 1.871965",\ + "0.604017, 0.834534, 1.024502, 1.327327, 1.912034",\ + "0.679903, 0.910420, 1.100388, 1.403213, 1.987920",\ + "0.899539, 1.130056, 1.320024, 1.622850, 2.207557",\ + "1.452153, 1.682670, 1.872638, 2.175464, 2.760171",\ + "0.627629, 0.852329, 1.042155, 1.344718, 1.929040",\ + "0.667698, 0.892398, 1.082224, 1.384787, 1.969109",\ + "0.743584, 0.968284, 1.158110, 1.460673, 2.044995",\ + "0.963221, 1.187921, 1.377747, 1.680310, 2.264632",\ + "1.515835, 1.740535, 1.930361, 2.232924, 2.817246",\ + "0.964253, 1.157875, 1.345814, 1.647914, 2.231333",\ + "1.004322, 1.197944, 1.385883, 1.687983, 2.271402",\ + "1.080208, 1.273830, 1.461769, 1.763869, 2.347288",\ + "1.299845, 1.493467, 1.681406, 1.983506, 2.566925",\ + "1.852459, 2.046081, 2.234020, 2.536120, 3.119539"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135322, 2.135323, 2.135323, 2.135323, 2.135323",\ + "0.048600, 0.048600, 0.048600, 0.048600, 0.048600",\ + "0.136047, 0.136047, 0.136047, 0.136047, 0.136047",\ + "0.314137, 0.314137, 0.314137, 0.314137, 0.314137",\ + "0.833559, 0.833559, 0.833559, 0.833558, 0.833558",\ + "2.135323, 2.135323, 2.135323, 2.135323, 2.135323"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.360625, 0.601076, 0.791385, 1.094185, 1.678841",\ + "0.390270, 0.630722, 0.821031, 1.123831, 1.708486",\ + "0.442205, 0.682656, 0.872965, 1.175765, 1.760421",\ + "0.590660, 0.831111, 1.021420, 1.324220, 1.908875",\ + "0.963060, 1.203512, 1.393821, 1.696621, 2.281276",\ + "0.448924, 0.688394, 0.878666, 1.181490, 1.766194",\ + "0.478570, 0.718040, 0.908312, 1.211136, 1.795840",\ + "0.530504, 0.769974, 0.960246, 1.263070, 1.847774",\ + "0.678959, 0.918429, 1.108701, 1.411525, 1.996229",\ + "1.051360, 1.290830, 1.481102, 1.783926, 2.368629",\ + "0.538208, 0.768725, 0.958693, 1.261519, 1.846226",\ + "0.567854, 0.798371, 0.988339, 1.291164, 1.875871",\ + "0.619788, 0.850305, 1.040273, 1.343099, 1.927806",\ + "0.768243, 0.998760, 1.188728, 1.491554, 2.076260",\ + "1.140644, 1.371161, 1.561129, 1.863954, 2.448661",\ + "0.601890, 0.826589, 1.016415, 1.318978, 1.903300",\ + "0.631535, 0.856235, 1.046061, 1.348624, 1.932946",\ + "0.683470, 0.908169, 1.097996, 1.400558, 1.984880",\ + "0.831925, 1.056624, 1.246450, 1.549013, 2.133335",\ + "1.204325, 1.429025, 1.618851, 1.921414, 2.505736",\ + "0.938514, 1.132136, 1.320075, 1.622174, 2.205594",\ + "0.968159, 1.161781, 1.349720, 1.651820, 2.235239",\ + "1.020094, 1.213716, 1.401655, 1.703755, 2.287174",\ + "1.168548, 1.362170, 1.550110, 1.852209, 2.435628",\ + "1.540949, 1.734571, 1.922510, 2.224610, 2.808029"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002742, 0.075741, 0.162559, 0.322376, 0.642011"); + values ( "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119107, 1.119112, 1.119115, 1.119119, 1.119125",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119107, 1.119112, 1.119115, 1.119119, 1.119125",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119108, 1.119112, 1.119115, 1.119119, 1.119125",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439544, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119108, 1.119112, 1.119115, 1.119119, 1.119125",\ + "0.026625, 0.026625, 0.026625, 0.026625, 0.026624",\ + "0.075785, 0.075785, 0.075785, 0.075785, 0.075785",\ + "0.169304, 0.169304, 0.169304, 0.169304, 0.169303",\ + "0.439545, 0.439546, 0.439547, 0.439548, 0.439550",\ + "1.119111, 1.119112, 1.119115, 1.119119, 1.119125"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2441*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[46]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.401355, 0.623039, 0.801084, 1.090019, 1.650864",\ + "0.444265, 0.665948, 0.843993, 1.132928, 1.693773",\ + "0.520764, 0.742448, 0.920493, 1.209427, 1.770273",\ + "0.744064, 0.965747, 1.143793, 1.432727, 1.993572",\ + "1.303239, 1.524854, 1.702965, 1.991765, 2.552283",\ + "0.489764, 0.710357, 0.888365, 1.177324, 1.738218",\ + "0.532673, 0.753266, 0.931274, 1.220233, 1.781127",\ + "0.609173, 0.829766, 1.007774, 1.296732, 1.857626",\ + "0.832472, 1.053066, 1.231073, 1.520032, 2.080926",\ + "1.391647, 1.612173, 1.790246, 2.079070, 2.639636",\ + "0.578854, 0.790693, 0.968392, 1.257352, 1.818249",\ + "0.621763, 0.833602, 1.011301, 1.300261, 1.861158",\ + "0.698263, 0.910101, 1.087801, 1.376761, 1.937658",\ + "0.921562, 1.133401, 1.311100, 1.600060, 2.160957",\ + "1.480738, 1.692508, 1.870273, 2.159099, 2.719668",\ + "0.642132, 0.848514, 1.026085, 1.314782, 1.875265",\ + "0.685041, 0.891423, 1.068994, 1.357691, 1.918174",\ + "0.761541, 0.967922, 1.145494, 1.434191, 1.994673",\ + "0.984840, 1.191222, 1.368793, 1.657490, 2.217973",\ + "1.544015, 1.750334, 1.927966, 2.216528, 2.776682",\ + "0.973287, 1.153774, 1.329742, 1.617954, 2.177485",\ + "1.016196, 1.196683, 1.372651, 1.660863, 2.220395",\ + "1.092696, 1.273183, 1.449150, 1.737363, 2.296894",\ + "1.315995, 1.496482, 1.672450, 1.960662, 2.520194",\ + "1.874038, 2.055627, 2.231622, 2.519700, 3.078903"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833612, 0.833612, 0.833612, 0.833613",\ + "2.135107, 2.135107, 2.135107, 2.135106, 2.135106"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.389319, 0.610934, 0.789045, 1.077845, 1.638363",\ + "0.418979, 0.640595, 0.818706, 1.107506, 1.668024",\ + "0.470920, 0.692535, 0.870646, 1.159446, 1.719964",\ + "0.619380, 0.840995, 1.019106, 1.307906, 1.868424",\ + "0.983284, 1.204968, 1.383013, 1.671947, 2.232793",\ + "0.477727, 0.698253, 0.876326, 1.165150, 1.725716",\ + "0.507388, 0.727914, 0.905987, 1.194811, 1.755377",\ + "0.559328, 0.779854, 0.957927, 1.246751, 1.807317",\ + "0.707788, 0.928314, 1.106387, 1.395211, 1.955777",\ + "1.071693, 1.292286, 1.470294, 1.759253, 2.320147",\ + "0.566817, 0.778588, 0.956353, 1.245178, 1.805748",\ + "0.596478, 0.808249, 0.986014, 1.274839, 1.835409",\ + "0.648419, 0.860189, 1.037954, 1.326780, 1.887349",\ + "0.796878, 1.008649, 1.186414, 1.475240, 2.035809",\ + "1.160783, 1.372622, 1.550321, 1.839281, 2.400178",\ + "0.630095, 0.836414, 1.014046, 1.302608, 1.862762",\ + "0.659756, 0.866074, 1.043707, 1.332269, 1.892423",\ + "0.711696, 0.918015, 1.095647, 1.384209, 1.944364",\ + "0.860156, 1.066475, 1.244107, 1.532669, 2.092824",\ + "1.224061, 1.430443, 1.608014, 1.896711, 2.457193",\ + "0.960117, 1.141707, 1.317702, 1.605780, 2.164983",\ + "0.989778, 1.171368, 1.347363, 1.635441, 2.194643",\ + "1.041718, 1.223308, 1.399303, 1.687381, 2.246584",\ + "1.190178, 1.371768, 1.547763, 1.835841, 2.395044",\ + "1.555216, 1.735703, 1.911671, 2.199883, 2.759414"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439562, 0.439562, 0.439561",\ + "1.119158, 1.119158, 1.119158, 1.119158, 1.119157"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2497*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[47]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.380051, 0.607077, 0.791540, 1.086441, 1.656420",\ + "0.422960, 0.649986, 0.834449, 1.129350, 1.699329",\ + "0.499459, 0.726486, 0.910949, 1.205850, 1.775828",\ + "0.722759, 0.949785, 1.134248, 1.429149, 1.999128",\ + "1.281942, 1.507667, 1.692145, 1.987100, 2.557201",\ + "0.468382, 0.694395, 0.878821, 1.173746, 1.743773",\ + "0.511291, 0.737304, 0.921730, 1.216655, 1.786682",\ + "0.587791, 0.813804, 0.998230, 1.293155, 1.863182",\ + "0.811090, 1.037103, 1.221529, 1.516454, 2.086481",\ + "1.370273, 1.594985, 1.779426, 2.074405, 2.644555",\ + "0.557789, 0.774725, 0.958848, 1.253775, 1.823805",\ + "0.600698, 0.817634, 1.001757, 1.296684, 1.866714",\ + "0.677198, 0.894134, 1.078257, 1.373183, 1.943213",\ + "0.900497, 1.117434, 1.301556, 1.596483, 2.166513",\ + "1.459679, 1.675315, 1.859452, 2.154434, 2.724586",\ + "0.621599, 0.832548, 1.016557, 1.311216, 1.880844",\ + "0.664508, 0.875457, 1.059467, 1.354125, 1.923753",\ + "0.741007, 0.951957, 1.135966, 1.430625, 2.000253",\ + "0.964307, 1.175256, 1.359266, 1.653924, 2.223552",\ + "1.523487, 1.733139, 1.917162, 2.211875, 2.781626",\ + "0.958721, 1.137805, 1.320215, 1.614397, 2.183095",\ + "1.001630, 1.180714, 1.363124, 1.657306, 2.226004",\ + "1.078130, 1.257213, 1.439624, 1.733806, 2.302503",\ + "1.301429, 1.480513, 1.662923, 1.957105, 2.525803",\ + "1.859271, 2.038396, 2.220819, 2.515056, 3.083877"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136075, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136075, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105",\ + "0.048588, 0.048588, 0.048588, 0.048588, 0.048588",\ + "0.136076, 0.136076, 0.136076, 0.136076, 0.136076",\ + "0.314168, 0.314168, 0.314168, 0.314168, 0.314168",\ + "0.833612, 0.833613, 0.833613, 0.833613, 0.833613",\ + "2.135108, 2.135106, 2.135105, 2.135105, 2.135105"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.368022, 0.593747, 0.778225, 1.073180, 1.643281",\ + "0.397682, 0.623408, 0.807886, 1.102841, 1.672942",\ + "0.449623, 0.675348, 0.859826, 1.154781, 1.724883",\ + "0.598083, 0.823808, 1.008286, 1.303241, 1.873343",\ + "0.961980, 1.189006, 1.373469, 1.668370, 2.238349",\ + "0.456353, 0.681065, 0.865506, 1.160485, 1.730635",\ + "0.486014, 0.710726, 0.895167, 1.190146, 1.760296",\ + "0.537954, 0.762666, 0.947107, 1.242086, 1.812236",\ + "0.686414, 0.911126, 1.095567, 1.390546, 1.960696",\ + "1.050311, 1.276324, 1.460750, 1.755675, 2.325702",\ + "0.545759, 0.761395, 0.945533, 1.240514, 1.810667",\ + "0.575419, 0.791056, 0.975194, 1.270175, 1.840328",\ + "0.627360, 0.842997, 1.027134, 1.322115, 1.892268",\ + "0.775819, 0.991457, 1.175594, 1.470575, 2.040728",\ + "1.139718, 1.356654, 1.540777, 1.835704, 2.405734",\ + "0.609567, 0.819218, 1.003242, 1.297955, 1.867706",\ + "0.639228, 0.848879, 1.032903, 1.327616, 1.897367",\ + "0.691168, 0.900820, 1.084843, 1.379556, 1.949308",\ + "0.839628, 1.049280, 1.233303, 1.528016, 2.097767",\ + "1.203528, 1.414477, 1.598486, 1.893145, 2.462773",\ + "0.945351, 1.124476, 1.306899, 1.601136, 2.169957",\ + "0.975012, 1.154137, 1.336560, 1.630797, 2.199618",\ + "1.026952, 1.206077, 1.388500, 1.682738, 2.251558",\ + "1.175412, 1.354537, 1.536960, 1.831198, 2.400018",\ + "1.540650, 1.719733, 1.902144, 2.196326, 2.765023"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001581, 0.004543, 0.013052, 0.034401"); + index_3 ( "0.002792, 0.075790, 0.162597, 0.322401, 0.642011"); + values ( "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119158, 1.119157, 1.119157, 1.119157",\ + "0.026623, 0.026623, 0.026623, 0.026623, 0.026623",\ + "0.075784, 0.075784, 0.075784, 0.075784, 0.075784",\ + "0.169301, 0.169301, 0.169301, 0.169301, 0.169301",\ + "0.439562, 0.439562, 0.439561, 0.439561, 0.439561",\ + "1.119159, 1.119157, 1.119157, 1.119157, 1.119157"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[3]_redg_min_2420*/ + +} /* end of pin tl_o[3] */ + +pin("tl_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.020161 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.596162, 0.867359, 1.159405, 1.656731, 2.651384",\ + "0.643260, 0.914475, 1.206618, 1.704208, 2.699388",\ + "0.730525, 1.001791, 1.294214, 1.792557, 2.789245",\ + "0.956361, 1.227706, 1.520560, 2.020066, 3.019080",\ + "1.523589, 1.795036, 2.088453, 2.589476, 3.591523",\ + "0.683575, 0.954952, 1.247062, 1.743446, 2.737318",\ + "0.730672, 1.002068, 1.294276, 1.790923, 2.785322",\ + "0.817938, 1.089384, 1.381874, 1.879272, 2.875178",\ + "1.043774, 1.315300, 1.608224, 2.106781, 3.105014",\ + "1.611001, 1.882631, 2.176121, 2.676191, 3.677457",\ + "0.766406, 1.044042, 1.335028, 1.831069, 2.824273",\ + "0.813504, 1.091158, 1.382242, 1.878545, 2.872277",\ + "0.900771, 1.178475, 1.469840, 1.966895, 2.962133",\ + "1.126608, 1.404392, 1.696190, 2.194404, 3.191969",\ + "1.693838, 1.971725, 2.264088, 2.763813, 3.764412",\ + "0.829815, 1.109836, 1.399173, 1.894982, 2.887782",\ + "0.876913, 1.156952, 1.446387, 1.942459, 2.935786",\ + "0.964180, 1.244271, 1.533985, 2.030808, 3.025642",\ + "1.190018, 1.470190, 1.760335, 2.258317, 3.255478",\ + "1.757249, 2.037525, 2.328233, 2.827727, 3.827921",\ + "1.164720, 1.476052, 1.751329, 2.244448, 3.233238",\ + "1.211820, 1.523174, 1.798545, 2.291926, 3.281242",\ + "1.299091, 1.610508, 1.886151, 2.380279, 3.371099",\ + "1.524935, 1.836451, 2.112513, 2.607793, 3.600934",\ + "2.092175, 2.403818, 2.680427, 3.177208, 4.173377"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.053862, 0.053914, 0.054909, 0.058152, 0.064638",\ + "0.173267, 0.173231, 0.173035, 0.172508, 0.171453",\ + "0.375460, 0.375376, 0.374957, 0.373858, 0.371660",\ + "0.885481, 0.885445, 0.885292, 0.884908, 0.884140",\ + "2.163051, 2.163105, 2.163316, 2.163829, 2.164857",\ + "0.053862, 0.053914, 0.054919, 0.058152, 0.064638",\ + "0.173267, 0.173231, 0.173034, 0.172508, 0.171453",\ + "0.375460, 0.375376, 0.374953, 0.373858, 0.371660",\ + "0.885481, 0.885444, 0.885291, 0.884908, 0.884140",\ + "2.163051, 2.163105, 2.163317, 2.163829, 2.164857",\ + "0.053863, 0.053915, 0.054919, 0.058152, 0.064638",\ + "0.173266, 0.173230, 0.173034, 0.172508, 0.171453",\ + "0.375459, 0.375374, 0.374953, 0.373858, 0.371660",\ + "0.885480, 0.885444, 0.885290, 0.884908, 0.884140",\ + "2.163052, 2.163106, 2.163317, 2.163829, 2.164857",\ + "0.053864, 0.053916, 0.054920, 0.058152, 0.064638",\ + "0.173266, 0.173229, 0.173034, 0.172508, 0.171453",\ + "0.375457, 0.375372, 0.374953, 0.373858, 0.371660",\ + "0.885480, 0.885443, 0.885290, 0.884908, 0.884140",\ + "2.163053, 2.163108, 2.163317, 2.163829, 2.164857",\ + "0.053868, 0.053932, 0.054952, 0.058165, 0.064638",\ + "0.173263, 0.173218, 0.173028, 0.172506, 0.171453",\ + "0.375451, 0.375346, 0.374942, 0.373853, 0.371660",\ + "0.885476, 0.885432, 0.885287, 0.884906, 0.884140",\ + "2.163059, 2.163123, 2.163322, 2.163831, 2.164857"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.526597, 0.797546, 1.089766, 1.588771, 2.586781",\ + "0.587519, 0.858706, 1.150697, 1.647877, 2.642235",\ + "0.654254, 0.925628, 1.218645, 1.718590, 2.718481",\ + "0.788462, 1.059820, 1.352751, 1.852464, 2.851889",\ + "1.131923, 1.403187, 1.695595, 2.193900, 3.190510",\ + "0.614010, 0.885137, 1.177429, 1.675486, 2.672715",\ + "0.674932, 0.946299, 1.238354, 1.734592, 2.728169",\ + "0.741667, 1.013223, 1.306311, 1.805305, 2.804415",\ + "0.875874, 1.147414, 1.440416, 1.939178, 2.937823",\ + "1.219336, 1.490780, 1.783256, 2.280615, 3.276443",\ + "0.696837, 0.974222, 1.265395, 1.763108, 2.759670",\ + "0.757763, 1.035389, 1.326320, 1.822214, 2.815124",\ + "0.824502, 1.102316, 1.394277, 1.892928, 2.891370",\ + "0.958709, 1.236507, 1.528382, 2.026801, 3.024778",\ + "1.302169, 1.579871, 1.871222, 2.368237, 3.363399",\ + "0.760242, 1.040009, 1.329540, 1.827022, 2.823179",\ + "0.821171, 1.101182, 1.390465, 1.886127, 2.878633",\ + "0.887912, 1.168114, 1.458422, 1.956841, 2.954879",\ + "1.022119, 1.302305, 1.592527, 2.090714, 3.088287",\ + "1.365578, 1.645666, 1.935366, 2.432151, 3.426908",\ + "1.095129, 1.406150, 1.681713, 2.176495, 3.168635",\ + "1.156076, 1.467395, 1.742619, 2.235593, 3.224089",\ + "1.222832, 1.534384, 1.810604, 2.306318, 3.300335",\ + "1.357038, 1.668570, 1.944707, 2.440191, 3.433743",\ + "1.700489, 2.011903, 2.287532, 2.781621, 3.772364"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.071571, 0.071932, 0.073911, 0.079246, 0.089916",\ + "0.129642, 0.130131, 0.132813, 0.140046, 0.154511",\ + "0.213984, 0.214431, 0.216880, 0.223483, 0.236689",\ + "0.447086, 0.447136, 0.447410, 0.448149, 0.449626",\ + "1.100696, 1.100673, 1.100546, 1.100205, 1.099521",\ + "0.071571, 0.071935, 0.073927, 0.079246, 0.089916",\ + "0.129642, 0.130135, 0.132836, 0.140046, 0.154511",\ + "0.213984, 0.214435, 0.216901, 0.223483, 0.236689",\ + "0.447086, 0.447137, 0.447412, 0.448149, 0.449626",\ + "1.100696, 1.100673, 1.100545, 1.100205, 1.099521",\ + "0.071578, 0.071942, 0.073928, 0.079246, 0.089916",\ + "0.129651, 0.130144, 0.132837, 0.140046, 0.154511",\ + "0.213993, 0.214443, 0.216901, 0.223483, 0.236689",\ + "0.447087, 0.447137, 0.447412, 0.448149, 0.449626",\ + "1.100696, 1.100673, 1.100545, 1.100205, 1.099521",\ + "0.071582, 0.071951, 0.073929, 0.079246, 0.089916",\ + "0.129657, 0.130157, 0.132838, 0.140046, 0.154511",\ + "0.213998, 0.214454, 0.216902, 0.223483, 0.236689",\ + "0.447088, 0.447139, 0.447413, 0.448149, 0.449626",\ + "1.100696, 1.100672, 1.100545, 1.100205, 1.099521",\ + "0.071611, 0.072061, 0.073983, 0.079268, 0.089916",\ + "0.129696, 0.130306, 0.132911, 0.140076, 0.154511",\ + "0.214033, 0.214590, 0.216969, 0.223510, 0.236689",\ + "0.447092, 0.447154, 0.447420, 0.448152, 0.449626",\ + "1.100694, 1.100665, 1.100542, 1.100203, 1.099521"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2642*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.620483, 0.875327, 1.158797, 1.657448, 2.654750",\ + "0.666691, 0.921535, 1.205006, 1.703663, 2.700977",\ + "0.750941, 1.005785, 1.289255, 1.787906, 2.785209",\ + "0.971936, 1.226783, 1.510836, 2.011498, 3.012820",\ + "1.532384, 1.787236, 2.072631, 2.577909, 3.588464",\ + "0.707891, 0.962871, 1.246456, 1.744162, 2.740684",\ + "0.754100, 1.009078, 1.292665, 1.790377, 2.786911",\ + "0.838350, 1.093329, 1.376915, 1.874621, 2.871142",\ + "1.059345, 1.314327, 1.598502, 2.098212, 3.098754",\ + "1.619793, 1.874780, 2.160311, 2.664623, 3.674398",\ + "0.788766, 1.051830, 1.334422, 1.831784, 2.827639",\ + "0.834975, 1.098037, 1.380631, 1.877999, 2.873866",\ + "0.919225, 1.182288, 1.464880, 1.962242, 2.958097",\ + "1.140220, 1.403286, 1.686468, 2.185834, 3.185709",\ + "1.700668, 1.963739, 2.248277, 2.752245, 3.761353",\ + "0.848948, 1.117433, 1.398566, 1.895697, 2.891148",\ + "0.895156, 1.163640, 1.444775, 1.941912, 2.937375",\ + "0.979406, 1.247891, 1.529024, 2.026155, 3.021606",\ + "1.200402, 1.468889, 1.750613, 2.249747, 3.249218",\ + "1.760850, 2.029342, 2.312423, 2.816158, 3.824862",\ + "1.183848, 1.481469, 1.750734, 2.245165, 3.236604",\ + "1.230056, 1.527677, 1.796943, 2.291380, 3.282831",\ + "1.314306, 1.611928, 1.881192, 2.375623, 3.367063",\ + "1.535303, 1.832926, 2.102801, 2.599223, 3.594674",\ + "2.095753, 2.393380, 2.664657, 3.165653, 4.170318"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\ + "0.885930, 0.885935, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\ + "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\ + "0.885930, 0.885935, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\ + "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\ + "0.885930, 0.885935, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\ + "0.052746, 0.052746, 0.052770, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178378, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381650, 0.381714, 0.381841",\ + "0.885931, 0.885935, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162427, 2.162551, 2.162801",\ + "0.052746, 0.052746, 0.052771, 0.052852, 0.053015",\ + "0.178338, 0.178338, 0.178380, 0.178516, 0.178792",\ + "0.381631, 0.381631, 0.381651, 0.381714, 0.381841",\ + "0.885932, 0.885936, 0.885937, 0.885937, 0.885937",\ + "2.162390, 2.162390, 2.162428, 2.162552, 2.162801"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.568910, 0.823730, 1.112547, 1.629674, 2.663928",\ + "0.612218, 0.867064, 1.154057, 1.664859, 2.686463",\ + "0.668015, 0.922863, 1.208574, 1.714952, 2.727708",\ + "0.803644, 1.058488, 1.343000, 1.845245, 2.849735",\ + "1.152943, 1.407785, 1.691260, 2.189933, 3.187279",\ + "0.656319, 0.911274, 1.200265, 1.716388, 2.749862",\ + "0.699627, 0.954607, 1.241755, 1.751573, 2.772397",\ + "0.755424, 1.010406, 1.296258, 1.801666, 2.813642",\ + "0.891053, 1.146032, 1.430671, 1.931960, 2.935669",\ + "1.240352, 1.495328, 1.778919, 2.276647, 3.273213",\ + "0.737194, 1.000233, 1.288231, 1.804010, 2.836817",\ + "0.780502, 1.043566, 1.329721, 1.839195, 2.859352",\ + "0.836299, 1.099365, 1.384223, 1.889288, 2.900597",\ + "0.971928, 1.234991, 1.518637, 2.019581, 3.022624",\ + "1.321227, 1.584288, 1.866885, 2.364269, 3.360168",\ + "0.797372, 1.065835, 1.352379, 1.867923, 2.900326",\ + "0.840683, 1.109169, 1.393867, 1.903108, 2.922861",\ + "0.896481, 1.164968, 1.448369, 1.953201, 2.964106",\ + "1.032109, 1.300594, 1.582782, 2.083494, 3.086133",\ + "1.381408, 1.649890, 1.931029, 2.428182, 3.423677",\ + "1.132264, 1.429870, 1.704734, 2.217468, 3.245782",\ + "1.175584, 1.473206, 1.746158, 2.252626, 3.268317",\ + "1.231382, 1.529005, 1.800615, 2.302701, 3.309562",\ + "1.367010, 1.664631, 1.934986, 2.432977, 3.431589",\ + "1.716307, 2.013927, 2.283197, 2.777650, 3.769133"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095973, 0.095695, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\ + "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095972, 0.095695, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\ + "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095972, 0.095695, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\ + "0.046309, 0.046309, 0.046284, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095972, 0.095695, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605",\ + "0.046309, 0.046309, 0.046283, 0.046200, 0.046032",\ + "0.096054, 0.096054, 0.095970, 0.095693, 0.095137",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443993",\ + "1.101657, 1.101657, 1.101653, 1.101637, 1.101605"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2640*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.197465, 0.431884, 0.691143, 1.132576, 2.015443",\ + "0.256904, 0.482244, 0.742878, 1.186420, 2.073503",\ + "0.340726, 0.558560, 0.820216, 1.263968, 2.151470",\ + "0.552743, 0.766273, 1.030363, 1.473596, 2.360062",\ + "1.106694, 1.318615, 1.585993, 2.032644, 2.925946",\ + "0.284867, 0.519390, 0.778620, 1.219289, 2.101377",\ + "0.344307, 0.569755, 0.830361, 1.273133, 2.159437",\ + "0.428128, 0.646078, 0.907700, 1.350681, 2.237404",\ + "0.640145, 0.853808, 1.117845, 1.560309, 2.445995",\ + "1.194097, 1.406166, 1.673486, 2.119357, 3.011879",\ + "0.365670, 0.608240, 0.866580, 1.306910, 2.188332",\ + "0.425121, 0.658616, 0.918322, 1.360754, 2.246392",\ + "0.508950, 0.734952, 0.995661, 1.438301, 2.324359",\ + "0.720977, 0.942721, 1.205806, 1.647930, 2.532950",\ + "1.274933, 1.495112, 1.761447, 2.206978, 3.098835",\ + "0.423291, 0.673682, 0.930715, 1.370823, 2.251841",\ + "0.482765, 0.724074, 0.982457, 1.424666, 2.309901",\ + "0.566610, 0.800431, 1.059796, 1.502214, 2.387868",\ + "0.778657, 1.008255, 1.269941, 1.711842, 2.596459",\ + "1.332621, 1.560694, 1.825583, 2.270890, 3.162344",\ + "0.752280, 1.035917, 1.282299, 1.720049, 2.597297",\ + "0.801700, 1.086498, 1.334062, 1.773901, 2.655357",\ + "0.877280, 1.163095, 1.411404, 1.851450, 2.733324",\ + "1.083334, 1.371566, 1.621543, 2.061076, 2.941916",\ + "1.635803, 1.924576, 2.177220, 2.620138, 3.507800"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.177313, 0.213506, 0.303388, 0.457575, 0.765950",\ + "0.250045, 0.279683, 0.356813, 0.520203, 0.846983",\ + "0.414563, 0.415723, 0.459642, 0.603351, 0.890769",\ + "0.887841, 0.887858, 0.923884, 1.046147, 1.290675",\ + "2.163213, 2.163213, 2.177271, 2.225014, 2.320500",\ + "0.177313, 0.213805, 0.303871, 0.457575, 0.765950",\ + "0.250045, 0.279878, 0.357325, 0.520203, 0.846983",\ + "0.414563, 0.415734, 0.460093, 0.603351, 0.890769",\ + "0.887841, 0.887859, 0.924267, 1.046147, 1.290675",\ + "2.163213, 2.163213, 2.177421, 2.225014, 2.320500",\ + "0.177336, 0.214457, 0.303880, 0.457575, 0.765950",\ + "0.250094, 0.280303, 0.357335, 0.520203, 0.846983",\ + "0.414563, 0.415757, 0.460101, 0.603351, 0.890769",\ + "0.887841, 0.887859, 0.924274, 1.046147, 1.290675",\ + "2.163213, 2.163213, 2.177424, 2.225014, 2.320500",\ + "0.177382, 0.215405, 0.303907, 0.457575, 0.765950",\ + "0.250194, 0.280922, 0.357363, 0.520203, 0.846983",\ + "0.414563, 0.415792, 0.460126, 0.603351, 0.890769",\ + "0.887841, 0.887859, 0.924295, 1.046147, 1.290675",\ + "2.163213, 2.163213, 2.177432, 2.225014, 2.320500",\ + "0.179823, 0.226531, 0.305470, 0.458210, 0.765950",\ + "0.255480, 0.288180, 0.359019, 0.520875, 0.846983",\ + "0.414563, 0.416192, 0.461583, 0.603943, 0.890769",\ + "0.887841, 0.887865, 0.925535, 1.046651, 1.290675",\ + "2.163213, 2.163213, 2.177916, 2.225211, 2.320500"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.186444, 0.372257, 0.626401, 1.055911, 1.914929",\ + "0.215837, 0.420150, 0.691942, 1.154794, 2.080498",\ + "0.262380, 0.480818, 0.763209, 1.249238, 2.221297",\ + "0.391146, 0.611553, 0.905194, 1.430347, 2.480653",\ + "0.735395, 0.947247, 1.249008, 1.808760, 2.928262",\ + "0.273847, 0.459753, 0.713841, 1.142624, 2.000862",\ + "0.303239, 0.507698, 0.779487, 1.241508, 2.166432",\ + "0.349783, 0.568392, 0.850825, 1.335951, 2.307231",\ + "0.478548, 0.699125, 0.992933, 1.517060, 2.566586",\ + "0.822797, 1.034805, 1.336856, 1.895473, 3.014196",\ + "0.354708, 0.548579, 0.801801, 1.230244, 2.087817",\ + "0.384100, 0.596639, 0.867448, 1.329128, 2.253387",\ + "0.430643, 0.657388, 0.938789, 1.423572, 2.394186",\ + "0.559400, 0.788117, 1.080899, 1.604681, 2.653542",\ + "0.903640, 1.123767, 1.424824, 1.983094, 3.101151",\ + "0.412447, 0.613987, 0.865934, 1.294157, 2.151326",\ + "0.441838, 0.662214, 0.931587, 1.393041, 2.316896",\ + "0.488379, 0.723043, 1.002931, 1.487485, 2.457695",\ + "0.617120, 0.853767, 1.145048, 1.668593, 2.717051",\ + "0.961342, 1.189372, 1.488979, 2.047006, 3.164660",\ + "0.716098, 0.975821, 1.217396, 1.643334, 2.496783",\ + "0.745485, 1.026006, 1.283388, 1.742355, 2.662352",\ + "0.795750, 1.087780, 1.354967, 1.836895, 2.803151",\ + "0.926660, 1.218436, 1.497480, 2.018165, 3.062507",\ + "1.264652, 1.553524, 1.841762, 2.396720, 3.510116"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.071183, 0.106877, 0.175281, 0.296416, 0.538687",\ + "0.120882, 0.144932, 0.213033, 0.350090, 0.624205",\ + "0.200934, 0.210788, 0.256182, 0.378836, 0.624145",\ + "0.444935, 0.444935, 0.478349, 0.591825, 0.818777",\ + "1.101088, 1.102468, 1.122488, 1.190477, 1.326455",\ + "0.071183, 0.107097, 0.175661, 0.296416, 0.538687",\ + "0.120882, 0.145118, 0.213463, 0.350090, 0.624205",\ + "0.200934, 0.210850, 0.256566, 0.378836, 0.624145",\ + "0.444935, 0.444935, 0.478705, 0.591825, 0.818777",\ + "1.101088, 1.102468, 1.122701, 1.190477, 1.326455",\ + "0.071251, 0.107578, 0.175668, 0.296416, 0.538687",\ + "0.120905, 0.145525, 0.213471, 0.350090, 0.624205",\ + "0.200952, 0.210986, 0.256574, 0.378836, 0.624145",\ + "0.444935, 0.444935, 0.478711, 0.591825, 0.818777",\ + "1.101096, 1.102468, 1.122705, 1.190477, 1.326455",\ + "0.071390, 0.108275, 0.175689, 0.296416, 0.538687",\ + "0.120951, 0.146116, 0.213494, 0.350090, 0.624205",\ + "0.200988, 0.211184, 0.256595, 0.378836, 0.624145",\ + "0.444935, 0.444935, 0.478731, 0.591825, 0.818777",\ + "1.101112, 1.102468, 1.122717, 1.190477, 1.326455",\ + "0.072681, 0.116463, 0.176917, 0.296915, 0.538687",\ + "0.121377, 0.153056, 0.214884, 0.350655, 0.624205",\ + "0.202910, 0.213504, 0.257838, 0.379341, 0.624145",\ + "0.444935, 0.444935, 0.479881, 0.592292, 0.818777",\ + "1.101261, 1.102468, 1.123406, 1.190757, 1.326455"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2293*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.606811, 0.855240, 1.131420, 1.600406, 2.538379",\ + "0.653020, 0.901448, 1.177629, 1.646621, 2.584605",\ + "0.737270, 0.985698, 1.261878, 1.730864, 2.668837",\ + "0.958264, 1.206694, 1.482871, 1.951840, 2.889778",\ + "1.518707, 1.767142, 2.043312, 2.512236, 3.450085",\ + "0.694214, 0.942805, 1.218983, 1.687119, 2.624312",\ + "0.740423, 0.989013, 1.265193, 1.733334, 2.670539",\ + "0.824672, 1.073263, 1.349441, 1.817578, 2.754771",\ + "1.045666, 1.294259, 1.570434, 2.038553, 2.975712",\ + "1.606110, 1.854707, 2.130875, 2.598950, 3.536019",\ + "0.775027, 1.031783, 1.306946, 1.774740, 2.711267",\ + "0.821236, 1.077992, 1.353155, 1.820955, 2.757494",\ + "0.905485, 1.162242, 1.437404, 1.905199, 2.841726",\ + "1.126479, 1.383237, 1.658397, 2.126174, 3.062667",\ + "1.686923, 1.943686, 2.218838, 2.686570, 3.622974",\ + "0.832667, 1.097413, 1.371085, 1.838653, 2.774776",\ + "0.878876, 1.143622, 1.417294, 1.884868, 2.821003",\ + "0.963125, 1.227872, 1.501543, 1.969111, 2.905235",\ + "1.184119, 1.448868, 1.722536, 2.190087, 3.126176",\ + "1.744563, 2.009316, 2.282977, 2.750483, 3.686483",\ + "1.167769, 1.461851, 1.722948, 2.187993, 3.120233",\ + "1.213978, 1.508059, 1.769157, 2.234208, 3.166459",\ + "1.298227, 1.592309, 1.853406, 2.318451, 3.250691",\ + "1.519221, 1.813305, 2.074399, 2.539426, 3.471632",\ + "2.079665, 2.373755, 2.634840, 3.099823, 4.031939"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.052753, 0.052753, 0.052776, 0.052854, 0.053011",\ + "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\ + "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\ + "0.052753, 0.052753, 0.052777, 0.052854, 0.053011",\ + "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\ + "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\ + "0.052753, 0.052753, 0.052777, 0.052854, 0.053011",\ + "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\ + "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\ + "0.052753, 0.052753, 0.052777, 0.052854, 0.053011",\ + "0.178350, 0.178350, 0.178389, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381655, 0.381716, 0.381838",\ + "0.885927, 0.885931, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162430, 2.162547, 2.162780",\ + "0.052753, 0.052753, 0.052777, 0.052855, 0.053011",\ + "0.178350, 0.178350, 0.178390, 0.178521, 0.178785",\ + "0.381637, 0.381637, 0.381656, 0.381716, 0.381838",\ + "0.885927, 0.885932, 0.885936, 0.885936, 0.885936",\ + "2.162395, 2.162395, 2.162431, 2.162547, 2.162780"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.555254, 0.803664, 1.079873, 1.549041, 2.487376",\ + "0.598546, 0.846975, 1.123154, 1.592132, 2.530087",\ + "0.654342, 0.902772, 1.178949, 1.647912, 2.585838",\ + "0.789973, 1.038401, 1.314582, 1.783569, 2.721544",\ + "1.139274, 1.387700, 1.663883, 2.132891, 3.070906",\ + "0.642657, 0.891229, 1.167437, 1.635754, 2.573310",\ + "0.685949, 0.934540, 1.210717, 1.678845, 2.616020",\ + "0.741745, 0.990338, 1.266512, 1.734625, 2.671772",\ + "0.877376, 1.125967, 1.402145, 1.870283, 2.807478",\ + "1.226676, 1.475265, 1.751447, 2.219604, 3.156840",\ + "0.723469, 0.980207, 1.255399, 1.723375, 2.660265",\ + "0.766762, 1.023519, 1.298680, 1.766466, 2.702976",\ + "0.822557, 1.079316, 1.354475, 1.822246, 2.758727",\ + "0.958189, 1.214945, 1.490107, 1.957903, 2.894433",\ + "1.307489, 1.564244, 1.839409, 2.307225, 3.243795",\ + "0.781109, 1.045837, 1.319539, 1.787287, 2.723774",\ + "0.824402, 1.089149, 1.362819, 1.830378, 2.766484",\ + "0.880198, 1.144946, 1.418614, 1.886158, 2.822236",\ + "1.015829, 1.280575, 1.554247, 2.021816, 2.957942",\ + "1.365129, 1.629874, 1.903549, 2.371138, 3.307304",\ + "1.116211, 1.410268, 1.671404, 2.136628, 3.069230",\ + "1.159504, 1.453587, 1.714682, 2.179718, 3.111940",\ + "1.215299, 1.509384, 1.770477, 2.235498, 3.167692",\ + "1.350931, 1.645012, 1.906110, 2.371156, 3.303398",\ + "1.700231, 1.994310, 2.255412, 2.720478, 3.652760"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095965, 0.095693, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\ + "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095964, 0.095693, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\ + "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095964, 0.095693, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\ + "0.046307, 0.046307, 0.046284, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095964, 0.095693, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606",\ + "0.046307, 0.046307, 0.046283, 0.046204, 0.046045",\ + "0.096045, 0.096045, 0.095961, 0.095692, 0.095150",\ + "0.188958, 0.188958, 0.188958, 0.188958, 0.188958",\ + "0.444028, 0.444028, 0.444025, 0.444014, 0.443994",\ + "1.101656, 1.101656, 1.101651, 1.101636, 1.101606"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2451*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.574242, 0.825673, 1.106128, 1.575345, 2.513779",\ + "0.621341, 0.872791, 1.153329, 1.622748, 2.561586",\ + "0.708610, 0.960115, 1.240890, 1.710886, 2.650879",\ + "0.934451, 1.186041, 1.467182, 1.938070, 2.879846",\ + "1.501685, 1.753387, 2.035005, 2.507055, 3.451155",\ + "0.661652, 0.913251, 1.193695, 1.662059, 2.599712",\ + "0.708750, 0.960370, 1.240897, 1.709462, 2.647520",\ + "0.796019, 1.047694, 1.328459, 1.797601, 2.736813",\ + "1.021860, 1.273621, 1.554754, 2.024784, 2.965779",\ + "1.589094, 1.840967, 2.122581, 2.593769, 3.537089",\ + "0.742484, 1.002291, 1.281659, 1.749681, 2.686667",\ + "0.789583, 1.049409, 1.328861, 1.797084, 2.734475",\ + "0.876852, 1.136734, 1.416423, 1.885223, 2.823768",\ + "1.102693, 1.362663, 1.642718, 2.112406, 3.052734",\ + "1.669927, 1.930012, 2.210544, 2.681391, 3.624044",\ + "0.800100, 1.068010, 1.345799, 1.813594, 2.750176",\ + "0.847199, 1.115129, 1.393000, 1.860997, 2.797984",\ + "0.934467, 1.202456, 1.480563, 1.949136, 2.887277",\ + "1.160309, 1.428387, 1.706858, 2.176319, 3.116243",\ + "1.727543, 1.995738, 2.274684, 2.745304, 3.687553",\ + "1.129877, 1.433405, 1.697668, 2.162941, 3.095633",\ + "1.176977, 1.480531, 1.744871, 2.210345, 3.143440",\ + "1.264251, 1.567875, 1.832440, 2.298486, 3.232733",\ + "1.490099, 1.793832, 2.058744, 2.525673, 3.461699",\ + "2.057343, 2.361218, 2.626582, 3.094663, 4.033009"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.053866, 0.053921, 0.054375, 0.055698, 0.058344",\ + "0.173264, 0.173226, 0.173060, 0.172656, 0.171847",\ + "0.375455, 0.375364, 0.374978, 0.374041, 0.372167",\ + "0.885489, 0.885476, 0.885382, 0.885110, 0.884566",\ + "2.163040, 2.163059, 2.163198, 2.163598, 2.164399",\ + "0.053866, 0.053922, 0.054379, 0.055698, 0.058344",\ + "0.173264, 0.173226, 0.173059, 0.172656, 0.171847",\ + "0.375455, 0.375363, 0.374975, 0.374041, 0.372167",\ + "0.885489, 0.885476, 0.885381, 0.885110, 0.884566",\ + "2.163040, 2.163059, 2.163199, 2.163598, 2.164399",\ + "0.053866, 0.053923, 0.054379, 0.055698, 0.058344",\ + "0.173264, 0.173225, 0.173059, 0.172656, 0.171847",\ + "0.375455, 0.375361, 0.374975, 0.374041, 0.372167",\ + "0.885489, 0.885476, 0.885381, 0.885110, 0.884566",\ + "2.163040, 2.163059, 2.163199, 2.163598, 2.164399",\ + "0.053866, 0.053924, 0.054379, 0.055698, 0.058344",\ + "0.173264, 0.173224, 0.173059, 0.172656, 0.171847",\ + "0.375454, 0.375359, 0.374975, 0.374041, 0.372167",\ + "0.885489, 0.885476, 0.885381, 0.885110, 0.884566",\ + "2.163040, 2.163060, 2.163199, 2.163598, 2.164399",\ + "0.053870, 0.053942, 0.054392, 0.055703, 0.058344",\ + "0.173261, 0.173212, 0.173054, 0.172654, 0.171847",\ + "0.375447, 0.375331, 0.374965, 0.374037, 0.372167",\ + "0.885488, 0.885472, 0.885378, 0.885109, 0.884566",\ + "2.163042, 2.163065, 2.163203, 2.163600, 2.164399"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.504662, 0.755823, 1.035123, 1.501524, 2.434327",\ + "0.565599, 0.817019, 1.097428, 1.566532, 2.504740",\ + "0.632345, 0.883968, 1.165247, 1.636471, 2.578919",\ + "0.766552, 1.018158, 1.299363, 1.770409, 2.712501",\ + "1.110008, 1.361510, 1.642273, 2.112240, 3.052173",\ + "0.592071, 0.843399, 1.122681, 1.588239, 2.520261",\ + "0.653008, 0.904597, 1.184994, 1.653246, 2.590674",\ + "0.719755, 0.971548, 1.252820, 1.723185, 2.664853",\ + "0.853962, 1.105738, 1.386936, 1.857124, 2.798434",\ + "1.197417, 1.449089, 1.729842, 2.198954, 3.138107",\ + "0.672903, 0.932434, 1.210645, 1.675861, 2.607216",\ + "0.733841, 0.993636, 1.272958, 1.740868, 2.677629",\ + "0.800588, 1.060591, 1.340784, 1.810807, 2.751808",\ + "0.934794, 1.194780, 1.474900, 1.944745, 2.885390",\ + "1.278250, 1.538130, 1.817806, 2.286576, 3.225062",\ + "0.730518, 0.998146, 1.274784, 1.739774, 2.670725",\ + "0.791456, 1.059355, 1.337098, 1.804781, 2.741138",\ + "0.858203, 1.126316, 1.404924, 1.874720, 2.815317",\ + "0.992410, 1.260504, 1.539040, 2.008659, 2.948899",\ + "1.335865, 1.603851, 1.881946, 2.350489, 3.288571",\ + "1.060274, 1.363457, 1.626624, 2.089109, 3.016181",\ + "1.121233, 1.424747, 1.688966, 2.154127, 3.086594",\ + "1.187996, 1.491771, 1.756814, 2.224075, 3.160773",\ + "1.322202, 1.625954, 1.890928, 2.358013, 3.294354",\ + "1.665648, 1.969269, 2.233823, 2.699839, 3.634027"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.071595, 0.071985, 0.073663, 0.077752, 0.085929",\ + "0.129674, 0.130204, 0.132478, 0.138021, 0.149107",\ + "0.214013, 0.214497, 0.216573, 0.221634, 0.231755",\ + "0.447089, 0.447144, 0.447376, 0.447942, 0.449074",\ + "1.100695, 1.100670, 1.100562, 1.100300, 1.099777",\ + "0.071595, 0.071989, 0.073676, 0.077752, 0.085929",\ + "0.129674, 0.130208, 0.132495, 0.138021, 0.149107",\ + "0.214013, 0.214501, 0.216589, 0.221634, 0.231755",\ + "0.447089, 0.447144, 0.447378, 0.447942, 0.449074",\ + "1.100695, 1.100670, 1.100561, 1.100300, 1.099777",\ + "0.071595, 0.071996, 0.073676, 0.077752, 0.085929",\ + "0.129674, 0.130218, 0.132496, 0.138021, 0.149107",\ + "0.214014, 0.214510, 0.216590, 0.221634, 0.231755",\ + "0.447089, 0.447145, 0.447378, 0.447942, 0.449074",\ + "1.100695, 1.100669, 1.100561, 1.100300, 1.099777",\ + "0.071596, 0.072006, 0.073677, 0.077752, 0.085929",\ + "0.129675, 0.130232, 0.132497, 0.138021, 0.149107",\ + "0.214014, 0.214523, 0.216591, 0.221634, 0.231755",\ + "0.447090, 0.447146, 0.447378, 0.447942, 0.449074",\ + "1.100695, 1.100668, 1.100561, 1.100300, 1.099777",\ + "0.071627, 0.072128, 0.073719, 0.077769, 0.085929",\ + "0.129718, 0.130397, 0.132553, 0.138044, 0.149107",\ + "0.214054, 0.214674, 0.216642, 0.221655, 0.231755",\ + "0.447094, 0.447163, 0.447384, 0.447944, 0.449074",\ + "1.100693, 1.100661, 1.100559, 1.100299, 1.099777"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2541*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.244315, 0.514723, 0.800077, 1.287472, 2.262263",\ + "0.295834, 0.565221, 0.850051, 1.338109, 2.314226",\ + "0.370354, 0.642449, 0.926203, 1.412852, 2.386149",\ + "0.577074, 0.851060, 1.132979, 1.615988, 2.582005",\ + "1.130301, 1.404191, 1.684823, 2.164586, 3.124112",\ + "0.331716, 0.602319, 0.887697, 1.374185, 2.348197",\ + "0.383234, 0.652812, 0.937673, 1.424822, 2.400160",\ + "0.457755, 0.730036, 1.013820, 1.499564, 2.472083",\ + "0.665475, 0.938641, 1.220586, 1.702701, 2.667939",\ + "1.218705, 1.491770, 1.772419, 2.251299, 3.210045",\ + "0.417649, 0.691352, 0.975660, 1.461806, 2.435152",\ + "0.468650, 0.741835, 1.025635, 1.512442, 2.487115",\ + "0.546403, 0.819049, 1.101783, 1.587185, 2.559038",\ + "0.755504, 1.027643, 1.308548, 1.790321, 2.754894",\ + "1.308745, 1.580767, 1.860382, 2.338919, 3.297000",\ + "0.482221, 0.757061, 1.039803, 1.525718, 2.498661",\ + "0.533223, 0.807529, 1.089778, 1.576355, 2.550624",\ + "0.610973, 0.884729, 1.165926, 1.651097, 2.622547",\ + "0.820080, 1.093307, 1.372690, 1.854234, 2.818403",\ + "1.373332, 1.646424, 1.924523, 2.402832, 3.360509",\ + "0.824496, 1.122462, 1.391851, 1.875132, 2.844117",\ + "0.875514, 1.172748, 1.441833, 1.925771, 2.896080",\ + "0.953244, 1.249783, 1.517967, 2.000508, 2.968003",\ + "1.162385, 1.458171, 1.724694, 2.203629, 3.163859",\ + "1.715704, 2.011206, 2.276494, 2.752214, 3.705966"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.247846, 0.303832, 0.405143, 0.595020, 0.974773",\ + "0.313786, 0.346638, 0.435686, 0.627210, 1.010259",\ + "0.435716, 0.458756, 0.530637, 0.704592, 1.052501",\ + "0.888071, 0.889365, 0.918106, 1.015199, 1.209385",\ + "2.165255, 2.165436, 2.171895, 2.192891, 2.234884",\ + "0.247846, 0.304139, 0.405737, 0.595020, 0.974773",\ + "0.313786, 0.346858, 0.436285, 0.627210, 1.010259",\ + "0.435716, 0.458895, 0.531182, 0.704592, 1.052501",\ + "0.888102, 0.889365, 0.918410, 1.015199, 1.209385",\ + "2.165255, 2.165437, 2.171961, 2.192891, 2.234884",\ + "0.250082, 0.304803, 0.405749, 0.595020, 0.974773",\ + "0.314671, 0.347334, 0.436296, 0.627210, 1.010259",\ + "0.436504, 0.459195, 0.531192, 0.704592, 1.052501",\ + "0.888199, 0.889365, 0.918416, 1.015199, 1.209385",\ + "2.165255, 2.165441, 2.171962, 2.192891, 2.234884",\ + "0.251727, 0.305767, 0.405781, 0.595020, 0.974773",\ + "0.315322, 0.348025, 0.436329, 0.627210, 1.010259",\ + "0.437083, 0.459631, 0.531222, 0.704592, 1.052501",\ + "0.888292, 0.889365, 0.918433, 1.015199, 1.209385",\ + "2.165255, 2.165446, 2.171966, 2.192891, 2.234884",\ + "0.262263, 0.317092, 0.407706, 0.595800, 0.974773",\ + "0.319491, 0.356149, 0.438270, 0.627998, 1.010259",\ + "0.440795, 0.464750, 0.532985, 0.705307, 1.052501",\ + "0.888892, 0.889365, 0.919417, 1.015598, 1.209385",\ + "2.165255, 2.165507, 2.172179, 2.192978, 2.234884"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.244906, 0.429066, 0.715031, 1.201577, 2.174669",\ + "0.279961, 0.467088, 0.760757, 1.264102, 2.270793",\ + "0.330500, 0.520871, 0.819993, 1.340074, 2.380235",\ + "0.460001, 0.650607, 0.955135, 1.497108, 2.581054",\ + "0.797840, 0.992388, 1.299994, 1.860913, 2.982751",\ + "0.332306, 0.516668, 0.802648, 1.288290, 2.260602",\ + "0.367361, 0.554708, 0.848427, 1.350815, 2.356727",\ + "0.417900, 0.608494, 0.907716, 1.426787, 2.466169",\ + "0.547401, 0.738223, 1.042926, 1.583821, 2.666988",\ + "0.885240, 1.079987, 1.387844, 1.947626, 3.068685",\ + "0.413157, 0.605714, 0.890611, 1.375910, 2.347558",\ + "0.448212, 0.643794, 0.936391, 1.438436, 2.443682",\ + "0.498750, 0.697588, 0.995681, 1.514407, 2.553124",\ + "0.628251, 0.827301, 1.130892, 1.671441, 2.753943",\ + "0.966089, 1.169027, 1.475811, 2.035246, 3.155640",\ + "0.470897, 0.671442, 0.954754, 1.439822, 2.411067",\ + "0.505953, 0.709581, 1.000537, 1.502348, 2.507191",\ + "0.556489, 0.763385, 1.059829, 1.578320, 2.616633",\ + "0.685989, 0.893075, 1.195044, 1.735354, 2.817452",\ + "1.023827, 1.234747, 1.539967, 2.099159, 3.219149",\ + "0.774671, 1.037059, 1.306793, 1.789232, 2.756522",\ + "0.809728, 1.075884, 1.352747, 1.851827, 2.852647",\ + "0.860246, 1.129813, 1.412209, 1.927867, 2.962089",\ + "0.989742, 1.259233, 1.547645, 2.084991, 3.162908",\ + "1.327573, 1.600271, 1.892761, 2.448874, 3.564605"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.078481, 0.114548, 0.190287, 0.342583, 0.647174",\ + "0.121015, 0.135349, 0.195602, 0.346123, 0.647167",\ + "0.210717, 0.216175, 0.259364, 0.388602, 0.647078",\ + "0.448759, 0.449668, 0.471637, 0.541681, 0.681771",\ + "1.102116, 1.102394, 1.113655, 1.151696, 1.227780",\ + "0.078481, 0.114757, 0.190764, 0.342583, 0.647174",\ + "0.121015, 0.135456, 0.196073, 0.346123, 0.647167",\ + "0.210717, 0.216208, 0.259768, 0.388602, 0.647078",\ + "0.448759, 0.449677, 0.471856, 0.541681, 0.681771",\ + "1.102116, 1.102394, 1.113774, 1.151696, 1.227780",\ + "0.078556, 0.115208, 0.190773, 0.342583, 0.647174",\ + "0.121030, 0.135687, 0.196082, 0.346123, 0.647167",\ + "0.210727, 0.216281, 0.259776, 0.388602, 0.647078",\ + "0.448759, 0.449695, 0.471860, 0.541681, 0.681771",\ + "1.102118, 1.102394, 1.113776, 1.151696, 1.227780",\ + "0.078710, 0.115863, 0.190799, 0.342583, 0.647174",\ + "0.121062, 0.136023, 0.196108, 0.346123, 0.647167",\ + "0.210748, 0.216386, 0.259798, 0.388602, 0.647078",\ + "0.448759, 0.449721, 0.471872, 0.541681, 0.681771",\ + "1.102121, 1.102394, 1.113783, 1.151696, 1.227780",\ + "0.080154, 0.123560, 0.192343, 0.343209, 0.647174",\ + "0.121358, 0.139963, 0.197633, 0.346742, 0.647167",\ + "0.210943, 0.217625, 0.261108, 0.389133, 0.647078",\ + "0.448759, 0.450031, 0.472582, 0.541969, 0.681771",\ + "1.102151, 1.102394, 1.114168, 1.151853, 1.227780"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2586*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.802622, 1.056036, 1.346324, 1.867286, 2.909209",\ + "0.849165, 1.102582, 1.392879, 1.913861, 2.955825",\ + "0.934845, 1.188269, 1.478593, 1.999634, 3.041714",\ + "1.158235, 1.411669, 1.702036, 2.223166, 3.265427",\ + "1.722272, 1.975720, 2.266142, 2.787390, 3.829885",\ + "0.890034, 1.143575, 1.434056, 1.954001, 2.995142",\ + "0.936578, 1.190121, 1.480612, 2.000576, 3.041759",\ + "1.022258, 1.275808, 1.566326, 2.086349, 3.127648",\ + "1.245647, 1.499208, 1.789768, 2.309881, 3.351360",\ + "1.809685, 2.063260, 2.353875, 2.874104, 3.915819",\ + "0.970907, 1.232542, 1.522024, 2.041623, 3.082098",\ + "1.017450, 1.279087, 1.568579, 2.088199, 3.128714",\ + "1.103130, 1.364774, 1.654293, 2.173971, 3.214603",\ + "1.326520, 1.588175, 1.877736, 2.397503, 3.438315",\ + "1.890557, 2.152227, 2.441842, 2.961727, 4.002774",\ + "1.029596, 1.298156, 1.586172, 2.105536, 3.145607",\ + "1.076139, 1.344701, 1.632727, 2.152112, 3.192223",\ + "1.161819, 1.430389, 1.718441, 2.237885, 3.278112",\ + "1.385208, 1.653790, 1.941884, 2.461417, 3.501824",\ + "1.949246, 2.217842, 2.505991, 3.025640, 4.066283",\ + "1.361666, 1.662270, 1.938568, 2.455101, 3.491063",\ + "1.408209, 1.708817, 1.985123, 2.501677, 3.537679",\ + "1.493889, 1.794507, 2.070838, 2.587449, 3.623568",\ + "1.717279, 2.017912, 2.294282, 2.810982, 3.847281",\ + "2.281316, 2.581969, 2.858389, 3.375206, 4.411739"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.052266, 0.052273, 0.052301, 0.052359, 0.052477",\ + "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\ + "0.378069, 0.378057, 0.378013, 0.377917, 0.377724",\ + "0.885437, 0.885434, 0.885402, 0.885305, 0.885113",\ + "2.163117, 2.163121, 2.163168, 2.163310, 2.163594",\ + "0.052266, 0.052273, 0.052301, 0.052359, 0.052477",\ + "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\ + "0.378069, 0.378057, 0.378012, 0.377917, 0.377724",\ + "0.885437, 0.885434, 0.885401, 0.885305, 0.885113",\ + "2.163117, 2.163121, 2.163169, 2.163310, 2.163594",\ + "0.052266, 0.052274, 0.052301, 0.052359, 0.052477",\ + "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\ + "0.378069, 0.378057, 0.378012, 0.377917, 0.377724",\ + "0.885437, 0.885434, 0.885401, 0.885305, 0.885113",\ + "2.163117, 2.163121, 2.163169, 2.163310, 2.163594",\ + "0.052266, 0.052274, 0.052301, 0.052359, 0.052477",\ + "0.174376, 0.174371, 0.174352, 0.174312, 0.174230",\ + "0.378069, 0.378057, 0.378012, 0.377917, 0.377724",\ + "0.885437, 0.885434, 0.885401, 0.885305, 0.885113",\ + "2.163117, 2.163121, 2.163169, 2.163310, 2.163594",\ + "0.052266, 0.052276, 0.052301, 0.052360, 0.052477",\ + "0.174376, 0.174369, 0.174352, 0.174311, 0.174230",\ + "0.378069, 0.378052, 0.378011, 0.377916, 0.377724",\ + "0.885437, 0.885432, 0.885400, 0.885305, 0.885113",\ + "2.163117, 2.163123, 2.163170, 2.163311, 2.163594"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.740784, 0.994165, 1.284321, 1.804998, 2.846352",\ + "0.794288, 1.047701, 1.337984, 1.858934, 2.900834",\ + "0.855205, 1.108643, 1.399026, 1.920190, 2.962518",\ + "0.989902, 1.243338, 1.533712, 2.054859, 3.097151",\ + "1.336325, 1.589748, 1.880072, 2.401109, 3.443183",\ + "0.828197, 1.081704, 1.372052, 1.891713, 2.932285",\ + "0.881701, 1.135240, 1.425716, 1.945649, 2.986768",\ + "0.942617, 1.196183, 1.486758, 2.006905, 3.048452",\ + "1.077314, 1.330878, 1.621445, 2.141573, 3.183085",\ + "1.423737, 1.677287, 1.967804, 2.487824, 3.529117",\ + "0.909070, 1.170669, 1.460019, 1.979335, 3.019240",\ + "0.962574, 1.224207, 1.513683, 2.033271, 3.073723",\ + "1.023490, 1.285149, 1.574726, 2.094527, 3.135407",\ + "1.158187, 1.419844, 1.709412, 2.229196, 3.270040",\ + "1.504610, 1.766254, 2.055771, 2.575446, 3.616072",\ + "0.967758, 1.236282, 1.524167, 2.043248, 3.082749",\ + "1.021262, 1.289820, 1.577832, 2.097185, 3.137232",\ + "1.082179, 1.350764, 1.638874, 2.158441, 3.198916",\ + "1.216876, 1.485459, 1.773561, 2.293109, 3.333549",\ + "1.563299, 1.831868, 2.119919, 2.639359, 3.679581",\ + "1.299828, 1.600384, 1.876561, 2.392812, 3.428205",\ + "1.353332, 1.653935, 1.930228, 2.446749, 3.482688",\ + "1.414249, 1.714888, 1.991272, 2.508006, 3.544372",\ + "1.548946, 1.849582, 2.125958, 2.642674, 3.679005",\ + "1.895369, 2.195986, 2.472316, 2.988924, 4.025037"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.060356, 0.060405, 0.060595, 0.061007, 0.061830",\ + "0.114429, 0.114496, 0.114756, 0.115316, 0.116436",\ + "0.200095, 0.200156, 0.200394, 0.200905, 0.201928",\ + "0.445532, 0.445539, 0.445566, 0.445623, 0.445737",\ + "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\ + "0.060356, 0.060405, 0.060597, 0.061007, 0.061830",\ + "0.114429, 0.114496, 0.114758, 0.115316, 0.116436",\ + "0.200095, 0.200157, 0.200396, 0.200905, 0.201928",\ + "0.445532, 0.445539, 0.445566, 0.445623, 0.445737",\ + "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\ + "0.060356, 0.060406, 0.060597, 0.061007, 0.061830",\ + "0.114429, 0.114498, 0.114758, 0.115316, 0.116436",\ + "0.200095, 0.200158, 0.200396, 0.200905, 0.201928",\ + "0.445532, 0.445539, 0.445566, 0.445623, 0.445737",\ + "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\ + "0.060356, 0.060408, 0.060597, 0.061007, 0.061830",\ + "0.114429, 0.114500, 0.114758, 0.115316, 0.116436",\ + "0.200095, 0.200160, 0.200396, 0.200905, 0.201928",\ + "0.445532, 0.445540, 0.445566, 0.445623, 0.445737",\ + "1.101415, 1.101412, 1.101400, 1.101373, 1.101320",\ + "0.060356, 0.060425, 0.060601, 0.061009, 0.061830",\ + "0.114429, 0.114524, 0.114764, 0.115319, 0.116436",\ + "0.200095, 0.200182, 0.200401, 0.200907, 0.201928",\ + "0.445532, 0.445542, 0.445567, 0.445623, 0.445737",\ + "1.101415, 1.101411, 1.101399, 1.101373, 1.101320"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2628*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.793277, 1.039130, 1.319023, 1.798101, 2.756257",\ + "0.839819, 1.085675, 1.365575, 1.844669, 2.802857",\ + "0.925498, 1.171358, 1.451280, 1.930420, 2.888700",\ + "1.148884, 1.394753, 1.674707, 2.153918, 3.112340",\ + "1.712918, 1.958797, 2.238793, 2.718097, 3.676705",\ + "0.880682, 1.126695, 1.406620, 1.884815, 2.842191",\ + "0.927225, 1.173240, 1.453171, 1.931383, 2.888791",\ + "1.012903, 1.258923, 1.538876, 2.017133, 2.974633",\ + "1.236289, 1.482318, 1.762303, 2.240632, 3.198274",\ + "1.800323, 2.046363, 2.326390, 2.804811, 3.762639",\ + "0.961504, 1.215685, 1.494583, 1.972436, 2.929146",\ + "1.008047, 1.262229, 1.541135, 2.019004, 2.975746",\ + "1.093725, 1.347913, 1.626839, 2.104754, 3.061589",\ + "1.317111, 1.571308, 1.850267, 2.328253, 3.285229",\ + "1.881145, 2.135353, 2.414354, 2.892432, 3.849594",\ + "1.019140, 1.281331, 1.558724, 2.036349, 2.992655",\ + "1.065682, 1.327876, 1.605276, 2.082916, 3.039255",\ + "1.151360, 1.413560, 1.690981, 2.168667, 3.125098",\ + "1.374747, 1.636955, 1.914408, 2.392166, 3.348738",\ + "1.938781, 2.201000, 2.478495, 2.956345, 3.913103",\ + "1.348815, 1.645927, 1.910691, 2.385732, 3.338111",\ + "1.395358, 1.692472, 1.957243, 2.432300, 3.384711",\ + "1.481036, 1.778158, 2.042948, 2.518051, 3.470554",\ + "1.704422, 2.001556, 2.266376, 2.741550, 3.694194",\ + "2.268456, 2.565605, 2.830464, 3.305729, 4.258559"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\ + "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378063, 0.378028, 0.377953, 0.377801",\ + "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\ + "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\ + "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\ + "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378063, 0.378028, 0.377953, 0.377801",\ + "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\ + "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\ + "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\ + "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378063, 0.378028, 0.377953, 0.377801",\ + "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\ + "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\ + "0.052265, 0.052270, 0.052291, 0.052337, 0.052430",\ + "0.174378, 0.174374, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378062, 0.378028, 0.377953, 0.377801",\ + "0.885436, 0.885432, 0.885397, 0.885300, 0.885105",\ + "2.163117, 2.163124, 2.163175, 2.163318, 2.163605",\ + "0.052265, 0.052272, 0.052292, 0.052338, 0.052430",\ + "0.174378, 0.174372, 0.174359, 0.174327, 0.174262",\ + "0.378072, 0.378059, 0.378027, 0.377952, 0.377801",\ + "0.885436, 0.885430, 0.885396, 0.885299, 0.885105",\ + "2.163117, 2.163126, 2.163177, 2.163319, 2.163605"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.731449, 0.977276, 1.257067, 1.735920, 2.693626",\ + "0.784944, 1.030796, 1.310685, 1.789754, 2.747891",\ + "0.845853, 1.091725, 1.371691, 1.850929, 2.809405",\ + "0.980551, 1.226421, 1.506381, 1.985605, 2.944052",\ + "1.326977, 1.572838, 1.852758, 2.331896, 3.290171",\ + "0.818854, 1.064841, 1.344662, 1.822633, 2.779559",\ + "0.872349, 1.118361, 1.398281, 1.876467, 2.833825",\ + "0.933258, 1.179290, 1.459288, 1.937643, 2.895339",\ + "1.067956, 1.313987, 1.593977, 2.072318, 3.029986",\ + "1.414383, 1.660403, 1.940354, 2.418609, 3.376105",\ + "0.899676, 1.153830, 1.432626, 1.910254, 2.866514",\ + "0.953171, 1.207350, 1.486244, 1.964088, 2.920780",\ + "1.014081, 1.268280, 1.547251, 2.025264, 2.982294",\ + "1.148778, 1.402976, 1.681941, 2.159939, 3.116941",\ + "1.495205, 1.749392, 2.028318, 2.506230, 3.463060",\ + "0.957311, 1.219475, 1.496767, 1.974167, 2.930023",\ + "1.010806, 1.272997, 1.550386, 2.028001, 2.984289",\ + "1.071716, 1.333927, 1.611393, 2.089177, 3.045803",\ + "1.206414, 1.468623, 1.746082, 2.223852, 3.180450",\ + "1.552840, 1.815039, 2.092459, 2.570143, 3.526569",\ + "1.286987, 1.584062, 1.848731, 2.323550, 3.275480",\ + "1.340482, 1.637592, 1.902352, 2.377385, 3.329745",\ + "1.401392, 1.698529, 1.963361, 2.438561, 3.391259",\ + "1.536089, 1.833225, 2.098050, 2.573236, 3.525906",\ + "1.882516, 2.179637, 2.444427, 2.919527, 3.872025"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.060343, 0.060380, 0.060528, 0.060852, 0.061502",\ + "0.114411, 0.114462, 0.114664, 0.115106, 0.115991",\ + "0.200079, 0.200126, 0.200310, 0.200714, 0.201522",\ + "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\ + "1.101416, 1.101414, 1.101404, 1.101383, 1.101341",\ + "0.060343, 0.060381, 0.060529, 0.060852, 0.061502",\ + "0.114411, 0.114463, 0.114665, 0.115106, 0.115991",\ + "0.200079, 0.200126, 0.200311, 0.200714, 0.201522",\ + "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\ + "1.101416, 1.101414, 1.101404, 1.101383, 1.101341",\ + "0.060343, 0.060382, 0.060529, 0.060852, 0.061502",\ + "0.114411, 0.114464, 0.114665, 0.115106, 0.115991",\ + "0.200079, 0.200127, 0.200311, 0.200714, 0.201522",\ + "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\ + "1.101416, 1.101413, 1.101404, 1.101383, 1.101341",\ + "0.060343, 0.060383, 0.060529, 0.060852, 0.061502",\ + "0.114411, 0.114465, 0.114665, 0.115106, 0.115991",\ + "0.200079, 0.200128, 0.200311, 0.200714, 0.201522",\ + "0.445531, 0.445536, 0.445556, 0.445602, 0.445692",\ + "1.101416, 1.101413, 1.101404, 1.101383, 1.101341",\ + "0.060343, 0.060396, 0.060532, 0.060854, 0.061502",\ + "0.114411, 0.114483, 0.114670, 0.115108, 0.115991",\ + "0.200079, 0.200145, 0.200315, 0.200715, 0.201522",\ + "0.445531, 0.445538, 0.445557, 0.445602, 0.445692",\ + "1.101416, 1.101413, 1.101404, 1.101383, 1.101341"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2679*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.704078, 0.962448, 1.254543, 1.772415, 2.808159",\ + "0.750305, 1.008676, 1.300771, 1.818645, 2.854393",\ + "0.834537, 1.092907, 1.385001, 1.902873, 2.938617",\ + "1.055475, 1.313845, 1.605937, 2.123804, 3.159536",\ + "1.615778, 1.874147, 2.166233, 2.684084, 3.719787",\ + "0.791487, 1.050012, 1.342263, 1.859129, 2.894093",\ + "0.837714, 1.096239, 1.388491, 1.905359, 2.940326",\ + "0.921945, 1.180470, 1.472721, 1.989588, 3.024551",\ + "1.142884, 1.401409, 1.693658, 2.210518, 3.245470",\ + "1.703187, 1.961710, 2.253953, 2.770799, 3.805721",\ + "0.872371, 1.139015, 1.430229, 1.946751, 2.981048",\ + "0.918598, 1.185243, 1.476457, 1.992981, 3.027281",\ + "1.002829, 1.269474, 1.560688, 2.077209, 3.111506",\ + "1.223768, 1.490412, 1.781624, 2.298140, 3.332425",\ + "1.784070, 2.050714, 2.341920, 2.858420, 3.892676",\ + "0.932831, 1.204683, 1.494377, 2.010664, 3.044557",\ + "0.979058, 1.250910, 1.540605, 2.056894, 3.090790",\ + "1.063289, 1.335141, 1.624835, 2.141123, 3.175015",\ + "1.284228, 1.556080, 1.845772, 2.362053, 3.395934",\ + "1.844531, 2.116381, 2.406067, 2.922334, 3.956185",\ + "1.268348, 1.569475, 1.846740, 2.360211, 3.390013",\ + "1.314575, 1.615702, 1.892967, 2.406441, 3.436246",\ + "1.398806, 1.699933, 1.977198, 2.490670, 3.520471",\ + "1.619745, 1.920872, 2.198134, 2.711600, 3.741390",\ + "2.180047, 2.481173, 2.758430, 3.271881, 4.301641"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\ + "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\ + "2.162832, 2.162841, 2.162898, 2.163049, 2.163351",\ + "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\ + "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\ + "2.162832, 2.162841, 2.162899, 2.163049, 2.163351",\ + "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\ + "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\ + "2.162832, 2.162841, 2.162899, 2.163049, 2.163351",\ + "0.053020, 0.053022, 0.053032, 0.053060, 0.053117",\ + "0.178801, 0.178804, 0.178822, 0.178869, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885624, 0.885585, 0.885483, 0.885278",\ + "2.162832, 2.162841, 2.162899, 2.163049, 2.163351",\ + "0.053020, 0.053022, 0.053033, 0.053061, 0.053117",\ + "0.178801, 0.178805, 0.178823, 0.178870, 0.178965",\ + "0.381845, 0.381847, 0.381855, 0.381877, 0.381921",\ + "0.885630, 0.885621, 0.885584, 0.885482, 0.885278",\ + "2.162832, 2.162845, 2.162900, 2.163050, 2.163351"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.653096, 0.911470, 1.203587, 1.721520, 2.757385",\ + "0.695785, 0.954155, 1.246248, 1.764117, 2.799856",\ + "0.751534, 1.009904, 1.301996, 1.819860, 2.855588",\ + "0.887244, 1.145615, 1.437709, 1.955581, 2.991326",\ + "1.236608, 1.494979, 1.787076, 2.304955, 3.340714",\ + "0.740505, 0.999033, 1.291307, 1.808234, 2.843319",\ + "0.783194, 1.041719, 1.333969, 1.850832, 2.885789",\ + "0.838943, 1.097468, 1.389716, 1.906574, 2.941522",\ + "0.974653, 1.233178, 1.525429, 2.042296, 3.077260",\ + "1.324017, 1.582542, 1.874796, 2.391670, 3.426647",\ + "0.821388, 1.088037, 1.379274, 1.895856, 2.930274",\ + "0.864078, 1.130722, 1.421935, 1.938454, 2.972744",\ + "0.919827, 1.186471, 1.477682, 1.994196, 3.028477",\ + "1.055537, 1.322181, 1.613395, 2.129917, 3.164215",\ + "1.404901, 1.671546, 1.962763, 2.479291, 3.513602",\ + "0.881849, 1.153705, 1.443422, 1.959769, 2.993783",\ + "0.924538, 1.196390, 1.486083, 2.002367, 3.036253",\ + "0.980287, 1.252139, 1.541830, 2.058109, 3.091986",\ + "1.115997, 1.387849, 1.677543, 2.193830, 3.227724",\ + "1.465361, 1.737213, 2.026911, 2.543204, 3.577111",\ + "1.217365, 1.518498, 1.795785, 2.309317, 3.339239",\ + "1.260055, 1.561182, 1.838445, 2.351914, 3.381710",\ + "1.315804, 1.616930, 1.894192, 2.407657, 3.437442",\ + "1.451514, 1.752641, 2.029906, 2.543378, 3.573180",\ + "1.800878, 2.102005, 2.379273, 2.892752, 3.922567"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\ + "0.095119, 0.095114, 0.095079, 0.094989, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\ + "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\ + "0.095119, 0.095114, 0.095079, 0.094989, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\ + "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\ + "0.095119, 0.095114, 0.095079, 0.094989, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\ + "0.046012, 0.046005, 0.045968, 0.045869, 0.045670",\ + "0.095119, 0.095113, 0.095079, 0.094989, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101604, 1.101601, 1.101596, 1.101585",\ + "0.046012, 0.046003, 0.045967, 0.045868, 0.045670",\ + "0.095119, 0.095111, 0.095078, 0.094988, 0.094807",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188975",\ + "0.443992, 0.443992, 0.443991, 0.443987, 0.443980",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101585"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.687749, 0.939290, 1.220370, 1.693212, 2.638895",\ + "0.733976, 0.985517, 1.266598, 1.739441, 2.685128",\ + "0.818208, 1.069748, 1.350828, 1.823670, 2.769354",\ + "1.039147, 1.290687, 1.571764, 2.044601, 2.990274",\ + "1.599449, 1.850988, 2.132060, 2.604883, 3.550529",\ + "0.775154, 1.026875, 1.307946, 1.779925, 2.724829",\ + "0.821381, 1.073102, 1.354175, 1.826155, 2.771062",\ + "0.905613, 1.157333, 1.438405, 1.910384, 2.855288",\ + "1.126552, 1.378272, 1.659341, 2.131315, 3.076208",\ + "1.686854, 1.938572, 2.219636, 2.691597, 3.636462",\ + "0.855968, 1.115908, 1.395910, 1.867546, 2.811784",\ + "0.902195, 1.162135, 1.442138, 1.913776, 2.858017",\ + "0.986426, 1.246367, 1.526368, 1.998005, 2.942243",\ + "1.207365, 1.467305, 1.747304, 2.218936, 3.163163",\ + "1.767667, 2.027606, 2.307599, 2.779218, 3.723417",\ + "0.913586, 1.181618, 1.460050, 1.931459, 2.875293",\ + "0.959814, 1.227846, 1.506278, 1.977689, 2.921526",\ + "1.044045, 1.312077, 1.590508, 2.061918, 3.005752",\ + "1.264984, 1.533015, 1.811444, 2.282849, 3.226672",\ + "1.825286, 2.093316, 2.371740, 2.843130, 3.786926",\ + "1.247292, 1.546964, 1.811953, 2.280817, 3.220749",\ + "1.293519, 1.593192, 1.858181, 2.327047, 3.266982",\ + "1.377751, 1.677423, 1.942412, 2.411276, 3.351208",\ + "1.598690, 1.898361, 2.163348, 2.632206, 3.572128",\ + "2.158992, 2.458661, 2.723643, 3.192488, 4.132382"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\ + "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\ + "2.162833, 2.162845, 2.162902, 2.163039, 2.163313",\ + "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\ + "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\ + "2.162833, 2.162845, 2.162903, 2.163039, 2.163313",\ + "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\ + "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\ + "2.162833, 2.162846, 2.162903, 2.163039, 2.163313",\ + "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178805, 0.178823, 0.178866, 0.178953",\ + "0.381846, 0.381847, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885621, 0.885582, 0.885489, 0.885303",\ + "2.162833, 2.162846, 2.162903, 2.163039, 2.163313",\ + "0.053020, 0.053023, 0.053033, 0.053059, 0.053110",\ + "0.178802, 0.178807, 0.178824, 0.178867, 0.178953",\ + "0.381846, 0.381848, 0.381856, 0.381876, 0.381916",\ + "0.885629, 0.885618, 0.885581, 0.885489, 0.885303",\ + "2.162833, 2.162850, 2.162904, 2.163039, 2.163313"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.636768, 0.888313, 1.169416, 1.642313, 2.588106",\ + "0.679456, 0.930997, 1.212076, 1.684915, 2.630593",\ + "0.735206, 0.986745, 1.267823, 1.740657, 2.686327",\ + "0.870915, 1.122456, 1.403536, 1.876378, 2.822062",\ + "1.220279, 1.471821, 1.752903, 2.225752, 3.171448",\ + "0.724173, 0.975898, 1.256993, 1.729026, 2.674040",\ + "0.766861, 1.018582, 1.299652, 1.771628, 2.716527",\ + "0.822611, 1.074330, 1.355399, 1.827371, 2.772260",\ + "0.958320, 1.210041, 1.491113, 1.963092, 2.907996",\ + "1.307685, 1.559406, 1.840480, 2.312465, 3.257382",\ + "0.804986, 1.064932, 1.344956, 1.816648, 2.760995",\ + "0.847675, 1.107615, 1.387615, 1.859249, 2.803482",\ + "0.903424, 1.163364, 1.443362, 1.914992, 2.859215",\ + "1.039134, 1.299074, 1.579076, 2.050713, 2.994951",\ + "1.388498, 1.648439, 1.928443, 2.400086, 3.344337",\ + "0.862605, 1.130642, 1.409096, 1.880560, 2.824504",\ + "0.905293, 1.173325, 1.451756, 1.923162, 2.866991",\ + "0.961043, 1.229074, 1.507503, 1.978905, 2.922724",\ + "1.096752, 1.364785, 1.643216, 2.114626, 3.058460",\ + "1.446117, 1.714149, 1.992583, 2.463999, 3.407846",\ + "1.196311, 1.495989, 1.761000, 2.229918, 3.169960",\ + "1.238999, 1.538671, 1.803659, 2.272520, 3.212447",\ + "1.294749, 1.594420, 1.859406, 2.328263, 3.268181",\ + "1.430458, 1.730130, 1.995120, 2.463984, 3.403916",\ + "1.779823, 2.079495, 2.344487, 2.813357, 3.753302"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.046010, 0.046003, 0.045965, 0.045875, 0.045695",\ + "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\ + "0.046010, 0.046002, 0.045965, 0.045875, 0.045695",\ + "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\ + "0.046010, 0.046002, 0.045965, 0.045875, 0.045695",\ + "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\ + "0.188959, 0.188960, 0.188961, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\ + "0.046010, 0.046002, 0.045965, 0.045875, 0.045695",\ + "0.095118, 0.095111, 0.095077, 0.094995, 0.094830",\ + "0.188959, 0.188960, 0.188962, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586",\ + "0.046010, 0.045999, 0.045964, 0.045875, 0.045695",\ + "0.095118, 0.095108, 0.095076, 0.094994, 0.094830",\ + "0.188959, 0.188960, 0.188962, 0.188966, 0.188974",\ + "0.443992, 0.443992, 0.443991, 0.443988, 0.443981",\ + "1.101604, 1.101603, 1.101601, 1.101596, 1.101586"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2370*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.622933, 0.904214, 1.205191, 1.719790, 2.748989",\ + "0.669468, 0.950758, 1.251803, 1.766599, 2.796192",\ + "0.755125, 1.036441, 1.337680, 1.853039, 2.883759",\ + "0.978478, 1.259834, 1.561373, 2.077602, 3.110059",\ + "1.542469, 1.823877, 2.125806, 2.643168, 3.677893",\ + "0.710344, 0.991835, 1.292902, 1.806505, 2.834923",\ + "0.756879, 1.038379, 1.339514, 1.853314, 2.882126",\ + "0.842536, 1.124062, 1.425393, 1.939754, 2.969692",\ + "1.065890, 1.347456, 1.649089, 2.164316, 3.195993",\ + "1.629880, 1.911499, 2.213525, 2.729883, 3.763827",\ + "0.799646, 1.080982, 1.380869, 1.894127, 2.921878",\ + "0.846182, 1.127527, 1.427481, 1.940936, 2.969081",\ + "0.931839, 1.213210, 1.513360, 2.027376, 3.056648",\ + "1.155193, 1.436604, 1.737056, 2.251938, 3.282948",\ + "1.719185, 2.000648, 2.301492, 2.817505, 3.850782",\ + "0.863267, 1.146859, 1.445016, 1.958041, 2.985387",\ + "0.909803, 1.193403, 1.491629, 2.004849, 3.032590",\ + "0.995460, 1.279087, 1.577507, 2.091290, 3.120157",\ + "1.218815, 1.502483, 1.801203, 2.315852, 3.346457",\ + "1.782807, 2.066528, 2.365640, 2.881418, 3.914291",\ + "1.199521, 1.514063, 1.797347, 2.307577, 3.330843",\ + "1.246057, 1.560610, 1.843961, 2.354387, 3.378046",\ + "1.331717, 1.646302, 1.929846, 2.440829, 3.465612",\ + "1.555075, 1.869709, 2.153550, 2.665395, 3.691913",\ + "2.119071, 2.433770, 2.717999, 3.230966, 4.259747"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.052243, 0.052269, 0.054671, 0.062895, 0.079343",\ + "0.174393, 0.174375, 0.174239, 0.173844, 0.173056",\ + "0.378107, 0.378064, 0.377824, 0.377171, 0.375864",\ + "0.885321, 0.885201, 0.884881, 0.884213, 0.882876",\ + "2.163287, 2.163464, 2.163713, 2.163931, 2.164366",\ + "0.052243, 0.052269, 0.054697, 0.062895, 0.079343",\ + "0.174393, 0.174374, 0.174237, 0.173844, 0.173056",\ + "0.378107, 0.378064, 0.377822, 0.377171, 0.375864",\ + "0.885321, 0.885200, 0.884879, 0.884213, 0.882876",\ + "2.163287, 2.163465, 2.163714, 2.163931, 2.164366",\ + "0.052243, 0.052270, 0.054697, 0.062895, 0.079343",\ + "0.174392, 0.174374, 0.174237, 0.173844, 0.173056",\ + "0.378106, 0.378063, 0.377822, 0.377171, 0.375864",\ + "0.885318, 0.885198, 0.884879, 0.884213, 0.882876",\ + "2.163292, 2.163468, 2.163714, 2.163931, 2.164366",\ + "0.052244, 0.052270, 0.054698, 0.062895, 0.079343",\ + "0.174392, 0.174374, 0.174237, 0.173844, 0.173056",\ + "0.378106, 0.378062, 0.377822, 0.377171, 0.375864",\ + "0.885315, 0.885196, 0.884879, 0.884213, 0.882876",\ + "2.163296, 2.163471, 2.163714, 2.163931, 2.164366",\ + "0.052246, 0.052278, 0.054782, 0.062929, 0.079343",\ + "0.174391, 0.174368, 0.174233, 0.173843, 0.173056",\ + "0.378102, 0.378049, 0.377815, 0.377168, 0.375864",\ + "0.885300, 0.885164, 0.884872, 0.884210, 0.882876",\ + "2.163318, 2.163518, 2.163716, 2.163932, 2.164366"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.561209, 0.842364, 1.145718, 1.669104, 2.715876",\ + "0.614604, 0.895880, 1.196912, 1.711724, 2.741347",\ + "0.675435, 0.956806, 1.258457, 1.775014, 2.808127",\ + "0.810139, 1.091502, 1.393093, 1.909477, 2.942242",\ + "1.156606, 1.437920, 1.739149, 2.254480, 3.285141",\ + "0.648620, 0.929984, 1.233457, 1.755819, 2.801810",\ + "0.702015, 0.983501, 1.284623, 1.798438, 2.827281",\ + "0.762846, 1.044428, 1.346174, 1.861729, 2.894061",\ + "0.897551, 1.179124, 1.480810, 1.996191, 3.028176",\ + "1.244017, 1.525542, 1.826863, 2.341195, 3.371075",\ + "0.737920, 1.019129, 1.321424, 1.843441, 2.888765",\ + "0.791317, 1.072648, 1.372590, 1.886060, 2.914236",\ + "0.852150, 1.133576, 1.434141, 1.949351, 2.981016",\ + "0.986854, 1.268272, 1.568777, 2.083813, 3.115131",\ + "1.333320, 1.614689, 1.914829, 2.428817, 3.458030",\ + "0.801540, 1.085002, 1.385573, 1.907354, 2.952274",\ + "0.854938, 1.138524, 1.436738, 1.949974, 2.977745",\ + "0.915772, 1.199455, 1.498289, 2.013264, 3.044525",\ + "1.050476, 1.334151, 1.632925, 2.147727, 3.178640",\ + "1.396941, 1.680567, 1.978977, 2.492730, 3.521539",\ + "1.137784, 1.452168, 1.737993, 2.256927, 3.297729",\ + "1.191192, 1.505727, 1.789070, 2.299511, 3.323201",\ + "1.252033, 1.566686, 1.850639, 2.362809, 3.389981",\ + "1.386736, 1.701380, 1.985273, 2.497271, 3.524096",\ + "1.733197, 2.047781, 2.331315, 2.842270, 3.866995"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.060194, 0.060374, 0.061744, 0.065730, 0.073703",\ + "0.114206, 0.114454, 0.116316, 0.121721, 0.132532",\ + "0.199891, 0.200118, 0.201818, 0.206753, 0.216623",\ + "0.445510, 0.445535, 0.445725, 0.446277, 0.447381",\ + "1.101426, 1.101414, 1.101326, 1.101071, 1.100560",\ + "0.060194, 0.060375, 0.061757, 0.065730, 0.073703",\ + "0.114206, 0.114455, 0.116333, 0.121721, 0.132532",\ + "0.199891, 0.200119, 0.201834, 0.206753, 0.216623",\ + "0.445510, 0.445535, 0.445727, 0.446277, 0.447381",\ + "1.101426, 1.101414, 1.101325, 1.101071, 1.100560",\ + "0.060197, 0.060379, 0.061757, 0.065730, 0.073703",\ + "0.114210, 0.114460, 0.116333, 0.121721, 0.132532",\ + "0.199895, 0.200123, 0.201834, 0.206753, 0.216623",\ + "0.445510, 0.445535, 0.445727, 0.446277, 0.447381",\ + "1.101426, 1.101414, 1.101325, 1.101071, 1.100560",\ + "0.060200, 0.060383, 0.061757, 0.065730, 0.073703",\ + "0.114213, 0.114466, 0.116334, 0.121721, 0.132532",\ + "0.199898, 0.200129, 0.201835, 0.206753, 0.216623",\ + "0.445510, 0.445536, 0.445727, 0.446277, 0.447381",\ + "1.101425, 1.101413, 1.101325, 1.101071, 1.100560",\ + "0.060213, 0.060438, 0.061798, 0.065747, 0.073703",\ + "0.114232, 0.114541, 0.116389, 0.121744, 0.132532",\ + "0.199915, 0.200198, 0.201885, 0.206773, 0.216623",\ + "0.445512, 0.445544, 0.445733, 0.446279, 0.447381",\ + "1.101425, 1.101410, 1.101323, 1.101070, 1.100560"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2367*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.746470, 1.014882, 1.306808, 1.802638, 2.794297",\ + "0.792702, 1.061114, 1.353041, 1.848873, 2.840536",\ + "0.876929, 1.145341, 1.437267, 1.933097, 2.924756",\ + "1.097854, 1.366266, 1.658190, 2.154013, 3.145659",\ + "1.658121, 1.926532, 2.218450, 2.714257, 3.705872",\ + "0.833878, 1.102487, 1.394459, 1.889352, 2.880230",\ + "0.880110, 1.148719, 1.440691, 1.935587, 2.926469",\ + "0.964337, 1.232946, 1.524917, 2.019811, 3.010689",\ + "1.185262, 1.453871, 1.745840, 2.240727, 3.231593",\ + "1.745530, 2.014137, 2.306100, 2.800972, 3.791806",\ + "0.914792, 1.191581, 1.482424, 1.976974, 2.967185",\ + "0.961024, 1.237813, 1.528656, 2.023208, 3.013424",\ + "1.045251, 1.322040, 1.612882, 2.107432, 3.097644",\ + "1.266176, 1.542965, 1.833805, 2.328349, 3.318548",\ + "1.826444, 2.103231, 2.394065, 2.888593, 3.878761",\ + "0.976718, 1.257380, 1.546568, 2.040887, 3.030694",\ + "1.022949, 1.303612, 1.592801, 2.087121, 3.076933",\ + "1.107176, 1.387838, 1.677027, 2.171345, 3.161153",\ + "1.328102, 1.608763, 1.897949, 2.392262, 3.382057",\ + "1.888369, 2.169030, 2.458210, 2.952506, 3.942270",\ + "1.314895, 1.623717, 1.898706, 2.390343, 3.376151",\ + "1.361127, 1.669949, 1.944939, 2.436577, 3.422390",\ + "1.445354, 1.754176, 2.029165, 2.520801, 3.506609",\ + "1.666279, 1.975101, 2.250087, 2.741717, 3.727513",\ + "2.226547, 2.535367, 2.810348, 3.301962, 4.287725"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\ + "2.163183, 2.163193, 2.163255, 2.163418, 2.163742",\ + "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\ + "2.163183, 2.163194, 2.163256, 2.163418, 2.163742",\ + "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\ + "2.163183, 2.163194, 2.163256, 2.163418, 2.163742",\ + "0.053085, 0.053087, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178915, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381898, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885384, 0.885342, 0.885232, 0.885012",\ + "2.163183, 2.163194, 2.163256, 2.163418, 2.163742",\ + "0.053085, 0.053088, 0.053099, 0.053129, 0.053189",\ + "0.178912, 0.178916, 0.178935, 0.178986, 0.179088",\ + "0.381897, 0.381899, 0.381907, 0.381931, 0.381978",\ + "0.885391, 0.885382, 0.885341, 0.885232, 0.885012",\ + "2.163183, 2.163198, 2.163258, 2.163418, 2.163742"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.695629, 0.964045, 1.256010, 1.751953, 2.743838",\ + "0.738170, 1.006582, 1.298507, 1.794334, 2.785986",\ + "0.793908, 1.062320, 1.354243, 1.850064, 2.841706",\ + "0.929637, 1.198049, 1.489976, 1.985806, 2.977466",\ + "1.279017, 1.547430, 1.839359, 2.335196, 3.326870",\ + "0.783037, 1.051650, 1.343661, 1.838667, 2.829772",\ + "0.825579, 1.094187, 1.386158, 1.881048, 2.871920",\ + "0.881317, 1.149925, 1.441893, 1.936778, 2.927640",\ + "1.017045, 1.285654, 1.577626, 2.072520, 3.063399",\ + "1.366425, 1.635035, 1.927009, 2.421910, 3.412804",\ + "0.863951, 1.140744, 1.431626, 1.926289, 2.916727",\ + "0.906492, 1.183281, 1.474123, 1.968669, 2.958875",\ + "0.962231, 1.239019, 1.529858, 2.024400, 3.014595",\ + "1.097959, 1.374748, 1.665591, 2.160141, 3.150354",\ + "1.447339, 1.724128, 2.014974, 2.509532, 3.499759",\ + "0.925877, 1.206543, 1.495770, 1.990202, 2.980236",\ + "0.968418, 1.249080, 1.538267, 2.032583, 3.022384",\ + "1.024156, 1.304818, 1.594002, 2.088313, 3.078104",\ + "1.159885, 1.440547, 1.729735, 2.224055, 3.213863",\ + "1.509265, 1.789927, 2.079118, 2.573445, 3.563268",\ + "1.264054, 1.572882, 1.847910, 2.339658, 3.325692",\ + "1.306595, 1.615417, 1.890405, 2.382038, 3.367840",\ + "1.362333, 1.671155, 1.946141, 2.437769, 3.423560",\ + "1.498062, 1.806884, 2.081874, 2.573510, 3.559319",\ + "1.847442, 2.156265, 2.431257, 2.922901, 3.908724"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.045780, 0.045773, 0.045733, 0.045626, 0.045413",\ + "0.094908, 0.094902, 0.094864, 0.094767, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\ + "0.045780, 0.045773, 0.045733, 0.045626, 0.045413",\ + "0.094908, 0.094902, 0.094864, 0.094767, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\ + "0.045780, 0.045773, 0.045733, 0.045626, 0.045413",\ + "0.094908, 0.094901, 0.094864, 0.094767, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\ + "0.045780, 0.045773, 0.045732, 0.045626, 0.045413",\ + "0.094908, 0.094901, 0.094864, 0.094767, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571",\ + "0.045780, 0.045771, 0.045731, 0.045626, 0.045413",\ + "0.094908, 0.094899, 0.094863, 0.094766, 0.094572",\ + "0.188970, 0.188970, 0.188972, 0.188977, 0.188987",\ + "0.443984, 0.443984, 0.443983, 0.443979, 0.443971",\ + "1.101591, 1.101591, 1.101588, 1.101583, 1.101571"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2564*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.720239, 0.982131, 1.267428, 1.744868, 2.699749",\ + "0.766471, 1.028363, 1.313660, 1.791102, 2.745986",\ + "0.850698, 1.112590, 1.397886, 1.875327, 2.830208",\ + "1.071623, 1.333515, 1.618809, 2.096245, 3.051117",\ + "1.631890, 1.893781, 2.179071, 2.656495, 3.611344",\ + "0.807647, 1.069728, 1.355020, 1.831583, 2.785683",\ + "0.853879, 1.115960, 1.401253, 1.877816, 2.831920",\ + "0.938106, 1.200187, 1.485479, 1.962041, 2.916142",\ + "1.159031, 1.421112, 1.706402, 2.182960, 3.137051",\ + "1.719299, 1.981378, 2.266663, 2.743210, 3.697278",\ + "0.888462, 1.158804, 1.442984, 1.919204, 2.872638",\ + "0.934694, 1.205035, 1.489217, 1.965438, 2.918875",\ + "1.018921, 1.289262, 1.573443, 2.049663, 3.003097",\ + "1.239846, 1.510187, 1.794366, 2.270581, 3.224006",\ + "1.800113, 2.070453, 2.354627, 2.830831, 3.784233",\ + "0.949702, 1.224575, 1.507125, 1.983117, 2.936147",\ + "0.995934, 1.270807, 1.553358, 2.029351, 2.982384",\ + "1.080161, 1.355034, 1.637584, 2.113576, 3.066606",\ + "1.301086, 1.575958, 1.858507, 2.334494, 3.287515",\ + "1.861354, 2.136225, 2.418768, 2.894744, 3.847742",\ + "1.285416, 1.590595, 1.859077, 2.332497, 3.281603",\ + "1.331648, 1.636827, 1.905309, 2.378731, 3.327840",\ + "1.415875, 1.721054, 1.989536, 2.462955, 3.412062",\ + "1.636800, 1.941979, 2.210458, 2.683874, 3.632971",\ + "2.197067, 2.502244, 2.770720, 3.244124, 4.193198"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178915, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\ + "0.885390, 0.885384, 0.885350, 0.885270, 0.885109",\ + "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\ + "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178915, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\ + "0.885390, 0.885384, 0.885350, 0.885270, 0.885109",\ + "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\ + "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178916, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\ + "0.885390, 0.885383, 0.885350, 0.885270, 0.885109",\ + "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\ + "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178916, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381898, 0.381905, 0.381923, 0.381957",\ + "0.885390, 0.885383, 0.885350, 0.885270, 0.885109",\ + "2.163185, 2.163195, 2.163244, 2.163362, 2.163599",\ + "0.053086, 0.053088, 0.053097, 0.053119, 0.053163",\ + "0.178912, 0.178917, 0.178931, 0.178968, 0.179043",\ + "0.381897, 0.381899, 0.381906, 0.381923, 0.381957",\ + "0.885390, 0.885381, 0.885349, 0.885270, 0.885109",\ + "2.163185, 2.163199, 2.163245, 2.163363, 2.163599"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.669399, 0.931295, 1.216611, 1.694099, 2.649075",\ + "0.711939, 0.973832, 1.259127, 1.736565, 2.691442",\ + "0.767677, 1.029569, 1.314863, 1.792297, 2.747166",\ + "0.903406, 1.165299, 1.450595, 1.928036, 2.882917",\ + "1.252786, 1.514679, 1.799978, 2.277424, 3.232316",\ + "0.756807, 1.018892, 1.304204, 1.780813, 2.735009",\ + "0.799348, 1.061428, 1.346719, 1.823279, 2.777375",\ + "0.855086, 1.117166, 1.402455, 1.879012, 2.833100",\ + "0.990815, 1.252895, 1.538187, 2.014750, 2.968851",\ + "1.340194, 1.602276, 1.887570, 2.364138, 3.318250",\ + "0.837622, 1.107967, 1.392168, 1.868435, 2.821964",\ + "0.880162, 1.150504, 1.434683, 1.910901, 2.864330",\ + "0.935900, 1.206241, 1.490419, 1.966633, 2.920055",\ + "1.071629, 1.341971, 1.626151, 2.102372, 3.055806",\ + "1.421009, 1.691351, 1.975534, 2.451760, 3.405205",\ + "0.898862, 1.173739, 1.456309, 1.932348, 2.885473",\ + "0.941403, 1.216275, 1.498824, 1.974814, 2.927839",\ + "0.997141, 1.272013, 1.554560, 2.030546, 2.983564",\ + "1.132869, 1.407742, 1.690292, 2.166285, 3.119315",\ + "1.482249, 1.757123, 2.039675, 2.515673, 3.468714",\ + "1.234576, 1.539761, 1.808261, 2.281728, 3.230929",\ + "1.277116, 1.582295, 1.850776, 2.324194, 3.273295",\ + "1.332854, 1.638033, 1.906512, 2.379926, 3.329020",\ + "1.468583, 1.773762, 2.042244, 2.515665, 3.464771",\ + "1.817963, 2.123143, 2.391627, 2.865052, 3.814170"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.045779, 0.045773, 0.045741, 0.045663, 0.045507",\ + "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\ + "0.045779, 0.045773, 0.045740, 0.045663, 0.045507",\ + "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\ + "0.045779, 0.045773, 0.045740, 0.045663, 0.045507",\ + "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\ + "0.045779, 0.045772, 0.045740, 0.045663, 0.045507",\ + "0.094907, 0.094901, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101591, 1.101589, 1.101584, 1.101576",\ + "0.045779, 0.045770, 0.045740, 0.045662, 0.045507",\ + "0.094907, 0.094898, 0.094871, 0.094800, 0.094658",\ + "0.188970, 0.188970, 0.188972, 0.188975, 0.188983",\ + "0.443984, 0.443984, 0.443983, 0.443980, 0.443975",\ + "1.101591, 1.101590, 1.101589, 1.101584, 1.101576"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2515*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.505424, 0.768046, 1.055041, 1.540850, 2.512468",\ + "0.551960, 0.814596, 1.101656, 1.587624, 2.559559",\ + "0.637620, 0.900293, 1.187543, 1.673963, 2.646803",\ + "0.860979, 1.123711, 1.411252, 1.898370, 2.872607",\ + "1.424976, 1.687784, 1.975705, 2.463734, 3.439793",\ + "0.593483, 0.855643, 1.142658, 1.627564, 2.598402",\ + "0.640020, 0.902192, 1.189274, 1.674337, 2.645493",\ + "0.725680, 0.987891, 1.275163, 1.760677, 2.732737",\ + "0.949039, 1.211309, 1.498873, 1.985084, 2.958541",\ + "1.513036, 1.775383, 2.063330, 2.550448, 3.525727",\ + "0.682045, 0.944707, 1.230622, 1.715185, 2.685357",\ + "0.728581, 0.991257, 1.277238, 1.761959, 2.732448",\ + "0.814241, 1.076956, 1.363127, 1.848298, 2.819692",\ + "1.037599, 1.300375, 1.586838, 2.072705, 3.045496",\ + "1.601596, 1.864452, 2.151294, 2.638070, 3.612682",\ + "0.745042, 1.010463, 1.294765, 1.779098, 2.748866",\ + "0.791578, 1.057013, 1.341381, 1.825872, 2.795957",\ + "0.877238, 1.142714, 1.427269, 1.912211, 2.883201",\ + "1.100596, 1.366135, 1.650980, 2.136618, 3.109005",\ + "1.664593, 1.930213, 2.215437, 2.701982, 3.676191",\ + "1.077301, 1.376325, 1.646801, 2.128510, 3.094322",\ + "1.123837, 1.422881, 1.693418, 2.175285, 3.141412",\ + "1.209496, 1.508595, 1.779311, 2.261626, 3.228657",\ + "1.432853, 1.732038, 2.003029, 2.486036, 3.454461",\ + "1.996848, 2.296144, 2.567495, 3.051404, 4.021647"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.052246, 0.052286, 0.053457, 0.057279, 0.064922",\ + "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378101, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885463, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163087, 2.163255, 2.163786, 2.164848",\ + "0.052246, 0.052286, 0.053469, 0.057279, 0.064922",\ + "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378101, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885464, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163087, 2.163257, 2.163786, 2.164848",\ + "0.052246, 0.052287, 0.053469, 0.057279, 0.064922",\ + "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378102, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885464, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163087, 2.163257, 2.163786, 2.164848",\ + "0.052246, 0.052288, 0.053470, 0.057279, 0.064922",\ + "0.174390, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378102, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885465, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163087, 2.163257, 2.163786, 2.164848",\ + "0.052246, 0.052302, 0.053509, 0.057295, 0.064922",\ + "0.174391, 0.174392, 0.174392, 0.174392, 0.174392",\ + "0.378103, 0.378105, 0.378105, 0.378105, 0.378105",\ + "0.885469, 0.885472, 0.885472, 0.885472, 0.885472",\ + "2.163077, 2.163090, 2.163262, 2.163788, 2.164848"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.443684, 0.706121, 0.992534, 1.477296, 2.446822",\ + "0.497094, 0.759709, 1.046667, 1.532387, 2.503829",\ + "0.557938, 0.820691, 1.108342, 1.595724, 2.570488",\ + "0.692641, 0.955383, 1.242975, 1.730217, 2.704702",\ + "1.039101, 1.301772, 1.589012, 2.075409, 3.048203",\ + "0.531743, 0.793716, 1.080148, 1.564010, 2.532755",\ + "0.585154, 0.847306, 1.134284, 1.619101, 2.589763",\ + "0.645997, 0.908289, 1.195965, 1.682438, 2.656422",\ + "0.780700, 1.042981, 1.330598, 1.816931, 2.790636",\ + "1.127160, 1.389370, 1.676632, 2.162122, 3.134136",\ + "0.620305, 0.882776, 1.168112, 1.651631, 2.619710",\ + "0.673715, 0.936370, 1.222248, 1.706723, 2.676718",\ + "0.734558, 0.997357, 1.283929, 1.770059, 2.743377",\ + "0.869261, 1.132048, 1.418562, 1.904553, 2.877591",\ + "1.215722, 1.478435, 1.764596, 2.249744, 3.221091",\ + "0.683303, 0.948526, 1.232255, 1.715544, 2.683219",\ + "0.736712, 1.002125, 1.286391, 1.770636, 2.740227",\ + "0.797555, 1.063117, 1.348072, 1.833972, 2.806886",\ + "0.932258, 1.197807, 1.482705, 1.968466, 2.941100",\ + "1.278719, 1.544192, 1.828738, 2.313657, 3.284600",\ + "1.015567, 1.314320, 1.584279, 2.064952, 3.028676",\ + "1.068972, 1.367985, 1.638425, 2.120048, 3.085683",\ + "1.129811, 1.429028, 1.700123, 2.183391, 3.152342",\ + "1.264514, 1.563714, 1.834755, 2.317884, 3.286556",\ + "1.610977, 1.910073, 2.180780, 2.663072, 3.630056"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.060218, 0.060490, 0.061813, 0.065017, 0.071424",\ + "0.114238, 0.114613, 0.116413, 0.120756, 0.129442",\ + "0.199921, 0.200263, 0.201907, 0.205872, 0.213802",\ + "0.445513, 0.445551, 0.445735, 0.446179, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\ + "0.060218, 0.060493, 0.061823, 0.065017, 0.071424",\ + "0.114238, 0.114616, 0.116427, 0.120756, 0.129442",\ + "0.199921, 0.200266, 0.201919, 0.205872, 0.213802",\ + "0.445513, 0.445551, 0.445736, 0.446179, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\ + "0.060218, 0.060498, 0.061824, 0.065017, 0.071424",\ + "0.114238, 0.114624, 0.116427, 0.120756, 0.129442",\ + "0.199921, 0.200273, 0.201920, 0.205872, 0.213802",\ + "0.445513, 0.445552, 0.445736, 0.446179, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\ + "0.060218, 0.060507, 0.061824, 0.065017, 0.071424",\ + "0.114238, 0.114635, 0.116428, 0.120756, 0.129442",\ + "0.199921, 0.200284, 0.201920, 0.205872, 0.213802",\ + "0.445513, 0.445553, 0.445737, 0.446179, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424",\ + "0.060218, 0.060603, 0.061857, 0.065030, 0.071424",\ + "0.114238, 0.114768, 0.116472, 0.120774, 0.129442",\ + "0.199921, 0.200405, 0.201961, 0.205888, 0.213802",\ + "0.445513, 0.445567, 0.445741, 0.446180, 0.447066",\ + "1.101424, 1.101424, 1.101424, 1.101424, 1.101424"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_2700*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[16]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.378256, 0.565826, 0.756593, 1.054119, 1.624836",\ + "0.428118, 0.615688, 0.806455, 1.103981, 1.674699",\ + "0.529986, 0.717556, 0.908323, 1.205849, 1.776567",\ + "0.767847, 0.955417, 1.146184, 1.443710, 2.014428",\ + "1.340168, 1.527737, 1.718505, 2.016031, 2.586749",\ + "0.466466, 0.653144, 0.843873, 1.141424, 1.712190",\ + "0.516328, 0.703006, 0.893736, 1.191286, 1.762052",\ + "0.618195, 0.804874, 0.995604, 1.293154, 1.863920",\ + "0.856057, 1.042735, 1.233465, 1.531015, 2.101782",\ + "1.428377, 1.615056, 1.805786, 2.103336, 2.674102",\ + "0.553983, 0.733479, 0.923900, 1.221452, 1.792222",\ + "0.603845, 0.783341, 0.973763, 1.271315, 1.842084",\ + "0.705713, 0.885209, 1.075631, 1.373183, 1.943952",\ + "0.943574, 1.123071, 1.313492, 1.611044, 2.181813",\ + "1.515895, 1.695391, 1.885813, 2.183364, 2.754134",\ + "0.611623, 0.791310, 0.981624, 1.278894, 1.849260",\ + "0.661485, 0.841172, 1.031486, 1.328757, 1.899123",\ + "0.763353, 0.943040, 1.133354, 1.430624, 2.000991",\ + "1.001214, 1.180901, 1.371215, 1.668486, 2.238852",\ + "1.573535, 1.753222, 1.943536, 2.240806, 2.811173",\ + "0.913876, 1.096638, 1.285285, 1.582076, 2.151510",\ + "0.963738, 1.146500, 1.335147, 1.631939, 2.201373",\ + "1.065606, 1.248368, 1.437015, 1.733807, 2.303241",\ + "1.303467, 1.486229, 1.674876, 1.971668, 2.541102",\ + "1.875787, 2.058550, 2.247197, 2.543989, 3.113423"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039802, 0.039802, 0.039803, 0.039804, 0.039804",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137192, 2.137192, 2.137192, 2.137192, 2.137192"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.406562, 0.606556, 0.797323, 1.091399, 1.653630",\ + "0.441336, 0.628906, 0.819673, 1.117199, 1.687917",\ + "0.482700, 0.670269, 0.861036, 1.158563, 1.729280",\ + "0.604735, 0.792305, 0.983072, 1.280598, 1.851316",\ + "0.936348, 1.123917, 1.314685, 1.612211, 2.182929",\ + "0.494915, 0.693874, 0.884604, 1.178704, 1.740983",\ + "0.529546, 0.716224, 0.906954, 1.204504, 1.775270",\ + "0.570909, 0.757588, 0.948317, 1.245868, 1.816634",\ + "0.692944, 0.879623, 1.070353, 1.367903, 1.938669",\ + "1.024557, 1.211236, 1.401965, 1.699516, 2.270282",\ + "0.583845, 0.774209, 0.964631, 1.258732, 1.821015",\ + "0.617063, 0.796559, 0.986981, 1.284533, 1.855302",\ + "0.658427, 0.837923, 1.028344, 1.325896, 1.896666",\ + "0.780462, 0.959958, 1.150380, 1.447932, 2.018701",\ + "1.112075, 1.291571, 1.481992, 1.779544, 2.350314",\ + "0.646974, 0.832040, 1.022354, 1.316164, 1.878034",\ + "0.674703, 0.854390, 1.044704, 1.341975, 1.912341",\ + "0.716066, 0.895753, 1.086067, 1.383338, 1.953704",\ + "0.838102, 1.017789, 1.208103, 1.505373, 2.075740",\ + "1.169714, 1.349402, 1.539716, 1.836986, 2.407352",\ + "0.954606, 1.137368, 1.326015, 1.619337, 2.180259",\ + "0.976956, 1.159718, 1.348365, 1.645157, 2.214591",\ + "1.018319, 1.201081, 1.389728, 1.686520, 2.255954",\ + "1.140355, 1.323117, 1.511764, 1.808556, 2.377990",\ + "1.471967, 1.654730, 1.843377, 2.140168, 2.709602"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001808, 0.074806, 0.161858, 0.321909, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2509*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[18]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.377666, 0.597755, 0.775019, 1.063430, 1.623644",\ + "0.425426, 0.645514, 0.822779, 1.111188, 1.671399",\ + "0.527520, 0.747609, 0.924873, 1.213283, 1.773495",\ + "0.765177, 0.985265, 1.162530, 1.450942, 2.011159",\ + "1.337186, 1.557274, 1.734539, 2.022954, 2.583179",\ + "0.466063, 0.685073, 0.862300, 1.150735, 1.710998",\ + "0.513823, 0.732832, 0.910060, 1.198493, 1.758752",\ + "0.615917, 0.834927, 1.012154, 1.300588, 1.860848",\ + "0.853574, 1.072584, 1.249811, 1.538247, 2.098513",\ + "1.425583, 1.644592, 1.821819, 2.110259, 2.670533",\ + "0.555414, 0.765406, 0.942327, 1.230764, 1.791029",\ + "0.603174, 0.813165, 0.990086, 1.278522, 1.838784",\ + "0.705268, 0.915260, 1.092181, 1.380617, 1.940880",\ + "0.942925, 1.152916, 1.329838, 1.618276, 2.178544",\ + "1.514933, 1.724925, 1.901846, 2.190288, 2.750564",\ + "0.619064, 0.823222, 1.000019, 1.288193, 1.848044",\ + "0.666823, 0.870981, 1.047778, 1.335951, 1.895798",\ + "0.768918, 0.973076, 1.149873, 1.438046, 1.997895",\ + "1.006574, 1.210732, 1.387530, 1.675705, 2.235559",\ + "1.578583, 1.782741, 1.959538, 2.247717, 2.807579",\ + "0.950146, 1.128438, 1.303674, 1.591364, 2.150265",\ + "0.997905, 1.176197, 1.351434, 1.639122, 2.198019",\ + "1.100000, 1.278292, 1.453528, 1.741217, 2.300115",\ + "1.337656, 1.515949, 1.691185, 1.978876, 2.537780",\ + "1.909665, 2.087957, 2.263194, 2.550888, 3.109800"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375682",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375682",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375682",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035377, 0.035377, 0.035377, 0.035399, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375681",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035377, 0.035377, 0.035377, 0.035400, 0.035455",\ + "0.147294, 0.147294, 0.147294, 0.147285, 0.147262",\ + "0.375697, 0.375697, 0.375697, 0.375693, 0.375681",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871174",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.402575, 0.622525, 0.800017, 1.088497, 1.648804",\ + "0.437980, 0.658068, 0.835333, 1.123750, 1.683980",\ + "0.479393, 0.699481, 0.876745, 1.165163, 1.725394",\ + "0.601610, 0.821698, 0.998963, 1.287380, 1.847608",\ + "0.933557, 1.153646, 1.330910, 1.619324, 2.179546",\ + "0.490972, 0.709843, 0.887297, 1.175802, 1.736157",\ + "0.526376, 0.745386, 0.922613, 1.211055, 1.771333",\ + "0.567789, 0.786799, 0.964026, 1.252468, 1.812747",\ + "0.690007, 0.909017, 1.086244, 1.374685, 1.934961",\ + "1.021954, 1.240964, 1.418191, 1.706629, 2.266899",\ + "0.580323, 0.790176, 0.967324, 1.255831, 1.816189",\ + "0.615727, 0.825719, 1.002640, 1.291084, 1.851365",\ + "0.657140, 0.867132, 1.044053, 1.332497, 1.892779",\ + "0.779358, 0.989349, 1.166271, 1.454713, 2.014993",\ + "1.111305, 1.321296, 1.498218, 1.786658, 2.346931",\ + "0.643973, 0.848003, 1.025017, 1.313260, 1.873204",\ + "0.679377, 0.883535, 1.060332, 1.348513, 1.908380",\ + "0.720790, 0.924948, 1.101745, 1.389926, 1.949794",\ + "0.843007, 1.047165, 1.223963, 1.512143, 2.072008",\ + "1.174954, 1.379112, 1.555910, 1.844087, 2.403945",\ + "0.972398, 1.153296, 1.328672, 1.616431, 2.175425",\ + "1.010459, 1.188751, 1.363988, 1.651684, 2.210601",\ + "1.051872, 1.230164, 1.405401, 1.693097, 2.252014",\ + "1.174089, 1.352381, 1.527618, 1.815314, 2.374228",\ + "1.506037, 1.684329, 1.859565, 2.147258, 2.706166"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039061",\ + "0.088924, 0.088924, 0.088924, 0.088923, 0.088920",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185897",\ + "0.432264, 0.432264, 0.432264, 0.432263, 0.432260",\ + "1.064285, 1.064285, 1.064285, 1.064278, 1.064261"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2574*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[21]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.170596, 0.344816, 0.534412, 0.834679, 1.413369",\ + "0.220441, 0.410383, 0.608141, 0.926922, 1.543926",\ + "0.296778, 0.497025, 0.695631, 1.028154, 1.678015",\ + "0.503693, 0.714118, 0.910633, 1.258044, 1.946084",\ + "1.056578, 1.269082, 1.463888, 1.813508, 2.508415",\ + "0.258804, 0.432134, 0.621693, 0.921985, 1.500723",\ + "0.308666, 0.497701, 0.695422, 1.014227, 1.631279",\ + "0.385015, 0.584343, 0.782912, 1.115460, 1.765368",\ + "0.591916, 0.801436, 0.997914, 1.345350, 2.033438",\ + "1.144755, 1.356400, 1.551169, 1.900813, 2.595769",\ + "0.340291, 0.512462, 0.701720, 1.002013, 1.580754",\ + "0.397987, 0.578029, 0.775449, 1.094256, 1.711311",\ + "0.474366, 0.664671, 0.862939, 1.195488, 1.845400",\ + "0.681230, 0.881765, 1.077941, 1.425378, 2.113470",\ + "1.233925, 1.436728, 1.631195, 1.980842, 2.675800",\ + "0.397929, 0.570271, 0.759443, 1.059465, 1.637816",\ + "0.461810, 0.635841, 0.833191, 1.151754, 1.768465",\ + "0.538221, 0.722485, 0.920682, 1.253027, 1.902633",\ + "0.745047, 0.939586, 1.135680, 1.482963, 2.170795",\ + "1.297604, 1.494552, 1.688930, 2.038435, 2.733142",\ + "0.700648, 0.875417, 1.063102, 1.362655, 1.940093",\ + "0.765372, 0.941013, 1.136853, 1.454984, 2.070854",\ + "0.851488, 1.027673, 1.224345, 1.556291, 2.205118",\ + "1.066931, 1.244823, 1.439341, 1.786267, 2.473392",\ + "1.621222, 1.799810, 1.992591, 2.341746, 3.035759"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.138974, 0.138974, 0.138974, 0.148690, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872440, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139579, 2.140538, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148690, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872464, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139603, 2.140538, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148690, 0.172413",\ + "0.231167, 0.231167, 0.231167, 0.238024, 0.254767",\ + "0.397287, 0.397287, 0.397287, 0.400375, 0.407916",\ + "0.872536, 0.873368, 0.873689, 0.874395, 0.875876",\ + "2.139678, 2.140538, 2.140572, 2.140672, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148719, 0.172470",\ + "0.231167, 0.231167, 0.231167, 0.238044, 0.254807",\ + "0.397287, 0.397287, 0.397287, 0.400384, 0.407935",\ + "0.872605, 0.873372, 0.873689, 0.874397, 0.875879",\ + "2.139749, 2.140541, 2.140572, 2.140673, 2.140918",\ + "0.138974, 0.138974, 0.138974, 0.148743, 0.172540",\ + "0.231167, 0.231167, 0.231167, 0.238062, 0.254856",\ + "0.397287, 0.397287, 0.397287, 0.400392, 0.407957",\ + "0.872560, 0.873396, 0.873689, 0.874398, 0.875884",\ + "2.139703, 2.140566, 2.140572, 2.140673, 2.140919"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.114526, 0.367093, 0.558483, 0.861637, 1.446138",\ + "0.150625, 0.396446, 0.587679, 0.892767, 1.482109",\ + "0.204730, 0.442254, 0.633143, 0.939029, 1.530580",\ + "0.336119, 0.565619, 0.755974, 1.061799, 1.653613",\ + "0.673349, 0.896842, 1.086112, 1.390772, 1.980608",\ + "0.202682, 0.454411, 0.645764, 0.948942, 1.533492",\ + "0.238886, 0.483764, 0.674960, 0.980073, 1.569463",\ + "0.292968, 0.529572, 0.720424, 1.026334, 1.617934",\ + "0.424327, 0.652937, 0.843255, 1.149104, 1.740967",\ + "0.761530, 0.984159, 1.173393, 1.478077, 2.067961",\ + "0.291788, 0.534739, 0.725791, 1.028971, 1.613523",\ + "0.328316, 0.564093, 0.754987, 1.060101, 1.649494",\ + "0.382328, 0.609901, 0.800451, 1.106363, 1.697965",\ + "0.513590, 0.733265, 0.923281, 1.229132, 1.820998",\ + "0.850714, 1.064488, 1.253420, 1.558105, 2.147993",\ + "0.355407, 0.592582, 0.783517, 1.086430, 1.670599",\ + "0.392245, 0.621934, 0.812712, 1.117566, 1.706581",\ + "0.446190, 0.667738, 0.858175, 1.163830, 1.755058",\ + "0.577359, 0.791098, 0.981005, 1.286600, 1.878091",\ + "0.914407, 1.122314, 1.311141, 1.615571, 2.205081",\ + "0.691600, 0.897972, 1.087176, 1.389626, 1.972893",\ + "0.730424, 0.927308, 1.116372, 1.420767, 2.008889",\ + "0.783940, 0.973087, 1.161835, 1.467034, 2.057372",\ + "0.914518, 1.096413, 1.284664, 1.589804, 2.180407",\ + "1.248497, 1.427586, 1.614800, 1.918772, 2.507391"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003224, 0.076222, 0.162920, 0.322617, 0.642011"); + values ( "0.055015, 0.067358, 0.073977, 0.088785, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432841, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.055327, 0.067358, 0.073977, 0.088785, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432868, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.056284, 0.067358, 0.073977, 0.088785, 0.119708",\ + "0.104870, 0.104870, 0.106669, 0.116295, 0.138275",\ + "0.190674, 0.190674, 0.191255, 0.196129, 0.207539",\ + "0.432953, 0.433934, 0.434139, 0.435063, 0.437176",\ + "1.062723, 1.062723, 1.063223, 1.064130, 1.065922",\ + "0.057202, 0.067404, 0.073991, 0.088823, 0.119782",\ + "0.104870, 0.104870, 0.106673, 0.116322, 0.138328",\ + "0.190674, 0.190674, 0.191256, 0.196143, 0.207567",\ + "0.433035, 0.433938, 0.434140, 0.435065, 0.437181",\ + "1.062723, 1.062723, 1.063224, 1.064132, 1.065926",\ + "0.063074, 0.067726, 0.073994, 0.088855, 0.119873",\ + "0.104870, 0.104870, 0.106674, 0.116345, 0.138392",\ + "0.190674, 0.190674, 0.191256, 0.196155, 0.207600",\ + "0.433555, 0.433967, 0.434140, 0.435067, 0.437187",\ + "1.062723, 1.062723, 1.063224, 1.064134, 1.065932"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2723*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[24]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.357397, 0.601995, 0.794649, 1.097312, 1.679722",\ + "0.405158, 0.649756, 0.842409, 1.145087, 1.727533",\ + "0.507252, 0.751850, 0.944504, 1.247180, 1.829623",\ + "0.744907, 0.989505, 1.182159, 1.483890, 2.064025",\ + "1.316914, 1.559947, 1.747496, 2.046616, 2.624655",\ + "0.445689, 0.689313, 0.881930, 1.184617, 1.767075",\ + "0.493449, 0.737074, 0.929690, 1.232392, 1.814886",\ + "0.595543, 0.839168, 1.031785, 1.334485, 1.916976",\ + "0.833198, 1.076823, 1.269440, 1.571195, 2.151379",\ + "1.405205, 1.647264, 1.834777, 2.133921, 2.712009",\ + "0.535203, 0.769642, 0.961957, 1.264645, 1.847107",\ + "0.582964, 0.817402, 1.009717, 1.312421, 1.894918",\ + "0.685058, 0.919496, 1.111811, 1.414514, 1.997008",\ + "0.922713, 1.157152, 1.349467, 1.651224, 2.231411",\ + "1.494720, 1.727593, 1.914804, 2.213950, 2.792040",\ + "0.599211, 0.827507, 1.019685, 1.322102, 1.904177",\ + "0.646972, 0.875268, 1.067446, 1.369877, 1.951988",\ + "0.749066, 0.977362, 1.169540, 1.471970, 2.054078",\ + "0.986721, 1.215017, 1.407195, 1.708678, 2.288475",\ + "1.558728, 1.785452, 1.972520, 2.271401, 2.849100",\ + "0.937895, 1.133051, 1.323345, 1.625296, 2.206465",\ + "0.985656, 1.180812, 1.371106, 1.673071, 2.254277",\ + "1.087750, 1.282906, 1.473200, 1.775164, 2.356366",\ + "1.325405, 1.520561, 1.710855, 2.011869, 2.590756",\ + "1.897411, 2.090956, 2.276178, 2.574590, 3.151375"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.035362, 0.035362, 0.035362, 0.035420, 0.035563",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035362, 0.035362, 0.035362, 0.035420, 0.035563",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035362, 0.035362, 0.035362, 0.035420, 0.035563",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035362, 0.035362, 0.035362, 0.035421, 0.035564",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600",\ + "0.035362, 0.035362, 0.035362, 0.035421, 0.035564",\ + "0.147300, 0.147300, 0.147300, 0.147294, 0.147280",\ + "0.375700, 0.375700, 0.375700, 0.375690, 0.375665",\ + "0.871174, 0.871174, 0.871174, 0.871174, 0.871175",\ + "2.136600, 2.136600, 2.136600, 2.136600, 2.136600"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.382270, 0.607170, 0.794344, 1.093466, 1.671509",\ + "0.417706, 0.645645, 0.832819, 1.131939, 1.709979",\ + "0.459119, 0.700449, 0.887937, 1.187057, 1.765097",\ + "0.581337, 0.825935, 1.018589, 1.319527, 1.897724",\ + "0.913286, 1.157884, 1.350538, 1.652760, 2.234094",\ + "0.470573, 0.694488, 0.881625, 1.180771, 1.758862",\ + "0.505998, 0.732962, 0.920100, 1.219244, 1.797333",\ + "0.547411, 0.787767, 0.975218, 1.274362, 1.852450",\ + "0.669629, 0.913253, 1.105870, 1.406832, 1.985077",\ + "1.001577, 1.245202, 1.437819, 1.740065, 2.321447",\ + "0.560124, 0.774817, 0.961652, 1.260799, 1.838894",\ + "0.595513, 0.813291, 1.000127, 1.299273, 1.877364",\ + "0.636925, 0.868096, 1.055245, 1.354391, 1.932482",\ + "0.759143, 0.993582, 1.185897, 1.486860, 2.065109",\ + "1.091092, 1.325531, 1.517846, 1.820093, 2.401479",\ + "0.624166, 0.832637, 1.019369, 1.318251, 1.895954",\ + "0.659520, 0.871112, 1.057843, 1.356724, 1.934424",\ + "0.700933, 0.925949, 1.112961, 1.411842, 1.989542",\ + "0.823151, 1.051447, 1.243625, 1.544312, 2.122169",\ + "1.155100, 1.383396, 1.575574, 1.877549, 2.458546",\ + "0.960128, 1.137870, 1.323027, 1.621440, 2.198229",\ + "0.998204, 1.176344, 1.361501, 1.659913, 2.236699",\ + "1.039617, 1.231408, 1.416619, 1.715032, 2.291817",\ + "1.161835, 1.356991, 1.547285, 1.847501, 2.424445",\ + "1.493784, 1.688940, 1.879234, 2.180742, 2.760831"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003210, 0.076209, 0.162911, 0.322611, 0.642011"); + values ( "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264",\ + "0.039065, 0.039065, 0.039065, 0.039064, 0.039059",\ + "0.088925, 0.088925, 0.088925, 0.088923, 0.088919",\ + "0.185901, 0.185901, 0.185901, 0.185900, 0.185895",\ + "0.432265, 0.432265, 0.432265, 0.432264, 0.432260",\ + "1.064290, 1.064290, 1.064290, 1.064282, 1.064264"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2363*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[26]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.348095, 0.545075, 0.727042, 1.018426, 1.581852",\ + "0.397956, 0.594939, 0.776906, 1.068290, 1.631715",\ + "0.499824, 0.696806, 0.878774, 1.170157, 1.733583",\ + "0.737685, 0.934668, 1.116635, 1.408019, 1.971444",\ + "1.310006, 1.506989, 1.688956, 1.980340, 2.543765",\ + "0.436445, 0.632394, 0.814323, 1.105731, 1.669206",\ + "0.486307, 0.682257, 0.864187, 1.155595, 1.719068",\ + "0.588175, 0.784125, 0.966055, 1.257463, 1.820936",\ + "0.826036, 1.021986, 1.203916, 1.495324, 2.058797",\ + "1.398357, 1.594307, 1.776237, 2.067645, 2.631118",\ + "0.525620, 0.712727, 0.894350, 1.185759, 1.749237",\ + "0.575481, 0.762590, 0.944214, 1.235623, 1.799100",\ + "0.677349, 0.864458, 1.046082, 1.337491, 1.900968",\ + "0.915211, 1.102319, 1.283943, 1.575353, 2.138829",\ + "1.487531, 1.674640, 1.856264, 2.147673, 2.711150",\ + "0.589087, 0.770548, 0.952053, 1.243192, 1.806260",\ + "0.638949, 0.820411, 1.001917, 1.293056, 1.856122",\ + "0.740817, 0.922279, 1.103785, 1.394924, 1.957990",\ + "0.978678, 1.160140, 1.341646, 1.632786, 2.195851",\ + "1.550998, 1.732461, 1.913967, 2.205106, 2.768172",\ + "0.896146, 1.075801, 1.255710, 1.546367, 2.108490",\ + "0.946008, 1.125664, 1.305574, 1.596231, 2.158352",\ + "1.047876, 1.227532, 1.407442, 1.698099, 2.260220",\ + "1.285737, 1.465394, 1.645303, 1.935960, 2.498081",\ + "1.858057, 2.037714, 2.217624, 2.508281, 3.070402"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192",\ + "0.039799, 0.039799, 0.039799, 0.039799, 0.039799",\ + "0.147770, 0.147770, 0.147770, 0.147770, 0.147770",\ + "0.375009, 0.375009, 0.375009, 0.375009, 0.375009",\ + "0.869291, 0.869291, 0.869292, 0.869292, 0.869292",\ + "2.137191, 2.137192, 2.137192, 2.137192, 2.137192"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.386309, 0.585807, 0.767775, 1.059158, 1.622583",\ + "0.411174, 0.608157, 0.790125, 1.081508, 1.644933",\ + "0.452537, 0.649520, 0.831488, 1.122872, 1.686296",\ + "0.574573, 0.771556, 0.953524, 1.244907, 1.808332",\ + "0.906186, 1.103168, 1.285136, 1.576519, 2.139944",\ + "0.474546, 0.673125, 0.855056, 1.146463, 1.709936",\ + "0.499525, 0.695475, 0.877406, 1.168813, 1.732286",\ + "0.540888, 0.736839, 0.918769, 1.210177, 1.773650",\ + "0.662924, 0.858874, 1.040805, 1.332212, 1.895685",\ + "0.994536, 1.190487, 1.372417, 1.663825, 2.227298",\ + "0.563389, 0.753458, 0.935083, 1.226492, 1.789968",\ + "0.588699, 0.775808, 0.957433, 1.248842, 1.812318",\ + "0.630063, 0.817172, 0.998796, 1.290205, 1.853681",\ + "0.752098, 0.939207, 1.120831, 1.412241, 1.975717",\ + "1.083711, 1.270820, 1.452444, 1.743853, 2.307329",\ + "0.626548, 0.811280, 0.992786, 1.283925, 1.846990",\ + "0.652167, 0.833630, 1.015136, 1.306275, 1.869340",\ + "0.693530, 0.874993, 1.056499, 1.347638, 1.910704",\ + "0.815566, 0.997028, 1.178535, 1.469674, 2.032739",\ + "1.147178, 1.328641, 1.510147, 1.801286, 2.364352",\ + "0.936876, 1.116533, 1.296443, 1.587100, 2.149220",\ + "0.959225, 1.138883, 1.318793, 1.609450, 2.171570",\ + "1.000589, 1.180246, 1.360156, 1.650813, 2.212934",\ + "1.122624, 1.302282, 1.482192, 1.772848, 2.334969",\ + "1.454237, 1.633894, 1.813804, 2.104461, 2.666582"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002267, 0.075266, 0.162203, 0.322139, 0.642011"); + values ( "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247",\ + "0.045856, 0.045856, 0.045856, 0.045856, 0.045856",\ + "0.091389, 0.091389, 0.091389, 0.091389, 0.091389",\ + "0.185814, 0.185814, 0.185814, 0.185814, 0.185814",\ + "0.432252, 0.432252, 0.432252, 0.432252, 0.432252",\ + "1.064247, 1.064247, 1.064247, 1.064247, 1.064247"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2685*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[27]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.226427, 0.405869, 0.606598, 0.932774, 1.565599",\ + "0.282384, 0.460178, 0.659964, 0.990994, 1.636396",\ + "0.358192, 0.534364, 0.733448, 1.069708, 1.728405",\ + "0.560390, 0.734140, 0.930018, 1.272669, 1.949568",\ + "1.105015, 1.276795, 1.468799, 1.815230, 2.504534",\ + "0.313828, 0.493186, 0.693879, 1.020079, 1.652953",\ + "0.369785, 0.547496, 0.747245, 1.078299, 1.723750",\ + "0.445593, 0.621681, 0.820729, 1.157013, 1.815759",\ + "0.647791, 0.821458, 1.017299, 1.359975, 2.036922",\ + "1.192415, 1.364112, 1.556080, 1.902535, 2.591887",\ + "0.394677, 0.573514, 0.773906, 1.100108, 1.732984",\ + "0.450625, 0.627823, 0.827272, 1.158327, 1.803782",\ + "0.526423, 0.702008, 0.900756, 1.237042, 1.895791",\ + "0.728608, 0.901785, 1.097326, 1.440003, 2.116953",\ + "1.273221, 1.444439, 1.636107, 1.982563, 2.671918",\ + "0.452415, 0.631348, 0.831654, 1.157626, 1.790177",\ + "0.508343, 0.685651, 0.885018, 1.215861, 1.861005",\ + "0.584122, 0.759831, 0.958501, 1.294592, 1.953046",\ + "0.786278, 0.959598, 1.155063, 1.497575, 2.174253",\ + "1.330868, 1.502245, 1.693835, 2.040151, 2.729248",\ + "0.756161, 0.936672, 1.135317, 1.460873, 2.092613",\ + "0.811907, 0.990932, 1.188681, 1.519120, 2.163478",\ + "0.887507, 1.065070, 1.262163, 1.597865, 2.255558",\ + "1.089394, 1.264774, 1.458724, 1.800867, 2.476817",\ + "1.633766, 1.807370, 1.997495, 2.343456, 3.031849"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.149901, 0.149901, 0.154318, 0.175674, 0.224033",\ + "0.237266, 0.237266, 0.240233, 0.254222, 0.285839",\ + "0.400134, 0.400516, 0.400740, 0.407020, 0.422153",\ + "0.873536, 0.873536, 0.873536, 0.874627, 0.877289",\ + "2.137014, 2.139136, 2.139203, 2.139990, 2.141907",\ + "0.149901, 0.149901, 0.154318, 0.175674, 0.224033",\ + "0.237266, 0.237266, 0.240233, 0.254222, 0.285839",\ + "0.400134, 0.400516, 0.400740, 0.407020, 0.422153",\ + "0.873536, 0.873536, 0.873536, 0.874627, 0.877289",\ + "2.137014, 2.139136, 2.139203, 2.139990, 2.141907",\ + "0.149901, 0.149901, 0.154318, 0.175674, 0.224033",\ + "0.237266, 0.237266, 0.240233, 0.254222, 0.285839",\ + "0.400136, 0.400516, 0.400740, 0.407020, 0.422153",\ + "0.873536, 0.873536, 0.873536, 0.874627, 0.877289",\ + "2.137026, 2.139136, 2.139203, 2.139990, 2.141907",\ + "0.149901, 0.149901, 0.154329, 0.175732, 0.224149",\ + "0.237266, 0.237266, 0.240240, 0.254260, 0.285916",\ + "0.400141, 0.400517, 0.400740, 0.407038, 0.422190",\ + "0.873536, 0.873536, 0.873536, 0.874631, 0.877295",\ + "2.137051, 2.139143, 2.139203, 2.139992, 2.141911",\ + "0.149901, 0.149901, 0.154330, 0.175783, 0.224291",\ + "0.237266, 0.237266, 0.240241, 0.254293, 0.286008",\ + "0.400183, 0.400527, 0.400740, 0.407054, 0.422234",\ + "0.873536, 0.873536, 0.873536, 0.874633, 0.877303",\ + "2.137286, 2.139199, 2.139203, 2.139994, 2.141917"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.152176, 0.424550, 0.621056, 0.937588, 1.550446",\ + "0.188303, 0.458742, 0.655289, 0.973816, 1.591506",\ + "0.242989, 0.508512, 0.704797, 1.024208, 1.644274",\ + "0.376456, 0.636940, 0.832877, 1.152112, 1.772037",\ + "0.711310, 0.972696, 1.168342, 1.486421, 2.103779",\ + "0.240546, 0.511867, 0.708337, 1.024893, 1.637799",\ + "0.276651, 0.546059, 0.742570, 1.061121, 1.678860",\ + "0.331309, 0.595830, 0.792078, 1.111513, 1.731628",\ + "0.464761, 0.724258, 0.920158, 1.239417, 1.859390",\ + "0.799595, 1.060013, 1.255623, 1.573726, 2.191132",\ + "0.330479, 0.592194, 0.788364, 1.104922, 1.717831",\ + "0.366514, 0.626386, 0.822597, 1.141150, 1.758891",\ + "0.421085, 0.676157, 0.872105, 1.191542, 1.811660",\ + "0.554489, 0.804585, 1.000185, 1.319445, 1.939422",\ + "0.889264, 1.140340, 1.335650, 1.653755, 2.271164",\ + "0.394961, 0.650030, 0.846103, 1.162416, 1.774975",\ + "0.430928, 0.684222, 0.880335, 1.198650, 1.816048",\ + "0.485415, 0.733993, 0.929843, 1.249045, 1.868822",\ + "0.618773, 0.862421, 1.057922, 1.376948, 1.996584",\ + "0.953489, 1.198177, 1.393386, 1.711254, 2.328319",\ + "0.736666, 0.955361, 1.149764, 1.465641, 2.077353",\ + "0.772199, 0.989556, 1.183996, 1.501880, 2.118440",\ + "0.826145, 1.039328, 1.233504, 1.552278, 2.171221",\ + "0.959204, 1.167753, 1.361583, 1.680181, 2.298982",\ + "1.293546, 1.503515, 1.697047, 2.014484, 2.630710"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.003525, 0.076523, 0.163147, 0.322768, 0.642011"); + values ( "0.071550, 0.071795, 0.076447, 0.093063, 0.129680",\ + "0.104996, 0.104996, 0.106778, 0.118004, 0.143877",\ + "0.191021, 0.191212, 0.191736, 0.197505, 0.211137",\ + "0.431517, 0.431517, 0.431517, 0.433292, 0.437617",\ + "1.063952, 1.065332, 1.065376, 1.065376, 1.065376",\ + "0.071556, 0.071795, 0.076447, 0.093063, 0.129680",\ + "0.104996, 0.104996, 0.106778, 0.118004, 0.143877",\ + "0.191026, 0.191212, 0.191736, 0.197505, 0.211137",\ + "0.431517, 0.431517, 0.431517, 0.433292, 0.437617",\ + "1.063986, 1.065332, 1.065376, 1.065376, 1.065376",\ + "0.071574, 0.071795, 0.076447, 0.093063, 0.129680",\ + "0.104996, 0.104996, 0.106778, 0.118004, 0.143877",\ + "0.191041, 0.191212, 0.191736, 0.197505, 0.211137",\ + "0.431517, 0.431517, 0.431517, 0.433292, 0.437617",\ + "1.064092, 1.065332, 1.065376, 1.065376, 1.065376",\ + "0.071593, 0.071796, 0.076458, 0.093108, 0.129768",\ + "0.104996, 0.104996, 0.106782, 0.118035, 0.143939",\ + "0.191055, 0.191213, 0.191737, 0.197522, 0.211169",\ + "0.431517, 0.431517, 0.431517, 0.433297, 0.437628",\ + "1.064195, 1.065337, 1.065376, 1.065376, 1.065376",\ + "0.071710, 0.071803, 0.076460, 0.093146, 0.129875",\ + "0.104996, 0.104996, 0.106783, 0.118062, 0.144015",\ + "0.191146, 0.191218, 0.191737, 0.197536, 0.211209",\ + "0.431517, 0.431517, 0.431517, 0.433301, 0.437640",\ + "1.064855, 1.065373, 1.065376, 1.065376, 1.065376"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2743*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[28]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.511543, 0.732095, 0.909621, 1.198355, 1.759116",\ + "0.561373, 0.781924, 0.959450, 1.248185, 1.808946",\ + "0.663244, 0.883796, 1.061322, 1.350056, 1.910817",\ + "0.901102, 1.121654, 1.299180, 1.587914, 2.148676",\ + "1.473419, 1.693970, 1.871496, 2.160231, 2.720992",\ + "0.599955, 0.819413, 0.996902, 1.285660, 1.846469",\ + "0.649784, 0.869243, 1.046731, 1.335490, 1.896299",\ + "0.751656, 0.971114, 1.148603, 1.437361, 1.998171",\ + "0.989514, 1.208973, 1.386461, 1.675220, 2.236029",\ + "1.561830, 1.781289, 1.958777, 2.247536, 2.808345",\ + "0.689055, 0.899748, 1.076928, 1.365689, 1.926501",\ + "0.738884, 0.949578, 1.126758, 1.415518, 1.976331",\ + "0.840756, 1.051450, 1.228629, 1.517390, 2.078202",\ + "1.078614, 1.289308, 1.466488, 1.755248, 2.316061",\ + "1.650930, 1.861624, 2.038804, 2.327564, 2.888377",\ + "0.752342, 0.957565, 1.134620, 1.423118, 1.983516",\ + "0.802171, 1.007395, 1.184450, 1.472948, 2.033346",\ + "0.904043, 1.109266, 1.286322, 1.574819, 2.135217",\ + "1.141901, 1.347125, 1.524180, 1.812678, 2.373076",\ + "1.714217, 1.919441, 2.096496, 2.384994, 2.945392",\ + "1.083355, 1.262794, 1.438277, 1.726290, 2.285737",\ + "1.133185, 1.312624, 1.488106, 1.776120, 2.335567",\ + "1.235056, 1.414496, 1.589978, 1.877991, 2.437438",\ + "1.472914, 1.652354, 1.827836, 2.115849, 2.675297",\ + "2.045231, 2.224670, 2.400152, 2.688166, 3.247612"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.544225, 0.764777, 0.942302, 1.231037, 1.791798",\ + "0.574581, 0.795133, 0.972659, 1.261393, 1.822155",\ + "0.615945, 0.836497, 1.014023, 1.302758, 1.863519",\ + "0.737984, 0.958535, 1.136061, 1.424796, 1.985557",\ + "1.069601, 1.290153, 1.467679, 1.756413, 2.317174",\ + "0.632637, 0.852095, 1.029583, 1.318342, 1.879151",\ + "0.662993, 0.882452, 1.059940, 1.348698, 1.909508",\ + "0.704357, 0.923816, 1.101304, 1.390063, 1.950872",\ + "0.826395, 1.045854, 1.223342, 1.512101, 2.072910",\ + "1.158013, 1.377472, 1.554960, 1.843718, 2.404528",\ + "0.721737, 0.932430, 1.109610, 1.398370, 1.959183",\ + "0.752093, 0.962787, 1.139967, 1.428727, 1.989540",\ + "0.793457, 1.004151, 1.181331, 1.470091, 2.030904",\ + "0.915496, 1.126189, 1.303369, 1.592129, 2.152942",\ + "1.247113, 1.457807, 1.634987, 1.923747, 2.484560",\ + "0.785023, 0.990247, 1.167302, 1.455800, 2.016198",\ + "0.815380, 1.020603, 1.197659, 1.486156, 2.046555",\ + "0.856744, 1.061968, 1.239023, 1.527521, 2.087919",\ + "0.978782, 1.184006, 1.361061, 1.649559, 2.209957",\ + "1.310400, 1.515623, 1.692679, 1.981176, 2.541574",\ + "1.116037, 1.295476, 1.470958, 1.758972, 2.318419",\ + "1.146393, 1.325833, 1.501315, 1.789329, 2.348775",\ + "1.187757, 1.367197, 1.542679, 1.830693, 2.390140",\ + "1.309796, 1.489235, 1.664717, 1.952731, 2.512178",\ + "1.641413, 1.820853, 1.996335, 2.284348, 2.843795"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001816, 0.074814, 0.161865, 0.321913, 0.642011"); + values ( "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[29]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.493881, 0.730366, 0.921755, 1.228337, 1.821155",\ + "0.543711, 0.780195, 0.971585, 1.278167, 1.870984",\ + "0.645582, 0.882067, 1.073456, 1.380038, 1.972856",\ + "0.883440, 1.119925, 1.311315, 1.617896, 2.210714",\ + "1.455756, 1.692241, 1.883631, 2.190213, 2.783030",\ + "0.582168, 0.817683, 1.009036, 1.315642, 1.908508",\ + "0.631998, 0.867513, 1.058866, 1.365472, 1.958338",\ + "0.733870, 0.969384, 1.160737, 1.467343, 2.060209",\ + "0.971728, 1.207243, 1.398596, 1.705202, 2.298068",\ + "1.544044, 1.779559, 1.970912, 2.277518, 2.870384",\ + "0.671482, 0.898014, 1.089063, 1.395671, 1.988540",\ + "0.721312, 0.947843, 1.138893, 1.445500, 2.038369",\ + "0.823183, 1.049715, 1.240764, 1.547372, 2.140241",\ + "1.061042, 1.287573, 1.478623, 1.785230, 2.378099",\ + "1.633358, 1.859889, 2.050939, 2.357546, 2.950415",\ + "0.735219, 0.955859, 1.146789, 1.453140, 2.045635",\ + "0.785049, 1.005688, 1.196618, 1.502970, 2.095464",\ + "0.886921, 1.107560, 1.298490, 1.604841, 2.197336",\ + "1.124779, 1.345418, 1.536348, 1.842699, 2.435194",\ + "1.697095, 1.917734, 2.108664, 2.415015, 3.007510",\ + "1.072194, 1.261268, 1.450449, 1.756345, 2.347952",\ + "1.122024, 1.311097, 1.500278, 1.806174, 2.397781",\ + "1.223895, 1.412969, 1.602150, 1.908046, 2.499653",\ + "1.461754, 1.650827, 1.840008, 2.145904, 2.737511",\ + "2.034070, 2.223143, 2.412324, 2.718220, 3.309827"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213",\ + "0.039738, 0.039738, 0.039738, 0.039738, 0.039738",\ + "0.147762, 0.147762, 0.147762, 0.147762, 0.147762",\ + "0.375019, 0.375019, 0.375019, 0.375019, 0.375019",\ + "0.869329, 0.869329, 0.869329, 0.869329, 0.869329",\ + "2.137213, 2.137213, 2.137213, 2.137213, 2.137213"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.526563, 0.763047, 0.954437, 1.261019, 1.853837",\ + "0.556919, 0.793404, 0.984794, 1.291375, 1.884193",\ + "0.598283, 0.834768, 1.026158, 1.332739, 1.925557",\ + "0.720322, 0.956806, 1.148196, 1.454778, 2.047596",\ + "1.051939, 1.288424, 1.479813, 1.786395, 2.379213",\ + "0.614850, 0.850365, 1.041718, 1.348324, 1.941190",\ + "0.645207, 0.880722, 1.072075, 1.378680, 1.971546",\ + "0.686571, 0.922086, 1.113439, 1.420045, 2.012911",\ + "0.808609, 1.044124, 1.235477, 1.542083, 2.134949",\ + "1.140227, 1.375741, 1.567094, 1.873700, 2.466566",\ + "0.704164, 0.930695, 1.121745, 1.428352, 2.021222",\ + "0.734520, 0.961052, 1.152102, 1.458709, 2.051578",\ + "0.775885, 1.002416, 1.193466, 1.500073, 2.092942",\ + "0.897923, 1.124454, 1.315504, 1.622111, 2.214981",\ + "1.229540, 1.456072, 1.647121, 1.953729, 2.546598",\ + "0.767901, 0.988540, 1.179470, 1.485822, 2.078316",\ + "0.798258, 1.018897, 1.209827, 1.516178, 2.108673",\ + "0.839622, 1.060261, 1.251191, 1.557542, 2.150037",\ + "0.961660, 1.182299, 1.373229, 1.679581, 2.272075",\ + "1.293278, 1.513917, 1.704847, 2.011198, 2.603693",\ + "1.104876, 1.293949, 1.483130, 1.789026, 2.380633",\ + "1.135232, 1.324306, 1.513487, 1.819383, 2.410990",\ + "1.176597, 1.365670, 1.554851, 1.860747, 2.452354",\ + "1.298635, 1.487708, 1.676889, 1.982785, 2.574392",\ + "1.630252, 1.819326, 2.008507, 2.314403, 2.906010"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045860, 0.045860, 0.045860",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091392",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185815",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2333*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[31]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.470602, 0.685204, 0.866879, 1.157031, 1.717773",\ + "0.518644, 0.733246, 0.914922, 1.205074, 1.765816",\ + "0.620710, 0.835312, 1.016988, 1.307140, 1.867882",\ + "0.851211, 1.065814, 1.247489, 1.537641, 2.098383",\ + "1.409103, 1.623705, 1.805381, 2.095532, 2.656275",\ + "0.558998, 0.772522, 0.954160, 1.244336, 1.805127",\ + "0.607041, 0.820565, 1.002203, 1.292379, 1.853169",\ + "0.709107, 0.922631, 1.104269, 1.394445, 1.955235",\ + "0.939608, 1.153132, 1.334770, 1.624946, 2.185737",\ + "1.497499, 1.711023, 1.892661, 2.182837, 2.743628",\ + "0.648348, 0.852854, 1.034187, 1.324365, 1.885158",\ + "0.696391, 0.900897, 1.082230, 1.372408, 1.933201",\ + "0.798457, 1.002963, 1.184296, 1.474474, 2.035267",\ + "1.028958, 1.233464, 1.414797, 1.704975, 2.265768",\ + "1.586850, 1.791356, 1.972688, 2.262866, 2.823659",\ + "0.711997, 0.910682, 1.091889, 1.381795, 1.942174",\ + "0.760040, 0.958725, 1.139932, 1.429837, 1.990217",\ + "0.862106, 1.060791, 1.241998, 1.531904, 2.092283",\ + "1.092607, 1.291292, 1.472499, 1.762405, 2.322784",\ + "1.650499, 1.849183, 2.030391, 2.320296, 2.880676",\ + "1.035012, 1.215977, 1.395546, 1.684966, 2.244397",\ + "1.083055, 1.264019, 1.443589, 1.733009, 2.292439",\ + "1.185121, 1.366086, 1.545655, 1.835075, 2.394506",\ + "1.415622, 1.596586, 1.776156, 2.065576, 2.625007",\ + "1.973513, 2.154478, 2.334047, 2.623468, 3.182898"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.455792, 0.670394, 0.852070, 1.142222, 1.702964",\ + "0.494395, 0.708997, 0.890673, 1.180825, 1.741567",\ + "0.549522, 0.764125, 0.945800, 1.235952, 1.796694",\ + "0.682338, 0.896940, 1.078616, 1.368768, 1.929510",\ + "1.022840, 1.237442, 1.419117, 1.709269, 2.270011",\ + "0.544189, 0.757712, 0.939351, 1.229527, 1.790317",\ + "0.582792, 0.796315, 0.977954, 1.268130, 1.828920",\ + "0.637919, 0.851443, 1.033081, 1.323257, 1.884048",\ + "0.770735, 0.984258, 1.165897, 1.456073, 2.016863",\ + "1.111236, 1.324760, 1.506398, 1.796574, 2.357365",\ + "0.633539, 0.838045, 1.019377, 1.309555, 1.870349",\ + "0.672142, 0.876648, 1.057981, 1.348158, 1.908952",\ + "0.727269, 0.931775, 1.113108, 1.403286, 1.964079",\ + "0.860085, 1.064591, 1.245924, 1.536101, 2.096895",\ + "1.200586, 1.405093, 1.586425, 1.876603, 2.437396",\ + "0.697188, 0.895872, 1.077080, 1.366985, 1.927365",\ + "0.735791, 0.934475, 1.115683, 1.405588, 1.965968",\ + "0.790918, 0.989603, 1.170810, 1.460716, 2.021095",\ + "0.923734, 1.122418, 1.303626, 1.593531, 2.153911",\ + "1.264235, 1.462920, 1.644127, 1.934033, 2.494412",\ + "1.020202, 1.201167, 1.380737, 1.670157, 2.229587",\ + "1.058805, 1.239770, 1.419340, 1.708760, 2.268190",\ + "1.113933, 1.294898, 1.474467, 1.763887, 2.323318",\ + "1.246748, 1.427713, 1.607283, 1.896703, 2.456133",\ + "1.587250, 1.768215, 1.947784, 2.237205, 2.796635"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002343, 0.075342, 0.162260, 0.322177, 0.642011"); + values ( "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039238, 0.039238, 0.039238, 0.039238, 0.039238",\ + "0.089111, 0.089111, 0.089111, 0.089111, 0.089111",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2437*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[33]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.448199, 0.668078, 0.854477, 1.152594, 1.728783",\ + "0.496242, 0.716121, 0.902520, 1.200637, 1.776826",\ + "0.598308, 0.818187, 1.004586, 1.302703, 1.878892",\ + "0.828809, 1.048688, 1.235087, 1.533204, 2.109392",\ + "1.386700, 1.606579, 1.792978, 2.091095, 2.667284",\ + "0.536520, 0.755396, 0.941758, 1.239900, 1.816137",\ + "0.584563, 0.803439, 0.989801, 1.287942, 1.864179",\ + "0.686629, 0.905505, 1.091867, 1.390008, 1.966245",\ + "0.917129, 1.136006, 1.322368, 1.620509, 2.196746",\ + "1.475021, 1.693897, 1.880259, 2.178401, 2.754637",\ + "0.625932, 0.835726, 1.021785, 1.319928, 1.896168",\ + "0.673975, 0.883769, 1.069828, 1.367971, 1.944211",\ + "0.776041, 0.985835, 1.171894, 1.470037, 2.046277",\ + "1.006542, 1.216336, 1.402395, 1.700537, 2.276778",\ + "1.564433, 1.774227, 1.960286, 2.258429, 2.834669",\ + "0.689763, 0.893549, 1.079499, 1.377377, 1.953223",\ + "0.737806, 0.941592, 1.127542, 1.425420, 2.001266",\ + "0.839872, 1.043658, 1.229608, 1.527486, 2.103332",\ + "1.070373, 1.274158, 1.460109, 1.757986, 2.333832",\ + "1.628264, 1.832049, 2.018000, 2.315878, 2.891724",\ + "1.020000, 1.198799, 1.383157, 1.680565, 2.255491",\ + "1.068043, 1.246842, 1.431200, 1.728607, 2.303534",\ + "1.170109, 1.348908, 1.533266, 1.830673, 2.405600",\ + "1.400609, 1.579409, 1.763767, 2.061174, 2.636101",\ + "1.958501, 2.137300, 2.321658, 2.619065, 3.193992"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871151, 0.871151, 0.871151, 0.871151, 0.871151",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.433389, 0.653268, 0.839667, 1.137784, 1.713973",\ + "0.471993, 0.691871, 0.878270, 1.176387, 1.752576",\ + "0.527120, 0.746999, 0.933398, 1.231515, 1.807704",\ + "0.659935, 0.879814, 1.066213, 1.364330, 1.940519",\ + "1.000437, 1.220316, 1.406715, 1.704832, 2.281021",\ + "0.521709, 0.740586, 0.926948, 1.225089, 1.801326",\ + "0.560313, 0.779189, 0.965551, 1.263693, 1.839930",\ + "0.615440, 0.834317, 1.020679, 1.318820, 1.895057",\ + "0.748256, 0.967132, 1.153494, 1.451635, 2.027873",\ + "1.088757, 1.307634, 1.493996, 1.792137, 2.368374",\ + "0.611122, 0.820916, 1.006975, 1.305118, 1.881358",\ + "0.649725, 0.859520, 1.045578, 1.343721, 1.919961",\ + "0.704853, 0.914647, 1.100706, 1.398849, 1.975089",\ + "0.837668, 1.047462, 1.233521, 1.531664, 2.107904",\ + "1.178170, 1.387964, 1.574023, 1.872166, 2.448406",\ + "0.674953, 0.878738, 1.064689, 1.362566, 1.938412",\ + "0.713556, 0.917342, 1.103292, 1.401170, 1.977016",\ + "0.768684, 0.972469, 1.158420, 1.456297, 2.032143",\ + "0.901499, 1.105285, 1.291235, 1.589113, 2.164959",\ + "1.242001, 1.445786, 1.631737, 1.929615, 2.505460",\ + "1.005189, 1.183989, 1.368347, 1.665754, 2.240681",\ + "1.043793, 1.222592, 1.406950, 1.704358, 2.279284",\ + "1.098920, 1.277719, 1.462078, 1.759485, 2.334412",\ + "1.231736, 1.410535, 1.594893, 1.892301, 2.467227",\ + "1.572237, 1.751037, 1.935395, 2.232802, 2.807729"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002863, 0.075861, 0.162650, 0.322437, 0.642011"); + values ( "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039239, 0.039239, 0.039239, 0.039239, 0.039239",\ + "0.089112, 0.089112, 0.089112, 0.089112, 0.089112",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2540*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[34]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.361629, 0.625108, 0.820219, 1.137042, 1.751491",\ + "0.411458, 0.674937, 0.870045, 1.186864, 1.801305",\ + "0.513330, 0.776809, 0.971917, 1.288736, 1.903178",\ + "0.751188, 1.014667, 1.209775, 1.526594, 2.141035",\ + "1.323504, 1.586983, 1.782091, 2.098909, 2.713349",\ + "0.450018, 0.712426, 0.907500, 1.224347, 1.838845",\ + "0.499848, 0.762256, 0.957326, 1.274169, 1.888658",\ + "0.601719, 0.864127, 1.059198, 1.376041, 1.990532",\ + "0.839577, 1.101985, 1.297056, 1.613899, 2.228389",\ + "1.411893, 1.674302, 1.869372, 2.186214, 2.800702",\ + "0.539154, 0.792761, 0.987527, 1.304375, 1.918876",\ + "0.588984, 0.842590, 1.037353, 1.354197, 1.968690",\ + "0.690855, 0.944462, 1.139225, 1.456070, 2.070563",\ + "0.928713, 1.182320, 1.377083, 1.693927, 2.308420",\ + "1.501029, 1.754636, 1.949399, 2.266243, 2.880734",\ + "0.602519, 0.850602, 1.045260, 1.361870, 1.976021",\ + "0.652348, 0.900431, 1.095087, 1.411692, 2.025835",\ + "0.754220, 1.002303, 1.196958, 1.513565, 2.127708",\ + "0.992078, 1.240161, 1.434817, 1.751422, 2.365565",\ + "1.564394, 1.812477, 2.007132, 2.323737, 2.937879",\ + "0.937147, 1.156000, 1.348922, 1.665098, 2.278399",\ + "0.986977, 1.205830, 1.398749, 1.714920, 2.328213",\ + "1.088848, 1.307701, 1.500621, 1.816792, 2.430086",\ + "1.326707, 1.545559, 1.738479, 2.054650, 2.667943",\ + "1.899023, 2.117875, 2.310795, 2.626965, 3.240257"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.039738, 0.039738, 0.039733, 0.039724, 0.039707",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\ + "0.039738, 0.039738, 0.039733, 0.039724, 0.039707",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\ + "0.039738, 0.039738, 0.039733, 0.039724, 0.039707",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\ + "0.039738, 0.039738, 0.039733, 0.039724, 0.039706",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137214, 2.137215",\ + "0.039738, 0.039738, 0.039733, 0.039724, 0.039706",\ + "0.147762, 0.147762, 0.147761, 0.147760, 0.147758",\ + "0.375020, 0.375020, 0.375020, 0.375022, 0.375024",\ + "0.869330, 0.869330, 0.869330, 0.869331, 0.869332",\ + "2.137214, 2.137214, 2.137214, 2.137215, 2.137215"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.394276, 0.657755, 0.852725, 1.169033, 1.782342",\ + "0.424667, 0.688146, 0.883253, 1.200070, 1.814509",\ + "0.466031, 0.729510, 0.924618, 1.241435, 1.855873",\ + "0.588069, 0.851548, 1.046656, 1.363473, 1.977913",\ + "0.919687, 1.183166, 1.378274, 1.695092, 2.309533",\ + "0.482665, 0.745074, 0.940006, 1.256338, 1.869696",\ + "0.513056, 0.775464, 0.970534, 1.287375, 1.901862",\ + "0.554420, 0.816828, 1.011898, 1.328740, 1.943227",\ + "0.676459, 0.938867, 1.133937, 1.450778, 2.065267",\ + "1.008076, 1.270484, 1.465555, 1.782397, 2.396886",\ + "0.571801, 0.825408, 1.020033, 1.336366, 1.949727",\ + "0.602192, 0.855799, 1.050561, 1.367404, 1.981894",\ + "0.643556, 0.897163, 1.091925, 1.408768, 2.023258",\ + "0.765595, 1.019201, 1.213964, 1.530807, 2.145298",\ + "1.097212, 1.350819, 1.545582, 1.862426, 2.476918",\ + "0.635166, 0.883249, 1.077766, 1.393860, 2.006869",\ + "0.665557, 0.913640, 1.108294, 1.424899, 2.039039",\ + "0.706921, 0.955004, 1.149659, 1.466263, 2.080403",\ + "0.828959, 1.077042, 1.271697, 1.588302, 2.202443",\ + "1.160577, 1.408660, 1.603315, 1.919921, 2.534063",\ + "0.969795, 1.188647, 1.381428, 1.697086, 2.309244",\ + "1.000185, 1.219038, 1.411957, 1.728126, 2.341417",\ + "1.041550, 1.260402, 1.453321, 1.769491, 2.382781",\ + "1.163588, 1.382441, 1.575360, 1.891530, 2.504821",\ + "1.495205, 1.714058, 1.906978, 2.223148, 2.836441"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.001996, 0.074995, 0.162000, 0.322004, 0.642011"); + values ( "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045860, 0.045860, 0.045861, 0.045861, 0.045862",\ + "0.091392, 0.091392, 0.091392, 0.091392, 0.091393",\ + "0.185815, 0.185815, 0.185815, 0.185815, 0.185816",\ + "0.432253, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064246, 1.064246, 1.064246, 1.064246, 1.064246"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2607*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[41]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.485123, 0.675497, 0.864625, 1.161795, 1.733234",\ + "0.533166, 0.723539, 0.912668, 1.209837, 1.781277",\ + "0.635232, 0.825605, 1.014734, 1.311903, 1.883343",\ + "0.865729, 1.056102, 1.245231, 1.542400, 2.113840",\ + "1.423621, 1.613994, 1.803123, 2.100292, 2.671732",\ + "0.573330, 0.762815, 0.951906, 1.249100, 1.820588",\ + "0.621373, 0.810857, 0.999949, 1.297143, 1.868630",\ + "0.723439, 0.912923, 1.102015, 1.399209, 1.970696",\ + "0.953936, 1.143420, 1.332512, 1.629706, 2.201193",\ + "1.511828, 1.701312, 1.890404, 2.187598, 2.759085",\ + "0.662165, 0.843147, 1.031933, 1.329129, 1.900620",\ + "0.710207, 0.891190, 1.079975, 1.377171, 1.948662",\ + "0.812273, 0.993256, 1.182042, 1.479237, 2.050728",\ + "1.042770, 1.223753, 1.412539, 1.709734, 2.281225",\ + "1.600662, 1.781645, 1.970431, 2.267626, 2.839117",\ + "0.722821, 0.900974, 1.089653, 1.386572, 1.957662",\ + "0.770863, 0.949017, 1.137696, 1.434614, 2.005704",\ + "0.872929, 1.051083, 1.239762, 1.536680, 2.107770",\ + "1.103426, 1.281580, 1.470258, 1.767177, 2.338267",\ + "1.661318, 1.839472, 2.028151, 2.325069, 2.896159",\ + "1.025458, 1.206267, 1.393313, 1.689754, 2.259915",\ + "1.073501, 1.254310, 1.441355, 1.737797, 2.307958",\ + "1.175567, 1.356376, 1.543421, 1.839863, 2.410024",\ + "1.406064, 1.586873, 1.773918, 2.070360, 2.640521",\ + "1.963956, 2.144765, 2.331810, 2.628252, 3.198413"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.470306, 0.660679, 0.849808, 1.146978, 1.718417",\ + "0.508912, 0.699286, 0.888414, 1.185584, 1.757023",\ + "0.564040, 0.754413, 0.943542, 1.240712, 1.812151",\ + "0.696855, 0.887228, 1.076357, 1.373527, 1.944966",\ + "1.037356, 1.227730, 1.416858, 1.714028, 2.285468",\ + "0.558513, 0.747998, 0.937089, 1.234283, 1.805771",\ + "0.597120, 0.786604, 0.975695, 1.272889, 1.844377",\ + "0.652247, 0.841732, 1.030823, 1.328017, 1.899504",\ + "0.785062, 0.974547, 1.163638, 1.460832, 2.032320",\ + "1.125564, 1.315048, 1.504139, 1.801333, 2.372821",\ + "0.647348, 0.828330, 1.017116, 1.314311, 1.885802",\ + "0.685954, 0.866936, 1.055722, 1.352918, 1.924409",\ + "0.741081, 0.922064, 1.110850, 1.408045, 1.979536",\ + "0.873897, 1.054879, 1.243665, 1.540860, 2.112351",\ + "1.214398, 1.395380, 1.584166, 1.881362, 2.452853",\ + "0.708003, 0.886157, 1.074836, 1.371754, 1.942844",\ + "0.746610, 0.924764, 1.113442, 1.410361, 1.981451",\ + "0.801737, 0.979891, 1.168570, 1.465488, 2.036578",\ + "0.934552, 1.112706, 1.301385, 1.598303, 2.169393",\ + "1.275054, 1.453207, 1.641886, 1.938805, 2.509895",\ + "1.010641, 1.191450, 1.378495, 1.674937, 2.245098",\ + "1.049248, 1.230056, 1.417102, 1.713544, 2.283704",\ + "1.104375, 1.285184, 1.472229, 1.768671, 2.338832",\ + "1.237190, 1.417999, 1.605044, 1.901486, 2.471647",\ + "1.577692, 1.758500, 1.945546, 2.241987, 2.812148"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002414, 0.075412, 0.162313, 0.322212, 0.642011"); + values ( "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2372*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[42]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.459771, 0.648282, 0.825192, 1.109164, 1.658848",\ + "0.507814, 0.696324, 0.873234, 1.157206, 1.706890",\ + "0.609880, 0.798391, 0.975300, 1.259272, 1.808956",\ + "0.840377, 1.028888, 1.205797, 1.489769, 2.039453",\ + "1.398269, 1.586780, 1.763690, 2.047661, 2.597345",\ + "0.548200, 0.735600, 0.912473, 1.196469, 1.746201",\ + "0.596242, 0.783643, 0.960515, 1.244511, 1.794243",\ + "0.698308, 0.885709, 1.062581, 1.346577, 1.896309",\ + "0.928805, 1.116206, 1.293078, 1.577074, 2.126806",\ + "1.486698, 1.674098, 1.850971, 2.134966, 2.684699",\ + "0.637701, 0.815933, 0.992500, 1.276497, 1.826233",\ + "0.685743, 0.863975, 1.040542, 1.324540, 1.874275",\ + "0.787809, 0.966041, 1.142608, 1.426606, 1.976341",\ + "1.018306, 1.196538, 1.373105, 1.657103, 2.206838",\ + "1.576198, 1.754430, 1.930997, 2.214995, 2.764730",\ + "0.697261, 0.873753, 1.050191, 1.333914, 1.883222",\ + "0.745304, 0.921796, 1.098233, 1.381956, 1.931265",\ + "0.847370, 1.023862, 1.200299, 1.484022, 2.033331",\ + "1.077867, 1.254359, 1.430796, 1.714519, 2.263828",\ + "1.635759, 1.812251, 1.988688, 2.272411, 2.821720",\ + "0.999714, 1.179002, 1.353846, 1.637074, 2.185413",\ + "1.047756, 1.227044, 1.401888, 1.685117, 2.233455",\ + "1.149822, 1.329110, 1.503954, 1.787183, 2.335521",\ + "1.380320, 1.559607, 1.734451, 2.017680, 2.566018",\ + "1.938212, 2.117499, 2.292344, 2.575572, 3.123910"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611",\ + "0.036124, 0.036124, 0.036124, 0.036124, 0.036124",\ + "0.147307, 0.147307, 0.147307, 0.147307, 0.147307",\ + "0.375576, 0.375576, 0.375576, 0.375576, 0.375576",\ + "0.871150, 0.871150, 0.871150, 0.871150, 0.871150",\ + "2.136611, 2.136611, 2.136611, 2.136611, 2.136611"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.444954, 0.633465, 0.810375, 1.094347, 1.644030",\ + "0.483561, 0.672071, 0.848981, 1.132953, 1.682637",\ + "0.538688, 0.727199, 0.904109, 1.188081, 1.737764",\ + "0.671503, 0.860014, 1.036924, 1.320896, 1.870579",\ + "1.012004, 1.200515, 1.377425, 1.661397, 2.211081",\ + "0.533383, 0.720783, 0.897656, 1.181652, 1.731384",\ + "0.571989, 0.759389, 0.936262, 1.220258, 1.769990",\ + "0.627117, 0.814517, 0.991390, 1.275386, 1.825118",\ + "0.759932, 0.947332, 1.124205, 1.408201, 1.957933",\ + "1.100433, 1.287833, 1.464706, 1.748702, 2.298434",\ + "0.622883, 0.801115, 0.977683, 1.261680, 1.811415",\ + "0.661490, 0.839722, 1.016289, 1.300287, 1.850022",\ + "0.716617, 0.894849, 1.071416, 1.355414, 1.905149",\ + "0.849432, 1.027664, 1.204232, 1.488229, 2.037964",\ + "1.189934, 1.368166, 1.544733, 1.828730, 2.378466",\ + "0.682444, 0.858936, 1.035374, 1.319097, 1.868405",\ + "0.721051, 0.897543, 1.073980, 1.357703, 1.907012",\ + "0.776178, 0.952670, 1.129108, 1.412831, 1.962139",\ + "0.908993, 1.085485, 1.261923, 1.545646, 2.094954",\ + "1.249495, 1.425987, 1.602424, 1.886147, 2.435456",\ + "0.984897, 1.164185, 1.339029, 1.622257, 2.170596",\ + "1.023503, 1.202791, 1.377635, 1.660863, 2.209202",\ + "1.078631, 1.257918, 1.432763, 1.715991, 2.264329",\ + "1.211446, 1.390733, 1.565578, 1.848806, 2.397144",\ + "1.551947, 1.731235, 1.906079, 2.189307, 2.737646"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002445, 0.075444, 0.162337, 0.322228, 0.642011"); + values ( "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240",\ + "0.039243, 0.039243, 0.039243, 0.039243, 0.039243",\ + "0.089116, 0.089116, 0.089116, 0.089116, 0.089116",\ + "0.185883, 0.185883, 0.185883, 0.185883, 0.185883",\ + "0.432255, 0.432255, 0.432255, 0.432255, 0.432255",\ + "1.064240, 1.064240, 1.064240, 1.064240, 1.064240"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2329*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[45]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.301772, 0.506117, 0.689126, 0.977165, 1.531523",\ + "0.351626, 0.555943, 0.738945, 1.026979, 1.581328",\ + "0.453495, 0.657815, 0.840818, 1.128852, 1.683202",\ + "0.691355, 0.895673, 1.078675, 1.366709, 1.921058",\ + "1.263674, 1.467989, 1.650990, 1.939023, 2.493371",\ + "0.390122, 0.593435, 0.776407, 1.064470, 1.618876",\ + "0.439975, 0.643261, 0.826226, 1.114284, 1.668681",\ + "0.541844, 0.745133, 0.928099, 1.216157, 1.770555",\ + "0.779704, 0.982991, 1.165956, 1.454014, 2.008411",\ + "1.352023, 1.555307, 1.738271, 2.026328, 2.580724",\ + "0.479549, 0.673766, 0.856434, 1.144499, 1.698908",\ + "0.529399, 0.723592, 0.906253, 1.194312, 1.748713",\ + "0.631269, 0.825464, 1.008125, 1.296185, 1.850587",\ + "0.869129, 1.063322, 1.245983, 1.534042, 2.088443",\ + "1.441448, 1.635638, 1.818298, 2.106356, 2.660756",\ + "0.543362, 0.731582, 0.914140, 1.201921, 1.755909",\ + "0.593211, 0.781408, 0.963959, 1.251735, 1.805714",\ + "0.695080, 0.883280, 1.065832, 1.353608, 1.907588",\ + "0.932940, 1.121138, 1.303689, 1.591465, 2.145445",\ + "1.505259, 1.693454, 1.876004, 2.163779, 2.717757",\ + "0.859181, 1.036793, 1.217797, 1.505086, 2.058114",\ + "0.909031, 1.086618, 1.267616, 1.554900, 2.107919",\ + "1.010900, 1.188490, 1.369488, 1.656773, 2.209793",\ + "1.248760, 1.426348, 1.607346, 1.894630, 2.447649",\ + "1.821079, 1.998664, 2.179661, 2.466944, 3.019962"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.039786, 0.039731, 0.039718, 0.039707, 0.039690",\ + "0.147768, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375012, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\ + "0.039784, 0.039731, 0.039718, 0.039707, 0.039690",\ + "0.147768, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375012, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\ + "0.039780, 0.039731, 0.039718, 0.039707, 0.039690",\ + "0.147767, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375013, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\ + "0.039776, 0.039731, 0.039718, 0.039707, 0.039690",\ + "0.147767, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375014, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212",\ + "0.039779, 0.039730, 0.039718, 0.039707, 0.039690",\ + "0.147767, 0.147761, 0.147759, 0.147758, 0.147756",\ + "0.375013, 0.375021, 0.375023, 0.375024, 0.375027",\ + "0.869318, 0.869319, 0.869321, 0.869323, 0.869326",\ + "2.137207, 2.137208, 2.137209, 2.137210, 2.137212"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.335876, 0.546804, 0.729804, 1.017837, 1.572184",\ + "0.364841, 0.569151, 0.752151, 1.040183, 1.594529",\ + "0.406205, 0.610515, 0.793515, 1.081547, 1.635894",\ + "0.528241, 0.732554, 0.915554, 1.203587, 1.757934",\ + "0.859855, 1.064172, 1.247173, 1.535207, 2.089556",\ + "0.424190, 0.634122, 0.817085, 1.105142, 1.659538",\ + "0.453190, 0.656469, 0.839432, 1.127488, 1.681883",\ + "0.494554, 0.697833, 0.880796, 1.168852, 1.723248",\ + "0.616590, 0.819872, 1.002835, 1.290892, 1.845288",\ + "0.948204, 1.151490, 1.334454, 1.622512, 2.176909",\ + "0.513507, 0.714453, 0.897112, 1.185170, 1.739569",\ + "0.542614, 0.736800, 0.919459, 1.207516, 1.761914",\ + "0.583978, 0.778164, 0.960823, 1.248881, 1.803279",\ + "0.706014, 0.900203, 1.082862, 1.370920, 1.925319",\ + "1.037629, 1.231821, 1.414481, 1.702540, 2.256941",\ + "0.577218, 0.772269, 0.954818, 1.242593, 1.796571",\ + "0.606425, 0.794616, 0.977165, 1.264939, 1.818916",\ + "0.647789, 0.835980, 1.018529, 1.306303, 1.860281",\ + "0.769825, 0.958019, 1.140568, 1.428343, 1.982321",\ + "1.101440, 1.289637, 1.472187, 1.759963, 2.313942",\ + "0.899896, 1.077479, 1.258475, 1.545758, 2.098775",\ + "0.922245, 1.099826, 1.280822, 1.568104, 2.121120",\ + "0.963609, 1.141190, 1.322186, 1.609468, 2.162485",\ + "1.085645, 1.263229, 1.444225, 1.731508, 2.284525",\ + "1.417260, 1.594847, 1.775844, 2.063128, 2.616147"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001159, 0.003003, 0.007781, 0.020161"); + index_3 ( "0.002729, 0.075727, 0.162549, 0.322370, 0.642011"); + values ( "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246",\ + "0.045857, 0.045861, 0.045862, 0.045862, 0.045864",\ + "0.091390, 0.091392, 0.091392, 0.091393, 0.091393",\ + "0.185814, 0.185815, 0.185815, 0.185816, 0.185816",\ + "0.432252, 0.432253, 0.432253, 0.432253, 0.432253",\ + "1.064247, 1.064246, 1.064246, 1.064246, 1.064246"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[2]_redg_min_2545*/ + +} /* end of pin tl_o[2] */ + +pin("tl_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001509 ; + + /* Other user defined attributes. */ + original_pin : tl_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.046822, 0.200204, 0.375821, 0.698828, 1.344843",\ + "0.133063, 0.287379, 0.462927, 0.785543, 1.430777",\ + "0.215932, 0.375508, 0.550883, 0.873166, 1.517732",\ + "0.273510, 0.439904, 0.614999, 0.937080, 1.581241",\ + "0.571476, 0.789768, 0.965387, 1.285824, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.022274, 0.297864, 0.631591, 1.248582, 2.482564",\ + "0.026983, 0.298841, 0.633546, 1.248582, 2.482564",\ + "0.040131, 0.301114, 0.633582, 1.248582, 2.482564",\ + "0.052012, 0.304418, 0.633682, 1.248582, 2.482564",\ + "0.127272, 0.343015, 0.639946, 1.251147, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.066617, 0.172302, 0.283906, 0.488180, 0.896728",\ + "0.154032, 0.259620, 0.371187, 0.575485, 0.984081",\ + "0.234373, 0.339957, 0.451214, 0.655513, 1.064113",\ + "0.291019, 0.397505, 0.508757, 0.712758, 1.120761",\ + "0.584343, 0.700840, 0.812391, 1.015773, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.023322, 0.186287, 0.386928, 0.759411, 1.504378",\ + "0.023322, 0.186429, 0.387433, 0.759411, 1.504378",\ + "0.024460, 0.186429, 0.387433, 0.759411, 1.504378",\ + "0.026582, 0.186429, 0.387433, 0.759411, 1.504378",\ + "0.045430, 0.190441, 0.387433, 0.759411, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.046822, 0.200204, 0.375821, 0.698828, 1.344843",\ + "0.133063, 0.287379, 0.462927, 0.785543, 1.430777",\ + "0.215932, 0.375508, 0.550883, 0.873166, 1.517732",\ + "0.273510, 0.439904, 0.614999, 0.937080, 1.581241",\ + "0.571476, 0.789768, 0.965387, 1.285824, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.022274, 0.297864, 0.631591, 1.247358, 2.473548",\ + "0.026983, 0.298841, 0.633546, 1.247358, 2.473548",\ + "0.040131, 0.301114, 0.633582, 1.247433, 2.473548",\ + "0.052012, 0.304418, 0.633682, 1.248176, 2.473548",\ + "0.127272, 0.343015, 0.639946, 1.251147, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.066617, 0.172302, 0.283906, 0.488180, 0.896728",\ + "0.154032, 0.259620, 0.371187, 0.575485, 0.984081",\ + "0.234373, 0.339957, 0.451214, 0.655513, 1.064113",\ + "0.291019, 0.397505, 0.508757, 0.712758, 1.120761",\ + "0.584343, 0.700840, 0.812391, 1.015773, 1.422537"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001509, 0.074507, 0.161634, 0.321760, 0.642011"); + values ( "0.023322, 0.185492, 0.385423, 0.757182, 1.500701",\ + "0.023322, 0.185492, 0.385423, 0.757182, 1.500701",\ + "0.024460, 0.185492, 0.385423, 0.757182, 1.500701",\ + "0.026582, 0.186104, 0.385879, 0.758083, 1.502492",\ + "0.045430, 0.190441, 0.385949, 0.758852, 1.504658"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022274, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215141, 0.169212, 0.139013, 0.127669, 0.141354",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023322, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250035, 0.174713, 0.106554, 0.083587, 0.146501",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022274, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147068, -0.104651, -0.070164, -0.030741, 0.275306",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023322, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163191, -0.097276, -0.039617, 0.002344, 0.222952",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[1]_hldr*/ + +} /* end of pin tl_o[1] */ + +pin("tl_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044859 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : tl_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[65]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.097208, 0.256769, 0.409091, 0.656426, 1.137408",\ + "0.115461, 0.284095, 0.450445, 0.715246, 1.227124",\ + "0.150308, 0.323698, 0.505958, 0.792733, 1.344666",\ + "0.555435, 0.728531, 0.927338, 1.279607, 1.977668",\ + "1.416767, 1.591727, 1.785882, 2.145544, 2.866017",\ + "0.184700, 0.344133, 0.496471, 0.743731, 1.224761",\ + "0.202953, 0.371467, 0.537861, 0.802551, 1.314477",\ + "0.237800, 0.411073, 0.593415, 0.880038, 1.432020",\ + "0.642927, 0.815906, 1.014839, 1.366912, 2.065021",\ + "1.504259, 1.679104, 1.873371, 2.232849, 2.953371",\ + "0.265280, 0.424472, 0.576498, 0.823760, 1.304793",\ + "0.283590, 0.451806, 0.617887, 0.882580, 1.394509",\ + "0.318468, 0.491412, 0.673442, 0.960067, 1.512051",\ + "0.723592, 0.896245, 1.094866, 1.446940, 2.145053",\ + "1.584936, 1.759443, 1.953398, 2.312878, 3.033402",\ + "0.322520, 0.482020, 0.634043, 0.881006, 1.361440",\ + "0.340954, 0.509354, 0.675432, 0.939825, 1.451157",\ + "0.375896, 0.548960, 0.730986, 1.017312, 1.568699",\ + "0.781016, 0.953793, 1.152410, 1.504186, 2.201700",\ + "1.642386, 1.816991, 2.010942, 2.370123, 3.090050",\ + "0.620809, 0.786662, 0.937678, 1.184021, 1.663244",\ + "0.640290, 0.814221, 0.979067, 1.242841, 1.752972",\ + "0.675782, 0.853946, 1.034621, 1.320328, 1.870529",\ + "1.080868, 1.258772, 1.456046, 1.807201, 2.503586",\ + "1.942453, 2.122015, 2.314578, 2.673139, 3.391944"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.031051, 0.064939, 0.106507, 0.168112, 0.284243",\ + "0.062823, 0.089481, 0.136238, 0.207829, 0.343471",\ + "0.126154, 0.132352, 0.184740, 0.267437, 0.424225",\ + "0.854886, 0.854886, 0.855036, 0.913502, 1.057002",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\ + "0.031051, 0.064968, 0.106612, 0.168112, 0.284243",\ + "0.062823, 0.089504, 0.136357, 0.207829, 0.343471",\ + "0.126154, 0.132357, 0.184878, 0.267437, 0.424225",\ + "0.854886, 0.854886, 0.855037, 0.913502, 1.057002",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\ + "0.031266, 0.064968, 0.106612, 0.168112, 0.284243",\ + "0.062992, 0.089504, 0.136357, 0.207829, 0.343471",\ + "0.126193, 0.132357, 0.184878, 0.267437, 0.424225",\ + "0.854886, 0.854886, 0.855037, 0.913502, 1.057002",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\ + "0.031727, 0.064968, 0.106612, 0.168112, 0.284243",\ + "0.063355, 0.089504, 0.136357, 0.207829, 0.343471",\ + "0.126277, 0.132357, 0.184878, 0.267437, 0.424225",\ + "0.854886, 0.854886, 0.855037, 0.913502, 1.057002",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422973",\ + "0.035640, 0.065810, 0.106612, 0.168112, 0.284287",\ + "0.066433, 0.090167, 0.136357, 0.207829, 0.343522",\ + "0.126993, 0.132511, 0.184878, 0.267437, 0.424284",\ + "0.854886, 0.854886, 0.855037, 0.913502, 1.057056",\ + "2.399794, 2.399794, 2.399794, 2.406500, 2.422979"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.062809, 0.283388, 0.498683, 0.866951, 1.603486",\ + "0.068905, 0.306781, 0.537627, 0.930389, 1.715913",\ + "0.080269, 0.336426, 0.586045, 1.007586, 1.850669",\ + "0.212849, 0.497229, 0.809203, 1.343143, 2.411022",\ + "0.495174, 0.777787, 1.106916, 1.706802, 2.906575",\ + "0.150255, 0.370725, 0.585933, 0.953667, 1.689420",\ + "0.156684, 0.394170, 0.624955, 1.017105, 1.801846",\ + "0.168373, 0.423879, 0.673464, 1.094302, 1.936603",\ + "0.301203, 0.584867, 0.896980, 1.429859, 2.496955",\ + "0.583505, 0.865416, 1.194902, 1.793518, 2.992509",\ + "0.236169, 0.459238, 0.673893, 1.041290, 1.776375",\ + "0.243498, 0.482807, 0.712916, 1.104728, 1.888801",\ + "0.256066, 0.512668, 0.761427, 1.181925, 2.023558",\ + "0.389574, 0.674096, 0.984949, 1.517482, 2.583910",\ + "0.671814, 0.954623, 1.282876, 1.881141, 3.079464",\ + "0.296494, 0.524194, 0.738017, 1.105204, 1.839884",\ + "0.304623, 0.547943, 0.777044, 1.168642, 1.952310",\ + "0.317970, 0.578026, 0.825559, 1.245839, 2.087067",\ + "0.452080, 0.740091, 1.049099, 1.581396, 2.647419",\ + "0.734265, 1.020587, 1.347036, 1.945055, 3.142973",\ + "0.612030, 0.880553, 1.088866, 1.454138, 2.185340",\ + "0.625211, 0.906402, 1.128142, 1.517678, 2.297766",\ + "0.643489, 0.939075, 1.176949, 1.594995, 2.432523",\ + "0.781402, 1.108582, 1.401631, 1.931020, 2.992876",\ + "1.063240, 1.388711, 1.700238, 2.294955, 3.488429"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.011160, 0.064436, 0.116932, 0.202254, 0.372899",\ + "0.020800, 0.078264, 0.137685, 0.234686, 0.428687",\ + "0.041454, 0.098634, 0.166400, 0.277542, 0.499826",\ + "0.284826, 0.291930, 0.346150, 0.498019, 0.801757",\ + "0.801745, 0.802553, 0.834131, 0.941202, 1.155343",\ + "0.012155, 0.064608, 0.117203, 0.202254, 0.372899",\ + "0.021847, 0.078458, 0.137993, 0.234686, 0.428687",\ + "0.042416, 0.098854, 0.166753, 0.277542, 0.499826",\ + "0.284826, 0.291998, 0.346632, 0.498019, 0.801757",\ + "0.801745, 0.802560, 0.834471, 0.941202, 1.155343",\ + "0.014841, 0.065015, 0.117208, 0.202254, 0.372899",\ + "0.024678, 0.078917, 0.137999, 0.234686, 0.428687",\ + "0.045017, 0.099375, 0.166760, 0.277542, 0.499826",\ + "0.284826, 0.292159, 0.346641, 0.498019, 0.801757",\ + "0.801745, 0.802579, 0.834477, 0.941202, 1.155343",\ + "0.017226, 0.065607, 0.117221, 0.202254, 0.372899",\ + "0.027191, 0.079585, 0.138014, 0.234686, 0.428687",\ + "0.047325, 0.100134, 0.166777, 0.277542, 0.499826",\ + "0.284826, 0.292394, 0.346665, 0.498019, 0.801757",\ + "0.801745, 0.802605, 0.834494, 0.941202, 1.155343",\ + "0.032302, 0.072514, 0.118088, 0.202610, 0.372899",\ + "0.043078, 0.087374, 0.139000, 0.235090, 0.428687",\ + "0.061921, 0.108981, 0.167906, 0.278005, 0.499826",\ + "0.284826, 0.295133, 0.348208, 0.498652, 0.801757",\ + "0.801745, 0.802917, 0.835582, 0.941648, 1.155343"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "tl_o[65]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.091649, 0.250131, 0.402296, 0.649078, 1.128418",\ + "0.104662, 0.273549, 0.438178, 0.701696, 1.211503",\ + "0.129595, 0.307072, 0.486657, 0.770890, 1.318582",\ + "0.419859, 0.596841, 0.797852, 1.150232, 1.846445",\ + "1.036012, 1.213814, 1.416984, 1.786820, 2.524206",\ + "0.179141, 0.337450, 0.489577, 0.736383, 1.215771",\ + "0.192154, 0.360868, 0.525459, 0.789001, 1.298857",\ + "0.217087, 0.394391, 0.573938, 0.858195, 1.405936",\ + "0.507351, 0.684160, 0.885133, 1.237537, 1.933798",\ + "1.123504, 1.301133, 1.504265, 1.874125, 2.611559",\ + "0.259715, 0.417789, 0.569604, 0.816412, 1.295803",\ + "0.272795, 0.441207, 0.605486, 0.869029, 1.378888",\ + "0.297783, 0.474730, 0.653965, 0.938223, 1.485967",\ + "0.588044, 0.764499, 0.965159, 1.317566, 2.013830",\ + "1.204202, 1.381472, 1.584292, 1.954154, 2.691591",\ + "0.316944, 0.475532, 0.627237, 0.873742, 1.352620",\ + "0.330166, 0.498989, 0.663147, 0.926397, 1.435779",\ + "0.355271, 0.532545, 0.711661, 0.995637, 1.542949",\ + "0.645525, 0.822313, 1.022907, 1.375159, 2.071169",\ + "1.261694, 1.439288, 1.642045, 2.011797, 2.749029",\ + "0.615137, 0.780253, 0.930886, 1.176831, 1.654602",\ + "0.629566, 0.803991, 0.966800, 1.229517, 1.737849",\ + "0.655668, 0.837777, 1.015319, 1.298796, 1.845130",\ + "0.945865, 1.127532, 1.326573, 1.678471, 2.373782",\ + "1.562129, 1.744529, 1.945711, 2.315152, 3.051762"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.022568, 0.058250, 0.097501, 0.158155, 0.273924",\ + "0.045222, 0.077904, 0.123497, 0.193808, 0.327390",\ + "0.090348, 0.107489, 0.163971, 0.245678, 0.396404",\ + "0.621445, 0.621445, 0.621445, 0.691541, 0.864683",\ + "1.751287, 1.751287, 1.752785, 1.770247, 1.811996",\ + "0.022568, 0.058250, 0.097501, 0.158155, 0.273924",\ + "0.045222, 0.077904, 0.123497, 0.193808, 0.327390",\ + "0.090348, 0.107489, 0.163971, 0.245678, 0.396404",\ + "0.621445, 0.621445, 0.621445, 0.691541, 0.864683",\ + "1.751287, 1.751287, 1.752785, 1.770247, 1.811996",\ + "0.022795, 0.058250, 0.097501, 0.158155, 0.273924",\ + "0.045430, 0.077904, 0.123497, 0.193808, 0.327390",\ + "0.090457, 0.107489, 0.163971, 0.245678, 0.396404",\ + "0.621445, 0.621445, 0.621445, 0.691541, 0.864683",\ + "1.751287, 1.751287, 1.752785, 1.770247, 1.811996",\ + "0.023283, 0.058385, 0.097589, 0.158295, 0.274203",\ + "0.045877, 0.078027, 0.123601, 0.193969, 0.327712",\ + "0.090692, 0.107553, 0.164104, 0.245861, 0.396767",\ + "0.621445, 0.621445, 0.621445, 0.691750, 0.865100",\ + "1.751287, 1.751287, 1.752788, 1.770297, 1.812096",\ + "0.027423, 0.059345, 0.097603, 0.158415, 0.274540",\ + "0.049669, 0.078907, 0.123617, 0.194107, 0.328101",\ + "0.092680, 0.108015, 0.164124, 0.246016, 0.397205",\ + "0.621445, 0.621445, 0.621445, 0.691929, 0.865604",\ + "1.751287, 1.751287, 1.752789, 1.770340, 1.812218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.062799, 0.282922, 0.497986, 0.866154, 1.602100",\ + "0.068878, 0.306290, 0.537336, 0.930038, 1.714836",\ + "0.080236, 0.335964, 0.585498, 1.006969, 1.849055",\ + "0.212818, 0.496736, 0.807979, 1.341514, 2.406755",\ + "0.493894, 0.777156, 1.106499, 1.705590, 2.901373",\ + "0.150236, 0.370257, 0.585236, 0.952870, 1.688034",\ + "0.156640, 0.393680, 0.624665, 1.016754, 1.800770",\ + "0.168330, 0.423416, 0.672918, 1.093685, 1.934989",\ + "0.301173, 0.584370, 0.895755, 1.428230, 2.492689",\ + "0.582238, 0.864786, 1.194485, 1.792306, 2.987307",\ + "0.236126, 0.458767, 0.673196, 1.040499, 1.774989",\ + "0.243411, 0.482319, 0.712626, 1.104385, 1.887725",\ + "0.255996, 0.512204, 0.760881, 1.181320, 2.021944",\ + "0.389544, 0.673587, 0.983724, 1.515878, 2.579644",\ + "0.670583, 0.953997, 1.282458, 1.879963, 3.074262",\ + "0.296431, 0.523718, 0.737319, 1.104467, 1.838498",\ + "0.304497, 0.547459, 0.776753, 1.168383, 1.951234",\ + "0.317876, 0.577559, 0.825013, 1.245352, 2.085453",\ + "0.452050, 0.739568, 1.047875, 1.580045, 2.643153",\ + "0.733066, 1.019967, 1.346619, 1.944209, 3.137771",\ + "0.611833, 0.880022, 1.088168, 1.453430, 2.183954",\ + "0.624839, 0.905962, 1.127852, 1.517465, 2.296690",\ + "0.643244, 0.938579, 1.176404, 1.594573, 2.430909",\ + "0.781372, 1.107880, 1.400406, 1.929807, 2.988609",\ + "1.062240, 1.388161, 1.699817, 2.294288, 3.483227"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000590, 0.001754, 0.015524, 0.044859"); + index_3 ( "0.000991, 0.073990, 0.161246, 0.321501, 0.642011"); + values ( "0.011131, 0.063936, 0.115966, 0.201201, 0.370930",\ + "0.020777, 0.078242, 0.137616, 0.234279, 0.426765",\ + "0.041132, 0.097162, 0.164744, 0.275022, 0.494619",\ + "0.282873, 0.290343, 0.344847, 0.495374, 0.795117",\ + "0.794988, 0.797692, 0.832143, 0.938552, 1.150445",\ + "0.012121, 0.064104, 0.116237, 0.201201, 0.370930",\ + "0.021825, 0.078435, 0.137924, 0.234279, 0.426765",\ + "0.042062, 0.097382, 0.165095, 0.275022, 0.494619",\ + "0.282873, 0.290415, 0.345327, 0.495374, 0.795117",\ + "0.794988, 0.797718, 0.832482, 0.938552, 1.150445",\ + "0.014795, 0.064505, 0.116242, 0.201211, 0.370930",\ + "0.024656, 0.078894, 0.137930, 0.234291, 0.426765",\ + "0.044575, 0.097903, 0.165102, 0.275036, 0.494619",\ + "0.282873, 0.290585, 0.345336, 0.495392, 0.795117",\ + "0.794988, 0.797779, 0.832488, 0.938565, 1.150445",\ + "0.017168, 0.065086, 0.116256, 0.201314, 0.370930",\ + "0.027169, 0.079562, 0.137945, 0.234407, 0.426765",\ + "0.046806, 0.098662, 0.165119, 0.275169, 0.494619",\ + "0.282873, 0.290832, 0.345360, 0.495573, 0.795117",\ + "0.794988, 0.797869, 0.832505, 0.938693, 1.150445",\ + "0.032175, 0.071874, 0.117123, 0.201725, 0.370930",\ + "0.043057, 0.087350, 0.138929, 0.234874, 0.426765",\ + "0.060912, 0.107509, 0.166242, 0.275701, 0.494619",\ + "0.282873, 0.293712, 0.346892, 0.496300, 0.795117",\ + "0.794988, 0.798911, 0.833588, 0.939207, 1.150445"); + } + + } /* end of arc clk_ast_tlul_i_tl_o[0]_redg_min*/ + +} /* end of pin tl_o[0] */ +} /* end of bus tl_o */ + +pin("ast_init_done_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000556 ; + + /* Other user defined attributes. */ + original_pin : ast_init_done_o; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.043384, 0.198284, 0.374379, 0.697867, 1.344843",\ + "0.129257, 0.285459, 0.461486, 0.784583, 1.430777",\ + "0.210733, 0.373589, 0.549444, 0.872207, 1.517732",\ + "0.267175, 0.437989, 0.613561, 0.936121, 1.581241",\ + "0.558327, 0.787842, 0.963956, 1.284870, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.018706, 0.294221, 0.628837, 1.246746, 2.482563",\ + "0.023795, 0.295177, 0.630806, 1.246746, 2.482563",\ + "0.037168, 0.297482, 0.630842, 1.246746, 2.482563",\ + "0.048861, 0.300835, 0.630939, 1.246746, 2.482563",\ + "0.122687, 0.339900, 0.637218, 1.249328, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.063197, 0.171101, 0.283015, 0.487593, 0.896749",\ + "0.150760, 0.258420, 0.370296, 0.574898, 0.984103",\ + "0.230918, 0.338761, 0.450323, 0.654927, 1.064134",\ + "0.287331, 0.396309, 0.507868, 0.712173, 1.120782",\ + "0.578538, 0.699638, 0.811505, 1.015189, 1.422559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.020743, 0.184138, 0.385305, 0.758342, 1.504417",\ + "0.020743, 0.184274, 0.385812, 0.758342, 1.504417",\ + "0.021682, 0.184274, 0.385812, 0.758342, 1.504417",\ + "0.023987, 0.184274, 0.385812, 0.758342, 1.504417",\ + "0.042807, 0.188367, 0.385812, 0.758342, 1.504697"); + } + + } /* end of arc clk_ast_tlul_i_ast_init_done_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.043384, 0.198284, 0.374379, 0.697867, 1.344843",\ + "0.129257, 0.285459, 0.461486, 0.784583, 1.430777",\ + "0.210733, 0.373589, 0.549444, 0.872207, 1.517732",\ + "0.267175, 0.437989, 0.613561, 0.936121, 1.581241",\ + "0.558327, 0.787842, 0.963956, 1.284870, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.018706, 0.294221, 0.628837, 1.245531, 2.473548",\ + "0.023795, 0.295177, 0.630806, 1.245531, 2.473548",\ + "0.037168, 0.297482, 0.630842, 1.245606, 2.473548",\ + "0.048861, 0.300835, 0.630939, 1.246347, 2.473548",\ + "0.122687, 0.339900, 0.637218, 1.249328, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.063197, 0.171101, 0.283015, 0.487593, 0.896749",\ + "0.150760, 0.258420, 0.370296, 0.574898, 0.984103",\ + "0.230918, 0.338761, 0.450323, 0.654927, 1.064134",\ + "0.287331, 0.396309, 0.507868, 0.712173, 1.120782",\ + "0.578538, 0.699638, 0.811505, 1.015189, 1.422559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000556, 0.073554, 0.160919, 0.321283, 0.642011"); + values ( "0.020743, 0.183352, 0.383802, 0.756115, 1.500740",\ + "0.020743, 0.183352, 0.383802, 0.756115, 1.500740",\ + "0.021682, 0.183352, 0.383802, 0.756115, 1.500740",\ + "0.023987, 0.183968, 0.384256, 0.757015, 1.502532",\ + "0.042807, 0.188367, 0.384324, 0.757782, 1.504697"); + } + + } /* end of arc clk_ast_tlul_i_ast_init_done_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018706, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.166278, 0.120559, 0.090376, 0.079044, 0.092801",\ + "0.171862, 0.126143, 0.095959, 0.084628, 0.098385",\ + "0.245234, 0.199449, 0.169261, 0.157926, 0.171660",\ + "0.322551, 0.276573, 0.246370, 0.235023, 0.248691",\ + "0.666536, 0.618843, 0.588507, 0.577057, 0.590140"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020743, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.195653, 0.120302, 0.052066, 0.028959, 0.090570",\ + "0.201000, 0.125650, 0.057413, 0.034307, 0.095918",\ + "0.271909, 0.196575, 0.128353, 0.105282, 0.167257",\ + "0.351861, 0.276541, 0.208391, 0.185439, 0.248491",\ + "0.700887, 0.625677, 0.558111, 0.536111, 0.607801"); + } + + } /* end of arc clk_ast_tlul_i_ast_init_done_o_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018706, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.098385, -0.055930, -0.021532, 0.019602, 0.346880",\ + "-0.103969, -0.061514, -0.027115, 0.014019, 0.341296",\ + "-0.177290, -0.134846, -0.100420, -0.059816, 0.260884",\ + "-0.254454, -0.212046, -0.177538, -0.138520, 0.162505",\ + "-0.597087, -0.554990, -0.519760, -0.494735, -0.367407"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020743, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.108800, -0.043157, 0.014117, 0.055975, 0.277251",\ + "-0.114148, -0.048505, 0.008770, 0.050627, 0.271903",\ + "-0.185082, -0.119364, -0.061987, -0.020103, 0.200995",\ + "-0.265110, -0.199164, -0.141461, -0.099488, 0.121043",\ + "-0.614747, -0.546974, -0.486651, -0.443970, -0.227977"); + } + + } /* end of arc clk_ast_tlul_i_ast_init_done_o_hldr*/ + +} /* end of pin ast_init_done_o */ + +pin("clk_ast_adc_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.009042 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_adc_i; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.151080"); + } + + } /* end of arc clk_ast_adc_i_clk_ast_adc_i_pwl*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.077628"); + } + + } /* end of arc clk_ast_adc_i_clk_ast_adc_i_pwh*/ + +} /* end of pin clk_ast_adc_i */ + +pin("rst_ast_adc_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.009042 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_adc_ni; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.274432, 0.227738, 0.193623, 0.189926, 0.219386",\ + "0.355422, 0.308727, 0.274612, 0.270915, 0.300375",\ + "0.429898, 0.383203, 0.349088, 0.345391, 0.374851",\ + "0.553172, 0.506477, 0.472362, 0.468665, 0.498125",\ + "0.739732, 0.693038, 0.658922, 0.655226, 0.684685"); + } + + } /* end of arc clk_ast_adc_i_rst_ast_adc_ni_recrr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.027752, 0.053659, 0.141339, 0.280082, 0.570819",\ + "-0.108741, -0.027330, 0.060350, 0.199093, 0.489830",\ + "-0.183217, -0.101806, -0.014126, 0.124617, 0.415354",\ + "-0.306491, -0.225081, -0.137400, 0.001342, 0.292080",\ + "-0.493052, -0.411641, -0.323961, -0.185218, 0.105519"); + } + + } /* end of arc clk_ast_adc_i_rst_ast_adc_ni_remrr*/ + +} /* end of pin rst_ast_adc_ni */ + +pin("clk_ast_alert_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.111907 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_alert_i; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.131491"); + } + + } /* end of arc clk_ast_alert_i_clk_ast_alert_i_pwl*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_alert_i_clk_ast_alert_i_pwh*/ + +} /* end of pin clk_ast_alert_i */ + +pin("rst_ast_alert_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.063611 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_alert_ni; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.113563, 0.076989, 0.018933, 0.022110, 0.146261",\ + "0.193721, 0.155461, 0.100982, 0.103788, 0.220372",\ + "0.282614, 0.243810, 0.191411, 0.194005, 0.308054",\ + "0.566671, 0.464344, 0.331922, 0.334358, 0.433019",\ + "1.363218, 1.178999, 0.828491, 0.816184, 0.684690"); + } + + } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_recrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.092068, 0.057718, -0.003401, -0.002983, 0.002097",\ + "0.189535, 0.154850, 0.093649, 0.094132, 0.100007",\ + "0.301664, 0.264351, 0.202415, 0.202944, 0.209366",\ + "0.503950, 0.455349, 0.390148, 0.390390, 0.393333",\ + "0.857313, 0.785929, 0.714140, 0.713804, 0.709723"); + } + + } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_recfr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.123357, 0.181341, 0.319709, 0.347503, 0.685278",\ + "0.102353, 0.159959, 0.295858, 0.323234, 0.655939",\ + "0.092806, 0.153066, 0.290747, 0.317698, 0.645224",\ + "0.064479, 0.123792, 0.266686, 0.294183, 0.628352",\ + "-0.004662, 0.048858, 0.204447, 0.233992, 0.593057"); + } + + } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_remrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.074257, 0.131115, 0.268439, 0.296209, 0.633696",\ + "-0.014192, 0.042690, 0.179264, 0.206921, 0.543039",\ + "-0.102387, -0.045223, 0.090380, 0.117827, 0.451393",\ + "-0.249899, -0.191425, -0.054943, -0.027706, 0.303305",\ + "-0.492713, -0.431597, -0.293340, -0.266527, 0.059328"); + } + + } /* end of arc clk_ast_alert_i_rst_ast_alert_ni_remfr*/ + +} /* end of pin rst_ast_alert_ni */ + +pin("clk_ast_es_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.142021 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_es_i; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.131491"); + } + + } /* end of arc clk_ast_es_i_clk_ast_es_i_pwl*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_es_i_clk_ast_es_i_pwh*/ + +} /* end of pin clk_ast_es_i */ + +pin("rst_ast_es_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.184622 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_es_ni; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.210479, 0.169372, 0.114546, 0.118621, 0.168150",\ + "0.293165, 0.250654, 0.192180, 0.195438, 0.235030",\ + "0.391384, 0.349291, 0.288209, 0.290833, 0.322724",\ + "0.566327, 0.524466, 0.460601, 0.462751, 0.488884",\ + "0.947368, 0.905673, 0.836972, 0.838520, 0.857344"); + } + + } /* end of arc clk_ast_es_i_rst_ast_es_ni_recrr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.051490, -0.010118, 0.054432, 0.065559, 0.200781",\ + "-0.130202, -0.094826, -0.027856, -0.016996, 0.114987",\ + "-0.215839, -0.180431, -0.119977, -0.109196, 0.021823",\ + "-0.347231, -0.311623, -0.255002, -0.244742, -0.120048",\ + "-0.619519, -0.583379, -0.529999, -0.521121, -0.413232"); + } + + } /* end of arc clk_ast_es_i_rst_ast_es_ni_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.330641, 0.279192, 0.245179, 0.243672, 0.279220",\ + "0.409639, 0.358190, 0.324177, 0.322670, 0.358218",\ + "0.487644, 0.436183, 0.402110, 0.400492, 0.435798",\ + "0.623048, 0.571541, 0.537264, 0.535269, 0.569741",\ + "0.842293, 0.790722, 0.756013, 0.753223, 0.785948"); + } + + } /* end of arc clk_ast_ext_i_rst_ast_es_ni_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.138360, -0.088735, -0.049180, 0.004893, 0.111904",\ + "-0.218903, -0.169277, -0.129723, -0.075649, 0.031362",\ + "-0.301318, -0.252007, -0.212321, -0.158231, -0.051325",\ + "-0.443423, -0.394857, -0.354861, -0.300729, -0.194073",\ + "-0.673239, -0.626523, -0.585755, -0.531523, -0.425485"); + } + + } /* end of arc clk_ast_ext_i_rst_ast_es_ni_remrr*/ + +} /* end of pin rst_ast_es_ni */ + +pin("clk_ast_rng_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.016298 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_rng_i; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.131491"); + } + + } /* end of arc clk_ast_rng_i_clk_ast_rng_i_pwl*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_rng_i_clk_ast_rng_i_pwh*/ + +} /* end of pin clk_ast_rng_i */ + +pin("rst_ast_rng_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.019282 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_rng_ni; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.397809, 0.355150, 0.299205, 0.303092, 0.350337",\ + "0.476858, 0.434199, 0.378254, 0.382142, 0.429386",\ + "0.555484, 0.512828, 0.456739, 0.460590, 0.507394",\ + "0.694132, 0.651484, 0.595040, 0.598802, 0.644521",\ + "0.924501, 0.881869, 0.824615, 0.828174, 0.871421"); + } + + } /* end of arc clk_ast_rng_i_rst_ast_rng_ni_recrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.051490, -0.010118, 0.054432, 0.065559, 0.200781",\ + "-0.130202, -0.094826, -0.027856, -0.016996, 0.114987",\ + "-0.215839, -0.180431, -0.119977, -0.109196, 0.021823",\ + "-0.347231, -0.311623, -0.255002, -0.244742, -0.120048",\ + "-0.619519, -0.580113, -0.514458, -0.503429, -0.369398"); + } + + } /* end of arc clk_ast_rng_i_rst_ast_rng_ni_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.210479, 0.160879, 0.128086, 0.118621, 0.168150",\ + "0.293165, 0.241596, 0.206622, 0.195438, 0.235030",\ + "0.391384, 0.339830, 0.303295, 0.290833, 0.322724",\ + "0.566327, 0.514573, 0.476374, 0.462751, 0.488884",\ + "0.947368, 0.895031, 0.853939, 0.838520, 0.857344"); + } + + } /* end of arc clk_ast_tlul_i_rst_ast_rng_ni_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.124168, -0.077180, -0.040446, -0.015137, 0.108101",\ + "-0.205037, -0.158304, -0.123014, -0.098281, 0.025219",\ + "-0.301967, -0.254997, -0.221149, -0.197116, -0.074898",\ + "-0.470369, -0.422280, -0.389838, -0.366778, -0.249319",\ + "-0.834370, -0.783388, -0.753247, -0.732123, -0.626660"); + } + + } /* end of arc clk_ast_tlul_i_rst_ast_rng_ni_remrr*/ + +} /* end of pin rst_ast_rng_ni */ + +pin("clk_ast_tlul_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.070969 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_tlul_i; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.149001"); + } + + } /* end of arc clk_ast_tlul_i_clk_ast_tlul_i_pwl*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_tlul_i_clk_ast_tlul_i_pwh*/ + +} /* end of pin clk_ast_tlul_i */ + +pin("rst_ast_tlul_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 2.103311 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_tlul_ni; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.716936, 0.665384, 0.628579, 0.622004, 0.646451",\ + "0.794990, 0.743439, 0.706634, 0.700058, 0.724506",\ + "0.863378, 0.811826, 0.775021, 0.768446, 0.792893",\ + "0.983598, 0.932046, 0.895241, 0.888666, 0.913113",\ + "1.184568, 1.133018, 1.096165, 1.089503, 1.113762"); + } + + } /* end of arc clk_ast_ext_i_rst_ast_tlul_ni_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.208883, -0.162400, -0.121535, -0.067290, 0.038670",\ + "-0.289818, -0.243335, -0.202470, -0.148225, -0.042265",\ + "-0.371428, -0.325048, -0.284140, -0.229890, -0.123964",\ + "-0.514608, -0.468588, -0.427530, -0.373260, -0.267455",\ + "-0.754762, -0.708893, -0.668362, -0.614349, -0.508655"); + } + + } /* end of arc clk_ast_ext_i_rst_ast_tlul_ni_remrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.210479, 0.169372, 0.114546, 0.118621, 0.168150",\ + "0.293165, 0.250654, 0.192180, 0.195438, 0.235030",\ + "0.391384, 0.349291, 0.288209, 0.290833, 0.322724",\ + "0.566327, 0.524466, 0.460601, 0.462751, 0.488884",\ + "0.947368, 0.905673, 0.836972, 0.838520, 0.857344"); + } + + } /* end of arc clk_ast_rng_i_rst_ast_tlul_ni_recrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.124168, -0.086693, -0.025277, -0.015137, 0.108101",\ + "-0.205037, -0.167443, -0.108443, -0.098281, 0.025219",\ + "-0.301967, -0.263763, -0.207172, -0.197116, -0.074898",\ + "-0.470369, -0.430682, -0.376443, -0.366778, -0.249319",\ + "-0.834370, -0.791194, -0.740802, -0.732123, -0.626660"); + } + + } /* end of arc clk_ast_rng_i_rst_ast_tlul_ni_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "1.869923, 1.822277, 1.788958, 1.777550, 1.806108",\ + "1.951337, 1.903690, 1.870372, 1.858964, 1.887521",\ + "2.032032, 1.984385, 1.951067, 1.939659, 1.968216",\ + "2.170088, 2.122442, 2.089123, 2.077716, 2.106273",\ + "2.387489, 2.339843, 2.306524, 2.295116, 2.323674"); + } + + } /* end of arc clk_ast_tlul_i_rst_ast_tlul_ni_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.059314, 0.134642, 0.207217, 0.259023, 0.524416",\ + "-0.004435, 0.071727, 0.144173, 0.196109, 0.463735",\ + "-0.061661, 0.013696, 0.087717, 0.140099, 0.405234",\ + "-0.144853, -0.069971, 0.004287, 0.056772, 0.321975",\ + "-0.313738, -0.239256, -0.166173, -0.113918, 0.154394"); + } + + } /* end of arc clk_ast_tlul_i_rst_ast_tlul_ni_remrr*/ + +} /* end of pin rst_ast_tlul_ni */ + +pin("clk_ast_usb_i") { + direction : input ; + clock : true ; + max_transition : 2.480000 ; + capacitance : 0.008679 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_usb_i; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.131491"); + } + + } /* end of arc clk_ast_usb_i_clk_ast_usb_i_pwl*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.073311"); + } + + } /* end of arc clk_ast_usb_i_clk_ast_usb_i_pwh*/ + +} /* end of pin clk_ast_usb_i */ + +pin("rst_ast_usb_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.013220 ; + + /* Other user defined attributes. */ + original_pin : rst_ast_usb_ni; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.400327, 0.357670, 0.301625, 0.305488, 0.352426",\ + "0.476049, 0.433392, 0.377347, 0.381210, 0.428148",\ + "0.548090, 0.505436, 0.449256, 0.453084, 0.499610",\ + "0.675976, 0.633329, 0.576799, 0.580539, 0.625997",\ + "0.887381, 0.844752, 0.787402, 0.790936, 0.833890"); + } + + } /* end of arc clk_ast_usb_i_rst_ast_usb_ni_recrr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.128239, -0.088359, -0.022542, -0.011521, 0.122413",\ + "-0.208722, -0.168842, -0.103025, -0.092004, 0.041930",\ + "-0.287884, -0.248004, -0.182187, -0.171166, -0.037232",\ + "-0.421984, -0.382104, -0.316287, -0.305266, -0.171332",\ + "-0.631259, -0.591379, -0.525562, -0.514541, -0.380607"); + } + + } /* end of arc clk_ast_usb_i_rst_ast_usb_ni_remrr*/ + +} /* end of pin rst_ast_usb_ni */ + +pin("clk_ast_ext_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.005952 ; + + /* Other user defined attributes. */ + original_pin : clk_ast_ext_i; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : min_pulse_width ; + fall_constraint( scalar ){ + values ( "0.300783"); + } + + } /* end of arc clk_ast_ext_i_clk_ast_ext_i_pwl*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : min_pulse_width ; + rise_constraint( scalar ){ + values ( "0.123380"); + } + + } /* end of arc clk_ast_ext_i_clk_ast_ext_i_pwh*/ + +} /* end of pin clk_ast_ext_i */ + +pin("por_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000461 ; + + /* Other user defined attributes. */ + original_pin : por_ni; +} /* end of pin por_ni */ +bus ( sns_clks_i ) { + + bus_type : BUS27_type2 ; + direction : input ; + +pin("sns_clks_i[26]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[26]; +} /* end of pin sns_clks_i[26] */ + +pin("sns_clks_i[25]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[25]; +} /* end of pin sns_clks_i[25] */ + +pin("sns_clks_i[24]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[24]; +} /* end of pin sns_clks_i[24] */ + +pin("sns_clks_i[23]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[23]; +} /* end of pin sns_clks_i[23] */ + +pin("sns_clks_i[22]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[22]; +} /* end of pin sns_clks_i[22] */ + +pin("sns_clks_i[21]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[21]; +} /* end of pin sns_clks_i[21] */ + +pin("sns_clks_i[20]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[20]; +} /* end of pin sns_clks_i[20] */ + +pin("sns_clks_i[19]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[19]; +} /* end of pin sns_clks_i[19] */ + +pin("sns_clks_i[18]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[18]; +} /* end of pin sns_clks_i[18] */ + +pin("sns_clks_i[17]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[17]; +} /* end of pin sns_clks_i[17] */ + +pin("sns_clks_i[16]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[16]; +} /* end of pin sns_clks_i[16] */ + +pin("sns_clks_i[15]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[15]; +} /* end of pin sns_clks_i[15] */ + +pin("sns_clks_i[14]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[14]; +} /* end of pin sns_clks_i[14] */ + +pin("sns_clks_i[13]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[13]; +} /* end of pin sns_clks_i[13] */ + +pin("sns_clks_i[12]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[12]; +} /* end of pin sns_clks_i[12] */ + +pin("sns_clks_i[11]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[11]; +} /* end of pin sns_clks_i[11] */ + +pin("sns_clks_i[10]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[10]; +} /* end of pin sns_clks_i[10] */ + +pin("sns_clks_i[9]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[9]; +} /* end of pin sns_clks_i[9] */ + +pin("sns_clks_i[8]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[8]; +} /* end of pin sns_clks_i[8] */ + +pin("sns_clks_i[7]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[7]; +} /* end of pin sns_clks_i[7] */ + +pin("sns_clks_i[6]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[6]; +} /* end of pin sns_clks_i[6] */ + +pin("sns_clks_i[5]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[5]; +} /* end of pin sns_clks_i[5] */ + +pin("sns_clks_i[4]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[4]; +} /* end of pin sns_clks_i[4] */ + +pin("sns_clks_i[3]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[3]; +} /* end of pin sns_clks_i[3] */ + +pin("sns_clks_i[2]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[2]; +} /* end of pin sns_clks_i[2] */ + +pin("sns_clks_i[1]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[1]; +} /* end of pin sns_clks_i[1] */ + +pin("sns_clks_i[0]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_clks_i[0]; +} /* end of pin sns_clks_i[0] */ +} /* end of bus sns_clks_i */ +bus ( sns_rsts_i ) { + + bus_type : BUS56_type3 ; + direction : input ; + +pin("sns_rsts_i[55]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[55]; +} /* end of pin sns_rsts_i[55] */ + +pin("sns_rsts_i[54]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[54]; +} /* end of pin sns_rsts_i[54] */ + +pin("sns_rsts_i[53]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[53]; +} /* end of pin sns_rsts_i[53] */ + +pin("sns_rsts_i[52]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[52]; +} /* end of pin sns_rsts_i[52] */ + +pin("sns_rsts_i[51]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[51]; +} /* end of pin sns_rsts_i[51] */ + +pin("sns_rsts_i[50]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[50]; +} /* end of pin sns_rsts_i[50] */ + +pin("sns_rsts_i[49]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[49]; +} /* end of pin sns_rsts_i[49] */ + +pin("sns_rsts_i[48]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[48]; +} /* end of pin sns_rsts_i[48] */ + +pin("sns_rsts_i[47]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[47]; +} /* end of pin sns_rsts_i[47] */ + +pin("sns_rsts_i[46]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[46]; +} /* end of pin sns_rsts_i[46] */ + +pin("sns_rsts_i[45]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[45]; +} /* end of pin sns_rsts_i[45] */ + +pin("sns_rsts_i[44]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[44]; +} /* end of pin sns_rsts_i[44] */ + +pin("sns_rsts_i[43]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[43]; +} /* end of pin sns_rsts_i[43] */ + +pin("sns_rsts_i[42]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[42]; +} /* end of pin sns_rsts_i[42] */ + +pin("sns_rsts_i[41]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[41]; +} /* end of pin sns_rsts_i[41] */ + +pin("sns_rsts_i[40]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[40]; +} /* end of pin sns_rsts_i[40] */ + +pin("sns_rsts_i[39]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[39]; +} /* end of pin sns_rsts_i[39] */ + +pin("sns_rsts_i[38]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[38]; +} /* end of pin sns_rsts_i[38] */ + +pin("sns_rsts_i[37]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[37]; +} /* end of pin sns_rsts_i[37] */ + +pin("sns_rsts_i[36]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[36]; +} /* end of pin sns_rsts_i[36] */ + +pin("sns_rsts_i[35]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[35]; +} /* end of pin sns_rsts_i[35] */ + +pin("sns_rsts_i[34]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[34]; +} /* end of pin sns_rsts_i[34] */ + +pin("sns_rsts_i[33]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[33]; +} /* end of pin sns_rsts_i[33] */ + +pin("sns_rsts_i[32]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[32]; +} /* end of pin sns_rsts_i[32] */ + +pin("sns_rsts_i[31]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[31]; +} /* end of pin sns_rsts_i[31] */ + +pin("sns_rsts_i[30]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[30]; +} /* end of pin sns_rsts_i[30] */ + +pin("sns_rsts_i[29]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[29]; +} /* end of pin sns_rsts_i[29] */ + +pin("sns_rsts_i[28]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[28]; +} /* end of pin sns_rsts_i[28] */ + +pin("sns_rsts_i[27]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[27]; +} /* end of pin sns_rsts_i[27] */ + +pin("sns_rsts_i[26]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[26]; +} /* end of pin sns_rsts_i[26] */ + +pin("sns_rsts_i[25]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[25]; +} /* end of pin sns_rsts_i[25] */ + +pin("sns_rsts_i[24]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[24]; +} /* end of pin sns_rsts_i[24] */ + +pin("sns_rsts_i[23]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[23]; +} /* end of pin sns_rsts_i[23] */ + +pin("sns_rsts_i[22]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[22]; +} /* end of pin sns_rsts_i[22] */ + +pin("sns_rsts_i[21]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[21]; +} /* end of pin sns_rsts_i[21] */ + +pin("sns_rsts_i[20]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[20]; +} /* end of pin sns_rsts_i[20] */ + +pin("sns_rsts_i[19]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[19]; +} /* end of pin sns_rsts_i[19] */ + +pin("sns_rsts_i[18]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[18]; +} /* end of pin sns_rsts_i[18] */ + +pin("sns_rsts_i[17]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[17]; +} /* end of pin sns_rsts_i[17] */ + +pin("sns_rsts_i[16]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[16]; +} /* end of pin sns_rsts_i[16] */ + +pin("sns_rsts_i[15]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[15]; +} /* end of pin sns_rsts_i[15] */ + +pin("sns_rsts_i[14]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[14]; +} /* end of pin sns_rsts_i[14] */ + +pin("sns_rsts_i[13]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[13]; +} /* end of pin sns_rsts_i[13] */ + +pin("sns_rsts_i[12]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[12]; +} /* end of pin sns_rsts_i[12] */ + +pin("sns_rsts_i[11]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[11]; +} /* end of pin sns_rsts_i[11] */ + +pin("sns_rsts_i[10]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[10]; +} /* end of pin sns_rsts_i[10] */ + +pin("sns_rsts_i[9]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[9]; +} /* end of pin sns_rsts_i[9] */ + +pin("sns_rsts_i[8]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[8]; +} /* end of pin sns_rsts_i[8] */ + +pin("sns_rsts_i[7]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[7]; +} /* end of pin sns_rsts_i[7] */ + +pin("sns_rsts_i[6]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[6]; +} /* end of pin sns_rsts_i[6] */ + +pin("sns_rsts_i[5]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[5]; +} /* end of pin sns_rsts_i[5] */ + +pin("sns_rsts_i[4]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[4]; +} /* end of pin sns_rsts_i[4] */ + +pin("sns_rsts_i[3]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[3]; +} /* end of pin sns_rsts_i[3] */ + +pin("sns_rsts_i[2]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[2]; +} /* end of pin sns_rsts_i[2] */ + +pin("sns_rsts_i[1]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[1]; +} /* end of pin sns_rsts_i[1] */ + +pin("sns_rsts_i[0]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_rsts_i[0]; +} /* end of pin sns_rsts_i[0] */ +} /* end of bus sns_rsts_i */ + +pin("sns_spi_ext_clk_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : sns_spi_ext_clk_i; +} /* end of pin sns_spi_ext_clk_i */ + +pin("vcc_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : vcc_supp_i; +} /* end of pin vcc_supp_i */ + +pin("vcaon_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : vcaon_supp_i; +} /* end of pin vcaon_supp_i */ + +pin("vcmain_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : vcmain_supp_i; +} /* end of pin vcmain_supp_i */ + +pin("vioa_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : vioa_supp_i; +} /* end of pin vioa_supp_i */ + +pin("viob_supp_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : viob_supp_i; +} /* end of pin viob_supp_i */ +bus ( ast_pwst_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("ast_pwst_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.652273 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000495 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[4]; +} /* end of pin ast_pwst_o[4] */ + +pin("ast_pwst_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.007560 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[3]; +} /* end of pin ast_pwst_o[3] */ + +pin("ast_pwst_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.029213 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000584 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[2]; + timing () { + related_pin : "ast_pwst_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\ + "0.125647, 0.191441, 0.306120, 0.621529, 1.461089",\ + "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\ + "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\ + "0.704776, 0.781389, 0.901027, 1.217412, 2.063059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118650, 0.232640, 0.431328, 0.981607, 2.441227",\ + "0.118668, 0.232640, 0.431330, 0.981682, 2.441227",\ + "0.118668, 0.233537, 0.432463, 0.981682, 2.441227",\ + "0.120002, 0.233537, 0.433774, 0.981682, 2.441227",\ + "0.161250, 0.255527, 0.435044, 0.981682, 2.441227"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\ + "0.068682, 0.082462, 0.106420, 0.172219, 0.347402",\ + "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\ + "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\ + "0.645975, 0.686648, 0.737659, 0.832084, 1.014107"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026953, 0.051423, 0.094862, 0.215093, 0.534102",\ + "0.026955, 0.051424, 0.094862, 0.215093, 0.534102",\ + "0.033450, 0.053875, 0.094993, 0.215093, 0.534241",\ + "0.046741, 0.065795, 0.101823, 0.215093, 0.534701",\ + "0.120319, 0.148529, 0.186126, 0.267902, 0.543427"); + } + + } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "ast_pwst_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\ + "0.125568, 0.191362, 0.306040, 0.621450, 1.461010",\ + "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\ + "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\ + "0.704776, 0.781389, 0.901027, 1.217412, 2.063059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118650, 0.232611, 0.431328, 0.977612, 2.431972",\ + "0.118650, 0.232611, 0.431330, 0.977612, 2.431972",\ + "0.118650, 0.233259, 0.432463, 0.977612, 2.431972",\ + "0.120002, 0.233259, 0.433774, 0.977612, 2.431972",\ + "0.161250, 0.255527, 0.435044, 0.981481, 2.431972"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\ + "0.068410, 0.082189, 0.106148, 0.171946, 0.347129",\ + "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\ + "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\ + "0.645975, 0.686648, 0.737659, 0.832084, 1.014107"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026953, 0.051423, 0.094862, 0.214557, 0.534102",\ + "0.026954, 0.051424, 0.094862, 0.214557, 0.534102",\ + "0.033450, 0.053875, 0.094993, 0.214557, 0.534241",\ + "0.046741, 0.065795, 0.101823, 0.215088, 0.534701",\ + "0.120319, 0.148529, 0.186126, 0.267902, 0.543427"); + } + + } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.120145, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.404676, 0.353105, 0.318351, 0.315478, 0.348023",\ + "0.454532, 0.402961, 0.368207, 0.365334, 0.397879",\ + "0.484555, 0.432984, 0.398230, 0.395357, 0.427902",\ + "0.566329, 0.514758, 0.480004, 0.477131, 0.509676",\ + "0.956464, 0.904894, 0.869963, 0.866772, 0.898621"); + } + + } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.118140, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.316729, -0.270030, -0.234537, -0.184982, -0.086025",\ + "-0.365783, -0.319083, -0.283591, -0.234035, -0.135079",\ + "-0.396608, -0.349909, -0.314416, -0.264861, -0.165904",\ + "-0.478382, -0.431683, -0.396190, -0.346635, -0.247678",\ + "-0.868371, -0.821645, -0.786315, -0.736867, -0.638027"); + } + + } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380000.531250, 380000.593750, 380000.718750, 380001.031250, 380001.875000",\ + "380000.625000, 380000.687500, 380000.812500, 380001.125000, 380001.968750",\ + "380000.687500, 380000.750000, 380000.875000, 380001.187500, 380002.031250",\ + "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\ + "380001.062500, 380001.125000, 380001.250000, 380001.562500, 380002.406250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\ + "380001.968750, 380001.968750, 380002.000000, 380002.062500, 380002.250000",\ + "380002.062500, 380002.062500, 380002.093750, 380002.156250, 380002.343750",\ + "380002.125000, 380002.125000, 380002.156250, 380002.218750, 380002.406250",\ + "380002.468750, 380002.468750, 380002.500000, 380002.562500, 380002.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.396377, 0.462195, 0.577090, 0.892530, 1.731965",\ + "0.483687, 0.549505, 0.664400, 0.979841, 1.819276",\ + "0.581466, 0.647284, 0.762179, 1.077619, 1.917054",\ + "0.654025, 0.719843, 0.834738, 1.150178, 1.989613",\ + "1.042482, 1.108301, 1.223195, 1.538636, 2.378071"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.326727, 0.341464, 0.366815, 0.435950, 0.619738",\ + "0.414576, 0.429313, 0.454664, 0.523799, 0.707587",\ + "0.495656, 0.510394, 0.535744, 0.604879, 0.788667",\ + "0.553927, 0.568665, 0.594015, 0.663150, 0.846938",\ + "0.864022, 0.878760, 0.904110, 0.973245, 1.157033"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380000.406250, 380000.468750, 380000.593750, 380000.906250, 380001.750000",\ + "380000.500000, 380000.562500, 380000.687500, 380001.000000, 380001.843750",\ + "380000.593750, 380000.656250, 380000.781250, 380001.093750, 380001.937500",\ + "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\ + "380001.000000, 380001.062500, 380001.187500, 380001.500000, 380002.343750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.781250, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\ + "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\ + "380002.000000, 380002.000000, 380002.031250, 380002.093750, 380002.281250",\ + "380002.187500, 380002.187500, 380002.218750, 380002.281250, 380002.468750",\ + "380002.500000, 380002.500000, 380002.531250, 380002.593750, 380002.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "379999.937500, 380000.000000, 380000.093750, 380000.406250, 380001.250000",\ + "380000.031250, 380000.093750, 380000.187500, 380000.500000, 380001.343750",\ + "380000.093750, 380000.156250, 380000.250000, 380000.562500, 380001.406250",\ + "380000.250000, 380000.312500, 380000.406250, 380000.718750, 380001.562500",\ + "380000.468750, 380000.531250, 380000.625000, 380000.937500, 380001.781250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.375000, 380001.406250, 380001.437500, 380001.500000, 380001.687500",\ + "380001.468750, 380001.500000, 380001.531250, 380001.593750, 380001.781250",\ + "380001.562500, 380001.593750, 380001.625000, 380001.687500, 380001.875000",\ + "380001.750000, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\ + "380002.000000, 380002.031250, 380002.062500, 380002.125000, 380002.312500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una_min*/ + +} /* end of pin ast_pwst_o[2] */ + +pin("ast_pwst_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.101136 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\ + "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\ + "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\ + "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\ + "7.693051, 7.884589, 8.004029, 8.262691, 9.135794"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\ + "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\ + "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\ + "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\ + "5.773359, 5.930601, 6.056160, 6.243834, 6.833694"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\ + "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\ + "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\ + "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\ + "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\ + "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\ + "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\ + "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\ + "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una_min*/ + +} /* end of pin ast_pwst_o[1] */ + +pin("ast_pwst_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.101136 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\ + "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\ + "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\ + "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\ + "7.693051, 7.884589, 8.004029, 8.262691, 9.135794"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\ + "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\ + "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\ + "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\ + "5.773359, 5.930601, 6.056160, 6.243834, 6.833694"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\ + "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\ + "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\ + "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\ + "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\ + "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\ + "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\ + "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\ + "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una_min*/ + +} /* end of pin ast_pwst_o[0] */ +} /* end of bus ast_pwst_o */ +bus ( ast_pwst_h_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("ast_pwst_h_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003358 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[4]; +} /* end of pin ast_pwst_h_o[4] */ + +pin("ast_pwst_h_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.007560 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[3]; +} /* end of pin ast_pwst_h_o[3] */ + +pin("ast_pwst_h_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.029213 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000584 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[2]; + timing () { + related_pin : "ast_pwst_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\ + "0.125647, 0.191441, 0.306120, 0.621529, 1.461089",\ + "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\ + "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\ + "0.704776, 0.781389, 0.901027, 1.217412, 2.063059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.018088, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118650, 0.232640, 0.431328, 0.981607, 2.441227",\ + "0.118668, 0.232640, 0.431330, 0.981682, 2.441227",\ + "0.118668, 0.233537, 0.432463, 0.981682, 2.441227",\ + "0.120002, 0.233537, 0.433774, 0.981682, 2.441227",\ + "0.161250, 0.255527, 0.435044, 0.981682, 2.441227"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\ + "0.068682, 0.082462, 0.106420, 0.172219, 0.347402",\ + "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\ + "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\ + "0.645975, 0.686648, 0.737659, 0.832084, 1.014107"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.021349, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026953, 0.051423, 0.094862, 0.215093, 0.534102",\ + "0.026955, 0.051424, 0.094862, 0.215093, 0.534102",\ + "0.033450, 0.053875, 0.094993, 0.215093, 0.534241",\ + "0.046741, 0.065795, 0.101823, 0.215093, 0.534701",\ + "0.120319, 0.148529, 0.186126, 0.267902, 0.543427"); + } + + } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "ast_pwst_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120368, 0.186170, 0.300859, 0.616258, 1.455810",\ + "0.125568, 0.191362, 0.306040, 0.621450, 1.461010",\ + "0.207819, 0.273839, 0.388973, 0.704719, 1.544218",\ + "0.296772, 0.362735, 0.477872, 0.794339, 1.635091",\ + "0.704776, 0.781389, 0.901027, 1.217412, 2.063059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.017926, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118650, 0.232611, 0.431328, 0.977612, 2.431972",\ + "0.118650, 0.232611, 0.431330, 0.977612, 2.431972",\ + "0.118650, 0.233259, 0.432463, 0.977612, 2.431972",\ + "0.120002, 0.233259, 0.433774, 0.977612, 2.431972",\ + "0.161250, 0.255527, 0.435044, 0.981481, 2.431972"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.061996, 0.075776, 0.099734, 0.165532, 0.340715",\ + "0.068410, 0.082189, 0.106148, 0.171946, 0.347129",\ + "0.154377, 0.169144, 0.193145, 0.258865, 0.434247",\ + "0.245754, 0.264276, 0.291081, 0.357185, 0.532518",\ + "0.645975, 0.686648, 0.737659, 0.832084, 1.014107"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.020771, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026953, 0.051423, 0.094862, 0.214557, 0.534102",\ + "0.026954, 0.051424, 0.094862, 0.214557, 0.534102",\ + "0.033450, 0.053875, 0.094993, 0.214557, 0.534241",\ + "0.046741, 0.065795, 0.101823, 0.215088, 0.534701",\ + "0.120319, 0.148529, 0.186126, 0.267902, 0.543427"); + } + + } /* end of arc ast_pwst_o[4]_ast_pwst_o[2]_una_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.120145, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.404676, 0.353105, 0.318351, 0.315478, 0.348023",\ + "0.454532, 0.402961, 0.368207, 0.365334, 0.397879",\ + "0.484555, 0.432984, 0.398230, 0.395357, 0.427902",\ + "0.566329, 0.514758, 0.480004, 0.477131, 0.509676",\ + "0.956464, 0.904894, 0.869963, 0.866772, 0.898621"); + } + + } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.118140, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.316729, -0.270030, -0.234537, -0.184982, -0.086025",\ + "-0.365783, -0.319083, -0.283591, -0.234035, -0.135079",\ + "-0.396608, -0.349909, -0.314416, -0.264861, -0.165904",\ + "-0.478382, -0.431683, -0.396190, -0.346635, -0.247678",\ + "-0.868371, -0.821645, -0.786315, -0.736867, -0.638027"); + } + + } /* end of arc clk_ast_ext_i_ast_pwst_o[2]_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380000.531250, 380000.593750, 380000.718750, 380001.031250, 380001.875000",\ + "380000.625000, 380000.687500, 380000.812500, 380001.125000, 380001.968750",\ + "380000.687500, 380000.750000, 380000.875000, 380001.187500, 380002.031250",\ + "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\ + "380001.062500, 380001.125000, 380001.250000, 380001.562500, 380002.406250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\ + "380001.968750, 380001.968750, 380002.000000, 380002.062500, 380002.250000",\ + "380002.062500, 380002.062500, 380002.093750, 380002.156250, 380002.343750",\ + "380002.125000, 380002.125000, 380002.156250, 380002.218750, 380002.406250",\ + "380002.468750, 380002.468750, 380002.500000, 380002.562500, 380002.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875",\ + "0.031251, 0.056161, 0.101276, 0.226771, 0.561875"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.396377, 0.462195, 0.577090, 0.892530, 1.731965",\ + "0.483687, 0.549505, 0.664400, 0.979841, 1.819276",\ + "0.581466, 0.647284, 0.762179, 1.077619, 1.917054",\ + "0.654025, 0.719843, 0.834738, 1.150178, 1.989613",\ + "1.042482, 1.108301, 1.223195, 1.538636, 2.378071"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812",\ + "0.118140, 0.231881, 0.431660, 0.979741, 2.437812"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.326727, 0.341464, 0.366815, 0.435950, 0.619738",\ + "0.414576, 0.429313, 0.454664, 0.523799, 0.707587",\ + "0.495656, 0.510394, 0.535744, 0.604879, 0.788667",\ + "0.553927, 0.568665, 0.594015, 0.663150, 0.846938",\ + "0.864022, 0.878760, 0.904110, 0.973245, 1.157033"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[2]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380000.406250, 380000.468750, 380000.593750, 380000.906250, 380001.750000",\ + "380000.500000, 380000.562500, 380000.687500, 380001.000000, 380001.843750",\ + "380000.593750, 380000.656250, 380000.781250, 380001.093750, 380001.937500",\ + "380000.750000, 380000.812500, 380000.937500, 380001.250000, 380002.093750",\ + "380001.000000, 380001.062500, 380001.187500, 380001.500000, 380002.343750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448",\ + "0.120145, 0.234100, 0.432069, 0.982878, 2.445448"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.781250, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\ + "380001.875000, 380001.875000, 380001.906250, 380001.968750, 380002.156250",\ + "380002.000000, 380002.000000, 380002.031250, 380002.093750, 380002.281250",\ + "380002.187500, 380002.187500, 380002.218750, 380002.281250, 380002.468750",\ + "380002.500000, 380002.500000, 380002.531250, 380002.593750, 380002.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877",\ + "0.031236, 0.056156, 0.101275, 0.226769, 0.561877"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "379999.937500, 380000.000000, 380000.093750, 380000.406250, 380001.250000",\ + "380000.031250, 380000.093750, 380000.187500, 380000.500000, 380001.343750",\ + "380000.093750, 380000.156250, 380000.250000, 380000.562500, 380001.406250",\ + "380000.250000, 380000.312500, 380000.406250, 380000.718750, 380001.562500",\ + "380000.468750, 380000.531250, 380000.625000, 380000.937500, 380001.781250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852",\ + "0.118145, 0.231881, 0.431660, 0.979741, 2.437852"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "380001.375000, 380001.406250, 380001.437500, 380001.500000, 380001.687500",\ + "380001.468750, 380001.500000, 380001.531250, 380001.593750, 380001.781250",\ + "380001.562500, 380001.593750, 380001.625000, 380001.687500, 380001.875000",\ + "380001.750000, 380001.781250, 380001.812500, 380001.875000, 380002.062500",\ + "380002.000000, 380002.031250, 380002.062500, 380002.125000, 380002.312500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000584, 0.001979, 0.004430, 0.011183, 0.029213"); + values ( "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206",\ + "0.026020, 0.051544, 0.096671, 0.220662, 0.551206"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[2]_una_min*/ + +} /* end of pin ast_pwst_h_o[2] */ + +pin("ast_pwst_h_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.101136 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\ + "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\ + "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\ + "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\ + "7.693051, 7.884589, 8.004029, 8.262691, 9.135794"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\ + "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\ + "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\ + "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\ + "5.773359, 5.930601, 6.056160, 6.243834, 6.833694"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[1]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\ + "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\ + "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\ + "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\ + "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\ + "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\ + "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\ + "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\ + "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[1]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[1]_una_min*/ + +} /* end of pin ast_pwst_h_o[1] */ + +pin("ast_pwst_h_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.101136 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast_pwst_h_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "7.046945, 7.238483, 7.357924, 7.616586, 8.489688",\ + "7.134256, 7.325794, 7.445234, 7.703897, 8.576999",\ + "7.232034, 7.423573, 7.543013, 7.801675, 8.674777",\ + "7.304593, 7.496131, 7.615571, 7.874234, 8.747335",\ + "7.693051, 7.884589, 8.004029, 8.262691, 9.135794"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "5.236063, 5.393305, 5.518865, 5.706539, 6.296398",\ + "5.323912, 5.481154, 5.606714, 5.794387, 6.384247",\ + "5.404993, 5.562235, 5.687795, 5.875468, 6.465328",\ + "5.463264, 5.620506, 5.746066, 5.933739, 6.523599",\ + "5.773359, 5.930601, 6.056160, 6.243834, 6.833694"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133",\ + "0.242588, 0.288084, 0.303651, 0.497673, 1.551133"); + } + + } /* end of arc clk_ast_tlul_i_ast_pwst_o[0]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.781250, 380006.968750, 380007.093750, 380007.343750, 380008.218750",\ + "380006.937500, 380007.125000, 380007.250000, 380007.500000, 380008.375000",\ + "380007.187500, 380007.375000, 380007.500000, 380007.750000, 380008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.500000, 380006.656250, 380006.781250, 380006.968750, 380007.562500",\ + "380006.687500, 380006.843750, 380006.968750, 380007.156250, 380007.750000",\ + "380007.000000, 380007.156250, 380007.281250, 380007.468750, 380008.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.593750, 380006.781250, 380006.906250, 380007.156250, 380008.031250",\ + "380006.687500, 380006.875000, 380007.000000, 380007.250000, 380008.125000",\ + "380006.750000, 380006.937500, 380007.062500, 380007.312500, 380008.187500",\ + "380006.906250, 380007.093750, 380007.218750, 380007.468750, 380008.343750",\ + "380007.125000, 380007.312500, 380007.437500, 380007.687500, 380008.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "380006.281250, 380006.437500, 380006.562500, 380006.750000, 380007.343750",\ + "380006.375000, 380006.531250, 380006.656250, 380006.843750, 380007.437500",\ + "380006.468750, 380006.625000, 380006.750000, 380006.937500, 380007.531250",\ + "380006.656250, 380006.812500, 380006.937500, 380007.125000, 380007.718750",\ + "380006.906250, 380007.062500, 380007.187500, 380007.375000, 380007.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.187500, 970006.312500, 970006.437500, 970006.625000, 970007.250000",\ + "970006.437500, 970006.562500, 970006.687500, 970006.875000, 970007.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.812500, 970009.000000, 970009.125000, 970009.375000, 970010.250000",\ + "970009.062500, 970009.250000, 970009.375000, 970009.625000, 970010.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832",\ + "0.256850, 0.317997, 0.317997, 0.797663, 2.394832"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970005.812500, 970005.937500, 970006.062500, 970006.250000, 970006.875000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970005.937500, 970006.062500, 970006.187500, 970006.375000, 970007.000000",\ + "970006.062500, 970006.187500, 970006.312500, 970006.500000, 970007.125000",\ + "970006.312500, 970006.437500, 970006.562500, 970006.750000, 970007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132",\ + "0.242595, 0.288092, 0.303657, 0.497674, 1.551132"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "970008.312500, 970008.500000, 970008.625000, 970008.875000, 970009.750000",\ + "970008.437500, 970008.625000, 970008.750000, 970009.000000, 970009.875000",\ + "970008.562500, 970008.750000, 970008.875000, 970009.125000, 970010.000000",\ + "970008.687500, 970008.875000, 970009.000000, 970009.250000, 970010.125000",\ + "970008.937500, 970009.125000, 970009.250000, 970009.500000, 970010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + + } /* end of arc padmux2ast_i[4]_ast_pwst_o[0]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127",\ + "0.256090, 0.317188, 0.317188, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.312500, 590006.437500, 590006.562500, 590006.750000, 590007.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.687500, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590006.812500, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590006.937500, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.187500, 590007.375000, 590007.500000, 590007.750000, 590008.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127",\ + "0.256090, 0.291712, 0.291712, 0.797460, 2.395127"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "590005.562500, 590005.687500, 590005.812500, 590006.000000, 590006.625000",\ + "590005.687500, 590005.812500, 590005.937500, 590006.125000, 590006.750000",\ + "590005.812500, 590005.937500, 590006.062500, 590006.250000, 590006.875000",\ + "590005.937500, 590006.062500, 590006.187500, 590006.375000, 590007.000000",\ + "590006.187500, 590006.312500, 590006.437500, 590006.625000, 590007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002606, 0.008844, 0.030015, 0.101136"); + values ( "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101",\ + "0.242962, 0.288493, 0.303943, 0.497719, 1.551101"); + } + + } /* end of arc padmux2ast_i[5]_ast_pwst_o[0]_una_min*/ + +} /* end of pin ast_pwst_h_o[0] */ +} /* end of bus ast_pwst_h_o */ + +pin("main_pd_ni") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001140 ; + + /* Other user defined attributes. */ + original_pin : main_pd_ni; +} /* end of pin main_pd_ni */ + +pin("main_env_iso_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000488 ; + + /* Other user defined attributes. */ + original_pin : main_env_iso_en_i; +} /* end of pin main_env_iso_en_i */ + +pin("flash_power_down_h_o") { + direction : output ; + max_transition : 3.720000 ; + min_transition : 0.000000 ; + max_capacitance : 0.350585 ; + min_capacitance : 0.000387 ; + max_fanout : 50.000000 ; + capacitance : 0.004062 ; + + /* Other user defined attributes. */ + original_pin : flash_power_down_h_o; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.718750, 380000.781250, 380000.937500, 380001.375000, 380002.718750",\ + "380000.812500, 380000.875000, 380001.031250, 380001.468750, 380002.812500",\ + "380000.875000, 380000.937500, 380001.093750, 380001.531250, 380002.875000",\ + "380000.937500, 380001.000000, 380001.156250, 380001.593750, 380002.937500",\ + "380001.250000, 380001.312500, 380001.468750, 380001.906250, 380003.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074057, 0.193193, 0.452097, 1.259663, 3.712074",\ + "0.074058, 0.193193, 0.452097, 1.259663, 3.712070",\ + "0.074060, 0.193194, 0.452097, 1.259660, 3.712049",\ + "0.074063, 0.193195, 0.452097, 1.259657, 3.712028",\ + "0.074111, 0.193204, 0.452092, 1.259600, 3.711658"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.000000, 380002.031250, 380002.093750, 380002.312500, 380002.843750",\ + "380002.093750, 380002.125000, 380002.187500, 380002.406250, 380002.937500",\ + "380002.187500, 380002.218750, 380002.281250, 380002.500000, 380003.031250",\ + "380002.250000, 380002.281250, 380002.343750, 380002.562500, 380003.093750",\ + "380002.593750, 380002.625000, 380002.687500, 380002.906250, 380003.437500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364"); + } + + } /* end of arc clk_ast_tlul_i_flash_power_down_h_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.352648, 0.424230, 0.570187, 1.017271, 2.367661",\ + "0.440969, 0.512551, 0.658508, 1.105592, 2.455982",\ + "0.531538, 0.603120, 0.749077, 1.196161, 2.546552",\ + "0.596976, 0.668558, 0.814515, 1.261599, 2.611990",\ + "0.939689, 1.011271, 1.157229, 1.604312, 2.954703"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.254546, 0.300198, 0.374019, 0.564384, 1.125543",\ + "0.341890, 0.387542, 0.461363, 0.651728, 1.212887",\ + "0.422786, 0.468439, 0.542260, 0.732625, 1.293784",\ + "0.480635, 0.526288, 0.600109, 0.790475, 1.351633",\ + "0.785321, 0.830974, 0.904795, 1.095161, 1.656318"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054514, 0.105890, 0.199332, 0.496290, 1.444361",\ + "0.054514, 0.105890, 0.199332, 0.496290, 1.444361",\ + "0.054513, 0.105889, 0.199332, 0.496290, 1.444360",\ + "0.054513, 0.105887, 0.199332, 0.496290, 1.444359",\ + "0.054513, 0.105887, 0.199332, 0.496290, 1.444358"); + } + + } /* end of arc clk_ast_tlul_i_flash_power_down_h_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.593750, 380000.656250, 380000.812500, 380001.250000, 380002.593750",\ + "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\ + "380000.781250, 380000.843750, 380001.000000, 380001.437500, 380002.781250",\ + "380000.937500, 380001.000000, 380001.156250, 380001.593750, 380002.937500",\ + "380001.187500, 380001.250000, 380001.406250, 380001.843750, 380003.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380001.906250, 380001.937500, 380002.000000, 380002.218750, 380002.750000",\ + "380002.000000, 380002.031250, 380002.093750, 380002.312500, 380002.843750",\ + "380002.125000, 380002.156250, 380002.218750, 380002.437500, 380002.968750",\ + "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\ + "380002.625000, 380002.656250, 380002.718750, 380002.937500, 380003.468750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364"); + } + + } /* end of arc padmux2ast_i[4]_flash_power_down_h_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.593750, 380000.656250, 380000.812500, 380001.250000, 380002.593750",\ + "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\ + "380000.750000, 380000.812500, 380000.968750, 380001.406250, 380002.750000",\ + "380000.906250, 380000.968750, 380001.125000, 380001.562500, 380002.906250",\ + "380001.125000, 380001.187500, 380001.343750, 380001.781250, 380003.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141",\ + "0.074048, 0.193192, 0.452098, 1.259674, 3.712141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380001.906250, 380001.937500, 380002.000000, 380002.218750, 380002.750000",\ + "380002.000000, 380002.031250, 380002.093750, 380002.312500, 380002.843750",\ + "380002.093750, 380002.125000, 380002.187500, 380002.406250, 380002.937500",\ + "380002.281250, 380002.312500, 380002.375000, 380002.593750, 380003.125000",\ + "380002.531250, 380002.562500, 380002.625000, 380002.843750, 380003.375000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364",\ + "0.054518, 0.105901, 0.199326, 0.496289, 1.444364"); + } + + } /* end of arc padmux2ast_i[4]_flash_power_down_h_o_una_min*/ + +} /* end of pin flash_power_down_h_o */ + +pin("flash_power_ready_h_o") { + direction : output ; + max_transition : 3.720000 ; + min_transition : 0.000000 ; + max_capacitance : 0.350585 ; + min_capacitance : 0.000387 ; + max_fanout : 50.000000 ; + capacitance : 0.004062 ; + + /* Other user defined attributes. */ + original_pin : flash_power_ready_h_o; +} /* end of pin flash_power_ready_h_o */ +bus ( otp_power_seq_i ) { + + bus_type : BUS2_type5 ; + direction : input ; + +pin("otp_power_seq_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002066 ; + + /* Other user defined attributes. */ + original_pin : otp_power_seq_i[1]; +} /* end of pin otp_power_seq_i[1] */ + +pin("otp_power_seq_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002439 ; + + /* Other user defined attributes. */ + original_pin : otp_power_seq_i[0]; +} /* end of pin otp_power_seq_i[0] */ +} /* end of bus otp_power_seq_i */ +bus ( otp_power_seq_h_o ) { + + bus_type : BUS2_type5 ; + direction : output ; + +pin("otp_power_seq_h_o[1]") { + direction : output ; + max_transition : 3.720000 ; + min_transition : 0.000000 ; + max_capacitance : 0.350585 ; + min_capacitance : 0.000387 ; + max_fanout : 50.000000 ; + capacitance : 0.004062 ; + + /* Other user defined attributes. */ + original_pin : otp_power_seq_h_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.812500, 380000.875000, 380001.031250, 380001.468750, 380002.812500",\ + "380000.906250, 380000.968750, 380001.125000, 380001.562500, 380002.906250",\ + "380000.968750, 380001.031250, 380001.187500, 380001.625000, 380002.968750",\ + "380001.031250, 380001.093750, 380001.250000, 380001.687500, 380003.031250",\ + "380001.343750, 380001.406250, 380001.562500, 380002.000000, 380003.343750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\ + "380002.406250, 380002.437500, 380002.500000, 380002.718750, 380003.250000",\ + "380002.500000, 380002.531250, 380002.593750, 380002.812500, 380003.343750",\ + "380002.562500, 380002.593750, 380002.656250, 380002.875000, 380003.406250",\ + "380002.906250, 380002.937500, 380003.000000, 380003.218750, 380003.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343"); + } + + } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.448711, 0.520292, 0.666247, 1.113340, 2.463725",\ + "0.537164, 0.608745, 0.754701, 1.201793, 2.552178",\ + "0.627117, 0.698698, 0.844654, 1.291746, 2.642131",\ + "0.691522, 0.763103, 0.909059, 1.356151, 2.706536",\ + "1.028584, 1.100166, 1.246121, 1.693213, 3.043598"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.535143, 0.580795, 0.654612, 0.844979, 1.406126",\ + "0.622520, 0.668171, 0.741989, 0.932356, 1.493503",\ + "0.703389, 0.749041, 0.822858, 1.013225, 1.574372",\ + "0.761087, 0.806739, 0.880556, 1.070923, 1.632070",\ + "1.064074, 1.109726, 1.183543, 1.373910, 1.935057"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343"); + } + + } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[1]_redg_min*/ + + timing () { + related_pin : "otp_power_seq_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.280735, 0.352314, 0.498262, 0.945381, 2.295748",\ + "0.365932, 0.437494, 0.583395, 1.030705, 2.380943",\ + "0.458471, 0.529972, 0.675698, 1.123714, 2.473475",\ + "0.634070, 0.705499, 0.850886, 1.299582, 2.649080",\ + "0.942777, 1.014243, 1.159029, 1.607148, 2.957408"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074065, 0.193195, 0.452096, 1.259655, 3.712015",\ + "0.074153, 0.193212, 0.452096, 1.259655, 3.712015",\ + "0.074479, 0.193278, 0.452096, 1.259655, 3.712015",\ + "0.075512, 0.193773, 0.452096, 1.259655, 3.712015",\ + "0.077859, 0.195201, 0.452096, 1.259655, 3.712015"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.164110, 0.209762, 0.283580, 0.473944, 1.035104",\ + "0.247135, 0.292784, 0.366597, 0.556994, 1.118023",\ + "0.324377, 0.370013, 0.443807, 0.634329, 1.194869",\ + "0.452551, 0.498155, 0.571901, 0.762742, 1.322028",\ + "0.650770, 0.696491, 0.770670, 0.961172, 1.520128"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.105900, 0.199326, 0.496289, 1.444363",\ + "0.054583, 0.105900, 0.199350, 0.496296, 1.444363",\ + "0.054828, 0.105900, 0.199442, 0.496321, 1.444363",\ + "0.055455, 0.105900, 0.199678, 0.496387, 1.444363",\ + "0.057468, 0.107107, 0.200875, 0.496387, 1.444363"); + } + + } /* end of arc otp_power_seq_i[1]_otp_power_seq_h_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_power_seq_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.280735, 0.352314, 0.498262, 0.945381, 2.295748",\ + "0.365932, 0.437494, 0.583395, 1.030705, 2.380943",\ + "0.458471, 0.529972, 0.675698, 1.123714, 2.473475",\ + "0.634070, 0.705499, 0.850886, 1.299582, 2.649080",\ + "0.942777, 1.014243, 1.159029, 1.607148, 2.957408"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074065, 0.193195, 0.451499, 1.259037, 3.706044",\ + "0.074153, 0.193212, 0.451499, 1.259037, 3.706044",\ + "0.074479, 0.193278, 0.451499, 1.259037, 3.706044",\ + "0.075512, 0.193773, 0.451499, 1.259037, 3.706044",\ + "0.077859, 0.195201, 0.451499, 1.259378, 3.706689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.164110, 0.209762, 0.283580, 0.473944, 1.035104",\ + "0.247135, 0.292784, 0.366597, 0.556994, 1.118023",\ + "0.324377, 0.370013, 0.443807, 0.634329, 1.194869",\ + "0.452551, 0.498155, 0.571901, 0.762742, 1.322028",\ + "0.650770, 0.696491, 0.770670, 0.961172, 1.520128"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054518, 0.104862, 0.199326, 0.496289, 1.441414",\ + "0.054583, 0.104862, 0.199350, 0.496296, 1.441414",\ + "0.054828, 0.104862, 0.199442, 0.496321, 1.441414",\ + "0.055455, 0.104862, 0.199678, 0.496356, 1.441414",\ + "0.057468, 0.107107, 0.200875, 0.496356, 1.442153"); + } + + } /* end of arc otp_power_seq_i[1]_otp_power_seq_h_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\ + "380000.781250, 380000.843750, 380001.000000, 380001.437500, 380002.781250",\ + "380000.875000, 380000.937500, 380001.093750, 380001.531250, 380002.875000",\ + "380001.031250, 380001.093750, 380001.250000, 380001.687500, 380003.031250",\ + "380001.281250, 380001.343750, 380001.500000, 380001.937500, 380003.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.218750, 380002.250000, 380002.312500, 380002.531250, 380003.062500",\ + "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\ + "380002.437500, 380002.468750, 380002.531250, 380002.750000, 380003.281250",\ + "380002.625000, 380002.656250, 380002.718750, 380002.937500, 380003.468750",\ + "380002.937500, 380002.968750, 380003.031250, 380003.250000, 380003.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343"); + } + + } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.687500, 380000.750000, 380000.906250, 380001.343750, 380002.687500",\ + "380000.781250, 380000.843750, 380001.000000, 380001.437500, 380002.781250",\ + "380000.843750, 380000.906250, 380001.062500, 380001.500000, 380002.843750",\ + "380001.000000, 380001.062500, 380001.218750, 380001.656250, 380003.000000",\ + "380001.218750, 380001.281250, 380001.437500, 380001.875000, 380003.218750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109",\ + "0.074053, 0.193192, 0.452098, 1.259669, 3.712109"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.218750, 380002.250000, 380002.312500, 380002.531250, 380003.062500",\ + "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.156250",\ + "380002.406250, 380002.437500, 380002.500000, 380002.718750, 380003.250000",\ + "380002.593750, 380002.625000, 380002.687500, 380002.906250, 380003.437500",\ + "380002.843750, 380002.875000, 380002.937500, 380003.156250, 380003.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343",\ + "0.054525, 0.105893, 0.199328, 0.496289, 1.444343"); + } + + } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[1]_una_min*/ + +} /* end of pin otp_power_seq_h_o[1] */ + +pin("otp_power_seq_h_o[0]") { + direction : output ; + max_transition : 3.720000 ; + min_transition : 0.000000 ; + max_capacitance : 0.350585 ; + min_capacitance : 0.000387 ; + max_fanout : 50.000000 ; + capacitance : 0.004062 ; + + /* Other user defined attributes. */ + original_pin : otp_power_seq_h_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.312500, 380002.406250, 380002.531250, 380003.000000, 380004.343750",\ + "380002.406250, 380002.500000, 380002.625000, 380003.093750, 380004.437500",\ + "380002.500000, 380002.593750, 380002.718750, 380003.187500, 380004.531250",\ + "380002.562500, 380002.656250, 380002.781250, 380003.250000, 380004.593750",\ + "380002.906250, 380003.000000, 380003.125000, 380003.593750, 380004.937500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073833, 0.193149, 0.452120, 1.259926, 3.713809",\ + "0.073833, 0.193149, 0.452120, 1.259926, 3.713809",\ + "0.073833, 0.193149, 0.452120, 1.259926, 3.713809",\ + "0.073834, 0.193149, 0.452120, 1.259926, 3.713806",\ + "0.073834, 0.193149, 0.452120, 1.259926, 3.713804"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.593750, 380000.656250, 380000.718750, 380000.906250, 380001.468750",\ + "380000.687500, 380000.750000, 380000.812500, 380001.000000, 380001.562500",\ + "380000.750000, 380000.812500, 380000.875000, 380001.062500, 380001.625000",\ + "380000.812500, 380000.875000, 380000.937500, 380001.125000, 380001.687500",\ + "380001.125000, 380001.187500, 380001.250000, 380001.437500, 380002.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054415, 0.105307, 0.199650, 0.496371, 1.443909",\ + "0.054415, 0.105307, 0.199650, 0.496371, 1.443909",\ + "0.054415, 0.105307, 0.199650, 0.496371, 1.443909",\ + "0.054415, 0.105309, 0.199649, 0.496371, 1.443911",\ + "0.054417, 0.105319, 0.199643, 0.496370, 1.443919"); + } + + } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.573426, 0.645049, 0.791123, 1.237737, 2.588445",\ + "0.660803, 0.732425, 0.878500, 1.325114, 2.675822",\ + "0.741672, 0.813295, 0.959369, 1.405983, 2.756691",\ + "0.799370, 0.870993, 1.017067, 1.463682, 2.814389",\ + "1.102357, 1.173980, 1.320054, 1.766668, 3.117376"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.260939, 0.306616, 0.380550, 0.571046, 1.131945",\ + "0.349392, 0.395070, 0.469004, 0.659499, 1.220399",\ + "0.439345, 0.485023, 0.558957, 0.749452, 1.310352",\ + "0.503750, 0.549428, 0.623362, 0.813857, 1.374757",\ + "0.840813, 0.886490, 0.960424, 1.150919, 1.711819"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908"); + } + + } /* end of arc clk_ast_tlul_i_otp_power_seq_h_o[0]_redg_min*/ + + timing () { + related_pin : "otp_power_seq_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.258742, 0.330399, 0.476573, 0.922786, 2.273765",\ + "0.342268, 0.413906, 0.560027, 1.006455, 2.357289",\ + "0.432373, 0.503959, 0.649927, 1.096969, 2.447388",\ + "0.604916, 0.676353, 0.821884, 1.270636, 2.619913",\ + "0.890695, 0.962107, 1.107175, 1.555746, 2.905733"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073647, 0.193112, 0.452140, 1.260145, 3.715251",\ + "0.073746, 0.193131, 0.452140, 1.260145, 3.715251",\ + "0.074030, 0.193188, 0.452140, 1.260145, 3.715251",\ + "0.074867, 0.193375, 0.452140, 1.260145, 3.715251",\ + "0.076941, 0.194654, 0.452140, 1.260145, 3.715251"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.158895, 0.204571, 0.278502, 0.468994, 1.029901",\ + "0.236396, 0.282061, 0.355936, 0.546363, 1.107398",\ + "0.299798, 0.345438, 0.419238, 0.609722, 1.170409",\ + "0.399856, 0.445471, 0.519267, 0.710096, 1.269222",\ + "0.539370, 0.585337, 0.659872, 0.850367, 1.409363"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054417, 0.105322, 0.199642, 0.496369, 1.443922",\ + "0.054466, 0.105609, 0.199642, 0.496369, 1.443922",\ + "0.054754, 0.105639, 0.199642, 0.496369, 1.443922",\ + "0.055765, 0.105639, 0.199849, 0.496390, 1.443922",\ + "0.058856, 0.108680, 0.201816, 0.496464, 1.443922"); + } + + } /* end of arc otp_power_seq_i[0]_otp_power_seq_h_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_power_seq_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.258742, 0.330399, 0.476573, 0.922786, 2.273765",\ + "0.342268, 0.413906, 0.560027, 1.006455, 2.357289",\ + "0.432373, 0.503959, 0.649927, 1.096969, 2.447388",\ + "0.604916, 0.676353, 0.821884, 1.270636, 2.619913",\ + "0.890695, 0.962107, 1.107175, 1.555746, 2.905733"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073647, 0.193112, 0.451380, 1.258785, 3.705802",\ + "0.073746, 0.193131, 0.451380, 1.258785, 3.705802",\ + "0.074030, 0.193188, 0.451380, 1.258785, 3.705802",\ + "0.074867, 0.193375, 0.451380, 1.258785, 3.705802",\ + "0.076941, 0.194654, 0.451380, 1.259595, 3.705802"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.158895, 0.204571, 0.278502, 0.468994, 1.029901",\ + "0.236396, 0.282061, 0.355936, 0.546363, 1.107398",\ + "0.299798, 0.345438, 0.419238, 0.609722, 1.170409",\ + "0.399856, 0.445471, 0.519267, 0.710096, 1.269222",\ + "0.539370, 0.585337, 0.659872, 0.850367, 1.409363"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054417, 0.105076, 0.199414, 0.496314, 1.441319",\ + "0.054466, 0.105076, 0.199414, 0.496314, 1.441319",\ + "0.054754, 0.105076, 0.199414, 0.496314, 1.441319",\ + "0.055765, 0.105076, 0.199849, 0.496390, 1.441319",\ + "0.058856, 0.108680, 0.201816, 0.496464, 1.442721"); + } + + } /* end of arc otp_power_seq_i[0]_otp_power_seq_h_o[0]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.468750, 380000.531250, 380000.593750, 380000.781250, 380001.343750",\ + "380000.562500, 380000.625000, 380000.687500, 380000.875000, 380001.437500",\ + "380000.656250, 380000.718750, 380000.781250, 380000.968750, 380001.531250",\ + "380000.812500, 380000.875000, 380000.937500, 380001.125000, 380001.687500",\ + "380001.062500, 380001.125000, 380001.187500, 380001.375000, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.218750, 380002.312500, 380002.437500, 380002.906250, 380004.250000",\ + "380002.312500, 380002.406250, 380002.531250, 380003.000000, 380004.343750",\ + "380002.437500, 380002.531250, 380002.656250, 380003.125000, 380004.468750",\ + "380002.625000, 380002.718750, 380002.843750, 380003.312500, 380004.656250",\ + "380002.937500, 380003.031250, 380003.156250, 380003.625000, 380004.968750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817"); + } + + } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380000.468750, 380000.531250, 380000.593750, 380000.781250, 380001.343750",\ + "380000.562500, 380000.625000, 380000.687500, 380000.875000, 380001.437500",\ + "380000.625000, 380000.687500, 380000.750000, 380000.937500, 380001.500000",\ + "380000.781250, 380000.843750, 380000.906250, 380001.093750, 380001.656250",\ + "380001.000000, 380001.062500, 380001.125000, 380001.312500, 380001.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908",\ + "0.054414, 0.105305, 0.199651, 0.496372, 1.443908"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "380002.218750, 380002.312500, 380002.437500, 380002.906250, 380004.250000",\ + "380002.312500, 380002.406250, 380002.531250, 380003.000000, 380004.343750",\ + "380002.406250, 380002.500000, 380002.625000, 380003.093750, 380004.437500",\ + "380002.593750, 380002.687500, 380002.812500, 380003.281250, 380004.625000",\ + "380002.843750, 380002.937500, 380003.062500, 380003.531250, 380004.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.004062, 0.015733, 0.040393, 0.117156, 0.350585"); + values ( "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817",\ + "0.073832, 0.193148, 0.452121, 1.259928, 3.713817"); + } + + } /* end of arc padmux2ast_i[4]_otp_power_seq_h_o[0]_inv_min*/ + +} /* end of pin otp_power_seq_h_o[0] */ +} /* end of bus otp_power_seq_h_o */ + +pin("clk_src_sys_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002156 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_en_i; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.271588, 0.219415, 0.179927, 0.162045, 0.157577",\ + "0.363033, 0.310027, 0.270334, 0.252385, 0.247965",\ + "0.507780, 0.454308, 0.413646, 0.395357, 0.391106",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.324602, 0.241857, 0.166855, 0.126539, 0.100040",\ + "0.429418, 0.345854, 0.270221, 0.227986, 0.196782",\ + "0.605833, 0.521783, 0.445878, 0.397956, 0.350944",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_en_i_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\ + "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\ + "-0.373429, -0.330963, -0.299719, -0.251733, -0.152256",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\ + "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\ + "-0.470591, -0.397956, -0.329423, -0.234665, -0.046227",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_en_i_hldr*/ + +} /* end of pin clk_src_sys_en_i */ +bus ( clk_src_sys_jen_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("clk_src_sys_jen_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_jen_i[3]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.116868, 0.046289, 0.009123, -0.023399, -0.072101",\ + "0.130035, 0.060315, 0.022495, -0.010308, -0.059037",\ + "0.171476, 0.101933, 0.064692, 0.030941, -0.021156",\ + "0.330098, 0.263569, 0.222296, 0.181197, 0.112987",\ + "0.772581, 0.713134, 0.646673, 0.587289, 0.496722"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.164832, 0.206226, 0.283518, 0.436969, 0.781571",\ + "0.176771, 0.218346, 0.296254, 0.450000, 0.794722",\ + "0.219963, 0.260510, 0.337961, 0.490822, 0.833567",\ + "0.396019, 0.435268, 0.507744, 0.654408, 0.985407",\ + "0.931350, 0.951153, 1.007354, 1.144760, 1.468564"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.015255, 0.029491, 0.060650, 0.100375, 0.176530",\ + "-0.028040, 0.015174, 0.046352, 0.086407, 0.163478",\ + "-0.067695, -0.029062, 0.006032, 0.048125, 0.126390",\ + "-0.170614, -0.143005, -0.113142, -0.070129, 0.016864",\ + "-0.388675, -0.412783, -0.403332, -0.363654, -0.262218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.058687, -0.133819, -0.215174, -0.342668, -0.608913",\ + "-0.070579, -0.145649, -0.226804, -0.353700, -0.618487",\ + "-0.113780, -0.187774, -0.267897, -0.394083, -0.658063",\ + "-0.257059, -0.339271, -0.416614, -0.539608, -0.797794",\ + "-0.613549, -0.743897, -0.832843, -0.961101, -1.220625"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[3]_hldr*/ + +} /* end of pin clk_src_sys_jen_i[3] */ + +pin("clk_src_sys_jen_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_jen_i[2]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.100962, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.138649, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.289688, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.060195, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.100267, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.269875, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.107327, -0.064625, -0.028931, 0.021950, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.015040, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.159889, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.091894, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.053525, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.113499, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[2]_hldr*/ + +} /* end of pin clk_src_sys_jen_i[2] */ + +pin("clk_src_sys_jen_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_jen_i[1]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.100962, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.138649, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.289688, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.060195, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.100267, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.269875, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.107327, -0.064625, -0.028931, 0.021950, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.015040, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.159889, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.091894, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.053525, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.113499, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[1]_hldr*/ + +} /* end of pin clk_src_sys_jen_i[1] */ + +pin("clk_src_sys_jen_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_jen_i[0]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.116868, 0.046289, 0.009123, -0.023399, -0.072101",\ + "0.130035, 0.060315, 0.022495, -0.010308, -0.059037",\ + "0.171476, 0.101933, 0.064692, 0.030941, -0.021156",\ + "0.330098, 0.263569, 0.222296, 0.181197, 0.112987",\ + "0.772581, 0.713134, 0.646673, 0.587289, 0.496722"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.164832, 0.206226, 0.283518, 0.436969, 0.781571",\ + "0.176771, 0.218346, 0.296254, 0.450000, 0.794722",\ + "0.219963, 0.260510, 0.337961, 0.490822, 0.833567",\ + "0.396019, 0.435268, 0.507744, 0.654408, 0.985407",\ + "0.931350, 0.951153, 1.007354, 1.144760, 1.468564"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.015255, 0.029491, 0.060650, 0.100375, 0.176530",\ + "-0.028040, 0.015174, 0.046352, 0.086407, 0.163478",\ + "-0.067695, -0.029062, 0.006032, 0.048125, 0.126390",\ + "-0.170614, -0.143005, -0.113142, -0.070129, 0.016864",\ + "-0.388675, -0.412783, -0.403332, -0.363654, -0.262218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.058687, -0.133819, -0.215174, -0.342668, -0.608913",\ + "-0.070579, -0.145649, -0.226804, -0.353700, -0.618487",\ + "-0.113780, -0.187774, -0.267897, -0.394083, -0.658063",\ + "-0.257059, -0.339271, -0.416614, -0.539608, -0.797794",\ + "-0.613549, -0.743897, -0.832843, -0.961101, -1.220625"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_jen_i[0]_hldr*/ + +} /* end of pin clk_src_sys_jen_i[0] */ +} /* end of bus clk_src_sys_jen_i */ + +pin("clk_src_sys_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.069236 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.009042 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\ + "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\ + "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\ + "1.261778, 1.293108, 1.361483, 1.578982, 2.139170",\ + "1.261778, 1.293108, 1.361483, 1.578982, 2.139170"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\ + "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\ + "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\ + "1.205621, 1.248652, 1.342563, 1.639882, 2.402873",\ + "1.205621, 1.248652, 1.342563, 1.639882, 2.402873"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_o_fedg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\ + "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\ + "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\ + "1.260982, 1.292312, 1.360687, 1.578186, 2.138375",\ + "1.260982, 1.292312, 1.360687, 1.578186, 2.138375"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\ + "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\ + "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\ + "1.203406, 1.246437, 1.340349, 1.637667, 2.400659",\ + "1.203406, 1.246437, 1.340349, 1.637667, 2.400659"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_o_fedg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.165332, 1.196662, 1.265037, 1.482536, 2.042725",\ + "1.244902, 1.276232, 1.344607, 1.562106, 2.122294",\ + "1.324816, 1.356146, 1.424521, 1.642020, 2.202208",\ + "1.454541, 1.485872, 1.554247, 1.771746, 2.331934",\ + "1.654547, 1.685877, 1.754252, 1.971751, 2.531940"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.060530, 1.103561, 1.197473, 1.494792, 2.257783",\ + "1.149702, 1.192733, 1.286645, 1.583964, 2.346955",\ + "1.240645, 1.283676, 1.377588, 1.674906, 2.437898",\ + "1.395684, 1.438715, 1.532626, 1.829945, 2.592937",\ + "1.648565, 1.691596, 1.785508, 2.082827, 2.845818"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.149655, 1.180985, 1.249360, 1.466859, 2.027048",\ + "1.229405, 1.260735, 1.329110, 1.546609, 2.106797",\ + "1.304807, 1.336138, 1.404513, 1.622012, 2.182200",\ + "1.424932, 1.456262, 1.524637, 1.742136, 2.302324",\ + "1.608101, 1.639431, 1.707806, 1.925305, 2.485494"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "1.052743, 1.095775, 1.189686, 1.487005, 2.249996",\ + "1.140331, 1.183362, 1.277273, 1.574592, 2.337583",\ + "1.227129, 1.270160, 1.364072, 1.661390, 2.424382",\ + "1.376376, 1.419407, 1.513318, 1.810637, 2.573628",\ + "1.620792, 1.663824, 1.757735, 2.055053, 2.818045"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166",\ + "0.321380, 0.396761, 0.561274, 1.083463, 2.426166"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_o_una_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970011.625000, 970011.687500, 970011.750000, 970011.937500, 970012.500000",\ + "970011.750000, 970011.812500, 970011.875000, 970012.062500, 970012.625000",\ + "970011.875000, 970011.937500, 970012.000000, 970012.187500, 970012.750000",\ + "970011.875000, 970011.937500, 970012.000000, 970012.187500, 970012.750000",\ + "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970010.187500, 970010.250000, 970010.375000, 970010.625000, 970011.437500",\ + "970010.312500, 970010.375000, 970010.500000, 970010.750000, 970011.562500",\ + "970010.437500, 970010.500000, 970010.625000, 970010.875000, 970011.687500",\ + "970010.437500, 970010.500000, 970010.625000, 970010.875000, 970011.687500",\ + "970010.812500, 970010.875000, 970011.000000, 970011.250000, 970012.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_sys_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.692745, 0.724133, 0.792634, 1.010340, 1.570735",\ + "0.780545, 0.811933, 0.880435, 1.098141, 1.658535",\ + "0.861845, 0.893233, 0.961734, 1.179440, 1.739835",\ + "0.919998, 0.951386, 1.019887, 1.237593, 1.797988",\ + "1.228719, 1.260107, 1.328608, 1.546314, 2.106709"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.771503, 0.814271, 0.907608, 1.204488, 1.969053",\ + "0.859377, 0.902145, 0.995481, 1.292362, 2.056926",\ + "0.953713, 0.996481, 1.089818, 1.386698, 2.151263",\ + "1.021471, 1.064239, 1.157575, 1.454456, 2.219020",\ + "1.382169, 1.424937, 1.518274, 1.815154, 2.579719"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_sys_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970007.000000, 970007.000000, 970007.062500, 970007.312500, 970007.875000",\ + "970007.125000, 970007.125000, 970007.187500, 970007.437500, 970008.000000",\ + "970007.125000, 970007.125000, 970007.187500, 970007.437500, 970008.000000",\ + "970007.375000, 970007.375000, 970007.437500, 970007.687500, 970008.250000",\ + "970007.625000, 970007.625000, 970007.687500, 970007.937500, 970008.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970010.062500, 970010.125000, 970010.250000, 970010.500000, 970011.312500",\ + "970010.187500, 970010.250000, 970010.375000, 970010.625000, 970011.437500",\ + "970010.312500, 970010.375000, 970010.500000, 970010.750000, 970011.562500",\ + "970010.562500, 970010.625000, 970010.750000, 970011.000000, 970011.812500",\ + "970010.812500, 970010.875000, 970011.000000, 970011.250000, 970012.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "380001.281250, 380001.312500, 380001.375000, 380001.593750, 380002.156250",\ + "380001.375000, 380001.406250, 380001.468750, 380001.687500, 380002.250000",\ + "380001.437500, 380001.468750, 380001.531250, 380001.750000, 380002.312500",\ + "380001.593750, 380001.625000, 380001.687500, 380001.906250, 380002.468750",\ + "380001.812500, 380001.843750, 380001.906250, 380002.125000, 380002.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "380002.656250, 380002.718750, 380002.812500, 380003.093750, 380003.875000",\ + "380002.750000, 380002.812500, 380002.906250, 380003.187500, 380003.968750",\ + "380002.843750, 380002.906250, 380003.000000, 380003.281250, 380004.062500",\ + "380003.031250, 380003.093750, 380003.187500, 380003.468750, 380004.250000",\ + "380003.281250, 380003.343750, 380003.437500, 380003.718750, 380004.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970008.250000, 970008.250000, 970008.375000, 970008.687500, 970009.437500",\ + "970008.375000, 970008.375000, 970008.500000, 970008.812500, 970009.562500",\ + "970008.375000, 970008.375000, 970008.500000, 970008.812500, 970009.562500",\ + "970008.625000, 970008.625000, 970008.750000, 970009.062500, 970009.812500",\ + "970008.875000, 970008.875000, 970009.000000, 970009.312500, 970010.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504",\ + "0.319241, 0.394420, 0.558621, 1.081391, 2.429504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "970011.500000, 970011.562500, 970011.625000, 970011.812500, 970012.375000",\ + "970011.625000, 970011.687500, 970011.750000, 970011.937500, 970012.500000",\ + "970011.750000, 970011.812500, 970011.875000, 970012.062500, 970012.625000",\ + "970012.000000, 970012.062500, 970012.125000, 970012.312500, 970012.875000",\ + "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "380000.531250, 380000.562500, 380000.656250, 380000.937500, 380001.718750",\ + "380000.625000, 380000.656250, 380000.750000, 380001.031250, 380001.812500",\ + "380000.687500, 380000.718750, 380000.812500, 380001.093750, 380001.875000",\ + "380000.843750, 380000.875000, 380000.968750, 380001.250000, 380002.031250",\ + "380001.062500, 380001.093750, 380001.187500, 380001.468750, 380002.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166",\ + "0.317826, 0.392935, 0.556854, 1.079626, 2.426166"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "380001.875000, 380001.906250, 380001.968750, 380002.187500, 380002.750000",\ + "380001.968750, 380002.000000, 380002.062500, 380002.281250, 380002.843750",\ + "380002.062500, 380002.093750, 380002.156250, 380002.375000, 380002.937500",\ + "380002.250000, 380002.281250, 380002.343750, 380002.562500, 380003.125000",\ + "380002.500000, 380002.531250, 380002.593750, 380002.812500, 380003.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590009.875000, 590009.937500, 590010.000000, 590010.187500, 590010.750000",\ + "590010.000000, 590010.062500, 590010.125000, 590010.312500, 590010.875000",\ + "590010.000000, 590010.062500, 590010.125000, 590010.312500, 590010.875000",\ + "590010.125000, 590010.187500, 590010.250000, 590010.437500, 590011.000000",\ + "590010.375000, 590010.437500, 590010.500000, 590010.687500, 590011.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590008.000000, 590008.000000, 590008.125000, 590008.437500, 590009.187500",\ + "590008.125000, 590008.125000, 590008.250000, 590008.562500, 590009.312500",\ + "590008.250000, 590008.250000, 590008.375000, 590008.687500, 590009.437500",\ + "590008.375000, 590008.375000, 590008.500000, 590008.812500, 590009.562500",\ + "590008.750000, 590008.750000, 590008.875000, 590009.187500, 590009.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590008.625000, 590008.625000, 590008.687500, 590008.937500, 590009.500000",\ + "590008.625000, 590008.625000, 590008.687500, 590008.937500, 590009.500000",\ + "590008.750000, 590008.750000, 590008.812500, 590009.062500, 590009.625000",\ + "590008.875000, 590008.875000, 590008.937500, 590009.187500, 590009.750000",\ + "590009.125000, 590009.125000, 590009.187500, 590009.437500, 590010.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.312500, 590008.062500",\ + "590007.000000, 590007.062500, 590007.125000, 590007.437500, 590008.187500",\ + "590007.125000, 590007.187500, 590007.250000, 590007.562500, 590008.312500",\ + "590007.250000, 590007.312500, 590007.375000, 590007.687500, 590008.437500",\ + "590007.500000, 590007.562500, 590007.625000, 590007.937500, 590008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590008.437500, 590008.500000, 590008.625000, 590008.875000, 590009.687500",\ + "590008.562500, 590008.625000, 590008.750000, 590009.000000, 590009.812500",\ + "590008.562500, 590008.625000, 590008.750000, 590009.000000, 590009.812500",\ + "590008.687500, 590008.750000, 590008.875000, 590009.125000, 590009.937500",\ + "590008.937500, 590009.000000, 590009.125000, 590009.375000, 590010.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503",\ + "0.319235, 0.394420, 0.558621, 1.081391, 2.429503"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.437500, 590008.000000",\ + "590007.500000, 590007.500000, 590007.562500, 590007.812500, 590008.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878",\ + "0.268551, 0.328271, 0.458604, 0.872597, 1.937878"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590008.437500, 590008.500000, 590008.625000, 590008.875000, 590009.687500",\ + "590008.437500, 590008.500000, 590008.625000, 590008.875000, 590009.687500",\ + "590008.562500, 590008.625000, 590008.750000, 590009.000000, 590009.812500",\ + "590008.687500, 590008.750000, 590008.875000, 590009.125000, 590009.937500",\ + "590008.937500, 590009.000000, 590009.125000, 590009.375000, 590010.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166",\ + "0.319235, 0.394241, 0.557935, 1.080416, 2.426166"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.437500, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.687500, 590008.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.009042, 0.011190, 0.015878, 0.030798, 0.069236"); + values ( "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571",\ + "0.266320, 0.325777, 0.455536, 0.867948, 1.929571"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_o_inv_min*/ + +} /* end of pin clk_src_sys_o */ + +pin("clk_src_sys_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.090214 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002720 ; + + /* Other user defined attributes. */ + original_pin : clk_src_sys_val_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.393375, 0.428628, 0.510890, 0.784879, 1.641015",\ + "0.480773, 0.516025, 0.598287, 0.872277, 1.728413",\ + "0.561620, 0.596872, 0.679134, 0.953123, 1.809259",\ + "0.699752, 0.735005, 0.817267, 1.091256, 1.947392",\ + "0.940296, 0.975559, 1.057603, 1.330256, 2.187617"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\ + "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\ + "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\ + "0.090897, 0.157759, 0.313710, 0.838441, 2.477149",\ + "0.090897, 0.157759, 0.313710, 0.838442, 2.477149"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.432455, 0.458343, 0.517176, 0.707295, 1.304954",\ + "0.519853, 0.545740, 0.604574, 0.794693, 1.392351",\ + "0.600665, 0.626553, 0.685387, 0.875506, 1.473164",\ + "0.738675, 0.764563, 0.823397, 1.013516, 1.611174",\ + "0.958865, 0.984753, 1.043586, 1.233705, 1.831364"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\ + "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\ + "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\ + "0.074157, 0.115650, 0.215819, 0.564523, 1.651598",\ + "0.074157, 0.115650, 0.215819, 0.564523, 1.651598"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.266769, 0.302004, 0.384050, 0.657034, 1.516706",\ + "0.354958, 0.390193, 0.472239, 0.745222, 1.604895",\ + "0.442595, 0.477830, 0.559876, 0.832859, 1.692532",\ + "0.590863, 0.626097, 0.708144, 0.981127, 1.840799",\ + "0.826177, 0.861412, 0.943458, 1.216442, 2.076114"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\ + "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\ + "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\ + "0.090757, 0.157284, 0.313129, 0.831079, 2.456895",\ + "0.090757, 0.157284, 0.313129, 0.831079, 2.456895"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.303512, 0.329439, 0.388317, 0.578409, 1.176194",\ + "0.391701, 0.417628, 0.476506, 0.666598, 1.264383",\ + "0.479338, 0.505265, 0.564143, 0.754235, 1.352020",\ + "0.627605, 0.653533, 0.712411, 0.902503, 1.500287",\ + "0.853156, 0.879043, 0.937890, 1.128062, 1.724915"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\ + "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\ + "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\ + "0.072021, 0.113734, 0.214400, 0.561002, 1.650535",\ + "0.072021, 0.113734, 0.214400, 0.561002, 1.650535"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_redg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.091331, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.274613, 0.222555, 0.182645, 0.164813, 0.160978",\ + "0.311604, 0.259547, 0.219637, 0.201805, 0.197970",\ + "0.350063, 0.298005, 0.258095, 0.240263, 0.236428",\ + "0.426515, 0.374464, 0.334588, 0.316753, 0.312873",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.074152, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.319192, 0.236521, 0.161241, 0.120791, 0.094238",\ + "0.350005, 0.267334, 0.192054, 0.151604, 0.125051",\ + "0.404336, 0.321669, 0.246404, 0.205976, 0.179465",\ + "0.493898, 0.411245, 0.336023, 0.295656, 0.269270",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.683170"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.090757, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.098980, -0.056266, -0.020568, 0.030300, 0.132735",\ + "-0.130504, -0.087736, -0.052066, -0.001191, 0.101296",\ + "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\ + "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.072021, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.133098, -0.057590, 0.008390, 0.100023, 0.282590",\ + "-0.157464, -0.082691, -0.016549, 0.075171, 0.257794",\ + "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\ + "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\ + "-0.787774, -0.712937, -0.646782, -0.554947, -0.372013"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_hldr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.091331, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.404032, 0.352558, 0.318430, 0.316711, 0.351792",\ + "0.438477, 0.387003, 0.352875, 0.351156, 0.386237",\ + "0.480582, 0.429108, 0.394981, 0.393261, 0.428342",\ + "0.577835, 0.526352, 0.492184, 0.490390, 0.525306",\ + "1.061708, 1.010135, 0.975535, 0.972941, 1.006095"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.090757, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.316209, -0.269420, -0.233349, -0.183696, -0.085143",\ + "-0.350428, -0.303639, -0.267567, -0.217915, -0.119361",\ + "-0.392769, -0.345980, -0.309909, -0.260256, -0.161702",\ + "-0.490012, -0.443234, -0.407200, -0.357545, -0.258944",\ + "-0.973610, -0.926934, -0.891298, -0.841646, -0.742588"); + } + + } /* end of arc clk_ast_ext_i_clk_src_sys_val_o_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970010.375000, 970010.437500, 970010.500000, 970010.750000, 970011.625000",\ + "970010.500000, 970010.562500, 970010.625000, 970010.875000, 970011.750000",\ + "970010.625000, 970010.687500, 970010.750000, 970011.000000, 970011.875000",\ + "970010.625000, 970010.687500, 970010.750000, 970011.000000, 970011.875000",\ + "970011.000000, 970011.062500, 970011.125000, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970010.375000, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.500000, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.625000, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.625000, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970011.000000, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_sys_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.735494, 0.770750, 0.853002, 1.126914, 1.983374",\ + "0.823294, 0.858551, 0.940802, 1.214714, 2.071174",\ + "0.904594, 0.939850, 1.022102, 1.296013, 2.152474",\ + "0.962747, 0.998003, 1.080255, 1.354167, 2.210627",\ + "1.271467, 1.306724, 1.388975, 1.662887, 2.519347"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.709749, 0.735637, 0.794488, 0.984673, 1.581583",\ + "0.797549, 0.823438, 0.882288, 1.072473, 1.669383",\ + "0.878849, 0.904737, 0.963588, 1.153773, 1.750682",\ + "0.937002, 0.962891, 1.021741, 1.211926, 1.808836",\ + "1.245723, 1.271611, 1.330462, 1.520647, 2.117556"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_sys_val_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970007.125000, 970007.187500, 970007.250000, 970007.562500, 970008.375000",\ + "970007.250000, 970007.312500, 970007.375000, 970007.687500, 970008.500000",\ + "970007.250000, 970007.312500, 970007.375000, 970007.687500, 970008.500000",\ + "970007.500000, 970007.562500, 970007.625000, 970007.937500, 970008.750000",\ + "970007.750000, 970007.812500, 970007.875000, 970008.187500, 970009.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970010.250000, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\ + "970010.375000, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.500000, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.750000, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\ + "970011.000000, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "380000.500000, 380000.531250, 380000.593750, 380000.875000, 380001.750000",\ + "380000.593750, 380000.625000, 380000.687500, 380000.968750, 380001.843750",\ + "380000.656250, 380000.687500, 380000.750000, 380001.031250, 380001.906250",\ + "380000.812500, 380000.843750, 380000.906250, 380001.187500, 380002.062500",\ + "380001.031250, 380001.062500, 380001.125000, 380001.406250, 380002.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "380001.906250, 380001.937500, 380002.000000, 380002.187500, 380002.781250",\ + "380002.000000, 380002.031250, 380002.093750, 380002.281250, 380002.875000",\ + "380002.093750, 380002.125000, 380002.187500, 380002.375000, 380002.968750",\ + "380002.281250, 380002.312500, 380002.375000, 380002.562500, 380003.156250",\ + "380002.531250, 380002.562500, 380002.625000, 380002.812500, 380003.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970007.187500, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\ + "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.562500, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\ + "970007.812500, 970007.812500, 970007.875000, 970008.062500, 970008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563923, 1.651340"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "970010.250000, 970010.312500, 970010.375000, 970010.625000, 970011.500000",\ + "970010.375000, 970010.437500, 970010.500000, 970010.750000, 970011.625000",\ + "970010.500000, 970010.562500, 970010.625000, 970010.875000, 970011.750000",\ + "970010.750000, 970010.812500, 970010.875000, 970011.125000, 970012.000000",\ + "970011.000000, 970011.062500, 970011.125000, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430",\ + "0.091331, 0.157635, 0.313856, 0.840284, 2.469430"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "380000.531250, 380000.562500, 380000.625000, 380000.812500, 380001.406250",\ + "380000.625000, 380000.656250, 380000.718750, 380000.906250, 380001.500000",\ + "380000.687500, 380000.718750, 380000.781250, 380000.968750, 380001.562500",\ + "380000.843750, 380000.875000, 380000.937500, 380001.125000, 380001.718750",\ + "380001.062500, 380001.093750, 380001.156250, 380001.343750, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196",\ + "0.072027, 0.113736, 0.214396, 0.560990, 1.651196"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "380001.937500, 380001.968750, 380002.062500, 380002.343750, 380003.187500",\ + "380002.031250, 380002.062500, 380002.156250, 380002.437500, 380003.281250",\ + "380002.125000, 380002.156250, 380002.250000, 380002.531250, 380003.375000",\ + "380002.312500, 380002.343750, 380002.437500, 380002.718750, 380003.562500",\ + "380002.562500, 380002.593750, 380002.687500, 380002.968750, 380003.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156",\ + "0.090757, 0.157284, 0.313155, 0.830725, 2.460156"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_sys_val_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590008.625000, 590008.687500, 590008.750000, 590009.000000, 590009.875000",\ + "590008.750000, 590008.812500, 590008.875000, 590009.125000, 590010.000000",\ + "590008.750000, 590008.812500, 590008.875000, 590009.125000, 590010.000000",\ + "590008.875000, 590008.937500, 590009.000000, 590009.250000, 590010.125000",\ + "590009.125000, 590009.187500, 590009.250000, 590009.500000, 590010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590006.937500, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\ + "590007.062500, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\ + "590007.187500, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\ + "590007.312500, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\ + "590007.687500, 590007.687500, 590007.750000, 590007.937500, 590008.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590008.437500, 590008.437500, 590008.562500, 590008.812500, 590009.687500",\ + "590008.437500, 590008.437500, 590008.562500, 590008.812500, 590009.687500",\ + "590008.562500, 590008.562500, 590008.687500, 590008.937500, 590009.812500",\ + "590008.687500, 590008.687500, 590008.812500, 590009.062500, 590009.937500",\ + "590008.937500, 590008.937500, 590009.062500, 590009.312500, 590010.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590006.750000, 590006.812500, 590006.875000, 590007.062500, 590007.625000",\ + "590006.875000, 590006.937500, 590007.000000, 590007.187500, 590007.750000",\ + "590007.000000, 590007.062500, 590007.125000, 590007.312500, 590007.875000",\ + "590007.125000, 590007.187500, 590007.250000, 590007.437500, 590008.000000",\ + "590007.375000, 590007.437500, 590007.500000, 590007.687500, 590008.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590008.625000, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.750000, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.750000, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.875000, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.125000, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340",\ + "0.074152, 0.115602, 0.215213, 0.563930, 1.651340"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.312500, 590008.125000",\ + "590007.000000, 590007.062500, 590007.125000, 590007.437500, 590008.250000",\ + "590007.125000, 590007.187500, 590007.250000, 590007.562500, 590008.375000",\ + "590007.250000, 590007.312500, 590007.375000, 590007.687500, 590008.500000",\ + "590007.625000, 590007.687500, 590007.750000, 590008.062500, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430",\ + "0.091331, 0.157635, 0.313861, 0.840307, 2.469430"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590008.625000, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.625000, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.750000, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.875000, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.125000, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020",\ + "0.072111, 0.113800, 0.214396, 0.559011, 1.650020"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.312500, 590008.125000",\ + "590007.000000, 590007.062500, 590007.125000, 590007.437500, 590008.250000",\ + "590007.125000, 590007.187500, 590007.250000, 590007.562500, 590008.375000",\ + "590007.250000, 590007.312500, 590007.375000, 590007.687500, 590008.500000",\ + "590007.500000, 590007.562500, 590007.625000, 590007.937500, 590008.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002720, 0.005181, 0.010916, 0.030014, 0.090214"); + values ( "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812",\ + "0.090757, 0.157286, 0.312487, 0.829843, 2.465812"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_sys_val_o_inv_min*/ + +} /* end of pin clk_src_sys_val_o */ + +pin("clk_src_aon_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 4.852190 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.018084 ; + + /* Other user defined attributes. */ + original_pin : clk_src_aon_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.829798, 0.861406, 1.030187, 1.471304, 2.111221",\ + "0.918104, 0.949713, 1.118494, 1.559610, 2.199528",\ + "1.006314, 1.037922, 1.206704, 1.647820, 2.287737",\ + "1.155623, 1.187232, 1.356013, 1.797129, 2.437046",\ + "1.394957, 1.426565, 1.595346, 2.036462, 2.676380"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.883488, 0.912350, 1.061245, 1.451119, 2.016701",\ + "0.970887, 0.999749, 1.148644, 1.538518, 2.104100",\ + "1.051701, 1.080563, 1.229459, 1.619333, 2.184914",\ + "1.189711, 1.218573, 1.367469, 1.757343, 2.322925",\ + "1.410200, 1.439062, 1.587957, 1.977831, 2.543413"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033"); + } + + } /* end of arc clk_ast_ext_i_clk_src_aon_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.829665, 0.861273, 1.030054, 1.471171, 2.111088",\ + "0.917971, 0.949579, 1.118361, 1.559477, 2.199394",\ + "1.006180, 1.037788, 1.206569, 1.647686, 2.287603",\ + "1.155489, 1.187097, 1.355879, 1.796995, 2.436912",\ + "1.394823, 1.426431, 1.595212, 2.036328, 2.676246"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.882434, 0.911296, 1.060191, 1.450065, 2.015647",\ + "0.969833, 0.998695, 1.147590, 1.537464, 2.103046",\ + "1.050646, 1.079508, 1.228404, 1.618278, 2.183859",\ + "1.188651, 1.217513, 1.366409, 1.756283, 2.321865",\ + "1.409136, 1.437999, 1.586894, 1.976768, 2.542350"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033",\ + "0.017866, 0.065807, 0.337647, 1.043323, 2.067033"); + } + + } /* end of arc clk_ast_ext_i_clk_src_aon_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970010.562500, 970010.562500, 970010.750000, 970011.187500, 970011.812500",\ + "970010.687500, 970010.687500, 970010.875000, 970011.312500, 970011.937500",\ + "970010.812500, 970010.812500, 970011.000000, 970011.437500, 970012.062500",\ + "970010.812500, 970010.812500, 970011.000000, 970011.437500, 970012.062500",\ + "970011.187500, 970011.187500, 970011.375000, 970011.812500, 970012.437500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970010.375000, 970010.375000, 970010.562500, 970010.937500, 970011.500000",\ + "970010.500000, 970010.500000, 970010.687500, 970011.062500, 970011.625000",\ + "970010.625000, 970010.625000, 970010.812500, 970011.187500, 970011.750000",\ + "970010.625000, 970010.625000, 970010.812500, 970011.187500, 970011.750000",\ + "970011.000000, 970011.000000, 970011.187500, 970011.562500, 970012.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_aon_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.860464, 0.892073, 1.060854, 1.501970, 2.141887",\ + "0.948265, 0.979873, 1.148654, 1.589771, 2.229688",\ + "1.029564, 1.061172, 1.229954, 1.671070, 2.310987",\ + "1.087717, 1.119326, 1.288107, 1.729223, 2.369140",\ + "1.396438, 1.428046, 1.596828, 2.037944, 2.677861"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.970766, 0.999628, 1.148520, 1.538388, 2.103961",\ + "1.058640, 1.087502, 1.236394, 1.626262, 2.191835",\ + "1.152976, 1.181838, 1.330730, 1.720598, 2.286171",\ + "1.220734, 1.249595, 1.398488, 1.788356, 2.353929",\ + "1.581432, 1.610294, 1.759186, 2.149055, 2.714628"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_aon_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970007.187500, 970007.187500, 970007.375000, 970007.812500, 970008.437500",\ + "970007.312500, 970007.312500, 970007.500000, 970007.937500, 970008.562500",\ + "970007.312500, 970007.312500, 970007.500000, 970007.937500, 970008.562500",\ + "970007.562500, 970007.562500, 970007.750000, 970008.187500, 970008.812500",\ + "970007.812500, 970007.812500, 970008.000000, 970008.437500, 970009.062500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970010.250000, 970010.250000, 970010.437500, 970010.812500, 970011.375000",\ + "970010.375000, 970010.375000, 970010.562500, 970010.937500, 970011.500000",\ + "970010.500000, 970010.500000, 970010.687500, 970011.062500, 970011.625000",\ + "970010.750000, 970010.750000, 970010.937500, 970011.312500, 970011.875000",\ + "970011.000000, 970011.000000, 970011.187500, 970011.562500, 970012.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "380008.531250, 380008.562500, 380008.750000, 380009.187500, 380009.812500",\ + "380008.625000, 380008.656250, 380008.843750, 380009.281250, 380009.906250",\ + "380008.687500, 380008.718750, 380008.906250, 380009.343750, 380009.968750",\ + "380008.843750, 380008.875000, 380009.062500, 380009.500000, 380010.125000",\ + "380009.062500, 380009.093750, 380009.281250, 380009.718750, 380010.343750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "380007.906250, 380007.906250, 380008.062500, 380008.468750, 380009.031250",\ + "380008.000000, 380008.000000, 380008.156250, 380008.562500, 380009.125000",\ + "380008.093750, 380008.093750, 380008.250000, 380008.656250, 380009.218750",\ + "380008.281250, 380008.281250, 380008.437500, 380008.843750, 380009.406250",\ + "380008.531250, 380008.531250, 380008.687500, 380009.093750, 380009.656250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970007.437500, 970007.437500, 970007.625000, 970008.000000, 970008.562500",\ + "970007.562500, 970007.562500, 970007.750000, 970008.125000, 970008.687500",\ + "970007.562500, 970007.562500, 970007.750000, 970008.125000, 970008.687500",\ + "970007.812500, 970007.812500, 970008.000000, 970008.375000, 970008.937500",\ + "970008.062500, 970008.062500, 970008.250000, 970008.625000, 970009.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "970010.437500, 970010.437500, 970010.625000, 970011.062500, 970011.687500",\ + "970010.562500, 970010.562500, 970010.750000, 970011.187500, 970011.812500",\ + "970010.687500, 970010.687500, 970010.875000, 970011.312500, 970011.937500",\ + "970010.937500, 970010.937500, 970011.125000, 970011.562500, 970012.187500",\ + "970011.187500, 970011.187500, 970011.375000, 970011.812500, 970012.437500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "380000.750000, 380000.750000, 380000.906250, 380001.312500, 380001.875000",\ + "380000.843750, 380000.843750, 380001.000000, 380001.406250, 380001.968750",\ + "380000.906250, 380000.906250, 380001.062500, 380001.468750, 380002.031250",\ + "380001.062500, 380001.062500, 380001.218750, 380001.625000, 380002.187500",\ + "380001.281250, 380001.281250, 380001.437500, 380001.843750, 380002.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043",\ + "0.017866, 0.065808, 0.337669, 1.043341, 2.067043"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "380002.031250, 380002.062500, 380002.250000, 380002.687500, 380003.312500",\ + "380002.125000, 380002.156250, 380002.343750, 380002.781250, 380003.406250",\ + "380002.218750, 380002.250000, 380002.437500, 380002.875000, 380003.500000",\ + "380002.406250, 380002.437500, 380002.625000, 380003.062500, 380003.687500",\ + "380002.656250, 380002.687500, 380002.875000, 380003.312500, 380003.937500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523",\ + "0.018689, 0.076907, 0.397582, 1.240182, 2.462523"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590008.812500, 590008.812500, 590009.000000, 590009.437500, 590010.062500",\ + "590008.937500, 590008.937500, 590009.125000, 590009.562500, 590010.187500",\ + "590008.937500, 590008.937500, 590009.125000, 590009.562500, 590010.187500",\ + "590009.062500, 590009.062500, 590009.250000, 590009.687500, 590010.312500",\ + "590009.312500, 590009.312500, 590009.500000, 590009.937500, 590010.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590007.187500, 590007.187500, 590007.375000, 590007.750000, 590008.312500",\ + "590007.312500, 590007.312500, 590007.500000, 590007.875000, 590008.437500",\ + "590007.437500, 590007.437500, 590007.625000, 590008.000000, 590008.562500",\ + "590007.562500, 590007.562500, 590007.750000, 590008.125000, 590008.687500",\ + "590007.937500, 590007.937500, 590008.125000, 590008.500000, 590009.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590008.812500, 590008.812500, 590009.000000, 590009.437500, 590010.062500",\ + "590008.812500, 590008.812500, 590009.000000, 590009.437500, 590010.062500",\ + "590008.937500, 590008.937500, 590009.125000, 590009.562500, 590010.187500",\ + "590009.062500, 590009.062500, 590009.250000, 590009.687500, 590010.312500",\ + "590009.312500, 590009.312500, 590009.500000, 590009.937500, 590010.562500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590007.187500, 590007.187500, 590007.375000, 590007.750000, 590008.312500",\ + "590007.312500, 590007.312500, 590007.500000, 590007.875000, 590008.437500",\ + "590007.437500, 590007.437500, 590007.625000, 590008.000000, 590008.562500",\ + "590007.562500, 590007.562500, 590007.750000, 590008.125000, 590008.687500",\ + "590007.812500, 590007.812500, 590008.000000, 590008.375000, 590008.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590008.625000, 590008.625000, 590008.812500, 590009.187500, 590009.750000",\ + "590008.750000, 590008.750000, 590008.937500, 590009.312500, 590009.875000",\ + "590008.750000, 590008.750000, 590008.937500, 590009.312500, 590009.875000",\ + "590008.875000, 590008.875000, 590009.062500, 590009.437500, 590010.000000",\ + "590009.125000, 590009.125000, 590009.312500, 590009.687500, 590010.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039",\ + "0.017866, 0.065807, 0.337660, 1.043334, 2.067039"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590006.937500, 590006.937500, 590007.125000, 590007.562500, 590008.187500",\ + "590007.062500, 590007.062500, 590007.250000, 590007.687500, 590008.312500",\ + "590007.187500, 590007.187500, 590007.375000, 590007.812500, 590008.437500",\ + "590007.312500, 590007.312500, 590007.500000, 590007.937500, 590008.562500",\ + "590007.687500, 590007.687500, 590007.875000, 590008.312500, 590008.937500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535",\ + "0.018690, 0.076907, 0.397572, 1.240181, 2.462535"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590008.625000, 590008.625000, 590008.812500, 590009.187500, 590009.750000",\ + "590008.625000, 590008.625000, 590008.812500, 590009.187500, 590009.750000",\ + "590008.750000, 590008.750000, 590008.937500, 590009.312500, 590009.875000",\ + "590008.875000, 590008.875000, 590009.062500, 590009.437500, 590010.000000",\ + "590009.125000, 590009.125000, 590009.312500, 590009.687500, 590010.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040",\ + "0.017866, 0.065808, 0.337663, 1.043336, 2.067040"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "590006.937500, 590006.937500, 590007.125000, 590007.562500, 590008.187500",\ + "590007.062500, 590007.062500, 590007.250000, 590007.687500, 590008.312500",\ + "590007.187500, 590007.187500, 590007.375000, 590007.812500, 590008.437500",\ + "590007.312500, 590007.312500, 590007.500000, 590007.937500, 590008.562500",\ + "590007.562500, 590007.562500, 590007.750000, 590008.187500, 590008.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.018084, 0.134289, 0.768982, 2.435137, 4.852190"); + values ( "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529",\ + "0.018689, 0.076907, 0.397577, 1.240181, 2.462529"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_o_inv_min*/ + +} /* end of pin clk_src_aon_o */ + +pin("clk_src_aon_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.090214 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : clk_src_aon_val_o; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970010.375000, 970010.375000, 970010.500000, 970010.750000, 970011.625000",\ + "970010.500000, 970010.500000, 970010.625000, 970010.875000, 970011.750000",\ + "970010.625000, 970010.625000, 970010.750000, 970011.000000, 970011.875000",\ + "970010.625000, 970010.625000, 970010.750000, 970011.000000, 970011.875000",\ + "970011.000000, 970011.000000, 970011.125000, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_aon_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.710726, 0.747218, 0.829413, 1.103529, 1.981775",\ + "0.798527, 0.835019, 0.917213, 1.191329, 2.069575",\ + "0.879826, 0.916318, 0.998513, 1.272629, 2.150875",\ + "0.937979, 0.974471, 1.056666, 1.330782, 2.209028",\ + "1.246700, 1.283192, 1.365386, 1.639502, 2.517748"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.688713, 0.718170, 0.777854, 0.968115, 1.580205",\ + "0.776513, 0.805970, 0.865655, 1.055915, 1.668005",\ + "0.857813, 0.887270, 0.946954, 1.137214, 1.749305",\ + "0.915966, 0.945423, 1.005107, 1.195368, 1.807458",\ + "1.224687, 1.254144, 1.313828, 1.504088, 2.116179"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_aon_val_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970007.125000, 970007.125000, 970007.250000, 970007.500000, 970008.375000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.500000, 970007.500000, 970007.625000, 970007.875000, 970008.750000",\ + "970007.750000, 970007.750000, 970007.875000, 970008.125000, 970009.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "380000.468750, 380000.500000, 380000.593750, 380000.843750, 380001.750000",\ + "380000.562500, 380000.593750, 380000.687500, 380000.937500, 380001.843750",\ + "380000.625000, 380000.656250, 380000.750000, 380001.000000, 380001.906250",\ + "380000.781250, 380000.812500, 380000.906250, 380001.156250, 380002.062500",\ + "380001.000000, 380001.031250, 380001.125000, 380001.375000, 380002.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "380001.906250, 380001.937500, 380002.000000, 380002.187500, 380002.781250",\ + "380002.000000, 380002.031250, 380002.093750, 380002.281250, 380002.875000",\ + "380002.093750, 380002.125000, 380002.187500, 380002.375000, 380002.968750",\ + "380002.281250, 380002.312500, 380002.375000, 380002.562500, 380003.156250",\ + "380002.531250, 380002.562500, 380002.625000, 380002.812500, 380003.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970007.187500, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\ + "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.312500, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.562500, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\ + "970007.812500, 970007.812500, 970007.875000, 970008.062500, 970008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536743, 1.653005"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "970010.250000, 970010.250000, 970010.375000, 970010.625000, 970011.500000",\ + "970010.375000, 970010.375000, 970010.500000, 970010.750000, 970011.625000",\ + "970010.500000, 970010.500000, 970010.625000, 970010.875000, 970011.750000",\ + "970010.750000, 970010.750000, 970010.875000, 970011.125000, 970012.000000",\ + "970011.000000, 970011.000000, 970011.125000, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799035, 2.469430"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "380000.500000, 380000.531250, 380000.593750, 380000.781250, 380001.406250",\ + "380000.593750, 380000.625000, 380000.687500, 380000.875000, 380001.500000",\ + "380000.656250, 380000.687500, 380000.750000, 380000.937500, 380001.562500",\ + "380000.812500, 380000.843750, 380000.906250, 380001.093750, 380001.718750",\ + "380001.031250, 380001.062500, 380001.125000, 380001.312500, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611",\ + "0.046907, 0.088182, 0.186999, 0.533681, 1.651611"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "380001.906250, 380001.968750, 380002.031250, 380002.312500, 380003.187500",\ + "380002.000000, 380002.062500, 380002.125000, 380002.406250, 380003.281250",\ + "380002.093750, 380002.156250, 380002.218750, 380002.500000, 380003.375000",\ + "380002.281250, 380002.343750, 380002.406250, 380002.687500, 380003.562500",\ + "380002.531250, 380002.593750, 380002.656250, 380002.937500, 380003.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133",\ + "0.051468, 0.115906, 0.271423, 0.789292, 2.460133"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_aon_val_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590008.625000, 590008.625000, 590008.750000, 590009.000000, 590009.875000",\ + "590008.750000, 590008.750000, 590008.875000, 590009.125000, 590010.000000",\ + "590008.750000, 590008.750000, 590008.875000, 590009.125000, 590010.000000",\ + "590008.875000, 590008.875000, 590009.000000, 590009.250000, 590010.125000",\ + "590009.125000, 590009.125000, 590009.250000, 590009.500000, 590010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590006.937500, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\ + "590007.062500, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\ + "590007.187500, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\ + "590007.312500, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\ + "590007.687500, 590007.687500, 590007.750000, 590007.937500, 590008.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590008.437500, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.437500, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.562500, 590008.562500, 590008.625000, 590008.937500, 590009.812500",\ + "590008.687500, 590008.687500, 590008.750000, 590009.062500, 590009.937500",\ + "590008.937500, 590008.937500, 590009.000000, 590009.312500, 590010.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.000000, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.125000, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.250000, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.375000, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.625000, 590008.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005",\ + "0.049199, 0.090220, 0.188113, 0.536750, 1.653005"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.625000, 590007.625000, 590007.750000, 590008.000000, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430",\ + "0.051936, 0.116244, 0.271542, 0.799058, 2.469430"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439",\ + "0.046941, 0.088258, 0.187000, 0.531185, 1.650439"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.500000, 590007.500000, 590007.625000, 590007.875000, 590008.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001189, 0.003650, 0.009385, 0.028484, 0.090214"); + values ( "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855",\ + "0.051557, 0.115907, 0.271016, 0.788173, 2.465855"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_aon_val_o_inv_min*/ + +} /* end of pin clk_src_aon_val_o */ + +pin("clk_src_io_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002154 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_en_i; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.271588, 0.219415, 0.179927, 0.162045, 0.157577",\ + "0.363033, 0.310027, 0.270334, 0.252385, 0.247965",\ + "0.507780, 0.454308, 0.413646, 0.395357, 0.391106",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.324602, 0.241857, 0.166855, 0.126539, 0.100040",\ + "0.429418, 0.345854, 0.270221, 0.227986, 0.196782",\ + "0.605833, 0.521783, 0.445878, 0.397956, 0.350944",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_en_i_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\ + "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\ + "-0.373429, -0.330963, -0.299719, -0.251733, -0.152256",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\ + "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\ + "-0.470591, -0.397956, -0.329423, -0.234665, -0.046227",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_en_i_hldr*/ + +} /* end of pin clk_src_io_en_i */ + +pin("clk_src_io_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.069236 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.028657 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\ + "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\ + "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\ + "1.549102, 1.558939, 1.580409, 1.648733, 2.140488",\ + "1.549102, 1.558939, 1.580409, 1.648733, 2.140488"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\ + "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\ + "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\ + "1.576328, 1.589726, 1.618968, 1.712027, 2.381811",\ + "1.576328, 1.589726, 1.618968, 1.712027, 2.381811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_o_fedg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\ + "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\ + "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\ + "1.548301, 1.558138, 1.579608, 1.647932, 2.139687",\ + "1.548301, 1.558138, 1.579608, 1.647932, 2.139687"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\ + "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\ + "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\ + "1.574098, 1.587497, 1.616739, 1.709798, 2.379581",\ + "1.574098, 1.587497, 1.616739, 1.709798, 2.379581"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_o_fedg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.452656, 1.462494, 1.483963, 1.552287, 2.044042",\ + "1.532226, 1.542063, 1.563532, 1.631856, 2.123611",\ + "1.612140, 1.621977, 1.643447, 1.711771, 2.203526",\ + "1.741866, 1.751703, 1.773172, 1.841496, 2.333251",\ + "1.941871, 1.951709, 1.973178, 2.041502, 2.533257"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.431237, 1.444636, 1.473878, 1.566937, 2.236720",\ + "1.520409, 1.533808, 1.563050, 1.656109, 2.325892",\ + "1.611352, 1.624751, 1.653993, 1.747052, 2.416835",\ + "1.766391, 1.779789, 1.809031, 1.902090, 2.571874",\ + "2.019272, 2.032671, 2.061913, 2.154972, 2.824755"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044609, 1.208373, 2.387050"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.436974, 1.446811, 1.468281, 1.536605, 2.028360",\ + "1.516723, 1.526561, 1.548030, 1.616354, 2.108109",\ + "1.592126, 1.601964, 1.623433, 1.691757, 2.183512",\ + "1.712250, 1.722088, 1.743557, 1.811881, 2.303636",\ + "1.895420, 1.905257, 1.926727, 1.995051, 2.486806"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.423435, 1.436834, 1.466076, 1.559135, 2.228919",\ + "1.511023, 1.524422, 1.553663, 1.646723, 2.316506",\ + "1.597821, 1.611220, 1.640462, 1.733521, 2.403305",\ + "1.747068, 1.760467, 1.789708, 1.882767, 2.552551",\ + "1.991484, 2.004883, 2.034125, 2.127184, 2.796968"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050",\ + "0.969570, 0.993149, 1.044608, 1.208373, 2.387050"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_o_una_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970011.937500, 970011.937500, 970011.937500, 970012.062500, 970012.500000",\ + "970012.062500, 970012.062500, 970012.062500, 970012.187500, 970012.625000",\ + "970012.187500, 970012.187500, 970012.187500, 970012.312500, 970012.750000",\ + "970012.187500, 970012.187500, 970012.187500, 970012.312500, 970012.750000",\ + "970012.562500, 970012.562500, 970012.562500, 970012.687500, 970013.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970010.562500, 970010.625000, 970010.625000, 970010.687500, 970011.375000",\ + "970010.687500, 970010.750000, 970010.750000, 970010.812500, 970011.500000",\ + "970010.812500, 970010.875000, 970010.875000, 970010.937500, 970011.625000",\ + "970010.812500, 970010.875000, 970010.875000, 970010.937500, 970011.625000",\ + "970011.187500, 970011.250000, 970011.250000, 970011.312500, 970012.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_io_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.979131, 0.988972, 1.010450, 1.078799, 1.570735",\ + "1.066932, 1.076773, 1.098250, 1.166599, 1.658535",\ + "1.148231, 1.158072, 1.179549, 1.247899, 1.739835",\ + "1.206384, 1.216226, 1.237703, 1.306052, 1.797988",\ + "1.515105, 1.524946, 1.546423, 1.614772, 2.106709"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "1.139635, 1.153062, 1.182364, 1.275615, 1.946779",\ + "1.227509, 1.240935, 1.270237, 1.363488, 2.034653",\ + "1.321845, 1.335272, 1.364574, 1.457825, 2.128989",\ + "1.389603, 1.403029, 1.432331, 1.525582, 2.196747",\ + "1.750301, 1.763728, 1.793030, 1.886281, 2.557446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_io_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970007.250000, 970007.250000, 970007.312500, 970007.375000, 970007.875000",\ + "970007.375000, 970007.375000, 970007.437500, 970007.500000, 970008.000000",\ + "970007.375000, 970007.375000, 970007.437500, 970007.500000, 970008.000000",\ + "970007.625000, 970007.625000, 970007.687500, 970007.750000, 970008.250000",\ + "970007.875000, 970007.875000, 970007.937500, 970008.000000, 970008.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970010.437500, 970010.500000, 970010.500000, 970010.562500, 970011.250000",\ + "970010.562500, 970010.625000, 970010.625000, 970010.687500, 970011.375000",\ + "970010.687500, 970010.750000, 970010.750000, 970010.812500, 970011.500000",\ + "970010.937500, 970011.000000, 970011.000000, 970011.062500, 970011.750000",\ + "970011.187500, 970011.250000, 970011.250000, 970011.312500, 970012.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "380001.562500, 380001.593750, 380001.593750, 380001.687500, 380002.156250",\ + "380001.656250, 380001.687500, 380001.687500, 380001.781250, 380002.250000",\ + "380001.718750, 380001.750000, 380001.750000, 380001.843750, 380002.312500",\ + "380001.875000, 380001.906250, 380001.906250, 380002.000000, 380002.468750",\ + "380002.093750, 380002.125000, 380002.125000, 380002.218750, 380002.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "380003.031250, 380003.062500, 380003.093750, 380003.187500, 380003.843750",\ + "380003.125000, 380003.156250, 380003.187500, 380003.281250, 380003.937500",\ + "380003.218750, 380003.250000, 380003.281250, 380003.375000, 380004.031250",\ + "380003.406250, 380003.437500, 380003.468750, 380003.562500, 380004.218750",\ + "380003.656250, 380003.687500, 380003.718750, 380003.812500, 380004.468750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970008.625000, 970008.625000, 970008.625000, 970008.750000, 970009.437500",\ + "970008.750000, 970008.750000, 970008.750000, 970008.875000, 970009.562500",\ + "970008.750000, 970008.750000, 970008.750000, 970008.875000, 970009.562500",\ + "970009.000000, 970009.000000, 970009.000000, 970009.125000, 970009.812500",\ + "970009.250000, 970009.250000, 970009.250000, 970009.375000, 970010.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390203"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "970011.812500, 970011.812500, 970011.812500, 970011.937500, 970012.375000",\ + "970011.937500, 970011.937500, 970011.937500, 970012.062500, 970012.500000",\ + "970012.062500, 970012.062500, 970012.062500, 970012.187500, 970012.625000",\ + "970012.312500, 970012.312500, 970012.312500, 970012.437500, 970012.875000",\ + "970012.562500, 970012.562500, 970012.562500, 970012.687500, 970013.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "380000.875000, 380000.906250, 380000.937500, 380001.031250, 380001.687500",\ + "380000.968750, 380001.000000, 380001.031250, 380001.125000, 380001.781250",\ + "380001.031250, 380001.062500, 380001.093750, 380001.187500, 380001.843750",\ + "380001.187500, 380001.218750, 380001.250000, 380001.343750, 380002.000000",\ + "380001.406250, 380001.437500, 380001.468750, 380001.562500, 380002.218750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050",\ + "0.965198, 0.988888, 1.040589, 1.205123, 2.387050"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "380002.156250, 380002.187500, 380002.187500, 380002.281250, 380002.750000",\ + "380002.250000, 380002.281250, 380002.281250, 380002.375000, 380002.843750",\ + "380002.343750, 380002.375000, 380002.375000, 380002.468750, 380002.937500",\ + "380002.531250, 380002.562500, 380002.562500, 380002.656250, 380003.125000",\ + "380002.781250, 380002.812500, 380002.812500, 380002.906250, 380003.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590010.187500, 590010.187500, 590010.187500, 590010.312500, 590010.750000",\ + "590010.312500, 590010.312500, 590010.312500, 590010.437500, 590010.875000",\ + "590010.312500, 590010.312500, 590010.312500, 590010.437500, 590010.875000",\ + "590010.437500, 590010.437500, 590010.437500, 590010.562500, 590011.000000",\ + "590010.687500, 590010.687500, 590010.687500, 590010.812500, 590011.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590008.375000, 590008.375000, 590008.375000, 590008.500000, 590009.187500",\ + "590008.500000, 590008.500000, 590008.500000, 590008.625000, 590009.312500",\ + "590008.625000, 590008.625000, 590008.625000, 590008.750000, 590009.437500",\ + "590008.750000, 590008.750000, 590008.750000, 590008.875000, 590009.562500",\ + "590009.125000, 590009.125000, 590009.125000, 590009.250000, 590009.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590008.875000, 590008.875000, 590008.937500, 590009.000000, 590009.500000",\ + "590008.875000, 590008.875000, 590008.937500, 590009.000000, 590009.500000",\ + "590009.000000, 590009.000000, 590009.062500, 590009.125000, 590009.625000",\ + "590009.125000, 590009.125000, 590009.187500, 590009.250000, 590009.750000",\ + "590009.375000, 590009.375000, 590009.437500, 590009.500000, 590010.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590007.250000, 590007.250000, 590007.312500, 590007.375000, 590008.062500",\ + "590007.375000, 590007.375000, 590007.437500, 590007.500000, 590008.187500",\ + "590007.500000, 590007.500000, 590007.562500, 590007.625000, 590008.312500",\ + "590007.625000, 590007.625000, 590007.687500, 590007.750000, 590008.437500",\ + "590007.875000, 590007.875000, 590007.937500, 590008.000000, 590008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590008.812500, 590008.875000, 590008.875000, 590008.937500, 590009.625000",\ + "590008.937500, 590009.000000, 590009.000000, 590009.062500, 590009.750000",\ + "590008.937500, 590009.000000, 590009.000000, 590009.062500, 590009.750000",\ + "590009.062500, 590009.125000, 590009.125000, 590009.187500, 590009.875000",\ + "590009.312500, 590009.375000, 590009.375000, 590009.437500, 590010.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202",\ + "0.967112, 0.990771, 1.042405, 1.206725, 2.390202"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590007.000000, 590007.000000, 590007.062500, 590007.125000, 590007.625000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.250000, 590007.750000",\ + "590007.250000, 590007.250000, 590007.312500, 590007.375000, 590007.875000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.500000, 590008.000000",\ + "590007.750000, 590007.750000, 590007.812500, 590007.875000, 590008.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878",\ + "0.813271, 0.831978, 0.872805, 1.002733, 1.937878"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590008.812500, 590008.875000, 590008.875000, 590008.937500, 590009.625000",\ + "590008.812500, 590008.875000, 590008.875000, 590008.937500, 590009.625000",\ + "590008.937500, 590009.000000, 590009.000000, 590009.062500, 590009.750000",\ + "590009.062500, 590009.125000, 590009.125000, 590009.187500, 590009.875000",\ + "590009.312500, 590009.375000, 590009.375000, 590009.437500, 590010.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050",\ + "0.965982, 0.989673, 1.041377, 1.205920, 2.387050"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "590007.000000, 590007.000000, 590007.062500, 590007.125000, 590007.625000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.250000, 590007.750000",\ + "590007.250000, 590007.250000, 590007.312500, 590007.375000, 590007.875000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.500000, 590008.000000",\ + "590007.625000, 590007.625000, 590007.687500, 590007.750000, 590008.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028657, 0.029332, 0.030805, 0.035494, 0.069236"); + values ( "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571",\ + "0.808825, 0.827468, 0.868155, 0.997637, 1.929571"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_o_inv_min*/ + +} /* end of pin clk_src_io_o */ + +pin("clk_src_io_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.090214 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_val_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.349435, 0.390046, 0.472189, 0.746558, 1.641427",\ + "0.436833, 0.477444, 0.559587, 0.833956, 1.728824",\ + "0.517679, 0.558291, 0.640433, 0.914803, 1.809671",\ + "0.655812, 0.696423, 0.778566, 1.052935, 1.947804",\ + "0.895822, 0.936589, 1.018755, 1.291518, 2.187617"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\ + "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\ + "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\ + "0.023045, 0.083902, 0.239677, 0.764755, 2.477069",\ + "0.023045, 0.083902, 0.239677, 0.764756, 2.477069"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.392641, 0.430353, 0.490673, 0.680876, 1.305538",\ + "0.480039, 0.517751, 0.578071, 0.768273, 1.392936",\ + "0.560851, 0.598563, 0.658884, 0.849086, 1.473748",\ + "0.698861, 0.736574, 0.796894, 0.987096, 1.611758",\ + "0.919051, 0.956763, 1.017083, 1.207286, 1.831948"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\ + "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\ + "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\ + "0.028953, 0.070788, 0.167469, 0.516472, 1.652650",\ + "0.028953, 0.070788, 0.167469, 0.516472, 1.652650"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.222488, 0.262832, 0.344930, 0.617962, 1.516487",\ + "0.310677, 0.351020, 0.433119, 0.706150, 1.604676",\ + "0.398314, 0.438657, 0.520756, 0.793787, 1.692313",\ + "0.546582, 0.586925, 0.669023, 0.942055, 1.840581",\ + "0.781897, 0.822240, 0.904338, 1.177370, 2.075895"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\ + "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\ + "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\ + "0.021529, 0.083764, 0.238778, 0.757629, 2.456834",\ + "0.021529, 0.083764, 0.238778, 0.757629, 2.456834"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.263406, 0.301157, 0.361570, 0.551735, 1.176520",\ + "0.351595, 0.389345, 0.449758, 0.639924, 1.264709",\ + "0.439232, 0.476982, 0.537395, 0.727561, 1.352346",\ + "0.587500, 0.625250, 0.685663, 0.875828, 1.500613",\ + "0.814247, 0.851409, 0.911729, 1.102035, 1.725865"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\ + "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\ + "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\ + "0.025912, 0.068635, 0.165828, 0.512808, 1.651582",\ + "0.025912, 0.068635, 0.165828, 0.512808, 1.651582"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_val_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\ + "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\ + "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_io_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.691562, 0.732168, 0.814319, 1.088582, 1.983787",\ + "0.779362, 0.819968, 0.902120, 1.176383, 2.071587",\ + "0.860662, 0.901268, 0.983419, 1.257682, 2.152886",\ + "0.918815, 0.959421, 1.041572, 1.315835, 2.211040",\ + "1.227535, 1.268142, 1.350293, 1.624556, 2.519760"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.670852, 0.708006, 0.768329, 0.958648, 1.582536",\ + "0.758652, 0.795807, 0.856129, 1.046448, 1.670336",\ + "0.839952, 0.877106, 0.937428, 1.127748, 1.751636",\ + "0.898105, 0.935259, 0.995582, 1.185901, 1.809789",\ + "1.206825, 1.243980, 1.304302, 1.494621, 2.118509"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_io_val_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970007.125000, 970007.125000, 970007.250000, 970007.500000, 970008.375000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.500000, 970007.500000, 970007.625000, 970007.875000, 970008.750000",\ + "970007.750000, 970007.750000, 970007.875000, 970008.125000, 970009.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380000.437500, 380000.500000, 380000.562500, 380000.843750, 380001.750000",\ + "380000.531250, 380000.593750, 380000.656250, 380000.937500, 380001.843750",\ + "380000.593750, 380000.656250, 380000.718750, 380001.000000, 380001.906250",\ + "380000.750000, 380000.812500, 380000.875000, 380001.156250, 380002.062500",\ + "380000.968750, 380001.031250, 380001.093750, 380001.375000, 380002.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380001.875000, 380001.906250, 380001.968750, 380002.156250, 380002.781250",\ + "380001.968750, 380002.000000, 380002.062500, 380002.250000, 380002.875000",\ + "380002.062500, 380002.093750, 380002.156250, 380002.343750, 380002.968750",\ + "380002.250000, 380002.281250, 380002.343750, 380002.531250, 380003.156250",\ + "380002.500000, 380002.531250, 380002.593750, 380002.781250, 380003.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970007.125000, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\ + "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.500000, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\ + "970007.750000, 970007.812500, 970007.875000, 970008.062500, 970008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515896, 1.652424"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.625000, 970011.500000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.125000, 970012.000000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430",\ + "0.022870, 0.084359, 0.238855, 0.766786, 2.469430"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380000.500000, 380000.531250, 380000.593750, 380000.781250, 380001.406250",\ + "380000.593750, 380000.625000, 380000.687500, 380000.875000, 380001.500000",\ + "380000.656250, 380000.687500, 380000.750000, 380000.937500, 380001.562500",\ + "380000.812500, 380000.843750, 380000.906250, 380001.093750, 380001.718750",\ + "380001.031250, 380001.062500, 380001.125000, 380001.312500, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262",\ + "0.025902, 0.068641, 0.165825, 0.512797, 1.652262"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380001.906250, 380001.937500, 380002.031250, 380002.281250, 380003.187500",\ + "380002.000000, 380002.031250, 380002.125000, 380002.375000, 380003.281250",\ + "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\ + "380002.281250, 380002.312500, 380002.406250, 380002.656250, 380003.562500",\ + "380002.531250, 380002.562500, 380002.656250, 380002.906250, 380003.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111",\ + "0.021561, 0.083764, 0.238778, 0.757109, 2.460111"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_io_val_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590009.000000, 590009.875000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.250000, 590010.125000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.500000, 590010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\ + "590007.000000, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\ + "590007.125000, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\ + "590007.250000, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\ + "590007.625000, 590007.687500, 590007.750000, 590007.937500, 590008.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.500000, 590008.562500, 590008.625000, 590008.937500, 590009.812500",\ + "590008.625000, 590008.687500, 590008.750000, 590009.062500, 590009.937500",\ + "590008.875000, 590008.937500, 590009.000000, 590009.312500, 590010.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.000000, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.125000, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.250000, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.375000, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.625000, 590008.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424",\ + "0.028495, 0.070786, 0.167370, 0.515903, 1.652424"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.625000, 590007.625000, 590007.750000, 590008.000000, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430",\ + "0.022871, 0.084359, 0.238855, 0.766810, 2.469430"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078",\ + "0.026015, 0.068726, 0.165865, 0.510718, 1.651078"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.500000, 590007.500000, 590007.625000, 590007.875000, 590008.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788",\ + "0.022032, 0.083764, 0.238625, 0.755849, 2.465788"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_io_val_o_inv_min*/ + +} /* end of pin clk_src_io_val_o */ +bus ( clk_src_io_48m_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("clk_src_io_48m_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_48m_o[3]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[3]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[3]_redg_min*/ + +} /* end of pin clk_src_io_48m_o[3] */ + +pin("clk_src_io_48m_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_48m_o[2]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[2]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[2]_redg_min*/ + +} /* end of pin clk_src_io_48m_o[2] */ + +pin("clk_src_io_48m_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_48m_o[1]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[1]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[1]_redg_min*/ + +} /* end of pin clk_src_io_48m_o[1] */ + +pin("clk_src_io_48m_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_io_48m_o[0]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_clk_src_io_48m_o[0]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_clk_src_io_48m_o[0]_redg_min*/ + +} /* end of pin clk_src_io_48m_o[0] */ +} /* end of bus clk_src_io_48m_o */ + +pin("usb_ref_pulse_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000498 ; + + /* Other user defined attributes. */ + original_pin : usb_ref_pulse_i; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.601598, 0.562432, 0.511802, 0.512897, 0.526214",\ + "0.685611, 0.646445, 0.595815, 0.596911, 0.610227",\ + "0.776643, 0.737477, 0.686847, 0.687943, 0.701259",\ + "0.941188, 0.902022, 0.851392, 0.852488, 0.865804",\ + "1.218007, 1.178841, 1.128211, 1.129307, 1.142623"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.502275, 0.444594, 0.389492, 0.390588, 0.403904",\ + "0.590200, 0.532519, 0.477417, 0.478513, 0.491829",\ + "0.690598, 0.632917, 0.577816, 0.578911, 0.592227",\ + "0.875082, 0.817401, 0.762299, 0.763395, 0.776711",\ + "1.192023, 1.134342, 1.079240, 1.080336, 1.093652"); + } + + } /* end of arc clk_ast_usb_i_usb_ref_pulse_i_stupr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.289933, -0.256850, -0.198215, -0.184587, -0.018969",\ + "-0.373947, -0.340864, -0.282229, -0.268602, -0.102983",\ + "-0.464983, -0.431900, -0.373265, -0.359637, -0.194019",\ + "-0.629535, -0.596452, -0.537817, -0.524189, -0.358571",\ + "-0.906192, -0.873109, -0.814474, -0.800846, -0.635228"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.244346, -0.193347, -0.096886, -0.078739, 0.141805",\ + "-0.332296, -0.281297, -0.184836, -0.166688, 0.053856",\ + "-0.432681, -0.381682, -0.285221, -0.267073, -0.046529",\ + "-0.616949, -0.565951, -0.469489, -0.451342, -0.230798",\ + "-0.933995, -0.882996, -0.786535, -0.768387, -0.547843"); + } + + } /* end of arc clk_ast_usb_i_usb_ref_pulse_i_hldr*/ + +} /* end of pin usb_ref_pulse_i */ + +pin("usb_ref_val_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000622 ; + + /* Other user defined attributes. */ + original_pin : usb_ref_val_i; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.572947, 0.533781, 0.483152, 0.484247, 0.497563",\ + "0.655514, 0.616348, 0.565718, 0.566814, 0.580130",\ + "0.734317, 0.695151, 0.644522, 0.645617, 0.658933",\ + "0.870061, 0.830896, 0.780266, 0.781361, 0.794677",\ + "1.084318, 1.045152, 0.994522, 0.995618, 1.008934"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.471556, 0.413875, 0.358773, 0.359869, 0.373185",\ + "0.557541, 0.499860, 0.444758, 0.445854, 0.459170",\ + "0.648123, 0.590443, 0.535341, 0.536436, 0.549753",\ + "0.811397, 0.753716, 0.698614, 0.699710, 0.713026",\ + "1.086303, 1.028622, 0.973521, 0.974616, 0.987932"); + } + + } /* end of arc clk_ast_usb_i_usb_ref_val_i_stupr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.261299, -0.228217, -0.169581, -0.155962, 0.009554",\ + "-0.343866, -0.310783, -0.252148, -0.238528, -0.073013",\ + "-0.422669, -0.389587, -0.330951, -0.317332, -0.151816",\ + "-0.558414, -0.525331, -0.466695, -0.453076, -0.287561",\ + "-0.772670, -0.739587, -0.680952, -0.667332, -0.501817"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.213704, -0.162701, -0.066223, -0.048077, 0.172450",\ + "-0.299689, -0.248686, -0.152209, -0.134063, 0.086465",\ + "-0.390272, -0.339269, -0.242791, -0.224645, -0.004118",\ + "-0.553545, -0.502542, -0.406065, -0.387919, -0.167392",\ + "-0.828451, -0.777448, -0.680971, -0.662825, -0.442298"); + } + + } /* end of arc clk_ast_usb_i_usb_ref_val_i_hldr*/ + +} /* end of pin usb_ref_val_i */ + +pin("clk_src_usb_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001677 ; + + /* Other user defined attributes. */ + original_pin : clk_src_usb_en_i; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.090457, 0.087585",\ + "0.271588, 0.219415, 0.179927, 0.162045, 0.157577",\ + "0.363033, 0.310027, 0.270334, 0.252385, 0.247965",\ + "0.507780, 0.454308, 0.413646, 0.395357, 0.391106",\ + "0.811131, 0.757315, 0.714144, 0.694969, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.049669, 0.020498",\ + "0.324602, 0.241857, 0.166855, 0.126539, 0.100040",\ + "0.429418, 0.345854, 0.270221, 0.227986, 0.196782",\ + "0.605833, 0.521783, 0.445878, 0.397956, 0.350944",\ + "0.983325, 0.898854, 0.822917, 0.761117, 0.674795"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_en_i_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.032751, 0.135173",\ + "-0.166367, -0.123600, -0.088245, -0.037477, 0.065076",\ + "-0.251291, -0.208679, -0.174484, -0.124115, -0.021332",\ + "-0.373429, -0.330963, -0.299719, -0.251733, -0.152256",\ + "-0.620310, -0.578080, -0.553843, -0.512151, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.102409, 0.285045",\ + "-0.205839, -0.131127, -0.064641, 0.027653, 0.211502",\ + "-0.308157, -0.233980, -0.166224, -0.072248, 0.114884",\ + "-0.470591, -0.397956, -0.329423, -0.234665, -0.046227",\ + "-0.811364, -0.742478, -0.673228, -0.578223, -0.389923"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_en_i_hldr*/ + +} /* end of pin clk_src_usb_en_i */ + +pin("clk_src_usb_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.069236 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_usb_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\ + "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\ + "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\ + "1.737872, 1.770095, 1.839437, 2.057034, 2.749000",\ + "1.737872, 1.770095, 1.839437, 2.057034, 2.749000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\ + "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\ + "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\ + "1.568604, 1.612346, 1.706142, 2.005007, 2.947481",\ + "1.568604, 1.612346, 1.706142, 2.005007, 2.947481"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_fedg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : falling_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\ + "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\ + "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\ + "1.093582, 1.125805, 1.195148, 1.412745, 2.104710",\ + "1.093582, 1.125805, 1.195148, 1.412745, 2.104710"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\ + "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\ + "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\ + "1.010551, 1.054292, 1.148088, 1.446953, 2.389427",\ + "1.010551, 1.054292, 1.148088, 1.446953, 2.389427"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_fedg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.101180, 1.133403, 1.202745, 1.420342, 2.112307",\ + "1.189325, 1.221548, 1.290891, 1.508488, 2.200453",\ + "1.285347, 1.317570, 1.386912, 1.604509, 2.296474",\ + "1.453311, 1.485534, 1.554876, 1.772473, 2.464438",\ + "1.727352, 1.759575, 1.828917, 2.046515, 2.738480"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.029003, 1.072744, 1.166540, 1.465405, 2.407880",\ + "1.116853, 1.160595, 1.254391, 1.553256, 2.495730",\ + "1.198296, 1.242037, 1.335833, 1.634698, 2.577173",\ + "1.337780, 1.381521, 1.475317, 1.774182, 2.716657",\ + "1.565882, 1.609623, 1.703419, 2.002285, 2.944759"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.100277, 1.132500, 1.201842, 1.419439, 2.111404",\ + "1.188403, 1.220626, 1.289968, 1.507565, 2.199530",\ + "1.284444, 1.316668, 1.386010, 1.603607, 2.295572",\ + "1.452407, 1.484630, 1.553972, 1.771569, 2.463535",\ + "1.726368, 1.758591, 1.827933, 2.045531, 2.737496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.026546, 1.070287, 1.164084, 1.462948, 2.405423",\ + "1.114365, 1.158106, 1.251902, 1.550767, 2.493242",\ + "1.195575, 1.239316, 1.333112, 1.631977, 2.574452",\ + "1.335306, 1.379047, 1.472843, 1.771708, 2.714183",\ + "1.563376, 1.607117, 1.700913, 1.999778, 2.942253"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_redg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.641426, 1.673649, 1.742991, 1.960589, 2.652554",\ + "1.720995, 1.753218, 1.822561, 2.040158, 2.732123",\ + "1.800790, 1.833013, 1.902355, 2.119953, 2.811918",\ + "1.930632, 1.962856, 2.032198, 2.249795, 2.941760",\ + "2.130731, 2.162954, 2.232296, 2.449894, 3.141859"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017599, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.423514, 1.467255, 1.561051, 1.859916, 2.802391",\ + "1.512686, 1.556427, 1.650223, 1.949089, 2.891563",\ + "1.603640, 1.647381, 1.741178, 2.040043, 2.982517",\ + "1.758735, 1.802476, 1.896272, 2.195137, 3.137612",\ + "2.011581, 2.055323, 2.149119, 2.447984, 3.390458"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.625646, 1.657869, 1.727212, 1.944809, 2.636774",\ + "1.705396, 1.737619, 1.806961, 2.024558, 2.716523",\ + "1.780640, 1.812864, 1.882206, 2.099803, 2.791768",\ + "1.900872, 1.933095, 2.002438, 2.220035, 2.912000",\ + "2.084163, 2.116387, 2.185729, 2.403326, 3.095291"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "1.415430, 1.459171, 1.552967, 1.851832, 2.794307",\ + "1.503017, 1.546759, 1.640555, 1.939419, 2.881894",\ + "1.589827, 1.633568, 1.727364, 2.026229, 2.968703",\ + "1.739106, 1.782847, 1.876643, 2.175508, 3.117983",\ + "1.983528, 2.027269, 2.121065, 2.419930, 3.362405"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935",\ + "0.020388, 0.096008, 0.262833, 0.786379, 2.444935"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_o_una_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970012.125000, 970012.187500, 970012.250000, 970012.437500, 970013.125000",\ + "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.250000",\ + "970012.375000, 970012.437500, 970012.500000, 970012.687500, 970013.375000",\ + "970012.375000, 970012.437500, 970012.500000, 970012.687500, 970013.375000",\ + "970012.750000, 970012.812500, 970012.875000, 970013.062500, 970013.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970010.062500, 970010.062500, 970010.187500, 970010.500000, 970011.437500",\ + "970010.187500, 970010.187500, 970010.312500, 970010.625000, 970011.562500",\ + "970010.312500, 970010.312500, 970010.437500, 970010.750000, 970011.687500",\ + "970010.312500, 970010.312500, 970010.437500, 970010.750000, 970011.687500",\ + "970010.687500, 970010.687500, 970010.812500, 970011.125000, 970012.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_usb_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.559788, 0.592011, 0.660516, 0.878515, 1.570735",\ + "0.647589, 0.679811, 0.748316, 0.966316, 1.658535",\ + "0.728888, 0.761111, 0.829615, 1.047615, 1.739835",\ + "0.787041, 0.819264, 0.887769, 1.105768, 1.797988",\ + "1.095762, 1.127984, 1.196489, 1.414489, 2.106709"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.600873, 0.644670, 0.738286, 1.035322, 1.979740",\ + "0.688747, 0.732544, 0.826160, 1.123196, 2.067614",\ + "0.783083, 0.826880, 0.920496, 1.217532, 2.161950",\ + "0.850841, 0.894638, 0.988254, 1.285290, 2.229708",\ + "1.211540, 1.255336, 1.348952, 1.645988, 2.590406"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_usb_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970006.875000, 970006.875000, 970006.937500, 970007.187500, 970007.875000",\ + "970007.000000, 970007.000000, 970007.062500, 970007.312500, 970008.000000",\ + "970007.000000, 970007.000000, 970007.062500, 970007.312500, 970008.000000",\ + "970007.250000, 970007.250000, 970007.312500, 970007.562500, 970008.250000",\ + "970007.500000, 970007.500000, 970007.562500, 970007.812500, 970008.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970009.937500, 970009.937500, 970010.062500, 970010.375000, 970011.312500",\ + "970010.062500, 970010.062500, 970010.187500, 970010.500000, 970011.437500",\ + "970010.187500, 970010.187500, 970010.312500, 970010.625000, 970011.562500",\ + "970010.437500, 970010.437500, 970010.562500, 970010.875000, 970011.812500",\ + "970010.687500, 970010.687500, 970010.812500, 970011.125000, 970012.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "380001.781250, 380001.812500, 380001.875000, 380002.093750, 380002.781250",\ + "380001.875000, 380001.906250, 380001.968750, 380002.187500, 380002.875000",\ + "380001.937500, 380001.968750, 380002.031250, 380002.250000, 380002.937500",\ + "380002.093750, 380002.125000, 380002.187500, 380002.406250, 380003.093750",\ + "380002.312500, 380002.343750, 380002.406250, 380002.625000, 380003.312500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "380003.031250, 380003.062500, 380003.156250, 380003.468750, 380004.406250",\ + "380003.125000, 380003.156250, 380003.250000, 380003.562500, 380004.500000",\ + "380003.218750, 380003.250000, 380003.343750, 380003.656250, 380004.593750",\ + "380003.406250, 380003.437500, 380003.531250, 380003.843750, 380004.781250",\ + "380003.656250, 380003.687500, 380003.781250, 380004.093750, 380005.031250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970008.625000, 970008.687500, 970008.750000, 970009.062500, 970010.000000",\ + "970008.750000, 970008.812500, 970008.875000, 970009.187500, 970010.125000",\ + "970008.750000, 970008.812500, 970008.875000, 970009.187500, 970010.125000",\ + "970009.000000, 970009.062500, 970009.125000, 970009.437500, 970010.375000",\ + "970009.250000, 970009.312500, 970009.375000, 970009.687500, 970010.625000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260986, 0.783299, 2.448362"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "970012.000000, 970012.062500, 970012.125000, 970012.312500, 970013.000000",\ + "970012.125000, 970012.187500, 970012.250000, 970012.437500, 970013.125000",\ + "970012.250000, 970012.312500, 970012.375000, 970012.562500, 970013.250000",\ + "970012.500000, 970012.562500, 970012.625000, 970012.812500, 970013.500000",\ + "970012.750000, 970012.812500, 970012.875000, 970013.062500, 970013.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878",\ + "0.042128, 0.086864, 0.207230, 0.622005, 1.937878"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "380000.343750, 380000.375000, 380000.468750, 380000.781250, 380001.718750",\ + "380000.437500, 380000.468750, 380000.562500, 380000.875000, 380001.812500",\ + "380000.500000, 380000.531250, 380000.625000, 380000.937500, 380001.875000",\ + "380000.656250, 380000.687500, 380000.781250, 380001.093750, 380002.031250",\ + "380000.875000, 380000.906250, 380001.000000, 380001.312500, 380002.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935",\ + "0.020039, 0.095921, 0.259491, 0.781146, 2.444935"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "380001.750000, 380001.781250, 380001.843750, 380002.062500, 380002.750000",\ + "380001.843750, 380001.875000, 380001.937500, 380002.156250, 380002.843750",\ + "380001.937500, 380001.968750, 380002.031250, 380002.250000, 380002.937500",\ + "380002.125000, 380002.156250, 380002.218750, 380002.437500, 380003.125000",\ + "380002.375000, 380002.406250, 380002.468750, 380002.687500, 380003.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590010.375000, 590010.437500, 590010.500000, 590010.687500, 590011.375000",\ + "590010.500000, 590010.562500, 590010.625000, 590010.812500, 590011.500000",\ + "590010.500000, 590010.562500, 590010.625000, 590010.812500, 590011.500000",\ + "590010.625000, 590010.687500, 590010.750000, 590010.937500, 590011.625000",\ + "590010.875000, 590010.937500, 590011.000000, 590011.187500, 590011.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.750000",\ + "590008.500000, 590008.562500, 590008.625000, 590008.937500, 590009.875000",\ + "590008.625000, 590008.687500, 590008.750000, 590009.062500, 590010.000000",\ + "590008.750000, 590008.812500, 590008.875000, 590009.187500, 590010.125000",\ + "590009.125000, 590009.187500, 590009.250000, 590009.562500, 590010.500000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590008.437500, 590008.500000, 590008.562500, 590008.812500, 590009.500000",\ + "590008.437500, 590008.500000, 590008.562500, 590008.812500, 590009.500000",\ + "590008.562500, 590008.625000, 590008.687500, 590008.937500, 590009.625000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.062500, 590009.750000",\ + "590008.937500, 590009.000000, 590009.062500, 590009.312500, 590010.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590006.687500, 590006.750000, 590006.875000, 590007.125000, 590008.125000",\ + "590006.812500, 590006.875000, 590007.000000, 590007.250000, 590008.250000",\ + "590006.937500, 590007.000000, 590007.125000, 590007.375000, 590008.375000",\ + "590007.062500, 590007.125000, 590007.250000, 590007.500000, 590008.500000",\ + "590007.312500, 590007.375000, 590007.500000, 590007.750000, 590008.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590008.312500, 590008.312500, 590008.437500, 590008.750000, 590009.687500",\ + "590008.437500, 590008.437500, 590008.562500, 590008.875000, 590009.812500",\ + "590008.437500, 590008.437500, 590008.562500, 590008.875000, 590009.812500",\ + "590008.562500, 590008.562500, 590008.687500, 590009.000000, 590009.937500",\ + "590008.812500, 590008.812500, 590008.937500, 590009.250000, 590010.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362",\ + "0.038124, 0.100137, 0.260980, 0.783299, 2.448362"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590006.625000, 590006.625000, 590006.687500, 590006.937500, 590007.625000",\ + "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.750000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.875000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.687500, 590008.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878",\ + "0.042077, 0.086820, 0.207230, 0.622005, 1.937878"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590008.312500, 590008.312500, 590008.437500, 590008.750000, 590009.687500",\ + "590008.312500, 590008.312500, 590008.437500, 590008.750000, 590009.687500",\ + "590008.437500, 590008.437500, 590008.562500, 590008.875000, 590009.812500",\ + "590008.562500, 590008.562500, 590008.687500, 590009.000000, 590009.937500",\ + "590008.812500, 590008.812500, 590008.937500, 590009.250000, 590010.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935",\ + "0.020388, 0.095624, 0.260980, 0.781920, 2.444935"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "590006.625000, 590006.625000, 590006.687500, 590006.937500, 590007.625000",\ + "590006.750000, 590006.750000, 590006.812500, 590007.062500, 590007.750000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.187500, 590007.875000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.312500, 590008.000000",\ + "590007.250000, 590007.250000, 590007.312500, 590007.562500, 590008.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002148, 0.006836, 0.021756, 0.069236"); + values ( "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571",\ + "0.017600, 0.075142, 0.205270, 0.618216, 1.929571"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_o_inv_min*/ + +} /* end of pin clk_src_usb_o */ + +pin("clk_src_usb_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.090214 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : clk_src_usb_val_o; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.349057, 0.389670, 0.471811, 0.746196, 1.641015",\ + "0.436455, 0.477067, 0.559209, 0.833594, 1.728413",\ + "0.517302, 0.557914, 0.640055, 0.914441, 1.809259",\ + "0.655434, 0.696047, 0.778188, 1.052573, 1.947392",\ + "0.895822, 0.936589, 1.018755, 1.291518, 2.187617"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\ + "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\ + "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\ + "0.023046, 0.083902, 0.239672, 0.764755, 2.477149",\ + "0.023046, 0.083902, 0.239672, 0.764756, 2.477149"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.392641, 0.430353, 0.490673, 0.680876, 1.305538",\ + "0.480039, 0.517751, 0.578071, 0.768273, 1.392936",\ + "0.560851, 0.598563, 0.658884, 0.849086, 1.473748",\ + "0.698861, 0.736574, 0.796894, 0.987096, 1.611758",\ + "0.919051, 0.956763, 1.017083, 1.207286, 1.831948"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\ + "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\ + "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\ + "0.028951, 0.070788, 0.167468, 0.516468, 1.652661",\ + "0.028951, 0.070788, 0.167468, 0.516468, 1.652661"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.222724, 0.263066, 0.345165, 0.618191, 1.516706",\ + "0.310912, 0.351255, 0.433354, 0.706380, 1.604895",\ + "0.398549, 0.438892, 0.520991, 0.794016, 1.692532",\ + "0.546817, 0.587159, 0.669259, 0.942284, 1.840799",\ + "0.782132, 0.822474, 0.904573, 1.177599, 2.076114"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\ + "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\ + "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\ + "0.021530, 0.083764, 0.238778, 0.757619, 2.456895",\ + "0.021530, 0.083764, 0.238778, 0.757619, 2.456895"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.263657, 0.301407, 0.361820, 0.551984, 1.176778",\ + "0.351846, 0.389595, 0.450008, 0.640173, 1.264967",\ + "0.439483, 0.477232, 0.537645, 0.727810, 1.352604",\ + "0.587750, 0.625500, 0.685913, 0.876077, 1.500872",\ + "0.813891, 0.851054, 0.911373, 1.101677, 1.725499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\ + "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\ + "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\ + "0.025914, 0.068635, 0.165828, 0.512808, 1.651598",\ + "0.025914, 0.068635, 0.165828, 0.512808, 1.651598"); + } + + } /* end of arc clk_ast_ext_i_clk_src_usb_val_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\ + "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\ + "970010.562500, 970010.625000, 970010.687500, 970011.000000, 970011.875000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.562500, 970010.625000, 970010.687500, 970010.875000, 970011.500000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_usb_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.691181, 0.731788, 0.813938, 1.088216, 1.983374",\ + "0.778982, 0.819588, 0.901739, 1.176016, 2.071174",\ + "0.860281, 0.900888, 0.983038, 1.257316, 2.152474",\ + "0.918434, 0.959041, 1.041191, 1.315469, 2.210627",\ + "1.227155, 1.267762, 1.349912, 1.624190, 2.519347"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.670492, 0.707647, 0.767969, 0.958286, 1.582166",\ + "0.758292, 0.795447, 0.855769, 1.046087, 1.669967",\ + "0.839591, 0.876747, 0.937069, 1.127386, 1.751266",\ + "0.897745, 0.934900, 0.995222, 1.185539, 1.809419",\ + "1.206465, 1.243621, 1.303943, 1.494260, 2.118140"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262"); + } + + } /* end of arc clk_ast_tlul_i_clk_src_usb_val_o_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970007.125000, 970007.125000, 970007.250000, 970007.500000, 970008.375000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.250000, 970007.250000, 970007.375000, 970007.625000, 970008.500000",\ + "970007.500000, 970007.500000, 970007.625000, 970007.875000, 970008.750000",\ + "970007.750000, 970007.750000, 970007.875000, 970008.125000, 970009.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.500000, 970011.125000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.625000, 970011.250000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.750000, 970011.375000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.000000, 970011.625000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.250000, 970011.875000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380000.437500, 380000.500000, 380000.562500, 380000.843750, 380001.750000",\ + "380000.531250, 380000.593750, 380000.656250, 380000.937500, 380001.843750",\ + "380000.593750, 380000.656250, 380000.718750, 380001.000000, 380001.906250",\ + "380000.750000, 380000.812500, 380000.875000, 380001.156250, 380002.062500",\ + "380000.968750, 380001.031250, 380001.093750, 380001.375000, 380002.281250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380001.875000, 380001.906250, 380001.968750, 380002.156250, 380002.781250",\ + "380001.968750, 380002.000000, 380002.062500, 380002.250000, 380002.875000",\ + "380002.062500, 380002.093750, 380002.156250, 380002.343750, 380002.968750",\ + "380002.250000, 380002.281250, 380002.343750, 380002.531250, 380003.156250",\ + "380002.500000, 380002.531250, 380002.593750, 380002.781250, 380003.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970007.125000, 970007.187500, 970007.250000, 970007.437500, 970008.062500",\ + "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.250000, 970007.312500, 970007.375000, 970007.562500, 970008.187500",\ + "970007.500000, 970007.562500, 970007.625000, 970007.812500, 970008.437500",\ + "970007.750000, 970007.812500, 970007.875000, 970008.062500, 970008.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515912, 1.652408"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "970010.187500, 970010.250000, 970010.312500, 970010.625000, 970011.500000",\ + "970010.312500, 970010.375000, 970010.437500, 970010.750000, 970011.625000",\ + "970010.437500, 970010.500000, 970010.562500, 970010.875000, 970011.750000",\ + "970010.687500, 970010.750000, 970010.812500, 970011.125000, 970012.000000",\ + "970010.937500, 970011.000000, 970011.062500, 970011.375000, 970012.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766838, 2.469430"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380000.500000, 380000.531250, 380000.593750, 380000.781250, 380001.406250",\ + "380000.593750, 380000.625000, 380000.687500, 380000.875000, 380001.500000",\ + "380000.656250, 380000.687500, 380000.750000, 380000.937500, 380001.562500",\ + "380000.812500, 380000.843750, 380000.906250, 380001.093750, 380001.718750",\ + "380001.031250, 380001.062500, 380001.125000, 380001.312500, 380001.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262",\ + "0.025904, 0.068640, 0.165825, 0.512797, 1.652262"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "380001.906250, 380001.937500, 380002.031250, 380002.281250, 380003.187500",\ + "380002.000000, 380002.031250, 380002.125000, 380002.375000, 380003.281250",\ + "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\ + "380002.281250, 380002.312500, 380002.406250, 380002.656250, 380003.562500",\ + "380002.531250, 380002.562500, 380002.656250, 380002.906250, 380003.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156",\ + "0.021562, 0.083764, 0.238778, 0.757102, 2.460156"); + } + + } /* end of arc padmux2ast_i[4]_clk_src_usb_val_o_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590009.000000, 590009.875000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.125000, 590010.000000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.250000, 590010.125000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.500000, 590010.375000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.937500, 590007.000000, 590007.187500, 590007.812500",\ + "590007.000000, 590007.062500, 590007.125000, 590007.312500, 590007.937500",\ + "590007.125000, 590007.187500, 590007.250000, 590007.437500, 590008.062500",\ + "590007.250000, 590007.312500, 590007.375000, 590007.562500, 590008.187500",\ + "590007.625000, 590007.687500, 590007.750000, 590007.937500, 590008.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.375000, 590008.437500, 590008.500000, 590008.812500, 590009.687500",\ + "590008.500000, 590008.562500, 590008.625000, 590008.937500, 590009.812500",\ + "590008.625000, 590008.687500, 590008.750000, 590009.062500, 590009.937500",\ + "590008.875000, 590008.937500, 590009.000000, 590009.312500, 590010.187500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.750000, 590006.750000, 590006.812500, 590007.000000, 590007.625000",\ + "590006.875000, 590006.875000, 590006.937500, 590007.125000, 590007.750000",\ + "590007.000000, 590007.000000, 590007.062500, 590007.250000, 590007.875000",\ + "590007.125000, 590007.125000, 590007.187500, 590007.375000, 590008.000000",\ + "590007.375000, 590007.375000, 590007.437500, 590007.625000, 590008.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408",\ + "0.028494, 0.070786, 0.167369, 0.515919, 1.652408"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.625000, 590007.625000, 590007.750000, 590008.000000, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430",\ + "0.022871, 0.084362, 0.238855, 0.766861, 2.469430"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.562500, 590008.625000, 590008.687500, 590008.875000, 590009.500000",\ + "590008.687500, 590008.750000, 590008.812500, 590009.000000, 590009.625000",\ + "590008.812500, 590008.875000, 590008.937500, 590009.125000, 590009.750000",\ + "590009.062500, 590009.125000, 590009.187500, 590009.375000, 590010.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082",\ + "0.026011, 0.068726, 0.165863, 0.510725, 1.651082"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "590006.875000, 590006.875000, 590007.000000, 590007.250000, 590008.125000",\ + "590007.000000, 590007.000000, 590007.125000, 590007.375000, 590008.250000",\ + "590007.125000, 590007.125000, 590007.250000, 590007.500000, 590008.375000",\ + "590007.250000, 590007.250000, 590007.375000, 590007.625000, 590008.500000",\ + "590007.500000, 590007.500000, 590007.625000, 590007.875000, 590008.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.002461, 0.008196, 0.027294, 0.090214"); + values ( "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812",\ + "0.022032, 0.083764, 0.238629, 0.755850, 2.465812"); + } + + } /* end of arc padmux2ast_i[5]_clk_src_usb_val_o_inv_min*/ + +} /* end of pin clk_src_usb_val_o */ +bus ( usb_io_pu_cal_o ) { + + bus_type : BUS20_type7 ; + direction : output ; + +pin("usb_io_pu_cal_o[19]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[19]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\ + "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\ + "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\ + "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\ + "0.830581, 0.852045, 0.888318, 1.293020, 2.184924"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070225, 0.128223, 0.852056, 2.450128",\ + "0.046369, 0.071964, 0.128232, 0.852062, 2.450135"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\ + "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\ + "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\ + "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\ + "0.839028, 0.848765, 0.862546, 1.001302, 1.307204"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025202, 0.034115, 0.048740, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048740, 0.301167, 0.860107",\ + "0.025203, 0.034116, 0.048742, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048744, 0.301167, 0.860107",\ + "0.025222, 0.034137, 0.048764, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[19]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.197396, 0.217798, 0.253787, 0.659515, 1.549779",\ + "0.285773, 0.306177, 0.342166, 0.747894, 1.638158",\ + "0.375534, 0.395928, 0.431912, 0.837641, 1.727905",\ + "0.439799, 0.460179, 0.496157, 0.901887, 1.792151",\ + "0.781328, 0.801955, 0.838037, 1.243750, 2.134013"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\ + "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\ + "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\ + "0.041661, 0.069999, 0.126709, 0.849969, 2.447141",\ + "0.041673, 0.070094, 0.126932, 0.849969, 2.447141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.177011, 0.187648, 0.201756, 0.342079, 0.647165",\ + "0.264382, 0.275019, 0.289127, 0.429450, 0.734536",\ + "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\ + "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\ + "0.681430, 0.692081, 0.706196, 0.846525, 1.151605"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024126, 0.032778, 0.047567, 0.299569, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[19]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[19] */ + +pin("usb_io_pu_cal_o[18]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[18]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\ + "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\ + "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\ + "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\ + "0.830581, 0.852045, 0.888318, 1.293020, 2.184924"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128218, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070225, 0.128223, 0.852056, 2.450128",\ + "0.046369, 0.071964, 0.128232, 0.852062, 2.450135"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\ + "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\ + "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\ + "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\ + "0.839028, 0.848765, 0.862546, 1.001302, 1.307204"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025200, 0.034112, 0.048740, 0.301167, 0.860107",\ + "0.025200, 0.034112, 0.048740, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048742, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048744, 0.301167, 0.860107",\ + "0.025221, 0.034136, 0.048764, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[18]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.211928, 0.232331, 0.268319, 0.674047, 1.564311",\ + "0.300343, 0.320746, 0.356735, 0.762463, 1.652727",\ + "0.394726, 0.415129, 0.451117, 0.856845, 1.747110",\ + "0.462784, 0.483187, 0.519176, 0.924904, 1.815168",\ + "0.787427, 0.807827, 0.843815, 1.249543, 2.139807"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041661, 0.070068, 0.126730, 0.849972, 2.447344",\ + "0.041661, 0.070068, 0.126730, 0.849972, 2.447344",\ + "0.041661, 0.070068, 0.126730, 0.849972, 2.447344",\ + "0.041661, 0.070068, 0.126730, 0.849972, 2.447345",\ + "0.041673, 0.070061, 0.126728, 0.849969, 2.447347"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.180996, 0.190508, 0.204096, 0.342744, 0.648655",\ + "0.266400, 0.277038, 0.291146, 0.430107, 0.736018",\ + "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\ + "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\ + "0.681430, 0.692081, 0.706196, 0.846525, 1.151605"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024113, 0.032746, 0.047552, 0.299568, 0.856157",\ + "0.024126, 0.032778, 0.047567, 0.299569, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[18]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[18] */ + +pin("usb_io_pu_cal_o[17]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[17]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\ + "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\ + "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\ + "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\ + "0.830581, 0.852045, 0.888318, 1.293020, 2.184924"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044601, 0.070148, 0.128218, 0.852056, 2.450125",\ + "0.044663, 0.070159, 0.128218, 0.852056, 2.450125",\ + "0.044669, 0.070182, 0.128220, 0.852056, 2.450126",\ + "0.044669, 0.070225, 0.128223, 0.852056, 2.450128",\ + "0.046118, 0.071698, 0.128232, 0.852061, 2.450135"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\ + "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\ + "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\ + "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\ + "0.839028, 0.848765, 0.862546, 1.001302, 1.307204"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048740, 0.301166, 0.860107",\ + "0.025213, 0.034127, 0.048740, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048742, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048744, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048764, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[17]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\ + "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\ + "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\ + "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041673, 0.070054, 0.126726, 0.849969, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.175899, 0.186544, 0.200656, 0.340982, 0.646065",\ + "0.263271, 0.273916, 0.288028, 0.428355, 0.733437",\ + "0.344128, 0.354771, 0.368883, 0.509209, 0.814291",\ + "0.401818, 0.412460, 0.426571, 0.566896, 0.871980",\ + "0.705550, 0.716209, 0.730328, 0.870660, 1.175736"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\ + "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\ + "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\ + "0.024113, 0.032746, 0.047558, 0.299568, 0.856133",\ + "0.024126, 0.032778, 0.047574, 0.299569, 0.856133"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[17]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[17] */ + +pin("usb_io_pu_cal_o[16]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[16]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.314417, 0.335777, 0.372002, 0.776684, 1.668587",\ + "0.399220, 0.420577, 0.456801, 0.861483, 1.753386",\ + "0.475457, 0.496832, 0.533065, 0.937750, 1.829653",\ + "0.530163, 0.551559, 0.587801, 0.992490, 1.884393",\ + "0.830581, 0.852045, 0.888318, 1.293020, 2.184924"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070225, 0.128223, 0.852056, 2.450128",\ + "0.044695, 0.070368, 0.128232, 0.852056, 2.450135"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.217558, 0.227289, 0.241063, 0.379813, 0.685715",\ + "0.306214, 0.315945, 0.329719, 0.468469, 0.774371",\ + "0.401954, 0.411685, 0.425460, 0.564210, 0.870112",\ + "0.471485, 0.481216, 0.494992, 0.633742, 0.939644",\ + "0.839028, 0.848765, 0.862546, 1.001302, 1.307204"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048740, 0.301166, 0.860107",\ + "0.025212, 0.034126, 0.048740, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048742, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048744, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048764, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[16]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.241214, 0.262542, 0.298754, 0.703431, 1.595333",\ + "0.329624, 0.350953, 0.387164, 0.791841, 1.683743",\ + "0.418828, 0.440156, 0.476368, 0.881044, 1.772947",\ + "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041661, 0.070060, 0.126728, 0.849972, 2.447347",\ + "0.041673, 0.070054, 0.126726, 0.849969, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.180996, 0.190508, 0.204096, 0.342744, 0.648655",\ + "0.268360, 0.277871, 0.291459, 0.430107, 0.736018",\ + "0.349209, 0.358716, 0.372303, 0.510951, 0.816863",\ + "0.406926, 0.416431, 0.430016, 0.568664, 0.874576",\ + "0.710950, 0.720466, 0.734056, 0.872703, 1.178614"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\ + "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\ + "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\ + "0.024113, 0.032746, 0.047559, 0.299568, 0.856139",\ + "0.024126, 0.032778, 0.047572, 0.299569, 0.856139"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[16]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[16] */ + +pin("usb_io_pu_cal_o[15]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[15]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\ + "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\ + "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\ + "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\ + "0.862468, 0.884064, 0.920396, 1.325122, 2.217029"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070220, 0.128222, 0.852056, 2.450128",\ + "0.046369, 0.071964, 0.128250, 0.852062, 2.450147"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.208477, 0.218207, 0.231981, 0.370730, 0.676633",\ + "0.296951, 0.306682, 0.320455, 0.459205, 0.765107",\ + "0.387709, 0.397440, 0.411214, 0.549964, 0.855866",\ + "0.453111, 0.462843, 0.476618, 0.615368, 0.921270",\ + "0.800244, 0.809980, 0.823761, 0.962517, 1.268419"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025202, 0.034115, 0.048739, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048739, 0.301167, 0.860107",\ + "0.025203, 0.034116, 0.048740, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048742, 0.301167, 0.860107",\ + "0.025222, 0.034137, 0.048763, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[15]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.197396, 0.217798, 0.253787, 0.659515, 1.549779",\ + "0.285773, 0.306177, 0.342166, 0.747894, 1.638158",\ + "0.375534, 0.395928, 0.431912, 0.837641, 1.727905",\ + "0.439799, 0.460179, 0.496157, 0.901887, 1.792151",\ + "0.781328, 0.801955, 0.838037, 1.243750, 2.134013"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041685, 0.069999, 0.126709, 0.849953, 2.447141",\ + "0.041695, 0.069999, 0.126709, 0.849953, 2.447141",\ + "0.041741, 0.069999, 0.126709, 0.849953, 2.447141",\ + "0.041758, 0.069999, 0.126709, 0.849953, 2.447141",\ + "0.041766, 0.070174, 0.126932, 0.849953, 2.447141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.177011, 0.187648, 0.201756, 0.340918, 0.646830",\ + "0.264382, 0.275019, 0.289127, 0.428292, 0.734203",\ + "0.342508, 0.353145, 0.367252, 0.506601, 0.812513",\ + "0.397042, 0.407678, 0.421785, 0.561150, 0.867061",\ + "0.681430, 0.692081, 0.706196, 0.845682, 1.151594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\ + "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\ + "0.024117, 0.032767, 0.047553, 0.299569, 0.856201",\ + "0.024117, 0.032759, 0.047552, 0.299568, 0.856201",\ + "0.024117, 0.032759, 0.047552, 0.299568, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[15]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[15] */ + +pin("usb_io_pu_cal_o[14]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[14]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\ + "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\ + "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\ + "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\ + "0.862468, 0.884064, 0.920396, 1.325122, 2.217029"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128219, 0.852056, 2.450125",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070220, 0.128222, 0.852056, 2.450128",\ + "0.046369, 0.071964, 0.128250, 0.852062, 2.450147"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.208477, 0.218207, 0.231981, 0.370730, 0.676633",\ + "0.296951, 0.306682, 0.320455, 0.459205, 0.765107",\ + "0.387709, 0.397440, 0.411214, 0.549964, 0.855866",\ + "0.453111, 0.462843, 0.476618, 0.615368, 0.921270",\ + "0.800244, 0.809980, 0.823761, 0.962517, 1.268419"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025200, 0.034112, 0.048739, 0.301167, 0.860107",\ + "0.025200, 0.034112, 0.048739, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048740, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048742, 0.301167, 0.860107",\ + "0.025221, 0.034136, 0.048763, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[14]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.211928, 0.232331, 0.268319, 0.674047, 1.564311",\ + "0.300343, 0.320746, 0.356735, 0.762463, 1.652727",\ + "0.394726, 0.415129, 0.451117, 0.856845, 1.747110",\ + "0.462784, 0.483187, 0.519176, 0.924904, 1.815168",\ + "0.787427, 0.807827, 0.843815, 1.249543, 2.139807"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041685, 0.070068, 0.126730, 0.849967, 2.447344",\ + "0.041695, 0.070068, 0.126730, 0.849965, 2.447344",\ + "0.041741, 0.070068, 0.126730, 0.849957, 2.447344",\ + "0.041758, 0.070068, 0.126730, 0.849954, 2.447345",\ + "0.041766, 0.070061, 0.126728, 0.849953, 2.447347"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.179169, 0.188682, 0.202271, 0.340918, 0.646830",\ + "0.266400, 0.276055, 0.289644, 0.428292, 0.734203",\ + "0.342508, 0.353145, 0.367252, 0.506601, 0.812513",\ + "0.397042, 0.407678, 0.421785, 0.561150, 0.867061",\ + "0.681430, 0.692081, 0.706196, 0.845682, 1.151594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\ + "0.024118, 0.032771, 0.047553, 0.299569, 0.856201",\ + "0.024117, 0.032767, 0.047553, 0.299569, 0.856201",\ + "0.024117, 0.032759, 0.047552, 0.299568, 0.856201",\ + "0.024117, 0.032759, 0.047552, 0.299568, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[14]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[14] */ + +pin("usb_io_pu_cal_o[13]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[13]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\ + "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\ + "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\ + "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\ + "0.862468, 0.884064, 0.920396, 1.325122, 2.217029"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044601, 0.070167, 0.128219, 0.852056, 2.450125",\ + "0.044663, 0.070167, 0.128219, 0.852056, 2.450125",\ + "0.044669, 0.070177, 0.128220, 0.852056, 2.450126",\ + "0.044669, 0.070220, 0.128222, 0.852056, 2.450128",\ + "0.046118, 0.071698, 0.128250, 0.852061, 2.450147"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.208477, 0.218207, 0.231981, 0.372429, 0.677586",\ + "0.296951, 0.306682, 0.320688, 0.461137, 0.766294",\ + "0.391373, 0.402162, 0.416428, 0.556878, 0.862036",\ + "0.460819, 0.471609, 0.485876, 0.626327, 0.931486",\ + "0.825748, 0.836544, 0.850818, 0.991274, 1.296437"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048739, 0.301166, 0.860107",\ + "0.025213, 0.034127, 0.048739, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048740, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048742, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048763, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[13]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\ + "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\ + "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\ + "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041685, 0.070060, 0.126728, 0.849967, 2.447347",\ + "0.041695, 0.070060, 0.126728, 0.849965, 2.447347",\ + "0.041741, 0.070060, 0.126728, 0.849957, 2.447347",\ + "0.041758, 0.070060, 0.126728, 0.849954, 2.447347",\ + "0.041766, 0.070054, 0.126726, 0.849953, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.175899, 0.186544, 0.200656, 0.340918, 0.646065",\ + "0.263271, 0.273916, 0.288028, 0.428292, 0.733437",\ + "0.344128, 0.354365, 0.367954, 0.506601, 0.812513",\ + "0.399406, 0.408915, 0.422502, 0.561150, 0.867061",\ + "0.683934, 0.693446, 0.707035, 0.845682, 1.151594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024118, 0.032771, 0.047561, 0.299569, 0.856177",\ + "0.024118, 0.032771, 0.047561, 0.299569, 0.856176",\ + "0.024117, 0.032767, 0.047560, 0.299569, 0.856176",\ + "0.024117, 0.032759, 0.047558, 0.299568, 0.856176",\ + "0.024117, 0.032759, 0.047558, 0.299568, 0.856133"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[13]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[13] */ + +pin("usb_io_pu_cal_o[12]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[12]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320701, 0.342069, 0.378299, 0.782982, 1.674885",\ + "0.408065, 0.429433, 0.465663, 0.870347, 1.762250",\ + "0.488969, 0.510342, 0.546573, 0.951258, 1.843161",\ + "0.546844, 0.568237, 0.604478, 1.009167, 1.901070",\ + "0.862468, 0.884064, 0.920396, 1.325122, 2.217029"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044695, 0.070193, 0.128219, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128219, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070220, 0.128222, 0.852056, 2.450128",\ + "0.044695, 0.070644, 0.128250, 0.852056, 2.450147"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.208477, 0.218207, 0.231981, 0.372429, 0.677586",\ + "0.296951, 0.306682, 0.320455, 0.460894, 0.766051",\ + "0.391373, 0.402162, 0.416428, 0.556878, 0.862036",\ + "0.460819, 0.471609, 0.485876, 0.626327, 0.931486",\ + "0.825748, 0.836544, 0.850818, 0.991274, 1.296437"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048739, 0.301166, 0.860107",\ + "0.025212, 0.034126, 0.048739, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048740, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048742, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048763, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[12]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.238920, 0.260258, 0.296474, 0.701152, 1.593054",\ + "0.327371, 0.348714, 0.384932, 0.789611, 1.681513",\ + "0.416587, 0.437948, 0.474174, 0.878857, 1.770759",\ + "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041685, 0.070060, 0.126728, 0.849967, 2.447347",\ + "0.041695, 0.070060, 0.126728, 0.849965, 2.447347",\ + "0.041741, 0.070060, 0.126728, 0.849957, 2.447347",\ + "0.041758, 0.070060, 0.126728, 0.849954, 2.447347",\ + "0.041766, 0.070054, 0.126726, 0.849953, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.179169, 0.188682, 0.202271, 0.340918, 0.646830",\ + "0.266542, 0.276055, 0.289644, 0.428292, 0.734203",\ + "0.344853, 0.354365, 0.367954, 0.506601, 0.812513",\ + "0.399406, 0.408915, 0.422502, 0.561150, 0.867061",\ + "0.683934, 0.693446, 0.707035, 0.845682, 1.151594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024118, 0.032771, 0.047563, 0.299569, 0.856171",\ + "0.024118, 0.032771, 0.047563, 0.299569, 0.856171",\ + "0.024117, 0.032767, 0.047561, 0.299569, 0.856171",\ + "0.024117, 0.032759, 0.047559, 0.299568, 0.856171",\ + "0.024117, 0.032759, 0.047559, 0.299568, 0.856139"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[12]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[12] */ + +pin("usb_io_pu_cal_o[11]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[11]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\ + "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\ + "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\ + "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\ + "0.858742, 0.881931, 0.919078, 1.324622, 2.214868"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051946, 0.077865, 0.129119, 0.852080, 2.449966",\ + "0.052034, 0.077959, 0.129147, 0.852081, 2.449966",\ + "0.052292, 0.078232, 0.129231, 0.852081, 2.450003"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.206143, 0.216949, 0.231236, 0.371702, 0.676873",\ + "0.294617, 0.305423, 0.319710, 0.460177, 0.765348",\ + "0.385375, 0.396181, 0.410468, 0.550935, 0.856106",\ + "0.450776, 0.461583, 0.475870, 0.616338, 0.921509",\ + "0.797902, 0.808713, 0.823006, 0.963477, 1.268652"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025267, 0.034187, 0.048727, 0.301161, 0.860108",\ + "0.025267, 0.034187, 0.048727, 0.301161, 0.860108",\ + "0.025267, 0.034188, 0.048728, 0.301161, 0.860108",\ + "0.025268, 0.034189, 0.048730, 0.301161, 0.860108",\ + "0.025282, 0.034204, 0.048751, 0.301161, 0.860108"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[11]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.205226, 0.224853, 0.260301, 0.664656, 1.556533",\ + "0.293604, 0.313232, 0.348681, 0.753036, 1.644913",\ + "0.383357, 0.402977, 0.438423, 0.842777, 1.734654",\ + "0.447610, 0.467222, 0.502663, 0.907016, 1.798893",\ + "0.789341, 0.809115, 0.844630, 1.249013, 2.140893"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444969",\ + "0.037854, 0.066833, 0.128000, 0.850658, 2.444969"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.179497, 0.189096, 0.202727, 0.341364, 0.647272",\ + "0.266868, 0.276467, 0.290098, 0.428735, 0.734643",\ + "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\ + "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\ + "0.683921, 0.693531, 0.707168, 0.845803, 1.151711"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024427, 0.033054, 0.047472, 0.299575, 0.856462"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[11]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[11] */ + +pin("usb_io_pu_cal_o[10]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[10]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\ + "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\ + "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\ + "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\ + "0.858742, 0.881931, 0.919078, 1.324622, 2.214868"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051946, 0.077865, 0.129119, 0.852080, 2.449966",\ + "0.052034, 0.077959, 0.129147, 0.852081, 2.449966",\ + "0.052292, 0.078232, 0.129231, 0.852081, 2.450003"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.206143, 0.216949, 0.231236, 0.371702, 0.676873",\ + "0.294617, 0.305423, 0.319710, 0.460177, 0.765348",\ + "0.385375, 0.396181, 0.410468, 0.550935, 0.856106",\ + "0.450776, 0.461583, 0.475870, 0.616338, 0.921509",\ + "0.797902, 0.808713, 0.823006, 0.963477, 1.268652"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025267, 0.034187, 0.048724, 0.301161, 0.860108",\ + "0.025267, 0.034187, 0.048724, 0.301161, 0.860108",\ + "0.025267, 0.034188, 0.048727, 0.301161, 0.860108",\ + "0.025268, 0.034189, 0.048730, 0.301161, 0.860108",\ + "0.025282, 0.034204, 0.048750, 0.301161, 0.860108"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[10]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.219758, 0.239385, 0.274833, 0.679189, 1.571066",\ + "0.308173, 0.327801, 0.363249, 0.767605, 1.659482",\ + "0.402556, 0.422183, 0.457632, 0.861987, 1.753864",\ + "0.470615, 0.490242, 0.525690, 0.930046, 1.821923",\ + "0.795255, 0.814880, 0.850328, 1.254683, 2.146560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037493, 0.066526, 0.127980, 0.850723, 2.444973",\ + "0.037493, 0.066526, 0.127980, 0.850723, 2.444973",\ + "0.037493, 0.066525, 0.127980, 0.850723, 2.444973",\ + "0.037493, 0.066525, 0.127980, 0.850723, 2.444972",\ + "0.037489, 0.066522, 0.127980, 0.850723, 2.444969"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.184074, 0.193673, 0.207304, 0.345941, 0.651849",\ + "0.268886, 0.278485, 0.292117, 0.430754, 0.736662",\ + "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\ + "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\ + "0.683921, 0.693531, 0.707168, 0.845803, 1.151711"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024391, 0.033017, 0.047459, 0.299575, 0.856462",\ + "0.024427, 0.033054, 0.047472, 0.299575, 0.856462"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[10]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[10] */ + +pin("usb_io_pu_cal_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\ + "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\ + "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\ + "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\ + "0.858742, 0.881931, 0.919078, 1.324622, 2.214868"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449964",\ + "0.051871, 0.077785, 0.129094, 0.852080, 2.449965",\ + "0.051946, 0.077865, 0.129119, 0.852080, 2.449965",\ + "0.052034, 0.077959, 0.129147, 0.852081, 2.449965",\ + "0.052292, 0.078232, 0.129231, 0.852081, 2.449997"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.209465, 0.219196, 0.232970, 0.371719, 0.677621",\ + "0.298173, 0.307904, 0.321678, 0.460428, 0.766330",\ + "0.393912, 0.403643, 0.417418, 0.556169, 0.862071",\ + "0.463358, 0.473091, 0.486867, 0.625618, 0.931520",\ + "0.828290, 0.838027, 0.851809, 0.990566, 1.296468"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025267, 0.034187, 0.048739, 0.301161, 0.860107",\ + "0.025267, 0.034187, 0.048740, 0.301161, 0.860107",\ + "0.025267, 0.034188, 0.048743, 0.301161, 0.860107",\ + "0.025268, 0.034189, 0.048747, 0.301161, 0.860107",\ + "0.025282, 0.034204, 0.048767, 0.301161, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.202317, 0.221942, 0.257390, 0.661745, 1.553622",\ + "0.290456, 0.310081, 0.345529, 0.749884, 1.641761",\ + "0.379864, 0.399489, 0.434937, 0.839292, 1.731169",\ + "0.443880, 0.463505, 0.498953, 0.903308, 1.795185",\ + "0.771045, 0.790669, 0.826116, 1.230471, 2.122348"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444972",\ + "0.037486, 0.066519, 0.127980, 0.850725, 2.444969"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.178388, 0.187993, 0.201627, 0.340263, 0.646171",\ + "0.265760, 0.275365, 0.289000, 0.427635, 0.733544",\ + "0.345043, 0.355588, 0.369648, 0.508490, 0.814398",\ + "0.399593, 0.410134, 0.424192, 0.564475, 0.869603",\ + "0.684147, 0.694701, 0.708766, 0.849054, 1.154177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\ + "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\ + "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\ + "0.024411, 0.033033, 0.047459, 0.299575, 0.856462",\ + "0.024446, 0.033071, 0.047472, 0.299576, 0.856462"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[9]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[9] */ + +pin("usb_io_pu_cal_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310563, 0.333600, 0.370684, 0.776237, 1.666485",\ + "0.397928, 0.420965, 0.458048, 0.863602, 1.753849",\ + "0.478891, 0.501955, 0.539050, 0.944602, 1.834849",\ + "0.536743, 0.559839, 0.596947, 1.002497, 1.892744",\ + "0.858742, 0.881931, 0.919078, 1.324622, 2.214868"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051871, 0.077785, 0.129094, 0.852080, 2.449966",\ + "0.051946, 0.077865, 0.129119, 0.852080, 2.449966",\ + "0.052034, 0.077959, 0.129147, 0.852081, 2.449966",\ + "0.052292, 0.078232, 0.129231, 0.852081, 2.449966"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.209465, 0.219196, 0.232970, 0.371719, 0.677621",\ + "0.297931, 0.307661, 0.321435, 0.460184, 0.766087",\ + "0.393912, 0.403643, 0.417418, 0.556169, 0.862071",\ + "0.463358, 0.473091, 0.486867, 0.625618, 0.931520",\ + "0.828290, 0.838027, 0.851809, 0.990566, 1.296468"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025267, 0.034187, 0.048739, 0.301161, 0.860107",\ + "0.025267, 0.034187, 0.048739, 0.301161, 0.860107",\ + "0.025267, 0.034188, 0.048743, 0.301161, 0.860107",\ + "0.025268, 0.034189, 0.048747, 0.301161, 0.860107",\ + "0.025282, 0.034204, 0.048767, 0.301161, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.248424, 0.271436, 0.308509, 0.714064, 1.604311",\ + "0.336713, 0.359725, 0.396797, 0.802353, 1.692600",\ + "0.429673, 0.449299, 0.484746, 0.889101, 1.780978",\ + "0.486001, 0.505626, 0.541074, 0.945429, 1.837306",\ + "0.771045, 0.790669, 0.826116, 1.230471, 2.122348"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444973",\ + "0.037489, 0.066522, 0.127980, 0.850724, 2.444972",\ + "0.037486, 0.066519, 0.127980, 0.850725, 2.444969"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.184129, 0.194678, 0.208740, 0.349027, 0.654152",\ + "0.268945, 0.279493, 0.293555, 0.433842, 0.738967",\ + "0.345043, 0.355588, 0.369648, 0.509933, 0.815059",\ + "0.399593, 0.410134, 0.424192, 0.564475, 0.869603",\ + "0.684147, 0.694701, 0.708766, 0.849054, 1.154177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\ + "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\ + "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\ + "0.024415, 0.033034, 0.047459, 0.299575, 0.856462",\ + "0.024441, 0.033067, 0.047472, 0.299576, 0.856462"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[8]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[8] */ + +pin("usb_io_pu_cal_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310638, 0.333683, 0.370769, 0.776322, 1.666569",\ + "0.398002, 0.421047, 0.458133, 0.863687, 1.753934",\ + "0.478900, 0.501952, 0.539042, 0.944594, 1.834842",\ + "0.536750, 0.559833, 0.596935, 1.002486, 1.892733",\ + "0.841468, 0.864657, 0.901804, 1.307347, 2.197594"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051891, 0.077808, 0.129101, 0.852080, 2.449966",\ + "0.051892, 0.077808, 0.129101, 0.852080, 2.449966",\ + "0.051912, 0.077829, 0.129108, 0.852080, 2.449966",\ + "0.051998, 0.077921, 0.129136, 0.852080, 2.449966",\ + "0.052293, 0.078232, 0.129231, 0.852081, 2.450003"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.213971, 0.224767, 0.239042, 0.379500, 0.684663",\ + "0.302629, 0.313425, 0.327700, 0.468158, 0.773321",\ + "0.398375, 0.409171, 0.423447, 0.563905, 0.869068",\ + "0.467906, 0.478703, 0.492979, 0.633438, 0.938602",\ + "0.835457, 0.846260, 0.860543, 1.001007, 1.306175"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025238, 0.034155, 0.048727, 0.301163, 0.860108",\ + "0.025238, 0.034155, 0.048727, 0.301163, 0.860108",\ + "0.025238, 0.034156, 0.048728, 0.301163, 0.860108",\ + "0.025240, 0.034158, 0.048730, 0.301163, 0.860108",\ + "0.025257, 0.034176, 0.048751, 0.301163, 0.860108"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.205226, 0.224853, 0.260301, 0.664656, 1.556533",\ + "0.293604, 0.313232, 0.348681, 0.753036, 1.644913",\ + "0.383357, 0.402977, 0.438423, 0.842777, 1.734654",\ + "0.447610, 0.467222, 0.502663, 0.907016, 1.798893",\ + "0.789341, 0.809115, 0.844630, 1.249013, 2.140893"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\ + "0.037493, 0.066493, 0.127978, 0.850658, 2.444959",\ + "0.037854, 0.066833, 0.128000, 0.850658, 2.444959"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.176807, 0.187341, 0.201395, 0.341364, 0.646807",\ + "0.264176, 0.274709, 0.288763, 0.428735, 0.734175",\ + "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\ + "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\ + "0.683921, 0.693531, 0.707168, 0.845803, 1.151711"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047450, 0.299575, 0.856488",\ + "0.024427, 0.033054, 0.047464, 0.299575, 0.856488"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[7]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[7] */ + +pin("usb_io_pu_cal_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.310638, 0.333683, 0.370769, 0.776322, 1.666569",\ + "0.398002, 0.421047, 0.458133, 0.863687, 1.753934",\ + "0.478900, 0.501952, 0.539042, 0.944594, 1.834842",\ + "0.536750, 0.559833, 0.596935, 1.002486, 1.892733",\ + "0.841468, 0.864657, 0.901804, 1.307347, 2.197594"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.051891, 0.077808, 0.129101, 0.852080, 2.449966",\ + "0.051892, 0.077808, 0.129101, 0.852080, 2.449966",\ + "0.051912, 0.077829, 0.129108, 0.852080, 2.449966",\ + "0.051998, 0.077921, 0.129136, 0.852080, 2.449966",\ + "0.052293, 0.078232, 0.129231, 0.852081, 2.450003"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.213971, 0.224767, 0.239042, 0.379500, 0.684663",\ + "0.302629, 0.313425, 0.327700, 0.468158, 0.773321",\ + "0.398375, 0.409171, 0.423447, 0.563905, 0.869068",\ + "0.467906, 0.478703, 0.492979, 0.633438, 0.938602",\ + "0.835457, 0.846260, 0.860543, 1.001007, 1.306175"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025238, 0.034155, 0.048724, 0.301163, 0.860108",\ + "0.025238, 0.034155, 0.048724, 0.301163, 0.860108",\ + "0.025238, 0.034156, 0.048727, 0.301163, 0.860108",\ + "0.025240, 0.034158, 0.048730, 0.301163, 0.860108",\ + "0.025257, 0.034176, 0.048750, 0.301163, 0.860108"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.219758, 0.239385, 0.274833, 0.679189, 1.571066",\ + "0.308173, 0.327801, 0.363249, 0.767605, 1.659482",\ + "0.402556, 0.422183, 0.457632, 0.861987, 1.753864",\ + "0.469866, 0.490242, 0.525690, 0.930046, 1.821923",\ + "0.795255, 0.814880, 0.850328, 1.254683, 2.146560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.037493, 0.066526, 0.127980, 0.850723, 2.444963",\ + "0.037493, 0.066526, 0.127980, 0.850723, 2.444963",\ + "0.037493, 0.066525, 0.127980, 0.850723, 2.444963",\ + "0.037493, 0.066525, 0.127980, 0.850723, 2.444962",\ + "0.037489, 0.066522, 0.127980, 0.850723, 2.444959"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.176807, 0.187341, 0.201395, 0.341676, 0.646807",\ + "0.264176, 0.274709, 0.288763, 0.429043, 0.734175",\ + "0.344994, 0.354592, 0.368223, 0.506860, 0.812768",\ + "0.399528, 0.409125, 0.422756, 0.561393, 0.867301",\ + "0.683921, 0.693531, 0.707168, 0.845803, 1.151711"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047448, 0.299575, 0.856488",\ + "0.024391, 0.033017, 0.047450, 0.299575, 0.856488",\ + "0.024427, 0.033054, 0.047464, 0.299575, 0.856488"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[6]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[6] */ + +pin("usb_io_pu_cal_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320620, 0.341983, 0.378211, 0.782894, 1.674796",\ + "0.407985, 0.429348, 0.465575, 0.870258, 1.762161",\ + "0.488889, 0.510256, 0.546486, 0.951170, 1.843073",\ + "0.546764, 0.568152, 0.604391, 1.009078, 1.900981",\ + "0.851568, 0.873026, 0.909296, 1.313997, 2.205901"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044601, 0.070156, 0.128218, 0.852056, 2.450125",\ + "0.044663, 0.070159, 0.128218, 0.852056, 2.450125",\ + "0.044669, 0.070166, 0.128219, 0.852056, 2.450125",\ + "0.044669, 0.070209, 0.128222, 0.852056, 2.450127",\ + "0.046118, 0.071698, 0.128231, 0.852061, 2.450134"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216513, 0.226251, 0.240034, 0.378792, 0.684694",\ + "0.305171, 0.314909, 0.328692, 0.467450, 0.773352",\ + "0.400916, 0.410655, 0.424439, 0.563197, 0.869098",\ + "0.470448, 0.480187, 0.493971, 0.632730, 0.938632",\ + "0.838001, 0.847745, 0.861536, 1.000300, 1.306202"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048771, 0.301166, 0.860107",\ + "0.025213, 0.034127, 0.048771, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048772, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048774, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048795, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\ + "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\ + "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\ + "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041716, 0.070054, 0.126726, 0.849962, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.175899, 0.186544, 0.200656, 0.340982, 0.646065",\ + "0.263271, 0.273916, 0.288028, 0.428355, 0.733437",\ + "0.344128, 0.354771, 0.368883, 0.509209, 0.814291",\ + "0.401818, 0.412460, 0.426571, 0.566896, 0.871980",\ + "0.705550, 0.716209, 0.730328, 0.870579, 1.175736"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024130, 0.032772, 0.047558, 0.299569, 0.856133",\ + "0.024130, 0.032772, 0.047558, 0.299569, 0.856133",\ + "0.024130, 0.032772, 0.047558, 0.299569, 0.856133",\ + "0.024130, 0.032776, 0.047558, 0.299569, 0.856133",\ + "0.024160, 0.032809, 0.047574, 0.299570, 0.856133"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[5]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[5] */ + +pin("usb_io_pu_cal_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320620, 0.341983, 0.378211, 0.782894, 1.674796",\ + "0.407985, 0.429348, 0.465575, 0.870258, 1.762161",\ + "0.488889, 0.510256, 0.546486, 0.951170, 1.843073",\ + "0.546764, 0.568152, 0.604391, 1.009078, 1.900981",\ + "0.851568, 0.873026, 0.909296, 1.313997, 2.205901"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128218, 0.852056, 2.450125",\ + "0.044695, 0.070193, 0.128219, 0.852056, 2.450125",\ + "0.044695, 0.070209, 0.128222, 0.852056, 2.450127",\ + "0.044695, 0.070356, 0.128231, 0.852056, 2.450134"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216513, 0.226251, 0.240034, 0.378792, 0.684694",\ + "0.305171, 0.314909, 0.328692, 0.467450, 0.773352",\ + "0.400916, 0.410655, 0.424439, 0.563197, 0.869098",\ + "0.470448, 0.480187, 0.493971, 0.632730, 0.938632",\ + "0.838001, 0.847745, 0.861536, 1.000300, 1.306202"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048771, 0.301166, 0.860107",\ + "0.025212, 0.034126, 0.048771, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048772, 0.301166, 0.860107",\ + "0.025218, 0.034133, 0.048774, 0.301166, 0.860107",\ + "0.025235, 0.034151, 0.048795, 0.301166, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.238935, 0.260283, 0.296504, 0.701185, 1.593087",\ + "0.327362, 0.348711, 0.384931, 0.789612, 1.681514",\ + "0.416458, 0.437806, 0.474027, 0.878708, 1.770610",\ + "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041711, 0.070060, 0.126728, 0.849963, 2.447347",\ + "0.041716, 0.070054, 0.126726, 0.849962, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.179257, 0.188774, 0.202365, 0.341012, 0.646923",\ + "0.266626, 0.276142, 0.289732, 0.428379, 0.734291",\ + "0.347482, 0.356996, 0.370585, 0.509232, 0.815144",\ + "0.405200, 0.414714, 0.428304, 0.566951, 0.872863",\ + "0.708812, 0.718338, 0.731933, 0.870579, 1.176490"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024130, 0.032772, 0.047559, 0.299569, 0.856139",\ + "0.024130, 0.032772, 0.047559, 0.299569, 0.856139",\ + "0.024130, 0.032772, 0.047559, 0.299569, 0.856139",\ + "0.024130, 0.032776, 0.047559, 0.299569, 0.856139",\ + "0.024160, 0.032809, 0.047572, 0.299570, 0.856139"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[4]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[4] */ + +pin("usb_io_pu_cal_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\ + "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\ + "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\ + "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\ + "0.851113, 0.872490, 0.908724, 1.313410, 2.205313"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.046369, 0.071964, 0.128220, 0.852062, 2.450126"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\ + "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\ + "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\ + "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\ + "0.837901, 0.847639, 0.861421, 1.000178, 1.306080"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025202, 0.034115, 0.048744, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048744, 0.301167, 0.860107",\ + "0.025203, 0.034116, 0.048746, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048746, 0.301167, 0.860107",\ + "0.025222, 0.034137, 0.048767, 0.301167, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.197396, 0.217798, 0.253787, 0.659515, 1.549779",\ + "0.285773, 0.306177, 0.342166, 0.747894, 1.638158",\ + "0.375534, 0.395928, 0.431912, 0.837641, 1.727905",\ + "0.439799, 0.460179, 0.496157, 0.901887, 1.792151",\ + "0.781328, 0.801955, 0.838037, 1.243750, 2.134013"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\ + "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\ + "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\ + "0.041723, 0.069999, 0.126709, 0.849959, 2.447141",\ + "0.041728, 0.070141, 0.126932, 0.849959, 2.447141"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.177011, 0.187648, 0.201756, 0.342079, 0.647165",\ + "0.264382, 0.275019, 0.289127, 0.429450, 0.734536",\ + "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\ + "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\ + "0.681430, 0.692081, 0.706196, 0.846525, 1.151605"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024132, 0.032784, 0.047567, 0.299569, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[3]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[3] */ + +pin("usb_io_pu_cal_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\ + "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\ + "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\ + "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\ + "0.851113, 0.872490, 0.908724, 1.313410, 2.205313"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.044702, 0.070201, 0.128220, 0.852056, 2.450126",\ + "0.046369, 0.071964, 0.128220, 0.852062, 2.450126"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\ + "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\ + "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\ + "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\ + "0.837901, 0.847639, 0.861421, 1.000178, 1.306080"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025200, 0.034112, 0.048744, 0.301167, 0.860107",\ + "0.025200, 0.034112, 0.048744, 0.301167, 0.860107",\ + "0.025202, 0.034115, 0.048746, 0.301167, 0.860107",\ + "0.025205, 0.034118, 0.048746, 0.301166, 0.860107",\ + "0.025221, 0.034136, 0.048767, 0.301165, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.211928, 0.232331, 0.268319, 0.674047, 1.564311",\ + "0.300343, 0.320746, 0.356735, 0.762463, 1.652727",\ + "0.394726, 0.415129, 0.451117, 0.856845, 1.747110",\ + "0.462784, 0.483187, 0.519176, 0.924904, 1.815168",\ + "0.787427, 0.807827, 0.843815, 1.249543, 2.139807"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041723, 0.070068, 0.126730, 0.849961, 2.447344",\ + "0.041723, 0.070068, 0.126730, 0.849961, 2.447344",\ + "0.041723, 0.070068, 0.126730, 0.849961, 2.447344",\ + "0.041723, 0.070068, 0.126730, 0.849961, 2.447345",\ + "0.041728, 0.070061, 0.126728, 0.849959, 2.447347"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.181588, 0.192225, 0.206333, 0.346656, 0.651742",\ + "0.266400, 0.277038, 0.291146, 0.431469, 0.736554",\ + "0.342508, 0.353145, 0.367252, 0.507575, 0.812661",\ + "0.397042, 0.407678, 0.421785, 0.562107, 0.867194",\ + "0.681430, 0.692081, 0.706196, 0.846525, 1.151605"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024102, 0.032747, 0.047552, 0.299568, 0.856157",\ + "0.024132, 0.032784, 0.047567, 0.299569, 0.856157"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[2]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[2] */ + +pin("usb_io_pu_cal_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\ + "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\ + "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\ + "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\ + "0.851113, 0.872490, 0.908724, 1.313410, 2.205313"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044601, 0.070181, 0.128220, 0.852056, 2.450126",\ + "0.044663, 0.070181, 0.128220, 0.852056, 2.450126",\ + "0.044669, 0.070181, 0.128220, 0.852056, 2.450126",\ + "0.044669, 0.070181, 0.128220, 0.852056, 2.450126",\ + "0.046118, 0.071698, 0.128220, 0.852061, 2.450126"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\ + "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\ + "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\ + "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\ + "0.837901, 0.847639, 0.861421, 1.000178, 1.306080"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048744, 0.301166, 0.860107",\ + "0.025213, 0.034127, 0.048744, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048746, 0.301165, 0.860107",\ + "0.025218, 0.034133, 0.048746, 0.301165, 0.860107",\ + "0.025235, 0.034151, 0.048767, 0.301164, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.194489, 0.214889, 0.250877, 0.656605, 1.546869",\ + "0.282628, 0.303028, 0.339015, 0.744743, 1.635008",\ + "0.372036, 0.392436, 0.428424, 0.834152, 1.724416",\ + "0.436052, 0.456452, 0.492440, 0.898167, 1.788432",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041728, 0.070054, 0.126726, 0.849959, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.175899, 0.186544, 0.200656, 0.340982, 0.646065",\ + "0.263271, 0.273916, 0.288028, 0.428355, 0.733437",\ + "0.344128, 0.354771, 0.368883, 0.509209, 0.814291",\ + "0.401818, 0.412460, 0.426571, 0.566896, 0.871980",\ + "0.705550, 0.716209, 0.730328, 0.870660, 1.175736"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\ + "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\ + "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\ + "0.024102, 0.032747, 0.047558, 0.299568, 0.856133",\ + "0.024132, 0.032784, 0.047574, 0.299569, 0.856133"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[1]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[1] */ + +pin("usb_io_pu_cal_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044612 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_io_pu_cal_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.320745, 0.342120, 0.378352, 0.783037, 1.674940",\ + "0.408109, 0.429484, 0.465717, 0.870402, 1.762305",\ + "0.488983, 0.510358, 0.546591, 0.951276, 1.843179",\ + "0.546734, 0.568108, 0.604341, 1.009026, 1.900929",\ + "0.851113, 0.872490, 0.908724, 1.313410, 2.205313"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044695, 0.070193, 0.128220, 0.852056, 2.450126",\ + "0.044688, 0.070187, 0.128220, 0.852056, 2.450126"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.216415, 0.226147, 0.239922, 0.378673, 0.684575",\ + "0.304894, 0.314626, 0.328401, 0.467152, 0.773054",\ + "0.400819, 0.410552, 0.424328, 0.563079, 0.868981",\ + "0.469454, 0.479186, 0.492962, 0.631714, 0.937616",\ + "0.837901, 0.847639, 0.861421, 1.000178, 1.306080"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.025212, 0.034126, 0.048744, 0.301166, 0.860107",\ + "0.025212, 0.034126, 0.048744, 0.301166, 0.860107",\ + "0.025216, 0.034130, 0.048746, 0.301165, 0.860107",\ + "0.025218, 0.034133, 0.048746, 0.301165, 0.860107",\ + "0.025235, 0.034151, 0.048767, 0.301164, 0.860107"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.253595, 0.273995, 0.309982, 0.715710, 1.605975",\ + "0.340966, 0.361366, 0.397353, 0.803081, 1.693346",\ + "0.421845, 0.442245, 0.478233, 0.883961, 1.774225",\ + "0.478173, 0.498573, 0.534561, 0.940289, 1.830553",\ + "0.763219, 0.783617, 0.819604, 1.225332, 2.115596"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041723, 0.070060, 0.126728, 0.849961, 2.447347",\ + "0.041728, 0.070054, 0.126726, 0.849959, 2.447349"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.187072, 0.197718, 0.211831, 0.352158, 0.657240",\ + "0.275510, 0.286157, 0.300270, 0.440597, 0.745678",\ + "0.366248, 0.376893, 0.391005, 0.531331, 0.836413",\ + "0.431562, 0.442205, 0.456315, 0.596641, 0.901724",\ + "0.774613, 0.785269, 0.799387, 0.939719, 1.244796"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.000583, 0.001725, 0.015098, 0.044612"); + values ( "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\ + "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\ + "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\ + "0.024102, 0.032747, 0.047559, 0.299568, 0.856139",\ + "0.024132, 0.032784, 0.047572, 0.299569, 0.856139"); + } + + } /* end of arc clk_ast_tlul_i_usb_io_pu_cal_o[0]_redg_min*/ + +} /* end of pin usb_io_pu_cal_o[0] */ +} /* end of bus usb_io_pu_cal_o */ + +pin("adc_pd_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000990 ; + + /* Other user defined attributes. */ + original_pin : adc_pd_i; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.145974, 0.070413, 0.002322, -0.008532, 0.040411",\ + "0.237817, 0.162519, 0.094482, 0.084652, 0.136438",\ + "0.327313, 0.252083, 0.184412, 0.176262, 0.232381",\ + "0.476369, 0.401228, 0.333138, 0.324719, 0.380566",\ + "0.727129, 0.652156, 0.582810, 0.572596, 0.624823"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.143537, 0.097803, 0.067619, 0.059035, 0.070038",\ + "0.237266, 0.190708, 0.160460, 0.151771, 0.162549",\ + "0.329371, 0.281569, 0.251215, 0.242361, 0.252794",\ + "0.482853, 0.435010, 0.403977, 0.394743, 0.404895",\ + "0.739407, 0.691484, 0.659103, 0.649115, 0.658707"); + } + + } /* end of arc clk_ast_adc_i_adc_pd_i_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.059104, 0.006478, 0.063764, 0.149867, 0.326932",\ + "-0.151184, -0.084885, -0.026675, 0.059343, 0.235088",\ + "-0.241063, -0.173618, -0.113766, -0.027872, 0.145596",\ + "-0.389953, -0.320592, -0.259252, -0.172562, 0.001425",\ + "-0.640054, -0.566890, -0.503114, -0.414430, -0.237640"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.075633, -0.033180, 0.001225, 0.107355, 0.367997",\ + "-0.168712, -0.126409, -0.091657, -0.008939, 0.184913",\ + "-0.259774, -0.217681, -0.182405, -0.135026, -0.041991",\ + "-0.408979, -0.365800, -0.330498, -0.282705, -0.188522",\ + "-0.657040, -0.611703, -0.576351, -0.527733, -0.431269"); + } + + } /* end of arc clk_ast_adc_i_adc_pd_i_hldr*/ + +} /* end of pin adc_pd_i */ + +pin("adc_a0_ai") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : adc_a0_ai; +} /* end of pin adc_a0_ai */ + +pin("adc_a1_ai") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : adc_a1_ai; +} /* end of pin adc_a1_ai */ +bus ( adc_chnsel_i ) { + + bus_type : BUS2_type5 ; + direction : input ; + +pin("adc_chnsel_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000460 ; + + /* Other user defined attributes. */ + original_pin : adc_chnsel_i[1]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.500117, 0.461902, 0.438325, 0.435047, 0.453355",\ + "0.595615, 0.557400, 0.533823, 0.530545, 0.548853",\ + "0.695525, 0.657310, 0.633733, 0.630455, 0.648763",\ + "0.875461, 0.837246, 0.813669, 0.810391, 0.828699",\ + "1.191947, 1.153731, 1.130154, 1.126876, 1.145184"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.605397, 0.537315, 0.507057, 0.526616, 0.751141",\ + "0.681420, 0.613337, 0.583080, 0.602638, 0.827164",\ + "0.783637, 0.715554, 0.685297, 0.704855, 0.929381",\ + "0.996963, 0.928735, 0.898477, 0.918181, 1.142707",\ + "1.384407, 1.315680, 1.285422, 1.305625, 1.530151"); + } + + } /* end of arc clk_ast_adc_i_adc_chnsel_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.108536, -0.069519, -0.039211, 0.000204, 0.221057",\ + "-0.207833, -0.168834, -0.138446, -0.098987, 0.125559",\ + "-0.311546, -0.272599, -0.241997, -0.202419, 0.025649",\ + "-0.492274, -0.453433, -0.422380, -0.382553, -0.154287",\ + "-0.791907, -0.753246, -0.721402, -0.681127, -0.470772"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.305777, -0.243225, -0.192080, -0.118367, 0.030759",\ + "-0.381816, -0.319265, -0.268119, -0.194406, -0.045281",\ + "-0.483977, -0.421325, -0.370075, -0.296389, -0.147462",\ + "-0.695975, -0.632864, -0.581137, -0.507574, -0.359554",\ + "-1.082510, -1.018340, -0.965517, -0.892237, -0.746305"); + } + + } /* end of arc clk_ast_adc_i_adc_chnsel_i[1]_hldr*/ + +} /* end of pin adc_chnsel_i[1] */ + +pin("adc_chnsel_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000438 ; + + /* Other user defined attributes. */ + original_pin : adc_chnsel_i[0]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.501910, 0.463695, 0.440118, 0.436840, 0.455148",\ + "0.598688, 0.560473, 0.536896, 0.533618, 0.551926",\ + "0.702673, 0.664458, 0.640881, 0.637603, 0.655911",\ + "0.888472, 0.850257, 0.826680, 0.823402, 0.841710",\ + "1.218538, 1.180323, 1.156746, 1.153468, 1.171776"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.606473, 0.538391, 0.508134, 0.527691, 0.752217",\ + "0.684191, 0.616110, 0.585852, 0.605410, 0.829935",\ + "0.780333, 0.712252, 0.681994, 0.701552, 0.926077",\ + "0.980044, 0.911864, 0.881606, 0.901262, 1.125788",\ + "1.359676, 1.291175, 1.260918, 1.280894, 1.505420"); + } + + } /* end of arc clk_ast_adc_i_adc_chnsel_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.110705, -0.071690, -0.041374, -0.001954, 0.219264",\ + "-0.211096, -0.172099, -0.141707, -0.102245, 0.122486",\ + "-0.318758, -0.279812, -0.249205, -0.209624, 0.018501",\ + "-0.505427, -0.466584, -0.435539, -0.395715, -0.167298",\ + "-0.819228, -0.780572, -0.748725, -0.708453, -0.497364"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.306862, -0.244315, -0.193173, -0.119459, 0.029674",\ + "-0.384597, -0.322050, -0.270908, -0.197194, -0.048061",\ + "-0.480694, -0.418072, -0.366852, -0.293158, -0.144173",\ + "-0.679326, -0.616367, -0.564798, -0.491194, -0.342874",\ + "-1.058081, -0.994264, -0.941806, -0.868432, -0.721804"); + } + + } /* end of arc clk_ast_adc_i_adc_chnsel_i[0]_hldr*/ + +} /* end of pin adc_chnsel_i[0] */ +} /* end of bus adc_chnsel_i */ +bus ( adc_d_o ) { + + bus_type : BUS10_type8 ; + direction : output ; + +pin("adc_d_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[9]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[9]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[9]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[9]_hldr*/ + +} /* end of pin adc_d_o[9] */ + +pin("adc_d_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[8]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[8]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[8]_hldr*/ + +} /* end of pin adc_d_o[8] */ + +pin("adc_d_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[7]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[7]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[7]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[7]_hldr*/ + +} /* end of pin adc_d_o[7] */ + +pin("adc_d_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[6]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[6]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[6]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[6]_hldr*/ + +} /* end of pin adc_d_o[6] */ + +pin("adc_d_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[5]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[5]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[5]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[5]_hldr*/ + +} /* end of pin adc_d_o[5] */ + +pin("adc_d_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[4]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[4]_hldr*/ + +} /* end of pin adc_d_o[4] */ + +pin("adc_d_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[3]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[3]_hldr*/ + +} /* end of pin adc_d_o[3] */ + +pin("adc_d_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[2]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[2]_hldr*/ + +} /* end of pin adc_d_o[2] */ + +pin("adc_d_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[1]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[1]_hldr*/ + +} /* end of pin adc_d_o[1] */ + +pin("adc_d_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000474 ; + + /* Other user defined attributes. */ + original_pin : adc_d_o[0]; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.246589, 2.482563",\ + "0.023522, 0.294865, 0.630572, 1.246589, 2.482563",\ + "0.036913, 0.297173, 0.630608, 1.246589, 2.482563",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.482563",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183996, 0.385207, 0.758292, 1.504462",\ + "0.020571, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.021496, 0.184130, 0.385715, 0.758292, 1.504462",\ + "0.027055, 0.184687, 0.385715, 0.758292, 1.504742",\ + "0.042630, 0.188229, 0.385715, 0.758292, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.043083, 0.198120, 0.374256, 0.697785, 1.344843",\ + "0.128923, 0.285295, 0.461364, 0.784501, 1.430777",\ + "0.210274, 0.373426, 0.549322, 0.872125, 1.517732",\ + "0.345402, 0.527885, 0.703101, 1.025419, 1.670053",\ + "0.557160, 0.787678, 0.963834, 1.284789, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.018401, 0.293911, 0.628602, 1.245375, 2.473548",\ + "0.023522, 0.294865, 0.630572, 1.245375, 2.473548",\ + "0.036913, 0.297173, 0.630608, 1.245450, 2.473548",\ + "0.064917, 0.305223, 0.630841, 1.247228, 2.473548",\ + "0.122287, 0.339635, 0.636985, 1.249173, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.062966, 0.171021, 0.282962, 0.487566, 0.896774",\ + "0.150539, 0.258340, 0.370243, 0.574871, 0.984127",\ + "0.230685, 0.338682, 0.450270, 0.654899, 1.064159",\ + "0.365948, 0.476706, 0.588287, 0.792199, 1.200024",\ + "0.578145, 0.699559, 0.811451, 1.015162, 1.422583"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000474, 0.073473, 0.160858, 0.321243, 0.642011"); + values ( "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.020571, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.021496, 0.183210, 0.383705, 0.756065, 1.500784",\ + "0.027055, 0.184687, 0.384226, 0.757731, 1.504742",\ + "0.042630, 0.188229, 0.384226, 0.757731, 1.504742"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.203067, 0.157249, 0.127058, 0.118464, 0.129443",\ + "0.207936, 0.162118, 0.131927, 0.123333, 0.134312",\ + "0.282684, 0.236865, 0.206674, 0.198080, 0.209060",\ + "0.376050, 0.329912, 0.299696, 0.291061, 0.301953",\ + "0.789608, 0.741801, 0.711356, 0.702451, 0.712846"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.248522, 0.173196, 0.105012, 0.094508, 0.144555",\ + "0.253666, 0.178340, 0.110157, 0.099653, 0.149700",\ + "0.325959, 0.250633, 0.182449, 0.171946, 0.221993",\ + "0.430477, 0.355166, 0.287060, 0.276913, 0.327879",\ + "0.906305, 0.831103, 0.763471, 0.755707, 0.812875"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018401, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.129733, -0.087286, -0.052870, 0.052534, 0.311104",\ + "-0.134675, -0.092227, -0.057811, 0.047593, 0.306162",\ + "-0.208828, -0.166380, -0.131964, -0.026560, 0.232009",\ + "-0.298006, -0.255611, -0.221074, -0.123848, 0.111390",\ + "-0.695505, -0.653392, -0.618114, -0.570728, -0.477670"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020571, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.128225, -0.062545, -0.005224, 0.080862, 0.257839",\ + "-0.134070, -0.068391, -0.011070, 0.075016, 0.251993",\ + "-0.211053, -0.145374, -0.088052, -0.001967, 0.175010",\ + "-0.312522, -0.246536, -0.188774, -0.102722, 0.073645",\ + "-0.766129, -0.698256, -0.637868, -0.551957, -0.379066"); + } + + } /* end of arc clk_ast_adc_i_adc_d_o[0]_hldr*/ + +} /* end of pin adc_d_o[0] */ +} /* end of bus adc_d_o */ + +pin("adc_d_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000485 ; + + /* Other user defined attributes. */ + original_pin : adc_d_val_o; + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.043124, 0.198142, 0.374272, 0.697796, 1.344843",\ + "0.128968, 0.285317, 0.461380, 0.784513, 1.430777",\ + "0.210336, 0.373448, 0.549338, 0.872136, 1.517732",\ + "0.345497, 0.527907, 0.703118, 1.025430, 1.670053",\ + "0.557318, 0.787701, 0.963851, 1.284800, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.018442, 0.293953, 0.628634, 1.246610, 2.482563",\ + "0.023559, 0.294907, 0.630604, 1.246610, 2.482563",\ + "0.036948, 0.297215, 0.630640, 1.246610, 2.482563",\ + "0.064957, 0.305264, 0.630873, 1.247249, 2.482563",\ + "0.122341, 0.339671, 0.637017, 1.249194, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.062980, 0.171026, 0.282963, 0.487563, 0.896764",\ + "0.150552, 0.258345, 0.370244, 0.574868, 0.984118",\ + "0.230698, 0.338686, 0.450271, 0.654897, 1.064149",\ + "0.365964, 0.476710, 0.588288, 0.792197, 1.200014",\ + "0.578168, 0.699563, 0.811453, 1.015159, 1.422574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.020581, 0.184004, 0.385209, 0.758288, 1.504444",\ + "0.020581, 0.184139, 0.385717, 0.758288, 1.504444",\ + "0.021507, 0.184139, 0.385717, 0.758288, 1.504444",\ + "0.027064, 0.184695, 0.385717, 0.758288, 1.504725",\ + "0.042640, 0.188237, 0.385717, 0.758288, 1.504725"); + } + + } /* end of arc clk_ast_adc_i_adc_d_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_adc_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.043124, 0.198142, 0.374272, 0.697796, 1.344843",\ + "0.128968, 0.285317, 0.461380, 0.784513, 1.430777",\ + "0.210336, 0.373448, 0.549338, 0.872136, 1.517732",\ + "0.345497, 0.527907, 0.703118, 1.025430, 1.670053",\ + "0.557318, 0.787701, 0.963851, 1.284800, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.018442, 0.293953, 0.628634, 1.245396, 2.473548",\ + "0.023559, 0.294907, 0.630604, 1.245396, 2.473548",\ + "0.036948, 0.297215, 0.630640, 1.245471, 2.473548",\ + "0.064957, 0.305264, 0.630873, 1.247249, 2.473548",\ + "0.122341, 0.339671, 0.637017, 1.249194, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.062980, 0.171026, 0.282963, 0.487563, 0.896764",\ + "0.150552, 0.258345, 0.370244, 0.574868, 0.984118",\ + "0.230698, 0.338686, 0.450271, 0.654897, 1.064149",\ + "0.365964, 0.476710, 0.588288, 0.792197, 1.200014",\ + "0.578168, 0.699563, 0.811453, 1.015159, 1.422574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000485, 0.073484, 0.160867, 0.321248, 0.642011"); + values ( "0.020581, 0.183219, 0.383707, 0.756060, 1.500767",\ + "0.020581, 0.183219, 0.383707, 0.756060, 1.500767",\ + "0.021507, 0.183219, 0.383707, 0.756060, 1.500767",\ + "0.027064, 0.184695, 0.384228, 0.757727, 1.504725",\ + "0.042640, 0.188237, 0.384228, 0.757727, 1.504725"); + } + + } /* end of arc clk_ast_adc_i_adc_d_val_o_redg_min*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018442, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.243976, 0.197294, 0.167037, 0.158332, 0.169076",\ + "0.249724, 0.203042, 0.172784, 0.164080, 0.174823",\ + "0.330128, 0.283446, 0.253188, 0.244484, 0.255227",\ + "0.421667, 0.374985, 0.344728, 0.336023, 0.346766",\ + "0.857546, 0.810300, 0.779998, 0.771221, 0.781810"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.235882, 0.160549, 0.092329, 0.081659, 0.131277",\ + "0.241065, 0.165732, 0.097513, 0.086843, 0.136460",\ + "0.320960, 0.245631, 0.177435, 0.166874, 0.216773",\ + "0.424142, 0.348830, 0.280724, 0.270576, 0.321539",\ + "0.869196, 0.793968, 0.726309, 0.718213, 0.774472"); + } + + } /* end of arc clk_ast_adc_i_adc_d_val_o_stupr*/ + + timing () { + related_pin : "clk_ast_adc_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.018442, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.172771, -0.130490, -0.095686, -0.016470, 0.167392",\ + "-0.178433, -0.136153, -0.101349, -0.022133, 0.161730",\ + "-0.256684, -0.214404, -0.179600, -0.100383, 0.083479",\ + "-0.345053, -0.302773, -0.267969, -0.188752, -0.004890",\ + "-0.762797, -0.720612, -0.685586, -0.621349, -0.480218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.121789, -0.056140, 0.001137, 0.087226, 0.264264",\ + "-0.127527, -0.061878, -0.004601, 0.081488, 0.258526",\ + "-0.211930, -0.146176, -0.088749, -0.002671, 0.174159",\ + "-0.309060, -0.243056, -0.185270, -0.099220, 0.077113",\ + "-0.732847, -0.665438, -0.605637, -0.519740, -0.346201"); + } + + } /* end of arc clk_ast_adc_i_adc_d_val_o_hldr*/ + +} /* end of pin adc_d_val_o */ + +pin("rng_en_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : rng_en_i; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.695925, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.782684, 0.674795"); + } + + } /* end of arc clk_ast_tlul_i_rng_en_i_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\ + "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923"); + } + + } /* end of arc clk_ast_tlul_i_rng_en_i_hldr*/ + +} /* end of pin rng_en_i */ + +pin("rng_fips_i") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : rng_fips_i; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.695925, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.782684, 0.674795"); + } + + } /* end of arc clk_ast_tlul_i_rng_fips_i_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\ + "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923"); + } + + } /* end of arc clk_ast_tlul_i_rng_fips_i_hldr*/ + +} /* end of pin rng_fips_i */ + +pin("rng_val_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : rng_val_o; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.043198, 0.198183, 0.374303, 0.697816, 1.344843",\ + "0.100770, 0.256465, 0.432811, 0.755524, 1.400950",\ + "0.234375, 0.400817, 0.576577, 0.899279, 1.544683",\ + "0.266829, 0.437889, 0.613486, 0.936071, 1.581241",\ + "0.557607, 0.787741, 0.963881, 1.284820, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.018518, 0.294029, 0.628692, 1.246649, 2.482563",\ + "0.020629, 0.294660, 0.630087, 1.246649, 2.482563",\ + "0.041968, 0.298715, 0.630739, 1.246649, 2.482563",\ + "0.048693, 0.300646, 0.630795, 1.246649, 2.482563",\ + "0.122440, 0.339737, 0.637074, 1.249232, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.063098, 0.171066, 0.282997, 0.487591, 0.896779",\ + "0.123042, 0.230894, 0.342842, 0.547360, 0.956396",\ + "0.254755, 0.363148, 0.474725, 0.679218, 1.088204",\ + "0.287224, 0.396275, 0.507850, 0.712171, 1.120812",\ + "0.578369, 0.699604, 0.811487, 1.015187, 1.422589"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.020669, 0.184077, 0.385272, 0.758339, 1.504472",\ + "0.020669, 0.184227, 0.385542, 0.758386, 1.504472",\ + "0.022583, 0.184227, 0.385542, 0.758386, 1.504472",\ + "0.023913, 0.184227, 0.385542, 0.758386, 1.504472",\ + "0.042731, 0.188308, 0.385542, 0.758386, 1.504752"); + } + + } /* end of arc clk_ast_rng_i_rng_val_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.043198, 0.198183, 0.374303, 0.697816, 1.344843",\ + "0.100770, 0.256465, 0.432811, 0.755524, 1.400950",\ + "0.234375, 0.400817, 0.576577, 0.899279, 1.544683",\ + "0.266829, 0.437889, 0.613486, 0.936071, 1.581241",\ + "0.557607, 0.787741, 0.963881, 1.284820, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.018518, 0.294029, 0.628692, 1.245563, 2.473548",\ + "0.020629, 0.294660, 0.630087, 1.245563, 2.473548",\ + "0.041968, 0.298715, 0.630739, 1.245824, 2.473548",\ + "0.048693, 0.300646, 0.630795, 1.246251, 2.473548",\ + "0.122440, 0.339737, 0.637074, 1.249232, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.063098, 0.171066, 0.282997, 0.487591, 0.896779",\ + "0.123042, 0.230894, 0.342842, 0.547360, 0.956396",\ + "0.254755, 0.363148, 0.474725, 0.679218, 1.088204",\ + "0.287224, 0.396275, 0.507850, 0.712171, 1.120812",\ + "0.578369, 0.699604, 0.811487, 1.015187, 1.422589"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.020669, 0.183553, 0.383962, 0.756493, 1.501555",\ + "0.020669, 0.183553, 0.383962, 0.756493, 1.501555",\ + "0.022583, 0.183553, 0.383962, 0.756493, 1.501555",\ + "0.023913, 0.183907, 0.384224, 0.757011, 1.502586",\ + "0.042731, 0.188308, 0.384291, 0.757778, 1.504752"); + } + + } /* end of arc clk_ast_rng_i_rng_val_o_redg_min*/ + +} /* end of pin rng_val_o */ +bus ( rng_b_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("rng_b_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001003 ; + + /* Other user defined attributes. */ + original_pin : rng_b_o[3]; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\ + "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\ + "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\ + "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\ + "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.044109, 0.189380, 0.386379, 0.758933, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\ + "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\ + "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\ + "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\ + "0.044109, 0.189380, 0.385129, 0.758326, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020388, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.036802, 0.036802, 0.036802, 0.036802, 0.036802",\ + "0.042346, 0.042346, 0.042346, 0.042346, 0.042346",\ + "0.109280, 0.109280, 0.109280, 0.109280, 0.109280",\ + "0.178232, 0.178232, 0.178232, 0.178232, 0.178232",\ + "0.458063, 0.458063, 0.458063, 0.458063, 0.458063"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022008, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.053733, 0.053733, 0.053733, 0.053733, 0.053733",\ + "0.060946, 0.060946, 0.060946, 0.060946, 0.060946",\ + "0.137682, 0.137682, 0.137682, 0.137682, 0.137682",\ + "0.226588, 0.226588, 0.226588, 0.226588, 0.226588",\ + "0.644240, 0.644240, 0.644240, 0.644240, 0.644240"); + } + + } /* end of arc clk_ast_tlul_i_rng_b_o[3]_cgsf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.020388, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.034468, -0.034468, -0.034468, -0.034468, -0.034468",\ + "-0.040015, -0.040015, -0.040015, -0.040015, -0.040015",\ + "-0.106260, -0.106260, -0.106260, -0.106260, -0.106260",\ + "-0.173208, -0.173208, -0.173208, -0.173208, -0.173208",\ + "-0.445027, -0.445027, -0.445027, -0.445027, -0.445027"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022008, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.046633, -0.046633, -0.046633, -0.046633, -0.046633",\ + "-0.053872, -0.053872, -0.053872, -0.053872, -0.053872",\ + "-0.131912, -0.131912, -0.131912, -0.131912, -0.131912",\ + "-0.220120, -0.220120, -0.220120, -0.220120, -0.220120",\ + "-0.629632, -0.629632, -0.629632, -0.629632, -0.629632"); + } + + } /* end of arc clk_ast_tlul_i_rng_b_o[3]_cghr*/ + +} /* end of pin rng_b_o[3] */ + +pin("rng_b_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001003 ; + + /* Other user defined attributes. */ + original_pin : rng_b_o[2]; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\ + "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\ + "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\ + "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\ + "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.044109, 0.189380, 0.386379, 0.758933, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\ + "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\ + "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\ + "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\ + "0.044109, 0.189380, 0.385129, 0.758326, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[2]_redg_min*/ + +} /* end of pin rng_b_o[2] */ + +pin("rng_b_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001003 ; + + /* Other user defined attributes. */ + original_pin : rng_b_o[1]; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\ + "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\ + "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\ + "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\ + "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.044109, 0.189380, 0.386379, 0.758933, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\ + "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\ + "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\ + "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\ + "0.044109, 0.189380, 0.385129, 0.758326, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[1]_redg_min*/ + +} /* end of pin rng_b_o[1] */ + +pin("rng_b_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001003 ; + + /* Other user defined attributes. */ + original_pin : rng_b_o[0]; + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.247608, 2.482563",\ + "0.022435, 0.296571, 0.631520, 1.247608, 2.482563",\ + "0.043575, 0.300601, 0.632171, 1.247608, 2.482563",\ + "0.050360, 0.302518, 0.632228, 1.247608, 2.482563",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.185188, 0.386108, 0.758886, 1.504440",\ + "0.022008, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.023991, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.025265, 0.185339, 0.386379, 0.758933, 1.504440",\ + "0.044109, 0.189380, 0.386379, 0.758933, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.045041, 0.199186, 0.375056, 0.698318, 1.344843",\ + "0.102677, 0.257471, 0.433562, 0.756025, 1.400950",\ + "0.237455, 0.401819, 0.577329, 0.899780, 1.544683",\ + "0.270266, 0.438889, 0.614237, 0.936571, 1.581241",\ + "0.564763, 0.788747, 0.964628, 1.285318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.020388, 0.295933, 0.630131, 1.246518, 2.473548",\ + "0.022435, 0.296571, 0.631520, 1.246518, 2.473548",\ + "0.043575, 0.300601, 0.632171, 1.246779, 2.473548",\ + "0.050360, 0.302518, 0.632228, 1.247206, 2.473548",\ + "0.124896, 0.341364, 0.638500, 1.250182, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.064894, 0.171688, 0.283456, 0.487892, 0.896762",\ + "0.124805, 0.231515, 0.343301, 0.547660, 0.956379",\ + "0.256621, 0.363767, 0.475184, 0.679518, 1.088186",\ + "0.289162, 0.396894, 0.508308, 0.712471, 1.120795",\ + "0.581429, 0.700226, 0.811944, 1.015486, 1.422571"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.022008, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.023991, 0.184659, 0.384798, 0.757040, 1.501523",\ + "0.025265, 0.185012, 0.385060, 0.757558, 1.502554",\ + "0.044109, 0.189380, 0.385129, 0.758326, 1.504720"); + } + + } /* end of arc clk_ast_rng_i_rng_b_o[0]_redg_min*/ + +} /* end of pin rng_b_o[0] */ +} /* end of bus rng_b_o */ +bus ( entropy_rsp_i ) { + + bus_type : BUS34_type9 ; + direction : input ; + +pin("entropy_rsp_i[33]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001563 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[33]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "1.119801, 1.062115, 1.000165, 1.001253, 1.020223",\ + "1.200891, 1.143205, 1.081255, 1.082343, 1.101313",\ + "1.316914, 1.259228, 1.197278, 1.198366, 1.217336",\ + "1.518457, 1.460771, 1.398821, 1.399909, 1.418879",\ + "1.859802, 1.802116, 1.740050, 1.741138, 1.760224"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.903123, 0.863686, 0.813020, 0.814108, 0.827330",\ + "1.003527, 0.964090, 0.913424, 0.914512, 0.927734",\ + "1.127836, 1.088399, 1.037733, 1.038821, 1.052043",\ + "1.347378, 1.307941, 1.257275, 1.258363, 1.271584",\ + "1.738717, 1.699280, 1.648614, 1.649702, 1.662924"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[33]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.168954, -0.118035, -0.021877, -0.003703, 0.217154",\ + "-0.249369, -0.198449, -0.102291, -0.084118, 0.136740",\ + "-0.329424, -0.278473, -0.182197, -0.164034, 0.056702",\ + "-0.457832, -0.406830, -0.310356, -0.292210, -0.071679",\ + "-0.639075, -0.587937, -0.490944, -0.472842, -0.252849"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.139897, -0.089049, 0.006833, 0.025029, 0.246173",\ + "-0.240100, -0.189184, -0.093041, -0.074866, 0.146007",\ + "-0.358064, -0.306668, -0.208689, -0.190671, 0.057939",\ + "-0.516949, -0.483468, -0.393287, -0.375391, -0.096605",\ + "-0.756377, -0.722936, -0.665170, -0.641259, -0.350671"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[33]_hldr*/ + +} /* end of pin entropy_rsp_i[33] */ + +pin("entropy_rsp_i[32]") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[32]; +} /* end of pin entropy_rsp_i[32] */ + +pin("entropy_rsp_i[31]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[31]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[31]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[31]_hldr*/ + +} /* end of pin entropy_rsp_i[31] */ + +pin("entropy_rsp_i[30]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[30]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[30]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[30]_hldr*/ + +} /* end of pin entropy_rsp_i[30] */ + +pin("entropy_rsp_i[29]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[29]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[29]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[29]_hldr*/ + +} /* end of pin entropy_rsp_i[29] */ + +pin("entropy_rsp_i[28]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[28]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[28]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[28]_hldr*/ + +} /* end of pin entropy_rsp_i[28] */ + +pin("entropy_rsp_i[27]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[27]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[27]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[27]_hldr*/ + +} /* end of pin entropy_rsp_i[27] */ + +pin("entropy_rsp_i[26]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[26]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[26]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[26]_hldr*/ + +} /* end of pin entropy_rsp_i[26] */ + +pin("entropy_rsp_i[25]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[25]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[25]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[25]_hldr*/ + +} /* end of pin entropy_rsp_i[25] */ + +pin("entropy_rsp_i[24]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[24]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[24]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[24]_hldr*/ + +} /* end of pin entropy_rsp_i[24] */ + +pin("entropy_rsp_i[23]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[23]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[23]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[23]_hldr*/ + +} /* end of pin entropy_rsp_i[23] */ + +pin("entropy_rsp_i[22]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[22]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[22]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[22]_hldr*/ + +} /* end of pin entropy_rsp_i[22] */ + +pin("entropy_rsp_i[21]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[21]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[21]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[21]_hldr*/ + +} /* end of pin entropy_rsp_i[21] */ + +pin("entropy_rsp_i[20]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[20]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[20]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[20]_hldr*/ + +} /* end of pin entropy_rsp_i[20] */ + +pin("entropy_rsp_i[19]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[19]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[19]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[19]_hldr*/ + +} /* end of pin entropy_rsp_i[19] */ + +pin("entropy_rsp_i[18]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[18]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[18]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[18]_hldr*/ + +} /* end of pin entropy_rsp_i[18] */ + +pin("entropy_rsp_i[17]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[17]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[17]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[17]_hldr*/ + +} /* end of pin entropy_rsp_i[17] */ + +pin("entropy_rsp_i[16]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[16]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[16]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[16]_hldr*/ + +} /* end of pin entropy_rsp_i[16] */ + +pin("entropy_rsp_i[15]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[15]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[15]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[15]_hldr*/ + +} /* end of pin entropy_rsp_i[15] */ + +pin("entropy_rsp_i[14]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[14]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[14]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[14]_hldr*/ + +} /* end of pin entropy_rsp_i[14] */ + +pin("entropy_rsp_i[13]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[13]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[13]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[13]_hldr*/ + +} /* end of pin entropy_rsp_i[13] */ + +pin("entropy_rsp_i[12]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[12]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[12]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[12]_hldr*/ + +} /* end of pin entropy_rsp_i[12] */ + +pin("entropy_rsp_i[11]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[11]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[11]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[11]_hldr*/ + +} /* end of pin entropy_rsp_i[11] */ + +pin("entropy_rsp_i[10]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[10]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[10]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[10]_hldr*/ + +} /* end of pin entropy_rsp_i[10] */ + +pin("entropy_rsp_i[9]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[9]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[9]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[9]_hldr*/ + +} /* end of pin entropy_rsp_i[9] */ + +pin("entropy_rsp_i[8]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[8]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[8]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[8]_hldr*/ + +} /* end of pin entropy_rsp_i[8] */ + +pin("entropy_rsp_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[7]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[7]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[7]_hldr*/ + +} /* end of pin entropy_rsp_i[7] */ + +pin("entropy_rsp_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[6]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[6]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[6]_hldr*/ + +} /* end of pin entropy_rsp_i[6] */ + +pin("entropy_rsp_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[5]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[5]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[5]_hldr*/ + +} /* end of pin entropy_rsp_i[5] */ + +pin("entropy_rsp_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[4]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[4]_hldr*/ + +} /* end of pin entropy_rsp_i[4] */ + +pin("entropy_rsp_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[3]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[3]_hldr*/ + +} /* end of pin entropy_rsp_i[3] */ + +pin("entropy_rsp_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[2]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[2]_hldr*/ + +} /* end of pin entropy_rsp_i[2] */ + +pin("entropy_rsp_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[1]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[1]_hldr*/ + +} /* end of pin entropy_rsp_i[1] */ + +pin("entropy_rsp_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001123 ; + + /* Other user defined attributes. */ + original_pin : entropy_rsp_i[0]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.202977, 0.164874, 0.114384, 0.115510, 0.129197",\ + "0.287655, 0.249552, 0.199062, 0.200188, 0.213875",\ + "0.378849, 0.340583, 0.290072, 0.291193, 0.304823",\ + "0.542220, 0.503561, 0.452999, 0.454109, 0.467602",\ + "0.818496, 0.778874, 0.728184, 0.729266, 0.742423"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.245106, 0.187436, 0.073491, 0.078675, 0.141673",\ + "0.333057, 0.275386, 0.161441, 0.166625, 0.229623",\ + "0.433433, 0.375759, 0.261891, 0.267131, 0.330810",\ + "0.619112, 0.561430, 0.447762, 0.453147, 0.518594",\ + "0.940670, 0.882965, 0.769819, 0.775584, 0.845650"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.134918, -0.101431, -0.043776, -0.018552, 0.287989",\ + "-0.219595, -0.186108, -0.128453, -0.103229, 0.203312",\ + "-0.310658, -0.277219, -0.219447, -0.195609, 0.094094",\ + "-0.473587, -0.440262, -0.382212, -0.361659, -0.111869",\ + "-0.749178, -0.716141, -0.657395, -0.645080, -0.495412"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.158345, -0.107350, -0.010904, 0.007245, 0.227804",\ + "-0.246288, -0.195293, -0.098847, -0.080698, 0.139861",\ + "-0.346722, -0.295637, -0.198845, -0.180726, 0.039476",\ + "-0.532525, -0.481205, -0.383518, -0.365475, -0.146201",\ + "-0.854381, -0.802448, -0.702421, -0.684578, -0.467728"); + } + + } /* end of arc clk_ast_es_i_entropy_rsp_i[0]_hldr*/ + +} /* end of pin entropy_rsp_i[0] */ +} /* end of bus entropy_rsp_i */ +bus ( entropy_req_o ) { + + bus_type : BUS1_type10 ; + direction : output ; + +pin("entropy_req_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : entropy_req_o[0]; + timing () { + related_pin : "clk_ast_es_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.041147, 0.197164, 0.373538, 0.697306, 1.344843",\ + "0.098611, 0.255444, 0.432048, 0.755015, 1.400950",\ + "0.230794, 0.399801, 0.575814, 0.898771, 1.544683",\ + "0.262809, 0.436873, 0.612723, 0.935562, 1.581241",\ + "0.549011, 0.786720, 0.963122, 1.284314, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.016407, 0.292097, 0.627231, 1.245675, 2.482563",\ + "0.018818, 0.292719, 0.628632, 1.245675, 2.482563",\ + "0.040240, 0.296800, 0.629285, 1.245675, 2.482563",\ + "0.046879, 0.298746, 0.629340, 1.245675, 2.482563",\ + "0.119467, 0.338085, 0.635627, 1.248267, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.061012, 0.170429, 0.282525, 0.487280, 0.896790",\ + "0.121003, 0.230257, 0.342370, 0.547049, 0.956407",\ + "0.252523, 0.362513, 0.474253, 0.678907, 1.088215",\ + "0.284909, 0.395640, 0.507378, 0.711860, 1.120823",\ + "0.574684, 0.698966, 0.811016, 1.014877, 1.422600"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.018854, 0.182937, 0.384410, 0.757771, 1.504492",\ + "0.018854, 0.183085, 0.384681, 0.757818, 1.504492",\ + "0.021110, 0.183085, 0.384681, 0.757818, 1.504492",\ + "0.022486, 0.183085, 0.384681, 0.757818, 1.504492",\ + "0.041128, 0.187207, 0.384681, 0.757818, 1.504772"); + } + + } /* end of arc clk_ast_es_i_entropy_req_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_es_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.041147, 0.197164, 0.373538, 0.697306, 1.344843",\ + "0.098611, 0.255444, 0.432048, 0.755015, 1.400950",\ + "0.230794, 0.399801, 0.575814, 0.898771, 1.544683",\ + "0.262809, 0.436873, 0.612723, 0.935562, 1.581241",\ + "0.549011, 0.786720, 0.963122, 1.284314, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.016407, 0.292097, 0.627231, 1.244593, 2.473548",\ + "0.018818, 0.292719, 0.628632, 1.244593, 2.473548",\ + "0.040240, 0.296800, 0.629285, 1.244855, 2.473548",\ + "0.046879, 0.298746, 0.629340, 1.245281, 2.473548",\ + "0.119467, 0.338085, 0.635627, 1.248267, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.061012, 0.170429, 0.282525, 0.487280, 0.896790",\ + "0.121003, 0.230257, 0.342370, 0.547049, 0.956407",\ + "0.252523, 0.362513, 0.474253, 0.678907, 1.088215",\ + "0.284909, 0.395640, 0.507378, 0.711860, 1.120823",\ + "0.574684, 0.698966, 0.811016, 1.014877, 1.422600"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.072998, 0.160503, 0.321005, 0.642011"); + values ( "0.018854, 0.182418, 0.383102, 0.755926, 1.501575",\ + "0.018854, 0.182418, 0.383102, 0.755926, 1.501575",\ + "0.021110, 0.182418, 0.383102, 0.755926, 1.501575",\ + "0.022486, 0.182773, 0.383362, 0.756444, 1.502606",\ + "0.041128, 0.187207, 0.383428, 0.757210, 1.504772"); + } + + } /* end of arc clk_ast_es_i_entropy_req_o[0]_redg_min*/ + +} /* end of pin entropy_req_o[0] */ +} /* end of bus entropy_req_o */ +bus ( fla_alert_src_i ) { + + bus_type : BUS2_type5 ; + direction : input ; + +pin("fla_alert_src_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000977 ; + + /* Other user defined attributes. */ + original_pin : fla_alert_src_i[1]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.160061, 0.122171, 0.071764, 0.072890, 0.086576",\ + "0.244155, 0.206260, 0.155798, 0.156930, 0.170689",\ + "0.325133, 0.287001, 0.236508, 0.237633, 0.251310",\ + "0.464429, 0.425692, 0.375119, 0.376227, 0.389693",\ + "0.687556, 0.647617, 0.596849, 0.597922, 0.610956"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.188609, 0.130944, 0.016876, 0.021970, 0.083878",\ + "0.276270, 0.218603, 0.104578, 0.109703, 0.171989",\ + "0.365048, 0.307375, 0.193490, 0.198718, 0.262247",\ + "0.519717, 0.462029, 0.348488, 0.353966, 0.420536",\ + "0.771986, 0.714301, 0.601221, 0.607099, 0.678536"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.092219, -0.058653, -0.001237, 0.026220, 0.359896",\ + "-0.176268, -0.142720, -0.085214, -0.058223, 0.269794",\ + "-0.257056, -0.223577, -0.165901, -0.140924, 0.162616",\ + "-0.395865, -0.362566, -0.304455, -0.284621, -0.043580",\ + "-0.617889, -0.584914, -0.525934, -0.516364, -0.400062"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.101777, -0.050927, 0.044966, 0.063162, 0.284294",\ + "-0.189465, -0.138565, -0.042479, -0.024300, 0.196634",\ + "-0.278331, -0.227265, -0.130550, -0.112424, 0.107856",\ + "-0.433215, -0.381745, -0.283488, -0.265494, -0.046811",\ + "-0.685809, -0.633481, -0.532401, -0.514612, -0.298423"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_hldr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.346181, 0.303572, 0.245705, 0.249110, 0.290489",\ + "0.442377, 0.399789, 0.341790, 0.345163, 0.386153",\ + "0.570076, 0.527583, 0.468994, 0.472224, 0.511474",\ + "0.816390, 0.774143, 0.714024, 0.716882, 0.751614",\ + "1.243561, 1.201654, 1.139151, 1.141470, 1.169661"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_recfr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.258352, -0.220900, -0.161340, -0.151153, -0.027357",\ + "-0.354483, -0.317000, -0.257562, -0.247380, -0.123649",\ + "-0.481891, -0.444270, -0.385376, -0.375219, -0.251777",\ + "-0.727449, -0.689470, -0.631990, -0.621894, -0.499204",\ + "-1.152401, -1.113697, -1.058374, -1.048432, -0.927596"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[1]_remfr*/ + +} /* end of pin fla_alert_src_i[1] */ + +pin("fla_alert_src_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001210 ; + + /* Other user defined attributes. */ + original_pin : fla_alert_src_i[0]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.153898, 0.096234, -0.017862, -0.012789, 0.048865",\ + "0.234547, 0.176873, 0.063006, 0.068247, 0.131938",\ + "0.312922, 0.255231, 0.141780, 0.147323, 0.214693",\ + "0.443628, 0.385987, 0.272716, 0.278561, 0.349586",\ + "0.643976, 0.586670, 0.471971, 0.477562, 0.545510"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.135497, 0.097521, 0.047194, 0.048307, 0.061839",\ + "0.227162, 0.188584, 0.138031, 0.139144, 0.152665",\ + "0.314547, 0.274830, 0.224128, 0.225207, 0.238331",\ + "0.459106, 0.419271, 0.367632, 0.368682, 0.381446",\ + "0.699539, 0.659946, 0.606277, 0.607276, 0.619410"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.067048, -0.016232, 0.079533, 0.097739, 0.319005",\ + "-0.147841, -0.096754, 0.000043, 0.018162, 0.238358",\ + "-0.226477, -0.174901, -0.076238, -0.058278, 0.159985",\ + "-0.357390, -0.304774, -0.203323, -0.185507, 0.031000",\ + "-0.557290, -0.502515, -0.398294, -0.380283, -0.161393"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.067653, -0.034085, 0.023249, 0.050680, 0.384046",\ + "-0.158725, -0.125379, -0.067382, -0.046199, 0.211248",\ + "-0.245194, -0.212186, -0.153370, -0.141879, -0.002219",\ + "-0.386154, -0.352349, -0.293338, -0.283677, -0.166272",\ + "-0.618941, -0.583206, -0.524120, -0.514248, -0.394277"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_hldr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.348301, 0.305676, 0.248104, 0.251583, 0.293858",\ + "0.429286, 0.386661, 0.329089, 0.332567, 0.374842",\ + "0.504635, 0.462011, 0.404396, 0.407864, 0.450008",\ + "0.638699, 0.596084, 0.538251, 0.541665, 0.583146",\ + "0.863013, 0.820471, 0.762185, 0.765489, 0.805634"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_recrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.260501, -0.223062, -0.163229, -0.153056, -0.029425",\ + "-0.341485, -0.304046, -0.244213, -0.234040, -0.110409",\ + "-0.416836, -0.379397, -0.319604, -0.309428, -0.185759",\ + "-0.550887, -0.513443, -0.453851, -0.443663, -0.319850",\ + "-0.774977, -0.737427, -0.678253, -0.668084, -0.544492"); + } + + } /* end of arc clk_ast_alert_i_fla_alert_src_i[0]_remrr*/ + +} /* end of pin fla_alert_src_i[0] */ +} /* end of bus fla_alert_src_i */ +bus ( otp_alert_src_i ) { + + bus_type : BUS2_type5 ; + direction : input ; + +pin("otp_alert_src_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000977 ; + + /* Other user defined attributes. */ + original_pin : otp_alert_src_i[1]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.160061, 0.122171, 0.071764, 0.072890, 0.086576",\ + "0.244155, 0.206260, 0.155798, 0.156930, 0.170689",\ + "0.325133, 0.287001, 0.236508, 0.237633, 0.251310",\ + "0.464429, 0.425692, 0.375119, 0.376227, 0.389693",\ + "0.687556, 0.647617, 0.596849, 0.597922, 0.610956"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.188609, 0.130944, 0.016876, 0.021970, 0.083878",\ + "0.276270, 0.218603, 0.104578, 0.109703, 0.171989",\ + "0.365048, 0.307375, 0.193490, 0.198718, 0.262247",\ + "0.519717, 0.462029, 0.348488, 0.353966, 0.420536",\ + "0.771986, 0.714301, 0.601221, 0.607099, 0.678536"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.092219, -0.058653, -0.001237, 0.026220, 0.359896",\ + "-0.176268, -0.142720, -0.085214, -0.058223, 0.269794",\ + "-0.257056, -0.223577, -0.165901, -0.140924, 0.162616",\ + "-0.395865, -0.362566, -0.304455, -0.284621, -0.043580",\ + "-0.617889, -0.584914, -0.525934, -0.516364, -0.400062"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.101777, -0.050927, 0.044966, 0.063162, 0.284294",\ + "-0.189465, -0.138565, -0.042479, -0.024300, 0.196634",\ + "-0.278331, -0.227265, -0.130550, -0.112424, 0.107856",\ + "-0.433215, -0.381745, -0.283488, -0.265494, -0.046811",\ + "-0.685809, -0.633481, -0.532401, -0.514612, -0.298423"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_hldr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.346181, 0.303572, 0.245705, 0.249110, 0.290489",\ + "0.442377, 0.399789, 0.341790, 0.345163, 0.386153",\ + "0.570076, 0.527583, 0.468994, 0.472224, 0.511474",\ + "0.816390, 0.774143, 0.714024, 0.716882, 0.751614",\ + "1.243561, 1.201654, 1.139151, 1.141470, 1.169661"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_recfr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.258352, -0.220900, -0.161340, -0.151153, -0.027357",\ + "-0.354483, -0.317000, -0.257562, -0.247380, -0.123649",\ + "-0.481891, -0.444270, -0.385376, -0.375219, -0.251777",\ + "-0.727449, -0.689470, -0.631990, -0.621894, -0.499204",\ + "-1.152401, -1.113697, -1.058374, -1.048432, -0.927596"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[1]_remfr*/ + +} /* end of pin otp_alert_src_i[1] */ + +pin("otp_alert_src_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001210 ; + + /* Other user defined attributes. */ + original_pin : otp_alert_src_i[0]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.153898, 0.096234, -0.017862, -0.012789, 0.048865",\ + "0.234547, 0.176873, 0.063006, 0.068247, 0.131938",\ + "0.312922, 0.255231, 0.141780, 0.147323, 0.214693",\ + "0.443628, 0.385987, 0.272716, 0.278561, 0.349586",\ + "0.643976, 0.586670, 0.471971, 0.477562, 0.545510"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.135497, 0.097521, 0.047194, 0.048307, 0.061839",\ + "0.227162, 0.188584, 0.138031, 0.139144, 0.152665",\ + "0.314547, 0.274830, 0.224128, 0.225207, 0.238331",\ + "0.459106, 0.419271, 0.367632, 0.368682, 0.381446",\ + "0.699539, 0.659946, 0.606277, 0.607276, 0.619410"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.067048, -0.016232, 0.079533, 0.097739, 0.319005",\ + "-0.147841, -0.096754, 0.000043, 0.018162, 0.238358",\ + "-0.226477, -0.174901, -0.076238, -0.058278, 0.159985",\ + "-0.357390, -0.304774, -0.203323, -0.185507, 0.031000",\ + "-0.557290, -0.502515, -0.398294, -0.380283, -0.161393"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.067653, -0.034085, 0.023249, 0.050680, 0.384046",\ + "-0.158725, -0.125379, -0.067382, -0.046199, 0.211248",\ + "-0.245194, -0.212186, -0.153370, -0.141879, -0.002219",\ + "-0.386154, -0.352349, -0.293338, -0.283677, -0.166272",\ + "-0.618941, -0.583206, -0.524120, -0.514248, -0.394277"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_hldr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.348301, 0.305676, 0.248104, 0.251583, 0.293858",\ + "0.429286, 0.386661, 0.329089, 0.332567, 0.374842",\ + "0.504635, 0.462011, 0.404396, 0.407864, 0.450008",\ + "0.638699, 0.596084, 0.538251, 0.541665, 0.583146",\ + "0.863013, 0.820471, 0.762185, 0.765489, 0.805634"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_recrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.260501, -0.223062, -0.163229, -0.153056, -0.029425",\ + "-0.341485, -0.304046, -0.244213, -0.234040, -0.110409",\ + "-0.416836, -0.379397, -0.319604, -0.309428, -0.185759",\ + "-0.550887, -0.513443, -0.453851, -0.443663, -0.319850",\ + "-0.774977, -0.737427, -0.678253, -0.668084, -0.544492"); + } + + } /* end of arc clk_ast_alert_i_otp_alert_src_i[0]_remrr*/ + +} /* end of pin otp_alert_src_i[0] */ +} /* end of bus otp_alert_src_i */ +bus ( alert_rsp_i ) { + + bus_type : BUS52_type11 ; + direction : input ; + +pin("alert_rsp_i[51]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[51]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[51]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[51]_hldr*/ + +} /* end of pin alert_rsp_i[51] */ + +pin("alert_rsp_i[50]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[50]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[50]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[50]_hldr*/ + +} /* end of pin alert_rsp_i[50] */ + +pin("alert_rsp_i[49]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[49]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[49]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[49]_hldr*/ + +} /* end of pin alert_rsp_i[49] */ + +pin("alert_rsp_i[48]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[48]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[48]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[48]_hldr*/ + +} /* end of pin alert_rsp_i[48] */ + +pin("alert_rsp_i[47]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[47]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[47]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[47]_hldr*/ + +} /* end of pin alert_rsp_i[47] */ + +pin("alert_rsp_i[46]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[46]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[46]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[46]_hldr*/ + +} /* end of pin alert_rsp_i[46] */ + +pin("alert_rsp_i[45]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[45]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[45]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[45]_hldr*/ + +} /* end of pin alert_rsp_i[45] */ + +pin("alert_rsp_i[44]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[44]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[44]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[44]_hldr*/ + +} /* end of pin alert_rsp_i[44] */ + +pin("alert_rsp_i[43]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[43]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[43]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[43]_hldr*/ + +} /* end of pin alert_rsp_i[43] */ + +pin("alert_rsp_i[42]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[42]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[42]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[42]_hldr*/ + +} /* end of pin alert_rsp_i[42] */ + +pin("alert_rsp_i[41]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[41]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[41]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[41]_hldr*/ + +} /* end of pin alert_rsp_i[41] */ + +pin("alert_rsp_i[40]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[40]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[40]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[40]_hldr*/ + +} /* end of pin alert_rsp_i[40] */ + +pin("alert_rsp_i[39]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[39]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[39]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[39]_hldr*/ + +} /* end of pin alert_rsp_i[39] */ + +pin("alert_rsp_i[38]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[38]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[38]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[38]_hldr*/ + +} /* end of pin alert_rsp_i[38] */ + +pin("alert_rsp_i[37]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[37]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[37]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[37]_hldr*/ + +} /* end of pin alert_rsp_i[37] */ + +pin("alert_rsp_i[36]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[36]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[36]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[36]_hldr*/ + +} /* end of pin alert_rsp_i[36] */ + +pin("alert_rsp_i[35]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[35]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[35]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[35]_hldr*/ + +} /* end of pin alert_rsp_i[35] */ + +pin("alert_rsp_i[34]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[34]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[34]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[34]_hldr*/ + +} /* end of pin alert_rsp_i[34] */ + +pin("alert_rsp_i[33]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[33]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[33]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[33]_hldr*/ + +} /* end of pin alert_rsp_i[33] */ + +pin("alert_rsp_i[32]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[32]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[32]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[32]_hldr*/ + +} /* end of pin alert_rsp_i[32] */ + +pin("alert_rsp_i[31]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[31]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[31]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[31]_hldr*/ + +} /* end of pin alert_rsp_i[31] */ + +pin("alert_rsp_i[30]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[30]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[30]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[30]_hldr*/ + +} /* end of pin alert_rsp_i[30] */ + +pin("alert_rsp_i[29]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[29]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[29]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[29]_hldr*/ + +} /* end of pin alert_rsp_i[29] */ + +pin("alert_rsp_i[28]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[28]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[28]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[28]_hldr*/ + +} /* end of pin alert_rsp_i[28] */ + +pin("alert_rsp_i[27]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000591 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[27]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.199726, 0.138633, 0.033463, 0.054461, 0.309637",\ + "0.287373, 0.226285, 0.121029, 0.142110, 0.398309",\ + "0.384684, 0.323610, 0.218105, 0.239430, 0.498591",\ + "0.560847, 0.499591, 0.393454, 0.414928, 0.675905",\ + "0.860633, 0.798634, 0.691077, 0.712170, 0.968509"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.214871, 0.178837, 0.123974, 0.124132, 0.126049",\ + "0.298634, 0.262602, 0.208037, 0.208173, 0.209823",\ + "0.403277, 0.367383, 0.313251, 0.313345, 0.314481",\ + "0.578488, 0.543087, 0.488416, 0.488511, 0.489666",\ + "0.868870, 0.834430, 0.778706, 0.778804, 0.779997"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[27]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.112157, -0.054218, 0.050557, 0.069205, 0.295841",\ + "-0.199804, -0.141906, -0.036659, -0.018006, 0.208689",\ + "-0.297115, -0.239335, -0.132721, -0.114053, 0.112815",\ + "-0.473050, -0.415309, -0.306338, -0.287512, -0.058720",\ + "-0.771971, -0.713924, -0.601352, -0.581984, -0.346599"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.126284, -0.091801, -0.026053, 0.006825, 0.406380",\ + "-0.209910, -0.175609, -0.109372, -0.076372, 0.324685",\ + "-0.312970, -0.278942, -0.212075, -0.178671, 0.227297",\ + "-0.483276, -0.448963, -0.383263, -0.349244, 0.064176",\ + "-0.764074, -0.729205, -0.665784, -0.630568, -0.202592"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[27]_hldr*/ + +} /* end of pin alert_rsp_i[27] */ + +pin("alert_rsp_i[26]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000589 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[26]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.192162, 0.131067, 0.025934, 0.046895, 0.301630",\ + "0.279200, 0.218116, 0.112785, 0.133940, 0.391038",\ + "0.372216, 0.311153, 0.205428, 0.226969, 0.488754",\ + "0.526955, 0.465449, 0.358834, 0.380180, 0.639596",\ + "0.781727, 0.719289, 0.610887, 0.631753, 0.885337"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.203639, 0.167601, 0.112469, 0.112646, 0.114806",\ + "0.292883, 0.256848, 0.201897, 0.202061, 0.204057",\ + "0.398578, 0.362549, 0.308291, 0.308405, 0.309779",\ + "0.587975, 0.552224, 0.497936, 0.498030, 0.499172",\ + "0.915076, 0.879998, 0.824973, 0.825069, 0.826237"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[26]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.104592, -0.046636, 0.057935, 0.076581, 0.303191",\ + "-0.191631, -0.133768, -0.028107, -0.009449, 0.217299",\ + "-0.284646, -0.226970, -0.119146, -0.100465, 0.126557",\ + "-0.438866, -0.381023, -0.270840, -0.251831, -0.020821",\ + "-0.692552, -0.634323, -0.519612, -0.499921, -0.260619"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.115174, -0.080527, -0.015220, 0.017546, 0.415745",\ + "-0.204335, -0.169799, -0.104194, -0.071353, 0.327762",\ + "-0.309715, -0.275599, -0.208862, -0.175734, 0.226866",\ + "-0.496251, -0.462141, -0.395611, -0.362029, 0.046093",\ + "-0.816650, -0.782151, -0.717215, -0.682795, -0.264493"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[26]_hldr*/ + +} /* end of pin alert_rsp_i[26] */ + +pin("alert_rsp_i[25]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[25]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[25]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[25]_hldr*/ + +} /* end of pin alert_rsp_i[25] */ + +pin("alert_rsp_i[24]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[24]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[24]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[24]_hldr*/ + +} /* end of pin alert_rsp_i[24] */ + +pin("alert_rsp_i[23]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[23]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[23]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[23]_hldr*/ + +} /* end of pin alert_rsp_i[23] */ + +pin("alert_rsp_i[22]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[22]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[22]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[22]_hldr*/ + +} /* end of pin alert_rsp_i[22] */ + +pin("alert_rsp_i[21]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[21]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[21]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[21]_hldr*/ + +} /* end of pin alert_rsp_i[21] */ + +pin("alert_rsp_i[20]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[20]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[20]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[20]_hldr*/ + +} /* end of pin alert_rsp_i[20] */ + +pin("alert_rsp_i[19]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[19]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[19]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[19]_hldr*/ + +} /* end of pin alert_rsp_i[19] */ + +pin("alert_rsp_i[18]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[18]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[18]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[18]_hldr*/ + +} /* end of pin alert_rsp_i[18] */ + +pin("alert_rsp_i[17]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[17]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[17]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[17]_hldr*/ + +} /* end of pin alert_rsp_i[17] */ + +pin("alert_rsp_i[16]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[16]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[16]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[16]_hldr*/ + +} /* end of pin alert_rsp_i[16] */ + +pin("alert_rsp_i[15]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[15]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[15]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[15]_hldr*/ + +} /* end of pin alert_rsp_i[15] */ + +pin("alert_rsp_i[14]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[14]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[14]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[14]_hldr*/ + +} /* end of pin alert_rsp_i[14] */ + +pin("alert_rsp_i[13]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[13]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[13]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[13]_hldr*/ + +} /* end of pin alert_rsp_i[13] */ + +pin("alert_rsp_i[12]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[12]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[12]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[12]_hldr*/ + +} /* end of pin alert_rsp_i[12] */ + +pin("alert_rsp_i[11]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[11]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[11]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[11]_hldr*/ + +} /* end of pin alert_rsp_i[11] */ + +pin("alert_rsp_i[10]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[10]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[10]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[10]_hldr*/ + +} /* end of pin alert_rsp_i[10] */ + +pin("alert_rsp_i[9]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[9]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[9]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[9]_hldr*/ + +} /* end of pin alert_rsp_i[9] */ + +pin("alert_rsp_i[8]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[8]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[8]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[8]_hldr*/ + +} /* end of pin alert_rsp_i[8] */ + +pin("alert_rsp_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[7]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[7]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[7]_hldr*/ + +} /* end of pin alert_rsp_i[7] */ + +pin("alert_rsp_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[6]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[6]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[6]_hldr*/ + +} /* end of pin alert_rsp_i[6] */ + +pin("alert_rsp_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[5]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[5]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[5]_hldr*/ + +} /* end of pin alert_rsp_i[5] */ + +pin("alert_rsp_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[4]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[4]_hldr*/ + +} /* end of pin alert_rsp_i[4] */ + +pin("alert_rsp_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[3]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[3]_hldr*/ + +} /* end of pin alert_rsp_i[3] */ + +pin("alert_rsp_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[2]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[2]_hldr*/ + +} /* end of pin alert_rsp_i[2] */ + +pin("alert_rsp_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000448 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[1]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.185938, 0.149895, 0.094200, 0.094419, 0.097084",\ + "0.272325, 0.236283, 0.180640, 0.180856, 0.183473",\ + "0.358907, 0.322867, 0.267423, 0.267624, 0.270063",\ + "0.517339, 0.481305, 0.426450, 0.426607, 0.428517",\ + "0.782742, 0.746824, 0.692719, 0.692812, 0.693947"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.247782, 0.186691, 0.081487, 0.102517, 0.358097",\ + "0.337069, 0.275978, 0.170775, 0.191805, 0.447385",\ + "0.437523, 0.376437, 0.271157, 0.292262, 0.548747",\ + "0.618326, 0.557252, 0.451732, 0.473072, 0.732422",\ + "0.922412, 0.861156, 0.755022, 0.776496, 1.037479"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.097073, -0.062070, 0.002277, 0.034799, 0.430045",\ + "-0.183156, -0.148183, -0.083758, -0.051216, 0.344267",\ + "-0.269694, -0.234839, -0.170093, -0.137470, 0.259003",\ + "-0.427321, -0.392813, -0.327135, -0.294275, 0.105065",\ + "-0.690363, -0.656367, -0.589370, -0.556034, -0.150898"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.143047, -0.085078, 0.019349, 0.037994, 0.264586",\ + "-0.232868, -0.174900, -0.070472, -0.051827, 0.174765",\ + "-0.335734, -0.277819, -0.172775, -0.154124, 0.072546",\ + "-0.517254, -0.459461, -0.352995, -0.334328, -0.107479",\ + "-0.818219, -0.760494, -0.651701, -0.632901, -0.404435"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[1]_hldr*/ + +} /* end of pin alert_rsp_i[1] */ + +pin("alert_rsp_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000500 ; + + /* Other user defined attributes. */ + original_pin : alert_rsp_i[0]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.220674, 0.184637, 0.129589, 0.129760, 0.131844",\ + "0.297060, 0.261023, 0.205975, 0.206146, 0.208230",\ + "0.368632, 0.332596, 0.277611, 0.277778, 0.279805",\ + "0.497931, 0.461898, 0.407219, 0.407363, 0.409115",\ + "0.712779, 0.676837, 0.622759, 0.622852, 0.623986"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.209550, 0.148448, 0.043450, 0.064279, 0.317417",\ + "0.301584, 0.240483, 0.135457, 0.156314, 0.409784",\ + "0.402135, 0.341040, 0.235908, 0.256868, 0.511598",\ + "0.580476, 0.519395, 0.414005, 0.435218, 0.693015",\ + "0.877762, 0.816594, 0.710628, 0.732149, 0.993683"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.105222, -0.070365, -0.005626, 0.026996, 0.423447",\ + "-0.183185, -0.148328, -0.083588, -0.050966, 0.345485",\ + "-0.257972, -0.223201, -0.158231, -0.125551, 0.271609",\ + "-0.390468, -0.355966, -0.290271, -0.257407, 0.141987",\ + "-0.603765, -0.569785, -0.502723, -0.469420, -0.064694"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.121294, -0.063271, 0.040519, 0.059158, 0.285669",\ + "-0.213390, -0.155380, -0.051441, -0.032801, 0.193729",\ + "-0.313842, -0.255881, -0.151371, -0.132725, 0.093876",\ + "-0.490960, -0.433113, -0.327285, -0.308625, -0.081856",\ + "-0.786249, -0.728564, -0.620239, -0.601510, -0.373902"); + } + + } /* end of arc clk_ast_alert_i_alert_rsp_i[0]_hldr*/ + +} /* end of pin alert_rsp_i[0] */ +} /* end of bus alert_rsp_i */ +bus ( alert_req_o ) { + + bus_type : BUS26_type12 ; + direction : output ; + +pin("alert_req_o[25]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[25]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[25]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[25]_redg_min*/ + +} /* end of pin alert_req_o[25] */ + +pin("alert_req_o[24]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[24]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[24]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[24]_redg_min*/ + +} /* end of pin alert_req_o[24] */ + +pin("alert_req_o[23]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[23]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[23]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[23]_redg_min*/ + +} /* end of pin alert_req_o[23] */ + +pin("alert_req_o[22]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[22]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[22]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[22]_redg_min*/ + +} /* end of pin alert_req_o[22] */ + +pin("alert_req_o[21]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[21]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[21]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[21]_redg_min*/ + +} /* end of pin alert_req_o[21] */ + +pin("alert_req_o[20]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[20]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[20]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[20]_redg_min*/ + +} /* end of pin alert_req_o[20] */ + +pin("alert_req_o[19]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[19]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[19]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[19]_redg_min*/ + +} /* end of pin alert_req_o[19] */ + +pin("alert_req_o[18]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[18]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[18]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[18]_redg_min*/ + +} /* end of pin alert_req_o[18] */ + +pin("alert_req_o[17]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[17]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[17]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[17]_redg_min*/ + +} /* end of pin alert_req_o[17] */ + +pin("alert_req_o[16]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[16]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[16]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[16]_redg_min*/ + +} /* end of pin alert_req_o[16] */ + +pin("alert_req_o[15]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[15]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[15]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[15]_redg_min*/ + +} /* end of pin alert_req_o[15] */ + +pin("alert_req_o[14]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[14]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[14]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[14]_redg_min*/ + +} /* end of pin alert_req_o[14] */ + +pin("alert_req_o[13]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[13]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[13]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[13]_redg_min*/ + +} /* end of pin alert_req_o[13] */ + +pin("alert_req_o[12]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[12]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[12]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[12]_redg_min*/ + +} /* end of pin alert_req_o[12] */ + +pin("alert_req_o[11]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[11]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[11]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[11]_redg_min*/ + +} /* end of pin alert_req_o[11] */ + +pin("alert_req_o[10]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[10]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[10]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[10]_redg_min*/ + +} /* end of pin alert_req_o[10] */ + +pin("alert_req_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[9]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[9]_redg_min*/ + +} /* end of pin alert_req_o[9] */ + +pin("alert_req_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[8]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[8]_redg_min*/ + +} /* end of pin alert_req_o[8] */ + +pin("alert_req_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[7]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[7]_redg_min*/ + +} /* end of pin alert_req_o[7] */ + +pin("alert_req_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[6]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[6]_redg_min*/ + +} /* end of pin alert_req_o[6] */ + +pin("alert_req_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[5]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[5]_redg_min*/ + +} /* end of pin alert_req_o[5] */ + +pin("alert_req_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[4]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[4]_redg_min*/ + +} /* end of pin alert_req_o[4] */ + +pin("alert_req_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[3]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296659, 0.552264, 2.441059",\ + "0.027606, 0.137424, 0.296659, 0.552264, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.555346, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.555346, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.186120, 0.340034, 1.494292",\ + "0.022299, 0.090163, 0.186120, 0.340034, 1.494292",\ + "0.024376, 0.090410, 0.186120, 0.340034, 1.494292",\ + "0.025559, 0.090772, 0.186120, 0.340034, 1.494292",\ + "0.043338, 0.097514, 0.190357, 0.340034, 1.494292"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.054627, 0.128254, 0.213264, 0.349398, 1.341047",\ + "0.111446, 0.185285, 0.270053, 0.405814, 1.402083",\ + "0.250051, 0.333480, 0.418189, 0.553854, 1.548154",\ + "0.283766, 0.371624, 0.456253, 0.591793, 1.586834",\ + "0.584903, 0.727700, 0.813314, 0.950396, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.026420, 0.137079, 0.296653, 0.551706, 2.441059",\ + "0.027606, 0.137424, 0.296653, 0.551706, 2.442441",\ + "0.048973, 0.143889, 0.302016, 0.554928, 2.445574",\ + "0.056124, 0.147298, 0.303942, 0.554928, 2.445574",\ + "0.135119, 0.207795, 0.342920, 0.559922, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.074318, 0.127023, 0.181661, 0.269150, 0.901570",\ + "0.135238, 0.187941, 0.242461, 0.329766, 0.964295",\ + "0.278249, 0.331631, 0.386036, 0.473153, 1.104683",\ + "0.313722, 0.367652, 0.422063, 0.509190, 1.140690",\ + "0.637044, 0.700813, 0.755435, 0.842904, 1.478811"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.031162, 0.073075, 0.140203, 0.634048"); + values ( "0.022299, 0.090049, 0.185649, 0.338251, 1.490219",\ + "0.022299, 0.090163, 0.185649, 0.338251, 1.490219",\ + "0.024376, 0.090410, 0.185649, 0.338251, 1.490219",\ + "0.025559, 0.090772, 0.185933, 0.338414, 1.490219",\ + "0.043338, 0.097514, 0.190357, 0.339166, 1.490219"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[3]_redg_min*/ + +} /* end of pin alert_req_o[3] */ + +pin("alert_req_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001149 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[2]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297295, 0.552903, 2.441059",\ + "0.028270, 0.138058, 0.297295, 0.552903, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555988, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555988, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186489, 0.340409, 1.494277",\ + "0.022756, 0.090531, 0.186489, 0.340409, 1.494277",\ + "0.024833, 0.090775, 0.186489, 0.340409, 1.494277",\ + "0.025999, 0.091137, 0.186489, 0.340409, 1.494277",\ + "0.043741, 0.097870, 0.190712, 0.340409, 1.494277"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.055384, 0.128593, 0.213603, 0.349733, 1.341047",\ + "0.112211, 0.185623, 0.270391, 0.406151, 1.402083",\ + "0.251189, 0.333817, 0.418527, 0.554191, 1.548154",\ + "0.285031, 0.371962, 0.456591, 0.592129, 1.586834",\ + "0.587490, 0.728041, 0.813655, 0.950730, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.027116, 0.137715, 0.297287, 0.552346, 2.441059",\ + "0.028270, 0.138058, 0.297287, 0.552346, 2.442441",\ + "0.049599, 0.144519, 0.302646, 0.555570, 2.445574",\ + "0.056771, 0.147922, 0.304566, 0.555570, 2.445574",\ + "0.136105, 0.208333, 0.343458, 0.560560, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.074922, 0.127232, 0.181871, 0.269356, 0.901561",\ + "0.135837, 0.188150, 0.242670, 0.329973, 0.964286",\ + "0.278886, 0.331840, 0.386244, 0.473358, 1.104675",\ + "0.314388, 0.367860, 0.422271, 0.509395, 1.140682",\ + "0.638051, 0.701022, 0.755644, 0.843111, 1.478802"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001149, 0.031329, 0.073242, 0.140370, 0.634048"); + values ( "0.022737, 0.090417, 0.186014, 0.338627, 1.490204",\ + "0.022756, 0.090531, 0.186014, 0.338627, 1.490204",\ + "0.024833, 0.090775, 0.186014, 0.338627, 1.490204",\ + "0.025999, 0.091137, 0.186298, 0.338790, 1.490204",\ + "0.043741, 0.097870, 0.190712, 0.339540, 1.490204"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[2]_redg_min*/ + +} /* end of pin alert_req_o[2] */ + +pin("alert_req_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001011 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[1]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.054759, 0.128313, 0.213323, 0.349457, 1.341047",\ + "0.111579, 0.185344, 0.270112, 0.405873, 1.402083",\ + "0.250250, 0.333539, 0.418248, 0.553913, 1.548154",\ + "0.283987, 0.371683, 0.456312, 0.591852, 1.586834",\ + "0.585354, 0.727759, 0.813374, 0.950454, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.026541, 0.137190, 0.296770, 0.552376, 2.441059",\ + "0.027722, 0.137535, 0.296770, 0.552376, 2.442441",\ + "0.049082, 0.143999, 0.302126, 0.555458, 2.445574",\ + "0.056237, 0.147407, 0.304051, 0.555458, 2.445574",\ + "0.135291, 0.207889, 0.343014, 0.560034, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.074438, 0.127065, 0.181703, 0.269191, 0.901573",\ + "0.135357, 0.187983, 0.242503, 0.329807, 0.964298",\ + "0.278376, 0.331673, 0.386077, 0.473193, 1.104686",\ + "0.313854, 0.367693, 0.422104, 0.509231, 1.140694",\ + "0.637244, 0.700854, 0.755477, 0.842945, 1.478814"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.022386, 0.090122, 0.186194, 0.340109, 1.494298",\ + "0.022386, 0.090236, 0.186194, 0.340109, 1.494298",\ + "0.024466, 0.090482, 0.186194, 0.340109, 1.494298",\ + "0.025646, 0.090844, 0.186194, 0.340109, 1.494298",\ + "0.043418, 0.097585, 0.190427, 0.340109, 1.494298"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.054759, 0.128313, 0.213323, 0.349457, 1.341047",\ + "0.111579, 0.185344, 0.270112, 0.405873, 1.402083",\ + "0.250250, 0.333539, 0.418248, 0.553913, 1.548154",\ + "0.283987, 0.371683, 0.456312, 0.591852, 1.586834",\ + "0.585354, 0.727759, 0.813374, 0.950454, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.026541, 0.137190, 0.296764, 0.551818, 2.441059",\ + "0.027722, 0.137535, 0.296764, 0.551818, 2.442441",\ + "0.049082, 0.143999, 0.302126, 0.555040, 2.445574",\ + "0.056237, 0.147407, 0.304051, 0.555040, 2.445574",\ + "0.135291, 0.207889, 0.343014, 0.560034, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.074438, 0.127065, 0.181703, 0.269191, 0.901573",\ + "0.135357, 0.187983, 0.242503, 0.329807, 0.964298",\ + "0.278376, 0.331673, 0.386077, 0.473193, 1.104686",\ + "0.313854, 0.367693, 0.422104, 0.509231, 1.140694",\ + "0.637244, 0.700854, 0.755477, 0.842945, 1.478814"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.001011, 0.031191, 0.073104, 0.140232, 0.634048"); + values ( "0.022386, 0.090122, 0.185722, 0.338326, 1.490226",\ + "0.022386, 0.090236, 0.185722, 0.338326, 1.490226",\ + "0.024466, 0.090482, 0.185722, 0.338326, 1.490226",\ + "0.025646, 0.090844, 0.186005, 0.338489, 1.490226",\ + "0.043418, 0.097585, 0.190427, 0.339240, 1.490226"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[1]_redg_min*/ + +} /* end of pin alert_req_o[1] */ + +pin("alert_req_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.634048 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000990 ; + + /* Other user defined attributes. */ + original_pin : alert_req_o[0]; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.054663, 0.128270, 0.213280, 0.349414, 1.341047",\ + "0.111482, 0.185301, 0.270069, 0.405830, 1.402083",\ + "0.250105, 0.333496, 0.418205, 0.553870, 1.548154",\ + "0.283826, 0.371640, 0.456269, 0.591809, 1.586834",\ + "0.585026, 0.727716, 0.813330, 0.950411, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.026453, 0.137109, 0.296689, 0.552294, 2.441059",\ + "0.027638, 0.137454, 0.296689, 0.552294, 2.442441",\ + "0.049002, 0.143919, 0.302046, 0.555377, 2.445574",\ + "0.056155, 0.147327, 0.303971, 0.555377, 2.445574",\ + "0.135166, 0.207821, 0.342945, 0.559953, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.074369, 0.127040, 0.181679, 0.269167, 0.901576",\ + "0.135288, 0.187959, 0.242479, 0.329784, 0.964302",\ + "0.278302, 0.331649, 0.386053, 0.473170, 1.104690",\ + "0.313777, 0.367669, 0.422080, 0.509207, 1.140697",\ + "0.637128, 0.700830, 0.755452, 0.842922, 1.478818"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.022335, 0.090079, 0.186151, 0.340065, 1.494304",\ + "0.022335, 0.090194, 0.186151, 0.340065, 1.494304",\ + "0.024413, 0.090440, 0.186151, 0.340065, 1.494304",\ + "0.025595, 0.090802, 0.186151, 0.340065, 1.494304",\ + "0.043371, 0.097543, 0.190386, 0.340065, 1.494304"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_alert_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.054663, 0.128270, 0.213280, 0.349414, 1.341047",\ + "0.111482, 0.185301, 0.270069, 0.405830, 1.402083",\ + "0.250105, 0.333496, 0.418205, 0.553870, 1.548154",\ + "0.283826, 0.371640, 0.456269, 0.591809, 1.586834",\ + "0.585026, 0.727716, 0.813330, 0.950411, 1.938873"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.026453, 0.137109, 0.296683, 0.551737, 2.441059",\ + "0.027638, 0.137454, 0.296683, 0.551737, 2.442441",\ + "0.049002, 0.143919, 0.302046, 0.554959, 2.445574",\ + "0.056155, 0.147327, 0.303971, 0.554959, 2.445574",\ + "0.135166, 0.207821, 0.342945, 0.559953, 2.445574"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.074369, 0.127040, 0.181679, 0.269167, 0.901576",\ + "0.135288, 0.187959, 0.242479, 0.329784, 0.964302",\ + "0.278302, 0.331649, 0.386053, 0.473170, 1.104690",\ + "0.313777, 0.367669, 0.422080, 0.509207, 1.140697",\ + "0.637128, 0.700830, 0.755452, 0.842922, 1.478818"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000990, 0.031170, 0.073083, 0.140211, 0.634048"); + values ( "0.022335, 0.090079, 0.185679, 0.338282, 1.490232",\ + "0.022335, 0.090194, 0.185679, 0.338282, 1.490232",\ + "0.024413, 0.090440, 0.185679, 0.338282, 1.490232",\ + "0.025595, 0.090802, 0.185963, 0.338445, 1.490232",\ + "0.043371, 0.097543, 0.190386, 0.339197, 1.490232"); + } + + } /* end of arc clk_ast_alert_i_alert_req_o[0]_redg_min*/ + +} /* end of pin alert_req_o[0] */ +} /* end of bus alert_req_o */ +bus ( dft_strap_test_i ) { + + bus_type : BUS3_type13 ; + direction : input ; + +pin("dft_strap_test_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001120 ; + + /* Other user defined attributes. */ + original_pin : dft_strap_test_i[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.478706, 0.503228, 0.581052, 0.648637, 1.079464",\ + "0.567148, 0.591670, 0.669494, 0.737079, 1.167906",\ + "0.650074, 0.674596, 0.752419, 0.820004, 1.250831",\ + "0.793078, 0.817600, 0.895423, 0.963008, 1.393835",\ + "1.032445, 1.056946, 1.134770, 1.202355, 1.633182"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.463301, 0.380673, 0.305530, 0.271812, 0.239120",\ + "0.556491, 0.473863, 0.398720, 0.365002, 0.332310",\ + "0.646873, 0.564245, 0.489102, 0.455384, 0.422692",\ + "0.811633, 0.729010, 0.653883, 0.620177, 0.587543",\ + "1.181053, 1.098457, 1.023414, 0.989768, 0.957438"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.265123, -0.222342, -0.186677, -0.161410, -0.033314",\ + "-0.347654, -0.304874, -0.269208, -0.243941, -0.115845",\ + "-0.437836, -0.395055, -0.359390, -0.334122, -0.206027",\ + "-0.606076, -0.563289, -0.527626, -0.502359, -0.374263",\ + "-0.890704, -0.847899, -0.812254, -0.786994, -0.658891"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.255864, -0.182785, -0.116647, -0.070567, 0.157553",\ + "-0.349537, -0.279942, -0.213805, -0.167724, 0.060396",\ + "-0.440910, -0.389678, -0.323541, -0.277461, -0.049341",\ + "-0.599026, -0.557614, -0.524142, -0.478056, -0.249871",\ + "-0.851183, -0.809770, -0.777053, -0.739869, -0.511712"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[2]_hldr*/ + +} /* end of pin dft_strap_test_i[2] */ + +pin("dft_strap_test_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001321 ; + + /* Other user defined attributes. */ + original_pin : dft_strap_test_i[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.428035, 0.345406, 0.276171, 0.259388, 0.254027",\ + "0.519710, 0.437082, 0.361939, 0.340063, 0.334702",\ + "0.618532, 0.535904, 0.460761, 0.427043, 0.420880",\ + "0.797361, 0.714733, 0.639590, 0.605872, 0.573180",\ + "1.098214, 1.015590, 0.940461, 0.906752, 0.874108"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.453520, 0.478042, 0.555866, 0.623451, 1.054278",\ + "0.538258, 0.562780, 0.640604, 0.708189, 1.139016",\ + "0.651889, 0.676378, 0.754202, 0.821787, 1.252614",\ + "0.864482, 0.889878, 0.967702, 1.035287, 1.466114",\ + "1.235476, 1.260812, 1.338683, 1.406288, 1.837127"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.221451, -0.180039, -0.147321, -0.110125, 0.118032",\ + "-0.314428, -0.273016, -0.240298, -0.203102, 0.025055",\ + "-0.409753, -0.368340, -0.335623, -0.298439, -0.070282",\ + "-0.551259, -0.508465, -0.472804, -0.447539, -0.236382",\ + "-0.757339, -0.714548, -0.679008, -0.653790, -0.510956"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.247877, -0.173125, -0.106987, -0.060907, 0.167213",\ + "-0.342789, -0.268037, -0.201899, -0.155819, 0.072301",\ + "-0.443799, -0.369047, -0.302909, -0.256829, -0.028709",\ + "-0.627085, -0.552322, -0.486182, -0.440095, -0.211908",\ + "-0.932472, -0.857684, -0.791539, -0.745437, -0.517093"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[1]_hldr*/ + +} /* end of pin dft_strap_test_i[1] */ + +pin("dft_strap_test_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000495 ; + + /* Other user defined attributes. */ + original_pin : dft_strap_test_i[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.476989, 0.501509, 0.579333, 0.646918, 1.077745",\ + "0.568510, 0.593031, 0.670855, 0.738440, 1.169267",\ + "0.663180, 0.687701, 0.765525, 0.833110, 1.263937",\ + "0.832054, 0.856556, 0.934380, 1.001965, 1.432792",\ + "1.118659, 1.143116, 1.220940, 1.288525, 1.719352"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.474663, 0.392034, 0.328853, 0.312070, 0.306709",\ + "0.571978, 0.489349, 0.424889, 0.408106, 0.402744",\ + "0.676749, 0.594121, 0.529069, 0.512287, 0.506925",\ + "0.856563, 0.773935, 0.708488, 0.691705, 0.686343",\ + "1.151508, 1.068880, 1.004139, 0.987361, 0.981971"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.289829, -0.215077, -0.148940, -0.102859, 0.125261",\ + "-0.385674, -0.310922, -0.244784, -0.198704, 0.029416",\ + "-0.484928, -0.410176, -0.344038, -0.297958, -0.069838",\ + "-0.657145, -0.582393, -0.516256, -0.470176, -0.242056",\ + "-0.943033, -0.868281, -0.802144, -0.756064, -0.527944"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.269424, -0.228012, -0.195294, -0.158099, 0.070058",\ + "-0.366945, -0.325532, -0.292815, -0.255619, -0.027462",\ + "-0.471935, -0.430523, -0.397805, -0.360610, -0.132453",\ + "-0.650169, -0.608757, -0.576039, -0.538849, -0.310692",\ + "-0.940386, -0.898973, -0.866256, -0.829075, -0.600918"); + } + + } /* end of arc clk_ast_tlul_i_dft_strap_test_i[0]_hldr*/ + +} /* end of pin dft_strap_test_i[0] */ +} /* end of bus dft_strap_test_i */ +bus ( lc_dft_en_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("lc_dft_en_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : lc_dft_en_i[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.116868, 0.046289, 0.009123, -0.011232, -0.072101",\ + "0.130035, 0.060315, 0.022495, 0.001866, -0.059037",\ + "0.171476, 0.101933, 0.064692, 0.043957, -0.021156",\ + "0.330098, 0.263569, 0.222296, 0.198239, 0.112987",\ + "0.772581, 0.713134, 0.646673, 0.609916, 0.496722"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.164832, 0.206226, 0.283518, 0.350873, 0.781571",\ + "0.176771, 0.218346, 0.296254, 0.363875, 0.794722",\ + "0.219963, 0.260510, 0.337961, 0.405191, 0.833567",\ + "0.396019, 0.435268, 0.507744, 0.571712, 0.985407",\ + "0.931350, 0.951153, 1.007354, 1.063861, 1.468564"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.015255, 0.029491, 0.060650, 0.081348, 0.176530",\ + "-0.028040, 0.015174, 0.046352, 0.067152, 0.163478",\ + "-0.067695, -0.029062, 0.006032, 0.028571, 0.126390",\ + "-0.170614, -0.143005, -0.113142, -0.091864, 0.016864",\ + "-0.388675, -0.412783, -0.403332, -0.388997, -0.262218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.058687, -0.133819, -0.215174, -0.276149, -0.608913",\ + "-0.070579, -0.145649, -0.226804, -0.287545, -0.618487",\ + "-0.113780, -0.187774, -0.267897, -0.328130, -0.658063",\ + "-0.257059, -0.339271, -0.416614, -0.475103, -0.797794",\ + "-0.613549, -0.743897, -0.832843, -0.896262, -1.220625"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[3]_hldr*/ + +} /* end of pin lc_dft_en_i[3] */ + +pin("lc_dft_en_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : lc_dft_en_i[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.695925, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.782684, 0.674795"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\ + "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[2]_hldr*/ + +} /* end of pin lc_dft_en_i[2] */ + +pin("lc_dft_en_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : lc_dft_en_i[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.116868, 0.046289, 0.009123, -0.011232, -0.072101",\ + "0.130035, 0.060315, 0.022495, 0.001866, -0.059037",\ + "0.171476, 0.101933, 0.064692, 0.043957, -0.021156",\ + "0.330098, 0.263569, 0.222296, 0.198239, 0.112987",\ + "0.772581, 0.713134, 0.646673, 0.609916, 0.496722"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.164832, 0.206226, 0.283518, 0.350873, 0.781571",\ + "0.176771, 0.218346, 0.296254, 0.363875, 0.794722",\ + "0.219963, 0.260510, 0.337961, 0.405191, 0.833567",\ + "0.396019, 0.435268, 0.507744, 0.571712, 0.985407",\ + "0.931350, 0.951153, 1.007354, 1.063861, 1.468564"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.015255, 0.029491, 0.060650, 0.081348, 0.176530",\ + "-0.028040, 0.015174, 0.046352, 0.067152, 0.163478",\ + "-0.067695, -0.029062, 0.006032, 0.028571, 0.126390",\ + "-0.170614, -0.143005, -0.113142, -0.091864, 0.016864",\ + "-0.388675, -0.412783, -0.403332, -0.388997, -0.262218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.058687, -0.133819, -0.215174, -0.276149, -0.608913",\ + "-0.070579, -0.145649, -0.226804, -0.287545, -0.618487",\ + "-0.113780, -0.187774, -0.267897, -0.328130, -0.658063",\ + "-0.257059, -0.339271, -0.416614, -0.475103, -0.797794",\ + "-0.613549, -0.743897, -0.832843, -0.896262, -1.220625"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[1]_hldr*/ + +} /* end of pin lc_dft_en_i[1] */ + +pin("lc_dft_en_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : lc_dft_en_i[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.200076, 0.146984, 0.107694, 0.091175, 0.087585",\ + "0.210849, 0.158775, 0.118789, 0.101895, 0.097230",\ + "0.247906, 0.195949, 0.156513, 0.139769, 0.134169",\ + "0.400793, 0.347442, 0.307665, 0.290788, 0.285288",\ + "0.811131, 0.757315, 0.714144, 0.695925, 0.691143"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.249331, 0.166333, 0.091045, 0.056957, 0.020498",\ + "0.258619, 0.175944, 0.100656, 0.066835, 0.033618",\ + "0.297457, 0.214925, 0.140086, 0.106583, 0.074986",\ + "0.472698, 0.388796, 0.312903, 0.278157, 0.236728",\ + "0.983325, 0.898854, 0.822917, 0.782684, 0.674795"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.096530, -0.053812, -0.018112, 0.007162, 0.135173",\ + "-0.107327, -0.064625, -0.028931, -0.003653, 0.124428",\ + "-0.144374, -0.101567, -0.065911, -0.040647, 0.087453",\ + "-0.286358, -0.243809, -0.210094, -0.185592, -0.057011",\ + "-0.620310, -0.578080, -0.553843, -0.534595, -0.422314"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.028986, 0.127724, 0.562810, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.130907, -0.055165, 0.010770, 0.056779, 0.285045",\ + "-0.140562, -0.065848, 0.000282, 0.046339, 0.274227",\ + "-0.179341, -0.104491, -0.038333, 0.007805, 0.236523",\ + "-0.350407, -0.276449, -0.208169, -0.160590, 0.074989",\ + "-0.811364, -0.742478, -0.673228, -0.625268, -0.389923"); + } + + } /* end of arc clk_ast_tlul_i_lc_dft_en_i[0]_hldr*/ + +} /* end of pin lc_dft_en_i[0] */ +} /* end of bus lc_dft_en_i */ +bus ( fla_obs_i ) { + + bus_type : BUS8_type14 ; + direction : input ; + +pin("fla_obs_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[7]; +} /* end of pin fla_obs_i[7] */ + +pin("fla_obs_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[6]; +} /* end of pin fla_obs_i[6] */ + +pin("fla_obs_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[5]; +} /* end of pin fla_obs_i[5] */ + +pin("fla_obs_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[4]; +} /* end of pin fla_obs_i[4] */ + +pin("fla_obs_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[3]; +} /* end of pin fla_obs_i[3] */ + +pin("fla_obs_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[2]; +} /* end of pin fla_obs_i[2] */ + +pin("fla_obs_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[1]; +} /* end of pin fla_obs_i[1] */ + +pin("fla_obs_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : fla_obs_i[0]; +} /* end of pin fla_obs_i[0] */ +} /* end of bus fla_obs_i */ +bus ( otp_obs_i ) { + + bus_type : BUS8_type14 ; + direction : input ; + +pin("otp_obs_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[7]; +} /* end of pin otp_obs_i[7] */ + +pin("otp_obs_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[6]; +} /* end of pin otp_obs_i[6] */ + +pin("otp_obs_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[5]; +} /* end of pin otp_obs_i[5] */ + +pin("otp_obs_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[4]; +} /* end of pin otp_obs_i[4] */ + +pin("otp_obs_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[3]; +} /* end of pin otp_obs_i[3] */ + +pin("otp_obs_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[2]; +} /* end of pin otp_obs_i[2] */ + +pin("otp_obs_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[1]; +} /* end of pin otp_obs_i[1] */ + +pin("otp_obs_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otp_obs_i[0]; +} /* end of pin otp_obs_i[0] */ +} /* end of bus otp_obs_i */ +bus ( otm_obs_i ) { + + bus_type : BUS8_type14 ; + direction : input ; + +pin("otm_obs_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[7]; +} /* end of pin otm_obs_i[7] */ + +pin("otm_obs_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[6]; +} /* end of pin otm_obs_i[6] */ + +pin("otm_obs_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[5]; +} /* end of pin otm_obs_i[5] */ + +pin("otm_obs_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[4]; +} /* end of pin otm_obs_i[4] */ + +pin("otm_obs_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[3]; +} /* end of pin otm_obs_i[3] */ + +pin("otm_obs_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[2]; +} /* end of pin otm_obs_i[2] */ + +pin("otm_obs_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000506 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[1]; +} /* end of pin otm_obs_i[1] */ + +pin("otm_obs_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000492 ; + + /* Other user defined attributes. */ + original_pin : otm_obs_i[0]; +} /* end of pin otm_obs_i[0] */ +} /* end of bus otm_obs_i */ + +pin("usb_obs_i") { + direction : input ; + max_transition : 5.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : usb_obs_i; +} /* end of pin usb_obs_i */ +bus ( obs_ctrl_o ) { + + bus_type : BUS12_type15 ; + direction : output ; + +pin("obs_ctrl_o[11]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000605 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[11]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.551399, 0.731602, 0.919092, 1.221084, 1.804596",\ + "0.583544, 0.763747, 0.951237, 1.253229, 1.836741",\ + "0.655451, 0.835654, 1.023144, 1.325136, 1.908648",\ + "0.911916, 1.092119, 1.279609, 1.581602, 2.165114",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.636337, 0.816885, 1.005100, 1.307096, 1.890974",\ + "0.668482, 0.849030, 1.037246, 1.339242, 1.923120",\ + "0.740389, 0.920937, 1.109152, 1.411149, 1.995026",\ + "0.996855, 1.177402, 1.365618, 1.667614, 2.251492",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.712249, 0.892328, 1.079909, 1.381693, 1.965147",\ + "0.744394, 0.924473, 1.112054, 1.413838, 1.997292",\ + "0.816301, 0.996380, 1.183961, 1.485745, 2.069199",\ + "1.072767, 1.252846, 1.440427, 1.742211, 2.325664",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.766618, 0.946840, 1.134560, 1.436233, 2.019464",\ + "0.798764, 0.978985, 1.166705, 1.468378, 2.051609",\ + "0.870670, 1.050892, 1.238612, 1.540285, 2.123516",\ + "1.127136, 1.307358, 1.495078, 1.796751, 2.379982",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.048213, 1.232108, 1.418511, 1.719959, 2.302742",\ + "1.080358, 1.264253, 1.450656, 1.752105, 2.334887",\ + "1.152265, 1.336160, 1.522563, 1.824011, 2.406794",\ + "1.408731, 1.592625, 1.779028, 2.080477, 2.663259",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.410192, 0.677978, 0.939558, 1.379255, 2.258650",\ + "0.437946, 0.705732, 0.967312, 1.407009, 2.286404",\ + "0.489378, 0.757164, 1.018744, 1.458441, 2.337836",\ + "0.655862, 0.923647, 1.185227, 1.624924, 2.504319",\ + "1.246932, 1.514718, 1.776298, 2.215995, 3.095390",\ + "0.498896, 0.766053, 1.028199, 1.467484, 2.346055",\ + "0.526650, 0.793807, 1.055953, 1.495238, 2.373809",\ + "0.578082, 0.845239, 1.107385, 1.546670, 2.425241",\ + "0.744566, 1.011722, 1.273868, 1.713154, 2.591724",\ + "1.335636, 1.602793, 1.864939, 2.304224, 3.182795",\ + "0.591838, 0.859198, 1.119924, 1.559648, 2.439097",\ + "0.619592, 0.886952, 1.147678, 1.587402, 2.466851",\ + "0.671024, 0.938384, 1.199110, 1.638834, 2.518283",\ + "0.837508, 1.104867, 1.365594, 1.805318, 2.684766",\ + "1.428578, 1.695938, 1.956664, 2.396388, 3.275837",\ + "0.657682, 0.927762, 1.186944, 1.626498, 2.505608",\ + "0.685436, 0.955516, 1.214698, 1.654252, 2.533362",\ + "0.736868, 1.006948, 1.266130, 1.705685, 2.584794",\ + "0.903352, 1.173432, 1.432614, 1.872168, 2.751277",\ + "1.494422, 1.764502, 2.023684, 2.463239, 3.342348",\ + "1.004203, 1.308598, 1.557607, 1.995652, 2.871743",\ + "1.031957, 1.336352, 1.585361, 2.023406, 2.899497",\ + "1.083390, 1.387784, 1.636793, 2.074838, 2.950930",\ + "1.249873, 1.554267, 1.803276, 2.241322, 3.117413",\ + "1.840944, 2.145338, 2.394347, 2.832392, 3.708484"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2706*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.459504, 0.723077, 0.999350, 1.468080, 2.405539",\ + "0.491649, 0.755223, 1.031495, 1.500225, 2.437684",\ + "0.563556, 0.827130, 1.103402, 1.572132, 2.509591",\ + "0.820022, 1.083595, 1.359868, 1.828597, 2.766056",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.547698, 0.810618, 1.086918, 1.554795, 2.491473",\ + "0.579843, 0.842764, 1.119063, 1.586940, 2.523618",\ + "0.651750, 0.914670, 1.190970, 1.658847, 2.595525",\ + "0.908216, 1.171136, 1.447435, 1.915312, 2.851990",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.636014, 0.899599, 1.174883, 1.642418, 2.578428",\ + "0.668159, 0.931744, 1.207028, 1.674563, 2.610573",\ + "0.740066, 1.003651, 1.278935, 1.746470, 2.682480",\ + "0.996532, 1.260116, 1.535400, 2.002935, 2.938945",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.698510, 0.965234, 1.239022, 1.706331, 2.641937",\ + "0.730655, 0.997379, 1.271168, 1.738477, 2.674082",\ + "0.802562, 1.069286, 1.343075, 1.810383, 2.745989",\ + "1.059028, 1.325751, 1.599540, 2.066849, 3.002454",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.027636, 1.329564, 1.590890, 2.055681, 2.987393",\ + "1.059781, 1.361710, 1.623035, 2.087826, 3.019538",\ + "1.131688, 1.433616, 1.694942, 2.159733, 3.091445",\ + "1.388154, 1.690082, 1.951407, 2.416198, 3.347910",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703320, 0.703316",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.393145, 0.575577, 0.771969, 1.081022, 1.675830",\ + "0.420899, 0.603331, 0.799723, 1.108776, 1.703585",\ + "0.472331, 0.654763, 0.851155, 1.160208, 1.755017",\ + "0.638815, 0.821247, 1.017638, 1.326692, 1.921499",\ + "1.229885, 1.412317, 1.608709, 1.917762, 2.512568",\ + "0.480560, 0.662962, 0.859462, 1.168327, 1.763184",\ + "0.508314, 0.690716, 0.887216, 1.196081, 1.790938",\ + "0.559746, 0.742149, 0.938648, 1.247514, 1.842370",\ + "0.726229, 0.908632, 1.105132, 1.413997, 2.008852",\ + "1.317300, 1.499703, 1.696202, 2.005067, 2.599921",\ + "0.561436, 0.743299, 0.939489, 1.248356, 1.843215",\ + "0.589190, 0.771053, 0.967243, 1.276110, 1.870970",\ + "0.640622, 0.822485, 1.018675, 1.327542, 1.922402",\ + "0.807106, 0.988969, 1.185158, 1.494025, 2.088884",\ + "1.398176, 1.580039, 1.776229, 2.085095, 2.679953",\ + "0.619083, 0.800848, 0.997033, 1.305601, 1.899863",\ + "0.646837, 0.828601, 1.024787, 1.333355, 1.927617",\ + "0.698269, 0.880034, 1.076219, 1.384787, 1.979049",\ + "0.864752, 1.046517, 1.242702, 1.551270, 2.145531",\ + "1.455823, 1.637588, 1.833773, 2.142340, 2.736601",\ + "0.921290, 1.106072, 1.300666, 1.608616, 2.201710",\ + "0.949044, 1.133826, 1.328420, 1.636370, 2.229464",\ + "1.000476, 1.185258, 1.379853, 1.687802, 2.280896",\ + "1.166960, 1.351742, 1.546336, 1.854285, 2.447378",\ + "1.758030, 1.942812, 2.137407, 2.445355, 3.038447"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066652",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2637*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.455529, 0.715158, 0.987030, 1.443910, 2.357670",\ + "0.487674, 0.747303, 1.019175, 1.476055, 2.389815",\ + "0.559581, 0.819210, 1.091082, 1.547962, 2.461721",\ + "0.816046, 1.075675, 1.347547, 1.804427, 2.718186",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.543634, 0.802691, 1.074561, 1.530625, 2.443603",\ + "0.575779, 0.834837, 1.106706, 1.562770, 2.475748",\ + "0.647686, 0.906743, 1.178613, 1.634677, 2.547655",\ + "0.904151, 1.163209, 1.435078, 1.891142, 2.804120",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.631664, 0.891657, 1.162525, 1.618248, 2.530558",\ + "0.663809, 0.923802, 1.194670, 1.650393, 2.562703",\ + "0.735716, 0.995709, 1.266577, 1.722300, 2.634610",\ + "0.992181, 1.252175, 1.523042, 1.978765, 2.891075",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.693885, 0.957271, 1.226663, 1.682162, 2.594067",\ + "0.726030, 0.989416, 1.258808, 1.714307, 2.626212",\ + "0.797937, 1.061323, 1.330715, 1.786214, 2.698119",\ + "1.054402, 1.317788, 1.587180, 2.042679, 2.954584",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.021272, 1.321346, 1.578410, 2.031462, 2.939523",\ + "1.053417, 1.353491, 1.610555, 2.063607, 2.971668",\ + "1.125324, 1.425398, 1.682462, 2.135514, 3.043575",\ + "1.381790, 1.681863, 1.938927, 2.391979, 3.300040",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034925",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211195, 0.211195",\ + "0.703322, 0.703322, 0.703321, 0.703318, 0.703312",\ + "2.463890, 2.463889, 2.463888, 2.463885, 2.463879"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.391484, 0.574025, 0.770279, 1.079497, 1.674793",\ + "0.419237, 0.601779, 0.798033, 1.107251, 1.702548",\ + "0.470670, 0.653211, 0.849465, 1.158683, 1.753979",\ + "0.637153, 0.819694, 1.015949, 1.325166, 1.920461",\ + "1.228224, 1.410765, 1.607020, 1.916236, 2.511531",\ + "0.478904, 0.661410, 0.857772, 1.166802, 1.762147",\ + "0.506657, 0.689164, 0.885526, 1.194556, 1.789901",\ + "0.558090, 0.740596, 0.936958, 1.245988, 1.841333",\ + "0.724573, 0.907080, 1.103442, 1.412471, 2.007815",\ + "1.315644, 1.498150, 1.694512, 2.003541, 2.598884",\ + "0.559771, 0.741747, 0.937799, 1.246830, 1.842178",\ + "0.587525, 0.769501, 0.965553, 1.274584, 1.869933",\ + "0.638957, 0.820933, 1.016985, 1.326016, 1.921365",\ + "0.805441, 0.987416, 1.183469, 1.492499, 2.087847",\ + "1.396511, 1.578487, 1.774539, 2.083570, 2.678916",\ + "0.617410, 0.799295, 0.995343, 1.304075, 1.898826",\ + "0.645164, 0.827049, 1.023097, 1.331829, 1.926580",\ + "0.696596, 0.878481, 1.074529, 1.383261, 1.978012",\ + "0.863080, 1.044965, 1.241013, 1.549745, 2.144494",\ + "1.454150, 1.636036, 1.832083, 2.140815, 2.735564",\ + "0.919505, 1.104522, 1.298977, 1.607090, 2.200673",\ + "0.947259, 1.132276, 1.326731, 1.634844, 2.228427",\ + "0.998691, 1.183708, 1.378163, 1.686276, 2.279859",\ + "1.165175, 1.350191, 1.544647, 1.852759, 2.446341",\ + "1.756245, 1.941262, 2.135717, 2.443830, 3.037410"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036751",\ + "0.066655, 0.066655, 0.066655, 0.066654, 0.066651",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440315",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523674"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2582*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.547812, 0.726239, 0.906500, 1.192706, 1.743823",\ + "0.579958, 0.758384, 0.938645, 1.224851, 1.775968",\ + "0.651865, 0.830291, 1.010552, 1.296758, 1.847875",\ + "0.908330, 1.086757, 1.267017, 1.553223, 2.104340",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.632751, 0.811512, 0.992415, 1.278626, 1.830201",\ + "0.664896, 0.843657, 1.024560, 1.310771, 1.862346",\ + "0.736803, 0.915564, 1.096467, 1.382678, 1.934253",\ + "0.993268, 1.172029, 1.352932, 1.639144, 2.190719",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.708657, 0.886955, 1.067224, 1.353223, 1.904374",\ + "0.740802, 0.919100, 1.099369, 1.385368, 1.936519",\ + "0.812709, 0.991007, 1.171276, 1.457275, 2.008426",\ + "1.069174, 1.247472, 1.427741, 1.713740, 2.264891",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.763009, 0.941467, 1.121875, 1.407763, 1.958691",\ + "0.795154, 0.973612, 1.154020, 1.439908, 1.990836",\ + "0.867061, 1.045519, 1.225927, 1.511815, 2.062743",\ + "1.123527, 1.301984, 1.482392, 1.768280, 2.319208",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.044431, 1.226694, 1.405825, 1.691489, 2.241968",\ + "1.076576, 1.258839, 1.437970, 1.723634, 2.274114",\ + "1.148483, 1.330746, 1.509877, 1.795541, 2.346020",\ + "1.404948, 1.587211, 1.766343, 2.052006, 2.602486",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.034926, 0.034926, 0.034926, 0.034926, 0.034926",\ + "0.080177, 0.080177, 0.080177, 0.080177, 0.080177",\ + "0.211196, 0.211196, 0.211196, 0.211196, 0.211196",\ + "0.703322, 0.703322, 0.703322, 0.703322, 0.703322",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.408756, 0.673926, 0.933128, 1.369310, 2.241675",\ + "0.436510, 0.701680, 0.960881, 1.397064, 2.269429",\ + "0.487942, 0.753112, 1.012314, 1.448496, 2.320861",\ + "0.654426, 0.919595, 1.178797, 1.614980, 2.487345",\ + "1.245496, 1.510666, 1.769868, 2.206050, 3.078415",\ + "0.497422, 0.762001, 1.021768, 1.457539, 2.329080",\ + "0.525175, 0.789755, 1.049522, 1.485293, 2.356834",\ + "0.576608, 0.841187, 1.100955, 1.536725, 2.408266",\ + "0.743091, 1.007670, 1.267438, 1.703208, 2.574750",\ + "1.334162, 1.598741, 1.858509, 2.294279, 3.165820",\ + "0.590228, 0.855124, 1.113494, 1.549703, 2.422122",\ + "0.617982, 0.882878, 1.141248, 1.577457, 2.449876",\ + "0.669414, 0.934310, 1.192680, 1.628889, 2.501308",\ + "0.835898, 1.100793, 1.359163, 1.795373, 2.667792",\ + "1.426969, 1.691864, 1.950234, 2.386443, 3.258862",\ + "0.655951, 0.923658, 1.180514, 1.616553, 2.488633",\ + "0.683705, 0.951412, 1.208267, 1.644307, 2.516387",\ + "0.735137, 1.002844, 1.259700, 1.695739, 2.567819",\ + "0.901620, 1.169327, 1.426183, 1.862223, 2.734303",\ + "1.492691, 1.760398, 2.017254, 2.453294, 3.325373",\ + "1.001740, 1.304156, 1.551144, 1.985685, 2.854766",\ + "1.029494, 1.331910, 1.578898, 2.013438, 2.882520",\ + "1.080926, 1.383342, 1.630330, 2.064871, 2.933952",\ + "1.247410, 1.549826, 1.796813, 2.231354, 3.100436",\ + "1.838480, 2.140896, 2.387884, 2.822425, 3.691506"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677",\ + "0.036752, 0.036752, 0.036752, 0.036752, 0.036752",\ + "0.066655, 0.066655, 0.066655, 0.066655, 0.066655",\ + "0.142207, 0.142207, 0.142207, 0.142207, 0.142207",\ + "0.440316, 0.440316, 0.440316, 0.440316, 0.440316",\ + "1.523676, 1.523676, 1.523676, 1.523676, 1.523677"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_2520*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.315086, 0.347231, 0.419138, 0.675604, 1.594576",\ + "0.402477, 0.434622, 0.506529, 0.762995, 1.681967",\ + "0.483396, 0.515541, 0.587448, 0.843914, 1.762885",\ + "0.541136, 0.573281, 0.645189, 0.901655, 1.820624",\ + "0.843842, 0.875987, 0.947895, 1.204361, 2.123326"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.034927, 0.080178, 0.211197, 0.703303, 2.463871",\ + "0.034927, 0.080178, 0.211262, 0.703303, 2.463871",\ + "0.034927, 0.080178, 0.211506, 0.703303, 2.463871",\ + "0.034928, 0.080178, 0.211506, 0.703303, 2.463871",\ + "0.035124, 0.080207, 0.211847, 0.703316, 2.463884"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.288640, 0.316394, 0.367826, 0.534309, 1.125380",\ + "0.376032, 0.403786, 0.455218, 0.621702, 1.212772",\ + "0.456902, 0.484656, 0.536088, 0.702571, 1.293642",\ + "0.514551, 0.542304, 0.593737, 0.760220, 1.351291",\ + "0.817630, 0.845638, 0.897452, 1.064344, 1.655102"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.036752, 0.066655, 0.142211, 0.440316, 1.524426",\ + "0.036752, 0.066655, 0.142211, 0.440316, 1.524426",\ + "0.036752, 0.066655, 0.142211, 0.440316, 1.524300",\ + "0.036752, 0.066655, 0.142211, 0.440316, 1.524064",\ + "0.036746, 0.066581, 0.142211, 0.440310, 1.523676"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.499182, 0.679295, 0.866874, 1.168853, 1.751950",\ + "0.529816, 0.709930, 0.897508, 1.199488, 1.782584",\ + "0.601083, 0.781197, 0.968775, 1.270755, 1.853851",\ + "0.856808, 1.036922, 1.224500, 1.526480, 2.109576",\ + "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\ + "0.584120, 0.764131, 0.951944, 1.254360, 1.838328",\ + "0.614754, 0.794765, 0.982578, 1.284994, 1.868962",\ + "0.686022, 0.866033, 1.053846, 1.356261, 1.940230",\ + "0.941746, 1.121757, 1.309570, 1.611986, 2.195954",\ + "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\ + "0.660032, 0.839574, 1.026753, 1.328956, 1.912500",\ + "0.690666, 0.870209, 1.057387, 1.359591, 1.943135",\ + "0.761934, 0.941476, 1.128654, 1.430858, 2.014402",\ + "1.017658, 1.197201, 1.384379, 1.686583, 2.270127",\ + "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\ + "0.714401, 0.894326, 1.081641, 1.383562, 1.966818",\ + "0.745036, 0.924960, 1.112276, 1.414196, 1.997452",\ + "0.816303, 0.996228, 1.183543, 1.485464, 2.068719",\ + "1.072027, 1.251952, 1.439268, 1.741188, 2.324444",\ + "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\ + "0.995996, 1.179891, 1.365817, 1.667288, 2.250095",\ + "1.026630, 1.210525, 1.396451, 1.697923, 2.280730",\ + "1.097898, 1.281793, 1.467719, 1.769190, 2.351997",\ + "1.353622, 1.537517, 1.723443, 2.024915, 2.607721",\ + "2.270849, 2.454743, 2.640669, 2.942141, 3.524948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.382273, 0.649883, 0.911284, 1.351061, 2.230222",\ + "0.407140, 0.674750, 0.936142, 1.375888, 2.254987",\ + "0.455457, 0.723068, 0.984460, 1.424205, 2.303304",\ + "0.620747, 0.888357, 1.149749, 1.589495, 2.468594",\ + "1.214576, 1.482187, 1.743588, 2.183365, 3.062526",\ + "0.470977, 0.737958, 0.999925, 1.439290, 2.317627",\ + "0.495844, 0.762825, 1.024783, 1.464117, 2.342392",\ + "0.544161, 0.811142, 1.073101, 1.512434, 2.390709",\ + "0.709451, 0.976432, 1.238390, 1.677724, 2.555999",\ + "1.303280, 1.570262, 1.832229, 2.271594, 3.149931",\ + "0.563919, 0.831278, 1.091970, 1.531536, 2.410669",\ + "0.588786, 0.856145, 1.116828, 1.556363, 2.435434",\ + "0.637103, 0.904463, 1.165145, 1.604680, 2.483751",\ + "0.802393, 1.069752, 1.330435, 1.769970, 2.649041",\ + "1.396222, 1.663582, 1.924273, 2.363840, 3.242973",\ + "0.629763, 0.899843, 1.159026, 1.598547, 2.477591",\ + "0.654629, 0.924710, 1.183884, 1.623374, 2.502355",\ + "0.702947, 0.973027, 1.232201, 1.671691, 2.550673",\ + "0.868237, 1.138317, 1.397491, 1.836981, 2.715962",\ + "1.462066, 1.732146, 1.991329, 2.430851, 3.309894",\ + "0.976284, 1.280678, 1.529696, 1.967773, 2.843926",\ + "1.001151, 1.305545, 1.554554, 1.992599, 2.868690",\ + "1.049468, 1.353863, 1.602872, 2.040917, 2.917008",\ + "1.214758, 1.519152, 1.768161, 2.206207, 3.082298",\ + "1.808588, 2.112982, 2.362000, 2.800076, 3.676230"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2461*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.407290, 0.670821, 0.946941, 1.415072, 2.350076",\ + "0.437925, 0.701456, 0.977575, 1.445707, 2.380711",\ + "0.509192, 0.772723, 1.048843, 1.516974, 2.451978",\ + "0.764916, 1.028448, 1.304567, 1.772699, 2.707703",\ + "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\ + "0.495484, 0.758362, 1.034508, 1.501788, 2.436010",\ + "0.526119, 0.788996, 1.065142, 1.532422, 2.466645",\ + "0.597386, 0.860264, 1.136409, 1.603690, 2.537912",\ + "0.853111, 1.115988, 1.392134, 1.859414, 2.793636",\ + "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\ + "0.583800, 0.847341, 1.122472, 1.589428, 2.522965",\ + "0.614435, 0.877976, 1.153107, 1.620063, 2.553600",\ + "0.685702, 0.949243, 1.224374, 1.691330, 2.624867",\ + "0.941427, 1.204967, 1.480099, 1.947054, 2.880591",\ + "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\ + "0.646296, 0.912975, 1.186612, 1.653517, 2.586474",\ + "0.676931, 0.943609, 1.217247, 1.684151, 2.617109",\ + "0.748198, 1.014877, 1.288514, 1.755419, 2.688376",\ + "1.003923, 1.270601, 1.544238, 2.011143, 2.944100",\ + "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\ + "0.975422, 1.277290, 1.538476, 2.002961, 2.931930",\ + "1.006057, 1.307924, 1.569111, 2.033595, 2.962565",\ + "1.077324, 1.379191, 1.640378, 2.104863, 3.033832",\ + "1.333048, 1.634916, 1.896102, 2.360587, 3.289557",\ + "2.250275, 2.552142, 2.813329, 3.277813, 4.206782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.031515, 0.031515, 0.031516, 0.031516, 0.031517",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699348",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.365228, 0.547285, 0.743519, 1.052700, 1.647184",\ + "0.390093, 0.572150, 0.768283, 1.077415, 1.671868",\ + "0.438410, 0.620468, 0.816601, 1.125732, 1.720186",\ + "0.603700, 0.785757, 0.981890, 1.291023, 1.885478",\ + "1.197531, 1.379589, 1.575822, 1.885003, 2.479486",\ + "0.452642, 0.634604, 0.830800, 1.140005, 1.734538",\ + "0.477507, 0.659469, 0.855564, 1.164720, 1.759222",\ + "0.525825, 0.707786, 0.903881, 1.213037, 1.807539",\ + "0.691115, 0.873076, 1.069171, 1.378328, 1.972831",\ + "1.284946, 1.466908, 1.663103, 1.972308, 2.566839",\ + "0.533519, 0.714940, 0.910827, 1.220034, 1.814569",\ + "0.558384, 0.739805, 0.935591, 1.244748, 1.839253",\ + "0.606701, 0.788123, 0.983908, 1.293066, 1.887571",\ + "0.771991, 0.953413, 1.149198, 1.458356, 2.052863",\ + "1.365822, 1.547244, 1.743130, 2.052336, 2.646871",\ + "0.591165, 0.772777, 0.968562, 1.277504, 1.871665",\ + "0.616030, 0.797642, 0.993326, 1.302219, 1.896349",\ + "0.664348, 0.845960, 1.041644, 1.350536, 1.944667",\ + "0.829637, 1.011249, 1.206933, 1.515826, 2.109958",\ + "1.423469, 1.605081, 1.800866, 2.109807, 2.703966",\ + "0.893373, 1.078154, 1.272226, 1.580711, 2.173983",\ + "0.918238, 1.103019, 1.296990, 1.605426, 2.198667",\ + "0.966555, 1.151337, 1.345307, 1.653743, 2.246984",\ + "1.131845, 1.316627, 1.510597, 1.819033, 2.412276",\ + "1.725676, 1.910458, 2.104529, 2.413014, 3.006285"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435755, 0.435768",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2383*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.403312, 0.662871, 0.934506, 1.390667, 2.301835",\ + "0.433946, 0.693506, 0.965141, 1.421302, 2.332470",\ + "0.505214, 0.764773, 1.036408, 1.492569, 2.403737",\ + "0.760938, 1.020497, 1.292132, 1.748294, 2.659461",\ + "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\ + "0.491417, 0.750404, 1.022035, 1.477383, 2.387769",\ + "0.522051, 0.781039, 1.052670, 1.508018, 2.418404",\ + "0.593319, 0.852306, 1.123937, 1.579285, 2.489671",\ + "0.849043, 1.108030, 1.379661, 1.835009, 2.745395",\ + "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\ + "0.579447, 0.839368, 1.109999, 1.565022, 2.474724",\ + "0.610081, 0.870003, 1.140634, 1.595656, 2.505359",\ + "0.681349, 0.941270, 1.211901, 1.666924, 2.576626",\ + "0.937073, 1.196995, 1.467626, 1.922648, 2.832350",\ + "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\ + "0.641668, 0.904980, 1.174137, 1.629096, 2.538233",\ + "0.672303, 0.935614, 1.204772, 1.659731, 2.568868",\ + "0.743570, 1.006881, 1.276039, 1.730998, 2.640135",\ + "0.999294, 1.262606, 1.531763, 1.986722, 2.895859",\ + "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\ + "0.969056, 1.269028, 1.525880, 1.978482, 2.883689",\ + "0.999690, 1.299663, 1.556514, 2.009117, 2.914324",\ + "1.070957, 1.370930, 1.627782, 2.080384, 2.985591",\ + "1.326682, 1.626654, 1.883506, 2.336109, 3.241315",\ + "2.243908, 2.543881, 2.800732, 3.253335, 4.158542"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.031515, 0.031515, 0.031516, 0.031517, 0.031519",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077661",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699349, 0.699347",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.363564, 0.545731, 0.741830, 1.051168, 1.646128",\ + "0.388431, 0.570598, 0.766595, 1.075888, 1.670830",\ + "0.436748, 0.618916, 0.814913, 1.124206, 1.719148",\ + "0.602038, 0.784206, 0.980202, 1.289496, 1.884440",\ + "1.195867, 1.378035, 1.574133, 1.883471, 2.478430",\ + "0.450984, 0.633050, 0.829111, 1.138473, 1.733482",\ + "0.475851, 0.657917, 0.853876, 1.163193, 1.758184",\ + "0.524168, 0.706235, 0.902193, 1.211511, 1.806502",\ + "0.689458, 0.871524, 1.067483, 1.376801, 1.971793",\ + "1.283288, 1.465354, 1.661414, 1.970776, 2.565784",\ + "0.531851, 0.713387, 0.909137, 1.218501, 1.813514",\ + "0.556719, 0.738254, 0.933903, 1.243222, 1.838215",\ + "0.605036, 0.786572, 0.982220, 1.291539, 1.886533",\ + "0.770326, 0.951861, 1.147510, 1.456830, 2.051825",\ + "1.364155, 1.545691, 1.741441, 2.050804, 2.645815",\ + "0.589490, 0.771224, 0.966873, 1.275972, 1.870610",\ + "0.614358, 0.796091, 0.991638, 1.300693, 1.895312",\ + "0.662675, 0.844408, 1.039955, 1.349010, 1.943630",\ + "0.827965, 1.009698, 1.205245, 1.514301, 2.108922",\ + "1.421794, 1.603527, 1.799176, 2.108275, 2.702911",\ + "0.891585, 1.076602, 1.270536, 1.579180, 2.172930",\ + "0.916453, 1.101469, 1.295302, 1.603900, 2.197631",\ + "0.964770, 1.149787, 1.343619, 1.652218, 2.245949",\ + "1.130060, 1.315076, 1.508909, 1.817508, 2.411241",\ + "1.723889, 1.908906, 2.102840, 2.411483, 3.005231"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017",\ + "0.028581, 0.028581, 0.028581, 0.028582, 0.028582",\ + "0.057562, 0.057562, 0.057562, 0.057563, 0.057564",\ + "0.134857, 0.134857, 0.134857, 0.134858, 0.134859",\ + "0.435749, 0.435749, 0.435750, 0.435756, 0.435770",\ + "1.519015, 1.519015, 1.519015, 1.519016, 1.519017"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2325*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.495595, 0.673935, 0.854281, 1.140468, 1.691221",\ + "0.526230, 0.704569, 0.884916, 1.171102, 1.721856",\ + "0.597497, 0.775836, 0.956183, 1.242370, 1.793123",\ + "0.853221, 1.031561, 1.211908, 1.498094, 2.048847",\ + "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\ + "0.580534, 0.758770, 0.939351, 1.225974, 1.777599",\ + "0.611168, 0.789405, 0.969986, 1.256609, 1.808234",\ + "0.682435, 0.860672, 1.041253, 1.327876, 1.879501",\ + "0.938160, 1.116397, 1.296978, 1.583601, 2.135226",\ + "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\ + "0.656440, 0.834214, 1.014160, 1.300571, 1.851772",\ + "0.687074, 0.864848, 1.044795, 1.331205, 1.882406",\ + "0.758341, 0.936116, 1.116062, 1.402473, 1.953674",\ + "1.014066, 1.191840, 1.371787, 1.658197, 2.209398",\ + "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\ + "0.710792, 0.888959, 1.069026, 1.355165, 1.906089",\ + "0.741426, 0.919594, 1.099660, 1.385799, 1.936724",\ + "0.812694, 0.990861, 1.170928, 1.457067, 2.007991",\ + "1.068418, 1.246586, 1.426652, 1.712791, 2.263715",\ + "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\ + "0.992214, 1.174477, 1.353179, 1.638891, 2.189367",\ + "1.022848, 1.205111, 1.383813, 1.669525, 2.220001",\ + "1.094115, 1.276379, 1.455081, 1.740793, 2.291269",\ + "1.349840, 1.532103, 1.710805, 1.996517, 2.546993",\ + "2.267066, 2.449329, 2.628031, 2.913743, 3.464219"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.031515, 0.031515, 0.031515, 0.031515, 0.031515",\ + "0.077660, 0.077660, 0.077660, 0.077660, 0.077660",\ + "0.209649, 0.209649, 0.209649, 0.209649, 0.209649",\ + "0.699350, 0.699350, 0.699350, 0.699350, 0.699350",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.380837, 0.645836, 0.904865, 1.341130, 2.213276",\ + "0.405704, 0.670703, 0.929723, 1.365952, 2.238030",\ + "0.454021, 0.719020, 0.978040, 1.414270, 2.286347",\ + "0.619311, 0.884310, 1.143330, 1.579559, 2.451637",\ + "1.213140, 1.478139, 1.737169, 2.173433, 3.045579",\ + "0.469502, 0.733911, 0.993506, 1.429358, 2.300681",\ + "0.494369, 0.758778, 1.018363, 1.454181, 2.325435",\ + "0.542686, 0.807095, 1.066681, 1.502498, 2.373752",\ + "0.707976, 0.972385, 1.231971, 1.667788, 2.539042",\ + "1.301806, 1.566214, 1.825810, 2.261662, 3.132985",\ + "0.562309, 0.827204, 1.085541, 1.521602, 2.393723",\ + "0.587176, 0.852071, 1.110399, 1.546425, 2.418477",\ + "0.635493, 0.900389, 1.158716, 1.594742, 2.466794",\ + "0.800783, 1.065678, 1.324006, 1.760032, 2.632084",\ + "1.394613, 1.659508, 1.917845, 2.353905, 3.226027",\ + "0.628031, 0.895738, 1.152596, 1.588608, 2.460633",\ + "0.652898, 0.920605, 1.177454, 1.613431, 2.485386",\ + "0.701216, 0.968923, 1.225771, 1.661748, 2.533704",\ + "0.866506, 1.134212, 1.391061, 1.827038, 2.698993",\ + "1.460335, 1.728042, 1.984900, 2.420912, 3.292936",\ + "0.973821, 1.276237, 1.523234, 1.957809, 2.826960",\ + "0.998688, 1.301104, 1.548091, 1.982632, 2.851713",\ + "1.047005, 1.349421, 1.596409, 2.030949, 2.900031",\ + "1.212295, 1.514711, 1.761698, 2.196239, 3.065320",\ + "1.806124, 2.108541, 2.355538, 2.790113, 3.659263"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015",\ + "0.028581, 0.028581, 0.028581, 0.028581, 0.028581",\ + "0.057562, 0.057562, 0.057562, 0.057562, 0.057562",\ + "0.134857, 0.134857, 0.134857, 0.134857, 0.134857",\ + "0.435749, 0.435749, 0.435749, 0.435749, 0.435750",\ + "1.519015, 1.519015, 1.519015, 1.519015, 1.519015"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min_2267*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.132999, 0.164048, 0.235821, 0.492102, 1.411098",\ + "0.221194, 0.252231, 0.324016, 0.580346, 1.499024",\ + "0.309537, 0.340556, 0.412339, 0.668869, 1.587106",\ + "0.372125, 0.403153, 0.474871, 0.731698, 1.650402",\ + "0.701985, 0.733051, 0.804557, 1.061823, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\ + "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\ + "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\ + "0.031515, 0.077660, 0.209649, 0.699350, 2.448223",\ + "0.031515, 0.077660, 0.209649, 0.699350, 2.448223"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.172647, 0.198025, 0.247447, 0.413179, 1.004020",\ + "0.260051, 0.285429, 0.334851, 0.500582, 1.091424",\ + "0.340949, 0.366324, 0.415751, 0.581486, 1.172337",\ + "0.398613, 0.423981, 0.473417, 0.639160, 1.230028",\ + "0.700957, 0.726326, 0.775791, 0.941604, 1.532645"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.028580, 0.057560, 0.134856, 0.434927, 1.516730",\ + "0.028580, 0.057560, 0.134856, 0.434927, 1.516730",\ + "0.028580, 0.057560, 0.134856, 0.434975, 1.516730",\ + "0.028580, 0.057560, 0.134856, 0.435062, 1.516730",\ + "0.028580, 0.057561, 0.134856, 0.435749, 1.516730"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[11]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.079929, 0.111758, 0.183223, 0.439138, 1.359203",\ + "0.167497, 0.199454, 0.270769, 0.526908, 1.444562",\ + "0.264286, 0.298668, 0.370756, 0.626584, 1.547694",\ + "0.439501, 0.480020, 0.554277, 0.809849, 1.732299",\ + "0.736451, 0.793429, 0.877676, 1.133252, 2.048527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.033688, 0.079103, 0.210853, 0.705450, 2.481454",\ + "0.034938, 0.079398, 0.210853, 0.707160, 2.481454",\ + "0.042553, 0.084403, 0.210853, 0.707160, 2.481454",\ + "0.062025, 0.097740, 0.214926, 0.707160, 2.481454",\ + "0.107816, 0.136398, 0.233803, 0.707160, 2.481454"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.118927, 0.147104, 0.198913, 0.365810, 0.957538",\ + "0.198088, 0.226133, 0.277877, 0.444754, 1.035269",\ + "0.300437, 0.331131, 0.384010, 0.550764, 1.143163",\ + "0.474766, 0.514213, 0.573035, 0.741315, 1.332791",\ + "0.755439, 0.816369, 0.892028, 1.065959, 1.655414"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.037147, 0.066922, 0.142202, 0.440625, 1.525476",\ + "0.037147, 0.066922, 0.142202, 0.440625, 1.525476",\ + "0.046795, 0.072955, 0.144989, 0.440625, 1.525476",\ + "0.074873, 0.097054, 0.159133, 0.443319, 1.525476",\ + "0.131163, 0.155817, 0.206305, 0.453921, 1.527125"); + } + + } /* end of arc padmux2ast_i[3]_obs_ctrl_o[11]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.076002, 0.106508, 0.177677, 0.433841, 1.352120",\ + "0.163173, 0.193992, 0.265018, 0.521506, 1.439207",\ + "0.258934, 0.291253, 0.363111, 0.618813, 1.536303",\ + "0.430665, 0.469075, 0.541536, 0.798208, 1.718362",\ + "0.721771, 0.774421, 0.855976, 1.109381, 2.025527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.030664, 0.077525, 0.209536, 0.696987, 2.440521",\ + "0.032038, 0.077878, 0.209536, 0.696987, 2.440521",\ + "0.038668, 0.082173, 0.210178, 0.699757, 2.449750",\ + "0.056119, 0.094147, 0.214335, 0.699757, 2.460771",\ + "0.095850, 0.132052, 0.230566, 0.703608, 2.462313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.085902, 0.110542, 0.159236, 0.324759, 0.917124",\ + "0.171172, 0.195634, 0.244356, 0.409704, 1.001295",\ + "0.269100, 0.297524, 0.347992, 0.513168, 1.105193",\ + "0.434670, 0.473174, 0.529868, 0.695133, 1.285706",\ + "0.702119, 0.762927, 0.838318, 1.010679, 1.597765"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000605, 0.003844, 0.012425, 0.043741, 0.156168"); + values ( "0.029180, 0.058574, 0.135500, 0.435380, 1.519944",\ + "0.030330, 0.058789, 0.135664, 0.436655, 1.520555",\ + "0.042270, 0.067457, 0.139493, 0.437267, 1.520555",\ + "0.069987, 0.091747, 0.153270, 0.440379, 1.520568",\ + "0.124960, 0.149736, 0.200354, 0.450127, 1.523278"); + } + + } /* end of arc padmux2ast_i[3]_obs_ctrl_o[11]_una_min*/ + +} /* end of pin obs_ctrl_o[11] */ + +pin("obs_ctrl_o[10]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002440 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[10]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.570547, 0.750750, 0.938240, 1.240232, 1.823744",\ + "0.598946, 0.779149, 0.966639, 1.268632, 1.852144",\ + "0.670479, 0.850682, 1.038172, 1.340165, 1.923677",\ + "0.926915, 1.107118, 1.294608, 1.596601, 2.180113",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.655485, 0.836033, 1.024249, 1.326245, 1.910123",\ + "0.683885, 0.864432, 1.052648, 1.354644, 1.938522",\ + "0.755418, 0.935965, 1.124181, 1.426177, 2.010055",\ + "1.011854, 1.192401, 1.380617, 1.682613, 2.266491",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.731397, 0.911476, 1.099057, 1.400841, 1.984295",\ + "0.759797, 0.939876, 1.127457, 1.429241, 2.012694",\ + "0.831330, 1.011409, 1.198990, 1.500774, 2.084227",\ + "1.087766, 1.267845, 1.455426, 1.757210, 2.340663",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.785767, 0.965988, 1.153708, 1.455381, 2.038612",\ + "0.814166, 0.994387, 1.182108, 1.483781, 2.067012",\ + "0.885699, 1.065920, 1.253641, 1.555314, 2.138545",\ + "1.142135, 1.322356, 1.510077, 1.811749, 2.394980",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.067361, 1.251256, 1.437659, 1.739108, 2.321890",\ + "1.095761, 1.279655, 1.466058, 1.767507, 2.350289",\ + "1.167294, 1.351188, 1.537591, 1.839040, 2.421822",\ + "1.423730, 1.607624, 1.794027, 2.095476, 2.678258",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.426873, 0.694659, 0.956239, 1.395936, 2.275331",\ + "0.448702, 0.716487, 0.978067, 1.417764, 2.297159",\ + "0.498842, 0.766628, 1.028208, 1.467905, 2.347300",\ + "0.665219, 0.933004, 1.194584, 1.634281, 2.513676",\ + "1.246642, 1.514428, 1.776008, 2.215705, 3.095100",\ + "0.515577, 0.782734, 1.044880, 1.484165, 2.362736",\ + "0.537406, 0.804562, 1.066708, 1.505994, 2.384564",\ + "0.587546, 0.854703, 1.116849, 1.556134, 2.434705",\ + "0.753923, 1.021079, 1.283225, 1.722511, 2.601081",\ + "1.335346, 1.602503, 1.864649, 2.303934, 3.182505",\ + "0.608520, 0.875879, 1.136606, 1.576329, 2.455778",\ + "0.630348, 0.897707, 1.158434, 1.598158, 2.477606",\ + "0.680488, 0.947848, 1.208574, 1.648298, 2.527747",\ + "0.846865, 1.114224, 1.374951, 1.814675, 2.694123",\ + "1.428288, 1.695648, 1.956374, 2.396098, 3.275547",\ + "0.674363, 0.944443, 1.203625, 1.643180, 2.522289",\ + "0.696192, 0.966272, 1.225454, 1.665008, 2.544117",\ + "0.746332, 1.016412, 1.275594, 1.715149, 2.594258",\ + "0.912709, 1.182789, 1.441971, 1.881525, 2.760634",\ + "1.494132, 1.764212, 2.023394, 2.462949, 3.342058",\ + "1.020885, 1.325279, 1.574288, 2.012334, 2.888425",\ + "1.042713, 1.347107, 1.596116, 2.034162, 2.910253",\ + "1.092854, 1.397248, 1.646257, 2.084302, 2.960393",\ + "1.259230, 1.563624, 1.812633, 2.250679, 3.126770",\ + "1.840654, 2.145048, 2.394057, 2.832103, 3.708194"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2689*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.478652, 0.742226, 1.018498, 1.487228, 2.424687",\ + "0.507052, 0.770625, 1.046898, 1.515627, 2.453087",\ + "0.578584, 0.842158, 1.118431, 1.587160, 2.524619",\ + "0.835020, 1.098594, 1.374866, 1.843596, 2.781055",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.566846, 0.829767, 1.106066, 1.573943, 2.510621",\ + "0.595246, 0.858166, 1.134465, 1.602343, 2.539020",\ + "0.666779, 0.929699, 1.205998, 1.673875, 2.610553",\ + "0.923215, 1.186135, 1.462434, 1.930311, 2.866989",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.655163, 0.918747, 1.194031, 1.661566, 2.597576",\ + "0.683562, 0.947146, 1.222430, 1.689965, 2.625975",\ + "0.755095, 1.018679, 1.293963, 1.761498, 2.697508",\ + "1.011531, 1.275115, 1.550399, 2.017934, 2.953944",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.717659, 0.984382, 1.258171, 1.725480, 2.661085",\ + "0.746058, 1.012781, 1.286570, 1.753879, 2.689484",\ + "0.817591, 1.084314, 1.358103, 1.825412, 2.761017",\ + "1.074027, 1.340750, 1.614539, 2.081847, 3.017453",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.046784, 1.348713, 1.610038, 2.074829, 3.006541",\ + "1.075184, 1.377112, 1.638437, 2.103229, 3.034940",\ + "1.146717, 1.448645, 1.709970, 2.174761, 3.106473",\ + "1.403152, 1.705081, 1.966406, 2.431197, 3.362909",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732054, 0.732051",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.409826, 0.592258, 0.788650, 1.097704, 1.692512",\ + "0.431655, 0.614087, 0.810479, 1.119532, 1.714340",\ + "0.481795, 0.664227, 0.860619, 1.169672, 1.764480",\ + "0.648172, 0.830604, 1.026996, 1.336049, 1.930856",\ + "1.229595, 1.412027, 1.608419, 1.917472, 2.512278",\ + "0.497241, 0.679644, 0.876143, 1.185009, 1.779865",\ + "0.519070, 0.701472, 0.897972, 1.206837, 1.801694",\ + "0.569210, 0.751613, 0.948112, 1.256977, 1.851834",\ + "0.735586, 0.917989, 1.114489, 1.423354, 2.018209",\ + "1.317010, 1.499413, 1.695912, 2.004777, 2.599632",\ + "0.578118, 0.759980, 0.956170, 1.265037, 1.859897",\ + "0.599946, 0.781809, 0.977999, 1.286866, 1.881726",\ + "0.650086, 0.831949, 1.028139, 1.337006, 1.931865",\ + "0.816463, 0.998326, 1.194516, 1.503382, 2.098241",\ + "1.397886, 1.579749, 1.775939, 2.084805, 2.679663",\ + "0.635764, 0.817529, 1.013714, 1.322282, 1.916544",\ + "0.657592, 0.839357, 1.035542, 1.344111, 1.938373",\ + "0.707733, 0.889498, 1.085683, 1.394251, 1.988513",\ + "0.874109, 1.055874, 1.252059, 1.560627, 2.154888",\ + "1.455533, 1.637298, 1.833483, 2.142051, 2.736311",\ + "0.937972, 1.122753, 1.317348, 1.625297, 2.218391",\ + "0.959800, 1.144582, 1.339176, 1.647125, 2.240220",\ + "1.009940, 1.194722, 1.389317, 1.697266, 2.290360",\ + "1.176317, 1.361099, 1.555693, 1.863642, 2.456735",\ + "1.757740, 1.942522, 2.137117, 2.445065, 3.038157"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082235, 0.082233",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2623*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.474677, 0.734306, 1.006178, 1.463058, 2.376818",\ + "0.503076, 0.762705, 1.034578, 1.491457, 2.405217",\ + "0.574609, 0.834238, 1.106111, 1.562990, 2.476750",\ + "0.831045, 1.090674, 1.362546, 1.819426, 2.733185",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.562782, 0.821840, 1.093709, 1.549773, 2.462751",\ + "0.591181, 0.850239, 1.122108, 1.578173, 2.491151",\ + "0.662714, 0.921772, 1.193641, 1.649706, 2.562684",\ + "0.919150, 1.178208, 1.450077, 1.906141, 2.819119",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.650812, 0.910805, 1.181673, 1.637396, 2.549706",\ + "0.679211, 0.939205, 1.210072, 1.665795, 2.578106",\ + "0.750744, 1.010738, 1.281605, 1.737328, 2.649639",\ + "1.007180, 1.267174, 1.538041, 1.993764, 2.906074",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.713033, 0.976419, 1.245811, 1.701310, 2.613215",\ + "0.741432, 1.004818, 1.274210, 1.729709, 2.641615",\ + "0.812965, 1.076351, 1.345743, 1.801242, 2.713148",\ + "1.069401, 1.332787, 1.602179, 2.057678, 2.969583",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.040421, 1.340494, 1.597558, 2.050611, 2.958672",\ + "1.068820, 1.368893, 1.625957, 2.079010, 2.987071",\ + "1.140353, 1.440426, 1.697490, 2.150543, 3.058604",\ + "1.396789, 1.696862, 1.953926, 2.406978, 3.315039",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239906, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108035",\ + "0.239906, 0.239905, 0.239905, 0.239905, 0.239905",\ + "0.732057, 0.732057, 0.732056, 0.732053, 0.732046",\ + "2.463890, 2.463889, 2.463888, 2.463885, 2.463879"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.408165, 0.590706, 0.786961, 1.096178, 1.691475",\ + "0.429993, 0.612534, 0.808789, 1.118006, 1.713303",\ + "0.480134, 0.662675, 0.858930, 1.168147, 1.763443",\ + "0.646510, 0.829051, 1.025306, 1.334523, 1.929818",\ + "1.227934, 1.410475, 1.606730, 1.915946, 2.511241",\ + "0.495585, 0.678091, 0.874454, 1.183483, 1.778828",\ + "0.517413, 0.699920, 0.896282, 1.205312, 1.800657",\ + "0.567554, 0.750060, 0.946422, 1.255452, 1.850797",\ + "0.733930, 0.916437, 1.112799, 1.421828, 2.017172",\ + "1.315354, 1.497860, 1.694222, 2.003251, 2.598594",\ + "0.576453, 0.758428, 0.954480, 1.263512, 1.858860",\ + "0.598281, 0.780257, 0.976309, 1.285340, 1.880688",\ + "0.648421, 0.830397, 1.026449, 1.335480, 1.930828",\ + "0.814798, 0.996773, 1.192826, 1.501856, 2.097203",\ + "1.396221, 1.578197, 1.774249, 2.083280, 2.678626",\ + "0.634091, 0.815977, 1.012024, 1.320757, 1.915507",\ + "0.655920, 0.837805, 1.033853, 1.342585, 1.937336",\ + "0.706060, 0.887945, 1.083993, 1.392725, 1.987476",\ + "0.872437, 1.054322, 1.250370, 1.559102, 2.153851",\ + "1.453860, 1.635746, 1.831793, 2.140525, 2.735273",\ + "0.936187, 1.121203, 1.315658, 1.623772, 2.217354",\ + "0.958015, 1.143031, 1.337487, 1.645600, 2.239183",\ + "1.008155, 1.193172, 1.387627, 1.695740, 2.289323",\ + "1.174532, 1.359548, 1.554004, 1.862116, 2.455698",\ + "1.755955, 1.940972, 2.135427, 2.443540, 3.037120"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142",\ + "0.053502, 0.053502, 0.053502, 0.053501, 0.053499",\ + "0.082236, 0.082236, 0.082235, 0.082234, 0.082232",\ + "0.159095, 0.159095, 0.159095, 0.159095, 0.159095",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523142"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2570*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.566961, 0.745387, 0.925648, 1.211854, 1.762971",\ + "0.595360, 0.773787, 0.954047, 1.240253, 1.791370",\ + "0.666893, 0.845320, 1.025580, 1.311786, 1.862903",\ + "0.923329, 1.101756, 1.282016, 1.568222, 2.119339",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.651899, 0.830660, 1.011563, 1.297774, 1.849349",\ + "0.680298, 0.859059, 1.039962, 1.326174, 1.877749",\ + "0.751831, 0.930592, 1.111495, 1.397707, 1.949282",\ + "1.008267, 1.187028, 1.367931, 1.654143, 2.205718",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.727805, 0.906103, 1.086372, 1.372371, 1.923522",\ + "0.756204, 0.934502, 1.114771, 1.400770, 1.951921",\ + "0.827737, 1.006035, 1.186304, 1.472303, 2.023454",\ + "1.084173, 1.262471, 1.442740, 1.728739, 2.279890",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.782157, 0.960615, 1.141023, 1.426911, 1.977839",\ + "0.810557, 0.989014, 1.169422, 1.455310, 2.006238",\ + "0.882089, 1.060547, 1.240955, 1.526843, 2.077771",\ + "1.138525, 1.316983, 1.497391, 1.783279, 2.334207",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.063579, 1.245842, 1.424973, 1.710637, 2.261117",\ + "1.091979, 1.274241, 1.453373, 1.739037, 2.289516",\ + "1.163512, 1.345774, 1.524906, 1.810570, 2.361049",\ + "1.419947, 1.602210, 1.781342, 2.067005, 2.617485",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.059998, 0.059998, 0.059998, 0.059998, 0.059998",\ + "0.108036, 0.108036, 0.108036, 0.108036, 0.108036",\ + "0.239906, 0.239906, 0.239906, 0.239906, 0.239906",\ + "0.732057, 0.732057, 0.732057, 0.732057, 0.732057",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.425437, 0.690607, 0.949809, 1.385991, 2.258357",\ + "0.447266, 0.712435, 0.971637, 1.407820, 2.280185",\ + "0.497406, 0.762576, 1.021778, 1.457960, 2.330325",\ + "0.663783, 0.928952, 1.188154, 1.624336, 2.496702",\ + "1.245206, 1.510376, 1.769578, 2.205760, 3.078125",\ + "0.514103, 0.778682, 1.038450, 1.474220, 2.345762",\ + "0.535931, 0.800510, 1.060278, 1.496048, 2.367590",\ + "0.586072, 0.850651, 1.110419, 1.546189, 2.417730",\ + "0.752448, 1.017027, 1.276795, 1.712565, 2.584107",\ + "1.333872, 1.598451, 1.858219, 2.293989, 3.165530",\ + "0.606910, 0.871805, 1.130175, 1.566384, 2.438803",\ + "0.628738, 0.893633, 1.152003, 1.588213, 2.460632",\ + "0.678878, 0.943774, 1.202144, 1.638353, 2.510772",\ + "0.845255, 1.110150, 1.368520, 1.804730, 2.677149",\ + "1.426679, 1.691574, 1.949944, 2.386153, 3.258572",\ + "0.672632, 0.940339, 1.197195, 1.633235, 2.505315",\ + "0.694461, 0.962168, 1.219023, 1.655063, 2.527143",\ + "0.744601, 1.012308, 1.269164, 1.705203, 2.577283",\ + "0.910977, 1.178684, 1.435540, 1.871580, 2.743660",\ + "1.492401, 1.760108, 2.016964, 2.453003, 3.325083",\ + "1.018422, 1.320838, 1.567825, 2.002366, 2.871448",\ + "1.040250, 1.342666, 1.589653, 2.024194, 2.893276",\ + "1.090390, 1.392806, 1.639794, 2.074335, 2.943416",\ + "1.256767, 1.559183, 1.806170, 2.240711, 3.109793",\ + "1.838190, 2.140606, 2.387594, 2.822135, 3.691216"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144",\ + "0.053502, 0.053502, 0.053502, 0.053502, 0.053502",\ + "0.082236, 0.082236, 0.082236, 0.082236, 0.082235",\ + "0.159094, 0.159094, 0.159094, 0.159094, 0.159094",\ + "0.457392, 0.457392, 0.457392, 0.457392, 0.457392",\ + "1.523144, 1.523144, 1.523144, 1.523144, 1.523144"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_2508*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.334234, 0.362633, 0.434167, 0.690603, 1.594576",\ + "0.421625, 0.450024, 0.521558, 0.777994, 1.681967",\ + "0.502544, 0.530943, 0.602477, 0.858913, 1.762885",\ + "0.560284, 0.588684, 0.660217, 0.916654, 1.820624",\ + "0.862990, 0.891389, 0.962923, 1.219360, 2.123326"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.059999, 0.108036, 0.239907, 0.732038, 2.463871",\ + "0.059999, 0.108053, 0.240000, 0.732038, 2.463871",\ + "0.059999, 0.108094, 0.240218, 0.732038, 2.463871",\ + "0.059999, 0.108094, 0.240218, 0.732038, 2.463871",\ + "0.060087, 0.108094, 0.240545, 0.732051, 2.463884"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.305321, 0.327149, 0.377290, 0.543666, 1.125090",\ + "0.392714, 0.414542, 0.464682, 0.631059, 1.212482",\ + "0.473583, 0.495412, 0.545552, 0.711928, 1.293352",\ + "0.531232, 0.553060, 0.603201, 0.769577, 1.351001",\ + "0.834460, 0.856477, 0.906940, 1.073696, 1.654812"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.053502, 0.082236, 0.159102, 0.457392, 1.523894",\ + "0.053502, 0.082236, 0.159102, 0.457392, 1.523894",\ + "0.053502, 0.082236, 0.159102, 0.457392, 1.523767",\ + "0.053502, 0.082236, 0.159102, 0.457392, 1.523532",\ + "0.053458, 0.082179, 0.159102, 0.457388, 1.523144"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.517252, 0.697365, 0.884944, 1.186924, 1.770020",\ + "0.545074, 0.725188, 0.912766, 1.214746, 1.797842",\ + "0.616076, 0.796190, 0.983769, 1.285748, 1.868845",\ + "0.871803, 1.051917, 1.239495, 1.541475, 2.124571",\ + "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\ + "0.602190, 0.782201, 0.970014, 1.272430, 1.856398",\ + "0.630012, 0.810023, 0.997836, 1.300252, 1.884220",\ + "0.701015, 0.881026, 1.068839, 1.371255, 1.955223",\ + "0.956741, 1.136753, 1.324565, 1.626981, 2.210949",\ + "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\ + "0.678102, 0.857644, 1.044823, 1.347027, 1.930570",\ + "0.705924, 0.885467, 1.072645, 1.374849, 1.958393",\ + "0.776927, 0.956469, 1.143648, 1.445851, 2.029395",\ + "1.032653, 1.212196, 1.399374, 1.701578, 2.285122",\ + "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\ + "0.732471, 0.912396, 1.099712, 1.401632, 1.984888",\ + "0.760294, 0.940218, 1.127534, 1.429455, 2.012710",\ + "0.831296, 1.011221, 1.198536, 1.500457, 2.083713",\ + "1.087023, 1.266947, 1.454263, 1.756184, 2.339439",\ + "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\ + "1.014066, 1.197961, 1.383887, 1.685358, 2.268165",\ + "1.041888, 1.225783, 1.411709, 1.713181, 2.295988",\ + "1.112891, 1.296786, 1.482712, 1.784183, 2.366990",\ + "1.368618, 1.552512, 1.738438, 2.039910, 2.622717",\ + "2.270849, 2.454743, 2.640669, 2.942141, 3.524948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.397272, 0.664882, 0.926275, 1.366020, 2.245119",\ + "0.417207, 0.684818, 0.946210, 1.385955, 2.265054",\ + "0.464850, 0.732461, 0.993853, 1.433599, 2.312697",\ + "0.630183, 0.897793, 1.159185, 1.598931, 2.478030",\ + "1.214286, 1.481897, 1.743298, 2.183075, 3.062236",\ + "0.485976, 0.752957, 1.014915, 1.454249, 2.332524",\ + "0.505911, 0.772893, 1.034851, 1.474185, 2.352459",\ + "0.553554, 0.820536, 1.082494, 1.521828, 2.400102",\ + "0.718887, 0.985868, 1.247826, 1.687160, 2.565435",\ + "1.302990, 1.569972, 1.831939, 2.271304, 3.149641",\ + "0.578918, 0.846278, 1.106960, 1.546495, 2.425566",\ + "0.598853, 0.866213, 1.126895, 1.566430, 2.445501",\ + "0.646497, 0.913856, 1.174538, 1.614074, 2.493144",\ + "0.811829, 1.079188, 1.339871, 1.779406, 2.658477",\ + "1.395933, 1.663292, 1.923983, 2.363550, 3.242683",\ + "0.644762, 0.914842, 1.174016, 1.613506, 2.492487",\ + "0.664697, 0.934777, 1.193951, 1.633442, 2.512423",\ + "0.712340, 0.982420, 1.241595, 1.681085, 2.560066",\ + "0.877673, 1.147753, 1.406927, 1.846417, 2.725398",\ + "1.461776, 1.731856, 1.991039, 2.430561, 3.309604",\ + "0.991283, 1.295677, 1.544687, 1.982732, 2.858823",\ + "1.011218, 1.315613, 1.564622, 2.002667, 2.878758",\ + "1.058862, 1.363256, 1.612265, 2.050310, 2.926401",\ + "1.224194, 1.528588, 1.777597, 2.215642, 3.091733",\ + "1.808298, 2.112692, 2.361710, 2.799787, 3.675940"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2444*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.425360, 0.688891, 0.965011, 1.433143, 2.368146",\ + "0.453182, 0.716714, 0.992833, 1.460965, 2.395969",\ + "0.524185, 0.787716, 1.063836, 1.531968, 2.466971",\ + "0.779912, 1.043443, 1.319562, 1.787694, 2.722698",\ + "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\ + "0.513554, 0.776432, 1.052578, 1.519858, 2.454080",\ + "0.541377, 0.804254, 1.080400, 1.547680, 2.481903",\ + "0.612379, 0.875257, 1.151402, 1.618683, 2.552905",\ + "0.868106, 1.130983, 1.407129, 1.874409, 2.808632",\ + "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\ + "0.601870, 0.865411, 1.140543, 1.607498, 2.541035",\ + "0.629693, 0.893234, 1.168365, 1.635320, 2.568858",\ + "0.700695, 0.964236, 1.239367, 1.706323, 2.639860",\ + "0.956422, 1.219963, 1.495094, 1.962050, 2.895587",\ + "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\ + "0.664366, 0.931045, 1.204682, 1.671587, 2.604544",\ + "0.692189, 0.958867, 1.232504, 1.699409, 2.632367",\ + "0.763191, 1.029870, 1.303507, 1.770412, 2.703369",\ + "1.018918, 1.285596, 1.559234, 2.026138, 2.959096",\ + "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\ + "0.993492, 1.295360, 1.556546, 2.021031, 2.950000",\ + "1.021315, 1.323182, 1.584368, 2.048853, 2.977823",\ + "1.092317, 1.394185, 1.655371, 2.119856, 3.048825",\ + "1.348044, 1.649911, 1.911098, 2.375582, 3.304552",\ + "2.250275, 2.552142, 2.813329, 3.277813, 4.206782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057229",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727954",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.380225, 0.562282, 0.758415, 1.067547, 1.662000",\ + "0.400160, 0.582218, 0.778351, 1.087482, 1.681936",\ + "0.447803, 0.629861, 0.825994, 1.135126, 1.729579",\ + "0.613136, 0.795193, 0.991326, 1.300459, 1.894914",\ + "1.197241, 1.379299, 1.575532, 1.884713, 2.479196",\ + "0.467640, 0.649601, 0.845696, 1.154852, 1.749354",\ + "0.487575, 0.669536, 0.865631, 1.174787, 1.769289",\ + "0.535218, 0.717180, 0.913275, 1.222431, 1.816933",\ + "0.700550, 0.882512, 1.078607, 1.387764, 1.982267",\ + "1.284656, 1.466618, 1.662813, 1.972018, 2.566549",\ + "0.548516, 0.729938, 0.925723, 1.234881, 1.829386",\ + "0.568451, 0.749873, 0.945658, 1.254816, 1.849321",\ + "0.616094, 0.797516, 0.993302, 1.302459, 1.896965",\ + "0.781427, 0.962848, 1.158634, 1.467792, 2.062299",\ + "1.365532, 1.546954, 1.742840, 2.052047, 2.646581",\ + "0.606162, 0.787775, 0.983459, 1.292351, 1.886481",\ + "0.626098, 0.807710, 1.003394, 1.312286, 1.906416",\ + "0.673741, 0.855353, 1.051037, 1.359930, 1.954060",\ + "0.839073, 1.020685, 1.216369, 1.525263, 2.119395",\ + "1.423179, 1.604791, 1.800576, 2.109517, 2.703676",\ + "0.908370, 1.093152, 1.287122, 1.595558, 2.188799",\ + "0.928305, 1.113087, 1.307057, 1.615493, 2.208735",\ + "0.975949, 1.160730, 1.354700, 1.663137, 2.256378",\ + "1.141281, 1.326062, 1.520033, 1.828470, 2.421713",\ + "1.725386, 1.910168, 2.104239, 2.412724, 3.005995"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452943",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2368*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.421382, 0.680941, 0.952576, 1.408738, 2.319905",\ + "0.449204, 0.708764, 0.980399, 1.436560, 2.347728",\ + "0.520207, 0.779766, 1.051401, 1.507563, 2.418730",\ + "0.775933, 1.035493, 1.307128, 1.763289, 2.674457",\ + "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\ + "0.509487, 0.768474, 1.040105, 1.495453, 2.405839",\ + "0.537309, 0.796296, 1.067928, 1.523275, 2.433661",\ + "0.608312, 0.867299, 1.138930, 1.594278, 2.504664",\ + "0.864038, 1.123026, 1.394657, 1.850005, 2.760391",\ + "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\ + "0.597517, 0.857438, 1.128069, 1.583092, 2.492794",\ + "0.625339, 0.885261, 1.155892, 1.610914, 2.520617",\ + "0.696342, 0.956263, 1.226894, 1.681917, 2.591619",\ + "0.952068, 1.211990, 1.482621, 1.937644, 2.847346",\ + "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\ + "0.659738, 0.923050, 1.192207, 1.647166, 2.556303",\ + "0.687560, 0.950872, 1.220030, 1.674989, 2.584126",\ + "0.758563, 1.021875, 1.291032, 1.745991, 2.655128",\ + "1.014290, 1.277601, 1.546759, 2.001718, 2.910855",\ + "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\ + "0.987126, 1.287098, 1.543950, 1.996553, 2.901759",\ + "1.014948, 1.314920, 1.571772, 2.024375, 2.929582",\ + "1.085950, 1.385923, 1.642775, 2.095378, 3.000584",\ + "1.341677, 1.641650, 1.898501, 2.351104, 3.256311",\ + "2.243908, 2.543881, 2.800732, 3.253335, 4.158542"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.057228, 0.057228, 0.057228, 0.057229, 0.057230",\ + "0.105834, 0.105834, 0.105834, 0.105835, 0.105835",\ + "0.238478, 0.238478, 0.238478, 0.238479, 0.238479",\ + "0.727955, 0.727955, 0.727955, 0.727954, 0.727953",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.378563, 0.560731, 0.756728, 1.066021, 1.660963",\ + "0.398499, 0.580666, 0.776663, 1.085956, 1.680898",\ + "0.446142, 0.628309, 0.824306, 1.133599, 1.728542",\ + "0.611474, 0.793641, 0.989638, 1.298932, 1.893877",\ + "1.195578, 1.377745, 1.573843, 1.883181, 2.478140",\ + "0.465983, 0.648049, 0.844008, 1.153326, 1.748316",\ + "0.485919, 0.667985, 0.863944, 1.173261, 1.768251",\ + "0.533562, 0.715628, 0.911587, 1.220904, 1.815895",\ + "0.698894, 0.880960, 1.076919, 1.386237, 1.981230",\ + "1.282998, 1.465064, 1.661124, 1.970486, 2.565494",\ + "0.546851, 0.728386, 0.924035, 1.233354, 1.828348",\ + "0.566786, 0.748322, 0.943970, 1.253289, 1.848283",\ + "0.614429, 0.795965, 0.991614, 1.300933, 1.895927",\ + "0.779762, 0.961297, 1.156946, 1.466266, 2.061262",\ + "1.363865, 1.545401, 1.741151, 2.050514, 2.645525",\ + "0.604490, 0.786223, 0.981770, 1.290825, 1.885444",\ + "0.624425, 0.806158, 1.001706, 1.310760, 1.905379",\ + "0.672068, 0.853802, 1.049349, 1.358404, 1.953023",\ + "0.837401, 1.019134, 1.214681, 1.523737, 2.118358",\ + "1.421504, 1.603237, 1.798886, 2.107985, 2.702621",\ + "0.906585, 1.091602, 1.285434, 1.594033, 2.187764",\ + "0.926520, 1.111537, 1.305369, 1.613968, 2.207699",\ + "0.974163, 1.159180, 1.353012, 1.661611, 2.255342",\ + "1.139496, 1.324512, 1.518345, 1.826944, 2.420678",\ + "1.723599, 1.908616, 2.102550, 2.411193, 3.004941"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044582",\ + "0.073511, 0.073511, 0.073511, 0.073512, 0.073513",\ + "0.152010, 0.152010, 0.152010, 0.152011, 0.152012",\ + "0.452924, 0.452924, 0.452925, 0.452931, 0.452944",\ + "1.518485, 1.518485, 1.518485, 1.518486, 1.518488"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2312*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.513665, 0.692005, 0.872351, 1.158538, 1.709291",\ + "0.541488, 0.719827, 0.900174, 1.186360, 1.737113",\ + "0.612490, 0.790830, 0.971176, 1.257363, 1.808116",\ + "0.868217, 1.046556, 1.226903, 1.513090, 2.063843",\ + "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\ + "0.598604, 0.776840, 0.957422, 1.244044, 1.795670",\ + "0.626426, 0.804663, 0.985244, 1.271867, 1.823492",\ + "0.697429, 0.875665, 1.056247, 1.342869, 1.894494",\ + "0.953155, 1.131392, 1.311973, 1.598596, 2.150221",\ + "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\ + "0.674510, 0.852284, 1.032230, 1.318641, 1.869842",\ + "0.702332, 0.880106, 1.060053, 1.346463, 1.897664",\ + "0.773335, 0.951109, 1.131055, 1.417466, 1.968667",\ + "1.029061, 1.206835, 1.386782, 1.673193, 2.224393",\ + "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\ + "0.728862, 0.907029, 1.087096, 1.373235, 1.924159",\ + "0.756684, 0.934852, 1.114918, 1.401057, 1.951982",\ + "0.827687, 1.005854, 1.185921, 1.472059, 2.022984",\ + "1.083413, 1.261581, 1.441647, 1.727786, 2.278711",\ + "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\ + "1.010284, 1.192547, 1.371249, 1.656961, 2.207437",\ + "1.038106, 1.220369, 1.399071, 1.684783, 2.235259",\ + "1.109109, 1.291372, 1.470074, 1.755786, 2.306262",\ + "1.364835, 1.547098, 1.725800, 2.011513, 2.561988",\ + "2.267066, 2.449329, 2.628031, 2.913743, 3.464219"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.057228, 0.057228, 0.057228, 0.057228, 0.057228",\ + "0.105834, 0.105834, 0.105834, 0.105834, 0.105834",\ + "0.238478, 0.238478, 0.238478, 0.238478, 0.238478",\ + "0.727955, 0.727955, 0.727955, 0.727955, 0.727955",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.395836, 0.660835, 0.919855, 1.356084, 2.228162",\ + "0.415771, 0.680770, 0.939790, 1.376020, 2.248097",\ + "0.463414, 0.728413, 0.987433, 1.423663, 2.295740",\ + "0.628747, 0.893746, 1.152766, 1.588995, 2.461072",\ + "1.212850, 1.477849, 1.736879, 2.173143, 3.045290",\ + "0.484501, 0.748910, 1.008496, 1.444313, 2.315567",\ + "0.504437, 0.768845, 1.028431, 1.464249, 2.335502",\ + "0.552080, 0.816488, 1.076074, 1.511892, 2.383145",\ + "0.717412, 0.981821, 1.241406, 1.677224, 2.548478",\ + "1.301516, 1.565924, 1.825520, 2.261372, 3.132695",\ + "0.577308, 0.842203, 1.100531, 1.536557, 2.408609",\ + "0.597243, 0.862139, 1.120466, 1.556492, 2.428544",\ + "0.644887, 0.909782, 1.168109, 1.604135, 2.476187",\ + "0.810219, 1.075114, 1.333442, 1.769467, 2.641520",\ + "1.394323, 1.659218, 1.917555, 2.353615, 3.225737",\ + "0.643031, 0.910738, 1.167586, 1.603563, 2.475518",\ + "0.662966, 0.930673, 1.187521, 1.623498, 2.495454",\ + "0.710609, 0.978316, 1.235164, 1.671142, 2.543097",\ + "0.875941, 1.143648, 1.400497, 1.836474, 2.708429",\ + "1.460045, 1.727752, 1.984610, 2.420622, 3.292646",\ + "0.988820, 1.291236, 1.538224, 1.972764, 2.841846",\ + "1.008755, 1.311171, 1.558159, 1.992699, 2.861781",\ + "1.056399, 1.358814, 1.605802, 2.040343, 2.909424",\ + "1.221731, 1.524147, 1.771134, 2.205675, 3.074756",\ + "1.805834, 2.108251, 2.355248, 2.789823, 3.658973"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485",\ + "0.044581, 0.044581, 0.044581, 0.044581, 0.044581",\ + "0.073511, 0.073511, 0.073511, 0.073511, 0.073511",\ + "0.152010, 0.152010, 0.152010, 0.152010, 0.152010",\ + "0.452924, 0.452924, 0.452924, 0.452925, 0.452925",\ + "1.518485, 1.518485, 1.518485, 1.518485, 1.518485"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min_2754*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.151345, 0.179420, 0.250838, 0.507101, 1.411098",\ + "0.239529, 0.267606, 0.339037, 0.595340, 1.499024",\ + "0.327854, 0.355929, 0.427371, 0.683856, 1.587106",\ + "0.390452, 0.418510, 0.489921, 0.746692, 1.650402",\ + "0.720352, 0.748358, 0.819633, 1.076844, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\ + "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\ + "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\ + "0.057228, 0.105834, 0.238478, 0.727955, 2.448223",\ + "0.057228, 0.105834, 0.238478, 0.727955, 2.448223"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.187745, 0.208337, 0.256868, 0.422532, 1.003731",\ + "0.275148, 0.295740, 0.344271, 0.509935, 1.091134",\ + "0.356045, 0.376636, 0.425171, 0.590840, 1.172047",\ + "0.413704, 0.434296, 0.482838, 0.648514, 1.229738",\ + "0.716053, 0.736646, 0.785216, 0.950960, 1.532355"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.044579, 0.073509, 0.152008, 0.452080, 1.516200",\ + "0.044579, 0.073509, 0.152008, 0.452080, 1.516200",\ + "0.044579, 0.073509, 0.152008, 0.452124, 1.516200",\ + "0.044579, 0.073509, 0.152008, 0.452204, 1.516200",\ + "0.044579, 0.073509, 0.152008, 0.452924, 1.516200"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.146298, 0.146298, 0.146298, 0.146298, 0.146298",\ + "0.171440, 0.171440, 0.171440, 0.171440, 0.171440",\ + "0.241225, 0.241225, 0.241225, 0.241225, 0.241225",\ + "0.364369, 0.364369, 0.364369, 0.364369, 0.364369",\ + "0.930611, 0.930611, 0.930611, 0.930611, 0.930611"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.419370, 0.419370, 0.419370, 0.419370, 0.419370",\ + "0.439927, 0.439927, 0.439927, 0.439927, 0.439927",\ + "0.498432, 0.498432, 0.498432, 0.498432, 0.498432",\ + "0.607706, 0.607706, 0.607706, 0.607706, 0.607706",\ + "1.345296, 1.345296, 1.345296, 1.345296, 1.345296"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_cgsf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.138551, -0.138551, -0.138551, -0.138551, -0.138551",\ + "-0.162150, -0.162150, -0.162150, -0.162150, -0.162150",\ + "-0.233628, -0.233628, -0.233628, -0.233628, -0.233628",\ + "-0.357370, -0.357370, -0.357370, -0.357370, -0.357370",\ + "-0.923132, -0.923132, -0.923132, -0.923132, -0.923132"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.415516, -0.415516, -0.415516, -0.415516, -0.415516",\ + "-0.432323, -0.432323, -0.432323, -0.432323, -0.432323",\ + "-0.494548, -0.494548, -0.494548, -0.494548, -0.494548",\ + "-0.603812, -0.603812, -0.603812, -0.603812, -0.603812",\ + "-1.339799, -1.339799, -1.339799, -1.339799, -1.339799"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[10]_cghr*/ + + timing () { + related_pin : "padmux2ast_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.098861, 0.127061, 0.198218, 0.454154, 1.359203",\ + "0.186535, 0.214722, 0.285779, 0.541885, 1.444562",\ + "0.285062, 0.314115, 0.385746, 0.641617, 1.547694",\ + "0.464742, 0.495967, 0.569252, 0.824864, 1.732299",\ + "0.773180, 0.811674, 0.892653, 1.148190, 2.048527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.058877, 0.106972, 0.239632, 0.734291, 2.481454",\ + "0.059452, 0.107162, 0.239653, 0.735798, 2.481454",\ + "0.065492, 0.111214, 0.239653, 0.735798, 2.481454",\ + "0.080964, 0.122543, 0.243345, 0.735798, 2.481454",\ + "0.122739, 0.156713, 0.261409, 0.735798, 2.481454"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.135906, 0.157942, 0.208401, 0.375177, 0.957248",\ + "0.214952, 0.236957, 0.287364, 0.454102, 1.034980",\ + "0.319131, 0.342208, 0.393489, 0.560142, 1.142872",\ + "0.499405, 0.526607, 0.582603, 0.750679, 1.332501",\ + "0.794222, 0.832488, 0.901924, 1.075291, 1.655125"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.053775, 0.082436, 0.159158, 0.457799, 1.524944",\ + "0.053775, 0.082436, 0.159158, 0.457799, 1.524944",\ + "0.061142, 0.087763, 0.161724, 0.457799, 1.524944",\ + "0.087222, 0.109690, 0.175261, 0.460373, 1.524944",\ + "0.145864, 0.166027, 0.220323, 0.470910, 1.526598"); + } + + } /* end of arc padmux2ast_i[2]_obs_ctrl_o[10]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.094010, 0.121742, 0.192687, 0.448829, 1.352120",\ + "0.181367, 0.209191, 0.280055, 0.536519, 1.439207",\ + "0.278263, 0.306648, 0.378094, 0.633788, 1.536303",\ + "0.454444, 0.484657, 0.556595, 0.813226, 1.718362",\ + "0.755309, 0.792056, 0.870822, 1.124333, 2.025527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.056753, 0.105860, 0.238203, 0.725444, 2.440521",\ + "0.057457, 0.106111, 0.238203, 0.725444, 2.440521",\ + "0.062809, 0.109450, 0.238891, 0.728499, 2.449750",\ + "0.076809, 0.119663, 0.242773, 0.728499, 2.460771",\ + "0.116537, 0.152614, 0.258265, 0.732313, 2.462313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.100529, 0.120692, 0.168644, 0.334136, 0.916833",\ + "0.185614, 0.205791, 0.253754, 0.419069, 1.001005",\ + "0.286304, 0.308070, 0.357380, 0.522540, 1.104903",\ + "0.458699, 0.485107, 0.539262, 0.704482, 1.285416",\ + "0.740887, 0.778992, 0.848123, 1.019973, 1.597477"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.002440, 0.005679, 0.014260, 0.045576, 0.156168"); + values ( "0.045486, 0.074449, 0.152541, 0.452549, 1.519412",\ + "0.046012, 0.074648, 0.152769, 0.453825, 1.520024",\ + "0.056013, 0.082252, 0.156413, 0.454416, 1.520024",\ + "0.082035, 0.104246, 0.169572, 0.457496, 1.520040",\ + "0.139812, 0.159966, 0.214496, 0.467116, 1.522752"); + } + + } /* end of arc padmux2ast_i[2]_obs_ctrl_o[10]_una_min*/ + +} /* end of pin obs_ctrl_o[10] */ + +pin("obs_ctrl_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001432 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.560564, 0.740767, 0.928257, 1.230250, 1.813761",\ + "0.590490, 0.770693, 0.958183, 1.260175, 1.843687",\ + "0.662228, 0.842431, 1.029921, 1.331913, 1.915425",\ + "0.918680, 1.098883, 1.286373, 1.588366, 2.171877",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.645502, 0.826050, 1.014266, 1.316262, 1.900140",\ + "0.675428, 0.855976, 1.044191, 1.346187, 1.930065",\ + "0.747166, 0.927714, 1.115929, 1.417926, 2.001803",\ + "1.003618, 1.184166, 1.372382, 1.674378, 2.258256",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.721415, 0.901494, 1.089075, 1.390859, 1.974312",\ + "0.751340, 0.931419, 1.119000, 1.420784, 2.004238",\ + "0.823078, 1.003157, 1.190738, 1.492522, 2.075976",\ + "1.079530, 1.259610, 1.447191, 1.748975, 2.332428",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.775784, 0.956005, 1.143726, 1.445398, 2.028629",\ + "0.805709, 0.985931, 1.173651, 1.475324, 2.058555",\ + "0.877448, 1.057669, 1.245389, 1.547062, 2.130293",\ + "1.133900, 1.314121, 1.501842, 1.803514, 2.386745",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.057379, 1.241273, 1.427676, 1.729125, 2.311907",\ + "1.087304, 1.271199, 1.457602, 1.759050, 2.341833",\ + "1.159042, 1.342937, 1.529340, 1.830788, 2.413571",\ + "1.415495, 1.599389, 1.785792, 2.087241, 2.670023",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.418380, 0.686166, 0.947746, 1.387443, 2.266838",\ + "0.442754, 0.710540, 0.972120, 1.411817, 2.291212",\ + "0.493609, 0.761395, 1.022975, 1.462672, 2.342067",\ + "0.660045, 0.927830, 1.189410, 1.629108, 2.508502",\ + "1.246765, 1.514551, 1.776131, 2.215828, 3.095223",\ + "0.507084, 0.774241, 1.036387, 1.475672, 2.354243",\ + "0.531458, 0.798615, 1.060761, 1.500046, 2.378617",\ + "0.582313, 0.849470, 1.111616, 1.550901, 2.429472",\ + "0.748749, 1.015905, 1.278051, 1.717337, 2.595908",\ + "1.335469, 1.602626, 1.864772, 2.304057, 3.182628",\ + "0.600027, 0.867386, 1.128112, 1.567836, 2.447285",\ + "0.624401, 0.891760, 1.152486, 1.592211, 2.471659",\ + "0.675255, 0.942615, 1.203341, 1.643065, 2.522514",\ + "0.841691, 1.109051, 1.369777, 1.809501, 2.688950",\ + "1.428411, 1.695771, 1.956497, 2.396221, 3.275670",\ + "0.665870, 0.935950, 1.195132, 1.634687, 2.513796",\ + "0.690244, 0.960324, 1.219506, 1.659061, 2.538170",\ + "0.741099, 1.011179, 1.270361, 1.709916, 2.589025",\ + "0.907535, 1.177615, 1.436797, 1.876351, 2.755461",\ + "1.494255, 1.764335, 2.023517, 2.463071, 3.342181",\ + "1.012392, 1.316786, 1.565795, 2.003840, 2.879932",\ + "1.036766, 1.341160, 1.590169, 2.028214, 2.904306",\ + "1.087620, 1.392015, 1.641024, 2.079069, 2.955161",\ + "1.254056, 1.558450, 1.807460, 2.245505, 3.121596",\ + "1.840776, 2.145171, 2.394180, 2.832225, 3.708317"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2714*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.468669, 0.732243, 1.008515, 1.477245, 2.414704",\ + "0.498595, 0.762168, 1.038441, 1.507171, 2.444630",\ + "0.570333, 0.833907, 1.110179, 1.578909, 2.516368",\ + "0.826785, 1.090359, 1.366631, 1.835361, 2.772820",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.556864, 0.819784, 1.096083, 1.563960, 2.500638",\ + "0.586789, 0.849709, 1.126009, 1.593886, 2.530564",\ + "0.658527, 0.921448, 1.197747, 1.665624, 2.602302",\ + "0.914980, 1.177900, 1.454199, 1.922076, 2.858753",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.645180, 0.908764, 1.184048, 1.651583, 2.587593",\ + "0.675105, 0.938690, 1.213974, 1.681509, 2.617519",\ + "0.746844, 1.010428, 1.285712, 1.753247, 2.689257",\ + "1.003296, 1.266880, 1.542164, 2.009699, 2.945708",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.707676, 0.974399, 1.248188, 1.715497, 2.651102",\ + "0.737601, 1.004325, 1.278113, 1.745422, 2.681028",\ + "0.809340, 1.076063, 1.349852, 1.817160, 2.752766",\ + "1.065792, 1.332515, 1.606304, 2.073612, 3.009217",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.036801, 1.338730, 1.600055, 2.064846, 2.996558",\ + "1.066727, 1.368655, 1.629981, 2.094772, 3.026484",\ + "1.138465, 1.440394, 1.701719, 2.166510, 3.098222",\ + "1.394917, 1.696846, 1.958171, 2.422962, 3.354673",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716280, 0.716278, 0.716274",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.401333, 0.583765, 0.780157, 1.089211, 1.684018",\ + "0.425707, 0.608139, 0.804531, 1.113585, 1.708393",\ + "0.476562, 0.658994, 0.855386, 1.164439, 1.759248",\ + "0.642998, 0.825430, 1.021822, 1.330875, 1.925682",\ + "1.229718, 1.412150, 1.608542, 1.917595, 2.512401",\ + "0.488748, 0.671151, 0.867650, 1.176516, 1.771372",\ + "0.513122, 0.695525, 0.892024, 1.200890, 1.795747",\ + "0.563977, 0.746379, 0.942879, 1.251745, 1.846601",\ + "0.730413, 0.912815, 1.109315, 1.418180, 2.013035",\ + "1.317133, 1.499535, 1.696035, 2.004900, 2.599754",\ + "0.569624, 0.751487, 0.947677, 1.256544, 1.851403",\ + "0.593999, 0.775861, 0.972051, 1.280918, 1.875778",\ + "0.644853, 0.826716, 1.022906, 1.331773, 1.926633",\ + "0.811289, 0.993152, 1.189342, 1.498208, 2.093067",\ + "1.398009, 1.579872, 1.776062, 2.084928, 2.679786",\ + "0.627271, 0.809036, 1.005221, 1.313789, 1.908051",\ + "0.651645, 0.833410, 1.029595, 1.338163, 1.932426",\ + "0.702500, 0.884265, 1.080450, 1.389018, 1.983280",\ + "0.868935, 1.050700, 1.246886, 1.555453, 2.149714",\ + "1.455656, 1.637420, 1.833606, 2.142173, 2.736434",\ + "0.929479, 1.114260, 1.308855, 1.616804, 2.209898",\ + "0.953853, 1.138634, 1.333229, 1.641178, 2.234272",\ + "1.004707, 1.189489, 1.384084, 1.692033, 2.285127",\ + "1.171143, 1.355925, 1.550519, 1.858468, 2.451561",\ + "1.757863, 1.942645, 2.137239, 2.445188, 3.038280"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523368"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2644*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.464694, 0.724323, 0.996195, 1.453075, 2.366835",\ + "0.494620, 0.754249, 1.026121, 1.483001, 2.396760",\ + "0.566358, 0.825987, 1.097859, 1.554739, 2.468498",\ + "0.822810, 1.082439, 1.354311, 1.811191, 2.724950",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.552799, 0.811857, 1.083726, 1.539791, 2.452769",\ + "0.582724, 0.841782, 1.113652, 1.569716, 2.482694",\ + "0.654463, 0.913521, 1.185390, 1.641454, 2.554432",\ + "0.910915, 1.169973, 1.441842, 1.897906, 2.810884",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.640829, 0.900823, 1.171690, 1.627413, 2.539724",\ + "0.670754, 0.930748, 1.201616, 1.657339, 2.569649",\ + "0.742493, 1.002486, 1.273354, 1.729077, 2.641387",\ + "0.998945, 1.258938, 1.529806, 1.985529, 2.897839",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.703050, 0.966436, 1.235828, 1.691327, 2.603233",\ + "0.732976, 0.996362, 1.265754, 1.721252, 2.633158",\ + "0.804714, 1.068100, 1.337492, 1.792991, 2.704896",\ + "1.061166, 1.324552, 1.593944, 2.049443, 2.961348",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.030438, 1.330511, 1.587575, 2.040628, 2.948689",\ + "1.060363, 1.360437, 1.617501, 2.070553, 2.978614",\ + "1.132102, 1.432175, 1.689239, 2.142292, 3.050352",\ + "1.388554, 1.688627, 1.945691, 2.398743, 3.306804",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046136",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224142, 0.224142, 0.224142, 0.224142",\ + "0.716281, 0.716280, 0.716279, 0.716276, 0.716270",\ + "2.463890, 2.463889, 2.463888, 2.463885, 2.463879"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.399672, 0.582213, 0.778468, 1.087685, 1.682981",\ + "0.424046, 0.606587, 0.802842, 1.112059, 1.707356",\ + "0.474901, 0.657442, 0.853696, 1.162914, 1.758210",\ + "0.641336, 0.823877, 1.020132, 1.329349, 1.924644",\ + "1.228057, 1.410598, 1.606853, 1.916069, 2.511364",\ + "0.487092, 0.669598, 0.865960, 1.174990, 1.770335",\ + "0.511466, 0.693972, 0.890334, 1.199364, 1.794710",\ + "0.562321, 0.744827, 0.941189, 1.250219, 1.845564",\ + "0.728756, 0.911263, 1.107625, 1.416654, 2.011998",\ + "1.315477, 1.497983, 1.694345, 2.003374, 2.598717",\ + "0.567959, 0.749935, 0.945987, 1.255018, 1.850366",\ + "0.592334, 0.774309, 0.970361, 1.279393, 1.874741",\ + "0.643188, 0.825164, 1.021216, 1.330247, 1.925596",\ + "0.809624, 0.991600, 1.187652, 1.496683, 2.092030",\ + "1.396344, 1.578320, 1.774372, 2.083403, 2.678749",\ + "0.625598, 0.807484, 1.003531, 1.312263, 1.907014",\ + "0.649972, 0.831858, 1.027905, 1.336638, 1.931389",\ + "0.700827, 0.882712, 1.078760, 1.387492, 1.982243",\ + "0.867263, 1.049148, 1.245196, 1.553928, 2.148677",\ + "1.453983, 1.635868, 1.831916, 2.140648, 2.735396",\ + "0.927693, 1.112710, 1.307165, 1.615278, 2.208861",\ + "0.952068, 1.137084, 1.331539, 1.639653, 2.233236",\ + "1.002922, 1.187939, 1.382394, 1.690507, 2.284090",\ + "1.169358, 1.354374, 1.548830, 1.856943, 2.450524",\ + "1.756078, 1.941095, 2.135550, 2.443663, 3.037243"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073620, 0.073619, 0.073617",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523367"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2587*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.556978, 0.735404, 0.915665, 1.201871, 1.752988",\ + "0.586903, 0.765330, 0.945590, 1.231797, 1.782914",\ + "0.658642, 0.837068, 1.017329, 1.303535, 1.854652",\ + "0.915094, 1.093521, 1.273781, 1.559987, 2.111104",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.641916, 0.820677, 1.001580, 1.287791, 1.839366",\ + "0.671842, 0.850602, 1.031505, 1.317717, 1.869292",\ + "0.743580, 0.922341, 1.103244, 1.389455, 1.941030",\ + "1.000032, 1.178793, 1.359696, 1.645907, 2.197482",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.717822, 0.896120, 1.076389, 1.362388, 1.913539",\ + "0.747748, 0.926046, 1.106314, 1.392314, 1.943465",\ + "0.819486, 0.997784, 1.178053, 1.464052, 2.015203",\ + "1.075938, 1.254236, 1.434505, 1.720504, 2.271655",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.772174, 0.950632, 1.131040, 1.416928, 1.967856",\ + "0.802100, 0.980558, 1.160965, 1.446854, 1.997782",\ + "0.873838, 1.052296, 1.232704, 1.518592, 2.069520",\ + "1.130290, 1.308748, 1.489156, 1.775044, 2.325972",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.053596, 1.235859, 1.414990, 1.700654, 2.251134",\ + "1.083522, 1.265785, 1.444916, 1.730580, 2.281059",\ + "1.155260, 1.337523, 1.516654, 1.802318, 2.352798",\ + "1.411712, 1.593975, 1.773107, 2.058770, 2.609250",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.046137, 0.046137, 0.046137, 0.046137, 0.046137",\ + "0.092740, 0.092740, 0.092740, 0.092740, 0.092740",\ + "0.224143, 0.224143, 0.224143, 0.224143, 0.224143",\ + "0.716280, 0.716280, 0.716280, 0.716280, 0.716280",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.416944, 0.682114, 0.941316, 1.377498, 2.249863",\ + "0.441318, 0.706488, 0.965690, 1.401872, 2.274237",\ + "0.492173, 0.757343, 1.016545, 1.452727, 2.325092",\ + "0.658609, 0.923779, 1.182980, 1.619163, 2.491528",\ + "1.245329, 1.510499, 1.769700, 2.205883, 3.078248",\ + "0.505610, 0.770189, 1.029957, 1.465727, 2.337268",\ + "0.529984, 0.794563, 1.054331, 1.490101, 2.361642",\ + "0.580839, 0.845418, 1.105186, 1.540956, 2.412497",\ + "0.747274, 1.011853, 1.271621, 1.707392, 2.578933",\ + "1.333995, 1.598574, 1.858341, 2.294112, 3.165653",\ + "0.598417, 0.863312, 1.121682, 1.557891, 2.430310",\ + "0.622791, 0.887686, 1.146056, 1.582265, 2.454684",\ + "0.673645, 0.938541, 1.196911, 1.633120, 2.505539",\ + "0.840081, 1.104976, 1.363346, 1.799556, 2.671975",\ + "1.426801, 1.691697, 1.950067, 2.386276, 3.258695",\ + "0.664139, 0.931846, 1.188702, 1.624742, 2.496821",\ + "0.688513, 0.956220, 1.213076, 1.649116, 2.521195",\ + "0.739368, 1.007075, 1.263931, 1.699970, 2.572050",\ + "0.905804, 1.173511, 1.430366, 1.866406, 2.738486",\ + "1.492524, 1.760231, 2.017087, 2.453126, 3.325206",\ + "1.009929, 1.312345, 1.559332, 1.993873, 2.862955",\ + "1.034303, 1.336719, 1.583706, 2.018247, 2.887329",\ + "1.085157, 1.387573, 1.634561, 2.069102, 2.938183",\ + "1.251593, 1.554009, 1.800997, 2.235537, 3.104619",\ + "1.838313, 2.140729, 2.387717, 2.822258, 3.691339"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370",\ + "0.044458, 0.044458, 0.044458, 0.044458, 0.044458",\ + "0.073621, 0.073621, 0.073621, 0.073621, 0.073620",\ + "0.149757, 0.149757, 0.149757, 0.149757, 0.149757",\ + "0.447950, 0.447950, 0.447950, 0.447950, 0.447950",\ + "1.523369, 1.523369, 1.523369, 1.523369, 1.523370"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_2527*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.324251, 0.354177, 0.425915, 0.682368, 1.594576",\ + "0.411642, 0.441568, 0.513306, 0.769759, 1.681967",\ + "0.492561, 0.522487, 0.594225, 0.850678, 1.762885",\ + "0.550301, 0.580227, 0.651966, 0.908419, 1.820624",\ + "0.853007, 0.882932, 0.954672, 1.211125, 2.123326"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.046138, 0.092741, 0.224144, 0.716261, 2.463871",\ + "0.046138, 0.092741, 0.224221, 0.716261, 2.463871",\ + "0.046138, 0.092741, 0.224454, 0.716261, 2.463871",\ + "0.046138, 0.092741, 0.224454, 0.716261, 2.463871",\ + "0.046298, 0.092766, 0.224788, 0.716274, 2.463884"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.296828, 0.321202, 0.372057, 0.538492, 1.125213",\ + "0.384221, 0.408595, 0.459449, 0.625885, 1.212605",\ + "0.465090, 0.489464, 0.540319, 0.706755, 1.293475",\ + "0.522739, 0.547113, 0.597968, 0.764403, 1.351124",\ + "0.825878, 0.850484, 0.901694, 1.068525, 1.654935"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.044458, 0.073621, 0.149762, 0.447950, 1.524119",\ + "0.044458, 0.073621, 0.149762, 0.447950, 1.524119",\ + "0.044458, 0.073621, 0.149762, 0.447950, 1.523993",\ + "0.044458, 0.073621, 0.149762, 0.447950, 1.523757",\ + "0.044456, 0.073554, 0.149762, 0.447945, 1.523369"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.507754, 0.687868, 0.875446, 1.177426, 1.760522",\ + "0.536697, 0.716810, 0.904389, 1.206369, 1.789465",\ + "0.607845, 0.787958, 0.975537, 1.277516, 1.860613",\ + "0.863570, 1.043684, 1.231262, 1.533242, 2.116338",\ + "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\ + "0.592692, 0.772703, 0.960516, 1.262932, 1.846900",\ + "0.621635, 0.801646, 0.989459, 1.291875, 1.875843",\ + "0.692783, 0.872794, 1.060607, 1.363023, 1.946991",\ + "0.948508, 1.128520, 1.316332, 1.618748, 2.202716",\ + "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\ + "0.668604, 0.848147, 1.035325, 1.337529, 1.921072",\ + "0.697547, 0.877090, 1.064268, 1.366472, 1.950015",\ + "0.768695, 0.948237, 1.135416, 1.437619, 2.021163",\ + "1.024420, 1.203963, 1.391141, 1.693345, 2.276889",\ + "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\ + "0.722973, 0.902898, 1.090214, 1.392134, 1.975390",\ + "0.751916, 0.931841, 1.119157, 1.421077, 2.004333",\ + "0.823064, 1.002989, 1.190305, 1.492225, 2.075481",\ + "1.078790, 1.258714, 1.446030, 1.747951, 2.331206",\ + "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\ + "1.004568, 1.188463, 1.374389, 1.675861, 2.258667",\ + "1.033511, 1.217406, 1.403332, 1.704803, 2.287610",\ + "1.104659, 1.288554, 1.474480, 1.775951, 2.358758",\ + "1.360384, 1.544279, 1.730205, 2.031677, 2.614483",\ + "2.270849, 2.454743, 2.640669, 2.942141, 3.524948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043180",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.389691, 0.657302, 0.918703, 1.358480, 2.237641",\ + "0.411640, 0.679251, 0.940643, 1.380389, 2.259487",\ + "0.459656, 0.727267, 0.988659, 1.428405, 2.307503",\ + "0.624965, 0.892576, 1.153968, 1.593714, 2.472812",\ + "1.214409, 1.482020, 1.743420, 2.183197, 3.062358",\ + "0.478395, 0.745377, 1.007344, 1.446709, 2.325046",\ + "0.500344, 0.767326, 1.029284, 1.468618, 2.346892",\ + "0.548360, 0.815342, 1.077300, 1.516634, 2.394908",\ + "0.713669, 0.980651, 1.242609, 1.681943, 2.560217",\ + "1.303113, 1.570095, 1.832061, 2.271426, 3.149764",\ + "0.571337, 0.838697, 1.099388, 1.538955, 2.418088",\ + "0.593287, 0.860646, 1.121328, 1.560864, 2.439934",\ + "0.641303, 0.908662, 1.169344, 1.608880, 2.487950",\ + "0.806611, 1.073971, 1.334653, 1.774188, 2.653259",\ + "1.396055, 1.663415, 1.924106, 2.363672, 3.242805",\ + "0.637181, 0.907261, 1.166444, 1.605966, 2.485009",\ + "0.659130, 0.929210, 1.188385, 1.627875, 2.506856",\ + "0.707146, 0.977226, 1.236400, 1.675891, 2.554872",\ + "0.872455, 1.142535, 1.401709, 1.841200, 2.720181",\ + "1.461899, 1.731979, 1.991162, 2.430684, 3.309727",\ + "0.983703, 1.288097, 1.537115, 1.975192, 2.851345",\ + "1.005652, 1.310046, 1.559055, 1.997100, 2.873191",\ + "1.053668, 1.358062, 1.607071, 2.045116, 2.921207",\ + "1.218976, 1.523371, 1.772380, 2.210425, 3.086516",\ + "1.808420, 2.112815, 2.361833, 2.799909, 3.676063"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2469*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.415862, 0.679394, 0.955513, 1.423645, 2.358649",\ + "0.444805, 0.708336, 0.984456, 1.452588, 2.387592",\ + "0.515953, 0.779484, 1.055604, 1.523736, 2.458740",\ + "0.771678, 1.035210, 1.311329, 1.779461, 2.714465",\ + "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\ + "0.504057, 0.766934, 1.043080, 1.510360, 2.444582",\ + "0.532999, 0.795877, 1.072023, 1.539303, 2.473526",\ + "0.604147, 0.867025, 1.143171, 1.610451, 2.544673",\ + "0.859873, 1.122750, 1.398896, 1.866176, 2.800399",\ + "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\ + "0.592373, 0.855914, 1.131045, 1.598000, 2.531538",\ + "0.621315, 0.884856, 1.159988, 1.626943, 2.560481",\ + "0.692463, 0.956004, 1.231135, 1.698091, 2.631628",\ + "0.948189, 1.211730, 1.486861, 1.953817, 2.887354",\ + "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\ + "0.654869, 0.921547, 1.195184, 1.662089, 2.595047",\ + "0.683811, 0.950490, 1.224127, 1.691032, 2.623990",\ + "0.754959, 1.021638, 1.295275, 1.762180, 2.695137",\ + "1.010685, 1.277363, 1.551000, 2.017905, 2.950863",\ + "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\ + "0.983994, 1.285862, 1.547048, 2.011533, 2.940503",\ + "1.012937, 1.314805, 1.575991, 2.040476, 2.969446",\ + "1.084085, 1.385953, 1.647139, 2.111624, 3.040593",\ + "1.339811, 1.641678, 1.902864, 2.367349, 3.296319",\ + "2.250275, 2.552142, 2.813329, 3.277813, 4.206782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.043180, 0.043180, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043182",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712248",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.372646, 0.554704, 0.750937, 1.060114, 1.654586",\ + "0.394593, 0.576651, 0.772784, 1.081916, 1.676369",\ + "0.442609, 0.624667, 0.820800, 1.129932, 1.724385",\ + "0.607918, 0.789976, 0.986109, 1.295241, 1.889696",\ + "1.197364, 1.379422, 1.575655, 1.884836, 2.479319",\ + "0.460061, 0.642022, 0.838218, 1.147419, 1.741940",\ + "0.482008, 0.663970, 0.860065, 1.169221, 1.763722",\ + "0.530024, 0.711986, 0.908081, 1.217237, 1.811739",\ + "0.695333, 0.877294, 1.073389, 1.382546, 1.977050",\ + "1.284779, 1.466740, 1.662936, 1.972141, 2.566672",\ + "0.540937, 0.722359, 0.918245, 1.227448, 1.821971",\ + "0.562884, 0.744306, 0.940092, 1.249249, 1.843754",\ + "0.610900, 0.792322, 0.988108, 1.297265, 1.891770",\ + "0.776209, 0.957631, 1.153416, 1.462574, 2.057081",\ + "1.365655, 1.547077, 1.742963, 2.052169, 2.646704",\ + "0.598584, 0.780196, 0.975981, 1.284918, 1.879067",\ + "0.620531, 0.802143, 0.997827, 1.306720, 1.900850",\ + "0.668547, 0.850159, 1.045843, 1.354736, 1.948866",\ + "0.833856, 1.015468, 1.211152, 1.520045, 2.114177",\ + "1.423301, 1.604914, 1.800699, 2.109640, 2.703799",\ + "0.900791, 1.085573, 1.279644, 1.588125, 2.181385",\ + "0.922739, 1.107520, 1.301491, 1.609926, 2.203168",\ + "0.970755, 1.155536, 1.349506, 1.657943, 2.251184",\ + "1.136063, 1.320845, 1.514815, 1.823252, 2.416495",\ + "1.725509, 1.910291, 2.104362, 2.412847, 3.006117"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.035869, 0.035869, 0.035869, 0.035869, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443446",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2391*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.411884, 0.671443, 0.943078, 1.399240, 2.310408",\ + "0.440827, 0.700386, 0.972021, 1.428183, 2.339350",\ + "0.511975, 0.771534, 1.043169, 1.499331, 2.410498",\ + "0.767700, 1.027260, 1.298895, 1.755056, 2.666224",\ + "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\ + "0.499989, 0.758976, 1.030607, 1.485955, 2.396341",\ + "0.528932, 0.787919, 1.059550, 1.514898, 2.425284",\ + "0.600080, 0.859067, 1.130698, 1.586046, 2.496432",\ + "0.855805, 1.114792, 1.386424, 1.841771, 2.752157",\ + "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\ + "0.588019, 0.847941, 1.118572, 1.573594, 2.483296",\ + "0.616962, 0.876883, 1.147514, 1.602537, 2.512239",\ + "0.688110, 0.948031, 1.218662, 1.673685, 2.583387",\ + "0.943835, 1.203757, 1.474388, 1.929410, 2.839113",\ + "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\ + "0.650240, 0.913552, 1.182709, 1.637669, 2.546805",\ + "0.679183, 0.942495, 1.211652, 1.666611, 2.575748",\ + "0.750331, 1.013643, 1.282800, 1.737759, 2.646896",\ + "1.006057, 1.269368, 1.538526, 1.993485, 2.902622",\ + "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\ + "0.977628, 1.277600, 1.534452, 1.987055, 2.892262",\ + "1.006571, 1.306543, 1.563395, 2.015998, 2.921204",\ + "1.077719, 1.377691, 1.634543, 2.087146, 2.992352",\ + "1.333444, 1.633417, 1.890268, 2.342871, 3.248078",\ + "2.243908, 2.543881, 2.800732, 3.253335, 4.158542"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.043180, 0.043181, 0.043181, 0.043181, 0.043183",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090366",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712249, 0.712249, 0.712247",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.370982, 0.553150, 0.749248, 1.058587, 1.653547",\ + "0.392932, 0.575099, 0.771096, 1.080389, 1.675331",\ + "0.440948, 0.623115, 0.819112, 1.128405, 1.723348",\ + "0.606257, 0.788424, 0.984421, 1.293715, 1.888659",\ + "1.195700, 1.377868, 1.573966, 1.883303, 2.478263",\ + "0.458403, 0.640469, 0.836529, 1.145892, 1.740901",\ + "0.480352, 0.662418, 0.858377, 1.167694, 1.762685",\ + "0.528368, 0.710434, 0.906393, 1.215710, 1.810701",\ + "0.693677, 0.875743, 1.071702, 1.381020, 1.976012",\ + "1.283120, 1.465186, 1.661247, 1.970608, 2.565616",\ + "0.539270, 0.720805, 0.916556, 1.225920, 1.820932",\ + "0.561219, 0.742755, 0.938404, 1.247723, 1.842716",\ + "0.609235, 0.790771, 0.986420, 1.295739, 1.890733",\ + "0.774544, 0.956080, 1.151728, 1.461048, 2.056044",\ + "1.363988, 1.545523, 1.741274, 2.050637, 2.645648",\ + "0.596909, 0.778642, 0.974291, 1.283391, 1.878029",\ + "0.618858, 0.800592, 0.996139, 1.305194, 1.899813",\ + "0.666874, 0.848608, 1.044155, 1.353210, 1.947829",\ + "0.832183, 1.013916, 1.209464, 1.518519, 2.113140",\ + "1.421627, 1.603360, 1.799009, 2.108108, 2.702744",\ + "0.899004, 1.084021, 1.277955, 1.586599, 2.180348",\ + "0.920954, 1.105970, 1.299802, 1.608401, 2.202132",\ + "0.968969, 1.153986, 1.347818, 1.656417, 2.250149",\ + "1.134278, 1.319295, 1.513127, 1.821727, 2.415460",\ + "1.723722, 1.908738, 2.102673, 2.411315, 3.005064"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712",\ + "0.035869, 0.035869, 0.035869, 0.035870, 0.035870",\ + "0.064692, 0.064692, 0.064692, 0.064693, 0.064694",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142527",\ + "0.443427, 0.443427, 0.443428, 0.443434, 0.443448",\ + "1.518709, 1.518709, 1.518710, 1.518710, 1.518712"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2332*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.504167, 0.682507, 0.862854, 1.149040, 1.699793",\ + "0.533110, 0.711450, 0.891797, 1.177983, 1.728736",\ + "0.604258, 0.782598, 0.962945, 1.249131, 1.799884",\ + "0.859984, 1.038323, 1.218670, 1.504856, 2.055609",\ + "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\ + "0.589106, 0.767343, 0.947924, 1.234547, 1.786172",\ + "0.618049, 0.796286, 0.976867, 1.263489, 1.815114",\ + "0.689197, 0.867433, 1.048015, 1.334637, 1.886262",\ + "0.944922, 1.123159, 1.303740, 1.590363, 2.141988",\ + "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\ + "0.665012, 0.842786, 1.022733, 1.309143, 1.860344",\ + "0.693955, 0.871729, 1.051676, 1.338086, 1.889287",\ + "0.765103, 0.942877, 1.122823, 1.409234, 1.960435",\ + "1.020828, 1.198602, 1.378549, 1.664959, 2.216160",\ + "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\ + "0.719364, 0.897532, 1.077598, 1.363737, 1.914661",\ + "0.748307, 0.926474, 1.106541, 1.392680, 1.943604",\ + "0.819455, 0.997622, 1.177689, 1.463828, 2.014752",\ + "1.075180, 1.253348, 1.433414, 1.719553, 2.270478",\ + "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\ + "1.000786, 1.183049, 1.361751, 1.647463, 2.197939",\ + "1.029729, 1.211992, 1.390694, 1.676406, 2.226882",\ + "1.100877, 1.283140, 1.461842, 1.747554, 2.298030",\ + "1.356602, 1.538865, 1.717567, 2.003279, 2.553755",\ + "2.267066, 2.449329, 2.628031, 2.913743, 3.464219"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.043180, 0.043180, 0.043180, 0.043180, 0.043181",\ + "0.090365, 0.090365, 0.090365, 0.090365, 0.090365",\ + "0.222668, 0.222668, 0.222668, 0.222668, 0.222668",\ + "0.712250, 0.712250, 0.712250, 0.712250, 0.712250",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.388255, 0.653254, 0.912284, 1.348548, 2.220695",\ + "0.410204, 0.675204, 0.934223, 1.370453, 2.242530",\ + "0.458220, 0.723220, 0.982239, 1.418469, 2.290546",\ + "0.623529, 0.888528, 1.147548, 1.583778, 2.455855",\ + "1.212973, 1.477972, 1.737002, 2.173266, 3.045412",\ + "0.476921, 0.741329, 1.000925, 1.436777, 2.308100",\ + "0.498870, 0.763278, 1.022864, 1.458682, 2.329936",\ + "0.546886, 0.811294, 1.070880, 1.506698, 2.377952",\ + "0.712195, 0.976603, 1.236189, 1.672007, 2.543260",\ + "1.301638, 1.566047, 1.825642, 2.261495, 3.132817",\ + "0.569727, 0.834623, 1.092960, 1.529020, 2.401142",\ + "0.591677, 0.856572, 1.114899, 1.550925, 2.422977",\ + "0.639693, 0.904588, 1.162915, 1.598941, 2.470994",\ + "0.805001, 1.069897, 1.328224, 1.764250, 2.636302",\ + "1.394445, 1.659341, 1.917678, 2.353738, 3.225859",\ + "0.635450, 0.903157, 1.160015, 1.596027, 2.468051",\ + "0.657399, 0.925106, 1.181954, 1.617932, 2.489887",\ + "0.705415, 0.973122, 1.229970, 1.665948, 2.537903",\ + "0.870724, 1.138431, 1.395279, 1.831257, 2.703212",\ + "1.460168, 1.727875, 1.984733, 2.420745, 3.292769",\ + "0.981239, 1.283655, 1.530653, 1.965228, 2.834378",\ + "1.003189, 1.305605, 1.552592, 1.987133, 2.856214",\ + "1.051205, 1.353621, 1.600608, 2.035149, 2.904230",\ + "1.216513, 1.518929, 1.765917, 2.200458, 3.069539",\ + "1.805957, 2.108373, 2.355371, 2.789946, 3.659096"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443428",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443429",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710",\ + "0.035869, 0.035869, 0.035869, 0.035869, 0.035869",\ + "0.064692, 0.064692, 0.064692, 0.064692, 0.064692",\ + "0.142526, 0.142526, 0.142526, 0.142526, 0.142526",\ + "0.443427, 0.443427, 0.443427, 0.443428, 0.443429",\ + "1.518709, 1.518709, 1.518709, 1.518709, 1.518710"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min_2273*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.141721, 0.170980, 0.242593, 0.498866, 1.411098",\ + "0.229906, 0.259165, 0.330790, 0.587108, 1.499024",\ + "0.318231, 0.347489, 0.419118, 0.675627, 1.587106",\ + "0.380823, 0.410078, 0.481658, 0.738460, 1.650402",\ + "0.710704, 0.739954, 0.811356, 1.068597, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\ + "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\ + "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\ + "0.043180, 0.090365, 0.222668, 0.712250, 2.448223",\ + "0.043180, 0.090365, 0.222668, 0.712250, 2.448223"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.179981, 0.202635, 0.251659, 0.417360, 1.003853",\ + "0.267384, 0.290039, 0.339062, 0.504764, 1.091257",\ + "0.348282, 0.370934, 0.419962, 0.585668, 1.172170",\ + "0.405945, 0.428592, 0.477629, 0.643342, 1.229861",\ + "0.708302, 0.730939, 0.780004, 0.945787, 1.532477"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.035869, 0.064690, 0.142524, 0.442595, 1.516425",\ + "0.035869, 0.064690, 0.142524, 0.442595, 1.516425",\ + "0.035869, 0.064690, 0.142524, 0.442641, 1.516425",\ + "0.035869, 0.064690, 0.142524, 0.442726, 1.516425",\ + "0.035869, 0.064691, 0.142524, 0.443427, 1.516425"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.146678, 0.146678, 0.146678, 0.146678, 0.146678",\ + "0.165298, 0.165298, 0.165298, 0.165298, 0.165298",\ + "0.241802, 0.241802, 0.241802, 0.241802, 0.241802",\ + "0.367706, 0.367706, 0.367706, 0.367706, 0.367706",\ + "0.946794, 0.946794, 0.946794, 0.946794, 0.946794"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.412191, 0.412191, 0.412191, 0.412191, 0.412191",\ + "0.424880, 0.424880, 0.424880, 0.424880, 0.424880",\ + "0.479563, 0.479563, 0.479563, 0.479563, 0.479563",\ + "0.581996, 0.581996, 0.581996, 0.581996, 0.581996",\ + "1.256928, 1.256928, 1.256928, 1.256928, 1.256928"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_cgsf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.138937, -0.138937, -0.138937, -0.138937, -0.138937",\ + "-0.155751, -0.155751, -0.155751, -0.155751, -0.155751",\ + "-0.234216, -0.234216, -0.234216, -0.234216, -0.234216",\ + "-0.360721, -0.360721, -0.360721, -0.360721, -0.360721",\ + "-0.939265, -0.939265, -0.939265, -0.939265, -0.939265"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.408326, -0.408326, -0.408326, -0.408326, -0.408326",\ + "-0.417967, -0.417967, -0.417967, -0.417967, -0.417967",\ + "-0.475689, -0.475689, -0.475689, -0.475689, -0.475689",\ + "-0.578062, -0.578062, -0.578062, -0.578062, -0.578062",\ + "-1.250684, -1.250684, -1.250684, -1.250684, -1.250684"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[9]_cghr*/ + + timing () { + related_pin : "padmux2ast_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.088963, 0.118659, 0.189985, 0.445909, 1.359203",\ + "0.176595, 0.206339, 0.277538, 0.533662, 1.444562",\ + "0.274330, 0.305634, 0.377516, 0.633363, 1.547694",\ + "0.452110, 0.487212, 0.561030, 0.816620, 1.732299",\ + "0.755237, 0.801656, 0.884430, 1.139988, 2.048527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.044962, 0.091670, 0.223831, 0.718456, 2.481454",\ + "0.045846, 0.091918, 0.223831, 0.720074, 2.481454",\ + "0.052795, 0.096494, 0.223831, 0.720074, 2.481454",\ + "0.070125, 0.108925, 0.227741, 0.720074, 2.481454",\ + "0.113963, 0.145559, 0.246252, 0.720074, 2.481454"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.127301, 0.151950, 0.203155, 0.369998, 0.957371",\ + "0.206362, 0.230972, 0.282119, 0.448933, 1.035102",\ + "0.309711, 0.336083, 0.388248, 0.554957, 1.142995",\ + "0.487304, 0.519754, 0.577312, 0.745501, 1.332624",\ + "0.775221, 0.823575, 0.896452, 1.070131, 1.655247"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.044715, 0.073858, 0.149782, 0.448303, 1.525169",\ + "0.044715, 0.073858, 0.149782, 0.448303, 1.525169",\ + "0.053324, 0.079575, 0.152471, 0.448303, 1.525169",\ + "0.080832, 0.102703, 0.166343, 0.450943, 1.525169",\ + "0.138432, 0.160382, 0.212572, 0.461516, 1.526821"); + } + + } /* end of arc padmux2ast_i[1]_obs_ctrl_o[9]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.084586, 0.113378, 0.184446, 0.440600, 1.352120",\ + "0.171768, 0.200846, 0.271799, 0.528276, 1.439207",\ + "0.268285, 0.298195, 0.369868, 0.625566, 1.536303",\ + "0.442396, 0.476138, 0.548327, 0.804981, 1.718362",\ + "0.738546, 0.782374, 0.862671, 1.116124, 2.025527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.042344, 0.090303, 0.222464, 0.709820, 2.440521",\ + "0.043472, 0.090646, 0.222464, 0.709820, 2.440521",\ + "0.049500, 0.094474, 0.223126, 0.712718, 2.449750",\ + "0.065555, 0.105654, 0.227159, 0.712718, 2.460771",\ + "0.105524, 0.141324, 0.243057, 0.716552, 2.462313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.093008, 0.115079, 0.163442, 0.328951, 0.916956",\ + "0.178087, 0.200175, 0.248558, 0.413891, 1.001128",\ + "0.277566, 0.302239, 0.352189, 0.517358, 1.105026",\ + "0.446802, 0.478509, 0.534068, 0.699312, 1.285539",\ + "0.721986, 0.770109, 0.842702, 1.014834, 1.597599"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001432, 0.004671, 0.013253, 0.044568, 0.156168"); + values ( "0.036627, 0.065671, 0.143118, 0.443055, 1.519637",\ + "0.037498, 0.065879, 0.143311, 0.444331, 1.520249",\ + "0.048608, 0.074072, 0.147057, 0.444933, 1.520249",\ + "0.075730, 0.097335, 0.160558, 0.448031, 1.520263",\ + "0.132420, 0.154310, 0.206677, 0.457722, 1.522974"); + } + + } /* end of arc padmux2ast_i[1]_obs_ctrl_o[9]_una_min*/ + +} /* end of pin obs_ctrl_o[9] */ + +pin("obs_ctrl_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001401 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.560256, 0.740460, 0.927949, 1.229942, 1.813454",\ + "0.590229, 0.770432, 0.957922, 1.259915, 1.843426",\ + "0.661974, 0.842177, 1.029667, 1.331659, 1.915171",\ + "0.918426, 1.098629, 1.286119, 1.588112, 2.171624",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.645195, 0.825743, 1.013958, 1.315954, 1.899832",\ + "0.675168, 0.855715, 1.043931, 1.345927, 1.929805",\ + "0.746912, 0.927460, 1.115675, 1.417671, 2.001549",\ + "1.003365, 1.183912, 1.372128, 1.674124, 2.258002",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.721107, 0.901186, 1.088767, 1.390551, 1.974005",\ + "0.751079, 0.931159, 1.118740, 1.420524, 2.003977",\ + "0.822824, 1.002903, 1.190484, 1.492268, 2.075722",\ + "1.079277, 1.259356, 1.446937, 1.748721, 2.332174",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.775476, 0.955698, 1.143418, 1.445091, 2.028322",\ + "0.805449, 0.985670, 1.173391, 1.475063, 2.058295",\ + "0.877193, 1.057415, 1.245135, 1.546808, 2.130039",\ + "1.133646, 1.313868, 1.501588, 1.803261, 2.386492",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.057071, 1.240966, 1.427369, 1.728817, 2.311599",\ + "1.087044, 1.270938, 1.457341, 1.758790, 2.341572",\ + "1.158788, 1.342683, 1.529086, 1.830534, 2.413317",\ + "1.415241, 1.599136, 1.785538, 2.086987, 2.669769",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.418156, 0.685942, 0.947522, 1.387219, 2.266614",\ + "0.442597, 0.710383, 0.971963, 1.411660, 2.291055",\ + "0.493471, 0.761257, 1.022837, 1.462534, 2.341929",\ + "0.659908, 0.927694, 1.189274, 1.628971, 2.508366",\ + "1.246791, 1.514577, 1.776157, 2.215854, 3.095249",\ + "0.506860, 0.774017, 1.036163, 1.475448, 2.354019",\ + "0.531302, 0.798458, 1.060604, 1.499889, 2.378460",\ + "0.582175, 0.849332, 1.111478, 1.550763, 2.429334",\ + "0.748612, 1.015769, 1.277915, 1.717200, 2.595771",\ + "1.335496, 1.602652, 1.864798, 2.304084, 3.182654",\ + "0.599803, 0.867162, 1.127888, 1.567612, 2.447061",\ + "0.624244, 0.891603, 1.152330, 1.592054, 2.471502",\ + "0.675117, 0.942477, 1.203203, 1.642927, 2.522376",\ + "0.841555, 1.108914, 1.369640, 1.809364, 2.688813",\ + "1.428438, 1.695797, 1.956524, 2.396248, 3.275696",\ + "0.665646, 0.935726, 1.194908, 1.634463, 2.513572",\ + "0.690087, 0.960168, 1.219349, 1.658904, 2.538013",\ + "0.740961, 1.011041, 1.270223, 1.709777, 2.588887",\ + "0.907398, 1.177478, 1.436660, 1.876215, 2.755324",\ + "1.494281, 1.764362, 2.023544, 2.463098, 3.342207",\ + "1.012168, 1.316562, 1.565571, 2.003616, 2.879708",\ + "1.036609, 1.341003, 1.590012, 2.028058, 2.904149",\ + "1.087482, 1.391877, 1.640886, 2.078931, 2.955022",\ + "1.253920, 1.558314, 1.807323, 2.245368, 3.121460",\ + "1.840803, 2.145197, 2.394207, 2.832252, 3.708343"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2698*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.468362, 0.731935, 1.008208, 1.476938, 2.414397",\ + "0.498334, 0.761908, 1.038180, 1.506910, 2.444369",\ + "0.570079, 0.833652, 1.109925, 1.578655, 2.516114",\ + "0.826532, 1.090105, 1.366378, 1.835107, 2.772566",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.556556, 0.819476, 1.095776, 1.563653, 2.500330",\ + "0.586529, 0.849449, 1.125748, 1.593625, 2.530303",\ + "0.658273, 0.921193, 1.197493, 1.665370, 2.602047",\ + "0.914726, 1.177646, 1.453945, 1.921822, 2.858500",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.644872, 0.908457, 1.183741, 1.651275, 2.587286",\ + "0.674845, 0.938429, 1.213713, 1.681248, 2.617258",\ + "0.746589, 1.010174, 1.285458, 1.752992, 2.689003",\ + "1.003042, 1.266626, 1.541910, 2.009445, 2.945455",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.707368, 0.974091, 1.247880, 1.715189, 2.650795",\ + "0.737341, 1.004064, 1.277853, 1.745162, 2.680767",\ + "0.809085, 1.075809, 1.349597, 1.816906, 2.752512",\ + "1.065538, 1.332261, 1.606050, 2.073359, 3.008964",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.036494, 1.338422, 1.599747, 2.064539, 2.996251",\ + "1.066466, 1.368395, 1.629720, 2.094511, 3.026223",\ + "1.138211, 1.440139, 1.701465, 2.166256, 3.097968",\ + "1.394664, 1.696592, 1.957917, 2.422708, 3.354420",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715792, 0.715788",\ + "2.463890, 2.463890, 2.463889, 2.463887, 2.463883"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.401109, 0.583541, 0.779933, 1.088987, 1.683794",\ + "0.425551, 0.607982, 0.804374, 1.113428, 1.708236",\ + "0.476424, 0.658856, 0.855248, 1.164301, 1.759109",\ + "0.642861, 0.825293, 1.021685, 1.330738, 1.925545",\ + "1.229745, 1.412177, 1.608569, 1.917621, 2.512428",\ + "0.488524, 0.670927, 0.867426, 1.176292, 1.771148",\ + "0.512965, 0.695368, 0.891868, 1.200733, 1.795590",\ + "0.563839, 0.746242, 0.942741, 1.251606, 1.846463",\ + "0.730276, 0.912679, 1.109178, 1.418043, 2.012899",\ + "1.317160, 1.499562, 1.696062, 2.004926, 2.599781",\ + "0.569400, 0.751263, 0.947453, 1.256320, 1.851179",\ + "0.593842, 0.775705, 0.971894, 1.280761, 1.875621",\ + "0.644715, 0.826578, 1.022768, 1.331635, 1.926494",\ + "0.811152, 0.993015, 1.189205, 1.498072, 2.092930",\ + "1.398036, 1.579899, 1.776089, 2.084955, 2.679813",\ + "0.627047, 0.808812, 1.004997, 1.313565, 1.907827",\ + "0.651488, 0.833253, 1.029438, 1.338006, 1.932269",\ + "0.702362, 0.884127, 1.080312, 1.388880, 1.983142",\ + "0.868799, 1.050564, 1.246749, 1.555317, 2.149578",\ + "1.455682, 1.637447, 1.833632, 2.142200, 2.736460",\ + "0.929255, 1.114036, 1.308631, 1.616580, 2.209674",\ + "0.953696, 1.138477, 1.333072, 1.641021, 2.234116",\ + "1.004569, 1.189351, 1.383945, 1.691895, 2.284989",\ + "1.171007, 1.355788, 1.550383, 1.858332, 2.451425",\ + "1.757890, 1.942672, 2.137266, 2.445215, 3.038307"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523417"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2629*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.464386, 0.724016, 0.995888, 1.452767, 2.366527",\ + "0.494359, 0.753988, 1.025861, 1.482740, 2.396500",\ + "0.566104, 0.825733, 1.097605, 1.554485, 2.468244",\ + "0.822556, 1.082185, 1.354057, 1.810937, 2.724696",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.552491, 0.811549, 1.083418, 1.539483, 2.452461",\ + "0.582464, 0.841522, 1.113391, 1.569456, 2.482434",\ + "0.654208, 0.913266, 1.185135, 1.641200, 2.554178",\ + "0.910661, 1.169719, 1.441588, 1.897652, 2.810630",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.640521, 0.900515, 1.171383, 1.627106, 2.539416",\ + "0.670494, 0.930488, 1.201355, 1.657078, 2.569389",\ + "0.742239, 1.002232, 1.273100, 1.728823, 2.641133",\ + "0.998691, 1.258685, 1.529552, 1.985275, 2.897585",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.702743, 0.966129, 1.235520, 1.691019, 2.602925",\ + "0.732715, 0.996101, 1.265493, 1.720992, 2.632898",\ + "0.804460, 1.067846, 1.337237, 1.792736, 2.704642",\ + "1.060912, 1.324298, 1.593690, 2.049189, 2.961094",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.030130, 1.330203, 1.587268, 2.040320, 2.948381",\ + "1.060103, 1.360176, 1.617240, 2.070293, 2.978354",\ + "1.131847, 1.431921, 1.688985, 2.142037, 3.050098",\ + "1.388300, 1.688373, 1.945437, 2.398489, 3.306550",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463890, 2.463888, 2.463885, 2.463879",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045709",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223656, 0.223656",\ + "0.715794, 0.715794, 0.715793, 0.715790, 0.715784",\ + "2.463890, 2.463889, 2.463888, 2.463885, 2.463879"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.399448, 0.581989, 0.778244, 1.087461, 1.682757",\ + "0.423889, 0.606430, 0.802685, 1.111902, 1.707199",\ + "0.474763, 0.657304, 0.853558, 1.162776, 1.758072",\ + "0.641200, 0.823741, 1.019996, 1.329213, 1.924508",\ + "1.228083, 1.410624, 1.606879, 1.916096, 2.511390",\ + "0.486868, 0.669374, 0.865736, 1.174766, 1.770111",\ + "0.511309, 0.693815, 0.890178, 1.199207, 1.794553",\ + "0.562183, 0.744689, 0.941051, 1.250081, 1.845426",\ + "0.728620, 0.911126, 1.107488, 1.416518, 2.011862",\ + "1.315503, 1.498010, 1.694372, 2.003401, 2.598744",\ + "0.567735, 0.749711, 0.945763, 1.254794, 1.850142",\ + "0.592177, 0.774152, 0.970205, 1.279236, 1.874584",\ + "0.643050, 0.825026, 1.021078, 1.330109, 1.925457",\ + "0.809487, 0.991463, 1.187515, 1.496546, 2.091893",\ + "1.396371, 1.578347, 1.774399, 2.083429, 2.678775",\ + "0.625374, 0.807260, 1.003307, 1.312040, 1.906790",\ + "0.649816, 0.831701, 1.027748, 1.336481, 1.931232",\ + "0.700689, 0.882574, 1.078622, 1.387354, 1.982105",\ + "0.867126, 1.049011, 1.245059, 1.553791, 2.148541",\ + "1.454010, 1.635895, 1.831943, 2.140674, 2.735423",\ + "0.927469, 1.112486, 1.306941, 1.615054, 2.208637",\ + "0.951911, 1.136927, 1.331383, 1.639496, 2.233079",\ + "1.002784, 1.187801, 1.382256, 1.690369, 2.283952",\ + "1.169221, 1.354238, 1.548693, 1.856806, 2.450387",\ + "1.756105, 1.941121, 2.135577, 2.443689, 3.037270"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073392, 0.073390",\ + "0.149511, 0.149511, 0.149511, 0.149511, 0.149511",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523416"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2576*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.556670, 0.735097, 0.915357, 1.201564, 1.752681",\ + "0.586643, 0.765069, 0.945330, 1.231536, 1.782653",\ + "0.658387, 0.836814, 1.017074, 1.303281, 1.854398",\ + "0.914840, 1.093267, 1.273527, 1.559734, 2.110850",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.641609, 0.820369, 1.001272, 1.287484, 1.839059",\ + "0.671581, 0.850342, 1.031245, 1.317456, 1.869031",\ + "0.743326, 0.922086, 1.102990, 1.389201, 1.940776",\ + "0.999778, 1.178539, 1.359442, 1.645654, 2.197229",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.717515, 0.895813, 1.076081, 1.362081, 1.913231",\ + "0.747487, 0.925785, 1.106054, 1.392053, 1.943204",\ + "0.819232, 0.997530, 1.177799, 1.463798, 2.014948",\ + "1.075685, 1.253982, 1.434251, 1.720250, 2.271401",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.771867, 0.950324, 1.130732, 1.416620, 1.967548",\ + "0.801839, 0.980297, 1.160705, 1.446593, 1.997521",\ + "0.873584, 1.052042, 1.232450, 1.518338, 2.069266",\ + "1.130037, 1.308494, 1.488902, 1.774790, 2.325718",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.053289, 1.235552, 1.414683, 1.700347, 2.250826",\ + "1.083261, 1.265524, 1.444655, 1.730319, 2.280799",\ + "1.155006, 1.337269, 1.516400, 1.802064, 2.352543",\ + "1.411458, 1.593722, 1.772853, 2.058517, 2.608996",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890",\ + "0.045710, 0.045710, 0.045710, 0.045710, 0.045710",\ + "0.092269, 0.092269, 0.092269, 0.092269, 0.092269",\ + "0.223657, 0.223657, 0.223657, 0.223657, 0.223657",\ + "0.715794, 0.715794, 0.715794, 0.715794, 0.715794",\ + "2.463890, 2.463890, 2.463890, 2.463890, 2.463890"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.416720, 0.681890, 0.941092, 1.377274, 2.249640",\ + "0.441162, 0.706331, 0.965533, 1.401715, 2.274081",\ + "0.492035, 0.757205, 1.016407, 1.452589, 2.324954",\ + "0.658472, 0.923642, 1.182844, 1.619026, 2.491391",\ + "1.245356, 1.510525, 1.769727, 2.205910, 3.078275",\ + "0.505386, 0.769965, 1.029733, 1.465503, 2.337044",\ + "0.529827, 0.794406, 1.054174, 1.489944, 2.361485",\ + "0.580701, 0.845280, 1.105047, 1.540818, 2.412359",\ + "0.747138, 1.011717, 1.271485, 1.707255, 2.578796",\ + "1.334021, 1.598600, 1.858368, 2.294138, 3.165680",\ + "0.598193, 0.863088, 1.121458, 1.557667, 2.430086",\ + "0.622634, 0.887529, 1.145899, 1.582108, 2.454527",\ + "0.673507, 0.938403, 1.196773, 1.632982, 2.505401",\ + "0.839945, 1.104840, 1.363210, 1.799419, 2.671838",\ + "1.426828, 1.691723, 1.950093, 2.386303, 3.258722",\ + "0.663915, 0.931622, 1.188478, 1.624518, 2.496598",\ + "0.688356, 0.956063, 1.212919, 1.648959, 2.521039",\ + "0.739230, 1.006937, 1.263793, 1.699832, 2.571912",\ + "0.905667, 1.173374, 1.430230, 1.866270, 2.738349",\ + "1.492550, 1.760257, 2.017113, 2.453153, 3.325233",\ + "1.009705, 1.312121, 1.559108, 1.993649, 2.862731",\ + "1.034146, 1.336562, 1.583549, 2.018090, 2.887172",\ + "1.085019, 1.387435, 1.634423, 2.068964, 2.938045",\ + "1.251456, 1.553873, 1.800860, 2.235401, 3.104483",\ + "1.838340, 2.140756, 2.387743, 2.822284, 3.691366"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419",\ + "0.044220, 0.044220, 0.044220, 0.044220, 0.044220",\ + "0.073393, 0.073393, 0.073393, 0.073393, 0.073393",\ + "0.149510, 0.149510, 0.149510, 0.149510, 0.149510",\ + "0.447701, 0.447701, 0.447701, 0.447701, 0.447701",\ + "1.523418, 1.523418, 1.523418, 1.523418, 1.523419"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_2513*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.323944, 0.353916, 0.425661, 0.682114, 1.594576",\ + "0.411334, 0.441307, 0.513052, 0.769505, 1.681967",\ + "0.492253, 0.522226, 0.593971, 0.850424, 1.762885",\ + "0.549994, 0.579967, 0.651712, 0.908165, 1.820624",\ + "0.852699, 0.882672, 0.954417, 1.210871, 2.123326"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.045711, 0.092269, 0.223658, 0.715775, 2.463871",\ + "0.045711, 0.092269, 0.223735, 0.715775, 2.463871",\ + "0.045711, 0.092269, 0.223968, 0.715775, 2.463871",\ + "0.045711, 0.092270, 0.223968, 0.715775, 2.463871",\ + "0.045873, 0.092295, 0.224303, 0.715788, 2.463884"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.296604, 0.321045, 0.371919, 0.538356, 1.125239",\ + "0.383997, 0.408438, 0.459311, 0.625749, 1.212632",\ + "0.464866, 0.489307, 0.540181, 0.706618, 1.293501",\ + "0.522515, 0.546956, 0.597830, 0.764267, 1.351150",\ + "0.825652, 0.850326, 0.901556, 1.068388, 1.654962"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.044220, 0.073393, 0.149516, 0.447701, 1.524168",\ + "0.044220, 0.073393, 0.149516, 0.447701, 1.524168",\ + "0.044220, 0.073393, 0.149516, 0.447701, 1.524042",\ + "0.044220, 0.073393, 0.149516, 0.447701, 1.523806",\ + "0.044219, 0.073327, 0.149516, 0.447696, 1.523418"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.507461, 0.687575, 0.875153, 1.177133, 1.760229",\ + "0.536439, 0.716552, 0.904131, 1.206110, 1.789207",\ + "0.607591, 0.787705, 0.975283, 1.277263, 1.860359",\ + "0.863316, 1.043430, 1.231008, 1.532988, 2.116084",\ + "1.774034, 1.954148, 2.141726, 2.443706, 3.026802",\ + "0.592400, 0.772411, 0.960223, 1.262639, 1.846608",\ + "0.621377, 0.801388, 0.989201, 1.291617, 1.875585",\ + "0.692529, 0.872540, 1.060353, 1.362769, 1.946737",\ + "0.948255, 1.128266, 1.316078, 1.618494, 2.202463",\ + "1.858973, 2.038984, 2.226796, 2.529212, 3.113181",\ + "0.668312, 0.847854, 1.035032, 1.337236, 1.920780",\ + "0.697289, 0.876831, 1.064010, 1.366214, 1.949757",\ + "0.768441, 0.947984, 1.135162, 1.437366, 2.020910",\ + "1.024167, 1.203709, 1.390887, 1.693091, 2.276635",\ + "1.934885, 2.114427, 2.301605, 2.603809, 3.187353",\ + "0.722681, 0.902605, 1.089921, 1.391842, 1.975097",\ + "0.751658, 0.931583, 1.118899, 1.420819, 2.004075",\ + "0.822811, 1.002735, 1.190051, 1.491971, 2.075227",\ + "1.078536, 1.258460, 1.445776, 1.747697, 2.330952",\ + "1.989254, 2.169178, 2.356494, 2.658415, 3.241670",\ + "1.004276, 1.188170, 1.374097, 1.675568, 2.258375",\ + "1.033253, 1.217148, 1.403074, 1.704545, 2.287352",\ + "1.104405, 1.288300, 1.474226, 1.775698, 2.358505",\ + "1.360131, 1.544025, 1.729952, 2.031423, 2.614230",\ + "2.270849, 2.454743, 2.640669, 2.942141, 3.524948"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.389483, 0.657094, 0.918495, 1.358271, 2.237432",\ + "0.411493, 0.679104, 0.940496, 1.380242, 2.259341",\ + "0.459519, 0.727130, 0.988522, 1.428268, 2.307366",\ + "0.624827, 0.892438, 1.153830, 1.593576, 2.472674",\ + "1.214436, 1.482046, 1.743447, 2.183224, 3.062385",\ + "0.478187, 0.745169, 1.007135, 1.446501, 2.324838",\ + "0.500198, 0.767179, 1.029137, 1.468471, 2.346746",\ + "0.548223, 0.815205, 1.077163, 1.516497, 2.394772",\ + "0.713532, 0.980513, 1.242471, 1.681805, 2.560080",\ + "1.303140, 1.570121, 1.832088, 2.271453, 3.149790",\ + "0.571129, 0.838489, 1.099180, 1.538746, 2.417880",\ + "0.593140, 0.860499, 1.121182, 1.560717, 2.439788",\ + "0.641166, 0.908525, 1.169207, 1.608743, 2.487813",\ + "0.806474, 1.073833, 1.334516, 1.774051, 2.653121",\ + "1.396082, 1.663441, 1.924133, 2.363699, 3.242832",\ + "0.636973, 0.907053, 1.166236, 1.605758, 2.484801",\ + "0.658983, 0.929063, 1.188238, 1.627728, 2.506709",\ + "0.707009, 0.977089, 1.236264, 1.675754, 2.554735",\ + "0.872317, 1.142398, 1.401572, 1.841062, 2.720043",\ + "1.461926, 1.732006, 1.991189, 2.430710, 3.309754",\ + "0.983494, 1.287889, 1.536907, 1.974983, 2.851137",\ + "1.005505, 1.309899, 1.558908, 1.996953, 2.873044",\ + "1.053531, 1.357925, 1.606934, 2.044979, 2.921070",\ + "1.218839, 1.523233, 1.772242, 2.210288, 3.086378",\ + "1.808447, 2.112841, 2.361860, 2.799936, 3.676089"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2454*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.415570, 0.679101, 0.955220, 1.423352, 2.358356",\ + "0.444547, 0.708078, 0.984198, 1.452330, 2.387333",\ + "0.515699, 0.779231, 1.055350, 1.523482, 2.458486",\ + "0.771425, 1.034956, 1.311076, 1.779207, 2.714211",\ + "1.682143, 1.945674, 2.221793, 2.689925, 3.624929",\ + "0.503764, 0.766641, 1.042787, 1.510067, 2.444290",\ + "0.532741, 0.795619, 1.071764, 1.539045, 2.473267",\ + "0.603894, 0.866771, 1.142917, 1.610197, 2.544420",\ + "0.859619, 1.122496, 1.398642, 1.865922, 2.800145",\ + "1.770337, 2.033214, 2.309360, 2.776640, 3.710862",\ + "0.592080, 0.855621, 1.130752, 1.597708, 2.531245",\ + "0.621057, 0.884598, 1.159729, 1.626685, 2.560222",\ + "0.692210, 0.955751, 1.230882, 1.697837, 2.631375",\ + "0.947935, 1.211476, 1.486607, 1.953563, 2.887100",\ + "1.858653, 2.122194, 2.397325, 2.864281, 3.797817",\ + "0.654576, 0.921255, 1.194892, 1.661796, 2.594754",\ + "0.683553, 0.950232, 1.223869, 1.690774, 2.623731",\ + "0.754706, 1.021384, 1.295022, 1.761926, 2.694884",\ + "1.010431, 1.277110, 1.550747, 2.017652, 2.950609",\ + "1.921149, 2.187827, 2.461465, 2.928370, 3.861326",\ + "0.983702, 1.285569, 1.546756, 2.011240, 2.940210",\ + "1.012679, 1.314547, 1.575733, 2.040218, 2.969187",\ + "1.083832, 1.385699, 1.646886, 2.111370, 3.040340",\ + "1.339557, 1.641424, 1.902611, 2.367095, 3.296065",\ + "2.250275, 2.552142, 2.813329, 3.277813, 4.206782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042749",\ + "0.089888, 0.089888, 0.089888, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222180",\ + "0.711766, 0.711766, 0.711766, 0.711765, 0.711764",\ + "2.448223, 2.448223, 2.448224, 2.448226, 2.448230"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.372438, 0.554496, 0.750729, 1.059908, 1.654385",\ + "0.394447, 0.576504, 0.772637, 1.081769, 1.676222",\ + "0.442472, 0.624530, 0.820663, 1.129795, 1.724248",\ + "0.607781, 0.789838, 0.985971, 1.295103, 1.889559",\ + "1.197391, 1.379448, 1.575682, 1.884862, 2.479345",\ + "0.459853, 0.641814, 0.838010, 1.147213, 1.741738",\ + "0.481861, 0.663823, 0.859918, 1.169074, 1.763576",\ + "0.529887, 0.711849, 0.907944, 1.217100, 1.811602",\ + "0.695195, 0.877157, 1.073252, 1.382408, 1.976912",\ + "1.284805, 1.466767, 1.662963, 1.972167, 2.566699",\ + "0.540729, 0.722151, 0.918037, 1.227241, 1.821770",\ + "0.562738, 0.744159, 0.939945, 1.249102, 1.843607",\ + "0.610763, 0.792185, 0.987971, 1.297128, 1.891634",\ + "0.776072, 0.957493, 1.153279, 1.462437, 2.056944",\ + "1.365682, 1.547103, 1.742990, 2.052196, 2.646730",\ + "0.598376, 0.779988, 0.975773, 1.284712, 1.878866",\ + "0.620384, 0.801996, 0.997680, 1.306573, 1.900703",\ + "0.668410, 0.850022, 1.045706, 1.354599, 1.948729",\ + "0.833718, 1.015330, 1.211014, 1.519907, 2.114039",\ + "1.423328, 1.604940, 1.800725, 2.109667, 2.703826",\ + "0.900583, 1.085365, 1.279436, 1.587919, 2.181184",\ + "0.922592, 1.107373, 1.301344, 1.609780, 2.203021",\ + "0.970618, 1.155399, 1.349370, 1.657806, 2.251047",\ + "1.135926, 1.320707, 1.514678, 1.823114, 2.416358",\ + "1.725536, 1.910317, 2.104389, 2.412873, 3.006144"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443195",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443195",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443195",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443196",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064461",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443183, 0.443196",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2376*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.411592, 0.671151, 0.942786, 1.398947, 2.310115",\ + "0.440569, 0.700128, 0.971763, 1.427925, 2.339092",\ + "0.511721, 0.771281, 1.042916, 1.499077, 2.410245",\ + "0.767447, 1.027006, 1.298641, 1.754802, 2.665970",\ + "1.678164, 1.937724, 2.209359, 2.665520, 3.576688",\ + "0.499696, 0.758684, 1.030315, 1.485663, 2.396049",\ + "0.528674, 0.787661, 1.059292, 1.514640, 2.425026",\ + "0.599826, 0.858813, 1.130445, 1.585792, 2.496178",\ + "0.855551, 1.114539, 1.386170, 1.841518, 2.751904",\ + "1.766269, 2.025257, 2.296888, 2.752235, 3.662621",\ + "0.587726, 0.847648, 1.118279, 1.573302, 2.483004",\ + "0.616704, 0.876625, 1.147256, 1.602279, 2.511981",\ + "0.687856, 0.947778, 1.218409, 1.673431, 2.583133",\ + "0.943582, 1.203503, 1.474134, 1.929157, 2.838859",\ + "1.854300, 2.114221, 2.384852, 2.839874, 3.749576",\ + "0.649948, 0.913259, 1.182417, 1.637376, 2.546513",\ + "0.678925, 0.942237, 1.211394, 1.666353, 2.575490",\ + "0.750077, 1.013389, 1.282547, 1.737506, 2.646642",\ + "1.005803, 1.269114, 1.538272, 1.993231, 2.902368",\ + "1.916521, 2.179832, 2.448990, 2.903949, 3.813085",\ + "0.977335, 1.277308, 1.534159, 1.986762, 2.891969",\ + "1.006312, 1.306285, 1.563137, 2.015740, 2.920946",\ + "1.077465, 1.377437, 1.634289, 2.086892, 2.992099",\ + "1.333190, 1.633163, 1.890014, 2.342618, 3.247824",\ + "2.243908, 2.543881, 2.800732, 3.253335, 4.158542"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234",\ + "0.042748, 0.042748, 0.042748, 0.042749, 0.042750",\ + "0.089888, 0.089888, 0.089889, 0.089889, 0.089889",\ + "0.222179, 0.222179, 0.222179, 0.222180, 0.222180",\ + "0.711766, 0.711766, 0.711765, 0.711765, 0.711763",\ + "2.448223, 2.448223, 2.448225, 2.448228, 2.448234"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.370774, 0.552942, 0.749040, 1.058378, 1.653339",\ + "0.392785, 0.574952, 0.770949, 1.080242, 1.675184",\ + "0.440811, 0.622978, 0.818975, 1.128268, 1.723211",\ + "0.606119, 0.788286, 0.984283, 1.293577, 1.888521",\ + "1.195727, 1.377894, 1.573993, 1.883330, 2.478289",\ + "0.458194, 0.640260, 0.836321, 1.145683, 1.740692",\ + "0.480205, 0.662271, 0.858230, 1.167547, 1.762538",\ + "0.528231, 0.710297, 0.906256, 1.215573, 1.810564",\ + "0.693539, 0.875605, 1.071564, 1.380882, 1.975875",\ + "1.283147, 1.465213, 1.661273, 1.970635, 2.565643",\ + "0.539062, 0.720597, 0.916348, 1.225712, 1.820724",\ + "0.561073, 0.742608, 0.938257, 1.247576, 1.842569",\ + "0.609098, 0.790634, 0.986283, 1.295602, 1.890596",\ + "0.774407, 0.955942, 1.151591, 1.460911, 2.055906",\ + "1.364015, 1.545550, 1.741300, 2.050663, 2.645674",\ + "0.596701, 0.778434, 0.974083, 1.283183, 1.877821",\ + "0.618712, 0.800445, 0.995992, 1.305047, 1.899666",\ + "0.666737, 0.848471, 1.044018, 1.353073, 1.947692",\ + "0.832046, 1.013779, 1.209326, 1.518381, 2.113003",\ + "1.421654, 1.603387, 1.799036, 2.108135, 2.702771",\ + "0.898796, 1.083812, 1.277747, 1.586390, 2.180140",\ + "0.920807, 1.105823, 1.299656, 1.608254, 2.201985",\ + "0.968832, 1.153849, 1.347681, 1.656280, 2.250011",\ + "1.134141, 1.319157, 1.512989, 1.821589, 2.415322",\ + "1.723749, 1.908765, 2.102699, 2.411342, 3.005090"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064462",\ + "0.142275, 0.142275, 0.142275, 0.142276, 0.142277",\ + "0.443177, 0.443177, 0.443178, 0.443184, 0.443197",\ + "1.518758, 1.518758, 1.518758, 1.518759, 1.518761"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2318*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.503875, 0.682214, 0.862561, 1.148748, 1.699501",\ + "0.532852, 0.711192, 0.891538, 1.177725, 1.728478",\ + "0.604005, 0.782344, 0.962691, 1.248877, 1.799630",\ + "0.859730, 1.038069, 1.218416, 1.504603, 2.055356",\ + "1.770448, 1.948787, 2.129134, 2.415321, 2.966074",\ + "0.588813, 0.767050, 0.947631, 1.234254, 1.785879",\ + "0.617791, 0.796027, 0.976608, 1.263231, 1.814857",\ + "0.688943, 0.867180, 1.047761, 1.334384, 1.886009",\ + "0.944668, 1.122905, 1.303486, 1.590109, 2.141734",\ + "1.855386, 2.033623, 2.214204, 2.500827, 3.052452",\ + "0.664719, 0.842493, 1.022440, 1.308851, 1.860052",\ + "0.693697, 0.871471, 1.051417, 1.337828, 1.889029",\ + "0.764849, 0.942623, 1.122570, 1.408980, 1.960181",\ + "1.020574, 1.198349, 1.378295, 1.664706, 2.215907",\ + "1.931292, 2.109066, 2.289013, 2.575424, 3.126625",\ + "0.719071, 0.897239, 1.077305, 1.363444, 1.914369",\ + "0.748049, 0.926216, 1.106283, 1.392421, 1.943346",\ + "0.819201, 0.997369, 1.177435, 1.463574, 2.014498",\ + "1.074926, 1.253094, 1.433160, 1.719299, 2.270224",\ + "1.985644, 2.163812, 2.343878, 2.630017, 3.180942",\ + "1.000493, 1.182756, 1.361458, 1.647171, 2.197646",\ + "1.029471, 1.211734, 1.390436, 1.676148, 2.226624",\ + "1.100623, 1.282886, 1.461588, 1.747300, 2.297776",\ + "1.356348, 1.538611, 1.717313, 2.003026, 2.553502",\ + "2.267066, 2.449329, 2.628031, 2.913743, 3.464219"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223",\ + "0.042748, 0.042748, 0.042748, 0.042748, 0.042748",\ + "0.089888, 0.089888, 0.089888, 0.089888, 0.089888",\ + "0.222179, 0.222179, 0.222179, 0.222179, 0.222179",\ + "0.711766, 0.711766, 0.711766, 0.711766, 0.711766",\ + "2.448223, 2.448223, 2.448223, 2.448223, 2.448223"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.388047, 0.653046, 0.912076, 1.348340, 2.220486",\ + "0.410058, 0.675057, 0.934076, 1.370306, 2.242383",\ + "0.458083, 0.723083, 0.982102, 1.418332, 2.290410",\ + "0.623392, 0.888391, 1.147410, 1.583640, 2.455718",\ + "1.213000, 1.477999, 1.737028, 2.173293, 3.045439",\ + "0.476712, 0.741121, 1.000716, 1.436569, 2.307892",\ + "0.498723, 0.763132, 1.022717, 1.458535, 2.329789",\ + "0.546749, 0.811157, 1.070743, 1.506561, 2.377815",\ + "0.712057, 0.976466, 1.236051, 1.671869, 2.543123",\ + "1.301665, 1.566074, 1.825669, 2.261521, 3.132844",\ + "0.569519, 0.834415, 1.092752, 1.528812, 2.400934",\ + "0.591530, 0.856425, 1.114753, 1.550778, 2.422831",\ + "0.639556, 0.904451, 1.162778, 1.598804, 2.470856",\ + "0.804864, 1.069759, 1.328087, 1.764112, 2.636164",\ + "1.394472, 1.659367, 1.917704, 2.353765, 3.225886",\ + "0.635242, 0.902949, 1.159807, 1.595819, 2.467843",\ + "0.657252, 0.924959, 1.181808, 1.617785, 2.489740",\ + "0.705278, 0.972985, 1.229833, 1.665811, 2.537766",\ + "0.870586, 1.138293, 1.395142, 1.831119, 2.703074",\ + "1.460194, 1.727901, 1.984760, 2.420771, 3.292796",\ + "0.981031, 1.283447, 1.530445, 1.965020, 2.834170",\ + "1.003042, 1.305458, 1.552445, 1.986986, 2.856067",\ + "1.051068, 1.353484, 1.600471, 2.035012, 2.904093",\ + "1.216376, 1.518792, 1.765779, 2.200320, 3.069401",\ + "1.805984, 2.108400, 2.355398, 2.789973, 3.659123"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758",\ + "0.035640, 0.035640, 0.035640, 0.035640, 0.035640",\ + "0.064460, 0.064460, 0.064460, 0.064460, 0.064460",\ + "0.142275, 0.142275, 0.142275, 0.142275, 0.142275",\ + "0.443177, 0.443177, 0.443177, 0.443177, 0.443178",\ + "1.518758, 1.518758, 1.518758, 1.518758, 1.518758"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min_2260*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.141425, 0.170720, 0.242339, 0.498612, 1.411098",\ + "0.229610, 0.258905, 0.330536, 0.586854, 1.499024",\ + "0.317934, 0.347229, 0.418864, 0.675374, 1.587106",\ + "0.380526, 0.409818, 0.481403, 0.738206, 1.650402",\ + "0.710407, 0.739695, 0.811101, 1.068343, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\ + "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\ + "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\ + "0.042748, 0.089888, 0.222179, 0.711766, 2.448223",\ + "0.042748, 0.089888, 0.222179, 0.711766, 2.448223"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.179776, 0.202485, 0.251521, 0.417224, 1.003880",\ + "0.267179, 0.289888, 0.338925, 0.504627, 1.091283",\ + "0.348077, 0.370784, 0.419825, 0.585531, 1.172197",\ + "0.405741, 0.428442, 0.477491, 0.643206, 1.229887",\ + "0.708098, 0.730789, 0.779867, 0.945650, 1.532504"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.035639, 0.064458, 0.142274, 0.442345, 1.516474",\ + "0.035639, 0.064458, 0.142274, 0.442345, 1.516474",\ + "0.035639, 0.064458, 0.142274, 0.442391, 1.516474",\ + "0.035639, 0.064458, 0.142274, 0.442476, 1.516474",\ + "0.035639, 0.064458, 0.142274, 0.443177, 1.516474"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.454726, 0.454726, 0.454726, 0.454726, 0.454726",\ + "0.473076, 0.473076, 0.473076, 0.473076, 0.473076",\ + "0.545703, 0.545703, 0.545703, 0.545703, 0.545703",\ + "0.640171, 0.640171, 0.640171, 0.640171, 0.640171",\ + "1.087704, 1.087704, 1.087704, 1.087704, 1.087704"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.201983, 0.201983, 0.201983, 0.201983, 0.201983",\ + "0.219410, 0.219410, 0.219410, 0.219410, 0.219410",\ + "0.296741, 0.296741, 0.296741, 0.296741, 0.296741",\ + "0.405665, 0.405665, 0.405665, 0.405665, 0.405665",\ + "0.925258, 0.925258, 0.925258, 0.925258, 0.925258"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_cgsf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.450859, -0.450859, -0.450859, -0.450859, -0.450859",\ + "-0.467474, -0.467474, -0.467474, -0.467474, -0.467474",\ + "-0.541835, -0.541835, -0.541835, -0.541835, -0.541835",\ + "-0.636302, -0.636302, -0.636302, -0.636302, -0.636302",\ + "-1.083807, -1.083807, -1.083807, -1.083807, -1.083807"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.194280, -0.194280, -0.194280, -0.194280, -0.194280",\ + "-0.207626, -0.207626, -0.207626, -0.207626, -0.207626",\ + "-0.289038, -0.289038, -0.289038, -0.289038, -0.289038",\ + "-0.398036, -0.398036, -0.398036, -0.398036, -0.398036",\ + "-0.918416, -0.918416, -0.918416, -0.918416, -0.918416"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[8]_cghr*/ + + timing () { + related_pin : "padmux2ast_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.088658, 0.118400, 0.189731, 0.445655, 1.359203",\ + "0.176289, 0.206081, 0.277284, 0.533409, 1.444562",\ + "0.273999, 0.305373, 0.377262, 0.633109, 1.547694",\ + "0.451720, 0.486942, 0.560777, 0.816366, 1.732299",\ + "0.754684, 0.801348, 0.884176, 1.139736, 2.048527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.044533, 0.091199, 0.223344, 0.717968, 2.481454",\ + "0.045427, 0.091448, 0.223344, 0.719590, 2.481454",\ + "0.052404, 0.096040, 0.223344, 0.719590, 2.481454",\ + "0.069791, 0.108505, 0.227261, 0.719590, 2.481454",\ + "0.113693, 0.145215, 0.245785, 0.719590, 2.481454"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.127074, 0.151791, 0.203016, 0.369861, 0.957397",\ + "0.206135, 0.230814, 0.281980, 0.448797, 1.035129",\ + "0.309463, 0.335921, 0.388109, 0.554820, 1.143022",\ + "0.486985, 0.519573, 0.577173, 0.745365, 1.332651",\ + "0.774720, 0.823340, 0.896308, 1.069995, 1.655274"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.044476, 0.073631, 0.149535, 0.448052, 1.525218",\ + "0.044476, 0.073631, 0.149535, 0.448052, 1.525218",\ + "0.053117, 0.079360, 0.152226, 0.448052, 1.525218",\ + "0.080664, 0.102519, 0.166108, 0.450694, 1.525218",\ + "0.138236, 0.160233, 0.212368, 0.461268, 1.526869"); + } + + } /* end of arc padmux2ast_i[0]_obs_ctrl_o[8]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.084296, 0.113120, 0.184192, 0.440347, 1.352120",\ + "0.171472, 0.200589, 0.271545, 0.528022, 1.439207",\ + "0.267978, 0.297935, 0.369614, 0.625313, 1.536303",\ + "0.442024, 0.475873, 0.548072, 0.804727, 1.718362",\ + "0.738029, 0.782075, 0.862420, 1.115871, 2.025527"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.041900, 0.089823, 0.221979, 0.709338, 2.440521",\ + "0.043039, 0.090167, 0.221979, 0.709338, 2.440521",\ + "0.049089, 0.094012, 0.222641, 0.712232, 2.449750",\ + "0.065208, 0.105222, 0.226678, 0.712232, 2.460771",\ + "0.105185, 0.140977, 0.242589, 0.716067, 2.462313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.092809, 0.114931, 0.163305, 0.328814, 0.916983",\ + "0.177889, 0.200026, 0.248421, 0.413754, 1.001155",\ + "0.277335, 0.302085, 0.352052, 0.517221, 1.105053",\ + "0.446489, 0.478335, 0.533931, 0.699176, 1.285565",\ + "0.721488, 0.769874, 0.842559, 1.014698, 1.597625"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001401, 0.004640, 0.013222, 0.044537, 0.156168"); + values ( "0.036394, 0.065440, 0.142870, 0.442805, 1.519686",\ + "0.037274, 0.065647, 0.143061, 0.444080, 1.520298",\ + "0.048413, 0.073856, 0.146810, 0.444683, 1.520298",\ + "0.075564, 0.097153, 0.160320, 0.447782, 1.520312",\ + "0.132225, 0.154160, 0.206470, 0.457474, 1.523023"); + } + + } /* end of arc padmux2ast_i[0]_obs_ctrl_o[8]_una_min*/ + +} /* end of pin obs_ctrl_o[8] */ + +pin("obs_ctrl_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.094370 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001120 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.560132, 0.740335, 0.927825, 1.229818, 1.813330",\ + "0.598058, 0.778261, 0.965751, 1.267744, 1.851256",\ + "0.679713, 0.859917, 1.047406, 1.349399, 1.932911",\ + "0.950162, 1.130366, 1.317855, 1.619848, 2.203360",\ + "1.836798, 2.017001, 2.204491, 2.506483, 3.089995",\ + "0.645071, 0.825618, 1.013834, 1.315830, 1.899708",\ + "0.682997, 0.863544, 1.051760, 1.353756, 1.937634",\ + "0.764652, 0.945200, 1.133415, 1.435411, 2.019289",\ + "1.035101, 1.215649, 1.403864, 1.705860, 2.289738",\ + "1.921736, 2.102284, 2.290499, 2.592495, 3.176373",\ + "0.720983, 0.901062, 1.088643, 1.390427, 1.973880",\ + "0.758909, 0.938988, 1.126569, 1.428353, 2.011806",\ + "0.840564, 1.020643, 1.208224, 1.510008, 2.093462",\ + "1.111013, 1.291092, 1.478673, 1.780457, 2.363911",\ + "1.997648, 2.177727, 2.365308, 2.667092, 3.250545",\ + "0.775352, 0.955573, 1.143294, 1.444967, 2.028198",\ + "0.813278, 0.993499, 1.181220, 1.482893, 2.066123",\ + "0.894933, 1.075155, 1.262875, 1.564548, 2.147779",\ + "1.165382, 1.345604, 1.533324, 1.834997, 2.418228",\ + "2.052018, 2.232239, 2.419959, 2.721632, 3.304862",\ + "1.056947, 1.240841, 1.427244, 1.728693, 2.311475",\ + "1.094873, 1.278767, 1.465170, 1.766619, 2.349401",\ + "1.176528, 1.360423, 1.546826, 1.848274, 2.431056",\ + "1.446977, 1.630872, 1.817275, 2.118723, 2.701505",\ + "2.333612, 2.517507, 2.703910, 3.005358, 3.588140"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.442149, 0.709934, 0.971514, 1.411211, 2.290606",\ + "0.473003, 0.740789, 1.002369, 1.442066, 2.321460",\ + "0.534512, 0.802297, 1.063877, 1.503574, 2.382968",\ + "0.730402, 0.998188, 1.259768, 1.699465, 2.578859",\ + "1.368610, 1.636396, 1.897976, 2.337672, 3.217067",\ + "0.530853, 0.798009, 1.060155, 1.499440, 2.378011",\ + "0.561708, 0.828864, 1.091010, 1.530295, 2.408865",\ + "0.623216, 0.890372, 1.152518, 1.591803, 2.470374",\ + "0.819106, 1.086263, 1.348409, 1.787694, 2.666264",\ + "1.457314, 1.724471, 1.986617, 2.425902, 3.304472",\ + "0.623795, 0.891154, 1.151881, 1.591604, 2.471052",\ + "0.654650, 0.922009, 1.182735, 1.622459, 2.501907",\ + "0.716158, 0.983517, 1.244244, 1.683967, 2.563416",\ + "0.912048, 1.179408, 1.440134, 1.879858, 2.759306",\ + "1.550256, 1.817616, 2.078342, 2.518066, 3.397514",\ + "0.689639, 0.959719, 1.218900, 1.658455, 2.537564",\ + "0.720493, 0.990574, 1.249755, 1.689310, 2.568418",\ + "0.782001, 1.052082, 1.311263, 1.750818, 2.629927",\ + "0.977892, 1.247972, 1.507154, 1.946708, 2.825817",\ + "1.616100, 1.886180, 2.145362, 2.584916, 3.464025",\ + "1.036160, 1.340554, 1.589563, 2.027608, 2.903699",\ + "1.067015, 1.371409, 1.620418, 2.058463, 2.934554",\ + "1.128523, 1.432917, 1.681926, 2.119972, 2.996062",\ + "1.324414, 1.628808, 1.877817, 2.315862, 3.191953",\ + "1.962622, 2.267016, 2.516025, 2.954070, 3.830161"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2746*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.468238, 0.731811, 1.008084, 1.476814, 2.414274",\ + "0.506163, 0.769737, 1.046010, 1.514740, 2.452199",\ + "0.587819, 0.851392, 1.127665, 1.596395, 2.533855",\ + "0.858268, 1.121841, 1.398114, 1.866844, 2.804303",\ + "1.744903, 2.008476, 2.284747, 2.753474, 3.690928",\ + "0.556432, 0.819352, 1.095652, 1.563529, 2.500207",\ + "0.594358, 0.857278, 1.133578, 1.601455, 2.538133",\ + "0.676013, 0.938933, 1.215233, 1.683110, 2.619789",\ + "0.946462, 1.209382, 1.485682, 1.953559, 2.890237",\ + "1.833097, 2.096017, 2.372314, 2.840189, 3.776862",\ + "0.644748, 0.908332, 1.183617, 1.651152, 2.587162",\ + "0.682674, 0.946258, 1.221542, 1.689077, 2.625088",\ + "0.764329, 1.027914, 1.303198, 1.770733, 2.706744",\ + "1.034778, 1.298362, 1.573647, 2.041182, 2.977192",\ + "1.921414, 2.184997, 2.460279, 2.927812, 3.863817",\ + "0.707244, 0.973967, 1.247756, 1.715065, 2.650671",\ + "0.745170, 1.011893, 1.285682, 1.752991, 2.688597",\ + "0.826825, 1.093549, 1.367337, 1.834647, 2.770253",\ + "1.097274, 1.363997, 1.637786, 2.105095, 3.040701",\ + "1.983909, 2.250632, 2.524419, 2.991725, 3.927326",\ + "1.036370, 1.338298, 1.599624, 2.064415, 2.996128",\ + "1.074296, 1.376224, 1.637549, 2.102341, 3.034053",\ + "1.155951, 1.457879, 1.719205, 2.183996, 3.115709",\ + "1.426400, 1.728328, 1.989653, 2.454445, 3.386157",\ + "2.313035, 2.614962, 2.876286, 3.341075, 4.272782"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268819",\ + "0.790040, 0.790040, 0.790040, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.425102, 0.607534, 0.803925, 1.112984, 1.707807",\ + "0.455957, 0.638388, 0.834779, 1.143839, 1.738662",\ + "0.517465, 0.699897, 0.896288, 1.205346, 1.800168",\ + "0.713355, 0.895787, 1.092178, 1.401236, 1.996057",\ + "1.351563, 1.533995, 1.730386, 2.039446, 2.634272",\ + "0.512517, 0.694919, 0.891418, 1.200289, 1.795161",\ + "0.543371, 0.725774, 0.922273, 1.231144, 1.826015",\ + "0.604879, 0.787282, 0.983781, 1.292651, 1.887522",\ + "0.800770, 0.983173, 1.179671, 1.488541, 2.083410",\ + "1.438978, 1.621381, 1.817879, 2.126751, 2.721625",\ + "0.593393, 0.775256, 0.971445, 1.280318, 1.875192",\ + "0.624248, 0.806111, 1.002299, 1.311172, 1.906047",\ + "0.685756, 0.867619, 1.063808, 1.372680, 1.967553",\ + "0.881646, 1.063509, 1.259698, 1.568570, 2.163442",\ + "1.519854, 1.701717, 1.897906, 2.206779, 2.801657",\ + "0.651039, 0.832804, 1.028988, 1.337563, 1.931840",\ + "0.681894, 0.863659, 1.059843, 1.368417, 1.962695",\ + "0.743402, 0.925167, 1.121351, 1.429925, 2.024201",\ + "0.939293, 1.121058, 1.317242, 1.625815, 2.220089",\ + "1.577501, 1.759266, 1.955450, 2.264025, 2.858304",\ + "0.953247, 1.138029, 1.332622, 1.640577, 2.233686",\ + "0.984102, 1.168883, 1.363477, 1.671432, 2.264541",\ + "1.045610, 1.230392, 1.424985, 1.732940, 2.326047",\ + "1.241500, 1.426282, 1.620876, 1.928830, 2.521936",\ + "1.879708, 2.064490, 2.259084, 2.567039, 3.160151"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092504",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549208, 0.549211",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718751"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2673*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.464262, 0.723892, 0.995764, 1.452644, 2.366404",\ + "0.502188, 0.761817, 1.033690, 1.490570, 2.404330",\ + "0.583843, 0.843473, 1.115345, 1.572225, 2.485985",\ + "0.854292, 1.113922, 1.385794, 1.842674, 2.756433",\ + "1.740928, 2.000556, 2.272425, 2.729303, 3.643060",\ + "0.552367, 0.811425, 1.083295, 1.539359, 2.452338",\ + "0.590293, 0.849351, 1.121220, 1.577285, 2.490263",\ + "0.671948, 0.931006, 1.202876, 1.658941, 2.571919",\ + "0.942397, 1.201455, 1.473325, 1.929389, 2.842367",\ + "1.829032, 2.088089, 2.359956, 2.816019, 3.728994",\ + "0.640397, 0.900391, 1.171259, 1.626982, 2.539293",\ + "0.678323, 0.938317, 1.209185, 1.664908, 2.577219",\ + "0.759978, 1.019972, 1.290840, 1.746563, 2.658874",\ + "1.030427, 1.290421, 1.561289, 2.017012, 2.929322",\ + "1.917063, 2.177055, 2.447920, 2.903641, 3.815949",\ + "0.702618, 0.966004, 1.235397, 1.690896, 2.602802",\ + "0.740544, 1.003930, 1.273322, 1.728822, 2.640728",\ + "0.822200, 1.085586, 1.354978, 1.810477, 2.722383",\ + "1.092649, 1.356035, 1.625427, 2.080925, 2.992831",\ + "1.979284, 2.242668, 2.512058, 2.967555, 3.879458",\ + "1.030006, 1.330079, 1.587144, 2.040197, 2.948258",\ + "1.067932, 1.368005, 1.625070, 2.078122, 2.986184",\ + "1.149587, 1.449661, 1.706725, 2.159778, 3.067839",\ + "1.420036, 1.720109, 1.977174, 2.430226, 3.338287",\ + "2.306671, 2.606743, 2.863805, 3.316856, 4.224914"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268819, 0.268818",\ + "0.790040, 0.790040, 0.790039, 0.790039, 0.790038",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468304"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.423440, 0.605981, 0.802235, 1.111459, 1.706773",\ + "0.454295, 0.636836, 0.833090, 1.142314, 1.737628",\ + "0.515803, 0.698344, 0.894598, 1.203821, 1.799134",\ + "0.711694, 0.894235, 1.090489, 1.399711, 1.995022",\ + "1.349902, 1.532443, 1.728697, 2.037921, 2.633238",\ + "0.510860, 0.693367, 0.889728, 1.198764, 1.794126",\ + "0.541715, 0.724221, 0.920583, 1.229619, 1.824981",\ + "0.603223, 0.785730, 0.982091, 1.291126, 1.886487",\ + "0.799114, 0.981620, 1.177981, 1.487016, 2.082375",\ + "1.437322, 1.619828, 1.816189, 2.125226, 2.720591",\ + "0.591728, 0.773704, 0.969755, 1.278793, 1.874158",\ + "0.622583, 0.804558, 1.000610, 1.309647, 1.905013",\ + "0.684091, 0.866066, 1.062118, 1.371155, 1.966519",\ + "0.879981, 1.061957, 1.258008, 1.567045, 2.162407",\ + "1.518189, 1.700165, 1.896216, 2.205255, 2.800623",\ + "0.649367, 0.831252, 1.027299, 1.336038, 1.930805",\ + "0.680222, 0.862107, 1.058154, 1.366893, 1.961660",\ + "0.741730, 0.923615, 1.119662, 1.428400, 2.023166",\ + "0.937620, 1.119505, 1.315552, 1.624290, 2.219054",\ + "1.575828, 1.757713, 1.953760, 2.262500, 2.857270",\ + "0.951462, 1.136478, 1.330933, 1.639053, 2.232652",\ + "0.982317, 1.167333, 1.361788, 1.669907, 2.263507",\ + "1.043825, 1.228841, 1.423296, 1.731415, 2.325013",\ + "1.239715, 1.424732, 1.619186, 1.927305, 2.520901",\ + "1.877923, 2.062940, 2.257394, 2.565515, 3.159117"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753",\ + "0.050922, 0.050922, 0.050922, 0.050923, 0.050926",\ + "0.092496, 0.092496, 0.092497, 0.092499, 0.092505",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193182",\ + "0.549207, 0.549207, 0.549207, 0.549209, 0.549212",\ + "1.718736, 1.718736, 1.718736, 1.718741, 1.718753"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2611*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.556546, 0.734973, 0.915233, 1.201439, 1.752556",\ + "0.594472, 0.772898, 0.953159, 1.239365, 1.790482",\ + "0.676127, 0.854554, 1.034814, 1.321021, 1.872138",\ + "0.946576, 1.125003, 1.305263, 1.591470, 2.142586",\ + "1.833212, 2.011638, 2.191898, 2.478105, 3.029221",\ + "0.641484, 0.820245, 1.001148, 1.287360, 1.838935",\ + "0.679410, 0.858171, 1.039074, 1.325286, 1.876861",\ + "0.761066, 0.939826, 1.120729, 1.406941, 1.958516",\ + "1.031515, 1.210275, 1.391178, 1.677390, 2.228965",\ + "1.918150, 2.096910, 2.277814, 2.564025, 3.115599",\ + "0.717390, 0.895688, 1.075957, 1.361957, 1.913107",\ + "0.755316, 0.933614, 1.113883, 1.399882, 1.951033",\ + "0.836972, 1.015270, 1.195538, 1.481538, 2.032688",\ + "1.107421, 1.285719, 1.465987, 1.751987, 2.303137",\ + "1.994056, 2.172354, 2.352623, 2.638622, 3.189771",\ + "0.771742, 0.950200, 1.130608, 1.416496, 1.967424",\ + "0.809668, 0.988126, 1.168534, 1.454422, 2.005350",\ + "0.891324, 1.069781, 1.250189, 1.536077, 2.087006",\ + "1.161773, 1.340230, 1.520638, 1.806526, 2.357455",\ + "2.048408, 2.226866, 2.407274, 2.693161, 3.244089",\ + "1.053164, 1.235427, 1.414559, 1.700223, 2.250702",\ + "1.091090, 1.273353, 1.452485, 1.738148, 2.288628",\ + "1.172746, 1.355009, 1.534140, 1.819804, 2.370283",\ + "1.443195, 1.625458, 1.804589, 2.090253, 2.640732",\ + "2.329830, 2.512093, 2.691224, 2.976888, 3.527366"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303",\ + "0.060311, 0.060311, 0.060311, 0.060311, 0.060311",\ + "0.120043, 0.120043, 0.120043, 0.120043, 0.120043",\ + "0.268820, 0.268820, 0.268820, 0.268820, 0.268820",\ + "0.790040, 0.790040, 0.790040, 0.790040, 0.790040",\ + "2.468303, 2.468303, 2.468303, 2.468303, 2.468303"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.440713, 0.705883, 0.965084, 1.401266, 2.273631",\ + "0.471568, 0.736737, 0.995939, 1.432121, 2.304486",\ + "0.533076, 0.798245, 1.057447, 1.493629, 2.365994",\ + "0.728966, 0.994136, 1.253338, 1.689520, 2.561884",\ + "1.367174, 1.632344, 1.891546, 2.327728, 3.200092",\ + "0.529378, 0.793957, 1.053725, 1.489495, 2.361036",\ + "0.560233, 0.824812, 1.084580, 1.520350, 2.391891",\ + "0.621741, 0.886320, 1.146088, 1.581858, 2.453399",\ + "0.817632, 1.082211, 1.341978, 1.777749, 2.649290",\ + "1.455840, 1.720419, 1.980186, 2.415956, 3.287497",\ + "0.622185, 0.887080, 1.145450, 1.581659, 2.454078",\ + "0.653040, 0.917935, 1.176305, 1.612514, 2.484932",\ + "0.714548, 0.979443, 1.237813, 1.674022, 2.546441",\ + "0.910438, 1.175334, 1.433704, 1.869913, 2.742332",\ + "1.548646, 1.813542, 2.071912, 2.508121, 3.380539",\ + "0.687908, 0.955615, 1.212470, 1.648510, 2.520589",\ + "0.718762, 0.986469, 1.243325, 1.679364, 2.551444",\ + "0.780270, 1.047977, 1.304833, 1.740873, 2.612952",\ + "0.976161, 1.243868, 1.500724, 1.936763, 2.808843",\ + "1.614369, 1.882076, 2.138932, 2.574971, 3.447050",\ + "1.033697, 1.336113, 1.583101, 2.017641, 2.886722",\ + "1.064552, 1.366968, 1.613955, 2.048496, 2.917577",\ + "1.126060, 1.428476, 1.675463, 2.110004, 2.979085",\ + "1.321950, 1.624366, 1.871354, 2.305894, 3.174975",\ + "1.960158, 2.262574, 2.509562, 2.944102, 3.813183"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736",\ + "0.050922, 0.050922, 0.050922, 0.050922, 0.050922",\ + "0.092496, 0.092496, 0.092496, 0.092496, 0.092497",\ + "0.193181, 0.193181, 0.193181, 0.193181, 0.193181",\ + "0.549207, 0.549207, 0.549207, 0.549207, 0.549207",\ + "1.718736, 1.718736, 1.718736, 1.718736, 1.718736"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_2557*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380001.875000, 380001.906250, 380002.000000, 380002.250000, 380003.156250",\ + "380001.968750, 380002.000000, 380002.093750, 380002.343750, 380003.250000",\ + "380002.031250, 380002.062500, 380002.156250, 380002.406250, 380003.312500",\ + "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.781250, 380003.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.060312, 0.120043, 0.268889, 0.790048, 2.471058",\ + "0.060312, 0.120043, 0.268889, 0.790048, 2.471058",\ + "0.060312, 0.120043, 0.268889, 0.790048, 2.471058",\ + "0.060311, 0.120043, 0.268889, 0.790048, 2.471058",\ + "0.060311, 0.120043, 0.268889, 0.790048, 2.468313"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380003.906250, 380003.937500, 380004.000000, 380004.187500, 380004.843750",\ + "380004.000000, 380004.031250, 380004.093750, 380004.281250, 380004.937500",\ + "380004.093750, 380004.125000, 380004.187500, 380004.375000, 380005.031250",\ + "380004.156250, 380004.187500, 380004.250000, 380004.437500, 380005.093750",\ + "380004.500000, 380004.531250, 380004.593750, 380004.781250, 380005.437500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\ + "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\ + "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\ + "0.050922, 0.092579, 0.193181, 0.549207, 1.721959",\ + "0.050984, 0.092651, 0.193203, 0.549286, 1.721959"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.544292, 0.724406, 0.911984, 1.213964, 1.797060",\ + "0.582447, 0.762561, 0.950139, 1.252119, 1.835215",\ + "0.664874, 0.844988, 1.032566, 1.334546, 1.917642",\ + "0.936033, 1.116146, 1.303725, 1.605704, 2.188801",\ + "1.821919, 2.002032, 2.189611, 2.491591, 3.074687",\ + "0.629231, 0.809242, 0.997054, 1.299470, 1.883439",\ + "0.667386, 0.847397, 1.035209, 1.337625, 1.921593",\ + "0.749812, 0.929824, 1.117636, 1.420052, 2.004020",\ + "1.020971, 1.200982, 1.388795, 1.691211, 2.275179",\ + "1.906857, 2.086868, 2.274681, 2.577097, 3.161065",\ + "0.705143, 0.884685, 1.071863, 1.374067, 1.957611",\ + "0.743298, 0.922840, 1.110018, 1.412222, 1.995766",\ + "0.825724, 1.005267, 1.192445, 1.494649, 2.078193",\ + "1.096883, 1.276425, 1.463604, 1.765808, 2.349351",\ + "1.982769, 2.162312, 2.349490, 2.651694, 3.235237",\ + "0.759512, 0.939436, 1.126752, 1.428673, 2.011928",\ + "0.797667, 0.977591, 1.164907, 1.466828, 2.050083",\ + "0.880094, 1.060018, 1.247334, 1.549255, 2.132510",\ + "1.151252, 1.331177, 1.518492, 1.820413, 2.403668",\ + "2.037138, 2.217063, 2.404379, 2.706299, 3.289555",\ + "1.041107, 1.225001, 1.410928, 1.712399, 2.295206",\ + "1.079262, 1.263156, 1.449083, 1.750554, 2.333361",\ + "1.161688, 1.345583, 1.531509, 1.832981, 2.415788",\ + "1.432847, 1.616742, 1.802668, 2.104139, 2.686946",\ + "2.318733, 2.502628, 2.688554, 2.990026, 3.572832"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446672"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.363069, 0.630679, 0.892080, 1.331857, 2.211017",\ + "0.391013, 0.658624, 0.920025, 1.359801, 2.238962",\ + "0.450465, 0.718075, 0.979476, 1.419253, 2.298413",\ + "0.646065, 0.913676, 1.175077, 1.614853, 2.494013",\ + "1.283402, 1.551012, 1.812413, 2.252190, 3.131351",\ + "0.451773, 0.718754, 0.980721, 1.420086, 2.298422",\ + "0.479717, 0.746699, 1.008666, 1.448030, 2.326367",\ + "0.539169, 0.806150, 1.068117, 1.507482, 2.385818",\ + "0.734769, 1.001751, 1.263718, 1.703082, 2.581419",\ + "1.372106, 1.639087, 1.901054, 2.340420, 3.218756",\ + "0.544715, 0.812075, 1.072766, 1.512332, 2.391464",\ + "0.572660, 0.840019, 1.100710, 1.540276, 2.419409",\ + "0.632111, 0.899470, 1.160161, 1.599728, 2.478860",\ + "0.827712, 1.095071, 1.355762, 1.795328, 2.674460",\ + "1.465048, 1.732408, 1.993099, 2.432665, 3.311798",\ + "0.610559, 0.880639, 1.139822, 1.579343, 2.458386",\ + "0.638503, 0.908583, 1.167766, 1.607288, 2.486331",\ + "0.697955, 0.968035, 1.227218, 1.666739, 2.545782",\ + "0.893555, 1.163635, 1.422818, 1.862339, 2.741382",\ + "1.530892, 1.800972, 2.060155, 2.499676, 3.378720",\ + "0.957080, 1.261474, 1.510493, 1.948569, 2.824721",\ + "0.985025, 1.289419, 1.538437, 1.976513, 2.852666",\ + "1.044476, 1.348870, 1.597888, 2.035964, 2.912117",\ + "1.240077, 1.544471, 1.793489, 2.231565, 3.107717",\ + "1.877413, 2.181808, 2.430826, 2.868902, 3.745055"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2500*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.452401, 0.715932, 0.992051, 1.460182, 2.395185",\ + "0.490556, 0.754087, 1.030206, 1.498337, 2.433340",\ + "0.572982, 0.836514, 1.112633, 1.580764, 2.515767",\ + "0.844141, 1.107672, 1.383791, 1.851923, 2.786925",\ + "1.730027, 1.993558, 2.269678, 2.737809, 3.672812",\ + "0.540595, 0.803472, 1.079618, 1.546898, 2.481119",\ + "0.578750, 0.841627, 1.117773, 1.585052, 2.519274",\ + "0.661177, 0.924054, 1.200200, 1.667479, 2.601700",\ + "0.932335, 1.195213, 1.471358, 1.938638, 2.872859",\ + "1.818222, 2.081099, 2.357244, 2.824524, 3.758746",\ + "0.628911, 0.892452, 1.167583, 1.634538, 2.568074",\ + "0.667066, 0.930607, 1.205738, 1.672693, 2.606229",\ + "0.749493, 1.013034, 1.288164, 1.755120, 2.688655",\ + "1.020651, 1.284192, 1.559323, 2.026278, 2.959814",\ + "1.906538, 2.170078, 2.445210, 2.912164, 3.845701",\ + "0.691407, 0.958086, 1.231722, 1.698627, 2.631583",\ + "0.729562, 0.996240, 1.269877, 1.736781, 2.669738",\ + "0.811989, 1.078667, 1.352304, 1.819208, 2.752164",\ + "1.083147, 1.349826, 1.623463, 2.090367, 3.023323",\ + "1.969034, 2.235712, 2.509349, 2.976254, 3.909210",\ + "1.020533, 1.322400, 1.583586, 2.048070, 2.977039",\ + "1.058688, 1.360555, 1.621741, 2.086226, 3.015194",\ + "1.141114, 1.442982, 1.704168, 2.168652, 3.097620",\ + "1.412273, 1.714141, 1.975327, 2.439811, 3.368779",\ + "2.298159, 2.600027, 2.861213, 3.325697, 4.254666"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446672, 2.446677, 2.446682, 2.446693",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446670, 2.446673, 2.446677, 2.446682, 2.446693"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.346024, 0.528081, 0.724314, 1.033489, 1.627960",\ + "0.373968, 0.556026, 0.752258, 1.061434, 1.655906",\ + "0.433420, 0.615477, 0.811710, 1.120886, 1.715360",\ + "0.629020, 0.811078, 1.007310, 1.316483, 1.910951",\ + "1.266357, 1.448414, 1.644648, 1.953829, 2.548313",\ + "0.433439, 0.615400, 0.811595, 1.120794, 1.715314",\ + "0.461383, 0.643345, 0.839539, 1.148739, 1.743259",\ + "0.520834, 0.702796, 0.898991, 1.208191, 1.802713",\ + "0.716435, 0.898396, 1.094591, 1.403789, 1.998304",\ + "1.353772, 1.535733, 1.731929, 2.041134, 2.635666",\ + "0.514315, 0.695737, 0.891622, 1.200823, 1.795345",\ + "0.542259, 0.723681, 0.919566, 1.228768, 1.823291",\ + "0.601711, 0.783132, 0.979018, 1.288220, 1.882745",\ + "0.797311, 0.978733, 1.174618, 1.483817, 2.078336",\ + "1.434648, 1.616070, 1.811956, 2.121162, 2.715698",\ + "0.571961, 0.753573, 0.949357, 1.258293, 1.852441",\ + "0.599906, 0.781518, 0.977302, 1.286238, 1.880386",\ + "0.659357, 0.840969, 1.036753, 1.345690, 1.939840",\ + "0.854958, 1.036570, 1.232353, 1.541288, 2.135431",\ + "1.492294, 1.673906, 1.869692, 2.178633, 2.772793",\ + "0.874169, 1.058951, 1.253021, 1.561500, 2.154759",\ + "0.902114, 1.086895, 1.280965, 1.589445, 2.182705",\ + "0.961565, 1.146346, 1.340417, 1.648897, 2.242158",\ + "1.157166, 1.341947, 1.536017, 1.844495, 2.437749",\ + "1.794502, 1.979284, 2.173355, 2.481840, 3.075111"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186770",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543845",\ + "1.713838, 1.713838, 1.713836, 1.713827, 1.713805"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2425*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.448423, 0.707982, 0.979616, 1.435777, 2.346942",\ + "0.486578, 0.746137, 1.017771, 1.473932, 2.385097",\ + "0.569004, 0.828563, 1.100198, 1.556358, 2.467524",\ + "0.840163, 1.099722, 1.371357, 1.827517, 2.738683",\ + "1.726049, 1.985608, 2.257243, 2.713404, 3.624570",\ + "0.536527, 0.795515, 1.067145, 1.522492, 2.432876",\ + "0.574682, 0.833670, 1.105300, 1.560647, 2.471031",\ + "0.657109, 0.916096, 1.187727, 1.643074, 2.553458",\ + "0.928268, 1.187255, 1.458886, 1.914232, 2.824616",\ + "1.814154, 2.073141, 2.344772, 2.800119, 3.710504",\ + "0.624558, 0.884479, 1.155110, 1.610131, 2.519831",\ + "0.662712, 0.922634, 1.193264, 1.648286, 2.557986",\ + "0.745139, 1.005061, 1.275691, 1.730713, 2.640413",\ + "1.016298, 1.276219, 1.546850, 2.001871, 2.911571",\ + "1.902184, 2.162105, 2.432736, 2.887758, 3.797459",\ + "0.686779, 0.950090, 1.219247, 1.674205, 2.583340",\ + "0.724934, 0.988245, 1.257402, 1.712360, 2.621495",\ + "0.807361, 1.070672, 1.339829, 1.794787, 2.703922",\ + "1.078519, 1.341830, 1.610988, 2.065946, 2.975080",\ + "1.964405, 2.227717, 2.496874, 2.951832, 3.860968",\ + "1.014166, 1.314139, 1.570990, 2.023592, 2.928796",\ + "1.052321, 1.352293, 1.609145, 2.061747, 2.966951",\ + "1.134748, 1.434720, 1.691572, 2.144174, 3.049378",\ + "1.405907, 1.705879, 1.962730, 2.415332, 3.320536",\ + "2.291793, 2.591765, 2.848617, 3.301219, 4.206424"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446674, 2.446680, 2.446683, 2.446690",\ + "0.050112, 0.050112, 0.050112, 0.050111, 0.050111",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112174",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446675, 2.446680, 2.446683, 2.446690"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.344360, 0.526527, 0.722625, 1.031957, 1.626903",\ + "0.372305, 0.554472, 0.750569, 1.059901, 1.654848",\ + "0.431756, 0.613923, 0.810021, 1.119354, 1.714302",\ + "0.627357, 0.809524, 1.005621, 1.314951, 1.909892",\ + "1.264693, 1.446861, 1.642959, 1.952297, 2.547257",\ + "0.431780, 0.613846, 0.809906, 1.119262, 1.714256",\ + "0.459725, 0.641791, 0.837850, 1.147207, 1.742202",\ + "0.519176, 0.701242, 0.897302, 1.206659, 1.801656",\ + "0.714777, 0.896843, 1.092902, 1.402256, 1.997246",\ + "1.352113, 1.534179, 1.730240, 2.039602, 2.634611",\ + "0.512648, 0.694183, 0.889933, 1.199290, 1.794288",\ + "0.540592, 0.722128, 0.917877, 1.227235, 1.822234",\ + "0.600044, 0.781579, 0.977328, 1.286687, 1.881687",\ + "0.795644, 0.977180, 1.172929, 1.482284, 2.077278",\ + "1.432981, 1.614516, 1.810267, 2.119630, 2.714642",\ + "0.570287, 0.752020, 0.947668, 1.256761, 1.851384",\ + "0.598231, 0.779964, 0.975612, 1.284706, 1.879330",\ + "0.657682, 0.839416, 1.035064, 1.344158, 1.938784",\ + "0.853283, 1.035016, 1.230664, 1.539755, 2.134374",\ + "1.490620, 1.672353, 1.868002, 2.177101, 2.771739",\ + "0.872382, 1.057398, 1.251331, 1.559969, 2.153704",\ + "0.900326, 1.085343, 1.279276, 1.587914, 2.181649",\ + "0.959778, 1.144794, 1.338727, 1.647366, 2.241103",\ + "1.155378, 1.340395, 1.534328, 1.842963, 2.436693",\ + "1.792715, 1.977731, 2.171666, 2.480309, 3.074058"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802",\ + "0.040709, 0.040709, 0.040708, 0.040708, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186773, 0.186772, 0.186769",\ + "0.543828, 0.543828, 0.543829, 0.543834, 0.543846",\ + "1.713838, 1.713838, 1.713836, 1.713826, 1.713802"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2354*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.540706, 0.719045, 0.899392, 1.185579, 1.736332",\ + "0.578861, 0.757200, 0.937547, 1.223734, 1.774487",\ + "0.661288, 0.839627, 1.019974, 1.306160, 1.856914",\ + "0.932446, 1.110786, 1.291132, 1.577319, 2.128072",\ + "1.818332, 1.996672, 2.177019, 2.463205, 3.013958",\ + "0.625644, 0.803881, 0.984462, 1.271085, 1.822710",\ + "0.663799, 0.842036, 1.022617, 1.309240, 1.860865",\ + "0.746226, 0.924463, 1.105044, 1.391667, 1.943292",\ + "1.017385, 1.195621, 1.376203, 1.662825, 2.214450",\ + "1.903271, 2.081508, 2.262089, 2.548712, 3.100337",\ + "0.701550, 0.879325, 1.059271, 1.345682, 1.896883",\ + "0.739705, 0.917479, 1.097426, 1.383837, 1.935037",\ + "0.822132, 0.999906, 1.179853, 1.466263, 2.017464",\ + "1.093291, 1.271065, 1.451011, 1.737422, 2.288623",\ + "1.979177, 2.156951, 2.336898, 2.623308, 3.174509",\ + "0.755902, 0.934070, 1.114136, 1.400275, 1.951200",\ + "0.794057, 0.972225, 1.152291, 1.438430, 1.989355",\ + "0.876484, 1.054652, 1.234718, 1.520857, 2.071782",\ + "1.147643, 1.325810, 1.505877, 1.792016, 2.342940",\ + "2.033529, 2.211697, 2.391763, 2.677902, 3.228827",\ + "1.037324, 1.219587, 1.398289, 1.684002, 2.234478",\ + "1.075479, 1.257742, 1.436444, 1.722157, 2.272632",\ + "1.157906, 1.340169, 1.518871, 1.804583, 2.355059",\ + "1.429065, 1.611328, 1.790030, 2.075742, 2.626218",\ + "2.314951, 2.497214, 2.675916, 2.961628, 3.512104"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673",\ + "0.050112, 0.050112, 0.050112, 0.050112, 0.050112",\ + "0.112175, 0.112175, 0.112175, 0.112175, 0.112175",\ + "0.264098, 0.264098, 0.264098, 0.264098, 0.264098",\ + "0.776079, 0.776079, 0.776079, 0.776079, 0.776079",\ + "2.446671, 2.446671, 2.446671, 2.446671, 2.446673"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.361633, 0.626632, 0.885661, 1.321925, 2.194071",\ + "0.389577, 0.654577, 0.913606, 1.349870, 2.222015",\ + "0.449029, 0.714028, 0.973057, 1.409321, 2.281467",\ + "0.644629, 0.909628, 1.168658, 1.604922, 2.477067",\ + "1.281966, 1.546965, 1.805995, 2.242259, 3.114405",\ + "0.450298, 0.714707, 0.974302, 1.410154, 2.281476",\ + "0.478243, 0.742651, 1.002247, 1.438099, 2.309421",\ + "0.537694, 0.802103, 1.061698, 1.497550, 2.368872",\ + "0.733295, 0.997703, 1.257299, 1.693150, 2.564472",\ + "1.370631, 1.635040, 1.894635, 2.330488, 3.201810",\ + "0.543105, 0.808000, 1.066338, 1.502398, 2.374518",\ + "0.571050, 0.835945, 1.094282, 1.530342, 2.402462",\ + "0.630501, 0.895396, 1.153733, 1.589793, 2.461914",\ + "0.826102, 1.090997, 1.349334, 1.785394, 2.657514",\ + "1.463438, 1.728334, 1.986671, 2.422731, 3.294852",\ + "0.608828, 0.876535, 1.133393, 1.569404, 2.441428",\ + "0.636772, 0.904479, 1.161337, 1.597349, 2.469372",\ + "0.696223, 0.963930, 1.220788, 1.656800, 2.528824",\ + "0.891824, 1.159531, 1.416389, 1.852400, 2.724424",\ + "1.529161, 1.796868, 2.053726, 2.489738, 3.361762",\ + "0.954617, 1.257033, 1.504031, 1.938605, 2.807755",\ + "0.982561, 1.284978, 1.531975, 1.966550, 2.835699",\ + "1.042013, 1.344429, 1.591426, 2.026001, 2.895151",\ + "1.237613, 1.540030, 1.787027, 2.221601, 3.090751",\ + "1.874950, 2.177366, 2.424364, 2.858939, 3.728089"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836",\ + "0.040709, 0.040709, 0.040709, 0.040709, 0.040708",\ + "0.082941, 0.082941, 0.082941, 0.082941, 0.082941",\ + "0.186774, 0.186774, 0.186774, 0.186774, 0.186773",\ + "0.543828, 0.543828, 0.543828, 0.543829, 0.543829",\ + "1.713838, 1.713838, 1.713838, 1.713837, 1.713836"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min_2300*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.138985, 0.175019, 0.256111, 0.526543, 1.410212",\ + "0.227168, 0.263197, 0.344286, 0.614601, 1.498111",\ + "0.315465, 0.351510, 0.432605, 0.702794, 1.585954",\ + "0.378070, 0.414099, 0.495228, 0.765687, 1.648712",\ + "0.707467, 0.743520, 0.824710, 1.095700, 1.978611"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.049671, 0.111941, 0.264026, 0.776079, 2.446670",\ + "0.049671, 0.111941, 0.264026, 0.776079, 2.446670",\ + "0.049671, 0.111941, 0.264026, 0.776079, 2.446670",\ + "0.049683, 0.111941, 0.264026, 0.776079, 2.446670",\ + "0.050112, 0.112175, 0.264026, 0.776079, 2.446670"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.157324, 0.185053, 0.244293, 0.439369, 1.077476",\ + "0.244729, 0.272457, 0.331698, 0.526774, 1.164879",\ + "0.325583, 0.353311, 0.412545, 0.607616, 1.245783",\ + "0.383167, 0.410894, 0.470117, 0.665176, 1.303456",\ + "0.684927, 0.712665, 0.771862, 0.966921, 1.606322"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.040467, 0.082696, 0.186546, 0.543770, 1.713948",\ + "0.040467, 0.082696, 0.186546, 0.543770, 1.713948",\ + "0.040467, 0.082696, 0.186546, 0.543770, 1.713916",\ + "0.040467, 0.082696, 0.186546, 0.543770, 1.713853",\ + "0.040452, 0.082696, 0.186546, 0.543770, 1.713838"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[7]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380001.750000, 380001.781250, 380001.875000, 380002.125000, 380003.031250",\ + "380001.843750, 380001.875000, 380001.968750, 380002.218750, 380003.125000",\ + "380001.937500, 380001.968750, 380002.062500, 380002.312500, 380003.218750",\ + "380002.093750, 380002.125000, 380002.218750, 380002.468750, 380003.375000",\ + "380002.343750, 380002.375000, 380002.468750, 380002.718750, 380003.625000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\ + "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\ + "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\ + "0.060263, 0.120010, 0.268885, 0.784134, 2.468360",\ + "0.060263, 0.120010, 0.268885, 0.784134, 2.468360"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380003.812500, 380003.843750, 380003.906250, 380004.093750, 380004.750000",\ + "380003.906250, 380003.937500, 380004.000000, 380004.187500, 380004.843750",\ + "380004.031250, 380004.062500, 380004.125000, 380004.312500, 380004.968750",\ + "380004.218750, 380004.250000, 380004.312500, 380004.500000, 380005.156250",\ + "380004.531250, 380004.562500, 380004.625000, 380004.812500, 380005.468750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\ + "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\ + "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\ + "0.050461, 0.092299, 0.192599, 0.548730, 1.719198",\ + "0.050461, 0.092299, 0.192599, 0.548730, 1.719198"); + } + + } /* end of arc padmux2ast_i[4]_obs_ctrl_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380001.718750, 380001.781250, 380001.843750, 380002.125000, 380003.000000",\ + "380001.812500, 380001.875000, 380001.937500, 380002.218750, 380003.093750",\ + "380001.875000, 380001.937500, 380002.000000, 380002.281250, 380003.156250",\ + "380002.031250, 380002.093750, 380002.156250, 380002.437500, 380003.312500",\ + "380002.250000, 380002.312500, 380002.375000, 380002.656250, 380003.531250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\ + "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\ + "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\ + "0.057179, 0.117947, 0.268265, 0.782312, 2.467599",\ + "0.057179, 0.117947, 0.268265, 0.782312, 2.467599"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "380003.781250, 380003.812500, 380003.875000, 380004.062500, 380004.718750",\ + "380003.875000, 380003.906250, 380003.968750, 380004.156250, 380004.812500",\ + "380003.968750, 380004.000000, 380004.062500, 380004.250000, 380004.906250",\ + "380004.156250, 380004.187500, 380004.250000, 380004.437500, 380005.093750",\ + "380004.406250, 380004.437500, 380004.500000, 380004.687500, 380005.343750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\ + "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\ + "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\ + "0.044680, 0.086652, 0.188447, 0.546028, 1.713947",\ + "0.044680, 0.086652, 0.188447, 0.546028, 1.713947"); + } + + } /* end of arc padmux2ast_i[4]_obs_ctrl_o[7]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.138119, 0.177193, 0.260095, 0.531430, 1.418639",\ + "0.215767, 0.254860, 0.337696, 0.608981, 1.495289",\ + "0.308294, 0.348212, 0.431364, 0.702849, 1.589224",\ + "0.484710, 0.527128, 0.611576, 0.883003, 1.767226",\ + "0.797982, 0.847958, 0.937201, 1.208546, 2.091260"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.060518, 0.120076, 0.268511, 0.784628, 2.471116",\ + "0.060518, 0.120081, 0.268991, 0.784628, 2.471116",\ + "0.064343, 0.122204, 0.269307, 0.784628, 2.471116",\ + "0.074832, 0.129870, 0.272085, 0.785309, 2.471116",\ + "0.105095, 0.152930, 0.282207, 0.790964, 2.471949"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.152585, 0.183883, 0.246071, 0.443151, 1.081549",\ + "0.241411, 0.272612, 0.334887, 0.531878, 1.170082",\ + "0.351515, 0.383367, 0.445997, 0.642143, 1.279910",\ + "0.559588, 0.595140, 0.660416, 0.857529, 1.494932",\ + "0.931509, 0.975339, 1.048816, 1.248062, 1.886353"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.051005, 0.093001, 0.193536, 0.550167, 1.721145",\ + "0.051005, 0.093079, 0.193536, 0.550167, 1.721145",\ + "0.053874, 0.094487, 0.193931, 0.550167, 1.721145",\ + "0.067061, 0.106340, 0.200874, 0.550167, 1.721145",\ + "0.100525, 0.137944, 0.221526, 0.555674, 1.721145"); + } + + } /* end of arc padmux2ast_i[7]_obs_ctrl_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.132088, 0.170250, 0.252738, 0.523558, 1.410267",\ + "0.209647, 0.247859, 0.330344, 0.601532, 1.487547",\ + "0.301602, 0.340448, 0.423118, 0.694391, 1.578063",\ + "0.475914, 0.516815, 0.600289, 0.871567, 1.757498",\ + "0.784086, 0.831711, 0.918475, 1.188577, 2.072675"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.057008, 0.117873, 0.266652, 0.780708, 2.463387",\ + "0.057108, 0.118176, 0.268442, 0.782366, 2.463387",\ + "0.060610, 0.120100, 0.268442, 0.782366, 2.463387",\ + "0.069995, 0.126826, 0.271258, 0.783468, 2.466000",\ + "0.096521, 0.148240, 0.280183, 0.788214, 2.471217"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.124161, 0.153974, 0.214961, 0.411830, 1.047717",\ + "0.215312, 0.245079, 0.306058, 0.501475, 1.140252",\ + "0.327970, 0.358765, 0.420242, 0.616480, 1.254494",\ + "0.533590, 0.569301, 0.634108, 0.830328, 1.467817",\ + "0.890972, 0.936721, 1.011690, 1.210135, 1.847934"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001120, 0.003635, 0.009556, 0.029416, 0.094370"); + values ( "0.045487, 0.087234, 0.188597, 0.544901, 1.712083",\ + "0.045487, 0.087327, 0.189348, 0.546097, 1.714089",\ + "0.050060, 0.090091, 0.189686, 0.546097, 1.714380",\ + "0.065339, 0.103967, 0.197580, 0.546097, 1.714380",\ + "0.095856, 0.132931, 0.220241, 0.552890, 1.714380"); + } + + } /* end of arc padmux2ast_i[7]_obs_ctrl_o[7]_una_min*/ + +} /* end of pin obs_ctrl_o[7] */ + +pin("obs_ctrl_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000997 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.556254, 0.736457, 0.923947, 1.225939, 1.809451",\ + "0.586838, 0.767041, 0.954531, 1.256524, 1.840036",\ + "0.658665, 0.838868, 1.026358, 1.328351, 1.911863",\ + "0.915124, 1.095327, 1.282817, 1.584810, 2.168322",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.641192, 0.821740, 1.009955, 1.311951, 1.895829",\ + "0.671777, 0.852324, 1.040540, 1.342536, 1.926414",\ + "0.743604, 0.924151, 1.112367, 1.414363, 1.998241",\ + "1.000063, 1.180610, 1.368826, 1.670822, 2.254700",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.717104, 0.897183, 1.084764, 1.386548, 1.970002",\ + "0.747689, 0.927768, 1.115349, 1.417133, 2.000586",\ + "0.819516, 0.999595, 1.187176, 1.488960, 2.072413",\ + "1.075975, 1.256054, 1.443635, 1.745419, 2.328872",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244641",\ + "0.771473, 0.951695, 1.139415, 1.441088, 2.024319",\ + "0.802058, 0.982279, 1.170000, 1.471673, 2.054904",\ + "0.873885, 1.054106, 1.241827, 1.543499, 2.126730",\ + "1.130344, 1.310565, 1.498286, 1.799959, 2.383190",\ + "2.046112, 2.226333, 2.414054, 2.715727, 3.298958",\ + "1.053068, 1.236963, 1.423366, 1.724814, 2.307597",\ + "1.083653, 1.267547, 1.453950, 1.755399, 2.338181",\ + "1.155480, 1.339374, 1.525777, 1.827226, 2.410008",\ + "1.411939, 1.595834, 1.782236, 2.083685, 2.666467",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217337, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.426883, 0.694669, 0.956249, 1.395946, 2.275341",\ + "0.452678, 0.720463, 0.982044, 1.421741, 2.301136",\ + "0.504089, 0.771875, 1.033455, 1.473152, 2.352547",\ + "0.670899, 0.938685, 1.200265, 1.639962, 2.519357",\ + "1.261153, 1.528939, 1.790519, 2.230216, 3.109611",\ + "0.515587, 0.782744, 1.044890, 1.484175, 2.362746",\ + "0.541382, 0.808538, 1.070684, 1.509970, 2.388541",\ + "0.592793, 0.859950, 1.122096, 1.561381, 2.439952",\ + "0.759603, 1.026760, 1.288906, 1.728191, 2.606762",\ + "1.349858, 1.617014, 1.879160, 2.318445, 3.197016",\ + "0.608530, 0.875889, 1.136616, 1.576339, 2.455788",\ + "0.634324, 0.901683, 1.162410, 1.602134, 2.481582",\ + "0.685735, 0.953095, 1.213821, 1.653545, 2.532994",\ + "0.852545, 1.119905, 1.380631, 1.820355, 2.699804",\ + "1.442800, 1.710159, 1.970885, 2.410609, 3.290058",\ + "0.674373, 0.944453, 1.203635, 1.643190, 2.522299",\ + "0.700168, 0.970248, 1.229430, 1.668984, 2.548094",\ + "0.751579, 1.021659, 1.280841, 1.720395, 2.599505",\ + "0.918389, 1.188469, 1.447651, 1.887205, 2.766315",\ + "1.508643, 1.778723, 2.037905, 2.477460, 3.356569",\ + "1.020895, 1.325289, 1.574298, 2.012344, 2.888435",\ + "1.046689, 1.351083, 1.600093, 2.038138, 2.914229",\ + "1.098100, 1.402495, 1.651504, 2.089549, 2.965641",\ + "1.264910, 1.569304, 1.818314, 2.256359, 3.132450",\ + "1.855165, 2.159559, 2.408568, 2.846614, 3.722705"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2739*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.464359, 0.727932, 1.004205, 1.472935, 2.410394",\ + "0.494943, 0.758517, 1.034790, 1.503519, 2.440979",\ + "0.566770, 0.830344, 1.106616, 1.575346, 2.512805",\ + "0.823229, 1.086803, 1.363075, 1.831805, 2.769264",\ + "1.738998, 2.002571, 2.278845, 2.747575, 3.685036",\ + "0.552553, 0.815473, 1.091773, 1.559650, 2.496328",\ + "0.583138, 0.846058, 1.122357, 1.590235, 2.526912",\ + "0.654965, 0.917885, 1.194184, 1.662061, 2.598739",\ + "0.911424, 1.174344, 1.450643, 1.918520, 2.855197",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.640869, 0.904454, 1.179738, 1.647273, 2.583283",\ + "0.671454, 0.935038, 1.210322, 1.677857, 2.613867",\ + "0.743281, 1.006865, 1.282149, 1.749684, 2.685694",\ + "0.999740, 1.263324, 1.538608, 2.006143, 2.942153",\ + "1.915508, 2.179093, 2.454377, 2.921913, 3.857924",\ + "0.703365, 0.970089, 1.243877, 1.711186, 2.646792",\ + "0.733950, 1.000673, 1.274462, 1.741771, 2.677376",\ + "0.805777, 1.072500, 1.346289, 1.813598, 2.749203",\ + "1.062236, 1.328959, 1.602748, 2.070056, 3.005661",\ + "1.978004, 2.244728, 2.518517, 2.985826, 3.921433",\ + "1.032491, 1.334419, 1.595745, 2.060536, 2.992248",\ + "1.063076, 1.365004, 1.626329, 2.091120, 3.022832",\ + "1.134902, 1.436831, 1.698156, 2.162947, 3.094659",\ + "1.391361, 1.693290, 1.954615, 2.419406, 3.351118",\ + "2.307130, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715482, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217335",\ + "0.715483, 0.715483, 0.715481, 0.715478, 0.715471",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.409837, 0.592268, 0.788660, 1.097713, 1.692519",\ + "0.435631, 0.618063, 0.814455, 1.123508, 1.718315",\ + "0.487042, 0.669474, 0.865866, 1.174919, 1.769726",\ + "0.653852, 0.836284, 1.032676, 1.341729, 1.936536",\ + "1.244107, 1.426538, 1.622930, 1.931983, 2.526791",\ + "0.497251, 0.679654, 0.876154, 1.185018, 1.779872",\ + "0.523046, 0.705448, 0.901948, 1.210813, 1.805669",\ + "0.574457, 0.756860, 0.953359, 1.262224, 1.857080",\ + "0.741267, 0.923669, 1.120169, 1.429034, 2.023889",\ + "1.331521, 1.513924, 1.710423, 2.019289, 2.614144",\ + "0.578128, 0.759990, 0.956180, 1.265047, 1.859904",\ + "0.603922, 0.785785, 0.981975, 1.290841, 1.885700",\ + "0.655333, 0.837196, 1.033386, 1.342253, 1.937111",\ + "0.822143, 1.004006, 1.200196, 1.509062, 2.103921",\ + "1.412398, 1.594260, 1.790450, 2.099317, 2.694176",\ + "0.635774, 0.817539, 1.013724, 1.322292, 1.916552",\ + "0.661568, 0.843333, 1.039518, 1.348086, 1.942348",\ + "0.712980, 0.894745, 1.090930, 1.399498, 1.993759",\ + "0.879789, 1.061554, 1.257740, 1.566308, 2.160568",\ + "1.470044, 1.651809, 1.847994, 2.156562, 2.750823",\ + "0.937982, 1.122763, 1.317358, 1.625306, 2.218398",\ + "0.963776, 1.148558, 1.343152, 1.651101, 2.244195",\ + "1.015187, 1.199969, 1.394563, 1.702512, 2.295605",\ + "1.181997, 1.366779, 1.561373, 1.869322, 2.462415",\ + "1.772252, 1.957033, 2.151628, 2.459577, 3.052670"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523857"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2665*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.460384, 0.720013, 0.991885, 1.448765, 2.362525",\ + "0.490968, 0.750597, 1.022470, 1.479349, 2.393109",\ + "0.562795, 0.822424, 1.094296, 1.551176, 2.464936",\ + "0.819254, 1.078883, 1.350755, 1.807635, 2.721394",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.548488, 0.807546, 1.079415, 1.535480, 2.448458",\ + "0.579073, 0.838131, 1.110000, 1.566065, 2.479043",\ + "0.650900, 0.909958, 1.181827, 1.637892, 2.550869",\ + "0.907359, 1.166417, 1.438286, 1.894350, 2.807328",\ + "1.823127, 2.082186, 2.354055, 2.810120, 3.723099",\ + "0.636518, 0.896512, 1.167380, 1.623103, 2.535413",\ + "0.667103, 0.927097, 1.197964, 1.653687, 2.565998",\ + "0.738930, 0.998924, 1.269791, 1.725514, 2.637825",\ + "0.995389, 1.255383, 1.526250, 1.981973, 2.894283",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.698740, 0.962126, 1.231518, 1.687016, 2.598922",\ + "0.729324, 0.992710, 1.262102, 1.717601, 2.629507",\ + "0.801151, 1.064537, 1.333929, 1.789428, 2.701334",\ + "1.057610, 1.320996, 1.590388, 2.045887, 2.957792",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.026127, 1.326200, 1.583265, 2.036317, 2.944378",\ + "1.056712, 1.356785, 1.613849, 2.066902, 2.974963",\ + "1.128539, 1.428612, 1.685676, 2.138729, 3.046790",\ + "1.384998, 1.685071, 1.942135, 2.395187, 3.303248",\ + "2.300766, 2.600840, 2.857905, 3.310958, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040151",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217336, 0.217336, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715480, 0.715474, 0.715462",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.408175, 0.590716, 0.786971, 1.096187, 1.691482",\ + "0.433969, 0.616510, 0.812765, 1.121982, 1.717278",\ + "0.485381, 0.667922, 0.864176, 1.173393, 1.768689",\ + "0.652191, 0.834732, 1.030986, 1.340203, 1.935498",\ + "1.242445, 1.424986, 1.621241, 1.930458, 2.525753",\ + "0.495595, 0.678101, 0.874464, 1.183492, 1.778835",\ + "0.521389, 0.703896, 0.900258, 1.209287, 1.804631",\ + "0.572801, 0.755307, 0.951669, 1.260698, 1.856043",\ + "0.739611, 0.922117, 1.118479, 1.427508, 2.022852",\ + "1.329865, 1.512371, 1.708734, 2.017763, 2.613107",\ + "0.576463, 0.758438, 0.954491, 1.263521, 1.858867",\ + "0.602257, 0.784232, 0.980285, 1.289316, 1.884663",\ + "0.653668, 0.835644, 1.031696, 1.340727, 1.936074",\ + "0.820478, 1.002454, 1.198506, 1.507537, 2.102884",\ + "1.410733, 1.592708, 1.788760, 2.097791, 2.693139",\ + "0.634101, 0.815987, 1.012035, 1.320766, 1.915514",\ + "0.659896, 0.841781, 1.037829, 1.346561, 1.941311",\ + "0.711307, 0.893192, 1.089240, 1.397972, 1.992722",\ + "0.878117, 1.060002, 1.256050, 1.564782, 2.159531",\ + "1.468371, 1.650257, 1.846304, 2.155036, 2.749786",\ + "0.936197, 1.121213, 1.315669, 1.623781, 2.217361",\ + "0.961991, 1.147007, 1.341463, 1.649576, 2.243157",\ + "1.013402, 1.198419, 1.392874, 1.700987, 2.294569",\ + "1.180212, 1.365229, 1.559684, 1.867797, 2.461378",\ + "1.770467, 1.955483, 2.149939, 2.458051, 3.051633"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858",\ + "0.040587, 0.040587, 0.040587, 0.040588, 0.040588",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145760",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523854, 1.523858"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2605*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.552667, 0.731094, 0.911354, 1.197561, 1.748678",\ + "0.583252, 0.761679, 0.941939, 1.228145, 1.779262",\ + "0.655079, 0.833506, 1.013766, 1.299972, 1.851089",\ + "0.911538, 1.089965, 1.270225, 1.556431, 2.107548",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.637606, 0.816366, 0.997269, 1.283481, 1.835056",\ + "0.668190, 0.846951, 1.027854, 1.314066, 1.865641",\ + "0.740017, 0.918778, 1.099681, 1.385893, 1.937468",\ + "0.996476, 1.175237, 1.356140, 1.642352, 2.193927",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.713512, 0.891810, 1.072078, 1.358078, 1.909228",\ + "0.744096, 0.922394, 1.102663, 1.388662, 1.939813",\ + "0.815923, 0.994221, 1.174490, 1.460489, 2.011640",\ + "1.072382, 1.250680, 1.430949, 1.716949, 2.268099",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.767864, 0.946321, 1.126729, 1.412617, 1.963546",\ + "0.798448, 0.976906, 1.157314, 1.443202, 1.994130",\ + "0.870275, 1.048733, 1.229141, 1.515029, 2.065957",\ + "1.126734, 1.305192, 1.485600, 1.771488, 2.322416",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.049286, 1.231549, 1.410680, 1.696344, 2.246823",\ + "1.079870, 1.262133, 1.441265, 1.726928, 2.277408",\ + "1.151697, 1.333960, 1.513092, 1.798755, 2.349235",\ + "1.408157, 1.590420, 1.769551, 2.055214, 2.605694",\ + "2.323925, 2.506187, 2.685319, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040152, 0.040152, 0.040152, 0.040152, 0.040152",\ + "0.086136, 0.086136, 0.086136, 0.086136, 0.086136",\ + "0.217337, 0.217337, 0.217337, 0.217336, 0.217336",\ + "0.715483, 0.715483, 0.715483, 0.715483, 0.715483",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.425447, 0.690617, 0.949819, 1.386001, 2.258367",\ + "0.451242, 0.716412, 0.975613, 1.411796, 2.284161",\ + "0.502653, 0.767823, 1.027025, 1.463207, 2.335572",\ + "0.669463, 0.934633, 1.193834, 1.630017, 2.502382",\ + "1.259717, 1.524887, 1.784089, 2.220271, 3.092637",\ + "0.514113, 0.778692, 1.038460, 1.474230, 2.345772",\ + "0.539907, 0.804487, 1.064254, 1.500025, 2.371566",\ + "0.591319, 0.855898, 1.115665, 1.551436, 2.422977",\ + "0.758128, 1.022708, 1.282475, 1.718246, 2.589787",\ + "1.348383, 1.612962, 1.872730, 2.308500, 3.180042",\ + "0.606920, 0.871815, 1.130185, 1.566394, 2.438814",\ + "0.632714, 0.897609, 1.155979, 1.592189, 2.464608",\ + "0.684125, 0.949021, 1.207391, 1.643600, 2.516019",\ + "0.850935, 1.115831, 1.374201, 1.810410, 2.682829",\ + "1.441190, 1.706085, 1.964455, 2.400664, 3.273083",\ + "0.672642, 0.940349, 1.197205, 1.633245, 2.505325",\ + "0.698436, 0.966144, 1.222999, 1.659039, 2.531119",\ + "0.749848, 1.017555, 1.274411, 1.710450, 2.582530",\ + "0.916658, 1.184365, 1.441221, 1.877260, 2.749340",\ + "1.506912, 1.774619, 2.031475, 2.467515, 3.339595",\ + "1.018432, 1.320848, 1.567835, 2.002376, 2.871458",\ + "1.044226, 1.346642, 1.593630, 2.028170, 2.897252",\ + "1.095637, 1.398053, 1.645041, 2.079582, 2.948663",\ + "1.262447, 1.564863, 1.811851, 2.246391, 3.115473",\ + "1.852702, 2.155118, 2.402105, 2.836646, 3.705728"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852",\ + "0.040587, 0.040587, 0.040587, 0.040587, 0.040587",\ + "0.069933, 0.069933, 0.069933, 0.069933, 0.069933",\ + "0.145759, 0.145759, 0.145759, 0.145759, 0.145759",\ + "0.443908, 0.443908, 0.443908, 0.443908, 0.443908",\ + "1.523853, 1.523853, 1.523853, 1.523852, 1.523852"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_2550*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.319941, 0.350525, 0.422353, 0.678812, 1.594576",\ + "0.407332, 0.437916, 0.509743, 0.766203, 1.681967",\ + "0.488251, 0.518835, 0.590662, 0.847122, 1.762885",\ + "0.545991, 0.576576, 0.648403, 0.904863, 1.820624",\ + "0.849304, 0.879623, 0.951109, 1.207569, 2.123717"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.040153, 0.086136, 0.217338, 0.715446, 2.463218",\ + "0.040153, 0.086136, 0.217409, 0.715446, 2.463218",\ + "0.040153, 0.086136, 0.217647, 0.715446, 2.463317",\ + "0.040153, 0.086137, 0.217647, 0.715446, 2.463317",\ + "0.040344, 0.086164, 0.217985, 0.715471, 2.463779"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.305331, 0.331125, 0.382537, 0.549347, 1.139601",\ + "0.392724, 0.418518, 0.469929, 0.636739, 1.226994",\ + "0.473593, 0.499388, 0.550799, 0.717609, 1.307863",\ + "0.531242, 0.557036, 0.608448, 0.775257, 1.365512",\ + "0.833898, 0.859693, 0.911104, 1.077914, 1.668168"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\ + "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\ + "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\ + "0.040587, 0.069933, 0.145759, 0.443908, 1.524252",\ + "0.040602, 0.069933, 0.145764, 0.443908, 1.524252"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.513147, 0.693261, 0.880839, 1.182819, 1.765915",\ + "0.542599, 0.722713, 0.910291, 1.212271, 1.795367",\ + "0.613669, 0.793782, 0.981361, 1.283341, 1.866437",\ + "0.869896, 1.050010, 1.237589, 1.539568, 2.122664",\ + "1.786688, 1.966802, 2.154380, 2.456360, 3.039456",\ + "0.598086, 0.778097, 0.965909, 1.268325, 1.852293",\ + "0.627537, 0.807548, 0.995361, 1.297777, 1.881745",\ + "0.698607, 0.878618, 1.066431, 1.368847, 1.952815",\ + "0.954835, 1.134846, 1.322659, 1.625075, 2.209043",\ + "1.871626, 2.051637, 2.239450, 2.541866, 3.125834",\ + "0.673998, 0.853540, 1.040718, 1.342922, 1.926466",\ + "0.703449, 0.882992, 1.070170, 1.372374, 1.955918",\ + "0.774519, 0.954062, 1.141240, 1.443444, 2.026988",\ + "1.030747, 1.210289, 1.397468, 1.699671, 2.283215",\ + "1.947538, 2.127081, 2.314259, 2.616463, 3.200007",\ + "0.728367, 0.908291, 1.095607, 1.397528, 1.980783",\ + "0.757819, 0.937743, 1.125059, 1.426980, 2.010235",\ + "0.828888, 1.008813, 1.196129, 1.498049, 2.081305",\ + "1.085116, 1.265041, 1.452356, 1.754277, 2.337533",\ + "2.001908, 2.181832, 2.369148, 2.671069, 3.254324",\ + "1.009962, 1.193856, 1.379783, 1.681254, 2.264061",\ + "1.039413, 1.223308, 1.409234, 1.710706, 2.293513",\ + "1.110483, 1.294378, 1.480304, 1.781775, 2.364582",\ + "1.366711, 1.550606, 1.736532, 2.038003, 2.620810",\ + "2.283502, 2.467397, 2.653323, 2.954795, 3.537601"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705773, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.386312, 0.653923, 0.915324, 1.355101, 2.234262",\ + "0.410188, 0.677799, 0.939200, 1.378977, 2.258138",\ + "0.459747, 0.727358, 0.988759, 1.428536, 2.307697",\ + "0.625673, 0.893283, 1.154685, 1.594462, 2.473623",\ + "1.214481, 1.482092, 1.743493, 2.183270, 3.062431",\ + "0.475016, 0.741998, 1.003965, 1.443330, 2.321667",\ + "0.498892, 0.765874, 1.027841, 1.467206, 2.345543",\ + "0.548452, 0.815433, 1.077400, 1.516765, 2.395102",\ + "0.714377, 0.981359, 1.243325, 1.682691, 2.561028",\ + "1.303185, 1.570167, 1.832134, 2.271499, 3.149836",\ + "0.567959, 0.835318, 1.096009, 1.535576, 2.414709",\ + "0.591835, 0.859194, 1.119885, 1.559452, 2.438585",\ + "0.641394, 0.908753, 1.169445, 1.609011, 2.488144",\ + "0.807319, 1.074679, 1.335370, 1.774936, 2.654070",\ + "1.396127, 1.663487, 1.924178, 2.363745, 3.242877",\ + "0.633802, 0.903882, 1.163065, 1.602587, 2.481630",\ + "0.657678, 0.927758, 1.186941, 1.626463, 2.505507",\ + "0.707237, 0.977318, 1.236501, 1.676022, 2.555066",\ + "0.873163, 1.143243, 1.402426, 1.841948, 2.720992",\ + "1.461971, 1.732051, 1.991234, 2.430756, 3.309799",\ + "0.980324, 1.284718, 1.533736, 1.971813, 2.847966",\ + "1.004200, 1.308594, 1.557612, 1.995689, 2.871842",\ + "1.053759, 1.358153, 1.607171, 2.045248, 2.921401",\ + "1.219684, 1.524079, 1.773097, 2.211174, 3.087327",\ + "1.808493, 2.112887, 2.361905, 2.799982, 3.676135"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439342, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2492*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.421256, 0.684787, 0.960907, 1.429039, 2.364044",\ + "0.450707, 0.714239, 0.990358, 1.458491, 2.393496",\ + "0.521777, 0.785309, 1.061428, 1.529561, 2.464566",\ + "0.778005, 1.041536, 1.317656, 1.785789, 2.720794",\ + "1.694797, 1.958328, 2.234447, 2.702580, 3.637585",\ + "0.509450, 0.772327, 1.048474, 1.515754, 2.449978",\ + "0.538902, 0.801779, 1.077925, 1.545206, 2.479430",\ + "0.609972, 0.872849, 1.148995, 1.616276, 2.550500",\ + "0.866199, 1.129077, 1.405223, 1.872504, 2.806728",\ + "1.782991, 2.045868, 2.322014, 2.789295, 3.723519",\ + "0.597766, 0.861307, 1.136438, 1.603395, 2.536933",\ + "0.627218, 0.890759, 1.165890, 1.632846, 2.566385",\ + "0.698288, 0.961829, 1.236960, 1.703916, 2.637455",\ + "0.954515, 1.218056, 1.493188, 1.960144, 2.893683",\ + "1.871307, 2.134848, 2.409979, 2.876935, 3.810474",\ + "0.660262, 0.926941, 1.200578, 1.667483, 2.600442",\ + "0.689714, 0.956392, 1.230030, 1.696935, 2.629894",\ + "0.760784, 1.027462, 1.301100, 1.768005, 2.700964",\ + "1.017011, 1.283690, 1.557327, 2.024233, 2.957192",\ + "1.933803, 2.200481, 2.474119, 2.941024, 3.873983",\ + "0.989388, 1.291255, 1.552442, 2.016927, 2.945898",\ + "1.018839, 1.320707, 1.581894, 2.046379, 2.975350",\ + "1.089909, 1.391777, 1.652964, 2.117449, 3.046420",\ + "1.346137, 1.648005, 1.909191, 2.373677, 3.302648",\ + "2.262928, 2.564796, 2.825983, 3.290468, 4.219439"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036607",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705775, 0.705777, 0.705782",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.369267, 0.551325, 0.747559, 1.056740, 1.651224",\ + "0.393143, 0.575201, 0.771435, 1.080616, 1.675100",\ + "0.442703, 0.624760, 0.820994, 1.130175, 1.724659",\ + "0.608628, 0.790685, 0.986919, 1.296102, 1.890590",\ + "1.197436, 1.379494, 1.575727, 1.884908, 2.479391",\ + "0.456682, 0.638644, 0.834839, 1.144045, 1.738577",\ + "0.480558, 0.662519, 0.858715, 1.167921, 1.762453",\ + "0.530117, 0.712079, 0.908275, 1.217480, 1.812012",\ + "0.696043, 0.878004, 1.074200, 1.383407, 1.977943",\ + "1.284851, 1.466812, 1.663008, 1.972213, 2.566744",\ + "0.537558, 0.718980, 0.914866, 1.224073, 1.818609",\ + "0.561434, 0.742856, 0.938742, 1.247949, 1.842485",\ + "0.610994, 0.792415, 0.988301, 1.297508, 1.892044",\ + "0.776919, 0.958341, 1.154227, 1.463436, 2.057975",\ + "1.365727, 1.547149, 1.743035, 2.052242, 2.646776",\ + "0.595205, 0.776817, 0.972602, 1.281544, 1.875705",\ + "0.619081, 0.800693, 0.996478, 1.305420, 1.899580",\ + "0.668640, 0.850252, 1.046037, 1.354979, 1.949140",\ + "0.834565, 1.016178, 1.211963, 1.520906, 2.115070",\ + "1.423374, 1.604986, 1.800771, 2.109712, 2.703871",\ + "0.897412, 1.082194, 1.276265, 1.584751, 2.178023",\ + "0.921288, 1.106070, 1.300141, 1.608627, 2.201899",\ + "0.970848, 1.155629, 1.349701, 1.658186, 2.251458",\ + "1.136773, 1.321555, 1.515626, 1.824113, 2.417389",\ + "1.725581, 1.910363, 2.104434, 2.412919, 3.006190"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032797, 0.032797, 0.032797, 0.032797, 0.032797",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439321, 0.439321, 0.439321, 0.439321, 0.439321",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2414*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.417278, 0.676837, 0.948472, 1.404635, 2.315804",\ + "0.446729, 0.706289, 0.977924, 1.434087, 2.345256",\ + "0.517799, 0.777359, 1.048994, 1.505156, 2.416326",\ + "0.774027, 1.033586, 1.305222, 1.761384, 2.672554",\ + "1.690818, 1.950378, 2.222013, 2.678176, 3.589346",\ + "0.505382, 0.764370, 1.036001, 1.491350, 2.401738",\ + "0.534834, 0.793822, 1.065453, 1.520802, 2.431190",\ + "0.605904, 0.864891, 1.136523, 1.591872, 2.502260",\ + "0.862132, 1.121119, 1.392751, 1.848100, 2.758488",\ + "1.778923, 2.037910, 2.309542, 2.764891, 3.675279",\ + "0.593413, 0.853334, 1.123966, 1.578989, 2.488693",\ + "0.622864, 0.882786, 1.153417, 1.608441, 2.518145",\ + "0.693934, 0.953856, 1.224487, 1.679511, 2.589215",\ + "0.950162, 1.210083, 1.480715, 1.935739, 2.845443",\ + "1.866953, 2.126875, 2.397506, 2.852530, 3.762234",\ + "0.655634, 0.918945, 1.188103, 1.643063, 2.552202",\ + "0.685085, 0.948397, 1.217555, 1.672515, 2.581654",\ + "0.756155, 1.019467, 1.288625, 1.743585, 2.652724",\ + "1.012383, 1.275695, 1.544853, 1.999813, 2.908952",\ + "1.929174, 2.192486, 2.461644, 2.916605, 3.825743",\ + "0.983021, 1.282994, 1.539846, 1.992450, 2.897658",\ + "1.012473, 1.312446, 1.569298, 2.021902, 2.927110",\ + "1.083543, 1.383515, 1.640368, 2.092972, 2.998180",\ + "1.339770, 1.639743, 1.896595, 2.349199, 3.254408",\ + "2.256562, 2.556535, 2.813387, 3.265991, 4.171200"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766",\ + "0.036606, 0.036606, 0.036606, 0.036607, 0.036608",\ + "0.083622, 0.083622, 0.083622, 0.083623, 0.083623",\ + "0.215854, 0.215855, 0.215855, 0.215855, 0.215856",\ + "0.705773, 0.705774, 0.705776, 0.705780, 0.705788",\ + "2.456797, 2.456796, 2.456792, 2.456784, 2.456766"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.367604, 0.549771, 0.745869, 1.055208, 1.650168",\ + "0.391480, 0.573647, 0.769745, 1.079083, 1.674044",\ + "0.441039, 0.623206, 0.819305, 1.128643, 1.723603",\ + "0.606964, 0.789132, 0.985230, 1.294570, 1.889535",\ + "1.195773, 1.377940, 1.574038, 1.883376, 2.478335",\ + "0.455024, 0.637090, 0.833150, 1.142513, 1.737522",\ + "0.478900, 0.660966, 0.857026, 1.166389, 1.761397",\ + "0.528459, 0.710525, 0.906585, 1.215948, 1.810957",\ + "0.694384, 0.876450, 1.072511, 1.381875, 1.976888",\ + "1.283193, 1.465259, 1.661319, 1.970681, 2.565688",\ + "0.535891, 0.717427, 0.913177, 1.222541, 1.817554",\ + "0.559767, 0.741302, 0.937053, 1.246417, 1.841429",\ + "0.609326, 0.790862, 0.986612, 1.295976, 1.890988",\ + "0.775252, 0.956787, 1.152538, 1.461904, 2.056920",\ + "1.364060, 1.545596, 1.741346, 2.050709, 2.645720",\ + "0.593530, 0.775263, 0.970912, 1.280012, 1.874650",\ + "0.617406, 0.799139, 0.994788, 1.303888, 1.898526",\ + "0.666965, 0.848699, 1.044348, 1.353447, 1.948085",\ + "0.832891, 1.014624, 1.210274, 1.519375, 2.114016",\ + "1.421699, 1.603432, 1.799081, 2.108180, 2.702816",\ + "0.895625, 1.080642, 1.274576, 1.583220, 2.176970",\ + "0.919501, 1.104518, 1.298452, 1.607095, 2.200845",\ + "0.969060, 1.154077, 1.348011, 1.656655, 2.250404",\ + "1.134986, 1.320002, 1.513937, 1.822582, 2.416336",\ + "1.723794, 1.908811, 2.102745, 2.411388, 3.005136"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844",\ + "0.032796, 0.032796, 0.032796, 0.032796, 0.032796",\ + "0.061344, 0.061344, 0.061344, 0.061345, 0.061345",\ + "0.138997, 0.138997, 0.138997, 0.138997, 0.138997",\ + "0.439319, 0.439319, 0.439319, 0.439319, 0.439319",\ + "1.518841, 1.518841, 1.518841, 1.518842, 1.518844"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2348*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.509561, 0.687900, 0.868247, 1.154434, 1.705187",\ + "0.539012, 0.717352, 0.897699, 1.183885, 1.734638",\ + "0.610082, 0.788422, 0.968769, 1.254955, 1.805708",\ + "0.866310, 1.044649, 1.224996, 1.511183, 2.061936",\ + "1.783102, 1.961441, 2.141788, 2.427974, 2.978728",\ + "0.594499, 0.772736, 0.953317, 1.239940, 1.791565",\ + "0.623951, 0.802188, 0.982769, 1.269392, 1.821017",\ + "0.695021, 0.873258, 1.053839, 1.340461, 1.892087",\ + "0.951248, 1.129485, 1.310066, 1.596689, 2.148314",\ + "1.868040, 2.046277, 2.226858, 2.513481, 3.065106",\ + "0.670405, 0.848179, 1.028126, 1.314537, 1.865738",\ + "0.699857, 0.877631, 1.057578, 1.343988, 1.895189",\ + "0.770927, 0.948701, 1.128648, 1.415058, 1.966259",\ + "1.027155, 1.204929, 1.384875, 1.671286, 2.222487",\ + "1.943946, 2.121720, 2.301667, 2.588078, 3.139278",\ + "0.724757, 0.902925, 1.082991, 1.369130, 1.920055",\ + "0.754209, 0.932377, 1.112443, 1.398582, 1.949507",\ + "0.825279, 1.003447, 1.183513, 1.469652, 2.020576",\ + "1.081507, 1.259674, 1.439741, 1.725880, 2.276804",\ + "1.998298, 2.176466, 2.356532, 2.642671, 3.193595",\ + "1.006179, 1.188442, 1.367144, 1.652857, 2.203332",\ + "1.035631, 1.217894, 1.396596, 1.682308, 2.232784",\ + "1.106701, 1.288964, 1.467666, 1.753378, 2.303854",\ + "1.362929, 1.545192, 1.723894, 2.009606, 2.560082",\ + "2.279720, 2.461983, 2.640685, 2.926397, 3.476873"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036606, 0.036606, 0.036606, 0.036606, 0.036606",\ + "0.083622, 0.083622, 0.083622, 0.083622, 0.083622",\ + "0.215854, 0.215854, 0.215854, 0.215854, 0.215855",\ + "0.705773, 0.705773, 0.705773, 0.705774, 0.705774",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.384876, 0.649875, 0.908905, 1.345169, 2.217316",\ + "0.408752, 0.673751, 0.932781, 1.369045, 2.241192",\ + "0.458311, 0.723311, 0.982340, 1.418604, 2.290751",\ + "0.624237, 0.889236, 1.148266, 1.584530, 2.456676",\ + "1.213045, 1.478044, 1.737074, 2.173338, 3.045485",\ + "0.473542, 0.737950, 0.997546, 1.433398, 2.304721",\ + "0.497418, 0.761826, 1.021422, 1.457274, 2.328597",\ + "0.546977, 0.811386, 1.070981, 1.506833, 2.378156",\ + "0.712902, 0.977311, 1.236907, 1.672759, 2.544082",\ + "1.301711, 1.566119, 1.825715, 2.261567, 3.132890",\ + "0.566349, 0.831244, 1.089581, 1.525641, 2.397763",\ + "0.590225, 0.855120, 1.113457, 1.549517, 2.421639",\ + "0.639784, 0.904679, 1.163016, 1.599077, 2.471198",\ + "0.805709, 1.070605, 1.328942, 1.765002, 2.637124",\ + "1.394518, 1.659413, 1.917750, 2.353810, 3.225932",\ + "0.632071, 0.899778, 1.156636, 1.592648, 2.464673",\ + "0.655947, 0.923654, 1.180512, 1.616524, 2.488548",\ + "0.705506, 0.973213, 1.230071, 1.666083, 2.538108",\ + "0.871432, 1.139139, 1.395997, 1.832009, 2.704033",\ + "1.460240, 1.727947, 1.984805, 2.420817, 3.292841",\ + "0.977860, 1.280277, 1.527274, 1.961849, 2.830999",\ + "1.001736, 1.304152, 1.551150, 1.985725, 2.854876",\ + "1.051296, 1.353712, 1.600709, 2.035285, 2.904435",\ + "1.217221, 1.519637, 1.766635, 2.201210, 3.070360",\ + "1.806029, 2.108445, 2.355443, 2.790018, 3.659168"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841",\ + "0.032798, 0.032798, 0.032798, 0.032798, 0.032798",\ + "0.061344, 0.061344, 0.061344, 0.061344, 0.061344",\ + "0.138998, 0.138998, 0.138998, 0.138998, 0.138998",\ + "0.439342, 0.439342, 0.439343, 0.439343, 0.439343",\ + "1.518841, 1.518841, 1.518841, 1.518841, 1.518841"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min_2294*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.137566, 0.167336, 0.239033, 0.495310, 1.411098",\ + "0.225751, 0.255520, 0.327229, 0.583553, 1.499024",\ + "0.314076, 0.343844, 0.415554, 0.672074, 1.587106",\ + "0.376665, 0.406437, 0.478090, 0.734905, 1.650403",\ + "0.706539, 0.736325, 0.807782, 1.065036, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\ + "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\ + "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\ + "0.036606, 0.083622, 0.215854, 0.705773, 2.456797",\ + "0.036606, 0.083622, 0.215854, 0.705773, 2.456797"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.176657, 0.200194, 0.249429, 0.415146, 1.003925",\ + "0.264061, 0.287598, 0.336833, 0.502550, 1.091329",\ + "0.344959, 0.368493, 0.417732, 0.583454, 1.172242",\ + "0.402624, 0.426151, 0.475399, 0.641128, 1.229933",\ + "0.704984, 0.728497, 0.777773, 0.943572, 1.532550"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.032799, 0.061344, 0.138999, 0.438536, 1.518306",\ + "0.032799, 0.061344, 0.138999, 0.438535, 1.518306",\ + "0.032799, 0.061344, 0.138999, 0.438535, 1.518105",\ + "0.032799, 0.061344, 0.138999, 0.438535, 1.517729",\ + "0.032799, 0.061344, 0.138998, 0.438535, 1.516557"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[6]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.078864, 0.108975, 0.180232, 0.436421, 1.354955",\ + "0.161216, 0.191623, 0.263062, 0.519150, 1.434794",\ + "0.248912, 0.281774, 0.353596, 0.609294, 1.527520",\ + "0.395567, 0.436700, 0.511657, 0.767118, 1.680857",\ + "0.628444, 0.688613, 0.779970, 1.032241, 1.943170"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.039377, 0.084977, 0.216447, 0.713042, 2.472405",\ + "0.040943, 0.085824, 0.216786, 0.713478, 2.472405",\ + "0.053222, 0.092507, 0.217591, 0.713478, 2.472405",\ + "0.083456, 0.114560, 0.223431, 0.713478, 2.472405",\ + "0.146897, 0.173026, 0.257773, 0.713478, 2.472405"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.111091, 0.136344, 0.187602, 0.354583, 0.943175",\ + "0.190778, 0.216967, 0.268153, 0.434275, 1.024748",\ + "0.290508, 0.318338, 0.371105, 0.537415, 1.127562",\ + "0.459624, 0.495257, 0.553492, 0.720404, 1.308180",\ + "0.729304, 0.783232, 0.859550, 1.032706, 1.617889"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.039826, 0.069221, 0.145259, 0.444902, 1.525117",\ + "0.040254, 0.069221, 0.145259, 0.444902, 1.525117",\ + "0.050781, 0.076552, 0.148038, 0.444902, 1.525117",\ + "0.080540, 0.101538, 0.163724, 0.445523, 1.525117",\ + "0.141255, 0.162992, 0.212369, 0.458214, 1.525117"); + } + + } /* end of arc padmux2ast_i[6]_obs_ctrl_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.074357, 0.103835, 0.175088, 0.430040, 1.346996",\ + "0.156284, 0.185798, 0.256925, 0.512689, 1.426492",\ + "0.240577, 0.272242, 0.343453, 0.599199, 1.515415",\ + "0.383466, 0.422274, 0.495817, 0.750018, 1.664121",\ + "0.607663, 0.663725, 0.751347, 1.002896, 1.912977"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.036939, 0.083563, 0.215464, 0.698603, 2.446539",\ + "0.038445, 0.084260, 0.215464, 0.704042, 2.446539",\ + "0.049297, 0.090259, 0.216941, 0.705803, 2.446539",\ + "0.076679, 0.110998, 0.222061, 0.706283, 2.457507",\ + "0.134063, 0.165740, 0.252770, 0.710864, 2.457507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.080261, 0.102858, 0.151114, 0.316434, 0.906304",\ + "0.165732, 0.188510, 0.236836, 0.401880, 0.995903",\ + "0.261156, 0.287506, 0.337668, 0.502550, 1.091127",\ + "0.420973, 0.455458, 0.511965, 0.676394, 1.262831",\ + "0.677498, 0.731290, 0.807033, 0.979368, 1.563209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000997, 0.004236, 0.012818, 0.044133, 0.156168"); + values ( "0.032396, 0.061186, 0.138642, 0.440176, 1.520011",\ + "0.033582, 0.061465, 0.138784, 0.440176, 1.520011",\ + "0.046234, 0.071020, 0.142472, 0.440176, 1.520011",\ + "0.075362, 0.096304, 0.158284, 0.443536, 1.520011",\ + "0.135524, 0.156881, 0.206007, 0.453845, 1.520011"); + } + + } /* end of arc padmux2ast_i[6]_obs_ctrl_o[6]_una_min*/ + +} /* end of pin obs_ctrl_o[6] */ + +pin("obs_ctrl_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001502 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.561257, 0.741460, 0.928950, 1.230943, 1.814455",\ + "0.591077, 0.771280, 0.958770, 1.260762, 1.844274",\ + "0.662801, 0.843004, 1.030494, 1.332487, 1.915998",\ + "0.919252, 1.099455, 1.286945, 1.588937, 2.172449",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.646196, 0.826743, 1.014959, 1.316955, 1.900833",\ + "0.676015, 0.856563, 1.044779, 1.346775, 1.930653",\ + "0.747739, 0.928287, 1.116503, 1.418499, 2.002377",\ + "1.004190, 1.184738, 1.372953, 1.674950, 2.258828",\ + "1.915830, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.722108, 0.902187, 1.089768, 1.391552, 1.975005",\ + "0.751927, 0.932006, 1.119587, 1.421371, 2.004825",\ + "0.823651, 1.003731, 1.191312, 1.493096, 2.076549",\ + "1.080102, 1.260181, 1.447762, 1.749547, 2.333000",\ + "1.991742, 2.171822, 2.359402, 2.661187, 3.244640",\ + "0.776477, 0.956699, 1.144419, 1.446092, 2.029323",\ + "0.806297, 0.986518, 1.174238, 1.475911, 2.059142",\ + "0.878021, 1.058242, 1.245963, 1.547635, 2.130867",\ + "1.134472, 1.314693, 1.502414, 1.804086, 2.387317",\ + "2.046112, 2.226333, 2.414053, 2.715726, 3.298958",\ + "1.058072, 1.241966, 1.428370, 1.729818, 2.312600",\ + "1.087891, 1.271786, 1.458189, 1.759638, 2.342420",\ + "1.159616, 1.343510, 1.529913, 1.831362, 2.414144",\ + "1.416066, 1.599961, 1.786364, 2.087812, 2.670595",\ + "2.327706, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.431434, 0.699219, 0.960799, 1.400496, 2.279891",\ + "0.455832, 0.723618, 0.985198, 1.424895, 2.304290",\ + "0.506856, 0.774642, 1.036222, 1.475919, 2.355314",\ + "0.673635, 0.941421, 1.203001, 1.642698, 2.522093",\ + "1.261229, 1.529015, 1.790595, 2.230292, 3.109687",\ + "0.520138, 0.787294, 1.049440, 1.488726, 2.367296",\ + "0.544536, 0.811693, 1.073839, 1.513124, 2.391695",\ + "0.595560, 0.862717, 1.124863, 1.564148, 2.442719",\ + "0.762339, 1.029496, 1.291642, 1.730927, 2.609498",\ + "1.349933, 1.617090, 1.879236, 2.318521, 3.197092",\ + "0.613080, 0.880439, 1.141166, 1.580890, 2.460338",\ + "0.637479, 0.904838, 1.165565, 1.605289, 2.484737",\ + "0.688503, 0.955862, 1.216588, 1.656312, 2.535761",\ + "0.855281, 1.122641, 1.383367, 1.823091, 2.702539",\ + "1.442875, 1.710235, 1.970961, 2.410685, 3.290133",\ + "0.678924, 0.949004, 1.208186, 1.647740, 2.526850",\ + "0.703322, 0.973402, 1.232584, 1.672139, 2.551248",\ + "0.754346, 1.024426, 1.283608, 1.723163, 2.602272",\ + "0.921125, 1.191205, 1.450387, 1.889941, 2.769051",\ + "1.508719, 1.778799, 2.037981, 2.477535, 3.356645",\ + "1.025445, 1.329839, 1.578848, 2.016894, 2.892985",\ + "1.049844, 1.354238, 1.603247, 2.041293, 2.917384",\ + "1.100868, 1.405262, 1.654271, 2.092317, 2.968408",\ + "1.267646, 1.572041, 1.821050, 2.259095, 3.135186",\ + "1.855240, 2.159635, 2.408644, 2.846689, 3.722780"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2732*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.469363, 0.732936, 1.009209, 1.477938, 2.415398",\ + "0.499182, 0.762756, 1.039028, 1.507758, 2.445217",\ + "0.570906, 0.834480, 1.110752, 1.579482, 2.516941",\ + "0.827357, 1.090931, 1.367203, 1.835933, 2.773392",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.557557, 0.820477, 1.096777, 1.564654, 2.501331",\ + "0.587376, 0.850296, 1.126596, 1.594473, 2.531151",\ + "0.659100, 0.922021, 1.198320, 1.666197, 2.602875",\ + "0.915551, 1.178471, 1.454771, 1.922648, 2.859325",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.645873, 0.909457, 1.184741, 1.652276, 2.588286",\ + "0.675692, 0.939277, 1.214561, 1.682096, 2.618106",\ + "0.747417, 1.011001, 1.286285, 1.753820, 2.689830",\ + "1.003868, 1.267452, 1.542736, 2.010271, 2.946280",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.708369, 0.975092, 1.248881, 1.716190, 2.651795",\ + "0.738189, 1.004912, 1.278701, 1.746009, 2.681615",\ + "0.809913, 1.076636, 1.350425, 1.817733, 2.753339",\ + "1.066364, 1.333087, 1.606875, 2.074184, 3.009789",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.037495, 1.339423, 1.600748, 2.065540, 2.997252",\ + "1.067314, 1.369243, 1.630568, 2.095359, 3.027071",\ + "1.139038, 1.440967, 1.702292, 2.167083, 3.098795",\ + "1.395489, 1.697417, 1.958743, 2.423534, 3.355246",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463217, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723330, 0.723327, 0.723319",\ + "2.463217, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.414387, 0.596819, 0.793211, 1.102263, 1.697070",\ + "0.438785, 0.621217, 0.817609, 1.126662, 1.721470",\ + "0.489809, 0.672241, 0.868633, 1.177686, 1.772493",\ + "0.656588, 0.839020, 1.035412, 1.344465, 1.939272",\ + "1.244182, 1.426614, 1.623006, 1.932059, 2.526866",\ + "0.501801, 0.684204, 0.880704, 1.189568, 1.784423",\ + "0.526200, 0.708603, 0.905102, 1.213968, 1.808823",\ + "0.577224, 0.759627, 0.956126, 1.264991, 1.859847",\ + "0.744003, 0.926405, 1.122905, 1.431770, 2.026625",\ + "1.331597, 1.513999, 1.710499, 2.019364, 2.614220",\ + "0.582678, 0.764541, 0.960731, 1.269597, 1.864455",\ + "0.607077, 0.788939, 0.985129, 1.293996, 1.888855",\ + "0.658100, 0.839963, 1.036153, 1.345020, 1.939878",\ + "0.824879, 1.006742, 1.202932, 1.511798, 2.106657",\ + "1.412473, 1.594336, 1.790526, 2.099392, 2.694252",\ + "0.640324, 0.822089, 1.018274, 1.326842, 1.921102",\ + "0.664723, 0.846488, 1.042673, 1.351241, 1.945503",\ + "0.715747, 0.897512, 1.093697, 1.402265, 1.996526",\ + "0.882525, 1.064290, 1.260476, 1.569043, 2.163304",\ + "1.470119, 1.651884, 1.848070, 2.156638, 2.750899",\ + "0.942532, 1.127314, 1.321908, 1.629857, 2.222949",\ + "0.966931, 1.151712, 1.346307, 1.654256, 2.247349",\ + "1.017955, 1.202736, 1.397331, 1.705280, 2.298373",\ + "1.184733, 1.369515, 1.564109, 1.872058, 2.465151",\ + "1.772327, 1.957109, 2.151703, 2.459652, 3.052746"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523992, 1.523996"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2657*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.465387, 0.725016, 0.996889, 1.453768, 2.367528",\ + "0.495207, 0.754836, 1.026708, 1.483588, 2.397348",\ + "0.566931, 0.826560, 1.098432, 1.555312, 2.469071",\ + "0.823382, 1.083011, 1.354883, 1.811763, 2.725522",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637165",\ + "0.553492, 0.812550, 1.084419, 1.540484, 2.453462",\ + "0.583312, 0.842370, 1.114239, 1.570303, 2.483281",\ + "0.655036, 0.914094, 1.185963, 1.642027, 2.555005",\ + "0.911487, 1.170545, 1.442413, 1.898478, 2.811456",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.641522, 0.901516, 1.172383, 1.628106, 2.540417",\ + "0.671342, 0.931335, 1.202203, 1.657926, 2.570236",\ + "0.743066, 1.003059, 1.273927, 1.729650, 2.641960",\ + "0.999517, 1.259510, 1.530378, 1.986101, 2.898411",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.703743, 0.967129, 1.236521, 1.692020, 2.603926",\ + "0.733563, 0.996949, 1.266341, 1.721840, 2.633745",\ + "0.805287, 1.068673, 1.338065, 1.793564, 2.705469",\ + "1.061738, 1.325124, 1.594516, 2.050014, 2.961920",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.031131, 1.331204, 1.588269, 2.041321, 2.949382",\ + "1.060951, 1.361024, 1.618088, 2.071141, 2.979202",\ + "1.132675, 1.432748, 1.689812, 2.142864, 3.050925",\ + "1.389125, 1.689199, 1.946263, 2.399315, 3.307376",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723332, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047099, 0.047099, 0.047099, 0.047099",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225236",\ + "0.723332, 0.723331, 0.723329, 0.723323, 0.723311",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.412725, 0.595266, 0.791521, 1.100738, 1.696032",\ + "0.437124, 0.619665, 0.815920, 1.125137, 1.720433",\ + "0.488148, 0.670689, 0.866944, 1.176161, 1.771456",\ + "0.654926, 0.837467, 1.033722, 1.342939, 1.938234",\ + "1.242520, 1.425061, 1.621316, 1.930533, 2.525829",\ + "0.500145, 0.682652, 0.879014, 1.188043, 1.783386",\ + "0.524544, 0.707050, 0.903413, 1.212442, 1.807786",\ + "0.575568, 0.758074, 0.954436, 1.263466, 1.858810",\ + "0.742347, 0.924853, 1.121215, 1.430244, 2.025588",\ + "1.329941, 1.512447, 1.708809, 2.017838, 2.613183",\ + "0.581013, 0.762988, 0.959041, 1.268071, 1.863418",\ + "0.605412, 0.787387, 0.983440, 1.292470, 1.887818",\ + "0.656435, 0.838411, 1.034463, 1.343494, 1.938841",\ + "0.823214, 1.005190, 1.201242, 1.510273, 2.105619",\ + "1.410808, 1.592784, 1.788836, 2.097867, 2.693214",\ + "0.638652, 0.820537, 1.016585, 1.325316, 1.920065",\ + "0.663050, 0.844936, 1.040983, 1.349715, 1.944465",\ + "0.714074, 0.895960, 1.092007, 1.400739, 1.995489",\ + "0.880853, 1.062738, 1.258786, 1.567518, 2.162267",\ + "1.468447, 1.650332, 1.846380, 2.155112, 2.749862",\ + "0.940747, 1.125763, 1.320219, 1.628331, 2.221912",\ + "0.965146, 1.150162, 1.344617, 1.652730, 2.246312",\ + "1.016169, 1.201186, 1.395641, 1.703754, 2.297336",\ + "1.182948, 1.367965, 1.562420, 1.870533, 2.464114",\ + "1.770542, 1.955559, 2.150014, 2.458127, 3.051709"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523993, 1.523996"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2600*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.557671, 0.736098, 0.916358, 1.202564, 1.753681",\ + "0.587491, 0.765917, 0.946178, 1.232384, 1.783501",\ + "0.659215, 0.837641, 1.017902, 1.304108, 1.855225",\ + "0.915666, 1.094092, 1.274353, 1.560559, 2.111676",\ + "1.827306, 2.005732, 2.185993, 2.472199, 3.023316",\ + "0.642609, 0.821370, 1.002273, 1.288485, 1.840060",\ + "0.672429, 0.851190, 1.032093, 1.318304, 1.869879",\ + "0.744153, 0.922914, 1.103817, 1.390028, 1.941603",\ + "1.000604, 1.179365, 1.360268, 1.646479, 2.198054",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.718516, 0.896813, 1.077082, 1.363081, 1.914232",\ + "0.748335, 0.926633, 1.106902, 1.392901, 1.944052",\ + "0.820059, 0.998357, 1.178626, 1.464625, 2.015776",\ + "1.076510, 1.254808, 1.435077, 1.721076, 2.272227",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.772868, 0.951325, 1.131733, 1.417621, 1.968549",\ + "0.802687, 0.981145, 1.161553, 1.447441, 1.998369",\ + "0.874411, 1.052869, 1.233277, 1.519165, 2.070093",\ + "1.130862, 1.309320, 1.489728, 1.775616, 2.326544",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.054290, 1.236552, 1.415684, 1.701348, 2.251827",\ + "1.084109, 1.266372, 1.445503, 1.731167, 2.281647",\ + "1.155833, 1.338096, 1.517227, 1.802891, 2.353371",\ + "1.412284, 1.594547, 1.773678, 2.059342, 2.609822",\ + "2.323924, 2.506187, 2.685318, 2.970982, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.047100, 0.047100, 0.047100, 0.047100, 0.047100",\ + "0.093802, 0.093802, 0.093802, 0.093802, 0.093802",\ + "0.225237, 0.225237, 0.225237, 0.225237, 0.225237",\ + "0.723332, 0.723332, 0.723332, 0.723332, 0.723332",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.429998, 0.695167, 0.954369, 1.390552, 2.262917",\ + "0.454396, 0.719566, 0.978768, 1.414950, 2.287315",\ + "0.505420, 0.770590, 1.029792, 1.465974, 2.338339",\ + "0.672199, 0.937369, 1.196570, 1.632753, 2.505118",\ + "1.259793, 1.524963, 1.784164, 2.220347, 3.092712",\ + "0.518663, 0.783242, 1.043010, 1.478781, 2.350322",\ + "0.543062, 0.807641, 1.067409, 1.503179, 2.374721",\ + "0.594086, 0.858665, 1.118433, 1.554203, 2.425745",\ + "0.760864, 1.025444, 1.285211, 1.720982, 2.592523",\ + "1.348459, 1.613038, 1.872805, 2.308576, 3.180117",\ + "0.611470, 0.876365, 1.134735, 1.570945, 2.443364",\ + "0.635869, 0.900764, 1.159134, 1.595343, 2.467762",\ + "0.686893, 0.951788, 1.210158, 1.646367, 2.518786",\ + "0.853671, 1.118567, 1.376937, 1.813146, 2.685565",\ + "1.441265, 1.706161, 1.964531, 2.400740, 3.273159",\ + "0.677192, 0.944899, 1.201755, 1.637795, 2.509875",\ + "0.701591, 0.969298, 1.226154, 1.662194, 2.534274",\ + "0.752615, 1.020322, 1.277178, 1.713217, 2.585298",\ + "0.919394, 1.187101, 1.443956, 1.879996, 2.752076",\ + "1.506988, 1.774695, 2.031551, 2.467590, 3.339670",\ + "1.022982, 1.325398, 1.572386, 2.006926, 2.876008",\ + "1.047381, 1.349797, 1.596784, 2.031325, 2.900407",\ + "1.098405, 1.400820, 1.647808, 2.082349, 2.951431",\ + "1.265183, 1.567599, 1.814587, 2.249127, 3.118209",\ + "1.852777, 2.155193, 2.402181, 2.836721, 3.705803"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991",\ + "0.045359, 0.045359, 0.045359, 0.045359, 0.045359",\ + "0.074479, 0.074479, 0.074479, 0.074479, 0.074479",\ + "0.150687, 0.150687, 0.150687, 0.150687, 0.150687",\ + "0.448891, 0.448891, 0.448891, 0.448891, 0.448891",\ + "1.523991, 1.523991, 1.523991, 1.523991, 1.523991"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_2542*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.324944, 0.354764, 0.426488, 0.682940, 1.594576",\ + "0.412335, 0.442155, 0.513879, 0.770331, 1.681967",\ + "0.493254, 0.523074, 0.594798, 0.851250, 1.762885",\ + "0.550995, 0.580814, 0.652539, 0.908991, 1.820623",\ + "0.854260, 0.883835, 0.955245, 1.211697, 2.123717"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.047100, 0.093803, 0.225238, 0.723294, 2.463217",\ + "0.047100, 0.093803, 0.225317, 0.723294, 2.463217",\ + "0.047100, 0.093803, 0.225549, 0.723294, 2.463317",\ + "0.047101, 0.093803, 0.225549, 0.723294, 2.463317",\ + "0.047256, 0.093828, 0.225883, 0.723320, 2.463779"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.309881, 0.334280, 0.385304, 0.552083, 1.139677",\ + "0.397274, 0.421673, 0.472696, 0.639475, 1.227069",\ + "0.478143, 0.502542, 0.553566, 0.720345, 1.307939",\ + "0.535792, 0.560191, 0.611215, 0.777993, 1.365587",\ + "0.838449, 0.862847, 0.913871, 1.080650, 1.668244"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.045359, 0.074479, 0.150693, 0.448891, 1.524390",\ + "0.045359, 0.074479, 0.150693, 0.448891, 1.524390",\ + "0.045359, 0.074479, 0.150693, 0.448891, 1.524264",\ + "0.045359, 0.074479, 0.150693, 0.448891, 1.524028",\ + "0.045353, 0.074413, 0.150693, 0.448886, 1.523991"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.517919, 0.698033, 0.885611, 1.187591, 1.770688",\ + "0.546784, 0.726898, 0.914476, 1.216456, 1.799552",\ + "0.617826, 0.797940, 0.985519, 1.287498, 1.870595",\ + "0.874029, 1.054142, 1.241721, 1.543701, 2.126797",\ + "1.786688, 1.966801, 2.154380, 2.456360, 3.039456",\ + "0.602858, 0.782869, 0.970682, 1.273098, 1.857066",\ + "0.631723, 0.811734, 0.999546, 1.301962, 1.885931",\ + "0.702765, 0.882776, 1.070589, 1.373005, 1.956973",\ + "0.958967, 1.138978, 1.326791, 1.629207, 2.213175",\ + "1.871626, 2.051637, 2.239450, 2.541866, 3.125834",\ + "0.678770, 0.858312, 1.045491, 1.347694, 1.931238",\ + "0.707635, 0.887177, 1.074355, 1.376559, 1.960103",\ + "0.778677, 0.958219, 1.145398, 1.447601, 2.031145",\ + "1.034879, 1.214422, 1.401600, 1.703804, 2.287347",\ + "1.947538, 2.127081, 2.314259, 2.616463, 3.200006",\ + "0.733139, 0.913064, 1.100379, 1.402300, 1.985556",\ + "0.762004, 0.941928, 1.129244, 1.431165, 2.014421",\ + "0.833046, 1.012970, 1.200286, 1.502207, 2.085463",\ + "1.089248, 1.269173, 1.456489, 1.758409, 2.341665",\ + "2.001907, 2.181832, 2.369148, 2.671068, 3.254324",\ + "1.014734, 1.198629, 1.384555, 1.686026, 2.268833",\ + "1.043599, 1.227494, 1.413420, 1.714891, 2.297698",\ + "1.114641, 1.298536, 1.484462, 1.785933, 2.368740",\ + "1.370843, 1.554738, 1.740664, 2.042135, 2.624942",\ + "2.283502, 2.467397, 2.653323, 2.954794, 3.537601"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.390477, 0.658088, 0.919489, 1.359266, 2.238427",\ + "0.413219, 0.680829, 0.942230, 1.382007, 2.261168",\ + "0.462500, 0.730110, 0.991511, 1.431288, 2.310449",\ + "0.628402, 0.896013, 1.157414, 1.597191, 2.476352",\ + "1.214556, 1.482167, 1.743568, 2.183345, 3.062506",\ + "0.479181, 0.746163, 1.008130, 1.447495, 2.325832",\ + "0.501923, 0.768904, 1.030871, 1.470236, 2.348573",\ + "0.551204, 0.818185, 1.080152, 1.519517, 2.397854",\ + "0.717106, 0.984088, 1.246055, 1.685420, 2.563757",\ + "1.303261, 1.570242, 1.832209, 2.271574, 3.149911",\ + "0.572124, 0.839483, 1.100174, 1.539741, 2.418874",\ + "0.594865, 0.862224, 1.122916, 1.562482, 2.441615",\ + "0.644146, 0.911506, 1.172197, 1.611763, 2.490896",\ + "0.810049, 1.077408, 1.338099, 1.777666, 2.656799",\ + "1.396203, 1.663562, 1.924254, 2.363820, 3.242953",\ + "0.637967, 0.908047, 1.167230, 1.606752, 2.485795",\ + "0.660708, 0.930789, 1.189972, 1.629493, 2.508537",\ + "0.709990, 0.980070, 1.239253, 1.678774, 2.557818",\ + "0.875892, 1.145972, 1.405155, 1.844677, 2.723721",\ + "1.462046, 1.732126, 1.991310, 2.430831, 3.309875",\ + "0.984489, 1.288883, 1.537901, 1.975978, 2.852131",\ + "1.007230, 1.311624, 1.560642, 1.998719, 2.874872",\ + "1.056511, 1.360905, 1.609924, 2.048000, 2.924153",\ + "1.222414, 1.526808, 1.775826, 2.213903, 3.090056",\ + "1.808568, 2.112962, 2.361980, 2.800057, 3.676210"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2483*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.426028, 0.689559, 0.965679, 1.433811, 2.368817",\ + "0.454893, 0.718424, 0.994544, 1.462676, 2.397682",\ + "0.525935, 0.789466, 1.065586, 1.533718, 2.468724",\ + "0.782137, 1.045668, 1.321788, 1.789921, 2.724926",\ + "1.694796, 1.958328, 2.234447, 2.702580, 3.637585",\ + "0.514222, 0.777100, 1.053246, 1.520527, 2.454750",\ + "0.543087, 0.805965, 1.082111, 1.549392, 2.483615",\ + "0.614129, 0.877007, 1.153153, 1.620434, 2.554657",\ + "0.870331, 1.133209, 1.409355, 1.876636, 2.810860",\ + "1.782991, 2.045868, 2.322014, 2.789295, 3.723519",\ + "0.602538, 0.866079, 1.141211, 1.608167, 2.541705",\ + "0.631403, 0.894944, 1.170076, 1.637032, 2.570570",\ + "0.702445, 0.965986, 1.241118, 1.708074, 2.641613",\ + "0.958647, 1.222188, 1.497320, 1.964276, 2.897815",\ + "1.871307, 2.134848, 2.409979, 2.876935, 3.810474",\ + "0.665034, 0.931713, 1.205350, 1.672256, 2.605214",\ + "0.693899, 0.960578, 1.234215, 1.701121, 2.634079",\ + "0.764941, 1.031620, 1.305257, 1.772163, 2.705122",\ + "1.021144, 1.287822, 1.561460, 2.028365, 2.961324",\ + "1.933803, 2.200481, 2.474119, 2.941024, 3.873983",\ + "0.994160, 1.296028, 1.557214, 2.021699, 2.950670",\ + "1.023025, 1.324893, 1.586079, 2.050565, 2.979536",\ + "1.094067, 1.395935, 1.657121, 2.121607, 3.050578",\ + "1.350269, 1.652137, 1.913324, 2.377809, 3.306780",\ + "2.262928, 2.564796, 2.825983, 3.290468, 4.219439"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223754, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713687, 0.713690, 0.713695",\ + "2.456796, 2.456796, 2.456794, 2.456788, 2.456778"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.373432, 0.555490, 0.751724, 1.060905, 1.655389",\ + "0.396174, 0.578231, 0.774465, 1.083646, 1.678130",\ + "0.445455, 0.627512, 0.823746, 1.132927, 1.727411",\ + "0.611357, 0.793415, 0.989649, 1.298831, 1.893319",\ + "1.197512, 1.379569, 1.575803, 1.884983, 2.479466",\ + "0.460847, 0.642809, 0.839005, 1.148210, 1.742743",\ + "0.483588, 0.665550, 0.861746, 1.170951, 1.765483",\ + "0.532870, 0.714831, 0.911027, 1.220232, 1.814765",\ + "0.698772, 0.880733, 1.076930, 1.386137, 1.980672",\ + "1.284926, 1.466888, 1.663084, 1.972288, 2.566819",\ + "0.541724, 0.723145, 0.919032, 1.228239, 1.822774",\ + "0.564465, 0.745886, 0.941773, 1.250980, 1.845515",\ + "0.613746, 0.795168, 0.991054, 1.300261, 1.894796",\ + "0.779648, 0.961070, 1.156957, 1.466165, 2.060704",\ + "1.365803, 1.547224, 1.743111, 2.052317, 2.646851",\ + "0.599370, 0.780982, 0.976767, 1.285709, 1.879870",\ + "0.622111, 0.803723, 0.999508, 1.308450, 1.902611",\ + "0.671392, 0.853004, 1.048790, 1.357731, 1.951892",\ + "0.837295, 1.018907, 1.214692, 1.523636, 2.117800",\ + "1.423449, 1.605061, 1.800846, 2.109787, 2.703947",\ + "0.901578, 1.086359, 1.280431, 1.588916, 2.182188",\ + "0.924319, 1.109100, 1.303172, 1.611657, 2.204929",\ + "0.973600, 1.158382, 1.352453, 1.660938, 2.254210",\ + "1.139503, 1.324284, 1.518356, 1.826843, 2.420118",\ + "1.725657, 1.910438, 2.104510, 2.412994, 3.006265"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444332, 0.444332, 0.444332, 0.444332, 0.444332",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518981"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2405*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.422050, 0.681609, 0.953245, 1.409407, 2.320577",\ + "0.450915, 0.710474, 0.982110, 1.438272, 2.349442",\ + "0.521957, 0.781516, 1.053152, 1.509314, 2.420484",\ + "0.778159, 1.037718, 1.309354, 1.765517, 2.676687",\ + "1.690818, 1.950378, 2.222013, 2.678175, 3.589345",\ + "0.510155, 0.769142, 1.040774, 1.496122, 2.406510",\ + "0.539020, 0.798007, 1.069638, 1.524987, 2.435376",\ + "0.610062, 0.869049, 1.140681, 1.596030, 2.506418",\ + "0.866264, 1.125251, 1.396883, 1.852232, 2.762620",\ + "1.778923, 2.037910, 2.309542, 2.764891, 3.675279",\ + "0.598185, 0.858106, 1.128738, 1.583761, 2.493465",\ + "0.627050, 0.886971, 1.157603, 1.612626, 2.522331",\ + "0.698092, 0.958013, 1.228645, 1.683668, 2.593373",\ + "0.954294, 1.214216, 1.484847, 1.939871, 2.849576",\ + "1.866953, 2.126875, 2.397506, 2.852530, 3.762234",\ + "0.660406, 0.923718, 1.192876, 1.647836, 2.556974",\ + "0.689271, 0.952582, 1.221740, 1.676701, 2.585840",\ + "0.760313, 1.023625, 1.292783, 1.747743, 2.656882",\ + "1.016515, 1.279827, 1.548985, 2.003945, 2.913085",\ + "1.929174, 2.192486, 2.461644, 2.916604, 3.825743",\ + "0.987793, 1.287766, 1.544618, 1.997222, 2.902431",\ + "1.016658, 1.316631, 1.573483, 2.026087, 2.931296",\ + "1.087700, 1.387673, 1.644525, 2.097129, 3.002338",\ + "1.343903, 1.643875, 1.900728, 2.353332, 3.258541",\ + "2.256562, 2.556535, 2.813386, 3.265991, 4.171199"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\ + "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\ + "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\ + "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766",\ + "0.043742, 0.043742, 0.043742, 0.043743, 0.043743",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091389",\ + "0.223754, 0.223754, 0.223755, 0.223755, 0.223756",\ + "0.713686, 0.713686, 0.713688, 0.713692, 0.713700",\ + "2.456796, 2.456795, 2.456792, 2.456783, 2.456766"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.371769, 0.553936, 0.750035, 1.059373, 1.654333",\ + "0.394510, 0.576677, 0.772776, 1.082114, 1.677074",\ + "0.443791, 0.625958, 0.822057, 1.131395, 1.726356",\ + "0.609694, 0.791861, 0.987960, 1.297299, 1.892264",\ + "1.195848, 1.378015, 1.574114, 1.883451, 2.478410",\ + "0.459189, 0.641255, 0.837315, 1.146678, 1.741687",\ + "0.481930, 0.663996, 0.860057, 1.169419, 1.764428",\ + "0.531211, 0.713277, 0.909338, 1.218700, 1.813709",\ + "0.697114, 0.879180, 1.075240, 1.384604, 1.979617",\ + "1.283268, 1.465334, 1.661394, 1.970756, 2.565764",\ + "0.540056, 0.721592, 0.917342, 1.226706, 1.821719",\ + "0.562797, 0.744333, 0.940084, 1.249447, 1.844460",\ + "0.612079, 0.793614, 0.989365, 1.298728, 1.893741",\ + "0.777981, 0.959517, 1.155267, 1.464633, 2.059649",\ + "1.364136, 1.545671, 1.741421, 2.050785, 2.645795",\ + "0.597695, 0.779428, 0.975078, 1.284177, 1.878815",\ + "0.620436, 0.802170, 0.997819, 1.306918, 1.901556",\ + "0.669718, 0.851451, 1.047100, 1.356200, 1.950837",\ + "0.835620, 1.017353, 1.213003, 1.522104, 2.116745",\ + "1.421774, 1.603508, 1.799157, 2.108255, 2.702892",\ + "0.899790, 1.084807, 1.278741, 1.587385, 2.181135",\ + "0.922531, 1.107548, 1.301482, 1.610126, 2.203876",\ + "0.971813, 1.156829, 1.350764, 1.659407, 2.253157",\ + "1.137715, 1.322732, 1.516666, 1.825311, 2.419065",\ + "1.723870, 1.908886, 2.102820, 2.411463, 3.005211"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982",\ + "0.037337, 0.037337, 0.037337, 0.037337, 0.037337",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066009",\ + "0.143976, 0.143976, 0.143976, 0.143976, 0.143976",\ + "0.444330, 0.444330, 0.444330, 0.444330, 0.444330",\ + "1.518979, 1.518979, 1.518979, 1.518980, 1.518982"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2343*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.514333, 0.692672, 0.873019, 1.159206, 1.709959",\ + "0.543198, 0.721537, 0.901884, 1.188071, 1.738824",\ + "0.614240, 0.792579, 0.972926, 1.259113, 1.809866",\ + "0.870442, 1.048782, 1.229129, 1.515315, 2.066068",\ + "1.783101, 1.961441, 2.141788, 2.427974, 2.978728",\ + "0.599271, 0.777508, 0.958089, 1.244712, 1.796337",\ + "0.628136, 0.806373, 0.986954, 1.273577, 1.825202",\ + "0.699178, 0.877415, 1.057996, 1.344619, 1.896244",\ + "0.955381, 1.133618, 1.314199, 1.600821, 2.152447",\ + "1.868040, 2.046277, 2.226858, 2.513480, 3.065106",\ + "0.675178, 0.852952, 1.032898, 1.319309, 1.870510",\ + "0.704042, 0.881817, 1.061763, 1.348174, 1.899375",\ + "0.775084, 0.952859, 1.132805, 1.419216, 1.970417",\ + "1.031287, 1.209061, 1.389008, 1.675418, 2.226619",\ + "1.943946, 2.121720, 2.301667, 2.588077, 3.139278",\ + "0.729530, 0.907697, 1.087764, 1.373903, 1.924827",\ + "0.758394, 0.936562, 1.116628, 1.402767, 1.953692",\ + "0.829437, 1.007604, 1.187670, 1.473809, 2.024734",\ + "1.085639, 1.263806, 1.443873, 1.730012, 2.280936",\ + "1.998298, 2.176466, 2.356532, 2.642671, 3.193595",\ + "1.010952, 1.193215, 1.371917, 1.657629, 2.208105",\ + "1.039816, 1.222079, 1.400781, 1.686494, 2.236969",\ + "1.110858, 1.293122, 1.471824, 1.757536, 2.308012",\ + "1.367061, 1.549324, 1.728026, 2.013738, 2.564214",\ + "2.279720, 2.461983, 2.640685, 2.926397, 3.476873"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796",\ + "0.043742, 0.043742, 0.043742, 0.043742, 0.043742",\ + "0.091388, 0.091388, 0.091388, 0.091388, 0.091388",\ + "0.223754, 0.223754, 0.223754, 0.223754, 0.223754",\ + "0.713686, 0.713686, 0.713686, 0.713686, 0.713686",\ + "2.456796, 2.456796, 2.456796, 2.456796, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.389041, 0.654041, 0.913070, 1.349334, 2.221481",\ + "0.411783, 0.676782, 0.935811, 1.372076, 2.244222",\ + "0.461064, 0.726063, 0.985092, 1.421357, 2.293503",\ + "0.626966, 0.891965, 1.150995, 1.587259, 2.459406",\ + "1.213121, 1.478120, 1.737149, 2.173413, 3.045560",\ + "0.477707, 0.742116, 1.001711, 1.437563, 2.308886",\ + "0.500448, 0.764857, 1.024452, 1.460304, 2.331627",\ + "0.549729, 0.814138, 1.073733, 1.509586, 2.380908",\ + "0.715632, 0.980040, 1.239636, 1.675488, 2.546811",\ + "1.301786, 1.566195, 1.825790, 2.261642, 3.132965",\ + "0.570514, 0.835409, 1.093746, 1.529807, 2.401928",\ + "0.593255, 0.858150, 1.116487, 1.552548, 2.424669",\ + "0.642536, 0.907431, 1.165769, 1.601829, 2.473950",\ + "0.808439, 1.073334, 1.331671, 1.767732, 2.639853",\ + "1.394593, 1.659488, 1.917825, 2.353886, 3.226007",\ + "0.636236, 0.903943, 1.160801, 1.596813, 2.468838",\ + "0.658977, 0.926684, 1.183542, 1.619554, 2.491579",\ + "0.708259, 0.975966, 1.232824, 1.668836, 2.540860",\ + "0.874161, 1.141868, 1.398726, 1.834738, 2.706763",\ + "1.460315, 1.728022, 1.984880, 2.420892, 3.292917",\ + "0.982026, 1.284442, 1.531439, 1.966014, 2.835165",\ + "1.004767, 1.307183, 1.554181, 1.988755, 2.857906",\ + "1.054048, 1.356464, 1.603462, 2.038037, 2.907187",\ + "1.219950, 1.522366, 1.769364, 2.203939, 3.073090",\ + "1.806105, 2.108521, 2.355518, 2.790093, 3.659244"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979",\ + "0.037338, 0.037338, 0.037338, 0.037338, 0.037338",\ + "0.066008, 0.066008, 0.066008, 0.066008, 0.066008",\ + "0.143978, 0.143978, 0.143978, 0.143978, 0.143978",\ + "0.444353, 0.444353, 0.444354, 0.444354, 0.444354",\ + "1.518979, 1.518979, 1.518979, 1.518979, 1.518979"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min_2288*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.142389, 0.171566, 0.243166, 0.499437, 1.411098",\ + "0.230574, 0.259751, 0.331362, 0.587680, 1.499024",\ + "0.318899, 0.348075, 0.419691, 0.676199, 1.587106",\ + "0.381491, 0.410664, 0.482232, 0.739031, 1.650402",\ + "0.711374, 0.740537, 0.811930, 1.069170, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\ + "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\ + "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\ + "0.043742, 0.091388, 0.223754, 0.713686, 2.456796",\ + "0.043742, 0.091388, 0.223754, 0.713686, 2.456796"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.180754, 0.203203, 0.252178, 0.417875, 1.004001",\ + "0.268158, 0.290607, 0.339581, 0.505279, 1.091404",\ + "0.349055, 0.371502, 0.420481, 0.586183, 1.172317",\ + "0.406718, 0.429160, 0.478148, 0.643857, 1.230008",\ + "0.709074, 0.731508, 0.780524, 0.946302, 1.532625"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.037339, 0.066008, 0.143979, 0.443541, 1.518445",\ + "0.037339, 0.066008, 0.143979, 0.443540, 1.518445",\ + "0.037339, 0.066008, 0.143979, 0.443540, 1.518243",\ + "0.037339, 0.066008, 0.143979, 0.443540, 1.517867",\ + "0.037339, 0.066008, 0.143978, 0.443540, 1.516694"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[5]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.083777, 0.113177, 0.184363, 0.440561, 1.354954",\ + "0.166191, 0.195837, 0.267192, 0.523277, 1.434794",\ + "0.254428, 0.286014, 0.357719, 0.613433, 1.527519",\ + "0.402853, 0.441150, 0.515777, 0.771236, 1.680856",\ + "0.639529, 0.694162, 0.784036, 1.036347, 1.943170"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.046241, 0.092638, 0.224458, 0.720967, 2.472405",\ + "0.047673, 0.093421, 0.224642, 0.721323, 2.472405",\ + "0.058846, 0.099756, 0.225481, 0.721323, 2.472405",\ + "0.087693, 0.120786, 0.231211, 0.721323, 2.472405",\ + "0.150701, 0.177706, 0.265097, 0.721323, 2.472405"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.115523, 0.139488, 0.190373, 0.357311, 0.943250",\ + "0.195424, 0.220107, 0.270909, 0.437012, 1.024824",\ + "0.295483, 0.321586, 0.373863, 0.540151, 1.127638",\ + "0.466222, 0.498877, 0.556261, 0.723129, 1.308255",\ + "0.739560, 0.788071, 0.862427, 1.035419, 1.617964"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.044606, 0.073777, 0.150227, 0.449909, 1.525255",\ + "0.044880, 0.073777, 0.150227, 0.449909, 1.525255",\ + "0.054859, 0.080811, 0.152895, 0.449909, 1.525255",\ + "0.083786, 0.105188, 0.168383, 0.450518, 1.525255",\ + "0.145006, 0.165847, 0.216404, 0.463154, 1.525255"); + } + + } /* end of arc padmux2ast_i[5]_obs_ctrl_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.079158, 0.108043, 0.179215, 0.434173, 1.346996",\ + "0.161067, 0.189991, 0.261053, 0.516828, 1.426491",\ + "0.245841, 0.276441, 0.347577, 0.603328, 1.515415",\ + "0.390269, 0.426632, 0.499915, 0.754138, 1.664120",\ + "0.617992, 0.669105, 0.755401, 1.006998, 1.912977"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.043983, 0.091336, 0.223341, 0.706536, 2.446538",\ + "0.045333, 0.091976, 0.223341, 0.711950, 2.446538",\ + "0.055328, 0.097699, 0.224823, 0.713717, 2.446538",\ + "0.081572, 0.117377, 0.229870, 0.714277, 2.457507",\ + "0.139013, 0.170652, 0.260149, 0.718737, 2.457507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.084172, 0.105801, 0.153856, 0.319168, 0.906380",\ + "0.169681, 0.191458, 0.239573, 0.404634, 0.995979",\ + "0.265868, 0.290580, 0.340403, 0.505279, 1.091202",\ + "0.427357, 0.458965, 0.514692, 0.679112, 1.262906",\ + "0.687739, 0.736091, 0.809895, 0.982075, 1.563284"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.001502, 0.004741, 0.013323, 0.044638, 0.156168"); + values ( "0.037000, 0.065831, 0.143664, 0.445190, 1.520147",\ + "0.037985, 0.066094, 0.143861, 0.445190, 1.520147",\ + "0.050092, 0.075267, 0.147407, 0.445190, 1.520147",\ + "0.078605, 0.099932, 0.163006, 0.448532, 1.520147",\ + "0.139198, 0.159714, 0.210091, 0.458787, 1.520147"); + } + + } /* end of arc padmux2ast_i[5]_obs_ctrl_o[5]_una_min*/ + +} /* end of pin obs_ctrl_o[5] */ + +pin("obs_ctrl_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.156168 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000989 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.556168, 0.736371, 0.923861, 1.225854, 1.809366",\ + "0.586766, 0.766969, 0.954459, 1.256451, 1.839963",\ + "0.658595, 0.838798, 1.026288, 1.328280, 1.911792",\ + "0.915054, 1.095257, 1.282747, 1.584739, 2.168251",\ + "1.830892, 2.011095, 2.198585, 2.500578, 3.084090",\ + "0.641107, 0.821654, 1.009870, 1.311866, 1.895744",\ + "0.671704, 0.852252, 1.040468, 1.342464, 1.926342",\ + "0.743533, 0.924081, 1.112296, 1.414292, 1.998170",\ + "0.999992, 1.180540, 1.368755, 1.670752, 2.254630",\ + "1.915831, 2.096378, 2.284594, 2.586590, 3.170468",\ + "0.717019, 0.897098, 1.084679, 1.386463, 1.969916",\ + "0.747616, 0.927695, 1.115276, 1.417060, 2.000514",\ + "0.819445, 0.999524, 1.187105, 1.488889, 2.072343",\ + "1.075904, 1.255983, 1.443564, 1.745348, 2.328802",\ + "1.991743, 2.171822, 2.359403, 2.661187, 3.244640",\ + "0.771388, 0.951609, 1.139330, 1.441003, 2.024234",\ + "0.801986, 0.982207, 1.169927, 1.471600, 2.054831",\ + "0.873814, 1.054036, 1.241756, 1.543429, 2.126660",\ + "1.130274, 1.310495, 1.498215, 1.799888, 2.383119",\ + "2.046112, 2.226333, 2.414054, 2.715726, 3.298958",\ + "1.052983, 1.236877, 1.423280, 1.724729, 2.307511",\ + "1.083580, 1.267475, 1.453878, 1.755327, 2.338109",\ + "1.155409, 1.339304, 1.525707, 1.827155, 2.409937",\ + "1.411868, 1.595763, 1.782166, 2.083614, 2.666397",\ + "2.327707, 2.511601, 2.698004, 2.999453, 3.582235"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.426989, 0.694775, 0.956355, 1.396052, 2.275447",\ + "0.452751, 0.720537, 0.982117, 1.421814, 2.301209",\ + "0.504153, 0.771939, 1.033519, 1.473216, 2.352611",\ + "0.670963, 0.938748, 1.200328, 1.640025, 2.519420",\ + "1.261262, 1.529048, 1.790628, 2.230325, 3.109720",\ + "0.515693, 0.782850, 1.044996, 1.484281, 2.362852",\ + "0.541455, 0.808612, 1.070758, 1.510043, 2.388614",\ + "0.592858, 0.860014, 1.122160, 1.561445, 2.440016",\ + "0.759667, 1.026823, 1.288969, 1.728255, 2.606825",\ + "1.349967, 1.617123, 1.879269, 2.318554, 3.197125",\ + "0.608636, 0.875995, 1.136721, 1.576445, 2.455894",\ + "0.634398, 0.901757, 1.162483, 1.602207, 2.481656",\ + "0.685800, 0.953159, 1.213886, 1.653610, 2.533058",\ + "0.852609, 1.119968, 1.380695, 1.820419, 2.699867",\ + "1.442909, 1.710268, 1.970994, 2.410718, 3.290167",\ + "0.674479, 0.944559, 1.203741, 1.643296, 2.522405",\ + "0.700241, 0.970321, 1.229503, 1.669058, 2.548167",\ + "0.751643, 1.021724, 1.280905, 1.720460, 2.599569",\ + "0.918453, 1.188533, 1.447715, 1.887269, 2.766378",\ + "1.508752, 1.778832, 2.038014, 2.477569, 3.356678",\ + "1.021001, 1.325395, 1.574404, 2.012450, 2.888541",\ + "1.046763, 1.351157, 1.600166, 2.038211, 2.914303",\ + "1.098165, 1.402559, 1.651568, 2.089614, 2.965705",\ + "1.264974, 1.569368, 1.818377, 2.256423, 3.132514",\ + "1.855274, 2.159668, 2.408677, 2.846723, 3.722814"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2724*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.464273, 0.727847, 1.004120, 1.472849, 2.410309",\ + "0.494871, 0.758445, 1.034717, 1.503447, 2.440906",\ + "0.566700, 0.830273, 1.106546, 1.575275, 2.512735",\ + "0.823159, 1.086733, 1.363005, 1.831734, 2.769193",\ + "1.738997, 2.002571, 2.278844, 2.747575, 3.685036",\ + "0.552468, 0.815388, 1.091687, 1.559565, 2.496242",\ + "0.583065, 0.845985, 1.122285, 1.590162, 2.526840",\ + "0.654894, 0.917814, 1.194114, 1.661991, 2.598668",\ + "0.911353, 1.174273, 1.450573, 1.918450, 2.855127",\ + "1.827192, 2.090112, 2.366412, 2.834290, 3.770969",\ + "0.640784, 0.904368, 1.179652, 1.647187, 2.583197",\ + "0.671381, 0.934966, 1.210250, 1.677785, 2.613795",\ + "0.743210, 1.006795, 1.282079, 1.749613, 2.685623",\ + "0.999669, 1.263254, 1.538538, 2.006072, 2.942082",\ + "1.915508, 2.179092, 2.454377, 2.921913, 3.857924",\ + "0.703280, 0.970003, 1.243792, 1.711101, 2.646706",\ + "0.733877, 1.000601, 1.274390, 1.741699, 2.677304",\ + "0.805706, 1.072430, 1.346218, 1.813527, 2.749132",\ + "1.062165, 1.328889, 1.602677, 2.069986, 3.005591",\ + "1.978004, 2.244727, 2.518517, 2.985826, 3.921433",\ + "1.032405, 1.334334, 1.595659, 2.060451, 2.992162",\ + "1.063003, 1.364932, 1.626257, 2.091048, 3.022760",\ + "1.134832, 1.436760, 1.698085, 2.162877, 3.094589",\ + "1.391291, 1.693219, 1.954545, 2.419336, 3.351047",\ + "2.307129, 2.609058, 2.870384, 3.335176, 4.266890"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715347, 0.715344, 0.715337",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.409942, 0.592374, 0.788766, 1.097819, 1.692625",\ + "0.435704, 0.618136, 0.814528, 1.123581, 1.718389",\ + "0.487107, 0.669538, 0.865930, 1.174984, 1.769791",\ + "0.653916, 0.836348, 1.032740, 1.341792, 1.936599",\ + "1.244215, 1.426647, 1.623039, 1.932092, 2.526900",\ + "0.497357, 0.679760, 0.876259, 1.185124, 1.779979",\ + "0.523119, 0.705522, 0.902021, 1.210886, 1.805742",\ + "0.574521, 0.756924, 0.953424, 1.262289, 1.857144",\ + "0.741330, 0.923733, 1.120233, 1.429098, 2.023953",\ + "1.331630, 1.514033, 1.710532, 2.019397, 2.614253",\ + "0.578233, 0.760096, 0.956286, 1.265153, 1.860010",\ + "0.603995, 0.785858, 0.982048, 1.290915, 1.885774",\ + "0.655398, 0.837260, 1.033450, 1.342317, 1.937176",\ + "0.822207, 1.004070, 1.200260, 1.509126, 2.103984",\ + "1.412507, 1.594369, 1.790559, 2.099426, 2.694285",\ + "0.635880, 0.817645, 1.013830, 1.322398, 1.916658",\ + "0.661642, 0.843407, 1.039592, 1.348160, 1.942421",\ + "0.713044, 0.894809, 1.090994, 1.399562, 1.993823",\ + "0.879853, 1.061618, 1.257803, 1.566371, 2.160632",\ + "1.470153, 1.651918, 1.848103, 2.156671, 2.750932",\ + "0.938088, 1.122869, 1.317464, 1.625412, 2.218504",\ + "0.963849, 1.148631, 1.343226, 1.651175, 2.244268",\ + "1.015252, 1.200033, 1.394628, 1.702577, 2.295670",\ + "1.182061, 1.366843, 1.561437, 1.869386, 2.462479",\ + "1.772361, 1.957142, 2.151737, 2.459686, 3.052779"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524057"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2651*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.460298, 0.719927, 0.991800, 1.448679, 2.362439",\ + "0.490896, 0.750525, 1.022397, 1.479277, 2.393037",\ + "0.562724, 0.822354, 1.094226, 1.551105, 2.464865",\ + "0.819184, 1.078813, 1.350685, 1.807564, 2.721324",\ + "1.735022, 1.994652, 2.266525, 2.723405, 3.637166",\ + "0.548403, 0.807461, 1.079330, 1.535395, 2.448373",\ + "0.579001, 0.838059, 1.109928, 1.565992, 2.478970",\ + "0.650829, 0.909887, 1.181756, 1.637821, 2.550799",\ + "0.907289, 1.166346, 1.438215, 1.894280, 2.807258",\ + "1.823127, 2.082185, 2.354055, 2.810120, 3.723099",\ + "0.636433, 0.896427, 1.167294, 1.623017, 2.535328",\ + "0.667031, 0.927024, 1.197892, 1.653615, 2.565925",\ + "0.738859, 0.998853, 1.269721, 1.725444, 2.637754",\ + "0.995319, 1.255312, 1.526180, 1.981903, 2.894213",\ + "1.911157, 2.171151, 2.442019, 2.897743, 3.810054",\ + "0.698654, 0.962040, 1.231432, 1.686931, 2.598837",\ + "0.729252, 0.992638, 1.262030, 1.717529, 2.629434",\ + "0.801081, 1.064467, 1.333858, 1.789357, 2.701263",\ + "1.057540, 1.320926, 1.590317, 2.045816, 2.957722",\ + "1.973378, 2.236765, 2.506157, 2.961657, 3.873563",\ + "1.026042, 1.326115, 1.583179, 2.036232, 2.944293",\ + "1.056639, 1.356713, 1.613777, 2.066829, 2.974890",\ + "1.128468, 1.428541, 1.685606, 2.138658, 3.046719",\ + "1.384927, 1.685001, 1.942065, 2.395117, 3.303178",\ + "2.300766, 2.600840, 2.857904, 3.310957, 4.219019"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217201, 0.217201, 0.217201, 0.217201",\ + "0.715349, 0.715349, 0.715346, 0.715340, 0.715328",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.408281, 0.590822, 0.787077, 1.096293, 1.691588",\ + "0.434043, 0.616584, 0.812839, 1.122056, 1.717351",\ + "0.485445, 0.667986, 0.864241, 1.173458, 1.768753",\ + "0.652254, 0.834795, 1.031050, 1.340267, 1.935562",\ + "1.242554, 1.425095, 1.621350, 1.930567, 2.525863",\ + "0.495701, 0.678207, 0.874570, 1.183598, 1.778941",\ + "0.521463, 0.703969, 0.900331, 1.209361, 1.804705",\ + "0.572865, 0.755371, 0.951734, 1.260763, 1.856107",\ + "0.739674, 0.922180, 1.118543, 1.427572, 2.022916",\ + "1.329974, 1.512480, 1.708843, 2.017872, 2.613216",\ + "0.576569, 0.758544, 0.954597, 1.263627, 1.858973",\ + "0.602330, 0.784306, 0.980358, 1.289389, 1.884737",\ + "0.653733, 0.835708, 1.031761, 1.340791, 1.936139",\ + "0.820542, 1.002517, 1.198570, 1.507600, 2.102947",\ + "1.410842, 1.592817, 1.788870, 2.097900, 2.693248",\ + "0.634207, 0.816093, 1.012141, 1.320872, 1.915620",\ + "0.659969, 0.841854, 1.037902, 1.346634, 1.941384",\ + "0.711372, 0.893257, 1.089304, 1.398036, 1.992786",\ + "0.878181, 1.060066, 1.256114, 1.564846, 2.159595",\ + "1.468480, 1.650366, 1.846413, 2.155146, 2.749895",\ + "0.936303, 1.121319, 1.315774, 1.623887, 2.217467",\ + "0.962064, 1.147081, 1.341536, 1.649649, 2.243231",\ + "1.013467, 1.198483, 1.392939, 1.701051, 2.294633",\ + "1.180276, 1.365292, 1.559748, 1.867860, 2.461442",\ + "1.770576, 1.955592, 2.150048, 2.458160, 3.051742"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058",\ + "0.040698, 0.040698, 0.040698, 0.040699, 0.040699",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070039",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524054, 1.524058"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2594*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.552582, 0.731009, 0.911269, 1.197475, 1.748592",\ + "0.583180, 0.761606, 0.941867, 1.228073, 1.779190",\ + "0.655008, 0.833435, 1.013695, 1.299902, 1.851019",\ + "0.911468, 1.089894, 1.270155, 1.556361, 2.107478",\ + "1.827306, 2.005733, 2.185993, 2.472199, 3.023317",\ + "0.637520, 0.816281, 0.997184, 1.283396, 1.834971",\ + "0.668118, 0.846879, 1.027782, 1.313993, 1.865568",\ + "0.739947, 0.918707, 1.099610, 1.385822, 1.937397",\ + "0.996406, 1.175167, 1.356070, 1.642281, 2.193856",\ + "1.912244, 2.091005, 2.271908, 2.558120, 3.109695",\ + "0.713426, 0.891724, 1.071993, 1.357992, 1.909143",\ + "0.744024, 0.922322, 1.102591, 1.388590, 1.939741",\ + "0.815853, 0.994151, 1.174419, 1.460419, 2.011569",\ + "1.072312, 1.250610, 1.430879, 1.716878, 2.268029",\ + "1.988150, 2.166448, 2.346717, 2.632716, 3.183867",\ + "0.767778, 0.946236, 1.126644, 1.412532, 1.963460",\ + "0.798376, 0.976834, 1.157242, 1.443130, 1.994058",\ + "0.870205, 1.048662, 1.229070, 1.514959, 2.065886",\ + "1.126664, 1.305122, 1.485530, 1.771418, 2.322346",\ + "2.042502, 2.220960, 2.401368, 2.687256, 3.238184",\ + "1.049200, 1.231463, 1.410595, 1.696259, 2.246738",\ + "1.079798, 1.262061, 1.441192, 1.726856, 2.277336",\ + "1.151627, 1.333890, 1.513021, 1.798685, 2.349164",\ + "1.408086, 1.590349, 1.769480, 2.055144, 2.605623",\ + "2.323924, 2.506187, 2.685318, 2.970983, 3.521462"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218",\ + "0.040033, 0.040033, 0.040033, 0.040033, 0.040033",\ + "0.086005, 0.086005, 0.086005, 0.086005, 0.086005",\ + "0.217202, 0.217202, 0.217202, 0.217202, 0.217202",\ + "0.715349, 0.715349, 0.715349, 0.715349, 0.715349",\ + "2.463218, 2.463218, 2.463218, 2.463218, 2.463218"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.425553, 0.690723, 0.949925, 1.386107, 2.258472",\ + "0.451315, 0.716485, 0.975687, 1.411869, 2.284234",\ + "0.502717, 0.767887, 1.027089, 1.463271, 2.335637",\ + "0.669527, 0.934696, 1.193898, 1.630080, 2.502446",\ + "1.259826, 1.524996, 1.784198, 2.220380, 3.092745",\ + "0.514219, 0.778798, 1.038566, 1.474336, 2.345878",\ + "0.539981, 0.804560, 1.064327, 1.500098, 2.371639",\ + "0.591383, 0.855962, 1.115730, 1.551500, 2.423042",\ + "0.758192, 1.022771, 1.282539, 1.718309, 2.589851",\ + "1.348492, 1.613071, 1.872839, 2.308609, 3.180151",\ + "0.607026, 0.871921, 1.130291, 1.566500, 2.438920",\ + "0.632787, 0.897683, 1.156053, 1.592262, 2.464681",\ + "0.684190, 0.949085, 1.207455, 1.643664, 2.516083",\ + "0.850999, 1.115894, 1.374264, 1.810474, 2.682893",\ + "1.441299, 1.706194, 1.964564, 2.400774, 3.273192",\ + "0.672748, 0.940455, 1.197311, 1.633351, 2.505431",\ + "0.698510, 0.966217, 1.223073, 1.659112, 2.531192",\ + "0.749912, 1.017619, 1.274475, 1.710515, 2.582595",\ + "0.916721, 1.184428, 1.441284, 1.877324, 2.749404",\ + "1.507021, 1.774728, 2.031584, 2.467624, 3.339704",\ + "1.018538, 1.320954, 1.567941, 2.002482, 2.871564",\ + "1.044299, 1.346715, 1.593703, 2.028244, 2.897326",\ + "1.095702, 1.398118, 1.645105, 2.079646, 2.948728",\ + "1.262511, 1.564927, 1.811914, 2.246455, 3.115537",\ + "1.852811, 2.155227, 2.402214, 2.836755, 3.705837"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052",\ + "0.040698, 0.040698, 0.040698, 0.040698, 0.040698",\ + "0.070039, 0.070039, 0.070039, 0.070039, 0.070038",\ + "0.145874, 0.145874, 0.145874, 0.145874, 0.145874",\ + "0.444024, 0.444024, 0.444024, 0.444024, 0.444024",\ + "1.524052, 1.524052, 1.524052, 1.524052, 1.524052"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_2534*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.319855, 0.350453, 0.422282, 0.678742, 1.594576",\ + "0.407246, 0.437844, 0.509673, 0.766133, 1.681967",\ + "0.488165, 0.518763, 0.590592, 0.847052, 1.762885",\ + "0.545906, 0.576503, 0.648333, 0.904793, 1.820624",\ + "0.849219, 0.879552, 0.951038, 1.207499, 2.123717"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.040034, 0.086005, 0.217203, 0.715311, 2.463217",\ + "0.040034, 0.086005, 0.217274, 0.715311, 2.463217",\ + "0.040034, 0.086006, 0.217512, 0.715311, 2.463317",\ + "0.040035, 0.086006, 0.217512, 0.715311, 2.463317",\ + "0.040226, 0.086033, 0.217850, 0.715337, 2.463779"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.305437, 0.331199, 0.382601, 0.549410, 1.139710",\ + "0.392830, 0.418591, 0.469994, 0.636803, 1.227103",\ + "0.473699, 0.499461, 0.550863, 0.717672, 1.307972",\ + "0.531348, 0.557110, 0.608512, 0.775321, 1.365621",\ + "0.834004, 0.859766, 0.911168, 1.077978, 1.668277"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\ + "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\ + "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\ + "0.040698, 0.070039, 0.145874, 0.444024, 1.524451",\ + "0.040713, 0.070039, 0.145879, 0.444024, 1.524451"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.513066, 0.693179, 0.880758, 1.182738, 1.765834",\ + "0.542527, 0.722641, 0.910219, 1.212199, 1.795295",\ + "0.613598, 0.793711, 0.981290, 1.283270, 1.866366",\ + "0.869826, 1.049940, 1.237518, 1.539498, 2.122594",\ + "1.786688, 1.966801, 2.154380, 2.456360, 3.039456",\ + "0.598004, 0.778015, 0.965828, 1.268244, 1.852212",\ + "0.627466, 0.807477, 0.995290, 1.297706, 1.881674",\ + "0.698536, 0.878547, 1.066360, 1.368776, 1.952744",\ + "0.954764, 1.134775, 1.322588, 1.625004, 2.208972",\ + "1.871626, 2.051637, 2.239450, 2.541866, 3.125834",\ + "0.673916, 0.853459, 1.040637, 1.342841, 1.926384",\ + "0.703378, 0.882920, 1.070099, 1.372302, 1.955846",\ + "0.774448, 0.953991, 1.141169, 1.443373, 2.026917",\ + "1.030676, 1.210219, 1.397397, 1.699601, 2.283145",\ + "1.947538, 2.127081, 2.314259, 2.616463, 3.200006",\ + "0.728285, 0.908210, 1.095526, 1.397446, 1.980702",\ + "0.757747, 0.937672, 1.124987, 1.426908, 2.010164",\ + "0.828817, 1.008742, 1.196058, 1.497978, 2.081234",\ + "1.085046, 1.264970, 1.452286, 1.754207, 2.337462",\ + "2.001907, 2.181832, 2.369148, 2.671068, 3.254324",\ + "1.009880, 1.193775, 1.379701, 1.681172, 2.263979",\ + "1.039342, 1.223237, 1.409163, 1.710634, 2.293441",\ + "1.110412, 1.294307, 1.480233, 1.781705, 2.364511",\ + "1.366640, 1.550535, 1.736461, 2.037933, 2.620739",\ + "2.283502, 2.467397, 2.653323, 2.954794, 3.537601"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456797, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.386409, 0.654020, 0.915421, 1.355198, 2.234359",\ + "0.410259, 0.677869, 0.939270, 1.379047, 2.258208",\ + "0.459812, 0.727422, 0.988823, 1.428600, 2.307761",\ + "0.625736, 0.893347, 1.154748, 1.594525, 2.473686",\ + "1.214590, 1.482201, 1.743601, 2.183378, 3.062539",\ + "0.475113, 0.742095, 1.004062, 1.443427, 2.321764",\ + "0.498963, 0.765944, 1.027911, 1.467276, 2.345613",\ + "0.548516, 0.815497, 1.077464, 1.516829, 2.395166",\ + "0.714441, 0.981422, 1.243389, 1.682754, 2.561091",\ + "1.303294, 1.570276, 1.832242, 2.271607, 3.149944",\ + "0.568056, 0.835415, 1.096106, 1.535673, 2.414806",\ + "0.591905, 0.859264, 1.119956, 1.559522, 2.438655",\ + "0.641458, 0.908817, 1.169509, 1.609075, 2.488208",\ + "0.807383, 1.074742, 1.335433, 1.775000, 2.654133",\ + "1.396236, 1.663596, 1.924287, 2.363853, 3.242986",\ + "0.633899, 0.903979, 1.163162, 1.602684, 2.481728",\ + "0.657749, 0.927829, 1.187012, 1.626534, 2.505577",\ + "0.707301, 0.977382, 1.236565, 1.676086, 2.555130",\ + "0.873226, 1.143306, 1.402490, 1.842011, 2.721055",\ + "1.462080, 1.732160, 1.991343, 2.430865, 3.309908",\ + "0.980421, 1.284815, 1.533833, 1.971910, 2.848063",\ + "1.004270, 1.308664, 1.557683, 1.995759, 2.871912",\ + "1.053823, 1.358217, 1.607235, 2.045312, 2.921465",\ + "1.219748, 1.524142, 1.773160, 2.211237, 3.087390",\ + "1.808601, 2.112996, 2.362014, 2.800090, 3.676243"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2475*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.421174, 0.684705, 0.960825, 1.428958, 2.363963",\ + "0.450636, 0.714167, 0.990287, 1.458419, 2.393425",\ + "0.521706, 0.785238, 1.061357, 1.529490, 2.464495",\ + "0.777934, 1.041466, 1.317585, 1.785718, 2.720724",\ + "1.694796, 1.958328, 2.234447, 2.702580, 3.637585",\ + "0.509368, 0.772246, 1.048392, 1.515673, 2.449897",\ + "0.538830, 0.801708, 1.077854, 1.545135, 2.479358",\ + "0.609900, 0.872778, 1.148924, 1.616205, 2.550429",\ + "0.866129, 1.129006, 1.405152, 1.872433, 2.806657",\ + "1.782991, 2.045868, 2.322014, 2.789295, 3.723519",\ + "0.597685, 0.861225, 1.136357, 1.603313, 2.536852",\ + "0.627146, 0.890687, 1.165819, 1.632775, 2.566314",\ + "0.698217, 0.961758, 1.236889, 1.703845, 2.637384",\ + "0.954445, 1.217986, 1.493117, 1.960074, 2.893612",\ + "1.871307, 2.134848, 2.409979, 2.876935, 3.810474",\ + "0.660181, 0.926859, 1.200497, 1.667402, 2.600361",\ + "0.689642, 0.956321, 1.229958, 1.696864, 2.629822",\ + "0.760713, 1.027391, 1.301029, 1.767934, 2.700893",\ + "1.016941, 1.283619, 1.557257, 2.024162, 2.957121",\ + "1.933803, 2.200481, 2.474119, 2.941024, 3.873983",\ + "0.989306, 1.291174, 1.552361, 2.016846, 2.945817",\ + "1.018768, 1.320636, 1.581822, 2.046308, 2.975279",\ + "1.089838, 1.391706, 1.652893, 2.117378, 3.046349",\ + "1.346066, 1.647934, 1.909121, 2.373606, 3.302577",\ + "2.262928, 2.564796, 2.825983, 3.290468, 4.219439"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778",\ + "0.036484, 0.036484, 0.036484, 0.036485, 0.036485",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705642, 0.705647",\ + "2.456797, 2.456796, 2.456794, 2.456789, 2.456778"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.369364, 0.551422, 0.747656, 1.056837, 1.651321",\ + "0.393214, 0.575271, 0.771505, 1.080686, 1.675170",\ + "0.442767, 0.624824, 0.821058, 1.130239, 1.724723",\ + "0.608691, 0.790749, 0.986983, 1.296166, 1.890653",\ + "1.197545, 1.379603, 1.575836, 1.885017, 2.479500",\ + "0.456779, 0.638740, 0.834936, 1.144142, 1.738674",\ + "0.480629, 0.662590, 0.858786, 1.167991, 1.762524",\ + "0.530181, 0.712143, 0.908339, 1.217544, 1.812076",\ + "0.696106, 0.878068, 1.074264, 1.383471, 1.978007",\ + "1.284960, 1.466921, 1.663117, 1.972322, 2.566853",\ + "0.537655, 0.719077, 0.914963, 1.224170, 1.818706",\ + "0.561505, 0.742927, 0.938813, 1.248020, 1.842555",\ + "0.611058, 0.792479, 0.988366, 1.297573, 1.892108",\ + "0.776982, 0.958404, 1.154291, 1.463499, 2.058038",\ + "1.365836, 1.547258, 1.743144, 2.052350, 2.646885",\ + "0.595302, 0.776914, 0.972699, 1.281641, 1.875802",\ + "0.619151, 0.800763, 0.996549, 1.305490, 1.899651",\ + "0.668704, 0.850316, 1.046101, 1.355043, 1.949204",\ + "0.834629, 1.016241, 1.212026, 1.520970, 2.115134",\ + "1.423483, 1.605095, 1.800880, 2.109821, 2.703980",\ + "0.897509, 1.082291, 1.276362, 1.584848, 2.178120",\ + "0.921359, 1.106141, 1.300212, 1.608697, 2.201969",\ + "0.970912, 1.155693, 1.349765, 1.658250, 2.251522",\ + "1.136837, 1.321618, 1.515690, 1.824177, 2.417452",\ + "1.725690, 1.910472, 2.104543, 2.413028, 3.006299"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439438, 0.439438, 0.439438, 0.439438, 0.439438",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519042"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2397*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.417196, 0.676755, 0.948391, 1.404553, 2.315723",\ + "0.446658, 0.706217, 0.977853, 1.434015, 2.345185",\ + "0.517728, 0.777287, 1.048923, 1.505085, 2.416255",\ + "0.773956, 1.033516, 1.305151, 1.761314, 2.672484",\ + "1.690818, 1.950378, 2.222013, 2.678175, 3.589345",\ + "0.505301, 0.764288, 1.035920, 1.491269, 2.401657",\ + "0.534763, 0.793750, 1.065382, 1.520731, 2.431119",\ + "0.605833, 0.864820, 1.136452, 1.591801, 2.502189",\ + "0.862061, 1.121048, 1.392680, 1.848029, 2.758418",\ + "1.778923, 2.037910, 2.309542, 2.764891, 3.675279",\ + "0.593331, 0.853252, 1.123884, 1.578908, 2.488612",\ + "0.622793, 0.882714, 1.153346, 1.608370, 2.518074",\ + "0.693863, 0.953785, 1.224416, 1.679440, 2.589144",\ + "0.950091, 1.210013, 1.480644, 1.935668, 2.845373",\ + "1.866953, 2.126875, 2.397506, 2.852530, 3.762234",\ + "0.655552, 0.918864, 1.188022, 1.642982, 2.552121",\ + "0.685014, 0.948326, 1.217484, 1.672444, 2.581583",\ + "0.756084, 1.019396, 1.288554, 1.743514, 2.652653",\ + "1.012312, 1.275624, 1.544782, 1.999743, 2.908882",\ + "1.929174, 2.192486, 2.461644, 2.916604, 3.825743",\ + "0.982940, 1.282912, 1.539764, 1.992368, 2.897577",\ + "1.012401, 1.312374, 1.569226, 2.021830, 2.927039",\ + "1.083472, 1.383444, 1.640296, 2.092901, 2.998109",\ + "1.339700, 1.639673, 1.896525, 2.349129, 3.254338",\ + "2.256562, 2.556535, 2.813386, 3.265991, 4.171199"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\ + "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\ + "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\ + "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\ + "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\ + "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\ + "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705640, 0.705645, 0.705653",\ + "2.456797, 2.456796, 2.456792, 2.456783, 2.456766",\ + "0.036484, 0.036484, 0.036485, 0.036485, 0.036486",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215721",\ + "0.705638, 0.705639, 0.705641, 0.705645, 0.705653",\ + "2.456797, 2.456795, 2.456792, 2.456783, 2.456766"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.367701, 0.549868, 0.745966, 1.055305, 1.650265",\ + "0.391550, 0.573717, 0.769816, 1.079154, 1.674115",\ + "0.441103, 0.623270, 0.819369, 1.128707, 1.723667",\ + "0.607028, 0.789195, 0.985294, 1.294634, 1.889598",\ + "1.195881, 1.378049, 1.574147, 1.883484, 2.478444",\ + "0.455121, 0.637187, 0.833247, 1.142610, 1.737619",\ + "0.478970, 0.661036, 0.857097, 1.166459, 1.761468",\ + "0.528523, 0.710589, 0.906649, 1.216012, 1.811021",\ + "0.694448, 0.876514, 1.072575, 1.381939, 1.976952",\ + "1.283301, 1.465367, 1.661428, 1.970789, 2.565797",\ + "0.535988, 0.717524, 0.913274, 1.222638, 1.817651",\ + "0.559838, 0.741373, 0.937124, 1.246487, 1.841500",\ + "0.609390, 0.790926, 0.986676, 1.296040, 1.891052",\ + "0.775315, 0.956851, 1.152602, 1.461967, 2.056983",\ + "1.364169, 1.545704, 1.741455, 2.050818, 2.645829",\ + "0.593627, 0.775360, 0.971009, 1.280109, 1.874747",\ + "0.617477, 0.799210, 0.994859, 1.303958, 1.898596",\ + "0.667029, 0.848763, 1.044412, 1.353511, 1.948149",\ + "0.832954, 1.014688, 1.210337, 1.519438, 2.114080",\ + "1.421808, 1.603541, 1.799190, 2.108289, 2.702925",\ + "0.895722, 1.080739, 1.274673, 1.583317, 2.177067",\ + "0.919572, 1.104588, 1.298523, 1.607166, 2.200916",\ + "0.969124, 1.154141, 1.348075, 1.656719, 2.250468",\ + "1.135049, 1.320066, 1.514001, 1.822646, 2.416399",\ + "1.723903, 1.908919, 2.102854, 2.411496, 3.005245"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043",\ + "0.032902, 0.032902, 0.032902, 0.032902, 0.032902",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061454",\ + "0.139113, 0.139113, 0.139113, 0.139113, 0.139113",\ + "0.439435, 0.439435, 0.439435, 0.439435, 0.439435",\ + "1.519040, 1.519040, 1.519040, 1.519041, 1.519043"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2338*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + related_output_pin : "obs_ctrl_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.509479, 0.687819, 0.868166, 1.154352, 1.705105",\ + "0.538941, 0.717281, 0.897627, 1.183814, 1.734567",\ + "0.610011, 0.788351, 0.968698, 1.254884, 1.805637",\ + "0.866239, 1.044579, 1.224926, 1.511112, 2.061866",\ + "1.783101, 1.961441, 2.141788, 2.427974, 2.978728",\ + "0.594418, 0.772655, 0.953236, 1.239858, 1.791484",\ + "0.623879, 0.802116, 0.982697, 1.269320, 1.820946",\ + "0.694950, 0.873187, 1.053768, 1.340390, 1.892016",\ + "0.951178, 1.129415, 1.309996, 1.596619, 2.148244",\ + "1.868040, 2.046277, 2.226858, 2.513480, 3.065106",\ + "0.670324, 0.848098, 1.028045, 1.314455, 1.865656",\ + "0.699786, 0.877560, 1.057506, 1.343917, 1.895118",\ + "0.770856, 0.948630, 1.128577, 1.414987, 1.966188",\ + "1.027084, 1.204858, 1.384805, 1.671215, 2.222416",\ + "1.943946, 2.121720, 2.301667, 2.588077, 3.139278",\ + "0.724676, 0.902843, 1.082910, 1.369049, 1.919973",\ + "0.754138, 0.932305, 1.112372, 1.398511, 1.949435",\ + "0.825208, 1.003376, 1.183442, 1.469581, 2.020505",\ + "1.081436, 1.259604, 1.439670, 1.725809, 2.276733",\ + "1.998298, 2.176466, 2.356532, 2.642671, 3.193595",\ + "1.006098, 1.188361, 1.367063, 1.652775, 2.203251",\ + "1.035560, 1.217823, 1.396525, 1.682237, 2.232713",\ + "1.106630, 1.288893, 1.467595, 1.753307, 2.303783",\ + "1.362858, 1.545121, 1.723823, 2.009535, 2.560011",\ + "2.279720, 2.461983, 2.640685, 2.926397, 3.476873"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796",\ + "0.036484, 0.036484, 0.036484, 0.036484, 0.036484",\ + "0.083490, 0.083490, 0.083490, 0.083490, 0.083490",\ + "0.215720, 0.215720, 0.215720, 0.215720, 0.215720",\ + "0.705638, 0.705638, 0.705638, 0.705638, 0.705639",\ + "2.456797, 2.456797, 2.456797, 2.456796, 2.456796"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.384973, 0.649972, 0.909002, 1.345266, 2.217413",\ + "0.408823, 0.673822, 0.932851, 1.369116, 2.241262",\ + "0.458376, 0.723375, 0.982404, 1.418669, 2.290815",\ + "0.624300, 0.889300, 1.148329, 1.584594, 2.456740",\ + "1.213154, 1.478153, 1.737183, 2.173447, 3.045593",\ + "0.473639, 0.738047, 0.997643, 1.433495, 2.304818",\ + "0.497488, 0.761897, 1.021492, 1.457345, 2.328667",\ + "0.547041, 0.811450, 1.071045, 1.506897, 2.378220",\ + "0.712966, 0.977375, 1.236970, 1.672822, 2.544145",\ + "1.301819, 1.566228, 1.825824, 2.261676, 3.132998",\ + "0.566446, 0.831341, 1.089678, 1.525738, 2.397860",\ + "0.590295, 0.855190, 1.113528, 1.549588, 2.421709",\ + "0.639848, 0.904743, 1.163080, 1.599141, 2.471262",\ + "0.805773, 1.070668, 1.329005, 1.765066, 2.637187",\ + "1.394626, 1.659522, 1.917859, 2.353919, 3.226040",\ + "0.632168, 0.899875, 1.156733, 1.592745, 2.464769",\ + "0.656018, 0.923725, 1.180583, 1.616595, 2.488619",\ + "0.705570, 0.973277, 1.230135, 1.666147, 2.538172",\ + "0.871495, 1.139202, 1.396060, 1.832072, 2.704097",\ + "1.460349, 1.728056, 1.984914, 2.420926, 3.292950",\ + "0.977957, 1.280373, 1.527371, 1.961946, 2.831096",\ + "1.001807, 1.304223, 1.551221, 1.985796, 2.854946",\ + "1.051360, 1.353776, 1.600773, 2.035348, 2.904499",\ + "1.217285, 1.519701, 1.766698, 2.201273, 3.070424",\ + "1.806138, 2.108554, 2.355552, 2.790127, 3.659277"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + index_3 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040",\ + "0.032904, 0.032904, 0.032904, 0.032904, 0.032904",\ + "0.061453, 0.061453, 0.061453, 0.061453, 0.061453",\ + "0.139114, 0.139114, 0.139114, 0.139114, 0.139114",\ + "0.439459, 0.439459, 0.439459, 0.439459, 0.439460",\ + "1.519040, 1.519040, 1.519040, 1.519040, 1.519040"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min_2281*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.137483, 0.167263, 0.238963, 0.495239, 1.411098",\ + "0.225669, 0.255448, 0.327158, 0.583483, 1.499024",\ + "0.313993, 0.343772, 0.415484, 0.672004, 1.587106",\ + "0.376583, 0.406365, 0.478019, 0.734834, 1.650402",\ + "0.706456, 0.736253, 0.807711, 1.064965, 1.982165"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\ + "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\ + "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\ + "0.036484, 0.083490, 0.215720, 0.705638, 2.456797",\ + "0.036484, 0.083490, 0.215720, 0.705638, 2.456797"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.176752, 0.200264, 0.249493, 0.415210, 1.004034",\ + "0.264156, 0.287668, 0.336897, 0.502613, 1.091438",\ + "0.345055, 0.368563, 0.417796, 0.583517, 1.172351",\ + "0.402719, 0.426221, 0.475463, 0.641191, 1.230042",\ + "0.705079, 0.728567, 0.777838, 0.943636, 1.532658"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.032905, 0.061452, 0.139114, 0.438652, 1.518506",\ + "0.032905, 0.061452, 0.139114, 0.438651, 1.518506",\ + "0.032905, 0.061452, 0.139114, 0.438651, 1.518304",\ + "0.032905, 0.061452, 0.139114, 0.438651, 1.517928",\ + "0.032905, 0.061452, 0.139114, 0.438651, 1.516755"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[4]_redg_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.078780, 0.108904, 0.180162, 0.436350, 1.354954",\ + "0.161131, 0.191551, 0.262992, 0.519079, 1.434794",\ + "0.248818, 0.281701, 0.353526, 0.609224, 1.527520",\ + "0.395442, 0.436624, 0.511587, 0.767048, 1.680857",\ + "0.628254, 0.688519, 0.779900, 1.032171, 1.943170"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.039260, 0.084846, 0.216310, 0.712907, 2.472405",\ + "0.040828, 0.085695, 0.216652, 0.713345, 2.472405",\ + "0.053126, 0.092383, 0.217457, 0.713345, 2.472405",\ + "0.083384, 0.114454, 0.223298, 0.713345, 2.472405",\ + "0.146832, 0.172946, 0.257648, 0.713345, 2.472405"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.111195, 0.136417, 0.187667, 0.354647, 0.943283",\ + "0.190886, 0.217040, 0.268217, 0.434338, 1.024857",\ + "0.290624, 0.318413, 0.371169, 0.537479, 1.127671",\ + "0.459778, 0.495342, 0.553556, 0.720468, 1.308289",\ + "0.729543, 0.783345, 0.859617, 1.032769, 1.617997"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.039937, 0.069327, 0.145375, 0.445019, 1.525316",\ + "0.040361, 0.069327, 0.145375, 0.445019, 1.525316",\ + "0.050876, 0.076651, 0.148151, 0.445019, 1.525316",\ + "0.080615, 0.101623, 0.163833, 0.445639, 1.525316",\ + "0.141343, 0.163058, 0.212463, 0.458329, 1.525316"); + } + + } /* end of arc padmux2ast_i[4]_obs_ctrl_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.074275, 0.103763, 0.175018, 0.429970, 1.346996",\ + "0.156202, 0.185726, 0.256855, 0.512618, 1.426492",\ + "0.240487, 0.272170, 0.343383, 0.599128, 1.515415",\ + "0.383350, 0.422200, 0.495747, 0.749948, 1.664120",\ + "0.607487, 0.663633, 0.751277, 1.002826, 1.912977"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.036818, 0.083430, 0.215329, 0.698468, 2.446538",\ + "0.038327, 0.084129, 0.215329, 0.703907, 2.446538",\ + "0.049194, 0.090132, 0.216807, 0.705668, 2.446538",\ + "0.076596, 0.110889, 0.221927, 0.706146, 2.457507",\ + "0.133978, 0.165656, 0.252644, 0.710730, 2.457507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.080352, 0.102927, 0.151178, 0.316498, 0.906413",\ + "0.165823, 0.188579, 0.236900, 0.401944, 0.996012",\ + "0.261266, 0.287577, 0.337732, 0.502614, 1.091236",\ + "0.421122, 0.455539, 0.512029, 0.676457, 1.262940",\ + "0.677737, 0.731402, 0.807099, 0.979432, 1.563317"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000989, 0.004228, 0.012809, 0.044125, 0.156168"); + values ( "0.032503, 0.061295, 0.138759, 0.440292, 1.520208",\ + "0.033685, 0.061572, 0.138902, 0.440292, 1.520208",\ + "0.046324, 0.071119, 0.142587, 0.440292, 1.520208",\ + "0.075437, 0.096388, 0.158394, 0.443652, 1.520208",\ + "0.135609, 0.156947, 0.206102, 0.453960, 1.520208"); + } + + } /* end of arc padmux2ast_i[4]_obs_ctrl_o[4]_una_min*/ + +} /* end of pin obs_ctrl_o[4] */ + +pin("obs_ctrl_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.644672 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001495 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.055709, 0.210088, 0.384212, 0.703085, 1.340832",\ + "0.142647, 0.298162, 0.472853, 0.791314, 1.428237",\ + "0.229323, 0.390455, 0.564578, 0.883479, 1.521279",\ + "0.289539, 0.457859, 0.631598, 0.950329, 1.587790",\ + "0.602001, 0.825705, 1.001142, 1.318707, 1.953837"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.024618, 0.296918, 0.628376, 1.238420, 2.458509",\ + "0.028418, 0.296918, 0.628376, 1.238420, 2.458509",\ + "0.041905, 0.299457, 0.628376, 1.238420, 2.458509",\ + "0.054019, 0.302915, 0.628376, 1.238420, 2.458509",\ + "0.127335, 0.341609, 0.634026, 1.242336, 2.458956"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.067216, 0.173388, 0.285052, 0.487701, 0.892999",\ + "0.152154, 0.258224, 0.370122, 0.573207, 0.979377",\ + "0.227820, 0.333667, 0.444931, 0.647804, 1.053549",\ + "0.281475, 0.388179, 0.499582, 0.702344, 1.107867",\ + "0.555896, 0.671760, 0.783533, 0.986070, 1.391144"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.022975, 0.185702, 0.382816, 0.754065, 1.496563",\ + "0.022975, 0.186685, 0.385279, 0.756173, 1.496563",\ + "0.023515, 0.186685, 0.385279, 0.756173, 1.496563",\ + "0.025086, 0.186685, 0.385279, 0.756173, 1.496563",\ + "0.040851, 0.190393, 0.385279, 0.756173, 1.496563"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.055709, 0.210088, 0.384212, 0.703085, 1.340832",\ + "0.142647, 0.298162, 0.472853, 0.791314, 1.428237",\ + "0.229323, 0.390455, 0.564578, 0.883479, 1.521279",\ + "0.289539, 0.457859, 0.631598, 0.950329, 1.587790",\ + "0.602001, 0.825705, 1.001142, 1.318707, 1.953837"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.024618, 0.296396, 0.626543, 1.236834, 2.455429",\ + "0.028418, 0.296396, 0.626543, 1.236834, 2.455429",\ + "0.041905, 0.299457, 0.628154, 1.237245, 2.455429",\ + "0.054019, 0.302915, 0.628337, 1.238058, 2.457501",\ + "0.127335, 0.341609, 0.634026, 1.242336, 2.458956"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.067216, 0.173388, 0.285052, 0.487701, 0.892999",\ + "0.152154, 0.258224, 0.370122, 0.573207, 0.979377",\ + "0.227820, 0.333667, 0.444931, 0.647804, 1.053549",\ + "0.281475, 0.388179, 0.499582, 0.702344, 1.107867",\ + "0.555896, 0.671760, 0.783533, 0.986070, 1.391144"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001495, 0.074796, 0.162290, 0.323084, 0.644672"); + values ( "0.022975, 0.185506, 0.382814, 0.754047, 1.494909",\ + "0.022975, 0.185506, 0.382814, 0.754047, 1.494909",\ + "0.023515, 0.185506, 0.382814, 0.754047, 1.494909",\ + "0.025086, 0.186032, 0.383438, 0.754322, 1.494909",\ + "0.040851, 0.190393, 0.384028, 0.754322, 1.494909"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024618, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.205304, 0.155898, 0.121844, 0.108632, 0.118959",\ + "0.213705, 0.164299, 0.130245, 0.117033, 0.127360",\ + "0.286247, 0.236842, 0.202788, 0.189576, 0.199902",\ + "0.377880, 0.328444, 0.294355, 0.281122, 0.291373",\ + "0.826990, 0.777305, 0.742923, 0.729519, 0.739150"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022975, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.253248, 0.179609, 0.114078, 0.098860, 0.242765",\ + "0.260428, 0.186789, 0.121258, 0.106040, 0.249945",\ + "0.338311, 0.264672, 0.199141, 0.183923, 0.327828",\ + "0.439285, 0.365564, 0.300030, 0.284860, 0.429362",\ + "0.945572, 0.871138, 0.805582, 0.790828, 0.940493"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024618, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131653, -0.089547, -0.055448, -0.032345, 0.077315",\ + "-0.140054, -0.097948, -0.063849, -0.040746, 0.068914",\ + "-0.212597, -0.170490, -0.136392, -0.113288, -0.003629",\ + "-0.304160, -0.262036, -0.227893, -0.204765, -0.095035",\ + "-0.752635, -0.710363, -0.675857, -0.652532, -0.542218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022975, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.160975, -0.096153, -0.041987, -0.003573, 0.191467",\ + "-0.168149, -0.103327, -0.049161, -0.010747, 0.184293",\ + "-0.246073, -0.181251, -0.127085, -0.088671, 0.106369",\ + "-0.346978, -0.282082, -0.227737, -0.189269, 0.005504",\ + "-0.852619, -0.787096, -0.731202, -0.692284, -0.499800"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[3]_hldr*/ + +} /* end of pin obs_ctrl_o[3] */ + +pin("obs_ctrl_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001426 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.046598, 0.200037, 0.375695, 0.698745, 1.344843",\ + "0.132827, 0.287212, 0.462802, 0.785460, 1.430777",\ + "0.215641, 0.375341, 0.550758, 0.873083, 1.517732",\ + "0.273163, 0.439738, 0.614874, 0.936996, 1.581241",\ + "0.570794, 0.789601, 0.965263, 1.285741, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.021974, 0.297548, 0.631352, 1.248422, 2.482564",\ + "0.026714, 0.298523, 0.633308, 1.248422, 2.482564",\ + "0.039895, 0.300798, 0.633344, 1.248422, 2.482564",\ + "0.051772, 0.304107, 0.633444, 1.248422, 2.482564",\ + "0.126971, 0.342744, 0.639709, 1.250989, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.066407, 0.172211, 0.283842, 0.488142, 0.896743",\ + "0.153827, 0.259530, 0.371123, 0.575447, 0.984097",\ + "0.234160, 0.339867, 0.451150, 0.655476, 1.064128",\ + "0.290795, 0.397415, 0.508694, 0.712721, 1.120776",\ + "0.584007, 0.700750, 0.812328, 1.015736, 1.422553"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.023136, 0.186125, 0.386812, 0.759343, 1.504406",\ + "0.023136, 0.186266, 0.387317, 0.759343, 1.504406",\ + "0.024272, 0.186266, 0.387317, 0.759343, 1.504406",\ + "0.026405, 0.186266, 0.387317, 0.759343, 1.504406",\ + "0.045271, 0.190284, 0.387317, 0.759343, 1.504686"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.046598, 0.200037, 0.375695, 0.698745, 1.344843",\ + "0.132827, 0.287212, 0.462802, 0.785460, 1.430777",\ + "0.215641, 0.375341, 0.550758, 0.873083, 1.517732",\ + "0.273163, 0.439738, 0.614874, 0.936996, 1.581241",\ + "0.570794, 0.789601, 0.965263, 1.285741, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.021974, 0.297548, 0.631352, 1.247199, 2.473548",\ + "0.026714, 0.298523, 0.633308, 1.247199, 2.473548",\ + "0.039895, 0.300798, 0.633344, 1.247274, 2.473548",\ + "0.051772, 0.304107, 0.633444, 1.248017, 2.473548",\ + "0.126971, 0.342744, 0.639709, 1.250989, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.066407, 0.172211, 0.283842, 0.488142, 0.896743",\ + "0.153827, 0.259530, 0.371123, 0.575447, 0.984097",\ + "0.234160, 0.339867, 0.451150, 0.655476, 1.064128",\ + "0.290795, 0.397415, 0.508694, 0.712721, 1.120776",\ + "0.584007, 0.700750, 0.812328, 1.015736, 1.422553"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001426, 0.074424, 0.161572, 0.321718, 0.642011"); + values ( "0.023136, 0.185331, 0.385307, 0.757114, 1.500729",\ + "0.023136, 0.185331, 0.385307, 0.757114, 1.500729",\ + "0.024272, 0.185331, 0.385307, 0.757114, 1.500729",\ + "0.026405, 0.185943, 0.385763, 0.758015, 1.502520",\ + "0.045271, 0.190284, 0.385833, 0.758784, 1.504686"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.021974, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215002, 0.169073, 0.138873, 0.127530, 0.141215",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023136, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.249950, 0.174629, 0.106470, 0.083503, 0.146416",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.021974, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.146929, -0.104512, -0.070025, -0.030602, 0.275445",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023136, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163106, -0.097191, -0.039532, 0.002429, 0.223037",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[2]_hldr*/ + +} /* end of pin obs_ctrl_o[2] */ + +pin("obs_ctrl_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001497 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.046791, 0.200181, 0.375803, 0.698817, 1.344843",\ + "0.133030, 0.287356, 0.462909, 0.785532, 1.430777",\ + "0.215892, 0.375484, 0.550866, 0.873154, 1.517732",\ + "0.273461, 0.439881, 0.614982, 0.937068, 1.581241",\ + "0.571381, 0.789745, 0.965369, 1.285812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.022232, 0.297820, 0.631558, 1.248559, 2.482564",\ + "0.026946, 0.298797, 0.633513, 1.248559, 2.482564",\ + "0.040098, 0.301070, 0.633549, 1.248559, 2.482564",\ + "0.051979, 0.304374, 0.633649, 1.248559, 2.482564",\ + "0.127230, 0.342977, 0.639913, 1.251125, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.066637, 0.172312, 0.283920, 0.488198, 0.896753",\ + "0.154052, 0.259631, 0.371201, 0.575503, 0.984106",\ + "0.234393, 0.339967, 0.451228, 0.655531, 1.064138",\ + "0.291040, 0.397516, 0.508771, 0.712776, 1.120786",\ + "0.584372, 0.700851, 0.812405, 1.015791, 1.422562"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.023343, 0.186306, 0.386954, 0.759444, 1.504424",\ + "0.023343, 0.186447, 0.387459, 0.759444, 1.504424",\ + "0.024480, 0.186447, 0.387459, 0.759444, 1.504424",\ + "0.026601, 0.186447, 0.387459, 0.759444, 1.504424",\ + "0.045445, 0.190459, 0.387459, 0.759444, 1.504704"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.046791, 0.200181, 0.375803, 0.698817, 1.344843",\ + "0.133030, 0.287356, 0.462909, 0.785532, 1.430777",\ + "0.215892, 0.375484, 0.550866, 0.873154, 1.517732",\ + "0.273461, 0.439881, 0.614982, 0.937068, 1.581241",\ + "0.571381, 0.789745, 0.965369, 1.285812, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.022232, 0.297820, 0.631558, 1.247336, 2.473548",\ + "0.026946, 0.298797, 0.633513, 1.247336, 2.473548",\ + "0.040098, 0.301070, 0.633549, 1.247411, 2.473548",\ + "0.051979, 0.304374, 0.633649, 1.248154, 2.473548",\ + "0.127230, 0.342977, 0.639913, 1.251125, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.066637, 0.172312, 0.283920, 0.488198, 0.896753",\ + "0.154052, 0.259631, 0.371201, 0.575503, 0.984106",\ + "0.234393, 0.339967, 0.451228, 0.655531, 1.064138",\ + "0.291040, 0.397516, 0.508771, 0.712776, 1.120786",\ + "0.584372, 0.700851, 0.812405, 1.015791, 1.422562"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001497, 0.074496, 0.161626, 0.321754, 0.642011"); + values ( "0.023343, 0.185511, 0.385448, 0.757215, 1.500747",\ + "0.023343, 0.185511, 0.385448, 0.757215, 1.500747",\ + "0.024480, 0.185511, 0.385448, 0.757215, 1.500747",\ + "0.026601, 0.186123, 0.385904, 0.758116, 1.502538",\ + "0.045445, 0.190459, 0.385975, 0.758885, 1.504704"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022232, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215122, 0.169193, 0.138993, 0.127649, 0.141334",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023343, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250044, 0.174723, 0.106564, 0.083596, 0.146510",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022232, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147049, -0.104632, -0.070145, -0.030722, 0.275326",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.023343, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163200, -0.097285, -0.039626, 0.002335, 0.222943",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[1]_hldr*/ + +} /* end of pin obs_ctrl_o[1] */ + +pin("obs_ctrl_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.644672 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.001493 ; + + /* Other user defined attributes. */ + original_pin : obs_ctrl_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.055703, 0.210083, 0.384209, 0.703083, 1.340832",\ + "0.142641, 0.298158, 0.472850, 0.791312, 1.428237",\ + "0.229315, 0.390451, 0.564575, 0.883476, 1.521279",\ + "0.289529, 0.457854, 0.631595, 0.950327, 1.587790",\ + "0.601982, 0.825701, 1.001139, 1.318705, 1.953837"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.024610, 0.296910, 0.628369, 1.238416, 2.458509",\ + "0.028411, 0.296910, 0.628369, 1.238416, 2.458509",\ + "0.041899, 0.299449, 0.628369, 1.238416, 2.458509",\ + "0.054012, 0.302907, 0.628369, 1.238416, 2.458509",\ + "0.127326, 0.341602, 0.634020, 1.242332, 2.458956"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.067218, 0.173389, 0.285054, 0.487703, 0.893002",\ + "0.152156, 0.258225, 0.370124, 0.573210, 0.979381",\ + "0.227822, 0.333668, 0.444933, 0.647806, 1.053553",\ + "0.281477, 0.388180, 0.499584, 0.702346, 1.107870",\ + "0.555899, 0.671761, 0.783535, 0.986072, 1.391148"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.022977, 0.185704, 0.382820, 0.754070, 1.496570",\ + "0.022977, 0.186687, 0.385282, 0.756178, 1.496570",\ + "0.023517, 0.186687, 0.385282, 0.756178, 1.496570",\ + "0.025088, 0.186687, 0.385282, 0.756178, 1.496570",\ + "0.040853, 0.190395, 0.385282, 0.756178, 1.496570"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.055703, 0.210083, 0.384209, 0.703083, 1.340832",\ + "0.142641, 0.298158, 0.472850, 0.791312, 1.428237",\ + "0.229315, 0.390451, 0.564575, 0.883476, 1.521279",\ + "0.289529, 0.457854, 0.631595, 0.950327, 1.587790",\ + "0.601982, 0.825701, 1.001139, 1.318705, 1.953837"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.024610, 0.296388, 0.626537, 1.236829, 2.455429",\ + "0.028411, 0.296388, 0.626537, 1.236829, 2.455429",\ + "0.041899, 0.299449, 0.628148, 1.237241, 2.455429",\ + "0.054012, 0.302907, 0.628330, 1.238054, 2.457501",\ + "0.127326, 0.341602, 0.634020, 1.242332, 2.458956"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.067218, 0.173389, 0.285054, 0.487703, 0.893002",\ + "0.152156, 0.258225, 0.370124, 0.573210, 0.979381",\ + "0.227822, 0.333668, 0.444933, 0.647806, 1.053553",\ + "0.281477, 0.388180, 0.499584, 0.702346, 1.107870",\ + "0.555899, 0.671761, 0.783535, 0.986072, 1.391148"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.001493, 0.074794, 0.162288, 0.323083, 0.644672"); + values ( "0.022977, 0.185508, 0.382818, 0.754052, 1.494916",\ + "0.022977, 0.185508, 0.382818, 0.754052, 1.494916",\ + "0.023517, 0.185508, 0.382818, 0.754052, 1.494916",\ + "0.025088, 0.186034, 0.383442, 0.754326, 1.494916",\ + "0.040853, 0.190395, 0.384031, 0.754326, 1.494916"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.205304, 0.155898, 0.121844, 0.108632, 0.118959",\ + "0.213701, 0.164296, 0.130242, 0.117030, 0.127356",\ + "0.286247, 0.236842, 0.202788, 0.189576, 0.199902",\ + "0.377880, 0.328444, 0.294355, 0.281122, 0.291373",\ + "0.826990, 0.777305, 0.742923, 0.729519, 0.739150"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022977, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.253248, 0.179609, 0.114078, 0.098860, 0.242765",\ + "0.260429, 0.186790, 0.121259, 0.106041, 0.249946",\ + "0.338311, 0.264672, 0.199141, 0.183923, 0.327828",\ + "0.439285, 0.365564, 0.300030, 0.284860, 0.429362",\ + "0.945572, 0.871138, 0.805582, 0.790828, 0.940493"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.131653, -0.089547, -0.055448, -0.032345, 0.077315",\ + "-0.140051, -0.097944, -0.063846, -0.040742, 0.068917",\ + "-0.212597, -0.170490, -0.136392, -0.113288, -0.003629",\ + "-0.304160, -0.262036, -0.227893, -0.204765, -0.095035",\ + "-0.752635, -0.710363, -0.675857, -0.652532, -0.542218"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.022977, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.160975, -0.096153, -0.041987, -0.003573, 0.191467",\ + "-0.168150, -0.103328, -0.049162, -0.010747, 0.184292",\ + "-0.246073, -0.181251, -0.127085, -0.088671, 0.106369",\ + "-0.346978, -0.282082, -0.227737, -0.189269, 0.005504",\ + "-0.852619, -0.787096, -0.731202, -0.692284, -0.499800"); + } + + } /* end of arc clk_ast_tlul_i_obs_ctrl_o[0]_hldr*/ + +} /* end of pin obs_ctrl_o[0] */ +} /* end of bus obs_ctrl_o */ +bus ( padmux2ast_i ) { + + bus_type : BUS9_type16 ; + direction : input ; + +pin("padmux2ast_i[8]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001547 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[8]; +} /* end of pin padmux2ast_i[8] */ + +pin("padmux2ast_i[7]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001037 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[7]; + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.599931, 0.560765, 0.510135, 0.511231, 0.524547",\ + "0.684459, 0.645293, 0.594663, 0.595759, 0.609075",\ + "0.775549, 0.736383, 0.685753, 0.686849, 0.700165",\ + "0.937661, 0.898495, 0.847865, 0.848961, 0.862277",\ + "1.209352, 1.170186, 1.119556, 1.120651, 1.133968"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.507406, 0.449725, 0.394624, 0.395719, 0.409035",\ + "0.595359, 0.537678, 0.482576, 0.483672, 0.496988",\ + "0.695327, 0.637646, 0.582544, 0.583640, 0.596956",\ + "0.879705, 0.822024, 0.766922, 0.768018, 0.781334",\ + "1.197915, 1.140234, 1.085132, 1.086228, 1.099544"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[7]_stupr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.288273, -0.255190, -0.196555, -0.182927, -0.017307",\ + "-0.372801, -0.339718, -0.281083, -0.267455, -0.101836",\ + "-0.463895, -0.430812, -0.372177, -0.358549, -0.192930",\ + "-0.625950, -0.592867, -0.534232, -0.520604, -0.354985",\ + "-0.897654, -0.864571, -0.805936, -0.792308, -0.626688"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-0.249551, -0.198552, -0.102091, -0.083944, 0.136600",\ + "-0.337500, -0.286501, -0.190040, -0.171892, 0.048652",\ + "-0.437474, -0.386475, -0.290014, -0.271866, -0.051323",\ + "-0.621823, -0.570824, -0.474363, -0.456216, -0.235672",\ + "-0.940049, -0.889050, -0.792589, -0.774441, -0.553897"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[7]_hldr*/ + +} /* end of pin padmux2ast_i[7] */ + +pin("padmux2ast_i[6]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001036 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[6]; +} /* end of pin padmux2ast_i[6] */ + +pin("padmux2ast_i[5]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001070 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[5]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590008.937500, 590008.875000, 590008.812500, 590008.812500, 590008.812500",\ + "590009.062500, 590009.000000, 590008.937500, 590008.937500, 590008.937500",\ + "590009.062500, 590009.000000, 590008.937500, 590008.937500, 590008.937500",\ + "590009.187500, 590009.125000, 590009.062500, 590009.062500, 590009.062500",\ + "590009.437500, 590009.375000, 590009.312500, 590009.312500, 590009.312500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590007.187500, 590007.125000, 590007.062500, 590007.062500, 590007.062500",\ + "590007.312500, 590007.250000, 590007.187500, 590007.187500, 590007.187500",\ + "590007.437500, 590007.375000, 590007.312500, 590007.312500, 590007.312500",\ + "590007.562500, 590007.500000, 590007.437500, 590007.437500, 590007.437500",\ + "590007.937500, 590007.875000, 590007.812500, 590007.812500, 590007.812500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590008.312500, -590008.250000, -590008.250000, -590008.125000, -590007.875000",\ + "-590008.312500, -590008.250000, -590008.250000, -590008.125000, -590007.875000",\ + "-590008.437500, -590008.375000, -590008.375000, -590008.250000, -590008.000000",\ + "-590008.562500, -590008.500000, -590008.500000, -590008.375000, -590008.125000",\ + "-590008.812500, -590008.750000, -590008.750000, -590008.625000, -590008.375000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590006.625000, -590006.562500, -590006.500000, -590006.375000, -590006.250000",\ + "-590006.750000, -590006.687500, -590006.625000, -590006.500000, -590006.375000",\ + "-590006.875000, -590006.812500, -590006.750000, -590006.625000, -590006.500000",\ + "-590007.000000, -590006.937500, -590006.875000, -590006.750000, -590006.625000",\ + "-590007.250000, -590007.187500, -590007.125000, -590007.000000, -590006.875000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_hldr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590008.812500, 590008.750000, 590008.750000, 590008.750000, 590008.750000",\ + "590008.937500, 590008.875000, 590008.875000, 590008.875000, 590008.875000",\ + "590008.937500, 590008.875000, 590008.875000, 590008.875000, 590008.875000",\ + "590009.062500, 590009.000000, 590009.000000, 590009.000000, 590009.000000",\ + "590009.312500, 590009.250000, 590009.250000, 590009.250000, 590009.250000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590007.312500, 590007.312500, 590007.250000, 590007.250000, 590007.312500",\ + "590007.437500, 590007.437500, 590007.375000, 590007.375000, 590007.437500",\ + "590007.562500, 590007.562500, 590007.500000, 590007.500000, 590007.562500",\ + "590007.687500, 590007.687500, 590007.625000, 590007.625000, 590007.687500",\ + "590008.062500, 590008.062500, 590008.000000, 590008.000000, 590008.062500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_recfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590007.250000, -590007.250000, -590007.187500, -590007.125000, -590007.000000",\ + "-590007.250000, -590007.250000, -590007.187500, -590007.125000, -590007.000000",\ + "-590007.375000, -590007.375000, -590007.312500, -590007.250000, -590007.125000",\ + "-590007.500000, -590007.500000, -590007.437500, -590007.375000, -590007.250000",\ + "-590007.750000, -590007.750000, -590007.687500, -590007.625000, -590007.500000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590007.125000, -590007.125000, -590007.062500, -590007.000000, -590006.875000",\ + "-590007.250000, -590007.250000, -590007.187500, -590007.125000, -590007.000000",\ + "-590007.375000, -590007.375000, -590007.312500, -590007.250000, -590007.125000",\ + "-590007.500000, -590007.500000, -590007.437500, -590007.375000, -590007.250000",\ + "-590007.750000, -590007.750000, -590007.687500, -590007.625000, -590007.500000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_remfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590008.437500, 590008.437500, 590008.437500, 590008.500000, 590008.812500",\ + "590008.562500, 590008.562500, 590008.562500, 590008.625000, 590008.937500",\ + "590008.562500, 590008.562500, 590008.562500, 590008.625000, 590008.937500",\ + "590008.687500, 590008.687500, 590008.687500, 590008.750000, 590009.062500",\ + "590008.937500, 590008.937500, 590008.937500, 590009.000000, 590009.312500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590006.687500, 590006.687500, 590006.687500, 590006.687500, 590006.687500",\ + "590006.812500, 590006.812500, 590006.812500, 590006.812500, 590006.812500",\ + "590006.937500, 590006.937500, 590006.937500, 590006.937500, 590006.937500",\ + "590007.062500, 590007.062500, 590007.062500, 590007.062500, 590007.062500",\ + "590007.437500, 590007.437500, 590007.437500, 590007.437500, 590007.437500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cgsr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590008.250000, 590008.250000, 590008.250000, 590008.250000, 590008.250000",\ + "590008.375000, 590008.375000, 590008.375000, 590008.375000, 590008.375000",\ + "590008.375000, 590008.375000, 590008.375000, 590008.375000, 590008.375000",\ + "590008.500000, 590008.500000, 590008.500000, 590008.500000, 590008.500000",\ + "590008.750000, 590008.750000, 590008.750000, 590008.750000, 590008.750000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "590006.562500, 590006.562500, 590006.562500, 590006.562500, 590006.562500",\ + "590006.687500, 590006.687500, 590006.687500, 590006.687500, 590006.687500",\ + "590006.812500, 590006.812500, 590006.812500, 590006.812500, 590006.812500",\ + "590006.937500, 590006.937500, 590006.937500, 590006.937500, 590006.937500",\ + "590007.312500, 590007.312500, 590007.312500, 590007.312500, 590007.312500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cgsf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590008.250000, -590008.250000, -590008.250000, -590008.187500, -590008.062500",\ + "-590008.250000, -590008.250000, -590008.250000, -590008.187500, -590008.062500",\ + "-590008.375000, -590008.375000, -590008.375000, -590008.312500, -590008.187500",\ + "-590008.500000, -590008.500000, -590008.500000, -590008.437500, -590008.312500",\ + "-590008.750000, -590008.750000, -590008.750000, -590008.687500, -590008.562500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590006.562500, -590006.562500, -590006.437500, -590006.312500, -590006.062500",\ + "-590006.687500, -590006.687500, -590006.562500, -590006.437500, -590006.187500",\ + "-590006.812500, -590006.812500, -590006.687500, -590006.562500, -590006.312500",\ + "-590006.937500, -590006.937500, -590006.812500, -590006.687500, -590006.437500",\ + "-590007.187500, -590007.187500, -590007.062500, -590006.937500, -590006.687500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cghr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590008.250000, -590008.250000, -590008.250000, -590008.250000, -590008.250000",\ + "-590008.250000, -590008.250000, -590008.250000, -590008.250000, -590008.250000",\ + "-590008.375000, -590008.375000, -590008.375000, -590008.375000, -590008.375000",\ + "-590008.500000, -590008.500000, -590008.500000, -590008.500000, -590008.500000",\ + "-590008.750000, -590008.750000, -590008.750000, -590008.750000, -590008.750000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-590006.562500, -590006.562500, -590006.562500, -590006.562500, -590006.562500",\ + "-590006.687500, -590006.687500, -590006.687500, -590006.687500, -590006.687500",\ + "-590006.812500, -590006.812500, -590006.812500, -590006.812500, -590006.812500",\ + "-590006.937500, -590006.937500, -590006.937500, -590006.937500, -590006.937500",\ + "-590007.187500, -590007.187500, -590007.187500, -590007.187500, -590007.187500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[5]_cghf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "590011.500000, 590010.062500, 590009.187500, 590008.812500, 590008.750000",\ + "590011.625000, 590010.187500, 590009.312500, 590008.937500, 590008.875000",\ + "590011.625000, 590010.187500, 590009.312500, 590008.937500, 590008.875000",\ + "590011.750000, 590010.312500, 590009.437500, 590009.062500, 590009.000000",\ + "590012.000000, 590010.562500, 590009.687500, 590009.312500, 590009.250000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[5]_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-590006.562500, -590006.437500, -590006.375000, -590006.375000, -590006.312500",\ + "-590006.562500, -590006.437500, -590006.375000, -590006.375000, -590006.312500",\ + "-590006.687500, -590006.562500, -590006.500000, -590006.500000, -590006.437500",\ + "-590006.812500, -590006.687500, -590006.625000, -590006.625000, -590006.562500",\ + "-590007.062500, -590006.937500, -590006.875000, -590006.875000, -590006.812500"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[5]_remrr*/ + +} /* end of pin padmux2ast_i[5] */ + +pin("padmux2ast_i[4]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001489 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[4]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970007.437500, 970007.375000, 970007.312500, 970007.312500, 970007.312500",\ + "970007.562500, 970007.500000, 970007.437500, 970007.437500, 970007.437500",\ + "970007.562500, 970007.500000, 970007.437500, 970007.437500, 970007.437500",\ + "970007.812500, 970007.750000, 970007.687500, 970007.687500, 970007.687500",\ + "970008.062500, 970008.000000, 970007.937500, 970007.937500, 970007.937500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970010.562500, 970010.500000, 970010.437500, 970010.437500, 970010.437500",\ + "970010.687500, 970010.625000, 970010.562500, 970010.562500, 970010.562500",\ + "970010.812500, 970010.750000, 970010.687500, 970010.687500, 970010.687500",\ + "970011.062500, 970011.000000, 970010.937500, 970010.937500, 970010.937500",\ + "970011.312500, 970011.250000, 970011.187500, 970011.187500, 970011.187500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "380000.312500, 380000.312500, 380000.312500, 380000.312500, 380000.312500",\ + "380000.406250, 380000.406250, 380000.406250, 380000.406250, 380000.406250",\ + "380000.500000, 380000.500000, 380000.500000, 380000.500000, 380000.500000",\ + "380000.656250, 380000.656250, 380000.656250, 380000.656250, 380000.656250",\ + "380000.906250, 380000.906250, 380000.906250, 380000.906250, 380000.906250"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "380001.843750, 380001.843750, 380001.843750, 380001.843750, 380001.843750",\ + "380001.937500, 380001.937500, 380001.937500, 380001.937500, 380001.937500",\ + "380002.062500, 380002.062500, 380002.062500, 380002.062500, 380002.062500",\ + "380002.250000, 380002.250000, 380002.250000, 380002.250000, 380002.250000",\ + "380002.562500, 380002.562500, 380002.562500, 380002.562500, 380002.562500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_stupf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.375000, -380000.312500, -380000.281250, -380000.187500, -379999.906250",\ + "-380000.468750, -380000.406250, -380000.375000, -380000.281250, -380000.000000",\ + "-380000.531250, -380000.468750, -380000.437500, -380000.343750, -380000.062500",\ + "-380000.687500, -380000.625000, -380000.593750, -380000.500000, -380000.218750",\ + "-380000.906250, -380000.843750, -380000.812500, -380000.718750, -380000.437500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.750000, -380001.687500, -380001.656250, -380001.562500, -380001.375000",\ + "-380001.843750, -380001.781250, -380001.750000, -380001.656250, -380001.468750",\ + "-380001.937500, -380001.875000, -380001.843750, -380001.750000, -380001.562500",\ + "-380002.125000, -380002.062500, -380002.031250, -380001.937500, -380001.750000",\ + "-380002.375000, -380002.312500, -380002.281250, -380002.187500, -380002.000000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_hldr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.281250, -380000.281250, -380000.281250, -380000.281250, -380000.281250",\ + "-380000.375000, -380000.375000, -380000.375000, -380000.375000, -380000.375000",\ + "-380000.437500, -380000.437500, -380000.437500, -380000.437500, -380000.437500",\ + "-380000.593750, -380000.593750, -380000.593750, -380000.593750, -380000.593750",\ + "-380000.812500, -380000.812500, -380000.812500, -380000.812500, -380000.812500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.750000, -380001.750000, -380001.750000, -380001.750000, -380001.750000",\ + "-380001.843750, -380001.843750, -380001.843750, -380001.843750, -380001.843750",\ + "-380001.937500, -380001.937500, -380001.937500, -380001.937500, -380001.937500",\ + "-380002.125000, -380002.125000, -380002.125000, -380002.125000, -380002.125000",\ + "-380002.375000, -380002.375000, -380002.375000, -380002.375000, -380002.375000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_hldf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970007.625000, 970007.562500, 970007.500000, 970007.500000, 970007.562500",\ + "970007.750000, 970007.687500, 970007.625000, 970007.625000, 970007.687500",\ + "970007.750000, 970007.687500, 970007.625000, 970007.625000, 970007.687500",\ + "970008.000000, 970007.937500, 970007.875000, 970007.875000, 970007.937500",\ + "970008.250000, 970008.187500, 970008.125000, 970008.125000, 970008.187500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970010.437500, 970010.375000, 970010.375000, 970010.375000, 970010.375000",\ + "970010.562500, 970010.500000, 970010.500000, 970010.500000, 970010.500000",\ + "970010.687500, 970010.625000, 970010.625000, 970010.625000, 970010.625000",\ + "970010.937500, 970010.875000, 970010.875000, 970010.875000, 970010.875000",\ + "970011.187500, 970011.125000, 970011.125000, 970011.125000, 970011.125000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "380000.500000, 380000.500000, 380000.500000, 380000.500000, 380000.500000",\ + "380000.593750, 380000.593750, 380000.593750, 380000.593750, 380000.593750",\ + "380000.687500, 380000.687500, 380000.687500, 380000.687500, 380000.687500",\ + "380000.843750, 380000.843750, 380000.843750, 380000.843750, 380000.843750",\ + "380001.093750, 380001.093750, 380001.093750, 380001.093750, 380001.093750"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recrf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_falling ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "380001.937500, 380001.937500, 380001.937500, 380001.937500, 380001.937500",\ + "380002.031250, 380002.031250, 380002.031250, 380002.031250, 380002.031250",\ + "380002.156250, 380002.156250, 380002.156250, 380002.156250, 380002.156250",\ + "380002.343750, 380002.343750, 380002.343750, 380002.343750, 380002.343750",\ + "380002.656250, 380002.656250, 380002.656250, 380002.656250, 380002.656250"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_recff*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.375000, -380000.343750, -380000.281250, -380000.250000, -380000.125000",\ + "-380000.468750, -380000.437500, -380000.375000, -380000.343750, -380000.218750",\ + "-380000.531250, -380000.500000, -380000.437500, -380000.406250, -380000.281250",\ + "-380000.687500, -380000.656250, -380000.593750, -380000.562500, -380000.437500",\ + "-380000.906250, -380000.875000, -380000.812500, -380000.781250, -380000.656250"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.812500, -380001.781250, -380001.718750, -380001.687500, -380001.593750",\ + "-380001.906250, -380001.875000, -380001.812500, -380001.781250, -380001.687500",\ + "-380002.000000, -380001.968750, -380001.906250, -380001.875000, -380001.781250",\ + "-380002.187500, -380002.156250, -380002.093750, -380002.062500, -380001.968750",\ + "-380002.437500, -380002.406250, -380002.343750, -380002.312500, -380002.218750"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.312500, -380000.312500, -380000.312500, -380000.312500, -380000.312500",\ + "-380000.406250, -380000.406250, -380000.406250, -380000.406250, -380000.406250",\ + "-380000.468750, -380000.468750, -380000.468750, -380000.468750, -380000.468750",\ + "-380000.625000, -380000.625000, -380000.625000, -380000.625000, -380000.625000",\ + "-380000.843750, -380000.843750, -380000.843750, -380000.843750, -380000.843750"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remrf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_falling ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.750000, -380001.750000, -380001.750000, -380001.750000, -380001.750000",\ + "-380001.843750, -380001.843750, -380001.843750, -380001.843750, -380001.843750",\ + "-380001.937500, -380001.937500, -380001.937500, -380001.937500, -380001.937500",\ + "-380002.125000, -380002.125000, -380002.125000, -380002.125000, -380002.125000",\ + "-380002.375000, -380002.375000, -380002.375000, -380002.375000, -380002.375000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_remff*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970006.937500, 970006.937500, 970006.937500, 970006.937500, 970006.937500",\ + "970007.062500, 970007.062500, 970007.062500, 970007.062500, 970007.062500",\ + "970007.062500, 970007.062500, 970007.062500, 970007.062500, 970007.062500",\ + "970007.312500, 970007.312500, 970007.312500, 970007.312500, 970007.312500",\ + "970007.562500, 970007.562500, 970007.562500, 970007.562500, 970007.562500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970010.062500, 970010.062500, 970010.062500, 970010.125000, 970010.437500",\ + "970010.187500, 970010.187500, 970010.187500, 970010.250000, 970010.562500",\ + "970010.312500, 970010.312500, 970010.312500, 970010.375000, 970010.687500",\ + "970010.562500, 970010.562500, 970010.562500, 970010.625000, 970010.937500",\ + "970010.812500, 970010.812500, 970010.812500, 970010.875000, 970011.187500"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cgsr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970006.812500, 970006.812500, 970006.812500, 970006.812500, 970006.812500",\ + "970006.937500, 970006.937500, 970006.937500, 970006.937500, 970006.937500",\ + "970006.937500, 970006.937500, 970006.937500, 970006.937500, 970006.937500",\ + "970007.187500, 970007.187500, 970007.187500, 970007.187500, 970007.187500",\ + "970007.437500, 970007.437500, 970007.437500, 970007.437500, 970007.437500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "970009.875000, 970009.875000, 970009.875000, 970009.875000, 970009.875000",\ + "970010.000000, 970010.000000, 970010.000000, 970010.000000, 970010.000000",\ + "970010.125000, 970010.125000, 970010.125000, 970010.125000, 970010.125000",\ + "970010.375000, 970010.375000, 970010.375000, 970010.375000, 970010.375000",\ + "970010.625000, 970010.625000, 970010.625000, 970010.625000, 970010.625000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cgsf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.281250, -380000.218750, -380000.187500, -380000.125000, -380000.000000",\ + "-380000.375000, -380000.312500, -380000.281250, -380000.218750, -380000.093750",\ + "-380000.437500, -380000.375000, -380000.343750, -380000.281250, -380000.156250",\ + "-380000.593750, -380000.531250, -380000.500000, -380000.437500, -380000.312500",\ + "-380000.812500, -380000.750000, -380000.718750, -380000.656250, -380000.531250"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.718750, -380001.625000, -380001.531250, -380001.406250, -380001.125000",\ + "-380001.812500, -380001.718750, -380001.625000, -380001.500000, -380001.218750",\ + "-380001.906250, -380001.812500, -380001.718750, -380001.593750, -380001.312500",\ + "-380002.093750, -380002.000000, -380001.906250, -380001.781250, -380001.500000",\ + "-380002.343750, -380002.250000, -380002.156250, -380002.031250, -380001.750000"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cghr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380000.312500, -380000.312500, -380000.312500, -380000.312500, -380000.312500",\ + "-380000.406250, -380000.406250, -380000.406250, -380000.406250, -380000.406250",\ + "-380000.468750, -380000.468750, -380000.468750, -380000.468750, -380000.468750",\ + "-380000.625000, -380000.625000, -380000.625000, -380000.625000, -380000.625000",\ + "-380000.843750, -380000.843750, -380000.843750, -380000.843750, -380000.843750"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.718750, -380001.718750, -380001.718750, -380001.718750, -380001.718750",\ + "-380001.812500, -380001.812500, -380001.812500, -380001.812500, -380001.812500",\ + "-380001.906250, -380001.906250, -380001.906250, -380001.906250, -380001.906250",\ + "-380002.093750, -380002.093750, -380002.093750, -380002.093750, -380002.093750",\ + "-380002.343750, -380002.343750, -380002.343750, -380002.343750, -380002.343750"); + } + + } /* end of arc clk_ast_ext_i_padmux2ast_i[4]_cghf*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380000.500000, 380000.468750, 380000.406250, 380000.406250, 380000.468750",\ + "380000.593750, 380000.562500, 380000.500000, 380000.500000, 380000.562500",\ + "380000.687500, 380000.656250, 380000.593750, 380000.593750, 380000.656250",\ + "380000.843750, 380000.812500, 380000.750000, 380000.750000, 380000.812500",\ + "380001.093750, 380001.062500, 380001.000000, 380001.000000, 380001.062500"); + } + + } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_recrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380001.968750, 380001.937500, 380001.875000, 380001.875000, 380001.937500",\ + "380002.062500, 380002.031250, 380001.968750, 380001.968750, 380002.031250",\ + "380002.187500, 380002.156250, 380002.093750, 380002.093750, 380002.156250",\ + "380002.375000, 380002.343750, 380002.281250, 380002.281250, 380002.343750",\ + "380002.687500, 380002.656250, 380002.593750, 380002.593750, 380002.656250"); + } + + } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_recfr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380000.343750, -380000.312500, -380000.250000, -380000.218750, -380000.093750",\ + "-380000.437500, -380000.406250, -380000.343750, -380000.312500, -380000.187500",\ + "-380000.500000, -380000.468750, -380000.406250, -380000.375000, -380000.250000",\ + "-380000.656250, -380000.625000, -380000.562500, -380000.531250, -380000.406250",\ + "-380000.875000, -380000.843750, -380000.781250, -380000.750000, -380000.625000"); + } + + } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_remrr*/ + + timing () { + related_pin : "clk_ast_rng_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380001.812500, -380001.781250, -380001.718750, -380001.687500, -380001.562500",\ + "-380001.906250, -380001.875000, -380001.812500, -380001.781250, -380001.656250",\ + "-380002.000000, -380001.968750, -380001.906250, -380001.875000, -380001.750000",\ + "-380002.187500, -380002.156250, -380002.093750, -380002.062500, -380001.937500",\ + "-380002.437500, -380002.406250, -380002.343750, -380002.312500, -380002.187500"); + } + + } /* end of arc clk_ast_rng_i_padmux2ast_i[4]_remfr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380000.843750, 380000.750000, 380000.687500, 380000.687500, 380000.656250",\ + "380000.937500, 380000.843750, 380000.781250, 380000.781250, 380000.750000",\ + "380001.031250, 380000.937500, 380000.875000, 380000.875000, 380000.843750",\ + "380001.187500, 380001.093750, 380001.031250, 380001.031250, 380001.000000",\ + "380001.437500, 380001.343750, 380001.281250, 380001.281250, 380001.250000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380002.312500, 380002.218750, 380002.250000, 380002.343750, 380002.750000",\ + "380002.406250, 380002.312500, 380002.343750, 380002.437500, 380002.843750",\ + "380002.531250, 380002.437500, 380002.468750, 380002.562500, 380002.968750",\ + "380002.718750, 380002.625000, 380002.656250, 380002.750000, 380003.156250",\ + "380003.031250, 380002.937500, 380002.968750, 380003.062500, 380003.468750"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-380000.312500, -380000.281250, -380000.250000, -380000.218750, -380000.093750",\ + "-380000.406250, -380000.375000, -380000.343750, -380000.312500, -380000.187500",\ + "-380000.468750, -380000.437500, -380000.406250, -380000.375000, -380000.250000",\ + "-380000.625000, -380000.593750, -380000.562500, -380000.531250, -380000.406250",\ + "-380000.843750, -380000.812500, -380000.781250, -380000.750000, -380000.625000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-380001.781250, -380001.718750, -380001.656250, -380001.593750, -380001.375000",\ + "-380001.875000, -380001.812500, -380001.750000, -380001.687500, -380001.468750",\ + "-380001.968750, -380001.906250, -380001.843750, -380001.781250, -380001.562500",\ + "-380002.156250, -380002.093750, -380002.031250, -380001.968750, -380001.750000",\ + "-380002.406250, -380002.343750, -380002.281250, -380002.218750, -380002.000000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_hldr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380011.406250, 380010.000000, 380009.125000, 380008.718750, 380008.656250",\ + "380011.500000, 380010.093750, 380009.218750, 380008.812500, 380008.750000",\ + "380011.593750, 380010.187500, 380009.312500, 380008.906250, 380008.843750",\ + "380011.750000, 380010.343750, 380009.468750, 380009.062500, 380009.000000",\ + "380012.000000, 380010.593750, 380009.718750, 380009.312500, 380009.250000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "970013.125000, 970011.687500, 970010.875000, 970010.437500, 970010.375000",\ + "970013.250000, 970011.812500, 970011.000000, 970010.562500, 970010.500000",\ + "970013.375000, 970011.937500, 970011.125000, 970010.687500, 970010.625000",\ + "970013.625000, 970012.187500, 970011.375000, 970010.937500, 970010.875000",\ + "970013.875000, 970012.437500, 970011.625000, 970011.187500, 970011.125000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_recfr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-380000.343750, -380000.312500, -380000.250000, -380000.187500, -379999.843750",\ + "-380000.437500, -380000.406250, -380000.343750, -380000.281250, -379999.937500",\ + "-380000.500000, -380000.468750, -380000.406250, -380000.343750, -380000.000000",\ + "-380000.656250, -380000.625000, -380000.562500, -380000.500000, -380000.156250",\ + "-380000.875000, -380000.843750, -380000.781250, -380000.718750, -380000.375000"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-380001.812500, -380001.781250, -380001.687500, -380001.625000, -380001.281250",\ + "-380001.906250, -380001.875000, -380001.781250, -380001.718750, -380001.375000",\ + "-380002.000000, -380001.968750, -380001.875000, -380001.812500, -380001.468750",\ + "-380002.187500, -380002.156250, -380002.062500, -380002.000000, -380001.656250",\ + "-380002.437500, -380002.406250, -380002.312500, -380002.250000, -380001.906250"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_remfr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380001.343750, 380001.343750, 380001.343750, 380001.343750, 380001.343750",\ + "380001.437500, 380001.437500, 380001.437500, 380001.437500, 380001.437500",\ + "380001.531250, 380001.531250, 380001.531250, 380001.531250, 380001.531250",\ + "380001.687500, 380001.687500, 380001.687500, 380001.687500, 380001.687500",\ + "380001.937500, 380001.937500, 380001.937500, 380001.937500, 380001.937500"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "380003.062500, 380003.062500, 380003.062500, 380003.062500, 380003.062500",\ + "380003.156250, 380003.156250, 380003.156250, 380003.156250, 380003.156250",\ + "380003.281250, 380003.281250, 380003.281250, 380003.281250, 380003.281250",\ + "380003.468750, 380003.468750, 380003.468750, 380003.468750, 380003.468750",\ + "380003.781250, 380003.781250, 380003.781250, 380003.781250, 380003.781250"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_cgsr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_falling ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380001.343750, -380001.343750, -380001.343750, -380001.343750, -380001.343750",\ + "-380001.437500, -380001.437500, -380001.437500, -380001.437500, -380001.437500",\ + "-380001.500000, -380001.500000, -380001.500000, -380001.500000, -380001.500000",\ + "-380001.656250, -380001.656250, -380001.656250, -380001.656250, -380001.656250",\ + "-380001.875000, -380001.875000, -380001.875000, -380001.875000, -380001.875000"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-380003.062500, -380003.062500, -380003.062500, -380003.062500, -380003.062500",\ + "-380003.156250, -380003.156250, -380003.156250, -380003.156250, -380003.156250",\ + "-380003.250000, -380003.250000, -380003.250000, -380003.250000, -380003.250000",\ + "-380003.437500, -380003.437500, -380003.437500, -380003.437500, -380003.437500",\ + "-380003.687500, -380003.687500, -380003.687500, -380003.687500, -380003.687500"); + } + + } /* end of arc clk_ast_tlul_i_padmux2ast_i[4]_cghf*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380002.218750, 380002.156250, 380002.125000, 380002.125000, 380002.125000",\ + "380002.312500, 380002.250000, 380002.218750, 380002.218750, 380002.218750",\ + "380002.406250, 380002.343750, 380002.312500, 380002.312500, 380002.312500",\ + "380002.562500, 380002.500000, 380002.468750, 380002.468750, 380002.468750",\ + "380002.812500, 380002.750000, 380002.718750, 380002.718750, 380002.718750"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380004.218750, 380004.156250, 380004.125000, 380004.125000, 380004.125000",\ + "380004.312500, 380004.250000, 380004.218750, 380004.218750, 380004.218750",\ + "380004.437500, 380004.375000, 380004.343750, 380004.343750, 380004.343750",\ + "380004.625000, 380004.562500, 380004.531250, 380004.531250, 380004.531250",\ + "380004.937500, 380004.875000, 380004.843750, 380004.843750, 380004.843750"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_stupr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380001.781250, -380001.718750, -380001.625000, -380001.593750, -380001.375000",\ + "-380001.875000, -380001.812500, -380001.718750, -380001.687500, -380001.468750",\ + "-380001.937500, -380001.875000, -380001.781250, -380001.750000, -380001.531250",\ + "-380002.093750, -380002.031250, -380001.937500, -380001.906250, -380001.687500",\ + "-380002.312500, -380002.250000, -380002.156250, -380002.125000, -380001.906250"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380003.906250, -380003.843750, -380003.750000, -380003.718750, -380003.500000",\ + "-380004.000000, -380003.937500, -380003.843750, -380003.812500, -380003.593750",\ + "-380004.093750, -380004.031250, -380003.937500, -380003.906250, -380003.687500",\ + "-380004.281250, -380004.218750, -380004.125000, -380004.093750, -380003.875000",\ + "-380004.531250, -380004.468750, -380004.375000, -380004.343750, -380004.125000"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_hldr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380000.593750, 380000.562500, 380000.500000, 380000.500000, 380000.562500",\ + "380000.687500, 380000.656250, 380000.593750, 380000.593750, 380000.656250",\ + "380000.781250, 380000.750000, 380000.687500, 380000.687500, 380000.750000",\ + "380000.937500, 380000.906250, 380000.843750, 380000.843750, 380000.906250",\ + "380001.187500, 380001.156250, 380001.093750, 380001.093750, 380001.156250"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_recrr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "380002.031250, 380002.000000, 380001.937500, 380001.937500, 380002.000000",\ + "380002.125000, 380002.093750, 380002.031250, 380002.031250, 380002.093750",\ + "380002.250000, 380002.218750, 380002.156250, 380002.156250, 380002.218750",\ + "380002.437500, 380002.406250, 380002.343750, 380002.343750, 380002.406250",\ + "380002.750000, 380002.718750, 380002.656250, 380002.656250, 380002.718750"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_recfr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380000.437500, -380000.406250, -380000.343750, -380000.312500, -380000.187500",\ + "-380000.531250, -380000.500000, -380000.437500, -380000.406250, -380000.281250",\ + "-380000.593750, -380000.562500, -380000.500000, -380000.468750, -380000.343750",\ + "-380000.750000, -380000.718750, -380000.656250, -380000.625000, -380000.500000",\ + "-380000.968750, -380000.937500, -380000.875000, -380000.843750, -380000.718750"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_remrr*/ + + timing () { + related_pin : "clk_ast_usb_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-380001.875000, -380001.843750, -380001.781250, -380001.750000, -380001.625000",\ + "-380001.968750, -380001.937500, -380001.875000, -380001.843750, -380001.718750",\ + "-380002.062500, -380002.031250, -380001.968750, -380001.937500, -380001.812500",\ + "-380002.250000, -380002.218750, -380002.156250, -380002.125000, -380002.000000",\ + "-380002.500000, -380002.468750, -380002.406250, -380002.375000, -380002.250000"); + } + + } /* end of arc clk_ast_usb_i_padmux2ast_i[4]_remfr*/ + +} /* end of pin padmux2ast_i[4] */ + +pin("padmux2ast_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001527 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[3]; +} /* end of pin padmux2ast_i[3] */ + +pin("padmux2ast_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001451 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[2]; +} /* end of pin padmux2ast_i[2] */ + +pin("padmux2ast_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.002579 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[1]; +} /* end of pin padmux2ast_i[1] */ + +pin("padmux2ast_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001032 ; + + /* Other user defined attributes. */ + original_pin : padmux2ast_i[0]; +} /* end of pin padmux2ast_i[0] */ +} /* end of bus padmux2ast_i */ +bus ( ast2padmux_o ) { + + bus_type : BUS9_type16 ; + direction : output ; + +pin("ast2padmux_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.159377 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380004.343750, 380004.375000, 380004.437500, 380004.718750, 380005.625000",\ + "380004.437500, 380004.468750, 380004.531250, 380004.812500, 380005.718750",\ + "380004.531250, 380004.562500, 380004.625000, 380004.906250, 380005.812500",\ + "380004.593750, 380004.625000, 380004.687500, 380004.968750, 380005.875000",\ + "380004.937500, 380004.968750, 380005.031250, 380005.312500, 380006.218750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.437500, 380002.468750, 380002.531250, 380002.687500, 380003.281250",\ + "380002.531250, 380002.562500, 380002.625000, 380002.781250, 380003.375000",\ + "380002.593750, 380002.625000, 380002.687500, 380002.843750, 380003.437500",\ + "380002.656250, 380002.687500, 380002.750000, 380002.906250, 380003.500000",\ + "380003.000000, 380003.031250, 380003.093750, 380003.250000, 380003.843750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027375, 0.057503, 0.133586, 0.436974, 1.549209"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.198420, 0.230953, 0.301455, 0.556384, 1.484645",\ + "0.286701, 0.319234, 0.389735, 0.644664, 1.572926",\ + "0.375268, 0.407801, 0.478303, 0.733232, 1.661493",\ + "0.437972, 0.470506, 0.541007, 0.795935, 1.724196",\ + "0.757115, 0.789659, 0.860255, 1.115081, 2.043332"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\ + "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\ + "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\ + "0.020935, 0.066607, 0.198712, 0.685847, 2.460401",\ + "0.020935, 0.066607, 0.198712, 0.685847, 2.460401"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.211851, 0.238498, 0.286799, 0.453464, 1.060488",\ + "0.299253, 0.325901, 0.374202, 0.540867, 1.147891",\ + "0.380126, 0.406773, 0.455075, 0.621740, 1.228763",\ + "0.437748, 0.464395, 0.512697, 0.679362, 1.286385",\ + "0.739921, 0.766569, 0.814870, 0.981535, 1.588558"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\ + "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\ + "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\ + "0.020406, 0.050335, 0.128964, 0.434734, 1.543997",\ + "0.020406, 0.050336, 0.128964, 0.434733, 1.544003"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.408924, 0.441470, 0.512070, 0.766936, 1.695386",\ + "0.493120, 0.525666, 0.596266, 0.851132, 1.779583",\ + "0.583441, 0.615988, 0.686587, 0.941453, 1.869904",\ + "0.653401, 0.685947, 0.756547, 1.011413, 1.939865",\ + "1.044013, 1.076560, 1.147159, 1.402024, 2.330486"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020948, 0.066625, 0.198722, 0.685958, 2.464075",\ + "0.020948, 0.066625, 0.198722, 0.685958, 2.464075",\ + "0.020948, 0.066625, 0.198722, 0.685958, 2.464075",\ + "0.020948, 0.066625, 0.198723, 0.685958, 2.464075",\ + "0.020946, 0.066625, 0.198725, 0.685957, 2.464076"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.438271, 0.469168, 0.519837, 0.687755, 1.292925",\ + "0.526383, 0.557280, 0.607949, 0.775866, 1.381036",\ + "0.628083, 0.658980, 0.709649, 0.877567, 1.482737",\ + "0.819336, 0.850238, 0.900907, 1.068829, 1.674009",\ + "1.156747, 1.187659, 1.238328, 1.406259, 2.011461"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027368, 0.057498, 0.133582, 0.436963, 1.549160",\ + "0.027368, 0.057498, 0.133582, 0.436963, 1.549160",\ + "0.027368, 0.057498, 0.133582, 0.436963, 1.549160",\ + "0.027371, 0.057501, 0.133584, 0.436969, 1.549186",\ + "0.027379, 0.057507, 0.133588, 0.436980, 1.549240"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.398110, 0.430656, 0.501253, 0.756075, 1.684372",\ + "0.482288, 0.514834, 0.585431, 0.840253, 1.768550",\ + "0.572606, 0.605152, 0.675749, 0.930571, 1.858868",\ + "0.642450, 0.674996, 0.745593, 1.000414, 1.928712",\ + "1.032124, 1.064670, 1.135267, 1.390089, 2.318387"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.463750",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.463750"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.427883, 0.458770, 0.509441, 0.677352, 1.282498",\ + "0.516006, 0.546892, 0.597564, 0.765475, 1.370620",\ + "0.617659, 0.648546, 0.699217, 0.867128, 1.472274",\ + "0.808079, 0.838969, 0.889641, 1.057554, 1.662708",\ + "1.144522, 1.175420, 1.226092, 1.394011, 1.999181"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027342, 0.057489, 0.133570, 0.436937, 1.549078",\ + "0.027342, 0.057489, 0.133570, 0.436937, 1.549078",\ + "0.027342, 0.057489, 0.133570, 0.436937, 1.549078",\ + "0.027344, 0.057490, 0.133572, 0.436941, 1.549096",\ + "0.027347, 0.057494, 0.133575, 0.436950, 1.549136"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[8]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380000.718750, 380000.750000, 380000.812500, 380001.093750, 380002.000000",\ + "380000.812500, 380000.843750, 380000.906250, 380001.187500, 380002.093750",\ + "380000.906250, 380000.937500, 380001.000000, 380001.281250, 380002.187500",\ + "380001.062500, 380001.093750, 380001.156250, 380001.437500, 380002.343750",\ + "380001.312500, 380001.343750, 380001.406250, 380001.687500, 380002.593750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.125000, 380002.156250, 380002.218750, 380002.375000, 380002.968750",\ + "380002.218750, 380002.250000, 380002.312500, 380002.468750, 380003.062500",\ + "380002.343750, 380002.375000, 380002.437500, 380002.593750, 380003.187500",\ + "380002.531250, 380002.562500, 380002.625000, 380002.781250, 380003.375000",\ + "380002.843750, 380002.875000, 380002.937500, 380003.093750, 380003.687500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380000.687500, 380000.718750, 380000.781250, 380001.062500, 380001.968750",\ + "380000.781250, 380000.812500, 380000.875000, 380001.156250, 380002.062500",\ + "380000.843750, 380000.875000, 380000.937500, 380001.218750, 380002.125000",\ + "380001.000000, 380001.031250, 380001.093750, 380001.375000, 380002.281250",\ + "380001.218750, 380001.250000, 380001.312500, 380001.593750, 380002.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.125000, 380002.156250, 380002.187500, 380002.375000, 380002.968750",\ + "380002.218750, 380002.250000, 380002.281250, 380002.468750, 380003.062500",\ + "380002.312500, 380002.343750, 380002.375000, 380002.562500, 380003.156250",\ + "380002.500000, 380002.531250, 380002.562500, 380002.750000, 380003.343750",\ + "380002.750000, 380002.781250, 380002.812500, 380003.000000, 380003.593750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.312500, 380002.343750, 380002.406250, 380002.562500, 380003.156250",\ + "380002.406250, 380002.437500, 380002.500000, 380002.656250, 380003.250000",\ + "380002.500000, 380002.531250, 380002.593750, 380002.750000, 380003.343750",\ + "380002.656250, 380002.687500, 380002.750000, 380002.906250, 380003.500000",\ + "380002.906250, 380002.937500, 380003.000000, 380003.156250, 380003.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163",\ + "0.027368, 0.057498, 0.133582, 0.436964, 1.549163"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380004.250000, 380004.281250, 380004.343750, 380004.625000, 380005.531250",\ + "380004.343750, 380004.375000, 380004.437500, 380004.718750, 380005.625000",\ + "380004.468750, 380004.500000, 380004.562500, 380004.843750, 380005.750000",\ + "380004.656250, 380004.687500, 380004.750000, 380005.031250, 380005.937500",\ + "380004.968750, 380005.000000, 380005.062500, 380005.343750, 380006.250000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075",\ + "0.021241, 0.066861, 0.199049, 0.687205, 2.464075"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380000.687500, 380000.718750, 380000.750000, 380000.937500, 380001.531250",\ + "380000.781250, 380000.812500, 380000.843750, 380001.031250, 380001.625000",\ + "380000.843750, 380000.875000, 380000.906250, 380001.093750, 380001.687500",\ + "380001.000000, 380001.031250, 380001.062500, 380001.250000, 380001.843750",\ + "380001.218750, 380001.250000, 380001.281250, 380001.468750, 380002.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080",\ + "0.020492, 0.050440, 0.128935, 0.434235, 1.546080"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "380002.062500, 380002.093750, 380002.156250, 380002.437500, 380003.343750",\ + "380002.156250, 380002.187500, 380002.250000, 380002.531250, 380003.437500",\ + "380002.250000, 380002.281250, 380002.343750, 380002.625000, 380003.531250",\ + "380002.437500, 380002.468750, 380002.531250, 380002.812500, 380003.718750",\ + "380002.687500, 380002.718750, 380002.781250, 380003.062500, 380003.968750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.003266, 0.011949, 0.043724, 0.159377"); + values ( "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022",\ + "0.020932, 0.066607, 0.198719, 0.685843, 2.460022"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[8]_inv_min*/ + +} /* end of pin ast2padmux_o[8] */ + +pin("ast2padmux_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[7]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[7]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[7]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.495682, 0.527114, 0.579822, 0.722175, 1.100772",\ + "0.520857, 0.552289, 0.604997, 0.747350, 1.125947",\ + "0.590847, 0.622279, 0.674987, 0.817340, 1.195937",\ + "0.713975, 0.745406, 0.798114, 0.940467, 1.319064",\ + "1.300896, 1.332327, 1.385036, 1.527389, 1.905985"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.673247, 0.740150, 0.856588, 1.176256, 2.031462",\ + "0.693898, 0.760801, 0.877239, 1.196908, 2.052114",\ + "0.752520, 0.819423, 0.935861, 1.255530, 2.110735",\ + "0.862063, 0.928966, 1.045403, 1.365072, 2.220278",\ + "1.621675, 1.688580, 1.805019, 2.124689, 2.979892"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073039, 0.188935, 0.391846, 0.949113, 2.441342"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.342569, 0.373981, 0.426627, 0.569042, 0.947686",\ + "0.366027, 0.397440, 0.450085, 0.592500, 0.971144",\ + "0.437124, 0.468537, 0.521182, 0.663597, 1.042241",\ + "0.562321, 0.593734, 0.646379, 0.788794, 1.167438",\ + "1.165783, 1.197195, 1.249841, 1.392256, 1.770899"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.657383, 0.724274, 0.840701, 1.160369, 2.015589",\ + "0.673535, 0.740426, 0.856853, 1.176521, 2.031741",\ + "0.736621, 0.803512, 0.919939, 1.239607, 2.094827",\ + "0.845856, 0.912747, 1.029174, 1.348842, 2.204062",\ + "1.602693, 1.669584, 1.786011, 2.105679, 2.960899"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.690094, 0.756997, 0.873435, 1.193104, 2.048309",\ + "0.708444, 0.775347, 0.891784, 1.211453, 2.066659",\ + "0.778290, 0.845193, 0.961630, 1.281299, 2.136505",\ + "0.871001, 0.937904, 1.054342, 1.374010, 2.229216",\ + "1.316481, 1.383384, 1.499822, 1.819491, 2.674696"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452197, 0.483629, 0.536337, 0.678690, 1.057287",\ + "0.469625, 0.501056, 0.553764, 0.696117, 1.074714",\ + "0.546991, 0.578423, 0.631131, 0.773484, 1.152081",\ + "0.655363, 0.686795, 0.739503, 0.881856, 1.260453",\ + "1.172095, 1.203526, 1.256235, 1.398588, 1.777184"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.682055, 0.748946, 0.865373, 1.185041, 2.040261",\ + "0.698671, 0.765561, 0.881989, 1.201657, 2.056877",\ + "0.770251, 0.837141, 0.953569, 1.273237, 2.128457",\ + "0.862962, 0.929853, 1.046280, 1.365948, 2.221168",\ + "1.308443, 1.375334, 1.491761, 1.811429, 2.666649"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.393282, 0.424695, 0.477340, 0.619755, 0.998399",\ + "0.406628, 0.438041, 0.490686, 0.633102, 1.011745",\ + "0.488076, 0.519489, 0.572134, 0.714549, 1.093193",\ + "0.596558, 0.627970, 0.680616, 0.823031, 1.201674",\ + "1.114468, 1.145880, 1.198526, 1.340941, 1.719585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.501059, 0.532491, 0.585199, 0.727552, 1.106149",\ + "0.519617, 0.551049, 0.603757, 0.746110, 1.124707",\ + "0.596986, 0.628417, 0.681126, 0.823478, 1.202075",\ + "0.726207, 0.757638, 0.810347, 0.952700, 1.331296",\ + "1.349983, 1.381414, 1.434123, 1.576475, 1.955072"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.672551, 0.739454, 0.855892, 1.175561, 2.030766",\ + "0.690451, 0.757354, 0.873791, 1.193460, 2.048666",\ + "0.751450, 0.818353, 0.934791, 1.254459, 2.109665",\ + "0.853899, 0.920802, 1.037239, 1.356908, 2.212114",\ + "1.570440, 1.637343, 1.753780, 2.073449, 2.928655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.403368, 0.434780, 0.487426, 0.629841, 1.008485",\ + "0.420114, 0.451526, 0.504172, 0.646587, 1.025230",\ + "0.499560, 0.530972, 0.583618, 0.726033, 1.104676",\ + "0.629829, 0.661242, 0.713887, 0.856302, 1.234946",\ + "1.257639, 1.289051, 1.341697, 1.484112, 1.862756"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.659894, 0.726785, 0.843212, 1.162880, 2.018100",\ + "0.674063, 0.740954, 0.857382, 1.177050, 2.032269",\ + "0.738792, 0.805683, 0.922111, 1.241779, 2.096998",\ + "0.841228, 0.908118, 1.024546, 1.344214, 2.199434",\ + "1.556835, 1.623726, 1.740153, 2.059821, 2.915041"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.701899, 0.768802, 0.885240, 1.204909, 2.060114",\ + "0.720452, 0.787355, 0.903793, 1.223462, 2.078667",\ + "0.793150, 0.860053, 0.976490, 1.296159, 2.151365",\ + "0.888367, 0.955270, 1.071708, 1.391377, 2.246583",\ + "1.341174, 1.408077, 1.524515, 1.844184, 2.699389"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.458590, 0.490021, 0.542729, 0.685082, 1.063679",\ + "0.476132, 0.507563, 0.560272, 0.702625, 1.081221",\ + "0.553461, 0.584892, 0.637601, 0.779954, 1.158551",\ + "0.662931, 0.694363, 0.747071, 0.889424, 1.268021",\ + "1.187512, 1.218943, 1.271652, 1.414004, 1.792601"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.693852, 0.760742, 0.877170, 1.196838, 2.052058",\ + "0.710673, 0.777564, 0.893991, 1.213659, 2.068879",\ + "0.785102, 0.851993, 0.968420, 1.288088, 2.143308",\ + "0.880320, 0.947210, 1.063638, 1.383306, 2.238526",\ + "1.333127, 1.400018, 1.516445, 1.836113, 2.691333"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.399735, 0.431148, 0.483793, 0.626208, 1.004852",\ + "0.413192, 0.444604, 0.497250, 0.639665, 1.018308",\ + "0.494607, 0.526019, 0.578665, 0.721080, 1.099723",\ + "0.604175, 0.635587, 0.688233, 0.830648, 1.209292",\ + "1.129895, 1.161308, 1.213953, 1.356368, 1.735012"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.496000, 0.527432, 0.580140, 0.722493, 1.101090",\ + "0.514620, 0.546052, 0.598760, 0.741113, 1.119710",\ + "0.591411, 0.622842, 0.675550, 0.817903, 1.196500",\ + "0.717296, 0.748727, 0.801436, 0.943789, 1.322386",\ + "1.315738, 1.347169, 1.399878, 1.542231, 1.920827"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.666141, 0.733044, 0.849482, 1.169151, 2.024356",\ + "0.678814, 0.745717, 0.862155, 1.181824, 2.037030",\ + "0.733584, 0.800487, 0.916924, 1.236593, 2.091799",\ + "0.837061, 0.903964, 1.020401, 1.340070, 2.195276",\ + "1.538248, 1.605151, 1.721588, 2.041257, 2.896463"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.398263, 0.429676, 0.482321, 0.624736, 1.003380",\ + "0.415077, 0.446490, 0.499135, 0.641550, 1.020194",\ + "0.493940, 0.525353, 0.577998, 0.720414, 1.099057",\ + "0.620916, 0.652328, 0.704974, 0.847389, 1.226032",\ + "1.223414, 1.254826, 1.307472, 1.449887, 1.828531"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692",\ + "0.039011, 0.090734, 0.180376, 0.429203, 1.091692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.653476, 0.720367, 0.836794, 1.156462, 2.011682",\ + "0.663102, 0.729992, 0.846420, 1.166088, 2.021308",\ + "0.720914, 0.787805, 0.904232, 1.223900, 2.079120",\ + "0.824356, 0.891247, 1.007674, 1.327342, 2.182562",\ + "1.523659, 1.590550, 1.706977, 2.026645, 2.881865"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330",\ + "0.073030, 0.188914, 0.391814, 0.949025, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[7]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[7]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[7]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "otp_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[7]_ast2padmux_o[7]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[7]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[7]_ast2padmux_o[7]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[7]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[7]_inv_min*/ + +} /* end of pin ast2padmux_o[7] */ + +pin("ast2padmux_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[6]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[6]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[6]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.401444, 0.432876, 0.485584, 0.627937, 1.006534",\ + "0.426514, 0.457945, 0.510653, 0.653006, 1.031603",\ + "0.495788, 0.527220, 0.579928, 0.722281, 1.100878",\ + "0.620121, 0.651552, 0.704261, 0.846613, 1.225210",\ + "1.225494, 1.256926, 1.309634, 1.451987, 1.830584"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.665410, 0.732314, 0.848751, 1.168420, 2.023626",\ + "0.685984, 0.752887, 0.869324, 1.188993, 2.044199",\ + "0.744648, 0.811551, 0.927989, 1.247657, 2.102863",\ + "0.853883, 0.920786, 1.037224, 1.356892, 2.212098",\ + "1.621675, 1.688580, 1.805019, 2.124689, 2.979892"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073039, 0.188935, 0.391846, 0.949113, 2.441342"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.345553, 0.376966, 0.429613, 0.572027, 0.950669",\ + "0.369011, 0.400424, 0.453071, 0.595485, 0.974127",\ + "0.440108, 0.471521, 0.524168, 0.666582, 1.045224",\ + "0.565305, 0.596718, 0.649365, 0.791779, 1.170421",\ + "1.171631, 1.203044, 1.255693, 1.398105, 1.776746"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039018, 0.090728, 0.180391, 0.429207, 1.091650"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.663782, 0.730673, 0.847101, 1.166770, 2.021989",\ + "0.679934, 0.746826, 0.863254, 1.182922, 2.038141",\ + "0.743020, 0.809911, 0.926339, 1.246007, 2.101227",\ + "0.852255, 0.919146, 1.035574, 1.355242, 2.210462",\ + "1.620317, 1.687211, 1.803640, 2.123309, 2.978526"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073030, 0.188915, 0.391817, 0.949051, 2.441332"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[6]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.690094, 0.756997, 0.873435, 1.193104, 2.048309",\ + "0.708444, 0.775347, 0.891784, 1.211453, 2.066659",\ + "0.778290, 0.845193, 0.961630, 1.281299, 2.136505",\ + "0.871001, 0.937904, 1.054342, 1.374010, 2.229216",\ + "1.316481, 1.383384, 1.499822, 1.819491, 2.674696"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452134, 0.483566, 0.536274, 0.678627, 1.057224",\ + "0.469561, 0.500993, 0.553701, 0.696054, 1.074651",\ + "0.546928, 0.578360, 0.631068, 0.773421, 1.152018",\ + "0.655300, 0.686732, 0.739440, 0.881793, 1.260390",\ + "1.172032, 1.203463, 1.256172, 1.398524, 1.777121"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.688464, 0.755356, 0.871784, 1.191452, 2.046671",\ + "0.705080, 0.771971, 0.888399, 1.208067, 2.063287",\ + "0.776660, 0.843551, 0.959979, 1.279647, 2.134867",\ + "0.869371, 0.936263, 1.052691, 1.372359, 2.227578",\ + "1.314852, 1.381744, 1.498172, 1.817840, 2.673059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.396265, 0.427678, 0.480325, 0.622739, 1.001381",\ + "0.409612, 0.441025, 0.493672, 0.636085, 1.014728",\ + "0.491059, 0.522472, 0.575119, 0.717533, 1.096175",\ + "0.599541, 0.630954, 0.683601, 0.826015, 1.204657",\ + "1.117451, 1.148864, 1.201511, 1.343925, 1.722567"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.701899, 0.768802, 0.885240, 1.204909, 2.060114",\ + "0.720452, 0.787355, 0.903793, 1.223462, 2.078667",\ + "0.793150, 0.860053, 0.976490, 1.296159, 2.151365",\ + "0.888367, 0.955270, 1.071708, 1.391377, 2.246583",\ + "1.341174, 1.408077, 1.524515, 1.844184, 2.699389"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.458526, 0.489958, 0.542666, 0.685019, 1.063616",\ + "0.476069, 0.507500, 0.560208, 0.702561, 1.081158",\ + "0.553398, 0.584829, 0.637537, 0.779890, 1.158487",\ + "0.662868, 0.694299, 0.747008, 0.889361, 1.267957",\ + "1.187448, 1.218880, 1.271588, 1.413941, 1.792538"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700268, 0.767160, 0.883588, 1.203256, 2.058475",\ + "0.717089, 0.783981, 0.900409, 1.220077, 2.075296",\ + "0.791519, 0.858410, 0.974838, 1.294506, 2.149726",\ + "0.886736, 0.953628, 1.070056, 1.389724, 2.244943",\ + "1.339543, 1.406435, 1.522863, 1.842531, 2.697751"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.402716, 0.434129, 0.486776, 0.629190, 1.007832",\ + "0.416173, 0.447586, 0.500233, 0.642646, 1.021289",\ + "0.497588, 0.529001, 0.581648, 0.724061, 1.102704",\ + "0.607156, 0.638569, 0.691216, 0.833630, 1.212272",\ + "1.132876, 1.164289, 1.216936, 1.359350, 1.737992"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "otm_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[6]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[6]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "otp_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[6]_ast2padmux_o[6]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[6]_ast2padmux_o[6]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[6]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[6]_inv_min*/ + +} /* end of pin ast2padmux_o[6] */ + +pin("ast2padmux_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[5]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[5]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[5]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.401444, 0.432876, 0.485584, 0.627937, 1.006534",\ + "0.426514, 0.457945, 0.510653, 0.653006, 1.031603",\ + "0.495788, 0.527220, 0.579928, 0.722281, 1.100878",\ + "0.620121, 0.651552, 0.704261, 0.846613, 1.225210",\ + "1.225494, 1.256926, 1.309634, 1.451987, 1.830584"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.665410, 0.732314, 0.848751, 1.168420, 2.023626",\ + "0.685984, 0.752887, 0.869324, 1.188993, 2.044199",\ + "0.744648, 0.811551, 0.927989, 1.247657, 2.102863",\ + "0.853883, 0.920786, 1.037224, 1.356892, 2.212098",\ + "1.621675, 1.688580, 1.805019, 2.124689, 2.979892"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073039, 0.188935, 0.391846, 0.949113, 2.441342"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.345553, 0.376966, 0.429613, 0.572027, 0.950669",\ + "0.369011, 0.400424, 0.453071, 0.595485, 0.974127",\ + "0.440108, 0.471521, 0.524168, 0.666582, 1.045224",\ + "0.565305, 0.596718, 0.649365, 0.791779, 1.170421",\ + "1.171631, 1.203044, 1.255693, 1.398105, 1.776746"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039018, 0.090728, 0.180391, 0.429207, 1.091650"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.663782, 0.730673, 0.847101, 1.166770, 2.021989",\ + "0.679934, 0.746826, 0.863254, 1.182922, 2.038141",\ + "0.743020, 0.809911, 0.926339, 1.246007, 2.101227",\ + "0.852255, 0.919146, 1.035574, 1.355242, 2.210462",\ + "1.620317, 1.687211, 1.803640, 2.123309, 2.978526"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073030, 0.188915, 0.391817, 0.949051, 2.441332"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[5]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.690094, 0.756997, 0.873435, 1.193104, 2.048309",\ + "0.708444, 0.775347, 0.891784, 1.211453, 2.066659",\ + "0.778290, 0.845193, 0.961630, 1.281299, 2.136505",\ + "0.871001, 0.937904, 1.054342, 1.374010, 2.229216",\ + "1.316481, 1.383384, 1.499822, 1.819491, 2.674696"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452134, 0.483566, 0.536274, 0.678627, 1.057224",\ + "0.469561, 0.500993, 0.553701, 0.696054, 1.074651",\ + "0.546928, 0.578360, 0.631068, 0.773421, 1.152018",\ + "0.655300, 0.686732, 0.739440, 0.881793, 1.260390",\ + "1.172032, 1.203463, 1.256172, 1.398524, 1.777121"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.688464, 0.755356, 0.871784, 1.191452, 2.046671",\ + "0.705080, 0.771971, 0.888399, 1.208067, 2.063287",\ + "0.776660, 0.843551, 0.959979, 1.279647, 2.134867",\ + "0.869371, 0.936263, 1.052691, 1.372359, 2.227578",\ + "1.314852, 1.381744, 1.498172, 1.817840, 2.673059"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.396265, 0.427678, 0.480325, 0.622739, 1.001381",\ + "0.409612, 0.441025, 0.493672, 0.636085, 1.014728",\ + "0.491059, 0.522472, 0.575119, 0.717533, 1.096175",\ + "0.599541, 0.630954, 0.683601, 0.826015, 1.204657",\ + "1.117451, 1.148864, 1.201511, 1.343925, 1.722567"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.701899, 0.768802, 0.885240, 1.204909, 2.060114",\ + "0.720452, 0.787355, 0.903793, 1.223462, 2.078667",\ + "0.793150, 0.860053, 0.976490, 1.296159, 2.151365",\ + "0.888367, 0.955270, 1.071708, 1.391377, 2.246583",\ + "1.341174, 1.408077, 1.524515, 1.844184, 2.699389"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340",\ + "0.073037, 0.188931, 0.391841, 0.949101, 2.441340"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.458526, 0.489958, 0.542666, 0.685019, 1.063616",\ + "0.476069, 0.507500, 0.560208, 0.702561, 1.081158",\ + "0.553398, 0.584829, 0.637537, 0.779890, 1.158487",\ + "0.662868, 0.694299, 0.747008, 0.889361, 1.267957",\ + "1.187448, 1.218880, 1.271588, 1.413941, 1.792538"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700268, 0.767160, 0.883588, 1.203256, 2.058475",\ + "0.717089, 0.783981, 0.900409, 1.220077, 2.075296",\ + "0.791519, 0.858410, 0.974838, 1.294506, 2.149726",\ + "0.886736, 0.953628, 1.070056, 1.389724, 2.244943",\ + "1.339543, 1.406435, 1.522863, 1.842531, 2.697751"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330",\ + "0.073029, 0.188911, 0.391812, 0.949040, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.402716, 0.434129, 0.486776, 0.629190, 1.007832",\ + "0.416173, 0.447586, 0.500233, 0.642646, 1.021289",\ + "0.497588, 0.529001, 0.581648, 0.724061, 1.102704",\ + "0.607156, 0.638569, 0.691216, 0.833630, 1.212272",\ + "1.132876, 1.164289, 1.216936, 1.359350, 1.737992"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671",\ + "0.039014, 0.090731, 0.180384, 0.429205, 1.091671"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "otm_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[5]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[5]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "otp_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[5]_ast2padmux_o[5]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[5]_ast2padmux_o[5]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[5]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[5]_inv_min*/ + +} /* end of pin ast2padmux_o[5] */ + +pin("ast2padmux_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[4]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.256137, 0.526101, 0.791807, 1.233240, 2.116106",\ + "0.323038, 0.593004, 0.858715, 1.300159, 2.183047",\ + "0.439474, 0.709441, 0.975156, 1.416609, 2.299516",\ + "0.759143, 1.029110, 1.294825, 1.736279, 2.619187",\ + "1.614351, 1.884316, 2.150025, 2.591466, 3.474348",\ + "0.314712, 0.584612, 0.850579, 1.290946, 2.172213",\ + "0.381613, 0.651515, 0.917487, 1.357865, 2.239154",\ + "0.498049, 0.767952, 1.033928, 1.474316, 2.355623",\ + "0.817718, 1.087621, 1.353598, 1.793986, 2.675294",\ + "1.672926, 1.942827, 2.208797, 2.649173, 3.530455",\ + "0.459188, 0.730385, 0.994470, 1.434701, 2.315946",\ + "0.526089, 0.797288, 1.061378, 1.501621, 2.382887",\ + "0.642525, 0.913725, 1.177819, 1.618071, 2.499355",\ + "0.962194, 1.233394, 1.497489, 1.937741, 2.819027",\ + "1.817402, 2.088600, 2.352689, 2.792928, 3.674187",\ + "0.495112, 0.768133, 1.031389, 1.471493, 2.352504",\ + "0.562013, 0.835036, 1.098297, 1.538412, 2.419445",\ + "0.678449, 0.951473, 1.214738, 1.654862, 2.535913",\ + "0.998118, 1.271142, 1.534407, 1.974532, 2.855585",\ + "1.853326, 2.126348, 2.389607, 2.829719, 3.710746",\ + "0.823805, 1.131731, 1.382980, 1.820732, 2.697960",\ + "0.890706, 1.198635, 1.449888, 1.887651, 2.764901",\ + "1.007142, 1.315072, 1.566330, 2.004102, 2.881370",\ + "1.326811, 1.634741, 1.885999, 2.323771, 3.201041",\ + "2.182019, 2.489947, 2.741199, 3.178958, 4.056201"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\ + "0.949092, 0.949099, 0.949128, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\ + "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\ + "0.949092, 0.949099, 0.949128, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\ + "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\ + "0.949092, 0.949100, 0.949128, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\ + "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188931, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391840, 0.391853, 0.391881, 0.391936",\ + "0.949092, 0.949100, 0.949128, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374",\ + "0.073036, 0.073037, 0.073041, 0.073049, 0.073065",\ + "0.188928, 0.188932, 0.188940, 0.188959, 0.188997",\ + "0.391836, 0.391842, 0.391854, 0.391881, 0.391936",\ + "0.949092, 0.949103, 0.949129, 0.949187, 0.949305",\ + "2.441339, 2.441340, 2.441345, 2.441355, 2.441374"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.300809, 0.483950, 0.676379, 0.983182, 1.575800",\ + "0.332240, 0.515381, 0.707810, 1.014614, 1.607232",\ + "0.384949, 0.568090, 0.760519, 1.067323, 1.659944",\ + "0.527301, 0.710443, 0.902872, 1.209675, 1.802294",\ + "0.905898, 1.089039, 1.281469, 1.588271, 2.180888",\ + "0.360720, 0.543848, 0.736331, 1.042962, 1.635417",\ + "0.392152, 0.575280, 0.767762, 1.074394, 1.666849",\ + "0.444860, 0.627988, 0.820471, 1.127103, 1.719561",\ + "0.587213, 0.770341, 0.962824, 1.269455, 1.861911",\ + "0.965810, 1.148938, 1.341421, 1.648051, 2.240505",\ + "0.493463, 0.676099, 0.868214, 1.174820, 1.767224",\ + "0.524895, 0.707531, 0.899645, 1.206252, 1.798657",\ + "0.577603, 0.760239, 0.952354, 1.258961, 1.851368",\ + "0.719956, 0.902592, 1.094707, 1.401313, 1.993718",\ + "1.098553, 1.281189, 1.473303, 1.779909, 2.372313",\ + "0.526601, 0.709226, 0.901339, 1.207772, 1.799833",\ + "0.558032, 0.740658, 0.932770, 1.239204, 1.831265",\ + "0.610741, 0.793366, 0.985478, 1.291914, 1.883977",\ + "0.753093, 0.935719, 1.127831, 1.434265, 2.026326",\ + "1.131690, 1.314316, 1.506428, 1.812862, 2.404921",\ + "0.827685, 1.014449, 1.204974, 1.510788, 2.101678",\ + "0.859116, 1.045881, 1.236405, 1.542220, 2.133111",\ + "0.911824, 1.098589, 1.289114, 1.594929, 2.185822",\ + "1.054177, 1.240942, 1.431466, 1.737281, 2.328172",\ + "1.432774, 1.619539, 1.810063, 2.115877, 2.706767"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[3]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.252605, 0.520760, 0.784538, 1.222585, 2.097608",\ + "0.319496, 0.587651, 0.851435, 1.289491, 2.164534",\ + "0.435923, 0.704079, 0.967867, 1.405931, 2.280990",\ + "0.755591, 1.023747, 1.287535, 1.725600, 2.600661",\ + "1.610811, 1.878966, 2.142749, 2.580802, 3.455839",\ + "0.311166, 0.579267, 0.843303, 1.280291, 2.153714",\ + "0.378057, 0.646158, 0.910200, 1.347198, 2.220641",\ + "0.494484, 0.762586, 1.026632, 1.463638, 2.337097",\ + "0.814152, 1.082254, 1.346300, 1.783307, 2.656768",\ + "1.669372, 1.937473, 2.201514, 2.638509, 3.511946",\ + "0.455502, 0.725014, 0.987191, 1.424095, 2.297447",\ + "0.522393, 0.791906, 1.054087, 1.491001, 2.364373",\ + "0.638820, 0.908334, 1.170519, 1.607441, 2.480830",\ + "0.958488, 1.228002, 1.490188, 1.927111, 2.800500",\ + "1.813708, 2.083220, 2.345402, 2.782313, 3.655679",\ + "0.491381, 0.762750, 1.024109, 1.460966, 2.334005",\ + "0.558271, 0.829641, 1.091006, 1.527872, 2.400932",\ + "0.674699, 0.946069, 1.207438, 1.644312, 2.517388",\ + "0.994367, 1.265738, 1.527106, 1.963982, 2.837059",\ + "1.849586, 2.120956, 2.382320, 2.819183, 3.692237",\ + "0.819578, 1.126098, 1.375669, 1.810266, 2.679461",\ + "0.886469, 1.192990, 1.442565, 1.877173, 2.746387",\ + "1.002896, 1.309418, 1.558997, 1.993613, 2.862844",\ + "1.322564, 1.629086, 1.878666, 2.313282, 3.182515",\ + "2.177784, 2.484305, 2.733880, 3.168484, 4.037693"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441331, 2.441334, 2.441343, 2.441361"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.262934, 0.448489, 0.641595, 0.948297, 1.539521",\ + "0.294346, 0.479902, 0.673008, 0.979711, 1.570936",\ + "0.346992, 0.532548, 0.725656, 1.032361, 1.623593",\ + "0.489407, 0.674962, 0.868069, 1.174772, 1.765997",\ + "0.868050, 1.053605, 1.246711, 1.553412, 2.144632",\ + "0.322845, 0.508317, 0.701440, 1.008066, 1.599138",\ + "0.354258, 0.539729, 0.732853, 1.039480, 1.630553",\ + "0.406904, 0.592376, 0.785500, 1.092130, 1.683210",\ + "0.549319, 0.734790, 0.927914, 1.234540, 1.825614",\ + "0.927962, 1.113433, 1.306556, 1.613180, 2.204249",\ + "0.455621, 0.640568, 0.833323, 1.139923, 1.730945",\ + "0.487034, 0.671981, 0.864736, 1.171337, 1.762361",\ + "0.539679, 0.724627, 0.917383, 1.223988, 1.815017",\ + "0.682094, 0.867041, 1.059797, 1.366398, 1.957422",\ + "1.060737, 1.245684, 1.438439, 1.745038, 2.336057",\ + "0.488779, 0.673866, 0.866553, 1.173003, 1.763806",\ + "0.520192, 0.705279, 0.897966, 1.204417, 1.795222",\ + "0.572837, 0.757925, 0.950613, 1.257067, 1.847878",\ + "0.715252, 0.900339, 1.093027, 1.399478, 1.990283",\ + "1.093896, 1.278982, 1.471669, 1.778118, 2.368918",\ + "0.790171, 0.979313, 1.170216, 1.476207, 2.066113",\ + "0.821584, 1.010726, 1.201629, 1.507621, 2.097529",\ + "0.874230, 1.063372, 1.254276, 1.560271, 2.150186",\ + "1.016645, 1.205787, 1.396689, 1.702681, 2.292590",\ + "1.395288, 1.584430, 1.775331, 2.081321, 2.671225"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180432",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180432",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180432",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180433",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091627, 1.091540",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039035",\ + "0.090733, 0.090732, 0.090730, 0.090724, 0.090712",\ + "0.180378, 0.180379, 0.180385, 0.180400, 0.180433",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091687, 1.091683, 1.091668, 1.091627, 1.091540"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970002.000000, 970002.062500, 970002.187500, 970002.500000, 970003.375000",\ + "970002.125000, 970002.187500, 970002.312500, 970002.625000, 970003.500000",\ + "970002.250000, 970002.312500, 970002.437500, 970002.750000, 970003.625000",\ + "970002.250000, 970002.312500, 970002.437500, 970002.750000, 970003.625000",\ + "970002.625000, 970002.687500, 970002.812500, 970003.125000, 970004.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970001.187500, 970001.187500, 970001.250000, 970001.437500, 970001.812500",\ + "970001.312500, 970001.312500, 970001.375000, 970001.562500, 970001.937500",\ + "970001.312500, 970001.312500, 970001.375000, 970001.562500, 970001.937500",\ + "970001.437500, 970001.437500, 970001.500000, 970001.687500, 970002.062500",\ + "970001.687500, 970001.687500, 970001.750000, 970001.937500, 970002.312500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231764, 0.298665, 0.415101, 0.734770, 1.589978",\ + "0.323073, 0.389976, 0.506413, 0.826082, 1.681288",\ + "0.433906, 0.500813, 0.617254, 0.936923, 1.792124",\ + "0.514021, 0.580932, 0.697376, 1.017045, 1.872241",\ + "0.917338, 0.984292, 1.100771, 1.420444, 2.275589"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073036, 0.188928, 0.391836, 0.949092, 2.441339",\ + "0.073037, 0.188930, 0.391839, 0.949098, 2.441340",\ + "0.073040, 0.188938, 0.391851, 0.949124, 2.441344",\ + "0.073043, 0.188945, 0.391861, 0.949145, 2.441347",\ + "0.073075, 0.189019, 0.391969, 0.949375, 2.441386"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.336061, 0.367493, 0.420201, 0.562554, 0.941151",\ + "0.422827, 0.454258, 0.506967, 0.649320, 1.027916",\ + "0.529568, 0.561000, 0.613708, 0.756061, 1.134658",\ + "0.742022, 0.773454, 0.826162, 0.968515, 1.347112",\ + "1.127927, 1.159358, 1.212067, 1.354419, 1.733016"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.221966, 0.288856, 0.405284, 0.724952, 1.580171",\ + "0.311631, 0.378522, 0.494949, 0.814617, 1.669837",\ + "0.414337, 0.481231, 0.597661, 0.917329, 1.772546",\ + "0.488653, 0.555550, 0.671983, 0.991651, 1.846864",\ + "0.868804, 0.935731, 1.052188, 1.371858, 2.227036"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188915, 0.391815, 0.949015, 2.441330",\ + "0.073032, 0.188915, 0.391815, 0.949022, 2.441330",\ + "0.073032, 0.188916, 0.391818, 0.949053, 2.441332",\ + "0.073033, 0.188921, 0.391826, 0.949069, 2.441335",\ + "0.073055, 0.188972, 0.391900, 0.949227, 2.441361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.247879, 0.279292, 0.331938, 0.474353, 0.852996",\ + "0.337796, 0.369209, 0.421855, 0.564270, 0.942913",\ + "0.451084, 0.482497, 0.535144, 0.677558, 1.056200",\ + "0.662499, 0.693912, 0.746561, 0.888973, 1.267614",\ + "1.032523, 1.063938, 1.116591, 1.258999, 1.637636"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180379, 0.429204, 1.091684",\ + "0.039012, 0.090733, 0.180379, 0.429204, 1.091684",\ + "0.039014, 0.090731, 0.180383, 0.429205, 1.091673",\ + "0.039019, 0.090727, 0.180394, 0.429207, 1.091643",\ + "0.039029, 0.090717, 0.180418, 0.429213, 1.091579"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "fla_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[4]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[4]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\ + "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\ + "0.521995, 0.588899, 0.705338, 1.025007, 1.880211",\ + "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\ + "1.134534, 1.201443, 1.317885, 1.637554, 2.492753"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\ + "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\ + "0.579334, 0.610765, 0.663474, 0.805826, 1.184423",\ + "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\ + "1.246693, 1.278125, 1.330833, 1.473186, 1.851783"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\ + "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\ + "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\ + "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\ + "1.077990, 1.144880, 1.261307, 1.580975, 2.436195"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.392866, 0.424278, 0.476924, 0.619339, 0.997982",\ + "0.410271, 0.441684, 0.494330, 0.636744, 1.015388",\ + "0.482841, 0.514253, 0.566899, 0.709314, 1.087957",\ + "0.595475, 0.626888, 0.679534, 0.821949, 1.200592",\ + "1.122503, 1.153916, 1.206562, 1.348976, 1.727620"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\ + "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\ + "0.531700, 0.563132, 0.615840, 0.758193, 1.136790",\ + "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\ + "1.286840, 1.318272, 1.370980, 1.513333, 1.891930"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\ + "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\ + "0.754790, 0.821694, 0.938133, 1.257802, 2.113006",\ + "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\ + "1.641748, 1.708657, 1.825099, 2.144769, 2.999968"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.284420, 0.315833, 0.368479, 0.510893, 0.889537",\ + "0.308019, 0.339432, 0.392078, 0.534493, 0.913136",\ + "0.380089, 0.411502, 0.464148, 0.606562, 0.985206",\ + "0.506286, 0.537698, 0.590344, 0.732759, 1.111402",\ + "1.081944, 1.113356, 1.166002, 1.308417, 1.687060"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.601029, 0.667919, 0.784346, 1.104014, 1.959234",\ + "0.617835, 0.684726, 0.801153, 1.120821, 1.976041",\ + "0.680343, 0.747234, 0.863661, 1.183329, 2.038548",\ + "0.789694, 0.856584, 0.973011, 1.292679, 2.147899",\ + "1.539211, 1.606101, 1.722528, 2.042196, 2.897416"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\ + "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\ + "0.789289, 0.856194, 0.972632, 1.292301, 2.147506",\ + "0.881295, 0.948199, 1.064638, 1.384307, 2.239511",\ + "1.366874, 1.433786, 1.550230, 1.869900, 2.725095"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\ + "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\ + "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\ + "0.691218, 0.722650, 0.775358, 0.917711, 1.296308",\ + "1.240839, 1.272271, 1.324979, 1.467332, 1.845928"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\ + "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\ + "0.727479, 0.794369, 0.910796, 1.230464, 2.085684",\ + "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\ + "1.269718, 1.336608, 1.453035, 1.772703, 2.627923"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.340324, 0.371736, 0.424382, 0.566797, 0.945440",\ + "0.353670, 0.385083, 0.437728, 0.580143, 0.958786",\ + "0.435082, 0.466495, 0.519140, 0.661555, 1.040198",\ + "0.544387, 0.575800, 0.628446, 0.770861, 1.149504",\ + "1.068007, 1.099420, 1.152066, 1.294481, 1.673124"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\ + "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\ + "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\ + "0.714879, 0.746311, 0.799019, 0.941372, 1.319969",\ + "1.235698, 1.267130, 1.319839, 1.462191, 1.840788"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\ + "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\ + "0.718674, 0.785579, 0.902017, 1.221686, 2.076890",\ + "0.820628, 0.887532, 1.003971, 1.323640, 2.178844",\ + "1.548479, 1.615391, 1.731835, 2.051504, 2.906700"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.305082, 0.336495, 0.389141, 0.531556, 0.910199",\ + "0.321682, 0.353095, 0.405741, 0.548156, 0.926799",\ + "0.400692, 0.432104, 0.484750, 0.627165, 1.005808",\ + "0.527571, 0.558983, 0.611629, 0.754044, 1.132687",\ + "1.082115, 1.113528, 1.166173, 1.308588, 1.687232"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\ + "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\ + "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\ + "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\ + "1.120855, 1.187745, 1.304172, 1.623840, 2.479060"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\ + "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\ + "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\ + "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\ + "1.355292, 1.422199, 1.538640, 1.858309, 2.713511"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073040, 0.188938, 0.391851, 0.949122, 2.441344"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\ + "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\ + "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\ + "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\ + "1.224584, 1.256016, 1.308724, 1.451077, 1.829674"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\ + "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\ + "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\ + "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\ + "1.307789, 1.374679, 1.491106, 1.810774, 2.665994"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.361796, 0.393209, 0.445854, 0.588269, 0.966913",\ + "0.375252, 0.406665, 0.459311, 0.601726, 0.980369",\ + "0.456673, 0.488086, 0.540731, 0.683146, 1.061790",\ + "0.566647, 0.598060, 0.650706, 0.793121, 1.171764",\ + "1.092083, 1.123496, 1.176142, 1.318556, 1.697200"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\ + "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\ + "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\ + "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\ + "1.187533, 1.218965, 1.271673, 1.414026, 1.792623"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.604133, 0.671037, 0.787476, 1.107145, 1.962349",\ + "0.616822, 0.683727, 0.800165, 1.119834, 1.975038",\ + "0.671505, 0.738410, 0.854848, 1.174517, 2.029721",\ + "0.774589, 0.841493, 0.957932, 1.277601, 2.132805",\ + "1.473004, 1.539911, 1.656352, 1.976021, 2.831222"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073040, 0.188938, 0.391851, 0.949122, 2.441344"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.284809, 0.316222, 0.368868, 0.511283, 0.889926",\ + "0.301623, 0.333036, 0.385681, 0.528096, 0.906739",\ + "0.380088, 0.411501, 0.464146, 0.606561, 0.985205",\ + "0.509697, 0.541110, 0.593756, 0.736170, 1.114814",\ + "1.092277, 1.123690, 1.176336, 1.318751, 1.697394"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091686"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\ + "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\ + "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\ + "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\ + "1.119877, 1.186768, 1.303195, 1.622863, 2.478083"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[4]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[4]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "otp_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[4]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[4]_ast2padmux_o[4]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970001.062500, 970001.062500, 970001.125000, 970001.312500, 970001.687500",\ + "970001.187500, 970001.187500, 970001.250000, 970001.437500, 970001.812500",\ + "970001.187500, 970001.187500, 970001.250000, 970001.437500, 970001.812500",\ + "970001.437500, 970001.437500, 970001.500000, 970001.687500, 970002.062500",\ + "970001.687500, 970001.687500, 970001.750000, 970001.937500, 970002.312500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970001.875000, 970001.937500, 970002.062500, 970002.375000, 970003.250000",\ + "970002.000000, 970002.062500, 970002.187500, 970002.500000, 970003.375000",\ + "970002.125000, 970002.187500, 970002.312500, 970002.625000, 970003.500000",\ + "970002.375000, 970002.437500, 970002.562500, 970002.875000, 970003.750000",\ + "970002.625000, 970002.687500, 970002.812500, 970003.125000, 970004.000000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[4]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[4]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590000.250000, 590000.312500, 590000.437500, 590000.750000, 590001.625000",\ + "590000.375000, 590000.437500, 590000.562500, 590000.875000, 590001.750000",\ + "590000.375000, 590000.437500, 590000.562500, 590000.875000, 590001.750000",\ + "590000.500000, 590000.562500, 590000.687500, 590001.000000, 590001.875000",\ + "590000.750000, 590000.812500, 590000.937500, 590001.250000, 590002.125000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590000.812500, 590000.812500, 590000.875000, 590001.062500, 590001.437500",\ + "590000.937500, 590000.937500, 590001.000000, 590001.187500, 590001.562500",\ + "590001.062500, 590001.062500, 590001.125000, 590001.312500, 590001.687500",\ + "590001.187500, 590001.187500, 590001.250000, 590001.437500, 590001.812500",\ + "590001.562500, 590001.562500, 590001.625000, 590001.812500, 590002.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497"); + } + + } /* end of arc padmux2ast_i[5]_ast2padmux_o[4]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590000.187500, 590000.250000, 590000.375000, 590000.687500, 590001.562500",\ + "590000.187500, 590000.250000, 590000.375000, 590000.687500, 590001.562500",\ + "590000.312500, 590000.375000, 590000.500000, 590000.812500, 590001.687500",\ + "590000.437500, 590000.500000, 590000.625000, 590000.937500, 590001.812500",\ + "590000.687500, 590000.750000, 590000.875000, 590001.187500, 590002.062500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590000.812500, 590000.812500, 590000.875000, 590001.000000, 590001.437500",\ + "590000.937500, 590000.937500, 590001.000000, 590001.125000, 590001.562500",\ + "590001.062500, 590001.062500, 590001.125000, 590001.250000, 590001.687500",\ + "590001.187500, 590001.187500, 590001.250000, 590001.375000, 590001.812500",\ + "590001.437500, 590001.437500, 590001.500000, 590001.625000, 590002.062500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\ + "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\ + "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\ + "0.039013, 0.090351, 0.180124, 0.429131, 1.091682",\ + "0.039013, 0.090351, 0.180124, 0.429131, 1.091682"); + } + + } /* end of arc padmux2ast_i[5]_ast2padmux_o[4]_una_min*/ + +} /* end of pin ast2padmux_o[4] */ + +pin("ast2padmux_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[3]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.257031, 0.528778, 0.797030, 1.242767, 2.134242",\ + "0.323932, 0.595681, 0.863940, 1.309691, 2.201193",\ + "0.440368, 0.712118, 0.980382, 1.426145, 2.317669",\ + "0.760037, 1.031787, 1.300052, 1.745815, 2.637342",\ + "1.615245, 1.886993, 2.155250, 2.600997, 3.492491",\ + "0.315617, 0.587294, 0.855812, 1.300474, 2.190349",\ + "0.382518, 0.654197, 0.922722, 1.367397, 2.257300",\ + "0.498954, 0.770634, 1.039164, 1.483851, 2.373776",\ + "0.818623, 1.090303, 1.358834, 1.803522, 2.693449",\ + "1.673831, 1.945509, 2.214032, 2.658703, 3.548597",\ + "0.460207, 0.733101, 0.999707, 1.444229, 2.334082",\ + "0.527108, 0.800004, 1.066617, 1.511152, 2.401032",\ + "0.643544, 0.916442, 1.183060, 1.627606, 2.517509",\ + "0.963213, 1.236110, 1.502729, 1.947277, 2.837182",\ + "1.818421, 2.091316, 2.357927, 2.802459, 3.692330",\ + "0.496168, 0.770865, 1.036627, 1.481020, 2.370640",\ + "0.563069, 0.837768, 1.103536, 1.547944, 2.437591",\ + "0.679505, 0.954206, 1.219979, 1.664398, 2.554067",\ + "0.999174, 1.273875, 1.539648, 1.984068, 2.873740",\ + "1.854382, 2.129080, 2.394846, 2.839250, 3.728889",\ + "0.825262, 1.134787, 1.388262, 1.830277, 2.716096",\ + "0.892164, 1.201690, 1.455172, 1.897201, 2.783047",\ + "1.008600, 1.318128, 1.571615, 2.013655, 2.899523",\ + "1.328269, 1.637797, 1.891284, 2.333325, 3.219196",\ + "2.183476, 2.493002, 2.746482, 3.188507, 4.074345"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073038, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188932, 0.188943, 0.188966, 0.189013",\ + "0.391836, 0.391843, 0.391858, 0.391892, 0.391961",\ + "0.949092, 0.949105, 0.949137, 0.949210, 0.949357",\ + "2.441339, 2.441341, 2.441346, 2.441358, 2.441383"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.308725, 0.491796, 0.685627, 0.996163, 1.596700",\ + "0.340157, 0.523228, 0.717058, 1.027595, 1.628132",\ + "0.392865, 0.575936, 0.769767, 1.080304, 1.680844",\ + "0.535218, 0.718289, 0.912119, 1.222656, 1.823194",\ + "0.913815, 1.096886, 1.290716, 1.601252, 2.201788",\ + "0.368637, 0.551695, 0.745581, 1.055944, 1.656317",\ + "0.400068, 0.583126, 0.777012, 1.087376, 1.687749",\ + "0.452777, 0.635835, 0.829721, 1.140085, 1.740461",\ + "0.595130, 0.778187, 0.972073, 1.282437, 1.882811",\ + "0.973727, 1.156784, 1.350670, 1.661033, 2.261405",\ + "0.501379, 0.683946, 0.877464, 1.187801, 1.788124",\ + "0.532811, 0.715378, 0.908895, 1.219233, 1.819557",\ + "0.585519, 0.768086, 0.961603, 1.271942, 1.872268",\ + "0.727872, 0.910439, 1.103956, 1.414294, 2.014618",\ + "1.106469, 1.289036, 1.482553, 1.792891, 2.393212",\ + "0.534516, 0.717073, 0.910588, 1.220754, 1.820733",\ + "0.565947, 0.748505, 0.942020, 1.252186, 1.852165",\ + "0.618656, 0.801213, 0.994728, 1.304895, 1.904876",\ + "0.761009, 0.943566, 1.137081, 1.447247, 2.047226",\ + "1.139605, 1.322163, 1.515678, 1.825843, 2.425821",\ + "0.835592, 1.022294, 1.214223, 1.523770, 2.122581",\ + "0.867023, 1.053726, 1.245655, 1.555202, 2.154014",\ + "0.919731, 1.106434, 1.298363, 1.607911, 2.206725",\ + "1.062084, 1.248787, 1.440716, 1.750263, 2.349075",\ + "1.440681, 1.627384, 1.819313, 2.128859, 2.727669"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[2]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.252558, 0.520745, 0.784515, 1.222569, 2.097608",\ + "0.319449, 0.587637, 0.851411, 1.289475, 2.164534",\ + "0.435876, 0.704065, 0.967843, 1.405915, 2.280990",\ + "0.755544, 1.023733, 1.287511, 1.725584, 2.600661",\ + "1.610764, 1.878952, 2.142725, 2.580786, 3.455839",\ + "0.311120, 0.579252, 0.843280, 1.280275, 2.153714",\ + "0.378011, 0.646143, 0.910176, 1.347182, 2.220640",\ + "0.494438, 0.762572, 1.026608, 1.463622, 2.337097",\ + "0.814106, 1.082240, 1.346276, 1.783291, 2.656767",\ + "1.669326, 1.937458, 2.201490, 2.638493, 3.511946",\ + "0.455460, 0.724999, 0.987167, 1.424079, 2.297447",\ + "0.522351, 0.791891, 1.054064, 1.490985, 2.364373",\ + "0.638778, 0.908319, 1.170496, 1.607426, 2.480830",\ + "0.958446, 1.227987, 1.490164, 1.927095, 2.800500",\ + "1.813666, 2.083206, 2.345378, 2.782297, 3.655679",\ + "0.491341, 0.762735, 1.024086, 1.460950, 2.334005",\ + "0.558231, 0.829626, 1.090982, 1.527856, 2.400931",\ + "0.674659, 0.946054, 1.207414, 1.644296, 2.517388",\ + "0.994327, 1.265722, 1.527082, 1.963966, 2.837059",\ + "1.849546, 2.120941, 2.382296, 2.819168, 3.692237",\ + "0.819555, 1.126080, 1.375645, 1.810251, 2.679461",\ + "0.886446, 1.192972, 1.442542, 1.877157, 2.746387",\ + "1.002873, 1.309400, 1.558974, 1.993597, 2.862844",\ + "1.322541, 1.629068, 1.878642, 2.313266, 3.182515",\ + "2.177761, 2.484287, 2.733856, 3.168468, 4.037693"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441331, 2.441334, 2.441343, 2.441361"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.262934, 0.448489, 0.641595, 0.948064, 1.538713",\ + "0.294346, 0.479902, 0.673008, 0.979478, 1.570129",\ + "0.346992, 0.532548, 0.725656, 1.032128, 1.622785",\ + "0.489407, 0.674962, 0.868069, 1.174539, 1.765190",\ + "0.868050, 1.053605, 1.246711, 1.553179, 2.143825",\ + "0.322845, 0.508317, 0.701440, 1.007833, 1.598330",\ + "0.354258, 0.539729, 0.732853, 1.039247, 1.629746",\ + "0.406904, 0.592376, 0.785500, 1.091897, 1.682402",\ + "0.549319, 0.734790, 0.927914, 1.234307, 1.824806",\ + "0.927962, 1.113433, 1.306556, 1.612947, 2.203442",\ + "0.455621, 0.640568, 0.833323, 1.139690, 1.730137",\ + "0.487034, 0.671981, 0.864736, 1.171104, 1.761553",\ + "0.539679, 0.724627, 0.917383, 1.223754, 1.814209",\ + "0.682094, 0.867041, 1.059797, 1.366165, 1.956614",\ + "1.060737, 1.245684, 1.438439, 1.744805, 2.335249",\ + "0.488779, 0.673866, 0.866553, 1.172770, 1.762998",\ + "0.520192, 0.705279, 0.897966, 1.204184, 1.794413",\ + "0.572837, 0.757925, 0.950613, 1.256834, 1.847070",\ + "0.715252, 0.900339, 1.093027, 1.399244, 1.989474",\ + "1.093896, 1.278982, 1.471669, 1.777884, 2.368110",\ + "0.790171, 0.979313, 1.170216, 1.475973, 2.065303",\ + "0.821584, 1.010726, 1.201629, 1.507387, 2.096719",\ + "0.874230, 1.063372, 1.254276, 1.560037, 2.149375",\ + "1.016645, 1.205787, 1.396689, 1.702447, 2.291780",\ + "1.395288, 1.584430, 1.775331, 2.081088, 2.670415"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180378, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091687, 1.091683, 1.091668, 1.091628, 1.091545"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.562500, 380001.593750, 380001.656250, 380001.781250, 380002.156250",\ + "380001.656250, 380001.687500, 380001.750000, 380001.875000, 380002.250000",\ + "380001.750000, 380001.781250, 380001.843750, 380001.968750, 380002.343750",\ + "380001.812500, 380001.843750, 380001.906250, 380002.031250, 380002.406250",\ + "380002.156250, 380002.187500, 380002.250000, 380002.375000, 380002.750000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[3]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[3]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[3]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\ + "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\ + "0.522299, 0.589203, 0.705642, 1.025311, 1.880515",\ + "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\ + "1.134534, 1.201443, 1.317885, 1.637554, 2.492753"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\ + "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\ + "0.579305, 0.610737, 0.663445, 0.805798, 1.184395",\ + "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\ + "1.248357, 1.279789, 1.332497, 1.474850, 1.853447"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\ + "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\ + "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\ + "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\ + "1.077990, 1.144880, 1.261307, 1.580975, 2.436195"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.392762, 0.424174, 0.476820, 0.619235, 0.997878",\ + "0.410167, 0.441580, 0.494226, 0.636641, 1.015284",\ + "0.482737, 0.514149, 0.566795, 0.709210, 1.087853",\ + "0.595371, 0.626784, 0.679430, 0.821845, 1.200488",\ + "1.122399, 1.153812, 1.206458, 1.348872, 1.727516"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\ + "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\ + "0.531672, 0.563103, 0.615812, 0.758164, 1.136761",\ + "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\ + "1.288504, 1.319936, 1.372644, 1.514997, 1.893594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\ + "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\ + "0.755094, 0.821998, 0.938437, 1.258106, 2.113310",\ + "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\ + "1.641748, 1.708657, 1.825099, 2.144769, 2.999968"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262392, 0.293804, 0.346450, 0.488865, 0.867508",\ + "0.286002, 0.317414, 0.370060, 0.512475, 0.891118",\ + "0.357340, 0.388753, 0.441399, 0.583814, 0.962457",\ + "0.477148, 0.508560, 0.561206, 0.703621, 1.082264",\ + "1.022245, 1.053658, 1.106303, 1.248718, 1.627362"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.582342, 0.649232, 0.765660, 1.085328, 1.940547",\ + "0.599034, 0.665924, 0.782351, 1.102020, 1.957239",\ + "0.661428, 0.728319, 0.844746, 1.164414, 2.019634",\ + "0.770818, 0.837708, 0.954135, 1.273803, 2.129023",\ + "1.507966, 1.574856, 1.691283, 2.010951, 2.866171"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\ + "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\ + "0.789396, 0.856300, 0.972739, 1.292408, 2.147612",\ + "0.881867, 0.948772, 1.065210, 1.384879, 2.240083",\ + "1.366874, 1.433786, 1.550230, 1.869900, 2.725095"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\ + "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\ + "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\ + "0.691204, 0.722635, 0.775344, 0.917696, 1.296293",\ + "1.242374, 1.273805, 1.326514, 1.468867, 1.847463"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\ + "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\ + "0.727539, 0.794429, 0.910857, 1.230525, 2.085744",\ + "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\ + "1.269718, 1.336608, 1.453035, 1.772703, 2.627923"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.339768, 0.371181, 0.423827, 0.566242, 0.944885",\ + "0.353114, 0.384527, 0.437173, 0.579588, 0.958231",\ + "0.435092, 0.466504, 0.519150, 0.661565, 1.040208",\ + "0.544311, 0.575724, 0.628370, 0.770784, 1.149428",\ + "1.067931, 1.099343, 1.151989, 1.294404, 1.673047"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\ + "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\ + "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\ + "0.714865, 0.746296, 0.799004, 0.941357, 1.319954",\ + "1.237234, 1.268665, 1.321373, 1.463726, 1.842323"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\ + "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\ + "0.718781, 0.785685, 0.902124, 1.221793, 2.076997",\ + "0.821201, 0.888105, 1.004544, 1.324213, 2.179417",\ + "1.548479, 1.615391, 1.731835, 2.051504, 2.906700"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.267796, 0.299208, 0.351854, 0.494269, 0.872912",\ + "0.284541, 0.315954, 0.368600, 0.511015, 0.889658",\ + "0.362798, 0.394211, 0.446856, 0.589271, 0.967914",\ + "0.486677, 0.518090, 0.570736, 0.713151, 1.091794",\ + "1.055266, 1.086678, 1.139324, 1.281739, 1.660382"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\ + "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\ + "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\ + "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\ + "1.120855, 1.187745, 1.304172, 1.623840, 2.479060"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\ + "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\ + "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\ + "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\ + "1.358120, 1.425029, 1.541471, 1.861141, 2.716340"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\ + "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\ + "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\ + "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\ + "1.229663, 1.261095, 1.313803, 1.456156, 1.834753"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\ + "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\ + "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\ + "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\ + "1.307789, 1.374679, 1.491106, 1.810774, 2.665994"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.361699, 0.393111, 0.445757, 0.588172, 0.966815",\ + "0.375155, 0.406568, 0.459214, 0.601628, 0.980272",\ + "0.456576, 0.487988, 0.540634, 0.683049, 1.061692",\ + "0.566550, 0.597963, 0.650609, 0.793024, 1.171667",\ + "1.091986, 1.123399, 1.176044, 1.318459, 1.697102"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\ + "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\ + "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\ + "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\ + "1.192613, 1.224045, 1.276753, 1.419106, 1.797703"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.606303, 0.673207, 0.789646, 1.109315, 1.964519",\ + "0.618992, 0.685897, 0.802335, 1.122004, 1.977208",\ + "0.673763, 0.740668, 0.857106, 1.176775, 2.031980",\ + "0.776802, 0.843707, 0.960145, 1.279814, 2.135018",\ + "1.483718, 1.550627, 1.667069, 1.986738, 2.841937"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262699, 0.294112, 0.346758, 0.489173, 0.867816",\ + "0.279513, 0.310926, 0.363572, 0.505987, 0.884630",\ + "0.357852, 0.389264, 0.441910, 0.584325, 0.962968",\ + "0.480383, 0.511796, 0.564441, 0.706856, 1.085500",\ + "1.037548, 1.068961, 1.121607, 1.264022, 1.642665"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\ + "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\ + "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\ + "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\ + "1.119877, 1.186768, 1.303195, 1.622863, 2.478083"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[3]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[3]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[3]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "otp_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[3]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[3]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "379999.875000, 379999.937500, 380000.062500, 380000.375000, 380001.218750",\ + "379999.968750, 380000.031250, 380000.156250, 380000.468750, 380001.312500",\ + "380000.062500, 380000.125000, 380000.250000, 380000.562500, 380001.406250",\ + "380000.218750, 380000.281250, 380000.406250, 380000.718750, 380001.562500",\ + "380000.468750, 380000.531250, 380000.656250, 380000.968750, 380001.812500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.468750, 380001.500000, 380001.562500, 380001.687500, 380002.062500",\ + "380001.562500, 380001.593750, 380001.656250, 380001.781250, 380002.156250",\ + "380001.687500, 380001.718750, 380001.781250, 380001.906250, 380002.281250",\ + "380001.875000, 380001.906250, 380001.968750, 380002.093750, 380002.468750",\ + "380002.187500, 380002.218750, 380002.281250, 380002.406250, 380002.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "379999.843750, 379999.906250, 380000.031250, 380000.343750, 380001.187500",\ + "379999.937500, 380000.000000, 380000.125000, 380000.437500, 380001.281250",\ + "380000.000000, 380000.062500, 380000.187500, 380000.500000, 380001.343750",\ + "380000.156250, 380000.218750, 380000.343750, 380000.656250, 380001.500000",\ + "380000.375000, 380000.437500, 380000.562500, 380000.875000, 380001.718750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.375000, 380001.406250, 380001.437500, 380001.593750, 380001.968750",\ + "380001.468750, 380001.500000, 380001.531250, 380001.687500, 380002.062500",\ + "380001.562500, 380001.593750, 380001.625000, 380001.781250, 380002.156250",\ + "380001.750000, 380001.781250, 380001.812500, 380001.968750, 380002.343750",\ + "380002.000000, 380002.031250, 380002.062500, 380002.218750, 380002.593750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[3]_inv_min*/ + +} /* end of pin ast2padmux_o[3] */ + +pin("ast2padmux_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[2]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.257031, 0.528778, 0.797030, 1.242767, 2.134242",\ + "0.323932, 0.595681, 0.863940, 1.309691, 2.201193",\ + "0.440368, 0.712118, 0.980382, 1.426145, 2.317669",\ + "0.760037, 1.031787, 1.300052, 1.745815, 2.637342",\ + "1.615245, 1.886993, 2.155250, 2.600997, 3.492491",\ + "0.315617, 0.587294, 0.855812, 1.300474, 2.190349",\ + "0.382518, 0.654197, 0.922722, 1.367397, 2.257300",\ + "0.498954, 0.770634, 1.039164, 1.483851, 2.373776",\ + "0.818623, 1.090303, 1.358834, 1.803522, 2.693449",\ + "1.673831, 1.945509, 2.214032, 2.658703, 3.548597",\ + "0.460207, 0.733101, 0.999707, 1.444229, 2.334082",\ + "0.527108, 0.800004, 1.066617, 1.511152, 2.401032",\ + "0.643544, 0.916442, 1.183060, 1.627606, 2.517509",\ + "0.963213, 1.236110, 1.502729, 1.947277, 2.837182",\ + "1.818421, 2.091316, 2.357927, 2.802459, 3.692330",\ + "0.496168, 0.770865, 1.036627, 1.481020, 2.370640",\ + "0.563069, 0.837768, 1.103536, 1.547944, 2.437591",\ + "0.679505, 0.954206, 1.219979, 1.664398, 2.554067",\ + "0.999174, 1.273875, 1.539648, 1.984068, 2.873740",\ + "1.854382, 2.129080, 2.394846, 2.839250, 3.728889",\ + "0.825262, 1.134787, 1.388262, 1.830277, 2.716096",\ + "0.892164, 1.201690, 1.455172, 1.897201, 2.783047",\ + "1.008600, 1.318128, 1.571615, 2.013655, 2.899523",\ + "1.328269, 1.637797, 1.891284, 2.333325, 3.219196",\ + "2.183476, 2.493002, 2.746482, 3.188507, 4.074345"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073038, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188932, 0.188943, 0.188966, 0.189013",\ + "0.391836, 0.391843, 0.391858, 0.391892, 0.391961",\ + "0.949092, 0.949105, 0.949137, 0.949210, 0.949357",\ + "2.441339, 2.441341, 2.441346, 2.441358, 2.441383"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.308725, 0.491796, 0.685627, 0.996163, 1.596700",\ + "0.340157, 0.523228, 0.717058, 1.027595, 1.628132",\ + "0.392865, 0.575936, 0.769767, 1.080304, 1.680844",\ + "0.535218, 0.718289, 0.912119, 1.222656, 1.823194",\ + "0.913815, 1.096886, 1.290716, 1.601252, 2.201788",\ + "0.368637, 0.551695, 0.745581, 1.055944, 1.656317",\ + "0.400068, 0.583126, 0.777012, 1.087376, 1.687749",\ + "0.452777, 0.635835, 0.829721, 1.140085, 1.740461",\ + "0.595130, 0.778187, 0.972073, 1.282437, 1.882811",\ + "0.973727, 1.156784, 1.350670, 1.661033, 2.261405",\ + "0.501379, 0.683946, 0.877464, 1.187801, 1.788124",\ + "0.532811, 0.715378, 0.908895, 1.219233, 1.819557",\ + "0.585519, 0.768086, 0.961603, 1.271942, 1.872268",\ + "0.727872, 0.910439, 1.103956, 1.414294, 2.014618",\ + "1.106469, 1.289036, 1.482553, 1.792891, 2.393212",\ + "0.534516, 0.717073, 0.910588, 1.220754, 1.820733",\ + "0.565947, 0.748505, 0.942020, 1.252186, 1.852165",\ + "0.618656, 0.801213, 0.994728, 1.304895, 1.904876",\ + "0.761009, 0.943566, 1.137081, 1.447247, 2.047226",\ + "1.139605, 1.322163, 1.515678, 1.825843, 2.425821",\ + "0.835592, 1.022294, 1.214223, 1.523770, 2.122581",\ + "0.867023, 1.053726, 1.245655, 1.555202, 2.154014",\ + "0.919731, 1.106434, 1.298363, 1.607911, 2.206725",\ + "1.062084, 1.248787, 1.440716, 1.750263, 2.349075",\ + "1.440681, 1.627384, 1.819313, 2.128859, 2.727669"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[1]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.252558, 0.520745, 0.784515, 1.222569, 2.097608",\ + "0.319449, 0.587637, 0.851411, 1.289475, 2.164534",\ + "0.435876, 0.704065, 0.967843, 1.405915, 2.280990",\ + "0.755544, 1.023733, 1.287511, 1.725584, 2.600661",\ + "1.610764, 1.878952, 2.142725, 2.580786, 3.455839",\ + "0.311120, 0.579252, 0.843280, 1.280275, 2.153714",\ + "0.378011, 0.646143, 0.910176, 1.347182, 2.220640",\ + "0.494438, 0.762572, 1.026608, 1.463622, 2.337097",\ + "0.814106, 1.082240, 1.346276, 1.783291, 2.656767",\ + "1.669326, 1.937458, 2.201490, 2.638493, 3.511946",\ + "0.455460, 0.724999, 0.987167, 1.424079, 2.297447",\ + "0.522351, 0.791891, 1.054064, 1.490985, 2.364373",\ + "0.638778, 0.908319, 1.170496, 1.607426, 2.480830",\ + "0.958446, 1.227987, 1.490164, 1.927095, 2.800500",\ + "1.813666, 2.083206, 2.345378, 2.782297, 3.655679",\ + "0.491341, 0.762735, 1.024086, 1.460950, 2.334005",\ + "0.558231, 0.829626, 1.090982, 1.527856, 2.400931",\ + "0.674659, 0.946054, 1.207414, 1.644296, 2.517388",\ + "0.994327, 1.265722, 1.527082, 1.963966, 2.837059",\ + "1.849546, 2.120941, 2.382296, 2.819168, 3.692237",\ + "0.819555, 1.126080, 1.375645, 1.810251, 2.679461",\ + "0.886446, 1.192972, 1.442542, 1.877157, 2.746387",\ + "1.002873, 1.309400, 1.558974, 1.993597, 2.862844",\ + "1.322541, 1.629068, 1.878642, 2.313266, 3.182515",\ + "2.177761, 2.484287, 2.733856, 3.168468, 4.037693"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441331, 2.441334, 2.441343, 2.441361"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.262934, 0.448489, 0.641595, 0.948064, 1.538713",\ + "0.294346, 0.479902, 0.673008, 0.979478, 1.570129",\ + "0.346992, 0.532548, 0.725656, 1.032128, 1.622785",\ + "0.489407, 0.674962, 0.868069, 1.174539, 1.765190",\ + "0.868050, 1.053605, 1.246711, 1.553179, 2.143825",\ + "0.322845, 0.508317, 0.701440, 1.007833, 1.598330",\ + "0.354258, 0.539729, 0.732853, 1.039247, 1.629746",\ + "0.406904, 0.592376, 0.785500, 1.091897, 1.682402",\ + "0.549319, 0.734790, 0.927914, 1.234307, 1.824806",\ + "0.927962, 1.113433, 1.306556, 1.612947, 2.203442",\ + "0.455621, 0.640568, 0.833323, 1.139690, 1.730137",\ + "0.487034, 0.671981, 0.864736, 1.171104, 1.761553",\ + "0.539679, 0.724627, 0.917383, 1.223754, 1.814209",\ + "0.682094, 0.867041, 1.059797, 1.366165, 1.956614",\ + "1.060737, 1.245684, 1.438439, 1.744805, 2.335249",\ + "0.488779, 0.673866, 0.866553, 1.172770, 1.762998",\ + "0.520192, 0.705279, 0.897966, 1.204184, 1.794413",\ + "0.572837, 0.757925, 0.950613, 1.256834, 1.847070",\ + "0.715252, 0.900339, 1.093027, 1.399244, 1.989474",\ + "1.093896, 1.278982, 1.471669, 1.777884, 2.368110",\ + "0.790171, 0.979313, 1.170216, 1.475973, 2.065303",\ + "0.821584, 1.010726, 1.201629, 1.507387, 2.096719",\ + "0.874230, 1.063372, 1.254276, 1.560037, 2.149375",\ + "1.016645, 1.205787, 1.396689, 1.702447, 2.291780",\ + "1.395288, 1.584430, 1.775331, 2.081088, 2.670415"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180378, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091687, 1.091683, 1.091668, 1.091628, 1.091545"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[2]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[2]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[2]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\ + "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\ + "0.522299, 0.589203, 0.705642, 1.025311, 1.880515",\ + "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\ + "1.134534, 1.201443, 1.317885, 1.637554, 2.492753"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\ + "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\ + "0.579305, 0.610737, 0.663445, 0.805798, 1.184395",\ + "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\ + "1.248357, 1.279789, 1.332497, 1.474850, 1.853447"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\ + "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\ + "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\ + "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\ + "1.077990, 1.144880, 1.261307, 1.580975, 2.436195"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.392762, 0.424174, 0.476820, 0.619235, 0.997878",\ + "0.410167, 0.441580, 0.494226, 0.636641, 1.015284",\ + "0.482737, 0.514149, 0.566795, 0.709210, 1.087853",\ + "0.595371, 0.626784, 0.679430, 0.821845, 1.200488",\ + "1.122399, 1.153812, 1.206458, 1.348872, 1.727516"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\ + "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\ + "0.531672, 0.563103, 0.615812, 0.758164, 1.136761",\ + "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\ + "1.288504, 1.319936, 1.372644, 1.514997, 1.893594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\ + "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\ + "0.755094, 0.821998, 0.938437, 1.258106, 2.113310",\ + "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\ + "1.641748, 1.708657, 1.825099, 2.144769, 2.999968"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262392, 0.293804, 0.346450, 0.488865, 0.867508",\ + "0.286002, 0.317414, 0.370060, 0.512475, 0.891118",\ + "0.357340, 0.388753, 0.441399, 0.583814, 0.962457",\ + "0.477148, 0.508560, 0.561206, 0.703621, 1.082264",\ + "1.022245, 1.053658, 1.106303, 1.248718, 1.627362"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.582342, 0.649232, 0.765660, 1.085328, 1.940547",\ + "0.599034, 0.665924, 0.782351, 1.102020, 1.957239",\ + "0.661428, 0.728319, 0.844746, 1.164414, 2.019634",\ + "0.770818, 0.837708, 0.954135, 1.273803, 2.129023",\ + "1.507966, 1.574856, 1.691283, 2.010951, 2.866171"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\ + "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\ + "0.789396, 0.856300, 0.972739, 1.292408, 2.147612",\ + "0.881867, 0.948772, 1.065210, 1.384879, 2.240083",\ + "1.366874, 1.433786, 1.550230, 1.869900, 2.725095"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\ + "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\ + "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\ + "0.691204, 0.722635, 0.775344, 0.917696, 1.296293",\ + "1.242374, 1.273805, 1.326514, 1.468867, 1.847463"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\ + "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\ + "0.727539, 0.794429, 0.910857, 1.230525, 2.085744",\ + "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\ + "1.269718, 1.336608, 1.453035, 1.772703, 2.627923"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.339768, 0.371181, 0.423827, 0.566242, 0.944885",\ + "0.353114, 0.384527, 0.437173, 0.579588, 0.958231",\ + "0.435092, 0.466504, 0.519150, 0.661565, 1.040208",\ + "0.544311, 0.575724, 0.628370, 0.770784, 1.149428",\ + "1.067931, 1.099343, 1.151989, 1.294404, 1.673047"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\ + "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\ + "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\ + "0.714865, 0.746296, 0.799004, 0.941357, 1.319954",\ + "1.237234, 1.268665, 1.321373, 1.463726, 1.842323"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\ + "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\ + "0.718781, 0.785685, 0.902124, 1.221793, 2.076997",\ + "0.821201, 0.888105, 1.004544, 1.324213, 2.179417",\ + "1.548479, 1.615391, 1.731835, 2.051504, 2.906700"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.267796, 0.299208, 0.351854, 0.494269, 0.872912",\ + "0.284541, 0.315954, 0.368600, 0.511015, 0.889658",\ + "0.362798, 0.394211, 0.446856, 0.589271, 0.967914",\ + "0.486677, 0.518090, 0.570736, 0.713151, 1.091794",\ + "1.055266, 1.086678, 1.139324, 1.281739, 1.660382"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\ + "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\ + "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\ + "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\ + "1.120855, 1.187745, 1.304172, 1.623840, 2.479060"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\ + "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\ + "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\ + "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\ + "1.358120, 1.425029, 1.541471, 1.861141, 2.716340"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\ + "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\ + "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\ + "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\ + "1.229663, 1.261095, 1.313803, 1.456156, 1.834753"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\ + "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\ + "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\ + "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\ + "1.307789, 1.374679, 1.491106, 1.810774, 2.665994"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.361699, 0.393111, 0.445757, 0.588172, 0.966815",\ + "0.375155, 0.406568, 0.459214, 0.601628, 0.980272",\ + "0.456576, 0.487988, 0.540634, 0.683049, 1.061692",\ + "0.566550, 0.597963, 0.650609, 0.793024, 1.171667",\ + "1.091986, 1.123399, 1.176044, 1.318459, 1.697102"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\ + "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\ + "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\ + "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\ + "1.192613, 1.224045, 1.276753, 1.419106, 1.797703"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.606303, 0.673207, 0.789646, 1.109315, 1.964519",\ + "0.618992, 0.685897, 0.802335, 1.122004, 1.977208",\ + "0.673763, 0.740668, 0.857106, 1.176775, 2.031980",\ + "0.776802, 0.843707, 0.960145, 1.279814, 2.135018",\ + "1.483718, 1.550627, 1.667069, 1.986738, 2.841937"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262699, 0.294112, 0.346758, 0.489173, 0.867816",\ + "0.279513, 0.310926, 0.363572, 0.505987, 0.884630",\ + "0.357852, 0.389264, 0.441910, 0.584325, 0.962968",\ + "0.480383, 0.511796, 0.564441, 0.706856, 1.085500",\ + "1.037548, 1.068961, 1.121607, 1.264022, 1.642665"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\ + "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\ + "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\ + "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\ + "1.119877, 1.186768, 1.303195, 1.622863, 2.478083"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[2]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[2]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[2]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "otp_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[2]_ast2padmux_o[2]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[2]_ast2padmux_o[2]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[2]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[2]_inv_min*/ + +} /* end of pin ast2padmux_o[2] */ + +pin("ast2padmux_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[1]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.257031, 0.528778, 0.797030, 1.242767, 2.134242",\ + "0.323932, 0.595681, 0.863940, 1.309691, 2.201193",\ + "0.440368, 0.712118, 0.980382, 1.426145, 2.317669",\ + "0.760037, 1.031787, 1.300052, 1.745815, 2.637342",\ + "1.615245, 1.886993, 2.155250, 2.600997, 3.492491",\ + "0.315617, 0.587294, 0.855812, 1.300474, 2.190349",\ + "0.382518, 0.654197, 0.922722, 1.367397, 2.257300",\ + "0.498954, 0.770634, 1.039164, 1.483851, 2.373776",\ + "0.818623, 1.090303, 1.358834, 1.803522, 2.693449",\ + "1.673831, 1.945509, 2.214032, 2.658703, 3.548597",\ + "0.460207, 0.733101, 0.999707, 1.444229, 2.334082",\ + "0.527108, 0.800004, 1.066617, 1.511152, 2.401032",\ + "0.643544, 0.916442, 1.183060, 1.627606, 2.517509",\ + "0.963213, 1.236110, 1.502729, 1.947277, 2.837182",\ + "1.818421, 2.091316, 2.357927, 2.802459, 3.692330",\ + "0.496168, 0.770865, 1.036627, 1.481020, 2.370640",\ + "0.563069, 0.837768, 1.103536, 1.547944, 2.437591",\ + "0.679505, 0.954206, 1.219979, 1.664398, 2.554067",\ + "0.999174, 1.273875, 1.539648, 1.984068, 2.873740",\ + "1.854382, 2.129080, 2.394846, 2.839250, 3.728889",\ + "0.825262, 1.134787, 1.388262, 1.830277, 2.716096",\ + "0.892164, 1.201690, 1.455172, 1.897201, 2.783047",\ + "1.008600, 1.318128, 1.571615, 2.013655, 2.899523",\ + "1.328269, 1.637797, 1.891284, 2.333325, 3.219196",\ + "2.183476, 2.493002, 2.746482, 3.188507, 4.074345"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949101, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073037, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188931, 0.188942, 0.188966, 0.189013",\ + "0.391836, 0.391841, 0.391857, 0.391892, 0.391961",\ + "0.949092, 0.949102, 0.949136, 0.949210, 0.949357",\ + "2.441339, 2.441340, 2.441346, 2.441358, 2.441383",\ + "0.073036, 0.073038, 0.073042, 0.073052, 0.073073",\ + "0.188928, 0.188932, 0.188943, 0.188966, 0.189013",\ + "0.391836, 0.391843, 0.391858, 0.391892, 0.391961",\ + "0.949092, 0.949105, 0.949137, 0.949210, 0.949357",\ + "2.441339, 2.441341, 2.441346, 2.441358, 2.441383"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.308725, 0.491796, 0.685627, 0.996163, 1.596700",\ + "0.340157, 0.523228, 0.717058, 1.027595, 1.628132",\ + "0.392865, 0.575936, 0.769767, 1.080304, 1.680844",\ + "0.535218, 0.718289, 0.912119, 1.222656, 1.823194",\ + "0.913815, 1.096886, 1.290716, 1.601252, 2.201788",\ + "0.368637, 0.551695, 0.745581, 1.055944, 1.656317",\ + "0.400068, 0.583126, 0.777012, 1.087376, 1.687749",\ + "0.452777, 0.635835, 0.829721, 1.140085, 1.740461",\ + "0.595130, 0.778187, 0.972073, 1.282437, 1.882811",\ + "0.973727, 1.156784, 1.350670, 1.661033, 2.261405",\ + "0.501379, 0.683946, 0.877464, 1.187801, 1.788124",\ + "0.532811, 0.715378, 0.908895, 1.219233, 1.819557",\ + "0.585519, 0.768086, 0.961603, 1.271942, 1.872268",\ + "0.727872, 0.910439, 1.103956, 1.414294, 2.014618",\ + "1.106469, 1.289036, 1.482553, 1.792891, 2.393212",\ + "0.534516, 0.717073, 0.910588, 1.220754, 1.820733",\ + "0.565947, 0.748505, 0.942020, 1.252186, 1.852165",\ + "0.618656, 0.801213, 0.994728, 1.304895, 1.904876",\ + "0.761009, 0.943566, 1.137081, 1.447247, 2.047226",\ + "1.139605, 1.322163, 1.515678, 1.825843, 2.425821",\ + "0.835592, 1.022294, 1.214223, 1.523770, 2.122581",\ + "0.867023, 1.053726, 1.245655, 1.555202, 2.154014",\ + "0.919731, 1.106434, 1.298363, 1.607911, 2.206725",\ + "1.062084, 1.248787, 1.440716, 1.750263, 2.349075",\ + "1.440681, 1.627384, 1.819313, 2.128859, 2.727669"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796",\ + "0.039143, 0.039143, 0.039143, 0.039145, 0.039150",\ + "0.090610, 0.090610, 0.090610, 0.090608, 0.090604",\ + "0.180695, 0.180695, 0.180695, 0.180700, 0.180710",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429279",\ + "1.090837, 1.090837, 1.090837, 1.090825, 1.090796"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_b_o[0]" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.252558, 0.520745, 0.784515, 1.222569, 2.097608",\ + "0.319449, 0.587637, 0.851411, 1.289475, 2.164534",\ + "0.435876, 0.704065, 0.967843, 1.405915, 2.280990",\ + "0.755544, 1.023733, 1.287511, 1.725584, 2.600661",\ + "1.610764, 1.878952, 2.142725, 2.580786, 3.455839",\ + "0.311120, 0.579252, 0.843280, 1.280275, 2.153714",\ + "0.378011, 0.646143, 0.910176, 1.347182, 2.220640",\ + "0.494438, 0.762572, 1.026608, 1.463622, 2.337097",\ + "0.814106, 1.082240, 1.346276, 1.783291, 2.656767",\ + "1.669326, 1.937458, 2.201490, 2.638493, 3.511946",\ + "0.455460, 0.724999, 0.987167, 1.424079, 2.297447",\ + "0.522351, 0.791891, 1.054064, 1.490985, 2.364373",\ + "0.638778, 0.908319, 1.170496, 1.607426, 2.480830",\ + "0.958446, 1.227987, 1.490164, 1.927095, 2.800500",\ + "1.813666, 2.083206, 2.345378, 2.782297, 3.655679",\ + "0.491341, 0.762735, 1.024086, 1.460950, 2.334005",\ + "0.558231, 0.829626, 1.090982, 1.527856, 2.400931",\ + "0.674659, 0.946054, 1.207414, 1.644296, 2.517388",\ + "0.994327, 1.265722, 1.527082, 1.963966, 2.837059",\ + "1.849546, 2.120941, 2.382296, 2.819168, 3.692237",\ + "0.819555, 1.126080, 1.375645, 1.810251, 2.679461",\ + "0.886446, 1.192972, 1.442542, 1.877157, 2.746387",\ + "1.002873, 1.309400, 1.558974, 1.993597, 2.862844",\ + "1.322541, 1.629068, 1.878642, 2.313266, 3.182515",\ + "2.177761, 2.484287, 2.733856, 3.168468, 4.037693"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188919, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949028, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949118, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391815, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949029, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441330, 2.441334, 2.441343, 2.441361",\ + "0.073031, 0.073031, 0.073033, 0.073040, 0.073054",\ + "0.188915, 0.188915, 0.188920, 0.188937, 0.188971",\ + "0.391816, 0.391816, 0.391824, 0.391849, 0.391899",\ + "0.949014, 0.949034, 0.949065, 0.949119, 0.949226",\ + "2.441330, 2.441331, 2.441334, 2.441343, 2.441361"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.262934, 0.448489, 0.641595, 0.948064, 1.538713",\ + "0.294346, 0.479902, 0.673008, 0.979478, 1.570129",\ + "0.346992, 0.532548, 0.725656, 1.032128, 1.622785",\ + "0.489407, 0.674962, 0.868069, 1.174539, 1.765190",\ + "0.868050, 1.053605, 1.246711, 1.553179, 2.143825",\ + "0.322845, 0.508317, 0.701440, 1.007833, 1.598330",\ + "0.354258, 0.539729, 0.732853, 1.039247, 1.629746",\ + "0.406904, 0.592376, 0.785500, 1.091897, 1.682402",\ + "0.549319, 0.734790, 0.927914, 1.234307, 1.824806",\ + "0.927962, 1.113433, 1.306556, 1.612947, 2.203442",\ + "0.455621, 0.640568, 0.833323, 1.139690, 1.730137",\ + "0.487034, 0.671981, 0.864736, 1.171104, 1.761553",\ + "0.539679, 0.724627, 0.917383, 1.223754, 1.814209",\ + "0.682094, 0.867041, 1.059797, 1.366165, 1.956614",\ + "1.060737, 1.245684, 1.438439, 1.744805, 2.335249",\ + "0.488779, 0.673866, 0.866553, 1.172770, 1.762998",\ + "0.520192, 0.705279, 0.897966, 1.204184, 1.794413",\ + "0.572837, 0.757925, 0.950613, 1.256834, 1.847070",\ + "0.715252, 0.900339, 1.093027, 1.399244, 1.989474",\ + "1.093896, 1.278982, 1.471669, 1.777884, 2.368110",\ + "0.790171, 0.979313, 1.170216, 1.475973, 2.065303",\ + "0.821584, 1.010726, 1.201629, 1.507387, 2.096719",\ + "0.874230, 1.063372, 1.254276, 1.560037, 2.149375",\ + "1.016645, 1.205787, 1.396689, 1.702447, 2.291780",\ + "1.395288, 1.584430, 1.775331, 2.081088, 2.670415"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.001003, 0.074002, 0.161255, 0.321507, 0.642011"); + values ( "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090713",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180377, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091688, 1.091683, 1.091668, 1.091629, 1.091545",\ + "0.039012, 0.039013, 0.039015, 0.039021, 0.039034",\ + "0.090733, 0.090732, 0.090730, 0.090725, 0.090712",\ + "0.180378, 0.180379, 0.180385, 0.180400, 0.180431",\ + "0.429204, 0.429204, 0.429205, 0.429209, 0.429216",\ + "1.091687, 1.091683, 1.091668, 1.091628, 1.091545"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970008.750000, 970008.812500, 970008.937500, 970009.250000, 970010.125000",\ + "970008.875000, 970008.937500, 970009.062500, 970009.375000, 970010.250000",\ + "970009.000000, 970009.062500, 970009.187500, 970009.500000, 970010.375000",\ + "970009.000000, 970009.062500, 970009.187500, 970009.500000, 970010.375000",\ + "970009.375000, 970009.437500, 970009.562500, 970009.875000, 970010.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189354, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189365, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189385, 0.392560, 0.950608, 2.441526",\ + "0.073824, 0.189425, 0.393252, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970006.125000, 970006.187500, 970006.250000, 970006.375000, 970006.750000",\ + "970006.250000, 970006.312500, 970006.375000, 970006.500000, 970006.875000",\ + "970006.250000, 970006.312500, 970006.375000, 970006.500000, 970006.875000",\ + "970006.375000, 970006.437500, 970006.500000, 970006.625000, 970007.000000",\ + "970006.625000, 970006.687500, 970006.750000, 970006.875000, 970007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[1]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[1]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[1]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.443642, 0.510546, 0.626985, 0.946654, 1.801858",\ + "0.465905, 0.532810, 0.649248, 0.968917, 1.824121",\ + "0.522299, 0.589203, 0.705642, 1.025311, 1.880515",\ + "0.620162, 0.687066, 0.803505, 1.123173, 1.978378",\ + "1.134534, 1.201443, 1.317885, 1.637554, 2.492753"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.490585, 0.522017, 0.574725, 0.717078, 1.095675",\ + "0.512119, 0.543551, 0.596259, 0.738612, 1.117209",\ + "0.579305, 0.610737, 0.663445, 0.805798, 1.184395",\ + "0.689604, 0.721035, 0.773743, 0.916096, 1.294693",\ + "1.248357, 1.279789, 1.332497, 1.474850, 1.853447"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412827, 0.479717, 0.596144, 0.915812, 1.771032",\ + "0.433604, 0.500495, 0.616922, 0.936590, 1.791810",\ + "0.491196, 0.558086, 0.674513, 0.994181, 1.849401",\ + "0.589141, 0.656031, 0.772458, 1.092126, 1.947346",\ + "1.077990, 1.144880, 1.261307, 1.580975, 2.436195"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.392762, 0.424174, 0.476820, 0.619235, 0.997878",\ + "0.410167, 0.441580, 0.494226, 0.636641, 1.015284",\ + "0.482737, 0.514149, 0.566795, 0.709210, 1.087853",\ + "0.595371, 0.626784, 0.679430, 0.821845, 1.200488",\ + "1.122399, 1.153812, 1.206458, 1.348872, 1.727516"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437382, 0.468814, 0.521522, 0.663875, 1.042472",\ + "0.462451, 0.493883, 0.546591, 0.688944, 1.067541",\ + "0.531672, 0.563103, 0.615812, 0.758164, 1.136761",\ + "0.655903, 0.687335, 0.740043, 0.882396, 1.260993",\ + "1.288504, 1.319936, 1.372644, 1.514997, 1.893594"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.675759, 0.742664, 0.859102, 1.178771, 2.033976",\ + "0.696234, 0.763138, 0.879577, 1.199246, 2.054450",\ + "0.755094, 0.821998, 0.938437, 1.258106, 2.113310",\ + "0.864334, 0.931238, 1.047677, 1.367346, 2.222550",\ + "1.641748, 1.708657, 1.825099, 2.144769, 2.999968"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949108, 2.441341",\ + "0.073042, 0.188941, 0.391856, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262392, 0.293804, 0.346450, 0.488865, 0.867508",\ + "0.286002, 0.317414, 0.370060, 0.512475, 0.891118",\ + "0.357340, 0.388753, 0.441399, 0.583814, 0.962457",\ + "0.477148, 0.508560, 0.561206, 0.703621, 1.082264",\ + "1.022245, 1.053658, 1.106303, 1.248718, 1.627362"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.582342, 0.649232, 0.765660, 1.085328, 1.940547",\ + "0.599034, 0.665924, 0.782351, 1.102020, 1.957239",\ + "0.661428, 0.728319, 0.844746, 1.164414, 2.019634",\ + "0.770818, 0.837708, 0.954135, 1.273803, 2.129023",\ + "1.507966, 1.574856, 1.691283, 2.010951, 2.866171"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.180024, 0.211452, 0.264149, 0.406513, 0.785119",\ + "0.193406, 0.224834, 0.277531, 0.419896, 0.798501",\ + "0.275919, 0.307349, 0.360051, 0.502410, 0.881011",\ + "0.400910, 0.432352, 0.485095, 0.627414, 1.005985",\ + "0.975060, 1.010086, 1.063144, 1.205732, 1.584486"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039119, 0.090633, 0.180636, 0.429262, 1.090996",\ + "0.039132, 0.090633, 0.180667, 0.429269, 1.090996",\ + "0.039215, 0.090633, 0.180868, 0.429314, 1.090996",\ + "0.049347, 0.094034, 0.180868, 0.429355, 1.091896"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.465437, 0.532662, 0.649281, 0.969044, 1.824018",\ + "0.477695, 0.544920, 0.661539, 0.981302, 1.836276",\ + "0.541916, 0.609140, 0.725760, 1.045521, 1.900495",\ + "0.644626, 0.711856, 0.828474, 1.148242, 2.003221",\ + "1.319722, 1.387140, 1.503696, 1.823662, 2.678811"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189282, 0.392442, 0.950607, 2.441526",\ + "0.073862, 0.189282, 0.392442, 0.950619, 2.441526",\ + "0.075399, 0.189282, 0.392442, 0.951039, 2.441526"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.159139, 0.190553, 0.243202, 0.385613, 0.764254",\ + "0.170514, 0.201928, 0.254577, 0.396989, 0.775629",\ + "0.255576, 0.286993, 0.339652, 0.482053, 0.860686",\ + "0.379908, 0.411340, 0.464049, 0.606401, 0.984998",\ + "0.945167, 0.979651, 1.032663, 1.175209, 1.553933"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039020, 0.090609, 0.180397, 0.429208, 1.090831",\ + "0.039042, 0.090609, 0.180449, 0.429220, 1.090831",\ + "0.039144, 0.090609, 0.180675, 0.429276, 1.090831",\ + "0.047820, 0.093501, 0.180675, 0.429352, 1.091629"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.461683, 0.528880, 0.645509, 0.965243, 1.820192",\ + "0.470327, 0.537524, 0.654153, 0.973887, 1.828836",\ + "0.538174, 0.605371, 0.721999, 1.041733, 1.896681",\ + "0.640782, 0.707985, 0.824611, 1.144351, 1.999304",\ + "1.312551, 1.379913, 1.496487, 1.816396, 2.671496"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073594, 0.189124, 0.392388, 0.950544, 2.441454",\ + "0.073633, 0.189124, 0.392388, 0.950557, 2.441454",\ + "0.074954, 0.189124, 0.392388, 0.950917, 2.441454"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.500858, 0.568082, 0.684702, 1.004464, 1.859437",\ + "0.516623, 0.583848, 0.700467, 1.020230, 1.875203",\ + "0.590734, 0.657958, 0.774578, 1.094340, 1.949314",\ + "0.681946, 0.749171, 0.865790, 1.185553, 2.040526",\ + "1.108576, 1.175805, 1.292423, 1.612190, 2.467167"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.209985, 0.241400, 0.294052, 0.436461, 0.815099",\ + "0.221857, 0.253271, 0.305923, 0.448332, 0.826970",\ + "0.304351, 0.335766, 0.388417, 0.530826, 0.909465",\ + "0.409226, 0.440642, 0.493298, 0.635702, 1.014338",\ + "0.909442, 0.940877, 0.993596, 1.135938, 1.514527"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040752, 0.090632, 0.180638, 0.429262, 1.092497",\ + "0.040759, 0.090626, 0.180653, 0.429266, 1.092499",\ + "0.040922, 0.090525, 0.180916, 0.429325, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073816, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073848, 0.189277, 0.392440, 0.950615, 2.441524"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039025, 0.090327, 0.180161, 0.428971, 1.091605",\ + "0.039034, 0.090327, 0.180161, 0.428971, 1.091542",\ + "0.039166, 0.090324, 0.180166, 0.428948, 1.090692"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.176901, 0.208329, 0.261026, 0.403390, 0.781996",\ + "0.196158, 0.227585, 0.280282, 0.422647, 0.801252",\ + "0.273304, 0.304734, 0.357436, 0.499795, 0.878396",\ + "0.397207, 0.428649, 0.481392, 0.623711, 1.002282",\ + "0.961790, 0.996912, 1.049978, 1.192575, 1.571334"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180635, 0.429262, 1.092497",\ + "0.040752, 0.090633, 0.180666, 0.429269, 1.092497",\ + "0.040771, 0.090633, 0.180871, 0.429315, 1.092502",\ + "0.049622, 0.094130, 0.180871, 0.429356, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.455825, 0.523049, 0.639668, 0.959430, 1.814404",\ + "0.468963, 0.536187, 0.652807, 0.972569, 1.827542",\ + "0.531289, 0.598514, 0.715133, 1.034896, 1.889869",\ + "0.640154, 0.707387, 0.824004, 1.143775, 1.998757",\ + "1.332501, 1.399969, 1.516508, 1.836528, 2.691724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073812, 0.189282, 0.392442, 0.950605, 2.441527",\ + "0.073814, 0.189281, 0.392442, 0.950606, 2.441526",\ + "0.073887, 0.189271, 0.392439, 0.950626, 2.441522",\ + "0.075818, 0.189005, 0.392348, 0.951153, 2.441399"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.155833, 0.187247, 0.239896, 0.382308, 0.760949",\ + "0.173482, 0.204896, 0.257545, 0.399957, 0.778598",\ + "0.252964, 0.284381, 0.337040, 0.479441, 0.858074",\ + "0.376196, 0.407628, 0.460337, 0.602689, 0.981285",\ + "0.931678, 0.966257, 1.019278, 1.161831, 1.540560"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039018, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039041, 0.090294, 0.180161, 0.428752, 1.090822",\ + "0.039146, 0.090294, 0.180167, 0.428752, 1.090822",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.091676"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.452081, 0.519278, 0.635907, 0.955640, 1.810589",\ + "0.461862, 0.529059, 0.645688, 0.965421, 1.820370",\ + "0.527542, 0.594739, 0.711368, 1.031102, 1.886050",\ + "0.636262, 0.703467, 0.820093, 1.139835, 1.994791",\ + "1.324350, 1.391756, 1.508316, 1.828270, 2.683409"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.325984, 0.393209, 0.509828, 0.829592, 1.684567",\ + "0.341732, 0.408957, 0.525576, 0.845340, 1.700314",\ + "0.405621, 0.472847, 0.589466, 0.909229, 1.764204",\ + "0.483984, 0.551208, 0.667827, 0.987590, 1.842564",\ + "0.876566, 0.943791, 1.060410, 1.380173, 2.235147"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.207560, 0.238992, 0.291700, 0.434053, 0.812650",\ + "0.223441, 0.254873, 0.307582, 0.449934, 0.828531",\ + "0.292964, 0.324396, 0.377105, 0.519457, 0.898054",\ + "0.382304, 0.413736, 0.466444, 0.608797, 0.987394",\ + "0.808201, 0.839636, 0.892354, 1.034697, 1.413287"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.298728, 0.365697, 0.482189, 0.801862, 1.656989",\ + "0.312838, 0.379807, 0.496299, 0.815972, 1.671100",\ + "0.378416, 0.445385, 0.561877, 0.881551, 1.736677",\ + "0.456978, 0.523948, 0.640441, 0.960115, 1.815240",\ + "0.852482, 0.919491, 1.036016, 1.355692, 2.210772"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.185526, 0.216941, 0.269593, 0.412001, 0.790640",\ + "0.197528, 0.228943, 0.281595, 0.424004, 0.802642",\ + "0.270950, 0.302365, 0.355017, 0.497425, 0.876064",\ + "0.360375, 0.391790, 0.444442, 0.586850, 0.965489",\ + "0.786063, 0.817479, 0.870138, 1.012540, 1.391174"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040785, 0.090610, 0.180744, 0.429286, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.596327, 0.663552, 0.780171, 1.099935, 1.954909",\ + "0.609131, 0.676356, 0.792975, 1.112739, 1.967713",\ + "0.677113, 0.744339, 0.860958, 1.180721, 2.035696",\ + "0.788810, 0.856034, 0.972654, 1.292416, 2.147390",\ + "1.273667, 1.340892, 1.457511, 1.777274, 2.632248"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189281, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262848, 0.294262, 0.346915, 0.489323, 0.867962",\ + "0.276998, 0.308413, 0.361065, 0.503474, 0.882112",\ + "0.356726, 0.388141, 0.440793, 0.583202, 0.961840",\ + "0.457948, 0.489362, 0.542015, 0.684423, 1.063061",\ + "0.929777, 0.961193, 1.013852, 1.156254, 1.534888"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039039, 0.090322, 0.180169, 0.428938, 1.091513"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "0.999580, 1.030743, 1.083361, 1.225858, 1.604500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180732, 0.429283, 1.092497",\ + "0.042004, 0.091469, 0.180867, 0.429340, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.597332, 0.664558, 0.781177, 1.100940, 1.955915",\ + "0.618079, 0.685305, 0.801924, 1.121688, 1.976662",\ + "0.683404, 0.750630, 0.867249, 1.187012, 2.041987",\ + "0.797603, 0.864828, 0.981447, 1.301210, 2.156184",\ + "1.375793, 1.443018, 1.559637, 1.879400, 2.734374"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950609, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073823, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073819, 0.189281, 0.392442, 0.950607, 2.441526",\ + "0.073817, 0.189281, 0.392442, 0.950607, 2.441526"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.150722, 0.182137, 0.234789, 0.377197, 0.755836",\ + "0.171205, 0.202620, 0.255272, 0.397681, 0.776319",\ + "0.246518, 0.277932, 0.330585, 0.472993, 0.851631",\ + "0.352324, 0.383738, 0.436391, 0.578799, 0.957437",\ + "0.825559, 0.856975, 0.909634, 1.052036, 1.430670"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091598",\ + "0.039038, 0.090323, 0.180168, 0.428941, 1.091519"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.277343, 0.344312, 0.460804, 0.780477, 1.635605",\ + "0.293355, 0.360323, 0.476815, 0.796489, 1.651616",\ + "0.366113, 0.433085, 0.549579, 0.869253, 1.724376",\ + "0.487008, 0.554003, 0.670516, 0.990192, 1.845287",\ + "1.141953, 1.209132, 1.325766, 1.645481, 2.500414"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.700503, 0.767407, 0.883846, 1.203515, 2.058719",\ + "0.718853, 0.785757, 0.902195, 1.221864, 2.077069",\ + "0.789396, 0.856300, 0.972739, 1.292408, 2.147612",\ + "0.881867, 0.948772, 1.065210, 1.384879, 2.240083",\ + "1.366874, 1.433786, 1.550230, 1.869900, 2.725095"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.488066, 0.519497, 0.572205, 0.714558, 1.093155",\ + "0.505493, 0.536925, 0.589633, 0.731986, 1.110583",\ + "0.582890, 0.614322, 0.667030, 0.809383, 1.187980",\ + "0.691204, 0.722635, 0.775344, 0.917696, 1.296293",\ + "1.242374, 1.273805, 1.326514, 1.468867, 1.847463"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.636502, 0.703393, 0.819820, 1.139488, 1.994708",\ + "0.653118, 0.720008, 0.836435, 1.156103, 2.011323",\ + "0.727539, 0.794429, 0.910857, 1.230525, 2.085744",\ + "0.821960, 0.888850, 1.005277, 1.324945, 2.180165",\ + "1.269718, 1.336608, 1.453035, 1.772703, 2.627923"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.339768, 0.371181, 0.423827, 0.566242, 0.944885",\ + "0.353114, 0.384527, 0.437173, 0.579588, 0.958231",\ + "0.435092, 0.466504, 0.519150, 0.661565, 1.040208",\ + "0.544311, 0.575724, 0.628370, 0.770784, 1.149428",\ + "1.067931, 1.099343, 1.151989, 1.294404, 1.673047"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.524400, 0.555831, 0.608540, 0.750893, 1.129489",\ + "0.542749, 0.574181, 0.626889, 0.769242, 1.147839",\ + "0.616605, 0.648037, 0.700745, 0.843098, 1.221695",\ + "0.714865, 0.746296, 0.799004, 0.941357, 1.319954",\ + "1.237234, 1.268665, 1.321373, 1.463726, 1.842323"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.651244, 0.718149, 0.834587, 1.154256, 2.009460",\ + "0.663867, 0.730771, 0.847209, 1.166878, 2.022083",\ + "0.718781, 0.785685, 0.902124, 1.221793, 2.076997",\ + "0.821201, 0.888105, 1.004544, 1.324213, 2.179417",\ + "1.548479, 1.615391, 1.731835, 2.051504, 2.906700"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073043, 0.188945, 0.391861, 0.949146, 2.441348"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.267796, 0.299208, 0.351854, 0.494269, 0.872912",\ + "0.284541, 0.315954, 0.368600, 0.511015, 0.889658",\ + "0.362798, 0.394211, 0.446856, 0.589271, 0.967914",\ + "0.486677, 0.518090, 0.570736, 0.713151, 1.091794",\ + "1.055266, 1.086678, 1.139324, 1.281739, 1.660382"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.456335, 0.523226, 0.639653, 0.959321, 1.814541",\ + "0.469682, 0.536572, 0.652999, 0.972667, 1.827887",\ + "0.547821, 0.614711, 0.731138, 1.050806, 1.906026",\ + "0.649000, 0.715890, 0.832317, 1.151985, 2.007205",\ + "1.120855, 1.187745, 1.304172, 1.623840, 2.479060"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.712314, 0.779218, 0.895657, 1.215326, 2.070530",\ + "0.730867, 0.797771, 0.914210, 1.233879, 2.089083",\ + "0.803565, 0.870469, 0.986908, 1.306577, 2.161781",\ + "0.898790, 0.965694, 1.082133, 1.401802, 2.257006",\ + "1.358120, 1.425029, 1.541471, 1.861141, 2.716340"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.494441, 0.525873, 0.578581, 0.720934, 1.099531",\ + "0.511983, 0.543415, 0.596123, 0.738476, 1.117073",\ + "0.589312, 0.620744, 0.673452, 0.815805, 1.194402",\ + "0.698758, 0.730189, 0.782897, 0.925250, 1.303847",\ + "1.229663, 1.261095, 1.313803, 1.456156, 1.834753"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.668630, 0.735520, 0.851947, 1.171615, 2.026835",\ + "0.685451, 0.752341, 0.868768, 1.188436, 2.043656",\ + "0.759882, 0.826773, 0.943200, 1.262868, 2.118088",\ + "0.855138, 0.922028, 1.038455, 1.358123, 2.213343",\ + "1.307789, 1.374679, 1.491106, 1.810774, 2.665994"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.361699, 0.393111, 0.445757, 0.588172, 0.966815",\ + "0.375155, 0.406568, 0.459214, 0.601628, 0.980272",\ + "0.456576, 0.487988, 0.540634, 0.683049, 1.061692",\ + "0.566550, 0.597963, 0.650609, 0.793024, 1.171667",\ + "1.091986, 1.123399, 1.176044, 1.318459, 1.697102"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.528266, 0.559698, 0.612406, 0.754759, 1.133356",\ + "0.546819, 0.578250, 0.630959, 0.773312, 1.151908",\ + "0.620877, 0.652309, 0.705017, 0.847370, 1.225967",\ + "0.719978, 0.751410, 0.804118, 0.946471, 1.325068",\ + "1.192613, 1.224045, 1.276753, 1.419106, 1.797703"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090837",\ + "0.039143, 0.090610, 0.180695, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.606303, 0.673207, 0.789646, 1.109315, 1.964519",\ + "0.618992, 0.685897, 0.802335, 1.122004, 1.977208",\ + "0.673763, 0.740668, 0.857106, 1.176775, 2.031980",\ + "0.776802, 0.843707, 0.960145, 1.279814, 2.135018",\ + "1.483718, 1.550627, 1.667069, 1.986738, 2.841937"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073038, 0.188934, 0.391844, 0.949109, 2.441341",\ + "0.073041, 0.188941, 0.391855, 0.949133, 2.441345"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.262699, 0.294112, 0.346758, 0.489173, 0.867816",\ + "0.279513, 0.310926, 0.363572, 0.505987, 0.884630",\ + "0.357852, 0.389264, 0.441910, 0.584325, 0.962968",\ + "0.480383, 0.511796, 0.564441, 0.706856, 1.085500",\ + "1.037548, 1.068961, 1.121607, 1.264022, 1.642665"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687",\ + "0.039012, 0.090733, 0.180378, 0.429204, 1.091687"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.463612, 0.530502, 0.646929, 0.966597, 1.821817",\ + "0.477068, 0.543958, 0.660386, 0.980054, 1.835274",\ + "0.555357, 0.622247, 0.738674, 1.058342, 1.913562",\ + "0.655033, 0.721923, 0.838350, 1.158018, 2.013238",\ + "1.119877, 1.186768, 1.303195, 1.622863, 2.478083"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330",\ + "0.073032, 0.188916, 0.391816, 0.949015, 2.441330"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.123879, 0.190820, 0.307288, 0.626960, 1.482121",\ + "0.210891, 0.277978, 0.394567, 0.714249, 1.569235",\ + "0.301781, 0.369068, 0.485667, 0.805496, 1.660526",\ + "0.453978, 0.523120, 0.640034, 0.960158, 1.815427",\ + "0.695902, 0.774527, 0.893732, 1.214148, 2.069560"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188997, 0.391936, 0.949305, 2.441374",\ + "0.073175, 0.189249, 0.392304, 0.950092, 2.441498",\ + "0.074330, 0.189249, 0.392418, 0.950747, 2.441498",\ + "0.079436, 0.191164, 0.392505, 0.951076, 2.441498",\ + "0.098084, 0.204137, 0.393542, 0.951076, 2.441498"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114293, 0.145721, 0.198417, 0.340782, 0.719388",\ + "0.205394, 0.236828, 0.289545, 0.431889, 0.810480",\ + "0.309904, 0.342065, 0.394885, 0.537244, 0.915841",\ + "0.501618, 0.536979, 0.590065, 0.732680, 1.111452",\ + "0.825607, 0.870622, 0.930343, 1.075147, 1.454209"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039117, 0.090634, 0.180632, 0.429261, 1.091005",\ + "0.039161, 0.090634, 0.180739, 0.429285, 1.091005",\ + "0.041267, 0.091212, 0.180891, 0.429338, 1.091005",\ + "0.050293, 0.094364, 0.180891, 0.429357, 1.092061",\ + "0.068556, 0.114740, 0.192215, 0.429716, 1.093122"); + } + + } /* end of arc otm_obs_i[1]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.120559, 0.187489, 0.303948, 0.623619, 1.478793",\ + "0.205712, 0.272774, 0.389342, 0.709022, 1.564038",\ + "0.292652, 0.359907, 0.476516, 0.796311, 1.651312",\ + "0.437434, 0.505450, 0.622092, 0.942182, 1.797434",\ + "0.662107, 0.738115, 0.856688, 1.177023, 2.032395"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073057, 0.188977, 0.391908, 0.949245, 2.441364",\ + "0.073156, 0.189206, 0.392241, 0.949956, 2.441378",\ + "0.074065, 0.189247, 0.392382, 0.950255, 2.441378",\ + "0.077223, 0.189624, 0.392382, 0.950255, 2.441378",\ + "0.092938, 0.200557, 0.393255, 0.950255, 2.441468"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094368, 0.125782, 0.178430, 0.320842, 0.699483",\ + "0.188259, 0.219683, 0.272369, 0.414744, 0.793358",\ + "0.291365, 0.323244, 0.376040, 0.518376, 0.896959",\ + "0.474009, 0.509208, 0.562280, 0.704883, 1.083646",\ + "0.777508, 0.822171, 0.881623, 1.026340, 1.405392"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090654, 0.180392, 0.429207, 1.090346",\ + "0.039096, 0.090654, 0.180581, 0.429249, 1.090346",\ + "0.040472, 0.090934, 0.180608, 0.429337, 1.090346",\ + "0.049836, 0.094205, 0.180608, 0.429356, 1.091981",\ + "0.067933, 0.113945, 0.191732, 0.429701, 1.093101"); + } + + } /* end of arc otm_obs_i[1]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "otp_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[1]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[1]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[1]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380006.843750, 380006.906250, 380007.031250, 380007.343750, 380008.187500",\ + "380006.937500, 380007.000000, 380007.125000, 380007.437500, 380008.281250",\ + "380007.031250, 380007.093750, 380007.218750, 380007.531250, 380008.375000",\ + "380007.187500, 380007.250000, 380007.375000, 380007.687500, 380008.531250",\ + "380007.437500, 380007.500000, 380007.625000, 380007.937500, 380008.781250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380006.562500, 380006.593750, 380006.656250, 380006.812500, 380007.187500",\ + "380006.656250, 380006.687500, 380006.750000, 380006.906250, 380007.281250",\ + "380006.781250, 380006.812500, 380006.875000, 380007.031250, 380007.406250",\ + "380006.968750, 380007.000000, 380007.062500, 380007.218750, 380007.593750",\ + "380007.281250, 380007.312500, 380007.375000, 380007.531250, 380007.906250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380006.781250, 380006.843750, 380006.968750, 380007.281250, 380008.125000",\ + "380006.875000, 380006.937500, 380007.062500, 380007.375000, 380008.218750",\ + "380006.937500, 380007.000000, 380007.125000, 380007.437500, 380008.281250",\ + "380007.093750, 380007.156250, 380007.281250, 380007.593750, 380008.437500",\ + "380007.312500, 380007.375000, 380007.500000, 380007.812500, 380008.656250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380006.437500, 380006.468750, 380006.500000, 380006.656250, 380007.031250",\ + "380006.531250, 380006.562500, 380006.593750, 380006.750000, 380007.125000",\ + "380006.625000, 380006.656250, 380006.687500, 380006.843750, 380007.218750",\ + "380006.812500, 380006.843750, 380006.875000, 380007.031250, 380007.406250",\ + "380007.062500, 380007.093750, 380007.125000, 380007.281250, 380007.656250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970006.000000, 970006.062500, 970006.125000, 970006.250000, 970006.625000",\ + "970006.125000, 970006.187500, 970006.250000, 970006.375000, 970006.750000",\ + "970006.125000, 970006.187500, 970006.250000, 970006.375000, 970006.750000",\ + "970006.375000, 970006.437500, 970006.500000, 970006.625000, 970007.000000",\ + "970006.625000, 970006.687500, 970006.750000, 970006.875000, 970007.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "970008.625000, 970008.687500, 970008.812500, 970009.125000, 970010.000000",\ + "970008.750000, 970008.812500, 970008.937500, 970009.250000, 970010.125000",\ + "970008.875000, 970008.937500, 970009.062500, 970009.375000, 970010.250000",\ + "970009.125000, 970009.187500, 970009.312500, 970009.625000, 970010.500000",\ + "970009.375000, 970009.437500, 970009.562500, 970009.875000, 970010.750000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[1]_inv_min*/ + + timing () { + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590007.000000, 590007.062500, 590007.187500, 590007.500000, 590008.375000",\ + "590007.125000, 590007.187500, 590007.312500, 590007.625000, 590008.500000",\ + "590007.125000, 590007.187500, 590007.312500, 590007.625000, 590008.500000",\ + "590007.250000, 590007.312500, 590007.437500, 590007.750000, 590008.625000",\ + "590007.500000, 590007.562500, 590007.687500, 590008.000000, 590008.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526",\ + "0.073824, 0.189280, 0.392442, 0.950608, 2.441526"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590005.750000, 590005.812500, 590005.875000, 590006.000000, 590006.375000",\ + "590005.875000, 590005.937500, 590006.000000, 590006.125000, 590006.500000",\ + "590006.000000, 590006.062500, 590006.125000, 590006.250000, 590006.625000",\ + "590006.125000, 590006.187500, 590006.250000, 590006.375000, 590006.750000",\ + "590006.500000, 590006.562500, 590006.625000, 590006.750000, 590007.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497",\ + "0.041204, 0.091190, 0.180893, 0.429338, 1.092497"); + } + + } /* end of arc padmux2ast_i[5]_ast2padmux_o[1]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590006.875000, 590006.937500, 590007.062500, 590007.375000, 590008.187500",\ + "590006.875000, 590006.937500, 590007.062500, 590007.375000, 590008.187500",\ + "590007.000000, 590007.062500, 590007.187500, 590007.500000, 590008.312500",\ + "590007.125000, 590007.187500, 590007.312500, 590007.625000, 590008.437500",\ + "590007.375000, 590007.437500, 590007.562500, 590007.875000, 590008.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507",\ + "0.067834, 0.184682, 0.382509, 0.937727, 2.417507"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "590005.687500, 590005.687500, 590005.750000, 590005.875000, 590006.312500",\ + "590005.812500, 590005.812500, 590005.875000, 590006.000000, 590006.437500",\ + "590005.937500, 590005.937500, 590006.000000, 590006.125000, 590006.562500",\ + "590006.062500, 590006.062500, 590006.125000, 590006.250000, 590006.687500",\ + "590006.312500, 590006.312500, 590006.375000, 590006.500000, 590006.937500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\ + "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\ + "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\ + "0.039018, 0.090351, 0.180124, 0.429131, 1.091647",\ + "0.039018, 0.090351, 0.180124, 0.429131, 1.091647"); + } + + } /* end of arc padmux2ast_i[5]_ast2padmux_o[1]_una_min*/ + +} /* end of pin ast2padmux_o[1] */ + +pin("ast2padmux_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.028584 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2padmux_o[0]; + timing () { + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_val_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.265266, 0.537827, 0.806617, 1.252725, 2.144939",\ + "0.332206, 0.604767, 0.873561, 1.319677, 2.211910",\ + "0.448674, 0.721235, 0.990031, 1.436155, 2.328403",\ + "0.768345, 1.040907, 1.309703, 1.755827, 2.648076",\ + "1.623507, 1.896068, 2.164861, 2.610974, 3.503201",\ + "0.323816, 0.596337, 0.865402, 1.310432, 2.201046",\ + "0.390756, 0.663277, 0.932346, 1.377385, 2.268016",\ + "0.507224, 0.779745, 1.048816, 1.493863, 2.384509",\ + "0.826895, 1.099417, 1.368488, 1.813535, 2.704183",\ + "1.682057, 1.954579, 2.223646, 2.668682, 3.559309",\ + "0.467311, 0.742155, 1.009298, 1.454188, 2.344779",\ + "0.534251, 0.809095, 1.076241, 1.521140, 2.411749",\ + "0.650718, 0.925563, 1.192712, 1.637618, 2.528242",\ + "0.970390, 1.245234, 1.512384, 1.957291, 2.847916",\ + "1.825552, 2.100396, 2.367542, 2.812438, 3.703041",\ + "0.502881, 0.779924, 1.046217, 1.490979, 2.381337",\ + "0.569821, 0.846864, 1.113161, 1.557931, 2.448308",\ + "0.686289, 0.963332, 1.229631, 1.674409, 2.564800",\ + "1.005960, 1.283003, 1.549303, 1.994082, 2.884474",\ + "1.861122, 2.138165, 2.404461, 2.849229, 3.739599",\ + "0.827836, 1.143899, 1.397858, 1.840240, 2.726793",\ + "0.894775, 1.210839, 1.464802, 1.907193, 2.793763",\ + "1.011243, 1.327307, 1.581273, 2.023671, 2.910256",\ + "1.330914, 1.646978, 1.900944, 2.343343, 3.229930",\ + "2.186077, 2.502140, 2.756102, 3.198490, 4.085055"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\ + "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\ + "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\ + "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\ + "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\ + "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\ + "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\ + "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\ + "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\ + "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188995, 0.189001, 0.189016, 0.189048",\ + "0.391933, 0.391934, 0.391942, 0.391965, 0.392010",\ + "0.949299, 0.949301, 0.949318, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441384, 2.441401",\ + "0.073065, 0.073065, 0.073067, 0.073074, 0.073087",\ + "0.188995, 0.188996, 0.189001, 0.189017, 0.189048",\ + "0.391933, 0.391935, 0.391943, 0.391965, 0.392010",\ + "0.949299, 0.949302, 0.949319, 0.949367, 0.949463",\ + "2.441373, 2.441374, 2.441376, 2.441385, 2.441401"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.321682, 0.506101, 0.700572, 1.011955, 1.613898",\ + "0.353113, 0.537532, 0.732004, 1.043387, 1.645330",\ + "0.405822, 0.590241, 0.784712, 1.096096, 1.698039",\ + "0.548175, 0.732594, 0.927065, 1.238448, 1.840391",\ + "0.926771, 1.111190, 1.305661, 1.617045, 2.218987",\ + "0.381626, 0.565998, 0.760527, 1.071737, 1.673515",\ + "0.413058, 0.597430, 0.791958, 1.103168, 1.704947",\ + "0.465766, 0.650139, 0.844667, 1.155877, 1.757656",\ + "0.608119, 0.792491, 0.987020, 1.298229, 1.900008",\ + "0.986715, 1.171088, 1.365616, 1.676826, 2.278605",\ + "0.514234, 0.698252, 0.892410, 1.203594, 1.805323",\ + "0.545665, 0.729684, 0.923841, 1.235026, 1.836754",\ + "0.598374, 0.782393, 0.976550, 1.287735, 1.889464",\ + "0.740726, 0.924745, 1.118903, 1.430087, 2.031816",\ + "1.119323, 1.303342, 1.497499, 1.808684, 2.410412",\ + "0.547325, 0.731379, 0.925535, 1.236547, 1.837931",\ + "0.578757, 0.762811, 0.956967, 1.267979, 1.869363",\ + "0.631466, 0.815519, 1.009675, 1.320688, 1.922072",\ + "0.773818, 0.957872, 1.152028, 1.463040, 2.064424",\ + "1.152415, 1.336468, 1.530624, 1.841637, 2.443020",\ + "0.847275, 1.036618, 1.229172, 1.539564, 2.139780",\ + "0.878707, 1.068050, 1.260603, 1.570995, 2.171212",\ + "0.931415, 1.120758, 1.313312, 1.623704, 2.223921",\ + "1.073768, 1.263111, 1.455664, 1.766057, 2.366273",\ + "1.452364, 1.641707, 1.834261, 2.144653, 2.744869"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\ + "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\ + "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\ + "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832",\ + "0.039144, 0.039144, 0.039144, 0.039144, 0.039145",\ + "0.090609, 0.090609, 0.090609, 0.090609, 0.090609",\ + "0.180697, 0.180697, 0.180697, 0.180698, 0.180700",\ + "0.429275, 0.429275, 0.429275, 0.429276, 0.429276",\ + "1.090832, 1.090832, 1.090832, 1.090832, 1.090832"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_rng_i" ; + related_output_pin : "rng_val_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.258488, 0.527564, 0.791863, 1.230215, 2.105847",\ + "0.325417, 0.594493, 0.858794, 1.297152, 2.172797",\ + "0.441875, 0.710952, 0.975255, 1.413618, 2.289272",\ + "0.761546, 1.030622, 1.294926, 1.733289, 2.608944",\ + "1.616721, 1.885797, 2.150098, 2.588454, 3.464095",\ + "0.317013, 0.586065, 0.850631, 1.287923, 2.161954",\ + "0.383942, 0.652994, 0.917562, 1.354860, 2.228903",\ + "0.500401, 0.769453, 1.034023, 1.471326, 2.345379",\ + "0.820072, 1.089123, 1.353694, 1.790997, 2.665051",\ + "1.675247, 1.944298, 2.208866, 2.646162, 3.520202",\ + "0.460262, 0.731823, 0.994519, 1.431727, 2.305687",\ + "0.527191, 0.798752, 1.061450, 1.498664, 2.372636",\ + "0.643650, 0.915210, 1.177911, 1.615129, 2.489112",\ + "0.963321, 1.234881, 1.497581, 1.934801, 2.808784",\ + "1.818496, 2.090056, 2.352754, 2.789966, 3.663935",\ + "0.495756, 0.769563, 1.031437, 1.468598, 2.342245",\ + "0.562684, 0.836492, 1.098369, 1.535535, 2.409194",\ + "0.679143, 0.952951, 1.214829, 1.652000, 2.525670",\ + "0.998814, 1.272622, 1.534500, 1.971672, 2.845342",\ + "1.853989, 2.127797, 2.389672, 2.826837, 3.700493",\ + "0.819862, 1.132963, 1.383002, 1.817902, 2.687701",\ + "0.886791, 1.199892, 1.449933, 1.884839, 2.754651",\ + "1.003250, 1.316351, 1.566393, 2.001304, 2.871126",\ + "1.322921, 1.636022, 1.886065, 2.320976, 3.190798",\ + "2.178096, 2.491197, 2.741237, 3.176141, 4.045949"); + } + rise_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949284, 0.949349",\ + "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\ + "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949284, 0.949349",\ + "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\ + "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949284, 0.949349",\ + "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\ + "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391911, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949285, 0.949349",\ + "2.441363, 2.441363, 2.441365, 2.441371, 2.441381",\ + "0.073056, 0.073057, 0.073058, 0.073063, 0.073072",\ + "0.188976, 0.188976, 0.188980, 0.188990, 0.189011",\ + "0.391905, 0.391906, 0.391912, 0.391927, 0.391957",\ + "0.949239, 0.949241, 0.949252, 0.949285, 0.949349",\ + "2.441363, 2.441364, 2.441365, 2.441371, 2.441381"); + } + cell_fall( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.280172, 0.467016, 0.660531, 0.967486, 1.558860",\ + "0.311589, 0.498432, 0.691948, 0.998903, 1.590277",\ + "0.364248, 0.551092, 0.744607, 1.051563, 1.642938",\ + "0.506650, 0.693493, 0.887008, 1.193964, 1.785338",\ + "0.885283, 1.072126, 1.265642, 1.572596, 2.163970",\ + "0.340116, 0.526843, 0.720376, 1.027255, 1.618477",\ + "0.371533, 0.558260, 0.751792, 1.058672, 1.649894",\ + "0.424192, 0.610919, 0.804452, 1.111332, 1.702555",\ + "0.566594, 0.753321, 0.946853, 1.253732, 1.844955",\ + "0.945227, 1.131954, 1.325486, 1.632365, 2.223587",\ + "0.472755, 0.659097, 0.852258, 1.159112, 1.750284",\ + "0.504172, 0.690514, 0.883675, 1.190529, 1.781701",\ + "0.556831, 0.743173, 0.936334, 1.243189, 1.834362",\ + "0.699233, 0.885575, 1.078736, 1.385590, 1.976762",\ + "1.077866, 1.264208, 1.457369, 1.764223, 2.355394",\ + "0.505869, 0.692396, 0.885489, 1.192192, 1.783144",\ + "0.537286, 0.723812, 0.916906, 1.223609, 1.814562",\ + "0.589945, 0.776472, 0.969565, 1.276269, 1.867223",\ + "0.732346, 0.918873, 1.111966, 1.418670, 2.009622",\ + "1.110980, 1.297506, 1.490599, 1.797303, 2.388254",\ + "0.806127, 0.997856, 1.189152, 1.495396, 2.085451",\ + "0.837544, 1.029273, 1.220569, 1.526813, 2.116868",\ + "0.890203, 1.081932, 1.273229, 1.579473, 2.169529",\ + "1.032604, 1.224334, 1.415630, 1.721874, 2.311929",\ + "1.411238, 1.602967, 1.794263, 2.100507, 2.690561"); + } + fall_transition( f_itrans_ocap_rcap ){ + index_1 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + index_3 ( "0.000506, 0.073504, 0.160882, 0.321258, 0.642011"); + values ( "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\ + "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\ + "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\ + "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090707, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479",\ + "0.039040, 0.039040, 0.039040, 0.039042, 0.039044",\ + "0.090706, 0.090706, 0.090706, 0.090705, 0.090703",\ + "0.180446, 0.180446, 0.180447, 0.180449, 0.180455",\ + "0.429219, 0.429219, 0.429219, 0.429220, 0.429221",\ + "1.091504, 1.091503, 1.091503, 1.091496, 1.091479"); + } + + } /* end of arc clk_ast_rng_i_ast2padmux_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380001.968750, 380002.031250, 380002.156250, 380002.468750, 380003.343750",\ + "380002.062500, 380002.125000, 380002.250000, 380002.562500, 380003.437500",\ + "380002.125000, 380002.187500, 380002.312500, 380002.625000, 380003.500000",\ + "380002.468750, 380002.531250, 380002.656250, 380002.968750, 380003.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189354, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189354, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189365, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189385, 0.392560, 0.950561, 2.441537",\ + "0.073650, 0.189425, 0.393252, 0.950561, 2.441537"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.437500, 380000.437500, 380000.468750, 380000.531250, 380000.718750",\ + "380000.531250, 380000.531250, 380000.562500, 380000.625000, 380000.812500",\ + "380000.593750, 380000.593750, 380000.625000, 380000.687500, 380000.875000",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.968750, 380000.968750, 380001.000000, 380001.062500, 380001.250000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.118063, 0.173160, 0.267375, 0.527316, 1.216798",\ + "0.205470, 0.260567, 0.354781, 0.614720, 1.304204",\ + "0.286205, 0.341346, 0.435579, 0.695608, 1.384949",\ + "0.343571, 0.398793, 0.493060, 0.753254, 1.442331",\ + "0.643636, 0.699058, 0.793671, 1.054205, 1.742813"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055140, 0.149920, 0.315966, 0.770671, 1.992169",\ + "0.055064, 0.149920, 0.315966, 0.770616, 1.992169",\ + "0.054924, 0.149920, 0.315966, 0.770514, 1.992169",\ + "0.054820, 0.149920, 0.315966, 0.770514, 1.988361"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.068977, 0.083624, 0.108789, 0.177707, 0.362145",\ + "0.157440, 0.172093, 0.197279, 0.266195, 0.450612",\ + "0.246166, 0.261189, 0.286407, 0.355291, 0.539679",\ + "0.308361, 0.324424, 0.349591, 0.418444, 0.602842",\ + "0.630702, 0.654723, 0.683267, 0.752219, 0.936438"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015416, 0.041075, 0.085652, 0.207740, 0.535967",\ + "0.015763, 0.041089, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + + } /* end of arc clk_ast_tlul_i_ast2padmux_o[0]_redg_min*/ + + timing () { + related_pin : "fla_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111862, 0.178517, 0.294685, 0.611498, 1.461412",\ + "0.196887, 0.263820, 0.381200, 0.697836, 1.546758",\ + "0.280874, 0.348002, 0.465333, 0.783744, 1.631498",\ + "0.419192, 0.490016, 0.607541, 0.927454, 1.774732",\ + "0.629434, 0.713469, 0.835221, 1.155234, 2.004311"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067759, 0.184639, 0.382501, 0.937507, 2.417566",\ + "0.067759, 0.184639, 0.382501, 0.937507, 2.418347",\ + "0.069174, 0.184639, 0.382586, 0.937507, 2.418347",\ + "0.077831, 0.187460, 0.383300, 0.940319, 2.418347",\ + "0.099054, 0.205738, 0.390315, 0.940320, 2.425200"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.103322, 0.134506, 0.187130, 0.329612, 0.708263",\ + "0.188196, 0.219801, 0.272413, 0.414932, 0.793505",\ + "0.281500, 0.317246, 0.369943, 0.512302, 0.890520",\ + "0.433568, 0.478875, 0.537406, 0.680993, 1.058708",\ + "0.668936, 0.733428, 0.809479, 0.962224, 1.340585"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040521, 0.090274, 0.180244, 0.428614, 1.092440",\ + "0.042863, 0.090977, 0.180401, 0.428614, 1.092696",\ + "0.054661, 0.097371, 0.180899, 0.428690, 1.092793",\ + "0.077190, 0.120374, 0.194930, 0.430280, 1.092793",\ + "0.118581, 0.174509, 0.240947, 0.445113, 1.092793"); + } + + } /* end of arc fla_obs_i[0]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "fla_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.110629, 0.177262, 0.293339, 0.610165, 1.460154",\ + "0.194795, 0.261696, 0.378936, 0.695592, 1.544629",\ + "0.275980, 0.343081, 0.460479, 0.778514, 1.626463",\ + "0.408884, 0.478137, 0.595421, 0.915532, 1.762573",\ + "0.610985, 0.691263, 0.810230, 1.128954, 1.977655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.067834, 0.183634, 0.382402, 0.934951, 2.414331",\ + "0.068631, 0.183634, 0.382540, 0.936478, 2.414331",\ + "0.075251, 0.185541, 0.383090, 0.939701, 2.414331",\ + "0.093347, 0.198994, 0.384563, 0.939701, 2.425563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077370, 0.108647, 0.161299, 0.303710, 0.682406",\ + "0.166391, 0.197521, 0.250129, 0.392651, 0.771277",\ + "0.253394, 0.288299, 0.340979, 0.483371, 0.861661",\ + "0.395347, 0.439383, 0.496795, 0.640121, 1.017884",\ + "0.615736, 0.679130, 0.754042, 0.905113, 1.283136"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039363, 0.090228, 0.180124, 0.428312, 1.092155",\ + "0.041196, 0.090228, 0.180315, 0.428312, 1.092511",\ + "0.052267, 0.096073, 0.180798, 0.428601, 1.092511",\ + "0.074482, 0.116813, 0.192279, 0.430033, 1.092511",\ + "0.116096, 0.171326, 0.236992, 0.441817, 1.092511"); + } + + } /* end of arc fla_obs_i[0]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.454321, 0.521261, 0.637729, 0.957401, 1.812562",\ + "0.476584, 0.543525, 0.659993, 0.979665, 1.834826",\ + "0.532978, 0.599918, 0.716386, 1.036058, 1.891219",\ + "0.630840, 0.697781, 0.814249, 1.133921, 1.989082",\ + "1.144998, 1.211940, 1.328409, 1.648081, 2.503240"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073066, 0.188998, 0.391939, 0.949310, 2.441375"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.506462, 0.537893, 0.590602, 0.732954, 1.111551",\ + "0.527996, 0.559427, 0.612136, 0.754488, 1.133085",\ + "0.595181, 0.626613, 0.679322, 0.821674, 1.200271",\ + "0.705480, 0.736911, 0.789620, 0.931973, 1.310569",\ + "1.265269, 1.296700, 1.349409, 1.491761, 1.870358"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.421371, 0.488300, 0.604758, 0.924429, 1.779604",\ + "0.442149, 0.509077, 0.625536, 0.945207, 1.800382",\ + "0.499740, 0.566669, 0.683127, 1.002798, 1.857973",\ + "0.597685, 0.664614, 0.781072, 1.100743, 1.955918",\ + "1.086534, 1.153463, 1.269921, 1.589592, 2.444767"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.412434, 0.443851, 0.496510, 0.638912, 1.017545",\ + "0.429840, 0.461257, 0.513916, 0.656317, 1.034951",\ + "0.502410, 0.533827, 0.586486, 0.728887, 1.107521",\ + "0.615047, 0.646463, 0.699123, 0.841524, 1.220157",\ + "1.142076, 1.173492, 1.226152, 1.368553, 1.747186"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.453258, 0.484690, 0.537398, 0.679751, 1.058348",\ + "0.478327, 0.509759, 0.562468, 0.704820, 1.083417",\ + "0.547548, 0.578980, 0.631688, 0.774041, 1.152637",\ + "0.671779, 0.703211, 0.755919, 0.898272, 1.276869",\ + "1.305416, 1.336847, 1.389556, 1.531909, 1.910505"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.059999, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.686438, 0.753379, 0.869847, 1.189519, 2.044680",\ + "0.706913, 0.773853, 0.890321, 1.209993, 2.065154",\ + "0.765773, 0.832713, 0.949182, 1.268853, 2.124014",\ + "0.875012, 0.941953, 1.058421, 1.378093, 2.233254",\ + "1.652212, 1.719154, 1.835623, 2.155295, 3.010454"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.053775, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073066, 0.188998, 0.391939, 0.949310, 2.441375"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[10]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.282064, 0.313481, 0.366140, 0.508541, 0.887175",\ + "0.305674, 0.337091, 0.389750, 0.532151, 0.910785",\ + "0.377014, 0.408430, 0.461090, 0.603491, 0.982124",\ + "0.496822, 0.528239, 0.580898, 0.723300, 1.101933",\ + "1.041943, 1.073360, 1.126019, 1.268421, 1.647054"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.056753, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.590884, 0.657812, 0.774271, 1.093942, 1.949117",\ + "0.607576, 0.674504, 0.790963, 1.110634, 1.965809",\ + "0.669970, 0.736899, 0.853357, 1.173028, 2.028203",\ + "0.779360, 0.846288, 0.962747, 1.282418, 2.137593",\ + "1.516501, 1.583430, 1.699888, 2.019559, 2.874734"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044579, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + + } /* end of arc obs_ctrl_o[10]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.197401, 0.228828, 0.281523, 0.423889, 0.802496",\ + "0.210783, 0.242210, 0.294905, 0.437272, 0.815878",\ + "0.293723, 0.325151, 0.377848, 0.520213, 0.898818",\ + "0.418374, 0.449806, 0.502515, 0.644867, 1.023463",\ + "1.005445, 1.038016, 1.090870, 1.233261, 1.611881"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.034927, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039115, 0.090636, 0.180627, 0.429260, 1.091020",\ + "0.039115, 0.090636, 0.180627, 0.429260, 1.091020",\ + "0.039119, 0.090636, 0.180636, 0.429262, 1.091020",\ + "0.039145, 0.090636, 0.180699, 0.429276, 1.091020",\ + "0.042423, 0.091616, 0.180853, 0.429341, 1.091020"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.483196, 0.550400, 0.667026, 0.986767, 1.841721",\ + "0.495454, 0.562658, 0.679284, 0.999025, 1.853979",\ + "0.559644, 0.626847, 0.743473, 1.063213, 1.918167",\ + "0.662607, 0.729816, 0.846440, 1.166186, 2.021145",\ + "1.344671, 1.412041, 1.528612, 1.848528, 2.703634"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037147, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073644, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073644, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073644, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073683, 0.189305, 0.392450, 0.950570, 2.441537",\ + "0.075005, 0.189305, 0.392450, 0.950931, 2.441537"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[11]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.178015, 0.209429, 0.262079, 0.404490, 0.783130",\ + "0.189390, 0.220804, 0.273454, 0.415865, 0.794505",\ + "0.274579, 0.305993, 0.358646, 0.501054, 0.879692",\ + "0.400471, 0.431892, 0.484565, 0.626953, 1.005576",\ + "0.985792, 1.018105, 1.070937, 1.213308, 1.591914"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.030664, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090679, 0.180398, 0.429208, 1.090559",\ + "0.039020, 0.090679, 0.180398, 0.429208, 1.090559",\ + "0.039027, 0.090679, 0.180413, 0.429212, 1.090559",\ + "0.039069, 0.090679, 0.180517, 0.429235, 1.090559",\ + "0.041694, 0.091361, 0.180877, 0.429339, 1.090559"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.476048, 0.543228, 0.659862, 0.979577, 1.834510",\ + "0.484692, 0.551872, 0.668506, 0.988221, 1.843154",\ + "0.552511, 0.619690, 0.736325, 1.056039, 1.910971",\ + "0.655347, 0.722531, 0.839164, 1.158884, 2.013820",\ + "1.333397, 1.400722, 1.517308, 1.837177, 2.692242"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.028580, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073446, 0.189167, 0.392403, 0.950504, 2.441474",\ + "0.073446, 0.189167, 0.392403, 0.950504, 2.441474",\ + "0.073446, 0.189167, 0.392403, 0.950504, 2.441474",\ + "0.073481, 0.189167, 0.392403, 0.950515, 2.441474",\ + "0.074640, 0.189167, 0.392403, 0.950831, 2.441474"); + } + + } /* end of arc obs_ctrl_o[11]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.518600, 0.585804, 0.702430, 1.022170, 1.877124",\ + "0.534366, 0.601569, 0.718195, 1.037936, 1.892890",\ + "0.608476, 0.675680, 0.792306, 1.112046, 1.967001",\ + "0.699697, 0.766901, 0.883527, 1.203267, 2.058222",\ + "1.126490, 1.193697, 1.310322, 1.630066, 2.485023"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073643, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073671, 0.189301, 0.392449, 0.950567, 2.441536"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.275118, 0.306284, 0.358903, 0.501398, 0.880041",\ + "0.290749, 0.321915, 0.374533, 0.517029, 0.895671",\ + "0.363703, 0.394869, 0.447488, 0.589983, 0.968626",\ + "0.474794, 0.505959, 0.558577, 0.701073, 1.079716",\ + "1.013269, 1.044421, 1.097036, 1.239541, 1.618177"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040759, 0.090635, 0.180631, 0.429261, 1.092499",\ + "0.040922, 0.090603, 0.180713, 0.429279, 1.092539"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337608, 0.404302, 0.520641, 0.837429, 1.687203",\ + "0.349939, 0.416633, 0.532972, 0.849760, 1.699534",\ + "0.408752, 0.475446, 0.591785, 0.908573, 1.758347",\ + "0.496083, 0.562777, 0.679117, 0.995905, 1.845678",\ + "0.949078, 1.015776, 1.132136, 1.448920, 2.298678"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.228794, 0.260208, 0.312858, 0.455269, 0.833909",\ + "0.240665, 0.272079, 0.324729, 0.467140, 0.845780",\ + "0.323160, 0.354574, 0.407224, 0.549635, 0.928275",\ + "0.428120, 0.459534, 0.512186, 0.654595, 1.033234",\ + "0.930331, 0.961753, 1.014431, 1.156814, 1.535434"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039024, 0.090327, 0.180161, 0.428971, 1.091612",\ + "0.039078, 0.090324, 0.180166, 0.428948, 1.091257"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287803, 0.318969, 0.371587, 0.514083, 0.892726",\ + "0.303569, 0.334734, 0.387353, 0.529848, 0.908491",\ + "0.378810, 0.409975, 0.462594, 0.605089, 0.983732",\ + "0.473884, 0.505049, 0.557668, 0.700163, 1.078806",\ + "0.918190, 0.949342, 1.001956, 1.144462, 1.523098"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040034, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090637, 0.180627, 0.429260, 1.092497",\ + "0.040759, 0.090635, 0.180631, 0.429261, 1.092499",\ + "0.040922, 0.090603, 0.180713, 0.429279, 1.092539"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.376755, 0.443500, 0.560063, 0.876818, 1.726409",\ + "0.392417, 0.459162, 0.575725, 0.892480, 1.742071",\ + "0.467424, 0.534169, 0.650732, 0.967487, 1.817078",\ + "0.562603, 0.629351, 0.745928, 1.062681, 1.912261",\ + "1.006927, 1.073706, 1.190415, 1.507149, 2.356620"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040698, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073643, 0.189305, 0.392450, 0.950559, 2.441537",\ + "0.073671, 0.189301, 0.392449, 0.950567, 2.441536"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.264318, 0.295567, 0.348210, 0.490643, 0.869326",\ + "0.278489, 0.309737, 0.362381, 0.504814, 0.883496",\ + "0.355325, 0.386573, 0.439217, 0.581649, 0.960332",\ + "0.450369, 0.481617, 0.534260, 0.676693, 1.055376",\ + "0.893831, 0.925076, 0.977718, 1.120154, 1.498834"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036484, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039024, 0.090327, 0.180161, 0.428971, 1.091612",\ + "0.039078, 0.090324, 0.180166, 0.428948, 1.091257"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.373701, 0.440395, 0.556734, 0.873522, 1.723296",\ + "0.385572, 0.452266, 0.568605, 0.885393, 1.735167",\ + "0.464371, 0.531065, 0.647404, 0.964192, 1.813966",\ + "0.559385, 0.626079, 0.742420, 1.059207, 1.908981",\ + "1.002245, 1.068944, 1.185303, 1.502088, 2.351846"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032503, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184561, 0.382485, 0.937100, 2.417676",\ + "0.067620, 0.184560, 0.382485, 0.937098, 2.417677",\ + "0.067604, 0.184551, 0.382483, 0.937052, 2.417689"); + } + + } /* end of arc obs_ctrl_o[4]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.337998, 0.404744, 0.521308, 0.838063, 1.687653",\ + "0.353177, 0.419923, 0.536487, 0.853242, 1.702832",\ + "0.412195, 0.478941, 0.595505, 0.912260, 1.761850",\ + "0.508449, 0.575199, 0.691783, 1.008535, 1.858109",\ + "0.997007, 1.063817, 1.180658, 1.497372, 2.346736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\ + "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441538",\ + "0.073704, 0.189296, 0.392447, 0.950576, 2.441534",\ + "0.075364, 0.189067, 0.392369, 0.951029, 2.441428"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.272032, 0.303198, 0.355817, 0.498312, 0.876955",\ + "0.289891, 0.321056, 0.373675, 0.516170, 0.894813",\ + "0.360955, 0.392121, 0.444739, 0.587235, 0.965878",\ + "0.471378, 0.502542, 0.555160, 0.697656, 1.076298",\ + "1.004117, 1.035227, 1.087829, 1.230366, 1.608983"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090636, 0.180636, 0.429262, 1.092497",\ + "0.040771, 0.090636, 0.180700, 0.429276, 1.092502",\ + "0.042582, 0.091671, 0.180848, 0.429341, 1.092666"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.329221, 0.395915, 0.512254, 0.829041, 1.678816",\ + "0.344592, 0.411286, 0.527624, 0.844412, 1.694187",\ + "0.406780, 0.473474, 0.589813, 0.906601, 1.756375",\ + "0.502234, 0.568932, 0.685288, 1.002073, 1.851833",\ + "0.957622, 1.024367, 1.140929, 1.457685, 2.307276"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.231492, 0.262740, 0.315383, 0.457816, 0.836499",\ + "0.245351, 0.276600, 0.329243, 0.471676, 0.850359",\ + "0.320124, 0.351372, 0.404016, 0.546449, 0.925131",\ + "0.430166, 0.461410, 0.514053, 0.656489, 1.035169",\ + "0.955028, 0.986237, 1.038869, 1.181331, 1.559995"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091594",\ + "0.039070, 0.090324, 0.180167, 0.428947, 1.091311",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.090589"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.194141, 0.225569, 0.278263, 0.420630, 0.799236",\ + "0.213398, 0.244825, 0.297520, 0.439886, 0.818493",\ + "0.291110, 0.322538, 0.375235, 0.517599, 0.896205",\ + "0.414666, 0.446098, 0.498807, 0.641159, 1.019755",\ + "0.992685, 1.025312, 1.078170, 1.220567, 1.599190"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.047100, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090636, 0.180627, 0.429260, 1.092497",\ + "0.040752, 0.090636, 0.180636, 0.429262, 1.092497",\ + "0.040771, 0.090636, 0.180700, 0.429276, 1.092502",\ + "0.042582, 0.091671, 0.180848, 0.429341, 1.092666"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.473555, 0.540758, 0.657385, 0.977125, 1.832079",\ + "0.486694, 0.553897, 0.670524, 0.990264, 1.845218",\ + "0.549031, 0.616234, 0.732861, 1.052601, 1.907555",\ + "0.658256, 0.725467, 0.842091, 1.161839, 2.016800",\ + "1.359176, 1.426589, 1.543146, 1.863108, 2.718254"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045359, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\ + "0.073639, 0.189305, 0.392450, 0.950558, 2.441538",\ + "0.073641, 0.189305, 0.392450, 0.950559, 2.441538",\ + "0.073704, 0.189296, 0.392447, 0.950576, 2.441534",\ + "0.075364, 0.189067, 0.392369, 0.951029, 2.441428"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[5]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.174738, 0.206152, 0.258801, 0.401212, 0.779853",\ + "0.192387, 0.223801, 0.276451, 0.418861, 0.797502",\ + "0.271960, 0.303374, 0.356027, 0.498435, 0.877073",\ + "0.396781, 0.428202, 0.480875, 0.623262, 1.001885",\ + "0.972879, 1.005251, 1.058088, 1.200464, 1.579073"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.043742, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039026, 0.090327, 0.180161, 0.428971, 1.091594",\ + "0.039070, 0.090324, 0.180167, 0.428947, 1.091311",\ + "0.040211, 0.090294, 0.180212, 0.428752, 1.090589"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.466421, 0.533601, 0.650235, 0.969950, 1.824882",\ + "0.476202, 0.543381, 0.660016, 0.979730, 1.834662",\ + "0.541892, 0.609071, 0.725705, 1.045420, 1.900352",\ + "0.650936, 0.718122, 0.834754, 1.154476, 2.009415",\ + "1.346760, 1.414122, 1.530696, 1.850604, 2.705703"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.037000, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067621, 0.184561, 0.382485, 0.937101, 2.417676",\ + "0.067607, 0.184553, 0.382483, 0.937060, 2.417687",\ + "0.067439, 0.184458, 0.382464, 0.936568, 2.417820"); + } + + } /* end of arc obs_ctrl_o[5]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.313610, 0.380815, 0.497441, 0.817182, 1.672137",\ + "0.329358, 0.396562, 0.513188, 0.832930, 1.687885",\ + "0.393235, 0.460439, 0.577065, 0.896806, 1.751761",\ + "0.471556, 0.538760, 0.655386, 0.975126, 1.830081",\ + "0.862244, 0.929448, 1.046074, 1.365815, 2.220770"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.191794, 0.223225, 0.275933, 0.418286, 0.796883",\ + "0.207675, 0.239106, 0.291815, 0.434167, 0.812764",\ + "0.277023, 0.308454, 0.361162, 0.503515, 0.882112",\ + "0.365690, 0.397121, 0.449830, 0.592182, 0.970779",\ + "0.790485, 0.821927, 0.874671, 1.016989, 1.395559"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040785, 0.090539, 0.180878, 0.429316, 1.092505"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.289937, 0.356887, 0.473363, 0.793036, 1.648185",\ + "0.304047, 0.370997, 0.487474, 0.807146, 1.662295",\ + "0.369617, 0.436567, 0.553044, 0.872716, 1.727865",\ + "0.448151, 0.515103, 0.631581, 0.951254, 1.806401",\ + "0.842717, 0.909715, 1.026232, 1.345907, 2.200999"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.167066, 0.198479, 0.251128, 0.393540, 0.772181",\ + "0.179068, 0.210482, 0.263130, 0.405543, 0.784184",\ + "0.252467, 0.283881, 0.336530, 0.478942, 0.857582",\ + "0.341502, 0.372916, 0.425566, 0.567976, 0.946617",\ + "0.759790, 0.791205, 0.843857, 0.986265, 1.364904"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\ + "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\ + "0.039019, 0.090327, 0.180161, 0.428971, 1.091642",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039025, 0.090322, 0.180169, 0.428938, 1.091600"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.314064, 0.345229, 0.397848, 0.540343, 0.918986",\ + "0.329859, 0.361025, 0.413644, 0.556139, 0.934782",\ + "0.407724, 0.438890, 0.491508, 0.634004, 1.012646",\ + "0.508778, 0.539944, 0.592562, 0.735058, 1.113701",\ + "0.984655, 1.015818, 1.068436, 1.210933, 1.589574"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040785, 0.090539, 0.180878, 0.429316, 1.092505"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.614118, 0.681322, 0.797948, 1.117689, 1.972644",\ + "0.626922, 0.694126, 0.810752, 1.130493, 1.985448",\ + "0.694897, 0.762101, 0.878727, 1.198468, 2.053423",\ + "0.806557, 0.873761, 0.990387, 1.310127, 2.165082",\ + "1.291436, 1.358640, 1.475266, 1.795007, 2.649961"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040587, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[6]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.270718, 0.301966, 0.354610, 0.497042, 0.875725",\ + "0.284868, 0.316117, 0.368760, 0.511193, 0.889875",\ + "0.364362, 0.395610, 0.448254, 0.590687, 0.969369",\ + "0.465503, 0.496751, 0.549395, 0.691827, 1.070510",\ + "0.941451, 0.972693, 1.025335, 1.167772, 1.546452"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.036606, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\ + "0.039018, 0.090327, 0.180161, 0.428971, 1.091651",\ + "0.039019, 0.090327, 0.180161, 0.428971, 1.091642",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039025, 0.090322, 0.180169, 0.428938, 1.091600"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.437011, 0.503705, 0.620045, 0.936832, 1.786606",\ + "0.446608, 0.513302, 0.629642, 0.946429, 1.796203",\ + "0.517780, 0.584475, 0.700814, 1.017602, 1.867376",\ + "0.629396, 0.696091, 0.812430, 1.129218, 1.978992",\ + "1.131911, 1.198614, 1.314996, 1.631778, 2.481517"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.032396, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067586, 0.184541, 0.382481, 0.936998, 2.417704"); + } + + } /* end of arc obs_ctrl_o[6]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.315427, 0.346593, 0.399212, 0.541707, 0.920350",\ + "0.342146, 0.373312, 0.425930, 0.568426, 0.947068",\ + "0.410184, 0.441350, 0.493968, 0.636464, 1.015106",\ + "0.512927, 0.544093, 0.596711, 0.739207, 1.117850",\ + "1.020553, 1.055041, 1.108054, 1.250599, 1.629324"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.060518, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180695, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180696, 0.429275, 1.092497",\ + "0.040752, 0.090610, 0.180832, 0.429306, 1.092497",\ + "0.047830, 0.093504, 0.180832, 0.429352, 1.092504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.615123, 0.682328, 0.798954, 1.118695, 1.973650",\ + "0.635870, 0.703074, 0.819700, 1.139442, 1.994397",\ + "0.701192, 0.768396, 0.885022, 1.204764, 2.059719",\ + "0.815370, 0.882574, 0.999200, 1.318941, 2.173895",\ + "1.395166, 1.462382, 1.579004, 1.898758, 2.753724"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.051005, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189305, 0.392450, 0.950561, 2.441537",\ + "0.073748, 0.189305, 0.392450, 0.950588, 2.441537"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[7]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.132284, 0.163698, 0.216345, 0.358758, 0.737400",\ + "0.152768, 0.184181, 0.236829, 0.379242, 0.757883",\ + "0.226947, 0.258361, 0.311010, 0.453421, 0.832062",\ + "0.328095, 0.359509, 0.412158, 0.554569, 0.933209",\ + "0.769672, 0.801087, 0.853739, 0.996148, 1.374786"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.049671, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039016, 0.090327, 0.180161, 0.428971, 1.091660",\ + "0.039016, 0.090327, 0.180161, 0.428971, 1.091660",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039020, 0.090327, 0.180161, 0.428971, 1.091633",\ + "0.039025, 0.090323, 0.180168, 0.428941, 1.091602"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.268552, 0.335503, 0.451979, 0.771651, 1.626801",\ + "0.284564, 0.351514, 0.467990, 0.787663, 1.642812",\ + "0.357242, 0.424196, 0.540676, 0.860348, 1.715493",\ + "0.477594, 0.544576, 0.661079, 0.980754, 1.835865",\ + "1.125477, 1.192657, 1.309291, 1.629006, 2.483939"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.040467, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067620, 0.184560, 0.382485, 0.937099, 2.417677",\ + "0.067601, 0.184550, 0.382483, 0.937044, 2.417691"); + } + + } /* end of arc obs_ctrl_o[7]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.711181, 0.778121, 0.894590, 1.214261, 2.069422",\ + "0.729530, 0.796471, 0.912939, 1.232611, 2.087772",\ + "0.800074, 0.867014, 0.983483, 1.303154, 2.158315",\ + "0.892545, 0.959485, 1.075954, 1.395625, 2.250786",\ + "1.377232, 1.444175, 1.560645, 1.880316, 2.735475"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073067, 0.188999, 0.391940, 0.949314, 2.441375"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.503942, 0.535373, 0.588082, 0.730435, 1.109031",\ + "0.521369, 0.552801, 0.605509, 0.747862, 1.126459",\ + "0.598766, 0.630198, 0.682907, 0.825259, 1.203856",\ + "0.707080, 0.738512, 0.791220, 0.933573, 1.312169",\ + "1.259288, 1.290720, 1.343428, 1.485781, 1.864378"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.645044, 0.711973, 0.828431, 1.148102, 2.003277",\ + "0.661659, 0.728588, 0.845047, 1.164717, 2.019893",\ + "0.736081, 0.803009, 0.919468, 1.239139, 2.094314",\ + "0.830502, 0.897430, 1.013889, 1.333560, 2.188735",\ + "1.278260, 1.345188, 1.461647, 1.781317, 2.636493"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.359441, 0.390858, 0.443517, 0.585919, 0.964552",\ + "0.372788, 0.404204, 0.456864, 0.599265, 0.977898",\ + "0.454765, 0.486182, 0.538841, 0.681242, 1.059876",\ + "0.563985, 0.595401, 0.648061, 0.790462, 1.169096",\ + "1.087607, 1.119023, 1.171683, 1.314084, 1.692717"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.540276, 0.571708, 0.624416, 0.766769, 1.145365",\ + "0.558625, 0.590057, 0.642766, 0.785118, 1.163715",\ + "0.632481, 0.663913, 0.716621, 0.858974, 1.237571",\ + "0.730741, 0.762172, 0.814881, 0.957234, 1.335830",\ + "1.254148, 1.285579, 1.338288, 1.480641, 1.859237"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.045711, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.661922, 0.728863, 0.845331, 1.165002, 2.020164",\ + "0.674544, 0.741485, 0.857953, 1.177625, 2.032786",\ + "0.729459, 0.796399, 0.912867, 1.232539, 2.087700",\ + "0.831878, 0.898819, 1.015287, 1.334959, 2.190120",\ + "1.558837, 1.625780, 1.742250, 2.061921, 2.917080"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044476, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073067, 0.188999, 0.391940, 0.949314, 2.441375"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[8]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.287469, 0.318885, 0.371545, 0.513946, 0.892579",\ + "0.304214, 0.335631, 0.388290, 0.530692, 0.909325",\ + "0.382471, 0.413888, 0.466547, 0.608949, 0.987582",\ + "0.506351, 0.537768, 0.590427, 0.732828, 1.111462",\ + "1.074942, 1.106358, 1.159018, 1.301419, 1.680052"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.041900, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.464880, 0.531808, 0.648267, 0.967938, 1.823113",\ + "0.478226, 0.545155, 0.661613, 0.981284, 1.836459",\ + "0.556365, 0.623294, 0.739753, 1.059423, 1.914599",\ + "0.657544, 0.724473, 0.840931, 1.160602, 2.015777",\ + "1.129399, 1.196328, 1.312786, 1.632457, 2.487632"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035639, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + + } /* end of arc obs_ctrl_o[8]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.722991, 0.789932, 0.906400, 1.226072, 2.081233",\ + "0.741544, 0.808485, 0.924953, 1.244625, 2.099786",\ + "0.814242, 0.881183, 0.997651, 1.317322, 2.172483",\ + "0.909467, 0.976408, 1.092876, 1.412548, 2.267709",\ + "1.368597, 1.435539, 1.552008, 1.871680, 2.726840"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073066, 0.188998, 0.391938, 0.949310, 2.441375"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.510317, 0.541749, 0.594457, 0.736810, 1.115407",\ + "0.527859, 0.559291, 0.612000, 0.754352, 1.132949",\ + "0.605188, 0.636620, 0.689329, 0.831681, 1.210278",\ + "0.714634, 0.746065, 0.798774, 0.941126, 1.319723",\ + "1.246573, 1.278005, 1.330713, 1.473066, 1.851663"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.677174, 0.744103, 0.860561, 1.180232, 2.035407",\ + "0.693995, 0.760924, 0.877382, 1.197053, 2.052228",\ + "0.768427, 0.835355, 0.951814, 1.271485, 2.126660",\ + "0.863682, 0.930611, 1.047069, 1.366740, 2.221915",\ + "1.316333, 1.383262, 1.499720, 1.819391, 2.674566"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.381372, 0.412788, 0.465448, 0.607849, 0.986482",\ + "0.394828, 0.426245, 0.478904, 0.621306, 0.999939",\ + "0.476249, 0.507665, 0.560325, 0.702726, 1.081359",\ + "0.586223, 0.617640, 0.670299, 0.812701, 1.191334",\ + "1.111662, 1.143078, 1.195738, 1.338139, 1.716772"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.544142, 0.575574, 0.628282, 0.770635, 1.149231",\ + "0.562695, 0.594126, 0.646835, 0.789188, 1.167784",\ + "0.636753, 0.668185, 0.720893, 0.863246, 1.241843",\ + "0.735854, 0.767286, 0.819994, 0.962347, 1.340943",\ + "1.209522, 1.240954, 1.293662, 1.436015, 1.814612"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.046138, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090609, 0.180697, 0.429275, 1.090833",\ + "0.039144, 0.090610, 0.180696, 0.429275, 1.090836"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.616983, 0.683923, 0.800391, 1.120063, 1.975224",\ + "0.629672, 0.696613, 0.813081, 1.132753, 1.987914",\ + "0.684443, 0.751384, 0.867852, 1.187524, 2.042685",\ + "0.787482, 0.854422, 0.970891, 1.290562, 2.145723",\ + "1.494185, 1.561127, 1.677597, 1.997268, 2.852428"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.044715, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073065, 0.188996, 0.391935, 0.949303, 2.441374",\ + "0.073066, 0.188998, 0.391938, 0.949310, 2.441375"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "obs_ctrl_o[9]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.282372, 0.313788, 0.366448, 0.508849, 0.887482",\ + "0.299186, 0.330603, 0.383262, 0.525663, 0.904297",\ + "0.377525, 0.408942, 0.461601, 0.604002, 0.982636",\ + "0.500058, 0.531475, 0.584134, 0.726535, 1.105169",\ + "1.057248, 1.088664, 1.141323, 1.283725, 1.662358"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.042344, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504",\ + "0.039040, 0.090706, 0.180446, 0.429219, 1.091504"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.472156, 0.539085, 0.655543, 0.975214, 1.830389",\ + "0.485612, 0.552541, 0.669000, 0.988670, 1.843846",\ + "0.563901, 0.630829, 0.747288, 1.066959, 1.922134",\ + "0.663577, 0.730506, 0.846965, 1.166635, 2.021811",\ + "1.128422, 1.195350, 1.311809, 1.631480, 2.486655"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.035869, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363",\ + "0.073056, 0.188976, 0.391905, 0.949239, 2.441363"); + } + + } /* end of arc obs_ctrl_o[9]_ast2padmux_o[0]_inv_min*/ + + timing () { + related_pin : "otm_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.113025, 0.179927, 0.296363, 0.616032, 1.471239",\ + "0.197499, 0.264597, 0.381195, 0.700878, 1.555851",\ + "0.280076, 0.347397, 0.463985, 0.783849, 1.638912",\ + "0.416433, 0.486812, 0.604025, 0.924187, 1.779474",\ + "0.624246, 0.705773, 0.827408, 1.148979, 2.004448"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073036, 0.188929, 0.391837, 0.949094, 2.441339",\ + "0.073183, 0.189268, 0.392332, 0.950151, 2.441515",\ + "0.074613, 0.189268, 0.392404, 0.950824, 2.441515",\ + "0.081868, 0.192856, 0.392640, 0.950928, 2.441515",\ + "0.102993, 0.209850, 0.398253, 0.950928, 2.441550"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.102851, 0.134278, 0.186974, 0.329339, 0.707946",\ + "0.188654, 0.220274, 0.273049, 0.415364, 0.793932",\ + "0.283232, 0.317549, 0.370548, 0.513080, 0.891796",\ + "0.439854, 0.481254, 0.538206, 0.682122, 1.061087",\ + "0.686111, 0.743348, 0.813206, 0.964006, 1.344314"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039116, 0.090635, 0.180630, 0.429260, 1.091011",\ + "0.039742, 0.090679, 0.180942, 0.429335, 1.091011",\ + "0.047350, 0.093337, 0.180942, 0.429351, 1.091547",\ + "0.062153, 0.106580, 0.187253, 0.429567, 1.092904",\ + "0.090069, 0.142497, 0.212830, 0.435355, 1.093832"); + } + + } /* end of arc otm_obs_i[0]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otm_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.111805, 0.178694, 0.295120, 0.614788, 1.470008",\ + "0.195286, 0.262361, 0.378939, 0.698621, 1.553622",\ + "0.274742, 0.342025, 0.458625, 0.778449, 1.633475",\ + "0.405125, 0.474114, 0.590991, 0.911111, 1.766377",\ + "0.603219, 0.681326, 0.800406, 1.120805, 1.976209"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073037, 0.188925, 0.391823, 0.948978, 2.441330",\ + "0.073166, 0.189215, 0.392273, 0.950004, 2.441389",\ + "0.074291, 0.189215, 0.392420, 0.950004, 2.441389",\ + "0.079135, 0.190954, 0.392488, 0.950004, 2.441389",\ + "0.097064, 0.203428, 0.393485, 0.950004, 2.441492"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.077369, 0.108778, 0.161412, 0.303838, 0.682490",\ + "0.166731, 0.198172, 0.250911, 0.393234, 0.771808",\ + "0.254923, 0.288717, 0.341672, 0.484162, 0.862849",\ + "0.400634, 0.441041, 0.497234, 0.640906, 1.019844",\ + "0.631133, 0.687293, 0.756057, 0.905549, 1.285508"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.038988, 0.090550, 0.180320, 0.429191, 1.090420",\ + "0.039208, 0.090550, 0.180739, 0.429310, 1.090420",\ + "0.045872, 0.092820, 0.180739, 0.429348, 1.091289",\ + "0.060397, 0.104342, 0.185891, 0.429526, 1.092845",\ + "0.088207, 0.140006, 0.210014, 0.433521, 1.093776"); + } + + } /* end of arc otm_obs_i[0]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "otp_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.122660, 0.189370, 0.305783, 0.622560, 1.472274",\ + "0.209824, 0.276743, 0.394059, 0.710704, 1.559679",\ + "0.301920, 0.369023, 0.486415, 0.804486, 1.652417",\ + "0.455547, 0.524976, 0.642287, 0.962376, 1.809444",\ + "0.699992, 0.780922, 0.900058, 1.218756, 2.067549"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067561, 0.184527, 0.382478, 0.936925, 2.417724",\ + "0.067561, 0.184527, 0.382478, 0.936925, 2.418306",\ + "0.068683, 0.184527, 0.382544, 0.936925, 2.418306",\ + "0.075540, 0.185756, 0.383113, 0.940410, 2.418306",\ + "0.094401, 0.199857, 0.384817, 0.940410, 2.426093"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.114764, 0.145947, 0.198571, 0.341053, 0.719705",\ + "0.205629, 0.236785, 0.289401, 0.431904, 0.810542",\ + "0.310076, 0.342571, 0.395201, 0.537686, 0.916183",\ + "0.500896, 0.538360, 0.591093, 0.733386, 1.111456",\ + "0.820213, 0.870292, 0.933027, 1.077593, 1.455130"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040532, 0.090273, 0.180246, 0.428609, 1.092443",\ + "0.040870, 0.090273, 0.180281, 0.428609, 1.092443",\ + "0.045400, 0.092351, 0.180508, 0.428609, 1.092443",\ + "0.059558, 0.100025, 0.181106, 0.428872, 1.092443",\ + "0.087354, 0.133744, 0.204884, 0.431205, 1.092443"); + } + + } /* end of arc otp_obs_i[0]_ast2padmux_o[0]_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "otp_obs_i[0]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.119334, 0.186028, 0.302368, 0.619155, 1.468929",\ + "0.204833, 0.271716, 0.388876, 0.705544, 1.554647",\ + "0.293319, 0.360401, 0.477846, 0.795625, 1.643707",\ + "0.440314, 0.508488, 0.625608, 0.945855, 1.792734",\ + "0.667813, 0.745674, 0.864272, 1.183300, 2.031636"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.067620, 0.183691, 0.382409, 0.935142, 2.413233",\ + "0.068262, 0.183691, 0.382508, 0.936031, 2.413233",\ + "0.073482, 0.184226, 0.382946, 0.939859, 2.413233",\ + "0.089380, 0.196045, 0.384240, 0.939859, 2.423100"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.094521, 0.125776, 0.178422, 0.320849, 0.699535",\ + "0.188239, 0.219444, 0.272075, 0.414540, 0.793202",\ + "0.291550, 0.323577, 0.376197, 0.518700, 0.897237",\ + "0.473699, 0.510899, 0.563627, 0.705929, 1.084022",\ + "0.773733, 0.823401, 0.885774, 1.030256, 1.407808"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.039633, 0.090291, 0.180152, 0.428296, 1.092222",\ + "0.040262, 0.090291, 0.180217, 0.428296, 1.092377",\ + "0.044064, 0.091627, 0.180452, 0.428296, 1.092425",\ + "0.058805, 0.099616, 0.181075, 0.428844, 1.092425",\ + "0.086478, 0.132591, 0.204027, 0.431125, 1.092425"); + } + + } /* end of arc otp_obs_i[0]_ast2padmux_o[0]_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.500000, 380000.500000, 380000.531250, 380000.593750, 380000.781250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.750000, 380000.937500",\ + "380000.906250, 380000.906250, 380000.937500, 380001.000000, 380001.187500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497",\ + "0.040752, 0.090609, 0.180697, 0.429275, 1.092497"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.843750, 380001.968750, 380002.281250, 380003.156250",\ + "380001.875000, 380001.937500, 380002.062500, 380002.375000, 380003.250000",\ + "380002.000000, 380002.062500, 380002.187500, 380002.500000, 380003.375000",\ + "380002.187500, 380002.250000, 380002.375000, 380002.687500, 380003.562500",\ + "380002.500000, 380002.562500, 380002.687500, 380003.000000, 380003.875000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537",\ + "0.073650, 0.189304, 0.392450, 0.950561, 2.441537"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[0]_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380000.312500, 380000.312500, 380000.343750, 380000.406250, 380000.593750",\ + "380000.406250, 380000.406250, 380000.437500, 380000.500000, 380000.687500",\ + "380000.468750, 380000.468750, 380000.500000, 380000.562500, 380000.750000",\ + "380000.625000, 380000.625000, 380000.656250, 380000.718750, 380000.906250",\ + "380000.843750, 380000.843750, 380000.875000, 380000.937500, 380001.125000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967",\ + "0.015905, 0.041179, 0.085652, 0.207740, 0.535967"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "380001.781250, 380001.812500, 380001.906250, 380002.187500, 380002.875000",\ + "380001.875000, 380001.906250, 380002.000000, 380002.281250, 380002.968750",\ + "380001.968750, 380002.000000, 380002.093750, 380002.375000, 380003.062500",\ + "380002.156250, 380002.187500, 380002.281250, 380002.562500, 380003.250000",\ + "380002.406250, 380002.437500, 380002.531250, 380002.812500, 380003.500000"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.001393, 0.003837, 0.010569, 0.028584"); + values ( "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169",\ + "0.055484, 0.149920, 0.315966, 0.772511, 1.992169"); + } + + } /* end of arc padmux2ast_i[4]_ast2padmux_o[0]_inv_min*/ + +} /* end of pin ast2padmux_o[0] */ +} /* end of bus ast2padmux_o */ + +pin("ast2pad_t0_ao") { + direction : output ; + max_transition : 5.000000 ; + min_transition : 0.000000 ; + max_capacitance : 0.340000 ; + min_capacitance : 0.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2pad_t0_ao; +} /* end of pin ast2pad_t0_ao */ + +pin("ast2pad_t1_ao") { + direction : output ; + max_transition : 5.000000 ; + min_transition : 0.000000 ; + max_capacitance : 64.000000 ; + min_capacitance : 0.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : ast2pad_t1_ao; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "380005.937500, 380010.968750, 380015.437500, 380024.343750, 380042.031250",\ + "380006.031250, 380011.062500, 380015.531250, 380024.437500, 380042.125000",\ + "380006.125000, 380011.156250, 380015.625000, 380024.531250, 380042.218750",\ + "380006.187500, 380011.218750, 380015.687500, 380024.593750, 380042.281250",\ + "380006.531250, 380011.562500, 380016.031250, 380024.937500, 380042.625000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232"); + } + + } /* end of arc clk_ast_tlul_i_ast2pad_t1_ao_redgf*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "3.958968, 8.968638, 13.431835, 22.333540, 40.062149",\ + "4.046352, 9.056024, 13.519220, 22.420925, 40.149536",\ + "4.127131, 9.136803, 13.599998, 22.501705, 40.230312",\ + "4.184652, 9.194324, 13.657520, 22.559225, 40.287834",\ + "4.486489, 9.496161, 13.959356, 22.861061, 40.589668"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000"); + } + + } /* end of arc clk_ast_tlul_i_ast2pad_t1_ao_redgf_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : three_state_enable_fall ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "380005.843750, 380010.875000, 380015.343750, 380024.250000, 380041.937500",\ + "380005.937500, 380010.968750, 380015.437500, 380024.343750, 380042.031250",\ + "380006.062500, 380011.093750, 380015.562500, 380024.468750, 380042.156250",\ + "380006.250000, 380011.281250, 380015.750000, 380024.656250, 380042.343750",\ + "380006.562500, 380011.593750, 380016.062500, 380024.968750, 380042.656250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232",\ + "0.131672, 1.724206, 3.350886, 6.646091, 13.236232"); + } + + } /* end of arc padmux2ast_i[4]_ast2pad_t1_ao_enlf*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : three_state_enable_fall ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "380005.843750, 380010.875000, 380015.343750, 380024.250000, 380041.937500",\ + "380005.937500, 380010.968750, 380015.437500, 380024.343750, 380042.031250",\ + "380006.031250, 380011.062500, 380015.531250, 380024.437500, 380042.125000",\ + "380006.218750, 380011.250000, 380015.718750, 380024.625000, 380042.312500",\ + "380006.468750, 380011.500000, 380015.968750, 380024.875000, 380042.562500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 8.000000, 16.000000, 32.000000, 64.000000"); + values ( "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000",\ + "0.000000, 0.000000, 0.000000, 0.000000, 0.000000"); + } + + } /* end of arc padmux2ast_i[4]_ast2pad_t1_ao_enlf_min*/ + +} /* end of pin ast2pad_t1_ao */ +bus ( ext_freq_is_96m_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("ext_freq_is_96m_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : ext_freq_is_96m_i[3]; +} /* end of pin ext_freq_is_96m_i[3] */ + +pin("ext_freq_is_96m_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : ext_freq_is_96m_i[2]; +} /* end of pin ext_freq_is_96m_i[2] */ + +pin("ext_freq_is_96m_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : ext_freq_is_96m_i[1]; +} /* end of pin ext_freq_is_96m_i[1] */ + +pin("ext_freq_is_96m_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : ext_freq_is_96m_i[0]; +} /* end of pin ext_freq_is_96m_i[0] */ +} /* end of bus ext_freq_is_96m_i */ +bus ( all_clk_byp_req_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("all_clk_byp_req_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_req_i[3]; +} /* end of pin all_clk_byp_req_i[3] */ + +pin("all_clk_byp_req_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_req_i[2]; +} /* end of pin all_clk_byp_req_i[2] */ + +pin("all_clk_byp_req_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_req_i[1]; +} /* end of pin all_clk_byp_req_i[1] */ + +pin("all_clk_byp_req_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_req_i[0]; +} /* end of pin all_clk_byp_req_i[0] */ +} /* end of bus all_clk_byp_req_i */ +bus ( all_clk_byp_ack_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("all_clk_byp_ack_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_ack_o[3]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[3]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[3]_redg_min*/ + +} /* end of pin all_clk_byp_ack_o[3] */ + +pin("all_clk_byp_ack_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_ack_o[2]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[2]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[2]_redg_min*/ + +} /* end of pin all_clk_byp_ack_o[2] */ + +pin("all_clk_byp_ack_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_ack_o[1]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[1]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[1]_redg_min*/ + +} /* end of pin all_clk_byp_ack_o[1] */ + +pin("all_clk_byp_ack_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : all_clk_byp_ack_o[0]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_all_clk_byp_ack_o[0]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_all_clk_byp_ack_o[0]_redg_min*/ + +} /* end of pin all_clk_byp_ack_o[0] */ +} /* end of bus all_clk_byp_ack_o */ +bus ( io_clk_byp_req_i ) { + + bus_type : BUS4_type6 ; + direction : input ; + +pin("io_clk_byp_req_i[3]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_req_i[3]; +} /* end of pin io_clk_byp_req_i[3] */ + +pin("io_clk_byp_req_i[2]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_req_i[2]; +} /* end of pin io_clk_byp_req_i[2] */ + +pin("io_clk_byp_req_i[1]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.001189 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_req_i[1]; +} /* end of pin io_clk_byp_req_i[1] */ + +pin("io_clk_byp_req_i[0]") { + direction : input ; + max_transition : 2.480000 ; + capacitance : 0.000648 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_req_i[0]; +} /* end of pin io_clk_byp_req_i[0] */ +} /* end of bus io_clk_byp_req_i */ +bus ( io_clk_byp_ack_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("io_clk_byp_ack_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_ack_o[3]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[3]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[3]_redg_min*/ + +} /* end of pin io_clk_byp_ack_o[3] */ + +pin("io_clk_byp_ack_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_ack_o[2]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[2]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[2]_redg_min*/ + +} /* end of pin io_clk_byp_ack_o[2] */ + +pin("io_clk_byp_ack_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_ack_o[1]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055481, 0.185725, 0.392886, 0.714270, 1.356390",\ + "0.142013, 0.273097, 0.480288, 0.802449, 1.446276",\ + "0.227644, 0.367997, 0.574907, 0.896875, 1.540369",\ + "0.372058, 0.538899, 0.745297, 1.066605, 1.708810",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021797, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.025516, 0.238359, 0.631876, 1.247087, 2.477274",\ + "0.039138, 0.240277, 0.631876, 1.247087, 2.477473",\ + "0.067159, 0.248694, 0.631876, 1.247087, 2.479640",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522191, 0.932963",\ + "0.170164, 0.270956, 0.404436, 0.610175, 1.020954",\ + "0.251445, 0.351944, 0.485256, 0.690977, 1.101771",\ + "0.388999, 0.491163, 0.624361, 0.829801, 1.240010",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025565, 0.151628, 0.387851, 0.763293, 1.515348",\ + "0.025565, 0.151804, 0.389259, 0.763293, 1.515348",\ + "0.025976, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.029120, 0.151804, 0.389479, 0.764390, 1.515348",\ + "0.041734, 0.154598, 0.389479, 0.764390, 1.515348"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.055478, 0.185724, 0.392885, 0.714263, 1.356368",\ + "0.141644, 0.273073, 0.480017, 0.801359, 1.443459",\ + "0.227644, 0.367995, 0.574890, 0.896861, 1.540369",\ + "0.372055, 0.538895, 0.745296, 1.066605, 1.708810",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021795, 0.238265, 0.630524, 1.245754, 2.477107",\ + "0.025501, 0.238265, 0.630524, 1.245754, 2.477170",\ + "0.039138, 0.240263, 0.630524, 1.245754, 2.477473",\ + "0.067158, 0.248694, 0.630752, 1.245754, 2.478674",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.082179, 0.183018, 0.316461, 0.522190, 0.932959",\ + "0.170151, 0.270913, 0.404355, 0.610080, 1.020840",\ + "0.251186, 0.351686, 0.484981, 0.690703, 1.101507",\ + "0.388979, 0.491150, 0.624343, 0.829707, 1.239752",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025557, 0.151128, 0.387354, 0.761934, 1.510661",\ + "0.025965, 0.151128, 0.387354, 0.761934, 1.511090",\ + "0.029101, 0.151585, 0.387354, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[1]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058414, 0.188667, 0.395813, 0.717110, 1.359045",\ + "0.112550, 0.243041, 0.450135, 0.772138, 1.415649",\ + "0.253196, 0.398235, 0.605055, 0.926906, 1.570171",\ + "0.312752, 0.468715, 0.675324, 0.996903, 1.639637",\ + "0.601931, 0.834236, 1.042645, 1.363437, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021790, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.023317, 0.238360, 0.631894, 1.247121, 2.477336",\ + "0.044096, 0.241766, 0.631894, 1.247121, 2.477920",\ + "0.055652, 0.245238, 0.631894, 1.247121, 2.478962",\ + "0.123088, 0.289704, 0.642858, 1.251241, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141978, 0.242754, 0.376239, 0.581985, 0.992777",\ + "0.275783, 0.376576, 0.509868, 0.715539, 1.126231",\ + "0.332511, 0.433991, 0.567236, 0.772791, 1.183241",\ + "0.607343, 0.718683, 0.852150, 1.057410, 1.467133"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151693, 0.388430, 0.763132, 1.513362",\ + "0.025646, 0.151849, 0.389568, 0.763815, 1.513362",\ + "0.026529, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.027825, 0.151849, 0.389568, 0.764056, 1.513362",\ + "0.041734, 0.154598, 0.389568, 0.764056, 1.513362"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.058410, 0.188665, 0.395812, 0.717100, 1.359014",\ + "0.112399, 0.243028, 0.450025, 0.771635, 1.414310",\ + "0.253195, 0.398233, 0.605040, 0.926895, 1.570171",\ + "0.311693, 0.467461, 0.674069, 0.995655, 1.638404",\ + "0.601899, 0.834203, 1.042596, 1.363402, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.021782, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.023311, 0.238225, 0.630549, 1.245808, 2.476689",\ + "0.044096, 0.241755, 0.630564, 1.245808, 2.477789",\ + "0.055446, 0.245170, 0.630656, 1.245808, 2.478512",\ + "0.122913, 0.289395, 0.639350, 1.248196, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.085404, 0.186224, 0.319679, 0.525413, 0.936188",\ + "0.141970, 0.242733, 0.376196, 0.581868, 0.992503",\ + "0.275567, 0.376362, 0.509639, 0.715298, 1.125968",\ + "0.331384, 0.432856, 0.566092, 0.771606, 1.181968",\ + "0.607308, 0.718634, 0.852099, 1.057372, 1.467127"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.014296, 0.039544, 0.079088, 0.158177"); + values ( "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.025646, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.026523, 0.151208, 0.387784, 0.761934, 1.511090",\ + "0.027795, 0.151394, 0.387784, 0.761934, 1.511090",\ + "0.041668, 0.154530, 0.388178, 0.761934, 1.511090"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[1]_redg_min*/ + +} /* end of pin io_clk_byp_ack_o[1] */ + +pin("io_clk_byp_ack_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000000 ; + + /* Other user defined attributes. */ + original_pin : io_clk_byp_ack_o[0]; + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100843, 0.266735, 0.427088, 0.747616, 1.388635",\ + "0.184687, 0.350464, 0.510809, 0.831717, 1.473578",\ + "0.260267, 0.426010, 0.586434, 0.907636, 1.550114",\ + "0.386507, 0.552662, 0.713534, 1.034573, 1.676504",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015579, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.316961, 0.624670, 1.238691, 2.466601",\ + "0.015665, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.015838, 0.317088, 0.625771, 1.239746, 2.466601",\ + "0.016716, 0.317340, 0.625771, 1.239746, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.088041, 0.202376, 0.303813, 0.506089, 0.910516",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664815, 1.067688",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015700, 0.193950, 0.379890, 0.747742, 1.482887",\ + "0.016044, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.017520, 0.193950, 0.379890, 0.747742, 1.485202",\ + "0.022344, 0.194037, 0.379890, 0.747742, 1.485202",\ + "0.034639, 0.196727, 0.379890, 0.748439, 1.491839"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.100718, 0.266618, 0.426903, 0.747412, 1.388420",\ + "0.184686, 0.350463, 0.510806, 0.831715, 1.473578",\ + "0.260208, 0.425985, 0.586426, 0.907607, 1.550030",\ + "0.386259, 0.552119, 0.712336, 1.032993, 1.674352",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316821, 0.622606, 1.236473, 2.462725",\ + "0.015496, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.015814, 0.316929, 0.622606, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.087868, 0.202376, 0.303809, 0.506029, 0.910334",\ + "0.168483, 0.282824, 0.383745, 0.585711, 0.989669",\ + "0.247358, 0.362640, 0.463376, 0.664779, 1.067573",\ + "0.380658, 0.500049, 0.601022, 0.802517, 1.205414",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015619, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.016032, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.017339, 0.192979, 0.376641, 0.744531, 1.480142",\ + "0.022190, 0.193551, 0.376842, 0.744531, 1.480142",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_ast_ext_i_io_clk_byp_ack_o[0]_redg_min*/ + + timing () { + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103995, 0.269872, 0.430200, 0.750758, 1.391853",\ + "0.158337, 0.324154, 0.484388, 0.804979, 1.446186",\ + "0.282603, 0.448419, 0.608923, 0.930096, 1.572477",\ + "0.334665, 0.500651, 0.661339, 0.982445, 1.624600",\ + "0.580400, 0.747044, 0.907773, 1.228098, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015542, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317035, 0.624600, 1.238588, 2.466325",\ + "0.015645, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.015655, 0.317066, 0.625211, 1.239292, 2.466325",\ + "0.016716, 0.317340, 0.625211, 1.239292, 2.466325"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090477, 0.204718, 0.305888, 0.507773, 0.911447",\ + "0.141442, 0.255688, 0.356617, 0.558511, 0.962305",\ + "0.270943, 0.386953, 0.487730, 0.689180, 1.092056",\ + "0.325917, 0.443620, 0.544496, 0.745968, 1.148855",\ + "0.586485, 0.719001, 0.819955, 1.021830, 1.425575"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.813271, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015734, 0.193610, 0.378735, 0.747021, 1.483183",\ + "0.015916, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.018374, 0.193610, 0.378735, 0.747293, 1.484513",\ + "0.020363, 0.193614, 0.378735, 0.747293, 1.484513",\ + "0.034639, 0.196727, 0.378735, 0.748439, 1.491839"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_src_io_o" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.103875, 0.269735, 0.430056, 0.750620, 1.391729",\ + "0.158336, 0.324133, 0.484382, 0.804893, 1.445917",\ + "0.282510, 0.448302, 0.608704, 0.929792, 1.572026",\ + "0.333572, 0.499397, 0.659708, 0.980584, 1.622387",\ + "0.580173, 0.746795, 0.907585, 1.227594, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316838, 0.623370, 1.236473, 2.462725",\ + "0.015480, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.015652, 0.316929, 0.623370, 1.236473, 2.462725",\ + "0.016700, 0.316929, 0.623370, 1.236473, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.090378, 0.204717, 0.305882, 0.507735, 0.911343",\ + "0.141442, 0.255688, 0.356617, 0.558510, 0.962304",\ + "0.270943, 0.386953, 0.487730, 0.689150, 1.091961",\ + "0.324941, 0.442615, 0.543488, 0.744945, 1.147798",\ + "0.586485, 0.718955, 0.819794, 1.021516, 1.424967"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.006578, 0.127724, 0.562810, 0.808825, 2.480000"); + index_2 ( "0.000000, 0.020214, 0.040428, 0.080856, 0.161713"); + values ( "0.015687, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.015912, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.018197, 0.193080, 0.376676, 0.744928, 1.481536",\ + "0.020162, 0.193312, 0.376758, 0.744928, 1.481536",\ + "0.033893, 0.196557, 0.377640, 0.746288, 1.484937"); + } + + } /* end of arc clk_src_io_o_io_clk_byp_ack_o[0]_redg_min*/ + +} /* end of pin io_clk_byp_ack_o[0] */ +} /* end of bus io_clk_byp_ack_o */ +bus ( flash_bist_en_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("flash_bist_en_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000495 ; + + /* Other user defined attributes. */ + original_pin : flash_bist_en_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.106472, 0.270169, 0.430032, 0.749578, 1.388635",\ + "0.190222, 0.353899, 0.513753, 0.833681, 1.473578",\ + "0.265754, 0.429446, 0.589380, 0.909602, 1.550114",\ + "0.318401, 0.482257, 0.642376, 0.962527, 1.602811",\ + "0.586143, 0.750487, 0.910724, 1.230057, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\ + "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\ + "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\ + "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\ + "0.023510, 0.323927, 0.631438, 1.243501, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.093077, 0.204486, 0.305612, 0.507263, 0.910452",\ + "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\ + "0.252842, 0.364735, 0.465162, 0.665985, 1.067625",\ + "0.308854, 0.422028, 0.522554, 0.723398, 1.125048",\ + "0.595772, 0.721100, 0.821745, 1.023002, 1.425511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.020965, 0.197814, 0.383189, 0.749876, 1.482771",\ + "0.021088, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.022399, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.024352, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.039819, 0.200489, 0.383189, 0.750597, 1.491722"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.106274, 0.270052, 0.429845, 0.749374, 1.388420",\ + "0.190221, 0.353898, 0.513750, 0.833679, 1.473578",\ + "0.265727, 0.429421, 0.589372, 0.909573, 1.550030",\ + "0.318289, 0.482010, 0.641868, 0.961850, 1.601865",\ + "0.585943, 0.750239, 0.910537, 1.229551, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\ + "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\ + "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\ + "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\ + "0.023422, 0.323493, 0.628996, 1.240225, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.093062, 0.204485, 0.305607, 0.507203, 0.910270",\ + "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\ + "0.252842, 0.364735, 0.465162, 0.665949, 1.067509",\ + "0.308854, 0.422028, 0.522554, 0.723377, 1.124981",\ + "0.595772, 0.721051, 0.821582, 1.022687, 1.424903"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.020958, 0.196798, 0.379897, 0.747224, 1.481125",\ + "0.021082, 0.196798, 0.379897, 0.747224, 1.481487",\ + "0.022349, 0.196798, 0.379897, 0.747224, 1.481970",\ + "0.024295, 0.197033, 0.379979, 0.747224, 1.481970",\ + "0.039434, 0.200322, 0.380851, 0.748432, 1.484821"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[3]_redg_min*/ + +} /* end of pin flash_bist_en_o[3] */ + +pin("flash_bist_en_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000933 ; + + /* Other user defined attributes. */ + original_pin : flash_bist_en_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.068360, 0.193376, 0.398624, 0.718055, 1.356390",\ + "0.155472, 0.280749, 0.486028, 0.806244, 1.446276",\ + "0.245378, 0.375639, 0.580639, 0.900669, 1.540369",\ + "0.309418, 0.446887, 0.651675, 0.971433, 1.610599",\ + "0.645820, 0.841934, 1.048418, 1.367213, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.036908, 0.252893, 0.642777, 1.254340, 2.477274",\ + "0.039249, 0.252893, 0.642777, 1.254340, 2.477274",\ + "0.052853, 0.254696, 0.642777, 1.254340, 2.477473",\ + "0.066089, 0.258077, 0.642777, 1.254340, 2.478527",\ + "0.148778, 0.302748, 0.652641, 1.258483, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.095441, 0.187812, 0.320023, 0.524480, 0.932830",\ + "0.183363, 0.275751, 0.407999, 0.612464, 1.020822",\ + "0.264739, 0.356733, 0.488814, 0.693266, 1.101639",\ + "0.322419, 0.414777, 0.546811, 0.751146, 1.159276",\ + "0.625473, 0.723477, 0.855712, 1.059693, 1.467001"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.038391, 0.160114, 0.394156, 0.767483, 1.515105",\ + "0.038391, 0.160334, 0.395597, 0.767483, 1.515105",\ + "0.038391, 0.160334, 0.395837, 0.768571, 1.515105",\ + "0.039404, 0.160334, 0.395837, 0.768571, 1.515105",\ + "0.052962, 0.163010, 0.395837, 0.768571, 1.515105"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.068360, 0.193375, 0.398624, 0.718048, 1.356368",\ + "0.155472, 0.280716, 0.485750, 0.805145, 1.443459",\ + "0.245377, 0.375636, 0.580621, 0.900655, 1.540369",\ + "0.309416, 0.446884, 0.651665, 0.971425, 1.610599",\ + "0.645736, 0.841900, 1.048369, 1.367178, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.036903, 0.252768, 0.641334, 1.253096, 2.477107",\ + "0.039197, 0.252768, 0.641334, 1.253096, 2.477170",\ + "0.052850, 0.254678, 0.641334, 1.253096, 2.477473",\ + "0.066086, 0.258066, 0.641335, 1.253096, 2.478218",\ + "0.148778, 0.302321, 0.649044, 1.255451, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.095441, 0.187812, 0.320023, 0.524479, 0.932827",\ + "0.183333, 0.275707, 0.407917, 0.612369, 1.020708",\ + "0.264498, 0.356474, 0.488538, 0.692993, 1.101375",\ + "0.322270, 0.414621, 0.546643, 0.750947, 1.159015",\ + "0.625416, 0.723429, 0.855662, 1.059656, 1.466994"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000933, 0.015228, 0.040244, 0.079555, 0.158177"); + values ( "0.038382, 0.159650, 0.394147, 0.766109, 1.510420",\ + "0.038382, 0.159650, 0.394269, 0.766109, 1.510420",\ + "0.038382, 0.159650, 0.394269, 0.766109, 1.510848",\ + "0.039368, 0.159819, 0.394269, 0.766109, 1.510848",\ + "0.052940, 0.162923, 0.394414, 0.766109, 1.510848"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.036908, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.389662, 0.307033, 0.231889, 0.198170, 0.165471",\ + "0.404008, 0.321379, 0.246234, 0.212515, 0.179817",\ + "0.484046, 0.401418, 0.326273, 0.292554, 0.259856",\ + "0.581919, 0.499290, 0.424146, 0.390427, 0.357729",\ + "1.023710, 0.941089, 0.865969, 0.832267, 0.799656"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.038391, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.456800, 0.480507, 0.558316, 0.625895, 1.056719",\ + "0.470804, 0.494511, 0.572320, 0.639899, 1.070723",\ + "0.534795, 0.558499, 0.636308, 0.703887, 1.134711",\ + "0.638862, 0.662815, 0.740625, 0.808204, 1.239027",\ + "1.201475, 1.225922, 1.303731, 1.371310, 1.802133"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.036903, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.194420, -0.153007, -0.120290, -0.084607, 0.143547",\ + "-0.208763, -0.167350, -0.134633, -0.098950, 0.129204",\ + "-0.288800, -0.247387, -0.214670, -0.178991, 0.049163",\ + "-0.387771, -0.346358, -0.313641, -0.276864, -0.048710",\ + "-0.830571, -0.789157, -0.756441, -0.718639, -0.490440"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.038382, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.332777, -0.310549, -0.274864, -0.249589, -0.121504",\ + "-0.346777, -0.324549, -0.288864, -0.263590, -0.135504",\ + "-0.410769, -0.388544, -0.352859, -0.327585, -0.199499",\ + "-0.515085, -0.492611, -0.456925, -0.431651, -0.303566",\ + "-1.078191, -1.055218, -1.019535, -0.994261, -0.866175"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[2]_hldr*/ + +} /* end of pin flash_bist_en_o[2] */ + +pin("flash_bist_en_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000982 ; + + /* Other user defined attributes. */ + original_pin : flash_bist_en_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.068874, 0.193784, 0.398930, 0.718257, 1.356391",\ + "0.155991, 0.281157, 0.486334, 0.806447, 1.446276",\ + "0.245977, 0.376046, 0.580944, 0.900871, 1.540369",\ + "0.310114, 0.447294, 0.651980, 0.971635, 1.610599",\ + "0.647142, 0.842344, 1.048726, 1.367414, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.037694, 0.253668, 0.643358, 1.254727, 2.477274",\ + "0.040003, 0.253668, 0.643358, 1.254727, 2.477274",\ + "0.053519, 0.255465, 0.643358, 1.254727, 2.477474",\ + "0.066746, 0.258839, 0.643358, 1.254727, 2.478527",\ + "0.149647, 0.303443, 0.653162, 1.258869, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.095870, 0.188047, 0.320193, 0.524583, 0.932804",\ + "0.183791, 0.275986, 0.408168, 0.612567, 1.020795",\ + "0.265166, 0.356968, 0.488983, 0.693368, 1.101612",\ + "0.322850, 0.415012, 0.546981, 0.751248, 1.159250",\ + "0.625969, 0.723713, 0.855882, 1.059795, 1.466974"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.038860, 0.160530, 0.394456, 0.767671, 1.515056",\ + "0.038860, 0.160753, 0.395899, 0.767671, 1.515056",\ + "0.038860, 0.160753, 0.396141, 0.768758, 1.515056",\ + "0.039865, 0.160753, 0.396141, 0.768758, 1.515056",\ + "0.053336, 0.163423, 0.396141, 0.768758, 1.515056"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.068873, 0.193783, 0.398930, 0.718250, 1.356368",\ + "0.155991, 0.281124, 0.486056, 0.805347, 1.443459",\ + "0.245976, 0.376044, 0.580926, 0.900857, 1.540369",\ + "0.310112, 0.447291, 0.651970, 0.971627, 1.610599",\ + "0.647058, 0.842310, 1.048677, 1.367379, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.037688, 0.253541, 0.641906, 1.253483, 2.477107",\ + "0.039952, 0.253541, 0.641906, 1.253483, 2.477170",\ + "0.053515, 0.255446, 0.641906, 1.253483, 2.477474",\ + "0.066744, 0.258828, 0.641906, 1.253483, 2.478218",\ + "0.149647, 0.303009, 0.649561, 1.255837, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.095870, 0.188047, 0.320193, 0.524582, 0.932800",\ + "0.183761, 0.275942, 0.408087, 0.612471, 1.020681",\ + "0.264924, 0.356709, 0.488708, 0.693095, 1.101348",\ + "0.322701, 0.414856, 0.546813, 0.751050, 1.158988",\ + "0.625912, 0.723664, 0.855831, 1.059758, 1.466968"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000982, 0.015278, 0.040281, 0.079579, 0.158177"); + values ( "0.038851, 0.160069, 0.394447, 0.766295, 1.510371",\ + "0.038851, 0.160069, 0.394570, 0.766295, 1.510371",\ + "0.038851, 0.160069, 0.394570, 0.766295, 1.510800",\ + "0.039829, 0.160236, 0.394570, 0.766295, 1.510800",\ + "0.053313, 0.163335, 0.394711, 0.766295, 1.510800"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.037694, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.387207, 0.304578, 0.229434, 0.195714, 0.163016",\ + "0.401633, 0.319004, 0.243859, 0.210140, 0.177442",\ + "0.477915, 0.395287, 0.320142, 0.286423, 0.253725",\ + "0.569150, 0.486521, 0.411377, 0.377658, 0.344959",\ + "0.968197, 0.885576, 0.810456, 0.776755, 0.744146"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.038860, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.458514, 0.482233, 0.560042, 0.627621, 1.058444",\ + "0.470955, 0.494673, 0.572482, 0.640062, 1.070885",\ + "0.535510, 0.559226, 0.637035, 0.704614, 1.135437",\ + "0.647291, 0.671342, 0.749152, 0.816731, 1.247554",\ + "1.199795, 1.224990, 1.302845, 1.370443, 1.801277"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.037688, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.191963, -0.150550, -0.117833, -0.082151, 0.146002",\ + "-0.206387, -0.164973, -0.132257, -0.096575, 0.131579",\ + "-0.282671, -0.241257, -0.208540, -0.172860, 0.055294",\ + "-0.374978, -0.333564, -0.300848, -0.264095, -0.035941",\ + "-0.775028, -0.733615, -0.700898, -0.663125, -0.434925"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.038851, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.334502, -0.312263, -0.276578, -0.251304, -0.123218",\ + "-0.346939, -0.324701, -0.289015, -0.263741, -0.135656",\ + "-0.411495, -0.389259, -0.353574, -0.328299, -0.200214",\ + "-0.523612, -0.501040, -0.465355, -0.440080, -0.311995",\ + "-1.077244, -1.053536, -1.017853, -0.992580, -0.864493"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[1]_hldr*/ + +} /* end of pin flash_bist_en_o[1] */ + +pin("flash_bist_en_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.000495 ; + + /* Other user defined attributes. */ + original_pin : flash_bist_en_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.106472, 0.270169, 0.430032, 0.749578, 1.388635",\ + "0.190222, 0.353899, 0.513753, 0.833681, 1.473578",\ + "0.265754, 0.429446, 0.589380, 0.909602, 1.550114",\ + "0.318401, 0.482257, 0.642376, 0.962527, 1.602811",\ + "0.586143, 0.750487, 0.910724, 1.230057, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\ + "0.022534, 0.323552, 0.630320, 1.242449, 2.466601",\ + "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\ + "0.022534, 0.323700, 0.631438, 1.243501, 2.466601",\ + "0.023510, 0.323927, 0.631438, 1.243501, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.093077, 0.204486, 0.305612, 0.507263, 0.910452",\ + "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\ + "0.252842, 0.364735, 0.465162, 0.665985, 1.067625",\ + "0.308854, 0.422028, 0.522554, 0.723398, 1.125048",\ + "0.595772, 0.721100, 0.821745, 1.023002, 1.425511"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.020965, 0.197814, 0.383189, 0.749876, 1.482771",\ + "0.021088, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.022399, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.024352, 0.197814, 0.383189, 0.749876, 1.485086",\ + "0.039819, 0.200489, 0.383189, 0.750597, 1.491722"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.106274, 0.270052, 0.429845, 0.749374, 1.388420",\ + "0.190221, 0.353898, 0.513750, 0.833679, 1.473578",\ + "0.265727, 0.429421, 0.589372, 0.909573, 1.550030",\ + "0.318289, 0.482010, 0.641868, 0.961850, 1.601865",\ + "0.585943, 0.750239, 0.910537, 1.229551, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\ + "0.022505, 0.323384, 0.628823, 1.240225, 2.462725",\ + "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\ + "0.022505, 0.323493, 0.628996, 1.240225, 2.462725",\ + "0.023422, 0.323493, 0.628996, 1.240225, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.093062, 0.204485, 0.305607, 0.507203, 0.910270",\ + "0.173702, 0.284922, 0.385535, 0.586884, 0.989605",\ + "0.252842, 0.364735, 0.465162, 0.665949, 1.067509",\ + "0.308854, 0.422028, 0.522554, 0.723377, 1.124981",\ + "0.595772, 0.721051, 0.821582, 1.022687, 1.424903"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.000495, 0.020647, 0.040799, 0.081104, 0.161713"); + values ( "0.020958, 0.196798, 0.379897, 0.747224, 1.481125",\ + "0.021082, 0.196798, 0.379897, 0.747224, 1.481487",\ + "0.022349, 0.196798, 0.379897, 0.747224, 1.481970",\ + "0.024295, 0.197033, 0.379979, 0.747224, 1.481970",\ + "0.039434, 0.200322, 0.380851, 0.748432, 1.484821"); + } + + } /* end of arc clk_ast_tlul_i_flash_bist_en_o[0]_redg_min*/ + +} /* end of pin flash_bist_en_o[0] */ +} /* end of bus flash_bist_en_o */ +bus ( dpram_rmf_o ) { + + bus_type : BUS10_type8 ; + direction : output ; + +pin("dpram_rmf_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002475 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.250443, 2.482564",\ + "0.030125, 0.302556, 0.636324, 1.250443, 2.482564",\ + "0.042888, 0.304795, 0.636360, 1.250443, 2.482564",\ + "0.054816, 0.308050, 0.636463, 1.250443, 2.482564",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.188435, 0.388543, 0.760465, 1.504307",\ + "0.025687, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.026721, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.028743, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.047139, 0.192514, 0.389046, 0.760465, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.249210, 2.473548",\ + "0.030125, 0.302556, 0.636324, 1.249210, 2.473548",\ + "0.042888, 0.304795, 0.636360, 1.249285, 2.473548",\ + "0.054816, 0.308050, 0.636463, 1.250030, 2.473548",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.026721, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.028743, 0.188240, 0.387493, 0.759136, 1.502422",\ + "0.047139, 0.192514, 0.387566, 0.759907, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216765, 0.170836, 0.140637, 0.129293, 0.142978",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251111, 0.175790, 0.107631, 0.084664, 0.147578",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148693, -0.106276, -0.071789, -0.032365, 0.273682",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164267, -0.098352, -0.040693, 0.001268, 0.221876",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[9]_hldr*/ + +} /* end of pin dpram_rmf_o[9] */ + +pin("dpram_rmf_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002026 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\ + "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\ + "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\ + "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\ + "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.046348, 0.191554, 0.388300, 0.759979, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\ + "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\ + "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\ + "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\ + "0.046348, 0.191554, 0.386818, 0.759420, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[8]_hldr*/ + +} /* end of pin dpram_rmf_o[8] */ + +pin("dpram_rmf_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002475 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.250443, 2.482564",\ + "0.030125, 0.302556, 0.636324, 1.250443, 2.482564",\ + "0.042888, 0.304795, 0.636360, 1.250443, 2.482564",\ + "0.054816, 0.308050, 0.636463, 1.250443, 2.482564",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.188435, 0.388543, 0.760465, 1.504307",\ + "0.025687, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.026721, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.028743, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.047139, 0.192514, 0.389046, 0.760465, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.249210, 2.473548",\ + "0.030125, 0.302556, 0.636324, 1.249210, 2.473548",\ + "0.042888, 0.304795, 0.636360, 1.249285, 2.473548",\ + "0.054816, 0.308050, 0.636463, 1.250030, 2.473548",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.026721, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.028743, 0.188240, 0.387493, 0.759136, 1.502422",\ + "0.047139, 0.192514, 0.387566, 0.759907, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216765, 0.170836, 0.140637, 0.129293, 0.142978",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251111, 0.175790, 0.107631, 0.084664, 0.147578",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148693, -0.106276, -0.071789, -0.032365, 0.273682",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164267, -0.098352, -0.040693, 0.001268, 0.221876",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[7]_hldr*/ + +} /* end of pin dpram_rmf_o[7] */ + +pin("dpram_rmf_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002493 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.049484, 0.202188, 0.377310, 0.699821, 1.344843",\ + "0.135872, 0.289362, 0.464414, 0.786535, 1.430777",\ + "0.219397, 0.377489, 0.552369, 0.874157, 1.517732",\ + "0.277634, 0.441882, 0.616484, 0.938070, 1.581241",\ + "0.579590, 0.791757, 0.966864, 1.286808, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.025847, 0.301627, 0.634436, 1.250478, 2.482563",\ + "0.030184, 0.302625, 0.636376, 1.250478, 2.482563",\ + "0.042939, 0.304864, 0.636412, 1.250478, 2.482563",\ + "0.054868, 0.308118, 0.636515, 1.250478, 2.482563",\ + "0.130853, 0.346231, 0.642764, 1.253025, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.068955, 0.173526, 0.284810, 0.488770, 0.896690",\ + "0.156363, 0.260844, 0.372091, 0.576075, 0.984043",\ + "0.236740, 0.341176, 0.452118, 0.656103, 1.064075",\ + "0.293480, 0.398725, 0.509660, 0.713348, 1.120723",\ + "0.587780, 0.702066, 0.813291, 1.016361, 1.422500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.025734, 0.188477, 0.388576, 0.760487, 1.504309",\ + "0.025734, 0.188626, 0.389079, 0.760487, 1.504309",\ + "0.026766, 0.188626, 0.389079, 0.760487, 1.504309",\ + "0.028786, 0.188626, 0.389079, 0.760487, 1.504309",\ + "0.047173, 0.192555, 0.389079, 0.760487, 1.504589"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.049484, 0.202188, 0.377310, 0.699821, 1.344843",\ + "0.135872, 0.289362, 0.464414, 0.786535, 1.430777",\ + "0.219397, 0.377489, 0.552369, 0.874157, 1.517732",\ + "0.277634, 0.441882, 0.616484, 0.938070, 1.581241",\ + "0.579590, 0.791757, 0.966864, 1.286808, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.025847, 0.301627, 0.634436, 1.249244, 2.473548",\ + "0.030184, 0.302625, 0.636376, 1.249244, 2.473548",\ + "0.042939, 0.304864, 0.636412, 1.249320, 2.473548",\ + "0.054868, 0.308118, 0.636515, 1.250065, 2.473548",\ + "0.130853, 0.346231, 0.642764, 1.253025, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.068955, 0.173526, 0.284810, 0.488770, 0.896690",\ + "0.156363, 0.260844, 0.372091, 0.576075, 0.984043",\ + "0.236740, 0.341176, 0.452118, 0.656103, 1.064075",\ + "0.293480, 0.398725, 0.509660, 0.713348, 1.120723",\ + "0.587780, 0.702066, 0.813291, 1.016361, 1.422500"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002493, 0.075491, 0.162372, 0.322252, 0.642011"); + values ( "0.025734, 0.187674, 0.387068, 0.758256, 1.500632",\ + "0.025734, 0.187674, 0.387068, 0.758256, 1.500632",\ + "0.026766, 0.187674, 0.387068, 0.758256, 1.500632",\ + "0.028786, 0.188283, 0.387526, 0.759158, 1.502423",\ + "0.047173, 0.192555, 0.387599, 0.759929, 1.504589"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025847, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216796, 0.170867, 0.140667, 0.129323, 0.143008",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025734, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251133, 0.175811, 0.107652, 0.084685, 0.147599",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025847, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148723, -0.106306, -0.071819, -0.032395, 0.273652",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025734, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164288, -0.098373, -0.040714, 0.001247, 0.221854",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[6]_hldr*/ + +} /* end of pin dpram_rmf_o[6] */ + +pin("dpram_rmf_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002464 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.049406, 0.202130, 0.377266, 0.699792, 1.344843",\ + "0.135790, 0.289304, 0.464371, 0.786506, 1.430777",\ + "0.219296, 0.377431, 0.552325, 0.874128, 1.517732",\ + "0.277514, 0.441824, 0.616441, 0.938041, 1.581241",\ + "0.579353, 0.791699, 0.966821, 1.286780, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.025743, 0.301517, 0.634353, 1.250423, 2.482564",\ + "0.030090, 0.302515, 0.636293, 1.250423, 2.482564",\ + "0.042857, 0.304754, 0.636329, 1.250423, 2.482564",\ + "0.054785, 0.308010, 0.636433, 1.250423, 2.482564",\ + "0.130748, 0.346137, 0.642682, 1.252970, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.068893, 0.173494, 0.284787, 0.488756, 0.896694",\ + "0.156301, 0.260812, 0.372068, 0.576061, 0.984048",\ + "0.236678, 0.341144, 0.452094, 0.656090, 1.064079",\ + "0.293415, 0.398693, 0.509637, 0.713334, 1.120727",\ + "0.587689, 0.702034, 0.813268, 1.016347, 1.422504"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.025670, 0.188420, 0.388534, 0.760462, 1.504317",\ + "0.025670, 0.188568, 0.389037, 0.760462, 1.504317",\ + "0.026706, 0.188568, 0.389037, 0.760462, 1.504317",\ + "0.028728, 0.188568, 0.389037, 0.760462, 1.504317",\ + "0.047127, 0.192499, 0.389037, 0.760462, 1.504597"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.049406, 0.202130, 0.377266, 0.699792, 1.344843",\ + "0.135790, 0.289304, 0.464371, 0.786506, 1.430777",\ + "0.219296, 0.377431, 0.552325, 0.874128, 1.517732",\ + "0.277514, 0.441824, 0.616441, 0.938041, 1.581241",\ + "0.579353, 0.791699, 0.966821, 1.286780, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.025743, 0.301517, 0.634353, 1.249189, 2.473548",\ + "0.030090, 0.302515, 0.636293, 1.249189, 2.473548",\ + "0.042857, 0.304754, 0.636329, 1.249264, 2.473548",\ + "0.054785, 0.308010, 0.636433, 1.250010, 2.473548",\ + "0.130748, 0.346137, 0.642682, 1.252970, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.068893, 0.173494, 0.284787, 0.488756, 0.896694",\ + "0.156301, 0.260812, 0.372068, 0.576061, 0.984048",\ + "0.236678, 0.341144, 0.452094, 0.656090, 1.064079",\ + "0.293415, 0.398693, 0.509637, 0.713334, 1.120727",\ + "0.587689, 0.702034, 0.813268, 1.016347, 1.422504"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002464, 0.075463, 0.162351, 0.322237, 0.642011"); + values ( "0.025670, 0.187616, 0.387026, 0.758231, 1.500640",\ + "0.025670, 0.187616, 0.387026, 0.758231, 1.500640",\ + "0.026706, 0.187616, 0.387026, 0.758231, 1.500640",\ + "0.028728, 0.188225, 0.387484, 0.759133, 1.502431",\ + "0.047127, 0.192499, 0.387557, 0.759904, 1.504597"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025743, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216747, 0.170818, 0.140619, 0.129275, 0.142960",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025670, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251104, 0.175782, 0.107623, 0.084656, 0.147570",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025743, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148675, -0.106258, -0.071771, -0.032347, 0.273700",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025670, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164259, -0.098344, -0.040686, 0.001276, 0.221883",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[5]_hldr*/ + +} /* end of pin dpram_rmf_o[5] */ + +pin("dpram_rmf_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002015 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\ + "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\ + "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\ + "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\ + "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.046336, 0.191539, 0.388291, 0.759976, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\ + "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\ + "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\ + "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\ + "0.046336, 0.191539, 0.386809, 0.759417, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[4]_hldr*/ + +} /* end of pin dpram_rmf_o[4] */ + +pin("dpram_rmf_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002005 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\ + "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\ + "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\ + "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\ + "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.046319, 0.191519, 0.388276, 0.759966, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\ + "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\ + "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\ + "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\ + "0.046319, 0.191519, 0.386794, 0.759408, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[3]_hldr*/ + +} /* end of pin dpram_rmf_o[3] */ + +pin("dpram_rmf_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002015 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\ + "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\ + "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\ + "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\ + "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.046336, 0.191539, 0.388291, 0.759976, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\ + "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\ + "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\ + "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\ + "0.046336, 0.191539, 0.386809, 0.759417, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[2]_hldr*/ + +} /* end of pin dpram_rmf_o[2] */ + +pin("dpram_rmf_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003002 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.251459, 2.482564",\ + "0.031840, 0.304583, 0.637840, 1.251459, 2.482564",\ + "0.044392, 0.306804, 0.637876, 1.251459, 2.482564",\ + "0.056346, 0.310032, 0.637981, 1.251459, 2.482564",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.189618, 0.389436, 0.761051, 1.504280",\ + "0.026989, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.027967, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.029933, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.048080, 0.193656, 0.389937, 0.761051, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.250220, 2.473548",\ + "0.031840, 0.304583, 0.637840, 1.250220, 2.473548",\ + "0.044392, 0.306804, 0.637876, 1.250296, 2.473548",\ + "0.056346, 0.310032, 0.637981, 1.251042, 2.473548",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.027967, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.029933, 0.189417, 0.388385, 0.759721, 1.502395",\ + "0.048080, 0.193656, 0.388460, 0.760493, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217652, 0.171723, 0.141523, 0.130179, 0.143864",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251704, 0.176383, 0.108224, 0.085257, 0.148171",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149579, -0.107162, -0.072675, -0.033251, 0.272796",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164860, -0.098945, -0.041286, 0.000675, 0.221283",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[1]_hldr*/ + +} /* end of pin dpram_rmf_o[1] */ + +pin("dpram_rmf_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002026 ; + + /* Other user defined attributes. */ + original_pin : dpram_rmf_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\ + "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\ + "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\ + "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\ + "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.046348, 0.191554, 0.388300, 0.759979, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\ + "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\ + "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\ + "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\ + "0.046348, 0.191554, 0.386818, 0.759420, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rmf_o[0]_hldr*/ + +} /* end of pin dpram_rmf_o[0] */ +} /* end of bus dpram_rmf_o */ +bus ( dpram_rml_o ) { + + bus_type : BUS10_type8 ; + direction : output ; + +pin("dpram_rml_o[9]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003142 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[9]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.051240, 0.203496, 0.378292, 0.700476, 1.344843",\ + "0.137724, 0.290671, 0.465395, 0.787189, 1.430777",\ + "0.221682, 0.378796, 0.553349, 0.874810, 1.517732",\ + "0.280355, 0.443186, 0.617463, 0.938722, 1.581241",\ + "0.584942, 0.793069, 0.967839, 1.287458, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.028205, 0.304109, 0.636312, 1.251729, 2.482563",\ + "0.032295, 0.305121, 0.638243, 1.251729, 2.482563",\ + "0.044791, 0.307337, 0.638279, 1.251729, 2.482563",\ + "0.056753, 0.310558, 0.638384, 1.251729, 2.482563",\ + "0.133215, 0.348353, 0.644623, 1.254264, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.070508, 0.174340, 0.285412, 0.489165, 0.896671",\ + "0.157911, 0.261657, 0.372693, 0.576470, 0.984024",\ + "0.238313, 0.341986, 0.452720, 0.656498, 1.064056",\ + "0.295115, 0.399536, 0.510261, 0.713742, 1.120703",\ + "0.590063, 0.702880, 0.813890, 1.016754, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.027336, 0.189933, 0.389674, 0.761207, 1.504274",\ + "0.027336, 0.190085, 0.390175, 0.761207, 1.504274",\ + "0.028299, 0.190085, 0.390175, 0.761207, 1.504274",\ + "0.030250, 0.190085, 0.390175, 0.761207, 1.504274",\ + "0.048330, 0.193960, 0.390175, 0.761207, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.051240, 0.203496, 0.378292, 0.700476, 1.344843",\ + "0.137724, 0.290671, 0.465395, 0.787189, 1.430777",\ + "0.221682, 0.378796, 0.553349, 0.874810, 1.517732",\ + "0.280355, 0.443186, 0.617463, 0.938722, 1.581241",\ + "0.584942, 0.793069, 0.967839, 1.287458, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.028205, 0.304109, 0.636312, 1.250489, 2.473548",\ + "0.032295, 0.305121, 0.638243, 1.250489, 2.473548",\ + "0.044791, 0.307337, 0.638279, 1.250564, 2.473548",\ + "0.056753, 0.310558, 0.638384, 1.251310, 2.473548",\ + "0.133215, 0.348353, 0.644623, 1.254264, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.070508, 0.174340, 0.285412, 0.489165, 0.896671",\ + "0.157911, 0.261657, 0.372693, 0.576470, 0.984024",\ + "0.238313, 0.341986, 0.452720, 0.656498, 1.064056",\ + "0.295115, 0.399536, 0.510261, 0.713742, 1.120703",\ + "0.590063, 0.702880, 0.813890, 1.016754, 1.422480"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003142, 0.076141, 0.162859, 0.322576, 0.642011"); + values ( "0.027336, 0.189123, 0.388163, 0.758974, 1.500597",\ + "0.027336, 0.189123, 0.388163, 0.758974, 1.500597",\ + "0.028299, 0.189123, 0.388163, 0.758974, 1.500597",\ + "0.030250, 0.189730, 0.388622, 0.759878, 1.502388",\ + "0.048330, 0.193960, 0.388698, 0.760650, 1.504554"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028205, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217887, 0.171958, 0.141759, 0.130415, 0.144100",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027336, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251862, 0.176541, 0.108382, 0.085415, 0.148328",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028205, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149814, -0.107397, -0.072910, -0.033487, 0.272560",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027336, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.165018, -0.099103, -0.041444, 0.000517, 0.221125",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[9]_hldr*/ + +} /* end of pin dpram_rml_o[9] */ + +pin("dpram_rml_o[8]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002583 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[8]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.049728, 0.202370, 0.377446, 0.699912, 1.344843",\ + "0.136129, 0.289544, 0.464550, 0.786626, 1.430777",\ + "0.219715, 0.377671, 0.552505, 0.874247, 1.517732",\ + "0.278013, 0.442063, 0.616620, 0.938160, 1.581241",\ + "0.580334, 0.791940, 0.967000, 1.286899, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.026175, 0.301972, 0.634697, 1.250652, 2.482564",\ + "0.030477, 0.302972, 0.636635, 1.250652, 2.482564",\ + "0.043197, 0.305208, 0.636672, 1.250652, 2.482564",\ + "0.055131, 0.308457, 0.636775, 1.250652, 2.482564",\ + "0.131181, 0.346526, 0.643023, 1.253198, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.069162, 0.173635, 0.284889, 0.488820, 0.896683",\ + "0.156569, 0.260953, 0.372170, 0.576125, 0.984036",\ + "0.236950, 0.341284, 0.452197, 0.656154, 1.064068",\ + "0.293698, 0.398833, 0.509739, 0.713398, 1.120715",\ + "0.588084, 0.702174, 0.813370, 1.016411, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.025948, 0.188671, 0.388720, 0.760579, 1.504295",\ + "0.025948, 0.188820, 0.389223, 0.760579, 1.504295",\ + "0.026971, 0.188820, 0.389223, 0.760579, 1.504295",\ + "0.028981, 0.188820, 0.389223, 0.760579, 1.504295",\ + "0.047327, 0.192742, 0.389223, 0.760579, 1.504576"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.049728, 0.202370, 0.377446, 0.699912, 1.344843",\ + "0.136129, 0.289544, 0.464550, 0.786626, 1.430777",\ + "0.219715, 0.377671, 0.552505, 0.874247, 1.517732",\ + "0.278013, 0.442063, 0.616620, 0.938160, 1.581241",\ + "0.580334, 0.791940, 0.967000, 1.286899, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.026175, 0.301972, 0.634697, 1.249417, 2.473548",\ + "0.030477, 0.302972, 0.636635, 1.249417, 2.473548",\ + "0.043197, 0.305208, 0.636672, 1.249493, 2.473548",\ + "0.055131, 0.308457, 0.636775, 1.250238, 2.473548",\ + "0.131181, 0.346526, 0.643023, 1.253198, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.069162, 0.173635, 0.284889, 0.488820, 0.896683",\ + "0.156569, 0.260953, 0.372170, 0.576125, 0.984036",\ + "0.236950, 0.341284, 0.452197, 0.656154, 1.064068",\ + "0.293698, 0.398833, 0.509739, 0.713398, 1.120715",\ + "0.588084, 0.702174, 0.813370, 1.016411, 1.422492"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002583, 0.075582, 0.162440, 0.322297, 0.642011"); + values ( "0.025948, 0.187867, 0.387212, 0.758347, 1.500618",\ + "0.025948, 0.187867, 0.387212, 0.758347, 1.500618",\ + "0.026971, 0.187867, 0.387212, 0.758347, 1.500618",\ + "0.028981, 0.188476, 0.387670, 0.759250, 1.502410",\ + "0.047327, 0.192742, 0.387744, 0.760021, 1.504576"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026175, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216947, 0.171018, 0.140819, 0.129475, 0.143160",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025948, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251230, 0.175909, 0.107750, 0.084782, 0.147696",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026175, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148875, -0.106458, -0.071971, -0.032547, 0.273500",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025948, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164386, -0.098471, -0.040812, 0.001149, 0.221757",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[8]_hldr*/ + +} /* end of pin dpram_rml_o[8] */ + +pin("dpram_rml_o[7]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002594 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[7]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.049757, 0.202391, 0.377463, 0.699923, 1.344843",\ + "0.136160, 0.289566, 0.464567, 0.786637, 1.430777",\ + "0.219753, 0.377693, 0.552521, 0.874258, 1.517732",\ + "0.278058, 0.442085, 0.616637, 0.938171, 1.581241",\ + "0.580424, 0.791962, 0.967016, 1.286910, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.026215, 0.302013, 0.634728, 1.250673, 2.482563",\ + "0.030513, 0.303014, 0.636667, 1.250673, 2.482563",\ + "0.043228, 0.305249, 0.636703, 1.250673, 2.482563",\ + "0.055162, 0.308498, 0.636806, 1.250673, 2.482563",\ + "0.131221, 0.346562, 0.643054, 1.253218, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.069192, 0.173650, 0.284901, 0.488829, 0.896685",\ + "0.156600, 0.260968, 0.372182, 0.576134, 0.984038",\ + "0.236980, 0.341300, 0.452209, 0.656163, 1.064070",\ + "0.293730, 0.398849, 0.509751, 0.713407, 1.120717",\ + "0.588129, 0.702190, 0.813382, 1.016419, 1.422494"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.025979, 0.188700, 0.388743, 0.760595, 1.504299",\ + "0.025979, 0.188849, 0.389245, 0.760595, 1.504299",\ + "0.027001, 0.188849, 0.389245, 0.760595, 1.504299",\ + "0.029010, 0.188849, 0.389245, 0.760595, 1.504299",\ + "0.047350, 0.192770, 0.389245, 0.760595, 1.504579"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.049757, 0.202391, 0.377463, 0.699923, 1.344843",\ + "0.136160, 0.289566, 0.464567, 0.786637, 1.430777",\ + "0.219753, 0.377693, 0.552521, 0.874258, 1.517732",\ + "0.278058, 0.442085, 0.616637, 0.938171, 1.581241",\ + "0.580424, 0.791962, 0.967016, 1.286910, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.026215, 0.302013, 0.634728, 1.249438, 2.473548",\ + "0.030513, 0.303014, 0.636667, 1.249438, 2.473548",\ + "0.043228, 0.305249, 0.636703, 1.249514, 2.473548",\ + "0.055162, 0.308498, 0.636806, 1.250259, 2.473548",\ + "0.131221, 0.346562, 0.643054, 1.253218, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.069192, 0.173650, 0.284901, 0.488829, 0.896685",\ + "0.156600, 0.260968, 0.372182, 0.576134, 0.984038",\ + "0.236980, 0.341300, 0.452209, 0.656163, 1.064070",\ + "0.293730, 0.398849, 0.509751, 0.713407, 1.120717",\ + "0.588129, 0.702190, 0.813382, 1.016419, 1.422494"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002594, 0.075593, 0.162448, 0.322302, 0.642011"); + values ( "0.025979, 0.187895, 0.387234, 0.758363, 1.500622",\ + "0.025979, 0.187895, 0.387234, 0.758363, 1.500622",\ + "0.027001, 0.187895, 0.387234, 0.758363, 1.500622",\ + "0.029010, 0.188504, 0.387692, 0.759266, 1.502414",\ + "0.047350, 0.192770, 0.387766, 0.760037, 1.504579"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026215, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216966, 0.171037, 0.140837, 0.129493, 0.143178",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025979, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251244, 0.175923, 0.107764, 0.084797, 0.147711",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026215, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148893, -0.106476, -0.071989, -0.032565, 0.273482",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025979, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164400, -0.098485, -0.040826, 0.001135, 0.221743",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[7]_hldr*/ + +} /* end of pin dpram_rml_o[7] */ + +pin("dpram_rml_o[6]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002460 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[6]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.049394, 0.202121, 0.377259, 0.699787, 1.344843",\ + "0.135777, 0.289295, 0.464364, 0.786501, 1.430777",\ + "0.219280, 0.377422, 0.552318, 0.874123, 1.517732",\ + "0.277495, 0.441815, 0.616434, 0.938036, 1.581241",\ + "0.579315, 0.791690, 0.966814, 1.286775, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.025727, 0.301499, 0.634339, 1.250414, 2.482564",\ + "0.030075, 0.302497, 0.636280, 1.250414, 2.482564",\ + "0.042844, 0.304737, 0.636316, 1.250414, 2.482564",\ + "0.054772, 0.307992, 0.636419, 1.250414, 2.482564",\ + "0.130732, 0.346122, 0.642669, 1.252962, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.068872, 0.173483, 0.284777, 0.488748, 0.896689",\ + "0.156281, 0.260801, 0.372058, 0.576053, 0.984043",\ + "0.236656, 0.341133, 0.452085, 0.656082, 1.064075",\ + "0.293393, 0.398682, 0.509628, 0.713326, 1.120722",\ + "0.587658, 0.702023, 0.813259, 1.016339, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.025649, 0.188400, 0.388517, 0.760448, 1.504308",\ + "0.025649, 0.188548, 0.389020, 0.760448, 1.504308",\ + "0.026685, 0.188548, 0.389020, 0.760448, 1.504308",\ + "0.028708, 0.188548, 0.389020, 0.760448, 1.504308",\ + "0.047111, 0.192480, 0.389020, 0.760448, 1.504588"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.049394, 0.202121, 0.377259, 0.699787, 1.344843",\ + "0.135777, 0.289295, 0.464364, 0.786501, 1.430777",\ + "0.219280, 0.377422, 0.552318, 0.874123, 1.517732",\ + "0.277495, 0.441815, 0.616434, 0.938036, 1.581241",\ + "0.579315, 0.791690, 0.966814, 1.286775, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.025727, 0.301499, 0.634339, 1.249181, 2.473548",\ + "0.030075, 0.302497, 0.636280, 1.249181, 2.473548",\ + "0.042844, 0.304737, 0.636316, 1.249256, 2.473548",\ + "0.054772, 0.307992, 0.636419, 1.250001, 2.473548",\ + "0.130732, 0.346122, 0.642669, 1.252962, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.068872, 0.173483, 0.284777, 0.488748, 0.896689",\ + "0.156281, 0.260801, 0.372058, 0.576053, 0.984043",\ + "0.236656, 0.341133, 0.452085, 0.656082, 1.064075",\ + "0.293393, 0.398682, 0.509628, 0.713326, 1.120722",\ + "0.587658, 0.702023, 0.813259, 1.016339, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002460, 0.075458, 0.162347, 0.322235, 0.642011"); + values ( "0.025649, 0.187597, 0.387009, 0.758216, 1.500631",\ + "0.025649, 0.187597, 0.387009, 0.758216, 1.500631",\ + "0.026685, 0.187597, 0.387009, 0.758216, 1.500631",\ + "0.028708, 0.188206, 0.387467, 0.759119, 1.502422",\ + "0.047111, 0.192480, 0.387540, 0.759889, 1.504588"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025727, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216740, 0.170811, 0.140611, 0.129267, 0.142952",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025649, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251094, 0.175772, 0.107614, 0.084646, 0.147560",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025727, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148667, -0.106250, -0.071763, -0.032339, 0.273708",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025649, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164250, -0.098335, -0.040676, 0.001285, 0.221893",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[6]_hldr*/ + +} /* end of pin dpram_rml_o[6] */ + +pin("dpram_rml_o[5]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002976 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[5]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.050791, 0.203162, 0.378041, 0.700308, 1.344843",\ + "0.137251, 0.290336, 0.465144, 0.787022, 1.430777",\ + "0.221098, 0.378462, 0.553098, 0.874643, 1.517732",\ + "0.279660, 0.442853, 0.617213, 0.938556, 1.581241",\ + "0.583574, 0.792734, 0.967589, 1.287292, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.027602, 0.303474, 0.635832, 1.251409, 2.482564",\ + "0.031755, 0.304483, 0.637765, 1.251409, 2.482564",\ + "0.044318, 0.306705, 0.637801, 1.251409, 2.482564",\ + "0.056271, 0.309934, 0.637906, 1.251409, 2.482564",\ + "0.132611, 0.347810, 0.644148, 1.253948, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.070108, 0.174130, 0.285256, 0.489062, 0.896674",\ + "0.157512, 0.261448, 0.372537, 0.576367, 0.984027",\ + "0.237907, 0.341777, 0.452564, 0.656396, 1.064059",\ + "0.294694, 0.399327, 0.510106, 0.713639, 1.120707",\ + "0.589475, 0.702670, 0.813735, 1.016652, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.026923, 0.189558, 0.389390, 0.761020, 1.504280",\ + "0.026923, 0.189709, 0.389892, 0.761020, 1.504280",\ + "0.027904, 0.189709, 0.389892, 0.761020, 1.504280",\ + "0.029873, 0.189709, 0.389892, 0.761020, 1.504280",\ + "0.048032, 0.193598, 0.389892, 0.761020, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.050791, 0.203162, 0.378041, 0.700308, 1.344843",\ + "0.137251, 0.290336, 0.465144, 0.787022, 1.430777",\ + "0.221098, 0.378462, 0.553098, 0.874643, 1.517732",\ + "0.279660, 0.442853, 0.617213, 0.938556, 1.581241",\ + "0.583574, 0.792734, 0.967589, 1.287292, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.027602, 0.303474, 0.635832, 1.250171, 2.473548",\ + "0.031755, 0.304483, 0.637765, 1.250171, 2.473548",\ + "0.044318, 0.306705, 0.637801, 1.250246, 2.473548",\ + "0.056271, 0.309934, 0.637906, 1.250992, 2.473548",\ + "0.132611, 0.347810, 0.644148, 1.253948, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.070108, 0.174130, 0.285256, 0.489062, 0.896674",\ + "0.157512, 0.261448, 0.372537, 0.576367, 0.984027",\ + "0.237907, 0.341777, 0.452564, 0.656396, 1.064059",\ + "0.294694, 0.399327, 0.510106, 0.713639, 1.120707",\ + "0.589475, 0.702670, 0.813735, 1.016652, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002976, 0.075975, 0.162735, 0.322493, 0.642011"); + values ( "0.026923, 0.188750, 0.387880, 0.758788, 1.500602",\ + "0.026923, 0.188750, 0.387880, 0.758788, 1.500602",\ + "0.027904, 0.188750, 0.387880, 0.758788, 1.500602",\ + "0.029873, 0.189357, 0.388339, 0.759691, 1.502394",\ + "0.048032, 0.193598, 0.388414, 0.760463, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027602, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217608, 0.171679, 0.141479, 0.130136, 0.143821",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026923, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251674, 0.176353, 0.108194, 0.085227, 0.148140",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027602, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149535, -0.107118, -0.072631, -0.033208, 0.272839",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026923, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164830, -0.098915, -0.041256, 0.000705, 0.221313",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[5]_hldr*/ + +} /* end of pin dpram_rml_o[5] */ + +pin("dpram_rml_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.004037 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\ + "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\ + "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\ + "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\ + "0.592316, 0.794877, 0.969181, 1.288353, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.031452, 0.307528, 0.638897, 1.253452, 2.482564",\ + "0.035203, 0.308560, 0.640814, 1.253452, 2.482564",\ + "0.047343, 0.310745, 0.640850, 1.253452, 2.482564",\ + "0.059348, 0.313921, 0.640958, 1.253452, 2.482564",\ + "0.136469, 0.351276, 0.647183, 1.255971, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\ + "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\ + "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\ + "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\ + "0.593185, 0.703993, 0.814708, 1.017287, 1.422446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.029527, 0.191922, 0.391170, 0.762184, 1.504210",\ + "0.029527, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.030394, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.032251, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.049913, 0.195880, 0.391669, 0.762184, 1.504490"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\ + "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\ + "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\ + "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\ + "0.592316, 0.794877, 0.969181, 1.288353, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.031452, 0.307528, 0.638897, 1.252203, 2.473548",\ + "0.035203, 0.308560, 0.640814, 1.252203, 2.473548",\ + "0.047343, 0.310745, 0.640850, 1.252279, 2.473548",\ + "0.059348, 0.313921, 0.640958, 1.253027, 2.473548",\ + "0.136469, 0.351276, 0.647183, 1.255971, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\ + "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\ + "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\ + "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\ + "0.593185, 0.703993, 0.814708, 1.017287, 1.422446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.030394, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.032251, 0.191709, 0.390118, 0.760853, 1.502324",\ + "0.049913, 0.195880, 0.390196, 0.761627, 1.504490"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.219390, 0.173461, 0.143262, 0.131918, 0.145603",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252859, 0.177538, 0.109379, 0.086412, 0.149326",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.151318, -0.108901, -0.074414, -0.034990, 0.271057",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.166015, -0.100100, -0.042441, -0.000480, 0.220128",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[4]_hldr*/ + +} /* end of pin dpram_rml_o[4] */ + +pin("dpram_rml_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002031 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\ + "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\ + "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\ + "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\ + "0.575781, 0.790824, 0.966170, 1.286346, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024170, 0.299860, 0.633100, 1.249588, 2.482563",\ + "0.028681, 0.300849, 0.635047, 1.249588, 2.482563",\ + "0.041621, 0.303103, 0.635083, 1.249588, 2.482563",\ + "0.053528, 0.306381, 0.635185, 1.249588, 2.482563",\ + "0.129172, 0.344721, 0.641441, 1.252143, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\ + "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\ + "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\ + "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\ + "0.586178, 0.701495, 0.812873, 1.016089, 1.422521"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024610, 0.187457, 0.387810, 0.759990, 1.504349",\ + "0.024610, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.025692, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.027759, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.046361, 0.191570, 0.388314, 0.759990, 1.504629"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\ + "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\ + "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\ + "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\ + "0.575781, 0.790824, 0.966170, 1.286346, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024170, 0.299860, 0.633100, 1.248359, 2.473548",\ + "0.028681, 0.300849, 0.635047, 1.248359, 2.473548",\ + "0.041621, 0.303103, 0.635083, 1.248434, 2.473548",\ + "0.053528, 0.306381, 0.635185, 1.249178, 2.473548",\ + "0.129172, 0.344721, 0.641441, 1.252143, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\ + "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\ + "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\ + "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\ + "0.586178, 0.701495, 0.812873, 1.016089, 1.422521"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.025692, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.027759, 0.187268, 0.386760, 0.758661, 1.502463",\ + "0.046361, 0.191570, 0.386832, 0.759431, 1.504629"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216019, 0.170090, 0.139890, 0.128547, 0.142232",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250621, 0.175300, 0.107141, 0.084173, 0.147087",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147946, -0.105529, -0.071042, -0.031619, 0.274428",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163777, -0.097862, -0.040203, 0.001758, 0.222366",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[3]_hldr*/ + +} /* end of pin dpram_rml_o[3] */ + +pin("dpram_rml_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003654 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\ + "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\ + "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\ + "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\ + "0.589159, 0.794103, 0.968606, 1.287970, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.030062, 0.306064, 0.637790, 1.252714, 2.482564",\ + "0.033958, 0.307087, 0.639713, 1.252714, 2.482564",\ + "0.046250, 0.309286, 0.639749, 1.252714, 2.482564",\ + "0.058237, 0.312481, 0.639856, 1.252714, 2.482564",\ + "0.135075, 0.350024, 0.646087, 1.255240, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\ + "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\ + "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\ + "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\ + "0.591837, 0.703513, 0.814354, 1.017055, 1.422457"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.028581, 0.191064, 0.390523, 0.761759, 1.504230",\ + "0.028581, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.029490, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.031388, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.049229, 0.195051, 0.391022, 0.761759, 1.504510"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\ + "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\ + "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\ + "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\ + "0.589159, 0.794103, 0.968606, 1.287970, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.030062, 0.306064, 0.637790, 1.251469, 2.473548",\ + "0.033958, 0.307087, 0.639713, 1.251469, 2.473548",\ + "0.046250, 0.309286, 0.639749, 1.251544, 2.473548",\ + "0.058237, 0.312481, 0.639856, 1.252292, 2.473548",\ + "0.135075, 0.350024, 0.646087, 1.255240, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\ + "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\ + "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\ + "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\ + "0.591837, 0.703513, 0.814354, 1.017055, 1.422457"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.029490, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.031388, 0.190855, 0.389471, 0.760429, 1.502345",\ + "0.049229, 0.195051, 0.389548, 0.761202, 1.504510"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.218747, 0.172818, 0.142618, 0.131274, 0.144959",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252429, 0.177108, 0.108949, 0.085981, 0.148895",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.150674, -0.108257, -0.073770, -0.034347, 0.271701",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.165584, -0.099669, -0.042010, -0.000049, 0.220558",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[2]_hldr*/ + +} /* end of pin dpram_rml_o[2] */ + +pin("dpram_rml_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002005 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\ + "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\ + "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\ + "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\ + "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.046319, 0.191519, 0.388276, 0.759966, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\ + "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\ + "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\ + "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\ + "0.046319, 0.191519, 0.386794, 0.759408, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[1]_hldr*/ + +} /* end of pin dpram_rml_o[1] */ + +pin("dpram_rml_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002547 ; + + /* Other user defined attributes. */ + original_pin : dpram_rml_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\ + "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\ + "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\ + "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\ + "0.580033, 0.791866, 0.966945, 1.286862, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.026043, 0.301832, 0.634591, 1.250582, 2.482563",\ + "0.030358, 0.302831, 0.636530, 1.250582, 2.482563",\ + "0.043092, 0.305068, 0.636566, 1.250582, 2.482563",\ + "0.055024, 0.308320, 0.636670, 1.250582, 2.482563",\ + "0.131048, 0.346407, 0.642918, 1.253128, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\ + "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\ + "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\ + "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\ + "0.587968, 0.702133, 0.813340, 1.016393, 1.422498"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.025866, 0.188597, 0.388667, 0.760546, 1.504306",\ + "0.025866, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.026893, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.028907, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.047268, 0.192671, 0.389169, 0.760546, 1.504586"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\ + "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\ + "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\ + "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\ + "0.580033, 0.791866, 0.966945, 1.286862, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.026043, 0.301832, 0.634591, 1.249347, 2.473548",\ + "0.030358, 0.302831, 0.636530, 1.249347, 2.473548",\ + "0.043092, 0.305068, 0.636566, 1.249423, 2.473548",\ + "0.055024, 0.308320, 0.636670, 1.250168, 2.473548",\ + "0.131048, 0.346407, 0.642918, 1.253128, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\ + "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\ + "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\ + "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\ + "0.587968, 0.702133, 0.813340, 1.016393, 1.422498"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.026893, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.028907, 0.188402, 0.387616, 0.759217, 1.502420",\ + "0.047268, 0.192671, 0.387690, 0.759988, 1.504586"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216886, 0.170957, 0.140757, 0.129414, 0.143099",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251193, 0.175871, 0.107712, 0.084745, 0.147659",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148813, -0.106396, -0.071909, -0.032486, 0.273561",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164349, -0.098434, -0.040775, 0.001186, 0.221794",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_dpram_rml_o[0]_hldr*/ + +} /* end of pin dpram_rml_o[0] */ +} /* end of bus dpram_rml_o */ +bus ( spram_rm_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("spram_rm_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002015 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\ + "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\ + "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\ + "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\ + "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.046336, 0.191539, 0.388291, 0.759976, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\ + "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\ + "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\ + "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\ + "0.046336, 0.191539, 0.386809, 0.759417, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[4]_hldr*/ + +} /* end of pin spram_rm_o[4] */ + +pin("spram_rm_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002005 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\ + "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\ + "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\ + "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\ + "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.046319, 0.191519, 0.388276, 0.759966, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\ + "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\ + "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\ + "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\ + "0.046319, 0.191519, 0.386794, 0.759408, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[3]_hldr*/ + +} /* end of pin spram_rm_o[3] */ + +pin("spram_rm_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002015 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.249558, 2.482564",\ + "0.028631, 0.300789, 0.635003, 1.249558, 2.482564",\ + "0.041577, 0.303044, 0.635039, 1.249558, 2.482564",\ + "0.053483, 0.306322, 0.635141, 1.249558, 2.482564",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.187425, 0.387787, 0.759976, 1.504353",\ + "0.024575, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.025658, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.027727, 0.187570, 0.388291, 0.759976, 1.504353",\ + "0.046336, 0.191539, 0.388291, 0.759976, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.048192, 0.201225, 0.376587, 0.699339, 1.344843",\ + "0.134509, 0.288400, 0.463692, 0.786054, 1.430777",\ + "0.217716, 0.376528, 0.551648, 0.873676, 1.517732",\ + "0.275633, 0.440922, 0.615763, 0.937589, 1.581241",\ + "0.575653, 0.790792, 0.966147, 1.286330, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024114, 0.299801, 0.633056, 1.248329, 2.473548",\ + "0.028631, 0.300789, 0.635003, 1.248329, 2.473548",\ + "0.041577, 0.303044, 0.635039, 1.248404, 2.473548",\ + "0.053483, 0.306322, 0.635141, 1.249148, 2.473548",\ + "0.129115, 0.344671, 0.641397, 1.252114, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.067832, 0.172938, 0.284377, 0.488489, 0.896714",\ + "0.155243, 0.260256, 0.371658, 0.575794, 0.984068",\ + "0.235603, 0.340590, 0.451685, 0.655823, 1.064099",\ + "0.292298, 0.398139, 0.509228, 0.713068, 1.120747",\ + "0.586128, 0.701477, 0.812860, 1.016081, 1.422524"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002015, 0.075014, 0.162014, 0.322013, 0.642011"); + values ( "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.024575, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.025658, 0.186626, 0.386280, 0.757745, 1.500676",\ + "0.027727, 0.187236, 0.386737, 0.758647, 1.502467",\ + "0.046336, 0.191539, 0.386809, 0.759417, 1.504633"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215993, 0.170064, 0.139864, 0.128520, 0.142206",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250605, 0.175284, 0.107125, 0.084158, 0.147071",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024114, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147920, -0.105503, -0.071016, -0.031593, 0.274454",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024575, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163761, -0.097846, -0.040187, 0.001774, 0.222382",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[2]_hldr*/ + +} /* end of pin spram_rm_o[2] */ + +pin("spram_rm_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003002 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.251459, 2.482564",\ + "0.031840, 0.304583, 0.637840, 1.251459, 2.482564",\ + "0.044392, 0.306804, 0.637876, 1.251459, 2.482564",\ + "0.056346, 0.310032, 0.637981, 1.251459, 2.482564",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.189618, 0.389436, 0.761051, 1.504280",\ + "0.026989, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.027967, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.029933, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.048080, 0.193656, 0.389937, 0.761051, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.250220, 2.473548",\ + "0.031840, 0.304583, 0.637840, 1.250220, 2.473548",\ + "0.044392, 0.306804, 0.637876, 1.250296, 2.473548",\ + "0.056346, 0.310032, 0.637981, 1.251042, 2.473548",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.027967, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.029933, 0.189417, 0.388385, 0.759721, 1.502395",\ + "0.048080, 0.193656, 0.388460, 0.760493, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217652, 0.171723, 0.141523, 0.130179, 0.143864",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251704, 0.176383, 0.108224, 0.085257, 0.148171",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149579, -0.107162, -0.072675, -0.033251, 0.272796",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164860, -0.098945, -0.041286, 0.000675, 0.221283",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[1]_hldr*/ + +} /* end of pin spram_rm_o[1] */ + +pin("spram_rm_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002026 ; + + /* Other user defined attributes. */ + original_pin : spram_rm_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\ + "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\ + "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\ + "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\ + "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.046348, 0.191554, 0.388300, 0.759979, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\ + "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\ + "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\ + "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\ + "0.046348, 0.191554, 0.386818, 0.759420, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_spram_rm_o[0]_hldr*/ + +} /* end of pin spram_rm_o[0] */ +} /* end of bus spram_rm_o */ +bus ( sprgf_rm_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("sprgf_rm_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.004037 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\ + "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\ + "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\ + "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\ + "0.592316, 0.794877, 0.969181, 1.288353, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.031452, 0.307528, 0.638897, 1.253452, 2.482564",\ + "0.035203, 0.308560, 0.640814, 1.253452, 2.482564",\ + "0.047343, 0.310745, 0.640850, 1.253452, 2.482564",\ + "0.059348, 0.313921, 0.640958, 1.253452, 2.482564",\ + "0.136469, 0.351276, 0.647183, 1.255971, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\ + "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\ + "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\ + "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\ + "0.593185, 0.703993, 0.814708, 1.017287, 1.422446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.029527, 0.191922, 0.391170, 0.762184, 1.504210",\ + "0.029527, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.030394, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.032251, 0.192081, 0.391669, 0.762184, 1.504210",\ + "0.049913, 0.195880, 0.391669, 0.762184, 1.504490"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.053659, 0.205298, 0.379645, 0.701378, 1.344843",\ + "0.140277, 0.292473, 0.466747, 0.788090, 1.430777",\ + "0.224830, 0.380596, 0.554699, 0.875710, 1.517732",\ + "0.284103, 0.444983, 0.618813, 0.939622, 1.581241",\ + "0.592316, 0.794877, 0.969181, 1.288353, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.031452, 0.307528, 0.638897, 1.252203, 2.473548",\ + "0.035203, 0.308560, 0.640814, 1.252203, 2.473548",\ + "0.047343, 0.310745, 0.640850, 1.252279, 2.473548",\ + "0.059348, 0.313921, 0.640958, 1.253027, 2.473548",\ + "0.136469, 0.351276, 0.647183, 1.255971, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.072631, 0.175452, 0.286232, 0.489700, 0.896636",\ + "0.160028, 0.262769, 0.373513, 0.577005, 0.983989",\ + "0.240463, 0.343094, 0.453540, 0.657034, 1.064021",\ + "0.297350, 0.400643, 0.511081, 0.714277, 1.120669",\ + "0.593185, 0.703993, 0.814708, 1.017287, 1.422446"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004037, 0.077035, 0.163530, 0.323024, 0.642011"); + values ( "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.029527, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.030394, 0.191105, 0.389657, 0.759949, 1.500533",\ + "0.032251, 0.191709, 0.390118, 0.760853, 1.502324",\ + "0.049913, 0.195880, 0.390196, 0.761627, 1.504490"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.219390, 0.173461, 0.143262, 0.131918, 0.145603",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252859, 0.177538, 0.109379, 0.086412, 0.149326",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.031452, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.151318, -0.108901, -0.074414, -0.034990, 0.271057",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.029527, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.166015, -0.100100, -0.042441, -0.000480, 0.220128",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[4]_hldr*/ + +} /* end of pin sprgf_rm_o[4] */ + +pin("sprgf_rm_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002031 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\ + "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\ + "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\ + "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\ + "0.575781, 0.790824, 0.966170, 1.286346, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024170, 0.299860, 0.633100, 1.249588, 2.482563",\ + "0.028681, 0.300849, 0.635047, 1.249588, 2.482563",\ + "0.041621, 0.303103, 0.635083, 1.249588, 2.482563",\ + "0.053528, 0.306381, 0.635185, 1.249588, 2.482563",\ + "0.129172, 0.344721, 0.641441, 1.252143, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\ + "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\ + "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\ + "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\ + "0.586178, 0.701495, 0.812873, 1.016089, 1.422521"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024610, 0.187457, 0.387810, 0.759990, 1.504349",\ + "0.024610, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.025692, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.027759, 0.187602, 0.388314, 0.759990, 1.504349",\ + "0.046361, 0.191570, 0.388314, 0.759990, 1.504629"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.048234, 0.201257, 0.376611, 0.699355, 1.344843",\ + "0.134553, 0.288431, 0.463716, 0.786070, 1.430777",\ + "0.217771, 0.376559, 0.551671, 0.873691, 1.517732",\ + "0.275698, 0.440953, 0.615787, 0.937605, 1.581241",\ + "0.575781, 0.790824, 0.966170, 1.286346, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024170, 0.299860, 0.633100, 1.248359, 2.473548",\ + "0.028681, 0.300849, 0.635047, 1.248359, 2.473548",\ + "0.041621, 0.303103, 0.635083, 1.248434, 2.473548",\ + "0.053528, 0.306381, 0.635185, 1.249178, 2.473548",\ + "0.129172, 0.344721, 0.641441, 1.252143, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.067866, 0.172955, 0.284390, 0.488497, 0.896712",\ + "0.155277, 0.260274, 0.371670, 0.575802, 0.984065",\ + "0.235637, 0.340608, 0.451697, 0.655831, 1.064097",\ + "0.292333, 0.398157, 0.509240, 0.713075, 1.120745",\ + "0.586178, 0.701495, 0.812873, 1.016089, 1.422521"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002031, 0.075029, 0.162026, 0.322021, 0.642011"); + values ( "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.024610, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.025692, 0.186657, 0.386303, 0.757760, 1.500672",\ + "0.027759, 0.187268, 0.386760, 0.758661, 1.502463",\ + "0.046361, 0.191570, 0.386832, 0.759431, 1.504629"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216019, 0.170090, 0.139890, 0.128547, 0.142232",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250621, 0.175300, 0.107141, 0.084173, 0.147087",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024170, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147946, -0.105529, -0.071042, -0.031619, 0.274428",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024610, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163777, -0.097862, -0.040203, 0.001758, 0.222366",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[3]_hldr*/ + +} /* end of pin sprgf_rm_o[3] */ + +pin("sprgf_rm_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003654 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\ + "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\ + "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\ + "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\ + "0.589159, 0.794103, 0.968606, 1.287970, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.030062, 0.306064, 0.637790, 1.252714, 2.482564",\ + "0.033958, 0.307087, 0.639713, 1.252714, 2.482564",\ + "0.046250, 0.309286, 0.639749, 1.252714, 2.482564",\ + "0.058237, 0.312481, 0.639856, 1.252714, 2.482564",\ + "0.135075, 0.350024, 0.646087, 1.255240, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\ + "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\ + "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\ + "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\ + "0.591837, 0.703513, 0.814354, 1.017055, 1.422457"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.028581, 0.191064, 0.390523, 0.761759, 1.504230",\ + "0.028581, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.029490, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.031388, 0.191220, 0.391022, 0.761759, 1.504230",\ + "0.049229, 0.195051, 0.391022, 0.761759, 1.504510"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.052623, 0.204527, 0.379066, 0.700992, 1.344843",\ + "0.139184, 0.291701, 0.466168, 0.787704, 1.430777",\ + "0.223482, 0.379826, 0.554121, 0.875325, 1.517732",\ + "0.282499, 0.444214, 0.618235, 0.939237, 1.581241",\ + "0.589159, 0.794103, 0.968606, 1.287970, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.030062, 0.306064, 0.637790, 1.251469, 2.473548",\ + "0.033958, 0.307087, 0.639713, 1.251469, 2.473548",\ + "0.046250, 0.309286, 0.639749, 1.251544, 2.473548",\ + "0.058237, 0.312481, 0.639856, 1.252292, 2.473548",\ + "0.135075, 0.350024, 0.646087, 1.255240, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.071715, 0.174972, 0.285877, 0.489467, 0.896647",\ + "0.159114, 0.262289, 0.373158, 0.576772, 0.984000",\ + "0.239535, 0.342616, 0.453185, 0.656801, 1.064032",\ + "0.296386, 0.400165, 0.510726, 0.714044, 1.120680",\ + "0.591837, 0.703513, 0.814354, 1.017055, 1.422457"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003654, 0.076652, 0.163243, 0.322832, 0.642011"); + values ( "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.028581, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.029490, 0.190249, 0.389010, 0.759525, 1.500553",\ + "0.031388, 0.190855, 0.389471, 0.760429, 1.502345",\ + "0.049229, 0.195051, 0.389548, 0.761202, 1.504510"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.218747, 0.172818, 0.142618, 0.131274, 0.144959",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.252429, 0.177108, 0.108949, 0.085981, 0.148895",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030062, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.150674, -0.108257, -0.073770, -0.034347, 0.271701",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.028581, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.165584, -0.099669, -0.042010, -0.000049, 0.220558",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[2]_hldr*/ + +} /* end of pin sprgf_rm_o[2] */ + +pin("sprgf_rm_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002005 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.249539, 2.482564",\ + "0.028598, 0.300750, 0.634974, 1.249539, 2.482564",\ + "0.041548, 0.303005, 0.635010, 1.249539, 2.482564",\ + "0.053453, 0.306284, 0.635112, 1.249539, 2.482564",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.187404, 0.387772, 0.759966, 1.504356",\ + "0.024552, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.025636, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.027706, 0.187549, 0.388276, 0.759966, 1.504356",\ + "0.046319, 0.191519, 0.388276, 0.759966, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.048165, 0.201205, 0.376572, 0.699329, 1.344843",\ + "0.134480, 0.288380, 0.463677, 0.786044, 1.430777",\ + "0.217680, 0.376507, 0.551633, 0.873666, 1.517732",\ + "0.275590, 0.440902, 0.615748, 0.937579, 1.581241",\ + "0.575569, 0.790772, 0.966132, 1.286320, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024077, 0.299762, 0.633026, 1.248310, 2.473548",\ + "0.028598, 0.300750, 0.634974, 1.248310, 2.473548",\ + "0.041548, 0.303005, 0.635010, 1.248385, 2.473548",\ + "0.053453, 0.306284, 0.635112, 1.249129, 2.473548",\ + "0.129078, 0.344637, 0.641368, 1.252094, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.067810, 0.172926, 0.284369, 0.488484, 0.896715",\ + "0.155221, 0.260244, 0.371649, 0.575789, 0.984069",\ + "0.235580, 0.340579, 0.451676, 0.655818, 1.064101",\ + "0.292274, 0.398127, 0.509219, 0.713062, 1.120748",\ + "0.586096, 0.701465, 0.812852, 1.016076, 1.422525"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002005, 0.075004, 0.162007, 0.322008, 0.642011"); + values ( "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.024552, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.025636, 0.186605, 0.386265, 0.757736, 1.500678",\ + "0.027706, 0.187215, 0.386722, 0.758638, 1.502470",\ + "0.046319, 0.191519, 0.386794, 0.759408, 1.504636"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.215976, 0.170047, 0.139847, 0.128503, 0.142188",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250595, 0.175273, 0.107114, 0.084147, 0.147061",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024077, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147903, -0.105486, -0.070999, -0.031576, 0.274471",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024552, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163751, -0.097835, -0.040177, 0.001784, 0.222392",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[1]_hldr*/ + +} /* end of pin sprgf_rm_o[1] */ + +pin("sprgf_rm_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002547 ; + + /* Other user defined attributes. */ + original_pin : sprgf_rm_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\ + "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\ + "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\ + "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\ + "0.580033, 0.791866, 0.966945, 1.286862, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.026043, 0.301832, 0.634591, 1.250582, 2.482563",\ + "0.030358, 0.302831, 0.636530, 1.250582, 2.482563",\ + "0.043092, 0.305068, 0.636566, 1.250582, 2.482563",\ + "0.055024, 0.308320, 0.636670, 1.250582, 2.482563",\ + "0.131048, 0.346407, 0.642918, 1.253128, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\ + "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\ + "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\ + "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\ + "0.587968, 0.702133, 0.813340, 1.016393, 1.422498"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.025866, 0.188597, 0.388667, 0.760546, 1.504306",\ + "0.025866, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.026893, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.028907, 0.188746, 0.389169, 0.760546, 1.504306",\ + "0.047268, 0.192671, 0.389169, 0.760546, 1.504586"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.049629, 0.202296, 0.377391, 0.699875, 1.344843",\ + "0.136025, 0.289471, 0.464495, 0.786589, 1.430777",\ + "0.219586, 0.377597, 0.552450, 0.874211, 1.517732",\ + "0.277859, 0.441990, 0.616565, 0.938124, 1.581241",\ + "0.580033, 0.791866, 0.966945, 1.286862, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.026043, 0.301832, 0.634591, 1.249347, 2.473548",\ + "0.030358, 0.302831, 0.636530, 1.249347, 2.473548",\ + "0.043092, 0.305068, 0.636566, 1.249423, 2.473548",\ + "0.055024, 0.308320, 0.636670, 1.250168, 2.473548",\ + "0.131048, 0.346407, 0.642918, 1.253128, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.069083, 0.173593, 0.284859, 0.488802, 0.896688",\ + "0.156491, 0.260911, 0.372140, 0.576107, 0.984042",\ + "0.236870, 0.341243, 0.452167, 0.656136, 1.064073",\ + "0.293615, 0.398792, 0.509709, 0.713380, 1.120721",\ + "0.587968, 0.702133, 0.813340, 1.016393, 1.422498"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002547, 0.075545, 0.162413, 0.322279, 0.642011"); + values ( "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.025866, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.026893, 0.187793, 0.387158, 0.758315, 1.500628",\ + "0.028907, 0.188402, 0.387616, 0.759217, 1.502420",\ + "0.047268, 0.192671, 0.387690, 0.759988, 1.504586"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216886, 0.170957, 0.140757, 0.129414, 0.143099",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251193, 0.175871, 0.107712, 0.084745, 0.147659",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026043, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148813, -0.106396, -0.071909, -0.032486, 0.273561",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025866, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164349, -0.098434, -0.040775, 0.001186, 0.221794",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprgf_rm_o[0]_hldr*/ + +} /* end of pin sprgf_rm_o[0] */ +} /* end of bus sprgf_rm_o */ +bus ( sprom_rm_o ) { + + bus_type : BUS5_type4 ; + direction : output ; + +pin("sprom_rm_o[4]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003002 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[4]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.251459, 2.482564",\ + "0.031840, 0.304583, 0.637840, 1.251459, 2.482564",\ + "0.044392, 0.306804, 0.637876, 1.251459, 2.482564",\ + "0.056346, 0.310032, 0.637981, 1.251459, 2.482564",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.189618, 0.389436, 0.761051, 1.504280",\ + "0.026989, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.027967, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.029933, 0.189769, 0.389937, 0.761051, 1.504280",\ + "0.048080, 0.193656, 0.389937, 0.761051, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.050861, 0.203214, 0.378080, 0.700335, 1.344843",\ + "0.137325, 0.290388, 0.465183, 0.787048, 1.430777",\ + "0.221189, 0.378514, 0.553137, 0.874669, 1.517732",\ + "0.279768, 0.442905, 0.617252, 0.938582, 1.581241",\ + "0.583788, 0.792786, 0.967628, 1.287318, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.027696, 0.303573, 0.635907, 1.250220, 2.473548",\ + "0.031840, 0.304583, 0.637840, 1.250220, 2.473548",\ + "0.044392, 0.306804, 0.637876, 1.250296, 2.473548",\ + "0.056346, 0.310032, 0.637981, 1.251042, 2.473548",\ + "0.132705, 0.347895, 0.644222, 1.253997, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.070172, 0.174163, 0.285281, 0.489079, 0.896674",\ + "0.157576, 0.261481, 0.372562, 0.576384, 0.984028",\ + "0.237972, 0.341811, 0.452589, 0.656412, 1.064059",\ + "0.294761, 0.399360, 0.510131, 0.713656, 1.120707",\ + "0.589569, 0.702704, 0.813760, 1.016668, 1.422484"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003002, 0.076001, 0.162754, 0.322506, 0.642011"); + values ( "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.026989, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.027967, 0.188809, 0.387926, 0.758818, 1.500603",\ + "0.029933, 0.189417, 0.388385, 0.759721, 1.502395",\ + "0.048080, 0.193656, 0.388460, 0.760493, 1.504560"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.217652, 0.171723, 0.141523, 0.130179, 0.143864",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251704, 0.176383, 0.108224, 0.085257, 0.148171",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.027696, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.149579, -0.107162, -0.072675, -0.033251, 0.272796",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026989, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164860, -0.098945, -0.041286, 0.000675, 0.221283",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[4]_hldr*/ + +} /* end of pin sprom_rm_o[4] */ + +pin("sprom_rm_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002553 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.049647, 0.202309, 0.377401, 0.699882, 1.344843",\ + "0.136044, 0.289484, 0.464505, 0.786596, 1.430777",\ + "0.219609, 0.377611, 0.552460, 0.874217, 1.517732",\ + "0.277887, 0.442003, 0.616575, 0.938130, 1.581241",\ + "0.580088, 0.791879, 0.966955, 1.286869, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.026067, 0.301857, 0.634610, 1.250594, 2.482563",\ + "0.030380, 0.302857, 0.636549, 1.250594, 2.482563",\ + "0.043111, 0.305094, 0.636586, 1.250594, 2.482563",\ + "0.055044, 0.308345, 0.636689, 1.250594, 2.482563",\ + "0.131072, 0.346429, 0.642937, 1.253140, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.069111, 0.173607, 0.284871, 0.488812, 0.896694",\ + "0.156518, 0.260926, 0.372152, 0.576117, 0.984047",\ + "0.236897, 0.341257, 0.452179, 0.656146, 1.064079",\ + "0.293644, 0.398806, 0.509722, 0.713390, 1.120727",\ + "0.588008, 0.702147, 0.813352, 1.016403, 1.422503"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.025894, 0.188623, 0.388689, 0.760565, 1.504316",\ + "0.025894, 0.188772, 0.389191, 0.760565, 1.504316",\ + "0.026920, 0.188772, 0.389191, 0.760565, 1.504316",\ + "0.028933, 0.188772, 0.389191, 0.760565, 1.504316",\ + "0.047288, 0.192696, 0.389191, 0.760565, 1.504596"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.049647, 0.202309, 0.377401, 0.699882, 1.344843",\ + "0.136044, 0.289484, 0.464505, 0.786596, 1.430777",\ + "0.219609, 0.377611, 0.552460, 0.874217, 1.517732",\ + "0.277887, 0.442003, 0.616575, 0.938130, 1.581241",\ + "0.580088, 0.791879, 0.966955, 1.286869, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.026067, 0.301857, 0.634610, 1.249360, 2.473548",\ + "0.030380, 0.302857, 0.636549, 1.249360, 2.473548",\ + "0.043111, 0.305094, 0.636586, 1.249435, 2.473548",\ + "0.055044, 0.308345, 0.636689, 1.250180, 2.473548",\ + "0.131072, 0.346429, 0.642937, 1.253140, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.069111, 0.173607, 0.284871, 0.488812, 0.896694",\ + "0.156518, 0.260926, 0.372152, 0.576117, 0.984047",\ + "0.236897, 0.341257, 0.452179, 0.656146, 1.064079",\ + "0.293644, 0.398806, 0.509722, 0.713390, 1.120727",\ + "0.588008, 0.702147, 0.813352, 1.016403, 1.422503"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002553, 0.075552, 0.162418, 0.322282, 0.642011"); + values ( "0.025894, 0.187819, 0.387180, 0.758333, 1.500639",\ + "0.025894, 0.187819, 0.387180, 0.758333, 1.500639",\ + "0.026920, 0.187819, 0.387180, 0.758333, 1.500639",\ + "0.028933, 0.188428, 0.387638, 0.759236, 1.502430",\ + "0.047288, 0.192696, 0.387712, 0.760007, 1.504596"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026067, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216897, 0.170968, 0.140769, 0.129425, 0.143110",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025894, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251206, 0.175884, 0.107725, 0.084758, 0.147672",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.026067, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148824, -0.106407, -0.071920, -0.032497, 0.273550",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025894, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164361, -0.098446, -0.040787, 0.001174, 0.221781",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[3]_hldr*/ + +} /* end of pin sprom_rm_o[3] */ + +pin("sprom_rm_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.004615 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.055222, 0.206463, 0.380520, 0.701961, 1.344843",\ + "0.141926, 0.293637, 0.467620, 0.788672, 1.430777",\ + "0.226864, 0.381760, 0.555571, 0.876292, 1.517732",\ + "0.286525, 0.446144, 0.619684, 0.940203, 1.581241",\ + "0.597080, 0.796044, 0.970048, 1.288931, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.033550, 0.309737, 0.640567, 1.254566, 2.482564",\ + "0.037083, 0.310781, 0.642475, 1.254566, 2.482564",\ + "0.048991, 0.312947, 0.642512, 1.254566, 2.482564",\ + "0.061025, 0.316093, 0.642622, 1.254566, 2.482564",\ + "0.138571, 0.353164, 0.648838, 1.257074, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.073991, 0.176164, 0.286756, 0.490040, 0.896607",\ + "0.161383, 0.263480, 0.374037, 0.577345, 0.983960",\ + "0.241839, 0.343803, 0.454064, 0.657373, 1.063992",\ + "0.298782, 0.401353, 0.511604, 0.714616, 1.120639",\ + "0.595184, 0.704706, 0.815229, 1.017625, 1.422416"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.030929, 0.193196, 0.392126, 0.762803, 1.504157",\ + "0.030929, 0.193359, 0.392623, 0.762803, 1.504157",\ + "0.031735, 0.193359, 0.392623, 0.762803, 1.504157",\ + "0.033533, 0.193359, 0.392623, 0.762803, 1.504157",\ + "0.050926, 0.197109, 0.392623, 0.762803, 1.504437"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.055222, 0.206463, 0.380520, 0.701961, 1.344843",\ + "0.141926, 0.293637, 0.467620, 0.788672, 1.430777",\ + "0.226864, 0.381760, 0.555571, 0.876292, 1.517732",\ + "0.286525, 0.446144, 0.619684, 0.940203, 1.581241",\ + "0.597080, 0.796044, 0.970048, 1.288931, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.033550, 0.309737, 0.640567, 1.253311, 2.473548",\ + "0.037083, 0.310781, 0.642475, 1.253311, 2.473548",\ + "0.048991, 0.312947, 0.642512, 1.253386, 2.473548",\ + "0.061025, 0.316093, 0.642622, 1.254135, 2.473548",\ + "0.138571, 0.353164, 0.648838, 1.257074, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.073991, 0.176164, 0.286756, 0.490040, 0.896607",\ + "0.161383, 0.263480, 0.374037, 0.577345, 0.983960",\ + "0.241839, 0.343803, 0.454064, 0.657373, 1.063992",\ + "0.298782, 0.401353, 0.511604, 0.714616, 1.120639",\ + "0.595184, 0.704706, 0.815229, 1.017625, 1.422416"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.004615, 0.077613, 0.163964, 0.323313, 0.642011"); + values ( "0.030929, 0.192373, 0.390610, 0.760567, 1.500480",\ + "0.030929, 0.192373, 0.390610, 0.760567, 1.500480",\ + "0.031735, 0.192373, 0.390610, 0.760567, 1.500480",\ + "0.033533, 0.192976, 0.391072, 0.761472, 1.502271",\ + "0.050926, 0.197109, 0.391153, 0.762247, 1.504437"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.033550, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.220362, 0.174433, 0.144233, 0.132890, 0.146575",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030929, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.253498, 0.178177, 0.110018, 0.087050, 0.149964",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.033550, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.152289, -0.109872, -0.075385, -0.035962, 0.270085",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.030929, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.166653, -0.100738, -0.043079, -0.001118, 0.219490",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[2]_hldr*/ + +} /* end of pin sprom_rm_o[2] */ + +pin("sprom_rm_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002475 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.250443, 2.482564",\ + "0.030125, 0.302556, 0.636324, 1.250443, 2.482564",\ + "0.042888, 0.304795, 0.636360, 1.250443, 2.482564",\ + "0.054816, 0.308050, 0.636463, 1.250443, 2.482564",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.482564"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.188435, 0.388543, 0.760465, 1.504307",\ + "0.025687, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.026721, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.028743, 0.188583, 0.389046, 0.760465, 1.504307",\ + "0.047139, 0.192514, 0.389046, 0.760465, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.049435, 0.202151, 0.377283, 0.699803, 1.344843",\ + "0.135820, 0.289326, 0.464387, 0.786517, 1.430777",\ + "0.219334, 0.377453, 0.552342, 0.874138, 1.517732",\ + "0.277559, 0.441846, 0.616457, 0.938052, 1.581241",\ + "0.579442, 0.791721, 0.966837, 1.286790, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025782, 0.301558, 0.634384, 1.249210, 2.473548",\ + "0.030125, 0.302556, 0.636324, 1.249210, 2.473548",\ + "0.042888, 0.304795, 0.636360, 1.249285, 2.473548",\ + "0.054816, 0.308050, 0.636463, 1.250030, 2.473548",\ + "0.130787, 0.346172, 0.642713, 1.252991, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.068909, 0.173502, 0.284792, 0.488757, 0.896689",\ + "0.156317, 0.260820, 0.372072, 0.576063, 0.984042",\ + "0.236694, 0.341152, 0.452099, 0.656091, 1.064074",\ + "0.293432, 0.398701, 0.509642, 0.713335, 1.120722",\ + "0.587713, 0.702042, 0.813273, 1.016348, 1.422499"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002475, 0.075473, 0.162359, 0.322243, 0.642011"); + values ( "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.025687, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.026721, 0.187631, 0.387035, 0.758233, 1.500630",\ + "0.028743, 0.188240, 0.387493, 0.759136, 1.502422",\ + "0.047139, 0.192514, 0.387566, 0.759907, 1.504587"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216765, 0.170836, 0.140637, 0.129293, 0.142978",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.251111, 0.175790, 0.107631, 0.084664, 0.147578",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025782, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.148693, -0.106276, -0.071789, -0.032365, 0.273682",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.025687, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.164267, -0.098352, -0.040693, 0.001268, 0.221876",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[1]_hldr*/ + +} /* end of pin sprom_rm_o[1] */ + +pin("sprom_rm_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.642011 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002026 ; + + /* Other user defined attributes. */ + original_pin : sprom_rm_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.249579, 2.482563",\ + "0.028666, 0.300830, 0.635034, 1.249579, 2.482563",\ + "0.041608, 0.303085, 0.635070, 1.249579, 2.482563",\ + "0.053514, 0.306363, 0.635172, 1.249579, 2.482563",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.482563"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.187440, 0.387796, 0.759979, 1.504343",\ + "0.024592, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.025674, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.027742, 0.187585, 0.388300, 0.759979, 1.504343",\ + "0.046348, 0.191554, 0.388300, 0.759979, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.048221, 0.201247, 0.376603, 0.699350, 1.344843",\ + "0.134540, 0.288422, 0.463709, 0.786065, 1.430777",\ + "0.217754, 0.376549, 0.551664, 0.873687, 1.517732",\ + "0.275678, 0.440944, 0.615780, 0.937600, 1.581241",\ + "0.575742, 0.790814, 0.966163, 1.286341, 1.926697"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024153, 0.299842, 0.633087, 1.248350, 2.473548",\ + "0.028666, 0.300830, 0.635034, 1.248350, 2.473548",\ + "0.041608, 0.303085, 0.635070, 1.248425, 2.473548",\ + "0.053514, 0.306363, 0.635172, 1.249169, 2.473548",\ + "0.129154, 0.344706, 0.641428, 1.252134, 2.473548"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.067848, 0.172946, 0.284382, 0.488491, 0.896709",\ + "0.155259, 0.260265, 0.371663, 0.575796, 0.984062",\ + "0.235619, 0.340599, 0.451690, 0.655824, 1.064094",\ + "0.292315, 0.398147, 0.509233, 0.713069, 1.120741",\ + "0.586152, 0.701486, 0.812865, 1.016083, 1.422518"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002026, 0.075025, 0.162022, 0.322018, 0.642011"); + values ( "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.024592, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.025674, 0.186641, 0.386289, 0.757748, 1.500666",\ + "0.027742, 0.187251, 0.386746, 0.758650, 1.502457",\ + "0.046348, 0.191554, 0.386818, 0.759420, 1.504623"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.207828, 0.161899, 0.131700, 0.120356, 0.134041",\ + "0.216011, 0.170082, 0.139882, 0.128539, 0.142224",\ + "0.288779, 0.242850, 0.212651, 0.201307, 0.214992",\ + "0.380040, 0.333963, 0.303752, 0.292400, 0.306034",\ + "0.827149, 0.779820, 0.749512, 0.738085, 0.751291"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.242722, 0.167401, 0.099242, 0.076275, 0.139189",\ + "0.250613, 0.175291, 0.107132, 0.084165, 0.147079",\ + "0.327767, 0.252445, 0.184286, 0.161319, 0.224233",\ + "0.428766, 0.353454, 0.285343, 0.262454, 0.326079",\ + "0.935354, 0.860120, 0.792428, 0.770222, 0.840039"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024153, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.139756, -0.097339, -0.062852, -0.023429, 0.282618",\ + "-0.147938, -0.105521, -0.071034, -0.031611, 0.274436",\ + "-0.220707, -0.178290, -0.143803, -0.104379, 0.201668",\ + "-0.311850, -0.269460, -0.234911, -0.196695, 0.094357",\ + "-0.757887, -0.715724, -0.680647, -0.652650, -0.488425"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.024592, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.155880, -0.089965, -0.032306, 0.009655, 0.230263",\ + "-0.163769, -0.097854, -0.040195, 0.001766, 0.222374",\ + "-0.240964, -0.175049, -0.117390, -0.075429, 0.145179",\ + "-0.341987, -0.275921, -0.218047, -0.176027, 0.044207",\ + "-0.848724, -0.781360, -0.721623, -0.679100, -0.462092"); + } + + } /* end of arc clk_ast_tlul_i_sprom_rm_o[0]_hldr*/ + +} /* end of pin sprom_rm_o[0] */ +} /* end of bus sprom_rm_o */ +bus ( dft_scan_md_o ) { + + bus_type : BUS4_type6 ; + direction : output ; + +pin("dft_scan_md_o[3]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003517 ; + + /* Other user defined attributes. */ + original_pin : dft_scan_md_o[3]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.133436, 0.291149, 0.448015, 0.761558, 1.388635",\ + "0.217239, 0.374877, 0.531734, 0.845677, 1.473578",\ + "0.292722, 0.450435, 0.607370, 0.921610, 1.550114",\ + "0.345414, 0.503270, 0.660387, 0.974530, 1.602811",\ + "0.613422, 0.771515, 0.928749, 1.242027, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.066308, 0.363809, 0.664826, 1.265395, 2.466601",\ + "0.066379, 0.363809, 0.664826, 1.265395, 2.466601",\ + "0.066379, 0.364085, 0.666054, 1.266438, 2.466601",\ + "0.066379, 0.364085, 0.666054, 1.266438, 2.466601",\ + "0.066665, 0.364152, 0.666054, 1.266438, 2.466601"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.114669, 0.217180, 0.316410, 0.514247, 0.909878",\ + "0.195349, 0.297552, 0.396278, 0.593860, 0.989031",\ + "0.275060, 0.377342, 0.475886, 0.672942, 1.067052",\ + "0.331983, 0.434648, 0.533289, 0.730356, 1.124476",\ + "0.627120, 0.733734, 0.832492, 1.029975, 1.424937"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.047862, 0.221071, 0.402991, 0.762572, 1.481727",\ + "0.048050, 0.221071, 0.402991, 0.762572, 1.484038",\ + "0.048841, 0.221071, 0.402991, 0.762572, 1.484038",\ + "0.050174, 0.221071, 0.402991, 0.762572, 1.484038",\ + "0.063454, 0.223134, 0.402991, 0.763435, 1.490666"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.133312, 0.291022, 0.447820, 0.761354, 1.388420",\ + "0.217237, 0.374875, 0.531731, 0.845675, 1.473578",\ + "0.292688, 0.450412, 0.607364, 0.921580, 1.550030",\ + "0.345261, 0.502988, 0.659849, 0.973849, 1.601865",\ + "0.613232, 0.771275, 0.928568, 1.241507, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.066239, 0.363467, 0.663180, 1.263144, 2.462725",\ + "0.066251, 0.363467, 0.663180, 1.263144, 2.462725",\ + "0.066251, 0.363585, 0.663361, 1.263144, 2.462725",\ + "0.066330, 0.363585, 0.663361, 1.263144, 2.462725",\ + "0.066585, 0.363585, 0.663361, 1.263144, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.114669, 0.217179, 0.316406, 0.514185, 0.909696",\ + "0.195349, 0.297552, 0.396278, 0.593860, 0.989031",\ + "0.275060, 0.377342, 0.475886, 0.672905, 1.066937",\ + "0.331983, 0.434648, 0.533289, 0.730334, 1.124409",\ + "0.627120, 0.733671, 0.832318, 1.029654, 1.424330"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003517, 0.023292, 0.043066, 0.082615, 0.161713"); + values ( "0.047860, 0.219783, 0.399450, 0.759952, 1.480082",\ + "0.047983, 0.219783, 0.399450, 0.759952, 1.480442",\ + "0.048841, 0.219783, 0.399450, 0.759952, 1.480924",\ + "0.050169, 0.219999, 0.399514, 0.759952, 1.480924",\ + "0.063451, 0.222984, 0.400129, 0.761188, 1.483772"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.066308, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.460686, 0.485165, 0.562988, 0.630573, 1.061400",\ + "0.481673, 0.506153, 0.583976, 0.651561, 1.082387",\ + "0.534849, 0.559328, 0.637151, 0.704736, 1.135562",\ + "0.617824, 0.642303, 0.720126, 0.787711, 1.218538",\ + "0.947556, 0.972173, 1.049996, 1.117581, 1.548407"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.047862, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.457000, 0.374371, 0.299229, 0.265511, 0.232819",\ + "0.477245, 0.394617, 0.319474, 0.285756, 0.253064",\ + "0.547749, 0.465121, 0.389978, 0.356260, 0.323568",\ + "0.640993, 0.558364, 0.483222, 0.449504, 0.416811",\ + "1.063337, 0.980709, 0.905566, 0.871848, 0.839156"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.066239, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.335865, -0.312869, -0.277184, -0.251910, -0.123825",\ + "-0.356827, -0.333831, -0.298147, -0.272873, -0.144787",\ + "-0.410399, -0.387403, -0.351719, -0.326444, -0.198359",\ + "-0.492968, -0.469972, -0.434287, -0.409013, -0.280927",\ + "-0.820618, -0.797635, -0.761950, -0.736676, -0.608590"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.047860, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.242066, -0.200653, -0.167936, -0.130741, 0.097416",\ + "-0.262424, -0.221011, -0.188294, -0.151099, 0.077058",\ + "-0.336018, -0.294606, -0.261888, -0.224693, 0.003464",\ + "-0.427308, -0.385895, -0.353178, -0.315983, -0.087826",\ + "-0.831346, -0.789933, -0.757216, -0.720060, -0.491903"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[3]_hldr*/ + +} /* end of pin dft_scan_md_o[3] */ + +pin("dft_scan_md_o[2]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002946 ; + + /* Other user defined attributes. */ + original_pin : dft_scan_md_o[2]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.089185, 0.209900, 0.411017, 0.726230, 1.356390",\ + "0.176530, 0.297275, 0.498423, 0.814441, 1.446276",\ + "0.269642, 0.392143, 0.593017, 0.908861, 1.540369",\ + "0.337617, 0.463374, 0.664040, 0.979619, 1.610599",\ + "0.699386, 0.858557, 1.060886, 1.375366, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.068736, 0.284281, 0.666318, 1.270003, 2.477274",\ + "0.069806, 0.284281, 0.666318, 1.270003, 2.477274",\ + "0.079825, 0.285836, 0.666318, 1.270003, 2.477473",\ + "0.092727, 0.288939, 0.666318, 1.270003, 2.478527",\ + "0.183999, 0.330916, 0.673768, 1.274123, 2.479640"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.114548, 0.198291, 0.327841, 0.529548, 0.932669",\ + "0.202420, 0.286233, 0.415819, 0.617532, 1.020660",\ + "0.283719, 0.367201, 0.496624, 0.698334, 1.101477",\ + "0.341605, 0.425242, 0.554619, 0.756211, 1.159115",\ + "0.647553, 0.733958, 0.863532, 1.064748, 1.466840"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.059272, 0.178664, 0.407996, 0.776762, 1.514808",\ + "0.059349, 0.178981, 0.409509, 0.776762, 1.514808",\ + "0.059349, 0.178981, 0.409796, 0.777827, 1.514808",\ + "0.059903, 0.178981, 0.409796, 0.777827, 1.514808",\ + "0.069603, 0.181400, 0.409796, 0.777827, 1.514808"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[2]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.089178, 0.209899, 0.411017, 0.726223, 1.356368",\ + "0.176530, 0.297223, 0.498130, 0.813320, 1.443459",\ + "0.269641, 0.392139, 0.592998, 0.908848, 1.540369",\ + "0.337615, 0.463370, 0.664029, 0.979611, 1.610599",\ + "0.699305, 0.858522, 1.060836, 1.375332, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.068736, 0.284090, 0.664476, 1.268786, 2.477107",\ + "0.069799, 0.284090, 0.664476, 1.268786, 2.477170",\ + "0.079823, 0.285806, 0.664476, 1.268786, 2.477473",\ + "0.092726, 0.288922, 0.664476, 1.268786, 2.478218",\ + "0.183999, 0.330234, 0.669979, 1.271116, 2.478674"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.114547, 0.198291, 0.327841, 0.529547, 0.932665",\ + "0.202385, 0.286186, 0.415735, 0.617437, 1.020546",\ + "0.283468, 0.366941, 0.496348, 0.698061, 1.101213",\ + "0.341452, 0.425085, 0.554450, 0.756012, 1.158853",\ + "0.647498, 0.733909, 0.863481, 1.064711, 1.466833"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002946, 0.017242, 0.041754, 0.080562, 0.158177"); + values ( "0.059268, 0.178282, 0.407986, 0.775351, 1.510125",\ + "0.059268, 0.178282, 0.408103, 0.775351, 1.510125",\ + "0.059268, 0.178282, 0.408103, 0.775351, 1.510553",\ + "0.059897, 0.178402, 0.408103, 0.775351, 1.510553",\ + "0.069562, 0.181271, 0.408103, 0.775351, 1.510553"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[2]_redg_min*/ + +} /* end of pin dft_scan_md_o[2] */ + +pin("dft_scan_md_o[1]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.158177 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.002940 ; + + /* Other user defined attributes. */ + original_pin : dft_scan_md_o[1]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.089114, 0.209844, 0.410975, 0.726203, 1.356391",\ + "0.176459, 0.297219, 0.498381, 0.814414, 1.446276",\ + "0.269560, 0.392087, 0.592975, 0.908833, 1.540369",\ + "0.337521, 0.463318, 0.663998, 0.979591, 1.610599",\ + "0.699205, 0.858501, 1.060843, 1.375339, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.068629, 0.284175, 0.666239, 1.269949, 2.477274",\ + "0.069702, 0.284175, 0.666239, 1.269949, 2.477274",\ + "0.079734, 0.285730, 0.666239, 1.269949, 2.477474",\ + "0.092637, 0.288835, 0.666239, 1.269949, 2.478527",\ + "0.183880, 0.330821, 0.673696, 1.274070, 2.479641"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.114532, 0.198282, 0.327841, 0.529557, 0.932695",\ + "0.202404, 0.286224, 0.415819, 0.617541, 1.020687",\ + "0.283703, 0.367192, 0.496624, 0.698343, 1.101503",\ + "0.341588, 0.425233, 0.554619, 0.756220, 1.159141",\ + "0.647534, 0.733949, 0.863532, 1.064757, 1.466866"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.059254, 0.178648, 0.407996, 0.776778, 1.514857",\ + "0.059330, 0.178965, 0.409508, 0.776778, 1.514857",\ + "0.059330, 0.178965, 0.409796, 0.777843, 1.514857",\ + "0.059885, 0.178965, 0.409796, 0.777843, 1.514857",\ + "0.069589, 0.181384, 0.409796, 0.777843, 1.514857"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[1]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.089108, 0.209843, 0.410975, 0.726196, 1.356369",\ + "0.176459, 0.297167, 0.498088, 0.813292, 1.443459",\ + "0.269559, 0.392083, 0.592956, 0.908820, 1.540369",\ + "0.337519, 0.463314, 0.663987, 0.979583, 1.610599",\ + "0.699124, 0.858466, 1.060793, 1.375304, 2.003839"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.068628, 0.283984, 0.664398, 1.268733, 2.477107",\ + "0.069695, 0.283984, 0.664398, 1.268733, 2.477171",\ + "0.079731, 0.285701, 0.664398, 1.268733, 2.477474",\ + "0.092635, 0.288817, 0.664398, 1.268733, 2.478218",\ + "0.183880, 0.330139, 0.669908, 1.271063, 2.478675"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.114530, 0.198282, 0.327841, 0.529556, 0.932692",\ + "0.202368, 0.286177, 0.415735, 0.617446, 1.020573",\ + "0.283452, 0.366932, 0.496348, 0.698070, 1.101240",\ + "0.341435, 0.425076, 0.554450, 0.756020, 1.158880",\ + "0.647479, 0.733900, 0.863481, 1.064720, 1.466859"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.002940, 0.017235, 0.041749, 0.080558, 0.158177"); + values ( "0.059249, 0.178266, 0.407986, 0.775367, 1.510173",\ + "0.059249, 0.178266, 0.408103, 0.775367, 1.510173",\ + "0.059249, 0.178266, 0.408103, 0.775367, 1.510602",\ + "0.059879, 0.178385, 0.408103, 0.775367, 1.510602",\ + "0.069548, 0.181255, 0.408103, 0.775367, 1.510602"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[1]_redg_min*/ + +} /* end of pin dft_scan_md_o[1] */ + +pin("dft_scan_md_o[0]") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.161713 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.003291 ; + + /* Other user defined attributes. */ + original_pin : dft_scan_md_o[0]; + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.131615, 0.289575, 0.446666, 0.760660, 1.388635",\ + "0.215420, 0.373304, 0.530386, 0.844778, 1.473578",\ + "0.290903, 0.448861, 0.606021, 0.920710, 1.550114",\ + "0.343593, 0.501694, 0.659036, 0.973630, 1.602811",\ + "0.611596, 0.769938, 0.927397, 1.241129, 1.868510"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.062950, 0.360790, 0.662238, 1.263674, 2.466600",\ + "0.063013, 0.360790, 0.662238, 1.263674, 2.466600",\ + "0.063013, 0.361056, 0.663457, 1.264718, 2.466600",\ + "0.063013, 0.361056, 0.663457, 1.264718, 2.466600",\ + "0.063304, 0.361135, 0.663457, 1.264718, 2.466600"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.113407, 0.216311, 0.315683, 0.513806, 0.910003",\ + "0.194085, 0.296687, 0.395555, 0.593419, 0.989157",\ + "0.273778, 0.376478, 0.475164, 0.672502, 1.067177",\ + "0.330670, 0.433783, 0.532566, 0.729916, 1.124601",\ + "0.625514, 0.732868, 0.831768, 1.029534, 1.425062"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.046113, 0.219478, 0.401657, 0.761769, 1.481954",\ + "0.046300, 0.219478, 0.401657, 0.761769, 1.484267",\ + "0.047120, 0.219478, 0.401657, 0.761769, 1.484267",\ + "0.048485, 0.219478, 0.401657, 0.761769, 1.484267",\ + "0.061963, 0.221582, 0.401657, 0.762623, 1.490896"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.131490, 0.289449, 0.446472, 0.760456, 1.388420",\ + "0.215418, 0.373302, 0.530383, 0.844776, 1.473578",\ + "0.290869, 0.448838, 0.606015, 0.920679, 1.550029",\ + "0.343439, 0.501415, 0.658500, 0.972949, 1.601865",\ + "0.611409, 0.769697, 0.927216, 1.240610, 1.867283"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.062879, 0.360460, 0.660603, 1.261425, 2.462725",\ + "0.062899, 0.360460, 0.660603, 1.261425, 2.462725",\ + "0.062899, 0.360578, 0.660783, 1.261425, 2.462725",\ + "0.062968, 0.360578, 0.660783, 1.261425, 2.462725",\ + "0.063222, 0.360578, 0.660783, 1.261425, 2.462725"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.113407, 0.216309, 0.315678, 0.513743, 0.909821",\ + "0.194085, 0.296687, 0.395555, 0.593419, 0.989157",\ + "0.273778, 0.376478, 0.475164, 0.672465, 1.067062",\ + "0.330670, 0.433783, 0.532566, 0.729894, 1.124533",\ + "0.625514, 0.732807, 0.831595, 1.029214, 1.424455"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.003291, 0.023093, 0.042896, 0.082502, 0.161713"); + values ( "0.046112, 0.218208, 0.398133, 0.759147, 1.480310",\ + "0.046235, 0.218208, 0.398133, 0.759147, 1.480670",\ + "0.047116, 0.218208, 0.398133, 0.759147, 1.481152",\ + "0.048480, 0.218425, 0.398198, 0.759147, 1.481152",\ + "0.061948, 0.221432, 0.398830, 0.760382, 1.484000"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.062950, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.468253, 0.492732, 0.570555, 0.638140, 1.068967",\ + "0.490044, 0.514523, 0.592346, 0.659931, 1.090757",\ + "0.545368, 0.569847, 0.647670, 0.715255, 1.146082",\ + "0.634688, 0.659168, 0.736991, 0.804576, 1.235402",\ + "1.017271, 1.041743, 1.119566, 1.187151, 1.617977"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.046113, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.459602, 0.376973, 0.301830, 0.268113, 0.235420",\ + "0.477883, 0.395254, 0.320112, 0.286394, 0.253701",\ + "0.549719, 0.467091, 0.391948, 0.358230, 0.325538",\ + "0.644311, 0.561683, 0.486540, 0.452822, 0.420130",\ + "1.067339, 0.984711, 0.909568, 0.875850, 0.843158"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_stupr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.062879, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.343432, -0.320436, -0.284752, -0.259478, -0.131392",\ + "-0.365195, -0.342199, -0.306515, -0.281240, -0.153155",\ + "-0.420715, -0.397719, -0.362035, -0.336760, -0.208675",\ + "-0.509827, -0.486831, -0.451147, -0.425873, -0.297787",\ + "-0.891088, -0.868095, -0.832410, -0.807136, -0.679050"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.046112, 0.195118, 0.455354, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.244757, -0.203344, -0.170627, -0.133432, 0.094725",\ + "-0.263038, -0.221625, -0.188908, -0.151713, 0.076444",\ + "-0.337776, -0.296363, -0.263646, -0.226451, 0.001706",\ + "-0.430900, -0.389488, -0.356770, -0.319575, -0.091418",\ + "-0.836348, -0.794936, -0.762218, -0.725057, -0.496900"); + } + + } /* end of arc clk_ast_tlul_i_dft_scan_md_o[0]_hldr*/ + +} /* end of pin dft_scan_md_o[0] */ +} /* end of bus dft_scan_md_o */ + +pin("scan_shift_en_o") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.095084 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.028179 ; + + /* Other user defined attributes. */ + original_pin : scan_shift_en_o; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.532219, 0.489613, 0.431727, 0.435127, 0.476450",\ + "0.639994, 0.597388, 0.539502, 0.542902, 0.584225",\ + "0.783455, 0.740849, 0.682963, 0.686363, 0.727686",\ + "0.930263, 0.887658, 0.829771, 0.833171, 0.874494",\ + "1.623874, 1.581268, 1.523381, 1.526781, 1.568104"); + } + + } /* end of arc clk_ast_alert_i_scan_shift_en_o_recrr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "0.043626, 0.100485, 0.237779, 0.265545, 0.602978",\ + "-0.038691, 0.018168, 0.155463, 0.183228, 0.520661",\ + "-0.121016, -0.064151, 0.072977, 0.100718, 0.437847",\ + "-0.190085, -0.133213, 0.003667, 0.031370, 0.368047",\ + "-0.499886, -0.442913, -0.307440, -0.279961, 0.053979"); + } + + } /* end of arc clk_ast_alert_i_scan_shift_en_o_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.063826, 0.062652, 0.129143, 0.282266, 0.638582",\ + "0.144516, 0.122873, 0.153635, 0.250761, 0.490135",\ + "0.243845, 0.203218, 0.197002, 0.225868, 0.314993",\ + "0.333420, 0.283466, 0.260028, 0.260578, 0.289579",\ + "0.742571, 0.680072, 0.640181, 0.639634, 0.684785"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.484230, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.069804, -0.018648, -0.111764, -0.244874, -0.513274",\ + "0.147065, 0.058673, -0.032069, -0.165383, -0.437145",\ + "0.257633, 0.169188, 0.076752, -0.058192, -0.332590",\ + "0.419789, 0.332087, 0.238963, 0.102061, -0.177084",\ + "0.794358, 0.708802, 0.615035, 0.473837, 0.183265"); + } + + } /* end of arc clk_ast_ext_i_scan_shift_en_o_cgsr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.041482, 0.004889, 0.044867, 0.102673, 0.219769",\ + "-0.121636, -0.074743, -0.032444, 0.026924, 0.145736",\ + "-0.213199, -0.163583, -0.120926, -0.060090, 0.062464",\ + "-0.289736, -0.238766, -0.195667, -0.134080, -0.009915",\ + "-0.654569, -0.601430, -0.555559, -0.492609, -0.367822"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.476372, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.044121, 0.037282, 0.129537, 0.261976, 0.529485",\ + "-0.122275, -0.038844, 0.049184, 0.181641, 0.454147",\ + "-0.228703, -0.144549, -0.055160, 0.079110, 0.355165",\ + "-0.387423, -0.304473, -0.214026, -0.077712, 0.202895",\ + "-0.744719, -0.665813, -0.573547, -0.433021, -0.142598"); + } + + } /* end of arc clk_ast_ext_i_scan_shift_en_o_cghr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380000.437500, 380000.468750, 380000.531250, 380000.812500, 380001.312500",\ + "380000.531250, 380000.562500, 380000.625000, 380000.906250, 380001.406250",\ + "380000.593750, 380000.625000, 380000.687500, 380000.968750, 380001.468750",\ + "380000.656250, 380000.687500, 380000.750000, 380001.031250, 380001.531250",\ + "380000.968750, 380001.000000, 380001.062500, 380001.343750, 380001.843750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380001.750000, 380001.781250, 380001.843750, 380002.031250, 380002.375000",\ + "380001.843750, 380001.875000, 380001.937500, 380002.125000, 380002.468750",\ + "380001.937500, 380001.968750, 380002.031250, 380002.218750, 380002.562500",\ + "380002.000000, 380002.031250, 380002.093750, 380002.281250, 380002.625000",\ + "380002.343750, 380002.375000, 380002.437500, 380002.625000, 380002.968750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.476972, 0.520642, 0.623430, 0.968675, 1.632439",\ + "0.476972, 0.520642, 0.623430, 0.968675, 1.632439",\ + "0.476984, 0.520655, 0.623442, 0.968683, 1.632439",\ + "0.477092, 0.520773, 0.623551, 0.968760, 1.632439",\ + "0.477240, 0.520936, 0.623729, 0.968990, 1.632439"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.567867, 0.601968, 0.682377, 0.952454, 1.470934",\ + "0.656009, 0.690105, 0.770491, 1.040492, 1.558825",\ + "0.750333, 0.784422, 0.864790, 1.134732, 1.652952",\ + "0.817746, 0.851834, 0.932210, 1.202178, 1.720448",\ + "1.177034, 1.211190, 1.291747, 1.562319, 2.081752"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.742023, 0.806942, 0.960129, 1.473159, 2.454133",\ + "0.742023, 0.806942, 0.960129, 1.473159, 2.454133",\ + "0.742023, 0.806942, 0.960129, 1.473554, 2.458020",\ + "0.742023, 0.806942, 0.960129, 1.474655, 2.462414",\ + "0.742023, 0.806942, 0.960129, 1.474655, 2.462414"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.436555, 0.460383, 0.516602, 0.705431, 1.067936",\ + "0.524364, 0.548192, 0.604409, 0.793229, 1.155716",\ + "0.605651, 0.629479, 0.685698, 0.874530, 1.237040",\ + "0.663776, 0.687602, 0.743831, 0.932696, 1.295270",\ + "0.971918, 0.995743, 1.051944, 1.240713, 1.603103"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.476372, 0.519944, 0.622887, 0.968653, 1.631455",\ + "0.476372, 0.519944, 0.622887, 0.968653, 1.631455",\ + "0.476372, 0.519944, 0.622887, 0.968653, 1.631461",\ + "0.476372, 0.519944, 0.622887, 0.968653, 1.631478",\ + "0.476373, 0.519944, 0.622887, 0.968653, 1.631806"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "1.025280, 0.973708, 0.938980, 0.927998, 0.968803",\ + "1.133724, 1.082152, 1.047424, 1.036442, 1.077247",\ + "1.276742, 1.225171, 1.190443, 1.179460, 1.220266",\ + "1.421700, 1.370129, 1.335400, 1.324418, 1.365223",\ + "2.112985, 2.061414, 2.026685, 2.015703, 2.056509"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.484807, -0.401976, -0.317025, -0.255738, 0.062771",\ + "-0.593251, -0.510420, -0.425469, -0.364182, -0.045673",\ + "-0.735922, -0.653091, -0.568140, -0.506853, -0.188344",\ + "-0.871661, -0.788831, -0.703879, -0.642593, -0.324084",\ + "-1.567978, -1.485147, -1.400195, -1.338909, -1.020400"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_remrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : setup_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.766211, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.500052, 0.464257, 0.467454, 0.481872, 0.641062",\ + "0.608496, 0.572702, 0.575898, 0.590317, 0.749506",\ + "0.751349, 0.715408, 0.718319, 0.732500, 0.890238",\ + "0.895828, 0.859887, 0.862797, 0.876979, 1.034717",\ + "1.584854, 1.547746, 1.548384, 1.560677, 1.706875"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.484230, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "0.472376, 0.383961, 0.292457, 0.226602, -0.114540",\ + "0.571622, 0.483207, 0.391702, 0.325848, -0.015294",\ + "0.718823, 0.630408, 0.538891, 0.473029, 0.131864",\ + "0.967954, 0.879538, 0.787986, 0.722105, 0.380872",\ + "1.461814, 1.373393, 1.281717, 1.215763, 0.874287"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_cgsr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : hold_rising ; + clock_gating_flag : true ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.746802, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.471383, -0.422460, -0.379894, -0.349813, -0.197830",\ + "-0.579827, -0.530904, -0.488339, -0.458257, -0.306274",\ + "-0.722620, -0.673676, -0.631108, -0.601022, -0.449003",\ + "-0.858078, -0.809134, -0.766565, -0.736479, -0.584461",\ + "-1.555647, -1.506536, -1.463946, -1.433827, -1.281521"); + } + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.476372, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.447062, -0.363296, -0.274639, -0.209836, 0.132805",\ + "-0.546307, -0.462542, -0.373884, -0.309082, 0.033560",\ + "-0.689363, -0.605598, -0.516940, -0.452138, -0.109496",\ + "-0.942607, -0.858821, -0.770125, -0.705296, -0.362529",\ + "-1.436381, -1.352539, -1.263740, -1.198841, -0.855737"); + } + + } /* end of arc clk_ast_tlul_i_scan_shift_en_o_cghr*/ + + timing () { + related_pin : "padmux2ast_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.489833, 0.523915, 0.604311, 0.874343, 1.392737",\ + "0.566174, 0.600431, 0.681298, 0.952915, 1.474352",\ + "0.660833, 0.694982, 0.775530, 1.046072, 1.565447",\ + "0.820966, 0.855139, 0.935773, 1.206609, 1.726547",\ + "1.095138, 1.129115, 1.209400, 1.479059, 1.996736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.766211, 0.830301, 0.980244, 1.483872, 2.450712",\ + "0.766211, 0.830301, 0.980244, 1.483872, 2.456399",\ + "0.766211, 0.830301, 0.980244, 1.483872, 2.457642",\ + "0.766211, 0.830301, 0.980244, 1.483872, 2.465531",\ + "0.766211, 0.830301, 0.980244, 1.483872, 2.465531"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.331095, 0.354971, 0.411113, 0.599682, 0.961689",\ + "0.422338, 0.446186, 0.502618, 0.692160, 1.056035",\ + "0.529474, 0.553262, 0.609349, 0.797734, 1.159388",\ + "0.719234, 0.743081, 0.799295, 0.988106, 1.350577",\ + "1.047647, 1.071864, 1.127881, 1.316028, 1.677225"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\ + "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\ + "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\ + "0.484230, 0.528601, 0.631276, 0.976140, 1.638195",\ + "0.491280, 0.530601, 0.632503, 0.976140, 1.638195"); + } + + } /* end of arc padmux2ast_i[2]_scan_shift_en_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[2]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.489833, 0.523915, 0.604311, 0.874343, 1.392737",\ + "0.566174, 0.600431, 0.681298, 0.952915, 1.474352",\ + "0.660833, 0.694982, 0.775530, 1.046072, 1.565447",\ + "0.820966, 0.855139, 0.935773, 1.206609, 1.726547",\ + "1.095138, 1.129115, 1.209400, 1.479059, 1.996736"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.748897, 0.805011, 0.957821, 1.471076, 2.450712",\ + "0.748897, 0.805011, 0.957821, 1.471076, 2.456399",\ + "0.748897, 0.811237, 0.965448, 1.477816, 2.457642",\ + "0.748897, 0.811237, 0.965448, 1.479720, 2.465531",\ + "0.748897, 0.813325, 0.966210, 1.479720, 2.465531"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.331095, 0.354971, 0.411113, 0.599682, 0.961689",\ + "0.422338, 0.446186, 0.502618, 0.692160, 1.056035",\ + "0.529474, 0.553262, 0.609349, 0.797734, 1.159388",\ + "0.719234, 0.743081, 0.799295, 0.988106, 1.350577",\ + "1.047647, 1.071864, 1.127881, 1.316028, 1.677225"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.484230, 0.518873, 0.622079, 0.966408, 1.621243",\ + "0.484230, 0.518873, 0.622079, 0.966408, 1.621243",\ + "0.484230, 0.518873, 0.622079, 0.968730, 1.631847",\ + "0.484230, 0.522164, 0.625240, 0.971450, 1.631847",\ + "0.491280, 0.530601, 0.632503, 0.974773, 1.631847"); + } + + } /* end of arc padmux2ast_i[2]_scan_shift_en_o_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380000.312500, 380000.343750, 380000.406250, 380000.687500, 380001.187500",\ + "380000.406250, 380000.437500, 380000.500000, 380000.781250, 380001.281250",\ + "380000.500000, 380000.531250, 380000.593750, 380000.875000, 380001.375000",\ + "380000.656250, 380000.687500, 380000.750000, 380001.031250, 380001.531250",\ + "380000.906250, 380000.937500, 380001.000000, 380001.281250, 380001.781250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380001.656250, 380001.687500, 380001.750000, 380001.937500, 380002.281250",\ + "380001.750000, 380001.781250, 380001.843750, 380002.031250, 380002.375000",\ + "380001.875000, 380001.906250, 380001.968750, 380002.156250, 380002.500000",\ + "380002.062500, 380002.093750, 380002.156250, 380002.343750, 380002.687500",\ + "380002.375000, 380002.406250, 380002.468750, 380002.656250, 380003.000000"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439"); + } + + } /* end of arc padmux2ast_i[4]_scan_shift_en_o_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380000.312500, 380000.343750, 380000.406250, 380000.687500, 380001.187500",\ + "380000.406250, 380000.437500, 380000.500000, 380000.781250, 380001.281250",\ + "380000.468750, 380000.500000, 380000.562500, 380000.843750, 380001.343750",\ + "380000.625000, 380000.656250, 380000.718750, 380001.000000, 380001.500000",\ + "380000.843750, 380000.875000, 380000.937500, 380001.218750, 380001.718750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965",\ + "0.750971, 0.815816, 0.968419, 1.480978, 2.464965"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "380001.656250, 380001.687500, 380001.750000, 380001.937500, 380002.281250",\ + "380001.750000, 380001.781250, 380001.843750, 380002.031250, 380002.375000",\ + "380001.843750, 380001.875000, 380001.937500, 380002.125000, 380002.468750",\ + "380002.031250, 380002.062500, 380002.125000, 380002.312500, 380002.656250",\ + "380002.281250, 380002.312500, 380002.375000, 380002.562500, 380002.906250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.028179, 0.030705, 0.036662, 0.056671, 0.095084"); + values ( "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439",\ + "0.476385, 0.519957, 0.622899, 0.968661, 1.632439"); + } + + } /* end of arc padmux2ast_i[4]_scan_shift_en_o_una_min*/ + +} /* end of pin scan_shift_en_o */ + +pin("scan_reset_no") { + direction : output ; + max_transition : 2.480000 ; + min_transition : 0.000000 ; + max_capacitance : 0.044252 ; + min_capacitance : 0.000067 ; + max_fanout : 50.000000 ; + capacitance : 0.021601 ; + + /* Other user defined attributes. */ + original_pin : scan_reset_no; + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : recovery_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 1.099537, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "1.964051, 1.921426, 1.863863, 1.867343, 1.909642",\ + "2.060242, 2.017617, 1.960053, 1.963533, 2.005833",\ + "2.173090, 2.130465, 2.072901, 2.076381, 2.118681",\ + "2.375021, 2.332396, 2.274832, 2.278312, 2.320612",\ + "2.686105, 2.643480, 2.585916, 2.589396, 2.631696"); + } + + } /* end of arc clk_ast_alert_i_scan_reset_no_recfr*/ + + timing () { + related_pin : "clk_ast_alert_i" ; + timing_type : removal_rising ; + fall_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 0.898734, 2.480000"); + index_2 ( "0.000000, 0.127724, 0.562810, 0.708571, 2.480000"); + values ( "-1.851924, -1.814471, -1.754913, -1.744727, -1.620931",\ + "-1.948175, -1.910723, -1.851165, -1.840978, -1.717183",\ + "-2.061304, -2.023851, -1.964293, -1.954107, -1.830311",\ + "-2.203395, -2.165943, -2.106384, -2.096198, -1.972402",\ + "-2.574453, -2.537001, -2.477442, -2.467256, -2.343460"); + } + + } /* end of arc clk_ast_alert_i_scan_reset_no_remfr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.802143, 0.819742, 0.854125, 0.955681, 1.487746",\ + "0.890534, 0.908134, 0.942517, 1.044073, 1.576140",\ + "0.986100, 1.003701, 1.038085, 1.139644, 1.671728",\ + "1.152159, 1.169761, 1.204148, 1.305714, 1.837840",\ + "1.418048, 1.435651, 1.470039, 1.571612, 2.103765"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.229517, 1.260918, 1.322264, 1.503458, 2.452761",\ + "1.229525, 1.260928, 1.322278, 1.503483, 2.452843",\ + "1.229623, 1.261050, 1.322445, 1.503785, 2.453854",\ + "1.229849, 1.261330, 1.322831, 1.504483, 2.456189",\ + "1.230249, 1.261792, 1.323416, 1.505431, 2.459036"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.798583, 0.815273, 0.847880, 0.944189, 1.448769",\ + "0.886419, 0.903109, 0.935716, 1.032025, 1.536605",\ + "0.967929, 0.984620, 1.017227, 1.113536, 1.618116",\ + "1.107256, 1.123946, 1.156553, 1.252862, 1.757442",\ + "1.334271, 1.350961, 1.383568, 1.479877, 1.984456"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.070623, 1.099479, 1.155855, 1.322366, 2.194748",\ + "1.070624, 1.099480, 1.155855, 1.322366, 2.194748",\ + "1.070624, 1.099480, 1.155855, 1.322366, 2.194748",\ + "1.070624, 1.099480, 1.155855, 1.322366, 2.194752",\ + "1.070624, 1.099480, 1.155855, 1.322366, 2.194762"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_ext_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.802125, 0.819724, 0.854108, 0.955663, 1.487728",\ + "0.890342, 0.907941, 0.942325, 1.043880, 1.575947",\ + "0.986099, 1.003699, 1.038084, 1.139642, 1.671727",\ + "1.152155, 1.169757, 1.204144, 1.305710, 1.837835",\ + "1.417944, 1.435547, 1.469935, 1.571508, 2.103662"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.229517, 1.260918, 1.322264, 1.503458, 2.452760",\ + "1.229525, 1.260928, 1.322278, 1.503482, 2.452842",\ + "1.229623, 1.261050, 1.322445, 1.503785, 2.453854",\ + "1.229849, 1.261330, 1.322831, 1.504483, 2.456189",\ + "1.230248, 1.261792, 1.323416, 1.505430, 2.459036"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.798579, 0.815269, 0.847876, 0.944185, 1.448765",\ + "0.886379, 0.903069, 0.935677, 1.031986, 1.536566",\ + "0.967658, 0.984348, 1.016956, 1.113265, 1.617844",\ + "1.107229, 1.123919, 1.156526, 1.252835, 1.757415",\ + "1.334205, 1.350896, 1.383503, 1.479811, 1.984390"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.070600, 1.099457, 1.155835, 1.322351, 2.194748",\ + "1.070600, 1.099457, 1.155835, 1.322351, 2.194748",\ + "1.070600, 1.099457, 1.155835, 1.322351, 2.194748",\ + "1.070600, 1.099457, 1.155835, 1.322351, 2.194752",\ + "1.070600, 1.099457, 1.155835, 1.322351, 2.194762"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_redg_min*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 1.230133, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "3.588611, 3.540715, 3.506416, 3.500099, 3.522348",\ + "3.671103, 3.623207, 3.588908, 3.582592, 3.604841",\ + "3.766086, 3.718189, 3.683890, 3.677574, 3.699822",\ + "3.975284, 3.927388, 3.893089, 3.886772, 3.909021",\ + "4.236159, 4.188263, 4.153964, 4.147648, 4.169896"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_recrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : recovery_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 1.230133, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "0.254411, 0.254411, 0.254411, 0.254411, 0.254411",\ + "0.332233, 0.332233, 0.332233, 0.332233, 0.332233",\ + "0.412826, 0.412826, 0.412826, 0.412826, 0.412826",\ + "0.584722, 0.584722, 0.584722, 0.584722, 0.584722",\ + "0.796290, 0.796290, 0.796290, 0.796290, 0.796290"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_recrf*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.591561, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.156602, -0.106021, -0.062437, -0.009182, 0.090788",\ + "-0.234424, -0.183844, -0.140259, -0.087005, 0.012965",\ + "-0.347653, -0.297234, -0.253546, -0.200284, -0.100415",\ + "-0.457700, -0.407414, -0.363694, -0.310440, -0.210630",\ + "-0.693682, -0.643595, -0.600273, -0.547145, -0.447229"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_remrr*/ + + timing () { + related_pin : "clk_ast_ext_i" ; + timing_type : removal_falling ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.591561, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + values ( "-0.072639, -0.072639, -0.072639, -0.072639, -0.072639",\ + "-0.150732, -0.150732, -0.150732, -0.150732, -0.150732",\ + "-0.261960, -0.261960, -0.261960, -0.261960, -0.261960",\ + "-0.368573, -0.368573, -0.368573, -0.368573, -0.368573",\ + "-0.585347, -0.585347, -0.585347, -0.585347, -0.585347"); + } + + } /* end of arc clk_ast_ext_i_scan_reset_no_remrf*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380001.750000, 380001.750000, 380001.750000, 380001.812500, 380002.062500",\ + "380001.843750, 380001.843750, 380001.843750, 380001.906250, 380002.156250",\ + "380001.937500, 380001.937500, 380001.937500, 380002.000000, 380002.250000",\ + "380002.000000, 380002.000000, 380002.000000, 380002.062500, 380002.312500",\ + "380002.343750, 380002.343750, 380002.343750, 380002.406250, 380002.656250"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.229646, 1.261078, 1.322484, 1.503854, 2.454086",\ + "1.229646, 1.261078, 1.322484, 1.503854, 2.454086",\ + "1.229646, 1.261078, 1.322484, 1.503854, 2.454086",\ + "1.229646, 1.261078, 1.322484, 1.503855, 2.454087",\ + "1.229648, 1.261080, 1.322487, 1.503860, 2.454105"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380000.593750, 380000.593750, 380000.625000, 380000.718750, 380001.250000",\ + "380000.687500, 380000.687500, 380000.718750, 380000.812500, 380001.343750",\ + "380000.750000, 380000.750000, 380000.781250, 380000.875000, 380001.406250",\ + "380000.812500, 380000.812500, 380000.843750, 380000.937500, 380001.468750",\ + "380001.125000, 380001.125000, 380001.156250, 380001.250000, 380001.781250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.099064, 1.128619, 1.186359, 1.356900, 2.250939"); + } + + } /* end of arc clk_ast_tlul_i_scan_reset_no_redg*/ + + timing () { + min_delay_flag : true ; + related_pin : "clk_ast_tlul_i" ; + timing_type : rising_edge ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.422873, 0.430902, 0.446588, 0.492920, 0.735645",\ + "0.510672, 0.518701, 0.534387, 0.580719, 0.823446",\ + "0.591965, 0.599994, 0.615680, 0.662012, 0.904736",\ + "0.650145, 0.658174, 0.673861, 0.720193, 0.962908",\ + "0.958388, 0.966413, 0.982090, 1.028394, 1.270988"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.591561, 0.606759, 0.636466, 0.724197, 1.183709",\ + "0.591561, 0.606759, 0.636466, 0.724197, 1.183709",\ + "0.591563, 0.606768, 0.636472, 0.724197, 1.183709",\ + "0.591595, 0.606795, 0.636489, 0.724197, 1.183709",\ + "0.591849, 0.607055, 0.636761, 0.724504, 1.184204"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.601971, 0.615882, 0.643058, 0.723326, 1.143863",\ + "0.689980, 0.703892, 0.731069, 0.811342, 1.231904",\ + "0.785109, 0.799012, 0.826172, 0.906394, 1.326690",\ + "0.853674, 0.867567, 0.894707, 0.974869, 1.394853",\ + "1.216942, 1.230863, 1.258059, 1.338388, 1.759243"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.898014, 0.922343, 0.969635, 1.108981, 1.838479",\ + "0.898014, 0.922343, 0.969635, 1.108981, 1.838479",\ + "0.898014, 0.922343, 0.969635, 1.108981, 1.839038",\ + "0.898014, 0.922343, 0.969800, 1.109378, 1.840651",\ + "0.898014, 0.922343, 0.969873, 1.110259, 1.842156"); + } + + } /* end of arc clk_ast_tlul_i_scan_reset_no_redg_min*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : recovery_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.455354, 1.230133, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "1.415613, 1.363816, 1.325401, 1.311644, 1.337231",\ + "1.501586, 1.449789, 1.411374, 1.397617, 1.423205",\ + "1.612727, 1.560930, 1.522515, 1.508758, 1.534346",\ + "1.834322, 1.782526, 1.744110, 1.730354, 1.755941",\ + "2.101753, 2.049956, 2.011540, 1.997784, 2.023371"); + } + + } /* end of arc clk_ast_tlul_i_scan_reset_no_recrr*/ + + timing () { + related_pin : "clk_ast_tlul_i" ; + timing_type : removal_rising ; + rise_constraint( f_dtrans_ctrans ){ + index_1 ( "0.006578, 0.195118, 0.591561, 1.062676, 2.480000"); + index_2 ( "0.000000, 0.195118, 0.455354, 0.708571, 2.480000"); + values ( "-0.697532, -0.650599, -0.616529, -0.592387, -0.469972",\ + "-0.783374, -0.736441, -0.702370, -0.678229, -0.555814",\ + "-0.939179, -0.892246, -0.858175, -0.834034, -0.711619",\ + "-1.080269, -1.033336, -0.999265, -0.975124, -0.852709",\ + "-1.378594, -1.331661, -1.297591, -1.273450, -1.151034"); + } + + } /* end of arc clk_ast_tlul_i_scan_reset_no_remrr*/ + + timing () { + related_pin : "padmux2ast_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.726887, 0.744473, 0.778830, 0.880309, 1.411971",\ + "0.813994, 0.831587, 0.865957, 0.967473, 1.499333",\ + "0.895839, 0.913433, 0.947805, 1.049329, 1.581226",\ + "1.037802, 1.055400, 1.089781, 1.191329, 1.723358",\ + "1.277047, 1.294652, 1.329045, 1.430630, 1.962853"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.230133, 1.261577, 1.323007, 1.504448, 2.455048",\ + "1.230133, 1.261577, 1.323007, 1.504448, 2.455048",\ + "1.230191, 1.261616, 1.323008, 1.504448, 2.455048",\ + "1.230748, 1.262222, 1.323711, 1.505326, 2.455673",\ + "1.230748, 1.262222, 1.323711, 1.505326, 2.455673"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.683808, 0.700926, 0.734366, 0.833138, 1.350622",\ + "0.774648, 0.791774, 0.825231, 0.924052, 1.441793",\ + "0.860296, 0.877424, 0.910885, 1.009716, 1.527510",\ + "1.010613, 1.027735, 1.061184, 1.159981, 1.677597",\ + "1.262256, 1.279377, 1.312826, 1.411619, 1.929216"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\ + "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\ + "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\ + "1.099537, 1.129083, 1.186806, 1.357299, 2.250541",\ + "1.099652, 1.129190, 1.186897, 1.357342, 2.250541"); + } + + } /* end of arc padmux2ast_i[3]_scan_reset_no_una*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[3]" ; + timing_type : combinational ; + timing_sense : positive_unate ; + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.726887, 0.744473, 0.778830, 0.880309, 1.411971",\ + "0.813994, 0.831587, 0.865957, 0.967473, 1.499333",\ + "0.895839, 0.913433, 0.947805, 1.049329, 1.581226",\ + "1.037802, 1.055400, 1.089781, 1.191329, 1.723358",\ + "1.277047, 1.294652, 1.329045, 1.430630, 1.962853"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.230133, 1.260882, 1.322288, 1.503659, 2.453893",\ + "1.230133, 1.260882, 1.322288, 1.503659, 2.453893",\ + "1.230191, 1.261616, 1.323008, 1.504337, 2.454350",\ + "1.230581, 1.262030, 1.323468, 1.504936, 2.455673",\ + "1.230581, 1.262030, 1.323468, 1.504936, 2.455673"); + } + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.683808, 0.700926, 0.734366, 0.833138, 1.350622",\ + "0.774648, 0.791774, 0.825231, 0.924052, 1.441793",\ + "0.860296, 0.877424, 0.910885, 1.009716, 1.527510",\ + "1.010613, 1.027735, 1.061184, 1.159981, 1.677597",\ + "1.262256, 1.279377, 1.312826, 1.411619, 1.929216"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.099537, 1.128236, 1.185986, 1.356560, 2.250221",\ + "1.099537, 1.128236, 1.185986, 1.356560, 2.250221",\ + "1.099537, 1.128268, 1.186038, 1.356667, 2.250334",\ + "1.099537, 1.128795, 1.186566, 1.357201, 2.250334",\ + "1.099652, 1.129190, 1.186897, 1.357342, 2.250334"); + } + + } /* end of arc padmux2ast_i[3]_scan_reset_no_una_min*/ + + timing () { + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380000.468750, 380000.468750, 380000.500000, 380000.593750, 380001.125000",\ + "380000.562500, 380000.562500, 380000.593750, 380000.687500, 380001.218750",\ + "380000.656250, 380000.656250, 380000.687500, 380000.781250, 380001.312500",\ + "380000.812500, 380000.812500, 380000.843750, 380000.937500, 380001.468750",\ + "380001.062500, 380001.062500, 380001.093750, 380001.187500, 380001.718750"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939",\ + "1.098794, 1.128370, 1.186150, 1.356812, 2.250939"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380001.656250, 380001.656250, 380001.656250, 380001.718750, 380001.968750",\ + "380001.750000, 380001.750000, 380001.750000, 380001.812500, 380002.062500",\ + "380001.875000, 380001.875000, 380001.875000, 380001.937500, 380002.187500",\ + "380002.062500, 380002.062500, 380002.062500, 380002.125000, 380002.375000",\ + "380002.375000, 380002.375000, 380002.375000, 380002.437500, 380002.687500"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\ + "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\ + "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\ + "0.602094, 0.617527, 0.647677, 0.736728, 1.205538",\ + "0.602094, 0.617527, 0.647677, 0.736728, 1.205538"); + } + + } /* end of arc padmux2ast_i[4]_scan_reset_no_inv*/ + + timing () { + min_delay_flag : true ; + related_pin : "padmux2ast_i[4]" ; + timing_type : combinational ; + timing_sense : negative_unate ; + cell_fall( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380000.343750, 380000.343750, 380000.375000, 380000.468750, 380000.875000",\ + "380000.437500, 380000.437500, 380000.468750, 380000.562500, 380000.968750",\ + "380000.500000, 380000.500000, 380000.531250, 380000.625000, 380001.031250",\ + "380000.656250, 380000.656250, 380000.687500, 380000.781250, 380001.187500",\ + "380000.875000, 380000.875000, 380000.906250, 380001.000000, 380001.406250"); + } + fall_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\ + "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\ + "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\ + "0.899963, 0.924149, 0.971400, 1.110963, 1.842156",\ + "0.899963, 0.924149, 0.971400, 1.110963, 1.842156"); + } + cell_rise( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "380001.656250, 380001.656250, 380001.656250, 380001.718750, 380001.968750",\ + "380001.750000, 380001.750000, 380001.750000, 380001.812500, 380002.062500",\ + "380001.843750, 380001.843750, 380001.843750, 380001.906250, 380002.156250",\ + "380002.031250, 380002.031250, 380002.031250, 380002.093750, 380002.343750",\ + "380002.281250, 380002.281250, 380002.281250, 380002.343750, 380002.593750"); + } + rise_transition( f_itrans_ocap ){ + index_1 ( "0.000000, 0.195118, 0.455354, 1.062676, 2.480000"); + index_2 ( "0.021601, 0.022183, 0.023319, 0.026674, 0.044252"); + values ( "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\ + "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\ + "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\ + "0.599658, 0.615162, 0.645450, 0.734911, 1.203284",\ + "0.599658, 0.615162, 0.645450, 0.734911, 1.203284"); + } + + } /* end of arc padmux2ast_i[4]_scan_reset_no_inv_min*/ + +} /* end of pin scan_reset_no */ + + + + + + +} /* end of cell */ + +} /* end of library */ diff --git a/hw/top_darjeeling_no_ibex/ip/ast/lint/ast.vlt b/hw/top_darjeeling_no_ibex/ip/ast/lint/ast.vlt new file mode 100644 index 00000000000..b4c6b30d7b2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/lint/ast.vlt @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for ast + +`verilator_config + +// ast_clks_byp.sv has an always_latch block which doesn't actually do anything +// because the enable signal (!scan_mode_i) is always true. Verilator notices +// and complains, but we're doing this on purpose. +lint_off -rule NOLATCH -file "*/rtl/ast_clks_byp.sv" + +// Manually mark a clock enable: if we don't tell Verilator we're doing it on +// purpose, it will warn us that there's a path from "normal" logic through to +// a clock signal. +clock_enable -module "ast_clks_byp" -var "clk_ext_en" diff --git a/hw/top_darjeeling_no_ibex/ip/ast/lint/ast.waiver b/hw/top_darjeeling_no_ibex/ip/ast/lint/ast.waiver new file mode 100644 index 00000000000..ba1701f409a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/lint/ast.waiver @@ -0,0 +1,377 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for ast + +waive -rules CONST_FF -location {ast_clks_byp.sv} \ + -msg {Flip-flop 'sw_clk_byp_en' is driven by constant one} \ + -comment {This flip flop is supposed to change to 1 on the first clock cycle and remain there afterwards.} + +waive -rules IFDEF_CODE -location {ast.sv} \ + -msg {Assignment to 'ast2pad_t0_ao' contained within `else block at ast.sv} \ + -comment {This ifdef statement is used for analog simulations and is OK.} + +waive -rules IFDEF_CODE -location {ast.sv} \ + -msg {Assignment to 'unused_analog_sigs' contained within `ifndef 'ANALOGSIM' block at} \ + -comment {This ifdef statement is used for assigning "unused" signals and is OK.} + +waive -rules IFDEF_CODE -location {ast.sv} \ + -regexp {Assignment to 'clk_(sys|usb|aon|io)_ext' contained within `ifdef 'AST_BYPASS_CLK' block at} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \ + -regexp {Assignment to '(sys|usb|aon|io)_clk_dly' contained within `else block at} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \ + -regexp {Assignment to 'en_osc_re' contained within} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {aon_osc.sv} \ + -regexp {Assignment to 'clk' contained within} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules CLOCK_EDGE -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \ + -msg {Falling edge of clock 'clk' used here, should use rising edge} \ + -comment {This negedge trigger is done on purpose.} + +waive -rules CLOCK_EDGE -location {ast_clks_byp.sv} \ + -msg {Falling edge of clock 'clk_ast_ext_scn' used here, should use rising edge} \ + -comment {This negedge trigger is done on purpose.} + +waive -rules CLOCK_EDGE -location {ast_clks_byp.sv} \ + -msg {'prim_flop_2sync' instance 'u_no_scan_ext_freq_is_96m_sync' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifdef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules CLOCK_DRIVER -location {ast.sv} \ + -regexp {'clk_src_(aon|io|sys|usb)' is driven by instance 'u_ast_clks_byp' of module 'ast_clks_byp', and used as a clock 'clk_i' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast.sv} \ + -regexp {'clk_src_(aon|io|sys)' in module 'ast_clks_byp' by port} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast.sv} \ + -msg {'clk_o' driven in module 'gfr_clk_mux2' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \ + -msg {'clk_o' driven in module 'gfr_clk_mux2' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'clk_src_(aon|io)_o' is driven by instance 'u_clk_src_(aon|io)_sel' of module 'gfr_clk_mux2', and used as a clock 'clk_i' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'clk_src_io' is driven by instance 'u_clk_src_io_sel' of module 'gfr_clk_mux2', and used as a clock 'clk_i' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'clk_ext_scn' is driven here, and used as a clock 'clk_i' at} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_MUX -location {ast_clks_byp.sv} \ + -regexp {Clock '(clk_ast_ext_scn|clk_ext_scn|clk_src_ext_usb|clk_ext_aon)' is driven by a multiplexer here, used as a clock} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules CLOCK_MUX -location {ast_clks_byp.sv} \ + -regexp {Clock 'clk_ast_ext' reaches a multiplexer here, used as a clock} \ + -comment {This is clock generation logic, hence it needs to drive this clock signal.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {Assignment to 'clk_ast_ext_scn' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {Assignment to 'clk_ext_scn' contained within `else block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {Assignment to 'clk_src_io_val_o' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {'prim_clock_div' instance 'u_no_scan_clk_(ext_d1ord2|usb_div240_div)' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {'prim_flop_2sync' instance 'u_no_scan_ext_freq_is_96m_sync' contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules IFDEF_CODE -location {ast_clks_byp.sv} \ + -regexp {always_latch block contained within `ifndef 'AST_BYPASS_CLK' block at} \ + -comment {This ifndef statement is fine as it is part of the FPGA/Verilator clock bypass mechanism.} + +waive -rules CLOCK_MUX -location {ast.sv} \ + -regexp {Clock 'clk_aon_n' is driven by a multiplexer here, used as a clock} \ + -comment {This clock inverter has a DFT mux.} + +waive -rules CLOCK_MUX -location {rglts_pdm_3p3v.sv} \ + -regexp {Clock 'clk_src_aon_h_n' is driven by a multiplexer here, used as a clock at } \ + -comment {This signal has a DFT mux.} + +waive -rules CLOCK_USE -location {gfr_clk_mux2.sv} \ + -regexp {('clk_ext'|'clk_osc') is used for some other purpose, and as clock ('clk_ext_i'|'clk_osc_i') at gfr_clk_mux2.sv} \ + -comment {This message pops up due to a clock OR operation.} + +waive -rules CLOCK_USE -location {ast.sv} \ + -regexp {'clk_ast_tlul_i' is connected to 'ast_dft' port 'clk_i', and used as a clock 'clk_i' at prim_lfsr} \ + -comment {This is a valid clock signal and the LFSR runs on the bus clock here.} + +waive -rules CLOCK_USE -location {ast.sv} \ + -regexp {'clk_aon' is connected to 'rglts_pdm_3p3v' port 'clk_src_aon_h_i', and used as a clock} \ + -comment {This is a valid clock signal and the connection is ok here.} + +waive -rules CLOCK_USE -location {ast.sv} \ + -regexp {'clk_ast_usb_i' is used for some other purpose, and as clock 'clk_i' at prim_flop.sv} \ + -comment {This is a valid clock signal and the connection is ok here.} + +waive -rules INV_CLOCK -location {ast.sv rglts_pdm_3p3v.sv} \ + -regexp {'(clk_aon|clk_src_aon_h_i)' is inverted, used as clock} \ + -comment {These clocks are inverted.} + +waive -rules RESET_DRIVER -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ + -msg {'rst_val_n' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ + -regexp {'(aon|io|sys|usb)_clk_en' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {rng.sv} \ + -msg {'rst_n' is driven here, and used as an asynchronous reset at rng.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'(vcaon_pok_h|por_rst_n|vcmain_pok_por|vcmain_pok_por_src)' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'clk_io_osc_val' is driven by instance 'u_io_clk' of module 'io_clk', and used as an asynchronous reset 'rst_clk_osc_n' at ast_dft.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'clk_src_io_val_o' driven in module 'io_clk' by port 'u_val_sync.q_o[0]' at io_clk.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv dev_entropy.sv ast_clks_byp.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port .* at prim_flop_2sync.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'vcmain_pok_por_sys' is driven by instance 'u_rst_sys_dasrt' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_dev_ni' at dev_entropy.sv} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {dev_entropy.sv} \ + -msg {'rst_es_dev_nd' is driven by instance 'u_rst_es_n_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_es_dev_n'} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {dev_entropy.sv} \ + -msg {'rst_es_dev_nd' is driven by instance 'u_rst_es_n_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_es_dev_n'} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {dev_entropy.sv} \ + -msg {'rst_es_dev_da_n' is driven by instance 'u_rst_es_n_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_es_dev_n' at} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {dev_entropy.sv} \ + -msg {'rst_es_dev_in_n' is driven here, and used as an asynchronous reset 'rst_ni' at} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast_pulse_sync.sv} \ + -regexp {'(rst_src_n|rst_dst_n)' is driven here, and used as an asynchronous reset at} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'rst_aon_n_(ioda|exda)' is driven by instance 'u_rst_aon_n_(ioda|exda)_sync' of module} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast_clks_byp.sv} \ + -regexp {'rst_sw_clk_byp_en' is driven here, and used as an asynchronous reset 'rst_sw_ckbpe_n'} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'(vcc_pok|rst_poks_n|rst_poks_por_n|vcaon_pok_por_lat)' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'vcmain_pok_por_sys' is driven by instance 'u_rst_sys_dasrt' of module} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -msg {'rst_aon_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at} \ + -comment {This is reset generation logic, hence it needs to drive this reset signal.} + +waive -rules RESET_DRIVER -location {rglts_pdm_3p3v.sv} \ + -regexp {'(vcc_pok_rst_h_n|vcc_pok_set_h|vcc_pok_str_.*|)' is driven here, and used as an asynchronous reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'(vcaon_pok|vcaon_pok_h)' is driven by instance 'u_rglts_pdm_3p3v'} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'(vcaon_pok_1p1_h_o|vcaon_pok_h_o)' driven in module 'rglts_pdm_3p3v'} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'rst_sys_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'rst_usb_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {ast.sv} \ + -regexp {'rst_io_clk_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'rst_da_n' is driven by instance 'u_rst_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port 'u_sync_2.q_o[0]' at prim_flop_2sync.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' by port 'gen_generic.u_impl_generic.q_o[0]' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'rst_n' is driven here, and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'rst_n' driven in module 'usb_clk' by 'rst_da_n' at usb_clk.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port 'u_sync_2.q_o[0]' at prim_flop_2sync.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' by port 'gen_generic.u_impl_generic.q_o[0]' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'rst_usb_n' is driven by instance 'u_rst_ast_usb_da' of module 'prim_flop_2sync', and used as an asynchronous reset 'rst_ni' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop_2sync' by port 'u_sync_2.q_o[0]' at prim_flop_2sync.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' by port 'gen_generic.u_impl_generic.q_o[0]' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_DRIVER -location {usb_clk.sv} \ + -regexp {'q_o[0]' driven in module 'prim_flop' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ + -msg {Asynchronous reset 'rst_val_n' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {ast.sv} \ + -regexp {Asynchronous reset '(rst_poks_n|rst_poks_por_n|vcmain_pok_por|rst_src_sys_n|vcaon_pok_por)' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {rng.sv} \ + -msg {Asynchronous reset 'rst_n' is driven by a multiplexer here, used as a reset at rng.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {ast_clks_byp.sv} \ + -regexp {Asynchronous reset '(rst_aon_n|rst_aon_exda_n|rst_aon_ioda_n|rst_sw_ckbpe_n)' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {ast_pulse_sync.sv} \ + -regexp {Asynchronous reset '(rst_src_n|rst_dst_n)' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {rglts_pdm_3p3v.sv} \ + -msg {Asynchronous reset 'vcc_pok_rst_h_n' is driven by a multiplexer here, used as a reset} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_MUX -location {usb_clk.sv} \ + -regexp {Asynchronous reset 'rst_n' is driven by a multiplexer here, used as a reset 'rst_ni' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {('vcore_pok_h_i'|'vcaon_pok') is used for some other purpose, and as asynchronous reset} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {'(vcmain_pok_por|vcmain_pok_por_src)' is connected to 'rglts_pdm_3p3v' port 'vcmain_pok_por_h_i', and used as an asynchronous reset or set} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -msg {'vcaon_pok_por' is connected to 'rglts_pdm_3p3v' port 'vcaon_pok_por_h_i', and used as an asynchronous reset or set} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {'(vcc_pok|vcmain_pok_por)' is used for some other purpose, and as asynchronous reset} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {'rst_(usb|aon|io|sys)_clk_n' is connected to '(usb|aon|io|sys)_clk' port 'rst_(usb|aon|io|sys)_clk_ni', and used as an asynchronous reset or set ('rst_ni'|'vcore_pok_h_i'|'rst_clk_byp_n')} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {io_osc.sv sys_osc.sv usb_osc.sv aon_osc.sv} \ + -msg {'vcore_pok_h_i' is used for some other purpose, and as asynchronous reset at} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast_dft.sv} \ + -msg {'clk_io_osc_val_i' is used for some other purpose, and as asynchronous reset 'rst_clk_osc_n' at ast_dft.sv} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -msg {'rst_ast_tlul_ni' is connected to 'ast_dft' port 'rst_ni', and used as an asynchronous reset or set 'rst_n' at rng} \ + -comment {This is a valid reset connection.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {('rst_sys_clk_n'|'rst_usb_clk_n') is connected to ('sys_clk'|'usb_clk') port ('rst_sys_clk_ni'|'rst_usb_clk_ni'), and used as an asynchronous reset or set} \ + -comment {This is a valid reset connection.} + +waive -rules RESET_USE -location {aon_clk.sv io_clk.sv sys_clk.sv usb_clk.sv} \ + -regexp {'(aon|io|sys|usb)_clk_en' is connected to '(aon|io|sys|usb)_osc' port '(aon|io|sys|usb)_en_i', and used as an asynchronous reset or set} \ + -comment {This is reset / clock generation logic, hence special reset usage is allowed.} + +waive -rules RESET_USE -location {ast.sv} \ + -regexp {'rst_ast_usb_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules RESET_USE -location {usb_clk.sv} \ + -regexp {'rst_usb_clk_ni' is used for some other purpose, and as asynchronous reset 'rst_ni' at prim_flop.sv} \ + -comment {This is reset generation logic, hence reset muxes are allowed.} + +waive -rules TRI_DRIVER -location {ast.sv} \ + -regexp {'ast2pad_(t0|t1)_ao' is driven by a tristate driver} \ + -comment {This part models a tristate driver.} + +waive -rules TERMINAL_STATE -location {rglts_pdm_3p3v.sv} \ + -msg {Terminal state 'RGLS_BROUT' is detected. State register 'rgls_sm' is not assigned to another state.} \ + -comment {The brownout state is terminal.} + +waive -rules Z_USE -location {ast.sv} \ + -msg {Constant with 'Z literal value '1'bz' encountered} \ + -comment {This part models a tristate driver.} + +waive -rules MULTI_RESET -location {rglts_pdm_3p3v.sv} \ + -msg {Found 2 asynchronous resets for this block: 'vcc_pok_rst_h_n', 'vcc_pok_set_h'} \ + -comment {This code is only a model and hence this is allowed.} + +waive -rules NOT_READ -location {aon_osc.sv io_osc.sv sys_osc.sv usb_osc.sv} \ + -msg {Signal 'en_osc' is not read from in module} \ + -comment {Signal 'en_osc' is not read when SYNTHESIS is defined, and AST_BYPASS_CLK is not defined.} diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/adc.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/adc.sv new file mode 100644 index 00000000000..2ebf0890e56 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/adc.sv @@ -0,0 +1,137 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: adc +// *Module Description: Analog/Digital Converter +//############################################################################ + +module adc #( + parameter int unsigned AdcCnvtClks = 19,// 21cc from adc_chnsel_i change to adc_d_val_o assertion + parameter int AdcChannels = 2, // ADC number of Channels + parameter int AdcDataWidth = 10 +) ( + input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input + input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input + input [AdcChannels-1:0] adc_chnsel_i, // Onehot value only for selrction + input adc_pd_i, // ADC Power Down + input clk_adc_i, // ADC Clock (aon_clk - 200KHz) + input rst_adc_ni, // ADC Reset active low + output logic [AdcDataWidth-1:0] adc_d_o, // ADC 10-bit Data Output + output logic adc_d_val_o // ADC Data Valid Output +); + +/////////////////////////////////////// +// ADC Enable +/////////////////////////////////////// +logic adc_en; + +always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin + if ( !rst_adc_ni ) begin + adc_en <= 1'b0; + end else begin + adc_en <= !adc_pd_i; + end +end + + +/////////////////////////////////////// +// ADC Channel Select +/////////////////////////////////////// +logic chn_selected, chn_selected_d, new_convert, adc_busy; + +assign chn_selected = |(adc_chnsel_i); + +always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin + if ( !rst_adc_ni ) begin + chn_selected_d <= 1'b0; + end else begin + chn_selected_d <= chn_selected; + end +end + +// New Convertion +assign new_convert = chn_selected && !chn_selected_d && !adc_busy; + +//////////////////////////////////////// +// ADC Analog Model +//////////////////////////////////////// +logic [10-1:0] adc_d_ch0, adc_d_ch1; + +adc_ana u_adc_ana ( + .adc_a0_ai ( adc_a0_ai ), + .adc_a1_ai ( adc_a1_ai ), + .adc_d_ch0_o ( adc_d_ch0[10-1:0] ), + .adc_d_ch1_o ( adc_d_ch1[10-1:0] ) +); + + +//////////////////////////////////////// +// ADC Digital Model +//////////////////////////////////////// +logic [8-1:0] cnv_cyc; +logic [8-1:0] ConvertCount; + +assign ConvertCount = AdcCnvtClks[8-1:0]; + +always_ff @( posedge clk_adc_i, negedge rst_adc_ni ) begin + if (!rst_adc_ni ) begin + cnv_cyc <= 8'h00; + adc_busy <= 1'b0; + adc_d_val_o <= 1'b0; + adc_d_o <= {AdcDataWidth{1'b0}}; + end else if ( !(adc_en && chn_selected) ) begin + cnv_cyc <= 8'h00; + adc_busy <= 1'b0; + adc_d_val_o <= 1'b0; + end else if ( new_convert ) begin + cnv_cyc <= ConvertCount; + adc_busy <= 1'b1; + adc_d_val_o <= 1'b0; + end else if ( adc_busy && (cnv_cyc > 8'h00) ) begin + cnv_cyc <= cnv_cyc - 1'b1; + adc_busy <= 1'b1; + adc_d_val_o <= 1'b0; + end else if ( adc_busy ) begin + adc_busy <= 1'b0; + adc_d_val_o <= 1'b1; + adc_d_o <= (adc_chnsel_i[1:0] == 2'b00) ? adc_d_o : + (adc_chnsel_i[1:0] == 2'b01) ? adc_d_ch0[10-1:0] : + (adc_chnsel_i[1:0] == 2'b10) ? adc_d_ch1[10-1:0] : + {AdcDataWidth{1'b1}}; + end +end + +///////////////////////// +// ASSERTIONS +///////////////////////// +// Add Assertion mux selector is onehot - zero is allowed +`ASSERT(AdcChnselOneHot_A, $onehot0(adc_chnsel_i), clk_adc_i, !rst_adc_ni) + +// Add Assertion adc_en=0 chnsel is 0. +`ASSERT(NoChannelWhileDisabled_A, (adc_en == 0) |-> (adc_chnsel_i == 4'h0), clk_adc_i, !rst_adc_ni) + +// The power up time period is 30us throughout which the adc_chnsel_i needs to be stable at 0. +// Since we are dealing with a time period here, and not clock cycles, we need to make sure +// that we sample and check enough clock ticks in order to guarantee the timing is met. +// Assuming that the clk_adc_i period is 200kHz, this SVA makes sure that: +// +// a) the signal adc_chnsel_i was 0 before adc_pd_i fell. this is achieved by sampling +// and checking on clock edges (-1) ... 0 in the illustration below. +// b) the signal adc_chnsel_i remained at 0 for at least 30us after adc_pd_i fell. +// this is achieved by sampling and checking on clock edges 0 ... 6 which cover a +// time period of 6 x 5us as shown in the illustration below. +// ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ +// clk_ast_adc_i : | |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__ +// ___________ +// adc_pd_i : | |_______________________________________________________ +// +// adc_chnsel_i : xxxxxx___________________________________________________xxxxxxxxx +// +// ChannelStableOnAdcEn_A: | | | | | | | | +// -1 0 1 2 3 4 5 6 +// <------------ 6 x 5us = 30us -----------> +`ASSERT(ChannelStableOnAdcEn_A, + $fell(adc_pd_i) |-> ($past(adc_chnsel_i) == 4'h0)[*8], clk_adc_i, !rst_adc_ni) + +endmodule : adc diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/adc_ana.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/adc_ana.sv new file mode 100644 index 00000000000..6f4b6409be4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/adc_ana.sv @@ -0,0 +1,45 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: sdc_ana +// *Module Description: ADC Analog +//############################################################################ + +module adc_ana ( + input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input + input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input + output logic [10-1:0] adc_d_ch0_o, // ADC A0 Digital Output + output logic [10-1:0] adc_d_ch1_o // ADC A1 Digital Output +); + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +real vref = 2.3; +real adc_vi0_hook = 1.0; +real adc_vi1_hook = 1.0; +real adc_vi0, adc_vi1; + +`ifdef ANALOGSIM +assign adc_vi0 = adc_a0_ai; +assign adc_vi1 = adc_a1_ai; +`else +assign adc_vi0 = adc_a0_ai ? adc_vi0_hook : 0.0; +assign adc_vi1 = adc_a1_ai ? adc_vi1_hook : 0.0; +`endif +assign adc_d_ch0_o = $rtoi((adc_vi0/vref) * $itor(10'h3ff)); +assign adc_d_ch1_o = $rtoi((adc_vi1/vref) * $itor(10'h3ff)); +`else // of SYNTHESIS +// FPGA/VERILATOR +//////////////////////////////////////// +logic [10-1:0] adc_d_vi0_hook, adc_d_vi1_hook; + +assign adc_d_vi0_hook = 10'h155; +assign adc_d_vi1_hook = 10'h2AA; + +assign adc_d_ch0_o = adc_a0_ai ? adc_d_vi0_hook : 10'h000; +assign adc_d_ch1_o = adc_a1_ai ? adc_d_vi1_hook : 10'h000; +`endif + +endmodule : adc_ana diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/aon_clk.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/aon_clk.sv new file mode 100644 index 00000000000..86379bb82f0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/aon_clk.sv @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: aon_clk +// *Module Description: Always ON Clock +//############################################################################ + +module aon_clk ( + input vcore_pok_h_i, // VCORE POK @3.3V (for OSC) + input clk_aon_pd_ni, // AON Clock Power-down + input rst_aon_clk_ni, // AON Clock Logic reset + input clk_src_aon_en_i, // AON Source Clock Enable + input scan_mode_i, // Scan Mode + input aon_osc_cal_i, // AON Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_aon_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic clk_src_aon_o, // AON Source Clock + output logic clk_src_aon_val_o // AON Source Clock Valid +); + +logic clk, osc_en, aon_clk_en; + +assign osc_en = (clk_src_aon_en_i && clk_aon_pd_ni && rst_aon_clk_ni); +assign aon_clk_en = scan_mode_i || osc_en; + +// Clock Oscillator +/////////////////////////////////////// +aon_osc u_aon_osc ( + .vcore_pok_h_i ( vcore_pok_h_i ), + .aon_en_i ( aon_clk_en ), + .aon_osc_cal_i ( aon_osc_cal_i ), +`ifdef AST_BYPASS_CLK + .clk_aon_ext_i ( clk_aon_ext_i ), +`endif + .aon_clk_o ( clk ) +); // of u_aon_osc + +// Clock & Valid +/////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_aon_buf( + .clk_i ( clk ), + .clk_o ( clk_src_aon_o ) +); + +// 2-stage de-assertion +logic rst_val_n; +assign rst_val_n = aon_clk_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_val_sync ( + .clk_i ( clk_src_aon_o ), + .rst_ni ( rst_val_n ), + .d_i ( 1'b1 ), + .q_o ( clk_src_aon_val_o ) +); + +endmodule : aon_clk diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/aon_osc.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/aon_osc.sv new file mode 100644 index 00000000000..c18e51c4c08 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/aon_osc.sv @@ -0,0 +1,132 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: aon_osc +// *Module Description: AON Clock Oscilator +//############################################################################ + +module aon_osc ( + input vcore_pok_h_i, // VCORE POK @3.3V + input aon_en_i, // AON Source Clock Enable + input aon_osc_cal_i, // AON Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_aon_ext_i, // FPGA/VERILATOR Clock input\ +`endif + output logic aon_clk_o // AON Clock Output +); + +`ifndef AST_BYPASS_CLK +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +timeunit 1ns / 10ps; + +real CLK_PERIOD, ckmul; + +reg init_start; +initial init_start = 1'b0; + +initial begin + if ( !$value$plusargs("osc200k_freq_multiplier=%f", ckmul) ) ckmul = 1.0; + #1; + init_start = 1'b1; + #1; + $display("\n%m: AON Base Clock Power-up Frequency: %0d Hz", $rtoi(10**9/(CLK_PERIOD*ckmul))); + $display("%m: AON %0.1fxBase Clock Power-up Frequency: %0d Hz", ckmul, $rtoi(10**9/CLK_PERIOD)); +end + +// Enable 5us RC Delay on rise +wire en_osc_re_buf, en_osc_re; +buf #(ast_bhv_pkg::AON_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && aon_en_i)); +assign en_osc_re = en_osc_re_buf && init_start; + +// Clock Oscillator +//////////////////////////////////////// +real CalAonClkPeriod, UncAonClkPeriod, AonClkPeriod; + +initial CalAonClkPeriod = $itor( 5000 ); // 5000ns (200KHz) +initial UncAonClkPeriod = $itor( $urandom_range(10000, 5555) ); // 10000-5555ps (100-180KHz) + +assign AonClkPeriod = (aon_osc_cal_i && init_start) ? CalAonClkPeriod : UncAonClkPeriod; +assign CLK_PERIOD = AonClkPeriod/ckmul; + +// Free running oscillator +reg clk_osc; +initial clk_osc = 1'b1; + +always begin + #(CLK_PERIOD/2) clk_osc = ~clk_osc; +end + +logic en_osc; + +// HDL Clock Gate +logic en_clk, clk; + +always_latch begin + if ( !clk_osc ) en_clk = en_osc; +end + +assign clk = clk_osc && en_clk; +`else // of SYNTHESIS +// SYNTHESIS/LINTER +/////////////////////////////////////// +logic clk, en_osc; +assign clk = 1'b0; + +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && aon_en_i; +`endif // of SYNTHESIS +`else // of AST_BYPASS_CLK +// VERILATOR/FPGA +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && aon_en_i; + +// Clock Oscillator +//////////////////////////////////////// +logic clk, en_osc; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1 ) +) u_clk_ckgt ( + .clk_i ( clk_aon_ext_i ), + .en_i ( en_osc ), + .test_en_i ( 1'b0 ), + .clk_o ( clk ) +); +`endif + +logic en_osc_fe; + +// Syncronize en_osc to clk FE for glitch free disable +always_ff @( negedge clk, negedge vcore_pok_h_i ) begin + if ( !vcore_pok_h_i ) begin + en_osc_fe <= 1'b0; + end else begin + en_osc_fe <= en_osc_re; + end +end + +assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0 + +// Clock Output Buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_buf ( + .clk_i ( clk ), + .clk_o ( aon_clk_o ) +); + + +`ifdef SYNTHESIS +/////////////////////// +// Unused Signals +/////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ aon_osc_cal_i }; +`endif + +endmodule : aon_osc diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast.sv new file mode 100644 index 00000000000..fc078225665 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast.sv @@ -0,0 +1,1045 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +//############################################################################ +// *Name: ast +// *Module Description: Analog Sensors Top +//############################################################################ + +`include "prim_assert.sv" + +module ast + import ast_pkg::EntropyStreams; +#( + parameter int unsigned AdcChannels = 2, + parameter int unsigned AdcDataWidth = 10, + parameter int unsigned UsbCalibWidth = 20, + parameter int unsigned Ast2PadOutWidth = 9, + parameter int unsigned Pad2AstInWidth = 9 +) ( + // tlul if + input tlul_pkg::tl_h2d_t tl_i, // TLUL H2D + output tlul_pkg::tl_d2h_t tl_o, // TLUL D2H + output prim_mubi_pkg::mubi4_t ast_init_done_o, // AST (registers) Init Done + + // clocks / resets + input clk_ast_adc_i, // Buffered AST ADC Clock + input rst_ast_adc_ni, // Buffered AST ADC Reset + input clk_ast_alert_i, // Buffered AST Alert Clock + input rst_ast_alert_ni, // Buffered AST Alert Reset + input clk_ast_rng_i, // Buffered AST RNG Clock + input rst_ast_rng_ni, // Buffered AST RNG Reset + input clk_ast_tlul_i, // Buffered AST TLUL Clock + input rst_ast_tlul_ni, // Buffered AST TLUL Reset + input clk_ast_usb_i, // Buffered AST USB Clock + input rst_ast_usb_ni, // Buffered AST USB Reset + input clk_ast_ext_i, // Buffered AST External Clock + input por_ni, // Power ON Reset + + // sensed clocks / resets + input clkmgr_pkg::clkmgr_out_t sns_clks_i, // Sensed Clocks + input rstmgr_pkg::rstmgr_out_t sns_rsts_i, // Sensed Resets + input sns_spi_ext_clk_i, // Sensed SPI External Clock + +`ifdef AST_BYPASS_CLK + // Clocks' Oschillator bypass for OS FPGA + input ast_pkg::clks_osc_byp_t clk_osc_byp_i, // Clocks' Oschillator bypass for OS FPGA/VERILATOR +`endif + + // power OK control + // In non-power aware DV environment, the <>_supp_i is for debug only! + // POK signal follow this input. + // In a power aware environment this signal should be connected to constant '1' + input vcc_supp_i, // VCC Supply Test for OS FPGA + input vcaon_supp_i, // VCAON Supply Test for OS FPGA + input vcmain_supp_i, // VCMAIN Supply Test for OS FPGA + input vioa_supp_i, // VIOA Rail Supply Test for OS FPGA + input viob_supp_i, // VIOB Rail Supply Test for OS FPGA + output ast_pkg::ast_pwst_t ast_pwst_o, // AON, MAIN, IO-0 Rail, IO-1 Rail Power OK @1.1V + output ast_pkg::ast_pwst_t ast_pwst_h_o, // AON, MAIN, IO-9 Rail, IO-1 Rail Power OK @3.3V + + // Power and IO pin connections + input main_pd_ni, // MAIN Regulator Power Down + input main_env_iso_en_i, // Enveloped ISOlation ENable for MAIN + + // power down monitor logic - flash/otp related + output logic flash_power_down_h_o, // Flash Power Down + output logic flash_power_ready_h_o, // Flash Power Ready + input [1:0] otp_power_seq_i, // MMR0,24 in (VDD) + output logic [1:0] otp_power_seq_h_o, // MMR0,24 masked by PDM, out (VCC) + + // system source clock + input clk_src_sys_en_i, // SYS Source Clock Enable + input prim_mubi_pkg::mubi4_t clk_src_sys_jen_i, // SYS Source Clock Jitter Enable + output logic clk_src_sys_o, // SYS Source Clock + output logic clk_src_sys_val_o, // SYS Source Clock Valid + + // aon source clock + output logic clk_src_aon_o, // AON Source Clock + output logic clk_src_aon_val_o, // AON Source Clock Valid + + // io source clock + input clk_src_io_en_i, // IO Source Clock Enable + output logic clk_src_io_o, // IO Source Clock + output logic clk_src_io_val_o, // IO Source Clock Valid + output prim_mubi_pkg::mubi4_t clk_src_io_48m_o, // IO Source Clock is 48MHz + + // usb source clock + input usb_ref_pulse_i, // USB Reference Pulse + input usb_ref_val_i, // USB Reference Valid + input clk_src_usb_en_i, // USB Source Clock Enable + output logic clk_src_usb_o, // USB Source Clock + output logic clk_src_usb_val_o, // USB Source Clock Valid + output logic [UsbCalibWidth-1:0] usb_io_pu_cal_o, // USB IO Pull-up Calibration Setting + + // adc interface + input adc_pd_i, // ADC Power Down + input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input + input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input + input [AdcChannels-1:0] adc_chnsel_i, // ADC Channel Select + output [AdcDataWidth-1:0] adc_d_o, // ADC Digital (per channel) + output adc_d_val_o, // ADC Digital Valid + + // rng (entropy source) interface + input rng_en_i, // RNG Enable + input rng_fips_i, // RNG FIPS + output logic rng_val_o, // RNG Valid + output logic [EntropyStreams-1:0] rng_b_o, // RNG Bit(s) + + // alerts + input ast_pkg::ast_alert_rsp_t alert_rsp_i, // Alerts Trigger & Acknowledge Inputs + output ast_pkg::ast_alert_req_t alert_req_o, // Alerts Output + + // dft interface + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, // DFT enable (secure bus) + input [8-1:0] fla_obs_i, // FLASH Observe Bus + input [8-1:0] otp_obs_i, // OTP Observe Bus + input [8-1:0] otm_obs_i, // OT Modules Observe Bus + input usb_obs_i, // USB DIFF RX Observe + output ast_pkg::ast_obs_ctrl_t obs_ctrl_o, // Observe Control + + // pad mux/pad related + input [Pad2AstInWidth-1:0] padmux2ast_i, // IO_2_DFT Input Signals + output logic [Ast2PadOutWidth-1:0] ast2padmux_o, // DFT_2_IO Output Signals + +`ifdef ANALOGSIM + output real ast2pad_t0_ao, // AST_2_PAD Analog T0 Output Signal + output real ast2pad_t1_ao, // AST_2_PAD Analog T1 Output Signal +`else + output wire ast2pad_t0_ao, // AST_2_PAD Analog T0 Output Signal + output wire ast2pad_t1_ao, // AST_2_PAD Analog T1 Output Signal +`endif + + // flash and external clocks + input prim_mubi_pkg::mubi4_t ext_freq_is_96m_i, // External clock frequecy is 96MHz + input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // All clocks bypass request + output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o, // Switch all clocks to External clocks + input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // IO clock bypass request (for OTP bootstrap) + output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o, // Switch IO clock to External clockn + output prim_mubi_pkg::mubi4_t flash_bist_en_o, // Flush BIST (TAP) Enable + + // memories read-write margins + output ast_pkg::dpm_rm_t dpram_rmf_o, // Dual Port RAM Read-write Margin Fast + output ast_pkg::dpm_rm_t dpram_rml_o, // Dual Port RAM Read-write Margin sLow + output ast_pkg::spm_rm_t spram_rm_o, // Single Port RAM Read-write Margin + output ast_pkg::spm_rm_t sprgf_rm_o, // Single Port Reg-File Read-write Margin + output ast_pkg::spm_rm_t sprom_rm_o, // Single Port ROM Read-write Margin + + // Scan interface + output prim_mubi_pkg::mubi4_t dft_scan_md_o, // Scan Mode output + output scan_shift_en_o, // Scan Shift Enable output + output scan_reset_no // Scan Reset output +); + +import ast_pkg::* ; +import ast_reg_pkg::* ; +import ast_bhv_pkg::* ; + +logic scan_mode, shift_en, scan_reset_n; +logic vcc_pok, vcc_pok_h, vcc_pok_str; +logic vcaon_pok, vcaon_pok_h, vcmain_pok; +logic vcaon_pok_por, vcmain_pok_por; + +// Local (AST) System clock buffer +//////////////////////////////////////// +logic clk_sys; + +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_sys_buf ( + .clk_i ( clk_src_sys_o ), + .clk_o ( clk_sys ) +); + +// Local (AST) AON clock buffer +//////////////////////////////////////// +logic clk_aon; + +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_aon_buf ( + .clk_i ( clk_src_aon_o ), + .clk_o ( clk_aon ) +); + + +assign flash_bist_en_o = prim_mubi_pkg::MuBi4False; +// +assign dft_scan_md_o = prim_mubi_pkg::MuBi4False; +assign scan_shift_en_o = 1'b0; +assign scan_reset_no = 1'b1; +assign scan_mode = 1'b0; +assign shift_en = 1'b0; +assign scan_reset_n = 1'b1; + + +/////////////////////////////////////// +// VCC POK (Always ON) +/////////////////////////////////////// +logic vcc_pok_int; + +vcc_pgd u_vcc_pok ( + .vcc_pok_o ( vcc_pok_int ) +); + +assign vcc_pok = vcc_pok_int && vcc_supp_i; +assign vcc_pok_h = vcc_pok; // "Level Shifter" + + +//////////////////////////////////////// +// VCAON POK POR (Always ON) +/////////////////////////////////////// +logic rst_poks_n, rst_poks_por_n, por_sync_n; +logic vcaon_pok_por_src, vcaon_pok_por_lat, poks_por_ack, rglssm_vcmon, rglssm_brout; + +assign rst_poks_n = vcc_pok_str && vcaon_pok; +assign rst_poks_por_n = vcc_pok_str && vcaon_pok && por_ni; +assign poks_por_ack = vcaon_pok_por_src || rglssm_vcmon; + +// Reset De-Assert Sync +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_poks_por_dasrt ( + .clk_i ( clk_aon ), + .rst_ni ( rst_poks_por_n ), + .d_i ( poks_por_ack ), + .q_o ( vcaon_pok_por_src ) +); + +logic clk_aon_n; + +prim_clock_inv #( + .HasScanMode ( 1 ) +) u_clk_aon_inv ( + .clk_i ( clk_aon ), + .scanmode_i ( scan_mode ), + .clk_no ( clk_aon_n ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_por_sync_n ( + .clk_i ( clk_aon_n ), + .rst_ni ( rst_poks_n ), + .d_i ( vcaon_pok_por_src ), + .q_o ( por_sync_n ) +); + +// Replace Latch for the OS code +assign vcaon_pok_por_lat = rglssm_brout || por_sync_n; +assign ast_pwst_o.aon_pok = vcaon_pok_por_lat; +assign vcaon_pok_por = scan_mode ? scan_reset_n : vcaon_pok_por_lat; + + +//////////////////////////////////////// +// VCMAIN POK POR (Always ON) +/////////////////////////////////////// +logic rglssm_vmppr, vcmain_pok_por_src; + +assign vcmain_pok_por_src = vcaon_pok_por_lat && vcmain_pok && !rglssm_vmppr; +assign ast_pwst_o.main_pok = vcmain_pok_por_src; +assign vcmain_pok_por = scan_mode ? scan_reset_n : vcmain_pok_por_src; + + +/////////////////////////////////////// +// VIOA POK (Always ON) +/////////////////////////////////////// +logic vioa_pok; +logic vioa_pok_int; + +vio_pgd u_vioa_pok ( + .vio_pok_o ( vioa_pok_int ) +); + +assign vioa_pok = vioa_pok_int && vioa_supp_i; +assign ast_pwst_o.io_pok[0] = vcaon_pok && vioa_pok; + + +/////////////////////////////////////// +// VIOB POK (Always ON) +/////////////////////////////////////// +logic viob_pok; +logic viob_pok_int; + +vio_pgd u_viob_pok ( + .vio_pok_o ( viob_pok_int ) +); + +assign viob_pok = viob_pok_int && viob_supp_i; +assign ast_pwst_o.io_pok[1] = vcaon_pok && viob_pok; + + +/////////////////////////////////////// +// Regulators & PDM Logic (VCC) +/////////////////////////////////////// +logic deep_sleep; +logic main_pd, por_sync; + +assign main_pd = !main_pd_ni; +assign por_sync = !por_sync_n; + +rglts_pdm_3p3v u_rglts_pdm_3p3v ( + .vcc_pok_h_i ( vcc_pok_h ), + .vcaon_pok_por_h_i ( vcaon_pok_por_src ), + .vcmain_pok_por_h_i ( vcmain_pok_por_src ), + .vio_pok_h_i ( ast_pwst_o.io_pok[1:0] ), + .clk_src_aon_h_i ( clk_aon ), + .main_pd_h_i ( main_pd ), + .por_sync_h_i ( por_sync ), + .scan_mode_h_i ( scan_mode ), + .otp_power_seq_h_i ( otp_power_seq_i[2-1:0] ), + .vcaon_supp_i ( vcaon_supp_i ), + .vcmain_supp_i ( vcmain_supp_i ), + .rglssm_vmppr_h_o ( rglssm_vmppr ), + .rglssm_vcmon_h_o ( rglssm_vcmon ), + .rglssm_brout_h_o ( rglssm_brout ), + .vcmain_pok_h_o ( vcmain_pok ), + .vcmain_pok_por_h_o ( ast_pwst_h_o.main_pok ), + .vcaon_pok_h_o ( vcaon_pok_h ), + .vcaon_pok_1p1_h_o ( vcaon_pok ), + .vcaon_pok_por_h_o ( ast_pwst_h_o.aon_pok ), + .vio_pok_h_o ( ast_pwst_h_o.io_pok[2-1:0] ), + .vcc_pok_str_h_o ( ast_pwst_h_o.vcc_pok ), + .vcc_pok_str_1p1_h_o ( vcc_pok_str ), + .deep_sleep_h_o ( deep_sleep ), + .flash_power_down_h_o ( flash_power_down_h_o ), + .flash_power_ready_h_o ( flash_power_ready_h_o ), + .otp_power_seq_h_o ( otp_power_seq_h_o[2-1:0] ) +); + +assign ast_pwst_o.vcc_pok = vcc_pok_str; + + +/////////////////////////////////////// +/////////////////////////////////////// +// Clocks Oscillattors +/////////////////////////////////////// +/////////////////////////////////////// + + +/////////////////////////////////////// +// System Clock (Always ON) +/////////////////////////////////////// +logic rst_sys_clk_n, clk_sys_pd_n; +logic clk_sys_en, clk_osc_sys, clk_osc_sys_val; +prim_mubi_pkg::mubi4_t clk_src_sys_jen; + +assign rst_sys_clk_n = vcmain_pok_por && vcc_pok; +assign clk_sys_pd_n = scan_mode || !deep_sleep; + +logic sys_io_osc_cal; + +assign clk_sys_en = clk_src_sys_en_i; + +`ifdef AST_BYPASS_CLK +logic clk_sys_ext; +assign clk_sys_ext = clk_osc_byp_i.sys; +`endif + +sys_clk u_sys_clk ( + .clk_src_sys_jen_i ( prim_mubi_pkg::mubi4_test_true_loose(clk_src_sys_jen) ), + .clk_src_sys_en_i ( clk_sys_en ), + .clk_sys_pd_ni ( clk_sys_pd_n ), + .rst_sys_clk_ni ( rst_sys_clk_n ), + .vcore_pok_h_i ( vcaon_pok_h ), + .scan_mode_i ( scan_mode ), + .sys_osc_cal_i ( sys_io_osc_cal ), +`ifdef AST_BYPASS_CLK + .clk_sys_ext_i ( clk_sys_ext ), +`endif + .clk_src_sys_o ( clk_osc_sys ), + .clk_src_sys_val_o ( clk_osc_sys_val ) +); + + +/////////////////////////////////////// +// USB Clock (Always ON) +/////////////////////////////////////// +logic rst_usb_clk_n, clk_usb_pd_n; +logic clk_usb_en, clk_osc_usb, clk_osc_usb_val; +logic usb_ref_val, usb_ref_pulse; + +assign rst_usb_clk_n = vcmain_pok_por && vcc_pok; +assign clk_usb_pd_n = scan_mode || !deep_sleep; + +logic usb_osc_cal; + +`ifdef AST_BYPASS_CLK +logic clk_usb_ext; +assign clk_usb_ext = clk_osc_byp_i.usb; +`endif + +assign clk_usb_en = clk_src_usb_en_i; +assign usb_ref_val = usb_ref_val_i; +assign usb_ref_pulse = usb_ref_pulse_i; + +usb_clk u_usb_clk ( + .vcore_pok_h_i ( vcaon_pok_h ), + .clk_usb_pd_ni ( clk_usb_pd_n ), + .rst_usb_clk_ni ( rst_usb_clk_n ), + .clk_src_usb_en_i ( clk_usb_en ), + .usb_ref_val_i ( usb_ref_val ), + .usb_ref_pulse_i ( usb_ref_pulse ), + .clk_ast_usb_i ( clk_ast_usb_i ), + .rst_ast_usb_ni ( rst_ast_usb_ni ), + .scan_mode_i ( scan_mode ), + .usb_osc_cal_i ( usb_osc_cal ), +`ifdef AST_BYPASS_CLK + .clk_usb_ext_i ( clk_usb_ext ), +`endif + .clk_src_usb_o ( clk_osc_usb ), + .clk_src_usb_val_o ( clk_osc_usb_val ) +); + + +/////////////////////////////////////// +// AON Clock (Always ON) +/////////////////////////////////////// +logic rst_aon_clk_n; +logic clk_src_aon_en, clk_osc_aon, clk_osc_aon_val; +logic aon_osc_cal; + +`ifdef AST_BYPASS_CLK +logic clk_aon_ext; +assign clk_aon_ext = clk_osc_byp_i.aon; +`endif + +assign rst_aon_clk_n = vcc_pok_str && vcaon_pok; +assign clk_src_aon_en = 1'b1; // Always Enabled + +aon_clk u_aon_clk ( + .vcore_pok_h_i ( vcaon_pok_h ), + .clk_aon_pd_ni ( 1'b1 ), // Always Enabled + .rst_aon_clk_ni ( rst_aon_clk_n ), + .clk_src_aon_en_i ( clk_src_aon_en ), + .scan_mode_i ( scan_mode ), + .aon_osc_cal_i ( aon_osc_cal ), +`ifdef AST_BYPASS_CLK + .clk_aon_ext_i ( clk_aon_ext ), +`endif + .clk_src_aon_o ( clk_osc_aon ), + .clk_src_aon_val_o ( clk_osc_aon_val ) +); + +logic vcmpp_aon_sync_n, rst_vcmpp_aon_n; + +// Reset De-Assert Sync +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_vcmpp_aon_dasrt ( + .clk_i ( clk_aon ), + .rst_ni ( vcmain_pok_por ), + .d_i ( 1'b1 ), + .q_o ( vcmpp_aon_sync_n ) +); + +assign rst_vcmpp_aon_n = scan_mode ? scan_reset_n : vcmpp_aon_sync_n; + + +/////////////////////////////////////// +// IO Clock (Always ON) +/////////////////////////////////////// +logic rst_io_clk_n, clk_io_pd_n; +logic clk_src_io_en, clk_osc_io, clk_osc_io_val; + +assign rst_io_clk_n = vcmain_pok_por && vcc_pok; +assign clk_io_pd_n = scan_mode || !deep_sleep; + +`ifdef AST_BYPASS_CLK +logic clk_io_ext; +assign clk_io_ext = clk_osc_byp_i.io; +`endif + +assign clk_src_io_en = clk_src_io_en_i; + +io_clk u_io_clk ( + .vcore_pok_h_i ( vcaon_pok_h ), + .clk_io_pd_ni ( clk_io_pd_n ), + .rst_io_clk_ni ( rst_io_clk_n ), + .clk_src_io_en_i ( clk_src_io_en ), + .scan_mode_i ( scan_mode ), + .io_osc_cal_i ( sys_io_osc_cal ), +`ifdef AST_BYPASS_CLK + .clk_io_ext_i ( clk_io_ext ), +`endif + .clk_src_io_o ( clk_osc_io ), + .clk_src_io_val_o ( clk_osc_io_val ) +); + + +/////////////////////////////////////// +// AST Clocks Bypass +/////////////////////////////////////// +logic clk_src_sys, clk_src_io, clk_src_usb, clk_src_aon; + +ast_clks_byp u_ast_clks_byp ( + .vcaon_pok_i ( vcaon_pok ), + .vcaon_pok_por_i ( vcaon_pok_por ), + .deep_sleep_i ( deep_sleep ), + .clk_src_sys_en_i ( clk_src_sys_en_i ), + .clk_osc_sys_i ( clk_osc_sys ), + .clk_osc_sys_val_i ( clk_osc_sys_val ), + .clk_src_io_en_i ( clk_src_io_en_i ), + .clk_osc_io_i ( clk_osc_io ), + .clk_osc_io_val_i ( clk_osc_io_val ), + .clk_src_usb_en_i ( clk_src_usb_en_i ), + .clk_osc_usb_i ( clk_osc_usb ), + .clk_osc_usb_val_i ( clk_osc_usb_val ), + .clk_osc_aon_i ( clk_osc_aon ), + .clk_osc_aon_val_i ( clk_osc_aon_val ), + .clk_ast_ext_i ( clk_ast_ext_i ), +`ifdef AST_BYPASS_CLK + .clk_ext_sys_i( clk_sys_ext ), + .clk_ext_io_i( clk_io_ext ), + .clk_ext_usb_i( clk_usb_ext ), + .clk_ext_aon_i( clk_aon_ext ), +`endif + .io_clk_byp_req_i ( io_clk_byp_req_i ), + .all_clk_byp_req_i ( all_clk_byp_req_i ), + .ext_freq_is_96m_i ( ext_freq_is_96m_i ), + .io_clk_byp_ack_o ( io_clk_byp_ack_o ), + .all_clk_byp_ack_o ( all_clk_byp_ack_o ), + .clk_src_sys_o ( clk_src_sys ), + .clk_src_sys_val_o ( clk_src_sys_val_o ), + .clk_src_io_o ( clk_src_io ), + .clk_src_io_val_o ( clk_src_io_val_o ), + .clk_src_io_48m_o ( clk_src_io_48m_o ), + .clk_src_usb_o ( clk_src_usb ), + .clk_src_usb_val_o ( clk_src_usb_val_o ), + .clk_src_aon_o ( clk_src_aon ), + .clk_src_aon_val_o ( clk_src_aon_val_o ) +); + +// System source clock buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_src_sys_buf ( + .clk_i ( clk_src_sys ), + .clk_o ( clk_src_sys_o ) +); + +// IO source clock buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_src_io_buf ( + .clk_i ( clk_src_io ), + .clk_o ( clk_src_io_o ) +); + +// USB source clock buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_src_usb_buf ( + .clk_i ( clk_src_usb ), + .clk_o ( clk_src_usb_o ) +); + +// AON source clock buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_src_aon_buf ( + .clk_i ( clk_src_aon ), + .clk_o ( clk_src_aon_o ) +); + + +/////////////////////////////////////// +// ADC (Always ON) +/////////////////////////////////////// +adc #( + .AdcCnvtClks ( AdcCnvtClks ), + .AdcChannels ( AdcChannels ), + .AdcDataWidth ( AdcDataWidth ) +) u_adc ( + .adc_a0_ai ( adc_a0_ai ), + .adc_a1_ai ( adc_a1_ai ), + .adc_chnsel_i ( adc_chnsel_i[AdcChannels-1:0] ), + .adc_pd_i ( adc_pd_i ), + .clk_adc_i ( clk_ast_adc_i ), + .rst_adc_ni ( rst_ast_adc_ni ), + .adc_d_o ( adc_d_o[AdcDataWidth-1:0] ), + .adc_d_val_o ( adc_d_val_o ) +); + + +/////////////////////////////////////// +// Entropy (Always ON) +/////////////////////////////////////// +logic vcmain_pok_por_sys, rst_src_sys_n; + +// Sync clk_src_sys_jen_i to clk_sys +prim_mubi4_sync #( + .NumCopies ( 1 ), + .AsyncOn ( 1 ), + .StabilityCheck ( 1 ), + .ResetValue (prim_mubi_pkg::MuBi4False ) +) u_jitter_en_sync ( + .clk_i ( clk_sys ), + .rst_ni ( rst_src_sys_n ), + .mubi_i ( clk_src_sys_jen_i ), + .mubi_o ( {clk_src_sys_jen} ) +); + +// Reset De-Assert Sync +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_sys_dasrt ( + .clk_i ( clk_sys ), + .rst_ni ( vcmain_pok_por ), + .d_i ( 1'b1 ), + .q_o ( vcmain_pok_por_sys ) +); + +assign rst_src_sys_n = scan_mode ? scan_reset_n : vcmain_pok_por_sys; + +/////////////////////////////////////// +// RNG (Always ON) +/////////////////////////////////////// +ast_pkg::ast_dif_t ot1_alert_src; + +rng #( + .EntropyStreams ( EntropyStreams ) +) u_rng ( + .clk_i ( clk_ast_rng_i ), + .rst_ni ( rst_ast_rng_ni ), + .clk_ast_rng_i ( clk_ast_rng_i ), + .rst_ast_rng_ni ( rst_ast_rng_ni ), + .rng_en_i ( rng_en_i ), + .rng_fips_i ( rng_fips_i ), + .scan_mode_i ( scan_mode ), + .rng_b_o ( rng_b_o[EntropyStreams-1:0] ), + .rng_val_o ( rng_val_o ) +); + +/////////////////////////////////////// +// Alerts (Always ON) +/////////////////////////////////////// +ast_pkg::ast_dif_t as_alert_src; +ast_pkg::ast_dif_t cg_alert_src; +ast_pkg::ast_dif_t gd_alert_src; +ast_pkg::ast_dif_t ts_alert_hi_src; +ast_pkg::ast_dif_t ts_alert_lo_src; +ast_pkg::ast_dif_t ot0_alert_src; +ast_pkg::ast_dif_t ot2_alert_src; +ast_pkg::ast_dif_t ot3_alert_src; +ast_pkg::ast_dif_t ot4_alert_src; +ast_pkg::ast_dif_t ot5_alert_src; +ast_pkg::ast_dif_t es0_alert_src; +ast_pkg::ast_dif_t es1_alert_src; +ast_pkg::ast_dif_t es2_alert_src; + +// Active Shield (AS) +/////////////////////////////////////// +ast_alert u_alert_as ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( as_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::AsSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::AsSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::AsSel] ) +); + +// Clock Glitch (CG) +/////////////////////////////////////// +ast_alert u_alert_cg ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( cg_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::CgSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::CgSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::CgSel] ) +); + +// Glitch Detector (GD) +/////////////////////////////////////// +ast_alert u_alert_gd ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( gd_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::GdSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::GdSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::GdSel] ) +); + +// Temprature Sensor High (TS Hi) +/////////////////////////////////////// +ast_alert u_alert_ts_hi ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ts_alert_hi_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::TsHiSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::TsHiSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::TsHiSel] ) +); + +// Temprature Sensor Low (TS Lo) +/////////////////////////////////////// +ast_alert u_alert_ts_lo ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ts_alert_lo_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::TsLoSel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::TsLoSel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::TsLoSel] ) +); + +// Other-0 Alert (OT0) +/////////////////////////////////////// +ast_alert u_alert_ot0 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot0_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot0Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot0Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot0Sel] ) +); // of u_alert_ot0 + +// Other-1 Alert (OT1) +/////////////////////////////////////// +ast_alert u_alert_ot1 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot1_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot1Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot1Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot1Sel] ) +); // of u_alert_ot1 + +// Other-2 Alert (OT2) +/////////////////////////////////////// +ast_alert u_alert_ot2 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot2_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[Ot2Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[Ot2Sel] ), + .alert_req_o ( alert_req_o.alerts[Ot2Sel] ) +); // of u_alert_ot2 + +// Other-3 Alert (OT3) +/////////////////////////////////////// +ast_alert u_alert_ot3 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot3_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[Ot3Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[Ot3Sel] ), + .alert_req_o ( alert_req_o.alerts[Ot3Sel] ) +); // of u_alert_ot3 + +// Other-4 Alert (OT4) +/////////////////////////////////////// +ast_alert u_alert_ot4 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot4_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot4Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot4Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot4Sel] ) +); // of u_alert_ot4 + +// Other-5 Alert (OT5) +/////////////////////////////////////// +ast_alert u_alert_ot5 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( ot5_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Ot5Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Ot5Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Ot5Sel] ) +); // of u_alert_ot5 + +// Entropy Source Vendor IP Health Test Alert 0 +/////////////////////////////////////////////// +ast_alert u_alert_es0 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( es0_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Es0Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Es0Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Es0Sel] ) +); + +// Entropy Source Vendor IP Health Test Alert 1 +/////////////////////////////////////////////// +ast_alert u_alert_es1 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( es1_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Es1Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Es1Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Es1Sel] ) +); + +// Entropy Source Vendor IP Health Test Alert 2 +/////////////////////////////////////////////// +ast_alert u_alert_es2 ( + .clk_i ( clk_ast_alert_i ), + .rst_ni ( rst_ast_alert_ni ), + .alert_src_i ( es2_alert_src ), + .alert_trig_i ( alert_rsp_i.alerts_trig[ast_pkg::Es2Sel] ), + .alert_ack_i ( alert_rsp_i.alerts_ack[ast_pkg::Es2Sel] ), + .alert_req_o ( alert_req_o.alerts[ast_pkg::Es2Sel] ) +); + +// Alerts Open-Source Selection +//////////////////////////////////////// +assign as_alert_src = '{p: 1'b0, n: 1'b1}; +assign cg_alert_src = '{p: 1'b0, n: 1'b1}; +assign gd_alert_src = '{p: 1'b0, n: 1'b1}; +assign ts_alert_hi_src = '{p: 1'b0, n: 1'b1}; +assign ts_alert_lo_src = '{p: 1'b0, n: 1'b1}; +assign ot1_alert_src = '{p: 1'b0, n: 1'b1}; +assign ot2_alert_src = '{p: 1'b0, n: 1'b1}; +assign ot3_alert_src = '{p: 1'b0, n: 1'b1}; +assign ot4_alert_src = '{p: 1'b0, n: 1'b1}; +assign ot5_alert_src = '{p: 1'b0, n: 1'b1}; +assign es0_alert_src = '{p: 1'b0, n: 1'b1}; +assign es1_alert_src = '{p: 1'b0, n: 1'b1}; +assign es2_alert_src = '{p: 1'b0, n: 1'b1}; + +/////////////////////////////////////// +// AST Registers (Always ON) +/////////////////////////////////////// +ast_reg_pkg::ast_reg2hw_t reg2hw; // Write (To HW) +ast_reg_pkg::ast_hw2reg_t hw2reg; // Read (From HW) +logic intg_err; + +ast_reg_top u_reg ( + .clk_i ( clk_ast_tlul_i ), + .rst_ni ( rst_ast_tlul_ni ), + .tl_i ( tl_i ), + .tl_o ( tl_o ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + .intg_err_o ( intg_err ) +); + + +/////////////////////////////////////// +// REGAL Register +/////////////////////////////////////// +logic regal_rst_n; +assign regal_rst_n = rst_ast_tlul_ni; + +logic regal_we; +logic [32-1:0] regal, regal_di; + +assign regal_we = reg2hw.regal.qe; +assign regal_di = reg2hw.regal.q; +assign hw2reg.regal.d = regal; + +// REGAL & AST init done indication +always_ff @( posedge clk_ast_tlul_i, negedge regal_rst_n ) begin + if ( !regal_rst_n ) begin + regal <= ast_reg_pkg::AST_REGAL_RESVAL; + ast_init_done_o <= prim_mubi_pkg::MuBi4False; + end else if ( regal_we ) begin + regal <= regal_di; + ast_init_done_o <= prim_mubi_pkg::MuBi4True; + end +end + +always_ff @( posedge clk_ast_tlul_i, negedge rst_ast_tlul_ni ) begin + if ( !rst_ast_tlul_ni ) begin + sys_io_osc_cal <= 1'b0; + end else if ( regal_we ) begin + sys_io_osc_cal <= 1'b1; + end +end + +always_ff @( posedge clk_ast_tlul_i, negedge vcaon_pok_por ) begin + if ( !vcaon_pok_por ) begin + usb_osc_cal <= 1'b0; + end else if ( regal_we ) begin + usb_osc_cal <= 1'b1; + end +end + +always_ff @( posedge clk_ast_tlul_i, negedge vcaon_pok ) begin + if ( !vcaon_pok ) begin + aon_osc_cal <= 1'b0; + end else if ( regal_we ) begin + aon_osc_cal <= 1'b1; + end +end + +// TLUL Integrity Error +assign ot0_alert_src = '{p: intg_err, n: !intg_err}; + +// USB PU-P and PU-N value selection +assign usb_io_pu_cal_o = UsbCalibWidth'(1 << (UsbCalibWidth[5-1:0]/2)); + + +/////////////////////////////////////// +// DFT (Main | Always ON) +/////////////////////////////////////// +ast_dft u_ast_dft ( + .obs_ctrl_o ( obs_ctrl_o ), + .ast2padmux_o ( ast2padmux_o[Ast2PadOutWidth-1:0] ), + .dpram_rmf_o ( dpram_rmf_o ), + .dpram_rml_o ( dpram_rml_o ), + .spram_rm_o ( spram_rm_o ), + .sprgf_rm_o ( sprgf_rm_o ), + .sprom_rm_o ( sprom_rm_o ) +); + + +//////////////////////////////////////// +// DFT Misc Logic +//////////////////////////////////////// +`ifdef ANALOGSIM +assign ast2pad_t0_ao = 0.0; +assign ast2pad_t1_ao = 0.1; +`else +assign ast2pad_t0_ao = 1'bz; +assign ast2pad_t1_ao = 1'bz; +`endif + + +//////////////// +// Assertions // +//////////////// + +// Clocks +`ASSERT_KNOWN(ClkSrcAonKnownO_A, clk_src_aon_o, 1, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(ClkSrcAonValKnownO_A, clk_src_aon_val_o, clk_src_aon_o, rst_aon_clk_n) +`ASSERT_KNOWN(ClkSrcIoKnownO_A, clk_src_io_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(ClkSrcIoValKnownO_A, clk_src_io_val_o, clk_src_io_o, rst_io_clk_n) +`ASSERT_KNOWN(ClkSrcIo48mKnownO_A, clk_src_io_48m_o, clk_src_io_o, rst_io_clk_n) +`ASSERT_KNOWN(ClkSrcSysKnownO_A, clk_src_sys_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(ClkSrcSysValKnownO_A, clk_src_sys_val_o, clk_src_sys_o, rst_sys_clk_n) +`ASSERT_KNOWN(ClkSrcUsbKnownO_A, clk_src_usb_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(ClkSrcUsbValKnownO_A, clk_src_usb_val_o, clk_src_usb_o, rst_usb_clk_n) +// +`ASSERT_KNOWN(UsbIoPuCalKnownO_A, usb_io_pu_cal_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(LcClkBypAckEnKnownO_A, io_clk_byp_ack_o, clk_ast_tlul_i, rst_ast_tlul_ni) +`ASSERT_KNOWN(AllClkBypAckEnKnownO_A, all_clk_byp_ack_o, clk_ast_tlul_i, rst_ast_tlul_ni) +// ADC +`ASSERT_KNOWN(AdcDKnownO_A, adc_d_o, clk_ast_adc_i, rst_ast_adc_ni) +`ASSERT_KNOWN(AdcDValKnownO_A, adc_d_val_o, clk_ast_adc_i, rst_ast_adc_ni) +// RNG +`ASSERT_KNOWN(RngBKnownO_A, rng_b_o, clk_ast_rng_i, rst_ast_rng_ni) +`ASSERT_KNOWN(RngValKnownO_A, rng_val_o, clk_ast_rng_i, rst_ast_rng_ni) +// TLUL +`ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid, clk_ast_tlul_i, rst_ast_tlul_ni) +`ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready, clk_ast_tlul_i, rst_ast_tlul_ni) +// +`ASSERT_KNOWN(InitDoneKnownO_A, ast_init_done_o, clk_ast_tlul_i, rst_ast_tlul_ni) +// POs +`ASSERT_KNOWN(VcaonPokKnownO_A, ast_pwst_o.aon_pok, clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VcmainPokKnownO_A, ast_pwst_o.main_pok, clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VioaPokKnownO_A, ast_pwst_o.io_pok[0], clk_src_aon_o, por_ni) +`ASSERT_KNOWN(ViobPokKnownO_A, ast_pwst_o.io_pok[1], clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VcaonPokHKnownO_A, ast_pwst_h_o.aon_pok, clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VcmainPokHKnownO_A, ast_pwst_h_o.main_pok, clk_src_aon_o, por_ni) +`ASSERT_KNOWN(VioaPokHKnownO_A, ast_pwst_h_o.io_pok[0], clk_src_aon_o, por_ni) +`ASSERT_KNOWN(ViobPokHKnownO_A, ast_pwst_h_o.io_pok[1], clk_src_aon_o, por_ni) +// FLASH/OTP +`ASSERT_KNOWN(FlashPowerDownKnownO_A, flash_power_down_h_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(FlashPowerReadyKnownO_A, flash_power_ready_h_o, 1, ast_pwst_o.main_pok) +`ASSERT_KNOWN(OtpPowerSeqKnownO_A, otp_power_seq_h_o, 1, ast_pwst_o.main_pok) +// Alerts +`ASSERT_KNOWN(AlertReqKnownO_A, alert_req_o, clk_ast_alert_i, rst_ast_alert_ni) +// DPRAM/SPRAM +`ASSERT_KNOWN(DpramRmfKnownO_A, dpram_rmf_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(DpramRmlKnownO_A, dpram_rml_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(SpramRmKnownO_A, spram_rm_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(SprgfRmKnownO_A, sprgf_rm_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(SpromRmKnownO_A, sprom_rm_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +// DFT +`ASSERT_KNOWN(Ast2PadmuxKnownO_A, ast2padmux_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +// SCAN +`ASSERT_KNOWN(DftScanMdKnownO_A, dft_scan_md_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(ScanShiftEnKnownO_A, scan_shift_en_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(ScanResetKnownO_A, scan_reset_no, clk_ast_tlul_i, ast_pwst_o.aon_pok) +`ASSERT_KNOWN(FlashBistEnKnownO_A, flash_bist_en_o, clk_ast_tlul_i, ast_pwst_o.aon_pok) + +// Alert assertions for reg_we onehot check +`ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(RegWeOnehot_A, + u_reg, alert_req_o.alerts[ast_pkg::Ot0Sel].p, , , clk_ast_alert_i, rst_ast_alert_ni) + + +///////////////////// +// Unused Signals // +///////////////////// +logic unused_sigs; + +assign unused_sigs = ^{ clk_ast_usb_i, + rst_ast_usb_ni, + sns_spi_ext_clk_i, + sns_clks_i, + sns_rsts_i, + intg_err, + shift_en, + main_env_iso_en_i, + rst_vcmpp_aon_n, + padmux2ast_i[Pad2AstInWidth-1:0], + lc_dft_en_i[3:0], + fla_obs_i[8-1:0], + otp_obs_i[8-1:0], + otm_obs_i[8-1:0], + usb_obs_i, + reg2hw.rega0, + reg2hw.rega1, + reg2hw.rega2, + reg2hw.rega3, + reg2hw.rega4, + reg2hw.rega5, + reg2hw.rega6, + reg2hw.rega7, + reg2hw.rega8, + reg2hw.rega9, + reg2hw.rega10, + reg2hw.rega11, + reg2hw.rega12, + reg2hw.rega13, + reg2hw.rega14, + reg2hw.rega15, + reg2hw.rega16, + reg2hw.rega17, + reg2hw.rega18, + reg2hw.rega19, + reg2hw.rega20, + reg2hw.rega21, + reg2hw.rega22, + reg2hw.rega23, + reg2hw.rega24, + reg2hw.rega25, + reg2hw.rega26, + reg2hw.rega27, + reg2hw.rega28, + reg2hw.rega29, + reg2hw.regb // [0:3] + }; + +endmodule : ast diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_alert.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_alert.sv new file mode 100644 index 00000000000..1547c48273a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_alert.sv @@ -0,0 +1,73 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: ast_alert +// *Module Description: AST Alert +//############################################################################ + +module ast_alert ( + input clk_i, + input rst_ni, + input ast_pkg::ast_dif_t alert_src_i, + input ast_pkg::ast_dif_t alert_ack_i, + input ast_pkg::ast_dif_t alert_trig_i, + output ast_pkg::ast_dif_t alert_req_o +); + +// Unpack inputs +logic p_alert_src, n_alert_src; +assign p_alert_src = alert_src_i.p; +assign n_alert_src = alert_src_i.n; + +logic p_alert_ack, n_alert_ack; +assign p_alert_ack = alert_ack_i.p; +assign n_alert_ack = alert_ack_i.n; + +logic p_alert_trig, n_alert_trig; +assign p_alert_trig = alert_trig_i.p; +assign n_alert_trig = alert_trig_i.n; + +// Pack outputs +logic p_alert_req, n_alert_req; + +assign alert_req_o.p = p_alert_req; +assign alert_req_o.n = n_alert_req; + +// P Alert +logic p_alert, set_p_alert, clr_p_alert; + +assign set_p_alert = p_alert_src || p_alert_trig; +assign clr_p_alert = !set_p_alert && p_alert_ack; + +always_ff @( posedge clk_i, negedge rst_ni ) begin + if ( !rst_ni ) begin + p_alert <= 1'b0; + end else if ( set_p_alert ) begin + p_alert <= 1'b1; + end else if ( clr_p_alert ) begin + p_alert <= 1'b0; + end +end + +assign p_alert_req = p_alert; + +// N Alert +logic n_alert, set_n_alert, clr_n_alert; + +assign set_n_alert = !(n_alert_src && n_alert_trig); +assign clr_n_alert = !(set_n_alert || n_alert_ack); + +always_ff @( posedge clk_i, negedge rst_ni ) begin + if ( !rst_ni ) begin + n_alert <= 1'b1; + end else if ( set_n_alert ) begin + n_alert <= 1'b0; + end else if ( clr_n_alert ) begin + n_alert <= 1'b1; + end +end + +assign n_alert_req = n_alert; + +endmodule : ast_alert diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_bhv_pkg.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_bhv_pkg.sv new file mode 100644 index 00000000000..7c2dacb9813 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_bhv_pkg.sv @@ -0,0 +1,46 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: ast_bhv_pkg +// *Module Description: AST Behavioral Package +//############################################################################ +`ifdef __AST_BHV_PKG_SV +`else +`define __AST_BHV_PKG_SV + +package ast_bhv_pkg; + + ///////////////////////////////// + // Delay Parameters from Spec + ///////////////////////////////// +`ifndef SYNTHESIS + // POKs + parameter time VCC_POK_RDLY = 3us; + parameter time VCC_POK_FDLY = 500ns; + parameter time VCAON_POK_RDLY = 3us; + parameter time VCAON_POK_FDLY = 500ns; + parameter time VCMAIN_POK_RDLY = 3us; + parameter time VCMAIN_POK_FDLY = 500ns; + parameter time VIO_POK_RDLY = 3us; + parameter time VIO_POK_FDLY = 500ns; + // Main Regulator + parameter time MPVCC_RDLY = 5us; + parameter time MPVCC_FDLY = 100ns; + parameter time MPPD_RDLY = 50us; + parameter time MPPD_FDLY = 1us; + // Clocks + parameter time SYS_EN_RDLY = 5us; + parameter time USB_EN_RDLY = 5us; + // Reduced for simulation from 50ms + parameter time USB_VAL_RDLY = 80ns; // 50ms + parameter time USB_VAL_FDLY = 80ns; + parameter time IO_EN_RDLY = 5us; + parameter time AON_EN_RDLY = 5us; + parameter time RNG_EN_RDLY = 5us; +`endif // of SYNTHESIS + // ADC + parameter int unsigned AdcCnvtClks = 19; + +endpackage // of ast_bhv_pkg +`endif // of __AST_BHV_PKG_SV diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_clks_byp.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_clks_byp.sv new file mode 100644 index 00000000000..a9661185041 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_clks_byp.sv @@ -0,0 +1,793 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: ast_clks_byp +// *Module Description: AST Clocks Bypass +//############################################################################ + +`include "prim_assert.sv" + +module ast_clks_byp ( + input vcaon_pok_i, // VCAON POK + input vcaon_pok_por_i, // VCAON POK POR + input deep_sleep_i, // Deep Sleep (main regulator & switch are off) + input clk_src_sys_en_i, // SYS Source Clock Enable + input clk_osc_sys_i, // SYS Oscillator Clock + input clk_osc_sys_val_i, // SYS Oscillator Clock Valid + input clk_src_io_en_i, // IO Source Clock Enable + input clk_osc_io_i, // IO Oscillator Clock + input clk_osc_io_val_i, // IO Oscillator Clock Valid + input clk_src_usb_en_i, // USB Source Clock Enable + input clk_osc_usb_i, // USB Oscillator Clock + input clk_osc_usb_val_i, // USB Oscillator Clock Valid + input clk_osc_aon_i, // AON Oscillator Clock + input clk_osc_aon_val_i, // AON Oscillator Clock Valid + input clk_ast_ext_i, // External Clock +`ifdef AST_BYPASS_CLK + input clk_ext_sys_i, + input clk_ext_io_i, + input clk_ext_usb_i, + input clk_ext_aon_i, +`endif // of AST_BYPASS_CLK + input prim_mubi_pkg::mubi4_t io_clk_byp_req_i, // External IO clock mux for OTP bootstrap + input prim_mubi_pkg::mubi4_t all_clk_byp_req_i, // External all clock mux override + input prim_mubi_pkg::mubi4_t ext_freq_is_96m_i, // External Clock Frequecy is 96MHz (else 48MHz) + output prim_mubi_pkg::mubi4_t io_clk_byp_ack_o, // Switch IO clock to External clock + output prim_mubi_pkg::mubi4_t all_clk_byp_ack_o, // Switch all clocks to External clock + output logic clk_src_sys_o, // SYS Source Clock + output logic clk_src_sys_val_o, // SYS Source Clock Valid + output logic clk_src_io_o, // IO Source Clock + output logic clk_src_io_val_o, // IO Source Clock Valid + output prim_mubi_pkg::mubi4_t clk_src_io_48m_o, // IO Source Clock is 48Mhz + output logic clk_src_usb_o, // USB Source Clock + output logic clk_src_usb_val_o, // USB Source Clock Valid + output logic clk_src_aon_o, // AON Source Clock + output logic clk_src_aon_val_o // AON Source Clock Valid +); + +logic scan_mode_i, scan_reset_ni; + +assign scan_mode_i = 1'b0; +assign scan_reset_ni = 1'b1; + +//////////////////////////////////////// +// Local AON clock buffer +//////////////////////////////////////// +logic clk_aon, rst_aon_n; + +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_aon_buf ( + .clk_i ( clk_src_aon_o ), + .clk_o ( clk_aon ) +); + +logic vcaon_pok; // For Spyglass waiver!!! + +assign vcaon_pok = vcaon_pok_i; +assign rst_aon_n = scan_mode_i ? scan_reset_ni : vcaon_pok; + + +//////////////////////////////////////// +// External Clocks Generation +//////////////////////////////////////// +// Enable External Clock for SW Bypass +logic rst_sw_clk_byp_en, sw_all_clk_byp, sw_io_clk_byp; + +always_ff @( posedge clk_aon, negedge rst_aon_n ) begin + if ( !rst_aon_n ) begin + rst_sw_clk_byp_en <= 1'b0; + end else if ( sw_all_clk_byp || sw_io_clk_byp ) begin + rst_sw_clk_byp_en <= 1'b1; + end +end + +logic rst_sw_ckbpe_n, clk_ast_ext_scn, sw_clk_byp_en; + +assign rst_sw_ckbpe_n = scan_mode_i ? scan_reset_ni : rst_sw_clk_byp_en; +`ifndef AST_BYPASS_CLK +assign clk_ast_ext_scn = scan_mode_i ? clk_osc_sys_i : clk_ast_ext_i; +`else // of AST_BYPASS_CLK +assign clk_ast_ext_scn = scan_mode_i ? clk_osc_sys_i : clk_ext_sys_i; +`endif // of AST_BYPASS_CLK + +// De-assert with external clock input +always_ff @( negedge clk_ast_ext_scn, negedge rst_sw_ckbpe_n ) begin + if ( !rst_sw_ckbpe_n ) begin + sw_clk_byp_en <= 1'b0; + end else begin + sw_clk_byp_en <= 1'b1; + end +end + +logic clk_ext_en, clk_ext_scn; + +assign clk_ext_en = sw_clk_byp_en; +`ifdef AST_BYPASS_CLK +logic clk_ast_ext; + +prim_clock_gating #( + .NoFpgaGate(1'b1) +) u_clk_ast_ext_gating ( + .clk_i( clk_ext_sys_i ), + .en_i( clk_ext_en ), + .test_en_i( 1'b0 ), + .clk_o( clk_ast_ext ) +); + +assign clk_ext_scn = scan_mode_i ? clk_osc_sys_i : clk_ast_ext; +`else +//we can't use prim_clock_gating here for the following reason: +//prim_clock_gating default behavior at wakeup: clk_i=1'bx, en_i=don't care --> clk_o=1'bx +//we want to mask that 1'bx as some tests doesn't use clk_ast_ext_i +assign clk_ext_scn = scan_mode_i ? clk_osc_sys_i : (clk_ast_ext_i && clk_ext_en); +`endif + +// Local EXT clock buffer +//////////////////////////////////////// +logic clk_ext; + +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_ext_buf ( + .clk_i ( clk_ext_scn ), + .clk_o ( clk_ext ) +); + +logic rst_aon_n_exda, rst_aon_exda_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_aon_n_exda_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_n ), + .d_i ( 1'b1 ), + .q_o ( rst_aon_n_exda ) +); + +assign rst_aon_exda_n = scan_mode_i ? scan_reset_ni : rst_aon_n_exda; + +// External USB & AON clocks genaration +//////////////////////////////////////// +`ifndef AST_BYPASS_CLK +logic clk_src_ext_usb, ext_freq_is_96m, ext_freq_is_96m_sync; + +prim_flop_2sync #( + .Width ( 1 ), + // Assume external clock is 96Hhz on reset + .ResetValue ( 1'b1 ) +) u_no_scan_ext_freq_is_96m_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( ext_freq_is_96m ), + .q_o ( ext_freq_is_96m_sync ) +); + +prim_clock_div #( + .Divisor( 2 ) +) u_no_scan_clk_ext_d1ord2 ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .step_down_req_i( !ext_freq_is_96m_sync ), + .step_down_ack_o ( ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_src_ext_usb ) +); +`else // of AST_BYPASS_CLK +logic clk_src_ext_usb, ext_freq_is_96m; +assign clk_src_ext_usb = clk_ext_usb_i; +`endif // of AST_BYPASS_CLK + +logic clk_ext_aon, clk_ext_aon_val; + +assign clk_ext_aon_val = 1'b1; // Always ON clock + +`ifndef AST_BYPASS_CLK +prim_clock_div #( + .Divisor( 240 ) +) u_no_scan_clk_usb_div240_div ( + .clk_i ( clk_src_ext_usb ), + .rst_ni ( rst_aon_exda_n ), + .step_down_req_i( 1'b0 ), + .step_down_ack_o ( ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_ext_aon ) +); +`else // of AST_BYPASS_CLK +assign clk_ext_aon = clk_ext_aon_i; +`endif // of AST_BYPASS_CLK + + +//////////////////////////////////////// +// Deep-Sleep/Enables Gators +//////////////////////////////////////// + +// Deep-Sleep Sync to External clcok +//////////////////////////////////////// +logic deep_sleep, deep_sleep_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_deep_sleep_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( deep_sleep_i ), + .q_o ( deep_sleep ) +); + +assign deep_sleep_n = !deep_sleep; + +// SYS External Clock Enable +//////////////////////////////////////// +logic clk_ext_sys, clk_ext_sys_en, clk_ext_sys_val; +logic clk_src_sys_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_clk_src_sys_en_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( clk_src_sys_en_i ), + .q_o ( clk_src_sys_en ) +); + +assign clk_ext_sys_en = deep_sleep_n && clk_src_sys_en; +assign clk_ext_sys_val = clk_ext_sys_en; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1) +) u_clk_ext_sys_ckgt ( + .clk_i ( clk_ext ), + .en_i ( clk_ext_sys_en ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_ext_sys ) +); + +// IO External Clock Enable +//////////////////////////////////////// +logic clk_ext_io, clk_ext_io_en, clk_ext_io_val; +logic clk_src_io_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_clk_src_io_en_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( clk_src_io_en_i ), + .q_o ( clk_src_io_en ) +); + +assign clk_ext_io_en = deep_sleep_n && clk_src_io_en; +assign clk_ext_io_val = clk_ext_io_en; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1) +) u_clk_ext_io_ckgt ( +`ifndef AST_BYPASS_CLK + .clk_i ( clk_ext ), +`else // of AST_BYPASS_CLK + .clk_i ( clk_ext_io_i ), +`endif // of AST_BYPASS_CLK + .en_i ( clk_ext_io_en ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_ext_io ) +); + +// USB External Clock Enable +//////////////////////////////////////// +logic clk_ext_usb, clk_ext_usb_en, clk_ext_usb_val; +logic clk_src_usb_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_clk_src_usb_en_sync ( + .clk_i ( clk_ext ), + .rst_ni ( rst_aon_exda_n ), + .d_i ( clk_src_usb_en_i ), + .q_o ( clk_src_usb_en ) +); + +assign clk_ext_usb_en = deep_sleep_n && clk_src_usb_en; +assign clk_ext_usb_val = clk_ext_usb_en; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1) +) u_clk_ext_usb_ckgt ( + .clk_i ( clk_src_ext_usb ), + .en_i ( clk_ext_usb_en ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_ext_usb ) +); + + +//////////////////////////////////////// +// SW Bypass select logic +//////////////////////////////////////// +// Sync to local AON clock +prim_mubi_pkg::mubi4_t ot_io_clk_byp_req, ot_all_clk_byp_req, ot_ext_freq_is_96m; + +prim_mubi4_sync #( + .StabilityCheck ( 1 ), + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_io_clk_byp_req ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .mubi_i ( io_clk_byp_req_i ), + .mubi_o ( {ot_io_clk_byp_req} ) +); + +prim_mubi4_sync #( + .StabilityCheck ( 1 ), + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_all_clk_byp_req ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .mubi_i ( all_clk_byp_req_i ), + .mubi_o ( {ot_all_clk_byp_req} ) +); + +prim_mubi4_sync #( + .StabilityCheck ( 1 ), + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_ext_freq_is_96m ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .mubi_i ( ext_freq_is_96m_i ), + .mubi_o ( {ot_ext_freq_is_96m} ) +); + +// Decode logic +logic ot_all_clk_byp, ot_sys_clk_byp, ot_io_clk_byp, ot_usb_clk_byp, ot_aon_clk_byp; + +prim_mubi4_dec u_all_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_all_clk_byp ) ); +prim_mubi4_dec u_sys_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_sys_clk_byp ) ); +prim_mubi4_dec u_io_byp_sel ( .mubi_i ( ot_io_clk_byp_req ), .mubi_dec_o ( ot_io_clk_byp ) ); +prim_mubi4_dec u_usb_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_usb_clk_byp ) ); +prim_mubi4_dec u_aon_byp_sel ( .mubi_i ( ot_all_clk_byp_req ), .mubi_dec_o ( ot_aon_clk_byp ) ); + +// De-Glitch selects (decode "noise") +logic sw_sys_clk_byp, sw_usb_clk_byp, sw_aon_clk_byp, sw_exfr_is_96m; + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_all_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_all_clk_byp ), + .q_o ( sw_all_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_sys_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_sys_clk_byp ), + .q_o ( sw_sys_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_io_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_io_clk_byp ), + .q_o ( sw_io_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_usb_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_usb_clk_byp ), + .q_o ( sw_usb_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_aon_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( ot_aon_clk_byp ), + .q_o ( sw_aon_clk_byp ) +); + +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sw_exfr_is_96m_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( prim_mubi_pkg::mubi4_test_true_strict(ot_ext_freq_is_96m) ), + .q_o ( sw_exfr_is_96m ) +); + +logic sys_clk_byp; + +assign sys_clk_byp = sw_sys_clk_byp; + +logic sel_io_clk_byp, io_clk_byp; + +assign sel_io_clk_byp = sw_io_clk_byp || sw_all_clk_byp; + +// De-Glitch IO Clock Bypass Select +//////////////////////////////////////// +prim_flop #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_io_clk_byp_dgl ( + .clk_i ( clk_aon ), + .rst_ni ( rst_aon_n ), + .d_i ( sel_io_clk_byp ), + .q_o ( io_clk_byp ) +); + +logic usb_clk_byp; + +assign usb_clk_byp = sw_usb_clk_byp; + +logic aon_clk_byp; + +assign aon_clk_byp = sw_aon_clk_byp; + +logic extfreq_is_96m; + +assign extfreq_is_96m = sw_exfr_is_96m; + +// Block changes during scan mode +//////////////////////////////////////// +logic sys_clk_byp_sel, io_clk_byp_sel, usb_clk_byp_sel, aon_clk_byp_sel; + +`ifndef AST_BYPASS_CLK +always_latch begin + if ( !scan_mode_i ) begin + sys_clk_byp_sel = sys_clk_byp; + io_clk_byp_sel = io_clk_byp; + usb_clk_byp_sel = usb_clk_byp; + aon_clk_byp_sel = aon_clk_byp; + ext_freq_is_96m = extfreq_is_96m; + end +end +`else // of AST_BYPASS_CLK +assign sys_clk_byp_sel = sys_clk_byp; +assign io_clk_byp_sel = io_clk_byp; +assign usb_clk_byp_sel = usb_clk_byp; +assign aon_clk_byp_sel = aon_clk_byp; +assign ext_freq_is_96m = extfreq_is_96m; +`endif // of AST_BYPASS_CLK + + +//////////////////////////////////////// +// Clocks Bypass Muxes +//////////////////////////////////////// +logic sys_clk_osc_en, io_clk_osc_en, usb_clk_osc_en, aon_clk_osc_en; +logic sys_clk_byp_en, io_clk_byp_en, usb_clk_byp_en, aon_clk_byp_en; +logic rst_clk_osc_n, rst_clk_ext_n, aon_rst_clk_ext_n; + +assign rst_clk_osc_n = vcaon_pok; +assign rst_clk_ext_n = vcaon_pok_por_i; +assign aon_rst_clk_ext_n = vcaon_pok; + +// DV Hooks for IO clocks +logic io_clk_byp_select, io_clk_byp_sel_buf, io_clk_osc_en_buf, io_clk_byp_en_buf; + +assign io_clk_byp_select = io_clk_byp_sel; + +prim_buf u_io_clk_byp_sel ( + .in_i ( io_clk_byp_select ), + .out_o ( io_clk_byp_sel_buf ) +); + +prim_buf u_io_clk_osc_en ( + .in_i ( io_clk_osc_en ), + .out_o ( io_clk_osc_en_buf ) +); + +prim_buf u_io_clk_byp_en ( + .in_i ( io_clk_byp_en ), + .out_o ( io_clk_byp_en_buf ) +); + +logic rst_clk_osc_sys_n, rst_clk_ext_sys_n, rst_clk_osc_io_n, rst_clk_ext_io_n; +logic rst_clk_osc_usb_n, rst_clk_ext_usb_n, rst_clk_osc_aon_n, rst_clk_ext_aon_n; + +prim_buf u_rst_clk_osc_sys ( + .in_i ( rst_clk_osc_n ), + .out_o ( rst_clk_osc_sys_n ) +); + +prim_buf u_rst_clk_ext_sys ( + .in_i ( rst_clk_ext_n ), + .out_o ( rst_clk_ext_sys_n ) +); + +prim_buf u_rst_clk_osc_io ( + .in_i ( rst_clk_osc_n ), + .out_o ( rst_clk_osc_io_n ) +); + +prim_buf u_rst_clk_ext_io ( + .in_i ( rst_clk_ext_n ), + .out_o ( rst_clk_ext_io_n ) +); + +prim_buf u_rst_clk_osc_usb ( + .in_i ( rst_clk_osc_n ), + .out_o ( rst_clk_osc_usb_n ) +); + +prim_buf u_rst_clk_ext_usb ( + .in_i ( rst_clk_ext_n ), + .out_o ( rst_clk_ext_usb_n ) +); + +prim_buf u_rst_clk_osc_aon ( + .in_i ( rst_clk_osc_n ), + .out_o ( rst_clk_osc_aon_n ) +); + +prim_buf u_rst_clk_ext_aon ( + .in_i ( aon_rst_clk_ext_n ), + .out_o ( rst_clk_ext_aon_n ) +); + +// rst_aon_n deasset to io clock +//////////////////////////////////////// +logic rst_aon_n_ioda, rst_aon_ioda_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_aon_n_ioda_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_n ), + .d_i ( 1'b1 ), + .q_o ( rst_aon_n_ioda ) +); + +assign rst_aon_ioda_n = scan_mode_i ? scan_reset_ni : rst_aon_n_ioda; + +// SYS Clock Bypass Mux +//////////////////////////////////////// +gfr_clk_mux2 u_clk_src_sys_sel ( + .clk_osc_i ( clk_osc_sys_i ), + .clk_osc_val_i ( clk_osc_sys_val_i ), + .rst_clk_osc_ni ( rst_clk_osc_sys_n ), + .clk_ext_i ( clk_ext_sys ), + .clk_ext_val_i ( clk_ext_sys_val ), + .rst_clk_ext_ni ( rst_clk_ext_sys_n ), + .ext_sel_i ( sys_clk_byp_sel ), + .clk_osc_en_o ( sys_clk_osc_en ), + .clk_ext_en_o ( sys_clk_byp_en ), + .clk_val_o ( clk_src_sys_val_o ), + .clk_o ( clk_src_sys_o ) +); + +// IO Clock Bypass Mux +//////////////////////////////////////// +logic clk_src_io, clk_src_io_val; + +gfr_clk_mux2 u_clk_src_io_sel ( + .clk_osc_i ( clk_osc_io_i ), + .clk_osc_val_i ( clk_osc_io_val_i ), + .rst_clk_osc_ni ( rst_clk_osc_io_n ), + .clk_ext_i ( clk_ext_io ), + .clk_ext_val_i ( clk_ext_io_val ), + .rst_clk_ext_ni ( rst_clk_ext_io_n ), + .ext_sel_i ( io_clk_byp_sel ), + .clk_osc_en_o ( io_clk_osc_en ), + .clk_ext_en_o ( io_clk_byp_en ), + .clk_val_o ( clk_src_io_val ), + .clk_o ( clk_src_io ) +); + +`ifndef AST_BYPASS_CLK +assign clk_src_io_val_o = clk_src_io_val; +assign clk_src_io_o = clk_src_io; +`else // of AST_BYPASS_CLK +// For FPGA, clk_ext is always the one frequency, so divide by 2 if downstream +// thinks it should be "48 MHz" instead of "96 MHz". +logic ext_freq_is_96m_io_sync; +logic rst_src_io_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_rst_src_io_n_sync ( + .clk_i ( clk_src_io ), + .rst_ni ( rst_aon_n ), + .d_i ( 1'b1 ), + .q_o ( rst_src_io_n ) +); + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_ext_freq_is_96m_io_sync ( + .clk_i ( clk_src_io ), + .rst_ni ( rst_src_io_n ), + .d_i ( ext_freq_is_96m ), + .q_o ( ext_freq_is_96m_io_sync ) +); + +logic clk_src_io_div2_sel; +assign clk_src_io_div2_sel = !ext_freq_is_96m_io_sync & io_clk_byp_sel; + +prim_clock_div #( + .Divisor( 2 ) +) u_no_scan_clk_src_io_d1ord2 ( + .clk_i ( clk_src_io ), + .rst_ni ( rst_src_io_n ), + .step_down_req_i( !clk_src_io_div2_sel ), + .step_down_ack_o ( ), + .test_en_i ( scan_mode_i ), + .clk_o ( clk_src_io_o ) +); + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_clk_src_io_val_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .d_i ( clk_src_io_val ), + .q_o ( clk_src_io_val_o ) +); +`endif // of AST_BYPASS_CLK + +// USB Clock Bypass Mux +//////////////////////////////////////// +gfr_clk_mux2 u_clk_src_usb_sel ( + .clk_osc_i ( clk_osc_usb_i ), + .clk_osc_val_i ( clk_osc_usb_val_i ), + .rst_clk_osc_ni ( rst_clk_osc_usb_n ), + .clk_ext_i ( clk_ext_usb ), + .clk_ext_val_i ( clk_ext_usb_val ), + .rst_clk_ext_ni ( rst_clk_ext_usb_n ), + .ext_sel_i ( usb_clk_byp_sel ), + .clk_osc_en_o ( usb_clk_osc_en ), + .clk_ext_en_o ( usb_clk_byp_en ), + .clk_val_o ( clk_src_usb_val_o ), + .clk_o ( clk_src_usb_o ) +); + +// AON Clock Bypass Mux +//////////////////////////////////////// +gfr_clk_mux2 u_clk_src_aon_sel ( + .clk_osc_i ( clk_osc_aon_i ), + .clk_osc_val_i ( clk_osc_aon_val_i ), + .rst_clk_osc_ni ( rst_clk_osc_aon_n ), + .clk_ext_i ( clk_ext_aon ), + .clk_ext_val_i ( clk_ext_aon_val ), + .rst_clk_ext_ni ( rst_clk_ext_aon_n ), + .ext_sel_i ( aon_clk_byp_sel ), + .clk_osc_en_o ( aon_clk_osc_en ), + .clk_ext_en_o ( aon_clk_byp_en ), + .clk_val_o ( clk_src_aon_val_o ), + .clk_o ( clk_src_aon_o ) +); + +// All Clocks Bypass Acknowledge +//////////////////////////////////////// +logic all_clks_byp_en_src, all_clks_byp_en; + +always_ff @( posedge clk_aon, negedge rst_aon_n ) begin + if ( !rst_aon_n ) begin + all_clks_byp_en_src <= 1'b0; + end else begin + all_clks_byp_en_src <= sw_all_clk_byp && sys_clk_byp_en && io_clk_byp_en && + usb_clk_byp_en && aon_clk_byp_en; + end +end + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_all_clks_byp_en_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .d_i ( all_clks_byp_en_src ), + .q_o ( all_clks_byp_en ) +); + +prim_mubi4_sender #( + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_all_clk_byp_ack ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(all_clks_byp_en) ), + .mubi_o ( {all_clk_byp_ack_o} ) +); + +// IO Clock Bypass Acknowledge +//////////////////////////////////////// +logic only_io_clk_byp_en_src, only_io_clk_byp_en; + +always_ff @( posedge clk_aon, negedge rst_aon_n ) begin + if ( !rst_aon_n ) begin + only_io_clk_byp_en_src <= 1'b0; + end else begin + only_io_clk_byp_en_src <= sw_io_clk_byp && io_clk_byp_en; + end +end + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_only_io_clk_byp_en_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .d_i ( only_io_clk_byp_en_src ), + .q_o ( only_io_clk_byp_en ) +); + +prim_mubi4_sender #( + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_io_clk_byp_ack ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(only_io_clk_byp_en) ), + .mubi_o ( {io_clk_byp_ack_o} ) +); + +// IO Clock Source is 48MHz +//////////////////////////////////////// +logic io_clk_byp_is_48m_src, io_clk_byp_is_48m; + +// Oscillator source is always 96MHz. +// External Bypass source is assume to be 96MHz until it is ebabled as 48MHz +always_ff @( posedge clk_aon, negedge rst_aon_n ) begin + if ( !rst_aon_n ) begin + io_clk_byp_is_48m_src <= 1'b0; + end else begin + io_clk_byp_is_48m_src <= io_clk_byp_en && !ext_freq_is_96m; + end +end + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_io_clk_byp_is_48m_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .d_i ( io_clk_byp_is_48m_src ), + .q_o ( io_clk_byp_is_48m ) +); + +prim_mubi4_sender #( + .ResetValue ( prim_mubi_pkg::MuBi4False ) +) u_clk_src_io_48m_sync ( + .clk_i ( clk_src_io_o ), + .rst_ni ( rst_aon_ioda_n ), + .mubi_i ( prim_mubi_pkg::mubi4_bool_to_mubi(io_clk_byp_is_48m) ), + .mubi_o ( {clk_src_io_48m_o} ) +); + + +///////////////////// +// Unused Signals // +///////////////////// +logic unused_sigs; + +assign unused_sigs = ^{ io_clk_byp_sel_buf, + io_clk_byp_en_buf, + io_clk_osc_en_buf, + sys_clk_osc_en, + io_clk_osc_en, + usb_clk_osc_en, + aon_clk_osc_en + }; + +endmodule : ast_clks_byp diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_dft.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_dft.sv new file mode 100644 index 00000000000..0fc6d1a5ce0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_dft.sv @@ -0,0 +1,41 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: ast_dft +// *Module Description: AST DFT +//############################################################################ + +`include "prim_assert.sv" + +module ast_dft ( + output ast_pkg::ast_obs_ctrl_t obs_ctrl_o, // Observe Control + output logic [ast_pkg::Ast2PadOutWidth-1:0] ast2padmux_o, // DFT observed outputs + // memories read-write margins + output ast_pkg::dpm_rm_t dpram_rmf_o, // Dual Port RAM Read-write Margin Fast + output ast_pkg::dpm_rm_t dpram_rml_o, // Dual Port RAM Read-write Margin sLow + output ast_pkg::spm_rm_t spram_rm_o, // Single Port RAM Read-write Margin + output ast_pkg::spm_rm_t sprgf_rm_o, // Single Port Reg-File Read-write Margin + output ast_pkg::spm_rm_t sprom_rm_o // Single Port ROM Read-write Margin +); + +// DFT to AST Digital PADs +assign ast2padmux_o = {ast_pkg::Ast2PadOutWidth{1'b0}}; + +assign obs_ctrl_o = '{ + obgsl: 4'h0, + obmsl: ast_pkg::ObsNon, + obmen: prim_mubi_pkg::MuBi4False + }; + + +//////////////////////////////////////// +// Memories Read-write Margins +//////////////////////////////////////// +assign dpram_rmf_o = 10'h000; +assign dpram_rml_o = 10'h000; +assign spram_rm_o = 5'h00; +assign sprgf_rm_o = 5'h00; +assign sprom_rm_o = 5'h00; + +endmodule : ast_dft diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_entropy.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_entropy.sv new file mode 100644 index 00000000000..2474bf938a2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_entropy.sv @@ -0,0 +1,121 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: ast_entropy +// *Module Description: AST Entropy +//############################################################################ + +module ast_entropy #( + parameter int EntropyRateWidth = 4 +) ( + input edn_pkg::edn_rsp_t entropy_rsp_i, // Entropy Response + input [EntropyRateWidth-1:0] entropy_rate_i, // Entropy Rate + input clk_ast_es_i, // Entropy Clock + input rst_ast_es_ni, // Entropy Reset + input clk_src_sys_i, // System Source Clock + input rst_src_sys_ni, // System Source Reset + input clk_src_sys_val_i, // System Source Clock Valid + input clk_src_sys_jen_i, // System Source Clock Jitter Enable + output edn_pkg::edn_req_t entropy_req_o // Entropy Request +); + +//////////////////////////////////////// +// Entropy Request FSM +//////////////////////////////////////// +typedef enum logic [2-1:0] { + ERQ_REQ0 = 2'd1, // Device-0 Request (source) + ERQ_ACK0 = 2'd3, // Device-0 Acknowledge + ERQ_IDLE = 2'd0 // IDLE/RESET +} erq_sm_e; + +erq_sm_e erq_sm; +logic dev0_wready, dev0_ack; +logic edn_ack, edn_req; +logic [32-1:0] edn_bus; + +// Pack/Un-pack +assign entropy_req_o.edn_req = edn_req; +assign edn_ack = entropy_rsp_i.edn_ack; +assign edn_bus = entropy_rsp_i.edn_bus; + +always_ff @( posedge clk_ast_es_i, negedge rst_ast_es_ni ) begin + if ( !rst_ast_es_ni ) begin + edn_req <= 1'b0; + erq_sm <= ERQ_IDLE; + end else begin + unique case ( erq_sm ) + ERQ_IDLE: begin + if ( dev0_wready ) begin + edn_req <= 1'b1; + erq_sm <= ERQ_REQ0; + end else begin + edn_req <= 1'b0; + erq_sm <= ERQ_IDLE; + end + end + + ERQ_REQ0: begin + if ( edn_ack ) begin + edn_req <= 1'b0; + erq_sm <= ERQ_ACK0; + end else begin + edn_req <= 1'b1; + erq_sm <= ERQ_REQ0; + end + end + + ERQ_ACK0: begin + if ( dev0_wready ) begin + edn_req <= 1'b1; + erq_sm <= ERQ_REQ0; + end else begin + edn_req <= 1'b0; + erq_sm <= ERQ_ACK0; + end + end + + default: begin + edn_req <= 1'b0; + erq_sm <= ERQ_IDLE; + end + endcase + end +end + +assign dev0_ack = edn_ack && ((erq_sm == ERQ_REQ0) || (erq_sm == ERQ_ACK0)); + + +//////////////////////////////////////// +// Device 0 +//////////////////////////////////////// +logic dev0_en, dev0_entropy; + +assign dev0_en = clk_src_sys_val_i && clk_src_sys_jen_i; + +dev_entropy #( + .EntropyRateWidth ( EntropyRateWidth ) +) u_dev0_entropy ( + .clk_i ( clk_ast_es_i ), + .rst_ni ( rst_ast_es_ni ), + .clk_dev_i ( clk_src_sys_i ), + .rst_dev_ni ( rst_src_sys_ni ), + .dev_en_i ( dev0_en ), + .dev_rate_i ( entropy_rate_i[EntropyRateWidth-1:0] ), + .dev_ack_i ( dev0_ack ), + .dev_data_i ( edn_bus[32-1:0] ), + .dev_wready_o ( dev0_wready ), + .dev_data_o ( dev0_entropy ) +); + + + +///////////////////// +// Unused Signals +///////////////////// +logic unused_sigs; +assign unused_sigs = ^{ entropy_rsp_i.edn_fips, + dev0_entropy // Used in ASIC implementation + }; + +endmodule : ast_entropy diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_pkg.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_pkg.sv new file mode 100644 index 00000000000..bbd38b89bc8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_pkg.sv @@ -0,0 +1,169 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: ast_pkg +// *Module Description: AST Package +//############################################################################ +`ifdef __AST_PKG_SV +`else +`define __AST_PKG_SV + +package ast_pkg; + +parameter int unsigned NumIoRails = 2; +// Alerts +parameter int unsigned NumAlerts = 14; +parameter int unsigned AsSel = 0; +parameter int unsigned CgSel = 1; +parameter int unsigned GdSel = 2; +parameter int unsigned TsHiSel = 3; +parameter int unsigned TsLoSel = 4; +parameter int unsigned Ot0Sel = 5; +parameter int unsigned Ot1Sel = 6; +parameter int unsigned Ot2Sel = 7; +parameter int unsigned Ot3Sel = 8; +parameter int unsigned Ot4Sel = 9; +parameter int unsigned Ot5Sel = 10; +parameter int unsigned Es0Sel = 11; +parameter int unsigned Es1Sel = 12; +parameter int unsigned Es2Sel = 13; +// +parameter int unsigned Lc2HcTrCyc = 102; // ((99+1)+(3+1))x5 = 520 us +parameter int unsigned Hc2LcTrCyc = 38; // ((35+1)+(3+1))x5 = 200 us +// +parameter int unsigned EntropyStreams = 16; +parameter int unsigned AdcChannels = 2; +parameter int unsigned AdcDataWidth = 10; +parameter int unsigned UsbCalibWidth = 20; +parameter int unsigned Ast2PadOutWidth = 9; +parameter int unsigned Pad2AstInWidth = 9; +// +// AstRegsNum is the number of AST registers programmed during initialization. It includes +// the register that marks the finalization of init, which asserts the ast_init_done_o. +// The offset of this register is represented with the AstLastRegOffset parameter. +parameter int unsigned AstRegsNum = 31; +parameter int unsigned AstLastRegOffset = (AstRegsNum-1)*4; + +// Memories Read-Write Margin Interface +typedef struct packed { + logic test_a; + logic marg_en_a; + logic [4-1:0] marg_a; + logic test_b; + logic marg_en_b; + logic [4-1:0] marg_b; +} dpm_rm_t; + +typedef struct packed { + logic test; + logic marg_en; + logic [4-1:0] marg; +} spm_rm_t; + +// ADC Interface +typedef struct packed { + logic [AdcChannels-1:0] channel_sel; + logic pd; +} adc_ast_req_t; + +typedef struct packed { + logic [AdcDataWidth-1:0] data; + logic data_valid; +} adc_ast_rsp_t; + +// Analog Signal + `ifdef ANALOGSIM +typedef real awire_t; + `else +typedef logic awire_t; + `endif + +// Clock & Resets Interface +typedef struct packed { + logic clk_sys; + logic clk_io; + logic clk_aon; +} ast_clks_t; + +typedef struct packed { + logic aon_pok; +} ast_rst_t; + +parameter ast_rst_t AST_RST_DEFAULT = '{ + aon_pok: 1'b1 +}; + +typedef struct packed { + logic [NumIoRails-1:0] io_pok; +} ast_status_t; + +typedef struct packed { + logic aon_pok; + logic vcc_pok; + logic main_pok; + logic [NumIoRails-1:0] io_pok; +} ast_pwst_t; + +// Alerts Interface +typedef struct packed { + logic p; + logic n; +} ast_dif_t; + +typedef struct packed { + ast_dif_t [NumAlerts-1:0] alerts; +} ast_alert_req_t; + +typedef struct packed { + ast_dif_t [NumAlerts-1:0] alerts_ack; + ast_dif_t [NumAlerts-1:0] alerts_trig; +} ast_alert_rsp_t; + +// Ack mode enumerations +typedef enum logic { + ImmAck = 0, + SwAck = 1 +} ast_ack_mode_e; + +// Clocks Oschillator Bypass +typedef struct packed { + logic usb; + logic sys; + logic io; + logic aon; +} clks_osc_byp_t; + +typedef enum logic [4-1:0] { + ObsNon = 4'h0, // No module observed (disable) + ObsAst = 4'h1, // Observe AST + ObsFla = 4'h2, // Observe FLASH + ObsOtp = 4'h3, // Observe OTP + ObsOt0 = 4'h4, // Observe OT0 + ObsOt1 = 4'h5, // Observe OT1 + ObsOt2 = 4'h6, // Observe OT2 + ObsOt3 = 4'h7, // Observe OT3 + ObsRs0 = 4'h8, // RESERVED + ObsRs1 = 4'h9, // RESERVED + ObsRs2 = 4'hA, // RESERVED + ObsRs3 = 4'hB, // RESERVED + ObsRs4 = 4'hC, // RESERVED + ObsRs5 = 4'hD, // RESERVED + ObsRs6 = 4'hE, // RESERVED + ObsRs7 = 4'hF // RESERVED +} ast_omdl_e; + +typedef struct packed { + logic [4-1:0] obgsl; + ast_omdl_e obmsl; + prim_mubi_pkg::mubi4_t obmen; +} ast_obs_ctrl_t; + +parameter ast_obs_ctrl_t AST_OBS_CTRL_DEFAULT = '{ + obgsl: '0, + obmsl: ObsNon, + obmen: prim_mubi_pkg::MuBi4False +}; + +endpackage // of ast_pkg +`endif // of __AST_PKG_SV diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_pulse_sync.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_pulse_sync.sv new file mode 100644 index 00000000000..632e1032f99 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_pulse_sync.sv @@ -0,0 +1,147 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: ast_pulse_symc +// *Module Description: AST Pulse Synchronizer +// +// Synchronizes a pulse from source clock domain (clk_src) to destination +// clock domain (clk_dst). The source pulse can have any length of the +// source clock cycle. +// The destination pulse has the length of one destination clock cycle. +// Consecutive pulses need to be spaced appropriately apart from each other +// depending on the clock frequency ratio of the two clock domains. +//############################################################################ + +`include "prim_assert.sv" + +module ast_pulse_sync ( + input scan_mode_i, + // source clock domain + input clk_src_i, + input rst_src_ni, + input src_pulse_i, + output logic src_pulse_en_o, + output logic src_busy_o, + // destination clock domain + input clk_dst_i, + input rst_dst_ni, + output logic dst_pulse_o +); + +// Reset all flops by both resets +//////////////////////////////////////// +logic rst_src_n, rst_dst_da_n; +logic rst_dst_n, rst_src_da_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_dst_da ( + .clk_i ( clk_src_i), + .rst_ni ( rst_dst_ni ), + .d_i ( 1'b1 ), + .q_o ( rst_dst_da_n ) +); + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_src_da ( + .clk_i ( clk_dst_i), + .rst_ni ( rst_src_ni ), + .d_i ( 1'b1 ), + .q_o ( rst_src_da_n ) +); + +assign rst_src_n = scan_mode_i ? rst_src_ni : rst_src_ni && rst_dst_da_n; +assign rst_dst_n = scan_mode_i ? rst_dst_ni : rst_dst_ni && rst_src_da_n; + + +// Pulse Rising Edge Detect & Block +/////////////////////////////////////// +logic src_pulse_d; + +always_ff @( posedge clk_src_i, negedge rst_src_n ) begin + if ( !rst_src_n ) begin + src_pulse_d <= 1'b0; + end else begin + src_pulse_d <= src_pulse_i; + end +end + +assign src_pulse_en_o = src_pulse_i & !src_pulse_d & !src_busy_o; + + +// Pulse Transformation +/////////////////////////////////////// +logic src_req; + +// Convert src_pulse_en to a level signal +always_ff @( posedge clk_src_i, negedge rst_src_n ) begin + if ( !rst_src_n ) begin + src_req <= 1'b0; + end else begin + src_req <= (src_pulse_en_o ^ src_req); + end +end + + +// SRC_REQ Synchronizer to DST +/////////////////////////////////////// +logic dst_req; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_dst_req ( + .clk_i ( clk_dst_i ), + .rst_ni ( rst_dst_n ), + .d_i ( src_req ), + .q_o ( dst_req ) +); + + +// DST_REQ Synchronizer to SRC for ACK +/////////////////////////////////////// +logic src_ack; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_sync2_ack ( + .clk_i ( clk_src_i ), + .rst_ni ( rst_src_n ), + .d_i ( dst_req ), + .q_o ( src_ack ) +); + +// Source is BUSY when REQ not equel to ACK +assign src_busy_o = (src_req ^ src_ack); + + +// Pulse Reconstruction +/////////////////////////////////////// +logic dst_req_d; + +always_ff @( posedge clk_dst_i, negedge rst_dst_n ) begin + if ( !rst_dst_n ) begin + dst_req_d <= 1'b0; + end else begin + dst_req_d <= dst_req; + end +end + +assign dst_pulse_o = (dst_req ^ dst_req_d); + + +//////////////////// +// Assertions +//////////////////// + +// A new PULSE can only be introduced when source is not BUSY. +`ASSERT(NewPulseWhenSrcBusy, $rose(src_pulse_i) |-> !src_busy_o, clk_src_i, !rst_src_n) + +`ASSERT(DstPulseCheck_A, dst_pulse_o |=> !dst_pulse_o, clk_dst_i, !rst_dst_n) + +endmodule : ast_pulse_sync diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_reg_pkg.sv new file mode 100644 index 00000000000..99c70eda08f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_reg_pkg.sv @@ -0,0 +1,319 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package ast_reg_pkg; + + // Param list + parameter int NumRegsB = 5; + parameter int NumUsbBeaconPulses = 8; + + // Address widths within the block + parameter int BlockAw = 10; + + // Number of registers for every interface + parameter int NumRegs = 36; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega0_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega1_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega2_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega3_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega4_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega5_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega6_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega7_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega8_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega9_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega10_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega11_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega12_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega13_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega14_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega15_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega16_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega17_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega18_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega19_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega20_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega21_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega22_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega23_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega24_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega25_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega26_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega27_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega28_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_rega29_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } ast_reg2hw_regal_reg_t; + + typedef struct packed { + logic [31:0] q; + } ast_reg2hw_regb_mreg_t; + + typedef struct packed { + logic [31:0] d; + } ast_hw2reg_regal_reg_t; + + // Register -> HW type + typedef struct packed { + ast_reg2hw_rega0_reg_t rega0; // [1152:1121] + ast_reg2hw_rega1_reg_t rega1; // [1120:1089] + ast_reg2hw_rega2_reg_t rega2; // [1088:1057] + ast_reg2hw_rega3_reg_t rega3; // [1056:1025] + ast_reg2hw_rega4_reg_t rega4; // [1024:993] + ast_reg2hw_rega5_reg_t rega5; // [992:961] + ast_reg2hw_rega6_reg_t rega6; // [960:929] + ast_reg2hw_rega7_reg_t rega7; // [928:897] + ast_reg2hw_rega8_reg_t rega8; // [896:865] + ast_reg2hw_rega9_reg_t rega9; // [864:833] + ast_reg2hw_rega10_reg_t rega10; // [832:801] + ast_reg2hw_rega11_reg_t rega11; // [800:769] + ast_reg2hw_rega12_reg_t rega12; // [768:737] + ast_reg2hw_rega13_reg_t rega13; // [736:705] + ast_reg2hw_rega14_reg_t rega14; // [704:673] + ast_reg2hw_rega15_reg_t rega15; // [672:641] + ast_reg2hw_rega16_reg_t rega16; // [640:609] + ast_reg2hw_rega17_reg_t rega17; // [608:577] + ast_reg2hw_rega18_reg_t rega18; // [576:545] + ast_reg2hw_rega19_reg_t rega19; // [544:513] + ast_reg2hw_rega20_reg_t rega20; // [512:481] + ast_reg2hw_rega21_reg_t rega21; // [480:449] + ast_reg2hw_rega22_reg_t rega22; // [448:417] + ast_reg2hw_rega23_reg_t rega23; // [416:385] + ast_reg2hw_rega24_reg_t rega24; // [384:353] + ast_reg2hw_rega25_reg_t rega25; // [352:321] + ast_reg2hw_rega26_reg_t rega26; // [320:289] + ast_reg2hw_rega27_reg_t rega27; // [288:257] + ast_reg2hw_rega28_reg_t rega28; // [256:225] + ast_reg2hw_rega29_reg_t rega29; // [224:193] + ast_reg2hw_regal_reg_t regal; // [192:160] + ast_reg2hw_regb_mreg_t [4:0] regb; // [159:0] + } ast_reg2hw_t; + + // HW -> register type + typedef struct packed { + ast_hw2reg_regal_reg_t regal; // [31:0] + } ast_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] AST_REGA0_OFFSET = 10'h 0; + parameter logic [BlockAw-1:0] AST_REGA1_OFFSET = 10'h 4; + parameter logic [BlockAw-1:0] AST_REGA2_OFFSET = 10'h 8; + parameter logic [BlockAw-1:0] AST_REGA3_OFFSET = 10'h c; + parameter logic [BlockAw-1:0] AST_REGA4_OFFSET = 10'h 10; + parameter logic [BlockAw-1:0] AST_REGA5_OFFSET = 10'h 14; + parameter logic [BlockAw-1:0] AST_REGA6_OFFSET = 10'h 18; + parameter logic [BlockAw-1:0] AST_REGA7_OFFSET = 10'h 1c; + parameter logic [BlockAw-1:0] AST_REGA8_OFFSET = 10'h 20; + parameter logic [BlockAw-1:0] AST_REGA9_OFFSET = 10'h 24; + parameter logic [BlockAw-1:0] AST_REGA10_OFFSET = 10'h 28; + parameter logic [BlockAw-1:0] AST_REGA11_OFFSET = 10'h 2c; + parameter logic [BlockAw-1:0] AST_REGA12_OFFSET = 10'h 30; + parameter logic [BlockAw-1:0] AST_REGA13_OFFSET = 10'h 34; + parameter logic [BlockAw-1:0] AST_REGA14_OFFSET = 10'h 38; + parameter logic [BlockAw-1:0] AST_REGA15_OFFSET = 10'h 3c; + parameter logic [BlockAw-1:0] AST_REGA16_OFFSET = 10'h 40; + parameter logic [BlockAw-1:0] AST_REGA17_OFFSET = 10'h 44; + parameter logic [BlockAw-1:0] AST_REGA18_OFFSET = 10'h 48; + parameter logic [BlockAw-1:0] AST_REGA19_OFFSET = 10'h 4c; + parameter logic [BlockAw-1:0] AST_REGA20_OFFSET = 10'h 50; + parameter logic [BlockAw-1:0] AST_REGA21_OFFSET = 10'h 54; + parameter logic [BlockAw-1:0] AST_REGA22_OFFSET = 10'h 58; + parameter logic [BlockAw-1:0] AST_REGA23_OFFSET = 10'h 5c; + parameter logic [BlockAw-1:0] AST_REGA24_OFFSET = 10'h 60; + parameter logic [BlockAw-1:0] AST_REGA25_OFFSET = 10'h 64; + parameter logic [BlockAw-1:0] AST_REGA26_OFFSET = 10'h 68; + parameter logic [BlockAw-1:0] AST_REGA27_OFFSET = 10'h 6c; + parameter logic [BlockAw-1:0] AST_REGA28_OFFSET = 10'h 70; + parameter logic [BlockAw-1:0] AST_REGA29_OFFSET = 10'h 74; + parameter logic [BlockAw-1:0] AST_REGAL_OFFSET = 10'h 78; + parameter logic [BlockAw-1:0] AST_REGB_0_OFFSET = 10'h 200; + parameter logic [BlockAw-1:0] AST_REGB_1_OFFSET = 10'h 204; + parameter logic [BlockAw-1:0] AST_REGB_2_OFFSET = 10'h 208; + parameter logic [BlockAw-1:0] AST_REGB_3_OFFSET = 10'h 20c; + parameter logic [BlockAw-1:0] AST_REGB_4_OFFSET = 10'h 210; + + // Reset values for hwext registers and their fields + parameter logic [31:0] AST_REGAL_RESVAL = 32'h 1e; + parameter logic [31:0] AST_REGAL_REG32_RESVAL = 32'h 1e; + + // Register index + typedef enum int { + AST_REGA0, + AST_REGA1, + AST_REGA2, + AST_REGA3, + AST_REGA4, + AST_REGA5, + AST_REGA6, + AST_REGA7, + AST_REGA8, + AST_REGA9, + AST_REGA10, + AST_REGA11, + AST_REGA12, + AST_REGA13, + AST_REGA14, + AST_REGA15, + AST_REGA16, + AST_REGA17, + AST_REGA18, + AST_REGA19, + AST_REGA20, + AST_REGA21, + AST_REGA22, + AST_REGA23, + AST_REGA24, + AST_REGA25, + AST_REGA26, + AST_REGA27, + AST_REGA28, + AST_REGA29, + AST_REGAL, + AST_REGB_0, + AST_REGB_1, + AST_REGB_2, + AST_REGB_3, + AST_REGB_4 + } ast_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] AST_PERMIT [36] = '{ + 4'b 1111, // index[ 0] AST_REGA0 + 4'b 1111, // index[ 1] AST_REGA1 + 4'b 1111, // index[ 2] AST_REGA2 + 4'b 1111, // index[ 3] AST_REGA3 + 4'b 1111, // index[ 4] AST_REGA4 + 4'b 1111, // index[ 5] AST_REGA5 + 4'b 1111, // index[ 6] AST_REGA6 + 4'b 1111, // index[ 7] AST_REGA7 + 4'b 1111, // index[ 8] AST_REGA8 + 4'b 1111, // index[ 9] AST_REGA9 + 4'b 1111, // index[10] AST_REGA10 + 4'b 1111, // index[11] AST_REGA11 + 4'b 1111, // index[12] AST_REGA12 + 4'b 1111, // index[13] AST_REGA13 + 4'b 1111, // index[14] AST_REGA14 + 4'b 1111, // index[15] AST_REGA15 + 4'b 1111, // index[16] AST_REGA16 + 4'b 1111, // index[17] AST_REGA17 + 4'b 1111, // index[18] AST_REGA18 + 4'b 1111, // index[19] AST_REGA19 + 4'b 1111, // index[20] AST_REGA20 + 4'b 1111, // index[21] AST_REGA21 + 4'b 1111, // index[22] AST_REGA22 + 4'b 1111, // index[23] AST_REGA23 + 4'b 1111, // index[24] AST_REGA24 + 4'b 1111, // index[25] AST_REGA25 + 4'b 1111, // index[26] AST_REGA26 + 4'b 1111, // index[27] AST_REGA27 + 4'b 1111, // index[28] AST_REGA28 + 4'b 1111, // index[29] AST_REGA29 + 4'b 1111, // index[30] AST_REGAL + 4'b 1111, // index[31] AST_REGB_0 + 4'b 1111, // index[32] AST_REGB_1 + 4'b 1111, // index[33] AST_REGB_2 + 4'b 1111, // index[34] AST_REGB_3 + 4'b 1111 // index[35] AST_REGB_4 + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_reg_top.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_reg_top.sv new file mode 100644 index 00000000000..4e642e21660 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/ast_reg_top.sv @@ -0,0 +1,1639 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module ast_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output ast_reg_pkg::ast_reg2hw_t reg2hw, // Write + input ast_reg_pkg::ast_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import ast_reg_pkg::* ; + + localparam int AW = 10; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [35:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(36) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [31:0] rega0_qs; + logic [31:0] rega1_qs; + logic rega2_we; + logic [31:0] rega2_qs; + logic [31:0] rega2_wd; + logic rega3_we; + logic [31:0] rega3_qs; + logic [31:0] rega3_wd; + logic rega4_we; + logic [31:0] rega4_qs; + logic [31:0] rega4_wd; + logic rega5_we; + logic [31:0] rega5_qs; + logic [31:0] rega5_wd; + logic rega6_we; + logic [31:0] rega6_qs; + logic [31:0] rega6_wd; + logic rega7_we; + logic [31:0] rega7_qs; + logic [31:0] rega7_wd; + logic rega8_we; + logic [31:0] rega8_qs; + logic [31:0] rega8_wd; + logic rega9_we; + logic [31:0] rega9_qs; + logic [31:0] rega9_wd; + logic rega10_we; + logic [31:0] rega10_qs; + logic [31:0] rega10_wd; + logic rega11_we; + logic [31:0] rega11_qs; + logic [31:0] rega11_wd; + logic rega12_we; + logic [31:0] rega12_qs; + logic [31:0] rega12_wd; + logic rega13_we; + logic [31:0] rega13_qs; + logic [31:0] rega13_wd; + logic rega14_we; + logic [31:0] rega14_qs; + logic [31:0] rega14_wd; + logic rega15_we; + logic [31:0] rega15_qs; + logic [31:0] rega15_wd; + logic rega16_we; + logic [31:0] rega16_qs; + logic [31:0] rega16_wd; + logic rega17_we; + logic [31:0] rega17_qs; + logic [31:0] rega17_wd; + logic rega18_we; + logic [31:0] rega18_qs; + logic [31:0] rega18_wd; + logic rega19_we; + logic [31:0] rega19_qs; + logic [31:0] rega19_wd; + logic rega20_we; + logic [31:0] rega20_qs; + logic [31:0] rega20_wd; + logic rega21_we; + logic [31:0] rega21_qs; + logic [31:0] rega21_wd; + logic rega22_we; + logic [31:0] rega22_qs; + logic [31:0] rega22_wd; + logic rega23_we; + logic [31:0] rega23_qs; + logic [31:0] rega23_wd; + logic rega24_we; + logic [31:0] rega24_qs; + logic [31:0] rega24_wd; + logic rega25_we; + logic [31:0] rega25_qs; + logic [31:0] rega25_wd; + logic rega26_we; + logic [31:0] rega26_qs; + logic [31:0] rega26_wd; + logic rega27_we; + logic [31:0] rega27_qs; + logic [31:0] rega27_wd; + logic [31:0] rega28_qs; + logic rega29_we; + logic [31:0] rega29_qs; + logic [31:0] rega29_wd; + logic regal_we; + logic [31:0] regal_wd; + logic regb_0_we; + logic [31:0] regb_0_qs; + logic [31:0] regb_0_wd; + logic regb_1_we; + logic [31:0] regb_1_qs; + logic [31:0] regb_1_wd; + logic regb_2_we; + logic [31:0] regb_2_qs; + logic [31:0] regb_2_wd; + logic regb_3_we; + logic [31:0] regb_3_qs; + logic [31:0] regb_3_wd; + logic regb_4_we; + logic [31:0] regb_4_qs; + logic [31:0] regb_4_wd; + + // Register instances + // R[rega0]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_rega0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega0.q), + .ds (), + + // to register interface (read) + .qs (rega0_qs) + ); + + + // R[rega1]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h1), + .Mubi (1'b0) + ) u_rega1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega1.q), + .ds (), + + // to register interface (read) + .qs (rega1_qs) + ); + + + // R[rega2]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h2), + .Mubi (1'b0) + ) u_rega2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega2_we), + .wd (rega2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega2.q), + .ds (), + + // to register interface (read) + .qs (rega2_qs) + ); + + + // R[rega3]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h3), + .Mubi (1'b0) + ) u_rega3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega3_we), + .wd (rega3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega3.q), + .ds (), + + // to register interface (read) + .qs (rega3_qs) + ); + + + // R[rega4]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h4), + .Mubi (1'b0) + ) u_rega4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega4_we), + .wd (rega4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega4.q), + .ds (), + + // to register interface (read) + .qs (rega4_qs) + ); + + + // R[rega5]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h5), + .Mubi (1'b0) + ) u_rega5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega5_we), + .wd (rega5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega5.q), + .ds (), + + // to register interface (read) + .qs (rega5_qs) + ); + + + // R[rega6]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h6), + .Mubi (1'b0) + ) u_rega6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega6_we), + .wd (rega6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega6.q), + .ds (), + + // to register interface (read) + .qs (rega6_qs) + ); + + + // R[rega7]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h7), + .Mubi (1'b0) + ) u_rega7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega7_we), + .wd (rega7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega7.q), + .ds (), + + // to register interface (read) + .qs (rega7_qs) + ); + + + // R[rega8]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h8), + .Mubi (1'b0) + ) u_rega8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega8_we), + .wd (rega8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega8.q), + .ds (), + + // to register interface (read) + .qs (rega8_qs) + ); + + + // R[rega9]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h9), + .Mubi (1'b0) + ) u_rega9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega9_we), + .wd (rega9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega9.q), + .ds (), + + // to register interface (read) + .qs (rega9_qs) + ); + + + // R[rega10]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'ha), + .Mubi (1'b0) + ) u_rega10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega10_we), + .wd (rega10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega10.q), + .ds (), + + // to register interface (read) + .qs (rega10_qs) + ); + + + // R[rega11]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'hb), + .Mubi (1'b0) + ) u_rega11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega11_we), + .wd (rega11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega11.q), + .ds (), + + // to register interface (read) + .qs (rega11_qs) + ); + + + // R[rega12]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'hc), + .Mubi (1'b0) + ) u_rega12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega12_we), + .wd (rega12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega12.q), + .ds (), + + // to register interface (read) + .qs (rega12_qs) + ); + + + // R[rega13]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'hd), + .Mubi (1'b0) + ) u_rega13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega13_we), + .wd (rega13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega13.q), + .ds (), + + // to register interface (read) + .qs (rega13_qs) + ); + + + // R[rega14]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'he), + .Mubi (1'b0) + ) u_rega14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega14_we), + .wd (rega14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega14.q), + .ds (), + + // to register interface (read) + .qs (rega14_qs) + ); + + + // R[rega15]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'hf), + .Mubi (1'b0) + ) u_rega15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega15_we), + .wd (rega15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega15.q), + .ds (), + + // to register interface (read) + .qs (rega15_qs) + ); + + + // R[rega16]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h10), + .Mubi (1'b0) + ) u_rega16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega16_we), + .wd (rega16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega16.q), + .ds (), + + // to register interface (read) + .qs (rega16_qs) + ); + + + // R[rega17]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h11), + .Mubi (1'b0) + ) u_rega17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega17_we), + .wd (rega17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega17.q), + .ds (), + + // to register interface (read) + .qs (rega17_qs) + ); + + + // R[rega18]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h12), + .Mubi (1'b0) + ) u_rega18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega18_we), + .wd (rega18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega18.q), + .ds (), + + // to register interface (read) + .qs (rega18_qs) + ); + + + // R[rega19]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h13), + .Mubi (1'b0) + ) u_rega19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega19_we), + .wd (rega19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega19.q), + .ds (), + + // to register interface (read) + .qs (rega19_qs) + ); + + + // R[rega20]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h14), + .Mubi (1'b0) + ) u_rega20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega20_we), + .wd (rega20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega20.q), + .ds (), + + // to register interface (read) + .qs (rega20_qs) + ); + + + // R[rega21]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h15), + .Mubi (1'b0) + ) u_rega21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega21_we), + .wd (rega21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega21.q), + .ds (), + + // to register interface (read) + .qs (rega21_qs) + ); + + + // R[rega22]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h16), + .Mubi (1'b0) + ) u_rega22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega22_we), + .wd (rega22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega22.q), + .ds (), + + // to register interface (read) + .qs (rega22_qs) + ); + + + // R[rega23]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h17), + .Mubi (1'b0) + ) u_rega23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega23_we), + .wd (rega23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega23.q), + .ds (), + + // to register interface (read) + .qs (rega23_qs) + ); + + + // R[rega24]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h18), + .Mubi (1'b0) + ) u_rega24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega24_we), + .wd (rega24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega24.q), + .ds (), + + // to register interface (read) + .qs (rega24_qs) + ); + + + // R[rega25]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h19), + .Mubi (1'b0) + ) u_rega25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega25_we), + .wd (rega25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega25.q), + .ds (), + + // to register interface (read) + .qs (rega25_qs) + ); + + + // R[rega26]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h1a), + .Mubi (1'b0) + ) u_rega26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega26_we), + .wd (rega26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega26.q), + .ds (), + + // to register interface (read) + .qs (rega26_qs) + ); + + + // R[rega27]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h1b), + .Mubi (1'b0) + ) u_rega27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega27_we), + .wd (rega27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega27.q), + .ds (), + + // to register interface (read) + .qs (rega27_qs) + ); + + + // R[rega28]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h1c), + .Mubi (1'b0) + ) u_rega28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega28.q), + .ds (), + + // to register interface (read) + .qs (rega28_qs) + ); + + + // R[rega29]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h1d), + .Mubi (1'b0) + ) u_rega29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rega29_we), + .wd (rega29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rega29.q), + .ds (), + + // to register interface (read) + .qs (rega29_qs) + ); + + + // R[regal]: V(True) + logic regal_qe; + logic [0:0] regal_flds_we; + assign regal_qe = ®al_flds_we; + prim_subreg_ext #( + .DW (32) + ) u_regal ( + .re (1'b0), + .we (regal_we), + .wd (regal_wd), + .d (hw2reg.regal.d), + .qre (), + .qe (regal_flds_we[0]), + .q (reg2hw.regal.q), + .ds (), + .qs () + ); + assign reg2hw.regal.qe = regal_qe; + + + // Subregister 0 of Multireg regb + // R[regb_0]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_0_we), + .wd (regb_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[0].q), + .ds (), + + // to register interface (read) + .qs (regb_0_qs) + ); + + + // Subregister 1 of Multireg regb + // R[regb_1]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_1_we), + .wd (regb_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[1].q), + .ds (), + + // to register interface (read) + .qs (regb_1_qs) + ); + + + // Subregister 2 of Multireg regb + // R[regb_2]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_2_we), + .wd (regb_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[2].q), + .ds (), + + // to register interface (read) + .qs (regb_2_qs) + ); + + + // Subregister 3 of Multireg regb + // R[regb_3]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_3_we), + .wd (regb_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[3].q), + .ds (), + + // to register interface (read) + .qs (regb_3_qs) + ); + + + // Subregister 4 of Multireg regb + // R[regb_4]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_regb_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (regb_4_we), + .wd (regb_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.regb[4].q), + .ds (), + + // to register interface (read) + .qs (regb_4_qs) + ); + + + + logic [35:0] addr_hit; + always_comb begin + addr_hit[ 0] = (reg_addr == AST_REGA0_OFFSET); + addr_hit[ 1] = (reg_addr == AST_REGA1_OFFSET); + addr_hit[ 2] = (reg_addr == AST_REGA2_OFFSET); + addr_hit[ 3] = (reg_addr == AST_REGA3_OFFSET); + addr_hit[ 4] = (reg_addr == AST_REGA4_OFFSET); + addr_hit[ 5] = (reg_addr == AST_REGA5_OFFSET); + addr_hit[ 6] = (reg_addr == AST_REGA6_OFFSET); + addr_hit[ 7] = (reg_addr == AST_REGA7_OFFSET); + addr_hit[ 8] = (reg_addr == AST_REGA8_OFFSET); + addr_hit[ 9] = (reg_addr == AST_REGA9_OFFSET); + addr_hit[10] = (reg_addr == AST_REGA10_OFFSET); + addr_hit[11] = (reg_addr == AST_REGA11_OFFSET); + addr_hit[12] = (reg_addr == AST_REGA12_OFFSET); + addr_hit[13] = (reg_addr == AST_REGA13_OFFSET); + addr_hit[14] = (reg_addr == AST_REGA14_OFFSET); + addr_hit[15] = (reg_addr == AST_REGA15_OFFSET); + addr_hit[16] = (reg_addr == AST_REGA16_OFFSET); + addr_hit[17] = (reg_addr == AST_REGA17_OFFSET); + addr_hit[18] = (reg_addr == AST_REGA18_OFFSET); + addr_hit[19] = (reg_addr == AST_REGA19_OFFSET); + addr_hit[20] = (reg_addr == AST_REGA20_OFFSET); + addr_hit[21] = (reg_addr == AST_REGA21_OFFSET); + addr_hit[22] = (reg_addr == AST_REGA22_OFFSET); + addr_hit[23] = (reg_addr == AST_REGA23_OFFSET); + addr_hit[24] = (reg_addr == AST_REGA24_OFFSET); + addr_hit[25] = (reg_addr == AST_REGA25_OFFSET); + addr_hit[26] = (reg_addr == AST_REGA26_OFFSET); + addr_hit[27] = (reg_addr == AST_REGA27_OFFSET); + addr_hit[28] = (reg_addr == AST_REGA28_OFFSET); + addr_hit[29] = (reg_addr == AST_REGA29_OFFSET); + addr_hit[30] = (reg_addr == AST_REGAL_OFFSET); + addr_hit[31] = (reg_addr == AST_REGB_0_OFFSET); + addr_hit[32] = (reg_addr == AST_REGB_1_OFFSET); + addr_hit[33] = (reg_addr == AST_REGB_2_OFFSET); + addr_hit[34] = (reg_addr == AST_REGB_3_OFFSET); + addr_hit[35] = (reg_addr == AST_REGB_4_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(AST_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(AST_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(AST_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(AST_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(AST_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(AST_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(AST_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(AST_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(AST_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(AST_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(AST_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(AST_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(AST_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(AST_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(AST_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(AST_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(AST_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(AST_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(AST_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(AST_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(AST_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(AST_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(AST_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(AST_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(AST_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(AST_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(AST_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(AST_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(AST_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(AST_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(AST_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(AST_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(AST_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(AST_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(AST_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(AST_PERMIT[35] & ~reg_be))))); + end + + // Generate write-enables + assign rega2_we = addr_hit[2] & reg_we & !reg_error; + + assign rega2_wd = reg_wdata[31:0]; + assign rega3_we = addr_hit[3] & reg_we & !reg_error; + + assign rega3_wd = reg_wdata[31:0]; + assign rega4_we = addr_hit[4] & reg_we & !reg_error; + + assign rega4_wd = reg_wdata[31:0]; + assign rega5_we = addr_hit[5] & reg_we & !reg_error; + + assign rega5_wd = reg_wdata[31:0]; + assign rega6_we = addr_hit[6] & reg_we & !reg_error; + + assign rega6_wd = reg_wdata[31:0]; + assign rega7_we = addr_hit[7] & reg_we & !reg_error; + + assign rega7_wd = reg_wdata[31:0]; + assign rega8_we = addr_hit[8] & reg_we & !reg_error; + + assign rega8_wd = reg_wdata[31:0]; + assign rega9_we = addr_hit[9] & reg_we & !reg_error; + + assign rega9_wd = reg_wdata[31:0]; + assign rega10_we = addr_hit[10] & reg_we & !reg_error; + + assign rega10_wd = reg_wdata[31:0]; + assign rega11_we = addr_hit[11] & reg_we & !reg_error; + + assign rega11_wd = reg_wdata[31:0]; + assign rega12_we = addr_hit[12] & reg_we & !reg_error; + + assign rega12_wd = reg_wdata[31:0]; + assign rega13_we = addr_hit[13] & reg_we & !reg_error; + + assign rega13_wd = reg_wdata[31:0]; + assign rega14_we = addr_hit[14] & reg_we & !reg_error; + + assign rega14_wd = reg_wdata[31:0]; + assign rega15_we = addr_hit[15] & reg_we & !reg_error; + + assign rega15_wd = reg_wdata[31:0]; + assign rega16_we = addr_hit[16] & reg_we & !reg_error; + + assign rega16_wd = reg_wdata[31:0]; + assign rega17_we = addr_hit[17] & reg_we & !reg_error; + + assign rega17_wd = reg_wdata[31:0]; + assign rega18_we = addr_hit[18] & reg_we & !reg_error; + + assign rega18_wd = reg_wdata[31:0]; + assign rega19_we = addr_hit[19] & reg_we & !reg_error; + + assign rega19_wd = reg_wdata[31:0]; + assign rega20_we = addr_hit[20] & reg_we & !reg_error; + + assign rega20_wd = reg_wdata[31:0]; + assign rega21_we = addr_hit[21] & reg_we & !reg_error; + + assign rega21_wd = reg_wdata[31:0]; + assign rega22_we = addr_hit[22] & reg_we & !reg_error; + + assign rega22_wd = reg_wdata[31:0]; + assign rega23_we = addr_hit[23] & reg_we & !reg_error; + + assign rega23_wd = reg_wdata[31:0]; + assign rega24_we = addr_hit[24] & reg_we & !reg_error; + + assign rega24_wd = reg_wdata[31:0]; + assign rega25_we = addr_hit[25] & reg_we & !reg_error; + + assign rega25_wd = reg_wdata[31:0]; + assign rega26_we = addr_hit[26] & reg_we & !reg_error; + + assign rega26_wd = reg_wdata[31:0]; + assign rega27_we = addr_hit[27] & reg_we & !reg_error; + + assign rega27_wd = reg_wdata[31:0]; + assign rega29_we = addr_hit[29] & reg_we & !reg_error; + + assign rega29_wd = reg_wdata[31:0]; + assign regal_we = addr_hit[30] & reg_we & !reg_error; + + assign regal_wd = reg_wdata[31:0]; + assign regb_0_we = addr_hit[31] & reg_we & !reg_error; + + assign regb_0_wd = reg_wdata[31:0]; + assign regb_1_we = addr_hit[32] & reg_we & !reg_error; + + assign regb_1_wd = reg_wdata[31:0]; + assign regb_2_we = addr_hit[33] & reg_we & !reg_error; + + assign regb_2_wd = reg_wdata[31:0]; + assign regb_3_we = addr_hit[34] & reg_we & !reg_error; + + assign regb_3_wd = reg_wdata[31:0]; + assign regb_4_we = addr_hit[35] & reg_we & !reg_error; + + assign regb_4_wd = reg_wdata[31:0]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = 1'b0; + reg_we_check[1] = 1'b0; + reg_we_check[2] = rega2_we; + reg_we_check[3] = rega3_we; + reg_we_check[4] = rega4_we; + reg_we_check[5] = rega5_we; + reg_we_check[6] = rega6_we; + reg_we_check[7] = rega7_we; + reg_we_check[8] = rega8_we; + reg_we_check[9] = rega9_we; + reg_we_check[10] = rega10_we; + reg_we_check[11] = rega11_we; + reg_we_check[12] = rega12_we; + reg_we_check[13] = rega13_we; + reg_we_check[14] = rega14_we; + reg_we_check[15] = rega15_we; + reg_we_check[16] = rega16_we; + reg_we_check[17] = rega17_we; + reg_we_check[18] = rega18_we; + reg_we_check[19] = rega19_we; + reg_we_check[20] = rega20_we; + reg_we_check[21] = rega21_we; + reg_we_check[22] = rega22_we; + reg_we_check[23] = rega23_we; + reg_we_check[24] = rega24_we; + reg_we_check[25] = rega25_we; + reg_we_check[26] = rega26_we; + reg_we_check[27] = rega27_we; + reg_we_check[28] = 1'b0; + reg_we_check[29] = rega29_we; + reg_we_check[30] = regal_we; + reg_we_check[31] = regb_0_we; + reg_we_check[32] = regb_1_we; + reg_we_check[33] = regb_2_we; + reg_we_check[34] = regb_3_we; + reg_we_check[35] = regb_4_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[31:0] = rega0_qs; + end + + addr_hit[1]: begin + reg_rdata_next[31:0] = rega1_qs; + end + + addr_hit[2]: begin + reg_rdata_next[31:0] = rega2_qs; + end + + addr_hit[3]: begin + reg_rdata_next[31:0] = rega3_qs; + end + + addr_hit[4]: begin + reg_rdata_next[31:0] = rega4_qs; + end + + addr_hit[5]: begin + reg_rdata_next[31:0] = rega5_qs; + end + + addr_hit[6]: begin + reg_rdata_next[31:0] = rega6_qs; + end + + addr_hit[7]: begin + reg_rdata_next[31:0] = rega7_qs; + end + + addr_hit[8]: begin + reg_rdata_next[31:0] = rega8_qs; + end + + addr_hit[9]: begin + reg_rdata_next[31:0] = rega9_qs; + end + + addr_hit[10]: begin + reg_rdata_next[31:0] = rega10_qs; + end + + addr_hit[11]: begin + reg_rdata_next[31:0] = rega11_qs; + end + + addr_hit[12]: begin + reg_rdata_next[31:0] = rega12_qs; + end + + addr_hit[13]: begin + reg_rdata_next[31:0] = rega13_qs; + end + + addr_hit[14]: begin + reg_rdata_next[31:0] = rega14_qs; + end + + addr_hit[15]: begin + reg_rdata_next[31:0] = rega15_qs; + end + + addr_hit[16]: begin + reg_rdata_next[31:0] = rega16_qs; + end + + addr_hit[17]: begin + reg_rdata_next[31:0] = rega17_qs; + end + + addr_hit[18]: begin + reg_rdata_next[31:0] = rega18_qs; + end + + addr_hit[19]: begin + reg_rdata_next[31:0] = rega19_qs; + end + + addr_hit[20]: begin + reg_rdata_next[31:0] = rega20_qs; + end + + addr_hit[21]: begin + reg_rdata_next[31:0] = rega21_qs; + end + + addr_hit[22]: begin + reg_rdata_next[31:0] = rega22_qs; + end + + addr_hit[23]: begin + reg_rdata_next[31:0] = rega23_qs; + end + + addr_hit[24]: begin + reg_rdata_next[31:0] = rega24_qs; + end + + addr_hit[25]: begin + reg_rdata_next[31:0] = rega25_qs; + end + + addr_hit[26]: begin + reg_rdata_next[31:0] = rega26_qs; + end + + addr_hit[27]: begin + reg_rdata_next[31:0] = rega27_qs; + end + + addr_hit[28]: begin + reg_rdata_next[31:0] = rega28_qs; + end + + addr_hit[29]: begin + reg_rdata_next[31:0] = rega29_qs; + end + + addr_hit[30]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[31]: begin + reg_rdata_next[31:0] = regb_0_qs; + end + + addr_hit[32]: begin + reg_rdata_next[31:0] = regb_1_qs; + end + + addr_hit[33]: begin + reg_rdata_next[31:0] = regb_2_qs; + end + + addr_hit[34]: begin + reg_rdata_next[31:0] = regb_3_qs; + end + + addr_hit[35]: begin + reg_rdata_next[31:0] = regb_4_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/dev_entropy.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/dev_entropy.sv new file mode 100644 index 00000000000..230ca422431 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/dev_entropy.sv @@ -0,0 +1,256 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: dev_entropy +// *Module Description: Device Entropy +//############################################################################ + +module dev_entropy #( + parameter int EntropyRateWidth = 4 +) ( + input clk_i, // Entropy Clock + input rst_ni, // Entropy Reset + input clk_dev_i, // Device Clock + input rst_dev_ni, // Device Reset + input dev_en_i, // Device Enable + input [EntropyRateWidth-1:0] dev_rate_i, // Entropy Rate + input dev_ack_i, // Write Valid (EDN_ACK) + input [32-1:0] dev_data_i, // Write Data (EDN_BUS) + output logic dev_wready_o, // Write Ready (EDN_REQ) + output logic dev_data_o // Entropy Data +); + + +//////////////////////////////////// +// Device Enable Sync +//////////////////////////////////// +logic dev_en_dev; + +// Sync dev_en to Dev clock +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_dev_en_dev_sync ( + .clk_i ( clk_dev_i ), + .rst_ni ( rst_dev_ni ), + .d_i ( dev_en_i ), + .q_o ( dev_en_dev ) +); + + +//////////////////////////////////// +// Entropy Rate +/////////////////////////////////////// +logic fast_start, rate_pulse, rready; +logic [7-1:0] fast_cnt; +logic [(1< 1 || EN -> 0 + +// Clock Output Buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_buf ( + .clk_i ( clk ), + .clk_o ( io_clk_o ) +); + + +`ifdef SYNTHESIS +///////////////////////// +// Unused Signals +///////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ io_osc_cal_i }; +`endif + +endmodule : io_osc diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/rglts_pdm_3p3v.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/rglts_pdm_3p3v.sv new file mode 100644 index 00000000000..511a978100d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/rglts_pdm_3p3v.sv @@ -0,0 +1,412 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: rglts_pdm_3p3v +// *Module Description: Regulators (MAIN & AON) & PDM Logic @3.3V +//############################################################################ + +`include "prim_assert.sv" + +module rglts_pdm_3p3v ( + input vcc_pok_h_i, // VCC Exist @3.3v + input vcaon_pok_por_h_i, // VCAON_POK_POR @1.1v + input vcmain_pok_por_h_i, // VCMAIN_POK_POR @1.1v + input [2-1:0] vio_pok_h_i, // vioa/b_pok signals @1.1v + input clk_src_aon_h_i, // AON Clock @1.1v + input main_pd_h_i, // MAIN Regulator Power Down @1.1v + input por_sync_h_i, // POR (Sync to AON clock) @1.1v + input scan_mode_h_i, // Scan Mode @1.1v + input [2-1:0] otp_power_seq_h_i, // MMR0,24 in @1.1v + input vcaon_supp_i, // + input vcmain_supp_i, // + output logic rglssm_vmppr_h_o, // Regulators SM at VMPPR (vcmaim_pok_por_reset) @3.3v + output logic rglssm_vcmon_h_o, // Regulators state machine at VCMON @3.3v + output logic rglssm_brout_h_o, // Regulators state machine at BROUT @3.3v + output logic vcmain_pok_h_o, // VCMAIN POK @3.3v + output logic vcmain_pok_por_h_o, // VCMAIN_POK_POR @3.3v + output logic vcaon_pok_h_o, // VCAON Exist @3.3v + output logic vcaon_pok_1p1_h_o, // VCAON Exist @3.3v for BE 1.1v (UPF issue) + output logic vcaon_pok_por_h_o, // VCAON_POK_POR @3.3v + output logic [2-1:0] vio_pok_h_o, // vioa/b_pok_h signals @3.3v + output logic vcc_pok_str_h_o, // VCC Exist Stretched @3.3V + output logic vcc_pok_str_1p1_h_o, // VCC Exist Stretched @3.3V for BE 1.1v (UPF issue) + output logic deep_sleep_h_o, // Deep Sleep (main regulator & switch are off) @3.3v + output logic flash_power_down_h_o, // + output logic flash_power_ready_h_o, // + output logic [2-1:0] otp_power_seq_h_o // MMR0,24 masked by PDM, out (VCC) +); + +// Turn 1.1v into 3.3v signals +//////////////////////////////////////// +assign vcaon_pok_por_h_o = vcaon_pok_por_h_i; // Level Up Shifter +assign vcmain_pok_por_h_o = vcmain_pok_por_h_i; // Level Up Shifter +assign vio_pok_h_o[1:0] = vio_pok_h_i[1:0]; // Level Up Shifter + + +/////////////////////////////////////// +// Regulators Enable State Machine +/////////////////////////////////////// +logic fla_pdm_h, otp_pdm_h; +logic [9-1:0] dly_cnt, hc2lc_val, lc2hc_val; // upto 255 aon clock (1275us) + +// DV Hook +logic [1:0] dv_hook, dft_sel; + +`ifndef SYNTHESIS +initial begin + // Regulator Power-up time (non cold power-up) selected according to 'dv_hook' value: + // + // 0: hc2lc_val=HC2LCOC; lc2hc_val=LC2HCOC; + // 1: hc2lc_val=HC2LCOC*2; lc2hc_val=LC2HCOC*2; + // 2: hc2lc_val=9'd2; lc2hc_val=9'd6; + // 3: hc2lc_val=9'd4; lc2hc_val=9'd12; + // + if ( !$value$plusargs("accelerate_regulators_power_up_time=%d", dv_hook) ) begin + dv_hook = 2'd0; + end + `ASSERT_I(accelerate_regulators_power_up_time, dv_hook inside {[0:3]}) +end +`else +assign dv_hook = 2'd0; +`endif + +localparam int unsigned HC2LCOC = ast_pkg::Hc2LcTrCyc; +localparam int unsigned LC2HCOC = ast_pkg::Lc2HcTrCyc; +logic [9-1:0] cld_pu_val; + +`ifndef SYNTHESIS +initial begin + // Cold Power-up time can be selected between 2 and LC2HCOC (default: ast_pkg::Lc2HcTrCyc) + if ( !$value$plusargs("accelerate_cold_power_up_time=%d", cld_pu_val) ) begin + cld_pu_val = LC2HCOC[9-1:0]; + end + `ASSERT_I(accelerate_cold_power_up_time, cld_pu_val inside {[2:LC2HCOC[9-1:0]]}) +end +`else +assign cld_pu_val = LC2HCOC[9-1:0]; +`endif + +// Force 2'b11 to reduce LDOs time & double LDOs start-up time +assign dft_sel = dv_hook; + +assign hc2lc_val = (dft_sel == 2'b10) ? 9'd2 : + (dft_sel == 2'b11) ? 9'd4 : + (dft_sel == 2'b00) ? HC2LCOC[9-1:0] : + HC2LCOC[8-1:0]*2; + +assign lc2hc_val = (dft_sel == 2'b10) ? 9'd6 : + (dft_sel == 2'b11) ? 9'd12 : + (dft_sel == 2'b00) ? LC2HCOC[9-1:0] : + LC2HCOC[8-1:0]*2; + + + +/////////////////////////////////////// +// Regulators State Machine +/////////////////////////////////////// +typedef enum logic [3-1:0] { + RGLS_CLDPU = 3'd0, // Cold power-up (MAIN Regulator ON, AON Regulator OFF, Power Switch Enabled) + RGLS_VCMON = 3'd1, // MAIN Regulator ON (AON Regulator OFF, Power Switch Enabled) + RGLS_VCM2A = 3'd3, // MAIN Regulator ON (AON Regulator rN, Power Switch Enabled->Disabled) + RGLS_VCAON = 3'd7, // AON Regulator ON (MAIN Regulator OFF, Power Switch Diabled) + RGLS_VCA2M = 3'd5, // AON Regulator ON (MAIN Regulator ON, Power Switch Diabled->Enabled) + RGLS_BROUT = 3'd6 // Brownout (MAIN Regulator ON, AON Regulator OFF, Power Switch Enabled) +} rgls_sm_e; + +rgls_sm_e rgls_sm; +logic vcmain_pok_h, vcaon_pok_h, main_pd_str_h; + +// Hold state machin reset on brownout for minimum 13us. +logic rgls_rst_h_n; +assign rgls_rst_h_n = vcc_pok_str_h_o; + +// Syncronizers +// First stage clk FE & second clk RE +/////////////////////////////////////// +logic vcc_pok_fe_h, vcc_pok_s_h; + + +logic clk_src_aon_h_n; +assign clk_src_aon_h_n = scan_mode_h_i ? clk_src_aon_h_i : + !clk_src_aon_h_i; + +always_ff @( posedge clk_src_aon_h_n, negedge rgls_rst_h_n ) begin + if ( !rgls_rst_h_n ) begin + vcc_pok_fe_h <= 1'b0; + end else begin + vcc_pok_fe_h <= vcc_pok_h_i; + end +end + +always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin + if ( !rgls_rst_h_n ) begin + vcc_pok_s_h <= 1'b0; + end else begin + vcc_pok_s_h <= vcc_pok_fe_h; + end +end + +// Regulators State Mashine +//////////////////////////////////////// +always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin + if ( !rgls_rst_h_n ) begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled + vcaon_pok_h <= 1'b0; // VCAON Rail Disabled + main_pd_str_h <= 1'b0; // Power Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= cld_pu_val; // VCMAIN Regulator power-up time + // + rgls_sm <= RGLS_CLDPU; // Power VCMAIN (Cold) + end else begin + unique case ( rgls_sm ) + RGLS_CLDPU: begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled + vcaon_pok_h <= 1'b0; // VCAON Rail Disabled + main_pd_str_h <= 1'b0; // Power Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON)||(rgls_sm == RGLS_BROUT)) + // + dly_cnt <= dly_cnt - 1'b1; + // + if (dly_cnt == '0) begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enable + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON) + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + fla_pdm_h <= 1'b0; // + rgls_sm <= RGLS_VCMON; // VCMAIN Regultor is ON! + end else begin + rgls_sm <= RGLS_CLDPU; // Power VCMAIN! + end + end + + RGLS_VCMON: begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enabled + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b0; // Power Down Stratch + // + rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON) + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b0; // + // + dly_cnt <= hc2lc_val; // VCAON Regulator power-up time + // + if ( !vcc_pok_s_h ) begin + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b1; // (rgls_sm == RGLS_BROUT) + fla_pdm_h <= 1'b0; // + rgls_sm <= RGLS_BROUT; // Brownout + end else if ( main_pd_h_i && !por_sync_h_i ) begin + main_pd_str_h <= 1'b1; // Power Down Stratch on + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + rgls_sm <= RGLS_VCM2A; // VCMAIN to VCAON Transition + end else begin + rgls_sm <= RGLS_VCMON; // VCMAIN Regulator is ON! + end + end + + RGLS_VCM2A: begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enabled + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b1; // Power Down Stratch + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= dly_cnt - 1'b1; + // + if ( por_sync_h_i ) begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enable + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON) + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + fla_pdm_h <= 1'b0; // + rgls_sm <= RGLS_VCMON; // VCMAIN Regultor is ON! + end else if ( dly_cnt == '0 ) begin + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rgls_sm <= RGLS_VCAON; // VCAON Regulator is ON! + end else begin + rgls_sm <= RGLS_VCM2A; // VCMAIN to VCAON Transition + end + end + + RGLS_VCAON: begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b1; // Power Down Stratch + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time + // + if ( !main_pd_h_i || por_sync_h_i ) begin + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rgls_sm <= RGLS_VCA2M; // VCAON->VCMAIN Transition + end else begin + rgls_sm <= RGLS_VCAON; // VCAON Regulator is ON! + end + end + + RGLS_VCA2M: begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disable + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b0; // Power Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= dly_cnt - 1'b1; + // + if ( dly_cnt == '0 ) begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enable + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + rglssm_vcmon_h_o <= 1'b1; // (rgls_sm == RGLS_VCMON) + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + fla_pdm_h <= 1'b0; // + rgls_sm <= RGLS_VCMON; // VCMAIN Regulator is ON! + end else begin + rgls_sm <= RGLS_VCA2M; // VCAON->VCMAIN Transition + end + end + + RGLS_BROUT: begin + vcmain_pok_h <= 1'b1; // VCMAIN Rail Enabled + vcaon_pok_h <= 1'b1; // VCAON Rail Enabled + main_pd_str_h <= 1'b0; // Powe Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b0; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b1; // (rgls_sm == RGLS_BROUT) + fla_pdm_h <= 1'b0; // + // + dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time + // + rgls_sm <= RGLS_BROUT; // Brownout + end + + default: begin + vcmain_pok_h <= 1'b0; // VCMAIN Rail Disabled + vcaon_pok_h <= 1'b0; // VCAON Rail Disabled + main_pd_str_h <= 1'b0; // Powe Down Stratch off + // + rglssm_vcmon_h_o <= 1'b0; // + rglssm_vmppr_h_o <= 1'b1; // (rgls_sm == RRGLS_[CLDPU | VCAON | VCA2M]) + rglssm_brout_h_o <= 1'b0; // + fla_pdm_h <= 1'b1; // !((rgls_sm == RGLS_VCMON) || (rgls_sm == RGLS_BROUT)) + // + dly_cnt <= lc2hc_val; // VCMAIN Regulator power-up time + // + rgls_sm <= RGLS_CLDPU; // Power VCMAIN (Cold) + end + endcase + end +end + + +/////////////////////////////////////// +// VCMAIN_POK & VCAON POK +/////////////////////////////////////// +assign vcmain_pok_h_o = vcmain_pok_h && vcmain_supp_i; +// VCAON POK is needed for cold power-up to enable the AON clock +// Therefore, it is connected directly to VCC POK. +assign vcaon_pok_h_o = vcc_pok_h_i && vcaon_supp_i; +assign vcaon_pok_1p1_h_o = vcaon_pok_h_o; // For layout separation + + +/////////////////////////////////////// +// Streched VCC_POK During Brownout +/////////////////////////////////////// +localparam int VccPokStrNum = 4; // (Min-Max) (3-4)x5us=(15-20)us + +logic vcc_pok_set_h, vcc_pok_rst_h_n; +logic [VccPokStrNum-1:0] vcc_pok_str_no_scan_h; + +assign vcc_pok_rst_h_n = vcc_pok_h_i || vcaon_pok_h_o; // Non-Scan + +// Enable proper order of reset/set execution +always_comb begin + vcc_pok_set_h = vcc_pok_rst_h_n && vcc_pok_h_i; +end + +always_ff @( posedge clk_src_aon_h_i, negedge vcc_pok_rst_h_n, posedge vcc_pok_set_h ) begin + if ( !vcc_pok_rst_h_n ) begin + vcc_pok_str_no_scan_h[0] <= 1'b0; + end else if ( vcc_pok_set_h ) begin + vcc_pok_str_no_scan_h[0] <= 1'b1; + end else begin + vcc_pok_str_no_scan_h[0] <= 1'b0; + end +end + +for (genvar i = 1; i < VccPokStrNum; i++ ) begin : gen_vcc_pok_str + always_ff @( posedge clk_src_aon_h_i, negedge vcc_pok_rst_h_n, posedge vcc_pok_set_h ) begin + if ( !vcc_pok_rst_h_n ) begin + vcc_pok_str_no_scan_h[i] <= 1'b0; + end else if ( vcc_pok_set_h ) begin + vcc_pok_str_no_scan_h[i] <= 1'b1; + end else begin + vcc_pok_str_no_scan_h[i] <= vcc_pok_str_no_scan_h[i-1]; + end + end +end + +assign vcc_pok_str_h_o = vcc_pok_str_no_scan_h[VccPokStrNum-1]; +assign vcc_pok_str_1p1_h_o = vcc_pok_str_no_scan_h[VccPokStrNum-1]; + + +/////////////////////////////////////// +// Deep Sleep Indication +/////////////////////////////////////// +always_ff @( posedge clk_src_aon_h_i, negedge rgls_rst_h_n ) begin + if ( !rgls_rst_h_n ) begin + deep_sleep_h_o <= 1'b0; + end else begin + deep_sleep_h_o <= main_pd_h_i || main_pd_str_h; + end +end + + +/////////////////////////////////////// +// Flash +/////////////////////////////////////// +// fla_pdm_h = !(rglssm_vcmon || rglssm_brout); +assign flash_power_down_h_o = scan_mode_h_i || fla_pdm_h; +assign flash_power_ready_h_o = vcc_pok_h_i; + + +/////////////////////////////////////// +// OTP +/////////////////////////////////////// +assign otp_pdm_h = !rglssm_vcmon_h_o; +assign otp_power_seq_h_o[0] = !scan_mode_h_i && !otp_pdm_h && otp_power_seq_h_i[0]; +assign otp_power_seq_h_o[1] = scan_mode_h_i || otp_pdm_h || otp_power_seq_h_i[1]; + + +///////////////////// +// Unused Signals // +///////////////////// +logic unused_sigs; + +assign unused_sigs = ^{ vcaon_pok_h }; + +endmodule : rglts_pdm_3p3v diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/rng.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/rng.sv new file mode 100644 index 00000000000..f1b20b7504e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/rng.sv @@ -0,0 +1,170 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +//############################################################################ +// *Name: rng +// *Module Description: Random (bit/s) Generator (Pseudo Model) +//############################################################################ + +`include "prim_assert.sv" + +module rng #( + parameter int EntropyStreams = 4 +) ( + input clk_i, // Non-Jittery Clock (TLUL) + input rst_ni, // Non-Jittery Reset (TLUL) + input clk_ast_rng_i, // Jittery Clock (RNG) + input rst_ast_rng_ni, // Jittery Reset (RNG) + input rng_en_i, // RNG Enable + input rng_fips_i, // RNG FIPS Enable + input scan_mode_i, // Scan Mode + output logic [EntropyStreams-1:0] rng_b_o, // RNG Bus/Bits Output + output logic rng_val_o // RNG Bus/Bits Valid +); + +/////////////////////////////////////// +// RNG Bus using LFSR +/////////////////////////////////////// +logic rst_n; +logic[EntropyStreams-1:0] lfsr_val; + +assign rst_n = scan_mode_i ? rst_ni : rst_ni && rng_en_i; + +// These LFSR parameters have been generated with +// $ ./util/design/gen-lfsr-seed.py --width 64 --seed 15513 --prefix "Rng" +localparam int RngLfsrWidth = 64; +typedef logic [RngLfsrWidth-1:0] rng_lfsr_seed_t; +typedef logic [RngLfsrWidth-1:0][$clog2(RngLfsrWidth)-1:0] rng_lfsr_perm_t; +localparam rng_lfsr_seed_t RndCnstRngLfsrSeedDefault = 64'h1d033d20eed3b14; +localparam rng_lfsr_perm_t RndCnstRngLfsrPermDefault = { + 128'h98c2c94ab5e40420ed73f6c7396cd9e1, + 256'h58c6d7435ddb2ed1f22400c53a5aaa796ef7785e120628fbabc87f0b3928550f +}; + +prim_lfsr #( + .LfsrDw ( RngLfsrWidth ), + .EntropyDw ( 1 ), + .StateOutDw ( EntropyStreams ), + .DefaultSeed ( RndCnstRngLfsrSeedDefault ), + .StatePermEn ( 1'b1 ), + .StatePerm ( RndCnstRngLfsrPermDefault ), + .ExtSeedSVA ( 1'b0 ) // ext seed is unused +) u_rng_lfsr ( + .clk_i ( clk_i ), + .rst_ni ( rst_n ), + .lfsr_en_i ( rng_en_i ), + .seed_en_i ( 1'b0 ), + .seed_i ( '0 ), + .entropy_i ( 1'b0 ), + .state_o ( lfsr_val ) +); + +// The digital noise source vendor IP of Earlgrey has 4 entropy streams whereas the entropy source +// vendor IP of Darjeeling has 16 entropy streams. For simplicity, this model takes 16 instead of +// just 4 LSBs of the LFSR above for Darjeeling. To remain compliant with the rate modulation +// performed in DV, the rate counter for Darjeeling is modified to count 4 times slower. Both +// models thus provide entropy at the same rate. +localparam int SRateWidth = 6; +localparam int SRateCntWidth = 6; + +logic srate_rng_val; +logic [SRateWidth-1:0] srate_value; +logic [SRateCntWidth-1:0] srate_cnt; +logic srate_cnt_expired; + +logic [EntropyStreams-1:0] rng_b; + +`ifndef SYNTHESIS +logic [SRateWidth-1:0] dv_srate_value; +// 16-bit rng_b needs at least 3 clock up to 34 +logic [SRateWidth-1:0] rng_srate_value_min = SRateWidth'(3); +logic [SRateWidth-1:0] rng_srate_value_max = SRateWidth'(34); + +initial begin : rng_plusargs + void'($value$plusargs("rng_srate_value_min=%0d", rng_srate_value_min)); + void'($value$plusargs("rng_srate_value_max=%0d", rng_srate_value_max)); + `ASSERT_I(DvRngSrateMinCheck, rng_srate_value_min inside {[3:34]}) + `ASSERT_I(DvRngSrateMaxCheck, rng_srate_value_max inside {[3:34]}) + `ASSERT_I(DvRngSrateBoundsCheck, rng_srate_value_max >= rng_srate_value_min) + dv_srate_value = + SRateWidth'($urandom_range(int'(rng_srate_value_min), int'(rng_srate_value_max))); + void'($value$plusargs("rng_srate_value=%0d", dv_srate_value)); + `ASSERT_I(DvSrateValueCheck, dv_srate_value inside {[3:34]}) +end + +assign srate_value = dv_srate_value; +`else +assign srate_value = SRateWidth'(3); +`endif + +logic src_busy; +assign srate_cnt_expired = (srate_cnt == srate_value); + +always_ff @( posedge clk_i, negedge rst_n ) begin + if ( !rst_n ) begin + srate_cnt <= '0; + srate_rng_val <= 1'b0; + end else if ( srate_cnt_expired && src_busy ) begin + srate_rng_val <= 1'b0; + end else if ( srate_cnt_expired ) begin + srate_cnt <= '0; + srate_rng_val <= 1'b1; + end else begin + srate_cnt <= srate_cnt + 1'b1; + srate_rng_val <= 1'b0; + end +end + + +//////////////////////////////////////// +// Sychronize Bus & Valid to RNG Clock +//////////////////////////////////////// +logic sync_rng_val, srate_rng_val_en; + +ast_pulse_sync u_rng_val_pulse_sync ( + .scan_mode_i ( scan_mode_i ), + // source clock domain + .clk_src_i ( clk_i ), + .rst_src_ni ( rst_n ), + .src_pulse_i ( srate_rng_val ), + .src_pulse_en_o ( srate_rng_val_en ), + .src_busy_o ( src_busy ), + // destination clock domain + .clk_dst_i ( clk_ast_rng_i ), + .rst_dst_ni ( rst_ast_rng_ni ), + .dst_pulse_o ( sync_rng_val ) +); + +// Sample & Hold the rng_b value until the sync completes +always_ff @( posedge clk_i, negedge rst_n ) begin + if ( !rst_n ) begin + rng_b <= {EntropyStreams{1'b0}}; + end else if ( srate_rng_val_en ) begin + rng_b <= lfsr_val[EntropyStreams-1:0]; + end +end + +//Sync to RNG clock domain +always_ff @( posedge clk_ast_rng_i, negedge rst_ast_rng_ni ) begin + if (!rst_ast_rng_ni ) begin + rng_b_o <= {EntropyStreams{1'b0}}; + rng_val_o <= 1'b0; + end else if ( sync_rng_val ) begin + rng_b_o <= rng_b[EntropyStreams-1:0]; + rng_val_o <= 1'b1; + end else begin + rng_val_o <= 1'b0; + end +end + + +/////////////////////// +// Unused Signals +/////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ + rng_fips_i // Used in ASIC implementation + }; + +endmodule : rng diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/sys_clk.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/sys_clk.sv new file mode 100644 index 00000000000..332c3f3dd97 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/sys_clk.sv @@ -0,0 +1,65 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: sys_clk +// *Module Description: System Clock +//############################################################################ + +module sys_clk ( + input clk_src_sys_jen_i, // System Source Clock Jitter Enable + input clk_src_sys_en_i, // System Source Clock Enable + input clk_sys_pd_ni, // System Clock Power-down + input rst_sys_clk_ni, // System Clock Logic reset + input vcore_pok_h_i, // VCORE POK @3.3V (for OSC) + input scan_mode_i, // Scan Mode + input sys_osc_cal_i, // System Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_sys_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic clk_src_sys_o, // System Source Clock + output logic clk_src_sys_val_o // System Source Clock Valid +); + +logic clk, osc_en, sys_clk_en; + +assign osc_en = (clk_src_sys_en_i && clk_sys_pd_ni && rst_sys_clk_ni); +assign sys_clk_en = scan_mode_i || osc_en; + +// Clock Oscilator +/////////////////////////////////////// +sys_osc u_sys_osc ( + .vcore_pok_h_i ( vcore_pok_h_i ), + .sys_en_i ( sys_clk_en ), + .sys_jen_i ( clk_src_sys_jen_i ), + .sys_osc_cal_i ( sys_osc_cal_i ), +`ifdef AST_BYPASS_CLK + .clk_sys_ext_i ( clk_sys_ext_i ), +`endif + .sys_clk_o ( clk ) +); // of u_sys_osc + +// Clock & Valid +/////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_sys_buf( + .clk_i ( clk ), + .clk_o ( clk_src_sys_o ) +); + +// 2-stage de-assertion +logic rst_val_n; +assign rst_val_n = sys_clk_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_val_sync ( + .clk_i ( clk_src_sys_o ), + .rst_ni ( rst_val_n ), + .d_i ( 1'b1 ), + .q_o ( clk_src_sys_val_o ) +); + +endmodule : sys_clk diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/sys_osc.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/sys_osc.sv new file mode 100644 index 00000000000..3a3db36c7ea --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/sys_osc.sv @@ -0,0 +1,158 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: sys_osc +// *Module Description: System Clock Oscilator +//############################################################################ + +module sys_osc ( + input vcore_pok_h_i, // VCORE POK @3.3V + input sys_en_i, // System Source Clock Enable + input sys_jen_i, // System Source Clock Jitter Enable + input sys_osc_cal_i, // System Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_sys_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic sys_clk_o // System Clock Output +); + +`ifndef AST_BYPASS_CLK +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +timeunit 1ns / 1ps; + +real CLK_PERIOD; + +reg init_start; +initial init_start = 1'b0; +logic cal_sys_clk_70mhz = 1'b0; +logic [16-1:0] jrate, jrate_cnt; + +initial begin + jrate = 16'(1 << $urandom_range(7, 0)) - 1'b1; + void'($value$plusargs("cal_sys_clk_70mhz=%0b", cal_sys_clk_70mhz)); + #1; + init_start = 1'b1; + #1; + $display("\n%m: System Clock Power-up Frequency: %0d Hz", $rtoi(10**9/CLK_PERIOD)); +end + +// Enable 5us RC Delay on rise +wire en_osc_re_buf, en_osc_re, sys_jen; +buf #(ast_bhv_pkg::SYS_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && sys_en_i)); +assign en_osc_re = en_osc_re_buf && init_start; +assign sys_jen = sys_jen_i && en_osc_re_buf && init_start; + +// Clock Oscillator +//////////////////////////////////////// +real CalSysClkPeriod, UncSysClkPeriod, SysClkPeriod, jitter; + +initial CalSysClkPeriod = cal_sys_clk_70mhz ? $itor( 14286 ) : // 14286ps (70MHz) + $itor( 10000 ); // 10000ps (100MHz) + +initial UncSysClkPeriod = $itor( $urandom_range(40000, 16667) ); // 40000-16667ps (25-60MHz) + +assign SysClkPeriod = (sys_osc_cal_i && init_start) ? CalSysClkPeriod : UncSysClkPeriod; + +logic clk; + +// -20% Jitter on calibrated frequency +always_ff (* xprop_off *) @( posedge clk, negedge vcore_pok_h_i ) begin + if ( !vcore_pok_h_i ) begin + jitter <= 0.0; + jrate_cnt <= '0; + end else if ( !sys_jen ) begin + jrate_cnt <= '0; + jitter <= 0.0; + end else if ( jrate_cnt == '0 ) begin + jrate_cnt <= jrate; + jitter <= cal_sys_clk_70mhz ? $itor($urandom_range(3571, 0)) : // 56MHz - 70MHz + $itor($urandom_range(2500, 0)); // 80MHz - 100MHz + end else if ( jrate_cnt > '0 ) begin + jrate_cnt <= jrate_cnt - 1'b1; + end +end + +assign CLK_PERIOD = (SysClkPeriod + jitter)/1000; + +// Free running oscillator +reg clk_osc; +initial clk_osc = 1'b1; + +always begin + #(CLK_PERIOD/2) clk_osc = ~clk_osc; +end + +logic en_osc; + +// HDL Clock Gate +logic en_clk; + +always_latch begin + if ( !clk_osc ) en_clk = en_osc; +end + +assign clk = clk_osc && en_clk; +`else // of SYNTHESIS +// SYNTHESIS/LINTER +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && sys_en_i; + +logic clk, en_osc; +assign clk = 1'b0; +`endif // of SYNTHESIS +`else // of AST_BYPASS_CLK +// VERILATOR/FPGA +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && sys_en_i; + +// Clock Oscillator +//////////////////////////////////////// +logic clk, en_osc; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1 ) +) u_clk_ckgt ( + .clk_i ( clk_sys_ext_i ), + .en_i ( en_osc ), + .test_en_i ( 1'b0 ), + .clk_o ( clk ) +); +`endif + +logic en_osc_fe; + +// Syncronize en_osc to clk FE for glitch free disable +always_ff @( negedge clk, negedge vcore_pok_h_i ) begin + if ( !vcore_pok_h_i ) begin + en_osc_fe <= 1'b0; + end else begin + en_osc_fe <= en_osc_re; + end +end + +assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0 + +// Clock Output Buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_buf ( + .clk_i ( clk ), + .clk_o ( sys_clk_o ) +); + + +`ifdef SYNTHESIS +///////////////////////// +// Unused Signals +///////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ sys_osc_cal_i, sys_jen_i }; +`endif + +endmodule : sys_osc diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/usb_clk.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/usb_clk.sv new file mode 100644 index 00000000000..e0aefb27fa4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/usb_clk.sv @@ -0,0 +1,143 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: usb_clk +// *Module Description: USB Clock +//############################################################################ + +module usb_clk ( + input vcore_pok_h_i, // VCORE POK @3.3V (for OSC) + input clk_usb_pd_ni, // USB Clock Power-down + input rst_usb_clk_ni, // USB Clock Logic reset + input clk_src_usb_en_i, // USB Source Clock Enable + input usb_ref_val_i, // USB Reference (Pulse) Valid + input usb_ref_pulse_i, // USB Reference Pulse + input clk_ast_usb_i, // USB Bufferd Clock + input rst_ast_usb_ni, // USB Bufferd Reset + input scan_mode_i, // Scan Mode + input usb_osc_cal_i, // USB Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_usb_ext_i, // FPGA/VERILATOR Clock input +`endif + // + output logic clk_src_usb_o, // USB Source Clock + output logic clk_src_usb_val_o // USB Source Clock Valid +); + +logic clk, osc_en, usb_clk_en; + +assign osc_en = (clk_src_usb_en_i && clk_usb_pd_ni && rst_usb_clk_ni); +assign usb_clk_en = scan_mode_i || osc_en; + +logic rst_da_n, rst_n; + +// 2-stage de-assertion +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_da ( + .clk_i ( clk_src_usb_o ), + .rst_ni ( rst_usb_clk_ni ), + .d_i ( 1'b1 ), + .q_o ( rst_da_n ) +); + +assign rst_n = scan_mode_i ? rst_ast_usb_ni : rst_da_n; + + +/////////////////////////////////////// +// Clock Calibrate & Drift Adjusment +/////////////////////////////////////// + +// Reference Pulse Detect +/////////////////////////////////////// +logic ref_pulse_in, ref_pulse_re, src_pulse_en, src_busy; + +assign ref_pulse_in = usb_ref_pulse_i && usb_ref_val_i; + +ast_pulse_sync u_ref_pulse_sync ( + .scan_mode_i ( scan_mode_i ), + // source clock domain + .clk_src_i ( clk_ast_usb_i ), + .rst_src_ni ( rst_ast_usb_ni ), + .src_pulse_i ( ref_pulse_in ), + .src_pulse_en_o ( src_pulse_en ), + .src_busy_o ( src_busy ), + // destination clock domain + .clk_dst_i ( clk ), + .rst_dst_ni ( rst_n ), + .dst_pulse_o ( ref_pulse_re ) +); + +// Clock Oscilator +/////////////////////////////////////// +// 2-stage de-assertion +logic rst_usb_n; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_rst_ast_usb_da ( + .clk_i ( clk ), + .rst_ni ( rst_ast_usb_ni ), + .d_i ( 1'b1 ), + .q_o ( rst_usb_n ) +); + +// Sync usb_ref_val_i to clk +logic usb_ref_val; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_ref_val_sync ( + .clk_i ( clk ), + .rst_ni ( rst_usb_n ), + .d_i ( usb_ref_val_i ), + .q_o ( usb_ref_val ) +); + +usb_osc u_usb_osc ( + .vcore_pok_h_i ( vcore_pok_h_i ), + .usb_en_i (usb_clk_en ), + .usb_ref_pulse_i ( ref_pulse_re ), + .usb_ref_val_i ( usb_ref_val ), + .usb_osc_cal_i ( usb_osc_cal_i ), +`ifdef AST_BYPASS_CLK + .clk_usb_ext_i ( clk_usb_ext_i ), +`endif + .usb_clk_o ( clk ) +); // u_usb_osc + +// Clock & Valid +/////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_clk_usb_buf( + .clk_i ( clk ), + .clk_o ( clk_src_usb_o ) +); + +// 2-stage de-assertion +logic rst_val_n; +assign rst_val_n = usb_clk_en; + +prim_flop_2sync #( + .Width ( 1 ), + .ResetValue ( 1'b0 ) +) u_no_scan_val_sync ( + .clk_i ( clk_src_usb_o ), + .rst_ni ( rst_val_n ), + .d_i ( 1'b1 ), + .q_o ( clk_src_usb_val_o ) +); + + +///////////////////////// +// Unused Signals +///////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ src_pulse_en, src_busy }; + +endmodule : usb_clk diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/usb_osc.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/usb_osc.sv new file mode 100644 index 00000000000..707bba5d258 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/usb_osc.sv @@ -0,0 +1,183 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: usb_osc +// *Module Description: USB Clock Oscilator +//############################################################################ + +module usb_osc ( + input vcore_pok_h_i, // VCORE POK @3.3V + input usb_en_i, // USB Source Clock Enable + input usb_ref_pulse_i, // USB Reference Pulse + input usb_ref_val_i, // USB Reference Valid + input usb_osc_cal_i, // USB Oscillator Calibrated +`ifdef AST_BYPASS_CLK + input clk_usb_ext_i, // FPGA/VERILATOR Clock input +`endif + output logic usb_clk_o // USB Clock Output +); + +`ifndef AST_BYPASS_CLK +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +timeunit 1ns / 1ps; + +real CLK_PERIOD; +integer beacon_rdly; +bit calibrate_usb_clk, max_drift; +localparam int MAXUSBDRIFT = 416; // 416 is +/-2% of 48MHz; 694 is +/-3% of 48MHz +integer usb_clk_drift; + +reg init_start; +initial init_start = 1'b0; + +initial begin + // With this flag activated, +calibrate_usb_clk=0. the USB clock will be calibrated + // as-soon-as the 'ast_init_done_o' gets active (using '=1' will delay by 1 ns). + // + // | <- BEACON_RDLY in ns -> | + // < un-calibrated clock >< calibrated+drift >< calibrated > + // _______________________/``````````````````````````````````````````````````` ast_init_done_o + // + if ( !$value$plusargs("calibrate_usb_clk=%0d", beacon_rdly) ) begin + beacon_rdly = 0; + calibrate_usb_clk = 1'b0; + end else begin + calibrate_usb_clk = 1'b1; + end + // Max USB drift is: +/-2% + if ( !$value$plusargs("usb_max_drift=%0b", max_drift) ) begin + max_drift = 1'b0; + end + // + #1; + init_start = 1'b1; + #1; + $display("\n%m: USB Clock Power-up Frequency: %0d Hz", $rtoi(10**9/CLK_PERIOD)); + usb_clk_drift = max_drift ? ($urandom_range(0, 1) ? MAXUSBDRIFT : -MAXUSBDRIFT) : // +2% or -2% + ($urandom_range(0, 2*MAXUSBDRIFT) - MAXUSBDRIFT); // Up to +/-2% + $display("%m: USB Clock Drift: %0d ps", usb_clk_drift); +end + +// Enable 5us RC Delay on rise +wire en_osc_re_buf, en_osc_re; +buf #(ast_bhv_pkg::USB_EN_RDLY, 0) b0 (en_osc_re_buf, (vcore_pok_h_i && usb_en_i)); +assign en_osc_re = en_osc_re_buf && init_start; + +logic usb_ref_val_buf, zero_drift; + +buf #(ast_bhv_pkg::USB_VAL_RDLY, ast_bhv_pkg::USB_VAL_FDLY) b1 + (usb_ref_val_buf, (vcore_pok_h_i && usb_ref_val_i)); + +buf #(beacon_rdly, 0) b2 (usb_beacon_on_buf, (usb_osc_cal_i && calibrate_usb_clk)); + +assign zero_drift = (usb_ref_val_buf && calibrate_usb_clk || usb_beacon_on_buf) && init_start; + +logic [4-1:0] ref_pulse_cnt_down; + +always_ff @( posedge usb_clk_o, negedge usb_ref_val_i ) begin + if ( !usb_ref_val_i ) begin + ref_pulse_cnt_down <= ast_reg_pkg::NumUsbBeaconPulses[4-1:0]; + end else if ( (ref_pulse_cnt_down > 4'h0) && usb_ref_pulse_i ) begin + ref_pulse_cnt_down <= ref_pulse_cnt_down - 1'b1; + end +end + +// Clock Oscillator +//////////////////////////////////////// +real CalUsbClkPeriod, UncUsbClkPeriod, UsbClkPeriod, drift; + +initial CalUsbClkPeriod = $itor( 1000000/48 ); // ~20833.33333ps (48MHz) +initial UncUsbClkPeriod = $itor( $urandom_range(55555, 25000) ); // 55555-25000ps (18-40MHz) + +real adj_drift; +assign adj_drift = $itor(usb_clk_drift) * $itor(ref_pulse_cnt_down) / + $itor(ast_reg_pkg::NumUsbBeaconPulses[4-1:0]); + +assign drift = zero_drift ? 0.0 : adj_drift; + +assign UsbClkPeriod = (usb_osc_cal_i && init_start) ? CalUsbClkPeriod : + UncUsbClkPeriod; +assign CLK_PERIOD = (UsbClkPeriod + drift)/1000; + +// Free running oscillator +reg clk_osc; +initial clk_osc = 1'b1; + +always begin + #(CLK_PERIOD/2) clk_osc = ~clk_osc; +end + +logic en_osc; + +// HDL Clock Gate +logic en_clk, clk; + +always_latch begin + if ( !clk_osc ) en_clk = en_osc; +end + +assign clk = clk_osc && en_clk; +`else // of SYNTHESIS +// SYNTHESIS/LINTER +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && usb_en_i; + +logic clk, en_osc; +assign clk = 1'b0; +`endif // of SYNTHESIS +`else // of AST_BYPASS_CLK +// VERILATOR/FPGA +/////////////////////////////////////// +logic en_osc_re; +assign en_osc_re = vcore_pok_h_i && usb_en_i; + +// Clock Oscillator +//////////////////////////////////////// +logic clk, en_osc; + +prim_clock_gating #( + .NoFpgaGate ( 1'b1 ) +) u_clk_ckgt ( + .clk_i ( clk_usb_ext_i ), + .en_i ( en_osc ), + .test_en_i ( 1'b0 ), + .clk_o ( clk ) +); +`endif + +logic en_osc_fe; + +// Syncronize en_osc to clk FE for glitch free disable +always_ff @( negedge clk, negedge vcore_pok_h_i ) begin + if ( !vcore_pok_h_i ) begin + en_osc_fe <= 1'b0; + end else begin + en_osc_fe <= en_osc_re; + end +end + +assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0 + +// Clock Output Buffer +//////////////////////////////////////// +prim_clock_buf #( + .NoFpgaBuf ( 1'b1 ) +) u_buf ( + .clk_i ( clk ), + .clk_o ( usb_clk_o ) +); + + +`ifdef SYNTHESIS +/////////////////////// +// Unused Signals +/////////////////////// +logic unused_sigs; +assign unused_sigs = ^{ usb_osc_cal_i, usb_ref_pulse_i, usb_ref_val_i }; +`endif + +endmodule : usb_osc diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/vcaon_pgd.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/vcaon_pgd.sv new file mode 100644 index 00000000000..e325fb44664 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/vcaon_pgd.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: vcaon_pgd +// *Module Description: VCAON Power Good +//############################################################################ +`ifdef SYNTHESIS +`ifndef PRIM_DEFAULT_IMPL +`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric +`endif +`endif + +module vcaon_pgd ( + output logic vcaon_pok_o +); + +// Local signal for testing hook +logic gen_supp_a; +assign gen_supp_a = 1'b1; + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +// The initial is needed to clear the X of the delays at the start +// Also to force a power-up effect at the bgining. +logic init_start; + +initial begin + init_start = 1'b1; #1; + init_start = 1'b0; +end + +always @( * ) begin + if ( init_start ) begin + vcaon_pok_o <= 1'b0; + end else if ( !init_start && gen_supp_a ) begin + vcaon_pok_o <= #(ast_bhv_pkg::VCAON_POK_RDLY) gen_supp_a; + end else if ( !init_start && !gen_supp_a ) begin + vcaon_pok_o <= #(ast_bhv_pkg::VCAON_POK_FDLY) gen_supp_a; + end +end +`else +// SYNTHESIS/VERILATOR/LINTER/FPGA +/////////////////////////////////////// +localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; + +if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx + // FPGA Specific (place holder) + /////////////////////////////////////// + assign vcaon_pok_o = gen_supp_a; +end else begin : gen_generic + assign vcaon_pok_o = gen_supp_a; +end +`endif + +endmodule : vcaon_pgd diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/vcc_pgd.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/vcc_pgd.sv new file mode 100644 index 00000000000..f66c4b41304 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/vcc_pgd.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: vcc_pgd +// *Module Description: VCC Power Good +//############################################################################ +`ifdef SYNTHESIS +`ifndef PRIM_DEFAULT_IMPL +`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric +`endif +`endif + +module vcc_pgd ( + output logic vcc_pok_o +); + +// Local signal for testing hook +logic gen_supp_a; +assign gen_supp_a = 1'b1; + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +// The initial is needed to clear the X of the delays at the start +// Also to force a power-up effect at the bgining. +logic init_start; + +initial begin + init_start = 1'b1; #1; + init_start = 1'b0; +end + +always (* xprop_off *) @( * ) begin + if ( init_start ) begin + vcc_pok_o <= 1'b0; + end + if ( !init_start && gen_supp_a ) begin + vcc_pok_o <= #(ast_bhv_pkg::VCC_POK_RDLY) gen_supp_a; + end + if ( !init_start && !gen_supp_a ) begin + vcc_pok_o <= #(ast_bhv_pkg::VCC_POK_FDLY) gen_supp_a; + end +end +`else +// SYNTHESIS/VERILATOR/LINTER/FPGA +/////////////////////////////////////// +localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; + +if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx + // FPGA Specific (place holder) + /////////////////////////////////////// + assign vcc_pok_o = gen_supp_a; +end else begin : gen_generic + assign vcc_pok_o = gen_supp_a; +end +`endif + +endmodule : vcc_pgd diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/vcmain_pgd.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/vcmain_pgd.sv new file mode 100644 index 00000000000..cf73b5fc627 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/vcmain_pgd.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: vcmain_pgd +// *Module Description: VCMAIN Power Good +//############################################################################ +`ifdef SYNTHESIS +`ifndef PRIM_DEFAULT_IMPL +`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric +`endif +`endif + +module vcmain_pgd ( + output logic vcmain_pok_o +); + +// Local signal for testing hook +logic gen_supp_a; +assign gen_supp_a = 1'b1; + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +// The initial is needed to clear the X of the delays at the start +// Also to force a power-up effect at the bgining. +logic init_start; + +initial begin + init_start = 1'b1; #1; + init_start = 1'b0; +end + +always @( * ) begin + if ( init_start ) begin + vcmain_pok_o <= 1'b0; + end else if ( !init_start && gen_supp_a ) begin + vcmain_pok_o <= #(ast_bhv_pkg::VCMAIN_POK_RDLY) gen_supp_a; + end else if ( !init_start && !gen_supp_a ) begin + vcmain_pok_o <= #(ast_bhv_pkg::VCMAIN_POK_FDLY) gen_supp_a; + end +end +`else +// SYNTHESIS/VERILATOR/LINTER/FPGA +/////////////////////////////////////// +localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; + +if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx + // FPGA Specific (place holder) + /////////////////////////////////////// + assign vcmain_pok_o = gen_supp_a; +end else begin : gen_generic + assign vcmain_pok_o = gen_supp_a; +end +`endif + +endmodule : vcmain_pgd diff --git a/hw/top_darjeeling_no_ibex/ip/ast/rtl/vio_pgd.sv b/hw/top_darjeeling_no_ibex/ip/ast/rtl/vio_pgd.sv new file mode 100644 index 00000000000..96c353f3e6a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/ast/rtl/vio_pgd.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +//############################################################################ +// *Name: vio_pgd +// *Module Description: VIO Power Good +//############################################################################ +`ifdef SYNTHESIS +`ifndef PRIM_DEFAULT_IMPL +`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric +`endif +`endif + +module vio_pgd ( + output logic vio_pok_o +); + +// Local signal for testing hook +logic gen_supp_a; +assign gen_supp_a = 1'b1; + +`ifndef SYNTHESIS +// Behavioral Model +//////////////////////////////////////// +// The initial is needed to clear the X of the delays at the start +// Also to force a power-up effect at the bgining. +logic init_start; + +initial begin + init_start = 1'b1; #1; + init_start = 1'b0; +end + +always (* xprop_off *) @( * ) begin + if ( init_start ) begin + vio_pok_o <= 1'b0; + end + if ( !init_start && gen_supp_a ) begin + vio_pok_o <= #(ast_bhv_pkg::VIO_POK_RDLY) gen_supp_a; + end + if ( !init_start && !gen_supp_a ) begin + vio_pok_o <= #(ast_bhv_pkg::VIO_POK_FDLY) gen_supp_a; + end +end +`else +// SYNTHESIS/VERILATOR/LINTER/FPGA +////////////////////////////////////// +localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL; + +if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx + // FPGA Specific (place holder) + /////////////////////////////////////// + assign vio_pok_o = gen_supp_a; +end else begin : gen_generic + assign vio_pok_o = gen_supp_a; +end +`endif + +endmodule : vio_pgd diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/BUILD b/hw/top_darjeeling_no_ibex/ip/soc_proxy/BUILD new file mode 100644 index 00000000000..9c1f68de888 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/BUILD @@ -0,0 +1,17 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]) + [ + "//hw/top_darjeeling/ip/soc_proxy/data:all_files", + ], +) + +filegroup( + name = "doc_files", + srcs = glob(["**/*.md"]), +) diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/README.md b/hw/top_darjeeling_no_ibex/ip/soc_proxy/README.md new file mode 100644 index 00000000000..d63dcf020fb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/README.md @@ -0,0 +1,31 @@ +# SoC Proxy Technical Specification + +SoC Proxy is a simple comportable IP module that facilitates the breakout of signals and buses internal to OpenTitan (similar to Sensor Control for AST). + +## Comportable Interfaces + +- Clock / reset (intended for connection to the fast clock domain) +- 1 TL-UL Device port for comportable CSR node +- 1 TL-UL Device port with an address range to egress into CTN +- 1 Fatal alert for bus integrity +- 24 Fatal external alert channels +- 4 Recoverable external alert channels +- 2 Wakeup requests + - Internal wakeup request, should be asserted whenever an external alert or IRQ is seen + - External wakeup request +- 32 Interrupts + - External interrupt requests + +## SoC-facing interfaces + +- Synchronous interfaces: + - 1 TL-UL Host port for egress into CTN + - 24 fatal alert and 4 recoverable alert differential input signals + - Status of each alert can be read and acknowledged via CSRs + - Optional acknowledgment signals (as in Sensor Control) + - The main difference with respect to Sensor Control is that each alert is sent out via its own alert channel instead of aggregating, since that way the alert crash dump latched in Reset Manager provides more info than if the alerts were aggregated. +- Asynchronous interfaces: + - 1 Wakeup request, asynchronous and level-encoded + - 32 Interrupts, asynchronous and level-encoded + - 16 general-purpose inputs + - 16 general-purpose outputs diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/data/BUILD b/hw/top_darjeeling_no_ibex/ip/soc_proxy/data/BUILD new file mode 100644 index 00000000000..dda56de039e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/data/BUILD @@ -0,0 +1,10 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/data/soc_proxy.hjson b/hw/top_darjeeling_no_ibex/ip/soc_proxy/data/soc_proxy.hjson new file mode 100644 index 00000000000..b2056aa45d6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/data/soc_proxy.hjson @@ -0,0 +1,322 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +{ + name: "soc_proxy" + human_name: "SoC Proxy" + one_line_desc: "Facilitates the breakout of signals and buses internal to OpenTitan" + cip_id: "38" // unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool + design_spec: "../doc" + dv_doc: "../doc/dv" + hw_checklist: "../doc/checklist" + sw_checklist: "/sw/ip/soc_proxy/dif/dif_soc_proxy" + + param_list: [ + { name: "NumExternalIrqs" + type: "int unsigned" + default: "32" + desc: "Number of external interrupt requests" + local: "true" + } + ] + + revisions: [ + { + version: "1.0.0" + life_stage: "L1" + design_stage: "D0" + verification_stage: "N/A" // block-level verification not planned + notes: "Verified at the top-level." + } + ] + + clocking: [ + { clock: "clk_i", reset: "rst_ni", primary: true } + { clock: "clk_aon_i", reset: "rst_por_ni" } + ] + + bus_interfaces: [ + { protocol: "tlul", direction: "device", name: "core" } + { protocol: "tlul", direction: "device", name: "ctn" } + ] + + available_input_list: [ + { name: "soc_gpi", width: 16, desc: "soc general purpose input" } + ], + available_output_list: [ + { name: "soc_gpo", width: 16, desc: "soc general purpose output" } + ], + + alert_list: [ + { name: "fatal_alert_intg" + desc: "Fatal bus integrity alert" + } + { name: "fatal_alert_external_0" + desc: "Fatal external alert channel 0" + } + { name: "fatal_alert_external_1" + desc: "Fatal external alert channel 1" + } + { name: "fatal_alert_external_2" + desc: "Fatal external alert channel 2" + } + { name: "fatal_alert_external_3" + desc: "Fatal external alert channel 3" + } + { name: "fatal_alert_external_4" + desc: "Fatal external alert channel 4" + } + { name: "fatal_alert_external_5" + desc: "Fatal external alert channel 5" + } + { name: "fatal_alert_external_6" + desc: "Fatal external alert channel 6" + } + { name: "fatal_alert_external_7" + desc: "Fatal external alert channel 7" + } + { name: "fatal_alert_external_8" + desc: "Fatal external alert channel 8" + } + { name: "fatal_alert_external_9" + desc: "Fatal external alert channel 9" + } + { name: "fatal_alert_external_10" + desc: "Fatal external alert channel 10" + } + { name: "fatal_alert_external_11" + desc: "Fatal external alert channel 11" + } + { name: "fatal_alert_external_12" + desc: "Fatal external alert channel 12" + } + { name: "fatal_alert_external_13" + desc: "Fatal external alert channel 13" + } + { name: "fatal_alert_external_14" + desc: "Fatal external alert channel 14" + } + { name: "fatal_alert_external_15" + desc: "Fatal external alert channel 15" + } + { name: "fatal_alert_external_16" + desc: "Fatal external alert channel 16" + } + { name: "fatal_alert_external_17" + desc: "Fatal external alert channel 17" + } + { name: "fatal_alert_external_18" + desc: "Fatal external alert channel 18" + } + { name: "fatal_alert_external_19" + desc: "Fatal external alert channel 19" + } + { name: "fatal_alert_external_20" + desc: "Fatal external alert channel 20" + } + { name: "fatal_alert_external_21" + desc: "Fatal external alert channel 21" + } + { name: "fatal_alert_external_22" + desc: "Fatal external alert channel 22" + } + { name: "fatal_alert_external_23" + desc: "Fatal external alert channel 23" + } + { name: "recov_alert_external_0" + desc: "Recoverable external alert channel 0" + } + { name: "recov_alert_external_1" + desc: "Recoverable external alert channel 1" + } + { name: "recov_alert_external_2" + desc: "Recoverable external alert channel 2" + } + { name: "recov_alert_external_3" + desc: "Recoverable external alert channel 3" + } + ] + + wakeup_list: [ + { name: "wkup_internal_req" + desc: "Internal wakeup request, should be asserted whenever an external alert or IRQ is seen" + } + { name: "wkup_external_req" + desc: "External wakeup request" + } + ] + + interrupt_list: [ + { name: "external" + desc: "External interrupt request" + width: 32 // keep equal to `NumExternalIrqs` + } + ] + + reset_request_list: [ + { name: "rst_req_external" + desc: "External reset request" + } + ] + + inter_signal_list: [ + { struct: "tl_h2d" + package: "tlul_pkg" + type: "uni" + name: "dma_tl_h2d" + act: "rcv" + desc: "TL-UL host port for the DMA to egress into CTN (request part), synchronous" + } + { struct: "tl_d2h" + package: "tlul_pkg" + type: "uni" + name: "dma_tl_d2h" + act: "req" + desc: "TL-UL host port for the DMA to egress into CTN (response part), synchronous" + } + { struct: "tl_h2d" + package: "tlul_pkg" + type: "uni" + name: "misc_tl_h2d" + act: "rcv" + desc: "TL-UL host port for the MISC to egress into CTN (request part), synchronous" + } + { struct: "tl_d2h" + package: "tlul_pkg" + type: "uni" + name: "misc_tl_d2h" + act: "req" + desc: "TL-UL host port for the MISC to egress into CTN (response part), synchronous" + } + + { struct: "logic" + type: "uni" + name: "wkup_internal_req" + act: "req" + } + { struct: "logic" + type: "uni" + name: "wkup_external_req" + act: "req" + } + { struct: "logic" + type: "uni" + name: "rst_req_external" + act: "req" + } + { struct: "tl_h2d" + package: "tlul_pkg" + type: "uni" + name: "ctn_tl_h2d" + act: "req" + desc: "TL-UL host port for egress into CTN (request part), synchronous" + } + { struct: "tl_d2h" + package: "tlul_pkg" + type: "uni" + name: "ctn_tl_d2h" + act: "rcv" + desc: "TL-UL host port for egress into CTN (response part), synchronous" + } + { struct: "logic" + type: "uni" + name: "i2c_lsio_trigger" + act: "rcv" + desc: "LSIO trigger signal from I2C" + } + { struct: "logic" + type: "uni" + name: "spi_host_lsio_trigger" + act: "rcv" + desc: "LSIO trigger signal from SPI Host" + } + { struct: "logic" + type: "uni" + name: "uart_lsio_trigger" + act: "rcv" + desc: "LSIO trigger signal from UART" + } + { struct: "logic" + width: 8 + type: "uni" + name: "soc_lsio_trigger" + act: "rcv" + desc: "LSIO trigger signal from SoC, synchronous" + } + { struct: "lsio_trigger" + package: "dma_pkg" + type: "uni" + name: "dma_lsio_trigger" + act: "req" + desc: "Collated synchronous LSIO trigger signals for DMA" + } + { struct: "soc_alert" + package: "soc_proxy_pkg" + type: "req_rsp" + name: "soc_fatal_alert" + act: "rsp" + desc: "Differential fatal alert from SoC, synchronous" + width: 24 + } + { struct: "soc_alert" + package: "soc_proxy_pkg" + type: "req_rsp" + name: "soc_recov_alert" + act: "rsp" + desc: "Differential recoverable alert from SoC, synchronous" + width: 4 + } + { struct: "logic" + type: "uni" + name: "soc_wkup_async" + act: "rcv" + desc: "Wakeup request from SoC, asynchronous, level-encoded" + } + { struct: "logic" + type: "uni" + name: "soc_rst_req_async" + act: "rcv" + desc: "Reset request from SoC, asynchronous, level-encoded" + } + { struct: "logic" + type: "uni" + name: "soc_intr_async" + act: "rcv" + width: 32 // keep equal to `NumExternalIrqs` + desc: "Interrupt request from SoC, asynchronous, level-encoded" + } + { struct: "logic" + type: "uni" + name: "soc_gpi_async" + act: "req" + width: 16 // keep equal to `NumSocGpio` + desc: "GPI from SoC, async" + } + { struct: "logic" + type: "uni" + name: "soc_gpo_async" + act: "rcv" + width: 16 // keep equal to `NumSocGpio` + desc: "GPO from SoC, async" + } + { struct: "logic" + width: 4 + type: "uni" + name: "integrator_id" + act: "rcv" + desc: "Integrator ID signal used in BAT" + } + ] + + regwidth: "32" + + registers: { + core: [ + // no CSRs defined yet + ] + ctn: [ + // no CSRs defined here + ] + } +} diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/defs.bzl b/hw/top_darjeeling_no_ibex/ip/soc_proxy/defs.bzl new file mode 100644 index 00000000000..c2184864599 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/defs.bzl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +SOC_PROXY = opentitan_ip( + name = "soc_proxy", + hjson = "//hw/top_darjeeling/ip/soc_proxy/data:soc_proxy.hjson", +) diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/lint/soc_proxy.vlt b/hw/top_darjeeling_no_ibex/ip/soc_proxy/lint/soc_proxy.vlt new file mode 100644 index 00000000000..bd14ffc12a3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/lint/soc_proxy.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for soc_proxy diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/lint/soc_proxy.waiver b/hw/top_darjeeling_no_ibex/ip/soc_proxy/lint/soc_proxy.waiver new file mode 100644 index 00000000000..ae971a65290 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/lint/soc_proxy.waiver @@ -0,0 +1,5 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for soc_proxy diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/bat.sv b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/bat.sv new file mode 100644 index 00000000000..b153f164c15 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/bat.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module bat ( + // Input port + input tlul_pkg::tl_h2d_t tl_in_h2d_i, + output tlul_pkg::tl_d2h_t tl_in_d2h_o, + + // Integrator bits used for custom BAT + input logic [3:0] integrator_id_i, + + // Translated output port + output tlul_pkg::tl_h2d_t tl_out_h2d_o, + input tlul_pkg::tl_d2h_t tl_out_d2h_i +); + + // A valid request in the range [1G,2G) or a broadcast request is considered to be valid + logic ctn_request; + assign ctn_request = tl_in_h2d_i.a_valid & (tl_in_h2d_i.a_address[31:30] == 2'b01); + + logic [top_pkg::TL_AW-1:0] bat_address; + logic [1:0] addr_msbs; + assign addr_msbs = tl_in_h2d_i.a_address[31:30]; + + // If there is a valid CTN request, perform the BAT (downlift to 0-1GB), + // else use the original address + assign bat_address = {ctn_request ? 2'b0 : addr_msbs, tl_in_h2d_i.a_address[29:0]}; + + // Assemble the new TLUL request with the BAT'ed address + tlul_pkg::tl_h2d_t tl_out_h2d_pre; + assign tl_out_h2d_pre = '{ + a_valid: tl_in_h2d_i.a_valid, + a_opcode: tl_in_h2d_i.a_opcode, + a_size: tl_in_h2d_i.a_size, + a_source: tl_in_h2d_i.a_source, + a_address: bat_address, + a_mask: tl_in_h2d_i.a_mask, + a_user: tl_in_h2d_i.a_user, + a_data: tl_in_h2d_i.a_data, + a_param: tl_in_h2d_i.a_param, + d_ready: tl_in_h2d_i.d_ready + }; + + // Regenerate integrity values after address change + tlul_cmd_intg_gen u_cmd_intg_gen ( + .tl_i(tl_out_h2d_pre), + .tl_o(tl_out_h2d_o) + ); + + // Feed back the response port + assign tl_in_d2h_o = tl_out_d2h_i; + + // Integrator ID is unused in the open-source BAT + logic unused_signals; + assign unused_signals = ^integrator_id_i; +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy.sv b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy.sv new file mode 100644 index 00000000000..452fe25d8ff --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy.sv @@ -0,0 +1,519 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// SoC Proxy + +`include "prim_assert.sv" + +module soc_proxy + import soc_proxy_reg_pkg::*; + import soc_proxy_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert signal + parameter int unsigned AlertSkewCycles = 1 +) ( + input logic clk_i, + input logic rst_ni, + input logic clk_aon_i, + input logic rst_por_ni, + + input tlul_pkg::tl_h2d_t core_tl_i, + output tlul_pkg::tl_d2h_t core_tl_o, + + input tlul_pkg::tl_h2d_t ctn_tl_i, + output tlul_pkg::tl_d2h_t ctn_tl_o, + + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + output logic [NumExternalIrqs-1:0] intr_external_o, + + output logic wkup_internal_req_o, + output logic wkup_external_req_o, + + output logic rst_req_external_o, + + // Integrator bits used for custom BAT + input logic [3:0] integrator_id_i, + + input [NumSocGpio-1:0] cio_soc_gpi_i, + output logic [NumSocGpio-1:0] cio_soc_gpo_o, + output logic [NumSocGpio-1:0] cio_soc_gpo_en_o, + + input logic i2c_lsio_trigger_i, + input logic spi_host_lsio_trigger_i, + input logic uart_lsio_trigger_i, + input logic [7:0] soc_lsio_trigger_i, + output dma_pkg::lsio_trigger_t dma_lsio_trigger_o, + + // Incomig TL ports get muxed + input tlul_pkg::tl_h2d_t dma_tl_h2d_i, + output tlul_pkg::tl_d2h_t dma_tl_d2h_o, + input tlul_pkg::tl_h2d_t misc_tl_h2d_i, + output tlul_pkg::tl_d2h_t misc_tl_d2h_o, + + output tlul_pkg::tl_h2d_t ctn_tl_h2d_o, + input tlul_pkg::tl_d2h_t ctn_tl_d2h_i, + + input soc_alert_req_t [NumFatalExternalAlerts-1:0] soc_fatal_alert_i, + output soc_alert_rsp_t [NumFatalExternalAlerts-1:0] soc_fatal_alert_o, + input soc_alert_req_t [NumRecovExternalAlerts-1:0] soc_recov_alert_i, + output soc_alert_rsp_t [NumRecovExternalAlerts-1:0] soc_recov_alert_o, + + input logic soc_wkup_async_i, + + input logic soc_rst_req_async_i, + + output logic [NumSocGpio-1:0] soc_gpi_async_o, + input logic [NumSocGpio-1:0] soc_gpo_async_i, + + input logic [NumExternalIrqs-1:0] soc_intr_async_i +); + localparam int unsigned TLUL_HOST_CNT = 3; + + // TLUL egress port muxing. First stage all incoming TLUL ports and them mux them + tlul_pkg::tl_h2d_t host_tl_h2d[TLUL_HOST_CNT]; + tlul_pkg::tl_d2h_t host_tl_d2h[TLUL_HOST_CNT]; + + assign host_tl_h2d [0] = ctn_tl_i; + assign ctn_tl_o = host_tl_d2h[0]; + + assign host_tl_h2d [1] = dma_tl_h2d_i; + assign dma_tl_d2h_o = host_tl_d2h[1]; + + assign host_tl_h2d [2] = misc_tl_h2d_i; + assign misc_tl_d2h_o = host_tl_d2h[2]; + + tlul_pkg::tl_h2d_t muxed_host_tl_h2d; + tlul_pkg::tl_d2h_t muxed_host_tl_d2h; + + // Add a MUX with a pipeline stage to shorten path through AC ranges + tlul_socket_m1 #( + .M ( TLUL_HOST_CNT ), + .HReqPass ( {TLUL_HOST_CNT{1'b1}} ), + .HRspPass ( {TLUL_HOST_CNT{1'b1}} ), + .HReqDepth ( {TLUL_HOST_CNT{4'd2}} ), + .HRspDepth ( {TLUL_HOST_CNT{4'd2}} ), + .DReqPass ( 0 ), + .DRspPass ( 0 ), + .DReqDepth ( 4'd4 ), + .DRspDepth ( 4'd4 ) + ) u_ctn_egress_mux ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .tl_h_i ( host_tl_h2d ), + .tl_h_o ( host_tl_d2h ), + .tl_d_o ( muxed_host_tl_h2d ), + .tl_d_i ( muxed_host_tl_d2h ) + ); + + // Perform the base address translation before exiting to the AC Ranges + bat u_bat ( + .tl_in_h2d_i ( muxed_host_tl_h2d ), + .tl_in_d2h_o ( muxed_host_tl_d2h ), + .integrator_id_i ( integrator_id_i ), + .tl_out_h2d_o ( ctn_tl_h2d_o ), + .tl_out_d2h_i ( ctn_tl_d2h_i ) + ); + + // GPI/O signal feed through. + assign soc_gpi_async_o = cio_soc_gpi_i; + assign cio_soc_gpo_en_o = {NumSocGpio{1'b1}}; + assign cio_soc_gpo_o = soc_gpo_async_i; + + // Register node + soc_proxy_core_reg2hw_t reg2hw; + soc_proxy_core_hw2reg_t hw2reg; + logic reg_top_intg_err; + soc_proxy_core_reg_top u_reg ( + .clk_i, + .rst_ni, + .tl_i (core_tl_i), + .tl_o (core_tl_o), + .reg2hw, + .hw2reg, + .intg_err_o (reg_top_intg_err) + ); + + // Alert test + logic [NumAlerts-1:0] alert_test; + assign alert_test[FatalAlertIntg] = reg2hw.alert_test.fatal_alert_intg.qe & + reg2hw.alert_test.fatal_alert_intg.q; + assign alert_test[FatalAlertExternal0] = reg2hw.alert_test.fatal_alert_external_0.qe & + reg2hw.alert_test.fatal_alert_external_0.q; + assign alert_test[FatalAlertExternal1] = reg2hw.alert_test.fatal_alert_external_1.qe & + reg2hw.alert_test.fatal_alert_external_1.q; + assign alert_test[FatalAlertExternal2] = reg2hw.alert_test.fatal_alert_external_2.qe & + reg2hw.alert_test.fatal_alert_external_2.q; + assign alert_test[FatalAlertExternal3] = reg2hw.alert_test.fatal_alert_external_3.qe & + reg2hw.alert_test.fatal_alert_external_3.q; + assign alert_test[FatalAlertExternal4] = reg2hw.alert_test.fatal_alert_external_4.qe & + reg2hw.alert_test.fatal_alert_external_4.q; + assign alert_test[FatalAlertExternal5] = reg2hw.alert_test.fatal_alert_external_5.qe & + reg2hw.alert_test.fatal_alert_external_5.q; + assign alert_test[FatalAlertExternal6] = reg2hw.alert_test.fatal_alert_external_6.qe & + reg2hw.alert_test.fatal_alert_external_6.q; + assign alert_test[FatalAlertExternal7] = reg2hw.alert_test.fatal_alert_external_7.qe & + reg2hw.alert_test.fatal_alert_external_7.q; + assign alert_test[FatalAlertExternal8] = reg2hw.alert_test.fatal_alert_external_8.qe & + reg2hw.alert_test.fatal_alert_external_8.q; + assign alert_test[FatalAlertExternal9] = reg2hw.alert_test.fatal_alert_external_9.qe & + reg2hw.alert_test.fatal_alert_external_9.q; + assign alert_test[FatalAlertExternal10] = reg2hw.alert_test.fatal_alert_external_10.qe & + reg2hw.alert_test.fatal_alert_external_10.q; + assign alert_test[FatalAlertExternal11] = reg2hw.alert_test.fatal_alert_external_11.qe & + reg2hw.alert_test.fatal_alert_external_11.q; + assign alert_test[FatalAlertExternal12] = reg2hw.alert_test.fatal_alert_external_12.qe & + reg2hw.alert_test.fatal_alert_external_12.q; + assign alert_test[FatalAlertExternal13] = reg2hw.alert_test.fatal_alert_external_13.qe & + reg2hw.alert_test.fatal_alert_external_13.q; + assign alert_test[FatalAlertExternal14] = reg2hw.alert_test.fatal_alert_external_14.qe & + reg2hw.alert_test.fatal_alert_external_14.q; + assign alert_test[FatalAlertExternal15] = reg2hw.alert_test.fatal_alert_external_15.qe & + reg2hw.alert_test.fatal_alert_external_15.q; + assign alert_test[FatalAlertExternal16] = reg2hw.alert_test.fatal_alert_external_16.qe & + reg2hw.alert_test.fatal_alert_external_16.q; + assign alert_test[FatalAlertExternal17] = reg2hw.alert_test.fatal_alert_external_17.qe & + reg2hw.alert_test.fatal_alert_external_17.q; + assign alert_test[FatalAlertExternal18] = reg2hw.alert_test.fatal_alert_external_18.qe & + reg2hw.alert_test.fatal_alert_external_18.q; + assign alert_test[FatalAlertExternal19] = reg2hw.alert_test.fatal_alert_external_19.qe & + reg2hw.alert_test.fatal_alert_external_19.q; + assign alert_test[FatalAlertExternal20] = reg2hw.alert_test.fatal_alert_external_20.qe & + reg2hw.alert_test.fatal_alert_external_20.q; + assign alert_test[FatalAlertExternal21] = reg2hw.alert_test.fatal_alert_external_21.qe & + reg2hw.alert_test.fatal_alert_external_21.q; + assign alert_test[FatalAlertExternal22] = reg2hw.alert_test.fatal_alert_external_22.qe & + reg2hw.alert_test.fatal_alert_external_22.q; + assign alert_test[FatalAlertExternal23] = reg2hw.alert_test.fatal_alert_external_23.qe & + reg2hw.alert_test.fatal_alert_external_23.q; + + assign alert_test[RecovAlertExternal0] = reg2hw.alert_test.recov_alert_external_0.qe & + reg2hw.alert_test.recov_alert_external_0.q; + assign alert_test[RecovAlertExternal1] = reg2hw.alert_test.recov_alert_external_1.qe & + reg2hw.alert_test.recov_alert_external_1.q; + assign alert_test[RecovAlertExternal2] = reg2hw.alert_test.recov_alert_external_2.qe & + reg2hw.alert_test.recov_alert_external_2.q; + assign alert_test[RecovAlertExternal3] = reg2hw.alert_test.recov_alert_external_3.qe & + reg2hw.alert_test.recov_alert_external_3.q; + + // Handle fatal external alert requests + logic [NumFatalExternalAlerts-1:0] fatal_alert_external, fatal_alert_external_async; + logic [NumFatalExternalAlerts-1:0] soc_fatal_alert_p, soc_fatal_alert_n; + logic [NumFatalExternalAlerts-1:0] soc_fatal_alert_ack_p_d, soc_fatal_alert_ack_n_d; + + // Acknowledge alert based on request. + // Ensure that Ack has always a valid encoding and we swallow a staggered _p/_n signal + always_comb begin + for(int i = 0; i < NumFatalExternalAlerts; i++) begin + // Acknowledge alert based on request. + // Ensure that Ack has always a valid encoding and we swallow a staggered _p/_n signal + if (soc_fatal_alert_p[i] ^ soc_fatal_alert_n[i]) begin + soc_fatal_alert_ack_p_d[i] = soc_fatal_alert_p[i]; + soc_fatal_alert_ack_n_d[i] = soc_fatal_alert_n[i]; + end else begin + soc_fatal_alert_ack_p_d[i] = soc_fatal_alert_o[i].ack_p; + soc_fatal_alert_ack_n_d[i] = soc_fatal_alert_o[i].ack_n; + end + end + end + + for (genvar i = 0; i < NumFatalExternalAlerts; i++) begin : gen_fatal_alert_handling + // Treat any positive value on `alert_p` and any negative value on `alert_n` as alert. + // Combinationally determine the alert on the input signals to generater an asynchronous + // wakeup. + assign fatal_alert_external_async[i] = soc_fatal_alert_p[i] | ~soc_fatal_alert_n[i]; + + // Synchronize external differentially encoded alert to internal clk domain + prim_flop_2sync #( + .Width(1), + .ResetValue(1'b0) + ) u_prim_flop_2sync_fatal_alert_p ( + .clk_i, + .rst_ni, + .d_i (soc_fatal_alert_i[i].alert_p), + .q_o (soc_fatal_alert_p[i]) + ); + prim_flop_2sync #( + .Width(1), + .ResetValue(1'b1) + ) u_prim_flop_2sync_fatal_alert_n ( + .clk_i, + .rst_ni, + .d_i (soc_fatal_alert_i[i].alert_n), + .q_o (soc_fatal_alert_n[i]) + ); + // Treat any positive value on `alert_p` and any negative value on `alert_n` as alert. + assign fatal_alert_external[i] = soc_fatal_alert_p[i] | ~soc_fatal_alert_n[i]; + + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_prim_flop_fatal_ack_p ( + .clk_i, + .rst_ni, + .d_i (soc_fatal_alert_ack_p_d[i]), + .q_o (soc_fatal_alert_o[i].ack_p) + ); + + prim_flop #( + .Width(1), + .ResetValue(1'b1) + ) u_prim_flop_fatal_ack_n ( + .clk_i, + .rst_ni, + .d_i (soc_fatal_alert_ack_n_d[i]), + .q_o (soc_fatal_alert_o[i].ack_n) + ); + end + + // Handle recoverable external alert requests + logic [NumRecovExternalAlerts-1:0] recov_alert_external, recov_alert_external_async; + logic [NumRecovExternalAlerts-1:0] soc_recov_alert_p, soc_recov_alert_n; + logic [NumRecovExternalAlerts-1:0] soc_recov_alert_ack_p_d, soc_recov_alert_ack_n_d; + + // Acknowledge alert based on request. + // Ensure that Ack has always a valid encoding and we swallow a staggered _p/_n signal + always_comb begin + for(int i = 0; i < NumRecovExternalAlerts; i++) begin + if (soc_recov_alert_p[i] ^ soc_recov_alert_n[i]) begin + soc_recov_alert_ack_p_d[i] = soc_recov_alert_p[i]; + soc_recov_alert_ack_n_d[i] = soc_recov_alert_n[i]; + end else begin + soc_recov_alert_ack_p_d[i] = soc_recov_alert_o[i].ack_p; + soc_recov_alert_ack_n_d[i] = soc_recov_alert_o[i].ack_n; + end + end + end + + for (genvar i = 0; i < NumRecovExternalAlerts; i++) begin : gen_recov_alert_handling + // Treat any positive value on `alert_p` and any negative value on `alert_n` as alert. + // Combinationally determine the alert on the input signals to generater an asynchronous + // wakeup. + assign recov_alert_external_async[i] = soc_recov_alert_i[i].alert_p | + ~soc_recov_alert_i[i].alert_n; + + // Synchronize external differentially encoded alert to internal clk domain + prim_flop_2sync #( + .Width(1), + .ResetValue(1'b0) + ) u_prim_flop_2sync_recov_alert_p ( + .clk_i, + .rst_ni, + .d_i (soc_recov_alert_i[i].alert_p), + .q_o (soc_recov_alert_p[i]) + ); + prim_flop_2sync #( + .Width(1), + .ResetValue(1'b1) + ) u_prim_flop_2sync_recov_alert_n ( + .clk_i, + .rst_ni, + .d_i (soc_recov_alert_i[i].alert_n), + .q_o (soc_recov_alert_n[i]) + ); + // Treat any positive value on `alert_p` and any negative value on `alert_n` as alert. + assign recov_alert_external[i] = soc_recov_alert_p[i] | ~soc_recov_alert_n[i]; + + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_prim_flop_recov_ack_p ( + .clk_i, + .rst_ni, + .d_i (soc_recov_alert_ack_p_d[i]), + .q_o (soc_recov_alert_o[i].ack_p) + ); + + prim_flop #( + .Width(1), + .ResetValue(1'b1) + ) u_prim_flop_recov_ack_n ( + .clk_i, + .rst_ni, + .d_i (soc_recov_alert_ack_n_d[i]), + .q_o (soc_recov_alert_o[i].ack_n) + ); + end + + // Aggregate integrity alerts + logic intg_err; + assign intg_err = reg_top_intg_err; + + // Alert sender for integrity alerts + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[FatalAlertIntg]), + .SkewCycles(AlertSkewCycles), + .IsFatal(1) + ) u_prim_fatal_alert_intg_sender ( + .clk_i, + .rst_ni, + .alert_test_i(alert_test[FatalAlertIntg]), + .alert_req_i(intg_err), + .alert_ack_o(), + .alert_state_o(), + .alert_rx_i(alert_rx_i[FatalAlertIntg]), + .alert_tx_o(alert_tx_o[FatalAlertIntg]) + ); + + // Alert senders for fatal external alerts + for (genvar i = 0; i < NumFatalExternalAlerts; i++) begin : gen_fatal_alert_sender + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[FatalAlertExternal0 + i]), + .SkewCycles(AlertSkewCycles), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i(alert_test[FatalAlertExternal0 + i]), + .alert_req_i(fatal_alert_external[i]), + .alert_ack_o(), + .alert_state_o(), + .alert_rx_i(alert_rx_i[FatalAlertExternal0 + i]), + .alert_tx_o(alert_tx_o[FatalAlertExternal0 + i]) + ); + end + + // Alert senders for recoverable external alerts + for (genvar i = 0; i < NumRecovExternalAlerts; i++) begin : gen_recov_alert_sender + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[RecovAlertExternal0 + i]), + .SkewCycles(AlertSkewCycles), + .IsFatal(1'b0) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i(alert_test[RecovAlertExternal0 + i]), + .alert_req_i(recov_alert_external[i]), + .alert_ack_o(), + .alert_state_o(), + .alert_rx_i(alert_rx_i[RecovAlertExternal0 + i]), + .alert_tx_o(alert_tx_o[RecovAlertExternal0 + i]) + ); + end + + // Synchronize external interrupt signals + logic [NumExternalIrqs-1:0] soc_intr; + for (genvar i = 0; i < NumExternalIrqs; i++) begin : gen_sync_external_irqs + prim_flop_2sync #( + .Width(1) + ) u_prim_flop_2sync ( + .clk_i, + .rst_ni, + .d_i(soc_intr_async_i[i]), + .q_o(soc_intr[i]) + ); + end + + // Handle external interrupts + prim_intr_hw #( + .Width(NumExternalIrqs) + ) u_prim_intr_hw ( + .clk_i, + .rst_ni, + .event_intr_i (soc_intr), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.d), + .intr_o (intr_external_o) + ); + + // Synchronize external wakeup request + prim_flop_2sync #( + .Width(1) + ) u_prim_flop_2sync_soc_wkup ( + .clk_i (clk_aon_i), + .rst_ni (rst_por_ni), + .d_i (soc_wkup_async_i), + .q_o (wkup_external_req_o) + ); + + // Generate internal wakeup signal combinatorially from asynchronous signals + logic async_wkup; + assign async_wkup = |{fatal_alert_external_async, recov_alert_external_async, soc_intr_async_i}; + + // Synchronize wakeup signal onto AON domain and filter out potential glitches + prim_filter #( + .AsyncOn(1'b1), + .Cycles(3) + ) u_prim_filter_wkup ( + .clk_i (clk_aon_i), + .rst_ni (rst_por_ni), + .enable_i (1'b1), + .filter_i (async_wkup), + .filter_o (wkup_internal_req_o) + ); + + // Synchronize reset request onto AON domain and filter out potential glitches + prim_filter #( + .AsyncOn(1'b1), + .Cycles(4) + ) u_prim_filter_soc_rst_req ( + .clk_i (clk_aon_i), + .rst_ni (rst_por_ni), + .enable_i (1'b1), + .filter_i (soc_rst_req_async_i), + .filter_o (rst_req_external_o) + ); + + // CDC sync of LSIO trigger signals between the peripheral and the high-speed clock domain + logic uart_lsio_trigger_sync, spi_host_lsio_trigger_sync, i2c_lsio_trigger_sync; + + prim_flop_2sync #( + .Width(1) + ) u_uart_lsio_trigger_sync ( + .clk_i, + .rst_ni, + .d_i (uart_lsio_trigger_i), + .q_o (uart_lsio_trigger_sync) + ); + + prim_flop_2sync #( + .Width(1) + ) u_spi_host_lsio_trigger_sync ( + .clk_i, + .rst_ni, + .d_i (spi_host_lsio_trigger_i), + .q_o (spi_host_lsio_trigger_sync) + ); + + prim_flop_2sync #( + .Width(1) + ) u_i2c_lsio_trigger_sync ( + .clk_i, + .rst_ni, + .d_i (i2c_lsio_trigger_i), + .q_o (i2c_lsio_trigger_sync) + ); + + // Collate LSIO trigger inputs into signal for DMA + assign dma_lsio_trigger_o = { + soc_lsio_trigger_i, + uart_lsio_trigger_sync, + spi_host_lsio_trigger_sync, + i2c_lsio_trigger_sync + }; + + // All outputs should be known value after reset + `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o) + `ASSERT_KNOWN(DmaLsioTriggerKnown_A, dma_lsio_trigger_o) + `ASSERT_KNOWN(CoreTlDValidKnownO_A, core_tl_o.d_valid) + `ASSERT_KNOWN(CoreTlAReadyKnownO_A, core_tl_o.a_ready) + + // Assertions + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, + u_reg, + alert_tx_o[FatalAlertIntg]) + + // Assert that there's one index for each alert defined in the Hjson. + `ASSERT_INIT(AlertSourcesComplete_A, NumAlertSources == NumAlerts) + + // Assert that the number of internal and external alerts sum up to the total number of alerts. + `ASSERT_INIT(AlertNumsSumCorrect_A, NumInternalAlerts + NumExternalAlerts == NumAlertSources) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_core_reg_top.sv b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_core_reg_top.sv new file mode 100644 index 00000000000..6c8047163cc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_core_reg_top.sv @@ -0,0 +1,889 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module soc_proxy_core_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output soc_proxy_reg_pkg::soc_proxy_core_reg2hw_t reg2hw, // Write + input soc_proxy_reg_pkg::soc_proxy_core_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import soc_proxy_reg_pkg::* ; + + localparam int AW = 4; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [3:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(4) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic [31:0] intr_state_qs; + logic [31:0] intr_state_wd; + logic intr_enable_we; + logic [31:0] intr_enable_qs; + logic [31:0] intr_enable_wd; + logic intr_test_we; + logic [31:0] intr_test_wd; + logic alert_test_we; + logic alert_test_fatal_alert_intg_wd; + logic alert_test_fatal_alert_external_0_wd; + logic alert_test_fatal_alert_external_1_wd; + logic alert_test_fatal_alert_external_2_wd; + logic alert_test_fatal_alert_external_3_wd; + logic alert_test_fatal_alert_external_4_wd; + logic alert_test_fatal_alert_external_5_wd; + logic alert_test_fatal_alert_external_6_wd; + logic alert_test_fatal_alert_external_7_wd; + logic alert_test_fatal_alert_external_8_wd; + logic alert_test_fatal_alert_external_9_wd; + logic alert_test_fatal_alert_external_10_wd; + logic alert_test_fatal_alert_external_11_wd; + logic alert_test_fatal_alert_external_12_wd; + logic alert_test_fatal_alert_external_13_wd; + logic alert_test_fatal_alert_external_14_wd; + logic alert_test_fatal_alert_external_15_wd; + logic alert_test_fatal_alert_external_16_wd; + logic alert_test_fatal_alert_external_17_wd; + logic alert_test_fatal_alert_external_18_wd; + logic alert_test_fatal_alert_external_19_wd; + logic alert_test_fatal_alert_external_20_wd; + logic alert_test_fatal_alert_external_21_wd; + logic alert_test_fatal_alert_external_22_wd; + logic alert_test_fatal_alert_external_23_wd; + logic alert_test_recov_alert_external_0_wd; + logic alert_test_recov_alert_external_1_wd; + logic alert_test_recov_alert_external_2_wd; + logic alert_test_recov_alert_external_3_wd; + + // Register instances + // R[intr_state]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_intr_state ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_wd), + + // from internal hardware + .de (hw2reg.intr_state.de), + .d (hw2reg.intr_state.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.q), + .ds (), + + // to register interface (read) + .qs (intr_state_qs) + ); + + + // R[intr_enable]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_intr_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [0:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + prim_subreg_ext #( + .DW (32) + ) u_intr_test ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [28:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[fatal_alert_intg]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_intg ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_intg_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.fatal_alert_intg.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_intg.qe = alert_test_qe; + + // F[fatal_alert_external_0]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_0 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_0_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_alert_external_0.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_0.qe = alert_test_qe; + + // F[fatal_alert_external_1]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_1 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_1_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[2]), + .q (reg2hw.alert_test.fatal_alert_external_1.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_1.qe = alert_test_qe; + + // F[fatal_alert_external_2]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_2 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_2_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[3]), + .q (reg2hw.alert_test.fatal_alert_external_2.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_2.qe = alert_test_qe; + + // F[fatal_alert_external_3]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_3 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_3_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[4]), + .q (reg2hw.alert_test.fatal_alert_external_3.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_3.qe = alert_test_qe; + + // F[fatal_alert_external_4]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_4 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_4_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[5]), + .q (reg2hw.alert_test.fatal_alert_external_4.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_4.qe = alert_test_qe; + + // F[fatal_alert_external_5]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_5 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_5_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[6]), + .q (reg2hw.alert_test.fatal_alert_external_5.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_5.qe = alert_test_qe; + + // F[fatal_alert_external_6]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_6 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_6_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[7]), + .q (reg2hw.alert_test.fatal_alert_external_6.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_6.qe = alert_test_qe; + + // F[fatal_alert_external_7]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_7 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_7_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[8]), + .q (reg2hw.alert_test.fatal_alert_external_7.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_7.qe = alert_test_qe; + + // F[fatal_alert_external_8]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_8 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_8_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[9]), + .q (reg2hw.alert_test.fatal_alert_external_8.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_8.qe = alert_test_qe; + + // F[fatal_alert_external_9]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_9 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_9_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[10]), + .q (reg2hw.alert_test.fatal_alert_external_9.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_9.qe = alert_test_qe; + + // F[fatal_alert_external_10]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_10 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_10_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[11]), + .q (reg2hw.alert_test.fatal_alert_external_10.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_10.qe = alert_test_qe; + + // F[fatal_alert_external_11]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_11 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_11_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[12]), + .q (reg2hw.alert_test.fatal_alert_external_11.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_11.qe = alert_test_qe; + + // F[fatal_alert_external_12]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_12 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_12_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[13]), + .q (reg2hw.alert_test.fatal_alert_external_12.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_12.qe = alert_test_qe; + + // F[fatal_alert_external_13]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_13 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_13_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[14]), + .q (reg2hw.alert_test.fatal_alert_external_13.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_13.qe = alert_test_qe; + + // F[fatal_alert_external_14]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_14 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_14_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[15]), + .q (reg2hw.alert_test.fatal_alert_external_14.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_14.qe = alert_test_qe; + + // F[fatal_alert_external_15]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_15 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_15_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[16]), + .q (reg2hw.alert_test.fatal_alert_external_15.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_15.qe = alert_test_qe; + + // F[fatal_alert_external_16]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_16 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_16_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[17]), + .q (reg2hw.alert_test.fatal_alert_external_16.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_16.qe = alert_test_qe; + + // F[fatal_alert_external_17]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_17 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_17_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[18]), + .q (reg2hw.alert_test.fatal_alert_external_17.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_17.qe = alert_test_qe; + + // F[fatal_alert_external_18]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_18 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_18_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[19]), + .q (reg2hw.alert_test.fatal_alert_external_18.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_18.qe = alert_test_qe; + + // F[fatal_alert_external_19]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_19 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_19_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[20]), + .q (reg2hw.alert_test.fatal_alert_external_19.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_19.qe = alert_test_qe; + + // F[fatal_alert_external_20]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_20 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_20_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[21]), + .q (reg2hw.alert_test.fatal_alert_external_20.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_20.qe = alert_test_qe; + + // F[fatal_alert_external_21]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_21 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_21_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[22]), + .q (reg2hw.alert_test.fatal_alert_external_21.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_21.qe = alert_test_qe; + + // F[fatal_alert_external_22]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_22 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_22_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[23]), + .q (reg2hw.alert_test.fatal_alert_external_22.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_22.qe = alert_test_qe; + + // F[fatal_alert_external_23]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_alert_external_23 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_alert_external_23_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[24]), + .q (reg2hw.alert_test.fatal_alert_external_23.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_alert_external_23.qe = alert_test_qe; + + // F[recov_alert_external_0]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_alert_external_0 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_alert_external_0_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[25]), + .q (reg2hw.alert_test.recov_alert_external_0.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_alert_external_0.qe = alert_test_qe; + + // F[recov_alert_external_1]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_alert_external_1 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_alert_external_1_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[26]), + .q (reg2hw.alert_test.recov_alert_external_1.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_alert_external_1.qe = alert_test_qe; + + // F[recov_alert_external_2]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_alert_external_2 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_alert_external_2_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[27]), + .q (reg2hw.alert_test.recov_alert_external_2.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_alert_external_2.qe = alert_test_qe; + + // F[recov_alert_external_3]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_alert_external_3 ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_alert_external_3_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[28]), + .q (reg2hw.alert_test.recov_alert_external_3.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_alert_external_3.qe = alert_test_qe; + + + + logic [3:0] addr_hit; + always_comb begin + addr_hit[0] = (reg_addr == SOC_PROXY_INTR_STATE_OFFSET); + addr_hit[1] = (reg_addr == SOC_PROXY_INTR_ENABLE_OFFSET); + addr_hit[2] = (reg_addr == SOC_PROXY_INTR_TEST_OFFSET); + addr_hit[3] = (reg_addr == SOC_PROXY_ALERT_TEST_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[0] & (|(SOC_PROXY_CORE_PERMIT[0] & ~reg_be))) | + (addr_hit[1] & (|(SOC_PROXY_CORE_PERMIT[1] & ~reg_be))) | + (addr_hit[2] & (|(SOC_PROXY_CORE_PERMIT[2] & ~reg_be))) | + (addr_hit[3] & (|(SOC_PROXY_CORE_PERMIT[3] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = addr_hit[0] & reg_we & !reg_error; + + assign intr_state_wd = reg_wdata[31:0]; + assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; + + assign intr_enable_wd = reg_wdata[31:0]; + assign intr_test_we = addr_hit[2] & reg_we & !reg_error; + + assign intr_test_wd = reg_wdata[31:0]; + assign alert_test_we = addr_hit[3] & reg_we & !reg_error; + + assign alert_test_fatal_alert_intg_wd = reg_wdata[0]; + + assign alert_test_fatal_alert_external_0_wd = reg_wdata[1]; + + assign alert_test_fatal_alert_external_1_wd = reg_wdata[2]; + + assign alert_test_fatal_alert_external_2_wd = reg_wdata[3]; + + assign alert_test_fatal_alert_external_3_wd = reg_wdata[4]; + + assign alert_test_fatal_alert_external_4_wd = reg_wdata[5]; + + assign alert_test_fatal_alert_external_5_wd = reg_wdata[6]; + + assign alert_test_fatal_alert_external_6_wd = reg_wdata[7]; + + assign alert_test_fatal_alert_external_7_wd = reg_wdata[8]; + + assign alert_test_fatal_alert_external_8_wd = reg_wdata[9]; + + assign alert_test_fatal_alert_external_9_wd = reg_wdata[10]; + + assign alert_test_fatal_alert_external_10_wd = reg_wdata[11]; + + assign alert_test_fatal_alert_external_11_wd = reg_wdata[12]; + + assign alert_test_fatal_alert_external_12_wd = reg_wdata[13]; + + assign alert_test_fatal_alert_external_13_wd = reg_wdata[14]; + + assign alert_test_fatal_alert_external_14_wd = reg_wdata[15]; + + assign alert_test_fatal_alert_external_15_wd = reg_wdata[16]; + + assign alert_test_fatal_alert_external_16_wd = reg_wdata[17]; + + assign alert_test_fatal_alert_external_17_wd = reg_wdata[18]; + + assign alert_test_fatal_alert_external_18_wd = reg_wdata[19]; + + assign alert_test_fatal_alert_external_19_wd = reg_wdata[20]; + + assign alert_test_fatal_alert_external_20_wd = reg_wdata[21]; + + assign alert_test_fatal_alert_external_21_wd = reg_wdata[22]; + + assign alert_test_fatal_alert_external_22_wd = reg_wdata[23]; + + assign alert_test_fatal_alert_external_23_wd = reg_wdata[24]; + + assign alert_test_recov_alert_external_0_wd = reg_wdata[25]; + + assign alert_test_recov_alert_external_1_wd = reg_wdata[26]; + + assign alert_test_recov_alert_external_2_wd = reg_wdata[27]; + + assign alert_test_recov_alert_external_3_wd = reg_wdata[28]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[31:0] = intr_state_qs; + end + + addr_hit[1]: begin + reg_rdata_next[31:0] = intr_enable_qs; + end + + addr_hit[2]: begin + reg_rdata_next[31:0] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; + reg_rdata_next[11] = '0; + reg_rdata_next[12] = '0; + reg_rdata_next[13] = '0; + reg_rdata_next[14] = '0; + reg_rdata_next[15] = '0; + reg_rdata_next[16] = '0; + reg_rdata_next[17] = '0; + reg_rdata_next[18] = '0; + reg_rdata_next[19] = '0; + reg_rdata_next[20] = '0; + reg_rdata_next[21] = '0; + reg_rdata_next[22] = '0; + reg_rdata_next[23] = '0; + reg_rdata_next[24] = '0; + reg_rdata_next[25] = '0; + reg_rdata_next[26] = '0; + reg_rdata_next[27] = '0; + reg_rdata_next[28] = '0; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_ctn_reg_top.sv b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_ctn_reg_top.sv new file mode 100644 index 00000000000..88c5d89daf6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_ctn_reg_top.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module soc_proxy_ctn_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + + // Integrity check errors + output logic intg_err_o +); + + import soc_proxy_reg_pkg::* ; + + + + // Since there are no registers in this block, commands are routed through to windows which + // can report their own integrity errors. + assign intg_err_o = 1'b0; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + // Unused signal tieoff +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_pkg.sv b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_pkg.sv new file mode 100644 index 00000000000..bac0fc5aad4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_pkg.sv @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package soc_proxy_pkg; + + // Alert interface types + typedef struct packed { + logic alert_p; + logic alert_n; + } soc_alert_req_t; + typedef struct packed { + logic ack_p; + logic ack_n; + } soc_alert_rsp_t; + + // Default values for alert interface types + parameter soc_alert_req_t SOC_ALERT_REQ_DEFAULT = '{alert_p: 1'b0, alert_n: 1'b1}; + parameter soc_alert_rsp_t SOC_ALERT_RSP_DEFAULT = '{ack_p: 1'b0, ack_n: 1'b1}; + + // This defines the index of each of SoC Proxy's alerts. If you add, change, or remove an alert, + // update this enum as well. + typedef enum logic [$clog2(soc_proxy_reg_pkg::NumAlerts+1)-1:0] { + FatalAlertIntg, + FatalAlertExternal0, + FatalAlertExternal1, + FatalAlertExternal2, + FatalAlertExternal3, + FatalAlertExternal4, + FatalAlertExternal5, + FatalAlertExternal6, + FatalAlertExternal7, + FatalAlertExternal8, + FatalAlertExternal9, + FatalAlertExternal10, + FatalAlertExternal11, + FatalAlertExternal12, + FatalAlertExternal13, + FatalAlertExternal14, + FatalAlertExternal15, + FatalAlertExternal16, + FatalAlertExternal17, + FatalAlertExternal18, + FatalAlertExternal19, + FatalAlertExternal20, + FatalAlertExternal21, + FatalAlertExternal22, + FatalAlertExternal23, + RecovAlertExternal0, + RecovAlertExternal1, + RecovAlertExternal2, + RecovAlertExternal3, + NumAlertSources + } soc_proxy_alert_e; + + localparam int unsigned NumSocGpio = 16; + + // Keep this value in sync with pinmux and top-level configuration. + localparam int unsigned NumSocGpioMappedOnDio = 12; + localparam int unsigned NumSocGpioMuxed = NumSocGpio - NumSocGpioMappedOnDio; + + // Assertions on these constants are part of the `soc_proxy` module (since they can't be put into + // this package). + localparam int unsigned NumInternalAlerts = FatalAlertIntg - FatalAlertIntg + 1; + parameter int unsigned NumFatalExternalAlerts = FatalAlertExternal23 - FatalAlertExternal0 + 1; + parameter int unsigned NumRecovExternalAlerts = RecovAlertExternal3 - RecovAlertExternal0 + 1; + localparam int unsigned NumExternalAlerts = NumFatalExternalAlerts + NumRecovExternalAlerts; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_reg_pkg.sv new file mode 100644 index 00000000000..9d32e297e38 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/rtl/soc_proxy_reg_pkg.sv @@ -0,0 +1,264 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package soc_proxy_reg_pkg; + + // Param list + parameter int unsigned NumExternalIrqs = 32; + parameter int NumAlerts = 29; + + // Address widths within the block + parameter int CoreAw = 4; + parameter int CtnAw = 1; + + // Number of registers for every interface + parameter int NumRegsCore = 4; + parameter int NumRegsCtn = 0; + + // Alert indices + typedef enum int { + AlertFatalAlertIntgIdx = 0, + AlertFatalAlertExternal0Idx = 1, + AlertFatalAlertExternal1Idx = 2, + AlertFatalAlertExternal2Idx = 3, + AlertFatalAlertExternal3Idx = 4, + AlertFatalAlertExternal4Idx = 5, + AlertFatalAlertExternal5Idx = 6, + AlertFatalAlertExternal6Idx = 7, + AlertFatalAlertExternal7Idx = 8, + AlertFatalAlertExternal8Idx = 9, + AlertFatalAlertExternal9Idx = 10, + AlertFatalAlertExternal10Idx = 11, + AlertFatalAlertExternal11Idx = 12, + AlertFatalAlertExternal12Idx = 13, + AlertFatalAlertExternal13Idx = 14, + AlertFatalAlertExternal14Idx = 15, + AlertFatalAlertExternal15Idx = 16, + AlertFatalAlertExternal16Idx = 17, + AlertFatalAlertExternal17Idx = 18, + AlertFatalAlertExternal18Idx = 19, + AlertFatalAlertExternal19Idx = 20, + AlertFatalAlertExternal20Idx = 21, + AlertFatalAlertExternal21Idx = 22, + AlertFatalAlertExternal22Idx = 23, + AlertFatalAlertExternal23Idx = 24, + AlertRecovAlertExternal0Idx = 25, + AlertRecovAlertExternal1Idx = 26, + AlertRecovAlertExternal2Idx = 27, + AlertRecovAlertExternal3Idx = 28 + } soc_proxy_alert_idx_t; + + /////////////////////////////////////////////// + // Typedefs for registers for core interface // + /////////////////////////////////////////////// + + typedef struct packed { + logic [31:0] q; + } soc_proxy_reg2hw_intr_state_reg_t; + + typedef struct packed { + logic [31:0] q; + } soc_proxy_reg2hw_intr_enable_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } soc_proxy_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } recov_alert_external_3; + struct packed { + logic q; + logic qe; + } recov_alert_external_2; + struct packed { + logic q; + logic qe; + } recov_alert_external_1; + struct packed { + logic q; + logic qe; + } recov_alert_external_0; + struct packed { + logic q; + logic qe; + } fatal_alert_external_23; + struct packed { + logic q; + logic qe; + } fatal_alert_external_22; + struct packed { + logic q; + logic qe; + } fatal_alert_external_21; + struct packed { + logic q; + logic qe; + } fatal_alert_external_20; + struct packed { + logic q; + logic qe; + } fatal_alert_external_19; + struct packed { + logic q; + logic qe; + } fatal_alert_external_18; + struct packed { + logic q; + logic qe; + } fatal_alert_external_17; + struct packed { + logic q; + logic qe; + } fatal_alert_external_16; + struct packed { + logic q; + logic qe; + } fatal_alert_external_15; + struct packed { + logic q; + logic qe; + } fatal_alert_external_14; + struct packed { + logic q; + logic qe; + } fatal_alert_external_13; + struct packed { + logic q; + logic qe; + } fatal_alert_external_12; + struct packed { + logic q; + logic qe; + } fatal_alert_external_11; + struct packed { + logic q; + logic qe; + } fatal_alert_external_10; + struct packed { + logic q; + logic qe; + } fatal_alert_external_9; + struct packed { + logic q; + logic qe; + } fatal_alert_external_8; + struct packed { + logic q; + logic qe; + } fatal_alert_external_7; + struct packed { + logic q; + logic qe; + } fatal_alert_external_6; + struct packed { + logic q; + logic qe; + } fatal_alert_external_5; + struct packed { + logic q; + logic qe; + } fatal_alert_external_4; + struct packed { + logic q; + logic qe; + } fatal_alert_external_3; + struct packed { + logic q; + logic qe; + } fatal_alert_external_2; + struct packed { + logic q; + logic qe; + } fatal_alert_external_1; + struct packed { + logic q; + logic qe; + } fatal_alert_external_0; + struct packed { + logic q; + logic qe; + } fatal_alert_intg; + } soc_proxy_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } soc_proxy_hw2reg_intr_state_reg_t; + + // Register -> HW type for core interface + typedef struct packed { + soc_proxy_reg2hw_intr_state_reg_t intr_state; // [154:123] + soc_proxy_reg2hw_intr_enable_reg_t intr_enable; // [122:91] + soc_proxy_reg2hw_intr_test_reg_t intr_test; // [90:58] + soc_proxy_reg2hw_alert_test_reg_t alert_test; // [57:0] + } soc_proxy_core_reg2hw_t; + + // HW -> register type for core interface + typedef struct packed { + soc_proxy_hw2reg_intr_state_reg_t intr_state; // [32:0] + } soc_proxy_core_hw2reg_t; + + // Register offsets for core interface + parameter logic [CoreAw-1:0] SOC_PROXY_INTR_STATE_OFFSET = 4'h 0; + parameter logic [CoreAw-1:0] SOC_PROXY_INTR_ENABLE_OFFSET = 4'h 4; + parameter logic [CoreAw-1:0] SOC_PROXY_INTR_TEST_OFFSET = 4'h 8; + parameter logic [CoreAw-1:0] SOC_PROXY_ALERT_TEST_OFFSET = 4'h c; + + // Reset values for hwext registers and their fields for core interface + parameter logic [31:0] SOC_PROXY_INTR_TEST_RESVAL = 32'h 0; + parameter logic [31:0] SOC_PROXY_INTR_TEST_EXTERNAL_RESVAL = 32'h 0; + parameter logic [28:0] SOC_PROXY_ALERT_TEST_RESVAL = 29'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_INTG_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_0_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_1_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_2_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_3_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_4_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_5_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_6_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_7_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_8_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_9_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_10_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_11_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_12_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_13_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_14_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_15_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_16_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_17_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_18_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_19_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_20_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_21_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_22_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_FATAL_ALERT_EXTERNAL_23_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_RECOV_ALERT_EXTERNAL_0_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_RECOV_ALERT_EXTERNAL_1_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_RECOV_ALERT_EXTERNAL_2_RESVAL = 1'h 0; + parameter logic [0:0] SOC_PROXY_ALERT_TEST_RECOV_ALERT_EXTERNAL_3_RESVAL = 1'h 0; + + // Register index for core interface + typedef enum int { + SOC_PROXY_INTR_STATE, + SOC_PROXY_INTR_ENABLE, + SOC_PROXY_INTR_TEST, + SOC_PROXY_ALERT_TEST + } soc_proxy_core_id_e; + + // Register width information to check illegal writes for core interface + parameter logic [3:0] SOC_PROXY_CORE_PERMIT [4] = '{ + 4'b 1111, // index[0] SOC_PROXY_INTR_STATE + 4'b 1111, // index[1] SOC_PROXY_INTR_ENABLE + 4'b 1111, // index[2] SOC_PROXY_INTR_TEST + 4'b 1111 // index[3] SOC_PROXY_ALERT_TEST + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/soc_proxy.core b/hw/top_darjeeling_no_ibex/ip/soc_proxy/soc_proxy.core new file mode 100644 index 00000000000..894bf9b3181 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/soc_proxy.core @@ -0,0 +1,60 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:soc_proxy:0.1" +description: "SoC Proxy" + +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + - lowrisc:ip:tlul + - lowrisc:ip:dma_pkg + - lowrisc:systems:soc_proxy_pkg + files: + - rtl/bat.sv + - rtl/soc_proxy_core_reg_top.sv + - rtl/soc_proxy.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/soc_proxy.waiver + file_type: waiver + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - files_rtl + toplevel: soc_proxy + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip/soc_proxy/soc_proxy_pkg.core b/hw/top_darjeeling_no_ibex/ip/soc_proxy/soc_proxy_pkg.core new file mode 100644 index 00000000000..c30c0a03795 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/soc_proxy/soc_proxy_pkg.core @@ -0,0 +1,20 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:soc_proxy_pkg:0.1" +description: "SoC Proxy Package" + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + files: + - rtl/soc_proxy_reg_pkg.sv + - rtl/soc_proxy_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson new file mode 100644 index 00000000000..431cfa10253 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/data/autogen/xbar_dbg.gen.hjson @@ -0,0 +1,188 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson -o hw/top_darjeeling_no_ibex/ + +{ + name: dbg + clock_srcs: + { + clk_dbg_i: main + clk_peri_i: io_div4 + } + clock_group: infra + reset: rst_dbg_ni + reset_connections: + { + rst_dbg_ni: + { + name: lc + domain: "0" + } + rst_peri_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_dbg_i: clkmgr_aon_clocks.clk_main_infra + clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + dbg: + [ + mbx_jtag.soc + lc_ctrl.dmi + soc_dbg_ctrl.jtag + ] + } + nodes: + [ + { + name: dbg + type: host + addr_space: soc_dbg + clock: clk_dbg_i + reset: rst_dbg_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_jtag.soc + type: device + clock: clk_dbg_i + reset: rst_dbg_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x2200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: lc_ctrl.dmi + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: lc_ctrl + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x3000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: soc_dbg_ctrl.jtag + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: soc_dbg_ctrl + addr_range: + [ + { + base_addrs: + { + soc_dbg: 0x2300 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + soc_dbg + ] + clock: clk_dbg_i + type: xbar + inter_signal_list: + [ + { + name: tl_dbg + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: dbg + width: 1 + default: "" + external: true + top_signame: dbg_tl + conn_type: false + index: -1 + } + { + name: tl_mbx_jtag__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: dbg + width: 1 + default: "" + top_signame: mbx_jtag_soc_tl_d + index: -1 + } + { + name: tl_lc_ctrl__dmi + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: dbg + width: 1 + default: "" + top_signame: lc_ctrl_dmi_tl + index: -1 + } + { + name: tl_soc_dbg_ctrl__jtag + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: dbg + width: 1 + default: "" + top_signame: soc_dbg_ctrl_jtag_tl + index: -1 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/data/autogen/xbar_dbg.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/data/autogen/xbar_dbg.hjson new file mode 100644 index 00000000000..a407a7e9de5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/data/autogen/xbar_dbg.hjson @@ -0,0 +1,41 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_dbg comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_dbg" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_dbg" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_jtag__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_lc_ctrl__dmi" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_soc_dbg_ctrl__jtag" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 00000000000..107edb6e276 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,25 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_dbg dut(); + +`DRIVE_CLK(clk_dbg_i) +`DRIVE_CLK(clk_peri_i) + +initial force dut.clk_dbg_i = clk_dbg_i; +initial force dut.clk_peri_i = clk_peri_i; + +// TODO, all resets tie together +initial force dut.rst_dbg_ni = rst_n; +initial force dut.rst_peri_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(dbg, dut, clk_dbg_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(mbx_jtag__soc, dut, clk_dbg_i, rst_n) +`CONNECT_TL_DEVICE_IF(lc_ctrl__dmi, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(soc_dbg_ctrl__jtag, dut, clk_peri_i, rst_n) diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_cov_excl.el new file mode 100644 index 00000000000..fa86a7e7963 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_dbg +Block 1 "0" "assign unused_scanmode = scanmode_i;" diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_cover.cfg new file mode 100644 index 00000000000..d8f5bfe1978 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_cover.cfg @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_mbx_jtag__soc_o.a_address[8:5] +-node tb.dut tl_mbx_jtag__soc_o.a_address[12:10] +-node tb.dut tl_mbx_jtag__soc_o.a_address[31:14] +-node tb.dut tl_lc_ctrl__dmi_o.a_address[31:14] +-node tb.dut tl_soc_dbg_ctrl__jtag_o.a_address[7:5] +-node tb.dut tl_soc_dbg_ctrl__jtag_o.a_address[12:10] +-node tb.dut tl_soc_dbg_ctrl__jtag_o.a_address[31:14] + +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core new file mode 100644 index 00000000000..9c544dfbe50 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_dbg_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_dbg_bind:0.1" +description: "XBAR dbg assertion bind" +filesets: + files_dv: + files: + - xbar_dbg_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv new file mode 100644 index 00000000000..2072662b0cd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_bind.sv @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_dbg_bind module generated by `tlgen.py` tool for assertions +module xbar_dbg_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_dbg tlul_assert #(.EndpointType("Device")) tlul_assert_host_dbg ( + .clk_i (clk_dbg_i), + .rst_ni (rst_dbg_ni), + .h2d (tl_dbg_i), + .d2h (tl_dbg_o) + ); + + // Device interfaces + bind xbar_dbg tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_jtag__soc ( + .clk_i (clk_dbg_i), + .rst_ni (rst_dbg_ni), + .h2d (tl_mbx_jtag__soc_o), + .d2h (tl_mbx_jtag__soc_i) + ); + bind xbar_dbg tlul_assert #(.EndpointType("Host")) tlul_assert_device_lc_ctrl__dmi ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_lc_ctrl__dmi_o), + .d2h (tl_lc_ctrl__dmi_i) + ); + bind xbar_dbg tlul_assert #(.EndpointType("Host")) tlul_assert_device_soc_dbg_ctrl__jtag ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_soc_dbg_ctrl__jtag_o), + .d2h (tl_soc_dbg_ctrl__jtag_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core new file mode 100644 index 00000000000..da9ae5fe4e4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_dbg_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_dbg_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling_no_ibex:xbar_dbg + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_no_ibex_xbar_dbg_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_sim_cfg.hjson new file mode 100644 index 00000000000..d2740a3b37d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_dbg_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_dbg_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_dbg + + // Top level dut name (sv module). + dut: xbar_dbg + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling_no_ibex + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 00000000000..4600dc07af4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"mbx_jtag__soc", '{ + '{32'h00002200, 32'h0000221f} + }}, + '{"lc_ctrl__dmi", '{ + '{32'h00003000, 32'h00003fff} + }}, + '{"soc_dbg_ctrl__jtag", '{ + '{32'h00002300, 32'h0000231f} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"dbg", 0, '{ + "mbx_jtag__soc", + "lc_ctrl__dmi", + "soc_dbg_ctrl__jtag"}} +}; diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv new file mode 100644 index 00000000000..56383398c88 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/rtl/autogen/tl_dbg_pkg.sv @@ -0,0 +1,30 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_dbg package generated by `tlgen.py` tool + +package tl_dbg_pkg; + + localparam logic [31:0] ADDR_SPACE_MBX_JTAG__SOC = 32'h 00002200; + localparam logic [31:0] ADDR_SPACE_LC_CTRL__DMI = 32'h 00003000; + localparam logic [31:0] ADDR_SPACE_SOC_DBG_CTRL__JTAG = 32'h 00002300; + + localparam logic [31:0] ADDR_MASK_MBX_JTAG__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_LC_CTRL__DMI = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_SOC_DBG_CTRL__JTAG = 32'h 0000001f; + + localparam int N_HOST = 1; + localparam int N_DEVICE = 3; + + typedef enum int { + TlMbxJtagSoc = 0, + TlLcCtrlDmi = 1, + TlSocDbgCtrlJtag = 2 + } tl_device_e; + + typedef enum int { + TlDbg = 0 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/rtl/autogen/xbar_dbg.sv b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/rtl/autogen/xbar_dbg.sv new file mode 100644 index 00000000000..3c139750d43 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/rtl/autogen/xbar_dbg.sv @@ -0,0 +1,147 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_dbg module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// dbg +// -> s1n_4 +// -> mbx_jtag.soc +// -> asf_5 +// -> lc_ctrl.dmi +// -> asf_6 +// -> soc_dbg_ctrl.jtag + +module xbar_dbg ( + input clk_dbg_i, + input clk_peri_i, + input rst_dbg_ni, + input rst_peri_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_dbg_i, + output tlul_pkg::tl_d2h_t tl_dbg_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_mbx_jtag__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx_jtag__soc_i, + output tlul_pkg::tl_h2d_t tl_lc_ctrl__dmi_o, + input tlul_pkg::tl_d2h_t tl_lc_ctrl__dmi_i, + output tlul_pkg::tl_h2d_t tl_soc_dbg_ctrl__jtag_o, + input tlul_pkg::tl_d2h_t tl_soc_dbg_ctrl__jtag_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_dbg_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_4_us_h2d ; + tl_d2h_t tl_s1n_4_us_d2h ; + + + tl_h2d_t tl_s1n_4_ds_h2d [3]; + tl_d2h_t tl_s1n_4_ds_d2h [3]; + + // Create steering signal + logic [1:0] dev_sel_s1n_4; + + tl_h2d_t tl_asf_5_us_h2d ; + tl_d2h_t tl_asf_5_us_d2h ; + tl_h2d_t tl_asf_5_ds_h2d ; + tl_d2h_t tl_asf_5_ds_d2h ; + + tl_h2d_t tl_asf_6_us_h2d ; + tl_d2h_t tl_asf_6_us_d2h ; + tl_h2d_t tl_asf_6_ds_h2d ; + tl_d2h_t tl_asf_6_ds_d2h ; + + + + assign tl_mbx_jtag__soc_o = tl_s1n_4_ds_h2d[0]; + assign tl_s1n_4_ds_d2h[0] = tl_mbx_jtag__soc_i; + + assign tl_asf_5_us_h2d = tl_s1n_4_ds_h2d[1]; + assign tl_s1n_4_ds_d2h[1] = tl_asf_5_us_d2h; + + assign tl_asf_6_us_h2d = tl_s1n_4_ds_h2d[2]; + assign tl_s1n_4_ds_d2h[2] = tl_asf_6_us_d2h; + + assign tl_s1n_4_us_h2d = tl_dbg_i; + assign tl_dbg_o = tl_s1n_4_us_d2h; + + assign tl_lc_ctrl__dmi_o = tl_asf_5_ds_h2d; + assign tl_asf_5_ds_d2h = tl_lc_ctrl__dmi_i; + + assign tl_soc_dbg_ctrl__jtag_o = tl_asf_6_ds_h2d; + assign tl_asf_6_ds_d2h = tl_soc_dbg_ctrl__jtag_i; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_4 = 2'd3; + if ((tl_s1n_4_us_h2d.a_address & + ~(ADDR_MASK_MBX_JTAG__SOC)) == ADDR_SPACE_MBX_JTAG__SOC) begin + dev_sel_s1n_4 = 2'd0; + + end else if ((tl_s1n_4_us_h2d.a_address & + ~(ADDR_MASK_LC_CTRL__DMI)) == ADDR_SPACE_LC_CTRL__DMI) begin + dev_sel_s1n_4 = 2'd1; + + end else if ((tl_s1n_4_us_h2d.a_address & + ~(ADDR_MASK_SOC_DBG_CTRL__JTAG)) == ADDR_SPACE_SOC_DBG_CTRL__JTAG) begin + dev_sel_s1n_4 = 2'd2; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (12'h0), + .DRspDepth (12'h0), + .N (3) + ) u_s1n_4 ( + .clk_i (clk_dbg_i), + .rst_ni (rst_dbg_ni), + .tl_h_i (tl_s1n_4_us_h2d), + .tl_h_o (tl_s1n_4_us_d2h), + .tl_d_o (tl_s1n_4_ds_h2d), + .tl_d_i (tl_s1n_4_ds_d2h), + .dev_select_i (dev_sel_s1n_4) + ); + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_5 ( + .clk_h_i (clk_dbg_i), + .rst_h_ni (rst_dbg_ni), + .clk_d_i (clk_peri_i), + .rst_d_ni (rst_peri_ni), + .tl_h_i (tl_asf_5_us_h2d), + .tl_h_o (tl_asf_5_us_d2h), + .tl_d_o (tl_asf_5_ds_h2d), + .tl_d_i (tl_asf_5_ds_d2h) + ); + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_6 ( + .clk_h_i (clk_dbg_i), + .rst_h_ni (rst_dbg_ni), + .clk_d_i (clk_peri_i), + .rst_d_ni (rst_peri_ni), + .tl_h_i (tl_asf_6_us_h2d), + .tl_h_o (tl_asf_6_us_d2h), + .tl_d_o (tl_asf_6_ds_h2d), + .tl_d_i (tl_asf_6_ds_d2h) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_dbg/xbar_dbg.core b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/xbar_dbg.core new file mode 100644 index 00000000000..4c4945ed03d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_dbg/xbar_dbg.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_dbg core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling_no_ibex:xbar_dbg:0.1" +description: "Generated RTL xbar_dbg" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_dbg_pkg.sv + - rtl/autogen/xbar_dbg.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_dbg diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_main/data/autogen/xbar_main.gen.hjson new file mode 100644 index 00000000000..95d7735f5da --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -0,0 +1,698 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson -o hw/top_darjeeling_no_ibex/ + +{ + name: main + clock_srcs: + { + clk_main_i: main + clk_fixed_i: io_div4 + } + clock_group: infra + reset: rst_main_ni + reset_connections: + { + rst_main_ni: + { + name: lc + domain: "0" + } + rst_fixed_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_main_i: clkmgr_aon_clocks.clk_main_infra + clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + dma.host: + [ + sram_ctrl_main.ram + sram_ctrl_mbox.ram + aes + hmac + otbn + keymgr_dpe + kmac + soc_proxy.ctn + peri + ] + mbx0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx1.sram: + [ + sram_ctrl_mbox.ram + ] + mbx2.sram: + [ + sram_ctrl_mbox.ram + ] + mbx3.sram: + [ + sram_ctrl_mbox.ram + ] + mbx4.sram: + [ + sram_ctrl_mbox.ram + ] + mbx5.sram: + [ + sram_ctrl_mbox.ram + ] + mbx6.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_jtag.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie1.sram: + [ + sram_ctrl_mbox.ram + ] + } + nodes: + [ + { + name: peri + type: device + clock: clk_fixed_i + reset: rst_fixed_ni + req_fifo_pass: false + rsp_fifo_pass: false + xbar: true + stub: false + pipeline: true + addr_space: hart + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x800000 + } + ] + } + { + name: soc_proxy.ctn + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: soc_proxy + addr_range: + [ + { + base_addrs: + { + hart: 0x40000000 + } + size_byte: 0x40000000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: hmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: hmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21110000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: kmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: kmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21120000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: aes + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: aes + addr_range: + [ + { + base_addrs: + { + hart: 0x21100000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: otbn + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: otbn + addr_range: + [ + { + base_addrs: + { + hart: 0x21130000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: keymgr_dpe + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: keymgr_dpe + addr_range: + [ + { + base_addrs: + { + hart: 0x21140000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: sram_ctrl_main.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x10000000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_mbox.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x11000000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: dma.host + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx2.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx3.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx4.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx5.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx6.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_jtag.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_main_i + type: xbar + inter_signal_list: + [ + { + name: tl_dma__host + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_dma__host + index: -1 + } + { + name: tl_mbx0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx0__sram + index: -1 + } + { + name: tl_mbx1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx1__sram + index: -1 + } + { + name: tl_mbx2__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx2__sram + index: -1 + } + { + name: tl_mbx3__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx3__sram + index: -1 + } + { + name: tl_mbx4__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx4__sram + index: -1 + } + { + name: tl_mbx5__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx5__sram + index: -1 + } + { + name: tl_mbx6__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx6__sram + index: -1 + } + { + name: tl_mbx_jtag__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx_jtag__sram + index: -1 + } + { + name: tl_mbx_pcie0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie0__sram + index: -1 + } + { + name: tl_mbx_pcie1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_mbx_pcie1__sram + index: -1 + } + { + name: tl_peri + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + end_idx: -1 + top_signame: main_tl_peri + index: -1 + } + { + name: tl_soc_proxy__ctn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: soc_proxy_ctn_tl + index: -1 + } + { + name: tl_hmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: hmac_tl + index: -1 + } + { + name: tl_kmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: kmac_tl + index: -1 + } + { + name: tl_aes + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: aes_tl + index: -1 + } + { + name: tl_otbn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: otbn_tl + index: -1 + } + { + name: tl_keymgr_dpe + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: keymgr_dpe_tl + index: -1 + } + { + name: tl_sram_ctrl_main__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + { + name: tl_sram_ctrl_mbox__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main + width: 1 + default: "" + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_main/data/autogen/xbar_main.hjson new file mode 100644 index 00000000000..e8fd27df3fd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/data/autogen/xbar_main.hjson @@ -0,0 +1,137 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_main" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_dma__host" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx0__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx1__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx2__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx3__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx4__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx5__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx6__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_jtag__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie0__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie1__sram" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_peri" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_soc_proxy__ctn" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_hmac" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_kmac" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_aes" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_otbn" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_keymgr_dpe" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_main__ram" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_mbox__ram" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 00000000000..6cda2c3160a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,41 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_main dut(); + +`DRIVE_CLK(clk_main_i) +`DRIVE_CLK(clk_fixed_i) + +initial force dut.clk_main_i = clk_main_i; +initial force dut.clk_fixed_i = clk_fixed_i; + +// TODO, all resets tie together +initial force dut.rst_main_ni = rst_n; +initial force dut.rst_fixed_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(dma__host, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx0__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx1__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx2__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx3__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx4__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx5__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx6__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx_jtag__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx_pcie0__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx_pcie1__sram, dut, clk_main_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(peri, dut, clk_fixed_i, rst_n) +`CONNECT_TL_DEVICE_IF(soc_proxy__ctn, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(hmac, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(kmac, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(aes, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(otbn, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(keymgr_dpe, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_main__ram, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_mbox__ram, dut, clk_main_i, rst_n) diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_cov_excl.el new file mode 100644 index 00000000000..70f12b332fa --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_main +Block 1 "0" "assign unused_scanmode = scanmode_i;" + +ANNOTATION: "[UNR]" +MODULE: prim_fifo_sync +Branch 2 "2323268504" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-" +Branch 3 "3736627057" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-" + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=2,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=3,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=4,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=5,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=6,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=7,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=8,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=9,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=10,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=11,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_cover.cfg new file mode 100644 index 00000000000..2e1118599c5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_peri_o.a_address[27:23] +-node tb.dut tl_peri_o.a_address[31:30] +-node tb.dut tl_soc_proxy__ctn_o.a_address[31:31] +-node tb.dut tl_hmac_o.a_address[15:13] +-node tb.dut tl_hmac_o.a_address[19:17] +-node tb.dut tl_hmac_o.a_address[23:21] +-node tb.dut tl_hmac_o.a_address[28:25] +-node tb.dut tl_hmac_o.a_address[31:30] +-node tb.dut tl_kmac_o.a_address[16:12] +-node tb.dut tl_kmac_o.a_address[19:18] +-node tb.dut tl_kmac_o.a_address[23:21] +-node tb.dut tl_kmac_o.a_address[28:25] +-node tb.dut tl_kmac_o.a_address[31:30] +-node tb.dut tl_aes_o.a_address[19:8] +-node tb.dut tl_aes_o.a_address[23:21] +-node tb.dut tl_aes_o.a_address[28:25] +-node tb.dut tl_aes_o.a_address[31:30] +-node tb.dut tl_otbn_o.a_address[19:18] +-node tb.dut tl_otbn_o.a_address[23:21] +-node tb.dut tl_otbn_o.a_address[28:25] +-node tb.dut tl_otbn_o.a_address[31:30] +-node tb.dut tl_keymgr_dpe_o.a_address[17:8] +-node tb.dut tl_keymgr_dpe_o.a_address[19:19] +-node tb.dut tl_keymgr_dpe_o.a_address[23:21] +-node tb.dut tl_keymgr_dpe_o.a_address[28:25] +-node tb.dut tl_keymgr_dpe_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_main__ram_o.a_address[27:16] +-node tb.dut tl_sram_ctrl_main__ram_o.a_address[31:29] +-node tb.dut tl_sram_ctrl_mbox__ram_o.a_address[23:12] +-node tb.dut tl_sram_ctrl_mbox__ram_o.a_address[27:25] +-node tb.dut tl_sram_ctrl_mbox__ram_o.a_address[31:29] + +-node tb.dut tl_*.a_source[7:4] +-node tb.dut tl_*.d_source[7:4] +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 00000000000..0220b9a93c0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,80 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"peri", '{ + '{32'h30000000, 32'h307fffff} + }}, + '{"soc_proxy__ctn", '{ + '{32'h40000000, 32'h7fffffff} + }}, + '{"hmac", '{ + '{32'h21110000, 32'h21111fff} + }}, + '{"kmac", '{ + '{32'h21120000, 32'h21120fff} + }}, + '{"aes", '{ + '{32'h21100000, 32'h211000ff} + }}, + '{"otbn", '{ + '{32'h21130000, 32'h2113ffff} + }}, + '{"keymgr_dpe", '{ + '{32'h21140000, 32'h211400ff} + }}, + '{"sram_ctrl_main__ram", '{ + '{32'h10000000, 32'h1000ffff} + }}, + '{"sram_ctrl_mbox__ram", '{ + '{32'h11000000, 32'h11000fff} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"dma__host", 0, '{ + "sram_ctrl_main__ram", + "sram_ctrl_mbox__ram", + "aes", + "hmac", + "otbn", + "keymgr_dpe", + "kmac", + "soc_proxy__ctn", + "peri"}} + , + '{"mbx0__sram", 1, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx1__sram", 2, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx2__sram", 3, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx3__sram", 4, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx4__sram", 5, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx5__sram", 6, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx6__sram", 7, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_jtag__sram", 8, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie0__sram", 9, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie1__sram", 10, '{ + "sram_ctrl_mbox__ram"}} +}; diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_bind.core b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_bind.core new file mode 100644 index 00000000000..58eb6d3af77 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_main_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_main_bind:0.1" +description: "XBAR main assertion bind" +filesets: + files_dv: + files: + - xbar_main_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_bind.sv new file mode 100644 index 00000000000..bb2d098af3b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_bind.sv @@ -0,0 +1,132 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main_bind module generated by `tlgen.py` tool for assertions +module xbar_main_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_dma__host ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_dma__host_i), + .d2h (tl_dma__host_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx0__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx0__sram_i), + .d2h (tl_mbx0__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx1__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx1__sram_i), + .d2h (tl_mbx1__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx2__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx2__sram_i), + .d2h (tl_mbx2__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx3__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx3__sram_i), + .d2h (tl_mbx3__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx4__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx4__sram_i), + .d2h (tl_mbx4__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx5__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx5__sram_i), + .d2h (tl_mbx5__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx6__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx6__sram_i), + .d2h (tl_mbx6__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx_jtag__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_jtag__sram_i), + .d2h (tl_mbx_jtag__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx_pcie0__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie0__sram_i), + .d2h (tl_mbx_pcie0__sram_o) + ); + bind xbar_main tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx_pcie1__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie1__sram_i), + .d2h (tl_mbx_pcie1__sram_o) + ); + + // Device interfaces + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_peri ( + .clk_i (clk_fixed_i), + .rst_ni (rst_fixed_ni), + .h2d (tl_peri_o), + .d2h (tl_peri_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_soc_proxy__ctn ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_soc_proxy__ctn_o), + .d2h (tl_soc_proxy__ctn_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_hmac ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_hmac_o), + .d2h (tl_hmac_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_kmac ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_kmac_o), + .d2h (tl_kmac_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_aes ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_aes_o), + .d2h (tl_aes_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_otbn ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_otbn_o), + .d2h (tl_otbn_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_keymgr_dpe ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_keymgr_dpe_o), + .d2h (tl_keymgr_dpe_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_main__ram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_main__ram_o), + .d2h (tl_sram_ctrl_main__ram_i) + ); + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_mbox__ram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_mbox__ram_o), + .d2h (tl_sram_ctrl_mbox__ram_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_sim.core b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_sim.core new file mode 100644 index 00000000000..7da90452961 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_main_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_main_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling_no_ibex:xbar_main + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_no_ibex_xbar_main_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson new file mode 100644 index 00000000000..5b725aae127 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/dv/autogen/xbar_main_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_main + + // Top level dut name (sv module). + dut: xbar_main + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling_no_ibex + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main/rtl/autogen/tl_main_pkg.sv new file mode 100644 index 00000000000..00d79003479 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_main package generated by `tlgen.py` tool + +package tl_main_pkg; + + localparam logic [0:0][31:0] ADDR_SPACE_PERI = { + 32'h 30000000 + }; + localparam logic [31:0] ADDR_SPACE_SOC_PROXY__CTN = 32'h 40000000; + localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 21110000; + localparam logic [31:0] ADDR_SPACE_KMAC = 32'h 21120000; + localparam logic [31:0] ADDR_SPACE_AES = 32'h 21100000; + localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 21130000; + localparam logic [31:0] ADDR_SPACE_KEYMGR_DPE = 32'h 21140000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__RAM = 32'h 10000000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MBOX__RAM = 32'h 11000000; + + localparam logic [0:0][31:0] ADDR_MASK_PERI = { + 32'h 007fffff + }; + localparam logic [31:0] ADDR_MASK_SOC_PROXY__CTN = 32'h 3fffffff; + localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00001fff; + localparam logic [31:0] ADDR_MASK_KMAC = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_AES = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0000ffff; + localparam logic [31:0] ADDR_MASK_KEYMGR_DPE = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__RAM = 32'h 0000ffff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MBOX__RAM = 32'h 00000fff; + + localparam int N_HOST = 11; + localparam int N_DEVICE = 9; + + typedef enum int { + TlPeri = 0, + TlSocProxyCtn = 1, + TlHmac = 2, + TlKmac = 3, + TlAes = 4, + TlOtbn = 5, + TlKeymgrDpe = 6, + TlSramCtrlMainRam = 7, + TlSramCtrlMboxRam = 8 + } tl_device_e; + + typedef enum int { + TlDmaHost = 0, + TlMbx0Sram = 1, + TlMbx1Sram = 2, + TlMbx2Sram = 3, + TlMbx3Sram = 4, + TlMbx4Sram = 5, + TlMbx5Sram = 6, + TlMbx6Sram = 7, + TlMbxJtagSram = 8, + TlMbxPcie0Sram = 9, + TlMbxPcie1Sram = 10 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main/rtl/autogen/xbar_main.sv new file mode 100644 index 00000000000..e58a1fa7e62 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/rtl/autogen/xbar_main.sv @@ -0,0 +1,672 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// dma.host +// -> s1n_20 +// -> sram_ctrl_main.ram +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// -> aes +// -> hmac +// -> otbn +// -> keymgr_dpe +// -> kmac +// -> soc_proxy.ctn +// -> asf_22 +// -> peri +// mbx0.sram +// -> s1n_23 +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// mbx1.sram +// -> s1n_24 +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// mbx2.sram +// -> s1n_25 +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// mbx3.sram +// -> s1n_26 +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// mbx4.sram +// -> s1n_27 +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// mbx5.sram +// -> s1n_28 +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// mbx6.sram +// -> s1n_29 +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// mbx_jtag.sram +// -> s1n_30 +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// mbx_pcie0.sram +// -> s1n_31 +// -> sm1_21 +// -> sram_ctrl_mbox.ram +// mbx_pcie1.sram +// -> s1n_32 +// -> sm1_21 +// -> sram_ctrl_mbox.ram + +module xbar_main ( + input clk_main_i, + input clk_fixed_i, + input rst_main_ni, + input rst_fixed_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_dma__host_i, + output tlul_pkg::tl_d2h_t tl_dma__host_o, + input tlul_pkg::tl_h2d_t tl_mbx0__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx0__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx1__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx1__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx2__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx2__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx3__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx3__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx4__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx4__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx5__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx5__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx6__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx6__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx_jtag__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx_jtag__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx_pcie0__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx_pcie0__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx_pcie1__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx_pcie1__sram_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_peri_o, + input tlul_pkg::tl_d2h_t tl_peri_i, + output tlul_pkg::tl_h2d_t tl_soc_proxy__ctn_o, + input tlul_pkg::tl_d2h_t tl_soc_proxy__ctn_i, + output tlul_pkg::tl_h2d_t tl_hmac_o, + input tlul_pkg::tl_d2h_t tl_hmac_i, + output tlul_pkg::tl_h2d_t tl_kmac_o, + input tlul_pkg::tl_d2h_t tl_kmac_i, + output tlul_pkg::tl_h2d_t tl_aes_o, + input tlul_pkg::tl_d2h_t tl_aes_i, + output tlul_pkg::tl_h2d_t tl_otbn_o, + input tlul_pkg::tl_d2h_t tl_otbn_i, + output tlul_pkg::tl_h2d_t tl_keymgr_dpe_o, + input tlul_pkg::tl_d2h_t tl_keymgr_dpe_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_main__ram_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_main__ram_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_mbox__ram_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_mbox__ram_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_main_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_20_us_h2d ; + tl_d2h_t tl_s1n_20_us_d2h ; + + + tl_h2d_t tl_s1n_20_ds_h2d [9]; + tl_d2h_t tl_s1n_20_ds_d2h [9]; + + // Create steering signal + logic [3:0] dev_sel_s1n_20; + + + tl_h2d_t tl_sm1_21_us_h2d [11]; + tl_d2h_t tl_sm1_21_us_d2h [11]; + + tl_h2d_t tl_sm1_21_ds_h2d ; + tl_d2h_t tl_sm1_21_ds_d2h ; + + tl_h2d_t tl_asf_22_us_h2d ; + tl_d2h_t tl_asf_22_us_d2h ; + tl_h2d_t tl_asf_22_ds_h2d ; + tl_d2h_t tl_asf_22_ds_d2h ; + + tl_h2d_t tl_s1n_23_us_h2d ; + tl_d2h_t tl_s1n_23_us_d2h ; + + + tl_h2d_t tl_s1n_23_ds_h2d [1]; + tl_d2h_t tl_s1n_23_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_23; + + tl_h2d_t tl_s1n_24_us_h2d ; + tl_d2h_t tl_s1n_24_us_d2h ; + + + tl_h2d_t tl_s1n_24_ds_h2d [1]; + tl_d2h_t tl_s1n_24_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_24; + + tl_h2d_t tl_s1n_25_us_h2d ; + tl_d2h_t tl_s1n_25_us_d2h ; + + + tl_h2d_t tl_s1n_25_ds_h2d [1]; + tl_d2h_t tl_s1n_25_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_25; + + tl_h2d_t tl_s1n_26_us_h2d ; + tl_d2h_t tl_s1n_26_us_d2h ; + + + tl_h2d_t tl_s1n_26_ds_h2d [1]; + tl_d2h_t tl_s1n_26_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_26; + + tl_h2d_t tl_s1n_27_us_h2d ; + tl_d2h_t tl_s1n_27_us_d2h ; + + + tl_h2d_t tl_s1n_27_ds_h2d [1]; + tl_d2h_t tl_s1n_27_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_27; + + tl_h2d_t tl_s1n_28_us_h2d ; + tl_d2h_t tl_s1n_28_us_d2h ; + + + tl_h2d_t tl_s1n_28_ds_h2d [1]; + tl_d2h_t tl_s1n_28_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_28; + + tl_h2d_t tl_s1n_29_us_h2d ; + tl_d2h_t tl_s1n_29_us_d2h ; + + + tl_h2d_t tl_s1n_29_ds_h2d [1]; + tl_d2h_t tl_s1n_29_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_29; + + tl_h2d_t tl_s1n_30_us_h2d ; + tl_d2h_t tl_s1n_30_us_d2h ; + + + tl_h2d_t tl_s1n_30_ds_h2d [1]; + tl_d2h_t tl_s1n_30_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_30; + + tl_h2d_t tl_s1n_31_us_h2d ; + tl_d2h_t tl_s1n_31_us_d2h ; + + + tl_h2d_t tl_s1n_31_ds_h2d [1]; + tl_d2h_t tl_s1n_31_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_31; + + tl_h2d_t tl_s1n_32_us_h2d ; + tl_d2h_t tl_s1n_32_us_d2h ; + + + tl_h2d_t tl_s1n_32_ds_h2d [1]; + tl_d2h_t tl_s1n_32_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_32; + + + + assign tl_sram_ctrl_main__ram_o = tl_s1n_20_ds_h2d[0]; + assign tl_s1n_20_ds_d2h[0] = tl_sram_ctrl_main__ram_i; + + assign tl_sm1_21_us_h2d[0] = tl_s1n_20_ds_h2d[1]; + assign tl_s1n_20_ds_d2h[1] = tl_sm1_21_us_d2h[0]; + + assign tl_aes_o = tl_s1n_20_ds_h2d[2]; + assign tl_s1n_20_ds_d2h[2] = tl_aes_i; + + assign tl_hmac_o = tl_s1n_20_ds_h2d[3]; + assign tl_s1n_20_ds_d2h[3] = tl_hmac_i; + + assign tl_otbn_o = tl_s1n_20_ds_h2d[4]; + assign tl_s1n_20_ds_d2h[4] = tl_otbn_i; + + assign tl_keymgr_dpe_o = tl_s1n_20_ds_h2d[5]; + assign tl_s1n_20_ds_d2h[5] = tl_keymgr_dpe_i; + + assign tl_kmac_o = tl_s1n_20_ds_h2d[6]; + assign tl_s1n_20_ds_d2h[6] = tl_kmac_i; + + assign tl_soc_proxy__ctn_o = tl_s1n_20_ds_h2d[7]; + assign tl_s1n_20_ds_d2h[7] = tl_soc_proxy__ctn_i; + + assign tl_asf_22_us_h2d = tl_s1n_20_ds_h2d[8]; + assign tl_s1n_20_ds_d2h[8] = tl_asf_22_us_d2h; + + assign tl_sm1_21_us_h2d[1] = tl_s1n_23_ds_h2d[0]; + assign tl_s1n_23_ds_d2h[0] = tl_sm1_21_us_d2h[1]; + + assign tl_sm1_21_us_h2d[2] = tl_s1n_24_ds_h2d[0]; + assign tl_s1n_24_ds_d2h[0] = tl_sm1_21_us_d2h[2]; + + assign tl_sm1_21_us_h2d[3] = tl_s1n_25_ds_h2d[0]; + assign tl_s1n_25_ds_d2h[0] = tl_sm1_21_us_d2h[3]; + + assign tl_sm1_21_us_h2d[4] = tl_s1n_26_ds_h2d[0]; + assign tl_s1n_26_ds_d2h[0] = tl_sm1_21_us_d2h[4]; + + assign tl_sm1_21_us_h2d[5] = tl_s1n_27_ds_h2d[0]; + assign tl_s1n_27_ds_d2h[0] = tl_sm1_21_us_d2h[5]; + + assign tl_sm1_21_us_h2d[6] = tl_s1n_28_ds_h2d[0]; + assign tl_s1n_28_ds_d2h[0] = tl_sm1_21_us_d2h[6]; + + assign tl_sm1_21_us_h2d[7] = tl_s1n_29_ds_h2d[0]; + assign tl_s1n_29_ds_d2h[0] = tl_sm1_21_us_d2h[7]; + + assign tl_sm1_21_us_h2d[8] = tl_s1n_30_ds_h2d[0]; + assign tl_s1n_30_ds_d2h[0] = tl_sm1_21_us_d2h[8]; + + assign tl_sm1_21_us_h2d[9] = tl_s1n_31_ds_h2d[0]; + assign tl_s1n_31_ds_d2h[0] = tl_sm1_21_us_d2h[9]; + + assign tl_sm1_21_us_h2d[10] = tl_s1n_32_ds_h2d[0]; + assign tl_s1n_32_ds_d2h[0] = tl_sm1_21_us_d2h[10]; + + assign tl_s1n_20_us_h2d = tl_dma__host_i; + assign tl_dma__host_o = tl_s1n_20_us_d2h; + + assign tl_sram_ctrl_mbox__ram_o = tl_sm1_21_ds_h2d; + assign tl_sm1_21_ds_d2h = tl_sram_ctrl_mbox__ram_i; + + assign tl_peri_o = tl_asf_22_ds_h2d; + assign tl_asf_22_ds_d2h = tl_peri_i; + + assign tl_s1n_23_us_h2d = tl_mbx0__sram_i; + assign tl_mbx0__sram_o = tl_s1n_23_us_d2h; + + assign tl_s1n_24_us_h2d = tl_mbx1__sram_i; + assign tl_mbx1__sram_o = tl_s1n_24_us_d2h; + + assign tl_s1n_25_us_h2d = tl_mbx2__sram_i; + assign tl_mbx2__sram_o = tl_s1n_25_us_d2h; + + assign tl_s1n_26_us_h2d = tl_mbx3__sram_i; + assign tl_mbx3__sram_o = tl_s1n_26_us_d2h; + + assign tl_s1n_27_us_h2d = tl_mbx4__sram_i; + assign tl_mbx4__sram_o = tl_s1n_27_us_d2h; + + assign tl_s1n_28_us_h2d = tl_mbx5__sram_i; + assign tl_mbx5__sram_o = tl_s1n_28_us_d2h; + + assign tl_s1n_29_us_h2d = tl_mbx6__sram_i; + assign tl_mbx6__sram_o = tl_s1n_29_us_d2h; + + assign tl_s1n_30_us_h2d = tl_mbx_jtag__sram_i; + assign tl_mbx_jtag__sram_o = tl_s1n_30_us_d2h; + + assign tl_s1n_31_us_h2d = tl_mbx_pcie0__sram_i; + assign tl_mbx_pcie0__sram_o = tl_s1n_31_us_d2h; + + assign tl_s1n_32_us_h2d = tl_mbx_pcie1__sram_i; + assign tl_mbx_pcie1__sram_o = tl_s1n_32_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_20 = 4'd9; + if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin + dev_sel_s1n_20 = 4'd0; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_20 = 4'd1; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_20 = 4'd2; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_20 = 4'd3; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + dev_sel_s1n_20 = 4'd4; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_KEYMGR_DPE)) == ADDR_SPACE_KEYMGR_DPE) begin + dev_sel_s1n_20 = 4'd5; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin + dev_sel_s1n_20 = 4'd6; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin + dev_sel_s1n_20 = 4'd7; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin + dev_sel_s1n_20 = 4'd8; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_23 = 1'd1; + if ((tl_s1n_23_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_23 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_24 = 1'd1; + if ((tl_s1n_24_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_24 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_25 = 1'd1; + if ((tl_s1n_25_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_25 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_26 = 1'd1; + if ((tl_s1n_26_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_26 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_27 = 1'd1; + if ((tl_s1n_27_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_27 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_28 = 1'd1; + if ((tl_s1n_28_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_28 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_29 = 1'd1; + if ((tl_s1n_29_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_29 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_30 = 1'd1; + if ((tl_s1n_30_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_30 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_31 = 1'd1; + if ((tl_s1n_31_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_31 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_32 = 1'd1; + if ((tl_s1n_32_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_32 = 1'd0; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqPass (9'h183), + .DRspPass (9'h183), + .DReqDepth (36'h1111100), + .DRspDepth (36'h1111100), + .N (9) + ) u_s1n_20 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_20_us_h2d), + .tl_h_o (tl_s1n_20_us_d2h), + .tl_d_o (tl_s1n_20_ds_h2d), + .tl_d_i (tl_s1n_20_ds_d2h), + .dev_select_i (dev_sel_s1n_20) + ); + tlul_socket_m1 #( + .HReqDepth (44'h0), + .HRspDepth (44'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (11) + ) u_sm1_21 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_21_us_h2d), + .tl_h_o (tl_sm1_21_us_d2h), + .tl_d_o (tl_sm1_21_ds_h2d), + .tl_d_i (tl_sm1_21_ds_d2h) + ); + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_22 ( + .clk_h_i (clk_main_i), + .rst_h_ni (rst_main_ni), + .clk_d_i (clk_fixed_i), + .rst_d_ni (rst_fixed_ni), + .tl_h_i (tl_asf_22_us_h2d), + .tl_h_o (tl_asf_22_us_d2h), + .tl_d_o (tl_asf_22_ds_h2d), + .tl_d_i (tl_asf_22_ds_d2h) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_23 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_23_us_h2d), + .tl_h_o (tl_s1n_23_us_d2h), + .tl_d_o (tl_s1n_23_ds_h2d), + .tl_d_i (tl_s1n_23_ds_d2h), + .dev_select_i (dev_sel_s1n_23) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_24 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_24_us_h2d), + .tl_h_o (tl_s1n_24_us_d2h), + .tl_d_o (tl_s1n_24_ds_h2d), + .tl_d_i (tl_s1n_24_ds_d2h), + .dev_select_i (dev_sel_s1n_24) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_25 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_25_us_h2d), + .tl_h_o (tl_s1n_25_us_d2h), + .tl_d_o (tl_s1n_25_ds_h2d), + .tl_d_i (tl_s1n_25_ds_d2h), + .dev_select_i (dev_sel_s1n_25) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_26 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_26_us_h2d), + .tl_h_o (tl_s1n_26_us_d2h), + .tl_d_o (tl_s1n_26_ds_h2d), + .tl_d_i (tl_s1n_26_ds_d2h), + .dev_select_i (dev_sel_s1n_26) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_27 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_27_us_h2d), + .tl_h_o (tl_s1n_27_us_d2h), + .tl_d_o (tl_s1n_27_ds_h2d), + .tl_d_i (tl_s1n_27_ds_d2h), + .dev_select_i (dev_sel_s1n_27) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_28 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_28_us_h2d), + .tl_h_o (tl_s1n_28_us_d2h), + .tl_d_o (tl_s1n_28_ds_h2d), + .tl_d_i (tl_s1n_28_ds_d2h), + .dev_select_i (dev_sel_s1n_28) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_29 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_29_us_h2d), + .tl_h_o (tl_s1n_29_us_d2h), + .tl_d_o (tl_s1n_29_ds_h2d), + .tl_d_i (tl_s1n_29_ds_d2h), + .dev_select_i (dev_sel_s1n_29) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_30 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_30_us_h2d), + .tl_h_o (tl_s1n_30_us_d2h), + .tl_d_o (tl_s1n_30_ds_h2d), + .tl_d_i (tl_s1n_30_ds_d2h), + .dev_select_i (dev_sel_s1n_30) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_31 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_31_us_h2d), + .tl_h_o (tl_s1n_31_us_d2h), + .tl_d_o (tl_s1n_31_ds_h2d), + .tl_d_i (tl_s1n_31_ds_d2h), + .dev_select_i (dev_sel_s1n_31) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_32 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_32_us_h2d), + .tl_h_o (tl_s1n_32_us_d2h), + .tl_d_o (tl_s1n_32_ds_h2d), + .tl_d_i (tl_s1n_32_ds_d2h), + .dev_select_i (dev_sel_s1n_32) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main/xbar_main.core b/hw/top_darjeeling_no_ibex/ip/xbar_main/xbar_main.core new file mode 100644 index 00000000000..ab47b08f08e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main/xbar_main.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_main core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling_no_ibex:xbar_main:0.1" +description: "Generated RTL xbar_main" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_main_pkg.sv + - rtl/autogen/xbar_main.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_main diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/data/autogen/xbar_main_no_ibex.gen.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/data/autogen/xbar_main_no_ibex.gen.hjson new file mode 100644 index 00000000000..3f03b9ad53e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/data/autogen/xbar_main_no_ibex.gen.hjson @@ -0,0 +1,1609 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson -o hw/top_darjeeling_no_ibex/ + +{ + name: main_no_ibex + clock_srcs: + { + clk_main_i: main + clk_fixed_i: io_div4 + } + clock_group: infra + reset: rst_main_ni + reset_connections: + { + rst_main_ni: + { + name: lc + domain: "0" + } + rst_fixed_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_main_i: clkmgr_aon_clocks.clk_main_infra + clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + rv_dm.sba: + [ + rom_ctrl0.rom + rom_ctrl0.regs + rom_ctrl1.rom + rom_ctrl1.regs + rv_dm.mem + rv_dm.regs + sram_ctrl_main.ram + peri_no_ibex + aes + entropy_src + csrng + edn0 + edn1 + hmac + rv_plic + otbn + keymgr_dpe + kmac + sram_ctrl_main.regs + sram_ctrl_mbox.ram + sram_ctrl_mbox.regs + soc_proxy.ctn + soc_proxy.core + dma + mbx0.core + mbx1.core + mbx2.core + mbx3.core + mbx4.core + mbx5.core + mbx6.core + mbx_jtag.core + mbx_pcie0.core + mbx_pcie1.core + ] + dma.host: + [ + sram_ctrl_main.ram + sram_ctrl_mbox.ram + aes + hmac + otbn + keymgr_dpe + kmac + soc_proxy.ctn + peri_no_ibex + ] + mbx0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx1.sram: + [ + sram_ctrl_mbox.ram + ] + mbx2.sram: + [ + sram_ctrl_mbox.ram + ] + mbx3.sram: + [ + sram_ctrl_mbox.ram + ] + mbx4.sram: + [ + sram_ctrl_mbox.ram + ] + mbx5.sram: + [ + sram_ctrl_mbox.ram + ] + mbx6.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_jtag.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie0.sram: + [ + sram_ctrl_mbox.ram + ] + mbx_pcie1.sram: + [ + sram_ctrl_mbox.ram + ] + } + nodes: + [ + { + name: rv_dm.sba + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + xbar: false + stub: false + inst_type: "" + pipeline: true + } + { + name: rv_dm.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rv_dm + addr_range: + [ + { + base_addrs: + { + hart: 0x21200000 + } + size_byte: 0x10 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rv_dm.mem + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rv_dm + addr_range: + [ + { + base_addrs: + { + hart: 0x40000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl0.rom + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: true + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x8000 + } + size_byte: 0x8000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl0.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211e0000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl1.rom + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: true + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x20000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rom_ctrl1.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: rom_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211e1000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: peri_no_ibex + type: device + clock: clk_fixed_i + reset: rst_fixed_ni + req_fifo_pass: false + rsp_fifo_pass: false + xbar: true + stub: false + pipeline: true + addr_space: hart + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x800000 + } + ] + } + { + name: soc_proxy.core + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: soc_proxy + addr_range: + [ + { + base_addrs: + { + hart: 0x22030000 + } + size_byte: 0x10 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: soc_proxy.ctn + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: soc_proxy + addr_range: + [ + { + base_addrs: + { + hart: 0x40000000 + } + size_byte: 0x40000000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: hmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: hmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21110000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: kmac + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: kmac + addr_range: + [ + { + base_addrs: + { + hart: 0x21120000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: aes + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: aes + addr_range: + [ + { + base_addrs: + { + hart: 0x21100000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: entropy_src + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: entropy_src + addr_range: + [ + { + base_addrs: + { + hart: 0x21160000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: csrng + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: csrng + addr_range: + [ + { + base_addrs: + { + hart: 0x21150000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: edn0 + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: edn + addr_range: + [ + { + base_addrs: + { + hart: 0x21170000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: edn1 + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: edn + addr_range: + [ + { + base_addrs: + { + hart: 0x21180000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: rv_plic + type: device + clock: clk_main_i + reset: rst_main_ni + inst_type: rv_plic + req_fifo_pass: false + rsp_fifo_pass: false + addr_range: + [ + { + base_addrs: + { + hart: 0x28000000 + } + size_byte: 0x8000000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: otbn + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: otbn + addr_range: + [ + { + base_addrs: + { + hart: 0x21130000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: keymgr_dpe + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: keymgr_dpe + addr_range: + [ + { + base_addrs: + { + hart: 0x21140000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: sram_ctrl_main.regs + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211c0000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: sram_ctrl_main.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x10000000 + } + size_byte: 0x10000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_mbox.regs + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x211d0000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_mbox.ram + type: device + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x11000000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: dma + type: device + clock: clk_main_i + reset: rst_main_ni + req_fifo_pass: false + rsp_fifo_pass: false + inst_type: dma + addr_range: + [ + { + base_addrs: + { + hart: 0x22010000 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + pipeline: true + } + { + name: dma.host + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx0.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx1.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000100 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx2.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000200 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx2.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx3.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000300 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx3.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx4.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000400 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx4.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx5.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000500 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx5.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx6.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000600 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx6.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_jtag.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22000800 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_jtag.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie0.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22040000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie0.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx_pcie1.core + type: device + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + hart: 0x22040100 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie1.sram + type: host + addr_space: hart + clock: clk_main_i + reset: rst_main_ni + pipeline: false + xbar: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_main_i + type: xbar + inter_signal_list: + [ + { + name: tl_rv_dm__sba + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_rv_dm__sba + index: -1 + } + { + name: tl_dma__host + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_dma__host + index: -1 + } + { + name: tl_mbx0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx0__sram + index: -1 + } + { + name: tl_mbx1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx1__sram + index: -1 + } + { + name: tl_mbx2__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx2__sram + index: -1 + } + { + name: tl_mbx3__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx3__sram + index: -1 + } + { + name: tl_mbx4__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx4__sram + index: -1 + } + { + name: tl_mbx5__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx5__sram + index: -1 + } + { + name: tl_mbx6__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx6__sram + index: -1 + } + { + name: tl_mbx_jtag__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx_jtag__sram + index: -1 + } + { + name: tl_mbx_pcie0__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx_pcie0__sram + index: -1 + } + { + name: tl_mbx_pcie1__sram + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_mbx_pcie1__sram + index: -1 + } + { + name: tl_rv_dm__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: rv_dm_regs_tl_d + index: -1 + } + { + name: tl_rv_dm__mem + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: rv_dm_mem_tl_d + index: -1 + } + { + name: tl_rom_ctrl0__rom + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: rom_ctrl0_rom_tl + index: -1 + } + { + name: tl_rom_ctrl0__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: rom_ctrl0_regs_tl + index: -1 + } + { + name: tl_rom_ctrl1__rom + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: rom_ctrl1_rom_tl + index: -1 + } + { + name: tl_rom_ctrl1__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: rom_ctrl1_regs_tl + index: -1 + } + { + name: tl_peri_no_ibex + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + end_idx: -1 + top_signame: main_no_ibex_tl_peri_no_ibex + index: -1 + } + { + name: tl_soc_proxy__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: soc_proxy_core_tl + index: -1 + } + { + name: tl_soc_proxy__ctn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: soc_proxy_ctn_tl + index: -1 + } + { + name: tl_hmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: hmac_tl + index: -1 + } + { + name: tl_kmac + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: kmac_tl + index: -1 + } + { + name: tl_aes + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: aes_tl + index: -1 + } + { + name: tl_entropy_src + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: entropy_src_tl + index: -1 + } + { + name: tl_csrng + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: csrng_tl + index: -1 + } + { + name: tl_edn0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: edn0_tl + index: -1 + } + { + name: tl_edn1 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: edn1_tl + index: -1 + } + { + name: tl_rv_plic + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: rv_plic_tl + index: -1 + } + { + name: tl_otbn + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: otbn_tl + index: -1 + } + { + name: tl_keymgr_dpe + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: keymgr_dpe_tl + index: -1 + } + { + name: tl_sram_ctrl_main__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: sram_ctrl_main_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_main__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: sram_ctrl_main_ram_tl + index: -1 + } + { + name: tl_sram_ctrl_mbox__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: sram_ctrl_mbox_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_mbox__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: sram_ctrl_mbox_ram_tl + index: -1 + } + { + name: tl_dma + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: dma_tl_d + index: -1 + } + { + name: tl_mbx0__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx0_core_tl_d + index: -1 + } + { + name: tl_mbx1__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx1_core_tl_d + index: -1 + } + { + name: tl_mbx2__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx2_core_tl_d + index: -1 + } + { + name: tl_mbx3__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx3_core_tl_d + index: -1 + } + { + name: tl_mbx4__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx4_core_tl_d + index: -1 + } + { + name: tl_mbx5__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx5_core_tl_d + index: -1 + } + { + name: tl_mbx6__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx6_core_tl_d + index: -1 + } + { + name: tl_mbx_jtag__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx_jtag_core_tl_d + index: -1 + } + { + name: tl_mbx_pcie0__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx_pcie0_core_tl_d + index: -1 + } + { + name: tl_mbx_pcie1__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: main_no_ibex + width: 1 + default: "" + top_signame: mbx_pcie1_core_tl_d + index: -1 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/data/autogen/xbar_main_no_ibex.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/data/autogen/xbar_main_no_ibex.hjson new file mode 100644 index 00000000000..89cce2b8d78 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/data/autogen/xbar_main_no_ibex.hjson @@ -0,0 +1,293 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main_no_ibex comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_main_no_ibex" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_rv_dm__sba" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_dma__host" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx0__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx1__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx2__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx3__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx4__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx5__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx6__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_jtag__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie0__sram" + act: "rsp" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie1__sram" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_rv_dm__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_dm__mem" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rom_ctrl0__rom" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rom_ctrl0__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rom_ctrl1__rom" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rom_ctrl1__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_peri_no_ibex" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_soc_proxy__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_soc_proxy__ctn" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_hmac" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_kmac" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_aes" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_entropy_src" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_csrng" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_edn0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_edn1" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_plic" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_otbn" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_keymgr_dpe" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_main__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_main__ram" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_mbox__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_mbox__ram" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_dma" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx0__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx1__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx2__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx3__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx4__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx5__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx6__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_jtag__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie0__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie1__core" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 00000000000..fa2ff282505 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,67 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_main_no_ibex dut(); + +`DRIVE_CLK(clk_main_i) +`DRIVE_CLK(clk_fixed_i) + +initial force dut.clk_main_i = clk_main_i; +initial force dut.clk_fixed_i = clk_fixed_i; + +// TODO, all resets tie together +initial force dut.rst_main_ni = rst_n; +initial force dut.rst_fixed_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(rv_dm__sba, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(dma__host, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx0__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx1__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx2__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx3__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx4__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx5__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx6__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx_jtag__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx_pcie0__sram, dut, clk_main_i, rst_n) +`CONNECT_TL_HOST_IF(mbx_pcie1__sram, dut, clk_main_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(rv_dm__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rv_dm__mem, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rom_ctrl0__rom, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rom_ctrl0__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rom_ctrl1__rom, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rom_ctrl1__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(peri_no_ibex, dut, clk_fixed_i, rst_n) +`CONNECT_TL_DEVICE_IF(soc_proxy__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(soc_proxy__ctn, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(hmac, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(kmac, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(aes, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(entropy_src, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(csrng, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(edn0, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(edn1, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(rv_plic, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(otbn, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(keymgr_dpe, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_main__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_main__ram, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_mbox__regs, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_mbox__ram, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(dma, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx0__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx1__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx2__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx3__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx4__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx5__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx6__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_jtag__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_pcie0__core, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_pcie1__core, dut, clk_main_i, rst_n) diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_cov_excl.el new file mode 100644 index 00000000000..bcac6f45329 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_main_no_ibex +Block 1 "0" "assign unused_scanmode = scanmode_i;" + +ANNOTATION: "[UNR]" +MODULE: prim_fifo_sync +Branch 2 "2323268504" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-" +Branch 3 "3736627057" "(!rst_ni)" (1) "(!rst_ni) 0,1,-,-" + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=2,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=3,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=4,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=5,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=6,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=7,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=8,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=9,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=10,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=11,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") + +ANNOTATION: "[UNR]" +MODULE: prim_arbiter_ppc ( parameter N=12,DW=102,EnDataPort=1,EnReqStabA=0 ) +Condition 2 "175047464" "(valid_o && ((!ready_i))) 1 -1" (2 "10") diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_cover.cfg new file mode 100644 index 00000000000..38cd510e1ca --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_cover.cfg @@ -0,0 +1,160 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_rv_dm__regs_o.a_address[20:4] +-node tb.dut tl_rv_dm__regs_o.a_address[23:22] +-node tb.dut tl_rv_dm__regs_o.a_address[28:25] +-node tb.dut tl_rv_dm__regs_o.a_address[31:30] +-node tb.dut tl_rv_dm__mem_o.a_address[17:12] +-node tb.dut tl_rv_dm__mem_o.a_address[31:19] +-node tb.dut tl_rom_ctrl0__rom_o.a_address[31:16] +-node tb.dut tl_rom_ctrl0__regs_o.a_address[16:7] +-node tb.dut tl_rom_ctrl0__regs_o.a_address[23:21] +-node tb.dut tl_rom_ctrl0__regs_o.a_address[28:25] +-node tb.dut tl_rom_ctrl0__regs_o.a_address[31:30] +-node tb.dut tl_rom_ctrl1__rom_o.a_address[16:16] +-node tb.dut tl_rom_ctrl1__rom_o.a_address[31:18] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[11:7] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[16:13] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[23:21] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[28:25] +-node tb.dut tl_rom_ctrl1__regs_o.a_address[31:30] +-node tb.dut tl_peri_no_ibex_o.a_address[27:23] +-node tb.dut tl_peri_no_ibex_o.a_address[31:30] +-node tb.dut tl_soc_proxy__core_o.a_address[15:4] +-node tb.dut tl_soc_proxy__core_o.a_address[24:18] +-node tb.dut tl_soc_proxy__core_o.a_address[28:26] +-node tb.dut tl_soc_proxy__core_o.a_address[31:30] +-node tb.dut tl_soc_proxy__ctn_o.a_address[31:31] +-node tb.dut tl_hmac_o.a_address[15:13] +-node tb.dut tl_hmac_o.a_address[19:17] +-node tb.dut tl_hmac_o.a_address[23:21] +-node tb.dut tl_hmac_o.a_address[28:25] +-node tb.dut tl_hmac_o.a_address[31:30] +-node tb.dut tl_kmac_o.a_address[16:12] +-node tb.dut tl_kmac_o.a_address[19:18] +-node tb.dut tl_kmac_o.a_address[23:21] +-node tb.dut tl_kmac_o.a_address[28:25] +-node tb.dut tl_kmac_o.a_address[31:30] +-node tb.dut tl_aes_o.a_address[19:8] +-node tb.dut tl_aes_o.a_address[23:21] +-node tb.dut tl_aes_o.a_address[28:25] +-node tb.dut tl_aes_o.a_address[31:30] +-node tb.dut tl_entropy_src_o.a_address[16:8] +-node tb.dut tl_entropy_src_o.a_address[19:19] +-node tb.dut tl_entropy_src_o.a_address[23:21] +-node tb.dut tl_entropy_src_o.a_address[28:25] +-node tb.dut tl_entropy_src_o.a_address[31:30] +-node tb.dut tl_csrng_o.a_address[15:7] +-node tb.dut tl_csrng_o.a_address[17:17] +-node tb.dut tl_csrng_o.a_address[19:19] +-node tb.dut tl_csrng_o.a_address[23:21] +-node tb.dut tl_csrng_o.a_address[28:25] +-node tb.dut tl_csrng_o.a_address[31:30] +-node tb.dut tl_edn0_o.a_address[15:7] +-node tb.dut tl_edn0_o.a_address[19:19] +-node tb.dut tl_edn0_o.a_address[23:21] +-node tb.dut tl_edn0_o.a_address[28:25] +-node tb.dut tl_edn0_o.a_address[31:30] +-node tb.dut tl_edn1_o.a_address[18:7] +-node tb.dut tl_edn1_o.a_address[23:21] +-node tb.dut tl_edn1_o.a_address[28:25] +-node tb.dut tl_edn1_o.a_address[31:30] +-node tb.dut tl_rv_plic_o.a_address[28:28] +-node tb.dut tl_rv_plic_o.a_address[31:30] +-node tb.dut tl_otbn_o.a_address[19:18] +-node tb.dut tl_otbn_o.a_address[23:21] +-node tb.dut tl_otbn_o.a_address[28:25] +-node tb.dut tl_otbn_o.a_address[31:30] +-node tb.dut tl_keymgr_dpe_o.a_address[17:8] +-node tb.dut tl_keymgr_dpe_o.a_address[19:19] +-node tb.dut tl_keymgr_dpe_o.a_address[23:21] +-node tb.dut tl_keymgr_dpe_o.a_address[28:25] +-node tb.dut tl_keymgr_dpe_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_main__regs_o.a_address[17:6] +-node tb.dut tl_sram_ctrl_main__regs_o.a_address[23:21] +-node tb.dut tl_sram_ctrl_main__regs_o.a_address[28:25] +-node tb.dut tl_sram_ctrl_main__regs_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_main__ram_o.a_address[27:16] +-node tb.dut tl_sram_ctrl_main__ram_o.a_address[31:29] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[15:6] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[17:17] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[23:21] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[28:25] +-node tb.dut tl_sram_ctrl_mbox__regs_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_mbox__ram_o.a_address[23:12] +-node tb.dut tl_sram_ctrl_mbox__ram_o.a_address[27:25] +-node tb.dut tl_sram_ctrl_mbox__ram_o.a_address[31:29] +-node tb.dut tl_dma_o.a_address[15:9] +-node tb.dut tl_dma_o.a_address[24:17] +-node tb.dut tl_dma_o.a_address[28:26] +-node tb.dut tl_dma_o.a_address[31:30] +-node tb.dut tl_mbx0__core_o.a_address[24:7] +-node tb.dut tl_mbx0__core_o.a_address[28:26] +-node tb.dut tl_mbx0__core_o.a_address[31:30] +-node tb.dut tl_mbx1__core_o.a_address[7:7] +-node tb.dut tl_mbx1__core_o.a_address[24:9] +-node tb.dut tl_mbx1__core_o.a_address[28:26] +-node tb.dut tl_mbx1__core_o.a_address[31:30] +-node tb.dut tl_mbx2__core_o.a_address[8:7] +-node tb.dut tl_mbx2__core_o.a_address[24:10] +-node tb.dut tl_mbx2__core_o.a_address[28:26] +-node tb.dut tl_mbx2__core_o.a_address[31:30] +-node tb.dut tl_mbx3__core_o.a_address[7:7] +-node tb.dut tl_mbx3__core_o.a_address[24:10] +-node tb.dut tl_mbx3__core_o.a_address[28:26] +-node tb.dut tl_mbx3__core_o.a_address[31:30] +-node tb.dut tl_mbx4__core_o.a_address[9:7] +-node tb.dut tl_mbx4__core_o.a_address[24:11] +-node tb.dut tl_mbx4__core_o.a_address[28:26] +-node tb.dut tl_mbx4__core_o.a_address[31:30] +-node tb.dut tl_mbx5__core_o.a_address[7:7] +-node tb.dut tl_mbx5__core_o.a_address[9:9] +-node tb.dut tl_mbx5__core_o.a_address[24:11] +-node tb.dut tl_mbx5__core_o.a_address[28:26] +-node tb.dut tl_mbx5__core_o.a_address[31:30] +-node tb.dut tl_mbx6__core_o.a_address[8:7] +-node tb.dut tl_mbx6__core_o.a_address[24:11] +-node tb.dut tl_mbx6__core_o.a_address[28:26] +-node tb.dut tl_mbx6__core_o.a_address[31:30] +-node tb.dut tl_mbx_jtag__core_o.a_address[10:7] +-node tb.dut tl_mbx_jtag__core_o.a_address[24:12] +-node tb.dut tl_mbx_jtag__core_o.a_address[28:26] +-node tb.dut tl_mbx_jtag__core_o.a_address[31:30] +-node tb.dut tl_mbx_pcie0__core_o.a_address[17:7] +-node tb.dut tl_mbx_pcie0__core_o.a_address[24:19] +-node tb.dut tl_mbx_pcie0__core_o.a_address[28:26] +-node tb.dut tl_mbx_pcie0__core_o.a_address[31:30] +-node tb.dut tl_mbx_pcie1__core_o.a_address[7:7] +-node tb.dut tl_mbx_pcie1__core_o.a_address[17:9] +-node tb.dut tl_mbx_pcie1__core_o.a_address[24:19] +-node tb.dut tl_mbx_pcie1__core_o.a_address[28:26] +-node tb.dut tl_mbx_pcie1__core_o.a_address[31:30] + +-node tb.dut tl_*.a_source[7:4] +-node tb.dut tl_*.d_source[7:4] +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 00000000000..b976c4e0691 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,191 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"rv_dm__regs", '{ + '{32'h21200000, 32'h2120000f} + }}, + '{"rv_dm__mem", '{ + '{32'h00040000, 32'h00040fff} + }}, + '{"rom_ctrl0__rom", '{ + '{32'h00008000, 32'h0000ffff} + }}, + '{"rom_ctrl0__regs", '{ + '{32'h211e0000, 32'h211e007f} + }}, + '{"rom_ctrl1__rom", '{ + '{32'h00020000, 32'h0002ffff} + }}, + '{"rom_ctrl1__regs", '{ + '{32'h211e1000, 32'h211e107f} + }}, + '{"peri_no_ibex", '{ + '{32'h30000000, 32'h307fffff} + }}, + '{"soc_proxy__core", '{ + '{32'h22030000, 32'h2203000f} + }}, + '{"soc_proxy__ctn", '{ + '{32'h40000000, 32'h7fffffff} + }}, + '{"hmac", '{ + '{32'h21110000, 32'h21111fff} + }}, + '{"kmac", '{ + '{32'h21120000, 32'h21120fff} + }}, + '{"aes", '{ + '{32'h21100000, 32'h211000ff} + }}, + '{"entropy_src", '{ + '{32'h21160000, 32'h211600ff} + }}, + '{"csrng", '{ + '{32'h21150000, 32'h2115007f} + }}, + '{"edn0", '{ + '{32'h21170000, 32'h2117007f} + }}, + '{"edn1", '{ + '{32'h21180000, 32'h2118007f} + }}, + '{"rv_plic", '{ + '{32'h28000000, 32'h2fffffff} + }}, + '{"otbn", '{ + '{32'h21130000, 32'h2113ffff} + }}, + '{"keymgr_dpe", '{ + '{32'h21140000, 32'h211400ff} + }}, + '{"sram_ctrl_main__regs", '{ + '{32'h211c0000, 32'h211c003f} + }}, + '{"sram_ctrl_main__ram", '{ + '{32'h10000000, 32'h1000ffff} + }}, + '{"sram_ctrl_mbox__regs", '{ + '{32'h211d0000, 32'h211d003f} + }}, + '{"sram_ctrl_mbox__ram", '{ + '{32'h11000000, 32'h11000fff} + }}, + '{"dma", '{ + '{32'h22010000, 32'h220101ff} + }}, + '{"mbx0__core", '{ + '{32'h22000000, 32'h2200007f} + }}, + '{"mbx1__core", '{ + '{32'h22000100, 32'h2200017f} + }}, + '{"mbx2__core", '{ + '{32'h22000200, 32'h2200027f} + }}, + '{"mbx3__core", '{ + '{32'h22000300, 32'h2200037f} + }}, + '{"mbx4__core", '{ + '{32'h22000400, 32'h2200047f} + }}, + '{"mbx5__core", '{ + '{32'h22000500, 32'h2200057f} + }}, + '{"mbx6__core", '{ + '{32'h22000600, 32'h2200067f} + }}, + '{"mbx_jtag__core", '{ + '{32'h22000800, 32'h2200087f} + }}, + '{"mbx_pcie0__core", '{ + '{32'h22040000, 32'h2204007f} + }}, + '{"mbx_pcie1__core", '{ + '{32'h22040100, 32'h2204017f} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"rv_dm__sba", 0, '{ + "rom_ctrl0__rom", + "rom_ctrl0__regs", + "rom_ctrl1__rom", + "rom_ctrl1__regs", + "rv_dm__mem", + "rv_dm__regs", + "sram_ctrl_main__ram", + "peri_no_ibex", + "aes", + "entropy_src", + "csrng", + "edn0", + "edn1", + "hmac", + "rv_plic", + "otbn", + "keymgr_dpe", + "kmac", + "sram_ctrl_main__regs", + "sram_ctrl_mbox__ram", + "sram_ctrl_mbox__regs", + "soc_proxy__ctn", + "soc_proxy__core", + "dma", + "mbx0__core", + "mbx1__core", + "mbx2__core", + "mbx3__core", + "mbx4__core", + "mbx5__core", + "mbx6__core", + "mbx_jtag__core", + "mbx_pcie0__core", + "mbx_pcie1__core"}} + , + '{"dma__host", 1, '{ + "sram_ctrl_main__ram", + "sram_ctrl_mbox__ram", + "aes", + "hmac", + "otbn", + "keymgr_dpe", + "kmac", + "soc_proxy__ctn", + "peri_no_ibex"}} + , + '{"mbx0__sram", 2, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx1__sram", 3, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx2__sram", 4, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx3__sram", 5, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx4__sram", 6, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx5__sram", 7, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx6__sram", 8, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_jtag__sram", 9, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie0__sram", 10, '{ + "sram_ctrl_mbox__ram"}} + , + '{"mbx_pcie1__sram", 11, '{ + "sram_ctrl_mbox__ram"}} +}; diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_bind.core b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_bind.core new file mode 100644 index 00000000000..99bcd71fb6b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_main_no_ibex_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_main_no_ibex_bind:0.1" +description: "XBAR main_no_ibex assertion bind" +filesets: + files_dv: + files: + - xbar_main_no_ibex_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_bind.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_bind.sv new file mode 100644 index 00000000000..b889e5928b1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_bind.sv @@ -0,0 +1,288 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main_no_ibex_bind module generated by `tlgen.py` tool for assertions +module xbar_main_no_ibex_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_rv_dm__sba ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_dm__sba_i), + .d2h (tl_rv_dm__sba_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_dma__host ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_dma__host_i), + .d2h (tl_dma__host_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx0__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx0__sram_i), + .d2h (tl_mbx0__sram_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx1__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx1__sram_i), + .d2h (tl_mbx1__sram_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx2__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx2__sram_i), + .d2h (tl_mbx2__sram_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx3__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx3__sram_i), + .d2h (tl_mbx3__sram_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx4__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx4__sram_i), + .d2h (tl_mbx4__sram_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx5__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx5__sram_i), + .d2h (tl_mbx5__sram_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx6__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx6__sram_i), + .d2h (tl_mbx6__sram_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx_jtag__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_jtag__sram_i), + .d2h (tl_mbx_jtag__sram_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx_pcie0__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie0__sram_i), + .d2h (tl_mbx_pcie0__sram_o) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx_pcie1__sram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie1__sram_i), + .d2h (tl_mbx_pcie1__sram_o) + ); + + // Device interfaces + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_dm__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_dm__regs_o), + .d2h (tl_rv_dm__regs_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_dm__mem ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_dm__mem_o), + .d2h (tl_rv_dm__mem_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl0__rom ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rom_ctrl0__rom_o), + .d2h (tl_rom_ctrl0__rom_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl0__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rom_ctrl0__regs_o), + .d2h (tl_rom_ctrl0__regs_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl1__rom ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rom_ctrl1__rom_o), + .d2h (tl_rom_ctrl1__rom_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_rom_ctrl1__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rom_ctrl1__regs_o), + .d2h (tl_rom_ctrl1__regs_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_peri_no_ibex ( + .clk_i (clk_fixed_i), + .rst_ni (rst_fixed_ni), + .h2d (tl_peri_no_ibex_o), + .d2h (tl_peri_no_ibex_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_soc_proxy__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_soc_proxy__core_o), + .d2h (tl_soc_proxy__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_soc_proxy__ctn ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_soc_proxy__ctn_o), + .d2h (tl_soc_proxy__ctn_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_hmac ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_hmac_o), + .d2h (tl_hmac_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_kmac ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_kmac_o), + .d2h (tl_kmac_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_aes ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_aes_o), + .d2h (tl_aes_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_entropy_src ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_entropy_src_o), + .d2h (tl_entropy_src_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_csrng ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_csrng_o), + .d2h (tl_csrng_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_edn0 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_edn0_o), + .d2h (tl_edn0_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_edn1 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_edn1_o), + .d2h (tl_edn1_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_plic ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_rv_plic_o), + .d2h (tl_rv_plic_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_otbn ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_otbn_o), + .d2h (tl_otbn_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_keymgr_dpe ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_keymgr_dpe_o), + .d2h (tl_keymgr_dpe_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_main__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_main__regs_o), + .d2h (tl_sram_ctrl_main__regs_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_main__ram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_main__ram_o), + .d2h (tl_sram_ctrl_main__ram_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_mbox__regs ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_mbox__regs_o), + .d2h (tl_sram_ctrl_mbox__regs_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_mbox__ram ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_sram_ctrl_mbox__ram_o), + .d2h (tl_sram_ctrl_mbox__ram_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_dma ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_dma_o), + .d2h (tl_dma_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx0__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx0__core_o), + .d2h (tl_mbx0__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx1__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx1__core_o), + .d2h (tl_mbx1__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx2__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx2__core_o), + .d2h (tl_mbx2__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx3__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx3__core_o), + .d2h (tl_mbx3__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx4__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx4__core_o), + .d2h (tl_mbx4__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx5__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx5__core_o), + .d2h (tl_mbx5__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx6__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx6__core_o), + .d2h (tl_mbx6__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_jtag__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_jtag__core_o), + .d2h (tl_mbx_jtag__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_pcie0__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie0__core_o), + .d2h (tl_mbx_pcie0__core_i) + ); + bind xbar_main_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_pcie1__core ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .h2d (tl_mbx_pcie1__core_o), + .d2h (tl_mbx_pcie1__core_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_sim.core b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_sim.core new file mode 100644 index 00000000000..269f04425af --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_main_no_ibex_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_main_no_ibex_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling_no_ibex:xbar_main_no_ibex + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_no_ibex_xbar_main_no_ibex_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_sim_cfg.hjson new file mode 100644 index 00000000000..ba49fc83d4b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/dv/autogen/xbar_main_no_ibex_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main_no_ibex_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_main_no_ibex + + // Top level dut name (sv module). + dut: xbar_main_no_ibex + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling_no_ibex + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/rtl/autogen/tl_main_no_ibex_pkg.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/rtl/autogen/tl_main_no_ibex_pkg.sv new file mode 100644 index 00000000000..f7fb0b15b86 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/rtl/autogen/tl_main_no_ibex_pkg.sv @@ -0,0 +1,138 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_main_no_ibex package generated by `tlgen.py` tool + +package tl_main_no_ibex_pkg; + + localparam logic [31:0] ADDR_SPACE_RV_DM__REGS = 32'h 21200000; + localparam logic [31:0] ADDR_SPACE_RV_DM__MEM = 32'h 00040000; + localparam logic [31:0] ADDR_SPACE_ROM_CTRL0__ROM = 32'h 00008000; + localparam logic [31:0] ADDR_SPACE_ROM_CTRL0__REGS = 32'h 211e0000; + localparam logic [31:0] ADDR_SPACE_ROM_CTRL1__ROM = 32'h 00020000; + localparam logic [31:0] ADDR_SPACE_ROM_CTRL1__REGS = 32'h 211e1000; + localparam logic [0:0][31:0] ADDR_SPACE_PERI_NO_IBEX = { + 32'h 30000000 + }; + localparam logic [31:0] ADDR_SPACE_SOC_PROXY__CORE = 32'h 22030000; + localparam logic [31:0] ADDR_SPACE_SOC_PROXY__CTN = 32'h 40000000; + localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 21110000; + localparam logic [31:0] ADDR_SPACE_KMAC = 32'h 21120000; + localparam logic [31:0] ADDR_SPACE_AES = 32'h 21100000; + localparam logic [31:0] ADDR_SPACE_ENTROPY_SRC = 32'h 21160000; + localparam logic [31:0] ADDR_SPACE_CSRNG = 32'h 21150000; + localparam logic [31:0] ADDR_SPACE_EDN0 = 32'h 21170000; + localparam logic [31:0] ADDR_SPACE_EDN1 = 32'h 21180000; + localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 28000000; + localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 21130000; + localparam logic [31:0] ADDR_SPACE_KEYMGR_DPE = 32'h 21140000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__REGS = 32'h 211c0000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN__RAM = 32'h 10000000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MBOX__REGS = 32'h 211d0000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MBOX__RAM = 32'h 11000000; + localparam logic [31:0] ADDR_SPACE_DMA = 32'h 22010000; + localparam logic [31:0] ADDR_SPACE_MBX0__CORE = 32'h 22000000; + localparam logic [31:0] ADDR_SPACE_MBX1__CORE = 32'h 22000100; + localparam logic [31:0] ADDR_SPACE_MBX2__CORE = 32'h 22000200; + localparam logic [31:0] ADDR_SPACE_MBX3__CORE = 32'h 22000300; + localparam logic [31:0] ADDR_SPACE_MBX4__CORE = 32'h 22000400; + localparam logic [31:0] ADDR_SPACE_MBX5__CORE = 32'h 22000500; + localparam logic [31:0] ADDR_SPACE_MBX6__CORE = 32'h 22000600; + localparam logic [31:0] ADDR_SPACE_MBX_JTAG__CORE = 32'h 22000800; + localparam logic [31:0] ADDR_SPACE_MBX_PCIE0__CORE = 32'h 22040000; + localparam logic [31:0] ADDR_SPACE_MBX_PCIE1__CORE = 32'h 22040100; + + localparam logic [31:0] ADDR_MASK_RV_DM__REGS = 32'h 0000000f; + localparam logic [31:0] ADDR_MASK_RV_DM__MEM = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_ROM_CTRL0__ROM = 32'h 00007fff; + localparam logic [31:0] ADDR_MASK_ROM_CTRL0__REGS = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_ROM_CTRL1__ROM = 32'h 0000ffff; + localparam logic [31:0] ADDR_MASK_ROM_CTRL1__REGS = 32'h 0000007f; + localparam logic [0:0][31:0] ADDR_MASK_PERI_NO_IBEX = { + 32'h 007fffff + }; + localparam logic [31:0] ADDR_MASK_SOC_PROXY__CORE = 32'h 0000000f; + localparam logic [31:0] ADDR_MASK_SOC_PROXY__CTN = 32'h 3fffffff; + localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00001fff; + localparam logic [31:0] ADDR_MASK_KMAC = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_AES = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_ENTROPY_SRC = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_CSRNG = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_EDN0 = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_EDN1 = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 07ffffff; + localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0000ffff; + localparam logic [31:0] ADDR_MASK_KEYMGR_DPE = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__REGS = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN__RAM = 32'h 0000ffff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MBOX__REGS = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MBOX__RAM = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_DMA = 32'h 000001ff; + localparam logic [31:0] ADDR_MASK_MBX0__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX1__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX2__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX3__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX4__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX5__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX6__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX_JTAG__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX_PCIE0__CORE = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_MBX_PCIE1__CORE = 32'h 0000007f; + + localparam int N_HOST = 12; + localparam int N_DEVICE = 34; + + typedef enum int { + TlRvDmRegs = 0, + TlRvDmMem = 1, + TlRomCtrl0Rom = 2, + TlRomCtrl0Regs = 3, + TlRomCtrl1Rom = 4, + TlRomCtrl1Regs = 5, + TlPeriNoIbex = 6, + TlSocProxyCore = 7, + TlSocProxyCtn = 8, + TlHmac = 9, + TlKmac = 10, + TlAes = 11, + TlEntropySrc = 12, + TlCsrng = 13, + TlEdn0 = 14, + TlEdn1 = 15, + TlRvPlic = 16, + TlOtbn = 17, + TlKeymgrDpe = 18, + TlSramCtrlMainRegs = 19, + TlSramCtrlMainRam = 20, + TlSramCtrlMboxRegs = 21, + TlSramCtrlMboxRam = 22, + TlDma = 23, + TlMbx0Core = 24, + TlMbx1Core = 25, + TlMbx2Core = 26, + TlMbx3Core = 27, + TlMbx4Core = 28, + TlMbx5Core = 29, + TlMbx6Core = 30, + TlMbxJtagCore = 31, + TlMbxPcie0Core = 32, + TlMbxPcie1Core = 33 + } tl_device_e; + + typedef enum int { + TlRvDmSba = 0, + TlDmaHost = 1, + TlMbx0Sram = 2, + TlMbx1Sram = 3, + TlMbx2Sram = 4, + TlMbx3Sram = 5, + TlMbx4Sram = 6, + TlMbx5Sram = 7, + TlMbx6Sram = 8, + TlMbxJtagSram = 9, + TlMbxPcie0Sram = 10, + TlMbxPcie1Sram = 11 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/rtl/autogen/xbar_main_no_ibex.sv b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/rtl/autogen/xbar_main_no_ibex.sv new file mode 100644 index 00000000000..7c908be2b4b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/rtl/autogen/xbar_main_no_ibex.sv @@ -0,0 +1,1241 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_main_no_ibex module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// rv_dm.sba +// -> s1n_46 +// -> rom_ctrl0.rom +// -> rom_ctrl0.regs +// -> rom_ctrl1.rom +// -> rom_ctrl1.regs +// -> rv_dm.mem +// -> rv_dm.regs +// -> sm1_47 +// -> sram_ctrl_main.ram +// -> sm1_49 +// -> asf_48 +// -> peri_no_ibex +// -> sm1_50 +// -> aes +// -> entropy_src +// -> csrng +// -> edn0 +// -> edn1 +// -> sm1_51 +// -> hmac +// -> rv_plic +// -> sm1_52 +// -> otbn +// -> sm1_53 +// -> keymgr_dpe +// -> sm1_54 +// -> kmac +// -> sram_ctrl_main.regs +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// -> sram_ctrl_mbox.regs +// -> sm1_56 +// -> soc_proxy.ctn +// -> soc_proxy.core +// -> dma +// -> mbx0.core +// -> mbx1.core +// -> mbx2.core +// -> mbx3.core +// -> mbx4.core +// -> mbx5.core +// -> mbx6.core +// -> mbx_jtag.core +// -> mbx_pcie0.core +// -> mbx_pcie1.core +// dma.host +// -> s1n_57 +// -> sm1_47 +// -> sram_ctrl_main.ram +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// -> sm1_50 +// -> aes +// -> sm1_51 +// -> hmac +// -> sm1_52 +// -> otbn +// -> sm1_53 +// -> keymgr_dpe +// -> sm1_54 +// -> kmac +// -> sm1_56 +// -> soc_proxy.ctn +// -> sm1_49 +// -> asf_48 +// -> peri_no_ibex +// mbx0.sram +// -> s1n_58 +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// mbx1.sram +// -> s1n_59 +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// mbx2.sram +// -> s1n_60 +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// mbx3.sram +// -> s1n_61 +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// mbx4.sram +// -> s1n_62 +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// mbx5.sram +// -> s1n_63 +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// mbx6.sram +// -> s1n_64 +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// mbx_jtag.sram +// -> s1n_65 +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// mbx_pcie0.sram +// -> s1n_66 +// -> sm1_55 +// -> sram_ctrl_mbox.ram +// mbx_pcie1.sram +// -> s1n_67 +// -> sm1_55 +// -> sram_ctrl_mbox.ram + +module xbar_main_no_ibex ( + input clk_main_i, + input clk_fixed_i, + input rst_main_ni, + input rst_fixed_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_rv_dm__sba_i, + output tlul_pkg::tl_d2h_t tl_rv_dm__sba_o, + input tlul_pkg::tl_h2d_t tl_dma__host_i, + output tlul_pkg::tl_d2h_t tl_dma__host_o, + input tlul_pkg::tl_h2d_t tl_mbx0__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx0__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx1__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx1__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx2__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx2__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx3__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx3__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx4__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx4__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx5__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx5__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx6__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx6__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx_jtag__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx_jtag__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx_pcie0__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx_pcie0__sram_o, + input tlul_pkg::tl_h2d_t tl_mbx_pcie1__sram_i, + output tlul_pkg::tl_d2h_t tl_mbx_pcie1__sram_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_rv_dm__regs_o, + input tlul_pkg::tl_d2h_t tl_rv_dm__regs_i, + output tlul_pkg::tl_h2d_t tl_rv_dm__mem_o, + input tlul_pkg::tl_d2h_t tl_rv_dm__mem_i, + output tlul_pkg::tl_h2d_t tl_rom_ctrl0__rom_o, + input tlul_pkg::tl_d2h_t tl_rom_ctrl0__rom_i, + output tlul_pkg::tl_h2d_t tl_rom_ctrl0__regs_o, + input tlul_pkg::tl_d2h_t tl_rom_ctrl0__regs_i, + output tlul_pkg::tl_h2d_t tl_rom_ctrl1__rom_o, + input tlul_pkg::tl_d2h_t tl_rom_ctrl1__rom_i, + output tlul_pkg::tl_h2d_t tl_rom_ctrl1__regs_o, + input tlul_pkg::tl_d2h_t tl_rom_ctrl1__regs_i, + output tlul_pkg::tl_h2d_t tl_peri_no_ibex_o, + input tlul_pkg::tl_d2h_t tl_peri_no_ibex_i, + output tlul_pkg::tl_h2d_t tl_soc_proxy__core_o, + input tlul_pkg::tl_d2h_t tl_soc_proxy__core_i, + output tlul_pkg::tl_h2d_t tl_soc_proxy__ctn_o, + input tlul_pkg::tl_d2h_t tl_soc_proxy__ctn_i, + output tlul_pkg::tl_h2d_t tl_hmac_o, + input tlul_pkg::tl_d2h_t tl_hmac_i, + output tlul_pkg::tl_h2d_t tl_kmac_o, + input tlul_pkg::tl_d2h_t tl_kmac_i, + output tlul_pkg::tl_h2d_t tl_aes_o, + input tlul_pkg::tl_d2h_t tl_aes_i, + output tlul_pkg::tl_h2d_t tl_entropy_src_o, + input tlul_pkg::tl_d2h_t tl_entropy_src_i, + output tlul_pkg::tl_h2d_t tl_csrng_o, + input tlul_pkg::tl_d2h_t tl_csrng_i, + output tlul_pkg::tl_h2d_t tl_edn0_o, + input tlul_pkg::tl_d2h_t tl_edn0_i, + output tlul_pkg::tl_h2d_t tl_edn1_o, + input tlul_pkg::tl_d2h_t tl_edn1_i, + output tlul_pkg::tl_h2d_t tl_rv_plic_o, + input tlul_pkg::tl_d2h_t tl_rv_plic_i, + output tlul_pkg::tl_h2d_t tl_otbn_o, + input tlul_pkg::tl_d2h_t tl_otbn_i, + output tlul_pkg::tl_h2d_t tl_keymgr_dpe_o, + input tlul_pkg::tl_d2h_t tl_keymgr_dpe_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_main__regs_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_main__regs_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_main__ram_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_main__ram_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_mbox__regs_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_mbox__regs_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_mbox__ram_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_mbox__ram_i, + output tlul_pkg::tl_h2d_t tl_dma_o, + input tlul_pkg::tl_d2h_t tl_dma_i, + output tlul_pkg::tl_h2d_t tl_mbx0__core_o, + input tlul_pkg::tl_d2h_t tl_mbx0__core_i, + output tlul_pkg::tl_h2d_t tl_mbx1__core_o, + input tlul_pkg::tl_d2h_t tl_mbx1__core_i, + output tlul_pkg::tl_h2d_t tl_mbx2__core_o, + input tlul_pkg::tl_d2h_t tl_mbx2__core_i, + output tlul_pkg::tl_h2d_t tl_mbx3__core_o, + input tlul_pkg::tl_d2h_t tl_mbx3__core_i, + output tlul_pkg::tl_h2d_t tl_mbx4__core_o, + input tlul_pkg::tl_d2h_t tl_mbx4__core_i, + output tlul_pkg::tl_h2d_t tl_mbx5__core_o, + input tlul_pkg::tl_d2h_t tl_mbx5__core_i, + output tlul_pkg::tl_h2d_t tl_mbx6__core_o, + input tlul_pkg::tl_d2h_t tl_mbx6__core_i, + output tlul_pkg::tl_h2d_t tl_mbx_jtag__core_o, + input tlul_pkg::tl_d2h_t tl_mbx_jtag__core_i, + output tlul_pkg::tl_h2d_t tl_mbx_pcie0__core_o, + input tlul_pkg::tl_d2h_t tl_mbx_pcie0__core_i, + output tlul_pkg::tl_h2d_t tl_mbx_pcie1__core_o, + input tlul_pkg::tl_d2h_t tl_mbx_pcie1__core_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_main_no_ibex_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_46_us_h2d ; + tl_d2h_t tl_s1n_46_us_d2h ; + + + tl_h2d_t tl_s1n_46_ds_h2d [34]; + tl_d2h_t tl_s1n_46_ds_d2h [34]; + + // Create steering signal + logic [5:0] dev_sel_s1n_46; + + + tl_h2d_t tl_sm1_47_us_h2d [2]; + tl_d2h_t tl_sm1_47_us_d2h [2]; + + tl_h2d_t tl_sm1_47_ds_h2d ; + tl_d2h_t tl_sm1_47_ds_d2h ; + + tl_h2d_t tl_asf_48_us_h2d ; + tl_d2h_t tl_asf_48_us_d2h ; + tl_h2d_t tl_asf_48_ds_h2d ; + tl_d2h_t tl_asf_48_ds_d2h ; + + + tl_h2d_t tl_sm1_49_us_h2d [2]; + tl_d2h_t tl_sm1_49_us_d2h [2]; + + tl_h2d_t tl_sm1_49_ds_h2d ; + tl_d2h_t tl_sm1_49_ds_d2h ; + + + tl_h2d_t tl_sm1_50_us_h2d [2]; + tl_d2h_t tl_sm1_50_us_d2h [2]; + + tl_h2d_t tl_sm1_50_ds_h2d ; + tl_d2h_t tl_sm1_50_ds_d2h ; + + + tl_h2d_t tl_sm1_51_us_h2d [2]; + tl_d2h_t tl_sm1_51_us_d2h [2]; + + tl_h2d_t tl_sm1_51_ds_h2d ; + tl_d2h_t tl_sm1_51_ds_d2h ; + + + tl_h2d_t tl_sm1_52_us_h2d [2]; + tl_d2h_t tl_sm1_52_us_d2h [2]; + + tl_h2d_t tl_sm1_52_ds_h2d ; + tl_d2h_t tl_sm1_52_ds_d2h ; + + + tl_h2d_t tl_sm1_53_us_h2d [2]; + tl_d2h_t tl_sm1_53_us_d2h [2]; + + tl_h2d_t tl_sm1_53_ds_h2d ; + tl_d2h_t tl_sm1_53_ds_d2h ; + + + tl_h2d_t tl_sm1_54_us_h2d [2]; + tl_d2h_t tl_sm1_54_us_d2h [2]; + + tl_h2d_t tl_sm1_54_ds_h2d ; + tl_d2h_t tl_sm1_54_ds_d2h ; + + + tl_h2d_t tl_sm1_55_us_h2d [12]; + tl_d2h_t tl_sm1_55_us_d2h [12]; + + tl_h2d_t tl_sm1_55_ds_h2d ; + tl_d2h_t tl_sm1_55_ds_d2h ; + + + tl_h2d_t tl_sm1_56_us_h2d [2]; + tl_d2h_t tl_sm1_56_us_d2h [2]; + + tl_h2d_t tl_sm1_56_ds_h2d ; + tl_d2h_t tl_sm1_56_ds_d2h ; + + tl_h2d_t tl_s1n_57_us_h2d ; + tl_d2h_t tl_s1n_57_us_d2h ; + + + tl_h2d_t tl_s1n_57_ds_h2d [9]; + tl_d2h_t tl_s1n_57_ds_d2h [9]; + + // Create steering signal + logic [3:0] dev_sel_s1n_57; + + tl_h2d_t tl_s1n_58_us_h2d ; + tl_d2h_t tl_s1n_58_us_d2h ; + + + tl_h2d_t tl_s1n_58_ds_h2d [1]; + tl_d2h_t tl_s1n_58_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_58; + + tl_h2d_t tl_s1n_59_us_h2d ; + tl_d2h_t tl_s1n_59_us_d2h ; + + + tl_h2d_t tl_s1n_59_ds_h2d [1]; + tl_d2h_t tl_s1n_59_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_59; + + tl_h2d_t tl_s1n_60_us_h2d ; + tl_d2h_t tl_s1n_60_us_d2h ; + + + tl_h2d_t tl_s1n_60_ds_h2d [1]; + tl_d2h_t tl_s1n_60_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_60; + + tl_h2d_t tl_s1n_61_us_h2d ; + tl_d2h_t tl_s1n_61_us_d2h ; + + + tl_h2d_t tl_s1n_61_ds_h2d [1]; + tl_d2h_t tl_s1n_61_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_61; + + tl_h2d_t tl_s1n_62_us_h2d ; + tl_d2h_t tl_s1n_62_us_d2h ; + + + tl_h2d_t tl_s1n_62_ds_h2d [1]; + tl_d2h_t tl_s1n_62_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_62; + + tl_h2d_t tl_s1n_63_us_h2d ; + tl_d2h_t tl_s1n_63_us_d2h ; + + + tl_h2d_t tl_s1n_63_ds_h2d [1]; + tl_d2h_t tl_s1n_63_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_63; + + tl_h2d_t tl_s1n_64_us_h2d ; + tl_d2h_t tl_s1n_64_us_d2h ; + + + tl_h2d_t tl_s1n_64_ds_h2d [1]; + tl_d2h_t tl_s1n_64_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_64; + + tl_h2d_t tl_s1n_65_us_h2d ; + tl_d2h_t tl_s1n_65_us_d2h ; + + + tl_h2d_t tl_s1n_65_ds_h2d [1]; + tl_d2h_t tl_s1n_65_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_65; + + tl_h2d_t tl_s1n_66_us_h2d ; + tl_d2h_t tl_s1n_66_us_d2h ; + + + tl_h2d_t tl_s1n_66_ds_h2d [1]; + tl_d2h_t tl_s1n_66_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_66; + + tl_h2d_t tl_s1n_67_us_h2d ; + tl_d2h_t tl_s1n_67_us_d2h ; + + + tl_h2d_t tl_s1n_67_ds_h2d [1]; + tl_d2h_t tl_s1n_67_ds_d2h [1]; + + // Create steering signal + logic [0:0] dev_sel_s1n_67; + + + + assign tl_rom_ctrl0__rom_o = tl_s1n_46_ds_h2d[0]; + assign tl_s1n_46_ds_d2h[0] = tl_rom_ctrl0__rom_i; + + assign tl_rom_ctrl0__regs_o = tl_s1n_46_ds_h2d[1]; + assign tl_s1n_46_ds_d2h[1] = tl_rom_ctrl0__regs_i; + + assign tl_rom_ctrl1__rom_o = tl_s1n_46_ds_h2d[2]; + assign tl_s1n_46_ds_d2h[2] = tl_rom_ctrl1__rom_i; + + assign tl_rom_ctrl1__regs_o = tl_s1n_46_ds_h2d[3]; + assign tl_s1n_46_ds_d2h[3] = tl_rom_ctrl1__regs_i; + + assign tl_rv_dm__mem_o = tl_s1n_46_ds_h2d[4]; + assign tl_s1n_46_ds_d2h[4] = tl_rv_dm__mem_i; + + assign tl_rv_dm__regs_o = tl_s1n_46_ds_h2d[5]; + assign tl_s1n_46_ds_d2h[5] = tl_rv_dm__regs_i; + + assign tl_sm1_47_us_h2d[0] = tl_s1n_46_ds_h2d[6]; + assign tl_s1n_46_ds_d2h[6] = tl_sm1_47_us_d2h[0]; + + assign tl_sm1_49_us_h2d[0] = tl_s1n_46_ds_h2d[7]; + assign tl_s1n_46_ds_d2h[7] = tl_sm1_49_us_d2h[0]; + + assign tl_sm1_50_us_h2d[0] = tl_s1n_46_ds_h2d[8]; + assign tl_s1n_46_ds_d2h[8] = tl_sm1_50_us_d2h[0]; + + assign tl_entropy_src_o = tl_s1n_46_ds_h2d[9]; + assign tl_s1n_46_ds_d2h[9] = tl_entropy_src_i; + + assign tl_csrng_o = tl_s1n_46_ds_h2d[10]; + assign tl_s1n_46_ds_d2h[10] = tl_csrng_i; + + assign tl_edn0_o = tl_s1n_46_ds_h2d[11]; + assign tl_s1n_46_ds_d2h[11] = tl_edn0_i; + + assign tl_edn1_o = tl_s1n_46_ds_h2d[12]; + assign tl_s1n_46_ds_d2h[12] = tl_edn1_i; + + assign tl_sm1_51_us_h2d[0] = tl_s1n_46_ds_h2d[13]; + assign tl_s1n_46_ds_d2h[13] = tl_sm1_51_us_d2h[0]; + + assign tl_rv_plic_o = tl_s1n_46_ds_h2d[14]; + assign tl_s1n_46_ds_d2h[14] = tl_rv_plic_i; + + assign tl_sm1_52_us_h2d[0] = tl_s1n_46_ds_h2d[15]; + assign tl_s1n_46_ds_d2h[15] = tl_sm1_52_us_d2h[0]; + + assign tl_sm1_53_us_h2d[0] = tl_s1n_46_ds_h2d[16]; + assign tl_s1n_46_ds_d2h[16] = tl_sm1_53_us_d2h[0]; + + assign tl_sm1_54_us_h2d[0] = tl_s1n_46_ds_h2d[17]; + assign tl_s1n_46_ds_d2h[17] = tl_sm1_54_us_d2h[0]; + + assign tl_sram_ctrl_main__regs_o = tl_s1n_46_ds_h2d[18]; + assign tl_s1n_46_ds_d2h[18] = tl_sram_ctrl_main__regs_i; + + assign tl_sm1_55_us_h2d[0] = tl_s1n_46_ds_h2d[19]; + assign tl_s1n_46_ds_d2h[19] = tl_sm1_55_us_d2h[0]; + + assign tl_sram_ctrl_mbox__regs_o = tl_s1n_46_ds_h2d[20]; + assign tl_s1n_46_ds_d2h[20] = tl_sram_ctrl_mbox__regs_i; + + assign tl_sm1_56_us_h2d[0] = tl_s1n_46_ds_h2d[21]; + assign tl_s1n_46_ds_d2h[21] = tl_sm1_56_us_d2h[0]; + + assign tl_soc_proxy__core_o = tl_s1n_46_ds_h2d[22]; + assign tl_s1n_46_ds_d2h[22] = tl_soc_proxy__core_i; + + assign tl_dma_o = tl_s1n_46_ds_h2d[23]; + assign tl_s1n_46_ds_d2h[23] = tl_dma_i; + + assign tl_mbx0__core_o = tl_s1n_46_ds_h2d[24]; + assign tl_s1n_46_ds_d2h[24] = tl_mbx0__core_i; + + assign tl_mbx1__core_o = tl_s1n_46_ds_h2d[25]; + assign tl_s1n_46_ds_d2h[25] = tl_mbx1__core_i; + + assign tl_mbx2__core_o = tl_s1n_46_ds_h2d[26]; + assign tl_s1n_46_ds_d2h[26] = tl_mbx2__core_i; + + assign tl_mbx3__core_o = tl_s1n_46_ds_h2d[27]; + assign tl_s1n_46_ds_d2h[27] = tl_mbx3__core_i; + + assign tl_mbx4__core_o = tl_s1n_46_ds_h2d[28]; + assign tl_s1n_46_ds_d2h[28] = tl_mbx4__core_i; + + assign tl_mbx5__core_o = tl_s1n_46_ds_h2d[29]; + assign tl_s1n_46_ds_d2h[29] = tl_mbx5__core_i; + + assign tl_mbx6__core_o = tl_s1n_46_ds_h2d[30]; + assign tl_s1n_46_ds_d2h[30] = tl_mbx6__core_i; + + assign tl_mbx_jtag__core_o = tl_s1n_46_ds_h2d[31]; + assign tl_s1n_46_ds_d2h[31] = tl_mbx_jtag__core_i; + + assign tl_mbx_pcie0__core_o = tl_s1n_46_ds_h2d[32]; + assign tl_s1n_46_ds_d2h[32] = tl_mbx_pcie0__core_i; + + assign tl_mbx_pcie1__core_o = tl_s1n_46_ds_h2d[33]; + assign tl_s1n_46_ds_d2h[33] = tl_mbx_pcie1__core_i; + + assign tl_sm1_47_us_h2d[1] = tl_s1n_57_ds_h2d[0]; + assign tl_s1n_57_ds_d2h[0] = tl_sm1_47_us_d2h[1]; + + assign tl_sm1_55_us_h2d[1] = tl_s1n_57_ds_h2d[1]; + assign tl_s1n_57_ds_d2h[1] = tl_sm1_55_us_d2h[1]; + + assign tl_sm1_50_us_h2d[1] = tl_s1n_57_ds_h2d[2]; + assign tl_s1n_57_ds_d2h[2] = tl_sm1_50_us_d2h[1]; + + assign tl_sm1_51_us_h2d[1] = tl_s1n_57_ds_h2d[3]; + assign tl_s1n_57_ds_d2h[3] = tl_sm1_51_us_d2h[1]; + + assign tl_sm1_52_us_h2d[1] = tl_s1n_57_ds_h2d[4]; + assign tl_s1n_57_ds_d2h[4] = tl_sm1_52_us_d2h[1]; + + assign tl_sm1_53_us_h2d[1] = tl_s1n_57_ds_h2d[5]; + assign tl_s1n_57_ds_d2h[5] = tl_sm1_53_us_d2h[1]; + + assign tl_sm1_54_us_h2d[1] = tl_s1n_57_ds_h2d[6]; + assign tl_s1n_57_ds_d2h[6] = tl_sm1_54_us_d2h[1]; + + assign tl_sm1_56_us_h2d[1] = tl_s1n_57_ds_h2d[7]; + assign tl_s1n_57_ds_d2h[7] = tl_sm1_56_us_d2h[1]; + + assign tl_sm1_49_us_h2d[1] = tl_s1n_57_ds_h2d[8]; + assign tl_s1n_57_ds_d2h[8] = tl_sm1_49_us_d2h[1]; + + assign tl_sm1_55_us_h2d[2] = tl_s1n_58_ds_h2d[0]; + assign tl_s1n_58_ds_d2h[0] = tl_sm1_55_us_d2h[2]; + + assign tl_sm1_55_us_h2d[3] = tl_s1n_59_ds_h2d[0]; + assign tl_s1n_59_ds_d2h[0] = tl_sm1_55_us_d2h[3]; + + assign tl_sm1_55_us_h2d[4] = tl_s1n_60_ds_h2d[0]; + assign tl_s1n_60_ds_d2h[0] = tl_sm1_55_us_d2h[4]; + + assign tl_sm1_55_us_h2d[5] = tl_s1n_61_ds_h2d[0]; + assign tl_s1n_61_ds_d2h[0] = tl_sm1_55_us_d2h[5]; + + assign tl_sm1_55_us_h2d[6] = tl_s1n_62_ds_h2d[0]; + assign tl_s1n_62_ds_d2h[0] = tl_sm1_55_us_d2h[6]; + + assign tl_sm1_55_us_h2d[7] = tl_s1n_63_ds_h2d[0]; + assign tl_s1n_63_ds_d2h[0] = tl_sm1_55_us_d2h[7]; + + assign tl_sm1_55_us_h2d[8] = tl_s1n_64_ds_h2d[0]; + assign tl_s1n_64_ds_d2h[0] = tl_sm1_55_us_d2h[8]; + + assign tl_sm1_55_us_h2d[9] = tl_s1n_65_ds_h2d[0]; + assign tl_s1n_65_ds_d2h[0] = tl_sm1_55_us_d2h[9]; + + assign tl_sm1_55_us_h2d[10] = tl_s1n_66_ds_h2d[0]; + assign tl_s1n_66_ds_d2h[0] = tl_sm1_55_us_d2h[10]; + + assign tl_sm1_55_us_h2d[11] = tl_s1n_67_ds_h2d[0]; + assign tl_s1n_67_ds_d2h[0] = tl_sm1_55_us_d2h[11]; + + assign tl_s1n_46_us_h2d = tl_rv_dm__sba_i; + assign tl_rv_dm__sba_o = tl_s1n_46_us_d2h; + + assign tl_sram_ctrl_main__ram_o = tl_sm1_47_ds_h2d; + assign tl_sm1_47_ds_d2h = tl_sram_ctrl_main__ram_i; + + assign tl_peri_no_ibex_o = tl_asf_48_ds_h2d; + assign tl_asf_48_ds_d2h = tl_peri_no_ibex_i; + + assign tl_asf_48_us_h2d = tl_sm1_49_ds_h2d; + assign tl_sm1_49_ds_d2h = tl_asf_48_us_d2h; + + assign tl_aes_o = tl_sm1_50_ds_h2d; + assign tl_sm1_50_ds_d2h = tl_aes_i; + + assign tl_hmac_o = tl_sm1_51_ds_h2d; + assign tl_sm1_51_ds_d2h = tl_hmac_i; + + assign tl_otbn_o = tl_sm1_52_ds_h2d; + assign tl_sm1_52_ds_d2h = tl_otbn_i; + + assign tl_keymgr_dpe_o = tl_sm1_53_ds_h2d; + assign tl_sm1_53_ds_d2h = tl_keymgr_dpe_i; + + assign tl_kmac_o = tl_sm1_54_ds_h2d; + assign tl_sm1_54_ds_d2h = tl_kmac_i; + + assign tl_sram_ctrl_mbox__ram_o = tl_sm1_55_ds_h2d; + assign tl_sm1_55_ds_d2h = tl_sram_ctrl_mbox__ram_i; + + assign tl_soc_proxy__ctn_o = tl_sm1_56_ds_h2d; + assign tl_sm1_56_ds_d2h = tl_soc_proxy__ctn_i; + + assign tl_s1n_57_us_h2d = tl_dma__host_i; + assign tl_dma__host_o = tl_s1n_57_us_d2h; + + assign tl_s1n_58_us_h2d = tl_mbx0__sram_i; + assign tl_mbx0__sram_o = tl_s1n_58_us_d2h; + + assign tl_s1n_59_us_h2d = tl_mbx1__sram_i; + assign tl_mbx1__sram_o = tl_s1n_59_us_d2h; + + assign tl_s1n_60_us_h2d = tl_mbx2__sram_i; + assign tl_mbx2__sram_o = tl_s1n_60_us_d2h; + + assign tl_s1n_61_us_h2d = tl_mbx3__sram_i; + assign tl_mbx3__sram_o = tl_s1n_61_us_d2h; + + assign tl_s1n_62_us_h2d = tl_mbx4__sram_i; + assign tl_mbx4__sram_o = tl_s1n_62_us_d2h; + + assign tl_s1n_63_us_h2d = tl_mbx5__sram_i; + assign tl_mbx5__sram_o = tl_s1n_63_us_d2h; + + assign tl_s1n_64_us_h2d = tl_mbx6__sram_i; + assign tl_mbx6__sram_o = tl_s1n_64_us_d2h; + + assign tl_s1n_65_us_h2d = tl_mbx_jtag__sram_i; + assign tl_mbx_jtag__sram_o = tl_s1n_65_us_d2h; + + assign tl_s1n_66_us_h2d = tl_mbx_pcie0__sram_i; + assign tl_mbx_pcie0__sram_o = tl_s1n_66_us_d2h; + + assign tl_s1n_67_us_h2d = tl_mbx_pcie1__sram_i; + assign tl_mbx_pcie1__sram_o = tl_s1n_67_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_46 = 6'd34; + if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL0__ROM)) == ADDR_SPACE_ROM_CTRL0__ROM) begin + dev_sel_s1n_46 = 6'd0; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL0__REGS)) == ADDR_SPACE_ROM_CTRL0__REGS) begin + dev_sel_s1n_46 = 6'd1; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL1__ROM)) == ADDR_SPACE_ROM_CTRL1__ROM) begin + dev_sel_s1n_46 = 6'd2; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_ROM_CTRL1__REGS)) == ADDR_SPACE_ROM_CTRL1__REGS) begin + dev_sel_s1n_46 = 6'd3; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__MEM)) == ADDR_SPACE_RV_DM__MEM) begin + dev_sel_s1n_46 = 6'd4; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_RV_DM__REGS)) == ADDR_SPACE_RV_DM__REGS) begin + dev_sel_s1n_46 = 6'd5; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin + dev_sel_s1n_46 = 6'd6; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_PERI_NO_IBEX)) == ADDR_SPACE_PERI_NO_IBEX) begin + dev_sel_s1n_46 = 6'd7; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_46 = 6'd8; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin + dev_sel_s1n_46 = 6'd9; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin + dev_sel_s1n_46 = 6'd10; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin + dev_sel_s1n_46 = 6'd11; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin + dev_sel_s1n_46 = 6'd12; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_46 = 6'd13; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin + dev_sel_s1n_46 = 6'd14; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + dev_sel_s1n_46 = 6'd15; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_KEYMGR_DPE)) == ADDR_SPACE_KEYMGR_DPE) begin + dev_sel_s1n_46 = 6'd16; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin + dev_sel_s1n_46 = 6'd17; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__REGS)) == ADDR_SPACE_SRAM_CTRL_MAIN__REGS) begin + dev_sel_s1n_46 = 6'd18; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_46 = 6'd19; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__REGS)) == ADDR_SPACE_SRAM_CTRL_MBOX__REGS) begin + dev_sel_s1n_46 = 6'd20; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin + dev_sel_s1n_46 = 6'd21; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CORE)) == ADDR_SPACE_SOC_PROXY__CORE) begin + dev_sel_s1n_46 = 6'd22; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_DMA)) == ADDR_SPACE_DMA) begin + dev_sel_s1n_46 = 6'd23; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX0__CORE)) == ADDR_SPACE_MBX0__CORE) begin + dev_sel_s1n_46 = 6'd24; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX1__CORE)) == ADDR_SPACE_MBX1__CORE) begin + dev_sel_s1n_46 = 6'd25; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX2__CORE)) == ADDR_SPACE_MBX2__CORE) begin + dev_sel_s1n_46 = 6'd26; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX3__CORE)) == ADDR_SPACE_MBX3__CORE) begin + dev_sel_s1n_46 = 6'd27; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX4__CORE)) == ADDR_SPACE_MBX4__CORE) begin + dev_sel_s1n_46 = 6'd28; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX5__CORE)) == ADDR_SPACE_MBX5__CORE) begin + dev_sel_s1n_46 = 6'd29; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX6__CORE)) == ADDR_SPACE_MBX6__CORE) begin + dev_sel_s1n_46 = 6'd30; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX_JTAG__CORE)) == ADDR_SPACE_MBX_JTAG__CORE) begin + dev_sel_s1n_46 = 6'd31; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE0__CORE)) == ADDR_SPACE_MBX_PCIE0__CORE) begin + dev_sel_s1n_46 = 6'd32; + + end else if ((tl_s1n_46_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE1__CORE)) == ADDR_SPACE_MBX_PCIE1__CORE) begin + dev_sel_s1n_46 = 6'd33; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_57 = 4'd9; + if ((tl_s1n_57_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin + dev_sel_s1n_57 = 4'd0; + + end else if ((tl_s1n_57_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_57 = 4'd1; + + end else if ((tl_s1n_57_us_h2d.a_address & + ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin + dev_sel_s1n_57 = 4'd2; + + end else if ((tl_s1n_57_us_h2d.a_address & + ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin + dev_sel_s1n_57 = 4'd3; + + end else if ((tl_s1n_57_us_h2d.a_address & + ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin + dev_sel_s1n_57 = 4'd4; + + end else if ((tl_s1n_57_us_h2d.a_address & + ~(ADDR_MASK_KEYMGR_DPE)) == ADDR_SPACE_KEYMGR_DPE) begin + dev_sel_s1n_57 = 4'd5; + + end else if ((tl_s1n_57_us_h2d.a_address & + ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin + dev_sel_s1n_57 = 4'd6; + + end else if ((tl_s1n_57_us_h2d.a_address & + ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin + dev_sel_s1n_57 = 4'd7; + + end else if ((tl_s1n_57_us_h2d.a_address & + ~(ADDR_MASK_PERI_NO_IBEX)) == ADDR_SPACE_PERI_NO_IBEX) begin + dev_sel_s1n_57 = 4'd8; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_58 = 1'd1; + if ((tl_s1n_58_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_58 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_59 = 1'd1; + if ((tl_s1n_59_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_59 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_60 = 1'd1; + if ((tl_s1n_60_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_60 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_61 = 1'd1; + if ((tl_s1n_61_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_61 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_62 = 1'd1; + if ((tl_s1n_62_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_62 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_63 = 1'd1; + if ((tl_s1n_63_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_63 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_64 = 1'd1; + if ((tl_s1n_64_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_64 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_65 = 1'd1; + if ((tl_s1n_65_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_65 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_66 = 1'd1; + if ((tl_s1n_66_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_66 = 1'd0; +end + end + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_67 = 1'd1; + if ((tl_s1n_67_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_MBOX__RAM)) == ADDR_SPACE_SRAM_CTRL_MBOX__RAM) begin + dev_sel_s1n_67 = 1'd0; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqPass (1'b0), + .HRspPass (1'b0), + .DReqPass (34'h3ff3ba1c5), + .DRspPass (34'h3ff3ba1c0), + .DReqDepth (136'h110001000101111000111111), + .DRspDepth (136'h110001000101111000111111), + .N (34) + ) u_s1n_46 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_46_us_h2d), + .tl_h_o (tl_s1n_46_us_d2h), + .tl_d_o (tl_s1n_46_ds_h2d), + .tl_d_i (tl_s1n_46_ds_d2h), + .dev_select_i (dev_sel_s1n_46) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_47 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_47_us_h2d), + .tl_h_o (tl_sm1_47_us_d2h), + .tl_d_o (tl_sm1_47_ds_h2d), + .tl_d_i (tl_sm1_47_ds_d2h) + ); + tlul_fifo_async #( + .ReqDepth (1), + .RspDepth (1) + ) u_asf_48 ( + .clk_h_i (clk_main_i), + .rst_h_ni (rst_main_ni), + .clk_d_i (clk_fixed_i), + .rst_d_ni (rst_fixed_ni), + .tl_h_i (tl_asf_48_us_h2d), + .tl_h_o (tl_asf_48_us_d2h), + .tl_d_o (tl_asf_48_ds_h2d), + .tl_d_i (tl_asf_48_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_49 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_49_us_h2d), + .tl_h_o (tl_sm1_49_us_d2h), + .tl_d_o (tl_sm1_49_ds_h2d), + .tl_d_i (tl_sm1_49_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_50 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_50_us_h2d), + .tl_h_o (tl_sm1_50_us_d2h), + .tl_d_o (tl_sm1_50_ds_h2d), + .tl_d_i (tl_sm1_50_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_51 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_51_us_h2d), + .tl_h_o (tl_sm1_51_us_d2h), + .tl_d_o (tl_sm1_51_ds_h2d), + .tl_d_i (tl_sm1_51_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_52 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_52_us_h2d), + .tl_h_o (tl_sm1_52_us_d2h), + .tl_d_o (tl_sm1_52_ds_h2d), + .tl_d_i (tl_sm1_52_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_53 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_53_us_h2d), + .tl_h_o (tl_sm1_53_us_d2h), + .tl_d_o (tl_sm1_53_ds_h2d), + .tl_d_i (tl_sm1_53_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqPass (1'b0), + .DRspPass (1'b0), + .M (2) + ) u_sm1_54 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_54_us_h2d), + .tl_h_o (tl_sm1_54_us_d2h), + .tl_d_o (tl_sm1_54_ds_h2d), + .tl_d_i (tl_sm1_54_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (48'h0), + .HRspDepth (48'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (12) + ) u_sm1_55 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_55_us_h2d), + .tl_h_o (tl_sm1_55_us_d2h), + .tl_d_o (tl_sm1_55_ds_h2d), + .tl_d_i (tl_sm1_55_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth (8'h0), + .HRspDepth (8'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .M (2) + ) u_sm1_56 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_sm1_56_us_h2d), + .tl_h_o (tl_sm1_56_us_d2h), + .tl_d_o (tl_sm1_56_ds_h2d), + .tl_d_i (tl_sm1_56_ds_d2h) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (36'h0), + .DRspDepth (36'h0), + .N (9) + ) u_s1n_57 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_57_us_h2d), + .tl_h_o (tl_s1n_57_us_d2h), + .tl_d_o (tl_s1n_57_ds_h2d), + .tl_d_i (tl_s1n_57_ds_d2h), + .dev_select_i (dev_sel_s1n_57) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_58 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_58_us_h2d), + .tl_h_o (tl_s1n_58_us_d2h), + .tl_d_o (tl_s1n_58_ds_h2d), + .tl_d_i (tl_s1n_58_ds_d2h), + .dev_select_i (dev_sel_s1n_58) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_59 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_59_us_h2d), + .tl_h_o (tl_s1n_59_us_d2h), + .tl_d_o (tl_s1n_59_ds_h2d), + .tl_d_i (tl_s1n_59_ds_d2h), + .dev_select_i (dev_sel_s1n_59) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_60 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_60_us_h2d), + .tl_h_o (tl_s1n_60_us_d2h), + .tl_d_o (tl_s1n_60_ds_h2d), + .tl_d_i (tl_s1n_60_ds_d2h), + .dev_select_i (dev_sel_s1n_60) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_61 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_61_us_h2d), + .tl_h_o (tl_s1n_61_us_d2h), + .tl_d_o (tl_s1n_61_ds_h2d), + .tl_d_i (tl_s1n_61_ds_d2h), + .dev_select_i (dev_sel_s1n_61) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_62 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_62_us_h2d), + .tl_h_o (tl_s1n_62_us_d2h), + .tl_d_o (tl_s1n_62_ds_h2d), + .tl_d_i (tl_s1n_62_ds_d2h), + .dev_select_i (dev_sel_s1n_62) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_63 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_63_us_h2d), + .tl_h_o (tl_s1n_63_us_d2h), + .tl_d_o (tl_s1n_63_ds_h2d), + .tl_d_i (tl_s1n_63_ds_d2h), + .dev_select_i (dev_sel_s1n_63) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_64 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_64_us_h2d), + .tl_h_o (tl_s1n_64_us_d2h), + .tl_d_o (tl_s1n_64_ds_h2d), + .tl_d_i (tl_s1n_64_ds_d2h), + .dev_select_i (dev_sel_s1n_64) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_65 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_65_us_h2d), + .tl_h_o (tl_s1n_65_us_d2h), + .tl_d_o (tl_s1n_65_ds_h2d), + .tl_d_i (tl_s1n_65_ds_d2h), + .dev_select_i (dev_sel_s1n_65) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_66 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_66_us_h2d), + .tl_h_o (tl_s1n_66_us_d2h), + .tl_d_o (tl_s1n_66_ds_h2d), + .tl_d_i (tl_s1n_66_ds_d2h), + .dev_select_i (dev_sel_s1n_66) + ); + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (4'h0), + .DRspDepth (4'h0), + .N (1) + ) u_s1n_67 ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .tl_h_i (tl_s1n_67_us_h2d), + .tl_h_o (tl_s1n_67_us_d2h), + .tl_d_o (tl_s1n_67_ds_h2d), + .tl_d_i (tl_s1n_67_ds_d2h), + .dev_select_i (dev_sel_s1n_67) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/xbar_main_no_ibex.core b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/xbar_main_no_ibex.core new file mode 100644 index 00000000000..e27ef841ddf --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_main_no_ibex/xbar_main_no_ibex.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_main_no_ibex core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling_no_ibex:xbar_main_no_ibex:0.1" +description: "Generated RTL xbar_main_no_ibex" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_main_no_ibex_pkg.sv + - rtl/autogen/xbar_main_no_ibex.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_main_no_ibex diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson new file mode 100644 index 00000000000..588297cc894 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/data/autogen/xbar_mbx.gen.hjson @@ -0,0 +1,464 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson -o hw/top_darjeeling_no_ibex/ + +{ + name: mbx + clock_srcs: + { + clk_mbx_i: main + } + clock_group: infra + reset: rst_mbx_ni + reset_connections: + { + rst_mbx_ni: + { + name: lc + domain: "0" + } + } + clock_connections: + { + clk_mbx_i: clkmgr_aon_clocks.clk_main_infra + } + domain: + [ + "0" + ] + connections: + { + mbx: + [ + mbx0.soc + mbx1.soc + mbx2.soc + mbx3.soc + mbx4.soc + mbx5.soc + mbx6.soc + mbx_pcie0.soc + mbx_pcie1.soc + racl_ctrl + ac_range_check + ] + } + nodes: + [ + { + name: mbx + type: host + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: mbx0.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx1.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465100 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx2.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx3.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465300 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx4.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465400 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx5.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1465500 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx6.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1496000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie0.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1460100 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: mbx_pcie1.soc + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: mbx + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1460200 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: racl_ctrl + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: racl_ctrl + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1461f00 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: ac_range_check + type: device + addr_space: soc_mbx + clock: clk_mbx_i + reset: rst_mbx_ni + pipeline: false + inst_type: ac_range_check + addr_range: + [ + { + base_addrs: + { + soc_mbx: 0x1464000 + } + size_byte: 0x400 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + soc_mbx + ] + clock: clk_mbx_i + type: xbar + inter_signal_list: + [ + { + name: tl_mbx + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: mbx + width: 1 + default: "" + external: true + top_signame: mbx_tl + conn_type: false + index: -1 + } + { + name: tl_mbx0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx0_soc_tl_d + index: -1 + } + { + name: tl_mbx1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx1_soc_tl_d + index: -1 + } + { + name: tl_mbx2__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx2_soc_tl_d + index: -1 + } + { + name: tl_mbx3__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx3_soc_tl_d + index: -1 + } + { + name: tl_mbx4__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx4_soc_tl_d + index: -1 + } + { + name: tl_mbx5__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx5_soc_tl_d + index: -1 + } + { + name: tl_mbx6__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx6_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie0__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx_pcie0_soc_tl_d + index: -1 + } + { + name: tl_mbx_pcie1__soc + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: mbx_pcie1_soc_tl_d + index: -1 + } + { + name: tl_racl_ctrl + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: racl_ctrl_tl + index: -1 + } + { + name: tl_ac_range_check + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: mbx + width: 1 + default: "" + top_signame: ac_range_check_tl + index: -1 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/data/autogen/xbar_mbx.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/data/autogen/xbar_mbx.hjson new file mode 100644 index 00000000000..9a046c088ef --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/data/autogen/xbar_mbx.hjson @@ -0,0 +1,89 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_mbx comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_mbx" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_mbx" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_mbx0__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx1__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx2__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx3__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx4__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx5__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx6__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie0__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_mbx_pcie1__soc" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_racl_ctrl" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_ac_range_check" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 00000000000..17261f4d7bf --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,30 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_mbx dut(); + +`DRIVE_CLK(clk_mbx_i) + +initial force dut.clk_mbx_i = clk_mbx_i; + +// TODO, all resets tie together +initial force dut.rst_mbx_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(mbx, dut, clk_mbx_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(mbx0__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx1__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx2__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx3__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx4__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx5__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx6__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_pcie0__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(mbx_pcie1__soc, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(racl_ctrl, dut, clk_mbx_i, rst_n) +`CONNECT_TL_DEVICE_IF(ac_range_check, dut, clk_mbx_i, rst_n) diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_cov_excl.el new file mode 100644 index 00000000000..a6c31310191 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_mbx +Block 1 "0" "assign unused_scanmode = scanmode_i;" diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_cover.cfg new file mode 100644 index 00000000000..8e6ee708297 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_cover.cfg @@ -0,0 +1,96 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_mbx0__soc_o.a_address[11:5] +-node tb.dut tl_mbx0__soc_o.a_address[13:13] +-node tb.dut tl_mbx0__soc_o.a_address[16:15] +-node tb.dut tl_mbx0__soc_o.a_address[21:19] +-node tb.dut tl_mbx0__soc_o.a_address[23:23] +-node tb.dut tl_mbx0__soc_o.a_address[31:25] +-node tb.dut tl_mbx1__soc_o.a_address[7:5] +-node tb.dut tl_mbx1__soc_o.a_address[11:9] +-node tb.dut tl_mbx1__soc_o.a_address[13:13] +-node tb.dut tl_mbx1__soc_o.a_address[16:15] +-node tb.dut tl_mbx1__soc_o.a_address[21:19] +-node tb.dut tl_mbx1__soc_o.a_address[23:23] +-node tb.dut tl_mbx1__soc_o.a_address[31:25] +-node tb.dut tl_mbx2__soc_o.a_address[8:5] +-node tb.dut tl_mbx2__soc_o.a_address[11:10] +-node tb.dut tl_mbx2__soc_o.a_address[13:13] +-node tb.dut tl_mbx2__soc_o.a_address[16:15] +-node tb.dut tl_mbx2__soc_o.a_address[21:19] +-node tb.dut tl_mbx2__soc_o.a_address[23:23] +-node tb.dut tl_mbx2__soc_o.a_address[31:25] +-node tb.dut tl_mbx3__soc_o.a_address[7:5] +-node tb.dut tl_mbx3__soc_o.a_address[11:10] +-node tb.dut tl_mbx3__soc_o.a_address[13:13] +-node tb.dut tl_mbx3__soc_o.a_address[16:15] +-node tb.dut tl_mbx3__soc_o.a_address[21:19] +-node tb.dut tl_mbx3__soc_o.a_address[23:23] +-node tb.dut tl_mbx3__soc_o.a_address[31:25] +-node tb.dut tl_mbx4__soc_o.a_address[9:5] +-node tb.dut tl_mbx4__soc_o.a_address[11:11] +-node tb.dut tl_mbx4__soc_o.a_address[13:13] +-node tb.dut tl_mbx4__soc_o.a_address[16:15] +-node tb.dut tl_mbx4__soc_o.a_address[21:19] +-node tb.dut tl_mbx4__soc_o.a_address[23:23] +-node tb.dut tl_mbx4__soc_o.a_address[31:25] +-node tb.dut tl_mbx5__soc_o.a_address[7:5] +-node tb.dut tl_mbx5__soc_o.a_address[9:9] +-node tb.dut tl_mbx5__soc_o.a_address[11:11] +-node tb.dut tl_mbx5__soc_o.a_address[13:13] +-node tb.dut tl_mbx5__soc_o.a_address[16:15] +-node tb.dut tl_mbx5__soc_o.a_address[21:19] +-node tb.dut tl_mbx5__soc_o.a_address[23:23] +-node tb.dut tl_mbx5__soc_o.a_address[31:25] +-node tb.dut tl_mbx6__soc_o.a_address[12:5] +-node tb.dut tl_mbx6__soc_o.a_address[15:15] +-node tb.dut tl_mbx6__soc_o.a_address[18:17] +-node tb.dut tl_mbx6__soc_o.a_address[21:20] +-node tb.dut tl_mbx6__soc_o.a_address[23:23] +-node tb.dut tl_mbx6__soc_o.a_address[31:25] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[7:5] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[16:9] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[21:19] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[23:23] +-node tb.dut tl_mbx_pcie0__soc_o.a_address[31:25] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[8:5] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[16:10] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[21:19] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[23:23] +-node tb.dut tl_mbx_pcie1__soc_o.a_address[31:25] +-node tb.dut tl_racl_ctrl_o.a_address[16:13] +-node tb.dut tl_racl_ctrl_o.a_address[21:19] +-node tb.dut tl_racl_ctrl_o.a_address[23:23] +-node tb.dut tl_racl_ctrl_o.a_address[31:25] +-node tb.dut tl_ac_range_check_o.a_address[13:10] +-node tb.dut tl_ac_range_check_o.a_address[16:15] +-node tb.dut tl_ac_range_check_o.a_address[21:19] +-node tb.dut tl_ac_range_check_o.a_address[23:23] +-node tb.dut tl_ac_range_check_o.a_address[31:25] + +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 00000000000..b655ffca203 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,58 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"mbx0__soc", '{ + '{32'h01465000, 32'h0146501f} + }}, + '{"mbx1__soc", '{ + '{32'h01465100, 32'h0146511f} + }}, + '{"mbx2__soc", '{ + '{32'h01465200, 32'h0146521f} + }}, + '{"mbx3__soc", '{ + '{32'h01465300, 32'h0146531f} + }}, + '{"mbx4__soc", '{ + '{32'h01465400, 32'h0146541f} + }}, + '{"mbx5__soc", '{ + '{32'h01465500, 32'h0146551f} + }}, + '{"mbx6__soc", '{ + '{32'h01496000, 32'h0149601f} + }}, + '{"mbx_pcie0__soc", '{ + '{32'h01460100, 32'h0146011f} + }}, + '{"mbx_pcie1__soc", '{ + '{32'h01460200, 32'h0146021f} + }}, + '{"racl_ctrl", '{ + '{32'h01461f00, 32'h01461fff} + }}, + '{"ac_range_check", '{ + '{32'h01464000, 32'h014643ff} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"mbx", 0, '{ + "mbx0__soc", + "mbx1__soc", + "mbx2__soc", + "mbx3__soc", + "mbx4__soc", + "mbx5__soc", + "mbx6__soc", + "mbx_pcie0__soc", + "mbx_pcie1__soc", + "racl_ctrl", + "ac_range_check"}} +}; diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.core b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.core new file mode 100644 index 00000000000..182661d4c0f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_mbx_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_mbx_bind:0.1" +description: "XBAR mbx assertion bind" +filesets: + files_dv: + files: + - xbar_mbx_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.sv b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.sv new file mode 100644 index 00000000000..0ec271b0da9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_bind.sv @@ -0,0 +1,84 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_mbx_bind module generated by `tlgen.py` tool for assertions +module xbar_mbx_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_mbx tlul_assert #(.EndpointType("Device")) tlul_assert_host_mbx ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx_i), + .d2h (tl_mbx_o) + ); + + // Device interfaces + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx0__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx0__soc_o), + .d2h (tl_mbx0__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx1__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx1__soc_o), + .d2h (tl_mbx1__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx2__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx2__soc_o), + .d2h (tl_mbx2__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx3__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx3__soc_o), + .d2h (tl_mbx3__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx4__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx4__soc_o), + .d2h (tl_mbx4__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx5__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx5__soc_o), + .d2h (tl_mbx5__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx6__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx6__soc_o), + .d2h (tl_mbx6__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_pcie0__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx_pcie0__soc_o), + .d2h (tl_mbx_pcie0__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_mbx_pcie1__soc ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_mbx_pcie1__soc_o), + .d2h (tl_mbx_pcie1__soc_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_racl_ctrl ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_racl_ctrl_o), + .d2h (tl_racl_ctrl_i) + ); + bind xbar_mbx tlul_assert #(.EndpointType("Host")) tlul_assert_device_ac_range_check ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .h2d (tl_ac_range_check_o), + .d2h (tl_ac_range_check_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_sim.core b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_sim.core new file mode 100644 index 00000000000..cdbe3cc0963 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_mbx_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_mbx_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling_no_ibex:xbar_mbx + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_no_ibex_xbar_mbx_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_sim_cfg.hjson new file mode 100644 index 00000000000..45449f1caef --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/dv/autogen/xbar_mbx_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_mbx_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_mbx + + // Top level dut name (sv module). + dut: xbar_mbx + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling_no_ibex + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/rtl/autogen/tl_mbx_pkg.sv b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/rtl/autogen/tl_mbx_pkg.sv new file mode 100644 index 00000000000..82566273bd0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/rtl/autogen/tl_mbx_pkg.sv @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_mbx package generated by `tlgen.py` tool + +package tl_mbx_pkg; + + localparam logic [31:0] ADDR_SPACE_MBX0__SOC = 32'h 01465000; + localparam logic [31:0] ADDR_SPACE_MBX1__SOC = 32'h 01465100; + localparam logic [31:0] ADDR_SPACE_MBX2__SOC = 32'h 01465200; + localparam logic [31:0] ADDR_SPACE_MBX3__SOC = 32'h 01465300; + localparam logic [31:0] ADDR_SPACE_MBX4__SOC = 32'h 01465400; + localparam logic [31:0] ADDR_SPACE_MBX5__SOC = 32'h 01465500; + localparam logic [31:0] ADDR_SPACE_MBX6__SOC = 32'h 01496000; + localparam logic [31:0] ADDR_SPACE_MBX_PCIE0__SOC = 32'h 01460100; + localparam logic [31:0] ADDR_SPACE_MBX_PCIE1__SOC = 32'h 01460200; + localparam logic [31:0] ADDR_SPACE_RACL_CTRL = 32'h 01461f00; + localparam logic [31:0] ADDR_SPACE_AC_RANGE_CHECK = 32'h 01464000; + + localparam logic [31:0] ADDR_MASK_MBX0__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX1__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX2__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX3__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX4__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX5__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX6__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX_PCIE0__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_MBX_PCIE1__SOC = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_RACL_CTRL = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_AC_RANGE_CHECK = 32'h 000003ff; + + localparam int N_HOST = 1; + localparam int N_DEVICE = 11; + + typedef enum int { + TlMbx0Soc = 0, + TlMbx1Soc = 1, + TlMbx2Soc = 2, + TlMbx3Soc = 3, + TlMbx4Soc = 4, + TlMbx5Soc = 5, + TlMbx6Soc = 6, + TlMbxPcie0Soc = 7, + TlMbxPcie1Soc = 8, + TlRaclCtrl = 9, + TlAcRangeCheck = 10 + } tl_device_e; + + typedef enum int { + TlMbx = 0 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/rtl/autogen/xbar_mbx.sv b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/rtl/autogen/xbar_mbx.sv new file mode 100644 index 00000000000..c83335773cb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/rtl/autogen/xbar_mbx.sv @@ -0,0 +1,181 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_mbx module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// mbx +// -> s1n_12 +// -> mbx0.soc +// -> mbx1.soc +// -> mbx2.soc +// -> mbx3.soc +// -> mbx4.soc +// -> mbx5.soc +// -> mbx6.soc +// -> mbx_pcie0.soc +// -> mbx_pcie1.soc +// -> racl_ctrl +// -> ac_range_check + +module xbar_mbx ( + input clk_mbx_i, + input rst_mbx_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_mbx_i, + output tlul_pkg::tl_d2h_t tl_mbx_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_mbx0__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx0__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx1__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx1__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx2__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx2__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx3__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx3__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx4__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx4__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx5__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx5__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx6__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx6__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx_pcie0__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx_pcie0__soc_i, + output tlul_pkg::tl_h2d_t tl_mbx_pcie1__soc_o, + input tlul_pkg::tl_d2h_t tl_mbx_pcie1__soc_i, + output tlul_pkg::tl_h2d_t tl_racl_ctrl_o, + input tlul_pkg::tl_d2h_t tl_racl_ctrl_i, + output tlul_pkg::tl_h2d_t tl_ac_range_check_o, + input tlul_pkg::tl_d2h_t tl_ac_range_check_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_mbx_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_12_us_h2d ; + tl_d2h_t tl_s1n_12_us_d2h ; + + + tl_h2d_t tl_s1n_12_ds_h2d [11]; + tl_d2h_t tl_s1n_12_ds_d2h [11]; + + // Create steering signal + logic [3:0] dev_sel_s1n_12; + + + + assign tl_mbx0__soc_o = tl_s1n_12_ds_h2d[0]; + assign tl_s1n_12_ds_d2h[0] = tl_mbx0__soc_i; + + assign tl_mbx1__soc_o = tl_s1n_12_ds_h2d[1]; + assign tl_s1n_12_ds_d2h[1] = tl_mbx1__soc_i; + + assign tl_mbx2__soc_o = tl_s1n_12_ds_h2d[2]; + assign tl_s1n_12_ds_d2h[2] = tl_mbx2__soc_i; + + assign tl_mbx3__soc_o = tl_s1n_12_ds_h2d[3]; + assign tl_s1n_12_ds_d2h[3] = tl_mbx3__soc_i; + + assign tl_mbx4__soc_o = tl_s1n_12_ds_h2d[4]; + assign tl_s1n_12_ds_d2h[4] = tl_mbx4__soc_i; + + assign tl_mbx5__soc_o = tl_s1n_12_ds_h2d[5]; + assign tl_s1n_12_ds_d2h[5] = tl_mbx5__soc_i; + + assign tl_mbx6__soc_o = tl_s1n_12_ds_h2d[6]; + assign tl_s1n_12_ds_d2h[6] = tl_mbx6__soc_i; + + assign tl_mbx_pcie0__soc_o = tl_s1n_12_ds_h2d[7]; + assign tl_s1n_12_ds_d2h[7] = tl_mbx_pcie0__soc_i; + + assign tl_mbx_pcie1__soc_o = tl_s1n_12_ds_h2d[8]; + assign tl_s1n_12_ds_d2h[8] = tl_mbx_pcie1__soc_i; + + assign tl_racl_ctrl_o = tl_s1n_12_ds_h2d[9]; + assign tl_s1n_12_ds_d2h[9] = tl_racl_ctrl_i; + + assign tl_ac_range_check_o = tl_s1n_12_ds_h2d[10]; + assign tl_s1n_12_ds_d2h[10] = tl_ac_range_check_i; + + assign tl_s1n_12_us_h2d = tl_mbx_i; + assign tl_mbx_o = tl_s1n_12_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_12 = 4'd11; + if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_MBX0__SOC)) == ADDR_SPACE_MBX0__SOC) begin + dev_sel_s1n_12 = 4'd0; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_MBX1__SOC)) == ADDR_SPACE_MBX1__SOC) begin + dev_sel_s1n_12 = 4'd1; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_MBX2__SOC)) == ADDR_SPACE_MBX2__SOC) begin + dev_sel_s1n_12 = 4'd2; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_MBX3__SOC)) == ADDR_SPACE_MBX3__SOC) begin + dev_sel_s1n_12 = 4'd3; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_MBX4__SOC)) == ADDR_SPACE_MBX4__SOC) begin + dev_sel_s1n_12 = 4'd4; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_MBX5__SOC)) == ADDR_SPACE_MBX5__SOC) begin + dev_sel_s1n_12 = 4'd5; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_MBX6__SOC)) == ADDR_SPACE_MBX6__SOC) begin + dev_sel_s1n_12 = 4'd6; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE0__SOC)) == ADDR_SPACE_MBX_PCIE0__SOC) begin + dev_sel_s1n_12 = 4'd7; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_MBX_PCIE1__SOC)) == ADDR_SPACE_MBX_PCIE1__SOC) begin + dev_sel_s1n_12 = 4'd8; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_RACL_CTRL)) == ADDR_SPACE_RACL_CTRL) begin + dev_sel_s1n_12 = 4'd9; + + end else if ((tl_s1n_12_us_h2d.a_address & + ~(ADDR_MASK_AC_RANGE_CHECK)) == ADDR_SPACE_AC_RANGE_CHECK) begin + dev_sel_s1n_12 = 4'd10; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (44'h0), + .DRspDepth (44'h0), + .N (11) + ) u_s1n_12 ( + .clk_i (clk_mbx_i), + .rst_ni (rst_mbx_ni), + .tl_h_i (tl_s1n_12_us_h2d), + .tl_h_o (tl_s1n_12_us_d2h), + .tl_d_o (tl_s1n_12_ds_h2d), + .tl_d_i (tl_s1n_12_ds_d2h), + .dev_select_i (dev_sel_s1n_12) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_mbx/xbar_mbx.core b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/xbar_mbx.core new file mode 100644 index 00000000000..8aead0428c8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_mbx/xbar_mbx.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_mbx core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling_no_ibex:xbar_mbx:0.1" +description: "Generated RTL xbar_mbx" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_mbx_pkg.sv + - rtl/autogen/xbar_mbx.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_mbx diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson new file mode 100644 index 00000000000..b0228ed1ee2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson @@ -0,0 +1,691 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson -o hw/top_darjeeling_no_ibex/ + +{ + name: peri + clock_srcs: + { + clk_peri_i: io_div4 + } + clock_group: infra + reset: rst_peri_ni + reset_connections: + { + rst_peri_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + main: + [ + uart0 + i2c0 + gpio + spi_host0 + spi_device + pwrmgr_aon + rstmgr_aon + clkmgr_aon + pinmux_aon + otp_ctrl.core + otp_macro.prim + lc_ctrl.regs + alert_handler + ast + sram_ctrl_ret_aon.ram + sram_ctrl_ret_aon.regs + aon_timer_aon + soc_dbg_ctrl.core + ] + } + nodes: + [ + { + name: main + type: host + addr_space: hart + clock: clk_peri_i + reset: rst_peri_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: uart0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: uart + addr_range: + [ + { + base_addrs: + { + hart: 0x30010000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: i2c0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: i2c + addr_range: + [ + { + base_addrs: + { + hart: 0x30080000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: gpio + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: gpio + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_host0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_host + addr_range: + [ + { + base_addrs: + { + hart: 0x30300000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_device + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_device + addr_range: + [ + { + base_addrs: + { + hart: 0x30310000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pwrmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pwrmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30400000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: rstmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: rstmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30410000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: clkmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: clkmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30420000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pinmux_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pinmux + addr_range: + [ + { + base_addrs: + { + hart: 0x30460000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_ctrl.core + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30130000 + } + size_byte: 0x8000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_macro.prim + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_macro + addr_range: + [ + { + base_addrs: + { + hart: 0x30140000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: lc_ctrl.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: lc_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30150000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: alert_handler + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: alert_handler + addr_range: + [ + { + base_addrs: + { + hart: 0x30160000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30500000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.ram + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30600000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: aon_timer_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: aon_timer + addr_range: + [ + { + base_addrs: + { + hart: 0x30470000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: ast + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: ast + addr_range: + [ + { + base_addrs: + { + hart: 0x30480000 + } + size_byte: 0x400 + } + ] + xbar: false + stub: true + req_fifo_pass: true + } + { + name: soc_dbg_ctrl.core + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: soc_dbg_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30170000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_peri_i + type: xbar + inter_signal_list: + [ + { + name: tl_main + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: peri + width: 1 + default: "" + top_signame: main_tl_peri + index: -1 + } + { + name: tl_uart0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: uart0_tl + index: -1 + } + { + name: tl_i2c0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: i2c0_tl + index: -1 + } + { + name: tl_gpio + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: gpio_tl + index: -1 + } + { + name: tl_spi_host0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: spi_host0_tl + index: -1 + } + { + name: tl_spi_device + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: spi_device_tl + index: -1 + } + { + name: tl_pwrmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: pwrmgr_aon_tl + index: -1 + } + { + name: tl_rstmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: rstmgr_aon_tl + index: -1 + } + { + name: tl_clkmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: clkmgr_aon_tl + index: -1 + } + { + name: tl_pinmux_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: pinmux_aon_tl + index: -1 + } + { + name: tl_otp_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: otp_ctrl_core_tl + index: -1 + } + { + name: tl_otp_macro__prim + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: otp_macro_prim_tl + index: -1 + } + { + name: tl_lc_ctrl__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: tl_alert_handler + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: alert_handler_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + { + name: tl_aon_timer_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: aon_timer_aon_tl + index: -1 + } + { + name: tl_ast + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + external: true + top_signame: ast_tl + conn_type: false + index: -1 + } + { + name: tl_soc_dbg_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri + width: 1 + default: "" + top_signame: soc_dbg_ctrl_core_tl + index: -1 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_peri/data/autogen/xbar_peri.hjson new file mode 100644 index 00000000000..c7d9996befa --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/data/autogen/xbar_peri.hjson @@ -0,0 +1,131 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_peri" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_main" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_uart0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_i2c0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_gpio" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_spi_host0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_spi_device" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_pwrmgr_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rstmgr_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_clkmgr_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_pinmux_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_otp_ctrl__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_otp_macro__prim" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_lc_ctrl__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_alert_handler" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_ret_aon__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_ret_aon__ram" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_aon_timer_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_ast" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_soc_dbg_ctrl__core" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 00000000000..5c465362398 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_peri dut(); + +`DRIVE_CLK(clk_peri_i) + +initial force dut.clk_peri_i = clk_peri_i; + +// TODO, all resets tie together +initial force dut.rst_peri_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(main, dut, clk_peri_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(uart0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(i2c0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(gpio, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(spi_host0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(spi_device, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(pwrmgr_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(rstmgr_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(clkmgr_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(pinmux_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(otp_ctrl__core, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(otp_macro__prim, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(lc_ctrl__regs, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(alert_handler, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon__regs, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon__ram, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(aon_timer_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(ast, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(soc_dbg_ctrl__core, dut, clk_peri_i, rst_n) diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_cov_excl.el new file mode 100644 index 00000000000..645d899b062 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_peri +Block 1 "0" "assign unused_scanmode = scanmode_i;" diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_cover.cfg new file mode 100644 index 00000000000..529dc19e418 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_cover.cfg @@ -0,0 +1,95 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_uart0_o.a_address[15:6] +-node tb.dut tl_uart0_o.a_address[27:17] +-node tb.dut tl_uart0_o.a_address[31:30] +-node tb.dut tl_i2c0_o.a_address[18:7] +-node tb.dut tl_i2c0_o.a_address[27:20] +-node tb.dut tl_i2c0_o.a_address[31:30] +-node tb.dut tl_gpio_o.a_address[27:8] +-node tb.dut tl_gpio_o.a_address[31:30] +-node tb.dut tl_spi_host0_o.a_address[19:6] +-node tb.dut tl_spi_host0_o.a_address[27:22] +-node tb.dut tl_spi_host0_o.a_address[31:30] +-node tb.dut tl_spi_device_o.a_address[15:13] +-node tb.dut tl_spi_device_o.a_address[19:17] +-node tb.dut tl_spi_device_o.a_address[27:22] +-node tb.dut tl_spi_device_o.a_address[31:30] +-node tb.dut tl_pwrmgr_aon_o.a_address[21:7] +-node tb.dut tl_pwrmgr_aon_o.a_address[27:23] +-node tb.dut tl_pwrmgr_aon_o.a_address[31:30] +-node tb.dut tl_rstmgr_aon_o.a_address[15:7] +-node tb.dut tl_rstmgr_aon_o.a_address[21:17] +-node tb.dut tl_rstmgr_aon_o.a_address[27:23] +-node tb.dut tl_rstmgr_aon_o.a_address[31:30] +-node tb.dut tl_clkmgr_aon_o.a_address[16:6] +-node tb.dut tl_clkmgr_aon_o.a_address[21:18] +-node tb.dut tl_clkmgr_aon_o.a_address[27:23] +-node tb.dut tl_clkmgr_aon_o.a_address[31:30] +-node tb.dut tl_pinmux_aon_o.a_address[16:11] +-node tb.dut tl_pinmux_aon_o.a_address[21:19] +-node tb.dut tl_pinmux_aon_o.a_address[27:23] +-node tb.dut tl_pinmux_aon_o.a_address[31:30] +-node tb.dut tl_otp_ctrl__core_o.a_address[15:15] +-node tb.dut tl_otp_ctrl__core_o.a_address[19:18] +-node tb.dut tl_otp_ctrl__core_o.a_address[27:21] +-node tb.dut tl_otp_ctrl__core_o.a_address[31:30] +-node tb.dut tl_otp_macro__prim_o.a_address[17:5] +-node tb.dut tl_otp_macro__prim_o.a_address[19:19] +-node tb.dut tl_otp_macro__prim_o.a_address[27:21] +-node tb.dut tl_otp_macro__prim_o.a_address[31:30] +-node tb.dut tl_lc_ctrl__regs_o.a_address[15:8] +-node tb.dut tl_lc_ctrl__regs_o.a_address[17:17] +-node tb.dut tl_lc_ctrl__regs_o.a_address[19:19] +-node tb.dut tl_lc_ctrl__regs_o.a_address[27:21] +-node tb.dut tl_lc_ctrl__regs_o.a_address[31:30] +-node tb.dut tl_alert_handler_o.a_address[16:11] +-node tb.dut tl_alert_handler_o.a_address[19:19] +-node tb.dut tl_alert_handler_o.a_address[27:21] +-node tb.dut tl_alert_handler_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[19:6] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[21:21] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[27:23] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[20:12] +-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[27:23] +-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[31:30] +-node tb.dut tl_aon_timer_aon_o.a_address[15:6] +-node tb.dut tl_aon_timer_aon_o.a_address[21:19] +-node tb.dut tl_aon_timer_aon_o.a_address[27:23] +-node tb.dut tl_aon_timer_aon_o.a_address[31:30] +-node tb.dut tl_ast_o.a_address[18:10] +-node tb.dut tl_ast_o.a_address[21:20] +-node tb.dut tl_ast_o.a_address[27:23] +-node tb.dut tl_ast_o.a_address[31:30] +-node tb.dut tl_soc_dbg_ctrl__core_o.a_address[15:5] +-node tb.dut tl_soc_dbg_ctrl__core_o.a_address[19:19] +-node tb.dut tl_soc_dbg_ctrl__core_o.a_address[27:21] +-node tb.dut tl_soc_dbg_ctrl__core_o.a_address[31:30] + +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 00000000000..93268bda73b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,86 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"uart0", '{ + '{32'h30010000, 32'h3001003f} + }}, + '{"i2c0", '{ + '{32'h30080000, 32'h3008007f} + }}, + '{"gpio", '{ + '{32'h30000000, 32'h300000ff} + }}, + '{"spi_host0", '{ + '{32'h30300000, 32'h3030003f} + }}, + '{"spi_device", '{ + '{32'h30310000, 32'h30311fff} + }}, + '{"pwrmgr_aon", '{ + '{32'h30400000, 32'h3040007f} + }}, + '{"rstmgr_aon", '{ + '{32'h30410000, 32'h3041007f} + }}, + '{"clkmgr_aon", '{ + '{32'h30420000, 32'h3042003f} + }}, + '{"pinmux_aon", '{ + '{32'h30460000, 32'h304607ff} + }}, + '{"otp_ctrl__core", '{ + '{32'h30130000, 32'h30137fff} + }}, + '{"otp_macro__prim", '{ + '{32'h30140000, 32'h3014001f} + }}, + '{"lc_ctrl__regs", '{ + '{32'h30150000, 32'h301500ff} + }}, + '{"alert_handler", '{ + '{32'h30160000, 32'h301607ff} + }}, + '{"sram_ctrl_ret_aon__regs", '{ + '{32'h30500000, 32'h3050003f} + }}, + '{"sram_ctrl_ret_aon__ram", '{ + '{32'h30600000, 32'h30600fff} + }}, + '{"aon_timer_aon", '{ + '{32'h30470000, 32'h3047003f} + }}, + '{"ast", '{ + '{32'h30480000, 32'h304803ff} + }}, + '{"soc_dbg_ctrl__core", '{ + '{32'h30170000, 32'h3017001f} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"main", 0, '{ + "uart0", + "i2c0", + "gpio", + "spi_host0", + "spi_device", + "pwrmgr_aon", + "rstmgr_aon", + "clkmgr_aon", + "pinmux_aon", + "otp_ctrl__core", + "otp_macro__prim", + "lc_ctrl__regs", + "alert_handler", + "ast", + "sram_ctrl_ret_aon__ram", + "sram_ctrl_ret_aon__regs", + "aon_timer_aon", + "soc_dbg_ctrl__core"}} +}; diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_bind.core b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_bind.core new file mode 100644 index 00000000000..5156003a9f1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_peri_bind:0.1" +description: "XBAR peri assertion bind" +filesets: + files_dv: + files: + - xbar_peri_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv new file mode 100644 index 00000000000..e970e54d436 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv @@ -0,0 +1,126 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_bind module generated by `tlgen.py` tool for assertions +module xbar_peri_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_peri tlul_assert #(.EndpointType("Device")) tlul_assert_host_main ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_main_i), + .d2h (tl_main_o) + ); + + // Device interfaces + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_uart0_o), + .d2h (tl_uart0_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_i2c0_o), + .d2h (tl_i2c0_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_gpio ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_gpio_o), + .d2h (tl_gpio_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_spi_host0_o), + .d2h (tl_spi_host0_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_device ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_spi_device_o), + .d2h (tl_spi_device_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pwrmgr_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_pwrmgr_aon_o), + .d2h (tl_pwrmgr_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rstmgr_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_rstmgr_aon_o), + .d2h (tl_rstmgr_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_clkmgr_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_clkmgr_aon_o), + .d2h (tl_clkmgr_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pinmux_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_pinmux_aon_o), + .d2h (tl_pinmux_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_ctrl__core ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_otp_ctrl__core_o), + .d2h (tl_otp_ctrl__core_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_macro__prim ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_otp_macro__prim_o), + .d2h (tl_otp_macro__prim_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_lc_ctrl__regs ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_lc_ctrl__regs_o), + .d2h (tl_lc_ctrl__regs_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_alert_handler ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_alert_handler_o), + .d2h (tl_alert_handler_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret_aon__regs ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_sram_ctrl_ret_aon__regs_o), + .d2h (tl_sram_ctrl_ret_aon__regs_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret_aon__ram ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_sram_ctrl_ret_aon__ram_o), + .d2h (tl_sram_ctrl_ret_aon__ram_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_aon_timer_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_aon_timer_aon_o), + .d2h (tl_aon_timer_aon_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_ast ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_ast_o), + .d2h (tl_ast_i) + ); + bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_soc_dbg_ctrl__core ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_soc_dbg_ctrl__core_o), + .d2h (tl_soc_dbg_ctrl__core_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_sim.core b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_sim.core new file mode 100644 index 00000000000..143ca48481a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_peri_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling_no_ibex:xbar_peri + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_no_ibex_xbar_peri_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson new file mode 100644 index 00000000000..da378dfd013 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_peri + + // Top level dut name (sv module). + dut: xbar_peri + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling_no_ibex + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv new file mode 100644 index 00000000000..988065d4e26 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv @@ -0,0 +1,75 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_peri package generated by `tlgen.py` tool + +package tl_peri_pkg; + + localparam logic [31:0] ADDR_SPACE_UART0 = 32'h 30010000; + localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 30080000; + localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 30000000; + localparam logic [31:0] ADDR_SPACE_SPI_HOST0 = 32'h 30300000; + localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 30310000; + localparam logic [31:0] ADDR_SPACE_PWRMGR_AON = 32'h 30400000; + localparam logic [31:0] ADDR_SPACE_RSTMGR_AON = 32'h 30410000; + localparam logic [31:0] ADDR_SPACE_CLKMGR_AON = 32'h 30420000; + localparam logic [31:0] ADDR_SPACE_PINMUX_AON = 32'h 30460000; + localparam logic [31:0] ADDR_SPACE_OTP_CTRL__CORE = 32'h 30130000; + localparam logic [31:0] ADDR_SPACE_OTP_MACRO__PRIM = 32'h 30140000; + localparam logic [31:0] ADDR_SPACE_LC_CTRL__REGS = 32'h 30150000; + localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 30160000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON__REGS = 32'h 30500000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON__RAM = 32'h 30600000; + localparam logic [31:0] ADDR_SPACE_AON_TIMER_AON = 32'h 30470000; + localparam logic [31:0] ADDR_SPACE_AST = 32'h 30480000; + localparam logic [31:0] ADDR_SPACE_SOC_DBG_CTRL__CORE = 32'h 30170000; + + localparam logic [31:0] ADDR_MASK_UART0 = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_GPIO = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_SPI_HOST0 = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00001fff; + localparam logic [31:0] ADDR_MASK_PWRMGR_AON = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_CLKMGR_AON = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_PINMUX_AON = 32'h 000007ff; + localparam logic [31:0] ADDR_MASK_OTP_CTRL__CORE = 32'h 00007fff; + localparam logic [31:0] ADDR_MASK_OTP_MACRO__PRIM = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_LC_CTRL__REGS = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_ALERT_HANDLER = 32'h 000007ff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON__REGS = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON__RAM = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_AON_TIMER_AON = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_AST = 32'h 000003ff; + localparam logic [31:0] ADDR_MASK_SOC_DBG_CTRL__CORE = 32'h 0000001f; + + localparam int N_HOST = 1; + localparam int N_DEVICE = 18; + + typedef enum int { + TlUart0 = 0, + TlI2C0 = 1, + TlGpio = 2, + TlSpiHost0 = 3, + TlSpiDevice = 4, + TlPwrmgrAon = 5, + TlRstmgrAon = 6, + TlClkmgrAon = 7, + TlPinmuxAon = 8, + TlOtpCtrlCore = 9, + TlOtpMacroPrim = 10, + TlLcCtrlRegs = 11, + TlAlertHandler = 12, + TlSramCtrlRetAonRegs = 13, + TlSramCtrlRetAonRam = 14, + TlAonTimerAon = 15, + TlAst = 16, + TlSocDbgCtrlCore = 17 + } tl_device_e; + + typedef enum int { + TlMain = 0 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri/rtl/autogen/xbar_peri.sv new file mode 100644 index 00000000000..c72908bfcf9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/rtl/autogen/xbar_peri.sv @@ -0,0 +1,251 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// main +// -> s1n_19 +// -> uart0 +// -> i2c0 +// -> gpio +// -> spi_host0 +// -> spi_device +// -> pwrmgr_aon +// -> rstmgr_aon +// -> clkmgr_aon +// -> pinmux_aon +// -> otp_ctrl.core +// -> otp_macro.prim +// -> lc_ctrl.regs +// -> alert_handler +// -> ast +// -> sram_ctrl_ret_aon.ram +// -> sram_ctrl_ret_aon.regs +// -> aon_timer_aon +// -> soc_dbg_ctrl.core + +module xbar_peri ( + input clk_peri_i, + input rst_peri_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_main_i, + output tlul_pkg::tl_d2h_t tl_main_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_uart0_o, + input tlul_pkg::tl_d2h_t tl_uart0_i, + output tlul_pkg::tl_h2d_t tl_i2c0_o, + input tlul_pkg::tl_d2h_t tl_i2c0_i, + output tlul_pkg::tl_h2d_t tl_gpio_o, + input tlul_pkg::tl_d2h_t tl_gpio_i, + output tlul_pkg::tl_h2d_t tl_spi_host0_o, + input tlul_pkg::tl_d2h_t tl_spi_host0_i, + output tlul_pkg::tl_h2d_t tl_spi_device_o, + input tlul_pkg::tl_d2h_t tl_spi_device_i, + output tlul_pkg::tl_h2d_t tl_pwrmgr_aon_o, + input tlul_pkg::tl_d2h_t tl_pwrmgr_aon_i, + output tlul_pkg::tl_h2d_t tl_rstmgr_aon_o, + input tlul_pkg::tl_d2h_t tl_rstmgr_aon_i, + output tlul_pkg::tl_h2d_t tl_clkmgr_aon_o, + input tlul_pkg::tl_d2h_t tl_clkmgr_aon_i, + output tlul_pkg::tl_h2d_t tl_pinmux_aon_o, + input tlul_pkg::tl_d2h_t tl_pinmux_aon_i, + output tlul_pkg::tl_h2d_t tl_otp_ctrl__core_o, + input tlul_pkg::tl_d2h_t tl_otp_ctrl__core_i, + output tlul_pkg::tl_h2d_t tl_otp_macro__prim_o, + input tlul_pkg::tl_d2h_t tl_otp_macro__prim_i, + output tlul_pkg::tl_h2d_t tl_lc_ctrl__regs_o, + input tlul_pkg::tl_d2h_t tl_lc_ctrl__regs_i, + output tlul_pkg::tl_h2d_t tl_alert_handler_o, + input tlul_pkg::tl_d2h_t tl_alert_handler_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_aon__regs_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon__regs_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_aon__ram_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon__ram_i, + output tlul_pkg::tl_h2d_t tl_aon_timer_aon_o, + input tlul_pkg::tl_d2h_t tl_aon_timer_aon_i, + output tlul_pkg::tl_h2d_t tl_ast_o, + input tlul_pkg::tl_d2h_t tl_ast_i, + output tlul_pkg::tl_h2d_t tl_soc_dbg_ctrl__core_o, + input tlul_pkg::tl_d2h_t tl_soc_dbg_ctrl__core_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_peri_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_19_us_h2d ; + tl_d2h_t tl_s1n_19_us_d2h ; + + + tl_h2d_t tl_s1n_19_ds_h2d [18]; + tl_d2h_t tl_s1n_19_ds_d2h [18]; + + // Create steering signal + logic [4:0] dev_sel_s1n_19; + + + + assign tl_uart0_o = tl_s1n_19_ds_h2d[0]; + assign tl_s1n_19_ds_d2h[0] = tl_uart0_i; + + assign tl_i2c0_o = tl_s1n_19_ds_h2d[1]; + assign tl_s1n_19_ds_d2h[1] = tl_i2c0_i; + + assign tl_gpio_o = tl_s1n_19_ds_h2d[2]; + assign tl_s1n_19_ds_d2h[2] = tl_gpio_i; + + assign tl_spi_host0_o = tl_s1n_19_ds_h2d[3]; + assign tl_s1n_19_ds_d2h[3] = tl_spi_host0_i; + + assign tl_spi_device_o = tl_s1n_19_ds_h2d[4]; + assign tl_s1n_19_ds_d2h[4] = tl_spi_device_i; + + assign tl_pwrmgr_aon_o = tl_s1n_19_ds_h2d[5]; + assign tl_s1n_19_ds_d2h[5] = tl_pwrmgr_aon_i; + + assign tl_rstmgr_aon_o = tl_s1n_19_ds_h2d[6]; + assign tl_s1n_19_ds_d2h[6] = tl_rstmgr_aon_i; + + assign tl_clkmgr_aon_o = tl_s1n_19_ds_h2d[7]; + assign tl_s1n_19_ds_d2h[7] = tl_clkmgr_aon_i; + + assign tl_pinmux_aon_o = tl_s1n_19_ds_h2d[8]; + assign tl_s1n_19_ds_d2h[8] = tl_pinmux_aon_i; + + assign tl_otp_ctrl__core_o = tl_s1n_19_ds_h2d[9]; + assign tl_s1n_19_ds_d2h[9] = tl_otp_ctrl__core_i; + + assign tl_otp_macro__prim_o = tl_s1n_19_ds_h2d[10]; + assign tl_s1n_19_ds_d2h[10] = tl_otp_macro__prim_i; + + assign tl_lc_ctrl__regs_o = tl_s1n_19_ds_h2d[11]; + assign tl_s1n_19_ds_d2h[11] = tl_lc_ctrl__regs_i; + + assign tl_alert_handler_o = tl_s1n_19_ds_h2d[12]; + assign tl_s1n_19_ds_d2h[12] = tl_alert_handler_i; + + assign tl_ast_o = tl_s1n_19_ds_h2d[13]; + assign tl_s1n_19_ds_d2h[13] = tl_ast_i; + + assign tl_sram_ctrl_ret_aon__ram_o = tl_s1n_19_ds_h2d[14]; + assign tl_s1n_19_ds_d2h[14] = tl_sram_ctrl_ret_aon__ram_i; + + assign tl_sram_ctrl_ret_aon__regs_o = tl_s1n_19_ds_h2d[15]; + assign tl_s1n_19_ds_d2h[15] = tl_sram_ctrl_ret_aon__regs_i; + + assign tl_aon_timer_aon_o = tl_s1n_19_ds_h2d[16]; + assign tl_s1n_19_ds_d2h[16] = tl_aon_timer_aon_i; + + assign tl_soc_dbg_ctrl__core_o = tl_s1n_19_ds_h2d[17]; + assign tl_s1n_19_ds_d2h[17] = tl_soc_dbg_ctrl__core_i; + + assign tl_s1n_19_us_h2d = tl_main_i; + assign tl_main_o = tl_s1n_19_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_19 = 5'd18; + if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin + dev_sel_s1n_19 = 5'd0; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin + dev_sel_s1n_19 = 5'd1; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin + dev_sel_s1n_19 = 5'd2; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin + dev_sel_s1n_19 = 5'd3; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin + dev_sel_s1n_19 = 5'd4; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin + dev_sel_s1n_19 = 5'd5; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin + dev_sel_s1n_19 = 5'd6; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin + dev_sel_s1n_19 = 5'd7; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin + dev_sel_s1n_19 = 5'd8; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_OTP_CTRL__CORE)) == ADDR_SPACE_OTP_CTRL__CORE) begin + dev_sel_s1n_19 = 5'd9; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_OTP_MACRO__PRIM)) == ADDR_SPACE_OTP_MACRO__PRIM) begin + dev_sel_s1n_19 = 5'd10; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_LC_CTRL__REGS)) == ADDR_SPACE_LC_CTRL__REGS) begin + dev_sel_s1n_19 = 5'd11; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin + dev_sel_s1n_19 = 5'd12; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_AST)) == ADDR_SPACE_AST) begin + dev_sel_s1n_19 = 5'd13; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == ADDR_SPACE_SRAM_CTRL_RET_AON__RAM) begin + dev_sel_s1n_19 = 5'd14; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == ADDR_SPACE_SRAM_CTRL_RET_AON__REGS) begin + dev_sel_s1n_19 = 5'd15; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_AON_TIMER_AON)) == ADDR_SPACE_AON_TIMER_AON) begin + dev_sel_s1n_19 = 5'd16; + + end else if ((tl_s1n_19_us_h2d.a_address & + ~(ADDR_MASK_SOC_DBG_CTRL__CORE)) == ADDR_SPACE_SOC_DBG_CTRL__CORE) begin + dev_sel_s1n_19 = 5'd17; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (72'h0), + .DRspDepth (72'h0), + .N (18) + ) u_s1n_19 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .tl_h_i (tl_s1n_19_us_h2d), + .tl_h_o (tl_s1n_19_us_d2h), + .tl_d_o (tl_s1n_19_ds_h2d), + .tl_d_i (tl_s1n_19_ds_d2h), + .dev_select_i (dev_sel_s1n_19) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri/xbar_peri.core b/hw/top_darjeeling_no_ibex/ip/xbar_peri/xbar_peri.core new file mode 100644 index 00000000000..f745df73d2f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri/xbar_peri.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling_no_ibex:xbar_peri:0.1" +description: "Generated RTL xbar_peri" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_peri_pkg.sv + - rtl/autogen/xbar_peri.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_peri diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/data/autogen/xbar_peri_no_ibex.gen.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/data/autogen/xbar_peri_no_ibex.gen.hjson new file mode 100644 index 00000000000..14a78a064e7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/data/autogen/xbar_peri_no_ibex.gen.hjson @@ -0,0 +1,724 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson -o hw/top_darjeeling_no_ibex/ + +{ + name: peri_no_ibex + clock_srcs: + { + clk_peri_i: io_div4 + } + clock_group: infra + reset: rst_peri_ni + reset_connections: + { + rst_peri_ni: + { + name: lc_io_div4 + domain: "0" + } + } + clock_connections: + { + clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra + } + domain: + [ + "0" + ] + connections: + { + main_no_ibex: + [ + uart0 + i2c0 + gpio + spi_host0 + spi_device + rv_timer + pwrmgr_aon + rstmgr_aon + clkmgr_aon + pinmux_aon + otp_ctrl.core + otp_macro.prim + lc_ctrl.regs + alert_handler + ast + sram_ctrl_ret_aon.ram + sram_ctrl_ret_aon.regs + aon_timer_aon + soc_dbg_ctrl.core + ] + } + nodes: + [ + { + name: main_no_ibex + type: host + addr_space: hart + clock: clk_peri_i + reset: rst_peri_ni + xbar: true + pipeline: false + stub: false + inst_type: "" + req_fifo_pass: true + rsp_fifo_pass: true + } + { + name: uart0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: uart + addr_range: + [ + { + base_addrs: + { + hart: 0x30010000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: i2c0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: i2c + addr_range: + [ + { + base_addrs: + { + hart: 0x30080000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: gpio + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: gpio + addr_range: + [ + { + base_addrs: + { + hart: 0x30000000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_host0 + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_host + addr_range: + [ + { + base_addrs: + { + hart: 0x30300000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: spi_device + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: spi_device + addr_range: + [ + { + base_addrs: + { + hart: 0x30310000 + } + size_byte: 0x2000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: rv_timer + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: rv_timer + addr_range: + [ + { + base_addrs: + { + hart: 0x30100000 + } + size_byte: 0x200 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pwrmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pwrmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30400000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: rstmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: rstmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30410000 + } + size_byte: 0x80 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: clkmgr_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: clkmgr + addr_range: + [ + { + base_addrs: + { + hart: 0x30420000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: pinmux_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: pinmux + addr_range: + [ + { + base_addrs: + { + hart: 0x30460000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_ctrl.core + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30130000 + } + size_byte: 0x8000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: otp_macro.prim + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: otp_macro + addr_range: + [ + { + base_addrs: + { + hart: 0x30140000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: lc_ctrl.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: lc_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30150000 + } + size_byte: 0x100 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: alert_handler + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: alert_handler + addr_range: + [ + { + base_addrs: + { + hart: 0x30160000 + } + size_byte: 0x800 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.regs + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30500000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: sram_ctrl_ret_aon.ram + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: sram_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30600000 + } + size_byte: 0x1000 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: aon_timer_aon + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: aon_timer + addr_range: + [ + { + base_addrs: + { + hart: 0x30470000 + } + size_byte: 0x40 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + { + name: ast + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: ast + addr_range: + [ + { + base_addrs: + { + hart: 0x30480000 + } + size_byte: 0x400 + } + ] + xbar: false + stub: true + req_fifo_pass: true + } + { + name: soc_dbg_ctrl.core + type: device + clock: clk_peri_i + reset: rst_peri_ni + pipeline: false + inst_type: soc_dbg_ctrl + addr_range: + [ + { + base_addrs: + { + hart: 0x30170000 + } + size_byte: 0x20 + } + ] + xbar: false + stub: false + req_fifo_pass: true + } + ] + addr_spaces: + [ + hart + ] + clock: clk_peri_i + type: xbar + inter_signal_list: + [ + { + name: tl_main_no_ibex + struct: tl + package: tlul_pkg + type: req_rsp + act: rsp + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: main_no_ibex_tl_peri_no_ibex + index: -1 + } + { + name: tl_uart0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: uart0_tl + index: -1 + } + { + name: tl_i2c0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: i2c0_tl + index: -1 + } + { + name: tl_gpio + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: gpio_tl + index: -1 + } + { + name: tl_spi_host0 + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: spi_host0_tl + index: -1 + } + { + name: tl_spi_device + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: spi_device_tl + index: -1 + } + { + name: tl_rv_timer + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: rv_timer_tl + index: -1 + } + { + name: tl_pwrmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: pwrmgr_aon_tl + index: -1 + } + { + name: tl_rstmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: rstmgr_aon_tl + index: -1 + } + { + name: tl_clkmgr_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: clkmgr_aon_tl + index: -1 + } + { + name: tl_pinmux_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: pinmux_aon_tl + index: -1 + } + { + name: tl_otp_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: otp_ctrl_core_tl + index: -1 + } + { + name: tl_otp_macro__prim + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: otp_macro_prim_tl + index: -1 + } + { + name: tl_lc_ctrl__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: lc_ctrl_regs_tl + index: -1 + } + { + name: tl_alert_handler + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: alert_handler_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__regs + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: sram_ctrl_ret_aon_regs_tl + index: -1 + } + { + name: tl_sram_ctrl_ret_aon__ram + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: sram_ctrl_ret_aon_ram_tl + index: -1 + } + { + name: tl_aon_timer_aon + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: aon_timer_aon_tl + index: -1 + } + { + name: tl_ast + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + external: true + top_signame: ast_tl + conn_type: false + index: -1 + } + { + name: tl_soc_dbg_ctrl__core + struct: tl + package: tlul_pkg + type: req_rsp + act: req + inst_name: peri_no_ibex + width: 1 + default: "" + top_signame: soc_dbg_ctrl_core_tl + index: -1 + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/data/autogen/xbar_peri_no_ibex.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/data/autogen/xbar_peri_no_ibex.hjson new file mode 100644 index 00000000000..5ce13304970 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/data/autogen/xbar_peri_no_ibex.hjson @@ -0,0 +1,137 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_no_ibex comportable IP spec generated by `tlgen.py` tool +{ name: "xbar_peri_no_ibex" + clock_primary: "" + other_clock_list: [] + reset_primary: "" + other_reset_list: [] + //available_input_list: [] + + inter_signal_list: [ + // host + { struct: "tl" + type: "req_rsp" + name: "tl_main_no_ibex" + act: "rsp" + package: "tlul_pkg" + } + // device + { struct: "tl" + type: "req_rsp" + name: "tl_uart0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_i2c0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_gpio" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_spi_host0" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_spi_device" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rv_timer" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_pwrmgr_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_rstmgr_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_clkmgr_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_pinmux_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_otp_ctrl__core" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_otp_macro__prim" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_lc_ctrl__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_alert_handler" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_ret_aon__regs" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_sram_ctrl_ret_aon__ram" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_aon_timer_aon" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_ast" + act: "req" + package: "tlul_pkg" + } + { struct: "tl" + type: "req_rsp" + name: "tl_soc_dbg_ctrl__core" + act: "req" + package: "tlul_pkg" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/tb__xbar_connect.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/tb__xbar_connect.sv new file mode 100644 index 00000000000..8513e896d89 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/tb__xbar_connect.sv @@ -0,0 +1,38 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tb__xbar_connect generated by `tlgen.py` tool + +xbar_peri_no_ibex dut(); + +`DRIVE_CLK(clk_peri_i) + +initial force dut.clk_peri_i = clk_peri_i; + +// TODO, all resets tie together +initial force dut.rst_peri_ni = rst_n; + +// Host TileLink interface connections +`CONNECT_TL_HOST_IF(main_no_ibex, dut, clk_peri_i, rst_n) + +// Device TileLink interface connections +`CONNECT_TL_DEVICE_IF(uart0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(i2c0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(gpio, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(spi_host0, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(spi_device, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(rv_timer, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(pwrmgr_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(rstmgr_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(clkmgr_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(pinmux_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(otp_ctrl__core, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(otp_macro__prim, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(lc_ctrl__regs, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(alert_handler, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon__regs, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon__ram, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(aon_timer_aon, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(ast, dut, clk_peri_i, rst_n) +`CONNECT_TL_DEVICE_IF(soc_dbg_ctrl__core, dut, clk_peri_i, rst_n) diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_cov_excl.el b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_cov_excl.el new file mode 100644 index 00000000000..5ef50b1bfe4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_cov_excl.el @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cov_excl.el generated by `tlgen.py` tool + +ANNOTATION: "[NON_RTL]" +MODULE: uvm_pkg +Assert \uvm_reg_map::do_write .unnamed$$_0.unnamed$$_1 "assertion" +Assert \uvm_reg_map::do_read .unnamed$$_0.unnamed$$_1 "assertion" + +ANNOTATION: "[UNSUPPORTED] scan mode isn't available in RTL sim" +MODULE: xbar_peri_no_ibex +Block 1 "0" "assign unused_scanmode = scanmode_i;" diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_cover.cfg b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_cover.cfg new file mode 100644 index 00000000000..85e10f38212 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_cover.cfg @@ -0,0 +1,98 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_cover.cfg generated by `tlgen.py` tool + ++tree tb.dut +-module pins_if // DV construct. +-module clk_rst_if // DV construct. + +-assert legalAOpcodeErr_A +-assert sizeGTEMaskErr_A +-assert sizeMatchesMaskErr_A +-assert addrSizeAlignedErr_A + +// due to VCS issue (fixed at VCS/2020.12), can't move this part into begin...end (tgl) or after. +-node tb.dut tl_*.a_param +-node tb.dut tl_*.d_param +-node tb.dut tl_*.d_opcode[2:1] + +-moduletree prim_cdc_rand_delay // exclude DV construct. + +// [UNR] these device address bits are always 0 +-node tb.dut tl_uart0_o.a_address[15:6] +-node tb.dut tl_uart0_o.a_address[27:17] +-node tb.dut tl_uart0_o.a_address[31:30] +-node tb.dut tl_i2c0_o.a_address[18:7] +-node tb.dut tl_i2c0_o.a_address[27:20] +-node tb.dut tl_i2c0_o.a_address[31:30] +-node tb.dut tl_gpio_o.a_address[27:8] +-node tb.dut tl_gpio_o.a_address[31:30] +-node tb.dut tl_spi_host0_o.a_address[19:6] +-node tb.dut tl_spi_host0_o.a_address[27:22] +-node tb.dut tl_spi_host0_o.a_address[31:30] +-node tb.dut tl_spi_device_o.a_address[15:13] +-node tb.dut tl_spi_device_o.a_address[19:17] +-node tb.dut tl_spi_device_o.a_address[27:22] +-node tb.dut tl_spi_device_o.a_address[31:30] +-node tb.dut tl_rv_timer_o.a_address[19:9] +-node tb.dut tl_rv_timer_o.a_address[27:21] +-node tb.dut tl_rv_timer_o.a_address[31:30] +-node tb.dut tl_pwrmgr_aon_o.a_address[21:7] +-node tb.dut tl_pwrmgr_aon_o.a_address[27:23] +-node tb.dut tl_pwrmgr_aon_o.a_address[31:30] +-node tb.dut tl_rstmgr_aon_o.a_address[15:7] +-node tb.dut tl_rstmgr_aon_o.a_address[21:17] +-node tb.dut tl_rstmgr_aon_o.a_address[27:23] +-node tb.dut tl_rstmgr_aon_o.a_address[31:30] +-node tb.dut tl_clkmgr_aon_o.a_address[16:6] +-node tb.dut tl_clkmgr_aon_o.a_address[21:18] +-node tb.dut tl_clkmgr_aon_o.a_address[27:23] +-node tb.dut tl_clkmgr_aon_o.a_address[31:30] +-node tb.dut tl_pinmux_aon_o.a_address[16:11] +-node tb.dut tl_pinmux_aon_o.a_address[21:19] +-node tb.dut tl_pinmux_aon_o.a_address[27:23] +-node tb.dut tl_pinmux_aon_o.a_address[31:30] +-node tb.dut tl_otp_ctrl__core_o.a_address[15:15] +-node tb.dut tl_otp_ctrl__core_o.a_address[19:18] +-node tb.dut tl_otp_ctrl__core_o.a_address[27:21] +-node tb.dut tl_otp_ctrl__core_o.a_address[31:30] +-node tb.dut tl_otp_macro__prim_o.a_address[17:5] +-node tb.dut tl_otp_macro__prim_o.a_address[19:19] +-node tb.dut tl_otp_macro__prim_o.a_address[27:21] +-node tb.dut tl_otp_macro__prim_o.a_address[31:30] +-node tb.dut tl_lc_ctrl__regs_o.a_address[15:8] +-node tb.dut tl_lc_ctrl__regs_o.a_address[17:17] +-node tb.dut tl_lc_ctrl__regs_o.a_address[19:19] +-node tb.dut tl_lc_ctrl__regs_o.a_address[27:21] +-node tb.dut tl_lc_ctrl__regs_o.a_address[31:30] +-node tb.dut tl_alert_handler_o.a_address[16:11] +-node tb.dut tl_alert_handler_o.a_address[19:19] +-node tb.dut tl_alert_handler_o.a_address[27:21] +-node tb.dut tl_alert_handler_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[19:6] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[21:21] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[27:23] +-node tb.dut tl_sram_ctrl_ret_aon__regs_o.a_address[31:30] +-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[20:12] +-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[27:23] +-node tb.dut tl_sram_ctrl_ret_aon__ram_o.a_address[31:30] +-node tb.dut tl_aon_timer_aon_o.a_address[15:6] +-node tb.dut tl_aon_timer_aon_o.a_address[21:19] +-node tb.dut tl_aon_timer_aon_o.a_address[27:23] +-node tb.dut tl_aon_timer_aon_o.a_address[31:30] +-node tb.dut tl_ast_o.a_address[18:10] +-node tb.dut tl_ast_o.a_address[21:20] +-node tb.dut tl_ast_o.a_address[27:23] +-node tb.dut tl_ast_o.a_address[31:30] +-node tb.dut tl_soc_dbg_ctrl__core_o.a_address[15:5] +-node tb.dut tl_soc_dbg_ctrl__core_o.a_address[19:19] +-node tb.dut tl_soc_dbg_ctrl__core_o.a_address[27:21] +-node tb.dut tl_soc_dbg_ctrl__core_o.a_address[31:30] + +begin tgl + -tree tb + +tree tb.dut 1 + -node tb.dut.scanmode_i +end diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_env_pkg__params.sv new file mode 100644 index 00000000000..4523fb7c8a3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_env_pkg__params.sv @@ -0,0 +1,90 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_env_pkg__params generated by `tlgen.py` tool + + +// List of Xbar device memory map +tl_device_t xbar_devices[$] = '{ + '{"uart0", '{ + '{32'h30010000, 32'h3001003f} + }}, + '{"i2c0", '{ + '{32'h30080000, 32'h3008007f} + }}, + '{"gpio", '{ + '{32'h30000000, 32'h300000ff} + }}, + '{"spi_host0", '{ + '{32'h30300000, 32'h3030003f} + }}, + '{"spi_device", '{ + '{32'h30310000, 32'h30311fff} + }}, + '{"rv_timer", '{ + '{32'h30100000, 32'h301001ff} + }}, + '{"pwrmgr_aon", '{ + '{32'h30400000, 32'h3040007f} + }}, + '{"rstmgr_aon", '{ + '{32'h30410000, 32'h3041007f} + }}, + '{"clkmgr_aon", '{ + '{32'h30420000, 32'h3042003f} + }}, + '{"pinmux_aon", '{ + '{32'h30460000, 32'h304607ff} + }}, + '{"otp_ctrl__core", '{ + '{32'h30130000, 32'h30137fff} + }}, + '{"otp_macro__prim", '{ + '{32'h30140000, 32'h3014001f} + }}, + '{"lc_ctrl__regs", '{ + '{32'h30150000, 32'h301500ff} + }}, + '{"alert_handler", '{ + '{32'h30160000, 32'h301607ff} + }}, + '{"sram_ctrl_ret_aon__regs", '{ + '{32'h30500000, 32'h3050003f} + }}, + '{"sram_ctrl_ret_aon__ram", '{ + '{32'h30600000, 32'h30600fff} + }}, + '{"aon_timer_aon", '{ + '{32'h30470000, 32'h3047003f} + }}, + '{"ast", '{ + '{32'h30480000, 32'h304803ff} + }}, + '{"soc_dbg_ctrl__core", '{ + '{32'h30170000, 32'h3017001f} +}}}; + + // List of Xbar hosts +tl_host_t xbar_hosts[$] = '{ + '{"main_no_ibex", 0, '{ + "uart0", + "i2c0", + "gpio", + "spi_host0", + "spi_device", + "rv_timer", + "pwrmgr_aon", + "rstmgr_aon", + "clkmgr_aon", + "pinmux_aon", + "otp_ctrl__core", + "otp_macro__prim", + "lc_ctrl__regs", + "alert_handler", + "ast", + "sram_ctrl_ret_aon__ram", + "sram_ctrl_ret_aon__regs", + "aon_timer_aon", + "soc_dbg_ctrl__core"}} +}; diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_bind.core b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_bind.core new file mode 100644 index 00000000000..4a486da18a6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_bind.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri_no_ibex_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_peri_no_ibex_bind:0.1" +description: "XBAR peri_no_ibex assertion bind" +filesets: + files_dv: + files: + - xbar_peri_no_ibex_bind.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_bind.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_bind.sv new file mode 100644 index 00000000000..4af4aa7bb17 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_bind.sv @@ -0,0 +1,132 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_no_ibex_bind module generated by `tlgen.py` tool for assertions +module xbar_peri_no_ibex_bind; +`ifndef GATE_LEVEL + // Host interfaces + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Device")) tlul_assert_host_main_no_ibex ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_main_no_ibex_i), + .d2h (tl_main_no_ibex_o) + ); + + // Device interfaces + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_uart0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_uart0_o), + .d2h (tl_uart0_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_i2c0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_i2c0_o), + .d2h (tl_i2c0_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_gpio ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_gpio_o), + .d2h (tl_gpio_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host0 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_spi_host0_o), + .d2h (tl_spi_host0_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_device ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_spi_device_o), + .d2h (tl_spi_device_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_timer ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_rv_timer_o), + .d2h (tl_rv_timer_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_pwrmgr_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_pwrmgr_aon_o), + .d2h (tl_pwrmgr_aon_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_rstmgr_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_rstmgr_aon_o), + .d2h (tl_rstmgr_aon_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_clkmgr_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_clkmgr_aon_o), + .d2h (tl_clkmgr_aon_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_pinmux_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_pinmux_aon_o), + .d2h (tl_pinmux_aon_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_ctrl__core ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_otp_ctrl__core_o), + .d2h (tl_otp_ctrl__core_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_macro__prim ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_otp_macro__prim_o), + .d2h (tl_otp_macro__prim_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_lc_ctrl__regs ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_lc_ctrl__regs_o), + .d2h (tl_lc_ctrl__regs_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_alert_handler ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_alert_handler_o), + .d2h (tl_alert_handler_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret_aon__regs ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_sram_ctrl_ret_aon__regs_o), + .d2h (tl_sram_ctrl_ret_aon__regs_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret_aon__ram ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_sram_ctrl_ret_aon__ram_o), + .d2h (tl_sram_ctrl_ret_aon__ram_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_aon_timer_aon ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_aon_timer_aon_o), + .d2h (tl_aon_timer_aon_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_ast ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_ast_o), + .d2h (tl_ast_i) + ); + bind xbar_peri_no_ibex tlul_assert #(.EndpointType("Host")) tlul_assert_device_soc_dbg_ctrl__core ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .h2d (tl_soc_dbg_ctrl__core_o), + .d2h (tl_soc_dbg_ctrl__core_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_sim.core b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_sim.core new file mode 100644 index 00000000000..8176cc604ef --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri_no_ibex_sim core file generated by `tlgen.py` tool +name: "lowrisc:dv:top_darjeeling_no_ibex_xbar_peri_no_ibex_sim:0.1" +description: "XBAR DV sim target" +filesets: + files_dv: + depend: + - lowrisc:top_darjeeling_no_ibex:xbar_peri_no_ibex + - lowrisc:dv:dv_utils + - lowrisc:dv:xbar_tb + - lowrisc:dv:top_darjeeling_no_ibex_xbar_peri_no_ibex_bind + files: + - tb__xbar_connect.sv: {is_include_file: true} + - xbar_env_pkg__params.sv: {is_include_file: true} + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: xbar_tb_top + filesets: + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_sim_cfg.hjson new file mode 100644 index 00000000000..b0c2517378e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/dv/autogen/xbar_peri_no_ibex_sim_cfg.hjson @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_no_ibex_sim_cfg.hjson file generated by `tlgen.py` tool +{ + name: xbar_peri_no_ibex + + // Top level dut name (sv module). + dut: xbar_peri_no_ibex + + // The name of the chip this XBAR configuration is made for. + top_chip: top_darjeeling_no_ibex + + // Testplan hjson file. + testplan: "{proj_root}/hw/ip/tlul/data/tlul_testplan.hjson" + + // Add xbar_main specific exclusion files. + vcs_cov_excl_files: ["{proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cov_excl.el"] + + // replace common cover.cfg with a generated one, which includes xbar toggle exclusions + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_darjeeling_no_ibex/ip/{dut}/dv/autogen/xbar_cover.cfg" + } + ] + // Import additional common sim cfg files. + import_cfgs: [// xbar common sim cfg file + "{proj_root}/hw/ip/tlul/generic_dv/xbar_sim_cfg.hjson"] +} diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/rtl/autogen/tl_peri_no_ibex_pkg.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/rtl/autogen/tl_peri_no_ibex_pkg.sv new file mode 100644 index 00000000000..d2a0f3f7774 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/rtl/autogen/tl_peri_no_ibex_pkg.sv @@ -0,0 +1,78 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// tl_peri_no_ibex package generated by `tlgen.py` tool + +package tl_peri_no_ibex_pkg; + + localparam logic [31:0] ADDR_SPACE_UART0 = 32'h 30010000; + localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 30080000; + localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 30000000; + localparam logic [31:0] ADDR_SPACE_SPI_HOST0 = 32'h 30300000; + localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 30310000; + localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 30100000; + localparam logic [31:0] ADDR_SPACE_PWRMGR_AON = 32'h 30400000; + localparam logic [31:0] ADDR_SPACE_RSTMGR_AON = 32'h 30410000; + localparam logic [31:0] ADDR_SPACE_CLKMGR_AON = 32'h 30420000; + localparam logic [31:0] ADDR_SPACE_PINMUX_AON = 32'h 30460000; + localparam logic [31:0] ADDR_SPACE_OTP_CTRL__CORE = 32'h 30130000; + localparam logic [31:0] ADDR_SPACE_OTP_MACRO__PRIM = 32'h 30140000; + localparam logic [31:0] ADDR_SPACE_LC_CTRL__REGS = 32'h 30150000; + localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 30160000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON__REGS = 32'h 30500000; + localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON__RAM = 32'h 30600000; + localparam logic [31:0] ADDR_SPACE_AON_TIMER_AON = 32'h 30470000; + localparam logic [31:0] ADDR_SPACE_AST = 32'h 30480000; + localparam logic [31:0] ADDR_SPACE_SOC_DBG_CTRL__CORE = 32'h 30170000; + + localparam logic [31:0] ADDR_MASK_UART0 = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_GPIO = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_SPI_HOST0 = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00001fff; + localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 000001ff; + localparam logic [31:0] ADDR_MASK_PWRMGR_AON = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_CLKMGR_AON = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_PINMUX_AON = 32'h 000007ff; + localparam logic [31:0] ADDR_MASK_OTP_CTRL__CORE = 32'h 00007fff; + localparam logic [31:0] ADDR_MASK_OTP_MACRO__PRIM = 32'h 0000001f; + localparam logic [31:0] ADDR_MASK_LC_CTRL__REGS = 32'h 000000ff; + localparam logic [31:0] ADDR_MASK_ALERT_HANDLER = 32'h 000007ff; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON__REGS = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON__RAM = 32'h 00000fff; + localparam logic [31:0] ADDR_MASK_AON_TIMER_AON = 32'h 0000003f; + localparam logic [31:0] ADDR_MASK_AST = 32'h 000003ff; + localparam logic [31:0] ADDR_MASK_SOC_DBG_CTRL__CORE = 32'h 0000001f; + + localparam int N_HOST = 1; + localparam int N_DEVICE = 19; + + typedef enum int { + TlUart0 = 0, + TlI2C0 = 1, + TlGpio = 2, + TlSpiHost0 = 3, + TlSpiDevice = 4, + TlRvTimer = 5, + TlPwrmgrAon = 6, + TlRstmgrAon = 7, + TlClkmgrAon = 8, + TlPinmuxAon = 9, + TlOtpCtrlCore = 10, + TlOtpMacroPrim = 11, + TlLcCtrlRegs = 12, + TlAlertHandler = 13, + TlSramCtrlRetAonRegs = 14, + TlSramCtrlRetAonRam = 15, + TlAonTimerAon = 16, + TlAst = 17, + TlSocDbgCtrlCore = 18 + } tl_device_e; + + typedef enum int { + TlMainNoIbex = 0 + } tl_host_e; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/rtl/autogen/xbar_peri_no_ibex.sv b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/rtl/autogen/xbar_peri_no_ibex.sv new file mode 100644 index 00000000000..1f50e4914f2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/rtl/autogen/xbar_peri_no_ibex.sv @@ -0,0 +1,261 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// xbar_peri_no_ibex module generated by `tlgen.py` tool +// all reset signals should be generated from one reset signal to not make any deadlock +// +// Interconnect +// main_no_ibex +// -> s1n_20 +// -> uart0 +// -> i2c0 +// -> gpio +// -> spi_host0 +// -> spi_device +// -> rv_timer +// -> pwrmgr_aon +// -> rstmgr_aon +// -> clkmgr_aon +// -> pinmux_aon +// -> otp_ctrl.core +// -> otp_macro.prim +// -> lc_ctrl.regs +// -> alert_handler +// -> ast +// -> sram_ctrl_ret_aon.ram +// -> sram_ctrl_ret_aon.regs +// -> aon_timer_aon +// -> soc_dbg_ctrl.core + +module xbar_peri_no_ibex ( + input clk_peri_i, + input rst_peri_ni, + + // Host interfaces + input tlul_pkg::tl_h2d_t tl_main_no_ibex_i, + output tlul_pkg::tl_d2h_t tl_main_no_ibex_o, + + // Device interfaces + output tlul_pkg::tl_h2d_t tl_uart0_o, + input tlul_pkg::tl_d2h_t tl_uart0_i, + output tlul_pkg::tl_h2d_t tl_i2c0_o, + input tlul_pkg::tl_d2h_t tl_i2c0_i, + output tlul_pkg::tl_h2d_t tl_gpio_o, + input tlul_pkg::tl_d2h_t tl_gpio_i, + output tlul_pkg::tl_h2d_t tl_spi_host0_o, + input tlul_pkg::tl_d2h_t tl_spi_host0_i, + output tlul_pkg::tl_h2d_t tl_spi_device_o, + input tlul_pkg::tl_d2h_t tl_spi_device_i, + output tlul_pkg::tl_h2d_t tl_rv_timer_o, + input tlul_pkg::tl_d2h_t tl_rv_timer_i, + output tlul_pkg::tl_h2d_t tl_pwrmgr_aon_o, + input tlul_pkg::tl_d2h_t tl_pwrmgr_aon_i, + output tlul_pkg::tl_h2d_t tl_rstmgr_aon_o, + input tlul_pkg::tl_d2h_t tl_rstmgr_aon_i, + output tlul_pkg::tl_h2d_t tl_clkmgr_aon_o, + input tlul_pkg::tl_d2h_t tl_clkmgr_aon_i, + output tlul_pkg::tl_h2d_t tl_pinmux_aon_o, + input tlul_pkg::tl_d2h_t tl_pinmux_aon_i, + output tlul_pkg::tl_h2d_t tl_otp_ctrl__core_o, + input tlul_pkg::tl_d2h_t tl_otp_ctrl__core_i, + output tlul_pkg::tl_h2d_t tl_otp_macro__prim_o, + input tlul_pkg::tl_d2h_t tl_otp_macro__prim_i, + output tlul_pkg::tl_h2d_t tl_lc_ctrl__regs_o, + input tlul_pkg::tl_d2h_t tl_lc_ctrl__regs_i, + output tlul_pkg::tl_h2d_t tl_alert_handler_o, + input tlul_pkg::tl_d2h_t tl_alert_handler_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_aon__regs_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon__regs_i, + output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_aon__ram_o, + input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon__ram_i, + output tlul_pkg::tl_h2d_t tl_aon_timer_aon_o, + input tlul_pkg::tl_d2h_t tl_aon_timer_aon_i, + output tlul_pkg::tl_h2d_t tl_ast_o, + input tlul_pkg::tl_d2h_t tl_ast_i, + output tlul_pkg::tl_h2d_t tl_soc_dbg_ctrl__core_o, + input tlul_pkg::tl_d2h_t tl_soc_dbg_ctrl__core_i, + + input prim_mubi_pkg::mubi4_t scanmode_i +); + + import tlul_pkg::*; + import tl_peri_no_ibex_pkg::*; + + // scanmode_i is currently not used, but provisioned for future use + // this assignment prevents lint warnings + logic unused_scanmode; + assign unused_scanmode = ^scanmode_i; + + tl_h2d_t tl_s1n_20_us_h2d ; + tl_d2h_t tl_s1n_20_us_d2h ; + + + tl_h2d_t tl_s1n_20_ds_h2d [19]; + tl_d2h_t tl_s1n_20_ds_d2h [19]; + + // Create steering signal + logic [4:0] dev_sel_s1n_20; + + + + assign tl_uart0_o = tl_s1n_20_ds_h2d[0]; + assign tl_s1n_20_ds_d2h[0] = tl_uart0_i; + + assign tl_i2c0_o = tl_s1n_20_ds_h2d[1]; + assign tl_s1n_20_ds_d2h[1] = tl_i2c0_i; + + assign tl_gpio_o = tl_s1n_20_ds_h2d[2]; + assign tl_s1n_20_ds_d2h[2] = tl_gpio_i; + + assign tl_spi_host0_o = tl_s1n_20_ds_h2d[3]; + assign tl_s1n_20_ds_d2h[3] = tl_spi_host0_i; + + assign tl_spi_device_o = tl_s1n_20_ds_h2d[4]; + assign tl_s1n_20_ds_d2h[4] = tl_spi_device_i; + + assign tl_rv_timer_o = tl_s1n_20_ds_h2d[5]; + assign tl_s1n_20_ds_d2h[5] = tl_rv_timer_i; + + assign tl_pwrmgr_aon_o = tl_s1n_20_ds_h2d[6]; + assign tl_s1n_20_ds_d2h[6] = tl_pwrmgr_aon_i; + + assign tl_rstmgr_aon_o = tl_s1n_20_ds_h2d[7]; + assign tl_s1n_20_ds_d2h[7] = tl_rstmgr_aon_i; + + assign tl_clkmgr_aon_o = tl_s1n_20_ds_h2d[8]; + assign tl_s1n_20_ds_d2h[8] = tl_clkmgr_aon_i; + + assign tl_pinmux_aon_o = tl_s1n_20_ds_h2d[9]; + assign tl_s1n_20_ds_d2h[9] = tl_pinmux_aon_i; + + assign tl_otp_ctrl__core_o = tl_s1n_20_ds_h2d[10]; + assign tl_s1n_20_ds_d2h[10] = tl_otp_ctrl__core_i; + + assign tl_otp_macro__prim_o = tl_s1n_20_ds_h2d[11]; + assign tl_s1n_20_ds_d2h[11] = tl_otp_macro__prim_i; + + assign tl_lc_ctrl__regs_o = tl_s1n_20_ds_h2d[12]; + assign tl_s1n_20_ds_d2h[12] = tl_lc_ctrl__regs_i; + + assign tl_alert_handler_o = tl_s1n_20_ds_h2d[13]; + assign tl_s1n_20_ds_d2h[13] = tl_alert_handler_i; + + assign tl_ast_o = tl_s1n_20_ds_h2d[14]; + assign tl_s1n_20_ds_d2h[14] = tl_ast_i; + + assign tl_sram_ctrl_ret_aon__ram_o = tl_s1n_20_ds_h2d[15]; + assign tl_s1n_20_ds_d2h[15] = tl_sram_ctrl_ret_aon__ram_i; + + assign tl_sram_ctrl_ret_aon__regs_o = tl_s1n_20_ds_h2d[16]; + assign tl_s1n_20_ds_d2h[16] = tl_sram_ctrl_ret_aon__regs_i; + + assign tl_aon_timer_aon_o = tl_s1n_20_ds_h2d[17]; + assign tl_s1n_20_ds_d2h[17] = tl_aon_timer_aon_i; + + assign tl_soc_dbg_ctrl__core_o = tl_s1n_20_ds_h2d[18]; + assign tl_s1n_20_ds_d2h[18] = tl_soc_dbg_ctrl__core_i; + + assign tl_s1n_20_us_h2d = tl_main_no_ibex_i; + assign tl_main_no_ibex_o = tl_s1n_20_us_d2h; + + always_comb begin + // default steering to generate error response if address is not within the range + dev_sel_s1n_20 = 5'd19; + if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin + dev_sel_s1n_20 = 5'd0; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin + dev_sel_s1n_20 = 5'd1; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin + dev_sel_s1n_20 = 5'd2; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin + dev_sel_s1n_20 = 5'd3; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin + dev_sel_s1n_20 = 5'd4; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin + dev_sel_s1n_20 = 5'd5; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin + dev_sel_s1n_20 = 5'd6; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin + dev_sel_s1n_20 = 5'd7; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin + dev_sel_s1n_20 = 5'd8; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin + dev_sel_s1n_20 = 5'd9; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_OTP_CTRL__CORE)) == ADDR_SPACE_OTP_CTRL__CORE) begin + dev_sel_s1n_20 = 5'd10; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_OTP_MACRO__PRIM)) == ADDR_SPACE_OTP_MACRO__PRIM) begin + dev_sel_s1n_20 = 5'd11; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_LC_CTRL__REGS)) == ADDR_SPACE_LC_CTRL__REGS) begin + dev_sel_s1n_20 = 5'd12; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin + dev_sel_s1n_20 = 5'd13; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_AST)) == ADDR_SPACE_AST) begin + dev_sel_s1n_20 = 5'd14; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == ADDR_SPACE_SRAM_CTRL_RET_AON__RAM) begin + dev_sel_s1n_20 = 5'd15; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == ADDR_SPACE_SRAM_CTRL_RET_AON__REGS) begin + dev_sel_s1n_20 = 5'd16; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_AON_TIMER_AON)) == ADDR_SPACE_AON_TIMER_AON) begin + dev_sel_s1n_20 = 5'd17; + + end else if ((tl_s1n_20_us_h2d.a_address & + ~(ADDR_MASK_SOC_DBG_CTRL__CORE)) == ADDR_SPACE_SOC_DBG_CTRL__CORE) begin + dev_sel_s1n_20 = 5'd18; +end + end + + + // Instantiation phase + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (76'h0), + .DRspDepth (76'h0), + .N (19) + ) u_s1n_20 ( + .clk_i (clk_peri_i), + .rst_ni (rst_peri_ni), + .tl_h_i (tl_s1n_20_us_h2d), + .tl_h_o (tl_s1n_20_us_d2h), + .tl_d_o (tl_s1n_20_ds_h2d), + .tl_d_i (tl_s1n_20_ds_d2h), + .dev_select_i (dev_sel_s1n_20) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/xbar_peri_no_ibex.core b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/xbar_peri_no_ibex.core new file mode 100644 index 00000000000..46f12292aa2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip/xbar_peri_no_ibex/xbar_peri_no_ibex.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# xbar_peri_no_ibex core file generated by `tlgen.py` tool +name: "lowrisc:top_darjeeling_no_ibex:xbar_peri_no_ibex:0.1" +description: "Generated RTL xbar_peri_no_ibex" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:ip:lc_ctrl_pkg + files: + - rtl/autogen/tl_peri_no_ibex_pkg.sv + - rtl/autogen/xbar_peri_no_ibex.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: xbar_peri_no_ibex diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/BUILD new file mode 100644 index 00000000000..a248d8ff350 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/BUILD @@ -0,0 +1,25 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.svg", + ]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/README.md new file mode 100644 index 00000000000..11e7d8f798a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/README.md @@ -0,0 +1,123 @@ +# Access Control Range Check (AC Range Check) + +The System on Chip (SoC) must implement differentiated security access controls for shared memory regions located outside of the Root of Trust (RoT). +To facilitate access to these memory regions, a dedicated TL-UL port is provided, connecting to the Control Network (CTN) fabric. +This document outlines the requirements for a framework, referred to as Access Control Range Check (AC Range Check). +In the proposed architecture, the AC Range Check mechanism intercepts the outgoing TL-UL bus, ensuring that only valid and authorized addresses are accessed. +Adding the AC Range Check on the TL-UL bus will likely introduce a flop stage to meet the timings, which will cause a cycle of delay for bus initiators to receive their response. + +![145](./doc/ac_range_check.svg) + +## Comparison to IOPMP + +AC Range checks on the memory bus shares similarities with an I/O Peripheral Memory Protection (IOPMP) in that both mechanisms control access to memory regions, ensuring that only authorized transactions pass through. +Like an IOPMP, AC ranges define specific address spaces and enforce permissions, preventing unauthorized access. +However, AC range checks offer a simpler implementation and verification process. + +## Parameterizable Range Registers + +The AC range check IP shall support a configurable number of range registers, allowing a flexible and granular security configuration. +The number of range registers shall be parameterizable at design time for every instance of the IP to accommodate different use cases and system requirements, providing scalability based on system size and complexity. +A typical configuration would be between 16 and 32 ranges, but the design should not be limited to those bounds. + +## Range Configuration + +Each range register shall be configured by the following mechanism: + +* **Base/Limit Register** (Top-of-Range Matching): + * The range is defined using a base address and an upper limit address, where the base represents the starting address and the limit represents the end of the range. + +The limit register should be sufficiently large to cover the whole 32-bit address space. +Each range register shall also be associated with a set of permissions that determine the allowed access types within that range. +The permission options shall include: + +* **READ:** Allows read access within the range. +* **WRITE:** Allows write access within the range. +* **EXECUTE:** Allows to execute code from this range. + +If all, READ, WRITE, and EXECUTE are cleared any access to that range shall be denied. + +## Request Matching and Permissions + +Incoming access requests (e.g., memory reads or writes) shall be compared against all enabled range registers. +Each request shall be evaluated for a match based on its address and the configured ranges. +The matching process includes: + +* **Address Match:** The request's address is checked against the ranges defined by the enabled range registers (top-of-range matching). +* **Permission Check:** For each matching range, the permissions associated with that range (READ, WRITE) are checked against the type of access requested. +* **RACL Check:** For each matching range, the RACL policy associated with that range (read_perm, write_perm) is checked against the source role of the access requested. +RACL is specified in Integrated OpenTitan: Register Access Control (RACL). + +## Access Policy + +The following policy governs the handling of access requests based on the outcome of the range and permission matching: + +* **Allowed Access:** If an incoming request matches an enabled range and the corresponding permission allows the requested operation (READ or WRITE), the request is granted, and the transaction proceeds normally. +* **Denied Access:** If the request does not match any range or matches a range but the configured permission denied the requested operation, the TL-UL response shall return an error, i.e., setting `d_error = 1` when acknowledging the request. +Further, the request is denied as follows: + * **Write Requests** Denied write requests shall be dropped, meaning no write operation is performed. + * **Read/Execute Requests:** Denied read/execute requests shall return a zero value as a response. + +Range register 0 may be used as a configurable default policy to match the whole address space. +Subsequent range configuration may overwrite this policy to allow a different behavior. +See Priority of Matching for the priority based address matching. + + +## Priority of Matching + +If a request matches multiple enabled ranges with conflicting permissions, the lowest-index enabled range determines the permissions that apply to the request. + +## Error Logging and Interrupt Mechanism + +To ensure proper tracking and response to unauthorized access attempts, the system shall implement an error logging mechanism that monitors denied access requests across all configured ranges. + +### Global Denied Access Counter + +* A **global counter** shall be maintained to track the total number of denied access requests across all enabled range registers in the system. +* The counter increments by one each time a request is denied, regardless of whether the denial results from a READ or WRITE operation. +* The counter saturates once it reaches the programmed threshold. + +### Programmable Denied Access Threshold + +* The system shall support a programmable threshold that specifies the maximum number of denied access requests before triggering a further action. +* Once the number of denied accesses reaches or exceeds this threshold, the system shall raise an interrupt to the RoT. +* Acknowledging the interrupt automatically clears the denied access counter. + +To facilitate detailed diagnostics, the system shall implement a logging mechanism for the first denied access request. +This log captures key information to help identify the cause and context of the denial. + +### First Denied Access Log + +Upon the **first denied request**, the system shall record the following information: + +* **Range Index:** Identifies the specific range responsible for denying the request. If the access is denied because no range matches, it is logged in a dedicated status bit. +* **Access Type:** Indicates whether the request was a READ, WRITE, or EXECUTE operation. +* **RACL role:** Indicates the RACL role of th request and an indicator if a RACL read or write check caused the denial. +* **Access Address:** Logs the exact address that the request attempted to access. + +### Single Event Logging + +* This logging mechanism is triggered only for the first denied access after a reset or after the log has been cleared, ensuring that only the initial violation is captured for diagnostics. +* Subsequent denied requests will not overwrite the log, preserving the information of the first event until manually cleared by the RoT. +The log is cleared automatically when the interrupt is acknowledged or manually by writing a configuration bit. + +## Enable/Disable Control and Lock Mechanism + +Each range register shall include both an enable/disable control bit and a lock mechanism. +The following controls apply: + +* **Enable/Disable** Control: Each range register can be enabled or disabled individually. +Disabled range registers shall not participate in the matching process and shall have no effect on access control decisions. +* **Lock Mechanism:** Once a range register is configured, a lock can be asserted to prevent further modification of the range's configuration. +When the lock is active, the base, mask/limit, and permission settings of the range register are immutable and cannot be altered until the system is reset. + +## Bypass Mode + +The system shall support a bypass mode controlled via a bypass_wire signal. +The bypass_signal shall be driven by a 8-bit encoded multi-bit encoded signal in the ROT-controlled register space. +A single bypass_signal shall manage access override for all source AC range registers within the system. + +When the bypass_wire is asserted, the range register logic shall allow access for all transactions, overriding any existing configuration settings. +This includes ignoring permission restrictions such as READ, WRITE, or EXECUTE and RACL checks, ensuring all transactions are permitted while bypass mode is active. + +The bypass mode may be used during early silicon bring-up or debugging phases, where reducing the security due to disabled range filters is acceptable. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/ac_range_check.core b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/ac_range_check.core new file mode 100644 index 00000000000..8fa49c2081f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/ac_range_check.core @@ -0,0 +1,73 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:ac_range_check:0.1 +description: "AC Range Check RTL" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:mubi + - lowrisc:prim:all + - lowrisc:prim:leading_one_ppc + - lowrisc:darjeeling_no_ibex_constants:top_racl_pkg + - lowrisc:prim:edge_detector + - lowrisc:prim:onehot + files: + - rtl/ac_range_check_reg_pkg.sv + - rtl/ac_range_check_reg_top.sv + - rtl/ac_range_check.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/ac_range_check.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/ac_range_check.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: ac_range_check + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - '-Wall' + - '-Wno-ALWCOMBORDER' diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/BUILD new file mode 100644 index 00000000000..35e9ae328ee --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/BUILD @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_ac_range_check.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = glob([ + "ac_range_check.hjson", + "*_testplan.hjson", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/ac_range_check.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/ac_range_check.hjson new file mode 100644 index 00000000000..3e2f4b26e0c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/ac_range_check.hjson @@ -0,0 +1,423 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +# AC Range Check register template +{ + name: "ac_range_check" + human_name: "Access Control Range Check" + one_line_desc: "Access Control Range Check." + one_paragraph_desc: ''' + ''' + cip_id: "41", + design_spec: "../doc" + dv_doc: "../doc/dv" + version: "1.0.0" + + clocking: [{clock: "clk_i", reset: "rst_ni", primary: true}] + bus_interfaces: [ + { protocol: "tlul", direction: "device", hier_path: "u_ac_range_check_reg", racl_support: true } + ] + param_list: [ + { name: "NumRanges", + desc: "Number of range registers", + type: "int", + default: "32", + }, + { name: "DenyCountWidth", + desc: "Width of the deny counter", + type: "int", + default: "8", + local: "true" + }, + { name: "RangeCheckErrorRsp", + desc: ''' + Error behavior on blocked requests: + 1: A denied request returns a TLUL error (.d_error = 1 on the response) + 0: Writes are dropped and reads return all-zero, without a TLUL error + ''', + type: "bit", + default: "1", + local: "false" + expose: "true" + }, + ], + inter_signal_list: [ + { name: "range_check_overwrite" + type: "uni", + act: "rcv", + package: "prim_mubi_pkg", + struct: "mubi8", + width: "1" + desc: "Overwrites all ranges and let all requests pass through." + }, + { struct: "tl_h2d" + package: "tlul_pkg" + type: "uni" + name: "ctn_tl_h2d" + act: "rcv" + desc: "TL-UL input port (request part), synchronous" + } + { struct: "tl_d2h" + package: "tlul_pkg" + type: "uni" + name: "ctn_tl_d2h" + act: "req" + desc: "TL-UL input port (response part), synchronous" + } + { struct: "tl_h2d" + package: "tlul_pkg" + type: "uni" + name: "ctn_filtered_tl_h2d" + act: "req" + desc: "Filtered TL-UL output port (request part), synchronous" + } + { struct: "tl_d2h" + package: "tlul_pkg" + type: "uni" + name: "ctn_filtered_tl_d2h" + act: "rcv" + desc: "Filtered TL-UL output port (response part), synchronous" + } + { struct: "racl_policy_vec", + type: "uni", + name: "racl_policies", + act: "rcv", + package: "top_racl_pkg", + desc: ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + } + { struct: "racl_error_log", + type: "uni", + name: "racl_error", + act: "req", + width: "1" + package: "top_racl_pkg", + desc: ''' + RACL error log information of this module. + ''' + } + ] + interrupt_list: [ + { name: "deny_cnt_reached" + desc: "Deny counter has exceeded threshold." + type: "status" + } + ] + alert_list: [ + { name: "recov_ctrl_update_err", + desc: "This recoverable alert is triggered upon detecting an update error in the shadowed Control Register." + } + { name: "fatal_fault" + desc: "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected or the internal counter has an error." + } + ] + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "CTRL.REGWEN_MUBI" + desc: "Registers are protected from writes with a multi-bit encoded signal." + } + { name: "CTRL.MUBI" + desc: "Registers have multi-bit encoded fields." + } + { name: "INTERSIG.MUBI" + desc: "Range overwrite singal to bypass the matching logic." + } + { name: "CTR.REDUN" + desc: "The log counter is protected by a second counter that counts in the opposite direction." + } + ] + regwidth: "32" + registers: [ + { name: "ALERT_STATUS" + desc: "Status of hardware alerts." + swaccess: "ro" + hwaccess: "hwo" + fields: [ + { bits: "0" + name: "SHADOWED_UPDATE_ERR" + resval: "0" + swaccess: "rc" + desc: '''Update error of a shadowed register. + This is a recoverable error caused by SW misbehavior. + This field gets cleared by a SW read. + ''' + } + { bits: "1" + name: "SHADOWED_STORAGE_ERR" + resval: "0" + desc: '''Storage error of a shadowed register. + This is a fatal error. + Once set, this field remains set until this HW IP block gets reset. + ''' + } + { bits: "2" + name: "REG_INTG_ERR" + resval: "0" + desc: '''Integrity error in the register interface. + This is a fatal error. + Once set, this field remains set until this HW IP block gets reset. + ''' + } + { bits: "3" + name: "COUNTER_ERR" + resval: "0" + desc: '''Integrity error in a counter. + This is a fatal error. + Once set, this field remains set until this HW IP block gets reset. + ''' + } + ] + } + { name: "LOG_CONFIG" + desc: "" + swaccess: "rw" + hwaccess: "hro" + fields: [ + { bits: "9:2" + name: "deny_cnt_threshold" + resval: 0x0 + desc: "An interrupt is raised (if enabled) when deny_cnt exceeds the configured deny_cnt_threshold." + } + { bits: "1" + name: "log_clear" + resval: 0x0 + hwqe: "true" + swaccess: "r0w1c" + hwaccess: "hrw" + desc: '''Clears all log information for the first denied access including: + - LOG_STATUS + - LOG_ADDRESS. + ''' + } + { bits: "0" + name: "log_enable" + resval: 0x0 + desc: "When set, blocked requests are logged by the deny counter." + } + ] + } + { name: "LOG_STATUS" + desc: ''' + The LOG_STATUS register stores the number of denied accesses and gives more detailed diagnostics to the first denied request. + All fields of LOG_STATUS (other than deny_cnt) are only valid if deny_cnt > 0. + ''' + swaccess: "ro" + hwaccess: "hwo" + fields: [ + { bits: "27:23" + name: "deny_range_index" + resval: 0x0 + desc: "Index of the range that caused the denied access." + } + { bits: "22:18" + name: "denied_ctn_uid" + resval: 0x0 + desc: "Source CTN UID that was denied access." + } + { bits: "17:14" + name: "denied_source_role" + resval: 0x0 + desc: "Source RACL role that was denied access." + } + { bits: "13" + name: "denied_racl_write" + resval: 0x0 + desc: "Indicates whether a write access was denied by RACL." + } + { bits: "12" + name: "denied_racl_read" + resval: 0x0 + desc: "Indicates whether a read access was denied by RACL." + } + { bits: "11" + name: "denied_no_match" + resval: 0x0 + desc: "Indicates whether the access was denied because no range matched." + } + { bits: "10" + name: "denied_execute_access" + resval: 0x0 + desc: "Indicates whether execution access was denied." + } + { bits: "9" + name: "denied_write_access" + resval: 0x0 + desc: "Indicates whether a write access was denied." + } + { bits: "8" + name: "denied_read_access" + resval: 0x0 + desc: "Indicates whether a read access was denied." + } + { bits: "7:0" + name: "deny_cnt" + resval: 0x0 + desc: ''' + Software mirror of the internal deny counter. + Gets incremented for every blocked request. + ''' + } + ] + } + { name: "LOG_ADDRESS" + desc: ''' + First denied request address (if logging is enabled) gets written into that register. + ''' + swaccess: "ro" + hwaccess: "hwo" + fields: [ + { bits: "31:0" + name: "log_address" + resval: 0x0 + desc: "First denied request address." + } + ] + } + { multireg: { + name: "RANGE_REGWEN" + desc: ''' + This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. + When cleared to Mubi4::False, the corresponding range configuration registers are locked and cannot be changed until the next reset. + ''' + count: "NumRanges" + cname: "range_regwen" + swaccess: "rw0c" + hwaccess: "none" + compact: false + fields: [ + { bits: "3:0" + resval: true + mubi: true + name: "regwen" + desc: "Clearing this register locks the configuration registers of that range until the next reset." + } + ] + } + } + { multireg: { + name: "RANGE_BASE" + desc: ''' + Base address for the range check. + The range base register exists per range and holds the base address for the range check. + The minimum granularity of the range is 4 bytes. + Therefore, the lowest 2 bits of the 32-bit base and limit registers are tied to zero. + ''' + count: "NumRanges" + cname: "range_base" + swaccess: "rw" + hwaccess: "hro" + regwen: "RANGE_REGWEN" + regwen_multi: true + fields: [ + { name: "base" + desc: "Base address" + bits: "31:2" + resval: 0x0 + } + ] + } + } + { multireg: { + name: "RANGE_LIMIT" + desc: ''' + The (exclusive) limit address register used for the address matching. + ''' + count: "NumRanges" + cname: "BASE" + swaccess: "rw" + hwaccess: "hro" + regwen: "RANGE_REGWEN" + regwen_multi: true + fields: [ + { name: "limit" + desc: "Exclusive limit address." + bits: "31:2" + resval: 0x0 + } + ] + } + } + { multireg: { + name: "RANGE_ATTR" + desc: ''' + Attributes of the range. + This register exists per range and determines attributes (including permissions) of the particular range. + A range and its attributes are only considered if its `enable` field in this register is not set to `Mubi4::False`. + ''' + count: "NumRanges" + cname: "BASE" + swaccess: "rw" + hwaccess: "hro" + regwen: "RANGE_REGWEN" + regwen_multi: true + fields: [ + { name: "log_denied_access" + desc: "When set to Mubi4::True, a denied access based on in this range is being logged." + bits: "19:16" + mubi: true + resval: true + } + { name: "execute_access" + desc: "When set to Mubi4::True, code execution from this range is allowed." + bits: "15:12" + mubi: true + resval: false + } + { name: "write_access" + desc: "When set to Mubi4::True, write access to that range is allowed." + bits: "11:8" + mubi: true + resval: false + } + { name: "read_access" + desc: "When set to Mubi4::True, read access from that range is allowed." + bits: "7:4" + mubi: true + resval: false + } + { name: "enable" + desc: "When set to Mubi4::False, the range is _not_ considered in the range check; for any other value, the range _is_ considered in the range check." + bits: "3:0" + mubi: true + resval: false + } + ] + } + } + { multireg: { + name: "RANGE_RACL_POLICY_SHADOWED" + desc: ''' + The RACL policy register allows the system to further restrict the access to specific source roles. + The default value for both the read and write permission bitmaps is to deny access for all roles. + This register is protected against fault attacks by using a shadow register implementation. + ''' + count: "NumRanges" + cname: "RACL" + swaccess: "rw" + hwaccess: "hro" + regwen: "RANGE_REGWEN" + regwen_multi: true + shadowed: "true", + update_err_alert: "recov_ctrl_update_err", + storage_err_alert: "fatal_fault", + fields: [ + { name: "write_perm" + desc: "Write permission policy bitmap." + bits: "31:16" + resval: 0x0 + } + { name: "read_perm" + desc: "Read permission policy bitmap." + bits: "15:0" + resval: 0x0 + } + ] + } + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson new file mode 100644 index 00000000000..4720a2aec2b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson @@ -0,0 +1,95 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "ac_range_check" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"] + testpoints: [ + { + name: ac_range_check_smoke + desc: ''' + Smoke test in which we configure a randomized number of ranges to allow a transfer + and perform transfers. + + Stimulus: + - Assert range_check_overwrite_i to MuBi8::False + - Configure a random number of ranges: + * Randomize the RANGE_BASE and RANGE_LIMIT register (RANGE_LIMIT > RANGE_BASE) + * Randomize the RANGE_ATTR register and set the RANGE_ATTR.enable bit to 1 + * Set RANGE_RACL_POLICY_SHADOWED.read_perm and + RANGE_RACL_POLICY_SHADOWED.write_perm to 0xFFFF (disables RACL checks) + - Perform random TLUL requests on the unfiltered interface (ctn_tl_h2d_i) and + provide random TLUL responses on the filtered interface (ctn_filtered_tl_d2h_i). + + Checking: + - If a request falls outside of any enabled range: + * The request should be denied and an error should be returned in the response on + the unfiltered TLUL D channel (ctn_tl_d2h_o). + * Read and Execute requests should return all zero as data on the unfiltered TLUL + D channel (ctn_tl_d2h_o). + - If the request falls into the address space of at least one enabled range, the + request is allowed if and only if the permissions of that range allow it (e.g., if + the access is a data read, the range needs to allow reads for the access to be + allowed) and it does not fall into the address space of any other enabled range + with lower index whose permissions deny the request. + Allowed requests should propagate without modifications on the A channel. And the + corresponding responses should propagate unmodified on the D channel. One + exception to this is the d_data field for AccessAck responses (i.e., responses to + writes): the TL-UL spec defines that this field in this case can be any value, and + the current implementation sets it to zero (for the reason described in PR #1236). + ''' + stage: V1 + tests: ["ac_range_check_smoke"] + } + { + name: ac_range_check_lock_range + desc: ''' + Test the range lock functionality + + Stimulus: + - Configure a range's RANGE_BASE, RANGE_LIMIT, RANGE_ATTR, RANGE_RACL_POLICY_SHADOWED + register + - Clear RANGE_REGWEN to MuBi4::False in a randomized way + - Try to reconfigure the range with different values + + Checking: + - If RANGE_REGWEN was cleared to MuBi4::False, the reconfigured register values + The original configuration should remain in the registers. If RANGE_REGWEN was not + cleared, the reconfigured values should have replaced the original ones. + ''' + stage: V2 + tests: ["ac_range_check_lock_range"] + } + { + name: ac_range_bypass_enable + desc: ''' + Test the bypass functionality for enabled ranges. + + Stimulus: + - Assert range_check_overwrite_i to Mubi8::True + - Configure the AC range check to block certain address ranges + * Randomize type of denial (R/W/X, RACL policies) + - Perform random TLUL requests that fall within blocked ranges and outside with: + * Random request type (R/W/X) and random RACL role + + Checking: + - Check if all transfers are allowed + - LOG_STATUS.deny_cnt must stay 0 + ''' + stage: V2 + tests: ["ac_range_check_bypass"] + } + ] + covergroups: [ + { + name: ac_range_check_log_status_cg + desc: ''' + Cover all status fields of the LOG_STATUS. + (deny_cnt and deny_range_index are not part of this). + ''' + } + ] + } diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/top_darjeeling_no_ibex_ac_range_check.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/top_darjeeling_no_ibex_ac_range_check.ipconfig.hjson new file mode 100644 index 00000000000..d875f0fbc40 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data/top_darjeeling_no_ibex_ac_range_check.ipconfig.hjson @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_ac_range_check + param_values: + { + num_ranges: 32 + module_instance_name: ac_range_check + nr_role_bits: 4 + nr_ctn_uid_bits: 5 + topname: darjeeling_no_ibex + uniquified_modules: {} + } + dtgen: + { + num_ranges: + { + type: uint8 + name: num_ranges + doc: Number of range registers + } + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/defs.bzl new file mode 100644 index 00000000000..ed70f5dcf9b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/defs.bzl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +AC_RANGE_CHECK = opentitan_ip( + name = "ac_range_check", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/data:ac_range_check.hjson", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/ac_range_check.svg b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/ac_range_check.svg new file mode 100644 index 00000000000..ccf62f5aa44 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/ac_range_check.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/checklist.md b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/checklist.md new file mode 100644 index 00000000000..f663bc000f9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/checklist.md @@ -0,0 +1,275 @@ +--- +title: "AC_RANGE_CHECK Checklist" +--- + + +This checklist is for [Hardware Stage](/doc/project_governance/development_stages.md) transitions for the [AC_RANGE_CHECK peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](/doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Not Started | [AC_RANGE_CHECK Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Not Started | +RTL | [CLKRST_CONNECTED][] | Not Started | +RTL | [IP_TOP][] | Not Started | +RTL | [IP_INSTANTIABLE][] | Not Started | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started | +RTL | [FUNC_IMPLEMENTED][] | Not Started | +RTL | [ASSERT_KNOWN_ADDED][] | Not Started | +Code Quality | [LINT_SETUP][] | Not Started | +Security | [SEC_CM_SCOPED][] | Not Started | + +[SPEC_COMPLETE]: /doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: /doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: /doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: /doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: /doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: /doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: /doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: /doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: /doc/project_governance/checklist/README.md#lint_setup +[SEC_CM_SCOPED]: /doc/project_governance/checklist/README.md#sec_cm_scoped + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Not Started | +Documentation | [BLOCK_DIAGRAM][] | Not Started | +Documentation | [DOC_INTERFACE][] | Not Started | +Documentation | [DOC_INTEGRATION_GUIDE][] | Not Started | +Documentation | [MISSING_FUNC][] | Not Started | +Documentation | [FEATURE_FROZEN][] | Not Started | +RTL | [FEATURE_COMPLETE][] | Not Started | +RTL | [PORT_FROZEN][] | Not Started | +RTL | [ARCHITECTURE_FROZEN][] | Not Started | +RTL | [REVIEW_TODO][] | Not Started | +RTL | [STYLE_X][] | Not Started | +RTL | [CDC_SYNCMACRO][] | Not Started | +Code Quality | [LINT_PASS][] | Not Started | +Code Quality | [CDC_SETUP][] | Not Started | +Code Quality | [RDC_SETUP][] | Not Started | +Code Quality | [AREA_CHECK][] | Not Started | +Code Quality | [TIMING_CHECK][] | Not Started | +Security | [SEC_CM_DOCUMENTED][] | Not Started | + +[NEW_FEATURES]: /doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: /doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: /doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: /doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: /doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: /doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: /doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: /doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: /doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: /doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: /doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: /doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: /doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: /doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: /doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: /doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: /doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: /doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Not Started | +Security | [SEC_CM_IMPLEMENTED][] | Not Started | +Security | [SEC_CM_RND_CNST][] | Not Started | +Security | [SEC_CM_NON_RESET_FLOPS][] | Not Started | +Security | [SEC_CM_SHADOW_REGS][] | Not Started | +Security | [SEC_CM_RTL_REVIEWED][] | Not Started | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Not Started | + +[SEC_CM_ASSETS_LISTED]: /doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: /doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: /doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: /doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: /doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Not Started | +RTL | [TODO_COMPLETE][] | Not Started | +Code Quality | [LINT_COMPLETE][] | Not Started | +Code Quality | [CDC_COMPLETE][] | Not Started | +Code Quality | [RDC_COMPLETE][] | Not Started | +Review | [REVIEW_RTL][] | Not Started | +Review | [REVIEW_DELETED_FF][] | Not Started | +Review | [REVIEW_SW_CHANGE][] | Not Started | +Review | [REVIEW_SW_ERRATA][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[NEW_FEATURES_D3]: /doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: /doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: /doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: /doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: /doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: /doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: /doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: /doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: /doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [AC_RANGE_CHECK DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Not Started | [AC_RANGE_CHECK Testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Not Started | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started | +Testbench | [SIM_TB_ENV_CREATED][] | Not Started | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started | +Testbench | [TB_GEN_AUTOMATED][] | Not Started | +Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started | +Regression | [FPV_REGRESSION_SETUP][] | Not Started | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started | +Code Quality | [TB_LINT_SETUP][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started | +Review | [DESIGN_SPEC_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Not Started | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?) +Review | [V2_CHECKLIST_SCOPED][] | Not Started | + +[DV_DOC_DRAFT_COMPLETED]: /doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: /doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: /doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: /doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: /doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: /doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: /doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: /doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: /doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: /doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: /doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: /doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: /doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: /doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: /doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: /doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: /doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started | +Documentation | [DV_DOC_COMPLETED][] | Not Started | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Not Started | +Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started | +Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started | +Tests | [SIM_ALL_TESTS_PASSING][] | Not Started | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started | +Tests | [SIM_FW_SIMULATED][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started | +Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started | +Coverage | [FPV_COI_COVERAGE_V2][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started | +Review | [V3_CHECKLIST_SCOPED][] | Not Started | + +[DESIGN_DELTAS_CAPTURED_V2]: /doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: /doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: /doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: /doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: /doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: /doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: /doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: /doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: /doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: /doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: /doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: /doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: /doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: /doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: /doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: /doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:/doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: /doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: /doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Not Started | +Tests | [FPV_SEC_CM_VERIFIED][] | Not Started | +Tests | [SIM_SEC_CM_VERIFIED][] | Not Started | +Coverage | [SIM_COVERAGE_REVIEWED][] | Not Started | +Review | [SEC_CM_DV_REVIEWED][] | Not Started | + +[SEC_CM_TESTPLAN_COMPLETED]: /doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: /doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: /doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: /doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: /doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: /doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: /doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: /doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: /doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:/doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: /doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: /doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: /doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: /doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: /doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: /doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/interfaces.md b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/interfaces.md new file mode 100644 index 00000000000..e7a84b83437 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/interfaces.md @@ -0,0 +1,48 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`ac_range_check`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: *none* +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:----------------------|:------------------------------|:--------|:------|--------:|:-------------------------------------------------------------------------------------------------------------------------------------| +| range_check_overwrite | prim_mubi_pkg::mubi8 | uni | rcv | 1 | Overwrites all ranges and let all requests pass through. | +| ctn_tl_h2d | tlul_pkg::tl_h2d | uni | rcv | 1 | TL-UL input port (request part), synchronous | +| ctn_tl_d2h | tlul_pkg::tl_d2h | uni | req | 1 | TL-UL input port (response part), synchronous | +| ctn_filtered_tl_h2d | tlul_pkg::tl_h2d | uni | req | 1 | Filtered TL-UL output port (request part), synchronous | +| ctn_filtered_tl_d2h | tlul_pkg::tl_d2h | uni | rcv | 1 | Filtered TL-UL output port (response part), synchronous | +| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register. | +| racl_error | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Interrupts + +| Interrupt Name | Type | Description | +|:-----------------|:-------|:-------------------------------------| +| deny_cnt_reached | Status | Deny counter has exceeded threshold. | + +## Security Alerts + +| Alert Name | Description | +|:----------------------|:-----------------------------------------------------------------------------------------------------------------------| +| recov_ctrl_update_err | This recoverable alert is triggered upon detecting an update error in the shadowed Control Register. | +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected or the internal counter has an error. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:--------------------------------|:----------------------------------------------------------------------------------------| +| AC_RANGE_CHECK.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| AC_RANGE_CHECK.CTRL.REGWEN_MUBI | Registers are protected from writes with a multi-bit encoded signal. | +| AC_RANGE_CHECK.CTRL.MUBI | Registers have multi-bit encoded fields. | +| AC_RANGE_CHECK.INTERSIG.MUBI | Range overwrite singal to bypass the matching logic. | +| AC_RANGE_CHECK.CTR.REDUN | The log counter is protected by a second counter that counts in the opposite direction. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/registers.md b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/registers.md new file mode 100644 index 00000000000..c7d4c7c7c9c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/registers.md @@ -0,0 +1,615 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:------------------------------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------------------------------------------------------------------------------------------| +| ac_range_check.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | +| ac_range_check.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | +| ac_range_check.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | +| ac_range_check.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | +| ac_range_check.[`ALERT_STATUS`](#alert_status) | 0x10 | 4 | Status of hardware alerts. | +| ac_range_check.[`LOG_CONFIG`](#log_config) | 0x14 | 4 | | +| ac_range_check.[`LOG_STATUS`](#log_status) | 0x18 | 4 | The LOG_STATUS register stores the number of denied accesses and gives more detailed diagnostics to the first denied request. | +| ac_range_check.[`LOG_ADDRESS`](#log_address) | 0x1c | 4 | First denied request address (if logging is enabled) gets written into that register. | +| ac_range_check.[`RANGE_REGWEN_0`](#range_regwen) | 0x20 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_1`](#range_regwen) | 0x24 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_2`](#range_regwen) | 0x28 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_3`](#range_regwen) | 0x2c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_4`](#range_regwen) | 0x30 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_5`](#range_regwen) | 0x34 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_6`](#range_regwen) | 0x38 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_7`](#range_regwen) | 0x3c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_8`](#range_regwen) | 0x40 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_9`](#range_regwen) | 0x44 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_10`](#range_regwen) | 0x48 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_11`](#range_regwen) | 0x4c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_12`](#range_regwen) | 0x50 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_13`](#range_regwen) | 0x54 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_14`](#range_regwen) | 0x58 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_15`](#range_regwen) | 0x5c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_16`](#range_regwen) | 0x60 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_17`](#range_regwen) | 0x64 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_18`](#range_regwen) | 0x68 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_19`](#range_regwen) | 0x6c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_20`](#range_regwen) | 0x70 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_21`](#range_regwen) | 0x74 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_22`](#range_regwen) | 0x78 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_23`](#range_regwen) | 0x7c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_24`](#range_regwen) | 0x80 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_25`](#range_regwen) | 0x84 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_26`](#range_regwen) | 0x88 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_27`](#range_regwen) | 0x8c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_28`](#range_regwen) | 0x90 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_29`](#range_regwen) | 0x94 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_30`](#range_regwen) | 0x98 | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_REGWEN_31`](#range_regwen) | 0x9c | 4 | This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. | +| ac_range_check.[`RANGE_BASE_0`](#range_base) | 0xa0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_1`](#range_base) | 0xa4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_2`](#range_base) | 0xa8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_3`](#range_base) | 0xac | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_4`](#range_base) | 0xb0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_5`](#range_base) | 0xb4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_6`](#range_base) | 0xb8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_7`](#range_base) | 0xbc | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_8`](#range_base) | 0xc0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_9`](#range_base) | 0xc4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_10`](#range_base) | 0xc8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_11`](#range_base) | 0xcc | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_12`](#range_base) | 0xd0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_13`](#range_base) | 0xd4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_14`](#range_base) | 0xd8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_15`](#range_base) | 0xdc | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_16`](#range_base) | 0xe0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_17`](#range_base) | 0xe4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_18`](#range_base) | 0xe8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_19`](#range_base) | 0xec | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_20`](#range_base) | 0xf0 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_21`](#range_base) | 0xf4 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_22`](#range_base) | 0xf8 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_23`](#range_base) | 0xfc | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_24`](#range_base) | 0x100 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_25`](#range_base) | 0x104 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_26`](#range_base) | 0x108 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_27`](#range_base) | 0x10c | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_28`](#range_base) | 0x110 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_29`](#range_base) | 0x114 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_30`](#range_base) | 0x118 | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_BASE_31`](#range_base) | 0x11c | 4 | Base address for the range check. | +| ac_range_check.[`RANGE_LIMIT_0`](#range_limit) | 0x120 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_1`](#range_limit) | 0x124 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_2`](#range_limit) | 0x128 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_3`](#range_limit) | 0x12c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_4`](#range_limit) | 0x130 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_5`](#range_limit) | 0x134 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_6`](#range_limit) | 0x138 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_7`](#range_limit) | 0x13c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_8`](#range_limit) | 0x140 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_9`](#range_limit) | 0x144 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_10`](#range_limit) | 0x148 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_11`](#range_limit) | 0x14c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_12`](#range_limit) | 0x150 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_13`](#range_limit) | 0x154 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_14`](#range_limit) | 0x158 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_15`](#range_limit) | 0x15c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_16`](#range_limit) | 0x160 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_17`](#range_limit) | 0x164 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_18`](#range_limit) | 0x168 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_19`](#range_limit) | 0x16c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_20`](#range_limit) | 0x170 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_21`](#range_limit) | 0x174 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_22`](#range_limit) | 0x178 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_23`](#range_limit) | 0x17c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_24`](#range_limit) | 0x180 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_25`](#range_limit) | 0x184 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_26`](#range_limit) | 0x188 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_27`](#range_limit) | 0x18c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_28`](#range_limit) | 0x190 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_29`](#range_limit) | 0x194 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_30`](#range_limit) | 0x198 | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_LIMIT_31`](#range_limit) | 0x19c | 4 | The (exclusive) limit address register used for the address matching. | +| ac_range_check.[`RANGE_ATTR_0`](#range_attr) | 0x1a0 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_1`](#range_attr) | 0x1a4 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_2`](#range_attr) | 0x1a8 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_3`](#range_attr) | 0x1ac | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_4`](#range_attr) | 0x1b0 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_5`](#range_attr) | 0x1b4 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_6`](#range_attr) | 0x1b8 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_7`](#range_attr) | 0x1bc | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_8`](#range_attr) | 0x1c0 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_9`](#range_attr) | 0x1c4 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_10`](#range_attr) | 0x1c8 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_11`](#range_attr) | 0x1cc | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_12`](#range_attr) | 0x1d0 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_13`](#range_attr) | 0x1d4 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_14`](#range_attr) | 0x1d8 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_15`](#range_attr) | 0x1dc | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_16`](#range_attr) | 0x1e0 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_17`](#range_attr) | 0x1e4 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_18`](#range_attr) | 0x1e8 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_19`](#range_attr) | 0x1ec | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_20`](#range_attr) | 0x1f0 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_21`](#range_attr) | 0x1f4 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_22`](#range_attr) | 0x1f8 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_23`](#range_attr) | 0x1fc | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_24`](#range_attr) | 0x200 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_25`](#range_attr) | 0x204 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_26`](#range_attr) | 0x208 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_27`](#range_attr) | 0x20c | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_28`](#range_attr) | 0x210 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_29`](#range_attr) | 0x214 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_30`](#range_attr) | 0x218 | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_ATTR_31`](#range_attr) | 0x21c | 4 | Attributes of the range. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_0`](#range_racl_policy_shadowed) | 0x220 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_1`](#range_racl_policy_shadowed) | 0x224 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_2`](#range_racl_policy_shadowed) | 0x228 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_3`](#range_racl_policy_shadowed) | 0x22c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_4`](#range_racl_policy_shadowed) | 0x230 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_5`](#range_racl_policy_shadowed) | 0x234 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_6`](#range_racl_policy_shadowed) | 0x238 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_7`](#range_racl_policy_shadowed) | 0x23c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_8`](#range_racl_policy_shadowed) | 0x240 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_9`](#range_racl_policy_shadowed) | 0x244 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_10`](#range_racl_policy_shadowed) | 0x248 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_11`](#range_racl_policy_shadowed) | 0x24c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_12`](#range_racl_policy_shadowed) | 0x250 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_13`](#range_racl_policy_shadowed) | 0x254 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_14`](#range_racl_policy_shadowed) | 0x258 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_15`](#range_racl_policy_shadowed) | 0x25c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_16`](#range_racl_policy_shadowed) | 0x260 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_17`](#range_racl_policy_shadowed) | 0x264 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_18`](#range_racl_policy_shadowed) | 0x268 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_19`](#range_racl_policy_shadowed) | 0x26c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_20`](#range_racl_policy_shadowed) | 0x270 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_21`](#range_racl_policy_shadowed) | 0x274 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_22`](#range_racl_policy_shadowed) | 0x278 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_23`](#range_racl_policy_shadowed) | 0x27c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_24`](#range_racl_policy_shadowed) | 0x280 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_25`](#range_racl_policy_shadowed) | 0x284 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_26`](#range_racl_policy_shadowed) | 0x288 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_27`](#range_racl_policy_shadowed) | 0x28c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_28`](#range_racl_policy_shadowed) | 0x290 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_29`](#range_racl_policy_shadowed) | 0x294 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_30`](#range_racl_policy_shadowed) | 0x298 | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | +| ac_range_check.[`RANGE_RACL_POLICY_SHADOWED_31`](#range_racl_policy_shadowed) | 0x29c | 4 | The RACL policy register allows the system to further restrict the access to specific source roles. | + +## INTR_STATE +Interrupt State Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "deny_cnt_reached", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------|:-------------------------------------| +| 31:1 | | | | Reserved | +| 0 | ro | 0x0 | deny_cnt_reached | Deny counter has exceeded threshold. | + +## INTR_ENABLE +Interrupt Enable Register +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "deny_cnt_reached", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------|:---------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | deny_cnt_reached | Enable interrupt when [`INTR_STATE.deny_cnt_reached`](#intr_state) is set. | + +## INTR_TEST +Interrupt Test Register +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "deny_cnt_reached", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 180}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------|:--------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | deny_cnt_reached | Write 1 to force [`INTR_STATE.deny_cnt_reached`](#intr_state) to 1. | + +## ALERT_TEST +Alert Test Register +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "recov_ctrl_update_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------|:-------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | +| 0 | wo | 0x0 | recov_ctrl_update_err | Write 1 to trigger one alert event of this kind. | + +## ALERT_STATUS +Status of hardware alerts. +- Offset: `0x10` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "SHADOWED_UPDATE_ERR", "bits": 1, "attr": ["rc"], "rotate": -90}, {"name": "SHADOWED_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "COUNTER_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------------|:--------------------------------------------------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3 | ro | 0x0 | COUNTER_ERR | Integrity error in a counter. This is a fatal error. Once set, this field remains set until this HW IP block gets reset. | +| 2 | ro | 0x0 | REG_INTG_ERR | Integrity error in the register interface. This is a fatal error. Once set, this field remains set until this HW IP block gets reset. | +| 1 | ro | 0x0 | SHADOWED_STORAGE_ERR | Storage error of a shadowed register. This is a fatal error. Once set, this field remains set until this HW IP block gets reset. | +| 0 | rc | 0x0 | SHADOWED_UPDATE_ERR | Update error of a shadowed register. This is a recoverable error caused by SW misbehavior. This field gets cleared by a SW read. | + +## LOG_CONFIG + +- Offset: `0x14` +- Reset default: `0x0` +- Reset mask: `0x3ff` + +### Fields + +```wavejson +{"reg": [{"name": "log_enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "log_clear", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"name": "deny_cnt_threshold", "bits": 8, "attr": ["rw"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------|:----------------------------------------------------------------------------------------------| +| 31:10 | | | | Reserved | +| 9:2 | rw | 0x0 | deny_cnt_threshold | An interrupt is raised (if enabled) when deny_cnt exceeds the configured deny_cnt_threshold. | +| 1 | r0w1c | 0x0 | log_clear | Clears all log information for the first denied access including: - LOG_STATUS - LOG_ADDRESS. | +| 0 | rw | 0x0 | log_enable | When set, blocked requests are logged by the deny counter. | + +## LOG_STATUS +The LOG_STATUS register stores the number of denied accesses and gives more detailed diagnostics to the first denied request. +All fields of LOG_STATUS (other than deny_cnt) are only valid if deny_cnt > 0. +- Offset: `0x18` +- Reset default: `0x0` +- Reset mask: `0xfffffff` + +### Fields + +```wavejson +{"reg": [{"name": "deny_cnt", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "denied_read_access", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "denied_write_access", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "denied_execute_access", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "denied_no_match", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "denied_racl_read", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "denied_racl_write", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "denied_source_role", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "denied_ctn_uid", "bits": 5, "attr": ["ro"], "rotate": -90}, {"name": "deny_range_index", "bits": 5, "attr": ["ro"], "rotate": -90}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------|:------------------------------------------------------------------------------------------| +| 31:28 | | | | Reserved | +| 27:23 | ro | 0x0 | deny_range_index | Index of the range that caused the denied access. | +| 22:18 | ro | 0x0 | denied_ctn_uid | Source CTN UID that was denied access. | +| 17:14 | ro | 0x0 | denied_source_role | Source RACL role that was denied access. | +| 13 | ro | 0x0 | denied_racl_write | Indicates whether a write access was denied by RACL. | +| 12 | ro | 0x0 | denied_racl_read | Indicates whether a read access was denied by RACL. | +| 11 | ro | 0x0 | denied_no_match | Indicates whether the access was denied because no range matched. | +| 10 | ro | 0x0 | denied_execute_access | Indicates whether execution access was denied. | +| 9 | ro | 0x0 | denied_write_access | Indicates whether a write access was denied. | +| 8 | ro | 0x0 | denied_read_access | Indicates whether a read access was denied. | +| 7:0 | ro | 0x0 | deny_cnt | Software mirror of the internal deny counter. Gets incremented for every blocked request. | + +## LOG_ADDRESS +First denied request address (if logging is enabled) gets written into that register. +- Offset: `0x1c` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "log_address", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:------------------------------| +| 31:0 | ro | 0x0 | log_address | First denied request address. | + +## RANGE_REGWEN +This register exists per range and provides a regwen signal for the RANGE_BASE_x, RANGE_LIMIT_x, RANGE_ATTR_x, and RANGE_RACL_POLICY_SHADOWED_x register. +When cleared to Mubi4::False, the corresponding range configuration registers are locked and cannot be changed until the next reset. +- Reset default: `0x6` +- Reset mask: `0xf` + +### Instances + +| Name | Offset | +|:----------------|:---------| +| RANGE_REGWEN_0 | 0x20 | +| RANGE_REGWEN_1 | 0x24 | +| RANGE_REGWEN_2 | 0x28 | +| RANGE_REGWEN_3 | 0x2c | +| RANGE_REGWEN_4 | 0x30 | +| RANGE_REGWEN_5 | 0x34 | +| RANGE_REGWEN_6 | 0x38 | +| RANGE_REGWEN_7 | 0x3c | +| RANGE_REGWEN_8 | 0x40 | +| RANGE_REGWEN_9 | 0x44 | +| RANGE_REGWEN_10 | 0x48 | +| RANGE_REGWEN_11 | 0x4c | +| RANGE_REGWEN_12 | 0x50 | +| RANGE_REGWEN_13 | 0x54 | +| RANGE_REGWEN_14 | 0x58 | +| RANGE_REGWEN_15 | 0x5c | +| RANGE_REGWEN_16 | 0x60 | +| RANGE_REGWEN_17 | 0x64 | +| RANGE_REGWEN_18 | 0x68 | +| RANGE_REGWEN_19 | 0x6c | +| RANGE_REGWEN_20 | 0x70 | +| RANGE_REGWEN_21 | 0x74 | +| RANGE_REGWEN_22 | 0x78 | +| RANGE_REGWEN_23 | 0x7c | +| RANGE_REGWEN_24 | 0x80 | +| RANGE_REGWEN_25 | 0x84 | +| RANGE_REGWEN_26 | 0x88 | +| RANGE_REGWEN_27 | 0x8c | +| RANGE_REGWEN_28 | 0x90 | +| RANGE_REGWEN_29 | 0x94 | +| RANGE_REGWEN_30 | 0x98 | +| RANGE_REGWEN_31 | 0x9c | + + +### Fields + +```wavejson +{"reg": [{"name": "regwen", "bits": 4, "attr": ["rw0c"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw0c | 0x6 | regwen | Clearing this register locks the configuration registers of that range until the next reset. | + +## RANGE_BASE +Base address for the range check. +The range base register exists per range and holds the base address for the range check. +The minimum granularity of the range is 4 bytes. +Therefore, the lowest 2 bits of the 32-bit base and limit registers are tied to zero. +- Reset default: `0x0` +- Reset mask: `0xfffffffc` +- Register enable: [`RANGE_REGWEN`](#range_regwen) + +### Instances + +| Name | Offset | +|:--------------|:---------| +| RANGE_BASE_0 | 0xa0 | +| RANGE_BASE_1 | 0xa4 | +| RANGE_BASE_2 | 0xa8 | +| RANGE_BASE_3 | 0xac | +| RANGE_BASE_4 | 0xb0 | +| RANGE_BASE_5 | 0xb4 | +| RANGE_BASE_6 | 0xb8 | +| RANGE_BASE_7 | 0xbc | +| RANGE_BASE_8 | 0xc0 | +| RANGE_BASE_9 | 0xc4 | +| RANGE_BASE_10 | 0xc8 | +| RANGE_BASE_11 | 0xcc | +| RANGE_BASE_12 | 0xd0 | +| RANGE_BASE_13 | 0xd4 | +| RANGE_BASE_14 | 0xd8 | +| RANGE_BASE_15 | 0xdc | +| RANGE_BASE_16 | 0xe0 | +| RANGE_BASE_17 | 0xe4 | +| RANGE_BASE_18 | 0xe8 | +| RANGE_BASE_19 | 0xec | +| RANGE_BASE_20 | 0xf0 | +| RANGE_BASE_21 | 0xf4 | +| RANGE_BASE_22 | 0xf8 | +| RANGE_BASE_23 | 0xfc | +| RANGE_BASE_24 | 0x100 | +| RANGE_BASE_25 | 0x104 | +| RANGE_BASE_26 | 0x108 | +| RANGE_BASE_27 | 0x10c | +| RANGE_BASE_28 | 0x110 | +| RANGE_BASE_29 | 0x114 | +| RANGE_BASE_30 | 0x118 | +| RANGE_BASE_31 | 0x11c | + + +### Fields + +```wavejson +{"reg": [{"bits": 2}, {"name": "base", "bits": 30, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:2 | rw | 0x0 | base | Base address | +| 1:0 | | | | Reserved | + +## RANGE_LIMIT +The (exclusive) limit address register used for the address matching. +- Reset default: `0x0` +- Reset mask: `0xfffffffc` +- Register enable: [`RANGE_REGWEN`](#range_regwen) + +### Instances + +| Name | Offset | +|:---------------|:---------| +| RANGE_LIMIT_0 | 0x120 | +| RANGE_LIMIT_1 | 0x124 | +| RANGE_LIMIT_2 | 0x128 | +| RANGE_LIMIT_3 | 0x12c | +| RANGE_LIMIT_4 | 0x130 | +| RANGE_LIMIT_5 | 0x134 | +| RANGE_LIMIT_6 | 0x138 | +| RANGE_LIMIT_7 | 0x13c | +| RANGE_LIMIT_8 | 0x140 | +| RANGE_LIMIT_9 | 0x144 | +| RANGE_LIMIT_10 | 0x148 | +| RANGE_LIMIT_11 | 0x14c | +| RANGE_LIMIT_12 | 0x150 | +| RANGE_LIMIT_13 | 0x154 | +| RANGE_LIMIT_14 | 0x158 | +| RANGE_LIMIT_15 | 0x15c | +| RANGE_LIMIT_16 | 0x160 | +| RANGE_LIMIT_17 | 0x164 | +| RANGE_LIMIT_18 | 0x168 | +| RANGE_LIMIT_19 | 0x16c | +| RANGE_LIMIT_20 | 0x170 | +| RANGE_LIMIT_21 | 0x174 | +| RANGE_LIMIT_22 | 0x178 | +| RANGE_LIMIT_23 | 0x17c | +| RANGE_LIMIT_24 | 0x180 | +| RANGE_LIMIT_25 | 0x184 | +| RANGE_LIMIT_26 | 0x188 | +| RANGE_LIMIT_27 | 0x18c | +| RANGE_LIMIT_28 | 0x190 | +| RANGE_LIMIT_29 | 0x194 | +| RANGE_LIMIT_30 | 0x198 | +| RANGE_LIMIT_31 | 0x19c | + + +### Fields + +```wavejson +{"reg": [{"bits": 2}, {"name": "limit", "bits": 30, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------| +| 31:2 | rw | 0x0 | limit | Exclusive limit address. | +| 1:0 | | | | Reserved | + +## RANGE_ATTR +Attributes of the range. +This register exists per range and determines attributes (including permissions) of the particular range. +A range and its attributes are only considered if its `enable` field in this register is not set to `Mubi4::False`. +- Reset default: `0x69999` +- Reset mask: `0xfffff` +- Register enable: [`RANGE_REGWEN`](#range_regwen) + +### Instances + +| Name | Offset | +|:--------------|:---------| +| RANGE_ATTR_0 | 0x1a0 | +| RANGE_ATTR_1 | 0x1a4 | +| RANGE_ATTR_2 | 0x1a8 | +| RANGE_ATTR_3 | 0x1ac | +| RANGE_ATTR_4 | 0x1b0 | +| RANGE_ATTR_5 | 0x1b4 | +| RANGE_ATTR_6 | 0x1b8 | +| RANGE_ATTR_7 | 0x1bc | +| RANGE_ATTR_8 | 0x1c0 | +| RANGE_ATTR_9 | 0x1c4 | +| RANGE_ATTR_10 | 0x1c8 | +| RANGE_ATTR_11 | 0x1cc | +| RANGE_ATTR_12 | 0x1d0 | +| RANGE_ATTR_13 | 0x1d4 | +| RANGE_ATTR_14 | 0x1d8 | +| RANGE_ATTR_15 | 0x1dc | +| RANGE_ATTR_16 | 0x1e0 | +| RANGE_ATTR_17 | 0x1e4 | +| RANGE_ATTR_18 | 0x1e8 | +| RANGE_ATTR_19 | 0x1ec | +| RANGE_ATTR_20 | 0x1f0 | +| RANGE_ATTR_21 | 0x1f4 | +| RANGE_ATTR_22 | 0x1f8 | +| RANGE_ATTR_23 | 0x1fc | +| RANGE_ATTR_24 | 0x200 | +| RANGE_ATTR_25 | 0x204 | +| RANGE_ATTR_26 | 0x208 | +| RANGE_ATTR_27 | 0x20c | +| RANGE_ATTR_28 | 0x210 | +| RANGE_ATTR_29 | 0x214 | +| RANGE_ATTR_30 | 0x218 | +| RANGE_ATTR_31 | 0x21c | + + +### Fields + +```wavejson +{"reg": [{"name": "enable", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "read_access", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "write_access", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "execute_access", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "log_denied_access", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------|:-----------------------------------------------------------------------------------------------------------------------------------------------| +| 31:20 | | | | Reserved | +| 19:16 | rw | 0x6 | log_denied_access | When set to Mubi4::True, a denied access based on in this range is being logged. | +| 15:12 | rw | 0x9 | execute_access | When set to Mubi4::True, code execution from this range is allowed. | +| 11:8 | rw | 0x9 | write_access | When set to Mubi4::True, write access to that range is allowed. | +| 7:4 | rw | 0x9 | read_access | When set to Mubi4::True, read access from that range is allowed. | +| 3:0 | rw | 0x9 | enable | When set to Mubi4::False, the range is _not_ considered in the range check; for any other value, the range _is_ considered in the range check. | + +## RANGE_RACL_POLICY_SHADOWED +The RACL policy register allows the system to further restrict the access to specific source roles. +The default value for both the read and write permission bitmaps is to deny access for all roles. +This register is protected against fault attacks by using a shadow register implementation. +- Reset default: `0x0` +- Reset mask: `0xffffffff` +- Register enable: [`RANGE_REGWEN`](#range_regwen) + +### Instances + +| Name | Offset | +|:------------------------------|:---------| +| RANGE_RACL_POLICY_SHADOWED_0 | 0x220 | +| RANGE_RACL_POLICY_SHADOWED_1 | 0x224 | +| RANGE_RACL_POLICY_SHADOWED_2 | 0x228 | +| RANGE_RACL_POLICY_SHADOWED_3 | 0x22c | +| RANGE_RACL_POLICY_SHADOWED_4 | 0x230 | +| RANGE_RACL_POLICY_SHADOWED_5 | 0x234 | +| RANGE_RACL_POLICY_SHADOWED_6 | 0x238 | +| RANGE_RACL_POLICY_SHADOWED_7 | 0x23c | +| RANGE_RACL_POLICY_SHADOWED_8 | 0x240 | +| RANGE_RACL_POLICY_SHADOWED_9 | 0x244 | +| RANGE_RACL_POLICY_SHADOWED_10 | 0x248 | +| RANGE_RACL_POLICY_SHADOWED_11 | 0x24c | +| RANGE_RACL_POLICY_SHADOWED_12 | 0x250 | +| RANGE_RACL_POLICY_SHADOWED_13 | 0x254 | +| RANGE_RACL_POLICY_SHADOWED_14 | 0x258 | +| RANGE_RACL_POLICY_SHADOWED_15 | 0x25c | +| RANGE_RACL_POLICY_SHADOWED_16 | 0x260 | +| RANGE_RACL_POLICY_SHADOWED_17 | 0x264 | +| RANGE_RACL_POLICY_SHADOWED_18 | 0x268 | +| RANGE_RACL_POLICY_SHADOWED_19 | 0x26c | +| RANGE_RACL_POLICY_SHADOWED_20 | 0x270 | +| RANGE_RACL_POLICY_SHADOWED_21 | 0x274 | +| RANGE_RACL_POLICY_SHADOWED_22 | 0x278 | +| RANGE_RACL_POLICY_SHADOWED_23 | 0x27c | +| RANGE_RACL_POLICY_SHADOWED_24 | 0x280 | +| RANGE_RACL_POLICY_SHADOWED_25 | 0x284 | +| RANGE_RACL_POLICY_SHADOWED_26 | 0x288 | +| RANGE_RACL_POLICY_SHADOWED_27 | 0x28c | +| RANGE_RACL_POLICY_SHADOWED_28 | 0x290 | +| RANGE_RACL_POLICY_SHADOWED_29 | 0x294 | +| RANGE_RACL_POLICY_SHADOWED_30 | 0x298 | +| RANGE_RACL_POLICY_SHADOWED_31 | 0x29c | + + +### Fields + +```wavejson +{"reg": [{"name": "read_perm", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "write_perm", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------|:--------------------------------| +| 31:16 | rw | 0x0 | write_perm | Write permission policy bitmap. | +| 15:0 | rw | 0x0 | read_perm | Read permission policy bitmap. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/theory_of_operation.md b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/theory_of_operation.md new file mode 100644 index 00000000000..08fd714a587 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/doc/theory_of_operation.md @@ -0,0 +1,37 @@ +# Theory of Operation + +The following pseudo-code illustrates the range check logic, incorporating range priorities and access control rules. +The default system behavior is to deny access unless explicitly allowed by the range configuration. +The incoming address is compared against each enabled range register, and access control decisions are made based on matching and permissions. +The priority order (a lower range slot has a higher priority) of the ranges ensures that higher-priority ranges override lower-priority ones when a conflict occurs (i.e., if more than one range matches the incoming request). + +``` +def range_check_access(address, access_type): + access_granted = False # Default: access is denied + for i = 0 to (num_ranges - 1): # Iterate through ranges, starting from the highest priority + if range[i].enabled: # Only process enabled ranges + # Address matching based on base/limit + if (range[i].base >= address) and (address < range[i].limit): + range_match = True + else: + range_match = False + + # If address matches within this range, check permissions + if range_match: + if access_type == EXECUTE and range[i].execute and access_role in range[i].read_perm: + access_granted == True + else if access_type == READ and range[i].read and access_role in range[i].read_perm: + access_granted = True + else if access_type == WRITE and range[i].write and access_role in range[i].write_perm: + access_granted = True + else: + access_granted = False # No matching permissions + # Stop after the first match (highest-priority range matched) + break + + # Return the final access decision + if access_granted: + return ACCESS_GRANTED + else: + return ACCESS_DENIED +``` diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/README.md new file mode 100644 index 00000000000..f3d307d2552 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/README.md @@ -0,0 +1,130 @@ +# AC_RANGE_CHECK DV document + +## Goals +* **DV** + * Verify all AC_RANGE_CHECK IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + +## Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/latest/report.html) + +## Design features +For detailed information on `ac_range_check` design features, please see the [`ac_range_check` HWIP technical specification](../README.md). + +## Testbench architecture +The `ac_range_check` UVM DV testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) +Note: this diagram is editable from [this address](https://docs.google.com/drawings/d/1-0r4V6H8RwLeiAa3ng73vcDZdCbeeuFDYPZcX-QXRYo/edit?usp=sharing). + +### Top level testbench +Top level testbench is located at `hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tb/tb.sv`. +It instantiates the `ac_range_check` DUT module `hw/ip/ac_range_check/rtl/ac_range_check.sv`. +In addition, the testbench instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [Reset shadowed interface](../../../../dv/sv/common_ifs/README.md) // TODO add something in this doc about this interface. +* [TileLink host interface for the CSRs](../../../../dv/sv/tl_agent/README.md) +* [TileLink host interface for the Unfiltered CTN accesses](../../../../dv/sv/tl_agent/README.md) +* [TileLink device interface for the Filtered CTN accesses](../../../../dv/sv/tl_agent/README.md) +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Compile-time configurations +[list compile time configurations, if any and what are they used for] + +### Global types & methods +All common types and methods defined at the package level can be found in `ac_range_check_env_pkg`. +Some of them in use are: +```systemverilog +[list a few parameters, types & methods; no need to mention all] +``` + +### TL_agent +* `ac_range_check` UVM environment instantiates a (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into `ac_range_check` device, to access to the CSRs (Control/Status Registers). +* Host interface to the Unfiltered CTN accesses. +* Device interface to the Filtered CTN accesses. + +The `tl_agent` monitor supplies partial TileLink request packets as well as completed TileLink response packets over the TLM analysis port for further processing within the `ac_range_check` scoreboard. + +### Alert_agent +`ac_range_check` testbench instantiates (already handled in CIP base env) [alert_agents](../../../../dv/sv/alert_esc_agent/README.md): +[list alert names]. +The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in AC_RANGE_CHECK device. + +### UVM RAL Model +The `ac_range_check` RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md): + +#### Sequence cfg +An efficient way to develop test sequences is by providing some random variables that are used to configure the DUT / drive stimulus. +The random variables are constrained using weights and knobs that can be controlled. +These weights and knobs take on a "default" value that will result in the widest exploration of the design state space, when the test sequence is randomized and run as-is. +To steer the randomization towards a particular distribution or to achieve interesting combinations of the random variables, the test sequence can be extended to create a specialized variant. +In this extended sequence, nothing would need to be done, other than setting those weights and knobs appropriately. +This helps increase the likelihood of hitting the design corners that would otherwise be difficult to achieve, while maximizing reuse. + +This object aims to provide such run-time controls. + +#### Env cfg +The `ac_range_check_env_cfg`, environment configuration object provides access to the following elements: +* Build-time controls to configure the UVM environment composition during the `build_phase` +* Downstream agent configuration objects for ease of lookup from any environment component + * This includes the `tl_agent_cfg` objects for both TL interfaces +* All virtual interfaces that connect to the DUT listed above (retrieved from the `uvm_config_db`) +* Sequence configuration object described above + +All environment components contain a handle to an instance of this class (that was created in the test class via the parent `dv_base_test`). +By housing all of the above, all pertinent information is more easily shared with all environment components. + +### Stimulus strategy +#### Test sequences +All test sequences reside in `hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib`. +The `ac_range_check_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +All test sequences are extended from `ac_range_check_base_vseq`. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: From `hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq/ac_range_check_base_vseq.sv`, +* task 1: +* task 2: + +#### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* cg1: +* cg2: + +### Self-checking strategy +#### Scoreboard +It creates the following analysis ports to retrieve the data monitored by corresponding interface agents: +* analysis port1: +* analysis port2: + + +#### Assertions +* TLUL assertions: The `hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. +* assert prop 1: +* assert prop 2: + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ cd $REPO_TOP +$ ./util/dvsim/dvsim.py hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson -i ac_range_check_smoke +``` + +## Testplan +[Testplan](../data/ac_range_check_testplan.hjson) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/ac_range_check_sim.core b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/ac_range_check_sim.core new file mode 100644 index 00000000000..102e56ac313 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/ac_range_check_sim.core @@ -0,0 +1,32 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:ac_range_check_sim:0.1 +description: "AC_RANGE_CHECK DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:darjeeling_no_ibex_ip:ac_range_check:0.1 + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:ac_range_check_test + - lowrisc:darjeeling_no_ibex_dv:ac_range_check_sva + files: + - env/ac_range_check_misc_io_if.sv + - tb/tb.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson new file mode 100644 index 00000000000..a4a9057d82b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson @@ -0,0 +1,86 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: ac_range_check + + // Top level dut name (sv module). + dut: ac_range_check + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: xcelium + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_dv:ac_range_check_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/ac_range_check_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", // TODO MVy needed? + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["ac_range_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: ac_range_check_base_test + uvm_test_seq: ac_range_check_base_vseq + + // List of test specifications. + tests: [ + { + name: ac_range_check_smoke + uvm_test_seq: ac_range_check_smoke_vseq + reseed: 20 + } + { + name: ac_range_check_smoke_racl + uvm_test_seq: ac_range_check_smoke_racl_vseq + reseed: 20 + } + { + name: ac_range_check_bypass + uvm_test_seq: ac_range_check_bypass_vseq + reseed: 1 + } + { + name: ac_range_check_lock_range + uvm_test_seq: ac_range_check_lock_range_vseq + reseed: 20 + } + + // TODO: add more tests here + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["ac_range_check_smoke", "ac_range_check_smoke_racl"] + } + { + name: normal + tests: ["ac_range_check_smoke", + "ac_range_check_smoke_racl", + "ac_range_check_bypass", + "ac_range_check_lock_range" + ] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/doc/tb.svg b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/doc/tb.svg new file mode 100644 index 00000000000..f35cb2fe9de --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_dut_cfg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_dut_cfg.sv new file mode 100644 index 00000000000..0c879bf4843 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_dut_cfg.sv @@ -0,0 +1,52 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This class is a bundle that contains all the configuration parameters for the DUT. This avoids +// repeating the variable declaration multiple times. On the other hand, their constraints must not +// be contained in this file, but directly in the files where they are needed as this may lead to +// some conflicts. +class ac_range_check_dut_cfg extends uvm_object; + rand bit [TL_DW-1:0] range_base[NUM_RANGES]; // Granularity is 32-bit words, 2-LSBs are ignored + rand bit [TL_DW-1:0] range_limit[NUM_RANGES]; // Granularity is 32-bit words, 2-LSBs are ignored + rand range_attr_t range_attr[NUM_RANGES]; + rand racl_policy_t range_racl_policy[NUM_RANGES]; + + // Standard SV/UVM methods + extern function new(string name=""); + extern function void post_randomize(); + extern function void do_print(uvm_printer printer); + + // UVM Factory Registration Macro + `uvm_object_utils_begin (ac_range_check_dut_cfg) + `uvm_field_sarray_int(range_base, UVM_DEFAULT) + `uvm_field_sarray_int(range_limit, UVM_DEFAULT) + `uvm_object_utils_end +endclass : ac_range_check_dut_cfg + + +function ac_range_check_dut_cfg::new(string name=""); + super.new(name); +endfunction : new + +function void ac_range_check_dut_cfg::post_randomize(); + if (uvm_top.get_report_verbosity_level() >= UVM_HIGH) begin + this.print(); + end +endfunction : post_randomize + +// Some types are unsupported by the macros and have to be implemented manually +function void ac_range_check_dut_cfg::do_print(uvm_printer printer); + `uvm_info(this.get_name(), "do_print function has been called", UVM_DEBUG); + super.do_print(printer); + + foreach (range_attr[i]) begin + printer.print_field($sformatf("range_attr[%0d]", i), "range_attr_t", $bits(range_attr[i]), + $sformatf("%p", range_attr[i])); + end + + foreach (range_racl_policy[i]) begin + printer.print_field($sformatf("range_racl_policy[%0d]", i), "racl_policy_t", + $bits(range_racl_policy[i]), $sformatf("%p", range_racl_policy[i])); + end +endfunction: do_print diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core new file mode 100644 index 00000000000..21c8295e44d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core @@ -0,0 +1,47 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:ac_range_check_env:0.1 +description: "AC_RANGE_CHECK DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:dv:dv_base_reg + - lowrisc:dv:dv_lib + files: + - ac_range_check_env_pkg.sv + - ac_range_check_dut_cfg.sv: {is_include_file: true} + - ac_range_check_scb_item.sv: {is_include_file: true} + - ac_range_check_env_cfg.sv: {is_include_file: true} + - ac_range_check_env_cov.sv: {is_include_file: true} + - ac_range_check_virtual_sequencer.sv: {is_include_file: true} + - ac_range_check_predictor.sv: {is_include_file: true} + - ac_range_check_scoreboard.sv: {is_include_file: true} + - ac_range_check_env.sv: {is_include_file: true} + - seq_lib/ac_range_check_vseq_list.sv: {is_include_file: true} + - seq_lib/ac_range_check_base_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_common_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_smoke_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_smoke_racl_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_bypass_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_lock_range_vseq.sv: {is_include_file: true} + - seq_lib/ac_range_check_stress_all_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: ac_range_check + ip_hjson: ../../data/ac_range_check.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv new file mode 100644 index 00000000000..642b32eba13 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv @@ -0,0 +1,64 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_env extends cip_base_env #( + .CFG_T (ac_range_check_env_cfg), + .COV_T (ac_range_check_env_cov), + .VIRTUAL_SEQUENCER_T(ac_range_check_virtual_sequencer), + .SCOREBOARD_T (ac_range_check_scoreboard) + ); + `uvm_component_utils(ac_range_check_env) + + tl_agent tl_unfilt_agt; + tl_agent tl_filt_agt; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); + extern function void connect_phase(uvm_phase phase); +endclass : ac_range_check_env + + +function ac_range_check_env::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new + +function void ac_range_check_env::build_phase(uvm_phase phase); + super.build_phase(phase); + + // Create Unfiltered TL agent + tl_unfilt_agt = tl_agent::type_id::create("tl_unfilt_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_unfilt_agt*", "cfg", cfg.tl_unfilt_agt_cfg); + cfg.tl_unfilt_agt_cfg.en_cov = cfg.en_cov; + + // Create Fltered TL agent + tl_filt_agt = tl_agent::type_id::create("tl_filt_agt", this); + uvm_config_db#(tl_agent_cfg)::set(this, "tl_filt_agt*", "cfg", cfg.tl_filt_agt_cfg); + cfg.tl_filt_agt_cfg.en_cov = cfg.en_cov; + + // Retrieve the ac_range_check_misc_io_if virtual interface + if (!uvm_config_db#(misc_vif_t)::get(this, "", "misc_vif", cfg.misc_vif)) begin + `uvm_fatal(`gfn, "Failed to get misc_vif from uvm_config_db") + end +endfunction : build_phase + +function void ac_range_check_env::connect_phase(uvm_phase phase); + super.connect_phase(phase); + if (cfg.en_scb) begin + tl_unfilt_agt.monitor.a_chan_port.connect( + scoreboard.predict.tl_unfilt_a_chan_fifo.analysis_export); + tl_unfilt_agt.monitor.d_chan_port.connect( + scoreboard.tl_unfilt_d_chan_fifo.analysis_export); + tl_filt_agt.monitor.a_chan_port.connect( + scoreboard.tl_filt_a_chan_fifo.analysis_export); + tl_filt_agt.monitor.d_chan_port.connect( + scoreboard.predict.tl_filt_d_chan_fifo.analysis_export); + end + if (cfg.is_active && cfg.tl_unfilt_agt_cfg.is_active) begin + virtual_sequencer.tl_unfilt_sqr = tl_unfilt_agt.sequencer; + end + if (cfg.is_active && cfg.tl_filt_agt_cfg.is_active) begin + virtual_sequencer.tl_filt_sqr = tl_filt_agt.sequencer; + end +endfunction : connect_phase diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv new file mode 100644 index 00000000000..380d281736c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv @@ -0,0 +1,70 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_env_cfg extends cip_base_env_cfg #(.RAL_T(ac_range_check_reg_block)); + + // Enabling Scoreboard checks downgrading in ac_range_check_scoreboard + // Addresses issue #27380 that identified in very specific scenarios no valid TLUL transactions + // will be ever generated + bit en_scb_err_downgrade; + + // External interfaces + misc_vif_t misc_vif; + + // External component config objects + rand tl_agent_cfg tl_unfilt_agt_cfg; + rand tl_agent_cfg tl_filt_agt_cfg; + + `uvm_object_utils_begin(ac_range_check_env_cfg) + `uvm_field_object(tl_unfilt_agt_cfg, UVM_DEFAULT) + `uvm_field_object(tl_filt_agt_cfg, UVM_DEFAULT) + `uvm_object_utils_end + + // Standard SV/UVM methods + extern function new(string name=""); + + // Class specific methods + extern function void initialize(bit [31:0] csr_base_addr = '1); +endclass : ac_range_check_env_cfg + + +function ac_range_check_env_cfg::new(string name=""); + super.new(name); +endfunction : new + +function void ac_range_check_env_cfg::initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = ac_range_check_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + + // Set shadow register error status + tl_intg_alert_fields[ral.alert_status.reg_intg_err] = 1; + shadow_update_err_status_fields[ral.alert_status.shadowed_update_err] = 1; + shadow_storage_err_status_fields[ral.alert_status.shadowed_storage_err] = 1; + + // TL Agent Configuration objects - Non RAL + // Create tl_unfilt agent config obj + tl_unfilt_agt_cfg = tl_agent_cfg::type_id::create("tl_unfilt_agt_cfg"); + tl_unfilt_agt_cfg.if_mode = dv_utils_pkg::Host; + + // Create tl_filt agent config obj + tl_filt_agt_cfg = tl_agent_cfg::type_id::create("tl_filt_agt_cfg"); + tl_filt_agt_cfg.if_mode = dv_utils_pkg::Device; + + // Set num_interrupts + begin + uvm_reg rg = ral.get_reg_by_name("intr_state"); + if (rg != null) begin + num_interrupts = ral.intr_state.get_n_used_bits(); + end + end + + // Used to allow reset operations without waiting for CSR accesses to complete + // At the moment resets will only be used in stress_all_with_rand_reset. + // Reset strategy in genral will need a rethink (Check PR #25463) + can_reset_with_csr_accesses = 1; + + // By default no error downgrade is allowed. + // Only in specific testcases this should be allowed + en_scb_err_downgrade = 0; +endfunction : initialize diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cov.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cov.sv new file mode 100644 index 00000000000..767508c1173 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cov.sv @@ -0,0 +1,281 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergroups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ + +class ac_range_check_env_cov extends cip_base_env_cov #(.CFG_T(ac_range_check_env_cfg)); + + `uvm_component_utils(ac_range_check_env_cov) + + // The base class provides the following handles for use: + // ac_range_check_env_cfg: cfg + + // Holds the type of TLUL transaction being processed by the predictor + ac_range_check_env_pkg::access_type_e access_type_cp; + + int idx_cp; // Range Index for which coverage is sampled + bit read_cp; // Read permission from CSR Attr field 1 = enabled, 0 = disabled + bit write_cp; // Write permission from CSR Attr field 1 = enabled, 0 = disabled + bit execute_cp; // Execute permission from CSR Attr field 1 = enabled, 0 = disabled + int role_cp; // Holds RACL Role Identifier + + bit access_permit_cp; // Access due to permissions 1 = Access permitted, 0 = Access denied + bit racl_cp; // Access due to RACL Check 1 = Access permitted, 0 = Access denied + bit range_en_cp; // State of specific Range Index at sampling point + // 1 = enabled, 0 = disabled + + bit addr_hit_cp; // State of Address Check at sampling 1 = hit, 0 = miss + bit all_index_miss_cp; // 1 = addr miss on all indexes, 0 = addr hit on some index range + + bit bypass_cp; // Bypass Mode 1 = enabled, 0 = disabled + bit lock_idx_cp; // Status of lock bit for an index 1 = locked, 0 = unlocked + + // Primary covergroup that verifies the operation of AC_RANGE_CHECK module. + // There are 4 parts to the cross in this covergroup. + // - Index that had the address match + // - Type of transaction observed + // - RWX permissions that was configured + // - Access Granted / Denied + // + // Illegal bins are specified to ensure all combinations that can never be seen are excluded from + // coverage reports and make them clean. If ever a situation is observed where an illegal_bins is + // sampled, it is treated on par with assertions and will trigger a simulation failure at the + // point of sampling an illegal bin. + + covergroup attr_perm_cg; + coverpoint idx_cp + { + bins index[] = {[0:NUM_RANGES-1]}; + } + + coverpoint access_type_cp; + coverpoint read_cp { bins disabled = {0}; bins enabled = {1}; } + coverpoint write_cp { bins disabled = {0}; bins enabled = {1}; } + coverpoint execute_cp { bins disabled = {0}; bins enabled = {1}; } + + + coverpoint access_permit_cp { bins deny = {0}; bins permit = {1}; } + + idx_X_access_type_X_read_X_write_X_execute_X_access_permit: + cross idx_cp, access_type_cp, read_cp, write_cp, execute_cp, access_permit_cp + { + + // If an execute transaction is observed and execute permission is enabled + // the transaction can never be filtered out. + illegal_bins deny_when_ex_is_set = + binsof (access_type_cp) intersect {ac_range_check_env_pkg::Execute} + && binsof (execute_cp) intersect {1} + && binsof (access_permit_cp) intersect {0}; + + // If an execute transaction is observed and execute permission is disabled + // the transaction will always be filtered out. + illegal_bins permit_when_ex_unset = + binsof (access_type_cp) intersect {ac_range_check_env_pkg::Execute} + && binsof (execute_cp) intersect {0} + && binsof (access_permit_cp) intersect {1}; + + + // If a write transaction is observed and write permissions are enabled + // the transaction can never be filtered out. + illegal_bins deny_when_wr_is_set = + binsof (access_type_cp) intersect {ac_range_check_env_pkg::Write} + && binsof (write_cp) intersect {1} + && binsof (access_permit_cp) intersect {0}; + + // If a write transaction is observed and write permission is disabled + // the transaction will always be filtered out. + illegal_bins permit_when_wr_unset = + binsof (access_type_cp) intersect {ac_range_check_env_pkg::Write} + && binsof (write_cp) intersect {0} + && binsof (access_permit_cp) intersect {1}; + + + // If a read transaction is observed and read permissions are enabled + // the transaction can never be filtered out. + illegal_bins deny_when_rd_is_set = + binsof (access_type_cp) intersect {ac_range_check_env_pkg::Read} + && binsof (read_cp) intersect {1} + && binsof (access_permit_cp) intersect {0}; + + // If a read transaction is observed and read permission is disabled + // the transaction will always be filtered out. + illegal_bins permit_when_rd_unset = + binsof (access_type_cp) intersect {ac_range_check_env_pkg::Read} + && binsof (read_cp) intersect {0} + && binsof (access_permit_cp) intersect {1}; + } + endgroup : attr_perm_cg + + + // RACL checks are not performed when normal range check has failed. + // This covergroup is sampled when RACL checks are performed. + covergroup racl_cg; + coverpoint idx_cp + { + bins index[] = {[0:NUM_RANGES-1]}; + } + + coverpoint role_cp + { + bins role[] = {[0:NUM_ROLES-1]}; + } + + coverpoint access_type_cp; + coverpoint racl_cp { bins deny = {0}; bins permit = {1}; } + + idx_X_access_type_X_role_X_racl : cross idx_cp, access_type_cp, role_cp, racl_cp; + endgroup : racl_cg + + // To observe that each index is enabled or disabled. + covergroup range_cg; + coverpoint idx_cp + { + bins index[] = {[0:NUM_RANGES-1]}; + } + + coverpoint range_en_cp { bins disabled = {0}; bins enabled = {1}; } + + idx_X_range_en : cross idx_cp, range_en_cp; + endgroup : range_cg + + // To ensure address matches are observed on all range indexes. + covergroup addr_match_cg; + coverpoint idx_cp + { + bins index[] = {[0:NUM_RANGES-1]}; + } + + coverpoint addr_hit_cp { bins miss = {0}; bins hit = {1}; } + + idx_X_addr_hit : cross idx_cp, addr_hit_cp; + endgroup : addr_match_cg + + // all_index_miss_cg is a negative covergroup. + // A situtation can occur when a TLUL transaction being checked by ac_range will miss all + // configured indexes and be denied. + covergroup all_index_miss_cg; + coverpoint all_index_miss_cp { bins addr_hit_seen = {0}; + bins addr_not_matched_in_any_index = {1}; } + endgroup : all_index_miss_cg + + covergroup bypass_cg; + coverpoint bypass_cp { bins disabled = {0}; bins enabled = {1}; } + endgroup : bypass_cg + + + covergroup range_lock_cg; + coverpoint idx_cp + { + bins index[] = {[0:NUM_RANGES-1]}; + } + + coverpoint range_en_cp { bins disabled = {0}; bins enabled = {1}; } + coverpoint lock_idx_cp { bins unlocked = {0}; bins locked = {1}; } + + idx_X_enable_X_lock : cross idx_cp, range_en_cp, lock_idx_cp; + endgroup : range_lock_cg + + // Standard SV/UVM methods + extern function new(string name, uvm_component parent); + extern function void build_phase(uvm_phase phase); + + extern function void sample_attr_cg(int idx, + ac_range_check_env_pkg::access_type_e access_type, + bit read_perm, bit write_perm, bit execute_perm, + bit acc_permit); + extern function void sample_racl_cg(int idx, + ac_range_check_env_pkg::access_type_e access_type, + int role, bit racl_check); + + extern function void sample_range_cg(int idx, bit range_en); + extern function void sample_addr_match_cg(int idx, bit addr_hit); + extern function void sample_all_index_miss_cg(); + extern function void sample_bypass_cg(bit bypass_en); + extern function void sample_range_lock_cg(int idx, bit enable, bit lock); +endclass : ac_range_check_env_cov + + +function ac_range_check_env_cov::new(string name, uvm_component parent); + super.new(name, parent); + attr_perm_cg = new(); + racl_cg = new(); + range_cg = new(); + addr_match_cg = new(); + all_index_miss_cg = new(); + bypass_cg = new(); + range_lock_cg = new(); +endfunction : new + +function void ac_range_check_env_cov::build_phase(uvm_phase phase); + super.build_phase(phase); + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details +endfunction : build_phase + + +function void ac_range_check_env_cov::sample_attr_cg(int idx, + ac_range_check_env_pkg::access_type_e access_type, + bit read_perm, bit write_perm, bit execute_perm, + bit acc_permit); + this.idx_cp = idx; + this.access_type_cp = access_type; + this.access_permit_cp = acc_permit; + this.read_cp = read_perm; + this.write_cp = write_perm; + this.execute_cp = execute_perm; + + attr_perm_cg.sample(); +endfunction : sample_attr_cg + +function void ac_range_check_env_cov::sample_racl_cg(int idx, + ac_range_check_env_pkg::access_type_e access_type, + int role, bit racl_check); + this.idx_cp = idx; + this.access_type_cp = access_type; + this.role_cp = role; + this.racl_cp = racl_check; + + racl_cg.sample(); +endfunction : sample_racl_cg + +function void ac_range_check_env_cov::sample_range_cg(int idx, bit range_en); + this.idx_cp = idx; + this.range_en_cp = range_en; + + range_cg.sample(); +endfunction : sample_range_cg + +function void ac_range_check_env_cov::sample_addr_match_cg(int idx, bit addr_hit); + this.idx_cp = idx; + this.addr_hit_cp = addr_hit; + + addr_match_cg.sample(); + + if (addr_hit) begin + this.all_index_miss_cp = 0; + all_index_miss_cg.sample(); + end +endfunction : sample_addr_match_cg + +function void ac_range_check_env_cov::sample_all_index_miss_cg(); + this.all_index_miss_cp = 1; + all_index_miss_cg.sample(); +endfunction : sample_all_index_miss_cg + +function void ac_range_check_env_cov::sample_bypass_cg(bit bypass_en); + this.bypass_cp = bypass_en; + bypass_cg.sample(); +endfunction : sample_bypass_cg + +function void ac_range_check_env_cov::sample_range_lock_cg(int idx, bit enable, bit lock); + this.idx_cp = idx; + this.range_en_cp = enable; + this.lock_idx_cp = lock; + + range_lock_cg.sample(); +endfunction : sample_range_lock_cg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env_pkg.sv new file mode 100644 index 00000000000..d0588ac0346 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_env_pkg.sv @@ -0,0 +1,118 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ac_range_check_env_pkg; + // Dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import tl_agent_pkg::*; + import dv_lib_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import ac_range_check_ral_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // Imports from packages + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4Width; + import prim_mubi_pkg::mubi4_bool_to_mubi; + import prim_mubi_pkg::mubi4_logic_test_true_strict; + import prim_mubi_pkg::mubi8_t; + import prim_mubi_pkg::MuBi8True; + import prim_mubi_pkg::MuBi8False; + import tl_agent_pkg::InstrTypeLsbPos; + import tl_agent_pkg::InstrTypeMsbPos; + + // Parameters + parameter uint NUM_ALERTS = 2; + parameter string LIST_OF_ALERTS[NUM_ALERTS] = {"recov_ctrl_update_err", "fatal_fault"}; + parameter uint NUM_RANGES = 32; + parameter uint NUM_ROLES = 16; + parameter uint ROLE_WIDTH = 4; + + // Types + typedef virtual ac_range_check_misc_io_if misc_vif_t; + + typedef enum int { + DenyCntReached = 0 + } ac_range_check_intr_e; + + typedef enum { + Read = 0, + Write = 1, + Execute = 2 + } access_type_e; + + typedef enum bit [1:0] { + AChanRead = 0, + AChanWrite = 1, + DChanRead = 2, + DChanWrite = 3 + } tl_phase_e; + + typedef enum bit { + AccessDenied = 0, + AccessGranted = 1 + } access_decision_e; + + typedef struct packed { + bit log_denied_access; + bit execute_access; + bit write_access; + bit read_access; + bit enable; + } range_attr_t; + + typedef struct packed { + bit [15:0] write_perm; + bit [15:0] read_perm; + } racl_policy_t; + + typedef struct packed { + bit instr_type; + bit write; + bit [AddrWidth-1:0] addr; + bit [MaskWidth-1:0] mask; + bit [DataWidth-1:0] data; + + bit [ROLE_WIDTH-1:0] role; + } tl_main_vars_t; + + // Functions + // Retrieve the index of the CSR based on its name + function automatic int get_csr_idx(string csr_ral_name, string csr_name); + string csr_name_with_idx; + for (int idx=0; idx= NrRaclPolicies) begin + `uvm_fatal("ac_range_check_misc_io_if", $sformatf("Invalid RACL policy index %0d", idx)) + end + racl_policies[idx] = perm; + endfunction : set_racl_policies + + function automatic racl_policy_t get_racl_policies(int unsigned idx); + if (idx >= NrRaclPolicies) begin + `uvm_fatal("ac_range_check_misc_io_if", $sformatf("Invalid RACL policy index %0d", idx)) + end + return racl_policies[idx]; + endfunction : get_racl_policies + +endinterface : ac_range_check_misc_io_if diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_predictor.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_predictor.sv new file mode 100644 index 00000000000..58c9db5a95d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_predictor.sv @@ -0,0 +1,358 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_predictor extends uvm_component; + `uvm_component_utils(ac_range_check_predictor) + + // Local objects + ac_range_check_dut_cfg dut_cfg; + ac_range_check_env_cfg env_cfg; + + // TODO: Add check to the coverage object such that it is not null when + // coverage is enabled + ac_range_check_env_cov cov; + + bit bypass_sampled; // This is used for sampling the bypass mode setup + + cip_tl_seq_item latest_filtered_item; + ac_range_check_scb_item exp_tl_filt_a_chan; + ac_range_check_scb_item exp_tl_unfilt_d_chan; + + // Local variables + int all_unfilt_a_chan_cnt; // Total number of received transactions on unfilt A channel + int exp_unfilt_d_chan_cnt; + int exp_filt_a_chan_cnt; + + // Local queues + access_decision_e tr_access_decision_q[$]; // Access decision for each incoming transaction + + // TLM FIFOs for incoming transactions from the monitors + uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_a_chan_fifo; + uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_d_chan_fifo; + + // Outgoing transactions which will be used in the scoreboard for comparison + uvm_blocking_put_port #(ac_range_check_scb_item) tl_filt_put; + uvm_blocking_put_port #(ac_range_check_scb_item) tl_unfilt_put; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); + extern function void check_phase(uvm_phase phase); + + // Class specific methods + extern task process_tl_unfilt_a_chan_fifo(output ac_range_check_scb_item tl_unfilt); + extern task get_tl_filt_d_chan_item(output ac_range_check_scb_item tl_filt); + extern task manage_tl_fifos(); + extern function void reset(string kind = "HARD"); + extern function access_decision_e check_access(tl_seq_item item); + extern function cip_tl_seq_item predict_tl_unfilt_d_chan(); +endclass : ac_range_check_predictor + + +function ac_range_check_predictor::new(string name="", uvm_component parent=null); + super.new(name, parent); + dut_cfg = ac_range_check_dut_cfg::type_id::create("dut_cfg"); + bypass_sampled = 0; +endfunction : new + +function void ac_range_check_predictor::build_phase (uvm_phase phase); + super.build_phase(phase); + // For incoming transactions + tl_unfilt_a_chan_fifo = new("tl_unfilt_a_chan_fifo", this); + tl_filt_d_chan_fifo = new("tl_filt_d_chan_fifo", this); + // For outgoing transactions + tl_filt_put = new("tl_filt_put", this); + tl_unfilt_put = new("tl_unfilt_put", this); +endfunction : build_phase + +// For A channels: +// - Denied TL transactions are filtered out. +// - Granted TL transactions are forwarded without any change. +// This task predicts the EXPECTED item only when the check_access called from +// process_tl_unfilt_a_chan_fifo returns AccessGranted. Gets the ACTUAL item from its dedicated +// queue. When both items are available, calls the comparison function. +// +// For D channels, when the check_access called from process_tl_unfilt_a_chan_fifo returns: +// - AccessDenied: the D fields of the item are fed with the info from the latest_filtered_item +// of the A channel. Additionally, d_error is set to high and d_data is set to 0 in case of a +// read/execute access. +// - AccessGranted: the responses provided by the TL device agent (tl_filt_agt) and received +// on the tl_filt_d_chan_fifo are forwarded without any change, except for d_data when the +// access is a write. In that case the d_data will be zeroed (REF_001), but it has been decided +// to ignore this field in that condition. Note: this is because we cannot stick an "x" into a +// FIFO, as mentioned in the PR #1236 ("to avoid unknown assertion failure on prim_fifo_sync"). +// This task predicts the EXPECTED item based on what has been assessed by the +// process_tl_unfilt_a_chan_fifo task (by calling the check_access function). Gets the ACTUAL item +// from its dedicated queue. When both items are available, calls the comparison function. +task ac_range_check_predictor::manage_tl_fifos(); + ac_range_check_scb_item exp_tl_filt_a_chan; + ac_range_check_scb_item exp_tl_unfilt_d_chan; + + exp_tl_filt_a_chan = ac_range_check_scb_item::type_id::create("exp_tl_filt_a_chan"); + exp_tl_unfilt_d_chan = ac_range_check_scb_item::type_id::create("exp_tl_unfilt_d_chan"); + + forever begin + // Wait until a transaction is available on the tl_unfilt_a_chan port and process it + process_tl_unfilt_a_chan_fifo(exp_tl_filt_a_chan); + + // When the predicted access is AccessGranted + if (tr_access_decision_q[all_unfilt_a_chan_cnt-1] == AccessGranted) begin + // Send the expected item to the scoreboard for checking + tl_filt_put.put(exp_tl_filt_a_chan); + // Get item from the tl_filt_d_chan_fifo (no process is required as it should just go through + // except for WRITE operations. + get_tl_filt_d_chan_item(exp_tl_unfilt_d_chan); + // In presence of a WRITE, see comment REF_001 + if (exp_tl_unfilt_d_chan.item.is_write()) begin + exp_tl_unfilt_d_chan.item.d_data = 0; + end + // When the predicted access is AccessDenied + end else begin + `uvm_create_obj(tl_seq_item, exp_tl_unfilt_d_chan.item) + // Predict what the DUT will build based on the latest_filtered_item on A channel + exp_tl_unfilt_d_chan.item = predict_tl_unfilt_d_chan(); + // Update the expected counter as this should match the actual + exp_unfilt_d_chan_cnt++; + exp_tl_unfilt_d_chan.cnt = exp_unfilt_d_chan_cnt; + end + // Send the expected item to the scoreboard for checking + tl_unfilt_put.put(exp_tl_unfilt_d_chan); + end +endtask : manage_tl_fifos + +// Get an item from the tl_unfilt_a_chan_fifo and call the check_access function to assess whether +// the current transaction should be granted or denied. +task ac_range_check_predictor::process_tl_unfilt_a_chan_fifo( + output ac_range_check_scb_item tl_unfilt); + tl_unfilt = ac_range_check_scb_item::type_id::create("tl_unfilt"); + tl_unfilt_a_chan_fifo.get(tl_unfilt.item); + all_unfilt_a_chan_cnt++; + `uvm_info(`gfn, $sformatf("Received tl_unfilt_a_chan unfiltered item #%0d:\n%0s", + all_unfilt_a_chan_cnt, tl_unfilt.item.sprint()), UVM_HIGH) + + // Store whether the access is granted or not, this info could be then retrieved by using the + // the queue index based on the all_unfilt_a_chan_cnt + tr_access_decision_q.push_back(check_access(tl_unfilt.item)); + + if (tr_access_decision_q[all_unfilt_a_chan_cnt-1] == AccessGranted) begin + exp_filt_a_chan_cnt++; + tl_unfilt.cnt = exp_filt_a_chan_cnt; + `uvm_info(`gfn, $sformatf({"EXPECTED filtered item #%0d/%0d on tl_unfilt_a_chan has been ", + "forwarded for comparison"}, exp_filt_a_chan_cnt, all_unfilt_a_chan_cnt), UVM_LOW) + end else begin + `uvm_info(`gfn, $sformatf("Item #%0d from tl_unfilt_a_chan has been filtered", + all_unfilt_a_chan_cnt), UVM_LOW) + `DV_CHECK_FATAL($cast(latest_filtered_item, tl_unfilt.item)); + end +endtask : process_tl_unfilt_a_chan_fifo + +// Get the item generated from the TB and sent to the tl_filt D channel. +task ac_range_check_predictor::get_tl_filt_d_chan_item(output ac_range_check_scb_item tl_filt); + tl_filt = ac_range_check_scb_item::type_id::create("tl_filt"); + // Timeout with an error if the FIFO remains empty + fork + `DV_WAIT_TIMEOUT(10_000_000, `gfn, "Unable to get any item from tl_filt_d_chan_fifo.", 0) + tl_filt_d_chan_fifo.get(tl_filt.item); + join_any + exp_unfilt_d_chan_cnt++; + tl_filt.cnt = exp_unfilt_d_chan_cnt; + `uvm_info(`gfn, $sformatf("Received tl_filt_d_chan item #%0d:\n%0s", + exp_unfilt_d_chan_cnt, tl_filt.item.sprint()), UVM_HIGH) +endtask : get_tl_filt_d_chan_item + +// Check whether the current TL access is granted. +// Note: if a request matches multiple ranges with conflicting permissions enabled, the priority is +// given to the first enabled matching range based on the register configuration order (index +// 0 has priority over 1 for example). Thus, directly return when an enabled matching range is +// granting or denying the access. +// TODO: check if RACL policies control is OK as done below +function access_decision_e ac_range_check_predictor::check_access(tl_seq_item item); + bit attr_ok; + bit racl_ok; + int racl_role; + bit [15:0] racl_perm; + + tlul_pkg::tl_a_user_t a_user; + + bit bypass_enable; + + ac_range_check_env_pkg::access_type_e access_type; // Type of transaction access (R/W/X) + + `uvm_info(`gfn, $sformatf("Analyzing unfiltered item #%0d", all_unfilt_a_chan_cnt), UVM_MEDIUM) + + // Check if bypass is enabled + bypass_enable = env_cfg.misc_vif.get_range_check_overwrite(); + + if (env_cfg.en_cov && !bypass_sampled) begin + // bypass_sampled is set so that we only need to sample coverage once per test and not per + // transaction + bypass_sampled = 1; + cov.sample_bypass_cg(bypass_enable); + end + + if (bypass_enable) begin + return AccessGranted; + end + + + // Due to the note above, we should keep this loop starting from index 0 + for (int i = 0; i < NUM_RANGES; i++) begin + // Start building coverage model right from the begining + if (env_cfg.en_cov) begin + cov.sample_range_cg(.idx(i), .range_en(dut_cfg.range_attr[i].enable)); + end + + // Skip disabled ranges + if (!dut_cfg.range_attr[i].enable) begin + continue; + end + + // At this point the range is enabled. We now check if the transaction + // address in within the address range specified. If the address is not + // in the range, move forward to the next range index + if (item.a_addr < dut_cfg.range_base[i] || item.a_addr >= dut_cfg.range_limit[i]) begin + `uvm_info(`gfn, $sformatf("Address 0x%0h not in range #%0d", item.a_addr, i), UVM_HIGH) + if (env_cfg.en_cov) begin + cov.sample_addr_match_cg(.idx(i), .addr_hit(0)); + end + continue; + end + + if (env_cfg.en_cov) begin + cov.sample_addr_match_cg(.idx(i), .addr_hit(1)); + end + + // At this point we know the address of the transaction address is within + // the values specified by the range index. Now check what kind of + // transaction we are observing and fetch the necessary permissions for + // the access type + if (item.is_write()) begin + attr_ok = dut_cfg.range_attr[i].write_access; + racl_perm = dut_cfg.range_racl_policy[i].write_perm; + access_type = ac_range_check_env_pkg::Write; + end else if (item.a_user[InstrTypeMsbPos:InstrTypeLsbPos] == MuBi4True) begin + attr_ok = dut_cfg.range_attr[i].execute_access; + racl_perm = dut_cfg.range_racl_policy[i].read_perm; // EXECUTE reuses READ in RACL + access_type = ac_range_check_env_pkg::Execute; + end else begin + attr_ok = dut_cfg.range_attr[i].read_access; + racl_perm = dut_cfg.range_racl_policy[i].read_perm; + access_type = ac_range_check_env_pkg::Read; + end + `uvm_info(`gfn, $sformatf("RACL Permissions: 0x%0h", racl_perm), UVM_MEDIUM) + + // Extract the role bits that are part of the a_user.rsvd field. + a_user = item.a_user; + racl_role = top_racl_pkg::tlul_extract_racl_role_bits(a_user.rsvd); + `uvm_info(`gfn, $sformatf("a_user: 0x%0h", a_user), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("racl_role: %0d", racl_role), UVM_MEDIUM) + + // Extract the RACL configuration bit for racl_role from the extracted + // shadow index register + racl_ok = racl_perm[racl_role]; + `uvm_info(`gfn, $sformatf("racl_ok: %0b", racl_ok), UVM_MEDIUM) + + // --------------------------------------------------------- + // Apply policy + // --------------------------------------------------------- + if (!attr_ok) begin + `uvm_info(`gfn, $sformatf("%s access to 0x%0h is *DENIED* by range_attr[%0d]", + access_type.name(), item.a_addr, i), UVM_MEDIUM) + // Sample coverage data + if (env_cfg.en_cov) begin + cov.sample_attr_cg(.idx(i), .access_type(access_type), + .read_perm (dut_cfg.range_attr[i].read_access ), + .write_perm (dut_cfg.range_attr[i].write_access ), + .execute_perm(dut_cfg.range_attr[i].execute_access), + .acc_permit(0)); + end + + return AccessDenied; + end + + if (!racl_ok) begin + `uvm_info(`gfn, $sformatf("%s access to 0x%0h is *DENIED* by range_racl_policy[%0d]", + access_type.name(), item.a_addr, i), UVM_MEDIUM) + if (env_cfg.en_cov) cov.sample_racl_cg(.idx(i), .access_type(access_type), + .role(racl_role), .racl_check(0)); + return AccessDenied; + end + + // At this point all checks have passed including RACL. So transaction is GRANTED access + if (env_cfg.en_cov) begin + cov.sample_attr_cg(.idx(i), .access_type(access_type), + .read_perm (dut_cfg.range_attr[i].read_access ), + .write_perm (dut_cfg.range_attr[i].write_access ), + .execute_perm(dut_cfg.range_attr[i].execute_access), + .acc_permit(1)); + cov.sample_racl_cg(.idx(i), .access_type(access_type), .role(racl_role), .racl_check(1)); + end + + `uvm_info(`gfn, $sformatf("%s access to 0x%0h is *GRANTED* by range[%0d]", + access_type.name(), item.a_addr, i), UVM_MEDIUM) + return AccessGranted; + end // end for i 0) begin + `uvm_error(`gfn, {"FIFO tl_unfilt_a_chan_fifo is not empty: not all the received TL", + " transactions have been compared."}) + end + + if (tl_filt_d_chan_fifo.size() > 0) begin + `uvm_error(`gfn, {"FIFO tl_filt_d_chan_fifo not empty: not all the received TL", + " transactions have been compared."}) + end +endfunction : check_phase diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_scb_item.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_scb_item.sv new file mode 100644 index 00000000000..49752872422 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_scb_item.sv @@ -0,0 +1,13 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Wrapper class to hold tl_seq_item and a counter for scoreboarding purposes +class ac_range_check_scb_item extends uvm_object; + `uvm_object_utils(ac_range_check_scb_item) + + tl_seq_item item; + int cnt; + + `uvm_object_new +endclass : ac_range_check_scb_item diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv new file mode 100644 index 00000000000..cb7295eee5e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv @@ -0,0 +1,410 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_scoreboard extends cip_base_scoreboard #( + .CFG_T(ac_range_check_env_cfg), + .RAL_T(ac_range_check_reg_block), + .COV_T(ac_range_check_env_cov) + ); + `uvm_component_utils(ac_range_check_scoreboard) + + // Local objects + ac_range_check_dut_cfg dut_cfg; + ac_range_check_predictor predict; + + // Local variables + int a_chan_matching_cnt; // Number of matching transactions on A channel + int d_chan_matching_cnt; // Number of matching transactions on D channel + int act_unfilt_d_chan_cnt; + int act_filt_a_chan_cnt; + uvm_event exp_tl_filt_ev; + uvm_event exp_tl_unfilt_ev; + + // Local queues + ac_range_check_scb_item exp_tl_filt_a_chan_q[$]; // Expected tl_filt items from the predictor + ac_range_check_scb_item exp_tl_unfilt_d_chan_q[$]; // Expected tl_unfilt items from the predictor + + // TLM FIFOs for incoming transactions from the monitors + uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_d_chan_fifo; + uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_a_chan_fifo; + + // Incoming transactions from the predictor + uvm_blocking_put_imp_filt #(ac_range_check_scb_item, ac_range_check_scoreboard) tl_filt_imp; + uvm_blocking_put_imp_unfilt #(ac_range_check_scb_item, ac_range_check_scoreboard) tl_unfilt_imp; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); + extern function void connect_phase(uvm_phase phase); + extern task run_phase(uvm_phase phase); + extern function void check_phase(uvm_phase phase); + extern function void report_phase(uvm_phase phase); + + // Class specific methods + extern task get_tl_unfilt_d_chan_item(output ac_range_check_scb_item tl_unfilt); + extern task get_tl_filt_a_chan_item(output ac_range_check_scb_item tl_filt); + extern task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + extern task tl_filt_wait_and_compare(); + extern task tl_unfilt_wait_and_compare(); + extern task put_filt(ac_range_check_scb_item tl_filt); + extern task put_unfilt(ac_range_check_scb_item tl_unfilt); + extern function void reset(string kind = "HARD"); + extern function void compare_tl_item(string tl_type, ac_range_check_scb_item exp, + ac_range_check_scb_item act); +endclass : ac_range_check_scoreboard + + +function ac_range_check_scoreboard::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new + +function void ac_range_check_scoreboard::build_phase(uvm_phase phase); + super.build_phase(phase); + dut_cfg = ac_range_check_dut_cfg::type_id::create("dut_cfg"); + predict = ac_range_check_predictor::type_id::create("predict", this); + predict.dut_cfg = dut_cfg; + predict.cov = cov; + predict.env_cfg = cfg; + exp_tl_filt_ev = new(); + exp_tl_unfilt_ev = new(); + tl_unfilt_d_chan_fifo = new("tl_unfilt_d_chan_fifo", this); + tl_filt_a_chan_fifo = new("tl_filt_a_chan_fifo", this); + tl_filt_imp = new("tl_filt_imp", this); + tl_unfilt_imp = new("tl_unfilt_imp", this); + // TODO: remove once support alert checking + do_alert_check = 0; +endfunction : build_phase + +function void ac_range_check_scoreboard::connect_phase(uvm_phase phase); + super.connect_phase(phase); + predict.tl_filt_put.connect(this.tl_filt_imp); + predict.tl_unfilt_put.connect(this.tl_unfilt_imp); +endfunction : connect_phase + +task ac_range_check_scoreboard::run_phase(uvm_phase phase); + super.run_phase(phase); + wait(cfg.under_reset); + forever begin + wait(!cfg.under_reset); + // This isolation fork is needed to ensure that "disable fork" call won't kill any other + // processes at the same level from the parent classes + fork begin : isolation_fork + fork + begin : main_thread + fork + predict.manage_tl_fifos(); + tl_filt_wait_and_compare(); + tl_unfilt_wait_and_compare(); + join + end + begin : reset_thread + wait(cfg.under_reset); + end + join_any + disable fork; // Terminates all descendants and sub-descendants of isolation_fork + end join + end +endtask : run_phase + +task ac_range_check_scoreboard::tl_filt_wait_and_compare(); + ac_range_check_scb_item act_tl_filt_a_chan; + ac_range_check_scb_item exp_tl_filt_a_chan; + + forever begin + // Wait until a transaction has been fed from the predictor + if (exp_tl_filt_a_chan_q.size() == 0) begin + exp_tl_filt_ev.wait_trigger; + end + // Get item from the exp_tl_filt_a_chan_q + exp_tl_filt_a_chan = exp_tl_filt_a_chan_q.pop_front(); + // Get item from the tl_filt_a_chan_fifo + get_tl_filt_a_chan_item(act_tl_filt_a_chan); + // Finally do the comparison of the filtered A channel items + compare_tl_item("tl_filt_a_chan", exp_tl_filt_a_chan, act_tl_filt_a_chan); + end +endtask : tl_filt_wait_and_compare + +task ac_range_check_scoreboard::tl_unfilt_wait_and_compare(); + ac_range_check_scb_item act_tl_unfilt_d_chan; + ac_range_check_scb_item exp_tl_unfilt_d_chan; + + forever begin + // Wait until a transaction has been fed from the predictor + if (exp_tl_unfilt_d_chan_q.size() == 0) begin + exp_tl_unfilt_ev.wait_trigger; + end + // Get item from the exp_tl_unfilt_d_chan_q + exp_tl_unfilt_d_chan = exp_tl_unfilt_d_chan_q.pop_front(); + // Get item from the tl_unfilt_d_chan_fifo + get_tl_unfilt_d_chan_item(act_tl_unfilt_d_chan); + // Finally do the comparison of the unfiltered D channel items + compare_tl_item("tl_unfilt_d_chan", exp_tl_unfilt_d_chan, act_tl_unfilt_d_chan); + end +endtask : tl_unfilt_wait_and_compare + +// As required by the macro uvm_blocking_put_imp_decl, we need to implement this task which will be +// called from the predictor when calling the "put" method +task ac_range_check_scoreboard::put_filt(ac_range_check_scb_item tl_filt); + exp_tl_filt_a_chan_q.push_back(tl_filt); + exp_tl_filt_ev.trigger; +endtask : put_filt + +// As required by the macro uvm_blocking_put_imp_decl, we need to implement this task which will be +// called from the predictor when calling the "put" method +task ac_range_check_scoreboard::put_unfilt(ac_range_check_scb_item tl_unfilt); + exp_tl_unfilt_d_chan_q.push_back(tl_unfilt); + exp_tl_unfilt_ev.trigger; +endtask : put_unfilt + +task ac_range_check_scoreboard::get_tl_unfilt_d_chan_item(output ac_range_check_scb_item tl_unfilt); + tl_unfilt = ac_range_check_scb_item::type_id::create("tl_unfilt"); + // Timeout with an error if the FIFO remains empty + fork + `DV_WAIT_TIMEOUT(10_000_000, `gfn, "Unable to get any item from tl_unfilt_d_chan_fifo.", 0) + tl_unfilt_d_chan_fifo.get(tl_unfilt.item); + join_any + act_unfilt_d_chan_cnt++; + tl_unfilt.cnt = act_unfilt_d_chan_cnt; + `uvm_info(`gfn, $sformatf("Received tl_unfilt_d_chan ACTUAL filtered item #%0d:\n%0s", + act_unfilt_d_chan_cnt, tl_unfilt.item.sprint()), UVM_HIGH) + `uvm_info(`gfn, $sformatf({"ACTUAL filtered item #%0d on tl_unfilt_d_chan has been ", + "forwarded for comparison"}, act_unfilt_d_chan_cnt), UVM_LOW) +endtask : get_tl_unfilt_d_chan_item + +task ac_range_check_scoreboard::get_tl_filt_a_chan_item(output ac_range_check_scb_item tl_filt); + tl_filt = ac_range_check_scb_item::type_id::create("tl_filt"); + // Timeout with an error if the FIFO remains empty + fork + `DV_WAIT_TIMEOUT(10_000_000, `gfn, "Unable to get any item from tl_filt_a_chan_fifo.", 0) + tl_filt_a_chan_fifo.get(tl_filt.item); + join_any + act_filt_a_chan_cnt++; + tl_filt.cnt = act_filt_a_chan_cnt; + `uvm_info(`gfn, $sformatf("Received tl_filt_a_chan ACTUAL filtered item #%0d:\n%0s", + act_filt_a_chan_cnt, tl_filt.item.sprint()), UVM_HIGH) + `uvm_info(`gfn, $sformatf({"ACTUAL filtered item #%0d on tl_filt_a_chan has been ", + "forwarded for comparison"}, act_filt_a_chan_cnt), UVM_LOW) +endtask : get_tl_filt_a_chan_item + +function void ac_range_check_scoreboard::compare_tl_item(string tl_type, + ac_range_check_scb_item exp, + ac_range_check_scb_item act); + int unsigned matching_cnt_increment = 0; + + `uvm_info(`gfn, $sformatf("EXPECTED %0s item:\n%0s", tl_type, exp.item.sprint()), UVM_HIGH) + + // Compare DUT output against the expected data + if (act.item.compare(exp.item)) begin + matching_cnt_increment = 1; + `uvm_info(`gfn, $sformatf("ACTUAL item matched the prediction for the %0s item #%0d", + tl_type, act.cnt), UVM_LOW) + end else begin + `uvm_info(`gfn, $sformatf("Trying to compare %0s ACTUAL item #%0d vs EXPECTED item #%0d", + tl_type, act.cnt, exp.cnt), UVM_LOW) + `uvm_error(`gfn, $sformatf({"ACTUAL and EXPECTED %0s items are not matching:\n\nACTUAL: \n%0s", + " \nEXPECTED: \n%0s"}, tl_type, act.item.sprint(), exp.item.sprint())) + end + + if (tl_type == "tl_filt_a_chan") begin + a_chan_matching_cnt += matching_cnt_increment; + end else if (tl_type == "tl_unfilt_d_chan") begin + d_chan_matching_cnt += matching_cnt_increment; + end else begin + `uvm_error(`gfn, $sformatf("The specified tl_type (%0s) doesn't exist!", tl_type)) + end +endfunction : compare_tl_item + +task ac_range_check_scoreboard::process_tl_access(tl_seq_item item, + tl_channels_e channel, + string ral_name); + uvm_reg csr; + string csr_name; + int csr_idx = -1; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + tl_phase_e tl_phase; + + // Note: AddrChannel and DataChannel don't exist in the TL spec. There is a confusion as TileLink + // defines 5 channels called A, B, C, D and E. But for TLUL version, only A and D are used. + if (!write && channel == AddrChannel) tl_phase = AChanRead; + if ( write && channel == AddrChannel) tl_phase = AChanWrite; + if (!write && channel == DataChannel) tl_phase = DChanRead; + if ( write && channel == DataChannel) tl_phase = DChanWrite; + + // If access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + // When the CSR is defined as an array, simplify the name to make it generic. This will be + // useful if the template parameter "num_ranges" is changed. + if (csr.get_type_name() == "ac_range_check_reg_range_regwen") begin + csr_name = "range_regwen"; + end else if (csr.get_type_name() == "ac_range_check_reg_range_base") begin + csr_name = "range_base"; + end else if (csr.get_type_name() == "ac_range_check_reg_range_limit") begin + csr_name = "range_limit"; + end else if (csr.get_type_name() == "ac_range_check_reg_range_attr") begin + csr_name = "range_attr"; + end else if (csr.get_type_name() == "ac_range_check_reg_range_racl_policy_shadowed") begin + csr_name = "range_racl_policy_shadowed"; + end else begin + csr_name = csr.get_name(); + end + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + csr_idx = get_csr_idx(csr.get_name(), csr_name); + + // If incoming access is a write to a valid csr, then make updates right away + if (tl_phase == AChanWrite) begin + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // Process the CSR req: + // - for write, update local variable and FIFO at AChanWrite phase + // - for read, update prediction at AChanRead phase and compare at DChanRead phase + case (csr_name) + // Add individual case item for each csr + "intr_state": begin + // FIXME TODO MVy + end + "intr_enable": begin + // FIXME TODO MVy + end + "intr_test": begin + // FIXME TODO MVy + end + "alert_test": begin + // FIXME TODO MVy + end + "alert_status": begin + // FIXME TODO MVy + end + "log_config": begin + // FIXME TODO MVy + end + "log_status": begin + // FIXME TODO MVy + end + "log_address": begin + // FIXME TODO MVy + end + "range_regwen": begin + // FIXME TODO MVy + end + "range_base": begin + if (tl_phase == AChanWrite) begin + dut_cfg.range_base[csr_idx] = `gmv(ral.range_base[csr_idx]); + end + end + "range_limit": begin + if (tl_phase == AChanWrite) begin + dut_cfg.range_limit[csr_idx] = `gmv(ral.range_limit[csr_idx]); + end + end + "range_attr": begin + if (tl_phase == AChanWrite) begin + dut_cfg.range_attr[csr_idx].log_denied_access = + mubi4_logic_test_true_strict(`gmv(ral.range_attr[csr_idx].log_denied_access)); + dut_cfg.range_attr[csr_idx].execute_access = + mubi4_logic_test_true_strict(`gmv(ral.range_attr[csr_idx].execute_access)); + dut_cfg.range_attr[csr_idx].write_access = + mubi4_logic_test_true_strict(`gmv(ral.range_attr[csr_idx].write_access)); + dut_cfg.range_attr[csr_idx].read_access = + mubi4_logic_test_true_strict(`gmv(ral.range_attr[csr_idx].read_access)); + dut_cfg.range_attr[csr_idx].enable = + mubi4_logic_test_true_strict(`gmv(ral.range_attr[csr_idx].enable)); + end + end + "range_racl_policy_shadowed": begin + if (tl_phase == AChanWrite) begin + dut_cfg.range_racl_policy[csr_idx].read_perm = + `gmv(ral.range_racl_policy_shadowed[csr_idx].read_perm); + dut_cfg.range_racl_policy[csr_idx].write_perm = + `gmv(ral.range_racl_policy_shadowed[csr_idx].write_perm); + end + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (tl_phase == DChanRead) begin + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end +endtask : process_tl_access + +function void ac_range_check_scoreboard::reset(string kind = "HARD"); + super.reset(kind); + predict.reset(kind); + tl_unfilt_d_chan_fifo.flush(); + tl_filt_a_chan_fifo.flush(); + act_unfilt_d_chan_cnt = 0; + act_filt_a_chan_cnt = 0; + a_chan_matching_cnt = 0; + d_chan_matching_cnt = 0; +endfunction : reset + +function void ac_range_check_scoreboard::check_phase(uvm_phase phase); + super.check_phase(phase); + + // This condition seems useless, but the way the environment builds the scoreboard, it doesn't + // care about this configuration field for some reason. We don't need to check the following + // things when the ran test is related to the CSR checks in particular. + if (cfg.en_scb) begin + if (a_chan_matching_cnt == 0) begin + // Downgrading this to an info. If all input TL transaction for some reason get + // filtered, the block has legally done its job. Cannot downgrade this to a warning as all + // warnings are also treated as errors. + + // There is a legal scenario where all range indexes are disabled and bypass is also disabled, + // then all TLUL transactions are DENIED and will never see a_chan_matching_cnt > 0 + // Other scenario where no TLUL traffic will be observed are standard CSR tests + // The scoreboard is usually disabled for the standard CIP tests, but for intr_test + // scoreboard will be enabled and this specific check has to be disabled + if (cfg.en_scb_err_downgrade) begin + `uvm_info(`gfn, {"No matching transaction found, it can be because all the TL accesses ", + "have been filtered. Please check your DUT configuration and your sequence."}, UVM_LOW) + end else begin + `uvm_error(`gfn, {"No matching transaction found, it can be because all the TL accesses ", + "have been filtered. Please check your DUT configuration and your sequence."}) + end + end + + if (d_chan_matching_cnt != predict.all_unfilt_a_chan_cnt) begin + `uvm_error(`gfn, $sformatf({"The number of matching transactions on the A and on the D ", + "channels must be equal: all_unfilt_a_chan_cnt=%0d vs d_chan_matching_cnt=%0d"}, + predict.all_unfilt_a_chan_cnt, d_chan_matching_cnt)) + end + + if (tl_unfilt_d_chan_fifo.size() > 0) begin + `uvm_error(`gfn, {"FIFO tl_unfilt_d_chan_fifo is not empty: not all the received TL", + " transactions have been compared."}) + end + + if (tl_filt_a_chan_fifo.size() > 0) begin + `uvm_error(`gfn, {"FIFO tl_filt_a_chan_fifo is not empty: not all the received TL", + " transactions have been compared."}) + end + end +endfunction : check_phase + +function void ac_range_check_scoreboard::report_phase(uvm_phase phase); + super.report_phase(phase); + `uvm_info(`gfn, + $sformatf("The number of transactions that matched the prediction on a_chan is %0d", + a_chan_matching_cnt), + UVM_MEDIUM) + `uvm_info(`gfn, + $sformatf("The number of transactions that matched the prediction on d_chan is %0d", + d_chan_matching_cnt), + UVM_MEDIUM) +endfunction : report_phase diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv new file mode 100644 index 00000000000..096537e3291 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(ac_range_check_env_cfg), + .COV_T(ac_range_check_env_cov) + ); + `uvm_component_utils(ac_range_check_virtual_sequencer) + + tl_sequencer tl_unfilt_sqr; + tl_sequencer tl_filt_sqr; + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); +endclass : ac_range_check_virtual_sequencer + +function ac_range_check_virtual_sequencer::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv new file mode 100644 index 00000000000..4617d96a102 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv @@ -0,0 +1,195 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Base sequence from which all other sequences must be derived. It contains the instantiation of +// the "dut_cfg" class which itself contains all variables relating to the DUT configuration. +// By default, we keep TL transactions random, as this can easily be overridden by derived +// sequences if required, as the constraints are declared "soft". +class ac_range_check_base_vseq extends cip_base_vseq #( + .RAL_T (ac_range_check_reg_block), + .CFG_T (ac_range_check_env_cfg), + .COV_T (ac_range_check_env_cov), + .VIRTUAL_SEQUENCER_T (ac_range_check_virtual_sequencer) + ); + `uvm_object_utils(ac_range_check_base_vseq) + + // Various knobs to enable certain routines + bit do_ac_range_check_init = 1; + + // Configuration variables + rand ac_range_check_dut_cfg dut_cfg; + rand tl_main_vars_t tl_main_vars; + rand int range_idx; + + // Constraints + extern constraint range_idx_c; + + // Standard SV/UVM methods + extern function new(string name=""); + + // Class specific methods + extern task dut_init(string reset_kind = "HARD"); + extern task ac_range_check_init(); + extern task cfg_range_base(); + extern task cfg_range_limit(); + extern task cfg_range_attr(); + extern task cfg_range_racl_policy(); + extern task send_single_tl_unfilt_tr(bit zero_delays = 0); + extern task tl_filt_device_auto_resp(int min_rsp_delay = 0, int max_rsp_delay = 80, + int rsp_abort_pct = 25, int d_error_pct = 0, int d_chan_intg_err_pct = 0); + extern virtual task configure_range(int unsigned idx = 0, bit [DataWidth-1:0] base = 0, + bit [DataWidth-1:0] limit = 0, bit read_perm = 0, bit write_perm = 0, bit execute_perm = 0, + bit en = 0); +endclass : ac_range_check_base_vseq + + +constraint ac_range_check_base_vseq::range_idx_c { + range_idx inside {[0:NUM_RANGES-1]}; +} + +function ac_range_check_base_vseq::new(string name=""); + super.new(name); + dut_cfg = ac_range_check_dut_cfg::type_id::create("dut_cfg"); +endfunction : new + +task ac_range_check_base_vseq::dut_init(string reset_kind = "HARD"); + // Initialize some of DUT inputs + cfg.misc_vif.set_range_check_overwrite(0); + cfg.misc_vif.init_racl_policies(); + + super.dut_init(); + + if (do_ac_range_check_init) begin + ac_range_check_init(); + end + + // Spawns off a thread to auto-respond to incoming TL accesses on the Filtered host interface. + // Note: the fork is required as the called sequence will loop indefinitely. + fork + tl_filt_device_auto_resp(); + join_none +endtask : dut_init + +task ac_range_check_base_vseq::ac_range_check_init(); + // This fork will ensure that configuration takes place in "disorder", as the TL register + // sequencer will have to deal with parallel requests (and random delays). + fork + cfg_range_base(); + cfg_range_limit(); + cfg_range_attr(); + cfg_range_racl_policy(); + join + // TODO lastly, randomly lock the configuration with RANGE_REGWEN +endtask : ac_range_check_init + +// Only update registers whose value does not match the new one (usage of set+update instead write) +task ac_range_check_base_vseq::cfg_range_base(); + foreach (dut_cfg.range_base[i]) begin + ral.range_base[i].set(dut_cfg.range_base[i]); + csr_update(.csr(ral.range_base[i])); + end +endtask : cfg_range_base + +task ac_range_check_base_vseq::cfg_range_limit(); + foreach (dut_cfg.range_limit[i]) begin + ral.range_limit[i].set(dut_cfg.range_limit[i]); + csr_update(.csr(ral.range_limit[i])); + end +endtask : cfg_range_limit + +task ac_range_check_base_vseq::cfg_range_attr(); + foreach (dut_cfg.range_attr[i]) begin + ral.range_attr[i].log_denied_access.set(mubi4_bool_to_mubi( + dut_cfg.range_attr[i].log_denied_access)); + ral.range_attr[i].execute_access.set(mubi4_bool_to_mubi(dut_cfg.range_attr[i].execute_access)); + ral.range_attr[i].write_access.set(mubi4_bool_to_mubi(dut_cfg.range_attr[i].write_access)); + ral.range_attr[i].read_access.set(mubi4_bool_to_mubi(dut_cfg.range_attr[i].read_access)); + ral.range_attr[i].enable.set(mubi4_bool_to_mubi(dut_cfg.range_attr[i].enable)); + csr_update(.csr(ral.range_attr[i])); + end +endtask : cfg_range_attr + +task ac_range_check_base_vseq::cfg_range_racl_policy(); + foreach (dut_cfg.range_racl_policy[i]) begin + ral.range_racl_policy_shadowed[i].set(dut_cfg.range_racl_policy[i]); + // Shadowed register: the 2 writes are automatically managed by the csr_utils_pkg + csr_update(.csr(ral.range_racl_policy_shadowed[i])); + end +endtask : cfg_range_racl_policy + +task ac_range_check_base_vseq::send_single_tl_unfilt_tr(bit zero_delays = 0); + cip_tl_host_single_seq tl_unfilt_host_seq; + `uvm_create_on(tl_unfilt_host_seq, p_sequencer.tl_unfilt_sqr) + if (zero_delays) begin + tl_unfilt_host_seq.min_req_delay = 0; + tl_unfilt_host_seq.max_req_delay = 0; + end + + `DV_CHECK_RANDOMIZE_WITH_FATAL(tl_unfilt_host_seq, + instr_type == mubi4_bool_to_mubi(tl_main_vars.instr_type); + write == tl_main_vars.write; + addr == tl_main_vars.addr; + mask == tl_main_vars.mask; + data == tl_main_vars.data; + racl_role == tl_main_vars.role;) + + csr_utils_pkg::increment_outstanding_access(); + `uvm_info(`gfn, "Starting tl_unfilt_host_seq", UVM_MEDIUM) + `DV_SPINWAIT(`uvm_send(tl_unfilt_host_seq), "Timed out when sending fetch request") + csr_utils_pkg::decrement_outstanding_access(); +endtask : send_single_tl_unfilt_tr + +task ac_range_check_base_vseq::tl_filt_device_auto_resp(int min_rsp_delay = 0, + int max_rsp_delay = 80, + int rsp_abort_pct = 25, + int d_error_pct = 0, + int d_chan_intg_err_pct = 0); + cip_tl_device_seq tl_filt_device_seq; + tl_filt_device_seq = cip_tl_device_seq::type_id::create("tl_filt_device_seq"); + tl_filt_device_seq.min_rsp_delay = min_rsp_delay; + tl_filt_device_seq.max_rsp_delay = max_rsp_delay; + tl_filt_device_seq.rsp_abort_pct = rsp_abort_pct; + tl_filt_device_seq.d_error_pct = d_error_pct; + tl_filt_device_seq.d_chan_intg_err_pct = d_chan_intg_err_pct; + `DV_CHECK_RANDOMIZE_FATAL(tl_filt_device_seq) + `uvm_info(`gfn, "Starting tl_filt_device_seq", UVM_MEDIUM) + tl_filt_device_seq.start(p_sequencer.tl_filt_sqr); +endtask : tl_filt_device_auto_resp + +task ac_range_check_base_vseq::configure_range(int unsigned idx = 0, + bit [DataWidth-1:0] base = 0, bit [DataWidth-1:0] limit = 0, bit read_perm = 0, + bit write_perm = 0, bit execute_perm = 0,bit en = 0); + + `uvm_info(`gfn, $sformatf("Configuring range index: %0d", idx), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("Base: 0%0h Limit:0%0h", base, limit), UVM_MEDIUM) + + // RANGE_BASE_x + ral.range_base[idx].set(base); + csr_update(.csr(ral.range_base[idx])); + + // RANGE_LIMIT_x + ral.range_limit[idx].set(limit); + csr_update(.csr(ral.range_limit[idx])); + + // Needed by the parent sequence to generate TLUL transaction with appropriate addresses. + // Randomisation is disabled on the base and limit so as to allow this sequence to do the + // appropriate lock range testing + dut_cfg.range_base[idx] = base; + dut_cfg.range_base[idx].rand_mode(0); + + dut_cfg.range_limit[idx] = limit; + dut_cfg.range_limit[idx].rand_mode(0); + + // RANGE_ATTR_x broken down into fields + ral.range_attr[idx].execute_access.set(mubi4_bool_to_mubi(execute_perm)); + ral.range_attr[idx].write_access.set (mubi4_bool_to_mubi(write_perm)); + ral.range_attr[idx].read_access.set (mubi4_bool_to_mubi(read_perm)); + ral.range_attr[idx].enable.set (mubi4_bool_to_mubi(en)); + csr_update(.csr(ral.range_attr[idx])); + + // Disable RACL side effects for simplicity. + ral.range_racl_policy_shadowed[idx].set(32'hFFFF_FFFF); + csr_update(.csr(ral.range_racl_policy_shadowed[idx])); + +endtask : configure_range diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_bypass_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_bypass_vseq.sv new file mode 100644 index 00000000000..b71e37857bb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_bypass_vseq.sv @@ -0,0 +1,39 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// High-level goal +// --------------- +// - Exercises the *bypass* feature for AC_RANGE_CHECK. +// - Confirms that once RANGE_CHECK_OVERWRITE interface is set, The module is in bypass mode and the +// design is transperent to all TLUL transactions on the TLUL unfiltered interface. +// - Runs live TLUL traffic to catch any functional issues. +// +// Key take-aways +// -------------- +// - Verifies that AC_RANGE_CHECK has no implications on TLUL traffic +//------------------------------------------------------------------------------ + +class ac_range_check_bypass_vseq extends ac_range_check_smoke_vseq; + `uvm_object_utils(ac_range_check_bypass_vseq) + + // Standard SV/UVM methods + extern function new(string name=""); + extern task body(); +endclass : ac_range_check_bypass_vseq + + + +function ac_range_check_bypass_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_bypass_vseq::body(); + + // AC_RANGE_CHECK can only be set to bypass when 'range_check_overwrite' pins are set to 1 + // This interface is part of the misc intf in the TB and direct access is available via the cfg in + // the TB. + cfg.misc_vif.set_range_check_overwrite(1); + + super.body(); +endtask : body diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv new file mode 100644 index 00000000000..f7a7d2a7fc2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_common_vseq.sv @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This sequence should only be used to run the CSR tests: +// - no need to have the scoreboard enabled (as it causes false errors with CSR tests) +// - no need to run multiple transactions. Hence, the constraint "num_trans" is set to 1 +class ac_range_check_common_vseq extends ac_range_check_base_vseq; + `uvm_object_utils(ac_range_check_common_vseq) + + // Constraints + extern constraint num_trans_c; + + // Standard SV/UVM methods + extern function new(string name=""); + extern task pre_start(); + extern task body(); +endclass : ac_range_check_common_vseq + + +constraint ac_range_check_common_vseq::num_trans_c { + num_trans == 1; +} + +function ac_range_check_common_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_common_vseq::pre_start(); + do_ac_range_check_init = 1'b0; + super.pre_start(); +endtask : pre_start + +task ac_range_check_common_vseq::body(); + run_common_vseq_wrapper(num_trans); +endtask : body diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_lock_range_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_lock_range_vseq.sv new file mode 100644 index 00000000000..96a53c74b3e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_lock_range_vseq.sv @@ -0,0 +1,269 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// High-level goal +// --------------- +// - Exercises the *range-locking* feature for AC_RANGE_CHECK. +// - Confirms that once RANGE_REGWEN_x is cleared, subsequent CSR writes to that +// range are ignored while unlocked ranges continue to accept re-programming. +// - Runs live TLUL traffic throughout to catch any functional regressions. +// +// Key take-aways +// -------------- +// - Verifies that locked ranges cannot be modified even by direct CSR writes. +// - Confirms unlocked ranges remain fully programmable. +// - Applies continuous traffic pressure to catch timing or side effect issues. +//------------------------------------------------------------------------------ + + +class ac_range_check_lock_range_vseq extends ac_range_check_smoke_vseq; + `uvm_object_utils(ac_range_check_lock_range_vseq) + + // --------------------------------------------------------------------------- + // Random knobs for every range + // --------------------------------------------------------------------------- + rand bit [DataWidth-1:0] base [NUM_RANGES]; + rand bit [DataWidth-1:0] limit [NUM_RANGES]; + + rand bit read_perm [NUM_RANGES]; + rand bit write_perm [NUM_RANGES]; + rand bit execute_perm[NUM_RANGES]; + + // Second set of values used in the re-program step + rand bit [DataWidth-1:0] base_new [NUM_RANGES]; + rand bit [DataWidth-1:0] limit_new [NUM_RANGES]; + + rand bit read_perm_new [NUM_RANGES]; + rand bit write_perm_new [NUM_RANGES]; + rand bit execute_perm_new[NUM_RANGES]; + + // Mask indicating which Range Indexes are locked + rand bit [NUM_RANGES-1:0] lock_mask; + + // Mask indicating which Range Indexes are enabled + // enable_new is the second set for the re-program step + rand bit [NUM_RANGES-1:0] enable; + rand bit [NUM_RANGES-1:0] enable_new; + + // Random delay in **clock cycles** before the re-program phase begins. + rand int unsigned reprogram_delay_clks; + + + // --------------------------------------------------------------------------- + // Constraints + // --------------------------------------------------------------------------- + constraint addr_pairs_c { + foreach (base[i]) { + // 16-Byte alignment + base [i][3:0] == 0; + limit [i][3:0] == 0; + base_new [i][3:0] == 0; + limit_new [i][3:0] == 0; + + // Forward ranges only + (limit [i] - base [i]) inside {[32'h100:32'h200]}; + (limit_new [i] - base_new [i]) inside {[32'h100:32'h200]}; + + // Ensure base is always less than limit + base [i] < limit [i]; + base_new [i] < limit_new [i]; + + + if (i == (NUM_RANGES-1)) { + // This is a catch all since there is a situation where the test fails due to a TB condition + // which checks for at least 1 TLUL GRANTED transaction. By enabling the write permission + // for the very last index and forcing a transaction that is guranteed to be GRANTED + // overcomes this restriction. + enable[i] == 1; + lock_mask[i] == 1; + write_perm[i] == 1; + } + } + } + + constraint mask_c { + // At least one index will be locked in the test. Similarly enable is also set so that there is + // atleast one index that is enabled + lock_mask != 0; + enable != 0; + enable_new != 0; + } + constraint reprogram_delay_clks_c { reprogram_delay_clks inside {[0:100]}; } + + // // Standard SV/UVM methods + extern function new(string name = ""); + extern virtual task body(); + +endclass : ac_range_check_lock_range_vseq + +function ac_range_check_lock_range_vseq::new(string name); + super.new(name); +endfunction + + +task ac_range_check_lock_range_vseq::body(); + // Local variable just for the body task + bit reprogram_done = 0; + + `uvm_info(`gfn, "Starting ac_range_check_lock_range_seq", UVM_LOW) + + `DV_CHECK_RANDOMIZE_FATAL(this) + this.base.rand_mode(0); + this.limit.rand_mode(0); + this.read_perm.rand_mode(0); + this.write_perm.rand_mode(0); + this.execute_perm.rand_mode(0); + this.enable.rand_mode(0); + this.base_new.rand_mode(0); + this.limit_new.rand_mode(0); + this.read_perm_new.rand_mode(0); + this.write_perm_new.rand_mode(0); + this.execute_perm_new.rand_mode(0); + this.enable_new.rand_mode(0); + this.lock_mask.rand_mode(0); + this.reprogram_delay_clks.rand_mode(0); + + //------------------------------------------------------------------ + // Step 1 : Configure every range once with *initial* values. + //------------------------------------------------------------------ + foreach (base[i]) begin + configure_range(i, base[i], limit[i], read_perm[i], write_perm[i], execute_perm[i], enable[i]); + end + + //------------------------------------------------------------------ + // Step 2 : Lock a random subset by clearing RANGE_REGWEN_x. + //------------------------------------------------------------------ + foreach (lock_mask[i]) begin + if (lock_mask[i]) begin + `uvm_info(`gfn, $sformatf("Range index: %0d Locked", i), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("enable: %0h", enable[i]), UVM_MEDIUM) + ral.range_regwen[i].set(32'h0); + csr_update(.csr(ral.range_regwen[i])); + end else begin + `uvm_info(`gfn, $sformatf("Range index: %0d Unlocked", i), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("enable: %0h", enable[i]), UVM_MEDIUM) + end + + // TODO(#27352): Coverage sampling needs to be moved to scoreboard. + // Currently in ac_range_check_scoreboard we are seeing TL transactions to range_regwen[i] + // register being dropped when a write with range_regwen[i] = 1. This needs to be debugged as + // a write to this register irrespective of the value triggers coverage sampling + if (cfg.en_cov) cov.sample_range_lock_cg(i, enable[i], lock_mask[i]); + end + + //------------------------------------------------------------------ + // Step 3 : Kick off traffic that runs until re-programming completes. A + // boolean flag `reprogram_done` communicates between the two forked threads. + //------------------------------------------------------------------ + fork + // Traffic thread - keep going until the flag is asserted. + begin : traffic_thread + while (!reprogram_done) begin + `DV_CHECK_RANDOMIZE_FATAL(this) + send_single_tl_unfilt_tr(0); + end + end + + // Re-Program thread + begin : reprogram_thread + cfg.clk_rst_vif.wait_clks(reprogram_delay_clks); + foreach (base_new[i]) begin + `uvm_info(`gfn, $sformatf("Attempting to reprogram Range index: %0d", i), UVM_MEDIUM) + if (lock_mask[i]) begin + int unsigned lsb; + + // The below temp variables are used for setting configuration for each range index. + bit [MuBi4Width-1:0] mubi4_execute; + bit [MuBi4Width-1:0] mubi4_write; + bit [MuBi4Width-1:0] mubi4_read; + bit [MuBi4Width-1:0] mubi4_enable; + bit [MuBi4Width-1:0] mubi4_log_denied; + + // Combination word that is needed to program the CSR for each Range Index Attribute + bit [DataWidth-1:0] mubi4_attr; + + // When range index is locked, the RTL and the RAL are in sync. Which means the RAL model + // is also locked for the sepcific index and the set methods for fields such as + // 'ral.range_attr[i].read_access.set(mubi4_bool_to_mubi(read_perm_new[i]));' + // 'ral.range_attr[i].write_access.set(mubi4_bool_to_mubi(write_perm_new[i]));' + // will not work. We need to build the attr field explictly and then write new values + // to the CSRlocation via csr_wr() method for base, limit & attr. + mubi4_execute = mubi4_bool_to_mubi(execute_perm_new[i]); + mubi4_write = mubi4_bool_to_mubi(write_perm_new[i] ); + mubi4_read = mubi4_bool_to_mubi(read_perm_new[i] ); + mubi4_enable = mubi4_bool_to_mubi(enable_new[i] ); + mubi4_log_denied = MuBi4True; + + // The attr register consist of 5 fields namely: + // log_denied_access, execute_access, write_access, read_access, enable. + // 'mubi4_attr' is used to build this word that will be written. + + // Variable reset before building the word to be written. + mubi4_attr = 0; + + // Insert log_denied into correct position + lsb = ral.range_attr[i].log_denied_access.get_lsb_pos(); + mubi4_attr |= mubi4_log_denied << lsb; + + // Insert Execute into correct position + lsb = ral.range_attr[i].execute_access.get_lsb_pos(); + mubi4_attr |= mubi4_execute << lsb; + + // Insert Write into correct position + lsb = ral.range_attr[i].write_access.get_lsb_pos(); + mubi4_attr |= mubi4_write << lsb; + + // Insert Read into correct position + lsb = ral.range_attr[i].read_access.get_lsb_pos(); + mubi4_attr |= mubi4_read << lsb; + + // Insert enable into correct position + lsb = ral.range_attr[i].enable.get_lsb_pos(); + mubi4_attr |= mubi4_enable << lsb; + + `uvm_info(`gfn, $sformatf("Setting mubi4_attr: 0x%0h", mubi4_attr), UVM_MEDIUM) + + // Attempt direct writes to a locked range; they should be ignored. + // Direct access is done here. If we attempt to set ral object expected results will not + // be observed at the interface.. + csr_wr(.ptr(ral.range_base [i]), .value(base_new[i] )); + csr_wr(.ptr(ral.range_limit[i]), .value(limit_new[i])); + csr_wr(.ptr(ral.range_attr [i]), .value(mubi4_attr )); + end else begin + // Unlocked ranges get a full, legal re-configuration. + configure_range(i, base_new[i], limit_new[i], read_perm_new[i], write_perm_new[i], + execute_perm_new[i], enable_new[i]); + end + end + reprogram_done = 1; + end + join + + //------------------------------------------------------------------ + // Step 4 : Read back registers and verify lock behaviour. + //------------------------------------------------------------------ + foreach (base[i]) begin + uvm_reg_data_t act_base , act_lim , act_attr; + csr_rd(.ptr(ral.range_base [i]), .value(act_base)); + csr_rd(.ptr(ral.range_limit[i]), .value(act_lim)); + csr_rd(.ptr(ral.range_attr [i]), .value(act_attr)); + + // Readback is done so that CSR data checks are done in the scoreboard to prove data integrity + // of the Locked Fields in the CSR. No further check here. + + `uvm_info(`gfn, $sformatf("Readback range index: %0d", i), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("act_base: 0x%0h, act_lim: 0x%0h, act_attr: 0x%0h", + act_base, act_lim, act_attr), UVM_MEDIUM) + + + // The lock range test fails because of a check in the scoreboard that has not seen a single + // transaction granted. By sending a TLUL request that gurantees to get granted, The TB + // condition is satisfied. + if (i == (NUM_RANGES-1)) begin + tl_main_vars.addr = base[i]; + tl_main_vars.write = 1; + send_single_tl_unfilt_tr(0); + end + end +endtask : body diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_racl_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_racl_vseq.sv new file mode 100644 index 00000000000..2f6bffc1fd9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_racl_vseq.sv @@ -0,0 +1,38 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_smoke_racl_vseq extends ac_range_check_smoke_vseq; + `uvm_object_utils(ac_range_check_smoke_racl_vseq) + + // Constraints + extern constraint range_attr_c; + extern constraint range_racl_policy_c; + + // Standard SV/UVM methods + extern function new(string name=""); +endclass : ac_range_check_smoke_racl_vseq + + +constraint ac_range_check_smoke_racl_vseq::range_attr_c { + foreach (dut_cfg.range_base[i]) { + dut_cfg.range_attr[i].execute_access == 1; + dut_cfg.range_attr[i].write_access == 1; + dut_cfg.range_attr[i].read_access == 1; + dut_cfg.range_attr[i].enable dist { + 0 :/ 1, + 1 :/ 2 + }; + } +} + +constraint ac_range_check_smoke_racl_vseq::range_racl_policy_c { + foreach (dut_cfg.range_racl_policy[i]) { + dut_cfg.range_racl_policy[i].write_perm inside {[16'h0000:16'hFFFF]}; + dut_cfg.range_racl_policy[i].read_perm inside {[16'h0000:16'hFFFF]}; + } +} + +function ac_range_check_smoke_racl_vseq::new(string name=""); + super.new(name); +endfunction : new diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv new file mode 100644 index 00000000000..1c7b216500e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_smoke_vseq.sv @@ -0,0 +1,124 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_smoke_vseq extends ac_range_check_base_vseq; + `uvm_object_utils(ac_range_check_smoke_vseq) + + // Local variables + rand bit zero_delays; + rand protected bit [NUM_RANGES-1:0] config_range_mask; // Which ranges should be constrained + + // Constraints + extern constraint num_trans_c; + extern constraint tmp_c; + extern constraint range_c; + extern constraint range_attr_c; + extern constraint range_racl_policy_c; + extern constraint tl_main_vars_addr_c; + extern constraint tl_main_vars_mask_c; + + // Standard SV/UVM methods + extern function new(string name=""); + extern task body(); +endclass : ac_range_check_smoke_vseq + + +constraint ac_range_check_smoke_vseq::num_trans_c { + num_trans inside {[50:100]}; +} + +// TODO remove this temporary directed constraint +constraint ac_range_check_smoke_vseq::tmp_c { + foreach (dut_cfg.range_base[i]) { + dut_cfg.range_attr[i].log_denied_access == 1; + } +} + +constraint ac_range_check_smoke_vseq::range_c { + solve config_range_mask before dut_cfg.range_base; + solve dut_cfg.range_base before dut_cfg.range_limit; + foreach (dut_cfg.range_limit[i]) { + // Limit always greater than base + dut_cfg.range_limit[i] > dut_cfg.range_base[i]; + if (config_range_mask[i]) { + // Range size in 32-bit words, it shouldn't be too large and let it be 1 word size + ((dut_cfg.range_limit[i] - dut_cfg.range_base[i]) >> 2) inside {[1:49]}; + } + } +} + +// Enable/allow the range 2/3 of the time, to get more granted accesses +constraint ac_range_check_smoke_vseq::range_attr_c { + foreach (dut_cfg.range_base[i]) { + dut_cfg.range_attr[i].execute_access dist { + 0 :/ 1, + 1 :/ 2 + }; + dut_cfg.range_attr[i].write_access dist { + 0 :/ 1, + 1 :/ 2 + }; + dut_cfg.range_attr[i].read_access dist { + 0 :/ 1, + 1 :/ 2 + }; + dut_cfg.range_attr[i].enable dist { + 0 :/ 1, + 1 :/ 2 + }; + } +} + +constraint ac_range_check_smoke_vseq::range_racl_policy_c { + foreach (dut_cfg.range_racl_policy[i]) { + soft dut_cfg.range_racl_policy[i].write_perm == 16'hFFFF; + soft dut_cfg.range_racl_policy[i].read_perm == 16'hFFFF; + } +} + +constraint ac_range_check_smoke_vseq::tl_main_vars_addr_c { + solve dut_cfg.range_base before tl_main_vars; + solve dut_cfg.range_limit before tl_main_vars; + solve range_idx before tl_main_vars; + tl_main_vars.addr dist { + // 98% more or less inside range, this will allow us to also test the range boundaries, as this + // is usually where bug are found (+/-2*32-bit words -> -8 for the range_base and +4 for the + // range_limit as range_limit is exclusive) + [dut_cfg.range_base[range_idx]-8 : dut_cfg.range_limit[range_idx]+4] :/ 98, + // 1% on the lowest part of the range + [0 : 9 ] :/ 1, + // 1% on the uppermost part of the range + [2^NUM_RANGES-10 : 2^NUM_RANGES-1 ] :/ 1 + }; +} + +constraint ac_range_check_smoke_vseq::tl_main_vars_mask_c { + soft tl_main_vars.mask == 'hF; +} + +function ac_range_check_smoke_vseq::new(string name=""); + super.new(name); +endfunction : new + +task ac_range_check_smoke_vseq::body(); + for (int i=1; i<=num_trans; i++) begin + `uvm_info(`gfn, $sformatf("Starting seq %0d/%0d", i, num_trans), UVM_LOW) + + // Randomly keep the same configuration to allow transactions back to back transactions, as no + // configuration change will happen in between + randcase + // 25% of the time, change the config + 1: begin + `DV_CHECK_RANDOMIZE_FATAL(this) + ac_range_check_init(); + end + // 75% of the time, keep the same config + 3: begin + `uvm_info(`gfn, $sformatf("Keep the same configuration for seq #%0d", i), UVM_MEDIUM) + end + endcase + send_single_tl_unfilt_tr(zero_delays); // Send a single TLUL seq with random zero delays + $display("\n"); + end +endtask : body diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_stress_all_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_stress_all_vseq.sv new file mode 100644 index 00000000000..a09af898fab --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_stress_all_vseq.sv @@ -0,0 +1,46 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_stress_all_vseq extends ac_range_check_base_vseq; + `uvm_object_utils(ac_range_check_stress_all_vseq) + + `uvm_object_new + + constraint num_trans_c { + num_trans inside {[3:6]}; + } + + task body(); + // ac-range_check_lock_range is removed since it corrupts the stress test. If lock_range test + // is executed no other test that follow the lock test will pass as the range indexes will be + // locked and can only be released via a HARD reset. + string seq_names[] = { + "ac_range_check_smoke_vseq", + "ac_range_check_smoke_racl_vseq", + "ac_range_check_bypass_vseq" + }; + + // Reset testing in sequences is flaky. At this time make sure all reset capability is disabled + this.do_apply_reset = 0; + + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + ac_range_check_base_vseq ac_range_check_vseq; + + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(ac_range_check_vseq, seq) + + ac_range_check_vseq.do_apply_reset = this.do_apply_reset; + + ac_range_check_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(ac_range_check_vseq) + + `uvm_info(`gfn, $sformatf("starting stress_all sub-sequence %s", seq_names[seq_idx]), UVM_LOW) + ac_range_check_vseq.start(p_sequencer); + end + endtask : body + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv new file mode 100644 index 00000000000..98bc1470291 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_vseq_list.sv @@ -0,0 +1,11 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "ac_range_check_base_vseq.sv" +`include "ac_range_check_smoke_vseq.sv" +`include "ac_range_check_smoke_racl_vseq.sv" +`include "ac_range_check_bypass_vseq.sv" +`include "ac_range_check_lock_range_vseq.sv" +`include "ac_range_check_common_vseq.sv" +`include "ac_range_check_stress_all_vseq.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv new file mode 100644 index 00000000000..87cc1a4fb82 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/sva/ac_range_check_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ac_range_check_bind; + + bind ac_range_check tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind ac_range_check ac_range_check_csr_assert_fpv ac_range_check_csr_assert ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/sva/ac_range_check_sva.core b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/sva/ac_range_check_sva.core new file mode 100644 index 00000000000..1494aa2dcb1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/sva/ac_range_check_sva.core @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:ac_range_check_sva:0.1 +description: "AC_RANGE_CHECK assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - ac_range_check_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:darjeeling_no_ibex_ip:ac_range_check + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/ac_range_check.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: ac_range_check diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tb/tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tb/tb.sv new file mode 100644 index 00000000000..a1d83b283dc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tb/tb.sv @@ -0,0 +1,74 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // Dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import ac_range_check_env_pkg::*; + import ac_range_check_test_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk; + wire rst_n; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire rst_shadowed_n; + wire intr_deny_cnt_reached; + + // Interfaces + pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts); + clk_rst_if clk_rst_if (.clk(clk), .rst_n(rst_n)); + rst_shadowed_if rst_shad_if (.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n)); + tl_if tl_csr_if (.clk(clk), .rst_n(rst_n)); + tl_if tl_unfilt_if (.clk(clk), .rst_n(rst_n)); + tl_if tl_filt_if (.clk(clk), .rst_n(rst_n)); + ac_range_check_misc_io_if misc_if (); + + `DV_ALERT_IF_CONNECT() + + // DUT + ac_range_check dut ( + .clk_i (clk ), + .rst_ni (rst_n ), + .rst_shadowed_ni (rst_shadowed_n ), + // Alerts + .alert_rx_i (alert_rx ), + .alert_tx_o (alert_tx ), + // RACL interface + .racl_policies_i (misc_if.racl_policies ), + .racl_error_o (misc_if.racl_error ), + // Access range check interrupts + .intr_deny_cnt_reached_o (intr_deny_cnt_reached ), + // Bus interface + .tl_i (tl_csr_if.h2d ), + .tl_o (tl_csr_if.d2h ), + // Inter module signals + .range_check_overwrite_i (misc_if.range_check_overwrite), + // Incoming TLUL interface + .ctn_tl_h2d_i (tl_unfilt_if.h2d ), + .ctn_tl_d2h_o (tl_unfilt_if.d2h ), + // Filtered outgoing TLUL interface to the target if request is not squashed + .ctn_filtered_tl_h2d_o (tl_filt_if.h2d ), + .ctn_filtered_tl_d2h_i (tl_filt_if.d2h ) + ); + + assign interrupts[DenyCntReached] = intr_deny_cnt_reached; + + initial begin + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shad_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_csr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_unfilt_agt*", "vif", tl_unfilt_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_filt_agt*", "vif", tl_filt_if); + uvm_config_db#(misc_vif_t)::set(null, "*.env", "misc_vif", misc_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tests/ac_range_check_base_test.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tests/ac_range_check_base_test.sv new file mode 100644 index 00000000000..a11c49ac145 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tests/ac_range_check_base_test.sv @@ -0,0 +1,52 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class ac_range_check_base_test extends cip_base_test #( + .CFG_T(ac_range_check_env_cfg), + .ENV_T(ac_range_check_env) + ); + + `uvm_component_utils(ac_range_check_base_test) + + // The base class dv_base_test creates the following instances: + // - ac_range_check_env_cfg: cfg + // - ac_range_check_env: env + + // The base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in the run_phase. + // As such, nothing more needs to be done + + // Standard SV/UVM methods + extern function new(string name="", uvm_component parent=null); + extern function void build_phase(uvm_phase phase); +endclass : ac_range_check_base_test + + +function ac_range_check_base_test::new(string name="", uvm_component parent=null); + super.new(name, parent); +endfunction : new + +function void ac_range_check_base_test::build_phase(uvm_phase phase); + string test_seq_s; + string common_seq_type; + + super.build_phase(phase); + + // Disable some scoreboard checks for the CSR tests (unfortunately we cannot simply avoid the + // scoreboard to be created by setting this config flag, which should be the case) + void'($value$plusargs("UVM_TEST_SEQ=%0s", test_seq_s)); + void'($value$plusargs("run_%0s", common_seq_type)); + `uvm_info(`gfn, $sformatf("test_seq_s = %s", test_seq_s), UVM_LOW) + + if (common_seq_type != "") begin + `uvm_info(`gfn, $sformatf("common_seq_type = %s", common_seq_type), UVM_LOW) + end + + if (test_seq_s == "ac_range_check_common_vseq" && common_seq_type != "intr_test") begin + `uvm_info(`gfn, "Disabling scoreboard for common cip tests", UVM_LOW) + cfg.en_scb = 0; + end else if (test_seq_s == "ac_range_check_common_vseq" && common_seq_type == "intr_test") begin + `uvm_info(`gfn, "Running Interrupt Test - Downgrading error in scoreboard check_phase", UVM_LOW) + cfg.en_scb_err_downgrade = 1; + end +endfunction : build_phase diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tests/ac_range_check_test.core b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tests/ac_range_check_test.core new file mode 100644 index 00000000000..67c36ce79ad --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tests/ac_range_check_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:ac_range_check_test:0.1 +description: "AC_RANGE_CHECK DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:ac_range_check_env + files: + - ac_range_check_test_pkg.sv + - ac_range_check_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tests/ac_range_check_test_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tests/ac_range_check_test_pkg.sv new file mode 100644 index 00000000000..a409d852dcd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/dv/tests/ac_range_check_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package ac_range_check_test_pkg; + // Dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import ac_range_check_env_pkg::*; + + // Macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // Local types + + // Functions + + // Package sources + `include "ac_range_check_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/lint/ac_range_check.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/lint/ac_range_check.vlt new file mode 100644 index 00000000000..f5984ff79f6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/lint/ac_range_check.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for ac_range_check diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/lint/ac_range_check.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/lint/ac_range_check.waiver new file mode 100644 index 00000000000..d1b68019ea8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/lint/ac_range_check.waiver @@ -0,0 +1,5 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for ac_range_check diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/rtl/ac_range_check.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/rtl/ac_range_check.sv new file mode 100644 index 00000000000..dd2bf85fd56 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/rtl/ac_range_check.sv @@ -0,0 +1,398 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ac_range_check + import tlul_pkg::*; + import ac_range_check_reg_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert signal + parameter int unsigned AlertSkewCycles = 1, + parameter bit RangeCheckErrorRsp = 1'b1, + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = EnableRacl, + parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[NumRegs] = '{NumRegs{0}} +) ( + input logic clk_i, + input logic rst_ni, + input logic rst_shadowed_ni, + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output top_racl_pkg::racl_error_log_t racl_error_o, + // Access range check interrupts + output logic intr_deny_cnt_reached_o, + // Bus interface + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // Inter module signals + // SEC_CM: INTERSIG.MUBI + input prim_mubi_pkg::mubi8_t range_check_overwrite_i, + // Incoming TLUL interface + input tlul_pkg::tl_h2d_t ctn_tl_h2d_i, + output tlul_pkg::tl_d2h_t ctn_tl_d2h_o, + // Filtered outgoing TLUL interface to the target if request is not squashed + output tlul_pkg::tl_h2d_t ctn_filtered_tl_h2d_o, + input tlul_pkg::tl_d2h_t ctn_filtered_tl_d2h_i +); + ac_range_check_reg2hw_t reg2hw; + ac_range_check_hw2reg_t hw2reg; + + ////////////////////////////////////////////////////////////////////////////// + // Register Interface + ////////////////////////////////////////////////////////////////////////////// + logic reg_intg_error, shadowed_storage_err, shadowed_update_err; + // SEC_CM: BUS.INTEGRITY + // SEC_CM: CTRL.MUBI + // SEC_CM: CTRL.REGWEN_MUBI + ac_range_check_reg_top #( + .EnableRacl(EnableRacl), + .RaclErrorRsp(RaclErrorRsp), + .RaclPolicySelVec(RaclPolicySelVec) + ) u_ac_range_check_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .rst_shadowed_ni ( rst_shadowed_ni ), + .tl_i ( tl_i ), + .tl_o ( tl_o ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + .racl_policies_i ( racl_policies_i ), + .racl_error_o ( racl_error_o ), + .shadowed_storage_err_o ( shadowed_storage_err ), + .shadowed_update_err_o ( shadowed_update_err ), + .intg_err_o ( reg_intg_error ) + ); + + ////////////////////////////////////////////////////////////////////////////// + // Alerts + ////////////////////////////////////////////////////////////////////////////// + logic [NumAlerts-1:0] alert_test, alert; + logic deny_cnt_error; + + assign alert[AlertRecovCtrlUpdateErrIdx] = shadowed_update_err; + assign alert[AlertFatalFaultIdx] = reg_intg_error | shadowed_storage_err | + deny_cnt_error; + + assign alert_test[AlertFatalFaultIdx] = reg2hw.alert_test.fatal_fault.q & + reg2hw.alert_test.fatal_fault.qe; + assign alert_test[AlertRecovCtrlUpdateErrIdx] = reg2hw.alert_test.recov_ctrl_update_err.q & + reg2hw.alert_test.recov_ctrl_update_err.qe; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .SkewCycles(AlertSkewCycles), + .IsFatal(i == AlertFatalFaultIdx) + ) u_prim_alert_sender ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alert[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + assign hw2reg.alert_status.shadowed_storage_err.d = 1'b1; + assign hw2reg.alert_status.shadowed_storage_err.de = shadowed_storage_err; + assign hw2reg.alert_status.shadowed_update_err.d = 1'b1; + assign hw2reg.alert_status.shadowed_update_err.de = shadowed_update_err; + assign hw2reg.alert_status.reg_intg_err.d = 1'b1; + assign hw2reg.alert_status.reg_intg_err.de = reg_intg_error; + assign hw2reg.alert_status.counter_err.d = 1'b1; + assign hw2reg.alert_status.counter_err.de = deny_cnt_error; + + ////////////////////////////////////////////////////////////////////////////// + // Range Check Logic + ////////////////////////////////////////////////////////////////////////////// + + logic [NumRanges-1:0] addr_hit; + logic [NumRanges-1:0] r_deny_mask, w_deny_mask, x_deny_mask, deny_mask; + logic [NumRanges-1:0] r_grant_mask, w_grant_mask, x_grant_mask, grant_mask; + logic [NumRanges-1:0] log_enable_mask; + logic [NumRanges-1:0] racl_read_hit, racl_write_hit; + + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(ctn_tl_h2d_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + + // Figure out whether the access is an instruction fetch ("execute") or not. Note that the + // following two signals are *not* complementary strictly speaking: if `instr_type` isn't a valid + // MuBi value, neither of them will be true, hence the access will not be granted at all. + logic no_exec_access, exec_access; + assign no_exec_access = prim_mubi_pkg::mubi4_test_false_strict( + prim_mubi_pkg::mubi4_t'(ctn_tl_h2d_i.a_user.instr_type)); + assign exec_access = prim_mubi_pkg::mubi4_test_true_strict( + prim_mubi_pkg::mubi4_t'(ctn_tl_h2d_i.a_user.instr_type)); + + // Figure out whether the access is a read, write, or execute. + logic read_access, write_access, execute_access; + assign read_access = (ctn_tl_h2d_i.a_opcode == Get) & no_exec_access; + assign write_access = (ctn_tl_h2d_i.a_opcode == PutFullData) | + (ctn_tl_h2d_i.a_opcode == PutPartialData); + assign execute_access = (ctn_tl_h2d_i.a_opcode == Get) & exec_access; + + for (genvar i = 0; i < NumRanges; i++) begin : gen_range_checks + // Extend base, limit, and mask to 32 bits + logic [31:0] base_ext, limit_ext; + logic tor_hit; + + assign base_ext = {reg2hw.range_base[i].q, 2'b00}; + assign limit_ext = {reg2hw.range_limit[i].q, 2'b00}; + + assign tor_hit = (ctn_tl_h2d_i.a_address >= base_ext) & + (ctn_tl_h2d_i.a_address < limit_ext); + + // Request hits an enabled range and comparison logic + assign addr_hit[i] = prim_mubi_pkg::mubi4_test_true_loose( + prim_mubi_pkg::mubi4_t'(reg2hw.range_attr[i].enable.q)) & tor_hit; + + // Perform RACL checks - check if the incoming role matches with the configured policy + assign racl_read_hit [i] = |(racl_role_vec & reg2hw.range_racl_policy_shadowed[i].read_perm.q); + assign racl_write_hit[i] = |(racl_role_vec & reg2hw.range_racl_policy_shadowed[i].write_perm.q); + + // Decode the multi-bit access fields for convenient access + logic perm_read_access, perm_write_access, perm_execute_access; + assign perm_read_access = prim_mubi_pkg::mubi4_test_true_strict( + prim_mubi_pkg::mubi4_t'(reg2hw.range_attr[i].read_access.q)) & + racl_read_hit[i]; + assign perm_write_access = prim_mubi_pkg::mubi4_test_true_strict( + prim_mubi_pkg::mubi4_t'(reg2hw.range_attr[i].write_access.q)) & + racl_write_hit[i]; + assign perm_execute_access = prim_mubi_pkg::mubi4_test_true_strict( + prim_mubi_pkg::mubi4_t'(reg2hw.range_attr[i].execute_access.q)) & + racl_read_hit[i]; + + // A range grants a request if the request address hits and the type of the access (R/W/X) is + // permitted by that range. In the grant masks and the deny masks (see below), the range with + // index 0 is at the MSB, giving it the highest priority in the greater-than comparison to + // decide between grant and denial. + assign r_grant_mask[NumRanges-1-i] = addr_hit[i] & read_access & perm_read_access; + assign w_grant_mask[NumRanges-1-i] = addr_hit[i] & write_access & perm_write_access; + assign x_grant_mask[NumRanges-1-i] = addr_hit[i] & execute_access & perm_execute_access; + + // A range denies a request if the request address hits and the type of the access (R/W/X) is + // *not* permitted by that range. + assign r_deny_mask[NumRanges-1-i] = addr_hit[i] & read_access & ~perm_read_access; + assign w_deny_mask[NumRanges-1-i] = addr_hit[i] & write_access & ~perm_write_access; + assign x_deny_mask[NumRanges-1-i] = addr_hit[i] & execute_access & ~perm_execute_access; + + // Use log_enable_mask to mask logging. Note, this mask is not reversed as we use the index + // that caused to the denial to read from that mask and don't use it as a comparison. + assign log_enable_mask[i] = prim_mubi_pkg::mubi4_test_true_strict( + prim_mubi_pkg::mubi4_t'(reg2hw.range_attr[i].log_denied_access.q)); + end + + // The overall grant and deny mask is simply the OR combination of the access-type-specific masks. + assign grant_mask = r_grant_mask | w_grant_mask | x_grant_mask; + assign deny_mask = r_deny_mask | w_deny_mask | x_deny_mask; + + // Based on the deny mask, we compute the leading bit in the mask. The index of the leading + // bit determines the index of the range that denied the request. As `prim_leading_one_ppc` starts + // its search for the "leading" bit at the LSB, `deny_mask` needs to be reversed to compute the + // index. The result is then directly the index of the SW-configured range, due to how + // `grant_mask` and `deny_mask` get built (see above). + logic [NumRanges-1:0] deny_mask_reversed; + assign deny_mask_reversed = {<<{deny_mask}}; + + localparam int unsigned NumRangesWidth = prim_util_pkg::vbits(NumRanges); + logic [NumRangesWidth-1:0] deny_index; + prim_leading_one_ppc #( + .N ( NumRanges ) + ) u_leading_one ( + .in_i ( deny_mask_reversed ), + .leading_one_o ( ), + .ppc_out_o ( ), + .idx_o ( deny_index ) + ); + + // A request gets granted if and only if + // (1) the request is valid and + // (2.1) at least one range matches and among the matching ranges the one with the highest + // priority grants the request or + // (2.2) range checks are bypassed. + logic range_check_grant; + assign range_check_grant = ctn_tl_h2d_i.a_valid & ( + (|addr_hit & (grant_mask > deny_mask)) | + prim_mubi_pkg::mubi8_test_true_strict(range_check_overwrite_i) + ); + + // A request gets denied if and only if it is valid and doesn't get granted. + logic range_check_fail; + assign range_check_fail = ctn_tl_h2d_i.a_valid & ~range_check_grant; + + ////////////////////////////////////////////////////////////////////////////// + // TLUL Loopback for failing accesses + ////////////////////////////////////////////////////////////////////////////// + + tlul_request_loopback #( + .ErrorRsp( RangeCheckErrorRsp ) + ) u_req_loopback ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .squash_req_i ( range_check_fail ), + // Incoming request + .tl_h2d_i ( ctn_tl_h2d_i ), + .tl_d2h_o ( ctn_tl_d2h_o ), + // Outgoing request/rsp if not squashed + .tl_h2d_o ( ctn_filtered_tl_h2d_o ), + .tl_d2h_i ( ctn_filtered_tl_d2h_i ) + ); + + ////////////////////////////////////////////////////////////////////////////// + // Range Check Deny Counting Logic + ////////////////////////////////////////////////////////////////////////////// + + logic [DenyCountWidth-1:0] deny_cnt; + logic deny_cnt_incr; + + // Clear log information when clearing the log manually via the writing of a 1 to the + // log_clear bit. + logic clear_log; + assign clear_log = (reg2hw.log_config.log_clear.qe & reg2hw.log_config.log_clear.q); + + // Always clear the log_clear bit from hardware + assign hw2reg.log_config.log_clear.de = 1'b1; + assign hw2reg.log_config.log_clear.d = 1'b0; + + // Only increment the deny counter if logging is globally enabled and for the particular range, + // we are not clearing the counter in this cycle, and see a failing range check + assign deny_cnt_incr = reg2hw.log_config.log_enable.q & + log_enable_mask[deny_index] & + ~clear_log & + range_check_fail; + // Determine if we are doing the first log. This one is special, since it also needs to log + // diagnostics data + logic log_first_deny; + assign log_first_deny = deny_cnt_incr & (deny_cnt == 0); + + // SEC_CM: CTR.REDUN + prim_count #( + .Width(DenyCountWidth) + ) u_deny_count ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .clr_i ( 1'b0 ), + .set_i ( clear_log ), + .set_cnt_i ( DenyCountWidth'(deny_cnt_incr) ), + .incr_en_i ( deny_cnt_incr ), + .decr_en_i ( 1'b0 ), + .step_i ( DenyCountWidth'(1) ), + .commit_i ( 1'b1 ), + .cnt_o ( deny_cnt ), + .cnt_after_commit_o ( ), + .err_o ( deny_cnt_error ) + ); + + // Log count is transparently mirrored. Clearing happens on the counter. + assign hw2reg.log_status.deny_cnt.de = 1'b1; + assign hw2reg.log_status.deny_cnt.d = deny_cnt; + + assign hw2reg.log_status.denied_read_access.de = log_first_deny | clear_log; + assign hw2reg.log_status.denied_read_access.d = log_first_deny ? read_access : 1'b0; + + assign hw2reg.log_status.denied_write_access.de = log_first_deny | clear_log; + assign hw2reg.log_status.denied_write_access.d = log_first_deny ? write_access : 1'b0; + + assign hw2reg.log_status.denied_execute_access.de = log_first_deny | clear_log; + assign hw2reg.log_status.denied_execute_access.d = log_first_deny ? execute_access : 1'b0; + + // Request is denied because no range was matching at all + assign hw2reg.log_status.denied_no_match.de = log_first_deny | clear_log; + assign hw2reg.log_status.denied_no_match.d = log_first_deny ? ~(|addr_hit) : 1'b0; + + // Log if denied range lacks a valid READ RACL hit + assign hw2reg.log_status.denied_racl_read.de = log_first_deny | clear_log; + assign hw2reg.log_status.denied_racl_read.d = + log_first_deny ? ((read_access | execute_access) & ~racl_read_hit[deny_index]) : '0; + + // Log if denied range lacks a valid WRITE RACL hit + assign hw2reg.log_status.denied_racl_write.de = log_first_deny | clear_log; + assign hw2reg.log_status.denied_racl_write.d = + log_first_deny ? (write_access & ~racl_write_hit[deny_index]) : '0; + + assign hw2reg.log_status.denied_source_role.de = log_first_deny | clear_log; + assign hw2reg.log_status.denied_source_role.d = log_first_deny ? racl_role : '0; + + assign hw2reg.log_status.denied_ctn_uid.de = log_first_deny | clear_log; + assign hw2reg.log_status.denied_ctn_uid.d = + log_first_deny ? top_racl_pkg::tlul_extract_ctn_uid_bits(ctn_tl_h2d_i.a_user.rsvd) + : '0; + + assign hw2reg.log_status.deny_range_index.de = log_first_deny | clear_log; + assign hw2reg.log_status.deny_range_index.d = log_first_deny ? deny_index : 0; + + assign hw2reg.log_address.de = log_first_deny | clear_log; + assign hw2reg.log_address.d = log_first_deny ? ctn_tl_h2d_i.a_address : '0; + + ////////////////////////////////////////////////////////////////////////////// + // Interrupt Notification Logic + ////////////////////////////////////////////////////////////////////////////// + + // Create the IRQ condition when the deny counter is above the configured threshold. + logic deny_cnt_threshold_reached; + assign deny_cnt_threshold_reached = deny_cnt > reg2hw.log_config.deny_cnt_threshold.q; + + prim_intr_hw #( + .Width ( 1 ), + .IntrT ( "Status" ) + ) u_intr_range_check_deny ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .event_intr_i ( deny_cnt_threshold_reached ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.d ), + .intr_o ( intr_deny_cnt_reached_o ) + ); + + ////////////////////////////////////////////////////////////////////////////// + // Unused Signals + ////////////////////////////////////////////////////////////////////////////// + logic unused_signals; + assign unused_signals = ^log_enable_mask; + + ////////////////////////////////////////////////////////////////////////////// + // Assertions + ////////////////////////////////////////////////////////////////////////////// + + // All outputs should have known values after reset + `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o) + `ASSERT_KNOWN(DenyCntIrqKnown_A, intr_deny_cnt_reached_o) + + `ASSERT_KNOWN_IF(TlODKnown_A, tl_o, tl_o.d_valid) + `ASSERT_KNOWN(TlOAReadyKnown_A, tl_o.a_ready) + + `ASSERT_KNOWN_IF(TlCtnODKnown_A, ctn_tl_d2h_o, ctn_tl_d2h_o.d_valid) + `ASSERT_KNOWN(TlCtnOAReadyKnown_A, ctn_tl_d2h_o.a_ready) + `ASSERT_KNOWN_IF(TlCtnFilteredOAKnown_A, ctn_filtered_tl_h2d_o, ctn_filtered_tl_h2d_o.a_valid) + `ASSERT_KNOWN(TlCtnFilteredODReadyKnown_A, ctn_filtered_tl_h2d_o.d_ready) + + `ASSERT_KNOWN_IF(RaclErrorOKnown_A, racl_error_o, racl_error_o.valid) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_ac_range_check_reg, + alert_tx_o[0]) + // Deny Counter error + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(DenyCountCheck_A, u_deny_count, + alert_tx_o[1]) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/rtl/ac_range_check_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/rtl/ac_range_check_reg_pkg.sv new file mode 100644 index 00000000000..84dfeab54eb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/rtl/ac_range_check_reg_pkg.sv @@ -0,0 +1,725 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package ac_range_check_reg_pkg; + + // Param list + parameter int NumRanges = 32; + parameter int DenyCountWidth = 8; + parameter int NumAlerts = 2; + + // Address widths within the block + parameter int BlockAw = 10; + + // Number of registers for every interface + parameter int NumRegs = 168; + + // Alert indices + typedef enum int { + AlertRecovCtrlUpdateErrIdx = 0, + AlertFatalFaultIdx = 1 + } ac_range_check_alert_idx_t; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic q; + } ac_range_check_reg2hw_intr_state_reg_t; + + typedef struct packed { + logic q; + } ac_range_check_reg2hw_intr_enable_reg_t; + + typedef struct packed { + logic q; + logic qe; + } ac_range_check_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } fatal_fault; + struct packed { + logic q; + logic qe; + } recov_ctrl_update_err; + } ac_range_check_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] q; + } deny_cnt_threshold; + struct packed { + logic q; + logic qe; + } log_clear; + struct packed { + logic q; + } log_enable; + } ac_range_check_reg2hw_log_config_reg_t; + + typedef struct packed { + logic [29:0] q; + } ac_range_check_reg2hw_range_base_mreg_t; + + typedef struct packed { + logic [29:0] q; + } ac_range_check_reg2hw_range_limit_mreg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + } log_denied_access; + struct packed { + logic [3:0] q; + } execute_access; + struct packed { + logic [3:0] q; + } write_access; + struct packed { + logic [3:0] q; + } read_access; + struct packed { + logic [3:0] q; + } enable; + } ac_range_check_reg2hw_range_attr_mreg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + } write_perm; + struct packed { + logic [15:0] q; + } read_perm; + } ac_range_check_reg2hw_range_racl_policy_shadowed_mreg_t; + + typedef struct packed { + logic d; + logic de; + } ac_range_check_hw2reg_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } counter_err; + struct packed { + logic d; + logic de; + } reg_intg_err; + struct packed { + logic d; + logic de; + } shadowed_storage_err; + struct packed { + logic d; + logic de; + } shadowed_update_err; + } ac_range_check_hw2reg_alert_status_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } log_clear; + } ac_range_check_hw2reg_log_config_reg_t; + + typedef struct packed { + struct packed { + logic [4:0] d; + logic de; + } deny_range_index; + struct packed { + logic [4:0] d; + logic de; + } denied_ctn_uid; + struct packed { + logic [3:0] d; + logic de; + } denied_source_role; + struct packed { + logic d; + logic de; + } denied_racl_write; + struct packed { + logic d; + logic de; + } denied_racl_read; + struct packed { + logic d; + logic de; + } denied_no_match; + struct packed { + logic d; + logic de; + } denied_execute_access; + struct packed { + logic d; + logic de; + } denied_write_access; + struct packed { + logic d; + logic de; + } denied_read_access; + struct packed { + logic [7:0] d; + logic de; + } deny_cnt; + } ac_range_check_hw2reg_log_status_reg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } ac_range_check_hw2reg_log_address_reg_t; + + // Register -> HW type + typedef struct packed { + ac_range_check_reg2hw_intr_state_reg_t intr_state; // [3602:3602] + ac_range_check_reg2hw_intr_enable_reg_t intr_enable; // [3601:3601] + ac_range_check_reg2hw_intr_test_reg_t intr_test; // [3600:3599] + ac_range_check_reg2hw_alert_test_reg_t alert_test; // [3598:3595] + ac_range_check_reg2hw_log_config_reg_t log_config; // [3594:3584] + ac_range_check_reg2hw_range_base_mreg_t [31:0] range_base; // [3583:2624] + ac_range_check_reg2hw_range_limit_mreg_t [31:0] range_limit; // [2623:1664] + ac_range_check_reg2hw_range_attr_mreg_t [31:0] range_attr; // [1663:1024] + ac_range_check_reg2hw_range_racl_policy_shadowed_mreg_t [31:0] + range_racl_policy_shadowed; // [1023:0] + } ac_range_check_reg2hw_t; + + // HW -> register type + typedef struct packed { + ac_range_check_hw2reg_intr_state_reg_t intr_state; // [82:81] + ac_range_check_hw2reg_alert_status_reg_t alert_status; // [80:73] + ac_range_check_hw2reg_log_config_reg_t log_config; // [72:71] + ac_range_check_hw2reg_log_status_reg_t log_status; // [70:33] + ac_range_check_hw2reg_log_address_reg_t log_address; // [32:0] + } ac_range_check_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_INTR_STATE_OFFSET = 10'h 0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_INTR_ENABLE_OFFSET = 10'h 4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_INTR_TEST_OFFSET = 10'h 8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_ALERT_TEST_OFFSET = 10'h c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_ALERT_STATUS_OFFSET = 10'h 10; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_LOG_CONFIG_OFFSET = 10'h 14; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_LOG_STATUS_OFFSET = 10'h 18; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_LOG_ADDRESS_OFFSET = 10'h 1c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_0_OFFSET = 10'h 20; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_1_OFFSET = 10'h 24; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_2_OFFSET = 10'h 28; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_3_OFFSET = 10'h 2c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_4_OFFSET = 10'h 30; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_5_OFFSET = 10'h 34; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_6_OFFSET = 10'h 38; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_7_OFFSET = 10'h 3c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_8_OFFSET = 10'h 40; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_9_OFFSET = 10'h 44; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_10_OFFSET = 10'h 48; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_11_OFFSET = 10'h 4c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_12_OFFSET = 10'h 50; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_13_OFFSET = 10'h 54; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_14_OFFSET = 10'h 58; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_15_OFFSET = 10'h 5c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_16_OFFSET = 10'h 60; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_17_OFFSET = 10'h 64; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_18_OFFSET = 10'h 68; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_19_OFFSET = 10'h 6c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_20_OFFSET = 10'h 70; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_21_OFFSET = 10'h 74; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_22_OFFSET = 10'h 78; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_23_OFFSET = 10'h 7c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_24_OFFSET = 10'h 80; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_25_OFFSET = 10'h 84; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_26_OFFSET = 10'h 88; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_27_OFFSET = 10'h 8c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_28_OFFSET = 10'h 90; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_29_OFFSET = 10'h 94; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_30_OFFSET = 10'h 98; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_REGWEN_31_OFFSET = 10'h 9c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_0_OFFSET = 10'h a0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_1_OFFSET = 10'h a4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_2_OFFSET = 10'h a8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_3_OFFSET = 10'h ac; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_4_OFFSET = 10'h b0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_5_OFFSET = 10'h b4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_6_OFFSET = 10'h b8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_7_OFFSET = 10'h bc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_8_OFFSET = 10'h c0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_9_OFFSET = 10'h c4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_10_OFFSET = 10'h c8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_11_OFFSET = 10'h cc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_12_OFFSET = 10'h d0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_13_OFFSET = 10'h d4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_14_OFFSET = 10'h d8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_15_OFFSET = 10'h dc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_16_OFFSET = 10'h e0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_17_OFFSET = 10'h e4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_18_OFFSET = 10'h e8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_19_OFFSET = 10'h ec; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_20_OFFSET = 10'h f0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_21_OFFSET = 10'h f4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_22_OFFSET = 10'h f8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_23_OFFSET = 10'h fc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_24_OFFSET = 10'h 100; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_25_OFFSET = 10'h 104; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_26_OFFSET = 10'h 108; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_27_OFFSET = 10'h 10c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_28_OFFSET = 10'h 110; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_29_OFFSET = 10'h 114; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_30_OFFSET = 10'h 118; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_BASE_31_OFFSET = 10'h 11c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_0_OFFSET = 10'h 120; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_1_OFFSET = 10'h 124; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_2_OFFSET = 10'h 128; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_3_OFFSET = 10'h 12c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_4_OFFSET = 10'h 130; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_5_OFFSET = 10'h 134; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_6_OFFSET = 10'h 138; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_7_OFFSET = 10'h 13c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_8_OFFSET = 10'h 140; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_9_OFFSET = 10'h 144; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_10_OFFSET = 10'h 148; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_11_OFFSET = 10'h 14c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_12_OFFSET = 10'h 150; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_13_OFFSET = 10'h 154; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_14_OFFSET = 10'h 158; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_15_OFFSET = 10'h 15c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_16_OFFSET = 10'h 160; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_17_OFFSET = 10'h 164; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_18_OFFSET = 10'h 168; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_19_OFFSET = 10'h 16c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_20_OFFSET = 10'h 170; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_21_OFFSET = 10'h 174; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_22_OFFSET = 10'h 178; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_23_OFFSET = 10'h 17c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_24_OFFSET = 10'h 180; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_25_OFFSET = 10'h 184; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_26_OFFSET = 10'h 188; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_27_OFFSET = 10'h 18c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_28_OFFSET = 10'h 190; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_29_OFFSET = 10'h 194; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_30_OFFSET = 10'h 198; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_LIMIT_31_OFFSET = 10'h 19c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_0_OFFSET = 10'h 1a0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_1_OFFSET = 10'h 1a4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_2_OFFSET = 10'h 1a8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_3_OFFSET = 10'h 1ac; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_4_OFFSET = 10'h 1b0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_5_OFFSET = 10'h 1b4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_6_OFFSET = 10'h 1b8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_7_OFFSET = 10'h 1bc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_8_OFFSET = 10'h 1c0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_9_OFFSET = 10'h 1c4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_10_OFFSET = 10'h 1c8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_11_OFFSET = 10'h 1cc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_12_OFFSET = 10'h 1d0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_13_OFFSET = 10'h 1d4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_14_OFFSET = 10'h 1d8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_15_OFFSET = 10'h 1dc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_16_OFFSET = 10'h 1e0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_17_OFFSET = 10'h 1e4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_18_OFFSET = 10'h 1e8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_19_OFFSET = 10'h 1ec; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_20_OFFSET = 10'h 1f0; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_21_OFFSET = 10'h 1f4; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_22_OFFSET = 10'h 1f8; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_23_OFFSET = 10'h 1fc; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_24_OFFSET = 10'h 200; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_25_OFFSET = 10'h 204; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_26_OFFSET = 10'h 208; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_27_OFFSET = 10'h 20c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_28_OFFSET = 10'h 210; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_29_OFFSET = 10'h 214; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_30_OFFSET = 10'h 218; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_ATTR_31_OFFSET = 10'h 21c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_OFFSET = 10'h 220; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_OFFSET = 10'h 224; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_OFFSET = 10'h 228; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_OFFSET = 10'h 22c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_OFFSET = 10'h 230; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_OFFSET = 10'h 234; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_OFFSET = 10'h 238; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_OFFSET = 10'h 23c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_OFFSET = 10'h 240; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_OFFSET = 10'h 244; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_OFFSET = 10'h 248; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_OFFSET = 10'h 24c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_OFFSET = 10'h 250; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_OFFSET = 10'h 254; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_OFFSET = 10'h 258; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_OFFSET = 10'h 25c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_OFFSET = 10'h 260; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_OFFSET = 10'h 264; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_OFFSET = 10'h 268; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_OFFSET = 10'h 26c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_OFFSET = 10'h 270; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_OFFSET = 10'h 274; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_OFFSET = 10'h 278; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_OFFSET = 10'h 27c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_OFFSET = 10'h 280; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_OFFSET = 10'h 284; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_OFFSET = 10'h 288; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_OFFSET = 10'h 28c; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_OFFSET = 10'h 290; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_OFFSET = 10'h 294; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_OFFSET = 10'h 298; + parameter logic [BlockAw-1:0] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_OFFSET = 10'h 29c; + + // Reset values for hwext registers and their fields + parameter logic [0:0] AC_RANGE_CHECK_INTR_TEST_RESVAL = 1'h 0; + parameter logic [0:0] AC_RANGE_CHECK_INTR_TEST_DENY_CNT_REACHED_RESVAL = 1'h 0; + parameter logic [1:0] AC_RANGE_CHECK_ALERT_TEST_RESVAL = 2'h 0; + parameter logic [0:0] AC_RANGE_CHECK_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_RESVAL = 1'h 0; + parameter logic [0:0] AC_RANGE_CHECK_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + + // Register index + typedef enum int { + AC_RANGE_CHECK_INTR_STATE, + AC_RANGE_CHECK_INTR_ENABLE, + AC_RANGE_CHECK_INTR_TEST, + AC_RANGE_CHECK_ALERT_TEST, + AC_RANGE_CHECK_ALERT_STATUS, + AC_RANGE_CHECK_LOG_CONFIG, + AC_RANGE_CHECK_LOG_STATUS, + AC_RANGE_CHECK_LOG_ADDRESS, + AC_RANGE_CHECK_RANGE_REGWEN_0, + AC_RANGE_CHECK_RANGE_REGWEN_1, + AC_RANGE_CHECK_RANGE_REGWEN_2, + AC_RANGE_CHECK_RANGE_REGWEN_3, + AC_RANGE_CHECK_RANGE_REGWEN_4, + AC_RANGE_CHECK_RANGE_REGWEN_5, + AC_RANGE_CHECK_RANGE_REGWEN_6, + AC_RANGE_CHECK_RANGE_REGWEN_7, + AC_RANGE_CHECK_RANGE_REGWEN_8, + AC_RANGE_CHECK_RANGE_REGWEN_9, + AC_RANGE_CHECK_RANGE_REGWEN_10, + AC_RANGE_CHECK_RANGE_REGWEN_11, + AC_RANGE_CHECK_RANGE_REGWEN_12, + AC_RANGE_CHECK_RANGE_REGWEN_13, + AC_RANGE_CHECK_RANGE_REGWEN_14, + AC_RANGE_CHECK_RANGE_REGWEN_15, + AC_RANGE_CHECK_RANGE_REGWEN_16, + AC_RANGE_CHECK_RANGE_REGWEN_17, + AC_RANGE_CHECK_RANGE_REGWEN_18, + AC_RANGE_CHECK_RANGE_REGWEN_19, + AC_RANGE_CHECK_RANGE_REGWEN_20, + AC_RANGE_CHECK_RANGE_REGWEN_21, + AC_RANGE_CHECK_RANGE_REGWEN_22, + AC_RANGE_CHECK_RANGE_REGWEN_23, + AC_RANGE_CHECK_RANGE_REGWEN_24, + AC_RANGE_CHECK_RANGE_REGWEN_25, + AC_RANGE_CHECK_RANGE_REGWEN_26, + AC_RANGE_CHECK_RANGE_REGWEN_27, + AC_RANGE_CHECK_RANGE_REGWEN_28, + AC_RANGE_CHECK_RANGE_REGWEN_29, + AC_RANGE_CHECK_RANGE_REGWEN_30, + AC_RANGE_CHECK_RANGE_REGWEN_31, + AC_RANGE_CHECK_RANGE_BASE_0, + AC_RANGE_CHECK_RANGE_BASE_1, + AC_RANGE_CHECK_RANGE_BASE_2, + AC_RANGE_CHECK_RANGE_BASE_3, + AC_RANGE_CHECK_RANGE_BASE_4, + AC_RANGE_CHECK_RANGE_BASE_5, + AC_RANGE_CHECK_RANGE_BASE_6, + AC_RANGE_CHECK_RANGE_BASE_7, + AC_RANGE_CHECK_RANGE_BASE_8, + AC_RANGE_CHECK_RANGE_BASE_9, + AC_RANGE_CHECK_RANGE_BASE_10, + AC_RANGE_CHECK_RANGE_BASE_11, + AC_RANGE_CHECK_RANGE_BASE_12, + AC_RANGE_CHECK_RANGE_BASE_13, + AC_RANGE_CHECK_RANGE_BASE_14, + AC_RANGE_CHECK_RANGE_BASE_15, + AC_RANGE_CHECK_RANGE_BASE_16, + AC_RANGE_CHECK_RANGE_BASE_17, + AC_RANGE_CHECK_RANGE_BASE_18, + AC_RANGE_CHECK_RANGE_BASE_19, + AC_RANGE_CHECK_RANGE_BASE_20, + AC_RANGE_CHECK_RANGE_BASE_21, + AC_RANGE_CHECK_RANGE_BASE_22, + AC_RANGE_CHECK_RANGE_BASE_23, + AC_RANGE_CHECK_RANGE_BASE_24, + AC_RANGE_CHECK_RANGE_BASE_25, + AC_RANGE_CHECK_RANGE_BASE_26, + AC_RANGE_CHECK_RANGE_BASE_27, + AC_RANGE_CHECK_RANGE_BASE_28, + AC_RANGE_CHECK_RANGE_BASE_29, + AC_RANGE_CHECK_RANGE_BASE_30, + AC_RANGE_CHECK_RANGE_BASE_31, + AC_RANGE_CHECK_RANGE_LIMIT_0, + AC_RANGE_CHECK_RANGE_LIMIT_1, + AC_RANGE_CHECK_RANGE_LIMIT_2, + AC_RANGE_CHECK_RANGE_LIMIT_3, + AC_RANGE_CHECK_RANGE_LIMIT_4, + AC_RANGE_CHECK_RANGE_LIMIT_5, + AC_RANGE_CHECK_RANGE_LIMIT_6, + AC_RANGE_CHECK_RANGE_LIMIT_7, + AC_RANGE_CHECK_RANGE_LIMIT_8, + AC_RANGE_CHECK_RANGE_LIMIT_9, + AC_RANGE_CHECK_RANGE_LIMIT_10, + AC_RANGE_CHECK_RANGE_LIMIT_11, + AC_RANGE_CHECK_RANGE_LIMIT_12, + AC_RANGE_CHECK_RANGE_LIMIT_13, + AC_RANGE_CHECK_RANGE_LIMIT_14, + AC_RANGE_CHECK_RANGE_LIMIT_15, + AC_RANGE_CHECK_RANGE_LIMIT_16, + AC_RANGE_CHECK_RANGE_LIMIT_17, + AC_RANGE_CHECK_RANGE_LIMIT_18, + AC_RANGE_CHECK_RANGE_LIMIT_19, + AC_RANGE_CHECK_RANGE_LIMIT_20, + AC_RANGE_CHECK_RANGE_LIMIT_21, + AC_RANGE_CHECK_RANGE_LIMIT_22, + AC_RANGE_CHECK_RANGE_LIMIT_23, + AC_RANGE_CHECK_RANGE_LIMIT_24, + AC_RANGE_CHECK_RANGE_LIMIT_25, + AC_RANGE_CHECK_RANGE_LIMIT_26, + AC_RANGE_CHECK_RANGE_LIMIT_27, + AC_RANGE_CHECK_RANGE_LIMIT_28, + AC_RANGE_CHECK_RANGE_LIMIT_29, + AC_RANGE_CHECK_RANGE_LIMIT_30, + AC_RANGE_CHECK_RANGE_LIMIT_31, + AC_RANGE_CHECK_RANGE_ATTR_0, + AC_RANGE_CHECK_RANGE_ATTR_1, + AC_RANGE_CHECK_RANGE_ATTR_2, + AC_RANGE_CHECK_RANGE_ATTR_3, + AC_RANGE_CHECK_RANGE_ATTR_4, + AC_RANGE_CHECK_RANGE_ATTR_5, + AC_RANGE_CHECK_RANGE_ATTR_6, + AC_RANGE_CHECK_RANGE_ATTR_7, + AC_RANGE_CHECK_RANGE_ATTR_8, + AC_RANGE_CHECK_RANGE_ATTR_9, + AC_RANGE_CHECK_RANGE_ATTR_10, + AC_RANGE_CHECK_RANGE_ATTR_11, + AC_RANGE_CHECK_RANGE_ATTR_12, + AC_RANGE_CHECK_RANGE_ATTR_13, + AC_RANGE_CHECK_RANGE_ATTR_14, + AC_RANGE_CHECK_RANGE_ATTR_15, + AC_RANGE_CHECK_RANGE_ATTR_16, + AC_RANGE_CHECK_RANGE_ATTR_17, + AC_RANGE_CHECK_RANGE_ATTR_18, + AC_RANGE_CHECK_RANGE_ATTR_19, + AC_RANGE_CHECK_RANGE_ATTR_20, + AC_RANGE_CHECK_RANGE_ATTR_21, + AC_RANGE_CHECK_RANGE_ATTR_22, + AC_RANGE_CHECK_RANGE_ATTR_23, + AC_RANGE_CHECK_RANGE_ATTR_24, + AC_RANGE_CHECK_RANGE_ATTR_25, + AC_RANGE_CHECK_RANGE_ATTR_26, + AC_RANGE_CHECK_RANGE_ATTR_27, + AC_RANGE_CHECK_RANGE_ATTR_28, + AC_RANGE_CHECK_RANGE_ATTR_29, + AC_RANGE_CHECK_RANGE_ATTR_30, + AC_RANGE_CHECK_RANGE_ATTR_31, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30, + AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31 + } ac_range_check_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] AC_RANGE_CHECK_PERMIT [168] = '{ + 4'b 0001, // index[ 0] AC_RANGE_CHECK_INTR_STATE + 4'b 0001, // index[ 1] AC_RANGE_CHECK_INTR_ENABLE + 4'b 0001, // index[ 2] AC_RANGE_CHECK_INTR_TEST + 4'b 0001, // index[ 3] AC_RANGE_CHECK_ALERT_TEST + 4'b 0001, // index[ 4] AC_RANGE_CHECK_ALERT_STATUS + 4'b 0011, // index[ 5] AC_RANGE_CHECK_LOG_CONFIG + 4'b 1111, // index[ 6] AC_RANGE_CHECK_LOG_STATUS + 4'b 1111, // index[ 7] AC_RANGE_CHECK_LOG_ADDRESS + 4'b 0001, // index[ 8] AC_RANGE_CHECK_RANGE_REGWEN_0 + 4'b 0001, // index[ 9] AC_RANGE_CHECK_RANGE_REGWEN_1 + 4'b 0001, // index[ 10] AC_RANGE_CHECK_RANGE_REGWEN_2 + 4'b 0001, // index[ 11] AC_RANGE_CHECK_RANGE_REGWEN_3 + 4'b 0001, // index[ 12] AC_RANGE_CHECK_RANGE_REGWEN_4 + 4'b 0001, // index[ 13] AC_RANGE_CHECK_RANGE_REGWEN_5 + 4'b 0001, // index[ 14] AC_RANGE_CHECK_RANGE_REGWEN_6 + 4'b 0001, // index[ 15] AC_RANGE_CHECK_RANGE_REGWEN_7 + 4'b 0001, // index[ 16] AC_RANGE_CHECK_RANGE_REGWEN_8 + 4'b 0001, // index[ 17] AC_RANGE_CHECK_RANGE_REGWEN_9 + 4'b 0001, // index[ 18] AC_RANGE_CHECK_RANGE_REGWEN_10 + 4'b 0001, // index[ 19] AC_RANGE_CHECK_RANGE_REGWEN_11 + 4'b 0001, // index[ 20] AC_RANGE_CHECK_RANGE_REGWEN_12 + 4'b 0001, // index[ 21] AC_RANGE_CHECK_RANGE_REGWEN_13 + 4'b 0001, // index[ 22] AC_RANGE_CHECK_RANGE_REGWEN_14 + 4'b 0001, // index[ 23] AC_RANGE_CHECK_RANGE_REGWEN_15 + 4'b 0001, // index[ 24] AC_RANGE_CHECK_RANGE_REGWEN_16 + 4'b 0001, // index[ 25] AC_RANGE_CHECK_RANGE_REGWEN_17 + 4'b 0001, // index[ 26] AC_RANGE_CHECK_RANGE_REGWEN_18 + 4'b 0001, // index[ 27] AC_RANGE_CHECK_RANGE_REGWEN_19 + 4'b 0001, // index[ 28] AC_RANGE_CHECK_RANGE_REGWEN_20 + 4'b 0001, // index[ 29] AC_RANGE_CHECK_RANGE_REGWEN_21 + 4'b 0001, // index[ 30] AC_RANGE_CHECK_RANGE_REGWEN_22 + 4'b 0001, // index[ 31] AC_RANGE_CHECK_RANGE_REGWEN_23 + 4'b 0001, // index[ 32] AC_RANGE_CHECK_RANGE_REGWEN_24 + 4'b 0001, // index[ 33] AC_RANGE_CHECK_RANGE_REGWEN_25 + 4'b 0001, // index[ 34] AC_RANGE_CHECK_RANGE_REGWEN_26 + 4'b 0001, // index[ 35] AC_RANGE_CHECK_RANGE_REGWEN_27 + 4'b 0001, // index[ 36] AC_RANGE_CHECK_RANGE_REGWEN_28 + 4'b 0001, // index[ 37] AC_RANGE_CHECK_RANGE_REGWEN_29 + 4'b 0001, // index[ 38] AC_RANGE_CHECK_RANGE_REGWEN_30 + 4'b 0001, // index[ 39] AC_RANGE_CHECK_RANGE_REGWEN_31 + 4'b 1111, // index[ 40] AC_RANGE_CHECK_RANGE_BASE_0 + 4'b 1111, // index[ 41] AC_RANGE_CHECK_RANGE_BASE_1 + 4'b 1111, // index[ 42] AC_RANGE_CHECK_RANGE_BASE_2 + 4'b 1111, // index[ 43] AC_RANGE_CHECK_RANGE_BASE_3 + 4'b 1111, // index[ 44] AC_RANGE_CHECK_RANGE_BASE_4 + 4'b 1111, // index[ 45] AC_RANGE_CHECK_RANGE_BASE_5 + 4'b 1111, // index[ 46] AC_RANGE_CHECK_RANGE_BASE_6 + 4'b 1111, // index[ 47] AC_RANGE_CHECK_RANGE_BASE_7 + 4'b 1111, // index[ 48] AC_RANGE_CHECK_RANGE_BASE_8 + 4'b 1111, // index[ 49] AC_RANGE_CHECK_RANGE_BASE_9 + 4'b 1111, // index[ 50] AC_RANGE_CHECK_RANGE_BASE_10 + 4'b 1111, // index[ 51] AC_RANGE_CHECK_RANGE_BASE_11 + 4'b 1111, // index[ 52] AC_RANGE_CHECK_RANGE_BASE_12 + 4'b 1111, // index[ 53] AC_RANGE_CHECK_RANGE_BASE_13 + 4'b 1111, // index[ 54] AC_RANGE_CHECK_RANGE_BASE_14 + 4'b 1111, // index[ 55] AC_RANGE_CHECK_RANGE_BASE_15 + 4'b 1111, // index[ 56] AC_RANGE_CHECK_RANGE_BASE_16 + 4'b 1111, // index[ 57] AC_RANGE_CHECK_RANGE_BASE_17 + 4'b 1111, // index[ 58] AC_RANGE_CHECK_RANGE_BASE_18 + 4'b 1111, // index[ 59] AC_RANGE_CHECK_RANGE_BASE_19 + 4'b 1111, // index[ 60] AC_RANGE_CHECK_RANGE_BASE_20 + 4'b 1111, // index[ 61] AC_RANGE_CHECK_RANGE_BASE_21 + 4'b 1111, // index[ 62] AC_RANGE_CHECK_RANGE_BASE_22 + 4'b 1111, // index[ 63] AC_RANGE_CHECK_RANGE_BASE_23 + 4'b 1111, // index[ 64] AC_RANGE_CHECK_RANGE_BASE_24 + 4'b 1111, // index[ 65] AC_RANGE_CHECK_RANGE_BASE_25 + 4'b 1111, // index[ 66] AC_RANGE_CHECK_RANGE_BASE_26 + 4'b 1111, // index[ 67] AC_RANGE_CHECK_RANGE_BASE_27 + 4'b 1111, // index[ 68] AC_RANGE_CHECK_RANGE_BASE_28 + 4'b 1111, // index[ 69] AC_RANGE_CHECK_RANGE_BASE_29 + 4'b 1111, // index[ 70] AC_RANGE_CHECK_RANGE_BASE_30 + 4'b 1111, // index[ 71] AC_RANGE_CHECK_RANGE_BASE_31 + 4'b 1111, // index[ 72] AC_RANGE_CHECK_RANGE_LIMIT_0 + 4'b 1111, // index[ 73] AC_RANGE_CHECK_RANGE_LIMIT_1 + 4'b 1111, // index[ 74] AC_RANGE_CHECK_RANGE_LIMIT_2 + 4'b 1111, // index[ 75] AC_RANGE_CHECK_RANGE_LIMIT_3 + 4'b 1111, // index[ 76] AC_RANGE_CHECK_RANGE_LIMIT_4 + 4'b 1111, // index[ 77] AC_RANGE_CHECK_RANGE_LIMIT_5 + 4'b 1111, // index[ 78] AC_RANGE_CHECK_RANGE_LIMIT_6 + 4'b 1111, // index[ 79] AC_RANGE_CHECK_RANGE_LIMIT_7 + 4'b 1111, // index[ 80] AC_RANGE_CHECK_RANGE_LIMIT_8 + 4'b 1111, // index[ 81] AC_RANGE_CHECK_RANGE_LIMIT_9 + 4'b 1111, // index[ 82] AC_RANGE_CHECK_RANGE_LIMIT_10 + 4'b 1111, // index[ 83] AC_RANGE_CHECK_RANGE_LIMIT_11 + 4'b 1111, // index[ 84] AC_RANGE_CHECK_RANGE_LIMIT_12 + 4'b 1111, // index[ 85] AC_RANGE_CHECK_RANGE_LIMIT_13 + 4'b 1111, // index[ 86] AC_RANGE_CHECK_RANGE_LIMIT_14 + 4'b 1111, // index[ 87] AC_RANGE_CHECK_RANGE_LIMIT_15 + 4'b 1111, // index[ 88] AC_RANGE_CHECK_RANGE_LIMIT_16 + 4'b 1111, // index[ 89] AC_RANGE_CHECK_RANGE_LIMIT_17 + 4'b 1111, // index[ 90] AC_RANGE_CHECK_RANGE_LIMIT_18 + 4'b 1111, // index[ 91] AC_RANGE_CHECK_RANGE_LIMIT_19 + 4'b 1111, // index[ 92] AC_RANGE_CHECK_RANGE_LIMIT_20 + 4'b 1111, // index[ 93] AC_RANGE_CHECK_RANGE_LIMIT_21 + 4'b 1111, // index[ 94] AC_RANGE_CHECK_RANGE_LIMIT_22 + 4'b 1111, // index[ 95] AC_RANGE_CHECK_RANGE_LIMIT_23 + 4'b 1111, // index[ 96] AC_RANGE_CHECK_RANGE_LIMIT_24 + 4'b 1111, // index[ 97] AC_RANGE_CHECK_RANGE_LIMIT_25 + 4'b 1111, // index[ 98] AC_RANGE_CHECK_RANGE_LIMIT_26 + 4'b 1111, // index[ 99] AC_RANGE_CHECK_RANGE_LIMIT_27 + 4'b 1111, // index[100] AC_RANGE_CHECK_RANGE_LIMIT_28 + 4'b 1111, // index[101] AC_RANGE_CHECK_RANGE_LIMIT_29 + 4'b 1111, // index[102] AC_RANGE_CHECK_RANGE_LIMIT_30 + 4'b 1111, // index[103] AC_RANGE_CHECK_RANGE_LIMIT_31 + 4'b 0111, // index[104] AC_RANGE_CHECK_RANGE_ATTR_0 + 4'b 0111, // index[105] AC_RANGE_CHECK_RANGE_ATTR_1 + 4'b 0111, // index[106] AC_RANGE_CHECK_RANGE_ATTR_2 + 4'b 0111, // index[107] AC_RANGE_CHECK_RANGE_ATTR_3 + 4'b 0111, // index[108] AC_RANGE_CHECK_RANGE_ATTR_4 + 4'b 0111, // index[109] AC_RANGE_CHECK_RANGE_ATTR_5 + 4'b 0111, // index[110] AC_RANGE_CHECK_RANGE_ATTR_6 + 4'b 0111, // index[111] AC_RANGE_CHECK_RANGE_ATTR_7 + 4'b 0111, // index[112] AC_RANGE_CHECK_RANGE_ATTR_8 + 4'b 0111, // index[113] AC_RANGE_CHECK_RANGE_ATTR_9 + 4'b 0111, // index[114] AC_RANGE_CHECK_RANGE_ATTR_10 + 4'b 0111, // index[115] AC_RANGE_CHECK_RANGE_ATTR_11 + 4'b 0111, // index[116] AC_RANGE_CHECK_RANGE_ATTR_12 + 4'b 0111, // index[117] AC_RANGE_CHECK_RANGE_ATTR_13 + 4'b 0111, // index[118] AC_RANGE_CHECK_RANGE_ATTR_14 + 4'b 0111, // index[119] AC_RANGE_CHECK_RANGE_ATTR_15 + 4'b 0111, // index[120] AC_RANGE_CHECK_RANGE_ATTR_16 + 4'b 0111, // index[121] AC_RANGE_CHECK_RANGE_ATTR_17 + 4'b 0111, // index[122] AC_RANGE_CHECK_RANGE_ATTR_18 + 4'b 0111, // index[123] AC_RANGE_CHECK_RANGE_ATTR_19 + 4'b 0111, // index[124] AC_RANGE_CHECK_RANGE_ATTR_20 + 4'b 0111, // index[125] AC_RANGE_CHECK_RANGE_ATTR_21 + 4'b 0111, // index[126] AC_RANGE_CHECK_RANGE_ATTR_22 + 4'b 0111, // index[127] AC_RANGE_CHECK_RANGE_ATTR_23 + 4'b 0111, // index[128] AC_RANGE_CHECK_RANGE_ATTR_24 + 4'b 0111, // index[129] AC_RANGE_CHECK_RANGE_ATTR_25 + 4'b 0111, // index[130] AC_RANGE_CHECK_RANGE_ATTR_26 + 4'b 0111, // index[131] AC_RANGE_CHECK_RANGE_ATTR_27 + 4'b 0111, // index[132] AC_RANGE_CHECK_RANGE_ATTR_28 + 4'b 0111, // index[133] AC_RANGE_CHECK_RANGE_ATTR_29 + 4'b 0111, // index[134] AC_RANGE_CHECK_RANGE_ATTR_30 + 4'b 0111, // index[135] AC_RANGE_CHECK_RANGE_ATTR_31 + 4'b 1111, // index[136] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0 + 4'b 1111, // index[137] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1 + 4'b 1111, // index[138] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2 + 4'b 1111, // index[139] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3 + 4'b 1111, // index[140] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4 + 4'b 1111, // index[141] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5 + 4'b 1111, // index[142] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6 + 4'b 1111, // index[143] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7 + 4'b 1111, // index[144] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8 + 4'b 1111, // index[145] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9 + 4'b 1111, // index[146] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10 + 4'b 1111, // index[147] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11 + 4'b 1111, // index[148] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12 + 4'b 1111, // index[149] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13 + 4'b 1111, // index[150] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14 + 4'b 1111, // index[151] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15 + 4'b 1111, // index[152] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16 + 4'b 1111, // index[153] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17 + 4'b 1111, // index[154] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18 + 4'b 1111, // index[155] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19 + 4'b 1111, // index[156] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20 + 4'b 1111, // index[157] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21 + 4'b 1111, // index[158] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22 + 4'b 1111, // index[159] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23 + 4'b 1111, // index[160] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24 + 4'b 1111, // index[161] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25 + 4'b 1111, // index[162] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26 + 4'b 1111, // index[163] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27 + 4'b 1111, // index[164] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28 + 4'b 1111, // index[165] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29 + 4'b 1111, // index[166] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30 + 4'b 1111 // index[167] AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31 + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/rtl/ac_range_check_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/rtl/ac_range_check_reg_top.sv new file mode 100644 index 00000000000..15216076ea2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/ac_range_check/rtl/ac_range_check_reg_top.sv @@ -0,0 +1,14458 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module ac_range_check_reg_top + # ( + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[ac_range_check_reg_pkg::NumRegs] = + '{ac_range_check_reg_pkg::NumRegs{0}} + ) ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output ac_range_check_reg_pkg::ac_range_check_reg2hw_t reg2hw, // Write + input ac_range_check_reg_pkg::ac_range_check_hw2reg_t hw2reg, // Read + + output logic shadowed_storage_err_o, + output logic shadowed_update_err_o, + + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output top_racl_pkg::racl_error_log_t racl_error_o, + + // Integrity check errors + output logic intg_err_o +); + + import ac_range_check_reg_pkg::* ; + + localparam int AW = 10; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [167:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(168) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + // Translate RACL error to TLUL error if enabled + .error_i (reg_error | (RaclErrorRsp & racl_error_o.valid)) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_qs; + logic intr_enable_we; + logic intr_enable_qs; + logic intr_enable_wd; + logic intr_test_we; + logic intr_test_wd; + logic alert_test_we; + logic alert_test_recov_ctrl_update_err_wd; + logic alert_test_fatal_fault_wd; + logic alert_status_re; + logic alert_status_shadowed_update_err_qs; + logic alert_status_shadowed_update_err_wd; + logic alert_status_shadowed_storage_err_qs; + logic alert_status_reg_intg_err_qs; + logic alert_status_counter_err_qs; + logic log_config_we; + logic log_config_log_enable_qs; + logic log_config_log_enable_wd; + logic log_config_log_clear_wd; + logic [7:0] log_config_deny_cnt_threshold_qs; + logic [7:0] log_config_deny_cnt_threshold_wd; + logic [7:0] log_status_deny_cnt_qs; + logic log_status_denied_read_access_qs; + logic log_status_denied_write_access_qs; + logic log_status_denied_execute_access_qs; + logic log_status_denied_no_match_qs; + logic log_status_denied_racl_read_qs; + logic log_status_denied_racl_write_qs; + logic [3:0] log_status_denied_source_role_qs; + logic [4:0] log_status_denied_ctn_uid_qs; + logic [4:0] log_status_deny_range_index_qs; + logic [31:0] log_address_qs; + logic range_regwen_0_we; + logic [3:0] range_regwen_0_qs; + logic [3:0] range_regwen_0_wd; + logic range_regwen_1_we; + logic [3:0] range_regwen_1_qs; + logic [3:0] range_regwen_1_wd; + logic range_regwen_2_we; + logic [3:0] range_regwen_2_qs; + logic [3:0] range_regwen_2_wd; + logic range_regwen_3_we; + logic [3:0] range_regwen_3_qs; + logic [3:0] range_regwen_3_wd; + logic range_regwen_4_we; + logic [3:0] range_regwen_4_qs; + logic [3:0] range_regwen_4_wd; + logic range_regwen_5_we; + logic [3:0] range_regwen_5_qs; + logic [3:0] range_regwen_5_wd; + logic range_regwen_6_we; + logic [3:0] range_regwen_6_qs; + logic [3:0] range_regwen_6_wd; + logic range_regwen_7_we; + logic [3:0] range_regwen_7_qs; + logic [3:0] range_regwen_7_wd; + logic range_regwen_8_we; + logic [3:0] range_regwen_8_qs; + logic [3:0] range_regwen_8_wd; + logic range_regwen_9_we; + logic [3:0] range_regwen_9_qs; + logic [3:0] range_regwen_9_wd; + logic range_regwen_10_we; + logic [3:0] range_regwen_10_qs; + logic [3:0] range_regwen_10_wd; + logic range_regwen_11_we; + logic [3:0] range_regwen_11_qs; + logic [3:0] range_regwen_11_wd; + logic range_regwen_12_we; + logic [3:0] range_regwen_12_qs; + logic [3:0] range_regwen_12_wd; + logic range_regwen_13_we; + logic [3:0] range_regwen_13_qs; + logic [3:0] range_regwen_13_wd; + logic range_regwen_14_we; + logic [3:0] range_regwen_14_qs; + logic [3:0] range_regwen_14_wd; + logic range_regwen_15_we; + logic [3:0] range_regwen_15_qs; + logic [3:0] range_regwen_15_wd; + logic range_regwen_16_we; + logic [3:0] range_regwen_16_qs; + logic [3:0] range_regwen_16_wd; + logic range_regwen_17_we; + logic [3:0] range_regwen_17_qs; + logic [3:0] range_regwen_17_wd; + logic range_regwen_18_we; + logic [3:0] range_regwen_18_qs; + logic [3:0] range_regwen_18_wd; + logic range_regwen_19_we; + logic [3:0] range_regwen_19_qs; + logic [3:0] range_regwen_19_wd; + logic range_regwen_20_we; + logic [3:0] range_regwen_20_qs; + logic [3:0] range_regwen_20_wd; + logic range_regwen_21_we; + logic [3:0] range_regwen_21_qs; + logic [3:0] range_regwen_21_wd; + logic range_regwen_22_we; + logic [3:0] range_regwen_22_qs; + logic [3:0] range_regwen_22_wd; + logic range_regwen_23_we; + logic [3:0] range_regwen_23_qs; + logic [3:0] range_regwen_23_wd; + logic range_regwen_24_we; + logic [3:0] range_regwen_24_qs; + logic [3:0] range_regwen_24_wd; + logic range_regwen_25_we; + logic [3:0] range_regwen_25_qs; + logic [3:0] range_regwen_25_wd; + logic range_regwen_26_we; + logic [3:0] range_regwen_26_qs; + logic [3:0] range_regwen_26_wd; + logic range_regwen_27_we; + logic [3:0] range_regwen_27_qs; + logic [3:0] range_regwen_27_wd; + logic range_regwen_28_we; + logic [3:0] range_regwen_28_qs; + logic [3:0] range_regwen_28_wd; + logic range_regwen_29_we; + logic [3:0] range_regwen_29_qs; + logic [3:0] range_regwen_29_wd; + logic range_regwen_30_we; + logic [3:0] range_regwen_30_qs; + logic [3:0] range_regwen_30_wd; + logic range_regwen_31_we; + logic [3:0] range_regwen_31_qs; + logic [3:0] range_regwen_31_wd; + logic range_base_0_we; + logic [29:0] range_base_0_qs; + logic [29:0] range_base_0_wd; + logic range_base_1_we; + logic [29:0] range_base_1_qs; + logic [29:0] range_base_1_wd; + logic range_base_2_we; + logic [29:0] range_base_2_qs; + logic [29:0] range_base_2_wd; + logic range_base_3_we; + logic [29:0] range_base_3_qs; + logic [29:0] range_base_3_wd; + logic range_base_4_we; + logic [29:0] range_base_4_qs; + logic [29:0] range_base_4_wd; + logic range_base_5_we; + logic [29:0] range_base_5_qs; + logic [29:0] range_base_5_wd; + logic range_base_6_we; + logic [29:0] range_base_6_qs; + logic [29:0] range_base_6_wd; + logic range_base_7_we; + logic [29:0] range_base_7_qs; + logic [29:0] range_base_7_wd; + logic range_base_8_we; + logic [29:0] range_base_8_qs; + logic [29:0] range_base_8_wd; + logic range_base_9_we; + logic [29:0] range_base_9_qs; + logic [29:0] range_base_9_wd; + logic range_base_10_we; + logic [29:0] range_base_10_qs; + logic [29:0] range_base_10_wd; + logic range_base_11_we; + logic [29:0] range_base_11_qs; + logic [29:0] range_base_11_wd; + logic range_base_12_we; + logic [29:0] range_base_12_qs; + logic [29:0] range_base_12_wd; + logic range_base_13_we; + logic [29:0] range_base_13_qs; + logic [29:0] range_base_13_wd; + logic range_base_14_we; + logic [29:0] range_base_14_qs; + logic [29:0] range_base_14_wd; + logic range_base_15_we; + logic [29:0] range_base_15_qs; + logic [29:0] range_base_15_wd; + logic range_base_16_we; + logic [29:0] range_base_16_qs; + logic [29:0] range_base_16_wd; + logic range_base_17_we; + logic [29:0] range_base_17_qs; + logic [29:0] range_base_17_wd; + logic range_base_18_we; + logic [29:0] range_base_18_qs; + logic [29:0] range_base_18_wd; + logic range_base_19_we; + logic [29:0] range_base_19_qs; + logic [29:0] range_base_19_wd; + logic range_base_20_we; + logic [29:0] range_base_20_qs; + logic [29:0] range_base_20_wd; + logic range_base_21_we; + logic [29:0] range_base_21_qs; + logic [29:0] range_base_21_wd; + logic range_base_22_we; + logic [29:0] range_base_22_qs; + logic [29:0] range_base_22_wd; + logic range_base_23_we; + logic [29:0] range_base_23_qs; + logic [29:0] range_base_23_wd; + logic range_base_24_we; + logic [29:0] range_base_24_qs; + logic [29:0] range_base_24_wd; + logic range_base_25_we; + logic [29:0] range_base_25_qs; + logic [29:0] range_base_25_wd; + logic range_base_26_we; + logic [29:0] range_base_26_qs; + logic [29:0] range_base_26_wd; + logic range_base_27_we; + logic [29:0] range_base_27_qs; + logic [29:0] range_base_27_wd; + logic range_base_28_we; + logic [29:0] range_base_28_qs; + logic [29:0] range_base_28_wd; + logic range_base_29_we; + logic [29:0] range_base_29_qs; + logic [29:0] range_base_29_wd; + logic range_base_30_we; + logic [29:0] range_base_30_qs; + logic [29:0] range_base_30_wd; + logic range_base_31_we; + logic [29:0] range_base_31_qs; + logic [29:0] range_base_31_wd; + logic range_limit_0_we; + logic [29:0] range_limit_0_qs; + logic [29:0] range_limit_0_wd; + logic range_limit_1_we; + logic [29:0] range_limit_1_qs; + logic [29:0] range_limit_1_wd; + logic range_limit_2_we; + logic [29:0] range_limit_2_qs; + logic [29:0] range_limit_2_wd; + logic range_limit_3_we; + logic [29:0] range_limit_3_qs; + logic [29:0] range_limit_3_wd; + logic range_limit_4_we; + logic [29:0] range_limit_4_qs; + logic [29:0] range_limit_4_wd; + logic range_limit_5_we; + logic [29:0] range_limit_5_qs; + logic [29:0] range_limit_5_wd; + logic range_limit_6_we; + logic [29:0] range_limit_6_qs; + logic [29:0] range_limit_6_wd; + logic range_limit_7_we; + logic [29:0] range_limit_7_qs; + logic [29:0] range_limit_7_wd; + logic range_limit_8_we; + logic [29:0] range_limit_8_qs; + logic [29:0] range_limit_8_wd; + logic range_limit_9_we; + logic [29:0] range_limit_9_qs; + logic [29:0] range_limit_9_wd; + logic range_limit_10_we; + logic [29:0] range_limit_10_qs; + logic [29:0] range_limit_10_wd; + logic range_limit_11_we; + logic [29:0] range_limit_11_qs; + logic [29:0] range_limit_11_wd; + logic range_limit_12_we; + logic [29:0] range_limit_12_qs; + logic [29:0] range_limit_12_wd; + logic range_limit_13_we; + logic [29:0] range_limit_13_qs; + logic [29:0] range_limit_13_wd; + logic range_limit_14_we; + logic [29:0] range_limit_14_qs; + logic [29:0] range_limit_14_wd; + logic range_limit_15_we; + logic [29:0] range_limit_15_qs; + logic [29:0] range_limit_15_wd; + logic range_limit_16_we; + logic [29:0] range_limit_16_qs; + logic [29:0] range_limit_16_wd; + logic range_limit_17_we; + logic [29:0] range_limit_17_qs; + logic [29:0] range_limit_17_wd; + logic range_limit_18_we; + logic [29:0] range_limit_18_qs; + logic [29:0] range_limit_18_wd; + logic range_limit_19_we; + logic [29:0] range_limit_19_qs; + logic [29:0] range_limit_19_wd; + logic range_limit_20_we; + logic [29:0] range_limit_20_qs; + logic [29:0] range_limit_20_wd; + logic range_limit_21_we; + logic [29:0] range_limit_21_qs; + logic [29:0] range_limit_21_wd; + logic range_limit_22_we; + logic [29:0] range_limit_22_qs; + logic [29:0] range_limit_22_wd; + logic range_limit_23_we; + logic [29:0] range_limit_23_qs; + logic [29:0] range_limit_23_wd; + logic range_limit_24_we; + logic [29:0] range_limit_24_qs; + logic [29:0] range_limit_24_wd; + logic range_limit_25_we; + logic [29:0] range_limit_25_qs; + logic [29:0] range_limit_25_wd; + logic range_limit_26_we; + logic [29:0] range_limit_26_qs; + logic [29:0] range_limit_26_wd; + logic range_limit_27_we; + logic [29:0] range_limit_27_qs; + logic [29:0] range_limit_27_wd; + logic range_limit_28_we; + logic [29:0] range_limit_28_qs; + logic [29:0] range_limit_28_wd; + logic range_limit_29_we; + logic [29:0] range_limit_29_qs; + logic [29:0] range_limit_29_wd; + logic range_limit_30_we; + logic [29:0] range_limit_30_qs; + logic [29:0] range_limit_30_wd; + logic range_limit_31_we; + logic [29:0] range_limit_31_qs; + logic [29:0] range_limit_31_wd; + logic range_attr_0_we; + logic [3:0] range_attr_0_enable_0_qs; + logic [3:0] range_attr_0_enable_0_wd; + logic [3:0] range_attr_0_read_access_0_qs; + logic [3:0] range_attr_0_read_access_0_wd; + logic [3:0] range_attr_0_write_access_0_qs; + logic [3:0] range_attr_0_write_access_0_wd; + logic [3:0] range_attr_0_execute_access_0_qs; + logic [3:0] range_attr_0_execute_access_0_wd; + logic [3:0] range_attr_0_log_denied_access_0_qs; + logic [3:0] range_attr_0_log_denied_access_0_wd; + logic range_attr_1_we; + logic [3:0] range_attr_1_enable_1_qs; + logic [3:0] range_attr_1_enable_1_wd; + logic [3:0] range_attr_1_read_access_1_qs; + logic [3:0] range_attr_1_read_access_1_wd; + logic [3:0] range_attr_1_write_access_1_qs; + logic [3:0] range_attr_1_write_access_1_wd; + logic [3:0] range_attr_1_execute_access_1_qs; + logic [3:0] range_attr_1_execute_access_1_wd; + logic [3:0] range_attr_1_log_denied_access_1_qs; + logic [3:0] range_attr_1_log_denied_access_1_wd; + logic range_attr_2_we; + logic [3:0] range_attr_2_enable_2_qs; + logic [3:0] range_attr_2_enable_2_wd; + logic [3:0] range_attr_2_read_access_2_qs; + logic [3:0] range_attr_2_read_access_2_wd; + logic [3:0] range_attr_2_write_access_2_qs; + logic [3:0] range_attr_2_write_access_2_wd; + logic [3:0] range_attr_2_execute_access_2_qs; + logic [3:0] range_attr_2_execute_access_2_wd; + logic [3:0] range_attr_2_log_denied_access_2_qs; + logic [3:0] range_attr_2_log_denied_access_2_wd; + logic range_attr_3_we; + logic [3:0] range_attr_3_enable_3_qs; + logic [3:0] range_attr_3_enable_3_wd; + logic [3:0] range_attr_3_read_access_3_qs; + logic [3:0] range_attr_3_read_access_3_wd; + logic [3:0] range_attr_3_write_access_3_qs; + logic [3:0] range_attr_3_write_access_3_wd; + logic [3:0] range_attr_3_execute_access_3_qs; + logic [3:0] range_attr_3_execute_access_3_wd; + logic [3:0] range_attr_3_log_denied_access_3_qs; + logic [3:0] range_attr_3_log_denied_access_3_wd; + logic range_attr_4_we; + logic [3:0] range_attr_4_enable_4_qs; + logic [3:0] range_attr_4_enable_4_wd; + logic [3:0] range_attr_4_read_access_4_qs; + logic [3:0] range_attr_4_read_access_4_wd; + logic [3:0] range_attr_4_write_access_4_qs; + logic [3:0] range_attr_4_write_access_4_wd; + logic [3:0] range_attr_4_execute_access_4_qs; + logic [3:0] range_attr_4_execute_access_4_wd; + logic [3:0] range_attr_4_log_denied_access_4_qs; + logic [3:0] range_attr_4_log_denied_access_4_wd; + logic range_attr_5_we; + logic [3:0] range_attr_5_enable_5_qs; + logic [3:0] range_attr_5_enable_5_wd; + logic [3:0] range_attr_5_read_access_5_qs; + logic [3:0] range_attr_5_read_access_5_wd; + logic [3:0] range_attr_5_write_access_5_qs; + logic [3:0] range_attr_5_write_access_5_wd; + logic [3:0] range_attr_5_execute_access_5_qs; + logic [3:0] range_attr_5_execute_access_5_wd; + logic [3:0] range_attr_5_log_denied_access_5_qs; + logic [3:0] range_attr_5_log_denied_access_5_wd; + logic range_attr_6_we; + logic [3:0] range_attr_6_enable_6_qs; + logic [3:0] range_attr_6_enable_6_wd; + logic [3:0] range_attr_6_read_access_6_qs; + logic [3:0] range_attr_6_read_access_6_wd; + logic [3:0] range_attr_6_write_access_6_qs; + logic [3:0] range_attr_6_write_access_6_wd; + logic [3:0] range_attr_6_execute_access_6_qs; + logic [3:0] range_attr_6_execute_access_6_wd; + logic [3:0] range_attr_6_log_denied_access_6_qs; + logic [3:0] range_attr_6_log_denied_access_6_wd; + logic range_attr_7_we; + logic [3:0] range_attr_7_enable_7_qs; + logic [3:0] range_attr_7_enable_7_wd; + logic [3:0] range_attr_7_read_access_7_qs; + logic [3:0] range_attr_7_read_access_7_wd; + logic [3:0] range_attr_7_write_access_7_qs; + logic [3:0] range_attr_7_write_access_7_wd; + logic [3:0] range_attr_7_execute_access_7_qs; + logic [3:0] range_attr_7_execute_access_7_wd; + logic [3:0] range_attr_7_log_denied_access_7_qs; + logic [3:0] range_attr_7_log_denied_access_7_wd; + logic range_attr_8_we; + logic [3:0] range_attr_8_enable_8_qs; + logic [3:0] range_attr_8_enable_8_wd; + logic [3:0] range_attr_8_read_access_8_qs; + logic [3:0] range_attr_8_read_access_8_wd; + logic [3:0] range_attr_8_write_access_8_qs; + logic [3:0] range_attr_8_write_access_8_wd; + logic [3:0] range_attr_8_execute_access_8_qs; + logic [3:0] range_attr_8_execute_access_8_wd; + logic [3:0] range_attr_8_log_denied_access_8_qs; + logic [3:0] range_attr_8_log_denied_access_8_wd; + logic range_attr_9_we; + logic [3:0] range_attr_9_enable_9_qs; + logic [3:0] range_attr_9_enable_9_wd; + logic [3:0] range_attr_9_read_access_9_qs; + logic [3:0] range_attr_9_read_access_9_wd; + logic [3:0] range_attr_9_write_access_9_qs; + logic [3:0] range_attr_9_write_access_9_wd; + logic [3:0] range_attr_9_execute_access_9_qs; + logic [3:0] range_attr_9_execute_access_9_wd; + logic [3:0] range_attr_9_log_denied_access_9_qs; + logic [3:0] range_attr_9_log_denied_access_9_wd; + logic range_attr_10_we; + logic [3:0] range_attr_10_enable_10_qs; + logic [3:0] range_attr_10_enable_10_wd; + logic [3:0] range_attr_10_read_access_10_qs; + logic [3:0] range_attr_10_read_access_10_wd; + logic [3:0] range_attr_10_write_access_10_qs; + logic [3:0] range_attr_10_write_access_10_wd; + logic [3:0] range_attr_10_execute_access_10_qs; + logic [3:0] range_attr_10_execute_access_10_wd; + logic [3:0] range_attr_10_log_denied_access_10_qs; + logic [3:0] range_attr_10_log_denied_access_10_wd; + logic range_attr_11_we; + logic [3:0] range_attr_11_enable_11_qs; + logic [3:0] range_attr_11_enable_11_wd; + logic [3:0] range_attr_11_read_access_11_qs; + logic [3:0] range_attr_11_read_access_11_wd; + logic [3:0] range_attr_11_write_access_11_qs; + logic [3:0] range_attr_11_write_access_11_wd; + logic [3:0] range_attr_11_execute_access_11_qs; + logic [3:0] range_attr_11_execute_access_11_wd; + logic [3:0] range_attr_11_log_denied_access_11_qs; + logic [3:0] range_attr_11_log_denied_access_11_wd; + logic range_attr_12_we; + logic [3:0] range_attr_12_enable_12_qs; + logic [3:0] range_attr_12_enable_12_wd; + logic [3:0] range_attr_12_read_access_12_qs; + logic [3:0] range_attr_12_read_access_12_wd; + logic [3:0] range_attr_12_write_access_12_qs; + logic [3:0] range_attr_12_write_access_12_wd; + logic [3:0] range_attr_12_execute_access_12_qs; + logic [3:0] range_attr_12_execute_access_12_wd; + logic [3:0] range_attr_12_log_denied_access_12_qs; + logic [3:0] range_attr_12_log_denied_access_12_wd; + logic range_attr_13_we; + logic [3:0] range_attr_13_enable_13_qs; + logic [3:0] range_attr_13_enable_13_wd; + logic [3:0] range_attr_13_read_access_13_qs; + logic [3:0] range_attr_13_read_access_13_wd; + logic [3:0] range_attr_13_write_access_13_qs; + logic [3:0] range_attr_13_write_access_13_wd; + logic [3:0] range_attr_13_execute_access_13_qs; + logic [3:0] range_attr_13_execute_access_13_wd; + logic [3:0] range_attr_13_log_denied_access_13_qs; + logic [3:0] range_attr_13_log_denied_access_13_wd; + logic range_attr_14_we; + logic [3:0] range_attr_14_enable_14_qs; + logic [3:0] range_attr_14_enable_14_wd; + logic [3:0] range_attr_14_read_access_14_qs; + logic [3:0] range_attr_14_read_access_14_wd; + logic [3:0] range_attr_14_write_access_14_qs; + logic [3:0] range_attr_14_write_access_14_wd; + logic [3:0] range_attr_14_execute_access_14_qs; + logic [3:0] range_attr_14_execute_access_14_wd; + logic [3:0] range_attr_14_log_denied_access_14_qs; + logic [3:0] range_attr_14_log_denied_access_14_wd; + logic range_attr_15_we; + logic [3:0] range_attr_15_enable_15_qs; + logic [3:0] range_attr_15_enable_15_wd; + logic [3:0] range_attr_15_read_access_15_qs; + logic [3:0] range_attr_15_read_access_15_wd; + logic [3:0] range_attr_15_write_access_15_qs; + logic [3:0] range_attr_15_write_access_15_wd; + logic [3:0] range_attr_15_execute_access_15_qs; + logic [3:0] range_attr_15_execute_access_15_wd; + logic [3:0] range_attr_15_log_denied_access_15_qs; + logic [3:0] range_attr_15_log_denied_access_15_wd; + logic range_attr_16_we; + logic [3:0] range_attr_16_enable_16_qs; + logic [3:0] range_attr_16_enable_16_wd; + logic [3:0] range_attr_16_read_access_16_qs; + logic [3:0] range_attr_16_read_access_16_wd; + logic [3:0] range_attr_16_write_access_16_qs; + logic [3:0] range_attr_16_write_access_16_wd; + logic [3:0] range_attr_16_execute_access_16_qs; + logic [3:0] range_attr_16_execute_access_16_wd; + logic [3:0] range_attr_16_log_denied_access_16_qs; + logic [3:0] range_attr_16_log_denied_access_16_wd; + logic range_attr_17_we; + logic [3:0] range_attr_17_enable_17_qs; + logic [3:0] range_attr_17_enable_17_wd; + logic [3:0] range_attr_17_read_access_17_qs; + logic [3:0] range_attr_17_read_access_17_wd; + logic [3:0] range_attr_17_write_access_17_qs; + logic [3:0] range_attr_17_write_access_17_wd; + logic [3:0] range_attr_17_execute_access_17_qs; + logic [3:0] range_attr_17_execute_access_17_wd; + logic [3:0] range_attr_17_log_denied_access_17_qs; + logic [3:0] range_attr_17_log_denied_access_17_wd; + logic range_attr_18_we; + logic [3:0] range_attr_18_enable_18_qs; + logic [3:0] range_attr_18_enable_18_wd; + logic [3:0] range_attr_18_read_access_18_qs; + logic [3:0] range_attr_18_read_access_18_wd; + logic [3:0] range_attr_18_write_access_18_qs; + logic [3:0] range_attr_18_write_access_18_wd; + logic [3:0] range_attr_18_execute_access_18_qs; + logic [3:0] range_attr_18_execute_access_18_wd; + logic [3:0] range_attr_18_log_denied_access_18_qs; + logic [3:0] range_attr_18_log_denied_access_18_wd; + logic range_attr_19_we; + logic [3:0] range_attr_19_enable_19_qs; + logic [3:0] range_attr_19_enable_19_wd; + logic [3:0] range_attr_19_read_access_19_qs; + logic [3:0] range_attr_19_read_access_19_wd; + logic [3:0] range_attr_19_write_access_19_qs; + logic [3:0] range_attr_19_write_access_19_wd; + logic [3:0] range_attr_19_execute_access_19_qs; + logic [3:0] range_attr_19_execute_access_19_wd; + logic [3:0] range_attr_19_log_denied_access_19_qs; + logic [3:0] range_attr_19_log_denied_access_19_wd; + logic range_attr_20_we; + logic [3:0] range_attr_20_enable_20_qs; + logic [3:0] range_attr_20_enable_20_wd; + logic [3:0] range_attr_20_read_access_20_qs; + logic [3:0] range_attr_20_read_access_20_wd; + logic [3:0] range_attr_20_write_access_20_qs; + logic [3:0] range_attr_20_write_access_20_wd; + logic [3:0] range_attr_20_execute_access_20_qs; + logic [3:0] range_attr_20_execute_access_20_wd; + logic [3:0] range_attr_20_log_denied_access_20_qs; + logic [3:0] range_attr_20_log_denied_access_20_wd; + logic range_attr_21_we; + logic [3:0] range_attr_21_enable_21_qs; + logic [3:0] range_attr_21_enable_21_wd; + logic [3:0] range_attr_21_read_access_21_qs; + logic [3:0] range_attr_21_read_access_21_wd; + logic [3:0] range_attr_21_write_access_21_qs; + logic [3:0] range_attr_21_write_access_21_wd; + logic [3:0] range_attr_21_execute_access_21_qs; + logic [3:0] range_attr_21_execute_access_21_wd; + logic [3:0] range_attr_21_log_denied_access_21_qs; + logic [3:0] range_attr_21_log_denied_access_21_wd; + logic range_attr_22_we; + logic [3:0] range_attr_22_enable_22_qs; + logic [3:0] range_attr_22_enable_22_wd; + logic [3:0] range_attr_22_read_access_22_qs; + logic [3:0] range_attr_22_read_access_22_wd; + logic [3:0] range_attr_22_write_access_22_qs; + logic [3:0] range_attr_22_write_access_22_wd; + logic [3:0] range_attr_22_execute_access_22_qs; + logic [3:0] range_attr_22_execute_access_22_wd; + logic [3:0] range_attr_22_log_denied_access_22_qs; + logic [3:0] range_attr_22_log_denied_access_22_wd; + logic range_attr_23_we; + logic [3:0] range_attr_23_enable_23_qs; + logic [3:0] range_attr_23_enable_23_wd; + logic [3:0] range_attr_23_read_access_23_qs; + logic [3:0] range_attr_23_read_access_23_wd; + logic [3:0] range_attr_23_write_access_23_qs; + logic [3:0] range_attr_23_write_access_23_wd; + logic [3:0] range_attr_23_execute_access_23_qs; + logic [3:0] range_attr_23_execute_access_23_wd; + logic [3:0] range_attr_23_log_denied_access_23_qs; + logic [3:0] range_attr_23_log_denied_access_23_wd; + logic range_attr_24_we; + logic [3:0] range_attr_24_enable_24_qs; + logic [3:0] range_attr_24_enable_24_wd; + logic [3:0] range_attr_24_read_access_24_qs; + logic [3:0] range_attr_24_read_access_24_wd; + logic [3:0] range_attr_24_write_access_24_qs; + logic [3:0] range_attr_24_write_access_24_wd; + logic [3:0] range_attr_24_execute_access_24_qs; + logic [3:0] range_attr_24_execute_access_24_wd; + logic [3:0] range_attr_24_log_denied_access_24_qs; + logic [3:0] range_attr_24_log_denied_access_24_wd; + logic range_attr_25_we; + logic [3:0] range_attr_25_enable_25_qs; + logic [3:0] range_attr_25_enable_25_wd; + logic [3:0] range_attr_25_read_access_25_qs; + logic [3:0] range_attr_25_read_access_25_wd; + logic [3:0] range_attr_25_write_access_25_qs; + logic [3:0] range_attr_25_write_access_25_wd; + logic [3:0] range_attr_25_execute_access_25_qs; + logic [3:0] range_attr_25_execute_access_25_wd; + logic [3:0] range_attr_25_log_denied_access_25_qs; + logic [3:0] range_attr_25_log_denied_access_25_wd; + logic range_attr_26_we; + logic [3:0] range_attr_26_enable_26_qs; + logic [3:0] range_attr_26_enable_26_wd; + logic [3:0] range_attr_26_read_access_26_qs; + logic [3:0] range_attr_26_read_access_26_wd; + logic [3:0] range_attr_26_write_access_26_qs; + logic [3:0] range_attr_26_write_access_26_wd; + logic [3:0] range_attr_26_execute_access_26_qs; + logic [3:0] range_attr_26_execute_access_26_wd; + logic [3:0] range_attr_26_log_denied_access_26_qs; + logic [3:0] range_attr_26_log_denied_access_26_wd; + logic range_attr_27_we; + logic [3:0] range_attr_27_enable_27_qs; + logic [3:0] range_attr_27_enable_27_wd; + logic [3:0] range_attr_27_read_access_27_qs; + logic [3:0] range_attr_27_read_access_27_wd; + logic [3:0] range_attr_27_write_access_27_qs; + logic [3:0] range_attr_27_write_access_27_wd; + logic [3:0] range_attr_27_execute_access_27_qs; + logic [3:0] range_attr_27_execute_access_27_wd; + logic [3:0] range_attr_27_log_denied_access_27_qs; + logic [3:0] range_attr_27_log_denied_access_27_wd; + logic range_attr_28_we; + logic [3:0] range_attr_28_enable_28_qs; + logic [3:0] range_attr_28_enable_28_wd; + logic [3:0] range_attr_28_read_access_28_qs; + logic [3:0] range_attr_28_read_access_28_wd; + logic [3:0] range_attr_28_write_access_28_qs; + logic [3:0] range_attr_28_write_access_28_wd; + logic [3:0] range_attr_28_execute_access_28_qs; + logic [3:0] range_attr_28_execute_access_28_wd; + logic [3:0] range_attr_28_log_denied_access_28_qs; + logic [3:0] range_attr_28_log_denied_access_28_wd; + logic range_attr_29_we; + logic [3:0] range_attr_29_enable_29_qs; + logic [3:0] range_attr_29_enable_29_wd; + logic [3:0] range_attr_29_read_access_29_qs; + logic [3:0] range_attr_29_read_access_29_wd; + logic [3:0] range_attr_29_write_access_29_qs; + logic [3:0] range_attr_29_write_access_29_wd; + logic [3:0] range_attr_29_execute_access_29_qs; + logic [3:0] range_attr_29_execute_access_29_wd; + logic [3:0] range_attr_29_log_denied_access_29_qs; + logic [3:0] range_attr_29_log_denied_access_29_wd; + logic range_attr_30_we; + logic [3:0] range_attr_30_enable_30_qs; + logic [3:0] range_attr_30_enable_30_wd; + logic [3:0] range_attr_30_read_access_30_qs; + logic [3:0] range_attr_30_read_access_30_wd; + logic [3:0] range_attr_30_write_access_30_qs; + logic [3:0] range_attr_30_write_access_30_wd; + logic [3:0] range_attr_30_execute_access_30_qs; + logic [3:0] range_attr_30_execute_access_30_wd; + logic [3:0] range_attr_30_log_denied_access_30_qs; + logic [3:0] range_attr_30_log_denied_access_30_wd; + logic range_attr_31_we; + logic [3:0] range_attr_31_enable_31_qs; + logic [3:0] range_attr_31_enable_31_wd; + logic [3:0] range_attr_31_read_access_31_qs; + logic [3:0] range_attr_31_read_access_31_wd; + logic [3:0] range_attr_31_write_access_31_qs; + logic [3:0] range_attr_31_write_access_31_wd; + logic [3:0] range_attr_31_execute_access_31_qs; + logic [3:0] range_attr_31_execute_access_31_wd; + logic [3:0] range_attr_31_log_denied_access_31_qs; + logic [3:0] range_attr_31_log_denied_access_31_wd; + logic range_racl_policy_shadowed_0_re; + logic range_racl_policy_shadowed_0_we; + logic [15:0] range_racl_policy_shadowed_0_read_perm_0_qs; + logic [15:0] range_racl_policy_shadowed_0_read_perm_0_wd; + logic range_racl_policy_shadowed_0_read_perm_0_storage_err; + logic range_racl_policy_shadowed_0_read_perm_0_update_err; + logic [15:0] range_racl_policy_shadowed_0_write_perm_0_qs; + logic [15:0] range_racl_policy_shadowed_0_write_perm_0_wd; + logic range_racl_policy_shadowed_0_write_perm_0_storage_err; + logic range_racl_policy_shadowed_0_write_perm_0_update_err; + logic range_racl_policy_shadowed_1_re; + logic range_racl_policy_shadowed_1_we; + logic [15:0] range_racl_policy_shadowed_1_read_perm_1_qs; + logic [15:0] range_racl_policy_shadowed_1_read_perm_1_wd; + logic range_racl_policy_shadowed_1_read_perm_1_storage_err; + logic range_racl_policy_shadowed_1_read_perm_1_update_err; + logic [15:0] range_racl_policy_shadowed_1_write_perm_1_qs; + logic [15:0] range_racl_policy_shadowed_1_write_perm_1_wd; + logic range_racl_policy_shadowed_1_write_perm_1_storage_err; + logic range_racl_policy_shadowed_1_write_perm_1_update_err; + logic range_racl_policy_shadowed_2_re; + logic range_racl_policy_shadowed_2_we; + logic [15:0] range_racl_policy_shadowed_2_read_perm_2_qs; + logic [15:0] range_racl_policy_shadowed_2_read_perm_2_wd; + logic range_racl_policy_shadowed_2_read_perm_2_storage_err; + logic range_racl_policy_shadowed_2_read_perm_2_update_err; + logic [15:0] range_racl_policy_shadowed_2_write_perm_2_qs; + logic [15:0] range_racl_policy_shadowed_2_write_perm_2_wd; + logic range_racl_policy_shadowed_2_write_perm_2_storage_err; + logic range_racl_policy_shadowed_2_write_perm_2_update_err; + logic range_racl_policy_shadowed_3_re; + logic range_racl_policy_shadowed_3_we; + logic [15:0] range_racl_policy_shadowed_3_read_perm_3_qs; + logic [15:0] range_racl_policy_shadowed_3_read_perm_3_wd; + logic range_racl_policy_shadowed_3_read_perm_3_storage_err; + logic range_racl_policy_shadowed_3_read_perm_3_update_err; + logic [15:0] range_racl_policy_shadowed_3_write_perm_3_qs; + logic [15:0] range_racl_policy_shadowed_3_write_perm_3_wd; + logic range_racl_policy_shadowed_3_write_perm_3_storage_err; + logic range_racl_policy_shadowed_3_write_perm_3_update_err; + logic range_racl_policy_shadowed_4_re; + logic range_racl_policy_shadowed_4_we; + logic [15:0] range_racl_policy_shadowed_4_read_perm_4_qs; + logic [15:0] range_racl_policy_shadowed_4_read_perm_4_wd; + logic range_racl_policy_shadowed_4_read_perm_4_storage_err; + logic range_racl_policy_shadowed_4_read_perm_4_update_err; + logic [15:0] range_racl_policy_shadowed_4_write_perm_4_qs; + logic [15:0] range_racl_policy_shadowed_4_write_perm_4_wd; + logic range_racl_policy_shadowed_4_write_perm_4_storage_err; + logic range_racl_policy_shadowed_4_write_perm_4_update_err; + logic range_racl_policy_shadowed_5_re; + logic range_racl_policy_shadowed_5_we; + logic [15:0] range_racl_policy_shadowed_5_read_perm_5_qs; + logic [15:0] range_racl_policy_shadowed_5_read_perm_5_wd; + logic range_racl_policy_shadowed_5_read_perm_5_storage_err; + logic range_racl_policy_shadowed_5_read_perm_5_update_err; + logic [15:0] range_racl_policy_shadowed_5_write_perm_5_qs; + logic [15:0] range_racl_policy_shadowed_5_write_perm_5_wd; + logic range_racl_policy_shadowed_5_write_perm_5_storage_err; + logic range_racl_policy_shadowed_5_write_perm_5_update_err; + logic range_racl_policy_shadowed_6_re; + logic range_racl_policy_shadowed_6_we; + logic [15:0] range_racl_policy_shadowed_6_read_perm_6_qs; + logic [15:0] range_racl_policy_shadowed_6_read_perm_6_wd; + logic range_racl_policy_shadowed_6_read_perm_6_storage_err; + logic range_racl_policy_shadowed_6_read_perm_6_update_err; + logic [15:0] range_racl_policy_shadowed_6_write_perm_6_qs; + logic [15:0] range_racl_policy_shadowed_6_write_perm_6_wd; + logic range_racl_policy_shadowed_6_write_perm_6_storage_err; + logic range_racl_policy_shadowed_6_write_perm_6_update_err; + logic range_racl_policy_shadowed_7_re; + logic range_racl_policy_shadowed_7_we; + logic [15:0] range_racl_policy_shadowed_7_read_perm_7_qs; + logic [15:0] range_racl_policy_shadowed_7_read_perm_7_wd; + logic range_racl_policy_shadowed_7_read_perm_7_storage_err; + logic range_racl_policy_shadowed_7_read_perm_7_update_err; + logic [15:0] range_racl_policy_shadowed_7_write_perm_7_qs; + logic [15:0] range_racl_policy_shadowed_7_write_perm_7_wd; + logic range_racl_policy_shadowed_7_write_perm_7_storage_err; + logic range_racl_policy_shadowed_7_write_perm_7_update_err; + logic range_racl_policy_shadowed_8_re; + logic range_racl_policy_shadowed_8_we; + logic [15:0] range_racl_policy_shadowed_8_read_perm_8_qs; + logic [15:0] range_racl_policy_shadowed_8_read_perm_8_wd; + logic range_racl_policy_shadowed_8_read_perm_8_storage_err; + logic range_racl_policy_shadowed_8_read_perm_8_update_err; + logic [15:0] range_racl_policy_shadowed_8_write_perm_8_qs; + logic [15:0] range_racl_policy_shadowed_8_write_perm_8_wd; + logic range_racl_policy_shadowed_8_write_perm_8_storage_err; + logic range_racl_policy_shadowed_8_write_perm_8_update_err; + logic range_racl_policy_shadowed_9_re; + logic range_racl_policy_shadowed_9_we; + logic [15:0] range_racl_policy_shadowed_9_read_perm_9_qs; + logic [15:0] range_racl_policy_shadowed_9_read_perm_9_wd; + logic range_racl_policy_shadowed_9_read_perm_9_storage_err; + logic range_racl_policy_shadowed_9_read_perm_9_update_err; + logic [15:0] range_racl_policy_shadowed_9_write_perm_9_qs; + logic [15:0] range_racl_policy_shadowed_9_write_perm_9_wd; + logic range_racl_policy_shadowed_9_write_perm_9_storage_err; + logic range_racl_policy_shadowed_9_write_perm_9_update_err; + logic range_racl_policy_shadowed_10_re; + logic range_racl_policy_shadowed_10_we; + logic [15:0] range_racl_policy_shadowed_10_read_perm_10_qs; + logic [15:0] range_racl_policy_shadowed_10_read_perm_10_wd; + logic range_racl_policy_shadowed_10_read_perm_10_storage_err; + logic range_racl_policy_shadowed_10_read_perm_10_update_err; + logic [15:0] range_racl_policy_shadowed_10_write_perm_10_qs; + logic [15:0] range_racl_policy_shadowed_10_write_perm_10_wd; + logic range_racl_policy_shadowed_10_write_perm_10_storage_err; + logic range_racl_policy_shadowed_10_write_perm_10_update_err; + logic range_racl_policy_shadowed_11_re; + logic range_racl_policy_shadowed_11_we; + logic [15:0] range_racl_policy_shadowed_11_read_perm_11_qs; + logic [15:0] range_racl_policy_shadowed_11_read_perm_11_wd; + logic range_racl_policy_shadowed_11_read_perm_11_storage_err; + logic range_racl_policy_shadowed_11_read_perm_11_update_err; + logic [15:0] range_racl_policy_shadowed_11_write_perm_11_qs; + logic [15:0] range_racl_policy_shadowed_11_write_perm_11_wd; + logic range_racl_policy_shadowed_11_write_perm_11_storage_err; + logic range_racl_policy_shadowed_11_write_perm_11_update_err; + logic range_racl_policy_shadowed_12_re; + logic range_racl_policy_shadowed_12_we; + logic [15:0] range_racl_policy_shadowed_12_read_perm_12_qs; + logic [15:0] range_racl_policy_shadowed_12_read_perm_12_wd; + logic range_racl_policy_shadowed_12_read_perm_12_storage_err; + logic range_racl_policy_shadowed_12_read_perm_12_update_err; + logic [15:0] range_racl_policy_shadowed_12_write_perm_12_qs; + logic [15:0] range_racl_policy_shadowed_12_write_perm_12_wd; + logic range_racl_policy_shadowed_12_write_perm_12_storage_err; + logic range_racl_policy_shadowed_12_write_perm_12_update_err; + logic range_racl_policy_shadowed_13_re; + logic range_racl_policy_shadowed_13_we; + logic [15:0] range_racl_policy_shadowed_13_read_perm_13_qs; + logic [15:0] range_racl_policy_shadowed_13_read_perm_13_wd; + logic range_racl_policy_shadowed_13_read_perm_13_storage_err; + logic range_racl_policy_shadowed_13_read_perm_13_update_err; + logic [15:0] range_racl_policy_shadowed_13_write_perm_13_qs; + logic [15:0] range_racl_policy_shadowed_13_write_perm_13_wd; + logic range_racl_policy_shadowed_13_write_perm_13_storage_err; + logic range_racl_policy_shadowed_13_write_perm_13_update_err; + logic range_racl_policy_shadowed_14_re; + logic range_racl_policy_shadowed_14_we; + logic [15:0] range_racl_policy_shadowed_14_read_perm_14_qs; + logic [15:0] range_racl_policy_shadowed_14_read_perm_14_wd; + logic range_racl_policy_shadowed_14_read_perm_14_storage_err; + logic range_racl_policy_shadowed_14_read_perm_14_update_err; + logic [15:0] range_racl_policy_shadowed_14_write_perm_14_qs; + logic [15:0] range_racl_policy_shadowed_14_write_perm_14_wd; + logic range_racl_policy_shadowed_14_write_perm_14_storage_err; + logic range_racl_policy_shadowed_14_write_perm_14_update_err; + logic range_racl_policy_shadowed_15_re; + logic range_racl_policy_shadowed_15_we; + logic [15:0] range_racl_policy_shadowed_15_read_perm_15_qs; + logic [15:0] range_racl_policy_shadowed_15_read_perm_15_wd; + logic range_racl_policy_shadowed_15_read_perm_15_storage_err; + logic range_racl_policy_shadowed_15_read_perm_15_update_err; + logic [15:0] range_racl_policy_shadowed_15_write_perm_15_qs; + logic [15:0] range_racl_policy_shadowed_15_write_perm_15_wd; + logic range_racl_policy_shadowed_15_write_perm_15_storage_err; + logic range_racl_policy_shadowed_15_write_perm_15_update_err; + logic range_racl_policy_shadowed_16_re; + logic range_racl_policy_shadowed_16_we; + logic [15:0] range_racl_policy_shadowed_16_read_perm_16_qs; + logic [15:0] range_racl_policy_shadowed_16_read_perm_16_wd; + logic range_racl_policy_shadowed_16_read_perm_16_storage_err; + logic range_racl_policy_shadowed_16_read_perm_16_update_err; + logic [15:0] range_racl_policy_shadowed_16_write_perm_16_qs; + logic [15:0] range_racl_policy_shadowed_16_write_perm_16_wd; + logic range_racl_policy_shadowed_16_write_perm_16_storage_err; + logic range_racl_policy_shadowed_16_write_perm_16_update_err; + logic range_racl_policy_shadowed_17_re; + logic range_racl_policy_shadowed_17_we; + logic [15:0] range_racl_policy_shadowed_17_read_perm_17_qs; + logic [15:0] range_racl_policy_shadowed_17_read_perm_17_wd; + logic range_racl_policy_shadowed_17_read_perm_17_storage_err; + logic range_racl_policy_shadowed_17_read_perm_17_update_err; + logic [15:0] range_racl_policy_shadowed_17_write_perm_17_qs; + logic [15:0] range_racl_policy_shadowed_17_write_perm_17_wd; + logic range_racl_policy_shadowed_17_write_perm_17_storage_err; + logic range_racl_policy_shadowed_17_write_perm_17_update_err; + logic range_racl_policy_shadowed_18_re; + logic range_racl_policy_shadowed_18_we; + logic [15:0] range_racl_policy_shadowed_18_read_perm_18_qs; + logic [15:0] range_racl_policy_shadowed_18_read_perm_18_wd; + logic range_racl_policy_shadowed_18_read_perm_18_storage_err; + logic range_racl_policy_shadowed_18_read_perm_18_update_err; + logic [15:0] range_racl_policy_shadowed_18_write_perm_18_qs; + logic [15:0] range_racl_policy_shadowed_18_write_perm_18_wd; + logic range_racl_policy_shadowed_18_write_perm_18_storage_err; + logic range_racl_policy_shadowed_18_write_perm_18_update_err; + logic range_racl_policy_shadowed_19_re; + logic range_racl_policy_shadowed_19_we; + logic [15:0] range_racl_policy_shadowed_19_read_perm_19_qs; + logic [15:0] range_racl_policy_shadowed_19_read_perm_19_wd; + logic range_racl_policy_shadowed_19_read_perm_19_storage_err; + logic range_racl_policy_shadowed_19_read_perm_19_update_err; + logic [15:0] range_racl_policy_shadowed_19_write_perm_19_qs; + logic [15:0] range_racl_policy_shadowed_19_write_perm_19_wd; + logic range_racl_policy_shadowed_19_write_perm_19_storage_err; + logic range_racl_policy_shadowed_19_write_perm_19_update_err; + logic range_racl_policy_shadowed_20_re; + logic range_racl_policy_shadowed_20_we; + logic [15:0] range_racl_policy_shadowed_20_read_perm_20_qs; + logic [15:0] range_racl_policy_shadowed_20_read_perm_20_wd; + logic range_racl_policy_shadowed_20_read_perm_20_storage_err; + logic range_racl_policy_shadowed_20_read_perm_20_update_err; + logic [15:0] range_racl_policy_shadowed_20_write_perm_20_qs; + logic [15:0] range_racl_policy_shadowed_20_write_perm_20_wd; + logic range_racl_policy_shadowed_20_write_perm_20_storage_err; + logic range_racl_policy_shadowed_20_write_perm_20_update_err; + logic range_racl_policy_shadowed_21_re; + logic range_racl_policy_shadowed_21_we; + logic [15:0] range_racl_policy_shadowed_21_read_perm_21_qs; + logic [15:0] range_racl_policy_shadowed_21_read_perm_21_wd; + logic range_racl_policy_shadowed_21_read_perm_21_storage_err; + logic range_racl_policy_shadowed_21_read_perm_21_update_err; + logic [15:0] range_racl_policy_shadowed_21_write_perm_21_qs; + logic [15:0] range_racl_policy_shadowed_21_write_perm_21_wd; + logic range_racl_policy_shadowed_21_write_perm_21_storage_err; + logic range_racl_policy_shadowed_21_write_perm_21_update_err; + logic range_racl_policy_shadowed_22_re; + logic range_racl_policy_shadowed_22_we; + logic [15:0] range_racl_policy_shadowed_22_read_perm_22_qs; + logic [15:0] range_racl_policy_shadowed_22_read_perm_22_wd; + logic range_racl_policy_shadowed_22_read_perm_22_storage_err; + logic range_racl_policy_shadowed_22_read_perm_22_update_err; + logic [15:0] range_racl_policy_shadowed_22_write_perm_22_qs; + logic [15:0] range_racl_policy_shadowed_22_write_perm_22_wd; + logic range_racl_policy_shadowed_22_write_perm_22_storage_err; + logic range_racl_policy_shadowed_22_write_perm_22_update_err; + logic range_racl_policy_shadowed_23_re; + logic range_racl_policy_shadowed_23_we; + logic [15:0] range_racl_policy_shadowed_23_read_perm_23_qs; + logic [15:0] range_racl_policy_shadowed_23_read_perm_23_wd; + logic range_racl_policy_shadowed_23_read_perm_23_storage_err; + logic range_racl_policy_shadowed_23_read_perm_23_update_err; + logic [15:0] range_racl_policy_shadowed_23_write_perm_23_qs; + logic [15:0] range_racl_policy_shadowed_23_write_perm_23_wd; + logic range_racl_policy_shadowed_23_write_perm_23_storage_err; + logic range_racl_policy_shadowed_23_write_perm_23_update_err; + logic range_racl_policy_shadowed_24_re; + logic range_racl_policy_shadowed_24_we; + logic [15:0] range_racl_policy_shadowed_24_read_perm_24_qs; + logic [15:0] range_racl_policy_shadowed_24_read_perm_24_wd; + logic range_racl_policy_shadowed_24_read_perm_24_storage_err; + logic range_racl_policy_shadowed_24_read_perm_24_update_err; + logic [15:0] range_racl_policy_shadowed_24_write_perm_24_qs; + logic [15:0] range_racl_policy_shadowed_24_write_perm_24_wd; + logic range_racl_policy_shadowed_24_write_perm_24_storage_err; + logic range_racl_policy_shadowed_24_write_perm_24_update_err; + logic range_racl_policy_shadowed_25_re; + logic range_racl_policy_shadowed_25_we; + logic [15:0] range_racl_policy_shadowed_25_read_perm_25_qs; + logic [15:0] range_racl_policy_shadowed_25_read_perm_25_wd; + logic range_racl_policy_shadowed_25_read_perm_25_storage_err; + logic range_racl_policy_shadowed_25_read_perm_25_update_err; + logic [15:0] range_racl_policy_shadowed_25_write_perm_25_qs; + logic [15:0] range_racl_policy_shadowed_25_write_perm_25_wd; + logic range_racl_policy_shadowed_25_write_perm_25_storage_err; + logic range_racl_policy_shadowed_25_write_perm_25_update_err; + logic range_racl_policy_shadowed_26_re; + logic range_racl_policy_shadowed_26_we; + logic [15:0] range_racl_policy_shadowed_26_read_perm_26_qs; + logic [15:0] range_racl_policy_shadowed_26_read_perm_26_wd; + logic range_racl_policy_shadowed_26_read_perm_26_storage_err; + logic range_racl_policy_shadowed_26_read_perm_26_update_err; + logic [15:0] range_racl_policy_shadowed_26_write_perm_26_qs; + logic [15:0] range_racl_policy_shadowed_26_write_perm_26_wd; + logic range_racl_policy_shadowed_26_write_perm_26_storage_err; + logic range_racl_policy_shadowed_26_write_perm_26_update_err; + logic range_racl_policy_shadowed_27_re; + logic range_racl_policy_shadowed_27_we; + logic [15:0] range_racl_policy_shadowed_27_read_perm_27_qs; + logic [15:0] range_racl_policy_shadowed_27_read_perm_27_wd; + logic range_racl_policy_shadowed_27_read_perm_27_storage_err; + logic range_racl_policy_shadowed_27_read_perm_27_update_err; + logic [15:0] range_racl_policy_shadowed_27_write_perm_27_qs; + logic [15:0] range_racl_policy_shadowed_27_write_perm_27_wd; + logic range_racl_policy_shadowed_27_write_perm_27_storage_err; + logic range_racl_policy_shadowed_27_write_perm_27_update_err; + logic range_racl_policy_shadowed_28_re; + logic range_racl_policy_shadowed_28_we; + logic [15:0] range_racl_policy_shadowed_28_read_perm_28_qs; + logic [15:0] range_racl_policy_shadowed_28_read_perm_28_wd; + logic range_racl_policy_shadowed_28_read_perm_28_storage_err; + logic range_racl_policy_shadowed_28_read_perm_28_update_err; + logic [15:0] range_racl_policy_shadowed_28_write_perm_28_qs; + logic [15:0] range_racl_policy_shadowed_28_write_perm_28_wd; + logic range_racl_policy_shadowed_28_write_perm_28_storage_err; + logic range_racl_policy_shadowed_28_write_perm_28_update_err; + logic range_racl_policy_shadowed_29_re; + logic range_racl_policy_shadowed_29_we; + logic [15:0] range_racl_policy_shadowed_29_read_perm_29_qs; + logic [15:0] range_racl_policy_shadowed_29_read_perm_29_wd; + logic range_racl_policy_shadowed_29_read_perm_29_storage_err; + logic range_racl_policy_shadowed_29_read_perm_29_update_err; + logic [15:0] range_racl_policy_shadowed_29_write_perm_29_qs; + logic [15:0] range_racl_policy_shadowed_29_write_perm_29_wd; + logic range_racl_policy_shadowed_29_write_perm_29_storage_err; + logic range_racl_policy_shadowed_29_write_perm_29_update_err; + logic range_racl_policy_shadowed_30_re; + logic range_racl_policy_shadowed_30_we; + logic [15:0] range_racl_policy_shadowed_30_read_perm_30_qs; + logic [15:0] range_racl_policy_shadowed_30_read_perm_30_wd; + logic range_racl_policy_shadowed_30_read_perm_30_storage_err; + logic range_racl_policy_shadowed_30_read_perm_30_update_err; + logic [15:0] range_racl_policy_shadowed_30_write_perm_30_qs; + logic [15:0] range_racl_policy_shadowed_30_write_perm_30_wd; + logic range_racl_policy_shadowed_30_write_perm_30_storage_err; + logic range_racl_policy_shadowed_30_write_perm_30_update_err; + logic range_racl_policy_shadowed_31_re; + logic range_racl_policy_shadowed_31_we; + logic [15:0] range_racl_policy_shadowed_31_read_perm_31_qs; + logic [15:0] range_racl_policy_shadowed_31_read_perm_31_wd; + logic range_racl_policy_shadowed_31_read_perm_31_storage_err; + logic range_racl_policy_shadowed_31_read_perm_31_update_err; + logic [15:0] range_racl_policy_shadowed_31_write_perm_31_qs; + logic [15:0] range_racl_policy_shadowed_31_write_perm_31_wd; + logic range_racl_policy_shadowed_31_write_perm_31_storage_err; + logic range_racl_policy_shadowed_31_write_perm_31_update_err; + + // Register instances + // R[intr_state]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.intr_state.de), + .d (hw2reg.intr_state.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.q), + .ds (), + + // to register interface (read) + .qs (intr_state_qs) + ); + + + // R[intr_enable]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [0:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_intr_test ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [1:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[recov_ctrl_update_err]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_ctrl_update_err ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_ctrl_update_err_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.recov_ctrl_update_err.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_ctrl_update_err.qe = alert_test_qe; + + // F[fatal_fault]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe; + + + // R[alert_status]: V(False) + // F[shadowed_update_err]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_status_shadowed_update_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_status_re), + .wd (alert_status_shadowed_update_err_wd), + + // from internal hardware + .de (hw2reg.alert_status.shadowed_update_err.de), + .d (hw2reg.alert_status.shadowed_update_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_status_shadowed_update_err_qs) + ); + + // F[shadowed_storage_err]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_status_shadowed_storage_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.alert_status.shadowed_storage_err.de), + .d (hw2reg.alert_status.shadowed_storage_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_status_shadowed_storage_err_qs) + ); + + // F[reg_intg_err]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_status_reg_intg_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.alert_status.reg_intg_err.de), + .d (hw2reg.alert_status.reg_intg_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_status_reg_intg_err_qs) + ); + + // F[counter_err]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_status_counter_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.alert_status.counter_err.de), + .d (hw2reg.alert_status.counter_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_status_counter_err_qs) + ); + + + // R[log_config]: V(False) + logic log_config_qe; + logic [2:0] log_config_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_log_config0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&log_config_flds_we), + .q_o(log_config_qe) + ); + // F[log_enable]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_log_config_log_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (log_config_we), + .wd (log_config_log_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (log_config_flds_we[0]), + .q (reg2hw.log_config.log_enable.q), + .ds (), + + // to register interface (read) + .qs (log_config_log_enable_qs) + ); + + // F[log_clear]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_log_config_log_clear ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (log_config_we), + .wd (log_config_log_clear_wd), + + // from internal hardware + .de (hw2reg.log_config.log_clear.de), + .d (hw2reg.log_config.log_clear.d), + + // to internal hardware + .qe (log_config_flds_we[1]), + .q (reg2hw.log_config.log_clear.q), + .ds (), + + // to register interface (read) + .qs () + ); + assign reg2hw.log_config.log_clear.qe = log_config_qe; + + // F[deny_cnt_threshold]: 9:2 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_log_config_deny_cnt_threshold ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (log_config_we), + .wd (log_config_deny_cnt_threshold_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (log_config_flds_we[2]), + .q (reg2hw.log_config.deny_cnt_threshold.q), + .ds (), + + // to register interface (read) + .qs (log_config_deny_cnt_threshold_qs) + ); + + + // R[log_status]: V(False) + // F[deny_cnt]: 7:0 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_log_status_deny_cnt ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.deny_cnt.de), + .d (hw2reg.log_status.deny_cnt.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_deny_cnt_qs) + ); + + // F[denied_read_access]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_log_status_denied_read_access ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.denied_read_access.de), + .d (hw2reg.log_status.denied_read_access.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_denied_read_access_qs) + ); + + // F[denied_write_access]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_log_status_denied_write_access ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.denied_write_access.de), + .d (hw2reg.log_status.denied_write_access.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_denied_write_access_qs) + ); + + // F[denied_execute_access]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_log_status_denied_execute_access ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.denied_execute_access.de), + .d (hw2reg.log_status.denied_execute_access.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_denied_execute_access_qs) + ); + + // F[denied_no_match]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_log_status_denied_no_match ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.denied_no_match.de), + .d (hw2reg.log_status.denied_no_match.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_denied_no_match_qs) + ); + + // F[denied_racl_read]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_log_status_denied_racl_read ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.denied_racl_read.de), + .d (hw2reg.log_status.denied_racl_read.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_denied_racl_read_qs) + ); + + // F[denied_racl_write]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_log_status_denied_racl_write ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.denied_racl_write.de), + .d (hw2reg.log_status.denied_racl_write.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_denied_racl_write_qs) + ); + + // F[denied_source_role]: 17:14 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_log_status_denied_source_role ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.denied_source_role.de), + .d (hw2reg.log_status.denied_source_role.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_denied_source_role_qs) + ); + + // F[denied_ctn_uid]: 22:18 + prim_subreg #( + .DW (5), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (5'h0), + .Mubi (1'b0) + ) u_log_status_denied_ctn_uid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.denied_ctn_uid.de), + .d (hw2reg.log_status.denied_ctn_uid.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_denied_ctn_uid_qs) + ); + + // F[deny_range_index]: 27:23 + prim_subreg #( + .DW (5), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (5'h0), + .Mubi (1'b0) + ) u_log_status_deny_range_index ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_status.deny_range_index.de), + .d (hw2reg.log_status.deny_range_index.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_status_deny_range_index_qs) + ); + + + // R[log_address]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_log_address ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.log_address.de), + .d (hw2reg.log_address.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (log_address_qs) + ); + + + // Subregister 0 of Multireg range_regwen + // R[range_regwen_0]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_0_we), + .wd (range_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_0_qs) + ); + + + // Subregister 1 of Multireg range_regwen + // R[range_regwen_1]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_1_we), + .wd (range_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_1_qs) + ); + + + // Subregister 2 of Multireg range_regwen + // R[range_regwen_2]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_2_we), + .wd (range_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_2_qs) + ); + + + // Subregister 3 of Multireg range_regwen + // R[range_regwen_3]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_3_we), + .wd (range_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_3_qs) + ); + + + // Subregister 4 of Multireg range_regwen + // R[range_regwen_4]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_4_we), + .wd (range_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_4_qs) + ); + + + // Subregister 5 of Multireg range_regwen + // R[range_regwen_5]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_5_we), + .wd (range_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_5_qs) + ); + + + // Subregister 6 of Multireg range_regwen + // R[range_regwen_6]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_6_we), + .wd (range_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_6_qs) + ); + + + // Subregister 7 of Multireg range_regwen + // R[range_regwen_7]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_7_we), + .wd (range_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_7_qs) + ); + + + // Subregister 8 of Multireg range_regwen + // R[range_regwen_8]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_8_we), + .wd (range_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_8_qs) + ); + + + // Subregister 9 of Multireg range_regwen + // R[range_regwen_9]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_9_we), + .wd (range_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_9_qs) + ); + + + // Subregister 10 of Multireg range_regwen + // R[range_regwen_10]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_10_we), + .wd (range_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_10_qs) + ); + + + // Subregister 11 of Multireg range_regwen + // R[range_regwen_11]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_11_we), + .wd (range_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_11_qs) + ); + + + // Subregister 12 of Multireg range_regwen + // R[range_regwen_12]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_12_we), + .wd (range_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_12_qs) + ); + + + // Subregister 13 of Multireg range_regwen + // R[range_regwen_13]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_13_we), + .wd (range_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_13_qs) + ); + + + // Subregister 14 of Multireg range_regwen + // R[range_regwen_14]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_14_we), + .wd (range_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_14_qs) + ); + + + // Subregister 15 of Multireg range_regwen + // R[range_regwen_15]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_15_we), + .wd (range_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_15_qs) + ); + + + // Subregister 16 of Multireg range_regwen + // R[range_regwen_16]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_16_we), + .wd (range_regwen_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_16_qs) + ); + + + // Subregister 17 of Multireg range_regwen + // R[range_regwen_17]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_17_we), + .wd (range_regwen_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_17_qs) + ); + + + // Subregister 18 of Multireg range_regwen + // R[range_regwen_18]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_18_we), + .wd (range_regwen_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_18_qs) + ); + + + // Subregister 19 of Multireg range_regwen + // R[range_regwen_19]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_19_we), + .wd (range_regwen_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_19_qs) + ); + + + // Subregister 20 of Multireg range_regwen + // R[range_regwen_20]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_20_we), + .wd (range_regwen_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_20_qs) + ); + + + // Subregister 21 of Multireg range_regwen + // R[range_regwen_21]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_21_we), + .wd (range_regwen_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_21_qs) + ); + + + // Subregister 22 of Multireg range_regwen + // R[range_regwen_22]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_22_we), + .wd (range_regwen_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_22_qs) + ); + + + // Subregister 23 of Multireg range_regwen + // R[range_regwen_23]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_23_we), + .wd (range_regwen_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_23_qs) + ); + + + // Subregister 24 of Multireg range_regwen + // R[range_regwen_24]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_24_we), + .wd (range_regwen_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_24_qs) + ); + + + // Subregister 25 of Multireg range_regwen + // R[range_regwen_25]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_25_we), + .wd (range_regwen_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_25_qs) + ); + + + // Subregister 26 of Multireg range_regwen + // R[range_regwen_26]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_26_we), + .wd (range_regwen_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_26_qs) + ); + + + // Subregister 27 of Multireg range_regwen + // R[range_regwen_27]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_27_we), + .wd (range_regwen_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_27_qs) + ); + + + // Subregister 28 of Multireg range_regwen + // R[range_regwen_28]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_28_we), + .wd (range_regwen_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_28_qs) + ); + + + // Subregister 29 of Multireg range_regwen + // R[range_regwen_29]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_29_we), + .wd (range_regwen_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_29_qs) + ); + + + // Subregister 30 of Multireg range_regwen + // R[range_regwen_30]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_30_we), + .wd (range_regwen_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_30_qs) + ); + + + // Subregister 31 of Multireg range_regwen + // R[range_regwen_31]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_regwen_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_regwen_31_we), + .wd (range_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (range_regwen_31_qs) + ); + + + // Subregister 0 of Multireg range_base + // R[range_base_0]: V(False) + // Create REGWEN-gated WE signal + logic range_base_0_gated_we; + assign range_base_0_gated_we = + range_base_0_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_0_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_0_gated_we), + .wd (range_base_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[0].q), + .ds (), + + // to register interface (read) + .qs (range_base_0_qs) + ); + + + // Subregister 1 of Multireg range_base + // R[range_base_1]: V(False) + // Create REGWEN-gated WE signal + logic range_base_1_gated_we; + assign range_base_1_gated_we = + range_base_1_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_1_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_1_gated_we), + .wd (range_base_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[1].q), + .ds (), + + // to register interface (read) + .qs (range_base_1_qs) + ); + + + // Subregister 2 of Multireg range_base + // R[range_base_2]: V(False) + // Create REGWEN-gated WE signal + logic range_base_2_gated_we; + assign range_base_2_gated_we = + range_base_2_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_2_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_2_gated_we), + .wd (range_base_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[2].q), + .ds (), + + // to register interface (read) + .qs (range_base_2_qs) + ); + + + // Subregister 3 of Multireg range_base + // R[range_base_3]: V(False) + // Create REGWEN-gated WE signal + logic range_base_3_gated_we; + assign range_base_3_gated_we = + range_base_3_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_3_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_3_gated_we), + .wd (range_base_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[3].q), + .ds (), + + // to register interface (read) + .qs (range_base_3_qs) + ); + + + // Subregister 4 of Multireg range_base + // R[range_base_4]: V(False) + // Create REGWEN-gated WE signal + logic range_base_4_gated_we; + assign range_base_4_gated_we = + range_base_4_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_4_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_4_gated_we), + .wd (range_base_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[4].q), + .ds (), + + // to register interface (read) + .qs (range_base_4_qs) + ); + + + // Subregister 5 of Multireg range_base + // R[range_base_5]: V(False) + // Create REGWEN-gated WE signal + logic range_base_5_gated_we; + assign range_base_5_gated_we = + range_base_5_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_5_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_5_gated_we), + .wd (range_base_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[5].q), + .ds (), + + // to register interface (read) + .qs (range_base_5_qs) + ); + + + // Subregister 6 of Multireg range_base + // R[range_base_6]: V(False) + // Create REGWEN-gated WE signal + logic range_base_6_gated_we; + assign range_base_6_gated_we = + range_base_6_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_6_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_6_gated_we), + .wd (range_base_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[6].q), + .ds (), + + // to register interface (read) + .qs (range_base_6_qs) + ); + + + // Subregister 7 of Multireg range_base + // R[range_base_7]: V(False) + // Create REGWEN-gated WE signal + logic range_base_7_gated_we; + assign range_base_7_gated_we = + range_base_7_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_7_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_7_gated_we), + .wd (range_base_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[7].q), + .ds (), + + // to register interface (read) + .qs (range_base_7_qs) + ); + + + // Subregister 8 of Multireg range_base + // R[range_base_8]: V(False) + // Create REGWEN-gated WE signal + logic range_base_8_gated_we; + assign range_base_8_gated_we = + range_base_8_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_8_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_8_gated_we), + .wd (range_base_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[8].q), + .ds (), + + // to register interface (read) + .qs (range_base_8_qs) + ); + + + // Subregister 9 of Multireg range_base + // R[range_base_9]: V(False) + // Create REGWEN-gated WE signal + logic range_base_9_gated_we; + assign range_base_9_gated_we = + range_base_9_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_9_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_9_gated_we), + .wd (range_base_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[9].q), + .ds (), + + // to register interface (read) + .qs (range_base_9_qs) + ); + + + // Subregister 10 of Multireg range_base + // R[range_base_10]: V(False) + // Create REGWEN-gated WE signal + logic range_base_10_gated_we; + assign range_base_10_gated_we = + range_base_10_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_10_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_10_gated_we), + .wd (range_base_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[10].q), + .ds (), + + // to register interface (read) + .qs (range_base_10_qs) + ); + + + // Subregister 11 of Multireg range_base + // R[range_base_11]: V(False) + // Create REGWEN-gated WE signal + logic range_base_11_gated_we; + assign range_base_11_gated_we = + range_base_11_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_11_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_11_gated_we), + .wd (range_base_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[11].q), + .ds (), + + // to register interface (read) + .qs (range_base_11_qs) + ); + + + // Subregister 12 of Multireg range_base + // R[range_base_12]: V(False) + // Create REGWEN-gated WE signal + logic range_base_12_gated_we; + assign range_base_12_gated_we = + range_base_12_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_12_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_12_gated_we), + .wd (range_base_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[12].q), + .ds (), + + // to register interface (read) + .qs (range_base_12_qs) + ); + + + // Subregister 13 of Multireg range_base + // R[range_base_13]: V(False) + // Create REGWEN-gated WE signal + logic range_base_13_gated_we; + assign range_base_13_gated_we = + range_base_13_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_13_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_13_gated_we), + .wd (range_base_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[13].q), + .ds (), + + // to register interface (read) + .qs (range_base_13_qs) + ); + + + // Subregister 14 of Multireg range_base + // R[range_base_14]: V(False) + // Create REGWEN-gated WE signal + logic range_base_14_gated_we; + assign range_base_14_gated_we = + range_base_14_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_14_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_14_gated_we), + .wd (range_base_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[14].q), + .ds (), + + // to register interface (read) + .qs (range_base_14_qs) + ); + + + // Subregister 15 of Multireg range_base + // R[range_base_15]: V(False) + // Create REGWEN-gated WE signal + logic range_base_15_gated_we; + assign range_base_15_gated_we = + range_base_15_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_15_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_15_gated_we), + .wd (range_base_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[15].q), + .ds (), + + // to register interface (read) + .qs (range_base_15_qs) + ); + + + // Subregister 16 of Multireg range_base + // R[range_base_16]: V(False) + // Create REGWEN-gated WE signal + logic range_base_16_gated_we; + assign range_base_16_gated_we = + range_base_16_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_16_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_16_gated_we), + .wd (range_base_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[16].q), + .ds (), + + // to register interface (read) + .qs (range_base_16_qs) + ); + + + // Subregister 17 of Multireg range_base + // R[range_base_17]: V(False) + // Create REGWEN-gated WE signal + logic range_base_17_gated_we; + assign range_base_17_gated_we = + range_base_17_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_17_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_17_gated_we), + .wd (range_base_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[17].q), + .ds (), + + // to register interface (read) + .qs (range_base_17_qs) + ); + + + // Subregister 18 of Multireg range_base + // R[range_base_18]: V(False) + // Create REGWEN-gated WE signal + logic range_base_18_gated_we; + assign range_base_18_gated_we = + range_base_18_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_18_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_18_gated_we), + .wd (range_base_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[18].q), + .ds (), + + // to register interface (read) + .qs (range_base_18_qs) + ); + + + // Subregister 19 of Multireg range_base + // R[range_base_19]: V(False) + // Create REGWEN-gated WE signal + logic range_base_19_gated_we; + assign range_base_19_gated_we = + range_base_19_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_19_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_19_gated_we), + .wd (range_base_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[19].q), + .ds (), + + // to register interface (read) + .qs (range_base_19_qs) + ); + + + // Subregister 20 of Multireg range_base + // R[range_base_20]: V(False) + // Create REGWEN-gated WE signal + logic range_base_20_gated_we; + assign range_base_20_gated_we = + range_base_20_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_20_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_20_gated_we), + .wd (range_base_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[20].q), + .ds (), + + // to register interface (read) + .qs (range_base_20_qs) + ); + + + // Subregister 21 of Multireg range_base + // R[range_base_21]: V(False) + // Create REGWEN-gated WE signal + logic range_base_21_gated_we; + assign range_base_21_gated_we = + range_base_21_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_21_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_21_gated_we), + .wd (range_base_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[21].q), + .ds (), + + // to register interface (read) + .qs (range_base_21_qs) + ); + + + // Subregister 22 of Multireg range_base + // R[range_base_22]: V(False) + // Create REGWEN-gated WE signal + logic range_base_22_gated_we; + assign range_base_22_gated_we = + range_base_22_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_22_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_22_gated_we), + .wd (range_base_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[22].q), + .ds (), + + // to register interface (read) + .qs (range_base_22_qs) + ); + + + // Subregister 23 of Multireg range_base + // R[range_base_23]: V(False) + // Create REGWEN-gated WE signal + logic range_base_23_gated_we; + assign range_base_23_gated_we = + range_base_23_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_23_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_23_gated_we), + .wd (range_base_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[23].q), + .ds (), + + // to register interface (read) + .qs (range_base_23_qs) + ); + + + // Subregister 24 of Multireg range_base + // R[range_base_24]: V(False) + // Create REGWEN-gated WE signal + logic range_base_24_gated_we; + assign range_base_24_gated_we = + range_base_24_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_24_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_24_gated_we), + .wd (range_base_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[24].q), + .ds (), + + // to register interface (read) + .qs (range_base_24_qs) + ); + + + // Subregister 25 of Multireg range_base + // R[range_base_25]: V(False) + // Create REGWEN-gated WE signal + logic range_base_25_gated_we; + assign range_base_25_gated_we = + range_base_25_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_25_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_25_gated_we), + .wd (range_base_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[25].q), + .ds (), + + // to register interface (read) + .qs (range_base_25_qs) + ); + + + // Subregister 26 of Multireg range_base + // R[range_base_26]: V(False) + // Create REGWEN-gated WE signal + logic range_base_26_gated_we; + assign range_base_26_gated_we = + range_base_26_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_26_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_26_gated_we), + .wd (range_base_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[26].q), + .ds (), + + // to register interface (read) + .qs (range_base_26_qs) + ); + + + // Subregister 27 of Multireg range_base + // R[range_base_27]: V(False) + // Create REGWEN-gated WE signal + logic range_base_27_gated_we; + assign range_base_27_gated_we = + range_base_27_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_27_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_27_gated_we), + .wd (range_base_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[27].q), + .ds (), + + // to register interface (read) + .qs (range_base_27_qs) + ); + + + // Subregister 28 of Multireg range_base + // R[range_base_28]: V(False) + // Create REGWEN-gated WE signal + logic range_base_28_gated_we; + assign range_base_28_gated_we = + range_base_28_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_28_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_28_gated_we), + .wd (range_base_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[28].q), + .ds (), + + // to register interface (read) + .qs (range_base_28_qs) + ); + + + // Subregister 29 of Multireg range_base + // R[range_base_29]: V(False) + // Create REGWEN-gated WE signal + logic range_base_29_gated_we; + assign range_base_29_gated_we = + range_base_29_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_29_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_29_gated_we), + .wd (range_base_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[29].q), + .ds (), + + // to register interface (read) + .qs (range_base_29_qs) + ); + + + // Subregister 30 of Multireg range_base + // R[range_base_30]: V(False) + // Create REGWEN-gated WE signal + logic range_base_30_gated_we; + assign range_base_30_gated_we = + range_base_30_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_30_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_30_gated_we), + .wd (range_base_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[30].q), + .ds (), + + // to register interface (read) + .qs (range_base_30_qs) + ); + + + // Subregister 31 of Multireg range_base + // R[range_base_31]: V(False) + // Create REGWEN-gated WE signal + logic range_base_31_gated_we; + assign range_base_31_gated_we = + range_base_31_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_31_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_base_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_base_31_gated_we), + .wd (range_base_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_base[31].q), + .ds (), + + // to register interface (read) + .qs (range_base_31_qs) + ); + + + // Subregister 0 of Multireg range_limit + // R[range_limit_0]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_0_gated_we; + assign range_limit_0_gated_we = + range_limit_0_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_0_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_0_gated_we), + .wd (range_limit_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[0].q), + .ds (), + + // to register interface (read) + .qs (range_limit_0_qs) + ); + + + // Subregister 1 of Multireg range_limit + // R[range_limit_1]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_1_gated_we; + assign range_limit_1_gated_we = + range_limit_1_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_1_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_1_gated_we), + .wd (range_limit_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[1].q), + .ds (), + + // to register interface (read) + .qs (range_limit_1_qs) + ); + + + // Subregister 2 of Multireg range_limit + // R[range_limit_2]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_2_gated_we; + assign range_limit_2_gated_we = + range_limit_2_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_2_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_2_gated_we), + .wd (range_limit_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[2].q), + .ds (), + + // to register interface (read) + .qs (range_limit_2_qs) + ); + + + // Subregister 3 of Multireg range_limit + // R[range_limit_3]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_3_gated_we; + assign range_limit_3_gated_we = + range_limit_3_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_3_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_3_gated_we), + .wd (range_limit_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[3].q), + .ds (), + + // to register interface (read) + .qs (range_limit_3_qs) + ); + + + // Subregister 4 of Multireg range_limit + // R[range_limit_4]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_4_gated_we; + assign range_limit_4_gated_we = + range_limit_4_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_4_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_4_gated_we), + .wd (range_limit_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[4].q), + .ds (), + + // to register interface (read) + .qs (range_limit_4_qs) + ); + + + // Subregister 5 of Multireg range_limit + // R[range_limit_5]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_5_gated_we; + assign range_limit_5_gated_we = + range_limit_5_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_5_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_5_gated_we), + .wd (range_limit_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[5].q), + .ds (), + + // to register interface (read) + .qs (range_limit_5_qs) + ); + + + // Subregister 6 of Multireg range_limit + // R[range_limit_6]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_6_gated_we; + assign range_limit_6_gated_we = + range_limit_6_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_6_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_6_gated_we), + .wd (range_limit_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[6].q), + .ds (), + + // to register interface (read) + .qs (range_limit_6_qs) + ); + + + // Subregister 7 of Multireg range_limit + // R[range_limit_7]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_7_gated_we; + assign range_limit_7_gated_we = + range_limit_7_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_7_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_7_gated_we), + .wd (range_limit_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[7].q), + .ds (), + + // to register interface (read) + .qs (range_limit_7_qs) + ); + + + // Subregister 8 of Multireg range_limit + // R[range_limit_8]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_8_gated_we; + assign range_limit_8_gated_we = + range_limit_8_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_8_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_8_gated_we), + .wd (range_limit_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[8].q), + .ds (), + + // to register interface (read) + .qs (range_limit_8_qs) + ); + + + // Subregister 9 of Multireg range_limit + // R[range_limit_9]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_9_gated_we; + assign range_limit_9_gated_we = + range_limit_9_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_9_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_9_gated_we), + .wd (range_limit_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[9].q), + .ds (), + + // to register interface (read) + .qs (range_limit_9_qs) + ); + + + // Subregister 10 of Multireg range_limit + // R[range_limit_10]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_10_gated_we; + assign range_limit_10_gated_we = + range_limit_10_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_10_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_10_gated_we), + .wd (range_limit_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[10].q), + .ds (), + + // to register interface (read) + .qs (range_limit_10_qs) + ); + + + // Subregister 11 of Multireg range_limit + // R[range_limit_11]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_11_gated_we; + assign range_limit_11_gated_we = + range_limit_11_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_11_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_11_gated_we), + .wd (range_limit_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[11].q), + .ds (), + + // to register interface (read) + .qs (range_limit_11_qs) + ); + + + // Subregister 12 of Multireg range_limit + // R[range_limit_12]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_12_gated_we; + assign range_limit_12_gated_we = + range_limit_12_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_12_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_12_gated_we), + .wd (range_limit_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[12].q), + .ds (), + + // to register interface (read) + .qs (range_limit_12_qs) + ); + + + // Subregister 13 of Multireg range_limit + // R[range_limit_13]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_13_gated_we; + assign range_limit_13_gated_we = + range_limit_13_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_13_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_13_gated_we), + .wd (range_limit_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[13].q), + .ds (), + + // to register interface (read) + .qs (range_limit_13_qs) + ); + + + // Subregister 14 of Multireg range_limit + // R[range_limit_14]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_14_gated_we; + assign range_limit_14_gated_we = + range_limit_14_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_14_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_14_gated_we), + .wd (range_limit_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[14].q), + .ds (), + + // to register interface (read) + .qs (range_limit_14_qs) + ); + + + // Subregister 15 of Multireg range_limit + // R[range_limit_15]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_15_gated_we; + assign range_limit_15_gated_we = + range_limit_15_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_15_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_15_gated_we), + .wd (range_limit_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[15].q), + .ds (), + + // to register interface (read) + .qs (range_limit_15_qs) + ); + + + // Subregister 16 of Multireg range_limit + // R[range_limit_16]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_16_gated_we; + assign range_limit_16_gated_we = + range_limit_16_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_16_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_16_gated_we), + .wd (range_limit_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[16].q), + .ds (), + + // to register interface (read) + .qs (range_limit_16_qs) + ); + + + // Subregister 17 of Multireg range_limit + // R[range_limit_17]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_17_gated_we; + assign range_limit_17_gated_we = + range_limit_17_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_17_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_17_gated_we), + .wd (range_limit_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[17].q), + .ds (), + + // to register interface (read) + .qs (range_limit_17_qs) + ); + + + // Subregister 18 of Multireg range_limit + // R[range_limit_18]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_18_gated_we; + assign range_limit_18_gated_we = + range_limit_18_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_18_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_18_gated_we), + .wd (range_limit_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[18].q), + .ds (), + + // to register interface (read) + .qs (range_limit_18_qs) + ); + + + // Subregister 19 of Multireg range_limit + // R[range_limit_19]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_19_gated_we; + assign range_limit_19_gated_we = + range_limit_19_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_19_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_19_gated_we), + .wd (range_limit_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[19].q), + .ds (), + + // to register interface (read) + .qs (range_limit_19_qs) + ); + + + // Subregister 20 of Multireg range_limit + // R[range_limit_20]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_20_gated_we; + assign range_limit_20_gated_we = + range_limit_20_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_20_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_20_gated_we), + .wd (range_limit_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[20].q), + .ds (), + + // to register interface (read) + .qs (range_limit_20_qs) + ); + + + // Subregister 21 of Multireg range_limit + // R[range_limit_21]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_21_gated_we; + assign range_limit_21_gated_we = + range_limit_21_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_21_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_21_gated_we), + .wd (range_limit_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[21].q), + .ds (), + + // to register interface (read) + .qs (range_limit_21_qs) + ); + + + // Subregister 22 of Multireg range_limit + // R[range_limit_22]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_22_gated_we; + assign range_limit_22_gated_we = + range_limit_22_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_22_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_22_gated_we), + .wd (range_limit_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[22].q), + .ds (), + + // to register interface (read) + .qs (range_limit_22_qs) + ); + + + // Subregister 23 of Multireg range_limit + // R[range_limit_23]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_23_gated_we; + assign range_limit_23_gated_we = + range_limit_23_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_23_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_23_gated_we), + .wd (range_limit_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[23].q), + .ds (), + + // to register interface (read) + .qs (range_limit_23_qs) + ); + + + // Subregister 24 of Multireg range_limit + // R[range_limit_24]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_24_gated_we; + assign range_limit_24_gated_we = + range_limit_24_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_24_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_24_gated_we), + .wd (range_limit_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[24].q), + .ds (), + + // to register interface (read) + .qs (range_limit_24_qs) + ); + + + // Subregister 25 of Multireg range_limit + // R[range_limit_25]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_25_gated_we; + assign range_limit_25_gated_we = + range_limit_25_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_25_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_25_gated_we), + .wd (range_limit_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[25].q), + .ds (), + + // to register interface (read) + .qs (range_limit_25_qs) + ); + + + // Subregister 26 of Multireg range_limit + // R[range_limit_26]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_26_gated_we; + assign range_limit_26_gated_we = + range_limit_26_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_26_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_26_gated_we), + .wd (range_limit_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[26].q), + .ds (), + + // to register interface (read) + .qs (range_limit_26_qs) + ); + + + // Subregister 27 of Multireg range_limit + // R[range_limit_27]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_27_gated_we; + assign range_limit_27_gated_we = + range_limit_27_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_27_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_27_gated_we), + .wd (range_limit_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[27].q), + .ds (), + + // to register interface (read) + .qs (range_limit_27_qs) + ); + + + // Subregister 28 of Multireg range_limit + // R[range_limit_28]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_28_gated_we; + assign range_limit_28_gated_we = + range_limit_28_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_28_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_28_gated_we), + .wd (range_limit_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[28].q), + .ds (), + + // to register interface (read) + .qs (range_limit_28_qs) + ); + + + // Subregister 29 of Multireg range_limit + // R[range_limit_29]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_29_gated_we; + assign range_limit_29_gated_we = + range_limit_29_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_29_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_29_gated_we), + .wd (range_limit_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[29].q), + .ds (), + + // to register interface (read) + .qs (range_limit_29_qs) + ); + + + // Subregister 30 of Multireg range_limit + // R[range_limit_30]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_30_gated_we; + assign range_limit_30_gated_we = + range_limit_30_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_30_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_30_gated_we), + .wd (range_limit_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[30].q), + .ds (), + + // to register interface (read) + .qs (range_limit_30_qs) + ); + + + // Subregister 31 of Multireg range_limit + // R[range_limit_31]: V(False) + // Create REGWEN-gated WE signal + logic range_limit_31_gated_we; + assign range_limit_31_gated_we = + range_limit_31_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_31_qs)); + prim_subreg #( + .DW (30), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (30'h0), + .Mubi (1'b0) + ) u_range_limit_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_limit_31_gated_we), + .wd (range_limit_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_limit[31].q), + .ds (), + + // to register interface (read) + .qs (range_limit_31_qs) + ); + + + // Subregister 0 of Multireg range_attr + // R[range_attr_0]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_0_gated_we; + assign range_attr_0_gated_we = + range_attr_0_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_0_qs)); + // F[enable_0]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_0_enable_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_0_gated_we), + .wd (range_attr_0_enable_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[0].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_0_enable_0_qs) + ); + + // F[read_access_0]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_0_read_access_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_0_gated_we), + .wd (range_attr_0_read_access_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[0].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_0_read_access_0_qs) + ); + + // F[write_access_0]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_0_write_access_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_0_gated_we), + .wd (range_attr_0_write_access_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[0].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_0_write_access_0_qs) + ); + + // F[execute_access_0]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_0_execute_access_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_0_gated_we), + .wd (range_attr_0_execute_access_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[0].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_0_execute_access_0_qs) + ); + + // F[log_denied_access_0]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_0_log_denied_access_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_0_gated_we), + .wd (range_attr_0_log_denied_access_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[0].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_0_log_denied_access_0_qs) + ); + + + // Subregister 1 of Multireg range_attr + // R[range_attr_1]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_1_gated_we; + assign range_attr_1_gated_we = + range_attr_1_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_1_qs)); + // F[enable_1]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_1_enable_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_1_gated_we), + .wd (range_attr_1_enable_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[1].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_1_enable_1_qs) + ); + + // F[read_access_1]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_1_read_access_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_1_gated_we), + .wd (range_attr_1_read_access_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[1].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_1_read_access_1_qs) + ); + + // F[write_access_1]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_1_write_access_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_1_gated_we), + .wd (range_attr_1_write_access_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[1].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_1_write_access_1_qs) + ); + + // F[execute_access_1]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_1_execute_access_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_1_gated_we), + .wd (range_attr_1_execute_access_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[1].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_1_execute_access_1_qs) + ); + + // F[log_denied_access_1]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_1_log_denied_access_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_1_gated_we), + .wd (range_attr_1_log_denied_access_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[1].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_1_log_denied_access_1_qs) + ); + + + // Subregister 2 of Multireg range_attr + // R[range_attr_2]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_2_gated_we; + assign range_attr_2_gated_we = + range_attr_2_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_2_qs)); + // F[enable_2]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_2_enable_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_2_gated_we), + .wd (range_attr_2_enable_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[2].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_2_enable_2_qs) + ); + + // F[read_access_2]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_2_read_access_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_2_gated_we), + .wd (range_attr_2_read_access_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[2].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_2_read_access_2_qs) + ); + + // F[write_access_2]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_2_write_access_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_2_gated_we), + .wd (range_attr_2_write_access_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[2].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_2_write_access_2_qs) + ); + + // F[execute_access_2]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_2_execute_access_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_2_gated_we), + .wd (range_attr_2_execute_access_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[2].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_2_execute_access_2_qs) + ); + + // F[log_denied_access_2]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_2_log_denied_access_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_2_gated_we), + .wd (range_attr_2_log_denied_access_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[2].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_2_log_denied_access_2_qs) + ); + + + // Subregister 3 of Multireg range_attr + // R[range_attr_3]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_3_gated_we; + assign range_attr_3_gated_we = + range_attr_3_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_3_qs)); + // F[enable_3]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_3_enable_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_3_gated_we), + .wd (range_attr_3_enable_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[3].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_3_enable_3_qs) + ); + + // F[read_access_3]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_3_read_access_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_3_gated_we), + .wd (range_attr_3_read_access_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[3].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_3_read_access_3_qs) + ); + + // F[write_access_3]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_3_write_access_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_3_gated_we), + .wd (range_attr_3_write_access_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[3].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_3_write_access_3_qs) + ); + + // F[execute_access_3]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_3_execute_access_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_3_gated_we), + .wd (range_attr_3_execute_access_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[3].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_3_execute_access_3_qs) + ); + + // F[log_denied_access_3]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_3_log_denied_access_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_3_gated_we), + .wd (range_attr_3_log_denied_access_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[3].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_3_log_denied_access_3_qs) + ); + + + // Subregister 4 of Multireg range_attr + // R[range_attr_4]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_4_gated_we; + assign range_attr_4_gated_we = + range_attr_4_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_4_qs)); + // F[enable_4]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_4_enable_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_4_gated_we), + .wd (range_attr_4_enable_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[4].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_4_enable_4_qs) + ); + + // F[read_access_4]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_4_read_access_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_4_gated_we), + .wd (range_attr_4_read_access_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[4].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_4_read_access_4_qs) + ); + + // F[write_access_4]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_4_write_access_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_4_gated_we), + .wd (range_attr_4_write_access_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[4].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_4_write_access_4_qs) + ); + + // F[execute_access_4]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_4_execute_access_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_4_gated_we), + .wd (range_attr_4_execute_access_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[4].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_4_execute_access_4_qs) + ); + + // F[log_denied_access_4]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_4_log_denied_access_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_4_gated_we), + .wd (range_attr_4_log_denied_access_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[4].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_4_log_denied_access_4_qs) + ); + + + // Subregister 5 of Multireg range_attr + // R[range_attr_5]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_5_gated_we; + assign range_attr_5_gated_we = + range_attr_5_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_5_qs)); + // F[enable_5]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_5_enable_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_5_gated_we), + .wd (range_attr_5_enable_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[5].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_5_enable_5_qs) + ); + + // F[read_access_5]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_5_read_access_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_5_gated_we), + .wd (range_attr_5_read_access_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[5].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_5_read_access_5_qs) + ); + + // F[write_access_5]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_5_write_access_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_5_gated_we), + .wd (range_attr_5_write_access_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[5].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_5_write_access_5_qs) + ); + + // F[execute_access_5]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_5_execute_access_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_5_gated_we), + .wd (range_attr_5_execute_access_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[5].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_5_execute_access_5_qs) + ); + + // F[log_denied_access_5]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_5_log_denied_access_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_5_gated_we), + .wd (range_attr_5_log_denied_access_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[5].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_5_log_denied_access_5_qs) + ); + + + // Subregister 6 of Multireg range_attr + // R[range_attr_6]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_6_gated_we; + assign range_attr_6_gated_we = + range_attr_6_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_6_qs)); + // F[enable_6]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_6_enable_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_6_gated_we), + .wd (range_attr_6_enable_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[6].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_6_enable_6_qs) + ); + + // F[read_access_6]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_6_read_access_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_6_gated_we), + .wd (range_attr_6_read_access_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[6].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_6_read_access_6_qs) + ); + + // F[write_access_6]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_6_write_access_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_6_gated_we), + .wd (range_attr_6_write_access_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[6].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_6_write_access_6_qs) + ); + + // F[execute_access_6]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_6_execute_access_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_6_gated_we), + .wd (range_attr_6_execute_access_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[6].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_6_execute_access_6_qs) + ); + + // F[log_denied_access_6]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_6_log_denied_access_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_6_gated_we), + .wd (range_attr_6_log_denied_access_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[6].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_6_log_denied_access_6_qs) + ); + + + // Subregister 7 of Multireg range_attr + // R[range_attr_7]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_7_gated_we; + assign range_attr_7_gated_we = + range_attr_7_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_7_qs)); + // F[enable_7]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_7_enable_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_7_gated_we), + .wd (range_attr_7_enable_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[7].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_7_enable_7_qs) + ); + + // F[read_access_7]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_7_read_access_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_7_gated_we), + .wd (range_attr_7_read_access_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[7].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_7_read_access_7_qs) + ); + + // F[write_access_7]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_7_write_access_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_7_gated_we), + .wd (range_attr_7_write_access_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[7].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_7_write_access_7_qs) + ); + + // F[execute_access_7]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_7_execute_access_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_7_gated_we), + .wd (range_attr_7_execute_access_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[7].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_7_execute_access_7_qs) + ); + + // F[log_denied_access_7]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_7_log_denied_access_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_7_gated_we), + .wd (range_attr_7_log_denied_access_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[7].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_7_log_denied_access_7_qs) + ); + + + // Subregister 8 of Multireg range_attr + // R[range_attr_8]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_8_gated_we; + assign range_attr_8_gated_we = + range_attr_8_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_8_qs)); + // F[enable_8]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_8_enable_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_8_gated_we), + .wd (range_attr_8_enable_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[8].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_8_enable_8_qs) + ); + + // F[read_access_8]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_8_read_access_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_8_gated_we), + .wd (range_attr_8_read_access_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[8].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_8_read_access_8_qs) + ); + + // F[write_access_8]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_8_write_access_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_8_gated_we), + .wd (range_attr_8_write_access_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[8].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_8_write_access_8_qs) + ); + + // F[execute_access_8]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_8_execute_access_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_8_gated_we), + .wd (range_attr_8_execute_access_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[8].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_8_execute_access_8_qs) + ); + + // F[log_denied_access_8]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_8_log_denied_access_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_8_gated_we), + .wd (range_attr_8_log_denied_access_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[8].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_8_log_denied_access_8_qs) + ); + + + // Subregister 9 of Multireg range_attr + // R[range_attr_9]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_9_gated_we; + assign range_attr_9_gated_we = + range_attr_9_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_9_qs)); + // F[enable_9]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_9_enable_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_9_gated_we), + .wd (range_attr_9_enable_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[9].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_9_enable_9_qs) + ); + + // F[read_access_9]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_9_read_access_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_9_gated_we), + .wd (range_attr_9_read_access_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[9].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_9_read_access_9_qs) + ); + + // F[write_access_9]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_9_write_access_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_9_gated_we), + .wd (range_attr_9_write_access_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[9].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_9_write_access_9_qs) + ); + + // F[execute_access_9]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_9_execute_access_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_9_gated_we), + .wd (range_attr_9_execute_access_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[9].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_9_execute_access_9_qs) + ); + + // F[log_denied_access_9]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_9_log_denied_access_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_9_gated_we), + .wd (range_attr_9_log_denied_access_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[9].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_9_log_denied_access_9_qs) + ); + + + // Subregister 10 of Multireg range_attr + // R[range_attr_10]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_10_gated_we; + assign range_attr_10_gated_we = + range_attr_10_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_10_qs)); + // F[enable_10]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_10_enable_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_10_gated_we), + .wd (range_attr_10_enable_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[10].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_10_enable_10_qs) + ); + + // F[read_access_10]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_10_read_access_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_10_gated_we), + .wd (range_attr_10_read_access_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[10].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_10_read_access_10_qs) + ); + + // F[write_access_10]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_10_write_access_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_10_gated_we), + .wd (range_attr_10_write_access_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[10].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_10_write_access_10_qs) + ); + + // F[execute_access_10]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_10_execute_access_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_10_gated_we), + .wd (range_attr_10_execute_access_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[10].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_10_execute_access_10_qs) + ); + + // F[log_denied_access_10]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_10_log_denied_access_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_10_gated_we), + .wd (range_attr_10_log_denied_access_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[10].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_10_log_denied_access_10_qs) + ); + + + // Subregister 11 of Multireg range_attr + // R[range_attr_11]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_11_gated_we; + assign range_attr_11_gated_we = + range_attr_11_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_11_qs)); + // F[enable_11]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_11_enable_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_11_gated_we), + .wd (range_attr_11_enable_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[11].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_11_enable_11_qs) + ); + + // F[read_access_11]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_11_read_access_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_11_gated_we), + .wd (range_attr_11_read_access_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[11].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_11_read_access_11_qs) + ); + + // F[write_access_11]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_11_write_access_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_11_gated_we), + .wd (range_attr_11_write_access_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[11].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_11_write_access_11_qs) + ); + + // F[execute_access_11]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_11_execute_access_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_11_gated_we), + .wd (range_attr_11_execute_access_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[11].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_11_execute_access_11_qs) + ); + + // F[log_denied_access_11]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_11_log_denied_access_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_11_gated_we), + .wd (range_attr_11_log_denied_access_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[11].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_11_log_denied_access_11_qs) + ); + + + // Subregister 12 of Multireg range_attr + // R[range_attr_12]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_12_gated_we; + assign range_attr_12_gated_we = + range_attr_12_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_12_qs)); + // F[enable_12]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_12_enable_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_12_gated_we), + .wd (range_attr_12_enable_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[12].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_12_enable_12_qs) + ); + + // F[read_access_12]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_12_read_access_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_12_gated_we), + .wd (range_attr_12_read_access_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[12].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_12_read_access_12_qs) + ); + + // F[write_access_12]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_12_write_access_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_12_gated_we), + .wd (range_attr_12_write_access_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[12].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_12_write_access_12_qs) + ); + + // F[execute_access_12]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_12_execute_access_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_12_gated_we), + .wd (range_attr_12_execute_access_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[12].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_12_execute_access_12_qs) + ); + + // F[log_denied_access_12]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_12_log_denied_access_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_12_gated_we), + .wd (range_attr_12_log_denied_access_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[12].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_12_log_denied_access_12_qs) + ); + + + // Subregister 13 of Multireg range_attr + // R[range_attr_13]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_13_gated_we; + assign range_attr_13_gated_we = + range_attr_13_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_13_qs)); + // F[enable_13]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_13_enable_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_13_gated_we), + .wd (range_attr_13_enable_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[13].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_13_enable_13_qs) + ); + + // F[read_access_13]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_13_read_access_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_13_gated_we), + .wd (range_attr_13_read_access_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[13].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_13_read_access_13_qs) + ); + + // F[write_access_13]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_13_write_access_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_13_gated_we), + .wd (range_attr_13_write_access_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[13].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_13_write_access_13_qs) + ); + + // F[execute_access_13]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_13_execute_access_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_13_gated_we), + .wd (range_attr_13_execute_access_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[13].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_13_execute_access_13_qs) + ); + + // F[log_denied_access_13]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_13_log_denied_access_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_13_gated_we), + .wd (range_attr_13_log_denied_access_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[13].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_13_log_denied_access_13_qs) + ); + + + // Subregister 14 of Multireg range_attr + // R[range_attr_14]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_14_gated_we; + assign range_attr_14_gated_we = + range_attr_14_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_14_qs)); + // F[enable_14]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_14_enable_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_14_gated_we), + .wd (range_attr_14_enable_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[14].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_14_enable_14_qs) + ); + + // F[read_access_14]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_14_read_access_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_14_gated_we), + .wd (range_attr_14_read_access_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[14].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_14_read_access_14_qs) + ); + + // F[write_access_14]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_14_write_access_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_14_gated_we), + .wd (range_attr_14_write_access_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[14].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_14_write_access_14_qs) + ); + + // F[execute_access_14]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_14_execute_access_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_14_gated_we), + .wd (range_attr_14_execute_access_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[14].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_14_execute_access_14_qs) + ); + + // F[log_denied_access_14]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_14_log_denied_access_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_14_gated_we), + .wd (range_attr_14_log_denied_access_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[14].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_14_log_denied_access_14_qs) + ); + + + // Subregister 15 of Multireg range_attr + // R[range_attr_15]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_15_gated_we; + assign range_attr_15_gated_we = + range_attr_15_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_15_qs)); + // F[enable_15]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_15_enable_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_15_gated_we), + .wd (range_attr_15_enable_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[15].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_15_enable_15_qs) + ); + + // F[read_access_15]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_15_read_access_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_15_gated_we), + .wd (range_attr_15_read_access_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[15].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_15_read_access_15_qs) + ); + + // F[write_access_15]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_15_write_access_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_15_gated_we), + .wd (range_attr_15_write_access_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[15].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_15_write_access_15_qs) + ); + + // F[execute_access_15]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_15_execute_access_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_15_gated_we), + .wd (range_attr_15_execute_access_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[15].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_15_execute_access_15_qs) + ); + + // F[log_denied_access_15]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_15_log_denied_access_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_15_gated_we), + .wd (range_attr_15_log_denied_access_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[15].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_15_log_denied_access_15_qs) + ); + + + // Subregister 16 of Multireg range_attr + // R[range_attr_16]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_16_gated_we; + assign range_attr_16_gated_we = + range_attr_16_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_16_qs)); + // F[enable_16]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_16_enable_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_16_gated_we), + .wd (range_attr_16_enable_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[16].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_16_enable_16_qs) + ); + + // F[read_access_16]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_16_read_access_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_16_gated_we), + .wd (range_attr_16_read_access_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[16].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_16_read_access_16_qs) + ); + + // F[write_access_16]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_16_write_access_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_16_gated_we), + .wd (range_attr_16_write_access_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[16].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_16_write_access_16_qs) + ); + + // F[execute_access_16]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_16_execute_access_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_16_gated_we), + .wd (range_attr_16_execute_access_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[16].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_16_execute_access_16_qs) + ); + + // F[log_denied_access_16]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_16_log_denied_access_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_16_gated_we), + .wd (range_attr_16_log_denied_access_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[16].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_16_log_denied_access_16_qs) + ); + + + // Subregister 17 of Multireg range_attr + // R[range_attr_17]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_17_gated_we; + assign range_attr_17_gated_we = + range_attr_17_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_17_qs)); + // F[enable_17]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_17_enable_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_17_gated_we), + .wd (range_attr_17_enable_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[17].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_17_enable_17_qs) + ); + + // F[read_access_17]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_17_read_access_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_17_gated_we), + .wd (range_attr_17_read_access_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[17].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_17_read_access_17_qs) + ); + + // F[write_access_17]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_17_write_access_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_17_gated_we), + .wd (range_attr_17_write_access_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[17].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_17_write_access_17_qs) + ); + + // F[execute_access_17]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_17_execute_access_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_17_gated_we), + .wd (range_attr_17_execute_access_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[17].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_17_execute_access_17_qs) + ); + + // F[log_denied_access_17]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_17_log_denied_access_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_17_gated_we), + .wd (range_attr_17_log_denied_access_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[17].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_17_log_denied_access_17_qs) + ); + + + // Subregister 18 of Multireg range_attr + // R[range_attr_18]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_18_gated_we; + assign range_attr_18_gated_we = + range_attr_18_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_18_qs)); + // F[enable_18]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_18_enable_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_18_gated_we), + .wd (range_attr_18_enable_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[18].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_18_enable_18_qs) + ); + + // F[read_access_18]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_18_read_access_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_18_gated_we), + .wd (range_attr_18_read_access_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[18].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_18_read_access_18_qs) + ); + + // F[write_access_18]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_18_write_access_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_18_gated_we), + .wd (range_attr_18_write_access_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[18].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_18_write_access_18_qs) + ); + + // F[execute_access_18]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_18_execute_access_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_18_gated_we), + .wd (range_attr_18_execute_access_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[18].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_18_execute_access_18_qs) + ); + + // F[log_denied_access_18]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_18_log_denied_access_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_18_gated_we), + .wd (range_attr_18_log_denied_access_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[18].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_18_log_denied_access_18_qs) + ); + + + // Subregister 19 of Multireg range_attr + // R[range_attr_19]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_19_gated_we; + assign range_attr_19_gated_we = + range_attr_19_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_19_qs)); + // F[enable_19]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_19_enable_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_19_gated_we), + .wd (range_attr_19_enable_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[19].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_19_enable_19_qs) + ); + + // F[read_access_19]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_19_read_access_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_19_gated_we), + .wd (range_attr_19_read_access_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[19].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_19_read_access_19_qs) + ); + + // F[write_access_19]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_19_write_access_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_19_gated_we), + .wd (range_attr_19_write_access_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[19].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_19_write_access_19_qs) + ); + + // F[execute_access_19]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_19_execute_access_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_19_gated_we), + .wd (range_attr_19_execute_access_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[19].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_19_execute_access_19_qs) + ); + + // F[log_denied_access_19]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_19_log_denied_access_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_19_gated_we), + .wd (range_attr_19_log_denied_access_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[19].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_19_log_denied_access_19_qs) + ); + + + // Subregister 20 of Multireg range_attr + // R[range_attr_20]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_20_gated_we; + assign range_attr_20_gated_we = + range_attr_20_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_20_qs)); + // F[enable_20]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_20_enable_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_20_gated_we), + .wd (range_attr_20_enable_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[20].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_20_enable_20_qs) + ); + + // F[read_access_20]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_20_read_access_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_20_gated_we), + .wd (range_attr_20_read_access_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[20].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_20_read_access_20_qs) + ); + + // F[write_access_20]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_20_write_access_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_20_gated_we), + .wd (range_attr_20_write_access_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[20].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_20_write_access_20_qs) + ); + + // F[execute_access_20]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_20_execute_access_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_20_gated_we), + .wd (range_attr_20_execute_access_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[20].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_20_execute_access_20_qs) + ); + + // F[log_denied_access_20]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_20_log_denied_access_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_20_gated_we), + .wd (range_attr_20_log_denied_access_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[20].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_20_log_denied_access_20_qs) + ); + + + // Subregister 21 of Multireg range_attr + // R[range_attr_21]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_21_gated_we; + assign range_attr_21_gated_we = + range_attr_21_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_21_qs)); + // F[enable_21]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_21_enable_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_21_gated_we), + .wd (range_attr_21_enable_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[21].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_21_enable_21_qs) + ); + + // F[read_access_21]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_21_read_access_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_21_gated_we), + .wd (range_attr_21_read_access_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[21].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_21_read_access_21_qs) + ); + + // F[write_access_21]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_21_write_access_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_21_gated_we), + .wd (range_attr_21_write_access_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[21].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_21_write_access_21_qs) + ); + + // F[execute_access_21]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_21_execute_access_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_21_gated_we), + .wd (range_attr_21_execute_access_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[21].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_21_execute_access_21_qs) + ); + + // F[log_denied_access_21]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_21_log_denied_access_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_21_gated_we), + .wd (range_attr_21_log_denied_access_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[21].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_21_log_denied_access_21_qs) + ); + + + // Subregister 22 of Multireg range_attr + // R[range_attr_22]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_22_gated_we; + assign range_attr_22_gated_we = + range_attr_22_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_22_qs)); + // F[enable_22]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_22_enable_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_22_gated_we), + .wd (range_attr_22_enable_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[22].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_22_enable_22_qs) + ); + + // F[read_access_22]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_22_read_access_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_22_gated_we), + .wd (range_attr_22_read_access_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[22].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_22_read_access_22_qs) + ); + + // F[write_access_22]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_22_write_access_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_22_gated_we), + .wd (range_attr_22_write_access_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[22].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_22_write_access_22_qs) + ); + + // F[execute_access_22]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_22_execute_access_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_22_gated_we), + .wd (range_attr_22_execute_access_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[22].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_22_execute_access_22_qs) + ); + + // F[log_denied_access_22]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_22_log_denied_access_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_22_gated_we), + .wd (range_attr_22_log_denied_access_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[22].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_22_log_denied_access_22_qs) + ); + + + // Subregister 23 of Multireg range_attr + // R[range_attr_23]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_23_gated_we; + assign range_attr_23_gated_we = + range_attr_23_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_23_qs)); + // F[enable_23]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_23_enable_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_23_gated_we), + .wd (range_attr_23_enable_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[23].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_23_enable_23_qs) + ); + + // F[read_access_23]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_23_read_access_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_23_gated_we), + .wd (range_attr_23_read_access_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[23].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_23_read_access_23_qs) + ); + + // F[write_access_23]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_23_write_access_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_23_gated_we), + .wd (range_attr_23_write_access_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[23].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_23_write_access_23_qs) + ); + + // F[execute_access_23]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_23_execute_access_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_23_gated_we), + .wd (range_attr_23_execute_access_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[23].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_23_execute_access_23_qs) + ); + + // F[log_denied_access_23]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_23_log_denied_access_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_23_gated_we), + .wd (range_attr_23_log_denied_access_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[23].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_23_log_denied_access_23_qs) + ); + + + // Subregister 24 of Multireg range_attr + // R[range_attr_24]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_24_gated_we; + assign range_attr_24_gated_we = + range_attr_24_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_24_qs)); + // F[enable_24]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_24_enable_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_24_gated_we), + .wd (range_attr_24_enable_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[24].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_24_enable_24_qs) + ); + + // F[read_access_24]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_24_read_access_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_24_gated_we), + .wd (range_attr_24_read_access_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[24].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_24_read_access_24_qs) + ); + + // F[write_access_24]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_24_write_access_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_24_gated_we), + .wd (range_attr_24_write_access_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[24].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_24_write_access_24_qs) + ); + + // F[execute_access_24]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_24_execute_access_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_24_gated_we), + .wd (range_attr_24_execute_access_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[24].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_24_execute_access_24_qs) + ); + + // F[log_denied_access_24]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_24_log_denied_access_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_24_gated_we), + .wd (range_attr_24_log_denied_access_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[24].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_24_log_denied_access_24_qs) + ); + + + // Subregister 25 of Multireg range_attr + // R[range_attr_25]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_25_gated_we; + assign range_attr_25_gated_we = + range_attr_25_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_25_qs)); + // F[enable_25]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_25_enable_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_25_gated_we), + .wd (range_attr_25_enable_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[25].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_25_enable_25_qs) + ); + + // F[read_access_25]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_25_read_access_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_25_gated_we), + .wd (range_attr_25_read_access_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[25].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_25_read_access_25_qs) + ); + + // F[write_access_25]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_25_write_access_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_25_gated_we), + .wd (range_attr_25_write_access_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[25].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_25_write_access_25_qs) + ); + + // F[execute_access_25]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_25_execute_access_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_25_gated_we), + .wd (range_attr_25_execute_access_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[25].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_25_execute_access_25_qs) + ); + + // F[log_denied_access_25]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_25_log_denied_access_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_25_gated_we), + .wd (range_attr_25_log_denied_access_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[25].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_25_log_denied_access_25_qs) + ); + + + // Subregister 26 of Multireg range_attr + // R[range_attr_26]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_26_gated_we; + assign range_attr_26_gated_we = + range_attr_26_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_26_qs)); + // F[enable_26]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_26_enable_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_26_gated_we), + .wd (range_attr_26_enable_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[26].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_26_enable_26_qs) + ); + + // F[read_access_26]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_26_read_access_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_26_gated_we), + .wd (range_attr_26_read_access_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[26].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_26_read_access_26_qs) + ); + + // F[write_access_26]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_26_write_access_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_26_gated_we), + .wd (range_attr_26_write_access_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[26].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_26_write_access_26_qs) + ); + + // F[execute_access_26]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_26_execute_access_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_26_gated_we), + .wd (range_attr_26_execute_access_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[26].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_26_execute_access_26_qs) + ); + + // F[log_denied_access_26]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_26_log_denied_access_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_26_gated_we), + .wd (range_attr_26_log_denied_access_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[26].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_26_log_denied_access_26_qs) + ); + + + // Subregister 27 of Multireg range_attr + // R[range_attr_27]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_27_gated_we; + assign range_attr_27_gated_we = + range_attr_27_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_27_qs)); + // F[enable_27]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_27_enable_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_27_gated_we), + .wd (range_attr_27_enable_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[27].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_27_enable_27_qs) + ); + + // F[read_access_27]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_27_read_access_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_27_gated_we), + .wd (range_attr_27_read_access_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[27].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_27_read_access_27_qs) + ); + + // F[write_access_27]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_27_write_access_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_27_gated_we), + .wd (range_attr_27_write_access_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[27].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_27_write_access_27_qs) + ); + + // F[execute_access_27]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_27_execute_access_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_27_gated_we), + .wd (range_attr_27_execute_access_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[27].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_27_execute_access_27_qs) + ); + + // F[log_denied_access_27]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_27_log_denied_access_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_27_gated_we), + .wd (range_attr_27_log_denied_access_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[27].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_27_log_denied_access_27_qs) + ); + + + // Subregister 28 of Multireg range_attr + // R[range_attr_28]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_28_gated_we; + assign range_attr_28_gated_we = + range_attr_28_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_28_qs)); + // F[enable_28]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_28_enable_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_28_gated_we), + .wd (range_attr_28_enable_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[28].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_28_enable_28_qs) + ); + + // F[read_access_28]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_28_read_access_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_28_gated_we), + .wd (range_attr_28_read_access_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[28].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_28_read_access_28_qs) + ); + + // F[write_access_28]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_28_write_access_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_28_gated_we), + .wd (range_attr_28_write_access_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[28].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_28_write_access_28_qs) + ); + + // F[execute_access_28]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_28_execute_access_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_28_gated_we), + .wd (range_attr_28_execute_access_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[28].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_28_execute_access_28_qs) + ); + + // F[log_denied_access_28]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_28_log_denied_access_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_28_gated_we), + .wd (range_attr_28_log_denied_access_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[28].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_28_log_denied_access_28_qs) + ); + + + // Subregister 29 of Multireg range_attr + // R[range_attr_29]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_29_gated_we; + assign range_attr_29_gated_we = + range_attr_29_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_29_qs)); + // F[enable_29]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_29_enable_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_29_gated_we), + .wd (range_attr_29_enable_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[29].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_29_enable_29_qs) + ); + + // F[read_access_29]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_29_read_access_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_29_gated_we), + .wd (range_attr_29_read_access_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[29].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_29_read_access_29_qs) + ); + + // F[write_access_29]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_29_write_access_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_29_gated_we), + .wd (range_attr_29_write_access_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[29].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_29_write_access_29_qs) + ); + + // F[execute_access_29]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_29_execute_access_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_29_gated_we), + .wd (range_attr_29_execute_access_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[29].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_29_execute_access_29_qs) + ); + + // F[log_denied_access_29]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_29_log_denied_access_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_29_gated_we), + .wd (range_attr_29_log_denied_access_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[29].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_29_log_denied_access_29_qs) + ); + + + // Subregister 30 of Multireg range_attr + // R[range_attr_30]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_30_gated_we; + assign range_attr_30_gated_we = + range_attr_30_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_30_qs)); + // F[enable_30]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_30_enable_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_30_gated_we), + .wd (range_attr_30_enable_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[30].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_30_enable_30_qs) + ); + + // F[read_access_30]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_30_read_access_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_30_gated_we), + .wd (range_attr_30_read_access_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[30].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_30_read_access_30_qs) + ); + + // F[write_access_30]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_30_write_access_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_30_gated_we), + .wd (range_attr_30_write_access_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[30].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_30_write_access_30_qs) + ); + + // F[execute_access_30]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_30_execute_access_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_30_gated_we), + .wd (range_attr_30_execute_access_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[30].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_30_execute_access_30_qs) + ); + + // F[log_denied_access_30]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_30_log_denied_access_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_30_gated_we), + .wd (range_attr_30_log_denied_access_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[30].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_30_log_denied_access_30_qs) + ); + + + // Subregister 31 of Multireg range_attr + // R[range_attr_31]: V(False) + // Create REGWEN-gated WE signal + logic range_attr_31_gated_we; + assign range_attr_31_gated_we = + range_attr_31_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_31_qs)); + // F[enable_31]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_31_enable_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_31_gated_we), + .wd (range_attr_31_enable_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[31].enable.q), + .ds (), + + // to register interface (read) + .qs (range_attr_31_enable_31_qs) + ); + + // F[read_access_31]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_31_read_access_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_31_gated_we), + .wd (range_attr_31_read_access_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[31].read_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_31_read_access_31_qs) + ); + + // F[write_access_31]: 11:8 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_31_write_access_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_31_gated_we), + .wd (range_attr_31_write_access_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[31].write_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_31_write_access_31_qs) + ); + + // F[execute_access_31]: 15:12 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_range_attr_31_execute_access_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_31_gated_we), + .wd (range_attr_31_execute_access_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[31].execute_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_31_execute_access_31_qs) + ); + + // F[log_denied_access_31]: 19:16 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h6), + .Mubi (1'b1) + ) u_range_attr_31_log_denied_access_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (range_attr_31_gated_we), + .wd (range_attr_31_log_denied_access_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_attr[31].log_denied_access.q), + .ds (), + + // to register interface (read) + .qs (range_attr_31_log_denied_access_31_qs) + ); + + + // Subregister 0 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_0]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_0_gated_we; + assign range_racl_policy_shadowed_0_gated_we = + range_racl_policy_shadowed_0_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_0_qs)); + // F[read_perm_0]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_0_read_perm_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_0_re), + .we (range_racl_policy_shadowed_0_gated_we), + .wd (range_racl_policy_shadowed_0_read_perm_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[0].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_0_read_perm_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_0_read_perm_0_update_err), + .err_storage (range_racl_policy_shadowed_0_read_perm_0_storage_err) + ); + + // F[write_perm_0]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_0_write_perm_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_0_re), + .we (range_racl_policy_shadowed_0_gated_we), + .wd (range_racl_policy_shadowed_0_write_perm_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[0].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_0_write_perm_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_0_write_perm_0_update_err), + .err_storage (range_racl_policy_shadowed_0_write_perm_0_storage_err) + ); + + + // Subregister 1 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_1]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_1_gated_we; + assign range_racl_policy_shadowed_1_gated_we = + range_racl_policy_shadowed_1_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_1_qs)); + // F[read_perm_1]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_1_read_perm_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_1_re), + .we (range_racl_policy_shadowed_1_gated_we), + .wd (range_racl_policy_shadowed_1_read_perm_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[1].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_1_read_perm_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_1_read_perm_1_update_err), + .err_storage (range_racl_policy_shadowed_1_read_perm_1_storage_err) + ); + + // F[write_perm_1]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_1_write_perm_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_1_re), + .we (range_racl_policy_shadowed_1_gated_we), + .wd (range_racl_policy_shadowed_1_write_perm_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[1].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_1_write_perm_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_1_write_perm_1_update_err), + .err_storage (range_racl_policy_shadowed_1_write_perm_1_storage_err) + ); + + + // Subregister 2 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_2]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_2_gated_we; + assign range_racl_policy_shadowed_2_gated_we = + range_racl_policy_shadowed_2_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_2_qs)); + // F[read_perm_2]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_2_read_perm_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_2_re), + .we (range_racl_policy_shadowed_2_gated_we), + .wd (range_racl_policy_shadowed_2_read_perm_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[2].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_2_read_perm_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_2_read_perm_2_update_err), + .err_storage (range_racl_policy_shadowed_2_read_perm_2_storage_err) + ); + + // F[write_perm_2]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_2_write_perm_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_2_re), + .we (range_racl_policy_shadowed_2_gated_we), + .wd (range_racl_policy_shadowed_2_write_perm_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[2].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_2_write_perm_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_2_write_perm_2_update_err), + .err_storage (range_racl_policy_shadowed_2_write_perm_2_storage_err) + ); + + + // Subregister 3 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_3]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_3_gated_we; + assign range_racl_policy_shadowed_3_gated_we = + range_racl_policy_shadowed_3_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_3_qs)); + // F[read_perm_3]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_3_read_perm_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_3_re), + .we (range_racl_policy_shadowed_3_gated_we), + .wd (range_racl_policy_shadowed_3_read_perm_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[3].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_3_read_perm_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_3_read_perm_3_update_err), + .err_storage (range_racl_policy_shadowed_3_read_perm_3_storage_err) + ); + + // F[write_perm_3]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_3_write_perm_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_3_re), + .we (range_racl_policy_shadowed_3_gated_we), + .wd (range_racl_policy_shadowed_3_write_perm_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[3].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_3_write_perm_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_3_write_perm_3_update_err), + .err_storage (range_racl_policy_shadowed_3_write_perm_3_storage_err) + ); + + + // Subregister 4 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_4]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_4_gated_we; + assign range_racl_policy_shadowed_4_gated_we = + range_racl_policy_shadowed_4_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_4_qs)); + // F[read_perm_4]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_4_read_perm_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_4_re), + .we (range_racl_policy_shadowed_4_gated_we), + .wd (range_racl_policy_shadowed_4_read_perm_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[4].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_4_read_perm_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_4_read_perm_4_update_err), + .err_storage (range_racl_policy_shadowed_4_read_perm_4_storage_err) + ); + + // F[write_perm_4]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_4_write_perm_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_4_re), + .we (range_racl_policy_shadowed_4_gated_we), + .wd (range_racl_policy_shadowed_4_write_perm_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[4].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_4_write_perm_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_4_write_perm_4_update_err), + .err_storage (range_racl_policy_shadowed_4_write_perm_4_storage_err) + ); + + + // Subregister 5 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_5]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_5_gated_we; + assign range_racl_policy_shadowed_5_gated_we = + range_racl_policy_shadowed_5_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_5_qs)); + // F[read_perm_5]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_5_read_perm_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_5_re), + .we (range_racl_policy_shadowed_5_gated_we), + .wd (range_racl_policy_shadowed_5_read_perm_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[5].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_5_read_perm_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_5_read_perm_5_update_err), + .err_storage (range_racl_policy_shadowed_5_read_perm_5_storage_err) + ); + + // F[write_perm_5]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_5_write_perm_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_5_re), + .we (range_racl_policy_shadowed_5_gated_we), + .wd (range_racl_policy_shadowed_5_write_perm_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[5].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_5_write_perm_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_5_write_perm_5_update_err), + .err_storage (range_racl_policy_shadowed_5_write_perm_5_storage_err) + ); + + + // Subregister 6 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_6]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_6_gated_we; + assign range_racl_policy_shadowed_6_gated_we = + range_racl_policy_shadowed_6_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_6_qs)); + // F[read_perm_6]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_6_read_perm_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_6_re), + .we (range_racl_policy_shadowed_6_gated_we), + .wd (range_racl_policy_shadowed_6_read_perm_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[6].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_6_read_perm_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_6_read_perm_6_update_err), + .err_storage (range_racl_policy_shadowed_6_read_perm_6_storage_err) + ); + + // F[write_perm_6]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_6_write_perm_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_6_re), + .we (range_racl_policy_shadowed_6_gated_we), + .wd (range_racl_policy_shadowed_6_write_perm_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[6].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_6_write_perm_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_6_write_perm_6_update_err), + .err_storage (range_racl_policy_shadowed_6_write_perm_6_storage_err) + ); + + + // Subregister 7 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_7]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_7_gated_we; + assign range_racl_policy_shadowed_7_gated_we = + range_racl_policy_shadowed_7_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_7_qs)); + // F[read_perm_7]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_7_read_perm_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_7_re), + .we (range_racl_policy_shadowed_7_gated_we), + .wd (range_racl_policy_shadowed_7_read_perm_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[7].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_7_read_perm_7_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_7_read_perm_7_update_err), + .err_storage (range_racl_policy_shadowed_7_read_perm_7_storage_err) + ); + + // F[write_perm_7]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_7_write_perm_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_7_re), + .we (range_racl_policy_shadowed_7_gated_we), + .wd (range_racl_policy_shadowed_7_write_perm_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[7].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_7_write_perm_7_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_7_write_perm_7_update_err), + .err_storage (range_racl_policy_shadowed_7_write_perm_7_storage_err) + ); + + + // Subregister 8 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_8]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_8_gated_we; + assign range_racl_policy_shadowed_8_gated_we = + range_racl_policy_shadowed_8_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_8_qs)); + // F[read_perm_8]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_8_read_perm_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_8_re), + .we (range_racl_policy_shadowed_8_gated_we), + .wd (range_racl_policy_shadowed_8_read_perm_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[8].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_8_read_perm_8_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_8_read_perm_8_update_err), + .err_storage (range_racl_policy_shadowed_8_read_perm_8_storage_err) + ); + + // F[write_perm_8]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_8_write_perm_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_8_re), + .we (range_racl_policy_shadowed_8_gated_we), + .wd (range_racl_policy_shadowed_8_write_perm_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[8].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_8_write_perm_8_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_8_write_perm_8_update_err), + .err_storage (range_racl_policy_shadowed_8_write_perm_8_storage_err) + ); + + + // Subregister 9 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_9]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_9_gated_we; + assign range_racl_policy_shadowed_9_gated_we = + range_racl_policy_shadowed_9_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_9_qs)); + // F[read_perm_9]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_9_read_perm_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_9_re), + .we (range_racl_policy_shadowed_9_gated_we), + .wd (range_racl_policy_shadowed_9_read_perm_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[9].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_9_read_perm_9_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_9_read_perm_9_update_err), + .err_storage (range_racl_policy_shadowed_9_read_perm_9_storage_err) + ); + + // F[write_perm_9]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_9_write_perm_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_9_re), + .we (range_racl_policy_shadowed_9_gated_we), + .wd (range_racl_policy_shadowed_9_write_perm_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[9].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_9_write_perm_9_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_9_write_perm_9_update_err), + .err_storage (range_racl_policy_shadowed_9_write_perm_9_storage_err) + ); + + + // Subregister 10 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_10]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_10_gated_we; + assign range_racl_policy_shadowed_10_gated_we = + range_racl_policy_shadowed_10_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_10_qs)); + // F[read_perm_10]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_10_read_perm_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_10_re), + .we (range_racl_policy_shadowed_10_gated_we), + .wd (range_racl_policy_shadowed_10_read_perm_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[10].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_10_read_perm_10_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_10_read_perm_10_update_err), + .err_storage (range_racl_policy_shadowed_10_read_perm_10_storage_err) + ); + + // F[write_perm_10]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_10_write_perm_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_10_re), + .we (range_racl_policy_shadowed_10_gated_we), + .wd (range_racl_policy_shadowed_10_write_perm_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[10].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_10_write_perm_10_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_10_write_perm_10_update_err), + .err_storage (range_racl_policy_shadowed_10_write_perm_10_storage_err) + ); + + + // Subregister 11 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_11]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_11_gated_we; + assign range_racl_policy_shadowed_11_gated_we = + range_racl_policy_shadowed_11_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_11_qs)); + // F[read_perm_11]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_11_read_perm_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_11_re), + .we (range_racl_policy_shadowed_11_gated_we), + .wd (range_racl_policy_shadowed_11_read_perm_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[11].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_11_read_perm_11_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_11_read_perm_11_update_err), + .err_storage (range_racl_policy_shadowed_11_read_perm_11_storage_err) + ); + + // F[write_perm_11]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_11_write_perm_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_11_re), + .we (range_racl_policy_shadowed_11_gated_we), + .wd (range_racl_policy_shadowed_11_write_perm_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[11].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_11_write_perm_11_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_11_write_perm_11_update_err), + .err_storage (range_racl_policy_shadowed_11_write_perm_11_storage_err) + ); + + + // Subregister 12 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_12]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_12_gated_we; + assign range_racl_policy_shadowed_12_gated_we = + range_racl_policy_shadowed_12_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_12_qs)); + // F[read_perm_12]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_12_read_perm_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_12_re), + .we (range_racl_policy_shadowed_12_gated_we), + .wd (range_racl_policy_shadowed_12_read_perm_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[12].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_12_read_perm_12_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_12_read_perm_12_update_err), + .err_storage (range_racl_policy_shadowed_12_read_perm_12_storage_err) + ); + + // F[write_perm_12]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_12_write_perm_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_12_re), + .we (range_racl_policy_shadowed_12_gated_we), + .wd (range_racl_policy_shadowed_12_write_perm_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[12].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_12_write_perm_12_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_12_write_perm_12_update_err), + .err_storage (range_racl_policy_shadowed_12_write_perm_12_storage_err) + ); + + + // Subregister 13 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_13]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_13_gated_we; + assign range_racl_policy_shadowed_13_gated_we = + range_racl_policy_shadowed_13_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_13_qs)); + // F[read_perm_13]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_13_read_perm_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_13_re), + .we (range_racl_policy_shadowed_13_gated_we), + .wd (range_racl_policy_shadowed_13_read_perm_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[13].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_13_read_perm_13_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_13_read_perm_13_update_err), + .err_storage (range_racl_policy_shadowed_13_read_perm_13_storage_err) + ); + + // F[write_perm_13]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_13_write_perm_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_13_re), + .we (range_racl_policy_shadowed_13_gated_we), + .wd (range_racl_policy_shadowed_13_write_perm_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[13].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_13_write_perm_13_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_13_write_perm_13_update_err), + .err_storage (range_racl_policy_shadowed_13_write_perm_13_storage_err) + ); + + + // Subregister 14 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_14]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_14_gated_we; + assign range_racl_policy_shadowed_14_gated_we = + range_racl_policy_shadowed_14_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_14_qs)); + // F[read_perm_14]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_14_read_perm_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_14_re), + .we (range_racl_policy_shadowed_14_gated_we), + .wd (range_racl_policy_shadowed_14_read_perm_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[14].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_14_read_perm_14_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_14_read_perm_14_update_err), + .err_storage (range_racl_policy_shadowed_14_read_perm_14_storage_err) + ); + + // F[write_perm_14]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_14_write_perm_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_14_re), + .we (range_racl_policy_shadowed_14_gated_we), + .wd (range_racl_policy_shadowed_14_write_perm_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[14].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_14_write_perm_14_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_14_write_perm_14_update_err), + .err_storage (range_racl_policy_shadowed_14_write_perm_14_storage_err) + ); + + + // Subregister 15 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_15]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_15_gated_we; + assign range_racl_policy_shadowed_15_gated_we = + range_racl_policy_shadowed_15_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_15_qs)); + // F[read_perm_15]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_15_read_perm_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_15_re), + .we (range_racl_policy_shadowed_15_gated_we), + .wd (range_racl_policy_shadowed_15_read_perm_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[15].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_15_read_perm_15_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_15_read_perm_15_update_err), + .err_storage (range_racl_policy_shadowed_15_read_perm_15_storage_err) + ); + + // F[write_perm_15]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_15_write_perm_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_15_re), + .we (range_racl_policy_shadowed_15_gated_we), + .wd (range_racl_policy_shadowed_15_write_perm_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[15].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_15_write_perm_15_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_15_write_perm_15_update_err), + .err_storage (range_racl_policy_shadowed_15_write_perm_15_storage_err) + ); + + + // Subregister 16 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_16]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_16_gated_we; + assign range_racl_policy_shadowed_16_gated_we = + range_racl_policy_shadowed_16_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_16_qs)); + // F[read_perm_16]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_16_read_perm_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_16_re), + .we (range_racl_policy_shadowed_16_gated_we), + .wd (range_racl_policy_shadowed_16_read_perm_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[16].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_16_read_perm_16_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_16_read_perm_16_update_err), + .err_storage (range_racl_policy_shadowed_16_read_perm_16_storage_err) + ); + + // F[write_perm_16]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_16_write_perm_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_16_re), + .we (range_racl_policy_shadowed_16_gated_we), + .wd (range_racl_policy_shadowed_16_write_perm_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[16].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_16_write_perm_16_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_16_write_perm_16_update_err), + .err_storage (range_racl_policy_shadowed_16_write_perm_16_storage_err) + ); + + + // Subregister 17 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_17]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_17_gated_we; + assign range_racl_policy_shadowed_17_gated_we = + range_racl_policy_shadowed_17_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_17_qs)); + // F[read_perm_17]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_17_read_perm_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_17_re), + .we (range_racl_policy_shadowed_17_gated_we), + .wd (range_racl_policy_shadowed_17_read_perm_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[17].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_17_read_perm_17_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_17_read_perm_17_update_err), + .err_storage (range_racl_policy_shadowed_17_read_perm_17_storage_err) + ); + + // F[write_perm_17]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_17_write_perm_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_17_re), + .we (range_racl_policy_shadowed_17_gated_we), + .wd (range_racl_policy_shadowed_17_write_perm_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[17].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_17_write_perm_17_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_17_write_perm_17_update_err), + .err_storage (range_racl_policy_shadowed_17_write_perm_17_storage_err) + ); + + + // Subregister 18 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_18]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_18_gated_we; + assign range_racl_policy_shadowed_18_gated_we = + range_racl_policy_shadowed_18_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_18_qs)); + // F[read_perm_18]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_18_read_perm_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_18_re), + .we (range_racl_policy_shadowed_18_gated_we), + .wd (range_racl_policy_shadowed_18_read_perm_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[18].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_18_read_perm_18_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_18_read_perm_18_update_err), + .err_storage (range_racl_policy_shadowed_18_read_perm_18_storage_err) + ); + + // F[write_perm_18]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_18_write_perm_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_18_re), + .we (range_racl_policy_shadowed_18_gated_we), + .wd (range_racl_policy_shadowed_18_write_perm_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[18].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_18_write_perm_18_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_18_write_perm_18_update_err), + .err_storage (range_racl_policy_shadowed_18_write_perm_18_storage_err) + ); + + + // Subregister 19 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_19]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_19_gated_we; + assign range_racl_policy_shadowed_19_gated_we = + range_racl_policy_shadowed_19_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_19_qs)); + // F[read_perm_19]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_19_read_perm_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_19_re), + .we (range_racl_policy_shadowed_19_gated_we), + .wd (range_racl_policy_shadowed_19_read_perm_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[19].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_19_read_perm_19_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_19_read_perm_19_update_err), + .err_storage (range_racl_policy_shadowed_19_read_perm_19_storage_err) + ); + + // F[write_perm_19]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_19_write_perm_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_19_re), + .we (range_racl_policy_shadowed_19_gated_we), + .wd (range_racl_policy_shadowed_19_write_perm_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[19].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_19_write_perm_19_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_19_write_perm_19_update_err), + .err_storage (range_racl_policy_shadowed_19_write_perm_19_storage_err) + ); + + + // Subregister 20 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_20]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_20_gated_we; + assign range_racl_policy_shadowed_20_gated_we = + range_racl_policy_shadowed_20_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_20_qs)); + // F[read_perm_20]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_20_read_perm_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_20_re), + .we (range_racl_policy_shadowed_20_gated_we), + .wd (range_racl_policy_shadowed_20_read_perm_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[20].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_20_read_perm_20_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_20_read_perm_20_update_err), + .err_storage (range_racl_policy_shadowed_20_read_perm_20_storage_err) + ); + + // F[write_perm_20]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_20_write_perm_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_20_re), + .we (range_racl_policy_shadowed_20_gated_we), + .wd (range_racl_policy_shadowed_20_write_perm_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[20].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_20_write_perm_20_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_20_write_perm_20_update_err), + .err_storage (range_racl_policy_shadowed_20_write_perm_20_storage_err) + ); + + + // Subregister 21 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_21]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_21_gated_we; + assign range_racl_policy_shadowed_21_gated_we = + range_racl_policy_shadowed_21_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_21_qs)); + // F[read_perm_21]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_21_read_perm_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_21_re), + .we (range_racl_policy_shadowed_21_gated_we), + .wd (range_racl_policy_shadowed_21_read_perm_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[21].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_21_read_perm_21_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_21_read_perm_21_update_err), + .err_storage (range_racl_policy_shadowed_21_read_perm_21_storage_err) + ); + + // F[write_perm_21]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_21_write_perm_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_21_re), + .we (range_racl_policy_shadowed_21_gated_we), + .wd (range_racl_policy_shadowed_21_write_perm_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[21].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_21_write_perm_21_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_21_write_perm_21_update_err), + .err_storage (range_racl_policy_shadowed_21_write_perm_21_storage_err) + ); + + + // Subregister 22 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_22]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_22_gated_we; + assign range_racl_policy_shadowed_22_gated_we = + range_racl_policy_shadowed_22_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_22_qs)); + // F[read_perm_22]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_22_read_perm_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_22_re), + .we (range_racl_policy_shadowed_22_gated_we), + .wd (range_racl_policy_shadowed_22_read_perm_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[22].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_22_read_perm_22_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_22_read_perm_22_update_err), + .err_storage (range_racl_policy_shadowed_22_read_perm_22_storage_err) + ); + + // F[write_perm_22]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_22_write_perm_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_22_re), + .we (range_racl_policy_shadowed_22_gated_we), + .wd (range_racl_policy_shadowed_22_write_perm_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[22].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_22_write_perm_22_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_22_write_perm_22_update_err), + .err_storage (range_racl_policy_shadowed_22_write_perm_22_storage_err) + ); + + + // Subregister 23 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_23]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_23_gated_we; + assign range_racl_policy_shadowed_23_gated_we = + range_racl_policy_shadowed_23_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_23_qs)); + // F[read_perm_23]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_23_read_perm_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_23_re), + .we (range_racl_policy_shadowed_23_gated_we), + .wd (range_racl_policy_shadowed_23_read_perm_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[23].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_23_read_perm_23_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_23_read_perm_23_update_err), + .err_storage (range_racl_policy_shadowed_23_read_perm_23_storage_err) + ); + + // F[write_perm_23]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_23_write_perm_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_23_re), + .we (range_racl_policy_shadowed_23_gated_we), + .wd (range_racl_policy_shadowed_23_write_perm_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[23].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_23_write_perm_23_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_23_write_perm_23_update_err), + .err_storage (range_racl_policy_shadowed_23_write_perm_23_storage_err) + ); + + + // Subregister 24 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_24]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_24_gated_we; + assign range_racl_policy_shadowed_24_gated_we = + range_racl_policy_shadowed_24_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_24_qs)); + // F[read_perm_24]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_24_read_perm_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_24_re), + .we (range_racl_policy_shadowed_24_gated_we), + .wd (range_racl_policy_shadowed_24_read_perm_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[24].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_24_read_perm_24_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_24_read_perm_24_update_err), + .err_storage (range_racl_policy_shadowed_24_read_perm_24_storage_err) + ); + + // F[write_perm_24]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_24_write_perm_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_24_re), + .we (range_racl_policy_shadowed_24_gated_we), + .wd (range_racl_policy_shadowed_24_write_perm_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[24].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_24_write_perm_24_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_24_write_perm_24_update_err), + .err_storage (range_racl_policy_shadowed_24_write_perm_24_storage_err) + ); + + + // Subregister 25 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_25]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_25_gated_we; + assign range_racl_policy_shadowed_25_gated_we = + range_racl_policy_shadowed_25_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_25_qs)); + // F[read_perm_25]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_25_read_perm_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_25_re), + .we (range_racl_policy_shadowed_25_gated_we), + .wd (range_racl_policy_shadowed_25_read_perm_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[25].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_25_read_perm_25_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_25_read_perm_25_update_err), + .err_storage (range_racl_policy_shadowed_25_read_perm_25_storage_err) + ); + + // F[write_perm_25]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_25_write_perm_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_25_re), + .we (range_racl_policy_shadowed_25_gated_we), + .wd (range_racl_policy_shadowed_25_write_perm_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[25].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_25_write_perm_25_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_25_write_perm_25_update_err), + .err_storage (range_racl_policy_shadowed_25_write_perm_25_storage_err) + ); + + + // Subregister 26 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_26]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_26_gated_we; + assign range_racl_policy_shadowed_26_gated_we = + range_racl_policy_shadowed_26_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_26_qs)); + // F[read_perm_26]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_26_read_perm_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_26_re), + .we (range_racl_policy_shadowed_26_gated_we), + .wd (range_racl_policy_shadowed_26_read_perm_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[26].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_26_read_perm_26_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_26_read_perm_26_update_err), + .err_storage (range_racl_policy_shadowed_26_read_perm_26_storage_err) + ); + + // F[write_perm_26]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_26_write_perm_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_26_re), + .we (range_racl_policy_shadowed_26_gated_we), + .wd (range_racl_policy_shadowed_26_write_perm_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[26].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_26_write_perm_26_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_26_write_perm_26_update_err), + .err_storage (range_racl_policy_shadowed_26_write_perm_26_storage_err) + ); + + + // Subregister 27 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_27]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_27_gated_we; + assign range_racl_policy_shadowed_27_gated_we = + range_racl_policy_shadowed_27_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_27_qs)); + // F[read_perm_27]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_27_read_perm_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_27_re), + .we (range_racl_policy_shadowed_27_gated_we), + .wd (range_racl_policy_shadowed_27_read_perm_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[27].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_27_read_perm_27_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_27_read_perm_27_update_err), + .err_storage (range_racl_policy_shadowed_27_read_perm_27_storage_err) + ); + + // F[write_perm_27]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_27_write_perm_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_27_re), + .we (range_racl_policy_shadowed_27_gated_we), + .wd (range_racl_policy_shadowed_27_write_perm_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[27].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_27_write_perm_27_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_27_write_perm_27_update_err), + .err_storage (range_racl_policy_shadowed_27_write_perm_27_storage_err) + ); + + + // Subregister 28 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_28]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_28_gated_we; + assign range_racl_policy_shadowed_28_gated_we = + range_racl_policy_shadowed_28_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_28_qs)); + // F[read_perm_28]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_28_read_perm_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_28_re), + .we (range_racl_policy_shadowed_28_gated_we), + .wd (range_racl_policy_shadowed_28_read_perm_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[28].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_28_read_perm_28_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_28_read_perm_28_update_err), + .err_storage (range_racl_policy_shadowed_28_read_perm_28_storage_err) + ); + + // F[write_perm_28]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_28_write_perm_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_28_re), + .we (range_racl_policy_shadowed_28_gated_we), + .wd (range_racl_policy_shadowed_28_write_perm_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[28].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_28_write_perm_28_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_28_write_perm_28_update_err), + .err_storage (range_racl_policy_shadowed_28_write_perm_28_storage_err) + ); + + + // Subregister 29 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_29]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_29_gated_we; + assign range_racl_policy_shadowed_29_gated_we = + range_racl_policy_shadowed_29_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_29_qs)); + // F[read_perm_29]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_29_read_perm_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_29_re), + .we (range_racl_policy_shadowed_29_gated_we), + .wd (range_racl_policy_shadowed_29_read_perm_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[29].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_29_read_perm_29_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_29_read_perm_29_update_err), + .err_storage (range_racl_policy_shadowed_29_read_perm_29_storage_err) + ); + + // F[write_perm_29]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_29_write_perm_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_29_re), + .we (range_racl_policy_shadowed_29_gated_we), + .wd (range_racl_policy_shadowed_29_write_perm_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[29].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_29_write_perm_29_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_29_write_perm_29_update_err), + .err_storage (range_racl_policy_shadowed_29_write_perm_29_storage_err) + ); + + + // Subregister 30 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_30]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_30_gated_we; + assign range_racl_policy_shadowed_30_gated_we = + range_racl_policy_shadowed_30_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_30_qs)); + // F[read_perm_30]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_30_read_perm_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_30_re), + .we (range_racl_policy_shadowed_30_gated_we), + .wd (range_racl_policy_shadowed_30_read_perm_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[30].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_30_read_perm_30_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_30_read_perm_30_update_err), + .err_storage (range_racl_policy_shadowed_30_read_perm_30_storage_err) + ); + + // F[write_perm_30]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_30_write_perm_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_30_re), + .we (range_racl_policy_shadowed_30_gated_we), + .wd (range_racl_policy_shadowed_30_write_perm_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[30].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_30_write_perm_30_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_30_write_perm_30_update_err), + .err_storage (range_racl_policy_shadowed_30_write_perm_30_storage_err) + ); + + + // Subregister 31 of Multireg range_racl_policy_shadowed + // R[range_racl_policy_shadowed_31]: V(False) + // Create REGWEN-gated WE signal + logic range_racl_policy_shadowed_31_gated_we; + assign range_racl_policy_shadowed_31_gated_we = + range_racl_policy_shadowed_31_we & + prim_mubi_pkg::mubi4_test_true_strict(prim_mubi_pkg::mubi4_t'(range_regwen_31_qs)); + // F[read_perm_31]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_31_read_perm_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_31_re), + .we (range_racl_policy_shadowed_31_gated_we), + .wd (range_racl_policy_shadowed_31_read_perm_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[31].read_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_31_read_perm_31_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_31_read_perm_31_update_err), + .err_storage (range_racl_policy_shadowed_31_read_perm_31_storage_err) + ); + + // F[write_perm_31]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_range_racl_policy_shadowed_31_write_perm_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (range_racl_policy_shadowed_31_re), + .we (range_racl_policy_shadowed_31_gated_we), + .wd (range_racl_policy_shadowed_31_write_perm_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.range_racl_policy_shadowed[31].write_perm.q), + .ds (), + + // to register interface (read) + .qs (range_racl_policy_shadowed_31_write_perm_31_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (range_racl_policy_shadowed_31_write_perm_31_update_err), + .err_storage (range_racl_policy_shadowed_31_write_perm_31_storage_err) + ); + + + + logic [167:0] addr_hit; + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + + logic [167:0] racl_addr_hit_read; + logic [167:0] racl_addr_hit_write; + + if (EnableRacl) begin : gen_racl_role_logic + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + end else begin : gen_no_racl_role_logic + assign racl_role = '0; + assign racl_role_vec = '0; + end + + always_comb begin + racl_addr_hit_read = '0; + racl_addr_hit_write = '0; + addr_hit[ 0] = (reg_addr == AC_RANGE_CHECK_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == AC_RANGE_CHECK_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == AC_RANGE_CHECK_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == AC_RANGE_CHECK_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == AC_RANGE_CHECK_ALERT_STATUS_OFFSET); + addr_hit[ 5] = (reg_addr == AC_RANGE_CHECK_LOG_CONFIG_OFFSET); + addr_hit[ 6] = (reg_addr == AC_RANGE_CHECK_LOG_STATUS_OFFSET); + addr_hit[ 7] = (reg_addr == AC_RANGE_CHECK_LOG_ADDRESS_OFFSET); + addr_hit[ 8] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_0_OFFSET); + addr_hit[ 9] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_1_OFFSET); + addr_hit[ 10] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_2_OFFSET); + addr_hit[ 11] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_3_OFFSET); + addr_hit[ 12] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_4_OFFSET); + addr_hit[ 13] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_5_OFFSET); + addr_hit[ 14] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_6_OFFSET); + addr_hit[ 15] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_7_OFFSET); + addr_hit[ 16] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_8_OFFSET); + addr_hit[ 17] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_9_OFFSET); + addr_hit[ 18] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_10_OFFSET); + addr_hit[ 19] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_11_OFFSET); + addr_hit[ 20] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_12_OFFSET); + addr_hit[ 21] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_13_OFFSET); + addr_hit[ 22] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_14_OFFSET); + addr_hit[ 23] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_15_OFFSET); + addr_hit[ 24] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_16_OFFSET); + addr_hit[ 25] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_17_OFFSET); + addr_hit[ 26] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_18_OFFSET); + addr_hit[ 27] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_19_OFFSET); + addr_hit[ 28] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_20_OFFSET); + addr_hit[ 29] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_21_OFFSET); + addr_hit[ 30] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_22_OFFSET); + addr_hit[ 31] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_23_OFFSET); + addr_hit[ 32] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_24_OFFSET); + addr_hit[ 33] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_25_OFFSET); + addr_hit[ 34] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_26_OFFSET); + addr_hit[ 35] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_27_OFFSET); + addr_hit[ 36] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_28_OFFSET); + addr_hit[ 37] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_29_OFFSET); + addr_hit[ 38] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_30_OFFSET); + addr_hit[ 39] = (reg_addr == AC_RANGE_CHECK_RANGE_REGWEN_31_OFFSET); + addr_hit[ 40] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_0_OFFSET); + addr_hit[ 41] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_1_OFFSET); + addr_hit[ 42] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_2_OFFSET); + addr_hit[ 43] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_3_OFFSET); + addr_hit[ 44] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_4_OFFSET); + addr_hit[ 45] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_5_OFFSET); + addr_hit[ 46] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_6_OFFSET); + addr_hit[ 47] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_7_OFFSET); + addr_hit[ 48] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_8_OFFSET); + addr_hit[ 49] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_9_OFFSET); + addr_hit[ 50] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_10_OFFSET); + addr_hit[ 51] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_11_OFFSET); + addr_hit[ 52] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_12_OFFSET); + addr_hit[ 53] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_13_OFFSET); + addr_hit[ 54] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_14_OFFSET); + addr_hit[ 55] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_15_OFFSET); + addr_hit[ 56] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_16_OFFSET); + addr_hit[ 57] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_17_OFFSET); + addr_hit[ 58] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_18_OFFSET); + addr_hit[ 59] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_19_OFFSET); + addr_hit[ 60] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_20_OFFSET); + addr_hit[ 61] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_21_OFFSET); + addr_hit[ 62] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_22_OFFSET); + addr_hit[ 63] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_23_OFFSET); + addr_hit[ 64] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_24_OFFSET); + addr_hit[ 65] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_25_OFFSET); + addr_hit[ 66] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_26_OFFSET); + addr_hit[ 67] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_27_OFFSET); + addr_hit[ 68] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_28_OFFSET); + addr_hit[ 69] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_29_OFFSET); + addr_hit[ 70] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_30_OFFSET); + addr_hit[ 71] = (reg_addr == AC_RANGE_CHECK_RANGE_BASE_31_OFFSET); + addr_hit[ 72] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_0_OFFSET); + addr_hit[ 73] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_1_OFFSET); + addr_hit[ 74] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_2_OFFSET); + addr_hit[ 75] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_3_OFFSET); + addr_hit[ 76] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_4_OFFSET); + addr_hit[ 77] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_5_OFFSET); + addr_hit[ 78] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_6_OFFSET); + addr_hit[ 79] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_7_OFFSET); + addr_hit[ 80] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_8_OFFSET); + addr_hit[ 81] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_9_OFFSET); + addr_hit[ 82] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_10_OFFSET); + addr_hit[ 83] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_11_OFFSET); + addr_hit[ 84] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_12_OFFSET); + addr_hit[ 85] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_13_OFFSET); + addr_hit[ 86] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_14_OFFSET); + addr_hit[ 87] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_15_OFFSET); + addr_hit[ 88] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_16_OFFSET); + addr_hit[ 89] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_17_OFFSET); + addr_hit[ 90] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_18_OFFSET); + addr_hit[ 91] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_19_OFFSET); + addr_hit[ 92] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_20_OFFSET); + addr_hit[ 93] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_21_OFFSET); + addr_hit[ 94] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_22_OFFSET); + addr_hit[ 95] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_23_OFFSET); + addr_hit[ 96] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_24_OFFSET); + addr_hit[ 97] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_25_OFFSET); + addr_hit[ 98] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_26_OFFSET); + addr_hit[ 99] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_27_OFFSET); + addr_hit[100] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_28_OFFSET); + addr_hit[101] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_29_OFFSET); + addr_hit[102] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_30_OFFSET); + addr_hit[103] = (reg_addr == AC_RANGE_CHECK_RANGE_LIMIT_31_OFFSET); + addr_hit[104] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_0_OFFSET); + addr_hit[105] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_1_OFFSET); + addr_hit[106] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_2_OFFSET); + addr_hit[107] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_3_OFFSET); + addr_hit[108] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_4_OFFSET); + addr_hit[109] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_5_OFFSET); + addr_hit[110] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_6_OFFSET); + addr_hit[111] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_7_OFFSET); + addr_hit[112] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_8_OFFSET); + addr_hit[113] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_9_OFFSET); + addr_hit[114] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_10_OFFSET); + addr_hit[115] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_11_OFFSET); + addr_hit[116] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_12_OFFSET); + addr_hit[117] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_13_OFFSET); + addr_hit[118] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_14_OFFSET); + addr_hit[119] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_15_OFFSET); + addr_hit[120] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_16_OFFSET); + addr_hit[121] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_17_OFFSET); + addr_hit[122] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_18_OFFSET); + addr_hit[123] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_19_OFFSET); + addr_hit[124] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_20_OFFSET); + addr_hit[125] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_21_OFFSET); + addr_hit[126] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_22_OFFSET); + addr_hit[127] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_23_OFFSET); + addr_hit[128] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_24_OFFSET); + addr_hit[129] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_25_OFFSET); + addr_hit[130] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_26_OFFSET); + addr_hit[131] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_27_OFFSET); + addr_hit[132] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_28_OFFSET); + addr_hit[133] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_29_OFFSET); + addr_hit[134] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_30_OFFSET); + addr_hit[135] = (reg_addr == AC_RANGE_CHECK_RANGE_ATTR_31_OFFSET); + addr_hit[136] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_0_OFFSET); + addr_hit[137] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_1_OFFSET); + addr_hit[138] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_2_OFFSET); + addr_hit[139] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_3_OFFSET); + addr_hit[140] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_4_OFFSET); + addr_hit[141] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_5_OFFSET); + addr_hit[142] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_6_OFFSET); + addr_hit[143] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_7_OFFSET); + addr_hit[144] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_8_OFFSET); + addr_hit[145] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_9_OFFSET); + addr_hit[146] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_10_OFFSET); + addr_hit[147] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_11_OFFSET); + addr_hit[148] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_12_OFFSET); + addr_hit[149] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_13_OFFSET); + addr_hit[150] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_14_OFFSET); + addr_hit[151] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_15_OFFSET); + addr_hit[152] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_16_OFFSET); + addr_hit[153] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_17_OFFSET); + addr_hit[154] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_18_OFFSET); + addr_hit[155] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_19_OFFSET); + addr_hit[156] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_20_OFFSET); + addr_hit[157] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_21_OFFSET); + addr_hit[158] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_22_OFFSET); + addr_hit[159] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_23_OFFSET); + addr_hit[160] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_24_OFFSET); + addr_hit[161] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_25_OFFSET); + addr_hit[162] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_26_OFFSET); + addr_hit[163] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_27_OFFSET); + addr_hit[164] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_28_OFFSET); + addr_hit[165] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_29_OFFSET); + addr_hit[166] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_30_OFFSET); + addr_hit[167] = (reg_addr == AC_RANGE_CHECK_RANGE_RACL_POLICY_SHADOWED_31_OFFSET); + + if (EnableRacl) begin : gen_racl_hit + for (int unsigned slice_idx = 0; slice_idx < 168; slice_idx++) begin + racl_addr_hit_read[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].read_perm + & racl_role_vec)); + racl_addr_hit_write[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].write_perm + & racl_role_vec)); + end + end else begin : gen_no_racl + racl_addr_hit_read = addr_hit; + racl_addr_hit_write = addr_hit; + end + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + // A valid address hit, access, but failed the RACL check + assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) | + (reg_we & ~|racl_addr_hit_write)); + assign racl_error_o.request_address = top_pkg::TL_AW'(reg_addr); + assign racl_error_o.racl_role = racl_role; + assign racl_error_o.overflow = 1'b0; + + if (EnableRacl) begin : gen_racl_log + assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd); + assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get; + end else begin : gen_no_racl_log + assign racl_error_o.ctn_uid = '0; + assign racl_error_o.read_access = 1'b0; + end + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((racl_addr_hit_write[ 0] & (|(AC_RANGE_CHECK_PERMIT[ 0] & ~reg_be))) | + (racl_addr_hit_write[ 1] & (|(AC_RANGE_CHECK_PERMIT[ 1] & ~reg_be))) | + (racl_addr_hit_write[ 2] & (|(AC_RANGE_CHECK_PERMIT[ 2] & ~reg_be))) | + (racl_addr_hit_write[ 3] & (|(AC_RANGE_CHECK_PERMIT[ 3] & ~reg_be))) | + (racl_addr_hit_write[ 4] & (|(AC_RANGE_CHECK_PERMIT[ 4] & ~reg_be))) | + (racl_addr_hit_write[ 5] & (|(AC_RANGE_CHECK_PERMIT[ 5] & ~reg_be))) | + (racl_addr_hit_write[ 6] & (|(AC_RANGE_CHECK_PERMIT[ 6] & ~reg_be))) | + (racl_addr_hit_write[ 7] & (|(AC_RANGE_CHECK_PERMIT[ 7] & ~reg_be))) | + (racl_addr_hit_write[ 8] & (|(AC_RANGE_CHECK_PERMIT[ 8] & ~reg_be))) | + (racl_addr_hit_write[ 9] & (|(AC_RANGE_CHECK_PERMIT[ 9] & ~reg_be))) | + (racl_addr_hit_write[ 10] & (|(AC_RANGE_CHECK_PERMIT[ 10] & ~reg_be))) | + (racl_addr_hit_write[ 11] & (|(AC_RANGE_CHECK_PERMIT[ 11] & ~reg_be))) | + (racl_addr_hit_write[ 12] & (|(AC_RANGE_CHECK_PERMIT[ 12] & ~reg_be))) | + (racl_addr_hit_write[ 13] & (|(AC_RANGE_CHECK_PERMIT[ 13] & ~reg_be))) | + (racl_addr_hit_write[ 14] & (|(AC_RANGE_CHECK_PERMIT[ 14] & ~reg_be))) | + (racl_addr_hit_write[ 15] & (|(AC_RANGE_CHECK_PERMIT[ 15] & ~reg_be))) | + (racl_addr_hit_write[ 16] & (|(AC_RANGE_CHECK_PERMIT[ 16] & ~reg_be))) | + (racl_addr_hit_write[ 17] & (|(AC_RANGE_CHECK_PERMIT[ 17] & ~reg_be))) | + (racl_addr_hit_write[ 18] & (|(AC_RANGE_CHECK_PERMIT[ 18] & ~reg_be))) | + (racl_addr_hit_write[ 19] & (|(AC_RANGE_CHECK_PERMIT[ 19] & ~reg_be))) | + (racl_addr_hit_write[ 20] & (|(AC_RANGE_CHECK_PERMIT[ 20] & ~reg_be))) | + (racl_addr_hit_write[ 21] & (|(AC_RANGE_CHECK_PERMIT[ 21] & ~reg_be))) | + (racl_addr_hit_write[ 22] & (|(AC_RANGE_CHECK_PERMIT[ 22] & ~reg_be))) | + (racl_addr_hit_write[ 23] & (|(AC_RANGE_CHECK_PERMIT[ 23] & ~reg_be))) | + (racl_addr_hit_write[ 24] & (|(AC_RANGE_CHECK_PERMIT[ 24] & ~reg_be))) | + (racl_addr_hit_write[ 25] & (|(AC_RANGE_CHECK_PERMIT[ 25] & ~reg_be))) | + (racl_addr_hit_write[ 26] & (|(AC_RANGE_CHECK_PERMIT[ 26] & ~reg_be))) | + (racl_addr_hit_write[ 27] & (|(AC_RANGE_CHECK_PERMIT[ 27] & ~reg_be))) | + (racl_addr_hit_write[ 28] & (|(AC_RANGE_CHECK_PERMIT[ 28] & ~reg_be))) | + (racl_addr_hit_write[ 29] & (|(AC_RANGE_CHECK_PERMIT[ 29] & ~reg_be))) | + (racl_addr_hit_write[ 30] & (|(AC_RANGE_CHECK_PERMIT[ 30] & ~reg_be))) | + (racl_addr_hit_write[ 31] & (|(AC_RANGE_CHECK_PERMIT[ 31] & ~reg_be))) | + (racl_addr_hit_write[ 32] & (|(AC_RANGE_CHECK_PERMIT[ 32] & ~reg_be))) | + (racl_addr_hit_write[ 33] & (|(AC_RANGE_CHECK_PERMIT[ 33] & ~reg_be))) | + (racl_addr_hit_write[ 34] & (|(AC_RANGE_CHECK_PERMIT[ 34] & ~reg_be))) | + (racl_addr_hit_write[ 35] & (|(AC_RANGE_CHECK_PERMIT[ 35] & ~reg_be))) | + (racl_addr_hit_write[ 36] & (|(AC_RANGE_CHECK_PERMIT[ 36] & ~reg_be))) | + (racl_addr_hit_write[ 37] & (|(AC_RANGE_CHECK_PERMIT[ 37] & ~reg_be))) | + (racl_addr_hit_write[ 38] & (|(AC_RANGE_CHECK_PERMIT[ 38] & ~reg_be))) | + (racl_addr_hit_write[ 39] & (|(AC_RANGE_CHECK_PERMIT[ 39] & ~reg_be))) | + (racl_addr_hit_write[ 40] & (|(AC_RANGE_CHECK_PERMIT[ 40] & ~reg_be))) | + (racl_addr_hit_write[ 41] & (|(AC_RANGE_CHECK_PERMIT[ 41] & ~reg_be))) | + (racl_addr_hit_write[ 42] & (|(AC_RANGE_CHECK_PERMIT[ 42] & ~reg_be))) | + (racl_addr_hit_write[ 43] & (|(AC_RANGE_CHECK_PERMIT[ 43] & ~reg_be))) | + (racl_addr_hit_write[ 44] & (|(AC_RANGE_CHECK_PERMIT[ 44] & ~reg_be))) | + (racl_addr_hit_write[ 45] & (|(AC_RANGE_CHECK_PERMIT[ 45] & ~reg_be))) | + (racl_addr_hit_write[ 46] & (|(AC_RANGE_CHECK_PERMIT[ 46] & ~reg_be))) | + (racl_addr_hit_write[ 47] & (|(AC_RANGE_CHECK_PERMIT[ 47] & ~reg_be))) | + (racl_addr_hit_write[ 48] & (|(AC_RANGE_CHECK_PERMIT[ 48] & ~reg_be))) | + (racl_addr_hit_write[ 49] & (|(AC_RANGE_CHECK_PERMIT[ 49] & ~reg_be))) | + (racl_addr_hit_write[ 50] & (|(AC_RANGE_CHECK_PERMIT[ 50] & ~reg_be))) | + (racl_addr_hit_write[ 51] & (|(AC_RANGE_CHECK_PERMIT[ 51] & ~reg_be))) | + (racl_addr_hit_write[ 52] & (|(AC_RANGE_CHECK_PERMIT[ 52] & ~reg_be))) | + (racl_addr_hit_write[ 53] & (|(AC_RANGE_CHECK_PERMIT[ 53] & ~reg_be))) | + (racl_addr_hit_write[ 54] & (|(AC_RANGE_CHECK_PERMIT[ 54] & ~reg_be))) | + (racl_addr_hit_write[ 55] & (|(AC_RANGE_CHECK_PERMIT[ 55] & ~reg_be))) | + (racl_addr_hit_write[ 56] & (|(AC_RANGE_CHECK_PERMIT[ 56] & ~reg_be))) | + (racl_addr_hit_write[ 57] & (|(AC_RANGE_CHECK_PERMIT[ 57] & ~reg_be))) | + (racl_addr_hit_write[ 58] & (|(AC_RANGE_CHECK_PERMIT[ 58] & ~reg_be))) | + (racl_addr_hit_write[ 59] & (|(AC_RANGE_CHECK_PERMIT[ 59] & ~reg_be))) | + (racl_addr_hit_write[ 60] & (|(AC_RANGE_CHECK_PERMIT[ 60] & ~reg_be))) | + (racl_addr_hit_write[ 61] & (|(AC_RANGE_CHECK_PERMIT[ 61] & ~reg_be))) | + (racl_addr_hit_write[ 62] & (|(AC_RANGE_CHECK_PERMIT[ 62] & ~reg_be))) | + (racl_addr_hit_write[ 63] & (|(AC_RANGE_CHECK_PERMIT[ 63] & ~reg_be))) | + (racl_addr_hit_write[ 64] & (|(AC_RANGE_CHECK_PERMIT[ 64] & ~reg_be))) | + (racl_addr_hit_write[ 65] & (|(AC_RANGE_CHECK_PERMIT[ 65] & ~reg_be))) | + (racl_addr_hit_write[ 66] & (|(AC_RANGE_CHECK_PERMIT[ 66] & ~reg_be))) | + (racl_addr_hit_write[ 67] & (|(AC_RANGE_CHECK_PERMIT[ 67] & ~reg_be))) | + (racl_addr_hit_write[ 68] & (|(AC_RANGE_CHECK_PERMIT[ 68] & ~reg_be))) | + (racl_addr_hit_write[ 69] & (|(AC_RANGE_CHECK_PERMIT[ 69] & ~reg_be))) | + (racl_addr_hit_write[ 70] & (|(AC_RANGE_CHECK_PERMIT[ 70] & ~reg_be))) | + (racl_addr_hit_write[ 71] & (|(AC_RANGE_CHECK_PERMIT[ 71] & ~reg_be))) | + (racl_addr_hit_write[ 72] & (|(AC_RANGE_CHECK_PERMIT[ 72] & ~reg_be))) | + (racl_addr_hit_write[ 73] & (|(AC_RANGE_CHECK_PERMIT[ 73] & ~reg_be))) | + (racl_addr_hit_write[ 74] & (|(AC_RANGE_CHECK_PERMIT[ 74] & ~reg_be))) | + (racl_addr_hit_write[ 75] & (|(AC_RANGE_CHECK_PERMIT[ 75] & ~reg_be))) | + (racl_addr_hit_write[ 76] & (|(AC_RANGE_CHECK_PERMIT[ 76] & ~reg_be))) | + (racl_addr_hit_write[ 77] & (|(AC_RANGE_CHECK_PERMIT[ 77] & ~reg_be))) | + (racl_addr_hit_write[ 78] & (|(AC_RANGE_CHECK_PERMIT[ 78] & ~reg_be))) | + (racl_addr_hit_write[ 79] & (|(AC_RANGE_CHECK_PERMIT[ 79] & ~reg_be))) | + (racl_addr_hit_write[ 80] & (|(AC_RANGE_CHECK_PERMIT[ 80] & ~reg_be))) | + (racl_addr_hit_write[ 81] & (|(AC_RANGE_CHECK_PERMIT[ 81] & ~reg_be))) | + (racl_addr_hit_write[ 82] & (|(AC_RANGE_CHECK_PERMIT[ 82] & ~reg_be))) | + (racl_addr_hit_write[ 83] & (|(AC_RANGE_CHECK_PERMIT[ 83] & ~reg_be))) | + (racl_addr_hit_write[ 84] & (|(AC_RANGE_CHECK_PERMIT[ 84] & ~reg_be))) | + (racl_addr_hit_write[ 85] & (|(AC_RANGE_CHECK_PERMIT[ 85] & ~reg_be))) | + (racl_addr_hit_write[ 86] & (|(AC_RANGE_CHECK_PERMIT[ 86] & ~reg_be))) | + (racl_addr_hit_write[ 87] & (|(AC_RANGE_CHECK_PERMIT[ 87] & ~reg_be))) | + (racl_addr_hit_write[ 88] & (|(AC_RANGE_CHECK_PERMIT[ 88] & ~reg_be))) | + (racl_addr_hit_write[ 89] & (|(AC_RANGE_CHECK_PERMIT[ 89] & ~reg_be))) | + (racl_addr_hit_write[ 90] & (|(AC_RANGE_CHECK_PERMIT[ 90] & ~reg_be))) | + (racl_addr_hit_write[ 91] & (|(AC_RANGE_CHECK_PERMIT[ 91] & ~reg_be))) | + (racl_addr_hit_write[ 92] & (|(AC_RANGE_CHECK_PERMIT[ 92] & ~reg_be))) | + (racl_addr_hit_write[ 93] & (|(AC_RANGE_CHECK_PERMIT[ 93] & ~reg_be))) | + (racl_addr_hit_write[ 94] & (|(AC_RANGE_CHECK_PERMIT[ 94] & ~reg_be))) | + (racl_addr_hit_write[ 95] & (|(AC_RANGE_CHECK_PERMIT[ 95] & ~reg_be))) | + (racl_addr_hit_write[ 96] & (|(AC_RANGE_CHECK_PERMIT[ 96] & ~reg_be))) | + (racl_addr_hit_write[ 97] & (|(AC_RANGE_CHECK_PERMIT[ 97] & ~reg_be))) | + (racl_addr_hit_write[ 98] & (|(AC_RANGE_CHECK_PERMIT[ 98] & ~reg_be))) | + (racl_addr_hit_write[ 99] & (|(AC_RANGE_CHECK_PERMIT[ 99] & ~reg_be))) | + (racl_addr_hit_write[100] & (|(AC_RANGE_CHECK_PERMIT[100] & ~reg_be))) | + (racl_addr_hit_write[101] & (|(AC_RANGE_CHECK_PERMIT[101] & ~reg_be))) | + (racl_addr_hit_write[102] & (|(AC_RANGE_CHECK_PERMIT[102] & ~reg_be))) | + (racl_addr_hit_write[103] & (|(AC_RANGE_CHECK_PERMIT[103] & ~reg_be))) | + (racl_addr_hit_write[104] & (|(AC_RANGE_CHECK_PERMIT[104] & ~reg_be))) | + (racl_addr_hit_write[105] & (|(AC_RANGE_CHECK_PERMIT[105] & ~reg_be))) | + (racl_addr_hit_write[106] & (|(AC_RANGE_CHECK_PERMIT[106] & ~reg_be))) | + (racl_addr_hit_write[107] & (|(AC_RANGE_CHECK_PERMIT[107] & ~reg_be))) | + (racl_addr_hit_write[108] & (|(AC_RANGE_CHECK_PERMIT[108] & ~reg_be))) | + (racl_addr_hit_write[109] & (|(AC_RANGE_CHECK_PERMIT[109] & ~reg_be))) | + (racl_addr_hit_write[110] & (|(AC_RANGE_CHECK_PERMIT[110] & ~reg_be))) | + (racl_addr_hit_write[111] & (|(AC_RANGE_CHECK_PERMIT[111] & ~reg_be))) | + (racl_addr_hit_write[112] & (|(AC_RANGE_CHECK_PERMIT[112] & ~reg_be))) | + (racl_addr_hit_write[113] & (|(AC_RANGE_CHECK_PERMIT[113] & ~reg_be))) | + (racl_addr_hit_write[114] & (|(AC_RANGE_CHECK_PERMIT[114] & ~reg_be))) | + (racl_addr_hit_write[115] & (|(AC_RANGE_CHECK_PERMIT[115] & ~reg_be))) | + (racl_addr_hit_write[116] & (|(AC_RANGE_CHECK_PERMIT[116] & ~reg_be))) | + (racl_addr_hit_write[117] & (|(AC_RANGE_CHECK_PERMIT[117] & ~reg_be))) | + (racl_addr_hit_write[118] & (|(AC_RANGE_CHECK_PERMIT[118] & ~reg_be))) | + (racl_addr_hit_write[119] & (|(AC_RANGE_CHECK_PERMIT[119] & ~reg_be))) | + (racl_addr_hit_write[120] & (|(AC_RANGE_CHECK_PERMIT[120] & ~reg_be))) | + (racl_addr_hit_write[121] & (|(AC_RANGE_CHECK_PERMIT[121] & ~reg_be))) | + (racl_addr_hit_write[122] & (|(AC_RANGE_CHECK_PERMIT[122] & ~reg_be))) | + (racl_addr_hit_write[123] & (|(AC_RANGE_CHECK_PERMIT[123] & ~reg_be))) | + (racl_addr_hit_write[124] & (|(AC_RANGE_CHECK_PERMIT[124] & ~reg_be))) | + (racl_addr_hit_write[125] & (|(AC_RANGE_CHECK_PERMIT[125] & ~reg_be))) | + (racl_addr_hit_write[126] & (|(AC_RANGE_CHECK_PERMIT[126] & ~reg_be))) | + (racl_addr_hit_write[127] & (|(AC_RANGE_CHECK_PERMIT[127] & ~reg_be))) | + (racl_addr_hit_write[128] & (|(AC_RANGE_CHECK_PERMIT[128] & ~reg_be))) | + (racl_addr_hit_write[129] & (|(AC_RANGE_CHECK_PERMIT[129] & ~reg_be))) | + (racl_addr_hit_write[130] & (|(AC_RANGE_CHECK_PERMIT[130] & ~reg_be))) | + (racl_addr_hit_write[131] & (|(AC_RANGE_CHECK_PERMIT[131] & ~reg_be))) | + (racl_addr_hit_write[132] & (|(AC_RANGE_CHECK_PERMIT[132] & ~reg_be))) | + (racl_addr_hit_write[133] & (|(AC_RANGE_CHECK_PERMIT[133] & ~reg_be))) | + (racl_addr_hit_write[134] & (|(AC_RANGE_CHECK_PERMIT[134] & ~reg_be))) | + (racl_addr_hit_write[135] & (|(AC_RANGE_CHECK_PERMIT[135] & ~reg_be))) | + (racl_addr_hit_write[136] & (|(AC_RANGE_CHECK_PERMIT[136] & ~reg_be))) | + (racl_addr_hit_write[137] & (|(AC_RANGE_CHECK_PERMIT[137] & ~reg_be))) | + (racl_addr_hit_write[138] & (|(AC_RANGE_CHECK_PERMIT[138] & ~reg_be))) | + (racl_addr_hit_write[139] & (|(AC_RANGE_CHECK_PERMIT[139] & ~reg_be))) | + (racl_addr_hit_write[140] & (|(AC_RANGE_CHECK_PERMIT[140] & ~reg_be))) | + (racl_addr_hit_write[141] & (|(AC_RANGE_CHECK_PERMIT[141] & ~reg_be))) | + (racl_addr_hit_write[142] & (|(AC_RANGE_CHECK_PERMIT[142] & ~reg_be))) | + (racl_addr_hit_write[143] & (|(AC_RANGE_CHECK_PERMIT[143] & ~reg_be))) | + (racl_addr_hit_write[144] & (|(AC_RANGE_CHECK_PERMIT[144] & ~reg_be))) | + (racl_addr_hit_write[145] & (|(AC_RANGE_CHECK_PERMIT[145] & ~reg_be))) | + (racl_addr_hit_write[146] & (|(AC_RANGE_CHECK_PERMIT[146] & ~reg_be))) | + (racl_addr_hit_write[147] & (|(AC_RANGE_CHECK_PERMIT[147] & ~reg_be))) | + (racl_addr_hit_write[148] & (|(AC_RANGE_CHECK_PERMIT[148] & ~reg_be))) | + (racl_addr_hit_write[149] & (|(AC_RANGE_CHECK_PERMIT[149] & ~reg_be))) | + (racl_addr_hit_write[150] & (|(AC_RANGE_CHECK_PERMIT[150] & ~reg_be))) | + (racl_addr_hit_write[151] & (|(AC_RANGE_CHECK_PERMIT[151] & ~reg_be))) | + (racl_addr_hit_write[152] & (|(AC_RANGE_CHECK_PERMIT[152] & ~reg_be))) | + (racl_addr_hit_write[153] & (|(AC_RANGE_CHECK_PERMIT[153] & ~reg_be))) | + (racl_addr_hit_write[154] & (|(AC_RANGE_CHECK_PERMIT[154] & ~reg_be))) | + (racl_addr_hit_write[155] & (|(AC_RANGE_CHECK_PERMIT[155] & ~reg_be))) | + (racl_addr_hit_write[156] & (|(AC_RANGE_CHECK_PERMIT[156] & ~reg_be))) | + (racl_addr_hit_write[157] & (|(AC_RANGE_CHECK_PERMIT[157] & ~reg_be))) | + (racl_addr_hit_write[158] & (|(AC_RANGE_CHECK_PERMIT[158] & ~reg_be))) | + (racl_addr_hit_write[159] & (|(AC_RANGE_CHECK_PERMIT[159] & ~reg_be))) | + (racl_addr_hit_write[160] & (|(AC_RANGE_CHECK_PERMIT[160] & ~reg_be))) | + (racl_addr_hit_write[161] & (|(AC_RANGE_CHECK_PERMIT[161] & ~reg_be))) | + (racl_addr_hit_write[162] & (|(AC_RANGE_CHECK_PERMIT[162] & ~reg_be))) | + (racl_addr_hit_write[163] & (|(AC_RANGE_CHECK_PERMIT[163] & ~reg_be))) | + (racl_addr_hit_write[164] & (|(AC_RANGE_CHECK_PERMIT[164] & ~reg_be))) | + (racl_addr_hit_write[165] & (|(AC_RANGE_CHECK_PERMIT[165] & ~reg_be))) | + (racl_addr_hit_write[166] & (|(AC_RANGE_CHECK_PERMIT[166] & ~reg_be))) | + (racl_addr_hit_write[167] & (|(AC_RANGE_CHECK_PERMIT[167] & ~reg_be))))); + end + + // Generate write-enables + assign intr_enable_we = racl_addr_hit_write[1] & reg_we & !reg_error; + + assign intr_enable_wd = reg_wdata[0]; + assign intr_test_we = racl_addr_hit_write[2] & reg_we & !reg_error; + + assign intr_test_wd = reg_wdata[0]; + assign alert_test_we = racl_addr_hit_write[3] & reg_we & !reg_error; + + assign alert_test_recov_ctrl_update_err_wd = reg_wdata[0]; + + assign alert_test_fatal_fault_wd = reg_wdata[1]; + assign alert_status_re = racl_addr_hit_read[4] & reg_re & !reg_error; + + assign alert_status_shadowed_update_err_wd = '1; + assign log_config_we = racl_addr_hit_write[5] & reg_we & !reg_error; + + assign log_config_log_enable_wd = reg_wdata[0]; + + assign log_config_log_clear_wd = reg_wdata[1]; + + assign log_config_deny_cnt_threshold_wd = reg_wdata[9:2]; + assign range_regwen_0_we = racl_addr_hit_write[8] & reg_we & !reg_error; + + assign range_regwen_0_wd = reg_wdata[3:0]; + assign range_regwen_1_we = racl_addr_hit_write[9] & reg_we & !reg_error; + + assign range_regwen_1_wd = reg_wdata[3:0]; + assign range_regwen_2_we = racl_addr_hit_write[10] & reg_we & !reg_error; + + assign range_regwen_2_wd = reg_wdata[3:0]; + assign range_regwen_3_we = racl_addr_hit_write[11] & reg_we & !reg_error; + + assign range_regwen_3_wd = reg_wdata[3:0]; + assign range_regwen_4_we = racl_addr_hit_write[12] & reg_we & !reg_error; + + assign range_regwen_4_wd = reg_wdata[3:0]; + assign range_regwen_5_we = racl_addr_hit_write[13] & reg_we & !reg_error; + + assign range_regwen_5_wd = reg_wdata[3:0]; + assign range_regwen_6_we = racl_addr_hit_write[14] & reg_we & !reg_error; + + assign range_regwen_6_wd = reg_wdata[3:0]; + assign range_regwen_7_we = racl_addr_hit_write[15] & reg_we & !reg_error; + + assign range_regwen_7_wd = reg_wdata[3:0]; + assign range_regwen_8_we = racl_addr_hit_write[16] & reg_we & !reg_error; + + assign range_regwen_8_wd = reg_wdata[3:0]; + assign range_regwen_9_we = racl_addr_hit_write[17] & reg_we & !reg_error; + + assign range_regwen_9_wd = reg_wdata[3:0]; + assign range_regwen_10_we = racl_addr_hit_write[18] & reg_we & !reg_error; + + assign range_regwen_10_wd = reg_wdata[3:0]; + assign range_regwen_11_we = racl_addr_hit_write[19] & reg_we & !reg_error; + + assign range_regwen_11_wd = reg_wdata[3:0]; + assign range_regwen_12_we = racl_addr_hit_write[20] & reg_we & !reg_error; + + assign range_regwen_12_wd = reg_wdata[3:0]; + assign range_regwen_13_we = racl_addr_hit_write[21] & reg_we & !reg_error; + + assign range_regwen_13_wd = reg_wdata[3:0]; + assign range_regwen_14_we = racl_addr_hit_write[22] & reg_we & !reg_error; + + assign range_regwen_14_wd = reg_wdata[3:0]; + assign range_regwen_15_we = racl_addr_hit_write[23] & reg_we & !reg_error; + + assign range_regwen_15_wd = reg_wdata[3:0]; + assign range_regwen_16_we = racl_addr_hit_write[24] & reg_we & !reg_error; + + assign range_regwen_16_wd = reg_wdata[3:0]; + assign range_regwen_17_we = racl_addr_hit_write[25] & reg_we & !reg_error; + + assign range_regwen_17_wd = reg_wdata[3:0]; + assign range_regwen_18_we = racl_addr_hit_write[26] & reg_we & !reg_error; + + assign range_regwen_18_wd = reg_wdata[3:0]; + assign range_regwen_19_we = racl_addr_hit_write[27] & reg_we & !reg_error; + + assign range_regwen_19_wd = reg_wdata[3:0]; + assign range_regwen_20_we = racl_addr_hit_write[28] & reg_we & !reg_error; + + assign range_regwen_20_wd = reg_wdata[3:0]; + assign range_regwen_21_we = racl_addr_hit_write[29] & reg_we & !reg_error; + + assign range_regwen_21_wd = reg_wdata[3:0]; + assign range_regwen_22_we = racl_addr_hit_write[30] & reg_we & !reg_error; + + assign range_regwen_22_wd = reg_wdata[3:0]; + assign range_regwen_23_we = racl_addr_hit_write[31] & reg_we & !reg_error; + + assign range_regwen_23_wd = reg_wdata[3:0]; + assign range_regwen_24_we = racl_addr_hit_write[32] & reg_we & !reg_error; + + assign range_regwen_24_wd = reg_wdata[3:0]; + assign range_regwen_25_we = racl_addr_hit_write[33] & reg_we & !reg_error; + + assign range_regwen_25_wd = reg_wdata[3:0]; + assign range_regwen_26_we = racl_addr_hit_write[34] & reg_we & !reg_error; + + assign range_regwen_26_wd = reg_wdata[3:0]; + assign range_regwen_27_we = racl_addr_hit_write[35] & reg_we & !reg_error; + + assign range_regwen_27_wd = reg_wdata[3:0]; + assign range_regwen_28_we = racl_addr_hit_write[36] & reg_we & !reg_error; + + assign range_regwen_28_wd = reg_wdata[3:0]; + assign range_regwen_29_we = racl_addr_hit_write[37] & reg_we & !reg_error; + + assign range_regwen_29_wd = reg_wdata[3:0]; + assign range_regwen_30_we = racl_addr_hit_write[38] & reg_we & !reg_error; + + assign range_regwen_30_wd = reg_wdata[3:0]; + assign range_regwen_31_we = racl_addr_hit_write[39] & reg_we & !reg_error; + + assign range_regwen_31_wd = reg_wdata[3:0]; + assign range_base_0_we = racl_addr_hit_write[40] & reg_we & !reg_error; + + assign range_base_0_wd = reg_wdata[31:2]; + assign range_base_1_we = racl_addr_hit_write[41] & reg_we & !reg_error; + + assign range_base_1_wd = reg_wdata[31:2]; + assign range_base_2_we = racl_addr_hit_write[42] & reg_we & !reg_error; + + assign range_base_2_wd = reg_wdata[31:2]; + assign range_base_3_we = racl_addr_hit_write[43] & reg_we & !reg_error; + + assign range_base_3_wd = reg_wdata[31:2]; + assign range_base_4_we = racl_addr_hit_write[44] & reg_we & !reg_error; + + assign range_base_4_wd = reg_wdata[31:2]; + assign range_base_5_we = racl_addr_hit_write[45] & reg_we & !reg_error; + + assign range_base_5_wd = reg_wdata[31:2]; + assign range_base_6_we = racl_addr_hit_write[46] & reg_we & !reg_error; + + assign range_base_6_wd = reg_wdata[31:2]; + assign range_base_7_we = racl_addr_hit_write[47] & reg_we & !reg_error; + + assign range_base_7_wd = reg_wdata[31:2]; + assign range_base_8_we = racl_addr_hit_write[48] & reg_we & !reg_error; + + assign range_base_8_wd = reg_wdata[31:2]; + assign range_base_9_we = racl_addr_hit_write[49] & reg_we & !reg_error; + + assign range_base_9_wd = reg_wdata[31:2]; + assign range_base_10_we = racl_addr_hit_write[50] & reg_we & !reg_error; + + assign range_base_10_wd = reg_wdata[31:2]; + assign range_base_11_we = racl_addr_hit_write[51] & reg_we & !reg_error; + + assign range_base_11_wd = reg_wdata[31:2]; + assign range_base_12_we = racl_addr_hit_write[52] & reg_we & !reg_error; + + assign range_base_12_wd = reg_wdata[31:2]; + assign range_base_13_we = racl_addr_hit_write[53] & reg_we & !reg_error; + + assign range_base_13_wd = reg_wdata[31:2]; + assign range_base_14_we = racl_addr_hit_write[54] & reg_we & !reg_error; + + assign range_base_14_wd = reg_wdata[31:2]; + assign range_base_15_we = racl_addr_hit_write[55] & reg_we & !reg_error; + + assign range_base_15_wd = reg_wdata[31:2]; + assign range_base_16_we = racl_addr_hit_write[56] & reg_we & !reg_error; + + assign range_base_16_wd = reg_wdata[31:2]; + assign range_base_17_we = racl_addr_hit_write[57] & reg_we & !reg_error; + + assign range_base_17_wd = reg_wdata[31:2]; + assign range_base_18_we = racl_addr_hit_write[58] & reg_we & !reg_error; + + assign range_base_18_wd = reg_wdata[31:2]; + assign range_base_19_we = racl_addr_hit_write[59] & reg_we & !reg_error; + + assign range_base_19_wd = reg_wdata[31:2]; + assign range_base_20_we = racl_addr_hit_write[60] & reg_we & !reg_error; + + assign range_base_20_wd = reg_wdata[31:2]; + assign range_base_21_we = racl_addr_hit_write[61] & reg_we & !reg_error; + + assign range_base_21_wd = reg_wdata[31:2]; + assign range_base_22_we = racl_addr_hit_write[62] & reg_we & !reg_error; + + assign range_base_22_wd = reg_wdata[31:2]; + assign range_base_23_we = racl_addr_hit_write[63] & reg_we & !reg_error; + + assign range_base_23_wd = reg_wdata[31:2]; + assign range_base_24_we = racl_addr_hit_write[64] & reg_we & !reg_error; + + assign range_base_24_wd = reg_wdata[31:2]; + assign range_base_25_we = racl_addr_hit_write[65] & reg_we & !reg_error; + + assign range_base_25_wd = reg_wdata[31:2]; + assign range_base_26_we = racl_addr_hit_write[66] & reg_we & !reg_error; + + assign range_base_26_wd = reg_wdata[31:2]; + assign range_base_27_we = racl_addr_hit_write[67] & reg_we & !reg_error; + + assign range_base_27_wd = reg_wdata[31:2]; + assign range_base_28_we = racl_addr_hit_write[68] & reg_we & !reg_error; + + assign range_base_28_wd = reg_wdata[31:2]; + assign range_base_29_we = racl_addr_hit_write[69] & reg_we & !reg_error; + + assign range_base_29_wd = reg_wdata[31:2]; + assign range_base_30_we = racl_addr_hit_write[70] & reg_we & !reg_error; + + assign range_base_30_wd = reg_wdata[31:2]; + assign range_base_31_we = racl_addr_hit_write[71] & reg_we & !reg_error; + + assign range_base_31_wd = reg_wdata[31:2]; + assign range_limit_0_we = racl_addr_hit_write[72] & reg_we & !reg_error; + + assign range_limit_0_wd = reg_wdata[31:2]; + assign range_limit_1_we = racl_addr_hit_write[73] & reg_we & !reg_error; + + assign range_limit_1_wd = reg_wdata[31:2]; + assign range_limit_2_we = racl_addr_hit_write[74] & reg_we & !reg_error; + + assign range_limit_2_wd = reg_wdata[31:2]; + assign range_limit_3_we = racl_addr_hit_write[75] & reg_we & !reg_error; + + assign range_limit_3_wd = reg_wdata[31:2]; + assign range_limit_4_we = racl_addr_hit_write[76] & reg_we & !reg_error; + + assign range_limit_4_wd = reg_wdata[31:2]; + assign range_limit_5_we = racl_addr_hit_write[77] & reg_we & !reg_error; + + assign range_limit_5_wd = reg_wdata[31:2]; + assign range_limit_6_we = racl_addr_hit_write[78] & reg_we & !reg_error; + + assign range_limit_6_wd = reg_wdata[31:2]; + assign range_limit_7_we = racl_addr_hit_write[79] & reg_we & !reg_error; + + assign range_limit_7_wd = reg_wdata[31:2]; + assign range_limit_8_we = racl_addr_hit_write[80] & reg_we & !reg_error; + + assign range_limit_8_wd = reg_wdata[31:2]; + assign range_limit_9_we = racl_addr_hit_write[81] & reg_we & !reg_error; + + assign range_limit_9_wd = reg_wdata[31:2]; + assign range_limit_10_we = racl_addr_hit_write[82] & reg_we & !reg_error; + + assign range_limit_10_wd = reg_wdata[31:2]; + assign range_limit_11_we = racl_addr_hit_write[83] & reg_we & !reg_error; + + assign range_limit_11_wd = reg_wdata[31:2]; + assign range_limit_12_we = racl_addr_hit_write[84] & reg_we & !reg_error; + + assign range_limit_12_wd = reg_wdata[31:2]; + assign range_limit_13_we = racl_addr_hit_write[85] & reg_we & !reg_error; + + assign range_limit_13_wd = reg_wdata[31:2]; + assign range_limit_14_we = racl_addr_hit_write[86] & reg_we & !reg_error; + + assign range_limit_14_wd = reg_wdata[31:2]; + assign range_limit_15_we = racl_addr_hit_write[87] & reg_we & !reg_error; + + assign range_limit_15_wd = reg_wdata[31:2]; + assign range_limit_16_we = racl_addr_hit_write[88] & reg_we & !reg_error; + + assign range_limit_16_wd = reg_wdata[31:2]; + assign range_limit_17_we = racl_addr_hit_write[89] & reg_we & !reg_error; + + assign range_limit_17_wd = reg_wdata[31:2]; + assign range_limit_18_we = racl_addr_hit_write[90] & reg_we & !reg_error; + + assign range_limit_18_wd = reg_wdata[31:2]; + assign range_limit_19_we = racl_addr_hit_write[91] & reg_we & !reg_error; + + assign range_limit_19_wd = reg_wdata[31:2]; + assign range_limit_20_we = racl_addr_hit_write[92] & reg_we & !reg_error; + + assign range_limit_20_wd = reg_wdata[31:2]; + assign range_limit_21_we = racl_addr_hit_write[93] & reg_we & !reg_error; + + assign range_limit_21_wd = reg_wdata[31:2]; + assign range_limit_22_we = racl_addr_hit_write[94] & reg_we & !reg_error; + + assign range_limit_22_wd = reg_wdata[31:2]; + assign range_limit_23_we = racl_addr_hit_write[95] & reg_we & !reg_error; + + assign range_limit_23_wd = reg_wdata[31:2]; + assign range_limit_24_we = racl_addr_hit_write[96] & reg_we & !reg_error; + + assign range_limit_24_wd = reg_wdata[31:2]; + assign range_limit_25_we = racl_addr_hit_write[97] & reg_we & !reg_error; + + assign range_limit_25_wd = reg_wdata[31:2]; + assign range_limit_26_we = racl_addr_hit_write[98] & reg_we & !reg_error; + + assign range_limit_26_wd = reg_wdata[31:2]; + assign range_limit_27_we = racl_addr_hit_write[99] & reg_we & !reg_error; + + assign range_limit_27_wd = reg_wdata[31:2]; + assign range_limit_28_we = racl_addr_hit_write[100] & reg_we & !reg_error; + + assign range_limit_28_wd = reg_wdata[31:2]; + assign range_limit_29_we = racl_addr_hit_write[101] & reg_we & !reg_error; + + assign range_limit_29_wd = reg_wdata[31:2]; + assign range_limit_30_we = racl_addr_hit_write[102] & reg_we & !reg_error; + + assign range_limit_30_wd = reg_wdata[31:2]; + assign range_limit_31_we = racl_addr_hit_write[103] & reg_we & !reg_error; + + assign range_limit_31_wd = reg_wdata[31:2]; + assign range_attr_0_we = racl_addr_hit_write[104] & reg_we & !reg_error; + + assign range_attr_0_enable_0_wd = reg_wdata[3:0]; + + assign range_attr_0_read_access_0_wd = reg_wdata[7:4]; + + assign range_attr_0_write_access_0_wd = reg_wdata[11:8]; + + assign range_attr_0_execute_access_0_wd = reg_wdata[15:12]; + + assign range_attr_0_log_denied_access_0_wd = reg_wdata[19:16]; + assign range_attr_1_we = racl_addr_hit_write[105] & reg_we & !reg_error; + + assign range_attr_1_enable_1_wd = reg_wdata[3:0]; + + assign range_attr_1_read_access_1_wd = reg_wdata[7:4]; + + assign range_attr_1_write_access_1_wd = reg_wdata[11:8]; + + assign range_attr_1_execute_access_1_wd = reg_wdata[15:12]; + + assign range_attr_1_log_denied_access_1_wd = reg_wdata[19:16]; + assign range_attr_2_we = racl_addr_hit_write[106] & reg_we & !reg_error; + + assign range_attr_2_enable_2_wd = reg_wdata[3:0]; + + assign range_attr_2_read_access_2_wd = reg_wdata[7:4]; + + assign range_attr_2_write_access_2_wd = reg_wdata[11:8]; + + assign range_attr_2_execute_access_2_wd = reg_wdata[15:12]; + + assign range_attr_2_log_denied_access_2_wd = reg_wdata[19:16]; + assign range_attr_3_we = racl_addr_hit_write[107] & reg_we & !reg_error; + + assign range_attr_3_enable_3_wd = reg_wdata[3:0]; + + assign range_attr_3_read_access_3_wd = reg_wdata[7:4]; + + assign range_attr_3_write_access_3_wd = reg_wdata[11:8]; + + assign range_attr_3_execute_access_3_wd = reg_wdata[15:12]; + + assign range_attr_3_log_denied_access_3_wd = reg_wdata[19:16]; + assign range_attr_4_we = racl_addr_hit_write[108] & reg_we & !reg_error; + + assign range_attr_4_enable_4_wd = reg_wdata[3:0]; + + assign range_attr_4_read_access_4_wd = reg_wdata[7:4]; + + assign range_attr_4_write_access_4_wd = reg_wdata[11:8]; + + assign range_attr_4_execute_access_4_wd = reg_wdata[15:12]; + + assign range_attr_4_log_denied_access_4_wd = reg_wdata[19:16]; + assign range_attr_5_we = racl_addr_hit_write[109] & reg_we & !reg_error; + + assign range_attr_5_enable_5_wd = reg_wdata[3:0]; + + assign range_attr_5_read_access_5_wd = reg_wdata[7:4]; + + assign range_attr_5_write_access_5_wd = reg_wdata[11:8]; + + assign range_attr_5_execute_access_5_wd = reg_wdata[15:12]; + + assign range_attr_5_log_denied_access_5_wd = reg_wdata[19:16]; + assign range_attr_6_we = racl_addr_hit_write[110] & reg_we & !reg_error; + + assign range_attr_6_enable_6_wd = reg_wdata[3:0]; + + assign range_attr_6_read_access_6_wd = reg_wdata[7:4]; + + assign range_attr_6_write_access_6_wd = reg_wdata[11:8]; + + assign range_attr_6_execute_access_6_wd = reg_wdata[15:12]; + + assign range_attr_6_log_denied_access_6_wd = reg_wdata[19:16]; + assign range_attr_7_we = racl_addr_hit_write[111] & reg_we & !reg_error; + + assign range_attr_7_enable_7_wd = reg_wdata[3:0]; + + assign range_attr_7_read_access_7_wd = reg_wdata[7:4]; + + assign range_attr_7_write_access_7_wd = reg_wdata[11:8]; + + assign range_attr_7_execute_access_7_wd = reg_wdata[15:12]; + + assign range_attr_7_log_denied_access_7_wd = reg_wdata[19:16]; + assign range_attr_8_we = racl_addr_hit_write[112] & reg_we & !reg_error; + + assign range_attr_8_enable_8_wd = reg_wdata[3:0]; + + assign range_attr_8_read_access_8_wd = reg_wdata[7:4]; + + assign range_attr_8_write_access_8_wd = reg_wdata[11:8]; + + assign range_attr_8_execute_access_8_wd = reg_wdata[15:12]; + + assign range_attr_8_log_denied_access_8_wd = reg_wdata[19:16]; + assign range_attr_9_we = racl_addr_hit_write[113] & reg_we & !reg_error; + + assign range_attr_9_enable_9_wd = reg_wdata[3:0]; + + assign range_attr_9_read_access_9_wd = reg_wdata[7:4]; + + assign range_attr_9_write_access_9_wd = reg_wdata[11:8]; + + assign range_attr_9_execute_access_9_wd = reg_wdata[15:12]; + + assign range_attr_9_log_denied_access_9_wd = reg_wdata[19:16]; + assign range_attr_10_we = racl_addr_hit_write[114] & reg_we & !reg_error; + + assign range_attr_10_enable_10_wd = reg_wdata[3:0]; + + assign range_attr_10_read_access_10_wd = reg_wdata[7:4]; + + assign range_attr_10_write_access_10_wd = reg_wdata[11:8]; + + assign range_attr_10_execute_access_10_wd = reg_wdata[15:12]; + + assign range_attr_10_log_denied_access_10_wd = reg_wdata[19:16]; + assign range_attr_11_we = racl_addr_hit_write[115] & reg_we & !reg_error; + + assign range_attr_11_enable_11_wd = reg_wdata[3:0]; + + assign range_attr_11_read_access_11_wd = reg_wdata[7:4]; + + assign range_attr_11_write_access_11_wd = reg_wdata[11:8]; + + assign range_attr_11_execute_access_11_wd = reg_wdata[15:12]; + + assign range_attr_11_log_denied_access_11_wd = reg_wdata[19:16]; + assign range_attr_12_we = racl_addr_hit_write[116] & reg_we & !reg_error; + + assign range_attr_12_enable_12_wd = reg_wdata[3:0]; + + assign range_attr_12_read_access_12_wd = reg_wdata[7:4]; + + assign range_attr_12_write_access_12_wd = reg_wdata[11:8]; + + assign range_attr_12_execute_access_12_wd = reg_wdata[15:12]; + + assign range_attr_12_log_denied_access_12_wd = reg_wdata[19:16]; + assign range_attr_13_we = racl_addr_hit_write[117] & reg_we & !reg_error; + + assign range_attr_13_enable_13_wd = reg_wdata[3:0]; + + assign range_attr_13_read_access_13_wd = reg_wdata[7:4]; + + assign range_attr_13_write_access_13_wd = reg_wdata[11:8]; + + assign range_attr_13_execute_access_13_wd = reg_wdata[15:12]; + + assign range_attr_13_log_denied_access_13_wd = reg_wdata[19:16]; + assign range_attr_14_we = racl_addr_hit_write[118] & reg_we & !reg_error; + + assign range_attr_14_enable_14_wd = reg_wdata[3:0]; + + assign range_attr_14_read_access_14_wd = reg_wdata[7:4]; + + assign range_attr_14_write_access_14_wd = reg_wdata[11:8]; + + assign range_attr_14_execute_access_14_wd = reg_wdata[15:12]; + + assign range_attr_14_log_denied_access_14_wd = reg_wdata[19:16]; + assign range_attr_15_we = racl_addr_hit_write[119] & reg_we & !reg_error; + + assign range_attr_15_enable_15_wd = reg_wdata[3:0]; + + assign range_attr_15_read_access_15_wd = reg_wdata[7:4]; + + assign range_attr_15_write_access_15_wd = reg_wdata[11:8]; + + assign range_attr_15_execute_access_15_wd = reg_wdata[15:12]; + + assign range_attr_15_log_denied_access_15_wd = reg_wdata[19:16]; + assign range_attr_16_we = racl_addr_hit_write[120] & reg_we & !reg_error; + + assign range_attr_16_enable_16_wd = reg_wdata[3:0]; + + assign range_attr_16_read_access_16_wd = reg_wdata[7:4]; + + assign range_attr_16_write_access_16_wd = reg_wdata[11:8]; + + assign range_attr_16_execute_access_16_wd = reg_wdata[15:12]; + + assign range_attr_16_log_denied_access_16_wd = reg_wdata[19:16]; + assign range_attr_17_we = racl_addr_hit_write[121] & reg_we & !reg_error; + + assign range_attr_17_enable_17_wd = reg_wdata[3:0]; + + assign range_attr_17_read_access_17_wd = reg_wdata[7:4]; + + assign range_attr_17_write_access_17_wd = reg_wdata[11:8]; + + assign range_attr_17_execute_access_17_wd = reg_wdata[15:12]; + + assign range_attr_17_log_denied_access_17_wd = reg_wdata[19:16]; + assign range_attr_18_we = racl_addr_hit_write[122] & reg_we & !reg_error; + + assign range_attr_18_enable_18_wd = reg_wdata[3:0]; + + assign range_attr_18_read_access_18_wd = reg_wdata[7:4]; + + assign range_attr_18_write_access_18_wd = reg_wdata[11:8]; + + assign range_attr_18_execute_access_18_wd = reg_wdata[15:12]; + + assign range_attr_18_log_denied_access_18_wd = reg_wdata[19:16]; + assign range_attr_19_we = racl_addr_hit_write[123] & reg_we & !reg_error; + + assign range_attr_19_enable_19_wd = reg_wdata[3:0]; + + assign range_attr_19_read_access_19_wd = reg_wdata[7:4]; + + assign range_attr_19_write_access_19_wd = reg_wdata[11:8]; + + assign range_attr_19_execute_access_19_wd = reg_wdata[15:12]; + + assign range_attr_19_log_denied_access_19_wd = reg_wdata[19:16]; + assign range_attr_20_we = racl_addr_hit_write[124] & reg_we & !reg_error; + + assign range_attr_20_enable_20_wd = reg_wdata[3:0]; + + assign range_attr_20_read_access_20_wd = reg_wdata[7:4]; + + assign range_attr_20_write_access_20_wd = reg_wdata[11:8]; + + assign range_attr_20_execute_access_20_wd = reg_wdata[15:12]; + + assign range_attr_20_log_denied_access_20_wd = reg_wdata[19:16]; + assign range_attr_21_we = racl_addr_hit_write[125] & reg_we & !reg_error; + + assign range_attr_21_enable_21_wd = reg_wdata[3:0]; + + assign range_attr_21_read_access_21_wd = reg_wdata[7:4]; + + assign range_attr_21_write_access_21_wd = reg_wdata[11:8]; + + assign range_attr_21_execute_access_21_wd = reg_wdata[15:12]; + + assign range_attr_21_log_denied_access_21_wd = reg_wdata[19:16]; + assign range_attr_22_we = racl_addr_hit_write[126] & reg_we & !reg_error; + + assign range_attr_22_enable_22_wd = reg_wdata[3:0]; + + assign range_attr_22_read_access_22_wd = reg_wdata[7:4]; + + assign range_attr_22_write_access_22_wd = reg_wdata[11:8]; + + assign range_attr_22_execute_access_22_wd = reg_wdata[15:12]; + + assign range_attr_22_log_denied_access_22_wd = reg_wdata[19:16]; + assign range_attr_23_we = racl_addr_hit_write[127] & reg_we & !reg_error; + + assign range_attr_23_enable_23_wd = reg_wdata[3:0]; + + assign range_attr_23_read_access_23_wd = reg_wdata[7:4]; + + assign range_attr_23_write_access_23_wd = reg_wdata[11:8]; + + assign range_attr_23_execute_access_23_wd = reg_wdata[15:12]; + + assign range_attr_23_log_denied_access_23_wd = reg_wdata[19:16]; + assign range_attr_24_we = racl_addr_hit_write[128] & reg_we & !reg_error; + + assign range_attr_24_enable_24_wd = reg_wdata[3:0]; + + assign range_attr_24_read_access_24_wd = reg_wdata[7:4]; + + assign range_attr_24_write_access_24_wd = reg_wdata[11:8]; + + assign range_attr_24_execute_access_24_wd = reg_wdata[15:12]; + + assign range_attr_24_log_denied_access_24_wd = reg_wdata[19:16]; + assign range_attr_25_we = racl_addr_hit_write[129] & reg_we & !reg_error; + + assign range_attr_25_enable_25_wd = reg_wdata[3:0]; + + assign range_attr_25_read_access_25_wd = reg_wdata[7:4]; + + assign range_attr_25_write_access_25_wd = reg_wdata[11:8]; + + assign range_attr_25_execute_access_25_wd = reg_wdata[15:12]; + + assign range_attr_25_log_denied_access_25_wd = reg_wdata[19:16]; + assign range_attr_26_we = racl_addr_hit_write[130] & reg_we & !reg_error; + + assign range_attr_26_enable_26_wd = reg_wdata[3:0]; + + assign range_attr_26_read_access_26_wd = reg_wdata[7:4]; + + assign range_attr_26_write_access_26_wd = reg_wdata[11:8]; + + assign range_attr_26_execute_access_26_wd = reg_wdata[15:12]; + + assign range_attr_26_log_denied_access_26_wd = reg_wdata[19:16]; + assign range_attr_27_we = racl_addr_hit_write[131] & reg_we & !reg_error; + + assign range_attr_27_enable_27_wd = reg_wdata[3:0]; + + assign range_attr_27_read_access_27_wd = reg_wdata[7:4]; + + assign range_attr_27_write_access_27_wd = reg_wdata[11:8]; + + assign range_attr_27_execute_access_27_wd = reg_wdata[15:12]; + + assign range_attr_27_log_denied_access_27_wd = reg_wdata[19:16]; + assign range_attr_28_we = racl_addr_hit_write[132] & reg_we & !reg_error; + + assign range_attr_28_enable_28_wd = reg_wdata[3:0]; + + assign range_attr_28_read_access_28_wd = reg_wdata[7:4]; + + assign range_attr_28_write_access_28_wd = reg_wdata[11:8]; + + assign range_attr_28_execute_access_28_wd = reg_wdata[15:12]; + + assign range_attr_28_log_denied_access_28_wd = reg_wdata[19:16]; + assign range_attr_29_we = racl_addr_hit_write[133] & reg_we & !reg_error; + + assign range_attr_29_enable_29_wd = reg_wdata[3:0]; + + assign range_attr_29_read_access_29_wd = reg_wdata[7:4]; + + assign range_attr_29_write_access_29_wd = reg_wdata[11:8]; + + assign range_attr_29_execute_access_29_wd = reg_wdata[15:12]; + + assign range_attr_29_log_denied_access_29_wd = reg_wdata[19:16]; + assign range_attr_30_we = racl_addr_hit_write[134] & reg_we & !reg_error; + + assign range_attr_30_enable_30_wd = reg_wdata[3:0]; + + assign range_attr_30_read_access_30_wd = reg_wdata[7:4]; + + assign range_attr_30_write_access_30_wd = reg_wdata[11:8]; + + assign range_attr_30_execute_access_30_wd = reg_wdata[15:12]; + + assign range_attr_30_log_denied_access_30_wd = reg_wdata[19:16]; + assign range_attr_31_we = racl_addr_hit_write[135] & reg_we & !reg_error; + + assign range_attr_31_enable_31_wd = reg_wdata[3:0]; + + assign range_attr_31_read_access_31_wd = reg_wdata[7:4]; + + assign range_attr_31_write_access_31_wd = reg_wdata[11:8]; + + assign range_attr_31_execute_access_31_wd = reg_wdata[15:12]; + + assign range_attr_31_log_denied_access_31_wd = reg_wdata[19:16]; + assign range_racl_policy_shadowed_0_re = racl_addr_hit_read[136] & reg_re & !reg_error; + assign range_racl_policy_shadowed_0_we = racl_addr_hit_write[136] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_0_read_perm_0_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_0_write_perm_0_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_1_re = racl_addr_hit_read[137] & reg_re & !reg_error; + assign range_racl_policy_shadowed_1_we = racl_addr_hit_write[137] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_1_read_perm_1_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_1_write_perm_1_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_2_re = racl_addr_hit_read[138] & reg_re & !reg_error; + assign range_racl_policy_shadowed_2_we = racl_addr_hit_write[138] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_2_read_perm_2_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_2_write_perm_2_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_3_re = racl_addr_hit_read[139] & reg_re & !reg_error; + assign range_racl_policy_shadowed_3_we = racl_addr_hit_write[139] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_3_read_perm_3_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_3_write_perm_3_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_4_re = racl_addr_hit_read[140] & reg_re & !reg_error; + assign range_racl_policy_shadowed_4_we = racl_addr_hit_write[140] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_4_read_perm_4_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_4_write_perm_4_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_5_re = racl_addr_hit_read[141] & reg_re & !reg_error; + assign range_racl_policy_shadowed_5_we = racl_addr_hit_write[141] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_5_read_perm_5_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_5_write_perm_5_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_6_re = racl_addr_hit_read[142] & reg_re & !reg_error; + assign range_racl_policy_shadowed_6_we = racl_addr_hit_write[142] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_6_read_perm_6_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_6_write_perm_6_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_7_re = racl_addr_hit_read[143] & reg_re & !reg_error; + assign range_racl_policy_shadowed_7_we = racl_addr_hit_write[143] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_7_read_perm_7_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_7_write_perm_7_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_8_re = racl_addr_hit_read[144] & reg_re & !reg_error; + assign range_racl_policy_shadowed_8_we = racl_addr_hit_write[144] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_8_read_perm_8_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_8_write_perm_8_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_9_re = racl_addr_hit_read[145] & reg_re & !reg_error; + assign range_racl_policy_shadowed_9_we = racl_addr_hit_write[145] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_9_read_perm_9_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_9_write_perm_9_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_10_re = racl_addr_hit_read[146] & reg_re & !reg_error; + assign range_racl_policy_shadowed_10_we = racl_addr_hit_write[146] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_10_read_perm_10_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_10_write_perm_10_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_11_re = racl_addr_hit_read[147] & reg_re & !reg_error; + assign range_racl_policy_shadowed_11_we = racl_addr_hit_write[147] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_11_read_perm_11_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_11_write_perm_11_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_12_re = racl_addr_hit_read[148] & reg_re & !reg_error; + assign range_racl_policy_shadowed_12_we = racl_addr_hit_write[148] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_12_read_perm_12_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_12_write_perm_12_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_13_re = racl_addr_hit_read[149] & reg_re & !reg_error; + assign range_racl_policy_shadowed_13_we = racl_addr_hit_write[149] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_13_read_perm_13_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_13_write_perm_13_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_14_re = racl_addr_hit_read[150] & reg_re & !reg_error; + assign range_racl_policy_shadowed_14_we = racl_addr_hit_write[150] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_14_read_perm_14_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_14_write_perm_14_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_15_re = racl_addr_hit_read[151] & reg_re & !reg_error; + assign range_racl_policy_shadowed_15_we = racl_addr_hit_write[151] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_15_read_perm_15_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_15_write_perm_15_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_16_re = racl_addr_hit_read[152] & reg_re & !reg_error; + assign range_racl_policy_shadowed_16_we = racl_addr_hit_write[152] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_16_read_perm_16_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_16_write_perm_16_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_17_re = racl_addr_hit_read[153] & reg_re & !reg_error; + assign range_racl_policy_shadowed_17_we = racl_addr_hit_write[153] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_17_read_perm_17_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_17_write_perm_17_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_18_re = racl_addr_hit_read[154] & reg_re & !reg_error; + assign range_racl_policy_shadowed_18_we = racl_addr_hit_write[154] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_18_read_perm_18_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_18_write_perm_18_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_19_re = racl_addr_hit_read[155] & reg_re & !reg_error; + assign range_racl_policy_shadowed_19_we = racl_addr_hit_write[155] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_19_read_perm_19_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_19_write_perm_19_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_20_re = racl_addr_hit_read[156] & reg_re & !reg_error; + assign range_racl_policy_shadowed_20_we = racl_addr_hit_write[156] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_20_read_perm_20_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_20_write_perm_20_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_21_re = racl_addr_hit_read[157] & reg_re & !reg_error; + assign range_racl_policy_shadowed_21_we = racl_addr_hit_write[157] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_21_read_perm_21_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_21_write_perm_21_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_22_re = racl_addr_hit_read[158] & reg_re & !reg_error; + assign range_racl_policy_shadowed_22_we = racl_addr_hit_write[158] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_22_read_perm_22_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_22_write_perm_22_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_23_re = racl_addr_hit_read[159] & reg_re & !reg_error; + assign range_racl_policy_shadowed_23_we = racl_addr_hit_write[159] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_23_read_perm_23_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_23_write_perm_23_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_24_re = racl_addr_hit_read[160] & reg_re & !reg_error; + assign range_racl_policy_shadowed_24_we = racl_addr_hit_write[160] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_24_read_perm_24_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_24_write_perm_24_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_25_re = racl_addr_hit_read[161] & reg_re & !reg_error; + assign range_racl_policy_shadowed_25_we = racl_addr_hit_write[161] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_25_read_perm_25_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_25_write_perm_25_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_26_re = racl_addr_hit_read[162] & reg_re & !reg_error; + assign range_racl_policy_shadowed_26_we = racl_addr_hit_write[162] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_26_read_perm_26_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_26_write_perm_26_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_27_re = racl_addr_hit_read[163] & reg_re & !reg_error; + assign range_racl_policy_shadowed_27_we = racl_addr_hit_write[163] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_27_read_perm_27_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_27_write_perm_27_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_28_re = racl_addr_hit_read[164] & reg_re & !reg_error; + assign range_racl_policy_shadowed_28_we = racl_addr_hit_write[164] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_28_read_perm_28_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_28_write_perm_28_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_29_re = racl_addr_hit_read[165] & reg_re & !reg_error; + assign range_racl_policy_shadowed_29_we = racl_addr_hit_write[165] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_29_read_perm_29_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_29_write_perm_29_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_30_re = racl_addr_hit_read[166] & reg_re & !reg_error; + assign range_racl_policy_shadowed_30_we = racl_addr_hit_write[166] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_30_read_perm_30_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_30_write_perm_30_wd = reg_wdata[31:16]; + assign range_racl_policy_shadowed_31_re = racl_addr_hit_read[167] & reg_re & !reg_error; + assign range_racl_policy_shadowed_31_we = racl_addr_hit_write[167] & reg_we & !reg_error; + + assign range_racl_policy_shadowed_31_read_perm_31_wd = reg_wdata[15:0]; + + assign range_racl_policy_shadowed_31_write_perm_31_wd = reg_wdata[31:16]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = 1'b0; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + reg_we_check[4] = 1'b0; + reg_we_check[5] = log_config_we; + reg_we_check[6] = 1'b0; + reg_we_check[7] = 1'b0; + reg_we_check[8] = range_regwen_0_we; + reg_we_check[9] = range_regwen_1_we; + reg_we_check[10] = range_regwen_2_we; + reg_we_check[11] = range_regwen_3_we; + reg_we_check[12] = range_regwen_4_we; + reg_we_check[13] = range_regwen_5_we; + reg_we_check[14] = range_regwen_6_we; + reg_we_check[15] = range_regwen_7_we; + reg_we_check[16] = range_regwen_8_we; + reg_we_check[17] = range_regwen_9_we; + reg_we_check[18] = range_regwen_10_we; + reg_we_check[19] = range_regwen_11_we; + reg_we_check[20] = range_regwen_12_we; + reg_we_check[21] = range_regwen_13_we; + reg_we_check[22] = range_regwen_14_we; + reg_we_check[23] = range_regwen_15_we; + reg_we_check[24] = range_regwen_16_we; + reg_we_check[25] = range_regwen_17_we; + reg_we_check[26] = range_regwen_18_we; + reg_we_check[27] = range_regwen_19_we; + reg_we_check[28] = range_regwen_20_we; + reg_we_check[29] = range_regwen_21_we; + reg_we_check[30] = range_regwen_22_we; + reg_we_check[31] = range_regwen_23_we; + reg_we_check[32] = range_regwen_24_we; + reg_we_check[33] = range_regwen_25_we; + reg_we_check[34] = range_regwen_26_we; + reg_we_check[35] = range_regwen_27_we; + reg_we_check[36] = range_regwen_28_we; + reg_we_check[37] = range_regwen_29_we; + reg_we_check[38] = range_regwen_30_we; + reg_we_check[39] = range_regwen_31_we; + reg_we_check[40] = range_base_0_gated_we; + reg_we_check[41] = range_base_1_gated_we; + reg_we_check[42] = range_base_2_gated_we; + reg_we_check[43] = range_base_3_gated_we; + reg_we_check[44] = range_base_4_gated_we; + reg_we_check[45] = range_base_5_gated_we; + reg_we_check[46] = range_base_6_gated_we; + reg_we_check[47] = range_base_7_gated_we; + reg_we_check[48] = range_base_8_gated_we; + reg_we_check[49] = range_base_9_gated_we; + reg_we_check[50] = range_base_10_gated_we; + reg_we_check[51] = range_base_11_gated_we; + reg_we_check[52] = range_base_12_gated_we; + reg_we_check[53] = range_base_13_gated_we; + reg_we_check[54] = range_base_14_gated_we; + reg_we_check[55] = range_base_15_gated_we; + reg_we_check[56] = range_base_16_gated_we; + reg_we_check[57] = range_base_17_gated_we; + reg_we_check[58] = range_base_18_gated_we; + reg_we_check[59] = range_base_19_gated_we; + reg_we_check[60] = range_base_20_gated_we; + reg_we_check[61] = range_base_21_gated_we; + reg_we_check[62] = range_base_22_gated_we; + reg_we_check[63] = range_base_23_gated_we; + reg_we_check[64] = range_base_24_gated_we; + reg_we_check[65] = range_base_25_gated_we; + reg_we_check[66] = range_base_26_gated_we; + reg_we_check[67] = range_base_27_gated_we; + reg_we_check[68] = range_base_28_gated_we; + reg_we_check[69] = range_base_29_gated_we; + reg_we_check[70] = range_base_30_gated_we; + reg_we_check[71] = range_base_31_gated_we; + reg_we_check[72] = range_limit_0_gated_we; + reg_we_check[73] = range_limit_1_gated_we; + reg_we_check[74] = range_limit_2_gated_we; + reg_we_check[75] = range_limit_3_gated_we; + reg_we_check[76] = range_limit_4_gated_we; + reg_we_check[77] = range_limit_5_gated_we; + reg_we_check[78] = range_limit_6_gated_we; + reg_we_check[79] = range_limit_7_gated_we; + reg_we_check[80] = range_limit_8_gated_we; + reg_we_check[81] = range_limit_9_gated_we; + reg_we_check[82] = range_limit_10_gated_we; + reg_we_check[83] = range_limit_11_gated_we; + reg_we_check[84] = range_limit_12_gated_we; + reg_we_check[85] = range_limit_13_gated_we; + reg_we_check[86] = range_limit_14_gated_we; + reg_we_check[87] = range_limit_15_gated_we; + reg_we_check[88] = range_limit_16_gated_we; + reg_we_check[89] = range_limit_17_gated_we; + reg_we_check[90] = range_limit_18_gated_we; + reg_we_check[91] = range_limit_19_gated_we; + reg_we_check[92] = range_limit_20_gated_we; + reg_we_check[93] = range_limit_21_gated_we; + reg_we_check[94] = range_limit_22_gated_we; + reg_we_check[95] = range_limit_23_gated_we; + reg_we_check[96] = range_limit_24_gated_we; + reg_we_check[97] = range_limit_25_gated_we; + reg_we_check[98] = range_limit_26_gated_we; + reg_we_check[99] = range_limit_27_gated_we; + reg_we_check[100] = range_limit_28_gated_we; + reg_we_check[101] = range_limit_29_gated_we; + reg_we_check[102] = range_limit_30_gated_we; + reg_we_check[103] = range_limit_31_gated_we; + reg_we_check[104] = range_attr_0_gated_we; + reg_we_check[105] = range_attr_1_gated_we; + reg_we_check[106] = range_attr_2_gated_we; + reg_we_check[107] = range_attr_3_gated_we; + reg_we_check[108] = range_attr_4_gated_we; + reg_we_check[109] = range_attr_5_gated_we; + reg_we_check[110] = range_attr_6_gated_we; + reg_we_check[111] = range_attr_7_gated_we; + reg_we_check[112] = range_attr_8_gated_we; + reg_we_check[113] = range_attr_9_gated_we; + reg_we_check[114] = range_attr_10_gated_we; + reg_we_check[115] = range_attr_11_gated_we; + reg_we_check[116] = range_attr_12_gated_we; + reg_we_check[117] = range_attr_13_gated_we; + reg_we_check[118] = range_attr_14_gated_we; + reg_we_check[119] = range_attr_15_gated_we; + reg_we_check[120] = range_attr_16_gated_we; + reg_we_check[121] = range_attr_17_gated_we; + reg_we_check[122] = range_attr_18_gated_we; + reg_we_check[123] = range_attr_19_gated_we; + reg_we_check[124] = range_attr_20_gated_we; + reg_we_check[125] = range_attr_21_gated_we; + reg_we_check[126] = range_attr_22_gated_we; + reg_we_check[127] = range_attr_23_gated_we; + reg_we_check[128] = range_attr_24_gated_we; + reg_we_check[129] = range_attr_25_gated_we; + reg_we_check[130] = range_attr_26_gated_we; + reg_we_check[131] = range_attr_27_gated_we; + reg_we_check[132] = range_attr_28_gated_we; + reg_we_check[133] = range_attr_29_gated_we; + reg_we_check[134] = range_attr_30_gated_we; + reg_we_check[135] = range_attr_31_gated_we; + reg_we_check[136] = range_racl_policy_shadowed_0_gated_we; + reg_we_check[137] = range_racl_policy_shadowed_1_gated_we; + reg_we_check[138] = range_racl_policy_shadowed_2_gated_we; + reg_we_check[139] = range_racl_policy_shadowed_3_gated_we; + reg_we_check[140] = range_racl_policy_shadowed_4_gated_we; + reg_we_check[141] = range_racl_policy_shadowed_5_gated_we; + reg_we_check[142] = range_racl_policy_shadowed_6_gated_we; + reg_we_check[143] = range_racl_policy_shadowed_7_gated_we; + reg_we_check[144] = range_racl_policy_shadowed_8_gated_we; + reg_we_check[145] = range_racl_policy_shadowed_9_gated_we; + reg_we_check[146] = range_racl_policy_shadowed_10_gated_we; + reg_we_check[147] = range_racl_policy_shadowed_11_gated_we; + reg_we_check[148] = range_racl_policy_shadowed_12_gated_we; + reg_we_check[149] = range_racl_policy_shadowed_13_gated_we; + reg_we_check[150] = range_racl_policy_shadowed_14_gated_we; + reg_we_check[151] = range_racl_policy_shadowed_15_gated_we; + reg_we_check[152] = range_racl_policy_shadowed_16_gated_we; + reg_we_check[153] = range_racl_policy_shadowed_17_gated_we; + reg_we_check[154] = range_racl_policy_shadowed_18_gated_we; + reg_we_check[155] = range_racl_policy_shadowed_19_gated_we; + reg_we_check[156] = range_racl_policy_shadowed_20_gated_we; + reg_we_check[157] = range_racl_policy_shadowed_21_gated_we; + reg_we_check[158] = range_racl_policy_shadowed_22_gated_we; + reg_we_check[159] = range_racl_policy_shadowed_23_gated_we; + reg_we_check[160] = range_racl_policy_shadowed_24_gated_we; + reg_we_check[161] = range_racl_policy_shadowed_25_gated_we; + reg_we_check[162] = range_racl_policy_shadowed_26_gated_we; + reg_we_check[163] = range_racl_policy_shadowed_27_gated_we; + reg_we_check[164] = range_racl_policy_shadowed_28_gated_we; + reg_we_check[165] = range_racl_policy_shadowed_29_gated_we; + reg_we_check[166] = range_racl_policy_shadowed_30_gated_we; + reg_we_check[167] = range_racl_policy_shadowed_31_gated_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + racl_addr_hit_read[0]: begin + reg_rdata_next[0] = intr_state_qs; + end + + racl_addr_hit_read[1]: begin + reg_rdata_next[0] = intr_enable_qs; + end + + racl_addr_hit_read[2]: begin + reg_rdata_next[0] = '0; + end + + racl_addr_hit_read[3]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + racl_addr_hit_read[4]: begin + reg_rdata_next[0] = alert_status_shadowed_update_err_qs; + reg_rdata_next[1] = alert_status_shadowed_storage_err_qs; + reg_rdata_next[2] = alert_status_reg_intg_err_qs; + reg_rdata_next[3] = alert_status_counter_err_qs; + end + + racl_addr_hit_read[5]: begin + reg_rdata_next[0] = log_config_log_enable_qs; + reg_rdata_next[1] = '0; + reg_rdata_next[9:2] = log_config_deny_cnt_threshold_qs; + end + + racl_addr_hit_read[6]: begin + reg_rdata_next[7:0] = log_status_deny_cnt_qs; + reg_rdata_next[8] = log_status_denied_read_access_qs; + reg_rdata_next[9] = log_status_denied_write_access_qs; + reg_rdata_next[10] = log_status_denied_execute_access_qs; + reg_rdata_next[11] = log_status_denied_no_match_qs; + reg_rdata_next[12] = log_status_denied_racl_read_qs; + reg_rdata_next[13] = log_status_denied_racl_write_qs; + reg_rdata_next[17:14] = log_status_denied_source_role_qs; + reg_rdata_next[22:18] = log_status_denied_ctn_uid_qs; + reg_rdata_next[27:23] = log_status_deny_range_index_qs; + end + + racl_addr_hit_read[7]: begin + reg_rdata_next[31:0] = log_address_qs; + end + + racl_addr_hit_read[8]: begin + reg_rdata_next[3:0] = range_regwen_0_qs; + end + + racl_addr_hit_read[9]: begin + reg_rdata_next[3:0] = range_regwen_1_qs; + end + + racl_addr_hit_read[10]: begin + reg_rdata_next[3:0] = range_regwen_2_qs; + end + + racl_addr_hit_read[11]: begin + reg_rdata_next[3:0] = range_regwen_3_qs; + end + + racl_addr_hit_read[12]: begin + reg_rdata_next[3:0] = range_regwen_4_qs; + end + + racl_addr_hit_read[13]: begin + reg_rdata_next[3:0] = range_regwen_5_qs; + end + + racl_addr_hit_read[14]: begin + reg_rdata_next[3:0] = range_regwen_6_qs; + end + + racl_addr_hit_read[15]: begin + reg_rdata_next[3:0] = range_regwen_7_qs; + end + + racl_addr_hit_read[16]: begin + reg_rdata_next[3:0] = range_regwen_8_qs; + end + + racl_addr_hit_read[17]: begin + reg_rdata_next[3:0] = range_regwen_9_qs; + end + + racl_addr_hit_read[18]: begin + reg_rdata_next[3:0] = range_regwen_10_qs; + end + + racl_addr_hit_read[19]: begin + reg_rdata_next[3:0] = range_regwen_11_qs; + end + + racl_addr_hit_read[20]: begin + reg_rdata_next[3:0] = range_regwen_12_qs; + end + + racl_addr_hit_read[21]: begin + reg_rdata_next[3:0] = range_regwen_13_qs; + end + + racl_addr_hit_read[22]: begin + reg_rdata_next[3:0] = range_regwen_14_qs; + end + + racl_addr_hit_read[23]: begin + reg_rdata_next[3:0] = range_regwen_15_qs; + end + + racl_addr_hit_read[24]: begin + reg_rdata_next[3:0] = range_regwen_16_qs; + end + + racl_addr_hit_read[25]: begin + reg_rdata_next[3:0] = range_regwen_17_qs; + end + + racl_addr_hit_read[26]: begin + reg_rdata_next[3:0] = range_regwen_18_qs; + end + + racl_addr_hit_read[27]: begin + reg_rdata_next[3:0] = range_regwen_19_qs; + end + + racl_addr_hit_read[28]: begin + reg_rdata_next[3:0] = range_regwen_20_qs; + end + + racl_addr_hit_read[29]: begin + reg_rdata_next[3:0] = range_regwen_21_qs; + end + + racl_addr_hit_read[30]: begin + reg_rdata_next[3:0] = range_regwen_22_qs; + end + + racl_addr_hit_read[31]: begin + reg_rdata_next[3:0] = range_regwen_23_qs; + end + + racl_addr_hit_read[32]: begin + reg_rdata_next[3:0] = range_regwen_24_qs; + end + + racl_addr_hit_read[33]: begin + reg_rdata_next[3:0] = range_regwen_25_qs; + end + + racl_addr_hit_read[34]: begin + reg_rdata_next[3:0] = range_regwen_26_qs; + end + + racl_addr_hit_read[35]: begin + reg_rdata_next[3:0] = range_regwen_27_qs; + end + + racl_addr_hit_read[36]: begin + reg_rdata_next[3:0] = range_regwen_28_qs; + end + + racl_addr_hit_read[37]: begin + reg_rdata_next[3:0] = range_regwen_29_qs; + end + + racl_addr_hit_read[38]: begin + reg_rdata_next[3:0] = range_regwen_30_qs; + end + + racl_addr_hit_read[39]: begin + reg_rdata_next[3:0] = range_regwen_31_qs; + end + + racl_addr_hit_read[40]: begin + reg_rdata_next[31:2] = range_base_0_qs; + end + + racl_addr_hit_read[41]: begin + reg_rdata_next[31:2] = range_base_1_qs; + end + + racl_addr_hit_read[42]: begin + reg_rdata_next[31:2] = range_base_2_qs; + end + + racl_addr_hit_read[43]: begin + reg_rdata_next[31:2] = range_base_3_qs; + end + + racl_addr_hit_read[44]: begin + reg_rdata_next[31:2] = range_base_4_qs; + end + + racl_addr_hit_read[45]: begin + reg_rdata_next[31:2] = range_base_5_qs; + end + + racl_addr_hit_read[46]: begin + reg_rdata_next[31:2] = range_base_6_qs; + end + + racl_addr_hit_read[47]: begin + reg_rdata_next[31:2] = range_base_7_qs; + end + + racl_addr_hit_read[48]: begin + reg_rdata_next[31:2] = range_base_8_qs; + end + + racl_addr_hit_read[49]: begin + reg_rdata_next[31:2] = range_base_9_qs; + end + + racl_addr_hit_read[50]: begin + reg_rdata_next[31:2] = range_base_10_qs; + end + + racl_addr_hit_read[51]: begin + reg_rdata_next[31:2] = range_base_11_qs; + end + + racl_addr_hit_read[52]: begin + reg_rdata_next[31:2] = range_base_12_qs; + end + + racl_addr_hit_read[53]: begin + reg_rdata_next[31:2] = range_base_13_qs; + end + + racl_addr_hit_read[54]: begin + reg_rdata_next[31:2] = range_base_14_qs; + end + + racl_addr_hit_read[55]: begin + reg_rdata_next[31:2] = range_base_15_qs; + end + + racl_addr_hit_read[56]: begin + reg_rdata_next[31:2] = range_base_16_qs; + end + + racl_addr_hit_read[57]: begin + reg_rdata_next[31:2] = range_base_17_qs; + end + + racl_addr_hit_read[58]: begin + reg_rdata_next[31:2] = range_base_18_qs; + end + + racl_addr_hit_read[59]: begin + reg_rdata_next[31:2] = range_base_19_qs; + end + + racl_addr_hit_read[60]: begin + reg_rdata_next[31:2] = range_base_20_qs; + end + + racl_addr_hit_read[61]: begin + reg_rdata_next[31:2] = range_base_21_qs; + end + + racl_addr_hit_read[62]: begin + reg_rdata_next[31:2] = range_base_22_qs; + end + + racl_addr_hit_read[63]: begin + reg_rdata_next[31:2] = range_base_23_qs; + end + + racl_addr_hit_read[64]: begin + reg_rdata_next[31:2] = range_base_24_qs; + end + + racl_addr_hit_read[65]: begin + reg_rdata_next[31:2] = range_base_25_qs; + end + + racl_addr_hit_read[66]: begin + reg_rdata_next[31:2] = range_base_26_qs; + end + + racl_addr_hit_read[67]: begin + reg_rdata_next[31:2] = range_base_27_qs; + end + + racl_addr_hit_read[68]: begin + reg_rdata_next[31:2] = range_base_28_qs; + end + + racl_addr_hit_read[69]: begin + reg_rdata_next[31:2] = range_base_29_qs; + end + + racl_addr_hit_read[70]: begin + reg_rdata_next[31:2] = range_base_30_qs; + end + + racl_addr_hit_read[71]: begin + reg_rdata_next[31:2] = range_base_31_qs; + end + + racl_addr_hit_read[72]: begin + reg_rdata_next[31:2] = range_limit_0_qs; + end + + racl_addr_hit_read[73]: begin + reg_rdata_next[31:2] = range_limit_1_qs; + end + + racl_addr_hit_read[74]: begin + reg_rdata_next[31:2] = range_limit_2_qs; + end + + racl_addr_hit_read[75]: begin + reg_rdata_next[31:2] = range_limit_3_qs; + end + + racl_addr_hit_read[76]: begin + reg_rdata_next[31:2] = range_limit_4_qs; + end + + racl_addr_hit_read[77]: begin + reg_rdata_next[31:2] = range_limit_5_qs; + end + + racl_addr_hit_read[78]: begin + reg_rdata_next[31:2] = range_limit_6_qs; + end + + racl_addr_hit_read[79]: begin + reg_rdata_next[31:2] = range_limit_7_qs; + end + + racl_addr_hit_read[80]: begin + reg_rdata_next[31:2] = range_limit_8_qs; + end + + racl_addr_hit_read[81]: begin + reg_rdata_next[31:2] = range_limit_9_qs; + end + + racl_addr_hit_read[82]: begin + reg_rdata_next[31:2] = range_limit_10_qs; + end + + racl_addr_hit_read[83]: begin + reg_rdata_next[31:2] = range_limit_11_qs; + end + + racl_addr_hit_read[84]: begin + reg_rdata_next[31:2] = range_limit_12_qs; + end + + racl_addr_hit_read[85]: begin + reg_rdata_next[31:2] = range_limit_13_qs; + end + + racl_addr_hit_read[86]: begin + reg_rdata_next[31:2] = range_limit_14_qs; + end + + racl_addr_hit_read[87]: begin + reg_rdata_next[31:2] = range_limit_15_qs; + end + + racl_addr_hit_read[88]: begin + reg_rdata_next[31:2] = range_limit_16_qs; + end + + racl_addr_hit_read[89]: begin + reg_rdata_next[31:2] = range_limit_17_qs; + end + + racl_addr_hit_read[90]: begin + reg_rdata_next[31:2] = range_limit_18_qs; + end + + racl_addr_hit_read[91]: begin + reg_rdata_next[31:2] = range_limit_19_qs; + end + + racl_addr_hit_read[92]: begin + reg_rdata_next[31:2] = range_limit_20_qs; + end + + racl_addr_hit_read[93]: begin + reg_rdata_next[31:2] = range_limit_21_qs; + end + + racl_addr_hit_read[94]: begin + reg_rdata_next[31:2] = range_limit_22_qs; + end + + racl_addr_hit_read[95]: begin + reg_rdata_next[31:2] = range_limit_23_qs; + end + + racl_addr_hit_read[96]: begin + reg_rdata_next[31:2] = range_limit_24_qs; + end + + racl_addr_hit_read[97]: begin + reg_rdata_next[31:2] = range_limit_25_qs; + end + + racl_addr_hit_read[98]: begin + reg_rdata_next[31:2] = range_limit_26_qs; + end + + racl_addr_hit_read[99]: begin + reg_rdata_next[31:2] = range_limit_27_qs; + end + + racl_addr_hit_read[100]: begin + reg_rdata_next[31:2] = range_limit_28_qs; + end + + racl_addr_hit_read[101]: begin + reg_rdata_next[31:2] = range_limit_29_qs; + end + + racl_addr_hit_read[102]: begin + reg_rdata_next[31:2] = range_limit_30_qs; + end + + racl_addr_hit_read[103]: begin + reg_rdata_next[31:2] = range_limit_31_qs; + end + + racl_addr_hit_read[104]: begin + reg_rdata_next[3:0] = range_attr_0_enable_0_qs; + reg_rdata_next[7:4] = range_attr_0_read_access_0_qs; + reg_rdata_next[11:8] = range_attr_0_write_access_0_qs; + reg_rdata_next[15:12] = range_attr_0_execute_access_0_qs; + reg_rdata_next[19:16] = range_attr_0_log_denied_access_0_qs; + end + + racl_addr_hit_read[105]: begin + reg_rdata_next[3:0] = range_attr_1_enable_1_qs; + reg_rdata_next[7:4] = range_attr_1_read_access_1_qs; + reg_rdata_next[11:8] = range_attr_1_write_access_1_qs; + reg_rdata_next[15:12] = range_attr_1_execute_access_1_qs; + reg_rdata_next[19:16] = range_attr_1_log_denied_access_1_qs; + end + + racl_addr_hit_read[106]: begin + reg_rdata_next[3:0] = range_attr_2_enable_2_qs; + reg_rdata_next[7:4] = range_attr_2_read_access_2_qs; + reg_rdata_next[11:8] = range_attr_2_write_access_2_qs; + reg_rdata_next[15:12] = range_attr_2_execute_access_2_qs; + reg_rdata_next[19:16] = range_attr_2_log_denied_access_2_qs; + end + + racl_addr_hit_read[107]: begin + reg_rdata_next[3:0] = range_attr_3_enable_3_qs; + reg_rdata_next[7:4] = range_attr_3_read_access_3_qs; + reg_rdata_next[11:8] = range_attr_3_write_access_3_qs; + reg_rdata_next[15:12] = range_attr_3_execute_access_3_qs; + reg_rdata_next[19:16] = range_attr_3_log_denied_access_3_qs; + end + + racl_addr_hit_read[108]: begin + reg_rdata_next[3:0] = range_attr_4_enable_4_qs; + reg_rdata_next[7:4] = range_attr_4_read_access_4_qs; + reg_rdata_next[11:8] = range_attr_4_write_access_4_qs; + reg_rdata_next[15:12] = range_attr_4_execute_access_4_qs; + reg_rdata_next[19:16] = range_attr_4_log_denied_access_4_qs; + end + + racl_addr_hit_read[109]: begin + reg_rdata_next[3:0] = range_attr_5_enable_5_qs; + reg_rdata_next[7:4] = range_attr_5_read_access_5_qs; + reg_rdata_next[11:8] = range_attr_5_write_access_5_qs; + reg_rdata_next[15:12] = range_attr_5_execute_access_5_qs; + reg_rdata_next[19:16] = range_attr_5_log_denied_access_5_qs; + end + + racl_addr_hit_read[110]: begin + reg_rdata_next[3:0] = range_attr_6_enable_6_qs; + reg_rdata_next[7:4] = range_attr_6_read_access_6_qs; + reg_rdata_next[11:8] = range_attr_6_write_access_6_qs; + reg_rdata_next[15:12] = range_attr_6_execute_access_6_qs; + reg_rdata_next[19:16] = range_attr_6_log_denied_access_6_qs; + end + + racl_addr_hit_read[111]: begin + reg_rdata_next[3:0] = range_attr_7_enable_7_qs; + reg_rdata_next[7:4] = range_attr_7_read_access_7_qs; + reg_rdata_next[11:8] = range_attr_7_write_access_7_qs; + reg_rdata_next[15:12] = range_attr_7_execute_access_7_qs; + reg_rdata_next[19:16] = range_attr_7_log_denied_access_7_qs; + end + + racl_addr_hit_read[112]: begin + reg_rdata_next[3:0] = range_attr_8_enable_8_qs; + reg_rdata_next[7:4] = range_attr_8_read_access_8_qs; + reg_rdata_next[11:8] = range_attr_8_write_access_8_qs; + reg_rdata_next[15:12] = range_attr_8_execute_access_8_qs; + reg_rdata_next[19:16] = range_attr_8_log_denied_access_8_qs; + end + + racl_addr_hit_read[113]: begin + reg_rdata_next[3:0] = range_attr_9_enable_9_qs; + reg_rdata_next[7:4] = range_attr_9_read_access_9_qs; + reg_rdata_next[11:8] = range_attr_9_write_access_9_qs; + reg_rdata_next[15:12] = range_attr_9_execute_access_9_qs; + reg_rdata_next[19:16] = range_attr_9_log_denied_access_9_qs; + end + + racl_addr_hit_read[114]: begin + reg_rdata_next[3:0] = range_attr_10_enable_10_qs; + reg_rdata_next[7:4] = range_attr_10_read_access_10_qs; + reg_rdata_next[11:8] = range_attr_10_write_access_10_qs; + reg_rdata_next[15:12] = range_attr_10_execute_access_10_qs; + reg_rdata_next[19:16] = range_attr_10_log_denied_access_10_qs; + end + + racl_addr_hit_read[115]: begin + reg_rdata_next[3:0] = range_attr_11_enable_11_qs; + reg_rdata_next[7:4] = range_attr_11_read_access_11_qs; + reg_rdata_next[11:8] = range_attr_11_write_access_11_qs; + reg_rdata_next[15:12] = range_attr_11_execute_access_11_qs; + reg_rdata_next[19:16] = range_attr_11_log_denied_access_11_qs; + end + + racl_addr_hit_read[116]: begin + reg_rdata_next[3:0] = range_attr_12_enable_12_qs; + reg_rdata_next[7:4] = range_attr_12_read_access_12_qs; + reg_rdata_next[11:8] = range_attr_12_write_access_12_qs; + reg_rdata_next[15:12] = range_attr_12_execute_access_12_qs; + reg_rdata_next[19:16] = range_attr_12_log_denied_access_12_qs; + end + + racl_addr_hit_read[117]: begin + reg_rdata_next[3:0] = range_attr_13_enable_13_qs; + reg_rdata_next[7:4] = range_attr_13_read_access_13_qs; + reg_rdata_next[11:8] = range_attr_13_write_access_13_qs; + reg_rdata_next[15:12] = range_attr_13_execute_access_13_qs; + reg_rdata_next[19:16] = range_attr_13_log_denied_access_13_qs; + end + + racl_addr_hit_read[118]: begin + reg_rdata_next[3:0] = range_attr_14_enable_14_qs; + reg_rdata_next[7:4] = range_attr_14_read_access_14_qs; + reg_rdata_next[11:8] = range_attr_14_write_access_14_qs; + reg_rdata_next[15:12] = range_attr_14_execute_access_14_qs; + reg_rdata_next[19:16] = range_attr_14_log_denied_access_14_qs; + end + + racl_addr_hit_read[119]: begin + reg_rdata_next[3:0] = range_attr_15_enable_15_qs; + reg_rdata_next[7:4] = range_attr_15_read_access_15_qs; + reg_rdata_next[11:8] = range_attr_15_write_access_15_qs; + reg_rdata_next[15:12] = range_attr_15_execute_access_15_qs; + reg_rdata_next[19:16] = range_attr_15_log_denied_access_15_qs; + end + + racl_addr_hit_read[120]: begin + reg_rdata_next[3:0] = range_attr_16_enable_16_qs; + reg_rdata_next[7:4] = range_attr_16_read_access_16_qs; + reg_rdata_next[11:8] = range_attr_16_write_access_16_qs; + reg_rdata_next[15:12] = range_attr_16_execute_access_16_qs; + reg_rdata_next[19:16] = range_attr_16_log_denied_access_16_qs; + end + + racl_addr_hit_read[121]: begin + reg_rdata_next[3:0] = range_attr_17_enable_17_qs; + reg_rdata_next[7:4] = range_attr_17_read_access_17_qs; + reg_rdata_next[11:8] = range_attr_17_write_access_17_qs; + reg_rdata_next[15:12] = range_attr_17_execute_access_17_qs; + reg_rdata_next[19:16] = range_attr_17_log_denied_access_17_qs; + end + + racl_addr_hit_read[122]: begin + reg_rdata_next[3:0] = range_attr_18_enable_18_qs; + reg_rdata_next[7:4] = range_attr_18_read_access_18_qs; + reg_rdata_next[11:8] = range_attr_18_write_access_18_qs; + reg_rdata_next[15:12] = range_attr_18_execute_access_18_qs; + reg_rdata_next[19:16] = range_attr_18_log_denied_access_18_qs; + end + + racl_addr_hit_read[123]: begin + reg_rdata_next[3:0] = range_attr_19_enable_19_qs; + reg_rdata_next[7:4] = range_attr_19_read_access_19_qs; + reg_rdata_next[11:8] = range_attr_19_write_access_19_qs; + reg_rdata_next[15:12] = range_attr_19_execute_access_19_qs; + reg_rdata_next[19:16] = range_attr_19_log_denied_access_19_qs; + end + + racl_addr_hit_read[124]: begin + reg_rdata_next[3:0] = range_attr_20_enable_20_qs; + reg_rdata_next[7:4] = range_attr_20_read_access_20_qs; + reg_rdata_next[11:8] = range_attr_20_write_access_20_qs; + reg_rdata_next[15:12] = range_attr_20_execute_access_20_qs; + reg_rdata_next[19:16] = range_attr_20_log_denied_access_20_qs; + end + + racl_addr_hit_read[125]: begin + reg_rdata_next[3:0] = range_attr_21_enable_21_qs; + reg_rdata_next[7:4] = range_attr_21_read_access_21_qs; + reg_rdata_next[11:8] = range_attr_21_write_access_21_qs; + reg_rdata_next[15:12] = range_attr_21_execute_access_21_qs; + reg_rdata_next[19:16] = range_attr_21_log_denied_access_21_qs; + end + + racl_addr_hit_read[126]: begin + reg_rdata_next[3:0] = range_attr_22_enable_22_qs; + reg_rdata_next[7:4] = range_attr_22_read_access_22_qs; + reg_rdata_next[11:8] = range_attr_22_write_access_22_qs; + reg_rdata_next[15:12] = range_attr_22_execute_access_22_qs; + reg_rdata_next[19:16] = range_attr_22_log_denied_access_22_qs; + end + + racl_addr_hit_read[127]: begin + reg_rdata_next[3:0] = range_attr_23_enable_23_qs; + reg_rdata_next[7:4] = range_attr_23_read_access_23_qs; + reg_rdata_next[11:8] = range_attr_23_write_access_23_qs; + reg_rdata_next[15:12] = range_attr_23_execute_access_23_qs; + reg_rdata_next[19:16] = range_attr_23_log_denied_access_23_qs; + end + + racl_addr_hit_read[128]: begin + reg_rdata_next[3:0] = range_attr_24_enable_24_qs; + reg_rdata_next[7:4] = range_attr_24_read_access_24_qs; + reg_rdata_next[11:8] = range_attr_24_write_access_24_qs; + reg_rdata_next[15:12] = range_attr_24_execute_access_24_qs; + reg_rdata_next[19:16] = range_attr_24_log_denied_access_24_qs; + end + + racl_addr_hit_read[129]: begin + reg_rdata_next[3:0] = range_attr_25_enable_25_qs; + reg_rdata_next[7:4] = range_attr_25_read_access_25_qs; + reg_rdata_next[11:8] = range_attr_25_write_access_25_qs; + reg_rdata_next[15:12] = range_attr_25_execute_access_25_qs; + reg_rdata_next[19:16] = range_attr_25_log_denied_access_25_qs; + end + + racl_addr_hit_read[130]: begin + reg_rdata_next[3:0] = range_attr_26_enable_26_qs; + reg_rdata_next[7:4] = range_attr_26_read_access_26_qs; + reg_rdata_next[11:8] = range_attr_26_write_access_26_qs; + reg_rdata_next[15:12] = range_attr_26_execute_access_26_qs; + reg_rdata_next[19:16] = range_attr_26_log_denied_access_26_qs; + end + + racl_addr_hit_read[131]: begin + reg_rdata_next[3:0] = range_attr_27_enable_27_qs; + reg_rdata_next[7:4] = range_attr_27_read_access_27_qs; + reg_rdata_next[11:8] = range_attr_27_write_access_27_qs; + reg_rdata_next[15:12] = range_attr_27_execute_access_27_qs; + reg_rdata_next[19:16] = range_attr_27_log_denied_access_27_qs; + end + + racl_addr_hit_read[132]: begin + reg_rdata_next[3:0] = range_attr_28_enable_28_qs; + reg_rdata_next[7:4] = range_attr_28_read_access_28_qs; + reg_rdata_next[11:8] = range_attr_28_write_access_28_qs; + reg_rdata_next[15:12] = range_attr_28_execute_access_28_qs; + reg_rdata_next[19:16] = range_attr_28_log_denied_access_28_qs; + end + + racl_addr_hit_read[133]: begin + reg_rdata_next[3:0] = range_attr_29_enable_29_qs; + reg_rdata_next[7:4] = range_attr_29_read_access_29_qs; + reg_rdata_next[11:8] = range_attr_29_write_access_29_qs; + reg_rdata_next[15:12] = range_attr_29_execute_access_29_qs; + reg_rdata_next[19:16] = range_attr_29_log_denied_access_29_qs; + end + + racl_addr_hit_read[134]: begin + reg_rdata_next[3:0] = range_attr_30_enable_30_qs; + reg_rdata_next[7:4] = range_attr_30_read_access_30_qs; + reg_rdata_next[11:8] = range_attr_30_write_access_30_qs; + reg_rdata_next[15:12] = range_attr_30_execute_access_30_qs; + reg_rdata_next[19:16] = range_attr_30_log_denied_access_30_qs; + end + + racl_addr_hit_read[135]: begin + reg_rdata_next[3:0] = range_attr_31_enable_31_qs; + reg_rdata_next[7:4] = range_attr_31_read_access_31_qs; + reg_rdata_next[11:8] = range_attr_31_write_access_31_qs; + reg_rdata_next[15:12] = range_attr_31_execute_access_31_qs; + reg_rdata_next[19:16] = range_attr_31_log_denied_access_31_qs; + end + + racl_addr_hit_read[136]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_0_read_perm_0_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_0_write_perm_0_qs; + end + + racl_addr_hit_read[137]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_1_read_perm_1_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_1_write_perm_1_qs; + end + + racl_addr_hit_read[138]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_2_read_perm_2_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_2_write_perm_2_qs; + end + + racl_addr_hit_read[139]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_3_read_perm_3_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_3_write_perm_3_qs; + end + + racl_addr_hit_read[140]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_4_read_perm_4_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_4_write_perm_4_qs; + end + + racl_addr_hit_read[141]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_5_read_perm_5_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_5_write_perm_5_qs; + end + + racl_addr_hit_read[142]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_6_read_perm_6_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_6_write_perm_6_qs; + end + + racl_addr_hit_read[143]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_7_read_perm_7_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_7_write_perm_7_qs; + end + + racl_addr_hit_read[144]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_8_read_perm_8_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_8_write_perm_8_qs; + end + + racl_addr_hit_read[145]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_9_read_perm_9_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_9_write_perm_9_qs; + end + + racl_addr_hit_read[146]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_10_read_perm_10_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_10_write_perm_10_qs; + end + + racl_addr_hit_read[147]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_11_read_perm_11_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_11_write_perm_11_qs; + end + + racl_addr_hit_read[148]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_12_read_perm_12_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_12_write_perm_12_qs; + end + + racl_addr_hit_read[149]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_13_read_perm_13_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_13_write_perm_13_qs; + end + + racl_addr_hit_read[150]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_14_read_perm_14_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_14_write_perm_14_qs; + end + + racl_addr_hit_read[151]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_15_read_perm_15_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_15_write_perm_15_qs; + end + + racl_addr_hit_read[152]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_16_read_perm_16_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_16_write_perm_16_qs; + end + + racl_addr_hit_read[153]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_17_read_perm_17_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_17_write_perm_17_qs; + end + + racl_addr_hit_read[154]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_18_read_perm_18_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_18_write_perm_18_qs; + end + + racl_addr_hit_read[155]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_19_read_perm_19_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_19_write_perm_19_qs; + end + + racl_addr_hit_read[156]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_20_read_perm_20_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_20_write_perm_20_qs; + end + + racl_addr_hit_read[157]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_21_read_perm_21_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_21_write_perm_21_qs; + end + + racl_addr_hit_read[158]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_22_read_perm_22_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_22_write_perm_22_qs; + end + + racl_addr_hit_read[159]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_23_read_perm_23_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_23_write_perm_23_qs; + end + + racl_addr_hit_read[160]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_24_read_perm_24_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_24_write_perm_24_qs; + end + + racl_addr_hit_read[161]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_25_read_perm_25_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_25_write_perm_25_qs; + end + + racl_addr_hit_read[162]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_26_read_perm_26_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_26_write_perm_26_qs; + end + + racl_addr_hit_read[163]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_27_read_perm_27_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_27_write_perm_27_qs; + end + + racl_addr_hit_read[164]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_28_read_perm_28_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_28_write_perm_28_qs; + end + + racl_addr_hit_read[165]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_29_read_perm_29_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_29_write_perm_29_qs; + end + + racl_addr_hit_read[166]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_30_read_perm_30_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_30_write_perm_30_qs; + end + + racl_addr_hit_read[167]: begin + reg_rdata_next[15:0] = range_racl_policy_shadowed_31_read_perm_31_qs; + reg_rdata_next[31:16] = range_racl_policy_shadowed_31_write_perm_31_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + logic rst_done; + logic shadow_rst_done; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_done <= '0; + end else begin + rst_done <= 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin + if (!rst_shadowed_ni) begin + shadow_rst_done <= '0; + end else begin + shadow_rst_done <= 1'b1; + end + end + + // both shadow and normal resets have been released + assign shadow_busy = ~(rst_done & shadow_rst_done); + + // Collect up storage and update errors + assign shadowed_storage_err_o = |{ + range_racl_policy_shadowed_0_read_perm_0_storage_err, + range_racl_policy_shadowed_0_write_perm_0_storage_err, + range_racl_policy_shadowed_1_read_perm_1_storage_err, + range_racl_policy_shadowed_1_write_perm_1_storage_err, + range_racl_policy_shadowed_2_read_perm_2_storage_err, + range_racl_policy_shadowed_2_write_perm_2_storage_err, + range_racl_policy_shadowed_3_read_perm_3_storage_err, + range_racl_policy_shadowed_3_write_perm_3_storage_err, + range_racl_policy_shadowed_4_read_perm_4_storage_err, + range_racl_policy_shadowed_4_write_perm_4_storage_err, + range_racl_policy_shadowed_5_read_perm_5_storage_err, + range_racl_policy_shadowed_5_write_perm_5_storage_err, + range_racl_policy_shadowed_6_read_perm_6_storage_err, + range_racl_policy_shadowed_6_write_perm_6_storage_err, + range_racl_policy_shadowed_7_read_perm_7_storage_err, + range_racl_policy_shadowed_7_write_perm_7_storage_err, + range_racl_policy_shadowed_8_read_perm_8_storage_err, + range_racl_policy_shadowed_8_write_perm_8_storage_err, + range_racl_policy_shadowed_9_read_perm_9_storage_err, + range_racl_policy_shadowed_9_write_perm_9_storage_err, + range_racl_policy_shadowed_10_read_perm_10_storage_err, + range_racl_policy_shadowed_10_write_perm_10_storage_err, + range_racl_policy_shadowed_11_read_perm_11_storage_err, + range_racl_policy_shadowed_11_write_perm_11_storage_err, + range_racl_policy_shadowed_12_read_perm_12_storage_err, + range_racl_policy_shadowed_12_write_perm_12_storage_err, + range_racl_policy_shadowed_13_read_perm_13_storage_err, + range_racl_policy_shadowed_13_write_perm_13_storage_err, + range_racl_policy_shadowed_14_read_perm_14_storage_err, + range_racl_policy_shadowed_14_write_perm_14_storage_err, + range_racl_policy_shadowed_15_read_perm_15_storage_err, + range_racl_policy_shadowed_15_write_perm_15_storage_err, + range_racl_policy_shadowed_16_read_perm_16_storage_err, + range_racl_policy_shadowed_16_write_perm_16_storage_err, + range_racl_policy_shadowed_17_read_perm_17_storage_err, + range_racl_policy_shadowed_17_write_perm_17_storage_err, + range_racl_policy_shadowed_18_read_perm_18_storage_err, + range_racl_policy_shadowed_18_write_perm_18_storage_err, + range_racl_policy_shadowed_19_read_perm_19_storage_err, + range_racl_policy_shadowed_19_write_perm_19_storage_err, + range_racl_policy_shadowed_20_read_perm_20_storage_err, + range_racl_policy_shadowed_20_write_perm_20_storage_err, + range_racl_policy_shadowed_21_read_perm_21_storage_err, + range_racl_policy_shadowed_21_write_perm_21_storage_err, + range_racl_policy_shadowed_22_read_perm_22_storage_err, + range_racl_policy_shadowed_22_write_perm_22_storage_err, + range_racl_policy_shadowed_23_read_perm_23_storage_err, + range_racl_policy_shadowed_23_write_perm_23_storage_err, + range_racl_policy_shadowed_24_read_perm_24_storage_err, + range_racl_policy_shadowed_24_write_perm_24_storage_err, + range_racl_policy_shadowed_25_read_perm_25_storage_err, + range_racl_policy_shadowed_25_write_perm_25_storage_err, + range_racl_policy_shadowed_26_read_perm_26_storage_err, + range_racl_policy_shadowed_26_write_perm_26_storage_err, + range_racl_policy_shadowed_27_read_perm_27_storage_err, + range_racl_policy_shadowed_27_write_perm_27_storage_err, + range_racl_policy_shadowed_28_read_perm_28_storage_err, + range_racl_policy_shadowed_28_write_perm_28_storage_err, + range_racl_policy_shadowed_29_read_perm_29_storage_err, + range_racl_policy_shadowed_29_write_perm_29_storage_err, + range_racl_policy_shadowed_30_read_perm_30_storage_err, + range_racl_policy_shadowed_30_write_perm_30_storage_err, + range_racl_policy_shadowed_31_read_perm_31_storage_err, + range_racl_policy_shadowed_31_write_perm_31_storage_err + }; + assign shadowed_update_err_o = |{ + range_racl_policy_shadowed_0_read_perm_0_update_err, + range_racl_policy_shadowed_0_write_perm_0_update_err, + range_racl_policy_shadowed_1_read_perm_1_update_err, + range_racl_policy_shadowed_1_write_perm_1_update_err, + range_racl_policy_shadowed_2_read_perm_2_update_err, + range_racl_policy_shadowed_2_write_perm_2_update_err, + range_racl_policy_shadowed_3_read_perm_3_update_err, + range_racl_policy_shadowed_3_write_perm_3_update_err, + range_racl_policy_shadowed_4_read_perm_4_update_err, + range_racl_policy_shadowed_4_write_perm_4_update_err, + range_racl_policy_shadowed_5_read_perm_5_update_err, + range_racl_policy_shadowed_5_write_perm_5_update_err, + range_racl_policy_shadowed_6_read_perm_6_update_err, + range_racl_policy_shadowed_6_write_perm_6_update_err, + range_racl_policy_shadowed_7_read_perm_7_update_err, + range_racl_policy_shadowed_7_write_perm_7_update_err, + range_racl_policy_shadowed_8_read_perm_8_update_err, + range_racl_policy_shadowed_8_write_perm_8_update_err, + range_racl_policy_shadowed_9_read_perm_9_update_err, + range_racl_policy_shadowed_9_write_perm_9_update_err, + range_racl_policy_shadowed_10_read_perm_10_update_err, + range_racl_policy_shadowed_10_write_perm_10_update_err, + range_racl_policy_shadowed_11_read_perm_11_update_err, + range_racl_policy_shadowed_11_write_perm_11_update_err, + range_racl_policy_shadowed_12_read_perm_12_update_err, + range_racl_policy_shadowed_12_write_perm_12_update_err, + range_racl_policy_shadowed_13_read_perm_13_update_err, + range_racl_policy_shadowed_13_write_perm_13_update_err, + range_racl_policy_shadowed_14_read_perm_14_update_err, + range_racl_policy_shadowed_14_write_perm_14_update_err, + range_racl_policy_shadowed_15_read_perm_15_update_err, + range_racl_policy_shadowed_15_write_perm_15_update_err, + range_racl_policy_shadowed_16_read_perm_16_update_err, + range_racl_policy_shadowed_16_write_perm_16_update_err, + range_racl_policy_shadowed_17_read_perm_17_update_err, + range_racl_policy_shadowed_17_write_perm_17_update_err, + range_racl_policy_shadowed_18_read_perm_18_update_err, + range_racl_policy_shadowed_18_write_perm_18_update_err, + range_racl_policy_shadowed_19_read_perm_19_update_err, + range_racl_policy_shadowed_19_write_perm_19_update_err, + range_racl_policy_shadowed_20_read_perm_20_update_err, + range_racl_policy_shadowed_20_write_perm_20_update_err, + range_racl_policy_shadowed_21_read_perm_21_update_err, + range_racl_policy_shadowed_21_write_perm_21_update_err, + range_racl_policy_shadowed_22_read_perm_22_update_err, + range_racl_policy_shadowed_22_write_perm_22_update_err, + range_racl_policy_shadowed_23_read_perm_23_update_err, + range_racl_policy_shadowed_23_write_perm_23_update_err, + range_racl_policy_shadowed_24_read_perm_24_update_err, + range_racl_policy_shadowed_24_write_perm_24_update_err, + range_racl_policy_shadowed_25_read_perm_25_update_err, + range_racl_policy_shadowed_25_write_perm_25_update_err, + range_racl_policy_shadowed_26_read_perm_26_update_err, + range_racl_policy_shadowed_26_write_perm_26_update_err, + range_racl_policy_shadowed_27_read_perm_27_update_err, + range_racl_policy_shadowed_27_write_perm_27_update_err, + range_racl_policy_shadowed_28_read_perm_28_update_err, + range_racl_policy_shadowed_28_write_perm_28_update_err, + range_racl_policy_shadowed_29_read_perm_29_update_err, + range_racl_policy_shadowed_29_write_perm_29_update_err, + range_racl_policy_shadowed_30_read_perm_30_update_err, + range_racl_policy_shadowed_30_write_perm_30_update_err, + range_racl_policy_shadowed_31_read_perm_31_update_err, + range_racl_policy_shadowed_31_write_perm_31_update_err + }; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + logic unused_policy_sel; + assign unused_policy_sel = ^racl_policies_i; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/BUILD new file mode 100644 index 00000000000..490c5dca631 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/BUILD @@ -0,0 +1,25 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.svg", + ]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/README.md new file mode 100644 index 00000000000..a1871a013dc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/README.md @@ -0,0 +1,73 @@ +# Alert Handler Technical Specification + +[`alert_handler`](https://reports.opentitan.org/hw/top_earlgrey/ip_autogen/alert_handler/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/alert_handler/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/alert_handler/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/alert_handler/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/alert_handler/code.svg) + +# Overview + +This document specifies the functionality of the alert handler mechanism. +The alert handler is a module that is a peripheral on the chip interconnect bus, and thus follows the [Comportability Specification](../../../../doc/contributing/hw/comportability/README.md). +It gathers alerts - defined as interrupt-type signals from other peripherals that are designated as potential security threats - throughout the design, and converts them to interrupts that the processor can handle. +If the processor does not handle them, the alert handler mechanism provides hardware responses to handle the threat. + + +## Features + +- Differentially-signaled, asynchronous alert inputs from `NAlerts` peripheral sources, where `NAlerts` is a function of the requirements of the peripherals. + +- Ping testing of alert sources: + - responder module requests periodic alert response from each source to ensure proper wiring. + - reset-asserted and clock-gated information is used to temporarily pause the ping mechanism on alert channels that are in a low-power state. + +- Register locking on all configuration registers. + - Once locked, can not be modified by software until next system reset. + +- Register-based assignment of alert to alert-class. + - Four classes, can be individually disabled. + - Each class generates one interrupt. + - Disambiguation history for software to determine which alert caused the class interrupt. + - Each class has configurable response time for escalation. + - Disable allows for ignoring alerts, should only be used in cases when alerts are faulty. + Undesirable access is enforced by locking the register state after initial configuration. + +- Register-based escalation controls. + - Number of alerts in class before escalation. + - Timeout for unhandled alert IRQs can also trigger escalation. + - Configurable escalation enables for 4 escalation signals. + - Could map to NMI, wipe secrets signal, lower privilege, chip reset, etc. + - Escalation signals differentially-signaled with heartbeat, will trigger response if differential or heartbeat failure at destination. + - Configurable time in cycles between each escalation level. + +- Two locally sourced hardware alerts. + - Differential signaling from a source has failed. + - Ping response from a source has failed. + + +## Description + +The alert handler module manages incoming alerts from throughout the system, classifies them, sends interrupts, and escalates interrupts to hardware responses if the processor does not respond to any interrupts. +The intention is for this module to be a stand-in for security responses in the case where the processor can not handle the security alerts. + +It is first notable that all security alerts are rare events. +Module and top level designers should only designate events as alerts if they are expected to never happen, and if they have potential security consequences. +Examples are parity errors (which might indicate an attack), illegal actions on cryptography or security modules, physical sensors of environmental modification (e.g. voltage, temperature), etc. +Alerts will be routed through this module and initially converted to interrupts for the processor to handle. +The expectation is that the secure operating system has a protocol for handling any such alert interrupt in software. +The operating system should respond, then clear the interrupt. +Since these are possible security attacks, the response is not always obvious, but the response is beyond the scope of this document. + +This module is designed to help the full chip respond to security threats in the case where the processor is not trusted: either it has been attacked, or is not responding. +It does this by escalating alerts beyond a processor interrupt. +It provides four such escalation signals that can be routed to chip functions for attack responses. +This could include such functions as wiping secret chip material, power down, reset, etc. +It is beyond the scope of this document to specify what those escalation responses are at the chip level. + +To ease software management of alerts, classification is provided whereby each alert can be classified into one of four classes. +How the classification is done by software is beyond the scope of this document, but it is suggested that alerts of a similar profile (risk of occurring, level of security concern, frequency of false trigger, etc) are classed together. +For each class a counter of alerts is kept, clearable by software. +If that counter exceeds a programmable maximum value, then the escalation protocol for that class begins. + +The details for alert signaling, classification, and escalation are all given in the Theory of Operations section. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler.core new file mode 100644 index 00000000000..4f752c1db6a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler.core @@ -0,0 +1,36 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:alert_handler:0.1 +description: "Alert Handler" + +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:alert_handler_component:0.1 + - lowrisc:darjeeling_no_ibex_ip:alert_handler_reg:0.1 + file_type: systemVerilogSource + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: alert_handler + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler_component.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler_component.core new file mode 100644 index 00000000000..a51686efbc4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler_component.core @@ -0,0 +1,62 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:alert_handler_component:0.1 +description: "Alert Handler component without the CSRs" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:prim:esc + - lowrisc:prim:double_lfsr + - lowrisc:prim:count + - lowrisc:prim:edn_req + - lowrisc:prim:buf + - lowrisc:prim:mubi + - lowrisc:prim:sparse_fsm + - lowrisc:darjeeling_no_ibex_ip:alert_handler_reg + files: + - rtl/alert_handler_reg_wrap.sv + - rtl/alert_handler_lpg_ctrl.sv + - rtl/alert_handler_class.sv + - rtl/alert_handler_ping_timer.sv + - rtl/alert_handler_esc_timer.sv + - rtl/alert_handler_accu.sv + - rtl/alert_handler.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/alert_handler.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/alert_handler.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler_pkg.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler_pkg.core new file mode 100644 index 00000000000..0c1dab899ac --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler_pkg.core @@ -0,0 +1,42 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:alert_handler_pkg:0.1 +description: "Alert Handler constants in packages" + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + files: + - rtl/alert_handler_reg_pkg.sv + - rtl/alert_handler_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler_reg.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler_reg.core new file mode 100644 index 00000000000..2c06e4da1ca --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/alert_handler_reg.core @@ -0,0 +1,23 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:alert_handler_reg:0.1 +description: "Auto-generated alert handler register sources" + +filesets: + files_rtl: + depend: + - lowrisc:prim:subreg + - lowrisc:ip:tlul + - lowrisc:prim:subreg + - lowrisc:darjeeling_no_ibex_ip:alert_handler_pkg + files: + - rtl/alert_handler_reg_top.sv + file_type: systemVerilogSource + + +targets: + default: &default_target + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/BUILD new file mode 100644 index 00000000000..a3ee8786dec --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/BUILD @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_alert_handler.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = glob([ + "alert_handler.hjson", + "*_testplan.hjson", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/alert_handler.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/alert_handler.hjson new file mode 100644 index 00000000000..b4e738fdb40 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/alert_handler.hjson @@ -0,0 +1,2066 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +# ALERT_HANDLER register template + +{ + name: "alert_handler", + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "32", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_alert_handler" + version: "1.0.1", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "Use both FPV and DV to perform block level verification.", + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_edn_i", reset: "rst_edn_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device", hier_path: "u_reg_wrap.u_reg" } + ], + regwidth: "32", + # The number of escalation severities and ping count width parameters + # have a local and non-local varieties instantiated with the same value. + # This is to work around the restriction in CSR generation to only allow + # local parameters, or the value may become inconsistent when the + # parameter gets an override. + param_list: [ + // Random netlist constants + { name: "RndCnstLfsrSeed", + desc: "Compile-time random bits for initial LFSR seed", + type: "alert_handler_pkg::lfsr_seed_t" + randcount: "32", + randtype: "data", // randomize randcount databits + } + { name: "RndCnstLfsrPerm", + desc: "Compile-time random permutation for LFSR output", + type: "alert_handler_pkg::lfsr_perm_t" + randcount: "32", + randtype: "perm", // random permutation for randcount elements + } + // Normal parameters + { name: "NAlerts", + desc: "Number of alert channels.", + type: "int", + default: "99", + local: "true" + }, + { name: "NLpg", + desc: "Number of LPGs.", + type: "int", + default: "16", + local: "true" + }, + { name: "NLpgWidth", + desc: "Width of LPG ID.", + type: "int", + default: "5", + local: "true" + }, + { name: "LpgMap", + desc: ''' + Defines a mapping from alerts to LPGs. + ''' + type: "logic [NAlerts-1:0][NLpgWidth-1:0]", + default: ''' + { + 5'd11, + 5'd11, + 5'd9, + 5'd9, + 5'd3, + 5'd3, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd15, + 5'd15, + 5'd14, + 5'd14, + 5'd13, + 5'd12, + 5'd12, + 5'd11, + 5'd10, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd7, + 5'd6, + 5'd6, + 5'd6, + 5'd6, + 5'd6, + 5'd5, + 5'd4, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd2, + 5'd1, + 5'd0, + 5'd0 + } + ''', + local: "true" + }, + { name: "EscCntDw", + desc: "Width of the escalation timer.", + type: "int", + default: "32", + local: "true" + }, + { name: "AccuCntDw", + desc: "Width of the accumulation counter.", + type: "int", + default: "16", + local: "true" + }, + { name: "AsyncOn", + desc: ''' + Each bit of this parameter corresponds to an escalation channel and + defines whether the protocol is synchronous (0) or asynchronous (1). + ''' + type: "logic [NAlerts-1:0]", + default: ''' + { + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1 + } + ''' + local: "true" + }, + { name: "N_CLASSES", + desc: "Number of classes", + type: "int", + default: "4", + local: "true" + }, + { name: "EscNumSeverities", + desc: "Number of escalation severities as regular parameter", + type: "int", + # NOTE: If this value is to be changed, pass the exposed parameter as + # a regular override to all IPs with prim_esc_receiver + default: "4", + expose: "true", + local: "false" + }, + { name: "N_ESC_SEV", + desc: "Number of escalation severities", + type: "int", + # NOTE: If this value is to be changed, ensure all IPs with + # prim_esc_receiver get updated as well. + default: "4", + local: "true" + }, + { name: "N_PHASES", + desc: "Number of escalation phases", + type: "int", + default: "4", + local: "true" + }, + { name: "N_LOC_ALERT", + desc: "Number of local alerts", + type: "int", + default: "7", + local: "true" + }, + { name: "EscPingCountWidth", + desc: "Width of ping counter as regular parameter", + type: "int", + # NOTE: If this value is to be changed, pass the exposed parameter as + # a regular override to all IPs with prim_esc_receiver + default: "16", + expose: "true", + local: "false" + }, + { name: "PING_CNT_DW", + desc: "Width of ping counter", + type: "int", + # NOTE: If this value is to be changed, ensure all IPs with + # prim_esc_receiver get updated as well. + default: "16", + local: "true" + }, + { name: "PHASE_DW", + desc: "Width of phase ID", + type: "int", + default: "2", + local: "true" + }, + { name: "CLASS_DW", + desc: "Width of class ID", + type: "int", + default: "2", + local: "true" + }, + { name: "LOCAL_ALERT_ID_ALERT_PINGFAIL", + desc: "Local alert ID for alert ping failure.", + type: "int", + default: "0", + local: "true" + }, + { name: "LOCAL_ALERT_ID_ESC_PINGFAIL", + desc: "Local alert ID for escalation ping failure.", + type: "int", + default: "1", + local: "true" + }, + { name: "LOCAL_ALERT_ID_ALERT_INTEGFAIL", + desc: "Local alert ID for alert integrity failure.", + type: "int", + default: "2", + local: "true" + }, + { name: "LOCAL_ALERT_ID_ESC_INTEGFAIL", + desc: "Local alert ID for escalation integrity failure.", + type: "int", + default: "3", + local: "true" + }, + { name: "LOCAL_ALERT_ID_BUS_INTEGFAIL", + desc: "Local alert ID for bus integrity failure.", + type: "int", + default: "4", + local: "true" + }, + { name: "LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR", + desc: "Local alert ID for shadow register update error.", + type: "int", + default: "5", + local: "true" + }, + { name: "LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR", + desc: "Local alert ID for shadow register storage error.", + type: "int", + default: "6", + local: "true" + }, + { name: "LOCAL_ALERT_ID_LAST", + desc: "Last local alert ID.", + type: "int", + default: "6", + local: "true" + }, + ], + + inter_signal_list: [ + { struct: "alert_crashdump", + type: "uni", + name: "crashdump", + act: "req", + package: "alert_handler_pkg" + }, + { struct: "edn" + type: "req_rsp" + name: "edn" + act: "req" + width: "1" + package: "edn_pkg" + }, + { struct: "esc_rx" + type: "uni" + name: "esc_rx" + act: "rcv" + width: "4", // N_ESC_SEV + package: "prim_esc_pkg" + }, + { struct: "esc_tx" + type: "uni" + name: "esc_tx" + act: "req" + width: "4", // N_ESC_SEV + package: "prim_esc_pkg" + }, + ] + + features: [ + { name: "ALERT_HANDLER.ALERT.OBSERVE", + desc: ''' + All incoming alerts can be observed by the alert handler. + ''' + } + { name: "ALERT_HANDLER.ALERT.INTERRUPT", + desc: ''' + All alert classes can raise an interrupt when an alert that is + allocated to them is raised. + ''' + } + { name: "ALERT_HANDLER.ALERT.ESCALATE", + desc: ''' + All incoming alerts can trigger the alert escalation mechanisms + of the classes they are allocated to + ''' + } + { + name: "ALERT_HANDLER.PING_TIMER", + desc: ''' + The alert handler periodically pings all alert receivers and + will raise an alert if the ping isn't responded to in good time + ''' + } + { name: "ALERT_HANDLER.ESCALATION.COUNT", + desc: ''' + An escalation can be triggered when the number of alerts seen in + a particular class exceeds a software programmable threshold + ''' + } + { name: "ALERT_HANDLER.ESCALATION.TIMEOUT", + desc: ''' + An escalation can be triggered when an interrupt from a class + isn't acknowledged after a software programmable timeout + ''' + } + { name: "ALERT_HANDLER.ESCALATION.PHASES", + desc: ''' + Each alert class can trigger the same 4 escalation phases. A + programmable timer specifies the delay between each of the + escalation phases. The actions taken on each of the escalation + signals are specific to the top-level integration. + ''' + } + { + name: "ALERT_HANDLER.CRASH_DUMP", + desc: ''' + A crashdump with the state of CSRs and alert handler state bits + is made available. When a programmable latching trigger condition + is met the crashdump is held constant at its value on that + trigger condition so it can be recorded and made available for + later analysis + ''' + } + ] + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "CONFIG.SHADOW", + desc: "Important CSRs are shadowed." + } + { name: "PING_TIMER.CONFIG.REGWEN", + desc: "The ping timer configuration registers are REGWEN protected." + } + { name: "ALERT.CONFIG.REGWEN", + desc: "The individual alert enables are REGWEN protected." + } + { name: "ALERT_LOC.CONFIG.REGWEN", + desc: "The individual local alert enables are REGWEN protected." + } + { name: "CLASS.CONFIG.REGWEN", + desc: "The class configuration registers are REGWEN protected." + } + { name: "ALERT.INTERSIG.DIFF", + desc: "Differentially encoded alert channels." + } + { name: "LPG.INTERSIG.MUBI", + desc: "LPG signals are encoded with MUBI types." + } + { name: "ESC.INTERSIG.DIFF", + desc: "Differentially encoded escalation channels." + } + { name: "ALERT_RX.INTERSIG.BKGN_CHK", + desc: "Periodic background checks on alert channels (ping mechanism)." + } + { name: "ESC_TX.INTERSIG.BKGN_CHK", + desc: "Periodic background checks on escalation channels (ping mechanism)." + } + { name: "ESC_RX.INTERSIG.BKGN_CHK", + desc: "Escalation receivers can detect absence of periodic ping requests." + } + { name: "ESC_TIMER.FSM.SPARSE", + desc: "Escalation timer FSMs are sparsely encoded." + } + { name: "PING_TIMER.FSM.SPARSE", + desc: "Ping timer FSM is sparsely encoded." + } + { name: "ESC_TIMER.FSM.LOCAL_ESC", + desc: "Escalation timer FSMs move into an invalid state upon local escalation." + } + { name: "PING_TIMER.FSM.LOCAL_ESC", + desc: "Ping timer FSM moves into an invalid state upon local escalation." + } + { name: "ESC_TIMER.FSM.GLOBAL_ESC", + desc: ''' + The escalation timer FSMs are the root of global escalation, + hence if any of them moves into an invalid state by virtue of + ESC_TIMER.FSM.LOCAL_ESC, this will trigger all escalation actions + and thereby global escalation as well. + ''' + } + { name: "ACCU.CTR.REDUN", + desc: "Accumulator counters employ a cross-counter implementation." + } + { name: "ESC_TIMER.CTR.REDUN", + desc: "Escalation timer counters employ a duplicated counter implementation." + } + { name: "PING_TIMER.CTR.REDUN", + desc: "Ping timer counters employ a duplicated counter implementation." + } + { name: "PING_TIMER.LFSR.REDUN", + desc: "Ping timer LFSR is redundant." + } + ] + +# interrupt registers for the classes + interrupt_list: [ + { name: "classa", + desc: ''' + Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. + ''', + }, + { name: "classb", + desc: ''' + Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. + ''', + }, + { name: "classc", + desc: ''' + Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. + ''', + }, + { name: "classd", + desc: ''' + Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. + ''', + }, + ], + + registers: [ +# register lock for ping timeout counter + { name: "PING_TIMER_REGWEN", + desc: ''' + Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { + bits: "0", + desc: ''' + When true, the !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED registers can be modified. + When false, they become read-only. Defaults true, write one to clear. + This should be cleared once the alert handler has been configured and the ping + timer mechanism has been kicked off. + ''' + resval: 1, + }, + ] + }, + { name: "PING_TIMEOUT_CYC_SHADOWED", + desc: ''' + Ping timeout cycle count. + ''' + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "PING_TIMER_REGWEN", + fields: [ + { + bits: "PING_CNT_DW-1:0", + resval: 256, + desc: ''' + Timeout value in cycles. + If an alert receiver or an escalation sender does not respond to a ping within this timeout window, a pingfail alert will be raised. + It is recommended to set this value to the equivalent of 256 cycles of the slowest alert sender clock domain in the system (or greater). + ''' + } + ] + } + { name: "PING_TIMER_EN_SHADOWED", + desc: ''' + Ping timer enable. + ''' + shadowed: "true", + swaccess: "rw1s", + hwaccess: "hro", + regwen: "PING_TIMER_REGWEN", + fields: [ + { + bits: "0", + resval: 0, + desc: ''' + Setting this to 1 enables the ping timer mechanism. + This bit cannot be cleared to 0 once it has been set to 1. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''' + } + ] + } +# all alerts + { multireg: { name: "ALERT_REGWEN", + desc: "Register write enable for alert enable bits.", + count: "NAlerts", + compact: "false", + swaccess: "rw0c", + hwaccess: "hro", + hwqe: "false", + cname: "alert", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Alert configuration write enable bit. + If this is cleared to 0, the corresponding !!ALERT_EN_SHADOWED + and !!ALERT_CLASS_SHADOWED bits are not writable anymore. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "ALERT_EN_SHADOWED", + desc: '''Enable register for alerts. + ''', + count: "NAlerts", + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "ALERT_REGWEN", + regwen_multi: "true", + cname: "alert", + tags: [// Enable `alert_en` might cause top-level escalators to trigger + // unexpected reset + "excl:CsrAllTests:CsrExclWrite"] + fields: [ + { bits: "0", + name: "EN_A", + resval: 0 + desc: ''' + Alert enable bit. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''' + } + ] + } + }, + { multireg: { name: "ALERT_CLASS_SHADOWED", + desc: '''Class assignment of alerts. + ''', + count: "NAlerts", + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "ALERT_REGWEN", + regwen_multi: "true", + cname: "alert", + fields: [ + { + bits: "CLASS_DW-1:0", + name: "CLASS_A", + resval: 0 + desc: "Classification ", + enum: [ + { value: "0", name: "ClassA", desc: "" }, + { value: "1", name: "ClassB", desc: "" }, + { value: "2", name: "ClassC", desc: "" }, + { value: "3", name: "ClassD", desc: "" }, + ] + } + ] + } + }, + { multireg: { + name: "ALERT_CAUSE", + desc: "Alert Cause Register", + count: "NAlerts", + compact: "false", + cname: "ALERT", + swaccess: "rw1c", + hwaccess: "hrw", + fields: [ + { bits: "0", name: "A", desc: "Cause bit ", resval: 0} + ], + } + }, +# local alerts + { multireg: { name: "LOC_ALERT_REGWEN", + desc: "Register write enable for alert enable bits.", + count: "N_LOC_ALERT", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "LOC_ALERT", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Alert configuration write enable bit. + If this is cleared to 0, the corresponding !!LOC_ALERT_EN_SHADOWED + and !!LOC_ALERT_CLASS_SHADOWED bits are not writable anymore. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "LOC_ALERT_EN_SHADOWED", + desc: + ''' + Enable register for the local alerts + "alert pingfail" (0), "escalation pingfail" (1), + "alert integfail" (2), "escalation integfail" (3), + "bus integrity failure" (4), "shadow reg update error" (5) + and "shadow reg storage error" (6). + ''', + count: "N_LOC_ALERT", + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "LOC_ALERT_REGWEN", + regwen_multi: "true", + cname: "LOC_ALERT", + fields: [ + { bits: "0", + name: "EN_LA", + resval: 0 + desc: ''' + Alert enable bit. + + Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. + ''' + } + ] + } + }, + { multireg: { name: "LOC_ALERT_CLASS_SHADOWED", + desc: ''' + Class assignment of the local alerts + "alert pingfail" (0), "escalation pingfail" (1), + "alert integfail" (2), "escalation integfail" (3), + "bus integrity failure" (4), "shadow reg update error" (5) + and "shadow reg storage error" (6). + ''', + count: "N_LOC_ALERT", + shadowed: "true", + swaccess: "rw", + hwaccess: "hro", + regwen: "LOC_ALERT_REGWEN", + regwen_multi: "true", + cname: "LOC_ALERT", + fields: [ + { + bits: "CLASS_DW-1:0", + name: "CLASS_LA", + resval: 0 + desc: "Classification ", + enum: [ + { value: "0", name: "ClassA", desc: "" }, + { value: "1", name: "ClassB", desc: "" }, + { value: "2", name: "ClassC", desc: "" }, + { value: "3", name: "ClassD", desc: "" }, + ] + } + ] + } + }, + { multireg: { + name: "LOC_ALERT_CAUSE", + desc: '''Alert Cause Register for the local alerts + "alert pingfail" (0), "escalation pingfail" (1), + "alert integfail" (2), "escalation integfail" (3), + "bus integrity failure" (4), "shadow reg update error" (5) + and "shadow reg storage error" (6). + ''', + count: "N_LOC_ALERT", + compact: "false", + cname: "LOC_ALERT", + swaccess: "rw1c", + hwaccess: "hrw", + tags: [// Top level CSR automation test, CPU clock is disabled, so escalation response will + // not send back to alert handler. This will set loc_alert_cause and could not predict + // automatically. + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { bits: "0", name: "LA", desc: "Cause bit ", resval: 0} + ] + } + }, +# classes + + { name: "CLASSA_REGWEN", + desc: ''' + Lock bit for Class A configuration. + ''' + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + Class configuration enable bit. + If this is cleared to 0, the corresponding class configuration + registers cannot be written anymore. + ''', + resval: 1, + } + ] + }, + { name: "CLASSA_CTRL_SHADOWED", + desc: "Escalation control register for alert Class A. Can not be modified if !!CLASSA_REGWEN is false." + swaccess: "rw", + hwaccess: "hro", + regwen: "CLASSA_REGWEN", + shadowed: "true", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Enable escalation mechanisms (accumulation and + interrupt timeout) for Class A. Note that interrupts can fire + regardless of whether the escalation mechanisms are enabled for + this class or not. + ''', + } + { bits: "1", + name: "LOCK", + desc: ''' + Enable automatic locking of escalation counter for class A. + If true, there is no way to stop the escalation protocol for class A + once it has been triggered. + ''' + } + { bits: "2", + name: "EN_E0", + resval: 1, + desc: "Enable escalation signal 0 for Class A", + } + { bits: "3", + name: "EN_E1", + resval: 1, + desc: "Enable escalation signal 1 for Class A", + } + { bits: "4", + name: "EN_E2", + resval: 1, + desc: "Enable escalation signal 2 for Class A", + } + { bits: "5", + name: "EN_E3", + resval: 1, + desc: "Enable escalation signal 3 for Class A", + } + { bits: "7:6", + name: "MAP_E0", + resval: 0, + desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", + } + { bits: "9:8", + name: "MAP_E1", + resval: 1, + desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", + } + { bits: "11:10", + name: "MAP_E2", + resval: 2, + desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", + } + { bits: "13:12", + name: "MAP_E3", + resval: 3, + desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", + } + ] + }, + { name: "CLASSA_CLR_REGWEN", + desc: ''' + Clear enable for escalation protocol of Class A alerts. + ''' + swaccess: "rw0c", + hwaccess: "hwo", + fields: [ + { bits: "0", + desc: '''Register defaults to true, can only be cleared. This register is set + to false by the hardware if the escalation protocol has been triggered and the bit + !!CLASSA_CTRL_SHADOWED.LOCK is true. + ''', + resval: 1, + } + ], + tags: [// The value of this register is set to false only by hardware, under the condition + // that escalation is triggered and the corresponding lock bit is true + // Cannot not be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSA_CLR_SHADOWED", + desc: ''' + Clear for escalation protocol of Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + shadowed: "true", + regwen: "CLASSA_CLR_REGWEN", + fields: [ + { bits: "0", + desc: '''Writing 1 to this register clears the accumulator and aborts escalation + (if it has been triggered). This clear is disabled if !!CLASSA_CLR_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSA_ACCUM_CNT", + desc: ''' + Current accumulation value for alert Class A. Software can clear this register + with a write to !!CLASSA_CLR_SHADOWED register unless !!CLASSA_CLR_REGWEN is false. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "AccuCntDw-1:0" } + ], + tags: [// The value of this register is determined by how many alerts have been triggered + // Cannot be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSA_ACCUM_THRESH_SHADOWED", + desc: ''' + Accumulation threshold value for alert Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "AccuCntDw-1:0", + desc: '''Once the accumulation value register is equal to the threshold escalation will + be triggered on the next alert occurrence within this class A begins. Note that this + register can not be modified if !!CLASSA_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSA_TIMEOUT_CYC_SHADOWED", + desc: ''' + Interrupt timeout in cycles. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''If the interrupt corresponding to this class is not + handled within the specified amount of cycles, escalation will be triggered. + Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero + by default, which disables this feature. Note that this register can not be modified if + !!CLASSA_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSA_CRASHDUMP_TRIGGER_SHADOWED", + desc: ''' + Crashdump trigger configuration for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + resval: "0", + fields: [ + { bits: "PHASE_DW-1:0", + desc: ''' + Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation + timer states. It is recommended to capture the crashdump upon entering the first escalation phase + that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order + to prevent spurious alert events from masking the original alert causes. + Note that this register can not be modified if !!CLASSA_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSA_PHASE0_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 0 for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSA_REGWEN is false.''' + } + ] + } + { name: "CLASSA_PHASE1_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 1 for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSA_REGWEN is false.''' + } + ] + } + { name: "CLASSA_PHASE2_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 2 for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSA_REGWEN is false.''' + } + ] + } + { name: "CLASSA_PHASE3_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 3 for Class A. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSA_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSA_REGWEN is false.''' + } + ] + } + { name: "CLASSA_ESC_CNT", + desc: ''' + Escalation counter in cycles for Class A. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''Returns the current timeout or escalation count (depending on !!CLASSA_STATE). + This register can not be directly cleared. However, SW can indirectly clear as follows. + + If the class is in the Timeout state, the timeout can be aborted by clearing the + corresponding interrupt bit. + + If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be + aborted by writing to !!CLASSA_CLR_SHADOWED. Note however that has no effect if !!CLASSA_REGWEN + is set to false (either by SW or by HW via the !!CLASSA_CTRL_SHADOWED.LOCK feature). + ''' + } + ], + tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted + // Cannot be auto-predicted so excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSA_STATE", + desc: ''' + Current escalation state of Class A. See also !!CLASSA_ESC_CNT. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "2:0", + enum: [ + { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, + { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, + { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, + { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, + { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, + { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, + { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, + { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } + ] + } + ], + tags: [// The current escalation state cannot be auto-predicted + // so this register is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + + { name: "CLASSB_REGWEN", + desc: ''' + Lock bit for Class B configuration. + ''' + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + Class configuration enable bit. + If this is cleared to 0, the corresponding class configuration + registers cannot be written anymore. + ''', + resval: 1, + } + ] + }, + { name: "CLASSB_CTRL_SHADOWED", + desc: "Escalation control register for alert Class B. Can not be modified if !!CLASSB_REGWEN is false." + swaccess: "rw", + hwaccess: "hro", + regwen: "CLASSB_REGWEN", + shadowed: "true", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Enable escalation mechanisms (accumulation and + interrupt timeout) for Class B. Note that interrupts can fire + regardless of whether the escalation mechanisms are enabled for + this class or not. + ''', + } + { bits: "1", + name: "LOCK", + desc: ''' + Enable automatic locking of escalation counter for class B. + If true, there is no way to stop the escalation protocol for class B + once it has been triggered. + ''' + } + { bits: "2", + name: "EN_E0", + resval: 1, + desc: "Enable escalation signal 0 for Class B", + } + { bits: "3", + name: "EN_E1", + resval: 1, + desc: "Enable escalation signal 1 for Class B", + } + { bits: "4", + name: "EN_E2", + resval: 1, + desc: "Enable escalation signal 2 for Class B", + } + { bits: "5", + name: "EN_E3", + resval: 1, + desc: "Enable escalation signal 3 for Class B", + } + { bits: "7:6", + name: "MAP_E0", + resval: 0, + desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", + } + { bits: "9:8", + name: "MAP_E1", + resval: 1, + desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", + } + { bits: "11:10", + name: "MAP_E2", + resval: 2, + desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", + } + { bits: "13:12", + name: "MAP_E3", + resval: 3, + desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", + } + ] + }, + { name: "CLASSB_CLR_REGWEN", + desc: ''' + Clear enable for escalation protocol of Class B alerts. + ''' + swaccess: "rw0c", + hwaccess: "hwo", + fields: [ + { bits: "0", + desc: '''Register defaults to true, can only be cleared. This register is set + to false by the hardware if the escalation protocol has been triggered and the bit + !!CLASSB_CTRL_SHADOWED.LOCK is true. + ''', + resval: 1, + } + ], + tags: [// The value of this register is set to false only by hardware, under the condition + // that escalation is triggered and the corresponding lock bit is true + // Cannot not be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSB_CLR_SHADOWED", + desc: ''' + Clear for escalation protocol of Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + shadowed: "true", + regwen: "CLASSB_CLR_REGWEN", + fields: [ + { bits: "0", + desc: '''Writing 1 to this register clears the accumulator and aborts escalation + (if it has been triggered). This clear is disabled if !!CLASSB_CLR_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSB_ACCUM_CNT", + desc: ''' + Current accumulation value for alert Class B. Software can clear this register + with a write to !!CLASSB_CLR_SHADOWED register unless !!CLASSB_CLR_REGWEN is false. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "AccuCntDw-1:0" } + ], + tags: [// The value of this register is determined by how many alerts have been triggered + // Cannot be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSB_ACCUM_THRESH_SHADOWED", + desc: ''' + Accumulation threshold value for alert Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "AccuCntDw-1:0", + desc: '''Once the accumulation value register is equal to the threshold escalation will + be triggered on the next alert occurrence within this class B begins. Note that this + register can not be modified if !!CLASSB_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSB_TIMEOUT_CYC_SHADOWED", + desc: ''' + Interrupt timeout in cycles. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''If the interrupt corresponding to this class is not + handled within the specified amount of cycles, escalation will be triggered. + Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero + by default, which disables this feature. Note that this register can not be modified if + !!CLASSB_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSB_CRASHDUMP_TRIGGER_SHADOWED", + desc: ''' + Crashdump trigger configuration for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + resval: "0", + fields: [ + { bits: "PHASE_DW-1:0", + desc: ''' + Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation + timer states. It is recommended to capture the crashdump upon entering the first escalation phase + that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order + to prevent spurious alert events from masking the original alert causes. + Note that this register can not be modified if !!CLASSB_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSB_PHASE0_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 0 for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSB_REGWEN is false.''' + } + ] + } + { name: "CLASSB_PHASE1_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 1 for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSB_REGWEN is false.''' + } + ] + } + { name: "CLASSB_PHASE2_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 2 for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSB_REGWEN is false.''' + } + ] + } + { name: "CLASSB_PHASE3_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 3 for Class B. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSB_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSB_REGWEN is false.''' + } + ] + } + { name: "CLASSB_ESC_CNT", + desc: ''' + Escalation counter in cycles for Class B. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''Returns the current timeout or escalation count (depending on !!CLASSB_STATE). + This register can not be directly cleared. However, SW can indirectly clear as follows. + + If the class is in the Timeout state, the timeout can be aborted by clearing the + corresponding interrupt bit. + + If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be + aborted by writing to !!CLASSB_CLR_SHADOWED. Note however that has no effect if !!CLASSB_REGWEN + is set to false (either by SW or by HW via the !!CLASSB_CTRL_SHADOWED.LOCK feature). + ''' + } + ], + tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted + // Cannot be auto-predicted so excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSB_STATE", + desc: ''' + Current escalation state of Class B. See also !!CLASSB_ESC_CNT. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "2:0", + enum: [ + { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, + { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, + { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, + { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, + { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, + { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, + { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, + { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } + ] + } + ], + tags: [// The current escalation state cannot be auto-predicted + // so this register is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + + { name: "CLASSC_REGWEN", + desc: ''' + Lock bit for Class C configuration. + ''' + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + Class configuration enable bit. + If this is cleared to 0, the corresponding class configuration + registers cannot be written anymore. + ''', + resval: 1, + } + ] + }, + { name: "CLASSC_CTRL_SHADOWED", + desc: "Escalation control register for alert Class C. Can not be modified if !!CLASSC_REGWEN is false." + swaccess: "rw", + hwaccess: "hro", + regwen: "CLASSC_REGWEN", + shadowed: "true", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Enable escalation mechanisms (accumulation and + interrupt timeout) for Class C. Note that interrupts can fire + regardless of whether the escalation mechanisms are enabled for + this class or not. + ''', + } + { bits: "1", + name: "LOCK", + desc: ''' + Enable automatic locking of escalation counter for class C. + If true, there is no way to stop the escalation protocol for class C + once it has been triggered. + ''' + } + { bits: "2", + name: "EN_E0", + resval: 1, + desc: "Enable escalation signal 0 for Class C", + } + { bits: "3", + name: "EN_E1", + resval: 1, + desc: "Enable escalation signal 1 for Class C", + } + { bits: "4", + name: "EN_E2", + resval: 1, + desc: "Enable escalation signal 2 for Class C", + } + { bits: "5", + name: "EN_E3", + resval: 1, + desc: "Enable escalation signal 3 for Class C", + } + { bits: "7:6", + name: "MAP_E0", + resval: 0, + desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", + } + { bits: "9:8", + name: "MAP_E1", + resval: 1, + desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", + } + { bits: "11:10", + name: "MAP_E2", + resval: 2, + desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", + } + { bits: "13:12", + name: "MAP_E3", + resval: 3, + desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", + } + ] + }, + { name: "CLASSC_CLR_REGWEN", + desc: ''' + Clear enable for escalation protocol of Class C alerts. + ''' + swaccess: "rw0c", + hwaccess: "hwo", + fields: [ + { bits: "0", + desc: '''Register defaults to true, can only be cleared. This register is set + to false by the hardware if the escalation protocol has been triggered and the bit + !!CLASSC_CTRL_SHADOWED.LOCK is true. + ''', + resval: 1, + } + ], + tags: [// The value of this register is set to false only by hardware, under the condition + // that escalation is triggered and the corresponding lock bit is true + // Cannot not be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSC_CLR_SHADOWED", + desc: ''' + Clear for escalation protocol of Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + shadowed: "true", + regwen: "CLASSC_CLR_REGWEN", + fields: [ + { bits: "0", + desc: '''Writing 1 to this register clears the accumulator and aborts escalation + (if it has been triggered). This clear is disabled if !!CLASSC_CLR_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSC_ACCUM_CNT", + desc: ''' + Current accumulation value for alert Class C. Software can clear this register + with a write to !!CLASSC_CLR_SHADOWED register unless !!CLASSC_CLR_REGWEN is false. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "AccuCntDw-1:0" } + ], + tags: [// The value of this register is determined by how many alerts have been triggered + // Cannot be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSC_ACCUM_THRESH_SHADOWED", + desc: ''' + Accumulation threshold value for alert Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "AccuCntDw-1:0", + desc: '''Once the accumulation value register is equal to the threshold escalation will + be triggered on the next alert occurrence within this class C begins. Note that this + register can not be modified if !!CLASSC_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSC_TIMEOUT_CYC_SHADOWED", + desc: ''' + Interrupt timeout in cycles. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''If the interrupt corresponding to this class is not + handled within the specified amount of cycles, escalation will be triggered. + Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero + by default, which disables this feature. Note that this register can not be modified if + !!CLASSC_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSC_CRASHDUMP_TRIGGER_SHADOWED", + desc: ''' + Crashdump trigger configuration for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + resval: "0", + fields: [ + { bits: "PHASE_DW-1:0", + desc: ''' + Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation + timer states. It is recommended to capture the crashdump upon entering the first escalation phase + that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order + to prevent spurious alert events from masking the original alert causes. + Note that this register can not be modified if !!CLASSC_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSC_PHASE0_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 0 for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSC_REGWEN is false.''' + } + ] + } + { name: "CLASSC_PHASE1_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 1 for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSC_REGWEN is false.''' + } + ] + } + { name: "CLASSC_PHASE2_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 2 for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSC_REGWEN is false.''' + } + ] + } + { name: "CLASSC_PHASE3_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 3 for Class C. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSC_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSC_REGWEN is false.''' + } + ] + } + { name: "CLASSC_ESC_CNT", + desc: ''' + Escalation counter in cycles for Class C. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''Returns the current timeout or escalation count (depending on !!CLASSC_STATE). + This register can not be directly cleared. However, SW can indirectly clear as follows. + + If the class is in the Timeout state, the timeout can be aborted by clearing the + corresponding interrupt bit. + + If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be + aborted by writing to !!CLASSC_CLR_SHADOWED. Note however that has no effect if !!CLASSC_REGWEN + is set to false (either by SW or by HW via the !!CLASSC_CTRL_SHADOWED.LOCK feature). + ''' + } + ], + tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted + // Cannot be auto-predicted so excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSC_STATE", + desc: ''' + Current escalation state of Class C. See also !!CLASSC_ESC_CNT. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "2:0", + enum: [ + { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, + { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, + { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, + { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, + { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, + { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, + { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, + { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } + ] + } + ], + tags: [// The current escalation state cannot be auto-predicted + // so this register is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + + { name: "CLASSD_REGWEN", + desc: ''' + Lock bit for Class D configuration. + ''' + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + Class configuration enable bit. + If this is cleared to 0, the corresponding class configuration + registers cannot be written anymore. + ''', + resval: 1, + } + ] + }, + { name: "CLASSD_CTRL_SHADOWED", + desc: "Escalation control register for alert Class D. Can not be modified if !!CLASSD_REGWEN is false." + swaccess: "rw", + hwaccess: "hro", + regwen: "CLASSD_REGWEN", + shadowed: "true", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Enable escalation mechanisms (accumulation and + interrupt timeout) for Class D. Note that interrupts can fire + regardless of whether the escalation mechanisms are enabled for + this class or not. + ''', + } + { bits: "1", + name: "LOCK", + desc: ''' + Enable automatic locking of escalation counter for class D. + If true, there is no way to stop the escalation protocol for class D + once it has been triggered. + ''' + } + { bits: "2", + name: "EN_E0", + resval: 1, + desc: "Enable escalation signal 0 for Class D", + } + { bits: "3", + name: "EN_E1", + resval: 1, + desc: "Enable escalation signal 1 for Class D", + } + { bits: "4", + name: "EN_E2", + resval: 1, + desc: "Enable escalation signal 2 for Class D", + } + { bits: "5", + name: "EN_E3", + resval: 1, + desc: "Enable escalation signal 3 for Class D", + } + { bits: "7:6", + name: "MAP_E0", + resval: 0, + desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", + } + { bits: "9:8", + name: "MAP_E1", + resval: 1, + desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", + } + { bits: "11:10", + name: "MAP_E2", + resval: 2, + desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", + } + { bits: "13:12", + name: "MAP_E3", + resval: 3, + desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", + } + ] + }, + { name: "CLASSD_CLR_REGWEN", + desc: ''' + Clear enable for escalation protocol of Class D alerts. + ''' + swaccess: "rw0c", + hwaccess: "hwo", + fields: [ + { bits: "0", + desc: '''Register defaults to true, can only be cleared. This register is set + to false by the hardware if the escalation protocol has been triggered and the bit + !!CLASSD_CTRL_SHADOWED.LOCK is true. + ''', + resval: 1, + } + ], + tags: [// The value of this register is set to false only by hardware, under the condition + // that escalation is triggered and the corresponding lock bit is true + // Cannot not be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSD_CLR_SHADOWED", + desc: ''' + Clear for escalation protocol of Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + hwqe: "true", + shadowed: "true", + regwen: "CLASSD_CLR_REGWEN", + fields: [ + { bits: "0", + desc: '''Writing 1 to this register clears the accumulator and aborts escalation + (if it has been triggered). This clear is disabled if !!CLASSD_CLR_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSD_ACCUM_CNT", + desc: ''' + Current accumulation value for alert Class D. Software can clear this register + with a write to !!CLASSD_CLR_SHADOWED register unless !!CLASSD_CLR_REGWEN is false. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "AccuCntDw-1:0" } + ], + tags: [// The value of this register is determined by how many alerts have been triggered + // Cannot be auto-predicted so it is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSD_ACCUM_THRESH_SHADOWED", + desc: ''' + Accumulation threshold value for alert Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "AccuCntDw-1:0", + desc: '''Once the accumulation value register is equal to the threshold escalation will + be triggered on the next alert occurrence within this class D begins. Note that this + register can not be modified if !!CLASSD_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSD_TIMEOUT_CYC_SHADOWED", + desc: ''' + Interrupt timeout in cycles. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''If the interrupt corresponding to this class is not + handled within the specified amount of cycles, escalation will be triggered. + Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero + by default, which disables this feature. Note that this register can not be modified if + !!CLASSD_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSD_CRASHDUMP_TRIGGER_SHADOWED", + desc: ''' + Crashdump trigger configuration for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + resval: "0", + fields: [ + { bits: "PHASE_DW-1:0", + desc: ''' + Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation + timer states. It is recommended to capture the crashdump upon entering the first escalation phase + that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order + to prevent spurious alert events from masking the original alert causes. + Note that this register can not be modified if !!CLASSD_REGWEN is false. + ''' + } + ] + }, + { name: "CLASSD_PHASE0_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 0 for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSD_REGWEN is false.''' + } + ] + } + { name: "CLASSD_PHASE1_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 1 for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSD_REGWEN is false.''' + } + ] + } + { name: "CLASSD_PHASE2_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 2 for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSD_REGWEN is false.''' + } + ] + } + { name: "CLASSD_PHASE3_CYC_SHADOWED", + desc: ''' + Duration of escalation phase 3 for Class D. + ''' + swaccess: "rw", + hwaccess: "hro", + shadowed: "true", + regwen: "CLASSD_REGWEN", + fields: [ + { bits: "EscCntDw-1:0" , + desc: '''Escalation phase duration in cycles. Note that this register can not be + modified if !!CLASSD_REGWEN is false.''' + } + ] + } + { name: "CLASSD_ESC_CNT", + desc: ''' + Escalation counter in cycles for Class D. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "EscCntDw-1:0", + desc: '''Returns the current timeout or escalation count (depending on !!CLASSD_STATE). + This register can not be directly cleared. However, SW can indirectly clear as follows. + + If the class is in the Timeout state, the timeout can be aborted by clearing the + corresponding interrupt bit. + + If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be + aborted by writing to !!CLASSD_CLR_SHADOWED. Note however that has no effect if !!CLASSD_REGWEN + is set to false (either by SW or by HW via the !!CLASSD_CTRL_SHADOWED.LOCK feature). + ''' + } + ], + tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted + // Cannot be auto-predicted so excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + { name: "CLASSD_STATE", + desc: ''' + Current escalation state of Class D. See also !!CLASSD_ESC_CNT. + ''' + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { bits: "2:0", + enum: [ + { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, + { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, + { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, + { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, + { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, + { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, + { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, + { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } + ] + } + ], + tags: [// The current escalation state cannot be auto-predicted + // so this register is excluded from read check + "excl:CsrNonInitTests:CsrExclWriteCheck"] + }, + ], +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/alert_handler_sec_cm_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/alert_handler_sec_cm_testplan.hjson new file mode 100644 index 00000000000..08b11bc5ec9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/alert_handler_sec_cm_testplan.hjson @@ -0,0 +1,156 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../alert_handler/data/alert_handler.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../alert_handler/data/alert_handler_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: "Verify the countermeasure(s) BUS.INTEGRITY." + stage: V2S + tests: ["alert_handler_tl_intg_err"] + } + { + name: sec_cm_config_shadow + desc: "Verify the countermeasure(s) CONFIG.SHADOW." + stage: V2S + tests: ["alert_handler_shadow_reg_errors"] + } + { + name: sec_cm_ping_timer_config_regwen + desc: "Verify the countermeasure(s) PING_TIMER.CONFIG.REGWEN." + stage: V2S + tests: ["alert_handler_smoke"] + } + { + name: sec_cm_alert_config_regwen + desc: "Verify the countermeasure(s) ALERT.CONFIG.REGWEN." + stage: V2S + tests: ["alert_handler_smoke"] + } + { + name: sec_cm_alert_loc_config_regwen + desc: "Verify the countermeasure(s) ALERT_LOC.CONFIG.REGWEN." + stage: V2S + tests: ["alert_handler_smoke"] + } + { + name: sec_cm_class_config_regwen + desc: "Verify the countermeasure(s) CLASS.CONFIG.REGWEN." + stage: V2S + tests: ["alert_handler_smoke"] + } + { + name: sec_cm_alert_intersig_diff + desc: "Verify the countermeasure(s) ALERT.INTERSIG.DIFF." + stage: V2S + tests: ["alert_handler_sig_int_fail"] + } + { + name: sec_cm_lpg_intersig_mubi + desc: "Verify the countermeasure(s) LPG.INTERSIG.MUBI." + stage: V2S + tests: ["alert_handler_lpg"] + } + { + name: sec_cm_esc_intersig_diff + desc: "Verify the countermeasure(s) ESC.INTERSIG.DIFF." + stage: V2S + tests: ["alert_handler_sig_int_fail"] + } + { + name: sec_cm_alert_rx_intersig_bkgn_chk + desc: "Verify the countermeasure(s) ALERT_RX.INTERSIG.BKGN_CHK." + stage: V2S + tests: ["alert_handler_entropy"] + } + { + name: sec_cm_esc_tx_intersig_bkgn_chk + desc: "Verify the countermeasure(s) ESC_TX.INTERSIG.BKGN_CHK." + stage: V2S + tests: ["alert_handler_entropy"] + } + { + name: sec_cm_esc_rx_intersig_bkgn_chk + desc: "Verify the countermeasure(s) ESC_RX.INTERSIG.BKGN_CHK." + stage: V2S + // This test entry is only valid with prim_esc_receiver module, which is not included in the + // alert_handler testbench. Thus this test point will be checked in `prim_esc` testbench and + // top-level testbench. + tests: ["N/A"] + } + { + name: sec_cm_esc_timer_fsm_sparse + desc: "Verify the countermeasure(s) ESC_TIMER.FSM.SPARSE." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_ping_timer_fsm_sparse + desc: "Verify the countermeasure(s) PING_TIMER.FSM.SPARSE." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_esc_timer_fsm_local_esc + desc: "Verify the countermeasure(s) ESC_TIMER.FSM.LOCAL_ESC." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_ping_timer_fsm_local_esc + desc: "Verify the countermeasure(s) PING_TIMER.FSM.LOCAL_ESC." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_esc_timer_fsm_global_esc + desc: "Verify the countermeasure(s) ESC_TIMER.FSM.GLOBAL_ESC." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_accu_ctr_redun + desc: "Verify the countermeasure(s) ACCU.CTR.REDUN." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_esc_timer_ctr_redun + desc: "Verify the countermeasure(s) ESC_TIMER.CTR.REDUN." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_ping_timer_ctr_redun + desc: "Verify the countermeasure(s) PING_TIMER.CTR.REDUN." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + { + name: sec_cm_ping_timer_lfsr_redun + desc: "Verify the countermeasure(s) PING_TIMER.LFSR.REDUN." + stage: V2S + tests: ["alert_handler_sec_cm"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/alert_handler_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/alert_handler_testplan.hjson new file mode 100644 index 00000000000..7de5a99b8fd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/alert_handler_testplan.hjson @@ -0,0 +1,285 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "alert_handler" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/sv/alert_esc_agent/data/alert_agent_basic_testplan.hjson", + "hw/dv/sv/alert_esc_agent/data/alert_agent_additional_testplan.hjson", + "hw/dv/sv/alert_esc_agent/data/esc_agent_basic_testplan.hjson", + "hw/dv/sv/alert_esc_agent/data/esc_agent_additional_testplan.hjson", + // Generated in IP gen area (hw/{top}/ip_autogen). + "alert_handler_sec_cm_testplan.hjson"] + testpoints: [ + { + name: smoke + desc: ''' + - Alert_handler smoke test with one class configured that escalates through all + phases after one alert has been triggered + - Check interrupt pins, alert cause CSR values, escalation pings, and crashdump_o + output values + - Support both synchronous and asynchronous settings + ''' + stage: V1 + tests: ["alert_handler_smoke"] + } + { + name: esc_accum + desc: ''' + Based on the smoke test, this test will focus on testing the escalation accumulation + feature. So all the escalations in the test will be triggered by alert accumulation. + ''' + stage: V2 + tests: ["alert_handler_esc_alert_accum"] + } + { + name: esc_timeout + desc: ''' + Based on the smoke test, this test will focus on testing the escalation timeout + feature. So all the escalations in the test will be triggered by interrupt timeout. + ''' + stage: V2 + tests: ["alert_handler_esc_intr_timeout"] + } + { + name: entropy + desc: ''' + Based on the smoke test, this test enables ping testing, and check if the ping feature + correctly pings all devices within certain period of time. + ''' + stage: V2 + tests: ["alert_handler_entropy"] + } + { + name: sig_int_fail + desc: ''' + This test will randomly inject differential pair failures on alert tx/rx pairs and the + escalator tx/rx pairs. Then check if integrity failure alert is triggered and + escalated. + ''' + stage: V2 + tests: ["alert_handler_sig_int_fail"] + } + { + name: clk_skew + desc: ''' + This test will randomly inject clock skew within the differential pairs. Then check no + alert is raised. + ''' + stage: V2 + tests: ["alert_handler_smoke"] + } + { + name: random_alerts + desc: "Input random alerts and randomly write phase cycles." + stage: V2 + tests: ["alert_handler_random_alerts"] + } + { + name: random_classes + desc: "Based on random_alerts test, this test will also randomly enable interrupt classes." + stage: V2 + tests: ["alert_handler_random_classes"] + } + { + name: ping_timeout + desc: ''' + Based on entropy test, this test request alert_sender and esc_receiver drivers to + randomly create ping requests timeout stimulus. + + Checks: + - Verify interrupt pin and states. + - Verify alert and local alert causes. + - Verify escalation states and counts. + ''' + stage: V2 + tests: ["alert_handler_ping_timeout"] + } + { + name: lpg + desc: ''' + Test alert_handler low_power_group(lpg) request. + + Stimulus: + - Randomly enabled alert_receivers' `alert_en` but disable their ping response. + - Turn on their low-power control by either set `lpg_cg_en_i` or `lpg_rst_en_i`. + Or pause the alert_handler's clk input for a random period of time. + - Enable alert ping timeout local alert. + - Run alert_handler_entropy_vseq. + + Checks: + - Expect no ping timeout error because the alert_receivers are disabled via low-power + group, or because alert_handler's clk input is paused due to sleep mode. + ''' + stage: V2 + tests: ["alert_handler_lpg", "alert_handler_lpg_stub_clk"] + } + { + name: stress_all + desc: ''' + Combine above sequences in one test to run sequentially with the following exclusions: + - CSR sequences: scoreboard disabled + - Ping_corner_cases sequence: included reset in the sequence + ''' + stage: V2 + tests: ["alert_handler_stress_all"] + } + { + name: alert_handler_entropy_stress_test + desc: ''' + Stress the alert_handler's entropy request and make sure there is no spurious alert. + + Stimulus: + - Randomly force the `wait_cyc_mask_i` to a legal value to stress the ping requests. + - Wait for all alerts at least being pinged for a few times. + Checks: + - Check alert_cause and loc_alert_cause registers to make sure there is no spurious + alert being fired. + ''' + stage: V2 + tests: ["alert_handler_entropy_stress"] + } + + { + name: alert_handler_alert_accum_saturation + desc: ''' + This sequence forces all four alert classes' accumulate counters to a large value that + is close to the max saturation value. + Then the sequence triggers alerts until the count saturates. + + Checks: + - Check `accum_cnt` register does not overflow, but stays at the max value. + - Check the correct interrupt fires if even the count saturates. + ''' + stage: V2 + tests: ["alert_handler_alert_accum_saturation"] + } + ] + + covergroups: [ + { + name: accum_cnt_cg + desc: '''Covers escalation due to accumulated alerts. + + - Collect the threshold of accumulated alerts. + - Collect which alert_class exceeds the accumulated count. + - Cross the above coverpoints. + ''' + } + { + name: intr_timeout_cnt_cg + desc: '''Covers escalation due to interrupt timeout. + + - Collect the threshold of interrupt timeout cycles. + - Collect which alert_class exceeds the timeout threshold. + - Cross the above coverpoints. + ''' + } + { + name: esc_sig_length_cg + desc: '''Covers escalation signal length for each escalation signal.''' + } + { + name: clear_intr_cnt_cg + desc: '''Covers interrupt counter being cleared by class_clr_shadowed register.''' + } + { + name: clear_esc_cnt_cg + desc: '''Covers escalation counter being cleared by class_clr_shadowed register.''' + } + { + name: alert_cause_cg + desc: '''Covers alert_cause register and related items. + + - Collect which alert causes the alert_cause register to set. + - Collect the alert_class that this alert belongs to. + - Cross the above coverpoints. + ''' + } + { + name: alert_loc_alert_cause_cg + desc: '''Covers loc_alert_cause register regarding alert. + + - Collect two loc_alert causes: alert_ping_fail and alert_integrity_fail. + - Collect which alert triggers this loc_alert. + - Collect the alert_class that this local alert belongs to. + - Cross the first coverpoint with the rest of the coverpoints. + ''' + } + { + name: esc_loc_alert_cause_cg + desc: '''Covers loc_alert_cause register regarding escalation. + + - Collect two loc_alert causes: esc_ping_fail and esc_integrity_fail. + - Collect which escalation triggers this loc_alert. + - Collect the alert_class that this local alert belongs to. + - Cross the first coverpoint with the rest of the coverpoints. + ''' + } + { + name: crashdump_trigger_cg + desc: '''Covers which phase triggers crashdump.''' + } + { + name: alert_en_regwen_cg + desc: '''Covers if regwen is locked for alert_en registers.''' + } + { + name: alert_class_regwen_cg + desc: '''Covers if regwen is locked for alert_class registers.''' + } + { + name: loc_alert_en_regwen_cg + desc: '''Covers if regwen is locked for loc_alert_en registers.''' + } + { + name: loc_alert_class_regwen_cg + desc: '''Covers if regwen is locked for loc_alert_class registers.''' + } + { + name: class_ctrl_regwen_cg + desc: '''Covers if regwen is locked for class_ctrl registers.''' + } + { + name: class_clr_regwen_cg + desc: '''Covers if regwen is locked for class_clr registers.''' + } + { + name: class_accum_thresh_regwen_cg + desc: '''Covers if regwen is locked for class_accum_thresh registers.''' + } + { + name: class_timeout_cyc_regwen_cg + desc: '''Covers if regwen is locked for class_timeout_cyc registers.''' + } + { + name: class_crashdump_trigger_regwen_cg + desc: '''Covers if regwen is locked for class_crashdump_trigger registers.''' + } + { + name: class_phase_cyc_regwen_cg + desc: '''Covers if regwen is locked for class_phase_cyc registers.''' + } + { + name: num_edn_reqs_cg + desc: '''Covers if simulation runs long enough to capture more than five EDN requests.''' + } + { + name: num_checked_pings_cg + desc: '''Covers if simulation runs long enough to capture more than twenty ping requests.''' + } + { + name: cycles_bwtween_pings_cg + desc: '''Covers how many cycles are there between two ping requests.''' + } + { + name: alert_ping_with_lpg_wrap_cg + desc: '''Covers ping requests are initiated with LPG enabled or disabled.''' + } + + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/top_darjeeling_no_ibex_alert_handler.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/top_darjeeling_no_ibex_alert_handler.ipconfig.hjson new file mode 100644 index 00000000000..81978b0e056 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data/top_darjeeling_no_ibex_alert_handler.ipconfig.hjson @@ -0,0 +1,224 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_alert_handler + param_values: + { + module_instance_name: alert_handler + n_alerts: 99 + esc_cnt_dw: 32 + accu_cnt_dw: 16 + async_on: + [ + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + 1'b1 + ] + n_classes: 4 + n_esc_sev: 4 + ping_cnt_dw: 16 + n_lpg: 16 + lpg_map: + [ + 5'd0 + 5'd0 + 5'd1 + 5'd2 + 5'd3 + 5'd3 + 5'd3 + 5'd3 + 5'd3 + 5'd3 + 5'd3 + 5'd3 + 5'd4 + 5'd5 + 5'd6 + 5'd6 + 5'd6 + 5'd6 + 5'd6 + 5'd7 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd10 + 5'd11 + 5'd12 + 5'd12 + 5'd13 + 5'd14 + 5'd14 + 5'd15 + 5'd15 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd11 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd9 + 5'd3 + 5'd3 + 5'd9 + 5'd9 + 5'd11 + 5'd11 + ] + topname: darjeeling_no_ibex + uniquified_modules: {} + racl_support: false + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/defs.bzl new file mode 100644 index 00000000000..3d964928865 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/defs.bzl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +ALERT_HANDLER = opentitan_ip( + name = "alert_handler", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/data:alert_handler.hjson", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_alert_rxtx.svg b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_alert_rxtx.svg new file mode 100644 index 00000000000..d851d503f36 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_alert_rxtx.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_block_diagram.svg b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_block_diagram.svg new file mode 100644 index 00000000000..1976ea10fb9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_block_diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_escalation_rxtx.svg b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_escalation_rxtx.svg new file mode 100644 index 00000000000..9012f2c0d29 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_escalation_rxtx.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_lp_overview.svg b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_lp_overview.svg new file mode 100644 index 00000000000..0278ad8baa1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_lp_overview.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_lpg_ctrl.svg b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_lpg_ctrl.svg new file mode 100644 index 00000000000..d524dacae93 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_lpg_ctrl.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_receiver_fsm.svg b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_receiver_fsm.svg new file mode 100644 index 00000000000..840987ade9a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/alert_handler_receiver_fsm.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/checklist.md b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/checklist.md new file mode 100644 index 00000000000..d398772f977 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/checklist.md @@ -0,0 +1,266 @@ +# Alert Handler Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [Alert Handler peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|----------------------- |-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [Alert Handler spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Done | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | Done | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | adk@ vogelpi@ +Review | Signoff date | Done | 2024-08-08 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | +Documentation | [TESTPLAN_COMPLETED][] | Done | +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | N/A | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done | prim_alert_receiver and prim_esc_sender. +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | N/A | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | N/A | +Tests | [SIM_FW_SIMULATED][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | N/A | +Coverage | [FPV_COI_COVERAGE_V2][] | N/A | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Done | prim_alert_receiver and prim_esc_sender. +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]: ../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_PROVEN][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_proven +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/programmers_guide.md b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/programmers_guide.md new file mode 100644 index 00000000000..7f6f368b40e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/programmers_guide.md @@ -0,0 +1,122 @@ +# Programmer's Guide + + +## Power-up and Reset Considerations + +False alerts during power-up and reset are not possible since the alerts are disabled by default, and need to be configured and locked in by the firmware. +The ping timer won't start until initial configuration is over and the registers are locked in. + +The low-power state management of alert channels is handled entirely by hardware and hence this is transparent to software. +Note however that the LPGs inherit the security properties of the associated clock groups and resets. +This means that the low-power state of certain alerts can be controlled by SW by means of clock gating or block reset. +For example, certain crypto blocks are located in a transactional clock group which can be clock gated by SW - and this also affects the associated alerts of these crypto blocks. +See [clock](../../clkmgr/README.md) and [reset managers](../../rstmgr/README.md) for more detail. + + +## Initialization + +To initialize the block, software running at a high privilege levels (early in the security settings process) should do the following: + +1. For each alert and each local alert: + + - Determine if alert is enabled (should only be false if alert is known to be faulty). + Set [`ALERT_EN_SHADOWED_0.EN_A_0`](../data/alert_handler.hjson#alert_en_shadowed_0) and [`LOC_ALERT_EN_SHADOWED_0.EN_LA_0`](../data/alert_handler.hjson#loc_alert_en_shadowed_0) accordingly. + + - Determine which class (A..D) the alert is associated with. + Set [`ALERT_CLASS_SHADOWED_0.CLASS_A_0`](../data/alert_handler.hjson#alert_class_shadowed_0) and [`LOC_ALERT_CLASS_SHADOWED_0.CLASS_LA_0`](../data/alert_handler.hjson#loc_alert_class_shadowed_0) accordingly. + + - Optionally lock each alert configuration by writing 0 to [`ALERT_REGWEN_0.EN_0`](../data/alert_handler.hjson#alert_regwen_0) or [`LOC_ALERT_REGWEN_0.EN_0`](../data/alert_handler.hjson#loc_alert_regwen_0). + Note however that only **locked and enabled** alerts are going to be pinged using the ping mechanism. + This ensures that spurious ping failures cannot occur when previously enabled alerts are being disabled again (before locking). + + +2. Set the ping timeout value [`PING_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#ping_timeout_cyc_shadowed). + This value is dependent on the clock ratios present in the system. + +3. For each class (A..D): + + - Determine whether to enable escalation mechanisms (accumulation / interrupt timeout) for this particular class. Set [`CLASSA_CTRL_SHADOWED.EN`](../data/alert_handler.hjson#classa_ctrl_shadowed) accordingly. + + - Determine if this class of alerts allows clearing of escalation once it has begun. + Set [`CLASSA_CTRL_SHADOWED.LOCK`](../data/alert_handler.hjson#classa_ctrl_shadowed) to true if clearing should be disabled. + If true, once escalation protocol begins, it can not be stopped, the assumption being that it ends in a chip reset else it will be rendered useless thenceforth. + + - Determine the number of alerts required to be accumulated before escalation protocol kicks in. Set [`CLASSA_ACCUM_THRESH`](../data/alert_handler.hjson#classa_accum_thresh) accordingly. + + - Determine whether the interrupt associated with that class needs a timeout. + If yes, set [`CLASSA_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#classa_timeout_cyc_shadowed) to an appropriate value greater than zero (zero corresponds to an infinite timeout and disables the mechanism). + + - For each escalation phase (0..3): + - Determine length of each escalation phase by setting [`CLASSA_PHASE0_CYC`](../data/alert_handler.hjson#classa_phase0_cyc) accordingly + + - For each escalation signal (0..3): + - Determine whether to enable the escalation signal, and set the [`CLASSA_CTRL_SHADOWED.E0_EN`](../data/alert_handler.hjson#classa_ctrl_shadowed) bit accordingly (default is enabled). + Note that setting all of the `E*_EN` bits to 0 within a class has the same effect of disabling the entire class by setting [`CLASSA_CTRL_SHADOWED.EN`](../data/alert_handler.hjson#classa_ctrl_shadowed) to zero. + - Determine the phase -> escalation mapping of this class and program it via the [`CLASSA_CTRL_SHADOWED.E0_MAP`](../data/alert_handler.hjson#classa_ctrl_shadowed) values if it needs to be changed from the default mapping (0->0, 1->1, 2->2, 3->3). + + - Optionally lock the class configuration by writing 0 to [`CLASSA_CTRL_SHADOWED.REGWEN`](../data/alert_handler.hjson#classa_ctrl_shadowed). + +4. After initial configuration at startup, enable the ping timer mechanism by writing 1 to [`PING_TIMER_EN`](../data/alert_handler.hjson#ping_timer_en). +It is also recommended to lock the ping timer configuration by clearing [`PING_TIMER_REGWEN`](../data/alert_handler.hjson#ping_timer_regwen). +Note that only **locked and enabled** alerts are going to be pinged using the ping mechanism. +This ensures that spurious ping failures cannot occur when previously enabled alerts are being disabled again (before locking). + +## Interrupt Handling + +For every alert that is enabled, an interrupt will be triggered on class A, B, C, or D. +To handle an interrupt of a particular class, software should execute the following steps: + +1. If needed, check the escalation state of this class by reading [`CLASSA_STATE`](../data/alert_handler.hjson#classa_state). + This reveals whether escalation protocol has been triggered and in which escalation phase the class is. + In case interrupt timeouts are enabled the class will be in timeout state unless escalation has already been triggered. + The current interrupt or escalation cycle counter can be read via [`CLASSA_ESC_CNT`](../data/alert_handler.hjson#classa_esc_cnt). + +2. Since the interrupt does not indicate which alert triggered, SW must read the cause registers [`LOC_ALERT_CAUSE`](../data/alert_handler.hjson#loc_alert_cause) and [`ALERT_CAUSE`](../data/alert_handler.hjson#alert_cause) etc. + The cause bits of all alerts are concatenated and chunked into 32bit words. + Hence the register file contains as many cause words as needed to cover all alerts present in the system. + Each cause register contains a sticky bit that is set by the incoming alert, and is clearable with a write by software. + This should only be cleared after software has cleared the event trigger, if applicable. + It is possible that the event requires no clearing (e.g. a parity error), or can't be cleared (a breach in the metal mesh protecting the chip). + + Note that in the rare case when multiple events are triggered at or about the same time, all events should be cleared before proceeding. + +3. After the event is cleared (if needed or possible), software should handle the interrupt as follows: + + - Resetting the accumulation register for the class by writing [`CLASSA_CLR`](../data/alert_handler.hjson#classa_clr). + This also aborts the escalation protocol if it has been triggered. + If for some reason it is desired to never allow the accumulator or escalation to be cleared, software can initialize the [`CLASSA_CLR_REGWEN`](../data/alert_handler.hjson#classa_clr_regwen) register to zero. + If [`CLASSA_CLR_REGWEN`](../data/alert_handler.hjson#classa_clr_regwen) is already false when an alert interrupt is detected (either due to software control or hardware trigger via [`CLASSA_CTRL_SHADOWED.LOCK`](../data/alert_handler.hjson#classa_ctrl_shadowed)), then the accumulation counter can not be cleared and this step has no effect. + + - After the accumulation counter is reset (if applicable), software should clear the class A interrupt state bit [`INTR_STATE.CLASSA`](../data/alert_handler.hjson#intr_state). + Clearing the class A interrupt state bit also clears and stops the interrupt timeout counter (if enabled). + +Note that testing interrupts by writing to the interrupt test registers does also trigger the internal interrupt timeout (if enabled), since the interrupt state is used as enable signal for the timer. +However, alert accumulation will not be triggered by this testing mechanism. + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_alert_handler.h) + +## Register Table + +* [Register Table](../data/alert_handler.hjson#registers) + + +# Additional Notes + +## Timing Constraints + +The skew within all differential signal pairs must be constrained to be smaller than the period of the fastest clock operating the alert handler receivers. +The maximum propagation delay of differential pair should also be constrained (although it may be longer than the clock periods involved). + + +## Fast-track Alerts + +Note that it is possible to program a certain class to provide a fast-track response for critical alerts by setting its accumulation trigger value to 1, and configuring the escalation protocol such that the appropriate escalation measure is triggered within escalation phase 0. +This results in a minimal escalation latency of 4 clock cycles from alert sender input to escalation receiver output in the case where all involved signaling modules are completely synchronous with the alert handler. +In case the alert sender is asynchronous w.r.t. to the alert handler, the actual latency depends on the clock periods involved. +Assuming both clocks have the same frequency alert propagation takes at least 6-8 clock alert handler clock cycles. + +For alerts that mandate an asynchronous response (i.e. without requiring a clock to be active), it is highly recommended to build a separate network at the top-level. +That network should OR' the critical sources together and route the asynchronous alert signal directly to the highest severity countermeasure device. +Examples for alert conditions of this sort would be attacks on the secure clock. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/theory_of_operation.md b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/theory_of_operation.md new file mode 100644 index 00000000000..07e68dbf49a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/doc/theory_of_operation.md @@ -0,0 +1,785 @@ +# Theory of Operation + +## Block Diagram + +The figure below shows a block diagram of the alert handler module, as well as a few examples of alert senders in other peripheral modules. +In this diagram, there are seven sources of alerts: three sources from external modules (two from `periph0` and one from `periph1`), and four local sources (`alert_ping_fail`, `alert_sig_int`, `esc_ping_fail`, `esc_sig_int`). +The local sources represent alerts that are created by this module itself. See the later section on special local alerts. + +![Alert Handler Block Diagram](alert_handler_block_diagram.svg) + +Also shown are internal modules for classification, interrupt generation, accumulation, escalation, ping generation and alert-channel low-power control. +These are described later in the document. +Note that the differential alert sender and receiver blocks used for alert signaling support both _asynchronous_ and _synchronous_ clocking schemes, and hence peripherals able to raise alerts may be placed in clock domains different from that of the alert handler (Jittered clock domains are also supported in the asynchronous clocking scheme). +Proper care must however be taken when formulating the timing constraints for the diff pairs, and when determining clock-dependent parameters (such as the ping timeout) of the design. +On the escalation sender / receiver side, the differential signaling blocks employ a fully synchronous clocking scheme throughout. + +## Hardware Interfaces + +### Parameters + +The following table lists the main parameters used throughout the alert handler design. +Note that the alert handler is generated based on the system configuration, and hence these parameters are placed into a package as "localparams". +The parameterization rules are explained in more detail in the architectural description. + +Localparam | Default (Max) | This Core | Description +---------------|-----------------------|----------------|--------------- +`NAlerts` | 8 (248) | 99 | Number of alert instances. Maximum number bounded by LFSR implementation that generates ping timing. +`NLpg` | 1 | 16 | Number of unique low-power groups as determined by topgen. +`LpgMap` | {0} | see RTL | Array mapping each alert to a unique low-power group as determined by topgen. +`EscCntWidth` | 32 (32) | 32 | Width of the escalation counters in bit. +`AccuCntWidth` | 16 (32) | 16 | Width of the alert accumulation counters in bit. +`AsyncOn` | '0 (2^`NAlerts`-1) | see RTL | This is a bit array specifying whether a certain alert sender / receiver pair goes across an asynchronous boundary or not. + +The next table lists free parameters in the `prim_alert_sender` and +`prim_alert receiver` submodules. + +Parameter | Default (Max) | Description +---------------|------------------|--------------- +`AsyncOn` | `1'b0` (`1'b1`) | 0: Synchronous, 1: Asynchronous, determines whether additional synchronizer flops and logic need to be instantiated. + + +### Signals + +* [Interface Tables](../data/alert_handler.hjson#interfaces) + +The table below lists other alert handler module signals. +The number of alert instances is parametric and hence alert and ping diff pairs are grouped together in packed arrays. +The diff pair signals are indexed with the corresponding alert instance ``. + +Signal | Direction | Type | Description +-------------------------|------------------|---------------- |--------------- +`edn_o` | `output` | `otp_edn_req_t` | Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation. +`edn_i` | `input` | `otp_edn_rsp_t` | Entropy acknowledgment to the entropy distribution network for LFSR reseeding and ephemeral key derivation. +`alert_tx_i[]` | `input` | packed `alert_tx_t` array | Incoming alert or ping response(s), differentially encoded. Index range: `[NAlerts-1:0]` +`alert_rx_o[]` | `output` | packed `alert_rx_t` array | Outgoing alert acknowledgment and ping requests, differentially encoded. Index range: `[NAlerts-1:0]` +`esc_tx_o[]` | `output` | packed `esc_tx_t` array | Escalation or ping request, differentially encoded. Index corresponds to severity level, and ranges from 0 to 3. +`esc_rx_i[]` | `input` | packed `esc_rx_t` array | Escalation ping response, differentially encoded. Index corresponds to severity level, and ranges from 0 to 3. +`lpg_cg_en_i[]` | `input` | packed `mubi4_t` array | Incoming clock gated indication from clock manager. Index range: `[NLpg-1:0]` +`lpg_rst_en_i[]` | `input` | packed `mubi4_t` array | Incoming reset asserted indication from reset manager. Index range: `[NLpg-1:0]` +`crashdump_o` | `output` | packed `struct` | This is a collection of alert handler state registers that can be latched by hardware debugging circuitry, if needed. + +#### Entropy Network Connections + +The LFSR ping timer needs to be periodically reseeded. +Therefore, the alert handler is connected to the entropy distribution network via the `edn_i/o` signals. + +#### Alert Channels + +For each alert, there is a pair of input and two pairs of output signals. +These signals are connected to a differential sender module within the source, and a differential receiver module within the alert handler. +Both of these modules are described in more detail in the following section. +These signal pairs carry differentially encoded messages that enable two types of signaling: a native alert and a ping/response test of the alert mechanism. +The latter is to ensure that all alert senders are always active and have not been the target of an attack. + +#### Escalation Channels + +For each escalation action in the system, there is a pair of input and a pair of output signals, encapsulated in the `esc_rx_t` and `esc_tx_t` types. +These signals are connected to a differential sender module within the alert handler, and a differential receiver module within the module that performs a particular escalation action (for example the reset manager or life cycle controllers). +The signal pairs carry differentially encoded messages that enable two types of signaling: a native escalation and a ping/response test of the escalation mechanism. +The latter is to ensure that all escalation receivers are always active and have not been the target of an attack. + +#### Low-power Indication Signals + +The `lpg_cg_en_i` and `lpg_rst_en_i` are two arrays with multibit indication signals from the [clock](../../clkmgr/README.md) and [reset managers](../../rstmgr/README.md). +These indication signals convey whether a specific group of alert senders are either clock gated or in reset. +As explained in [more detail below](#low-power-management-of-alert-channels), this information is used to temporarily halt the ping timer mechanism on channels that are in a low-power state in order to prevent false positives. + +#### Crashdump Output + +The `crashdump_o` struct outputs a snapshot of CSRs and alert handler state bits that can be read by hardware debugging circuitry: + +```systemverilog + typedef struct packed { + // alerts + logic [NAlerts-1:0] alert_cause; // alert cause bits + logic [6:0] loc_alert_cause; // local alert cause bits + // class state + logic [3:0][15:0] class_accum_cnt; // current accumulator value + logic [3:0][31:0] class_esc_cnt; // current escalation counter value + cstate_e [3:0] class_esc_state; // current escalation protocol state + } alert_crashdump_t; +``` + +This can be useful for extracting more information about possible failures or bugs without having to use the tile-link bus interface (which may become unresponsive under certain circumstances). +It is recommended for the top level to store this information in an always-on location. + +Note that the crashdump state is continuously output via `crashdump_o` until the latching trigger condition is true for the first time (see [`CLASSA_CRASHDUMP_TRIGGER_SHADOWED`](../data/alert_handler.hjson#classa_crashdump_trigger_shadowed)). +After that, the `crashdump_o` is held constant until all classes that have escalated are cleared. +This is done so that it is possible to capture the true alert cause before spurious alert events start to pop up due to escalation countermeasures with excessive side effects (like life cycle scrapping for example). +If classes that have escalated are not configured as clearable, then it is not possible to re-arm the crashdump latching mechanism at runtime and the alert handler has to be reset. + +## Design Details + +This section gives the full design details of the alert handler module and its submodules. + + +### Alert Definition + +Alerts are defined as events that have security implications, and should be handled by the main processor, or escalated to other hardware modules to take action. +Each peripheral has the option to define one or more alert signals. +Those peripherals should instantiate one module (`prim_alert_sender`) to convert the event associated with that alert into a signal to the alert handler module. +The alert handler instantiates one receiver module (`prim_alert_receiver`) per alert, then handles the classification, accumulation, and escalation of the received signal. +The differential signaling submodules may either use a synchronous or asynchronous clocking scheme, since the message type to be transferred is a single discrete event. + + +### Differential Alert Signaling + +Each alert sender is connected to the corresponding alert receiver via the 3 differential pairs `alert_tx_i/o.alert_p/n`, `alert_rx_i/o.ack_p/n` and `alert_rx_i/o.ping_p/n`, as illustrated below: + +![Alert Handler Alert RXTX](alert_handler_alert_rxtx.svg) + +Alerts are encoded differentially and signaled using a full handshake on the `alert_tx_i/o.alert_p/n` and `alert_rx_i/o.ack_p/n` wires. +The use of a full handshake protocol allows this mechanism to be used with an asynchronous clocking strategy, where peripherals may reside in a different clock domain than the alert handler. +The full handshake guarantees that alert messages are correctly back-pressured and no alert is "lost" at the asynchronous boundary due to (possibly variable) clock ratios greater or less than 1.0. +The "native alert message" will be repeated on the output wires as long as the alert event is still true within the peripheral. + +The wave pattern below illustrates differential full handshake mechanism. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...............' }, + { name: 'alert_req_i', wave: '01.|..|..|...|..' }, + { name: 'alert_ack_o', wave: '0..|..|..|10.|..' }, + { name: 'alert_tx_o/i.alert_p', wave: '01.|..|0.|..1|..' , node: '.a.....c....e'}, + { name: 'alert_tx_o/i.alert_n', wave: '10.|..|1.|..0|..' }, + { name: 'alert_rx_i/o.ack_p', wave: '0..|1.|..|0..|1.' , node: '....b.....d..'}, + { name: 'alert_rx_i/o.ack_n', wave: '1..|0.|..|1..|0.' }, + { name: 'alert_o', wave: '0..|10|..|...|10' }, + ], + edge: [ + 'a~>b Phase 0/1', + 'b~>c Phase 1/2', + 'c~>d Phase 2/3', + 'd~>e 2 Pause Cycles', + ], + head: { + text: 'Alert signaling and repeat pattern', + }, + foot: { + text: 'Native alert at time 1 with 4-phase handshake; repeated alert at time 12;', + tick: 0, + } +} +``` + +The handshake pattern is repeated as long as the alert is true. +The sender will wait for 2 cycles between handshakes. + +Note that the alert is immediately propagated to `alert_o` once the initial level change on `alert_tx_i.alert_p/n` has been received and synchronized to the local clock on the receiver side. +This ensures that the first occurrence of an alert is always propagated - even if the handshake lines have been manipulated to emulate backpressure. +(In such a scenario, all subsequent alerts would be back-pressured and eventually the ping testing mechanism described in the next subsection would detect that the wires have been tampered with.) + +The alert sender and receiver modules can either be used synchronously or asynchronously. +The signaling protocol remains the same in both cases, but the additional synchronizer flops at the diff pair inputs may be omitted, which results in lower signaling latency. + +### Ping Testing + +In order to ensure that the event sending modules have not been compromised, the alert receiver module `prim_alert_receiver` will "ping" or line-test the senders periodically every few microseconds. +Pings timing is randomized so their appearance can not be predicted. + + +The ping timing is generated by a central LFSR-based timer within the alert handler that randomly asserts the `ping_req_i` signal of a particular `prim_alert_receiver` module. +Once `ping_req_i` is asserted, the receiver module encodes the ping message as a level change on the differential `alert_rx_o.ping_p/n` output, and waits until the sender responds with a full handshake on the `alert_tx_i.alert_p/n` and `alert_rx_o.ack_p/n` lines. +Once that handshake is complete, the `ping_ok_o` signal is asserted. +The LFSR timer has a programmable ping timeout, after which it will automatically assert a "pingfail" alert. +That timeout is a function of the clock ratios present in the system, and has to be programmed accordingly at system startup (as explained later in the LFSR timer subsection). + +The following wave diagram illustrates a correct ping sequence, viewed from the receiver side: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p..............' }, + { name: 'ping_req_i', wave: '01.|..|..|..|.0' }, + { name: 'ping_ok_o', wave: '0..|..|..|..|10' , node: '.............e'}, + { name: 'alert_rx_o.ping_p', wave: '01.|..|..|..|..' , node: '.a'}, + { name: 'alert_rx_o.ping_n', wave: '10.|..|..|..|..' , node: '.b'}, + { name: 'alert_tx_i.alert_p', wave: '0..|1.|..|0.|..' , node: '....c'}, + { name: 'alert_tx_i.alert_n', wave: '1..|0.|..|1.|..' }, + { name: 'alert_rx_o.ack_p', wave: '0..|..|1.|..|0.' , node: '.............d'}, + { name: 'alert_rx_o.ack_n', wave: '1..|..|0.|..|1.' }, + ], + edge: [ + 'a-b', + 'b~>c ping response', + 'd->e response complete', + ], + head: { + text: 'Ping testing', + }, + foot: { + text: 'Level change at time 1 triggers a full handshake (ping response) at time 4', + tick: 0, + } +} +``` + +In the unlikely case that a ping request collides with a native alert at the sender side, the native alert is held back until the ping handshake has been completed. +This slightly delays the transmission of a native alert, but the alert will eventually be signaled. +Further, if an alert is sent out right before a ping requests comes in at the sender side, the receiver will treat the alert as a ping response. +However, the "true" ping response will be returned right after the alert handshake completed, and thus the alert will eventually be signaled with a slight delay. + +Note that in both collision cases mentioned, the delay will be in the order of the handshake length, plus the constant amount of pause cycles between handshakes (2 sender cycles). + + +### Monitoring of Signal Integrity Issues + +All differential pairs are monitored for signal integrity issues, and if an encoding failure is detected, the receiver module asserts a signal integrity alert via `integ_fail_o`. In particular, this covers the following failure cases: + +1. The `alert_tx_i.alert_p/n` pair is not correctly encoded on the receiver side. +This can be directly flagged as an integrity failure on the receiver side. + +2. The `alert_rx_i.ping_p/n` or the `alert_rx_i.ack_p/n` pairs are not correctly encoded on the sender side. +This is signaled to the receiver by setting the `alert_tx_o.alert_p/n` wires to the same value, and that value will be continuously toggled. +This implicitly triggers a signal integrity alert on the receiver side. + +Some of these failure patterns are illustrated in the wave diagram below: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p..............' }, + { name: 'alert_tx_o.alert_p', wave: '0.1...|0..10101' , node: '..a.......d'}, + { name: 'alert_tx_o.alert_n', wave: '1.....|....0101' }, + { name: 'alert_rx_i.ack_p', wave: '0.....|.1......' , node: '........c'}, + { name: 'alert_rx_i.ack_n', wave: '1.....|........' }, + { name: 'integ_fail_o', wave: '0...1.|0....1..' , node: '....b.......e'}, + ], + edge: [ + 'a~>b sigint issue detected', + 'c~>d', + 'd~>e indirect sigint issue detected', + ], + head: { + text: 'Detection of Signal Integrity Issues', + }, + foot: { + text: 'signal integrity issues occur at times 2 and 8; synchronizer latency is 2 cycles.', + tick: 0, + } +} +``` + +Note that if signal integrity failures occur during ping or alert handshaking, it is possible that the protocol state-machines lock up and the alert sender and receiver modules become unresponsive. However, the above mechanisms ensure that this will always trigger either a signal integrity alert or eventually a "pingfail" alert. + +### Skew on Asynchronous Differential Pairs + +Note that there is likely a (small) skew present within each differential pair of the signaling mechanism above. Since these pairs cross clock domain boundaries, it may thus happen that a level change appears in staggered manner after resynchronization, as illustrated below: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...........' }, + { name: 'diff_p', wave: '0.1.|.0.|..1' , node: '......a....d' }, + { name: 'diff_n', wave: '1.0.|..1|.0.' , node: '.......b..c.' }, + ], + edge: [ + 'a-~>b skew', + 'c-~>d skew' + ], + head: { + text: 'Skewed diff pair', + }, + foot: { + text: 'Correctly sampled diff pair at time 2; staggered samples at time 6-7 and 10-11', + tick: 0, + } +} +``` + +This behavior is permissible, but needs to be accounted for in the protocol logic. +Further, the skew within the differential pair should be constrained to be smaller than the shortest clock period in the system. +This ensures that the staggered level changes appear at most 1 cycle apart from each other. + + +### LFSR Timer + +The `ping_req_i` inputs of all signaling modules (`prim_alert_receiver`, `prim_esc_sender`) instantiated within the alert handler are connected to a central ping timer that alternatingly pings either an alert line or an escalation line after waiting for a pseudo-random amount of clock cycles. +Further, this ping timer also randomly selects a particular alert line to be pinged (escalation senders are always pinged in-order due to the [ping monitoring mechanism](#monitoring-of-pings-at-the-escalation-receiver-side) on the escalation side). +That should make it more difficult to predict the next ping occurrence based on past observations. + +The ping timer is implemented using an [LFSR-based PRNG of Galois type](../../../../ip/prim/doc/prim_lfsr.md). +This ping timer is reseeded with fresh entropy from EDN roughly every 500k cycles which corresponds to around 16 ping operations on average. +The LFSR is 32bits wide, but only 24bits of its state are actually being used to generate the random timer count and select the alert line to be pinged. +I.e., the 32bits first go through a fixed permutation function, and then bits `[23:16]` are used to determine which alert line to ping. +The random cycle count is created by OR'ing bits `[15:0]` with the constant `3'b100` as follows: + +``` +cycle_cnt = permuted[15:0] | 3'b100; +``` + +This constant DC offset introduces a minimum ping spacing of 4 cycles (1 cycle + margin) to ensure that the handshake protocols of the sender/receiver pairs work. + +After selecting one of the peripherals to ping, the LFSR timer waits until either the corresponding `*_ping_ok[]` signal is asserted, or until the programmable ping timeout value is reached. +In both cases, the LFSR timer proceeds with the next ping, but in the second case it will additionally raise a "pingfail" alert. +The ping enable signal remains asserted during the time where the LFSR counter waits. + +The timeout value is a function of the ratios between the alert handler clock and peripheral clocks present in the system, and can be programmed at startup time via the register [`PING_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#ping_timeout_cyc_shadowed). + +Note that the ping timer directly flags a "pingfail" alert if a spurious "ping ok" message comes in that has not been requested. + + +As described in the programmers guide below, the ping timer has to be enabled explicitly. +Only alerts that have been *enabled and locked* will be pinged in order to avoid spurious alerts. +Escalation channels are always enabled, and hence will always be pinged once this mechanism has been turned on. + +In addition to the ping timer mechanism described above, the escalation receivers contain monitoring counters that monitor the liveness of the alert handler (described in more detail in [this section](#monitoring-of-pings-at-the-escalation-receiver-side). +This mechanism requires that the maximum wait time between escalation receiver pings is bounded. +To that end, escalation senders are pinged in-order every second ping operation (i.e., the wait time is randomized, but the selection of the escalation line is not). + +### Alert Receiving + +The alert handler module contains one alert receiver module (`prim_alert_receiver`) per sending module. +This receiver module has three outputs based upon the signaling of the input alert. +Primary is the signal of a received native alert, shown in the top-level diagram as `alert_triggered[]`. +Also generated are two other outputs, one that signals a differential encoding error (`alert_integ_fail[]`), and one that signals the receipt of a ping response (`alert_ping_ok[]`). +Each "triggered" alert received is sent into the classification block for individual configuration. +All of the `integ_fail` signals are OR'ed together to create one alert for classification. +The ping responses are fed to the LFSR timer, which determines whether a ping has correctly completed within the timeout window or not. + + +### Alert Classification and Interrupts + +Each of the incoming and local alert signals can be classified generically to one of four classes, or disabled for no classification at all. +These are the classes A, B, C, and D. +There is no pre-determined definition of a class, that is left to software. +But for guidance, software can consider that some alert types are similar to others; some alert types are more "noisy" than others (i.e. when triggered they stay on for long periods of time); some are more critical than others, etc. + +For each alert class (A-D), an interrupt is generally sent. +Like all other peripheral interrupts, there is a triad of registers: enable, status, test. +Thus like all other interrupts, software should handle the source of the interrupt (in this case, the original alert), then clear the state. +Since the interrupt class is disassociated with the original alert (due to the classification process), software can access cause registers to determine which alerts have fired since the last clearing. +Since alerts are expected to be rare (if ever) events, the complexity of dealing with multiple interrupts per class firing during the same time period should not be of concern. See the programming section on interrupt clearing. + +Each of the four interrupts can optionally trigger a timeout counter that triggers escalation if the interrupt is not handled and cleared within a certain time frame. +This feature is explained in more detail in the next subsection about escalation mechanisms. + +Note that an interrupt always fires once an alert has been registered in the corresponding class. +Interrupts are not dependent on escalation mechanisms like alert accumulation or timeout as described in the next subsection. + + +### Escalation Mechanisms + +There are two mechanisms per class that can trigger the corresponding escalation +protocol: + +1. The first consists of an accumulation counter that counts the amount of alert occurrences within a particular class. + An alert classified to class A indicates that on every received alert trigger, the accumulation counter for class A is incremented. + Note: since alerts are expected to be rare or never occur, the module does not attempt to count every alert per cycle, but rather all triggers per class are ORd before sending to the accumulation counter as an increment signal. + Once the threshold has been reached, the next occurrence triggers the escalation escalation protocol for this particular class. + The counter is a saturation counter, meaning that it will not wrap around once it hits the maximum representable count. + This mechanism has two associated CSRs: + + - Accumulation max value. + This is the total number (sum of all alerts classified in this group) of alerts required to enter escalation phase (see below). + Example register is [`CLASSA_ACCUM_THRESH_SHADOWED`](../data/alert_handler.hjson#classa_accum_thresh_shadowed). + - Current accumulation register. + This clearable register indicates how many alerts have been accumulated to date. + Software should clear before it reaches the accumulation setting to avoid escalation. + Example register is [`CLASSA_ACCUM_CNT`](../data/alert_handler.hjson#classa_accum_cnt). + +2. The second way is an interrupt timeout counter which triggers escalation if an alert interrupt is not handled within the programmable timeout window. + Once the counter hits the timeout threshold, the escalation protocol is triggered. + The corresponding CSRs are: + + - Interrupt timeout value in cycles [`CLASSA_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#classa_timeout_cyc_shadowed). + The interrupt timeout is disabled if this is set to 0 (default). + - The current interrupt timeout value can be read via [`CLASSA_ESC_CNT`](../data/alert_handler.hjson#classa_esc_cnt) if [`CLASSA_STATE`](../data/alert_handler.hjson#classa_state) is in the `Timeout` state. + Software should clear the corresponding interrupt state bit [`INTR_STATE.CLASSA`](../data/alert_handler.hjson#intr_state) before the timeout expires to avoid escalation. + +Technically, the interrupt timeout feature (2. above) is implemented using the same counter used to time the escalation phases. +This is possible since escalation phases or interrupt timeout periods are non-overlapping (escalation always takes precedence should it be triggered). + + +### Programmable Escalation Protocol + +There are four output escalation signals, 0, 1, 2, and 3. +There is no predetermined definition of an escalation signal, that is left to the top-level integration. +Examples could be processor Non Maskable Interrupt (NMI), privilege lowering, secret wiping, chip reset, etc. +Typically the assumption is that escalation level 0 is the first to trigger, followed by 1, 2, and then 3, emulating a "fuse" that is lit that can't be stopped once the first triggers (this is however not a requirement). +See register section for discussion of counter clearing and register locking to determine the finality of accumulation +triggers. + +Each class can be programmed with its own escalation protocol. +If one of the two mechanisms described above fires, a timer for that particular class is started. +The timer can be programmed with up to 4 delays (e.g., [`CLASSA_PHASE0_CYC`](../data/alert_handler.hjson#classa_phase0_cyc)), each representing a distinct escalation phase (0 - 3). +Each of the four escalation severity outputs (0 - 3) are by default configured to be asserted during the corresponding phase, e.g., severity 0 in phase 0, severity 1 in phase 1, etc. +However, this mapping can be freely reassigned by modifying the corresponding enable/phase mappings (e.g., [`CLASSA_CTRL_SHADOWED.E0_MAP`](../data/alert_handler.hjson#classa_ctrl_shadowed) for enable bit 0 of class A). +This mapping will be locked in together with the alert enable configuration after initial configuration. + +SW can stop a triggered escalation protocol by clearing the corresponding escalation counter (e.g., [`CLASSA_ESC_CNT`](../data/alert_handler.hjson#classa_esc_cnt)). +Protection of this clearing is up to software, see the register control section that follows for [`CLASSA_CTRL_SHADOWED.LOCK`](../data/alert_handler.hjson#classa_ctrl_shadowed). + +It should be noted that each of the escalation phases have a duration of at least 1 clock cycle, even if the cycle count of a particular phase has been +set to 0. + +The next waveform shows the gathering of alerts of one class until eventually the escalation protocol is engaged. +In this diagram, two different alerts are shown for class A, and the gathering and escalation configuration values are shown. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...................' }, + { name: 'CLASSA_ACCUM_THRESH_SHADOWED', wave: '2...................', data: ['15'] }, + { name: 'CLASSA_PHASE0_CYC_SHADOWED', wave: '2...................', data: ['1e3 cycles'] }, + { name: 'CLASSA_PHASE1_CYC_SHADOWED', wave: '2...................', data: ['1e4 cycles'] }, + { name: 'CLASSA_PHASE2_CYC_SHADOWED', wave: '2...................', data: ['1e5 cycles'] }, + { name: 'CLASSA_PHASE3_CYC_SHADOWED', wave: '2...................', data: ['1e6 cycles'] }, + { name: 'alert_triggered[0]', wave: '010|.10.............' }, + { name: 'alert_triggered[1]', wave: '0..|10..............' }, + { name: 'CLASSA_ACCUM_CNT', wave: '33.|33..............', data: ['0', '1','15','16'] }, + { name: 'irq_o[0]', wave: '01.|................' }, + { name: 'CLASSA_STATE', wave: '3..|.3|3.|3..|3..|3.', data: ['Idle', ' Phase0','Phase1','Phase2','Phase3','Terminal'] }, + { name: 'CLASSA_ESC_CNT', wave: '3..|.3|33|333|333|3.', data: ['0','1','1','2','1','2','3','1','2','3','0'] }, + { name: 'esc_tx_o.esc_p[0]', wave: '0..|.1|.0...........', node: '.....a..b' }, + { name: 'esc_tx_o.esc_n[0]', wave: '1..|.0|.1...........' }, + { name: 'esc_tx_o.esc_p[1]', wave: '0..|..|1.|.0........', node: '.......c...d' }, + { name: 'esc_tx_o.esc_n[1]', wave: '1..|..|0.|.1........' }, + { name: 'esc_tx_o.esc_p[2]', wave: '0..|.....|1..|.0....', node: '..........e....f' }, + { name: 'esc_tx_o.esc_n[2]', wave: '1..|.....|0..|.1....' }, + { name: 'esc_tx_o.esc_p[3]', wave: '0..|.........|1..|.0', node: '..............g....h' }, + { name: 'esc_tx_o.esc_n[3]', wave: '1..|.........|0..|.1' }, + ], + edge: [ + 'a->b 1e3 + 1 cycles', + 'c->d 1e4 + 1 cycles', + 'e->f 1e5 + 1 cycles', + 'g->h 1e6 + 1 cycles', + ], + head: { + text: 'Alert class gathering and escalation triggers (fully synchronous case)', + }, + foot: { + text: 'alert class A gathers 16 alerts, triggers first escalation, followed by three more', + tick: 0, + } +} +``` + +In this diagram, the first alert triggers an interrupt to class A. +The assumption is that the processor is wedged or taken over, in which case it does not handle the interrupt. +Once enough interrupts gather (16 in this case), the first escalation phase is entered, followed by three more (each phase has its own programmable length). +Note that the accumulator threshold is set to 15 in order to trigger on the 16th occurrence. +If escalation shall be triggered on the first occurrence within an alert class, the accumulation threshold shall be set to 0. +Also note that it takes one cycle to activate escalation and enter phase 0. + +The next wave shows a case where an interrupt remains unhandled and hence the interrupt timeout counter triggers escalation. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p.....................' }, + { name: 'CLASSA_TIMEOUT_CYC_SHADOWED', wave: '2.....................', data: ['1e4 cycles'] }, + { name: 'alert_triggered[0]', wave: '010.|.................' }, + { name: 'irq_o[0]', wave: '01..|.................', node: '.a..|.b' }, + { name: 'CLASSA_ESC_STATE', wave: '33..|.3|3.|3..|3...|3.', data: ['Idle', 'Timeout',' Phase0','Phase1','Phase2','Phase3','Terminal'] }, + { name: 'CLASSA_ESC_CNT', wave: '3333|33|33|333|3333|3.', data: ['0', '1','2','3','1e4','1','1','2','1','2','3','1','2','3','4','0'] }, + { name: 'esc_tx_o.esc_p[0]', wave: '0...|.1|.0............' }, + { name: 'esc_tx_o.esc_n[0]', wave: '1...|.0|.1............' }, + { name: 'esc_tx_o.esc_p[1]', wave: '0...|..|1.|.0.........' }, + { name: 'esc_tx_o.esc_n[1]', wave: '1...|..|0.|.1.........' }, + { name: 'esc_tx_o.esc_p[2]', wave: '0...|.....|1..|.0.....' }, + { name: 'esc_tx_o.esc_n[2]', wave: '1...|.....|0..|.1.....' }, + { name: 'esc_tx_o.esc_p[3]', wave: '0...|.........|1...|.0' }, + { name: 'esc_tx_o.esc_n[3]', wave: '1...|.........|0...|.1' }, + ], + edge: [ + 'a->b 1e4 cycles', + ], + head: { + text: 'Escalation due to an interrupt timeout (fully synchronous case)', + }, + foot: { + text: 'alert class A triggers an interrupt and the timeout counter, which eventually triggers escalation after 1e4 cycles.', + tick: 0, + } +} +``` + +It should be noted here that the differential escalation signaling protocol distinguishes 'true' escalation conditions from mere pings by encoding them as pulses that are N + 1 cycles long. +This is reflected in the two wave diagrams above. +Refer to the subsequent section on escalation signaling for more details. + +### Escalation Signaling + +For each of the four escalation severities, the alert handler instantiates a `prim_esc_sender` module and each of the four escalation countermeasures instantiates an `prim_esc_receiver` module. +The signaling mechanism has similarities with the alert signaling mechanism - but it is a fully synchronous protocol. +Hence, it must be ensured at the top-level that all escalation sender and receiver modules are using the same clock and reset +signals. + +As illustrated in the following block diagram, a sender-receiver pair is connected with two differential lines, one going from sender to receiver and the other going from receiver to sender. + +![Alert Handler Escalation RXTX](alert_handler_escalation_rxtx.svg) + +Upon receiving an escalation enable pulse of width N > 0 at the `esc_req_i` input, the escalation sender encodes that signal as a differential pulse of width N+1 on `esc_tx.esc_p/n`. +The receiver decodes that message and asserts the `esc_req_o` output after one cycle of delay. +Further, it acknowledges the receipt of that message by continuously toggling the `esc_rx.resp_p/n` signals as long as the escalation signal is asserted. +Any failure to respond correctly will trigger a `integ_fail_o` alert, as illustrated below: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p..................' }, + { name: 'ping_req_i', wave: '0........|.........' }, + { name: 'ping_ok_o', wave: '0........|.........' }, + { name: 'integ_fail_o', wave: '0........|..1010...' , node: '............b.d' }, + { name: 'ping_fail_o', wave: '0........|.........' }, + { name: 'esc_req_i', wave: '01....0..|.1....0..' }, + { name: 'esc_rx_i/o.resp_p', wave: '0.101010.|.........', node: '............a.c' }, + { name: 'esc_rx_i/o.resp_n', wave: '1.010101.|.........' }, + { name: 'esc_tx_o/i.esc_p', wave: '01.....0.|.1.....0.' }, + { name: 'esc_tx_o/i.esc_n', wave: '10.....1.|.0.....1.' }, + { name: 'esc_req_o', wave: '0.1....0.|..?....0.'}, + ], + edge: [ + 'a~>b missing response', + 'c~>d', + ], + head: { + text: 'Escalation signaling and response', + }, + foot: { + text: 'escalation enable pulse shown at input sender at time 1 and 11; missing response and repeated integfail at time 12 and 14', + tick: 0, + } +} +``` + +Further, any differential signal mismatch on both the `esc_tx_i.esc_p/n` and `esc_rx_i.resp_p/n` lines will trigger an `integ_fail_o` alert. +Mismatches on `esc_rx_i.resp_p/n` can be directly detected at the sender. +Mismatches on the `esc_tx_i.esc_p/n` line will be signaled back to the sender by setting both the positive and negative response wires to the same value - and that value is being toggled each cycle. +This implicitly triggers a signal integrity alert on the sender side. +In addition to that, a signal integrity error on the `esc_tx_i.esc_p/n` lines will lead to assertion of the `esc_req_o` output, since it cannot be guaranteed that the back signalling mechanism always works when the sender / receiver pair is being tampered with. + +This back-signaling mechanism can be leveraged to fast-track escalation and use another countermeasure in case it is detected that a particular escalation signaling path has been tampered with. + +Some signal integrity failure cases are illustrated in the wave diagram below: + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p...........' }, + { name: 'ping_req_i', wave: '0....|......' }, + { name: 'ping_ok_o', wave: '0....|......' }, + { name: 'integ_fail_o', wave: '0.1.0|.1....' , node: '..b....e' }, + { name: 'esc_req_i', wave: '0....|......' }, + { name: 'esc_rx_i.resp_p', wave: '0.1.0|..1010', node: '..a..' }, + { name: 'esc_rx_i.resp_n', wave: '1....|.01010', node: '.......d' }, + { name: 'esc_tx_i.esc_p', wave: '0....|1.....', node: '......c..' }, + { name: 'esc_tx_i.esc_n', wave: '1....|......' }, + { name: 'esc_req_o', wave: '0....|1.....'}, + ], + edge: [ + 'a~>b', + 'c->d', + 'd->e', + ], + head: { + text: 'possible signal integrity failure cases', + }, + foot: { + text: 'direct signal integrity failure at time 2; indirect failure at time 6', + tick: 0, + } +} +``` + + +### Ping Testing of the Escalation Signals + + +Similarly to the alert signaling scheme, the escalation signaling lines can be pinged / line tested in order to test whether the escalation receiver has been tampered with. +This is achieved by asserting `ping_req_i` at the escalation sender module. +A ping request is encoded as a single cycle pulse on the `esc_tx_o.esc_p/n` outputs. +Hence, the receiver module will not decode this single cycle pulse as an escalation enable message, but it will respond to it with a "1010" pattern on the `esc_rx_i.resp_p/n` lines. +The escalation sender module will assert `ping_ok_o` if that pattern is received correctly after one cycle of latency. +Otherwise, the escalation sender will first assert `integ_fail_o` later, after the programmable ping timeout is reached, the LFSR timer will raise a "pingfail" alert. +The `integ_fail_o` triggers in this case since "no ping response" and "wrong ping response" are ambiguous in this setting, and it has been decided to not suppress integrity failures when expecting a ping response. + +This mechanism is illustrated below from the viewpoint of the sender module. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p..............' }, + { name: 'ping_req_i', wave: '01....0|.1.....' , node: '.a'}, + { name: 'ping_ok_o', wave: '0....10|.......' , node: '.....e....g'}, + { name: 'integ_fail_o', wave: '0......|..10101' }, + { name: 'esc_req_i', wave: '0......|.......' }, + { name: 'esc_rx_i.resp_p', wave: '0.1010.|.......' , node: '..c..d....f'}, + { name: 'esc_rx_i.resp_n', wave: '1.0101.|.......' }, + { name: 'esc_tx_o.esc_p', wave: '010....|.10....' , node: '.b'}, + { name: 'esc_tx_o.esc_n', wave: '101....|.01....' }, + ], + edge: [ + 'a->b', + 'b->c', + 'd->e correct response', + 'f->g missing response', + ], + head: { + text: 'ping testing of escalation lines', + }, + foot: { + text: 'ping trig at sender input at time 1 and 9; correct response at time 5; missing response at time 10', + tick: 0, + } +} +``` + +Note that the escalation signal always takes precedence, and the `ping_req_i` will just be acknowledged with `ping_ok_o` in case `esc_req_i` is already asserted. +An ongoing ping sequence will be aborted immediately. + +Another thing to note is that the ping and escalation response sequences have to start _exactly_ one cycle after either a ping or escalation event has been signaled. +Otherwise the escalation sender will assert `integ_fail_o` immediately. + +### Monitoring of Pings at the Escalation Receiver Side + +Escalation receivers contain a mechanism to monitor the liveness of the alert handler itself. +In particular, the receivers passively monitor the ping requests sent out by the alert handler using a timeout counter. +If ping requests are absent for too long, the corresponding escalation action will be automatically asserted until reset. + +The monitoring mechanism builds on top of the following properties of the alert handler system: +1. the ping mechanism can only be enabled, but not disabled. +This allows us to start the timeout counter once the first ping request arrives at a particular escalation receiver. + +2. the escalation receivers are in the same clock/reset domain as the alert handler. +This ensures that we are seeing the same clock frequency, and the mechanism is properly reset together with the alert handler logic. + +3. the maximum cycle count between subsequent pings on the same escalation line is bounded, even though the wait counts are randomized. +This allows us to compute a safe and fixed timeout threshold based on design constants. + + +### Low-power Management of Alert Channels + +Due to the various clock and reset domains in the OpenTitan system, the alert handler ping mechanism needs to have additional logic to deal with alert senders that are either held in reset, or that are clock gated. +This is needed to ensure that no false alarms are produced by the ping mechanism when an alert channel (sender / receiver pair) does not respond due to the sender being either in reset or clock gated. + +Since the FSMs associated with an alert channel may end up in an inconsistent state when the sender is reset or gated while an asynchronous event handshake is in progress, this logic also needs to be able to re-initialize affected alert channels whenever the channels comes back from reset / clock gated state. + +#### Assumptions + +The following diagram shows a typical arrangement of alert sender (TX) and receiver (RX) pairs. + +![Alert Handler Low-Power Overview](alert_handler_lp_overview.svg) + +It is assumed that: + +1. The alert handler clock domain cannot be gated by SW. + This means that this clock domain is only ever disabled as part of the power-down sequence of the corresponding power domain. +2. The alert senders are in general located within different clock and reset domains than the alert receivers within the alert handler, and thus use the asynchronous event handshake mode. +3. Some alert senders may be located in an always-on (AON) power domain, within different clock and reset groups than the alert handler. +4. The alert handler may be located in an non-AON power domain, and may thus undergo a reset cycle where it cannot be guaranteed that all alert senders are reset as well (i.e., some alert senders may retain their state). + +Further, we assume that we can get the following side-band information from the clock and reset managers in the system: + +- All relevant reset signals pertaining to alert sender domains +- All relevant clock enable signals pertaining to alert sender domains + +#### Scenarios + +With the assumptions above, the following two problematic scenarios can occur. + +##### Alert Handler in Reset + +It may happen that the alert handler is reset while some alert senders (e.g. those located in the AON domain) are not. +In general, if the associated alert channels are idle during an alert handler reset cycle, no problems arise. + +However, if an alert channel is reset while it is handling a ping request or an alert event, the sender / receiver FSMs may end up in an inconsistent state upon deassertion of the alert handler reset. +This can either lead to spurious alert or ping events, or a completely locked up alert channel which will be flagged eventually by the ping mechanism. + +##### Alert Sender in Reset or Clock-gated + +If any of the alert senders is either put into reset or its clock is disabled while the alert handler is operational, the ping mechanism inside the alert handler will eventually report a ping failure because of missing ping responses from the affected alert channel(s). + +Further, if the alert sender is reset while the corresponding alert channel is handling a ping request or an alert event, the sender / receiver FSMs may end up in an inconsistent state after reset deassertion. + +#### Employed Solution + +As elaborated before, the side effects of resetting / clock gating either the alert handler or any of the alert senders are inconsistent FSM states, leading to locked up alert channels, or spurious alert or ping events. +To address these issues, we have to: + +1. make sure spurious events (alert and ping_ok outputs of the alert receivers) are suppressed if an alert channel is clock gated or in reset, +2. provide a mechanism for resetting an alert channel to an operational state once the associated clock is re-enabled, or the associated reset is released, +3. trigger this reset mechanism on all alert channels whenever the alert handler itself has been reset. + +To attain this, the idea is to make use of side-band information available from the clock and reset managers to detect whether an alert channel (or a group of alert channels with the same clock and reset on the sender side) has to be put into a low-power state. +In the following we will refer to such a clock / reset domain grouping as a low-power group (LPG). + +The mechanism is illustrated below for a single LPG (in practice, this logic is replicated for each LPG that is identified in the system): + +![Alert Handler LPG Ctrl](alert_handler_lpg_ctrl.svg) + +The clock gating enable (`lpg_cg_en`) and reset enable (`lpg_rst_en`) indications are routed as multibit signals to the alert handler, where they are synchronized to the alert handler clock and logically combined using an OR function to form a combined low-power indication signal that is multibit encoded. + +This multibit indication signal is then routed to all alert receivers, where it is used to trigger re-initialization of each alert channel, and bypass the ping requests from the ping mechanism. + +To that end, two extra *init states* are added to the alert receiver FSMs to perform this in-band reset, as indicated in the state diagram below: + +![Alert Handler Receiver FSM](alert_handler_receiver_fsm.svg) + +Whenever the `init_trig` multibit signal of an LPG is asserted, all corresponding sender FSMs are moved into the `InitReq` state. +In that state, the alert receivers immediately acknowledge ping requests from the ping mechanism, and ignore alert events from the sender side. +In addition to that, the receivers intentionally place a signal integrity error onto the `ping_p` / `ping_n`, `ack_p` / `ack_n` lines going from receivers to the senders. +This causes the senders to 1) move into the signal integrity error state, and 2) respond by placing a signal integrity error onto the `alert_p` / `alert_n` lines, which serves as an initialization "acknowledge" signal in this case. +Since the sender FSMs fall back into the `Idle` state once the signal integrity error disappears, this procedure essentially implements an in-band reset mechanism with an acknowledgement handshake that can be used to determine whether the reset has been successful. + +#### Implementation Aspects + +##### Ping Mechanism Bypass + +Note that the ping bypass mechanism is to be implemented in a way that pings are only ack'ed immediately if 1) the FSM is in the `InitReq` state, and 2) the `init_trig` signal is still asserted. + +This allows to subject the initialization process of each alert channel to the ping mechanism for channels that are recovering from a reset or clock gated cycle on the sender side. +I.e., alert channels that get stuck during the initialization process can be detected by the ping mechanism since ping requests are not immediately ack'ed anymore once `init_trig` is deasserted. + +##### FSM Encoding + +Since there are many alert channels in the design, the receiver and sender FSMs themselves are not sparsely encoded. +Instead, we rely on the ping mechanism to detect alert channels that are in a bad state. +The specific implementation of the ping bypass mentioned in the previous subsection ensures that the ping mechanism can also be used to monitor the initialization sequence of alert channels. + +##### Latency / Skew Considerations + +Due to asynchronous transitions and different path latencies in the system, a change in reset or clock gating state will experience a different latency through the alert channels than through the indication signals (`rst_n` and `clk_en`) that are connected to the low-power control logic. + +It is consequently possible for a group of alert senders to already be in reset or clock gated state, while the corresponding LPG logic does not yet know about this state change - and vice versa. + +In practice, this means that ping requests may be pending for several cycles until the LPG logic detects a reset or clock-gated condition and disables the corresponding alert channel(s). +Fortunately, such delay can be tolerated by setting the ping timeout to a sufficiently large value (see [`CLASSA_TIMEOUT_CYC_SHADOWED`](../data/alert_handler.hjson#classa_timeout_cyc_shadowed)). + +As for alert events, this latency difference should not pose a problem. +Alert events may get stuck in the alert sender due to a reset or clock-gated condition - but this is to be expected. + +##### Integration Considerations + +Note that due to the aforementioned latency tolerance built into the ping timer, it is permissible to connect **any** reset or clock enable indication signal from the relevant clock group to the LPG logic. +I.e., the only requirement is that the indication signals are logically related to the resets and clocks routed to the alert senders, and that the skew between reset / clock state changes and the indication signals is bounded. + +The topgen script is extended so that it can identify all LPGs and the associated alert channels. +This information is then used to parameterize the alert handler design, and make the necessary top-level connections from the reset and clock management controllers to the alert handler. + +### Hardening Against Glitch Attacks + +In addition to the differential alert and escalation signalling scheme, the internal state machines and counters are hardened against glitch attacks as described bellow: + +1. Ping Timer: + - The FSM is sparsely encoded. + - The LFSR and the counter are duplicated. + - If the FSM or counter are glitched into an invalid state, all internal ping fail alerts will be permanently asserted. + +2. Escalation Timers: + - The escalation timer FSMs are sparsely encoded. + - The escalation timer counters are duplicated. + - The escalation accumulators are duplicated. + - If one of these FSMs, counters or accumulators are glitched into an invalid state, all escalation actions will be triggered and the affected FSM goes into a terminal `FsmError` state. + +3. CSRs: + - Critical configuration CSRs are shadowed. + - The shadow CSRs can trigger additional internal alerts for CSR storage and update failures. + These internal alerts are fed back into the alert classifier in the same manner as the ping and integrity failure alerts. + +4. LPGs: + - Clock-gated and reset-asserted indication signals that are routed from clock and reset managers to the alert handler are encoded with multibit signals. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/README.md new file mode 100644 index 00000000000..f747f76b52c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/README.md @@ -0,0 +1,119 @@ +# ALERT_HANDLER DV document + +## Goals +* **DV** + * Verify all ALERT_HANDLER IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules + * Verify transmitter and receiver pairs for alert (/hw/ip/prim/dv/prim_alert) and escalation (/hw/ip/prim/dv/prim_esc) via direct stimulus. +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + * Verify transmitter and receiver pairs for alert and escalator + * Verify alert_handler_esc_timer and alert_handler_ping_timer + +## Current status +* [Design & verification stage](../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_earlgrey/ip_autogen/alert_handler/dv/latest/report.html) + +## Design features +For detailed information on ALERT_HANDLER design features, please see the [ALERT_HANDLER HWIP technical specification](../README.md). + +## Testbench architecture +ALERT_HANDLER testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at `hw/ip/alert_handler/dv/tb/tb.sv`. It instantiates the ALERT_HANDLER DUT module `hw/ip/alert_handler/rtl/alert_handler.sv`. +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* ALERT_HANDLER IOs +* Alerts and escalations([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md#pins_if)) + +The alert_handler testbench environment can be reused in chip level testing. + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Global types & methods +All common types and methods defined at the package level can be found in +`alert_handler_env_pkg`. Some of them in use are: +```systemverilog + parameter uint NUM_MAX_ESC_SEV = 8; +``` + +### TL_agent +ALERT_HANDLER testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) +which provides the ability to drive and independently monitor random traffic via +TL host interface into ALERT_HANDLER device. + +### ALERT_ESC Agent +[ALERT_ESC agent](../../../../dv/sv/alert_esc_agent/README.md) is used to drive and monitor transmitter and receiver pairs for the alerts and escalators. +Alert_handler DUT includes alert_receivers and esc_senders, so the alert_esc agent will drive output signals of the alert_senders and esc_receivers. + +### UVM RAL Model +The ALERT_HANDLER RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md). + +### Stimulus strategy +#### Test sequences +All test sequences reside in `hw/ip/alert_handler/dv/env/seq_lib`. +The `alert_handler_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +All test sequences are extended from `alert_handler_base_vseq`. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: +* alert_handler_init: Configure alert_handler DUT by writing to `intr_en`, `alert_en_shadowed_*`, `alert_class_shadowed_*`, `loc_alert_en_shadowed_*`, `loc_alert_class_shadowed_*` registers. +* drive_alert: Drive alert_tx signal pairs through `alert_sender_driver`. +* drive_esc_rsp: Drive esc_rx signal pairs through `esc_receiver_driver`. +* read_ecs_status: Readout registers that reflect escalation status, including `classa/b/c/d_accum_cnt`, `classa/b/c/d_esc_cnt`, and `classa/b/c/d_state`. +* wait_alert_handshake_done: Wait for alert_rx/tx handshake to finish. If the alert's low-power-group(LPG) is enabled, immediately return. +* wait_esc_handshake_done: Wait for esc_rx/tx handshake to finish by reading `class*_state` registers and check esc_rx/tx signals. +* set_alert_lpg: Given alert index, find the linked LPG group and enabled the LPG group by driving `lpg_cg_en` or `lpg_rst_en` to Mubi4True. +* run_esc_rsp_seq_nonblocking: A non-blocking sequence to drive `esc_tx` when received escalation or escalation-ping requests. +* run_alert_ping_rsp_seq_nonblocking: A non-blocking sequence to drive `alert_rx` when received alert-ping requests. + +#### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The detailed covergroups are documented under alert_handler [testplan](#testplan). + +### Self-checking strategy +#### Scoreboard +The `alert_handler_scoreboard` is primarily used for end to end checking. +It creates the following analysis ports to retrieve the data monitored by corresponding interface agents: +* tl_a_chan_fifo: tl address channel +* tl_d_chan_fifo: tl data channel +* alert_fifo: An array of `alert_fifo` that connects to corresponding alert_monitors +* esc_fifo: An array of `esc_fifo` that connects to corresponding esc_monitors + +Alert_handler scoreboard monitors all valid CSR registers, alert handshakes, and escalation handshakes. +To ensure certain alert, interrupt, or escalation signals are triggered at the expected time, the alert_handler scoreboard implemented a few counters: +* intr_cnter_per_class[NUM_ALERT_HANDLER_CLASSES]: Count number of clock cycles that the interrupt bit stays high. + If the stored number is larger than the `timeout_cyc` registers, the corresponding escalation is expected to be triggered +* accum_cnter_per_class[NUM_ALERT_HANDLER_CLASSES]: Count number of alerts triggered under the same class. + If the stored number is larger than the `accum_threshold` registers, the corresponding escalation is expected to be triggered +* esc_cnter_per_signal[NUM_ESC_SIGNALS]: Count number of clock cycles that each escalation signal stays high. + Compare the counter against `phase_cyc` registers + +The alert_handler scoreboard is parameterized to support different number of classes, alert pairs, and escalation pairs. + +#### Assertions +* TLUL assertions: The `tb/alert_handler_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/$CHIP/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson -i alert_handler_smoke +``` +In this run command, $CHIP can be top_earlgrey, etc. + +## Testplan +[Testplan](../data/alert_handler_testplan.hjson) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/alert_handler_sim.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/alert_handler_sim.core new file mode 100644 index 00000000000..ce210d69b2d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/alert_handler_sim.core @@ -0,0 +1,37 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:alert_handler_sim:0.1 +description: "ALERT_HANDLER DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:alert_handler:0.1 + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:alert_handler_tb:0.1 + - lowrisc:darjeeling_no_ibex_dv:alert_handler_cov:0.1 + - lowrisc:darjeeling_no_ibex_dv:alert_handler_sva:0.1 + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: alert_handler + ip_hjson: ../data/alert_handler.hjson + position: prepend + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson new file mode 100644 index 00000000000..4f3efbc4a91 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/alert_handler_sim_cfg.hjson @@ -0,0 +1,153 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: alert_handler + + // Top level dut name (sv module). + dut: alert_handler + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_dv:alert_handler_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/alert_handler_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["alert_handler_bind", + "alert_handler_cov_bind", + "sec_cm_prim_sparse_fsm_flop_bind", + "sec_cm_prim_count_bind", + "sec_cm_prim_double_lfsr_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + overrides: [ + { + name: cover_reg_top_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/top_earlgrey/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg" + } + ] + + // Add ALERT_HANDLER specific exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov/alert_handler_cov_excl.el", + "{self_dir}/cov/alert_handler_cov_unr.el"] + + // Default UVM test and seq class name. + uvm_test: alert_handler_base_test + uvm_test_seq: alert_handler_base_vseq + + // List of test specifications. + tests: [ + { + name: alert_handler_smoke + uvm_test_seq: alert_handler_smoke_vseq + } + + { + name: alert_handler_random_alerts + uvm_test_seq: alert_handler_random_alerts_vseq + } + + { + name: alert_handler_random_classes + uvm_test_seq: alert_handler_random_classes_vseq + } + + { + name: alert_handler_esc_intr_timeout + uvm_test_seq: alert_handler_esc_intr_timeout_vseq + } + + { + name: alert_handler_esc_alert_accum + uvm_test_seq: alert_handler_esc_alert_accum_vseq + } + + { + name: alert_handler_sig_int_fail + uvm_test_seq: alert_handler_sig_int_fail_vseq + } + + { + name: alert_handler_entropy + uvm_test_seq: alert_handler_entropy_vseq + run_opts: ["+test_timeout_ns=1_000_000_000"] + } + + { + name: alert_handler_ping_timeout + uvm_test_seq: alert_handler_ping_timeout_vseq + run_opts: ["+test_timeout_ns=1_000_000_000"] + } + + { + name: alert_handler_lpg + uvm_test_seq: alert_handler_lpg_vseq + run_opts: ["+test_timeout_ns=1_000_000_000"] + } + + { + name: alert_handler_lpg_stub_clk + uvm_test_seq: alert_handler_lpg_stub_clk_vseq + run_opts: ["+test_timeout_ns=1_000_000_000"] + } + + { + name: alert_handler_entropy_stress + uvm_test_seq: alert_handler_entropy_stress_vseq + // This sequence forces signal `wait_cyc_mask_i` to a much smaller value. + // So all the timings are not accurate and we need to disable the scb. + run_opts: ["+en_scb=0"] + reseed: 20 + } + + { + name: alert_handler_stress_all + run_opts: ["+test_timeout_ns=15_000_000_000"] + } + + { + name: alert_handler_shadow_reg_errors_with_csr_rw + run_opts: ["+test_timeout_ns=500_000_000"] + run_timeout_mins: 120 + } + + { + name: alert_handler_alert_accum_saturation + uvm_test_seq: alert_handler_alert_accum_saturation_vseq + // This is a direct sequence that forces the accum_cnt to a large number, so does not support + // scb checkings. + run_opts: ["+en_scb=0"] + reseed: 20 + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["alert_handler_smoke"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov.core new file mode 100644 index 00000000000..3ef37021e46 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:alert_handler_cov:0.1 +description: "ALERT_HANDLER cov bind files" +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_ip:alert_handler_component:0.1 # import alert_handler_pkg + - lowrisc:dv:dv_utils + files: + - alert_handler_cov_bind.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov_bind.sv new file mode 100644 index 00000000000..8686e56b7ea --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov_bind.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Binds ALERT_HANDLER functional coverage interfaces to the top level ALERT_HANDLER module. + +module alert_handler_cov_bind; + import alert_handler_pkg::*; + + bind alert_handler cip_mubi_cov_wrapper#(.NumMubis(NLpg)) u_lpg_cg_en_cov_if ( + .rst_ni (rst_ni), + .mubis (lpg_cg_en_i) + ); + + bind alert_handler cip_mubi_cov_wrapper#(.NumMubis(NLpg)) u_lpg_rst_en_cov_if ( + .rst_ni (rst_ni), + .mubis (lpg_rst_en_i) + ); +endmodule : alert_handler_cov_bind diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov_excl.el new file mode 100644 index 00000000000..fb759d63074 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov_excl.el @@ -0,0 +1,163 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//================================================== +// This file contains the Excluded objects +// Generated By User: chencindy +// Format Version: 2 +// Date: Wed Nov 30 12:30:55 2022 +// ExclMode: default +//================================================== +CHECKSUM: "951561765 3328643058" +INSTANCE: tb.dut.u_ping_timer +Fsm state_q "2842986776" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition AlertPingSt->FsmErrorSt "369->366" +Fsm state_q "2842986776" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition EscWaitSt->FsmErrorSt "182->366" +Fsm state_q "2842986776" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition EscPingSt->FsmErrorSt "29->366" +Fsm state_q "2842986776" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition InitSt->FsmErrorSt "203->366" +CHECKSUM: "3358687906 2811042798" +INSTANCE: tb.dut.gen_classes[0].u_esc_timer +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase1St->FsmErrorSt "340->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase2St->FsmErrorSt "25->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase3St->FsmErrorSt "609->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TerminalSt->FsmErrorSt "895->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TimeoutSt->FsmErrorSt "38->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase0St->FsmErrorSt "901->488" +CHECKSUM: "3358687906 2811042798" +INSTANCE: tb.dut.gen_classes[1].u_esc_timer +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase0St->FsmErrorSt "901->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TerminalSt->FsmErrorSt "895->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TimeoutSt->FsmErrorSt "38->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase3St->FsmErrorSt "609->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase2St->FsmErrorSt "25->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase1St->FsmErrorSt "340->488" +CHECKSUM: "3358687906 2811042798" +INSTANCE: tb.dut.gen_classes[2].u_esc_timer +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase0St->FsmErrorSt "901->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TimeoutSt->FsmErrorSt "38->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TerminalSt->FsmErrorSt "895->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase3St->FsmErrorSt "609->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase2St->FsmErrorSt "25->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase1St->FsmErrorSt "340->488" +CHECKSUM: "3358687906 2811042798" +INSTANCE: tb.dut.gen_classes[3].u_esc_timer +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase1St->FsmErrorSt "340->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase2St->FsmErrorSt "25->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase3St->FsmErrorSt "609->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TerminalSt->FsmErrorSt "895->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition TimeoutSt->FsmErrorSt "38->488" +Fsm state_q "3850519017" +ANNOTATION: "[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV." +Transition Phase0St->FsmErrorSt "901->488" +CHECKSUM: "1268953672 3214085926" +INSTANCE: tb.dut +ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." +Toggle crashdump_o.class_esc_cnt [1][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" +ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." +Toggle crashdump_o.class_esc_cnt [2][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" +ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." +Toggle crashdump_o.class_esc_cnt [3][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" +ANNOTATION: "[LOW_RISK] To reduce the simulation time, the max escalation cycle length is set to 1000." +Toggle crashdump_o.class_esc_cnt [0][31:10] "logic [3:0][31:0]crashdump_o.class_esc_cnt" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.u_ping_timer.u_prim_count_esc_cnt +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.u_ping_timer.u_prim_count_cnt +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.gen_classes[0].u_accu.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.gen_classes[1].u_accu.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.gen_classes[2].u_accu.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 1403235006" +INSTANCE: tb.dut.gen_classes[3].u_accu.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[15:0]" +CHECKSUM: "2301929872 277894862" +INSTANCE: tb.dut.gen_classes[0].u_esc_timer.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle set_cnt_i "net set_cnt_i[31:0]" +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[31:0]" +CHECKSUM: "2301929872 277894862" +INSTANCE: tb.dut.gen_classes[1].u_esc_timer.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle set_cnt_i "net set_cnt_i[31:0]" +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[31:0]" +CHECKSUM: "2301929872 277894862" +INSTANCE: tb.dut.gen_classes[2].u_esc_timer.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle set_cnt_i "net set_cnt_i[31:0]" +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[31:0]" +CHECKSUM: "2301929872 277894862" +INSTANCE: tb.dut.gen_classes[3].u_esc_timer.u_prim_count +ANNOTATION: "[UNR]: Tied off to 1." +Toggle step_i "net step_i[31:0]" +ANNOTATION: "[UNR]: Tied off to 1." +Toggle set_cnt_i "net set_cnt_i[31:0]" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov_unr.el b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov_unr.el new file mode 100644 index 00000000000..392540ba67c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cov_unr.el @@ -0,0 +1,933 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//================================================== +// This file contains the Excluded objects +// Generated By User: miguelosorio +// Format Version: 2 +// Date: Fri Aug 16 16:37:33 2024 +// ExclMode: default +//================================================== +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_4 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_5 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_6 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_7 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_8 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_9 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_10 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_11 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_12 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: 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phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_clr_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_accum_thresh_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_crashdump_trigger_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase0_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase1_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase2_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classa_phase3_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_lock +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1549052440 1514362506" +INSTANCE: tb.dut.u_alert_handler_lpg_ctrl +ANNOTATION: "VC_COV_UNR" +Block 30 "3894967986" "unused_lpg_init_trig ^= (^lpg_init_trig[k]);" +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_ping_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_clr_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_accum_thresh_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_crashdump_trigger_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase0_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase1_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase2_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classb_phase3_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_lock +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_accum_thresh_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_crashdump_trigger_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase0_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase1_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase2_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classc_phase3_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_lock +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e1 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e2 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e3 +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_accum_thresh_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_timeout_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_crashdump_trigger_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase0_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase1_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase2_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "1923524726 1594399761" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_classd_phase3_cyc_shadowed +ANNOTATION: "VC_COV_UNR" +Condition 5 "2665247081" "(we & phase_q & ((~err_update)) & ((~err_storage))) 1 -1" (4 "1110") +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_reg_wrap.u_reg.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") +CHECKSUM: "3655552781 2169403375" +INSTANCE: tb.dut.u_edn_req.u_prim_packer_fifo +ANNOTATION: "VC_COV_UNR" +Condition 9 "2531947712" "(gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 11 "1372743715" "(gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 16 "1428458034" "(( ! (depth_q == '0) ) && ((!clr_q))) 1 -1" (2 "10") +CHECKSUM: "571876547 4131299725" +INSTANCE: tb.dut.gen_classes[0].u_esc_timer +ANNOTATION: "VC_COV_UNR" +Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +CHECKSUM: "571876547 4131299725" +INSTANCE: tb.dut.gen_classes[1].u_esc_timer +ANNOTATION: "VC_COV_UNR" +Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +CHECKSUM: "571876547 4131299725" +INSTANCE: tb.dut.gen_classes[2].u_esc_timer +ANNOTATION: "VC_COV_UNR" +Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +CHECKSUM: "571876547 4131299725" +INSTANCE: tb.dut.gen_classes[3].u_esc_timer +ANNOTATION: "VC_COV_UNR" +Condition 1 "1114111443" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 4 "687068015" "(accu_trig_i && en_i && ((!clr_i))) 1 -1" (2 "101") +CHECKSUM: "3655552781 749591850" +INSTANCE: tb.dut.u_edn_req.u_prim_packer_fifo +ANNOTATION: "VC_COV_UNR" +Branch 0 "3339891226" "clear_status" (2) "clear_status 0,0,1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "3667320634" "clear_status" (1) "clear_status 0,1" +CHECKSUM: "1549052440 851307434" +INSTANCE: tb.dut.u_alert_handler_lpg_ctrl +ANNOTATION: "VC_COV_UNR" +Branch 0 "3440992731" "(!lpg_used)" (0) "(!lpg_used) 1" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg new file mode 100644 index 00000000000..33d5c073ced --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/cov/alert_handler_cover_reg_top.cfg @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Limits coverage collection only to the *_reg_top module and the TL interface +// of the DUT. +// Alert_handler wraps alert_handler_reg_top with alert_handler_reg_wrap, so this overwrites the +// common cfg file to include the alert_handler_reg_wrap module. + ++moduletree *_reg_wrap ++node tb.dut tl_* +-module prim_cdc_rand_delay // DV construct. +-module prim_onehot_check // FPV verified + +begin assert + +moduletree *csr_assert_fpv + +moduletree tlul_assert +end + +// Remove everything else from toggle coverage except: +// - `prim_alert_sender`: the `alert_test` task under `cip_base_vseq` drives `alert_test_i` and +// verifies `alert_rx/tx` handshake in each IP. +begin tgl + -tree tb + +module prim_alert_sender +end diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/doc/tb.svg b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/doc/tb.svg new file mode 100644 index 00000000000..e02634731aa --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env.core new file mode 100644 index 00000000000..37181fc3f3c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env.core @@ -0,0 +1,54 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:alert_handler_env:0.1 +description: "ALERT_HANDLER DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:darjeeling_no_ibex_ip:alert_handler_pkg:0.1 + - lowrisc:prim:mubi_pkg + - lowrisc:darjeeling_no_ibex_constants:top_pkg + files: + - alert_handler_env_pkg.sv + - alert_handler_if.sv + - alert_handler_env_cfg.sv: {is_include_file: true} + - alert_handler_env_cov.sv: {is_include_file: true} + - alert_handler_virtual_sequencer.sv: {is_include_file: true} + - alert_handler_scoreboard.sv: {is_include_file: true} + - alert_handler_env.sv: {is_include_file: true} + - seq_lib/alert_handler_vseq_list.sv: {is_include_file: true} + - seq_lib/alert_handler_base_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_common_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_smoke_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_random_alerts_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_random_classes_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_esc_intr_timeout_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_esc_alert_accum_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_sig_int_fail_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_entropy_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_ping_timeout_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_lpg_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_lpg_stub_clk_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_entropy_stress_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/alert_handler_alert_accum_saturation_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: alert_handler + ip_hjson: ../../data/alert_handler.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env.sv new file mode 100644 index 00000000000..a98944894ed --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env.sv @@ -0,0 +1,80 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_env extends cip_base_env #( + .CFG_T (alert_handler_env_cfg), + .COV_T (alert_handler_env_cov), + .VIRTUAL_SEQUENCER_T(alert_handler_virtual_sequencer), + .SCOREBOARD_T (alert_handler_scoreboard) + ); + `uvm_component_utils(alert_handler_env) + + `uvm_component_new + + alert_esc_agent alert_host_agent[]; + alert_esc_agent esc_device_agent[]; + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + // build alert agents + alert_host_agent = new[NUM_ALERTS]; + virtual_sequencer.alert_host_seqr_h = new[NUM_ALERTS]; + foreach (alert_host_agent[i]) begin + alert_host_agent[i] = alert_esc_agent::type_id::create( + $sformatf("alert_host_agent[%0d]", i), this); + uvm_config_db#(alert_esc_agent_cfg)::set(this, + $sformatf("alert_host_agent[%0d]", i), "cfg", cfg.alert_host_cfg[i]); + cfg.alert_host_cfg[i].en_cov = cfg.en_cov; + cfg.alert_host_cfg[i].clk_freq_mhz = int'(cfg.clk_freq_mhz); + end + + // build escalator agents + esc_device_agent = new[NUM_ESCS]; + virtual_sequencer.esc_device_seqr_h = new[NUM_ESCS]; + foreach (esc_device_agent[i]) begin + esc_device_agent[i] = alert_esc_agent::type_id::create( + $sformatf("esc_device_agent[%0d]", i), this); + uvm_config_db#(alert_esc_agent_cfg)::set(this, + $sformatf("esc_device_agent[%0d]", i), "cfg", cfg.esc_device_cfg[i]); + cfg.esc_device_cfg[i].en_cov = cfg.en_cov; + end + + // get vifs + if (!uvm_config_db#(crashdump_vif)::get(this, "", "crashdump_vif", cfg.crashdump_vif)) begin + `uvm_fatal(get_full_name(), "failed to get crashdump_vif from uvm_config_db") + end + if (!uvm_config_db#(alert_handler_vif)::get(this, "", "alert_handler_vif", + cfg.alert_handler_vif)) begin + `uvm_fatal(`gfn, "failed to get alert_handler_vif from uvm_config_db") + end + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + if (cfg.en_scb) begin + foreach (alert_host_agent[i]) begin + alert_host_agent[i].monitor.alert_esc_port.connect( + scoreboard.alert_fifo[i].analysis_export); + end + foreach (esc_device_agent[i]) begin + esc_device_agent[i].monitor.alert_esc_port.connect( + scoreboard.esc_fifo[i].analysis_export); + end + end + if (cfg.is_active) begin + foreach (alert_host_agent[i]) begin + if (cfg.alert_host_cfg[i].is_active) begin + virtual_sequencer.alert_host_seqr_h[i] = alert_host_agent[i].sequencer; + end + end + end + foreach (esc_device_agent[i]) begin + if (cfg.esc_device_cfg[i].is_active) begin + virtual_sequencer.esc_device_seqr_h[i] = esc_device_agent[i].sequencer; + end + end + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv new file mode 100644 index 00000000000..cb1aeb71034 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_env_cfg extends cip_base_env_cfg #(.RAL_T(alert_handler_reg_block)); + + // ext component cfgs + esc_en_vif esc_en_vif; + crashdump_vif crashdump_vif; + alert_handler_vif alert_handler_vif; + rand alert_esc_agent_cfg alert_host_cfg[]; + rand alert_esc_agent_cfg esc_device_cfg[]; + + `uvm_object_utils_begin(alert_handler_env_cfg) + `uvm_field_array_object(alert_host_cfg, UVM_DEFAULT) + `uvm_field_array_object(esc_device_cfg, UVM_DEFAULT) + `uvm_object_utils_end + + `uvm_object_new + + virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1); + num_edn = 1; + super.initialize(csr_base_addr); + shadow_update_err_status_fields[ral.loc_alert_cause[LocalShadowRegUpdateErr].la] = 1; + shadow_storage_err_status_fields[ral.loc_alert_cause[LocalShadowRegStorageErr].la] = 1; + + // set num_interrupts & num_alerts + num_interrupts = ral.intr_state.get_n_used_bits(); + + alert_host_cfg = new[NUM_ALERTS]; + esc_device_cfg = new[NUM_ESCS]; + foreach (alert_host_cfg[i]) begin + alert_host_cfg[i] = + alert_esc_agent_cfg::type_id::create($sformatf("alert_host_cfg[%0d]", i)); + alert_host_cfg[i].if_mode = dv_utils_pkg::Host; + alert_host_cfg[i].is_async = ASYNC_ON[i]; + end + foreach (esc_device_cfg[i]) begin + esc_device_cfg[i] = + alert_esc_agent_cfg::type_id::create($sformatf("esc_device_cfg[%0d]", i)); + esc_device_cfg[i].if_mode = dv_utils_pkg::Device; + esc_device_cfg[i].is_alert = 0; + end + // only support 1 outstanding TL items in tlul_adapter + m_tl_agent_cfg.max_outstanding_req = 1; + endfunction + + // Override shadow register naming checks. The alert handler does not expose any alert signals, + // hence no alerts are defined in Hjson. + virtual function void check_shadow_reg_alerts(); + // Nothing to check. + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env_cov.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env_cov.sv new file mode 100644 index 00000000000..a6094ba17c8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env_cov.sv @@ -0,0 +1,176 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_ping_with_lpg_cg_wrap; + covergroup alert_ping_with_lpg_cg(string name) with function sample (bit lpg_en); + option.per_instance = 1; + option.name = name; + lpg_cg: coverpoint lpg_en { + bins lpg_en = {1}; + bins lpg_dis = {0}; + } + endgroup + + function new(string name); + alert_ping_with_lpg_cg = new(name); + endfunction +endclass + +class alert_handler_env_cov extends cip_base_env_cov #(.CFG_T(alert_handler_env_cfg)); + `uvm_component_utils(alert_handler_env_cov) + + alert_ping_with_lpg_cg_wrap ping_with_lpg_cg_wrap[NUM_ALERTS]; + + // covergroups + covergroup accum_cnt_cg with function sample(int class_index, int cnt); + class_index_cp: coverpoint class_index { + bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + // Due to the limited simulation time, this only collect accum coverage until 2000. For the + // saturation case, design has assertions to cover that. + accum_cnt_cp: coverpoint cnt { + bins accum_cnt_0 = {0}; + bins accum_cnt_10 = {[1:10]}; + bins accum_cnt_50 = {[11:50]}; + bins accum_cnt_100 = {[51:100]}; + bins accum_cnt_1000 = {[101:1000]}; + bins accum_cnt_2000 = {[1001:2000]}; + } + class_cnt_cross: cross class_index_cp, accum_cnt_cp; + endgroup : accum_cnt_cg + + covergroup intr_timeout_cnt_cg with function sample(int class_index, int cnt); + class_index_cp: coverpoint class_index { + bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + intr_timeout_cnt_cp: coverpoint cnt { + bins intr_timeout_cnt[10] = {[0:1000]}; + } + class_cnt_cross: cross class_index_cp, intr_timeout_cnt_cp; + endgroup + + covergroup esc_sig_length_cg with function sample(int sig_index, int sig_len); + esc_sig_index_cp: coverpoint sig_index { + bins index[NUM_ESC_SIGNALS] = {[0:NUM_ESC_SIGNALS-1]}; + } + esc_sig_len_cp: coverpoint sig_len { + bins len_2 = {2}; + bins lens_less_than_1000[10] = {[3:1000]}; + } + len_per_esc_sig: cross esc_sig_index_cp, esc_sig_len_cp; + endgroup : esc_sig_length_cg + + covergroup clear_intr_cnt_cg with function sample(int class_index); + clear_intr_cnt_cp: coverpoint class_index { + bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + endgroup + + covergroup clear_esc_cnt_cg with function sample(int class_index); + clear_esc_cnt_cp: coverpoint class_index { + bins class_index[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + endgroup + + covergroup alert_cause_cg with function sample(int alert_index, int class_index); + alert_cause_cp: coverpoint alert_index { + bins alert[NUM_ALERTS] = {[0:NUM_ALERTS-1]}; + } + class_index_cp: coverpoint class_index { + bins class_i[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + alert_cause_cross_class_index: cross alert_cause_cp, class_index_cp; + endgroup + + covergroup alert_loc_alert_cause_cg with function sample(local_alert_type_e local_alert, + int alert_index, + int class_index); + loc_alert_cause_cp: coverpoint local_alert { + bins alert_ping_fail = {LocalAlertPingFail}; + bins alert_integrity_fail = {LocalAlertIntFail}; + } + alert_index_cp: coverpoint alert_index { + bins alert[NUM_ALERTS] = {[0:NUM_ALERTS-1]}; + } + class_index_cp: coverpoint class_index { + bins class_i[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + loc_alert_cause_cross_alert_index: cross loc_alert_cause_cp, alert_index_cp; + loc_alert_cause_cross_class_index: cross loc_alert_cause_cp, class_index_cp; + endgroup + + covergroup esc_loc_alert_cause_cg with function sample(local_alert_type_e local_alert, + int esc_index, + int class_index); + loc_alert_cause_cp: coverpoint local_alert { + bins esc_ping_fail = {LocalEscPingFail}; + bins esc_integrity_fail = {LocalEscIntFail}; + } + esc_index_cp: coverpoint esc_index { + bins alert[NUM_ESCS] = {[0:NUM_ESCS-1]}; + } + class_index_cp: coverpoint class_index { + bins class_i[NUM_ALERT_CLASSES] = {[0:NUM_ALERT_CLASSES-1]}; + } + loc_alert_cause_cross_alert_index: cross loc_alert_cause_cp, esc_index_cp; + loc_alert_cause_cross_class_index: cross loc_alert_cause_cp, class_index_cp; + endgroup + + covergroup crashdump_trigger_cg with function sample(bit [1:0] phase); + crashdump_trigger_phase_cp: coverpoint phase { + bins phase_0 = {0}; + bins phase_1 = {1}; + bins phase_2 = {2}; + bins phase_3 = {3}; + } + endgroup + + // Covergroup to make sure simulation is long enough to fetch more than five EDN requests. + covergroup num_edn_reqs_cg with function sample(int num_edn_reqs); + num_edn_reqs_cp: coverpoint num_edn_reqs { + bins less_than_five_reqs = {[1:4]}; + bins five_or_more_reqs = {[5:$]}; + } + endgroup + + covergroup num_checked_pings_cg with function sample (int num_pings); + num_pings_cp: coverpoint num_pings { + bins less_than_ten_pings = {[1:9]}; + bins ten_to_twenty_pings = {[10:19]}; + bins more_than_twenty_pings = {[20:$]}; + } + endgroup + + covergroup cycles_between_pings_cg with function sample (int num_cycles_between_pings); + num_cycles_cp: coverpoint num_cycles_between_pings{ + bins less_than_5000_cycs = {[1:4_999]}; + bins less_than_100k_cycs = {[5_000:99_999]}; + bins less_than_150k_cycs = {[5_000:149_999]}; + bins less_than_200k_cycs = {[150_000:199_999]}; + bins more_than_200k_cycs = {[200_000:$]}; + } + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + accum_cnt_cg = new(); + intr_timeout_cnt_cg = new(); + esc_sig_length_cg = new(); + clear_intr_cnt_cg = new(); + clear_esc_cnt_cg = new(); + alert_cause_cg = new(); + alert_loc_alert_cause_cg = new(); + esc_loc_alert_cause_cg = new(); + crashdump_trigger_cg = new(); + + num_edn_reqs_cg = new(); + num_checked_pings_cg = new(); + cycles_between_pings_cg = new(); + + foreach (ping_with_lpg_cg_wrap[i]) begin + ping_with_lpg_cg_wrap[i] = new($sformatf("ping_with_lpg_cg_wrap[%0d]", i)); + end + endfunction : new + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env_pkg.sv new file mode 100644 index 00000000000..54afee0f008 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_env_pkg.sv @@ -0,0 +1,106 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package alert_handler_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import csr_utils_pkg::*; + import tl_agent_pkg::*; + import alert_esc_agent_pkg::*; + import alert_handler_ral_pkg::*; + import dv_base_reg_pkg::*; + import cip_base_pkg::*; + import push_pull_agent_pkg::*; + import sec_cm_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter uint NUM_ALERTS = alert_handler_reg_pkg::NAlerts; + parameter uint NUM_EDN = 1; + parameter uint NUM_ESCS = 4; + parameter uint NUM_MAX_ESC_SEV = 8; + parameter uint NUM_ESC_SIGNALS = 4; + parameter uint NUM_ALERT_CLASSES = 4; + parameter uint NUM_ESC_PHASES = 4; + parameter uint NUM_ALERT_CLASS_MSB = $clog2(NUM_ALERT_CLASSES) - 1; + parameter uint MIN_CYCLE_PER_PHASE = 2; + parameter uint NUM_LOCAL_ALERTS = 7; + parameter bit [NUM_ALERTS-1:0] ASYNC_ON = alert_handler_reg_pkg::AsyncOn; + // ignore esc signal cycle count after ping occurs - as ping response might ended up adding one + // extra cycle to the calculated cnt, or even combine two signals into one. + parameter uint IGNORE_CNT_CHECK_NS = 100_000_000; + // set the max ping timeout cycle to constrain the simulation run time + parameter uint MAX_PING_TIMEOUT_CYCLE = 300; + + // Alert_handler ping timer design should automatically fetch EDN entropy every 500k clock + // cycles. We set the threshold to 600k clock cycles. + parameter uint MAX_EDN_REQ_WAIT_CYCLES = 600_000; + + parameter uint NUM_CRASHDUMP = NUM_ALERT_CLASSES * (alert_handler_reg_pkg::AccuCntDw + + alert_handler_reg_pkg::EscCntDw + 3) + + NUM_ALERTS + NUM_LOCAL_ALERTS; + parameter bit[15:0] MAX_PING_WAIT_CYCLES = '1; + + // types + typedef enum { + EscPhase0, + EscPhase1, + EscPhase2, + EscPhase3 + } esc_phase_e; + + typedef enum { + AlertClassCtrlEn, + AlertClassCtrlLock, + AlertClassCtrlEnE0, + AlertClassCtrlEnE1, + AlertClassCtrlEnE2, + AlertClassCtrlEnE3, + AlertClassCtrlMapE0, + AlertClassCtrlMapE1, + AlertClassCtrlMapE2, + AlertClassCtrlMapE3 + } alert_class_ctrl_e; + + typedef enum { + EscStateIdle = 'b000, + EscStateTimeout = 'b001, + EscStateTerminal = 'b011, + EscStatePhase0 = 'b100, + EscStatePhase1 = 'b101, + EscStatePhase2 = 'b110, + EscStatePhase3 = 'b111 + } esc_state_e; + + typedef enum { + LocalAlertPingFail, + LocalEscPingFail, + LocalAlertIntFail, + LocalEscIntFail, + LocalBusIntgFail, + LocalShadowRegUpdateErr, + LocalShadowRegStorageErr + } local_alert_type_e; + + // forward declare classes to allow typedefs below + typedef virtual pins_if #(NUM_MAX_ESC_SEV) esc_en_vif; + typedef virtual pins_if #(NUM_CRASHDUMP) crashdump_vif; + typedef virtual alert_handler_if alert_handler_vif; + + // functions + + // package sources + `include "alert_handler_env_cfg.sv" + `include "alert_handler_env_cov.sv" + `include "alert_handler_virtual_sequencer.sv" + `include "alert_handler_scoreboard.sv" + `include "alert_handler_env.sv" + `include "alert_handler_vseq_list.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_if.sv new file mode 100644 index 00000000000..26c2a85fce9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_if.sv @@ -0,0 +1,60 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Interface for LPG and crashdump output. +interface alert_handler_if(input clk, input rst_n); + import uvm_pkg::*; + import alert_handler_pkg::*; + import prim_mubi_pkg::*; + import cip_base_pkg::*; + import alert_handler_env_pkg::*; + + mubi4_t [NLpg-1:0] lpg_cg_en; + mubi4_t [NLpg-1:0] lpg_rst_en; + + logic [NUM_ALERTS-1:0] alert_ping_reqs; + logic [NUM_ESCS-1:0] esc_ping_reqs; + + string msg_id = "alert_handler_if"; + + function automatic void init(); + mubi4_t mubi_false_val = get_rand_mubi4_val(0, 1, 1); + lpg_cg_en = '{default: mubi_false_val}; + lpg_rst_en = '{default: mubi_false_val}; + endfunction + + function automatic bit get_lpg_status(int index); + check_lpg_index(index); + return (lpg_cg_en[index] == MuBi4True || lpg_rst_en[index] == MuBi4True); + endfunction + + function automatic void set_lpg_cg_en(int index); + check_lpg_index(index); + lpg_cg_en[index] = MuBi4True; + endfunction + + function automatic void set_lpg_rst_en(int index); + check_lpg_index(index); + lpg_rst_en[index] = MuBi4True; + endfunction + + function automatic void check_lpg_index(int index); + if (index >= NLpg) begin + `uvm_fatal(msg_id, $sformatf("Alert_handler has %0d LPGs but attempts to set index %0d", + NLpg, index)) + end + endfunction + + task automatic set_wait_cyc_mask(logic [PING_CNT_DW-1:0] val); + static logic [PING_CNT_DW-1:0] val_static; + begin + val_static = val; + force tb.dut.u_ping_timer.wait_cyc_mask_i = val_static; + end + endtask + + task automatic release_wait_cyc_mask(); + release tb.dut.u_ping_timer.wait_cyc_mask_i; + endtask +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_scoreboard.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_scoreboard.sv new file mode 100644 index 00000000000..cc261bd7d6a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_scoreboard.sv @@ -0,0 +1,793 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`define ASSIGN_CLASS_PHASE_REGS(index, i) \ + reg_esc_phase_cycs_per_class_q[``index``] = \ + {ral.class``i``_phase0_cyc_shadowed, ral.class``i``_phase1_cyc_shadowed, \ + ral.class``i``_phase2_cyc_shadowed, ral.class``i``_phase3_cyc_shadowed}; + +class alert_handler_scoreboard extends cip_base_scoreboard #( + .CFG_T(alert_handler_env_cfg), + .RAL_T(alert_handler_reg_block), + .COV_T(alert_handler_env_cov) + ); + `uvm_component_utils(alert_handler_scoreboard) + + // esc_phase_cyc_per_class_q: each class has four phase cycles, stores each cycle length + // --- class --- phase0_cyc --- phase1_cyc --- phase2_cyc --- phase3_cyc --- + // --- A -classa_phase0_cyc - classa_phase1_cyc - classa_phase2_cyc - classa_phase3_cyc -- + // --- B -classb_phase0_cyc - classb_phase1_cyc - classb_phase2_cyc - classb_phase3_cyc -- + // --- C -classc_phase0_cyc - classc_phase1_cyc - classc_phase2_cyc - classc_phase3_cyc -- + // --- D -classd_phase0_cyc - classd_phase1_cyc - classd_phase2_cyc - classd_phase3_cyc -- + dv_base_reg reg_esc_phase_cycs_per_class_q[NUM_ALERT_CLASSES][$]; + + uvm_reg_field intr_state_fields[$]; + uvm_reg_field intr_state_field; + // once escalation triggers, no alerts can trigger another escalation in the same class + // until the class esc is cleared + bit [NUM_ALERT_CLASSES-1:0] under_esc_classes; + bit [NUM_ALERT_CLASSES-1:0] under_intr_classes; + bit [NUM_ALERT_CLASSES-1:0] clr_esc_under_intr; + int intr_cnter_per_class [NUM_ALERT_CLASSES]; + int accum_cnter_per_class [NUM_ALERT_CLASSES]; + esc_state_e state_per_class [NUM_ALERT_CLASSES]; + int esc_signal_release [NUM_ESC_SIGNALS]; + int esc_sig_class [NUM_ESC_SIGNALS]; // one class can increment one esc signal at a time + // For different alert classify in the same class and trigger at the same cycle, design only + // count once. So record the alert triggered timing here + realtime last_triggered_alert_per_class[NUM_ALERT_CLASSES]; + + string class_name[] = {"a", "b", "c", "d"}; + bit [TL_DW-1:0] intr_state_val; + + bit [NUM_ALERT_CLASSES-1:0] crashdump_triggered = 0; + + bit ping_timer_en; + + // TLM agent fifos + uvm_tlm_analysis_fifo #(alert_esc_seq_item) alert_fifo[NUM_ALERTS]; + uvm_tlm_analysis_fifo #(alert_esc_seq_item) esc_fifo[NUM_ESCS]; + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + ral.intr_state.get_fields(intr_state_fields); + `ASSIGN_CLASS_PHASE_REGS(0, a) + `ASSIGN_CLASS_PHASE_REGS(1, b) + `ASSIGN_CLASS_PHASE_REGS(2, c) + `ASSIGN_CLASS_PHASE_REGS(3, d) + + foreach (alert_fifo[i]) alert_fifo[i] = new($sformatf("alert_fifo[%0d]", i), this); + foreach (esc_fifo[i]) esc_fifo[i] = new($sformatf("esc_fifo[%0d]" , i), this); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + fork + process_alert_fifo(); + process_esc_fifo(); + process_edn_fifos(); + check_ping_timer(); + check_crashdump(); + check_intr_timeout_trigger_esc(); + esc_phase_signal_cnter(); + release_esc_signal(); + join_none + endtask + + virtual task process_alert_fifo(); + foreach (alert_fifo[i]) begin + automatic int index = i; + automatic int lpg_index = alert_handler_reg_pkg::LpgMap[index]; + fork + forever begin + bit alert_en, loc_alert_en; + alert_esc_seq_item act_item; + alert_fifo[index].get(act_item); + alert_en = ral.alert_en_shadowed[index].get_mirrored_value() && + prim_mubi_pkg::mubi4_test_false_loose(cfg.alert_handler_vif.lpg_cg_en[lpg_index]) && + prim_mubi_pkg::mubi4_test_false_loose(cfg.alert_handler_vif.lpg_rst_en[lpg_index]); + + // Check that ping mechanism will only ping alerts that have been enabled and locked. + if (act_item.alert_esc_type == AlertEscPingTrans) begin + `DV_CHECK(alert_en, $sformatf("alert %0s ping triggered but not enabled", index)) + `DV_CHECK((`gmv(ral.alert_regwen[index]) == 0), + $sformatf("alert %0s ping triggered but not locked", index)) + end + + if (alert_en) begin + // alert detected + if (act_item.alert_esc_type == AlertEscSigTrans && !act_item.ping_timeout && + act_item.alert_handshake_sta == AlertReceived) begin + process_alert_sig(index, 0); + // alert integrity fail + end else if (act_item.alert_esc_type == AlertEscIntFail) begin + loc_alert_en = ral.loc_alert_en_shadowed[LocalAlertIntFail].get_mirrored_value(); + if (loc_alert_en) process_alert_sig(index, 1, LocalAlertIntFail); + end else if (act_item.alert_esc_type == AlertEscPingTrans && + act_item.ping_timeout) begin + loc_alert_en = ral.loc_alert_en_shadowed[LocalAlertPingFail].get_mirrored_value(); + if (loc_alert_en) begin + process_alert_sig(index, 1, LocalAlertPingFail); + `uvm_info(`gfn, $sformatf("alert %0d ping timeout, timeout_cyc reg is %0d", + index, ral.ping_timeout_cyc_shadowed.get_mirrored_value()), UVM_LOW); + end + end + end + end + join_none + end + endtask : process_alert_fifo + + virtual task process_esc_fifo(); + foreach (esc_fifo[i]) begin + automatic int index = i; + fork + forever begin + alert_esc_seq_item act_item; + esc_fifo[index].get(act_item); + // escalation triggered, check signal length + if (act_item.alert_esc_type == AlertEscSigTrans && + act_item.esc_handshake_sta == EscRespComplete) begin + check_esc_signal(act_item.sig_cycle_cnt, index); + // escalation integrity fail + end else if (act_item.alert_esc_type == AlertEscIntFail || + (act_item.esc_handshake_sta == EscIntFail && !act_item.ping_timeout)) begin + bit loc_alert_en = ral.loc_alert_en_shadowed[LocalEscIntFail].get_mirrored_value(); + if (loc_alert_en) process_alert_sig(index, 1, LocalEscIntFail); + // escalation ping timeout + end else if (act_item.alert_esc_type == AlertEscPingTrans) begin + if (act_item.ping_timeout) begin + bit loc_alert_en = ral.loc_alert_en_shadowed[LocalEscPingFail].get_mirrored_value(); + if (loc_alert_en) begin + process_alert_sig(index, 1, LocalEscPingFail); + `uvm_info(`gfn, $sformatf("esc %0d ping timeout, timeout_cyc reg is %0d", + index, ral.ping_timeout_cyc_shadowed.get_mirrored_value()), UVM_LOW); + end + end + end + end + join_none + end + endtask : process_esc_fifo + + // Alert_handler ping timer is designed to fetch EDN value periodically. + virtual task process_edn_fifos(); + fork begin: isolation_fork + int num_edn_reqs; + forever begin + wait (cfg.under_reset == 0); + fork + begin + check_edn_request_cycles(); + num_edn_reqs++; + if (cfg.en_cov) cov.num_edn_reqs_cg.sample(num_edn_reqs); + end + begin + wait (cfg.under_reset == 1); + num_edn_reqs = 0; + end + join_any + disable fork; + end + end join + endtask + + virtual task check_edn_request_cycles(); + int edn_wait_cycles; + fork + begin : isolation_fork + fork + begin + while (edn_wait_cycles < MAX_EDN_REQ_WAIT_CYCLES) begin + cfg.clk_rst_vif.wait_clks(1); + edn_wait_cycles++; + end + `uvm_error(`gfn, "Timeout occured waiting for an EDN request!"); + end + begin + push_pull_item#(.DeviceDataWidth(EDN_DATA_WIDTH)) edn_item; + edn_fifos[0].get(edn_item); + end + join_any + disable fork; + end + join + endtask + + // this task process alert signal by checking if intergrity fail, then classify it to the + // mapping classes, then check if escalation is triggered by accumulation + // this task delayed to a negedge clk to avoid updating and checking regs at the same time + virtual task process_alert_sig(int alert_i, bit is_int_err, + local_alert_type_e local_alert_type = LocalAlertIntFail); + fork + begin + cfg.clk_rst_vif.wait_n_clks(1); + if (!under_reset) begin + bit [TL_DW-1:0] intr_en, class_ctrl; + bit [NUM_ALERT_CLASS_MSB:0] class_i; + if (!is_int_err) begin + class_i = `gmv(ral.alert_class_shadowed[alert_i]); + void'(ral.alert_cause[alert_i].predict(1)); + if (cfg.en_cov) begin + cov.alert_cause_cg.sample(alert_i, class_i); + end + end else begin + class_i = `gmv(ral.loc_alert_class_shadowed[int'(local_alert_type)]); + void'(ral.loc_alert_cause[int'(local_alert_type)].predict( + .value(1), .kind(UVM_PREDICT_READ))); + if (local_alert_type inside {LocalAlertPingFail, LocalAlertIntFail}) begin + if (cfg.en_cov) begin + cov.alert_loc_alert_cause_cg.sample(local_alert_type, alert_i, class_i); + end + end else begin + // Check the local alert type equals to the ones defined in the CG: + `DV_CHECK(local_alert_type inside {LocalEscPingFail, LocalEscIntFail}) + if (cfg.en_cov) begin + cov.esc_loc_alert_cause_cg.sample(local_alert_type, alert_i, class_i); + end + end + end + // Check to ensure alert_i and class_i is within bounds + `DV_CHECK(alert_i < NUM_ALERTS && class_i < NUM_ALERT_CLASSES) + + intr_state_field = intr_state_fields[class_i]; + void'(intr_state_field.predict(.value(1), .kind(UVM_PREDICT_READ))); + intr_en = ral.intr_enable.get_mirrored_value(); + + // calculate escalation + class_ctrl = get_class_ctrl(class_i); + `uvm_info(`gfn, $sformatf("class %0d is triggered, class ctrl=%0h, under_esc=%0b", + class_i, class_ctrl, under_esc_classes[class_i]), UVM_DEBUG) + // if class escalation is enabled, add alert to accumulation count + if (class_ctrl[AlertClassCtrlEn] && + (class_ctrl[AlertClassCtrlEnE3:AlertClassCtrlEnE0] > 0)) begin + alert_accum_cal(class_i); + end + + // according to issue #841, interrupt will have one clock cycle delay + // add an extra cycle for synchronizers from clk_edn to clk + cfg.clk_rst_vif.wait_n_clks(1); + if (!under_reset) begin + `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[class_i], intr_en[class_i], + $sformatf("Interrupt class_%s, is_local_err %0b, local_alert_type %s", + class_name[class_i],is_int_err, local_alert_type)); + if (!under_intr_classes[class_i] && intr_en[class_i]) under_intr_classes[class_i] = 1; + end + end + end + join_none + endtask + + // calculate alert accumulation count per class, if accumulation exceeds the threshold, + // and if current class is not under escalation, then predict escalation + // note: if more than one alerts triggered on the same clk cycle, only accumulates one + virtual function void alert_accum_cal(int class_i); + bit [TL_DW-1:0] accum_thresh = get_class_accum_thresh(class_i); + realtime curr_time = $realtime(); + if (curr_time != last_triggered_alert_per_class[class_i] && !cfg.under_reset) begin + last_triggered_alert_per_class[class_i] = curr_time; + // avoid accum_cnt saturate + if (accum_cnter_per_class[class_i] < 'hffff) begin + accum_cnter_per_class[class_i] += 1; + if (accum_cnter_per_class[class_i] > accum_thresh && !under_esc_classes[class_i]) begin + predict_esc(class_i); + end + end + end + `uvm_info(`gfn, + $sformatf("alert_accum: class=%0d, alert_cnt=%0d, thresh=%0d, under_esc=%0b", + class_i, accum_cnter_per_class[class_i], accum_thresh, + under_esc_classes[class_i]), UVM_DEBUG) + endfunction + + // if clren register is disabled, predict escalation signals by setting the corresponding + // under_esc_classes bit based on class_ctrl's lock bit + virtual function void predict_esc(int class_i); + bit [TL_DW-1:0] class_ctrl = get_class_ctrl(class_i); + if (class_ctrl[AlertClassCtrlLock]) begin + uvm_reg clren_rg; + clren_rg = ral.get_reg_by_name($sformatf("class%s_clr_regwen", class_name[class_i])); + `DV_CHECK_NE_FATAL(clren_rg, null) + void'(clren_rg.predict(0)); + end + under_esc_classes[class_i] = 1; + endfunction + + // check if escalation signal's duration length is correct + virtual function void check_esc_signal(int cycle_cnt, int esc_sig_i); + int class_a = `gmv(ral.classa_ctrl_shadowed); + int class_b = `gmv(ral.classb_ctrl_shadowed); + int class_c = `gmv(ral.classc_ctrl_shadowed); + int class_d = `gmv(ral.classd_ctrl_shadowed); + int sig_index = AlertClassCtrlEnE0+esc_sig_i; + bit [NUM_ALERT_CLASSES-1:0] select_class = {class_d[sig_index], class_c[sig_index], + class_b[sig_index], class_a[sig_index]}; + + + // Only compare the escalation signal length if exactly one class is assigned to this signal. + // Otherwise scb cannot predict the accurate cycle length if multiple classes are merged. + if ($countones(select_class) == 1) begin + int exp_cycle, phase, class_i; + // Find the class that triggers the escalation, and find which phase the escalation signal is + // reflecting. + for (class_i = 0; class_i < NUM_ALERT_CLASSES; class_i++) begin + if (select_class[class_i] == 1) begin + phase = `gmv(ral.get_reg_by_name($sformatf("class%0s_ctrl_shadowed", + class_name[class_i]))); + break; + end + end + phase = phase[(AlertClassCtrlMapE0 + esc_sig_i * 2) +: 2]; + exp_cycle = `gmv(ral.get_reg_by_name($sformatf("class%0s_phase%0d_cyc_shadowed", + class_name[class_i], phase))) + 1; + // Minimal phase length is 2 cycles. + exp_cycle = exp_cycle < 2 ? 2 : exp_cycle; + `uvm_info(`gfn, $sformatf("esc_signal_%0d, esc phase %0d, esc class %0d", + esc_sig_i, phase, class_i), UVM_HIGH); + + // If the escalation signal is interrupted by reset or esc_clear, we expect the signal length + // to be shorter than the phase_cycle_length. + if (cfg.under_reset || under_esc_classes[class_i] == 0) begin + `DV_CHECK_LE(cycle_cnt, exp_cycle) + end else begin + `DV_CHECK_EQ(cycle_cnt, exp_cycle) + end + if (cfg.en_cov) cov.esc_sig_length_cg.sample(esc_sig_i, cycle_cnt); + end + esc_sig_class[esc_sig_i] = 0; + endfunction + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + dv_base_reg dv_base_csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = {item.a_addr[TL_AW-1:2], 2'b00}; + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = ral.default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + `downcast(dv_base_csr, csr) + end + if (csr == null) begin + // we hit an oob addr - expect error response and return + `DV_CHECK_EQ(item.d_error, 1'b1) + return; + end + + if (channel == AddrChannel) begin + // if incoming access is a write to a valid csr, then make updates right away + if (write) begin + string csr_name = csr.get_name(); + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + // process the csr req + // for write, update local variable and fifo at address phase + case (csr_name) + // add individual case item for each csr + "intr_test": begin + bit [TL_DW-1:0] intr_state_exp = item.a_data | ral.intr_state.get_mirrored_value(); + if (cfg.en_cov) begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], intr_state_exp[i]); + end + end + void'(ral.intr_state.predict(.value(intr_state_exp), .kind(UVM_PREDICT_DIRECT))); + end + // disable intr_enable or clear intr_state will clear the interrupt timeout cnter + "intr_state": begin + fork + begin + // after interrupt is set, it needs one clock cycle to update the value and stop + // the intr_timeout counter + cfg.clk_rst_vif.wait_clks(1); + if (!cfg.under_reset) begin + foreach (under_intr_classes[i]) begin + if (item.a_data[i]) begin + under_intr_classes[i] = 0; + clr_esc_under_intr[i] = 0; + if (!under_esc_classes[i]) state_per_class[i] = EscStateIdle; + end + end + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), + .be(item.a_mask))); + end + end + join_none + end + "intr_enable": begin + foreach (under_intr_classes[i]) begin + if (item.a_data[i] == 0) under_intr_classes[i] = 0; + end + end + "classa_clr_shadowed": begin + if (!dv_base_csr.is_staged() && ral.classa_clr_regwen.get_mirrored_value()) begin + clr_reset_esc_class(0); + end + end + "classb_clr_shadowed": begin + if (!dv_base_csr.is_staged() && ral.classb_clr_regwen.get_mirrored_value()) begin + clr_reset_esc_class(1); + end + end + "classc_clr_shadowed": begin + if (!dv_base_csr.is_staged() && ral.classc_clr_regwen.get_mirrored_value()) begin + clr_reset_esc_class(2); + end + end + "classd_clr_shadowed": begin + if (!dv_base_csr.is_staged() && ral.classd_clr_regwen.get_mirrored_value()) begin + clr_reset_esc_class(3); + end + end + "ping_timer_en_shadowed": begin + if (shadowed_reg_wr_completed(dv_base_csr) && + item.a_data && + `gmv(ral.ping_timer_regwen)) begin + ping_timer_en = 1; + end + end + "alert_test", "ping_timeout_cyc_shadowed", "ping_timer_regwen": begin + // Do nothing. Already auto update mirrored value. + end + default: begin + // The following regs only need to auto update mirrored value. + if (!uvm_re_match("*alert_en_shadowed*", csr_name) || + !uvm_re_match("*alert_class_shadowed*", csr_name) || + !uvm_re_match("class*_ctrl_shadowed", csr_name) || + !uvm_re_match("class*_crashdump_trigger_shadowed", csr_name) || + !uvm_re_match("class*_phase*_cyc_shadowed", csr_name) || + !uvm_re_match("class*_timeout_cyc_shadowed", csr_name) || + !uvm_re_match("class*_accum_thresh_shadowed", csr_name) || + !uvm_re_match("class*_clr_regwen", csr_name) || + !uvm_re_match("class*_regwen", csr_name) || + !uvm_re_match("*alert_regwen_*", csr_name)) begin + end else begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + end + endcase + end + end + + // process the csr req + // for read, update prediction at address phase and compare at data phase + + if (!write) begin + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (channel == DataChannel) begin + if (cfg.en_cov) begin + if (csr.get_name() == "intr_state") begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + cov.intr_cg.sample(i, intr_en[i], item.d_data[i]); + cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]); + end + end else begin + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + if (csr.get_name() == $sformatf("class%s_accum_cnt", class_name[i])) begin + cov.accum_cnt_cg.sample(i, item.d_data); + end + end + end + end + if (csr.get_name == "intr_state") begin + `DV_CHECK_EQ(intr_state_val, item.d_data, $sformatf("reg name: %0s", "intr_state")) + do_read_check = 0; + end + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end else begin + // predict in address phase to avoid the register's value changed during the read + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + if (csr.get_name() == $sformatf("class%s_esc_cnt", class_name[i])) begin + void'(csr.predict(.value(intr_cnter_per_class[i]), .kind(UVM_PREDICT_READ))); + end else if (csr.get_name() == $sformatf("class%s_accum_cnt", class_name[i])) begin + void'(csr.predict(.value(accum_cnter_per_class[i]), .kind(UVM_PREDICT_READ))); + end else if (csr.get_name() == $sformatf("class%s_state", class_name[i])) begin + void'(csr.predict(.value(state_per_class[i]), .kind(UVM_PREDICT_READ))); + end + end + if (csr.get_name() == "intr_state") intr_state_val = csr.get_mirrored_value(); + end + end + endtask + + virtual task check_ping_timer(); + int num_checked_pings; + fork begin : isolation_fork + forever begin + wait (ping_timer_en == 1); + fork + begin + wait (cfg.under_reset == 1); + ping_timer_en = 0; + num_checked_pings = 0; + end + begin + check_ping_triggered_cycles(); + num_checked_pings++; + if (cfg.en_cov) cov.num_checked_pings_cg.sample(num_checked_pings); + end + join_any + disable fork; + end + end join + endtask + + // This task checks if pings are triggered within the expected time. + // + // The ping timer is 16 bits so ideally we should see alert_ping -> esc_ping -> alert_ping ... + // with the max length of 16'hFFFF clock cycle. However alert_ping is randomly selected so we + // can not guarantee the random alert index is valid (exists), enabld, and locked. + // However, esc ping timer should are always expected to trigger. + // So the max wait time is 'hFFFF*2. + // This task also used the probed design signal instead of detected ping requests from monitor. + // Because if esc ping request and real esc request come at the same time, design will ignore the + // ping requests. But the probed signal will still set to 1. + virtual task check_ping_triggered_cycles(); + int ping_wait_cycs; + while (ping_wait_cycs <= MAX_PING_WAIT_CYCLES * 2) begin + if (cfg.alert_handler_vif.alert_ping_reqs > 0) begin + if (cfg.en_cov) begin + int alert_id = $clog2(cfg.alert_handler_vif.alert_ping_reqs); + cov.ping_with_lpg_cg_wrap[alert_id].alert_ping_with_lpg_cg.sample( + cfg.alert_host_cfg[alert_id].en_alert_lpg); + end + break; + end + if (cfg.alert_handler_vif.esc_ping_reqs > 0) break; + cfg.clk_rst_vif.wait_clks(1); + ping_wait_cycs++; + end + if (ping_wait_cycs > MAX_PING_WAIT_CYCLES * 2) begin + `uvm_error(`gfn, "Timeout occured waiting for a ping."); + end + if (cfg.en_cov) cov.cycles_between_pings_cg.sample(ping_wait_cycs); + + // Wait for ping request to finish to avoid infinite loop. + wait (cfg.alert_handler_vif.alert_ping_reqs == 0 && cfg.alert_handler_vif.esc_ping_reqs == 0); + endtask + + virtual task check_crashdump(); + forever begin + wait (cfg.under_reset == 0 && cfg.en_scb == 1); + @(cfg.crashdump_vif.pins) begin + alert_handler_pkg::alert_crashdump_t crashdump_val = + alert_handler_pkg::alert_crashdump_t'(cfg.crashdump_vif.sample()); + + // Wait two negedge clock cycles to make sure csr mirrored values are updated. + `DV_SPINWAIT_EXIT(cfg.clk_rst_vif.wait_n_clks(2);, wait (cfg.under_reset == 1);) + + if (!cfg.under_reset) begin + // If crashdump reached the phase programmed at `crashdump_trigger_shadowed`, + // `crashdump_o` value should keep stable until reset. + if (crashdump_triggered) begin + `uvm_fatal(`gfn, + "crashdump value should not change after trigger condition is reached!") + end + + foreach (crashdump_val.class_esc_state[i]) begin + uvm_reg crashdump_trigger_csr = ral.get_reg_by_name( + $sformatf("class%0s_crashdump_trigger_shadowed", class_name[i])); + if (crashdump_val.class_esc_state[i] == (`gmv(crashdump_trigger_csr) + 3'b100)) begin + crashdump_triggered[i] = 1; + if (cfg.en_cov) cov.crashdump_trigger_cg.sample(`gmv(crashdump_trigger_csr)); + break; + end + end + + for (int i = 0; i < NUM_ALERTS; i++) begin + `DV_CHECK_EQ(crashdump_val.alert_cause[i], `gmv(ral.alert_cause[i])) + end + for (int i = 0; i < NUM_LOCAL_ALERTS; i++) begin + `DV_CHECK_EQ(crashdump_val.loc_alert_cause[i], `gmv(ral.loc_alert_cause[i])) + end + end + end + end + endtask + + // a counter to count how long each interrupt pins stay high until it is being reset + // if counter exceeds threshold, call predict_esc() function to calculate related esc + virtual task check_intr_timeout_trigger_esc(); + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + fork + automatic int class_i = i; + begin : intr_sig_counter + forever @(under_intr_classes[class_i] && !under_esc_classes[class_i]) begin + fork + begin + bit [TL_DW-1:0] timeout_cyc, class_ctrl; + // if escalation cleared but interrupt not cleared, wait one more clk cycle for the + // FSM to reset to Idle, then start to count + if (clr_esc_under_intr[class_i]) cfg.clk_rst_vif.wait_n_clks(1); + clr_esc_under_intr[class_i] = 0; + // wait a clk for esc signal to go high + cfg.clk_rst_vif.wait_n_clks(1); + class_ctrl = get_class_ctrl(class_i); + if (class_ctrl[AlertClassCtrlEn] && + class_ctrl[AlertClassCtrlEnE3:AlertClassCtrlEnE0] > 0) begin + intr_cnter_per_class[class_i] = 1; + `uvm_info(`gfn, $sformatf("Class %0d start counter", class_i), UVM_HIGH) + timeout_cyc = get_class_timeout_cyc(class_i); + if (timeout_cyc > 0) begin + state_per_class[class_i] = EscStateTimeout; + while (under_intr_classes[class_i]) begin + @(cfg.clk_rst_vif.cbn); + if (intr_cnter_per_class[class_i] >= timeout_cyc) begin + predict_esc(class_i); + if (cfg.en_cov) cov.intr_timeout_cnt_cg.sample(class_i, timeout_cyc); + end + intr_cnter_per_class[class_i] += 1; + `uvm_info(`gfn, $sformatf("counter_%0d value: %0d", class_i, + intr_cnter_per_class[class_i]), UVM_HIGH) + end + end + intr_cnter_per_class[class_i] = 0; + end + end + begin + wait(under_esc_classes[class_i]); + end + join_any + disable fork; + end // end forever + end + join_none + end + endtask + + // two counters for phases cycle length and esc signals cycle length + // phase cycle cnter: "intr_cnter_per_class" is used to check "esc_cnt" registers + virtual task esc_phase_signal_cnter(); + for (int i = 0; i < NUM_ALERT_CLASSES; i++) begin + fork + automatic int class_i = i; + begin : esc_phases_counter + forever @(!cfg.under_reset && under_esc_classes[class_i]) begin + fork + begin : inc_esc_cnt + for (int phase_i = 0; phase_i < NUM_ESC_PHASES; phase_i++) begin + int phase_thresh = `gmv(reg_esc_phase_cycs_per_class_q[class_i][phase_i]); + bit[TL_DW-1:0] class_ctrl = get_class_ctrl(class_i); + int enabled_sig_q[$]; + for (int sig_i = 0; sig_i < NUM_ESC_SIGNALS; sig_i++) begin + if (class_ctrl[sig_i*2+7 -: 2] == phase_i && class_ctrl[sig_i+2]) begin + enabled_sig_q.push_back(sig_i); + end + end + if (under_esc_classes[class_i]) begin + intr_cnter_per_class[class_i] = 1; + state_per_class[class_i] = esc_state_e'(phase_i + int'(EscStatePhase0)); + cfg.clk_rst_vif.wait_n_clks(1); + while (under_esc_classes[class_i] && + intr_cnter_per_class[class_i] < phase_thresh) begin + intr_cnter_per_class[class_i]++; + cfg.clk_rst_vif.wait_n_clks(1); + end + foreach (enabled_sig_q[i]) begin + int index = enabled_sig_q[i]; + if (esc_sig_class[index] == (class_i + 1)) esc_signal_release[index] = 1; + end + end + end // end four phases + intr_cnter_per_class[class_i] = 0; + if (under_esc_classes[class_i]) state_per_class[class_i] = EscStateTerminal; + end + begin + wait(cfg.under_reset || !under_esc_classes[class_i]); + if (!under_esc_classes[class_i]) begin + // wait 1 clk cycles until esc_signal_release is set + cfg.clk_rst_vif.wait_clks(1); + end + end + join_any + disable fork; + intr_cnter_per_class[class_i] = 0; + end // end forever + end + join_none + end + endtask + + // release escalation signal after one clock cycle, to ensure happens at the end of the clock + // cycle, waited 1 clks here + virtual task release_esc_signal(); + for (int i = 0; i < NUM_ESC_SIGNALS; i++) begin + fork + automatic int sig_i = i; + forever @ (esc_signal_release[sig_i]) begin + cfg.clk_rst_vif.wait_clks(1); + esc_sig_class[sig_i] = 0; + esc_signal_release[sig_i] = 0; + end + join_none + end + endtask + + virtual function void reset(string kind = "HARD"); + super.reset(kind); + under_intr_classes = '{default:0}; + intr_cnter_per_class = '{default:0}; + under_esc_classes = '{default:0}; + esc_sig_class = '{default:0}; + accum_cnter_per_class = '{default:0}; + state_per_class = '{default:EscStateIdle}; + clr_esc_under_intr = 0; + crashdump_triggered = 0; + ping_timer_en = 0; + last_triggered_alert_per_class = '{default:$realtime}; + endfunction + + // clear accumulative counters, and escalation counters if they are under escalation + // interrupt timeout counters cannot be cleared by this + task clr_reset_esc_class(int i); + fork + automatic int class_i = i; + begin + cfg.clk_rst_vif.wait_clks(1); + crashdump_triggered[class_i] = 0; + if (under_intr_classes[class_i]) begin + if (cfg.en_cov) cov.clear_intr_cnt_cg.sample(class_i); + clr_esc_under_intr[class_i] = 1; + end + if (under_esc_classes [class_i]) begin + if (cfg.en_cov) cov.clear_esc_cnt_cg.sample(class_i); + intr_cnter_per_class[class_i] = 0; + end + under_esc_classes[class_i] = 0; + cfg.clk_rst_vif.wait_n_clks(1); + last_triggered_alert_per_class[class_i] = $realtime; + accum_cnter_per_class[class_i] = 0; + if (state_per_class[class_i] != EscStateTimeout) state_per_class[class_i] = EscStateIdle; + end + join_none + endtask + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + endfunction + + // get class_ctrl register mirrored value by class + function bit [TL_DW-1:0] get_class_ctrl(int class_i); + uvm_reg class_ctrl_rg; + class_ctrl_rg = ral.get_reg_by_name($sformatf("class%s_ctrl_shadowed", class_name[class_i])); + `DV_CHECK_NE_FATAL(class_ctrl_rg, null) + return class_ctrl_rg.get_mirrored_value(); + endfunction + + // get class_accum_thresh register mirrored value by class + function bit [TL_DW-1:0] get_class_accum_thresh(int class_i); + uvm_reg class_thresh_rg; + class_thresh_rg = ral.get_reg_by_name($sformatf("class%s_accum_thresh_shadowed", + class_name[class_i])); + `DV_CHECK_NE_FATAL(class_thresh_rg, null) + return class_thresh_rg.get_mirrored_value(); + endfunction + + // get class_timeout_cyc register mirrored value by class + function bit [TL_DW-1:0] get_class_timeout_cyc(int class_i); + dv_base_reg class_timeout_rg = + ral.get_dv_base_reg_by_name($sformatf("class%s_timeout_cyc_shadowed", + class_name[class_i])); + return class_timeout_rg.get_mirrored_value(); + endfunction + + function bit shadowed_reg_wr_completed(dv_base_reg dv_base_reg); + return (!dv_base_reg.is_staged() && !dv_base_reg.get_shadow_update_err()); + endfunction + +endclass +`undef ASSIGN_CLASS_PHASE_REGS diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_virtual_sequencer.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_virtual_sequencer.sv new file mode 100644 index 00000000000..431f2a660cd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/alert_handler_virtual_sequencer.sv @@ -0,0 +1,16 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(alert_handler_env_cfg), + .COV_T(alert_handler_env_cov) + ); + alert_esc_sequencer alert_host_seqr_h[]; + alert_esc_sequencer esc_device_seqr_h[]; + + `uvm_component_utils(alert_handler_virtual_sequencer) + + `uvm_component_new + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_alert_accum_saturation_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_alert_accum_saturation_vseq.sv new file mode 100644 index 00000000000..7420b13e353 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_alert_accum_saturation_vseq.sv @@ -0,0 +1,108 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This sequence force the alert accumulation count to large value, then check if the accum count +// will saturate and won't overflow. + +`define CLASS_CNT_PATH(class_i, i) \ + string class_``class_i``_path_0 = \ + "tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[0]"; \ + string class_``class_i``_path_1 = \ + "tb.dut.gen_classes[``i``].u_accu.u_prim_count.cnt_q[1]"; + +`define CHECK_ALERT_ACCUM_CNT(class_i, i) \ + csr_rd_check(.ptr(ral.class``class_i``_accum_cnt), \ + .compare_value(saturated_class == ``i`` ? \ + MAX_ACCUM_CNT : MAX_ACCUM_CNT - num_alerts_to_saturate)); + +class alert_handler_alert_accum_saturation_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_alert_accum_saturation_vseq) + + `uvm_object_new + + parameter uint MAX_ACCUM_CNT = 'hffff; + rand int num_alerts_to_saturate; + rand bit [1:0] saturated_class; // only 4 classes: a, b, c, d + + `CLASS_CNT_PATH(a, 0) + `CLASS_CNT_PATH(b, 1) + `CLASS_CNT_PATH(c, 2) + `CLASS_CNT_PATH(d, 3) + + constraint num_alerts_to_saturate_c { + num_alerts_to_saturate inside {[1 : 10]}; + $countones(alert_trigger) == 1; + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + this.enable_classa_only_c.constraint_mode(0); + endfunction + + virtual task pre_start(); + // Force accum counts to a large value. + `DV_CHECK(uvm_hdl_force(class_a_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate))); + `DV_CHECK(uvm_hdl_force(class_a_path_1, (num_alerts_to_saturate))); + + `DV_CHECK(uvm_hdl_force(class_b_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate))); + `DV_CHECK(uvm_hdl_force(class_b_path_1, (num_alerts_to_saturate))); + + `DV_CHECK(uvm_hdl_force(class_c_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate))); + `DV_CHECK(uvm_hdl_force(class_c_path_1, (num_alerts_to_saturate))); + + `DV_CHECK(uvm_hdl_force(class_d_path_0, (MAX_ACCUM_CNT - num_alerts_to_saturate))); + `DV_CHECK(uvm_hdl_force(class_d_path_1, (num_alerts_to_saturate))); + + super.pre_start(); + endtask + + virtual task body(); + // Assign all alerts to one class. + foreach (alert_class_map[i]) alert_class_map[i] = saturated_class; + alert_handler_init(.intr_en('1), + .alert_en('1), + .alert_class(alert_class_map), + .loc_alert_en(0), + .loc_alert_class(0)); + csr_wr(ral.classa_accum_thresh_shadowed, '1); + csr_wr(ral.classb_accum_thresh_shadowed, '1); + csr_wr(ral.classc_accum_thresh_shadowed, '1); + csr_wr(ral.classd_accum_thresh_shadowed, '1); + + // Enable and lock all alert classes. + csr_wr(ral.classa_ctrl_shadowed.en, 1); + csr_wr(ral.classb_ctrl_shadowed.en, 1); + csr_wr(ral.classc_ctrl_shadowed.en, 1); + csr_wr(ral.classd_ctrl_shadowed.en, 1); + + `DV_CHECK(uvm_hdl_release(class_a_path_0)); + `DV_CHECK(uvm_hdl_release(class_a_path_1)); + `DV_CHECK(uvm_hdl_release(class_b_path_0)); + `DV_CHECK(uvm_hdl_release(class_b_path_1)); + `DV_CHECK(uvm_hdl_release(class_c_path_0)); + `DV_CHECK(uvm_hdl_release(class_c_path_1)); + `DV_CHECK(uvm_hdl_release(class_d_path_0)); + `DV_CHECK(uvm_hdl_release(class_d_path_1)); + + `uvm_info(`gfn, $sformatf("Saturate class %0d, alerts to saturate %0d", saturated_class, + num_alerts_to_saturate), UVM_LOW) + + // First round will reach the max count value, afterwards check if the max value saturates and + // won't overflow. + repeat ($urandom_range(2, 5)) begin + repeat (num_alerts_to_saturate) begin + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(alert_trigger) + drive_alert(alert_trigger, alert_int_err); + csr_rd_check(.ptr(ral.intr_state), .compare_value(1 << saturated_class)); + csr_wr(.ptr(ral.intr_state), .value(1 << saturated_class)); + end + + `CHECK_ALERT_ACCUM_CNT(a, 0) + `CHECK_ALERT_ACCUM_CNT(b, 1) + `CHECK_ALERT_ACCUM_CNT(c, 2) + `CHECK_ALERT_ACCUM_CNT(d, 3) + end + endtask + +endclass : alert_handler_alert_accum_saturation_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv new file mode 100644 index 00000000000..58f6f549f3e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_base_vseq.sv @@ -0,0 +1,353 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`define RAND_AND_WR_CLASS_PHASES_CYCLE(i) \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase0_cyc_shadowed, \ + class``i``_phase0_cyc_shadowed.value inside {[0: max_phase_cyc]};); \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase1_cyc_shadowed, \ + class``i``_phase1_cyc_shadowed.value inside {[0: max_phase_cyc]};); \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase2_cyc_shadowed, \ + class``i``_phase2_cyc_shadowed.value inside {[0: max_phase_cyc]};); \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_phase3_cyc_shadowed, \ + class``i``_phase3_cyc_shadowed.value inside {[0: max_phase_cyc]};); \ + csr_update(ral.class``i``_phase0_cyc_shadowed); \ + csr_update(ral.class``i``_phase1_cyc_shadowed); \ + csr_update(ral.class``i``_phase2_cyc_shadowed); \ + csr_update(ral.class``i``_phase3_cyc_shadowed); + +`define RAND_WRITE_CLASS_CTRL(i, en_bit, lock_bit) \ + `DV_CHECK_RANDOMIZE_WITH_FATAL(ral.class``i``_ctrl_shadowed, \ + en.value == en_bit; lock.value == lock_bit;) \ + csr_wr(.ptr(ral.class``i``_ctrl_shadowed), .value(ral.class``i``_ctrl_shadowed.get())); + +class alert_handler_base_vseq extends cip_base_vseq #( + .CFG_T (alert_handler_env_cfg), + .RAL_T (alert_handler_reg_block), + .COV_T (alert_handler_env_cov), + .VIRTUAL_SEQUENCER_T (alert_handler_virtual_sequencer) + ); + `uvm_object_utils(alert_handler_base_vseq) + + // various knobs to enable certain routines + bit do_alert_handler_init = 1'b0; + bit config_locked = 1'b0; + + `uvm_object_new + + virtual task dut_init(string reset_kind = "HARD"); + cfg.alert_handler_vif.init(); + super.dut_init(); + if (do_alert_handler_init) alert_handler_init(); + config_locked = 0; + endtask + + virtual task dut_shutdown(); + // nothing special yet + endtask + + // setup basic alert_handler features + // alert_class default 0 -> all alert will trigger interrupt classA + virtual task alert_handler_init( + bit [NUM_ALERT_CLASSES-1:0] intr_en = '1, + bit [NUM_ALERTS-1:0] alert_en = '1, + bit [NUM_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] alert_class = 'h0, + bit [NUM_LOCAL_ALERTS-1:0] loc_alert_en = '1, + bit [NUM_LOCAL_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] loc_alert_class = 'h0); + + csr_wr(.ptr(ral.intr_enable), .value(intr_en)); + foreach (alert_en[i]) csr_wr(.ptr(ral.alert_en_shadowed[i]), + .value(alert_en[i])); + foreach (alert_class[i]) csr_wr(.ptr(ral.alert_class_shadowed[i]), + .value(alert_class[i])); + foreach (loc_alert_en[i]) csr_wr(.ptr(ral.loc_alert_en_shadowed[i]), + .value(loc_alert_en[i])); + foreach (loc_alert_class[i]) csr_wr(.ptr(ral.loc_alert_class_shadowed[i]), + .value(loc_alert_class[i])); + endtask + + virtual task alert_handler_rand_wr_class_ctrl(bit [NUM_ALERT_CLASSES-1:0] lock_bit, + bit [NUM_ALERT_CLASSES-1:0] class_en); + `RAND_WRITE_CLASS_CTRL(a, class_en[0], lock_bit[0]) + `RAND_WRITE_CLASS_CTRL(b, class_en[1], lock_bit[1]) + `RAND_WRITE_CLASS_CTRL(c, class_en[2], lock_bit[2]) + `RAND_WRITE_CLASS_CTRL(d, class_en[3], lock_bit[3]) + endtask + + virtual task alert_handler_wr_regwen_regs(bit [NUM_ALERT_CLASSES-1:0] regwen = 0, + bit [NUM_ALERTS-1:0] alert_regwen = 0, + bit [NUM_LOCAL_ALERTS-1:0] loc_alert_regwen = 0, + bit ping_timer_regwen = 0, + bit [NUM_ALERT_CLASSES-1:0] class_regwen = 0); + + csr_wr(.ptr(ral.classa_clr_regwen), .value(regwen[0])); + csr_wr(.ptr(ral.classb_clr_regwen), .value(regwen[1])); + csr_wr(.ptr(ral.classc_clr_regwen), .value(regwen[2])); + csr_wr(.ptr(ral.classd_clr_regwen), .value(regwen[3])); + + foreach (alert_regwen[i]) csr_wr(.ptr(ral.alert_regwen[i]), .value(alert_regwen[i])); + + foreach (loc_alert_regwen[i]) begin + csr_wr(.ptr(ral.loc_alert_regwen[i]), .value(loc_alert_regwen[i])); + end + + csr_wr(.ptr(ral.ping_timer_regwen), .value(ping_timer_regwen)); + + csr_wr(.ptr(ral.classa_regwen), .value(class_regwen[0])); + csr_wr(.ptr(ral.classb_regwen), .value(class_regwen[1])); + csr_wr(.ptr(ral.classc_regwen), .value(class_regwen[2])); + csr_wr(.ptr(ral.classd_regwen), .value(class_regwen[3])); + endtask + + // If do_lock_config is set, write value 1 to ping_timer_en register. + // If not set, this task has 50% of chance to write value 1 to ping_timer_en register. + virtual task lock_config(bit do_lock_config); + if (do_lock_config || $urandom_range(0, 1)) begin + csr_wr(.ptr(ral.ping_timer_en_shadowed), .value(do_lock_config)); + end + endtask + + virtual task drive_alert(bit[NUM_ALERTS-1:0] alert_trigger, bit[NUM_ALERTS-1:0] alert_int_err); + fork + begin : isolation_fork + foreach (alert_trigger[i]) begin + if (alert_trigger[i]) begin + automatic int index = i; + fork + begin + alert_sender_seq alert_seq; + `uvm_create_on(alert_seq, p_sequencer.alert_host_seqr_h[index]); + `DV_CHECK_RANDOMIZE_WITH_FATAL(alert_seq, int_err == alert_int_err[index];) + `uvm_send(alert_seq) + end + join_none + end + end + wait fork; + end + join + endtask + + // This sequence will drive standalone esc_resp_p/n without esc_p/n + virtual task drive_esc_rsp(bit [NUM_ESCS-1:0] esc_int_errs); + fork + begin : isolation_fork + foreach (cfg.esc_device_cfg[i]) begin + automatic int index = i; + if (esc_int_errs[index]) begin + fork + begin + esc_receiver_esc_rsp_seq esc_seq = + esc_receiver_esc_rsp_seq::type_id::create("esc_seq"); + `DV_CHECK_RANDOMIZE_WITH_FATAL(esc_seq, int_err == 1; standalone_int_err == 1; + ping_timeout == 0;) + esc_seq.start(p_sequencer.esc_device_seqr_h[index]); + end + join_none + end + end + wait fork; + end + join + endtask + + // alert_handler scb will compare the read value with expected value + // Not using "clear_all_interrupts" function in cip_base_vseq because of the signal interity + // error: after clearing intr_state, intr_state might come back to 1 in the next cycle. + virtual task check_alert_interrupts(); + bit [TL_DW-1:0] intr; + // Wait until there is no ping handshake. + // This will avoid the case where interrupt is set and cleared at the same cycle. + `DV_WAIT((cfg.alert_handler_vif.alert_ping_reqs || cfg.alert_handler_vif.esc_ping_reqs) == 0) + csr_rd(.ptr(ral.intr_state), .value(intr)); + `DV_WAIT((cfg.alert_handler_vif.alert_ping_reqs || cfg.alert_handler_vif.esc_ping_reqs) == 0) + csr_wr(.ptr(ral.intr_state), .value('1)); + endtask + + virtual task clear_esc(); + csr_wr(.ptr(ral.classa_clr_shadowed), .value(1)); + csr_wr(.ptr(ral.classb_clr_shadowed), .value(1)); + csr_wr(.ptr(ral.classc_clr_shadowed), .value(1)); + csr_wr(.ptr(ral.classd_clr_shadowed), .value(1)); + endtask + + // checking for csr_rd is done in scb + virtual task read_alert_cause(); + bit [TL_DW-1:0] alert_cause; + foreach (ral.alert_cause[i]) begin + if ($urandom_range(0, 1)) begin + csr_rd(.ptr(ral.alert_cause[i]), .value(alert_cause)); + end + end + foreach (ral.loc_alert_cause[i]) begin + if ($urandom_range(0, 1)) begin + csr_rd(.ptr(ral.loc_alert_cause[i]), .value(alert_cause)); + end + end + endtask + + virtual task read_esc_status(); + bit [TL_DW-1:0] csr_val; + csr_rd(.ptr(ral.classa_accum_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classb_accum_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classc_accum_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classd_accum_cnt), .value(csr_val)); + + csr_rd(.ptr(ral.classa_state), .value(csr_val)); + csr_rd(.ptr(ral.classb_state), .value(csr_val)); + csr_rd(.ptr(ral.classc_state), .value(csr_val)); + csr_rd(.ptr(ral.classd_state), .value(csr_val)); + + csr_rd(.ptr(ral.classa_esc_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classb_esc_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classc_esc_cnt), .value(csr_val)); + csr_rd(.ptr(ral.classd_esc_cnt), .value(csr_val)); + endtask + + virtual task wait_alert_handshake_done(); + cfg.clk_rst_vif.wait_clks(2); + foreach (cfg.alert_host_cfg[i]) begin + if (!cfg.alert_host_cfg[i].en_alert_lpg) cfg.alert_host_cfg[i].vif.wait_ack_complete(); + end + endtask + + virtual function bit check_esc_done(bit[TL_DW-1:0] vals[$]); + foreach (vals[i]) begin + esc_state_e val = esc_state_e'(vals[i]); + if (val inside {EscStatePhase0, EscStatePhase1, EscStatePhase2, EscStatePhase3}) return 0; + end + return 1; + endfunction + + virtual task wait_esc_handshake_done(); + bit [TL_DW-1:0] csr_vals[4]; + do begin + csr_rd(.ptr(ral.classa_state), .value(csr_vals[0])); + csr_rd(.ptr(ral.classb_state), .value(csr_vals[1])); + csr_rd(.ptr(ral.classc_state), .value(csr_vals[2])); + csr_rd(.ptr(ral.classd_state), .value(csr_vals[3])); + end while (!check_esc_done(csr_vals)); + // check if there is any esc ping + foreach (cfg.esc_device_cfg[i]) cfg.esc_device_cfg[i].vif.wait_esc_complete(); + endtask + + // This task wait until any alert or esc protocol received a ping from LFSR. + // This task will also return the protocol index: + // alert index starts from 1; esc index stats from NUM_ALERTS + virtual task wait_alert_esc_ping(ref int ping_index); + int ping_i; + fork + begin : isolation_fork + foreach (cfg.alert_host_cfg[i]) begin + automatic int index = i; + fork + begin + cfg.alert_host_cfg[index].vif.wait_alert_ping(); + ping_i = index + 1; + end + join_none + end + foreach (cfg.esc_device_cfg[i]) begin + automatic int index = i; + fork + begin + cfg.esc_device_cfg[index].vif.wait_esc_ping(); + ping_i = index + NUM_ALERTS + 1; + end + join_none + end + wait (ping_i > 0); + disable fork; + ping_index = ping_i; + end + join + endtask + + function void enable_lpg_group(bit [NUM_ALERTS-1:0] alert_en_i); + foreach (alert_en_i[i]) begin + if (alert_en_i[i]) set_alert_lpg(i); + end + endfunction + + // Enable alert's LPG based on alert_i input. + // + // Only enable this alert's LPG if the lgp input `lpg_cg_en` or `lpg_rst_en` if not Mubi4True. + // Because one LPG will turn off a set of alert sensers. So this task will also set all LPG's + // alert_host_cfgs' `en_alert_lpg` to 1. + virtual function void set_alert_lpg(int alert_i); + int lpg_i = alert_handler_reg_pkg::LpgMap[alert_i]; + bit [1:0] set_lpg; + + if (cfg.alert_handler_vif.get_lpg_status(lpg_i) == 0) begin + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(set_lpg, set_lpg > 0;); + if (set_lpg[0]) cfg.alert_handler_vif.set_lpg_cg_en(lpg_i); + if (set_lpg[1]) cfg.alert_handler_vif.set_lpg_rst_en(lpg_i); + foreach (alert_handler_reg_pkg::LpgMap[i]) begin + if (alert_handler_reg_pkg::LpgMap[i] == lpg_i) cfg.alert_host_cfg[i].en_alert_lpg = 1; + end + end + endfunction + + virtual task alert_handler_crashdump_phases(bit [1:0] classa_phase = $urandom(), + bit [1:0] classb_phase = $urandom(), + bit [1:0] classc_phase = $urandom(), + bit [1:0] classd_phase = $urandom()); + csr_wr(.ptr(ral.classa_crashdump_trigger_shadowed), .value(classa_phase)); + csr_wr(.ptr(ral.classb_crashdump_trigger_shadowed), .value(classb_phase)); + csr_wr(.ptr(ral.classc_crashdump_trigger_shadowed), .value(classc_phase)); + csr_wr(.ptr(ral.classd_crashdump_trigger_shadowed), .value(classd_phase)); + endtask + + virtual task wr_phases_cycle(int max_phase_cyc); + `RAND_AND_WR_CLASS_PHASES_CYCLE(a); + `RAND_AND_WR_CLASS_PHASES_CYCLE(b); + `RAND_AND_WR_CLASS_PHASES_CYCLE(c); + `RAND_AND_WR_CLASS_PHASES_CYCLE(d); + endtask + + virtual task wr_intr_timeout_cycle(bit[TL_DW-1:0] intr_timeout_cyc[NUM_ALERT_CLASSES]); + csr_wr(.ptr(ral.classa_timeout_cyc_shadowed), .value(intr_timeout_cyc[0])); + csr_wr(.ptr(ral.classb_timeout_cyc_shadowed), .value(intr_timeout_cyc[1])); + csr_wr(.ptr(ral.classc_timeout_cyc_shadowed), .value(intr_timeout_cyc[2])); + csr_wr(.ptr(ral.classd_timeout_cyc_shadowed), .value(intr_timeout_cyc[3])); + endtask + + virtual task wr_class_accum_threshold(bit[TL_DW-1:0] accum_thresh[NUM_ALERT_CLASSES]); + csr_wr(.ptr(ral.classa_accum_thresh_shadowed), .value(accum_thresh[0])); + csr_wr(.ptr(ral.classb_accum_thresh_shadowed), .value(accum_thresh[1])); + csr_wr(.ptr(ral.classc_accum_thresh_shadowed), .value(accum_thresh[2])); + csr_wr(.ptr(ral.classd_accum_thresh_shadowed), .value(accum_thresh[3])); + endtask + + virtual task wr_ping_timeout_cycle(bit[TL_DW-1:0] timeout_val); + csr_wr(.ptr(ral.ping_timeout_cyc_shadowed), .value(timeout_val)); + if (`gmv(ral.ping_timer_regwen)) begin + if (timeout_val == 0) timeout_val = 1; + foreach (cfg.alert_host_cfg[i]) cfg.alert_host_cfg[i].ping_timeout_cycle = timeout_val; + foreach (cfg.esc_device_cfg[i]) cfg.esc_device_cfg[i].ping_timeout_cycle = timeout_val; + end + endtask + + // This sequence will automatically response to all escalation ping and esc responses + virtual task run_esc_rsp_seq_nonblocking(bit [NUM_ESCS-1:0] esc_int_errs = '0, + bit [NUM_ESCS-1:0] ping_timeout_errs = '0); + foreach (cfg.esc_device_cfg[i]) begin + automatic int index = i; + fork + forever begin + bit esc_int_err = esc_int_errs[index] ? $urandom_range(0, 1) : 0; + bit ping_timeout_err = ping_timeout_errs[index] ? $urandom_range(0, 1) : 0; + esc_receiver_esc_rsp_seq esc_seq = + esc_receiver_esc_rsp_seq::type_id::create("esc_seq"); + `DV_CHECK_RANDOMIZE_WITH_FATAL(esc_seq, int_err == esc_int_err; standalone_int_err == 0; + ping_timeout == ping_timeout_err;) + esc_seq.start(p_sequencer.esc_device_seqr_h[index]); + end + join_none + end + endtask + +endclass : alert_handler_base_vseq + +`undef RAND_AND_WR_CLASS_PHASES_CYCLE +`undef RAND_WRITE_CLASS_CTRL diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv new file mode 100644 index 00000000000..fc76795637a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_common_vseq.sv @@ -0,0 +1,172 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_common_vseq extends alert_handler_base_vseq; + `uvm_object_utils(alert_handler_common_vseq) + + constraint num_trans_c { + num_trans inside {[1:2]}; + } + + `uvm_object_new + + virtual task pre_start(); + super.pre_start(); + if (common_seq_type == "tl_intg_err") begin + // If `en_csr_vseq_w_tl_intg = 1`, this vseq will check tl intg error won't affect any other + // tl transaction. + // If `en_csr_vseq_w_tl_intg = 0`, this vseq will check status, interrupts, and class_count + // registers are updated correctly by DUT. + en_csr_vseq_w_tl_intg = $urandom_range(0, 1); + `uvm_info(`gfn, $sformatf("en_csr_vseq_w_tl_intg = %0b", en_csr_vseq_w_tl_intg), UVM_MEDIUM) + end + endtask + + virtual task body(); + // run alert/esc ping response sequences without error or timeout to prevent triggering local + // alert failure + run_esc_rsp_seq_nonblocking(0); + run_common_vseq_wrapper(num_trans); + endtask : body + + // If the tl_intg_err sequence does not run csr_rw in parallel, enable loc_alert error and enable + // interrupts. + // If the tl_intg_err sequence runs with csr_rw, do not enable loc_alert because it might trigger + // escalation and affect register predications. + virtual task run_tl_intg_err_vseq_sub(string ral_name); + if (en_csr_vseq_w_tl_intg == 0) begin + csr_wr(.ptr(ral.loc_alert_en_shadowed[LocalBusIntgFail]), + .value($urandom_range(0, 1)), + .predict(1)); + csr_wr(.ptr(ral.loc_alert_class_shadowed[LocalBusIntgFail]), + .value($urandom_range(0, 3)), + .predict(1)); + csr_wr(.ptr(ral.classa_ctrl_shadowed.en), .value(1)); + csr_wr(.ptr(ral.classb_ctrl_shadowed.en), .value(1)); + csr_wr(.ptr(ral.classc_ctrl_shadowed.en), .value(1)); + csr_wr(.ptr(ral.classd_ctrl_shadowed.en), .value(1)); + end + super.run_tl_intg_err_vseq_sub(ral_name); + endtask + + // Override the task to check corresponding CSR status is updated correctly. + virtual task check_tl_intg_error_response(); + bit exp_val = `gmv(ral.loc_alert_en_shadowed[LocalBusIntgFail]); + csr_rd_check(.ptr(ral.loc_alert_cause[LocalBusIntgFail]), .compare_value(exp_val)); + + // Only check interrupt, accumlate count, and alert_cause registers if the local alert is + // enabled. + // However, this task does not check escalation port because the common escalation path is + // checked in other tests that enabled scb. + if (exp_val == 1) begin + bit [TL_DW-1:0] class_i = `gmv(ral.loc_alert_class_shadowed[LocalBusIntgFail]); + bit [TL_DW-1:0] accum_cnt; + csr_rd_check(.ptr(ral.intr_state), .compare_value(1'b1 << class_i)); + case (class_i) + 0: csr_rd(.ptr(ral.classa_accum_cnt), .value(accum_cnt)); + 1: csr_rd(.ptr(ral.classb_accum_cnt), .value(accum_cnt)); + 2: csr_rd(.ptr(ral.classc_accum_cnt), .value(accum_cnt)); + 3: csr_rd(.ptr(ral.classd_accum_cnt), .value(accum_cnt)); + default: `uvm_fatal(`gfn, $sformatf("Invalid class index %0d", class_i)) + endcase + // Once tl_intg_err triggered, the error will be set to 1 until reset, so the counter will + // continuously increment. + `DV_CHECK_LT(0, accum_cnt, "Accumulated count should be larger than 0"); + end + endtask + + // If the common sequence is tl integrity error sequence, we override this task to disable local + // alert for tl_intg_err and lock this register. Because tl_intg_err can trigger local alert and + // eventually triggers escalation. Then the auto predications for escalation related registers + // such as `class_clr` and `clr_regwen` registers are not correct. + virtual task run_csr_vseq(string csr_test_type, + int num_test_csrs = 0, + bit do_rand_wr_and_reset = 1, + dv_base_reg_block models[$] = {}, + string ral_name = ""); + if (common_seq_type == "tl_intg_err") begin + csr_wr(.ptr(ral.loc_alert_regwen[LocalBusIntgFail]), .value(0), .predict(1)); + end + super.run_csr_vseq(csr_test_type, num_test_csrs, do_rand_wr_and_reset, models, ral_name); + endtask + + virtual function void predict_shadow_reg_status(bit predict_update_err = 0, + bit predict_storage_err = 0); + if (predict_update_err) begin + foreach (cfg.shadow_update_err_status_fields[status_field]) begin + if (`gmv(ral.loc_alert_en_shadowed[LocalShadowRegUpdateErr])) begin + void'(status_field.predict(cfg.shadow_update_err_status_fields[status_field])); + end + end + end + if (predict_storage_err) begin + foreach (cfg.shadow_storage_err_status_fields[status_field]) begin + if (`gmv(ral.loc_alert_en_shadowed[LocalShadowRegStorageErr])) begin + void'(status_field.predict(cfg.shadow_storage_err_status_fields[status_field])); + end + end + end + endfunction + + virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy); + if (!uvm_re_match("tb.dut.u_ping_timer.*", if_proxy.path)) begin + bit val; + csr_rd(.ptr(ral.loc_alert_cause[LocalAlertPingFail]), .value(val)); + `DV_CHECK_EQ(val, 1, "local alert ping fail mismatch") + csr_rd(.ptr(ral.loc_alert_cause[LocalEscPingFail]), .value(val)); + `DV_CHECK_EQ(val, 1, "local escalation ping fail mismatch") + end else begin + foreach (cfg.esc_device_cfg[i]) begin + `DV_CHECK_EQ(cfg.esc_device_cfg[i].vif.esc_tx.esc_p, 1, + $sformatf("escalation protocol_%0d is not set", i)); + end + end + // Let the simulation wait a few clock cycles before reset to make sure assertions are checked. + cfg.clk_rst_vif.wait_clks($urandom_range(2, 10)); + endtask + + virtual task sec_cm_inject_fault(sec_cm_base_if_proxy if_proxy); + if (!uvm_re_match("tb.dut.u_ping_timer.*", if_proxy.path)) begin + // Enable ping timer to get ping counter error + csr_wr(ral.ping_timer_en_shadowed, 1); + + // Enable loc_alerts + foreach (ral.loc_alert_en_shadowed[i]) csr_wr(ral.loc_alert_en_shadowed[i], 1); + end + super.sec_cm_inject_fault(if_proxy); + endtask : sec_cm_inject_fault + + virtual task pre_run_sec_cm_fi_vseq(); + // Disable prim_sparse_fsm assertions. + $assertoff(0, "tb.dut.gen_classes[0].u_esc_timer.CheckEn_A"); + $assertoff(0, "tb.dut.gen_classes[1].u_esc_timer.CheckEn_A"); + $assertoff(0, "tb.dut.gen_classes[2].u_esc_timer.CheckEn_A"); + $assertoff(0, "tb.dut.gen_classes[3].u_esc_timer.CheckEn_A"); + + // Disable the EscStateOut_A assertion while we do FI checks. This assertion checks that an FSM + // state matches an output signal, but this can totally fail to be true if we're forcing either + // side. + $assertoff(0, "tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A"); + + // Because the assertion contains `=>` statement. + // Wait one clock cycle until the assertions are fully disabled. + cfg.clk_rst_vif.wait_clks(1); + endtask : pre_run_sec_cm_fi_vseq + + virtual task post_run_sec_cm_fi_vseq(); + // Enable all the assertions that pre_run_sec_cm_fi_vseq disabled + $asserton(0, "tb.dut.gen_classes[0].u_esc_timer.CheckEn_A"); + $asserton(0, "tb.dut.gen_classes[1].u_esc_timer.CheckEn_A"); + $asserton(0, "tb.dut.gen_classes[2].u_esc_timer.CheckEn_A"); + $asserton(0, "tb.dut.gen_classes[3].u_esc_timer.CheckEn_A"); + $assertoff(0, "tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A"); + $assertoff(0, "tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A"); + endtask : post_run_sec_cm_fi_vseq + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv new file mode 100644 index 00000000000..b36e43178b8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_stress_vseq.sv @@ -0,0 +1,103 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This sequence uses a fixed setting to enable all alerts and locks them to class A. +// Then enable all local alerts and locks them to class B. +// Randomly force the `wait_cyc_mask_i` from design to a valid small number to fasten the ping +// request mechanism. +// Finally this sequence wait until alerts are pinged certain times. +class alert_handler_entropy_stress_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_entropy_stress_vseq) + + `uvm_object_new + + rand bit [7:0] forced_mask_val; + rand int num_pings; + + constraint valid_mask_val_c { + forced_mask_val >= 'h7; + $onehot(32'(forced_mask_val) + 1) == 1; + } + + constraint num_pings_c { + if (forced_mask_val > 'hf0) { + num_pings inside {[1 : 2]}; + } else { + num_pings inside {[1 : 3]}; + } + } + + virtual task pre_start(); + `DV_CHECK_RANDOMIZE_FATAL(this) + cfg.alert_handler_vif.set_wait_cyc_mask(forced_mask_val); + + foreach (cfg.alert_host_cfg[i]) begin + cfg.alert_host_cfg[i].alert_delay_max = 0; + cfg.alert_host_cfg[i].ping_delay_max = 0; + end + super.pre_start(); + endtask + + task body(); + bit [NUM_LOCAL_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] loc_alert_class; + + foreach (loc_alert_class[i]) loc_alert_class[i] = 1; + + `uvm_info(`gfn, "Test started", UVM_LOW) + + run_esc_rsp_seq_nonblocking(); + + alert_handler_init(.intr_en('1), // Enable all interrupts + .alert_en('1), // Enable all alerts + .alert_class(0), // Set all alerts to class A + .loc_alert_en('1), // Enable all local alerts + .loc_alert_class(loc_alert_class)); // Set all local alerts to class B + + // Enable all classes and lock them. + alert_handler_rand_wr_class_ctrl('1, '1); + + // Enable ping timer. + csr_wr(.ptr(ral.ping_timer_en_shadowed), .value(1)); + + // Lock alerts and configurations. + alert_handler_wr_regwen_regs(.regwen(0), + .alert_regwen(0), + .loc_alert_regwen(0), + .ping_timer_regwen(0), + .class_regwen(0)); + + // Wait for all alerts to be pinged at least once. + fork begin : isolation_fork + int num_alerts = NUM_ALERTS; + for (int i = 0; i < NUM_ALERTS; i++) begin + automatic int index = i; + fork begin + repeat (num_pings) cfg.alert_host_cfg[index].vif.wait_alert_ping(); + num_alerts--; + `uvm_info(`gfn, $sformatf("alert %0d received %0d ping request.\n %0d alerts remaining.", + index, num_pings, num_alerts), UVM_LOW); + end join_none + end + wait fork; + end join + + cfg.clk_rst_vif.wait_clks($urandom_range(50, 500)); + + // Check no error or local alerts triggered. + foreach (ral.alert_cause[i]) begin + csr_rd_check(.ptr(ral.alert_cause[i]), .compare_value(0)); + end + foreach (ral.loc_alert_cause[i]) begin + csr_rd_check(.ptr(ral.loc_alert_cause[i]), .compare_value(0)); + end + + // Wait some random delays, then release the force signal, issue reset. + // This will allow the test to pass ok_to_end check from alert/esc_monitors and + // push_pull_agent. + cfg.clk_rst_vif.wait_clks($urandom_range(0, 5)); + cfg.alert_handler_vif.release_wait_cyc_mask(); + dut_init(); + endtask + +endclass : alert_handler_entropy_stress_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv new file mode 100644 index 00000000000..11a45e29543 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_entropy_vseq.sv @@ -0,0 +1,41 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence enable entropy by writing 1 to the lock_regen register. + +class alert_handler_entropy_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_entropy_vseq) + + `uvm_object_new + + // large number of num_trans to make sure covers all alerts and escalation pings + constraint num_trans_c { + num_trans inside {[400:1000]}; + } + + // increase the possibility to enable more alerts, because alert_handler only sends ping on + // enabled alerts + constraint enable_one_alert_c { + alert_en dist {'1 :/ 9, [0:('1-1'b1)] :/ 1}; + (~alert_regwen) dist {'1 :/ 9, [0:('1-1'b1)] :/ 1}; + } + + constraint sig_int_c { + esc_int_err == 0; + } + + constraint lock_bit_c { + do_lock_config == 1; + } + + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {accum_thresh[i] dist {[0:1] :/ 5, [2:10] :/ 5};} + } + + function void pre_randomize(); + this.enable_classa_only_c.constraint_mode(0); + verbosity = UVM_HIGH; + endfunction + +endclass : alert_handler_entropy_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_alert_accum_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_alert_accum_vseq.sv new file mode 100644 index 00000000000..612d0389ff6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_alert_accum_vseq.sv @@ -0,0 +1,34 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence triggers escalation by accumulating alerts in the same class. +// difference from smoke test, this sequence set the threshold to larger numbers. + +class alert_handler_esc_alert_accum_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_esc_alert_accum_vseq) + + `uvm_object_new + + constraint disable_clr_esc_c { + do_clr_esc == 0; + } + + constraint enable_alert_accum_esc_only_c { + do_esc_intr_timeout == 0; // disable interrupt timeout triggered escalation + } + + constraint num_trans_c { + num_trans inside {[1:100]}; + } + + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {accum_thresh[i] inside {[0:100]};} + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + this.enable_classa_only_c.constraint_mode(0); + endfunction + +endclass : alert_handler_esc_alert_accum_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_intr_timeout_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_intr_timeout_vseq.sv new file mode 100644 index 00000000000..01df28d4c76 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_esc_intr_timeout_vseq.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence triggers escalation by the interrupt timeout + +class alert_handler_esc_intr_timeout_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_esc_intr_timeout_vseq) + + `uvm_object_new + + constraint esc_due_to_intr_timeout_only_c { + foreach (accum_thresh[i]) {accum_thresh[i] > 1;} // prevent alert accumulation triggers esc + do_esc_intr_timeout == 1; + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + this.enable_classa_only_c.constraint_mode(0); + endfunction + +endclass : alert_handler_esc_intr_timeout_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_stub_clk_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_stub_clk_vseq.sv new file mode 100644 index 00000000000..9abddcf2861 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_stub_clk_vseq.sv @@ -0,0 +1,43 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This sequence check LPG by randomly turn off alert_handler's clock, and check if ping timer can +// resume correctly without sending some spurious ping errors. +class alert_handler_lpg_stub_clk_vseq extends alert_handler_lpg_vseq; + `uvm_object_utils(alert_handler_lpg_stub_clk_vseq) + + `uvm_object_new + + constraint loc_alert_en_c { + local_alert_en[LocalAlertPingFail] == 1; + local_alert_en[LocalEscPingFail] == 1; + } + + constraint ping_fail_c { + alert_ping_timeout == 0; + esc_ping_timeout == 0; + } + + task body(); + fork begin : isolation_fork + trigger_non_blocking_seqs(); + fork + rand_stub_clk(); + run_smoke_seq(); + join + disable fork; // disable non-blocking seqs for stress_all tests + end join + endtask : body + + virtual task rand_stub_clk(); + repeat($urandom_range(1, 5)) begin + int clk_stub_ps = cfg.clk_rst_vif.clk_period_ps * $urandom_range(2, 1_000); + cfg.clk_rst_vif.wait_clks($urandom_range(0, 100_000)); + cfg.clk_rst_vif.stop_clk(); + #((clk_stub_ps)*1ps); + cfg.clk_rst_vif.start_clk(); + end + endtask + +endclass : alert_handler_lpg_stub_clk_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_vseq.sv new file mode 100644 index 00000000000..8444bc88029 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_lpg_vseq.sv @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_lpg_vseq extends alert_handler_entropy_vseq; + `uvm_object_utils(alert_handler_lpg_vseq) + + `uvm_object_new + + constraint sig_int_c { + alert_int_err == 0; + esc_int_err == 0; + esc_standalone_int_err == 0; + } + + constraint loc_alert_en_c { + local_alert_en[LocalAlertPingFail] > 0; + } + + constraint ping_fail_c { + alert_ping_timeout == alert_en; + esc_ping_timeout == 0; + } + + // disable interrupt timeout + constraint esc_intr_timeout_c { + foreach (intr_timeout_cyc[i]) {intr_timeout_cyc[i] == 0;} + } + + function void pre_randomize(); + this.enable_classa_only_c.constraint_mode(0); + this.enable_one_alert_c.constraint_mode(0); + verbosity = UVM_HIGH; + endfunction + + task body(); + fork + begin : isolation_fork + trigger_non_blocking_seqs(); + fork + enable_lpg_group(alert_en); + run_smoke_seq(); + join + disable fork; // disable non-blocking seqs for stress_all tests + end // end isolation_fork + join + endtask : body +endclass : alert_handler_lpg_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv new file mode 100644 index 00000000000..00237f42fed --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_ping_timeout_vseq.sv @@ -0,0 +1,79 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence test corner cases for alert or escalation pings: +// 1). ping integrity fail or timeout +// 2). ping interrupted by a reset signal +// 3). escalation ping interrupted by real escalation signal (this could happen because escalation +// ping and real escalation share the same esc_p/n signals) + +class alert_handler_ping_timeout_vseq extends alert_handler_entropy_vseq; + `uvm_object_utils(alert_handler_ping_timeout_vseq) + + `uvm_object_new + + constraint num_trans_c { + num_trans inside {[5:30]}; + } + + constraint alert_trigger_c { + alert_trigger == 0; + } + + constraint intr_en_c { + intr_en == '1; + } + + constraint sig_int_c { + alert_int_err == 0; + esc_int_err == 0; + esc_standalone_int_err == 0; + } + + constraint loc_alert_en_c { + local_alert_en[LocalEscPingFail] == 1; + local_alert_en[LocalAlertPingFail] == 1; + } + + constraint ping_fail_c { + alert_ping_timeout == '1; + esc_ping_timeout == '1; + } + + // At least enable and lock `NUM_ALERTS-4` alerts to avoid this sequence running too long. + // This constraint also ensures at least one alert is locked and enabled so that we can ensure at + // least one alert ping will fire. + constraint enable_one_alert_c { + $countones(alert_en) dist {NUM_ALERTS :/ 8, [NUM_ALERTS-4 : NUM_ALERTS-1] :/ 2}; + $countones(~alert_regwen) dist {NUM_ALERTS :/ 5, [NUM_ALERTS-4 : NUM_ALERTS-1] :/ 5}; + (~alert_regwen) & alert_en > 0; + } + + constraint ping_timeout_cyc_c { + ping_timeout_cyc inside {[1:MAX_PING_TIMEOUT_CYCLE]}; + } + + // disable interrupt timeout + constraint esc_intr_timeout_c { + foreach (intr_timeout_cyc[i]) {intr_timeout_cyc[i] == 0;} + } + + function void pre_randomize(); + this.enable_classa_only_c.constraint_mode(0); + endfunction + + // In this sequence, because we disable all external alerts, so to ensure local alerts are + // triggerd, we wait for interrupt pins to fire then wait for alert and escalation handshake + // to finish. + virtual task wait_alert_esc_done(); + wait (cfg.intr_vif.pins[NUM_ALERT_CLASSES-1:0]); + // Wait two clock cycles to avoid building a cycle-accurate scb. + cfg.clk_rst_vif.wait_clks(2); + `uvm_info(`gfn, $sformatf("Interrupt pin = %0h", cfg.intr_vif.pins[NUM_ALERT_CLASSES-1:0]), + UVM_LOW) + check_alert_interrupts(); + super.wait_alert_esc_done(); + endtask + +endclass : alert_handler_ping_timeout_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv new file mode 100644 index 00000000000..f8276a1d7ca --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_alerts_vseq.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence enable random alert inputs, and rand wr phase cycles + +class alert_handler_random_alerts_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_random_alerts_vseq) + + `uvm_object_new + + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {accum_thresh[i] dist {[0:1] :/ 5, [2:5] :/ 5};} + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + endfunction + +endclass : alert_handler_random_alerts_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_classes_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_classes_vseq.sv new file mode 100644 index 00000000000..b6d72600062 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_random_classes_vseq.sv @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence enable random classes, and rand wr phase cycles + +class alert_handler_random_classes_vseq extends alert_handler_random_alerts_vseq; + `uvm_object_utils(alert_handler_random_classes_vseq) + + `uvm_object_new + + function void pre_randomize(); + super.pre_randomize(); + this.enable_classa_only_c.constraint_mode(0); + endfunction + +endclass : alert_handler_random_classes_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_sig_int_fail_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_sig_int_fail_vseq.sv new file mode 100644 index 00000000000..5012d457a01 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_sig_int_fail_vseq.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// this sequence enable signal intergrity fail. + +class alert_handler_sig_int_fail_vseq extends alert_handler_smoke_vseq; + `uvm_object_utils(alert_handler_sig_int_fail_vseq) + + `uvm_object_new + + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {accum_thresh[i] dist {[0:1] :/ 5, [2:10] :/ 5};} + } + + function void pre_randomize(); + this.enable_one_alert_c.constraint_mode(0); + this.enable_classa_only_c.constraint_mode(0); + this.sig_int_c.constraint_mode(0); + endfunction + +endclass : alert_handler_sig_int_fail_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv new file mode 100644 index 00000000000..5845638e993 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_smoke_vseq.sv @@ -0,0 +1,221 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// basic smoke test vseq +class alert_handler_smoke_vseq extends alert_handler_base_vseq; + `uvm_object_utils(alert_handler_smoke_vseq) + + `uvm_object_new + + rand bit [NUM_ALERT_CLASSES-1:0] intr_en; + rand bit [NUM_ALERT_CLASSES-1:0] clr_regwen; + rand bit [NUM_ALERT_CLASSES-1:0] class_regwen; + rand bit [NUM_ALERT_CLASSES-1:0] clr_en; + rand bit [NUM_ALERT_CLASSES-1:0] lock_bit_en; + rand bit [NUM_ALERT_CLASSES-1:0] class_en; + rand bit [NUM_ALERTS-1:0] alert_regwen; + rand bit [NUM_ALERTS-1:0] alert_trigger; + rand bit [NUM_ALERTS-1:0] alert_int_err; + rand bit [NUM_ALERTS-1:0] alert_en; + rand bit [NUM_ALERTS-1:0] alert_ping_timeout; + rand bit [NUM_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] alert_class_map; + rand bit [NUM_LOCAL_ALERTS-1:0] local_alert_regwen; + rand bit [NUM_LOCAL_ALERTS-1:0] local_alert_en; + rand bit [NUM_LOCAL_ALERTS-1:0][NUM_ALERT_CLASSES-1:0] local_alert_class_map; + rand bit [NUM_ESCS-1:0] esc_int_err; + rand bit [NUM_ESCS-1:0] esc_standalone_int_err; + rand bit [NUM_ESCS-1:0] esc_ping_timeout; + + rand bit ping_timer_regwen; + rand bit do_clr_esc; + rand bit do_wr_phases_cyc; + rand bit do_esc_intr_timeout; + rand bit do_lock_config; + rand bit [TL_DW-1:0] ping_timeout_cyc; + rand bit [TL_DW-1:0] max_phase_cyc; + rand bit [TL_DW-1:0] intr_timeout_cyc [NUM_ALERT_CLASSES]; + rand bit [TL_DW-1:0] accum_thresh [NUM_ALERT_CLASSES]; + + int max_wait_phases_cyc = MIN_CYCLE_PER_PHASE * NUM_ESC_PHASES; + int max_intr_timeout_cyc; + + uvm_verbosity verbosity = UVM_LOW; + + constraint lock_bit_c { + do_lock_config dist {1 := 1, 0 := 49}; + } + + constraint clr_and_lock_en_c { + lock_bit_en dist {0 :/ 6, [1:'b1111] :/ 4}; + } + + constraint regwen_c { + clr_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6}; + class_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6}; + alert_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6}; + local_alert_regwen dist {[0:'1-1'b1] :/ 4, '1 :/ 6}; + ping_timer_regwen dist { 0 :/ 4 , 1 :/ 6}; + } + + constraint enable_one_alert_c { + $onehot(alert_en); + } + + constraint max_phase_cyc_c { + max_phase_cyc inside {[0:1_000]}; + } + + // Set min to 120 cycles to avoid alert ping timeout due to random delay. + // The max delay after ping request is 10 cycles plus 2 cycles async delay. + // Also the alert_sender and alert_handlers are in different clock domains, with a max 10 times + // difference in clock frequency. + constraint ping_timeout_cyc_c { + ping_timeout_cyc inside {[120:MAX_PING_TIMEOUT_CYCLE]}; + } + + constraint enable_classa_only_c { + alert_class_map == 0; // all the alerts assign to classa + local_alert_class_map == 0; // all local alerts assign to classa + class_en dist {1 :/ 8, 0 :/ 1, [2:'1-1'b1] :/ 1}; + } + + // constraint to trigger escalation + constraint esc_accum_thresh_c { + foreach (accum_thresh[i]) {soft accum_thresh[i] inside {[0:1]};} + } + + constraint esc_intr_timeout_c { + foreach (intr_timeout_cyc[i]) {intr_timeout_cyc[i] inside {[1:1_000]};} + } + + constraint sig_int_c { + alert_int_err == 0; + esc_int_err == 0; + esc_standalone_int_err == 0; + } + + constraint ping_fail_c { + alert_ping_timeout == 0; + esc_ping_timeout == 0; + } + + task pre_start(); + super.pre_start(); + // This is the input for a nonblocking sequence. The value won't be changed until the + // nonblockings sequence end. + esc_ping_timeout.rand_mode(0); + esc_int_err.rand_mode(0); + endtask + + task body(); + fork + begin : isolation_fork + trigger_non_blocking_seqs(); + run_smoke_seq(); + disable fork; // disable non-blocking seqs for stress_all tests + end // end fork + join + endtask : body + + virtual task trigger_non_blocking_seqs(); + `uvm_info(`gfn, $sformatf("esc_int_err %0h esc_ping_timeout %0h", + esc_int_err, esc_ping_timeout), UVM_LOW); + run_esc_rsp_seq_nonblocking(esc_int_err, esc_ping_timeout); + endtask + + virtual task run_smoke_seq(); + `uvm_info(`gfn, $sformatf("num_trans=%0d", num_trans), UVM_LOW) + if (verbosity != UVM_LOW) begin + `uvm_info(`gfn, + $sformatf("Config: intr_en=%0b, alert=%0b, alert_en=%0b, loc_alert_en=%0b", + intr_en, alert_trigger, alert_en, local_alert_en), UVM_LOW) + end + + for (int i = 1; i <= num_trans; i++) begin + `DV_CHECK_RANDOMIZE_FATAL(this) + + // Assign ping timeout value to each alert agent. + foreach (cfg.alert_host_cfg[i]) cfg.alert_host_cfg[i].ping_timeout = alert_ping_timeout[i]; + + `uvm_info(`gfn, $sformatf( + "start seq %0d/%0d: intr_en=0x%0h, alert=0x%0h, alert_en=0x%0h, loc_alert_en=0x%0h", + i, num_trans, intr_en, alert_trigger, alert_en, local_alert_en), verbosity) + + // write initial settings (enable and mapping csrs) + alert_handler_init(.intr_en(intr_en), + .alert_en(alert_en), + .alert_class(alert_class_map), + .loc_alert_en(local_alert_en), + .loc_alert_class(local_alert_class_map)); + + // write class_ctrl + alert_handler_rand_wr_class_ctrl(lock_bit_en, class_en); + + // randomize crashdump triggered phases + alert_handler_crashdump_phases(); + + // randomly write phase cycle registers + // always set phase_cycle for the first iteration, in order to pass stress_all test + if (do_wr_phases_cyc || i == 1) wr_phases_cycle(max_phase_cyc); + + // randomly write interrupt timeout resigers and accumulative threshold registers + if (do_esc_intr_timeout) wr_intr_timeout_cycle(intr_timeout_cyc); + wr_class_accum_threshold(accum_thresh); + wr_ping_timeout_cycle(ping_timeout_cyc); + + // when all configuration registers are set, write lock register + lock_config(do_lock_config); + + // once all above configs are written, lock them with regwen + alert_handler_wr_regwen_regs(clr_regwen, alert_regwen, local_alert_regwen, ping_timer_regwen, + class_regwen); + + // if config is not locked, update max_intr_timeout and max_wait_phases cycles + if (!config_locked) begin + bit [TL_DW-1:0] max_intr_timeout_cyc; + bit [TL_DW-1:0] max_q[$] = intr_timeout_cyc.max(); + max_intr_timeout_cyc = max_q[0]; + max_wait_phases_cyc = max2(max_wait_phases_cyc, max_phase_cyc * NUM_ESC_PHASES); + if (do_lock_config) config_locked = 1; + end + + // drive esc standalone responses and alerts + if (esc_standalone_int_err) drive_esc_rsp(esc_standalone_int_err); + drive_alert(alert_trigger, alert_int_err); + + if (do_esc_intr_timeout) begin + cfg.clk_rst_vif.wait_clks(max_intr_timeout_cyc); + // this task checks three sets of registers related to alert/esc status: + // alert_accum_cnt, esc_cnt, class_state + read_esc_status(); + end + // only check interrupt when no esc_int_err, otherwise clear interrupt might happen the + // same cycle as interrupt triggered by esc_int_err + if ((esc_int_err == 0) && (esc_ping_timeout == 0)) check_alert_interrupts(); + + // if ping timeout enabled, wait for ping timeout done before checking escalation phases + if ((esc_int_err | alert_ping_timeout) > 0) begin + cfg.clk_rst_vif.wait_clks(MAX_PING_TIMEOUT_CYCLE); + end + + // wait escalation done, and random interrupt with clear_esc + wait_alert_esc_done(); + + read_alert_cause(); + read_esc_status(); + if (do_clr_esc) clear_esc(); + check_alert_interrupts(); + end + endtask + + virtual task wait_alert_esc_done(); + wait_alert_handshake_done(); + if ($urandom_range(0, 1) && (esc_int_err == 0)) begin + cfg.clk_rst_vif.wait_clks($urandom_range(0, max_wait_phases_cyc)); + clear_esc(); + end + wait_esc_handshake_done(); + endtask + +endclass : alert_handler_smoke_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_stress_all_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_stress_all_vseq.sv new file mode 100644 index 00000000000..0dd261d7dea --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_stress_all_vseq.sv @@ -0,0 +1,55 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all alert_handler seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +class alert_handler_stress_all_vseq extends alert_handler_base_vseq; + `uvm_object_utils(alert_handler_stress_all_vseq) + + `uvm_object_new + + task body(); + bit entropy_test_flag; // this flag ensures entropy test only runs once due to its long runtime + string seq_names[] = {"alert_handler_smoke_vseq", + "alert_handler_random_alerts_vseq", + "alert_handler_random_classes_vseq", + "alert_handler_esc_intr_timeout_vseq", + "alert_handler_esc_alert_accum_vseq", + "alert_handler_sig_int_fail_vseq", + "alert_handler_entropy_vseq"}; + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + alert_handler_base_vseq alert_vseq; + uint seq_idx = entropy_test_flag ? $urandom_range(0, seq_names.size - 2) : + $urandom_range(0, seq_names.size - 1); + if (seq_names[seq_idx] == "alert_handler_entropy_vseq") entropy_test_flag = 1; + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(alert_vseq, seq) + + // if upper seq disables do_apply_reset for this seq, then can't issue reset + // as upper seq may drive reset + if (do_apply_reset) begin + alert_vseq.do_apply_reset = $urandom_range(0, 1); + // config_locked will be set unless reset is issued + alert_vseq.config_locked = alert_vseq.do_apply_reset ? 0 : config_locked; + end else begin + alert_vseq.do_apply_reset = 0; + alert_vseq.config_locked = config_locked; + end + + alert_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(alert_vseq) + if (seq_names[seq_idx] == "alert_common_vseq") begin + alert_handler_common_vseq common_vseq; + `downcast(common_vseq, alert_vseq); + common_vseq.common_seq_type = "intr_test"; + end + + alert_vseq.start(p_sequencer); + config_locked = alert_vseq.config_locked; + end + endtask : body + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_vseq_list.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_vseq_list.sv new file mode 100644 index 00000000000..99814127148 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/env/seq_lib/alert_handler_vseq_list.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "alert_handler_base_vseq.sv" +`include "alert_handler_smoke_vseq.sv" +`include "alert_handler_common_vseq.sv" +`include "alert_handler_random_alerts_vseq.sv" +`include "alert_handler_random_classes_vseq.sv" +`include "alert_handler_esc_intr_timeout_vseq.sv" +`include "alert_handler_esc_alert_accum_vseq.sv" +`include "alert_handler_sig_int_fail_vseq.sv" +`include "alert_handler_entropy_vseq.sv" +`include "alert_handler_ping_timeout_vseq.sv" +`include "alert_handler_lpg_vseq.sv" +`include "alert_handler_lpg_stub_clk_vseq.sv" +`include "alert_handler_entropy_stress_vseq.sv" +`include "alert_handler_stress_all_vseq.sv" +`include "alert_handler_alert_accum_saturation_vseq.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/sva/alert_handler_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/sva/alert_handler_bind.sv new file mode 100644 index 00000000000..dd69d9571e7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/sva/alert_handler_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module alert_handler_bind; + + bind alert_handler tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind alert_handler alert_handler_csr_assert_fpv alert_handler_csr_assert ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/sva/alert_handler_sva.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/sva/alert_handler_sva.core new file mode 100644 index 00000000000..24bbc56953f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/sva/alert_handler_sva.core @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:alert_handler_sva:0.1 +description: "ALERT_HANDLER assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - alert_handler_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:darjeeling_no_ibex_ip:alert_handler:0.1 + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/alert_handler.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: alert_handler diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core new file mode 100644 index 00000000000..5c5bbf65b76 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tb/alert_handler_tb.core @@ -0,0 +1,18 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:alert_handler_tb:0.1 +description: "ALERT_HANDLER UVM TB environment" +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:alert_handler_test:0.1 + files: + - tb.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tb/tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tb/tb.sv new file mode 100644 index 00000000000..b2e8e709af1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tb/tb.sv @@ -0,0 +1,112 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import alert_handler_env_pkg::*; + import alert_handler_test_pkg::*; + import alert_handler_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n, rst_shadowed_n; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire [NUM_MAX_ESC_SEV-1:0] esc_en; + wire [NUM_CRASHDUMP-1:0] crashdump; + + // interfaces + clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n)); + rst_shadowed_if rst_shadowed_if(.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n)); + pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts); + pins_if #(NUM_CRASHDUMP) crashdump_if(crashdump); + tl_if tl_if(.clk(clk), .rst_n(rst_n)); + alert_handler_if alert_handler_if(.clk(clk), .rst_n(rst_n)); + alert_esc_if esc_device_if [NUM_ESCS](.clk(clk), .rst_n(rst_n)); + alert_esc_if alert_host_if [NUM_ALERTS](.clk(clk), .rst_n(rst_n)); + alert_esc_probe_if probe_if[NUM_ESCS](.clk(clk), .rst_n(rst_n)); + + // dut signals + prim_alert_pkg::alert_rx_t [NUM_ALERTS-1:0] alert_rx; + prim_alert_pkg::alert_tx_t [NUM_ALERTS-1:0] alert_tx; + + prim_esc_pkg::esc_rx_t [NUM_ESCS-1:0] esc_rx; + prim_esc_pkg::esc_tx_t [NUM_ESCS-1:0] esc_tx; + + for (genvar k = 0; k < NUM_ALERTS; k++) begin : gen_alert_if + assign alert_tx[k].alert_p = alert_host_if[k].alert_tx.alert_p; + assign alert_tx[k].alert_n = alert_host_if[k].alert_tx.alert_n; + assign alert_host_if[k].alert_rx.ack_p = alert_rx[k].ack_p; + assign alert_host_if[k].alert_rx.ack_n = alert_rx[k].ack_n; + assign alert_host_if[k].alert_rx.ping_p = alert_rx[k].ping_p; + assign alert_host_if[k].alert_rx.ping_n = alert_rx[k].ping_n; + assign alert_handler_if.alert_ping_reqs[k] = dut.gen_alerts[k].u_alert_receiver.ping_req_i; + initial begin + uvm_config_db#(virtual alert_esc_if)::set(null, $sformatf("*.env.alert_host_agent[%0d]", k), + "vif", alert_host_if[k]); + end + end + + + for (genvar k = 0; k < NUM_ESCS; k++) begin : gen_esc_if + assign esc_rx[k].resp_p = esc_device_if[k].esc_rx.resp_p; + assign esc_rx[k].resp_n = esc_device_if[k].esc_rx.resp_n; + assign esc_device_if[k].esc_tx.esc_p = esc_tx[k].esc_p; + assign esc_device_if[k].esc_tx.esc_n = esc_tx[k].esc_n; + assign probe_if[k].esc_en = dut.esc_sig_req[k]; + assign alert_handler_if.esc_ping_reqs[k] = dut.gen_esc_sev[k].u_esc_sender.ping_req_i; + initial begin + uvm_config_db#(virtual alert_esc_if)::set(null, $sformatf("*.env.esc_device_agent[%0d]", k), + "vif", esc_device_if[k]); + uvm_config_db#(virtual alert_esc_probe_if)::set(null, + $sformatf("*.env.esc_device_agent[%0d]", k), "probe_vif", probe_if[k]); + end + end + + // edn_clk, edn_rst_n and edn_if are defined and driven in below macro + `DV_EDN_IF_CONNECT + + // main dut + alert_handler dut ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .rst_shadowed_ni ( rst_shadowed_n), + .clk_edn_i ( edn_clk ), + .rst_edn_ni ( edn_rst_n ), + .tl_i ( tl_if.h2d ), + .tl_o ( tl_if.d2h ), + .intr_classa_o ( interrupts[0] ), + .intr_classb_o ( interrupts[1] ), + .intr_classc_o ( interrupts[2] ), + .intr_classd_o ( interrupts[3] ), + .lpg_cg_en_i ( alert_handler_if.lpg_cg_en ), + .lpg_rst_en_i ( alert_handler_if.lpg_rst_en ), + .crashdump_o ( crashdump ), + .edn_o ( edn_if[0].req ), + .edn_i ( {edn_if[0].ack, edn_if[0].d_data} ), + .alert_rx_o ( alert_rx ), + .alert_tx_i ( alert_tx ), + .esc_rx_i ( esc_rx ), + .esc_tx_o ( esc_tx ) + ); + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", + rst_shadowed_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(crashdump_vif)::set(null, "*.env", "crashdump_vif", crashdump_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + uvm_config_db#(virtual alert_handler_if)::set(null, "*.env", "alert_handler_vif", + alert_handler_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tests/alert_handler_base_test.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tests/alert_handler_base_test.sv new file mode 100644 index 00000000000..32cc5b33d68 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tests/alert_handler_base_test.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class alert_handler_base_test extends cip_base_test #( + .ENV_T(alert_handler_env), + .CFG_T(alert_handler_env_cfg) + ); + + `uvm_component_utils(alert_handler_base_test) + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // alert_handler_env_cfg: cfg + // alert_handler_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : alert_handler_base_test diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tests/alert_handler_test.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tests/alert_handler_test.core new file mode 100644 index 00000000000..c4d8856d5a2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tests/alert_handler_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:alert_handler_test:0.1 +description: "ALERT_HANDLER DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:alert_handler_env + files: + - alert_handler_test_pkg.sv + - alert_handler_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tests/alert_handler_test_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tests/alert_handler_test_pkg.sv new file mode 100644 index 00000000000..357417515cf --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/dv/tests/alert_handler_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package alert_handler_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import alert_handler_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "alert_handler_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core new file mode 100644 index 00000000000..c1530971650 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/alert_handler_esc_timer_fpv.core @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_fpv:alert_handler_esc_timer_fpv:0.1 +description: "alert_handler_esc_timer FPV target" +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:darjeeling_no_ibex_ip:alert_handler + files: + - vip/alert_handler_esc_timer_assert_fpv.sv + - tb/alert_handler_esc_timer_bind_fpv.sv + - tb/alert_handler_esc_timer_tb.sv + file_type: systemVerilogSource + +targets: + default: &default_target + # note, this setting is just used + # to generate a file list for jg + default_tool: icarus + filesets: + - files_formal + toplevel: alert_handler_esc_timer_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core new file mode 100644 index 00000000000..055314f9aad --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/alert_handler_ping_timer_fpv.core @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_fpv:alert_handler_ping_timer_fpv:0.1 +description: "ALERT_HANDLER FPV target" +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:darjeeling_no_ibex_ip:alert_handler + files: + - vip/alert_handler_ping_timer_assert_fpv.sv + - tb/alert_handler_ping_timer_bind_fpv.sv + - tb/alert_handler_ping_timer_tb.sv + file_type: systemVerilogSource + +targets: + default: &default_target + # note, this setting is just used + # to generate a file list for jg + default_tool: icarus + filesets: + - files_formal + toplevel: alert_handler_ping_timer_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_bind_fpv.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_bind_fpv.sv new file mode 100644 index 00000000000..4bcbb1e19f6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_bind_fpv.sv @@ -0,0 +1,31 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +module alert_handler_esc_timer_bind_fpv; + + + bind alert_handler_esc_timer + alert_handler_esc_timer_assert_fpv i_alert_handler_esc_timer_assert_fpv ( + .clk_i, + .rst_ni, + .en_i, + .clr_i, + .accu_trig_i, + .accu_fail_i, + .timeout_en_i, + .timeout_cyc_i, + .esc_en_i, + .esc_map_i, + .phase_cyc_i, + .crashdump_phase_i, + .latch_crashdump_o, + .esc_trig_o, + .esc_cnt_o, + .esc_sig_req_o, + .esc_state_o + ); + + +endmodule : alert_handler_esc_timer_bind_fpv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv new file mode 100644 index 00000000000..a30b1c220ae --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_esc_timer_tb.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for alert_handler_esc_timer. +// Intended to be used with a formal tool. + +module alert_handler_esc_timer_tb import alert_handler_pkg::*; ( + input clk_i, + input rst_ni, + input en_i, + input clr_i, + input accu_trig_i, + input accu_fail_i, + input timeout_en_i, + input [EscCntDw-1:0] timeout_cyc_i, + input [N_ESC_SEV-1:0] esc_en_i, + input [N_ESC_SEV-1:0][PHASE_DW-1:0] esc_map_i, + input [N_PHASES-1:0][EscCntDw-1:0] phase_cyc_i, + input [PHASE_DW-1:0] crashdump_phase_i, + output logic latch_crashdump_o, + output logic esc_trig_o, + output logic[EscCntDw-1:0] esc_cnt_o, + output logic[N_ESC_SEV-1:0] esc_sig_req_o, + output cstate_e esc_state_o +); + + alert_handler_esc_timer i_alert_handler_esc_timer ( + .clk_i, + .rst_ni, + .en_i, + .clr_i, + .accu_trig_i, + .accu_fail_i, + .timeout_en_i, + .timeout_cyc_i, + .esc_en_i, + .esc_map_i, + .phase_cyc_i, + .crashdump_phase_i, + .latch_crashdump_o, + .esc_trig_o, + .esc_cnt_o, + .esc_sig_req_o, + .esc_state_o + ); + + +endmodule : alert_handler_esc_timer_tb diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_bind_fpv.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_bind_fpv.sv new file mode 100644 index 00000000000..59ee6e403e2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_bind_fpv.sv @@ -0,0 +1,29 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +module alert_handler_ping_timer_bind_fpv; + + + bind alert_handler_ping_timer + alert_handler_ping_timer_assert_fpv i_alert_handler_ping_timer_assert_fpv ( + .clk_i, + .rst_ni, + .edn_req_o, + .edn_ack_i, + .edn_data_i, + .en_i, + .alert_ping_en_i, + .ping_timeout_cyc_i, + .wait_cyc_mask_i, + .alert_ping_req_o, + .esc_ping_req_o, + .alert_ping_ok_i, + .esc_ping_ok_i, + .alert_ping_fail_o, + .esc_ping_fail_o + ); + + +endmodule : alert_handler_ping_timer_bind_fpv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv new file mode 100644 index 00000000000..fe28509e644 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/alert_handler_ping_timer_tb.sv @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for ping timer in alert handler. Intended to use with +// a formal tool. + +module alert_handler_ping_timer_tb import alert_handler_pkg::*; ( + input clk_i, + input rst_ni, + output logic edn_req_o, + input edn_ack_i, + input [LfsrWidth-1:0] edn_data_i, + input en_i, + input [NAlerts-1:0] alert_ping_en_i, + input [PING_CNT_DW-1:0] ping_timeout_cyc_i, + input [PING_CNT_DW-1:0] wait_cyc_mask_i, + output logic [NAlerts-1:0] alert_ping_req_o, + output logic [N_ESC_SEV-1:0] esc_ping_req_o, + input [NAlerts-1:0] alert_ping_ok_i, + input [N_ESC_SEV-1:0] esc_ping_ok_i, + output logic alert_ping_fail_o, + output logic esc_ping_fail_o +); + + alert_handler_ping_timer #( + // disable max length check in FPV, otherwise this + // will not converge within acceptable compute time + .MaxLenSVA ( 1'b0 ) + ) i_alert_handler_ping_timer ( + .clk_i , + .rst_ni , + .edn_req_o , + .edn_ack_i , + .edn_data_i , + .en_i , + .alert_ping_en_i , + .ping_timeout_cyc_i, + .wait_cyc_mask_i , + .alert_ping_req_o , + .esc_ping_req_o , + .alert_ping_ok_i , + .esc_ping_ok_i , + .alert_ping_fail_o , + .esc_ping_fail_o + ); + +endmodule : alert_handler_ping_timer_tb diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/esc_after_load.tcl b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/esc_after_load.tcl new file mode 100644 index 00000000000..bc38fee3a77 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/esc_after_load.tcl @@ -0,0 +1,10 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# The UpCntIncrStable_A and DnCntIncrStable_A assertions are vacuous +# in this test because we can never get to the situation where the +# counter would saturate: it only be set to 1 and incremented, but it +# is reasonably wide (EscCntDw=32). +cover -disable -regexp ".*\.g_check_incr\.UpCntIncrStable_A:precondition1" +cover -disable -regexp ".*\.g_check_incr\.DnCntIncrStable_A:precondition1" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/ping_after_load.tcl b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/ping_after_load.tcl new file mode 100644 index 00000000000..0026b5e6cfc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/tb/ping_after_load.tcl @@ -0,0 +1,11 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# In the ping timer, there is a counter called u_prim_count_esc_cnt. The FSM that drives this uses +# the prim_count to count through the N_ESC_SEV senders and then clears it back to zero. As a +# result, it never tries to increment the counter at maximum value (N_ESC_SEV-1), so we will never +# see the precondition for the *CntIncrStable_A assertions. Waive the cover property for each +# assertion. +cover -disable -regexp ".*\.u_prim_count_esc_cnt\..*\.UpCntIncrStable_A:precondition1" +cover -disable -regexp ".*\.u_prim_count_esc_cnt\..*\.DnCntIncrStable_A:precondition1" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/vip/alert_handler_esc_timer_assert_fpv.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/vip/alert_handler_esc_timer_assert_fpv.sv new file mode 100644 index 00000000000..37b99de1ca1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/vip/alert_handler_esc_timer_assert_fpv.sv @@ -0,0 +1,139 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Assertions for alert_handler_esc_timer. +// Intended to be used with a formal tool. + +`include "prim_assert.sv" + +module alert_handler_esc_timer_assert_fpv import alert_handler_pkg::*; ( + input clk_i, + input rst_ni, + input en_i, + input clr_i, + input accu_trig_i, + input accu_fail_i, + input timeout_en_i, + input [EscCntDw-1:0] timeout_cyc_i, + input [N_ESC_SEV-1:0] esc_en_i, + input [N_ESC_SEV-1:0][PHASE_DW-1:0] esc_map_i, + input [N_PHASES-1:0][EscCntDw-1:0] phase_cyc_i, + input [PHASE_DW-1:0] crashdump_phase_i, + input logic latch_crashdump_o, + input logic esc_trig_o, + input logic[EscCntDw-1:0] esc_cnt_o, + input logic[N_ESC_SEV-1:0] esc_sig_req_o, + input cstate_e esc_state_o +); + + /////////////////////////////// + // Declarations & Parameters // + /////////////////////////////// + + // constrain the state-spaces + localparam int unsigned MAX_TIMEOUT_CYCLES = 10; + localparam int unsigned MAX_PHASE_CYCLES = 10; + + // symbolic vars for phase map check + logic [1:0] esc_sel; + logic [1:0] phase_sel; + localparam cstate_e Phases [4] = {Phase0, Phase1, Phase2, Phase3}; + + // set regs + logic esc_has_triggered_q; + + + ///////////////// + // Assumptions // + ///////////////// + + `ASSUME(TimeoutCycles_M, timeout_cyc_i < MAX_TIMEOUT_CYCLES) + `ASSUME(TimeoutCyclesConst_M, ##1 $stable(timeout_cyc_i)) + + `ASSUME(PhaseCycles_M, phase_cyc_i < MAX_PHASE_CYCLES) + `ASSUME(PhaseCyclesConst_M, ##1 $stable(phase_cyc_i)) + + `ASSUME(CrashdumpPhaseConst_M, ##1 $stable(crashdump_phase_i)) + + `ASSUME(EscSelConst_M, ##1 $stable(esc_sel)) + `ASSUME(PhaseSelConst_M, ##1 $stable(phase_sel)) + + //////////////////////// + // Forward Assertions // + //////////////////////// + + // if the class is not enabled and we are in IDLE state, + // neither of the two escalation mechanisms shall fire + `ASSERT(ClassDisabledNoEscTrig_A, esc_state_o == Idle && !en_i |-> !esc_trig_o) + `ASSERT(ClassDisabledNoEsc_A, esc_state_o == Idle && !en_i && !alert_handler_esc_timer.fsm_error + |-> !esc_sig_req_o) + `ASSERT(EscDisabledNoEsc_A, !esc_en_i[esc_sel] && !alert_handler_esc_timer.fsm_error |-> + !esc_sig_req_o[esc_sel]) + + // if timeout counter is enabled due to a pending interrupt, check escalation + // assume accumulation trigger is not asserted during this sequence + `ASSERT(TimeoutEscTrig_A, esc_state_o == Idle ##1 en_i && $rose(timeout_en_i) && + (timeout_cyc_i > 0) ##1 timeout_en_i [*MAX_TIMEOUT_CYCLES] |=> esc_has_triggered_q, + clk_i, !rst_ni || accu_trig_i || clr_i || accu_fail_i) + + // check whether an accum trig leads to escalation if enabled + `ASSERT(AccumEscTrig_A, ##1 en_i && accu_trig_i && esc_state_o inside {Idle, Timeout} |=> + esc_has_triggered_q, clk_i, !rst_ni || clr_i || accu_fail_i) + + // check escalation cnt and state out + `ASSERT(EscCntOut_A, alert_handler_esc_timer.u_prim_count.cnt_q[0] == esc_cnt_o) + + // check clr input + // we cannot use clr to exit from the timeout state + `ASSERT(ClrCheck_A, clr_i && !(esc_state_o inside {Idle, Timeout, FsmError}) && !accu_fail_i |=> + esc_state_o == Idle) + + // check escalation map + `ASSERT(PhaseEscMap_A, esc_state_o == Phases[phase_sel] && esc_map_i[esc_sel] == phase_sel && + esc_en_i[esc_sel] |-> esc_sig_req_o[esc_sel]) + + // check terminal state is reached eventually if triggered and not cleared + `ASSERT(TerminalState_A, esc_trig_o |-> strong(##[1:$] esc_state_o == Terminal), + clk_i, !rst_ni || clr_i || accu_fail_i) + + // check that the crashdump capture trigger is asserted correctly + `ASSERT(CrashdumpTrigger_A, + ##1 $changed(esc_state_o) && + esc_state_o == cstate_e'(4 + crashdump_phase_i) + <-> + $past(latch_crashdump_o), esc_state_o == FsmError) + + ///////////////////////// + // Backward Assertions // + ///////////////////////// + + // escalation can only be triggered when in Idle or Timeout state. Trigger mechanisms are either + // the accumulation trigger or a timeout trigger + `ASSERT(EscTrigBkwd_A, esc_trig_o |-> esc_state_o inside {Idle, Timeout} && accu_trig_i || + esc_state_o == Timeout && esc_cnt_o >= timeout_cyc_i) + `ASSERT(NoEscTrigBkwd_A, !esc_trig_o |-> !(esc_state_o inside {Idle, Timeout}) || + !en_i || !accu_trig_i || !timeout_en_i || clr_i) + + // escalation signals can only be asserted in the escalation phase states, or + // if we are in the terminal FsmError state + `ASSERT(EscBkwd_A, esc_sig_req_o[esc_sel] |-> esc_en_i[esc_sel] && + esc_has_triggered_q || alert_handler_esc_timer.fsm_error) + `ASSERT(NoEscBkwd_A, !esc_sig_req_o[esc_sel] |-> !esc_en_i[esc_sel] || + esc_state_o != Phases[esc_map_i[esc_sel]] && esc_state_o != FsmError, + clk_i, !rst_ni || clr_i) + + ////////////////////// + // Helper Processes // + ////////////////////// + + // set registers + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + esc_has_triggered_q <= 1'b0; + end else begin + esc_has_triggered_q <= esc_has_triggered_q & ~clr_i | esc_trig_o; + end + end + +endmodule : alert_handler_esc_timer_assert_fpv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/vip/alert_handler_ping_timer_assert_fpv.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/vip/alert_handler_ping_timer_assert_fpv.sv new file mode 100644 index 00000000000..2de078e3e09 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/fpv/vip/alert_handler_ping_timer_assert_fpv.sv @@ -0,0 +1,132 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Assertions for ping timer in alert handler. Intended to use with +// a formal tool. + +`include "prim_assert.sv" + +module alert_handler_ping_timer_assert_fpv import alert_handler_pkg::*; ( + input clk_i, + input rst_ni, + input edn_req_o, + input edn_ack_i, + input [LfsrWidth-1:0] edn_data_i, + input en_i, + input [NAlerts-1:0] alert_ping_en_i, + input [PING_CNT_DW-1:0] ping_timeout_cyc_i, + input [PING_CNT_DW-1:0] wait_cyc_mask_i, + input [NAlerts-1:0] alert_ping_req_o, + input [N_ESC_SEV-1:0] esc_ping_req_o, + input [NAlerts-1:0] alert_ping_ok_i, + input [N_ESC_SEV-1:0] esc_ping_ok_i, + input alert_ping_fail_o, + input esc_ping_fail_o +); + + localparam int unsigned PingEnDw = N_ESC_SEV + NAlerts; + logic [PingEnDw-1:0] ping_en_vector, ping_en_mask, ping_ok_vector; + + assign ping_en_vector = {esc_ping_req_o, alert_ping_req_o}; + assign ping_en_mask = {N_ESC_SEV'('1), alert_ping_en_i}; + assign ping_ok_vector = {esc_ping_ok_i, alert_ping_ok_i}; + + ///////////////// + // Assumptions // + ///////////////// + + localparam int MaxWaitCntDw = 3; + + // symbolic variables. we want to assess all valid indices + logic [$clog2(PingEnDw)-1:0] ping_en_sel; + logic [$clog2(N_ESC_SEV)-1:0] esc_idx; + `ASSUME_FPV(PingEnSelRange_M, ping_en_sel < PingEnDw) + `ASSUME_FPV(PingEnSelStable_M, ##1 $stable(ping_en_sel)) + `ASSUME_FPV(EscIdxRange_M, esc_idx < N_ESC_SEV) + `ASSUME_FPV(EscIdxStable_M, ##1 $stable(esc_idx)) + // assume that the alert enable configuration is locked once en_i is high + // this is ensured by the CSR regfile on the outside + `ASSUME_FPV(ConfigLocked0_M, en_i |-> $stable(alert_ping_en_i)) + `ASSUME_FPV(ConfigLocked1_M, en_i |-> $stable(ping_timeout_cyc_i)) + // enable stays high forever, once it has been asserted + `ASSUME(ConfigLocked2_M, en_i |=> en_i) + // reduce state space by reducing length of wait period + `ASSUME_FPV(WaitPeriod0_M, wait_cyc_mask_i == {MaxWaitCntDw{1'b1}}) + `ASSUME_FPV(WaitPeriod1_M, ping_timeout_cyc_i <= {MaxWaitCntDw{1'b1}}) + + //////////////////////// + // Forward Assertions // + //////////////////////// + + // no pings on disabled alerts + `ASSERT(DisabledNoAlertPings_A, ((~alert_ping_en_i) & alert_ping_req_o) == 0) + // no pings when not enabled + `ASSERT(NoPingsWhenDisabled0_A, !en_i |-> !alert_ping_req_o) + `ASSERT(NoPingsWhenDisabled1_A, !en_i |-> !esc_ping_req_o) + `ASSERT(NoPingsWhenDisabled2_A, en_i && !ping_en_mask[ping_en_sel] |-> + !ping_en_vector[ping_en_sel]) + + // spurious pings (i.e. pings that where not requested) + // on alert channels + `ASSERT(SpuriousPingsDetected0_A, en_i && !ping_en_vector[ping_en_sel] && + ping_ok_vector[ping_en_sel] && ping_en_sel < NAlerts |-> + alert_ping_fail_o) + // on escalation channels + `ASSERT(SpuriousPingsDetected1_A, en_i && !ping_en_vector[ping_en_sel] && + ping_ok_vector[ping_en_sel] && ping_en_sel >= NAlerts |-> + esc_ping_fail_o) + // response must be one hot + `ASSERT(SpuriousPingsDetected2_A, en_i && !$onehot0(ping_ok_vector) |-> + esc_ping_fail_o || alert_ping_fail_o) + + // ensure that the number of cycles between pings on a specific escalation channel + // are within bounds. we try to prove this property with a margin of 2x here, whereas + // the ping receivers actually work with a margin of 4x to stay on the safe side. + localparam int MarginFactor = 2; + localparam int NumWaitCounts = 2; + localparam int NumTimeoutCounts = 2; + localparam int PingPeriodBound = MarginFactor * // margin to apply + N_ESC_SEV * // number of escalation channels to ping + (NumWaitCounts + // 1 alert and 1 esc wait count + NumTimeoutCounts) * // 1 alert and 1 esc timeout count + 2**MaxWaitCntDw; // maximum counter value + + `ASSERT(EscalationPingPeriodWithinBounds_A, + $rose(esc_ping_req_o[esc_idx]) + |-> + ##[1 : PingPeriodBound] + $rose(esc_ping_req_o[esc_idx])) + + ///////////////////////// + // Backward Assertions // + ///////////////////////// + + // no pings when not enabled + `ASSERT(NoPingsWhenDisabledBkwd0_A, alert_ping_req_o |-> en_i) + `ASSERT(NoPingsWhenDisabledBkwd1_A, esc_ping_req_o |-> en_i) + + // spurious pings (i.e. pings that where not requested) + // on alert channels + `ASSERT(SpuriousPingsDetectedBkwd0_A, !alert_ping_fail_o |-> + !en_i || ping_en_vector[ping_en_sel] || + !ping_ok_vector[ping_en_sel] || ping_en_sel >= NAlerts) + // on escalation channels + `ASSERT(SpuriousPingsDetectedBkwd1_A, !esc_ping_fail_o |-> + !en_i || ping_en_vector[ping_en_sel] || + !ping_ok_vector[ping_en_sel] || ping_en_sel < NAlerts) + // response must be one hot + `ASSERT(SpuriousPingsDetectedBkwd2_A, !esc_ping_fail_o && !alert_ping_fail_o |-> + !en_i || $onehot0(ping_ok_vector)) + + ////////////////////////////////////////////////////////// + // Currently not Tested in FPV due to large state space // + ////////////////////////////////////////////////////////// + + // 1) if an alert is enabled, it should be pinged eventually + // when entropy input is disabled + // 2) ping ok within timeout -> ok + // 3) ping ok after timeout -> alert + // 4) no ping response -> alert + +endmodule : alert_handler_ping_timer_assert_fpv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/lint/alert_handler.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/lint/alert_handler.vlt new file mode 100644 index 00000000000..b2bafa9c6df --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/lint/alert_handler.vlt @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +// Tell the Verilator scheduler to split up hw2reg_wrap into separate fields +// when scheduling processes. This structure is used (among other things) to +// communicate between alert_handler_accu and alert_handler_esc_timer instances +// and tracking it as one big blob causes spurious apparent circular +// dependencies. +split_var -module "alert_handler" -var "hw2reg_wrap" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/lint/alert_handler.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/lint/alert_handler.waiver new file mode 100644 index 00000000000..b34560b2567 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/lint/alert_handler.waiver @@ -0,0 +1,44 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for alert handler + +waive -rules ENUM_RANGE -location {alert_handler_esc_timer.sv} -regexp {state_q} \ + -comment "State is used to index timeout cycle counts" + +waive -rules NOT_READ -location {alert_handler_ping_timer.sv} -regexp {perm_state} \ + -comment "Upper bits of permuted array are not read" + +waive -rules HIER_NET_NOT_READ -location {alert_handler_ping_timer.sv} -regexp {perm_state} \ + -comment "Upper bits of permuted array are not read" + +waive -rules HIER_NET_NOT_READ -location {alert_handler.sv} -regexp {[Nn]et 'tl_[io]\.[ad]_(address|param|user)} \ + -comment "Register interface doesn't use upper address and param, user filed" + +waive -rules INSIDE_OP_CONTEXT -location {prim_esc_sender.sv} -regexp {inside} \ + -comment "Inside operator is used within SVA" + +waive -rules CASE_INC -location {alert_handler_esc_timer.sv} -regexp {'b010} \ + -comment "Not all case tags are required." + +waive -rules CASE_INC -location {alert_handler_ping_timer.sv} -regexp {'b11} \ + -comment "Not all case tags are required." + +waive -rules CASE_INC -location {prim_esc_sender.sv} -regexp {'b111} \ + -comment "Not all case tags are required." + +waive -rules ONE_BIT_VEC -location {prim_lfsr.sv} -regexp {InDw - 1:0} \ + -comment "Data input may be one bit wide." + +waive -rules VAR_INDEX -location {alert_handler_esc_timer.sv} -regexp {phase_cyc_i\[phase_idx\]} \ + -comment "This indexing expression is correct." + +waive -rules VAR_INDEX -location {alert_handler_ping_timer.sv} -regexp {enable_mask\[id_to_ping\]} \ + -comment "This indexing expression is correct." + +waive -rules CLOCK_USE -location {alert_handler_lpg_ctrl.sv} -msg {'clk_i' is connected to 'prim_lc_sync' port 'clk_i', and used as} \ + -comment "This clock connection is only used for assertions internal to the prim module." + +waive -rules RESET_USE -location {alert_handler_lpg_ctrl.sv} -msg {'rst_ni' is connected to 'prim_lc_sync' port 'rst_ni', and used as} \ + -comment "This reset connection is only used for assertions internal to the prim module." diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler.sv new file mode 100644 index 00000000000..ef14201f283 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler.sv @@ -0,0 +1,344 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Alert handler top + +`include "prim_assert.sv" + +module alert_handler + import alert_handler_pkg::*; + import prim_alert_pkg::*; + import prim_esc_pkg::*; +#( + // Number of cycles a differential skew is tolerated on the alert and escalation signal + parameter int unsigned AlertSkewCycles = 1, + parameter int EscNumSeverities = 4, + parameter int EscPingCountWidth = 16, + // Compile time random constants, to be overriden by topgen. + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault +) ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + input clk_edn_i, + input rst_edn_ni, + // Bus Interface (device) + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // Interrupt Requests + output logic intr_classa_o, + output logic intr_classb_o, + output logic intr_classc_o, + output logic intr_classd_o, + // Clock gating and reset info from rstmgr and clkmgr + // SEC_CM: LPG.INTERSIG.MUBI + input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_cg_en_i, + input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_rst_en_i, + // State information for HW crashdump + output alert_crashdump_t crashdump_o, + // Entropy Input + output edn_pkg::edn_req_t edn_o, + input edn_pkg::edn_rsp_t edn_i, + // Alert Sources + // SEC_CM: ALERT.INTERSIG.DIFF + input prim_alert_pkg::alert_tx_t [NAlerts-1:0] alert_tx_i, + output prim_alert_pkg::alert_rx_t [NAlerts-1:0] alert_rx_o, + // Escalation outputs + // SEC_CM: ESC.INTERSIG.DIFF + input prim_esc_pkg::esc_rx_t [N_ESC_SEV-1:0] esc_rx_i, + output prim_esc_pkg::esc_tx_t [N_ESC_SEV-1:0] esc_tx_o +); + + ////////////////////////////////// + // Regfile Breakout and Mapping // + ////////////////////////////////// + + logic [N_CLASSES-1:0] latch_crashdump; + logic [N_LOC_ALERT-1:0] loc_alert_trig; + logic [N_CLASSES-1:0] irq; + hw2reg_wrap_t hw2reg_wrap; + reg2hw_wrap_t reg2hw_wrap; + + assign {intr_classd_o, + intr_classc_o, + intr_classb_o, + intr_classa_o} = irq; + + // SEC_CM: CONFIG.SHADOW + // SEC_CM: PING_TIMER.CONFIG.REGWEN + // SEC_CM: ALERT.CONFIG.REGWEN + // SEC_CM: ALERT_LOC.CONFIG.REGWEN + // SEC_CM: CLASS.CONFIG.REGWEN + alert_handler_reg_wrap u_reg_wrap ( + .clk_i, + .rst_ni, + .rst_shadowed_ni, + .tl_i, + .tl_o, + .irq_o ( irq ), + .latch_crashdump_i ( latch_crashdump ), + .crashdump_o, + .hw2reg_wrap, + .reg2hw_wrap, + // SEC_CM: BUS.INTEGRITY + .fatal_integ_alert_o(loc_alert_trig[4]) + ); + + // SEC_CM: CONFIG.SHADOW + assign loc_alert_trig[5] = reg2hw_wrap.shadowed_err_update; + assign loc_alert_trig[6] = reg2hw_wrap.shadowed_err_storage; + + //////////////// + // Ping Timer // + //////////////// + + logic [NAlerts-1:0] alert_ping_req; + logic [NAlerts-1:0] alert_ping_ok; + logic [N_ESC_SEV-1:0] esc_ping_req; + logic [N_ESC_SEV-1:0] esc_ping_ok; + + logic edn_req, edn_ack; + logic [LfsrWidth-1:0] edn_data; + + prim_edn_req #( + .OutWidth(LfsrWidth) + ) u_edn_req ( + // Alert handler side + .clk_i, + .rst_ni, + .req_chk_i ( 1'b1 ), + .req_i ( edn_req ), + .ack_o ( edn_ack ), + .data_o ( edn_data ), + .fips_o ( ), + .err_o ( ), + // EDN side + .clk_edn_i, + .rst_edn_ni, + .edn_o ( edn_o ), + .edn_i ( edn_i ) + ); + + alert_handler_ping_timer #( + .RndCnstLfsrSeed(RndCnstLfsrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm) + ) u_ping_timer ( + .clk_i, + .rst_ni, + .edn_req_o ( edn_req ), + .edn_ack_i ( edn_ack ), + .edn_data_i ( edn_data ), + .en_i ( reg2hw_wrap.ping_enable ), + .alert_ping_en_i ( reg2hw_wrap.alert_ping_en ), + .ping_timeout_cyc_i ( reg2hw_wrap.ping_timeout_cyc ), + // set this to the maximum width in the design. + // can be overridden in DV and FPV to shorten the wait periods. + // note however that this needs to be a right-aligned mask. + // also, do not set this to a value lower than 0x7. + .wait_cyc_mask_i ( {PING_CNT_DW{1'b1}} ), + // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK + .alert_ping_req_o ( alert_ping_req ), + // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK + .esc_ping_req_o ( esc_ping_req ), + .alert_ping_ok_i ( alert_ping_ok ), + .esc_ping_ok_i ( esc_ping_ok ), + .alert_ping_fail_o ( loc_alert_trig[0] ), + .esc_ping_fail_o ( loc_alert_trig[1] ) + ); + + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(PingTimerEscCnterCheck_A, + u_ping_timer.u_prim_count_esc_cnt, + loc_alert_trig[0] & loc_alert_trig[1], + (reg2hw_wrap.ping_enable == 0)) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(PingTimerCnterCheck_A, + u_ping_timer.u_prim_count_cnt, + loc_alert_trig[0] & loc_alert_trig[1], + (reg2hw_wrap.ping_enable == 0)) + `ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ERR(PingTimerDoubleLfsrCheck_A, + u_ping_timer.u_prim_double_lfsr, + loc_alert_trig[0] & loc_alert_trig[1], + (reg2hw_wrap.ping_enable == 0)) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(PingTimerFsmCheck_A, + u_ping_timer.u_state_regs, + loc_alert_trig[0] & loc_alert_trig[1], + (reg2hw_wrap.ping_enable == 0)) + + ///////////////////////////// + // Low-power group control // + ///////////////////////////// + + prim_mubi_pkg::mubi4_t [NAlerts-1:0] alert_init_trig; + alert_handler_lpg_ctrl u_alert_handler_lpg_ctrl ( + .clk_i, + .rst_ni, + // SEC_CM: LPG.INTERSIG.MUBI + .lpg_cg_en_i, + .lpg_rst_en_i, + .alert_init_trig_o ( alert_init_trig ) + ); + + ///////////////////// + // Alert Receivers // + ///////////////////// + + logic [NAlerts-1:0] alert_integfail; + logic [NAlerts-1:0] alert_trig; + + // Target interrupt notification + for (genvar k = 0 ; k < NAlerts ; k++) begin : gen_alerts + prim_alert_receiver #( + .AsyncOn(AsyncOn[k]), + .SkewCycles(AlertSkewCycles) + ) u_alert_receiver ( + .clk_i, + .rst_ni, + .init_trig_i ( alert_init_trig[k] ), + .ping_req_i ( alert_ping_req[k] ), + .ping_ok_o ( alert_ping_ok[k] ), + .integ_fail_o ( alert_integfail[k] ), + .alert_o ( alert_trig[k] ), + // SEC_CM: ALERT.INTERSIG.DIFF + .alert_rx_o ( alert_rx_o[k] ), + .alert_tx_i ( alert_tx_i[k] ) + ); + end + + assign loc_alert_trig[2] = |(reg2hw_wrap.alert_en & alert_integfail); + + /////////////////////////////////////// + // Set alert cause bits and classify // + /////////////////////////////////////// + + alert_handler_class u_class ( + .alert_trig_i ( alert_trig ), + .loc_alert_trig_i ( loc_alert_trig ), + .alert_en_i ( reg2hw_wrap.alert_en ), + .loc_alert_en_i ( reg2hw_wrap.loc_alert_en ), + .alert_class_i ( reg2hw_wrap.alert_class ), + .loc_alert_class_i ( reg2hw_wrap.loc_alert_class ), + .alert_cause_o ( hw2reg_wrap.alert_cause ), + .loc_alert_cause_o ( hw2reg_wrap.loc_alert_cause ), + .class_trig_o ( hw2reg_wrap.class_trig ) + ); + + //////////////////////////////////// + // Escalation Handling of Classes // + //////////////////////////////////// + + logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_sig_req; + + for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classes + logic class_accu_fail, class_accu_trig; + alert_handler_accu u_accu ( + .clk_i, + .rst_ni, + .class_en_i ( reg2hw_wrap.class_en[k] ), + .clr_i ( reg2hw_wrap.class_clr[k] ), + .class_trig_i ( hw2reg_wrap.class_trig[k] ), + .thresh_i ( reg2hw_wrap.class_accum_thresh[k] ), + .accu_cnt_o ( hw2reg_wrap.class_accum_cnt[k] ), + .accu_trig_o ( class_accu_trig ), + .accu_fail_o ( class_accu_fail ) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(AccuCnterCheck_A, + u_accu.u_prim_count, + esc_tx_o[0].esc_p & esc_tx_o[1].esc_p & esc_tx_o[2].esc_p & esc_tx_o[3].esc_p) + + alert_handler_esc_timer u_esc_timer ( + .clk_i, + .rst_ni, + .en_i ( reg2hw_wrap.class_en[k] ), + // this clear does not apply to interrupts + .clr_i ( reg2hw_wrap.class_clr[k] ), + // an interrupt enables the timeout + .timeout_en_i ( irq[k] ), + .accu_trig_i ( class_accu_trig ), + .accu_fail_i ( class_accu_fail ), + .timeout_cyc_i ( reg2hw_wrap.class_timeout_cyc[k] ), + .esc_en_i ( reg2hw_wrap.class_esc_en[k] ), + .esc_map_i ( reg2hw_wrap.class_esc_map[k] ), + .phase_cyc_i ( reg2hw_wrap.class_phase_cyc[k] ), + .crashdump_phase_i ( reg2hw_wrap.class_crashdump_phase[k] ), + .latch_crashdump_o ( latch_crashdump[k] ), + .esc_trig_o ( hw2reg_wrap.class_esc_trig[k] ), + .esc_cnt_o ( hw2reg_wrap.class_esc_cnt[k] ), + .esc_state_o ( hw2reg_wrap.class_esc_state[k] ), + .esc_sig_req_o ( class_esc_sig_req[k] ) + ); + + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ERR(EscTimerCnterCheck_A, + u_esc_timer.u_prim_count, + esc_tx_o[0].esc_p & esc_tx_o[1].esc_p & esc_tx_o[2].esc_p & esc_tx_o[3].esc_p) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(EscTimerFsmCheck_A, + u_esc_timer.u_state_regs, + esc_tx_o[0].esc_p & esc_tx_o[1].esc_p & esc_tx_o[2].esc_p & esc_tx_o[3].esc_p) + end + + //////////////////////// + // Escalation Senders // + //////////////////////// + + logic [N_ESC_SEV-1:0] esc_sig_req; + logic [N_ESC_SEV-1:0] esc_integfail; + logic [N_ESC_SEV-1:0][N_CLASSES-1:0] esc_sig_req_trsp; + + for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_esc_sev + for (genvar j = 0; j < N_CLASSES; j++) begin : gen_transp + assign esc_sig_req_trsp[k][j] = class_esc_sig_req[j][k]; + end + + assign esc_sig_req[k] = |esc_sig_req_trsp[k]; + // SEC_CM: ESC_RX.INTERSIG.BKGN_CHK + // Note: This countermeasure is actually implemented on the receiver side. We currently cannot + // put this RTL label inside that module due to the way our countermeasure annotation check + // script discovers the RTL files. The label is thus put here. Please refer to + // prim_esc_receiver.sv for the actual implementation of this mechanism. + prim_esc_sender # ( + .SkewCycles(AlertSkewCycles) + ) u_esc_sender ( + .clk_i, + .rst_ni, + .ping_req_i ( esc_ping_req[k] ), + .ping_ok_o ( esc_ping_ok[k] ), + .integ_fail_o ( esc_integfail[k] ), + .esc_req_i ( esc_sig_req[k] ), + // SEC_CM: ESC.INTERSIG.DIFF + .esc_rx_i ( esc_rx_i[k] ), + .esc_tx_o ( esc_tx_o[k] ) + ); + end + + assign loc_alert_trig[3] = |esc_integfail; + + logic unused_params; + assign unused_params = ^{EscNumSeverities, EscPingCountWidth}; + + //////////////// + // Assertions // + //////////////// + + // check whether all outputs have a good known state after reset + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(IrqAKnownO_A, intr_classa_o) + `ASSERT_KNOWN(IrqBKnownO_A, intr_classb_o) + `ASSERT_KNOWN(IrqCKnownO_A, intr_classc_o) + `ASSERT_KNOWN(IrqDKnownO_A, intr_classd_o) + `ASSERT_KNOWN(CrashdumpKnownO_A, crashdump_o) + `ASSERT_KNOWN(AckPKnownO_A, alert_rx_o) + `ASSERT_KNOWN(EscPKnownO_A, esc_tx_o) + `ASSERT_KNOWN(EdnKnownO_A, edn_o) + + // this restriction is due to specifics in the ping selection mechanism + `ASSERT_INIT(CheckNAlerts, NAlerts < (256 - N_CLASSES)) + `ASSERT_INIT(CheckEscCntDw, EscCntDw <= 32) + `ASSERT_INIT(CheckAccuCntDw, AccuCntDw <= 32) + `ASSERT_INIT(CheckNClasses, N_CLASSES <= 8) + `ASSERT_INIT(CheckNEscSev, N_ESC_SEV <= 8) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ERR(RegWeOnehotCheck_A, + u_reg_wrap.u_reg, loc_alert_trig[4]) +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_accu.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_accu.sv new file mode 100644 index 00000000000..f43ae162ffb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_accu.sv @@ -0,0 +1,65 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module accumulates incoming alert triggers. Once the current accumulator +// value is greater or equal the accumulator threshold, the next occurence of +// class_trig_i will trigger escalation. +// +// Note that the accumulator is implemented using a saturation counter which +// does not wrap around. +// + +`include "prim_assert.sv" + +module alert_handler_accu import alert_handler_pkg::*; ( + input clk_i, + input rst_ni, + input class_en_i, // class enable + input clr_i, // clear the accumulator + input class_trig_i, // increments the accu + input [AccuCntDw-1:0] thresh_i, // escalation trigger threshold + output logic [AccuCntDw-1:0] accu_cnt_o, // output of current accu value + output logic accu_trig_o, // escalation trigger output + output logic accu_fail_o // asserted if the tandem accu counters are not equal +); + + logic trig_gated, accu_en; + assign trig_gated = class_trig_i & class_en_i; + assign accu_en = trig_gated && !(&accu_cnt_o); + + // SEC_CM: ACCU.CTR.REDUN + // We employ two redundant counters to guard against FI attacks. + // If any of the two is glitched and the two counter states do not agree, + // the check_fail_o signal is asserted which will move the corresponding escalation + // FSM into a terminal error state where all escalation actions will be permanently asserted. + prim_count #( + .Width(AccuCntDw), + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. + .EnableAlertTriggerSVA(0) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i, + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(accu_en), + .decr_en_i(1'b0), + .step_i(AccuCntDw'(1)), + .cnt_o(accu_cnt_o), + .commit_i(1'b1), + .cnt_after_commit_o(), + .err_o(accu_fail_o) + ); + + assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated; + + //////////////// + // Assertions // + //////////////// + + `ASSERT(DisabledNoTrigFwd_A, !class_en_i |-> !accu_trig_o) + `ASSERT(DisabledNoTrigBkwd_A, accu_trig_o |-> class_en_i) + `ASSERT(CountSaturateStable_A, accu_cnt_o == {AccuCntDw{1'b1}} |=> $stable(accu_cnt_o)) +endmodule : alert_handler_accu diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_class.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_class.sv new file mode 100644 index 00000000000..f3a8dc39fad --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_class.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module gates the alert triggers with their enable bits, and correctly bins +// the enabled alerts into the class that they have been assigned to. The module +// produces the alert cause and class trigger signals. +// + +module alert_handler_class import alert_handler_pkg::*; ( + input [NAlerts-1:0] alert_trig_i, // alert trigger + input [N_LOC_ALERT-1:0] loc_alert_trig_i, // alert trigger + input [NAlerts-1:0] alert_en_i, // alert enable + input [N_LOC_ALERT-1:0] loc_alert_en_i, // alert enable + input [NAlerts-1:0] [CLASS_DW-1:0] alert_class_i, // class assignment + input [N_LOC_ALERT-1:0][CLASS_DW-1:0] loc_alert_class_i, // class assignment + + output logic [NAlerts-1:0] alert_cause_o, // alert cause + output logic [N_LOC_ALERT-1:0] loc_alert_cause_o, // alert cause + output logic [N_CLASSES-1:0] class_trig_o // class triggered +); + + // assign alert cause + assign alert_cause_o = alert_en_i & alert_trig_i; + assign loc_alert_cause_o = loc_alert_en_i & loc_alert_trig_i; + + // classification mapping + logic [N_CLASSES-1:0][NAlerts-1:0] class_masks; + logic [N_CLASSES-1:0][N_LOC_ALERT-1:0] loc_class_masks; + + // this is basically an address to onehot0 decoder + always_comb begin : p_class_mask + class_masks = '0; + loc_class_masks = '0; + for (int unsigned kk = 0; kk < NAlerts; kk++) begin + class_masks[alert_class_i[kk]][kk] = 1'b1; + end + for (int unsigned kk = 0; kk < N_LOC_ALERT; kk++) begin + loc_class_masks[loc_alert_class_i[kk]][kk] = 1'b1; + end + end + + // mask and OR reduction, followed by class enable gating + for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classifier + assign class_trig_o[k] = (|{ alert_cause_o & class_masks[k], + loc_alert_cause_o & loc_class_masks[k] }); + end + +endmodule : alert_handler_class diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv new file mode 100644 index 00000000000..f05d5fc6641 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_esc_timer.sv @@ -0,0 +1,432 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements the escalation timer, which times the four escalation +// phases. There are two mechanisms that can trigger the escalation protocol: +// +// 1) via accum_trigger_i, which will be asserted once the accumulator value +// exceeds a programmable amount of alert occurences. +// +// 2) via an interrupt timeout, if this is enabled. If this functionality is +// enabled, the internal escalation counter is reused to check whether the +// interrupt times out. If it does time out, the outcome is the same as if +// accum_trigger_i where asserted. +// +// Note that escalation always takes precedence over the interrupt timeout. +// + +`include "prim_assert.sv" + +module alert_handler_esc_timer import alert_handler_pkg::*; ( + input clk_i, + input rst_ni, + input en_i, // enables timeout/escalation + input clr_i, // aborts escalation + input accu_trig_i, // this triggers escalation + input accu_fail_i, // this moves the FSM into a terminal error state + input timeout_en_i, // enables timeout + input [EscCntDw-1:0] timeout_cyc_i, // interrupt timeout. 0 = disabled + input [N_ESC_SEV-1:0] esc_en_i, // escalation signal enables + input [N_ESC_SEV-1:0] + [PHASE_DW-1:0] esc_map_i, // escalation signal / phase map + input [N_PHASES-1:0] + [EscCntDw-1:0] phase_cyc_i, // cycle counts of individual phases + input [PHASE_DW-1:0] crashdump_phase_i, // determines when to assert latch_crashdump_o + output logic latch_crashdump_o, // asserted when entering escalation + output logic esc_trig_o, // asserted if escalation triggers + output logic [EscCntDw-1:0] esc_cnt_o, // current timeout / escalation count + output logic [N_ESC_SEV-1:0] esc_sig_req_o, // escalation signal outputs + // current state output + // 000: idle, 001: irq timeout counting 100: phase0, 101: phase1, 110: phase2, 111: phase3 + output cstate_e esc_state_o +); + + //////////////////// + // Tandem Counter // + //////////////////// + + // We employ two redundant counters to guard against FI attacks. + // If any of the two is glitched and the two counter states do not agree, + // the FSM below is moved into a terminal error state and escalation actions + // are permanently asserted. + logic cnt_en, cnt_clr, cnt_error; + + // SEC_CM: ESC_TIMER.CTR.REDUN + prim_count #( + .Width(EscCntDw), + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. + .EnableAlertTriggerSVA(0), + // Pass a parameter to disable coverage for some assertions that are unreachable because + // decr_en_i is tied to zero. + .PossibleActions(prim_count_pkg::Clr | + prim_count_pkg::Set | + prim_count_pkg::Incr) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr && !cnt_en), + .set_i(cnt_clr && cnt_en), + .set_cnt_i(EscCntDw'(1)), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(EscCntDw'(1)), + .commit_i(1'b1), + .cnt_o(esc_cnt_o), + .cnt_after_commit_o(), + .err_o(cnt_error) + ); + + // threshold test, the thresholds are muxed further below + // depending on the current state + logic cnt_ge; + logic [EscCntDw-1:0] thresh; + assign cnt_ge = (esc_cnt_o >= thresh); + + ////////////// + // Main FSM // + ////////////// + + logic [N_PHASES-1:0] phase_oh; + + // SEC_CM: ESC_TIMER.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \ + // -s 784905746 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (46.43%) + // 6: |||||||||||||||||||| (46.43%) + // 7: ||| (7.14%) + // 8: -- + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 7 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 9 + // + localparam int StateWidth = 10; + typedef enum logic [StateWidth-1:0] { + IdleSt = 10'b1011011010, + TimeoutSt = 10'b0000100110, + Phase0St = 10'b1110000101, + Phase1St = 10'b0101010100, + Phase2St = 10'b0000011001, + Phase3St = 10'b1001100001, + TerminalSt = 10'b1101111111, + FsmErrorSt = 10'b0111101000 + } state_e; + + logic fsm_error; + state_e state_d, state_q; + + always_comb begin : p_fsm + // default + state_d = state_q; + esc_state_o = Idle; + cnt_en = 1'b0; + cnt_clr = 1'b0; + esc_trig_o = 1'b0; + phase_oh = '0; + thresh = timeout_cyc_i; + fsm_error = 1'b0; + latch_crashdump_o = 1'b0; + + unique case (state_q) + // wait for an escalation trigger or an alert trigger + // the latter will trigger an interrupt timeout + IdleSt: begin + cnt_clr = 1'b1; + esc_state_o = Idle; + + if (accu_trig_i && en_i && !clr_i) begin + state_d = Phase0St; + cnt_en = 1'b1; + esc_trig_o = 1'b1; + // the counter is zero in this state. so if the + // timeout count is zero (==disabled), cnt_ge will be true. + end else if (timeout_en_i && !cnt_ge && en_i) begin + cnt_en = 1'b1; + state_d = TimeoutSt; + end + end + // we are in interrupt timeout state + // in case an escalation comes in, we immediately have to + // switch over to the first escalation phase. + // in case the interrupt timeout hits it's cycle count, we + // also enter escalation phase0. + // ongoing timeouts can always be cleared. + TimeoutSt: begin + esc_state_o = Timeout; + + if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin + state_d = Phase0St; + cnt_en = 1'b1; + cnt_clr = 1'b1; + esc_trig_o = 1'b1; + // the timeout enable is connected to the irq state + // if that is cleared, stop the timeout counter + end else if (timeout_en_i) begin + cnt_en = 1'b1; + end else begin + state_d = IdleSt; + cnt_clr = 1'b1; + end + end + // note: autolocking the clear signal is done in the regfile + Phase0St: begin + cnt_en = 1'b1; + phase_oh[0] = 1'b1; + thresh = phase_cyc_i[0]; + esc_state_o = Phase0; + latch_crashdump_o = (crashdump_phase_i == 2'b00); + + if (clr_i) begin + state_d = IdleSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end else if (cnt_ge) begin + state_d = Phase1St; + cnt_clr = 1'b1; + cnt_en = 1'b1; + end + end + Phase1St: begin + cnt_en = 1'b1; + phase_oh[1] = 1'b1; + thresh = phase_cyc_i[1]; + esc_state_o = Phase1; + latch_crashdump_o = (crashdump_phase_i == 2'b01); + + if (clr_i) begin + state_d = IdleSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end else if (cnt_ge) begin + state_d = Phase2St; + cnt_clr = 1'b1; + cnt_en = 1'b1; + end + end + Phase2St: begin + cnt_en = 1'b1; + phase_oh[2] = 1'b1; + thresh = phase_cyc_i[2]; + esc_state_o = Phase2; + latch_crashdump_o = (crashdump_phase_i == 2'b10); + + + if (clr_i) begin + state_d = IdleSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end else if (cnt_ge) begin + state_d = Phase3St; + cnt_clr = 1'b1; + end + end + Phase3St: begin + cnt_en = 1'b1; + phase_oh[3] = 1'b1; + thresh = phase_cyc_i[3]; + esc_state_o = Phase3; + latch_crashdump_o = (crashdump_phase_i == 2'b11); + + if (clr_i) begin + state_d = IdleSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end else if (cnt_ge) begin + state_d = TerminalSt; + cnt_clr = 1'b1; + cnt_en = 1'b0; + end + end + // final, terminal state after escalation. + // if clr is locked down, only a system reset + // will get us out of this state + TerminalSt: begin + cnt_clr = 1'b1; + esc_state_o = Terminal; + if (clr_i) begin + state_d = IdleSt; + end + end + // error state, only reached if the FSM has been + // glitched. in this state, we trigger all escalation + // actions at once. + FsmErrorSt: begin + esc_state_o = FsmError; + fsm_error = 1'b1; + end + // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC + // catch glitches. + default: begin + state_d = FsmErrorSt; + esc_state_o = FsmError; + fsm_error = 1'b1; + end + endcase + + // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC + // if any of the duplicate counter pairs has an inconsistent state + // we move into the terminal FSM error state. + if (accu_fail_i || cnt_error) begin + state_d = FsmErrorSt; + fsm_error = 1'b1; + end + end + + logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh; + for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map + // generate configuration mask for escalation enable signals + assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k]; + // mask reduce current phase state vector + // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC + assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error; + end + + /////////////////// + // FSM Registers // + /////////////////// + + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. The + // EnableAlertTriggerSVA parameter is therefore set to 0. + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0) + + //////////////// + // Assertions // + //////////////// + + // a clear should always bring us back to idle + `ASSERT(CheckClr_A, + !accu_fail_i && + clr_i && + !(state_q inside {IdleSt, TimeoutSt, FsmErrorSt}) + |=> + state_q == IdleSt) + // if currently in idle and not enabled, must remain here + `ASSERT(CheckEn_A, + !accu_fail_i && + state_q == IdleSt && + !en_i + |=> + state_q == IdleSt) + // Check if accumulation trigger correctly captured + `ASSERT(CheckAccumTrig0_A, + !accu_fail_i && + accu_trig_i && + state_q == IdleSt && + en_i && + !clr_i + |=> + state_q == Phase0St) + `ASSERT(CheckAccumTrig1_A, + !accu_fail_i && + accu_trig_i && + state_q == TimeoutSt && + en_i && + !clr_i + |=> + state_q == Phase0St) + // Check if timeout correctly captured + `ASSERT(CheckTimeout0_A, + !accu_fail_i && + state_q == IdleSt && + timeout_en_i && + en_i && + timeout_cyc_i != 0 && + !accu_trig_i + |=> + state_q == TimeoutSt) + `ASSERT(CheckTimeoutSt1_A, + !accu_fail_i && + state_q == TimeoutSt && + timeout_en_i && + esc_cnt_o < timeout_cyc_i && + !accu_trig_i + |=> + state_q == TimeoutSt) + `ASSERT(CheckTimeoutSt2_A, + !accu_fail_i && + state_q == TimeoutSt && + !timeout_en_i && + !accu_trig_i + |=> + state_q == IdleSt) + // Check if timeout correctly triggers escalation + `ASSERT(CheckTimeoutStTrig_A, + !accu_fail_i && + state_q == TimeoutSt && + timeout_en_i && + esc_cnt_o == timeout_cyc_i + |=> + state_q == Phase0St) + // Check whether escalation phases are correctly switched + `ASSERT(CheckPhase0_A, + !accu_fail_i && + state_q == Phase0St && + !clr_i && + esc_cnt_o >= phase_cyc_i[0] + |=> + state_q == Phase1St) + `ASSERT(CheckPhase1_A, + !accu_fail_i && + state_q == Phase1St && + !clr_i && + esc_cnt_o >= phase_cyc_i[1] + |=> + state_q == Phase2St) + `ASSERT(CheckPhase2_A, + !accu_fail_i && + state_q == Phase2St && + !clr_i && + esc_cnt_o >= phase_cyc_i[2] + |=> + state_q == Phase3St) + `ASSERT(CheckPhase3_A, + !accu_fail_i && + state_q == Phase3St && + !clr_i && + esc_cnt_o >= phase_cyc_i[3] + |=> + state_q == TerminalSt) + `ASSERT(AccuFailToFsmError_A, + accu_fail_i + |=> + state_q == FsmErrorSt) + `ASSERT(ErrorStIsTerminal_A, + state_q == FsmErrorSt + |=> + state_q == FsmErrorSt) + `ASSERT(ErrorStAllEscAsserted_A, + state_q == FsmErrorSt + |-> + esc_sig_req_o == '1) + +`ifdef INC_ASSERT + // Check that our internal FSM matches the state index that we're exposing with esc_state_o. The + // StateEncodings parameter does the mapping to match. (Practically speaking, this is just adding + // "St" to each name so e.g. Idle gets mapped to IdleSt). + parameter logic [StateWidth-1:0] StateEncodings [8] = '{IdleSt, + TimeoutSt, + FsmErrorSt, + TerminalSt, + Phase0St, + Phase1St, + Phase2St, + Phase3St}; + `ASSERT(EscStateOut_A, state_q == StateEncodings[esc_state_o]) +`endif + +endmodule : alert_handler_esc_timer diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_lpg_ctrl.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_lpg_ctrl.sv new file mode 100644 index 00000000000..1e88e143162 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_lpg_ctrl.sv @@ -0,0 +1,93 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module gathers and synchronizes the clock gating and reset indication signals for all +// low-power groups (LPGs), synchronizes them to the alert handler clock domain. The clock gating +// and reset indication signals are then logically OR'ed to produce one multibit value for each +// LPG. The LPG multibit values are then mapped to the alert channels using the LpgMap parameter, +// and each multibit output value is buffered independently. +// + +`include "prim_assert.sv" + +module alert_handler_lpg_ctrl import alert_handler_pkg::*; ( + input clk_i, + input rst_ni, + // Low power clk and rst indication signals. + input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_cg_en_i, + input prim_mubi_pkg::mubi4_t [NLpg-1:0] lpg_rst_en_i, + // Init requests going to the individual alert channels. + output prim_mubi_pkg::mubi4_t [NAlerts-1:0] alert_init_trig_o +); + + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::mubi4_or_hi; + import prim_mubi_pkg::MuBi4True; + + /////////////////////////////////////////////////// + // Aggregate multibit indication signals per LPG // + /////////////////////////////////////////////////// + + mubi4_t [NLpg-1:0] synced_lpg_cg_en, synced_lpg_rst_en, lpg_init_trig; + for (genvar k = 0; k < NLpg; k++) begin : gen_lpgs + prim_mubi4_sync #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sync_cg_en ( + .clk_i, + .rst_ni, + .mubi_i(lpg_cg_en_i[k]), + .mubi_o(synced_lpg_cg_en[k:k]) + ); + prim_mubi4_sync #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sync_rst_en ( + .clk_i, + .rst_ni, + .mubi_i(lpg_rst_en_i[k]), + .mubi_o(synced_lpg_rst_en[k:k]) + ); + + // Perform a logical OR operation of the multibit life cycle signals. + // I.e., if any of the incoming multibit signals is On, the output will also be On. + // Otherwise, the output may have any value other than On. + assign lpg_init_trig[k] = mubi4_or_hi(synced_lpg_cg_en[k], synced_lpg_rst_en[k]); + end + + ////////////////////////////////// + // LPG to Alert Channel Mapping // + ////////////////////////////////// + + // select the correct lpg for the alert channel at index j and buffer the multibit signal for each + // alert channel. + for (genvar j=0; j < NAlerts; j++) begin : gen_alert_map + prim_mubi4_sync #( + .AsyncOn(0) // no sync flops + ) u_prim_mubi4_sync_lpg_en ( + .clk_i, + .rst_ni, + .mubi_i(lpg_init_trig[LpgMap[j]]), + .mubi_o({alert_init_trig_o[j]}) + ); + end + + if (NLpg > 1) begin : gen_read_unused_lpg + // explicitly read all unused lpg triggers to avoid lint errors. + // Only needed when there are at least two LPGs. + logic [NLpg-1:0] lpg_used; + logic unused_lpg_init_trig; + always_comb begin + lpg_used = '0; + unused_lpg_init_trig = 1'b0; + for (int j=0; j < NAlerts; j++) begin + lpg_used[LpgMap[j]] |= 1'b1; + end + for (int k=0; k < NLpg; k++) begin + if (!lpg_used) begin + unused_lpg_init_trig ^= ^lpg_init_trig[k]; + end + end + end + end + +endmodule : alert_handler_lpg_ctrl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv new file mode 100644 index 00000000000..b273d97b7eb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_ping_timer.sv @@ -0,0 +1,442 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements the ping mechanism. Once enabled, this module uses an +// LFSR-based PRNG to +// +// a) determine the next peripheral index to be pinged (can be an alert receiver or an +// escalation sender). If it is detected that a particular peripheral is disabled, +// another index will be drawn from the PRNG. +// +// b) determine the amount of pause cycles to wait before pinging the peripheral selected in a). +// +// Once the ping timer waited for the amount of pause cycles determined in b), it asserts +// the ping enable signal of the peripheral determined in a). If that peripheral does +// not respond within the ping timeout window, an internal alert will be raised. +// +// Further, if a spurious ping_ok signal is detected (i.e., a ping ok that has not been +// requested), the ping timer will also raise an internal alert. +// + +`include "prim_assert.sv" + +module alert_handler_ping_timer import alert_handler_pkg::*; #( + // Compile time random constants, to be overriden by topgen. + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, + // Enable this for DV, disable this for long LFSRs in FPV + parameter bit MaxLenSVA = 1'b1, + // Can be disabled in cases where entropy + // inputs are unused in order to not distort coverage + // (the SVA will be unreachable in such cases) + parameter bit LockupSVA = 1'b1 +) ( + input clk_i, + input rst_ni, + output logic edn_req_o, // request to EDN + input edn_ack_i, // ack from EDN + input [LfsrWidth-1:0] edn_data_i, // from EDN + input en_i, // enable ping testing + input [NAlerts-1:0] alert_ping_en_i, // determines which alerts to ping + input [PING_CNT_DW-1:0] ping_timeout_cyc_i, // timeout in cycles + input [PING_CNT_DW-1:0] wait_cyc_mask_i, // mask to shorten the counters in DV / FPV + output logic [NAlerts-1:0] alert_ping_req_o, // request to alert receivers + output logic [N_ESC_SEV-1:0] esc_ping_req_o, // request to esc senders + input [NAlerts-1:0] alert_ping_ok_i, // response from alert receivers + input [N_ESC_SEV-1:0] esc_ping_ok_i, // response from esc senders + output logic alert_ping_fail_o, // any of the alert receivers failed + output logic esc_ping_fail_o // any of the esc senders failed +); + + localparam int unsigned IdDw = $clog2(NAlerts); + + // Entropy reseeding is triggered every time this counter expires. + // The expected wait time between pings is 2**(PING_CNT_DW-1) on average. + // We do not need to reseed the LFSR very often, and the constant below is chosen + // such that on average the LFSR is reseeded every 16th ping. + localparam int unsigned ReseedLfsrExtraBits = 3; + localparam int unsigned ReseedLfsrWidth = PING_CNT_DW + ReseedLfsrExtraBits; + + // The number of bits needed for an index into the esc senders + localparam int unsigned EscSenderIdxWidth = $clog2(N_ESC_SEV); + + // A few smoke checks for the DV mask: + // 1) make sure the value is a right-aligned mask. + // this can be done by checking that mask+1 is a power of 2. + // 2) also make sure that the value is always >= 0x7. + `ASSERT(WaitCycMaskMin_A, wait_cyc_mask_i >= 'h7) + `ASSERT(WaitCycMaskIsRightAlignedMask_A, $onehot(32'(wait_cyc_mask_i) + 1)) + + //////////////////// + // Reseed counter // + //////////////////// + + logic reseed_en; + logic [ReseedLfsrWidth-1:0] reseed_timer_d, reseed_timer_q; + + assign reseed_timer_d = (reseed_timer_q > '0) ? reseed_timer_q - 1'b1 : + (reseed_en) ? {wait_cyc_mask_i, + {ReseedLfsrExtraBits{1'b1}}} : '0; + assign edn_req_o = (reseed_timer_q == '0); + assign reseed_en = edn_req_o & edn_ack_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + reseed_timer_q <= '0; + end else begin + reseed_timer_q <= reseed_timer_d; + end + end + + /////////////////////////// + // Tandem LFSR Instances // + /////////////////////////// + + logic cnt_set, lfsr_err; + logic [LfsrWidth-1:0] entropy; + logic [PING_CNT_DW + IdDw - 1:0] lfsr_state; + assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0; + + // SEC_CM: PING_TIMER.LFSR.REDUN + // We employ two redundant LFSRs to guard against FI attacks. + // If any of the two is glitched and the two LFSR states do not agree, + // the FSM below is moved into a terminal error state and all ping alerts + // are permanently asserted. + prim_double_lfsr #( + .LfsrDw ( LfsrWidth ), + .EntropyDw ( LfsrWidth ), + .StateOutDw ( PING_CNT_DW + IdDw ), + .DefaultSeed ( RndCnstLfsrSeed ), + .StatePermEn ( 1'b1 ), + .StatePerm ( RndCnstLfsrPerm ), + .MaxLenSVA ( MaxLenSVA ), + .LockupSVA ( LockupSVA ), + .ExtSeedSVA ( 1'b0 ), // ext seed is unused + .EnableAlertTriggerSVA ( 1'b0 ) + ) u_prim_double_lfsr ( + .clk_i, + .rst_ni, + .seed_en_i ( 1'b0 ), + .seed_i ( '0 ), + .lfsr_en_i ( reseed_en || cnt_set ), + .entropy_i ( entropy ), + .state_o ( lfsr_state ), + .err_o ( lfsr_err ) + ); + + logic [IdDw-1:0] id_to_ping_d, id_to_ping_q; + // The subtraction below ensures that the alert ID is always in range. If + // all alerts are enabled, an alert ID drawn in this way will always be + // valid. This comes at the cost of a bias towards certain alert IDs that + // will be pinged twice as often on average - but it ensures that we have + // less alert IDs that need to be skipped since they are invalid. + assign id_to_ping_d = (lfsr_state[PING_CNT_DW +: IdDw] >= NAlerts) ? + lfsr_state[PING_CNT_DW +: IdDw] - NAlerts : + lfsr_state[PING_CNT_DW +: IdDw]; + + // we need to hold the ID stable while the ping is ongoing since this will result in + // spurious ping responses otherwise. + always_ff @(posedge clk_i or negedge rst_ni) begin : p_id_reg + if (!rst_ni) begin + id_to_ping_q <= '0; + end else begin + if (cnt_set) begin + id_to_ping_q <= id_to_ping_d; + end + end + end + + // align the enable mask with powers of two for the indexing operation below. + logic [2**IdDw-1:0] enable_mask; + assign enable_mask = (2**IdDw)'(alert_ping_en_i); + + // check if the randomly drawn alert ID is actually valid and the alert is enabled + logic id_vld; + assign id_vld = enable_mask[id_to_ping_q]; + + ////////////////////////////////// + // Escalation Counter Instances // + ////////////////////////////////// + + // As opposed to the alert ID, the escalation sender ID to be pinged is not drawn at random. + // Rather, we cycle through the escalation senders one by one in a deterministic fashion. + // This allows us to provide guarantees needed for the ping timeout / auto escalation feature + // implemented at the escalation receiver side. + // + // In particular, with N_ESC_SEV escalation senders in the design, we can guarantee + // that each escalation channel will be pinged at least once every + // + // N_ESC_SEV x (NUM_WAIT_COUNT + NUM_TIMEOUT_COUNT) x 2**PING_CNT_DW + // + // cycles - independently of the reseeding operation. + // + // - N_ESC_SEV: # escalation channels to ping. + // - NUM_WAIT_COUNT: # wait counts between subsequent escalation channel pings. + // - NUM_TIMEOUT_COUNT: # timeout counts between subsequent escalation channel pings. + // - 2**PING_CNT_DW: # maximum counter value. + // + // This guarantee is used inside the escalation receivers to monitor the pings sent out by the + // alert handler. I.e., once the alert handler has started to send out pings, each escalation + // receiver employs a timeout window within which it expects the next ping to arrive. If + // escalation pings cease to arrive at an escalation receiver for any reason, this will + // automatically trigger the associated escalation countermeasure. + // + // In order to have enough margin, the escalation receiver timeout counters use a threshold that + // is 4x higher than the value calculated above. With N_ESC_SEV = 4, PING_CNT_DW = 16 and + // NUM_WAIT_COUNT = NUM_TIMEOUT_COUNT = 2 this amounts to a 22bit timeout threshold. + // + // We employ two redundant counters to guard against FI attacks. + // If any of the two is glitched and the two counter states do not agree, + // the FSM below is moved into a terminal error state and all ping alerts + // are permanently asserted. + + logic esc_cnt_en, esc_cnt_clr, esc_cnt_error; + logic [EscSenderIdxWidth-1:0] esc_cnt; + assign esc_cnt_clr = (esc_cnt >= EscSenderIdxWidth'(N_ESC_SEV-1)) && esc_cnt_en; + + // SEC_CM: PING_TIMER.CTR.REDUN + prim_count #( + .Width(EscSenderIdxWidth), + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. + .EnableAlertTriggerSVA(0), + // Pass a parameter to disable coverage for some assertions that are unreachable because set_i + // and decr_en_i are tied to zero. + .PossibleActions(prim_count_pkg::Clr | + prim_count_pkg::Incr) + ) u_prim_count_esc_cnt ( + .clk_i, + .rst_ni, + .clr_i(esc_cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(esc_cnt_en), + .decr_en_i(1'b0), + .step_i(EscSenderIdxWidth'(1)), + .commit_i(1'b1), + .cnt_o(esc_cnt), + .cnt_after_commit_o(), + .err_o(esc_cnt_error) + ); + + ///////////////////////////// + // Timer Counter Instances // + ///////////////////////////// + + // We employ two redundant counters to guard against FI attacks. + // If any of the two is glitched and the two counter states do not agree, + // the FSM below is moved into a terminal error state and all ping alerts + // are permanently asserted. + logic [PING_CNT_DW-1:0] cnt, cnt_setval; + logic wait_cnt_set, timeout_cnt_set, timer_expired, cnt_error; + assign timer_expired = (cnt == '0); + assign cnt_set = wait_cnt_set || timeout_cnt_set; + + // SEC_CM: PING_TIMER.CTR.REDUN + prim_count #( + .Width(PING_CNT_DW), + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. + .EnableAlertTriggerSVA(0), + // Pass a parameter to disable coverage for some assertions that are unreachable because clr_i + // and incr_en_i are tied to zero. + .PossibleActions(prim_count_pkg::Set | + prim_count_pkg::Decr) + ) u_prim_count_cnt ( + .clk_i, + .rst_ni, + .clr_i(1'b0), + .set_i(cnt_set), + .set_cnt_i(cnt_setval), + .incr_en_i(1'b0), + .decr_en_i(1'b1), // we are counting down here. + .step_i(PING_CNT_DW'(1'b1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_error) + ); + + // the constant offset ensures a minimum cycle spacing between pings. + logic unused_bits; + logic [PING_CNT_DW-1:0] wait_cyc; + assign wait_cyc = (lfsr_state[PING_CNT_DW-1:0] | PING_CNT_DW'(3'b100)); + assign unused_bits = lfsr_state[2]; + + // note that the masks are used for DV/FPV only in order to reduce the state space. + assign cnt_setval = (wait_cnt_set) ? (wait_cyc & wait_cyc_mask_i) : ping_timeout_cyc_i; + + //////////////////////////// + // Ping and Timeout Logic // + //////////////////////////// + + logic alert_ping_en, esc_ping_en; + logic spurious_alert_ping, spurious_esc_ping; + + // generate ping enable vector + assign alert_ping_req_o = NAlerts'(alert_ping_en) << id_to_ping_q; + assign esc_ping_req_o = N_ESC_SEV'(esc_ping_en) << esc_cnt; + + // under normal operation, these signals should never be asserted. + // we place hand instantiated buffers here such that these signals are not + // optimized away during synthesis (these buffers will receive a keep or size_only + // attribute in our Vivado and DC synthesis flows). + prim_buf u_prim_buf_spurious_alert_ping ( + .in_i(|(alert_ping_ok_i & ~alert_ping_req_o)), + .out_o(spurious_alert_ping) + ); + prim_buf u_prim_buf_spurious_esc_ping ( + .in_i(|(esc_ping_ok_i & ~esc_ping_req_o)), + .out_o(spurious_esc_ping) + ); + + // SEC_CM: PING_TIMER.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 6 -n 9 \ + // -s 728582219 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 6 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + InitSt = 9'b011001011, + AlertWaitSt = 9'b110000000, + AlertPingSt = 9'b101110001, + EscWaitSt = 9'b010110110, + EscPingSt = 9'b000011101, + FsmErrorSt = 9'b101101110 + } state_e; + + state_e state_d, state_q; + + always_comb begin : p_fsm + // default + state_d = state_q; + wait_cnt_set = 1'b0; + timeout_cnt_set = 1'b0; + esc_cnt_en = 1'b0; + alert_ping_en = 1'b0; + esc_ping_en = 1'b0; + // this captures spurious ping responses + alert_ping_fail_o = spurious_alert_ping; + esc_ping_fail_o = spurious_esc_ping; + + unique case (state_q) + // wait until activated + // we never return to this state + // once activated! + InitSt: begin + if (en_i) begin + state_d = AlertWaitSt; + wait_cnt_set = 1'b1; + end + end + // wait for random amount of cycles + AlertWaitSt: begin + if (timer_expired) begin + state_d = AlertPingSt; + timeout_cnt_set = 1'b1; + end + end + // SEC_CM: ALERT_RX.INTERSIG.BKGN_CHK + // send out an alert ping request and wait for a ping + // response or a ping timeout (whatever comes first). + // if the alert ID is not valid, we drop the request and + // proceed to the next ping. + AlertPingSt: begin + alert_ping_en = id_vld; + if (timer_expired || |(alert_ping_ok_i & alert_ping_req_o) || !id_vld) begin + state_d = EscWaitSt; + wait_cnt_set = 1'b1; + if (timer_expired) begin + alert_ping_fail_o = 1'b1; + end + end + end + // wait for random amount of cycles + EscWaitSt: begin + if (timer_expired) begin + state_d = EscPingSt; + timeout_cnt_set = 1'b1; + end + end + // SEC_CM: ESC_TX.INTERSIG.BKGN_CHK + // send out an escalation ping request and wait for a ping + // response or a ping timeout (whatever comes first) + EscPingSt: begin + esc_ping_en = 1'b1; + if (timer_expired || |(esc_ping_ok_i & esc_ping_req_o)) begin + state_d = AlertWaitSt; + wait_cnt_set = 1'b1; + esc_cnt_en = 1'b1; + if (timer_expired) begin + esc_ping_fail_o = 1'b1; + end + end + end + // SEC_CM: PING_TIMER.FSM.LOCAL_ESC + // terminal FSM error state. + // if we for some reason end up in this state (e.g. malicious glitching) + // we are going to assert both ping fails continuously + FsmErrorSt: begin + alert_ping_fail_o = 1'b1; + esc_ping_fail_o = 1'b1; + end + default: begin + state_d = FsmErrorSt; + alert_ping_fail_o = 1'b1; + esc_ping_fail_o = 1'b1; + end + endcase + + // SEC_CM: PING_TIMER.FSM.LOCAL_ESC + // if the two LFSR or counter states do not agree, + // we move into the terminal state. + if (lfsr_err || cnt_error || esc_cnt_error) begin + state_d = FsmErrorSt; + alert_ping_fail_o = 1'b1; + esc_ping_fail_o = 1'b1; + end + end + + /////////////////// + // FSM Registers // + /////////////////// + + // The alert handler behaves differently than other comportable IP. I.e., instead of sending out + // an alert signal, this condition is handled internally in the alert handler. The + // EnableAlertTriggerSVA parameter is therefore set to 0. + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, InitSt, clk_i, rst_ni, 0) + + //////////////// + // Assertions // + //////////////// + + // make sure the ID width is within bounds. + `ASSERT_INIT(MaxIdDw_A, IdDw <= (LfsrWidth - PING_CNT_DW)) + + // only one module is pinged at a time. + `ASSERT(PingOH0_A, $onehot0({alert_ping_req_o, esc_ping_req_o})) + + // we should never get into the ping state without knowing which module to ping. + `ASSERT(AlertPingOH_A, alert_ping_en |-> $onehot(alert_ping_req_o)) + `ASSERT(EscPingOH_A, esc_ping_en |-> $onehot(esc_ping_req_o)) + +endmodule : alert_handler_ping_timer diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_pkg.sv new file mode 100644 index 00000000000..766f82df249 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_pkg.sv @@ -0,0 +1,101 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package alert_handler_pkg; + + // these localparams are generated based on the system top-level configuration + localparam int unsigned NAlerts = alert_handler_reg_pkg::NAlerts; // maximum 252 + localparam int unsigned EscCntDw = alert_handler_reg_pkg::EscCntDw; // maximum 32 + localparam int unsigned AccuCntDw = alert_handler_reg_pkg::AccuCntDw; // maximum 32 + localparam int unsigned NLpg = alert_handler_reg_pkg::NLpg; + localparam int unsigned NLpgWidth = alert_handler_reg_pkg::NLpgWidth; + localparam logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = alert_handler_reg_pkg::LpgMap; + // enable async transitions for specific RX/TX pairs + localparam bit [NAlerts-1:0] AsyncOn = alert_handler_reg_pkg::AsyncOn; + + // common constants, do not change + localparam int unsigned N_CLASSES = alert_handler_reg_pkg::N_CLASSES; + localparam int unsigned N_ESC_SEV = alert_handler_reg_pkg::N_ESC_SEV; + localparam int unsigned N_PHASES = alert_handler_reg_pkg::N_PHASES; + localparam int unsigned N_LOC_ALERT = alert_handler_reg_pkg::N_LOC_ALERT; + + localparam int unsigned PING_CNT_DW = alert_handler_reg_pkg::PING_CNT_DW; + localparam int unsigned PHASE_DW = alert_handler_reg_pkg::PHASE_DW; + localparam int unsigned CLASS_DW = alert_handler_reg_pkg::CLASS_DW; + + // do not change the phase encoding + typedef enum logic [2:0] {Idle = 3'b000, Timeout = 3'b001, Terminal = 3'b011, + Phase0 = 3'b100, Phase1 = 3'b101, Phase2 = 3'b110, + Phase3 = 3'b111, FsmError = 3'b010} cstate_e; + + // These LFSR parameters have been generated with + // $ util/design/gen-lfsr-seed.py --width 32 --seed 2700182644 + localparam int LfsrWidth = 32; + typedef logic [LfsrWidth-1:0] lfsr_seed_t; + typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t; + localparam lfsr_seed_t RndCnstLfsrSeedDefault = 32'he96064e5; + localparam lfsr_perm_t RndCnstLfsrPermDefault = + 160'hebd1e5d4a1cee5afdb866a9c7a0278b899020d31; + + // struct containing the current alert handler state + // can be used to gather crashdump information in HW + typedef struct packed { + // alerts + logic [NAlerts-1:0] alert_cause; // alert cause bits + logic [N_LOC_ALERT-1:0] loc_alert_cause; // local alert cause bits + // class state + logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_cnt; // current accumulator value + logic [N_CLASSES-1:0][EscCntDw-1:0] class_esc_cnt; // current escalation counter value + cstate_e [N_CLASSES-1:0] class_esc_state; // current escalation protocol state + } alert_crashdump_t; + + // Default for dangling connection + parameter alert_crashdump_t ALERT_CRASHDUMP_DEFAULT = '{ + alert_cause: '0, + loc_alert_cause: '0, + class_accum_cnt: '0, + class_esc_cnt: '0, + class_esc_state: {N_CLASSES{Idle}} + }; + + // breakout wrapper structs + typedef struct packed { + // alerts + logic [NAlerts-1:0] alert_cause; // alert cause bits + logic [N_LOC_ALERT-1:0] loc_alert_cause; // local alert cause bits + // class state + logic [N_CLASSES-1:0] class_trig; // class trigger + logic [N_CLASSES-1:0] class_esc_trig; // escalation trigger + logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_cnt; // current accumulator value + logic [N_CLASSES-1:0][EscCntDw-1:0] class_esc_cnt; // current escalation counter value + cstate_e [N_CLASSES-1:0] class_esc_state; // current escalation protocol state + } hw2reg_wrap_t; + + typedef struct packed { + // aggregated shadow reg errors (trigger internal alerts) + logic shadowed_err_update; + logic shadowed_err_storage; + // ping config + logic ping_enable; // ping timer enable + logic [PING_CNT_DW-1:0] ping_timeout_cyc; // ping timeout config + logic [NAlerts-1:0] alert_ping_en; // ping enable for alerts + // alert config + logic [N_LOC_ALERT-1:0] loc_alert_en; // alert enable + logic [N_LOC_ALERT-1:0][CLASS_DW-1:0] loc_alert_class; // alert class config + logic [NAlerts-1:0] alert_en; // alert enable + logic [NAlerts-1:0][CLASS_DW-1:0] alert_class; // alert class config + // class config + logic [N_CLASSES-1:0] class_en; // enables esc mechanisms + logic [N_CLASSES-1:0] class_clr; // clears esc/accu + logic [N_CLASSES-1:0][AccuCntDw-1:0] class_accum_thresh; // accum esc threshold + logic [N_CLASSES-1:0][EscCntDw-1:0] class_timeout_cyc; // interrupt timeout + logic [N_CLASSES-1:0][N_PHASES-1:0][EscCntDw-1:0] class_phase_cyc; // length of phases 0..3 + logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_en; // esc signal enables + logic [N_CLASSES-1:0][N_ESC_SEV-1:0][PHASE_DW-1:0] class_esc_map; // esc signal/phase map + // determines when to latch the crashdump output. + logic [N_CLASSES-1:0][PHASE_DW-1:0] class_crashdump_phase; + } reg2hw_wrap_t; + +endpackage : alert_handler_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv new file mode 100644 index 00000000000..43f399317a8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_reg_pkg.sv @@ -0,0 +1,2260 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package alert_handler_reg_pkg; + + // Param list + parameter int NAlerts = 99; + parameter int NLpg = 16; + parameter int NLpgWidth = 5; + parameter logic [NAlerts-1:0][NLpgWidth-1:0] LpgMap = { + 5'd11, + 5'd11, + 5'd9, + 5'd9, + 5'd3, + 5'd3, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd11, + 5'd15, + 5'd15, + 5'd14, + 5'd14, + 5'd13, + 5'd12, + 5'd12, + 5'd11, + 5'd10, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd9, + 5'd7, + 5'd6, + 5'd6, + 5'd6, + 5'd6, + 5'd6, + 5'd5, + 5'd4, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd3, + 5'd2, + 5'd1, + 5'd0, + 5'd0 +}; + parameter int EscCntDw = 32; + parameter int AccuCntDw = 16; + parameter logic [NAlerts-1:0] AsyncOn = { + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1, + 1'b1 +}; + parameter int N_CLASSES = 4; + parameter int N_ESC_SEV = 4; + parameter int N_PHASES = 4; + parameter int N_LOC_ALERT = 7; + parameter int PING_CNT_DW = 16; + parameter int PHASE_DW = 2; + parameter int CLASS_DW = 2; + parameter int LOCAL_ALERT_ID_ALERT_PINGFAIL = 0; + parameter int LOCAL_ALERT_ID_ESC_PINGFAIL = 1; + parameter int LOCAL_ALERT_ID_ALERT_INTEGFAIL = 2; + parameter int LOCAL_ALERT_ID_ESC_INTEGFAIL = 3; + parameter int LOCAL_ALERT_ID_BUS_INTEGFAIL = 4; + parameter int LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR = 5; + parameter int LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR = 6; + parameter int LOCAL_ALERT_ID_LAST = 6; + + // Address widths within the block + parameter int BlockAw = 11; + + // Number of registers for every interface + parameter int NumRegs = 486; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } classd; + struct packed { + logic q; + } classc; + struct packed { + logic q; + } classb; + struct packed { + logic q; + } classa; + } alert_handler_reg2hw_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic q; + } classd; + struct packed { + logic q; + } classc; + struct packed { + logic q; + } classb; + struct packed { + logic q; + } classa; + } alert_handler_reg2hw_intr_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } classd; + struct packed { + logic q; + logic qe; + } classc; + struct packed { + logic q; + logic qe; + } classb; + struct packed { + logic q; + logic qe; + } classa; + } alert_handler_reg2hw_intr_test_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_ping_timer_en_shadowed_reg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_alert_regwen_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_alert_en_shadowed_mreg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_alert_class_shadowed_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_alert_cause_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t; + + typedef struct packed { + logic q; + } alert_handler_reg2hw_loc_alert_cause_mreg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classa_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classa_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classb_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classb_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classc_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classc_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } map_e3; + struct packed { + logic [1:0] q; + } map_e2; + struct packed { + logic [1:0] q; + } map_e1; + struct packed { + logic [1:0] q; + } map_e0; + struct packed { + logic q; + } en_e3; + struct packed { + logic q; + } en_e2; + struct packed { + logic q; + } en_e1; + struct packed { + logic q; + } en_e0; + struct packed { + logic q; + } lock; + struct packed { + logic q; + } en; + } alert_handler_reg2hw_classd_ctrl_shadowed_reg_t; + + typedef struct packed { + logic q; + logic qe; + } alert_handler_reg2hw_classd_clr_shadowed_reg_t; + + typedef struct packed { + logic [15:0] q; + } alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t; + + typedef struct packed { + logic [1:0] q; + } alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t; + + typedef struct packed { + logic [31:0] q; + } alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } classd; + struct packed { + logic d; + logic de; + } classc; + struct packed { + logic d; + logic de; + } classb; + struct packed { + logic d; + logic de; + } classa; + } alert_handler_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_alert_cause_mreg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_loc_alert_cause_mreg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classa_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classa_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classa_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classa_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classb_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classb_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classb_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classb_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classc_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classc_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classc_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classc_state_reg_t; + + typedef struct packed { + logic d; + logic de; + } alert_handler_hw2reg_classd_clr_regwen_reg_t; + + typedef struct packed { + logic [15:0] d; + } alert_handler_hw2reg_classd_accum_cnt_reg_t; + + typedef struct packed { + logic [31:0] d; + } alert_handler_hw2reg_classd_esc_cnt_reg_t; + + typedef struct packed { + logic [2:0] d; + } alert_handler_hw2reg_classd_state_reg_t; + + // Register -> HW type + typedef struct packed { + alert_handler_reg2hw_intr_state_reg_t intr_state; // [1331:1328] + alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1327:1324] + alert_handler_reg2hw_intr_test_reg_t intr_test; // [1323:1316] + alert_handler_reg2hw_ping_timeout_cyc_shadowed_reg_t ping_timeout_cyc_shadowed; // [1315:1300] + alert_handler_reg2hw_ping_timer_en_shadowed_reg_t ping_timer_en_shadowed; // [1299:1299] + alert_handler_reg2hw_alert_regwen_mreg_t [98:0] alert_regwen; // [1298:1200] + alert_handler_reg2hw_alert_en_shadowed_mreg_t [98:0] alert_en_shadowed; // [1199:1101] + alert_handler_reg2hw_alert_class_shadowed_mreg_t [98:0] alert_class_shadowed; // [1100:903] + alert_handler_reg2hw_alert_cause_mreg_t [98:0] alert_cause; // [902:804] + alert_handler_reg2hw_loc_alert_en_shadowed_mreg_t [6:0] loc_alert_en_shadowed; // [803:797] + alert_handler_reg2hw_loc_alert_class_shadowed_mreg_t [6:0] + loc_alert_class_shadowed; // [796:783] + alert_handler_reg2hw_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [782:776] + alert_handler_reg2hw_classa_ctrl_shadowed_reg_t classa_ctrl_shadowed; // [775:762] + alert_handler_reg2hw_classa_clr_shadowed_reg_t classa_clr_shadowed; // [761:760] + alert_handler_reg2hw_classa_accum_thresh_shadowed_reg_t + classa_accum_thresh_shadowed; // [759:744] + alert_handler_reg2hw_classa_timeout_cyc_shadowed_reg_t classa_timeout_cyc_shadowed; // [743:712] + alert_handler_reg2hw_classa_crashdump_trigger_shadowed_reg_t + classa_crashdump_trigger_shadowed; // [711:710] + alert_handler_reg2hw_classa_phase0_cyc_shadowed_reg_t classa_phase0_cyc_shadowed; // [709:678] + alert_handler_reg2hw_classa_phase1_cyc_shadowed_reg_t classa_phase1_cyc_shadowed; // [677:646] + alert_handler_reg2hw_classa_phase2_cyc_shadowed_reg_t classa_phase2_cyc_shadowed; // [645:614] + alert_handler_reg2hw_classa_phase3_cyc_shadowed_reg_t classa_phase3_cyc_shadowed; // [613:582] + alert_handler_reg2hw_classb_ctrl_shadowed_reg_t classb_ctrl_shadowed; // [581:568] + alert_handler_reg2hw_classb_clr_shadowed_reg_t classb_clr_shadowed; // [567:566] + alert_handler_reg2hw_classb_accum_thresh_shadowed_reg_t + classb_accum_thresh_shadowed; // [565:550] + alert_handler_reg2hw_classb_timeout_cyc_shadowed_reg_t classb_timeout_cyc_shadowed; // [549:518] + alert_handler_reg2hw_classb_crashdump_trigger_shadowed_reg_t + classb_crashdump_trigger_shadowed; // [517:516] + alert_handler_reg2hw_classb_phase0_cyc_shadowed_reg_t classb_phase0_cyc_shadowed; // [515:484] + alert_handler_reg2hw_classb_phase1_cyc_shadowed_reg_t classb_phase1_cyc_shadowed; // [483:452] + alert_handler_reg2hw_classb_phase2_cyc_shadowed_reg_t classb_phase2_cyc_shadowed; // [451:420] + alert_handler_reg2hw_classb_phase3_cyc_shadowed_reg_t classb_phase3_cyc_shadowed; // [419:388] + alert_handler_reg2hw_classc_ctrl_shadowed_reg_t classc_ctrl_shadowed; // [387:374] + alert_handler_reg2hw_classc_clr_shadowed_reg_t classc_clr_shadowed; // [373:372] + alert_handler_reg2hw_classc_accum_thresh_shadowed_reg_t + classc_accum_thresh_shadowed; // [371:356] + alert_handler_reg2hw_classc_timeout_cyc_shadowed_reg_t classc_timeout_cyc_shadowed; // [355:324] + alert_handler_reg2hw_classc_crashdump_trigger_shadowed_reg_t + classc_crashdump_trigger_shadowed; // [323:322] + alert_handler_reg2hw_classc_phase0_cyc_shadowed_reg_t classc_phase0_cyc_shadowed; // [321:290] + alert_handler_reg2hw_classc_phase1_cyc_shadowed_reg_t classc_phase1_cyc_shadowed; // [289:258] + alert_handler_reg2hw_classc_phase2_cyc_shadowed_reg_t classc_phase2_cyc_shadowed; // [257:226] + alert_handler_reg2hw_classc_phase3_cyc_shadowed_reg_t classc_phase3_cyc_shadowed; // [225:194] + alert_handler_reg2hw_classd_ctrl_shadowed_reg_t classd_ctrl_shadowed; // [193:180] + alert_handler_reg2hw_classd_clr_shadowed_reg_t classd_clr_shadowed; // [179:178] + alert_handler_reg2hw_classd_accum_thresh_shadowed_reg_t + classd_accum_thresh_shadowed; // [177:162] + alert_handler_reg2hw_classd_timeout_cyc_shadowed_reg_t classd_timeout_cyc_shadowed; // [161:130] + alert_handler_reg2hw_classd_crashdump_trigger_shadowed_reg_t + classd_crashdump_trigger_shadowed; // [129:128] + alert_handler_reg2hw_classd_phase0_cyc_shadowed_reg_t classd_phase0_cyc_shadowed; // [127:96] + alert_handler_reg2hw_classd_phase1_cyc_shadowed_reg_t classd_phase1_cyc_shadowed; // [95:64] + alert_handler_reg2hw_classd_phase2_cyc_shadowed_reg_t classd_phase2_cyc_shadowed; // [63:32] + alert_handler_reg2hw_classd_phase3_cyc_shadowed_reg_t classd_phase3_cyc_shadowed; // [31:0] + } alert_handler_reg2hw_t; + + // HW -> register type + typedef struct packed { + alert_handler_hw2reg_intr_state_reg_t intr_state; // [431:424] + alert_handler_hw2reg_alert_cause_mreg_t [98:0] alert_cause; // [423:226] + alert_handler_hw2reg_loc_alert_cause_mreg_t [6:0] loc_alert_cause; // [225:212] + alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210] + alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194] + alert_handler_hw2reg_classa_esc_cnt_reg_t classa_esc_cnt; // [193:162] + alert_handler_hw2reg_classa_state_reg_t classa_state; // [161:159] + alert_handler_hw2reg_classb_clr_regwen_reg_t classb_clr_regwen; // [158:157] + alert_handler_hw2reg_classb_accum_cnt_reg_t classb_accum_cnt; // [156:141] + alert_handler_hw2reg_classb_esc_cnt_reg_t classb_esc_cnt; // [140:109] + alert_handler_hw2reg_classb_state_reg_t classb_state; // [108:106] + alert_handler_hw2reg_classc_clr_regwen_reg_t classc_clr_regwen; // [105:104] + alert_handler_hw2reg_classc_accum_cnt_reg_t classc_accum_cnt; // [103:88] + alert_handler_hw2reg_classc_esc_cnt_reg_t classc_esc_cnt; // [87:56] + alert_handler_hw2reg_classc_state_reg_t classc_state; // [55:53] + alert_handler_hw2reg_classd_clr_regwen_reg_t classd_clr_regwen; // [52:51] + alert_handler_hw2reg_classd_accum_cnt_reg_t classd_accum_cnt; // [50:35] + alert_handler_hw2reg_classd_esc_cnt_reg_t classd_esc_cnt; // [34:3] + alert_handler_hw2reg_classd_state_reg_t classd_state; // [2:0] + } alert_handler_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_STATE_OFFSET = 11'h 0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_ENABLE_OFFSET = 11'h 4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_INTR_TEST_OFFSET = 11'h 8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET = 11'h c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 10; + parameter logic [BlockAw-1:0] ALERT_HANDLER_PING_TIMER_EN_SHADOWED_OFFSET = 11'h 14; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_0_OFFSET = 11'h 18; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_1_OFFSET = 11'h 1c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_2_OFFSET = 11'h 20; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_3_OFFSET = 11'h 24; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_4_OFFSET = 11'h 28; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_5_OFFSET = 11'h 2c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_6_OFFSET = 11'h 30; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_7_OFFSET = 11'h 34; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_8_OFFSET = 11'h 38; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_9_OFFSET = 11'h 3c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_10_OFFSET = 11'h 40; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_11_OFFSET = 11'h 44; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_12_OFFSET = 11'h 48; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_13_OFFSET = 11'h 4c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_14_OFFSET = 11'h 50; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_15_OFFSET = 11'h 54; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_16_OFFSET = 11'h 58; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_17_OFFSET = 11'h 5c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_18_OFFSET = 11'h 60; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_19_OFFSET = 11'h 64; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_20_OFFSET = 11'h 68; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_21_OFFSET = 11'h 6c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_22_OFFSET = 11'h 70; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_23_OFFSET = 11'h 74; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_24_OFFSET = 11'h 78; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_25_OFFSET = 11'h 7c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_26_OFFSET = 11'h 80; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_27_OFFSET = 11'h 84; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_28_OFFSET = 11'h 88; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_29_OFFSET = 11'h 8c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_30_OFFSET = 11'h 90; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_31_OFFSET = 11'h 94; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_32_OFFSET = 11'h 98; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_33_OFFSET = 11'h 9c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_34_OFFSET = 11'h a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_35_OFFSET = 11'h a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_36_OFFSET = 11'h a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_37_OFFSET = 11'h ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_38_OFFSET = 11'h b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_39_OFFSET = 11'h b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_40_OFFSET = 11'h b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_41_OFFSET = 11'h bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_42_OFFSET = 11'h c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_43_OFFSET = 11'h c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_44_OFFSET = 11'h c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_45_OFFSET = 11'h cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_46_OFFSET = 11'h d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_47_OFFSET = 11'h d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_48_OFFSET = 11'h d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_49_OFFSET = 11'h dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_50_OFFSET = 11'h e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_51_OFFSET = 11'h e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_52_OFFSET = 11'h e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_53_OFFSET = 11'h ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_54_OFFSET = 11'h f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_55_OFFSET = 11'h f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_56_OFFSET = 11'h f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_57_OFFSET = 11'h fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_58_OFFSET = 11'h 100; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_59_OFFSET = 11'h 104; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_60_OFFSET = 11'h 108; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_61_OFFSET = 11'h 10c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_62_OFFSET = 11'h 110; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_63_OFFSET = 11'h 114; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_64_OFFSET = 11'h 118; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_65_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_66_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_67_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_68_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_69_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_70_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_71_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_72_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_73_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_74_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_75_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_76_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_77_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_78_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_79_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_80_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_81_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_82_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_83_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_84_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_85_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_86_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_87_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_88_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_89_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_90_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_91_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_92_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_93_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_94_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_95_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_96_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_97_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_98_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_69_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_70_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_71_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_72_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_73_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_74_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_75_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_76_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_77_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_78_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_79_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_80_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_81_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_82_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_83_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_84_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_85_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_86_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_87_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_88_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_89_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_90_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_91_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_92_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_93_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_94_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_95_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_96_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_97_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_SHADOWED_98_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_41_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_42_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_43_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_44_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_45_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_46_OFFSET = 11'h 574; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_47_OFFSET = 11'h 578; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_48_OFFSET = 11'h 57c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_49_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_50_OFFSET = 11'h 584; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_51_OFFSET = 11'h 588; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_52_OFFSET = 11'h 58c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_53_OFFSET = 11'h 590; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_54_OFFSET = 11'h 594; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_55_OFFSET = 11'h 598; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_56_OFFSET = 11'h 59c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_57_OFFSET = 11'h 5a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_58_OFFSET = 11'h 5a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_59_OFFSET = 11'h 5a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_60_OFFSET = 11'h 5ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_61_OFFSET = 11'h 5b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_62_OFFSET = 11'h 5b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_63_OFFSET = 11'h 5b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_64_OFFSET = 11'h 5bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_65_OFFSET = 11'h 5c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_66_OFFSET = 11'h 5c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_67_OFFSET = 11'h 5c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_68_OFFSET = 11'h 5cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_69_OFFSET = 11'h 5d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_70_OFFSET = 11'h 5d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_71_OFFSET = 11'h 5d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_72_OFFSET = 11'h 5dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_73_OFFSET = 11'h 5e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_74_OFFSET = 11'h 5e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_75_OFFSET = 11'h 5e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_76_OFFSET = 11'h 5ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_77_OFFSET = 11'h 5f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_78_OFFSET = 11'h 5f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_79_OFFSET = 11'h 5f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_80_OFFSET = 11'h 5fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_81_OFFSET = 11'h 600; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_82_OFFSET = 11'h 604; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_83_OFFSET = 11'h 608; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_84_OFFSET = 11'h 60c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_85_OFFSET = 11'h 610; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_86_OFFSET = 11'h 614; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_87_OFFSET = 11'h 618; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_88_OFFSET = 11'h 61c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_89_OFFSET = 11'h 620; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_90_OFFSET = 11'h 624; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_91_OFFSET = 11'h 628; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_92_OFFSET = 11'h 62c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_93_OFFSET = 11'h 630; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_94_OFFSET = 11'h 634; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_95_OFFSET = 11'h 638; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_96_OFFSET = 11'h 63c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_97_OFFSET = 11'h 640; + parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_98_OFFSET = 11'h 644; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 11'h 648; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 11'h 64c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 11'h 650; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 11'h 654; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 11'h 658; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET = 11'h 65c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET = 11'h 660; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET = 11'h 664; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET = 11'h 668; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET = 11'h 66c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET = 11'h 670; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET = 11'h 674; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET = 11'h 678; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET = 11'h 67c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET = 11'h 680; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET = 11'h 684; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET = 11'h 688; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET = 11'h 68c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET = 11'h 690; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET = 11'h 694; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET = 11'h 698; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 11'h 69c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 11'h 6a0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 11'h 6a4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 11'h 6a8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 11'h 6ac; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET = 11'h 6b0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET = 11'h 6b4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 11'h 6b8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET = 11'h 6bc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 11'h 6c0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET = 11'h 6c4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 11'h 6c8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 6cc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 6d0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 6d4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET = 11'h 6d8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET = 11'h 6dc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET = 11'h 6e0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET = 11'h 6e4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 11'h 6e8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 11'h 6ec; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 11'h 6f0; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET = 11'h 6f4; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 11'h 6f8; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET = 11'h 6fc; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 11'h 700; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 704; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 708; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 70c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET = 11'h 710; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET = 11'h 714; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET = 11'h 718; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET = 11'h 71c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 11'h 720; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 11'h 724; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 11'h 728; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET = 11'h 72c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 11'h 730; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET = 11'h 734; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 11'h 738; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 73c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 740; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 744; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET = 11'h 748; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET = 11'h 74c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET = 11'h 750; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET = 11'h 754; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 11'h 758; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 11'h 75c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 11'h 760; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET = 11'h 764; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 11'h 768; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET = 11'h 76c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 11'h 770; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET = 11'h 774; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET = 11'h 778; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET = 11'h 77c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET = 11'h 780; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET = 11'h 784; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET = 11'h 788; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET = 11'h 78c; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 11'h 790; + parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 11'h 794; + + // Reset values for hwext registers and their fields + parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSA_RESVAL = 1'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSB_RESVAL = 1'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSC_RESVAL = 1'h 0; + parameter logic [0:0] ALERT_HANDLER_INTR_TEST_CLASSD_RESVAL = 1'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSA_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSA_STATE_RESVAL = 3'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSB_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSB_STATE_RESVAL = 3'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSC_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSC_STATE_RESVAL = 3'h 0; + parameter logic [15:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_RESVAL = 16'h 0; + parameter logic [31:0] ALERT_HANDLER_CLASSD_ESC_CNT_RESVAL = 32'h 0; + parameter logic [2:0] ALERT_HANDLER_CLASSD_STATE_RESVAL = 3'h 0; + + // Register index + typedef enum int { + ALERT_HANDLER_INTR_STATE, + ALERT_HANDLER_INTR_ENABLE, + ALERT_HANDLER_INTR_TEST, + ALERT_HANDLER_PING_TIMER_REGWEN, + ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_PING_TIMER_EN_SHADOWED, + ALERT_HANDLER_ALERT_REGWEN_0, + ALERT_HANDLER_ALERT_REGWEN_1, + ALERT_HANDLER_ALERT_REGWEN_2, + ALERT_HANDLER_ALERT_REGWEN_3, + ALERT_HANDLER_ALERT_REGWEN_4, + ALERT_HANDLER_ALERT_REGWEN_5, + ALERT_HANDLER_ALERT_REGWEN_6, + ALERT_HANDLER_ALERT_REGWEN_7, + ALERT_HANDLER_ALERT_REGWEN_8, + ALERT_HANDLER_ALERT_REGWEN_9, + ALERT_HANDLER_ALERT_REGWEN_10, + ALERT_HANDLER_ALERT_REGWEN_11, + ALERT_HANDLER_ALERT_REGWEN_12, + ALERT_HANDLER_ALERT_REGWEN_13, + ALERT_HANDLER_ALERT_REGWEN_14, + ALERT_HANDLER_ALERT_REGWEN_15, + ALERT_HANDLER_ALERT_REGWEN_16, + ALERT_HANDLER_ALERT_REGWEN_17, + ALERT_HANDLER_ALERT_REGWEN_18, + ALERT_HANDLER_ALERT_REGWEN_19, + ALERT_HANDLER_ALERT_REGWEN_20, + ALERT_HANDLER_ALERT_REGWEN_21, + ALERT_HANDLER_ALERT_REGWEN_22, + ALERT_HANDLER_ALERT_REGWEN_23, + ALERT_HANDLER_ALERT_REGWEN_24, + ALERT_HANDLER_ALERT_REGWEN_25, + ALERT_HANDLER_ALERT_REGWEN_26, + ALERT_HANDLER_ALERT_REGWEN_27, + ALERT_HANDLER_ALERT_REGWEN_28, + ALERT_HANDLER_ALERT_REGWEN_29, + ALERT_HANDLER_ALERT_REGWEN_30, + ALERT_HANDLER_ALERT_REGWEN_31, + ALERT_HANDLER_ALERT_REGWEN_32, + ALERT_HANDLER_ALERT_REGWEN_33, + ALERT_HANDLER_ALERT_REGWEN_34, + ALERT_HANDLER_ALERT_REGWEN_35, + ALERT_HANDLER_ALERT_REGWEN_36, + ALERT_HANDLER_ALERT_REGWEN_37, + ALERT_HANDLER_ALERT_REGWEN_38, + ALERT_HANDLER_ALERT_REGWEN_39, + ALERT_HANDLER_ALERT_REGWEN_40, + ALERT_HANDLER_ALERT_REGWEN_41, + ALERT_HANDLER_ALERT_REGWEN_42, + ALERT_HANDLER_ALERT_REGWEN_43, + ALERT_HANDLER_ALERT_REGWEN_44, + ALERT_HANDLER_ALERT_REGWEN_45, + ALERT_HANDLER_ALERT_REGWEN_46, + ALERT_HANDLER_ALERT_REGWEN_47, + ALERT_HANDLER_ALERT_REGWEN_48, + ALERT_HANDLER_ALERT_REGWEN_49, + ALERT_HANDLER_ALERT_REGWEN_50, + ALERT_HANDLER_ALERT_REGWEN_51, + ALERT_HANDLER_ALERT_REGWEN_52, + ALERT_HANDLER_ALERT_REGWEN_53, + ALERT_HANDLER_ALERT_REGWEN_54, + ALERT_HANDLER_ALERT_REGWEN_55, + ALERT_HANDLER_ALERT_REGWEN_56, + ALERT_HANDLER_ALERT_REGWEN_57, + ALERT_HANDLER_ALERT_REGWEN_58, + ALERT_HANDLER_ALERT_REGWEN_59, + ALERT_HANDLER_ALERT_REGWEN_60, + ALERT_HANDLER_ALERT_REGWEN_61, + ALERT_HANDLER_ALERT_REGWEN_62, + ALERT_HANDLER_ALERT_REGWEN_63, + ALERT_HANDLER_ALERT_REGWEN_64, + ALERT_HANDLER_ALERT_REGWEN_65, + ALERT_HANDLER_ALERT_REGWEN_66, + ALERT_HANDLER_ALERT_REGWEN_67, + ALERT_HANDLER_ALERT_REGWEN_68, + ALERT_HANDLER_ALERT_REGWEN_69, + ALERT_HANDLER_ALERT_REGWEN_70, + ALERT_HANDLER_ALERT_REGWEN_71, + ALERT_HANDLER_ALERT_REGWEN_72, + ALERT_HANDLER_ALERT_REGWEN_73, + ALERT_HANDLER_ALERT_REGWEN_74, + ALERT_HANDLER_ALERT_REGWEN_75, + ALERT_HANDLER_ALERT_REGWEN_76, + ALERT_HANDLER_ALERT_REGWEN_77, + ALERT_HANDLER_ALERT_REGWEN_78, + ALERT_HANDLER_ALERT_REGWEN_79, + ALERT_HANDLER_ALERT_REGWEN_80, + ALERT_HANDLER_ALERT_REGWEN_81, + ALERT_HANDLER_ALERT_REGWEN_82, + ALERT_HANDLER_ALERT_REGWEN_83, + ALERT_HANDLER_ALERT_REGWEN_84, + ALERT_HANDLER_ALERT_REGWEN_85, + ALERT_HANDLER_ALERT_REGWEN_86, + ALERT_HANDLER_ALERT_REGWEN_87, + ALERT_HANDLER_ALERT_REGWEN_88, + ALERT_HANDLER_ALERT_REGWEN_89, + ALERT_HANDLER_ALERT_REGWEN_90, + ALERT_HANDLER_ALERT_REGWEN_91, + ALERT_HANDLER_ALERT_REGWEN_92, + ALERT_HANDLER_ALERT_REGWEN_93, + ALERT_HANDLER_ALERT_REGWEN_94, + ALERT_HANDLER_ALERT_REGWEN_95, + ALERT_HANDLER_ALERT_REGWEN_96, + ALERT_HANDLER_ALERT_REGWEN_97, + ALERT_HANDLER_ALERT_REGWEN_98, + ALERT_HANDLER_ALERT_EN_SHADOWED_0, + ALERT_HANDLER_ALERT_EN_SHADOWED_1, + ALERT_HANDLER_ALERT_EN_SHADOWED_2, + ALERT_HANDLER_ALERT_EN_SHADOWED_3, + ALERT_HANDLER_ALERT_EN_SHADOWED_4, + ALERT_HANDLER_ALERT_EN_SHADOWED_5, + ALERT_HANDLER_ALERT_EN_SHADOWED_6, + ALERT_HANDLER_ALERT_EN_SHADOWED_7, + ALERT_HANDLER_ALERT_EN_SHADOWED_8, + ALERT_HANDLER_ALERT_EN_SHADOWED_9, + ALERT_HANDLER_ALERT_EN_SHADOWED_10, + ALERT_HANDLER_ALERT_EN_SHADOWED_11, + ALERT_HANDLER_ALERT_EN_SHADOWED_12, + ALERT_HANDLER_ALERT_EN_SHADOWED_13, + ALERT_HANDLER_ALERT_EN_SHADOWED_14, + ALERT_HANDLER_ALERT_EN_SHADOWED_15, + ALERT_HANDLER_ALERT_EN_SHADOWED_16, + ALERT_HANDLER_ALERT_EN_SHADOWED_17, + ALERT_HANDLER_ALERT_EN_SHADOWED_18, + ALERT_HANDLER_ALERT_EN_SHADOWED_19, + ALERT_HANDLER_ALERT_EN_SHADOWED_20, + ALERT_HANDLER_ALERT_EN_SHADOWED_21, + ALERT_HANDLER_ALERT_EN_SHADOWED_22, + ALERT_HANDLER_ALERT_EN_SHADOWED_23, + ALERT_HANDLER_ALERT_EN_SHADOWED_24, + ALERT_HANDLER_ALERT_EN_SHADOWED_25, + ALERT_HANDLER_ALERT_EN_SHADOWED_26, + ALERT_HANDLER_ALERT_EN_SHADOWED_27, + ALERT_HANDLER_ALERT_EN_SHADOWED_28, + ALERT_HANDLER_ALERT_EN_SHADOWED_29, + ALERT_HANDLER_ALERT_EN_SHADOWED_30, + ALERT_HANDLER_ALERT_EN_SHADOWED_31, + ALERT_HANDLER_ALERT_EN_SHADOWED_32, + ALERT_HANDLER_ALERT_EN_SHADOWED_33, + ALERT_HANDLER_ALERT_EN_SHADOWED_34, + ALERT_HANDLER_ALERT_EN_SHADOWED_35, + ALERT_HANDLER_ALERT_EN_SHADOWED_36, + ALERT_HANDLER_ALERT_EN_SHADOWED_37, + ALERT_HANDLER_ALERT_EN_SHADOWED_38, + ALERT_HANDLER_ALERT_EN_SHADOWED_39, + ALERT_HANDLER_ALERT_EN_SHADOWED_40, + ALERT_HANDLER_ALERT_EN_SHADOWED_41, + ALERT_HANDLER_ALERT_EN_SHADOWED_42, + ALERT_HANDLER_ALERT_EN_SHADOWED_43, + ALERT_HANDLER_ALERT_EN_SHADOWED_44, + ALERT_HANDLER_ALERT_EN_SHADOWED_45, + ALERT_HANDLER_ALERT_EN_SHADOWED_46, + ALERT_HANDLER_ALERT_EN_SHADOWED_47, + ALERT_HANDLER_ALERT_EN_SHADOWED_48, + ALERT_HANDLER_ALERT_EN_SHADOWED_49, + ALERT_HANDLER_ALERT_EN_SHADOWED_50, + ALERT_HANDLER_ALERT_EN_SHADOWED_51, + ALERT_HANDLER_ALERT_EN_SHADOWED_52, + ALERT_HANDLER_ALERT_EN_SHADOWED_53, + ALERT_HANDLER_ALERT_EN_SHADOWED_54, + ALERT_HANDLER_ALERT_EN_SHADOWED_55, + ALERT_HANDLER_ALERT_EN_SHADOWED_56, + ALERT_HANDLER_ALERT_EN_SHADOWED_57, + ALERT_HANDLER_ALERT_EN_SHADOWED_58, + ALERT_HANDLER_ALERT_EN_SHADOWED_59, + ALERT_HANDLER_ALERT_EN_SHADOWED_60, + ALERT_HANDLER_ALERT_EN_SHADOWED_61, + ALERT_HANDLER_ALERT_EN_SHADOWED_62, + ALERT_HANDLER_ALERT_EN_SHADOWED_63, + ALERT_HANDLER_ALERT_EN_SHADOWED_64, + ALERT_HANDLER_ALERT_EN_SHADOWED_65, + ALERT_HANDLER_ALERT_EN_SHADOWED_66, + ALERT_HANDLER_ALERT_EN_SHADOWED_67, + ALERT_HANDLER_ALERT_EN_SHADOWED_68, + ALERT_HANDLER_ALERT_EN_SHADOWED_69, + ALERT_HANDLER_ALERT_EN_SHADOWED_70, + ALERT_HANDLER_ALERT_EN_SHADOWED_71, + ALERT_HANDLER_ALERT_EN_SHADOWED_72, + ALERT_HANDLER_ALERT_EN_SHADOWED_73, + ALERT_HANDLER_ALERT_EN_SHADOWED_74, + ALERT_HANDLER_ALERT_EN_SHADOWED_75, + ALERT_HANDLER_ALERT_EN_SHADOWED_76, + ALERT_HANDLER_ALERT_EN_SHADOWED_77, + ALERT_HANDLER_ALERT_EN_SHADOWED_78, + ALERT_HANDLER_ALERT_EN_SHADOWED_79, + ALERT_HANDLER_ALERT_EN_SHADOWED_80, + ALERT_HANDLER_ALERT_EN_SHADOWED_81, + ALERT_HANDLER_ALERT_EN_SHADOWED_82, + ALERT_HANDLER_ALERT_EN_SHADOWED_83, + ALERT_HANDLER_ALERT_EN_SHADOWED_84, + ALERT_HANDLER_ALERT_EN_SHADOWED_85, + ALERT_HANDLER_ALERT_EN_SHADOWED_86, + ALERT_HANDLER_ALERT_EN_SHADOWED_87, + ALERT_HANDLER_ALERT_EN_SHADOWED_88, + ALERT_HANDLER_ALERT_EN_SHADOWED_89, + ALERT_HANDLER_ALERT_EN_SHADOWED_90, + ALERT_HANDLER_ALERT_EN_SHADOWED_91, + ALERT_HANDLER_ALERT_EN_SHADOWED_92, + ALERT_HANDLER_ALERT_EN_SHADOWED_93, + ALERT_HANDLER_ALERT_EN_SHADOWED_94, + ALERT_HANDLER_ALERT_EN_SHADOWED_95, + ALERT_HANDLER_ALERT_EN_SHADOWED_96, + ALERT_HANDLER_ALERT_EN_SHADOWED_97, + ALERT_HANDLER_ALERT_EN_SHADOWED_98, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_1, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_2, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_3, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_4, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_5, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_6, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_7, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_8, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_9, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_10, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_11, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_12, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_13, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_14, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_15, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_16, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_17, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_18, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_19, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_20, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_21, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_22, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_23, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_24, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_25, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_26, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_27, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_28, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_29, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_30, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_31, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_32, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_33, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_34, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_35, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_36, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_37, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_38, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_39, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_40, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_41, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_42, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_43, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_44, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_45, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_46, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_47, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_48, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_49, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_50, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_51, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_52, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_53, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_54, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_55, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_56, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_57, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_58, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_59, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_60, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_61, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_62, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_63, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_64, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_65, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_66, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_67, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_68, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_69, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_70, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_71, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_72, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_73, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_74, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_75, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_76, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_77, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_78, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_79, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_80, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_81, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_82, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_83, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_84, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_85, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_86, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_87, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_88, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_89, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_90, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_91, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_92, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_93, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_94, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_95, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_96, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_97, + ALERT_HANDLER_ALERT_CLASS_SHADOWED_98, + ALERT_HANDLER_ALERT_CAUSE_0, + ALERT_HANDLER_ALERT_CAUSE_1, + ALERT_HANDLER_ALERT_CAUSE_2, + ALERT_HANDLER_ALERT_CAUSE_3, + ALERT_HANDLER_ALERT_CAUSE_4, + ALERT_HANDLER_ALERT_CAUSE_5, + ALERT_HANDLER_ALERT_CAUSE_6, + ALERT_HANDLER_ALERT_CAUSE_7, + ALERT_HANDLER_ALERT_CAUSE_8, + ALERT_HANDLER_ALERT_CAUSE_9, + ALERT_HANDLER_ALERT_CAUSE_10, + ALERT_HANDLER_ALERT_CAUSE_11, + ALERT_HANDLER_ALERT_CAUSE_12, + ALERT_HANDLER_ALERT_CAUSE_13, + ALERT_HANDLER_ALERT_CAUSE_14, + ALERT_HANDLER_ALERT_CAUSE_15, + ALERT_HANDLER_ALERT_CAUSE_16, + ALERT_HANDLER_ALERT_CAUSE_17, + ALERT_HANDLER_ALERT_CAUSE_18, + ALERT_HANDLER_ALERT_CAUSE_19, + ALERT_HANDLER_ALERT_CAUSE_20, + ALERT_HANDLER_ALERT_CAUSE_21, + ALERT_HANDLER_ALERT_CAUSE_22, + ALERT_HANDLER_ALERT_CAUSE_23, + ALERT_HANDLER_ALERT_CAUSE_24, + ALERT_HANDLER_ALERT_CAUSE_25, + ALERT_HANDLER_ALERT_CAUSE_26, + ALERT_HANDLER_ALERT_CAUSE_27, + ALERT_HANDLER_ALERT_CAUSE_28, + ALERT_HANDLER_ALERT_CAUSE_29, + ALERT_HANDLER_ALERT_CAUSE_30, + ALERT_HANDLER_ALERT_CAUSE_31, + ALERT_HANDLER_ALERT_CAUSE_32, + ALERT_HANDLER_ALERT_CAUSE_33, + ALERT_HANDLER_ALERT_CAUSE_34, + ALERT_HANDLER_ALERT_CAUSE_35, + ALERT_HANDLER_ALERT_CAUSE_36, + ALERT_HANDLER_ALERT_CAUSE_37, + ALERT_HANDLER_ALERT_CAUSE_38, + ALERT_HANDLER_ALERT_CAUSE_39, + ALERT_HANDLER_ALERT_CAUSE_40, + ALERT_HANDLER_ALERT_CAUSE_41, + ALERT_HANDLER_ALERT_CAUSE_42, + ALERT_HANDLER_ALERT_CAUSE_43, + ALERT_HANDLER_ALERT_CAUSE_44, + ALERT_HANDLER_ALERT_CAUSE_45, + ALERT_HANDLER_ALERT_CAUSE_46, + ALERT_HANDLER_ALERT_CAUSE_47, + ALERT_HANDLER_ALERT_CAUSE_48, + ALERT_HANDLER_ALERT_CAUSE_49, + ALERT_HANDLER_ALERT_CAUSE_50, + ALERT_HANDLER_ALERT_CAUSE_51, + ALERT_HANDLER_ALERT_CAUSE_52, + ALERT_HANDLER_ALERT_CAUSE_53, + ALERT_HANDLER_ALERT_CAUSE_54, + ALERT_HANDLER_ALERT_CAUSE_55, + ALERT_HANDLER_ALERT_CAUSE_56, + ALERT_HANDLER_ALERT_CAUSE_57, + ALERT_HANDLER_ALERT_CAUSE_58, + ALERT_HANDLER_ALERT_CAUSE_59, + ALERT_HANDLER_ALERT_CAUSE_60, + ALERT_HANDLER_ALERT_CAUSE_61, + ALERT_HANDLER_ALERT_CAUSE_62, + ALERT_HANDLER_ALERT_CAUSE_63, + ALERT_HANDLER_ALERT_CAUSE_64, + ALERT_HANDLER_ALERT_CAUSE_65, + ALERT_HANDLER_ALERT_CAUSE_66, + ALERT_HANDLER_ALERT_CAUSE_67, + ALERT_HANDLER_ALERT_CAUSE_68, + ALERT_HANDLER_ALERT_CAUSE_69, + ALERT_HANDLER_ALERT_CAUSE_70, + ALERT_HANDLER_ALERT_CAUSE_71, + ALERT_HANDLER_ALERT_CAUSE_72, + ALERT_HANDLER_ALERT_CAUSE_73, + ALERT_HANDLER_ALERT_CAUSE_74, + ALERT_HANDLER_ALERT_CAUSE_75, + ALERT_HANDLER_ALERT_CAUSE_76, + ALERT_HANDLER_ALERT_CAUSE_77, + ALERT_HANDLER_ALERT_CAUSE_78, + ALERT_HANDLER_ALERT_CAUSE_79, + ALERT_HANDLER_ALERT_CAUSE_80, + ALERT_HANDLER_ALERT_CAUSE_81, + ALERT_HANDLER_ALERT_CAUSE_82, + ALERT_HANDLER_ALERT_CAUSE_83, + ALERT_HANDLER_ALERT_CAUSE_84, + ALERT_HANDLER_ALERT_CAUSE_85, + ALERT_HANDLER_ALERT_CAUSE_86, + ALERT_HANDLER_ALERT_CAUSE_87, + ALERT_HANDLER_ALERT_CAUSE_88, + ALERT_HANDLER_ALERT_CAUSE_89, + ALERT_HANDLER_ALERT_CAUSE_90, + ALERT_HANDLER_ALERT_CAUSE_91, + ALERT_HANDLER_ALERT_CAUSE_92, + ALERT_HANDLER_ALERT_CAUSE_93, + ALERT_HANDLER_ALERT_CAUSE_94, + ALERT_HANDLER_ALERT_CAUSE_95, + ALERT_HANDLER_ALERT_CAUSE_96, + ALERT_HANDLER_ALERT_CAUSE_97, + ALERT_HANDLER_ALERT_CAUSE_98, + ALERT_HANDLER_LOC_ALERT_REGWEN_0, + ALERT_HANDLER_LOC_ALERT_REGWEN_1, + ALERT_HANDLER_LOC_ALERT_REGWEN_2, + ALERT_HANDLER_LOC_ALERT_REGWEN_3, + ALERT_HANDLER_LOC_ALERT_REGWEN_4, + ALERT_HANDLER_LOC_ALERT_REGWEN_5, + ALERT_HANDLER_LOC_ALERT_REGWEN_6, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5, + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5, + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6, + ALERT_HANDLER_LOC_ALERT_CAUSE_0, + ALERT_HANDLER_LOC_ALERT_CAUSE_1, + ALERT_HANDLER_LOC_ALERT_CAUSE_2, + ALERT_HANDLER_LOC_ALERT_CAUSE_3, + ALERT_HANDLER_LOC_ALERT_CAUSE_4, + ALERT_HANDLER_LOC_ALERT_CAUSE_5, + ALERT_HANDLER_LOC_ALERT_CAUSE_6, + ALERT_HANDLER_CLASSA_REGWEN, + ALERT_HANDLER_CLASSA_CTRL_SHADOWED, + ALERT_HANDLER_CLASSA_CLR_REGWEN, + ALERT_HANDLER_CLASSA_CLR_SHADOWED, + ALERT_HANDLER_CLASSA_ACCUM_CNT, + ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSA_ESC_CNT, + ALERT_HANDLER_CLASSA_STATE, + ALERT_HANDLER_CLASSB_REGWEN, + ALERT_HANDLER_CLASSB_CTRL_SHADOWED, + ALERT_HANDLER_CLASSB_CLR_REGWEN, + ALERT_HANDLER_CLASSB_CLR_SHADOWED, + ALERT_HANDLER_CLASSB_ACCUM_CNT, + ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSB_ESC_CNT, + ALERT_HANDLER_CLASSB_STATE, + ALERT_HANDLER_CLASSC_REGWEN, + ALERT_HANDLER_CLASSC_CTRL_SHADOWED, + ALERT_HANDLER_CLASSC_CLR_REGWEN, + ALERT_HANDLER_CLASSC_CLR_SHADOWED, + ALERT_HANDLER_CLASSC_ACCUM_CNT, + ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSC_ESC_CNT, + ALERT_HANDLER_CLASSC_STATE, + ALERT_HANDLER_CLASSD_REGWEN, + ALERT_HANDLER_CLASSD_CTRL_SHADOWED, + ALERT_HANDLER_CLASSD_CLR_REGWEN, + ALERT_HANDLER_CLASSD_CLR_SHADOWED, + ALERT_HANDLER_CLASSD_ACCUM_CNT, + ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED, + ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED, + ALERT_HANDLER_CLASSD_ESC_CNT, + ALERT_HANDLER_CLASSD_STATE + } alert_handler_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] ALERT_HANDLER_PERMIT [486] = '{ + 4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE + 4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE + 4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST + 4'b 0001, // index[ 3] ALERT_HANDLER_PING_TIMER_REGWEN + 4'b 0011, // index[ 4] ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[ 5] ALERT_HANDLER_PING_TIMER_EN_SHADOWED + 4'b 0001, // index[ 6] ALERT_HANDLER_ALERT_REGWEN_0 + 4'b 0001, // index[ 7] ALERT_HANDLER_ALERT_REGWEN_1 + 4'b 0001, // index[ 8] ALERT_HANDLER_ALERT_REGWEN_2 + 4'b 0001, // index[ 9] ALERT_HANDLER_ALERT_REGWEN_3 + 4'b 0001, // index[ 10] ALERT_HANDLER_ALERT_REGWEN_4 + 4'b 0001, // index[ 11] ALERT_HANDLER_ALERT_REGWEN_5 + 4'b 0001, // index[ 12] ALERT_HANDLER_ALERT_REGWEN_6 + 4'b 0001, // index[ 13] ALERT_HANDLER_ALERT_REGWEN_7 + 4'b 0001, // index[ 14] ALERT_HANDLER_ALERT_REGWEN_8 + 4'b 0001, // index[ 15] ALERT_HANDLER_ALERT_REGWEN_9 + 4'b 0001, // index[ 16] ALERT_HANDLER_ALERT_REGWEN_10 + 4'b 0001, // index[ 17] ALERT_HANDLER_ALERT_REGWEN_11 + 4'b 0001, // index[ 18] ALERT_HANDLER_ALERT_REGWEN_12 + 4'b 0001, // index[ 19] ALERT_HANDLER_ALERT_REGWEN_13 + 4'b 0001, // index[ 20] ALERT_HANDLER_ALERT_REGWEN_14 + 4'b 0001, // index[ 21] ALERT_HANDLER_ALERT_REGWEN_15 + 4'b 0001, // index[ 22] ALERT_HANDLER_ALERT_REGWEN_16 + 4'b 0001, // index[ 23] ALERT_HANDLER_ALERT_REGWEN_17 + 4'b 0001, // index[ 24] ALERT_HANDLER_ALERT_REGWEN_18 + 4'b 0001, // index[ 25] ALERT_HANDLER_ALERT_REGWEN_19 + 4'b 0001, // index[ 26] ALERT_HANDLER_ALERT_REGWEN_20 + 4'b 0001, // index[ 27] ALERT_HANDLER_ALERT_REGWEN_21 + 4'b 0001, // index[ 28] ALERT_HANDLER_ALERT_REGWEN_22 + 4'b 0001, // index[ 29] ALERT_HANDLER_ALERT_REGWEN_23 + 4'b 0001, // index[ 30] ALERT_HANDLER_ALERT_REGWEN_24 + 4'b 0001, // index[ 31] ALERT_HANDLER_ALERT_REGWEN_25 + 4'b 0001, // index[ 32] ALERT_HANDLER_ALERT_REGWEN_26 + 4'b 0001, // index[ 33] ALERT_HANDLER_ALERT_REGWEN_27 + 4'b 0001, // index[ 34] ALERT_HANDLER_ALERT_REGWEN_28 + 4'b 0001, // index[ 35] ALERT_HANDLER_ALERT_REGWEN_29 + 4'b 0001, // index[ 36] ALERT_HANDLER_ALERT_REGWEN_30 + 4'b 0001, // index[ 37] ALERT_HANDLER_ALERT_REGWEN_31 + 4'b 0001, // index[ 38] ALERT_HANDLER_ALERT_REGWEN_32 + 4'b 0001, // index[ 39] ALERT_HANDLER_ALERT_REGWEN_33 + 4'b 0001, // index[ 40] ALERT_HANDLER_ALERT_REGWEN_34 + 4'b 0001, // index[ 41] ALERT_HANDLER_ALERT_REGWEN_35 + 4'b 0001, // index[ 42] ALERT_HANDLER_ALERT_REGWEN_36 + 4'b 0001, // index[ 43] ALERT_HANDLER_ALERT_REGWEN_37 + 4'b 0001, // index[ 44] ALERT_HANDLER_ALERT_REGWEN_38 + 4'b 0001, // index[ 45] ALERT_HANDLER_ALERT_REGWEN_39 + 4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_REGWEN_40 + 4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_REGWEN_41 + 4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_REGWEN_42 + 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_REGWEN_43 + 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_REGWEN_44 + 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_REGWEN_45 + 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_REGWEN_46 + 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_REGWEN_47 + 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_REGWEN_48 + 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_REGWEN_49 + 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_REGWEN_50 + 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_REGWEN_51 + 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_REGWEN_52 + 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_REGWEN_53 + 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_REGWEN_54 + 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_REGWEN_55 + 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_REGWEN_56 + 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_REGWEN_57 + 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_REGWEN_58 + 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_REGWEN_59 + 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_REGWEN_60 + 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_REGWEN_61 + 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_REGWEN_62 + 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_REGWEN_63 + 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_REGWEN_64 + 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_REGWEN_65 + 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_REGWEN_66 + 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_REGWEN_67 + 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_REGWEN_68 + 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_REGWEN_69 + 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_REGWEN_70 + 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_REGWEN_71 + 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_REGWEN_72 + 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_REGWEN_73 + 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_REGWEN_74 + 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_REGWEN_75 + 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_REGWEN_76 + 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_REGWEN_77 + 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_REGWEN_78 + 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_REGWEN_79 + 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_REGWEN_80 + 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_REGWEN_81 + 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_REGWEN_82 + 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_REGWEN_83 + 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_REGWEN_84 + 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_REGWEN_85 + 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_REGWEN_86 + 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_REGWEN_87 + 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_REGWEN_88 + 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_REGWEN_89 + 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_REGWEN_90 + 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_REGWEN_91 + 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_REGWEN_92 + 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_REGWEN_93 + 4'b 0001, // index[100] ALERT_HANDLER_ALERT_REGWEN_94 + 4'b 0001, // index[101] ALERT_HANDLER_ALERT_REGWEN_95 + 4'b 0001, // index[102] ALERT_HANDLER_ALERT_REGWEN_96 + 4'b 0001, // index[103] ALERT_HANDLER_ALERT_REGWEN_97 + 4'b 0001, // index[104] ALERT_HANDLER_ALERT_REGWEN_98 + 4'b 0001, // index[105] ALERT_HANDLER_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[106] ALERT_HANDLER_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[107] ALERT_HANDLER_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[108] ALERT_HANDLER_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[109] ALERT_HANDLER_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[110] ALERT_HANDLER_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[111] ALERT_HANDLER_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[112] ALERT_HANDLER_ALERT_EN_SHADOWED_7 + 4'b 0001, // index[113] ALERT_HANDLER_ALERT_EN_SHADOWED_8 + 4'b 0001, // index[114] ALERT_HANDLER_ALERT_EN_SHADOWED_9 + 4'b 0001, // index[115] ALERT_HANDLER_ALERT_EN_SHADOWED_10 + 4'b 0001, // index[116] ALERT_HANDLER_ALERT_EN_SHADOWED_11 + 4'b 0001, // index[117] ALERT_HANDLER_ALERT_EN_SHADOWED_12 + 4'b 0001, // index[118] ALERT_HANDLER_ALERT_EN_SHADOWED_13 + 4'b 0001, // index[119] ALERT_HANDLER_ALERT_EN_SHADOWED_14 + 4'b 0001, // index[120] ALERT_HANDLER_ALERT_EN_SHADOWED_15 + 4'b 0001, // index[121] ALERT_HANDLER_ALERT_EN_SHADOWED_16 + 4'b 0001, // index[122] ALERT_HANDLER_ALERT_EN_SHADOWED_17 + 4'b 0001, // index[123] ALERT_HANDLER_ALERT_EN_SHADOWED_18 + 4'b 0001, // index[124] ALERT_HANDLER_ALERT_EN_SHADOWED_19 + 4'b 0001, // index[125] ALERT_HANDLER_ALERT_EN_SHADOWED_20 + 4'b 0001, // index[126] ALERT_HANDLER_ALERT_EN_SHADOWED_21 + 4'b 0001, // index[127] ALERT_HANDLER_ALERT_EN_SHADOWED_22 + 4'b 0001, // index[128] ALERT_HANDLER_ALERT_EN_SHADOWED_23 + 4'b 0001, // index[129] ALERT_HANDLER_ALERT_EN_SHADOWED_24 + 4'b 0001, // index[130] ALERT_HANDLER_ALERT_EN_SHADOWED_25 + 4'b 0001, // index[131] ALERT_HANDLER_ALERT_EN_SHADOWED_26 + 4'b 0001, // index[132] ALERT_HANDLER_ALERT_EN_SHADOWED_27 + 4'b 0001, // index[133] ALERT_HANDLER_ALERT_EN_SHADOWED_28 + 4'b 0001, // index[134] ALERT_HANDLER_ALERT_EN_SHADOWED_29 + 4'b 0001, // index[135] ALERT_HANDLER_ALERT_EN_SHADOWED_30 + 4'b 0001, // index[136] ALERT_HANDLER_ALERT_EN_SHADOWED_31 + 4'b 0001, // index[137] ALERT_HANDLER_ALERT_EN_SHADOWED_32 + 4'b 0001, // index[138] ALERT_HANDLER_ALERT_EN_SHADOWED_33 + 4'b 0001, // index[139] ALERT_HANDLER_ALERT_EN_SHADOWED_34 + 4'b 0001, // index[140] ALERT_HANDLER_ALERT_EN_SHADOWED_35 + 4'b 0001, // index[141] ALERT_HANDLER_ALERT_EN_SHADOWED_36 + 4'b 0001, // index[142] ALERT_HANDLER_ALERT_EN_SHADOWED_37 + 4'b 0001, // index[143] ALERT_HANDLER_ALERT_EN_SHADOWED_38 + 4'b 0001, // index[144] ALERT_HANDLER_ALERT_EN_SHADOWED_39 + 4'b 0001, // index[145] ALERT_HANDLER_ALERT_EN_SHADOWED_40 + 4'b 0001, // index[146] ALERT_HANDLER_ALERT_EN_SHADOWED_41 + 4'b 0001, // index[147] ALERT_HANDLER_ALERT_EN_SHADOWED_42 + 4'b 0001, // index[148] ALERT_HANDLER_ALERT_EN_SHADOWED_43 + 4'b 0001, // index[149] ALERT_HANDLER_ALERT_EN_SHADOWED_44 + 4'b 0001, // index[150] ALERT_HANDLER_ALERT_EN_SHADOWED_45 + 4'b 0001, // index[151] ALERT_HANDLER_ALERT_EN_SHADOWED_46 + 4'b 0001, // index[152] ALERT_HANDLER_ALERT_EN_SHADOWED_47 + 4'b 0001, // index[153] ALERT_HANDLER_ALERT_EN_SHADOWED_48 + 4'b 0001, // index[154] ALERT_HANDLER_ALERT_EN_SHADOWED_49 + 4'b 0001, // index[155] ALERT_HANDLER_ALERT_EN_SHADOWED_50 + 4'b 0001, // index[156] ALERT_HANDLER_ALERT_EN_SHADOWED_51 + 4'b 0001, // index[157] ALERT_HANDLER_ALERT_EN_SHADOWED_52 + 4'b 0001, // index[158] ALERT_HANDLER_ALERT_EN_SHADOWED_53 + 4'b 0001, // index[159] ALERT_HANDLER_ALERT_EN_SHADOWED_54 + 4'b 0001, // index[160] ALERT_HANDLER_ALERT_EN_SHADOWED_55 + 4'b 0001, // index[161] ALERT_HANDLER_ALERT_EN_SHADOWED_56 + 4'b 0001, // index[162] ALERT_HANDLER_ALERT_EN_SHADOWED_57 + 4'b 0001, // index[163] ALERT_HANDLER_ALERT_EN_SHADOWED_58 + 4'b 0001, // index[164] ALERT_HANDLER_ALERT_EN_SHADOWED_59 + 4'b 0001, // index[165] ALERT_HANDLER_ALERT_EN_SHADOWED_60 + 4'b 0001, // index[166] ALERT_HANDLER_ALERT_EN_SHADOWED_61 + 4'b 0001, // index[167] ALERT_HANDLER_ALERT_EN_SHADOWED_62 + 4'b 0001, // index[168] ALERT_HANDLER_ALERT_EN_SHADOWED_63 + 4'b 0001, // index[169] ALERT_HANDLER_ALERT_EN_SHADOWED_64 + 4'b 0001, // index[170] ALERT_HANDLER_ALERT_EN_SHADOWED_65 + 4'b 0001, // index[171] ALERT_HANDLER_ALERT_EN_SHADOWED_66 + 4'b 0001, // index[172] ALERT_HANDLER_ALERT_EN_SHADOWED_67 + 4'b 0001, // index[173] ALERT_HANDLER_ALERT_EN_SHADOWED_68 + 4'b 0001, // index[174] ALERT_HANDLER_ALERT_EN_SHADOWED_69 + 4'b 0001, // index[175] ALERT_HANDLER_ALERT_EN_SHADOWED_70 + 4'b 0001, // index[176] ALERT_HANDLER_ALERT_EN_SHADOWED_71 + 4'b 0001, // index[177] ALERT_HANDLER_ALERT_EN_SHADOWED_72 + 4'b 0001, // index[178] ALERT_HANDLER_ALERT_EN_SHADOWED_73 + 4'b 0001, // index[179] ALERT_HANDLER_ALERT_EN_SHADOWED_74 + 4'b 0001, // index[180] ALERT_HANDLER_ALERT_EN_SHADOWED_75 + 4'b 0001, // index[181] ALERT_HANDLER_ALERT_EN_SHADOWED_76 + 4'b 0001, // index[182] ALERT_HANDLER_ALERT_EN_SHADOWED_77 + 4'b 0001, // index[183] ALERT_HANDLER_ALERT_EN_SHADOWED_78 + 4'b 0001, // index[184] ALERT_HANDLER_ALERT_EN_SHADOWED_79 + 4'b 0001, // index[185] ALERT_HANDLER_ALERT_EN_SHADOWED_80 + 4'b 0001, // index[186] ALERT_HANDLER_ALERT_EN_SHADOWED_81 + 4'b 0001, // index[187] ALERT_HANDLER_ALERT_EN_SHADOWED_82 + 4'b 0001, // index[188] ALERT_HANDLER_ALERT_EN_SHADOWED_83 + 4'b 0001, // index[189] ALERT_HANDLER_ALERT_EN_SHADOWED_84 + 4'b 0001, // index[190] ALERT_HANDLER_ALERT_EN_SHADOWED_85 + 4'b 0001, // index[191] ALERT_HANDLER_ALERT_EN_SHADOWED_86 + 4'b 0001, // index[192] ALERT_HANDLER_ALERT_EN_SHADOWED_87 + 4'b 0001, // index[193] ALERT_HANDLER_ALERT_EN_SHADOWED_88 + 4'b 0001, // index[194] ALERT_HANDLER_ALERT_EN_SHADOWED_89 + 4'b 0001, // index[195] ALERT_HANDLER_ALERT_EN_SHADOWED_90 + 4'b 0001, // index[196] ALERT_HANDLER_ALERT_EN_SHADOWED_91 + 4'b 0001, // index[197] ALERT_HANDLER_ALERT_EN_SHADOWED_92 + 4'b 0001, // index[198] ALERT_HANDLER_ALERT_EN_SHADOWED_93 + 4'b 0001, // index[199] ALERT_HANDLER_ALERT_EN_SHADOWED_94 + 4'b 0001, // index[200] ALERT_HANDLER_ALERT_EN_SHADOWED_95 + 4'b 0001, // index[201] ALERT_HANDLER_ALERT_EN_SHADOWED_96 + 4'b 0001, // index[202] ALERT_HANDLER_ALERT_EN_SHADOWED_97 + 4'b 0001, // index[203] ALERT_HANDLER_ALERT_EN_SHADOWED_98 + 4'b 0001, // index[204] ALERT_HANDLER_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[205] ALERT_HANDLER_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[206] ALERT_HANDLER_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[207] ALERT_HANDLER_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[208] ALERT_HANDLER_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[209] ALERT_HANDLER_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[210] ALERT_HANDLER_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[211] ALERT_HANDLER_ALERT_CLASS_SHADOWED_7 + 4'b 0001, // index[212] ALERT_HANDLER_ALERT_CLASS_SHADOWED_8 + 4'b 0001, // index[213] ALERT_HANDLER_ALERT_CLASS_SHADOWED_9 + 4'b 0001, // index[214] ALERT_HANDLER_ALERT_CLASS_SHADOWED_10 + 4'b 0001, // index[215] ALERT_HANDLER_ALERT_CLASS_SHADOWED_11 + 4'b 0001, // index[216] ALERT_HANDLER_ALERT_CLASS_SHADOWED_12 + 4'b 0001, // index[217] ALERT_HANDLER_ALERT_CLASS_SHADOWED_13 + 4'b 0001, // index[218] ALERT_HANDLER_ALERT_CLASS_SHADOWED_14 + 4'b 0001, // index[219] ALERT_HANDLER_ALERT_CLASS_SHADOWED_15 + 4'b 0001, // index[220] ALERT_HANDLER_ALERT_CLASS_SHADOWED_16 + 4'b 0001, // index[221] ALERT_HANDLER_ALERT_CLASS_SHADOWED_17 + 4'b 0001, // index[222] ALERT_HANDLER_ALERT_CLASS_SHADOWED_18 + 4'b 0001, // index[223] ALERT_HANDLER_ALERT_CLASS_SHADOWED_19 + 4'b 0001, // index[224] ALERT_HANDLER_ALERT_CLASS_SHADOWED_20 + 4'b 0001, // index[225] ALERT_HANDLER_ALERT_CLASS_SHADOWED_21 + 4'b 0001, // index[226] ALERT_HANDLER_ALERT_CLASS_SHADOWED_22 + 4'b 0001, // index[227] ALERT_HANDLER_ALERT_CLASS_SHADOWED_23 + 4'b 0001, // index[228] ALERT_HANDLER_ALERT_CLASS_SHADOWED_24 + 4'b 0001, // index[229] ALERT_HANDLER_ALERT_CLASS_SHADOWED_25 + 4'b 0001, // index[230] ALERT_HANDLER_ALERT_CLASS_SHADOWED_26 + 4'b 0001, // index[231] ALERT_HANDLER_ALERT_CLASS_SHADOWED_27 + 4'b 0001, // index[232] ALERT_HANDLER_ALERT_CLASS_SHADOWED_28 + 4'b 0001, // index[233] ALERT_HANDLER_ALERT_CLASS_SHADOWED_29 + 4'b 0001, // index[234] ALERT_HANDLER_ALERT_CLASS_SHADOWED_30 + 4'b 0001, // index[235] ALERT_HANDLER_ALERT_CLASS_SHADOWED_31 + 4'b 0001, // index[236] ALERT_HANDLER_ALERT_CLASS_SHADOWED_32 + 4'b 0001, // index[237] ALERT_HANDLER_ALERT_CLASS_SHADOWED_33 + 4'b 0001, // index[238] ALERT_HANDLER_ALERT_CLASS_SHADOWED_34 + 4'b 0001, // index[239] ALERT_HANDLER_ALERT_CLASS_SHADOWED_35 + 4'b 0001, // index[240] ALERT_HANDLER_ALERT_CLASS_SHADOWED_36 + 4'b 0001, // index[241] ALERT_HANDLER_ALERT_CLASS_SHADOWED_37 + 4'b 0001, // index[242] ALERT_HANDLER_ALERT_CLASS_SHADOWED_38 + 4'b 0001, // index[243] ALERT_HANDLER_ALERT_CLASS_SHADOWED_39 + 4'b 0001, // index[244] ALERT_HANDLER_ALERT_CLASS_SHADOWED_40 + 4'b 0001, // index[245] ALERT_HANDLER_ALERT_CLASS_SHADOWED_41 + 4'b 0001, // index[246] ALERT_HANDLER_ALERT_CLASS_SHADOWED_42 + 4'b 0001, // index[247] ALERT_HANDLER_ALERT_CLASS_SHADOWED_43 + 4'b 0001, // index[248] ALERT_HANDLER_ALERT_CLASS_SHADOWED_44 + 4'b 0001, // index[249] ALERT_HANDLER_ALERT_CLASS_SHADOWED_45 + 4'b 0001, // index[250] ALERT_HANDLER_ALERT_CLASS_SHADOWED_46 + 4'b 0001, // index[251] ALERT_HANDLER_ALERT_CLASS_SHADOWED_47 + 4'b 0001, // index[252] ALERT_HANDLER_ALERT_CLASS_SHADOWED_48 + 4'b 0001, // index[253] ALERT_HANDLER_ALERT_CLASS_SHADOWED_49 + 4'b 0001, // index[254] ALERT_HANDLER_ALERT_CLASS_SHADOWED_50 + 4'b 0001, // index[255] ALERT_HANDLER_ALERT_CLASS_SHADOWED_51 + 4'b 0001, // index[256] ALERT_HANDLER_ALERT_CLASS_SHADOWED_52 + 4'b 0001, // index[257] ALERT_HANDLER_ALERT_CLASS_SHADOWED_53 + 4'b 0001, // index[258] ALERT_HANDLER_ALERT_CLASS_SHADOWED_54 + 4'b 0001, // index[259] ALERT_HANDLER_ALERT_CLASS_SHADOWED_55 + 4'b 0001, // index[260] ALERT_HANDLER_ALERT_CLASS_SHADOWED_56 + 4'b 0001, // index[261] ALERT_HANDLER_ALERT_CLASS_SHADOWED_57 + 4'b 0001, // index[262] ALERT_HANDLER_ALERT_CLASS_SHADOWED_58 + 4'b 0001, // index[263] ALERT_HANDLER_ALERT_CLASS_SHADOWED_59 + 4'b 0001, // index[264] ALERT_HANDLER_ALERT_CLASS_SHADOWED_60 + 4'b 0001, // index[265] ALERT_HANDLER_ALERT_CLASS_SHADOWED_61 + 4'b 0001, // index[266] ALERT_HANDLER_ALERT_CLASS_SHADOWED_62 + 4'b 0001, // index[267] ALERT_HANDLER_ALERT_CLASS_SHADOWED_63 + 4'b 0001, // index[268] ALERT_HANDLER_ALERT_CLASS_SHADOWED_64 + 4'b 0001, // index[269] ALERT_HANDLER_ALERT_CLASS_SHADOWED_65 + 4'b 0001, // index[270] ALERT_HANDLER_ALERT_CLASS_SHADOWED_66 + 4'b 0001, // index[271] ALERT_HANDLER_ALERT_CLASS_SHADOWED_67 + 4'b 0001, // index[272] ALERT_HANDLER_ALERT_CLASS_SHADOWED_68 + 4'b 0001, // index[273] ALERT_HANDLER_ALERT_CLASS_SHADOWED_69 + 4'b 0001, // index[274] ALERT_HANDLER_ALERT_CLASS_SHADOWED_70 + 4'b 0001, // index[275] ALERT_HANDLER_ALERT_CLASS_SHADOWED_71 + 4'b 0001, // index[276] ALERT_HANDLER_ALERT_CLASS_SHADOWED_72 + 4'b 0001, // index[277] ALERT_HANDLER_ALERT_CLASS_SHADOWED_73 + 4'b 0001, // index[278] ALERT_HANDLER_ALERT_CLASS_SHADOWED_74 + 4'b 0001, // index[279] ALERT_HANDLER_ALERT_CLASS_SHADOWED_75 + 4'b 0001, // index[280] ALERT_HANDLER_ALERT_CLASS_SHADOWED_76 + 4'b 0001, // index[281] ALERT_HANDLER_ALERT_CLASS_SHADOWED_77 + 4'b 0001, // index[282] ALERT_HANDLER_ALERT_CLASS_SHADOWED_78 + 4'b 0001, // index[283] ALERT_HANDLER_ALERT_CLASS_SHADOWED_79 + 4'b 0001, // index[284] ALERT_HANDLER_ALERT_CLASS_SHADOWED_80 + 4'b 0001, // index[285] ALERT_HANDLER_ALERT_CLASS_SHADOWED_81 + 4'b 0001, // index[286] ALERT_HANDLER_ALERT_CLASS_SHADOWED_82 + 4'b 0001, // index[287] ALERT_HANDLER_ALERT_CLASS_SHADOWED_83 + 4'b 0001, // index[288] ALERT_HANDLER_ALERT_CLASS_SHADOWED_84 + 4'b 0001, // index[289] ALERT_HANDLER_ALERT_CLASS_SHADOWED_85 + 4'b 0001, // index[290] ALERT_HANDLER_ALERT_CLASS_SHADOWED_86 + 4'b 0001, // index[291] ALERT_HANDLER_ALERT_CLASS_SHADOWED_87 + 4'b 0001, // index[292] ALERT_HANDLER_ALERT_CLASS_SHADOWED_88 + 4'b 0001, // index[293] ALERT_HANDLER_ALERT_CLASS_SHADOWED_89 + 4'b 0001, // index[294] ALERT_HANDLER_ALERT_CLASS_SHADOWED_90 + 4'b 0001, // index[295] ALERT_HANDLER_ALERT_CLASS_SHADOWED_91 + 4'b 0001, // index[296] ALERT_HANDLER_ALERT_CLASS_SHADOWED_92 + 4'b 0001, // index[297] ALERT_HANDLER_ALERT_CLASS_SHADOWED_93 + 4'b 0001, // index[298] ALERT_HANDLER_ALERT_CLASS_SHADOWED_94 + 4'b 0001, // index[299] ALERT_HANDLER_ALERT_CLASS_SHADOWED_95 + 4'b 0001, // index[300] ALERT_HANDLER_ALERT_CLASS_SHADOWED_96 + 4'b 0001, // index[301] ALERT_HANDLER_ALERT_CLASS_SHADOWED_97 + 4'b 0001, // index[302] ALERT_HANDLER_ALERT_CLASS_SHADOWED_98 + 4'b 0001, // index[303] ALERT_HANDLER_ALERT_CAUSE_0 + 4'b 0001, // index[304] ALERT_HANDLER_ALERT_CAUSE_1 + 4'b 0001, // index[305] ALERT_HANDLER_ALERT_CAUSE_2 + 4'b 0001, // index[306] ALERT_HANDLER_ALERT_CAUSE_3 + 4'b 0001, // index[307] ALERT_HANDLER_ALERT_CAUSE_4 + 4'b 0001, // index[308] ALERT_HANDLER_ALERT_CAUSE_5 + 4'b 0001, // index[309] ALERT_HANDLER_ALERT_CAUSE_6 + 4'b 0001, // index[310] ALERT_HANDLER_ALERT_CAUSE_7 + 4'b 0001, // index[311] ALERT_HANDLER_ALERT_CAUSE_8 + 4'b 0001, // index[312] ALERT_HANDLER_ALERT_CAUSE_9 + 4'b 0001, // index[313] ALERT_HANDLER_ALERT_CAUSE_10 + 4'b 0001, // index[314] ALERT_HANDLER_ALERT_CAUSE_11 + 4'b 0001, // index[315] ALERT_HANDLER_ALERT_CAUSE_12 + 4'b 0001, // index[316] ALERT_HANDLER_ALERT_CAUSE_13 + 4'b 0001, // index[317] ALERT_HANDLER_ALERT_CAUSE_14 + 4'b 0001, // index[318] ALERT_HANDLER_ALERT_CAUSE_15 + 4'b 0001, // index[319] ALERT_HANDLER_ALERT_CAUSE_16 + 4'b 0001, // index[320] ALERT_HANDLER_ALERT_CAUSE_17 + 4'b 0001, // index[321] ALERT_HANDLER_ALERT_CAUSE_18 + 4'b 0001, // index[322] ALERT_HANDLER_ALERT_CAUSE_19 + 4'b 0001, // index[323] ALERT_HANDLER_ALERT_CAUSE_20 + 4'b 0001, // index[324] ALERT_HANDLER_ALERT_CAUSE_21 + 4'b 0001, // index[325] ALERT_HANDLER_ALERT_CAUSE_22 + 4'b 0001, // index[326] ALERT_HANDLER_ALERT_CAUSE_23 + 4'b 0001, // index[327] ALERT_HANDLER_ALERT_CAUSE_24 + 4'b 0001, // index[328] ALERT_HANDLER_ALERT_CAUSE_25 + 4'b 0001, // index[329] ALERT_HANDLER_ALERT_CAUSE_26 + 4'b 0001, // index[330] ALERT_HANDLER_ALERT_CAUSE_27 + 4'b 0001, // index[331] ALERT_HANDLER_ALERT_CAUSE_28 + 4'b 0001, // index[332] ALERT_HANDLER_ALERT_CAUSE_29 + 4'b 0001, // index[333] ALERT_HANDLER_ALERT_CAUSE_30 + 4'b 0001, // index[334] ALERT_HANDLER_ALERT_CAUSE_31 + 4'b 0001, // index[335] ALERT_HANDLER_ALERT_CAUSE_32 + 4'b 0001, // index[336] ALERT_HANDLER_ALERT_CAUSE_33 + 4'b 0001, // index[337] ALERT_HANDLER_ALERT_CAUSE_34 + 4'b 0001, // index[338] ALERT_HANDLER_ALERT_CAUSE_35 + 4'b 0001, // index[339] ALERT_HANDLER_ALERT_CAUSE_36 + 4'b 0001, // index[340] ALERT_HANDLER_ALERT_CAUSE_37 + 4'b 0001, // index[341] ALERT_HANDLER_ALERT_CAUSE_38 + 4'b 0001, // index[342] ALERT_HANDLER_ALERT_CAUSE_39 + 4'b 0001, // index[343] ALERT_HANDLER_ALERT_CAUSE_40 + 4'b 0001, // index[344] ALERT_HANDLER_ALERT_CAUSE_41 + 4'b 0001, // index[345] ALERT_HANDLER_ALERT_CAUSE_42 + 4'b 0001, // index[346] ALERT_HANDLER_ALERT_CAUSE_43 + 4'b 0001, // index[347] ALERT_HANDLER_ALERT_CAUSE_44 + 4'b 0001, // index[348] ALERT_HANDLER_ALERT_CAUSE_45 + 4'b 0001, // index[349] ALERT_HANDLER_ALERT_CAUSE_46 + 4'b 0001, // index[350] ALERT_HANDLER_ALERT_CAUSE_47 + 4'b 0001, // index[351] ALERT_HANDLER_ALERT_CAUSE_48 + 4'b 0001, // index[352] ALERT_HANDLER_ALERT_CAUSE_49 + 4'b 0001, // index[353] ALERT_HANDLER_ALERT_CAUSE_50 + 4'b 0001, // index[354] ALERT_HANDLER_ALERT_CAUSE_51 + 4'b 0001, // index[355] ALERT_HANDLER_ALERT_CAUSE_52 + 4'b 0001, // index[356] ALERT_HANDLER_ALERT_CAUSE_53 + 4'b 0001, // index[357] ALERT_HANDLER_ALERT_CAUSE_54 + 4'b 0001, // index[358] ALERT_HANDLER_ALERT_CAUSE_55 + 4'b 0001, // index[359] ALERT_HANDLER_ALERT_CAUSE_56 + 4'b 0001, // index[360] ALERT_HANDLER_ALERT_CAUSE_57 + 4'b 0001, // index[361] ALERT_HANDLER_ALERT_CAUSE_58 + 4'b 0001, // index[362] ALERT_HANDLER_ALERT_CAUSE_59 + 4'b 0001, // index[363] ALERT_HANDLER_ALERT_CAUSE_60 + 4'b 0001, // index[364] ALERT_HANDLER_ALERT_CAUSE_61 + 4'b 0001, // index[365] ALERT_HANDLER_ALERT_CAUSE_62 + 4'b 0001, // index[366] ALERT_HANDLER_ALERT_CAUSE_63 + 4'b 0001, // index[367] ALERT_HANDLER_ALERT_CAUSE_64 + 4'b 0001, // index[368] ALERT_HANDLER_ALERT_CAUSE_65 + 4'b 0001, // index[369] ALERT_HANDLER_ALERT_CAUSE_66 + 4'b 0001, // index[370] ALERT_HANDLER_ALERT_CAUSE_67 + 4'b 0001, // index[371] ALERT_HANDLER_ALERT_CAUSE_68 + 4'b 0001, // index[372] ALERT_HANDLER_ALERT_CAUSE_69 + 4'b 0001, // index[373] ALERT_HANDLER_ALERT_CAUSE_70 + 4'b 0001, // index[374] ALERT_HANDLER_ALERT_CAUSE_71 + 4'b 0001, // index[375] ALERT_HANDLER_ALERT_CAUSE_72 + 4'b 0001, // index[376] ALERT_HANDLER_ALERT_CAUSE_73 + 4'b 0001, // index[377] ALERT_HANDLER_ALERT_CAUSE_74 + 4'b 0001, // index[378] ALERT_HANDLER_ALERT_CAUSE_75 + 4'b 0001, // index[379] ALERT_HANDLER_ALERT_CAUSE_76 + 4'b 0001, // index[380] ALERT_HANDLER_ALERT_CAUSE_77 + 4'b 0001, // index[381] ALERT_HANDLER_ALERT_CAUSE_78 + 4'b 0001, // index[382] ALERT_HANDLER_ALERT_CAUSE_79 + 4'b 0001, // index[383] ALERT_HANDLER_ALERT_CAUSE_80 + 4'b 0001, // index[384] ALERT_HANDLER_ALERT_CAUSE_81 + 4'b 0001, // index[385] ALERT_HANDLER_ALERT_CAUSE_82 + 4'b 0001, // index[386] ALERT_HANDLER_ALERT_CAUSE_83 + 4'b 0001, // index[387] ALERT_HANDLER_ALERT_CAUSE_84 + 4'b 0001, // index[388] ALERT_HANDLER_ALERT_CAUSE_85 + 4'b 0001, // index[389] ALERT_HANDLER_ALERT_CAUSE_86 + 4'b 0001, // index[390] ALERT_HANDLER_ALERT_CAUSE_87 + 4'b 0001, // index[391] ALERT_HANDLER_ALERT_CAUSE_88 + 4'b 0001, // index[392] ALERT_HANDLER_ALERT_CAUSE_89 + 4'b 0001, // index[393] ALERT_HANDLER_ALERT_CAUSE_90 + 4'b 0001, // index[394] ALERT_HANDLER_ALERT_CAUSE_91 + 4'b 0001, // index[395] ALERT_HANDLER_ALERT_CAUSE_92 + 4'b 0001, // index[396] ALERT_HANDLER_ALERT_CAUSE_93 + 4'b 0001, // index[397] ALERT_HANDLER_ALERT_CAUSE_94 + 4'b 0001, // index[398] ALERT_HANDLER_ALERT_CAUSE_95 + 4'b 0001, // index[399] ALERT_HANDLER_ALERT_CAUSE_96 + 4'b 0001, // index[400] ALERT_HANDLER_ALERT_CAUSE_97 + 4'b 0001, // index[401] ALERT_HANDLER_ALERT_CAUSE_98 + 4'b 0001, // index[402] ALERT_HANDLER_LOC_ALERT_REGWEN_0 + 4'b 0001, // index[403] ALERT_HANDLER_LOC_ALERT_REGWEN_1 + 4'b 0001, // index[404] ALERT_HANDLER_LOC_ALERT_REGWEN_2 + 4'b 0001, // index[405] ALERT_HANDLER_LOC_ALERT_REGWEN_3 + 4'b 0001, // index[406] ALERT_HANDLER_LOC_ALERT_REGWEN_4 + 4'b 0001, // index[407] ALERT_HANDLER_LOC_ALERT_REGWEN_5 + 4'b 0001, // index[408] ALERT_HANDLER_LOC_ALERT_REGWEN_6 + 4'b 0001, // index[409] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0 + 4'b 0001, // index[410] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1 + 4'b 0001, // index[411] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2 + 4'b 0001, // index[412] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3 + 4'b 0001, // index[413] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4 + 4'b 0001, // index[414] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5 + 4'b 0001, // index[415] ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6 + 4'b 0001, // index[416] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0 + 4'b 0001, // index[417] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1 + 4'b 0001, // index[418] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2 + 4'b 0001, // index[419] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3 + 4'b 0001, // index[420] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4 + 4'b 0001, // index[421] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5 + 4'b 0001, // index[422] ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6 + 4'b 0001, // index[423] ALERT_HANDLER_LOC_ALERT_CAUSE_0 + 4'b 0001, // index[424] ALERT_HANDLER_LOC_ALERT_CAUSE_1 + 4'b 0001, // index[425] ALERT_HANDLER_LOC_ALERT_CAUSE_2 + 4'b 0001, // index[426] ALERT_HANDLER_LOC_ALERT_CAUSE_3 + 4'b 0001, // index[427] ALERT_HANDLER_LOC_ALERT_CAUSE_4 + 4'b 0001, // index[428] ALERT_HANDLER_LOC_ALERT_CAUSE_5 + 4'b 0001, // index[429] ALERT_HANDLER_LOC_ALERT_CAUSE_6 + 4'b 0001, // index[430] ALERT_HANDLER_CLASSA_REGWEN + 4'b 0011, // index[431] ALERT_HANDLER_CLASSA_CTRL_SHADOWED + 4'b 0001, // index[432] ALERT_HANDLER_CLASSA_CLR_REGWEN + 4'b 0001, // index[433] ALERT_HANDLER_CLASSA_CLR_SHADOWED + 4'b 0011, // index[434] ALERT_HANDLER_CLASSA_ACCUM_CNT + 4'b 0011, // index[435] ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[436] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[437] ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[438] ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED + 4'b 1111, // index[439] ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED + 4'b 1111, // index[440] ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED + 4'b 1111, // index[441] ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED + 4'b 1111, // index[442] ALERT_HANDLER_CLASSA_ESC_CNT + 4'b 0001, // index[443] ALERT_HANDLER_CLASSA_STATE + 4'b 0001, // index[444] ALERT_HANDLER_CLASSB_REGWEN + 4'b 0011, // index[445] ALERT_HANDLER_CLASSB_CTRL_SHADOWED + 4'b 0001, // index[446] ALERT_HANDLER_CLASSB_CLR_REGWEN + 4'b 0001, // index[447] ALERT_HANDLER_CLASSB_CLR_SHADOWED + 4'b 0011, // index[448] ALERT_HANDLER_CLASSB_ACCUM_CNT + 4'b 0011, // index[449] ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[450] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[451] ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[452] ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED + 4'b 1111, // index[453] ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED + 4'b 1111, // index[454] ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED + 4'b 1111, // index[455] ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED + 4'b 1111, // index[456] ALERT_HANDLER_CLASSB_ESC_CNT + 4'b 0001, // index[457] ALERT_HANDLER_CLASSB_STATE + 4'b 0001, // index[458] ALERT_HANDLER_CLASSC_REGWEN + 4'b 0011, // index[459] ALERT_HANDLER_CLASSC_CTRL_SHADOWED + 4'b 0001, // index[460] ALERT_HANDLER_CLASSC_CLR_REGWEN + 4'b 0001, // index[461] ALERT_HANDLER_CLASSC_CLR_SHADOWED + 4'b 0011, // index[462] ALERT_HANDLER_CLASSC_ACCUM_CNT + 4'b 0011, // index[463] ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[464] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[465] ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[466] ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED + 4'b 1111, // index[467] ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED + 4'b 1111, // index[468] ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED + 4'b 1111, // index[469] ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED + 4'b 1111, // index[470] ALERT_HANDLER_CLASSC_ESC_CNT + 4'b 0001, // index[471] ALERT_HANDLER_CLASSC_STATE + 4'b 0001, // index[472] ALERT_HANDLER_CLASSD_REGWEN + 4'b 0011, // index[473] ALERT_HANDLER_CLASSD_CTRL_SHADOWED + 4'b 0001, // index[474] ALERT_HANDLER_CLASSD_CLR_REGWEN + 4'b 0001, // index[475] ALERT_HANDLER_CLASSD_CLR_SHADOWED + 4'b 0011, // index[476] ALERT_HANDLER_CLASSD_ACCUM_CNT + 4'b 0011, // index[477] ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED + 4'b 1111, // index[478] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED + 4'b 0001, // index[479] ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED + 4'b 1111, // index[480] ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED + 4'b 1111, // index[481] ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED + 4'b 1111, // index[482] ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED + 4'b 1111, // index[483] ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED + 4'b 1111, // index[484] ALERT_HANDLER_CLASSD_ESC_CNT + 4'b 0001 // index[485] ALERT_HANDLER_CLASSD_STATE + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv new file mode 100644 index 00000000000..e4a50acdbe3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_reg_top.sv @@ -0,0 +1,26810 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module alert_handler_reg_top ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write + input alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read + + output logic shadowed_storage_err_o, + output logic shadowed_update_err_o, + + // Integrity check errors + output logic intg_err_o +); + + import alert_handler_reg_pkg::* ; + + localparam int AW = 11; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [485:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(486) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic intr_state_classa_qs; + logic intr_state_classa_wd; + logic intr_state_classb_qs; + logic intr_state_classb_wd; + logic intr_state_classc_qs; + logic intr_state_classc_wd; + logic intr_state_classd_qs; + logic intr_state_classd_wd; + logic intr_enable_we; + logic intr_enable_classa_qs; + logic intr_enable_classa_wd; + logic intr_enable_classb_qs; + logic intr_enable_classb_wd; + logic intr_enable_classc_qs; + logic intr_enable_classc_wd; + logic intr_enable_classd_qs; + logic intr_enable_classd_wd; + logic intr_test_we; + logic intr_test_classa_wd; + logic intr_test_classb_wd; + logic intr_test_classc_wd; + logic intr_test_classd_wd; + logic ping_timer_regwen_we; + logic ping_timer_regwen_qs; + logic ping_timer_regwen_wd; + logic ping_timeout_cyc_shadowed_re; + logic ping_timeout_cyc_shadowed_we; + logic [15:0] ping_timeout_cyc_shadowed_qs; + logic [15:0] ping_timeout_cyc_shadowed_wd; + logic ping_timeout_cyc_shadowed_storage_err; + logic ping_timeout_cyc_shadowed_update_err; + logic ping_timer_en_shadowed_re; + logic ping_timer_en_shadowed_we; + logic ping_timer_en_shadowed_qs; + logic ping_timer_en_shadowed_wd; + logic ping_timer_en_shadowed_storage_err; + logic ping_timer_en_shadowed_update_err; + logic alert_regwen_0_we; + logic alert_regwen_0_qs; + logic alert_regwen_0_wd; + logic alert_regwen_1_we; + logic alert_regwen_1_qs; + logic alert_regwen_1_wd; + logic alert_regwen_2_we; + logic alert_regwen_2_qs; + logic alert_regwen_2_wd; + logic alert_regwen_3_we; + logic alert_regwen_3_qs; + logic alert_regwen_3_wd; + logic alert_regwen_4_we; + logic alert_regwen_4_qs; + logic alert_regwen_4_wd; + logic alert_regwen_5_we; + logic alert_regwen_5_qs; + logic alert_regwen_5_wd; + logic alert_regwen_6_we; + logic alert_regwen_6_qs; + logic alert_regwen_6_wd; + logic alert_regwen_7_we; + logic alert_regwen_7_qs; + logic alert_regwen_7_wd; + logic alert_regwen_8_we; + logic alert_regwen_8_qs; + logic alert_regwen_8_wd; + logic alert_regwen_9_we; + logic alert_regwen_9_qs; + logic alert_regwen_9_wd; + logic alert_regwen_10_we; + logic alert_regwen_10_qs; + logic alert_regwen_10_wd; + logic alert_regwen_11_we; + logic alert_regwen_11_qs; + logic alert_regwen_11_wd; + logic alert_regwen_12_we; + logic alert_regwen_12_qs; + logic alert_regwen_12_wd; + logic alert_regwen_13_we; + logic alert_regwen_13_qs; + logic alert_regwen_13_wd; + logic alert_regwen_14_we; + logic alert_regwen_14_qs; + logic alert_regwen_14_wd; + logic alert_regwen_15_we; + logic alert_regwen_15_qs; + logic alert_regwen_15_wd; + logic alert_regwen_16_we; + logic alert_regwen_16_qs; + logic alert_regwen_16_wd; + logic alert_regwen_17_we; + logic alert_regwen_17_qs; + logic alert_regwen_17_wd; + logic alert_regwen_18_we; + logic alert_regwen_18_qs; + logic alert_regwen_18_wd; + logic alert_regwen_19_we; + logic alert_regwen_19_qs; + logic alert_regwen_19_wd; + logic alert_regwen_20_we; + logic alert_regwen_20_qs; + logic alert_regwen_20_wd; + logic alert_regwen_21_we; + logic alert_regwen_21_qs; + logic alert_regwen_21_wd; + logic alert_regwen_22_we; + logic alert_regwen_22_qs; + logic alert_regwen_22_wd; + logic alert_regwen_23_we; + logic alert_regwen_23_qs; + logic alert_regwen_23_wd; + logic alert_regwen_24_we; + logic alert_regwen_24_qs; + logic alert_regwen_24_wd; + logic alert_regwen_25_we; + logic alert_regwen_25_qs; + logic alert_regwen_25_wd; + logic alert_regwen_26_we; + logic alert_regwen_26_qs; + logic alert_regwen_26_wd; + logic alert_regwen_27_we; + logic alert_regwen_27_qs; + logic alert_regwen_27_wd; + logic alert_regwen_28_we; + logic alert_regwen_28_qs; + logic alert_regwen_28_wd; + logic alert_regwen_29_we; + logic alert_regwen_29_qs; + logic alert_regwen_29_wd; + logic alert_regwen_30_we; + logic alert_regwen_30_qs; + logic alert_regwen_30_wd; + logic alert_regwen_31_we; + logic alert_regwen_31_qs; + logic alert_regwen_31_wd; + logic alert_regwen_32_we; + logic alert_regwen_32_qs; + logic alert_regwen_32_wd; + logic alert_regwen_33_we; + logic alert_regwen_33_qs; + logic alert_regwen_33_wd; + logic alert_regwen_34_we; + logic alert_regwen_34_qs; + logic alert_regwen_34_wd; + logic alert_regwen_35_we; + logic alert_regwen_35_qs; + logic alert_regwen_35_wd; + logic alert_regwen_36_we; + logic alert_regwen_36_qs; + logic alert_regwen_36_wd; + logic alert_regwen_37_we; + logic alert_regwen_37_qs; + logic alert_regwen_37_wd; + logic alert_regwen_38_we; + logic alert_regwen_38_qs; + logic alert_regwen_38_wd; + logic alert_regwen_39_we; + logic alert_regwen_39_qs; + logic alert_regwen_39_wd; + logic alert_regwen_40_we; + logic alert_regwen_40_qs; + logic alert_regwen_40_wd; + logic alert_regwen_41_we; + logic alert_regwen_41_qs; + logic alert_regwen_41_wd; + logic alert_regwen_42_we; + logic alert_regwen_42_qs; + logic alert_regwen_42_wd; + logic alert_regwen_43_we; + logic alert_regwen_43_qs; + logic alert_regwen_43_wd; + logic alert_regwen_44_we; + logic alert_regwen_44_qs; + logic alert_regwen_44_wd; + logic alert_regwen_45_we; + logic alert_regwen_45_qs; + logic alert_regwen_45_wd; + logic alert_regwen_46_we; + logic alert_regwen_46_qs; + logic alert_regwen_46_wd; + logic alert_regwen_47_we; + logic alert_regwen_47_qs; + logic alert_regwen_47_wd; + logic alert_regwen_48_we; + logic alert_regwen_48_qs; + logic alert_regwen_48_wd; + logic alert_regwen_49_we; + logic alert_regwen_49_qs; + logic alert_regwen_49_wd; + logic alert_regwen_50_we; + logic alert_regwen_50_qs; + logic alert_regwen_50_wd; + logic alert_regwen_51_we; + logic alert_regwen_51_qs; + logic alert_regwen_51_wd; + logic alert_regwen_52_we; + logic alert_regwen_52_qs; + logic alert_regwen_52_wd; + logic alert_regwen_53_we; + logic alert_regwen_53_qs; + logic alert_regwen_53_wd; + logic alert_regwen_54_we; + logic alert_regwen_54_qs; + logic alert_regwen_54_wd; + logic alert_regwen_55_we; + logic alert_regwen_55_qs; + logic alert_regwen_55_wd; + logic alert_regwen_56_we; + logic alert_regwen_56_qs; + logic alert_regwen_56_wd; + logic alert_regwen_57_we; + logic alert_regwen_57_qs; + logic alert_regwen_57_wd; + logic alert_regwen_58_we; + logic alert_regwen_58_qs; + logic alert_regwen_58_wd; + logic alert_regwen_59_we; + logic alert_regwen_59_qs; + logic alert_regwen_59_wd; + logic alert_regwen_60_we; + logic alert_regwen_60_qs; + logic alert_regwen_60_wd; + logic alert_regwen_61_we; + logic alert_regwen_61_qs; + logic alert_regwen_61_wd; + logic alert_regwen_62_we; + logic alert_regwen_62_qs; + logic alert_regwen_62_wd; + logic alert_regwen_63_we; + logic alert_regwen_63_qs; + logic alert_regwen_63_wd; + logic alert_regwen_64_we; + logic alert_regwen_64_qs; + logic alert_regwen_64_wd; + logic alert_regwen_65_we; + logic alert_regwen_65_qs; + logic alert_regwen_65_wd; + logic alert_regwen_66_we; + logic alert_regwen_66_qs; + logic alert_regwen_66_wd; + logic alert_regwen_67_we; + logic alert_regwen_67_qs; + logic alert_regwen_67_wd; + logic alert_regwen_68_we; + logic alert_regwen_68_qs; + logic alert_regwen_68_wd; + logic alert_regwen_69_we; + logic alert_regwen_69_qs; + logic alert_regwen_69_wd; + logic alert_regwen_70_we; + logic alert_regwen_70_qs; + logic alert_regwen_70_wd; + logic alert_regwen_71_we; + logic alert_regwen_71_qs; + logic alert_regwen_71_wd; + logic alert_regwen_72_we; + logic alert_regwen_72_qs; + logic alert_regwen_72_wd; + logic alert_regwen_73_we; + logic alert_regwen_73_qs; + logic alert_regwen_73_wd; + logic alert_regwen_74_we; + logic alert_regwen_74_qs; + logic alert_regwen_74_wd; + logic alert_regwen_75_we; + logic alert_regwen_75_qs; + logic alert_regwen_75_wd; + logic alert_regwen_76_we; + logic alert_regwen_76_qs; + logic alert_regwen_76_wd; + logic alert_regwen_77_we; + logic alert_regwen_77_qs; + logic alert_regwen_77_wd; + logic alert_regwen_78_we; + logic alert_regwen_78_qs; + logic alert_regwen_78_wd; + logic alert_regwen_79_we; + logic alert_regwen_79_qs; + logic alert_regwen_79_wd; + logic alert_regwen_80_we; + logic alert_regwen_80_qs; + logic alert_regwen_80_wd; + logic alert_regwen_81_we; + logic alert_regwen_81_qs; + logic alert_regwen_81_wd; + logic alert_regwen_82_we; + logic alert_regwen_82_qs; + logic alert_regwen_82_wd; + logic alert_regwen_83_we; + logic alert_regwen_83_qs; + logic alert_regwen_83_wd; + logic alert_regwen_84_we; + logic alert_regwen_84_qs; + logic alert_regwen_84_wd; + logic alert_regwen_85_we; + logic alert_regwen_85_qs; + logic alert_regwen_85_wd; + logic alert_regwen_86_we; + logic alert_regwen_86_qs; + logic alert_regwen_86_wd; + logic alert_regwen_87_we; + logic alert_regwen_87_qs; + logic alert_regwen_87_wd; + logic alert_regwen_88_we; + logic alert_regwen_88_qs; + logic alert_regwen_88_wd; + logic alert_regwen_89_we; + logic alert_regwen_89_qs; + logic alert_regwen_89_wd; + logic alert_regwen_90_we; + logic alert_regwen_90_qs; + logic alert_regwen_90_wd; + logic alert_regwen_91_we; + logic alert_regwen_91_qs; + logic alert_regwen_91_wd; + logic alert_regwen_92_we; + logic alert_regwen_92_qs; + logic alert_regwen_92_wd; + logic alert_regwen_93_we; + logic alert_regwen_93_qs; + logic alert_regwen_93_wd; + logic alert_regwen_94_we; + logic alert_regwen_94_qs; + logic alert_regwen_94_wd; + logic alert_regwen_95_we; + logic alert_regwen_95_qs; + logic alert_regwen_95_wd; + logic alert_regwen_96_we; + logic alert_regwen_96_qs; + logic alert_regwen_96_wd; + logic alert_regwen_97_we; + logic alert_regwen_97_qs; + logic alert_regwen_97_wd; + logic alert_regwen_98_we; + logic alert_regwen_98_qs; + logic alert_regwen_98_wd; + logic alert_en_shadowed_0_re; + logic alert_en_shadowed_0_we; + logic alert_en_shadowed_0_qs; + logic alert_en_shadowed_0_wd; + logic alert_en_shadowed_0_storage_err; + logic alert_en_shadowed_0_update_err; + logic alert_en_shadowed_1_re; + logic alert_en_shadowed_1_we; + logic alert_en_shadowed_1_qs; + logic alert_en_shadowed_1_wd; + logic alert_en_shadowed_1_storage_err; + logic alert_en_shadowed_1_update_err; + logic alert_en_shadowed_2_re; + logic alert_en_shadowed_2_we; + logic alert_en_shadowed_2_qs; + logic alert_en_shadowed_2_wd; + logic alert_en_shadowed_2_storage_err; + logic alert_en_shadowed_2_update_err; + logic alert_en_shadowed_3_re; + logic alert_en_shadowed_3_we; + logic alert_en_shadowed_3_qs; + logic alert_en_shadowed_3_wd; + logic alert_en_shadowed_3_storage_err; + logic alert_en_shadowed_3_update_err; + logic alert_en_shadowed_4_re; + logic alert_en_shadowed_4_we; + logic alert_en_shadowed_4_qs; + logic alert_en_shadowed_4_wd; + logic alert_en_shadowed_4_storage_err; + logic alert_en_shadowed_4_update_err; + logic alert_en_shadowed_5_re; + logic alert_en_shadowed_5_we; + logic alert_en_shadowed_5_qs; + logic alert_en_shadowed_5_wd; + logic alert_en_shadowed_5_storage_err; + logic alert_en_shadowed_5_update_err; + logic alert_en_shadowed_6_re; + logic alert_en_shadowed_6_we; + logic alert_en_shadowed_6_qs; + logic alert_en_shadowed_6_wd; + logic alert_en_shadowed_6_storage_err; + logic alert_en_shadowed_6_update_err; + logic alert_en_shadowed_7_re; + logic alert_en_shadowed_7_we; + logic alert_en_shadowed_7_qs; + logic alert_en_shadowed_7_wd; + logic alert_en_shadowed_7_storage_err; + logic alert_en_shadowed_7_update_err; + logic alert_en_shadowed_8_re; + logic alert_en_shadowed_8_we; + logic alert_en_shadowed_8_qs; + logic alert_en_shadowed_8_wd; + logic alert_en_shadowed_8_storage_err; + logic alert_en_shadowed_8_update_err; + logic alert_en_shadowed_9_re; + logic alert_en_shadowed_9_we; + logic alert_en_shadowed_9_qs; + logic alert_en_shadowed_9_wd; + logic alert_en_shadowed_9_storage_err; + logic alert_en_shadowed_9_update_err; + logic alert_en_shadowed_10_re; + logic alert_en_shadowed_10_we; + logic alert_en_shadowed_10_qs; + logic alert_en_shadowed_10_wd; + logic alert_en_shadowed_10_storage_err; + logic alert_en_shadowed_10_update_err; + logic alert_en_shadowed_11_re; + logic alert_en_shadowed_11_we; + logic alert_en_shadowed_11_qs; + logic alert_en_shadowed_11_wd; + logic alert_en_shadowed_11_storage_err; + logic alert_en_shadowed_11_update_err; + logic alert_en_shadowed_12_re; + logic alert_en_shadowed_12_we; + logic alert_en_shadowed_12_qs; + logic alert_en_shadowed_12_wd; + logic alert_en_shadowed_12_storage_err; + logic alert_en_shadowed_12_update_err; + logic alert_en_shadowed_13_re; + logic alert_en_shadowed_13_we; + logic alert_en_shadowed_13_qs; + logic alert_en_shadowed_13_wd; + logic alert_en_shadowed_13_storage_err; + logic alert_en_shadowed_13_update_err; + logic alert_en_shadowed_14_re; + logic alert_en_shadowed_14_we; + logic alert_en_shadowed_14_qs; + logic alert_en_shadowed_14_wd; + logic alert_en_shadowed_14_storage_err; + logic alert_en_shadowed_14_update_err; + logic alert_en_shadowed_15_re; + logic alert_en_shadowed_15_we; + logic alert_en_shadowed_15_qs; + logic alert_en_shadowed_15_wd; + logic alert_en_shadowed_15_storage_err; + logic alert_en_shadowed_15_update_err; + logic alert_en_shadowed_16_re; + logic alert_en_shadowed_16_we; + logic alert_en_shadowed_16_qs; + logic alert_en_shadowed_16_wd; + logic alert_en_shadowed_16_storage_err; + logic alert_en_shadowed_16_update_err; + logic alert_en_shadowed_17_re; + logic alert_en_shadowed_17_we; + logic alert_en_shadowed_17_qs; + logic alert_en_shadowed_17_wd; + logic alert_en_shadowed_17_storage_err; + logic alert_en_shadowed_17_update_err; + logic alert_en_shadowed_18_re; + logic alert_en_shadowed_18_we; + logic alert_en_shadowed_18_qs; + logic alert_en_shadowed_18_wd; + logic alert_en_shadowed_18_storage_err; + logic alert_en_shadowed_18_update_err; + logic alert_en_shadowed_19_re; + logic alert_en_shadowed_19_we; + logic alert_en_shadowed_19_qs; + logic alert_en_shadowed_19_wd; + logic alert_en_shadowed_19_storage_err; + logic alert_en_shadowed_19_update_err; + logic alert_en_shadowed_20_re; + logic alert_en_shadowed_20_we; + logic alert_en_shadowed_20_qs; + logic alert_en_shadowed_20_wd; + logic alert_en_shadowed_20_storage_err; + logic alert_en_shadowed_20_update_err; + logic alert_en_shadowed_21_re; + logic alert_en_shadowed_21_we; + logic alert_en_shadowed_21_qs; + logic alert_en_shadowed_21_wd; + logic alert_en_shadowed_21_storage_err; + logic alert_en_shadowed_21_update_err; + logic alert_en_shadowed_22_re; + logic alert_en_shadowed_22_we; + logic alert_en_shadowed_22_qs; + logic alert_en_shadowed_22_wd; + logic alert_en_shadowed_22_storage_err; + logic alert_en_shadowed_22_update_err; + logic alert_en_shadowed_23_re; + logic alert_en_shadowed_23_we; + logic alert_en_shadowed_23_qs; + logic alert_en_shadowed_23_wd; + logic alert_en_shadowed_23_storage_err; + logic alert_en_shadowed_23_update_err; + logic alert_en_shadowed_24_re; + logic alert_en_shadowed_24_we; + logic alert_en_shadowed_24_qs; + logic alert_en_shadowed_24_wd; + logic alert_en_shadowed_24_storage_err; + logic alert_en_shadowed_24_update_err; + logic alert_en_shadowed_25_re; + logic alert_en_shadowed_25_we; + logic alert_en_shadowed_25_qs; + logic alert_en_shadowed_25_wd; + logic alert_en_shadowed_25_storage_err; + logic alert_en_shadowed_25_update_err; + logic alert_en_shadowed_26_re; + logic alert_en_shadowed_26_we; + logic alert_en_shadowed_26_qs; + logic alert_en_shadowed_26_wd; + logic alert_en_shadowed_26_storage_err; + logic alert_en_shadowed_26_update_err; + logic alert_en_shadowed_27_re; + logic alert_en_shadowed_27_we; + logic alert_en_shadowed_27_qs; + logic alert_en_shadowed_27_wd; + logic alert_en_shadowed_27_storage_err; + logic alert_en_shadowed_27_update_err; + logic alert_en_shadowed_28_re; + logic alert_en_shadowed_28_we; + logic alert_en_shadowed_28_qs; + logic alert_en_shadowed_28_wd; + logic alert_en_shadowed_28_storage_err; + logic alert_en_shadowed_28_update_err; + logic alert_en_shadowed_29_re; + logic alert_en_shadowed_29_we; + logic alert_en_shadowed_29_qs; + logic alert_en_shadowed_29_wd; + logic alert_en_shadowed_29_storage_err; + logic alert_en_shadowed_29_update_err; + logic alert_en_shadowed_30_re; + logic alert_en_shadowed_30_we; + logic alert_en_shadowed_30_qs; + logic alert_en_shadowed_30_wd; + logic alert_en_shadowed_30_storage_err; + logic alert_en_shadowed_30_update_err; + logic alert_en_shadowed_31_re; + logic alert_en_shadowed_31_we; + logic alert_en_shadowed_31_qs; + logic alert_en_shadowed_31_wd; + logic alert_en_shadowed_31_storage_err; + logic alert_en_shadowed_31_update_err; + logic alert_en_shadowed_32_re; + logic alert_en_shadowed_32_we; + logic alert_en_shadowed_32_qs; + logic alert_en_shadowed_32_wd; + logic alert_en_shadowed_32_storage_err; + logic alert_en_shadowed_32_update_err; + logic alert_en_shadowed_33_re; + logic alert_en_shadowed_33_we; + logic alert_en_shadowed_33_qs; + logic alert_en_shadowed_33_wd; + logic alert_en_shadowed_33_storage_err; + logic alert_en_shadowed_33_update_err; + logic alert_en_shadowed_34_re; + logic alert_en_shadowed_34_we; + logic alert_en_shadowed_34_qs; + logic alert_en_shadowed_34_wd; + logic alert_en_shadowed_34_storage_err; + logic alert_en_shadowed_34_update_err; + logic alert_en_shadowed_35_re; + logic alert_en_shadowed_35_we; + logic alert_en_shadowed_35_qs; + logic alert_en_shadowed_35_wd; + logic alert_en_shadowed_35_storage_err; + logic alert_en_shadowed_35_update_err; + logic alert_en_shadowed_36_re; + logic alert_en_shadowed_36_we; + logic alert_en_shadowed_36_qs; + logic alert_en_shadowed_36_wd; + logic alert_en_shadowed_36_storage_err; + logic alert_en_shadowed_36_update_err; + logic alert_en_shadowed_37_re; + logic alert_en_shadowed_37_we; + logic alert_en_shadowed_37_qs; + logic alert_en_shadowed_37_wd; + logic alert_en_shadowed_37_storage_err; + logic alert_en_shadowed_37_update_err; + logic alert_en_shadowed_38_re; + logic alert_en_shadowed_38_we; + logic alert_en_shadowed_38_qs; + logic alert_en_shadowed_38_wd; + logic alert_en_shadowed_38_storage_err; + logic alert_en_shadowed_38_update_err; + logic alert_en_shadowed_39_re; + logic alert_en_shadowed_39_we; + logic alert_en_shadowed_39_qs; + logic alert_en_shadowed_39_wd; + logic alert_en_shadowed_39_storage_err; + logic alert_en_shadowed_39_update_err; + logic alert_en_shadowed_40_re; + logic alert_en_shadowed_40_we; + logic alert_en_shadowed_40_qs; + logic alert_en_shadowed_40_wd; + logic alert_en_shadowed_40_storage_err; + logic alert_en_shadowed_40_update_err; + logic alert_en_shadowed_41_re; + logic alert_en_shadowed_41_we; + logic alert_en_shadowed_41_qs; + logic alert_en_shadowed_41_wd; + logic alert_en_shadowed_41_storage_err; + logic alert_en_shadowed_41_update_err; + logic alert_en_shadowed_42_re; + logic alert_en_shadowed_42_we; + logic alert_en_shadowed_42_qs; + logic alert_en_shadowed_42_wd; + logic alert_en_shadowed_42_storage_err; + logic alert_en_shadowed_42_update_err; + logic alert_en_shadowed_43_re; + logic alert_en_shadowed_43_we; + logic alert_en_shadowed_43_qs; + logic alert_en_shadowed_43_wd; + logic alert_en_shadowed_43_storage_err; + logic alert_en_shadowed_43_update_err; + logic alert_en_shadowed_44_re; + logic alert_en_shadowed_44_we; + logic alert_en_shadowed_44_qs; + logic alert_en_shadowed_44_wd; + logic alert_en_shadowed_44_storage_err; + logic alert_en_shadowed_44_update_err; + logic alert_en_shadowed_45_re; + logic alert_en_shadowed_45_we; + logic alert_en_shadowed_45_qs; + logic alert_en_shadowed_45_wd; + logic alert_en_shadowed_45_storage_err; + logic alert_en_shadowed_45_update_err; + logic alert_en_shadowed_46_re; + logic alert_en_shadowed_46_we; + logic alert_en_shadowed_46_qs; + logic alert_en_shadowed_46_wd; + logic alert_en_shadowed_46_storage_err; + logic alert_en_shadowed_46_update_err; + logic alert_en_shadowed_47_re; + logic alert_en_shadowed_47_we; + logic alert_en_shadowed_47_qs; + logic alert_en_shadowed_47_wd; + logic alert_en_shadowed_47_storage_err; + logic alert_en_shadowed_47_update_err; + logic alert_en_shadowed_48_re; + logic alert_en_shadowed_48_we; + logic alert_en_shadowed_48_qs; + logic alert_en_shadowed_48_wd; + logic alert_en_shadowed_48_storage_err; + logic alert_en_shadowed_48_update_err; + logic alert_en_shadowed_49_re; + logic alert_en_shadowed_49_we; + logic alert_en_shadowed_49_qs; + logic alert_en_shadowed_49_wd; + logic alert_en_shadowed_49_storage_err; + logic alert_en_shadowed_49_update_err; + logic alert_en_shadowed_50_re; + logic alert_en_shadowed_50_we; + logic alert_en_shadowed_50_qs; + logic alert_en_shadowed_50_wd; + logic alert_en_shadowed_50_storage_err; + logic alert_en_shadowed_50_update_err; + logic alert_en_shadowed_51_re; + logic alert_en_shadowed_51_we; + logic alert_en_shadowed_51_qs; + logic alert_en_shadowed_51_wd; + logic alert_en_shadowed_51_storage_err; + logic alert_en_shadowed_51_update_err; + logic alert_en_shadowed_52_re; + logic alert_en_shadowed_52_we; + logic alert_en_shadowed_52_qs; + logic alert_en_shadowed_52_wd; + logic alert_en_shadowed_52_storage_err; + logic alert_en_shadowed_52_update_err; + logic alert_en_shadowed_53_re; + logic alert_en_shadowed_53_we; + logic alert_en_shadowed_53_qs; + logic alert_en_shadowed_53_wd; + logic alert_en_shadowed_53_storage_err; + logic alert_en_shadowed_53_update_err; + logic alert_en_shadowed_54_re; + logic alert_en_shadowed_54_we; + logic alert_en_shadowed_54_qs; + logic alert_en_shadowed_54_wd; + logic alert_en_shadowed_54_storage_err; + logic alert_en_shadowed_54_update_err; + logic alert_en_shadowed_55_re; + logic alert_en_shadowed_55_we; + logic alert_en_shadowed_55_qs; + logic alert_en_shadowed_55_wd; + logic alert_en_shadowed_55_storage_err; + logic alert_en_shadowed_55_update_err; + logic alert_en_shadowed_56_re; + logic alert_en_shadowed_56_we; + logic alert_en_shadowed_56_qs; + logic alert_en_shadowed_56_wd; + logic alert_en_shadowed_56_storage_err; + logic alert_en_shadowed_56_update_err; + logic alert_en_shadowed_57_re; + logic alert_en_shadowed_57_we; + logic alert_en_shadowed_57_qs; + logic alert_en_shadowed_57_wd; + logic alert_en_shadowed_57_storage_err; + logic alert_en_shadowed_57_update_err; + logic alert_en_shadowed_58_re; + logic alert_en_shadowed_58_we; + logic alert_en_shadowed_58_qs; + logic alert_en_shadowed_58_wd; + logic alert_en_shadowed_58_storage_err; + logic alert_en_shadowed_58_update_err; + logic alert_en_shadowed_59_re; + logic alert_en_shadowed_59_we; + logic alert_en_shadowed_59_qs; + logic alert_en_shadowed_59_wd; + logic alert_en_shadowed_59_storage_err; + logic alert_en_shadowed_59_update_err; + logic alert_en_shadowed_60_re; + logic alert_en_shadowed_60_we; + logic alert_en_shadowed_60_qs; + logic alert_en_shadowed_60_wd; + logic alert_en_shadowed_60_storage_err; + logic alert_en_shadowed_60_update_err; + logic alert_en_shadowed_61_re; + logic alert_en_shadowed_61_we; + logic alert_en_shadowed_61_qs; + logic alert_en_shadowed_61_wd; + logic alert_en_shadowed_61_storage_err; + logic alert_en_shadowed_61_update_err; + logic alert_en_shadowed_62_re; + logic alert_en_shadowed_62_we; + logic alert_en_shadowed_62_qs; + logic alert_en_shadowed_62_wd; + logic alert_en_shadowed_62_storage_err; + logic alert_en_shadowed_62_update_err; + logic alert_en_shadowed_63_re; + logic alert_en_shadowed_63_we; + logic alert_en_shadowed_63_qs; + logic alert_en_shadowed_63_wd; + logic alert_en_shadowed_63_storage_err; + logic alert_en_shadowed_63_update_err; + logic alert_en_shadowed_64_re; + logic alert_en_shadowed_64_we; + logic alert_en_shadowed_64_qs; + logic alert_en_shadowed_64_wd; + logic alert_en_shadowed_64_storage_err; + logic alert_en_shadowed_64_update_err; + logic alert_en_shadowed_65_re; + logic alert_en_shadowed_65_we; + logic alert_en_shadowed_65_qs; + logic alert_en_shadowed_65_wd; + logic alert_en_shadowed_65_storage_err; + logic alert_en_shadowed_65_update_err; + logic alert_en_shadowed_66_re; + logic alert_en_shadowed_66_we; + logic alert_en_shadowed_66_qs; + logic alert_en_shadowed_66_wd; + logic alert_en_shadowed_66_storage_err; + logic alert_en_shadowed_66_update_err; + logic alert_en_shadowed_67_re; + logic alert_en_shadowed_67_we; + logic alert_en_shadowed_67_qs; + logic alert_en_shadowed_67_wd; + logic alert_en_shadowed_67_storage_err; + logic alert_en_shadowed_67_update_err; + logic alert_en_shadowed_68_re; + logic alert_en_shadowed_68_we; + logic alert_en_shadowed_68_qs; + logic alert_en_shadowed_68_wd; + logic alert_en_shadowed_68_storage_err; + logic alert_en_shadowed_68_update_err; + logic alert_en_shadowed_69_re; + logic alert_en_shadowed_69_we; + logic alert_en_shadowed_69_qs; + logic alert_en_shadowed_69_wd; + logic alert_en_shadowed_69_storage_err; + logic alert_en_shadowed_69_update_err; + logic alert_en_shadowed_70_re; + logic alert_en_shadowed_70_we; + logic alert_en_shadowed_70_qs; + logic alert_en_shadowed_70_wd; + logic alert_en_shadowed_70_storage_err; + logic alert_en_shadowed_70_update_err; + logic alert_en_shadowed_71_re; + logic alert_en_shadowed_71_we; + logic alert_en_shadowed_71_qs; + logic alert_en_shadowed_71_wd; + logic alert_en_shadowed_71_storage_err; + logic alert_en_shadowed_71_update_err; + logic alert_en_shadowed_72_re; + logic alert_en_shadowed_72_we; + logic alert_en_shadowed_72_qs; + logic alert_en_shadowed_72_wd; + logic alert_en_shadowed_72_storage_err; + logic alert_en_shadowed_72_update_err; + logic alert_en_shadowed_73_re; + logic alert_en_shadowed_73_we; + logic alert_en_shadowed_73_qs; + logic alert_en_shadowed_73_wd; + logic alert_en_shadowed_73_storage_err; + logic alert_en_shadowed_73_update_err; + logic alert_en_shadowed_74_re; + logic alert_en_shadowed_74_we; + logic alert_en_shadowed_74_qs; + logic alert_en_shadowed_74_wd; + logic alert_en_shadowed_74_storage_err; + logic alert_en_shadowed_74_update_err; + logic alert_en_shadowed_75_re; + logic alert_en_shadowed_75_we; + logic alert_en_shadowed_75_qs; + logic alert_en_shadowed_75_wd; + logic alert_en_shadowed_75_storage_err; + logic alert_en_shadowed_75_update_err; + logic alert_en_shadowed_76_re; + logic alert_en_shadowed_76_we; + logic alert_en_shadowed_76_qs; + logic alert_en_shadowed_76_wd; + logic alert_en_shadowed_76_storage_err; + logic alert_en_shadowed_76_update_err; + logic alert_en_shadowed_77_re; + logic alert_en_shadowed_77_we; + logic alert_en_shadowed_77_qs; + logic alert_en_shadowed_77_wd; + logic alert_en_shadowed_77_storage_err; + logic alert_en_shadowed_77_update_err; + logic alert_en_shadowed_78_re; + logic alert_en_shadowed_78_we; + logic alert_en_shadowed_78_qs; + logic alert_en_shadowed_78_wd; + logic alert_en_shadowed_78_storage_err; + logic alert_en_shadowed_78_update_err; + logic alert_en_shadowed_79_re; + logic alert_en_shadowed_79_we; + logic alert_en_shadowed_79_qs; + logic alert_en_shadowed_79_wd; + logic alert_en_shadowed_79_storage_err; + logic alert_en_shadowed_79_update_err; + logic alert_en_shadowed_80_re; + logic alert_en_shadowed_80_we; + logic alert_en_shadowed_80_qs; + logic alert_en_shadowed_80_wd; + logic alert_en_shadowed_80_storage_err; + logic alert_en_shadowed_80_update_err; + logic alert_en_shadowed_81_re; + logic alert_en_shadowed_81_we; + logic alert_en_shadowed_81_qs; + logic alert_en_shadowed_81_wd; + logic alert_en_shadowed_81_storage_err; + logic alert_en_shadowed_81_update_err; + logic alert_en_shadowed_82_re; + logic alert_en_shadowed_82_we; + logic alert_en_shadowed_82_qs; + logic alert_en_shadowed_82_wd; + logic alert_en_shadowed_82_storage_err; + logic alert_en_shadowed_82_update_err; + logic alert_en_shadowed_83_re; + logic alert_en_shadowed_83_we; + logic alert_en_shadowed_83_qs; + logic alert_en_shadowed_83_wd; + logic alert_en_shadowed_83_storage_err; + logic alert_en_shadowed_83_update_err; + logic alert_en_shadowed_84_re; + logic alert_en_shadowed_84_we; + logic alert_en_shadowed_84_qs; + logic alert_en_shadowed_84_wd; + logic alert_en_shadowed_84_storage_err; + logic alert_en_shadowed_84_update_err; + logic alert_en_shadowed_85_re; + logic alert_en_shadowed_85_we; + logic alert_en_shadowed_85_qs; + logic alert_en_shadowed_85_wd; + logic alert_en_shadowed_85_storage_err; + logic alert_en_shadowed_85_update_err; + logic alert_en_shadowed_86_re; + logic alert_en_shadowed_86_we; + logic alert_en_shadowed_86_qs; + logic alert_en_shadowed_86_wd; + logic alert_en_shadowed_86_storage_err; + logic alert_en_shadowed_86_update_err; + logic alert_en_shadowed_87_re; + logic alert_en_shadowed_87_we; + logic alert_en_shadowed_87_qs; + logic alert_en_shadowed_87_wd; + logic alert_en_shadowed_87_storage_err; + logic alert_en_shadowed_87_update_err; + logic alert_en_shadowed_88_re; + logic alert_en_shadowed_88_we; + logic alert_en_shadowed_88_qs; + logic alert_en_shadowed_88_wd; + logic alert_en_shadowed_88_storage_err; + logic alert_en_shadowed_88_update_err; + logic alert_en_shadowed_89_re; + logic alert_en_shadowed_89_we; + logic alert_en_shadowed_89_qs; + logic alert_en_shadowed_89_wd; + logic alert_en_shadowed_89_storage_err; + logic alert_en_shadowed_89_update_err; + logic alert_en_shadowed_90_re; + logic alert_en_shadowed_90_we; + logic alert_en_shadowed_90_qs; + logic alert_en_shadowed_90_wd; + logic alert_en_shadowed_90_storage_err; + logic alert_en_shadowed_90_update_err; + logic alert_en_shadowed_91_re; + logic alert_en_shadowed_91_we; + logic alert_en_shadowed_91_qs; + logic alert_en_shadowed_91_wd; + logic alert_en_shadowed_91_storage_err; + logic alert_en_shadowed_91_update_err; + logic alert_en_shadowed_92_re; + logic alert_en_shadowed_92_we; + logic alert_en_shadowed_92_qs; + logic alert_en_shadowed_92_wd; + logic alert_en_shadowed_92_storage_err; + logic alert_en_shadowed_92_update_err; + logic alert_en_shadowed_93_re; + logic alert_en_shadowed_93_we; + logic alert_en_shadowed_93_qs; + logic alert_en_shadowed_93_wd; + logic alert_en_shadowed_93_storage_err; + logic alert_en_shadowed_93_update_err; + logic alert_en_shadowed_94_re; + logic alert_en_shadowed_94_we; + logic alert_en_shadowed_94_qs; + logic alert_en_shadowed_94_wd; + logic alert_en_shadowed_94_storage_err; + logic alert_en_shadowed_94_update_err; + logic alert_en_shadowed_95_re; + logic alert_en_shadowed_95_we; + logic alert_en_shadowed_95_qs; + logic alert_en_shadowed_95_wd; + logic alert_en_shadowed_95_storage_err; + logic alert_en_shadowed_95_update_err; + logic alert_en_shadowed_96_re; + logic alert_en_shadowed_96_we; + logic alert_en_shadowed_96_qs; + logic alert_en_shadowed_96_wd; + logic alert_en_shadowed_96_storage_err; + logic alert_en_shadowed_96_update_err; + logic alert_en_shadowed_97_re; + logic alert_en_shadowed_97_we; + logic alert_en_shadowed_97_qs; + logic alert_en_shadowed_97_wd; + logic alert_en_shadowed_97_storage_err; + logic alert_en_shadowed_97_update_err; + logic alert_en_shadowed_98_re; + logic alert_en_shadowed_98_we; + logic alert_en_shadowed_98_qs; + logic alert_en_shadowed_98_wd; + logic alert_en_shadowed_98_storage_err; + logic alert_en_shadowed_98_update_err; + logic alert_class_shadowed_0_re; + logic alert_class_shadowed_0_we; + logic [1:0] alert_class_shadowed_0_qs; + logic [1:0] alert_class_shadowed_0_wd; + logic alert_class_shadowed_0_storage_err; + logic alert_class_shadowed_0_update_err; + logic alert_class_shadowed_1_re; + logic alert_class_shadowed_1_we; + logic [1:0] alert_class_shadowed_1_qs; + logic [1:0] alert_class_shadowed_1_wd; + logic alert_class_shadowed_1_storage_err; + logic alert_class_shadowed_1_update_err; + logic alert_class_shadowed_2_re; + logic alert_class_shadowed_2_we; + logic [1:0] alert_class_shadowed_2_qs; + logic [1:0] alert_class_shadowed_2_wd; + logic alert_class_shadowed_2_storage_err; + logic alert_class_shadowed_2_update_err; + logic alert_class_shadowed_3_re; + logic alert_class_shadowed_3_we; + logic [1:0] alert_class_shadowed_3_qs; + logic [1:0] alert_class_shadowed_3_wd; + logic alert_class_shadowed_3_storage_err; + logic alert_class_shadowed_3_update_err; + logic alert_class_shadowed_4_re; + logic alert_class_shadowed_4_we; + logic [1:0] alert_class_shadowed_4_qs; + logic [1:0] alert_class_shadowed_4_wd; + logic alert_class_shadowed_4_storage_err; + logic alert_class_shadowed_4_update_err; + logic alert_class_shadowed_5_re; + logic alert_class_shadowed_5_we; + logic [1:0] alert_class_shadowed_5_qs; + logic [1:0] alert_class_shadowed_5_wd; + logic alert_class_shadowed_5_storage_err; + logic alert_class_shadowed_5_update_err; + logic alert_class_shadowed_6_re; + logic alert_class_shadowed_6_we; + logic [1:0] alert_class_shadowed_6_qs; + logic [1:0] alert_class_shadowed_6_wd; + logic alert_class_shadowed_6_storage_err; + logic alert_class_shadowed_6_update_err; + logic alert_class_shadowed_7_re; + logic alert_class_shadowed_7_we; + logic [1:0] alert_class_shadowed_7_qs; + logic [1:0] alert_class_shadowed_7_wd; + logic alert_class_shadowed_7_storage_err; + logic alert_class_shadowed_7_update_err; + logic alert_class_shadowed_8_re; + logic alert_class_shadowed_8_we; + logic [1:0] alert_class_shadowed_8_qs; + logic [1:0] alert_class_shadowed_8_wd; + logic alert_class_shadowed_8_storage_err; + logic alert_class_shadowed_8_update_err; + logic alert_class_shadowed_9_re; + logic alert_class_shadowed_9_we; + logic [1:0] alert_class_shadowed_9_qs; + logic [1:0] alert_class_shadowed_9_wd; + logic alert_class_shadowed_9_storage_err; + logic alert_class_shadowed_9_update_err; + logic alert_class_shadowed_10_re; + logic alert_class_shadowed_10_we; + logic [1:0] alert_class_shadowed_10_qs; + logic [1:0] alert_class_shadowed_10_wd; + logic alert_class_shadowed_10_storage_err; + logic alert_class_shadowed_10_update_err; + logic alert_class_shadowed_11_re; + logic alert_class_shadowed_11_we; + logic [1:0] alert_class_shadowed_11_qs; + logic [1:0] alert_class_shadowed_11_wd; + logic alert_class_shadowed_11_storage_err; + logic alert_class_shadowed_11_update_err; + logic alert_class_shadowed_12_re; + logic alert_class_shadowed_12_we; + logic [1:0] alert_class_shadowed_12_qs; + logic [1:0] alert_class_shadowed_12_wd; + logic alert_class_shadowed_12_storage_err; + logic alert_class_shadowed_12_update_err; + logic alert_class_shadowed_13_re; + logic alert_class_shadowed_13_we; + logic [1:0] alert_class_shadowed_13_qs; + logic [1:0] alert_class_shadowed_13_wd; + logic alert_class_shadowed_13_storage_err; + logic alert_class_shadowed_13_update_err; + logic alert_class_shadowed_14_re; + logic alert_class_shadowed_14_we; + logic [1:0] alert_class_shadowed_14_qs; + logic [1:0] alert_class_shadowed_14_wd; + logic alert_class_shadowed_14_storage_err; + logic alert_class_shadowed_14_update_err; + logic alert_class_shadowed_15_re; + logic alert_class_shadowed_15_we; + logic [1:0] alert_class_shadowed_15_qs; + logic [1:0] alert_class_shadowed_15_wd; + logic alert_class_shadowed_15_storage_err; + logic alert_class_shadowed_15_update_err; + logic alert_class_shadowed_16_re; + logic alert_class_shadowed_16_we; + logic [1:0] alert_class_shadowed_16_qs; + logic [1:0] alert_class_shadowed_16_wd; + logic alert_class_shadowed_16_storage_err; + logic alert_class_shadowed_16_update_err; + logic alert_class_shadowed_17_re; + logic alert_class_shadowed_17_we; + logic [1:0] alert_class_shadowed_17_qs; + logic [1:0] alert_class_shadowed_17_wd; + logic alert_class_shadowed_17_storage_err; + logic alert_class_shadowed_17_update_err; + logic alert_class_shadowed_18_re; + logic alert_class_shadowed_18_we; + logic [1:0] alert_class_shadowed_18_qs; + logic [1:0] alert_class_shadowed_18_wd; + logic alert_class_shadowed_18_storage_err; + logic alert_class_shadowed_18_update_err; + logic alert_class_shadowed_19_re; + logic alert_class_shadowed_19_we; + logic [1:0] alert_class_shadowed_19_qs; + logic [1:0] alert_class_shadowed_19_wd; + logic alert_class_shadowed_19_storage_err; + logic alert_class_shadowed_19_update_err; + logic alert_class_shadowed_20_re; + logic alert_class_shadowed_20_we; + logic [1:0] alert_class_shadowed_20_qs; + logic [1:0] alert_class_shadowed_20_wd; + logic alert_class_shadowed_20_storage_err; + logic alert_class_shadowed_20_update_err; + logic alert_class_shadowed_21_re; + logic alert_class_shadowed_21_we; + logic [1:0] alert_class_shadowed_21_qs; + logic [1:0] alert_class_shadowed_21_wd; + logic alert_class_shadowed_21_storage_err; + logic alert_class_shadowed_21_update_err; + logic alert_class_shadowed_22_re; + logic alert_class_shadowed_22_we; + logic [1:0] alert_class_shadowed_22_qs; + logic [1:0] alert_class_shadowed_22_wd; + logic alert_class_shadowed_22_storage_err; + logic alert_class_shadowed_22_update_err; + logic alert_class_shadowed_23_re; + logic alert_class_shadowed_23_we; + logic [1:0] alert_class_shadowed_23_qs; + logic [1:0] alert_class_shadowed_23_wd; + logic alert_class_shadowed_23_storage_err; + logic alert_class_shadowed_23_update_err; + logic alert_class_shadowed_24_re; + logic alert_class_shadowed_24_we; + logic [1:0] alert_class_shadowed_24_qs; + logic [1:0] alert_class_shadowed_24_wd; + logic alert_class_shadowed_24_storage_err; + logic alert_class_shadowed_24_update_err; + logic alert_class_shadowed_25_re; + logic alert_class_shadowed_25_we; + logic [1:0] alert_class_shadowed_25_qs; + logic [1:0] alert_class_shadowed_25_wd; + logic alert_class_shadowed_25_storage_err; + logic alert_class_shadowed_25_update_err; + logic alert_class_shadowed_26_re; + logic alert_class_shadowed_26_we; + logic [1:0] alert_class_shadowed_26_qs; + logic [1:0] alert_class_shadowed_26_wd; + logic alert_class_shadowed_26_storage_err; + logic alert_class_shadowed_26_update_err; + logic alert_class_shadowed_27_re; + logic alert_class_shadowed_27_we; + logic [1:0] alert_class_shadowed_27_qs; + logic [1:0] alert_class_shadowed_27_wd; + logic alert_class_shadowed_27_storage_err; + logic alert_class_shadowed_27_update_err; + logic alert_class_shadowed_28_re; + logic alert_class_shadowed_28_we; + logic [1:0] alert_class_shadowed_28_qs; + logic [1:0] alert_class_shadowed_28_wd; + logic alert_class_shadowed_28_storage_err; + logic alert_class_shadowed_28_update_err; + logic alert_class_shadowed_29_re; + logic alert_class_shadowed_29_we; + logic [1:0] alert_class_shadowed_29_qs; + logic [1:0] alert_class_shadowed_29_wd; + logic alert_class_shadowed_29_storage_err; + logic alert_class_shadowed_29_update_err; + logic alert_class_shadowed_30_re; + logic alert_class_shadowed_30_we; + logic [1:0] alert_class_shadowed_30_qs; + logic [1:0] alert_class_shadowed_30_wd; + logic alert_class_shadowed_30_storage_err; + logic alert_class_shadowed_30_update_err; + logic alert_class_shadowed_31_re; + logic alert_class_shadowed_31_we; + logic [1:0] alert_class_shadowed_31_qs; + logic [1:0] alert_class_shadowed_31_wd; + logic alert_class_shadowed_31_storage_err; + logic alert_class_shadowed_31_update_err; + logic alert_class_shadowed_32_re; + logic alert_class_shadowed_32_we; + logic [1:0] alert_class_shadowed_32_qs; + logic [1:0] alert_class_shadowed_32_wd; + logic alert_class_shadowed_32_storage_err; + logic alert_class_shadowed_32_update_err; + logic alert_class_shadowed_33_re; + logic alert_class_shadowed_33_we; + logic [1:0] alert_class_shadowed_33_qs; + logic [1:0] alert_class_shadowed_33_wd; + logic alert_class_shadowed_33_storage_err; + logic alert_class_shadowed_33_update_err; + logic alert_class_shadowed_34_re; + logic alert_class_shadowed_34_we; + logic [1:0] alert_class_shadowed_34_qs; + logic [1:0] alert_class_shadowed_34_wd; + logic alert_class_shadowed_34_storage_err; + logic alert_class_shadowed_34_update_err; + logic alert_class_shadowed_35_re; + logic alert_class_shadowed_35_we; + logic [1:0] alert_class_shadowed_35_qs; + logic [1:0] alert_class_shadowed_35_wd; + logic alert_class_shadowed_35_storage_err; + logic alert_class_shadowed_35_update_err; + logic alert_class_shadowed_36_re; + logic alert_class_shadowed_36_we; + logic [1:0] alert_class_shadowed_36_qs; + logic [1:0] alert_class_shadowed_36_wd; + logic alert_class_shadowed_36_storage_err; + logic alert_class_shadowed_36_update_err; + logic alert_class_shadowed_37_re; + logic alert_class_shadowed_37_we; + logic [1:0] alert_class_shadowed_37_qs; + logic [1:0] alert_class_shadowed_37_wd; + logic alert_class_shadowed_37_storage_err; + logic alert_class_shadowed_37_update_err; + logic alert_class_shadowed_38_re; + logic alert_class_shadowed_38_we; + logic [1:0] alert_class_shadowed_38_qs; + logic [1:0] alert_class_shadowed_38_wd; + logic alert_class_shadowed_38_storage_err; + logic alert_class_shadowed_38_update_err; + logic alert_class_shadowed_39_re; + logic alert_class_shadowed_39_we; + logic [1:0] alert_class_shadowed_39_qs; + logic [1:0] alert_class_shadowed_39_wd; + logic alert_class_shadowed_39_storage_err; + logic alert_class_shadowed_39_update_err; + logic alert_class_shadowed_40_re; + logic alert_class_shadowed_40_we; + logic [1:0] alert_class_shadowed_40_qs; + logic [1:0] alert_class_shadowed_40_wd; + logic alert_class_shadowed_40_storage_err; + logic alert_class_shadowed_40_update_err; + logic alert_class_shadowed_41_re; + logic alert_class_shadowed_41_we; + logic [1:0] alert_class_shadowed_41_qs; + logic [1:0] alert_class_shadowed_41_wd; + logic alert_class_shadowed_41_storage_err; + logic alert_class_shadowed_41_update_err; + logic alert_class_shadowed_42_re; + logic alert_class_shadowed_42_we; + logic [1:0] alert_class_shadowed_42_qs; + logic [1:0] alert_class_shadowed_42_wd; + logic alert_class_shadowed_42_storage_err; + logic alert_class_shadowed_42_update_err; + logic alert_class_shadowed_43_re; + logic alert_class_shadowed_43_we; + logic [1:0] alert_class_shadowed_43_qs; + logic [1:0] alert_class_shadowed_43_wd; + logic alert_class_shadowed_43_storage_err; + logic alert_class_shadowed_43_update_err; + logic alert_class_shadowed_44_re; + logic alert_class_shadowed_44_we; + logic [1:0] alert_class_shadowed_44_qs; + logic [1:0] alert_class_shadowed_44_wd; + logic alert_class_shadowed_44_storage_err; + logic alert_class_shadowed_44_update_err; + logic alert_class_shadowed_45_re; + logic alert_class_shadowed_45_we; + logic [1:0] alert_class_shadowed_45_qs; + logic [1:0] alert_class_shadowed_45_wd; + logic alert_class_shadowed_45_storage_err; + logic alert_class_shadowed_45_update_err; + logic alert_class_shadowed_46_re; + logic alert_class_shadowed_46_we; + logic [1:0] alert_class_shadowed_46_qs; + logic [1:0] alert_class_shadowed_46_wd; + logic alert_class_shadowed_46_storage_err; + logic alert_class_shadowed_46_update_err; + logic alert_class_shadowed_47_re; + logic alert_class_shadowed_47_we; + logic [1:0] alert_class_shadowed_47_qs; + logic [1:0] alert_class_shadowed_47_wd; + logic alert_class_shadowed_47_storage_err; + logic alert_class_shadowed_47_update_err; + logic alert_class_shadowed_48_re; + logic alert_class_shadowed_48_we; + logic [1:0] alert_class_shadowed_48_qs; + logic [1:0] alert_class_shadowed_48_wd; + logic alert_class_shadowed_48_storage_err; + logic alert_class_shadowed_48_update_err; + logic alert_class_shadowed_49_re; + logic alert_class_shadowed_49_we; + logic [1:0] alert_class_shadowed_49_qs; + logic [1:0] alert_class_shadowed_49_wd; + logic alert_class_shadowed_49_storage_err; + logic alert_class_shadowed_49_update_err; + logic alert_class_shadowed_50_re; + logic alert_class_shadowed_50_we; + logic [1:0] alert_class_shadowed_50_qs; + logic [1:0] alert_class_shadowed_50_wd; + logic alert_class_shadowed_50_storage_err; + logic alert_class_shadowed_50_update_err; + logic alert_class_shadowed_51_re; + logic alert_class_shadowed_51_we; + logic [1:0] alert_class_shadowed_51_qs; + logic [1:0] alert_class_shadowed_51_wd; + logic alert_class_shadowed_51_storage_err; + logic alert_class_shadowed_51_update_err; + logic alert_class_shadowed_52_re; + logic alert_class_shadowed_52_we; + logic [1:0] alert_class_shadowed_52_qs; + logic [1:0] alert_class_shadowed_52_wd; + logic alert_class_shadowed_52_storage_err; + logic alert_class_shadowed_52_update_err; + logic alert_class_shadowed_53_re; + logic alert_class_shadowed_53_we; + logic [1:0] alert_class_shadowed_53_qs; + logic [1:0] alert_class_shadowed_53_wd; + logic alert_class_shadowed_53_storage_err; + logic alert_class_shadowed_53_update_err; + logic alert_class_shadowed_54_re; + logic alert_class_shadowed_54_we; + logic [1:0] alert_class_shadowed_54_qs; + logic [1:0] alert_class_shadowed_54_wd; + logic alert_class_shadowed_54_storage_err; + logic alert_class_shadowed_54_update_err; + logic alert_class_shadowed_55_re; + logic alert_class_shadowed_55_we; + logic [1:0] alert_class_shadowed_55_qs; + logic [1:0] alert_class_shadowed_55_wd; + logic alert_class_shadowed_55_storage_err; + logic alert_class_shadowed_55_update_err; + logic alert_class_shadowed_56_re; + logic alert_class_shadowed_56_we; + logic [1:0] alert_class_shadowed_56_qs; + logic [1:0] alert_class_shadowed_56_wd; + logic alert_class_shadowed_56_storage_err; + logic alert_class_shadowed_56_update_err; + logic alert_class_shadowed_57_re; + logic alert_class_shadowed_57_we; + logic [1:0] alert_class_shadowed_57_qs; + logic [1:0] alert_class_shadowed_57_wd; + logic alert_class_shadowed_57_storage_err; + logic alert_class_shadowed_57_update_err; + logic alert_class_shadowed_58_re; + logic alert_class_shadowed_58_we; + logic [1:0] alert_class_shadowed_58_qs; + logic [1:0] alert_class_shadowed_58_wd; + logic alert_class_shadowed_58_storage_err; + logic alert_class_shadowed_58_update_err; + logic alert_class_shadowed_59_re; + logic alert_class_shadowed_59_we; + logic [1:0] alert_class_shadowed_59_qs; + logic [1:0] alert_class_shadowed_59_wd; + logic alert_class_shadowed_59_storage_err; + logic alert_class_shadowed_59_update_err; + logic alert_class_shadowed_60_re; + logic alert_class_shadowed_60_we; + logic [1:0] alert_class_shadowed_60_qs; + logic [1:0] alert_class_shadowed_60_wd; + logic alert_class_shadowed_60_storage_err; + logic alert_class_shadowed_60_update_err; + logic alert_class_shadowed_61_re; + logic alert_class_shadowed_61_we; + logic [1:0] alert_class_shadowed_61_qs; + logic [1:0] alert_class_shadowed_61_wd; + logic alert_class_shadowed_61_storage_err; + logic alert_class_shadowed_61_update_err; + logic alert_class_shadowed_62_re; + logic alert_class_shadowed_62_we; + logic [1:0] alert_class_shadowed_62_qs; + logic [1:0] alert_class_shadowed_62_wd; + logic alert_class_shadowed_62_storage_err; + logic alert_class_shadowed_62_update_err; + logic alert_class_shadowed_63_re; + logic alert_class_shadowed_63_we; + logic [1:0] alert_class_shadowed_63_qs; + logic [1:0] alert_class_shadowed_63_wd; + logic alert_class_shadowed_63_storage_err; + logic alert_class_shadowed_63_update_err; + logic alert_class_shadowed_64_re; + logic alert_class_shadowed_64_we; + logic [1:0] alert_class_shadowed_64_qs; + logic [1:0] alert_class_shadowed_64_wd; + logic alert_class_shadowed_64_storage_err; + logic alert_class_shadowed_64_update_err; + logic alert_class_shadowed_65_re; + logic alert_class_shadowed_65_we; + logic [1:0] alert_class_shadowed_65_qs; + logic [1:0] alert_class_shadowed_65_wd; + logic alert_class_shadowed_65_storage_err; + logic alert_class_shadowed_65_update_err; + logic alert_class_shadowed_66_re; + logic alert_class_shadowed_66_we; + logic [1:0] alert_class_shadowed_66_qs; + logic [1:0] alert_class_shadowed_66_wd; + logic alert_class_shadowed_66_storage_err; + logic alert_class_shadowed_66_update_err; + logic alert_class_shadowed_67_re; + logic alert_class_shadowed_67_we; + logic [1:0] alert_class_shadowed_67_qs; + logic [1:0] alert_class_shadowed_67_wd; + logic alert_class_shadowed_67_storage_err; + logic alert_class_shadowed_67_update_err; + logic alert_class_shadowed_68_re; + logic alert_class_shadowed_68_we; + logic [1:0] alert_class_shadowed_68_qs; + logic [1:0] alert_class_shadowed_68_wd; + logic alert_class_shadowed_68_storage_err; + logic alert_class_shadowed_68_update_err; + logic alert_class_shadowed_69_re; + logic alert_class_shadowed_69_we; + logic [1:0] alert_class_shadowed_69_qs; + logic [1:0] alert_class_shadowed_69_wd; + logic alert_class_shadowed_69_storage_err; + logic alert_class_shadowed_69_update_err; + logic alert_class_shadowed_70_re; + logic alert_class_shadowed_70_we; + logic [1:0] alert_class_shadowed_70_qs; + logic [1:0] alert_class_shadowed_70_wd; + logic alert_class_shadowed_70_storage_err; + logic alert_class_shadowed_70_update_err; + logic alert_class_shadowed_71_re; + logic alert_class_shadowed_71_we; + logic [1:0] alert_class_shadowed_71_qs; + logic [1:0] alert_class_shadowed_71_wd; + logic alert_class_shadowed_71_storage_err; + logic alert_class_shadowed_71_update_err; + logic alert_class_shadowed_72_re; + logic alert_class_shadowed_72_we; + logic [1:0] alert_class_shadowed_72_qs; + logic [1:0] alert_class_shadowed_72_wd; + logic alert_class_shadowed_72_storage_err; + logic alert_class_shadowed_72_update_err; + logic alert_class_shadowed_73_re; + logic alert_class_shadowed_73_we; + logic [1:0] alert_class_shadowed_73_qs; + logic [1:0] alert_class_shadowed_73_wd; + logic alert_class_shadowed_73_storage_err; + logic alert_class_shadowed_73_update_err; + logic alert_class_shadowed_74_re; + logic alert_class_shadowed_74_we; + logic [1:0] alert_class_shadowed_74_qs; + logic [1:0] alert_class_shadowed_74_wd; + logic alert_class_shadowed_74_storage_err; + logic alert_class_shadowed_74_update_err; + logic alert_class_shadowed_75_re; + logic alert_class_shadowed_75_we; + logic [1:0] alert_class_shadowed_75_qs; + logic [1:0] alert_class_shadowed_75_wd; + logic alert_class_shadowed_75_storage_err; + logic alert_class_shadowed_75_update_err; + logic alert_class_shadowed_76_re; + logic alert_class_shadowed_76_we; + logic [1:0] alert_class_shadowed_76_qs; + logic [1:0] alert_class_shadowed_76_wd; + logic alert_class_shadowed_76_storage_err; + logic alert_class_shadowed_76_update_err; + logic alert_class_shadowed_77_re; + logic alert_class_shadowed_77_we; + logic [1:0] alert_class_shadowed_77_qs; + logic [1:0] alert_class_shadowed_77_wd; + logic alert_class_shadowed_77_storage_err; + logic alert_class_shadowed_77_update_err; + logic alert_class_shadowed_78_re; + logic alert_class_shadowed_78_we; + logic [1:0] alert_class_shadowed_78_qs; + logic [1:0] alert_class_shadowed_78_wd; + logic alert_class_shadowed_78_storage_err; + logic alert_class_shadowed_78_update_err; + logic alert_class_shadowed_79_re; + logic alert_class_shadowed_79_we; + logic [1:0] alert_class_shadowed_79_qs; + logic [1:0] alert_class_shadowed_79_wd; + logic alert_class_shadowed_79_storage_err; + logic alert_class_shadowed_79_update_err; + logic alert_class_shadowed_80_re; + logic alert_class_shadowed_80_we; + logic [1:0] alert_class_shadowed_80_qs; + logic [1:0] alert_class_shadowed_80_wd; + logic alert_class_shadowed_80_storage_err; + logic alert_class_shadowed_80_update_err; + logic alert_class_shadowed_81_re; + logic alert_class_shadowed_81_we; + logic [1:0] alert_class_shadowed_81_qs; + logic [1:0] alert_class_shadowed_81_wd; + logic alert_class_shadowed_81_storage_err; + logic alert_class_shadowed_81_update_err; + logic alert_class_shadowed_82_re; + logic alert_class_shadowed_82_we; + logic [1:0] alert_class_shadowed_82_qs; + logic [1:0] alert_class_shadowed_82_wd; + logic alert_class_shadowed_82_storage_err; + logic alert_class_shadowed_82_update_err; + logic alert_class_shadowed_83_re; + logic alert_class_shadowed_83_we; + logic [1:0] alert_class_shadowed_83_qs; + logic [1:0] alert_class_shadowed_83_wd; + logic alert_class_shadowed_83_storage_err; + logic alert_class_shadowed_83_update_err; + logic alert_class_shadowed_84_re; + logic alert_class_shadowed_84_we; + logic [1:0] alert_class_shadowed_84_qs; + logic [1:0] alert_class_shadowed_84_wd; + logic alert_class_shadowed_84_storage_err; + logic alert_class_shadowed_84_update_err; + logic alert_class_shadowed_85_re; + logic alert_class_shadowed_85_we; + logic [1:0] alert_class_shadowed_85_qs; + logic [1:0] alert_class_shadowed_85_wd; + logic alert_class_shadowed_85_storage_err; + logic alert_class_shadowed_85_update_err; + logic alert_class_shadowed_86_re; + logic alert_class_shadowed_86_we; + logic [1:0] alert_class_shadowed_86_qs; + logic [1:0] alert_class_shadowed_86_wd; + logic alert_class_shadowed_86_storage_err; + logic alert_class_shadowed_86_update_err; + logic alert_class_shadowed_87_re; + logic alert_class_shadowed_87_we; + logic [1:0] alert_class_shadowed_87_qs; + logic [1:0] alert_class_shadowed_87_wd; + logic alert_class_shadowed_87_storage_err; + logic alert_class_shadowed_87_update_err; + logic alert_class_shadowed_88_re; + logic alert_class_shadowed_88_we; + logic [1:0] alert_class_shadowed_88_qs; + logic [1:0] alert_class_shadowed_88_wd; + logic alert_class_shadowed_88_storage_err; + logic alert_class_shadowed_88_update_err; + logic alert_class_shadowed_89_re; + logic alert_class_shadowed_89_we; + logic [1:0] alert_class_shadowed_89_qs; + logic [1:0] alert_class_shadowed_89_wd; + logic alert_class_shadowed_89_storage_err; + logic alert_class_shadowed_89_update_err; + logic alert_class_shadowed_90_re; + logic alert_class_shadowed_90_we; + logic [1:0] alert_class_shadowed_90_qs; + logic [1:0] alert_class_shadowed_90_wd; + logic alert_class_shadowed_90_storage_err; + logic alert_class_shadowed_90_update_err; + logic alert_class_shadowed_91_re; + logic alert_class_shadowed_91_we; + logic [1:0] alert_class_shadowed_91_qs; + logic [1:0] alert_class_shadowed_91_wd; + logic alert_class_shadowed_91_storage_err; + logic alert_class_shadowed_91_update_err; + logic alert_class_shadowed_92_re; + logic alert_class_shadowed_92_we; + logic [1:0] alert_class_shadowed_92_qs; + logic [1:0] alert_class_shadowed_92_wd; + logic alert_class_shadowed_92_storage_err; + logic alert_class_shadowed_92_update_err; + logic alert_class_shadowed_93_re; + logic alert_class_shadowed_93_we; + logic [1:0] alert_class_shadowed_93_qs; + logic [1:0] alert_class_shadowed_93_wd; + logic alert_class_shadowed_93_storage_err; + logic alert_class_shadowed_93_update_err; + logic alert_class_shadowed_94_re; + logic alert_class_shadowed_94_we; + logic [1:0] alert_class_shadowed_94_qs; + logic [1:0] alert_class_shadowed_94_wd; + logic alert_class_shadowed_94_storage_err; + logic alert_class_shadowed_94_update_err; + logic alert_class_shadowed_95_re; + logic alert_class_shadowed_95_we; + logic [1:0] alert_class_shadowed_95_qs; + logic [1:0] alert_class_shadowed_95_wd; + logic alert_class_shadowed_95_storage_err; + logic alert_class_shadowed_95_update_err; + logic alert_class_shadowed_96_re; + logic alert_class_shadowed_96_we; + logic [1:0] alert_class_shadowed_96_qs; + logic [1:0] alert_class_shadowed_96_wd; + logic alert_class_shadowed_96_storage_err; + logic alert_class_shadowed_96_update_err; + logic alert_class_shadowed_97_re; + logic alert_class_shadowed_97_we; + logic [1:0] alert_class_shadowed_97_qs; + logic [1:0] alert_class_shadowed_97_wd; + logic alert_class_shadowed_97_storage_err; + logic alert_class_shadowed_97_update_err; + logic alert_class_shadowed_98_re; + logic alert_class_shadowed_98_we; + logic [1:0] alert_class_shadowed_98_qs; + logic [1:0] alert_class_shadowed_98_wd; + logic alert_class_shadowed_98_storage_err; + logic alert_class_shadowed_98_update_err; + logic alert_cause_0_we; + logic alert_cause_0_qs; + logic alert_cause_0_wd; + logic alert_cause_1_we; + logic alert_cause_1_qs; + logic alert_cause_1_wd; + logic alert_cause_2_we; + logic alert_cause_2_qs; + logic alert_cause_2_wd; + logic alert_cause_3_we; + logic alert_cause_3_qs; + logic alert_cause_3_wd; + logic alert_cause_4_we; + logic alert_cause_4_qs; + logic alert_cause_4_wd; + logic alert_cause_5_we; + logic alert_cause_5_qs; + logic alert_cause_5_wd; + logic alert_cause_6_we; + logic alert_cause_6_qs; + logic alert_cause_6_wd; + logic alert_cause_7_we; + logic alert_cause_7_qs; + logic alert_cause_7_wd; + logic alert_cause_8_we; + logic alert_cause_8_qs; + logic alert_cause_8_wd; + logic alert_cause_9_we; + logic alert_cause_9_qs; + logic alert_cause_9_wd; + logic alert_cause_10_we; + logic alert_cause_10_qs; + logic alert_cause_10_wd; + logic alert_cause_11_we; + logic alert_cause_11_qs; + logic alert_cause_11_wd; + logic alert_cause_12_we; + logic alert_cause_12_qs; + logic alert_cause_12_wd; + logic alert_cause_13_we; + logic alert_cause_13_qs; + logic alert_cause_13_wd; + logic alert_cause_14_we; + logic alert_cause_14_qs; + logic alert_cause_14_wd; + logic alert_cause_15_we; + logic alert_cause_15_qs; + logic alert_cause_15_wd; + logic alert_cause_16_we; + logic alert_cause_16_qs; + logic alert_cause_16_wd; + logic alert_cause_17_we; + logic alert_cause_17_qs; + logic alert_cause_17_wd; + logic alert_cause_18_we; + logic alert_cause_18_qs; + logic alert_cause_18_wd; + logic alert_cause_19_we; + logic alert_cause_19_qs; + logic alert_cause_19_wd; + logic alert_cause_20_we; + logic alert_cause_20_qs; + logic alert_cause_20_wd; + logic alert_cause_21_we; + logic alert_cause_21_qs; + logic alert_cause_21_wd; + logic alert_cause_22_we; + logic alert_cause_22_qs; + logic alert_cause_22_wd; + logic alert_cause_23_we; + logic alert_cause_23_qs; + logic alert_cause_23_wd; + logic alert_cause_24_we; + logic alert_cause_24_qs; + logic alert_cause_24_wd; + logic alert_cause_25_we; + logic alert_cause_25_qs; + logic alert_cause_25_wd; + logic alert_cause_26_we; + logic alert_cause_26_qs; + logic alert_cause_26_wd; + logic alert_cause_27_we; + logic alert_cause_27_qs; + logic alert_cause_27_wd; + logic alert_cause_28_we; + logic alert_cause_28_qs; + logic alert_cause_28_wd; + logic alert_cause_29_we; + logic alert_cause_29_qs; + logic alert_cause_29_wd; + logic alert_cause_30_we; + logic alert_cause_30_qs; + logic alert_cause_30_wd; + logic alert_cause_31_we; + logic alert_cause_31_qs; + logic alert_cause_31_wd; + logic alert_cause_32_we; + logic alert_cause_32_qs; + logic alert_cause_32_wd; + logic alert_cause_33_we; + logic alert_cause_33_qs; + logic alert_cause_33_wd; + logic alert_cause_34_we; + logic alert_cause_34_qs; + logic alert_cause_34_wd; + logic alert_cause_35_we; + logic alert_cause_35_qs; + logic alert_cause_35_wd; + logic alert_cause_36_we; + logic alert_cause_36_qs; + logic alert_cause_36_wd; + logic alert_cause_37_we; + logic alert_cause_37_qs; + logic alert_cause_37_wd; + logic alert_cause_38_we; + logic alert_cause_38_qs; + logic alert_cause_38_wd; + logic alert_cause_39_we; + logic alert_cause_39_qs; + logic alert_cause_39_wd; + logic alert_cause_40_we; + logic alert_cause_40_qs; + logic alert_cause_40_wd; + logic alert_cause_41_we; + logic alert_cause_41_qs; + logic alert_cause_41_wd; + logic alert_cause_42_we; + logic alert_cause_42_qs; + logic alert_cause_42_wd; + logic alert_cause_43_we; + logic alert_cause_43_qs; + logic alert_cause_43_wd; + logic alert_cause_44_we; + logic alert_cause_44_qs; + logic alert_cause_44_wd; + logic alert_cause_45_we; + logic alert_cause_45_qs; + logic alert_cause_45_wd; + logic alert_cause_46_we; + logic alert_cause_46_qs; + logic alert_cause_46_wd; + logic alert_cause_47_we; + logic alert_cause_47_qs; + logic alert_cause_47_wd; + logic alert_cause_48_we; + logic alert_cause_48_qs; + logic alert_cause_48_wd; + logic alert_cause_49_we; + logic alert_cause_49_qs; + logic alert_cause_49_wd; + logic alert_cause_50_we; + logic alert_cause_50_qs; + logic alert_cause_50_wd; + logic alert_cause_51_we; + logic alert_cause_51_qs; + logic alert_cause_51_wd; + logic alert_cause_52_we; + logic alert_cause_52_qs; + logic alert_cause_52_wd; + logic alert_cause_53_we; + logic alert_cause_53_qs; + logic alert_cause_53_wd; + logic alert_cause_54_we; + logic alert_cause_54_qs; + logic alert_cause_54_wd; + logic alert_cause_55_we; + logic alert_cause_55_qs; + logic alert_cause_55_wd; + logic alert_cause_56_we; + logic alert_cause_56_qs; + logic alert_cause_56_wd; + logic alert_cause_57_we; + logic alert_cause_57_qs; + logic alert_cause_57_wd; + logic alert_cause_58_we; + logic alert_cause_58_qs; + logic alert_cause_58_wd; + logic alert_cause_59_we; + logic alert_cause_59_qs; + logic alert_cause_59_wd; + logic alert_cause_60_we; + logic alert_cause_60_qs; + logic alert_cause_60_wd; + logic alert_cause_61_we; + logic alert_cause_61_qs; + logic alert_cause_61_wd; + logic alert_cause_62_we; + logic alert_cause_62_qs; + logic alert_cause_62_wd; + logic alert_cause_63_we; + logic alert_cause_63_qs; + logic alert_cause_63_wd; + logic alert_cause_64_we; + logic alert_cause_64_qs; + logic alert_cause_64_wd; + logic alert_cause_65_we; + logic alert_cause_65_qs; + logic alert_cause_65_wd; + logic alert_cause_66_we; + logic alert_cause_66_qs; + logic alert_cause_66_wd; + logic alert_cause_67_we; + logic alert_cause_67_qs; + logic alert_cause_67_wd; + logic alert_cause_68_we; + logic alert_cause_68_qs; + logic alert_cause_68_wd; + logic alert_cause_69_we; + logic alert_cause_69_qs; + logic alert_cause_69_wd; + logic alert_cause_70_we; + logic alert_cause_70_qs; + logic alert_cause_70_wd; + logic alert_cause_71_we; + logic alert_cause_71_qs; + logic alert_cause_71_wd; + logic alert_cause_72_we; + logic alert_cause_72_qs; + logic alert_cause_72_wd; + logic alert_cause_73_we; + logic alert_cause_73_qs; + logic alert_cause_73_wd; + logic alert_cause_74_we; + logic alert_cause_74_qs; + logic alert_cause_74_wd; + logic alert_cause_75_we; + logic alert_cause_75_qs; + logic alert_cause_75_wd; + logic alert_cause_76_we; + logic alert_cause_76_qs; + logic alert_cause_76_wd; + logic alert_cause_77_we; + logic alert_cause_77_qs; + logic alert_cause_77_wd; + logic alert_cause_78_we; + logic alert_cause_78_qs; + logic alert_cause_78_wd; + logic alert_cause_79_we; + logic alert_cause_79_qs; + logic alert_cause_79_wd; + logic alert_cause_80_we; + logic alert_cause_80_qs; + logic alert_cause_80_wd; + logic alert_cause_81_we; + logic alert_cause_81_qs; + logic alert_cause_81_wd; + logic alert_cause_82_we; + logic alert_cause_82_qs; + logic alert_cause_82_wd; + logic alert_cause_83_we; + logic alert_cause_83_qs; + logic alert_cause_83_wd; + logic alert_cause_84_we; + logic alert_cause_84_qs; + logic alert_cause_84_wd; + logic alert_cause_85_we; + logic alert_cause_85_qs; + logic alert_cause_85_wd; + logic alert_cause_86_we; + logic alert_cause_86_qs; + logic alert_cause_86_wd; + logic alert_cause_87_we; + logic alert_cause_87_qs; + logic alert_cause_87_wd; + logic alert_cause_88_we; + logic alert_cause_88_qs; + logic alert_cause_88_wd; + logic alert_cause_89_we; + logic alert_cause_89_qs; + logic alert_cause_89_wd; + logic alert_cause_90_we; + logic alert_cause_90_qs; + logic alert_cause_90_wd; + logic alert_cause_91_we; + logic alert_cause_91_qs; + logic alert_cause_91_wd; + logic alert_cause_92_we; + logic alert_cause_92_qs; + logic alert_cause_92_wd; + logic alert_cause_93_we; + logic alert_cause_93_qs; + logic alert_cause_93_wd; + logic alert_cause_94_we; + logic alert_cause_94_qs; + logic alert_cause_94_wd; + logic alert_cause_95_we; + logic alert_cause_95_qs; + logic alert_cause_95_wd; + logic alert_cause_96_we; + logic alert_cause_96_qs; + logic alert_cause_96_wd; + logic alert_cause_97_we; + logic alert_cause_97_qs; + logic alert_cause_97_wd; + logic alert_cause_98_we; + logic alert_cause_98_qs; + logic alert_cause_98_wd; + logic loc_alert_regwen_0_we; + logic loc_alert_regwen_0_qs; + logic loc_alert_regwen_0_wd; + logic loc_alert_regwen_1_we; + logic loc_alert_regwen_1_qs; + logic loc_alert_regwen_1_wd; + logic loc_alert_regwen_2_we; + logic loc_alert_regwen_2_qs; + logic loc_alert_regwen_2_wd; + logic loc_alert_regwen_3_we; + logic loc_alert_regwen_3_qs; + logic loc_alert_regwen_3_wd; + logic loc_alert_regwen_4_we; + logic loc_alert_regwen_4_qs; + logic loc_alert_regwen_4_wd; + logic loc_alert_regwen_5_we; + logic loc_alert_regwen_5_qs; + logic loc_alert_regwen_5_wd; + logic loc_alert_regwen_6_we; + logic loc_alert_regwen_6_qs; + logic loc_alert_regwen_6_wd; + logic loc_alert_en_shadowed_0_re; + logic loc_alert_en_shadowed_0_we; + logic loc_alert_en_shadowed_0_qs; + logic loc_alert_en_shadowed_0_wd; + logic loc_alert_en_shadowed_0_storage_err; + logic loc_alert_en_shadowed_0_update_err; + logic loc_alert_en_shadowed_1_re; + logic loc_alert_en_shadowed_1_we; + logic loc_alert_en_shadowed_1_qs; + logic loc_alert_en_shadowed_1_wd; + logic loc_alert_en_shadowed_1_storage_err; + logic loc_alert_en_shadowed_1_update_err; + logic loc_alert_en_shadowed_2_re; + logic loc_alert_en_shadowed_2_we; + logic loc_alert_en_shadowed_2_qs; + logic loc_alert_en_shadowed_2_wd; + logic loc_alert_en_shadowed_2_storage_err; + logic loc_alert_en_shadowed_2_update_err; + logic loc_alert_en_shadowed_3_re; + logic loc_alert_en_shadowed_3_we; + logic loc_alert_en_shadowed_3_qs; + logic loc_alert_en_shadowed_3_wd; + logic loc_alert_en_shadowed_3_storage_err; + logic loc_alert_en_shadowed_3_update_err; + logic loc_alert_en_shadowed_4_re; + logic loc_alert_en_shadowed_4_we; + logic loc_alert_en_shadowed_4_qs; + logic loc_alert_en_shadowed_4_wd; + logic loc_alert_en_shadowed_4_storage_err; + logic loc_alert_en_shadowed_4_update_err; + logic loc_alert_en_shadowed_5_re; + logic loc_alert_en_shadowed_5_we; + logic loc_alert_en_shadowed_5_qs; + logic loc_alert_en_shadowed_5_wd; + logic loc_alert_en_shadowed_5_storage_err; + logic loc_alert_en_shadowed_5_update_err; + logic loc_alert_en_shadowed_6_re; + logic loc_alert_en_shadowed_6_we; + logic loc_alert_en_shadowed_6_qs; + logic loc_alert_en_shadowed_6_wd; + logic loc_alert_en_shadowed_6_storage_err; + logic loc_alert_en_shadowed_6_update_err; + logic loc_alert_class_shadowed_0_re; + logic loc_alert_class_shadowed_0_we; + logic [1:0] loc_alert_class_shadowed_0_qs; + logic [1:0] loc_alert_class_shadowed_0_wd; + logic loc_alert_class_shadowed_0_storage_err; + logic loc_alert_class_shadowed_0_update_err; + logic loc_alert_class_shadowed_1_re; + logic loc_alert_class_shadowed_1_we; + logic [1:0] loc_alert_class_shadowed_1_qs; + logic [1:0] loc_alert_class_shadowed_1_wd; + logic loc_alert_class_shadowed_1_storage_err; + logic loc_alert_class_shadowed_1_update_err; + logic loc_alert_class_shadowed_2_re; + logic loc_alert_class_shadowed_2_we; + logic [1:0] loc_alert_class_shadowed_2_qs; + logic [1:0] loc_alert_class_shadowed_2_wd; + logic loc_alert_class_shadowed_2_storage_err; + logic loc_alert_class_shadowed_2_update_err; + logic loc_alert_class_shadowed_3_re; + logic loc_alert_class_shadowed_3_we; + logic [1:0] loc_alert_class_shadowed_3_qs; + logic [1:0] loc_alert_class_shadowed_3_wd; + logic loc_alert_class_shadowed_3_storage_err; + logic loc_alert_class_shadowed_3_update_err; + logic loc_alert_class_shadowed_4_re; + logic loc_alert_class_shadowed_4_we; + logic [1:0] loc_alert_class_shadowed_4_qs; + logic [1:0] loc_alert_class_shadowed_4_wd; + logic loc_alert_class_shadowed_4_storage_err; + logic loc_alert_class_shadowed_4_update_err; + logic loc_alert_class_shadowed_5_re; + logic loc_alert_class_shadowed_5_we; + logic [1:0] loc_alert_class_shadowed_5_qs; + logic [1:0] loc_alert_class_shadowed_5_wd; + logic loc_alert_class_shadowed_5_storage_err; + logic loc_alert_class_shadowed_5_update_err; + logic loc_alert_class_shadowed_6_re; + logic loc_alert_class_shadowed_6_we; + logic [1:0] loc_alert_class_shadowed_6_qs; + logic [1:0] loc_alert_class_shadowed_6_wd; + logic loc_alert_class_shadowed_6_storage_err; + logic loc_alert_class_shadowed_6_update_err; + logic loc_alert_cause_0_we; + logic loc_alert_cause_0_qs; + logic loc_alert_cause_0_wd; + logic loc_alert_cause_1_we; + logic loc_alert_cause_1_qs; + logic loc_alert_cause_1_wd; + logic loc_alert_cause_2_we; + logic loc_alert_cause_2_qs; + logic loc_alert_cause_2_wd; + logic loc_alert_cause_3_we; + logic loc_alert_cause_3_qs; + logic loc_alert_cause_3_wd; + logic loc_alert_cause_4_we; + logic loc_alert_cause_4_qs; + logic loc_alert_cause_4_wd; + logic loc_alert_cause_5_we; + logic loc_alert_cause_5_qs; + logic loc_alert_cause_5_wd; + logic loc_alert_cause_6_we; + logic loc_alert_cause_6_qs; + logic loc_alert_cause_6_wd; + logic classa_regwen_we; + logic classa_regwen_qs; + logic classa_regwen_wd; + logic classa_ctrl_shadowed_re; + logic classa_ctrl_shadowed_we; + logic classa_ctrl_shadowed_en_qs; + logic classa_ctrl_shadowed_en_wd; + logic classa_ctrl_shadowed_en_storage_err; + logic classa_ctrl_shadowed_en_update_err; + logic classa_ctrl_shadowed_lock_qs; + logic classa_ctrl_shadowed_lock_wd; + logic classa_ctrl_shadowed_lock_storage_err; + logic classa_ctrl_shadowed_lock_update_err; + logic classa_ctrl_shadowed_en_e0_qs; + logic classa_ctrl_shadowed_en_e0_wd; + logic classa_ctrl_shadowed_en_e0_storage_err; + logic classa_ctrl_shadowed_en_e0_update_err; + logic classa_ctrl_shadowed_en_e1_qs; + logic classa_ctrl_shadowed_en_e1_wd; + logic classa_ctrl_shadowed_en_e1_storage_err; + logic classa_ctrl_shadowed_en_e1_update_err; + logic classa_ctrl_shadowed_en_e2_qs; + logic classa_ctrl_shadowed_en_e2_wd; + logic classa_ctrl_shadowed_en_e2_storage_err; + logic classa_ctrl_shadowed_en_e2_update_err; + logic classa_ctrl_shadowed_en_e3_qs; + logic classa_ctrl_shadowed_en_e3_wd; + logic classa_ctrl_shadowed_en_e3_storage_err; + logic classa_ctrl_shadowed_en_e3_update_err; + logic [1:0] classa_ctrl_shadowed_map_e0_qs; + logic [1:0] classa_ctrl_shadowed_map_e0_wd; + logic classa_ctrl_shadowed_map_e0_storage_err; + logic classa_ctrl_shadowed_map_e0_update_err; + logic [1:0] classa_ctrl_shadowed_map_e1_qs; + logic [1:0] classa_ctrl_shadowed_map_e1_wd; + logic classa_ctrl_shadowed_map_e1_storage_err; + logic classa_ctrl_shadowed_map_e1_update_err; + logic [1:0] classa_ctrl_shadowed_map_e2_qs; + logic [1:0] classa_ctrl_shadowed_map_e2_wd; + logic classa_ctrl_shadowed_map_e2_storage_err; + logic classa_ctrl_shadowed_map_e2_update_err; + logic [1:0] classa_ctrl_shadowed_map_e3_qs; + logic [1:0] classa_ctrl_shadowed_map_e3_wd; + logic classa_ctrl_shadowed_map_e3_storage_err; + logic classa_ctrl_shadowed_map_e3_update_err; + logic classa_clr_regwen_we; + logic classa_clr_regwen_qs; + logic classa_clr_regwen_wd; + logic classa_clr_shadowed_re; + logic classa_clr_shadowed_we; + logic classa_clr_shadowed_qs; + logic classa_clr_shadowed_wd; + logic classa_clr_shadowed_storage_err; + logic classa_clr_shadowed_update_err; + logic classa_accum_cnt_re; + logic [15:0] classa_accum_cnt_qs; + logic classa_accum_thresh_shadowed_re; + logic classa_accum_thresh_shadowed_we; + logic [15:0] classa_accum_thresh_shadowed_qs; + logic [15:0] classa_accum_thresh_shadowed_wd; + logic classa_accum_thresh_shadowed_storage_err; + logic classa_accum_thresh_shadowed_update_err; + logic classa_timeout_cyc_shadowed_re; + logic classa_timeout_cyc_shadowed_we; + logic [31:0] classa_timeout_cyc_shadowed_qs; + logic [31:0] classa_timeout_cyc_shadowed_wd; + logic classa_timeout_cyc_shadowed_storage_err; + logic classa_timeout_cyc_shadowed_update_err; + logic classa_crashdump_trigger_shadowed_re; + logic classa_crashdump_trigger_shadowed_we; + logic [1:0] classa_crashdump_trigger_shadowed_qs; + logic [1:0] classa_crashdump_trigger_shadowed_wd; + logic classa_crashdump_trigger_shadowed_storage_err; + logic classa_crashdump_trigger_shadowed_update_err; + logic classa_phase0_cyc_shadowed_re; + logic classa_phase0_cyc_shadowed_we; + logic [31:0] classa_phase0_cyc_shadowed_qs; + logic [31:0] classa_phase0_cyc_shadowed_wd; + logic classa_phase0_cyc_shadowed_storage_err; + logic classa_phase0_cyc_shadowed_update_err; + logic classa_phase1_cyc_shadowed_re; + logic classa_phase1_cyc_shadowed_we; + logic [31:0] classa_phase1_cyc_shadowed_qs; + logic [31:0] classa_phase1_cyc_shadowed_wd; + logic classa_phase1_cyc_shadowed_storage_err; + logic classa_phase1_cyc_shadowed_update_err; + logic classa_phase2_cyc_shadowed_re; + logic classa_phase2_cyc_shadowed_we; + logic [31:0] classa_phase2_cyc_shadowed_qs; + logic [31:0] classa_phase2_cyc_shadowed_wd; + logic classa_phase2_cyc_shadowed_storage_err; + logic classa_phase2_cyc_shadowed_update_err; + logic classa_phase3_cyc_shadowed_re; + logic classa_phase3_cyc_shadowed_we; + logic [31:0] classa_phase3_cyc_shadowed_qs; + logic [31:0] classa_phase3_cyc_shadowed_wd; + logic classa_phase3_cyc_shadowed_storage_err; + logic classa_phase3_cyc_shadowed_update_err; + logic classa_esc_cnt_re; + logic [31:0] classa_esc_cnt_qs; + logic classa_state_re; + logic [2:0] classa_state_qs; + logic classb_regwen_we; + logic classb_regwen_qs; + logic classb_regwen_wd; + logic classb_ctrl_shadowed_re; + logic classb_ctrl_shadowed_we; + logic classb_ctrl_shadowed_en_qs; + logic classb_ctrl_shadowed_en_wd; + logic classb_ctrl_shadowed_en_storage_err; + logic classb_ctrl_shadowed_en_update_err; + logic classb_ctrl_shadowed_lock_qs; + logic classb_ctrl_shadowed_lock_wd; + logic classb_ctrl_shadowed_lock_storage_err; + logic classb_ctrl_shadowed_lock_update_err; + logic classb_ctrl_shadowed_en_e0_qs; + logic classb_ctrl_shadowed_en_e0_wd; + logic classb_ctrl_shadowed_en_e0_storage_err; + logic classb_ctrl_shadowed_en_e0_update_err; + logic classb_ctrl_shadowed_en_e1_qs; + logic classb_ctrl_shadowed_en_e1_wd; + logic classb_ctrl_shadowed_en_e1_storage_err; + logic classb_ctrl_shadowed_en_e1_update_err; + logic classb_ctrl_shadowed_en_e2_qs; + logic classb_ctrl_shadowed_en_e2_wd; + logic classb_ctrl_shadowed_en_e2_storage_err; + logic classb_ctrl_shadowed_en_e2_update_err; + logic classb_ctrl_shadowed_en_e3_qs; + logic classb_ctrl_shadowed_en_e3_wd; + logic classb_ctrl_shadowed_en_e3_storage_err; + logic classb_ctrl_shadowed_en_e3_update_err; + logic [1:0] classb_ctrl_shadowed_map_e0_qs; + logic [1:0] classb_ctrl_shadowed_map_e0_wd; + logic classb_ctrl_shadowed_map_e0_storage_err; + logic classb_ctrl_shadowed_map_e0_update_err; + logic [1:0] classb_ctrl_shadowed_map_e1_qs; + logic [1:0] classb_ctrl_shadowed_map_e1_wd; + logic classb_ctrl_shadowed_map_e1_storage_err; + logic classb_ctrl_shadowed_map_e1_update_err; + logic [1:0] classb_ctrl_shadowed_map_e2_qs; + logic [1:0] classb_ctrl_shadowed_map_e2_wd; + logic classb_ctrl_shadowed_map_e2_storage_err; + logic classb_ctrl_shadowed_map_e2_update_err; + logic [1:0] classb_ctrl_shadowed_map_e3_qs; + logic [1:0] classb_ctrl_shadowed_map_e3_wd; + logic classb_ctrl_shadowed_map_e3_storage_err; + logic classb_ctrl_shadowed_map_e3_update_err; + logic classb_clr_regwen_we; + logic classb_clr_regwen_qs; + logic classb_clr_regwen_wd; + logic classb_clr_shadowed_re; + logic classb_clr_shadowed_we; + logic classb_clr_shadowed_qs; + logic classb_clr_shadowed_wd; + logic classb_clr_shadowed_storage_err; + logic classb_clr_shadowed_update_err; + logic classb_accum_cnt_re; + logic [15:0] classb_accum_cnt_qs; + logic classb_accum_thresh_shadowed_re; + logic classb_accum_thresh_shadowed_we; + logic [15:0] classb_accum_thresh_shadowed_qs; + logic [15:0] classb_accum_thresh_shadowed_wd; + logic classb_accum_thresh_shadowed_storage_err; + logic classb_accum_thresh_shadowed_update_err; + logic classb_timeout_cyc_shadowed_re; + logic classb_timeout_cyc_shadowed_we; + logic [31:0] classb_timeout_cyc_shadowed_qs; + logic [31:0] classb_timeout_cyc_shadowed_wd; + logic classb_timeout_cyc_shadowed_storage_err; + logic classb_timeout_cyc_shadowed_update_err; + logic classb_crashdump_trigger_shadowed_re; + logic classb_crashdump_trigger_shadowed_we; + logic [1:0] classb_crashdump_trigger_shadowed_qs; + logic [1:0] classb_crashdump_trigger_shadowed_wd; + logic classb_crashdump_trigger_shadowed_storage_err; + logic classb_crashdump_trigger_shadowed_update_err; + logic classb_phase0_cyc_shadowed_re; + logic classb_phase0_cyc_shadowed_we; + logic [31:0] classb_phase0_cyc_shadowed_qs; + logic [31:0] classb_phase0_cyc_shadowed_wd; + logic classb_phase0_cyc_shadowed_storage_err; + logic classb_phase0_cyc_shadowed_update_err; + logic classb_phase1_cyc_shadowed_re; + logic classb_phase1_cyc_shadowed_we; + logic [31:0] classb_phase1_cyc_shadowed_qs; + logic [31:0] classb_phase1_cyc_shadowed_wd; + logic classb_phase1_cyc_shadowed_storage_err; + logic classb_phase1_cyc_shadowed_update_err; + logic classb_phase2_cyc_shadowed_re; + logic classb_phase2_cyc_shadowed_we; + logic [31:0] classb_phase2_cyc_shadowed_qs; + logic [31:0] classb_phase2_cyc_shadowed_wd; + logic classb_phase2_cyc_shadowed_storage_err; + logic classb_phase2_cyc_shadowed_update_err; + logic classb_phase3_cyc_shadowed_re; + logic classb_phase3_cyc_shadowed_we; + logic [31:0] classb_phase3_cyc_shadowed_qs; + logic [31:0] classb_phase3_cyc_shadowed_wd; + logic classb_phase3_cyc_shadowed_storage_err; + logic classb_phase3_cyc_shadowed_update_err; + logic classb_esc_cnt_re; + logic [31:0] classb_esc_cnt_qs; + logic classb_state_re; + logic [2:0] classb_state_qs; + logic classc_regwen_we; + logic classc_regwen_qs; + logic classc_regwen_wd; + logic classc_ctrl_shadowed_re; + logic classc_ctrl_shadowed_we; + logic classc_ctrl_shadowed_en_qs; + logic classc_ctrl_shadowed_en_wd; + logic classc_ctrl_shadowed_en_storage_err; + logic classc_ctrl_shadowed_en_update_err; + logic classc_ctrl_shadowed_lock_qs; + logic classc_ctrl_shadowed_lock_wd; + logic classc_ctrl_shadowed_lock_storage_err; + logic classc_ctrl_shadowed_lock_update_err; + logic classc_ctrl_shadowed_en_e0_qs; + logic classc_ctrl_shadowed_en_e0_wd; + logic classc_ctrl_shadowed_en_e0_storage_err; + logic classc_ctrl_shadowed_en_e0_update_err; + logic classc_ctrl_shadowed_en_e1_qs; + logic classc_ctrl_shadowed_en_e1_wd; + logic classc_ctrl_shadowed_en_e1_storage_err; + logic classc_ctrl_shadowed_en_e1_update_err; + logic classc_ctrl_shadowed_en_e2_qs; + logic classc_ctrl_shadowed_en_e2_wd; + logic classc_ctrl_shadowed_en_e2_storage_err; + logic classc_ctrl_shadowed_en_e2_update_err; + logic classc_ctrl_shadowed_en_e3_qs; + logic classc_ctrl_shadowed_en_e3_wd; + logic classc_ctrl_shadowed_en_e3_storage_err; + logic classc_ctrl_shadowed_en_e3_update_err; + logic [1:0] classc_ctrl_shadowed_map_e0_qs; + logic [1:0] classc_ctrl_shadowed_map_e0_wd; + logic classc_ctrl_shadowed_map_e0_storage_err; + logic classc_ctrl_shadowed_map_e0_update_err; + logic [1:0] classc_ctrl_shadowed_map_e1_qs; + logic [1:0] classc_ctrl_shadowed_map_e1_wd; + logic classc_ctrl_shadowed_map_e1_storage_err; + logic classc_ctrl_shadowed_map_e1_update_err; + logic [1:0] classc_ctrl_shadowed_map_e2_qs; + logic [1:0] classc_ctrl_shadowed_map_e2_wd; + logic classc_ctrl_shadowed_map_e2_storage_err; + logic classc_ctrl_shadowed_map_e2_update_err; + logic [1:0] classc_ctrl_shadowed_map_e3_qs; + logic [1:0] classc_ctrl_shadowed_map_e3_wd; + logic classc_ctrl_shadowed_map_e3_storage_err; + logic classc_ctrl_shadowed_map_e3_update_err; + logic classc_clr_regwen_we; + logic classc_clr_regwen_qs; + logic classc_clr_regwen_wd; + logic classc_clr_shadowed_re; + logic classc_clr_shadowed_we; + logic classc_clr_shadowed_qs; + logic classc_clr_shadowed_wd; + logic classc_clr_shadowed_storage_err; + logic classc_clr_shadowed_update_err; + logic classc_accum_cnt_re; + logic [15:0] classc_accum_cnt_qs; + logic classc_accum_thresh_shadowed_re; + logic classc_accum_thresh_shadowed_we; + logic [15:0] classc_accum_thresh_shadowed_qs; + logic [15:0] classc_accum_thresh_shadowed_wd; + logic classc_accum_thresh_shadowed_storage_err; + logic classc_accum_thresh_shadowed_update_err; + logic classc_timeout_cyc_shadowed_re; + logic classc_timeout_cyc_shadowed_we; + logic [31:0] classc_timeout_cyc_shadowed_qs; + logic [31:0] classc_timeout_cyc_shadowed_wd; + logic classc_timeout_cyc_shadowed_storage_err; + logic classc_timeout_cyc_shadowed_update_err; + logic classc_crashdump_trigger_shadowed_re; + logic classc_crashdump_trigger_shadowed_we; + logic [1:0] classc_crashdump_trigger_shadowed_qs; + logic [1:0] classc_crashdump_trigger_shadowed_wd; + logic classc_crashdump_trigger_shadowed_storage_err; + logic classc_crashdump_trigger_shadowed_update_err; + logic classc_phase0_cyc_shadowed_re; + logic classc_phase0_cyc_shadowed_we; + logic [31:0] classc_phase0_cyc_shadowed_qs; + logic [31:0] classc_phase0_cyc_shadowed_wd; + logic classc_phase0_cyc_shadowed_storage_err; + logic classc_phase0_cyc_shadowed_update_err; + logic classc_phase1_cyc_shadowed_re; + logic classc_phase1_cyc_shadowed_we; + logic [31:0] classc_phase1_cyc_shadowed_qs; + logic [31:0] classc_phase1_cyc_shadowed_wd; + logic classc_phase1_cyc_shadowed_storage_err; + logic classc_phase1_cyc_shadowed_update_err; + logic classc_phase2_cyc_shadowed_re; + logic classc_phase2_cyc_shadowed_we; + logic [31:0] classc_phase2_cyc_shadowed_qs; + logic [31:0] classc_phase2_cyc_shadowed_wd; + logic classc_phase2_cyc_shadowed_storage_err; + logic classc_phase2_cyc_shadowed_update_err; + logic classc_phase3_cyc_shadowed_re; + logic classc_phase3_cyc_shadowed_we; + logic [31:0] classc_phase3_cyc_shadowed_qs; + logic [31:0] classc_phase3_cyc_shadowed_wd; + logic classc_phase3_cyc_shadowed_storage_err; + logic classc_phase3_cyc_shadowed_update_err; + logic classc_esc_cnt_re; + logic [31:0] classc_esc_cnt_qs; + logic classc_state_re; + logic [2:0] classc_state_qs; + logic classd_regwen_we; + logic classd_regwen_qs; + logic classd_regwen_wd; + logic classd_ctrl_shadowed_re; + logic classd_ctrl_shadowed_we; + logic classd_ctrl_shadowed_en_qs; + logic classd_ctrl_shadowed_en_wd; + logic classd_ctrl_shadowed_en_storage_err; + logic classd_ctrl_shadowed_en_update_err; + logic classd_ctrl_shadowed_lock_qs; + logic classd_ctrl_shadowed_lock_wd; + logic classd_ctrl_shadowed_lock_storage_err; + logic classd_ctrl_shadowed_lock_update_err; + logic classd_ctrl_shadowed_en_e0_qs; + logic classd_ctrl_shadowed_en_e0_wd; + logic classd_ctrl_shadowed_en_e0_storage_err; + logic classd_ctrl_shadowed_en_e0_update_err; + logic classd_ctrl_shadowed_en_e1_qs; + logic classd_ctrl_shadowed_en_e1_wd; + logic classd_ctrl_shadowed_en_e1_storage_err; + logic classd_ctrl_shadowed_en_e1_update_err; + logic classd_ctrl_shadowed_en_e2_qs; + logic classd_ctrl_shadowed_en_e2_wd; + logic classd_ctrl_shadowed_en_e2_storage_err; + logic classd_ctrl_shadowed_en_e2_update_err; + logic classd_ctrl_shadowed_en_e3_qs; + logic classd_ctrl_shadowed_en_e3_wd; + logic classd_ctrl_shadowed_en_e3_storage_err; + logic classd_ctrl_shadowed_en_e3_update_err; + logic [1:0] classd_ctrl_shadowed_map_e0_qs; + logic [1:0] classd_ctrl_shadowed_map_e0_wd; + logic classd_ctrl_shadowed_map_e0_storage_err; + logic classd_ctrl_shadowed_map_e0_update_err; + logic [1:0] classd_ctrl_shadowed_map_e1_qs; + logic [1:0] classd_ctrl_shadowed_map_e1_wd; + logic classd_ctrl_shadowed_map_e1_storage_err; + logic classd_ctrl_shadowed_map_e1_update_err; + logic [1:0] classd_ctrl_shadowed_map_e2_qs; + logic [1:0] classd_ctrl_shadowed_map_e2_wd; + logic classd_ctrl_shadowed_map_e2_storage_err; + logic classd_ctrl_shadowed_map_e2_update_err; + logic [1:0] classd_ctrl_shadowed_map_e3_qs; + logic [1:0] classd_ctrl_shadowed_map_e3_wd; + logic classd_ctrl_shadowed_map_e3_storage_err; + logic classd_ctrl_shadowed_map_e3_update_err; + logic classd_clr_regwen_we; + logic classd_clr_regwen_qs; + logic classd_clr_regwen_wd; + logic classd_clr_shadowed_re; + logic classd_clr_shadowed_we; + logic classd_clr_shadowed_qs; + logic classd_clr_shadowed_wd; + logic classd_clr_shadowed_storage_err; + logic classd_clr_shadowed_update_err; + logic classd_accum_cnt_re; + logic [15:0] classd_accum_cnt_qs; + logic classd_accum_thresh_shadowed_re; + logic classd_accum_thresh_shadowed_we; + logic [15:0] classd_accum_thresh_shadowed_qs; + logic [15:0] classd_accum_thresh_shadowed_wd; + logic classd_accum_thresh_shadowed_storage_err; + logic classd_accum_thresh_shadowed_update_err; + logic classd_timeout_cyc_shadowed_re; + logic classd_timeout_cyc_shadowed_we; + logic [31:0] classd_timeout_cyc_shadowed_qs; + logic [31:0] classd_timeout_cyc_shadowed_wd; + logic classd_timeout_cyc_shadowed_storage_err; + logic classd_timeout_cyc_shadowed_update_err; + logic classd_crashdump_trigger_shadowed_re; + logic classd_crashdump_trigger_shadowed_we; + logic [1:0] classd_crashdump_trigger_shadowed_qs; + logic [1:0] classd_crashdump_trigger_shadowed_wd; + logic classd_crashdump_trigger_shadowed_storage_err; + logic classd_crashdump_trigger_shadowed_update_err; + logic classd_phase0_cyc_shadowed_re; + logic classd_phase0_cyc_shadowed_we; + logic [31:0] classd_phase0_cyc_shadowed_qs; + logic [31:0] classd_phase0_cyc_shadowed_wd; + logic classd_phase0_cyc_shadowed_storage_err; + logic classd_phase0_cyc_shadowed_update_err; + logic classd_phase1_cyc_shadowed_re; + logic classd_phase1_cyc_shadowed_we; + logic [31:0] classd_phase1_cyc_shadowed_qs; + logic [31:0] classd_phase1_cyc_shadowed_wd; + logic classd_phase1_cyc_shadowed_storage_err; + logic classd_phase1_cyc_shadowed_update_err; + logic classd_phase2_cyc_shadowed_re; + logic classd_phase2_cyc_shadowed_we; + logic [31:0] classd_phase2_cyc_shadowed_qs; + logic [31:0] classd_phase2_cyc_shadowed_wd; + logic classd_phase2_cyc_shadowed_storage_err; + logic classd_phase2_cyc_shadowed_update_err; + logic classd_phase3_cyc_shadowed_re; + logic classd_phase3_cyc_shadowed_we; + logic [31:0] classd_phase3_cyc_shadowed_qs; + logic [31:0] classd_phase3_cyc_shadowed_wd; + logic classd_phase3_cyc_shadowed_storage_err; + logic classd_phase3_cyc_shadowed_update_err; + logic classd_esc_cnt_re; + logic [31:0] classd_esc_cnt_qs; + logic classd_state_re; + logic [2:0] classd_state_qs; + + // Register instances + // R[intr_state]: V(False) + // F[classa]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_classa ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_classa_wd), + + // from internal hardware + .de (hw2reg.intr_state.classa.de), + .d (hw2reg.intr_state.classa.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.classa.q), + .ds (), + + // to register interface (read) + .qs (intr_state_classa_qs) + ); + + // F[classb]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_classb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_classb_wd), + + // from internal hardware + .de (hw2reg.intr_state.classb.de), + .d (hw2reg.intr_state.classb.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.classb.q), + .ds (), + + // to register interface (read) + .qs (intr_state_classb_qs) + ); + + // F[classc]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_classc ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_classc_wd), + + // from internal hardware + .de (hw2reg.intr_state.classc.de), + .d (hw2reg.intr_state.classc.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.classc.q), + .ds (), + + // to register interface (read) + .qs (intr_state_classc_qs) + ); + + // F[classd]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_classd ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_classd_wd), + + // from internal hardware + .de (hw2reg.intr_state.classd.de), + .d (hw2reg.intr_state.classd.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.classd.q), + .ds (), + + // to register interface (read) + .qs (intr_state_classd_qs) + ); + + + // R[intr_enable]: V(False) + // F[classa]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_classa ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_classa_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.classa.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_classa_qs) + ); + + // F[classb]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_classb ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_classb_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.classb.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_classb_qs) + ); + + // F[classc]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_classc ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_classc_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.classc.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_classc_qs) + ); + + // F[classd]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_classd ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_classd_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.classd.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_classd_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [3:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + // F[classa]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_classa ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_classa_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.classa.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.classa.qe = intr_test_qe; + + // F[classb]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_classb ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_classb_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[1]), + .q (reg2hw.intr_test.classb.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.classb.qe = intr_test_qe; + + // F[classc]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_classc ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_classc_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[2]), + .q (reg2hw.intr_test.classc.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.classc.qe = intr_test_qe; + + // F[classd]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_classd ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_classd_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[3]), + .q (reg2hw.intr_test.classd.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.classd.qe = intr_test_qe; + + + // R[ping_timer_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_ping_timer_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ping_timer_regwen_we), + .wd (ping_timer_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ping_timer_regwen_qs) + ); + + + // R[ping_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic ping_timeout_cyc_shadowed_gated_we; + assign ping_timeout_cyc_shadowed_gated_we = ping_timeout_cyc_shadowed_we & ping_timer_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h100), + .Mubi (1'b0) + ) u_ping_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (ping_timeout_cyc_shadowed_re), + .we (ping_timeout_cyc_shadowed_gated_we), + .wd (ping_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ping_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (ping_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (ping_timeout_cyc_shadowed_update_err), + .err_storage (ping_timeout_cyc_shadowed_storage_err) + ); + + + // R[ping_timer_en_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic ping_timer_en_shadowed_gated_we; + assign ping_timer_en_shadowed_gated_we = ping_timer_en_shadowed_we & ping_timer_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1S), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ping_timer_en_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (ping_timer_en_shadowed_re), + .we (ping_timer_en_shadowed_gated_we), + .wd (ping_timer_en_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ping_timer_en_shadowed.q), + .ds (), + + // to register interface (read) + .qs (ping_timer_en_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (ping_timer_en_shadowed_update_err), + .err_storage (ping_timer_en_shadowed_storage_err) + ); + + + // Subregister 0 of Multireg alert_regwen + // R[alert_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_0_we), + .wd (alert_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[0].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_0_qs) + ); + + + // Subregister 1 of Multireg alert_regwen + // R[alert_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_1_we), + .wd (alert_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[1].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_1_qs) + ); + + + // Subregister 2 of Multireg alert_regwen + // R[alert_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_2_we), + .wd (alert_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[2].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_2_qs) + ); + + + // Subregister 3 of Multireg alert_regwen + // R[alert_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_3_we), + .wd (alert_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[3].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_3_qs) + ); + + + // Subregister 4 of Multireg alert_regwen + // R[alert_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_4_we), + .wd (alert_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[4].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_4_qs) + ); + + + // Subregister 5 of Multireg alert_regwen + // R[alert_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_5_we), + .wd (alert_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[5].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_5_qs) + ); + + + // Subregister 6 of Multireg alert_regwen + // R[alert_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_6_we), + .wd (alert_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[6].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_6_qs) + ); + + + // Subregister 7 of Multireg alert_regwen + // R[alert_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_7_we), + .wd (alert_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[7].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_7_qs) + ); + + + // Subregister 8 of Multireg alert_regwen + // R[alert_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_8_we), + .wd (alert_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[8].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_8_qs) + ); + + + // Subregister 9 of Multireg alert_regwen + // R[alert_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_9_we), + .wd (alert_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[9].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_9_qs) + ); + + + // Subregister 10 of Multireg alert_regwen + // R[alert_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_10_we), + .wd (alert_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[10].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_10_qs) + ); + + + // Subregister 11 of Multireg alert_regwen + // R[alert_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_11_we), + .wd (alert_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[11].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_11_qs) + ); + + + // Subregister 12 of Multireg alert_regwen + // R[alert_regwen_12]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_12_we), + .wd (alert_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[12].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_12_qs) + ); + + + // Subregister 13 of Multireg alert_regwen + // R[alert_regwen_13]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_13_we), + .wd (alert_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[13].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_13_qs) + ); + + + // Subregister 14 of Multireg alert_regwen + // R[alert_regwen_14]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_14_we), + .wd (alert_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[14].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_14_qs) + ); + + + // Subregister 15 of Multireg alert_regwen + // R[alert_regwen_15]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_15_we), + .wd (alert_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[15].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_15_qs) + ); + + + // Subregister 16 of Multireg alert_regwen + // R[alert_regwen_16]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_16_we), + .wd (alert_regwen_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[16].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_16_qs) + ); + + + // Subregister 17 of Multireg alert_regwen + // R[alert_regwen_17]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_17_we), + .wd (alert_regwen_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[17].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_17_qs) + ); + + + // Subregister 18 of Multireg alert_regwen + // R[alert_regwen_18]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_18_we), + .wd (alert_regwen_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[18].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_18_qs) + ); + + + // Subregister 19 of Multireg alert_regwen + // R[alert_regwen_19]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_19_we), + .wd (alert_regwen_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[19].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_19_qs) + ); + + + // Subregister 20 of Multireg alert_regwen + // R[alert_regwen_20]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_20_we), + .wd (alert_regwen_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[20].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_20_qs) + ); + + + // Subregister 21 of Multireg alert_regwen + // R[alert_regwen_21]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_21_we), + .wd (alert_regwen_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[21].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_21_qs) + ); + + + // Subregister 22 of Multireg alert_regwen + // R[alert_regwen_22]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_22_we), + .wd (alert_regwen_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[22].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_22_qs) + ); + + + // Subregister 23 of Multireg alert_regwen + // R[alert_regwen_23]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_23_we), + .wd (alert_regwen_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[23].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_23_qs) + ); + + + // Subregister 24 of Multireg alert_regwen + // R[alert_regwen_24]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_24_we), + .wd (alert_regwen_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[24].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_24_qs) + ); + + + // Subregister 25 of Multireg alert_regwen + // R[alert_regwen_25]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_25_we), + .wd (alert_regwen_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[25].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_25_qs) + ); + + + // Subregister 26 of Multireg alert_regwen + // R[alert_regwen_26]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_26_we), + .wd (alert_regwen_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[26].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_26_qs) + ); + + + // Subregister 27 of Multireg alert_regwen + // R[alert_regwen_27]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_27_we), + .wd (alert_regwen_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[27].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_27_qs) + ); + + + // Subregister 28 of Multireg alert_regwen + // R[alert_regwen_28]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_28_we), + .wd (alert_regwen_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[28].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_28_qs) + ); + + + // Subregister 29 of Multireg alert_regwen + // R[alert_regwen_29]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_29_we), + .wd (alert_regwen_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[29].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_29_qs) + ); + + + // Subregister 30 of Multireg alert_regwen + // R[alert_regwen_30]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_30_we), + .wd (alert_regwen_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[30].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_30_qs) + ); + + + // Subregister 31 of Multireg alert_regwen + // R[alert_regwen_31]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_31_we), + .wd (alert_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[31].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_31_qs) + ); + + + // Subregister 32 of Multireg alert_regwen + // R[alert_regwen_32]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_32_we), + .wd (alert_regwen_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[32].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_32_qs) + ); + + + // Subregister 33 of Multireg alert_regwen + // R[alert_regwen_33]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_33_we), + .wd (alert_regwen_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[33].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_33_qs) + ); + + + // Subregister 34 of Multireg alert_regwen + // R[alert_regwen_34]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_34_we), + .wd (alert_regwen_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[34].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_34_qs) + ); + + + // Subregister 35 of Multireg alert_regwen + // R[alert_regwen_35]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_35_we), + .wd (alert_regwen_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[35].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_35_qs) + ); + + + // Subregister 36 of Multireg alert_regwen + // R[alert_regwen_36]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_36_we), + .wd (alert_regwen_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[36].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_36_qs) + ); + + + // Subregister 37 of Multireg alert_regwen + // R[alert_regwen_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_37_we), + .wd (alert_regwen_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[37].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_37_qs) + ); + + + // Subregister 38 of Multireg alert_regwen + // R[alert_regwen_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_38_we), + .wd (alert_regwen_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[38].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_38_qs) + ); + + + // Subregister 39 of Multireg alert_regwen + // R[alert_regwen_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_39_we), + .wd (alert_regwen_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[39].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_39_qs) + ); + + + // Subregister 40 of Multireg alert_regwen + // R[alert_regwen_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_40_we), + .wd (alert_regwen_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[40].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_40_qs) + ); + + + // Subregister 41 of Multireg alert_regwen + // R[alert_regwen_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_41_we), + .wd (alert_regwen_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[41].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_41_qs) + ); + + + // Subregister 42 of Multireg alert_regwen + // R[alert_regwen_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_42_we), + .wd (alert_regwen_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[42].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_42_qs) + ); + + + // Subregister 43 of Multireg alert_regwen + // R[alert_regwen_43]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_43_we), + .wd (alert_regwen_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[43].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_43_qs) + ); + + + // Subregister 44 of Multireg alert_regwen + // R[alert_regwen_44]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_44_we), + .wd (alert_regwen_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[44].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_44_qs) + ); + + + // Subregister 45 of Multireg alert_regwen + // R[alert_regwen_45]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_45_we), + .wd (alert_regwen_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[45].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_45_qs) + ); + + + // Subregister 46 of Multireg alert_regwen + // R[alert_regwen_46]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_46_we), + .wd (alert_regwen_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[46].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_46_qs) + ); + + + // Subregister 47 of Multireg alert_regwen + // R[alert_regwen_47]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_47_we), + .wd (alert_regwen_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[47].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_47_qs) + ); + + + // Subregister 48 of Multireg alert_regwen + // R[alert_regwen_48]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_48_we), + .wd (alert_regwen_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[48].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_48_qs) + ); + + + // Subregister 49 of Multireg alert_regwen + // R[alert_regwen_49]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_49_we), + .wd (alert_regwen_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[49].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_49_qs) + ); + + + // Subregister 50 of Multireg alert_regwen + // R[alert_regwen_50]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_50_we), + .wd (alert_regwen_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[50].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_50_qs) + ); + + + // Subregister 51 of Multireg alert_regwen + // R[alert_regwen_51]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_51_we), + .wd (alert_regwen_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[51].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_51_qs) + ); + + + // Subregister 52 of Multireg alert_regwen + // R[alert_regwen_52]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_52_we), + .wd (alert_regwen_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[52].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_52_qs) + ); + + + // Subregister 53 of Multireg alert_regwen + // R[alert_regwen_53]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_53_we), + .wd (alert_regwen_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[53].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_53_qs) + ); + + + // Subregister 54 of Multireg alert_regwen + // R[alert_regwen_54]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_54_we), + .wd (alert_regwen_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[54].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_54_qs) + ); + + + // Subregister 55 of Multireg alert_regwen + // R[alert_regwen_55]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_55_we), + .wd (alert_regwen_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[55].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_55_qs) + ); + + + // Subregister 56 of Multireg alert_regwen + // R[alert_regwen_56]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_56_we), + .wd (alert_regwen_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[56].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_56_qs) + ); + + + // Subregister 57 of Multireg alert_regwen + // R[alert_regwen_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_57_we), + .wd (alert_regwen_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[57].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_57_qs) + ); + + + // Subregister 58 of Multireg alert_regwen + // R[alert_regwen_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_58_we), + .wd (alert_regwen_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[58].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_58_qs) + ); + + + // Subregister 59 of Multireg alert_regwen + // R[alert_regwen_59]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_59_we), + .wd (alert_regwen_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[59].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_59_qs) + ); + + + // Subregister 60 of Multireg alert_regwen + // R[alert_regwen_60]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_60_we), + .wd (alert_regwen_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[60].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_60_qs) + ); + + + // Subregister 61 of Multireg alert_regwen + // R[alert_regwen_61]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_61_we), + .wd (alert_regwen_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[61].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_61_qs) + ); + + + // Subregister 62 of Multireg alert_regwen + // R[alert_regwen_62]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_62_we), + .wd (alert_regwen_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[62].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_62_qs) + ); + + + // Subregister 63 of Multireg alert_regwen + // R[alert_regwen_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_63_we), + .wd (alert_regwen_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[63].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_63_qs) + ); + + + // Subregister 64 of Multireg alert_regwen + // R[alert_regwen_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_64_we), + .wd (alert_regwen_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[64].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_64_qs) + ); + + + // Subregister 65 of Multireg alert_regwen + // R[alert_regwen_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_65_we), + .wd (alert_regwen_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[65].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_65_qs) + ); + + + // Subregister 66 of Multireg alert_regwen + // R[alert_regwen_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_66_we), + .wd (alert_regwen_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[66].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_66_qs) + ); + + + // Subregister 67 of Multireg alert_regwen + // R[alert_regwen_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_67_we), + .wd (alert_regwen_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[67].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_67_qs) + ); + + + // Subregister 68 of Multireg alert_regwen + // R[alert_regwen_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_68_we), + .wd (alert_regwen_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[68].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_68_qs) + ); + + + // Subregister 69 of Multireg alert_regwen + // R[alert_regwen_69]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_69_we), + .wd (alert_regwen_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[69].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_69_qs) + ); + + + // Subregister 70 of Multireg alert_regwen + // R[alert_regwen_70]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_70_we), + .wd (alert_regwen_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[70].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_70_qs) + ); + + + // Subregister 71 of Multireg alert_regwen + // R[alert_regwen_71]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_71_we), + .wd (alert_regwen_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[71].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_71_qs) + ); + + + // Subregister 72 of Multireg alert_regwen + // R[alert_regwen_72]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_72_we), + .wd (alert_regwen_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[72].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_72_qs) + ); + + + // Subregister 73 of Multireg alert_regwen + // R[alert_regwen_73]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_73_we), + .wd (alert_regwen_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[73].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_73_qs) + ); + + + // Subregister 74 of Multireg alert_regwen + // R[alert_regwen_74]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_74_we), + .wd (alert_regwen_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[74].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_74_qs) + ); + + + // Subregister 75 of Multireg alert_regwen + // R[alert_regwen_75]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_75_we), + .wd (alert_regwen_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[75].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_75_qs) + ); + + + // Subregister 76 of Multireg alert_regwen + // R[alert_regwen_76]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_76_we), + .wd (alert_regwen_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[76].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_76_qs) + ); + + + // Subregister 77 of Multireg alert_regwen + // R[alert_regwen_77]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_77_we), + .wd (alert_regwen_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[77].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_77_qs) + ); + + + // Subregister 78 of Multireg alert_regwen + // R[alert_regwen_78]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_78_we), + .wd (alert_regwen_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[78].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_78_qs) + ); + + + // Subregister 79 of Multireg alert_regwen + // R[alert_regwen_79]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_79_we), + .wd (alert_regwen_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[79].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_79_qs) + ); + + + // Subregister 80 of Multireg alert_regwen + // R[alert_regwen_80]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_80_we), + .wd (alert_regwen_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[80].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_80_qs) + ); + + + // Subregister 81 of Multireg alert_regwen + // R[alert_regwen_81]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_81_we), + .wd (alert_regwen_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[81].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_81_qs) + ); + + + // Subregister 82 of Multireg alert_regwen + // R[alert_regwen_82]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_82_we), + .wd (alert_regwen_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[82].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_82_qs) + ); + + + // Subregister 83 of Multireg alert_regwen + // R[alert_regwen_83]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_83_we), + .wd (alert_regwen_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[83].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_83_qs) + ); + + + // Subregister 84 of Multireg alert_regwen + // R[alert_regwen_84]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_84_we), + .wd (alert_regwen_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[84].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_84_qs) + ); + + + // Subregister 85 of Multireg alert_regwen + // R[alert_regwen_85]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_85_we), + .wd (alert_regwen_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[85].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_85_qs) + ); + + + // Subregister 86 of Multireg alert_regwen + // R[alert_regwen_86]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_86_we), + .wd (alert_regwen_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[86].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_86_qs) + ); + + + // Subregister 87 of Multireg alert_regwen + // R[alert_regwen_87]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_87_we), + .wd (alert_regwen_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[87].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_87_qs) + ); + + + // Subregister 88 of Multireg alert_regwen + // R[alert_regwen_88]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_88_we), + .wd (alert_regwen_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[88].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_88_qs) + ); + + + // Subregister 89 of Multireg alert_regwen + // R[alert_regwen_89]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_89_we), + .wd (alert_regwen_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[89].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_89_qs) + ); + + + // Subregister 90 of Multireg alert_regwen + // R[alert_regwen_90]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_90_we), + .wd (alert_regwen_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[90].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_90_qs) + ); + + + // Subregister 91 of Multireg alert_regwen + // R[alert_regwen_91]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_91_we), + .wd (alert_regwen_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[91].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_91_qs) + ); + + + // Subregister 92 of Multireg alert_regwen + // R[alert_regwen_92]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_92_we), + .wd (alert_regwen_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[92].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_92_qs) + ); + + + // Subregister 93 of Multireg alert_regwen + // R[alert_regwen_93]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_93_we), + .wd (alert_regwen_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[93].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_93_qs) + ); + + + // Subregister 94 of Multireg alert_regwen + // R[alert_regwen_94]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_94_we), + .wd (alert_regwen_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[94].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_94_qs) + ); + + + // Subregister 95 of Multireg alert_regwen + // R[alert_regwen_95]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_95_we), + .wd (alert_regwen_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[95].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_95_qs) + ); + + + // Subregister 96 of Multireg alert_regwen + // R[alert_regwen_96]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_96_we), + .wd (alert_regwen_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[96].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_96_qs) + ); + + + // Subregister 97 of Multireg alert_regwen + // R[alert_regwen_97]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_97_we), + .wd (alert_regwen_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[97].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_97_qs) + ); + + + // Subregister 98 of Multireg alert_regwen + // R[alert_regwen_98]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_98_we), + .wd (alert_regwen_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_regwen[98].q), + .ds (), + + // to register interface (read) + .qs (alert_regwen_98_qs) + ); + + + // Subregister 0 of Multireg alert_en_shadowed + // R[alert_en_shadowed_0]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_0_gated_we; + assign alert_en_shadowed_0_gated_we = alert_en_shadowed_0_we & alert_regwen_0_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_0_re), + .we (alert_en_shadowed_0_gated_we), + .wd (alert_en_shadowed_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[0].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_0_update_err), + .err_storage (alert_en_shadowed_0_storage_err) + ); + + + // Subregister 1 of Multireg alert_en_shadowed + // R[alert_en_shadowed_1]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_1_gated_we; + assign alert_en_shadowed_1_gated_we = alert_en_shadowed_1_we & alert_regwen_1_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_1_re), + .we (alert_en_shadowed_1_gated_we), + .wd (alert_en_shadowed_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[1].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_1_update_err), + .err_storage (alert_en_shadowed_1_storage_err) + ); + + + // Subregister 2 of Multireg alert_en_shadowed + // R[alert_en_shadowed_2]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_2_gated_we; + assign alert_en_shadowed_2_gated_we = alert_en_shadowed_2_we & alert_regwen_2_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_2_re), + .we (alert_en_shadowed_2_gated_we), + .wd (alert_en_shadowed_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[2].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_2_update_err), + .err_storage (alert_en_shadowed_2_storage_err) + ); + + + // Subregister 3 of Multireg alert_en_shadowed + // R[alert_en_shadowed_3]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_3_gated_we; + assign alert_en_shadowed_3_gated_we = alert_en_shadowed_3_we & alert_regwen_3_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_3_re), + .we (alert_en_shadowed_3_gated_we), + .wd (alert_en_shadowed_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[3].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_3_update_err), + .err_storage (alert_en_shadowed_3_storage_err) + ); + + + // Subregister 4 of Multireg alert_en_shadowed + // R[alert_en_shadowed_4]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_4_gated_we; + assign alert_en_shadowed_4_gated_we = alert_en_shadowed_4_we & alert_regwen_4_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_4_re), + .we (alert_en_shadowed_4_gated_we), + .wd (alert_en_shadowed_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[4].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_4_update_err), + .err_storage (alert_en_shadowed_4_storage_err) + ); + + + // Subregister 5 of Multireg alert_en_shadowed + // R[alert_en_shadowed_5]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_5_gated_we; + assign alert_en_shadowed_5_gated_we = alert_en_shadowed_5_we & alert_regwen_5_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_5_re), + .we (alert_en_shadowed_5_gated_we), + .wd (alert_en_shadowed_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[5].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_5_update_err), + .err_storage (alert_en_shadowed_5_storage_err) + ); + + + // Subregister 6 of Multireg alert_en_shadowed + // R[alert_en_shadowed_6]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_6_gated_we; + assign alert_en_shadowed_6_gated_we = alert_en_shadowed_6_we & alert_regwen_6_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_6_re), + .we (alert_en_shadowed_6_gated_we), + .wd (alert_en_shadowed_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[6].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_6_update_err), + .err_storage (alert_en_shadowed_6_storage_err) + ); + + + // Subregister 7 of Multireg alert_en_shadowed + // R[alert_en_shadowed_7]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_7_gated_we; + assign alert_en_shadowed_7_gated_we = alert_en_shadowed_7_we & alert_regwen_7_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_7_re), + .we (alert_en_shadowed_7_gated_we), + .wd (alert_en_shadowed_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[7].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_7_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_7_update_err), + .err_storage (alert_en_shadowed_7_storage_err) + ); + + + // Subregister 8 of Multireg alert_en_shadowed + // R[alert_en_shadowed_8]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_8_gated_we; + assign alert_en_shadowed_8_gated_we = alert_en_shadowed_8_we & alert_regwen_8_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_8_re), + .we (alert_en_shadowed_8_gated_we), + .wd (alert_en_shadowed_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[8].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_8_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_8_update_err), + .err_storage (alert_en_shadowed_8_storage_err) + ); + + + // Subregister 9 of Multireg alert_en_shadowed + // R[alert_en_shadowed_9]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_9_gated_we; + assign alert_en_shadowed_9_gated_we = alert_en_shadowed_9_we & alert_regwen_9_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_9_re), + .we (alert_en_shadowed_9_gated_we), + .wd (alert_en_shadowed_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[9].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_9_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_9_update_err), + .err_storage (alert_en_shadowed_9_storage_err) + ); + + + // Subregister 10 of Multireg alert_en_shadowed + // R[alert_en_shadowed_10]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_10_gated_we; + assign alert_en_shadowed_10_gated_we = alert_en_shadowed_10_we & alert_regwen_10_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_10_re), + .we (alert_en_shadowed_10_gated_we), + .wd (alert_en_shadowed_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[10].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_10_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_10_update_err), + .err_storage (alert_en_shadowed_10_storage_err) + ); + + + // Subregister 11 of Multireg alert_en_shadowed + // R[alert_en_shadowed_11]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_11_gated_we; + assign alert_en_shadowed_11_gated_we = alert_en_shadowed_11_we & alert_regwen_11_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_11_re), + .we (alert_en_shadowed_11_gated_we), + .wd (alert_en_shadowed_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[11].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_11_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_11_update_err), + .err_storage (alert_en_shadowed_11_storage_err) + ); + + + // Subregister 12 of Multireg alert_en_shadowed + // R[alert_en_shadowed_12]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_12_gated_we; + assign alert_en_shadowed_12_gated_we = alert_en_shadowed_12_we & alert_regwen_12_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_12_re), + .we (alert_en_shadowed_12_gated_we), + .wd (alert_en_shadowed_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[12].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_12_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_12_update_err), + .err_storage (alert_en_shadowed_12_storage_err) + ); + + + // Subregister 13 of Multireg alert_en_shadowed + // R[alert_en_shadowed_13]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_13_gated_we; + assign alert_en_shadowed_13_gated_we = alert_en_shadowed_13_we & alert_regwen_13_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_13_re), + .we (alert_en_shadowed_13_gated_we), + .wd (alert_en_shadowed_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[13].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_13_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_13_update_err), + .err_storage (alert_en_shadowed_13_storage_err) + ); + + + // Subregister 14 of Multireg alert_en_shadowed + // R[alert_en_shadowed_14]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_14_gated_we; + assign alert_en_shadowed_14_gated_we = alert_en_shadowed_14_we & alert_regwen_14_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_14_re), + .we (alert_en_shadowed_14_gated_we), + .wd (alert_en_shadowed_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[14].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_14_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_14_update_err), + .err_storage (alert_en_shadowed_14_storage_err) + ); + + + // Subregister 15 of Multireg alert_en_shadowed + // R[alert_en_shadowed_15]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_15_gated_we; + assign alert_en_shadowed_15_gated_we = alert_en_shadowed_15_we & alert_regwen_15_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_15_re), + .we (alert_en_shadowed_15_gated_we), + .wd (alert_en_shadowed_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[15].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_15_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_15_update_err), + .err_storage (alert_en_shadowed_15_storage_err) + ); + + + // Subregister 16 of Multireg alert_en_shadowed + // R[alert_en_shadowed_16]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_16_gated_we; + assign alert_en_shadowed_16_gated_we = alert_en_shadowed_16_we & alert_regwen_16_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_16_re), + .we (alert_en_shadowed_16_gated_we), + .wd (alert_en_shadowed_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[16].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_16_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_16_update_err), + .err_storage (alert_en_shadowed_16_storage_err) + ); + + + // Subregister 17 of Multireg alert_en_shadowed + // R[alert_en_shadowed_17]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_17_gated_we; + assign alert_en_shadowed_17_gated_we = alert_en_shadowed_17_we & alert_regwen_17_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_17_re), + .we (alert_en_shadowed_17_gated_we), + .wd (alert_en_shadowed_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[17].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_17_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_17_update_err), + .err_storage (alert_en_shadowed_17_storage_err) + ); + + + // Subregister 18 of Multireg alert_en_shadowed + // R[alert_en_shadowed_18]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_18_gated_we; + assign alert_en_shadowed_18_gated_we = alert_en_shadowed_18_we & alert_regwen_18_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_18_re), + .we (alert_en_shadowed_18_gated_we), + .wd (alert_en_shadowed_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[18].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_18_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_18_update_err), + .err_storage (alert_en_shadowed_18_storage_err) + ); + + + // Subregister 19 of Multireg alert_en_shadowed + // R[alert_en_shadowed_19]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_19_gated_we; + assign alert_en_shadowed_19_gated_we = alert_en_shadowed_19_we & alert_regwen_19_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_19_re), + .we (alert_en_shadowed_19_gated_we), + .wd (alert_en_shadowed_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[19].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_19_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_19_update_err), + .err_storage (alert_en_shadowed_19_storage_err) + ); + + + // Subregister 20 of Multireg alert_en_shadowed + // R[alert_en_shadowed_20]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_20_gated_we; + assign alert_en_shadowed_20_gated_we = alert_en_shadowed_20_we & alert_regwen_20_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_20_re), + .we (alert_en_shadowed_20_gated_we), + .wd (alert_en_shadowed_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[20].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_20_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_20_update_err), + .err_storage (alert_en_shadowed_20_storage_err) + ); + + + // Subregister 21 of Multireg alert_en_shadowed + // R[alert_en_shadowed_21]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_21_gated_we; + assign alert_en_shadowed_21_gated_we = alert_en_shadowed_21_we & alert_regwen_21_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_21_re), + .we (alert_en_shadowed_21_gated_we), + .wd (alert_en_shadowed_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[21].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_21_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_21_update_err), + .err_storage (alert_en_shadowed_21_storage_err) + ); + + + // Subregister 22 of Multireg alert_en_shadowed + // R[alert_en_shadowed_22]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_22_gated_we; + assign alert_en_shadowed_22_gated_we = alert_en_shadowed_22_we & alert_regwen_22_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_22_re), + .we (alert_en_shadowed_22_gated_we), + .wd (alert_en_shadowed_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[22].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_22_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_22_update_err), + .err_storage (alert_en_shadowed_22_storage_err) + ); + + + // Subregister 23 of Multireg alert_en_shadowed + // R[alert_en_shadowed_23]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_23_gated_we; + assign alert_en_shadowed_23_gated_we = alert_en_shadowed_23_we & alert_regwen_23_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_23_re), + .we (alert_en_shadowed_23_gated_we), + .wd (alert_en_shadowed_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[23].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_23_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_23_update_err), + .err_storage (alert_en_shadowed_23_storage_err) + ); + + + // Subregister 24 of Multireg alert_en_shadowed + // R[alert_en_shadowed_24]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_24_gated_we; + assign alert_en_shadowed_24_gated_we = alert_en_shadowed_24_we & alert_regwen_24_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_24_re), + .we (alert_en_shadowed_24_gated_we), + .wd (alert_en_shadowed_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[24].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_24_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_24_update_err), + .err_storage (alert_en_shadowed_24_storage_err) + ); + + + // Subregister 25 of Multireg alert_en_shadowed + // R[alert_en_shadowed_25]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_25_gated_we; + assign alert_en_shadowed_25_gated_we = alert_en_shadowed_25_we & alert_regwen_25_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_25_re), + .we (alert_en_shadowed_25_gated_we), + .wd (alert_en_shadowed_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[25].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_25_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_25_update_err), + .err_storage (alert_en_shadowed_25_storage_err) + ); + + + // Subregister 26 of Multireg alert_en_shadowed + // R[alert_en_shadowed_26]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_26_gated_we; + assign alert_en_shadowed_26_gated_we = alert_en_shadowed_26_we & alert_regwen_26_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_26_re), + .we (alert_en_shadowed_26_gated_we), + .wd (alert_en_shadowed_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[26].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_26_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_26_update_err), + .err_storage (alert_en_shadowed_26_storage_err) + ); + + + // Subregister 27 of Multireg alert_en_shadowed + // R[alert_en_shadowed_27]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_27_gated_we; + assign alert_en_shadowed_27_gated_we = alert_en_shadowed_27_we & alert_regwen_27_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_27_re), + .we (alert_en_shadowed_27_gated_we), + .wd (alert_en_shadowed_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[27].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_27_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_27_update_err), + .err_storage (alert_en_shadowed_27_storage_err) + ); + + + // Subregister 28 of Multireg alert_en_shadowed + // R[alert_en_shadowed_28]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_28_gated_we; + assign alert_en_shadowed_28_gated_we = alert_en_shadowed_28_we & alert_regwen_28_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_28_re), + .we (alert_en_shadowed_28_gated_we), + .wd (alert_en_shadowed_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[28].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_28_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_28_update_err), + .err_storage (alert_en_shadowed_28_storage_err) + ); + + + // Subregister 29 of Multireg alert_en_shadowed + // R[alert_en_shadowed_29]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_29_gated_we; + assign alert_en_shadowed_29_gated_we = alert_en_shadowed_29_we & alert_regwen_29_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_29_re), + .we (alert_en_shadowed_29_gated_we), + .wd (alert_en_shadowed_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[29].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_29_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_29_update_err), + .err_storage (alert_en_shadowed_29_storage_err) + ); + + + // Subregister 30 of Multireg alert_en_shadowed + // R[alert_en_shadowed_30]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_30_gated_we; + assign alert_en_shadowed_30_gated_we = alert_en_shadowed_30_we & alert_regwen_30_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_30_re), + .we (alert_en_shadowed_30_gated_we), + .wd (alert_en_shadowed_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[30].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_30_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_30_update_err), + .err_storage (alert_en_shadowed_30_storage_err) + ); + + + // Subregister 31 of Multireg alert_en_shadowed + // R[alert_en_shadowed_31]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_31_gated_we; + assign alert_en_shadowed_31_gated_we = alert_en_shadowed_31_we & alert_regwen_31_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_31_re), + .we (alert_en_shadowed_31_gated_we), + .wd (alert_en_shadowed_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[31].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_31_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_31_update_err), + .err_storage (alert_en_shadowed_31_storage_err) + ); + + + // Subregister 32 of Multireg alert_en_shadowed + // R[alert_en_shadowed_32]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_32_gated_we; + assign alert_en_shadowed_32_gated_we = alert_en_shadowed_32_we & alert_regwen_32_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_32_re), + .we (alert_en_shadowed_32_gated_we), + .wd (alert_en_shadowed_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[32].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_32_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_32_update_err), + .err_storage (alert_en_shadowed_32_storage_err) + ); + + + // Subregister 33 of Multireg alert_en_shadowed + // R[alert_en_shadowed_33]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_33_gated_we; + assign alert_en_shadowed_33_gated_we = alert_en_shadowed_33_we & alert_regwen_33_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_33_re), + .we (alert_en_shadowed_33_gated_we), + .wd (alert_en_shadowed_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[33].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_33_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_33_update_err), + .err_storage (alert_en_shadowed_33_storage_err) + ); + + + // Subregister 34 of Multireg alert_en_shadowed + // R[alert_en_shadowed_34]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_34_gated_we; + assign alert_en_shadowed_34_gated_we = alert_en_shadowed_34_we & alert_regwen_34_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_34_re), + .we (alert_en_shadowed_34_gated_we), + .wd (alert_en_shadowed_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[34].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_34_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_34_update_err), + .err_storage (alert_en_shadowed_34_storage_err) + ); + + + // Subregister 35 of Multireg alert_en_shadowed + // R[alert_en_shadowed_35]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_35_gated_we; + assign alert_en_shadowed_35_gated_we = alert_en_shadowed_35_we & alert_regwen_35_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_35_re), + .we (alert_en_shadowed_35_gated_we), + .wd (alert_en_shadowed_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[35].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_35_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_35_update_err), + .err_storage (alert_en_shadowed_35_storage_err) + ); + + + // Subregister 36 of Multireg alert_en_shadowed + // R[alert_en_shadowed_36]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_36_gated_we; + assign alert_en_shadowed_36_gated_we = alert_en_shadowed_36_we & alert_regwen_36_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_36_re), + .we (alert_en_shadowed_36_gated_we), + .wd (alert_en_shadowed_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[36].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_36_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_36_update_err), + .err_storage (alert_en_shadowed_36_storage_err) + ); + + + // Subregister 37 of Multireg alert_en_shadowed + // R[alert_en_shadowed_37]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_37_gated_we; + assign alert_en_shadowed_37_gated_we = alert_en_shadowed_37_we & alert_regwen_37_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_37_re), + .we (alert_en_shadowed_37_gated_we), + .wd (alert_en_shadowed_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[37].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_37_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_37_update_err), + .err_storage (alert_en_shadowed_37_storage_err) + ); + + + // Subregister 38 of Multireg alert_en_shadowed + // R[alert_en_shadowed_38]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_38_gated_we; + assign alert_en_shadowed_38_gated_we = alert_en_shadowed_38_we & alert_regwen_38_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_38_re), + .we (alert_en_shadowed_38_gated_we), + .wd (alert_en_shadowed_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[38].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_38_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_38_update_err), + .err_storage (alert_en_shadowed_38_storage_err) + ); + + + // Subregister 39 of Multireg alert_en_shadowed + // R[alert_en_shadowed_39]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_39_gated_we; + assign alert_en_shadowed_39_gated_we = alert_en_shadowed_39_we & alert_regwen_39_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_39_re), + .we (alert_en_shadowed_39_gated_we), + .wd (alert_en_shadowed_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[39].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_39_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_39_update_err), + .err_storage (alert_en_shadowed_39_storage_err) + ); + + + // Subregister 40 of Multireg alert_en_shadowed + // R[alert_en_shadowed_40]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_40_gated_we; + assign alert_en_shadowed_40_gated_we = alert_en_shadowed_40_we & alert_regwen_40_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_40_re), + .we (alert_en_shadowed_40_gated_we), + .wd (alert_en_shadowed_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[40].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_40_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_40_update_err), + .err_storage (alert_en_shadowed_40_storage_err) + ); + + + // Subregister 41 of Multireg alert_en_shadowed + // R[alert_en_shadowed_41]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_41_gated_we; + assign alert_en_shadowed_41_gated_we = alert_en_shadowed_41_we & alert_regwen_41_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_41_re), + .we (alert_en_shadowed_41_gated_we), + .wd (alert_en_shadowed_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[41].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_41_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_41_update_err), + .err_storage (alert_en_shadowed_41_storage_err) + ); + + + // Subregister 42 of Multireg alert_en_shadowed + // R[alert_en_shadowed_42]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_42_gated_we; + assign alert_en_shadowed_42_gated_we = alert_en_shadowed_42_we & alert_regwen_42_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_42_re), + .we (alert_en_shadowed_42_gated_we), + .wd (alert_en_shadowed_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[42].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_42_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_42_update_err), + .err_storage (alert_en_shadowed_42_storage_err) + ); + + + // Subregister 43 of Multireg alert_en_shadowed + // R[alert_en_shadowed_43]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_43_gated_we; + assign alert_en_shadowed_43_gated_we = alert_en_shadowed_43_we & alert_regwen_43_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_43_re), + .we (alert_en_shadowed_43_gated_we), + .wd (alert_en_shadowed_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[43].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_43_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_43_update_err), + .err_storage (alert_en_shadowed_43_storage_err) + ); + + + // Subregister 44 of Multireg alert_en_shadowed + // R[alert_en_shadowed_44]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_44_gated_we; + assign alert_en_shadowed_44_gated_we = alert_en_shadowed_44_we & alert_regwen_44_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_44_re), + .we (alert_en_shadowed_44_gated_we), + .wd (alert_en_shadowed_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[44].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_44_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_44_update_err), + .err_storage (alert_en_shadowed_44_storage_err) + ); + + + // Subregister 45 of Multireg alert_en_shadowed + // R[alert_en_shadowed_45]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_45_gated_we; + assign alert_en_shadowed_45_gated_we = alert_en_shadowed_45_we & alert_regwen_45_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_45_re), + .we (alert_en_shadowed_45_gated_we), + .wd (alert_en_shadowed_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[45].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_45_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_45_update_err), + .err_storage (alert_en_shadowed_45_storage_err) + ); + + + // Subregister 46 of Multireg alert_en_shadowed + // R[alert_en_shadowed_46]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_46_gated_we; + assign alert_en_shadowed_46_gated_we = alert_en_shadowed_46_we & alert_regwen_46_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_46_re), + .we (alert_en_shadowed_46_gated_we), + .wd (alert_en_shadowed_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[46].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_46_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_46_update_err), + .err_storage (alert_en_shadowed_46_storage_err) + ); + + + // Subregister 47 of Multireg alert_en_shadowed + // R[alert_en_shadowed_47]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_47_gated_we; + assign alert_en_shadowed_47_gated_we = alert_en_shadowed_47_we & alert_regwen_47_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_47_re), + .we (alert_en_shadowed_47_gated_we), + .wd (alert_en_shadowed_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[47].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_47_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_47_update_err), + .err_storage (alert_en_shadowed_47_storage_err) + ); + + + // Subregister 48 of Multireg alert_en_shadowed + // R[alert_en_shadowed_48]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_48_gated_we; + assign alert_en_shadowed_48_gated_we = alert_en_shadowed_48_we & alert_regwen_48_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_48_re), + .we (alert_en_shadowed_48_gated_we), + .wd (alert_en_shadowed_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[48].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_48_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_48_update_err), + .err_storage (alert_en_shadowed_48_storage_err) + ); + + + // Subregister 49 of Multireg alert_en_shadowed + // R[alert_en_shadowed_49]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_49_gated_we; + assign alert_en_shadowed_49_gated_we = alert_en_shadowed_49_we & alert_regwen_49_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_49_re), + .we (alert_en_shadowed_49_gated_we), + .wd (alert_en_shadowed_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[49].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_49_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_49_update_err), + .err_storage (alert_en_shadowed_49_storage_err) + ); + + + // Subregister 50 of Multireg alert_en_shadowed + // R[alert_en_shadowed_50]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_50_gated_we; + assign alert_en_shadowed_50_gated_we = alert_en_shadowed_50_we & alert_regwen_50_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_50_re), + .we (alert_en_shadowed_50_gated_we), + .wd (alert_en_shadowed_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[50].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_50_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_50_update_err), + .err_storage (alert_en_shadowed_50_storage_err) + ); + + + // Subregister 51 of Multireg alert_en_shadowed + // R[alert_en_shadowed_51]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_51_gated_we; + assign alert_en_shadowed_51_gated_we = alert_en_shadowed_51_we & alert_regwen_51_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_51_re), + .we (alert_en_shadowed_51_gated_we), + .wd (alert_en_shadowed_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[51].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_51_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_51_update_err), + .err_storage (alert_en_shadowed_51_storage_err) + ); + + + // Subregister 52 of Multireg alert_en_shadowed + // R[alert_en_shadowed_52]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_52_gated_we; + assign alert_en_shadowed_52_gated_we = alert_en_shadowed_52_we & alert_regwen_52_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_52_re), + .we (alert_en_shadowed_52_gated_we), + .wd (alert_en_shadowed_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[52].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_52_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_52_update_err), + .err_storage (alert_en_shadowed_52_storage_err) + ); + + + // Subregister 53 of Multireg alert_en_shadowed + // R[alert_en_shadowed_53]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_53_gated_we; + assign alert_en_shadowed_53_gated_we = alert_en_shadowed_53_we & alert_regwen_53_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_53_re), + .we (alert_en_shadowed_53_gated_we), + .wd (alert_en_shadowed_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[53].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_53_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_53_update_err), + .err_storage (alert_en_shadowed_53_storage_err) + ); + + + // Subregister 54 of Multireg alert_en_shadowed + // R[alert_en_shadowed_54]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_54_gated_we; + assign alert_en_shadowed_54_gated_we = alert_en_shadowed_54_we & alert_regwen_54_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_54_re), + .we (alert_en_shadowed_54_gated_we), + .wd (alert_en_shadowed_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[54].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_54_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_54_update_err), + .err_storage (alert_en_shadowed_54_storage_err) + ); + + + // Subregister 55 of Multireg alert_en_shadowed + // R[alert_en_shadowed_55]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_55_gated_we; + assign alert_en_shadowed_55_gated_we = alert_en_shadowed_55_we & alert_regwen_55_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_55_re), + .we (alert_en_shadowed_55_gated_we), + .wd (alert_en_shadowed_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[55].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_55_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_55_update_err), + .err_storage (alert_en_shadowed_55_storage_err) + ); + + + // Subregister 56 of Multireg alert_en_shadowed + // R[alert_en_shadowed_56]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_56_gated_we; + assign alert_en_shadowed_56_gated_we = alert_en_shadowed_56_we & alert_regwen_56_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_56_re), + .we (alert_en_shadowed_56_gated_we), + .wd (alert_en_shadowed_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[56].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_56_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_56_update_err), + .err_storage (alert_en_shadowed_56_storage_err) + ); + + + // Subregister 57 of Multireg alert_en_shadowed + // R[alert_en_shadowed_57]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_57_gated_we; + assign alert_en_shadowed_57_gated_we = alert_en_shadowed_57_we & alert_regwen_57_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_57_re), + .we (alert_en_shadowed_57_gated_we), + .wd (alert_en_shadowed_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[57].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_57_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_57_update_err), + .err_storage (alert_en_shadowed_57_storage_err) + ); + + + // Subregister 58 of Multireg alert_en_shadowed + // R[alert_en_shadowed_58]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_58_gated_we; + assign alert_en_shadowed_58_gated_we = alert_en_shadowed_58_we & alert_regwen_58_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_58_re), + .we (alert_en_shadowed_58_gated_we), + .wd (alert_en_shadowed_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[58].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_58_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_58_update_err), + .err_storage (alert_en_shadowed_58_storage_err) + ); + + + // Subregister 59 of Multireg alert_en_shadowed + // R[alert_en_shadowed_59]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_59_gated_we; + assign alert_en_shadowed_59_gated_we = alert_en_shadowed_59_we & alert_regwen_59_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_59_re), + .we (alert_en_shadowed_59_gated_we), + .wd (alert_en_shadowed_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[59].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_59_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_59_update_err), + .err_storage (alert_en_shadowed_59_storage_err) + ); + + + // Subregister 60 of Multireg alert_en_shadowed + // R[alert_en_shadowed_60]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_60_gated_we; + assign alert_en_shadowed_60_gated_we = alert_en_shadowed_60_we & alert_regwen_60_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_60_re), + .we (alert_en_shadowed_60_gated_we), + .wd (alert_en_shadowed_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[60].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_60_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_60_update_err), + .err_storage (alert_en_shadowed_60_storage_err) + ); + + + // Subregister 61 of Multireg alert_en_shadowed + // R[alert_en_shadowed_61]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_61_gated_we; + assign alert_en_shadowed_61_gated_we = alert_en_shadowed_61_we & alert_regwen_61_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_61_re), + .we (alert_en_shadowed_61_gated_we), + .wd (alert_en_shadowed_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[61].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_61_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_61_update_err), + .err_storage (alert_en_shadowed_61_storage_err) + ); + + + // Subregister 62 of Multireg alert_en_shadowed + // R[alert_en_shadowed_62]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_62_gated_we; + assign alert_en_shadowed_62_gated_we = alert_en_shadowed_62_we & alert_regwen_62_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_62_re), + .we (alert_en_shadowed_62_gated_we), + .wd (alert_en_shadowed_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[62].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_62_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_62_update_err), + .err_storage (alert_en_shadowed_62_storage_err) + ); + + + // Subregister 63 of Multireg alert_en_shadowed + // R[alert_en_shadowed_63]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_63_gated_we; + assign alert_en_shadowed_63_gated_we = alert_en_shadowed_63_we & alert_regwen_63_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_63_re), + .we (alert_en_shadowed_63_gated_we), + .wd (alert_en_shadowed_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[63].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_63_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_63_update_err), + .err_storage (alert_en_shadowed_63_storage_err) + ); + + + // Subregister 64 of Multireg alert_en_shadowed + // R[alert_en_shadowed_64]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_64_gated_we; + assign alert_en_shadowed_64_gated_we = alert_en_shadowed_64_we & alert_regwen_64_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_64_re), + .we (alert_en_shadowed_64_gated_we), + .wd (alert_en_shadowed_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[64].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_64_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_64_update_err), + .err_storage (alert_en_shadowed_64_storage_err) + ); + + + // Subregister 65 of Multireg alert_en_shadowed + // R[alert_en_shadowed_65]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_65_gated_we; + assign alert_en_shadowed_65_gated_we = alert_en_shadowed_65_we & alert_regwen_65_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_65_re), + .we (alert_en_shadowed_65_gated_we), + .wd (alert_en_shadowed_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[65].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_65_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_65_update_err), + .err_storage (alert_en_shadowed_65_storage_err) + ); + + + // Subregister 66 of Multireg alert_en_shadowed + // R[alert_en_shadowed_66]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_66_gated_we; + assign alert_en_shadowed_66_gated_we = alert_en_shadowed_66_we & alert_regwen_66_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_66_re), + .we (alert_en_shadowed_66_gated_we), + .wd (alert_en_shadowed_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[66].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_66_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_66_update_err), + .err_storage (alert_en_shadowed_66_storage_err) + ); + + + // Subregister 67 of Multireg alert_en_shadowed + // R[alert_en_shadowed_67]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_67_gated_we; + assign alert_en_shadowed_67_gated_we = alert_en_shadowed_67_we & alert_regwen_67_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_67_re), + .we (alert_en_shadowed_67_gated_we), + .wd (alert_en_shadowed_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[67].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_67_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_67_update_err), + .err_storage (alert_en_shadowed_67_storage_err) + ); + + + // Subregister 68 of Multireg alert_en_shadowed + // R[alert_en_shadowed_68]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_68_gated_we; + assign alert_en_shadowed_68_gated_we = alert_en_shadowed_68_we & alert_regwen_68_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_68_re), + .we (alert_en_shadowed_68_gated_we), + .wd (alert_en_shadowed_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[68].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_68_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_68_update_err), + .err_storage (alert_en_shadowed_68_storage_err) + ); + + + // Subregister 69 of Multireg alert_en_shadowed + // R[alert_en_shadowed_69]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_69_gated_we; + assign alert_en_shadowed_69_gated_we = alert_en_shadowed_69_we & alert_regwen_69_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_69_re), + .we (alert_en_shadowed_69_gated_we), + .wd (alert_en_shadowed_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[69].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_69_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_69_update_err), + .err_storage (alert_en_shadowed_69_storage_err) + ); + + + // Subregister 70 of Multireg alert_en_shadowed + // R[alert_en_shadowed_70]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_70_gated_we; + assign alert_en_shadowed_70_gated_we = alert_en_shadowed_70_we & alert_regwen_70_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_70_re), + .we (alert_en_shadowed_70_gated_we), + .wd (alert_en_shadowed_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[70].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_70_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_70_update_err), + .err_storage (alert_en_shadowed_70_storage_err) + ); + + + // Subregister 71 of Multireg alert_en_shadowed + // R[alert_en_shadowed_71]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_71_gated_we; + assign alert_en_shadowed_71_gated_we = alert_en_shadowed_71_we & alert_regwen_71_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_71_re), + .we (alert_en_shadowed_71_gated_we), + .wd (alert_en_shadowed_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[71].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_71_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_71_update_err), + .err_storage (alert_en_shadowed_71_storage_err) + ); + + + // Subregister 72 of Multireg alert_en_shadowed + // R[alert_en_shadowed_72]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_72_gated_we; + assign alert_en_shadowed_72_gated_we = alert_en_shadowed_72_we & alert_regwen_72_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_72_re), + .we (alert_en_shadowed_72_gated_we), + .wd (alert_en_shadowed_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[72].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_72_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_72_update_err), + .err_storage (alert_en_shadowed_72_storage_err) + ); + + + // Subregister 73 of Multireg alert_en_shadowed + // R[alert_en_shadowed_73]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_73_gated_we; + assign alert_en_shadowed_73_gated_we = alert_en_shadowed_73_we & alert_regwen_73_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_73_re), + .we (alert_en_shadowed_73_gated_we), + .wd (alert_en_shadowed_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[73].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_73_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_73_update_err), + .err_storage (alert_en_shadowed_73_storage_err) + ); + + + // Subregister 74 of Multireg alert_en_shadowed + // R[alert_en_shadowed_74]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_74_gated_we; + assign alert_en_shadowed_74_gated_we = alert_en_shadowed_74_we & alert_regwen_74_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_74_re), + .we (alert_en_shadowed_74_gated_we), + .wd (alert_en_shadowed_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[74].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_74_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_74_update_err), + .err_storage (alert_en_shadowed_74_storage_err) + ); + + + // Subregister 75 of Multireg alert_en_shadowed + // R[alert_en_shadowed_75]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_75_gated_we; + assign alert_en_shadowed_75_gated_we = alert_en_shadowed_75_we & alert_regwen_75_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_75_re), + .we (alert_en_shadowed_75_gated_we), + .wd (alert_en_shadowed_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[75].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_75_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_75_update_err), + .err_storage (alert_en_shadowed_75_storage_err) + ); + + + // Subregister 76 of Multireg alert_en_shadowed + // R[alert_en_shadowed_76]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_76_gated_we; + assign alert_en_shadowed_76_gated_we = alert_en_shadowed_76_we & alert_regwen_76_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_76_re), + .we (alert_en_shadowed_76_gated_we), + .wd (alert_en_shadowed_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[76].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_76_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_76_update_err), + .err_storage (alert_en_shadowed_76_storage_err) + ); + + + // Subregister 77 of Multireg alert_en_shadowed + // R[alert_en_shadowed_77]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_77_gated_we; + assign alert_en_shadowed_77_gated_we = alert_en_shadowed_77_we & alert_regwen_77_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_77_re), + .we (alert_en_shadowed_77_gated_we), + .wd (alert_en_shadowed_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[77].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_77_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_77_update_err), + .err_storage (alert_en_shadowed_77_storage_err) + ); + + + // Subregister 78 of Multireg alert_en_shadowed + // R[alert_en_shadowed_78]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_78_gated_we; + assign alert_en_shadowed_78_gated_we = alert_en_shadowed_78_we & alert_regwen_78_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_78_re), + .we (alert_en_shadowed_78_gated_we), + .wd (alert_en_shadowed_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[78].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_78_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_78_update_err), + .err_storage (alert_en_shadowed_78_storage_err) + ); + + + // Subregister 79 of Multireg alert_en_shadowed + // R[alert_en_shadowed_79]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_79_gated_we; + assign alert_en_shadowed_79_gated_we = alert_en_shadowed_79_we & alert_regwen_79_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_79_re), + .we (alert_en_shadowed_79_gated_we), + .wd (alert_en_shadowed_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[79].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_79_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_79_update_err), + .err_storage (alert_en_shadowed_79_storage_err) + ); + + + // Subregister 80 of Multireg alert_en_shadowed + // R[alert_en_shadowed_80]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_80_gated_we; + assign alert_en_shadowed_80_gated_we = alert_en_shadowed_80_we & alert_regwen_80_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_80_re), + .we (alert_en_shadowed_80_gated_we), + .wd (alert_en_shadowed_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[80].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_80_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_80_update_err), + .err_storage (alert_en_shadowed_80_storage_err) + ); + + + // Subregister 81 of Multireg alert_en_shadowed + // R[alert_en_shadowed_81]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_81_gated_we; + assign alert_en_shadowed_81_gated_we = alert_en_shadowed_81_we & alert_regwen_81_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_81_re), + .we (alert_en_shadowed_81_gated_we), + .wd (alert_en_shadowed_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[81].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_81_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_81_update_err), + .err_storage (alert_en_shadowed_81_storage_err) + ); + + + // Subregister 82 of Multireg alert_en_shadowed + // R[alert_en_shadowed_82]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_82_gated_we; + assign alert_en_shadowed_82_gated_we = alert_en_shadowed_82_we & alert_regwen_82_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_82_re), + .we (alert_en_shadowed_82_gated_we), + .wd (alert_en_shadowed_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[82].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_82_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_82_update_err), + .err_storage (alert_en_shadowed_82_storage_err) + ); + + + // Subregister 83 of Multireg alert_en_shadowed + // R[alert_en_shadowed_83]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_83_gated_we; + assign alert_en_shadowed_83_gated_we = alert_en_shadowed_83_we & alert_regwen_83_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_83_re), + .we (alert_en_shadowed_83_gated_we), + .wd (alert_en_shadowed_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[83].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_83_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_83_update_err), + .err_storage (alert_en_shadowed_83_storage_err) + ); + + + // Subregister 84 of Multireg alert_en_shadowed + // R[alert_en_shadowed_84]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_84_gated_we; + assign alert_en_shadowed_84_gated_we = alert_en_shadowed_84_we & alert_regwen_84_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_84_re), + .we (alert_en_shadowed_84_gated_we), + .wd (alert_en_shadowed_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[84].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_84_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_84_update_err), + .err_storage (alert_en_shadowed_84_storage_err) + ); + + + // Subregister 85 of Multireg alert_en_shadowed + // R[alert_en_shadowed_85]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_85_gated_we; + assign alert_en_shadowed_85_gated_we = alert_en_shadowed_85_we & alert_regwen_85_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_85_re), + .we (alert_en_shadowed_85_gated_we), + .wd (alert_en_shadowed_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[85].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_85_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_85_update_err), + .err_storage (alert_en_shadowed_85_storage_err) + ); + + + // Subregister 86 of Multireg alert_en_shadowed + // R[alert_en_shadowed_86]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_86_gated_we; + assign alert_en_shadowed_86_gated_we = alert_en_shadowed_86_we & alert_regwen_86_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_86_re), + .we (alert_en_shadowed_86_gated_we), + .wd (alert_en_shadowed_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[86].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_86_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_86_update_err), + .err_storage (alert_en_shadowed_86_storage_err) + ); + + + // Subregister 87 of Multireg alert_en_shadowed + // R[alert_en_shadowed_87]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_87_gated_we; + assign alert_en_shadowed_87_gated_we = alert_en_shadowed_87_we & alert_regwen_87_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_87_re), + .we (alert_en_shadowed_87_gated_we), + .wd (alert_en_shadowed_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[87].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_87_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_87_update_err), + .err_storage (alert_en_shadowed_87_storage_err) + ); + + + // Subregister 88 of Multireg alert_en_shadowed + // R[alert_en_shadowed_88]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_88_gated_we; + assign alert_en_shadowed_88_gated_we = alert_en_shadowed_88_we & alert_regwen_88_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_88_re), + .we (alert_en_shadowed_88_gated_we), + .wd (alert_en_shadowed_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[88].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_88_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_88_update_err), + .err_storage (alert_en_shadowed_88_storage_err) + ); + + + // Subregister 89 of Multireg alert_en_shadowed + // R[alert_en_shadowed_89]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_89_gated_we; + assign alert_en_shadowed_89_gated_we = alert_en_shadowed_89_we & alert_regwen_89_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_89_re), + .we (alert_en_shadowed_89_gated_we), + .wd (alert_en_shadowed_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[89].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_89_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_89_update_err), + .err_storage (alert_en_shadowed_89_storage_err) + ); + + + // Subregister 90 of Multireg alert_en_shadowed + // R[alert_en_shadowed_90]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_90_gated_we; + assign alert_en_shadowed_90_gated_we = alert_en_shadowed_90_we & alert_regwen_90_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_90_re), + .we (alert_en_shadowed_90_gated_we), + .wd (alert_en_shadowed_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[90].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_90_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_90_update_err), + .err_storage (alert_en_shadowed_90_storage_err) + ); + + + // Subregister 91 of Multireg alert_en_shadowed + // R[alert_en_shadowed_91]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_91_gated_we; + assign alert_en_shadowed_91_gated_we = alert_en_shadowed_91_we & alert_regwen_91_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_91_re), + .we (alert_en_shadowed_91_gated_we), + .wd (alert_en_shadowed_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[91].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_91_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_91_update_err), + .err_storage (alert_en_shadowed_91_storage_err) + ); + + + // Subregister 92 of Multireg alert_en_shadowed + // R[alert_en_shadowed_92]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_92_gated_we; + assign alert_en_shadowed_92_gated_we = alert_en_shadowed_92_we & alert_regwen_92_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_92_re), + .we (alert_en_shadowed_92_gated_we), + .wd (alert_en_shadowed_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[92].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_92_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_92_update_err), + .err_storage (alert_en_shadowed_92_storage_err) + ); + + + // Subregister 93 of Multireg alert_en_shadowed + // R[alert_en_shadowed_93]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_93_gated_we; + assign alert_en_shadowed_93_gated_we = alert_en_shadowed_93_we & alert_regwen_93_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_93_re), + .we (alert_en_shadowed_93_gated_we), + .wd (alert_en_shadowed_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[93].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_93_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_93_update_err), + .err_storage (alert_en_shadowed_93_storage_err) + ); + + + // Subregister 94 of Multireg alert_en_shadowed + // R[alert_en_shadowed_94]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_94_gated_we; + assign alert_en_shadowed_94_gated_we = alert_en_shadowed_94_we & alert_regwen_94_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_94_re), + .we (alert_en_shadowed_94_gated_we), + .wd (alert_en_shadowed_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[94].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_94_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_94_update_err), + .err_storage (alert_en_shadowed_94_storage_err) + ); + + + // Subregister 95 of Multireg alert_en_shadowed + // R[alert_en_shadowed_95]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_95_gated_we; + assign alert_en_shadowed_95_gated_we = alert_en_shadowed_95_we & alert_regwen_95_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_95_re), + .we (alert_en_shadowed_95_gated_we), + .wd (alert_en_shadowed_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[95].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_95_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_95_update_err), + .err_storage (alert_en_shadowed_95_storage_err) + ); + + + // Subregister 96 of Multireg alert_en_shadowed + // R[alert_en_shadowed_96]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_96_gated_we; + assign alert_en_shadowed_96_gated_we = alert_en_shadowed_96_we & alert_regwen_96_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_96_re), + .we (alert_en_shadowed_96_gated_we), + .wd (alert_en_shadowed_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[96].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_96_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_96_update_err), + .err_storage (alert_en_shadowed_96_storage_err) + ); + + + // Subregister 97 of Multireg alert_en_shadowed + // R[alert_en_shadowed_97]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_97_gated_we; + assign alert_en_shadowed_97_gated_we = alert_en_shadowed_97_we & alert_regwen_97_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_97_re), + .we (alert_en_shadowed_97_gated_we), + .wd (alert_en_shadowed_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[97].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_97_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_97_update_err), + .err_storage (alert_en_shadowed_97_storage_err) + ); + + + // Subregister 98 of Multireg alert_en_shadowed + // R[alert_en_shadowed_98]: V(False) + // Create REGWEN-gated WE signal + logic alert_en_shadowed_98_gated_we; + assign alert_en_shadowed_98_gated_we = alert_en_shadowed_98_we & alert_regwen_98_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_en_shadowed_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_en_shadowed_98_re), + .we (alert_en_shadowed_98_gated_we), + .wd (alert_en_shadowed_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_en_shadowed[98].q), + .ds (), + + // to register interface (read) + .qs (alert_en_shadowed_98_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_en_shadowed_98_update_err), + .err_storage (alert_en_shadowed_98_storage_err) + ); + + + // Subregister 0 of Multireg alert_class_shadowed + // R[alert_class_shadowed_0]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_0_gated_we; + assign alert_class_shadowed_0_gated_we = alert_class_shadowed_0_we & alert_regwen_0_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_0_re), + .we (alert_class_shadowed_0_gated_we), + .wd (alert_class_shadowed_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[0].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_0_update_err), + .err_storage (alert_class_shadowed_0_storage_err) + ); + + + // Subregister 1 of Multireg alert_class_shadowed + // R[alert_class_shadowed_1]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_1_gated_we; + assign alert_class_shadowed_1_gated_we = alert_class_shadowed_1_we & alert_regwen_1_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_1_re), + .we (alert_class_shadowed_1_gated_we), + .wd (alert_class_shadowed_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[1].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_1_update_err), + .err_storage (alert_class_shadowed_1_storage_err) + ); + + + // Subregister 2 of Multireg alert_class_shadowed + // R[alert_class_shadowed_2]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_2_gated_we; + assign alert_class_shadowed_2_gated_we = alert_class_shadowed_2_we & alert_regwen_2_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_2_re), + .we (alert_class_shadowed_2_gated_we), + .wd (alert_class_shadowed_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[2].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_2_update_err), + .err_storage (alert_class_shadowed_2_storage_err) + ); + + + // Subregister 3 of Multireg alert_class_shadowed + // R[alert_class_shadowed_3]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_3_gated_we; + assign alert_class_shadowed_3_gated_we = alert_class_shadowed_3_we & alert_regwen_3_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_3_re), + .we (alert_class_shadowed_3_gated_we), + .wd (alert_class_shadowed_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[3].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_3_update_err), + .err_storage (alert_class_shadowed_3_storage_err) + ); + + + // Subregister 4 of Multireg alert_class_shadowed + // R[alert_class_shadowed_4]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_4_gated_we; + assign alert_class_shadowed_4_gated_we = alert_class_shadowed_4_we & alert_regwen_4_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_4_re), + .we (alert_class_shadowed_4_gated_we), + .wd (alert_class_shadowed_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[4].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_4_update_err), + .err_storage (alert_class_shadowed_4_storage_err) + ); + + + // Subregister 5 of Multireg alert_class_shadowed + // R[alert_class_shadowed_5]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_5_gated_we; + assign alert_class_shadowed_5_gated_we = alert_class_shadowed_5_we & alert_regwen_5_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_5_re), + .we (alert_class_shadowed_5_gated_we), + .wd (alert_class_shadowed_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[5].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_5_update_err), + .err_storage (alert_class_shadowed_5_storage_err) + ); + + + // Subregister 6 of Multireg alert_class_shadowed + // R[alert_class_shadowed_6]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_6_gated_we; + assign alert_class_shadowed_6_gated_we = alert_class_shadowed_6_we & alert_regwen_6_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_6_re), + .we (alert_class_shadowed_6_gated_we), + .wd (alert_class_shadowed_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[6].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_6_update_err), + .err_storage (alert_class_shadowed_6_storage_err) + ); + + + // Subregister 7 of Multireg alert_class_shadowed + // R[alert_class_shadowed_7]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_7_gated_we; + assign alert_class_shadowed_7_gated_we = alert_class_shadowed_7_we & alert_regwen_7_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_7_re), + .we (alert_class_shadowed_7_gated_we), + .wd (alert_class_shadowed_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[7].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_7_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_7_update_err), + .err_storage (alert_class_shadowed_7_storage_err) + ); + + + // Subregister 8 of Multireg alert_class_shadowed + // R[alert_class_shadowed_8]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_8_gated_we; + assign alert_class_shadowed_8_gated_we = alert_class_shadowed_8_we & alert_regwen_8_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_8_re), + .we (alert_class_shadowed_8_gated_we), + .wd (alert_class_shadowed_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[8].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_8_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_8_update_err), + .err_storage (alert_class_shadowed_8_storage_err) + ); + + + // Subregister 9 of Multireg alert_class_shadowed + // R[alert_class_shadowed_9]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_9_gated_we; + assign alert_class_shadowed_9_gated_we = alert_class_shadowed_9_we & alert_regwen_9_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_9_re), + .we (alert_class_shadowed_9_gated_we), + .wd (alert_class_shadowed_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[9].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_9_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_9_update_err), + .err_storage (alert_class_shadowed_9_storage_err) + ); + + + // Subregister 10 of Multireg alert_class_shadowed + // R[alert_class_shadowed_10]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_10_gated_we; + assign alert_class_shadowed_10_gated_we = alert_class_shadowed_10_we & alert_regwen_10_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_10_re), + .we (alert_class_shadowed_10_gated_we), + .wd (alert_class_shadowed_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[10].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_10_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_10_update_err), + .err_storage (alert_class_shadowed_10_storage_err) + ); + + + // Subregister 11 of Multireg alert_class_shadowed + // R[alert_class_shadowed_11]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_11_gated_we; + assign alert_class_shadowed_11_gated_we = alert_class_shadowed_11_we & alert_regwen_11_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_11_re), + .we (alert_class_shadowed_11_gated_we), + .wd (alert_class_shadowed_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[11].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_11_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_11_update_err), + .err_storage (alert_class_shadowed_11_storage_err) + ); + + + // Subregister 12 of Multireg alert_class_shadowed + // R[alert_class_shadowed_12]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_12_gated_we; + assign alert_class_shadowed_12_gated_we = alert_class_shadowed_12_we & alert_regwen_12_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_12_re), + .we (alert_class_shadowed_12_gated_we), + .wd (alert_class_shadowed_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[12].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_12_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_12_update_err), + .err_storage (alert_class_shadowed_12_storage_err) + ); + + + // Subregister 13 of Multireg alert_class_shadowed + // R[alert_class_shadowed_13]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_13_gated_we; + assign alert_class_shadowed_13_gated_we = alert_class_shadowed_13_we & alert_regwen_13_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_13_re), + .we (alert_class_shadowed_13_gated_we), + .wd (alert_class_shadowed_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[13].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_13_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_13_update_err), + .err_storage (alert_class_shadowed_13_storage_err) + ); + + + // Subregister 14 of Multireg alert_class_shadowed + // R[alert_class_shadowed_14]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_14_gated_we; + assign alert_class_shadowed_14_gated_we = alert_class_shadowed_14_we & alert_regwen_14_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_14_re), + .we (alert_class_shadowed_14_gated_we), + .wd (alert_class_shadowed_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[14].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_14_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_14_update_err), + .err_storage (alert_class_shadowed_14_storage_err) + ); + + + // Subregister 15 of Multireg alert_class_shadowed + // R[alert_class_shadowed_15]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_15_gated_we; + assign alert_class_shadowed_15_gated_we = alert_class_shadowed_15_we & alert_regwen_15_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_15_re), + .we (alert_class_shadowed_15_gated_we), + .wd (alert_class_shadowed_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[15].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_15_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_15_update_err), + .err_storage (alert_class_shadowed_15_storage_err) + ); + + + // Subregister 16 of Multireg alert_class_shadowed + // R[alert_class_shadowed_16]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_16_gated_we; + assign alert_class_shadowed_16_gated_we = alert_class_shadowed_16_we & alert_regwen_16_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_16_re), + .we (alert_class_shadowed_16_gated_we), + .wd (alert_class_shadowed_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[16].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_16_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_16_update_err), + .err_storage (alert_class_shadowed_16_storage_err) + ); + + + // Subregister 17 of Multireg alert_class_shadowed + // R[alert_class_shadowed_17]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_17_gated_we; + assign alert_class_shadowed_17_gated_we = alert_class_shadowed_17_we & alert_regwen_17_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_17_re), + .we (alert_class_shadowed_17_gated_we), + .wd (alert_class_shadowed_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[17].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_17_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_17_update_err), + .err_storage (alert_class_shadowed_17_storage_err) + ); + + + // Subregister 18 of Multireg alert_class_shadowed + // R[alert_class_shadowed_18]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_18_gated_we; + assign alert_class_shadowed_18_gated_we = alert_class_shadowed_18_we & alert_regwen_18_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_18_re), + .we (alert_class_shadowed_18_gated_we), + .wd (alert_class_shadowed_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[18].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_18_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_18_update_err), + .err_storage (alert_class_shadowed_18_storage_err) + ); + + + // Subregister 19 of Multireg alert_class_shadowed + // R[alert_class_shadowed_19]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_19_gated_we; + assign alert_class_shadowed_19_gated_we = alert_class_shadowed_19_we & alert_regwen_19_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_19_re), + .we (alert_class_shadowed_19_gated_we), + .wd (alert_class_shadowed_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[19].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_19_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_19_update_err), + .err_storage (alert_class_shadowed_19_storage_err) + ); + + + // Subregister 20 of Multireg alert_class_shadowed + // R[alert_class_shadowed_20]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_20_gated_we; + assign alert_class_shadowed_20_gated_we = alert_class_shadowed_20_we & alert_regwen_20_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_20_re), + .we (alert_class_shadowed_20_gated_we), + .wd (alert_class_shadowed_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[20].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_20_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_20_update_err), + .err_storage (alert_class_shadowed_20_storage_err) + ); + + + // Subregister 21 of Multireg alert_class_shadowed + // R[alert_class_shadowed_21]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_21_gated_we; + assign alert_class_shadowed_21_gated_we = alert_class_shadowed_21_we & alert_regwen_21_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_21_re), + .we (alert_class_shadowed_21_gated_we), + .wd (alert_class_shadowed_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[21].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_21_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_21_update_err), + .err_storage (alert_class_shadowed_21_storage_err) + ); + + + // Subregister 22 of Multireg alert_class_shadowed + // R[alert_class_shadowed_22]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_22_gated_we; + assign alert_class_shadowed_22_gated_we = alert_class_shadowed_22_we & alert_regwen_22_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_22_re), + .we (alert_class_shadowed_22_gated_we), + .wd (alert_class_shadowed_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[22].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_22_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_22_update_err), + .err_storage (alert_class_shadowed_22_storage_err) + ); + + + // Subregister 23 of Multireg alert_class_shadowed + // R[alert_class_shadowed_23]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_23_gated_we; + assign alert_class_shadowed_23_gated_we = alert_class_shadowed_23_we & alert_regwen_23_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_23_re), + .we (alert_class_shadowed_23_gated_we), + .wd (alert_class_shadowed_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[23].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_23_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_23_update_err), + .err_storage (alert_class_shadowed_23_storage_err) + ); + + + // Subregister 24 of Multireg alert_class_shadowed + // R[alert_class_shadowed_24]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_24_gated_we; + assign alert_class_shadowed_24_gated_we = alert_class_shadowed_24_we & alert_regwen_24_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_24_re), + .we (alert_class_shadowed_24_gated_we), + .wd (alert_class_shadowed_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[24].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_24_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_24_update_err), + .err_storage (alert_class_shadowed_24_storage_err) + ); + + + // Subregister 25 of Multireg alert_class_shadowed + // R[alert_class_shadowed_25]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_25_gated_we; + assign alert_class_shadowed_25_gated_we = alert_class_shadowed_25_we & alert_regwen_25_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_25_re), + .we (alert_class_shadowed_25_gated_we), + .wd (alert_class_shadowed_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[25].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_25_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_25_update_err), + .err_storage (alert_class_shadowed_25_storage_err) + ); + + + // Subregister 26 of Multireg alert_class_shadowed + // R[alert_class_shadowed_26]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_26_gated_we; + assign alert_class_shadowed_26_gated_we = alert_class_shadowed_26_we & alert_regwen_26_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_26_re), + .we (alert_class_shadowed_26_gated_we), + .wd (alert_class_shadowed_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[26].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_26_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_26_update_err), + .err_storage (alert_class_shadowed_26_storage_err) + ); + + + // Subregister 27 of Multireg alert_class_shadowed + // R[alert_class_shadowed_27]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_27_gated_we; + assign alert_class_shadowed_27_gated_we = alert_class_shadowed_27_we & alert_regwen_27_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_27_re), + .we (alert_class_shadowed_27_gated_we), + .wd (alert_class_shadowed_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[27].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_27_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_27_update_err), + .err_storage (alert_class_shadowed_27_storage_err) + ); + + + // Subregister 28 of Multireg alert_class_shadowed + // R[alert_class_shadowed_28]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_28_gated_we; + assign alert_class_shadowed_28_gated_we = alert_class_shadowed_28_we & alert_regwen_28_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_28_re), + .we (alert_class_shadowed_28_gated_we), + .wd (alert_class_shadowed_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[28].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_28_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_28_update_err), + .err_storage (alert_class_shadowed_28_storage_err) + ); + + + // Subregister 29 of Multireg alert_class_shadowed + // R[alert_class_shadowed_29]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_29_gated_we; + assign alert_class_shadowed_29_gated_we = alert_class_shadowed_29_we & alert_regwen_29_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_29_re), + .we (alert_class_shadowed_29_gated_we), + .wd (alert_class_shadowed_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[29].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_29_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_29_update_err), + .err_storage (alert_class_shadowed_29_storage_err) + ); + + + // Subregister 30 of Multireg alert_class_shadowed + // R[alert_class_shadowed_30]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_30_gated_we; + assign alert_class_shadowed_30_gated_we = alert_class_shadowed_30_we & alert_regwen_30_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_30_re), + .we (alert_class_shadowed_30_gated_we), + .wd (alert_class_shadowed_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[30].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_30_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_30_update_err), + .err_storage (alert_class_shadowed_30_storage_err) + ); + + + // Subregister 31 of Multireg alert_class_shadowed + // R[alert_class_shadowed_31]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_31_gated_we; + assign alert_class_shadowed_31_gated_we = alert_class_shadowed_31_we & alert_regwen_31_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_31_re), + .we (alert_class_shadowed_31_gated_we), + .wd (alert_class_shadowed_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[31].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_31_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_31_update_err), + .err_storage (alert_class_shadowed_31_storage_err) + ); + + + // Subregister 32 of Multireg alert_class_shadowed + // R[alert_class_shadowed_32]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_32_gated_we; + assign alert_class_shadowed_32_gated_we = alert_class_shadowed_32_we & alert_regwen_32_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_32_re), + .we (alert_class_shadowed_32_gated_we), + .wd (alert_class_shadowed_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[32].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_32_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_32_update_err), + .err_storage (alert_class_shadowed_32_storage_err) + ); + + + // Subregister 33 of Multireg alert_class_shadowed + // R[alert_class_shadowed_33]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_33_gated_we; + assign alert_class_shadowed_33_gated_we = alert_class_shadowed_33_we & alert_regwen_33_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_33_re), + .we (alert_class_shadowed_33_gated_we), + .wd (alert_class_shadowed_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[33].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_33_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_33_update_err), + .err_storage (alert_class_shadowed_33_storage_err) + ); + + + // Subregister 34 of Multireg alert_class_shadowed + // R[alert_class_shadowed_34]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_34_gated_we; + assign alert_class_shadowed_34_gated_we = alert_class_shadowed_34_we & alert_regwen_34_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_34_re), + .we (alert_class_shadowed_34_gated_we), + .wd (alert_class_shadowed_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[34].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_34_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_34_update_err), + .err_storage (alert_class_shadowed_34_storage_err) + ); + + + // Subregister 35 of Multireg alert_class_shadowed + // R[alert_class_shadowed_35]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_35_gated_we; + assign alert_class_shadowed_35_gated_we = alert_class_shadowed_35_we & alert_regwen_35_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_35_re), + .we (alert_class_shadowed_35_gated_we), + .wd (alert_class_shadowed_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[35].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_35_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_35_update_err), + .err_storage (alert_class_shadowed_35_storage_err) + ); + + + // Subregister 36 of Multireg alert_class_shadowed + // R[alert_class_shadowed_36]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_36_gated_we; + assign alert_class_shadowed_36_gated_we = alert_class_shadowed_36_we & alert_regwen_36_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_36_re), + .we (alert_class_shadowed_36_gated_we), + .wd (alert_class_shadowed_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[36].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_36_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_36_update_err), + .err_storage (alert_class_shadowed_36_storage_err) + ); + + + // Subregister 37 of Multireg alert_class_shadowed + // R[alert_class_shadowed_37]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_37_gated_we; + assign alert_class_shadowed_37_gated_we = alert_class_shadowed_37_we & alert_regwen_37_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_37_re), + .we (alert_class_shadowed_37_gated_we), + .wd (alert_class_shadowed_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[37].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_37_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_37_update_err), + .err_storage (alert_class_shadowed_37_storage_err) + ); + + + // Subregister 38 of Multireg alert_class_shadowed + // R[alert_class_shadowed_38]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_38_gated_we; + assign alert_class_shadowed_38_gated_we = alert_class_shadowed_38_we & alert_regwen_38_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_38_re), + .we (alert_class_shadowed_38_gated_we), + .wd (alert_class_shadowed_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[38].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_38_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_38_update_err), + .err_storage (alert_class_shadowed_38_storage_err) + ); + + + // Subregister 39 of Multireg alert_class_shadowed + // R[alert_class_shadowed_39]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_39_gated_we; + assign alert_class_shadowed_39_gated_we = alert_class_shadowed_39_we & alert_regwen_39_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_39_re), + .we (alert_class_shadowed_39_gated_we), + .wd (alert_class_shadowed_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[39].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_39_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_39_update_err), + .err_storage (alert_class_shadowed_39_storage_err) + ); + + + // Subregister 40 of Multireg alert_class_shadowed + // R[alert_class_shadowed_40]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_40_gated_we; + assign alert_class_shadowed_40_gated_we = alert_class_shadowed_40_we & alert_regwen_40_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_40_re), + .we (alert_class_shadowed_40_gated_we), + .wd (alert_class_shadowed_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[40].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_40_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_40_update_err), + .err_storage (alert_class_shadowed_40_storage_err) + ); + + + // Subregister 41 of Multireg alert_class_shadowed + // R[alert_class_shadowed_41]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_41_gated_we; + assign alert_class_shadowed_41_gated_we = alert_class_shadowed_41_we & alert_regwen_41_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_41_re), + .we (alert_class_shadowed_41_gated_we), + .wd (alert_class_shadowed_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[41].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_41_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_41_update_err), + .err_storage (alert_class_shadowed_41_storage_err) + ); + + + // Subregister 42 of Multireg alert_class_shadowed + // R[alert_class_shadowed_42]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_42_gated_we; + assign alert_class_shadowed_42_gated_we = alert_class_shadowed_42_we & alert_regwen_42_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_42_re), + .we (alert_class_shadowed_42_gated_we), + .wd (alert_class_shadowed_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[42].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_42_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_42_update_err), + .err_storage (alert_class_shadowed_42_storage_err) + ); + + + // Subregister 43 of Multireg alert_class_shadowed + // R[alert_class_shadowed_43]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_43_gated_we; + assign alert_class_shadowed_43_gated_we = alert_class_shadowed_43_we & alert_regwen_43_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_43_re), + .we (alert_class_shadowed_43_gated_we), + .wd (alert_class_shadowed_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[43].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_43_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_43_update_err), + .err_storage (alert_class_shadowed_43_storage_err) + ); + + + // Subregister 44 of Multireg alert_class_shadowed + // R[alert_class_shadowed_44]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_44_gated_we; + assign alert_class_shadowed_44_gated_we = alert_class_shadowed_44_we & alert_regwen_44_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_44_re), + .we (alert_class_shadowed_44_gated_we), + .wd (alert_class_shadowed_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[44].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_44_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_44_update_err), + .err_storage (alert_class_shadowed_44_storage_err) + ); + + + // Subregister 45 of Multireg alert_class_shadowed + // R[alert_class_shadowed_45]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_45_gated_we; + assign alert_class_shadowed_45_gated_we = alert_class_shadowed_45_we & alert_regwen_45_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_45_re), + .we (alert_class_shadowed_45_gated_we), + .wd (alert_class_shadowed_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[45].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_45_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_45_update_err), + .err_storage (alert_class_shadowed_45_storage_err) + ); + + + // Subregister 46 of Multireg alert_class_shadowed + // R[alert_class_shadowed_46]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_46_gated_we; + assign alert_class_shadowed_46_gated_we = alert_class_shadowed_46_we & alert_regwen_46_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_46_re), + .we (alert_class_shadowed_46_gated_we), + .wd (alert_class_shadowed_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[46].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_46_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_46_update_err), + .err_storage (alert_class_shadowed_46_storage_err) + ); + + + // Subregister 47 of Multireg alert_class_shadowed + // R[alert_class_shadowed_47]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_47_gated_we; + assign alert_class_shadowed_47_gated_we = alert_class_shadowed_47_we & alert_regwen_47_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_47_re), + .we (alert_class_shadowed_47_gated_we), + .wd (alert_class_shadowed_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[47].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_47_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_47_update_err), + .err_storage (alert_class_shadowed_47_storage_err) + ); + + + // Subregister 48 of Multireg alert_class_shadowed + // R[alert_class_shadowed_48]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_48_gated_we; + assign alert_class_shadowed_48_gated_we = alert_class_shadowed_48_we & alert_regwen_48_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_48_re), + .we (alert_class_shadowed_48_gated_we), + .wd (alert_class_shadowed_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[48].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_48_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_48_update_err), + .err_storage (alert_class_shadowed_48_storage_err) + ); + + + // Subregister 49 of Multireg alert_class_shadowed + // R[alert_class_shadowed_49]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_49_gated_we; + assign alert_class_shadowed_49_gated_we = alert_class_shadowed_49_we & alert_regwen_49_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_49_re), + .we (alert_class_shadowed_49_gated_we), + .wd (alert_class_shadowed_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[49].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_49_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_49_update_err), + .err_storage (alert_class_shadowed_49_storage_err) + ); + + + // Subregister 50 of Multireg alert_class_shadowed + // R[alert_class_shadowed_50]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_50_gated_we; + assign alert_class_shadowed_50_gated_we = alert_class_shadowed_50_we & alert_regwen_50_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_50_re), + .we (alert_class_shadowed_50_gated_we), + .wd (alert_class_shadowed_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[50].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_50_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_50_update_err), + .err_storage (alert_class_shadowed_50_storage_err) + ); + + + // Subregister 51 of Multireg alert_class_shadowed + // R[alert_class_shadowed_51]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_51_gated_we; + assign alert_class_shadowed_51_gated_we = alert_class_shadowed_51_we & alert_regwen_51_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_51_re), + .we (alert_class_shadowed_51_gated_we), + .wd (alert_class_shadowed_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[51].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_51_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_51_update_err), + .err_storage (alert_class_shadowed_51_storage_err) + ); + + + // Subregister 52 of Multireg alert_class_shadowed + // R[alert_class_shadowed_52]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_52_gated_we; + assign alert_class_shadowed_52_gated_we = alert_class_shadowed_52_we & alert_regwen_52_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_52_re), + .we (alert_class_shadowed_52_gated_we), + .wd (alert_class_shadowed_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[52].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_52_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_52_update_err), + .err_storage (alert_class_shadowed_52_storage_err) + ); + + + // Subregister 53 of Multireg alert_class_shadowed + // R[alert_class_shadowed_53]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_53_gated_we; + assign alert_class_shadowed_53_gated_we = alert_class_shadowed_53_we & alert_regwen_53_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_53_re), + .we (alert_class_shadowed_53_gated_we), + .wd (alert_class_shadowed_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[53].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_53_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_53_update_err), + .err_storage (alert_class_shadowed_53_storage_err) + ); + + + // Subregister 54 of Multireg alert_class_shadowed + // R[alert_class_shadowed_54]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_54_gated_we; + assign alert_class_shadowed_54_gated_we = alert_class_shadowed_54_we & alert_regwen_54_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_54_re), + .we (alert_class_shadowed_54_gated_we), + .wd (alert_class_shadowed_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[54].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_54_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_54_update_err), + .err_storage (alert_class_shadowed_54_storage_err) + ); + + + // Subregister 55 of Multireg alert_class_shadowed + // R[alert_class_shadowed_55]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_55_gated_we; + assign alert_class_shadowed_55_gated_we = alert_class_shadowed_55_we & alert_regwen_55_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_55_re), + .we (alert_class_shadowed_55_gated_we), + .wd (alert_class_shadowed_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[55].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_55_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_55_update_err), + .err_storage (alert_class_shadowed_55_storage_err) + ); + + + // Subregister 56 of Multireg alert_class_shadowed + // R[alert_class_shadowed_56]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_56_gated_we; + assign alert_class_shadowed_56_gated_we = alert_class_shadowed_56_we & alert_regwen_56_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_56_re), + .we (alert_class_shadowed_56_gated_we), + .wd (alert_class_shadowed_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[56].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_56_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_56_update_err), + .err_storage (alert_class_shadowed_56_storage_err) + ); + + + // Subregister 57 of Multireg alert_class_shadowed + // R[alert_class_shadowed_57]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_57_gated_we; + assign alert_class_shadowed_57_gated_we = alert_class_shadowed_57_we & alert_regwen_57_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_57_re), + .we (alert_class_shadowed_57_gated_we), + .wd (alert_class_shadowed_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[57].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_57_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_57_update_err), + .err_storage (alert_class_shadowed_57_storage_err) + ); + + + // Subregister 58 of Multireg alert_class_shadowed + // R[alert_class_shadowed_58]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_58_gated_we; + assign alert_class_shadowed_58_gated_we = alert_class_shadowed_58_we & alert_regwen_58_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_58_re), + .we (alert_class_shadowed_58_gated_we), + .wd (alert_class_shadowed_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[58].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_58_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_58_update_err), + .err_storage (alert_class_shadowed_58_storage_err) + ); + + + // Subregister 59 of Multireg alert_class_shadowed + // R[alert_class_shadowed_59]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_59_gated_we; + assign alert_class_shadowed_59_gated_we = alert_class_shadowed_59_we & alert_regwen_59_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_59_re), + .we (alert_class_shadowed_59_gated_we), + .wd (alert_class_shadowed_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[59].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_59_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_59_update_err), + .err_storage (alert_class_shadowed_59_storage_err) + ); + + + // Subregister 60 of Multireg alert_class_shadowed + // R[alert_class_shadowed_60]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_60_gated_we; + assign alert_class_shadowed_60_gated_we = alert_class_shadowed_60_we & alert_regwen_60_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_60_re), + .we (alert_class_shadowed_60_gated_we), + .wd (alert_class_shadowed_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[60].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_60_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_60_update_err), + .err_storage (alert_class_shadowed_60_storage_err) + ); + + + // Subregister 61 of Multireg alert_class_shadowed + // R[alert_class_shadowed_61]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_61_gated_we; + assign alert_class_shadowed_61_gated_we = alert_class_shadowed_61_we & alert_regwen_61_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_61_re), + .we (alert_class_shadowed_61_gated_we), + .wd (alert_class_shadowed_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[61].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_61_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_61_update_err), + .err_storage (alert_class_shadowed_61_storage_err) + ); + + + // Subregister 62 of Multireg alert_class_shadowed + // R[alert_class_shadowed_62]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_62_gated_we; + assign alert_class_shadowed_62_gated_we = alert_class_shadowed_62_we & alert_regwen_62_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_62_re), + .we (alert_class_shadowed_62_gated_we), + .wd (alert_class_shadowed_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[62].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_62_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_62_update_err), + .err_storage (alert_class_shadowed_62_storage_err) + ); + + + // Subregister 63 of Multireg alert_class_shadowed + // R[alert_class_shadowed_63]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_63_gated_we; + assign alert_class_shadowed_63_gated_we = alert_class_shadowed_63_we & alert_regwen_63_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_63_re), + .we (alert_class_shadowed_63_gated_we), + .wd (alert_class_shadowed_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[63].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_63_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_63_update_err), + .err_storage (alert_class_shadowed_63_storage_err) + ); + + + // Subregister 64 of Multireg alert_class_shadowed + // R[alert_class_shadowed_64]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_64_gated_we; + assign alert_class_shadowed_64_gated_we = alert_class_shadowed_64_we & alert_regwen_64_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_64_re), + .we (alert_class_shadowed_64_gated_we), + .wd (alert_class_shadowed_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[64].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_64_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_64_update_err), + .err_storage (alert_class_shadowed_64_storage_err) + ); + + + // Subregister 65 of Multireg alert_class_shadowed + // R[alert_class_shadowed_65]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_65_gated_we; + assign alert_class_shadowed_65_gated_we = alert_class_shadowed_65_we & alert_regwen_65_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_65_re), + .we (alert_class_shadowed_65_gated_we), + .wd (alert_class_shadowed_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[65].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_65_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_65_update_err), + .err_storage (alert_class_shadowed_65_storage_err) + ); + + + // Subregister 66 of Multireg alert_class_shadowed + // R[alert_class_shadowed_66]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_66_gated_we; + assign alert_class_shadowed_66_gated_we = alert_class_shadowed_66_we & alert_regwen_66_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_66_re), + .we (alert_class_shadowed_66_gated_we), + .wd (alert_class_shadowed_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[66].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_66_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_66_update_err), + .err_storage (alert_class_shadowed_66_storage_err) + ); + + + // Subregister 67 of Multireg alert_class_shadowed + // R[alert_class_shadowed_67]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_67_gated_we; + assign alert_class_shadowed_67_gated_we = alert_class_shadowed_67_we & alert_regwen_67_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_67_re), + .we (alert_class_shadowed_67_gated_we), + .wd (alert_class_shadowed_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[67].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_67_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_67_update_err), + .err_storage (alert_class_shadowed_67_storage_err) + ); + + + // Subregister 68 of Multireg alert_class_shadowed + // R[alert_class_shadowed_68]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_68_gated_we; + assign alert_class_shadowed_68_gated_we = alert_class_shadowed_68_we & alert_regwen_68_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_68_re), + .we (alert_class_shadowed_68_gated_we), + .wd (alert_class_shadowed_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[68].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_68_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_68_update_err), + .err_storage (alert_class_shadowed_68_storage_err) + ); + + + // Subregister 69 of Multireg alert_class_shadowed + // R[alert_class_shadowed_69]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_69_gated_we; + assign alert_class_shadowed_69_gated_we = alert_class_shadowed_69_we & alert_regwen_69_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_69_re), + .we (alert_class_shadowed_69_gated_we), + .wd (alert_class_shadowed_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[69].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_69_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_69_update_err), + .err_storage (alert_class_shadowed_69_storage_err) + ); + + + // Subregister 70 of Multireg alert_class_shadowed + // R[alert_class_shadowed_70]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_70_gated_we; + assign alert_class_shadowed_70_gated_we = alert_class_shadowed_70_we & alert_regwen_70_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_70_re), + .we (alert_class_shadowed_70_gated_we), + .wd (alert_class_shadowed_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[70].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_70_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_70_update_err), + .err_storage (alert_class_shadowed_70_storage_err) + ); + + + // Subregister 71 of Multireg alert_class_shadowed + // R[alert_class_shadowed_71]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_71_gated_we; + assign alert_class_shadowed_71_gated_we = alert_class_shadowed_71_we & alert_regwen_71_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_71_re), + .we (alert_class_shadowed_71_gated_we), + .wd (alert_class_shadowed_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[71].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_71_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_71_update_err), + .err_storage (alert_class_shadowed_71_storage_err) + ); + + + // Subregister 72 of Multireg alert_class_shadowed + // R[alert_class_shadowed_72]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_72_gated_we; + assign alert_class_shadowed_72_gated_we = alert_class_shadowed_72_we & alert_regwen_72_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_72_re), + .we (alert_class_shadowed_72_gated_we), + .wd (alert_class_shadowed_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[72].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_72_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_72_update_err), + .err_storage (alert_class_shadowed_72_storage_err) + ); + + + // Subregister 73 of Multireg alert_class_shadowed + // R[alert_class_shadowed_73]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_73_gated_we; + assign alert_class_shadowed_73_gated_we = alert_class_shadowed_73_we & alert_regwen_73_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_73_re), + .we (alert_class_shadowed_73_gated_we), + .wd (alert_class_shadowed_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[73].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_73_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_73_update_err), + .err_storage (alert_class_shadowed_73_storage_err) + ); + + + // Subregister 74 of Multireg alert_class_shadowed + // R[alert_class_shadowed_74]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_74_gated_we; + assign alert_class_shadowed_74_gated_we = alert_class_shadowed_74_we & alert_regwen_74_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_74_re), + .we (alert_class_shadowed_74_gated_we), + .wd (alert_class_shadowed_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[74].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_74_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_74_update_err), + .err_storage (alert_class_shadowed_74_storage_err) + ); + + + // Subregister 75 of Multireg alert_class_shadowed + // R[alert_class_shadowed_75]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_75_gated_we; + assign alert_class_shadowed_75_gated_we = alert_class_shadowed_75_we & alert_regwen_75_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_75_re), + .we (alert_class_shadowed_75_gated_we), + .wd (alert_class_shadowed_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[75].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_75_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_75_update_err), + .err_storage (alert_class_shadowed_75_storage_err) + ); + + + // Subregister 76 of Multireg alert_class_shadowed + // R[alert_class_shadowed_76]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_76_gated_we; + assign alert_class_shadowed_76_gated_we = alert_class_shadowed_76_we & alert_regwen_76_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_76_re), + .we (alert_class_shadowed_76_gated_we), + .wd (alert_class_shadowed_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[76].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_76_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_76_update_err), + .err_storage (alert_class_shadowed_76_storage_err) + ); + + + // Subregister 77 of Multireg alert_class_shadowed + // R[alert_class_shadowed_77]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_77_gated_we; + assign alert_class_shadowed_77_gated_we = alert_class_shadowed_77_we & alert_regwen_77_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_77_re), + .we (alert_class_shadowed_77_gated_we), + .wd (alert_class_shadowed_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[77].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_77_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_77_update_err), + .err_storage (alert_class_shadowed_77_storage_err) + ); + + + // Subregister 78 of Multireg alert_class_shadowed + // R[alert_class_shadowed_78]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_78_gated_we; + assign alert_class_shadowed_78_gated_we = alert_class_shadowed_78_we & alert_regwen_78_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_78_re), + .we (alert_class_shadowed_78_gated_we), + .wd (alert_class_shadowed_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[78].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_78_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_78_update_err), + .err_storage (alert_class_shadowed_78_storage_err) + ); + + + // Subregister 79 of Multireg alert_class_shadowed + // R[alert_class_shadowed_79]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_79_gated_we; + assign alert_class_shadowed_79_gated_we = alert_class_shadowed_79_we & alert_regwen_79_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_79_re), + .we (alert_class_shadowed_79_gated_we), + .wd (alert_class_shadowed_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[79].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_79_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_79_update_err), + .err_storage (alert_class_shadowed_79_storage_err) + ); + + + // Subregister 80 of Multireg alert_class_shadowed + // R[alert_class_shadowed_80]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_80_gated_we; + assign alert_class_shadowed_80_gated_we = alert_class_shadowed_80_we & alert_regwen_80_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_80_re), + .we (alert_class_shadowed_80_gated_we), + .wd (alert_class_shadowed_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[80].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_80_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_80_update_err), + .err_storage (alert_class_shadowed_80_storage_err) + ); + + + // Subregister 81 of Multireg alert_class_shadowed + // R[alert_class_shadowed_81]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_81_gated_we; + assign alert_class_shadowed_81_gated_we = alert_class_shadowed_81_we & alert_regwen_81_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_81_re), + .we (alert_class_shadowed_81_gated_we), + .wd (alert_class_shadowed_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[81].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_81_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_81_update_err), + .err_storage (alert_class_shadowed_81_storage_err) + ); + + + // Subregister 82 of Multireg alert_class_shadowed + // R[alert_class_shadowed_82]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_82_gated_we; + assign alert_class_shadowed_82_gated_we = alert_class_shadowed_82_we & alert_regwen_82_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_82_re), + .we (alert_class_shadowed_82_gated_we), + .wd (alert_class_shadowed_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[82].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_82_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_82_update_err), + .err_storage (alert_class_shadowed_82_storage_err) + ); + + + // Subregister 83 of Multireg alert_class_shadowed + // R[alert_class_shadowed_83]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_83_gated_we; + assign alert_class_shadowed_83_gated_we = alert_class_shadowed_83_we & alert_regwen_83_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_83_re), + .we (alert_class_shadowed_83_gated_we), + .wd (alert_class_shadowed_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[83].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_83_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_83_update_err), + .err_storage (alert_class_shadowed_83_storage_err) + ); + + + // Subregister 84 of Multireg alert_class_shadowed + // R[alert_class_shadowed_84]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_84_gated_we; + assign alert_class_shadowed_84_gated_we = alert_class_shadowed_84_we & alert_regwen_84_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_84_re), + .we (alert_class_shadowed_84_gated_we), + .wd (alert_class_shadowed_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[84].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_84_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_84_update_err), + .err_storage (alert_class_shadowed_84_storage_err) + ); + + + // Subregister 85 of Multireg alert_class_shadowed + // R[alert_class_shadowed_85]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_85_gated_we; + assign alert_class_shadowed_85_gated_we = alert_class_shadowed_85_we & alert_regwen_85_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_85_re), + .we (alert_class_shadowed_85_gated_we), + .wd (alert_class_shadowed_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[85].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_85_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_85_update_err), + .err_storage (alert_class_shadowed_85_storage_err) + ); + + + // Subregister 86 of Multireg alert_class_shadowed + // R[alert_class_shadowed_86]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_86_gated_we; + assign alert_class_shadowed_86_gated_we = alert_class_shadowed_86_we & alert_regwen_86_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_86_re), + .we (alert_class_shadowed_86_gated_we), + .wd (alert_class_shadowed_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[86].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_86_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_86_update_err), + .err_storage (alert_class_shadowed_86_storage_err) + ); + + + // Subregister 87 of Multireg alert_class_shadowed + // R[alert_class_shadowed_87]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_87_gated_we; + assign alert_class_shadowed_87_gated_we = alert_class_shadowed_87_we & alert_regwen_87_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_87_re), + .we (alert_class_shadowed_87_gated_we), + .wd (alert_class_shadowed_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[87].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_87_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_87_update_err), + .err_storage (alert_class_shadowed_87_storage_err) + ); + + + // Subregister 88 of Multireg alert_class_shadowed + // R[alert_class_shadowed_88]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_88_gated_we; + assign alert_class_shadowed_88_gated_we = alert_class_shadowed_88_we & alert_regwen_88_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_88_re), + .we (alert_class_shadowed_88_gated_we), + .wd (alert_class_shadowed_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[88].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_88_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_88_update_err), + .err_storage (alert_class_shadowed_88_storage_err) + ); + + + // Subregister 89 of Multireg alert_class_shadowed + // R[alert_class_shadowed_89]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_89_gated_we; + assign alert_class_shadowed_89_gated_we = alert_class_shadowed_89_we & alert_regwen_89_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_89_re), + .we (alert_class_shadowed_89_gated_we), + .wd (alert_class_shadowed_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[89].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_89_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_89_update_err), + .err_storage (alert_class_shadowed_89_storage_err) + ); + + + // Subregister 90 of Multireg alert_class_shadowed + // R[alert_class_shadowed_90]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_90_gated_we; + assign alert_class_shadowed_90_gated_we = alert_class_shadowed_90_we & alert_regwen_90_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_90_re), + .we (alert_class_shadowed_90_gated_we), + .wd (alert_class_shadowed_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[90].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_90_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_90_update_err), + .err_storage (alert_class_shadowed_90_storage_err) + ); + + + // Subregister 91 of Multireg alert_class_shadowed + // R[alert_class_shadowed_91]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_91_gated_we; + assign alert_class_shadowed_91_gated_we = alert_class_shadowed_91_we & alert_regwen_91_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_91_re), + .we (alert_class_shadowed_91_gated_we), + .wd (alert_class_shadowed_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[91].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_91_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_91_update_err), + .err_storage (alert_class_shadowed_91_storage_err) + ); + + + // Subregister 92 of Multireg alert_class_shadowed + // R[alert_class_shadowed_92]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_92_gated_we; + assign alert_class_shadowed_92_gated_we = alert_class_shadowed_92_we & alert_regwen_92_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_92_re), + .we (alert_class_shadowed_92_gated_we), + .wd (alert_class_shadowed_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[92].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_92_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_92_update_err), + .err_storage (alert_class_shadowed_92_storage_err) + ); + + + // Subregister 93 of Multireg alert_class_shadowed + // R[alert_class_shadowed_93]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_93_gated_we; + assign alert_class_shadowed_93_gated_we = alert_class_shadowed_93_we & alert_regwen_93_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_93_re), + .we (alert_class_shadowed_93_gated_we), + .wd (alert_class_shadowed_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[93].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_93_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_93_update_err), + .err_storage (alert_class_shadowed_93_storage_err) + ); + + + // Subregister 94 of Multireg alert_class_shadowed + // R[alert_class_shadowed_94]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_94_gated_we; + assign alert_class_shadowed_94_gated_we = alert_class_shadowed_94_we & alert_regwen_94_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_94_re), + .we (alert_class_shadowed_94_gated_we), + .wd (alert_class_shadowed_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[94].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_94_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_94_update_err), + .err_storage (alert_class_shadowed_94_storage_err) + ); + + + // Subregister 95 of Multireg alert_class_shadowed + // R[alert_class_shadowed_95]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_95_gated_we; + assign alert_class_shadowed_95_gated_we = alert_class_shadowed_95_we & alert_regwen_95_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_95_re), + .we (alert_class_shadowed_95_gated_we), + .wd (alert_class_shadowed_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[95].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_95_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_95_update_err), + .err_storage (alert_class_shadowed_95_storage_err) + ); + + + // Subregister 96 of Multireg alert_class_shadowed + // R[alert_class_shadowed_96]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_96_gated_we; + assign alert_class_shadowed_96_gated_we = alert_class_shadowed_96_we & alert_regwen_96_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_96_re), + .we (alert_class_shadowed_96_gated_we), + .wd (alert_class_shadowed_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[96].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_96_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_96_update_err), + .err_storage (alert_class_shadowed_96_storage_err) + ); + + + // Subregister 97 of Multireg alert_class_shadowed + // R[alert_class_shadowed_97]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_97_gated_we; + assign alert_class_shadowed_97_gated_we = alert_class_shadowed_97_we & alert_regwen_97_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_97_re), + .we (alert_class_shadowed_97_gated_we), + .wd (alert_class_shadowed_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[97].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_97_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_97_update_err), + .err_storage (alert_class_shadowed_97_storage_err) + ); + + + // Subregister 98 of Multireg alert_class_shadowed + // R[alert_class_shadowed_98]: V(False) + // Create REGWEN-gated WE signal + logic alert_class_shadowed_98_gated_we; + assign alert_class_shadowed_98_gated_we = alert_class_shadowed_98_we & alert_regwen_98_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_alert_class_shadowed_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (alert_class_shadowed_98_re), + .we (alert_class_shadowed_98_gated_we), + .wd (alert_class_shadowed_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_class_shadowed[98].q), + .ds (), + + // to register interface (read) + .qs (alert_class_shadowed_98_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (alert_class_shadowed_98_update_err), + .err_storage (alert_class_shadowed_98_storage_err) + ); + + + // Subregister 0 of Multireg alert_cause + // R[alert_cause_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_0_we), + .wd (alert_cause_0_wd), + + // from internal hardware + .de (hw2reg.alert_cause[0].de), + .d (hw2reg.alert_cause[0].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[0].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_0_qs) + ); + + + // Subregister 1 of Multireg alert_cause + // R[alert_cause_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_1_we), + .wd (alert_cause_1_wd), + + // from internal hardware + .de (hw2reg.alert_cause[1].de), + .d (hw2reg.alert_cause[1].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[1].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_1_qs) + ); + + + // Subregister 2 of Multireg alert_cause + // R[alert_cause_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_2_we), + .wd (alert_cause_2_wd), + + // from internal hardware + .de (hw2reg.alert_cause[2].de), + .d (hw2reg.alert_cause[2].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[2].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_2_qs) + ); + + + // Subregister 3 of Multireg alert_cause + // R[alert_cause_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_3_we), + .wd (alert_cause_3_wd), + + // from internal hardware + .de (hw2reg.alert_cause[3].de), + .d (hw2reg.alert_cause[3].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[3].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_3_qs) + ); + + + // Subregister 4 of Multireg alert_cause + // R[alert_cause_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_4_we), + .wd (alert_cause_4_wd), + + // from internal hardware + .de (hw2reg.alert_cause[4].de), + .d (hw2reg.alert_cause[4].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[4].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_4_qs) + ); + + + // Subregister 5 of Multireg alert_cause + // R[alert_cause_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_5_we), + .wd (alert_cause_5_wd), + + // from internal hardware + .de (hw2reg.alert_cause[5].de), + .d (hw2reg.alert_cause[5].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[5].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_5_qs) + ); + + + // Subregister 6 of Multireg alert_cause + // R[alert_cause_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_6_we), + .wd (alert_cause_6_wd), + + // from internal hardware + .de (hw2reg.alert_cause[6].de), + .d (hw2reg.alert_cause[6].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[6].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_6_qs) + ); + + + // Subregister 7 of Multireg alert_cause + // R[alert_cause_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_7_we), + .wd (alert_cause_7_wd), + + // from internal hardware + .de (hw2reg.alert_cause[7].de), + .d (hw2reg.alert_cause[7].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[7].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_7_qs) + ); + + + // Subregister 8 of Multireg alert_cause + // R[alert_cause_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_8_we), + .wd (alert_cause_8_wd), + + // from internal hardware + .de (hw2reg.alert_cause[8].de), + .d (hw2reg.alert_cause[8].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[8].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_8_qs) + ); + + + // Subregister 9 of Multireg alert_cause + // R[alert_cause_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_9_we), + .wd (alert_cause_9_wd), + + // from internal hardware + .de (hw2reg.alert_cause[9].de), + .d (hw2reg.alert_cause[9].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[9].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_9_qs) + ); + + + // Subregister 10 of Multireg alert_cause + // R[alert_cause_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_10_we), + .wd (alert_cause_10_wd), + + // from internal hardware + .de (hw2reg.alert_cause[10].de), + .d (hw2reg.alert_cause[10].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[10].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_10_qs) + ); + + + // Subregister 11 of Multireg alert_cause + // R[alert_cause_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_11_we), + .wd (alert_cause_11_wd), + + // from internal hardware + .de (hw2reg.alert_cause[11].de), + .d (hw2reg.alert_cause[11].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[11].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_11_qs) + ); + + + // Subregister 12 of Multireg alert_cause + // R[alert_cause_12]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_12_we), + .wd (alert_cause_12_wd), + + // from internal hardware + .de (hw2reg.alert_cause[12].de), + .d (hw2reg.alert_cause[12].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[12].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_12_qs) + ); + + + // Subregister 13 of Multireg alert_cause + // R[alert_cause_13]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_13_we), + .wd (alert_cause_13_wd), + + // from internal hardware + .de (hw2reg.alert_cause[13].de), + .d (hw2reg.alert_cause[13].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[13].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_13_qs) + ); + + + // Subregister 14 of Multireg alert_cause + // R[alert_cause_14]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_14_we), + .wd (alert_cause_14_wd), + + // from internal hardware + .de (hw2reg.alert_cause[14].de), + .d (hw2reg.alert_cause[14].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[14].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_14_qs) + ); + + + // Subregister 15 of Multireg alert_cause + // R[alert_cause_15]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_15_we), + .wd (alert_cause_15_wd), + + // from internal hardware + .de (hw2reg.alert_cause[15].de), + .d (hw2reg.alert_cause[15].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[15].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_15_qs) + ); + + + // Subregister 16 of Multireg alert_cause + // R[alert_cause_16]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_16_we), + .wd (alert_cause_16_wd), + + // from internal hardware + .de (hw2reg.alert_cause[16].de), + .d (hw2reg.alert_cause[16].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[16].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_16_qs) + ); + + + // Subregister 17 of Multireg alert_cause + // R[alert_cause_17]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_17_we), + .wd (alert_cause_17_wd), + + // from internal hardware + .de (hw2reg.alert_cause[17].de), + .d (hw2reg.alert_cause[17].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[17].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_17_qs) + ); + + + // Subregister 18 of Multireg alert_cause + // R[alert_cause_18]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_18_we), + .wd (alert_cause_18_wd), + + // from internal hardware + .de (hw2reg.alert_cause[18].de), + .d (hw2reg.alert_cause[18].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[18].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_18_qs) + ); + + + // Subregister 19 of Multireg alert_cause + // R[alert_cause_19]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_19_we), + .wd (alert_cause_19_wd), + + // from internal hardware + .de (hw2reg.alert_cause[19].de), + .d (hw2reg.alert_cause[19].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[19].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_19_qs) + ); + + + // Subregister 20 of Multireg alert_cause + // R[alert_cause_20]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_20_we), + .wd (alert_cause_20_wd), + + // from internal hardware + .de (hw2reg.alert_cause[20].de), + .d (hw2reg.alert_cause[20].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[20].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_20_qs) + ); + + + // Subregister 21 of Multireg alert_cause + // R[alert_cause_21]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_21_we), + .wd (alert_cause_21_wd), + + // from internal hardware + .de (hw2reg.alert_cause[21].de), + .d (hw2reg.alert_cause[21].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[21].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_21_qs) + ); + + + // Subregister 22 of Multireg alert_cause + // R[alert_cause_22]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_22_we), + .wd (alert_cause_22_wd), + + // from internal hardware + .de (hw2reg.alert_cause[22].de), + .d (hw2reg.alert_cause[22].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[22].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_22_qs) + ); + + + // Subregister 23 of Multireg alert_cause + // R[alert_cause_23]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_23_we), + .wd (alert_cause_23_wd), + + // from internal hardware + .de (hw2reg.alert_cause[23].de), + .d (hw2reg.alert_cause[23].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[23].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_23_qs) + ); + + + // Subregister 24 of Multireg alert_cause + // R[alert_cause_24]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_24_we), + .wd (alert_cause_24_wd), + + // from internal hardware + .de (hw2reg.alert_cause[24].de), + .d (hw2reg.alert_cause[24].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[24].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_24_qs) + ); + + + // Subregister 25 of Multireg alert_cause + // R[alert_cause_25]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_25_we), + .wd (alert_cause_25_wd), + + // from internal hardware + .de (hw2reg.alert_cause[25].de), + .d (hw2reg.alert_cause[25].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[25].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_25_qs) + ); + + + // Subregister 26 of Multireg alert_cause + // R[alert_cause_26]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_26_we), + .wd (alert_cause_26_wd), + + // from internal hardware + .de (hw2reg.alert_cause[26].de), + .d (hw2reg.alert_cause[26].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[26].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_26_qs) + ); + + + // Subregister 27 of Multireg alert_cause + // R[alert_cause_27]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_27_we), + .wd (alert_cause_27_wd), + + // from internal hardware + .de (hw2reg.alert_cause[27].de), + .d (hw2reg.alert_cause[27].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[27].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_27_qs) + ); + + + // Subregister 28 of Multireg alert_cause + // R[alert_cause_28]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_28_we), + .wd (alert_cause_28_wd), + + // from internal hardware + .de (hw2reg.alert_cause[28].de), + .d (hw2reg.alert_cause[28].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[28].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_28_qs) + ); + + + // Subregister 29 of Multireg alert_cause + // R[alert_cause_29]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_29_we), + .wd (alert_cause_29_wd), + + // from internal hardware + .de (hw2reg.alert_cause[29].de), + .d (hw2reg.alert_cause[29].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[29].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_29_qs) + ); + + + // Subregister 30 of Multireg alert_cause + // R[alert_cause_30]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_30_we), + .wd (alert_cause_30_wd), + + // from internal hardware + .de (hw2reg.alert_cause[30].de), + .d (hw2reg.alert_cause[30].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[30].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_30_qs) + ); + + + // Subregister 31 of Multireg alert_cause + // R[alert_cause_31]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_31_we), + .wd (alert_cause_31_wd), + + // from internal hardware + .de (hw2reg.alert_cause[31].de), + .d (hw2reg.alert_cause[31].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[31].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_31_qs) + ); + + + // Subregister 32 of Multireg alert_cause + // R[alert_cause_32]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_32_we), + .wd (alert_cause_32_wd), + + // from internal hardware + .de (hw2reg.alert_cause[32].de), + .d (hw2reg.alert_cause[32].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[32].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_32_qs) + ); + + + // Subregister 33 of Multireg alert_cause + // R[alert_cause_33]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_33_we), + .wd (alert_cause_33_wd), + + // from internal hardware + .de (hw2reg.alert_cause[33].de), + .d (hw2reg.alert_cause[33].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[33].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_33_qs) + ); + + + // Subregister 34 of Multireg alert_cause + // R[alert_cause_34]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_34_we), + .wd (alert_cause_34_wd), + + // from internal hardware + .de (hw2reg.alert_cause[34].de), + .d (hw2reg.alert_cause[34].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[34].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_34_qs) + ); + + + // Subregister 35 of Multireg alert_cause + // R[alert_cause_35]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_35_we), + .wd (alert_cause_35_wd), + + // from internal hardware + .de (hw2reg.alert_cause[35].de), + .d (hw2reg.alert_cause[35].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[35].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_35_qs) + ); + + + // Subregister 36 of Multireg alert_cause + // R[alert_cause_36]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_36_we), + .wd (alert_cause_36_wd), + + // from internal hardware + .de (hw2reg.alert_cause[36].de), + .d (hw2reg.alert_cause[36].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[36].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_36_qs) + ); + + + // Subregister 37 of Multireg alert_cause + // R[alert_cause_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_37_we), + .wd (alert_cause_37_wd), + + // from internal hardware + .de (hw2reg.alert_cause[37].de), + .d (hw2reg.alert_cause[37].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[37].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_37_qs) + ); + + + // Subregister 38 of Multireg alert_cause + // R[alert_cause_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_38_we), + .wd (alert_cause_38_wd), + + // from internal hardware + .de (hw2reg.alert_cause[38].de), + .d (hw2reg.alert_cause[38].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[38].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_38_qs) + ); + + + // Subregister 39 of Multireg alert_cause + // R[alert_cause_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_39_we), + .wd (alert_cause_39_wd), + + // from internal hardware + .de (hw2reg.alert_cause[39].de), + .d (hw2reg.alert_cause[39].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[39].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_39_qs) + ); + + + // Subregister 40 of Multireg alert_cause + // R[alert_cause_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_40_we), + .wd (alert_cause_40_wd), + + // from internal hardware + .de (hw2reg.alert_cause[40].de), + .d (hw2reg.alert_cause[40].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[40].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_40_qs) + ); + + + // Subregister 41 of Multireg alert_cause + // R[alert_cause_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_41_we), + .wd (alert_cause_41_wd), + + // from internal hardware + .de (hw2reg.alert_cause[41].de), + .d (hw2reg.alert_cause[41].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[41].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_41_qs) + ); + + + // Subregister 42 of Multireg alert_cause + // R[alert_cause_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_42_we), + .wd (alert_cause_42_wd), + + // from internal hardware + .de (hw2reg.alert_cause[42].de), + .d (hw2reg.alert_cause[42].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[42].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_42_qs) + ); + + + // Subregister 43 of Multireg alert_cause + // R[alert_cause_43]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_43_we), + .wd (alert_cause_43_wd), + + // from internal hardware + .de (hw2reg.alert_cause[43].de), + .d (hw2reg.alert_cause[43].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[43].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_43_qs) + ); + + + // Subregister 44 of Multireg alert_cause + // R[alert_cause_44]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_44_we), + .wd (alert_cause_44_wd), + + // from internal hardware + .de (hw2reg.alert_cause[44].de), + .d (hw2reg.alert_cause[44].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[44].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_44_qs) + ); + + + // Subregister 45 of Multireg alert_cause + // R[alert_cause_45]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_45_we), + .wd (alert_cause_45_wd), + + // from internal hardware + .de (hw2reg.alert_cause[45].de), + .d (hw2reg.alert_cause[45].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[45].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_45_qs) + ); + + + // Subregister 46 of Multireg alert_cause + // R[alert_cause_46]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_46_we), + .wd (alert_cause_46_wd), + + // from internal hardware + .de (hw2reg.alert_cause[46].de), + .d (hw2reg.alert_cause[46].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[46].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_46_qs) + ); + + + // Subregister 47 of Multireg alert_cause + // R[alert_cause_47]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_47_we), + .wd (alert_cause_47_wd), + + // from internal hardware + .de (hw2reg.alert_cause[47].de), + .d (hw2reg.alert_cause[47].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[47].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_47_qs) + ); + + + // Subregister 48 of Multireg alert_cause + // R[alert_cause_48]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_48_we), + .wd (alert_cause_48_wd), + + // from internal hardware + .de (hw2reg.alert_cause[48].de), + .d (hw2reg.alert_cause[48].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[48].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_48_qs) + ); + + + // Subregister 49 of Multireg alert_cause + // R[alert_cause_49]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_49_we), + .wd (alert_cause_49_wd), + + // from internal hardware + .de (hw2reg.alert_cause[49].de), + .d (hw2reg.alert_cause[49].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[49].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_49_qs) + ); + + + // Subregister 50 of Multireg alert_cause + // R[alert_cause_50]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_50_we), + .wd (alert_cause_50_wd), + + // from internal hardware + .de (hw2reg.alert_cause[50].de), + .d (hw2reg.alert_cause[50].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[50].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_50_qs) + ); + + + // Subregister 51 of Multireg alert_cause + // R[alert_cause_51]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_51_we), + .wd (alert_cause_51_wd), + + // from internal hardware + .de (hw2reg.alert_cause[51].de), + .d (hw2reg.alert_cause[51].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[51].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_51_qs) + ); + + + // Subregister 52 of Multireg alert_cause + // R[alert_cause_52]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_52_we), + .wd (alert_cause_52_wd), + + // from internal hardware + .de (hw2reg.alert_cause[52].de), + .d (hw2reg.alert_cause[52].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[52].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_52_qs) + ); + + + // Subregister 53 of Multireg alert_cause + // R[alert_cause_53]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_53_we), + .wd (alert_cause_53_wd), + + // from internal hardware + .de (hw2reg.alert_cause[53].de), + .d (hw2reg.alert_cause[53].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[53].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_53_qs) + ); + + + // Subregister 54 of Multireg alert_cause + // R[alert_cause_54]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_54_we), + .wd (alert_cause_54_wd), + + // from internal hardware + .de (hw2reg.alert_cause[54].de), + .d (hw2reg.alert_cause[54].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[54].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_54_qs) + ); + + + // Subregister 55 of Multireg alert_cause + // R[alert_cause_55]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_55_we), + .wd (alert_cause_55_wd), + + // from internal hardware + .de (hw2reg.alert_cause[55].de), + .d (hw2reg.alert_cause[55].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[55].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_55_qs) + ); + + + // Subregister 56 of Multireg alert_cause + // R[alert_cause_56]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_56_we), + .wd (alert_cause_56_wd), + + // from internal hardware + .de (hw2reg.alert_cause[56].de), + .d (hw2reg.alert_cause[56].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[56].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_56_qs) + ); + + + // Subregister 57 of Multireg alert_cause + // R[alert_cause_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_57_we), + .wd (alert_cause_57_wd), + + // from internal hardware + .de (hw2reg.alert_cause[57].de), + .d (hw2reg.alert_cause[57].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[57].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_57_qs) + ); + + + // Subregister 58 of Multireg alert_cause + // R[alert_cause_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_58_we), + .wd (alert_cause_58_wd), + + // from internal hardware + .de (hw2reg.alert_cause[58].de), + .d (hw2reg.alert_cause[58].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[58].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_58_qs) + ); + + + // Subregister 59 of Multireg alert_cause + // R[alert_cause_59]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_59_we), + .wd (alert_cause_59_wd), + + // from internal hardware + .de (hw2reg.alert_cause[59].de), + .d (hw2reg.alert_cause[59].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[59].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_59_qs) + ); + + + // Subregister 60 of Multireg alert_cause + // R[alert_cause_60]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_60_we), + .wd (alert_cause_60_wd), + + // from internal hardware + .de (hw2reg.alert_cause[60].de), + .d (hw2reg.alert_cause[60].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[60].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_60_qs) + ); + + + // Subregister 61 of Multireg alert_cause + // R[alert_cause_61]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_61_we), + .wd (alert_cause_61_wd), + + // from internal hardware + .de (hw2reg.alert_cause[61].de), + .d (hw2reg.alert_cause[61].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[61].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_61_qs) + ); + + + // Subregister 62 of Multireg alert_cause + // R[alert_cause_62]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_62_we), + .wd (alert_cause_62_wd), + + // from internal hardware + .de (hw2reg.alert_cause[62].de), + .d (hw2reg.alert_cause[62].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[62].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_62_qs) + ); + + + // Subregister 63 of Multireg alert_cause + // R[alert_cause_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_63_we), + .wd (alert_cause_63_wd), + + // from internal hardware + .de (hw2reg.alert_cause[63].de), + .d (hw2reg.alert_cause[63].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[63].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_63_qs) + ); + + + // Subregister 64 of Multireg alert_cause + // R[alert_cause_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_64_we), + .wd (alert_cause_64_wd), + + // from internal hardware + .de (hw2reg.alert_cause[64].de), + .d (hw2reg.alert_cause[64].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[64].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_64_qs) + ); + + + // Subregister 65 of Multireg alert_cause + // R[alert_cause_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_65_we), + .wd (alert_cause_65_wd), + + // from internal hardware + .de (hw2reg.alert_cause[65].de), + .d (hw2reg.alert_cause[65].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[65].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_65_qs) + ); + + + // Subregister 66 of Multireg alert_cause + // R[alert_cause_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_66_we), + .wd (alert_cause_66_wd), + + // from internal hardware + .de (hw2reg.alert_cause[66].de), + .d (hw2reg.alert_cause[66].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[66].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_66_qs) + ); + + + // Subregister 67 of Multireg alert_cause + // R[alert_cause_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_67_we), + .wd (alert_cause_67_wd), + + // from internal hardware + .de (hw2reg.alert_cause[67].de), + .d (hw2reg.alert_cause[67].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[67].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_67_qs) + ); + + + // Subregister 68 of Multireg alert_cause + // R[alert_cause_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_68_we), + .wd (alert_cause_68_wd), + + // from internal hardware + .de (hw2reg.alert_cause[68].de), + .d (hw2reg.alert_cause[68].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[68].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_68_qs) + ); + + + // Subregister 69 of Multireg alert_cause + // R[alert_cause_69]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_69_we), + .wd (alert_cause_69_wd), + + // from internal hardware + .de (hw2reg.alert_cause[69].de), + .d (hw2reg.alert_cause[69].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[69].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_69_qs) + ); + + + // Subregister 70 of Multireg alert_cause + // R[alert_cause_70]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_70_we), + .wd (alert_cause_70_wd), + + // from internal hardware + .de (hw2reg.alert_cause[70].de), + .d (hw2reg.alert_cause[70].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[70].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_70_qs) + ); + + + // Subregister 71 of Multireg alert_cause + // R[alert_cause_71]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_71_we), + .wd (alert_cause_71_wd), + + // from internal hardware + .de (hw2reg.alert_cause[71].de), + .d (hw2reg.alert_cause[71].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[71].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_71_qs) + ); + + + // Subregister 72 of Multireg alert_cause + // R[alert_cause_72]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_72_we), + .wd (alert_cause_72_wd), + + // from internal hardware + .de (hw2reg.alert_cause[72].de), + .d (hw2reg.alert_cause[72].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[72].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_72_qs) + ); + + + // Subregister 73 of Multireg alert_cause + // R[alert_cause_73]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_73_we), + .wd (alert_cause_73_wd), + + // from internal hardware + .de (hw2reg.alert_cause[73].de), + .d (hw2reg.alert_cause[73].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[73].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_73_qs) + ); + + + // Subregister 74 of Multireg alert_cause + // R[alert_cause_74]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_74_we), + .wd (alert_cause_74_wd), + + // from internal hardware + .de (hw2reg.alert_cause[74].de), + .d (hw2reg.alert_cause[74].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[74].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_74_qs) + ); + + + // Subregister 75 of Multireg alert_cause + // R[alert_cause_75]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_75_we), + .wd (alert_cause_75_wd), + + // from internal hardware + .de (hw2reg.alert_cause[75].de), + .d (hw2reg.alert_cause[75].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[75].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_75_qs) + ); + + + // Subregister 76 of Multireg alert_cause + // R[alert_cause_76]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_76_we), + .wd (alert_cause_76_wd), + + // from internal hardware + .de (hw2reg.alert_cause[76].de), + .d (hw2reg.alert_cause[76].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[76].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_76_qs) + ); + + + // Subregister 77 of Multireg alert_cause + // R[alert_cause_77]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_77_we), + .wd (alert_cause_77_wd), + + // from internal hardware + .de (hw2reg.alert_cause[77].de), + .d (hw2reg.alert_cause[77].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[77].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_77_qs) + ); + + + // Subregister 78 of Multireg alert_cause + // R[alert_cause_78]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_78_we), + .wd (alert_cause_78_wd), + + // from internal hardware + .de (hw2reg.alert_cause[78].de), + .d (hw2reg.alert_cause[78].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[78].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_78_qs) + ); + + + // Subregister 79 of Multireg alert_cause + // R[alert_cause_79]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_79_we), + .wd (alert_cause_79_wd), + + // from internal hardware + .de (hw2reg.alert_cause[79].de), + .d (hw2reg.alert_cause[79].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[79].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_79_qs) + ); + + + // Subregister 80 of Multireg alert_cause + // R[alert_cause_80]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_80_we), + .wd (alert_cause_80_wd), + + // from internal hardware + .de (hw2reg.alert_cause[80].de), + .d (hw2reg.alert_cause[80].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[80].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_80_qs) + ); + + + // Subregister 81 of Multireg alert_cause + // R[alert_cause_81]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_81_we), + .wd (alert_cause_81_wd), + + // from internal hardware + .de (hw2reg.alert_cause[81].de), + .d (hw2reg.alert_cause[81].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[81].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_81_qs) + ); + + + // Subregister 82 of Multireg alert_cause + // R[alert_cause_82]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_82_we), + .wd (alert_cause_82_wd), + + // from internal hardware + .de (hw2reg.alert_cause[82].de), + .d (hw2reg.alert_cause[82].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[82].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_82_qs) + ); + + + // Subregister 83 of Multireg alert_cause + // R[alert_cause_83]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_83_we), + .wd (alert_cause_83_wd), + + // from internal hardware + .de (hw2reg.alert_cause[83].de), + .d (hw2reg.alert_cause[83].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[83].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_83_qs) + ); + + + // Subregister 84 of Multireg alert_cause + // R[alert_cause_84]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_84_we), + .wd (alert_cause_84_wd), + + // from internal hardware + .de (hw2reg.alert_cause[84].de), + .d (hw2reg.alert_cause[84].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[84].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_84_qs) + ); + + + // Subregister 85 of Multireg alert_cause + // R[alert_cause_85]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_85_we), + .wd (alert_cause_85_wd), + + // from internal hardware + .de (hw2reg.alert_cause[85].de), + .d (hw2reg.alert_cause[85].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[85].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_85_qs) + ); + + + // Subregister 86 of Multireg alert_cause + // R[alert_cause_86]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_86_we), + .wd (alert_cause_86_wd), + + // from internal hardware + .de (hw2reg.alert_cause[86].de), + .d (hw2reg.alert_cause[86].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[86].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_86_qs) + ); + + + // Subregister 87 of Multireg alert_cause + // R[alert_cause_87]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_87_we), + .wd (alert_cause_87_wd), + + // from internal hardware + .de (hw2reg.alert_cause[87].de), + .d (hw2reg.alert_cause[87].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[87].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_87_qs) + ); + + + // Subregister 88 of Multireg alert_cause + // R[alert_cause_88]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_88_we), + .wd (alert_cause_88_wd), + + // from internal hardware + .de (hw2reg.alert_cause[88].de), + .d (hw2reg.alert_cause[88].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[88].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_88_qs) + ); + + + // Subregister 89 of Multireg alert_cause + // R[alert_cause_89]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_89_we), + .wd (alert_cause_89_wd), + + // from internal hardware + .de (hw2reg.alert_cause[89].de), + .d (hw2reg.alert_cause[89].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[89].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_89_qs) + ); + + + // Subregister 90 of Multireg alert_cause + // R[alert_cause_90]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_90_we), + .wd (alert_cause_90_wd), + + // from internal hardware + .de (hw2reg.alert_cause[90].de), + .d (hw2reg.alert_cause[90].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[90].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_90_qs) + ); + + + // Subregister 91 of Multireg alert_cause + // R[alert_cause_91]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_91_we), + .wd (alert_cause_91_wd), + + // from internal hardware + .de (hw2reg.alert_cause[91].de), + .d (hw2reg.alert_cause[91].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[91].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_91_qs) + ); + + + // Subregister 92 of Multireg alert_cause + // R[alert_cause_92]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_92_we), + .wd (alert_cause_92_wd), + + // from internal hardware + .de (hw2reg.alert_cause[92].de), + .d (hw2reg.alert_cause[92].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[92].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_92_qs) + ); + + + // Subregister 93 of Multireg alert_cause + // R[alert_cause_93]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_93_we), + .wd (alert_cause_93_wd), + + // from internal hardware + .de (hw2reg.alert_cause[93].de), + .d (hw2reg.alert_cause[93].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[93].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_93_qs) + ); + + + // Subregister 94 of Multireg alert_cause + // R[alert_cause_94]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_94_we), + .wd (alert_cause_94_wd), + + // from internal hardware + .de (hw2reg.alert_cause[94].de), + .d (hw2reg.alert_cause[94].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[94].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_94_qs) + ); + + + // Subregister 95 of Multireg alert_cause + // R[alert_cause_95]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_95_we), + .wd (alert_cause_95_wd), + + // from internal hardware + .de (hw2reg.alert_cause[95].de), + .d (hw2reg.alert_cause[95].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[95].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_95_qs) + ); + + + // Subregister 96 of Multireg alert_cause + // R[alert_cause_96]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_96_we), + .wd (alert_cause_96_wd), + + // from internal hardware + .de (hw2reg.alert_cause[96].de), + .d (hw2reg.alert_cause[96].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[96].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_96_qs) + ); + + + // Subregister 97 of Multireg alert_cause + // R[alert_cause_97]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_97_we), + .wd (alert_cause_97_wd), + + // from internal hardware + .de (hw2reg.alert_cause[97].de), + .d (hw2reg.alert_cause[97].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[97].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_97_qs) + ); + + + // Subregister 98 of Multireg alert_cause + // R[alert_cause_98]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_cause_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_cause_98_we), + .wd (alert_cause_98_wd), + + // from internal hardware + .de (hw2reg.alert_cause[98].de), + .d (hw2reg.alert_cause[98].d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_cause[98].q), + .ds (), + + // to register interface (read) + .qs (alert_cause_98_qs) + ); + + + // Subregister 0 of Multireg loc_alert_regwen + // R[loc_alert_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_0_we), + .wd (loc_alert_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_0_qs) + ); + + + // Subregister 1 of Multireg loc_alert_regwen + // R[loc_alert_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_1_we), + .wd (loc_alert_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_1_qs) + ); + + + // Subregister 2 of Multireg loc_alert_regwen + // R[loc_alert_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_2_we), + .wd (loc_alert_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_2_qs) + ); + + + // Subregister 3 of Multireg loc_alert_regwen + // R[loc_alert_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_3_we), + .wd (loc_alert_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_3_qs) + ); + + + // Subregister 4 of Multireg loc_alert_regwen + // R[loc_alert_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_4_we), + .wd (loc_alert_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_4_qs) + ); + + + // Subregister 5 of Multireg loc_alert_regwen + // R[loc_alert_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_5_we), + .wd (loc_alert_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_5_qs) + ); + + + // Subregister 6 of Multireg loc_alert_regwen + // R[loc_alert_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_loc_alert_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_regwen_6_we), + .wd (loc_alert_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (loc_alert_regwen_6_qs) + ); + + + // Subregister 0 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_0]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_0_gated_we; + assign loc_alert_en_shadowed_0_gated_we = loc_alert_en_shadowed_0_we & loc_alert_regwen_0_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_0_re), + .we (loc_alert_en_shadowed_0_gated_we), + .wd (loc_alert_en_shadowed_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[0].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_0_update_err), + .err_storage (loc_alert_en_shadowed_0_storage_err) + ); + + + // Subregister 1 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_1]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_1_gated_we; + assign loc_alert_en_shadowed_1_gated_we = loc_alert_en_shadowed_1_we & loc_alert_regwen_1_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_1_re), + .we (loc_alert_en_shadowed_1_gated_we), + .wd (loc_alert_en_shadowed_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[1].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_1_update_err), + .err_storage (loc_alert_en_shadowed_1_storage_err) + ); + + + // Subregister 2 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_2]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_2_gated_we; + assign loc_alert_en_shadowed_2_gated_we = loc_alert_en_shadowed_2_we & loc_alert_regwen_2_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_2_re), + .we (loc_alert_en_shadowed_2_gated_we), + .wd (loc_alert_en_shadowed_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[2].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_2_update_err), + .err_storage (loc_alert_en_shadowed_2_storage_err) + ); + + + // Subregister 3 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_3]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_3_gated_we; + assign loc_alert_en_shadowed_3_gated_we = loc_alert_en_shadowed_3_we & loc_alert_regwen_3_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_3_re), + .we (loc_alert_en_shadowed_3_gated_we), + .wd (loc_alert_en_shadowed_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[3].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_3_update_err), + .err_storage (loc_alert_en_shadowed_3_storage_err) + ); + + + // Subregister 4 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_4]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_4_gated_we; + assign loc_alert_en_shadowed_4_gated_we = loc_alert_en_shadowed_4_we & loc_alert_regwen_4_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_4_re), + .we (loc_alert_en_shadowed_4_gated_we), + .wd (loc_alert_en_shadowed_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[4].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_4_update_err), + .err_storage (loc_alert_en_shadowed_4_storage_err) + ); + + + // Subregister 5 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_5]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_5_gated_we; + assign loc_alert_en_shadowed_5_gated_we = loc_alert_en_shadowed_5_we & loc_alert_regwen_5_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_5_re), + .we (loc_alert_en_shadowed_5_gated_we), + .wd (loc_alert_en_shadowed_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[5].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_5_update_err), + .err_storage (loc_alert_en_shadowed_5_storage_err) + ); + + + // Subregister 6 of Multireg loc_alert_en_shadowed + // R[loc_alert_en_shadowed_6]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_en_shadowed_6_gated_we; + assign loc_alert_en_shadowed_6_gated_we = loc_alert_en_shadowed_6_we & loc_alert_regwen_6_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_en_shadowed_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_en_shadowed_6_re), + .we (loc_alert_en_shadowed_6_gated_we), + .wd (loc_alert_en_shadowed_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_en_shadowed[6].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_en_shadowed_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_en_shadowed_6_update_err), + .err_storage (loc_alert_en_shadowed_6_storage_err) + ); + + + // Subregister 0 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_0]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_0_gated_we; + assign loc_alert_class_shadowed_0_gated_we = + loc_alert_class_shadowed_0_we & loc_alert_regwen_0_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_0_re), + .we (loc_alert_class_shadowed_0_gated_we), + .wd (loc_alert_class_shadowed_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[0].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_0_update_err), + .err_storage (loc_alert_class_shadowed_0_storage_err) + ); + + + // Subregister 1 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_1]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_1_gated_we; + assign loc_alert_class_shadowed_1_gated_we = + loc_alert_class_shadowed_1_we & loc_alert_regwen_1_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_1_re), + .we (loc_alert_class_shadowed_1_gated_we), + .wd (loc_alert_class_shadowed_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[1].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_1_update_err), + .err_storage (loc_alert_class_shadowed_1_storage_err) + ); + + + // Subregister 2 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_2]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_2_gated_we; + assign loc_alert_class_shadowed_2_gated_we = + loc_alert_class_shadowed_2_we & loc_alert_regwen_2_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_2_re), + .we (loc_alert_class_shadowed_2_gated_we), + .wd (loc_alert_class_shadowed_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[2].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_2_update_err), + .err_storage (loc_alert_class_shadowed_2_storage_err) + ); + + + // Subregister 3 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_3]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_3_gated_we; + assign loc_alert_class_shadowed_3_gated_we = + loc_alert_class_shadowed_3_we & loc_alert_regwen_3_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_3_re), + .we (loc_alert_class_shadowed_3_gated_we), + .wd (loc_alert_class_shadowed_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[3].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_3_update_err), + .err_storage (loc_alert_class_shadowed_3_storage_err) + ); + + + // Subregister 4 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_4]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_4_gated_we; + assign loc_alert_class_shadowed_4_gated_we = + loc_alert_class_shadowed_4_we & loc_alert_regwen_4_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_4_re), + .we (loc_alert_class_shadowed_4_gated_we), + .wd (loc_alert_class_shadowed_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[4].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_4_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_4_update_err), + .err_storage (loc_alert_class_shadowed_4_storage_err) + ); + + + // Subregister 5 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_5]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_5_gated_we; + assign loc_alert_class_shadowed_5_gated_we = + loc_alert_class_shadowed_5_we & loc_alert_regwen_5_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_5_re), + .we (loc_alert_class_shadowed_5_gated_we), + .wd (loc_alert_class_shadowed_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[5].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_5_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_5_update_err), + .err_storage (loc_alert_class_shadowed_5_storage_err) + ); + + + // Subregister 6 of Multireg loc_alert_class_shadowed + // R[loc_alert_class_shadowed_6]: V(False) + // Create REGWEN-gated WE signal + logic loc_alert_class_shadowed_6_gated_we; + assign loc_alert_class_shadowed_6_gated_we = + loc_alert_class_shadowed_6_we & loc_alert_regwen_6_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_loc_alert_class_shadowed_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (loc_alert_class_shadowed_6_re), + .we (loc_alert_class_shadowed_6_gated_we), + .wd (loc_alert_class_shadowed_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_class_shadowed[6].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_class_shadowed_6_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (loc_alert_class_shadowed_6_update_err), + .err_storage (loc_alert_class_shadowed_6_storage_err) + ); + + + // Subregister 0 of Multireg loc_alert_cause + // R[loc_alert_cause_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_0_we), + .wd (loc_alert_cause_0_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[0].de), + .d (hw2reg.loc_alert_cause[0].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[0].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_0_qs) + ); + + + // Subregister 1 of Multireg loc_alert_cause + // R[loc_alert_cause_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_1_we), + .wd (loc_alert_cause_1_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[1].de), + .d (hw2reg.loc_alert_cause[1].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[1].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_1_qs) + ); + + + // Subregister 2 of Multireg loc_alert_cause + // R[loc_alert_cause_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_2_we), + .wd (loc_alert_cause_2_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[2].de), + .d (hw2reg.loc_alert_cause[2].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[2].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_2_qs) + ); + + + // Subregister 3 of Multireg loc_alert_cause + // R[loc_alert_cause_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_3_we), + .wd (loc_alert_cause_3_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[3].de), + .d (hw2reg.loc_alert_cause[3].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[3].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_3_qs) + ); + + + // Subregister 4 of Multireg loc_alert_cause + // R[loc_alert_cause_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_4_we), + .wd (loc_alert_cause_4_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[4].de), + .d (hw2reg.loc_alert_cause[4].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[4].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_4_qs) + ); + + + // Subregister 5 of Multireg loc_alert_cause + // R[loc_alert_cause_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_5_we), + .wd (loc_alert_cause_5_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[5].de), + .d (hw2reg.loc_alert_cause[5].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[5].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_5_qs) + ); + + + // Subregister 6 of Multireg loc_alert_cause + // R[loc_alert_cause_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_loc_alert_cause_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (loc_alert_cause_6_we), + .wd (loc_alert_cause_6_wd), + + // from internal hardware + .de (hw2reg.loc_alert_cause[6].de), + .d (hw2reg.loc_alert_cause[6].d), + + // to internal hardware + .qe (), + .q (reg2hw.loc_alert_cause[6].q), + .ds (), + + // to register interface (read) + .qs (loc_alert_cause_6_qs) + ); + + + // R[classa_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classa_regwen_we), + .wd (classa_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classa_regwen_qs) + ); + + + // R[classa_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_ctrl_shadowed_gated_we; + assign classa_ctrl_shadowed_gated_we = classa_ctrl_shadowed_we & classa_regwen_qs; + // F[en]: 0:0 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_update_err), + .err_storage (classa_ctrl_shadowed_en_storage_err) + ); + + // F[lock]: 1:1 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.lock.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_lock_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_lock_update_err), + .err_storage (classa_ctrl_shadowed_lock_storage_err) + ); + + // F[en_e0]: 2:2 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en_e0.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_e0_update_err), + .err_storage (classa_ctrl_shadowed_en_e0_storage_err) + ); + + // F[en_e1]: 3:3 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en_e1.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_e1_update_err), + .err_storage (classa_ctrl_shadowed_en_e1_storage_err) + ); + + // F[en_e2]: 4:4 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en_e2.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_e2_update_err), + .err_storage (classa_ctrl_shadowed_en_e2_storage_err) + ); + + // F[en_e3]: 5:5 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_en_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_en_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.en_e3.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_en_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_en_e3_update_err), + .err_storage (classa_ctrl_shadowed_en_e3_storage_err) + ); + + // F[map_e0]: 7:6 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_map_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_map_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.map_e0.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_map_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_map_e0_update_err), + .err_storage (classa_ctrl_shadowed_map_e0_storage_err) + ); + + // F[map_e1]: 9:8 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h1), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_map_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_map_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.map_e1.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_map_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_map_e1_update_err), + .err_storage (classa_ctrl_shadowed_map_e1_storage_err) + ); + + // F[map_e2]: 11:10 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_map_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_map_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.map_e2.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_map_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_map_e2_update_err), + .err_storage (classa_ctrl_shadowed_map_e2_storage_err) + ); + + // F[map_e3]: 13:12 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h3), + .Mubi (1'b0) + ) u_classa_ctrl_shadowed_map_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_ctrl_shadowed_re), + .we (classa_ctrl_shadowed_gated_we), + .wd (classa_ctrl_shadowed_map_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_ctrl_shadowed.map_e3.q), + .ds (), + + // to register interface (read) + .qs (classa_ctrl_shadowed_map_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_ctrl_shadowed_map_e3_update_err), + .err_storage (classa_ctrl_shadowed_map_e3_storage_err) + ); + + + // R[classa_clr_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classa_clr_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classa_clr_regwen_we), + .wd (classa_clr_regwen_wd), + + // from internal hardware + .de (hw2reg.classa_clr_regwen.de), + .d (hw2reg.classa_clr_regwen.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classa_clr_regwen_qs) + ); + + + // R[classa_clr_shadowed]: V(False) + logic classa_clr_shadowed_qe; + logic [0:0] classa_clr_shadowed_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_classa_clr_shadowed0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&classa_clr_shadowed_flds_we), + .q_o(classa_clr_shadowed_qe) + ); + // Create REGWEN-gated WE signal + logic classa_clr_shadowed_gated_we; + assign classa_clr_shadowed_gated_we = classa_clr_shadowed_we & classa_clr_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classa_clr_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_clr_shadowed_re), + .we (classa_clr_shadowed_gated_we), + .wd (classa_clr_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (classa_clr_shadowed_flds_we[0]), + .q (reg2hw.classa_clr_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_clr_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_clr_shadowed_update_err), + .err_storage (classa_clr_shadowed_storage_err) + ); + assign reg2hw.classa_clr_shadowed.qe = classa_clr_shadowed_qe; + + + // R[classa_accum_cnt]: V(True) + prim_subreg_ext #( + .DW (16) + ) u_classa_accum_cnt ( + .re (classa_accum_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classa_accum_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classa_accum_cnt_qs) + ); + + + // R[classa_accum_thresh_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_accum_thresh_shadowed_gated_we; + assign classa_accum_thresh_shadowed_gated_we = classa_accum_thresh_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_classa_accum_thresh_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_accum_thresh_shadowed_re), + .we (classa_accum_thresh_shadowed_gated_we), + .wd (classa_accum_thresh_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_accum_thresh_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_accum_thresh_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_accum_thresh_shadowed_update_err), + .err_storage (classa_accum_thresh_shadowed_storage_err) + ); + + + // R[classa_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_timeout_cyc_shadowed_gated_we; + assign classa_timeout_cyc_shadowed_gated_we = classa_timeout_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_timeout_cyc_shadowed_re), + .we (classa_timeout_cyc_shadowed_gated_we), + .wd (classa_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_timeout_cyc_shadowed_update_err), + .err_storage (classa_timeout_cyc_shadowed_storage_err) + ); + + + // R[classa_crashdump_trigger_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_crashdump_trigger_shadowed_gated_we; + assign classa_crashdump_trigger_shadowed_gated_we = + classa_crashdump_trigger_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classa_crashdump_trigger_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_crashdump_trigger_shadowed_re), + .we (classa_crashdump_trigger_shadowed_gated_we), + .wd (classa_crashdump_trigger_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_crashdump_trigger_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_crashdump_trigger_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_crashdump_trigger_shadowed_update_err), + .err_storage (classa_crashdump_trigger_shadowed_storage_err) + ); + + + // R[classa_phase0_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_phase0_cyc_shadowed_gated_we; + assign classa_phase0_cyc_shadowed_gated_we = classa_phase0_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_phase0_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_phase0_cyc_shadowed_re), + .we (classa_phase0_cyc_shadowed_gated_we), + .wd (classa_phase0_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_phase0_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_phase0_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_phase0_cyc_shadowed_update_err), + .err_storage (classa_phase0_cyc_shadowed_storage_err) + ); + + + // R[classa_phase1_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_phase1_cyc_shadowed_gated_we; + assign classa_phase1_cyc_shadowed_gated_we = classa_phase1_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_phase1_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_phase1_cyc_shadowed_re), + .we (classa_phase1_cyc_shadowed_gated_we), + .wd (classa_phase1_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_phase1_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_phase1_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_phase1_cyc_shadowed_update_err), + .err_storage (classa_phase1_cyc_shadowed_storage_err) + ); + + + // R[classa_phase2_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_phase2_cyc_shadowed_gated_we; + assign classa_phase2_cyc_shadowed_gated_we = classa_phase2_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_phase2_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_phase2_cyc_shadowed_re), + .we (classa_phase2_cyc_shadowed_gated_we), + .wd (classa_phase2_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_phase2_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_phase2_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_phase2_cyc_shadowed_update_err), + .err_storage (classa_phase2_cyc_shadowed_storage_err) + ); + + + // R[classa_phase3_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classa_phase3_cyc_shadowed_gated_we; + assign classa_phase3_cyc_shadowed_gated_we = classa_phase3_cyc_shadowed_we & classa_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classa_phase3_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classa_phase3_cyc_shadowed_re), + .we (classa_phase3_cyc_shadowed_gated_we), + .wd (classa_phase3_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classa_phase3_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classa_phase3_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classa_phase3_cyc_shadowed_update_err), + .err_storage (classa_phase3_cyc_shadowed_storage_err) + ); + + + // R[classa_esc_cnt]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_classa_esc_cnt ( + .re (classa_esc_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classa_esc_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classa_esc_cnt_qs) + ); + + + // R[classa_state]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_classa_state ( + .re (classa_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classa_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classa_state_qs) + ); + + + // R[classb_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classb_regwen_we), + .wd (classb_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classb_regwen_qs) + ); + + + // R[classb_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_ctrl_shadowed_gated_we; + assign classb_ctrl_shadowed_gated_we = classb_ctrl_shadowed_we & classb_regwen_qs; + // F[en]: 0:0 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_update_err), + .err_storage (classb_ctrl_shadowed_en_storage_err) + ); + + // F[lock]: 1:1 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.lock.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_lock_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_lock_update_err), + .err_storage (classb_ctrl_shadowed_lock_storage_err) + ); + + // F[en_e0]: 2:2 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en_e0.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_e0_update_err), + .err_storage (classb_ctrl_shadowed_en_e0_storage_err) + ); + + // F[en_e1]: 3:3 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en_e1.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_e1_update_err), + .err_storage (classb_ctrl_shadowed_en_e1_storage_err) + ); + + // F[en_e2]: 4:4 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en_e2.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_e2_update_err), + .err_storage (classb_ctrl_shadowed_en_e2_storage_err) + ); + + // F[en_e3]: 5:5 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_en_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_en_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.en_e3.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_en_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_en_e3_update_err), + .err_storage (classb_ctrl_shadowed_en_e3_storage_err) + ); + + // F[map_e0]: 7:6 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_map_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_map_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.map_e0.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_map_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_map_e0_update_err), + .err_storage (classb_ctrl_shadowed_map_e0_storage_err) + ); + + // F[map_e1]: 9:8 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h1), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_map_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_map_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.map_e1.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_map_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_map_e1_update_err), + .err_storage (classb_ctrl_shadowed_map_e1_storage_err) + ); + + // F[map_e2]: 11:10 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_map_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_map_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.map_e2.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_map_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_map_e2_update_err), + .err_storage (classb_ctrl_shadowed_map_e2_storage_err) + ); + + // F[map_e3]: 13:12 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h3), + .Mubi (1'b0) + ) u_classb_ctrl_shadowed_map_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_ctrl_shadowed_re), + .we (classb_ctrl_shadowed_gated_we), + .wd (classb_ctrl_shadowed_map_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_ctrl_shadowed.map_e3.q), + .ds (), + + // to register interface (read) + .qs (classb_ctrl_shadowed_map_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_ctrl_shadowed_map_e3_update_err), + .err_storage (classb_ctrl_shadowed_map_e3_storage_err) + ); + + + // R[classb_clr_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classb_clr_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classb_clr_regwen_we), + .wd (classb_clr_regwen_wd), + + // from internal hardware + .de (hw2reg.classb_clr_regwen.de), + .d (hw2reg.classb_clr_regwen.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classb_clr_regwen_qs) + ); + + + // R[classb_clr_shadowed]: V(False) + logic classb_clr_shadowed_qe; + logic [0:0] classb_clr_shadowed_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_classb_clr_shadowed0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&classb_clr_shadowed_flds_we), + .q_o(classb_clr_shadowed_qe) + ); + // Create REGWEN-gated WE signal + logic classb_clr_shadowed_gated_we; + assign classb_clr_shadowed_gated_we = classb_clr_shadowed_we & classb_clr_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classb_clr_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_clr_shadowed_re), + .we (classb_clr_shadowed_gated_we), + .wd (classb_clr_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (classb_clr_shadowed_flds_we[0]), + .q (reg2hw.classb_clr_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_clr_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_clr_shadowed_update_err), + .err_storage (classb_clr_shadowed_storage_err) + ); + assign reg2hw.classb_clr_shadowed.qe = classb_clr_shadowed_qe; + + + // R[classb_accum_cnt]: V(True) + prim_subreg_ext #( + .DW (16) + ) u_classb_accum_cnt ( + .re (classb_accum_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classb_accum_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classb_accum_cnt_qs) + ); + + + // R[classb_accum_thresh_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_accum_thresh_shadowed_gated_we; + assign classb_accum_thresh_shadowed_gated_we = classb_accum_thresh_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_classb_accum_thresh_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_accum_thresh_shadowed_re), + .we (classb_accum_thresh_shadowed_gated_we), + .wd (classb_accum_thresh_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_accum_thresh_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_accum_thresh_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_accum_thresh_shadowed_update_err), + .err_storage (classb_accum_thresh_shadowed_storage_err) + ); + + + // R[classb_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_timeout_cyc_shadowed_gated_we; + assign classb_timeout_cyc_shadowed_gated_we = classb_timeout_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_timeout_cyc_shadowed_re), + .we (classb_timeout_cyc_shadowed_gated_we), + .wd (classb_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_timeout_cyc_shadowed_update_err), + .err_storage (classb_timeout_cyc_shadowed_storage_err) + ); + + + // R[classb_crashdump_trigger_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_crashdump_trigger_shadowed_gated_we; + assign classb_crashdump_trigger_shadowed_gated_we = + classb_crashdump_trigger_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classb_crashdump_trigger_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_crashdump_trigger_shadowed_re), + .we (classb_crashdump_trigger_shadowed_gated_we), + .wd (classb_crashdump_trigger_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_crashdump_trigger_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_crashdump_trigger_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_crashdump_trigger_shadowed_update_err), + .err_storage (classb_crashdump_trigger_shadowed_storage_err) + ); + + + // R[classb_phase0_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_phase0_cyc_shadowed_gated_we; + assign classb_phase0_cyc_shadowed_gated_we = classb_phase0_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_phase0_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_phase0_cyc_shadowed_re), + .we (classb_phase0_cyc_shadowed_gated_we), + .wd (classb_phase0_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_phase0_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_phase0_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_phase0_cyc_shadowed_update_err), + .err_storage (classb_phase0_cyc_shadowed_storage_err) + ); + + + // R[classb_phase1_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_phase1_cyc_shadowed_gated_we; + assign classb_phase1_cyc_shadowed_gated_we = classb_phase1_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_phase1_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_phase1_cyc_shadowed_re), + .we (classb_phase1_cyc_shadowed_gated_we), + .wd (classb_phase1_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_phase1_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_phase1_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_phase1_cyc_shadowed_update_err), + .err_storage (classb_phase1_cyc_shadowed_storage_err) + ); + + + // R[classb_phase2_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_phase2_cyc_shadowed_gated_we; + assign classb_phase2_cyc_shadowed_gated_we = classb_phase2_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_phase2_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_phase2_cyc_shadowed_re), + .we (classb_phase2_cyc_shadowed_gated_we), + .wd (classb_phase2_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_phase2_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_phase2_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_phase2_cyc_shadowed_update_err), + .err_storage (classb_phase2_cyc_shadowed_storage_err) + ); + + + // R[classb_phase3_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classb_phase3_cyc_shadowed_gated_we; + assign classb_phase3_cyc_shadowed_gated_we = classb_phase3_cyc_shadowed_we & classb_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classb_phase3_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classb_phase3_cyc_shadowed_re), + .we (classb_phase3_cyc_shadowed_gated_we), + .wd (classb_phase3_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classb_phase3_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classb_phase3_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classb_phase3_cyc_shadowed_update_err), + .err_storage (classb_phase3_cyc_shadowed_storage_err) + ); + + + // R[classb_esc_cnt]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_classb_esc_cnt ( + .re (classb_esc_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classb_esc_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classb_esc_cnt_qs) + ); + + + // R[classb_state]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_classb_state ( + .re (classb_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classb_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classb_state_qs) + ); + + + // R[classc_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classc_regwen_we), + .wd (classc_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classc_regwen_qs) + ); + + + // R[classc_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_ctrl_shadowed_gated_we; + assign classc_ctrl_shadowed_gated_we = classc_ctrl_shadowed_we & classc_regwen_qs; + // F[en]: 0:0 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_update_err), + .err_storage (classc_ctrl_shadowed_en_storage_err) + ); + + // F[lock]: 1:1 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.lock.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_lock_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_lock_update_err), + .err_storage (classc_ctrl_shadowed_lock_storage_err) + ); + + // F[en_e0]: 2:2 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en_e0.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_e0_update_err), + .err_storage (classc_ctrl_shadowed_en_e0_storage_err) + ); + + // F[en_e1]: 3:3 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en_e1.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_e1_update_err), + .err_storage (classc_ctrl_shadowed_en_e1_storage_err) + ); + + // F[en_e2]: 4:4 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en_e2.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_e2_update_err), + .err_storage (classc_ctrl_shadowed_en_e2_storage_err) + ); + + // F[en_e3]: 5:5 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_en_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_en_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.en_e3.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_en_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_en_e3_update_err), + .err_storage (classc_ctrl_shadowed_en_e3_storage_err) + ); + + // F[map_e0]: 7:6 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_map_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_map_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.map_e0.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_map_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_map_e0_update_err), + .err_storage (classc_ctrl_shadowed_map_e0_storage_err) + ); + + // F[map_e1]: 9:8 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h1), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_map_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_map_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.map_e1.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_map_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_map_e1_update_err), + .err_storage (classc_ctrl_shadowed_map_e1_storage_err) + ); + + // F[map_e2]: 11:10 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_map_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_map_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.map_e2.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_map_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_map_e2_update_err), + .err_storage (classc_ctrl_shadowed_map_e2_storage_err) + ); + + // F[map_e3]: 13:12 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h3), + .Mubi (1'b0) + ) u_classc_ctrl_shadowed_map_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_ctrl_shadowed_re), + .we (classc_ctrl_shadowed_gated_we), + .wd (classc_ctrl_shadowed_map_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_ctrl_shadowed.map_e3.q), + .ds (), + + // to register interface (read) + .qs (classc_ctrl_shadowed_map_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_ctrl_shadowed_map_e3_update_err), + .err_storage (classc_ctrl_shadowed_map_e3_storage_err) + ); + + + // R[classc_clr_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classc_clr_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classc_clr_regwen_we), + .wd (classc_clr_regwen_wd), + + // from internal hardware + .de (hw2reg.classc_clr_regwen.de), + .d (hw2reg.classc_clr_regwen.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classc_clr_regwen_qs) + ); + + + // R[classc_clr_shadowed]: V(False) + logic classc_clr_shadowed_qe; + logic [0:0] classc_clr_shadowed_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_classc_clr_shadowed0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&classc_clr_shadowed_flds_we), + .q_o(classc_clr_shadowed_qe) + ); + // Create REGWEN-gated WE signal + logic classc_clr_shadowed_gated_we; + assign classc_clr_shadowed_gated_we = classc_clr_shadowed_we & classc_clr_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classc_clr_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_clr_shadowed_re), + .we (classc_clr_shadowed_gated_we), + .wd (classc_clr_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (classc_clr_shadowed_flds_we[0]), + .q (reg2hw.classc_clr_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_clr_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_clr_shadowed_update_err), + .err_storage (classc_clr_shadowed_storage_err) + ); + assign reg2hw.classc_clr_shadowed.qe = classc_clr_shadowed_qe; + + + // R[classc_accum_cnt]: V(True) + prim_subreg_ext #( + .DW (16) + ) u_classc_accum_cnt ( + .re (classc_accum_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classc_accum_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classc_accum_cnt_qs) + ); + + + // R[classc_accum_thresh_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_accum_thresh_shadowed_gated_we; + assign classc_accum_thresh_shadowed_gated_we = classc_accum_thresh_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_classc_accum_thresh_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_accum_thresh_shadowed_re), + .we (classc_accum_thresh_shadowed_gated_we), + .wd (classc_accum_thresh_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_accum_thresh_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_accum_thresh_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_accum_thresh_shadowed_update_err), + .err_storage (classc_accum_thresh_shadowed_storage_err) + ); + + + // R[classc_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_timeout_cyc_shadowed_gated_we; + assign classc_timeout_cyc_shadowed_gated_we = classc_timeout_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_timeout_cyc_shadowed_re), + .we (classc_timeout_cyc_shadowed_gated_we), + .wd (classc_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_timeout_cyc_shadowed_update_err), + .err_storage (classc_timeout_cyc_shadowed_storage_err) + ); + + + // R[classc_crashdump_trigger_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_crashdump_trigger_shadowed_gated_we; + assign classc_crashdump_trigger_shadowed_gated_we = + classc_crashdump_trigger_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classc_crashdump_trigger_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_crashdump_trigger_shadowed_re), + .we (classc_crashdump_trigger_shadowed_gated_we), + .wd (classc_crashdump_trigger_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_crashdump_trigger_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_crashdump_trigger_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_crashdump_trigger_shadowed_update_err), + .err_storage (classc_crashdump_trigger_shadowed_storage_err) + ); + + + // R[classc_phase0_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_phase0_cyc_shadowed_gated_we; + assign classc_phase0_cyc_shadowed_gated_we = classc_phase0_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_phase0_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_phase0_cyc_shadowed_re), + .we (classc_phase0_cyc_shadowed_gated_we), + .wd (classc_phase0_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_phase0_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_phase0_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_phase0_cyc_shadowed_update_err), + .err_storage (classc_phase0_cyc_shadowed_storage_err) + ); + + + // R[classc_phase1_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_phase1_cyc_shadowed_gated_we; + assign classc_phase1_cyc_shadowed_gated_we = classc_phase1_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_phase1_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_phase1_cyc_shadowed_re), + .we (classc_phase1_cyc_shadowed_gated_we), + .wd (classc_phase1_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_phase1_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_phase1_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_phase1_cyc_shadowed_update_err), + .err_storage (classc_phase1_cyc_shadowed_storage_err) + ); + + + // R[classc_phase2_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_phase2_cyc_shadowed_gated_we; + assign classc_phase2_cyc_shadowed_gated_we = classc_phase2_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_phase2_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_phase2_cyc_shadowed_re), + .we (classc_phase2_cyc_shadowed_gated_we), + .wd (classc_phase2_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_phase2_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_phase2_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_phase2_cyc_shadowed_update_err), + .err_storage (classc_phase2_cyc_shadowed_storage_err) + ); + + + // R[classc_phase3_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classc_phase3_cyc_shadowed_gated_we; + assign classc_phase3_cyc_shadowed_gated_we = classc_phase3_cyc_shadowed_we & classc_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classc_phase3_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classc_phase3_cyc_shadowed_re), + .we (classc_phase3_cyc_shadowed_gated_we), + .wd (classc_phase3_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classc_phase3_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classc_phase3_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classc_phase3_cyc_shadowed_update_err), + .err_storage (classc_phase3_cyc_shadowed_storage_err) + ); + + + // R[classc_esc_cnt]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_classc_esc_cnt ( + .re (classc_esc_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classc_esc_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classc_esc_cnt_qs) + ); + + + // R[classc_state]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_classc_state ( + .re (classc_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classc_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classc_state_qs) + ); + + + // R[classd_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classd_regwen_we), + .wd (classd_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classd_regwen_qs) + ); + + + // R[classd_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_ctrl_shadowed_gated_we; + assign classd_ctrl_shadowed_gated_we = classd_ctrl_shadowed_we & classd_regwen_qs; + // F[en]: 0:0 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_update_err), + .err_storage (classd_ctrl_shadowed_en_storage_err) + ); + + // F[lock]: 1:1 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.lock.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_lock_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_lock_update_err), + .err_storage (classd_ctrl_shadowed_lock_storage_err) + ); + + // F[en_e0]: 2:2 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en_e0.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_e0_update_err), + .err_storage (classd_ctrl_shadowed_en_e0_storage_err) + ); + + // F[en_e1]: 3:3 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en_e1.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_e1_update_err), + .err_storage (classd_ctrl_shadowed_en_e1_storage_err) + ); + + // F[en_e2]: 4:4 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en_e2.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_e2_update_err), + .err_storage (classd_ctrl_shadowed_en_e2_storage_err) + ); + + // F[en_e3]: 5:5 + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_en_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_en_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.en_e3.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_en_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_en_e3_update_err), + .err_storage (classd_ctrl_shadowed_en_e3_storage_err) + ); + + // F[map_e0]: 7:6 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_map_e0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_map_e0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.map_e0.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_map_e0_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_map_e0_update_err), + .err_storage (classd_ctrl_shadowed_map_e0_storage_err) + ); + + // F[map_e1]: 9:8 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h1), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_map_e1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_map_e1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.map_e1.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_map_e1_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_map_e1_update_err), + .err_storage (classd_ctrl_shadowed_map_e1_storage_err) + ); + + // F[map_e2]: 11:10 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_map_e2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_map_e2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.map_e2.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_map_e2_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_map_e2_update_err), + .err_storage (classd_ctrl_shadowed_map_e2_storage_err) + ); + + // F[map_e3]: 13:12 + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h3), + .Mubi (1'b0) + ) u_classd_ctrl_shadowed_map_e3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_ctrl_shadowed_re), + .we (classd_ctrl_shadowed_gated_we), + .wd (classd_ctrl_shadowed_map_e3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_ctrl_shadowed.map_e3.q), + .ds (), + + // to register interface (read) + .qs (classd_ctrl_shadowed_map_e3_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_ctrl_shadowed_map_e3_update_err), + .err_storage (classd_ctrl_shadowed_map_e3_storage_err) + ); + + + // R[classd_clr_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_classd_clr_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (classd_clr_regwen_we), + .wd (classd_clr_regwen_wd), + + // from internal hardware + .de (hw2reg.classd_clr_regwen.de), + .d (hw2reg.classd_clr_regwen.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (classd_clr_regwen_qs) + ); + + + // R[classd_clr_shadowed]: V(False) + logic classd_clr_shadowed_qe; + logic [0:0] classd_clr_shadowed_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_classd_clr_shadowed0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&classd_clr_shadowed_flds_we), + .q_o(classd_clr_shadowed_qe) + ); + // Create REGWEN-gated WE signal + logic classd_clr_shadowed_gated_we; + assign classd_clr_shadowed_gated_we = classd_clr_shadowed_we & classd_clr_regwen_qs; + prim_subreg_shadow #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_classd_clr_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_clr_shadowed_re), + .we (classd_clr_shadowed_gated_we), + .wd (classd_clr_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (classd_clr_shadowed_flds_we[0]), + .q (reg2hw.classd_clr_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_clr_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_clr_shadowed_update_err), + .err_storage (classd_clr_shadowed_storage_err) + ); + assign reg2hw.classd_clr_shadowed.qe = classd_clr_shadowed_qe; + + + // R[classd_accum_cnt]: V(True) + prim_subreg_ext #( + .DW (16) + ) u_classd_accum_cnt ( + .re (classd_accum_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classd_accum_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classd_accum_cnt_qs) + ); + + + // R[classd_accum_thresh_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_accum_thresh_shadowed_gated_we; + assign classd_accum_thresh_shadowed_gated_we = classd_accum_thresh_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h0), + .Mubi (1'b0) + ) u_classd_accum_thresh_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_accum_thresh_shadowed_re), + .we (classd_accum_thresh_shadowed_gated_we), + .wd (classd_accum_thresh_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_accum_thresh_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_accum_thresh_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_accum_thresh_shadowed_update_err), + .err_storage (classd_accum_thresh_shadowed_storage_err) + ); + + + // R[classd_timeout_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_timeout_cyc_shadowed_gated_we; + assign classd_timeout_cyc_shadowed_gated_we = classd_timeout_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_timeout_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_timeout_cyc_shadowed_re), + .we (classd_timeout_cyc_shadowed_gated_we), + .wd (classd_timeout_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_timeout_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_timeout_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_timeout_cyc_shadowed_update_err), + .err_storage (classd_timeout_cyc_shadowed_storage_err) + ); + + + // R[classd_crashdump_trigger_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_crashdump_trigger_shadowed_gated_we; + assign classd_crashdump_trigger_shadowed_gated_we = + classd_crashdump_trigger_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_classd_crashdump_trigger_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_crashdump_trigger_shadowed_re), + .we (classd_crashdump_trigger_shadowed_gated_we), + .wd (classd_crashdump_trigger_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_crashdump_trigger_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_crashdump_trigger_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_crashdump_trigger_shadowed_update_err), + .err_storage (classd_crashdump_trigger_shadowed_storage_err) + ); + + + // R[classd_phase0_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_phase0_cyc_shadowed_gated_we; + assign classd_phase0_cyc_shadowed_gated_we = classd_phase0_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_phase0_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_phase0_cyc_shadowed_re), + .we (classd_phase0_cyc_shadowed_gated_we), + .wd (classd_phase0_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_phase0_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_phase0_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_phase0_cyc_shadowed_update_err), + .err_storage (classd_phase0_cyc_shadowed_storage_err) + ); + + + // R[classd_phase1_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_phase1_cyc_shadowed_gated_we; + assign classd_phase1_cyc_shadowed_gated_we = classd_phase1_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_phase1_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_phase1_cyc_shadowed_re), + .we (classd_phase1_cyc_shadowed_gated_we), + .wd (classd_phase1_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_phase1_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_phase1_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_phase1_cyc_shadowed_update_err), + .err_storage (classd_phase1_cyc_shadowed_storage_err) + ); + + + // R[classd_phase2_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_phase2_cyc_shadowed_gated_we; + assign classd_phase2_cyc_shadowed_gated_we = classd_phase2_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_phase2_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_phase2_cyc_shadowed_re), + .we (classd_phase2_cyc_shadowed_gated_we), + .wd (classd_phase2_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_phase2_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_phase2_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_phase2_cyc_shadowed_update_err), + .err_storage (classd_phase2_cyc_shadowed_storage_err) + ); + + + // R[classd_phase3_cyc_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic classd_phase3_cyc_shadowed_gated_we; + assign classd_phase3_cyc_shadowed_gated_we = classd_phase3_cyc_shadowed_we & classd_regwen_qs; + prim_subreg_shadow #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_classd_phase3_cyc_shadowed ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (classd_phase3_cyc_shadowed_re), + .we (classd_phase3_cyc_shadowed_gated_we), + .wd (classd_phase3_cyc_shadowed_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.classd_phase3_cyc_shadowed.q), + .ds (), + + // to register interface (read) + .qs (classd_phase3_cyc_shadowed_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (classd_phase3_cyc_shadowed_update_err), + .err_storage (classd_phase3_cyc_shadowed_storage_err) + ); + + + // R[classd_esc_cnt]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_classd_esc_cnt ( + .re (classd_esc_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classd_esc_cnt.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classd_esc_cnt_qs) + ); + + + // R[classd_state]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_classd_state ( + .re (classd_state_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.classd_state.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (classd_state_qs) + ); + + + + logic [485:0] addr_hit; + always_comb begin + addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == ALERT_HANDLER_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET); + addr_hit[ 4] = (reg_addr == ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[ 5] = (reg_addr == ALERT_HANDLER_PING_TIMER_EN_SHADOWED_OFFSET); + addr_hit[ 6] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_0_OFFSET); + addr_hit[ 7] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_1_OFFSET); + addr_hit[ 8] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_2_OFFSET); + addr_hit[ 9] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_3_OFFSET); + addr_hit[ 10] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_4_OFFSET); + addr_hit[ 11] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_5_OFFSET); + addr_hit[ 12] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_6_OFFSET); + addr_hit[ 13] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_7_OFFSET); + addr_hit[ 14] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_8_OFFSET); + addr_hit[ 15] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_9_OFFSET); + addr_hit[ 16] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_10_OFFSET); + addr_hit[ 17] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_11_OFFSET); + addr_hit[ 18] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_12_OFFSET); + addr_hit[ 19] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_13_OFFSET); + addr_hit[ 20] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_14_OFFSET); + addr_hit[ 21] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_15_OFFSET); + addr_hit[ 22] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_16_OFFSET); + addr_hit[ 23] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_17_OFFSET); + addr_hit[ 24] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_18_OFFSET); + addr_hit[ 25] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_19_OFFSET); + addr_hit[ 26] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_20_OFFSET); + addr_hit[ 27] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_21_OFFSET); + addr_hit[ 28] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_22_OFFSET); + addr_hit[ 29] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_23_OFFSET); + addr_hit[ 30] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_24_OFFSET); + addr_hit[ 31] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_25_OFFSET); + addr_hit[ 32] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_26_OFFSET); + addr_hit[ 33] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_27_OFFSET); + addr_hit[ 34] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_28_OFFSET); + addr_hit[ 35] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_29_OFFSET); + addr_hit[ 36] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_30_OFFSET); + addr_hit[ 37] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_31_OFFSET); + addr_hit[ 38] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_32_OFFSET); + addr_hit[ 39] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_33_OFFSET); + addr_hit[ 40] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_34_OFFSET); + addr_hit[ 41] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_35_OFFSET); + addr_hit[ 42] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_36_OFFSET); + addr_hit[ 43] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_37_OFFSET); + addr_hit[ 44] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_38_OFFSET); + addr_hit[ 45] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_39_OFFSET); + addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_40_OFFSET); + addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_41_OFFSET); + addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_42_OFFSET); + addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_43_OFFSET); + addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_44_OFFSET); + addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_45_OFFSET); + addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_46_OFFSET); + addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_47_OFFSET); + addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_48_OFFSET); + addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_49_OFFSET); + addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_50_OFFSET); + addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_51_OFFSET); + addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_52_OFFSET); + addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_53_OFFSET); + addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_54_OFFSET); + addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_55_OFFSET); + addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_56_OFFSET); + addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_57_OFFSET); + addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_58_OFFSET); + addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_59_OFFSET); + addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_60_OFFSET); + addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_61_OFFSET); + addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_62_OFFSET); + addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET); + addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET); + addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_65_OFFSET); + addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_66_OFFSET); + addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_67_OFFSET); + addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_68_OFFSET); + addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_69_OFFSET); + addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_70_OFFSET); + addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_71_OFFSET); + addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_72_OFFSET); + addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_73_OFFSET); + addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_74_OFFSET); + addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_75_OFFSET); + addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_76_OFFSET); + addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_77_OFFSET); + addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_78_OFFSET); + addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_79_OFFSET); + addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_80_OFFSET); + addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_81_OFFSET); + addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_82_OFFSET); + addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_83_OFFSET); + addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_84_OFFSET); + addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_85_OFFSET); + addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_86_OFFSET); + addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_87_OFFSET); + addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_88_OFFSET); + addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_89_OFFSET); + addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_90_OFFSET); + addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_91_OFFSET); + addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_92_OFFSET); + addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_93_OFFSET); + addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_94_OFFSET); + addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_95_OFFSET); + addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_96_OFFSET); + addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_97_OFFSET); + addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_98_OFFSET); + addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET); + addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET); + addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET); + addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET); + addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET); + addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET); + addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET); + addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET); + addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET); + addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET); + addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET); + addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET); + addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET); + addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET); + addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET); + addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET); + addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET); + addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET); + addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET); + addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET); + addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET); + addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET); + addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET); + addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET); + addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET); + addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET); + addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET); + addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET); + addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET); + addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET); + addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET); + addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET); + addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET); + addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET); + addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET); + addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET); + addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET); + addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET); + addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET); + addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET); + addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET); + addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET); + addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET); + addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET); + addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET); + addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET); + addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET); + addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET); + addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET); + addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET); + addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET); + addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET); + addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET); + addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET); + addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET); + addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET); + addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET); + addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET); + addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_65_OFFSET); + addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_66_OFFSET); + addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_67_OFFSET); + addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_68_OFFSET); + addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_69_OFFSET); + addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_70_OFFSET); + addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_71_OFFSET); + addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_72_OFFSET); + addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_73_OFFSET); + addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_74_OFFSET); + addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_75_OFFSET); + addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_76_OFFSET); + addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_77_OFFSET); + addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_78_OFFSET); + addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_79_OFFSET); + addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_80_OFFSET); + addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_81_OFFSET); + addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_82_OFFSET); + addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_83_OFFSET); + addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_84_OFFSET); + addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_85_OFFSET); + addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_86_OFFSET); + addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_87_OFFSET); + addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_88_OFFSET); + addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_89_OFFSET); + addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_90_OFFSET); + addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_91_OFFSET); + addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_92_OFFSET); + addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_93_OFFSET); + addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_94_OFFSET); + addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_95_OFFSET); + addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_96_OFFSET); + addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_97_OFFSET); + addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_98_OFFSET); + addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET); + addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET); + addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET); + addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET); + addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET); + addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET); + addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET); + addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET); + addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET); + addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET); + addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET); + addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET); + addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET); + addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET); + addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET); + addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET); + addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET); + addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET); + addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET); + addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET); + addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET); + addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET); + addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET); + addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET); + addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET); + addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET); + addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET); + addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET); + addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET); + addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET); + addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET); + addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET); + addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET); + addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET); + addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET); + addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET); + addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET); + addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET); + addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET); + addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET); + addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET); + addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET); + addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET); + addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET); + addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET); + addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET); + addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET); + addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET); + addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET); + addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET); + addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET); + addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET); + addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET); + addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET); + addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET); + addr_hit[266] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET); + addr_hit[267] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET); + addr_hit[268] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET); + addr_hit[269] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_65_OFFSET); + addr_hit[270] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_66_OFFSET); + addr_hit[271] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_67_OFFSET); + addr_hit[272] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_68_OFFSET); + addr_hit[273] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_69_OFFSET); + addr_hit[274] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_70_OFFSET); + addr_hit[275] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_71_OFFSET); + addr_hit[276] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_72_OFFSET); + addr_hit[277] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_73_OFFSET); + addr_hit[278] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_74_OFFSET); + addr_hit[279] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_75_OFFSET); + addr_hit[280] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_76_OFFSET); + addr_hit[281] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_77_OFFSET); + addr_hit[282] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_78_OFFSET); + addr_hit[283] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_79_OFFSET); + addr_hit[284] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_80_OFFSET); + addr_hit[285] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_81_OFFSET); + addr_hit[286] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_82_OFFSET); + addr_hit[287] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_83_OFFSET); + addr_hit[288] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_84_OFFSET); + addr_hit[289] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_85_OFFSET); + addr_hit[290] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_86_OFFSET); + addr_hit[291] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_87_OFFSET); + addr_hit[292] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_88_OFFSET); + addr_hit[293] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_89_OFFSET); + addr_hit[294] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_90_OFFSET); + addr_hit[295] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_91_OFFSET); + addr_hit[296] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_92_OFFSET); + addr_hit[297] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_93_OFFSET); + addr_hit[298] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_94_OFFSET); + addr_hit[299] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_95_OFFSET); + addr_hit[300] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_96_OFFSET); + addr_hit[301] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_97_OFFSET); + addr_hit[302] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_98_OFFSET); + addr_hit[303] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET); + addr_hit[304] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET); + addr_hit[305] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET); + addr_hit[306] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET); + addr_hit[307] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET); + addr_hit[308] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET); + addr_hit[309] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET); + addr_hit[310] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET); + addr_hit[311] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET); + addr_hit[312] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET); + addr_hit[313] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET); + addr_hit[314] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET); + addr_hit[315] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET); + addr_hit[316] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET); + addr_hit[317] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET); + addr_hit[318] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET); + addr_hit[319] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET); + addr_hit[320] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET); + addr_hit[321] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET); + addr_hit[322] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET); + addr_hit[323] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET); + addr_hit[324] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET); + addr_hit[325] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET); + addr_hit[326] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET); + addr_hit[327] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET); + addr_hit[328] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET); + addr_hit[329] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET); + addr_hit[330] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET); + addr_hit[331] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET); + addr_hit[332] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET); + addr_hit[333] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET); + addr_hit[334] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET); + addr_hit[335] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET); + addr_hit[336] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET); + addr_hit[337] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET); + addr_hit[338] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET); + addr_hit[339] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET); + addr_hit[340] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET); + addr_hit[341] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET); + addr_hit[342] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET); + addr_hit[343] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET); + addr_hit[344] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET); + addr_hit[345] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET); + addr_hit[346] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET); + addr_hit[347] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET); + addr_hit[348] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET); + addr_hit[349] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET); + addr_hit[350] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET); + addr_hit[351] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET); + addr_hit[352] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET); + addr_hit[353] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET); + addr_hit[354] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET); + addr_hit[355] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET); + addr_hit[356] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET); + addr_hit[357] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET); + addr_hit[358] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET); + addr_hit[359] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET); + addr_hit[360] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET); + addr_hit[361] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET); + addr_hit[362] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET); + addr_hit[363] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET); + addr_hit[364] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET); + addr_hit[365] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET); + addr_hit[366] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET); + addr_hit[367] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET); + addr_hit[368] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_65_OFFSET); + addr_hit[369] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_66_OFFSET); + addr_hit[370] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_67_OFFSET); + addr_hit[371] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_68_OFFSET); + addr_hit[372] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_69_OFFSET); + addr_hit[373] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_70_OFFSET); + addr_hit[374] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_71_OFFSET); + addr_hit[375] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_72_OFFSET); + addr_hit[376] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_73_OFFSET); + addr_hit[377] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_74_OFFSET); + addr_hit[378] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_75_OFFSET); + addr_hit[379] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_76_OFFSET); + addr_hit[380] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_77_OFFSET); + addr_hit[381] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_78_OFFSET); + addr_hit[382] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_79_OFFSET); + addr_hit[383] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_80_OFFSET); + addr_hit[384] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_81_OFFSET); + addr_hit[385] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_82_OFFSET); + addr_hit[386] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_83_OFFSET); + addr_hit[387] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_84_OFFSET); + addr_hit[388] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_85_OFFSET); + addr_hit[389] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_86_OFFSET); + addr_hit[390] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_87_OFFSET); + addr_hit[391] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_88_OFFSET); + addr_hit[392] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_89_OFFSET); + addr_hit[393] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_90_OFFSET); + addr_hit[394] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_91_OFFSET); + addr_hit[395] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_92_OFFSET); + addr_hit[396] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_93_OFFSET); + addr_hit[397] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_94_OFFSET); + addr_hit[398] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_95_OFFSET); + addr_hit[399] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_96_OFFSET); + addr_hit[400] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_97_OFFSET); + addr_hit[401] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_98_OFFSET); + addr_hit[402] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET); + addr_hit[403] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET); + addr_hit[404] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET); + addr_hit[405] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET); + addr_hit[406] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET); + addr_hit[407] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET); + addr_hit[408] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET); + addr_hit[409] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET); + addr_hit[410] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET); + addr_hit[411] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET); + addr_hit[412] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET); + addr_hit[413] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET); + addr_hit[414] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET); + addr_hit[415] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET); + addr_hit[416] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET); + addr_hit[417] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET); + addr_hit[418] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET); + addr_hit[419] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET); + addr_hit[420] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET); + addr_hit[421] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET); + addr_hit[422] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET); + addr_hit[423] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET); + addr_hit[424] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET); + addr_hit[425] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET); + addr_hit[426] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET); + addr_hit[427] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET); + addr_hit[428] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET); + addr_hit[429] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET); + addr_hit[430] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET); + addr_hit[431] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET); + addr_hit[432] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET); + addr_hit[433] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET); + addr_hit[434] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET); + addr_hit[435] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[436] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[437] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[438] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[439] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[440] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[441] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[442] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET); + addr_hit[443] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET); + addr_hit[444] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET); + addr_hit[445] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET); + addr_hit[446] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET); + addr_hit[447] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET); + addr_hit[448] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET); + addr_hit[449] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[450] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[451] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[452] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[453] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[454] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[455] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[456] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET); + addr_hit[457] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET); + addr_hit[458] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET); + addr_hit[459] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET); + addr_hit[460] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET); + addr_hit[461] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET); + addr_hit[462] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET); + addr_hit[463] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[464] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[465] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[466] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[467] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[468] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[469] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[470] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET); + addr_hit[471] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET); + addr_hit[472] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET); + addr_hit[473] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET); + addr_hit[474] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET); + addr_hit[475] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET); + addr_hit[476] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET); + addr_hit[477] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET); + addr_hit[478] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET); + addr_hit[479] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET); + addr_hit[480] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET); + addr_hit[481] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET); + addr_hit[482] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET); + addr_hit[483] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET); + addr_hit[484] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET); + addr_hit[485] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(ALERT_HANDLER_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(ALERT_HANDLER_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(ALERT_HANDLER_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(ALERT_HANDLER_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(ALERT_HANDLER_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(ALERT_HANDLER_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(ALERT_HANDLER_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(ALERT_HANDLER_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(ALERT_HANDLER_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(ALERT_HANDLER_PERMIT[ 9] & ~reg_be))) | + (addr_hit[ 10] & (|(ALERT_HANDLER_PERMIT[ 10] & ~reg_be))) | + (addr_hit[ 11] & (|(ALERT_HANDLER_PERMIT[ 11] & ~reg_be))) | + (addr_hit[ 12] & (|(ALERT_HANDLER_PERMIT[ 12] & ~reg_be))) | + (addr_hit[ 13] & (|(ALERT_HANDLER_PERMIT[ 13] & ~reg_be))) | + (addr_hit[ 14] & (|(ALERT_HANDLER_PERMIT[ 14] & ~reg_be))) | + (addr_hit[ 15] & (|(ALERT_HANDLER_PERMIT[ 15] & ~reg_be))) | + (addr_hit[ 16] & (|(ALERT_HANDLER_PERMIT[ 16] & ~reg_be))) | + (addr_hit[ 17] & (|(ALERT_HANDLER_PERMIT[ 17] & ~reg_be))) | + (addr_hit[ 18] & (|(ALERT_HANDLER_PERMIT[ 18] & ~reg_be))) | + (addr_hit[ 19] & (|(ALERT_HANDLER_PERMIT[ 19] & ~reg_be))) | + (addr_hit[ 20] & (|(ALERT_HANDLER_PERMIT[ 20] & ~reg_be))) | + (addr_hit[ 21] & (|(ALERT_HANDLER_PERMIT[ 21] & ~reg_be))) | + (addr_hit[ 22] & (|(ALERT_HANDLER_PERMIT[ 22] & ~reg_be))) | + (addr_hit[ 23] & (|(ALERT_HANDLER_PERMIT[ 23] & ~reg_be))) | + (addr_hit[ 24] & (|(ALERT_HANDLER_PERMIT[ 24] & ~reg_be))) | + (addr_hit[ 25] & (|(ALERT_HANDLER_PERMIT[ 25] & ~reg_be))) | + (addr_hit[ 26] & (|(ALERT_HANDLER_PERMIT[ 26] & ~reg_be))) | + (addr_hit[ 27] & (|(ALERT_HANDLER_PERMIT[ 27] & ~reg_be))) | + (addr_hit[ 28] & (|(ALERT_HANDLER_PERMIT[ 28] & ~reg_be))) | + (addr_hit[ 29] & (|(ALERT_HANDLER_PERMIT[ 29] & ~reg_be))) | + (addr_hit[ 30] & (|(ALERT_HANDLER_PERMIT[ 30] & ~reg_be))) | + (addr_hit[ 31] & (|(ALERT_HANDLER_PERMIT[ 31] & ~reg_be))) | + (addr_hit[ 32] & (|(ALERT_HANDLER_PERMIT[ 32] & ~reg_be))) | + (addr_hit[ 33] & (|(ALERT_HANDLER_PERMIT[ 33] & ~reg_be))) | + (addr_hit[ 34] & (|(ALERT_HANDLER_PERMIT[ 34] & ~reg_be))) | + (addr_hit[ 35] & (|(ALERT_HANDLER_PERMIT[ 35] & ~reg_be))) | + (addr_hit[ 36] & (|(ALERT_HANDLER_PERMIT[ 36] & ~reg_be))) | + (addr_hit[ 37] & (|(ALERT_HANDLER_PERMIT[ 37] & ~reg_be))) | + (addr_hit[ 38] & (|(ALERT_HANDLER_PERMIT[ 38] & ~reg_be))) | + (addr_hit[ 39] & (|(ALERT_HANDLER_PERMIT[ 39] & ~reg_be))) | + (addr_hit[ 40] & (|(ALERT_HANDLER_PERMIT[ 40] & ~reg_be))) | + (addr_hit[ 41] & (|(ALERT_HANDLER_PERMIT[ 41] & ~reg_be))) | + (addr_hit[ 42] & (|(ALERT_HANDLER_PERMIT[ 42] & ~reg_be))) | + (addr_hit[ 43] & (|(ALERT_HANDLER_PERMIT[ 43] & ~reg_be))) | + (addr_hit[ 44] & (|(ALERT_HANDLER_PERMIT[ 44] & ~reg_be))) | + (addr_hit[ 45] & (|(ALERT_HANDLER_PERMIT[ 45] & ~reg_be))) | + (addr_hit[ 46] & (|(ALERT_HANDLER_PERMIT[ 46] & ~reg_be))) | + (addr_hit[ 47] & (|(ALERT_HANDLER_PERMIT[ 47] & ~reg_be))) | + (addr_hit[ 48] & (|(ALERT_HANDLER_PERMIT[ 48] & ~reg_be))) | + (addr_hit[ 49] & (|(ALERT_HANDLER_PERMIT[ 49] & ~reg_be))) | + (addr_hit[ 50] & (|(ALERT_HANDLER_PERMIT[ 50] & ~reg_be))) | + (addr_hit[ 51] & (|(ALERT_HANDLER_PERMIT[ 51] & ~reg_be))) | + (addr_hit[ 52] & (|(ALERT_HANDLER_PERMIT[ 52] & ~reg_be))) | + (addr_hit[ 53] & (|(ALERT_HANDLER_PERMIT[ 53] & ~reg_be))) | + (addr_hit[ 54] & (|(ALERT_HANDLER_PERMIT[ 54] & ~reg_be))) | + (addr_hit[ 55] & (|(ALERT_HANDLER_PERMIT[ 55] & ~reg_be))) | + (addr_hit[ 56] & (|(ALERT_HANDLER_PERMIT[ 56] & ~reg_be))) | + (addr_hit[ 57] & (|(ALERT_HANDLER_PERMIT[ 57] & ~reg_be))) | + (addr_hit[ 58] & (|(ALERT_HANDLER_PERMIT[ 58] & ~reg_be))) | + (addr_hit[ 59] & (|(ALERT_HANDLER_PERMIT[ 59] & ~reg_be))) | + (addr_hit[ 60] & (|(ALERT_HANDLER_PERMIT[ 60] & ~reg_be))) | + (addr_hit[ 61] & (|(ALERT_HANDLER_PERMIT[ 61] & ~reg_be))) | + (addr_hit[ 62] & (|(ALERT_HANDLER_PERMIT[ 62] & ~reg_be))) | + (addr_hit[ 63] & (|(ALERT_HANDLER_PERMIT[ 63] & ~reg_be))) | + (addr_hit[ 64] & (|(ALERT_HANDLER_PERMIT[ 64] & ~reg_be))) | + (addr_hit[ 65] & (|(ALERT_HANDLER_PERMIT[ 65] & ~reg_be))) | + (addr_hit[ 66] & (|(ALERT_HANDLER_PERMIT[ 66] & ~reg_be))) | + (addr_hit[ 67] & (|(ALERT_HANDLER_PERMIT[ 67] & ~reg_be))) | + (addr_hit[ 68] & (|(ALERT_HANDLER_PERMIT[ 68] & ~reg_be))) | + (addr_hit[ 69] & (|(ALERT_HANDLER_PERMIT[ 69] & ~reg_be))) | + (addr_hit[ 70] & (|(ALERT_HANDLER_PERMIT[ 70] & ~reg_be))) | + (addr_hit[ 71] & (|(ALERT_HANDLER_PERMIT[ 71] & ~reg_be))) | + (addr_hit[ 72] & (|(ALERT_HANDLER_PERMIT[ 72] & ~reg_be))) | + (addr_hit[ 73] & (|(ALERT_HANDLER_PERMIT[ 73] & ~reg_be))) | + (addr_hit[ 74] & (|(ALERT_HANDLER_PERMIT[ 74] & ~reg_be))) | + (addr_hit[ 75] & (|(ALERT_HANDLER_PERMIT[ 75] & ~reg_be))) | + (addr_hit[ 76] & (|(ALERT_HANDLER_PERMIT[ 76] & ~reg_be))) | + (addr_hit[ 77] & (|(ALERT_HANDLER_PERMIT[ 77] & ~reg_be))) | + (addr_hit[ 78] & (|(ALERT_HANDLER_PERMIT[ 78] & ~reg_be))) | + (addr_hit[ 79] & (|(ALERT_HANDLER_PERMIT[ 79] & ~reg_be))) | + (addr_hit[ 80] & (|(ALERT_HANDLER_PERMIT[ 80] & ~reg_be))) | + (addr_hit[ 81] & (|(ALERT_HANDLER_PERMIT[ 81] & ~reg_be))) | + (addr_hit[ 82] & (|(ALERT_HANDLER_PERMIT[ 82] & ~reg_be))) | + (addr_hit[ 83] & (|(ALERT_HANDLER_PERMIT[ 83] & ~reg_be))) | + (addr_hit[ 84] & (|(ALERT_HANDLER_PERMIT[ 84] & ~reg_be))) | + (addr_hit[ 85] & (|(ALERT_HANDLER_PERMIT[ 85] & ~reg_be))) | + (addr_hit[ 86] & (|(ALERT_HANDLER_PERMIT[ 86] & ~reg_be))) | + (addr_hit[ 87] & (|(ALERT_HANDLER_PERMIT[ 87] & ~reg_be))) | + (addr_hit[ 88] & (|(ALERT_HANDLER_PERMIT[ 88] & ~reg_be))) | + (addr_hit[ 89] & (|(ALERT_HANDLER_PERMIT[ 89] & ~reg_be))) | + (addr_hit[ 90] & (|(ALERT_HANDLER_PERMIT[ 90] & ~reg_be))) | + (addr_hit[ 91] & (|(ALERT_HANDLER_PERMIT[ 91] & ~reg_be))) | + (addr_hit[ 92] & (|(ALERT_HANDLER_PERMIT[ 92] & ~reg_be))) | + (addr_hit[ 93] & (|(ALERT_HANDLER_PERMIT[ 93] & ~reg_be))) | + (addr_hit[ 94] & (|(ALERT_HANDLER_PERMIT[ 94] & ~reg_be))) | + (addr_hit[ 95] & (|(ALERT_HANDLER_PERMIT[ 95] & ~reg_be))) | + (addr_hit[ 96] & (|(ALERT_HANDLER_PERMIT[ 96] & ~reg_be))) | + (addr_hit[ 97] & (|(ALERT_HANDLER_PERMIT[ 97] & ~reg_be))) | + (addr_hit[ 98] & (|(ALERT_HANDLER_PERMIT[ 98] & ~reg_be))) | + (addr_hit[ 99] & (|(ALERT_HANDLER_PERMIT[ 99] & ~reg_be))) | + (addr_hit[100] & (|(ALERT_HANDLER_PERMIT[100] & ~reg_be))) | + (addr_hit[101] & (|(ALERT_HANDLER_PERMIT[101] & ~reg_be))) | + (addr_hit[102] & (|(ALERT_HANDLER_PERMIT[102] & ~reg_be))) | + (addr_hit[103] & (|(ALERT_HANDLER_PERMIT[103] & ~reg_be))) | + (addr_hit[104] & (|(ALERT_HANDLER_PERMIT[104] & ~reg_be))) | + (addr_hit[105] & (|(ALERT_HANDLER_PERMIT[105] & ~reg_be))) | + (addr_hit[106] & (|(ALERT_HANDLER_PERMIT[106] & ~reg_be))) | + (addr_hit[107] & (|(ALERT_HANDLER_PERMIT[107] & ~reg_be))) | + (addr_hit[108] & (|(ALERT_HANDLER_PERMIT[108] & ~reg_be))) | + (addr_hit[109] & (|(ALERT_HANDLER_PERMIT[109] & ~reg_be))) | + (addr_hit[110] & (|(ALERT_HANDLER_PERMIT[110] & ~reg_be))) | + (addr_hit[111] & (|(ALERT_HANDLER_PERMIT[111] & ~reg_be))) | + (addr_hit[112] & (|(ALERT_HANDLER_PERMIT[112] & ~reg_be))) | + (addr_hit[113] & (|(ALERT_HANDLER_PERMIT[113] & ~reg_be))) | + (addr_hit[114] & (|(ALERT_HANDLER_PERMIT[114] & ~reg_be))) | + (addr_hit[115] & (|(ALERT_HANDLER_PERMIT[115] & ~reg_be))) | + (addr_hit[116] & (|(ALERT_HANDLER_PERMIT[116] & ~reg_be))) | + (addr_hit[117] & (|(ALERT_HANDLER_PERMIT[117] & ~reg_be))) | + (addr_hit[118] & (|(ALERT_HANDLER_PERMIT[118] & ~reg_be))) | + (addr_hit[119] & (|(ALERT_HANDLER_PERMIT[119] & ~reg_be))) | + (addr_hit[120] & (|(ALERT_HANDLER_PERMIT[120] & ~reg_be))) | + (addr_hit[121] & (|(ALERT_HANDLER_PERMIT[121] & ~reg_be))) | + (addr_hit[122] & (|(ALERT_HANDLER_PERMIT[122] & ~reg_be))) | + (addr_hit[123] & (|(ALERT_HANDLER_PERMIT[123] & ~reg_be))) | + (addr_hit[124] & (|(ALERT_HANDLER_PERMIT[124] & ~reg_be))) | + (addr_hit[125] & (|(ALERT_HANDLER_PERMIT[125] & ~reg_be))) | + (addr_hit[126] & (|(ALERT_HANDLER_PERMIT[126] & ~reg_be))) | + (addr_hit[127] & (|(ALERT_HANDLER_PERMIT[127] & ~reg_be))) | + (addr_hit[128] & (|(ALERT_HANDLER_PERMIT[128] & ~reg_be))) | + (addr_hit[129] & (|(ALERT_HANDLER_PERMIT[129] & ~reg_be))) | + (addr_hit[130] & (|(ALERT_HANDLER_PERMIT[130] & ~reg_be))) | + (addr_hit[131] & (|(ALERT_HANDLER_PERMIT[131] & ~reg_be))) | + (addr_hit[132] & (|(ALERT_HANDLER_PERMIT[132] & ~reg_be))) | + (addr_hit[133] & (|(ALERT_HANDLER_PERMIT[133] & ~reg_be))) | + (addr_hit[134] & (|(ALERT_HANDLER_PERMIT[134] & ~reg_be))) | + (addr_hit[135] & (|(ALERT_HANDLER_PERMIT[135] & ~reg_be))) | + (addr_hit[136] & (|(ALERT_HANDLER_PERMIT[136] & ~reg_be))) | + (addr_hit[137] & (|(ALERT_HANDLER_PERMIT[137] & ~reg_be))) | + (addr_hit[138] & (|(ALERT_HANDLER_PERMIT[138] & ~reg_be))) | + (addr_hit[139] & (|(ALERT_HANDLER_PERMIT[139] & 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~reg_be))) | + (addr_hit[328] & (|(ALERT_HANDLER_PERMIT[328] & ~reg_be))) | + (addr_hit[329] & (|(ALERT_HANDLER_PERMIT[329] & ~reg_be))) | + (addr_hit[330] & (|(ALERT_HANDLER_PERMIT[330] & ~reg_be))) | + (addr_hit[331] & (|(ALERT_HANDLER_PERMIT[331] & ~reg_be))) | + (addr_hit[332] & (|(ALERT_HANDLER_PERMIT[332] & ~reg_be))) | + (addr_hit[333] & (|(ALERT_HANDLER_PERMIT[333] & ~reg_be))) | + (addr_hit[334] & (|(ALERT_HANDLER_PERMIT[334] & ~reg_be))) | + (addr_hit[335] & (|(ALERT_HANDLER_PERMIT[335] & ~reg_be))) | + (addr_hit[336] & (|(ALERT_HANDLER_PERMIT[336] & ~reg_be))) | + (addr_hit[337] & (|(ALERT_HANDLER_PERMIT[337] & ~reg_be))) | + (addr_hit[338] & (|(ALERT_HANDLER_PERMIT[338] & ~reg_be))) | + (addr_hit[339] & (|(ALERT_HANDLER_PERMIT[339] & ~reg_be))) | + (addr_hit[340] & (|(ALERT_HANDLER_PERMIT[340] & ~reg_be))) | + (addr_hit[341] & (|(ALERT_HANDLER_PERMIT[341] & ~reg_be))) | + (addr_hit[342] & (|(ALERT_HANDLER_PERMIT[342] & ~reg_be))) | + (addr_hit[343] & (|(ALERT_HANDLER_PERMIT[343] & ~reg_be))) | + (addr_hit[344] & (|(ALERT_HANDLER_PERMIT[344] & ~reg_be))) | + (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))) | + (addr_hit[346] & (|(ALERT_HANDLER_PERMIT[346] & ~reg_be))) | + (addr_hit[347] & (|(ALERT_HANDLER_PERMIT[347] & ~reg_be))) | + (addr_hit[348] & (|(ALERT_HANDLER_PERMIT[348] & ~reg_be))) | + (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be))) | + (addr_hit[350] & (|(ALERT_HANDLER_PERMIT[350] & ~reg_be))) | + (addr_hit[351] & (|(ALERT_HANDLER_PERMIT[351] & ~reg_be))) | + (addr_hit[352] & (|(ALERT_HANDLER_PERMIT[352] & ~reg_be))) | + (addr_hit[353] & (|(ALERT_HANDLER_PERMIT[353] & ~reg_be))) | + (addr_hit[354] & (|(ALERT_HANDLER_PERMIT[354] & ~reg_be))) | + (addr_hit[355] & (|(ALERT_HANDLER_PERMIT[355] & ~reg_be))) | + (addr_hit[356] & (|(ALERT_HANDLER_PERMIT[356] & ~reg_be))) | + (addr_hit[357] & (|(ALERT_HANDLER_PERMIT[357] & ~reg_be))) | + (addr_hit[358] & (|(ALERT_HANDLER_PERMIT[358] & ~reg_be))) | + (addr_hit[359] & (|(ALERT_HANDLER_PERMIT[359] & ~reg_be))) | + (addr_hit[360] & (|(ALERT_HANDLER_PERMIT[360] & ~reg_be))) | + (addr_hit[361] & (|(ALERT_HANDLER_PERMIT[361] & ~reg_be))) | + (addr_hit[362] & (|(ALERT_HANDLER_PERMIT[362] & ~reg_be))) | + (addr_hit[363] & (|(ALERT_HANDLER_PERMIT[363] & ~reg_be))) | + (addr_hit[364] & (|(ALERT_HANDLER_PERMIT[364] & ~reg_be))) | + (addr_hit[365] & (|(ALERT_HANDLER_PERMIT[365] & ~reg_be))) | + (addr_hit[366] & (|(ALERT_HANDLER_PERMIT[366] & ~reg_be))) | + (addr_hit[367] & (|(ALERT_HANDLER_PERMIT[367] & ~reg_be))) | + (addr_hit[368] & (|(ALERT_HANDLER_PERMIT[368] & ~reg_be))) | + (addr_hit[369] & (|(ALERT_HANDLER_PERMIT[369] & ~reg_be))) | + (addr_hit[370] & (|(ALERT_HANDLER_PERMIT[370] & ~reg_be))) | + (addr_hit[371] & (|(ALERT_HANDLER_PERMIT[371] & ~reg_be))) | + (addr_hit[372] & (|(ALERT_HANDLER_PERMIT[372] & ~reg_be))) | + (addr_hit[373] & (|(ALERT_HANDLER_PERMIT[373] & ~reg_be))) | + (addr_hit[374] & (|(ALERT_HANDLER_PERMIT[374] & ~reg_be))) | + (addr_hit[375] & (|(ALERT_HANDLER_PERMIT[375] & ~reg_be))) | + (addr_hit[376] & (|(ALERT_HANDLER_PERMIT[376] & ~reg_be))) | + (addr_hit[377] & (|(ALERT_HANDLER_PERMIT[377] & ~reg_be))) | + (addr_hit[378] & (|(ALERT_HANDLER_PERMIT[378] & ~reg_be))) | + (addr_hit[379] & (|(ALERT_HANDLER_PERMIT[379] & ~reg_be))) | + (addr_hit[380] & (|(ALERT_HANDLER_PERMIT[380] & ~reg_be))) | + (addr_hit[381] & (|(ALERT_HANDLER_PERMIT[381] & ~reg_be))) | + (addr_hit[382] & (|(ALERT_HANDLER_PERMIT[382] & ~reg_be))) | + (addr_hit[383] & (|(ALERT_HANDLER_PERMIT[383] & ~reg_be))) | + (addr_hit[384] & (|(ALERT_HANDLER_PERMIT[384] & ~reg_be))) | + (addr_hit[385] & (|(ALERT_HANDLER_PERMIT[385] & ~reg_be))) | + (addr_hit[386] & (|(ALERT_HANDLER_PERMIT[386] & ~reg_be))) | + (addr_hit[387] & (|(ALERT_HANDLER_PERMIT[387] & ~reg_be))) | + (addr_hit[388] & (|(ALERT_HANDLER_PERMIT[388] & ~reg_be))) | + (addr_hit[389] & (|(ALERT_HANDLER_PERMIT[389] & ~reg_be))) | + (addr_hit[390] & (|(ALERT_HANDLER_PERMIT[390] & ~reg_be))) | + (addr_hit[391] & (|(ALERT_HANDLER_PERMIT[391] & ~reg_be))) | + (addr_hit[392] & (|(ALERT_HANDLER_PERMIT[392] & ~reg_be))) | + (addr_hit[393] & (|(ALERT_HANDLER_PERMIT[393] & ~reg_be))) | + (addr_hit[394] & (|(ALERT_HANDLER_PERMIT[394] & ~reg_be))) | + (addr_hit[395] & (|(ALERT_HANDLER_PERMIT[395] & ~reg_be))) | + (addr_hit[396] & (|(ALERT_HANDLER_PERMIT[396] & ~reg_be))) | + (addr_hit[397] & (|(ALERT_HANDLER_PERMIT[397] & ~reg_be))) | + (addr_hit[398] & (|(ALERT_HANDLER_PERMIT[398] & ~reg_be))) | + (addr_hit[399] & (|(ALERT_HANDLER_PERMIT[399] & ~reg_be))) | + (addr_hit[400] & (|(ALERT_HANDLER_PERMIT[400] & ~reg_be))) | + (addr_hit[401] & (|(ALERT_HANDLER_PERMIT[401] & ~reg_be))) | + (addr_hit[402] & (|(ALERT_HANDLER_PERMIT[402] & ~reg_be))) | + (addr_hit[403] & (|(ALERT_HANDLER_PERMIT[403] & ~reg_be))) | + (addr_hit[404] & (|(ALERT_HANDLER_PERMIT[404] & ~reg_be))) | + (addr_hit[405] & (|(ALERT_HANDLER_PERMIT[405] & ~reg_be))) | + (addr_hit[406] & (|(ALERT_HANDLER_PERMIT[406] & ~reg_be))) | + (addr_hit[407] & (|(ALERT_HANDLER_PERMIT[407] & ~reg_be))) | + (addr_hit[408] & (|(ALERT_HANDLER_PERMIT[408] & ~reg_be))) | + (addr_hit[409] & (|(ALERT_HANDLER_PERMIT[409] & ~reg_be))) | + (addr_hit[410] & (|(ALERT_HANDLER_PERMIT[410] & ~reg_be))) | + (addr_hit[411] & (|(ALERT_HANDLER_PERMIT[411] & ~reg_be))) | + (addr_hit[412] & (|(ALERT_HANDLER_PERMIT[412] & ~reg_be))) | + (addr_hit[413] & (|(ALERT_HANDLER_PERMIT[413] & ~reg_be))) | + (addr_hit[414] & (|(ALERT_HANDLER_PERMIT[414] & ~reg_be))) | + (addr_hit[415] & (|(ALERT_HANDLER_PERMIT[415] & ~reg_be))) | + (addr_hit[416] & (|(ALERT_HANDLER_PERMIT[416] & ~reg_be))) | + (addr_hit[417] & (|(ALERT_HANDLER_PERMIT[417] & ~reg_be))) | + (addr_hit[418] & (|(ALERT_HANDLER_PERMIT[418] & ~reg_be))) | + (addr_hit[419] & (|(ALERT_HANDLER_PERMIT[419] & ~reg_be))) | + (addr_hit[420] & (|(ALERT_HANDLER_PERMIT[420] & ~reg_be))) | + (addr_hit[421] & (|(ALERT_HANDLER_PERMIT[421] & ~reg_be))) | + (addr_hit[422] & (|(ALERT_HANDLER_PERMIT[422] & ~reg_be))) | + (addr_hit[423] & (|(ALERT_HANDLER_PERMIT[423] & ~reg_be))) | + (addr_hit[424] & (|(ALERT_HANDLER_PERMIT[424] & ~reg_be))) | + (addr_hit[425] & (|(ALERT_HANDLER_PERMIT[425] & ~reg_be))) | + (addr_hit[426] & (|(ALERT_HANDLER_PERMIT[426] & ~reg_be))) | + (addr_hit[427] & (|(ALERT_HANDLER_PERMIT[427] & ~reg_be))) | + (addr_hit[428] & (|(ALERT_HANDLER_PERMIT[428] & ~reg_be))) | + (addr_hit[429] & (|(ALERT_HANDLER_PERMIT[429] & ~reg_be))) | + (addr_hit[430] & (|(ALERT_HANDLER_PERMIT[430] & ~reg_be))) | + (addr_hit[431] & (|(ALERT_HANDLER_PERMIT[431] & ~reg_be))) | + (addr_hit[432] & (|(ALERT_HANDLER_PERMIT[432] & ~reg_be))) | + (addr_hit[433] & (|(ALERT_HANDLER_PERMIT[433] & ~reg_be))) | + (addr_hit[434] & (|(ALERT_HANDLER_PERMIT[434] & ~reg_be))) | + (addr_hit[435] & (|(ALERT_HANDLER_PERMIT[435] & ~reg_be))) | + (addr_hit[436] & (|(ALERT_HANDLER_PERMIT[436] & ~reg_be))) | + (addr_hit[437] & (|(ALERT_HANDLER_PERMIT[437] & ~reg_be))) | + (addr_hit[438] & (|(ALERT_HANDLER_PERMIT[438] & ~reg_be))) | + (addr_hit[439] & (|(ALERT_HANDLER_PERMIT[439] & ~reg_be))) | + (addr_hit[440] & (|(ALERT_HANDLER_PERMIT[440] & ~reg_be))) | + (addr_hit[441] & (|(ALERT_HANDLER_PERMIT[441] & ~reg_be))) | + (addr_hit[442] & (|(ALERT_HANDLER_PERMIT[442] & ~reg_be))) | + (addr_hit[443] & (|(ALERT_HANDLER_PERMIT[443] & ~reg_be))) | + (addr_hit[444] & (|(ALERT_HANDLER_PERMIT[444] & ~reg_be))) | + (addr_hit[445] & (|(ALERT_HANDLER_PERMIT[445] & ~reg_be))) | + (addr_hit[446] & (|(ALERT_HANDLER_PERMIT[446] & ~reg_be))) | + (addr_hit[447] & (|(ALERT_HANDLER_PERMIT[447] & ~reg_be))) | + (addr_hit[448] & (|(ALERT_HANDLER_PERMIT[448] & ~reg_be))) | + (addr_hit[449] & (|(ALERT_HANDLER_PERMIT[449] & ~reg_be))) | + (addr_hit[450] & (|(ALERT_HANDLER_PERMIT[450] & ~reg_be))) | + (addr_hit[451] & (|(ALERT_HANDLER_PERMIT[451] & ~reg_be))) | + (addr_hit[452] & (|(ALERT_HANDLER_PERMIT[452] & ~reg_be))) | + (addr_hit[453] & (|(ALERT_HANDLER_PERMIT[453] & ~reg_be))) | + (addr_hit[454] & (|(ALERT_HANDLER_PERMIT[454] & ~reg_be))) | + (addr_hit[455] & (|(ALERT_HANDLER_PERMIT[455] & ~reg_be))) | + (addr_hit[456] & (|(ALERT_HANDLER_PERMIT[456] & ~reg_be))) | + (addr_hit[457] & (|(ALERT_HANDLER_PERMIT[457] & ~reg_be))) | + (addr_hit[458] & (|(ALERT_HANDLER_PERMIT[458] & ~reg_be))) | + (addr_hit[459] & (|(ALERT_HANDLER_PERMIT[459] & ~reg_be))) | + (addr_hit[460] & (|(ALERT_HANDLER_PERMIT[460] & ~reg_be))) | + (addr_hit[461] & (|(ALERT_HANDLER_PERMIT[461] & ~reg_be))) | + (addr_hit[462] & (|(ALERT_HANDLER_PERMIT[462] & ~reg_be))) | + (addr_hit[463] & (|(ALERT_HANDLER_PERMIT[463] & ~reg_be))) | + (addr_hit[464] & (|(ALERT_HANDLER_PERMIT[464] & ~reg_be))) | + (addr_hit[465] & (|(ALERT_HANDLER_PERMIT[465] & ~reg_be))) | + (addr_hit[466] & (|(ALERT_HANDLER_PERMIT[466] & ~reg_be))) | + (addr_hit[467] & (|(ALERT_HANDLER_PERMIT[467] & ~reg_be))) | + (addr_hit[468] & (|(ALERT_HANDLER_PERMIT[468] & ~reg_be))) | + (addr_hit[469] & (|(ALERT_HANDLER_PERMIT[469] & ~reg_be))) | + (addr_hit[470] & (|(ALERT_HANDLER_PERMIT[470] & ~reg_be))) | + (addr_hit[471] & (|(ALERT_HANDLER_PERMIT[471] & ~reg_be))) | + (addr_hit[472] & (|(ALERT_HANDLER_PERMIT[472] & ~reg_be))) | + (addr_hit[473] & (|(ALERT_HANDLER_PERMIT[473] & ~reg_be))) | + (addr_hit[474] & (|(ALERT_HANDLER_PERMIT[474] & ~reg_be))) | + (addr_hit[475] & (|(ALERT_HANDLER_PERMIT[475] & ~reg_be))) | + (addr_hit[476] & (|(ALERT_HANDLER_PERMIT[476] & ~reg_be))) | + (addr_hit[477] & (|(ALERT_HANDLER_PERMIT[477] & ~reg_be))) | + (addr_hit[478] & (|(ALERT_HANDLER_PERMIT[478] & ~reg_be))) | + (addr_hit[479] & (|(ALERT_HANDLER_PERMIT[479] & ~reg_be))) | + (addr_hit[480] & (|(ALERT_HANDLER_PERMIT[480] & ~reg_be))) | + (addr_hit[481] & (|(ALERT_HANDLER_PERMIT[481] & ~reg_be))) | + (addr_hit[482] & (|(ALERT_HANDLER_PERMIT[482] & ~reg_be))) | + (addr_hit[483] & (|(ALERT_HANDLER_PERMIT[483] & ~reg_be))) | + (addr_hit[484] & (|(ALERT_HANDLER_PERMIT[484] & ~reg_be))) | + (addr_hit[485] & (|(ALERT_HANDLER_PERMIT[485] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = addr_hit[0] & reg_we & !reg_error; + + assign intr_state_classa_wd = reg_wdata[0]; + + assign intr_state_classb_wd = reg_wdata[1]; + + assign intr_state_classc_wd = reg_wdata[2]; + + assign intr_state_classd_wd = reg_wdata[3]; + assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; + + assign intr_enable_classa_wd = reg_wdata[0]; + + assign intr_enable_classb_wd = reg_wdata[1]; + + assign intr_enable_classc_wd = reg_wdata[2]; + + assign intr_enable_classd_wd = reg_wdata[3]; + assign intr_test_we = addr_hit[2] & reg_we & !reg_error; + + assign intr_test_classa_wd = reg_wdata[0]; + + assign intr_test_classb_wd = reg_wdata[1]; + + assign intr_test_classc_wd = reg_wdata[2]; + + assign intr_test_classd_wd = reg_wdata[3]; + assign ping_timer_regwen_we = addr_hit[3] & reg_we & !reg_error; + + assign ping_timer_regwen_wd = reg_wdata[0]; + assign ping_timeout_cyc_shadowed_re = addr_hit[4] & reg_re & !reg_error; + assign ping_timeout_cyc_shadowed_we = addr_hit[4] & reg_we & !reg_error; + + assign ping_timeout_cyc_shadowed_wd = reg_wdata[15:0]; + assign ping_timer_en_shadowed_re = addr_hit[5] & reg_re & !reg_error; + assign ping_timer_en_shadowed_we = addr_hit[5] & reg_we & !reg_error; + + assign ping_timer_en_shadowed_wd = reg_wdata[0]; + assign alert_regwen_0_we = addr_hit[6] & reg_we & !reg_error; + + assign alert_regwen_0_wd = reg_wdata[0]; + assign alert_regwen_1_we = addr_hit[7] & reg_we & !reg_error; + + assign alert_regwen_1_wd = reg_wdata[0]; + assign alert_regwen_2_we = addr_hit[8] & reg_we & !reg_error; + + assign alert_regwen_2_wd = reg_wdata[0]; + assign alert_regwen_3_we = addr_hit[9] & reg_we & !reg_error; + + assign alert_regwen_3_wd = reg_wdata[0]; + assign alert_regwen_4_we = addr_hit[10] & reg_we & !reg_error; + + assign alert_regwen_4_wd = reg_wdata[0]; + assign alert_regwen_5_we = addr_hit[11] & reg_we & !reg_error; + + assign alert_regwen_5_wd = reg_wdata[0]; + assign alert_regwen_6_we = addr_hit[12] & reg_we & !reg_error; + + assign alert_regwen_6_wd = reg_wdata[0]; + assign alert_regwen_7_we = addr_hit[13] & reg_we & !reg_error; + + assign alert_regwen_7_wd = reg_wdata[0]; + assign alert_regwen_8_we = addr_hit[14] & reg_we & !reg_error; + + assign alert_regwen_8_wd = reg_wdata[0]; + assign alert_regwen_9_we = addr_hit[15] & reg_we & !reg_error; + + assign alert_regwen_9_wd = reg_wdata[0]; + assign alert_regwen_10_we = addr_hit[16] & reg_we & !reg_error; + + assign alert_regwen_10_wd = reg_wdata[0]; + assign alert_regwen_11_we = addr_hit[17] & reg_we & !reg_error; + + assign alert_regwen_11_wd = reg_wdata[0]; + assign alert_regwen_12_we = addr_hit[18] & reg_we & !reg_error; + + assign alert_regwen_12_wd = reg_wdata[0]; + assign alert_regwen_13_we = addr_hit[19] & reg_we & !reg_error; + + assign alert_regwen_13_wd = reg_wdata[0]; + assign alert_regwen_14_we = addr_hit[20] & reg_we & !reg_error; + + assign alert_regwen_14_wd = reg_wdata[0]; + assign alert_regwen_15_we = addr_hit[21] & reg_we & !reg_error; + + assign alert_regwen_15_wd = reg_wdata[0]; + assign alert_regwen_16_we = addr_hit[22] & reg_we & !reg_error; + + assign alert_regwen_16_wd = reg_wdata[0]; + assign alert_regwen_17_we = addr_hit[23] & reg_we & !reg_error; + + assign alert_regwen_17_wd = reg_wdata[0]; + assign alert_regwen_18_we = addr_hit[24] & reg_we & !reg_error; + + assign alert_regwen_18_wd = reg_wdata[0]; + assign alert_regwen_19_we = addr_hit[25] & reg_we & !reg_error; + + assign alert_regwen_19_wd = reg_wdata[0]; + assign alert_regwen_20_we = addr_hit[26] & reg_we & !reg_error; + + assign alert_regwen_20_wd = reg_wdata[0]; + assign alert_regwen_21_we = addr_hit[27] & reg_we & !reg_error; + + assign alert_regwen_21_wd = reg_wdata[0]; + assign alert_regwen_22_we = addr_hit[28] & reg_we & !reg_error; + + assign alert_regwen_22_wd = reg_wdata[0]; + assign alert_regwen_23_we = addr_hit[29] & reg_we & !reg_error; + + assign alert_regwen_23_wd = reg_wdata[0]; + assign alert_regwen_24_we = addr_hit[30] & reg_we & !reg_error; + + assign alert_regwen_24_wd = reg_wdata[0]; + assign alert_regwen_25_we = addr_hit[31] & reg_we & !reg_error; + + assign alert_regwen_25_wd = reg_wdata[0]; + assign alert_regwen_26_we = addr_hit[32] & reg_we & !reg_error; + + assign alert_regwen_26_wd = reg_wdata[0]; + assign alert_regwen_27_we = addr_hit[33] & reg_we & !reg_error; + + assign alert_regwen_27_wd = reg_wdata[0]; + assign alert_regwen_28_we = addr_hit[34] & reg_we & !reg_error; + + assign alert_regwen_28_wd = reg_wdata[0]; + assign alert_regwen_29_we = addr_hit[35] & reg_we & !reg_error; + + assign alert_regwen_29_wd = reg_wdata[0]; + assign alert_regwen_30_we = addr_hit[36] & reg_we & !reg_error; + + assign alert_regwen_30_wd = reg_wdata[0]; + assign alert_regwen_31_we = addr_hit[37] & reg_we & !reg_error; + + assign alert_regwen_31_wd = reg_wdata[0]; + assign alert_regwen_32_we = addr_hit[38] & reg_we & !reg_error; + + assign alert_regwen_32_wd = reg_wdata[0]; + assign alert_regwen_33_we = addr_hit[39] & reg_we & !reg_error; + + assign alert_regwen_33_wd = reg_wdata[0]; + assign alert_regwen_34_we = addr_hit[40] & reg_we & !reg_error; + + assign alert_regwen_34_wd = reg_wdata[0]; + assign alert_regwen_35_we = addr_hit[41] & reg_we & !reg_error; + + assign alert_regwen_35_wd = reg_wdata[0]; + assign alert_regwen_36_we = addr_hit[42] & reg_we & !reg_error; + + assign alert_regwen_36_wd = reg_wdata[0]; + assign alert_regwen_37_we = addr_hit[43] & reg_we & !reg_error; + + assign alert_regwen_37_wd = reg_wdata[0]; + assign alert_regwen_38_we = addr_hit[44] & reg_we & !reg_error; + + assign alert_regwen_38_wd = reg_wdata[0]; + assign alert_regwen_39_we = addr_hit[45] & reg_we & !reg_error; + + assign alert_regwen_39_wd = reg_wdata[0]; + assign alert_regwen_40_we = addr_hit[46] & reg_we & !reg_error; + + assign alert_regwen_40_wd = reg_wdata[0]; + assign alert_regwen_41_we = addr_hit[47] & reg_we & !reg_error; + + assign alert_regwen_41_wd = reg_wdata[0]; + assign alert_regwen_42_we = addr_hit[48] & reg_we & !reg_error; + + assign alert_regwen_42_wd = reg_wdata[0]; + assign alert_regwen_43_we = addr_hit[49] & reg_we & !reg_error; + + assign alert_regwen_43_wd = reg_wdata[0]; + assign alert_regwen_44_we = addr_hit[50] & reg_we & !reg_error; + + assign alert_regwen_44_wd = reg_wdata[0]; + assign alert_regwen_45_we = addr_hit[51] & reg_we & !reg_error; + + assign alert_regwen_45_wd = reg_wdata[0]; + assign alert_regwen_46_we = addr_hit[52] & reg_we & !reg_error; + + assign alert_regwen_46_wd = reg_wdata[0]; + assign alert_regwen_47_we = addr_hit[53] & reg_we & !reg_error; + + assign alert_regwen_47_wd = reg_wdata[0]; + assign alert_regwen_48_we = addr_hit[54] & reg_we & !reg_error; + + assign alert_regwen_48_wd = reg_wdata[0]; + assign alert_regwen_49_we = addr_hit[55] & reg_we & !reg_error; + + assign alert_regwen_49_wd = reg_wdata[0]; + assign alert_regwen_50_we = addr_hit[56] & reg_we & !reg_error; + + assign alert_regwen_50_wd = reg_wdata[0]; + assign alert_regwen_51_we = addr_hit[57] & reg_we & !reg_error; + + assign alert_regwen_51_wd = reg_wdata[0]; + assign alert_regwen_52_we = addr_hit[58] & reg_we & !reg_error; + + assign alert_regwen_52_wd = reg_wdata[0]; + assign alert_regwen_53_we = addr_hit[59] & reg_we & !reg_error; + + assign alert_regwen_53_wd = reg_wdata[0]; + assign alert_regwen_54_we = addr_hit[60] & reg_we & !reg_error; + + assign alert_regwen_54_wd = reg_wdata[0]; + assign alert_regwen_55_we = addr_hit[61] & reg_we & !reg_error; + + assign alert_regwen_55_wd = reg_wdata[0]; + assign alert_regwen_56_we = addr_hit[62] & reg_we & !reg_error; + + assign alert_regwen_56_wd = reg_wdata[0]; + assign alert_regwen_57_we = addr_hit[63] & reg_we & !reg_error; + + assign alert_regwen_57_wd = reg_wdata[0]; + assign alert_regwen_58_we = addr_hit[64] & reg_we & !reg_error; + + assign alert_regwen_58_wd = reg_wdata[0]; + assign alert_regwen_59_we = addr_hit[65] & reg_we & !reg_error; + + assign alert_regwen_59_wd = reg_wdata[0]; + assign alert_regwen_60_we = addr_hit[66] & reg_we & !reg_error; + + assign alert_regwen_60_wd = reg_wdata[0]; + assign alert_regwen_61_we = addr_hit[67] & reg_we & !reg_error; + + assign alert_regwen_61_wd = reg_wdata[0]; + assign alert_regwen_62_we = addr_hit[68] & reg_we & !reg_error; + + assign alert_regwen_62_wd = reg_wdata[0]; + assign alert_regwen_63_we = addr_hit[69] & reg_we & !reg_error; + + assign alert_regwen_63_wd = reg_wdata[0]; + assign alert_regwen_64_we = addr_hit[70] & reg_we & !reg_error; + + assign alert_regwen_64_wd = reg_wdata[0]; + assign alert_regwen_65_we = addr_hit[71] & reg_we & !reg_error; + + assign alert_regwen_65_wd = reg_wdata[0]; + assign alert_regwen_66_we = addr_hit[72] & reg_we & !reg_error; + + assign alert_regwen_66_wd = reg_wdata[0]; + assign alert_regwen_67_we = addr_hit[73] & reg_we & !reg_error; + + assign alert_regwen_67_wd = reg_wdata[0]; + assign alert_regwen_68_we = addr_hit[74] & reg_we & !reg_error; + + assign alert_regwen_68_wd = reg_wdata[0]; + assign alert_regwen_69_we = addr_hit[75] & reg_we & !reg_error; + + assign alert_regwen_69_wd = reg_wdata[0]; + assign alert_regwen_70_we = addr_hit[76] & reg_we & !reg_error; + + assign alert_regwen_70_wd = reg_wdata[0]; + assign alert_regwen_71_we = addr_hit[77] & reg_we & !reg_error; + + assign alert_regwen_71_wd = reg_wdata[0]; + assign alert_regwen_72_we = addr_hit[78] & reg_we & !reg_error; + + assign alert_regwen_72_wd = reg_wdata[0]; + assign alert_regwen_73_we = addr_hit[79] & reg_we & !reg_error; + + assign alert_regwen_73_wd = reg_wdata[0]; + assign alert_regwen_74_we = addr_hit[80] & reg_we & !reg_error; + + assign alert_regwen_74_wd = reg_wdata[0]; + assign alert_regwen_75_we = addr_hit[81] & reg_we & !reg_error; + + assign alert_regwen_75_wd = reg_wdata[0]; + assign alert_regwen_76_we = addr_hit[82] & reg_we & !reg_error; + + assign alert_regwen_76_wd = reg_wdata[0]; + assign alert_regwen_77_we = addr_hit[83] & reg_we & !reg_error; + + assign alert_regwen_77_wd = reg_wdata[0]; + assign alert_regwen_78_we = addr_hit[84] & reg_we & !reg_error; + + assign alert_regwen_78_wd = reg_wdata[0]; + assign alert_regwen_79_we = addr_hit[85] & reg_we & !reg_error; + + assign alert_regwen_79_wd = reg_wdata[0]; + assign alert_regwen_80_we = addr_hit[86] & reg_we & !reg_error; + + assign alert_regwen_80_wd = reg_wdata[0]; + assign alert_regwen_81_we = addr_hit[87] & reg_we & !reg_error; + + assign alert_regwen_81_wd = reg_wdata[0]; + assign alert_regwen_82_we = addr_hit[88] & reg_we & !reg_error; + + assign alert_regwen_82_wd = reg_wdata[0]; + assign alert_regwen_83_we = addr_hit[89] & reg_we & !reg_error; + + assign alert_regwen_83_wd = reg_wdata[0]; + assign alert_regwen_84_we = addr_hit[90] & reg_we & !reg_error; + + assign alert_regwen_84_wd = reg_wdata[0]; + assign alert_regwen_85_we = addr_hit[91] & reg_we & !reg_error; + + assign alert_regwen_85_wd = reg_wdata[0]; + assign alert_regwen_86_we = addr_hit[92] & reg_we & !reg_error; + + assign alert_regwen_86_wd = reg_wdata[0]; + assign alert_regwen_87_we = addr_hit[93] & reg_we & !reg_error; + + assign alert_regwen_87_wd = reg_wdata[0]; + assign alert_regwen_88_we = addr_hit[94] & reg_we & !reg_error; + + assign alert_regwen_88_wd = reg_wdata[0]; + assign alert_regwen_89_we = addr_hit[95] & reg_we & !reg_error; + + assign alert_regwen_89_wd = reg_wdata[0]; + assign alert_regwen_90_we = addr_hit[96] & reg_we & !reg_error; + + assign alert_regwen_90_wd = reg_wdata[0]; + assign alert_regwen_91_we = addr_hit[97] & reg_we & !reg_error; + + assign alert_regwen_91_wd = reg_wdata[0]; + assign alert_regwen_92_we = addr_hit[98] & reg_we & !reg_error; + + assign alert_regwen_92_wd = reg_wdata[0]; + assign alert_regwen_93_we = addr_hit[99] & reg_we & !reg_error; + + assign alert_regwen_93_wd = reg_wdata[0]; + assign alert_regwen_94_we = addr_hit[100] & reg_we & !reg_error; + + assign alert_regwen_94_wd = reg_wdata[0]; + assign alert_regwen_95_we = addr_hit[101] & reg_we & !reg_error; + + assign alert_regwen_95_wd = reg_wdata[0]; + assign alert_regwen_96_we = addr_hit[102] & reg_we & !reg_error; + + assign alert_regwen_96_wd = reg_wdata[0]; + assign alert_regwen_97_we = addr_hit[103] & reg_we & !reg_error; + + assign alert_regwen_97_wd = reg_wdata[0]; + assign alert_regwen_98_we = addr_hit[104] & reg_we & !reg_error; + + assign alert_regwen_98_wd = reg_wdata[0]; + assign alert_en_shadowed_0_re = addr_hit[105] & reg_re & !reg_error; + assign alert_en_shadowed_0_we = addr_hit[105] & reg_we & !reg_error; + + assign alert_en_shadowed_0_wd = reg_wdata[0]; + assign alert_en_shadowed_1_re = addr_hit[106] & reg_re & !reg_error; + assign alert_en_shadowed_1_we = addr_hit[106] & reg_we & !reg_error; + + assign alert_en_shadowed_1_wd = reg_wdata[0]; + assign alert_en_shadowed_2_re = addr_hit[107] & reg_re & !reg_error; + assign alert_en_shadowed_2_we = addr_hit[107] & reg_we & !reg_error; + + assign alert_en_shadowed_2_wd = reg_wdata[0]; + assign alert_en_shadowed_3_re = addr_hit[108] & reg_re & !reg_error; + assign alert_en_shadowed_3_we = addr_hit[108] & reg_we & !reg_error; + + assign alert_en_shadowed_3_wd = reg_wdata[0]; + assign alert_en_shadowed_4_re = addr_hit[109] & reg_re & !reg_error; + assign alert_en_shadowed_4_we = addr_hit[109] & reg_we & !reg_error; + + assign alert_en_shadowed_4_wd = reg_wdata[0]; + assign alert_en_shadowed_5_re = addr_hit[110] & reg_re & !reg_error; + assign alert_en_shadowed_5_we = addr_hit[110] & reg_we & !reg_error; + + assign alert_en_shadowed_5_wd = reg_wdata[0]; + assign alert_en_shadowed_6_re = addr_hit[111] & reg_re & !reg_error; + assign alert_en_shadowed_6_we = addr_hit[111] & reg_we & !reg_error; + + assign alert_en_shadowed_6_wd = reg_wdata[0]; + assign alert_en_shadowed_7_re = addr_hit[112] & reg_re & !reg_error; + assign alert_en_shadowed_7_we = addr_hit[112] & reg_we & !reg_error; + + assign alert_en_shadowed_7_wd = reg_wdata[0]; + assign alert_en_shadowed_8_re = addr_hit[113] & reg_re & !reg_error; + assign alert_en_shadowed_8_we = addr_hit[113] & reg_we & !reg_error; + + assign alert_en_shadowed_8_wd = reg_wdata[0]; + assign alert_en_shadowed_9_re = addr_hit[114] & reg_re & !reg_error; + assign alert_en_shadowed_9_we = addr_hit[114] & reg_we & !reg_error; + + assign alert_en_shadowed_9_wd = reg_wdata[0]; + assign alert_en_shadowed_10_re = addr_hit[115] & reg_re & !reg_error; + assign alert_en_shadowed_10_we = addr_hit[115] & reg_we & !reg_error; + + assign alert_en_shadowed_10_wd = reg_wdata[0]; + assign alert_en_shadowed_11_re = addr_hit[116] & reg_re & !reg_error; + assign alert_en_shadowed_11_we = addr_hit[116] & reg_we & !reg_error; + + assign alert_en_shadowed_11_wd = reg_wdata[0]; + assign alert_en_shadowed_12_re = addr_hit[117] & reg_re & !reg_error; + assign alert_en_shadowed_12_we = addr_hit[117] & reg_we & !reg_error; + + assign alert_en_shadowed_12_wd = reg_wdata[0]; + assign alert_en_shadowed_13_re = addr_hit[118] & reg_re & !reg_error; + assign alert_en_shadowed_13_we = addr_hit[118] & reg_we & !reg_error; + + assign alert_en_shadowed_13_wd = reg_wdata[0]; + assign alert_en_shadowed_14_re = addr_hit[119] & reg_re & !reg_error; + assign alert_en_shadowed_14_we = addr_hit[119] & reg_we & !reg_error; + + assign alert_en_shadowed_14_wd = reg_wdata[0]; + assign alert_en_shadowed_15_re = addr_hit[120] & reg_re & !reg_error; + assign alert_en_shadowed_15_we = addr_hit[120] & reg_we & !reg_error; + + assign alert_en_shadowed_15_wd = reg_wdata[0]; + assign alert_en_shadowed_16_re = addr_hit[121] & reg_re & !reg_error; + assign alert_en_shadowed_16_we = addr_hit[121] & reg_we & !reg_error; + + assign alert_en_shadowed_16_wd = reg_wdata[0]; + assign alert_en_shadowed_17_re = addr_hit[122] & reg_re & !reg_error; + assign alert_en_shadowed_17_we = addr_hit[122] & reg_we & !reg_error; + + assign alert_en_shadowed_17_wd = reg_wdata[0]; + assign alert_en_shadowed_18_re = addr_hit[123] & reg_re & !reg_error; + assign alert_en_shadowed_18_we = addr_hit[123] & reg_we & !reg_error; + + assign alert_en_shadowed_18_wd = reg_wdata[0]; + assign alert_en_shadowed_19_re = addr_hit[124] & reg_re & !reg_error; + assign alert_en_shadowed_19_we = addr_hit[124] & reg_we & !reg_error; + + assign alert_en_shadowed_19_wd = reg_wdata[0]; + assign alert_en_shadowed_20_re = addr_hit[125] & reg_re & !reg_error; + assign alert_en_shadowed_20_we = addr_hit[125] & reg_we & !reg_error; + + assign alert_en_shadowed_20_wd = reg_wdata[0]; + assign alert_en_shadowed_21_re = addr_hit[126] & reg_re & !reg_error; + assign alert_en_shadowed_21_we = addr_hit[126] & reg_we & !reg_error; + + assign alert_en_shadowed_21_wd = reg_wdata[0]; + assign alert_en_shadowed_22_re = addr_hit[127] & reg_re & !reg_error; + assign alert_en_shadowed_22_we = addr_hit[127] & reg_we & !reg_error; + + assign alert_en_shadowed_22_wd = reg_wdata[0]; + assign alert_en_shadowed_23_re = addr_hit[128] & reg_re & !reg_error; + assign alert_en_shadowed_23_we = addr_hit[128] & reg_we & !reg_error; + + assign alert_en_shadowed_23_wd = reg_wdata[0]; + assign alert_en_shadowed_24_re = addr_hit[129] & reg_re & !reg_error; + assign alert_en_shadowed_24_we = addr_hit[129] & reg_we & !reg_error; + + assign alert_en_shadowed_24_wd = reg_wdata[0]; + assign alert_en_shadowed_25_re = addr_hit[130] & reg_re & !reg_error; + assign alert_en_shadowed_25_we = addr_hit[130] & reg_we & !reg_error; + + assign alert_en_shadowed_25_wd = reg_wdata[0]; + assign alert_en_shadowed_26_re = addr_hit[131] & reg_re & !reg_error; + assign alert_en_shadowed_26_we = addr_hit[131] & reg_we & !reg_error; + + assign alert_en_shadowed_26_wd = reg_wdata[0]; + assign alert_en_shadowed_27_re = addr_hit[132] & reg_re & !reg_error; + assign alert_en_shadowed_27_we = addr_hit[132] & reg_we & !reg_error; + + assign alert_en_shadowed_27_wd = reg_wdata[0]; + assign alert_en_shadowed_28_re = addr_hit[133] & reg_re & !reg_error; + assign alert_en_shadowed_28_we = addr_hit[133] & reg_we & !reg_error; + + assign alert_en_shadowed_28_wd = reg_wdata[0]; + assign alert_en_shadowed_29_re = addr_hit[134] & reg_re & !reg_error; + assign alert_en_shadowed_29_we = addr_hit[134] & reg_we & !reg_error; + + assign alert_en_shadowed_29_wd = reg_wdata[0]; + assign alert_en_shadowed_30_re = addr_hit[135] & reg_re & !reg_error; + assign alert_en_shadowed_30_we = addr_hit[135] & reg_we & !reg_error; + + assign alert_en_shadowed_30_wd = reg_wdata[0]; + assign alert_en_shadowed_31_re = addr_hit[136] & reg_re & !reg_error; + assign alert_en_shadowed_31_we = addr_hit[136] & reg_we & !reg_error; + + assign alert_en_shadowed_31_wd = reg_wdata[0]; + assign alert_en_shadowed_32_re = addr_hit[137] & reg_re & !reg_error; + assign alert_en_shadowed_32_we = addr_hit[137] & reg_we & !reg_error; + + assign alert_en_shadowed_32_wd = reg_wdata[0]; + assign alert_en_shadowed_33_re = addr_hit[138] & reg_re & !reg_error; + assign alert_en_shadowed_33_we = addr_hit[138] & reg_we & !reg_error; + + assign alert_en_shadowed_33_wd = reg_wdata[0]; + assign alert_en_shadowed_34_re = addr_hit[139] & reg_re & !reg_error; + assign alert_en_shadowed_34_we = addr_hit[139] & reg_we & !reg_error; + + assign alert_en_shadowed_34_wd = reg_wdata[0]; + assign alert_en_shadowed_35_re = addr_hit[140] & reg_re & !reg_error; + assign alert_en_shadowed_35_we = addr_hit[140] & reg_we & !reg_error; + + assign alert_en_shadowed_35_wd = reg_wdata[0]; + assign alert_en_shadowed_36_re = addr_hit[141] & reg_re & !reg_error; + assign alert_en_shadowed_36_we = addr_hit[141] & reg_we & !reg_error; + + assign alert_en_shadowed_36_wd = reg_wdata[0]; + assign alert_en_shadowed_37_re = addr_hit[142] & reg_re & !reg_error; + assign alert_en_shadowed_37_we = addr_hit[142] & reg_we & !reg_error; + + assign alert_en_shadowed_37_wd = reg_wdata[0]; + assign alert_en_shadowed_38_re = addr_hit[143] & reg_re & !reg_error; + assign alert_en_shadowed_38_we = addr_hit[143] & reg_we & !reg_error; + + assign alert_en_shadowed_38_wd = reg_wdata[0]; + assign alert_en_shadowed_39_re = addr_hit[144] & reg_re & !reg_error; + assign alert_en_shadowed_39_we = addr_hit[144] & reg_we & !reg_error; + + assign alert_en_shadowed_39_wd = reg_wdata[0]; + assign alert_en_shadowed_40_re = addr_hit[145] & reg_re & !reg_error; + assign alert_en_shadowed_40_we = addr_hit[145] & reg_we & !reg_error; + + assign alert_en_shadowed_40_wd = reg_wdata[0]; + assign alert_en_shadowed_41_re = addr_hit[146] & reg_re & !reg_error; + assign alert_en_shadowed_41_we = addr_hit[146] & reg_we & !reg_error; + + assign alert_en_shadowed_41_wd = reg_wdata[0]; + assign alert_en_shadowed_42_re = addr_hit[147] & reg_re & !reg_error; + assign alert_en_shadowed_42_we = addr_hit[147] & reg_we & !reg_error; + + assign alert_en_shadowed_42_wd = reg_wdata[0]; + assign alert_en_shadowed_43_re = addr_hit[148] & reg_re & !reg_error; + assign alert_en_shadowed_43_we = addr_hit[148] & reg_we & !reg_error; + + assign alert_en_shadowed_43_wd = reg_wdata[0]; + assign alert_en_shadowed_44_re = addr_hit[149] & reg_re & !reg_error; + assign alert_en_shadowed_44_we = addr_hit[149] & reg_we & !reg_error; + + assign alert_en_shadowed_44_wd = reg_wdata[0]; + assign alert_en_shadowed_45_re = addr_hit[150] & reg_re & !reg_error; + assign alert_en_shadowed_45_we = addr_hit[150] & reg_we & !reg_error; + + assign alert_en_shadowed_45_wd = reg_wdata[0]; + assign alert_en_shadowed_46_re = addr_hit[151] & reg_re & !reg_error; + assign alert_en_shadowed_46_we = addr_hit[151] & reg_we & !reg_error; + + assign alert_en_shadowed_46_wd = reg_wdata[0]; + assign alert_en_shadowed_47_re = addr_hit[152] & reg_re & !reg_error; + assign alert_en_shadowed_47_we = addr_hit[152] & reg_we & !reg_error; + + assign alert_en_shadowed_47_wd = reg_wdata[0]; + assign alert_en_shadowed_48_re = addr_hit[153] & reg_re & !reg_error; + assign alert_en_shadowed_48_we = addr_hit[153] & reg_we & !reg_error; + + assign alert_en_shadowed_48_wd = reg_wdata[0]; + assign alert_en_shadowed_49_re = addr_hit[154] & reg_re & !reg_error; + assign alert_en_shadowed_49_we = addr_hit[154] & reg_we & !reg_error; + + assign alert_en_shadowed_49_wd = reg_wdata[0]; + assign alert_en_shadowed_50_re = addr_hit[155] & reg_re & !reg_error; + assign alert_en_shadowed_50_we = addr_hit[155] & reg_we & !reg_error; + + assign alert_en_shadowed_50_wd = reg_wdata[0]; + assign alert_en_shadowed_51_re = addr_hit[156] & reg_re & !reg_error; + assign alert_en_shadowed_51_we = addr_hit[156] & reg_we & !reg_error; + + assign alert_en_shadowed_51_wd = reg_wdata[0]; + assign alert_en_shadowed_52_re = addr_hit[157] & reg_re & !reg_error; + assign alert_en_shadowed_52_we = addr_hit[157] & reg_we & !reg_error; + + assign alert_en_shadowed_52_wd = reg_wdata[0]; + assign alert_en_shadowed_53_re = addr_hit[158] & reg_re & !reg_error; + assign alert_en_shadowed_53_we = addr_hit[158] & reg_we & !reg_error; + + assign alert_en_shadowed_53_wd = reg_wdata[0]; + assign alert_en_shadowed_54_re = addr_hit[159] & reg_re & !reg_error; + assign alert_en_shadowed_54_we = addr_hit[159] & reg_we & !reg_error; + + assign alert_en_shadowed_54_wd = reg_wdata[0]; + assign alert_en_shadowed_55_re = addr_hit[160] & reg_re & !reg_error; + assign alert_en_shadowed_55_we = addr_hit[160] & reg_we & !reg_error; + + assign alert_en_shadowed_55_wd = reg_wdata[0]; + assign alert_en_shadowed_56_re = addr_hit[161] & reg_re & !reg_error; + assign alert_en_shadowed_56_we = addr_hit[161] & reg_we & !reg_error; + + assign alert_en_shadowed_56_wd = reg_wdata[0]; + assign alert_en_shadowed_57_re = addr_hit[162] & reg_re & !reg_error; + assign alert_en_shadowed_57_we = addr_hit[162] & reg_we & !reg_error; + + assign alert_en_shadowed_57_wd = reg_wdata[0]; + assign alert_en_shadowed_58_re = addr_hit[163] & reg_re & !reg_error; + assign alert_en_shadowed_58_we = addr_hit[163] & reg_we & !reg_error; + + assign alert_en_shadowed_58_wd = reg_wdata[0]; + assign alert_en_shadowed_59_re = addr_hit[164] & reg_re & !reg_error; + assign alert_en_shadowed_59_we = addr_hit[164] & reg_we & !reg_error; + + assign alert_en_shadowed_59_wd = reg_wdata[0]; + assign alert_en_shadowed_60_re = addr_hit[165] & reg_re & !reg_error; + assign alert_en_shadowed_60_we = addr_hit[165] & reg_we & !reg_error; + + assign alert_en_shadowed_60_wd = reg_wdata[0]; + assign alert_en_shadowed_61_re = addr_hit[166] & reg_re & !reg_error; + assign alert_en_shadowed_61_we = addr_hit[166] & reg_we & !reg_error; + + assign alert_en_shadowed_61_wd = reg_wdata[0]; + assign alert_en_shadowed_62_re = addr_hit[167] & reg_re & !reg_error; + assign alert_en_shadowed_62_we = addr_hit[167] & reg_we & !reg_error; + + assign alert_en_shadowed_62_wd = reg_wdata[0]; + assign alert_en_shadowed_63_re = addr_hit[168] & reg_re & !reg_error; + assign alert_en_shadowed_63_we = addr_hit[168] & reg_we & !reg_error; + + assign alert_en_shadowed_63_wd = reg_wdata[0]; + assign alert_en_shadowed_64_re = addr_hit[169] & reg_re & !reg_error; + assign alert_en_shadowed_64_we = addr_hit[169] & reg_we & !reg_error; + + assign alert_en_shadowed_64_wd = reg_wdata[0]; + assign alert_en_shadowed_65_re = addr_hit[170] & reg_re & !reg_error; + assign alert_en_shadowed_65_we = addr_hit[170] & reg_we & !reg_error; + + assign alert_en_shadowed_65_wd = reg_wdata[0]; + assign alert_en_shadowed_66_re = addr_hit[171] & reg_re & !reg_error; + assign alert_en_shadowed_66_we = addr_hit[171] & reg_we & !reg_error; + + assign alert_en_shadowed_66_wd = reg_wdata[0]; + assign alert_en_shadowed_67_re = addr_hit[172] & reg_re & !reg_error; + assign alert_en_shadowed_67_we = addr_hit[172] & reg_we & !reg_error; + + assign alert_en_shadowed_67_wd = reg_wdata[0]; + assign alert_en_shadowed_68_re = addr_hit[173] & reg_re & !reg_error; + assign alert_en_shadowed_68_we = addr_hit[173] & reg_we & !reg_error; + + assign alert_en_shadowed_68_wd = reg_wdata[0]; + assign alert_en_shadowed_69_re = addr_hit[174] & reg_re & !reg_error; + assign alert_en_shadowed_69_we = addr_hit[174] & reg_we & !reg_error; + + assign alert_en_shadowed_69_wd = reg_wdata[0]; + assign alert_en_shadowed_70_re = addr_hit[175] & reg_re & !reg_error; + assign alert_en_shadowed_70_we = addr_hit[175] & reg_we & !reg_error; + + assign alert_en_shadowed_70_wd = reg_wdata[0]; + assign alert_en_shadowed_71_re = addr_hit[176] & reg_re & !reg_error; + assign alert_en_shadowed_71_we = addr_hit[176] & reg_we & !reg_error; + + assign alert_en_shadowed_71_wd = reg_wdata[0]; + assign alert_en_shadowed_72_re = addr_hit[177] & reg_re & !reg_error; + assign alert_en_shadowed_72_we = addr_hit[177] & reg_we & !reg_error; + + assign alert_en_shadowed_72_wd = reg_wdata[0]; + assign alert_en_shadowed_73_re = addr_hit[178] & reg_re & !reg_error; + assign alert_en_shadowed_73_we = addr_hit[178] & reg_we & !reg_error; + + assign alert_en_shadowed_73_wd = reg_wdata[0]; + assign alert_en_shadowed_74_re = addr_hit[179] & reg_re & !reg_error; + assign alert_en_shadowed_74_we = addr_hit[179] & reg_we & !reg_error; + + assign alert_en_shadowed_74_wd = reg_wdata[0]; + assign alert_en_shadowed_75_re = addr_hit[180] & reg_re & !reg_error; + assign alert_en_shadowed_75_we = addr_hit[180] & reg_we & !reg_error; + + assign alert_en_shadowed_75_wd = reg_wdata[0]; + assign alert_en_shadowed_76_re = addr_hit[181] & reg_re & !reg_error; + assign alert_en_shadowed_76_we = addr_hit[181] & reg_we & !reg_error; + + assign alert_en_shadowed_76_wd = reg_wdata[0]; + assign alert_en_shadowed_77_re = addr_hit[182] & reg_re & !reg_error; + assign alert_en_shadowed_77_we = addr_hit[182] & reg_we & !reg_error; + + assign alert_en_shadowed_77_wd = reg_wdata[0]; + assign alert_en_shadowed_78_re = addr_hit[183] & reg_re & !reg_error; + assign alert_en_shadowed_78_we = addr_hit[183] & reg_we & !reg_error; + + assign alert_en_shadowed_78_wd = reg_wdata[0]; + assign alert_en_shadowed_79_re = addr_hit[184] & reg_re & !reg_error; + assign alert_en_shadowed_79_we = addr_hit[184] & reg_we & !reg_error; + + assign alert_en_shadowed_79_wd = reg_wdata[0]; + assign alert_en_shadowed_80_re = addr_hit[185] & reg_re & !reg_error; + assign alert_en_shadowed_80_we = addr_hit[185] & reg_we & !reg_error; + + assign alert_en_shadowed_80_wd = reg_wdata[0]; + assign alert_en_shadowed_81_re = addr_hit[186] & reg_re & !reg_error; + assign alert_en_shadowed_81_we = addr_hit[186] & reg_we & !reg_error; + + assign alert_en_shadowed_81_wd = reg_wdata[0]; + assign alert_en_shadowed_82_re = addr_hit[187] & reg_re & !reg_error; + assign alert_en_shadowed_82_we = addr_hit[187] & reg_we & !reg_error; + + assign alert_en_shadowed_82_wd = reg_wdata[0]; + assign alert_en_shadowed_83_re = addr_hit[188] & reg_re & !reg_error; + assign alert_en_shadowed_83_we = addr_hit[188] & reg_we & !reg_error; + + assign alert_en_shadowed_83_wd = reg_wdata[0]; + assign alert_en_shadowed_84_re = addr_hit[189] & reg_re & !reg_error; + assign alert_en_shadowed_84_we = addr_hit[189] & reg_we & !reg_error; + + assign alert_en_shadowed_84_wd = reg_wdata[0]; + assign alert_en_shadowed_85_re = addr_hit[190] & reg_re & !reg_error; + assign alert_en_shadowed_85_we = addr_hit[190] & reg_we & !reg_error; + + assign alert_en_shadowed_85_wd = reg_wdata[0]; + assign alert_en_shadowed_86_re = addr_hit[191] & reg_re & !reg_error; + assign alert_en_shadowed_86_we = addr_hit[191] & reg_we & !reg_error; + + assign alert_en_shadowed_86_wd = reg_wdata[0]; + assign alert_en_shadowed_87_re = addr_hit[192] & reg_re & !reg_error; + assign alert_en_shadowed_87_we = addr_hit[192] & reg_we & !reg_error; + + assign alert_en_shadowed_87_wd = reg_wdata[0]; + assign alert_en_shadowed_88_re = addr_hit[193] & reg_re & !reg_error; + assign alert_en_shadowed_88_we = addr_hit[193] & reg_we & !reg_error; + + assign alert_en_shadowed_88_wd = reg_wdata[0]; + assign alert_en_shadowed_89_re = addr_hit[194] & reg_re & !reg_error; + assign alert_en_shadowed_89_we = addr_hit[194] & reg_we & !reg_error; + + assign alert_en_shadowed_89_wd = reg_wdata[0]; + assign alert_en_shadowed_90_re = addr_hit[195] & reg_re & !reg_error; + assign alert_en_shadowed_90_we = addr_hit[195] & reg_we & !reg_error; + + assign alert_en_shadowed_90_wd = reg_wdata[0]; + assign alert_en_shadowed_91_re = addr_hit[196] & reg_re & !reg_error; + assign alert_en_shadowed_91_we = addr_hit[196] & reg_we & !reg_error; + + assign alert_en_shadowed_91_wd = reg_wdata[0]; + assign alert_en_shadowed_92_re = addr_hit[197] & reg_re & !reg_error; + assign alert_en_shadowed_92_we = addr_hit[197] & reg_we & !reg_error; + + assign alert_en_shadowed_92_wd = reg_wdata[0]; + assign alert_en_shadowed_93_re = addr_hit[198] & reg_re & !reg_error; + assign alert_en_shadowed_93_we = addr_hit[198] & reg_we & !reg_error; + + assign alert_en_shadowed_93_wd = reg_wdata[0]; + assign alert_en_shadowed_94_re = addr_hit[199] & reg_re & !reg_error; + assign alert_en_shadowed_94_we = addr_hit[199] & reg_we & !reg_error; + + assign alert_en_shadowed_94_wd = reg_wdata[0]; + assign alert_en_shadowed_95_re = addr_hit[200] & reg_re & !reg_error; + assign alert_en_shadowed_95_we = addr_hit[200] & reg_we & !reg_error; + + assign alert_en_shadowed_95_wd = reg_wdata[0]; + assign alert_en_shadowed_96_re = addr_hit[201] & reg_re & !reg_error; + assign alert_en_shadowed_96_we = addr_hit[201] & reg_we & !reg_error; + + assign alert_en_shadowed_96_wd = reg_wdata[0]; + assign alert_en_shadowed_97_re = addr_hit[202] & reg_re & !reg_error; + assign alert_en_shadowed_97_we = addr_hit[202] & reg_we & !reg_error; + + assign alert_en_shadowed_97_wd = reg_wdata[0]; + assign alert_en_shadowed_98_re = addr_hit[203] & reg_re & !reg_error; + assign alert_en_shadowed_98_we = addr_hit[203] & reg_we & !reg_error; + + assign alert_en_shadowed_98_wd = reg_wdata[0]; + assign alert_class_shadowed_0_re = addr_hit[204] & reg_re & !reg_error; + assign alert_class_shadowed_0_we = addr_hit[204] & reg_we & !reg_error; + + assign alert_class_shadowed_0_wd = reg_wdata[1:0]; + assign alert_class_shadowed_1_re = addr_hit[205] & reg_re & !reg_error; + assign alert_class_shadowed_1_we = addr_hit[205] & reg_we & !reg_error; + + assign alert_class_shadowed_1_wd = reg_wdata[1:0]; + assign alert_class_shadowed_2_re = addr_hit[206] & reg_re & !reg_error; + assign alert_class_shadowed_2_we = addr_hit[206] & reg_we & !reg_error; + + assign alert_class_shadowed_2_wd = reg_wdata[1:0]; + assign alert_class_shadowed_3_re = addr_hit[207] & reg_re & !reg_error; + assign alert_class_shadowed_3_we = addr_hit[207] & reg_we & !reg_error; + + assign alert_class_shadowed_3_wd = reg_wdata[1:0]; + assign alert_class_shadowed_4_re = addr_hit[208] & reg_re & !reg_error; + assign alert_class_shadowed_4_we = addr_hit[208] & reg_we & !reg_error; + + assign alert_class_shadowed_4_wd = reg_wdata[1:0]; + assign alert_class_shadowed_5_re = addr_hit[209] & reg_re & !reg_error; + assign alert_class_shadowed_5_we = addr_hit[209] & reg_we & !reg_error; + + assign alert_class_shadowed_5_wd = reg_wdata[1:0]; + assign alert_class_shadowed_6_re = addr_hit[210] & reg_re & !reg_error; + assign alert_class_shadowed_6_we = addr_hit[210] & reg_we & !reg_error; + + assign alert_class_shadowed_6_wd = reg_wdata[1:0]; + assign alert_class_shadowed_7_re = addr_hit[211] & reg_re & !reg_error; + assign alert_class_shadowed_7_we = addr_hit[211] & reg_we & !reg_error; + + assign alert_class_shadowed_7_wd = reg_wdata[1:0]; + assign alert_class_shadowed_8_re = addr_hit[212] & reg_re & !reg_error; + assign alert_class_shadowed_8_we = addr_hit[212] & reg_we & !reg_error; + + assign alert_class_shadowed_8_wd = reg_wdata[1:0]; + assign alert_class_shadowed_9_re = addr_hit[213] & reg_re & !reg_error; + assign alert_class_shadowed_9_we = addr_hit[213] & reg_we & !reg_error; + + assign alert_class_shadowed_9_wd = reg_wdata[1:0]; + assign alert_class_shadowed_10_re = addr_hit[214] & reg_re & !reg_error; + assign alert_class_shadowed_10_we = addr_hit[214] & reg_we & !reg_error; + + assign alert_class_shadowed_10_wd = reg_wdata[1:0]; + assign alert_class_shadowed_11_re = addr_hit[215] & reg_re & !reg_error; + assign alert_class_shadowed_11_we = addr_hit[215] & reg_we & !reg_error; + + assign alert_class_shadowed_11_wd = reg_wdata[1:0]; + assign alert_class_shadowed_12_re = addr_hit[216] & reg_re & !reg_error; + assign alert_class_shadowed_12_we = addr_hit[216] & reg_we & !reg_error; + + assign alert_class_shadowed_12_wd = reg_wdata[1:0]; + assign alert_class_shadowed_13_re = addr_hit[217] & reg_re & !reg_error; + assign alert_class_shadowed_13_we = addr_hit[217] & reg_we & !reg_error; + + assign alert_class_shadowed_13_wd = reg_wdata[1:0]; + assign alert_class_shadowed_14_re = addr_hit[218] & reg_re & !reg_error; + assign alert_class_shadowed_14_we = addr_hit[218] & reg_we & !reg_error; + + assign alert_class_shadowed_14_wd = reg_wdata[1:0]; + assign alert_class_shadowed_15_re = addr_hit[219] & reg_re & !reg_error; + assign alert_class_shadowed_15_we = addr_hit[219] & reg_we & !reg_error; + + assign alert_class_shadowed_15_wd = reg_wdata[1:0]; + assign alert_class_shadowed_16_re = addr_hit[220] & reg_re & !reg_error; + assign alert_class_shadowed_16_we = addr_hit[220] & reg_we & !reg_error; + + assign alert_class_shadowed_16_wd = reg_wdata[1:0]; + assign alert_class_shadowed_17_re = addr_hit[221] & reg_re & !reg_error; + assign alert_class_shadowed_17_we = addr_hit[221] & reg_we & !reg_error; + + assign alert_class_shadowed_17_wd = reg_wdata[1:0]; + assign alert_class_shadowed_18_re = addr_hit[222] & reg_re & !reg_error; + assign alert_class_shadowed_18_we = addr_hit[222] & reg_we & !reg_error; + + assign alert_class_shadowed_18_wd = reg_wdata[1:0]; + assign alert_class_shadowed_19_re = addr_hit[223] & reg_re & !reg_error; + assign alert_class_shadowed_19_we = addr_hit[223] & reg_we & !reg_error; + + assign alert_class_shadowed_19_wd = reg_wdata[1:0]; + assign alert_class_shadowed_20_re = addr_hit[224] & reg_re & !reg_error; + assign alert_class_shadowed_20_we = addr_hit[224] & reg_we & !reg_error; + + assign alert_class_shadowed_20_wd = reg_wdata[1:0]; + assign alert_class_shadowed_21_re = addr_hit[225] & reg_re & !reg_error; + assign alert_class_shadowed_21_we = addr_hit[225] & reg_we & !reg_error; + + assign alert_class_shadowed_21_wd = reg_wdata[1:0]; + assign alert_class_shadowed_22_re = addr_hit[226] & reg_re & !reg_error; + assign alert_class_shadowed_22_we = addr_hit[226] & reg_we & !reg_error; + + assign alert_class_shadowed_22_wd = reg_wdata[1:0]; + assign alert_class_shadowed_23_re = addr_hit[227] & reg_re & !reg_error; + assign alert_class_shadowed_23_we = addr_hit[227] & reg_we & !reg_error; + + assign alert_class_shadowed_23_wd = reg_wdata[1:0]; + assign alert_class_shadowed_24_re = addr_hit[228] & reg_re & !reg_error; + assign alert_class_shadowed_24_we = addr_hit[228] & reg_we & !reg_error; + + assign alert_class_shadowed_24_wd = reg_wdata[1:0]; + assign alert_class_shadowed_25_re = addr_hit[229] & reg_re & !reg_error; + assign alert_class_shadowed_25_we = addr_hit[229] & reg_we & !reg_error; + + assign alert_class_shadowed_25_wd = reg_wdata[1:0]; + assign alert_class_shadowed_26_re = addr_hit[230] & reg_re & !reg_error; + assign alert_class_shadowed_26_we = addr_hit[230] & reg_we & !reg_error; + + assign alert_class_shadowed_26_wd = reg_wdata[1:0]; + assign alert_class_shadowed_27_re = addr_hit[231] & reg_re & !reg_error; + assign alert_class_shadowed_27_we = addr_hit[231] & reg_we & !reg_error; + + assign alert_class_shadowed_27_wd = reg_wdata[1:0]; + assign alert_class_shadowed_28_re = addr_hit[232] & reg_re & !reg_error; + assign alert_class_shadowed_28_we = addr_hit[232] & reg_we & !reg_error; + + assign alert_class_shadowed_28_wd = reg_wdata[1:0]; + assign alert_class_shadowed_29_re = addr_hit[233] & reg_re & !reg_error; + assign alert_class_shadowed_29_we = addr_hit[233] & reg_we & !reg_error; + + assign alert_class_shadowed_29_wd = reg_wdata[1:0]; + assign alert_class_shadowed_30_re = addr_hit[234] & reg_re & !reg_error; + assign alert_class_shadowed_30_we = addr_hit[234] & reg_we & !reg_error; + + assign alert_class_shadowed_30_wd = reg_wdata[1:0]; + assign alert_class_shadowed_31_re = addr_hit[235] & reg_re & !reg_error; + assign alert_class_shadowed_31_we = addr_hit[235] & reg_we & !reg_error; + + assign alert_class_shadowed_31_wd = reg_wdata[1:0]; + assign alert_class_shadowed_32_re = addr_hit[236] & reg_re & !reg_error; + assign alert_class_shadowed_32_we = addr_hit[236] & reg_we & !reg_error; + + assign alert_class_shadowed_32_wd = reg_wdata[1:0]; + assign alert_class_shadowed_33_re = addr_hit[237] & reg_re & !reg_error; + assign alert_class_shadowed_33_we = addr_hit[237] & reg_we & !reg_error; + + assign alert_class_shadowed_33_wd = reg_wdata[1:0]; + assign alert_class_shadowed_34_re = addr_hit[238] & reg_re & !reg_error; + assign alert_class_shadowed_34_we = addr_hit[238] & reg_we & !reg_error; + + assign alert_class_shadowed_34_wd = reg_wdata[1:0]; + assign alert_class_shadowed_35_re = addr_hit[239] & reg_re & !reg_error; + assign alert_class_shadowed_35_we = addr_hit[239] & reg_we & !reg_error; + + assign alert_class_shadowed_35_wd = reg_wdata[1:0]; + assign alert_class_shadowed_36_re = addr_hit[240] & reg_re & !reg_error; + assign alert_class_shadowed_36_we = addr_hit[240] & reg_we & !reg_error; + + assign alert_class_shadowed_36_wd = reg_wdata[1:0]; + assign alert_class_shadowed_37_re = addr_hit[241] & reg_re & !reg_error; + assign alert_class_shadowed_37_we = addr_hit[241] & reg_we & !reg_error; + + assign alert_class_shadowed_37_wd = reg_wdata[1:0]; + assign alert_class_shadowed_38_re = addr_hit[242] & reg_re & !reg_error; + assign alert_class_shadowed_38_we = addr_hit[242] & reg_we & !reg_error; + + assign alert_class_shadowed_38_wd = reg_wdata[1:0]; + assign alert_class_shadowed_39_re = addr_hit[243] & reg_re & !reg_error; + assign alert_class_shadowed_39_we = addr_hit[243] & reg_we & !reg_error; + + assign alert_class_shadowed_39_wd = reg_wdata[1:0]; + assign alert_class_shadowed_40_re = addr_hit[244] & reg_re & !reg_error; + assign alert_class_shadowed_40_we = addr_hit[244] & reg_we & !reg_error; + + assign alert_class_shadowed_40_wd = reg_wdata[1:0]; + assign alert_class_shadowed_41_re = addr_hit[245] & reg_re & !reg_error; + assign alert_class_shadowed_41_we = addr_hit[245] & reg_we & !reg_error; + + assign alert_class_shadowed_41_wd = reg_wdata[1:0]; + assign alert_class_shadowed_42_re = addr_hit[246] & reg_re & !reg_error; + assign alert_class_shadowed_42_we = addr_hit[246] & reg_we & !reg_error; + + assign alert_class_shadowed_42_wd = reg_wdata[1:0]; + assign alert_class_shadowed_43_re = addr_hit[247] & reg_re & !reg_error; + assign alert_class_shadowed_43_we = addr_hit[247] & reg_we & !reg_error; + + assign alert_class_shadowed_43_wd = reg_wdata[1:0]; + assign alert_class_shadowed_44_re = addr_hit[248] & reg_re & !reg_error; + assign alert_class_shadowed_44_we = addr_hit[248] & reg_we & !reg_error; + + assign alert_class_shadowed_44_wd = reg_wdata[1:0]; + assign alert_class_shadowed_45_re = addr_hit[249] & reg_re & !reg_error; + assign alert_class_shadowed_45_we = addr_hit[249] & reg_we & !reg_error; + + assign alert_class_shadowed_45_wd = reg_wdata[1:0]; + assign alert_class_shadowed_46_re = addr_hit[250] & reg_re & !reg_error; + assign alert_class_shadowed_46_we = addr_hit[250] & reg_we & !reg_error; + + assign alert_class_shadowed_46_wd = reg_wdata[1:0]; + assign alert_class_shadowed_47_re = addr_hit[251] & reg_re & !reg_error; + assign alert_class_shadowed_47_we = addr_hit[251] & reg_we & !reg_error; + + assign alert_class_shadowed_47_wd = reg_wdata[1:0]; + assign alert_class_shadowed_48_re = addr_hit[252] & reg_re & !reg_error; + assign alert_class_shadowed_48_we = addr_hit[252] & reg_we & !reg_error; + + assign alert_class_shadowed_48_wd = reg_wdata[1:0]; + assign alert_class_shadowed_49_re = addr_hit[253] & reg_re & !reg_error; + assign alert_class_shadowed_49_we = addr_hit[253] & reg_we & !reg_error; + + assign alert_class_shadowed_49_wd = reg_wdata[1:0]; + assign alert_class_shadowed_50_re = addr_hit[254] & reg_re & !reg_error; + assign alert_class_shadowed_50_we = addr_hit[254] & reg_we & !reg_error; + + assign alert_class_shadowed_50_wd = reg_wdata[1:0]; + assign alert_class_shadowed_51_re = addr_hit[255] & reg_re & !reg_error; + assign alert_class_shadowed_51_we = addr_hit[255] & reg_we & !reg_error; + + assign alert_class_shadowed_51_wd = reg_wdata[1:0]; + assign alert_class_shadowed_52_re = addr_hit[256] & reg_re & !reg_error; + assign alert_class_shadowed_52_we = addr_hit[256] & reg_we & !reg_error; + + assign alert_class_shadowed_52_wd = reg_wdata[1:0]; + assign alert_class_shadowed_53_re = addr_hit[257] & reg_re & !reg_error; + assign alert_class_shadowed_53_we = addr_hit[257] & reg_we & !reg_error; + + assign alert_class_shadowed_53_wd = reg_wdata[1:0]; + assign alert_class_shadowed_54_re = addr_hit[258] & reg_re & !reg_error; + assign alert_class_shadowed_54_we = addr_hit[258] & reg_we & !reg_error; + + assign alert_class_shadowed_54_wd = reg_wdata[1:0]; + assign alert_class_shadowed_55_re = addr_hit[259] & reg_re & !reg_error; + assign alert_class_shadowed_55_we = addr_hit[259] & reg_we & !reg_error; + + assign alert_class_shadowed_55_wd = reg_wdata[1:0]; + assign alert_class_shadowed_56_re = addr_hit[260] & reg_re & !reg_error; + assign alert_class_shadowed_56_we = addr_hit[260] & reg_we & !reg_error; + + assign alert_class_shadowed_56_wd = reg_wdata[1:0]; + assign alert_class_shadowed_57_re = addr_hit[261] & reg_re & !reg_error; + assign alert_class_shadowed_57_we = addr_hit[261] & reg_we & !reg_error; + + assign alert_class_shadowed_57_wd = reg_wdata[1:0]; + assign alert_class_shadowed_58_re = addr_hit[262] & reg_re & !reg_error; + assign alert_class_shadowed_58_we = addr_hit[262] & reg_we & !reg_error; + + assign alert_class_shadowed_58_wd = reg_wdata[1:0]; + assign alert_class_shadowed_59_re = addr_hit[263] & reg_re & !reg_error; + assign alert_class_shadowed_59_we = addr_hit[263] & reg_we & !reg_error; + + assign alert_class_shadowed_59_wd = reg_wdata[1:0]; + assign alert_class_shadowed_60_re = addr_hit[264] & reg_re & !reg_error; + assign alert_class_shadowed_60_we = addr_hit[264] & reg_we & !reg_error; + + assign alert_class_shadowed_60_wd = reg_wdata[1:0]; + assign alert_class_shadowed_61_re = addr_hit[265] & reg_re & !reg_error; + assign alert_class_shadowed_61_we = addr_hit[265] & reg_we & !reg_error; + + assign alert_class_shadowed_61_wd = reg_wdata[1:0]; + assign alert_class_shadowed_62_re = addr_hit[266] & reg_re & !reg_error; + assign alert_class_shadowed_62_we = addr_hit[266] & reg_we & !reg_error; + + assign alert_class_shadowed_62_wd = reg_wdata[1:0]; + assign alert_class_shadowed_63_re = addr_hit[267] & reg_re & !reg_error; + assign alert_class_shadowed_63_we = addr_hit[267] & reg_we & !reg_error; + + assign alert_class_shadowed_63_wd = reg_wdata[1:0]; + assign alert_class_shadowed_64_re = addr_hit[268] & reg_re & !reg_error; + assign alert_class_shadowed_64_we = addr_hit[268] & reg_we & !reg_error; + + assign alert_class_shadowed_64_wd = reg_wdata[1:0]; + assign alert_class_shadowed_65_re = addr_hit[269] & reg_re & !reg_error; + assign alert_class_shadowed_65_we = addr_hit[269] & reg_we & !reg_error; + + assign alert_class_shadowed_65_wd = reg_wdata[1:0]; + assign alert_class_shadowed_66_re = addr_hit[270] & reg_re & !reg_error; + assign alert_class_shadowed_66_we = addr_hit[270] & reg_we & !reg_error; + + assign alert_class_shadowed_66_wd = reg_wdata[1:0]; + assign alert_class_shadowed_67_re = addr_hit[271] & reg_re & !reg_error; + assign alert_class_shadowed_67_we = addr_hit[271] & reg_we & !reg_error; + + assign alert_class_shadowed_67_wd = reg_wdata[1:0]; + assign alert_class_shadowed_68_re = addr_hit[272] & reg_re & !reg_error; + assign alert_class_shadowed_68_we = addr_hit[272] & reg_we & !reg_error; + + assign alert_class_shadowed_68_wd = reg_wdata[1:0]; + assign alert_class_shadowed_69_re = addr_hit[273] & reg_re & !reg_error; + assign alert_class_shadowed_69_we = addr_hit[273] & reg_we & !reg_error; + + assign alert_class_shadowed_69_wd = reg_wdata[1:0]; + assign alert_class_shadowed_70_re = addr_hit[274] & reg_re & !reg_error; + assign alert_class_shadowed_70_we = addr_hit[274] & reg_we & !reg_error; + + assign alert_class_shadowed_70_wd = reg_wdata[1:0]; + assign alert_class_shadowed_71_re = addr_hit[275] & reg_re & !reg_error; + assign alert_class_shadowed_71_we = addr_hit[275] & reg_we & !reg_error; + + assign alert_class_shadowed_71_wd = reg_wdata[1:0]; + assign alert_class_shadowed_72_re = addr_hit[276] & reg_re & !reg_error; + assign alert_class_shadowed_72_we = addr_hit[276] & reg_we & !reg_error; + + assign alert_class_shadowed_72_wd = reg_wdata[1:0]; + assign alert_class_shadowed_73_re = addr_hit[277] & reg_re & !reg_error; + assign alert_class_shadowed_73_we = addr_hit[277] & reg_we & !reg_error; + + assign alert_class_shadowed_73_wd = reg_wdata[1:0]; + assign alert_class_shadowed_74_re = addr_hit[278] & reg_re & !reg_error; + assign alert_class_shadowed_74_we = addr_hit[278] & reg_we & !reg_error; + + assign alert_class_shadowed_74_wd = reg_wdata[1:0]; + assign alert_class_shadowed_75_re = addr_hit[279] & reg_re & !reg_error; + assign alert_class_shadowed_75_we = addr_hit[279] & reg_we & !reg_error; + + assign alert_class_shadowed_75_wd = reg_wdata[1:0]; + assign alert_class_shadowed_76_re = addr_hit[280] & reg_re & !reg_error; + assign alert_class_shadowed_76_we = addr_hit[280] & reg_we & !reg_error; + + assign alert_class_shadowed_76_wd = reg_wdata[1:0]; + assign alert_class_shadowed_77_re = addr_hit[281] & reg_re & !reg_error; + assign alert_class_shadowed_77_we = addr_hit[281] & reg_we & !reg_error; + + assign alert_class_shadowed_77_wd = reg_wdata[1:0]; + assign alert_class_shadowed_78_re = addr_hit[282] & reg_re & !reg_error; + assign alert_class_shadowed_78_we = addr_hit[282] & reg_we & !reg_error; + + assign alert_class_shadowed_78_wd = reg_wdata[1:0]; + assign alert_class_shadowed_79_re = addr_hit[283] & reg_re & !reg_error; + assign alert_class_shadowed_79_we = addr_hit[283] & reg_we & !reg_error; + + assign alert_class_shadowed_79_wd = reg_wdata[1:0]; + assign alert_class_shadowed_80_re = addr_hit[284] & reg_re & !reg_error; + assign alert_class_shadowed_80_we = addr_hit[284] & reg_we & !reg_error; + + assign alert_class_shadowed_80_wd = reg_wdata[1:0]; + assign alert_class_shadowed_81_re = addr_hit[285] & reg_re & !reg_error; + assign alert_class_shadowed_81_we = addr_hit[285] & reg_we & !reg_error; + + assign alert_class_shadowed_81_wd = reg_wdata[1:0]; + assign alert_class_shadowed_82_re = addr_hit[286] & reg_re & !reg_error; + assign alert_class_shadowed_82_we = addr_hit[286] & reg_we & !reg_error; + + assign alert_class_shadowed_82_wd = reg_wdata[1:0]; + assign alert_class_shadowed_83_re = addr_hit[287] & reg_re & !reg_error; + assign alert_class_shadowed_83_we = addr_hit[287] & reg_we & !reg_error; + + assign alert_class_shadowed_83_wd = reg_wdata[1:0]; + assign alert_class_shadowed_84_re = addr_hit[288] & reg_re & !reg_error; + assign alert_class_shadowed_84_we = addr_hit[288] & reg_we & !reg_error; + + assign alert_class_shadowed_84_wd = reg_wdata[1:0]; + assign alert_class_shadowed_85_re = addr_hit[289] & reg_re & !reg_error; + assign alert_class_shadowed_85_we = addr_hit[289] & reg_we & !reg_error; + + assign alert_class_shadowed_85_wd = reg_wdata[1:0]; + assign alert_class_shadowed_86_re = addr_hit[290] & reg_re & !reg_error; + assign alert_class_shadowed_86_we = addr_hit[290] & reg_we & !reg_error; + + assign alert_class_shadowed_86_wd = reg_wdata[1:0]; + assign alert_class_shadowed_87_re = addr_hit[291] & reg_re & !reg_error; + assign alert_class_shadowed_87_we = addr_hit[291] & reg_we & !reg_error; + + assign alert_class_shadowed_87_wd = reg_wdata[1:0]; + assign alert_class_shadowed_88_re = addr_hit[292] & reg_re & !reg_error; + assign alert_class_shadowed_88_we = addr_hit[292] & reg_we & !reg_error; + + assign alert_class_shadowed_88_wd = reg_wdata[1:0]; + assign alert_class_shadowed_89_re = addr_hit[293] & reg_re & !reg_error; + assign alert_class_shadowed_89_we = addr_hit[293] & reg_we & !reg_error; + + assign alert_class_shadowed_89_wd = reg_wdata[1:0]; + assign alert_class_shadowed_90_re = addr_hit[294] & reg_re & !reg_error; + assign alert_class_shadowed_90_we = addr_hit[294] & reg_we & !reg_error; + + assign alert_class_shadowed_90_wd = reg_wdata[1:0]; + assign alert_class_shadowed_91_re = addr_hit[295] & reg_re & !reg_error; + assign alert_class_shadowed_91_we = addr_hit[295] & reg_we & !reg_error; + + assign alert_class_shadowed_91_wd = reg_wdata[1:0]; + assign alert_class_shadowed_92_re = addr_hit[296] & reg_re & !reg_error; + assign alert_class_shadowed_92_we = addr_hit[296] & reg_we & !reg_error; + + assign alert_class_shadowed_92_wd = reg_wdata[1:0]; + assign alert_class_shadowed_93_re = addr_hit[297] & reg_re & !reg_error; + assign alert_class_shadowed_93_we = addr_hit[297] & reg_we & !reg_error; + + assign alert_class_shadowed_93_wd = reg_wdata[1:0]; + assign alert_class_shadowed_94_re = addr_hit[298] & reg_re & !reg_error; + assign alert_class_shadowed_94_we = addr_hit[298] & reg_we & !reg_error; + + assign alert_class_shadowed_94_wd = reg_wdata[1:0]; + assign alert_class_shadowed_95_re = addr_hit[299] & reg_re & !reg_error; + assign alert_class_shadowed_95_we = addr_hit[299] & reg_we & !reg_error; + + assign alert_class_shadowed_95_wd = reg_wdata[1:0]; + assign alert_class_shadowed_96_re = addr_hit[300] & reg_re & !reg_error; + assign alert_class_shadowed_96_we = addr_hit[300] & reg_we & !reg_error; + + assign alert_class_shadowed_96_wd = reg_wdata[1:0]; + assign alert_class_shadowed_97_re = addr_hit[301] & reg_re & !reg_error; + assign alert_class_shadowed_97_we = addr_hit[301] & reg_we & !reg_error; + + assign alert_class_shadowed_97_wd = reg_wdata[1:0]; + assign alert_class_shadowed_98_re = addr_hit[302] & reg_re & !reg_error; + assign alert_class_shadowed_98_we = addr_hit[302] & reg_we & !reg_error; + + assign alert_class_shadowed_98_wd = reg_wdata[1:0]; + assign alert_cause_0_we = addr_hit[303] & reg_we & !reg_error; + + assign alert_cause_0_wd = reg_wdata[0]; + assign alert_cause_1_we = addr_hit[304] & reg_we & !reg_error; + + assign alert_cause_1_wd = reg_wdata[0]; + assign alert_cause_2_we = addr_hit[305] & reg_we & !reg_error; + + assign alert_cause_2_wd = reg_wdata[0]; + assign alert_cause_3_we = addr_hit[306] & reg_we & !reg_error; + + assign alert_cause_3_wd = reg_wdata[0]; + assign alert_cause_4_we = addr_hit[307] & reg_we & !reg_error; + + assign alert_cause_4_wd = reg_wdata[0]; + assign alert_cause_5_we = addr_hit[308] & reg_we & !reg_error; + + assign alert_cause_5_wd = reg_wdata[0]; + assign alert_cause_6_we = addr_hit[309] & reg_we & !reg_error; + + assign alert_cause_6_wd = reg_wdata[0]; + assign alert_cause_7_we = addr_hit[310] & reg_we & !reg_error; + + assign alert_cause_7_wd = reg_wdata[0]; + assign alert_cause_8_we = addr_hit[311] & reg_we & !reg_error; + + assign alert_cause_8_wd = reg_wdata[0]; + assign alert_cause_9_we = addr_hit[312] & reg_we & !reg_error; + + assign alert_cause_9_wd = reg_wdata[0]; + assign alert_cause_10_we = addr_hit[313] & reg_we & !reg_error; + + assign alert_cause_10_wd = reg_wdata[0]; + assign alert_cause_11_we = addr_hit[314] & reg_we & !reg_error; + + assign alert_cause_11_wd = reg_wdata[0]; + assign alert_cause_12_we = addr_hit[315] & reg_we & !reg_error; + + assign alert_cause_12_wd = reg_wdata[0]; + assign alert_cause_13_we = addr_hit[316] & reg_we & !reg_error; + + assign alert_cause_13_wd = reg_wdata[0]; + assign alert_cause_14_we = addr_hit[317] & reg_we & !reg_error; + + assign alert_cause_14_wd = reg_wdata[0]; + assign alert_cause_15_we = addr_hit[318] & reg_we & !reg_error; + + assign alert_cause_15_wd = reg_wdata[0]; + assign alert_cause_16_we = addr_hit[319] & reg_we & !reg_error; + + assign alert_cause_16_wd = reg_wdata[0]; + assign alert_cause_17_we = addr_hit[320] & reg_we & !reg_error; + + assign alert_cause_17_wd = reg_wdata[0]; + assign alert_cause_18_we = addr_hit[321] & reg_we & !reg_error; + + assign alert_cause_18_wd = reg_wdata[0]; + assign alert_cause_19_we = addr_hit[322] & reg_we & !reg_error; + + assign alert_cause_19_wd = reg_wdata[0]; + assign alert_cause_20_we = addr_hit[323] & reg_we & !reg_error; + + assign alert_cause_20_wd = reg_wdata[0]; + assign alert_cause_21_we = addr_hit[324] & reg_we & !reg_error; + + assign alert_cause_21_wd = reg_wdata[0]; + assign alert_cause_22_we = addr_hit[325] & reg_we & !reg_error; + + assign alert_cause_22_wd = reg_wdata[0]; + assign alert_cause_23_we = addr_hit[326] & reg_we & !reg_error; + + assign alert_cause_23_wd = reg_wdata[0]; + assign alert_cause_24_we = addr_hit[327] & reg_we & !reg_error; + + assign alert_cause_24_wd = reg_wdata[0]; + assign alert_cause_25_we = addr_hit[328] & reg_we & !reg_error; + + assign alert_cause_25_wd = reg_wdata[0]; + assign alert_cause_26_we = addr_hit[329] & reg_we & !reg_error; + + assign alert_cause_26_wd = reg_wdata[0]; + assign alert_cause_27_we = addr_hit[330] & reg_we & !reg_error; + + assign alert_cause_27_wd = reg_wdata[0]; + assign alert_cause_28_we = addr_hit[331] & reg_we & !reg_error; + + assign alert_cause_28_wd = reg_wdata[0]; + assign alert_cause_29_we = addr_hit[332] & reg_we & !reg_error; + + assign alert_cause_29_wd = reg_wdata[0]; + assign alert_cause_30_we = addr_hit[333] & reg_we & !reg_error; + + assign alert_cause_30_wd = reg_wdata[0]; + assign alert_cause_31_we = addr_hit[334] & reg_we & !reg_error; + + assign alert_cause_31_wd = reg_wdata[0]; + assign alert_cause_32_we = addr_hit[335] & reg_we & !reg_error; + + assign alert_cause_32_wd = reg_wdata[0]; + assign alert_cause_33_we = addr_hit[336] & reg_we & !reg_error; + + assign alert_cause_33_wd = reg_wdata[0]; + assign alert_cause_34_we = addr_hit[337] & reg_we & !reg_error; + + assign alert_cause_34_wd = reg_wdata[0]; + assign alert_cause_35_we = addr_hit[338] & reg_we & !reg_error; + + assign alert_cause_35_wd = reg_wdata[0]; + assign alert_cause_36_we = addr_hit[339] & reg_we & !reg_error; + + assign alert_cause_36_wd = reg_wdata[0]; + assign alert_cause_37_we = addr_hit[340] & reg_we & !reg_error; + + assign alert_cause_37_wd = reg_wdata[0]; + assign alert_cause_38_we = addr_hit[341] & reg_we & !reg_error; + + assign alert_cause_38_wd = reg_wdata[0]; + assign alert_cause_39_we = addr_hit[342] & reg_we & !reg_error; + + assign alert_cause_39_wd = reg_wdata[0]; + assign alert_cause_40_we = addr_hit[343] & reg_we & !reg_error; + + assign alert_cause_40_wd = reg_wdata[0]; + assign alert_cause_41_we = addr_hit[344] & reg_we & !reg_error; + + assign alert_cause_41_wd = reg_wdata[0]; + assign alert_cause_42_we = addr_hit[345] & reg_we & !reg_error; + + assign alert_cause_42_wd = reg_wdata[0]; + assign alert_cause_43_we = addr_hit[346] & reg_we & !reg_error; + + assign alert_cause_43_wd = reg_wdata[0]; + assign alert_cause_44_we = addr_hit[347] & reg_we & !reg_error; + + assign alert_cause_44_wd = reg_wdata[0]; + assign alert_cause_45_we = addr_hit[348] & reg_we & !reg_error; + + assign alert_cause_45_wd = reg_wdata[0]; + assign alert_cause_46_we = addr_hit[349] & reg_we & !reg_error; + + assign alert_cause_46_wd = reg_wdata[0]; + assign alert_cause_47_we = addr_hit[350] & reg_we & !reg_error; + + assign alert_cause_47_wd = reg_wdata[0]; + assign alert_cause_48_we = addr_hit[351] & reg_we & !reg_error; + + assign alert_cause_48_wd = reg_wdata[0]; + assign alert_cause_49_we = addr_hit[352] & reg_we & !reg_error; + + assign alert_cause_49_wd = reg_wdata[0]; + assign alert_cause_50_we = addr_hit[353] & reg_we & !reg_error; + + assign alert_cause_50_wd = reg_wdata[0]; + assign alert_cause_51_we = addr_hit[354] & reg_we & !reg_error; + + assign alert_cause_51_wd = reg_wdata[0]; + assign alert_cause_52_we = addr_hit[355] & reg_we & !reg_error; + + assign alert_cause_52_wd = reg_wdata[0]; + assign alert_cause_53_we = addr_hit[356] & reg_we & !reg_error; + + assign alert_cause_53_wd = reg_wdata[0]; + assign alert_cause_54_we = addr_hit[357] & reg_we & !reg_error; + + assign alert_cause_54_wd = reg_wdata[0]; + assign alert_cause_55_we = addr_hit[358] & reg_we & !reg_error; + + assign alert_cause_55_wd = reg_wdata[0]; + assign alert_cause_56_we = addr_hit[359] & reg_we & !reg_error; + + assign alert_cause_56_wd = reg_wdata[0]; + assign alert_cause_57_we = addr_hit[360] & reg_we & !reg_error; + + assign alert_cause_57_wd = reg_wdata[0]; + assign alert_cause_58_we = addr_hit[361] & reg_we & !reg_error; + + assign alert_cause_58_wd = reg_wdata[0]; + assign alert_cause_59_we = addr_hit[362] & reg_we & !reg_error; + + assign alert_cause_59_wd = reg_wdata[0]; + assign alert_cause_60_we = addr_hit[363] & reg_we & !reg_error; + + assign alert_cause_60_wd = reg_wdata[0]; + assign alert_cause_61_we = addr_hit[364] & reg_we & !reg_error; + + assign alert_cause_61_wd = reg_wdata[0]; + assign alert_cause_62_we = addr_hit[365] & reg_we & !reg_error; + + assign alert_cause_62_wd = reg_wdata[0]; + assign alert_cause_63_we = addr_hit[366] & reg_we & !reg_error; + + assign alert_cause_63_wd = reg_wdata[0]; + assign alert_cause_64_we = addr_hit[367] & reg_we & !reg_error; + + assign alert_cause_64_wd = reg_wdata[0]; + assign alert_cause_65_we = addr_hit[368] & reg_we & !reg_error; + + assign alert_cause_65_wd = reg_wdata[0]; + assign alert_cause_66_we = addr_hit[369] & reg_we & !reg_error; + + assign alert_cause_66_wd = reg_wdata[0]; + assign alert_cause_67_we = addr_hit[370] & reg_we & !reg_error; + + assign alert_cause_67_wd = reg_wdata[0]; + assign alert_cause_68_we = addr_hit[371] & reg_we & !reg_error; + + assign alert_cause_68_wd = reg_wdata[0]; + assign alert_cause_69_we = addr_hit[372] & reg_we & !reg_error; + + assign alert_cause_69_wd = reg_wdata[0]; + assign alert_cause_70_we = addr_hit[373] & reg_we & !reg_error; + + assign alert_cause_70_wd = reg_wdata[0]; + assign alert_cause_71_we = addr_hit[374] & reg_we & !reg_error; + + assign alert_cause_71_wd = reg_wdata[0]; + assign alert_cause_72_we = addr_hit[375] & reg_we & !reg_error; + + assign alert_cause_72_wd = reg_wdata[0]; + assign alert_cause_73_we = addr_hit[376] & reg_we & !reg_error; + + assign alert_cause_73_wd = reg_wdata[0]; + assign alert_cause_74_we = addr_hit[377] & reg_we & !reg_error; + + assign alert_cause_74_wd = reg_wdata[0]; + assign alert_cause_75_we = addr_hit[378] & reg_we & !reg_error; + + assign alert_cause_75_wd = reg_wdata[0]; + assign alert_cause_76_we = addr_hit[379] & reg_we & !reg_error; + + assign alert_cause_76_wd = reg_wdata[0]; + assign alert_cause_77_we = addr_hit[380] & reg_we & !reg_error; + + assign alert_cause_77_wd = reg_wdata[0]; + assign alert_cause_78_we = addr_hit[381] & reg_we & !reg_error; + + assign alert_cause_78_wd = reg_wdata[0]; + assign alert_cause_79_we = addr_hit[382] & reg_we & !reg_error; + + assign alert_cause_79_wd = reg_wdata[0]; + assign alert_cause_80_we = addr_hit[383] & reg_we & !reg_error; + + assign alert_cause_80_wd = reg_wdata[0]; + assign alert_cause_81_we = addr_hit[384] & reg_we & !reg_error; + + assign alert_cause_81_wd = reg_wdata[0]; + assign alert_cause_82_we = addr_hit[385] & reg_we & !reg_error; + + assign alert_cause_82_wd = reg_wdata[0]; + assign alert_cause_83_we = addr_hit[386] & reg_we & !reg_error; + + assign alert_cause_83_wd = reg_wdata[0]; + assign alert_cause_84_we = addr_hit[387] & reg_we & !reg_error; + + assign alert_cause_84_wd = reg_wdata[0]; + assign alert_cause_85_we = addr_hit[388] & reg_we & !reg_error; + + assign alert_cause_85_wd = reg_wdata[0]; + assign alert_cause_86_we = addr_hit[389] & reg_we & !reg_error; + + assign alert_cause_86_wd = reg_wdata[0]; + assign alert_cause_87_we = addr_hit[390] & reg_we & !reg_error; + + assign alert_cause_87_wd = reg_wdata[0]; + assign alert_cause_88_we = addr_hit[391] & reg_we & !reg_error; + + assign alert_cause_88_wd = reg_wdata[0]; + assign alert_cause_89_we = addr_hit[392] & reg_we & !reg_error; + + assign alert_cause_89_wd = reg_wdata[0]; + assign alert_cause_90_we = addr_hit[393] & reg_we & !reg_error; + + assign alert_cause_90_wd = reg_wdata[0]; + assign alert_cause_91_we = addr_hit[394] & reg_we & !reg_error; + + assign alert_cause_91_wd = reg_wdata[0]; + assign alert_cause_92_we = addr_hit[395] & reg_we & !reg_error; + + assign alert_cause_92_wd = reg_wdata[0]; + assign alert_cause_93_we = addr_hit[396] & reg_we & !reg_error; + + assign alert_cause_93_wd = reg_wdata[0]; + assign alert_cause_94_we = addr_hit[397] & reg_we & !reg_error; + + assign alert_cause_94_wd = reg_wdata[0]; + assign alert_cause_95_we = addr_hit[398] & reg_we & !reg_error; + + assign alert_cause_95_wd = reg_wdata[0]; + assign alert_cause_96_we = addr_hit[399] & reg_we & !reg_error; + + assign alert_cause_96_wd = reg_wdata[0]; + assign alert_cause_97_we = addr_hit[400] & reg_we & !reg_error; + + assign alert_cause_97_wd = reg_wdata[0]; + assign alert_cause_98_we = addr_hit[401] & reg_we & !reg_error; + + assign alert_cause_98_wd = reg_wdata[0]; + assign loc_alert_regwen_0_we = addr_hit[402] & reg_we & !reg_error; + + assign loc_alert_regwen_0_wd = reg_wdata[0]; + assign loc_alert_regwen_1_we = addr_hit[403] & reg_we & !reg_error; + + assign loc_alert_regwen_1_wd = reg_wdata[0]; + assign loc_alert_regwen_2_we = addr_hit[404] & reg_we & !reg_error; + + assign loc_alert_regwen_2_wd = reg_wdata[0]; + assign loc_alert_regwen_3_we = addr_hit[405] & reg_we & !reg_error; + + assign loc_alert_regwen_3_wd = reg_wdata[0]; + assign loc_alert_regwen_4_we = addr_hit[406] & reg_we & !reg_error; + + assign loc_alert_regwen_4_wd = reg_wdata[0]; + assign loc_alert_regwen_5_we = addr_hit[407] & reg_we & !reg_error; + + assign loc_alert_regwen_5_wd = reg_wdata[0]; + assign loc_alert_regwen_6_we = addr_hit[408] & reg_we & !reg_error; + + assign loc_alert_regwen_6_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_0_re = addr_hit[409] & reg_re & !reg_error; + assign loc_alert_en_shadowed_0_we = addr_hit[409] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_0_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_1_re = addr_hit[410] & reg_re & !reg_error; + assign loc_alert_en_shadowed_1_we = addr_hit[410] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_1_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_2_re = addr_hit[411] & reg_re & !reg_error; + assign loc_alert_en_shadowed_2_we = addr_hit[411] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_2_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_3_re = addr_hit[412] & reg_re & !reg_error; + assign loc_alert_en_shadowed_3_we = addr_hit[412] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_3_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_4_re = addr_hit[413] & reg_re & !reg_error; + assign loc_alert_en_shadowed_4_we = addr_hit[413] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_4_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_5_re = addr_hit[414] & reg_re & !reg_error; + assign loc_alert_en_shadowed_5_we = addr_hit[414] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_5_wd = reg_wdata[0]; + assign loc_alert_en_shadowed_6_re = addr_hit[415] & reg_re & !reg_error; + assign loc_alert_en_shadowed_6_we = addr_hit[415] & reg_we & !reg_error; + + assign loc_alert_en_shadowed_6_wd = reg_wdata[0]; + assign loc_alert_class_shadowed_0_re = addr_hit[416] & reg_re & !reg_error; + assign loc_alert_class_shadowed_0_we = addr_hit[416] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_1_re = addr_hit[417] & reg_re & !reg_error; + assign loc_alert_class_shadowed_1_we = addr_hit[417] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_2_re = addr_hit[418] & reg_re & !reg_error; + assign loc_alert_class_shadowed_2_we = addr_hit[418] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_3_re = addr_hit[419] & reg_re & !reg_error; + assign loc_alert_class_shadowed_3_we = addr_hit[419] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_4_re = addr_hit[420] & reg_re & !reg_error; + assign loc_alert_class_shadowed_4_we = addr_hit[420] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_5_re = addr_hit[421] & reg_re & !reg_error; + assign loc_alert_class_shadowed_5_we = addr_hit[421] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0]; + assign loc_alert_class_shadowed_6_re = addr_hit[422] & reg_re & !reg_error; + assign loc_alert_class_shadowed_6_we = addr_hit[422] & reg_we & !reg_error; + + assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0]; + assign loc_alert_cause_0_we = addr_hit[423] & reg_we & !reg_error; + + assign loc_alert_cause_0_wd = reg_wdata[0]; + assign loc_alert_cause_1_we = addr_hit[424] & reg_we & !reg_error; + + assign loc_alert_cause_1_wd = reg_wdata[0]; + assign loc_alert_cause_2_we = addr_hit[425] & reg_we & !reg_error; + + assign loc_alert_cause_2_wd = reg_wdata[0]; + assign loc_alert_cause_3_we = addr_hit[426] & reg_we & !reg_error; + + assign loc_alert_cause_3_wd = reg_wdata[0]; + assign loc_alert_cause_4_we = addr_hit[427] & reg_we & !reg_error; + + assign loc_alert_cause_4_wd = reg_wdata[0]; + assign loc_alert_cause_5_we = addr_hit[428] & reg_we & !reg_error; + + assign loc_alert_cause_5_wd = reg_wdata[0]; + assign loc_alert_cause_6_we = addr_hit[429] & reg_we & !reg_error; + + assign loc_alert_cause_6_wd = reg_wdata[0]; + assign classa_regwen_we = addr_hit[430] & reg_we & !reg_error; + + assign classa_regwen_wd = reg_wdata[0]; + assign classa_ctrl_shadowed_re = addr_hit[431] & reg_re & !reg_error; + assign classa_ctrl_shadowed_we = addr_hit[431] & reg_we & !reg_error; + + assign classa_ctrl_shadowed_en_wd = reg_wdata[0]; + + assign classa_ctrl_shadowed_lock_wd = reg_wdata[1]; + + assign classa_ctrl_shadowed_en_e0_wd = reg_wdata[2]; + + assign classa_ctrl_shadowed_en_e1_wd = reg_wdata[3]; + + assign classa_ctrl_shadowed_en_e2_wd = reg_wdata[4]; + + assign classa_ctrl_shadowed_en_e3_wd = reg_wdata[5]; + + assign classa_ctrl_shadowed_map_e0_wd = reg_wdata[7:6]; + + assign classa_ctrl_shadowed_map_e1_wd = reg_wdata[9:8]; + + assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; + + assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; + assign classa_clr_regwen_we = addr_hit[432] & reg_we & !reg_error; + + assign classa_clr_regwen_wd = reg_wdata[0]; + assign classa_clr_shadowed_re = addr_hit[433] & reg_re & !reg_error; + assign classa_clr_shadowed_we = addr_hit[433] & reg_we & !reg_error; + + assign classa_clr_shadowed_wd = reg_wdata[0]; + assign classa_accum_cnt_re = addr_hit[434] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_re = addr_hit[435] & reg_re & !reg_error; + assign classa_accum_thresh_shadowed_we = addr_hit[435] & reg_we & !reg_error; + + assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0]; + assign classa_timeout_cyc_shadowed_re = addr_hit[436] & reg_re & !reg_error; + assign classa_timeout_cyc_shadowed_we = addr_hit[436] & reg_we & !reg_error; + + assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_crashdump_trigger_shadowed_re = addr_hit[437] & reg_re & !reg_error; + assign classa_crashdump_trigger_shadowed_we = addr_hit[437] & reg_we & !reg_error; + + assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; + assign classa_phase0_cyc_shadowed_re = addr_hit[438] & reg_re & !reg_error; + assign classa_phase0_cyc_shadowed_we = addr_hit[438] & reg_we & !reg_error; + + assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_phase1_cyc_shadowed_re = addr_hit[439] & reg_re & !reg_error; + assign classa_phase1_cyc_shadowed_we = addr_hit[439] & reg_we & !reg_error; + + assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_phase2_cyc_shadowed_re = addr_hit[440] & reg_re & !reg_error; + assign classa_phase2_cyc_shadowed_we = addr_hit[440] & reg_we & !reg_error; + + assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_phase3_cyc_shadowed_re = addr_hit[441] & reg_re & !reg_error; + assign classa_phase3_cyc_shadowed_we = addr_hit[441] & reg_we & !reg_error; + + assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0]; + assign classa_esc_cnt_re = addr_hit[442] & reg_re & !reg_error; + assign classa_state_re = addr_hit[443] & reg_re & !reg_error; + assign classb_regwen_we = addr_hit[444] & reg_we & !reg_error; + + assign classb_regwen_wd = reg_wdata[0]; + assign classb_ctrl_shadowed_re = addr_hit[445] & reg_re & !reg_error; + assign classb_ctrl_shadowed_we = addr_hit[445] & reg_we & !reg_error; + + assign classb_ctrl_shadowed_en_wd = reg_wdata[0]; + + assign classb_ctrl_shadowed_lock_wd = reg_wdata[1]; + + assign classb_ctrl_shadowed_en_e0_wd = reg_wdata[2]; + + assign classb_ctrl_shadowed_en_e1_wd = reg_wdata[3]; + + assign classb_ctrl_shadowed_en_e2_wd = reg_wdata[4]; + + assign classb_ctrl_shadowed_en_e3_wd = reg_wdata[5]; + + assign classb_ctrl_shadowed_map_e0_wd = reg_wdata[7:6]; + + assign classb_ctrl_shadowed_map_e1_wd = reg_wdata[9:8]; + + assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; + + assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; + assign classb_clr_regwen_we = addr_hit[446] & reg_we & !reg_error; + + assign classb_clr_regwen_wd = reg_wdata[0]; + assign classb_clr_shadowed_re = addr_hit[447] & reg_re & !reg_error; + assign classb_clr_shadowed_we = addr_hit[447] & reg_we & !reg_error; + + assign classb_clr_shadowed_wd = reg_wdata[0]; + assign classb_accum_cnt_re = addr_hit[448] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_re = addr_hit[449] & reg_re & !reg_error; + assign classb_accum_thresh_shadowed_we = addr_hit[449] & reg_we & !reg_error; + + assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0]; + assign classb_timeout_cyc_shadowed_re = addr_hit[450] & reg_re & !reg_error; + assign classb_timeout_cyc_shadowed_we = addr_hit[450] & reg_we & !reg_error; + + assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_crashdump_trigger_shadowed_re = addr_hit[451] & reg_re & !reg_error; + assign classb_crashdump_trigger_shadowed_we = addr_hit[451] & reg_we & !reg_error; + + assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; + assign classb_phase0_cyc_shadowed_re = addr_hit[452] & reg_re & !reg_error; + assign classb_phase0_cyc_shadowed_we = addr_hit[452] & reg_we & !reg_error; + + assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_phase1_cyc_shadowed_re = addr_hit[453] & reg_re & !reg_error; + assign classb_phase1_cyc_shadowed_we = addr_hit[453] & reg_we & !reg_error; + + assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_phase2_cyc_shadowed_re = addr_hit[454] & reg_re & !reg_error; + assign classb_phase2_cyc_shadowed_we = addr_hit[454] & reg_we & !reg_error; + + assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_phase3_cyc_shadowed_re = addr_hit[455] & reg_re & !reg_error; + assign classb_phase3_cyc_shadowed_we = addr_hit[455] & reg_we & !reg_error; + + assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0]; + assign classb_esc_cnt_re = addr_hit[456] & reg_re & !reg_error; + assign classb_state_re = addr_hit[457] & reg_re & !reg_error; + assign classc_regwen_we = addr_hit[458] & reg_we & !reg_error; + + assign classc_regwen_wd = reg_wdata[0]; + assign classc_ctrl_shadowed_re = addr_hit[459] & reg_re & !reg_error; + assign classc_ctrl_shadowed_we = addr_hit[459] & reg_we & !reg_error; + + assign classc_ctrl_shadowed_en_wd = reg_wdata[0]; + + assign classc_ctrl_shadowed_lock_wd = reg_wdata[1]; + + assign classc_ctrl_shadowed_en_e0_wd = reg_wdata[2]; + + assign classc_ctrl_shadowed_en_e1_wd = reg_wdata[3]; + + assign classc_ctrl_shadowed_en_e2_wd = reg_wdata[4]; + + assign classc_ctrl_shadowed_en_e3_wd = reg_wdata[5]; + + assign classc_ctrl_shadowed_map_e0_wd = reg_wdata[7:6]; + + assign classc_ctrl_shadowed_map_e1_wd = reg_wdata[9:8]; + + assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; + + assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; + assign classc_clr_regwen_we = addr_hit[460] & reg_we & !reg_error; + + assign classc_clr_regwen_wd = reg_wdata[0]; + assign classc_clr_shadowed_re = addr_hit[461] & reg_re & !reg_error; + assign classc_clr_shadowed_we = addr_hit[461] & reg_we & !reg_error; + + assign classc_clr_shadowed_wd = reg_wdata[0]; + assign classc_accum_cnt_re = addr_hit[462] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_re = addr_hit[463] & reg_re & !reg_error; + assign classc_accum_thresh_shadowed_we = addr_hit[463] & reg_we & !reg_error; + + assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0]; + assign classc_timeout_cyc_shadowed_re = addr_hit[464] & reg_re & !reg_error; + assign classc_timeout_cyc_shadowed_we = addr_hit[464] & reg_we & !reg_error; + + assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_crashdump_trigger_shadowed_re = addr_hit[465] & reg_re & !reg_error; + assign classc_crashdump_trigger_shadowed_we = addr_hit[465] & reg_we & !reg_error; + + assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; + assign classc_phase0_cyc_shadowed_re = addr_hit[466] & reg_re & !reg_error; + assign classc_phase0_cyc_shadowed_we = addr_hit[466] & reg_we & !reg_error; + + assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_phase1_cyc_shadowed_re = addr_hit[467] & reg_re & !reg_error; + assign classc_phase1_cyc_shadowed_we = addr_hit[467] & reg_we & !reg_error; + + assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_phase2_cyc_shadowed_re = addr_hit[468] & reg_re & !reg_error; + assign classc_phase2_cyc_shadowed_we = addr_hit[468] & reg_we & !reg_error; + + assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_phase3_cyc_shadowed_re = addr_hit[469] & reg_re & !reg_error; + assign classc_phase3_cyc_shadowed_we = addr_hit[469] & reg_we & !reg_error; + + assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0]; + assign classc_esc_cnt_re = addr_hit[470] & reg_re & !reg_error; + assign classc_state_re = addr_hit[471] & reg_re & !reg_error; + assign classd_regwen_we = addr_hit[472] & reg_we & !reg_error; + + assign classd_regwen_wd = reg_wdata[0]; + assign classd_ctrl_shadowed_re = addr_hit[473] & reg_re & !reg_error; + assign classd_ctrl_shadowed_we = addr_hit[473] & reg_we & !reg_error; + + assign classd_ctrl_shadowed_en_wd = reg_wdata[0]; + + assign classd_ctrl_shadowed_lock_wd = reg_wdata[1]; + + assign classd_ctrl_shadowed_en_e0_wd = reg_wdata[2]; + + assign classd_ctrl_shadowed_en_e1_wd = reg_wdata[3]; + + assign classd_ctrl_shadowed_en_e2_wd = reg_wdata[4]; + + assign classd_ctrl_shadowed_en_e3_wd = reg_wdata[5]; + + assign classd_ctrl_shadowed_map_e0_wd = reg_wdata[7:6]; + + assign classd_ctrl_shadowed_map_e1_wd = reg_wdata[9:8]; + + assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10]; + + assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12]; + assign classd_clr_regwen_we = addr_hit[474] & reg_we & !reg_error; + + assign classd_clr_regwen_wd = reg_wdata[0]; + assign classd_clr_shadowed_re = addr_hit[475] & reg_re & !reg_error; + assign classd_clr_shadowed_we = addr_hit[475] & reg_we & !reg_error; + + assign classd_clr_shadowed_wd = reg_wdata[0]; + assign classd_accum_cnt_re = addr_hit[476] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_re = addr_hit[477] & reg_re & !reg_error; + assign classd_accum_thresh_shadowed_we = addr_hit[477] & reg_we & !reg_error; + + assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0]; + assign classd_timeout_cyc_shadowed_re = addr_hit[478] & reg_re & !reg_error; + assign classd_timeout_cyc_shadowed_we = addr_hit[478] & reg_we & !reg_error; + + assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_crashdump_trigger_shadowed_re = addr_hit[479] & reg_re & !reg_error; + assign classd_crashdump_trigger_shadowed_we = addr_hit[479] & reg_we & !reg_error; + + assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0]; + assign classd_phase0_cyc_shadowed_re = addr_hit[480] & reg_re & !reg_error; + assign classd_phase0_cyc_shadowed_we = addr_hit[480] & reg_we & !reg_error; + + assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_phase1_cyc_shadowed_re = addr_hit[481] & reg_re & !reg_error; + assign classd_phase1_cyc_shadowed_we = addr_hit[481] & reg_we & !reg_error; + + assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_phase2_cyc_shadowed_re = addr_hit[482] & reg_re & !reg_error; + assign classd_phase2_cyc_shadowed_we = addr_hit[482] & reg_we & !reg_error; + + assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_phase3_cyc_shadowed_re = addr_hit[483] & reg_re & !reg_error; + assign classd_phase3_cyc_shadowed_we = addr_hit[483] & reg_we & !reg_error; + + assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0]; + assign classd_esc_cnt_re = addr_hit[484] & reg_re & !reg_error; + assign classd_state_re = addr_hit[485] & reg_re & !reg_error; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = ping_timer_regwen_we; + reg_we_check[4] = ping_timeout_cyc_shadowed_gated_we; + reg_we_check[5] = ping_timer_en_shadowed_gated_we; + reg_we_check[6] = alert_regwen_0_we; + reg_we_check[7] = alert_regwen_1_we; + reg_we_check[8] = alert_regwen_2_we; + reg_we_check[9] = alert_regwen_3_we; + reg_we_check[10] = alert_regwen_4_we; + reg_we_check[11] = alert_regwen_5_we; + reg_we_check[12] = alert_regwen_6_we; + reg_we_check[13] = alert_regwen_7_we; + reg_we_check[14] = alert_regwen_8_we; + reg_we_check[15] = alert_regwen_9_we; + reg_we_check[16] = alert_regwen_10_we; + reg_we_check[17] = alert_regwen_11_we; + reg_we_check[18] = alert_regwen_12_we; + reg_we_check[19] = alert_regwen_13_we; + reg_we_check[20] = alert_regwen_14_we; + reg_we_check[21] = alert_regwen_15_we; + reg_we_check[22] = alert_regwen_16_we; + reg_we_check[23] = alert_regwen_17_we; + reg_we_check[24] = alert_regwen_18_we; + reg_we_check[25] = alert_regwen_19_we; + reg_we_check[26] = alert_regwen_20_we; + reg_we_check[27] = alert_regwen_21_we; + reg_we_check[28] = alert_regwen_22_we; + reg_we_check[29] = alert_regwen_23_we; + reg_we_check[30] = alert_regwen_24_we; + reg_we_check[31] = alert_regwen_25_we; + reg_we_check[32] = alert_regwen_26_we; + reg_we_check[33] = alert_regwen_27_we; + reg_we_check[34] = alert_regwen_28_we; + reg_we_check[35] = alert_regwen_29_we; + reg_we_check[36] = alert_regwen_30_we; + reg_we_check[37] = alert_regwen_31_we; + reg_we_check[38] = alert_regwen_32_we; + reg_we_check[39] = alert_regwen_33_we; + reg_we_check[40] = alert_regwen_34_we; + reg_we_check[41] = alert_regwen_35_we; + reg_we_check[42] = alert_regwen_36_we; + reg_we_check[43] = alert_regwen_37_we; + reg_we_check[44] = alert_regwen_38_we; + reg_we_check[45] = alert_regwen_39_we; + reg_we_check[46] = alert_regwen_40_we; + reg_we_check[47] = alert_regwen_41_we; + reg_we_check[48] = alert_regwen_42_we; + reg_we_check[49] = alert_regwen_43_we; + reg_we_check[50] = alert_regwen_44_we; + reg_we_check[51] = alert_regwen_45_we; + reg_we_check[52] = alert_regwen_46_we; + reg_we_check[53] = alert_regwen_47_we; + reg_we_check[54] = alert_regwen_48_we; + reg_we_check[55] = alert_regwen_49_we; + reg_we_check[56] = alert_regwen_50_we; + reg_we_check[57] = alert_regwen_51_we; + reg_we_check[58] = alert_regwen_52_we; + reg_we_check[59] = alert_regwen_53_we; + reg_we_check[60] = alert_regwen_54_we; + reg_we_check[61] = alert_regwen_55_we; + reg_we_check[62] = alert_regwen_56_we; + reg_we_check[63] = alert_regwen_57_we; + reg_we_check[64] = alert_regwen_58_we; + reg_we_check[65] = alert_regwen_59_we; + reg_we_check[66] = alert_regwen_60_we; + reg_we_check[67] = alert_regwen_61_we; + reg_we_check[68] = alert_regwen_62_we; + reg_we_check[69] = alert_regwen_63_we; + reg_we_check[70] = alert_regwen_64_we; + reg_we_check[71] = alert_regwen_65_we; + reg_we_check[72] = alert_regwen_66_we; + reg_we_check[73] = alert_regwen_67_we; + reg_we_check[74] = alert_regwen_68_we; + reg_we_check[75] = alert_regwen_69_we; + reg_we_check[76] = alert_regwen_70_we; + reg_we_check[77] = alert_regwen_71_we; + reg_we_check[78] = alert_regwen_72_we; + reg_we_check[79] = alert_regwen_73_we; + reg_we_check[80] = alert_regwen_74_we; + reg_we_check[81] = alert_regwen_75_we; + reg_we_check[82] = alert_regwen_76_we; + reg_we_check[83] = alert_regwen_77_we; + reg_we_check[84] = alert_regwen_78_we; + reg_we_check[85] = alert_regwen_79_we; + reg_we_check[86] = alert_regwen_80_we; + reg_we_check[87] = alert_regwen_81_we; + reg_we_check[88] = alert_regwen_82_we; + reg_we_check[89] = alert_regwen_83_we; + reg_we_check[90] = alert_regwen_84_we; + reg_we_check[91] = alert_regwen_85_we; + reg_we_check[92] = alert_regwen_86_we; + reg_we_check[93] = alert_regwen_87_we; + reg_we_check[94] = alert_regwen_88_we; + reg_we_check[95] = alert_regwen_89_we; + reg_we_check[96] = alert_regwen_90_we; + reg_we_check[97] = alert_regwen_91_we; + reg_we_check[98] = alert_regwen_92_we; + reg_we_check[99] = alert_regwen_93_we; + reg_we_check[100] = alert_regwen_94_we; + reg_we_check[101] = alert_regwen_95_we; + reg_we_check[102] = alert_regwen_96_we; + reg_we_check[103] = alert_regwen_97_we; + reg_we_check[104] = alert_regwen_98_we; + reg_we_check[105] = alert_en_shadowed_0_gated_we; + reg_we_check[106] = alert_en_shadowed_1_gated_we; + reg_we_check[107] = alert_en_shadowed_2_gated_we; + reg_we_check[108] = alert_en_shadowed_3_gated_we; + reg_we_check[109] = alert_en_shadowed_4_gated_we; + reg_we_check[110] = alert_en_shadowed_5_gated_we; + reg_we_check[111] = alert_en_shadowed_6_gated_we; + reg_we_check[112] = alert_en_shadowed_7_gated_we; + reg_we_check[113] = alert_en_shadowed_8_gated_we; + reg_we_check[114] = alert_en_shadowed_9_gated_we; + reg_we_check[115] = alert_en_shadowed_10_gated_we; + reg_we_check[116] = alert_en_shadowed_11_gated_we; + reg_we_check[117] = alert_en_shadowed_12_gated_we; + reg_we_check[118] = alert_en_shadowed_13_gated_we; + reg_we_check[119] = alert_en_shadowed_14_gated_we; + reg_we_check[120] = alert_en_shadowed_15_gated_we; + reg_we_check[121] = alert_en_shadowed_16_gated_we; + reg_we_check[122] = alert_en_shadowed_17_gated_we; + reg_we_check[123] = alert_en_shadowed_18_gated_we; + reg_we_check[124] = alert_en_shadowed_19_gated_we; + reg_we_check[125] = alert_en_shadowed_20_gated_we; + reg_we_check[126] = alert_en_shadowed_21_gated_we; + reg_we_check[127] = alert_en_shadowed_22_gated_we; + reg_we_check[128] = alert_en_shadowed_23_gated_we; + reg_we_check[129] = alert_en_shadowed_24_gated_we; + reg_we_check[130] = alert_en_shadowed_25_gated_we; + reg_we_check[131] = alert_en_shadowed_26_gated_we; + reg_we_check[132] = alert_en_shadowed_27_gated_we; + reg_we_check[133] = alert_en_shadowed_28_gated_we; + reg_we_check[134] = alert_en_shadowed_29_gated_we; + reg_we_check[135] = alert_en_shadowed_30_gated_we; + reg_we_check[136] = alert_en_shadowed_31_gated_we; + reg_we_check[137] = alert_en_shadowed_32_gated_we; + reg_we_check[138] = alert_en_shadowed_33_gated_we; + reg_we_check[139] = alert_en_shadowed_34_gated_we; + reg_we_check[140] = alert_en_shadowed_35_gated_we; + reg_we_check[141] = alert_en_shadowed_36_gated_we; + reg_we_check[142] = alert_en_shadowed_37_gated_we; + reg_we_check[143] = alert_en_shadowed_38_gated_we; + reg_we_check[144] = alert_en_shadowed_39_gated_we; + reg_we_check[145] = alert_en_shadowed_40_gated_we; + reg_we_check[146] = alert_en_shadowed_41_gated_we; + reg_we_check[147] = alert_en_shadowed_42_gated_we; + reg_we_check[148] = alert_en_shadowed_43_gated_we; + reg_we_check[149] = alert_en_shadowed_44_gated_we; + reg_we_check[150] = alert_en_shadowed_45_gated_we; + reg_we_check[151] = alert_en_shadowed_46_gated_we; + reg_we_check[152] = alert_en_shadowed_47_gated_we; + reg_we_check[153] = alert_en_shadowed_48_gated_we; + reg_we_check[154] = alert_en_shadowed_49_gated_we; + reg_we_check[155] = alert_en_shadowed_50_gated_we; + reg_we_check[156] = alert_en_shadowed_51_gated_we; + reg_we_check[157] = alert_en_shadowed_52_gated_we; + reg_we_check[158] = alert_en_shadowed_53_gated_we; + reg_we_check[159] = alert_en_shadowed_54_gated_we; + reg_we_check[160] = alert_en_shadowed_55_gated_we; + reg_we_check[161] = alert_en_shadowed_56_gated_we; + reg_we_check[162] = alert_en_shadowed_57_gated_we; + reg_we_check[163] = alert_en_shadowed_58_gated_we; + reg_we_check[164] = alert_en_shadowed_59_gated_we; + reg_we_check[165] = alert_en_shadowed_60_gated_we; + reg_we_check[166] = alert_en_shadowed_61_gated_we; + reg_we_check[167] = alert_en_shadowed_62_gated_we; + reg_we_check[168] = alert_en_shadowed_63_gated_we; + reg_we_check[169] = alert_en_shadowed_64_gated_we; + reg_we_check[170] = alert_en_shadowed_65_gated_we; + reg_we_check[171] = alert_en_shadowed_66_gated_we; + reg_we_check[172] = alert_en_shadowed_67_gated_we; + reg_we_check[173] = alert_en_shadowed_68_gated_we; + reg_we_check[174] = alert_en_shadowed_69_gated_we; + reg_we_check[175] = alert_en_shadowed_70_gated_we; + reg_we_check[176] = alert_en_shadowed_71_gated_we; + reg_we_check[177] = alert_en_shadowed_72_gated_we; + reg_we_check[178] = alert_en_shadowed_73_gated_we; + reg_we_check[179] = alert_en_shadowed_74_gated_we; + reg_we_check[180] = alert_en_shadowed_75_gated_we; + reg_we_check[181] = alert_en_shadowed_76_gated_we; + reg_we_check[182] = alert_en_shadowed_77_gated_we; + reg_we_check[183] = alert_en_shadowed_78_gated_we; + reg_we_check[184] = alert_en_shadowed_79_gated_we; + reg_we_check[185] = alert_en_shadowed_80_gated_we; + reg_we_check[186] = alert_en_shadowed_81_gated_we; + reg_we_check[187] = alert_en_shadowed_82_gated_we; + reg_we_check[188] = alert_en_shadowed_83_gated_we; + reg_we_check[189] = alert_en_shadowed_84_gated_we; + reg_we_check[190] = alert_en_shadowed_85_gated_we; + reg_we_check[191] = alert_en_shadowed_86_gated_we; + reg_we_check[192] = alert_en_shadowed_87_gated_we; + reg_we_check[193] = alert_en_shadowed_88_gated_we; + reg_we_check[194] = alert_en_shadowed_89_gated_we; + reg_we_check[195] = alert_en_shadowed_90_gated_we; + reg_we_check[196] = alert_en_shadowed_91_gated_we; + reg_we_check[197] = alert_en_shadowed_92_gated_we; + reg_we_check[198] = alert_en_shadowed_93_gated_we; + reg_we_check[199] = alert_en_shadowed_94_gated_we; + reg_we_check[200] = alert_en_shadowed_95_gated_we; + reg_we_check[201] = alert_en_shadowed_96_gated_we; + reg_we_check[202] = alert_en_shadowed_97_gated_we; + reg_we_check[203] = alert_en_shadowed_98_gated_we; + reg_we_check[204] = alert_class_shadowed_0_gated_we; + reg_we_check[205] = alert_class_shadowed_1_gated_we; + reg_we_check[206] = alert_class_shadowed_2_gated_we; + reg_we_check[207] = alert_class_shadowed_3_gated_we; + reg_we_check[208] = alert_class_shadowed_4_gated_we; + reg_we_check[209] = alert_class_shadowed_5_gated_we; + reg_we_check[210] = alert_class_shadowed_6_gated_we; + reg_we_check[211] = alert_class_shadowed_7_gated_we; + reg_we_check[212] = alert_class_shadowed_8_gated_we; + reg_we_check[213] = alert_class_shadowed_9_gated_we; + reg_we_check[214] = alert_class_shadowed_10_gated_we; + reg_we_check[215] = alert_class_shadowed_11_gated_we; + reg_we_check[216] = alert_class_shadowed_12_gated_we; + reg_we_check[217] = alert_class_shadowed_13_gated_we; + reg_we_check[218] = alert_class_shadowed_14_gated_we; + reg_we_check[219] = alert_class_shadowed_15_gated_we; + reg_we_check[220] = alert_class_shadowed_16_gated_we; + reg_we_check[221] = alert_class_shadowed_17_gated_we; + reg_we_check[222] = alert_class_shadowed_18_gated_we; + reg_we_check[223] = alert_class_shadowed_19_gated_we; + reg_we_check[224] = alert_class_shadowed_20_gated_we; + reg_we_check[225] = alert_class_shadowed_21_gated_we; + reg_we_check[226] = alert_class_shadowed_22_gated_we; + reg_we_check[227] = alert_class_shadowed_23_gated_we; + reg_we_check[228] = alert_class_shadowed_24_gated_we; + reg_we_check[229] = alert_class_shadowed_25_gated_we; + reg_we_check[230] = alert_class_shadowed_26_gated_we; + reg_we_check[231] = alert_class_shadowed_27_gated_we; + reg_we_check[232] = alert_class_shadowed_28_gated_we; + reg_we_check[233] = alert_class_shadowed_29_gated_we; + reg_we_check[234] = alert_class_shadowed_30_gated_we; + reg_we_check[235] = alert_class_shadowed_31_gated_we; + reg_we_check[236] = alert_class_shadowed_32_gated_we; + reg_we_check[237] = alert_class_shadowed_33_gated_we; + reg_we_check[238] = alert_class_shadowed_34_gated_we; + reg_we_check[239] = alert_class_shadowed_35_gated_we; + reg_we_check[240] = alert_class_shadowed_36_gated_we; + reg_we_check[241] = alert_class_shadowed_37_gated_we; + reg_we_check[242] = alert_class_shadowed_38_gated_we; + reg_we_check[243] = alert_class_shadowed_39_gated_we; + reg_we_check[244] = alert_class_shadowed_40_gated_we; + reg_we_check[245] = alert_class_shadowed_41_gated_we; + reg_we_check[246] = alert_class_shadowed_42_gated_we; + reg_we_check[247] = alert_class_shadowed_43_gated_we; + reg_we_check[248] = alert_class_shadowed_44_gated_we; + reg_we_check[249] = alert_class_shadowed_45_gated_we; + reg_we_check[250] = alert_class_shadowed_46_gated_we; + reg_we_check[251] = alert_class_shadowed_47_gated_we; + reg_we_check[252] = alert_class_shadowed_48_gated_we; + reg_we_check[253] = alert_class_shadowed_49_gated_we; + reg_we_check[254] = alert_class_shadowed_50_gated_we; + reg_we_check[255] = alert_class_shadowed_51_gated_we; + reg_we_check[256] = alert_class_shadowed_52_gated_we; + reg_we_check[257] = alert_class_shadowed_53_gated_we; + reg_we_check[258] = alert_class_shadowed_54_gated_we; + reg_we_check[259] = alert_class_shadowed_55_gated_we; + reg_we_check[260] = alert_class_shadowed_56_gated_we; + reg_we_check[261] = alert_class_shadowed_57_gated_we; + reg_we_check[262] = alert_class_shadowed_58_gated_we; + reg_we_check[263] = alert_class_shadowed_59_gated_we; + reg_we_check[264] = alert_class_shadowed_60_gated_we; + reg_we_check[265] = alert_class_shadowed_61_gated_we; + reg_we_check[266] = alert_class_shadowed_62_gated_we; + reg_we_check[267] = alert_class_shadowed_63_gated_we; + reg_we_check[268] = alert_class_shadowed_64_gated_we; + reg_we_check[269] = alert_class_shadowed_65_gated_we; + reg_we_check[270] = alert_class_shadowed_66_gated_we; + reg_we_check[271] = alert_class_shadowed_67_gated_we; + reg_we_check[272] = alert_class_shadowed_68_gated_we; + reg_we_check[273] = alert_class_shadowed_69_gated_we; + reg_we_check[274] = alert_class_shadowed_70_gated_we; + reg_we_check[275] = alert_class_shadowed_71_gated_we; + reg_we_check[276] = alert_class_shadowed_72_gated_we; + reg_we_check[277] = alert_class_shadowed_73_gated_we; + reg_we_check[278] = alert_class_shadowed_74_gated_we; + reg_we_check[279] = alert_class_shadowed_75_gated_we; + reg_we_check[280] = alert_class_shadowed_76_gated_we; + reg_we_check[281] = alert_class_shadowed_77_gated_we; + reg_we_check[282] = alert_class_shadowed_78_gated_we; + reg_we_check[283] = alert_class_shadowed_79_gated_we; + reg_we_check[284] = alert_class_shadowed_80_gated_we; + reg_we_check[285] = alert_class_shadowed_81_gated_we; + reg_we_check[286] = alert_class_shadowed_82_gated_we; + reg_we_check[287] = alert_class_shadowed_83_gated_we; + reg_we_check[288] = alert_class_shadowed_84_gated_we; + reg_we_check[289] = alert_class_shadowed_85_gated_we; + reg_we_check[290] = alert_class_shadowed_86_gated_we; + reg_we_check[291] = alert_class_shadowed_87_gated_we; + reg_we_check[292] = alert_class_shadowed_88_gated_we; + reg_we_check[293] = alert_class_shadowed_89_gated_we; + reg_we_check[294] = alert_class_shadowed_90_gated_we; + reg_we_check[295] = alert_class_shadowed_91_gated_we; + reg_we_check[296] = alert_class_shadowed_92_gated_we; + reg_we_check[297] = alert_class_shadowed_93_gated_we; + reg_we_check[298] = alert_class_shadowed_94_gated_we; + reg_we_check[299] = alert_class_shadowed_95_gated_we; + reg_we_check[300] = alert_class_shadowed_96_gated_we; + reg_we_check[301] = alert_class_shadowed_97_gated_we; + reg_we_check[302] = alert_class_shadowed_98_gated_we; + reg_we_check[303] = alert_cause_0_we; + reg_we_check[304] = alert_cause_1_we; + reg_we_check[305] = alert_cause_2_we; + reg_we_check[306] = alert_cause_3_we; + reg_we_check[307] = alert_cause_4_we; + reg_we_check[308] = alert_cause_5_we; + reg_we_check[309] = alert_cause_6_we; + reg_we_check[310] = alert_cause_7_we; + reg_we_check[311] = alert_cause_8_we; + reg_we_check[312] = alert_cause_9_we; + reg_we_check[313] = alert_cause_10_we; + reg_we_check[314] = alert_cause_11_we; + reg_we_check[315] = alert_cause_12_we; + reg_we_check[316] = alert_cause_13_we; + reg_we_check[317] = alert_cause_14_we; + reg_we_check[318] = alert_cause_15_we; + reg_we_check[319] = alert_cause_16_we; + reg_we_check[320] = alert_cause_17_we; + reg_we_check[321] = alert_cause_18_we; + reg_we_check[322] = alert_cause_19_we; + reg_we_check[323] = alert_cause_20_we; + reg_we_check[324] = alert_cause_21_we; + reg_we_check[325] = alert_cause_22_we; + reg_we_check[326] = alert_cause_23_we; + reg_we_check[327] = alert_cause_24_we; + reg_we_check[328] = alert_cause_25_we; + reg_we_check[329] = alert_cause_26_we; + reg_we_check[330] = alert_cause_27_we; + reg_we_check[331] = alert_cause_28_we; + reg_we_check[332] = alert_cause_29_we; + reg_we_check[333] = alert_cause_30_we; + reg_we_check[334] = alert_cause_31_we; + reg_we_check[335] = alert_cause_32_we; + reg_we_check[336] = alert_cause_33_we; + reg_we_check[337] = alert_cause_34_we; + reg_we_check[338] = alert_cause_35_we; + reg_we_check[339] = alert_cause_36_we; + reg_we_check[340] = alert_cause_37_we; + reg_we_check[341] = alert_cause_38_we; + reg_we_check[342] = alert_cause_39_we; + reg_we_check[343] = alert_cause_40_we; + reg_we_check[344] = alert_cause_41_we; + reg_we_check[345] = alert_cause_42_we; + reg_we_check[346] = alert_cause_43_we; + reg_we_check[347] = alert_cause_44_we; + reg_we_check[348] = alert_cause_45_we; + reg_we_check[349] = alert_cause_46_we; + reg_we_check[350] = alert_cause_47_we; + reg_we_check[351] = alert_cause_48_we; + reg_we_check[352] = alert_cause_49_we; + reg_we_check[353] = alert_cause_50_we; + reg_we_check[354] = alert_cause_51_we; + reg_we_check[355] = alert_cause_52_we; + reg_we_check[356] = alert_cause_53_we; + reg_we_check[357] = alert_cause_54_we; + reg_we_check[358] = alert_cause_55_we; + reg_we_check[359] = alert_cause_56_we; + reg_we_check[360] = alert_cause_57_we; + reg_we_check[361] = alert_cause_58_we; + reg_we_check[362] = alert_cause_59_we; + reg_we_check[363] = alert_cause_60_we; + reg_we_check[364] = alert_cause_61_we; + reg_we_check[365] = alert_cause_62_we; + reg_we_check[366] = alert_cause_63_we; + reg_we_check[367] = alert_cause_64_we; + reg_we_check[368] = alert_cause_65_we; + reg_we_check[369] = alert_cause_66_we; + reg_we_check[370] = alert_cause_67_we; + reg_we_check[371] = alert_cause_68_we; + reg_we_check[372] = alert_cause_69_we; + reg_we_check[373] = alert_cause_70_we; + reg_we_check[374] = alert_cause_71_we; + reg_we_check[375] = alert_cause_72_we; + reg_we_check[376] = alert_cause_73_we; + reg_we_check[377] = alert_cause_74_we; + reg_we_check[378] = alert_cause_75_we; + reg_we_check[379] = alert_cause_76_we; + reg_we_check[380] = alert_cause_77_we; + reg_we_check[381] = alert_cause_78_we; + reg_we_check[382] = alert_cause_79_we; + reg_we_check[383] = alert_cause_80_we; + reg_we_check[384] = alert_cause_81_we; + reg_we_check[385] = alert_cause_82_we; + reg_we_check[386] = alert_cause_83_we; + reg_we_check[387] = alert_cause_84_we; + reg_we_check[388] = alert_cause_85_we; + reg_we_check[389] = alert_cause_86_we; + reg_we_check[390] = alert_cause_87_we; + reg_we_check[391] = alert_cause_88_we; + reg_we_check[392] = alert_cause_89_we; + reg_we_check[393] = alert_cause_90_we; + reg_we_check[394] = alert_cause_91_we; + reg_we_check[395] = alert_cause_92_we; + reg_we_check[396] = alert_cause_93_we; + reg_we_check[397] = alert_cause_94_we; + reg_we_check[398] = alert_cause_95_we; + reg_we_check[399] = alert_cause_96_we; + reg_we_check[400] = alert_cause_97_we; + reg_we_check[401] = alert_cause_98_we; + reg_we_check[402] = loc_alert_regwen_0_we; + reg_we_check[403] = loc_alert_regwen_1_we; + reg_we_check[404] = loc_alert_regwen_2_we; + reg_we_check[405] = loc_alert_regwen_3_we; + reg_we_check[406] = loc_alert_regwen_4_we; + reg_we_check[407] = loc_alert_regwen_5_we; + reg_we_check[408] = loc_alert_regwen_6_we; + reg_we_check[409] = loc_alert_en_shadowed_0_gated_we; + reg_we_check[410] = loc_alert_en_shadowed_1_gated_we; + reg_we_check[411] = loc_alert_en_shadowed_2_gated_we; + reg_we_check[412] = loc_alert_en_shadowed_3_gated_we; + reg_we_check[413] = loc_alert_en_shadowed_4_gated_we; + reg_we_check[414] = loc_alert_en_shadowed_5_gated_we; + reg_we_check[415] = loc_alert_en_shadowed_6_gated_we; + reg_we_check[416] = loc_alert_class_shadowed_0_gated_we; + reg_we_check[417] = loc_alert_class_shadowed_1_gated_we; + reg_we_check[418] = loc_alert_class_shadowed_2_gated_we; + reg_we_check[419] = loc_alert_class_shadowed_3_gated_we; + reg_we_check[420] = loc_alert_class_shadowed_4_gated_we; + reg_we_check[421] = loc_alert_class_shadowed_5_gated_we; + reg_we_check[422] = loc_alert_class_shadowed_6_gated_we; + reg_we_check[423] = loc_alert_cause_0_we; + reg_we_check[424] = loc_alert_cause_1_we; + reg_we_check[425] = loc_alert_cause_2_we; + reg_we_check[426] = loc_alert_cause_3_we; + reg_we_check[427] = loc_alert_cause_4_we; + reg_we_check[428] = loc_alert_cause_5_we; + reg_we_check[429] = loc_alert_cause_6_we; + reg_we_check[430] = classa_regwen_we; + reg_we_check[431] = classa_ctrl_shadowed_gated_we; + reg_we_check[432] = classa_clr_regwen_we; + reg_we_check[433] = classa_clr_shadowed_gated_we; + reg_we_check[434] = 1'b0; + reg_we_check[435] = classa_accum_thresh_shadowed_gated_we; + reg_we_check[436] = classa_timeout_cyc_shadowed_gated_we; + reg_we_check[437] = classa_crashdump_trigger_shadowed_gated_we; + reg_we_check[438] = classa_phase0_cyc_shadowed_gated_we; + reg_we_check[439] = classa_phase1_cyc_shadowed_gated_we; + reg_we_check[440] = classa_phase2_cyc_shadowed_gated_we; + reg_we_check[441] = classa_phase3_cyc_shadowed_gated_we; + reg_we_check[442] = 1'b0; + reg_we_check[443] = 1'b0; + reg_we_check[444] = classb_regwen_we; + reg_we_check[445] = classb_ctrl_shadowed_gated_we; + reg_we_check[446] = classb_clr_regwen_we; + reg_we_check[447] = classb_clr_shadowed_gated_we; + reg_we_check[448] = 1'b0; + reg_we_check[449] = classb_accum_thresh_shadowed_gated_we; + reg_we_check[450] = classb_timeout_cyc_shadowed_gated_we; + reg_we_check[451] = classb_crashdump_trigger_shadowed_gated_we; + reg_we_check[452] = classb_phase0_cyc_shadowed_gated_we; + reg_we_check[453] = classb_phase1_cyc_shadowed_gated_we; + reg_we_check[454] = classb_phase2_cyc_shadowed_gated_we; + reg_we_check[455] = classb_phase3_cyc_shadowed_gated_we; + reg_we_check[456] = 1'b0; + reg_we_check[457] = 1'b0; + reg_we_check[458] = classc_regwen_we; + reg_we_check[459] = classc_ctrl_shadowed_gated_we; + reg_we_check[460] = classc_clr_regwen_we; + reg_we_check[461] = classc_clr_shadowed_gated_we; + reg_we_check[462] = 1'b0; + reg_we_check[463] = classc_accum_thresh_shadowed_gated_we; + reg_we_check[464] = classc_timeout_cyc_shadowed_gated_we; + reg_we_check[465] = classc_crashdump_trigger_shadowed_gated_we; + reg_we_check[466] = classc_phase0_cyc_shadowed_gated_we; + reg_we_check[467] = classc_phase1_cyc_shadowed_gated_we; + reg_we_check[468] = classc_phase2_cyc_shadowed_gated_we; + reg_we_check[469] = classc_phase3_cyc_shadowed_gated_we; + reg_we_check[470] = 1'b0; + reg_we_check[471] = 1'b0; + reg_we_check[472] = classd_regwen_we; + reg_we_check[473] = classd_ctrl_shadowed_gated_we; + reg_we_check[474] = classd_clr_regwen_we; + reg_we_check[475] = classd_clr_shadowed_gated_we; + reg_we_check[476] = 1'b0; + reg_we_check[477] = classd_accum_thresh_shadowed_gated_we; + reg_we_check[478] = classd_timeout_cyc_shadowed_gated_we; + reg_we_check[479] = classd_crashdump_trigger_shadowed_gated_we; + reg_we_check[480] = classd_phase0_cyc_shadowed_gated_we; + reg_we_check[481] = classd_phase1_cyc_shadowed_gated_we; + reg_we_check[482] = classd_phase2_cyc_shadowed_gated_we; + reg_we_check[483] = classd_phase3_cyc_shadowed_gated_we; + reg_we_check[484] = 1'b0; + reg_we_check[485] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = intr_state_classa_qs; + reg_rdata_next[1] = intr_state_classb_qs; + reg_rdata_next[2] = intr_state_classc_qs; + reg_rdata_next[3] = intr_state_classd_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_classa_qs; + reg_rdata_next[1] = intr_enable_classb_qs; + reg_rdata_next[2] = intr_enable_classc_qs; + reg_rdata_next[3] = intr_enable_classd_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = ping_timer_regwen_qs; + end + + addr_hit[4]: begin + reg_rdata_next[15:0] = ping_timeout_cyc_shadowed_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = ping_timer_en_shadowed_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = alert_regwen_0_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = alert_regwen_1_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = alert_regwen_2_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = alert_regwen_3_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = alert_regwen_4_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = alert_regwen_5_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = alert_regwen_6_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = alert_regwen_7_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = alert_regwen_8_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = alert_regwen_9_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = alert_regwen_10_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = alert_regwen_11_qs; + end + + addr_hit[18]: begin + reg_rdata_next[0] = alert_regwen_12_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = alert_regwen_13_qs; + end + + addr_hit[20]: begin + reg_rdata_next[0] = alert_regwen_14_qs; + end + + addr_hit[21]: begin + reg_rdata_next[0] = alert_regwen_15_qs; + end + + addr_hit[22]: begin + reg_rdata_next[0] = alert_regwen_16_qs; + end + + addr_hit[23]: begin + reg_rdata_next[0] = alert_regwen_17_qs; + end + + addr_hit[24]: begin + reg_rdata_next[0] = alert_regwen_18_qs; + end + + addr_hit[25]: begin + reg_rdata_next[0] = alert_regwen_19_qs; + end + + addr_hit[26]: begin + reg_rdata_next[0] = alert_regwen_20_qs; + end + + addr_hit[27]: begin + reg_rdata_next[0] = alert_regwen_21_qs; + end + + addr_hit[28]: begin + reg_rdata_next[0] = alert_regwen_22_qs; + end + + addr_hit[29]: begin + reg_rdata_next[0] = alert_regwen_23_qs; + end + + addr_hit[30]: begin + reg_rdata_next[0] = alert_regwen_24_qs; + end + + addr_hit[31]: begin + reg_rdata_next[0] = alert_regwen_25_qs; + end + + addr_hit[32]: begin + reg_rdata_next[0] = alert_regwen_26_qs; + end + + addr_hit[33]: begin + reg_rdata_next[0] = alert_regwen_27_qs; + end + + addr_hit[34]: begin + reg_rdata_next[0] = alert_regwen_28_qs; + end + + addr_hit[35]: begin + reg_rdata_next[0] = alert_regwen_29_qs; + end + + addr_hit[36]: begin + reg_rdata_next[0] = alert_regwen_30_qs; + end + + addr_hit[37]: begin + reg_rdata_next[0] = alert_regwen_31_qs; + end + + addr_hit[38]: begin + reg_rdata_next[0] = alert_regwen_32_qs; + end + + addr_hit[39]: begin + reg_rdata_next[0] = alert_regwen_33_qs; + end + + addr_hit[40]: begin + reg_rdata_next[0] = alert_regwen_34_qs; + end + + addr_hit[41]: begin + reg_rdata_next[0] = alert_regwen_35_qs; + end + + addr_hit[42]: begin + reg_rdata_next[0] = alert_regwen_36_qs; + end + + addr_hit[43]: begin + reg_rdata_next[0] = alert_regwen_37_qs; + end + + addr_hit[44]: begin + reg_rdata_next[0] = alert_regwen_38_qs; + end + + addr_hit[45]: begin + reg_rdata_next[0] = alert_regwen_39_qs; + end + + addr_hit[46]: begin + reg_rdata_next[0] = alert_regwen_40_qs; + end + + addr_hit[47]: begin + reg_rdata_next[0] = alert_regwen_41_qs; + end + + addr_hit[48]: begin + reg_rdata_next[0] = alert_regwen_42_qs; + end + + addr_hit[49]: begin + reg_rdata_next[0] = alert_regwen_43_qs; + end + + addr_hit[50]: begin + reg_rdata_next[0] = alert_regwen_44_qs; + end + + addr_hit[51]: begin + reg_rdata_next[0] = alert_regwen_45_qs; + end + + addr_hit[52]: begin + reg_rdata_next[0] = alert_regwen_46_qs; + end + + addr_hit[53]: begin + reg_rdata_next[0] = alert_regwen_47_qs; + end + + addr_hit[54]: begin + reg_rdata_next[0] = alert_regwen_48_qs; + end + + addr_hit[55]: begin + reg_rdata_next[0] = alert_regwen_49_qs; + end + + addr_hit[56]: begin + reg_rdata_next[0] = alert_regwen_50_qs; + end + + addr_hit[57]: begin + reg_rdata_next[0] = alert_regwen_51_qs; + end + + addr_hit[58]: begin + reg_rdata_next[0] = alert_regwen_52_qs; + end + + addr_hit[59]: begin + reg_rdata_next[0] = alert_regwen_53_qs; + end + + addr_hit[60]: begin + reg_rdata_next[0] = alert_regwen_54_qs; + end + + addr_hit[61]: begin + reg_rdata_next[0] = alert_regwen_55_qs; + end + + addr_hit[62]: begin + reg_rdata_next[0] = alert_regwen_56_qs; + end + + addr_hit[63]: begin + reg_rdata_next[0] = alert_regwen_57_qs; + end + + addr_hit[64]: begin + reg_rdata_next[0] = alert_regwen_58_qs; + end + + addr_hit[65]: begin + reg_rdata_next[0] = alert_regwen_59_qs; + end + + addr_hit[66]: begin + reg_rdata_next[0] = alert_regwen_60_qs; + end + + addr_hit[67]: begin + reg_rdata_next[0] = alert_regwen_61_qs; + end + + addr_hit[68]: begin + reg_rdata_next[0] = alert_regwen_62_qs; + end + + addr_hit[69]: begin + reg_rdata_next[0] = alert_regwen_63_qs; + end + + addr_hit[70]: begin + reg_rdata_next[0] = alert_regwen_64_qs; + end + + addr_hit[71]: begin + reg_rdata_next[0] = alert_regwen_65_qs; + end + + addr_hit[72]: begin + reg_rdata_next[0] = alert_regwen_66_qs; + end + + addr_hit[73]: begin + reg_rdata_next[0] = alert_regwen_67_qs; + end + + addr_hit[74]: begin + reg_rdata_next[0] = alert_regwen_68_qs; + end + + addr_hit[75]: begin + reg_rdata_next[0] = alert_regwen_69_qs; + end + + addr_hit[76]: begin + reg_rdata_next[0] = alert_regwen_70_qs; + end + + addr_hit[77]: begin + reg_rdata_next[0] = alert_regwen_71_qs; + end + + addr_hit[78]: begin + reg_rdata_next[0] = alert_regwen_72_qs; + end + + addr_hit[79]: begin + reg_rdata_next[0] = alert_regwen_73_qs; + end + + addr_hit[80]: begin + reg_rdata_next[0] = alert_regwen_74_qs; + end + + addr_hit[81]: begin + reg_rdata_next[0] = alert_regwen_75_qs; + end + + addr_hit[82]: begin + reg_rdata_next[0] = alert_regwen_76_qs; + end + + addr_hit[83]: begin + reg_rdata_next[0] = alert_regwen_77_qs; + end + + addr_hit[84]: begin + reg_rdata_next[0] = alert_regwen_78_qs; + end + + addr_hit[85]: begin + reg_rdata_next[0] = alert_regwen_79_qs; + end + + addr_hit[86]: begin + reg_rdata_next[0] = alert_regwen_80_qs; + end + + addr_hit[87]: begin + reg_rdata_next[0] = alert_regwen_81_qs; + end + + addr_hit[88]: begin + reg_rdata_next[0] = alert_regwen_82_qs; + end + + addr_hit[89]: begin + reg_rdata_next[0] = alert_regwen_83_qs; + end + + addr_hit[90]: begin + reg_rdata_next[0] = alert_regwen_84_qs; + end + + addr_hit[91]: begin + reg_rdata_next[0] = alert_regwen_85_qs; + end + + addr_hit[92]: begin + reg_rdata_next[0] = alert_regwen_86_qs; + end + + addr_hit[93]: begin + reg_rdata_next[0] = alert_regwen_87_qs; + end + + addr_hit[94]: begin + reg_rdata_next[0] = alert_regwen_88_qs; + end + + addr_hit[95]: begin + reg_rdata_next[0] = alert_regwen_89_qs; + end + + addr_hit[96]: begin + reg_rdata_next[0] = alert_regwen_90_qs; + end + + addr_hit[97]: begin + reg_rdata_next[0] = alert_regwen_91_qs; + end + + addr_hit[98]: begin + reg_rdata_next[0] = alert_regwen_92_qs; + end + + addr_hit[99]: begin + reg_rdata_next[0] = alert_regwen_93_qs; + end + + addr_hit[100]: begin + reg_rdata_next[0] = alert_regwen_94_qs; + end + + addr_hit[101]: begin + reg_rdata_next[0] = alert_regwen_95_qs; + end + + addr_hit[102]: begin + reg_rdata_next[0] = alert_regwen_96_qs; + end + + addr_hit[103]: begin + reg_rdata_next[0] = alert_regwen_97_qs; + end + + addr_hit[104]: begin + reg_rdata_next[0] = alert_regwen_98_qs; + end + + addr_hit[105]: begin + reg_rdata_next[0] = alert_en_shadowed_0_qs; + end + + addr_hit[106]: begin + reg_rdata_next[0] = alert_en_shadowed_1_qs; + end + + addr_hit[107]: begin + reg_rdata_next[0] = alert_en_shadowed_2_qs; + end + + addr_hit[108]: begin + reg_rdata_next[0] = alert_en_shadowed_3_qs; + end + + addr_hit[109]: begin + reg_rdata_next[0] = alert_en_shadowed_4_qs; + end + + addr_hit[110]: begin + reg_rdata_next[0] = alert_en_shadowed_5_qs; + end + + addr_hit[111]: begin + reg_rdata_next[0] = alert_en_shadowed_6_qs; + end + + addr_hit[112]: begin + reg_rdata_next[0] = alert_en_shadowed_7_qs; + end + + addr_hit[113]: begin + reg_rdata_next[0] = alert_en_shadowed_8_qs; + end + + addr_hit[114]: begin + reg_rdata_next[0] = alert_en_shadowed_9_qs; + end + + addr_hit[115]: begin + reg_rdata_next[0] = alert_en_shadowed_10_qs; + end + + addr_hit[116]: begin + reg_rdata_next[0] = alert_en_shadowed_11_qs; + end + + addr_hit[117]: begin + reg_rdata_next[0] = alert_en_shadowed_12_qs; + end + + addr_hit[118]: begin + reg_rdata_next[0] = alert_en_shadowed_13_qs; + end + + addr_hit[119]: begin + reg_rdata_next[0] = alert_en_shadowed_14_qs; + end + + addr_hit[120]: begin + reg_rdata_next[0] = alert_en_shadowed_15_qs; + end + + addr_hit[121]: begin + reg_rdata_next[0] = alert_en_shadowed_16_qs; + end + + addr_hit[122]: begin + reg_rdata_next[0] = alert_en_shadowed_17_qs; + end + + addr_hit[123]: begin + reg_rdata_next[0] = alert_en_shadowed_18_qs; + end + + addr_hit[124]: begin + reg_rdata_next[0] = alert_en_shadowed_19_qs; + end + + addr_hit[125]: begin + reg_rdata_next[0] = alert_en_shadowed_20_qs; + end + + addr_hit[126]: begin + reg_rdata_next[0] = alert_en_shadowed_21_qs; + end + + addr_hit[127]: begin + reg_rdata_next[0] = alert_en_shadowed_22_qs; + end + + addr_hit[128]: begin + reg_rdata_next[0] = alert_en_shadowed_23_qs; + end + + addr_hit[129]: begin + reg_rdata_next[0] = alert_en_shadowed_24_qs; + end + + addr_hit[130]: begin + reg_rdata_next[0] = alert_en_shadowed_25_qs; + end + + addr_hit[131]: begin + reg_rdata_next[0] = alert_en_shadowed_26_qs; + end + + addr_hit[132]: begin + reg_rdata_next[0] = alert_en_shadowed_27_qs; + end + + addr_hit[133]: begin + reg_rdata_next[0] = alert_en_shadowed_28_qs; + end + + addr_hit[134]: begin + reg_rdata_next[0] = alert_en_shadowed_29_qs; + end + + addr_hit[135]: begin + reg_rdata_next[0] = alert_en_shadowed_30_qs; + end + + addr_hit[136]: begin + reg_rdata_next[0] = alert_en_shadowed_31_qs; + end + + addr_hit[137]: begin + reg_rdata_next[0] = alert_en_shadowed_32_qs; + end + + addr_hit[138]: begin + reg_rdata_next[0] = alert_en_shadowed_33_qs; + end + + addr_hit[139]: begin + reg_rdata_next[0] = alert_en_shadowed_34_qs; + end + + addr_hit[140]: begin + reg_rdata_next[0] = alert_en_shadowed_35_qs; + end + + addr_hit[141]: begin + reg_rdata_next[0] = alert_en_shadowed_36_qs; + end + + addr_hit[142]: begin + reg_rdata_next[0] = alert_en_shadowed_37_qs; + end + + addr_hit[143]: begin + reg_rdata_next[0] = alert_en_shadowed_38_qs; + end + + addr_hit[144]: begin + reg_rdata_next[0] = alert_en_shadowed_39_qs; + end + + addr_hit[145]: begin + reg_rdata_next[0] = alert_en_shadowed_40_qs; + end + + addr_hit[146]: begin + reg_rdata_next[0] = alert_en_shadowed_41_qs; + end + + addr_hit[147]: begin + reg_rdata_next[0] = alert_en_shadowed_42_qs; + end + + addr_hit[148]: begin + reg_rdata_next[0] = alert_en_shadowed_43_qs; + end + + addr_hit[149]: begin + reg_rdata_next[0] = alert_en_shadowed_44_qs; + end + + addr_hit[150]: begin + reg_rdata_next[0] = alert_en_shadowed_45_qs; + end + + addr_hit[151]: begin + reg_rdata_next[0] = alert_en_shadowed_46_qs; + end + + addr_hit[152]: begin + reg_rdata_next[0] = alert_en_shadowed_47_qs; + end + + addr_hit[153]: begin + reg_rdata_next[0] = alert_en_shadowed_48_qs; + end + + addr_hit[154]: begin + reg_rdata_next[0] = alert_en_shadowed_49_qs; + end + + addr_hit[155]: begin + reg_rdata_next[0] = alert_en_shadowed_50_qs; + end + + addr_hit[156]: begin + reg_rdata_next[0] = alert_en_shadowed_51_qs; + end + + addr_hit[157]: begin + reg_rdata_next[0] = alert_en_shadowed_52_qs; + end + + addr_hit[158]: begin + reg_rdata_next[0] = alert_en_shadowed_53_qs; + end + + addr_hit[159]: begin + reg_rdata_next[0] = alert_en_shadowed_54_qs; + end + + addr_hit[160]: begin + reg_rdata_next[0] = alert_en_shadowed_55_qs; + end + + addr_hit[161]: begin + reg_rdata_next[0] = alert_en_shadowed_56_qs; + end + + addr_hit[162]: begin + reg_rdata_next[0] = alert_en_shadowed_57_qs; + end + + addr_hit[163]: begin + reg_rdata_next[0] = alert_en_shadowed_58_qs; + end + + addr_hit[164]: begin + reg_rdata_next[0] = alert_en_shadowed_59_qs; + end + + addr_hit[165]: begin + reg_rdata_next[0] = alert_en_shadowed_60_qs; + end + + addr_hit[166]: begin + reg_rdata_next[0] = alert_en_shadowed_61_qs; + end + + addr_hit[167]: begin + reg_rdata_next[0] = alert_en_shadowed_62_qs; + end + + addr_hit[168]: begin + reg_rdata_next[0] = alert_en_shadowed_63_qs; + end + + addr_hit[169]: begin + reg_rdata_next[0] = alert_en_shadowed_64_qs; + end + + addr_hit[170]: begin + reg_rdata_next[0] = alert_en_shadowed_65_qs; + end + + addr_hit[171]: begin + reg_rdata_next[0] = alert_en_shadowed_66_qs; + end + + addr_hit[172]: begin + reg_rdata_next[0] = alert_en_shadowed_67_qs; + end + + addr_hit[173]: begin + reg_rdata_next[0] = alert_en_shadowed_68_qs; + end + + addr_hit[174]: begin + reg_rdata_next[0] = alert_en_shadowed_69_qs; + end + + addr_hit[175]: begin + reg_rdata_next[0] = alert_en_shadowed_70_qs; + end + + addr_hit[176]: begin + reg_rdata_next[0] = alert_en_shadowed_71_qs; + end + + addr_hit[177]: begin + reg_rdata_next[0] = alert_en_shadowed_72_qs; + end + + addr_hit[178]: begin + reg_rdata_next[0] = alert_en_shadowed_73_qs; + end + + addr_hit[179]: begin + reg_rdata_next[0] = alert_en_shadowed_74_qs; + end + + addr_hit[180]: begin + reg_rdata_next[0] = alert_en_shadowed_75_qs; + end + + addr_hit[181]: begin + reg_rdata_next[0] = alert_en_shadowed_76_qs; + end + + addr_hit[182]: begin + reg_rdata_next[0] = alert_en_shadowed_77_qs; + end + + addr_hit[183]: begin + reg_rdata_next[0] = alert_en_shadowed_78_qs; + end + + addr_hit[184]: begin + reg_rdata_next[0] = alert_en_shadowed_79_qs; + end + + addr_hit[185]: begin + reg_rdata_next[0] = alert_en_shadowed_80_qs; + end + + addr_hit[186]: begin + reg_rdata_next[0] = alert_en_shadowed_81_qs; + end + + addr_hit[187]: begin + reg_rdata_next[0] = alert_en_shadowed_82_qs; + end + + addr_hit[188]: begin + reg_rdata_next[0] = alert_en_shadowed_83_qs; + end + + addr_hit[189]: begin + reg_rdata_next[0] = alert_en_shadowed_84_qs; + end + + addr_hit[190]: begin + reg_rdata_next[0] = alert_en_shadowed_85_qs; + end + + addr_hit[191]: begin + reg_rdata_next[0] = alert_en_shadowed_86_qs; + end + + addr_hit[192]: begin + reg_rdata_next[0] = alert_en_shadowed_87_qs; + end + + addr_hit[193]: begin + reg_rdata_next[0] = alert_en_shadowed_88_qs; + end + + addr_hit[194]: begin + reg_rdata_next[0] = alert_en_shadowed_89_qs; + end + + addr_hit[195]: begin + reg_rdata_next[0] = alert_en_shadowed_90_qs; + end + + addr_hit[196]: begin + reg_rdata_next[0] = alert_en_shadowed_91_qs; + end + + addr_hit[197]: begin + reg_rdata_next[0] = alert_en_shadowed_92_qs; + end + + addr_hit[198]: begin + reg_rdata_next[0] = alert_en_shadowed_93_qs; + end + + addr_hit[199]: begin + reg_rdata_next[0] = alert_en_shadowed_94_qs; + end + + addr_hit[200]: begin + reg_rdata_next[0] = alert_en_shadowed_95_qs; + end + + addr_hit[201]: begin + reg_rdata_next[0] = alert_en_shadowed_96_qs; + end + + addr_hit[202]: begin + reg_rdata_next[0] = alert_en_shadowed_97_qs; + end + + addr_hit[203]: begin + reg_rdata_next[0] = alert_en_shadowed_98_qs; + end + + addr_hit[204]: begin + reg_rdata_next[1:0] = alert_class_shadowed_0_qs; + end + + addr_hit[205]: begin + reg_rdata_next[1:0] = alert_class_shadowed_1_qs; + end + + addr_hit[206]: begin + reg_rdata_next[1:0] = alert_class_shadowed_2_qs; + end + + addr_hit[207]: begin + reg_rdata_next[1:0] = alert_class_shadowed_3_qs; + end + + addr_hit[208]: begin + reg_rdata_next[1:0] = alert_class_shadowed_4_qs; + end + + addr_hit[209]: begin + reg_rdata_next[1:0] = alert_class_shadowed_5_qs; + end + + addr_hit[210]: begin + reg_rdata_next[1:0] = alert_class_shadowed_6_qs; + end + + addr_hit[211]: begin + reg_rdata_next[1:0] = alert_class_shadowed_7_qs; + end + + addr_hit[212]: begin + reg_rdata_next[1:0] = alert_class_shadowed_8_qs; + end + + addr_hit[213]: begin + reg_rdata_next[1:0] = alert_class_shadowed_9_qs; + end + + addr_hit[214]: begin + reg_rdata_next[1:0] = alert_class_shadowed_10_qs; + end + + addr_hit[215]: begin + reg_rdata_next[1:0] = alert_class_shadowed_11_qs; + end + + addr_hit[216]: begin + reg_rdata_next[1:0] = alert_class_shadowed_12_qs; + end + + addr_hit[217]: begin + reg_rdata_next[1:0] = alert_class_shadowed_13_qs; + end + + addr_hit[218]: begin + reg_rdata_next[1:0] = alert_class_shadowed_14_qs; + end + + addr_hit[219]: begin + reg_rdata_next[1:0] = alert_class_shadowed_15_qs; + end + + addr_hit[220]: begin + reg_rdata_next[1:0] = alert_class_shadowed_16_qs; + end + + addr_hit[221]: begin + reg_rdata_next[1:0] = alert_class_shadowed_17_qs; + end + + addr_hit[222]: begin + reg_rdata_next[1:0] = alert_class_shadowed_18_qs; + end + + addr_hit[223]: begin + reg_rdata_next[1:0] = alert_class_shadowed_19_qs; + end + + addr_hit[224]: begin + reg_rdata_next[1:0] = alert_class_shadowed_20_qs; + end + + addr_hit[225]: begin + reg_rdata_next[1:0] = alert_class_shadowed_21_qs; + end + + addr_hit[226]: begin + reg_rdata_next[1:0] = alert_class_shadowed_22_qs; + end + + addr_hit[227]: begin + reg_rdata_next[1:0] = alert_class_shadowed_23_qs; + end + + addr_hit[228]: begin + reg_rdata_next[1:0] = alert_class_shadowed_24_qs; + end + + addr_hit[229]: begin + reg_rdata_next[1:0] = alert_class_shadowed_25_qs; + end + + addr_hit[230]: begin + reg_rdata_next[1:0] = alert_class_shadowed_26_qs; + end + + addr_hit[231]: begin + reg_rdata_next[1:0] = alert_class_shadowed_27_qs; + end + + addr_hit[232]: begin + reg_rdata_next[1:0] = alert_class_shadowed_28_qs; + end + + addr_hit[233]: begin + reg_rdata_next[1:0] = alert_class_shadowed_29_qs; + end + + addr_hit[234]: begin + reg_rdata_next[1:0] = alert_class_shadowed_30_qs; + end + + addr_hit[235]: begin + reg_rdata_next[1:0] = alert_class_shadowed_31_qs; + end + + addr_hit[236]: begin + reg_rdata_next[1:0] = alert_class_shadowed_32_qs; + end + + addr_hit[237]: begin + reg_rdata_next[1:0] = alert_class_shadowed_33_qs; + end + + addr_hit[238]: begin + reg_rdata_next[1:0] = alert_class_shadowed_34_qs; + end + + addr_hit[239]: begin + reg_rdata_next[1:0] = alert_class_shadowed_35_qs; + end + + addr_hit[240]: begin + reg_rdata_next[1:0] = alert_class_shadowed_36_qs; + end + + addr_hit[241]: begin + reg_rdata_next[1:0] = alert_class_shadowed_37_qs; + end + + addr_hit[242]: begin + reg_rdata_next[1:0] = alert_class_shadowed_38_qs; + end + + addr_hit[243]: begin + reg_rdata_next[1:0] = alert_class_shadowed_39_qs; + end + + addr_hit[244]: begin + reg_rdata_next[1:0] = alert_class_shadowed_40_qs; + end + + addr_hit[245]: begin + reg_rdata_next[1:0] = alert_class_shadowed_41_qs; + end + + addr_hit[246]: begin + reg_rdata_next[1:0] = alert_class_shadowed_42_qs; + end + + addr_hit[247]: begin + reg_rdata_next[1:0] = alert_class_shadowed_43_qs; + end + + addr_hit[248]: begin + reg_rdata_next[1:0] = alert_class_shadowed_44_qs; + end + + addr_hit[249]: begin + reg_rdata_next[1:0] = alert_class_shadowed_45_qs; + end + + addr_hit[250]: begin + reg_rdata_next[1:0] = alert_class_shadowed_46_qs; + end + + addr_hit[251]: begin + reg_rdata_next[1:0] = alert_class_shadowed_47_qs; + end + + addr_hit[252]: begin + reg_rdata_next[1:0] = alert_class_shadowed_48_qs; + end + + addr_hit[253]: begin + reg_rdata_next[1:0] = alert_class_shadowed_49_qs; + end + + addr_hit[254]: begin + reg_rdata_next[1:0] = alert_class_shadowed_50_qs; + end + + addr_hit[255]: begin + reg_rdata_next[1:0] = alert_class_shadowed_51_qs; + end + + addr_hit[256]: begin + reg_rdata_next[1:0] = alert_class_shadowed_52_qs; + end + + addr_hit[257]: begin + reg_rdata_next[1:0] = alert_class_shadowed_53_qs; + end + + addr_hit[258]: begin + reg_rdata_next[1:0] = alert_class_shadowed_54_qs; + end + + addr_hit[259]: begin + reg_rdata_next[1:0] = alert_class_shadowed_55_qs; + end + + addr_hit[260]: begin + reg_rdata_next[1:0] = alert_class_shadowed_56_qs; + end + + addr_hit[261]: begin + reg_rdata_next[1:0] = alert_class_shadowed_57_qs; + end + + addr_hit[262]: begin + reg_rdata_next[1:0] = alert_class_shadowed_58_qs; + end + + addr_hit[263]: begin + reg_rdata_next[1:0] = alert_class_shadowed_59_qs; + end + + addr_hit[264]: begin + reg_rdata_next[1:0] = alert_class_shadowed_60_qs; + end + + addr_hit[265]: begin + reg_rdata_next[1:0] = alert_class_shadowed_61_qs; + end + + addr_hit[266]: begin + reg_rdata_next[1:0] = alert_class_shadowed_62_qs; + end + + addr_hit[267]: begin + reg_rdata_next[1:0] = alert_class_shadowed_63_qs; + end + + addr_hit[268]: begin + reg_rdata_next[1:0] = alert_class_shadowed_64_qs; + end + + addr_hit[269]: begin + reg_rdata_next[1:0] = alert_class_shadowed_65_qs; + end + + addr_hit[270]: begin + reg_rdata_next[1:0] = alert_class_shadowed_66_qs; + end + + addr_hit[271]: begin + reg_rdata_next[1:0] = alert_class_shadowed_67_qs; + end + + addr_hit[272]: begin + reg_rdata_next[1:0] = alert_class_shadowed_68_qs; + end + + addr_hit[273]: begin + reg_rdata_next[1:0] = alert_class_shadowed_69_qs; + end + + addr_hit[274]: begin + reg_rdata_next[1:0] = alert_class_shadowed_70_qs; + end + + addr_hit[275]: begin + reg_rdata_next[1:0] = alert_class_shadowed_71_qs; + end + + addr_hit[276]: begin + reg_rdata_next[1:0] = alert_class_shadowed_72_qs; + end + + addr_hit[277]: begin + reg_rdata_next[1:0] = alert_class_shadowed_73_qs; + end + + addr_hit[278]: begin + reg_rdata_next[1:0] = alert_class_shadowed_74_qs; + end + + addr_hit[279]: begin + reg_rdata_next[1:0] = alert_class_shadowed_75_qs; + end + + addr_hit[280]: begin + reg_rdata_next[1:0] = alert_class_shadowed_76_qs; + end + + addr_hit[281]: begin + reg_rdata_next[1:0] = alert_class_shadowed_77_qs; + end + + addr_hit[282]: begin + reg_rdata_next[1:0] = alert_class_shadowed_78_qs; + end + + addr_hit[283]: begin + reg_rdata_next[1:0] = alert_class_shadowed_79_qs; + end + + addr_hit[284]: begin + reg_rdata_next[1:0] = alert_class_shadowed_80_qs; + end + + addr_hit[285]: begin + reg_rdata_next[1:0] = alert_class_shadowed_81_qs; + end + + addr_hit[286]: begin + reg_rdata_next[1:0] = alert_class_shadowed_82_qs; + end + + addr_hit[287]: begin + reg_rdata_next[1:0] = alert_class_shadowed_83_qs; + end + + addr_hit[288]: begin + reg_rdata_next[1:0] = alert_class_shadowed_84_qs; + end + + addr_hit[289]: begin + reg_rdata_next[1:0] = alert_class_shadowed_85_qs; + end + + addr_hit[290]: begin + reg_rdata_next[1:0] = alert_class_shadowed_86_qs; + end + + addr_hit[291]: begin + reg_rdata_next[1:0] = alert_class_shadowed_87_qs; + end + + addr_hit[292]: begin + reg_rdata_next[1:0] = alert_class_shadowed_88_qs; + end + + addr_hit[293]: begin + reg_rdata_next[1:0] = alert_class_shadowed_89_qs; + end + + addr_hit[294]: begin + reg_rdata_next[1:0] = alert_class_shadowed_90_qs; + end + + addr_hit[295]: begin + reg_rdata_next[1:0] = alert_class_shadowed_91_qs; + end + + addr_hit[296]: begin + reg_rdata_next[1:0] = alert_class_shadowed_92_qs; + end + + addr_hit[297]: begin + reg_rdata_next[1:0] = alert_class_shadowed_93_qs; + end + + addr_hit[298]: begin + reg_rdata_next[1:0] = alert_class_shadowed_94_qs; + end + + addr_hit[299]: begin + reg_rdata_next[1:0] = alert_class_shadowed_95_qs; + end + + addr_hit[300]: begin + reg_rdata_next[1:0] = alert_class_shadowed_96_qs; + end + + addr_hit[301]: begin + reg_rdata_next[1:0] = alert_class_shadowed_97_qs; + end + + addr_hit[302]: begin + reg_rdata_next[1:0] = alert_class_shadowed_98_qs; + end + + addr_hit[303]: begin + reg_rdata_next[0] = alert_cause_0_qs; + end + + addr_hit[304]: begin + reg_rdata_next[0] = alert_cause_1_qs; + end + + addr_hit[305]: begin + reg_rdata_next[0] = alert_cause_2_qs; + end + + addr_hit[306]: begin + reg_rdata_next[0] = alert_cause_3_qs; + end + + addr_hit[307]: begin + reg_rdata_next[0] = alert_cause_4_qs; + end + + addr_hit[308]: begin + reg_rdata_next[0] = alert_cause_5_qs; + end + + addr_hit[309]: begin + reg_rdata_next[0] = alert_cause_6_qs; + end + + addr_hit[310]: begin + reg_rdata_next[0] = alert_cause_7_qs; + end + + addr_hit[311]: begin + reg_rdata_next[0] = alert_cause_8_qs; + end + + addr_hit[312]: begin + reg_rdata_next[0] = alert_cause_9_qs; + end + + addr_hit[313]: begin + reg_rdata_next[0] = alert_cause_10_qs; + end + + addr_hit[314]: begin + reg_rdata_next[0] = alert_cause_11_qs; + end + + addr_hit[315]: begin + reg_rdata_next[0] = alert_cause_12_qs; + end + + addr_hit[316]: begin + reg_rdata_next[0] = alert_cause_13_qs; + end + + addr_hit[317]: begin + reg_rdata_next[0] = alert_cause_14_qs; + end + + addr_hit[318]: begin + reg_rdata_next[0] = alert_cause_15_qs; + end + + addr_hit[319]: begin + reg_rdata_next[0] = alert_cause_16_qs; + end + + addr_hit[320]: begin + reg_rdata_next[0] = alert_cause_17_qs; + end + + addr_hit[321]: begin + reg_rdata_next[0] = alert_cause_18_qs; + end + + addr_hit[322]: begin + reg_rdata_next[0] = alert_cause_19_qs; + end + + addr_hit[323]: begin + reg_rdata_next[0] = alert_cause_20_qs; + end + + addr_hit[324]: begin + reg_rdata_next[0] = alert_cause_21_qs; + end + + addr_hit[325]: begin + reg_rdata_next[0] = alert_cause_22_qs; + end + + addr_hit[326]: begin + reg_rdata_next[0] = alert_cause_23_qs; + end + + addr_hit[327]: begin + reg_rdata_next[0] = alert_cause_24_qs; + end + + addr_hit[328]: begin + reg_rdata_next[0] = alert_cause_25_qs; + end + + addr_hit[329]: begin + reg_rdata_next[0] = alert_cause_26_qs; + end + + addr_hit[330]: begin + reg_rdata_next[0] = alert_cause_27_qs; + end + + addr_hit[331]: begin + reg_rdata_next[0] = alert_cause_28_qs; + end + + addr_hit[332]: begin + reg_rdata_next[0] = alert_cause_29_qs; + end + + addr_hit[333]: begin + reg_rdata_next[0] = alert_cause_30_qs; + end + + addr_hit[334]: begin + reg_rdata_next[0] = alert_cause_31_qs; + end + + addr_hit[335]: begin + reg_rdata_next[0] = alert_cause_32_qs; + end + + addr_hit[336]: begin + reg_rdata_next[0] = alert_cause_33_qs; + end + + addr_hit[337]: begin + reg_rdata_next[0] = alert_cause_34_qs; + end + + addr_hit[338]: begin + reg_rdata_next[0] = alert_cause_35_qs; + end + + addr_hit[339]: begin + reg_rdata_next[0] = alert_cause_36_qs; + end + + addr_hit[340]: begin + reg_rdata_next[0] = alert_cause_37_qs; + end + + addr_hit[341]: begin + reg_rdata_next[0] = alert_cause_38_qs; + end + + addr_hit[342]: begin + reg_rdata_next[0] = alert_cause_39_qs; + end + + addr_hit[343]: begin + reg_rdata_next[0] = alert_cause_40_qs; + end + + addr_hit[344]: begin + reg_rdata_next[0] = alert_cause_41_qs; + end + + addr_hit[345]: begin + reg_rdata_next[0] = alert_cause_42_qs; + end + + addr_hit[346]: begin + reg_rdata_next[0] = alert_cause_43_qs; + end + + addr_hit[347]: begin + reg_rdata_next[0] = alert_cause_44_qs; + end + + addr_hit[348]: begin + reg_rdata_next[0] = alert_cause_45_qs; + end + + addr_hit[349]: begin + reg_rdata_next[0] = alert_cause_46_qs; + end + + addr_hit[350]: begin + reg_rdata_next[0] = alert_cause_47_qs; + end + + addr_hit[351]: begin + reg_rdata_next[0] = alert_cause_48_qs; + end + + addr_hit[352]: begin + reg_rdata_next[0] = alert_cause_49_qs; + end + + addr_hit[353]: begin + reg_rdata_next[0] = alert_cause_50_qs; + end + + addr_hit[354]: begin + reg_rdata_next[0] = alert_cause_51_qs; + end + + addr_hit[355]: begin + reg_rdata_next[0] = alert_cause_52_qs; + end + + addr_hit[356]: begin + reg_rdata_next[0] = alert_cause_53_qs; + end + + addr_hit[357]: begin + reg_rdata_next[0] = alert_cause_54_qs; + end + + addr_hit[358]: begin + reg_rdata_next[0] = alert_cause_55_qs; + end + + addr_hit[359]: begin + reg_rdata_next[0] = alert_cause_56_qs; + end + + addr_hit[360]: begin + reg_rdata_next[0] = alert_cause_57_qs; + end + + addr_hit[361]: begin + reg_rdata_next[0] = alert_cause_58_qs; + end + + addr_hit[362]: begin + reg_rdata_next[0] = alert_cause_59_qs; + end + + addr_hit[363]: begin + reg_rdata_next[0] = alert_cause_60_qs; + end + + addr_hit[364]: begin + reg_rdata_next[0] = alert_cause_61_qs; + end + + addr_hit[365]: begin + reg_rdata_next[0] = alert_cause_62_qs; + end + + addr_hit[366]: begin + reg_rdata_next[0] = alert_cause_63_qs; + end + + addr_hit[367]: begin + reg_rdata_next[0] = alert_cause_64_qs; + end + + addr_hit[368]: begin + reg_rdata_next[0] = alert_cause_65_qs; + end + + addr_hit[369]: begin + reg_rdata_next[0] = alert_cause_66_qs; + end + + addr_hit[370]: begin + reg_rdata_next[0] = alert_cause_67_qs; + end + + addr_hit[371]: begin + reg_rdata_next[0] = alert_cause_68_qs; + end + + addr_hit[372]: begin + reg_rdata_next[0] = alert_cause_69_qs; + end + + addr_hit[373]: begin + reg_rdata_next[0] = alert_cause_70_qs; + end + + addr_hit[374]: begin + reg_rdata_next[0] = alert_cause_71_qs; + end + + addr_hit[375]: begin + reg_rdata_next[0] = alert_cause_72_qs; + end + + addr_hit[376]: begin + reg_rdata_next[0] = alert_cause_73_qs; + end + + addr_hit[377]: begin + reg_rdata_next[0] = alert_cause_74_qs; + end + + addr_hit[378]: begin + reg_rdata_next[0] = alert_cause_75_qs; + end + + addr_hit[379]: begin + reg_rdata_next[0] = alert_cause_76_qs; + end + + addr_hit[380]: begin + reg_rdata_next[0] = alert_cause_77_qs; + end + + addr_hit[381]: begin + reg_rdata_next[0] = alert_cause_78_qs; + end + + addr_hit[382]: begin + reg_rdata_next[0] = alert_cause_79_qs; + end + + addr_hit[383]: begin + reg_rdata_next[0] = alert_cause_80_qs; + end + + addr_hit[384]: begin + reg_rdata_next[0] = alert_cause_81_qs; + end + + addr_hit[385]: begin + reg_rdata_next[0] = alert_cause_82_qs; + end + + addr_hit[386]: begin + reg_rdata_next[0] = alert_cause_83_qs; + end + + addr_hit[387]: begin + reg_rdata_next[0] = alert_cause_84_qs; + end + + addr_hit[388]: begin + reg_rdata_next[0] = alert_cause_85_qs; + end + + addr_hit[389]: begin + reg_rdata_next[0] = alert_cause_86_qs; + end + + addr_hit[390]: begin + reg_rdata_next[0] = alert_cause_87_qs; + end + + addr_hit[391]: begin + reg_rdata_next[0] = alert_cause_88_qs; + end + + addr_hit[392]: begin + reg_rdata_next[0] = alert_cause_89_qs; + end + + addr_hit[393]: begin + reg_rdata_next[0] = alert_cause_90_qs; + end + + addr_hit[394]: begin + reg_rdata_next[0] = alert_cause_91_qs; + end + + addr_hit[395]: begin + reg_rdata_next[0] = alert_cause_92_qs; + end + + addr_hit[396]: begin + reg_rdata_next[0] = alert_cause_93_qs; + end + + addr_hit[397]: begin + reg_rdata_next[0] = alert_cause_94_qs; + end + + addr_hit[398]: begin + reg_rdata_next[0] = alert_cause_95_qs; + end + + addr_hit[399]: begin + reg_rdata_next[0] = alert_cause_96_qs; + end + + addr_hit[400]: begin + reg_rdata_next[0] = alert_cause_97_qs; + end + + addr_hit[401]: begin + reg_rdata_next[0] = alert_cause_98_qs; + end + + addr_hit[402]: begin + reg_rdata_next[0] = loc_alert_regwen_0_qs; + end + + addr_hit[403]: begin + reg_rdata_next[0] = loc_alert_regwen_1_qs; + end + + addr_hit[404]: begin + reg_rdata_next[0] = loc_alert_regwen_2_qs; + end + + addr_hit[405]: begin + reg_rdata_next[0] = loc_alert_regwen_3_qs; + end + + addr_hit[406]: begin + reg_rdata_next[0] = loc_alert_regwen_4_qs; + end + + addr_hit[407]: begin + reg_rdata_next[0] = loc_alert_regwen_5_qs; + end + + addr_hit[408]: begin + reg_rdata_next[0] = loc_alert_regwen_6_qs; + end + + addr_hit[409]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_0_qs; + end + + addr_hit[410]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_1_qs; + end + + addr_hit[411]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_2_qs; + end + + addr_hit[412]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_3_qs; + end + + addr_hit[413]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_4_qs; + end + + addr_hit[414]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_5_qs; + end + + addr_hit[415]: begin + reg_rdata_next[0] = loc_alert_en_shadowed_6_qs; + end + + addr_hit[416]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs; + end + + addr_hit[417]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs; + end + + addr_hit[418]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs; + end + + addr_hit[419]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs; + end + + addr_hit[420]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs; + end + + addr_hit[421]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs; + end + + addr_hit[422]: begin + reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs; + end + + addr_hit[423]: begin + reg_rdata_next[0] = loc_alert_cause_0_qs; + end + + addr_hit[424]: begin + reg_rdata_next[0] = loc_alert_cause_1_qs; + end + + addr_hit[425]: begin + reg_rdata_next[0] = loc_alert_cause_2_qs; + end + + addr_hit[426]: begin + reg_rdata_next[0] = loc_alert_cause_3_qs; + end + + addr_hit[427]: begin + reg_rdata_next[0] = loc_alert_cause_4_qs; + end + + addr_hit[428]: begin + reg_rdata_next[0] = loc_alert_cause_5_qs; + end + + addr_hit[429]: begin + reg_rdata_next[0] = loc_alert_cause_6_qs; + end + + addr_hit[430]: begin + reg_rdata_next[0] = classa_regwen_qs; + end + + addr_hit[431]: begin + reg_rdata_next[0] = classa_ctrl_shadowed_en_qs; + reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs; + reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs; + reg_rdata_next[3] = classa_ctrl_shadowed_en_e1_qs; + reg_rdata_next[4] = classa_ctrl_shadowed_en_e2_qs; + reg_rdata_next[5] = classa_ctrl_shadowed_en_e3_qs; + reg_rdata_next[7:6] = classa_ctrl_shadowed_map_e0_qs; + reg_rdata_next[9:8] = classa_ctrl_shadowed_map_e1_qs; + reg_rdata_next[11:10] = classa_ctrl_shadowed_map_e2_qs; + reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs; + end + + addr_hit[432]: begin + reg_rdata_next[0] = classa_clr_regwen_qs; + end + + addr_hit[433]: begin + reg_rdata_next[0] = classa_clr_shadowed_qs; + end + + addr_hit[434]: begin + reg_rdata_next[15:0] = classa_accum_cnt_qs; + end + + addr_hit[435]: begin + reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs; + end + + addr_hit[436]: begin + reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs; + end + + addr_hit[437]: begin + reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs; + end + + addr_hit[438]: begin + reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs; + end + + addr_hit[439]: begin + reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs; + end + + addr_hit[440]: begin + reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs; + end + + addr_hit[441]: begin + reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs; + end + + addr_hit[442]: begin + reg_rdata_next[31:0] = classa_esc_cnt_qs; + end + + addr_hit[443]: begin + reg_rdata_next[2:0] = classa_state_qs; + end + + addr_hit[444]: begin + reg_rdata_next[0] = classb_regwen_qs; + end + + addr_hit[445]: begin + reg_rdata_next[0] = classb_ctrl_shadowed_en_qs; + reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs; + reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs; + reg_rdata_next[3] = classb_ctrl_shadowed_en_e1_qs; + reg_rdata_next[4] = classb_ctrl_shadowed_en_e2_qs; + reg_rdata_next[5] = classb_ctrl_shadowed_en_e3_qs; + reg_rdata_next[7:6] = classb_ctrl_shadowed_map_e0_qs; + reg_rdata_next[9:8] = classb_ctrl_shadowed_map_e1_qs; + reg_rdata_next[11:10] = classb_ctrl_shadowed_map_e2_qs; + reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs; + end + + addr_hit[446]: begin + reg_rdata_next[0] = classb_clr_regwen_qs; + end + + addr_hit[447]: begin + reg_rdata_next[0] = classb_clr_shadowed_qs; + end + + addr_hit[448]: begin + reg_rdata_next[15:0] = classb_accum_cnt_qs; + end + + addr_hit[449]: begin + reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs; + end + + addr_hit[450]: begin + reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs; + end + + addr_hit[451]: begin + reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs; + end + + addr_hit[452]: begin + reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs; + end + + addr_hit[453]: begin + reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs; + end + + addr_hit[454]: begin + reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs; + end + + addr_hit[455]: begin + reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs; + end + + addr_hit[456]: begin + reg_rdata_next[31:0] = classb_esc_cnt_qs; + end + + addr_hit[457]: begin + reg_rdata_next[2:0] = classb_state_qs; + end + + addr_hit[458]: begin + reg_rdata_next[0] = classc_regwen_qs; + end + + addr_hit[459]: begin + reg_rdata_next[0] = classc_ctrl_shadowed_en_qs; + reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs; + reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs; + reg_rdata_next[3] = classc_ctrl_shadowed_en_e1_qs; + reg_rdata_next[4] = classc_ctrl_shadowed_en_e2_qs; + reg_rdata_next[5] = classc_ctrl_shadowed_en_e3_qs; + reg_rdata_next[7:6] = classc_ctrl_shadowed_map_e0_qs; + reg_rdata_next[9:8] = classc_ctrl_shadowed_map_e1_qs; + reg_rdata_next[11:10] = classc_ctrl_shadowed_map_e2_qs; + reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs; + end + + addr_hit[460]: begin + reg_rdata_next[0] = classc_clr_regwen_qs; + end + + addr_hit[461]: begin + reg_rdata_next[0] = classc_clr_shadowed_qs; + end + + addr_hit[462]: begin + reg_rdata_next[15:0] = classc_accum_cnt_qs; + end + + addr_hit[463]: begin + reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs; + end + + addr_hit[464]: begin + reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs; + end + + addr_hit[465]: begin + reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs; + end + + addr_hit[466]: begin + reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs; + end + + addr_hit[467]: begin + reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs; + end + + addr_hit[468]: begin + reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs; + end + + addr_hit[469]: begin + reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs; + end + + addr_hit[470]: begin + reg_rdata_next[31:0] = classc_esc_cnt_qs; + end + + addr_hit[471]: begin + reg_rdata_next[2:0] = classc_state_qs; + end + + addr_hit[472]: begin + reg_rdata_next[0] = classd_regwen_qs; + end + + addr_hit[473]: begin + reg_rdata_next[0] = classd_ctrl_shadowed_en_qs; + reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs; + reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs; + reg_rdata_next[3] = classd_ctrl_shadowed_en_e1_qs; + reg_rdata_next[4] = classd_ctrl_shadowed_en_e2_qs; + reg_rdata_next[5] = classd_ctrl_shadowed_en_e3_qs; + reg_rdata_next[7:6] = classd_ctrl_shadowed_map_e0_qs; + reg_rdata_next[9:8] = classd_ctrl_shadowed_map_e1_qs; + reg_rdata_next[11:10] = classd_ctrl_shadowed_map_e2_qs; + reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs; + end + + addr_hit[474]: begin + reg_rdata_next[0] = classd_clr_regwen_qs; + end + + addr_hit[475]: begin + reg_rdata_next[0] = classd_clr_shadowed_qs; + end + + addr_hit[476]: begin + reg_rdata_next[15:0] = classd_accum_cnt_qs; + end + + addr_hit[477]: begin + reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs; + end + + addr_hit[478]: begin + reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs; + end + + addr_hit[479]: begin + reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs; + end + + addr_hit[480]: begin + reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs; + end + + addr_hit[481]: begin + reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs; + end + + addr_hit[482]: begin + reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs; + end + + addr_hit[483]: begin + reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs; + end + + addr_hit[484]: begin + reg_rdata_next[31:0] = classd_esc_cnt_qs; + end + + addr_hit[485]: begin + reg_rdata_next[2:0] = classd_state_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + logic rst_done; + logic shadow_rst_done; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_done <= '0; + end else begin + rst_done <= 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin + if (!rst_shadowed_ni) begin + shadow_rst_done <= '0; + end else begin + shadow_rst_done <= 1'b1; + end + end + + // both shadow and normal resets have been released + assign shadow_busy = ~(rst_done & shadow_rst_done); + + // Collect up storage and update errors + assign shadowed_storage_err_o = |{ + ping_timeout_cyc_shadowed_storage_err, + ping_timer_en_shadowed_storage_err, + alert_en_shadowed_0_storage_err, + alert_en_shadowed_1_storage_err, + alert_en_shadowed_2_storage_err, + alert_en_shadowed_3_storage_err, + alert_en_shadowed_4_storage_err, + alert_en_shadowed_5_storage_err, + alert_en_shadowed_6_storage_err, + alert_en_shadowed_7_storage_err, + alert_en_shadowed_8_storage_err, + alert_en_shadowed_9_storage_err, + alert_en_shadowed_10_storage_err, + alert_en_shadowed_11_storage_err, + alert_en_shadowed_12_storage_err, + alert_en_shadowed_13_storage_err, + alert_en_shadowed_14_storage_err, + alert_en_shadowed_15_storage_err, + alert_en_shadowed_16_storage_err, + alert_en_shadowed_17_storage_err, + alert_en_shadowed_18_storage_err, + alert_en_shadowed_19_storage_err, + alert_en_shadowed_20_storage_err, + alert_en_shadowed_21_storage_err, + alert_en_shadowed_22_storage_err, + alert_en_shadowed_23_storage_err, + alert_en_shadowed_24_storage_err, + alert_en_shadowed_25_storage_err, + alert_en_shadowed_26_storage_err, + alert_en_shadowed_27_storage_err, + alert_en_shadowed_28_storage_err, + alert_en_shadowed_29_storage_err, + alert_en_shadowed_30_storage_err, + alert_en_shadowed_31_storage_err, + alert_en_shadowed_32_storage_err, + alert_en_shadowed_33_storage_err, + alert_en_shadowed_34_storage_err, + alert_en_shadowed_35_storage_err, + alert_en_shadowed_36_storage_err, + alert_en_shadowed_37_storage_err, + alert_en_shadowed_38_storage_err, + alert_en_shadowed_39_storage_err, + alert_en_shadowed_40_storage_err, + alert_en_shadowed_41_storage_err, + alert_en_shadowed_42_storage_err, + alert_en_shadowed_43_storage_err, + alert_en_shadowed_44_storage_err, + alert_en_shadowed_45_storage_err, + alert_en_shadowed_46_storage_err, + alert_en_shadowed_47_storage_err, + alert_en_shadowed_48_storage_err, + alert_en_shadowed_49_storage_err, + alert_en_shadowed_50_storage_err, + alert_en_shadowed_51_storage_err, + alert_en_shadowed_52_storage_err, + alert_en_shadowed_53_storage_err, + alert_en_shadowed_54_storage_err, + alert_en_shadowed_55_storage_err, + alert_en_shadowed_56_storage_err, + alert_en_shadowed_57_storage_err, + alert_en_shadowed_58_storage_err, + alert_en_shadowed_59_storage_err, + alert_en_shadowed_60_storage_err, + alert_en_shadowed_61_storage_err, + alert_en_shadowed_62_storage_err, + alert_en_shadowed_63_storage_err, + alert_en_shadowed_64_storage_err, + alert_en_shadowed_65_storage_err, + alert_en_shadowed_66_storage_err, + alert_en_shadowed_67_storage_err, + alert_en_shadowed_68_storage_err, + alert_en_shadowed_69_storage_err, + alert_en_shadowed_70_storage_err, + alert_en_shadowed_71_storage_err, + alert_en_shadowed_72_storage_err, + alert_en_shadowed_73_storage_err, + alert_en_shadowed_74_storage_err, + alert_en_shadowed_75_storage_err, + alert_en_shadowed_76_storage_err, + alert_en_shadowed_77_storage_err, + alert_en_shadowed_78_storage_err, + alert_en_shadowed_79_storage_err, + alert_en_shadowed_80_storage_err, + alert_en_shadowed_81_storage_err, + alert_en_shadowed_82_storage_err, + alert_en_shadowed_83_storage_err, + alert_en_shadowed_84_storage_err, + alert_en_shadowed_85_storage_err, + alert_en_shadowed_86_storage_err, + alert_en_shadowed_87_storage_err, + alert_en_shadowed_88_storage_err, + alert_en_shadowed_89_storage_err, + alert_en_shadowed_90_storage_err, + alert_en_shadowed_91_storage_err, + alert_en_shadowed_92_storage_err, + alert_en_shadowed_93_storage_err, + alert_en_shadowed_94_storage_err, + alert_en_shadowed_95_storage_err, + alert_en_shadowed_96_storage_err, + alert_en_shadowed_97_storage_err, + alert_en_shadowed_98_storage_err, + alert_class_shadowed_0_storage_err, + alert_class_shadowed_1_storage_err, + alert_class_shadowed_2_storage_err, + alert_class_shadowed_3_storage_err, + alert_class_shadowed_4_storage_err, + alert_class_shadowed_5_storage_err, + alert_class_shadowed_6_storage_err, + alert_class_shadowed_7_storage_err, + alert_class_shadowed_8_storage_err, + alert_class_shadowed_9_storage_err, + alert_class_shadowed_10_storage_err, + alert_class_shadowed_11_storage_err, + alert_class_shadowed_12_storage_err, + alert_class_shadowed_13_storage_err, + alert_class_shadowed_14_storage_err, + alert_class_shadowed_15_storage_err, + alert_class_shadowed_16_storage_err, + alert_class_shadowed_17_storage_err, + alert_class_shadowed_18_storage_err, + alert_class_shadowed_19_storage_err, + alert_class_shadowed_20_storage_err, + alert_class_shadowed_21_storage_err, + alert_class_shadowed_22_storage_err, + alert_class_shadowed_23_storage_err, + alert_class_shadowed_24_storage_err, + alert_class_shadowed_25_storage_err, + alert_class_shadowed_26_storage_err, + alert_class_shadowed_27_storage_err, + alert_class_shadowed_28_storage_err, + alert_class_shadowed_29_storage_err, + alert_class_shadowed_30_storage_err, + alert_class_shadowed_31_storage_err, + alert_class_shadowed_32_storage_err, + alert_class_shadowed_33_storage_err, + alert_class_shadowed_34_storage_err, + alert_class_shadowed_35_storage_err, + alert_class_shadowed_36_storage_err, + alert_class_shadowed_37_storage_err, + alert_class_shadowed_38_storage_err, + alert_class_shadowed_39_storage_err, + alert_class_shadowed_40_storage_err, + alert_class_shadowed_41_storage_err, + alert_class_shadowed_42_storage_err, + alert_class_shadowed_43_storage_err, + alert_class_shadowed_44_storage_err, + alert_class_shadowed_45_storage_err, + alert_class_shadowed_46_storage_err, + alert_class_shadowed_47_storage_err, + alert_class_shadowed_48_storage_err, + alert_class_shadowed_49_storage_err, + alert_class_shadowed_50_storage_err, + alert_class_shadowed_51_storage_err, + alert_class_shadowed_52_storage_err, + alert_class_shadowed_53_storage_err, + alert_class_shadowed_54_storage_err, + alert_class_shadowed_55_storage_err, + alert_class_shadowed_56_storage_err, + alert_class_shadowed_57_storage_err, + alert_class_shadowed_58_storage_err, + alert_class_shadowed_59_storage_err, + alert_class_shadowed_60_storage_err, + alert_class_shadowed_61_storage_err, + alert_class_shadowed_62_storage_err, + alert_class_shadowed_63_storage_err, + alert_class_shadowed_64_storage_err, + alert_class_shadowed_65_storage_err, + alert_class_shadowed_66_storage_err, + alert_class_shadowed_67_storage_err, + alert_class_shadowed_68_storage_err, + alert_class_shadowed_69_storage_err, + alert_class_shadowed_70_storage_err, + alert_class_shadowed_71_storage_err, + alert_class_shadowed_72_storage_err, + alert_class_shadowed_73_storage_err, + alert_class_shadowed_74_storage_err, + alert_class_shadowed_75_storage_err, + alert_class_shadowed_76_storage_err, + alert_class_shadowed_77_storage_err, + alert_class_shadowed_78_storage_err, + alert_class_shadowed_79_storage_err, + alert_class_shadowed_80_storage_err, + alert_class_shadowed_81_storage_err, + alert_class_shadowed_82_storage_err, + alert_class_shadowed_83_storage_err, + alert_class_shadowed_84_storage_err, + alert_class_shadowed_85_storage_err, + alert_class_shadowed_86_storage_err, + alert_class_shadowed_87_storage_err, + alert_class_shadowed_88_storage_err, + alert_class_shadowed_89_storage_err, + alert_class_shadowed_90_storage_err, + alert_class_shadowed_91_storage_err, + alert_class_shadowed_92_storage_err, + alert_class_shadowed_93_storage_err, + alert_class_shadowed_94_storage_err, + alert_class_shadowed_95_storage_err, + alert_class_shadowed_96_storage_err, + alert_class_shadowed_97_storage_err, + alert_class_shadowed_98_storage_err, + loc_alert_en_shadowed_0_storage_err, + loc_alert_en_shadowed_1_storage_err, + loc_alert_en_shadowed_2_storage_err, + loc_alert_en_shadowed_3_storage_err, + loc_alert_en_shadowed_4_storage_err, + loc_alert_en_shadowed_5_storage_err, + loc_alert_en_shadowed_6_storage_err, + loc_alert_class_shadowed_0_storage_err, + loc_alert_class_shadowed_1_storage_err, + loc_alert_class_shadowed_2_storage_err, + loc_alert_class_shadowed_3_storage_err, + loc_alert_class_shadowed_4_storage_err, + loc_alert_class_shadowed_5_storage_err, + loc_alert_class_shadowed_6_storage_err, + classa_ctrl_shadowed_en_storage_err, + classa_ctrl_shadowed_lock_storage_err, + classa_ctrl_shadowed_en_e0_storage_err, + classa_ctrl_shadowed_en_e1_storage_err, + classa_ctrl_shadowed_en_e2_storage_err, + classa_ctrl_shadowed_en_e3_storage_err, + classa_ctrl_shadowed_map_e0_storage_err, + classa_ctrl_shadowed_map_e1_storage_err, + classa_ctrl_shadowed_map_e2_storage_err, + classa_ctrl_shadowed_map_e3_storage_err, + classa_clr_shadowed_storage_err, + classa_accum_thresh_shadowed_storage_err, + classa_timeout_cyc_shadowed_storage_err, + classa_crashdump_trigger_shadowed_storage_err, + classa_phase0_cyc_shadowed_storage_err, + classa_phase1_cyc_shadowed_storage_err, + classa_phase2_cyc_shadowed_storage_err, + classa_phase3_cyc_shadowed_storage_err, + classb_ctrl_shadowed_en_storage_err, + classb_ctrl_shadowed_lock_storage_err, + classb_ctrl_shadowed_en_e0_storage_err, + classb_ctrl_shadowed_en_e1_storage_err, + classb_ctrl_shadowed_en_e2_storage_err, + classb_ctrl_shadowed_en_e3_storage_err, + classb_ctrl_shadowed_map_e0_storage_err, + classb_ctrl_shadowed_map_e1_storage_err, + classb_ctrl_shadowed_map_e2_storage_err, + classb_ctrl_shadowed_map_e3_storage_err, + classb_clr_shadowed_storage_err, + classb_accum_thresh_shadowed_storage_err, + classb_timeout_cyc_shadowed_storage_err, + classb_crashdump_trigger_shadowed_storage_err, + classb_phase0_cyc_shadowed_storage_err, + classb_phase1_cyc_shadowed_storage_err, + classb_phase2_cyc_shadowed_storage_err, + classb_phase3_cyc_shadowed_storage_err, + classc_ctrl_shadowed_en_storage_err, + classc_ctrl_shadowed_lock_storage_err, + classc_ctrl_shadowed_en_e0_storage_err, + classc_ctrl_shadowed_en_e1_storage_err, + classc_ctrl_shadowed_en_e2_storage_err, + classc_ctrl_shadowed_en_e3_storage_err, + classc_ctrl_shadowed_map_e0_storage_err, + classc_ctrl_shadowed_map_e1_storage_err, + classc_ctrl_shadowed_map_e2_storage_err, + classc_ctrl_shadowed_map_e3_storage_err, + classc_clr_shadowed_storage_err, + classc_accum_thresh_shadowed_storage_err, + classc_timeout_cyc_shadowed_storage_err, + classc_crashdump_trigger_shadowed_storage_err, + classc_phase0_cyc_shadowed_storage_err, + classc_phase1_cyc_shadowed_storage_err, + classc_phase2_cyc_shadowed_storage_err, + classc_phase3_cyc_shadowed_storage_err, + classd_ctrl_shadowed_en_storage_err, + classd_ctrl_shadowed_lock_storage_err, + classd_ctrl_shadowed_en_e0_storage_err, + classd_ctrl_shadowed_en_e1_storage_err, + classd_ctrl_shadowed_en_e2_storage_err, + classd_ctrl_shadowed_en_e3_storage_err, + classd_ctrl_shadowed_map_e0_storage_err, + classd_ctrl_shadowed_map_e1_storage_err, + classd_ctrl_shadowed_map_e2_storage_err, + classd_ctrl_shadowed_map_e3_storage_err, + classd_clr_shadowed_storage_err, + classd_accum_thresh_shadowed_storage_err, + classd_timeout_cyc_shadowed_storage_err, + classd_crashdump_trigger_shadowed_storage_err, + classd_phase0_cyc_shadowed_storage_err, + classd_phase1_cyc_shadowed_storage_err, + classd_phase2_cyc_shadowed_storage_err, + classd_phase3_cyc_shadowed_storage_err + }; + assign shadowed_update_err_o = |{ + ping_timeout_cyc_shadowed_update_err, + ping_timer_en_shadowed_update_err, + alert_en_shadowed_0_update_err, + alert_en_shadowed_1_update_err, + alert_en_shadowed_2_update_err, + alert_en_shadowed_3_update_err, + alert_en_shadowed_4_update_err, + alert_en_shadowed_5_update_err, + alert_en_shadowed_6_update_err, + alert_en_shadowed_7_update_err, + alert_en_shadowed_8_update_err, + alert_en_shadowed_9_update_err, + alert_en_shadowed_10_update_err, + alert_en_shadowed_11_update_err, + alert_en_shadowed_12_update_err, + alert_en_shadowed_13_update_err, + alert_en_shadowed_14_update_err, + alert_en_shadowed_15_update_err, + alert_en_shadowed_16_update_err, + alert_en_shadowed_17_update_err, + alert_en_shadowed_18_update_err, + alert_en_shadowed_19_update_err, + alert_en_shadowed_20_update_err, + alert_en_shadowed_21_update_err, + alert_en_shadowed_22_update_err, + alert_en_shadowed_23_update_err, + alert_en_shadowed_24_update_err, + alert_en_shadowed_25_update_err, + alert_en_shadowed_26_update_err, + alert_en_shadowed_27_update_err, + alert_en_shadowed_28_update_err, + alert_en_shadowed_29_update_err, + alert_en_shadowed_30_update_err, + alert_en_shadowed_31_update_err, + alert_en_shadowed_32_update_err, + alert_en_shadowed_33_update_err, + alert_en_shadowed_34_update_err, + alert_en_shadowed_35_update_err, + alert_en_shadowed_36_update_err, + alert_en_shadowed_37_update_err, + alert_en_shadowed_38_update_err, + alert_en_shadowed_39_update_err, + alert_en_shadowed_40_update_err, + alert_en_shadowed_41_update_err, + alert_en_shadowed_42_update_err, + alert_en_shadowed_43_update_err, + alert_en_shadowed_44_update_err, + alert_en_shadowed_45_update_err, + alert_en_shadowed_46_update_err, + alert_en_shadowed_47_update_err, + alert_en_shadowed_48_update_err, + alert_en_shadowed_49_update_err, + alert_en_shadowed_50_update_err, + alert_en_shadowed_51_update_err, + alert_en_shadowed_52_update_err, + alert_en_shadowed_53_update_err, + alert_en_shadowed_54_update_err, + alert_en_shadowed_55_update_err, + alert_en_shadowed_56_update_err, + alert_en_shadowed_57_update_err, + alert_en_shadowed_58_update_err, + alert_en_shadowed_59_update_err, + alert_en_shadowed_60_update_err, + alert_en_shadowed_61_update_err, + alert_en_shadowed_62_update_err, + alert_en_shadowed_63_update_err, + alert_en_shadowed_64_update_err, + alert_en_shadowed_65_update_err, + alert_en_shadowed_66_update_err, + alert_en_shadowed_67_update_err, + alert_en_shadowed_68_update_err, + alert_en_shadowed_69_update_err, + alert_en_shadowed_70_update_err, + alert_en_shadowed_71_update_err, + alert_en_shadowed_72_update_err, + alert_en_shadowed_73_update_err, + alert_en_shadowed_74_update_err, + alert_en_shadowed_75_update_err, + alert_en_shadowed_76_update_err, + alert_en_shadowed_77_update_err, + alert_en_shadowed_78_update_err, + alert_en_shadowed_79_update_err, + alert_en_shadowed_80_update_err, + alert_en_shadowed_81_update_err, + alert_en_shadowed_82_update_err, + alert_en_shadowed_83_update_err, + alert_en_shadowed_84_update_err, + alert_en_shadowed_85_update_err, + alert_en_shadowed_86_update_err, + alert_en_shadowed_87_update_err, + alert_en_shadowed_88_update_err, + alert_en_shadowed_89_update_err, + alert_en_shadowed_90_update_err, + alert_en_shadowed_91_update_err, + alert_en_shadowed_92_update_err, + alert_en_shadowed_93_update_err, + alert_en_shadowed_94_update_err, + alert_en_shadowed_95_update_err, + alert_en_shadowed_96_update_err, + alert_en_shadowed_97_update_err, + alert_en_shadowed_98_update_err, + alert_class_shadowed_0_update_err, + alert_class_shadowed_1_update_err, + alert_class_shadowed_2_update_err, + alert_class_shadowed_3_update_err, + alert_class_shadowed_4_update_err, + alert_class_shadowed_5_update_err, + alert_class_shadowed_6_update_err, + alert_class_shadowed_7_update_err, + alert_class_shadowed_8_update_err, + alert_class_shadowed_9_update_err, + alert_class_shadowed_10_update_err, + alert_class_shadowed_11_update_err, + alert_class_shadowed_12_update_err, + alert_class_shadowed_13_update_err, + alert_class_shadowed_14_update_err, + alert_class_shadowed_15_update_err, + alert_class_shadowed_16_update_err, + alert_class_shadowed_17_update_err, + alert_class_shadowed_18_update_err, + alert_class_shadowed_19_update_err, + alert_class_shadowed_20_update_err, + alert_class_shadowed_21_update_err, + alert_class_shadowed_22_update_err, + alert_class_shadowed_23_update_err, + alert_class_shadowed_24_update_err, + alert_class_shadowed_25_update_err, + alert_class_shadowed_26_update_err, + alert_class_shadowed_27_update_err, + alert_class_shadowed_28_update_err, + alert_class_shadowed_29_update_err, + alert_class_shadowed_30_update_err, + alert_class_shadowed_31_update_err, + alert_class_shadowed_32_update_err, + alert_class_shadowed_33_update_err, + alert_class_shadowed_34_update_err, + alert_class_shadowed_35_update_err, + alert_class_shadowed_36_update_err, + alert_class_shadowed_37_update_err, + alert_class_shadowed_38_update_err, + alert_class_shadowed_39_update_err, + alert_class_shadowed_40_update_err, + alert_class_shadowed_41_update_err, + alert_class_shadowed_42_update_err, + alert_class_shadowed_43_update_err, + alert_class_shadowed_44_update_err, + alert_class_shadowed_45_update_err, + alert_class_shadowed_46_update_err, + alert_class_shadowed_47_update_err, + alert_class_shadowed_48_update_err, + alert_class_shadowed_49_update_err, + alert_class_shadowed_50_update_err, + alert_class_shadowed_51_update_err, + alert_class_shadowed_52_update_err, + alert_class_shadowed_53_update_err, + alert_class_shadowed_54_update_err, + alert_class_shadowed_55_update_err, + alert_class_shadowed_56_update_err, + alert_class_shadowed_57_update_err, + alert_class_shadowed_58_update_err, + alert_class_shadowed_59_update_err, + alert_class_shadowed_60_update_err, + alert_class_shadowed_61_update_err, + alert_class_shadowed_62_update_err, + alert_class_shadowed_63_update_err, + alert_class_shadowed_64_update_err, + alert_class_shadowed_65_update_err, + alert_class_shadowed_66_update_err, + alert_class_shadowed_67_update_err, + alert_class_shadowed_68_update_err, + alert_class_shadowed_69_update_err, + alert_class_shadowed_70_update_err, + alert_class_shadowed_71_update_err, + alert_class_shadowed_72_update_err, + alert_class_shadowed_73_update_err, + alert_class_shadowed_74_update_err, + alert_class_shadowed_75_update_err, + alert_class_shadowed_76_update_err, + alert_class_shadowed_77_update_err, + alert_class_shadowed_78_update_err, + alert_class_shadowed_79_update_err, + alert_class_shadowed_80_update_err, + alert_class_shadowed_81_update_err, + alert_class_shadowed_82_update_err, + alert_class_shadowed_83_update_err, + alert_class_shadowed_84_update_err, + alert_class_shadowed_85_update_err, + alert_class_shadowed_86_update_err, + alert_class_shadowed_87_update_err, + alert_class_shadowed_88_update_err, + alert_class_shadowed_89_update_err, + alert_class_shadowed_90_update_err, + alert_class_shadowed_91_update_err, + alert_class_shadowed_92_update_err, + alert_class_shadowed_93_update_err, + alert_class_shadowed_94_update_err, + alert_class_shadowed_95_update_err, + alert_class_shadowed_96_update_err, + alert_class_shadowed_97_update_err, + alert_class_shadowed_98_update_err, + loc_alert_en_shadowed_0_update_err, + loc_alert_en_shadowed_1_update_err, + loc_alert_en_shadowed_2_update_err, + loc_alert_en_shadowed_3_update_err, + loc_alert_en_shadowed_4_update_err, + loc_alert_en_shadowed_5_update_err, + loc_alert_en_shadowed_6_update_err, + loc_alert_class_shadowed_0_update_err, + loc_alert_class_shadowed_1_update_err, + loc_alert_class_shadowed_2_update_err, + loc_alert_class_shadowed_3_update_err, + loc_alert_class_shadowed_4_update_err, + loc_alert_class_shadowed_5_update_err, + loc_alert_class_shadowed_6_update_err, + classa_ctrl_shadowed_en_update_err, + classa_ctrl_shadowed_lock_update_err, + classa_ctrl_shadowed_en_e0_update_err, + classa_ctrl_shadowed_en_e1_update_err, + classa_ctrl_shadowed_en_e2_update_err, + classa_ctrl_shadowed_en_e3_update_err, + classa_ctrl_shadowed_map_e0_update_err, + classa_ctrl_shadowed_map_e1_update_err, + classa_ctrl_shadowed_map_e2_update_err, + classa_ctrl_shadowed_map_e3_update_err, + classa_clr_shadowed_update_err, + classa_accum_thresh_shadowed_update_err, + classa_timeout_cyc_shadowed_update_err, + classa_crashdump_trigger_shadowed_update_err, + classa_phase0_cyc_shadowed_update_err, + classa_phase1_cyc_shadowed_update_err, + classa_phase2_cyc_shadowed_update_err, + classa_phase3_cyc_shadowed_update_err, + classb_ctrl_shadowed_en_update_err, + classb_ctrl_shadowed_lock_update_err, + classb_ctrl_shadowed_en_e0_update_err, + classb_ctrl_shadowed_en_e1_update_err, + classb_ctrl_shadowed_en_e2_update_err, + classb_ctrl_shadowed_en_e3_update_err, + classb_ctrl_shadowed_map_e0_update_err, + classb_ctrl_shadowed_map_e1_update_err, + classb_ctrl_shadowed_map_e2_update_err, + classb_ctrl_shadowed_map_e3_update_err, + classb_clr_shadowed_update_err, + classb_accum_thresh_shadowed_update_err, + classb_timeout_cyc_shadowed_update_err, + classb_crashdump_trigger_shadowed_update_err, + classb_phase0_cyc_shadowed_update_err, + classb_phase1_cyc_shadowed_update_err, + classb_phase2_cyc_shadowed_update_err, + classb_phase3_cyc_shadowed_update_err, + classc_ctrl_shadowed_en_update_err, + classc_ctrl_shadowed_lock_update_err, + classc_ctrl_shadowed_en_e0_update_err, + classc_ctrl_shadowed_en_e1_update_err, + classc_ctrl_shadowed_en_e2_update_err, + classc_ctrl_shadowed_en_e3_update_err, + classc_ctrl_shadowed_map_e0_update_err, + classc_ctrl_shadowed_map_e1_update_err, + classc_ctrl_shadowed_map_e2_update_err, + classc_ctrl_shadowed_map_e3_update_err, + classc_clr_shadowed_update_err, + classc_accum_thresh_shadowed_update_err, + classc_timeout_cyc_shadowed_update_err, + classc_crashdump_trigger_shadowed_update_err, + classc_phase0_cyc_shadowed_update_err, + classc_phase1_cyc_shadowed_update_err, + classc_phase2_cyc_shadowed_update_err, + classc_phase3_cyc_shadowed_update_err, + classd_ctrl_shadowed_en_update_err, + classd_ctrl_shadowed_lock_update_err, + classd_ctrl_shadowed_en_e0_update_err, + classd_ctrl_shadowed_en_e1_update_err, + classd_ctrl_shadowed_en_e2_update_err, + classd_ctrl_shadowed_en_e3_update_err, + classd_ctrl_shadowed_map_e0_update_err, + classd_ctrl_shadowed_map_e1_update_err, + classd_ctrl_shadowed_map_e2_update_err, + classd_ctrl_shadowed_map_e3_update_err, + classd_clr_shadowed_update_err, + classd_accum_thresh_shadowed_update_err, + classd_timeout_cyc_shadowed_update_err, + classd_crashdump_trigger_shadowed_update_err, + classd_phase0_cyc_shadowed_update_err, + classd_phase1_cyc_shadowed_update_err, + classd_phase2_cyc_shadowed_update_err, + classd_phase3_cyc_shadowed_update_err + }; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_reg_wrap.sv b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_reg_wrap.sv new file mode 100644 index 00000000000..fccc762a6df --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/alert_handler/rtl/alert_handler_reg_wrap.sv @@ -0,0 +1,360 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Breakout / remapping wrapper for register file. + +module alert_handler_reg_wrap import alert_handler_pkg::*; ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + // Bus Interface (device) + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // interrupt + output logic [N_CLASSES-1:0] irq_o, + // State information for HW crashdump + input [N_CLASSES-1:0] latch_crashdump_i, + output alert_crashdump_t crashdump_o, + // hw2reg + input hw2reg_wrap_t hw2reg_wrap, + // reg2hw + output reg2hw_wrap_t reg2hw_wrap, + // bus integrity alert + output logic fatal_integ_alert_o +); + + + ////////////////// + // reg instance // + ////////////////// + + logic [N_CLASSES-1:0] class_autolock_en; + alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw; + alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg; + + alert_handler_reg_top u_reg ( + .clk_i, + .rst_ni, + .rst_shadowed_ni, + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + .shadowed_storage_err_o(reg2hw_wrap.shadowed_err_storage), + .shadowed_update_err_o(reg2hw_wrap.shadowed_err_update), + .intg_err_o(fatal_integ_alert_o) + ); + + //////////////// + // interrupts // + //////////////// + + prim_intr_hw #( + .Width(1) + ) u_irq_classa ( + .clk_i, + .rst_ni, + .event_intr_i ( hw2reg_wrap.class_trig[0] ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classa.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.classa.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classa.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.classa.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.classa.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.classa.d ), + .intr_o ( irq_o[0] ) + ); + + prim_intr_hw #( + .Width(1) + ) u_irq_classb ( + .clk_i, + .rst_ni, + .event_intr_i ( hw2reg_wrap.class_trig[1] ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classb.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.classb.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classb.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.classb.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.classb.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.classb.d ), + .intr_o ( irq_o[1] ) + ); + + prim_intr_hw #( + .Width(1) + ) u_irq_classc ( + .clk_i, + .rst_ni, + .event_intr_i ( hw2reg_wrap.class_trig[2] ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classc.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.classc.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classc.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.classc.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.classc.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.classc.d ), + .intr_o ( irq_o[2] ) + ); + + prim_intr_hw #( + .Width(1) + ) u_irq_classd ( + .clk_i, + .rst_ni, + .event_intr_i ( hw2reg_wrap.class_trig[3] ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.classd.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.classd.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.classd.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.classd.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.classd.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.classd.d ), + .intr_o ( irq_o[3] ) + ); + + ///////////////////// + // hw2reg mappings // + ///////////////////// + + // if an alert is enabled and it fires, + // we have to set the corresponding cause bit + for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause + assign hw2reg.alert_cause[k].d = 1'b1; + assign hw2reg.alert_cause[k].de = reg2hw.alert_cause[k].q | + hw2reg_wrap.alert_cause[k]; + end + + // if a local alert is enabled and it fires, + // we have to set the corresponding cause bit + for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause + assign hw2reg.loc_alert_cause[k].d = 1'b1; + assign hw2reg.loc_alert_cause[k].de = reg2hw.loc_alert_cause[k].q | + hw2reg_wrap.loc_alert_cause[k]; + end + + // ping timeout in cycles + // autolock can clear these regs automatically upon entering escalation + // note: the class must be activated for this to occur + assign { hw2reg.classd_clr_regwen.d, + hw2reg.classc_clr_regwen.d, + hw2reg.classb_clr_regwen.d, + hw2reg.classa_clr_regwen.d } = '0; + + assign { hw2reg.classd_clr_regwen.de, + hw2reg.classc_clr_regwen.de, + hw2reg.classb_clr_regwen.de, + hw2reg.classa_clr_regwen.de } = hw2reg_wrap.class_esc_trig & + class_autolock_en & + reg2hw_wrap.class_en; + + // current accumulator counts + assign { hw2reg.classd_accum_cnt.d, + hw2reg.classc_accum_cnt.d, + hw2reg.classb_accum_cnt.d, + hw2reg.classa_accum_cnt.d } = hw2reg_wrap.class_accum_cnt; + + // current accumulator counts + assign { hw2reg.classd_esc_cnt.d, + hw2reg.classc_esc_cnt.d, + hw2reg.classb_esc_cnt.d, + hw2reg.classa_esc_cnt.d } = hw2reg_wrap.class_esc_cnt; + + // current accumulator counts + assign { hw2reg.classd_state.d, + hw2reg.classc_state.d, + hw2reg.classb_state.d, + hw2reg.classa_state.d } = hw2reg_wrap.class_esc_state; + + ///////////////////// + // reg2hw mappings // + ///////////////////// + + // config register lock + assign reg2hw_wrap.ping_enable = reg2hw.ping_timer_en_shadowed.q; + + // alert enable and class assignments + for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_en_class + // we only ping enabled alerts that are locked + assign reg2hw_wrap.alert_ping_en[k] = reg2hw.alert_en_shadowed[k].q & + ~reg2hw.alert_regwen[k].q; + assign reg2hw_wrap.alert_en[k] = reg2hw.alert_en_shadowed[k].q; + assign reg2hw_wrap.alert_class[k] = reg2hw.alert_class_shadowed[k].q; + end + + // local alert enable and class assignments + for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_en_class + assign reg2hw_wrap.loc_alert_en[k] = reg2hw.loc_alert_en_shadowed[k].q; + assign reg2hw_wrap.loc_alert_class[k] = reg2hw.loc_alert_class_shadowed[k].q; + end + + assign reg2hw_wrap.ping_timeout_cyc = reg2hw.ping_timeout_cyc_shadowed.q; + + // class enable + // we require that at least one of the enable signals is + // set for a class to be enabled + assign reg2hw_wrap.class_en = { + reg2hw.classd_ctrl_shadowed.en.q & ( reg2hw.classd_ctrl_shadowed.en_e3.q | + reg2hw.classd_ctrl_shadowed.en_e2.q | + reg2hw.classd_ctrl_shadowed.en_e1.q | + reg2hw.classd_ctrl_shadowed.en_e0.q ), + // + reg2hw.classc_ctrl_shadowed.en.q & ( reg2hw.classc_ctrl_shadowed.en_e3.q | + reg2hw.classc_ctrl_shadowed.en_e2.q | + reg2hw.classc_ctrl_shadowed.en_e1.q | + reg2hw.classc_ctrl_shadowed.en_e0.q ), + // + reg2hw.classb_ctrl_shadowed.en.q & ( reg2hw.classb_ctrl_shadowed.en_e3.q | + reg2hw.classb_ctrl_shadowed.en_e2.q | + reg2hw.classb_ctrl_shadowed.en_e1.q | + reg2hw.classb_ctrl_shadowed.en_e0.q ), + // + reg2hw.classa_ctrl_shadowed.en.q & ( reg2hw.classa_ctrl_shadowed.en_e3.q | + reg2hw.classa_ctrl_shadowed.en_e2.q | + reg2hw.classa_ctrl_shadowed.en_e1.q | + reg2hw.classa_ctrl_shadowed.en_e0.q ) + }; + + + // autolock enable + assign class_autolock_en = { reg2hw.classd_ctrl_shadowed.lock.q, + reg2hw.classc_ctrl_shadowed.lock.q, + reg2hw.classb_ctrl_shadowed.lock.q, + reg2hw.classa_ctrl_shadowed.lock.q }; + + // escalation signal enable + assign reg2hw_wrap.class_esc_en = { reg2hw.classd_ctrl_shadowed.en_e3.q, + reg2hw.classd_ctrl_shadowed.en_e2.q, + reg2hw.classd_ctrl_shadowed.en_e1.q, + reg2hw.classd_ctrl_shadowed.en_e0.q, + // + reg2hw.classc_ctrl_shadowed.en_e3.q, + reg2hw.classc_ctrl_shadowed.en_e2.q, + reg2hw.classc_ctrl_shadowed.en_e1.q, + reg2hw.classc_ctrl_shadowed.en_e0.q, + // + reg2hw.classb_ctrl_shadowed.en_e3.q, + reg2hw.classb_ctrl_shadowed.en_e2.q, + reg2hw.classb_ctrl_shadowed.en_e1.q, + reg2hw.classb_ctrl_shadowed.en_e0.q, + // + reg2hw.classa_ctrl_shadowed.en_e3.q, + reg2hw.classa_ctrl_shadowed.en_e2.q, + reg2hw.classa_ctrl_shadowed.en_e1.q, + reg2hw.classa_ctrl_shadowed.en_e0.q }; + + + // escalation phase to escalation signal mapping + assign reg2hw_wrap.class_esc_map = { reg2hw.classd_ctrl_shadowed.map_e3.q, + reg2hw.classd_ctrl_shadowed.map_e2.q, + reg2hw.classd_ctrl_shadowed.map_e1.q, + reg2hw.classd_ctrl_shadowed.map_e0.q, + // + reg2hw.classc_ctrl_shadowed.map_e3.q, + reg2hw.classc_ctrl_shadowed.map_e2.q, + reg2hw.classc_ctrl_shadowed.map_e1.q, + reg2hw.classc_ctrl_shadowed.map_e0.q, + // + reg2hw.classb_ctrl_shadowed.map_e3.q, + reg2hw.classb_ctrl_shadowed.map_e2.q, + reg2hw.classb_ctrl_shadowed.map_e1.q, + reg2hw.classb_ctrl_shadowed.map_e0.q, + // + reg2hw.classa_ctrl_shadowed.map_e3.q, + reg2hw.classa_ctrl_shadowed.map_e2.q, + reg2hw.classa_ctrl_shadowed.map_e1.q, + reg2hw.classa_ctrl_shadowed.map_e0.q }; + + // Determines in which phase to latch the crashdump. + assign reg2hw_wrap.class_crashdump_phase = { reg2hw.classd_crashdump_trigger_shadowed.q, + reg2hw.classc_crashdump_trigger_shadowed.q, + reg2hw.classb_crashdump_trigger_shadowed.q, + reg2hw.classa_crashdump_trigger_shadowed.q }; + + // writing 1b1 to a class clr register clears the accumulator and + // escalation state if autolock is not asserted + assign reg2hw_wrap.class_clr = { reg2hw.classd_clr_shadowed.q & reg2hw.classd_clr_shadowed.qe, + reg2hw.classc_clr_shadowed.q & reg2hw.classc_clr_shadowed.qe, + reg2hw.classb_clr_shadowed.q & reg2hw.classb_clr_shadowed.qe, + reg2hw.classa_clr_shadowed.q & reg2hw.classa_clr_shadowed.qe }; + + + // accumulator thresholds + assign reg2hw_wrap.class_accum_thresh = { reg2hw.classd_accum_thresh_shadowed.q, + reg2hw.classc_accum_thresh_shadowed.q, + reg2hw.classb_accum_thresh_shadowed.q, + reg2hw.classa_accum_thresh_shadowed.q }; + + // interrupt timeout lengths + assign reg2hw_wrap.class_timeout_cyc = { reg2hw.classd_timeout_cyc_shadowed.q, + reg2hw.classc_timeout_cyc_shadowed.q, + reg2hw.classb_timeout_cyc_shadowed.q, + reg2hw.classa_timeout_cyc_shadowed.q }; + // escalation phase lengths + assign reg2hw_wrap.class_phase_cyc = { reg2hw.classd_phase3_cyc_shadowed.q, + reg2hw.classd_phase2_cyc_shadowed.q, + reg2hw.classd_phase1_cyc_shadowed.q, + reg2hw.classd_phase0_cyc_shadowed.q, + // + reg2hw.classc_phase3_cyc_shadowed.q, + reg2hw.classc_phase2_cyc_shadowed.q, + reg2hw.classc_phase1_cyc_shadowed.q, + reg2hw.classc_phase0_cyc_shadowed.q, + // + reg2hw.classb_phase3_cyc_shadowed.q, + reg2hw.classb_phase2_cyc_shadowed.q, + reg2hw.classb_phase1_cyc_shadowed.q, + reg2hw.classb_phase0_cyc_shadowed.q, + // + reg2hw.classa_phase3_cyc_shadowed.q, + reg2hw.classa_phase2_cyc_shadowed.q, + reg2hw.classa_phase1_cyc_shadowed.q, + reg2hw.classa_phase0_cyc_shadowed.q}; + + ////////////////////// + // crashdump output // + ////////////////////// + + logic [N_CLASSES-1:0] crashdump_latched_q; + alert_crashdump_t crashdump_d, crashdump_q; + + // alert cause output + for (genvar k = 0; k < NAlerts; k++) begin : gen_alert_cause_dump + assign crashdump_d.alert_cause[k] = reg2hw.alert_cause[k].q; + end + + // local alert cause register output + for (genvar k = 0; k < N_LOC_ALERT; k++) begin : gen_loc_alert_cause_dump + assign crashdump_d.loc_alert_cause[k] = reg2hw.loc_alert_cause[k].q; + end + + assign crashdump_d.class_accum_cnt = hw2reg_wrap.class_accum_cnt; + assign crashdump_d.class_esc_cnt = hw2reg_wrap.class_esc_cnt; + assign crashdump_d.class_esc_state = hw2reg_wrap.class_esc_state; + + // We latch the crashdump upon triggering any of the escalation protocols. The reason for this is + // that during escalation, certain alert senders may start to trigger due to FSMs being moved + // into escalation mode - thereby masking the actual alert reasons exposed in the cause + // registers. + always_ff @(posedge clk_i or negedge rst_ni) begin : p_crashdump + if (!rst_ni) begin + crashdump_latched_q <= '0; + crashdump_q <= '0; + end else begin + // We track which class has been escalated so that the crashdump latching mechanism cannot be + // re-armed by clearing another class that has not escalated yet. This also implies that if + // an unclearable class has escalated, the crashdump latching mechanism cannot be re-armed. + crashdump_latched_q <= (crashdump_latched_q & ~reg2hw_wrap.class_clr) | latch_crashdump_i; + + // The alert handler only captures the first escalation event that asserts a latch_crashdump_i + // signal, unless all classes are cleared, in which case the crashdump latching mechanism is + // re-armed. In other words, we latch the crashdump if any of the latch_crashdump_i bits is + // asserted, and no crashdump has been latched yet. + if (|latch_crashdump_i && !(|crashdump_latched_q)) begin + crashdump_q <= crashdump_d; + end + end + end + + // As long as the crashdump has not been latched yet, we output the current alert handler state. + // Once any of the classes has triggered the latching, we switch to the latched snapshot. + assign crashdump_o = (|crashdump_latched_q) ? crashdump_q : crashdump_d; + +endmodule : alert_handler_reg_wrap diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/BUILD new file mode 100644 index 00000000000..429b0397fe8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/BUILD @@ -0,0 +1,25 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.svg", + ]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/README.md new file mode 100644 index 00000000000..10649f1d9a8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/README.md @@ -0,0 +1,18 @@ +# Clock Manager HWIP Technical Specification + +[`clkmgr`](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/clkmgr/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/clkmgr/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/clkmgr/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/clkmgr/code.svg) + +# Overview + +This document specifies the functionality of the OpenTitan clock manager. + +## Features + +- Attribute based controls of OpenTitan clocks. +- Minimal software clock controls to reduce risks in clock manipulation. +- External clock switch support +- Clock frequency /time-out measurement diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/clkmgr.core b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/clkmgr.core new file mode 100644 index 00000000000..e2b30341a6f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/clkmgr.core @@ -0,0 +1,71 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:clkmgr:0.1 +description: "Top specific clock manager " + +filesets: + files_rtl: + depend: + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:prim:buf + - lowrisc:prim:clock_buf + - lowrisc:prim:clock_div + - lowrisc:prim:clock_gating + - lowrisc:prim:edge_detector + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:measure + - lowrisc:darjeeling_no_ibex_ip:clkmgr_pkg:0.1 + - lowrisc:darjeeling_no_ibex_ip:clkmgr_reg:0.1 + files: + - rtl/clkmgr.sv + - rtl/clkmgr_byp.sv + - rtl/clkmgr_clk_status.sv + - rtl/clkmgr_meas_chk.sv + - rtl/clkmgr_root_ctrl.sv + - rtl/clkmgr_trans.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/clkmgr.waiver + file_type: waiver + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - files_rtl + toplevel: clkmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/clkmgr_pkg.core b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/clkmgr_pkg.core new file mode 100644 index 00000000000..5e878eec0c2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/clkmgr_pkg.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:clkmgr_pkg:0.1 +description: "Top specific clock manager package" + +filesets: + files_rtl: + depend: + - lowrisc:prim:mubi + files: + - rtl/clkmgr_pkg.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/clkmgr_reg.core b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/clkmgr_reg.core new file mode 100644 index 00000000000..4a47dee6a7c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/clkmgr_reg.core @@ -0,0 +1,24 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:clkmgr_reg:0.1 +description: "Clock manager registers" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:subreg + - lowrisc:tlul:headers + - lowrisc:prim:assert + - lowrisc:prim:mubi_pkg + files: + - rtl/clkmgr_reg_pkg.sv + - rtl/clkmgr_reg_top.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/BUILD new file mode 100644 index 00000000000..c9e3900ef00 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/BUILD @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_clkmgr.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = glob([ + "clkmgr.hjson", + "*_testplan.hjson", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr.hjson new file mode 100644 index 00000000000..c890c505330 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr.hjson @@ -0,0 +1,776 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +# CLKMGR register template +# +{ + name: "clkmgr", + human_name: "Clock Manager", + one_line_desc: "Derives and monitors on-chip clock signals, handles clock gating requests from power manager and software", + one_paragraph_desc: ''' + Clock Manager derives on-chip clocks from root clock signals provided by Analog Sensor Top (AST). + Input and output clocks may be asynchronous to each other. + During clock derivation, Clock Manager can divide clocks to lower frequencies and gate clocks based on control signals from the power manager and to a limited extent from software. + For example, the idle status of relevant hardware blocks is tracked and clock gating requests from software are ignored as long as these blocks are active. + Further security features include switchable clock jitter, continuous monitoring of clock frequencies, and various countermeasures to deter fault injection (FI) attacks. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "4", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_clkmgr", + revisions: [ + { + version: "1.0.1", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + } + ] + scan: "true", + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {reset: "rst_root_ni"}, + {clock: "clk_main_i", reset: "rst_main_ni"}, + {clock: "clk_io_i", reset: "rst_io_ni"}, + {clock: "clk_aon_i", reset: "rst_aon_ni"}, + {clock: "clk_io_div2_i", reset: "rst_io_div2_ni", internal: true}, + {clock: "clk_io_div4_i", reset: "rst_io_div4_ni", internal: true}, + {reset: "rst_root_main_ni"}, + {reset: "rst_root_io_ni"}, + {reset: "rst_root_io_div2_ni"}, + {reset: "rst_root_io_div4_ni"}, + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + alert_list: [ + { name: "recov_fault", + desc: ''' + This recoverable alert is triggered when there are measurement errors. + ''' + } + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + regwidth: "32", + param_list: [ + { name: "NumGroups", + desc: "Number of clock groups", + type: "int", + default: "7", + local: "true" + }, + { name: "NumSwGateableClocks", + desc: "Number of SW gateable clocks", + type: "int", + default: "2", + local: "true" + }, + { name: "NumHintableClocks", + desc: "Number of hintable clocks", + type: "int", + default: "4", + local: "true" + }, + ], + + features: [ + { name: "CLKMGR.ENABLE.IO_DIV4", + desc: "Gating of IO_DIV4 peripheral clock." + } + { name: "CLKMGR.ENABLE.IO_DIV2", + desc: "Gating of IO_DIV2 peripheral clock." + } + { name: "CLKMGR.HINT.AES", + desc: "Gating of AES transactional clock." + } + { name: "CLKMGR.HINT.HMAC", + desc: "Gating of HMAC transactional clock." + } + { name: "CLKMGR.HINT.KMAC", + desc: "Gating of KMAC transactional clock." + } + { name: "CLKMGR.HINT.OTBN", + desc: "Gating of OTBN transactional clock." + } + { name: "CLKMGR.MEAS_CTRL.REGWEN", + desc: '''Control modification of all clock frequency and timeout + measurements. + ''' + } + { name: "CLKMGR.MEAS_CTRL.IO_DIV4", + desc: "Frequency and timeout measurements of IO_DIV4 clock." + } + { name: "CLKMGR.MEAS_CTRL.MAIN", + desc: "Frequency and timeout measurements of MAIN clock." + } + { name: "CLKMGR.MEAS_CTRL.RECOV_ERR", + desc: "Frequency and timeout measurements can flag recoverable errors." + } + { name: "CLKMGR.LC_EXTCLK.SPEED", + desc: "Speed of LC controlled modification of external clock." + } + { name: "CLKMGR.SW_EXTCLK.REGWEN", + desc: "Control software modification of external clock configuration." + } + { name: "CLKMGR.SW_EXTCLK.HIGH_SPEED", + desc: "Software configuration of external clock running at 96 MHz." + } + { name: "CLKMGR.SW_EXTCLK.LOW_SPEED", + desc: "Software configuration of external clock running at 48 MHz." + } + { name: "CLKMGR.JITTER.REGWEN", + desc: "Control modification of clock jitter enable." + } + { name: "CLKMGR.JITTER.ENABLE", + desc: "Enable clock jitter." + } + { name: "CLKMGR.ALERT_HANDLER.CLOCK_STATUS", + desc: "Inform alert handler about clock enable status for each clock." + } +] + + inter_signal_list: [ + { struct: "clkmgr_out", + type: "uni", + name: "clocks", + act: "req", + package: "clkmgr_pkg", + }, + + { struct: "clkmgr_cg_en", + type: "uni", + name: "cg_en", + act: "req", + package: "clkmgr_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_hw_debug_en", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "io_clk_byp_req", + act: "req", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "io_clk_byp_ack", + act: "rcv", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "all_clk_byp_req", + act: "req", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "all_clk_byp_ack", + act: "rcv", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "hi_speed_sel", + act: "req", + package: "prim_mubi_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "div_step_down_req", + act: "rcv", + package: "prim_mubi_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_clk_byp_req", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_clk_byp_ack", + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "jitter_en", + act: "req", + package: "prim_mubi_pkg" + }, + + // Exported clocks + + { struct: "pwr_clk", + type: "req_rsp", + name: "pwr", + act: "rsp", + }, + + { struct: "mubi4", + type: "uni", + name: "idle", + act: "rcv", + package: "prim_mubi_pkg", + width: "4" + }, + + { struct: "mubi4", + desc: "Indicates clocks are calibrated and frequencies accurate", + type: "uni", + name: "calib_rdy", + act: "rcv", + package: "prim_mubi_pkg", + default: "prim_mubi_pkg::MuBi4True" + }, + ], + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + }, + { name: "TIMEOUT.CLK.BKGN_CHK", + desc: "Background check for clock timeout." + }, + { name: "MEAS.CLK.BKGN_CHK", + desc: "Background check for clock frequency." + }, + { name: "MEAS.CONFIG.SHADOW", + desc: "Measurement configurations are shadowed." + } + { name: "IDLE.INTERSIG.MUBI", + desc: "Idle inputs are multibit encoded." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "The life cycle control signals are multibit encoded." + } + { name: "LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI", + desc: "The life cycle clock req/ack signals are multibit encoded." + } + { name: "CLK_HANDSHAKE.INTERSIG.MUBI", + desc: "The external clock req/ack signals are multibit encoded." + } + { name: "DIV.INTERSIG.MUBI", + desc: "Divider step down request is multibit encoded." + } + { name: "JITTER.CONFIG.MUBI", + desc: "The jitter enable configuration is multibit encoded." + } + { name: "IDLE.CTR.REDUN", + desc: "Idle counter is duplicated." + } + { name: "MEAS.CONFIG.REGWEN", + desc: "The measurement controls protected with regwen." + } + { name: "CLK_CTRL.CONFIG.REGWEN", + desc: "Software controlled clock requests are proteced with regwen." + } + + ] + + registers: [ + { name: "EXTCLK_CTRL_REGWEN", + desc: "External clock control write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, the value of !!EXTCLK_CTRL can be set. When 0, writes to !!EXTCLK_CTRL have no + effect. + ''' + }, + ] + }, + + { name: "EXTCLK_CTRL", + desc: ''' + Select external clock + ''', + regwen: "EXTCLK_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "3:0", + name: "SEL", + mubi: true, + desc: ''' + When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True + selects external clock as clock for the system. Writing any other value has + no impact. + + When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False + selects internal clock as clock for the system. Writing any other value during this stage + has no impact. + + While this register can always be programmed, it only takes effect when debug functions are enabled + in life cycle TEST, DEV or RMA states. + ''' + resval: "false" + }, + { + bits: "7:4", + name: "HI_SPEED_SEL", + mubi: true, + desc: ''' + A value of kMultiBitBool4True selects nominal speed external clock. + All other values selects low speed clocks. + + Note this field only has an effect when the !!EXTCLK_CTRL.SEL field is set to + kMultiBitBool4True. + + Nominal speed means the external clock is approximately the same frequency as + the internal oscillator source. When this option is used, all clocks operate + at roughly the nominal frequency. + + Low speed means the external clock is approximately half the frequency of the + internal oscillator source. When this option is used, the internal dividers are + stepped down. As a result, previously undivided clocks now run at half frequency, + while previously divided clocks run at roughly the nominal frequency. + + See external clock switch support in documentation for more details. + ''' + resval: false + } + ] + // avoid writing random values to this register as it could trigger transient checks + // in mubi sync + tags: ["excl:CsrAllTests:CsrExclWrite"] + }, + + { name: "EXTCLK_STATUS", + desc: ''' + Status of requested external clock switch + ''', + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + fields: [ + { + bits: "3:0", + name: "ACK", + mubi: true, + desc: ''' + When !!EXTCLK_CTRL.SEL is set to kMultiBitBool4True, this field reflects + whether the clock has been switched the external source. + + kMultiBitBool4True indicates the switch is complete. + kMultiBitBool4False indicates the switch is either not possible or still ongoing. + ''' + resval: "false" + }, + ] + }, + + { name: "JITTER_REGWEN", + desc: "Jitter write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, the value of !!JITTER_ENABLE can be changed. When 0, writes have no + effect. + ''' + }, + ] + }, + + { name: "JITTER_ENABLE", + desc: ''' + Enable jittery clock + ''', + swaccess: "rw", + hwaccess: "hro", + regwen: "JITTER_REGWEN" + fields: [ + { + mubi: true, + bits: "3:0", + name: "VAL", + desc: ''' + Enable jittery clock. + A value of kMultiBitBool4False disables the jittery clock, + while all other values enable jittery clock. + ''', + resval: false + // avoid writing random values to this register as it could trigger transient checks + // in mubi sync + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + ] + }, + + { name: "CLK_ENABLES", + desc: ''' + Clock enable for software gateable clocks. + These clocks are directly controlled by software. + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0", + name: "CLK_IO_DIV4_PERI_EN", + resval: 1, + desc: ''' + 0 CLK_IO_DIV4_PERI is disabled. + 1 CLK_IO_DIV4_PERI is enabled. + ''' + } + { + bits: "1", + name: "CLK_IO_DIV2_PERI_EN", + resval: 1, + desc: ''' + 0 CLK_IO_DIV2_PERI is disabled. + 1 CLK_IO_DIV2_PERI is enabled. + ''' + } + ] + // the CLK_ENABLE register cannot be written. + // During top level randomized tests, it is possible to disable the clocks and then access + // a register in the disabled block. This would lead to a top level hang. + tags: ["excl:CsrAllTests:CsrExclAll"] + }, + + { name: "CLK_HINTS", + desc: ''' + Clock hint for software gateable transactional clocks during active mode. + During low power mode, all clocks are gated off regardless of the software hint. + + Transactional clocks are not fully controlled by software. Instead software provides only a disable hint. + + When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. + If the hardware block is idle, then the clock is disabled. + If the hardware block is not idle, the clock is kept on. + + For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any + feedback in this case. + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0", + name: "CLK_MAIN_AES_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_AES can be disabled. + 1 CLK_MAIN_AES is enabled. + ''' + } + { + bits: "1", + name: "CLK_MAIN_HMAC_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_HMAC can be disabled. + 1 CLK_MAIN_HMAC is enabled. + ''' + } + { + bits: "2", + name: "CLK_MAIN_KMAC_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_KMAC can be disabled. + 1 CLK_MAIN_KMAC is enabled. + ''' + } + { + bits: "3", + name: "CLK_MAIN_OTBN_HINT", + resval: 1, + desc: ''' + 0 CLK_MAIN_OTBN can be disabled. + 1 CLK_MAIN_OTBN is enabled. + ''' + } + ] + // the CLK_HINT register cannot be written. + // During top level randomized tests, it is possible to disable the clocks to transactional blocks + // and then access a register in the disabled block. This would lead to a top level hang. + tags: ["excl:CsrAllTests:CsrExclAll"] + }, + + { name: "CLK_HINTS_STATUS", + desc: ''' + Since the final state of !!CLK_HINTS is not always determined by software, + this register provides read feedback for the current clock state. + + ''', + swaccess: "ro", + hwaccess: "hwo", + fields: [ + { + bits: "0", + name: "CLK_MAIN_AES_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_AES is disabled. + 1 CLK_MAIN_AES is enabled. + ''' + } + { + bits: "1", + name: "CLK_MAIN_HMAC_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_HMAC is disabled. + 1 CLK_MAIN_HMAC is enabled. + ''' + } + { + bits: "2", + name: "CLK_MAIN_KMAC_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_KMAC is disabled. + 1 CLK_MAIN_KMAC is enabled. + ''' + } + { + bits: "3", + name: "CLK_MAIN_OTBN_VAL", + resval: 1, + desc: ''' + 0 CLK_MAIN_OTBN is disabled. + 1 CLK_MAIN_OTBN is enabled. + ''' + } + ] + // the CLK_HINT_STATUS register is read-only and cannot be checked. + // This register's value depends on the IDLE inputs, so cannot be predicted. + tags: ["excl:CsrNonInitTests:CsrExclCheck:CsrExclCheck"] + }, + + { name: "MEASURE_CTRL_REGWEN", + desc: "Measurement control write enable", + swaccess: "rw0c", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, the value of the measurement control can be set. When 0, writes have no + effect. + ''' + }, + ] + }, + { name: "IO_DIV4_MEAS_CTRL_EN", + desc: ''' + Enable for measurement control + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hrw", + async: "clk_io_div4_i", + fields: [ + { + bits: "3:0", + name: "EN", + desc: "Enable measurement for io_div4", + mubi: true, + resval: false, + }, + ] + // Measurements can cause recoverable errors depending on the + // thresholds which randomized CSR tests will not predict correctly. + // To provide better CSR coverage we allow writing the threshold + // fields, but not enabling the counters. + tags: ["excl:CsrAllTests:CsrExclWrite"] + }, + + { name: "IO_DIV4_MEAS_CTRL_SHADOWED", + desc: ''' + Configuration controls for io_div4 measurement. + + The threshold fields are made wider than required (by 1 bit) to ensure + there is room to adjust for measurement inaccuracies. + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hro", + async: "clk_io_div4_i", + shadowed: "true", + update_err_alert: "recov_fault", + storage_err_alert: "fatal_fault", + fields: [ + { + bits: "8:0", + name: "HI", + desc: "Max threshold for io_div4 measurement", + resval: "138" + }, + + { + bits: "17:9", + name: "LO", + desc: "Min threshold for io_div4 measurement", + resval: "118" + }, + ] + }, + { name: "MAIN_MEAS_CTRL_EN", + desc: ''' + Enable for measurement control + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hrw", + async: "clk_main_i", + fields: [ + { + bits: "3:0", + name: "EN", + desc: "Enable measurement for main", + mubi: true, + resval: false, + }, + ] + // Measurements can cause recoverable errors depending on the + // thresholds which randomized CSR tests will not predict correctly. + // To provide better CSR coverage we allow writing the threshold + // fields, but not enabling the counters. + tags: ["excl:CsrAllTests:CsrExclWrite"] + }, + + { name: "MAIN_MEAS_CTRL_SHADOWED", + desc: ''' + Configuration controls for main measurement. + + The threshold fields are made wider than required (by 1 bit) to ensure + there is room to adjust for measurement inaccuracies. + ''', + regwen: "MEASURE_CTRL_REGWEN", + swaccess: "rw", + hwaccess: "hro", + async: "clk_main_i", + shadowed: "true", + update_err_alert: "recov_fault", + storage_err_alert: "fatal_fault", + fields: [ + { + bits: "8:0", + name: "HI", + desc: "Max threshold for main measurement", + resval: "138" + }, + + { + bits: "17:9", + name: "LO", + desc: "Min threshold for main measurement", + resval: "118" + }, + ] + }, + + { name: "RECOV_ERR_CODE", + desc: "Recoverable Error code", + swaccess: "rw1c", + hwaccess: "hwo", + fields: [ + { bits: "0", + name: "SHADOW_UPDATE_ERR", + resval: 0 + desc: ''' + One of the shadow registers encountered an update error. + ''' + }, + { + bits: "1", + name: "IO_DIV4_MEASURE_ERR", + resval: 0, + desc: ''' + io_div4 has encountered a measurement error. + ''' + }, + { + bits: "2", + name: "MAIN_MEASURE_ERR", + resval: 0, + desc: ''' + main has encountered a measurement error. + ''' + }, + { + bits: "3", + name: "IO_DIV4_TIMEOUT_ERR", + resval: 0, + desc: ''' + io_div4 has timed out. + ''' + } + { + bits: "4", + name: "MAIN_TIMEOUT_ERR", + resval: 0, + desc: ''' + main has timed out. + ''' + } + ] + }, + + { name: "FATAL_ERR_CODE", + desc: "Error code", + swaccess: "ro", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "REG_INTG", + resval: 0 + desc: ''' + Register file has experienced a fatal integrity error. + ''' + }, + { bits: "1", + name: "IDLE_CNT", + resval: 0 + desc: ''' + One of the idle counts encountered a duplicate error. + ''' + }, + { bits: "2", + name: "SHADOW_STORAGE_ERR", + resval: 0 + desc: ''' + One of the shadow registers encountered a storage error. + ''' + }, + ] + }, + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr_sec_cm_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr_sec_cm_testplan.hjson new file mode 100644 index 00000000000..f9c12d7d8f4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr_sec_cm_testplan.hjson @@ -0,0 +1,190 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../clkmgr/data/clkmgr.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../clkmgr/data/clkmgr_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: '''Verify the countermeasure(s) BUS.INTEGRITY. + This entry is covered by tl_access_test. + ''' + stage: V2S + tests: ["clkmgr_tl_intg_err"] + } + { + name: sec_cm_meas_clk_bkgn_chk + desc: '''Verify the countermeasure(s) MEAS.CLK.BKGN_CHK. + - Test measurement feature of clkmgr_meas_chk modules. + For all test clocks (clk_main, clk_usb, clk_io, clk_io_div2 + and clk_io_div4), do measurement with normal configuration. + Then change either min or max threshold value to see + whether the module can detect measurement error for each test + clock. + - Measurement error should trigger a recoverable alert + ''' + stage: V2S + tests: ["clkmgr_frequency"] + } + { + name: sec_cm_timeout_clk_bkgn_chk + desc: '''Verify the countermeasure(s) TIMEOUT.CLK.BKGN_CHK. + - Test timeout feature of clkmgr_meas_chk modules. + While frequency measurement, one of + clk_main, clk_usb, clk_io, clk_io_div2 and clk_io_div4 are choose + and stopped. This will leads to timeout event. + - Timeout should cause a recoverable alert + ''' + stage: V2S + tests: ["clkmgr_frequency_timeout"] + } + { + name: sec_cm_meas_config_shadow + desc: ''' + Verify the countermeasure(s) MEAS.CONFIG.SHADOW. + + This is covered by shadow_reg_errors_tests + (https://github.com/lowRISC/opentitan/blob/master/ + hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson) + ''' + stage: V2S + tests: ["clkmgr_shadow_reg_errors"] + } + { + name: sec_cm_idle_intersig_mubi + desc: '''Verify the countermeasure(s) IDLE.INTERSIG.MUBI. + It uses true_strict and false_loose. + **Stimulus**: + Use same sequence as trans_enables test. + Randomize dut.idle_i ports with illegal values. + **Check**: + - hins_status check: + When clk_hints update from '1' to '0', + clk_hints_status has to wait idle becomes 'true'. So check + clk_hints_status with random idle value, then check again + after set all idle values to 'true'. + + - clock output check: + When clk_hints_status go to '0', check clocks_o + to see if clock is really off + ''' + stage: V2S + tests: ["clkmgr_idle_intersig_mubi"] + } + { + name: sec_cm_lc_ctrl_intersig_mubi + desc: '''Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI. + It compares to lc_ctrl_pkg::On only. + Use clkmgr_extclk test as in testplan.extclk but randomize + dut.lc_hw_debug_en_i s.t. all 16 values can be generated with equal priority. + + **Checks**: + When dut sees invalid values of lc_hw_debug_en_i, + all_clk_byp_req should not be asserted. Covered by assertion checker. + ''' + stage: V2S + tests: ["clkmgr_lc_ctrl_intersig_mubi"] + } + { + name: sec_cm_lc_ctrl_clk_handshake_intersig_mubi + desc: '''Verify the countermeasure(s) LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI. + It compared to lc_ctrl_pkg::On only. + Use clkmgr_extclk test but randomize lc_clk_byp_req s.t. + all 16 values can be generated with equal priority. + lc_clk_byp_req drives dut.lc_clk_byp_req_i in the test. + **Checks**: + When dut sees invalid values of lc_clk_byp_req_i, + io_clk_byp_req_o should not be asserted. Covered by assertion checker. + ''' + stage: V2S + tests: ["clkmgr_lc_clk_byp_req_intersig_mubi"] + } + { + name: sec_cm_clk_handshake_intersig_mubi + desc: '''Verify the countermeasure(s) CLK_HANDSHAKE.INTERSIG.MUBI. + It uses true_strict. + Use clkmgr_extclk test. Upon receiving [io|all]_clk_byp_req_o from dut, + assert invalid [io|all]_clk_byp_ack values to dut. + + **Check**: + all_clk_byp_ack is copied to CLKGMR.EXTCLK_STATUS as is. So read extclk + status and compare. + io_clk_byp_ack is evaluated with step_down_acks_syn. + When both are true, lc_clk_byp_req is assigned to lc_clk_byp_ack. + Covered by assertion checker. + ''' + stage: V2S + tests: ["clkmgr_clk_handshake_intersig_mubi"] + } + { + name: sec_cm_div_intersig_mubi + desc: '''Verify the countermeasure(s) DIV.INTERSIG.MUBI. + use true_strict. + Use clkmgr_extclk test. Before, test drive dut.div_step_down_req_i + with 'true', sends invalid values. + **Check**: + dut should ignore invalid req values. Covered by assertion checker. + ''' + stage: V2S + tests: ["clkmgr_div_intersig_mubi"] + } + { + name: sec_cm_jitter_config_mubi + desc: '''Verify the countermeasure(s) JITTER.CONFIG.MUBI. + use false_strict. + This doesn't do any function in the dut but indicating + jittery clock is enabled. So it can be covered by default + csr test. + ''' + stage: V2S + tests: ["clkmgr_csr_rw"] + } + { + name: sec_cm_idle_ctr_redun + desc: '''Verify the countermeasure(s) IDLE.CTR.REDUN. + This is triggered by common cm primitives (SecCmPrimCount). + **Check**: + read check CLKMGR.FATAL_ERR_CODE.IDLE_CNT == 1 + ''' + stage: V2S + tests: ["clkmgr_sec_cm"] + } + { + name: sec_cm_meas_config_regwen + desc: '''Verify the countermeasure(s) MEAS.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["clkmgr_csr_rw"] + } + { + name: sec_cm_clk_ctrl_config_regwen + desc: '''Verify the countermeasure(s) CLK_CTRL.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["clkmgr_csr_rw"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr_testplan.hjson new file mode 100644 index 00000000000..af05156616e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr_testplan.hjson @@ -0,0 +1,334 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "clkmgr" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson", + "clkmgr_sec_cm_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson"] + testpoints: [ + { + name: smoke + desc: ''' + Smoke test disabling peripheral and transactional clocks. + + - Disables all peripheral clocks from their enabled reset state. + - Transactional clocks gating depends on whether they are idle. + - Initializes all units as busy (not idle). + - Clears each unit's `clk_hints` bit, which has no effect until + the unit becomes idle. + - Sets the unit's `idle_i` bit, which should disable the clock. + - Writes both values of the `jitter_enable` CSR. + + **Stimulus**: + - CSR writes to `clk_enables` and `clk_hints`. + - Setting `idle_i` clkmgr input. + + **Checks**: + - SVA assertions for peripheral clocks enable and disable + properties. + - Transactional clocks check SVA properties as follows: + - If the hint enables it, the clock becomes active. + - If the hint disables it but the unit is busy, the clock remains + active. + - If the hint disables it and the unit is idle, the clock stops. + - For transactional units the CSR `clk_hints_status` is checked + to correspond to `clk_hints` once the units are idle. + - Check in scoreboard the `jitter_en_o` output tracks updates of the + `jitter_enable` CSR. + ''' + stage: V1 + tests: ["clkmgr_smoke"] + } + { + name: peri_enables + desc: ''' + Peripheral clocks are disabled if its `clk_enables` bit is off, + or the corresponding `pwr_i.*_ip_clk_en` is off, and `scanmode_i` + is not `lc_ctrl_pkg::On`. + + This test runs multiple rounds which do the following: + - Randomize `pwr_i.usb_ip_clk_en` and `scanmode_i`, and the initial + setting of `clk_enables`. + - Send a CSR write to `clk_enables` with its initial value. + - Send a CSR write to `clk_enables` that flips all bits. + + It makes no sense to have `pwr_i.io_ip_clk_en` set to zero since + that would prevent the CPU from running and sending CSR updates. + + **Checks**: + - SVA assertions for peripheral clocks enable and disable + properties. + ''' + stage: V2 + tests: ["clkmgr_peri"] + } + { + name: trans_enables + desc: ''' + Transactional unit clocks are disabled if they are idle and + their CSR `clk_hints` bit is off, or `pwr_i.main_ip_clk_en` is off, + and `scanmode_i` is not `lc_ctrl_pkg::On`. + This test randomizes the initial setting of `idle_i` and the + desired value of `clk_hints`. Each round performs this sequence: + - Writes the desired value to CSR `clk_hints` and checks that the + CSR `clk_hints_status` reflects CSR `clk_hints` except for the + units not-idle. + - Marks all units as idle, and checks that `csr_hints_status` + matches `clk_hints`. + - Writes `clk_hints` to all ones and checks that `csr_hints_status` + is all ones. + - Writes `clk_hints` with its reset value. + + **Checks**: + - SVA assertions for transactional unit clocks described in + clkmgr_smoke. + ''' + stage: V2 + tests: ["clkmgr_trans"] + } + { + name: extclk + desc: ''' + Tests the functionality of enabling external clocks. + + - External clock is enabled if the `lc_clk_byp_req_i` input from + `lc_ctrl` is `lc_ctrl_pkg::On`. + - External clock is also be enabled when CSR `extclk_ctrl.sel` is + set to + `lc_ctrl_pkg::On` and the `lc_dtl_en_i` input from `lc_ctrl` is + `lc_ctrl_pkg::On`. + - Notice writes to the `extclk_ctrl.sel` register are ignored unless + the CSR `extclk_ctrl_regwen` is 1. + - A successful switch to external clocks due to `lc_clk_byl_req_i` + will cause the clkmgr to undo a divide by 2 for io_div4 and + io_div2 clocks except when `(scanmode_i == prim_mubi_pkg::MuBi4True)`. + - A software triggered switch to external clock will undo divides + by 2 if `extclk_ctrl.hi_speed_sel` is set to `prim_mubi_pkg::MuBi4True`. + + **Stimulus**: + - CSR writes to `extclk_ctrl` and `extclk_ctrl_regwen`. + - Setting `lc_hw_debug_en_i`, `lc_clk_byp_req_i`, and the handshake to + ast via `ast_clk_byp_req_o` and `ast_clk_byp_ack_i`. + - Setting `scanmode_i`. + + **Checks**: + Clock divider checks are done with SVA assertions. + - When the external clock is selected (and not defeated by + `scanmode_i` for scoreboard checks): + - The `clk_io_div2_powerup` output matches the `clk_io_powerup` + output. + - The `clk_io_div4_powerup` output matches the `clk_io_powerup` + output at half its frequency. + - When the external clock is not selected or division is defeated: + - The `clk_io_div2_powerup` output matches the `clk_io_powerup` + output at half its frequency. + - The `clk_io_div4_powerup` output matches the `clk_io_powerup` + output at a quarter of its frequency. + LC / AST handshake: + - When the external clock functionality is triggered the + `ast_clk_byp_req_o` output pin is set to `lc_ctrl_pkg::On`. + - When `ast_clk_byp_ack_i` is set to `lc_ctrl_pkg::On` in response + to a corresponding request: + - The clock dividers are stepped down, unless defeated by + `scanmode_i` being `lc_ctrl_pkg::On`. + - If the initial request was due to the assertion of the + `lc_clk_byp_req_i`, the `lc_clk_byp_ack_o` output is set to + `lc_ctrl_pkg::On`. + ''' + stage: V2 + tests: ["clkmgr_extclk"] + } + { + name: clk_status + desc: ''' + This tests the three `pwr_o.*_status` output ports, for the + `io`, `main`, and `usb` clocks. + + The `pwr_o.*_status` output must track the correspponding + `pwr_i.*_ip_clk_en` input. + + **Stimulus**: + - Randomize the `pwr_i.*_ip_clk_en` setting for each clock. + + **Check**: + - The checks are done in SVA at `clkmgr_pwrmgr_sva_if.sv`. + ''' + stage: V2 + tests: ["clkmgr_clk_status"] + } + { + name: jitter + desc: ''' + This tests the jitter functionality. + + The jitter functionality is implemented by the AST block, but + controlled by the `jitter_enable` CSR in this block. This CSR + directly drives the `jitter_en_o` output pin. + + **Stimulus**: + - CSR write to `jitter_enable`. + + **Check**: + - The `jitter_en_o` output pin reflects the `jitter_enable` CSR. + Test is implemented in the scoreboard, and is always running. + ''' + stage: V2 + tests: ["clkmgr_smoke"] + } + { + name: frequency + desc: '''This tests the frequency counters measured count functionality. + + These counters compute the number of cycles of each clock relative + to the aon timer, and compares it to the corresponding + thresholds written into the `*_meas_ctrl_shadowed` CSR. Measurements + beyond these thresholds trigger a recoverable alert and set a bit + in the `recov_err_code` CSR. Also, if the counters reach their + maximum value they don't wrap around. + + If clock calibration is lost, indicated by the `calib_rdy_i` input + being `prim_mubi_pkg::MuBi4False`, the measurements stop, no + error is triggered, and `measure_ctrl_regwen` is set to 1. + + **Stimulus**: + - Randomly set slow, correct, and fast interval for each counter + and test. + - Randomly set the `calib_rdy_i` input. + - Randomly trigger a clock saturation by forcing its cycle count + to be near its maximum value while counting. + + **Check**: + - Slow and fast intervals should cause a recoverable alert. + - Coverage collected per clock. + ''' + stage: V2 + tests: ["clkmgr_frequency"] + } + { + name: frequency_timeout + desc: '''This tests the frequency counters timeout functionality. + + These counters compute the number of cycles of some clock relative + to the aon timer. It should trigger a recoverable alert when there + is no valid measurement when enabled, leading to a timeout. This is + separate from the `frequenty` testpoint to simplify the test checks. + + **Stimulus**: + - Randomly stop measured clocks to trigger a timeout. + + **Check**: + - Timeout should cause a recoverable alert. + - Coverage collected per clock. + ''' + stage: V2 + tests: ["clkmgr_frequency_timeout"] + } + { + name: frequency_overflow + desc: '''This tests the overflow feature in prim_clock_meas. + + This needs to modify the state of the counter to trigger the + feature. + + **Stimulus**: + - Program the counter. Whenever it hits the value of 1, set it to + the range - 2. + + **Check**: + - The internal cnt_ovfl flop is set. + - The fast_o output should be set. + ''' + stage: V2 + tests: ["clkmgr_frequency"] + } + { + name: regwen + desc: '''This tests the behavior of the regwen CSRs. + + When a regwen is clear, any write to CSRs it locks are ignored. + Once a regwen is cleared, it will only be set again after a full + reset. + + **Stimulus**: + - Clear each regwen. + - Write to the corresponding locked CSRs. + + **Check**: + - The locked CSR value is not updated. + ''' + stage: V3 + tests: ["clkmgr_regwen"] + } + { + name: stress_all + desc: '''This runs random sequences in succession. + + Randomly chooses from the following sequences: + - clkmgr_extclk_vseq, + - clkmgr_frequency_timeout_vseq, + - clkmgr_frequency_vseq, + - clkmgr_peri_vseq, + - clkmgr_smoke_vseq, + - clkmgr_trans_vseq + ''' + stage: V2 + tests: ["clkmgr_stress_all"] + } + ] + + covergroups: [ + { + name: peri_cg + desc: ''' + Collects coverage for each peripheral clock. + + The peripheral clocks depend on a bit in the clk_enables CSR, + the ip_clk_en input from pwrmgr, and the scanmode input. + This collects the cross of them for each peripheral. + + FIXME This is collected in an array, one instance for each clock, + but the dvsim coverage flow doesn't yet support arrays. + ''' + } + { + name: trans_cg + desc: ''' + Collects coverage for each transactional unit clock. + + The transactional unit clocks depend on a bit in the clk_hints CSR, + the ip_clk_en input from pwrmgr, the respective idle input bit from + the unit, and the scanmode input. + This collects the cross of them for each transactional unit. + + FIXME This is collected in an array, one instance for each clock, + but the dvsim coverage flow doesn't yet support arrays. + ''' + } + { + name: extclk_cg + desc: ''' + Collects coverage for the external clock selection. + + The external clock selection depends on the `extclk_ctrl` CSR + fields `sel` and `hi_speed_sel`, and the `lc_hw_debug_en_i`, + `lc_clk_byp_req_i`, and `scanmode_i` input pins. This covergroup + collects their cross. + ''' + } + { + name: freq_measure_cg + desc: ''' + Collects coverage for the frequency measurement counters. + + The relevant information is whether it got an okay, slow, or + fast measurement, or a timeout. + ''' + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/top_darjeeling_no_ibex_clkmgr.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/top_darjeeling_no_ibex_clkmgr.ipconfig.hjson new file mode 100644 index 00000000000..357895f2359 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/top_darjeeling_no_ibex_clkmgr.ipconfig.hjson @@ -0,0 +1,220 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_clkmgr + param_values: + { + src_clks: + { + main: + { + name: main + aon: false + freq: 1000000000 + ref: false + } + io: + { + name: io + aon: false + freq: 1000000000 + ref: false + } + aon: + { + name: aon + aon: true + freq: 62500000 + ref: true + } + } + derived_clks: + { + io_div2: + { + name: io_div2 + aon: false + freq: 500000000 + ref: false + div: 2 + src: + { + name: io + aon: no + freq: "1000000000" + ref: false + } + } + io_div4: + { + name: io_div4 + aon: false + freq: 250000000 + ref: false + div: 4 + src: + { + name: io + aon: no + freq: "1000000000" + ref: false + } + } + } + typed_clocks: + { + ast_clks: + { + clk_main_i: + { + src_name: main + endpoint_ip: clkmgr_aon + } + clk_io_i: + { + src_name: io + endpoint_ip: clkmgr_aon + } + clk_aon_i: + { + src_name: aon + endpoint_ip: clkmgr_aon + } + } + ft_clks: + { + clk_io_div4_powerup: + { + src_name: io_div4 + endpoint_ip: pwrmgr_aon + } + clk_aon_powerup: + { + src_name: aon + endpoint_ip: pwrmgr_aon + } + clk_main_powerup: + { + src_name: main + endpoint_ip: rstmgr_aon + } + clk_io_powerup: + { + src_name: io + endpoint_ip: rstmgr_aon + } + clk_io_div2_powerup: + { + src_name: io_div2 + endpoint_ip: rstmgr_aon + } + clk_aon_infra: + { + src_name: aon + endpoint_ip: soc_proxy + } + clk_aon_peri: + { + src_name: aon + endpoint_ip: ast + } + clk_aon_timers: + { + src_name: aon + endpoint_ip: aon_timer_aon + } + } + rg_clks: + { + clk_io_div4_infra: + { + src_name: io_div4 + endpoint_ip: ast + } + clk_main_infra: + { + src_name: main + endpoint_ip: soc_proxy + } + clk_io_div4_secure: + { + src_name: io_div4 + endpoint_ip: otp_ctrl + } + clk_main_secure: + { + src_name: main + endpoint_ip: otp_ctrl + } + clk_io_div4_timers: + { + src_name: io_div4 + endpoint_ip: aon_timer_aon + } + } + sw_clks: + { + clk_io_div4_peri: + { + src_name: io_div4 + endpoint_ip: uart0 + } + clk_io_div2_peri: + { + src_name: io_div2 + endpoint_ip: spi_device + } + } + hint_clks: + { + clk_main_aes: + { + src_name: main + endpoint_ip: aes + } + clk_main_hmac: + { + src_name: main + endpoint_ip: hmac + } + clk_main_kmac: + { + src_name: main + endpoint_ip: kmac + } + clk_main_otbn: + { + src_name: main + endpoint_ip: otbn + } + } + } + hint_names: + { + clk_main_aes: HintMainAes + clk_main_hmac: HintMainHmac + clk_main_kmac: HintMainKmac + clk_main_otbn: HintMainOtbn + } + parent_child_clks: + { + main: + [ + main + ] + io: + [ + io + io_div2 + io_div4 + ] + } + exported_clks: {} + number_of_clock_groups: 7 + with_alert_handler: true + topname: darjeeling_no_ibex + uniquified_modules: {} + module_instance_name: clkmgr + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/defs.bzl new file mode 100644 index 00000000000..33406d055d1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/defs.bzl @@ -0,0 +1,11 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +CLKMGR = opentitan_ip( + name = "clkmgr", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data:clkmgr.hjson", + ipconfig = "//hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data:top_darjeeling_no_ibex_clkmgr.ipconfig.hjson", + extension = "//hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util:dt", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/checklist.md b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/checklist.md new file mode 100644 index 00000000000..28ac5395584 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/checklist.md @@ -0,0 +1,271 @@ +# CLKMGR Checklist + + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [CLKMGR peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [CLKMGR Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | NA | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | With waivers approved by TC on 2024-08-08 +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Done | +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | matutem@, vogelpi@, adk@ +Review | Signoff date | Done | 2024-08-08 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [CLKMGR DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | [CLKMGR Testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | NA | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | NA | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | xcelium +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | NA | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | NA | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | NA | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | NA | +Tests | [SIM_FW_SIMULATED][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | NA | +Coverage | [FPV_COI_COVERAGE_V2][] | NA | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | NA | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_VERIFIED][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/clkmgr_block_diagram.svg b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/clkmgr_block_diagram.svg new file mode 100644 index 00000000000..b3977b5124c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/clkmgr_block_diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/clkmgr_rst_domain.svg b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/clkmgr_rst_domain.svg new file mode 100644 index 00000000000..2e5276cc7c2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/clkmgr_rst_domain.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/example_chip_partition.svg b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/example_chip_partition.svg new file mode 100644 index 00000000000..2c8bc65081b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/example_chip_partition.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/interfaces.md b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/interfaces.md new file mode 100644 index 00000000000..966952eacc5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/interfaces.md @@ -0,0 +1,59 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`clkmgr`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_main_i`**, **`clk_io_i`**, **`clk_aon_i`**, **`clk_io_div2_i`**, **`clk_io_div4_i`** +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* +- Interrupts: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:------------------|:-------------------------|:--------|:------|--------:|:---------------------------------------------------------| +| clocks | clkmgr_pkg::clkmgr_out | uni | req | 1 | | +| cg_en | clkmgr_pkg::clkmgr_cg_en | uni | req | 1 | | +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| io_clk_byp_req | prim_mubi_pkg::mubi4 | uni | req | 1 | | +| io_clk_byp_ack | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| all_clk_byp_req | prim_mubi_pkg::mubi4 | uni | req | 1 | | +| all_clk_byp_ack | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| hi_speed_sel | prim_mubi_pkg::mubi4 | uni | req | 1 | | +| div_step_down_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| lc_clk_byp_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_clk_byp_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | | +| jitter_en | prim_mubi_pkg::mubi4 | uni | req | 1 | | +| pwr | pwr_clk | req_rsp | rsp | 1 | | +| idle | prim_mubi_pkg::mubi4 | uni | rcv | 4 | | +| calib_rdy | prim_mubi_pkg::mubi4 | uni | rcv | 1 | Indicates clocks are calibrated and frequencies accurate | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Security Alerts + +| Alert Name | Description | +|:-------------|:----------------------------------------------------------------------------------| +| recov_fault | This recoverable alert is triggered when there are measurement errors. | +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:-------------------------------------------|:-------------------------------------------------------------| +| CLKMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| CLKMGR.TIMEOUT.CLK.BKGN_CHK | Background check for clock timeout. | +| CLKMGR.MEAS.CLK.BKGN_CHK | Background check for clock frequency. | +| CLKMGR.MEAS.CONFIG.SHADOW | Measurement configurations are shadowed. | +| CLKMGR.IDLE.INTERSIG.MUBI | Idle inputs are multibit encoded. | +| CLKMGR.LC_CTRL.INTERSIG.MUBI | The life cycle control signals are multibit encoded. | +| CLKMGR.LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI | The life cycle clock req/ack signals are multibit encoded. | +| CLKMGR.CLK_HANDSHAKE.INTERSIG.MUBI | The external clock req/ack signals are multibit encoded. | +| CLKMGR.DIV.INTERSIG.MUBI | Divider step down request is multibit encoded. | +| CLKMGR.JITTER.CONFIG.MUBI | The jitter enable configuration is multibit encoded. | +| CLKMGR.IDLE.CTR.REDUN | Idle counter is duplicated. | +| CLKMGR.MEAS.CONFIG.REGWEN | The measurement controls protected with regwen. | +| CLKMGR.CLK_CTRL.CONFIG.REGWEN | Software controlled clock requests are proteced with regwen. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/programmers_guide.md b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/programmers_guide.md new file mode 100644 index 00000000000..eea3386a2e2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/programmers_guide.md @@ -0,0 +1,17 @@ +# Programmer's Guide + +There are in general only two software controllable functions in the clock manager. + + +## Transactional Clock Hints + +To enable a transactional clock, set the corresponding hint in [`CLK_HINTS`](registers.md#clk_hints) to `1`. +To disable a transactional clock, set the corresponding hint in [`CLK_HINTS`](registers.md#clk_hints) to `0`. +Note, a `0` does not indicate clock is actually disabled, software can thus check [`CLK_HINTS_STATUS`](registers.md#clk_hints_status) for the actual state of the clock. + +## Peripheral Clock Controls +To control peripheral clocks, directly change the bits in [`CLK_ENABLES`](registers.md#clk_enables). + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_clkmgr.h) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/registers.md b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/registers.md new file mode 100644 index 00000000000..855d009ae97 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/registers.md @@ -0,0 +1,377 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:-------------------------------------------------------------------|:---------|---------:|:-----------------------------------------------------------------------------------------| +| clkmgr.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| clkmgr.[`EXTCLK_CTRL_REGWEN`](#extclk_ctrl_regwen) | 0x4 | 4 | External clock control write enable | +| clkmgr.[`EXTCLK_CTRL`](#extclk_ctrl) | 0x8 | 4 | Select external clock | +| clkmgr.[`EXTCLK_STATUS`](#extclk_status) | 0xc | 4 | Status of requested external clock switch | +| clkmgr.[`JITTER_REGWEN`](#jitter_regwen) | 0x10 | 4 | Jitter write enable | +| clkmgr.[`JITTER_ENABLE`](#jitter_enable) | 0x14 | 4 | Enable jittery clock | +| clkmgr.[`CLK_ENABLES`](#clk_enables) | 0x18 | 4 | Clock enable for software gateable clocks. | +| clkmgr.[`CLK_HINTS`](#clk_hints) | 0x1c | 4 | Clock hint for software gateable transactional clocks during active mode. | +| clkmgr.[`CLK_HINTS_STATUS`](#clk_hints_status) | 0x20 | 4 | Since the final state of [`CLK_HINTS`](#clk_hints) is not always determined by software, | +| clkmgr.[`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) | 0x24 | 4 | Measurement control write enable | +| clkmgr.[`IO_DIV4_MEAS_CTRL_EN`](#io_div4_meas_ctrl_en) | 0x28 | 4 | Enable for measurement control | +| clkmgr.[`IO_DIV4_MEAS_CTRL_SHADOWED`](#io_div4_meas_ctrl_shadowed) | 0x2c | 4 | Configuration controls for io_div4 measurement. | +| clkmgr.[`MAIN_MEAS_CTRL_EN`](#main_meas_ctrl_en) | 0x30 | 4 | Enable for measurement control | +| clkmgr.[`MAIN_MEAS_CTRL_SHADOWED`](#main_meas_ctrl_shadowed) | 0x34 | 4 | Configuration controls for main measurement. | +| clkmgr.[`RECOV_ERR_CODE`](#recov_err_code) | 0x38 | 4 | Recoverable Error code | +| clkmgr.[`FATAL_ERR_CODE`](#fatal_err_code) | 0x3c | 4 | Error code | + +## ALERT_TEST +Alert Test Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "recov_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:-------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | +| 0 | wo | 0x0 | recov_fault | Write 1 to trigger one alert event of this kind. | + +## EXTCLK_CTRL_REGWEN +External clock control write enable +- Offset: `0x4` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, the value of [`EXTCLK_CTRL`](#extclk_ctrl) can be set. When 0, writes to [`EXTCLK_CTRL`](#extclk_ctrl) have no effect. | + +## EXTCLK_CTRL +Select external clock +- Offset: `0x8` +- Reset default: `0x99` +- Reset mask: `0xff` +- Register enable: [`EXTCLK_CTRL_REGWEN`](#extclk_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "SEL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "HI_SPEED_SEL", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-------------------------------------------| +| 31:8 | | | Reserved | +| 7:4 | rw | 0x9 | [HI_SPEED_SEL](#extclk_ctrl--hi_speed_sel) | +| 3:0 | rw | 0x9 | [SEL](#extclk_ctrl--sel) | + +### EXTCLK_CTRL . HI_SPEED_SEL +A value of kMultiBitBool4True selects nominal speed external clock. +All other values selects low speed clocks. + +Note this field only has an effect when the [`EXTCLK_CTRL.SEL`](#extclk_ctrl) field is set to +kMultiBitBool4True. + +Nominal speed means the external clock is approximately the same frequency as +the internal oscillator source. When this option is used, all clocks operate +at roughly the nominal frequency. + +Low speed means the external clock is approximately half the frequency of the +internal oscillator source. When this option is used, the internal dividers are +stepped down. As a result, previously undivided clocks now run at half frequency, +while previously divided clocks run at roughly the nominal frequency. + +See external clock switch support in documentation for more details. + +### EXTCLK_CTRL . SEL +When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True +selects external clock as clock for the system. Writing any other value has +no impact. + +When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False +selects internal clock as clock for the system. Writing any other value during this stage +has no impact. + +While this register can always be programmed, it only takes effect when debug functions are enabled +in life cycle TEST, DEV or RMA states. + +## EXTCLK_STATUS +Status of requested external clock switch +- Offset: `0xc` +- Reset default: `0x9` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "ACK", "bits": 4, "attr": ["ro"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:---------------------------| +| 31:4 | | | Reserved | +| 3:0 | ro | 0x9 | [ACK](#extclk_status--ack) | + +### EXTCLK_STATUS . ACK +When [`EXTCLK_CTRL.SEL`](#extclk_ctrl) is set to kMultiBitBool4True, this field reflects +whether the clock has been switched the external source. + +kMultiBitBool4True indicates the switch is complete. +kMultiBitBool4False indicates the switch is either not possible or still ongoing. + +## JITTER_REGWEN +Jitter write enable +- Offset: `0x10` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, the value of [`JITTER_ENABLE`](#jitter_enable) can be changed. When 0, writes have no effect. | + +## JITTER_ENABLE +Enable jittery clock +- Offset: `0x14` +- Reset default: `0x9` +- Reset mask: `0xf` +- Register enable: [`JITTER_REGWEN`](#jitter_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x9 | VAL | Enable jittery clock. A value of kMultiBitBool4False disables the jittery clock, while all other values enable jittery clock. | + +## CLK_ENABLES +Clock enable for software gateable clocks. +These clocks are directly controlled by software. +- Offset: `0x18` +- Reset default: `0x3` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "CLK_IO_DIV4_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_IO_DIV2_PERI_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:---------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw | 0x1 | CLK_IO_DIV2_PERI_EN | 0 CLK_IO_DIV2_PERI is disabled. 1 CLK_IO_DIV2_PERI is enabled. | +| 0 | rw | 0x1 | CLK_IO_DIV4_PERI_EN | 0 CLK_IO_DIV4_PERI is disabled. 1 CLK_IO_DIV4_PERI is enabled. | + +## CLK_HINTS +Clock hint for software gateable transactional clocks during active mode. +During low power mode, all clocks are gated off regardless of the software hint. + +Transactional clocks are not fully controlled by software. Instead software provides only a disable hint. + +When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. +If the hardware block is idle, then the clock is disabled. +If the hardware block is not idle, the clock is kept on. + +For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any +feedback in this case. +- Offset: `0x1c` +- Reset default: `0xf` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "CLK_MAIN_AES_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------|:-------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3 | rw | 0x1 | CLK_MAIN_OTBN_HINT | 0 CLK_MAIN_OTBN can be disabled. 1 CLK_MAIN_OTBN is enabled. | +| 2 | rw | 0x1 | CLK_MAIN_KMAC_HINT | 0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled. | +| 1 | rw | 0x1 | CLK_MAIN_HMAC_HINT | 0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled. | +| 0 | rw | 0x1 | CLK_MAIN_AES_HINT | 0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled. | + +## CLK_HINTS_STATUS +Since the final state of [`CLK_HINTS`](#clk_hints) is not always determined by software, +this register provides read feedback for the current clock state. + +- Offset: `0x20` +- Reset default: `0xf` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "CLK_MAIN_AES_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_HMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_KMAC_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CLK_MAIN_OTBN_VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------|:---------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3 | ro | 0x1 | CLK_MAIN_OTBN_VAL | 0 CLK_MAIN_OTBN is disabled. 1 CLK_MAIN_OTBN is enabled. | +| 2 | ro | 0x1 | CLK_MAIN_KMAC_VAL | 0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled. | +| 1 | ro | 0x1 | CLK_MAIN_HMAC_VAL | 0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled. | +| 0 | ro | 0x1 | CLK_MAIN_AES_VAL | 0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled. | + +## MEASURE_CTRL_REGWEN +Measurement control write enable +- Offset: `0x24` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, the value of the measurement control can be set. When 0, writes have no effect. | + +## IO_DIV4_MEAS_CTRL_EN +Enable for measurement control +- Offset: `0x28` +- Reset default: `0x9` +- Reset mask: `0xf` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x9 | EN | Enable measurement for io_div4 | + +## IO_DIV4_MEAS_CTRL_SHADOWED +Configuration controls for io_div4 measurement. + +The threshold fields are made wider than required (by 1 bit) to ensure +there is room to adjust for measurement inaccuracies. +- Offset: `0x2c` +- Reset default: `0xec8a` +- Reset mask: `0x3ffff` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "HI", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------| +| 31:18 | | | | Reserved | +| 17:9 | rw | 0x76 | LO | Min threshold for io_div4 measurement | +| 8:0 | rw | 0x8a | HI | Max threshold for io_div4 measurement | + +## MAIN_MEAS_CTRL_EN +Enable for measurement control +- Offset: `0x30` +- Reset default: `0x9` +- Reset mask: `0xf` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x9 | EN | Enable measurement for main | + +## MAIN_MEAS_CTRL_SHADOWED +Configuration controls for main measurement. + +The threshold fields are made wider than required (by 1 bit) to ensure +there is room to adjust for measurement inaccuracies. +- Offset: `0x34` +- Reset default: `0xec8a` +- Reset mask: `0x3ffff` +- Register enable: [`MEASURE_CTRL_REGWEN`](#measure_ctrl_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "HI", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "LO", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 14}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------| +| 31:18 | | | | Reserved | +| 17:9 | rw | 0x76 | LO | Min threshold for main measurement | +| 8:0 | rw | 0x8a | HI | Max threshold for main measurement | + +## RECOV_ERR_CODE +Recoverable Error code +- Offset: `0x38` +- Reset default: `0x0` +- Reset mask: `0x1f` + +### Fields + +```wavejson +{"reg": [{"name": "SHADOW_UPDATE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV4_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_MEASURE_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "IO_DIV4_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "MAIN_TIMEOUT_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:---------------------------------------------------------| +| 31:5 | | | | Reserved | +| 4 | rw1c | 0x0 | MAIN_TIMEOUT_ERR | main has timed out. | +| 3 | rw1c | 0x0 | IO_DIV4_TIMEOUT_ERR | io_div4 has timed out. | +| 2 | rw1c | 0x0 | MAIN_MEASURE_ERR | main has encountered a measurement error. | +| 1 | rw1c | 0x0 | IO_DIV4_MEASURE_ERR | io_div4 has encountered a measurement error. | +| 0 | rw1c | 0x0 | SHADOW_UPDATE_ERR | One of the shadow registers encountered an update error. | + +## FATAL_ERR_CODE +Error code +- Offset: `0x3c` +- Reset default: `0x0` +- Reset mask: `0x7` + +### Fields + +```wavejson +{"reg": [{"name": "REG_INTG", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "IDLE_CNT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SHADOW_STORAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------|:---------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2 | ro | 0x0 | SHADOW_STORAGE_ERR | One of the shadow registers encountered a storage error. | +| 1 | ro | 0x0 | IDLE_CNT | One of the idle counts encountered a duplicate error. | +| 0 | ro | 0x0 | REG_INTG | Register file has experienced a fatal integrity error. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/theory_of_operation.md b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/theory_of_operation.md new file mode 100644 index 00000000000..93101dde835 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/doc/theory_of_operation.md @@ -0,0 +1,298 @@ +# Theory of Operation + +Clock management in OpenTitan is divided into groups. +Each group has specific attributes and controls whether software is allowed to influence individual clocks during the active power state. +For low power states, please see [power manager](../../pwrmgr/README.md). + +The grouping is derived from the chip partition and related security properties. +For illustrative purposes, this document uses the following assumed chip partition + +![Example chip partition](example_chip_partition.svg) + +The actual partition may differ per design, however the general principles are assumed to be the same. +Each group can be made up of more than 1 source clock. +The clocks themselves may be asynchronous - the grouping is thus a logical grouping instead of a physical one. + +The grouping is summarized in the table below and described in more detail afterwards. +The table shows the group name, the modules that belong to each group, and whether SW can directly (via register control) or indirectly (via wait-for-interrupt) influence the state of the clock in the form of clock gating. + +| Group | Frequencies | Modules | Software | Wait for Interrupt | +| ------------- | ------------------------------ | -------------------------------------------------------------- | -------------- | ------------------ | +| Power-up | 100~200KHz, 24MHz | Clock Manager, Power Manager, Reset Manager, Pinmux | No | No | +| Transactional | ~100MHz | Aes, Kmac, Hmac, Key Manager, Otbn | Yes (1) | Yes (2) | +| Infrastructural | 24MHz, ~100MHz | Fabric, Fabric gaskets (iopmp), Memories | No | Yes (3) | +| Security | 24MHz, ~100MHz | Alert handler, Entropy, Life cycle, Plic, Sensors | No | No | +| Peripheral | 24MHz, 48MHz, 96MHz | I2c, Spi, Uart, Usb, others | Yes | Yes | +| Timers | 100-200KHz, 24MHz | AON timers, Timers, Watchdog | No | No | + +* 1 - Transactional clock group's software control is only a software hint. +* 2 - Transactional clock group's wait-for-interrupt control is only a hint. +* 3 - May require additional complexity to handle multi-host (non-wait-for-interrupt) scenarios + +## Power-up Clock Group + +The group refers to modules responsible for power up, such as power, reset and clock managers. +Large portions of these modules operate to release clocks and resets for the rest of the design, thus cannot operate on gated versions of the clocks themselves. +They are the only group running clocks directly from the source. +All follow groups are derived after root clock gating. +See [block diagram](#block-diagram) for more details. + +## Transactional Clock Group + +This group refers to the collection of modules that are transactional by nature (example: `Hmac` / `Aes` / `Kmac`). +This means these modules perform specific tasks (for example encrypt, decrypt or hashing). +While performing these tasks, it is unsafe to manipulate or change the clocks. +Once these tasks are complete, the clocks can be safely shut-off. + +To ensure such behavior on the clocks, The final clock enable is qualified with an `Idle` indication to signify that a transaction is ongoing and manipulation of the clock is not permitted. +The `Idle` signal must be sourced from the transactional modules and sent to the clock manager. + +For this group software can only express its intent to shut-off, and does not have full control over the final state. +This intent is indicated with a register in the clock manager register file, see [`CLK_HINTS`](registers.md#clk_hints). + +Even when the hint is set, the `Idle` does not directly manipulate the clock. +When an idle indication is received, the `clkmgr` counts for a period of 10 local clocks to ensure the idle was not a glitch. + +Wait-for-interrupt based control is already a software hint, it can thus be applied to this group with the same `Idle` requirement. + +For modules in this group, each module can be individually influenced, and thus each has its own dedicated clock gating logic. +The added benefit of allowing software control in this group is to save power, as some transactional modules can be both power and area hungry. + +## Infrastructure Clock Group + +This group refers to the collection of modules that support infrastructure functions. + +If the clocks to these modules are turned off, there may not be a way to turn them back on and could thus result in system deadlock. +This includes but is not limited to: +* Turning off fabric / gasket clocks, and thus having no way to access the fabric and resume the clock. +* Turning off memory clocks such that there is no way to execute code that would resume the clocks. + +For this group, there is no reason to allow software control over the clocks, as it could be used to create a system deadlock where after disabling infrastructure clocks there is no way to turn them back on. +Wait-for-interrupt controls however can be used, as long as there is a way to break the processor out of wait-for-interrupt and handle other bus hosts, while also separating the functional portions from bus access. +See Wait-for-interrupt clock gating for more details. + +## Security Clock Group + +The security clock group is made up of security modules that either have background functions (entropy, alert manager, sensors) or perform critical security functions where disabling clocks could have unexpected side effects (life cycle, otp, pinmux, plic). + +For this group, no software influence over the clock state is allowed during the active state. +The clocks are always running as long as the source is on. + +This group is not functionally identical to the power-up group. +The power-up group is run on clocks directly from the clock source, while the security group is derived after root clock gating. + +## Timer Clock Group + +The timer clock group is composed of modules that track time for various purposes. +As influencing time can change the perspective of software and potentially reveal security vulnerabilities, the clock state for these modules cannot be directly or indirectly influenced by software. + +Functionally, this group is identical to the security group. + +## Peripheral Clock Group + +The peripheral clock group is composed of I/O peripherals modules. +By their nature, I/O peripherals are both transactional and most of the time not security critical - so long as proper care is taken to sandbox peripherals from the system. + +These modules can be both directly and indirectly controlled by software. +The controls can also be individual to each peripheral. + +## Wait-for-Interrupt (wfi) Gating + +Wait-for-interrupt clock gating refers to the mechanism of using a processor's sleep indication to actively gate off module clocks. +Of the groups enumerated, only transactional, infrastructural and peripheral groups can be influenced by `wfi`. + +As `wfi` is effectively a processor clock request, there are subtleties related to its use. +The interaction with each clock group is briefly described below. + +### Transactional Clock Group + +While `wfi` gating can be applied to this group, the modules in this category are already expected to be turned off and on by software depending on usage. +Specifically, these modules are already completely managed by software when not in use, thus may not see significant benefit from `wfi` gating. + +### Peripheral Clock Group + +Since peripherals, especially those in device mode, are often operated in an interrupt driven way, the peripheral's core operating clock frequently must stay alive even if the processor is asleep. +This implies that in order for peripherals to completely support `wfi` clock gating, they must be split between functional clocks and bus clocks. + +The bus clocks represent the software interface and can be turned off based on `wfi gating`, while the functional clocks should be kept running to ensure outside activity can be captured and interrupts created. +In this scenario, it is important to ensure the functional clocks are responsible for creating interrupts and not the bus clocks, as the latter may not be available during `wfi`. + +This division may only be beneficial for peripherals where register and local fabric size is large relative to the functional component. + +### Infrastructural Clock Group + +This clock group matches `wfi` functionality well. +Most infrastructural components such as fabric, gaskets and memories, have no need to be clocked when the processor is idle. +Some components such as flash controller however would also need to be split into bus and functional halves to support long, background activities while the processor is idle. + +However, there are additional complications. +In systems where the processor is not the only bus host, `wfi` can only be used as the software request and not final clock state decision. +Hardware driven requests, such as those coming from a `dma` or any peripheral driven bus host, would also need to be included as part of the equation. +Further, since it is possible hardware may issue requests at the boundary of a clock state changes, additional fabric gaskets would be required to protect hosts when destinations are temporarily clocked off. +The bus requests themselves thus become dynamic clock request signals to help enable components in its path. + +There is thus a moderate design and high verification cost to supporting `wfi` gating for the infrastructural group. + +## Block Diagram + +The following is a high level block diagram of the clock manager. + +![Clock Manager Block Diagram](clkmgr_block_diagram.svg) + +### Reset Domains + +Since the function of the clock manager is tied closely into the power-up behavior of the device, the reset domain selection must also be purposefully done. +To ensure that default clocks are available for the [power manager to release resets and initialize memories](../../pwrmgr/README.md#fast-clock-domain-fsm), the clock dividers inside the clock manager directly use `por` (power-on-reset) derived resets. +This ensures that the root clocks are freely running after power-up and its status can be communicated to the `pwrmgr` regardless of any other activity in the device. + +The other functions inside the clock manager operate on the `life cycle reset` domain. +This ensures that other clock manager functions still release early relative to most functions in the system, and that a user or escalation initiated reset still restores the clock manager to a default clean slate. + +The escalation reset restoration is especially important as the clock manager can generate fatal faults that lead to escalation. +If there were not a mechanism that allows escalation to clear the original fault, the system would simply remain in a faulted state until a user initiated a `por` event. + +For a detailed breakdown between `por` and `life cycle` resets, please see the [reset manager](../../rstmgr/README.md). + +The following diagram enhances the block diagram to illustrate the overall reset domains of the clock manager. +![Clock Manager Block Diagram](clkmgr_rst_domain.svg) + +### Clock Gated Indications for Alert Handler + +The alert handler needs to know the status of the various clock domains in the system to avoid false alert indications due to the ping mechanism. +To that end, the clock manager outputs a 4bit MuBi signal for each clock domain that indicates whether its clock is active. +For more information on this mechanism, see [alert handler documentation](../../alert_handler/doc/theory_of_operation.md#low-power-management-of-alert-channels). + +## Design Details + +### Root Clock Gating and Interface with Power Manager + +All clock groups except the power-up group run from gated source clocks. +The source clocks are gated off during low power states as controlled by the power manager. +When the power manager makes a clock enable request, the clock manager ensures all root clock gates are enabled before acknowledging. +Likewise, when the power manager makes a clock disable request, the clock manager ensures all root clock gates off disabled before acknowledging. + +Note, the power manager's request to turn off clocks supersedes all other local controls in the clock manager. +This means even if a particular clock is turned on by the clock manager (for example a transactional unit that is ongoing or a peripheral that is enabled), the power manager requests will still turn clocks on / off at the root. + +This makes it software's responsibility to ensure low power entry requests (which can only be initiated by software) do not conflict with any ongoing activities controlled by software. +For example, software should ensure that Aes / Otbn activities have completed before initializing a low power entry process. + +### Clock Division + +Not all peripherals run at the full IO clock speed, hence the IO clock is divided down by 2x and 4x in normal operation. +This division ratio can be modified to 1x and 2x when switching to an external clock, since the external clock may be slower than the internal clock source. +See also [external clock switch support](#external-clock-switch-support). + +The divided clock is not assumed to be synchronous with its source and is thus treated like another asynchronous branch. +Further, the clock dividers are hardwired and have no software control, this is to further ensure there are no simple paths for faulty or malicious software to tamper. + +Note that for debug purposes, `ast` can also request a change in the clock division ratio via a dedicated hardware interface (`div_step_down_req_i`). + +### Wait-for-Interrupt Support + +Given the marginal benefits and the increased complexity of `wfi` support, the first version of this design does not support `wfi` gating. +All `wfi CG` modules in the block diagram are thus drawn with dashed lines to indicate it can be theoretically supported but currently not implemented. + +It may be added for future more complex systems where there is a need to tightly control infrastructural power consumption as a result from clocks. + +### External Clock Switch Support + +Clock manager supports the ability to request root clocks switch to an external clock. +There are two occasions where this is required: +- Life cycle transition from `RAW` / `TEST_LOCKED*` to `TEST_UNLOCKED*` [states](../../../../ip/lc_ctrl/README.md#clk_byp_req). +- Software request for external clocks during normal functional mode. + + +#### Life Cycle Requested External Clock + +The life cycle controller only requests the io clock input to be switched. +When the life cycle controller requests external clock, a request signal `lc_clk_byp_req_i` is sent from `lc_ctrl` to `clkmgr`. +`clkmgr` then forwards the request to `ast` through `io_clk_byp_req_o`, which performs the actual clock switch and is acknowledged through `io_clk_byp_ack_i`. +When the clock switch is complete, the clock dividers are stepped down by a factor of 2 and the life cycle controller is acknowledged through `lc_clk_byp_ack_o`. + +Note that this division factor change is done since the external clock is expected to be 48MHz while the nominal frequency of the internal clock is 96MHz. +I.e. this division factor change keeps the nominal frequencies of the div_2 and div_4 clocks stable at 48Mhz and 24MHz, respectively. +See [Clock Frequency Summary](#clock-frequency-summary) for more details. + +#### Software Requested External Clocks + +Unlike the life cycle controller, a software request for external clocks switches all clock sources to an external source. +Software request for external clocks is not always valid. +Software is only able to request for external clocks when hardware debug functions are [allowed](../../../../ip/lc_ctrl/README.md#hw_debug_en). + +When software requests the external clock switch, it also provides an indication how fast the external clock is through [`EXTCLK_CTRL.HI_SPEED_SEL`](registers.md#extclk_ctrl). +There are two supported clock speeds: +* High speed - external clock is close to nominal speeds (e.g. external clock is 96MHz and nominal frequency is 96MHz-100MHz) +* Low speed - external clock is half of nominal speeds (e.g. external clock is 48MHz and nominal frequency is 96MHz-100MHz) + +When software requests external clock, the register bit [`EXTCLK_CTRL.SEL`](registers.md#extclk_ctrl) is written. +If hardware debug functions are allowed, the `clkmgr` sends a request signal `all_clk_byp_req_o` to `ast` and is acknowledged through `all_clk_byp_ack_i`. + +If software requests a low speed external clock, at the completion of the switch, internal dividers are also stepped down. +When the divider is stepped down, a divide-by-4 clock becomes divide-by-2 clock , and a divide-by-2 becomes a divide-by-1 clock. + +If software requests a high speed external clock, the dividers are kept as is. + + +Note, software external clock switch support is meant to be a debug / evaluation feature, and should not be used in conjunction with the clock frequency and timeout measurement features. +This is because if the clock frequency suddenly changes, the thresholds used for timeout / measurement checks will no longer apply. +There is currently no support in hardware to dynamically synchronize a threshold change to the expected frequency. + +#### Clock Frequency Summary + +The table below summarises the valid modes and the settings required. + +| Mode | `lc_clk_byp_req_i` | `extclk_ctrl.sel` | `extclk_ctrl.hi_speed_sel` | life cycle state | +| ------------- | --------------------- | ----------------- | ----------------------------| -------------------------------| +| Life cycle in `RAW`, `TEST*` and `RMA` states | `lc_ctrl_pkg::On` | `kMultiBit4False` | Don't care | Controlled by `lc_ctrl` | +| Internal Clocks | `lc_ctrl_pkg::Off` | `kMultiBit4False` | Don't care | All | +| Software external high speed | `lc_ctrl_pkg::Off` | `kMultiBit4True` | `kMultiBit4True` | `TEST_UNLOCKED*`, `DEV`, `RMA` | +| Software external low speed | `lc_ctrl_pkg::Off` | `kMultiBit4True` | `kMultiBit4False` | `TEST_UNLOCKED*`, `DEV`, `RMA` | + +The table below summarizes the frequencies in each mode. +This table assumes that the internal clock source is 96MHz. +This table also assumes that high speed external clock is 96MHz, while low speed external clock is 48MHz. + +| Mode | External Clock Frequency | div_1_clock | div_2_clock | div_4_clock | +| ------------- | ------------------------ | ------------- | --------------- | -------------| +| Internal Clocks | Not applicable | 96MHz | 48MHz | 24MHz | +| Life cycle transition | 48MHz | 48MHz | 48MHz | 24MHz | +| Software external high speed | 96MHz | 96MHz | 48MHz | 24MHz | +| Software external low speed | 48MHz | 48MHz | 48MHz | 24MHz | + +As can be seen from the table, the external clock switch scheme prioritizes the stability of the divided clocks, while allowing the undivided clocks to slow down. + + +### Clock Frequency / Time-out Measurements + +Clock manager can continuously measure root clock frequencies to see if any of the root clocks have deviated from the expected frequency. +This feature can be enabled through the various measurement control registers such as [`IO_MEASURE_CTRL`](registers.md#io_measure_ctrl). + +The root clocks, specifically the clocks supplied from `ast` and their divided variants, are constantly measured against the `always on clock` when this feature is enabled. +Software sets both an expected maximum and minimum for each measured clock. + +Clock manager then counts the number of relevant root clock cycles in each always-on clock period. +If the resulting count differs from the programmed thresholds, a recoverable error is registered. + +Since the counts are measured against a single cycle of always on clock, the minimal error that can be detected is dependent on the clock ratio between the measured clock and 1 cycle of the always on clock. +Assume a 24MHz clock and an always-on clock of 200KHz. +The minimal error detection is then 200KHz / 24MHz, or approximately 0.83%. + +This means if the clock's actual value is between 23.8MHz and 24.2MHz, this deviation will not be detected. +Conversely, if the clock's natural operation has an error range wider than this resolution, the min / max counts must be adjusted to account for this error. + +Additionally, clock manager uses a similar time-out mechanism to see if any of the root clocks have stopped toggling for an extended period of time. +This is done by creating an artificial handshake between the root clock domain and the always on clock domain that must complete within a certain amount of time based on known clock ratios. +Based on the nature of the handshake and the margin window, the minimal timeout detection window is approximately 2-4 always on clock cycles. +If the root clock domain stops and resumes in significantly less time than this window, the time-out may not be detected. + +There are three types of errors: +* Clock too fast error +* Clock too slow error +* Clock time-out error + +Clock too fast is registered when the clock cycle count is greater than the software programmed max threshold. +Clock too slow is registered when the clock cycle count is less than the software programmed min threshold. +Clock time-out is registered when the clock stops toggling and the timeout threshold is reached. + +As these are all software supplied values, the entire measurement control can be locked from further programming through [`MEASURE_CTRL_REGWEN`](registers.md#measure_ctrl_regwen). diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/README.md new file mode 100644 index 00000000000..9c42bfe3194 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/README.md @@ -0,0 +1,190 @@ +# CLKMGR DV document + +## Goals +* **DV** + * Verify all CLKMGR IP features by running dynamic simulations with a SV/UVM based testbench. + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules. +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench. + * Verify clock gating assertions. + +## Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/latest/report.html) + +## Design features +The detailed information on CLKMGR design features is at [CLKMGR HWIP technical specification](../README.md). + +## Testbench architecture +CLKMGR testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at `hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tb.sv`. +It instantiates the CLKMGR DUT module `hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr.sv`. +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: + +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* CLKMGR IOs: `hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_if.sv` + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: + +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Global types & methods +All common types and methods defined at the package level can be found in +`clkmgr_env_pkg`. Some of them in use are: + +```systemverilog + localparam int NUM_PERI = 2; + localparam int NUM_TRANS = 4; + localparam int NUM_ALERTS = 2; + + typedef logic [NUM_PERI-1:0] peri_enables_t; + typedef logic [NUM_TRANS-1:0] hintables_t; + + typedef virtual clkmgr_if clkmgr_vif; + typedef virtual clk_rst_if clk_rst_vif; + typedef enum int { + PeriIoDiv4, + PeriIoDiv2 + } peri_e; + typedef enum int {TransAes, TransHmac, TransKmac, TransOtbn} trans_e; +``` + +### TL_agent +CLKMGR testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into CLKMGR device. + +### UVM RAL Model +The CLKMGR RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md): + +## Stimulus strategy +This module is rather simple: the stimulus is just the external pins and the CSR updates. +There are a couple stages for synchronization of the CSR updates for clock gating controls, but scanmode is used asynchronously. +These go to the clock gating latches. +The external pins controlling the external clock selection need no synchronization. +The tests randomize the inputs and issue CSR updates affecting the specific functions being tested. + +### Test sequences +All test sequences reside in `hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib`. +The `clkmgr_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +It provides commonly used handles, variables, functions and tasks that the test sequences can use or call. +Some of the most commonly used tasks / functions are as follows: +* `clkmgr_init`: Sets the frequencies of the various clocks. +* `control_ip_clocks`: Turns on or off the input clocks based on the various clock enable and status ports to and from the `pwrmgr` IP. + +All test sequences are extended from `clkmgr_base_vseq`, and are described below. + +#### clkmgr_peri_vseq + +The sequence `clkmgr_peri_vseq` randomizes the stimuli that drive the four peripheral clocks. +These clocks are mutually independent so they are tested in parallel. +They depend on +* The `clk_enables` CSR, which has a dedicated enable for each peripheral clock +* The pwrmgr's `_ip_clk_en` which has a dedicated bit controlling `io`, `main`, and `usb` clocks +* The `scanmode_i` input, which is used asynchronously and also controls all. + +The sequence runs a number of iterations, each randomizing the above except for `io_ip_clk_en` since that would imply the processor is disabled. + +#### clkmgr_trans_vseq + +The sequence `clkmgr_trans_vseq` randomizes the stimuli that drive the five transactional unit clocks. +These are also mutually independent so they are tested in parallel. +They depend on the `clk_hints` CSR, which has a separate bit for each, `main_ip_clk_en` and `scanmode_i`, similar to the peripheral clocks. +They also depend on the `idle_i` input, which also has a separate multi-bit value for each unit. +Units are considered busy when their corresponding `idle_i` value is not `mubi_pkg::MuBi4True`, and this prevents its clock turning off until it becomes idle. + +#### clkmgr_extclk_vseq + +The sequence `clkmgr_extclk_vseq` randomizes the stimuli that drive the external clock selection. +The selection is controlled by software if the `extclk_ctrl.sel` CSR is `prim_mubi_pkg::MuBi4True`, provided the `lc_hw_debug_en_i` input is also set to `lc_ctrl_pkg::On`. +Alternatively, the external clock is selected by the life cycle controller if the `lc_ctrl_byp_req_i` input is `lc_ctrl_pkg::On`. +When the external clock is selected and `scanmode_i` is not set to `prim_mubi_pkg::MuBi4True`, the clock dividers for the clk_io_div2 and clk_io_div4 output clocks are stepped down: +* If `lc_ctrl_byp_req_i` is on, or +* If `extclk_ctrl.hi_speed_sel` CSR is `prim_mubi_pkg::MuBi4True`, when the selection is enabled by software. + +#### clkmgr_frequency_vseq + +The sequence `clkmgr_frequency_vseq` randomly programs the frequency measurement for each clock so its measurement is either okay, slow, or fast. +It checks the recoverable alerts trigger as expected when a measurement is not okay. +It also checks the `recov_err_code` CSR sets bits for clocks whose measurement is out of bounds. +It also checks that loss of calibration stops clock measurements and doesn't trigger errors. + +#### clkmgr_frequency_timeout_vseq + +The sequence `clkmgr_frequency_timeout_vseq` programs the frequency measurement for each clock so its measurement is okay. +It randomly stops one of the clocks, and checks the corresponding bit in the `recov_err_code` show a timeout. +It also checks the recoverable alerts trigger as expected for a timeout. + +#### clkmgr_clk_status_vseq + +This checks that the `pwr_o.*_status` outputs track the `pwr_i.*_ip_clk_en` inputs. +The inputs are set at random and the outputs are checked via SVA. + +### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: + +* Covergroups for inputs to each software gated peripheral clock. + These are wrapped in class `clkmgr_peri_cg_wrap` and instantiated in `clkmgr_env_cov`. +* Covergroups for inputs to each transactional gated unit clock. + These are wrapped in class `clkmgr_trans_cg_wrap` and instantiated in `clkmgr_env_cov`. +* Covergroups for the outcome of each clock measurement. + These are wrapped in class `freq_measure_cg_wrap` and instantiated in `clkmgr_env_cov`. +* Covergroup for the external clock selection logic: `extclk_cg` in `clkmgr_env_cov`. + +See more detailed description at `hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/data/clkmgr_testplan.hjson`. + +## Self-checking strategy + +Most of the checking is done using SVA for input to output, or CSR update to output behavior. +Some of the CLKMGR outputs are gated clocks, which are controlled by both synchronous logic and asynchronous enables. +These asynchronous enables become synchronous because of the SVA semantics. +This is fine since the assertions allow some cycles for the expected behavior to occur. + +### Scoreboard +The `clkmgr_scoreboard` combines CSR updates and signals from the clkmgr vif to instrument some checks and coverage collection. +The CSR updates are determined using the TLUL analysis port. + +The CSR controlled output clocks can be separated into two groups: peripheral ip clocks and transactional unit clocks. +Please refer to the [Test sequences section](#test-sequences) above. +The clock gating logic is pretty similar across units in each group. +For each peripheral and transactional clock the scoreboard samples their coverage based on clocking blocks instantiated in `clkmgr_if`. +Most other other functional coverage groups are also sampled in the scoreboard. + +The `jitter_en_o` output is checked to match the `jitter_enable` CSR. + +### Assertions +* Pwrmgr enable-status assertions: Interface `clkmgr_pwrmgr_sva_if` contains concurrent SVA that checks that edges of the various ip_clk_en are followed by corresponding edges of their clk_status. + The clocks checked are `main`, `io`, and `usb`. +* Gated clock assertions: Interface `clkmgr_gated_clock_sva_if` contains concurrent SVA that checks each gated clock is either running or stopped based on their control logic. + There is one assertion for each of the four peripheral clock and four hintable clocks. +* Transactional clock assertions: Interface `clkmgr_trans_sva_if` contains concurrent SVA that checks each transactional clock is either running or stopped based on their control logic. + There is one assertion for each of the four hintable clocks. +* Clock divider assertions: Interface `clkmgr_div_sva_if` contains concurrent SVA that checks the `io_div2` and `io_div4` clocks are running at nominal frequency, or are divided by two each in response to the `extclk` logic. +* External clock assertions: Interface `clkmgr_extclk_sva_if` contains concurrent SVA that checks the external control outputs respond correctly to the various CSR or inputs that control them. +* Clock gating assertions: Interface `clkmgr_cg_en_sva_if` contains concurrent assertions that check a clock's cg_en output is active when the clock is disabled, and viceversa. + As a special case, interface `clkmgr_aon_cg_en_sva_if` checks cg_en is never active for an aon clock. +* Lost calibration assertions: Interfaces `clkmgr_lost_calib_ctrl_en_sva_if` and `clkmgr_lost_calib_regwen_sva_if` check that losing calibration turns off clock measurements and re-enables measure control writes. +* TLUL assertions: `clkmgr_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: + +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson -i clkmgr_smoke +``` + +## Testplan +[Testplan](../data/clkmgr_testplan.hjson) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/clkmgr_sim.core b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/clkmgr_sim.core new file mode 100644 index 00000000000..a57b18e880b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/clkmgr_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:clkmgr_sim:0.1 +description: "CLKMGR DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:clkmgr + + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:clkmgr_test:0.1 + - lowrisc:darjeeling_no_ibex_dv:clkmgr_sva:0.1 + files: + - tb.sv + - cov/clkmgr_cov_bind.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson new file mode 100644 index 00000000000..6866f056fc4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson @@ -0,0 +1,135 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: clkmgr + + // Top level dut name (sv module). + dut: clkmgr + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_dv:clkmgr_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/clkmgr_testplan.hjson" + + // RAL spec - used to generate the RAL model. + ral_spec: "{self_dir}/../data/clkmgr.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson" + ] + + // Add additional tops for simulation. + sim_tops: ["clkmgr_bind", + "clkmgr_cov_bind", + "sec_cm_prim_count_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // CLKMGR exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov/clkmgr_cov_manual_excl.el", + "{self_dir}/cov/clkmgr_cov_unr_excl.el"] + + // Handle generated coverage exclusion. + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {dv_root}/tools/vcs/cover.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/clkmgr_tgl_excl.cfg" + } + ] + // Default UVM test and seq class name. + uvm_test: clkmgr_base_test + uvm_test_seq: clkmgr_base_vseq + + // Disable clearing interrupts since clkmgr doesn't have any. + run_opts: ["+do_clear_all_interrupts=0", + // Enable cdc instrumentation. + "+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: clkmgr_smoke + uvm_test_seq: clkmgr_smoke_vseq + } + { + name: clkmgr_extclk + uvm_test_seq: clkmgr_extclk_vseq + } + { + name: clkmgr_frequency + uvm_test_seq: clkmgr_frequency_vseq + } + { + name: clkmgr_frequency_timeout + uvm_test_seq: clkmgr_frequency_timeout_vseq + } + { + name: clkmgr_peri + uvm_test_seq: clkmgr_peri_vseq + } + { + name: clkmgr_trans + uvm_test_seq: clkmgr_trans_vseq + } + { + name: clkmgr_clk_status + uvm_test_seq: clkmgr_clk_status_vseq + } + { + name: clkmgr_idle_intersig_mubi + uvm_test_seq: clkmgr_trans_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiIdle"] + } + { + name: clkmgr_lc_ctrl_intersig_mubi + uvm_test_seq: clkmgr_extclk_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiLcCtrl"] + } + { + name: clkmgr_lc_clk_byp_req_intersig_mubi + uvm_test_seq: clkmgr_extclk_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiLcHand"] + } + { + name: clkmgr_clk_handshake_intersig_mubi + uvm_test_seq: clkmgr_extclk_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiHand"] + } + { + name: clkmgr_div_intersig_mubi + uvm_test_seq: clkmgr_extclk_vseq + run_opts: ["+clkmgr_mubi_mode=ClkmgrMubiDiv"] + } + { + name: clkmgr_regwen + uvm_test_seq: clkmgr_regwen_vseq + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["clkmgr_smoke"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_cov_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_cov_bind.sv new file mode 100644 index 00000000000..7e5ef8e3ec9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_cov_bind.sv @@ -0,0 +1,50 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// Clock manager coverage bindings for multi bus input +module clkmgr_cov_bind; + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_idle_0_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (idle_i[0]) + ); + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_idle_1_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (idle_i[1]) + ); + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_idle_2_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (idle_i[2]) + ); + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_idle_3_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (idle_i[3]) + ); + + bind clkmgr cip_lc_tx_cov_if u_lc_hw_debug_en_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_hw_debug_en_i) + ); + + bind clkmgr cip_lc_tx_cov_if u_lc_clk_byp_req_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_clk_byp_req_i) + ); + + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_io_clk_byp_ack_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (io_clk_byp_ack_i) + ); + + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_all_clk_byp_ack_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (all_clk_byp_ack_i) + ); + + bind clkmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_div_step_down_req_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (div_step_down_req_i) + ); + +endmodule // clkmgr_cov_bind diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el new file mode 100644 index 00000000000..ca5f99828dd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_cov_manual_excl.el @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This contains some obvious exclusions the UNR tool didn't flag. + +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Thu Sep 29 13:57:41 2022 +// ExclMode: default +//================================================== +CHECKSUM: "2301929872 1660332954" +INSTANCE: tb.dut.u_clk_main_aes_trans.u_idle_cnt +ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." +Toggle step_i "net step_i[3:0]" +CHECKSUM: "2301929872 1660332954" +INSTANCE: tb.dut.u_clk_main_hmac_trans.u_idle_cnt +ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." +Toggle step_i "net step_i[3:0]" +CHECKSUM: "2301929872 1660332954" +INSTANCE: tb.dut.u_clk_main_kmac_trans.u_idle_cnt +ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." +Toggle step_i "net step_i[3:0]" +CHECKSUM: "2301929872 1660332954" +INSTANCE: tb.dut.u_clk_main_otbn_trans.u_idle_cnt +ANNOTATION: "[UNR] Input tied to a constant, and unr doesn't detect it." +Toggle step_i "net step_i[3:0]" +CHECKSUM: "953655365 3155586170" +INSTANCE: tb.dut +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.aon_powerup "logic cg_en_o.aon_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.usb_powerup "logic cg_en_o.usb_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.main_powerup "logic cg_en_o.main_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.io_powerup "logic cg_en_o.io_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.io_div2_powerup "logic cg_en_o.io_div2_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.io_div4_powerup "logic cg_en_o.io_div4_powerup[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.aon_peri "logic cg_en_o.aon_peri[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.aon_timers "logic cg_en_o.aon_timers[3:0]" +ANNOTATION: "[UNR] This is driven by a constant, and unr doesn't detect it." +Toggle cg_en_o.aon_secure "logic cg_en_o.aon_secure[3:0]" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el new file mode 100644 index 00000000000..85e292d7a9f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_cov_unr_excl.el @@ -0,0 +1,200 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Generated UNR file from Synopsys UNR tool with security modules being +// black-boxed. + +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Wed Jan 18 15:59:24 2023 +// ExclMode: default +//================================================== +CHECKSUM: "2972535896 3274445021" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") +CHECKSUM: "2972535896 3274445021" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") +CHECKSUM: "2972535896 3274445021" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") +CHECKSUM: "2972535896 3274445021" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (1 "0") +CHECKSUM: "2972535896 3554514034" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_aes_val +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (1) "wr_en 0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" +CHECKSUM: "2972535896 3554514034" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_hmac_val +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (1) "wr_en 0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" +CHECKSUM: "2972535896 3554514034" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_kmac_val +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (1) "wr_en 0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" +CHECKSUM: "2972535896 3554514034" +INSTANCE: tb.dut.u_reg.u_clk_hints_status_clk_main_otbn_val +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (1) "wr_en 0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "215202837 3193272610" +INSTANCE: tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk +ANNOTATION: "VC_COV_UNR" +Branch 0 "3003057152" "(!rst_ni)" (4) "(!rst_ni) 0,0,0,0" +CHECKSUM: "2970503351 1213720317" +INSTANCE: tb.dut.u_reg +ANNOTATION: "VC_COV_UNR" +Condition 53 "2949805610" "(io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 55 "3453311186" "(io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 57 "3988383834" "(io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 59 "1995093715" "(main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 61 "2462107587" "(usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen) 1 -1" (1 "01") +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_reg.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "2928260248 4109606122" +INSTANCE: tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb +ANNOTATION: "VC_COV_UNR" +Condition 5 "593451913" "(((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d) 1 -1" (1 "01") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_div2_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_io_div4_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_main_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") +CHECKSUM: "704952876 1147758610" +INSTANCE: tb.dut.u_usb_meas.u_err_sync +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "700807773" "(dst_req_o & dst_ack_i) 1 -1" (2 "10") diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_tgl_excl.cfg b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_tgl_excl.cfg new file mode 100644 index 00000000000..d28f39cf064 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/cov/clkmgr_tgl_excl.cfg @@ -0,0 +1,16 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//====================================================================== +// This file contains outputs of clkmgr tied to constants. +//====================================================================== + +-module_node clkmgr cg_en_o.io_div4_powerup +-module_node clkmgr cg_en_o.aon_powerup +-module_node clkmgr cg_en_o.main_powerup +-module_node clkmgr cg_en_o.io_powerup +-module_node clkmgr cg_en_o.io_div2_powerup +-module_node clkmgr cg_en_o.aon_infra +-module_node clkmgr cg_en_o.aon_peri +-module_node clkmgr cg_en_o.aon_timers diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/doc/tb.svg b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/doc/tb.svg new file mode 100644 index 00000000000..3f48ecc3acc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_csrs_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_csrs_if.sv new file mode 100644 index 00000000000..e5ec0a107b5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_csrs_if.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This interface is used to sample some csr values directly from the rtl +// to avoid any confusion. + +interface clkmgr_csrs_if ( + input logic clk, + input logic [4:0] recov_err_csr, + input logic [2:0] fatal_err_csr, + input logic [1:0] clk_enables, + input logic [3:0] clk_hints +); + +clocking csrs_cb @(posedge clk); + input recov_err_csr; + input fatal_err_csr; + input clk_enables; + input clk_hints; +endclocking + +endinterface : clkmgr_csrs_if diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env.core b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env.core new file mode 100644 index 00000000000..7c1da804806 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env.core @@ -0,0 +1,51 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:clkmgr_env:0.1 +description: "CLKMGR DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg + - lowrisc:darjeeling_no_ibex_ip:clkmgr_pkg + - lowrisc:darjeeling_no_ibex_constants:top_pkg + files: + - clkmgr_csrs_if.sv + - clkmgr_env_pkg.sv + - clkmgr_env_cfg.sv: {is_include_file: true} + - clkmgr_env_cov.sv: {is_include_file: true} + - clkmgr_virtual_sequencer.sv: {is_include_file: true} + - clkmgr_scoreboard.sv: {is_include_file: true} + - clkmgr_env.sv: {is_include_file: true} + - seq_lib/clkmgr_vseq_list.sv: {is_include_file: true} + - seq_lib/clkmgr_base_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_clk_status_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_common_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_extclk_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_frequency_timeout_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_frequency_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_peri_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_regwen_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_smoke_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/clkmgr_trans_vseq.sv: {is_include_file: true} + - clkmgr_if.sv + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: clkmgr + ip_hjson: ../../data/clkmgr.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env.sv new file mode 100644 index 00000000000..30cfd7da35c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env.sv @@ -0,0 +1,78 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_env extends cip_base_env #( + .CFG_T (clkmgr_env_cfg), + .COV_T (clkmgr_env_cov), + .VIRTUAL_SEQUENCER_T(clkmgr_virtual_sequencer), + .SCOREBOARD_T (clkmgr_scoreboard) +); + `uvm_component_utils(clkmgr_env) + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "aon_clk_rst_vif", cfg.aon_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get aon_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_clk_rst_vif", cfg.io_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "main_clk_rst_vif", cfg.main_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get main_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_div2_clk_rst_vif", cfg.io_div2_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_div2_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_div4_clk_rst_vif", cfg.io_div4_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_div4_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "root_main_clk_rst_vif", cfg.root_main_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get root_main_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "root_io_clk_rst_vif", cfg.root_io_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get root_io_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "root_io_div2_clk_rst_vif", cfg.root_io_div2_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get root_io_div2_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "root_io_div4_clk_rst_vif", cfg.root_io_div4_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get root_io_div4_clk_rst_vif from uvm_config_db") + end + + if (!uvm_config_db#(virtual clkmgr_if)::get(this, "", "clkmgr_vif", cfg.clkmgr_vif)) begin + `uvm_fatal(`gfn, "failed to get clkmgr_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clkmgr_csrs_if)::get( + this, "", "clkmgr_csrs_vif", cfg.clkmgr_csrs_vif + )) begin + `uvm_fatal(`gfn, "failed to get clkmgr_csrs_vif from uvm_config_db") + end + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env_cfg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env_cfg.sv new file mode 100644 index 00000000000..460b7adbd5f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env_cfg.sv @@ -0,0 +1,47 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_env_cfg extends cip_base_env_cfg #( + .RAL_T(clkmgr_reg_block) +); + + // This scoreboard handle is used to flag expected errors. + clkmgr_scoreboard scoreboard; + + // ext component cfgs + + // ext interfaces + virtual clkmgr_if clkmgr_vif; + virtual clkmgr_csrs_if clkmgr_csrs_vif; + virtual clk_rst_if aon_clk_rst_vif; + virtual clk_rst_if io_clk_rst_vif; + virtual clk_rst_if main_clk_rst_vif; + virtual clk_rst_if io_div2_clk_rst_vif; + virtual clk_rst_if io_div4_clk_rst_vif; + + virtual clk_rst_if root_main_clk_rst_vif; + virtual clk_rst_if root_io_clk_rst_vif; + virtual clk_rst_if root_io_div2_clk_rst_vif; + virtual clk_rst_if root_io_div4_clk_rst_vif; + + `uvm_object_utils_begin(clkmgr_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + virtual function void initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = clkmgr_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + + // This is for the integrity error test. + tl_intg_alert_name = "fatal_fault"; + tl_intg_alert_fields[ral.fatal_err_code.reg_intg] = 1; + m_tl_agent_cfg.max_outstanding_req = 1; + + // shadow registers + shadow_update_err_status_fields[ral.recov_err_code.shadow_update_err] = 1; + shadow_storage_err_status_fields[ral.fatal_err_code.shadow_storage_err] = 1; + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env_cov.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env_cov.sv new file mode 100644 index 00000000000..2c68ddacc5f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env_cov.sv @@ -0,0 +1,178 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergroups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ + +// Wrapper class for peripheral clock covergroup. +class clkmgr_peri_cg_wrap; + // This covergroup collects signals affecting peripheral clock. + covergroup peri_cg(string name) with function sample (bit enable, bit ip_clk_en, bit scanmode); + option.name = name; + option.per_instance = 1; + + csr_enable_cp: coverpoint enable; + ip_clk_en_cp: coverpoint ip_clk_en; + scanmode_cp: coverpoint scanmode; + + peri_cross: cross csr_enable_cp, ip_clk_en_cp, scanmode_cp{ + // The enable CSRs cannot be manipulated in low power mode. + ignore_bins ignore_enable_off = peri_cross with (csr_enable_cp == 1 && ip_clk_en_cp == 0); + } + endgroup + + function new(string name); + peri_cg = new(name); + endfunction + + function void sample (bit enable, bit ip_clk_en, bit scanmode); + peri_cg.sample(enable, ip_clk_en, scanmode); + endfunction +endclass + +// Wrapper class for transactional unit clock covergroup. +class clkmgr_trans_cg_wrap; + // This covergroup collects signals affecting transactional clock. + covergroup trans_cg( + string name + ) with function sample ( + bit hint, bit ip_clk_en, bit scanmode, bit idle + ); + option.name = name; + option.per_instance = 1; + + csr_hint_cp: coverpoint hint; + ip_clk_en_cp: coverpoint ip_clk_en; + scanmode_cp: coverpoint scanmode; + idle_cp: coverpoint idle; + + trans_cross: cross csr_hint_cp, ip_clk_en_cp, scanmode_cp, idle_cp{ + // If the clock is disabled the unit must be idle. + ignore_bins ignore_idle_off = trans_cross with (idle_cp == 0 && ip_clk_en_cp == 0); + // The hint CSRs cannot be manipulated in low power mode. + ignore_bins ignore_enable_off = trans_cross with (csr_hint_cp == 1 && ip_clk_en_cp == 0); + } + endgroup + + function new(string name); + trans_cg = new(name); + endfunction + + function void sample (bit hint, bit ip_clk_en, bit scanmode, bit idle); + trans_cg.sample(hint, ip_clk_en, scanmode, idle); + endfunction +endclass + +// Wrapper class for frequency measurement covergroup. +class freq_measure_cg_wrap; + // This covergroup collects outcomes of clock frequency measurements. + covergroup freq_measure_cg( + string name + ) with function sample ( + bit okay, bit slow, bit fast, bit timeout + ); + option.name = name; + option.per_instance = 1; + + okay_cp: coverpoint okay; + slow_cp: coverpoint slow; + fast_cp: coverpoint fast; + timeout_cp: coverpoint timeout; + endgroup + + function new(string name); + freq_measure_cg = new(name); + endfunction + + function void sample (bit okay, bit slow, bit fast, bit timeout); + freq_measure_cg.sample(okay, slow, fast, timeout); + endfunction +endclass + +class clkmgr_env_cov extends cip_base_env_cov #( + .CFG_T(clkmgr_env_cfg) +); + `uvm_component_utils(clkmgr_env_cov) + + // the base class provides the following handles for use: + // clkmgr_env_cfg: cfg + + // These covergroups collect signals affecting peripheral clocks. + clkmgr_peri_cg_wrap peri_cg_wrap[NUM_PERI]; + + // These covergroups collect signals affecting transactional clocks. + clkmgr_trans_cg_wrap trans_cg_wrap[NUM_TRANS]; + + // These covergroups collect outcomes of clock frequency measurements. + freq_measure_cg_wrap freq_measure_cg_wrap[2]; + + // This embeded covergroup collects coverage for the external clock functionality. + covergroup extclk_cg with function sample ( + bit csr_sel, bit csr_low_speed, bit hw_debug_en, bit byp_req, bit scanmode + ); + csr_sel_cp: coverpoint csr_sel; + csr_low_speed_cp: coverpoint csr_low_speed; + hw_debug_en_cp: coverpoint hw_debug_en; + byp_req_cp: coverpoint byp_req; + scanmode_cp: coverpoint scanmode; + + extclk_cross: cross csr_sel_cp, csr_low_speed_cp, hw_debug_en_cp, byp_req_cp, scanmode_cp; + endgroup + + // This collects coverage for recoverable errors. + covergroup recov_err_cg with function sample ( + bit main_timeout, + bit io_div4_timeout, + bit main_measure, + bit io_div4_measure, + bit shadow_update + ); + shadow_update_cp: coverpoint shadow_update; + io_div4_measure_cp: coverpoint io_div4_measure; + main_measure_cp: coverpoint main_measure; + io_div4_timeout_cp: coverpoint io_div4_timeout; + main_timeout_cp: coverpoint main_timeout; + endgroup + + // This collects coverage for fatal errors. + covergroup fatal_err_cg with function sample ( + bit shadow_storage, bit idle_cnt, bit reg_integ + ); + reg_integ_cp: coverpoint reg_integ; + idle_cnt_cp: coverpoint idle_cnt; + shadow_storage_cp: coverpoint shadow_storage; + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + // The peripheral Covergroups. + foreach (peri_cg_wrap[i]) begin + clkmgr_env_pkg::peri_e peri = clkmgr_env_pkg::peri_e'(i); + peri_cg_wrap[i] = new(peri.name); + end + // The transactional covergroups. + foreach (trans_cg_wrap[i]) begin + clkmgr_env_pkg::trans_e trans = clkmgr_env_pkg::trans_e'(i); + trans_cg_wrap[i] = new(trans.name); + end + foreach (ExpectedCounts[i]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(i); + freq_measure_cg_wrap[i] = new(clk_mesr.name); + end + extclk_cg = new(); + recov_err_cg = new(); + fatal_err_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv new file mode 100644 index 00000000000..3bcdb699795 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_env_pkg.sv @@ -0,0 +1,147 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package clkmgr_env_pkg; + // dep packages + import uvm_pkg::*; + import sec_cm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import clkmgr_ral_pkg::*; + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + + import lc_ctrl_pkg::lc_tx_t; + import lc_ctrl_pkg::On; + import lc_ctrl_pkg::Off; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + typedef virtual clkmgr_if clkmgr_vif; + typedef virtual clk_rst_if clk_rst_vif; + + // parameters + parameter int NUM_PERI = 2; + parameter int NUM_TRANS = 4; + + typedef logic [NUM_PERI-1:0] peri_enables_t; + typedef logic [NUM_TRANS-1:0] hintables_t; + typedef mubi4_t [NUM_TRANS-1:0] mubi_hintables_t; + parameter mubi_hintables_t IdleAllBusy = {NUM_TRANS{prim_mubi_pkg::MuBi4False}}; + + parameter int MainClkHz = 1_000_000_000; + parameter int IoClkHz = 1_000_000_000; + parameter int AonClkHz = 62_500_000; + parameter int IoDiv2ClkHz = 500_000_000; + parameter int IoDiv4ClkHz = 250_000_000; + parameter int FakeAonClkHz = 7_000_000; + + // alerts + parameter uint NUM_ALERTS = 2; + parameter string LIST_OF_ALERTS[NUM_ALERTS] = {"recov_fault", "fatal_fault"}; + + // types + + // Forward class decl to enable cfg to hold a scoreboard handle. + typedef class clkmgr_scoreboard; + + // The enum values for these match the bit order in the CSRs. + typedef enum int { + PeriIoDiv4, + PeriIoDiv2 + } peri_e; + typedef struct packed { + logic io_div2_peri_en; + logic io_div4_peri_en; + } clk_enables_t; + + typedef enum int { + TransAes, + TransHmac, + TransKmac, + TransOtbn + } trans_e; + typedef struct packed { + logic otbn; + logic kmac; + logic hmac; + logic aes; + } clk_hints_t; + + typedef struct { + logic valid; + logic slow; + logic fast; + } freq_measurement_t; + + // These are ordered per the bits in the recov_err_code register. + typedef enum int { + ClkMesrIoDiv4, + ClkMesrMain, + ClkMesrSize + } clk_mesr_e; + + // Mubi test mode + typedef enum int { + ClkmgrMubiNone = 0, + ClkmgrMubiIdle = 1, + ClkmgrMubiLcCtrl = 2, + ClkmgrMubiLcHand = 3, + ClkmgrMubiHand = 4, + ClkmgrMubiDiv = 5 + } clkmgr_mubi_e; + + // This is to examine separately the measurement and timeout recoverable error bits. + typedef logic [ClkMesrSize-1:0] recov_bits_t; + + typedef struct packed { + recov_bits_t timeouts; + recov_bits_t measures; + logic shadow_update; + } clkmgr_recov_err_t; + + // These must be after the declaration of clk_mesr_e for sizing. + parameter int ClkInHz[ClkMesrSize] = { + IoDiv4ClkHz, + MainClkHz + }; + + // Take into account if multiple aon clock cycles are needed for a measurement. + parameter int ExpectedCounts[ClkMesrSize] = { + (ClkInHz[ClkMesrIoDiv4] / AonClkHz) * 32 - 1, + (ClkInHz[ClkMesrMain] / AonClkHz) * 8 - 1 + }; + + // functions + function automatic void print_hintable(hintables_t tbl); + foreach (tbl[i]) begin + `uvm_info("HINTBL", $sformatf("entry%0d : %b", i, tbl[i]), UVM_LOW) + end + endfunction : print_hintable + + function automatic void print_mubi_hintable(mubi_hintables_t tbl); + string val = "INVALID"; + foreach (tbl[i]) begin + if (tbl[i].name != "") val = tbl[i].name; + `uvm_info("MUBIHINTBL", $sformatf("entry%0d : %s", i, val), UVM_LOW) + end + endfunction : print_mubi_hintable + + // package sources + `include "clkmgr_env_cfg.sv" + `include "clkmgr_env_cov.sv" + `include "clkmgr_virtual_sequencer.sv" + `include "clkmgr_scoreboard.sv" + `include "clkmgr_env.sv" + `include "clkmgr_vseq_list.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_if.sv new file mode 100644 index 00000000000..afb199050f5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_if.sv @@ -0,0 +1,282 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// clkmgr interface. + +interface clkmgr_if ( + input logic clk, + input logic rst_n, + input logic rst_aon_n, + input logic rst_io_n, + input logic rst_main_n +); + import uvm_pkg::*; + import clkmgr_env_pkg::*; + + // The ports to the dut side. + + localparam int LcTxTWidth = $bits(lc_ctrl_pkg::lc_tx_t); + + // Encodes the transactional units that are idle. + mubi_hintables_t idle_i; + + // pwrmgr req contains ip_clk_en, set to enable the gated clocks. + pwrmgr_pkg::pwr_clk_req_t pwr_i; + + // outputs clk_status: transitions to 1 if all clocks are enabled, and + // to 0 when all are disabled. + pwrmgr_pkg::pwr_clk_rsp_t pwr_o; + + // scanmode_i == MuBi4True defeats all clock gating. + prim_mubi_pkg::mubi4_t scanmode_i; + + // Life cycle enables clock bypass functionality. + lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i; + + // Life cycle clock bypass request and clkmgr ack. + lc_ctrl_pkg::lc_tx_t lc_clk_byp_req; + lc_ctrl_pkg::lc_tx_t lc_clk_byp_ack; + // clkmgr clock bypass request for io clocks and ast ack: triggered by lc_clk_byp_req. + prim_mubi_pkg::mubi4_t io_clk_byp_req; + prim_mubi_pkg::mubi4_t io_clk_byp_ack; + // clkmgr clock bypass request for all clocks and ast ack: triggered by software. + prim_mubi_pkg::mubi4_t all_clk_byp_req; + prim_mubi_pkg::mubi4_t all_clk_byp_ack; + + prim_mubi_pkg::mubi4_t div_step_down_req; + + prim_mubi_pkg::mubi4_t jitter_en_o; + clkmgr_pkg::clkmgr_out_t clocks_o; + + prim_mubi_pkg::mubi4_t calib_rdy; + prim_mubi_pkg::mubi4_t hi_speed_sel; + + // Internal DUT signals. + // ICEBOX(lowrisc/opentitan#18379): This is a core env component (i.e. reusable entity) that + // makes hierarchical references into the DUT. A better strategy would be to bind this interface + // to the DUT in tb.sv and use relative paths instead. +`ifndef CLKMGR_HIER + `define CLKMGR_HIER tb.dut +`endif + + // The CSR values from the testbench side. + clk_enables_t clk_enables_csr; + always_comb + clk_enables_csr = '{ + io_div2_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.clk_io_div2_peri_en.q, + io_div4_peri_en: `CLKMGR_HIER.reg2hw.clk_enables.clk_io_div4_peri_en.q + }; + + clk_hints_t clk_hints_csr; + always_comb + clk_hints_csr = '{ + otbn: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_otbn_hint.q, + kmac: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_kmac_hint.q, + hmac: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_hmac_hint.q, + aes: `CLKMGR_HIER.reg2hw.clk_hints.clk_main_aes_hint.q + }; + + clk_hints_t clk_hints_status_csr; + always_comb + clk_hints_status_csr = '{ + otbn: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_otbn_val_qs, + kmac: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_kmac_val_qs, + hmac: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_hmac_val_qs, + aes: `CLKMGR_HIER.u_reg.clk_hints_status_clk_main_aes_val_qs + }; + + prim_mubi_pkg::mubi4_t extclk_ctrl_csr_sel; + always_comb begin + extclk_ctrl_csr_sel = prim_mubi_pkg::mubi4_t'(`CLKMGR_HIER.reg2hw.extclk_ctrl.sel.q); + end + + prim_mubi_pkg::mubi4_t extclk_ctrl_csr_step_down; + always_comb begin + extclk_ctrl_csr_step_down = prim_mubi_pkg::mubi4_t'( + `CLKMGR_HIER.reg2hw.extclk_ctrl.hi_speed_sel.q); + end + + prim_mubi_pkg::mubi4_t jitter_enable_csr; + always_comb begin + jitter_enable_csr = prim_mubi_pkg::mubi4_t'(`CLKMGR_HIER.reg2hw.jitter_enable.q); + end + + freq_measurement_t io_div4_freq_measurement; + logic io_div4_timeout_err; + always @(posedge `CLKMGR_HIER.u_io_div4_meas.u_meas.clk_i) begin + if (`CLKMGR_HIER.u_io_div4_meas.u_meas.valid_o) begin + io_div4_freq_measurement = '{valid: `CLKMGR_HIER.u_io_div4_meas.u_meas.valid_o, + slow: `CLKMGR_HIER.u_io_div4_meas.u_meas.slow_o, + fast: `CLKMGR_HIER.u_io_div4_meas.u_meas.fast_o}; + `uvm_info("clkmgr_if", $sformatf( + "Sampled coverage for ClkMesrIoDiv4 as %p", io_div4_freq_measurement), UVM_HIGH) + end + end + always_comb io_div4_timeout_err = `CLKMGR_HIER.u_io_div4_meas.timeout_err_o; + + freq_measurement_t main_freq_measurement; + logic main_timeout_err; + always @(posedge `CLKMGR_HIER.u_main_meas.u_meas.clk_i) begin + if (`CLKMGR_HIER.u_main_meas.u_meas.valid_o) begin + main_freq_measurement = '{valid: `CLKMGR_HIER.u_main_meas.u_meas.valid_o, + slow: `CLKMGR_HIER.u_main_meas.u_meas.slow_o, + fast: `CLKMGR_HIER.u_main_meas.u_meas.fast_o}; + `uvm_info("clkmgr_if", $sformatf( + "Sampled coverage for ClkMesrMain as %p", main_freq_measurement), UVM_HIGH) + end + end + always_comb main_timeout_err = `CLKMGR_HIER.u_main_meas.timeout_err_o; + + function automatic void update_calib_rdy(prim_mubi_pkg::mubi4_t value); + calib_rdy = value; + endfunction + + function automatic void update_idle(mubi_hintables_t value); + idle_i = value; + endfunction + + function automatic void update_io_ip_clk_en(bit value); + pwr_i.io_ip_clk_en = value; + endfunction + + function automatic void update_main_ip_clk_en(bit value); + pwr_i.main_ip_clk_en = value; + endfunction + + function automatic void update_scanmode(prim_mubi_pkg::mubi4_t value); + scanmode_i = value; + endfunction + + function automatic void update_lc_debug_en(lc_ctrl_pkg::lc_tx_t value); + lc_hw_debug_en_i = value; + endfunction + + function automatic void update_lc_clk_byp_req(lc_ctrl_pkg::lc_tx_t value); + lc_clk_byp_req = value; + endfunction + + function automatic void update_all_clk_byp_ack(prim_mubi_pkg::mubi4_t value); + `uvm_info("clkmgr_if", $sformatf("In clkmgr_if update_all_clk_byp_ack with %b", value), + UVM_MEDIUM) + all_clk_byp_ack = value; + endfunction + + function automatic void update_div_step_down_req(prim_mubi_pkg::mubi4_t value); + `uvm_info("clkmgr_if", $sformatf("In clkmgr_if update_div_step_down_req with %b", value), + UVM_MEDIUM) + div_step_down_req = value; + endfunction + + function automatic void update_io_clk_byp_ack(prim_mubi_pkg::mubi4_t value); + io_clk_byp_ack = value; + endfunction + + function automatic void force_high_starting_count(clk_mesr_e clk); + `uvm_info("clkmgr_if", $sformatf("Forcing count of %0s to all 1.", clk.name()), UVM_MEDIUM) + case (clk) + ClkMesrIoDiv4: `CLKMGR_HIER.u_io_div4_meas.u_meas.cnt = '1; + ClkMesrMain: `CLKMGR_HIER.u_main_meas.u_meas.cnt = '1; + default: ; + endcase + endfunction + + task automatic init(mubi_hintables_t idle, prim_mubi_pkg::mubi4_t scanmode, + lc_ctrl_pkg::lc_tx_t lc_debug_en = lc_ctrl_pkg::Off, + lc_ctrl_pkg::lc_tx_t lc_clk_byp_req = lc_ctrl_pkg::Off, + prim_mubi_pkg::mubi4_t calib_rdy = prim_mubi_pkg::MuBi4True); + `uvm_info("clkmgr_if", "In clkmgr_if init", UVM_MEDIUM) + update_calib_rdy(calib_rdy); + update_idle(idle); + update_lc_clk_byp_req(lc_clk_byp_req); + update_lc_debug_en(lc_debug_en); + update_scanmode(scanmode); + update_all_clk_byp_ack(prim_mubi_pkg::MuBi4False); + endtask + + // Pipeline signals that go through synchronizers with the target clock domain's clock. + // thus the PIPELINE_DEPTH is 2. + + // Use clocking blocks clocked by the target clock domain's clock to transfer relevant + // control signals back to the scoreboard. + localparam int PIPELINE_DEPTH = 2; + + // Pipelines and clocking blocks for peripheral clocks. + + logic [PIPELINE_DEPTH-1:0] clk_enable_io_div4_ffs; + logic [PIPELINE_DEPTH-1:0] ip_clk_en_io_div4_ffs; + always @(posedge clocks_o.clk_io_div4_powerup or negedge rst_io_n) begin + if (rst_io_n) begin + clk_enable_io_div4_ffs <= { + clk_enable_io_div4_ffs[PIPELINE_DEPTH-2:0], clk_enables_csr.io_div4_peri_en + }; + ip_clk_en_io_div4_ffs <= {ip_clk_en_io_div4_ffs[PIPELINE_DEPTH-2:0], pwr_i.io_ip_clk_en}; + end else begin + clk_enable_io_div4_ffs <= '0; + ip_clk_en_io_div4_ffs <= '0; + end + end + clocking peri_io_div4_cb @(posedge clocks_o.clk_io_div4_powerup or negedge rst_io_n); + input ip_clk_en = ip_clk_en_io_div4_ffs[PIPELINE_DEPTH-1]; + input clk_enable = clk_enable_io_div4_ffs[PIPELINE_DEPTH-1]; + endclocking + + logic [PIPELINE_DEPTH-1:0] clk_enable_io_div2_ffs; + logic [PIPELINE_DEPTH-1:0] ip_clk_en_io_div2_ffs; + always @(posedge clocks_o.clk_io_div2_powerup or negedge rst_io_n) begin + if (rst_io_n) begin + clk_enable_io_div2_ffs <= { + clk_enable_io_div2_ffs[PIPELINE_DEPTH-2:0], clk_enables_csr.io_div2_peri_en + }; + ip_clk_en_io_div2_ffs <= {ip_clk_en_io_div2_ffs[PIPELINE_DEPTH-2:0], pwr_i.io_ip_clk_en}; + end else begin + clk_enable_io_div2_ffs <= '0; + ip_clk_en_io_div2_ffs <= '0; + end + end + clocking peri_io_div2_cb @(posedge clocks_o.clk_io_div2_powerup or negedge rst_io_n); + input ip_clk_en = ip_clk_en_io_div2_ffs[PIPELINE_DEPTH-1]; + input clk_enable = clk_enable_io_div2_ffs[PIPELINE_DEPTH-1]; + endclocking + + // Pipelining and clocking block for transactional unit clocks. + logic [PIPELINE_DEPTH-1:0][NUM_TRANS-1:0] clk_hints_ffs; + logic [PIPELINE_DEPTH-1:0] trans_clk_en_ffs; + always @(posedge clocks_o.clk_main_powerup or negedge rst_main_n) begin + if (rst_main_n) begin + clk_hints_ffs <= {clk_hints_ffs[PIPELINE_DEPTH-2:0], clk_hints_csr}; + trans_clk_en_ffs <= {trans_clk_en_ffs[PIPELINE_DEPTH-2:0], pwr_i.main_ip_clk_en}; + end else begin + clk_hints_ffs <= '0; + trans_clk_en_ffs <= '0; + end + end + clocking trans_cb @(posedge clocks_o.clk_main_powerup or negedge rst_main_n); + input ip_clk_en = trans_clk_en_ffs[PIPELINE_DEPTH-1]; + input clk_hints = clk_hints_ffs[PIPELINE_DEPTH-1]; + input idle_i; + endclocking + + // Pipelining and clocking block for external clock bypass. The divisor control is + // triggered by an ast ack, which goes through synchronizers. + logic step_down_ff; + always @(posedge clk) begin + if (rst_n) begin + step_down_ff <= io_clk_byp_ack == prim_mubi_pkg::MuBi4True; + end else begin + step_down_ff <= 1'b0; + end + end + + clocking clk_cb @(posedge clk); + input calib_rdy; + input extclk_ctrl_csr_sel; + input extclk_ctrl_csr_step_down; + input lc_hw_debug_en_i; + input io_clk_byp_req; + input lc_clk_byp_req; + input step_down = step_down_ff; + input jitter_enable_csr; + endclocking + +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_scoreboard.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_scoreboard.sv new file mode 100644 index 00000000000..dcf3152e242 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_scoreboard.sv @@ -0,0 +1,354 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The scoreboard checks the jitter_an_o output, and processes CSR checks. +// It also samples most functional coverage groups. +class clkmgr_scoreboard extends cip_base_scoreboard #( + .CFG_T(clkmgr_env_cfg), + .RAL_T(clkmgr_reg_block), + .COV_T(clkmgr_env_cov) +); + `uvm_component_utils(clkmgr_scoreboard) + + // local variables + logic extclk_ctrl_regwen; + logic measure_ctrl_regwen; + + // TLM agent fifos + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + cfg.scoreboard = this; + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + fork + monitor_all_clk_byp(); + monitor_io_clk_byp(); + monitor_jitter_en(); + sample_peri_covs(); + sample_trans_covs(); + sample_freq_measurement_covs(); + sample_fatal_err_cov(); + sample_recov_err_cov(); + join_none + endtask + + task monitor_all_clk_byp(); + mubi4_t prev_all_clk_byp_req = MuBi4False; + forever + @cfg.clkmgr_vif.clk_cb begin + if (cfg.clkmgr_vif.all_clk_byp_req != prev_all_clk_byp_req) begin + `uvm_info(`gfn, $sformatf( + "Got all_clk_byp_req %s", + cfg.clkmgr_vif.all_clk_byp_req == MuBi4True ? "True" : "False" + ), UVM_MEDIUM) + prev_all_clk_byp_req = cfg.clkmgr_vif.all_clk_byp_req; + end + if (cfg.clk_rst_vif.rst_n) begin + if (cfg.en_cov) begin + cov.extclk_cg.sample(cfg.clkmgr_vif.clk_cb.extclk_ctrl_csr_sel == MuBi4True, + cfg.clkmgr_vif.clk_cb.extclk_ctrl_csr_step_down == MuBi4True, + cfg.clkmgr_vif.clk_cb.lc_hw_debug_en_i == On, + cfg.clkmgr_vif.clk_cb.lc_clk_byp_req == On, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + end + endtask + + task monitor_io_clk_byp(); + lc_tx_t prev_lc_clk_byp_req = Off; + forever + @cfg.clkmgr_vif.clk_cb begin + if (cfg.clkmgr_vif.lc_clk_byp_req != prev_lc_clk_byp_req) begin + `uvm_info(`gfn, $sformatf( + "Got lc_clk_byp_req %s", cfg.clkmgr_vif.lc_clk_byp_req == On ? "On" : "Off"), + UVM_MEDIUM) + prev_lc_clk_byp_req = cfg.clkmgr_vif.lc_clk_byp_req; + end + if (cfg.clk_rst_vif.rst_n) begin + if (cfg.en_cov) begin + cov.extclk_cg.sample(cfg.clkmgr_vif.clk_cb.extclk_ctrl_csr_sel == MuBi4True, + cfg.clkmgr_vif.clk_cb.extclk_ctrl_csr_step_down == MuBi4True, + cfg.clkmgr_vif.clk_cb.lc_hw_debug_en_i == On, + cfg.clkmgr_vif.clk_cb.lc_clk_byp_req == On, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + end + endtask + + task monitor_jitter_en(); + fork + forever + @cfg.clkmgr_vif.clk_cb begin + if (cfg.clk_rst_vif.rst_n) begin + @cfg.clkmgr_vif.jitter_enable_csr begin + cfg.clk_rst_vif.wait_clks(2); + `DV_CHECK_EQ(cfg.clkmgr_vif.jitter_en_o, cfg.clkmgr_vif.jitter_enable_csr, + "Mismatching jitter enable output") + end + end + end + forever + @cfg.clkmgr_vif.clk_cb begin + if (cfg.clk_rst_vif.rst_n) begin + @cfg.clkmgr_vif.jitter_en_o begin + cfg.clk_rst_vif.wait_clks(2); + `DV_CHECK_EQ(cfg.clkmgr_vif.jitter_en_o, cfg.clkmgr_vif.jitter_enable_csr, + "Mismatching jitter enable output") + end + end + end + join + endtask + + task sample_peri_covs(); + fork + forever + @cfg.clkmgr_vif.peri_io_div4_cb begin + if (cfg.io_clk_rst_vif.rst_n && cfg.en_cov) begin + cov.peri_cg_wrap[PeriIoDiv4].sample(cfg.clkmgr_vif.peri_io_div4_cb.clk_enable, + cfg.clkmgr_vif.peri_io_div4_cb.ip_clk_en, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + forever + @cfg.clkmgr_vif.peri_io_div2_cb begin + if (cfg.io_clk_rst_vif.rst_n && cfg.en_cov) begin + cov.peri_cg_wrap[PeriIoDiv2].sample(cfg.clkmgr_vif.peri_io_div2_cb.clk_enable, + cfg.clkmgr_vif.peri_io_div2_cb.ip_clk_en, + cfg.clkmgr_vif.scanmode_i == MuBi4True); + end + end + join + endtask + + task sample_trans_cov(int trans_index); + logic hint, clk_en, idle, src_rst_en; + trans_e trans = trans_e'(trans_index); + forever begin + @cfg.clkmgr_vif.trans_cb; + hint = cfg.clkmgr_vif.trans_cb.clk_hints[trans_index]; + idle = cfg.clkmgr_vif.trans_cb.idle_i[trans_index]; + clk_en = cfg.clkmgr_vif.trans_cb.ip_clk_en; + src_rst_en = cfg.main_clk_rst_vif.rst_n; + if (src_rst_en && cfg.en_cov) begin + logic scan_en = cfg.clkmgr_vif.scanmode_i == prim_mubi_pkg::MuBi4True; + cov.trans_cg_wrap[trans].sample(hint, clk_en, scan_en, idle); + end + end + endtask + + task sample_trans_covs(); + for (int i = 0; i < $bits(hintables_t); ++i) begin + fork + automatic int trans_index = i; + sample_trans_cov(trans_index); + join_none + end + endtask + + local task sample_freq_measurement_cov(clk_mesr_e clk, ref freq_measurement_t measurement, + logic timeout); + if (cfg.en_cov) begin + cov.freq_measure_cg_wrap[clk].sample(!measurement.slow && !measurement.fast, measurement.slow, + measurement.fast, timeout); + `uvm_info(`gfn, $sformatf( + "Cov for %0s: %0s", + clk.name(), + measurement.slow ? "slow" : measurement.fast ? "fast" : "okay" + ), UVM_MEDIUM) + measurement = '{default: 0}; + end + endtask + + task sample_freq_measurement_covs(); + fork + forever + @(posedge cfg.clkmgr_vif.io_div4_freq_measurement.valid or + posedge cfg.clkmgr_vif.io_div4_timeout_err) begin + sample_freq_measurement_cov(ClkMesrIoDiv4, cfg.clkmgr_vif.io_div4_freq_measurement, + cfg.clkmgr_vif.io_div4_timeout_err); + end + + forever + @(posedge cfg.clkmgr_vif.main_freq_measurement.valid or + posedge cfg.clkmgr_vif.main_timeout_err) begin + sample_freq_measurement_cov(ClkMesrMain, cfg.clkmgr_vif.main_freq_measurement, + cfg.clkmgr_vif.main_timeout_err); + end + + join_none + endtask + + task sample_recov_err_cov(); + fork + forever + @cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr if (cfg.en_cov) begin + cov.recov_err_cg.sample( + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[4], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[3], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[2], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[1], + cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr[0]); + `uvm_info(`gfn, $sformatf( + "Recoverable errors sampled: 0x%x", cfg.clkmgr_csrs_vif.csrs_cb.recov_err_csr), + UVM_MEDIUM) + end + join_none + endtask + + task sample_fatal_err_cov(); + fork + forever + @cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr if (cfg.en_cov) begin + cov.fatal_err_cg.sample( + cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr[2], + cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr[1], + cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr[0]); + `uvm_info(`gfn, $sformatf( + "Fatal errors sampled: 0x%x", cfg.clkmgr_csrs_vif.csrs_cb.fatal_err_csr), + UVM_MEDIUM) + end + join_none + endtask + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + string access_str = write ? "write" : "read"; + string channel_str = channel == AddrChannel ? "address" : "data"; + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // If incoming access is a write to a valid csr, update prediction right away. + if (addr_phase_write) begin + `uvm_info(`gfn, $sformatf("Writing 0x%0x to %s", item.a_data, csr.get_name()), UVM_MEDIUM) + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // Process the csr req: + // - For write, update local variable and fifo at address phase. + // - For read, update prediction at address phase and compare at data phase. + case (csr.get_name()) + // add individual case item for each csr + "alert_test": begin + // FIXME + end + "extclk_ctrl_regwen": begin + if (addr_phase_write) extclk_ctrl_regwen = item.a_data; + end + "extclk_ctrl": begin + typedef logic [2*$bits(prim_mubi_pkg::mubi4_t) - 1:0] extclk_ctrl_t; + if (addr_phase_write && extclk_ctrl_regwen) begin + `DV_CHECK_EQ(extclk_ctrl_t'(item.a_data), { + cfg.clkmgr_vif.extclk_ctrl_csr_step_down, cfg.clkmgr_vif.extclk_ctrl_csr_sel + }) + end + end + "extclk_status": begin + do_read_check = 1'b0; + end + "jitter_regwen": begin + end + "jitter_enable": begin + if (addr_phase_write && `gmv(ral.jitter_regwen)) begin + `DV_CHECK_EQ(prim_mubi_pkg::mubi4_t'(item.a_data), cfg.clkmgr_vif.jitter_enable_csr) + end + end + "clk_enables": begin + if (addr_phase_write) begin + `DV_CHECK_EQ(clk_enables_t'(item.a_data), cfg.clkmgr_vif.clk_enables_csr) + end + end + "clk_hints": begin + // Clearing a hint sets an expectation for the status to transition to zero. + if (addr_phase_write) begin + `DV_CHECK_EQ(clk_hints_t'(item.a_data), cfg.clkmgr_vif.clk_hints_csr) + end + end + "clk_hints_status": begin + // The status will respond to the hint once the target unit is idle. We check it in + // the sequence. + do_read_check = 1'b0; + end + "measure_ctrl_regwen": begin + if (addr_phase_write) measure_ctrl_regwen = item.a_data; + end + "io_meas_ctrl_en": begin + end + "io_div2_meas_ctrl_en": begin + end + "io_div4_meas_ctrl_en": begin + end + "main_meas_ctrl_en": begin + end + "io_meas_ctrl_shadowed": begin + end + "io_div2_meas_ctrl_shadowed": begin + end + "io_div4_meas_ctrl_shadowed": begin + end + "main_meas_ctrl_shadowed": begin + end + "recov_err_code": begin + do_read_check = 1'b0; + end + "fatal_err_code": begin + do_read_check = 1'b0; + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + `uvm_info(`gfn, $sformatf("Reading 0x%0x from %s", item.d_data, csr.get_name()), UVM_MEDIUM) + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, $sformatf( + "reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endtask + + virtual function void reset(string kind = "HARD"); + super.reset(kind); + // reset local fifos queues and variables + extclk_ctrl_regwen = ral.extclk_ctrl_regwen.get_reset(); + measure_ctrl_regwen = ral.measure_ctrl_regwen.get_reset(); + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_virtual_sequencer.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_virtual_sequencer.sv new file mode 100644 index 00000000000..8239de0df3a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/clkmgr_virtual_sequencer.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(clkmgr_env_cfg), + .COV_T(clkmgr_env_cov) +); + `uvm_component_utils(clkmgr_virtual_sequencer) + + + `uvm_component_new + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv new file mode 100644 index 00000000000..453063c086d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_base_vseq.sv @@ -0,0 +1,404 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +class clkmgr_base_vseq extends cip_base_vseq #( + .RAL_T (clkmgr_reg_block), + .CFG_T (clkmgr_env_cfg), + .COV_T (clkmgr_env_cov), + .VIRTUAL_SEQUENCER_T(clkmgr_virtual_sequencer) +); + + `uvm_object_utils(clkmgr_base_vseq) + `uvm_object_new + + // The extra cycles to wait after reset before starting any test, required so some CSRs (notably + // hints_status) are properly set when inputs go through synchronizers. + localparam int POST_APPLY_RESET_CYCLES = 10; + + // This delay is needed to allow updates to the idle inputs to go through synchronizers and + // counters. + localparam int IDLE_SYNC_CYCLES = 20; + + // This is the timeout for the various clk status outputs to react to their inputs. + localparam int CLK_STATUS_TIMEOUT_NS = 100_000; + + rand bit io_ip_clk_en; + rand bit main_ip_clk_en; + + rand mubi_hintables_t idle; + + // Override this from cip_base_vseq, since clkmgr tests are relatively short. + constraint rand_reset_delay_c { + rand_reset_delay dist { + [1 : 1000] :/ 1, + [1001 : 100_000] :/ 2, + [100_001 : 1_000_000] :/ 6 + }; + } + + mubi4_t scanmode; + int scanmode_on_weight = 8; + + mubi4_t extclk_ctrl_high_speed_sel; + mubi4_t extclk_ctrl_sel; + clkmgr_mubi_e mubi_mode; + + // This holds the necessary per measure control CSR info. + typedef struct { + string name; + dv_base_reg en; + dv_base_reg_field ctrl_hi; + dv_base_reg_field ctrl_lo; + } meas_ctrl_regs_t; + meas_ctrl_regs_t meas_ctrl_regs[clk_mesr_e]; + + virtual function void set_scanmode_on_low_weight(); + scanmode_on_weight = 2; + endfunction + + function void post_randomize(); + extclk_ctrl_high_speed_sel = get_rand_mubi4_val(6, 2, 2); + extclk_ctrl_sel = get_rand_mubi4_val(4, 2, 2); + scanmode = get_rand_mubi4_val(scanmode_on_weight, 4, 4); + `uvm_info(`gfn, $sformatf( + "randomize: extclk_ctrl_sel=0x%x, extclk_ctrl_high_speed_sel=0x%x, scanmode=0x%x", + extclk_ctrl_sel, + extclk_ctrl_high_speed_sel, + scanmode + ), UVM_MEDIUM) + super.post_randomize(); + endfunction + + virtual task initialize_on_start(); + `uvm_info(`gfn, "In clkmgr_if initialize_on_start", UVM_MEDIUM) + idle = {NUM_TRANS{MuBi4True}}; + scanmode = MuBi4False; + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode), .lc_debug_en(Off)); + io_ip_clk_en = 1'b1; + main_ip_clk_en = 1'b1; + start_ip_clocks(); + endtask + + // Converts to bool with strict true. + protected function hintables_t mubi_hintables_to_hintables(mubi_hintables_t mubi_hints); + hintables_t ret; + foreach (mubi_hints[i]) ret[i] = prim_mubi_pkg::mubi4_test_true_strict(mubi_hints[i]); + return ret; + endfunction + + local function void disable_unnecessary_exclusions(); + ral.get_excl_item().enable_excl("clkmgr_reg_block.clk_enables", 0); + ral.get_excl_item().enable_excl("clkmgr_reg_block.clk_hints", 0); + `uvm_info(`gfn, "Adjusted exclusions", UVM_MEDIUM) + ral.get_excl_item().print_exclusions(UVM_MEDIUM); + endfunction + + task pre_start(); + meas_ctrl_regs[ClkMesrIoDiv4] = '{"io_div4", ral.io_div4_meas_ctrl_en, + ral.io_div4_meas_ctrl_shadowed.hi, + ral.io_div4_meas_ctrl_shadowed.lo}; + meas_ctrl_regs[ClkMesrMain] = '{"main", ral.main_meas_ctrl_en, + ral.main_meas_ctrl_shadowed.hi, + ral.main_meas_ctrl_shadowed.lo}; + mubi_mode = ClkmgrMubiNone; + `DV_GET_ENUM_PLUSARG(clkmgr_mubi_e, mubi_mode, clkmgr_mubi_mode) + `uvm_info(`gfn, $sformatf("mubi_mode = %s", mubi_mode.name), UVM_MEDIUM) + cfg.clkmgr_vif.init(.idle({NUM_TRANS{MuBi4True}}), .scanmode(scanmode), .lc_debug_en(Off)); + cfg.clkmgr_vif.update_io_ip_clk_en(1'b1); + cfg.clkmgr_vif.update_main_ip_clk_en(1'b1); + cfg.clkmgr_vif.update_div_step_down_req(MuBi4False); + cfg.clkmgr_vif.update_io_clk_byp_ack(MuBi4False); + + disable_unnecessary_exclusions(); + clkmgr_init(); + super.pre_start(); + if (common_seq_type inside {"shadow_reg_errors", "shadow_reg_errors_with_csr_rw"}) begin + expect_fatal_alerts = 1; + end + endtask + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(reset_kind); + endtask + + virtual task dut_shutdown(); + // check for pending clkmgr operations and wait for them to complete + endtask + + // This turns on the actual input clocks, as the pwrmgr would. + task start_ip_clocks(); + fork + start_io_ip_clock(); + start_main_ip_clock(); + join + endtask + + task start_io_ip_clock(); + `uvm_info(`gfn, $sformatf( + "starting io clk_en with current status %b", cfg.clkmgr_vif.pwr_o.io_status), + UVM_MEDIUM) + cfg.io_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.io_ip_clk_en = io_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.io_status == 1'b1);, + "timeout waiting for io_status to raise", CLK_STATUS_TIMEOUT_NS) + `uvm_info(`gfn, "starting io clock done", UVM_MEDIUM) + endtask + + task start_main_ip_clock(); + `uvm_info(`gfn, $sformatf( + "starting main clk_en with current status %b", cfg.clkmgr_vif.pwr_o.main_status), + UVM_MEDIUM) + cfg.main_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.main_ip_clk_en = main_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.main_status == 1'b1);, + "timeout waiting for main_status to raise", CLK_STATUS_TIMEOUT_NS) + `uvm_info(`gfn, "starting main clock done", UVM_MEDIUM) + endtask + + // This turns on or off the actual input clocks, as the pwrmgr would. + task control_ip_clocks(); + fork + control_io_ip_clock(); + control_main_ip_clock(); + join + endtask + + task control_io_ip_clock(); + // Do nothing if nothing interesting changed. + if (cfg.clkmgr_vif.pwr_i.io_ip_clk_en == io_ip_clk_en) return; + `uvm_info(`gfn, $sformatf( + "controlling io clk_en from %b to %b with current status %b", + cfg.clkmgr_vif.pwr_i.io_ip_clk_en, + io_ip_clk_en, + cfg.clkmgr_vif.pwr_o.io_status + ), UVM_MEDIUM) + if (!io_ip_clk_en) begin + cfg.clkmgr_vif.pwr_i.io_ip_clk_en = io_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.io_status == 1'b0);, + "timeout waiting for io_status to fall", CLK_STATUS_TIMEOUT_NS) + cfg.io_clk_rst_vif.stop_clk(); + end else begin + cfg.io_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.io_ip_clk_en = io_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.io_status == 1'b1);, + "timeout waiting for io_status to raise", CLK_STATUS_TIMEOUT_NS) + end + `uvm_info(`gfn, "controlling io clock done", UVM_MEDIUM) + endtask + + task control_main_ip_clock(); + // Do nothing if nothing interesting changed. + if (cfg.clkmgr_vif.pwr_i.main_ip_clk_en == main_ip_clk_en) return; + `uvm_info(`gfn, $sformatf( + "controlling main clk_en from %b to %b with current status %b", + cfg.clkmgr_vif.pwr_i.main_ip_clk_en, + main_ip_clk_en, + cfg.clkmgr_vif.pwr_o.main_status + ), UVM_MEDIUM) + if (!main_ip_clk_en) begin + cfg.clkmgr_vif.pwr_i.main_ip_clk_en = main_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.main_status == 1'b0);, + "timeout waiting for main_status to fall", CLK_STATUS_TIMEOUT_NS) + cfg.main_clk_rst_vif.stop_clk(); + end else begin + cfg.main_clk_rst_vif.start_clk(); + cfg.clkmgr_vif.pwr_i.main_ip_clk_en = main_ip_clk_en; + `DV_SPINWAIT(wait(cfg.clkmgr_vif.pwr_o.main_status == 1'b1);, + "timeout waiting for main_status to raise", CLK_STATUS_TIMEOUT_NS) + end + `uvm_info(`gfn, "controlling main clock done", UVM_MEDIUM) + endtask + + task disable_frequency_measurement(clk_mesr_e which); + `uvm_info(`gfn, $sformatf("Disabling frequency measurement for %0s", which.name), UVM_MEDIUM) + csr_wr(.ptr(meas_ctrl_regs[which].en), .value(MuBi4False)); + endtask + + protected function int get_meas_ctrl_value(int min_threshold, int max_threshold, + uvm_reg_field lo, uvm_reg_field hi); + int lo_mask = (1 << lo.get_n_bits()) - 1; + int hi_mask = (1 << hi.get_n_bits()) - 1; + + int value = (((min_threshold & lo_mask) << lo.get_lsb_pos()) | + ((max_threshold & hi_mask) << hi.get_lsb_pos())); + return value; + endfunction + + // Any non-false mubi value in the enable CSR turns measurements on. + task enable_frequency_measurement(clk_mesr_e which, int min_threshold, int max_threshold); + int value = get_meas_ctrl_value(min_threshold, max_threshold, meas_ctrl_regs[which].ctrl_lo, + meas_ctrl_regs[which].ctrl_hi); + mubi4_t en_value = get_rand_mubi4_val(1, 0, 3); + `uvm_info(`gfn, $sformatf( + "Enabling frequency measurement for %0s, min=0x%x, max=0x%x, expected=0x%x", + which.name, + min_threshold, + max_threshold, + ExpectedCounts[which] + ), UVM_MEDIUM) + csr_wr(.ptr(meas_ctrl_regs[which].ctrl_lo.get_dv_base_reg_parent()), .value(value)); + csr_wr(.ptr(meas_ctrl_regs[which].en), .value(en_value)); + endtask + + // This checks that when calibration is lost regwen should be re-enabled and measurements + // disabled. + task calibration_lost_checks(); + void'(ral.measure_ctrl_regwen.predict(1)); + csr_rd_check(.ptr(ral.measure_ctrl_regwen), .compare_value(1)); + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + csr_rd_check(.ptr(meas_ctrl_regs[clk_mesr].en), .compare_value(MuBi4False)); + end + endtask + + function control_meas_saturation_assert(clk_mesr_e clk, bit enable); + `uvm_info(`gfn, $sformatf( + "%sabling MaxWidth_A assertion for %s", enable ? "En" : "Dis", clk.name), + UVM_MEDIUM) + case (clk) + ClkMesrIoDiv4: begin + if (enable) $asserton(0, "tb.dut.u_io_div4_meas.u_meas.MaxWidth_A"); + else $assertoff(0, "tb.dut.u_io_div4_meas.u_meas.MaxWidth_A"); + end + ClkMesrMain: begin + if (enable) $asserton(0, "tb.dut.u_main_meas.u_meas.MaxWidth_A"); + else $assertoff(0, "tb.dut.u_main_meas.u_meas.MaxWidth_A"); + end + default: `uvm_error(`gfn, $sformatf("unexpected clock index '%0d'", clk)) + endcase + endfunction + + local function void control_sync_pulse_assert(clk_mesr_e clk, bit enable); + case (clk) + ClkMesrIoDiv4: begin + if (enable) $asserton(0, "tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + else $assertoff(0, "tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + end + ClkMesrMain: begin + if (enable) $asserton(0, "tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + else $assertoff(0, "tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M"); + end + default: `uvm_error(`gfn, $sformatf("unexpected clock index '%0d'", clk)) + endcase + endfunction + + // This turns off/on some clocks being measured to trigger a measurement timeout. + // A side-effect is that some RTL assertions will fire, so they are corresponsdingly controlled. + task disturb_measured_clock(clk_mesr_e clk, bit enable); + case (clk) + ClkMesrIoDiv4: begin + `uvm_info(`gfn, $sformatf("%sabling %s clk", enable ? "En" : "Dis", "io"), + UVM_MEDIUM) + if (enable) cfg.io_clk_rst_vif.start_clk(); + else cfg.io_clk_rst_vif.stop_clk(); + control_sync_pulse_assert(.clk(ClkMesrIoDiv4), .enable(enable)); + end + ClkMesrMain: begin + `uvm_info(`gfn, $sformatf("%sabling %s clk", enable ? "En" : "Dis", "main"), + UVM_MEDIUM) + if (enable) cfg.main_clk_rst_vif.start_clk(); + else cfg.main_clk_rst_vif.stop_clk(); + control_sync_pulse_assert(.clk(ClkMesrMain), .enable(enable)); + end + default: `uvm_fatal(`gfn, $sformatf("Unexpected clk '%0d'", clk)) + endcase + endtask + + function void report_recov_error_mismatch(string error_type, recov_bits_t expected, + recov_bits_t actual); + recov_bits_t mismatch = actual ^ expected; + foreach (mismatch[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + if (mismatch[clk]) begin + `uvm_info(`gfn, $sformatf( + "Mismatch %0s for %0s, expected %b, actual %b", + error_type, + clk_mesr.name, + expected[clk], + actual[clk] + ), UVM_LOW) + end + end + `uvm_error(`gfn, $sformatf( + "Mismatch for %0s recoverable error, expected 0b%b, got 0b%b", + error_type, + expected, + actual + )) + endfunction + + // This is tricky, and we choose to handle it all here, not in "super": + // - there are no multiple clk_rst_vifs, + // - it would be too complicated to coordinate reset durations with super. + // For hard resets we also reset the cfg.root*_clk_rst_vif, and its reset is shorter than + // that of all others. + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + int clk_periods_q[$] = { + reset_duration_ps, + cfg.aon_clk_rst_vif.clk_period_ps, + cfg.io_clk_rst_vif.clk_period_ps, + cfg.io_div2_clk_rst_vif.clk_period_ps, + cfg.io_div4_clk_rst_vif.clk_period_ps, + cfg.main_clk_rst_vif.clk_period_ps + }; + reset_duration_ps = max(clk_periods_q); + + `uvm_info(`gfn, "In apply_resets_concurrently", UVM_MEDIUM) + cfg.clk_rst_vif.drive_rst_pin(0); + cfg.root_main_clk_rst_vif.drive_rst_pin(0); + cfg.root_io_clk_rst_vif.drive_rst_pin(0); + cfg.root_io_div2_clk_rst_vif.drive_rst_pin(0); + cfg.root_io_div4_clk_rst_vif.drive_rst_pin(0); + cfg.aon_clk_rst_vif.drive_rst_pin(0); + cfg.io_clk_rst_vif.drive_rst_pin(0); + cfg.io_div2_clk_rst_vif.drive_rst_pin(0); + cfg.io_div4_clk_rst_vif.drive_rst_pin(0); + cfg.main_clk_rst_vif.drive_rst_pin(0); + + #(reset_duration_ps * $urandom_range(2, 10) * 1ps); + cfg.root_main_clk_rst_vif.drive_rst_pin(1); + cfg.root_io_clk_rst_vif.drive_rst_pin(1); + cfg.root_io_div2_clk_rst_vif.drive_rst_pin(1); + cfg.root_io_div4_clk_rst_vif.drive_rst_pin(1); + `uvm_info(`gfn, "apply_resets_concurrently releases POR", UVM_MEDIUM) + + #(reset_duration_ps * $urandom_range(2, 10) * 1ps); + cfg.clk_rst_vif.drive_rst_pin(1); + cfg.aon_clk_rst_vif.drive_rst_pin(1); + cfg.io_clk_rst_vif.drive_rst_pin(1); + cfg.io_div2_clk_rst_vif.drive_rst_pin(1); + cfg.io_div4_clk_rst_vif.drive_rst_pin(1); + cfg.main_clk_rst_vif.drive_rst_pin(1); + `uvm_info(`gfn, "apply_resets_concurrently releases other resets", UVM_MEDIUM) + endtask + + virtual task apply_reset(string kind = "HARD"); + if (kind == "HARD") apply_resets_concurrently(); + else begin + fork + cfg.clk_rst_vif.apply_reset(); + cfg.aon_clk_rst_vif.apply_reset(); + cfg.io_clk_rst_vif.apply_reset(); + cfg.io_div2_clk_rst_vif.apply_reset(); + cfg.io_div4_clk_rst_vif.apply_reset(); + cfg.main_clk_rst_vif.apply_reset(); + join + end + endtask + + task post_apply_reset(string reset_kind = "HARD"); + super.post_apply_reset(reset_kind); + initialize_on_start(); + cfg.io_clk_rst_vif.wait_clks(POST_APPLY_RESET_CYCLES); + endtask + + // setup basic clkmgr features + virtual task clkmgr_init(); + // Initialize input clock frequencies. + cfg.main_clk_rst_vif.set_freq_mhz((1.0 * 1_000_000_000) / 1_000_000); + cfg.io_clk_rst_vif.set_freq_mhz((1.0 * 1_000_000_000) / 1_000_000); + // The real clock rate for aon is 200kHz, but that can slow testing down. + // Increasing its frequency improves DV efficiency without compromising quality. + cfg.aon_clk_rst_vif.set_freq_mhz((1.0 * FakeAonClkHz) / 1_000_000); + endtask +endclass : clkmgr_base_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_clk_status_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_clk_status_vseq.sv new file mode 100644 index 00000000000..f5850366aa9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_clk_status_vseq.sv @@ -0,0 +1,35 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This tests the transitions of the various clock status outputs for random settings of the +// various ip_clk_en inputs. +// +// The checks are done via SVA in clkmgr_pwrmgr_sva_if. +class clkmgr_clk_status_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_clk_status_vseq) + + `uvm_object_new + + function void post_randomize(); + super.post_randomize(); + // Disable scanmode since it is not interesting. + scanmode = prim_mubi_pkg::MuBi4False; + endfunction + + task body(); + for (int i = 0; i < num_trans; ++i) begin + cfg.clk_rst_vif.wait_clks(4); + `DV_CHECK_RANDOMIZE_FATAL(this) + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode)); + control_ip_clocks(); + + // If some units were not idle, make them so. + idle = '1; + // Wait for idle to percolate. + cfg.clk_rst_vif.wait_clks(10); + end + // And set it back to more common values for stress tests. + initialize_on_start(); + endtask : body +endclass : clkmgr_clk_status_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_common_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_common_vseq.sv new file mode 100644 index 00000000000..21613892f0b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_common_vseq.sv @@ -0,0 +1,70 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_common_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_common_vseq) + + constraint num_trans_c {num_trans inside {[1 : 2]};} + `uvm_object_new + + virtual task pre_start(); + csr_excl_item csr_excl = ral.get_excl_item(); + super.pre_start(); + + // Remove rw1c type from same_csr_outstanding + if (common_seq_type == "same_csr_outstanding") begin + csr_excl.add_excl("clkmgr_reg_block.recov_err_code", CsrExclWrite); + end + endtask + + virtual task body(); + run_common_vseq_wrapper(num_trans); + endtask : body + + virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy); + super.check_sec_cm_fi_resp(if_proxy); + + case (if_proxy.sec_cm_type) + SecCmPrimCount: begin + csr_rd_check(.ptr(ral.fatal_err_code.idle_cnt), .compare_value(1)); + end + default: begin + `uvm_error(`gfn, $sformatf("Unexpected sec_cm_type %0s", if_proxy.sec_cm_type.name)) + end + endcase + endtask + + task initialize_on_start(); + super.initialize_on_start(); + // update default idle to false for + // csr test. + cfg.clkmgr_vif.idle_i = {NUM_TRANS{MuBi4False}}; + endtask : initialize_on_start + + // This task is used for non-main clock registers. + // to compensate clock difference, wait longer until + // see get_alert() + task skid_check_fatal_alert_nonblocking(string alert_name); + fork + `DV_SPINWAIT_EXIT( + forever begin + // 1 extra cycle to make sure no race condition + repeat (alert_esc_agent_pkg::ALERT_B2B_DELAY + 20) begin + cfg.clk_rst_vif.wait_n_clks(1); + if (cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1) break; + end + `DV_CHECK_EQ(cfg.m_alert_agent_cfgs[alert_name].vif.get_alert(), 1, + $sformatf("fatal error %0s does not trigger!", alert_name)) + cfg.m_alert_agent_cfgs[alert_name].vif.wait_ack_complete(); + end, + wait(cfg.under_reset);) + join_none + endtask + + // Override shadow_reg_errors task + // to cover shadow regs under clock div2, div4 + task shadow_reg_errors_check_fatal_alert_nonblocking(dv_base_reg shadowed_csr, string alert_name); + skid_check_fatal_alert_nonblocking(alert_name); + endtask +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv new file mode 100644 index 00000000000..8962c11167c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_extclk_vseq.sv @@ -0,0 +1,241 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The extclk vseq causes the external clock selection to be triggered. More details +// in the clkmgr_testplan.hjson file. +class clkmgr_extclk_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_extclk_vseq) + + `uvm_object_new + + // When extclk_ctrl_regwen is clear it is not possible to select external clocks. + // This is tested in regular csr_rw, so here this register is simply set to 1. + + // The extclk cannot be manipulated in low power mode. + constraint io_ip_clk_en_on_c {io_ip_clk_en == 1;} + constraint main_ip_clk_en_on_c {main_ip_clk_en == 1;} + + + // This randomizes the time when the extclk_ctrl CSR write and the lc_clk_byp_req + // input is asserted for good measure. Of course, there is a good chance only a single + // one of these trigger a request, so they are also independently tested. + rand int cycles_before_extclk_ctrl_sel; + rand int cycles_before_lc_clk_byp_req; + rand int cycles_before_lc_clk_byp_ack; + rand int cycles_before_all_clk_byp_ack; + rand int cycles_before_div_step_down_req; + rand int cycles_before_io_clk_byp_ack; + rand int cycles_before_next_trans; + + rand int flips_before_io_clk_byp_ack; + rand int flips_before_div_step_down_req; + rand int flips_before_all_clk_byp_ack; + rand int cycles_between_flips; + + constraint cycles_to_stim_c { + cycles_before_extclk_ctrl_sel inside {[4 : 20]}; + cycles_before_lc_clk_byp_req inside {[4 : 20]}; + cycles_before_lc_clk_byp_ack inside {[16 : 30]}; + cycles_before_all_clk_byp_ack inside {[3 : 11]}; + cycles_before_div_step_down_req inside {[3 : 11]}; + cycles_before_io_clk_byp_ack inside {[3 : 11]}; + cycles_before_next_trans inside {[15 : 35]}; + flips_before_io_clk_byp_ack inside {[0 : 3]}; + flips_before_div_step_down_req inside {[0 : 3]}; + flips_before_all_clk_byp_ack inside {[0 : 3]}; + cycles_between_flips inside {[3 : 5]}; + } + + lc_tx_t lc_clk_byp_req; + lc_tx_t lc_debug_en; + mubi4_t io_clk_byp_ack_non_true; + mubi4_t all_clk_byp_ack_non_true; + mubi4_t div_step_down_req_non_true; + + mubi4_t exp_all_clk_byp_ack; + + function void post_randomize(); + if (mubi_mode == ClkmgrMubiLcHand) begin + // increase weight of illegal value only in ClkmgrMubiLcHand + lc_clk_byp_req = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(14)); + end else begin + lc_clk_byp_req = get_rand_lc_tx_val(.t_weight(8), .f_weight(2), .other_weight(2)); + end + if (mubi_mode == ClkmgrMubiLcCtrl) begin + // increase weight of illgal value only in ClkmgrMubiLcHand + lc_debug_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(14)); + end else begin + lc_debug_en = get_rand_lc_tx_val(.t_weight(8), .f_weight(2), .other_weight(2)); + end + + io_clk_byp_ack_non_true = get_rand_mubi4_val(.t_weight(0), .f_weight(2), .other_weight(8)); + all_clk_byp_ack_non_true = get_rand_mubi4_val(.t_weight(0), .f_weight(2), .other_weight(8)); + div_step_down_req_non_true = get_rand_mubi4_val(.t_weight(0), .f_weight(2), .other_weight(8)); + + `uvm_info(`gfn, $sformatf( + "randomize gives lc_clk_byp_req=0x%x, lc_debug_en=0x%x", lc_clk_byp_req, lc_debug_en), + UVM_MEDIUM) + super.post_randomize(); + + extclk_ctrl_sel = get_rand_mubi4_val(.t_weight(8), .f_weight(1), .other_weight(1)); + `uvm_info(`gfn, $sformatf("overwrite extclk_ctrl_sel=0x%x", extclk_ctrl_sel), UVM_MEDIUM) + + endfunction + + // Notice only all_clk_byp_req and io_clk_byp_req Mubi4True and Mubi4False cause transitions. + local task delayed_update_all_clk_byp_ack(mubi4_t value, int cycles); + uvm_reg_data_t rd_data; + + if (mubi_mode == ClkmgrMubiHand && value == MuBi4True) begin + repeat (flips_before_all_clk_byp_ack) begin + exp_all_clk_byp_ack = get_rand_mubi4_val(.t_weight(0), .f_weight(1), .other_weight(1)); + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + cfg.clkmgr_vif.update_all_clk_byp_ack(exp_all_clk_byp_ack); + cfg.clk_rst_vif.wait_clks(4); + csr_rd(.ptr(ral.extclk_status), .value(rd_data)); + // csr_rd_check didn't work well for status register read check + `DV_CHECK_EQ(exp_all_clk_byp_ack, rd_data, "extclk_status mismatch") + end + end + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + cfg.clkmgr_vif.update_all_clk_byp_ack(value); + endtask + + local task delayed_update_div_step_down_req(mubi4_t value, int cycles); + if (mubi_mode == ClkmgrMubiDiv && value == MuBi4True) begin + repeat (flips_before_div_step_down_req) begin + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + cfg.clkmgr_vif.update_div_step_down_req(get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1))); + end + end + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + `uvm_info(`gfn, $sformatf("Settling div_step_down_req to 0x%x", value), UVM_MEDIUM) + cfg.clkmgr_vif.update_div_step_down_req(value); + endtask + + local task delayed_update_io_clk_byp_ack(mubi4_t value, int cycles); + if (mubi_mode == ClkmgrMubiHand && value == MuBi4True) begin + repeat (flips_before_io_clk_byp_ack) begin + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + cfg.clkmgr_vif.update_io_clk_byp_ack(get_rand_mubi4_val( + .t_weight(0), .f_weight(1), .other_weight(1))); + end + end + cfg.clk_rst_vif.wait_clks(cycles_between_flips); + `uvm_info(`gfn, $sformatf("Settling io_clk_byp_ack to 0x%x", value), UVM_MEDIUM) + cfg.clkmgr_vif.update_io_clk_byp_ack(value); + endtask + + local task all_clk_byp_handshake(); + forever + @cfg.clkmgr_vif.all_clk_byp_req begin : all_clk_byp_ack + if (cfg.clkmgr_vif.all_clk_byp_req == prim_mubi_pkg::MuBi4True) begin + `uvm_info(`gfn, "Got all_clk_byp_req on", UVM_MEDIUM) + fork + delayed_update_all_clk_byp_ack(MuBi4True, cycles_before_all_clk_byp_ack); + delayed_update_div_step_down_req(MuBi4True, cycles_before_div_step_down_req); + join + end else begin + `uvm_info(`gfn, "Got all_clk_byp_req off", UVM_MEDIUM) + // Set inputs to mubi4 non-True. + fork + delayed_update_all_clk_byp_ack(all_clk_byp_ack_non_true, cycles_before_all_clk_byp_ack); + delayed_update_div_step_down_req(div_step_down_req_non_true, + cycles_before_div_step_down_req); + join + end + end + endtask + + local task io_clk_byp_handshake(); + forever + @cfg.clkmgr_vif.io_clk_byp_req begin : io_clk_byp_ack + if (cfg.clkmgr_vif.io_clk_byp_req == MuBi4True) begin + `uvm_info(`gfn, "Got io_clk_byp_req True", UVM_MEDIUM) + fork + delayed_update_io_clk_byp_ack(MuBi4True, cycles_before_io_clk_byp_ack); + delayed_update_div_step_down_req(MuBi4True, cycles_before_div_step_down_req); + join + end else begin + `uvm_info(`gfn, "Got io_clk_byp_req non True", UVM_MEDIUM) + // Set inputs to mubi4 non-True. + fork + delayed_update_io_clk_byp_ack(io_clk_byp_ack_non_true, cycles_before_io_clk_byp_ack); + delayed_update_div_step_down_req(div_step_down_req_non_true, + cycles_before_div_step_down_req); + join + end + end + endtask + + local task lc_clk_byp_handshake(); + forever + @cfg.clkmgr_vif.lc_clk_byp_ack begin : lc_clk_byp_ack + if (cfg.clkmgr_vif.lc_clk_byp_ack == lc_ctrl_pkg::On) begin + `uvm_info(`gfn, "Got lc_clk_byp_ack on", UVM_MEDIUM) + end + end + endtask + + local task run_test(); + for (int i = 0; i < num_trans; ++i) begin + `DV_CHECK_RANDOMIZE_FATAL(this) + // Init needs to be synchronous. + @cfg.clk_rst_vif.cb begin + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode), .lc_debug_en(lc_debug_en)); + control_ip_clocks(); + end + fork + begin + cfg.clk_rst_vif.wait_clks(cycles_before_extclk_ctrl_sel); + csr_wr(.ptr(ral.extclk_ctrl), .value({extclk_ctrl_high_speed_sel, extclk_ctrl_sel})); + end + begin + cfg.clk_rst_vif.wait_clks(cycles_before_lc_clk_byp_req); + cfg.clkmgr_vif.update_lc_clk_byp_req(lc_clk_byp_req); + end + join + `uvm_info(`gfn, $sformatf( + { + "extclk_ctrl_sel=0x%0x, extclk_ctrl_high_speed_sel=0x%0x, lc_clk_byp_req=0x%0x, ", + "lc_debug_en=0x%0x, scanmode=0x%0x" + }, + extclk_ctrl_sel, + extclk_ctrl_high_speed_sel, + lc_clk_byp_req, + lc_debug_en, + scanmode + ), UVM_MEDIUM) + csr_rd_check(.ptr(ral.extclk_ctrl), + .compare_value({extclk_ctrl_high_speed_sel, extclk_ctrl_sel})); + if (lc_clk_byp_req == lc_ctrl_pkg::On) begin + wait(cfg.clkmgr_vif.lc_clk_byp_req == lc_ctrl_pkg::On); + cfg.clk_rst_vif.wait_clks(cycles_before_lc_clk_byp_ack); + cfg.clkmgr_vif.update_lc_clk_byp_req(lc_ctrl_pkg::Off); + end + // Disable extclk software control. + csr_wr(.ptr(ral.extclk_ctrl), .value({Off, Off})); + cfg.clk_rst_vif.wait_clks(cycles_before_next_trans); + end + endtask + + task body(); + set_scanmode_on_low_weight(); + csr_wr(.ptr(ral.extclk_ctrl_regwen), .value(1)); + + fork + begin : isolation_fork + fork + all_clk_byp_handshake(); + io_clk_byp_handshake(); + lc_clk_byp_handshake(); + run_test(); + join_any + disable fork; + end + join + endtask + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_timeout_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_timeout_vseq.sv new file mode 100644 index 00000000000..f8ba7a72af2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_timeout_vseq.sv @@ -0,0 +1,137 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The frequency timeout vseq exercises the frequency measurement counters. More details +// in the clkmgr_testplan.hjson file. +class clkmgr_frequency_timeout_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_frequency_timeout_vseq) + + `uvm_object_new + + // This is measured in aon clocks. We need to have a few rounds of measurement for timeouts to + // trigger, since they synchronize to the aon clock, and they wait for a few number of AON + // cycles before declaring a timeout. + localparam int CyclesToGetOneMeasurement = 12; + + // If cause_timeout is set, turn off clk_timeout so it gets a timeout. + rand bit cause_timeout; + constraint cause_timeout_c { + cause_timeout dist { + 1 := 4, + 0 := 1 + }; + } + rand clk_mesr_e clk_timeout; + constraint clk_timeout_c {clk_timeout != ClkMesrSize;} + + constraint all_clk_en_c { + io_ip_clk_en == 1; + main_ip_clk_en == 1; + } + + // The clock that will be disabled. + clk_mesr_e clk_mesr_timeout; + + // This waits a number of AON cycles so that the timeout can get detected. + task wait_before_read_recov_err_code(); + cfg.aon_clk_rst_vif.wait_clks(CyclesToGetOneMeasurement); + endtask + + // Get things back in normal order. + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + super.apply_resets_concurrently(reset_duration_ps); + if (cause_timeout) disturb_measured_clock(.clk(clk_mesr_timeout), .enable(1'b1)); + endtask + + task body(); + logic [TL_DW-1:0] value; + int prior_alert_count; + int current_alert_count; + csr_wr(.ptr(ral.measure_ctrl_regwen), .value(1)); + + // Make sure the aon clock is running as slow as it is meant to. + cfg.aon_clk_rst_vif.set_freq_khz(AonClkHz / 1_000); + control_ip_clocks(); + // Wait so the frequency change takes effect. + cfg.aon_clk_rst_vif.wait_clks(2); + + // Disable cip scoreboard exp_alert checks since they need very fine control, making checks + // really cumbersome. Instead we rely on the alert count to detect if alert were triggered. + cfg.scoreboard.do_alert_check = 0; + + `uvm_info(`gfn, $sformatf("Will run %0d rounds", num_trans), UVM_MEDIUM) + for (int i = 0; i < num_trans; ++i) begin + clkmgr_recov_err_t actual_recov_err = '{default: '0}; + logic [ClkMesrSize-1:0] expected_recov_timeout_err = '0; + bit expect_alert = 0; + `DV_CHECK_RANDOMIZE_FATAL(this) + `uvm_info(`gfn, "New round", UVM_MEDIUM) + + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + int min_threshold; + int max_threshold; + int expected = ExpectedCounts[clk]; + min_threshold = expected - 2; + max_threshold = expected + 2; + enable_frequency_measurement(clk_mesr, min_threshold, max_threshold); + end + + prior_alert_count = cfg.scoreboard.get_alert_count("recov_fault"); + // Allow some cycles for measurements to start before turning off the clocks, since the + // measurement control CSRs are controlled by the clocks we intend to stop. + cfg.aon_clk_rst_vif.wait_clks(4); + clk_mesr_timeout = clk_mesr_e'(clk_timeout); + + if (cause_timeout) begin + `uvm_info(`gfn, $sformatf("Will cause a timeout for clk %0s", clk_mesr_timeout.name()), + UVM_MEDIUM) + if (clk_mesr_timeout inside {ClkMesrIoDiv4}) begin + expected_recov_timeout_err[ClkMesrIoDiv4] = 1; + end else begin + expected_recov_timeout_err[clk_mesr_timeout] = 1; + end + disturb_measured_clock(.clk(clk_mesr_timeout), .enable(1'b0)); + end + wait_before_read_recov_err_code(); + if (cause_timeout) begin + disturb_measured_clock(.clk(clk_mesr_e'(clk_timeout)), .enable(1'b1)); + end + csr_rd(.ptr(ral.recov_err_code), .value(actual_recov_err)); + `uvm_info(`gfn, $sformatf("Got recov err register=0x%x", actual_recov_err), UVM_MEDIUM) + if (actual_recov_err.measures) begin + report_recov_error_mismatch("measurement", recov_bits_t'(0), actual_recov_err.measures); + end + if (!cfg.under_reset && actual_recov_err.timeouts != expected_recov_timeout_err) begin + report_recov_error_mismatch("timeout", expected_recov_timeout_err, + actual_recov_err.timeouts); + end + if (actual_recov_err.shadow_update != 0) begin + `uvm_error(`gfn, "Unexpected recoverable shadow update error") + end + // And check that the alert count increased if there was a timeout. + current_alert_count = cfg.scoreboard.get_alert_count("recov_fault"); + if (cause_timeout) begin + if (!cfg.under_reset) begin + `DV_CHECK_NE(current_alert_count, prior_alert_count, "expected some alerts to fire") + end + end else begin + `DV_CHECK_EQ(current_alert_count, prior_alert_count, "expected no alerts to fire") + end + + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + disable_frequency_measurement(clk_mesr); + end + + // Wait enough time for measurements to complete, and for alerts to get processed + // by the alert agents so expected alerts are properly wound down. + cfg.aon_clk_rst_vif.wait_clks(6); + // And clear errors. + csr_wr(.ptr(ral.recov_err_code), .value('1)); + cfg.aon_clk_rst_vif.wait_clks(2); + end + endtask : body + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_vseq.sv new file mode 100644 index 00000000000..6de89b71602 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_frequency_vseq.sv @@ -0,0 +1,248 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The frequency vseq exercises the frequency measurement counters. More details +// in the clkmgr_testplan.hjson file. +class clkmgr_frequency_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_frequency_vseq) + + `uvm_object_new + + // This is measured in aon clocks. This is cannot be too precise because of a synchronizer. + // It takes into account cases where some clocks need multiple aon clock cycles to get + // a measurement. + localparam int CyclesToGetMeasurements = 37; + + // The aon cycles between measurements, to make sure the previous measurement settles. + localparam int CyclesBetweenMeasurements = 37; + + // This is measured in clkmgr clk_i clocks. It is set to cover worst case delays. + // The clk_i frequency is randomized for IPs, but the clkmgr is hooked to io_div4, which would + // allow a tighter number of cycles. Leaving the clk_i random probably provides more cases, + // so leaving it as is. + localparam int CyclesForErrUpdate = 16; + + // The min ands max offsets from the expected counts. Notice the count occasionally matches + // expected_counts +- 2 because of CDC synchronizers, so the offsets are set carefully to + // avoid spurious results. + // + // The exp_alert cip feature requires a single alert at a time, so we set at most one of the + // clocks to fail measurement. + rand clk_mesr_e clk_tested; + constraint clk_tested_c {clk_tested != ClkMesrSize;} + + // If cause_saturation is active, force the initial measurement count of clk_tested to a high + // value so the counter will saturate. + rand bit cause_saturation; + + typedef enum int { + MesrLow, + MesrRight, + MesrHigh + } mesr_e; + rand mesr_e mesr; + rand int min_offset; + rand int max_offset; + + mubi4_t calib_rdy; + + constraint thresholds_c { + solve clk_tested before mesr; + solve mesr before min_offset, max_offset; + if (mesr == MesrLow) { + min_offset inside {[-5 : -3]}; + max_offset inside {[-5 : -3]}; + min_offset <= max_offset; + } else + if (mesr == MesrRight) { + min_offset == -2; + max_offset == 2; + } else + if (mesr == MesrHigh) { + min_offset inside {[3 : 5]}; + max_offset inside {[3 : 5]}; + min_offset <= max_offset; + } + } + + constraint all_clk_en_c { + io_ip_clk_en == 1; + main_ip_clk_en == 1; + } + + function void post_randomize(); + calib_rdy = get_rand_mubi4_val(6, 2, 2); + `uvm_info(`gfn, $sformatf("randomize: calib_rdy=0x%x", calib_rdy), UVM_MEDIUM) + super.post_randomize(); + endfunction + + // Keep saturating the count on aon negedges if needed. + local task maybe_saturate_count(bit saturate, clk_mesr_e clk_tested); + forever begin + @cfg.aon_clk_rst_vif.cbn; + if (saturate) begin + cfg.clkmgr_vif.force_high_starting_count(clk_mesr_e'(clk_tested)); + end + end + endtask + + // This waits a number of cycles so that: + // - at least one measurement completes, and, + // - the measurement has had time to update the recov_err_code CSR. + task wait_before_read_recov_err_code(bit expect_alert); + // Wait for one measurement (takes an extra cycle to really start). + cfg.aon_clk_rst_vif.wait_clks(CyclesToGetMeasurements); + // Wait for the result to propagate to the recov_err_code CSR. + cfg.clk_rst_vif.wait_clks(CyclesForErrUpdate); + endtask + + // If clocks become uncalibrated measure_ctrl_regwen is re-enabled. + task check_measure_ctrl_regwen_for_calib_rdy(); + logic value; + csr_wr(.ptr(ral.measure_ctrl_regwen), .value(0)); + cfg.clkmgr_vif.update_calib_rdy(MuBi4False); + cfg.clk_rst_vif.wait_clks(20); + calibration_lost_checks(); + endtask + + task body(); + logic [TL_DW-1:0] value; + int prior_alert_count; + int current_alert_count; + + csr_wr(.ptr(ral.measure_ctrl_regwen), .value(1)); + + // Disable alert checks since we cannot make sure a single alert will fire: there is too + // much uncertainty on the cycles for one measurement to complete due to synchronizers. + // This test will instead check whether alerts fire using the alert count. + cfg.scoreboard.do_alert_check = 0; + + // Make sure the aon clock is running as slow as it is meant to. + cfg.aon_clk_rst_vif.set_freq_khz(AonClkHz / 1_000); + control_ip_clocks(); + // Wait so the frequency change takes effect. + cfg.aon_clk_rst_vif.wait_clks(2); + + // Set the thresholds to get no error. + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + enable_frequency_measurement(clk_mesr, ExpectedCounts[clk] - 2, ExpectedCounts[clk] + 2); + end + wait_before_read_recov_err_code('0); + csr_rd_check(.ptr(ral.recov_err_code), .compare_value('0), + .err_msg("Expected no measurement errors")); + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + disable_frequency_measurement(clk_mesr); + end + cfg.aon_clk_rst_vif.wait_clks(CyclesBetweenMeasurements); + // And clear errors. + csr_wr(.ptr(ral.recov_err_code), .value('1)); + + `uvm_info(`gfn, $sformatf("Will run %0d rounds", num_trans), UVM_MEDIUM) + for (int i = 0; i < num_trans; ++i) begin + clkmgr_recov_err_t actual_recov_err = '{default: '0}; + logic [ClkMesrSize-1:0] expected_recov_meas_err = '0; + bit expect_alert = 0; + `DV_CHECK_RANDOMIZE_FATAL(this) + // Update calib_rdy input: if calibration is not ready the measurements + // don't happen, so we should not get faults. + cfg.clkmgr_vif.update_calib_rdy(calib_rdy); + `uvm_info(`gfn, $sformatf( + "Updating calib_rdy to 0x%x, predicted regwen 0x%x", + calib_rdy, + ral.measure_ctrl_regwen.get() + ), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("New round targetting %s", clk_tested), UVM_MEDIUM) + // Allow calib_rdy to generate side-effects. + cfg.clk_rst_vif.wait_clks(3); + if (calib_rdy == MuBi4False) calibration_lost_checks(); + prior_alert_count = cfg.scoreboard.get_alert_count("recov_fault"); + if (cause_saturation) begin + `uvm_info(`gfn, $sformatf( + "Will cause saturation for %s so disable measurement assertions", + clk_tested.name()), UVM_MEDIUM) + control_meas_saturation_assert(clk_tested, 0); + end + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + int min_threshold; + int max_threshold; + int expected = ExpectedCounts[clk]; + if (clk == clk_tested) begin + min_threshold = expected + min_offset; + max_threshold = expected + max_offset; + if (calib_rdy != MuBi4False && + (min_threshold > expected || max_threshold < expected - 1 || cause_saturation)) begin + `uvm_info(`gfn, $sformatf( + "Expect %0s to get a %0s error%0s", + clk_mesr.name, + (cause_saturation ? "fast" : (min_threshold > expected ? "slow" : "fast")), + (cause_saturation ? " due to saturation" : "") + ), UVM_MEDIUM) + expect_alert = 1; + expected_recov_meas_err[clk] = 1; + end + end else begin + min_threshold = expected - 2; + max_threshold = expected + 2; + end + enable_frequency_measurement(clk_mesr, min_threshold, max_threshold); + end + + fork + begin : wait_for_measurements + fork + maybe_saturate_count(cause_saturation, clk_mesr_e'(clk_tested)); + wait_before_read_recov_err_code(expect_alert); + join_any + disable fork; + end + join + + csr_rd(.ptr(ral.recov_err_code), .value(actual_recov_err)); + `uvm_info(`gfn, $sformatf("Expected recov err register=0x%x", expected_recov_meas_err), + UVM_MEDIUM) + if (!cfg.under_reset && actual_recov_err.measures != expected_recov_meas_err) begin + report_recov_error_mismatch("measurement", expected_recov_meas_err, + actual_recov_err.measures); + end + if (actual_recov_err.timeouts != '0) begin + `uvm_error(`gfn, $sformatf( + "Unexpected recoverable timeout error 0b%b", actual_recov_err.timeouts)) + end + if (actual_recov_err.shadow_update != 0) begin + `uvm_error(`gfn, "Unexpected recoverable shadow update error") + end + // Check alerts. + current_alert_count = cfg.scoreboard.get_alert_count("recov_fault"); + if (expect_alert) begin + if (!cfg.under_reset) begin + `DV_CHECK_NE(current_alert_count, prior_alert_count, "expected some alerts to fire") + end + end else begin + `DV_CHECK_EQ(current_alert_count, prior_alert_count, "expected no alerts to fire") + end + + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + disable_frequency_measurement(clk_mesr); + end + + // Wait enough time for measurements to complete, and for alerts to get processed + // by the alert agents so expected alerts are properly wound down. + cfg.aon_clk_rst_vif.wait_clks(CyclesBetweenMeasurements); + if (cause_saturation) begin + `uvm_info(`gfn, "Enable measurement assertions", UVM_MEDIUM) + control_meas_saturation_assert(clk_tested, 1); + end + // And clear errors. + csr_wr(.ptr(ral.recov_err_code), .value('1)); + cfg.aon_clk_rst_vif.wait_clks(12); + end + // And finally, check that unsetting calib_rdy causes meaesure_ctrl_regwen to be set to 1. + check_measure_ctrl_regwen_for_calib_rdy(); + endtask + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv new file mode 100644 index 00000000000..15203e58caf --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_peri_vseq.sv @@ -0,0 +1,50 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the control of the peripheral clocks using clk_enables CSR. +// +// This is more general than the corresponding smoke test since it randomizes the initial +// value of clk_enables CSR and the ip_clk_en input. +// +// The expectation is that the peripheral clocks will be sampled at their rate, so this +// sequence needs to wait for the slowest clock to tick before changing enable values. +// The dv environment sets the CSRs clock frequency randomly, so it may run too fast and +// the updates may become a glitch that ends up not sampled in the SVAs. +// To be safe this waits for two cycles of the slowest clock (io_div_4) which is eight +// io_clk cycles. + +class clkmgr_peri_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_peri_vseq) + + `uvm_object_new + + // IO clock cycles to wait before changing clk enable settings. + static int WaitIoCycles = 8; + + rand peri_enables_t initial_enables; + + // The clk_enables CSR cannot be manipulated in low power mode. + // ICEBOX(#17963) randomize the usb clk enable if there is one. + constraint io_ip_clk_en_on_c {io_ip_clk_en == 1;} + constraint main_ip_clk_en_on_c {main_ip_clk_en == 1;} + + task body(); + for (int i = 0; i < num_trans; ++i) begin + peri_enables_t flipped_enables; + `DV_CHECK_RANDOMIZE_FATAL(this) + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode)); + control_ip_clocks(); + csr_wr(.ptr(ral.clk_enables), .value(initial_enables)); + + cfg.io_clk_rst_vif.wait_clks(WaitIoCycles); + // Flip all bits of clk_enables. + flipped_enables = initial_enables ^ ((1 << ral.clk_enables.get_n_bits()) - 1); + csr_wr(.ptr(ral.clk_enables), .value(flipped_enables)); + cfg.io_clk_rst_vif.wait_clks(WaitIoCycles); + end + // And set it back to the reset value for stress tests. + cfg.clk_rst_vif.wait_clks(1); + csr_wr(.ptr(ral.clk_enables), .value(ral.clk_enables.get_reset())); + endtask : body +endclass : clkmgr_peri_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv new file mode 100644 index 00000000000..2f34d3bcde5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv @@ -0,0 +1,101 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The regwen vseq attempts to write to registers whose regwen is randomly on or off to check +// the register contents is not updated when off. More details in the clkmgr_testplan.hjson file. +class clkmgr_regwen_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_regwen_vseq) + + `uvm_object_new + + task check_jitter_regwen(); + bit enable; + mubi4_t prev_value; + mubi4_t new_value; + + `DV_CHECK_STD_RANDOMIZE_FATAL(enable) + new_value = get_rand_mubi4_val(.t_weight(1), .f_weight(1), .other_weight(2)); + `uvm_info(`gfn, $sformatf("Check jitter_regwen = %b", enable), UVM_MEDIUM) + csr_wr(.ptr(ral.jitter_regwen), .value(enable)); + csr_rd(.ptr(ral.jitter_enable), .value(prev_value)); + csr_wr(.ptr(ral.jitter_enable), .value(new_value)); + csr_rd_check(.ptr(ral. jitter_enable), .compare_value(enable ? new_value : prev_value)); + `uvm_info(`gfn, "Check jitter_regwen done", UVM_MEDIUM) + endtask : check_jitter_regwen + + task check_extclk_regwen(); + bit enable; + int prev_value; + int new_value = {extclk_ctrl_high_speed_sel, extclk_ctrl_sel}; + `DV_CHECK_STD_RANDOMIZE_FATAL(enable) + `uvm_info(`gfn, $sformatf("Check extclk_ctrl regwen = %b", enable), UVM_MEDIUM) + csr_wr(.ptr(ral.extclk_ctrl_regwen), .value(enable)); + csr_rd(.ptr(ral.extclk_ctrl), .value(prev_value)); + csr_wr(.ptr(ral.extclk_ctrl), .value(new_value)); + csr_rd_check(.ptr(ral.extclk_ctrl), .compare_value(enable ? new_value : prev_value)); + `uvm_info(`gfn, "Check extclk_ctrl regwen done", UVM_MEDIUM) + endtask : check_extclk_regwen + + // This must be careful to turn measurements off right after checking the updates + // to avoid measurement errors. We could set the thresholds correctly, but we + // might as well set them randomly for good measure. Carefully masks only the + // real bits for the comparison. + task check_meas_ctrl_regwen(); + bit regwen_enable; + `DV_CHECK_STD_RANDOMIZE_FATAL(regwen_enable) + csr_wr(.ptr(ral.measure_ctrl_regwen), .value(regwen_enable)); + foreach (ExpectedCounts[clk]) begin + clk_mesr_e clk_mesr = clk_mesr_e'(clk); + uvm_reg ctrl_shadowed = meas_ctrl_regs[clk_mesr].ctrl_lo.get_dv_base_reg_parent(); + uvm_reg_data_t prev_en; + mubi4_t new_en = get_rand_mubi4_val(1, 1, 2); + int prev_ctrl; + int max_threshold = ExpectedCounts[clk] + 2; + int min_threshold = ExpectedCounts[clk] - 2; + int new_ctrl = get_meas_ctrl_value(min_threshold, max_threshold, + meas_ctrl_regs[clk_mesr].ctrl_lo, meas_ctrl_regs[clk_mesr].ctrl_hi); + int actual_ctrl; + int lo_mask = ((1 << meas_ctrl_regs[clk_mesr].ctrl_lo.get_n_bits()) - 1) << + meas_ctrl_regs[clk_mesr].ctrl_lo.get_lsb_pos(); + int hi_mask = ((1 << meas_ctrl_regs[clk_mesr].ctrl_hi.get_n_bits()) - 1) << + meas_ctrl_regs[clk_mesr].ctrl_hi.get_lsb_pos(); + `uvm_info(`gfn, $sformatf( + "Check %0s regwen = %b", meas_ctrl_regs[clk_mesr].name, regwen_enable), + UVM_MEDIUM) + csr_rd(.ptr(meas_ctrl_regs[clk_mesr].en), .value(prev_en)); + csr_rd(.ptr(ctrl_shadowed), .value(prev_ctrl)); + csr_wr(.ptr(ctrl_shadowed), .value(new_ctrl)); + csr_wr(.ptr(meas_ctrl_regs[clk_mesr].en), .value(new_en)); + csr_rd_check(.ptr(meas_ctrl_regs[clk_mesr].en), + .compare_value(mubi4_t'(regwen_enable ? new_en : prev_en))); + csr_wr(.ptr(meas_ctrl_regs[clk_mesr].en), .value(MuBi4False)); + csr_rd_check(.ptr(ctrl_shadowed), .compare_value(regwen_enable ? new_ctrl : prev_ctrl), + .compare_mask(lo_mask | hi_mask)); + `uvm_info(`gfn, $sformatf("Check %0s regwen done", meas_ctrl_regs[clk_mesr].name), + UVM_MEDIUM) + end + endtask : check_meas_ctrl_regwen + + task body(); + // Make sure the aon clock is running as slow as it is meant to, otherwise the aon clock + // runs fast enough that we could end up triggering faults due to the random settings for + // the thresholds. + cfg.aon_clk_rst_vif.set_freq_khz(AonClkHz / 1_000); + + `uvm_info(`gfn, $sformatf("Will run %0d rounds", num_trans), UVM_MEDIUM) + for (int i = 0; i < num_trans; ++i) begin + check_jitter_regwen(); + check_extclk_regwen(); + check_meas_ctrl_regwen(); + apply_reset("HARD"); + // This is to make sure we don't start writes immediately after reset, + // otherwise the tl_agent could mistakenly consider the following read + // happens during reset. + cfg.clk_rst_vif.wait_clks(4); + csr_rd_check(.ptr(ral.extclk_ctrl_regwen), .compare_value(1)); + csr_rd_check(.ptr(ral.measure_ctrl_regwen), .compare_value(1)); + end + endtask : body + +endclass : clkmgr_regwen_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv new file mode 100644 index 00000000000..32a3dc315e9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_smoke_vseq.sv @@ -0,0 +1,107 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// smoke test vseq +class clkmgr_smoke_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_smoke_vseq) + + `uvm_object_new + + constraint io_ip_clk_en_on_c {io_ip_clk_en == 1'b1;} + constraint main_ip_clk_en_on_c {main_ip_clk_en == 1'b1;} + constraint all_busy_c {idle == IdleAllBusy;} + + task body(); + cfg.clk_rst_vif.wait_clks(10); + test_jitter(); + test_peri_clocks(); + test_trans_clocks(); + endtask : body + + // Simply flip the jitter enable CSR. The side-effects are checked in the scoreboard. + // This needs to be done outside the various CSR tests, since they update the jitter_enable + // CSR, but the scoreboard is disabled for those tests. + task test_jitter(); + prim_mubi_pkg::mubi4_t jitter_value; + for (int i = 0; i < (1 << $bits(prim_mubi_pkg::mubi4_t)); ++i) begin + jitter_value = prim_mubi_pkg::mubi4_t'(i); + csr_wr(.ptr(ral.jitter_enable), .value(jitter_value)); + csr_rd_check(.ptr(ral.jitter_enable), .compare_value(jitter_value)); + // And set it back. + cfg.clk_rst_vif.wait_clks(6); + csr_wr(.ptr(ral.jitter_enable), .value('0)); + csr_rd_check(.ptr(ral.jitter_enable), .compare_value('0)); + end + endtask + + // Flips all clk_enables bits from the reset value with all enabled. All is checked + // via assertions in clkmgr_if.sv and behavioral code in the scoreboard. + task test_peri_clocks(); + // Flip all bits of clk_enables. + peri_enables_t value = ral.clk_enables.get(); + peri_enables_t flipped_value; + csr_rd(.ptr(ral.clk_enables), .value(value)); + flipped_value = value ^ ((1 << ral.clk_enables.get_n_bits()) - 1); + csr_wr(.ptr(ral.clk_enables), .value(flipped_value)); + + // And set it back to the reset value for stress tests. + cfg.clk_rst_vif.wait_clks(1); + csr_wr(.ptr(ral.clk_enables), .value(ral.clk_enables.get_reset())); + endtask : test_peri_clocks + + // Starts with all units busy, and for each one this clears the hint and reads the hint status, + // expecting it to remain at 1 since the unit is busy; then it sets the corresponding idle bit + // and reads status again, expecting it to be low. + // + // We disable the value checks when reset is active since the reads return unpredictable data. + task test_trans_clocks(); + trans_e trans; + logic bit_value; + logic [TL_DW-1:0] value; + mubi_hintables_t idle; + hintables_t bool_idle; + typedef struct { + trans_e unit; + uvm_reg_field hint_bit; + uvm_reg_field value_bit; + } trans_descriptor_t; + trans_descriptor_t trans_descriptors[NUM_TRANS] = '{ + '{TransAes, ral.clk_hints.clk_main_aes_hint, ral.clk_hints_status.clk_main_aes_val}, + '{TransHmac, ral.clk_hints.clk_main_hmac_hint, ral.clk_hints_status.clk_main_hmac_val}, + '{TransKmac, ral.clk_hints.clk_main_kmac_hint, ral.clk_hints_status.clk_main_kmac_val}, + '{TransOtbn, ral.clk_hints.clk_main_otbn_hint, ral.clk_hints_status.clk_main_otbn_val} + }; + idle = 0; + // Changes in idle take at least 10 cycles to stick. + cfg.clkmgr_vif.update_idle(idle); + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + + trans = trans.first; + csr_rd(.ptr(ral.clk_hints), .value(value)); + `uvm_info(`gfn, $sformatf("Starting hints at 0x%0x, idle at 0x%x", value, idle), UVM_MEDIUM) + do begin + trans_descriptor_t descriptor = trans_descriptors[int'(trans)]; + `uvm_info(`gfn, $sformatf("Clearing %s hint bit", descriptor.unit.name), UVM_MEDIUM) + csr_wr(.ptr(descriptor.hint_bit), .value(1'b0)); + csr_rd(.ptr(descriptor.value_bit), .value(bit_value)); + if (!cfg.under_reset) begin + `DV_CHECK_EQ(bit_value, 1'b1, $sformatf( + "%s hint value cannot drop while busy", descriptor.unit.name())) + end + `uvm_info(`gfn, $sformatf("Setting %s idle bit", descriptor.unit.name), UVM_MEDIUM) + cfg.clk_rst_vif.wait_clks(1); + idle[trans] = prim_mubi_pkg::MuBi4True; + cfg.clkmgr_vif.update_idle(idle); + // Some cycles for the logic to settle. + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + csr_rd(.ptr(descriptor.value_bit), .value(bit_value)); + if (!cfg.under_reset) begin + `DV_CHECK_EQ(bit_value, 1'b0, $sformatf( + "%s hint value should drop when idle", descriptor.unit.name())) + end + trans = trans.next(); + end while (trans != trans.first); + csr_wr(.ptr(ral.clk_hints), .value(ral.clk_hints.get_reset())); + endtask : test_trans_clocks +endclass : clkmgr_smoke_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_stress_all_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_stress_all_vseq.sv new file mode 100644 index 00000000000..c8e0aa5860a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_stress_all_vseq.sv @@ -0,0 +1,44 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all clkmgr seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +class clkmgr_stress_all_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_stress_all_vseq) + + `uvm_object_new + + task body(); + string seq_names[] = { + "clkmgr_extclk_vseq", + "clkmgr_frequency_timeout_vseq", + "clkmgr_frequency_vseq", + "clkmgr_peri_vseq", + "clkmgr_smoke_vseq", + "clkmgr_trans_vseq" + }; + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + clkmgr_base_vseq clkmgr_vseq; + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(clkmgr_vseq, seq) + + // if upper seq disables do_apply_reset for this seq, then can't issue reset + // as upper seq may drive reset + if (do_apply_reset) clkmgr_vseq.do_apply_reset = $urandom_range(0, 1); + else clkmgr_vseq.do_apply_reset = 0; + clkmgr_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(clkmgr_vseq) + `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, clkmgr_vseq.get_name()), + UVM_MEDIUM) + + clkmgr_vseq.start(p_sequencer); + `uvm_info(`gfn, $sformatf( + "End of sequence %0s with seq_idx = %0d", clkmgr_vseq.get_name(), seq_idx), + UVM_MEDIUM) + end + endtask : body +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv new file mode 100644 index 00000000000..95597dd7b3c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_trans_vseq.sv @@ -0,0 +1,95 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// trans test vseq +// This is a more randomized version of the corresponding test in the smoke sequence. +// Starts with random units busy, set the hints at random. The idle units whose hint bit is off +// will be disabled, but the others will remain enabled. Then all units are made idle to check +// that status matches hints. Prior to the next round this raises all hints so all unit clocks are +// running. +// +// Transitions to turn off the clock only go through if idle is asserted for at least 10 main +// cycles, and there is additional synchronizer overhead. +// +// The checks for whether each unit's clock are running are done in SVA. This sequence only +// explicitly checks hints_status. + +class clkmgr_trans_vseq extends clkmgr_base_vseq; + `uvm_object_utils(clkmgr_trans_vseq) + + `uvm_object_new + + rand hintables_t initial_hints; + + // The clk_hints CSR cannot be manipulated in low power mode. + constraint io_ip_clk_en_on_c {io_ip_clk_en == 1'b1;} + constraint main_ip_clk_en_on_c {main_ip_clk_en == 1'b1;} + + task body(); + for (int i = 0; i < num_trans; ++i) begin + logic bit_value; + hintables_t value; + hintables_t bool_idle; + + `DV_CHECK_RANDOMIZE_FATAL(this) + + csr_rd(.ptr(ral.clk_hints_status), .value(value)); + + `uvm_info(`gfn, $sformatf("Initial clk_hints_status: %b", value), UVM_MEDIUM) + cfg.clkmgr_vif.init(.idle(idle), .scanmode(scanmode)); + + // add random value if mubi idle test + if (mubi_mode == ClkmgrMubiIdle) drive_idle(idle); + print_mubi_hintable(idle); + control_ip_clocks(); + `uvm_info(`gfn, $sformatf("Idle = 0x%x", cfg.clkmgr_vif.idle_i), UVM_MEDIUM) + cfg.clk_rst_vif.wait_clks(10); + `uvm_info(`gfn, $sformatf("Updating hints to 0x%0x", initial_hints), UVM_MEDIUM) + csr_wr(.ptr(ral.clk_hints), .value(initial_hints)); + + // Extra wait because of synchronizers plus counters. + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + // We expect the status to be determined by hints and idle, ignoring scanmode. + bool_idle = mubi_hintables_to_hintables(idle); + value = initial_hints | ~bool_idle; + csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(value), + .err_msg($sformatf( + "Busy units have status high: hints=0x%x, idle=0x%x", + initial_hints, + bool_idle + ))); + + // Setting all idle should make hint_status match hints. + `uvm_info(`gfn, "Setting all units idle", UVM_MEDIUM) + cfg.clkmgr_vif.update_idle({NUM_TRANS{MuBi4True}}); + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + + csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(initial_hints), + .err_msg("All idle: expect status matches hints")); + + // Now set all hints, and the status should also be all ones. + value = '1; + csr_wr(.ptr(ral.clk_hints), .value(value)); + cfg.clk_rst_vif.wait_clks(IDLE_SYNC_CYCLES); + // We expect all units to be on. + csr_rd_check(.ptr(ral.clk_hints_status), .compare_value(value), + .err_msg("All idle and all hints high: units status should be high")); + + // Set hints to the reset value for stress tests. + csr_wr(.ptr(ral.clk_hints), .value(ral.clk_hints.get_reset())); + end + endtask : body + + task drive_idle(ref mubi_hintables_t tbl); + int period; + mubi_hintables_t rand_idle; + foreach (rand_idle[i]) + rand_idle[i] = get_rand_mubi4_val(.t_weight(0), .f_weight(0), .other_weight(1)); + + @cfg.clkmgr_vif.trans_cb; + cfg.clkmgr_vif.idle_i = rand_idle; + + tbl = rand_idle; + endtask : drive_idle +endclass : clkmgr_trans_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_vseq_list.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_vseq_list.sv new file mode 100644 index 00000000000..c125df499f2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_vseq_list.sv @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "clkmgr_base_vseq.sv" +`include "clkmgr_clk_status_vseq.sv" +`include "clkmgr_common_vseq.sv" +`include "clkmgr_frequency_timeout_vseq.sv" +`include "clkmgr_frequency_vseq.sv" +`include "clkmgr_extclk_vseq.sv" +`include "clkmgr_peri_vseq.sv" +`include "clkmgr_regwen_vseq.sv" +`include "clkmgr_smoke_vseq.sv" +`include "clkmgr_stress_all_vseq.sv" +`include "clkmgr_trans_vseq.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_aon_cg_en_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_aon_cg_en_sva_if.sv new file mode 100644 index 00000000000..9e0bcbf7e1e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_aon_cg_en_sva_if.sv @@ -0,0 +1,10 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for clock gating output to alert_handler for +// AON clocks: they are never gated off. +interface clkmgr_aon_cg_en_sva_if (input logic cg_en); + + `ASSERT_INIT_NET(CgEn_A, !cg_en) +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv new file mode 100644 index 00000000000..aec9d7ef5a3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_bind.sv @@ -0,0 +1,294 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module clkmgr_bind; +`ifndef GATE_LEVEL + bind clkmgr tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); + + // In top-level testbench, do not bind the csr_assert_fpv to reduce simulation time. +`ifndef TOP_LEVEL_DV + bind clkmgr clkmgr_csr_assert_fpv clkmgr_csr_assert (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); +`endif + + bind clkmgr clkmgr_pwrmgr_sva_if #(.IS_USB(0)) clkmgr_pwrmgr_main_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_i.main_ip_clk_en), + .status(pwr_o.main_status) + ); + + bind clkmgr clkmgr_pwrmgr_sva_if #(.IS_USB(0)) clkmgr_pwrmgr_io_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_i.io_ip_clk_en), + .status(pwr_o.io_status) + ); + + bind clkmgr clkmgr_gated_clock_sva_if clkmgr_io_div4_peri_sva_if ( + .clk(clocks_o.clk_io_div4_powerup), + .rst_n(rst_io_div4_ni), + .ip_clk_en(pwr_i.io_ip_clk_en), + .sw_clk_en(clk_io_div4_peri_sw_en), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .gated_clk(clocks_o.clk_io_div4_peri) + ); + + bind clkmgr clkmgr_gated_clock_sva_if clkmgr_io_div2_peri_sva_if ( + .clk(clocks_o.clk_io_div2_powerup), + .rst_n(rst_io_div2_ni), + .ip_clk_en(pwr_i.io_ip_clk_en), + .sw_clk_en(clk_io_div2_peri_sw_en), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .gated_clk(clocks_o.clk_io_div2_peri) + ); + + // Assertions for transactional clocks. + bind clkmgr clkmgr_trans_sva_if clkmgr_aes_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_aes_hint.q), + .idle(idle_i[HintMainAes] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_aes_val.d), + .trans_clk(clocks_o.clk_main_aes) + ); + + bind clkmgr clkmgr_trans_sva_if clkmgr_hmac_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_hmac_hint.q), + .idle(idle_i[HintMainHmac] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_hmac_val.d), + .trans_clk(clocks_o.clk_main_hmac) + ); + + bind clkmgr clkmgr_trans_sva_if clkmgr_kmac_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_kmac_hint.q), + .idle(idle_i[HintMainKmac] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_kmac_val.d), + .trans_clk(clocks_o.clk_main_kmac) + ); + + bind clkmgr clkmgr_trans_sva_if clkmgr_otbn_trans_sva_if ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .hint(reg2hw.clk_hints.clk_main_otbn_hint.q), + .idle(idle_i[HintMainOtbn] == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True), + .status(hw2reg.clk_hints_status.clk_main_otbn_val.d), + .trans_clk(clocks_o.clk_main_otbn) + ); + + bind clkmgr clkmgr_extclk_sva_if clkmgr_extclk_sva_if ( + .clk_i, + .rst_ni, + .extclk_ctrl_sel, + .extclk_ctrl_hi_speed_sel, + .lc_hw_debug_en_i, + .lc_clk_byp_req_i, + .io_clk_byp_req_o, + .all_clk_byp_req_o, + .hi_speed_sel_o + ); + + bind clkmgr clkmgr_div_sva_if #( + .DIV(2) + ) clkmgr_div2_sva_if ( + .clk(clocks_o.clk_io_powerup), + .rst_n(rst_ni), + .maybe_divided_clk(clocks_o.clk_io_div2_powerup), + .div_step_down_req_i(div_step_down_req_i == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True) + ); + + // The div2 clk also steps, so not a good reference. Instead, check it always tracks io_div2. + bind clkmgr clkmgr_div_sva_if #( + .DIV(4) + ) clkmgr_div4_sva_if ( + .clk(clocks_o.clk_io_div2_powerup), + .rst_n(rst_ni), + .maybe_divided_clk(clocks_o.clk_io_div4_powerup), + .div_step_down_req_i(div_step_down_req_i == prim_mubi_pkg::MuBi4True), + .scanmode(scanmode_i == prim_mubi_pkg::MuBi4True) + ); + + // AON clock gating enables. + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_infra ( + .cg_en(cg_en_o.aon_infra == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_peri ( + .cg_en(cg_en_o.aon_peri == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_powerup ( + .cg_en(cg_en_o.aon_powerup == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_aon_timers ( + .cg_en(cg_en_o.aon_timers == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_io_div2_powerup ( + .cg_en(cg_en_o.io_div2_powerup == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_io_div4_powerup ( + .cg_en(cg_en_o.io_div4_powerup == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_io_powerup ( + .cg_en(cg_en_o.io_powerup == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_aon_cg_en_sva_if clkmgr_aon_cg_main_powerup ( + .cg_en(cg_en_o.main_powerup == prim_mubi_pkg::MuBi4True) + ); + + // Non-AON clock gating enables with no software control. + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_infra ( + .clk(clk_io_div4), + .rst_n(rst_io_div4_ni), + .ip_clk_en(clk_io_div4_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div4_infra == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_secure ( + .clk(clk_io_div4), + .rst_n(rst_io_div4_ni), + .ip_clk_en(clk_io_div4_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div4_secure == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_timers ( + .clk(clk_io_div4), + .rst_n(rst_io_div4_ni), + .ip_clk_en(clk_io_div4_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div4_timers == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_infra ( + .clk(clk_main), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_infra == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_secure ( + .clk(clk_main), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(1'b1), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_secure == prim_mubi_pkg::MuBi4True) + ); + + // Software controlled gating enables. + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div4_peri ( + .clk(clk_io_div4), + .rst_n(rst_io_div4_ni), + .ip_clk_en(clk_io_div4_en), + .sw_clk_en(clk_io_div4_peri_sw_en), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div4_peri == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_io_div2_peri ( + .clk(clk_io_div2), + .rst_n(rst_io_div2_ni), + .ip_clk_en(clk_io_div2_en), + .sw_clk_en(clk_io_div2_peri_sw_en), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.io_div2_peri == prim_mubi_pkg::MuBi4True) + ); + + // Hint controlled gating enables. + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_aes ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_aes_trans.sw_hint_synced || !u_clk_main_aes_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_aes == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_hmac ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_hmac_trans.sw_hint_synced || !u_clk_main_hmac_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_hmac == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_kmac ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_kmac_trans.sw_hint_synced || !u_clk_main_kmac_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_kmac == prim_mubi_pkg::MuBi4True) + ); + + bind clkmgr clkmgr_cg_en_sva_if clkmgr_cg_main_otbn ( + .clk(clk_main_i), + .rst_n(rst_main_ni), + .ip_clk_en(clk_main_en), + .sw_clk_en(u_clk_main_otbn_trans.sw_hint_synced || !u_clk_main_otbn_trans.idle_valid), + .scanmode(prim_mubi_pkg::MuBi4False), + .cg_en(cg_en_o.main_otbn == prim_mubi_pkg::MuBi4True) + ); + + // Calibration assertions. + bind clkmgr clkmgr_lost_calib_regwen_sva_if clkmgr_lost_calib_regwen_sva_if ( + .clk(clk_i), + .rst_n(rst_ni), + .calib_rdy(calib_rdy_i), + .meas_ctrl_regwen(u_reg.measure_ctrl_regwen_qs) + ); + + bind clkmgr clkmgr_lost_calib_ctrl_en_sva_if clkmgr_lost_calib_io_div4_ctrl_en_sva_if ( + .clk(clk_i), + .rst_n(rst_ni), + .calib_rdy(calib_rdy_i), + .meas_ctrl_en(u_reg.io_div4_meas_ctrl_en_qs) + ); + + bind clkmgr clkmgr_lost_calib_ctrl_en_sva_if clkmgr_lost_calib_main_ctrl_en_sva_if ( + .clk(clk_i), + .rst_n(rst_ni), + .calib_rdy(calib_rdy_i), + .meas_ctrl_en(u_reg.main_meas_ctrl_en_qs) + ); + + bind clkmgr clkmgr_sec_cm_checker_assert clkmgr_sec_cm_checker_assert ( + .clk_i, + .rst_ni, + .all_clk_byp_req_o, + .lc_hw_debug_en_i, + .lc_clk_byp_req_i, + .lc_clk_byp_ack_o, + .io_clk_byp_req_o, + // internal signal is picked due to inconsistent t->f, f->t delay + .io_clk_byp_ack(u_clkmgr_byp.io_clk_byp_ack), + // internal signal is picked due to inconsistent input to signal delay + .step_down_acks_sync(u_clkmgr_byp.step_down_acks_sync), + .extclk_ctrl_sel + ); +`endif +endmodule : clkmgr_bind diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_cg_en_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_cg_en_sva_if.sv new file mode 100644 index 00000000000..e995057c8e9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_cg_en_sva_if.sv @@ -0,0 +1,30 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for clock gating output to alert_handler. +// - cg_en corresponds to clock gating enabled, which means the clock is gated, +// thus inactive. +// - ip_clk_en and sw_clk_en have the opposite polarity: when they are active +// the clock is enabled. +interface clkmgr_cg_en_sva_if + import prim_mubi_pkg::*; +( + input logic clk, + input logic rst_n, + input logic ip_clk_en, + input logic sw_clk_en, + input prim_mubi_pkg::mubi4_t scanmode, + input logic cg_en +); + + bit disable_sva; + + logic clk_enable; + always_comb clk_enable = ip_clk_en && sw_clk_en; + + `ASSERT(CgEnOn_A, $fell(clk_enable) |=> ##[0:2] clk_enable || cg_en, clk, + !rst_n || scanmode == prim_mubi_pkg::MuBi4True || disable_sva) + `ASSERT(CgEnOff_A, $rose(clk_enable) |=> ##[0:2] !clk_enable || !cg_en, clk, + !rst_n || scanmode == prim_mubi_pkg::MuBi4True || disable_sva) +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_div_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_div_sva_if.sv new file mode 100644 index 00000000000..acf04088004 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_div_sva_if.sv @@ -0,0 +1,68 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for clock dividers. +// - For div2 (DIV == 2) the reference clk is io clock, which is never stepped. +// So when step_down check that the divided clock tracks the reference. This +// means we check at negedge, or we would see nothing interesting. +// - For div4 (DIV == 4) the reference clk is io_div2 clock, which is also stepped. +// So check it is always twice as slow, except during transitions. +// +// All checks at negedges for simplicity. +interface clkmgr_div_sva_if #( + parameter int DIV = 2 +) ( + input logic clk, + input logic rst_n, + input logic maybe_divided_clk, + input logic div_step_down_req_i, + input logic scanmode +); + + localparam int WAIT_CYCLES = 20; + logic step_down; + always_comb step_down = div_step_down_req_i && !scanmode; + + logic step_up; + always_comb step_up = !step_down; + + sequence WholeLeadHigh_S; + step_down || maybe_divided_clk ##1 step_down || !maybe_divided_clk; + endsequence + + sequence WholeLeadLow_S; + step_down || !maybe_divided_clk ##1 step_down || maybe_divided_clk; + endsequence + + if (DIV == 2) begin : g_div2 + + sequence TracksClk_S; step_up || maybe_divided_clk ##1 step_up || maybe_divided_clk; endsequence + + // Notice this fires at negedges, since maybe_divided_clk's value will be on when + // tracking. + `ASSERT(Div2Stepped_A, $rose(step_down) ##1 step_down [* WAIT_CYCLES] |-> TracksClk_S, !clk, + !rst_n) + `ASSERT(Div2Whole_A, + $fell(step_down) ##1 !step_down [* WAIT_CYCLES] |-> WholeLeadLow_S or WholeLeadHigh_S, + !clk, !rst_n) + + end else begin : g_div4 + + sequence StepLeadHigh_S; + step_up || maybe_divided_clk ##1 step_up || !maybe_divided_clk; + endsequence + + sequence StepLeadLow_S; + step_up || !maybe_divided_clk ##1 step_up || maybe_divided_clk; + endsequence + + `ASSERT(Div4Stepped_A, + $rose(step_down) ##1 step_down [* WAIT_CYCLES] |-> StepLeadLow_S or StepLeadHigh_S, + !clk, !rst_n) + `ASSERT(Div4Whole_A, + $fell(step_down) ##1 !step_down [* WAIT_CYCLES] |-> WholeLeadLow_S or WholeLeadHigh_S, + !clk, !rst_n) + + end +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_extclk_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_extclk_sva_if.sv new file mode 100644 index 00000000000..ab505f527c6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_extclk_sva_if.sv @@ -0,0 +1,81 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions to check the external clock bypass control outputs. +// +// Notice when a condition fails we allow the logic to generate non strict mubi values. Ideally it +// would generate mubi False: see https://github.com/lowRISC/opentitan/issues/11400. +interface clkmgr_extclk_sva_if + import prim_mubi_pkg::*, lc_ctrl_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input mubi4_t extclk_ctrl_sel, + input mubi4_t extclk_ctrl_hi_speed_sel, + input lc_tx_t lc_hw_debug_en_i, + input lc_tx_t lc_clk_byp_req_i, + input mubi4_t io_clk_byp_req_o, + input mubi4_t all_clk_byp_req_o, + input mubi4_t hi_speed_sel_o +); + + // The times are to cover the clock domain synchronizers. + localparam int FallCyclesMin = 1; + localparam int FallCyclesMax = 3; + + localparam int RiseCyclesMin = 1; + localparam int RiseCyclesMax = 3; + + bit disable_sva; + + // Check lc_clk_byp_req_i triggers io_clk_byp_req_o. + logic lc_clk_byp_req; + always_comb lc_clk_byp_req = lc_clk_byp_req_i == On; + + `ASSERT(IoClkBypReqRise_A, + $rose( + lc_clk_byp_req + ) |=> ##[RiseCyclesMin:RiseCyclesMax] !lc_clk_byp_req || (io_clk_byp_req_o == MuBi4True), + clk_i, !rst_ni || disable_sva) + `ASSERT(IoClkBypReqFall_A, + $fell( + lc_clk_byp_req + ) |=> ##[FallCyclesMin:FallCyclesMax] lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False), + clk_i, !rst_ni || disable_sva) + + // Check extclk_ctrl triggers all_clk_byp_req_o and hi_speed_sel_o. + logic extclk_sel_enabled; + always_comb extclk_sel_enabled = extclk_ctrl_sel == MuBi4True && lc_hw_debug_en_i == On; + + `ASSERT(AllClkBypReqRise_A, + $rose( + extclk_sel_enabled + ) |=> ##[RiseCyclesMin:RiseCyclesMax] + !extclk_sel_enabled || (all_clk_byp_req_o == MuBi4True), + clk_i, !rst_ni || disable_sva) + `ASSERT(AllClkBypReqFall_A, + $fell( + extclk_sel_enabled + ) |=> ##[FallCyclesMin:FallCyclesMax] + extclk_sel_enabled || (all_clk_byp_req_o != MuBi4True), + clk_i, !rst_ni || disable_sva) + + logic hi_speed_enabled; + always_comb begin + hi_speed_enabled = extclk_ctrl_sel == MuBi4True && extclk_ctrl_hi_speed_sel == MuBi4True && + lc_hw_debug_en_i == On; + end + + `ASSERT(HiSpeedSelRise_A, + $rose( + hi_speed_enabled + ) |=> ##[RiseCyclesMin:RiseCyclesMax] !hi_speed_enabled || (hi_speed_sel_o == MuBi4True), + clk_i, !rst_ni || disable_sva) + `ASSERT(HiSpeedSelFall_A, + $fell( + hi_speed_enabled + ) |=> ##[FallCyclesMin:FallCyclesMax] hi_speed_enabled || (hi_speed_sel_o != MuBi4True), + clk_i, !rst_ni || disable_sva) + +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_gated_clock_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_gated_clock_sva_if.sv new file mode 100644 index 00000000000..2d532f86130 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_gated_clock_sva_if.sv @@ -0,0 +1,26 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for gated clocks. +interface clkmgr_gated_clock_sva_if ( + input logic clk, + input logic rst_n, + input logic ip_clk_en, + input logic sw_clk_en, + input logic scanmode, + input logic gated_clk +); + // This fires at negedges: if the gated clock is inactive its value is expected to be low, + // and viceversa. The assertions pass if clk_enabled is not stable to avoid cycle accuracy, and + // these gated clocks are expected to be changed infrequently. + logic clk_enabled; + always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode; + + `ASSERT(GateOpen_A, + $rose(clk_enabled) |=> ##[0:3] !clk_enabled || $changed(clk_enabled) || gated_clk, !clk, + !rst_n) + `ASSERT(GateClose_A, + $fell(clk_enabled) |=> ##[0:3] clk_enabled || $changed(clk_enabled) || !gated_clk, !clk, + !rst_n) +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_ctrl_en_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_ctrl_en_sva_if.sv new file mode 100644 index 00000000000..4b67cd01e62 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_ctrl_en_sva_if.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions to check losing calibration turns off clock measurements. + +interface clkmgr_lost_calib_ctrl_en_sva_if ( + input logic clk, + input logic rst_n, + input logic [$bits(prim_mubi_pkg::mubi4_t)-1:0] calib_rdy, + input logic [$bits(prim_mubi_pkg::mubi4_t)-1:0] meas_ctrl_en +); + // There are two clocks involved, the clock measured and the clkmgr clk_i. + // The latter is io_div4 so it is pretty slow compared to all others. There + // are a number of clock domain crossings, so this needs a large number of + // wait cycles to account for the worst case. + localparam int MAX_CYCLES = 45; + `ASSERT(CtrlEnOn_A, + (calib_rdy == prim_mubi_pkg::MuBi4False && meas_ctrl_en != prim_mubi_pkg::MuBi4False) |=> + ##[0:MAX_CYCLES] (meas_ctrl_en == prim_mubi_pkg::MuBi4False), + clk, !rst_n) +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_regwen_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_regwen_sva_if.sv new file mode 100644 index 00000000000..47bbf710f60 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_lost_calib_regwen_sva_if.sv @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions to check losing calibration enables crtl regwen. + +interface clkmgr_lost_calib_regwen_sva_if ( + input logic clk, + input logic rst_n, + input prim_mubi_pkg::mubi4_t calib_rdy, + input logic meas_ctrl_regwen +); + localparam int MAX_CYCLES = 6; + `ASSERT(RegwenOff_A, + (calib_rdy == prim_mubi_pkg::MuBi4False) |=> ##[0:MAX_CYCLES] meas_ctrl_regwen, clk, + !rst_n) +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_sec_cm_checker_assert.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_sec_cm_checker_assert.sv new file mode 100644 index 00000000000..567e26076a8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_sec_cm_checker_assert.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Assertion checker for external clock bypass +// sec cm test +module clkmgr_sec_cm_checker_assert ( + input clk_i, + input rst_ni, + input prim_mubi_pkg::mubi4_t all_clk_byp_req_o, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input lc_ctrl_pkg::lc_tx_t lc_clk_byp_req_i, + input lc_ctrl_pkg::lc_tx_t lc_clk_byp_ack_o, + input prim_mubi_pkg::mubi4_t io_clk_byp_req_o, + input prim_mubi_pkg::mubi4_t io_clk_byp_ack, + input logic [1:0] step_down_acks_sync, + input prim_mubi_pkg::mubi4_t extclk_ctrl_sel +); + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_ni || disable_sva; + + // sec_cm_lc_ctrl_intersig_mubi + `ASSERT(AllClkBypReqTrue_A, + lc_hw_debug_en_i == lc_ctrl_pkg::On && extclk_ctrl_sel == prim_mubi_pkg::MuBi4True |=> + all_clk_byp_req_o == prim_mubi_pkg::MuBi4True, + clk_i, reset_or_disable) + `ASSERT(AllClkBypReqFalse_A, + lc_hw_debug_en_i != lc_ctrl_pkg::On || extclk_ctrl_sel != prim_mubi_pkg::MuBi4True |=> + all_clk_byp_req_o != prim_mubi_pkg::MuBi4True, + clk_i, reset_or_disable) + + // sec_cm_lc_ctrl_clk_handshake_intersig_mubi + `ASSERT(IoClkBypReqTrue_A, + lc_clk_byp_req_i == lc_ctrl_pkg::On |=> ##[2:3] + io_clk_byp_req_o == prim_mubi_pkg::MuBi4True, clk_i, reset_or_disable) + `ASSERT(IoClkBypReqFalse_A, + lc_clk_byp_req_i != lc_ctrl_pkg::On |=> ##[2:3] + io_clk_byp_req_o == prim_mubi_pkg::MuBi4False, clk_i, reset_or_disable) + + // sec_cm_clk_handshake_intersig_mubi, sec_cm_div_intersig_mubi + `ASSERT(LcClkBypAckTrue_A, + step_down_acks_sync == 2'b11 && io_clk_byp_ack == prim_mubi_pkg::MuBi4True |=> ($past( + lc_clk_byp_req_i, 3 + ) == lc_clk_byp_ack_o) || ($past( + lc_clk_byp_req_i, 4 + ) != $past( + lc_clk_byp_req_i, 3 + )), + clk_i, reset_or_disable) + `ASSERT(LcClkBypAckFalse_A, + step_down_acks_sync != 2'b11 || + io_clk_byp_ack != prim_mubi_pkg::MuBi4True |=> + lc_clk_byp_ack_o == lc_ctrl_pkg::Off, + clk_i, reset_or_disable) + +endmodule : clkmgr_sec_cm_checker_assert diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_sva.core b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_sva.core new file mode 100644 index 00000000000..61abfe89b1f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_sva.core @@ -0,0 +1,40 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:clkmgr_sva:0.1 +description: "CLKMGR assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + - lowrisc:darjeeling_no_ibex_dv:clkmgr_sva_ifs:0.1 + files: + - clkmgr_bind.sv + - clkmgr_sec_cm_checker_assert.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:darjeeling_no_ibex_ip:clkmgr + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/clkmgr.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: clkmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_sva_ifs.core b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_sva_ifs.core new file mode 100644 index 00000000000..8d363186d89 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_sva_ifs.core @@ -0,0 +1,28 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:clkmgr_sva_ifs:0.1 +description: "CLKMGR SVA interfaces." +filesets: + files_dv: + depend: + - lowrisc:prim:assert + - lowrisc:prim:mubi + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:dv:clkmgr_pwrmgr_sva_if + files: + - clkmgr_aon_cg_en_sva_if.sv + - clkmgr_cg_en_sva_if.sv + - clkmgr_div_sva_if.sv + - clkmgr_extclk_sva_if.sv + - clkmgr_gated_clock_sva_if.sv + - clkmgr_lost_calib_ctrl_en_sva_if.sv + - clkmgr_lost_calib_regwen_sva_if.sv + - clkmgr_trans_sva_if.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_trans_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_trans_sva_if.sv new file mode 100644 index 00000000000..692e049aac4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/sva/clkmgr_trans_sva_if.sv @@ -0,0 +1,35 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This contains SVA assertions for trans clocks. +interface clkmgr_trans_sva_if ( + input logic clk, + input logic rst_n, + input logic hint, + input logic idle, + input logic scanmode, + input logic status, + input logic trans_clk +); + // This fires at negedges: if the trans clock is inactive its value is expected to be low, and + // viceversa. The clock takes some cycles to react to idle and hint. + localparam int MIN_START_CYCLES = 0; + localparam int MAX_START_CYCLES = 3; + + localparam int MIN_STOP_CYCLES = 2; + localparam int MAX_STOP_CYCLES = 15; + + `ASSERT(TransStart_A, + $rose( + hint + ) ##1 hint [* MIN_START_CYCLES] |=> + ##[0:MAX_START_CYCLES-MIN_START_CYCLES] !hint || trans_clk, + !clk, !rst_n) + `ASSERT(TransStop_A, + $fell( + hint || !idle || scanmode + ) ##1 !hint && !scanmode [* MIN_STOP_CYCLES] |=> + ##[0:MAX_STOP_CYCLES-MIN_STOP_CYCLES] hint || scanmode || !trans_clk, + !clk, !rst_n) +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tb.sv new file mode 100644 index 00000000000..3fcf5ecdc90 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tb.sv @@ -0,0 +1,211 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import clkmgr_env_pkg::*; + import clkmgr_test_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // clock interfaces + wire clk, rst_n, rst_shadowed_n; + clk_rst_if clk_rst_if ( + .clk (clk), + .rst_n(rst_n) + ); + + wire clk_aon, rst_aon_n; + clk_rst_if aon_clk_rst_if ( + .clk (clk_aon), + .rst_n(rst_aon_n) + ); + + wire clk_io, rst_io_n; + clk_rst_if io_clk_rst_if ( + .clk (clk_io), + .rst_n(rst_io_n) + ); + + wire clk_main, rst_main_n; + clk_rst_if main_clk_rst_if ( + .clk (clk_main), + .rst_n(rst_main_n) + ); + + wire rst_io_div2_n; + clk_rst_if io_div2_clk_rst_if ( + .clk (), + .rst_n(rst_io_div2_n) + ); + wire rst_io_div4_n; + clk_rst_if io_div4_clk_rst_if ( + .clk (), + .rst_n(rst_io_div4_n) + ); + clk_rst_if root_main_clk_rst_if ( + .clk (), + .rst_n(rst_root_main_n) + ); + clk_rst_if root_io_clk_rst_if ( + .clk (), + .rst_n(rst_root_io_n) + ); + clk_rst_if root_io_div2_clk_rst_if ( + .clk (), + .rst_n(rst_root_io_div2_n) + ); + clk_rst_if root_io_div4_clk_rst_if ( + .clk (), + .rst_n(rst_root_io_div4_n) + ); + tl_if tl_if ( + .clk (clk), + .rst_n(rst_n) + ); + + // The clkmgr interface. + clkmgr_if clkmgr_if ( + .clk(clk), + .rst_n(rst_n), + .rst_aon_n(rst_aon_ni), + .rst_io_n(rst_io_ni), + .rst_main_n(rst_main_ni) + ); + + bind clkmgr clkmgr_csrs_if clkmgr_csrs_if ( + .clk(clk_i), + .recov_err_csr({ + u_reg.u_recov_err_code_main_timeout_err.qs, + u_reg.u_recov_err_code_io_div4_timeout_err.qs, + u_reg.u_recov_err_code_main_measure_err.qs, + u_reg.u_recov_err_code_io_div4_measure_err.qs, + u_reg.u_recov_err_code_shadow_update_err.qs + }), + .fatal_err_csr({ + u_reg.u_fatal_err_code_shadow_storage_err.qs, + u_reg.u_fatal_err_code_idle_cnt.qs, + u_reg.u_fatal_err_code_reg_intg.qs + }), + .clk_enables({ + reg2hw.clk_enables.clk_io_div2_peri_en.q, + reg2hw.clk_enables.clk_io_div4_peri_en.q}), + .clk_hints({ + reg2hw.clk_hints.clk_main_otbn_hint.q, + reg2hw.clk_hints.clk_main_kmac_hint.q, + reg2hw.clk_hints.clk_main_hmac_hint.q, + reg2hw.clk_hints.clk_main_aes_hint.q}) + ); + + rst_shadowed_if rst_shadowed_if ( + .rst_n(rst_n), + .rst_shadowed_n(rst_shadowed_n) + ); + + initial begin + // Clocks must be set to active at time 0. The rest of the clock configuration happens + // in clkmgr_base_vseq.sv. + clk_rst_if.set_active(); + aon_clk_rst_if.set_active(); + io_clk_rst_if.set_active(); + main_clk_rst_if.set_active(); + io_div2_clk_rst_if.set_active(); + io_div4_clk_rst_if.set_active(); + root_main_clk_rst_if.set_active(); + root_io_clk_rst_if.set_active(); + root_io_div2_clk_rst_if.set_active(); + root_io_div4_clk_rst_if.set_active(); + end + + `DV_ALERT_IF_CONNECT() + + // dut + clkmgr dut ( + .clk_i(clk), + .rst_ni(rst_n), + .rst_shadowed_ni(rst_shadowed_n), + + .clk_aon_i (clk_aon), + .rst_aon_ni(rst_aon_n), + .clk_io_i (clk_io), + .rst_io_ni(rst_io_n), + .clk_main_i (clk_main), + .rst_main_ni(rst_main_n), + .rst_io_div2_ni(rst_io_div2_n), + .rst_io_div4_ni(rst_io_div4_n), + // ICEBOX(#17934): differentiate the root resets as mentioned for rst_io_ni above. + .rst_root_ni(rst_root_io_n), + .rst_root_main_ni(rst_root_main_n), + .rst_root_io_ni(rst_root_io_n), + .rst_root_io_div2_ni(rst_root_io_div2_n), + .rst_root_io_div4_ni(rst_root_io_div4_n), + + .tl_i(tl_if.h2d), + .tl_o(tl_if.d2h), + + .alert_rx_i(alert_rx), + .alert_tx_o(alert_tx), + + .pwr_i(clkmgr_if.pwr_i), + .pwr_o(clkmgr_if.pwr_o), + + .scanmode_i(clkmgr_if.scanmode_i), + .idle_i (clkmgr_if.idle_i), + + .lc_hw_debug_en_i(clkmgr_if.lc_hw_debug_en_i), + .all_clk_byp_req_o(clkmgr_if.all_clk_byp_req), + .all_clk_byp_ack_i(clkmgr_if.all_clk_byp_ack), + .io_clk_byp_req_o(clkmgr_if.io_clk_byp_req), + .io_clk_byp_ack_i(clkmgr_if.io_clk_byp_ack), + .lc_clk_byp_req_i(clkmgr_if.lc_clk_byp_req), + .lc_clk_byp_ack_o(clkmgr_if.lc_clk_byp_ack), + .div_step_down_req_i(clkmgr_if.div_step_down_req), + + .cg_en_o(), + + .jitter_en_o(clkmgr_if.jitter_en_o), + .clocks_o (clkmgr_if.clocks_o), + + .calib_rdy_i(clkmgr_if.calib_rdy), + .hi_speed_sel_o(clkmgr_if.hi_speed_sel) + ); + + initial begin + // Register interfaces with uvm. + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "aon_clk_rst_vif", aon_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_clk_rst_vif", io_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "main_clk_rst_vif", main_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_div2_clk_rst_vif", + io_div2_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_div4_clk_rst_vif", + io_div4_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "root_main_clk_rst_vif", + root_main_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "root_io_clk_rst_vif", + root_io_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "root_io_div2_clk_rst_vif", + root_io_div2_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "root_io_div4_clk_rst_vif", + root_io_div4_clk_rst_if); + uvm_config_db#(virtual clkmgr_if)::set(null, "*.env", "clkmgr_vif", clkmgr_if); + + uvm_config_db#(virtual clkmgr_csrs_if)::set(null, "*.env", "clkmgr_csrs_vif", + dut.clkmgr_csrs_if); + + // FIXME Un-comment this once interrupts are created for this ip. + // uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", + rst_shadowed_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tests/clkmgr_base_test.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tests/clkmgr_base_test.sv new file mode 100644 index 00000000000..a0ddd45839b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tests/clkmgr_base_test.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class clkmgr_base_test extends cip_base_test #( + .CFG_T(clkmgr_env_cfg), + .ENV_T(clkmgr_env) +); + + `uvm_component_utils(clkmgr_base_test) + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // clkmgr_env_cfg: cfg + // clkmgr_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : clkmgr_base_test diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tests/clkmgr_test.core b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tests/clkmgr_test.core new file mode 100644 index 00000000000..4ccc889bdf2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tests/clkmgr_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:clkmgr_test:0.1 +description: "CLKMGR DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:clkmgr_env:0.1 + files: + - clkmgr_test_pkg.sv + - clkmgr_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tests/clkmgr_test_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tests/clkmgr_test_pkg.sv new file mode 100644 index 00000000000..0d1e07762f2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/dv/tests/clkmgr_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package clkmgr_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import clkmgr_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "clkmgr_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/lint/clkmgr.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/lint/clkmgr.vlt new file mode 100644 index 00000000000..f71656fb130 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/lint/clkmgr.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for clkmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/lint/clkmgr.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/lint/clkmgr.waiver new file mode 100644 index 00000000000..49663c1a7f6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/lint/clkmgr.waiver @@ -0,0 +1,21 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for clkmgr + +# +# fake errors + +waive -rules INPUT_NOT_READ -location {prim_clock_gating.sv} -regexp {.*} \ + -comment "Generated abstraction files use .*'s which create fake errors" + +waive -rules EMPTY_PARAM_LIST -location {prim_clock_gating.sv} -regexp {.*} \ + -comment "Generated abstraction files may have empty params" + +waive -rules OUTPUT_NOT_DRIVEN -location {prim_clock_gating.sv} -regexp {.*} \ + -comment "Generated abstraction files do not detect drivers" + +# clock mux errors +waive -rules CLOCK_MUX -location {clkmgr.sv} -regexp {.*clk_io_div.* is driven by a multiplexer here} \ + -comment "All divided clocks terminate with a scan mux" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr.sv new file mode 100644 index 00000000000..ffe3ac9613d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr.sv @@ -0,0 +1,838 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The overall clock manager + + +`include "prim_assert.sv" + + module clkmgr + import clkmgr_pkg::*; + import clkmgr_reg_pkg::*; + import lc_ctrl_pkg::lc_tx_t; + import prim_mubi_pkg::mubi4_t; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert signal + parameter int unsigned AlertSkewCycles = 1 +) ( + // Primary module control clocks and resets + // This drives the register interface + input clk_i, + input rst_ni, + input rst_shadowed_ni, + + // System clocks and resets + // These are the source clocks for the system + input clk_main_i, + input rst_main_ni, + input clk_io_i, + input rst_io_ni, + input clk_aon_i, + input rst_aon_ni, + + // Resets for derived clocks + // clocks are derived locally + input rst_io_div2_ni, + input rst_io_div4_ni, + + // Resets for derived clock generation, root clock gating and related status + input rst_root_ni, + input rst_root_main_ni, + input rst_root_io_ni, + input rst_root_io_div2_ni, + input rst_root_io_div4_ni, + + // Bus Interface + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // pwrmgr interface + input pwrmgr_pkg::pwr_clk_req_t pwr_i, + output pwrmgr_pkg::pwr_clk_rsp_t pwr_o, + + // dft interface + input prim_mubi_pkg::mubi4_t scanmode_i, + + // idle hints + // SEC_CM: IDLE.INTERSIG.MUBI + input prim_mubi_pkg::mubi4_t [3:0] idle_i, + + // life cycle state output + // SEC_CM: LC_CTRL.INTERSIG.MUBI + input lc_tx_t lc_hw_debug_en_i, + + // clock bypass control with lc_ctrl + // SEC_CM: LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI + input lc_tx_t lc_clk_byp_req_i, + output lc_tx_t lc_clk_byp_ack_o, + + // clock bypass control with ast + // SEC_CM: CLK_HANDSHAKE.INTERSIG.MUBI + output mubi4_t io_clk_byp_req_o, + input mubi4_t io_clk_byp_ack_i, + output mubi4_t all_clk_byp_req_o, + input mubi4_t all_clk_byp_ack_i, + output mubi4_t hi_speed_sel_o, + + // clock calibration has been done. + // If this is signal is 0, assume clock frequencies to be + // uncalibrated. + input prim_mubi_pkg::mubi4_t calib_rdy_i, + + // jittery enable to ast + output mubi4_t jitter_en_o, + + // external indication for whether dividers should be stepped down + // SEC_CM: DIV.INTERSIG.MUBI + input mubi4_t div_step_down_req_i, + + // clock gated indications going to alert handlers + output clkmgr_cg_en_t cg_en_o, + + // clock output interface + output clkmgr_out_t clocks_o + +); + + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::mubi4_test_true_strict; + import prim_mubi_pkg::mubi4_test_true_loose; + import prim_mubi_pkg::mubi4_test_false_strict; + + // Hookup point for OCC's on root clocks. + logic clk_main; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_clk_main_buf ( + .clk_i(clk_main_i), + .clk_o(clk_main) + ); + logic clk_io; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_clk_io_buf ( + .clk_i(clk_io_i), + .clk_o(clk_io) + ); + logic clk_aon; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_clk_aon_buf ( + .clk_i(clk_aon_i), + .clk_o(clk_aon) + ); + + //////////////////////////////////////////////////// + // External step down request + //////////////////////////////////////////////////// + mubi4_t io_step_down_req; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(1), + .StabilityCheck(1), + .ResetValue(MuBi4False) + ) u_io_step_down_req_sync ( + .clk_i(clk_io), + .rst_ni(rst_io_ni), + .mubi_i(div_step_down_req_i), + .mubi_o({io_step_down_req}) + ); + + + //////////////////////////////////////////////////// + // Divided clocks + // Note divided clocks must use the por version of + // its related reset to ensure clock division + // can happen without any dependency + //////////////////////////////////////////////////// + + logic [1:0] step_down_acks; + + logic clk_io_div2; + logic clk_io_div4; + + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] io_div2_div_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_io_div2_div_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o({io_div2_div_scanmode}) + ); + + prim_clock_div #( + .Divisor(2) + ) u_no_scan_io_div2_div ( + // We're using the pre-occ hookup (*_i) version for clock derivation. + .clk_i(clk_io_i), + .rst_ni(rst_root_io_ni), + .step_down_req_i(mubi4_test_true_strict(io_step_down_req)), + .step_down_ack_o(step_down_acks[0]), + .test_en_i(mubi4_test_true_strict(io_div2_div_scanmode[0])), + .clk_o(clk_io_div2) + ); + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] io_div4_div_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_io_div4_div_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o({io_div4_div_scanmode}) + ); + + prim_clock_div #( + .Divisor(4) + ) u_no_scan_io_div4_div ( + // We're using the pre-occ hookup (*_i) version for clock derivation. + .clk_i(clk_io_i), + .rst_ni(rst_root_io_ni), + .step_down_req_i(mubi4_test_true_strict(io_step_down_req)), + .step_down_ack_o(step_down_acks[1]), + .test_en_i(mubi4_test_true_strict(io_div4_div_scanmode[0])), + .clk_o(clk_io_div4) + ); + + //////////////////////////////////////////////////// + // Register Interface + //////////////////////////////////////////////////// + + logic [NumAlerts-1:0] alert_test, alerts; + clkmgr_reg_pkg::clkmgr_reg2hw_t reg2hw; + clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg; + + // SEC_CM: MEAS.CONFIG.REGWEN + // SEC_CM: MEAS.CONFIG.SHADOW + // SEC_CM: CLK_CTRL.CONFIG.REGWEN + clkmgr_reg_top u_reg ( + .clk_i, + .rst_ni, + .rst_shadowed_ni, + .clk_io_div4_i(clk_io_div4), + .rst_io_div4_ni, + .clk_main_i(clk_main), + .rst_main_ni, + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + .shadowed_storage_err_o(hw2reg.fatal_err_code.shadow_storage_err.de), + .shadowed_update_err_o(hw2reg.recov_err_code.shadow_update_err.de), + // SEC_CM: BUS.INTEGRITY + .intg_err_o(hw2reg.fatal_err_code.reg_intg.de) + ); + assign hw2reg.fatal_err_code.reg_intg.d = 1'b1; + assign hw2reg.recov_err_code.shadow_update_err.d = 1'b1; + assign hw2reg.fatal_err_code.shadow_storage_err.d = 1'b1; + + //////////////////////////////////////////////////// + // Alerts + //////////////////////////////////////////////////// + + assign alert_test = { + reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe, + reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe + }; + + logic recov_alert; + assign recov_alert = + hw2reg.recov_err_code.io_div4_measure_err.de | + hw2reg.recov_err_code.io_div4_timeout_err.de | + hw2reg.recov_err_code.main_measure_err.de | + hw2reg.recov_err_code.main_timeout_err.de | + hw2reg.recov_err_code.shadow_update_err.de; + + assign alerts = { + |reg2hw.fatal_err_code, + recov_alert + }; + + localparam logic [NumAlerts-1:0] AlertFatal = {1'b1, 1'b0}; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .SkewCycles(AlertSkewCycles), + .IsFatal(AlertFatal[i]) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + //////////////////////////////////////////////////// + // Clock bypass request + //////////////////////////////////////////////////// + + mubi4_t extclk_ctrl_sel; + mubi4_t extclk_ctrl_hi_speed_sel; + + assign extclk_ctrl_sel = mubi4_t'(reg2hw.extclk_ctrl.sel.q); + assign extclk_ctrl_hi_speed_sel = mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q); + + clkmgr_byp #( + .NumDivClks(2) + ) u_clkmgr_byp ( + .clk_i, + .rst_ni, + .en_i(lc_hw_debug_en_i), + .lc_clk_byp_req_i, + .lc_clk_byp_ack_o, + .byp_req_i(extclk_ctrl_sel), + .byp_ack_o(hw2reg.extclk_status.d), + .hi_speed_sel_i(extclk_ctrl_hi_speed_sel), + .all_clk_byp_req_o, + .all_clk_byp_ack_i, + .io_clk_byp_req_o, + .io_clk_byp_ack_i, + .hi_speed_sel_o, + + // divider step down controls + .step_down_acks_i(step_down_acks) + ); + + //////////////////////////////////////////////////// + // Feed through clocks + // Feed through clocks do not actually need to be in clkmgr, as they are + // completely untouched. The only reason they are here is for easier + // bundling management purposes through clocks_o + //////////////////////////////////////////////////// + prim_clock_buf u_clk_io_div4_powerup_buf ( + .clk_i(clk_io_div4), + .clk_o(clocks_o.clk_io_div4_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.io_div4_powerup = MuBi4False; + prim_clock_buf u_clk_aon_powerup_buf ( + .clk_i(clk_aon), + .clk_o(clocks_o.clk_aon_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.aon_powerup = MuBi4False; + prim_clock_buf u_clk_main_powerup_buf ( + .clk_i(clk_main), + .clk_o(clocks_o.clk_main_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.main_powerup = MuBi4False; + prim_clock_buf u_clk_io_powerup_buf ( + .clk_i(clk_io), + .clk_o(clocks_o.clk_io_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.io_powerup = MuBi4False; + prim_clock_buf u_clk_io_div2_powerup_buf ( + .clk_i(clk_io_div2), + .clk_o(clocks_o.clk_io_div2_powerup) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.io_div2_powerup = MuBi4False; + prim_clock_buf u_clk_aon_infra_buf ( + .clk_i(clk_aon), + .clk_o(clocks_o.clk_aon_infra) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.aon_infra = MuBi4False; + prim_clock_buf u_clk_aon_peri_buf ( + .clk_i(clk_aon), + .clk_o(clocks_o.clk_aon_peri) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.aon_peri = MuBi4False; + prim_clock_buf u_clk_aon_timers_buf ( + .clk_i(clk_aon), + .clk_o(clocks_o.clk_aon_timers) + ); + + // clock gated indication for alert handler: these clocks are never gated. + assign cg_en_o.aon_timers = MuBi4False; + + //////////////////////////////////////////////////// + // Distribute pwrmgr ip_clk_en requests to each family + //////////////////////////////////////////////////// + // clk_main family + logic pwrmgr_main_en; + assign pwrmgr_main_en = pwr_i.main_ip_clk_en; + // clk_io family + logic pwrmgr_io_en; + logic pwrmgr_io_div2_en; + logic pwrmgr_io_div4_en; + assign pwrmgr_io_en = pwr_i.io_ip_clk_en; + assign pwrmgr_io_div2_en = pwr_i.io_ip_clk_en; + assign pwrmgr_io_div4_en = pwr_i.io_ip_clk_en; + + //////////////////////////////////////////////////// + // Root gating + //////////////////////////////////////////////////// + + // clk_main family + logic [0:0] main_ens; + + logic clk_main_en; + logic clk_main_root; + clkmgr_root_ctrl u_main_root_ctrl ( + .clk_i(clk_main), + .rst_ni(rst_root_main_ni), + .scanmode_i, + .async_en_i(pwrmgr_main_en), + .en_o(clk_main_en), + .clk_o(clk_main_root) + ); + assign main_ens[0] = clk_main_en; + + // create synchronized status + clkmgr_clk_status #( + .NumClocks(1) + ) u_main_status ( + .clk_i, + .rst_ni(rst_root_ni), + .ens_i(main_ens), + .status_o(pwr_o.main_status) + ); + + // clk_io family + logic [2:0] io_ens; + + logic clk_io_en; + logic clk_io_root; + clkmgr_root_ctrl u_io_root_ctrl ( + .clk_i(clk_io), + .rst_ni(rst_root_io_ni), + .scanmode_i, + .async_en_i(pwrmgr_io_en), + .en_o(clk_io_en), + .clk_o(clk_io_root) + ); + assign io_ens[0] = clk_io_en; + + logic clk_io_div2_en; + logic clk_io_div2_root; + clkmgr_root_ctrl u_io_div2_root_ctrl ( + .clk_i(clk_io_div2), + .rst_ni(rst_root_io_div2_ni), + .scanmode_i, + .async_en_i(pwrmgr_io_div2_en), + .en_o(clk_io_div2_en), + .clk_o(clk_io_div2_root) + ); + assign io_ens[1] = clk_io_div2_en; + + logic clk_io_div4_en; + logic clk_io_div4_root; + clkmgr_root_ctrl u_io_div4_root_ctrl ( + .clk_i(clk_io_div4), + .rst_ni(rst_root_io_div4_ni), + .scanmode_i, + .async_en_i(pwrmgr_io_div4_en), + .en_o(clk_io_div4_en), + .clk_o(clk_io_div4_root) + ); + assign io_ens[2] = clk_io_div4_en; + + // create synchronized status + clkmgr_clk_status #( + .NumClocks(3) + ) u_io_status ( + .clk_i, + .rst_ni(rst_root_ni), + .ens_i(io_ens), + .status_o(pwr_o.io_status) + ); + + //////////////////////////////////////////////////// + // Clock Measurement for the roots + // SEC_CM: TIMEOUT.CLK.BKGN_CHK, MEAS.CLK.BKGN_CHK + //////////////////////////////////////////////////// + + typedef enum logic [1:0] { + BaseIdx, + ClkIoDiv4Idx, + ClkMainIdx, + CalibRdyLastIdx + } clkmgr_calib_idx_e; + + // if clocks become uncalibrated, allow the measurement control configurations to change + mubi4_t [CalibRdyLastIdx-1:0] calib_rdy; + prim_mubi4_sync #( + .AsyncOn(1), + .NumCopies(int'(CalibRdyLastIdx)), + .ResetValue(MuBi4False) + ) u_calib_rdy_sync ( + .clk_i, + .rst_ni, + .mubi_i(calib_rdy_i), + .mubi_o({calib_rdy}) + ); + + always_comb begin + hw2reg.measure_ctrl_regwen.de = '0; + hw2reg.measure_ctrl_regwen.d = reg2hw.measure_ctrl_regwen; + + if (mubi4_test_false_strict(calib_rdy[BaseIdx])) begin + hw2reg.measure_ctrl_regwen.de = 1'b1; + hw2reg.measure_ctrl_regwen.d = 1'b1; + end + end + + clkmgr_meas_chk #( + .Cnt(512), + .RefCnt(32) + ) u_io_div4_meas ( + .clk_i, + .rst_ni, + .clk_src_i(clk_io_div4), + .rst_src_ni(rst_io_div4_ni), + .clk_ref_i(clk_aon), + .rst_ref_ni(rst_aon_ni), + // signals on source domain + .src_en_i(clk_io_div4_en & mubi4_test_true_loose(mubi4_t'(reg2hw.io_div4_meas_ctrl_en))), + .src_max_cnt_i(reg2hw.io_div4_meas_ctrl_shadowed.hi.q), + .src_min_cnt_i(reg2hw.io_div4_meas_ctrl_shadowed.lo.q), + .src_cfg_meas_en_i(mubi4_t'(reg2hw.io_div4_meas_ctrl_en.q)), + .src_cfg_meas_en_valid_o(hw2reg.io_div4_meas_ctrl_en.de), + .src_cfg_meas_en_o(hw2reg.io_div4_meas_ctrl_en.d), + // signals on local clock domain + .calib_rdy_i(calib_rdy[ClkIoDiv4Idx]), + .meas_err_o(hw2reg.recov_err_code.io_div4_measure_err.de), + .timeout_err_o(hw2reg.recov_err_code.io_div4_timeout_err.de) + ); + + assign hw2reg.recov_err_code.io_div4_measure_err.d = 1'b1; + assign hw2reg.recov_err_code.io_div4_timeout_err.d = 1'b1; + + + clkmgr_meas_chk #( + .Cnt(512), + .RefCnt(8) + ) u_main_meas ( + .clk_i, + .rst_ni, + .clk_src_i(clk_main), + .rst_src_ni(rst_main_ni), + .clk_ref_i(clk_aon), + .rst_ref_ni(rst_aon_ni), + // signals on source domain + .src_en_i(clk_main_en & mubi4_test_true_loose(mubi4_t'(reg2hw.main_meas_ctrl_en))), + .src_max_cnt_i(reg2hw.main_meas_ctrl_shadowed.hi.q), + .src_min_cnt_i(reg2hw.main_meas_ctrl_shadowed.lo.q), + .src_cfg_meas_en_i(mubi4_t'(reg2hw.main_meas_ctrl_en.q)), + .src_cfg_meas_en_valid_o(hw2reg.main_meas_ctrl_en.de), + .src_cfg_meas_en_o(hw2reg.main_meas_ctrl_en.d), + // signals on local clock domain + .calib_rdy_i(calib_rdy[ClkMainIdx]), + .meas_err_o(hw2reg.recov_err_code.main_measure_err.de), + .timeout_err_o(hw2reg.recov_err_code.main_timeout_err.de) + ); + + assign hw2reg.recov_err_code.main_measure_err.d = 1'b1; + assign hw2reg.recov_err_code.main_timeout_err.d = 1'b1; + + + //////////////////////////////////////////////////// + // Clocks with only root gate + //////////////////////////////////////////////////// + assign clocks_o.clk_io_div4_infra = clk_io_div4_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div4_infra ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div4_infra) + ); + assign clocks_o.clk_main_infra = clk_main_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_main_infra ( + .clk_i(clk_main), + .rst_ni(rst_main_ni), + .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.main_infra) + ); + assign clocks_o.clk_io_div4_secure = clk_io_div4_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div4_secure ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div4_secure) + ); + assign clocks_o.clk_main_secure = clk_main_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_main_secure ( + .clk_i(clk_main), + .rst_ni(rst_main_ni), + .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.main_secure) + ); + assign clocks_o.clk_io_div4_timers = clk_io_div4_root; + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div4_timers ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div4_timers) + ); + + //////////////////////////////////////////////////// + // Software direct control group + //////////////////////////////////////////////////// + + logic clk_io_div4_peri_sw_en; + logic clk_io_div2_peri_sw_en; + + prim_flop_2sync #( + .Width(1) + ) u_clk_io_div4_peri_sw_en_sync ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .d_i(reg2hw.clk_enables.clk_io_div4_peri_en.q), + .q_o(clk_io_div4_peri_sw_en) + ); + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] clk_io_div4_peri_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_clk_io_div4_peri_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(clk_io_div4_peri_scanmode) + ); + + logic clk_io_div4_peri_combined_en; + assign clk_io_div4_peri_combined_en = clk_io_div4_peri_sw_en & clk_io_div4_en; + prim_clock_gating #( + .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions. + ) u_clk_io_div4_peri_cg ( + .clk_i(clk_io_div4), + .en_i(clk_io_div4_peri_combined_en), + .test_en_i(mubi4_test_true_strict(clk_io_div4_peri_scanmode[0])), + .clk_o(clocks_o.clk_io_div4_peri) + ); + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div4_peri ( + .clk_i(clk_io_div4), + .rst_ni(rst_io_div4_ni), + .mubi_i(((clk_io_div4_peri_combined_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div4_peri) + ); + + prim_flop_2sync #( + .Width(1) + ) u_clk_io_div2_peri_sw_en_sync ( + .clk_i(clk_io_div2), + .rst_ni(rst_io_div2_ni), + .d_i(reg2hw.clk_enables.clk_io_div2_peri_en.q), + .q_o(clk_io_div2_peri_sw_en) + ); + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] clk_io_div2_peri_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_clk_io_div2_peri_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(clk_io_div2_peri_scanmode) + ); + + logic clk_io_div2_peri_combined_en; + assign clk_io_div2_peri_combined_en = clk_io_div2_peri_sw_en & clk_io_div2_en; + prim_clock_gating #( + .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions. + ) u_clk_io_div2_peri_cg ( + .clk_i(clk_io_div2), + .en_i(clk_io_div2_peri_combined_en), + .test_en_i(mubi4_test_true_strict(clk_io_div2_peri_scanmode[0])), + .clk_o(clocks_o.clk_io_div2_peri) + ); + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender_clk_io_div2_peri ( + .clk_i(clk_io_div2), + .rst_ni(rst_io_div2_ni), + .mubi_i(((clk_io_div2_peri_combined_en) ? MuBi4False : MuBi4True)), + .mubi_o(cg_en_o.io_div2_peri) + ); + + + //////////////////////////////////////////////////// + // Software hint group + // The idle hint feedback is assumed to be synchronous to the + // clock target + //////////////////////////////////////////////////// + + logic [3:0] idle_cnt_err; + + clkmgr_trans #( + .FpgaBufGlobal(1'b0) // This clock is used primarily locally. + ) u_clk_main_aes_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainAes]), + .sw_hint_i(reg2hw.clk_hints.clk_main_aes_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_aes), + .clk_o(clocks_o.clk_main_aes), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_aes_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainAes]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainAesCountCheck_A, + u_clk_main_aes_trans.u_idle_cnt, + alert_tx_o[1]) + + clkmgr_trans #( + .FpgaBufGlobal(1'b0) // This clock is used primarily locally. + ) u_clk_main_hmac_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainHmac]), + .sw_hint_i(reg2hw.clk_hints.clk_main_hmac_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_hmac), + .clk_o(clocks_o.clk_main_hmac), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_hmac_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainHmac]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainHmacCountCheck_A, + u_clk_main_hmac_trans.u_idle_cnt, + alert_tx_o[1]) + + clkmgr_trans #( + .FpgaBufGlobal(1'b1) // KMAC is getting too big for a single clock region. + ) u_clk_main_kmac_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainKmac]), + .sw_hint_i(reg2hw.clk_hints.clk_main_kmac_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_kmac), + .clk_o(clocks_o.clk_main_kmac), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_kmac_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainKmac]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainKmacCountCheck_A, + u_clk_main_kmac_trans.u_idle_cnt, + alert_tx_o[1]) + + clkmgr_trans #( + .FpgaBufGlobal(1'b0) // This clock is used primarily locally. + ) u_clk_main_otbn_trans ( + .clk_i(clk_main), + .clk_gated_i(clk_main_root), + .rst_ni(rst_main_ni), + .en_i(clk_main_en), + .idle_i(idle_i[HintMainOtbn]), + .sw_hint_i(reg2hw.clk_hints.clk_main_otbn_hint.q), + .scanmode_i, + .alert_cg_en_o(cg_en_o.main_otbn), + .clk_o(clocks_o.clk_main_otbn), + .clk_reg_i(clk_i), + .rst_reg_ni(rst_ni), + .reg_en_o(hw2reg.clk_hints_status.clk_main_otbn_val.d), + .reg_cnt_err_o(idle_cnt_err[HintMainOtbn]) + ); + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT( + ClkMainOtbnCountCheck_A, + u_clk_main_otbn_trans.u_idle_cnt, + alert_tx_o[1]) + assign hw2reg.fatal_err_code.idle_cnt.d = 1'b1; + assign hw2reg.fatal_err_code.idle_cnt.de = |idle_cnt_err; + + // state readback + assign hw2reg.clk_hints_status.clk_main_aes_val.de = 1'b1; + assign hw2reg.clk_hints_status.clk_main_hmac_val.de = 1'b1; + assign hw2reg.clk_hints_status.clk_main_kmac_val.de = 1'b1; + assign hw2reg.clk_hints_status.clk_main_otbn_val.de = 1'b1; + + // SEC_CM: JITTER.CONFIG.MUBI + assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q); + + //////////////////////////////////////////////////// + // Exported clocks + //////////////////////////////////////////////////// + + + //////////////////////////////////////////////////// + // Assertions + //////////////////////////////////////////////////// + + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o) + `ASSERT_KNOWN(PwrMgrKnownO_A, pwr_o) + `ASSERT_KNOWN(AllClkBypReqKnownO_A, all_clk_byp_req_o) + `ASSERT_KNOWN(IoClkBypReqKnownO_A, io_clk_byp_req_o) + `ASSERT_KNOWN(LcCtrlClkBypAckKnownO_A, lc_clk_byp_ack_o) + `ASSERT_KNOWN(JitterEnableKnownO_A, jitter_en_o) + `ASSERT_KNOWN(ClocksKownO_A, clocks_o) + `ASSERT_KNOWN(CgEnKnownO_A, cg_en_o) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[1]) +endmodule // clkmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_byp.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_byp.sv new file mode 100644 index 00000000000..28bb82baa60 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_byp.sv @@ -0,0 +1,163 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Handle clock manager bypass requests + +module clkmgr_byp + import clkmgr_pkg::*; + import lc_ctrl_pkg::lc_tx_t; + import prim_mubi_pkg::mubi4_t; +# ( + parameter int NumDivClks = 1 +) ( + input clk_i, + input rst_ni, + // interaction with lc_ctrl + input lc_tx_t en_i, + input lc_tx_t lc_clk_byp_req_i, + output lc_tx_t lc_clk_byp_ack_o, + // interaction with software + input mubi4_t byp_req_i, + output mubi4_t byp_ack_o, + input mubi4_t hi_speed_sel_i, + // interaction with ast + output mubi4_t all_clk_byp_req_o, + input mubi4_t all_clk_byp_ack_i, + output mubi4_t io_clk_byp_req_o, + input mubi4_t io_clk_byp_ack_i, + output mubi4_t hi_speed_sel_o, + // interaction with dividers + input [NumDivClks-1:0] step_down_acks_i +); + + import prim_mubi_pkg::MuBi4Width; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::mubi4_and_hi; + import prim_mubi_pkg::mubi4_test_true_strict; + + // synchornize incoming lc signals + lc_tx_t en; + prim_lc_sync #( + .NumCopies(1), + .AsyncOn(1), + .ResetValueIsOn(0) + ) u_en_sync ( + .clk_i, + .rst_ni, + .lc_en_i(en_i), + .lc_en_o({en}) + ); + + typedef enum logic [1:0] { + LcClkBypReqIoReq, + LcClkBypReqLcAck, + LcClkBypReqLast + } lc_clk_byp_req_e; + + lc_tx_t [LcClkBypReqLast-1:0] lc_clk_byp_req; + prim_lc_sync #( + .NumCopies(int'(LcClkBypReqLast)), + .AsyncOn(1), + .ResetValueIsOn(0) + ) u_lc_byp_req ( + .clk_i, + .rst_ni, + .lc_en_i(lc_clk_byp_req_i), + .lc_en_o(lc_clk_byp_req) + ); + + // synchronize step down acks + logic [NumDivClks-1:0] step_down_acks_sync; + prim_flop #( + .Width(NumDivClks), + .ResetValue(0) + ) u_step_down_acks_sync ( + .clk_i, + .rst_ni, + .d_i(step_down_acks_i), + .q_o(step_down_acks_sync) + ); + + // life cycle handling + mubi4_t io_clk_byp_req_d; + assign io_clk_byp_req_d = lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_req[LcClkBypReqIoReq]) ? + MuBi4True : + MuBi4False; + + prim_mubi4_sender #( + .ResetValue(MuBi4False), + .EnSecBuf(1) + ) u_io_byp_req ( + .clk_i, + .rst_ni, + .mubi_i(io_clk_byp_req_d), + .mubi_o(io_clk_byp_req_o) + ); + + // only ack the lc_ctrl if it made a request. + mubi4_t io_clk_byp_ack; + prim_lc_sender u_send ( + .clk_i, + .rst_ni, + .lc_en_i(&step_down_acks_sync & mubi4_test_true_strict(io_clk_byp_ack) ? + lc_clk_byp_req[LcClkBypReqLcAck] : lc_ctrl_pkg::Off), + .lc_en_o(lc_clk_byp_ack_o) + ); + + // software switch request handling + mubi4_t debug_en; + assign debug_en = lc_ctrl_pkg::lc_to_mubi4(en); + + mubi4_t all_clk_byp_req_d; + assign all_clk_byp_req_d = mubi4_and_hi(byp_req_i, debug_en); + + prim_mubi4_sender #( + .AsyncOn(1), + .ResetValue(MuBi4False), + .EnSecBuf(1) + ) u_all_byp_req ( + .clk_i, + .rst_ni, + .mubi_i(all_clk_byp_req_d), + .mubi_o(all_clk_byp_req_o) + ); + + prim_mubi4_sync #( + .AsyncOn(1), + .StabilityCheck(1), + .ResetValue(MuBi4False) + ) u_io_ack_sync ( + .clk_i, + .rst_ni, + .mubi_i(io_clk_byp_ack_i), + .mubi_o({io_clk_byp_ack}) + ); + + // since div_step_down_req is now directly fed externally, there is no longer + // a use for the related 'ack' signals + prim_mubi4_sync #( + .AsyncOn(1), + .StabilityCheck(1), + .ResetValue(MuBi4False) + ) u_all_ack_sync ( + .clk_i, + .rst_ni, + .mubi_i(all_clk_byp_ack_i), + .mubi_o({byp_ack_o}) + ); + + // the software high speed select is valid only when software requests clock + // bypass + prim_mubi4_sender #( + .AsyncOn(1), + .ResetValue(MuBi4True) + ) u_hi_speed_sel ( + .clk_i, + .rst_ni, + .mubi_i(mubi4_and_hi(all_clk_byp_req_d, hi_speed_sel_i)), + .mubi_o(hi_speed_sel_o) + ); + +endmodule // clkmgr_byp diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_clk_status.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_clk_status.sv new file mode 100644 index 00000000000..3c6b38b1025 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_clk_status.sv @@ -0,0 +1,58 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Wrapper module for computing enable / disable status on family of clocks + +module clkmgr_clk_status #( + parameter int NumClocks = 1, + parameter int FilterStages = 2 +) ( + input clk_i, + input rst_ni, + input [NumClocks-1:0] ens_i, + output logic status_o +); + + // The enables are coming from different clock domains, + // therefore after synchronization we must de-bounce the + // signal to ensure it is stable + logic [NumClocks-1:0] ens_sync; + prim_flop_2sync #( + .Width(NumClocks) + ) u_en_sync ( + .clk_i, + .rst_ni, + .d_i(ens_i), + .q_o(ens_sync) + ); + + logic [FilterStages-1:0] en_q, dis_q, en_d, dis_d; + + // enable is true when all inputs are 1 + assign en_d = {en_q[FilterStages-2:0], &ens_sync}; + + // disable is true all all inputs are 0 + assign dis_d = {dis_q[FilterStages-2:0], ~|ens_sync}; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + en_q <= '0; + dis_q <= '0; + end else begin + en_q <= en_d; + dis_q <= dis_d; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + status_o <= '0; + end else if (&en_q) begin + status_o <= 1'b1; + end else if (&dis_q) begin + status_o <= 1'b0; + end + end + +endmodule // clkmgr_clk_status diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv new file mode 100644 index 00000000000..ea0bc8e92be --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_meas_chk.sv @@ -0,0 +1,127 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Clock manager measurement and timeout checks + +module clkmgr_meas_chk + import prim_mubi_pkg::mubi4_t; +#( + // Maximum value of input clock counts over measurement period + parameter int Cnt = 16, + // Maximum value of reference clock counts over measurement period + parameter int RefCnt = 1, + localparam int CntWidth = prim_util_pkg::vbits(Cnt) +) ( + // the local operating clock + input clk_i, + input rst_ni, + // the clock we are measuring + input clk_src_i, + input rst_src_ni, + // the reference clock we are measuring against + input clk_ref_i, + input rst_ref_ni, + // controls all provided on src clock + input src_en_i, + input [CntWidth-1:0] src_max_cnt_i, + input [CntWidth-1:0] src_min_cnt_i, + input mubi4_t src_cfg_meas_en_i, + output logic src_cfg_meas_en_valid_o, + output mubi4_t src_cfg_meas_en_o, + // calibration ready input provided on local operating clock + input mubi4_t calib_rdy_i, + // error output are provided on local operating clock + output logic meas_err_o, + output logic timeout_err_o +); + + logic src_fast_err; + logic src_slow_err; + logic ref_timeout_err; + + prim_clock_meas #( + .Cnt(Cnt), + .RefCnt(RefCnt), + .ClkTimeOutChkEn(1'b1), + .RefTimeOutChkEn(1'b0) + ) u_meas ( + .clk_i(clk_src_i), + .rst_ni(rst_src_ni), + .clk_ref_i, + .rst_ref_ni, + .en_i(src_en_i), + .max_cnt(src_max_cnt_i), + .min_cnt(src_min_cnt_i), + .valid_o(), + .fast_o(src_fast_err), + .slow_o(src_slow_err), + .timeout_clk_ref_o(), + .ref_timeout_clk_o(ref_timeout_err) + ); + + mubi4_t src_calib_rdy; + prim_mubi4_sync #( + .AsyncOn(1), + .ResetValue(prim_mubi_pkg::MuBi4False) + ) u_calib_rdy_sync ( + .clk_i, + .rst_ni, + .mubi_i(calib_rdy_i), + .mubi_o({src_calib_rdy}) + ); + + // if clocks become uncalibrated, switch off measurement controls + always_comb begin + src_cfg_meas_en_valid_o = '0; + src_cfg_meas_en_o = src_cfg_meas_en_i; + + // if calibration is lost when measurement is currently enabled, + // disable measurement enable. + if (prim_mubi_pkg::mubi4_test_false_strict(src_calib_rdy) && + prim_mubi_pkg::mubi4_test_true_loose(src_cfg_meas_en_o)) begin + src_cfg_meas_en_valid_o = 1'b1; + src_cfg_meas_en_o = prim_mubi_pkg::MuBi4False; + end + end + + // A reqack module is used here instead of a pulse_saync + // because the source pulses may toggle too fast for the + // the destination to receive. + logic src_err_req, src_err_ack; + always_ff @(posedge clk_src_i or negedge rst_src_ni) begin + if (!rst_src_ni) begin + src_err_req <= '0; + end else if (src_fast_err || src_slow_err) begin + src_err_req <= 1'b1; + end else if (src_err_req && src_err_ack) begin + src_err_req <= '0; + end + end + + prim_sync_reqack u_err_sync ( + .clk_src_i, + .rst_src_ni, + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .req_chk_i(1'b1), + .src_req_i(src_err_req), + .src_ack_o(src_err_ack), + .dst_req_o(meas_err_o), + .dst_ack_i(meas_err_o) + ); + + prim_edge_detector #( + .Width(1), + .ResetValue('0), + .EnSync(1'b1) + ) u_timeout_err_sync ( + .clk_i, + .rst_ni, + .d_i(ref_timeout_err), + .q_sync_o(), + .q_posedge_pulse_o(timeout_err_o), + .q_negedge_pulse_o() + ); + +endmodule // clkmgr_meas_chk diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv new file mode 100644 index 00000000000..f5c74c41c71 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_pkg.sv @@ -0,0 +1,71 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package clkmgr_pkg; + + typedef enum int { + HintMainAes = 0, + HintMainHmac = 1, + HintMainKmac = 2, + HintMainOtbn = 3 + } hint_names_e; + + // clocks generated and broadcast + typedef struct packed { + logic clk_io_div4_powerup; + logic clk_aon_powerup; + logic clk_main_powerup; + logic clk_io_powerup; + logic clk_io_div2_powerup; + logic clk_aon_infra; + logic clk_aon_peri; + logic clk_aon_timers; + logic clk_main_aes; + logic clk_main_hmac; + logic clk_main_kmac; + logic clk_main_otbn; + logic clk_io_div4_infra; + logic clk_main_infra; + logic clk_io_div4_secure; + logic clk_main_secure; + logic clk_io_div4_timers; + logic clk_io_div4_peri; + logic clk_io_div2_peri; + } clkmgr_out_t; + + // clock gating indication for alert handler + typedef struct packed { + prim_mubi_pkg::mubi4_t io_div4_powerup; + prim_mubi_pkg::mubi4_t aon_powerup; + prim_mubi_pkg::mubi4_t main_powerup; + prim_mubi_pkg::mubi4_t io_powerup; + prim_mubi_pkg::mubi4_t io_div2_powerup; + prim_mubi_pkg::mubi4_t aon_infra; + prim_mubi_pkg::mubi4_t aon_peri; + prim_mubi_pkg::mubi4_t aon_timers; + prim_mubi_pkg::mubi4_t main_aes; + prim_mubi_pkg::mubi4_t main_hmac; + prim_mubi_pkg::mubi4_t main_kmac; + prim_mubi_pkg::mubi4_t main_otbn; + prim_mubi_pkg::mubi4_t io_div4_infra; + prim_mubi_pkg::mubi4_t main_infra; + prim_mubi_pkg::mubi4_t io_div4_secure; + prim_mubi_pkg::mubi4_t main_secure; + prim_mubi_pkg::mubi4_t io_div4_timers; + prim_mubi_pkg::mubi4_t io_div4_peri; + prim_mubi_pkg::mubi4_t io_div2_peri; + } clkmgr_cg_en_t; + + parameter int NumOutputClk = 19; + + + typedef struct packed { + logic [4-1:0] idle; + } clk_hint_status_t; + + parameter clk_hint_status_t CLK_HINT_STATUS_DEFAULT = '{ + idle: {4{1'b1}} + }; + +endpackage // clkmgr_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv new file mode 100644 index 00000000000..bf5847b5b46 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_reg_pkg.sv @@ -0,0 +1,288 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package clkmgr_reg_pkg; + + // Param list + parameter int NumGroups = 7; + parameter int NumSwGateableClocks = 2; + parameter int NumHintableClocks = 4; + parameter int NumAlerts = 2; + + // Address widths within the block + parameter int BlockAw = 6; + + // Number of registers for every interface + parameter int NumRegs = 16; + + // Alert indices + typedef enum int { + AlertRecovFaultIdx = 0, + AlertFatalFaultIdx = 1 + } clkmgr_alert_idx_t; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + logic qe; + } fatal_fault; + struct packed { + logic q; + logic qe; + } recov_fault; + } clkmgr_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + } hi_speed_sel; + struct packed { + logic [3:0] q; + } sel; + } clkmgr_reg2hw_extclk_ctrl_reg_t; + + typedef struct packed { + logic [3:0] q; + } clkmgr_reg2hw_jitter_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + } clk_io_div2_peri_en; + struct packed { + logic q; + } clk_io_div4_peri_en; + } clkmgr_reg2hw_clk_enables_reg_t; + + typedef struct packed { + struct packed { + logic q; + } clk_main_otbn_hint; + struct packed { + logic q; + } clk_main_kmac_hint; + struct packed { + logic q; + } clk_main_hmac_hint; + struct packed { + logic q; + } clk_main_aes_hint; + } clkmgr_reg2hw_clk_hints_reg_t; + + typedef struct packed { + logic q; + } clkmgr_reg2hw_measure_ctrl_regwen_reg_t; + + typedef struct packed { + logic [3:0] q; + } clkmgr_reg2hw_io_div4_meas_ctrl_en_reg_t; + + typedef struct packed { + struct packed { + logic [8:0] q; + } lo; + struct packed { + logic [8:0] q; + } hi; + } clkmgr_reg2hw_io_div4_meas_ctrl_shadowed_reg_t; + + typedef struct packed { + logic [3:0] q; + } clkmgr_reg2hw_main_meas_ctrl_en_reg_t; + + typedef struct packed { + struct packed { + logic [8:0] q; + } lo; + struct packed { + logic [8:0] q; + } hi; + } clkmgr_reg2hw_main_meas_ctrl_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic q; + } shadow_storage_err; + struct packed { + logic q; + } idle_cnt; + struct packed { + logic q; + } reg_intg; + } clkmgr_reg2hw_fatal_err_code_reg_t; + + typedef struct packed { + logic [3:0] d; + } clkmgr_hw2reg_extclk_status_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } clk_main_otbn_val; + struct packed { + logic d; + logic de; + } clk_main_kmac_val; + struct packed { + logic d; + logic de; + } clk_main_hmac_val; + struct packed { + logic d; + logic de; + } clk_main_aes_val; + } clkmgr_hw2reg_clk_hints_status_reg_t; + + typedef struct packed { + logic d; + logic de; + } clkmgr_hw2reg_measure_ctrl_regwen_reg_t; + + typedef struct packed { + logic [3:0] d; + logic de; + } clkmgr_hw2reg_io_div4_meas_ctrl_en_reg_t; + + typedef struct packed { + logic [3:0] d; + logic de; + } clkmgr_hw2reg_main_meas_ctrl_en_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } main_timeout_err; + struct packed { + logic d; + logic de; + } io_div4_timeout_err; + struct packed { + logic d; + logic de; + } main_measure_err; + struct packed { + logic d; + logic de; + } io_div4_measure_err; + struct packed { + logic d; + logic de; + } shadow_update_err; + } clkmgr_hw2reg_recov_err_code_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } shadow_storage_err; + struct packed { + logic d; + logic de; + } idle_cnt; + struct packed { + logic d; + logic de; + } reg_intg; + } clkmgr_hw2reg_fatal_err_code_reg_t; + + // Register -> HW type + typedef struct packed { + clkmgr_reg2hw_alert_test_reg_t alert_test; // [69:66] + clkmgr_reg2hw_extclk_ctrl_reg_t extclk_ctrl; // [65:58] + clkmgr_reg2hw_jitter_enable_reg_t jitter_enable; // [57:54] + clkmgr_reg2hw_clk_enables_reg_t clk_enables; // [53:52] + clkmgr_reg2hw_clk_hints_reg_t clk_hints; // [51:48] + clkmgr_reg2hw_measure_ctrl_regwen_reg_t measure_ctrl_regwen; // [47:47] + clkmgr_reg2hw_io_div4_meas_ctrl_en_reg_t io_div4_meas_ctrl_en; // [46:43] + clkmgr_reg2hw_io_div4_meas_ctrl_shadowed_reg_t io_div4_meas_ctrl_shadowed; // [42:25] + clkmgr_reg2hw_main_meas_ctrl_en_reg_t main_meas_ctrl_en; // [24:21] + clkmgr_reg2hw_main_meas_ctrl_shadowed_reg_t main_meas_ctrl_shadowed; // [20:3] + clkmgr_reg2hw_fatal_err_code_reg_t fatal_err_code; // [2:0] + } clkmgr_reg2hw_t; + + // HW -> register type + typedef struct packed { + clkmgr_hw2reg_extclk_status_reg_t extclk_status; // [39:36] + clkmgr_hw2reg_clk_hints_status_reg_t clk_hints_status; // [35:28] + clkmgr_hw2reg_measure_ctrl_regwen_reg_t measure_ctrl_regwen; // [27:26] + clkmgr_hw2reg_io_div4_meas_ctrl_en_reg_t io_div4_meas_ctrl_en; // [25:21] + clkmgr_hw2reg_main_meas_ctrl_en_reg_t main_meas_ctrl_en; // [20:16] + clkmgr_hw2reg_recov_err_code_reg_t recov_err_code; // [15:6] + clkmgr_hw2reg_fatal_err_code_reg_t fatal_err_code; // [5:0] + } clkmgr_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] CLKMGR_ALERT_TEST_OFFSET = 6'h 0; + parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET = 6'h 4; + parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_CTRL_OFFSET = 6'h 8; + parameter logic [BlockAw-1:0] CLKMGR_EXTCLK_STATUS_OFFSET = 6'h c; + parameter logic [BlockAw-1:0] CLKMGR_JITTER_REGWEN_OFFSET = 6'h 10; + parameter logic [BlockAw-1:0] CLKMGR_JITTER_ENABLE_OFFSET = 6'h 14; + parameter logic [BlockAw-1:0] CLKMGR_CLK_ENABLES_OFFSET = 6'h 18; + parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_OFFSET = 6'h 1c; + parameter logic [BlockAw-1:0] CLKMGR_CLK_HINTS_STATUS_OFFSET = 6'h 20; + parameter logic [BlockAw-1:0] CLKMGR_MEASURE_CTRL_REGWEN_OFFSET = 6'h 24; + parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET = 6'h 28; + parameter logic [BlockAw-1:0] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET = 6'h 2c; + parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET = 6'h 30; + parameter logic [BlockAw-1:0] CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET = 6'h 34; + parameter logic [BlockAw-1:0] CLKMGR_RECOV_ERR_CODE_OFFSET = 6'h 38; + parameter logic [BlockAw-1:0] CLKMGR_FATAL_ERR_CODE_OFFSET = 6'h 3c; + + // Reset values for hwext registers and their fields + parameter logic [1:0] CLKMGR_ALERT_TEST_RESVAL = 2'h 0; + parameter logic [0:0] CLKMGR_ALERT_TEST_RECOV_FAULT_RESVAL = 1'h 0; + parameter logic [0:0] CLKMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [3:0] CLKMGR_EXTCLK_STATUS_RESVAL = 4'h 9; + parameter logic [3:0] CLKMGR_EXTCLK_STATUS_ACK_RESVAL = 4'h 9; + + // Register index + typedef enum int { + CLKMGR_ALERT_TEST, + CLKMGR_EXTCLK_CTRL_REGWEN, + CLKMGR_EXTCLK_CTRL, + CLKMGR_EXTCLK_STATUS, + CLKMGR_JITTER_REGWEN, + CLKMGR_JITTER_ENABLE, + CLKMGR_CLK_ENABLES, + CLKMGR_CLK_HINTS, + CLKMGR_CLK_HINTS_STATUS, + CLKMGR_MEASURE_CTRL_REGWEN, + CLKMGR_IO_DIV4_MEAS_CTRL_EN, + CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED, + CLKMGR_MAIN_MEAS_CTRL_EN, + CLKMGR_MAIN_MEAS_CTRL_SHADOWED, + CLKMGR_RECOV_ERR_CODE, + CLKMGR_FATAL_ERR_CODE + } clkmgr_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] CLKMGR_PERMIT [16] = '{ + 4'b 0001, // index[ 0] CLKMGR_ALERT_TEST + 4'b 0001, // index[ 1] CLKMGR_EXTCLK_CTRL_REGWEN + 4'b 0001, // index[ 2] CLKMGR_EXTCLK_CTRL + 4'b 0001, // index[ 3] CLKMGR_EXTCLK_STATUS + 4'b 0001, // index[ 4] CLKMGR_JITTER_REGWEN + 4'b 0001, // index[ 5] CLKMGR_JITTER_ENABLE + 4'b 0001, // index[ 6] CLKMGR_CLK_ENABLES + 4'b 0001, // index[ 7] CLKMGR_CLK_HINTS + 4'b 0001, // index[ 8] CLKMGR_CLK_HINTS_STATUS + 4'b 0001, // index[ 9] CLKMGR_MEASURE_CTRL_REGWEN + 4'b 0001, // index[10] CLKMGR_IO_DIV4_MEAS_CTRL_EN + 4'b 0111, // index[11] CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED + 4'b 0001, // index[12] CLKMGR_MAIN_MEAS_CTRL_EN + 4'b 0111, // index[13] CLKMGR_MAIN_MEAS_CTRL_SHADOWED + 4'b 0001, // index[14] CLKMGR_RECOV_ERR_CODE + 4'b 0001 // index[15] CLKMGR_FATAL_ERR_CODE + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv new file mode 100644 index 00000000000..28f488445cb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv @@ -0,0 +1,1717 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module clkmgr_reg_top ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + input clk_io_div4_i, + input rst_io_div4_ni, + input clk_main_i, + input rst_main_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output clkmgr_reg_pkg::clkmgr_reg2hw_t reg2hw, // Write + input clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg, // Read + + output logic shadowed_storage_err_o, + output logic shadowed_update_err_o, + + // Integrity check errors + output logic intg_err_o +); + + import clkmgr_reg_pkg::* ; + + localparam int AW = 6; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [15:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(16) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic alert_test_we; + logic alert_test_recov_fault_wd; + logic alert_test_fatal_fault_wd; + logic extclk_ctrl_regwen_we; + logic extclk_ctrl_regwen_qs; + logic extclk_ctrl_regwen_wd; + logic extclk_ctrl_we; + logic [3:0] extclk_ctrl_sel_qs; + logic [3:0] extclk_ctrl_sel_wd; + logic [3:0] extclk_ctrl_hi_speed_sel_qs; + logic [3:0] extclk_ctrl_hi_speed_sel_wd; + logic extclk_status_re; + logic [3:0] extclk_status_qs; + logic jitter_regwen_we; + logic jitter_regwen_qs; + logic jitter_regwen_wd; + logic jitter_enable_we; + logic [3:0] jitter_enable_qs; + logic [3:0] jitter_enable_wd; + logic clk_enables_we; + logic clk_enables_clk_io_div4_peri_en_qs; + logic clk_enables_clk_io_div4_peri_en_wd; + logic clk_enables_clk_io_div2_peri_en_qs; + logic clk_enables_clk_io_div2_peri_en_wd; + logic clk_hints_we; + logic clk_hints_clk_main_aes_hint_qs; + logic clk_hints_clk_main_aes_hint_wd; + logic clk_hints_clk_main_hmac_hint_qs; + logic clk_hints_clk_main_hmac_hint_wd; + logic clk_hints_clk_main_kmac_hint_qs; + logic clk_hints_clk_main_kmac_hint_wd; + logic clk_hints_clk_main_otbn_hint_qs; + logic clk_hints_clk_main_otbn_hint_wd; + logic clk_hints_status_clk_main_aes_val_qs; + logic clk_hints_status_clk_main_hmac_val_qs; + logic clk_hints_status_clk_main_kmac_val_qs; + logic clk_hints_status_clk_main_otbn_val_qs; + logic measure_ctrl_regwen_we; + logic measure_ctrl_regwen_qs; + logic measure_ctrl_regwen_wd; + logic io_div4_meas_ctrl_en_we; + logic [3:0] io_div4_meas_ctrl_en_qs; + logic io_div4_meas_ctrl_en_busy; + logic io_div4_meas_ctrl_shadowed_re; + logic io_div4_meas_ctrl_shadowed_we; + logic [17:0] io_div4_meas_ctrl_shadowed_qs; + logic io_div4_meas_ctrl_shadowed_busy; + logic io_div4_meas_ctrl_shadowed_hi_storage_err; + logic io_div4_meas_ctrl_shadowed_hi_update_err; + logic io_div4_meas_ctrl_shadowed_lo_storage_err; + logic io_div4_meas_ctrl_shadowed_lo_update_err; + logic main_meas_ctrl_en_we; + logic [3:0] main_meas_ctrl_en_qs; + logic main_meas_ctrl_en_busy; + logic main_meas_ctrl_shadowed_re; + logic main_meas_ctrl_shadowed_we; + logic [17:0] main_meas_ctrl_shadowed_qs; + logic main_meas_ctrl_shadowed_busy; + logic main_meas_ctrl_shadowed_hi_storage_err; + logic main_meas_ctrl_shadowed_hi_update_err; + logic main_meas_ctrl_shadowed_lo_storage_err; + logic main_meas_ctrl_shadowed_lo_update_err; + logic recov_err_code_we; + logic recov_err_code_shadow_update_err_qs; + logic recov_err_code_shadow_update_err_wd; + logic recov_err_code_io_div4_measure_err_qs; + logic recov_err_code_io_div4_measure_err_wd; + logic recov_err_code_main_measure_err_qs; + logic recov_err_code_main_measure_err_wd; + logic recov_err_code_io_div4_timeout_err_qs; + logic recov_err_code_io_div4_timeout_err_wd; + logic recov_err_code_main_timeout_err_qs; + logic recov_err_code_main_timeout_err_wd; + logic fatal_err_code_reg_intg_qs; + logic fatal_err_code_idle_cnt_qs; + logic fatal_err_code_shadow_storage_err_qs; + // Define register CDC handling. + // CDC handling is done on a per-reg instead of per-field boundary. + + logic [3:0] io_div4_io_div4_meas_ctrl_en_ds_int; + logic [3:0] io_div4_io_div4_meas_ctrl_en_qs_int; + logic [3:0] io_div4_io_div4_meas_ctrl_en_ds; + logic io_div4_io_div4_meas_ctrl_en_qe; + logic [3:0] io_div4_io_div4_meas_ctrl_en_qs; + logic [3:0] io_div4_io_div4_meas_ctrl_en_wdata; + logic io_div4_io_div4_meas_ctrl_en_we; + logic unused_io_div4_io_div4_meas_ctrl_en_wdata; + logic io_div4_io_div4_meas_ctrl_en_regwen; + + always_comb begin + io_div4_io_div4_meas_ctrl_en_qs = 4'h9; + io_div4_io_div4_meas_ctrl_en_ds = 4'h9; + io_div4_io_div4_meas_ctrl_en_ds = io_div4_io_div4_meas_ctrl_en_ds_int; + io_div4_io_div4_meas_ctrl_en_qs = io_div4_io_div4_meas_ctrl_en_qs_int; + end + + prim_reg_cdc #( + .DataWidth(4), + .ResetVal(4'h9), + .BitMask(4'hf), + .DstWrReq(1) + ) u_io_div4_meas_ctrl_en_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_io_div4_i), + .rst_dst_ni (rst_io_div4_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (io_div4_meas_ctrl_en_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[3:0]), + .src_busy_o (io_div4_meas_ctrl_en_busy), + .src_qs_o (io_div4_meas_ctrl_en_qs), // for software read back + .dst_update_i (io_div4_io_div4_meas_ctrl_en_qe), + .dst_ds_i (io_div4_io_div4_meas_ctrl_en_ds), + .dst_qs_i (io_div4_io_div4_meas_ctrl_en_qs), + .dst_we_o (io_div4_io_div4_meas_ctrl_en_we), + .dst_re_o (), + .dst_regwen_o (io_div4_io_div4_meas_ctrl_en_regwen), + .dst_wd_o (io_div4_io_div4_meas_ctrl_en_wdata) + ); + assign unused_io_div4_io_div4_meas_ctrl_en_wdata = + ^io_div4_io_div4_meas_ctrl_en_wdata; + + logic [8:0] io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int; + logic [8:0] io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int; + logic [17:0] io_div4_io_div4_meas_ctrl_shadowed_qs; + logic [17:0] io_div4_io_div4_meas_ctrl_shadowed_wdata; + logic io_div4_io_div4_meas_ctrl_shadowed_we; + logic unused_io_div4_io_div4_meas_ctrl_shadowed_wdata; + logic io_div4_io_div4_meas_ctrl_shadowed_re; + logic io_div4_io_div4_meas_ctrl_shadowed_regwen; + + always_comb begin + io_div4_io_div4_meas_ctrl_shadowed_qs = 18'hec8a; + io_div4_io_div4_meas_ctrl_shadowed_qs[8:0] = io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int; + io_div4_io_div4_meas_ctrl_shadowed_qs[17:9] = io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int; + end + + prim_reg_cdc #( + .DataWidth(18), + .ResetVal(18'hec8a), + .BitMask(18'h3ffff), + .DstWrReq(0) + ) u_io_div4_meas_ctrl_shadowed_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_io_div4_i), + .rst_dst_ni (rst_io_div4_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (io_div4_meas_ctrl_shadowed_we), + .src_re_i (io_div4_meas_ctrl_shadowed_re), + .src_wd_i (reg_wdata[17:0]), + .src_busy_o (io_div4_meas_ctrl_shadowed_busy), + .src_qs_o (io_div4_meas_ctrl_shadowed_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (io_div4_io_div4_meas_ctrl_shadowed_qs), + .dst_we_o (io_div4_io_div4_meas_ctrl_shadowed_we), + .dst_re_o (io_div4_io_div4_meas_ctrl_shadowed_re), + .dst_regwen_o (io_div4_io_div4_meas_ctrl_shadowed_regwen), + .dst_wd_o (io_div4_io_div4_meas_ctrl_shadowed_wdata) + ); + assign unused_io_div4_io_div4_meas_ctrl_shadowed_wdata = + ^io_div4_io_div4_meas_ctrl_shadowed_wdata; + + logic [3:0] main_main_meas_ctrl_en_ds_int; + logic [3:0] main_main_meas_ctrl_en_qs_int; + logic [3:0] main_main_meas_ctrl_en_ds; + logic main_main_meas_ctrl_en_qe; + logic [3:0] main_main_meas_ctrl_en_qs; + logic [3:0] main_main_meas_ctrl_en_wdata; + logic main_main_meas_ctrl_en_we; + logic unused_main_main_meas_ctrl_en_wdata; + logic main_main_meas_ctrl_en_regwen; + + always_comb begin + main_main_meas_ctrl_en_qs = 4'h9; + main_main_meas_ctrl_en_ds = 4'h9; + main_main_meas_ctrl_en_ds = main_main_meas_ctrl_en_ds_int; + main_main_meas_ctrl_en_qs = main_main_meas_ctrl_en_qs_int; + end + + prim_reg_cdc #( + .DataWidth(4), + .ResetVal(4'h9), + .BitMask(4'hf), + .DstWrReq(1) + ) u_main_meas_ctrl_en_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_main_i), + .rst_dst_ni (rst_main_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (main_meas_ctrl_en_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[3:0]), + .src_busy_o (main_meas_ctrl_en_busy), + .src_qs_o (main_meas_ctrl_en_qs), // for software read back + .dst_update_i (main_main_meas_ctrl_en_qe), + .dst_ds_i (main_main_meas_ctrl_en_ds), + .dst_qs_i (main_main_meas_ctrl_en_qs), + .dst_we_o (main_main_meas_ctrl_en_we), + .dst_re_o (), + .dst_regwen_o (main_main_meas_ctrl_en_regwen), + .dst_wd_o (main_main_meas_ctrl_en_wdata) + ); + assign unused_main_main_meas_ctrl_en_wdata = + ^main_main_meas_ctrl_en_wdata; + + logic [8:0] main_main_meas_ctrl_shadowed_hi_qs_int; + logic [8:0] main_main_meas_ctrl_shadowed_lo_qs_int; + logic [17:0] main_main_meas_ctrl_shadowed_qs; + logic [17:0] main_main_meas_ctrl_shadowed_wdata; + logic main_main_meas_ctrl_shadowed_we; + logic unused_main_main_meas_ctrl_shadowed_wdata; + logic main_main_meas_ctrl_shadowed_re; + logic main_main_meas_ctrl_shadowed_regwen; + + always_comb begin + main_main_meas_ctrl_shadowed_qs = 18'hec8a; + main_main_meas_ctrl_shadowed_qs[8:0] = main_main_meas_ctrl_shadowed_hi_qs_int; + main_main_meas_ctrl_shadowed_qs[17:9] = main_main_meas_ctrl_shadowed_lo_qs_int; + end + + prim_reg_cdc #( + .DataWidth(18), + .ResetVal(18'hec8a), + .BitMask(18'h3ffff), + .DstWrReq(0) + ) u_main_meas_ctrl_shadowed_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_main_i), + .rst_dst_ni (rst_main_ni), + .src_regwen_i (measure_ctrl_regwen_qs), + .src_we_i (main_meas_ctrl_shadowed_we), + .src_re_i (main_meas_ctrl_shadowed_re), + .src_wd_i (reg_wdata[17:0]), + .src_busy_o (main_meas_ctrl_shadowed_busy), + .src_qs_o (main_meas_ctrl_shadowed_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (main_main_meas_ctrl_shadowed_qs), + .dst_we_o (main_main_meas_ctrl_shadowed_we), + .dst_re_o (main_main_meas_ctrl_shadowed_re), + .dst_regwen_o (main_main_meas_ctrl_shadowed_regwen), + .dst_wd_o (main_main_meas_ctrl_shadowed_wdata) + ); + assign unused_main_main_meas_ctrl_shadowed_wdata = + ^main_main_meas_ctrl_shadowed_wdata; + + // Register instances + // R[alert_test]: V(True) + logic alert_test_qe; + logic [1:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[recov_fault]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.recov_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_fault.qe = alert_test_qe; + + // F[fatal_fault]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe; + + + // R[extclk_ctrl_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_extclk_ctrl_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (extclk_ctrl_regwen_we), + .wd (extclk_ctrl_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (extclk_ctrl_regwen_qs) + ); + + + // R[extclk_ctrl]: V(False) + // Create REGWEN-gated WE signal + logic extclk_ctrl_gated_we; + assign extclk_ctrl_gated_we = extclk_ctrl_we & extclk_ctrl_regwen_qs; + // F[sel]: 3:0 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_extclk_ctrl_sel ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (extclk_ctrl_gated_we), + .wd (extclk_ctrl_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.extclk_ctrl.sel.q), + .ds (), + + // to register interface (read) + .qs (extclk_ctrl_sel_qs) + ); + + // F[hi_speed_sel]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_extclk_ctrl_hi_speed_sel ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (extclk_ctrl_gated_we), + .wd (extclk_ctrl_hi_speed_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.extclk_ctrl.hi_speed_sel.q), + .ds (), + + // to register interface (read) + .qs (extclk_ctrl_hi_speed_sel_qs) + ); + + + // R[extclk_status]: V(True) + prim_subreg_ext #( + .DW (4) + ) u_extclk_status ( + .re (extclk_status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.extclk_status.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (extclk_status_qs) + ); + + + // R[jitter_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_jitter_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (jitter_regwen_we), + .wd (jitter_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (jitter_regwen_qs) + ); + + + // R[jitter_enable]: V(False) + // Create REGWEN-gated WE signal + logic jitter_enable_gated_we; + assign jitter_enable_gated_we = jitter_enable_we & jitter_regwen_qs; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_jitter_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (jitter_enable_gated_we), + .wd (jitter_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.jitter_enable.q), + .ds (), + + // to register interface (read) + .qs (jitter_enable_qs) + ); + + + // R[clk_enables]: V(False) + // F[clk_io_div4_peri_en]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_enables_clk_io_div4_peri_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_enables_we), + .wd (clk_enables_clk_io_div4_peri_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_enables.clk_io_div4_peri_en.q), + .ds (), + + // to register interface (read) + .qs (clk_enables_clk_io_div4_peri_en_qs) + ); + + // F[clk_io_div2_peri_en]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_enables_clk_io_div2_peri_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_enables_we), + .wd (clk_enables_clk_io_div2_peri_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_enables.clk_io_div2_peri_en.q), + .ds (), + + // to register interface (read) + .qs (clk_enables_clk_io_div2_peri_en_qs) + ); + + + // R[clk_hints]: V(False) + // F[clk_main_aes_hint]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_clk_main_aes_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_hints_we), + .wd (clk_hints_clk_main_aes_hint_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_hints.clk_main_aes_hint.q), + .ds (), + + // to register interface (read) + .qs (clk_hints_clk_main_aes_hint_qs) + ); + + // F[clk_main_hmac_hint]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_clk_main_hmac_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_hints_we), + .wd (clk_hints_clk_main_hmac_hint_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_hints.clk_main_hmac_hint.q), + .ds (), + + // to register interface (read) + .qs (clk_hints_clk_main_hmac_hint_qs) + ); + + // F[clk_main_kmac_hint]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_clk_main_kmac_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_hints_we), + .wd (clk_hints_clk_main_kmac_hint_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_hints.clk_main_kmac_hint.q), + .ds (), + + // to register interface (read) + .qs (clk_hints_clk_main_kmac_hint_qs) + ); + + // F[clk_main_otbn_hint]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_clk_main_otbn_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (clk_hints_we), + .wd (clk_hints_clk_main_otbn_hint_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.clk_hints.clk_main_otbn_hint.q), + .ds (), + + // to register interface (read) + .qs (clk_hints_clk_main_otbn_hint_qs) + ); + + + // R[clk_hints_status]: V(False) + // F[clk_main_aes_val]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_status_clk_main_aes_val ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.clk_hints_status.clk_main_aes_val.de), + .d (hw2reg.clk_hints_status.clk_main_aes_val.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (clk_hints_status_clk_main_aes_val_qs) + ); + + // F[clk_main_hmac_val]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_status_clk_main_hmac_val ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.clk_hints_status.clk_main_hmac_val.de), + .d (hw2reg.clk_hints_status.clk_main_hmac_val.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (clk_hints_status_clk_main_hmac_val_qs) + ); + + // F[clk_main_kmac_val]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_status_clk_main_kmac_val ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.clk_hints_status.clk_main_kmac_val.de), + .d (hw2reg.clk_hints_status.clk_main_kmac_val.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (clk_hints_status_clk_main_kmac_val_qs) + ); + + // F[clk_main_otbn_val]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_clk_hints_status_clk_main_otbn_val ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.clk_hints_status.clk_main_otbn_val.de), + .d (hw2reg.clk_hints_status.clk_main_otbn_val.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (clk_hints_status_clk_main_otbn_val_qs) + ); + + + // R[measure_ctrl_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_measure_ctrl_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (measure_ctrl_regwen_we), + .wd (measure_ctrl_regwen_wd), + + // from internal hardware + .de (hw2reg.measure_ctrl_regwen.de), + .d (hw2reg.measure_ctrl_regwen.d), + + // to internal hardware + .qe (), + .q (reg2hw.measure_ctrl_regwen.q), + .ds (), + + // to register interface (read) + .qs (measure_ctrl_regwen_qs) + ); + + + // R[io_div4_meas_ctrl_en]: V(False) + logic [0:0] io_div4_meas_ctrl_en_flds_we; + assign io_div4_io_div4_meas_ctrl_en_qe = |io_div4_meas_ctrl_en_flds_we; + // Create REGWEN-gated WE signal + logic io_div4_io_div4_meas_ctrl_en_gated_we; + assign io_div4_io_div4_meas_ctrl_en_gated_we = + io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_io_div4_meas_ctrl_en ( + .clk_i (clk_io_div4_i), + .rst_ni (rst_io_div4_ni), + + // from register interface + .we (io_div4_io_div4_meas_ctrl_en_gated_we), + .wd (io_div4_io_div4_meas_ctrl_en_wdata[3:0]), + + // from internal hardware + .de (hw2reg.io_div4_meas_ctrl_en.de), + .d (hw2reg.io_div4_meas_ctrl_en.d), + + // to internal hardware + .qe (io_div4_meas_ctrl_en_flds_we[0]), + .q (reg2hw.io_div4_meas_ctrl_en.q), + .ds (io_div4_io_div4_meas_ctrl_en_ds_int), + + // to register interface (read) + .qs (io_div4_io_div4_meas_ctrl_en_qs_int) + ); + + + // R[io_div4_meas_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic io_div4_io_div4_meas_ctrl_shadowed_gated_we; + assign io_div4_io_div4_meas_ctrl_shadowed_gated_we = + io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen; + // F[hi]: 8:0 + logic async_io_div4_meas_ctrl_shadowed_hi_err_update; + logic async_io_div4_meas_ctrl_shadowed_hi_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_io_div4_meas_ctrl_shadowed_hi_err_storage), + .q_o(io_div4_meas_ctrl_shadowed_hi_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_io_div4_meas_ctrl_shadowed_hi_err_update_sync ( + .clk_src_i(clk_io_div4_i), + .rst_src_ni(rst_io_div4_ni), + .src_pulse_i(async_io_div4_meas_ctrl_shadowed_hi_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(io_div4_meas_ctrl_shadowed_hi_update_err) + ); + prim_subreg_shadow #( + .DW (9), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (9'h8a), + .Mubi (1'b0) + ) u_io_div4_meas_ctrl_shadowed_hi ( + .clk_i (clk_io_div4_i), + .rst_ni (rst_io_div4_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (io_div4_io_div4_meas_ctrl_shadowed_re), + .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we), + .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[8:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.io_div4_meas_ctrl_shadowed.hi.q), + .ds (), + + // to register interface (read) + .qs (io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_io_div4_meas_ctrl_shadowed_hi_err_update), + .err_storage (async_io_div4_meas_ctrl_shadowed_hi_err_storage) + ); + + // F[lo]: 17:9 + logic async_io_div4_meas_ctrl_shadowed_lo_err_update; + logic async_io_div4_meas_ctrl_shadowed_lo_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_io_div4_meas_ctrl_shadowed_lo_err_storage), + .q_o(io_div4_meas_ctrl_shadowed_lo_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_io_div4_meas_ctrl_shadowed_lo_err_update_sync ( + .clk_src_i(clk_io_div4_i), + .rst_src_ni(rst_io_div4_ni), + .src_pulse_i(async_io_div4_meas_ctrl_shadowed_lo_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(io_div4_meas_ctrl_shadowed_lo_update_err) + ); + prim_subreg_shadow #( + .DW (9), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (9'h76), + .Mubi (1'b0) + ) u_io_div4_meas_ctrl_shadowed_lo ( + .clk_i (clk_io_div4_i), + .rst_ni (rst_io_div4_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (io_div4_io_div4_meas_ctrl_shadowed_re), + .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we), + .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[17:9]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.io_div4_meas_ctrl_shadowed.lo.q), + .ds (), + + // to register interface (read) + .qs (io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_io_div4_meas_ctrl_shadowed_lo_err_update), + .err_storage (async_io_div4_meas_ctrl_shadowed_lo_err_storage) + ); + + + // R[main_meas_ctrl_en]: V(False) + logic [0:0] main_meas_ctrl_en_flds_we; + assign main_main_meas_ctrl_en_qe = |main_meas_ctrl_en_flds_we; + // Create REGWEN-gated WE signal + logic main_main_meas_ctrl_en_gated_we; + assign main_main_meas_ctrl_en_gated_we = + main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_main_meas_ctrl_en ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + + // from register interface + .we (main_main_meas_ctrl_en_gated_we), + .wd (main_main_meas_ctrl_en_wdata[3:0]), + + // from internal hardware + .de (hw2reg.main_meas_ctrl_en.de), + .d (hw2reg.main_meas_ctrl_en.d), + + // to internal hardware + .qe (main_meas_ctrl_en_flds_we[0]), + .q (reg2hw.main_meas_ctrl_en.q), + .ds (main_main_meas_ctrl_en_ds_int), + + // to register interface (read) + .qs (main_main_meas_ctrl_en_qs_int) + ); + + + // R[main_meas_ctrl_shadowed]: V(False) + // Create REGWEN-gated WE signal + logic main_main_meas_ctrl_shadowed_gated_we; + assign main_main_meas_ctrl_shadowed_gated_we = + main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen; + // F[hi]: 8:0 + logic async_main_meas_ctrl_shadowed_hi_err_update; + logic async_main_meas_ctrl_shadowed_hi_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_main_meas_ctrl_shadowed_hi_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_main_meas_ctrl_shadowed_hi_err_storage), + .q_o(main_meas_ctrl_shadowed_hi_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_main_meas_ctrl_shadowed_hi_err_update_sync ( + .clk_src_i(clk_main_i), + .rst_src_ni(rst_main_ni), + .src_pulse_i(async_main_meas_ctrl_shadowed_hi_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(main_meas_ctrl_shadowed_hi_update_err) + ); + prim_subreg_shadow #( + .DW (9), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (9'h8a), + .Mubi (1'b0) + ) u_main_meas_ctrl_shadowed_hi ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (main_main_meas_ctrl_shadowed_re), + .we (main_main_meas_ctrl_shadowed_gated_we), + .wd (main_main_meas_ctrl_shadowed_wdata[8:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.main_meas_ctrl_shadowed.hi.q), + .ds (), + + // to register interface (read) + .qs (main_main_meas_ctrl_shadowed_hi_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_main_meas_ctrl_shadowed_hi_err_update), + .err_storage (async_main_meas_ctrl_shadowed_hi_err_storage) + ); + + // F[lo]: 17:9 + logic async_main_meas_ctrl_shadowed_lo_err_update; + logic async_main_meas_ctrl_shadowed_lo_err_storage; + + // storage error is persistent and can be sampled at any time + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_main_meas_ctrl_shadowed_lo_err_storage_sync ( + .clk_i, + .rst_ni, + .d_i(async_main_meas_ctrl_shadowed_lo_err_storage), + .q_o(main_meas_ctrl_shadowed_lo_storage_err) + ); + + // update error is transient and must be immediately captured + prim_pulse_sync u_main_meas_ctrl_shadowed_lo_err_update_sync ( + .clk_src_i(clk_main_i), + .rst_src_ni(rst_main_ni), + .src_pulse_i(async_main_meas_ctrl_shadowed_lo_err_update), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(main_meas_ctrl_shadowed_lo_update_err) + ); + prim_subreg_shadow #( + .DW (9), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (9'h76), + .Mubi (1'b0) + ) u_main_meas_ctrl_shadowed_lo ( + .clk_i (clk_main_i), + .rst_ni (rst_main_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (main_main_meas_ctrl_shadowed_re), + .we (main_main_meas_ctrl_shadowed_gated_we), + .wd (main_main_meas_ctrl_shadowed_wdata[17:9]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.main_meas_ctrl_shadowed.lo.q), + .ds (), + + // to register interface (read) + .qs (main_main_meas_ctrl_shadowed_lo_qs_int), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (async_main_meas_ctrl_shadowed_lo_err_update), + .err_storage (async_main_meas_ctrl_shadowed_lo_err_storage) + ); + + + // R[recov_err_code]: V(False) + // F[shadow_update_err]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_shadow_update_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_shadow_update_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.shadow_update_err.de), + .d (hw2reg.recov_err_code.shadow_update_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_shadow_update_err_qs) + ); + + // F[io_div4_measure_err]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_io_div4_measure_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_io_div4_measure_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.io_div4_measure_err.de), + .d (hw2reg.recov_err_code.io_div4_measure_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_io_div4_measure_err_qs) + ); + + // F[main_measure_err]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_main_measure_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_main_measure_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.main_measure_err.de), + .d (hw2reg.recov_err_code.main_measure_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_main_measure_err_qs) + ); + + // F[io_div4_timeout_err]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_io_div4_timeout_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_io_div4_timeout_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.io_div4_timeout_err.de), + .d (hw2reg.recov_err_code.io_div4_timeout_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_io_div4_timeout_err_qs) + ); + + // F[main_timeout_err]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_recov_err_code_main_timeout_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (recov_err_code_we), + .wd (recov_err_code_main_timeout_err_wd), + + // from internal hardware + .de (hw2reg.recov_err_code.main_timeout_err.de), + .d (hw2reg.recov_err_code.main_timeout_err.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (recov_err_code_main_timeout_err_qs) + ); + + + // R[fatal_err_code]: V(False) + // F[reg_intg]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fatal_err_code_reg_intg ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fatal_err_code.reg_intg.de), + .d (hw2reg.fatal_err_code.reg_intg.d), + + // to internal hardware + .qe (), + .q (reg2hw.fatal_err_code.reg_intg.q), + .ds (), + + // to register interface (read) + .qs (fatal_err_code_reg_intg_qs) + ); + + // F[idle_cnt]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fatal_err_code_idle_cnt ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fatal_err_code.idle_cnt.de), + .d (hw2reg.fatal_err_code.idle_cnt.d), + + // to internal hardware + .qe (), + .q (reg2hw.fatal_err_code.idle_cnt.q), + .ds (), + + // to register interface (read) + .qs (fatal_err_code_idle_cnt_qs) + ); + + // F[shadow_storage_err]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fatal_err_code_shadow_storage_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fatal_err_code.shadow_storage_err.de), + .d (hw2reg.fatal_err_code.shadow_storage_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.fatal_err_code.shadow_storage_err.q), + .ds (), + + // to register interface (read) + .qs (fatal_err_code_shadow_storage_err_qs) + ); + + + + logic [15:0] addr_hit; + always_comb begin + addr_hit[ 0] = (reg_addr == CLKMGR_ALERT_TEST_OFFSET); + addr_hit[ 1] = (reg_addr == CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET); + addr_hit[ 2] = (reg_addr == CLKMGR_EXTCLK_CTRL_OFFSET); + addr_hit[ 3] = (reg_addr == CLKMGR_EXTCLK_STATUS_OFFSET); + addr_hit[ 4] = (reg_addr == CLKMGR_JITTER_REGWEN_OFFSET); + addr_hit[ 5] = (reg_addr == CLKMGR_JITTER_ENABLE_OFFSET); + addr_hit[ 6] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET); + addr_hit[ 7] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET); + addr_hit[ 8] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET); + addr_hit[ 9] = (reg_addr == CLKMGR_MEASURE_CTRL_REGWEN_OFFSET); + addr_hit[10] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET); + addr_hit[11] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[12] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET); + addr_hit[13] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET); + addr_hit[14] = (reg_addr == CLKMGR_RECOV_ERR_CODE_OFFSET); + addr_hit[15] = (reg_addr == CLKMGR_FATAL_ERR_CODE_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(CLKMGR_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(CLKMGR_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(CLKMGR_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(CLKMGR_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(CLKMGR_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(CLKMGR_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(CLKMGR_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(CLKMGR_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(CLKMGR_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(CLKMGR_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(CLKMGR_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(CLKMGR_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(CLKMGR_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(CLKMGR_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(CLKMGR_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(CLKMGR_PERMIT[15] & ~reg_be))))); + end + + // Generate write-enables + assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + + assign alert_test_recov_fault_wd = reg_wdata[0]; + + assign alert_test_fatal_fault_wd = reg_wdata[1]; + assign extclk_ctrl_regwen_we = addr_hit[1] & reg_we & !reg_error; + + assign extclk_ctrl_regwen_wd = reg_wdata[0]; + assign extclk_ctrl_we = addr_hit[2] & reg_we & !reg_error; + + assign extclk_ctrl_sel_wd = reg_wdata[3:0]; + + assign extclk_ctrl_hi_speed_sel_wd = reg_wdata[7:4]; + assign extclk_status_re = addr_hit[3] & reg_re & !reg_error; + assign jitter_regwen_we = addr_hit[4] & reg_we & !reg_error; + + assign jitter_regwen_wd = reg_wdata[0]; + assign jitter_enable_we = addr_hit[5] & reg_we & !reg_error; + + assign jitter_enable_wd = reg_wdata[3:0]; + assign clk_enables_we = addr_hit[6] & reg_we & !reg_error; + + assign clk_enables_clk_io_div4_peri_en_wd = reg_wdata[0]; + + assign clk_enables_clk_io_div2_peri_en_wd = reg_wdata[1]; + assign clk_hints_we = addr_hit[7] & reg_we & !reg_error; + + assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0]; + + assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[1]; + + assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[2]; + + assign clk_hints_clk_main_otbn_hint_wd = reg_wdata[3]; + assign measure_ctrl_regwen_we = addr_hit[9] & reg_we & !reg_error; + + assign measure_ctrl_regwen_wd = reg_wdata[0]; + assign io_div4_meas_ctrl_en_we = addr_hit[10] & reg_we & !reg_error; + + assign io_div4_meas_ctrl_shadowed_re = addr_hit[11] & reg_re & !reg_error; + assign io_div4_meas_ctrl_shadowed_we = addr_hit[11] & reg_we & !reg_error; + + + assign main_meas_ctrl_en_we = addr_hit[12] & reg_we & !reg_error; + + assign main_meas_ctrl_shadowed_re = addr_hit[13] & reg_re & !reg_error; + assign main_meas_ctrl_shadowed_we = addr_hit[13] & reg_we & !reg_error; + + + assign recov_err_code_we = addr_hit[14] & reg_we & !reg_error; + + assign recov_err_code_shadow_update_err_wd = reg_wdata[0]; + + assign recov_err_code_io_div4_measure_err_wd = reg_wdata[1]; + + assign recov_err_code_main_measure_err_wd = reg_wdata[2]; + + assign recov_err_code_io_div4_timeout_err_wd = reg_wdata[3]; + + assign recov_err_code_main_timeout_err_wd = reg_wdata[4]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = alert_test_we; + reg_we_check[1] = extclk_ctrl_regwen_we; + reg_we_check[2] = extclk_ctrl_gated_we; + reg_we_check[3] = 1'b0; + reg_we_check[4] = jitter_regwen_we; + reg_we_check[5] = jitter_enable_gated_we; + reg_we_check[6] = clk_enables_we; + reg_we_check[7] = clk_hints_we; + reg_we_check[8] = 1'b0; + reg_we_check[9] = measure_ctrl_regwen_we; + reg_we_check[10] = io_div4_meas_ctrl_en_we; + reg_we_check[11] = io_div4_meas_ctrl_shadowed_we; + reg_we_check[12] = main_meas_ctrl_en_we; + reg_we_check[13] = main_meas_ctrl_shadowed_we; + reg_we_check[14] = recov_err_code_we; + reg_we_check[15] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[1]: begin + reg_rdata_next[0] = extclk_ctrl_regwen_qs; + end + + addr_hit[2]: begin + reg_rdata_next[3:0] = extclk_ctrl_sel_qs; + reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs; + end + + addr_hit[3]: begin + reg_rdata_next[3:0] = extclk_status_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = jitter_regwen_qs; + end + + addr_hit[5]: begin + reg_rdata_next[3:0] = jitter_enable_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs; + reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs; + reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs; + reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs; + reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs; + reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs; + reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs; + reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = measure_ctrl_regwen_qs; + end + + addr_hit[10]: begin + reg_rdata_next = DW'(io_div4_meas_ctrl_en_qs); + end + addr_hit[11]: begin + reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs); + end + addr_hit[12]: begin + reg_rdata_next = DW'(main_meas_ctrl_en_qs); + end + addr_hit[13]: begin + reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs); + end + addr_hit[14]: begin + reg_rdata_next[0] = recov_err_code_shadow_update_err_qs; + reg_rdata_next[1] = recov_err_code_io_div4_measure_err_qs; + reg_rdata_next[2] = recov_err_code_main_measure_err_qs; + reg_rdata_next[3] = recov_err_code_io_div4_timeout_err_qs; + reg_rdata_next[4] = recov_err_code_main_timeout_err_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = fatal_err_code_reg_intg_qs; + reg_rdata_next[1] = fatal_err_code_idle_cnt_qs; + reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + logic rst_done; + logic shadow_rst_done; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_done <= '0; + end else begin + rst_done <= 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin + if (!rst_shadowed_ni) begin + shadow_rst_done <= '0; + end else begin + shadow_rst_done <= 1'b1; + end + end + + // both shadow and normal resets have been released + assign shadow_busy = ~(rst_done & shadow_rst_done); + + // Collect up storage and update errors + assign shadowed_storage_err_o = |{ + io_div4_meas_ctrl_shadowed_hi_storage_err, + io_div4_meas_ctrl_shadowed_lo_storage_err, + main_meas_ctrl_shadowed_hi_storage_err, + main_meas_ctrl_shadowed_lo_storage_err + }; + assign shadowed_update_err_o = |{ + io_div4_meas_ctrl_shadowed_hi_update_err, + io_div4_meas_ctrl_shadowed_lo_update_err, + main_meas_ctrl_shadowed_hi_update_err, + main_meas_ctrl_shadowed_lo_update_err + }; + + // register busy + logic reg_busy_sel; + assign reg_busy = (reg_busy_sel | shadow_busy) & tl_i.a_valid; + always_comb begin + reg_busy_sel = '0; + unique case (1'b1) + addr_hit[10]: begin + reg_busy_sel = io_div4_meas_ctrl_en_busy; + end + addr_hit[11]: begin + reg_busy_sel = io_div4_meas_ctrl_shadowed_busy; + end + addr_hit[12]: begin + reg_busy_sel = main_meas_ctrl_en_busy; + end + addr_hit[13]: begin + reg_busy_sel = main_meas_ctrl_shadowed_busy; + end + default: begin + reg_busy_sel = '0; + end + endcase + end + + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_root_ctrl.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_root_ctrl.sv new file mode 100644 index 00000000000..3008d2b24aa --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_root_ctrl.sv @@ -0,0 +1,41 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Wrapper for scan sync and clock gating cell + +module clkmgr_root_ctrl + import clkmgr_pkg::*; + import prim_mubi_pkg::mubi4_t; +( + input clk_i, + input rst_ni, + + input mubi4_t scanmode_i, + input async_en_i, + + output logic en_o, + output logic clk_o +); + + mubi4_t scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) // clock/reset below is only used for SVAs. + ) u_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o({scanmode}) + ); + + prim_clock_gating_sync u_cg ( + .clk_i, + .rst_ni, + .test_en_i(prim_mubi_pkg::mubi4_test_true_strict(scanmode)), + .async_en_i, + .en_o, + .clk_o + ); + +endmodule // clkmgr_root_ctrl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_trans.sv b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_trans.sv new file mode 100644 index 00000000000..80c6aa21642 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/rtl/clkmgr_trans.sv @@ -0,0 +1,175 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Handle clock manager transactional clocks + +module clkmgr_trans + import clkmgr_pkg::*; + import prim_mubi_pkg::mubi4_t; +# ( + parameter bit FpgaBufGlobal = 1 +) ( + input clk_i, + input clk_gated_i, + input rst_ni, + input en_i, + input mubi4_t idle_i, + input sw_hint_i, + input mubi4_t scanmode_i, + output mubi4_t alert_cg_en_o, + output logic clk_o, + + // interface to regfile + input clk_reg_i, + input rst_reg_ni, + output logic reg_en_o, + output logic reg_cnt_err_o +); + + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::mubi4_test_true_strict; + import prim_mubi_pkg::mubi4_test_false_loose; + + // Note this value is specifically chosen. + // The binary value is 1010, which is a balanced 4-bit value + // that should in theory be resistant to all 0 or all 1 attacks. + localparam int unsigned TransIdleCnt = 10; + localparam int IdleCntWidth = $clog2(TransIdleCnt + 1); + + logic [IdleCntWidth-1:0] idle_cnt; + logic idle_valid; + logic sw_hint_synced; + logic local_en; + assign idle_valid = (idle_cnt == IdleCntWidth'(TransIdleCnt)); + assign local_en = sw_hint_synced | ~idle_valid; + + prim_flop_2sync #( + .Width(1) + ) u_hint_sync ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(sw_hint_i), + .q_o(sw_hint_synced) + ); + + // Idle sync: Idle signal comes from IP module. The reset of the Idle signal + // may differ from the reset here. Adding mubi sync to synchronize. + prim_mubi_pkg::mubi4_t [0:0] idle; + prim_mubi4_sync #( + .NumCopies ( 1 ), + .AsyncOn ( 1'b 1 ), + .StabilityCheck ( 1'b 1 ) + ) u_idle_sync ( + .clk_i, + .rst_ni, + .mubi_i (idle_i), + .mubi_o (idle) + ); + + // SEC_CM: IDLE.CTR.REDUN + logic cnt_err; + prim_count #( + .Width(IdleCntWidth) + ) u_idle_cnt ( + .clk_i(clk_i), + .rst_ni(rst_ni), + // the default condition is to keep the clock enabled + .clr_i(mubi4_test_false_loose(idle[0])), + .set_i('0), + .set_cnt_i('0), + .incr_en_i(mubi4_test_true_strict(idle[0]) & ~idle_valid), + .decr_en_i(1'b0), + .step_i(IdleCntWidth'(1'b1)), + .commit_i(1'b1), + .cnt_o(idle_cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(scanmode) + ); + + // Add a prim buf here to make sure the CG and the lc sender inputs + // are derived from the same physical signal. + logic combined_en_d, combined_en_q; + prim_buf u_prim_buf_en ( + .in_i(local_en & en_i), + .out_o(combined_en_d) + ); + + // clk_gated_i is already controlled by en_i, so there is no need + // to use it in the below gating function + prim_clock_gating #( + .FpgaBufGlobal(FpgaBufGlobal) + ) u_cg ( + .clk_i(clk_gated_i), + .en_i(local_en), + .test_en_i(mubi4_test_true_strict(scanmode[0])), + .clk_o(clk_o) + ); + + // clock gated indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .mubi_i(combined_en_d ? MuBi4False : MuBi4True), + .mubi_o(alert_cg_en_o) + ); + + // we hold the error because there is no guarantee on + // what the timing of cnt_err looks like, it may be a + // pulse or it may be level. If it's for former, + // prim_sync_reqack may miss it, if it's the latter, + // prim_pulse_sync may miss it. As a result, just + // latch forever and sync it over. + logic hold_err; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + hold_err <= '0; + end else if (cnt_err) begin + hold_err <= 1'b1; + end + end + + // register facing domain + prim_flop_2sync #( + .Width(1) + ) u_err_sync ( + .clk_i(clk_reg_i), + .rst_ni(rst_reg_ni), + .d_i(hold_err), + .q_o(reg_cnt_err_o) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + combined_en_q <= '0; + end else begin + combined_en_q <= combined_en_d; + end + end + + prim_flop_2sync #( + .Width(1) + ) u_en_sync ( + .clk_i(clk_reg_i), + .rst_ni(rst_reg_ni), + .d_i(combined_en_q), + .q_o(reg_en_o) + ); + + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util/BUILD.bazel b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util/BUILD.bazel new file mode 100644 index 00000000000..153a7c07877 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util/BUILD.bazel @@ -0,0 +1,20 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +py_library( + name = "ipconfig", + srcs = ["ipconfig.py"], +) + +py_library( + name = "dt", + srcs = ["dt.py"], + deps = [ + ":ipconfig", + "//util/dtgen:helper", + "//util/topgen", + ], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util/dt.py b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util/dt.py new file mode 100644 index 00000000000..49f0cd92dcc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util/dt.py @@ -0,0 +1,144 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +"""This contains a class which is used to help generate the device tables (DT) +files. +""" +from dtgen.helper import IpHelper, Extension, StructType, ScalarType, ArrayMapType +from topgen.lib import Name +from typing import Dict, Optional +import os +import sys + +sys.path.insert(0, os.path.dirname(os.path.realpath(__file__))) +from ipconfig import ClkmgrIpConfig # noqa: E402 + +HEADER_EXT_TEMPLATE = """ +/** + * Get the number of software gateable clocks. + * + * @param dt Instance of clkmgr. + * @return Number of gateable clocks. + */ +size_t dt_clkmgr_gateable_clock_count(dt_clkmgr_t dt); + +/** + * Get the instance ID of a gateable clock. + * + * The clocks are ordered as they appear in the registers. + * + * @param dt Instance of clkmgr. + * @param idx Index of the gateable clock, between 0 and `dt_clkmgr_sw_clock_count(dt)-1`. + * @return Instance ID of the device whose clock is gateable. + */ +dt_instance_id_t dt_clkmgr_gateable_clock(dt_clkmgr_t dt, size_t idx); + +/** + * Get the number of software hintable clocks. + * + * @param dt Instance of clkmgr. + * @return Number of hintable clocks. + */ +size_t dt_clkmgr_hintable_clock_count(dt_clkmgr_t dt); + +/** + * Get the instance ID of a hintable clock. + * + * The clocks sources are ordered as they appear in the registers. + * + * @param dt Instance of clkmgr. + * @param idx Index of the hintable clock, between 0 and `dt_clkmgr_hint_clock_count(dt)-1`. + * @return Instance ID of the device whose clock is hintable. + */ +dt_instance_id_t dt_clkmgr_hintable_clock(dt_clkmgr_t dt, size_t idx); +""" + +SOURCE_EXT_TEMPLATE = """ +size_t dt_clkmgr_gateable_clock_count(dt_clkmgr_t dt) { + return %(sw_clk_count)d; +} + +dt_instance_id_t dt_clkmgr_gateable_clock(dt_clkmgr_t dt, size_t idx) { + return TRY_GET_DT(dt, kDtInstanceIdUnknown)->clkmgr_ext.sw_clks[idx]; +} + +size_t dt_clkmgr_hintable_clock_count(dt_clkmgr_t dt) { + return %(hint_clk_count)d; +} + +dt_instance_id_t dt_clkmgr_hintable_clock(dt_clkmgr_t dt, size_t idx) { + return TRY_GET_DT(dt, kDtInstanceIdUnknown)->clkmgr_ext.hint_clks[idx]; +} +""" + + +class ClkmgrExt(Extension): + SW_CLOCKS_FIELD_NAME = Name(["sw", "clks"]) + HINT_CLOCKS_FIELD_NAME = Name(["hint", "clks"]) + + def __init__(self, ip_helper: IpHelper): + self.ip_helper = ip_helper + if self.ip_helper.ipconfig is None: + raise RuntimeError("the clkmgr extension requires the ipconfig to be provided") + self.ipconfig = ClkmgrIpConfig(self.ip_helper.ipconfig) + + @staticmethod + def create_ext(ip_helper: IpHelper) -> Optional["Extension"]: + if ip_helper.ip.name == "clkmgr": + return ClkmgrExt(ip_helper) + + def extend_dt_ip(self) -> tuple[Name, StructType]: + sw_clk_count = len(self.ipconfig.sw_clks()) + hint_clk_count = len(self.ipconfig.hint_clks()) + instance_id_enum = self.ip_helper.top_helper.instance_id_enum + + st = StructType() + # Add field to list gateable clocks. + st.add_field( + name = self.SW_CLOCKS_FIELD_NAME, + field_type = ArrayMapType( + elem_type = ScalarType(instance_id_enum.name), + index_type = ScalarType("size_t"), + length = str(sw_clk_count), + ), + docstring = "List of gateable clocks, in the order of the register fields", + ) + # Add field to list hintable clocks. + st.add_field( + name = self.HINT_CLOCKS_FIELD_NAME, + field_type = ArrayMapType( + elem_type = ScalarType(instance_id_enum.name), + index_type = ScalarType("size_t"), + length = str(hint_clk_count), + ), + docstring = "List of hintable clocks, in the order of the register fields", + ) + return Name(["clkmgr_ext"]), st + + def fill_dt_ip(self, m) -> Dict: + sw_clks = {} + for (idx, clk) in enumerate(self.ipconfig.sw_clks()): + sw_clks[str(idx)] = Name.from_snake_case(clk["module"]) + hint_clks = {} + for (idx, clk) in enumerate(self.ipconfig.hint_clks()): + hint_clks[str(idx)] = Name.from_snake_case(clk["module"]) + + return { + self.SW_CLOCKS_FIELD_NAME: sw_clks, + self.HINT_CLOCKS_FIELD_NAME: hint_clks, + } + + def render_dt_ip(self, pos: Extension.DtIpPos) -> str: + sw_clk_count = len(self.ipconfig.sw_clks()) + hint_clk_count = len(self.ipconfig.hint_clks()) + + if pos == Extension.DtIpPos.HeaderEnd: + return HEADER_EXT_TEMPLATE + elif pos == Extension.DtIpPos.SourceEnd: + subs = { + 'sw_clk_count': sw_clk_count, + 'hint_clk_count': hint_clk_count, + } + return SOURCE_EXT_TEMPLATE % subs + else: + return "" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util/ipconfig.py b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util/ipconfig.py new file mode 100644 index 00000000000..aae6616f25f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/clkmgr/util/ipconfig.py @@ -0,0 +1,51 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +""" +This contains a class to access the clkmgr's configuration from its ipconfig +files. +""" +from typing import List, Dict + + +class ClkmgrIpConfig: + def __init__(self, ipconfig: object): + """ + Initialize an `IpConfig` from an already loaded and parsed `ipconfig.hjson` + file, as well as a top configuration. + """ + self.param_values = ipconfig["param_values"] + + def sw_clks(self) -> List[Dict]: + """ + Return the list of software controllable clocks: each clock is described by a + dictionary with the following fields: + - `src`: clock source + - `module`: the module whose clock is controlled. + + The list is ordered as in the description. + """ + return [ + { + "src": clk["src_name"], + "module": clk["endpoint_ip"], + } + for clk in self.param_values["typed_clocks"]["sw_clks"].values() + ] + + def hint_clks(self) -> List[Dict]: + """ + Return the list of hintable clocks: each clock is described by a + dictionary with the following fields: + - `src`: clock source + - `module`: the module whose clock is controlled. + + The list is ordered as in the description. + """ + return [ + { + "src": clk["src_name"], + "module": clk["endpoint_ip"], + } + for clk in self.param_values["typed_clocks"]["hint_clks"].values() + ] diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/BUILD new file mode 100644 index 00000000000..faf1685a83f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/BUILD @@ -0,0 +1,25 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.svg", + ]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/gpio/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/README.md new file mode 100644 index 00000000000..dfa814ccdf5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/README.md @@ -0,0 +1,63 @@ +# GPIO HWIP Technical Specification + +[`gpio`](https://reports.opentitan.org/hw/ip/gpio/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/gpio/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/gpio/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/gpio/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/gpio/code.svg) + +# Overview + +This document specifies GPIO hardware IP functionality. This +module conforms to the [Comportable guideline for peripheral device +functionality](../../../../doc/contributing/hw/comportability/README.md) +See that document for integration overview within the broader top +level system. + +## Features + +- 32 GPIO ports +- Configurable interrupt per GPIO for detecting rising edge, falling edge, + or active low/high input +- Two ways to update GPIO output: direct-write and masked (thread-safe) update +- 8 input period counters + +## Description + +The GPIO block allows software to communicate through general purpose I/O +pins in a flexible manner. Each of 32 independent bits can be written +as peripheral outputs in two modes. Each of the 32 bits can be read +by software as peripheral inputs. How these peripheral inputs and +outputs are connected to the chip IO is not within the scope of this +document. See the Comportability Specification for peripheral IO options +at the top chip level. + +In the output direction, this module provides direct 32b access to each +GPIO value using direct write. This mode allows software to control all +GPIO bits simultaneously. Alternately, this module provides masked writes +to half of the bits at a time, allowing software to affect the output +value of a subset of the bits without requiring a read-modify-write. +In this mode the user provides a mask of which of the 16 bits are to be +modified, along with their new value. The details of this mode are given +in the [Programmers Guide](#programmers-guide) below. + +In the input direction, software can read the contents of any of the GPIO +peripheral inputs. In addition, software can request the detection of an +interrupt event for any of the 32 bits in a configurable manner. The choices +are positive edge, negative edge or level detection events. A noise +filter is available through configuration for any of the 32 GPIO inputs. +This requires the input to be stable for 16 cycles of the +module clock before the input register reflects the change and interrupt +generation is evaluated. Note that if the filter is enabled and the pin +is set to output then there will be a corresponding delay in a change +in output value being reflected in the input register. + +Each of the input period counters can count the number of clock cycles in one +period (i.e., from one rising or falling edge to the same edge in the same +direction) of an input signal. Each input signal can be assigned to any of the +counters. The counter can operate in one-shot (i.e., just measure one period) or +continuous (i.e., keep measuring periods) mode. The polarity (i.e., whether a +rising or a falling edge counts as begin and end of a period) is configurable. +A prescaler on the sampling clock extends the range of the period counter. + +See the Design Details section for more details on the features. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/BUILD new file mode 100644 index 00000000000..2661603d5ec --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/BUILD @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_gpio.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = glob([ + "gpio.hjson", + "*_testplan.hjson", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/gpio.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/gpio.hjson new file mode 100644 index 00000000000..14daea0fd91 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/gpio.hjson @@ -0,0 +1,548 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "gpio", + human_name: "General-Purpose I/O Controller", + one_line_desc: "General-purpose I/O pin control interface for software", + one_paragraph_desc: ''' + General-Purpose Input/Output (GPIO) Controller allows software to communicate through general-purpose I/O pins in a flexible manner. + It supports up to 32 GPIO ports and each of these ports can be written as peripheral outputs in two modes: either with direct access to each GPIO value using direct write, allowing software to control all GPIO ports simultaneously, or with masked writes to half of the bits at a time, allowing software to affect the output value of a subset of the bits without requiring a read-modify-write. + In the input direction, software can read the contents of any of the GPIO peripheral inputs, and it can request the detection of an interrupt event for any of the 32 bits in a configurable manner for detecting rising edge, falling edge, or active low/high input. + A noise filter is available through configuration for any of the inputs. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "9", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_gpio", + revisions: [ + { + version: "1.0.0", + life_stage: "L2", + design_stage: "D3", + verification_stage: "V3", + commit_id: "c1be7eb2b7265cd5ba6ceb026c28acf8e371151a", + notes: "", + } + { + version: "1.2.0", + life_stage: "L1", + design_stage: "D2", + verification_stage: "V1", + dif_stage: "S1", + notes: "" + } + ] + clocking: [{clock: "clk_i", reset: "rst_ni"}], + bus_interfaces: [ + { protocol: "tlul", direction: "device", racl_support: true } + ], + available_inout_list: [ + { name: "gpio", + width: 32, + desc: "GPIO inout to/from PAD" + } + ], + interrupt_list: [ + { name: "gpio", + width: 32, + desc: "raised if any of GPIO pin detects configured interrupt mode" + auto_split: "true" + } + ], + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + param_list: [ + { name: "GpioAsyncOn", + type: "bit", + default: "1'b1", + desc: ''' + Instantiates 2-flop synchronizers on all GPIO inputs if set to 1. + ''' + local: "false", + expose: "true" + }, + { name: "GpioAsHwStrapsEn", + type: "bit", + default: "1'b1", + desc: ''' + Enable HW straps sampling logic for GPIO inputs at initial cold boot + ''' + local: "false", + expose: "true" + }, + { name: "NumIOs", + type: "int", + default: "32", + desc: '''Number of I/Os. + If you change this, also change the width of `gpio` in `available_inout_list` and `interrupt_list`. + Values >= 17 and <= 32 should be supported without RTL changes, although only 32 has been verified. + Values outside that range would likely require significant RTL changes. + ''' + local: "true", + }, + { name: "NumInpPeriodCounters", + type: "int", + default: "8", + desc: "Number of input period counters.", + local: "true", + }, + ] + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + ] + features: [ + { + name: "GPIO.IN.INTR_CTRL" + desc: '''Input interrupts can be triggered identified by detecting either level or edge. + There are four detection modes available: rising edge, falling edge, high-level, and low-level. + ''' + } + { + name: "GPIO.IN.FILTER" + desc: '''GPIO module provides noise filter control. + It can be enabled with programing GPIO.CTRL_EN_INPUT_FILTER. + Once it enables, input value must be stable for 16cycles before transitioning + ''' + } + { + name: "GPIO.OUT.MASK" + desc: 'Masked output access enables to modify either upper or lower 16bits of output register without a Read-Modify-Write.' + } + ] + inter_signal_list: [ + { struct: "logic", + type: "uni", + name: "strap_en", + act: "rcv", + package: "", + desc: ''' + The strap enable signal tells gpio to take a snapshot of the input pins. + The behaviour of this signal after that event will have no effect. + ''', + default: "1'b0" + }, + { struct: "gpio_straps", + type: "uni", + name: "sampled_straps", + act: "req", + package: "gpio_pkg", + desc: ''' + This vector contains the sampled strap values. + ''', + default: "'0" + }, + { struct: "racl_policy_vec", + type: "uni", + name: "racl_policies", + act: "rcv", + package: "top_racl_pkg", + desc: ''' + Incoming RACL policy vector from a racl_ctrl instance. + The policy selection vector (parameter) selects the policy for each register. + ''' + } + { struct: "racl_error_log", + type: "uni", + name: "racl_error", + act: "req", + width: "1" + package: "top_racl_pkg", + desc: ''' + RACL error log information of this module. + ''' + } + ] + + + regwidth: "32", + registers: [ + { name: "DATA_IN", + desc: "GPIO Input data read value", + swaccess: "ro", + hwaccess: "hwo", + tags: [// data_in is ro register, so exclude its readback check + "excl:CsrNonInitTests:CsrExclWriteCheck"], + fields: [ + { bits: "31:0", + resval: "x" + } + ], + }, + { name: "DIRECT_OUT", + desc: "GPIO direct output data write value", + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + fields: [ + { bits: "31:0" } + ], + }, + { name: "MASKED_OUT_LOWER", + desc: '''GPIO write data lower with mask. + + Masked write for DATA_OUT[15:0]. + + Upper 16 bits of this register are used as mask. Writing + lower 16 bits of the register changes DATA_OUT[15:0] value + if mask bits are set. + + Read-back of this register returns upper 16 bits as zero + and lower 16 bits as DATA_OUT[15:0]. + ''' + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [// read value of masked_* registers yield a different value than written + // avoid writing to masked_out* registers as they affect direct_out value + "excl:CsrNonInitTests:CsrExclAll"], + fields: [ + { bits: "15:0", + name: "data", + desc: '''Write data value[15:0]. + + Value to write into DATA_OUT[i], valid in the presence of mask[i]==1 + ''' + }, + { bits: "31:16", + name: "mask", + desc: '''Write data mask[15:0]. + + A value of 1 in mask[i] allows the updating of DATA_OUT[i], 0 <= i <= 15 + ''' + swaccess: "wo" + }, + ], + }, + { name: "MASKED_OUT_UPPER", + desc: '''GPIO write data upper with mask. + + Masked write for DATA_OUT[31:16]. + + Upper 16 bits of this register are used as mask. Writing + lower 16 bits of the register changes DATA_OUT[31:16] value + if mask bits are set. + + Read-back of this register returns upper 16 bits as zero + and lower 16 bits as DATA_OUT[31:16]. + ''' + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [// read value of masked_* registers yield a different value than written + // avoid writing to masked_out* registers as they affect direct_out value + "excl:CsrNonInitTests:CsrExclAll"], + fields: [ + { bits: "15:0", + name: "data", + desc: '''Write data value[31:16]. + + Value to write into DATA_OUT[i], valid in the presence of mask[i]==1 + ''' + }, + { bits: "31:16", + name: "mask", + desc: '''Write data mask[31:16]. + + A value of 1 in mask[i] allows the updating of DATA_OUT[i], 16 <= i <= 31 + ''' + swaccess: "wo" + }, + ], + }, + { name: "DIRECT_OE", + desc: '''GPIO Output Enable. + + Setting direct_oe[i] to 1 enables output mode for GPIO[i] + ''', + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + fields: [ + { bits: "31:0", + auto_split: "true" + } + ], + }, + { name: "MASKED_OE_LOWER", + desc: '''GPIO write Output Enable lower with mask. + + Masked write for DATA_OE[15:0], the register that controls + output mode for GPIO pins [15:0]. + + Upper 16 bits of this register are used as mask. Writing + lower 16 bits of the register changes DATA_OE[15:0] value + if mask bits are set. + + Read-back of this register returns upper 16 bits as zero + and lower 16 bits as DATA_OE[15:0]. + ''', + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [// read value of masked_* registers yield a different value than written + // avoid writing to masked_oe* registers as they affect direct_oe value + "excl:CsrNonInitTests:CsrExclAll"], + fields: [ + { bits: "15:0", + name: "data", + desc: '''Write OE value[15:0]. + + Value to write into DATA_OE[i], valid in the presence of mask[i]==1 + ''', + }, + { name: "mask", + desc: '''Write OE mask[15:0]. + + A value of 1 in mask[i] allows the updating of DATA_OE[i], 0 <= i <= 15 + ''', + bits: "31:16" + }, + ], + }, + { name: "MASKED_OE_UPPER", + desc: '''GPIO write Output Enable upper with mask. + + Masked write for DATA_OE[31:16], the register that controls + output mode for GPIO pins [31:16]. + + Upper 16 bits of this register are used as mask. Writing + lower 16 bits of the register changes DATA_OE[31:16] value + if mask bits are set. + + Read-back of this register returns upper 16 bits as zero + and lower 16 bits as DATA_OE[31:16]. + ''', + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [// read value of masked_* registers yield a different value than written + // avoid writing to masked_oe* registers as they affect direct_oe value + "excl:CsrNonInitTests:CsrExclAll"], + fields: [ + { bits: "15:0", + name: "data", + desc: '''Write OE value[31:16]. + + Value to write into DATA_OE[i], valid in the presence of mask[i]==1 + ''', + }, + { name: "mask", + desc: '''Write OE mask[31:16]. + + A value of 1 in mask[i] allows the updating of DATA_OE[i], 16 <= i <= 31 + ''', + bits: "31:16" + }, + ], + }, + + { name: "INTR_CTRL_EN_RISING", + desc: '''GPIO interrupt enable for GPIO, rising edge. + + If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_RISING[i] + enables rising-edge interrupt detection on GPIO[i]. + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0" } + ], + }, + { name: "INTR_CTRL_EN_FALLING", + desc: '''GPIO interrupt enable for GPIO, falling edge. + + If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_FALLING[i] + enables falling-edge interrupt detection on GPIO[i]. + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0" } + ], + }, + { name: "INTR_CTRL_EN_LVLHIGH", + desc: '''GPIO interrupt enable for GPIO, level high. + + If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_LVLHIGH[i] + enables level high interrupt detection on GPIO[i]. + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0" } + ], + }, + { name: "INTR_CTRL_EN_LVLLOW", + desc: '''GPIO interrupt enable for GPIO, level low. + + If !!INTR_ENABLE[i] is true, a value of 1 on !!INTR_CTRL_EN_LVLLOW[i] + enables level low interrupt detection on GPIO[i]. + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0" } + ], + }, + { name: "CTRL_EN_INPUT_FILTER", + desc: '''filter enable for GPIO input bits. + + If !!CTRL_EN_INPUT_FILTER[i] is true, a value of input bit [i] + must be stable for 16 cycles before transitioning. + ''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0" } + ], + }, + { name: "HW_STRAPS_DATA_IN_VALID", + desc: "Indicates whether the data in !!HW_STRAPS_DATA_IN is valid.", + swaccess: "ro", + hwaccess: "hrw", + tags: [// Value in the register is determined by GPIO pin values that are sampled + // at system boot time (typically triggered by the power manager). Hence, + // we exclude both init and non-init checks here. + "excl:CsrAllTests:CsrExclAll"], + fields: [ + { bits: "0", + resval: "0" + } + ], + }, + { name: "HW_STRAPS_DATA_IN", + desc: ''' + GPIO input data that was sampled as straps at most once after the block + came out of reset. + + The behavior of this register depends on the GpioAsHwStrapsEn parameter. + - If the parameter is false then the register reads as zero. + - If the parameter is true then GPIO input data is sampled after reset + on the first cycle where the strap_en_i input is high. The + sampled data is then stored in this register. + ''', + swaccess: "ro", + hwaccess: "hrw", + tags: [// Value in the register is determined by GPIO pin values that are sampled + // at system boot time (typically triggered by the power manager). Hence, + // we exclude both init and non-init checks here. + "excl:CsrAllTests:CsrExclAll"], + fields: [ + { bits: "31:0", + resval: "0" + } + ], + }, + { multireg: + { name: "INP_PRD_CNT_CTRL", + cname: "INP_PRD_CNT_CTRL", + desc: "Control register of one input period counter.", + count: "8" + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "enable", + resval: "0", + desc: '''Enable this input period counter. + After enabling, this counter waits for the next relevant edge (see `polarity` field) of the input to start counting. + After that, it counts clock cycles until the next relevant edge. + On that edge, the measurement is complete and the count is stored in the !!INP_PRD_CNT_VAL register of this input period counter. + Then, if the `continuous_mode` field of this register is not set, the counter clears the `enable` field and returns to idle (see description of the `continuous_mode` field for what happens if that field is set). + ''' + }, + { bits: "1", + name: "continuous_mode", + resval: "0", + desc: '''Continuously count the input period. + When one measurement is completed (see description of `enable` field) and this field is set, all of the following apply: + - the wait for a relevant edge will immediately restart, with an internal counter of zero (while !!INP_PRD_CNT_VAL keeps the value of the completed measurement); + - the `enable` field is not cleared. + + This field may only be changed while the `enable` field is zero. + ''' + }, + { bits: "2", + name: "polarity", + resval: "1", + desc: '''Polarity of this input period counter. + If 0, *falling* edges of the input are relevant. + If 1, *rising* edges of the input are relevant. + + This field may only be changed while the `enable` field is zero. + ''' + }, + { bits: "15:8", + name: "input_select", + resval: "0", + desc: '''Index (starting at 0) of the input that this period counter should operate on. + The value must be smaller than the number of inputs (N), as only the `ceil(log2(N))` least significant bits of this field are considered. + + This may only be changed while the `enable` field is zero. + ''' + }, + { bits: "23:16", + name: "prescaler", + resval: "0", + desc: '''Prescaler for this input period counter. + The basic idea is that the value returned in !!INP_PRD_CNT_VAL can be multiplied by the value of this register plus one to obtain the number of `clk_i` cycles between two relevant edges. + + For example, assume the input pattern `00100100`: + - For `prescaler = 0`, !!INP_PRD_CNT_VAL = 2 + - For `prescaler = 1`, !!INP_PRD_CNT_VAL = 1 + + Note that, regardless of the prescaler, the input is sampled at every positive edge of `clk_i`. + The detection of relevant edges is thus not affected by the prescaler. + + This may only be changed while the `enable` field is zero. + ''' + } + ] + }, + }, + { multireg: + { name: "INP_PRD_CNT_VAL", + cname: "INP_PRD_CNT_VAL", + desc: "Output value of one input period counter.", + count: "8", + swaccess: "rc", + hwaccess: "hwo", + fields: [ + { bits: "31:0", + name: "value", + resval: "0", + desc: '''Number of clock cycles in one complete period. + If this contains the value 0, no complete period has been measured since the last time this register got cleared. + The minimum number of clock cycles in one complete period is 1, which is returned when the input inverts for one clock cycle and then inverts again. + + Expected values for some example patterns: + - `01010101` -> 1 + - `00100100` -> 2 + - `00010001` -> 3 + + The counter saturates at the maximum value. + + This register gets cleared after every read from SW. + ''' + } + ] + }, + } + ], +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/gpio_sec_cm_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/gpio_sec_cm_testplan.hjson new file mode 100644 index 00000000000..b0e79320187 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/gpio_sec_cm_testplan.hjson @@ -0,0 +1,33 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../gpio/data/gpio.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../gpio/data/gpio_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: "Verify the countermeasure(s) BUS.INTEGRITY." + stage: V2S + tests: ["gpio_tl_intg_err"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/gpio_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/gpio_testplan.hjson new file mode 100644 index 00000000000..fb4309d1b87 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/gpio_testplan.hjson @@ -0,0 +1,165 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "gpio" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "gpio_sec_cm_testplan.hjson"] + testpoints: [ + { + name: smoke + desc: '''GPIO smoke test that exercises gpio pins as inputs or outputs, and performs + data integrity checks by triggering scoreboard checks by reading data_in register. + This test repeats following steps are random no. of times: + - Configures all gpio pins as inputs, drives random value on cio_gpio_i signal and + reads data_in register after random delay + - Configures all gpio pins as outputs, programs direct_out and direct_oe registers to + random values and reads data_in register after random delay + The test is also run in a second build mode that enables the input synchronizers in + order to cover the input paths through these primitives. + ''' + stage: V1 + tests: ["gpio_smoke", + "gpio_smoke_no_pullup_pulldown", + "gpio_smoke_en_cdc_prim", + "gpio_smoke_no_pullup_pulldown_en_cdc_prim"] + } + { + name: direct_and_masked_out + desc: '''GPIO test that programs `DIRECT_OUT`, `DIRECT_OE`, `MASKED_OUT_LOWER`, + `MASKED_OE_LOWER`, `MASKED_OUT_UPPER` and `MASKED_OE_UPPER` registers and checks their + effect on GPIO pins as well as DATA_IN register value. + Every random iteration in this test would either: + - Program one or more of `\*OUT\*` and `\*OE\*` registers, or + - Drive new random value on GPIO pins''' + stage: V2 + tests: ["gpio_random_dout_din", + "gpio_random_dout_din_no_pullup_pulldown"] + } + { + name: out_in_regs_read_write + desc: '''GPIO test that exercises functionality of DATA_OUT and DATA_OE internal registers, + and `DATA_IN` register by programming any of `\*OUT\` and `\*OE\*` registers, + respectively. + Every random iteration in this test would perform one out of following operations: + - Drive new random value on GPIO pins + - Write random value to any one of `\*OUT\*`, `\*OE\*` or `DATA_IN` registers + - Read any one of `\*OUT\*`, `\*OE\*` or `DATA_IN` registers''' + stage: V2 + tests: ["gpio_dout_din_regs_random_rw"] + } + { + name: gpio_interrupt_programming + desc: '''GPIO test which programs one or multiple interrupt registers to check GPIO interrupt + functionality + Every random iteration in this test would do either of following steps, and then read + `INTR_STATE` register value: + - Drive new random value on GPIO pins (and thereby generate random interrupt event) + - Write random value to one or more interrupt registers that include `INTR_ENABLE`, + `INTR_CTRL_EN_FALLING`, `INTR_CTRL_EN_LVL_LOW`, `INTR_CTRL_EN_LVL_HIGH` and + `INTR_STATE`''' + stage: V2 + tests: ["gpio_intr_rand_pgm"] + } + { + name: random_interrupt_trigger + desc: '''GPIO test that randomly generates and clears multiple GPIO interrupts for each + random programming of interrupt registers, and performs checks by reading `DATA_IN` + and `INTR_STATE` registers. + Each random iteration of this test performs following operations: + 1. Programs one more interrupt registers to random values + 2. Following two operations are performed in parallel: + - Drive random value on GPIO pins multiple times, every time at a random time + intervals (random number of clock cycles) + - Randomize random time interval (random number of clock cycles) and read either + `DATA_IN` or `INTR_STATE` register value at randomized time interval + After every read, optionally perform random interrupt clearing operation by + writing to `INTR_STATE` register''' + stage: V2 + tests: ["gpio_rand_intr_trigger"] + } + { + name: interrupt_and_noise_filter + desc: '''GPIO test that exercise GPIO noise filter functionaliy along with random interrupt + programming and randomly toggling each GPIO pin value, independently of other GPIO pins. + Each random iteration performs following operations: + 1. programs random values in one or more interrupt registers + 2. optionally, programs new random value in `CTRL_EN_INPUT_FILTER` register + 3. performs following operations in parallel: + - drives each GPIO pin independently such that each pin has stable value for random + number of clock cycles within the range `[1:FILTER_CYCLES]`, and also predicts + updates in values of `DATA_IN` and `INTR_STATE` registers + - multiple registers reads, each for either `DATA_IN` or `INTR_STATE`''' + stage: V2 + tests: ["gpio_intr_with_filter_rand_intr_event"] + } + { + name: noise_filter_stress + desc: '''GPIO test that stresses noise filter functionality by driving each GPIO pin such + independently of other pins, and driving could be either synchronous to clock or + asynchronous. + Each iteration in test does following: + 1. Programs one or more interrupt registers with random values + 2. Programs noise filter register with random value + 3. Drives each GPIO pin with the mix of both synchronous and asynchronous driving, + and each pin is driven independently of others''' + stage: V2 + tests: ["gpio_filter_stress"] + } + { + name: regs_long_reads_and_writes + desc: '''GPIO test that performs back-to-back register writes and back-to-back register reads + on randomly selected GPIO registers. + Each iteration in this test performs one out of following operations: + - Drive new random value on GPIO pins + - Perform multiple random writes on randomly selected GPIO registers + - Perform multiple random reads on randomly selected GPIO registers''' + stage: V2 + tests: ["gpio_random_long_reg_writes_reg_reads"] + } + { + name: full_random + desc: '''GPIO full random test that performs any of following in each iteration: + - Drive new random value on GPIO pins such that GPIO inputs and GPIO outputs shall not + result in unknown value on any pin + - Write to one or more of `DIRECT_OUT`, `DIRECT_OE`, `MASKED_OUT_UPPER`, + `MASKED_OE_UPPER`, `MASKED_OE_LOWER` and `MASKED_OE_LOWER` registers such that GPIO + inputs and GPIO outputs shall not result in unknown value on any pin + - Write to one or more of GPIO interrupt registers that include `INTR_ENABLE`, + `INTR_CTRL_EN_FALLING`, `INTR_CTRL_EN_RISING`, `INTR_CTRL_EN_LVL_HIGH`, + `INTR_CTRL_EN_LVL_LOW` and `INTR_STATE` + - Write to other GPIO registers `DATA_IN`, `INTR_TEST`, `CTRL_EN_INPUT_FILTER` + - Read any one of the GPIO registers + - Apply hard reset''' + stage: V2 + tests: ["gpio_full_random"] + } + { + name: stress_all + desc: '''Stress_all test is a random mix of all the test above except csr tests, gpio full + random, intr_test and other gpio test that disabled scoreboard''' + stage: V2 + tests: ["gpio_stress_all"] + } + { + name: straps_data + desc: '''Verify the straps data/valid ouput expected values based on the strap_en and gpio_i inputs: + - Drive gpio_i input with random values. + - Set strap_en high for at least one clock cycle. + - Read the registers hw_straps_data_in and hw_straps_data_in_valid. + - Check the data read and sampled_straps_o in the scoreboard. + - Drive gpio_o and check that has no impact on straps registers. + - Apply a reset and ensure the strap registers are cleared. + - Read straps registers after reset. + - Iterate few times through the same flow again with new random values. Several iterations + will be done using the stress_all virtual sequence. + ''' + stage: V3 + tests: ["gpio_rand_straps"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/top_darjeeling_no_ibex_gpio.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/top_darjeeling_no_ibex_gpio.ipconfig.hjson new file mode 100644 index 00000000000..c69beb7f160 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/data/top_darjeeling_no_ibex_gpio.ipconfig.hjson @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_gpio + param_values: + { + num_inp_period_counters: 8 + module_instance_name: gpio + topname: darjeeling_no_ibex + uniquified_modules: {} + } + dtgen: + { + num_inp_period_counters: + { + type: uint8 + name: input_period_counter_count + doc: number of input period counters + } + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/defs.bzl new file mode 100644 index 00000000000..764cf811fca --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/defs.bzl @@ -0,0 +1,10 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +GPIO = opentitan_ip( + name = "gpio", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/gpio/data:gpio.hjson", + ipconfig = "//hw/top_darjeeling_no_ibex/ip_autogen/gpio/data:top_darjeeling_no_ibex_gpio.ipconfig.hjson", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/checklist.md b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/checklist.md new file mode 100644 index 00000000000..2d68fb2f9b7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/checklist.md @@ -0,0 +1,282 @@ +# GPIO Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [GPIO peripheral][GPIO Spec]. +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [GPIO Spec][] +Documentation | [CSR_DEFINED][] | Done | [GPIO CSR][] +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | N/A | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[GPIO Spec]: ../ +[GPIO CSR]: ../data/gpio.hjson + + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | N/A | +Documentation | [BLOCK_DIAGRAM][] | N/A | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | N/A | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | N/A | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | Fmax 50MHz on NexysVideo +Security | [SEC_CM_DOCUMENTED][] | N/A | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | N/A | +Security | [SEC_CM_SHADOW_REGS][] | N/A | +Security | [SEC_CM_RTL_REVIEWED][] | N/A | +Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A | This block only contains the bus-integrity CM. + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | N/A | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | eunchan@ jeoong@ weicai@ alphan@ +Review | Signoff date | Done | 2022-05-26 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-----------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [gpio_dv_doc][] +Documentation | [TESTPLAN_COMPLETED][] | Done | +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | waived | Revisit later. Tool setup in progress. +Testbench | [TB_GEN_AUTOMATED][] | N/A | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done w/ waivers | Exception (implemented in local) +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done w/ waivers | Exception (implemented in local) +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug) +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[gpio_dv_doc]: ../dv/README.md + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | N/A | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | Resolved: [#680][] +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | N/A | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | N/A | +Tests | [SIM_FW_SIMULATED][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | Resolved: [#807][] +Coverage | [FPV_CODE_COVERAGE_V2][] | N/A | +Coverage | [FPV_COI_COVERAGE_V2][] | N/A | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | N/A | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | [#41][] Not quite related, [#45][] root caused +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[#41]: https://github.com/lowRISC/opentitan/issues/41 +[#45]: https://github.com/lowRISC/opentitan/issues/45 +[#680]: https://github.com/lowRISC/opentitan/pull/680 +[#807]: https://github.com/lowRISC/opentitan/pull/807 + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_VERIFIED][] | N/A | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | +Review | [SEC_CM_DV_REVIEWED][] | Done | Waived the V2S review meeting, since only 1 standard sec_cm - bus integrity. + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | N/A | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Waived | Revisit later. Tool setup in progress. +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Done | Resolved: [#680][] +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Done | [common_cov_excl.el][], [gpio_cov_excl.el][] +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Done | [#807][] +Coverage | [FPV_CODE_COVERAGE_AT_100][] | N/A | +Coverage | [FPV_COI_COVERAGE_AT_100][] | N/A | +Code Quality | [ALL_TODOS_RESOLVED][] | Done | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Done | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | N/A | +Issues | [NO_ISSUES_PENDING][] | Done | +Review | Reviewer(s) | Done | @eunchan @sriyerg @sjgitty +Review | Signoff date | Done | 2019-11-04 + +[#807]: https://github.com/lowRISC/opentitan/pull/807 + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending + +[common_cov_excl.el]:https://github.com/lowRISC/opentitan/blob/9dff09b6c57f4962d67f5f64f8e69ac9bea6885c/hw/dv/tools/vcs/common_cov_excl.el +[gpio_cov_excl.el]: https://github.com/lowRISC/opentitan/blob/39aaeefdb43661b065c29ceab2efc1065aebf6dd/hw/ip/gpio/dv/cov/gpio_cov_excl.el diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/gpio_blockdiagram.svg b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/gpio_blockdiagram.svg new file mode 100644 index 00000000000..9dabed62f33 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/gpio_blockdiagram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/gpio_output.svg b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/gpio_output.svg new file mode 100644 index 00000000000..c9459822689 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/gpio_output.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/interfaces.md b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/interfaces.md new file mode 100644 index 00000000000..31546f5eccd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/interfaces.md @@ -0,0 +1,45 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`gpio`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: *none* +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* + +## Peripheral Pins for Chip IO + +| Pin name | Direction | Description | +|:-----------|:------------|:-----------------------| +| gpio[31:0] | inout | GPIO inout to/from PAD | + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:---------------|:------------------------------|:--------|:------|--------:|:--------------------------------------------------------------------------------------------------------------------------------------------| +| strap_en | logic | uni | rcv | 1 | The strap enable signal tells gpio to take a snapshot of the input pins. The behaviour of this signal after that event will have no effect. | +| sampled_straps | gpio_pkg::gpio_straps | uni | req | 1 | This vector contains the sampled strap values. | +| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register. | +| racl_error | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Interrupts + +| Interrupt Name | Type | Description | +|:-----------------|:-------|:------------------------------------------------------------| +| gpio[31:0] | Event | raised if any of GPIO pin detects configured interrupt mode | + +## Security Alerts + +| Alert Name | Description | +|:-------------|:----------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:--------------------|:---------------------------------| +| GPIO.BUS.INTEGRITY | End-to-end bus integrity scheme. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/programmers_guide.md b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/programmers_guide.md new file mode 100644 index 00000000000..d101520f500 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/programmers_guide.md @@ -0,0 +1,140 @@ +# Programmer's Guide + +## Initialization + +Initialization of the GPIO module includes the setting up of the interrupt +configuration for each GPIO input, as well as the configuration of +the required noise filtering. These do not provide masked access since +they are not expected to be done frequently. + +```cpp +// enable inputs 0 and 1 for rising edge detection with filtering, +// inputs 2 and 3 for falling edge detection with filtering, +// input 4 for both rising edge detection (no filtering) +// and inputs 6 and 7 for active low interrupt detection +*GPIO_INTR_ENABLE = 0b11011111; +*GPIO_INTR_CTRL_EN_RISING = 0b00010011; +*GPIO_INTR_CTRL_EN_FALLING = 0b00011100; +*GPIO_INTR_CTRL_EN_LVLLOW = 0b11000000; +*GPIO_INTR_CTRL_EN_LVLHIGH = 0b00000000; +*GPIO_CTRL_EN_INPUT_FILTER = 0b00001111; +``` + +## Common Examples + +This section below shows the interaction between the direct access +and mask access for data output and data enable. + +```cpp +// assume all GPIO are connected to chip pads. +// assume a weak pullup on all pads, returning 1 if undriven. +printf("0x%x", *GPIO_DATA_IN); // 0xffffffff + +*DIRECT_OUT = 0x11223344; +printf("0x%x", *GPIO_DIRECT_OUT); // 0x11223344 + +*DIRECT_OE = 0x00ff00ff; +printf("0x%x", *GPIO_DIRECT_OE); // 0x00ff00ff + +// weak pullup still applies to undriven signals +printf("0x%x", *GPIO_DATA_IN); // 0xff22ff44 + +// read of direct_out still returns DATA_OUT contents +printf("0x%x", *GPIO_DIRECT_OUT); // 0x11223344 + +// try masked accesses to DATA_OUT +*GPIO_MASKED_OUT_LOWER = 0x0f0f5566 +printf("0x%x", *GPIO_MASKED_OUT_LOWER); // 0x00003546 +printf("0x%x", *GPIO_DIRECT_OUT); // 0x11223546 + +*GPIO_MASKED_OUT_UPPER = 0x0f0f7788 +printf("0x%x", *GPIO_MASKED_OUT_UPPER); // 0x00001728 +printf("0x%x", *GPIO_DIRECT_OUT); // 0x17283546 + +// OE still applies +printf("0x%x", *GPIO_DATA_IN); // 0xff28ff46 + +// manipulate OE +*GPIO_DIRECT_OE = 0xff00ff00; +printf("0x%x", *GPIO_DIRECT_OE); // 0xff00ff00 +printf("0x%x", *GPIO_DATA_IN); // 0x17ff35ff + +*GPIO_MASKED_OE_LOWER = 0x0f0f0f0f; +printf("0x%x", *GPIO_MASKED_OE_LOWER); // 0x00000f0f +printf("0x%x", *GPIO_DIRECT_OE); // 0xff000f0f +printf("0x%x", *GPIO_DATA_IN); // 0x17fff5f6 + +*GPIO_MASKED_OE_UPPER = 0x0f0f0f0f; +printf("0x%x", *GPIO_MASKED_OE_UPPER); // 0x00000f0f +printf("0x%x", *GPIO_DIRECT_OE); // 0x0f0f0f0f +printf("0x%x", *GPIO_DATA_IN); // 0xf7f8f5f6 +``` + +## Interrupt Handling + +This section below gives an example of how interrupt clearing works, +assuming some events have occurred as shown in comments. + +```cpp +*INTR_ENABLE = 0x000000ff; // interrupts enabled GPIO[7:0] inputs +printf("0b%x", *GPIO_DATA_IN); // assume 0b00000000 +printf("0b%x", *GPIO_INTR_STATE); // 0b00000000 + +*INTR_CTRL_EN_RISING = 0b00010001; // rising detect on GPIO[0], GPIO[4] +*INTR_CTRL_EN_FALLING = 0b00010010; // falling detect on GPIO[1], GPIO[4] +*INTR_CTRL_EN_LVLLOW = 0b00001100; // falling detect on GPIO[2], GPIO[3] +*INTR_CTRL_EN_LVLHIGH = 0b11000000; // falling detect on GPIO[6], GPIO[7] + +// already detected intr[3,2] (level low) +printf("0b%b", *GPIO_INTR_STATE); // 0b00001100 + +// try and clear [3:2], fails since still active low +*GPIO_INTR_STATE = 0b00001100; +printf("0b%b", *GPIO_INTR_STATE); // 0b00001100 + +// EVENT: all bits [7:0] rising, triggers [7,6,4,0], [3,2] still latched +printf("0b%b", *GPIO_DATA_IN); // 0b11111111 +printf("0b%b", *GPIO_INTR_STATE); // 0b11011101 + +// try and clear all bits, [7,6] still detecting level high +*GPIO_INTR_STATE = 0b11111111; +printf("0b%b", *GPIO_INTR_STATE); // 0b11000000 + +// EVENT: all bits [7:0] falling, triggers [4,3,2,1], [7,6] still latched +printf("0b%b", *GPIO_DATA_IN); // 0b00000000 +printf("0b%b", *GPIO_INTR_STATE); // 0b11011110 + +// try and clear all bits, [3,2] still detecting level low +*GPIO_INTR_STATE = 0b11111111; +printf("0b%b", *GPIO_INTR_STATE); // 0b00001100 + +// write test register for all 8 events, trigger regardless of external events +*GPIO_INTR_TEST = 0b11111111; +printf("0b%b", *GPIO_INTR_STATE); // 0b11111111 + +// try and clear all bits, [3,2] still detecting level low +*GPIO_INTR_STATE = 0b11111111; +printf("0b%b", *GPIO_INTR_STATE); // 0b00001100 + +``` + +## Input Period Counters + +Each of the 8 input period counters can be configured, enabled and disabled, and +read out independently. +The programming flow is as follows: +1. Configure the counter using the `INP_PRD_CNT_CTRL` bits except `enable`. +2. Enable the counter by setting the `enable` bit to `1`. +3. Read the measured period from `INP_PRD_CNT_VAL`. If you read `0`, no complete + period has happened yet. If you read a non-zero value, that's the number of + clock cycles (prescaled if configured) from one relevant edge of the input + to the next. After your read, the `INP_PRD_CNT_VAL` register will be cleared + to zero, so you can read it again and determine based on the returned value + whether a new complete period has been measured or not. +4. If continuous mode is not enabled, the counter will disable itself after one + complete input period. Otherwise, disable it as needed by setting the + `enable` bit of `INP_PRD_CNT_CTRL` to `0`. + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_gpio.h) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/registers.md b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/registers.md new file mode 100644 index 00000000000..dd43f02bf22 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/registers.md @@ -0,0 +1,519 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:-----------------------------------------------------------|:---------|---------:|:----------------------------------------------------------------------------------| +| gpio.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | +| gpio.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | +| gpio.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | +| gpio.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | +| gpio.[`DATA_IN`](#data_in) | 0x10 | 4 | GPIO Input data read value | +| gpio.[`DIRECT_OUT`](#direct_out) | 0x14 | 4 | GPIO direct output data write value | +| gpio.[`MASKED_OUT_LOWER`](#masked_out_lower) | 0x18 | 4 | GPIO write data lower with mask. | +| gpio.[`MASKED_OUT_UPPER`](#masked_out_upper) | 0x1c | 4 | GPIO write data upper with mask. | +| gpio.[`DIRECT_OE`](#direct_oe) | 0x20 | 4 | GPIO Output Enable. | +| gpio.[`MASKED_OE_LOWER`](#masked_oe_lower) | 0x24 | 4 | GPIO write Output Enable lower with mask. | +| gpio.[`MASKED_OE_UPPER`](#masked_oe_upper) | 0x28 | 4 | GPIO write Output Enable upper with mask. | +| gpio.[`INTR_CTRL_EN_RISING`](#intr_ctrl_en_rising) | 0x2c | 4 | GPIO interrupt enable for GPIO, rising edge. | +| gpio.[`INTR_CTRL_EN_FALLING`](#intr_ctrl_en_falling) | 0x30 | 4 | GPIO interrupt enable for GPIO, falling edge. | +| gpio.[`INTR_CTRL_EN_LVLHIGH`](#intr_ctrl_en_lvlhigh) | 0x34 | 4 | GPIO interrupt enable for GPIO, level high. | +| gpio.[`INTR_CTRL_EN_LVLLOW`](#intr_ctrl_en_lvllow) | 0x38 | 4 | GPIO interrupt enable for GPIO, level low. | +| gpio.[`CTRL_EN_INPUT_FILTER`](#ctrl_en_input_filter) | 0x3c | 4 | filter enable for GPIO input bits. | +| gpio.[`HW_STRAPS_DATA_IN_VALID`](#hw_straps_data_in_valid) | 0x40 | 4 | Indicates whether the data in [`HW_STRAPS_DATA_IN`](#hw_straps_data_in) is valid. | +| gpio.[`HW_STRAPS_DATA_IN`](#hw_straps_data_in) | 0x44 | 4 | GPIO input data that was sampled as straps at most once after the block | +| gpio.[`INP_PRD_CNT_CTRL_0`](#inp_prd_cnt_ctrl) | 0x48 | 4 | Control register of one input period counter. | +| gpio.[`INP_PRD_CNT_CTRL_1`](#inp_prd_cnt_ctrl) | 0x4c | 4 | Control register of one input period counter. | +| gpio.[`INP_PRD_CNT_CTRL_2`](#inp_prd_cnt_ctrl) | 0x50 | 4 | Control register of one input period counter. | +| gpio.[`INP_PRD_CNT_CTRL_3`](#inp_prd_cnt_ctrl) | 0x54 | 4 | Control register of one input period counter. | +| gpio.[`INP_PRD_CNT_CTRL_4`](#inp_prd_cnt_ctrl) | 0x58 | 4 | Control register of one input period counter. | +| gpio.[`INP_PRD_CNT_CTRL_5`](#inp_prd_cnt_ctrl) | 0x5c | 4 | Control register of one input period counter. | +| gpio.[`INP_PRD_CNT_CTRL_6`](#inp_prd_cnt_ctrl) | 0x60 | 4 | Control register of one input period counter. | +| gpio.[`INP_PRD_CNT_CTRL_7`](#inp_prd_cnt_ctrl) | 0x64 | 4 | Control register of one input period counter. | +| gpio.[`INP_PRD_CNT_VAL_0`](#inp_prd_cnt_val) | 0x68 | 4 | Output value of one input period counter. | +| gpio.[`INP_PRD_CNT_VAL_1`](#inp_prd_cnt_val) | 0x6c | 4 | Output value of one input period counter. | +| gpio.[`INP_PRD_CNT_VAL_2`](#inp_prd_cnt_val) | 0x70 | 4 | Output value of one input period counter. | +| gpio.[`INP_PRD_CNT_VAL_3`](#inp_prd_cnt_val) | 0x74 | 4 | Output value of one input period counter. | +| gpio.[`INP_PRD_CNT_VAL_4`](#inp_prd_cnt_val) | 0x78 | 4 | Output value of one input period counter. | +| gpio.[`INP_PRD_CNT_VAL_5`](#inp_prd_cnt_val) | 0x7c | 4 | Output value of one input period counter. | +| gpio.[`INP_PRD_CNT_VAL_6`](#inp_prd_cnt_val) | 0x80 | 4 | Output value of one input period counter. | +| gpio.[`INP_PRD_CNT_VAL_7`](#inp_prd_cnt_val) | 0x84 | 4 | Output value of one input period counter. | + +## INTR_STATE +Interrupt State Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw1c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------| +| 31:0 | rw1c | 0x0 | gpio | raised if any of GPIO pin detects configured interrupt mode | + +## INTR_ENABLE +Interrupt Enable Register +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "gpio", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------| +| 31:0 | rw | 0x0 | gpio | Enable interrupt when corresponding bit in [`INTR_STATE.gpio`](#intr_state) is set. | + +## INTR_TEST +Interrupt Test Register +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "gpio", "bits": 32, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------| +| 31:0 | wo | 0x0 | gpio | Write 1 to force corresponding bit in [`INTR_STATE.gpio`](#intr_state) to 1. | + +## ALERT_TEST +Alert Test Register +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:-------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | + +## DATA_IN +GPIO Input data read value +- Offset: `0x10` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "DATA_IN", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:0 | ro | x | DATA_IN | | + +## DIRECT_OUT +GPIO direct output data write value +- Offset: `0x14` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "DIRECT_OUT", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------|:--------------| +| 31:0 | rw | x | DIRECT_OUT | | + +## MASKED_OUT_LOWER +GPIO write data lower with mask. + +Masked write for DATA_OUT[15:0]. + +Upper 16 bits of this register are used as mask. Writing +lower 16 bits of the register changes DATA_OUT[15:0] value +if mask bits are set. + +Read-back of this register returns upper 16 bits as zero +and lower 16 bits as DATA_OUT[15:0]. +- Offset: `0x18` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------| +| 31:16 | wo | x | mask | Write data mask[15:0]. A value of 1 in mask[i] allows the updating of DATA_OUT[i], 0 <= i <= 15 | +| 15:0 | rw | x | data | Write data value[15:0]. Value to write into DATA_OUT[i], valid in the presence of mask[i]==1 | + +## MASKED_OUT_UPPER +GPIO write data upper with mask. + +Masked write for DATA_OUT[31:16]. + +Upper 16 bits of this register are used as mask. Writing +lower 16 bits of the register changes DATA_OUT[31:16] value +if mask bits are set. + +Read-back of this register returns upper 16 bits as zero +and lower 16 bits as DATA_OUT[31:16]. +- Offset: `0x1c` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["wo"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------| +| 31:16 | wo | x | mask | Write data mask[31:16]. A value of 1 in mask[i] allows the updating of DATA_OUT[i], 16 <= i <= 31 | +| 15:0 | rw | x | data | Write data value[31:16]. Value to write into DATA_OUT[i], valid in the presence of mask[i]==1 | + +## DIRECT_OE +GPIO Output Enable. + +Setting direct_oe[i] to 1 enables output mode for GPIO[i] +- Offset: `0x20` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "DIRECT_OE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:--------------| +| 31:0 | rw | x | DIRECT_OE | | + +## MASKED_OE_LOWER +GPIO write Output Enable lower with mask. + +Masked write for DATA_OE[15:0], the register that controls +output mode for GPIO pins [15:0]. + +Upper 16 bits of this register are used as mask. Writing +lower 16 bits of the register changes DATA_OE[15:0] value +if mask bits are set. + +Read-back of this register returns upper 16 bits as zero +and lower 16 bits as DATA_OE[15:0]. +- Offset: `0x24` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------| +| 31:16 | rw | x | mask | Write OE mask[15:0]. A value of 1 in mask[i] allows the updating of DATA_OE[i], 0 <= i <= 15 | +| 15:0 | rw | x | data | Write OE value[15:0]. Value to write into DATA_OE[i], valid in the presence of mask[i]==1 | + +## MASKED_OE_UPPER +GPIO write Output Enable upper with mask. + +Masked write for DATA_OE[31:16], the register that controls +output mode for GPIO pins [31:16]. + +Upper 16 bits of this register are used as mask. Writing +lower 16 bits of the register changes DATA_OE[31:16] value +if mask bits are set. + +Read-back of this register returns upper 16 bits as zero +and lower 16 bits as DATA_OE[31:16]. +- Offset: `0x28` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "data", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "mask", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------| +| 31:16 | rw | x | mask | Write OE mask[31:16]. A value of 1 in mask[i] allows the updating of DATA_OE[i], 16 <= i <= 31 | +| 15:0 | rw | x | data | Write OE value[31:16]. Value to write into DATA_OE[i], valid in the presence of mask[i]==1 | + +## INTR_CTRL_EN_RISING +GPIO interrupt enable for GPIO, rising edge. + +If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_RISING`](#intr_ctrl_en_rising)[i] +enables rising-edge interrupt detection on GPIO[i]. +- Offset: `0x2c` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "INTR_CTRL_EN_RISING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:--------------| +| 31:0 | rw | 0x0 | INTR_CTRL_EN_RISING | | + +## INTR_CTRL_EN_FALLING +GPIO interrupt enable for GPIO, falling edge. + +If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_FALLING`](#intr_ctrl_en_falling)[i] +enables falling-edge interrupt detection on GPIO[i]. +- Offset: `0x30` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "INTR_CTRL_EN_FALLING", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------------|:--------------| +| 31:0 | rw | 0x0 | INTR_CTRL_EN_FALLING | | + +## INTR_CTRL_EN_LVLHIGH +GPIO interrupt enable for GPIO, level high. + +If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_LVLHIGH`](#intr_ctrl_en_lvlhigh)[i] +enables level high interrupt detection on GPIO[i]. +- Offset: `0x34` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "INTR_CTRL_EN_LVLHIGH", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------------|:--------------| +| 31:0 | rw | 0x0 | INTR_CTRL_EN_LVLHIGH | | + +## INTR_CTRL_EN_LVLLOW +GPIO interrupt enable for GPIO, level low. + +If [`INTR_ENABLE`](#intr_enable)[i] is true, a value of 1 on [`INTR_CTRL_EN_LVLLOW`](#intr_ctrl_en_lvllow)[i] +enables level low interrupt detection on GPIO[i]. +- Offset: `0x38` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "INTR_CTRL_EN_LVLLOW", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:--------------| +| 31:0 | rw | 0x0 | INTR_CTRL_EN_LVLLOW | | + +## CTRL_EN_INPUT_FILTER +filter enable for GPIO input bits. + +If [`CTRL_EN_INPUT_FILTER`](#ctrl_en_input_filter)[i] is true, a value of input bit [i] +must be stable for 16 cycles before transitioning. +- Offset: `0x3c` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "CTRL_EN_INPUT_FILTER", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------------|:--------------| +| 31:0 | rw | 0x0 | CTRL_EN_INPUT_FILTER | | + +## HW_STRAPS_DATA_IN_VALID +Indicates whether the data in [`HW_STRAPS_DATA_IN`](#hw_straps_data_in) is valid. +- Offset: `0x40` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "HW_STRAPS_DATA_IN_VALID", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------------|:--------------| +| 31:1 | | | | Reserved | +| 0 | ro | 0x0 | HW_STRAPS_DATA_IN_VALID | | + +## HW_STRAPS_DATA_IN +GPIO input data that was sampled as straps at most once after the block +came out of reset. + +The behavior of this register depends on the GpioAsHwStrapsEn parameter. +- If the parameter is false then the register reads as zero. +- If the parameter is true then GPIO input data is sampled after reset +on the first cycle where the strap_en_i input is high. The +sampled data is then stored in this register. +- Offset: `0x44` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "HW_STRAPS_DATA_IN", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------|:--------------| +| 31:0 | ro | 0x0 | HW_STRAPS_DATA_IN | | + +## INP_PRD_CNT_CTRL +Control register of one input period counter. +- Reset default: `0x4` +- Reset mask: `0xffff07` + +### Instances + +| Name | Offset | +|:-------------------|:---------| +| INP_PRD_CNT_CTRL_0 | 0x48 | +| INP_PRD_CNT_CTRL_1 | 0x4c | +| INP_PRD_CNT_CTRL_2 | 0x50 | +| INP_PRD_CNT_CTRL_3 | 0x54 | +| INP_PRD_CNT_CTRL_4 | 0x58 | +| INP_PRD_CNT_CTRL_5 | 0x5c | +| INP_PRD_CNT_CTRL_6 | 0x60 | +| INP_PRD_CNT_CTRL_7 | 0x64 | + + +### Fields + +```wavejson +{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "continuous_mode", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "polarity", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 5}, {"name": "input_select", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "prescaler", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:------------------------------------------------------| +| 31:24 | | | Reserved | +| 23:16 | rw | 0x0 | [prescaler](#inp_prd_cnt_ctrl--prescaler) | +| 15:8 | rw | 0x0 | [input_select](#inp_prd_cnt_ctrl--input_select) | +| 7:3 | | | Reserved | +| 2 | rw | 0x1 | [polarity](#inp_prd_cnt_ctrl--polarity) | +| 1 | rw | 0x0 | [continuous_mode](#inp_prd_cnt_ctrl--continuous_mode) | +| 0 | rw | 0x0 | [enable](#inp_prd_cnt_ctrl--enable) | + +### INP_PRD_CNT_CTRL . prescaler +Prescaler for this input period counter. +The basic idea is that the value returned in [`INP_PRD_CNT_VAL`](#inp_prd_cnt_val) can be multiplied by the value of this register plus one to obtain the number of `clk_i` cycles between two relevant edges. + +For example, assume the input pattern `00100100`: +- For `prescaler = 0`, [`INP_PRD_CNT_VAL`](#inp_prd_cnt_val) = 2 +- For `prescaler = 1`, [`INP_PRD_CNT_VAL`](#inp_prd_cnt_val) = 1 + +Note that, regardless of the prescaler, the input is sampled at every positive edge of `clk_i`. +The detection of relevant edges is thus not affected by the prescaler. + +This may only be changed while the `enable` field is zero. + +### INP_PRD_CNT_CTRL . input_select +Index (starting at 0) of the input that this period counter should operate on. +The value must be smaller than the number of inputs (N), as only the `ceil(log2(N))` least significant bits of this field are considered. + +This may only be changed while the `enable` field is zero. + +### INP_PRD_CNT_CTRL . polarity +Polarity of this input period counter. +If 0, *falling* edges of the input are relevant. +If 1, *rising* edges of the input are relevant. + +This field may only be changed while the `enable` field is zero. + +### INP_PRD_CNT_CTRL . continuous_mode +Continuously count the input period. +When one measurement is completed (see description of `enable` field) and this field is set, all of the following apply: +- the wait for a relevant edge will immediately restart, with an internal counter of zero (while [`INP_PRD_CNT_VAL`](#inp_prd_cnt_val) keeps the value of the completed measurement); +- the `enable` field is not cleared. + +This field may only be changed while the `enable` field is zero. + +### INP_PRD_CNT_CTRL . enable +Enable this input period counter. +After enabling, this counter waits for the next relevant edge (see `polarity` field) of the input to start counting. +After that, it counts clock cycles until the next relevant edge. +On that edge, the measurement is complete and the count is stored in the [`INP_PRD_CNT_VAL`](#inp_prd_cnt_val) register of this input period counter. +Then, if the `continuous_mode` field of this register is not set, the counter clears the `enable` field and returns to idle (see description of the `continuous_mode` field for what happens if that field is set). + +## INP_PRD_CNT_VAL +Output value of one input period counter. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:------------------|:---------| +| INP_PRD_CNT_VAL_0 | 0x68 | +| INP_PRD_CNT_VAL_1 | 0x6c | +| INP_PRD_CNT_VAL_2 | 0x70 | +| INP_PRD_CNT_VAL_3 | 0x74 | +| INP_PRD_CNT_VAL_4 | 0x78 | +| INP_PRD_CNT_VAL_5 | 0x7c | +| INP_PRD_CNT_VAL_6 | 0x80 | +| INP_PRD_CNT_VAL_7 | 0x84 | + + +### Fields + +```wavejson +{"reg": [{"name": "value", "bits": 32, "attr": ["rc"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:---------------------------------| +| 31:0 | rc | 0x0 | [value](#inp_prd_cnt_val--value) | + +### INP_PRD_CNT_VAL . value +Number of clock cycles in one complete period. +If this contains the value 0, no complete period has been measured since the last time this register got cleared. +The minimum number of clock cycles in one complete period is 1, which is returned when the input inverts for one clock cycle and then inverts again. + +Expected values for some example patterns: +- `01010101` -> 1 +- `00100100` -> 2 +- `00010001` -> 3 + +The counter saturates at the maximum value. + +This register gets cleared after every read from SW. + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/theory_of_operation.md b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/theory_of_operation.md new file mode 100644 index 00000000000..3387c0af4bd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/doc/theory_of_operation.md @@ -0,0 +1,134 @@ +# Theory of Operation + +## Block Diagram + +![GPIO Block Diagram](../doc/gpio_blockdiagram.svg) + +The block diagram above shows the `DATA_OUT` and `DATA_OE` registers +managed by hardware outside of the auto-generated register file. +For reference, it also shows the assumed connections to pads in +the top level netlist. + +## Design Details + +### GPIO Output logic + +![GPIO Output Diagram](../doc/gpio_output.svg) + +The GPIO module maintains one 32-bit output register `DATA_OUT` with two +ways to write to it. Direct write access uses [`DIRECT_OUT`](registers.md#direct_out), and +masked access uses [`MASKED_OUT_UPPER`](registers.md#masked_out_upper) and +[`MASKED_OUT_LOWER`](registers.md#masked_out_lower). Direct access provides full write and read +access for all 32 bits in one register. + +For masked access the bits to modify are given as a mask in the upper +16 bits of the [`MASKED_OUT_UPPER`](registers.md#masked_out_upper) and +[`MASKED_OUT_LOWER`](registers.md#masked_out_lower) register write, while the data to write is +provided in the lower 16 bits of the register write. The hardware updates +`DATA_OUT` with the mask so that the modification is done without software +requiring a Read-Modify-Write. + +Reads of masked registers return the lower/upper 16 bits of the `DATA_OUT` +contents. Zeros are returned in the upper 16 bits (mask field). To read +what is on the pins, software should read the [`DATA_IN`](registers.md#data_in) register. +(See [GPIO Input](#gpio-input) section below). + +The same concept is duplicated for the output enable register `DATA_OE`. +Direct access uses [`DIRECT_OE`](registers.md#direct_oe), and masked access is available +using [`MASKED_OE_UPPER`](registers.md#masked_oe_upper) and [`MASKED_OE_LOWER`](registers.md#masked_oe_lower). + +The output enable is sent to the pad control block to determine if the +pad should drive the `DATA_OUT` value to the associated pin or not. + +A typical use pattern is for initialization and suspend/resume code to +use the full access registers to set the output enables and current output +values, then switch to masked access for both `DATA_OUT` and `DATA_OE`. + +For GPIO outputs that are not used (either not wired to a pin output or +not selected for pin multiplexing), the output values are disconnected +and have no effect on the GPIO input, regardless of output enable values. + +### GPIO Input + +The [`DATA_IN`](registers.md#data_in) register returns the contents as seen on the +peripheral input, typically from the pads connected to those inputs. In the +presence of a pin-multiplexing unit, GPIO peripheral inputs that are +not connected to a chip input will be tied to a constant zero input. + +The GPIO module provides optional independent noise filter control for +each of the 32 input signals. Each input can be independently enabled with +the [`CTRL_EN_INPUT_FILTER`](registers.md#ctrl_en_input_filter) (one bit per input). This 16-cycle +filter is applied to both the [`DATA_IN`](registers.md#data_in) register and +the interrupt detection logic. The timing for [`DATA_IN`](registers.md#data_in) is still +not instantaneous if [`CTRL_EN_INPUT_FILTER`](registers.md#ctrl_en_input_filter) is false as there is +top-level routing involved, but no flops are between the chip input and the +[`DATA_IN`](registers.md#data_in) register. + +The contents of [`DATA_IN`](registers.md#data_in) are always readable and reflect the +value seen at the chip input pad regardless of the output enable setting from +DATA_OE. If the output enable is true (and the GPIO is connected to a +chip-level pad), the value read from [`DATA_IN`](registers.md#data_in) includes the +effect of the peripheral's driven output (so will only differ from DATA_OUT if +the output driver is unable to switch the pin or during the delay imposed +if the noise filter is enabled). + +#### GPIO Inputs as HW Straps + +The GPIO controller provides an optional feature to sample GPIO input values as hardware configuration straps. +After each reset, on the first cycle when the `strap_en_i` signal is asserted, the GPIO detects its transition from low to high. +One clock cycle later, it samples the GPIO input values and stores them in the `HW_STRAPS_DATA_IN` register. +The `strap_en_i` signal transition from low to high is expected only once after the reset process. +Sampling occurs exclusively at this time, and any subsequent changes to the GPIO input configuration will not be captured. +This mechanism samples all 32 bits of the GPIO input data, regardless of the GPIO output enable status, providing a reliable snapshot of the input values for firmware access. + + +### Interrupts + +The GPIO module provides 32 interrupt signals to the main processor. +Each interrupt can be independently enabled, tested, and configured. +Following the standard interrupt guidelines in the [Comportability +Specification](../../../../../doc/contributing/hw/comportability/README.md), +the 32 bits of the [`INTR_ENABLE`](registers.md#intr_enable) register determines whether the +associated inputs are configured to detect interrupt events. If enabled +via the various `INTR_CTRL_EN` registers, their current state can be +read in the [`INTR_STATE`](registers.md#intr_state) register. Clearing is done by writing a +`1` into the associated [`INTR_STATE`](registers.md#intr_state) bit field. + +For configuration, there are 4 types of interrupts available per bit, +controlled with four control registers. [`INTR_CTRL_EN_RISING`](registers.md#intr_ctrl_en_rising) +configures the associated input for rising-edge detection. +Similarly, [`INTR_CTRL_EN_FALLING`](registers.md#intr_ctrl_en_falling) detects falling edge inputs. +[`INTR_CTRL_EN_LVLHIGH`](registers.md#intr_ctrl_en_lvlhigh) and [`INTR_CTRL_EN_LVLLOW`](registers.md#intr_ctrl_en_lvllow) +allow the input to be level sensitive interrupts. In theory an input can be +configured to detect both a rising and falling edge, but there is no hardware +assistance to indicate which edge caused the output interrupt. + +**Note #1:** The interrupt can only be triggered by GPIO input. +**Note #2:** All inputs are sent through optional noise filtering before being sent into interrupt detection. +**Note #3:** All interrupts to the processor are level interrupts as per the Comportability Specification guidelines. +The GPIO module, if configured, converts an edge detection into a level interrupt to the processor core. + +### Input Period Counters + +The GPIO module provides 8 (number configurable through a template parameter) input period counters. +Each of those is independent of the others, and each can be independently configured, enabled and disabled, and read out. +A user guide to the counters is provided in the [register documentation](registers.md) and in the [programmer's guide](programmers_guide.md). +The following is a description of the internal mechanics of each of the input period counters. + +The selected input is sampled on every positive edge of `clk_i`. + +The relevant edge is detected based on the polarity: if the polarity is high, a rising edge is detected if the currently sampled input is low and the new sampled input is high; vice-versa if the polarity is low. + +A prescaler counter increments when the input period counter is enabled until the configured prescaler value is reached, then the prescaler counter resets to 0. +For a configured prescaler of 0, the prescaler counter will reach the value in every cycle; for a configured prescaler of 1, the prescaler will reach the value in every second cycle, and so on. +When the prescaler reaches the configured value and the input period counter is enabled, that's an internal event. + +A simple FSM controls the actual period counter. +When the input period counter is disabled, the FSM clears to the *disabled* state. +When the input period counter is enabled, the FSM goes into the *pre opening edge* state. +In the *pre opening edge* state, the FSM waits for a relevant edge that starts the period counting (the "opening" edge). +When that edge occurs, the counter starts incrementing and the FSM goes into the *pre closing edge* state. +In the *pre closing edge* state, the counter keeps incrementing on every prescaler event until the next relevant edge. +When the next relevant edge is detected, the counter value is propagated to the SW-visible register and the counter gets cleared to zero. +If continuous mode is not enabled, the `enable` bit in the control register is cleared and the FSM goes back to the *disabled* state. +Otherwise, the FSM stays in the *pre closing edge* state and repeats the actions described for that state. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/README.md new file mode 100644 index 00000000000..a24a6364f64 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/README.md @@ -0,0 +1,114 @@ +# GPIO DV document + +## Goals +* **DV** + * Verify all GPIO IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + +## Current status +* [Design & verification stage](../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/ip/gpio/dv/latest/report.html) + +## Design features +For detailed information on GPIO design features, please see the [GPIO design specification](../README.md). + +## Testbench architecture +GPIO testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at `gpio/dv/tb/tb.sv`. It instantiates the GPIO DUT module `pio/rtl/gpio.sv`. +In addition, it instantiates the following interfaces and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* GPIO IOs ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [common_ifs](../../../../dv/sv/common_ifs/README.md) +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Global types & methods +All common types and methods defined at the package level can be found in `gpio_env_pkg`. Some of them in use are: +```systemverilog +parameter uint NUM_GPIOS = 32; +parameter uint FILTER_CYCLES = 16; +``` +### TL_agent +GPIO testbench instantiates (handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into GPIO device. + +### UVM RAL Model +The GPIO RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md): + +### Stimulus strategy +#### Test sequences +All test sequences reside in `hw/ip/gpio/dv/env/seq_lib`. +The `gpio_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +All test sequences are extended from `gpio_base_vseq`. It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: + +* `set_gpio_pulls`: This function overrides values of `pullup_en` and `pulldown_en` members of randomized `gpio_env_cfg` +* `drive_gpio_in`: This task writes all bits of `direct_oe` register to 0's first and then drives specified value on dut GPIO inputs +* `undrive_gpio_in`: This task drives all dut GPIO inputs to 'z' values, so that dut GPIO outputs may be driven + +#### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met: + +* `gpio_pin_values_cov_obj`: Covers values and transitions on all GPIO IOs +* `intr_state_cov_obj`: Covers `intr_state` values and transitions for all GPIO interrupts +* `intr_ctrl_en_cov_objs`: Covers values and transitions on all bits of following interrupt control enable registers: + * `intr_ctrl_en_rising` + * `intr_ctrl_en_falling` + * `intr_ctrl_en_lvlhigh` + * `intr_ctrl_en_lvllow` +* `intr_event_type_cov_objs`: Covers all GPIO interrupts with following interrupt control registers and their cross coverage with `intr_enable` and `intr_state`: + * `intr_ctrl_en_rising` + * `intr_ctrl_en_falling` + * `intr_ctrl_en_lvlhigh` + * `intr_ctrl_en_lvllow` +* `data_in_cov_obj`: Covers values and transitions on all bits of data_in register +* `out_oe_cov_objs`: Covers values and transitions on all bits of `direct_out`, `direct_oe`, `masked_out_lower`, `masked_oe_lower`, `masked_out_upper` and `masked_oe_upper` registers +* `out_oe_mask_data_cov_objs`: Covers `mask`, `data` fields and their cross coverage for `masked_out_lower` / `masked_oe_lower` and `masked_out_upper` / `masked_oe_upper` registers +* `data_out_data_oe_cov_obj`: Covers data_out, data_oe and their cross coverage based on writes to `direct_out`, `direct_oe`, `masked_out_lower`, `masked_oe_lower`, `masked_out_upper` and `masked_oe_upper` registers + +### Self-checking strategy +#### Scoreboard +The `gpio_scoreboard` is primarily used for end to end checking. +It creates the following tlm analysis fifos to retrieve the data monitored by tlul interface agent monitors: +* tl_a_chan_fifo: tl address channel +* tl_d_chan_fifo: tl data channel + +GPIO scoreboard monitors all valid GPIO CSR register accesses, activity on GPIO IOs, and interrupt pins. For any monitored write transaction, CSR values are updated in RAL. Based on monitored activity, GPIO scoreboard predicts updated values of required CSRs. + +For any activity monitored on GPIO IOs or any write to \*out\* or \*oe\* registers, `gpio_predict_and_compare` task is called which in turn predict any possible update for `data_in` register and GPIO pins. A checker compares predicted value of GPIO pins against actual monitored value. + +GPIO IO update or CSR write on most of the GPIO registers may result in GPIO interrupt event. For any such interrupt event, GPIO scoreboard predicts any possible update to `intr_state` register. This also includes `inter_test` reg functionality. + +Any CSR read transaction would check actual read data against predicted value. Additionally, CSR read on intr_state would also check if monitored value of interrupt pins match the predicted value. + +#### Assertions +* TLUL assertions: The `sva/gpio_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset +* `IntrGpioKnown`: Checks that GPIO interrupt pins do not have any unknowns +* `CioGpioEnOKnown`: Checks that GPIO output does not have any unknowns +* `CioGpioOKnown`: Checks that GPIO output enable does not have any unknowns + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/gpio_sim_cfg.hjson -i gpio_smoke +``` + +## Testplan +[Testplan](../data/gpio_testplan.hjson) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/cov/gpio_cov_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/cov/gpio_cov_excl.el new file mode 100644 index 00000000000..fb89fe7d1a4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/cov/gpio_cov_excl.el @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//================================================== +// This file contains the Excluded objects +// Generated By User: marcelo +// Format Version: 2 +// Date: Tue Feb 25 14:48:01 2025 +// ExclMode: default +//================================================== +CHECKSUM: "1706182284 132761700" +INSTANCE: tb.dut.u_reg.u_reg_if.u_rsp_intg_gen +ANNOTATION: "The signal tl_i.d_user is tied to zero in the tlul_adapter_reg.sv which comes from tl_o_pre. Because of that, the rsp_intg it will be constant and can be excluded from the coverage analysis." +Block 1 "461445014" "assign rsp_intg = tl_i.d_user.rsp_intg;" +ANNOTATION: "The signal tl_i.d_user is tied to zero in the tlul_adapter_reg.sv which comes from tl_o_pre. Because of that, the rsp_intg it will be constant and can be excluded from the coverage analysis." +Block 2 "2643129081" "assign data_intg = tl_i.d_user.data_intg;" +CHECKSUM: "2099741489 2073313596" +INSTANCE: tb.dut.u_reg.u_data_in.wr_en_data_arb +ANNOTATION: "The line 41 where `wr_en = de` is constant because the \"de\" is wired to 1 in gpio.sv (line 104). `hw2reg.data_in.de = 1'b1;` +So it will not be hit by the coverage." +Block 1 "494386457" "assign wr_en = de;" +CHECKSUM: "295805079 2786204945" +INSTANCE: tb.dut.u_reg.u_masked_out_lower_mask +ANNOTATION: "The hardware always signals d=0 (through hw2reg.masked_out_lower.mask.d) so this continuous assignment will not execute." +Block 2 "1004401251" "assign qs = d;" +ANNOTATION: "The hardware always signals d=0 (through hw2reg.masked_out_lower.mask.d) so this continuous assignment will not execute." +Block 1 "531057943" "assign ds = d;" +CHECKSUM: "295805079 2786204945" +INSTANCE: tb.dut.u_reg.u_masked_oe_lower_mask +ANNOTATION: "The hardware always signals d=0 (through hw2reg.masked_oe_lower.mask.d). So this is continuous assignment will not execute." +Block 1 "531057943" "assign ds = d;" +ANNOTATION: "The hardware always signals d=0 (through hw2reg.masked_oe_lower.mask.d). So this is continuous assignment will not execute." +Block 2 "1004401251" "assign qs = d;" +CHECKSUM: "295805079 2786204945" +INSTANCE: tb.dut.u_reg.u_masked_out_upper_mask +ANNOTATION: "The hardware always signals d=0 (through hw2reg.masked_out_upper.mask.d) so this continuous assignment will not execute." +Block 2 "1004401251" "assign qs = d;" +ANNOTATION: "The hardware always signals d=0 (through hw2reg.masked_out_upper.mask.d) so this continuous assignment will not execute." +Block 1 "531057943" "assign ds = d;" +CHECKSUM: "295805079 2786204945" +INSTANCE: tb.dut.u_reg.u_masked_oe_upper_mask +ANNOTATION: "The hardware always signals d=0 (through hw2reg.masked_oe_upper.mask.d) so this continuous assignment will not execute." +Block 2 "1004401251" "assign qs = d;" +ANNOTATION: "The hardware always signals d=0 (through hw2reg.masked_oe_upper.mask.d) so this continuous assignment will not execute." +Block 1 "531057943" "assign ds = d;" +CHECKSUM: "4255502330 2331745845" +INSTANCE: tb.dut.u_reg.u_data_in +ANNOTATION: "The line 41 where `wr_en = de` is constant because the \"de\" is wired to 1 in gpio.sv (line 104). `hw2reg.data_in.de = 1'b1;` +So it will not be hit by the coverage." +Condition 1 "1896215154" "(wr_en ? wr_data : qs) 1 -1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_reg.u_data_in +ANNOTATION: "The line 41 where `wr_en = de` is constant because the \"de\" is wired to 1 in gpio.sv (line 104) where is hw2reg.data_in.de = 1'b1; +So it will not be hit by the coverage." +Branch 0 "3759852512" "wr_en" (1) "wr_en 0" +ANNOTATION: "[UNR]" +Branch 1 "1017474648" "(!rst_ni)" (2) "(!rst_ni) 0,0" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_reg.u_data_in +ANNOTATION: "The line 41 where `wr_en = de` is constant because the \"de\" is wired to 1 in gpio.sv (line 104). `hw2reg.data_in.de = 1'b1;` +So it will not be hit by the coverage." +Block 7 "1375076151" "assign qe = wr_en;" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/doc/tb.svg b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/doc/tb.svg new file mode 100644 index 00000000000..b326d48953a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env.core b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env.core new file mode 100644 index 00000000000..4e6d570c6ef --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env.core @@ -0,0 +1,48 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:gpio_env:0.1 +description: "GPIO DV UVM environmnt" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + files: + - gpio_env_pkg.sv + - gpio_env_cfg.sv: {is_include_file: true} + - gpio_env_cov.sv: {is_include_file: true} + - gpio_scoreboard.sv: {is_include_file: true} + - gpio_env.sv: {is_include_file: true} + - seq_lib/gpio_vseq_list.sv: {is_include_file: true} + - seq_lib/gpio_base_vseq.sv: {is_include_file: true} + - seq_lib/gpio_common_vseq.sv: {is_include_file: true} + - seq_lib/gpio_smoke_vseq.sv: {is_include_file: true} + - seq_lib/gpio_inp_prd_cnt_vseq.sv: {is_include_file: true} + - seq_lib/gpio_rand_intr_trigger_vseq.sv: {is_include_file: true} + - seq_lib/gpio_random_dout_din_vseq.sv: {is_include_file: true} + - seq_lib/gpio_dout_din_regs_random_rw_vseq.sv: {is_include_file: true} + - seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv: {is_include_file: true} + - seq_lib/gpio_filter_stress_vseq.sv: {is_include_file: true} + - seq_lib/gpio_full_random_vseq.sv: {is_include_file: true} + - seq_lib/gpio_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/gpio_intr_rand_pgm_vseq.sv: {is_include_file: true} + - seq_lib/gpio_intr_with_filter_rand_intr_event_vseq.sv: {is_include_file: true} + - seq_lib/gpio_rand_straps_vseq.sv : {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: gpio + ip_hjson: ../../data/gpio.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env.sv new file mode 100644 index 00000000000..ced2992614c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env.sv @@ -0,0 +1,25 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class gpio_env extends cip_base_env #( + .CFG_T (gpio_env_cfg), + .COV_T (gpio_env_cov), + .VIRTUAL_SEQUENCER_T(gpio_virtual_sequencer), + .SCOREBOARD_T (gpio_scoreboard) +); + `uvm_component_utils(gpio_env) + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + if (!uvm_config_db#(gpio_vif)::get(this, "", "gpio_vif", cfg.gpio_vif)) begin + `uvm_fatal(get_full_name(), "failed to get gpio_vif from uvm_config_db") + end + if (!uvm_config_db#(straps_vif)::get(this, "", "straps_vif", cfg.straps_vif_inst)) begin + `uvm_fatal(get_full_name(), "Virtual interface straps_vif_inst is not set") + end + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env_cfg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env_cfg.sv new file mode 100644 index 00000000000..e9e269c8d4c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env_cfg.sv @@ -0,0 +1,40 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class gpio_env_cfg extends cip_base_env_cfg #( + .RAL_T(gpio_reg_block) +); + + // flag to indicate if weak pullup has been introduced on gpio + // By default, weak pull up is always present + rand bit pullup_en; + // flag to indicate if weak pulldown has been introduced on gpio + rand bit pulldown_en; + // gpio virtual interface + gpio_vif gpio_vif; + // gpio straps interface + straps_vif straps_vif_inst; + + constraint pullup_pulldown_en_c {pullup_en ^ pulldown_en;} + + `uvm_object_utils(gpio_env_cfg) + + function new(string name = "gpio_env_cfg"); + super.new(name); + endfunction + + virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1); + list_of_alerts = gpio_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + // set num_interrupts & num_alerts which will be used to create coverage and more + num_interrupts = ral.intr_state.get_n_used_bits(); + + // only support 1 outstanding TL item + m_tl_agent_cfg.max_outstanding_req = 1; + + // Used to allow reset operation during a stress all tests and check the CSR after that. + can_reset_with_csr_accesses = 1'b1; + endfunction : initialize + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env_cov.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env_cov.sv new file mode 100644 index 00000000000..a51ed5eb9f1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env_cov.sv @@ -0,0 +1,156 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// We are enclosing generic covergroups inside class so that we can +// take avoid tool limitation of not allowing arrays of covergroup +// Refer to Issue#375 for more details +class gpio_intr_type_cov_obj extends uvm_object; + `uvm_object_utils(gpio_intr_type_cov_obj) + + // Covergroup: intr_type_cg + // Covergroup for different interrupt types based on "Interrupt Control" registers in + // gpio. This group samples combination of interrupt type, interrupt enable and + // interrupt state, on per bit basis. + covergroup intr_type_cg(string name) with function sample(bit type_ctrl_en, + bit intr_en, + bit intr_state); + option.per_instance = 1; + option.name = name; + cp_cross_type_en_state: cross type_ctrl_en, intr_en, intr_state { + ignore_bins intr_type_disabled = binsof(type_ctrl_en) intersect {0}; + } + endgroup : intr_type_cg + + // Function: new + function new(string name="gpio_intr_type_cov_obj"); + super.new(name); + intr_type_cg = new(name); + endfunction : new +endclass : gpio_intr_type_cov_obj + +class gpio_out_oe_cov_obj extends uvm_object; + `uvm_object_utils(gpio_out_oe_cov_obj) + + // Covergroup: var1_var2_cg + // Covergroup invovling two variables of bit type and are meant to + // be used for cross coverage related to *out* and *oe* registers + covergroup var1_var2_cg(string name) with function sample(bit var1, bit var2); + option.per_instance = 1; + option.name = name; + cp_var1: coverpoint var1; + cp_var2: coverpoint var2; + cp_var1_var2_cross: cross cp_var1, cp_var2; + endgroup : var1_var2_cg + + // Function: new + function new(string name="gpio_out_oe_cov_obj"); + super.new(name); + var1_var2_cg = new(name); + endfunction : new +endclass : gpio_out_oe_cov_obj + +class gpio_env_cov extends cip_base_env_cov #(.CFG_T(gpio_env_cfg)); + `uvm_component_utils(gpio_env_cov) + + // Array of coverage objects for per pin coverage for gpio pin values + bit_toggle_cg_wrap gpio_pin_values_cov_obj[NUM_GPIOS]; + // Interrupt State (Interrupt bit getting set and cleared) + bit_toggle_cg_wrap intr_state_cov_obj[NUM_GPIOS]; + // Interrupt Control Enable registers' values + bit_toggle_cg_wrap intr_ctrl_en_cov_objs[NUM_GPIOS][string]; + // data_in register per bit value coverage + bit_toggle_cg_wrap data_in_cov_obj[NUM_GPIOS]; + // Per bit coverage on *out* and *oe* registers + bit_toggle_cg_wrap out_oe_cov_objs[NUM_GPIOS][string]; + // Different gpio interrupt types' occurrences + gpio_intr_type_cov_obj intr_event_type_cov_objs[NUM_GPIOS][string]; + // Coverage on data and mask fields of masked* registers + gpio_out_oe_cov_obj out_oe_mask_data_cov_objs[NUM_GPIOS/2][string]; + // Coverage on effective values of DATA_OUT and DATA_OE + gpio_out_oe_cov_obj data_out_data_oe_cov_obj[NUM_GPIOS]; + // Cross Coverage between per pin values of data_out value, data_oe value + // and data_in value + covergroup data_out_data_oe_data_in_cross_cg(string name) with function sample(uint pin, + bit data_out, + bit data_oe, + bit data_in); + option.name = name; + cp_pin: coverpoint pin { + bins bins_for_gpio_bits[] = {[0:NUM_GPIOS-1]}; + } + cp_cross_all: cross cp_pin, data_out, data_oe, data_in { + // If data_oe is true, data_in cannot be different from data_out value + illegal_bins data_oe_1_data_out_0_data_in_1 = binsof(data_out) intersect {0} && + binsof(data_oe) intersect {1} && + binsof(data_in) intersect {1}; + illegal_bins data_oe_1_data_out_1_data_in_0 = binsof(data_out) intersect {1} && + binsof(data_oe) intersect {1} && + binsof(data_in) intersect {0}; + } + endgroup : data_out_data_oe_data_in_cross_cg + // Cross coverage between gpio pin value and effective data_in value + covergroup gpio_pins_data_in_cross_cg(string name) with function sample(uint pin, + bit gpio_value, + bit data_in); + option.name = name; + cp_pin: coverpoint pin { + bins bins_for_gpio_bits[] = {[0:NUM_GPIOS-1]}; + } + cp_cross_pins_data_in: cross cp_pin, gpio_value, data_in; + endgroup : gpio_pins_data_in_cross_cg + + function new(string name, uvm_component parent); + super.new(name, parent); + begin + string intr_types[4] = '{"rising", "falling", "lvlhigh", "lvllow"}; + string out_oe_reg_names[6] = '{"direct_out", + "direct_oe", + "masked_out_lower", + "masked_oe_lower", + "masked_out_upper", + "masked_oe_upper"}; + foreach (intr_state_cov_obj[each_pin]) begin + // Create coverage for each gpio pin values and transitions + gpio_pin_values_cov_obj[each_pin] = new($sformatf("gpio_values_cov_obj_pin%0d", each_pin)); + // Create per pin coverage for interrupt state values and transitions + intr_state_cov_obj[each_pin] = new($sformatf("intr_state_cov_obj_pin%0d", each_pin)); + // Create per pin coverage interrupts + foreach(intr_types[each_type]) begin + // Per pin coverage for "Intrrupt Control Enable" values + // and transitions for each type of interrupt + intr_ctrl_en_cov_objs[each_pin][{"intr_ctrl_en_", intr_types[each_type]}] = + new({"intr_ctrl_en_", intr_types[each_type], $sformatf("_pin%0d_cov", each_pin)}); + // Per pin coverage for different types of interrupt event occurrences + intr_event_type_cov_objs[each_pin][{"intr_event_", intr_types[each_type]}] = + new({"intr_event_", intr_types[each_type], $sformatf("_pin%0d", each_pin)}); + end + // Per pin coverage for values of different *out* and *oe* registers + foreach (out_oe_reg_names[each_reg]) begin + out_oe_cov_objs[each_pin][out_oe_reg_names[each_reg]] = + new({out_oe_reg_names[each_reg], $sformatf("_cov_obj_pin%0d", each_pin)}); + end + data_out_data_oe_cov_obj[each_pin] = new($sformatf("data_out_data_oe_cov_obj_pin%0d", + each_pin)); + data_in_cov_obj[each_pin] = new($sformatf("data_in_cov_obj_pin%0d", each_pin)); + // Create sticky interrupt coverage per pin + // No toggle coverage is required in this case, so specify toggle_cov_en = 0 + sticky_intr_cov[{"gpio_sticky_intr_pin", $sformatf("%0d", each_pin)}] = + new(.name({"gpio_sticky_intr_pin", $sformatf("%0d", each_pin)}), .toggle_cov_en(0)); + end + // Per pin coverage and cross coverage for mask and data + // fields within masked_* registers + foreach (out_oe_mask_data_cov_objs[each_pin]) begin + foreach (out_oe_reg_names[each_reg]) begin + if (!uvm_re_match("masked*", out_oe_reg_names[each_reg])) begin + out_oe_mask_data_cov_objs[each_pin][out_oe_reg_names[each_reg]] = + new({out_oe_reg_names[each_reg], $sformatf("_mask_data_cov_obj_pin%0d", each_pin)}); + end + end + end + data_out_data_oe_data_in_cross_cg = new("data_out_data_oe_data_in_cross_cg"); + gpio_pins_data_in_cross_cg = new("gpio_pins_data_in_cross_cg"); + end + endfunction : new + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env_pkg.sv new file mode 100644 index 00000000000..939580fd475 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_env_pkg.sv @@ -0,0 +1,61 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package gpio_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import csr_utils_pkg::*; + import dv_base_reg_pkg::*; + import tl_agent_pkg::*; + import dv_lib_pkg::*; + import cip_base_pkg::*; + import gpio_ral_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // no. of gpio pins + parameter uint NUM_GPIOS = 32; + // no. of cycles for noise filter + parameter uint FILTER_CYCLES = 16; + // No. of alerts + parameter uint NUM_ALERTS = 1; + parameter string LIST_OF_ALERTS[NUM_ALERTS] = {"fatal_fault"}; + // No. of input period counters + parameter uint NUM_INP_PRD_CNT = 8; + + typedef virtual pins_if #(NUM_GPIOS) gpio_vif; + typedef virtual gpio_straps_if straps_vif; + typedef class gpio_env_cfg; + typedef class gpio_env_cov; + typedef cip_base_virtual_sequencer #(gpio_env_cfg, gpio_env_cov) gpio_virtual_sequencer; + + // structure to indicate gpio pin transition and type of transition + // transition_occurred: 1-yes, 0-no + // is_rising_edge: 1-rising edge transition, 0-falling edge transition + typedef struct packed { + bit transition_occurred; + bit is_rising_edge; + } gpio_transition_t; + + // structure to indicate whether or not register update is due for particular gpio register + // needs_update: 1-update is due, 0-update is not due + // reg_value: value to be updated when update is due + // eval_time: time stamp of event, which triggered interrupt update + typedef struct packed { + bit needs_update; + bit [TL_DW-1:0] reg_value; + time eval_time; + } gpio_reg_update_due_t; + + // package sources + `include "gpio_env_cfg.sv" + `include "gpio_env_cov.sv" + `include "gpio_scoreboard.sv" + `include "gpio_env.sv" + `include "gpio_vseq_list.sv" +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_scoreboard.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_scoreboard.sv new file mode 100644 index 00000000000..ca08b50f867 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/gpio_scoreboard.sv @@ -0,0 +1,920 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +class gpio_scoreboard extends cip_base_scoreboard #(.CFG_T (gpio_env_cfg), + .RAL_T (gpio_reg_block), + .COV_T (gpio_env_cov)); + + // predicted value of DATA_OUT rtl implementation register + bit [NUM_GPIOS-1:0] data_out; + // predicted updated value of DATA_OE rtl implementation register + bit [NUM_GPIOS-1:0] data_oe; + // input presented by driving gpio_i + logic [NUM_GPIOS-1:0] gpio_i_driven; + // gpio input pins if previous out value + logic [NUM_GPIOS-1:0] prv_gpio_i_pins_o; + // gpio input pins if previous out enable value + logic [NUM_GPIOS-1:0] prv_gpio_i_pins_oe; + // Flag to store value to be updated for INTR_STATE register + // and to indicate whether value change is due currently + gpio_reg_update_due_t intr_state_update_queue[$]; + // data_in update queue + gpio_reg_update_due_t data_in_update_queue[$]; + // Latest Interrupt state update due to either of following reasons: + // (i) gpio value change + // (ii) interrupt control register value(s) write + // This flag is not meant for update when intr_state register is written + bit [TL_DW-1:0] last_intr_update_except_clearing; + // Value seen in last Interrupt Test write + bit [TL_DW-1:0] last_intr_test_event; + // Flag to: + // (i) indicate that write to INTR_STATE register just happened, and + // (ii) store information of which all interupt bits were cleared + bit [TL_DW-1:0] cleared_intr_bits; + // Flag to indicate that the strap was triggered + bit first_strap_triggered; + + // mask are WO, store the values in scb + uvm_reg_data_t masked_out_lower_mask; + uvm_reg_data_t masked_out_upper_mask; + + string common_seq_type; + + `uvm_component_utils(gpio_scoreboard) + + function new (string name = "gpio_scoreboard", uvm_component parent = null); + super.new (name, parent); + endfunction + + // Function: build_phase + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction + + // Task: run_phase + task run_phase(uvm_phase phase); + void'($value$plusargs("run_%0s", common_seq_type)); + super.run_phase(phase); + fork + monitor_gpio_i(); + monitor_gpio_interrupt_pins(); + monitor_gpio_straps(); + join_none + endtask + + // Task : process_tl_access + // process monitored tl transaction + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // grab completed transactions from data channel; ignore packets from address channel + if (channel == AddrChannel) begin + // Clock period in nano seconds (timeunit) + real clk_period = cfg.clk_rst_vif.clk_period_ps / 1000; + time crnt_time = $time; + + // apply pending update for `data_in` register + if (data_in_update_queue.size() > 0) begin + if (data_in_update_queue[$].needs_update == 1'b1 && + (int'((crnt_time - data_in_update_queue[$].eval_time) / clk_period)) > 1) begin + void'(ral.data_in.predict(.value(data_in_update_queue[$].reg_value), + .kind(UVM_PREDICT_READ))); + end else if(data_in_update_queue[$ - 1].needs_update == 1'b1) begin + // Use previous updated value for "data_in" prediction + void'(ral.data_in.predict(.value(data_in_update_queue[$ - 1].reg_value), + .kind(UVM_PREDICT_READ))); + end + end + + // apply pending update for interrupt state + if (intr_state_update_queue.size() > 0) begin + // As register read takes single clock cycle to latch the updated value, immediate + // read on same or next clock will not give latest updated value. So, look for time stamp + // of latest update to decide which value to predict for "intr_state" mirrored value + if (intr_state_update_queue[$].needs_update == 1'b1 && + (int'((crnt_time - intr_state_update_queue[$].eval_time) / clk_period)) > 1) begin + void'(ral.intr_state.predict(.value(intr_state_update_queue[$].reg_value), + .kind(UVM_PREDICT_READ))); + end else if(intr_state_update_queue[$ - 1].needs_update == 1'b1) begin + // Use previous updated value for "intr_state" prediction + void'(ral.intr_state.predict(.value(intr_state_update_queue[$ - 1].reg_value), + .kind(UVM_PREDICT_READ))); + end + end + + // if incoming access is a write to a valid csr, then make updates right away + if (write) begin + // GPIO scoreboard is cycle accurate and will only update `intr_state` mirrored value at + // the address phase of the next read operation. + // This is too late for intr_test and intr_test does not need this cycle accurate model, + // So we use csr predict function right after the write operations. + if ((common_seq_type == "intr_test") && + (csr.get_name() inside {"intr_state", "intr_enable", "intr_test"})) begin + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + if (csr.get_name() == "intr_state") begin + // As per rtl definition of W1C, hardware must get a chance to make update + // to interrupt state first, so we need to clear interrupt only after possible + // interrupt update due to gpio change + #0; + `uvm_info(`gfn, $sformatf("Write on intr_state: write data = %0h", item.a_data), UVM_HIGH) + if (intr_state_update_queue.size() > 0) begin + gpio_reg_update_due_t intr_state_write_to_clear_update = intr_state_update_queue[$]; + `uvm_info(`gfn, $sformatf("Entry taken out for clearing is %0p", + intr_state_write_to_clear_update), UVM_HIGH) + // Update time + intr_state_write_to_clear_update.eval_time = $time; + for (uint each_bit = 0; each_bit < TL_DW; each_bit++) begin + if (intr_state_write_to_clear_update.needs_update == 1'b1 && + intr_state_write_to_clear_update.reg_value[each_bit] == 1'b1 && + item.a_data[each_bit] == 1'b1) begin + intr_state_write_to_clear_update.reg_value[each_bit] = 1'b0; + cleared_intr_bits[each_bit] = 1'b1; + // Coverage Sampling: gpio interrupt cleared + if (cfg.en_cov) begin + cov.intr_state_cov_obj[each_bit].sample(1'b0); + end + end + end + // If same time stamp as last entry, update entry to account for "still active" event + // that caused last interrupt update (As per definition of w1c in comportability + // specification) + if (intr_state_write_to_clear_update.eval_time == intr_state_update_queue[$].eval_time) + begin + // Re-apply interrupt update + intr_state_write_to_clear_update.reg_value |= last_intr_update_except_clearing; + // Delete last entry with same time stamp + intr_state_update_queue.delete(intr_state_update_queue.size()-1); + // Coverage Sampling: cover a scenario wherein cleared interrupt state bit + // is re-asserted due to still active interrupt event + // Note: In this case, both interrupt clearing event and INTR_STATE reg write + // have occurred at the same time. + if (cfg.en_cov) begin + foreach (cleared_intr_bits[each_bit]) begin + if (cleared_intr_bits[each_bit]) begin + if (last_intr_update_except_clearing[each_bit]) begin + cov.sticky_intr_cov[{"gpio_sticky_intr_pin", + $sformatf("%0d", each_bit)}].sample(1'b1); + end else begin + cov.sticky_intr_cov[{"gpio_sticky_intr_pin", + $sformatf("%0d", each_bit)}].sample(1'b0); + end + end + end + end + end + // Push new interrupt state update entry into queue + intr_state_update_queue.push_back(intr_state_write_to_clear_update); + if (intr_state_update_queue.size() > 2) begin + // Delete extra unnecessary entry + intr_state_update_queue.delete(0); + end + end + end else begin + if (csr.get_name() == "intr_test") begin + // Store the written value as it is WO register + last_intr_test_event = item.a_data; + end else begin + // Coverage Sampling: coverage on *out* and *oe* register values + if (cfg.en_cov && (!uvm_re_match("*out*", csr.get_name()) || + !uvm_re_match("*oe*", csr.get_name()))) begin + for (uint each_pin = 0; each_pin < NUM_GPIOS; each_pin++) begin + cov.out_oe_cov_objs[each_pin][csr.get_name()].sample(item.a_data[each_pin]); + end + // Coverage Sampling: Cross coverage on mask and data within masked_* registers + if (!uvm_re_match("masked*", csr.get_name())) begin + bit [(NUM_GPIOS/2) - 1:0] mask, data; + {mask, data} = item.a_data; + for (uint each_pin = 0; each_pin < NUM_GPIOS/2; each_pin++) begin + cov.out_oe_mask_data_cov_objs[each_pin][csr.get_name()].var1_var2_cg.sample( + mask[each_pin], data[each_pin]); + end + end + end + // these fields are WO, save values in scb + if (csr.get_name() == "masked_out_lower") begin + masked_out_lower_mask = get_field_val(ral.masked_out_lower.mask, item.a_data); + end else if (csr.get_name() == "masked_out_upper") begin + masked_out_upper_mask = get_field_val(ral.masked_out_upper.mask, item.a_data); + end + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + end + `uvm_info(`gfn, "Calling gpio_predict_and_compare on reg write", UVM_HIGH) + gpio_predict_and_compare(csr); + end // if (write) + end else begin // if (channel == DataChannel) + if (write == 0) begin + if (csr.get_name() == "inp_prd_cnt_val_0") begin + // TODO(#26544): Check values read from all input period counters. + do_read_check = 1'b0; + end + if (csr.get_name() == "inp_prd_cnt_val_1") begin + // TODO(#26544): Check values read from all input period counters. + do_read_check = 1'b0; + end + if (csr.get_name() == "inp_prd_cnt_val_2") begin + // TODO(#26544): Check values read from all input period counters. + do_read_check = 1'b0; + end + if (csr.get_name() == "inp_prd_cnt_val_3") begin + // TODO(#26544): Check values read from all input period counters. + do_read_check = 1'b0; + end + if (csr.get_name() == "inp_prd_cnt_val_4") begin + // TODO(#26544): Check values read from all input period counters. + do_read_check = 1'b0; + end + if (csr.get_name() == "inp_prd_cnt_val_5") begin + // TODO(#26544): Check values read from all input period counters. + do_read_check = 1'b0; + end + if (csr.get_name() == "inp_prd_cnt_val_6") begin + // TODO(#26544): Check values read from all input period counters. + do_read_check = 1'b0; + end + if (csr.get_name() == "inp_prd_cnt_val_7") begin + // TODO(#26544): Check values read from all input period counters. + do_read_check = 1'b0; + end + // If do_read_check, is set, then check mirrored_value against item.d_data + if (do_read_check) begin + // Checker-2: Check if reg read data matches expected value or not + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data) + // Checker-3: Check value of interrupt pins against predicted value + if (csr.get_name() == "intr_state") begin + bit [TL_DW-1:0] intr_state = (intr_state_update_queue.size() > 0) ? + intr_state_update_queue[$].reg_value : + csr.get_mirrored_value(); + bit [TL_DW-1:0] pred_val_intr_pins = intr_state & + ral.intr_enable.get_mirrored_value(); + // according to issue #841, interrupt is a flop and the value will be updated after one + // clock cycle. Because the `pred_val_intr_pins` might be updated during the one clk + // cycle, we store the predicted intr val into a temp automatic variable. + fork + begin + automatic bit [TL_DW-1:0] pred_val_intr_pins_temp = pred_val_intr_pins; + cfg.clk_rst_vif.wait_clks(1); + if (!cfg.under_reset) `DV_CHECK_EQ(cfg.intr_vif.pins, pred_val_intr_pins_temp) + end + join_none + end + end + end // if (write == 0) + end + endtask : process_tl_access + + // Task : monitor_gpio_i + // monitor gpio input pins interface + virtual task monitor_gpio_i(); + logic [NUM_GPIOS-1:0] prev_gpio_i = cfg.gpio_vif.pins; + + forever begin : monitor_pins_if + @(cfg.gpio_vif.pins or cfg.under_reset); + `uvm_info(`gfn, $sformatf("cfg.gpio_vif.pins = %0h, under_reset = %0b", + cfg.gpio_vif.pins, cfg.under_reset), UVM_HIGH) + if (cfg.under_reset == 1'b0) begin + // Coverage Sampling: gpio pin values' coverage + if (cfg.en_cov) begin + foreach (cov.gpio_pin_values_cov_obj[each_pin]) begin + cov.gpio_pin_values_cov_obj[each_pin].sample(cfg.gpio_vif.pins[each_pin]); + end + end + // evaluate gpio input driven to dut + foreach (cfg.gpio_vif.pins_oe[pin_num]) begin + if (cfg.gpio_vif.pins_oe[pin_num] == 1'b1) begin + gpio_i_driven[pin_num] = cfg.gpio_vif.pins_o[pin_num]; + end else begin + gpio_i_driven[pin_num] = 1'bz; + end + `uvm_info(`gfn, $sformatf("pins_oe[%0d] = %0b pins_o[%0d] = %0b gpio_i_driven[%0d] = %0b", + pin_num, cfg.gpio_vif.pins_oe[pin_num], pin_num, + cfg.gpio_vif.pins_o[pin_num], pin_num, gpio_i_driven[pin_num]), + UVM_HIGH) + end + + `uvm_info(`gfn, $sformatf("pins = 0x%0h [%0b]) gpio_i_driven = 0x%0h [%0b]", + cfg.gpio_vif.pins, cfg.gpio_vif.pins, gpio_i_driven, + gpio_i_driven), UVM_HIGH) + // Predict effect on gpio pins + gpio_predict_and_compare(); + + if (prev_gpio_i !== cfg.gpio_vif.pins) begin + // Flag to indicate: + // (i) if there was any change in value on gpio_i pin - Bit0 + // (ii) what change occurred on gpio_i pin - Bit1 + gpio_transition_t [NUM_GPIOS-1:0] gpio_i_transition; + foreach (prev_gpio_i[pin]) begin + gpio_i_transition[pin].transition_occurred = + (cfg.gpio_vif.pins[pin] !== prev_gpio_i[pin]); + if (gpio_i_transition[pin].transition_occurred) begin + case (cfg.gpio_vif.pins[pin]) + 1'b0: begin + // Negedge seen on pin, indicated by 0 value + gpio_i_transition[pin].is_rising_edge = 1'b0; + end + 1'b1: begin + // Posedge seen on pin, indicated by 1 value + gpio_i_transition[pin].is_rising_edge = 1'b1; + end + 1'bz: begin + if (prev_gpio_i[pin] === 1'b1) begin + // Negedge seen on pin, indicated by 0 value + gpio_i_transition[pin].is_rising_edge = 1'b0; + end else if (prev_gpio_i[pin] === 1'b0) begin + // Posedge seen on pin, indicated by 1 value + gpio_i_transition[pin].is_rising_edge = 1'b1; + end else begin + // x->z does not indicate useful transition, reset transition bit + gpio_i_transition[pin].transition_occurred = 1'b0; + end + end + 1'bx: begin + if (prev_gpio_i[pin] === 1'b1) begin + // Negedge seen on pin, indicated by 0 value + gpio_i_transition[pin].is_rising_edge = 1'b0; + end else if (prev_gpio_i[pin] === 1'b0) begin + // Posedge seen on pin, indicated by 1 value + gpio_i_transition[pin].is_rising_edge = 1'b1; + end else begin + // z->x does not indicate useful transition, reset transition bit + gpio_i_transition[pin].transition_occurred = 1'b0; + end + end + endcase + end + end + foreach (gpio_i_transition[ii]) begin + `uvm_info(`gfn, $sformatf("gpio_i_transition[%0d] = %0p", ii, gpio_i_transition[ii]), + UVM_HIGH) + end + `uvm_info(`gfn, "Calling gpio_interrupt_predict from monitor_pins_if", UVM_HIGH) + // Look for interrupt event and update interrupt status + gpio_interrupt_predict(gpio_i_transition); + // Update value + prev_gpio_i = cfg.gpio_vif.pins; + `uvm_info(`gfn, $sformatf("updated prev_gpio_i = 0x%0h [%0b]", prev_gpio_i, prev_gpio_i), + UVM_HIGH) + end + // Update "previous pins if out and out enable" values + prv_gpio_i_pins_o = cfg.gpio_vif.pins_o; + prv_gpio_i_pins_oe = cfg.gpio_vif.pins_oe; + `uvm_info(`gfn, $sformatf("prv_gpio_i_pins_o = 0x%0h [%0b]", + prv_gpio_i_pins_o, prv_gpio_i_pins_o), UVM_HIGH) + `uvm_info(`gfn, $sformatf("prv_gpio_i_pins_oe = 0x%0h [%0b]", + prv_gpio_i_pins_oe, prv_gpio_i_pins_oe), UVM_HIGH) + end + + end // monitor_pins_if + + endtask : monitor_gpio_i + + // Task: monitor_gpio_interrupt_pins + virtual task monitor_gpio_interrupt_pins(); + forever begin : monitor_gpio_intr + @(cfg.intr_vif.pins or cfg.under_reset) begin + if (cfg.under_reset == 0) begin + if (cfg.en_cov) begin + // Coverage Sampling: gpio interrupt pin values and transitions + for (uint each_pin = 0; each_pin < NUM_GPIOS; each_pin++) begin + cov.intr_pins_cg.sample(each_pin, cfg.intr_vif.pins[each_pin]); + end + end + end + end + end + endtask : monitor_gpio_interrupt_pins + + virtual task update_gpio_straps_regs(logic [NUM_GPIOS-1:0] gpio_i_sampled); + // Update data_in and data_in_valid ral register value based on result of input + `DV_CHECK_FATAL(ral.hw_straps_data_in.predict(.value(gpio_i_sampled), + .kind(UVM_PREDICT_READ))); + `DV_CHECK_FATAL(ral.hw_straps_data_in_valid.predict(.value('b1), + .kind(UVM_PREDICT_READ))); + endtask : update_gpio_straps_regs + + // Task: monitor_gpio_straps + // The task monitors the gpio straps enable signal + // and checks the straps output signal after the first strap trigger + virtual task monitor_gpio_straps(); + logic [NUM_GPIOS-1:0] gpio_i_sampled; + forever begin : monitor_gpio_straps + // Wait for going out of reset operation. + wait(!cfg.under_reset); + // Wait until the strap_en input be triggered + // if a reset comes in the middle, step-out of the loop. + while (!cfg.straps_vif_inst.tb_port.strap_en) begin + cfg.clk_rst_vif.wait_clks_or_rst(1); + if (cfg.under_reset) break; + end + // Step out to the next iteration if a reset happens. + if (cfg.under_reset) continue; + // Get the gpio_i input data from the pins interface. + gpio_i_sampled = cfg.gpio_vif.pins; + // Wait for one clock cycle to update the register model. + cfg.clk_rst_vif.wait_clks_or_rst(1); + // Step out from the loop if a reset comes. + if (cfg.under_reset) continue; + // Update the register model. + update_gpio_straps_regs(gpio_i_sampled); + + // Checker: Compare actual values of gpio pins with straps register. + // Check the register hw_straps_data_in against gpio_i pins + `DV_CHECK_CASE_EQ(gpio_i_sampled, cfg.straps_vif_inst.tb_port.sampled_straps.data) + // Check the register hw_straps_data_in_valid + `DV_CHECK_CASE_EQ('b1, cfg.straps_vif_inst.tb_port.sampled_straps.valid) + + // Wait for the next reset, if it happens. + wait(cfg.under_reset); + end + endtask : monitor_gpio_straps + + // Function: actual_gpio_i_activity + function bit actual_gpio_i_activity(); + return ~((prv_gpio_i_pins_o === cfg.gpio_vif.pins_o) && + (prv_gpio_i_pins_oe === cfg.gpio_vif.pins_oe)); + endfunction : actual_gpio_i_activity + + // Function : gpio_predict_and_compare + function void gpio_predict_and_compare(uvm_reg csr = null); + string msg_id = {`gfn, " gpio_predict_and_compare: "}; + // Predicted value of "pins" from within gpio_vif + logic [NUM_GPIOS-1:0] pred_val_gpio_pins; + // Flag to decide if gpio data prediction and check are required + bit gpio_data_check = 1'b1; + + if (csr != null) begin + // process the csr req + case (csr.get_name()) + "data_in": begin + gpio_data_check = 1'b0; + end + "direct_out": begin + data_out = csr.get_mirrored_value(); + `uvm_info(`gfn, $sformatf("data_out updated to 0x%0h [%0b]", data_out, data_out), + UVM_HIGH) + // Update mirror values of *out* registers + update_gpio_out_regs(); + end + "masked_out_lower": begin + uvm_reg_data_t data = ral.masked_out_lower.data.get_mirrored_value(); + + for (uint pin_idx = 0; + pin_idx < ral.masked_out_lower.mask.get_n_bits(); pin_idx++) begin + if (masked_out_lower_mask[pin_idx] == 1'b1) begin + data_out[pin_idx] = data[pin_idx]; + end + end + `uvm_info(`gfn, $sformatf("data_out updated to 0x%0h [%0b]", data_out, data_out), + UVM_HIGH) + // Update mirror values of *out* registers + update_gpio_out_regs(); + end + "masked_out_upper": begin + uvm_reg_data_t data = ral.masked_out_upper.data.get_mirrored_value(); + + for (uint pin_idx = 0; pin_idx < ral.masked_out_upper.mask.get_n_bits(); pin_idx++) begin + if (masked_out_upper_mask[pin_idx] == 1'b1) begin + data_out[(NUM_GPIOS / 2) + pin_idx] = data[pin_idx]; + end + end + `uvm_info(`gfn, $sformatf("data_out updated to 0x%0h [%0b]", data_out, data_out), + UVM_HIGH) + // Update mirror values of *out* registers + update_gpio_out_regs(); + end + "direct_oe": begin + data_oe = csr.get_mirrored_value(); + `uvm_info(`gfn, $sformatf("data_out updated to 0x%0h [%0b]", data_out, data_out), + UVM_HIGH) + // Update mirror values of *oe* registers + update_gpio_oe_regs(); + end + "masked_oe_lower": begin + uvm_reg_data_t mask = ral.masked_oe_lower.mask.get_mirrored_value(); + uvm_reg_data_t data = ral.masked_oe_lower.data.get_mirrored_value(); + + for (uint pin_idx = 0; pin_idx < ral.masked_oe_lower.mask.get_n_bits(); pin_idx++) begin + if (mask[pin_idx] == 1'b1) begin + data_oe[pin_idx] = data[pin_idx]; + end + end + `uvm_info(`gfn, $sformatf("data_oe reg updated to 0x%0h [%0b]", data_oe, data_oe), + UVM_HIGH) + // Update mirror values of *oe* registers + update_gpio_oe_regs(); + end + "masked_oe_upper": begin + uvm_reg_data_t mask = ral.masked_oe_upper.mask.get_mirrored_value(); + uvm_reg_data_t data = ral.masked_oe_upper.data.get_mirrored_value(); + + for (uint pin_idx = 0; pin_idx < ral.masked_oe_upper.mask.get_n_bits(); pin_idx++) begin + if (mask[pin_idx] == 1'b1) begin + data_oe[(NUM_GPIOS / 2) + pin_idx] = data[pin_idx]; + end + end + `uvm_info(`gfn, $sformatf("data_oe reg updated to %0h", data_oe), UVM_HIGH) + // Update mirror values of *oe* registers + update_gpio_oe_regs(); + end + "intr_enable": begin + gpio_data_check = 1'b0; + gpio_interrupt_predict(); + end + "intr_state": begin + gpio_data_check = 1'b0; + gpio_interrupt_predict(); + end + "intr_test": begin + gpio_data_check = 1'b0; + gpio_interrupt_predict(); + end + "intr_ctrl_en_rising": begin + gpio_data_check = 1'b0; + gpio_interrupt_predict(); + end + "intr_ctrl_en_falling": begin + gpio_data_check = 1'b0; + gpio_interrupt_predict(); + end + "intr_ctrl_en_lvlhigh": begin + gpio_data_check = 1'b0; + gpio_interrupt_predict(); + end + "intr_ctrl_en_lvllow": begin + gpio_data_check = 1'b0; + gpio_interrupt_predict(); + end + "ctrl_en_input_filter": begin + end + "inp_prd_cnt_ctrl_0": begin + // TODO(#26544): Model input period counters in scoreboard. + end + "inp_prd_cnt_ctrl_1": begin + // TODO(#26544): Model input period counters in scoreboard. + end + "inp_prd_cnt_ctrl_2": begin + // TODO(#26544): Model input period counters in scoreboard. + end + "inp_prd_cnt_ctrl_3": begin + // TODO(#26544): Model input period counters in scoreboard. + end + "inp_prd_cnt_ctrl_4": begin + // TODO(#26544): Model input period counters in scoreboard. + end + "inp_prd_cnt_ctrl_5": begin + // TODO(#26544): Model input period counters in scoreboard. + end + "inp_prd_cnt_ctrl_6": begin + // TODO(#26544): Model input period counters in scoreboard. + end + "inp_prd_cnt_ctrl_7": begin + // TODO(#26544): Model input period counters in scoreboard. + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + end + + // GPIO inout signal value check + if (gpio_data_check == 1'b1) begin + // effect of gpio_o on gpio_i based on gpio_oe + logic [NUM_GPIOS-1:0] data_out_effect_on_gpio_i; + // As there is a common net that drives gpio_i and gets driven through gpio_o + // based on gpio_oe, gpio_i will have effect of (gpio_o & gpio_oe) value + foreach (data_oe[pin_num]) begin + if (data_oe[pin_num] === 1'b1) begin + data_out_effect_on_gpio_i[pin_num] = data_out[pin_num]; + end else begin + data_out_effect_on_gpio_i[pin_num] = 1'bz; + end + end + `uvm_info(msg_id, $sformatf("data_out_effect_on_gpio_i = 0x%0h [%0b]", + data_out_effect_on_gpio_i, data_out_effect_on_gpio_i), UVM_HIGH) + `uvm_info(msg_id, $sformatf("gpio_i_driven = 0x%0h [%0b]", gpio_i_driven, gpio_i_driven), + UVM_HIGH) + + // Predict effective value of common wire that- + // (i) drives gpio_i, and + // (ii) gets driven by gpio_o based on gpiooe value + for (uint pin_num = 0; pin_num < NUM_GPIOS; pin_num++) begin + if (data_out_effect_on_gpio_i[pin_num] === 1'bz) begin + pred_val_gpio_pins[pin_num] = gpio_i_driven[pin_num]; + end else if (gpio_i_driven[pin_num] === 1'bz) begin + pred_val_gpio_pins[pin_num] = data_out_effect_on_gpio_i[pin_num]; + end else if (data_out_effect_on_gpio_i[pin_num] === gpio_i_driven[pin_num]) begin + pred_val_gpio_pins[pin_num] = data_out_effect_on_gpio_i[pin_num]; + end else begin + pred_val_gpio_pins[pin_num] = 1'bx; + end + if (pred_val_gpio_pins[pin_num] === 1'bz) begin + if (cfg.gpio_vif.pins_pu[pin_num] == 1'b1) begin + pred_val_gpio_pins[pin_num] = 1'b1; + end else if (cfg.gpio_vif.pins_pd[pin_num] == 1'b1) begin + pred_val_gpio_pins[pin_num] = 1'b0; + end + end + end + `uvm_info(msg_id, $sformatf("pred_val_gpio_pins = %0h(%0b)", pred_val_gpio_pins, + pred_val_gpio_pins), UVM_HIGH) + + // Store latest update to be applied to data_in + begin + gpio_reg_update_due_t current_data_in_update; + if (data_in_update_queue.size == 2) begin + data_in_update_queue.delete(0); + end + current_data_in_update.needs_update = 1'b1; + current_data_in_update.reg_value = pred_val_gpio_pins; + current_data_in_update.eval_time = $time; + data_in_update_queue.push_back(current_data_in_update); + // Coverage Sampling: data_in register coverage + // Coverage Sampling: Cross coverage between data_out, data_oe and data_in + // values per bit + if (cfg.en_cov) begin + for (uint each_bit = 0; each_bit < NUM_GPIOS; each_bit++) begin + cov.data_in_cov_obj[each_bit].sample(pred_val_gpio_pins[each_bit]); + cov.data_out_data_oe_data_in_cross_cg.sample(each_bit, data_out[each_bit], + data_oe[each_bit], pred_val_gpio_pins[each_bit]); + cov.gpio_pins_data_in_cross_cg.sample(each_bit, cfg.gpio_vif.pins[each_bit], + pred_val_gpio_pins[each_bit]); + end + end + end + // If update was due to register write, we can call predict right away + if (csr != null) begin + // Update data_in register value based on result of input and output + void'(ral.data_in.data_in.predict(.value(pred_val_gpio_pins), .kind(UVM_PREDICT_DIRECT))); + end + + // Checker-1: Compare predicted and actual values of gpio pins + // Avoid calling this checker due to weak pull-up or pull-down effect + if ((csr != null) || + ((|gpio_i_driven === 1'b1) && (actual_gpio_i_activity() == 1))) begin + `DV_CHECK_CASE_EQ(pred_val_gpio_pins, cfg.gpio_vif.pins) + end + + end + + endfunction : gpio_predict_and_compare + + // Function : gpio_interrupt_predict + // This function computes expected value of gpio intr_status based on + // changes of gpio_i data or interrupt control registers + virtual function void gpio_interrupt_predict( + input gpio_transition_t [NUM_GPIOS-1:0] gpio_i_transition = {NUM_GPIOS{2'b00}}); + + string msg_id = {`gfn, $sformatf(" gpio_interrupt_predict: ")}; + bit [TL_DW-1:0] intr_enable = ral.intr_enable.get_mirrored_value(); + bit [TL_DW-1:0] intr_state = ral.intr_state.get_mirrored_value(); + bit [TL_DW-1:0] intr_ctrl_en_rising = ral.intr_ctrl_en_rising.get_mirrored_value(); + bit [TL_DW-1:0] intr_ctrl_en_falling = ral.intr_ctrl_en_falling.get_mirrored_value(); + bit [TL_DW-1:0] intr_ctrl_en_lvlhigh = ral.intr_ctrl_en_lvlhigh.get_mirrored_value(); + bit [TL_DW-1:0] intr_ctrl_en_lvllow = ral.intr_ctrl_en_lvllow.get_mirrored_value(); + // expected(predicted) value of interrupt status + bit [TL_DW-1:0] exp_intr_status; + + // Reset value of last_intr_update_except_clearing to 0 + last_intr_update_except_clearing = '0; + // Check if there is already INTR_STATE value update which was already due + // for update, but not actually updated + if (intr_state_update_queue.size() > 0) begin + if (intr_state_update_queue[$].needs_update) begin + intr_state = intr_state_update_queue[$].reg_value; + end + end + + // Coverage Sampling: gpio interrupt types + if (cfg.en_cov) begin + foreach (intr_ctrl_en_rising[each_bit]) begin + cov.intr_ctrl_en_cov_objs[each_bit]["intr_ctrl_en_rising"].sample( + intr_ctrl_en_rising[each_bit]); + cov.intr_ctrl_en_cov_objs[each_bit]["intr_ctrl_en_falling"].sample( + intr_ctrl_en_falling[each_bit]); + cov.intr_ctrl_en_cov_objs[each_bit]["intr_ctrl_en_lvlhigh"].sample( + intr_ctrl_en_lvlhigh[each_bit]); + cov.intr_ctrl_en_cov_objs[each_bit]["intr_ctrl_en_lvllow"].sample( + intr_ctrl_en_lvllow[each_bit]); + end + end + // 1. Look for edge triggerred interrupts + begin + bit [TL_DW-1:0] rising_edge_intr_events, falling_edge_intr_events; + if (gpio_i_transition != {NUM_GPIOS{2'b00}}) begin + foreach (rising_edge_intr_events[each_bit]) begin + if (gpio_i_transition[each_bit].transition_occurred) begin + rising_edge_intr_events[each_bit] = gpio_i_transition[each_bit].is_rising_edge & + intr_ctrl_en_rising[each_bit]; + falling_edge_intr_events[each_bit] = !gpio_i_transition[each_bit].is_rising_edge & + intr_ctrl_en_falling[each_bit]; + end + end + foreach (gpio_i_transition[each_bit]) begin + if (gpio_i_transition[each_bit].transition_occurred) begin + if (rising_edge_intr_events[each_bit] || falling_edge_intr_events[each_bit]) begin + exp_intr_status[each_bit] = 1'b1; + // Register the latest edge triggered gpio interrupt update, if any + last_intr_update_except_clearing[each_bit] = 1'b1; + end else begin + exp_intr_status[each_bit] = intr_state[each_bit]; + end + end + end + end + // Coverage Sampling: Cross coverage of (edge tiggered intr type)x(enable)x(state) + // when type is enabled + if (cfg.en_cov) begin + foreach (rising_edge_intr_events[each_bit]) begin + cov.intr_event_type_cov_objs[each_bit]["intr_event_rising"].intr_type_cg.sample( + intr_ctrl_en_rising[each_bit], + intr_enable[each_bit], + rising_edge_intr_events[each_bit]); + cov.intr_event_type_cov_objs[each_bit]["intr_event_falling"].intr_type_cg.sample( + intr_ctrl_en_falling[each_bit], + intr_enable[each_bit], + falling_edge_intr_events[each_bit]); + end + end + end + // 2. Look for level triggerred interrupts + begin + bit [TL_DW-1:0] lvlhigh_intr_events, lvllow_intr_events; + for (uint each_bit = 0; each_bit < TL_DW; each_bit++) begin + lvlhigh_intr_events[each_bit] = (cfg.gpio_vif.pins[each_bit] == 1'b1) && + (intr_ctrl_en_lvlhigh[each_bit] == 1'b1); + lvllow_intr_events[each_bit] = (cfg.gpio_vif.pins[each_bit] == 1'b0) && + (intr_ctrl_en_lvllow[each_bit] == 1'b1); + if (exp_intr_status[each_bit] == 1'b0) begin + if (lvlhigh_intr_events[each_bit] || lvllow_intr_events[each_bit]) begin + exp_intr_status[each_bit] = 1'b1; + // Register the latest level triggered gpio interrupt update, if any + last_intr_update_except_clearing[each_bit] = 1'b1; + end else begin + exp_intr_status[each_bit] = intr_state[each_bit]; + end + end + end + // Coverage Sampling: Cross coverage of (edge tiggered intr type)x(enable)x(state) + // when type is enabled + if (cfg.en_cov) begin + foreach (lvlhigh_intr_events[each_bit]) begin + cov.intr_event_type_cov_objs[each_bit]["intr_event_lvlhigh"].intr_type_cg.sample( + intr_ctrl_en_lvlhigh[each_bit], + intr_enable[each_bit], + lvlhigh_intr_events[each_bit]); + cov.intr_event_type_cov_objs[each_bit]["intr_event_lvllow"].intr_type_cg.sample( + intr_ctrl_en_lvllow[each_bit], + intr_enable[each_bit], + lvllow_intr_events[each_bit]); + end + end + end + // 3. Apply effect of "Interrupt Test" + exp_intr_status |= last_intr_test_event; + `uvm_info(`gfn, $sformatf("updated intr_state is %0h", exp_intr_status), UVM_HIGH) + // Coverage Sampling: Coverage on Interrupt Index, Interrupt Enable, + // Interrupt Status and their cross coverage + if (cfg.en_cov) begin + foreach (exp_intr_status[each_bit]) begin + cov.intr_cg.sample(each_bit, intr_enable[each_bit], exp_intr_status[each_bit]); + cov.intr_state_cov_obj[each_bit].sample(last_intr_update_except_clearing[each_bit]); + // Coverage Sampling: cover a scenario wherein cleared interrupt state bit + // is re-asserted due to still active interrupt event + if (cleared_intr_bits[each_bit]) begin + if (exp_intr_status[each_bit]) begin + cov.sticky_intr_cov[{"gpio_sticky_intr_pin", $sformatf("%0d", each_bit)}].sample(1'b1); + end else begin + cov.sticky_intr_cov[{"gpio_sticky_intr_pin", $sformatf("%0d", each_bit)}].sample(1'b0); + end + // Clear the flag + cleared_intr_bits[each_bit] = 1'b0; + end + // Interrupt Test coverage + cov.intr_test_cg.sample(each_bit, + last_intr_test_event[each_bit], + intr_enable[each_bit], + exp_intr_status[each_bit]); + end + end + // Clear last_intr_test_event + last_intr_test_event = '0; + `uvm_info(msg_id, $sformatf("Predicted interrupt status = 0x%0h [%0b]", + exp_intr_status, exp_intr_status), UVM_HIGH) + begin + gpio_reg_update_due_t crnt_intr_state_update; + // Keep update pending until register access is done + crnt_intr_state_update.needs_update = 1'b1; + crnt_intr_state_update.reg_value = exp_intr_status; + crnt_intr_state_update.eval_time = $time; + // Push new entry into queue + intr_state_update_queue.push_back(crnt_intr_state_update); + + // If queue already has two entries, remove 0th element + if (intr_state_update_queue.size() > 2) begin + intr_state_update_queue.delete(0); + end + end + endfunction : gpio_interrupt_predict + + // Function : update_gpio_out_regs + // This function is used for updating direct_out, masked_out_upper and masked_out_lower + // register values based on write to any one of these 3 registers. + // Note : Assumption for this method is that data_out has already been updated + // before calling the method. + function void update_gpio_out_regs(); + uvm_reg_data_t data; + // 1. Update "direct_out" register for writes to masked_out_* registers + // For write to "direct_out", it must have been updated already. + void'(ral.direct_out.predict(.value(data_out), .kind(UVM_PREDICT_WRITE))); + // 2. Update masked_out_lower + data = data_out; + for (uint idx = ral.masked_out_lower.data.get_n_bits(); + idx < `UVM_REG_DATA_WIDTH; + idx++) begin + data[idx] = 1'b0; + end + void'(ral.masked_out_lower.data.predict(.value(data), .kind(UVM_PREDICT_WRITE))); + // 3. Update masked_out_upper + data = 0; + for (uint idx = ral.masked_out_upper.data.get_n_bits(); + idx < `UVM_REG_DATA_WIDTH; + idx++) begin + data[idx - ral.masked_out_upper.data.get_n_bits()] = data_out[idx]; + end + void'(ral.masked_out_upper.data.predict(.value(data), .kind(UVM_PREDICT_WRITE))); + // Coverage Sampling: Coverage on DATA_OUT values and its combinations with DATA_OE + sample_data_out_data_oe_coverage(); + endfunction : update_gpio_out_regs + + // Function : update_gpio_oe_regs + // This function is used for updating direct_oe, masked_oe_upper and masked_oe_lower + // register values based on write to any one of these 3 registers. + // Note : Assumption for this method is that data_oe has already been updated + // before calling the method. + function void update_gpio_oe_regs(); + uvm_reg_data_t data; + const uvm_reg_data_t mask = 0; + // 1. Update "direct_oe" register for writes to masked_oe_* registers + // For write to "direct_oe", it must have been updated already. + void'(ral.direct_oe.predict(.value(data_oe), .kind(UVM_PREDICT_WRITE))); + // 2. Update masked_oe_lower + data = data_oe; + for (uint idx = ral.masked_oe_lower.data.get_n_bits(); idx < `UVM_REG_DATA_WIDTH; idx++) begin + data[idx] = 1'b0; + end + void'(ral.masked_oe_lower.mask.predict(.value(mask), .kind(UVM_PREDICT_WRITE))); + void'(ral.masked_oe_lower.data.predict(.value(data), .kind(UVM_PREDICT_WRITE))); + // 3. Update masked_oe_upper + data = 0; + for (uint idx = ral.masked_oe_upper.data.get_n_bits(); idx < `UVM_REG_DATA_WIDTH; idx++) begin + data[idx - ral.masked_oe_upper.data.get_n_bits()] = data_oe[idx]; + end + void'(ral.masked_oe_upper.mask.predict(.value(mask), .kind(UVM_PREDICT_WRITE))); + void'(ral.masked_oe_upper.data.predict(.value(data), .kind(UVM_PREDICT_WRITE))); + // Coverage Sampling: Coverage on DATA_OUT values and its combinations with DATA_OE + sample_data_out_data_oe_coverage(); + endfunction : update_gpio_oe_regs + + // Function: sample_data_out_data_oe_coverage + function void sample_data_out_data_oe_coverage(); + if (cfg.en_cov) begin + for (uint each_bit = 0; each_bit < NUM_GPIOS; each_bit++) begin + cov.data_out_data_oe_cov_obj[each_bit].var1_var2_cg.sample(data_out[each_bit], + data_oe[each_bit]); + end + end + endfunction : sample_data_out_data_oe_coverage + + // Function: reset + virtual function void reset(string kind = "HARD"); + super.reset(kind); + ral.reset(kind); + // Reset scoreboard variables + data_out = '0; + data_oe = '0; + intr_state_update_queue = {}; + data_in_update_queue = {}; + last_intr_update_except_clearing = '0; + last_intr_test_event = '0; + cleared_intr_bits = '0; + first_strap_triggered = 0; + endfunction + + // Function: check_phase + function void check_phase(uvm_phase phase); + super.check_phase(phase); + endfunction + +endclass : gpio_scoreboard diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_base_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_base_vseq.sv new file mode 100644 index 00000000000..4a73a511ee9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_base_vseq.sv @@ -0,0 +1,138 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class gpio_base_vseq extends cip_base_vseq #( + .CFG_T (gpio_env_cfg), + .RAL_T (gpio_reg_block), + .COV_T (gpio_env_cov), + .VIRTUAL_SEQUENCER_T (gpio_virtual_sequencer) + ); + + // Delay between consecutive transactions + rand uint delay; + bit do_init_reset = 1; + + constraint delay_c { + delay dist {0 :/ 20, [1:5] :/ 40, [6:15] :/ 30, [20:25] :/ 10}; + } + constraint num_trans_c { + num_trans inside {[20:200]}; + } + + `uvm_object_utils(gpio_base_vseq) + `uvm_object_new + + virtual task dut_init(string reset_kind = "HARD"); + if (do_init_reset) begin + // Check for weak pullup or weak pulldown requirement + if (cfg.pullup_en) begin + cfg.gpio_vif.set_pullup_en({NUM_GPIOS{1'b1}}); + //cfg.gpio_vif.set_pulldown_en({NUM_GPIOS{1'b0}}); + `uvm_info(`gfn, "weak pullup applied to gpio's", UVM_LOW) + end else if (cfg.pulldown_en) begin + //cfg.gpio_vif.set_pullup_en({NUM_GPIOS{1'b0}}); + cfg.gpio_vif.set_pulldown_en({NUM_GPIOS{1'b1}}); + `uvm_info(`gfn, "weak pulldown applied to gpio's", UVM_LOW) + end + super.dut_init(reset_kind); + end else begin + // since stress_all_with_rand_reset test have to turn off the reset here, + // this step makes sure that we reset out and oe pins to avoid drive x in gpio_in + drive_gpio_out('0); + drive_gpio_oe('0); + end + endtask : dut_init + + // Function: set_gpio_pulls + // This function is meant to override gpio pullup or pulldown value + // from extended sequence. + // Note: This function does not check whether only one of 'pu' and 'pd' is passed 1. + // If we pass both pu and pd to be 1, gpio pullup will be used. + protected function void set_gpio_pulls(bit pu = 1'b1, bit pd = 1'b0); + bit no_pullup_pulldown; + cfg.pullup_en = pu; + cfg.pulldown_en = pd; + if ($value$plusargs("no_pullup_pulldown=%0b", no_pullup_pulldown)) begin + if (no_pullup_pulldown == 1'b1) begin + cfg.pullup_en = 1'b0; + cfg.pulldown_en = 1'b0; + end + end + endfunction + + task pre_start(); + super.pre_start(); + endtask + + // Task: drive_gpio_in + // task to drive dut gpio inputs (gpio_en_o from dut must be configured to 0) + virtual task drive_gpio_in(bit [NUM_GPIOS-1:0] val); + ral.direct_oe.set('0); + csr_update(ral.direct_oe); + cfg.gpio_vif.drive(val); + endtask + + // Task: undrive_gpio_in + virtual task undrive_gpio_in(); + cfg.gpio_vif.drive_en('0); + endtask : undrive_gpio_in + + // Task: drive_gpio_out + // task to drive dut gpio outputs + virtual task drive_gpio_out(bit [NUM_GPIOS-1:0] val); + ral.direct_out.set(val); + csr_update(ral.direct_out); + endtask + + // Task: drive_gpio_oe + // task to drive dut gpio output enables + virtual task drive_gpio_oe(bit [NUM_GPIOS-1:0] val); + ral.direct_oe.set(val); + csr_update(ral.direct_oe); + endtask + + // Task: sample_gpio + // task to sample gpio pins + virtual task sample_gpio(ref bit [NUM_GPIOS-1:0] val); + val = cfg.gpio_vif.sample(); + endtask + + // Task : pgm_intr_regs + // This task program a random set of interrupt registers + // with random values + task pgm_intr_regs(); + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_enable) + csr_update(ral.intr_enable); + end + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_ctrl_en_falling) + csr_update(ral.intr_ctrl_en_falling); + end + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_ctrl_en_rising) + csr_update(ral.intr_ctrl_en_rising); + end + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_ctrl_en_lvllow) + csr_update(ral.intr_ctrl_en_lvllow); + end + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_ctrl_en_lvlhigh) + csr_update(ral.intr_ctrl_en_lvlhigh); + end + endtask : pgm_intr_regs + + // Wait a few cycles. If force_positive is true, Wait at least one clock cycle. + task short_wait(bit force_positive); + int unsigned delay; + `DV_CHECK_FATAL(std::randomize(delay) with + { + delay dist {0 :/ 20, [1:5] :/ 40, [6:15] :/ 30, [20:25] :/ 10}; + force_positive -> delay > 0; + }) + cfg.clk_rst_vif.wait_clks(delay); + endtask + +endclass : gpio_base_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_common_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_common_vseq.sv new file mode 100644 index 00000000000..468d992ea5d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_common_vseq.sv @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class gpio_common_vseq extends gpio_base_vseq; + `uvm_object_utils(gpio_common_vseq) + `uvm_object_new + + constraint num_trans_c { + num_trans inside {[1:3]}; + } + + virtual task dut_init(string reset_kind = "HARD"); + // Implement gpio pulldown for csr tests for avoiding comparison + // mismatch for DATA_IN register checks + set_gpio_pulls(.pu(1'b0), .pd(1'b1)); + super.dut_init(reset_kind); + endtask: dut_init + + virtual task body(); + run_common_vseq_wrapper(num_trans); + endtask : body + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv new file mode 100644 index 00000000000..38c2fab65f7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_dout_din_regs_random_rw_vseq.sv @@ -0,0 +1,93 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// class : gpio_dout_din_regs_random_rw_vseq +// This gpio random test sequence does any of the following: +// (i) drives random gpio input data values while gpio outputs are disabled +// (ii) programs random values of gpio direct output data, gpio direct output enable +// gpio masked outputs and gpio masked output enables. +class gpio_dout_din_regs_random_rw_vseq extends gpio_base_vseq; + + `uvm_object_utils(gpio_dout_din_regs_random_rw_vseq) + `uvm_object_new + + task body(); + `uvm_info(`gfn, $sformatf("num_trans = %0d", num_trans), UVM_HIGH) + for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin + // Stores either of following: + // 1. Write Data to be written to register + // 2. Register Read Data + logic [TL_DW-1:0] csr_val; + + `DV_CHECK_RANDOMIZE_FATAL(this) + // Insert some random delay + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + + randcase + // drive new gpio data in + 1: begin + // gpio input to drive + bit [NUM_GPIOS-1:0] gpio_i; + bit [TL_DW-1:0] data_in; + `uvm_info(`gfn, $sformatf("Transaction-%0d: drive random value to gpio_i", tr_num), + UVM_HIGH) + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) + // drive gpio_vif after setting all output enables to 0's + drive_gpio_in(gpio_i); + cfg.clk_rst_vif.wait_clks_or_rst(1); + + // read data_in register + csr_rd(.ptr(ral.data_in), .value(data_in)); + end + // write new value to any one of gpio data registers + 1: begin + `uvm_info(`gfn, $sformatf("Transaction-%0d: program a random gpio register", tr_num), + UVM_HIGH) + // First, stop driving gpio_i + undrive_gpio_in(); + // Randomize csr value + `DV_CHECK_STD_RANDOMIZE_FATAL(csr_val) + + randcase + 1: begin + // Add single clock cycle delay to avoid update and predict at + // the same time due to weak pull-up after undrive_gpio_in() + cfg.clk_rst_vif.wait_clks_or_rst(1); + + // DATA_IN register is RO, but writing random value to it + // should have no impact on gpio functionality + csr_wr(.ptr(ral.data_in), .value(csr_val)); + end + 1: csr_wr(.ptr(ral.direct_out ), .value(csr_val)); + 1: csr_wr(.ptr(ral.direct_oe ), .value(csr_val)); + 1: csr_wr(.ptr(ral.masked_out_lower), .value(csr_val)); + 1: csr_wr(.ptr(ral.masked_oe_lower ), .value(csr_val)); + 1: csr_wr(.ptr(ral.masked_out_upper), .value(csr_val)); + 1: csr_wr(.ptr(ral.masked_oe_upper ), .value(csr_val)); + endcase + end + // read any one of the gpio data registers + 1: begin + `uvm_info(`gfn, $sformatf("Transaction-%0d: read random register)", tr_num), UVM_HIGH) + randcase + 1: csr_rd(.ptr(ral.data_in ), .value(csr_val)); + 1: csr_rd(.ptr(ral.direct_out ), .value(csr_val)); + 1: csr_rd(.ptr(ral.direct_oe ), .value(csr_val)); + 1: csr_rd(.ptr(ral.masked_out_lower), .value(csr_val)); + 1: csr_rd(.ptr(ral.masked_oe_lower ), .value(csr_val)); + 1: csr_rd(.ptr(ral.masked_out_upper), .value(csr_val)); + 1: csr_rd(.ptr(ral.masked_oe_upper ), .value(csr_val)); + endcase + `uvm_info(`gfn, $sformatf("reg read data = 0x%0h [%0b]", csr_val, csr_val), UVM_HIGH) + end + endcase + `uvm_info(`gfn, $sformatf("End of Transaction-%0d", tr_num), UVM_HIGH) + + end // end for + + endtask : body + +endclass : gpio_dout_din_regs_random_rw_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_filter_stress_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_filter_stress_vseq.sv new file mode 100644 index 00000000000..cf3a37aa48b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_filter_stress_vseq.sv @@ -0,0 +1,201 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// class : gpio_filter_stress_vseq +// This gpio random test sequence performs random no. of iteration such that +// each iteration will the following operations: +// ( i) programs random set of interrupt registers with random values +// ( ii) programs CTRL_EN_INPUT_FILTER register to random value +// (iii) DATA_IN and INTR_STATE are read back and their read data are checked +// aginst predicted values. +// ( iv) random noise data (data with many frequent asynchronous toggling) is +// driven on gpio pins. After few cycles (less than FILTER_CYCLES), the +// are toggled to original values before noise was driven. This would make +// sure than noise filter does not see stable data on any pin long enough. +// ( v) DATA_IN and INTR_STATE are read back and their read data are checked +// aginst predicted values. +// ( vi) Non-noise data is driven multiple times (That is, gpio pins are kept +// stable for FILTER_CYCLES or longer). Every time after driving +// non-noise data, registers DATA_IN and INTR_STATE are read back and +// their read data are compared against predicted values. +class gpio_filter_stress_vseq extends gpio_intr_with_filter_rand_intr_event_vseq; + + `uvm_object_utils(gpio_filter_stress_vseq) + `uvm_object_new + + task body(); + bit [NUM_GPIOS-1:0] gpio_i; + bit [NUM_GPIOS-1:0] stable_value = (cfg.pullup_en) ? {NUM_GPIOS{1'b1}} : '0; + bit [NUM_GPIOS-1:0] crnt_intr_status; + `uvm_info(`gfn, $sformatf("num_trans = %0d", num_trans), UVM_HIGH) + + // Drive a new randomized gpio value initially for long enough + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) + cfg.gpio_vif.drive(gpio_i); + // Wait for FILTER_CYCLES to make sure that we start + // with stable gpio pins value + cfg.clk_rst_vif.wait_clks(FILTER_CYCLES); + stable_value = gpio_i; + + for (uint iter_num = 0; iter_num < num_trans; iter_num++) begin + `uvm_info(`gfn, $sformatf("Start of iteration-%0d", iter_num), UVM_HIGH) + + // program filter register + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_filter_value) + ral.ctrl_en_input_filter.set(gpio_filter_value); + csr_update(ral.ctrl_en_input_filter); + // Predict updated interrupt status register + update_intr_state(crnt_intr_status, stable_value, stable_value); + + // program random set of interrupt registers + pgm_intr_regs(); + // Calclulate update on interrupt state with new interrupt registers' + // programming + update_intr_state(crnt_intr_status, stable_value, stable_value); + // Read and check DATA_IN and INTR_STATE registers + read_and_check(stable_value, crnt_intr_status); + + begin : drive_noise_on_each_pin + repeat ($urandom_range(1, 10)) begin + fork : isolation_fork + begin + for (uint pin_num = 0; pin_num < NUM_GPIOS; pin_num++) begin + automatic uint pin = pin_num; + fork + begin + if (gpio_filter_value[pin] == 1'b1) begin + // Drive fully asynchronous noise for pins with filter enabled + drive_noise_on_pin(pin, gpio_i[pin]); + end else begin + uint ps_delay; + bit intr_state_this_pin = crnt_intr_status[pin]; + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(ps_delay, ps_delay inside {[1:10000]};) + // Drive single asynchronous change for pins with filter disabled + #(ps_delay * 1ps); + cfg.gpio_vif.drive_pin(pin, ~stable_value[pin]); + update_pin_intr_state(pin, + intr_state_this_pin, + stable_value[pin], + ~stable_value[pin]); + // update interrupt value for pin + crnt_intr_status[pin] = intr_state_this_pin; + // update stable value for pin + stable_value[pin] = ~stable_value[pin]; + end + end + join_none + end // end for loop + wait fork; + end // end isolation_fork + join + + // Keep driving toggled value until next clock edge + cfg.clk_rst_vif.wait_clks(1); + // Read and check DATA_IN and INTR_STATE registers + read_and_check(stable_value, crnt_intr_status); + end + end // drive_noise_on_each_pin + + // Drive some regular 'non-noise' data that stays unchanged for + // FILTER_CYCLES or more cycles + begin : drive_non_noise_data + repeat ($urandom_range(1, 10)) begin + uint num_clk_cycles; + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(num_clk_cycles, + num_clk_cycles inside {[(FILTER_CYCLES + 1) : + (FILTER_CYCLES + 10)]};) + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) + cfg.gpio_vif.drive(gpio_i); + cfg.clk_rst_vif.wait_clks(num_clk_cycles); + // Update predicted DATA_IN and INTR_STATE values + update_intr_state(crnt_intr_status, stable_value, gpio_i); + stable_value = gpio_i; + // Read and check DATA_IN and INTR_STATE registers + read_and_check(stable_value, crnt_intr_status); + end + end // drive_non_noise_data + + `uvm_info(`gfn, $sformatf("End of iteration-%0d", iter_num), UVM_HIGH) + end // end for + + endtask : body + + task drive_noise_on_pin(input uint pin_idx, + input bit crnt_gpio_pin_value); + bit pin_value = crnt_gpio_pin_value; + uint noise_length_cycles = $urandom_range(2, FILTER_CYCLES - 1); + bit noise_length_cycles_done; + uint async_drive_time_accumulated; + uint clk_period_ps = cfg.clk_rst_vif.clk_period_ps; + fork + begin : keep_driving_noise + while (async_drive_time_accumulated < (noise_length_cycles * clk_period_ps)) begin + uint ps_delay; + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(ps_delay, + ps_delay inside {[1:((noise_length_cycles * clk_period_ps) - 1)]};) + // Adjust ps_delay to avoid noise going beyond noise_length_cycles + // because it causes indeterministic filtering at times and test fails + if ((async_drive_time_accumulated + ps_delay) > + (noise_length_cycles * clk_period_ps) ) begin + ps_delay = (noise_length_cycles * clk_period_ps) - async_drive_time_accumulated; + end + // Add ps_delay to async_drive_time_accumulated + async_drive_time_accumulated += ps_delay; + // Wait for ps_delay + #(ps_delay * 1ps); + // Re-check if wait_noise_length_cycles thread has meanwhile finished + if (async_drive_time_accumulated < (noise_length_cycles * clk_period_ps)) begin + pin_value = ~pin_value; + cfg.gpio_vif.drive_pin(pin_idx, pin_value); + end + end + end + begin : wait_noise_length_cycles + cfg.clk_rst_vif.wait_clks(noise_length_cycles); + noise_length_cycles_done = 1'b1; + end + join + // Drive original pin value again + cfg.gpio_vif.drive_pin(pin_idx, crnt_gpio_pin_value); + endtask : drive_noise_on_pin + + function void update_pin_intr_state(input uint pin_idx, + ref bit pin_current_interrupt_state, + input bit pin_prev_filtered_value, + input bit pin_crnt_exp_filtered_value); + bit [NUM_GPIOS-1:0] intr_ctrl_en_rising = ral.intr_ctrl_en_rising.get(); + bit [NUM_GPIOS-1:0] intr_ctrl_en_falling = ral.intr_ctrl_en_falling.get(); + bit [NUM_GPIOS-1:0] intr_ctrl_en_lvlhigh = ral.intr_ctrl_en_lvlhigh.get(); + bit [NUM_GPIOS-1:0] intr_ctrl_en_lvllow = ral.intr_ctrl_en_lvllow.get(); + bit new_intr_state_updates; + + // Look for edge triggered interrupts + if (pin_crnt_exp_filtered_value != pin_prev_filtered_value) begin + if (((pin_prev_filtered_value == 1'b0 && pin_crnt_exp_filtered_value == 1'b1) && + intr_ctrl_en_rising[pin_idx] == 1'b1) || + ((pin_prev_filtered_value == 1'b1 && pin_crnt_exp_filtered_value == 1'b0) && + intr_ctrl_en_falling[pin_idx] == 1'b1)) begin + new_intr_state_updates = 1'b1; + end + end + // Look for level triggerred interrupts + if (new_intr_state_updates == 1'b0) begin + if ((pin_crnt_exp_filtered_value == 1'b1 && intr_ctrl_en_lvlhigh[pin_idx]) || + (pin_crnt_exp_filtered_value == 1'b0 && intr_ctrl_en_lvllow[pin_idx])) begin + new_intr_state_updates = 1'b1; + end + end + // Update interrupt value for pin_idx + pin_current_interrupt_state |= new_intr_state_updates; + endfunction : update_pin_intr_state + + task read_and_check(bit [NUM_GPIOS-1:0] predicted_data_in, + bit [NUM_GPIOS-1:0] predicted_intr_state); + // Read DATA_IN and check if predictaed and actual values match + csr_rd_check(.ptr(ral.data_in), .compare_value(predicted_data_in)); + // Read interrupt value after noise driving is finished + csr_rd_check(.ptr(ral.intr_state), .compare_value(predicted_intr_state)); + endtask : read_and_check + +endclass : gpio_filter_stress_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_full_random_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_full_random_vseq.sv new file mode 100644 index 00000000000..dd18500fb5c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_full_random_vseq.sv @@ -0,0 +1,303 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// class : gpio_full_random_vseq +// This gpio random test sequence performs random no. of iteration such that +// each iteration will do either of the following operations: +// (i) drives random gpio input data values such that none of the gpios become +// unknown value +// (ii) writes any of gpio registers +// (iii) reads any of gpio registers +class gpio_full_random_vseq extends gpio_random_long_reg_writes_reg_reads_vseq; + + // predicted value of DATA_OUT rtl implementation register + bit [NUM_GPIOS-1:0] data_out; + // predicted updated value of DATA_OE rtl implementation register + bit [NUM_GPIOS-1:0] data_oe; + // Previous value of gpio pins + bit [NUM_GPIOS-1:0] prev_gpio_val; + + `uvm_object_utils(gpio_full_random_vseq) + `uvm_object_new + + task body(); + // gpio pins_if pins_o value to drive + bit [NUM_GPIOS-1:0] gpio_i; + // gpio pins_if pins_oe value to drive + bit [NUM_GPIOS-1:0] gpio_i_oen; + `uvm_info(`gfn, $sformatf("num_trans = %0d", num_trans), UVM_HIGH) + // Wait for minimum 1 clock cycle initially to avoid reading of data_in + // immediately as the first iteration after reset, while data_in prediction + // is still being processed + cfg.clk_rst_vif.wait_clks(1); + // Initialize prev_gpio_val + prev_gpio_val = (cfg.pullup_en) ? '1 : '0; + + for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin + string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; + + `uvm_info(msg_id, "Start of Transaction", UVM_HIGH) + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) + cfg.clk_rst_vif.wait_clks(delay); + + randcase + // drive new gpio data in + 1: begin + `uvm_info(msg_id, $sformatf("Latest data_out = 0x%0h [%0b]", data_out, data_out), + UVM_HIGH) + `uvm_info(msg_id, $sformatf("Latest data_oe = 0x%0h [%0b]", data_oe, data_oe), + UVM_HIGH) + // Set all 1's in gpio_i_oen first up + gpio_i_oen = '1; + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) + `uvm_info(msg_id, $sformatf("drive random value 0x%0h on gpio_i", gpio_i), UVM_HIGH) + + foreach(gpio_i[pin]) begin + if (data_oe[pin]) begin + if (gpio_i[pin] != data_out[pin]) begin + data_oe[pin] = 1'b0; + end + else begin + bit gpio_i_oe_pin; + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i_oe_pin) + gpio_i_oen[pin] = gpio_i_oe_pin; + end + end + end + // Update data_oe reg value + ral.direct_oe.set(data_oe); + csr_update(ral.direct_oe); + // drive gpio_vif after setting all output enables to 0's + cfg.gpio_vif.pins_oe = gpio_i_oen; + cfg.gpio_vif.pins_o = gpio_i; + wait_for_filter_cyles(); + prev_gpio_val = cfg.gpio_vif.sample(); + `uvm_info(`gfn, $sformatf("prev_gpio_val updated to %0h", prev_gpio_val), UVM_HIGH) + end + 1: begin + pgm_out_oe_regs(.gpio_if_pins_o_val(gpio_i), .gpio_if_pins_oe_val(gpio_i_oen)); + end + 1: pgm_intr_regs(); + 1: pgm_misc_reg(); + 1: gpio_reg_rd(); + 1: begin + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) + cfg.clk_rst_vif.wait_clks(delay); + csr_utils_pkg::wait_no_outstanding_access(); + dut_init("HARD"); + data_out = '0; + data_oe = '0; + end + endcase + + `uvm_info(msg_id, "End of Transaction", UVM_HIGH) + + end // end for + + endtask : body + + // Task: pgm_out_oe_regs + // This task is for programming one or more of *out* and *oe* GPIO registers + // As some of the GPIO pins are already configured and driven as inputs, we need + // to make sure that DATA_OUT and DATA_OE combination is programmed such that: + // - Output driven on pin is same as GPIO input value, or + // - Outpurt enable on pin is 0 + // By doing either of above two options, we make sure that none of the GPIO pins + // become unknowns due to multiple drivers with conflicting values. + task pgm_out_oe_regs(bit [NUM_GPIOS-1:0] gpio_if_pins_o_val, + bit [NUM_GPIOS-1:0] gpio_if_pins_oe_val); + bit [TL_DW-1:0] csr_wr_value; + `DV_CHECK_STD_RANDOMIZE_FATAL(csr_wr_value) + + // write to direct_out reg + if ($urandom_range(0, 1)) begin + // Avoid 'x' due to different values driven from data_out + // and gpio_if_pins_o_val sides + for (uint pin = 0; pin < NUM_GPIOS; pin++) begin + if (data_oe[pin] == 1'b1 && gpio_if_pins_oe_val[pin] == 1'b1) begin + csr_wr_value[pin] = gpio_if_pins_o_val[pin]; + end + end + csr_wr(.ptr(ral.direct_out), .value(csr_wr_value)); + // Update value of data_out + data_out = csr_wr_value; + `uvm_info(`gfn, $sformatf("data_out updated to value %0h", data_out), UVM_HIGH) + // Check if there is update on gpio pins due to register update + gpio_pins_update_check(); + end + + // write to masked_out_lower reg + if ($urandom_range(0, 1)) begin + bit [(NUM_GPIOS/2)-1:0] mask, data; + {mask, data} = csr_wr_value; + for (uint pin = 0; pin < ral.masked_out_lower.mask.get_n_bits(); pin++) begin + if ((data_oe[pin] == 1'b1) && (gpio_if_pins_oe_val[pin] == 1'b1) && + (mask[pin] == 1'b1 && (data[pin] != gpio_if_pins_o_val[pin]))) begin + randcase + 1: data[pin] = gpio_if_pins_o_val[pin]; + 1: mask[pin] = 1'b0; + endcase + end + end + // updated csr_wr_value + csr_wr_value = {mask, data}; + csr_wr(.ptr(ral.masked_out_lower), .value(csr_wr_value)); + // Update data_out value + for (uint pin = 0; pin < ral.masked_out_lower.mask.get_n_bits(); pin++) begin + if (mask[pin] == 1'b1) begin + data_out[pin] = data[pin]; + end + end + `uvm_info(`gfn, $sformatf("data_out updated to value %0h", data_out), UVM_HIGH) + // Check if there is update on gpio pins due to register update + gpio_pins_update_check(); + end + + // write to masked_out_upper reg + if ($urandom_range(0, 1)) begin + bit [(NUM_GPIOS/2)-1:0] mask, data; + {mask, data} = csr_wr_value; + for (uint pin = 0; pin < ral.masked_out_upper.mask.get_n_bits(); pin++) begin + if ((data_oe[(NUM_GPIOS/2) + pin] == 1'b1) && + (gpio_if_pins_oe_val[(NUM_GPIOS/2) + pin] == 1'b1) && + (mask[pin] == 1'b1 && + (data[pin] != gpio_if_pins_o_val[(NUM_GPIOS/2) + pin]))) begin + randcase + 1: data[pin] = gpio_if_pins_o_val[(NUM_GPIOS/2) + pin]; + 1: mask[pin] = 1'b0; + endcase + end + end + // updated csr_wr_value + csr_wr_value = {mask, data}; + csr_wr(.ptr(ral.masked_out_upper), .value(csr_wr_value)); + // Update value of data_out + for (uint pin = 0; pin < ral.masked_out_upper.mask.get_n_bits(); pin++) begin + if (mask[pin] == 1'b1) begin + data_out[(NUM_GPIOS / 2) + pin] = data[pin]; + end + end + `uvm_info(`gfn, $sformatf("data_out updated to value %0h", data_out), UVM_HIGH) + // Check if there is update on gpio pins due to register update + gpio_pins_update_check(); + end + + // write to direct_oe reg + if ($urandom_range(0, 1)) begin + for (uint pin = 0; pin < NUM_GPIOS; pin++) begin + if ((csr_wr_value[pin] == 1'b1 && gpio_if_pins_oe_val[pin] == 1'b1) && + (data_out[pin] != gpio_if_pins_o_val[pin])) begin + csr_wr_value[pin] = 1'b0; + end + end + csr_wr(.ptr(ral.direct_oe), .value(csr_wr_value)); + // Update data_oe value + data_oe = csr_wr_value; + `uvm_info(`gfn, $sformatf("data_oe updated to value %0h", data_oe), UVM_HIGH) + // Check if there is update on gpio pins due to register update + gpio_pins_update_check(); + end + + // write to masked_oe_lower reg + if ($urandom_range(0, 1)) begin + bit [(NUM_GPIOS/2)-1:0] mask, data; + {mask, data} = csr_wr_value; + for (uint pin = 0; pin < ral.masked_oe_lower.mask.get_n_bits(); pin++) begin + if (mask[pin] == 1'b1 && data[pin] == 1'b1 && gpio_if_pins_oe_val[pin] == 1'b1 && + (data_out[pin] != gpio_if_pins_o_val[pin])) begin + randcase + 1: mask[pin] = 1'b0; + 1: data[pin] = 1'b0; + endcase + end + end + // updated csr_wr_value + csr_wr_value = {mask, data}; + csr_wr(.ptr(ral.masked_oe_lower), .value(csr_wr_value)); + // Update data_oe value + for (uint pin = 0; pin < ral.masked_oe_lower.mask.get_n_bits(); pin++) begin + if (mask[pin] == 1'b1) begin + data_oe[pin] = data[pin]; + end + end + `uvm_info(`gfn, $sformatf("data_oe updated to value %0h", data_oe), UVM_HIGH) + // Check if there is update on gpio pins due to register update + gpio_pins_update_check(); + end + + // write to masked_oe_upper + if ($urandom_range(0, 1)) begin + bit [(NUM_GPIOS/2)-1:0] mask, data; + {mask, data} = csr_wr_value; + for (uint pin = 0; pin < ral.masked_oe_upper.mask.get_n_bits(); pin++) begin + if (mask[pin] == 1'b1 && data[pin] == 1'b1 && + gpio_if_pins_oe_val[(TL_DW/2) + pin] == 1'b1 && + (data_out[(TL_DW/2) + pin] != gpio_if_pins_o_val[(TL_DW/2) + pin])) begin + randcase + 1: mask[pin] = 1'b0; + 1: data[pin] = 1'b0; + endcase + end + end + // updated csr_wr_value + csr_wr_value = {mask, data}; + csr_wr(.ptr(ral.masked_oe_upper), .value(csr_wr_value)); + // Update data_oe value + for (uint pin = 0; pin < ral.masked_oe_upper.mask.get_n_bits(); pin++) begin + if (mask[pin] == 1'b1) begin + data_oe[(NUM_GPIOS / 2) + pin] = data[pin]; + end + end + `uvm_info(`gfn, $sformatf("data_oe updated to value %0h", data_oe), UVM_HIGH) + // Check if there is update on gpio pins due to register update + gpio_pins_update_check(); + end + endtask : pgm_out_oe_regs + + task pgm_intr_regs(); + super.pgm_intr_regs(); + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_test) + `uvm_info(`gfn, "Writing to intr_test", UVM_NONE) + csr_update(.csr(ral.intr_test)); + end + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_state) + csr_update(.csr(ral.intr_state)); + end + endtask : pgm_intr_regs + + task pgm_misc_reg(); + randcase + 1: begin + `DV_CHECK_RANDOMIZE_FATAL(ral.data_in) + csr_update(.csr(ral.data_in)); + end + 1 : begin + `DV_CHECK_RANDOMIZE_FATAL(ral.ctrl_en_input_filter) + wait_for_filter_cyles(); + csr_update(.csr(ral.ctrl_en_input_filter)); + wait_for_filter_cyles(); + end + endcase + endtask : pgm_misc_reg + + // Function: gpio_pins_update_check + task gpio_pins_update_check(); + if (cfg.gpio_vif.sample() != prev_gpio_val) begin + // Wait until GPIO pins are stable + wait_for_filter_cyles(); + // Update prev_gpio_val + prev_gpio_val = cfg.gpio_vif.sample(); + end + endtask : gpio_pins_update_check + + // Task: wait_for_filter_cyles + task wait_for_filter_cyles; + // Wait for (FILTER_CYCLES + 1) clock cycles to make sure we can + // reliably read updated value of data_in even with filter enabled + cfg.clk_rst_vif.wait_clks(FILTER_CYCLES + 1); + endtask : wait_for_filter_cyles + +endclass : gpio_full_random_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_inp_prd_cnt_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_inp_prd_cnt_vseq.sv new file mode 100644 index 00000000000..d1c9aa332f9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_inp_prd_cnt_vseq.sv @@ -0,0 +1,115 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class gpio_inp_prd_cnt_vseq extends gpio_base_vseq; + `uvm_object_utils(gpio_inp_prd_cnt_vseq) + + // Random variables + // - GPIO inputs (driven by DV) + rand bit [NUM_GPIOS-1:0] gpio_i; + // - input period counter to test + rand int unsigned cnt_idx; + // - input to test + rand int unsigned inp_idx; + + `uvm_object_new + + task enable_inp_prd_cnt(bit continuous_mode, + int unsigned prescaler); + ral.inp_prd_cnt_ctrl[cnt_idx].enable.set(1); + ral.inp_prd_cnt_ctrl[cnt_idx].continuous_mode.set(continuous_mode); + ral.inp_prd_cnt_ctrl[cnt_idx].input_select.set(inp_idx); + ral.inp_prd_cnt_ctrl[cnt_idx].prescaler.set(prescaler); + csr_update(.csr(ral.inp_prd_cnt_ctrl[cnt_idx])); + endtask + + task disable_inp_prd_cnt(); + ral.inp_prd_cnt_ctrl[cnt_idx].enable.set(0); + csr_update(.csr(ral.inp_prd_cnt_ctrl[cnt_idx])); + endtask + + task drive_gpio(bit value); + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_i) + gpio_i[inp_idx] = value; + cfg.gpio_vif.drive(gpio_i); + endtask + + task drive_10_pattern(int unsigned cycles_after_0); + drive_gpio(.value(1'b1)); + cfg.clk_rst_vif.wait_clks_or_rst(1); + drive_gpio(.value(1'b0)); + cfg.clk_rst_vif.wait_clks_or_rst(cycles_after_0); + endtask + + task drive_1010_pattern(int unsigned cycles_between_1); + drive_10_pattern(.cycles_after_0(cycles_between_1)); + drive_10_pattern(.cycles_after_0(0)); + endtask + + task test_non_continuous(int unsigned prescaler, + int unsigned cycles_between_1, + int unsigned exp_val); + bit [TL_DW-1:0] act_val; + + enable_inp_prd_cnt(.continuous_mode(0), .prescaler(prescaler)); + drive_1010_pattern(.cycles_between_1(cycles_between_1)); + + // It may take up to `prescaler` cycles for the counter to be updated. + cfg.clk_rst_vif.wait_clks_or_rst(prescaler); + + // Read the value of the input pattern counter and check that it matches the expected value. + csr_rd(.ptr(ral.inp_prd_cnt_val[cnt_idx]), .value(act_val)); + `DV_CHECK_EQ(act_val, exp_val) + endtask + + task test_continuous_two_patterns(int unsigned prescaler, + int unsigned cycles_between_first_1, + int unsigned cycles_between_second_1, + int unsigned exp_val); + bit [TL_DW-1:0] act_val; + + enable_inp_prd_cnt(.continuous_mode(1), .prescaler(prescaler)); + drive_10_pattern(.cycles_after_0(cycles_between_first_1)); + drive_1010_pattern(.cycles_between_1(cycles_between_second_1)); + + // It may take up to `prescaler` cycles for the counter to be updated. + cfg.clk_rst_vif.wait_clks_or_rst(prescaler); + + // Read the value of the input pattern counter and check that it matches the expected value. + csr_rd(.ptr(ral.inp_prd_cnt_val[cnt_idx]), .value(act_val)); + `DV_CHECK_EQ(act_val, exp_val) + + // Disable the input pattern counter ahead of the next continuous test case. + disable_inp_prd_cnt(); + endtask + + task body(); + // Randomize vseq variables. + `DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(cnt_idx, cnt_idx < NUM_INP_PRD_CNT;) + `DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(inp_idx, inp_idx < NUM_GPIOS;) + + // Initialize GPIO inputs (zero for selected input, random for all others). + drive_gpio(.value(1'b0)); + + // Test case 1: 1010 pattern in non-continuous mode and with prescaler 0. + test_non_continuous(.prescaler(0), .cycles_between_1(1), .exp_val(1)); + + // Test case 2: 10010 pattern in non-continuous mode and with prescaler 0. + test_non_continuous(.prescaler(0), .cycles_between_1(2), .exp_val(2)); + + // Test case 3: 10010 pattern in non-continuous mode and with prescaler 1. + test_non_continuous(.prescaler(1), .cycles_between_1(2), .exp_val(1)); + + // Test case 4: 101010 pattern in continuous mode and with prescaler 0. + test_continuous_two_patterns(.prescaler(0), .cycles_between_first_1(1), + .cycles_between_second_1(1), .exp_val(1)); + + // Test case 5: 1010010 pattern in continuous mode and with prescaler 0. + test_continuous_two_patterns(.prescaler(0), .cycles_between_first_1(1), + .cycles_between_second_1(2), .exp_val(2)); + + // TODO(#26544): Test many more random patterns with different settings. + endtask + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv new file mode 100644 index 00000000000..600010086ee --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_intr_rand_pgm_vseq.sv @@ -0,0 +1,95 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// class : gpio_intr_rand_pgm_vseq +// This gpio random test sequence performs random no. of iteration such that +// each iteration will do either of the following operations: +// (i) drives random gpio input data values while gpio outputs are disabled +// (ii) programs random values to a set of selected registers out of following: +// INTR_ENABLE +// INTR_STATE +// INTR_CTRL_EN_LVL_LOW +// INTR_CTRL_EN_LVL_HIGH +// INTR_CTRL_EN_FALLING +// INTR_CTRL_EN_RISING +class gpio_intr_rand_pgm_vseq extends gpio_base_vseq; + + `uvm_object_utils(gpio_intr_rand_pgm_vseq) + `uvm_object_new + + task body(); + `uvm_info(`gfn, $sformatf("num_trans = %0d", num_trans), UVM_HIGH) + for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin + string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; + + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + + randcase + // drive new gpio data in + 1: begin + // gpio input to drive + bit [NUM_GPIOS-1:0] gpio_i; + bit [NUM_GPIOS-1:0] data_in; + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) + `uvm_info(msg_id, "drive random value on gpio_i", UVM_HIGH) + // drive gpio_vif after setting all output enables to 0's + drive_gpio_in(gpio_i); + + cfg.clk_rst_vif.wait_clks_or_rst(1); + // read data_in register + csr_rd(.ptr(ral.data_in), .value(data_in)); + end + // write random value(s) to gpio interrupt register(s) + 1: begin + `uvm_info(msg_id, "program interrupt register(s) to random value(s)", UVM_HIGH) + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_enable) + csr_update(ral.intr_enable); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_ctrl_en_falling) + csr_update(ral.intr_ctrl_en_falling); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_ctrl_en_rising) + csr_update(ral.intr_ctrl_en_rising); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_ctrl_en_lvllow) + csr_update(ral.intr_ctrl_en_lvllow); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_ctrl_en_lvlhigh) + csr_update(ral.intr_ctrl_en_lvlhigh); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_state) + csr_update(ral.intr_state); + end + end + endcase + // Read interrupt state register value + begin + bit [TL_DW-1:0] reg_rd_data; + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // read intr_state register + csr_rd(.ptr(ral.intr_state), .value(reg_rd_data)); + end + `uvm_info(msg_id, "End of Transaction", UVM_HIGH) + + end // end for + + endtask : body + +endclass : gpio_intr_rand_pgm_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_intr_with_filter_rand_intr_event_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_intr_with_filter_rand_intr_event_vseq.sv new file mode 100644 index 00000000000..573a5c72c88 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_intr_with_filter_rand_intr_event_vseq.sv @@ -0,0 +1,305 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// class : gpio_intr_with_filter_rand_intr_event_vseq +// This gpio random test sequence performs random no. of iteration such that +// each iteration will the following operations: +// ( i) programs random set of interrupt registers with random values +// ( ii) optionally, programs CTRL_EN_INPUT_FILTER register to random value +// (iii) drives random gpio input data values while gpio outputs are disabled, +// such that different pins changes value at random number of cycles +// selected within [1:15] range, or stays same for 16 cycles. +// This test sequence reads DATA_IN and INTR_STATE register multiple times +// and every time, it checks for corresponding expected register value. +class gpio_intr_with_filter_rand_intr_event_vseq extends gpio_base_vseq; + + // Random variable to specify for how many cycles one would like to keep + // gpio input pin value stable + rand uint stable_cycles_per_pin [NUM_GPIOS]; + + // Filter enable value + bit [TL_DW-1:0] gpio_filter_value; + + constraint stable_cycles_for_input_c { + foreach (stable_cycles_per_pin[i]) + stable_cycles_per_pin[i] dist { [1:FILTER_CYCLES-1] :/ 70, + FILTER_CYCLES :/ 30 }; + } + + covergroup pins_stable_period_and_filter_cg with function sample(uint pin, + uint stable_cycles, + bit pin_value, + bit filter_en); + cp_pins: coverpoint pin { + bins all_gpio_pins[] = {[0:NUM_GPIOS-1]}; + } + cp_stable_cycles: coverpoint stable_cycles { + bins one_to_filter_cycles_minus_1[] = {[1:FILTER_CYCLES - 1]}; + bins filter_cycles_or_more = {[FILTER_CYCLES:$]}; + } + cp_pin_value: coverpoint pin_value; + cp_filter_en: coverpoint filter_en; + cp_cross: cross cp_pins, cp_stable_cycles, cp_pin_value, cp_filter_en; + endgroup : pins_stable_period_and_filter_cg + + `uvm_object_utils(gpio_intr_with_filter_rand_intr_event_vseq) + + function new(string name = "gpio_intr_with_filter_rand_intr_event_vseq"); + super.new(name); + pins_stable_period_and_filter_cg = new(); + endfunction : new + + task sample_stable_cycles_and_filter_coverage(); + // Sampling coverage related to gpio pins' stable cycles + bit [NUM_GPIOS-1:0] prev_pins_val = (cfg.pullup_en == 1'b1) ? '1 : '0; + bit [NUM_GPIOS-1:0] crnt_pins_val; + uint stable_cycles_cnt[NUM_GPIOS]; + forever @(cfg.clk_rst_vif.cb) begin + // Assign current sampled gpio value + crnt_pins_val = cfg.gpio_vif.sample(); + foreach (crnt_pins_val[each_pin]) begin + if (crnt_pins_val[each_pin] == prev_pins_val[each_pin]) begin + stable_cycles_cnt[each_pin]++; + end else begin + stable_cycles_cnt[each_pin] = 1; + end + pins_stable_period_and_filter_cg.sample(each_pin, + stable_cycles_cnt[each_pin], + crnt_pins_val[each_pin], + gpio_filter_value[each_pin]); + end + // Update previous gpio value + prev_pins_val = crnt_pins_val; + end + endtask : sample_stable_cycles_and_filter_coverage + + task body(); + bit [NUM_GPIOS-1:0] gpio_i; + bit [NUM_GPIOS-1:0] stable_value = (cfg.pullup_en) ? {NUM_GPIOS{1'b1}} : '0; + bit [TL_DW-1:0] crnt_intr_status; + `uvm_info(`gfn, $sformatf("num_trans = %0d", num_trans), UVM_HIGH) + // Wait for FILTER_CYCLES to make sure that we start + // with stable gpio pins value + cfg.clk_rst_vif.wait_clks(FILTER_CYCLES); + + // Sample coverage for pins' stable cycles and filter + if (cfg.en_cov) begin + fork + sample_stable_cycles_and_filter_coverage(); + join_none + end + + for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin + string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; + uint tmp_q[$]; + // Minimum no. of cycles required after driving is done, to have + // get GPIO pins with stable and updated value with noise filter + uint additional_clk_cycles_until_all_gpio_pins_stable; + // Maximum no. of stable cycles among all the pins + uint max_stable_cycles; + + `uvm_info(msg_id, $sformatf("crnt_intr_status = 0x%0h [%0b]", + crnt_intr_status, crnt_intr_status), UVM_HIGH) + // Program random set of interrupt registers + pgm_intr_regs(); + // Predict updated interrupt status register + update_intr_state(crnt_intr_status, stable_value, stable_value); + // Program filter register + if ($urandom_range(0, 1)) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_filter_value) + ral.ctrl_en_input_filter.set(gpio_filter_value); + csr_update(ral.ctrl_en_input_filter); + end + `uvm_info(msg_id, $sformatf("gpio_filter_value = 0x%0h [%0b]", + gpio_filter_value, gpio_filter_value), UVM_HIGH) + // Predict updated interrupt status register again + update_intr_state(crnt_intr_status, stable_value, stable_value); + // Randomize gpio data + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(stable_cycles_per_pin) + foreach (stable_cycles_per_pin[each_pin]) begin + if (gpio_filter_value[each_pin] == 0) begin + stable_cycles_per_pin[each_pin] = FILTER_CYCLES; + end + end + `uvm_info(`gfn, $sformatf("stable_cycles_per_pin = %0p", stable_cycles_per_pin), UVM_HIGH) + `uvm_info(`gfn, $sformatf("gpio_i = 0x%0h [%0b]", gpio_i, gpio_i), UVM_HIGH) + // Calculate additional_clk_cycles_until_all_gpio_pins_stable + tmp_q = stable_cycles_per_pin.find(m) with (m != FILTER_CYCLES); + tmp_q.rsort(); + additional_clk_cycles_until_all_gpio_pins_stable = tmp_q[0]; + // Find maximum stable cycles among all pins + tmp_q.delete(); + tmp_q = stable_cycles_per_pin; + tmp_q.rsort(); + max_stable_cycles = tmp_q[0]; + // Program direct_oe to all 0's + if (tr_num == 0) begin + ral.direct_oe.set('0); + csr_update(ral.direct_oe); + end + + `uvm_info(msg_id, "Start driving new random value in gpio_i", UVM_HIGH) + fork + begin : drive_each_pin + for (uint pin_num = 0; pin_num < NUM_GPIOS; pin_num++) begin + automatic uint pin = pin_num; + fork + begin + cfg.gpio_vif.pins_oe[pin] = 1'b1; + cfg.gpio_vif.pins_o[pin] = gpio_i[pin]; + // When filter is not enabled, keep value stable + cfg.clk_rst_vif.wait_clks(stable_cycles_per_pin[pin]); + // Toggle pin if stable cycles are less than FILTER_CYCLES + if (stable_cycles_per_pin[pin] < FILTER_CYCLES) begin + cfg.gpio_vif.pins_o[pin] = ~gpio_i[pin]; + end + end + join_none + end + wait fork; + + // If one of more pins had FILTER_CYCLES no. of stable cycles, + // expect those pins' gpio_i data to be filtered out and hence + // interrupt update is expected + if (max_stable_cycles == FILTER_CYCLES) begin + bit [NUM_GPIOS-1:0] latest_stable_value = stable_value; + foreach (stable_cycles_per_pin[pin]) begin + if (stable_cycles_per_pin[pin] == FILTER_CYCLES) begin + latest_stable_value[pin] = gpio_i[pin]; + end + end + update_intr_state(crnt_intr_status, stable_value, latest_stable_value); + stable_value = latest_stable_value; + `uvm_info(msg_id, $sformatf("stable_value updated to %0h", stable_value), UVM_HIGH) + end + end // drive_each_pin + + begin : csr_read_and_check + uint num_cycles_elapsed; + bit [NUM_GPIOS-1:0] expected_value_data_in = predict_data_in_value(gpio_filter_value, + stable_value, + gpio_i); + // Predict updated interrupt status register again + update_intr_state(crnt_intr_status, stable_value, expected_value_data_in); + `uvm_info(msg_id, $sformatf("crnt_intr_status = 0x%0h [%0b]", + crnt_intr_status, crnt_intr_status), UVM_HIGH) + `uvm_info(`gfn, $sformatf("Expected data in = 0x%0h [%0b]", + expected_value_data_in, expected_value_data_in), UVM_HIGH) + fork + begin : count_clock + while (num_cycles_elapsed < FILTER_CYCLES) begin + cfg.clk_rst_vif.wait_clks(1); + num_cycles_elapsed++; + end // count_clock + end + begin : csr_rd_and_check + // Actual rtl register update takes additional cycle + // So if we read DATA_IN or INTR_STATE register immediately on + // subsequent clock cycle of write, we may still get older value + cfg.clk_rst_vif.wait_clks(1); + do begin + randcase + 3: csr_rd_check(.ptr(ral.intr_state), .compare_value(crnt_intr_status)); + 1: csr_rd_check(.ptr(ral.data_in), .compare_value(expected_value_data_in)); + endcase + end + while (num_cycles_elapsed < (FILTER_CYCLES -2)); + end // csr_rd_and_check + join // end fork..join + end // csr_read_and_check + + join + + begin : wait_all_pins_stable + uint cycles_after_16_per_pin[NUM_GPIOS]; + bit [NUM_GPIOS-1:0] latest_stable_value = stable_value; + repeat (additional_clk_cycles_until_all_gpio_pins_stable) begin + cfg.clk_rst_vif.wait_clks(1); + `uvm_info(msg_id, "After one clock cycle", UVM_HIGH) + foreach (stable_cycles_per_pin[pin]) begin + cycles_after_16_per_pin[pin]++; + if (cycles_after_16_per_pin[pin] == stable_cycles_per_pin[pin]) begin + latest_stable_value[pin] = ~gpio_i[pin]; + `uvm_info(msg_id, $sformatf("updating latest_stable_value[%0d] to %0b", + pin, latest_stable_value[pin]), UVM_HIGH) + end + end + // Check for interrupt update based on stabilized pin + update_intr_state(crnt_intr_status, stable_value, latest_stable_value); + stable_value = latest_stable_value; + end + // Additional cycle for rtl to latch updated DATA_IN and INTR_STATE values + cfg.clk_rst_vif.wait_clks(1); + stable_value = cfg.gpio_vif.pins; + // Predict updated interrupt status register again + update_intr_state(crnt_intr_status, stable_value, stable_value); + // Read and check DATA_IN value + csr_rd_check(.ptr(ral.data_in), .compare_value(stable_value)); + // Read and check INTR_STATE value + csr_rd_check(.ptr(ral.intr_state), .compare_value(crnt_intr_status)); + end // wait_all_pins_stable + + `uvm_info(msg_id, "End of Transaction", UVM_HIGH) + + end // end for + + endtask : body + + // Function: predict_data_in_value + // This function considers current 'unfiltered' value of gpio_i and + // predicts expected effective data_in value based on following: + // ( i) noise filter programming, and + // (ii) previous filtered value + function bit [NUM_GPIOS-1:0] predict_data_in_value( + input bit [ TL_DW-1:0] filter_en, + input bit [NUM_GPIOS-1:0] crnt_filtered_value, + input bit [NUM_GPIOS-1:0] gpio_i); + string msg_id = {`gfn, " predict_data_in_value: "}; + for (uint i = 0; i < NUM_GPIOS; i++) begin + predict_data_in_value[i] = filter_en[i] ? crnt_filtered_value[i] : gpio_i[i]; + `uvm_info(msg_id, { $sformatf("pin-%0d filter_en[%0d] = %0b", i, i, filter_en[i]), + $sformatf("crnt_filtered_value[%0d] = %0b", i, crnt_filtered_value[i]), + $sformatf("gpio_i[%0d] = %0b", i, gpio_i[i]) }, UVM_HIGH) + end + endfunction : predict_data_in_value + + // Function: update_intr_state + // This function takes current interrupt state as reference, and calculates + // updated interrupt state value based on following: + // (i) interrupt control registers' values + // (ii) previous filtered gpio value + // (iii) currently filtered gpio value + function void update_intr_state( ref bit [ TL_DW-1:0] current_interrupt_state, + input bit [NUM_GPIOS-1:0] prev_filtered_value, + input bit [NUM_GPIOS-1:0] crnt_exp_filtered_value); + bit [NUM_GPIOS-1:0] intr_ctrl_en_rising = ral.intr_ctrl_en_rising.get(); + bit [NUM_GPIOS-1:0] intr_ctrl_en_falling = ral.intr_ctrl_en_falling.get(); + bit [NUM_GPIOS-1:0] intr_ctrl_en_lvlhigh = ral.intr_ctrl_en_lvlhigh.get(); + bit [NUM_GPIOS-1:0] intr_ctrl_en_lvllow = ral.intr_ctrl_en_lvllow.get(); + bit [TL_DW-1:0] new_intr_state_updates; + + foreach (crnt_exp_filtered_value[pin]) begin + // Look for edge triggered interrupts + if (crnt_exp_filtered_value[pin] != prev_filtered_value[pin]) begin + if (((prev_filtered_value[pin] == 1'b0 && crnt_exp_filtered_value[pin] == 1'b1) && + intr_ctrl_en_rising[pin] == 1'b1) || + ((prev_filtered_value[pin] == 1'b1 && crnt_exp_filtered_value[pin] == 1'b0) && + intr_ctrl_en_falling[pin] == 1'b1)) begin + new_intr_state_updates[pin] = 1'b1; + end + end + // Look for level triggerred interrupts + if (new_intr_state_updates[pin] == 1'b0) begin + if ((crnt_exp_filtered_value[pin] == 1'b1 && intr_ctrl_en_lvlhigh[pin]) || + (crnt_exp_filtered_value[pin] == 1'b0 && intr_ctrl_en_lvllow[pin])) begin + new_intr_state_updates[pin] = 1'b1; + end + end + // Update interrupt value for pin + current_interrupt_state[pin] |= new_intr_state_updates[pin]; + end + endfunction : update_intr_state + +endclass : gpio_intr_with_filter_rand_intr_event_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv new file mode 100644 index 00000000000..1c06bb4b8b8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_rand_intr_trigger_vseq.sv @@ -0,0 +1,99 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// class : gpio_rand_intr_trigger_vseq +// This gpio random test sequence performs following in each of multiple iterations: +// (i) programs random values to a set of selected registers out of following: +// INTR_ENABLE +// INTR_CTRL_EN_LVL_LOW +// INTR_CTRL_EN_LVL_HIGH +// INTR_CTRL_EN_FALLING +// INTR_CTRL_EN_RISING +// (ii) performs following two in operations in parallel: +// - drive random value on gpio_i input +// - perform periodic read and random clearing of INTR_STATE register +class gpio_rand_intr_trigger_vseq extends gpio_base_vseq; + + constraint num_trans_c { + num_trans inside {[20:200]}; + } + + `uvm_object_utils(gpio_rand_intr_trigger_vseq) + `uvm_object_new + + task body(); + `uvm_info(`gfn, $sformatf("num_trans = %0d", num_trans), UVM_HIGH) + for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin + string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; + + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + `uvm_info(msg_id, $sformatf("delay = %0d", delay), UVM_HIGH) + + // Step-1 Program interrupt registers + pgm_intr_regs(); + + // Step-2 Do the following operations in parallel: + // (i) toggle gpio_i input at random intervals + // (ii) inject random read on gpio "intr_state" register + begin + uint cnt_gpio_tgl; + bit gpio_tgl_cycle_done; + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(cnt_gpio_tgl, cnt_gpio_tgl inside {[5:20]};) + fork + begin : gpio_in_data_drive + for (uint iter = 0; iter < cnt_gpio_tgl; iter++) begin + bit [TL_DW-1:0] gpio_i; + bit [TL_DW-1:0] data_in; + int delay_before_gpio_change; + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) + `uvm_info(msg_id, $sformatf("Driving new gpio value 0x%0h", gpio_i), UVM_HIGH) + cfg.gpio_vif.drive(gpio_i); + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(delay_before_gpio_change, + delay_before_gpio_change inside {[1:5]};) + cfg.clk_rst_vif.wait_clks_or_rst(delay_before_gpio_change); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) break; + end + gpio_tgl_cycle_done = 1'b1; + end + begin : periodic_intr_state_rd_check + do begin + uint rd_period; + bit [TL_DW-1:0] reg_rd_data; + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(rd_period, rd_period inside {[2:20]};) + + cfg.clk_rst_vif.wait_clks_or_rst(rd_period); + `uvm_info(msg_id, $sformatf("Reading intr_state after %0d more clock cycles", + rd_period), UVM_HIGH) + randcase + 1: begin + csr_rd(.ptr(ral.data_in), .value(reg_rd_data)); + end + 9: begin + csr_rd(.ptr(ral.intr_state), .value(reg_rd_data)); + end + endcase + // Randomly clear random set of interrupt state register bits + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.intr_state) + `uvm_info(msg_id, $sformatf("Writing value 0x%0h to intr_state", + ral.intr_state.get()), UVM_HIGH) + csr_update(ral.intr_state); + end + end + while (gpio_tgl_cycle_done != 1'b1); + end + join + end + + `uvm_info(msg_id, "End of Transaction", UVM_HIGH) + + end // end for + + endtask : body + +endclass : gpio_rand_intr_trigger_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_rand_straps_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_rand_straps_vseq.sv new file mode 100644 index 00000000000..1d22606331c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_rand_straps_vseq.sv @@ -0,0 +1,142 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Verify the straps data/valid ouput expected values based on the strap_en and gpio_in inputs: +// - Drive gpio_in input with random values. +// - Set the strap_en high for at least one clock cycle. +// - Read the registers hw_straps_data_in and hw_straps_data_in_valid. +// - The data read and sampled_straps_o will be checked in the scoreboard. +// - Drive the gpio_out to make sure that has no impact on straps registers. +// - Read to make sure that if does not affect the straps registers after drive the gpio_out. +// - Apply reset and make sure the strap registers are clean. +// - Read straps registers after reset. +// - Iterate again the same flow, with new random values. +class gpio_rand_straps_vseq extends gpio_base_vseq; + + `uvm_object_utils(gpio_rand_straps_vseq) + + // gpio input to drive + rand bit [NUM_GPIOS-1:0] gpio_in; + // gpio output to program in register + rand bit [NUM_GPIOS-1:0] gpio_out; + // gpio output enable to program in register + rand bit [NUM_GPIOS-1:0] gpio_oe; + + function new(string name = "gpio_rand_straps_vseq"); + super.new(name); + endfunction + + // Read hw_straps_data_in and hw_straps_data_in_valid and + // check they match the expected value in + // the scoreboard + task csr_strap_read(); + fork + begin + uvm_status_e status; + ral.hw_straps_data_in.mirror(status, UVM_CHECK); + `DV_CHECK_EQ(status, UVM_IS_OK) + `uvm_info(`gfn, $sformatf("Read the data_in status = %0d", status), UVM_HIGH) + end + begin + uvm_status_e status; + ral.hw_straps_data_in_valid.mirror(status, UVM_CHECK); + `DV_CHECK_EQ(status, UVM_IS_OK) + `uvm_info(`gfn, $sformatf("Read the data valid status = %0d", status), UVM_HIGH) + end + join + endtask : csr_strap_read + + task test_straps_gpio_in(); + // Drive the gpio_in + drive_gpio_in(gpio_in); + + // Random wait to drive the strap_en + // The strap feature should work from zero clock cycles + // after driving the gpio_i inputs into the interface. + short_wait(0); + + // Trigger the snapshot of gpio_in to be stored in the straps registers + cfg.straps_vif_inst.tb_port.strap_en = 1; + // Wait at least one clock cycle to update the strap register values. + short_wait(1); + + // Read the hw_straps_data_in registers and check the expected value in the scoreboard + csr_strap_read(); + + // Random wait + short_wait(0); + + // Stop driving gpio_in to make sure that, this is not affecting the strap_en registers + // so it will keep the same values were stored before. + undrive_gpio_in(); + + // Random wait + short_wait(0); + + // Read to make sure that if does not affect the straps registers after undrive the gpio_in + csr_strap_read(); + + endtask : test_straps_gpio_in + + task test_straps_gpio_out(); + + // Additional verification + // Drive the gpio_out to make sure that has no impact on straps registers. + // then read the gpio strap registers again + cfg.gpio_vif.drive_en('0); + csr_wr(ral.direct_out, gpio_out); + csr_wr(ral.direct_oe, gpio_oe); + + // Random wait + short_wait(0); + + // Read to make sure that if does not affect the straps registers after drive the gpio_out + csr_strap_read(); + + endtask : test_straps_gpio_out + + // This task start the strap en test. First it will test the strap enable + // with the driven gpio_i. On a second step drive the gpio_out and check the strap + // registers based on that. And finally applies a second reset and check if the strap registers + // are reseted. + task start_test(); + + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_in) + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_out) + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_oe) + + // User case to test the straps output, with gpio_in data randomised + test_straps_gpio_in(); + + // User case to test the straps output/registers, with gpio_out data randomised + // The gpio_out should not affect the straps output/registers. + test_straps_gpio_out(); + + // Random wait + short_wait(0); + + // Set zero to the strap_en input. + cfg.straps_vif_inst.tb_port.strap_en = 0; + // Apply reset and make sure the strap registers are clean + apply_reset(); + + // Random wait + // At least one clock cycle required to take the updated register values. + short_wait(1); + + // Read the straps registers after reset + csr_strap_read(); + + endtask : start_test + + task body(); + `uvm_info(`gfn, "Starting the test", UVM_HIGH) + // Just a minimum one clock cycle wait between more than one iteration if this + // test is executed into the stress_all virtual sequence. + short_wait(1); + start_test(); + `uvm_info(`gfn, "End of the test", UVM_HIGH) + endtask : body + +endclass : gpio_rand_straps_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv new file mode 100644 index 00000000000..5ca87d6043b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_random_dout_din_vseq.sv @@ -0,0 +1,98 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// class : gpio_random_dout_din_vseq +// This gpio random test sequence does any of the following: +// (i) drives random gpio input data values while gpio outputs are disabled +// (ii) programs random values of one or more registers out of following: +// gpio direct output data +// gpio direct output enable +// gpio masked output data lower +// gpio masked output data upper +// gpio masked output enable lower +// gpio masked output enable upper +class gpio_random_dout_din_vseq extends gpio_base_vseq; + + `uvm_object_utils(gpio_random_dout_din_vseq) + `uvm_object_new + + virtual task dut_init(string reset_kind = "HARD"); + // Continue using randomized value by default, unless plusarg + // no_pullup_pulldown is passed to have no pullup/pulldown + set_gpio_pulls(.pu(cfg.pullup_en), .pd(cfg.pulldown_en)); + super.dut_init(reset_kind); + endtask: dut_init + + task body(); + `uvm_info(`gfn, $sformatf("num_trans = %0d", num_trans), UVM_HIGH) + for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin + + `DV_CHECK_RANDOMIZE_FATAL(this) + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + + randcase + // drive new gpio data in + 1: begin + // gpio input to drive + bit [NUM_GPIOS-1:0] gpio_i; + bit [NUM_GPIOS-1:0] data_in; + `uvm_info(`gfn, $sformatf("Transaction-%0d: drive random value to gpio_i", tr_num), + UVM_HIGH) + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) + // drive gpio_vif after setting all output enables to 0's + drive_gpio_in(gpio_i); + cfg.clk_rst_vif.wait_clks_or_rst(1); + + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) break; + // read data_in register + csr_rd(.ptr(ral.data_in), .value(data_in)); + end + // write new value(s) to gpio out related register(s) + 1: begin + `uvm_info(`gfn, $sformatf("Transaction-%0d: program register(s) to random value(s)", + tr_num), UVM_HIGH) + // First, stop driving gpio_i + undrive_gpio_in(); + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.direct_out) + csr_update(ral.direct_out); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.direct_oe) + csr_update(ral.direct_oe); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.masked_out_lower) + csr_update(ral.masked_out_lower); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.masked_oe_lower) + csr_update(ral.masked_oe_lower); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.masked_out_upper) + csr_update(ral.masked_out_upper); + end + + if ($urandom_range(0, 1)) begin + `DV_CHECK_RANDOMIZE_FATAL(ral.masked_oe_upper) + csr_update(ral.masked_oe_upper); + end + end + endcase + `uvm_info(`gfn, $sformatf("End of Transaction-%0d", tr_num), UVM_HIGH) + + end // end for + + endtask : body + +endclass : gpio_random_dout_din_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv new file mode 100644 index 00000000000..c9a2864ad85 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_random_long_reg_writes_reg_reads_vseq.sv @@ -0,0 +1,187 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// class : gpio_random_long_reg_writes_reg_reads_vseq +// This gpio random test sequence performs random no. of iteration such that +// each iteration will do either of the following operations: +// (i) drives random gpio input data values +// (ii) writes any of gpio registers except for CTRL_EN_INPUT_FILTER register +// (iii) reads any of gpio registers +class gpio_random_long_reg_writes_reg_reads_vseq extends gpio_base_vseq; + + `uvm_object_utils(gpio_random_long_reg_writes_reg_reads_vseq) + `uvm_object_new + + task body(); + // gpio pins_if pins_o value to drive + bit [NUM_GPIOS-1:0] gpio_i; + // gpio pins_if pins_oe value to drive + bit [NUM_GPIOS-1:0] gpio_i_oen; + `uvm_info(`gfn, $sformatf("num_trans = %0d", num_trans), UVM_HIGH) + + // Wait for minimum 1 clock cycle initially to avoid reading of data_in + // immediately as the first iteration after reset, while data_in prediction + // is still being processed + cfg.clk_rst_vif.wait_clks_or_rst(1); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + + for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin + string msg_id = {`gfn, $sformatf(" Transaction-%0d", tr_num)}; + uint num_reg_op; + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(delay) + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(num_reg_op, num_reg_op inside {[25:50]};) + + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + + randcase + // drive new gpio data in + 1: begin + `DV_CHECK_STD_RANDOMIZE_FATAL(gpio_i) + `uvm_info(msg_id, $sformatf("drive random value 0x%0h on gpio_i", gpio_i), UVM_HIGH) + + // drive gpio_vif after setting all output enables to 0's + drive_gpio_in(gpio_i); + // Wait for one clock cycle for us to read data_in reg reliably + cfg.clk_rst_vif.wait_clks_or_rst(1); + end + // long reg write + 1: begin + undrive_gpio_in(); + repeat (num_reg_op) gpio_reg_wr(); + end + // long reg read + 1: begin + repeat (num_reg_op) gpio_reg_rd(); + end + endcase + + end // end for + + endtask : body + + // Task: gpio_reg_wr + task gpio_reg_wr(); + bit [NUM_GPIOS-1:0] csr_wr_value; + `DV_CHECK_STD_RANDOMIZE_FATAL(csr_wr_value) + + randcase + 1: begin + // Writing to DATA_IN reg + csr_wr(.ptr(ral.data_in), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.direct_out), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.masked_out_lower), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.masked_out_upper), .value(csr_wr_value)); + end + 1: begin + undrive_gpio_in(); + csr_wr(.ptr(ral.direct_oe), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.masked_oe_lower), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.masked_oe_upper), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.intr_enable), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.intr_test), .value(csr_wr_value)); + `uvm_info(`gfn, "Writing to intr_test", UVM_NONE) + end + 1: begin + csr_wr(.ptr(ral.intr_state), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.intr_ctrl_en_falling), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.intr_ctrl_en_rising), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.intr_ctrl_en_lvllow), .value(csr_wr_value)); + end + 1: begin + csr_wr(.ptr(ral.intr_ctrl_en_lvlhigh), .value(csr_wr_value)); + end + endcase + endtask : gpio_reg_wr + + // Task: gpio_reg_rd + task gpio_reg_rd(); + bit [TL_DW-1:0] csr_rd_value; + randcase + 5: begin + csr_rd(.ptr(ral.data_in), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading data_in", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.direct_out), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading direct_out", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.masked_out_lower), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading masked_out_lower", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.masked_out_upper), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading masked_out_upper", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.direct_oe), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading direct_oe", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.masked_oe_lower), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading masked_oe_lower", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.masked_oe_upper), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading masked_oe_upper", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.intr_enable), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading intr_enable", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.intr_test), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading intr_test", UVM_NONE) + end + 5: begin + csr_rd(.ptr(ral.intr_state), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading intr_state", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.intr_ctrl_en_falling), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading intr_ctrl_en_falling", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.intr_ctrl_en_rising), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading intr_ctrl_en_rising", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.intr_ctrl_en_lvllow), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading intr_ctrl_en_lvllow", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.intr_ctrl_en_lvlhigh), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading intr_ctrl_en_lvlhigh", UVM_HIGH) + end + 1: begin + csr_rd(.ptr(ral.ctrl_en_input_filter), .value(csr_rd_value)); + `uvm_info(`gfn, "Reading ctrl_en_input_filter", UVM_HIGH) + end + endcase + endtask : gpio_reg_rd + +endclass : gpio_random_long_reg_writes_reg_reads_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv new file mode 100644 index 00000000000..85da0257685 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_smoke_vseq.sv @@ -0,0 +1,81 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// class : gpio_smoke_vseq +// This is a smoke test sequence for gpio. +// This sequence does following: +// (i) drives random gpio input data with gpio outputs disabled +// (ii) programs random values of gpio output data and output enable +class gpio_smoke_vseq extends gpio_base_vseq; + `uvm_object_utils(gpio_smoke_vseq) + + // gpio input to drive + rand bit [NUM_GPIOS-1:0] gpio_i; + // gpio output to program in register + rand bit [NUM_GPIOS-1:0] gpio_o; + // gpio output enable to program in register + rand bit [NUM_GPIOS-1:0] gpio_oe; + + `uvm_object_new + + virtual task dut_init(string reset_kind = "HARD"); + // Continue using randomized value by default, unless plusarg + // no_pullup_pulldown is passed to have no pullup/pulldown + set_gpio_pulls(.pu(cfg.pullup_en), .pd(cfg.pulldown_en)); + super.dut_init(reset_kind); + endtask: dut_init + + task body(); + // test gpio inputs + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(num_trans) + `uvm_info(`gfn, $sformatf("No. of transactions (gpio_i) = %0d", num_trans), UVM_HIGH) + for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin + bit [TL_DW-1:0] csr_rd_val; + string msg_id = {`gfn, $sformatf(" Transaction-%0d: ", tr_num)}; + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_i) + cfg.gpio_vif.drive(gpio_i); +`ifdef GPIO_ASYNC_ON + // If the CDC synchronizer prims are instantiated, it takes 2-3 cycles longer for inputs + // to propagate to the register (2 for the sync flops and 0-1 for CDC randomization). + `DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(delay, delay >= 1 + 3;) +`else + // Wait at least one clock cycle + `DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(delay, delay >= 1;) +`endif + + cfg.clk_rst_vif.wait_clks_or_rst(delay); + // Skip if a reset is ongoing... + if (!cfg.clk_rst_vif.rst_n) return; + + // Reading data_in will trigger a check inside scoreboard + csr_rd(.ptr(ral.data_in), .value(csr_rd_val)); + `uvm_info(msg_id, {$sformatf("reading data_in after %0d clock cycles ", delay), + $sformatf("csr_rd_val = %0h", csr_rd_val)}, UVM_HIGH) + end + + // test gpio outputs + cfg.gpio_vif.drive_en('0); + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(num_trans) + `uvm_info(`gfn, $sformatf("No. of transactions (gpio_o) = %0d", num_trans), UVM_HIGH) + for (uint tr_num = 0; tr_num < num_trans; tr_num++) begin + logic [NUM_GPIOS-1:0] exp_gpio_o; + logic [NUM_GPIOS-1:0] obs_gpio_o; + string msg_id = {`gfn, $sformatf(" Transaction-%0d: ", tr_num)}; + + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_o) + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(gpio_oe) + `uvm_info(msg_id, $sformatf("writing direct_out = 0x%0h [%0b] direct_oe = 0x%0h [%0b]", + gpio_o, gpio_o, gpio_oe, gpio_oe), UVM_HIGH) + ral.direct_out.set(gpio_o); + ral.direct_oe.set(gpio_oe); + csr_update(.csr(ral.direct_out)); + csr_update(.csr(ral.direct_oe)); + // Wait at least one clock cycle + `DV_CHECK_MEMBER_RANDOMIZE_WITH_FATAL(delay, delay >= 1;) + `uvm_info(msg_id, $sformatf("waiting for %0d clock cycles", delay), UVM_HIGH) + cfg.clk_rst_vif.wait_clks_or_rst(delay); + end + endtask : body + +endclass : gpio_smoke_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_stress_all_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_stress_all_vseq.sv new file mode 100644 index 00000000000..aa80dcd011a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_stress_all_vseq.sv @@ -0,0 +1,45 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all gpio seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +// 2. gpio_cfg_update_on_fly, which requires zero_delays as it's very timing sensitive +class gpio_stress_all_vseq extends gpio_base_vseq; + `uvm_object_utils(gpio_stress_all_vseq) + + `uvm_object_new + + task body(); + string seq_names[] = {"gpio_smoke_vseq", + // "gpio_common_vseq", + // does not support intr_test as plus_arg disable do_clear_all_interrupts + "gpio_random_dout_din_vseq", + "gpio_dout_din_regs_random_rw_vseq", + "gpio_intr_rand_pgm_vseq", + "gpio_rand_intr_trigger_vseq", + "gpio_random_long_reg_writes_reg_reads_vseq", + "gpio_rand_straps_vseq"}; + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + gpio_base_vseq gpio_vseq; + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(gpio_vseq, seq) + + // hard_reset in dut_init can be skipped + if (do_apply_reset) gpio_vseq.do_init_reset = $urandom_range(0, 1); + else gpio_vseq.do_init_reset = 0; + + gpio_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(gpio_vseq) + `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, gpio_vseq.get_name()), + UVM_HIGH) + + gpio_vseq.start(p_sequencer); + `uvm_info(`gfn, $sformatf("End of sequence %0s with seq_idx = %0d", gpio_vseq.get_name(), + seq_idx), UVM_HIGH) + end + endtask : body +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_vseq_list.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_vseq_list.sv new file mode 100644 index 00000000000..e70e0e685f4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/env/seq_lib/gpio_vseq_list.sv @@ -0,0 +1,18 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "gpio_base_vseq.sv" +`include "gpio_smoke_vseq.sv" +`include "gpio_inp_prd_cnt_vseq.sv" +`include "gpio_common_vseq.sv" +`include "gpio_random_dout_din_vseq.sv" +`include "gpio_dout_din_regs_random_rw_vseq.sv" +`include "gpio_intr_rand_pgm_vseq.sv" +`include "gpio_rand_intr_trigger_vseq.sv" +`include "gpio_intr_with_filter_rand_intr_event_vseq.sv" +`include "gpio_filter_stress_vseq.sv" +`include "gpio_random_long_reg_writes_reg_reads_vseq.sv" +`include "gpio_full_random_vseq.sv" +`include "gpio_stress_all_vseq.sv" +`include "gpio_rand_straps_vseq.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/gpio_sim.core b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/gpio_sim.core new file mode 100644 index 00000000000..49214d5f163 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/gpio_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:gpio_sim:0.1 +description: "GPIO DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:gpio:0.1 + + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:gpio_test + - lowrisc:darjeeling_no_ibex_dv:gpio_sva + - lowrisc:darjeeling_no_ibex_dv:gpio_if + files: + - tb/tb.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/gpio_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/gpio_sim_cfg.hjson new file mode 100644 index 00000000000..fcd1a1676a5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/gpio_sim_cfg.hjson @@ -0,0 +1,202 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: gpio + + // Top level dut name (sv module). + dut: gpio + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_dv:gpio_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/gpio_testplan.hjson" + + // RAL spec - used to generate the RAL model. + ral_spec: "{self_dir}/../data/gpio.hjson" + + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] + + // Add additional tops for simulation. + sim_tops: ["gpio_bind", "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: gpio_base_test + uvm_test_seq: gpio_base_vseq + + // Add GPIO specific exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov/gpio_cov_excl.el"] + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // Add a second build mode to test the input synchronizers. + // Note that since the scoreboard has a cycle accurate model + // for GPIO without the synchronizers, the majority of the tests + // is run in the default build mode without the CDC prims. The en_cdc_prims + // build mode is used to run some additional smoke checks to ensure + // that the input paths through the CDC prims are connected correctly. + build_modes: [ + { + name: en_cdc_prims + build_opts: ["+define+GPIO_ASYNC_ON"] + } + ] + + en_cdc_prims_vcs_cov_cfg_file: "{default_vcs_cov_cfg_file}" + en_cdc_prims_xcelium_cov_cfg_file: "{default_xcelium_cov_cfg_file}" + + // List of test specifications. + tests: [ + { + name: gpio_smoke + uvm_test_seq: gpio_smoke_vseq + } + + { + name: gpio_smoke_no_pullup_pulldown + uvm_test_seq: gpio_smoke_vseq + run_opts: ["+no_pullup_pulldown=1"] + } + + { + name: gpio_inp_prd_cnt + uvm_test_seq: gpio_inp_prd_cnt_vseq + } + + { + name: gpio_random_dout_din + uvm_test_seq: gpio_random_dout_din_vseq + } + + { + name: gpio_random_dout_din_no_pullup_pulldown + uvm_test_seq: gpio_random_dout_din_vseq + run_opts: ["+no_pullup_pulldown=1"] + } + + { + name: gpio_dout_din_regs_random_rw + uvm_test_seq: gpio_dout_din_regs_random_rw_vseq + } + + { + name: gpio_intr_rand_pgm + uvm_test_seq: gpio_intr_rand_pgm_vseq + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_rand_intr_trigger + uvm_test_seq: gpio_rand_intr_trigger_vseq + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_intr_with_filter_rand_intr_event + uvm_test_seq: gpio_intr_with_filter_rand_intr_event_vseq + run_opts: ["+en_scb=0", "+zero_delays=1", "+do_clear_all_interrupts=0"] + } + + { + name: gpio_filter_stress + uvm_test_seq: gpio_filter_stress_vseq + run_opts: ["+en_scb=0", "+do_clear_all_interrupts=0"] + } + + { + name: gpio_random_long_reg_writes_reg_reads + uvm_test_seq: gpio_random_long_reg_writes_reg_reads_vseq + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_full_random + uvm_test_seq: gpio_full_random_vseq + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_stress_all + uvm_test_seq: gpio_stress_all_vseq + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_stress_all_with_rand_reset + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_csr_rw + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_same_csr_outstanding + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_csr_aliasing + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_csr_mem_rw_with_rand_reset + run_opts: ["+do_clear_all_interrupts=0"] + } + + { + name: gpio_tl_intg_err + run_opts: ["+do_clear_all_interrupts=0"] + } + + // Additional smoke checks for second build mode + { + name: gpio_smoke_en_cdc_prim + uvm_test_seq: gpio_smoke_vseq + build_mode: en_cdc_prims + } + + { + name: gpio_smoke_no_pullup_pulldown_en_cdc_prim + uvm_test_seq: gpio_smoke_vseq + build_mode: en_cdc_prims + run_opts: ["+no_pullup_pulldown=1"] + } + { + name: gpio_rand_straps + uvm_test_seq: gpio_rand_straps_vseq + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["gpio_smoke", "gpio_smoke_en_cdc_prim"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/interfaces/gpio_if.core b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/interfaces/gpio_if.core new file mode 100644 index 00000000000..9dff4fc67b5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/interfaces/gpio_if.core @@ -0,0 +1,18 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:gpio_if:0.1 +description: "GPIO Interfaces" +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_ip:gpio:0.1 + files: + - gpio_straps_if.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/interfaces/gpio_straps_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/interfaces/gpio_straps_if.sv new file mode 100644 index 00000000000..38a219b460b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/interfaces/gpio_straps_if.sv @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// interface : gpio_straps_if +`ifndef GPIO_STRAPS_IF_SV +`define GPIO_STRAPS_IF_SV + +import gpio_pkg::*; + +// Interface definition +interface gpio_straps_if(input logic clk, input logic rst_n); + + logic strap_en; // Signal to enable straps + gpio_straps_t sampled_straps; // Sampled gpio_i snapshot data from GPIO (DUT) + + modport dut_port(input strap_en, output sampled_straps); + modport tb_port(output strap_en, input sampled_straps); + +endinterface + +`endif // GPIO_STRAPS_IF_SV diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/sva/gpio_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/sva/gpio_bind.sv new file mode 100644 index 00000000000..7920e6dc2a1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/sva/gpio_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module gpio_bind; + + bind gpio tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind gpio gpio_csr_assert_fpv gpio_csr_assert ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/sva/gpio_sva.core b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/sva/gpio_sva.core new file mode 100644 index 00000000000..c45b72610d3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/sva/gpio_sva.core @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:gpio_sva:0.1 +description: "GPIO assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - gpio_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:darjeeling_no_ibex_ip:gpio:0.1 + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/gpio.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: gpio diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tb/tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tb/tb.sv new file mode 100644 index 00000000000..db15a8b8a6d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tb/tb.sv @@ -0,0 +1,100 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import tl_agent_pkg::*; + import gpio_env_pkg::*; + import gpio_test_pkg::*; + import gpio_reg_pkg::*; + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n; + wire [NUM_GPIOS-1:0] gpio_pins; + wire [NUM_GPIOS-1:0] gpio_i; + wire [NUM_GPIOS-1:0] gpio_o; + wire [NUM_GPIOS-1:0] gpio_oe; + wire [NUM_GPIOS-1:0] gpio_intr; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + gpio_straps_t sampled_straps; + wire strap_en; + + `DV_ALERT_IF_CONNECT() + + // interfaces + clk_rst_if clk_rst_if ( + .clk (clk), + .rst_n(rst_n) + ); + pins_if #(NUM_MAX_INTERRUPTS) intr_if (.pins(interrupts)); + gpio_straps_if straps_if_inst ( + .clk (clk), + .rst_n(rst_n) + ); + tl_if tl_if ( + .clk (clk), + .rst_n(rst_n) + ); + pins_if #(NUM_GPIOS) gpio_if (.pins(gpio_pins)); + + // dut + gpio #( + // We have two build modes in this testbench: one with CDC synchronizers enabled, and one + // where they are disabled. +`ifdef GPIO_ASYNC_ON + .GpioAsyncOn(1) +`else + .GpioAsyncOn(0) +`endif + ) dut ( + .clk_i (clk), + .rst_ni(rst_n), + + .strap_en_i(straps_if_inst.strap_en), + .sampled_straps_o(straps_if_inst.sampled_straps), + + .tl_i(tl_if.h2d), + .tl_o(tl_if.d2h), + + .intr_gpio_o(gpio_intr), + + .alert_rx_i(alert_rx), + .alert_tx_o(alert_tx), + + // RACL interface + .racl_policies_i('0), + .racl_error_o ( ), + + .cio_gpio_i (gpio_i), + .cio_gpio_o (gpio_o), + .cio_gpio_en_o (gpio_oe) + ); + + assign interrupts[NUM_GPIOS-1:0] = gpio_intr; + + // gpio pins are represented by bi-directional gpio_if interface + // drive the pins only if en_o bit from the dut is high + assign gpio_i = gpio_pins[NUM_GPIOS-1:0]; + for (genvar i = 0; i < NUM_GPIOS; i++) begin : gen_each_gpio + assign gpio_pins[i] = gpio_oe[i] ? gpio_o[i] : 1'bz; + end : gen_each_gpio + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + uvm_config_db#(virtual pins_if #(NUM_GPIOS))::set(null, "*.env", "gpio_vif", gpio_if); + uvm_config_db#(virtual gpio_straps_if)::set(null, "*.*", "straps_vif", straps_if_inst); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tests/gpio_base_test.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tests/gpio_base_test.sv new file mode 100644 index 00000000000..84116f8b57e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tests/gpio_base_test.sv @@ -0,0 +1,29 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +class gpio_base_test extends cip_base_test #( + .ENV_T(gpio_env), + .CFG_T(gpio_env_cfg) +); + `uvm_component_utils(gpio_base_test) + + straps_vif straps_vif_inst; // Virtual interface + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + task reset_phase(uvm_phase phase); + phase.raise_objection(this); + // Initialize inputs + straps_vif_inst.tb_port.strap_en = 0; + phase.drop_objection(this); + endtask + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + if (!uvm_config_db#(straps_vif)::get(this, "*.*", "straps_vif", straps_vif_inst)) begin + `uvm_fatal("SEQ", "Virtual interface straps_vif_inst is not set") + end + endfunction : build_phase +endclass : gpio_base_test diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tests/gpio_test.core b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tests/gpio_test.core new file mode 100644 index 00000000000..5351b5de8d7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tests/gpio_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:gpio_test:0.1 +description: "GPIO DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:gpio_env:0.1 + files: + - gpio_test_pkg.sv + - gpio_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tests/gpio_test_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tests/gpio_test_pkg.sv new file mode 100644 index 00000000000..437a9cd4109 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/dv/tests/gpio_test_pkg.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package gpio_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import gpio_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + + // local types + + // functions + + // package sources + `include "gpio_base_test.sv" +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/gpio.core b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/gpio.core new file mode 100644 index 00000000000..fa69e6b902f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/gpio.core @@ -0,0 +1,67 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:gpio:0.1 +description: "gpio" +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:all + files: + - rtl/gpio_pkg.sv + - rtl/gpio_reg_pkg.sv + - rtl/gpio_reg_top.sv + - rtl/gpio.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/gpio.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/gpio.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: gpio + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/lint/gpio.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/lint/gpio.vlt new file mode 100644 index 00000000000..12ff241a8d4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/lint/gpio.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for gpio diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/lint/gpio.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/lint/gpio.waiver new file mode 100644 index 00000000000..38220684482 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/lint/gpio.waiver @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for GPIO lint + +waive -rules HIER_NET_NOT_READ -location {gpio.sv} -regexp {[nN]et.*a_(address|param|user).*not read from} -comment "several TLUL signals are not used by register file" +waive -rules HIER_NET_NOT_READ -location {gpio.sv} -regexp {Net .reg2hw.*.qe. is not read from} -comment "registers with multiple fields often have unused qe's since they are duplicative" +waive -rules NOT_READ -location {gpio.sv} -regexp {Signal 'reg2hw.*.qe' is not read from} -comment "registers with multiple fields often have unused qe's since they are duplicative" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio.sv new file mode 100644 index 00000000000..9cccabedea9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio.sv @@ -0,0 +1,423 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// General Purpose Input/Output module + +`include "prim_assert.sv" + +module gpio + import gpio_pkg::*; + import gpio_reg_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert signal + parameter int unsigned AlertSkewCycles = 1, + parameter bit GpioAsHwStrapsEn = 1, + // This parameter instantiates 2-stage synchronizers on all GPIO inputs. + parameter bit GpioAsyncOn = 1, + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[NumRegs] = '{NumRegs{0}} +) ( + input clk_i, + input rst_ni, + + // Strap sampling trigger and broadcast output + input strap_en_i, + output gpio_straps_t sampled_straps_o, + + // Bus interface + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Interrupts + output logic [NumIOs-1:0] intr_gpio_o, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output top_racl_pkg::racl_error_log_t racl_error_o, + + // GPIOs + input [NumIOs-1:0] cio_gpio_i, + output logic [NumIOs-1:0] cio_gpio_o, + output logic [NumIOs-1:0] cio_gpio_en_o +); + localparam int unsigned IOWidth = prim_util_pkg::vbits(NumIOs); + + gpio_reg2hw_t reg2hw; + gpio_hw2reg_t hw2reg; + + logic [NumIOs-1:0] cio_gpio_q; + logic [NumIOs-1:0] cio_gpio_en_q; + + // possibly filter the input based upon register configuration + logic [NumIOs-1:0] data_in_d; + localparam int unsigned CntWidth = 4; + for (genvar i = 0 ; i < NumIOs ; i++) begin : gen_filter + prim_filter_ctr #( + .AsyncOn(GpioAsyncOn), + .CntWidth(CntWidth) + ) u_filter ( + .clk_i, + .rst_ni, + .enable_i(reg2hw.ctrl_en_input_filter.q[i]), + .filter_i(cio_gpio_i[i]), + .thresh_i({CntWidth{1'b1}}), + .filter_o(data_in_d[i]) + ); + end + + // Detect rising and falling edges. + logic [NumIOs-1:0] data_in_q, event_rise, event_fall; + always_ff @(posedge clk_i) begin + data_in_q <= data_in_d; + end + assign event_rise = data_in_d & ~data_in_q; + assign event_fall = ~data_in_d & data_in_q; + + // Input period counters + logic [NumInpPeriodCounters-1:0] inp_prd_cnt_clr, inp_prd_cnt_inc; + logic [NumInpPeriodCounters-1:0][31:0] inp_prd_cnt_d, inp_prd_cnt_q; + logic [NumInpPeriodCounters-1:0][7:0] prescaler_cnt_d, prescaler_cnt_q; + logic [NumInpPeriodCounters-1:0] prescaler_cnt_reached, relevant_edge, relevant_edge_clr; + logic [NumInpPeriodCounters-1:0] relevant_edge_d, relevant_edge_q; + typedef enum logic [1:0] { + InpPrdCntDisabled, + InpPrdCntPreOpeningEdge, + InpPrdCntPreClosingEdge + } inp_prd_cnt_state_e; + inp_prd_cnt_state_e [NumInpPeriodCounters-1:0] inp_prd_cnt_state_d, inp_prd_cnt_state_q; + + logic [NumInpPeriodCounters-1:0] unused_input_select; + for (genvar i = 0; i < NumInpPeriodCounters; i++) begin : gen_inp_prd_cnt + + // Determine when the prescaler counter reaches the prescaler threshold. + assign prescaler_cnt_reached[i] = + (prescaler_cnt_q[i] == reg2hw.inp_prd_cnt_ctrl[i].prescaler.q) & + reg2hw.inp_prd_cnt_ctrl[i].enable.q; + + always_comb begin + prescaler_cnt_d[i] = prescaler_cnt_q[i]; + + if (!reg2hw.inp_prd_cnt_ctrl[i].enable.q) begin + // Clear the prescaler counter when the input period counter is disabled. + prescaler_cnt_d[i] = '0; + end else begin + // When the input period counter is enabled .. + if (prescaler_cnt_reached[i]) begin + // .. and the prescaler counter has reached its threshold, clear it, .. + prescaler_cnt_d[i] = '0; + end else begin + // .. otherwise increment it. + prescaler_cnt_d[i] = prescaler_cnt_q[i] + 8'd1; + end + end + end + + // Detect relevant edges. + assign relevant_edge[i] = reg2hw.inp_prd_cnt_ctrl[i].polarity.q ? + // Rising edge + event_rise[reg2hw.inp_prd_cnt_ctrl[i].input_select.q[IOWidth-1:0]] : + // Falling edge + event_fall[reg2hw.inp_prd_cnt_ctrl[i].input_select.q[IOWidth-1:0]]; + + assign unused_input_select[i] = ^reg2hw.inp_prd_cnt_ctrl[i].input_select.q[7:IOWidth]; + + // Flop relevant edges until the prescaler counter reaches its threshold. + always_comb begin + // Hold by default + relevant_edge_d[i] = relevant_edge_q[i]; + + // Detected relevant edges take precedence. + if (relevant_edge[i]) begin + relevant_edge_d[i] = 1'b1; + end else if (relevant_edge_clr[i]) begin + // Clear flopped relevant edge when it was consumed by the FSM. + relevant_edge_d[i] = 1'b0; + end + end + + // Combinational logic of input period counter. + always_comb begin + // Hold by default + inp_prd_cnt_d[i] = inp_prd_cnt_q[i]; + + // Clearing takes precendence + if (inp_prd_cnt_clr[i]) begin + inp_prd_cnt_d[i] = '0; + end else if (inp_prd_cnt_inc[i] && inp_prd_cnt_q[i] != '1) begin + // Increment if the counter hasn't reached its maximum value yet. + inp_prd_cnt_d[i] = inp_prd_cnt_q[i] + 32'd1; + end + end + + // Simple FSM controlling the input period counter. + always_comb begin + hw2reg.inp_prd_cnt_ctrl[i].enable.de = 1'b0; + hw2reg.inp_prd_cnt_val[i].de = 1'b0; + inp_prd_cnt_clr[i] = 1'b0; + inp_prd_cnt_inc[i] = 1'b0; + inp_prd_cnt_state_d[i] = inp_prd_cnt_state_q[i]; + relevant_edge_clr[i] = 1'b0; + + unique case (inp_prd_cnt_state_q[i]) + InpPrdCntDisabled: begin + if (reg2hw.inp_prd_cnt_ctrl[i].enable.q) begin + // When the input period counter gets enabled, clear the counter and wait for the + // opening edge. + inp_prd_cnt_clr[i] = 1'b1; + inp_prd_cnt_state_d[i] = InpPrdCntPreOpeningEdge; + end + end + + InpPrdCntPreOpeningEdge: begin + // Wait for the opening edge. + if (relevant_edge_q[i]) begin + // Clear the relevant edge and switch to waiting for the closing edge. + relevant_edge_clr[i] = 1'b1; + inp_prd_cnt_state_d[i] = InpPrdCntPreClosingEdge; + end + end + + InpPrdCntPreClosingEdge: begin + if (prescaler_cnt_reached[i]) begin + // Increment the counter while waiting for the closing edge. + inp_prd_cnt_inc[i] = 1'b1; + if (relevant_edge_q[i]) begin + // Clear the relevant edge. + relevant_edge_clr[i] = 1'b1; + // Update the value register of this input period counter. + hw2reg.inp_prd_cnt_val[i].de = 1'b1; + // Clear the counter. + inp_prd_cnt_clr[i] = 1'b1; + // If continuous mode is not enabled, clear the enable bit and go back to the disabled + // state. + if (!reg2hw.inp_prd_cnt_ctrl[i].continuous_mode.q) begin + hw2reg.inp_prd_cnt_ctrl[i].enable.de = 1'b1; + inp_prd_cnt_state_d[i] = InpPrdCntDisabled; + end + // Else, (i.e., if continuous mode is enabled), implicitly don't clear the enable bit + // and keep waiting for the next closing edge. + end + end + end + + default: inp_prd_cnt_state_d[i] = InpPrdCntDisabled; + endcase + + // When the input period counter is not enabled, clear the counter and the relevant edge flop, + // and go back to the disabled state. + if (!reg2hw.inp_prd_cnt_ctrl[i].enable.q) begin + inp_prd_cnt_clr[i] = 1'b1; + relevant_edge_clr[i] = 1'b1; + inp_prd_cnt_state_d[i] = InpPrdCntDisabled; + end + end + + // When the SW-visible register gets updated, write the counter value (with saturation). + assign hw2reg.inp_prd_cnt_val[i].d = inp_prd_cnt_q[i]; + + // HW only ever clears the enable bit in the enable bit of the control register (in the FSM + // above), it never writes any of the other bits. + assign hw2reg.inp_prd_cnt_ctrl[i].enable.d = 1'b0; + assign hw2reg.inp_prd_cnt_ctrl[i].continuous_mode.d = 1'b0; + assign hw2reg.inp_prd_cnt_ctrl[i].continuous_mode.de = 1'b0; + assign hw2reg.inp_prd_cnt_ctrl[i].polarity.d = 1'b0; + assign hw2reg.inp_prd_cnt_ctrl[i].polarity.de = 1'b0; + assign hw2reg.inp_prd_cnt_ctrl[i].input_select.d = '0; + assign hw2reg.inp_prd_cnt_ctrl[i].input_select.de = 1'b0; + assign hw2reg.inp_prd_cnt_ctrl[i].prescaler.d = '0; + assign hw2reg.inp_prd_cnt_ctrl[i].prescaler.de = 1'b0; + + // Flops for each input period counter. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + inp_prd_cnt_q[i] <= '0; + inp_prd_cnt_state_q[i] <= InpPrdCntDisabled; + prescaler_cnt_q[i] <= '0; + relevant_edge_q[i] <= 1'b0; + end else begin + inp_prd_cnt_q[i] <= inp_prd_cnt_d[i]; + inp_prd_cnt_state_q[i] <= inp_prd_cnt_state_d[i]; + prescaler_cnt_q[i] <= prescaler_cnt_d[i]; + relevant_edge_q[i] <= relevant_edge_d[i]; + end + end + end + + if (GpioAsHwStrapsEn) begin : gen_strap_sample + // sample at gpio inputs at strap_en_i signal pulse. + logic strap_en; + + // The strap_en_i is a single cycle pulse generated by the pwrmgr + // Both sender (pwrmgr) and receiver (gpio controller) are in the same clock domain (io_div4) + // A cdc synchronizer is not required + // + assign strap_en = strap_en_i; + + // we guarantee here by design that this will always be done exactly once per reset cycle. + logic sample_trigger; + assign sample_trigger = strap_en && !reg2hw.hw_straps_data_in_valid.q; + assign hw2reg.hw_straps_data_in_valid.de = sample_trigger; + assign hw2reg.hw_straps_data_in_valid.d = 1'b1; + assign hw2reg.hw_straps_data_in.de = sample_trigger; + assign hw2reg.hw_straps_data_in.d = data_in_d; + assign sampled_straps_o.data = reg2hw.hw_straps_data_in.q; + assign sampled_straps_o.valid = reg2hw.hw_straps_data_in_valid.q; + end else begin : gen_no_strap_sample + assign hw2reg.hw_straps_data_in_valid.de = 1'b0; + assign hw2reg.hw_straps_data_in_valid.d = 1'b0; + assign hw2reg.hw_straps_data_in.de = 1'b0; + assign hw2reg.hw_straps_data_in.d = '0; + assign sampled_straps_o.data = '0; + assign sampled_straps_o.valid = 1'b0; + + logic unused_signals; + assign unused_signals = ^{strap_en_i, + reg2hw.hw_straps_data_in.q, + reg2hw.hw_straps_data_in_valid.q}; + end + + // GPIO_IN + assign hw2reg.data_in.de = 1'b1; + assign hw2reg.data_in.d = data_in_d; + + // GPIO_OUT + assign cio_gpio_o = cio_gpio_q; + assign cio_gpio_en_o = cio_gpio_en_q; + + assign hw2reg.direct_out.d = cio_gpio_q; + assign hw2reg.masked_out_upper.data.d = cio_gpio_q[NumIOs-1:16]; + assign hw2reg.masked_out_upper.mask.d = 16'h 0; + assign hw2reg.masked_out_lower.data.d = cio_gpio_q[15:0]; + assign hw2reg.masked_out_lower.mask.d = 16'h 0; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cio_gpio_q <= '0; + end else if (reg2hw.direct_out.qe) begin + cio_gpio_q <= reg2hw.direct_out.q; + end else if (reg2hw.masked_out_upper.data.qe) begin + cio_gpio_q[NumIOs-1:16] <= + ( reg2hw.masked_out_upper.mask.q & reg2hw.masked_out_upper.data.q) | + (~reg2hw.masked_out_upper.mask.q & cio_gpio_q[NumIOs-1:16]); + end else if (reg2hw.masked_out_lower.data.qe) begin + cio_gpio_q[15:0] <= + ( reg2hw.masked_out_lower.mask.q & reg2hw.masked_out_lower.data.q) | + (~reg2hw.masked_out_lower.mask.q & cio_gpio_q[15:0]); + end + end + + // GPIO OE + assign hw2reg.direct_oe.d = cio_gpio_en_q; + assign hw2reg.masked_oe_upper.data.d = cio_gpio_en_q[NumIOs-1:16]; + assign hw2reg.masked_oe_upper.mask.d = 16'h 0; + assign hw2reg.masked_oe_lower.data.d = cio_gpio_en_q[15:0]; + assign hw2reg.masked_oe_lower.mask.d = 16'h 0; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cio_gpio_en_q <= '0; + end else if (reg2hw.direct_oe.qe) begin + cio_gpio_en_q <= reg2hw.direct_oe.q; + end else if (reg2hw.masked_oe_upper.data.qe) begin + cio_gpio_en_q[NumIOs-1:16] <= + ( reg2hw.masked_oe_upper.mask.q & reg2hw.masked_oe_upper.data.q) | + (~reg2hw.masked_oe_upper.mask.q & cio_gpio_en_q[NumIOs-1:16]); + end else if (reg2hw.masked_oe_lower.data.qe) begin + cio_gpio_en_q[15:0] <= + ( reg2hw.masked_oe_lower.mask.q & reg2hw.masked_oe_lower.data.q) | + (~reg2hw.masked_oe_lower.mask.q & cio_gpio_en_q[15:0]); + end + end + + logic [NumIOs-1:0] event_intr_rise, event_intr_fall, event_intr_actlow, event_intr_acthigh; + logic [NumIOs-1:0] event_intr_combined; + + // instantiate interrupt hardware primitive + prim_intr_hw #(.Width(NumIOs)) intr_hw ( + .clk_i, + .rst_ni, + .event_intr_i (event_intr_combined), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.d), + .intr_o (intr_gpio_o) + ); + + // detect four possible individual interrupts + assign event_intr_rise = event_rise & reg2hw.intr_ctrl_en_rising.q; + assign event_intr_fall = event_fall & reg2hw.intr_ctrl_en_falling.q; + assign event_intr_acthigh = data_in_d & reg2hw.intr_ctrl_en_lvlhigh.q; + assign event_intr_actlow = ~data_in_d & reg2hw.intr_ctrl_en_lvllow.q; + + assign event_intr_combined = event_intr_rise | + event_intr_fall | + event_intr_actlow | + event_intr_acthigh; + + // Alerts + logic [NumAlerts-1:0] alert_test, alerts; + assign alert_test = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .SkewCycles(AlertSkewCycles), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[0] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + // Register module + gpio_reg_top #( + .EnableRacl(EnableRacl), + .RaclErrorRsp(RaclErrorRsp), + .RaclPolicySelVec(RaclPolicySelVec) + ) u_reg ( + .clk_i, + .rst_ni, + + .tl_i, + .tl_o, + + .reg2hw, + .hw2reg, + + .racl_policies_i, + .racl_error_o, + + // SEC_CM: BUS.INTEGRITY + .intg_err_o (alerts[0]) + ); + + // Assert Known: Outputs + `ASSERT_KNOWN(IntrGpioKnown, intr_gpio_o) + `ASSERT_KNOWN(CioGpioEnOKnown, cio_gpio_en_o) + `ASSERT_KNOWN(CioGpioOKnown, cio_gpio_o) + `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o) + `ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio_pkg.sv new file mode 100644 index 00000000000..61f9268ca50 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio_pkg.sv @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package gpio_pkg; + + typedef struct packed { + logic valid; + logic [31:0] data; + } gpio_straps_t; + +endpackage : gpio_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio_reg_pkg.sv new file mode 100644 index 00000000000..4a9d84f4aaa --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio_reg_pkg.sv @@ -0,0 +1,401 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package gpio_reg_pkg; + + // Param list + parameter int NumIOs = 32; + parameter int NumInpPeriodCounters = 8; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int BlockAw = 8; + + // Number of registers for every interface + parameter int NumRegs = 34; + + // Alert indices + typedef enum int { + AlertFatalFaultIdx = 0 + } gpio_alert_idx_t; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic [31:0] q; + } gpio_reg2hw_intr_state_reg_t; + + typedef struct packed { + logic [31:0] q; + } gpio_reg2hw_intr_enable_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } gpio_reg2hw_intr_test_reg_t; + + typedef struct packed { + logic q; + logic qe; + } gpio_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } gpio_reg2hw_direct_out_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + logic qe; + } mask; + struct packed { + logic [15:0] q; + logic qe; + } data; + } gpio_reg2hw_masked_out_lower_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + logic qe; + } mask; + struct packed { + logic [15:0] q; + logic qe; + } data; + } gpio_reg2hw_masked_out_upper_reg_t; + + typedef struct packed { + logic [31:0] q; + logic qe; + } gpio_reg2hw_direct_oe_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + logic qe; + } mask; + struct packed { + logic [15:0] q; + logic qe; + } data; + } gpio_reg2hw_masked_oe_lower_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + logic qe; + } mask; + struct packed { + logic [15:0] q; + logic qe; + } data; + } gpio_reg2hw_masked_oe_upper_reg_t; + + typedef struct packed { + logic [31:0] q; + } gpio_reg2hw_intr_ctrl_en_rising_reg_t; + + typedef struct packed { + logic [31:0] q; + } gpio_reg2hw_intr_ctrl_en_falling_reg_t; + + typedef struct packed { + logic [31:0] q; + } gpio_reg2hw_intr_ctrl_en_lvlhigh_reg_t; + + typedef struct packed { + logic [31:0] q; + } gpio_reg2hw_intr_ctrl_en_lvllow_reg_t; + + typedef struct packed { + logic [31:0] q; + } gpio_reg2hw_ctrl_en_input_filter_reg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_hw_straps_data_in_valid_reg_t; + + typedef struct packed { + logic [31:0] q; + } gpio_reg2hw_hw_straps_data_in_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] q; + } prescaler; + struct packed { + logic [7:0] q; + } input_select; + struct packed { + logic q; + } polarity; + struct packed { + logic q; + } continuous_mode; + struct packed { + logic q; + } enable; + } gpio_reg2hw_inp_prd_cnt_ctrl_mreg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } gpio_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } gpio_hw2reg_data_in_reg_t; + + typedef struct packed { + logic [31:0] d; + } gpio_hw2reg_direct_out_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] d; + } mask; + struct packed { + logic [15:0] d; + } data; + } gpio_hw2reg_masked_out_lower_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] d; + } mask; + struct packed { + logic [15:0] d; + } data; + } gpio_hw2reg_masked_out_upper_reg_t; + + typedef struct packed { + logic [31:0] d; + } gpio_hw2reg_direct_oe_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] d; + } mask; + struct packed { + logic [15:0] d; + } data; + } gpio_hw2reg_masked_oe_lower_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] d; + } mask; + struct packed { + logic [15:0] d; + } data; + } gpio_hw2reg_masked_oe_upper_reg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_hw_straps_data_in_valid_reg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } gpio_hw2reg_hw_straps_data_in_reg_t; + + typedef struct packed { + struct packed { + logic [7:0] d; + logic de; + } prescaler; + struct packed { + logic [7:0] d; + logic de; + } input_select; + struct packed { + logic d; + logic de; + } polarity; + struct packed { + logic d; + logic de; + } continuous_mode; + struct packed { + logic d; + logic de; + } enable; + } gpio_hw2reg_inp_prd_cnt_ctrl_mreg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } gpio_hw2reg_inp_prd_cnt_val_mreg_t; + + // Register -> HW type + typedef struct packed { + gpio_reg2hw_intr_state_reg_t intr_state; // [645:614] + gpio_reg2hw_intr_enable_reg_t intr_enable; // [613:582] + gpio_reg2hw_intr_test_reg_t intr_test; // [581:549] + gpio_reg2hw_alert_test_reg_t alert_test; // [548:547] + gpio_reg2hw_direct_out_reg_t direct_out; // [546:514] + gpio_reg2hw_masked_out_lower_reg_t masked_out_lower; // [513:480] + gpio_reg2hw_masked_out_upper_reg_t masked_out_upper; // [479:446] + gpio_reg2hw_direct_oe_reg_t direct_oe; // [445:413] + gpio_reg2hw_masked_oe_lower_reg_t masked_oe_lower; // [412:379] + gpio_reg2hw_masked_oe_upper_reg_t masked_oe_upper; // [378:345] + gpio_reg2hw_intr_ctrl_en_rising_reg_t intr_ctrl_en_rising; // [344:313] + gpio_reg2hw_intr_ctrl_en_falling_reg_t intr_ctrl_en_falling; // [312:281] + gpio_reg2hw_intr_ctrl_en_lvlhigh_reg_t intr_ctrl_en_lvlhigh; // [280:249] + gpio_reg2hw_intr_ctrl_en_lvllow_reg_t intr_ctrl_en_lvllow; // [248:217] + gpio_reg2hw_ctrl_en_input_filter_reg_t ctrl_en_input_filter; // [216:185] + gpio_reg2hw_hw_straps_data_in_valid_reg_t hw_straps_data_in_valid; // [184:184] + gpio_reg2hw_hw_straps_data_in_reg_t hw_straps_data_in; // [183:152] + gpio_reg2hw_inp_prd_cnt_ctrl_mreg_t [7:0] inp_prd_cnt_ctrl; // [151:0] + } gpio_reg2hw_t; + + // HW -> register type + typedef struct packed { + gpio_hw2reg_intr_state_reg_t intr_state; // [748:716] + gpio_hw2reg_data_in_reg_t data_in; // [715:683] + gpio_hw2reg_direct_out_reg_t direct_out; // [682:651] + gpio_hw2reg_masked_out_lower_reg_t masked_out_lower; // [650:619] + gpio_hw2reg_masked_out_upper_reg_t masked_out_upper; // [618:587] + gpio_hw2reg_direct_oe_reg_t direct_oe; // [586:555] + gpio_hw2reg_masked_oe_lower_reg_t masked_oe_lower; // [554:523] + gpio_hw2reg_masked_oe_upper_reg_t masked_oe_upper; // [522:491] + gpio_hw2reg_hw_straps_data_in_valid_reg_t hw_straps_data_in_valid; // [490:489] + gpio_hw2reg_hw_straps_data_in_reg_t hw_straps_data_in; // [488:456] + gpio_hw2reg_inp_prd_cnt_ctrl_mreg_t [7:0] inp_prd_cnt_ctrl; // [455:264] + gpio_hw2reg_inp_prd_cnt_val_mreg_t [7:0] inp_prd_cnt_val; // [263:0] + } gpio_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] GPIO_INTR_STATE_OFFSET = 8'h 0; + parameter logic [BlockAw-1:0] GPIO_INTR_ENABLE_OFFSET = 8'h 4; + parameter logic [BlockAw-1:0] GPIO_INTR_TEST_OFFSET = 8'h 8; + parameter logic [BlockAw-1:0] GPIO_ALERT_TEST_OFFSET = 8'h c; + parameter logic [BlockAw-1:0] GPIO_DATA_IN_OFFSET = 8'h 10; + parameter logic [BlockAw-1:0] GPIO_DIRECT_OUT_OFFSET = 8'h 14; + parameter logic [BlockAw-1:0] GPIO_MASKED_OUT_LOWER_OFFSET = 8'h 18; + parameter logic [BlockAw-1:0] GPIO_MASKED_OUT_UPPER_OFFSET = 8'h 1c; + parameter logic [BlockAw-1:0] GPIO_DIRECT_OE_OFFSET = 8'h 20; + parameter logic [BlockAw-1:0] GPIO_MASKED_OE_LOWER_OFFSET = 8'h 24; + parameter logic [BlockAw-1:0] GPIO_MASKED_OE_UPPER_OFFSET = 8'h 28; + parameter logic [BlockAw-1:0] GPIO_INTR_CTRL_EN_RISING_OFFSET = 8'h 2c; + parameter logic [BlockAw-1:0] GPIO_INTR_CTRL_EN_FALLING_OFFSET = 8'h 30; + parameter logic [BlockAw-1:0] GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET = 8'h 34; + parameter logic [BlockAw-1:0] GPIO_INTR_CTRL_EN_LVLLOW_OFFSET = 8'h 38; + parameter logic [BlockAw-1:0] GPIO_CTRL_EN_INPUT_FILTER_OFFSET = 8'h 3c; + parameter logic [BlockAw-1:0] GPIO_HW_STRAPS_DATA_IN_VALID_OFFSET = 8'h 40; + parameter logic [BlockAw-1:0] GPIO_HW_STRAPS_DATA_IN_OFFSET = 8'h 44; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_CTRL_0_OFFSET = 8'h 48; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_CTRL_1_OFFSET = 8'h 4c; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_CTRL_2_OFFSET = 8'h 50; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_CTRL_3_OFFSET = 8'h 54; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_CTRL_4_OFFSET = 8'h 58; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_CTRL_5_OFFSET = 8'h 5c; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_CTRL_6_OFFSET = 8'h 60; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_CTRL_7_OFFSET = 8'h 64; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_VAL_0_OFFSET = 8'h 68; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_VAL_1_OFFSET = 8'h 6c; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_VAL_2_OFFSET = 8'h 70; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_VAL_3_OFFSET = 8'h 74; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_VAL_4_OFFSET = 8'h 78; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_VAL_5_OFFSET = 8'h 7c; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_VAL_6_OFFSET = 8'h 80; + parameter logic [BlockAw-1:0] GPIO_INP_PRD_CNT_VAL_7_OFFSET = 8'h 84; + + // Reset values for hwext registers and their fields + parameter logic [31:0] GPIO_INTR_TEST_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_INTR_TEST_GPIO_RESVAL = 32'h 0; + parameter logic [0:0] GPIO_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] GPIO_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [31:0] GPIO_DIRECT_OUT_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_MASKED_OUT_LOWER_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_MASKED_OUT_UPPER_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_DIRECT_OE_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_MASKED_OE_LOWER_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_MASKED_OE_UPPER_RESVAL = 32'h 0; + + // Register index + typedef enum int { + GPIO_INTR_STATE, + GPIO_INTR_ENABLE, + GPIO_INTR_TEST, + GPIO_ALERT_TEST, + GPIO_DATA_IN, + GPIO_DIRECT_OUT, + GPIO_MASKED_OUT_LOWER, + GPIO_MASKED_OUT_UPPER, + GPIO_DIRECT_OE, + GPIO_MASKED_OE_LOWER, + GPIO_MASKED_OE_UPPER, + GPIO_INTR_CTRL_EN_RISING, + GPIO_INTR_CTRL_EN_FALLING, + GPIO_INTR_CTRL_EN_LVLHIGH, + GPIO_INTR_CTRL_EN_LVLLOW, + GPIO_CTRL_EN_INPUT_FILTER, + GPIO_HW_STRAPS_DATA_IN_VALID, + GPIO_HW_STRAPS_DATA_IN, + GPIO_INP_PRD_CNT_CTRL_0, + GPIO_INP_PRD_CNT_CTRL_1, + GPIO_INP_PRD_CNT_CTRL_2, + GPIO_INP_PRD_CNT_CTRL_3, + GPIO_INP_PRD_CNT_CTRL_4, + GPIO_INP_PRD_CNT_CTRL_5, + GPIO_INP_PRD_CNT_CTRL_6, + GPIO_INP_PRD_CNT_CTRL_7, + GPIO_INP_PRD_CNT_VAL_0, + GPIO_INP_PRD_CNT_VAL_1, + GPIO_INP_PRD_CNT_VAL_2, + GPIO_INP_PRD_CNT_VAL_3, + GPIO_INP_PRD_CNT_VAL_4, + GPIO_INP_PRD_CNT_VAL_5, + GPIO_INP_PRD_CNT_VAL_6, + GPIO_INP_PRD_CNT_VAL_7 + } gpio_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] GPIO_PERMIT [34] = '{ + 4'b 1111, // index[ 0] GPIO_INTR_STATE + 4'b 1111, // index[ 1] GPIO_INTR_ENABLE + 4'b 1111, // index[ 2] GPIO_INTR_TEST + 4'b 0001, // index[ 3] GPIO_ALERT_TEST + 4'b 1111, // index[ 4] GPIO_DATA_IN + 4'b 1111, // index[ 5] GPIO_DIRECT_OUT + 4'b 1111, // index[ 6] GPIO_MASKED_OUT_LOWER + 4'b 1111, // index[ 7] GPIO_MASKED_OUT_UPPER + 4'b 1111, // index[ 8] GPIO_DIRECT_OE + 4'b 1111, // index[ 9] GPIO_MASKED_OE_LOWER + 4'b 1111, // index[10] GPIO_MASKED_OE_UPPER + 4'b 1111, // index[11] GPIO_INTR_CTRL_EN_RISING + 4'b 1111, // index[12] GPIO_INTR_CTRL_EN_FALLING + 4'b 1111, // index[13] GPIO_INTR_CTRL_EN_LVLHIGH + 4'b 1111, // index[14] GPIO_INTR_CTRL_EN_LVLLOW + 4'b 1111, // index[15] GPIO_CTRL_EN_INPUT_FILTER + 4'b 0001, // index[16] GPIO_HW_STRAPS_DATA_IN_VALID + 4'b 1111, // index[17] GPIO_HW_STRAPS_DATA_IN + 4'b 0111, // index[18] GPIO_INP_PRD_CNT_CTRL_0 + 4'b 0111, // index[19] GPIO_INP_PRD_CNT_CTRL_1 + 4'b 0111, // index[20] GPIO_INP_PRD_CNT_CTRL_2 + 4'b 0111, // index[21] GPIO_INP_PRD_CNT_CTRL_3 + 4'b 0111, // index[22] GPIO_INP_PRD_CNT_CTRL_4 + 4'b 0111, // index[23] GPIO_INP_PRD_CNT_CTRL_5 + 4'b 0111, // index[24] GPIO_INP_PRD_CNT_CTRL_6 + 4'b 0111, // index[25] GPIO_INP_PRD_CNT_CTRL_7 + 4'b 1111, // index[26] GPIO_INP_PRD_CNT_VAL_0 + 4'b 1111, // index[27] GPIO_INP_PRD_CNT_VAL_1 + 4'b 1111, // index[28] GPIO_INP_PRD_CNT_VAL_2 + 4'b 1111, // index[29] GPIO_INP_PRD_CNT_VAL_3 + 4'b 1111, // index[30] GPIO_INP_PRD_CNT_VAL_4 + 4'b 1111, // index[31] GPIO_INP_PRD_CNT_VAL_5 + 4'b 1111, // index[32] GPIO_INP_PRD_CNT_VAL_6 + 4'b 1111 // index[33] GPIO_INP_PRD_CNT_VAL_7 + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio_reg_top.sv new file mode 100644 index 00000000000..0515fee8a72 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/gpio/rtl/gpio_reg_top.sv @@ -0,0 +1,2706 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module gpio_reg_top + # ( + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1, + parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[gpio_reg_pkg::NumRegs] = + '{gpio_reg_pkg::NumRegs{0}} + ) ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write + input gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read + + // RACL interface + input top_racl_pkg::racl_policy_vec_t racl_policies_i, + output top_racl_pkg::racl_error_log_t racl_error_o, + + // Integrity check errors + output logic intg_err_o +); + + import gpio_reg_pkg::* ; + + localparam int AW = 8; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [33:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(34) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + // Translate RACL error to TLUL error if enabled + .error_i (reg_error | (RaclErrorRsp & racl_error_o.valid)) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic [31:0] intr_state_qs; + logic [31:0] intr_state_wd; + logic intr_enable_we; + logic [31:0] intr_enable_qs; + logic [31:0] intr_enable_wd; + logic intr_test_we; + logic [31:0] intr_test_wd; + logic alert_test_we; + logic alert_test_wd; + logic [31:0] data_in_qs; + logic direct_out_re; + logic direct_out_we; + logic [31:0] direct_out_qs; + logic [31:0] direct_out_wd; + logic masked_out_lower_re; + logic masked_out_lower_we; + logic [15:0] masked_out_lower_data_qs; + logic [15:0] masked_out_lower_data_wd; + logic [15:0] masked_out_lower_mask_wd; + logic masked_out_upper_re; + logic masked_out_upper_we; + logic [15:0] masked_out_upper_data_qs; + logic [15:0] masked_out_upper_data_wd; + logic [15:0] masked_out_upper_mask_wd; + logic direct_oe_re; + logic direct_oe_we; + logic [31:0] direct_oe_qs; + logic [31:0] direct_oe_wd; + logic masked_oe_lower_re; + logic masked_oe_lower_we; + logic [15:0] masked_oe_lower_data_qs; + logic [15:0] masked_oe_lower_data_wd; + logic [15:0] masked_oe_lower_mask_qs; + logic [15:0] masked_oe_lower_mask_wd; + logic masked_oe_upper_re; + logic masked_oe_upper_we; + logic [15:0] masked_oe_upper_data_qs; + logic [15:0] masked_oe_upper_data_wd; + logic [15:0] masked_oe_upper_mask_qs; + logic [15:0] masked_oe_upper_mask_wd; + logic intr_ctrl_en_rising_we; + logic [31:0] intr_ctrl_en_rising_qs; + logic [31:0] intr_ctrl_en_rising_wd; + logic intr_ctrl_en_falling_we; + logic [31:0] intr_ctrl_en_falling_qs; + logic [31:0] intr_ctrl_en_falling_wd; + logic intr_ctrl_en_lvlhigh_we; + logic [31:0] intr_ctrl_en_lvlhigh_qs; + logic [31:0] intr_ctrl_en_lvlhigh_wd; + logic intr_ctrl_en_lvllow_we; + logic [31:0] intr_ctrl_en_lvllow_qs; + logic [31:0] intr_ctrl_en_lvllow_wd; + logic ctrl_en_input_filter_we; + logic [31:0] ctrl_en_input_filter_qs; + logic [31:0] ctrl_en_input_filter_wd; + logic hw_straps_data_in_valid_qs; + logic [31:0] hw_straps_data_in_qs; + logic inp_prd_cnt_ctrl_0_we; + logic inp_prd_cnt_ctrl_0_enable_0_qs; + logic inp_prd_cnt_ctrl_0_enable_0_wd; + logic inp_prd_cnt_ctrl_0_continuous_mode_0_qs; + logic inp_prd_cnt_ctrl_0_continuous_mode_0_wd; + logic inp_prd_cnt_ctrl_0_polarity_0_qs; + logic inp_prd_cnt_ctrl_0_polarity_0_wd; + logic [7:0] inp_prd_cnt_ctrl_0_input_select_0_qs; + logic [7:0] inp_prd_cnt_ctrl_0_input_select_0_wd; + logic [7:0] inp_prd_cnt_ctrl_0_prescaler_0_qs; + logic [7:0] inp_prd_cnt_ctrl_0_prescaler_0_wd; + logic inp_prd_cnt_ctrl_1_we; + logic inp_prd_cnt_ctrl_1_enable_1_qs; + logic inp_prd_cnt_ctrl_1_enable_1_wd; + logic inp_prd_cnt_ctrl_1_continuous_mode_1_qs; + logic inp_prd_cnt_ctrl_1_continuous_mode_1_wd; + logic inp_prd_cnt_ctrl_1_polarity_1_qs; + logic inp_prd_cnt_ctrl_1_polarity_1_wd; + logic [7:0] inp_prd_cnt_ctrl_1_input_select_1_qs; + logic [7:0] inp_prd_cnt_ctrl_1_input_select_1_wd; + logic [7:0] inp_prd_cnt_ctrl_1_prescaler_1_qs; + logic [7:0] inp_prd_cnt_ctrl_1_prescaler_1_wd; + logic inp_prd_cnt_ctrl_2_we; + logic inp_prd_cnt_ctrl_2_enable_2_qs; + logic inp_prd_cnt_ctrl_2_enable_2_wd; + logic inp_prd_cnt_ctrl_2_continuous_mode_2_qs; + logic inp_prd_cnt_ctrl_2_continuous_mode_2_wd; + logic inp_prd_cnt_ctrl_2_polarity_2_qs; + logic inp_prd_cnt_ctrl_2_polarity_2_wd; + logic [7:0] inp_prd_cnt_ctrl_2_input_select_2_qs; + logic [7:0] inp_prd_cnt_ctrl_2_input_select_2_wd; + logic [7:0] inp_prd_cnt_ctrl_2_prescaler_2_qs; + logic [7:0] inp_prd_cnt_ctrl_2_prescaler_2_wd; + logic inp_prd_cnt_ctrl_3_we; + logic inp_prd_cnt_ctrl_3_enable_3_qs; + logic inp_prd_cnt_ctrl_3_enable_3_wd; + logic inp_prd_cnt_ctrl_3_continuous_mode_3_qs; + logic inp_prd_cnt_ctrl_3_continuous_mode_3_wd; + logic inp_prd_cnt_ctrl_3_polarity_3_qs; + logic inp_prd_cnt_ctrl_3_polarity_3_wd; + logic [7:0] inp_prd_cnt_ctrl_3_input_select_3_qs; + logic [7:0] inp_prd_cnt_ctrl_3_input_select_3_wd; + logic [7:0] inp_prd_cnt_ctrl_3_prescaler_3_qs; + logic [7:0] inp_prd_cnt_ctrl_3_prescaler_3_wd; + logic inp_prd_cnt_ctrl_4_we; + logic inp_prd_cnt_ctrl_4_enable_4_qs; + logic inp_prd_cnt_ctrl_4_enable_4_wd; + logic inp_prd_cnt_ctrl_4_continuous_mode_4_qs; + logic inp_prd_cnt_ctrl_4_continuous_mode_4_wd; + logic inp_prd_cnt_ctrl_4_polarity_4_qs; + logic inp_prd_cnt_ctrl_4_polarity_4_wd; + logic [7:0] inp_prd_cnt_ctrl_4_input_select_4_qs; + logic [7:0] inp_prd_cnt_ctrl_4_input_select_4_wd; + logic [7:0] inp_prd_cnt_ctrl_4_prescaler_4_qs; + logic [7:0] inp_prd_cnt_ctrl_4_prescaler_4_wd; + logic inp_prd_cnt_ctrl_5_we; + logic inp_prd_cnt_ctrl_5_enable_5_qs; + logic inp_prd_cnt_ctrl_5_enable_5_wd; + logic inp_prd_cnt_ctrl_5_continuous_mode_5_qs; + logic inp_prd_cnt_ctrl_5_continuous_mode_5_wd; + logic inp_prd_cnt_ctrl_5_polarity_5_qs; + logic inp_prd_cnt_ctrl_5_polarity_5_wd; + logic [7:0] inp_prd_cnt_ctrl_5_input_select_5_qs; + logic [7:0] inp_prd_cnt_ctrl_5_input_select_5_wd; + logic [7:0] inp_prd_cnt_ctrl_5_prescaler_5_qs; + logic [7:0] inp_prd_cnt_ctrl_5_prescaler_5_wd; + logic inp_prd_cnt_ctrl_6_we; + logic inp_prd_cnt_ctrl_6_enable_6_qs; + logic inp_prd_cnt_ctrl_6_enable_6_wd; + logic inp_prd_cnt_ctrl_6_continuous_mode_6_qs; + logic inp_prd_cnt_ctrl_6_continuous_mode_6_wd; + logic inp_prd_cnt_ctrl_6_polarity_6_qs; + logic inp_prd_cnt_ctrl_6_polarity_6_wd; + logic [7:0] inp_prd_cnt_ctrl_6_input_select_6_qs; + logic [7:0] inp_prd_cnt_ctrl_6_input_select_6_wd; + logic [7:0] inp_prd_cnt_ctrl_6_prescaler_6_qs; + logic [7:0] inp_prd_cnt_ctrl_6_prescaler_6_wd; + logic inp_prd_cnt_ctrl_7_we; + logic inp_prd_cnt_ctrl_7_enable_7_qs; + logic inp_prd_cnt_ctrl_7_enable_7_wd; + logic inp_prd_cnt_ctrl_7_continuous_mode_7_qs; + logic inp_prd_cnt_ctrl_7_continuous_mode_7_wd; + logic inp_prd_cnt_ctrl_7_polarity_7_qs; + logic inp_prd_cnt_ctrl_7_polarity_7_wd; + logic [7:0] inp_prd_cnt_ctrl_7_input_select_7_qs; + logic [7:0] inp_prd_cnt_ctrl_7_input_select_7_wd; + logic [7:0] inp_prd_cnt_ctrl_7_prescaler_7_qs; + logic [7:0] inp_prd_cnt_ctrl_7_prescaler_7_wd; + logic inp_prd_cnt_val_0_re; + logic [31:0] inp_prd_cnt_val_0_qs; + logic [31:0] inp_prd_cnt_val_0_wd; + logic inp_prd_cnt_val_1_re; + logic [31:0] inp_prd_cnt_val_1_qs; + logic [31:0] inp_prd_cnt_val_1_wd; + logic inp_prd_cnt_val_2_re; + logic [31:0] inp_prd_cnt_val_2_qs; + logic [31:0] inp_prd_cnt_val_2_wd; + logic inp_prd_cnt_val_3_re; + logic [31:0] inp_prd_cnt_val_3_qs; + logic [31:0] inp_prd_cnt_val_3_wd; + logic inp_prd_cnt_val_4_re; + logic [31:0] inp_prd_cnt_val_4_qs; + logic [31:0] inp_prd_cnt_val_4_wd; + logic inp_prd_cnt_val_5_re; + logic [31:0] inp_prd_cnt_val_5_qs; + logic [31:0] inp_prd_cnt_val_5_wd; + logic inp_prd_cnt_val_6_re; + logic [31:0] inp_prd_cnt_val_6_qs; + logic [31:0] inp_prd_cnt_val_6_wd; + logic inp_prd_cnt_val_7_re; + logic [31:0] inp_prd_cnt_val_7_qs; + logic [31:0] inp_prd_cnt_val_7_wd; + + // Register instances + // R[intr_state]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_intr_state ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_wd), + + // from internal hardware + .de (hw2reg.intr_state.de), + .d (hw2reg.intr_state.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.q), + .ds (), + + // to register interface (read) + .qs (intr_state_qs) + ); + + + // R[intr_enable]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_intr_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [0:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + prim_subreg_ext #( + .DW (32) + ) u_intr_test ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [0:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.qe = alert_test_qe; + + + // R[data_in]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_data_in ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.data_in.de), + .d (hw2reg.data_in.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (data_in_qs) + ); + + + // R[direct_out]: V(True) + logic direct_out_qe; + logic [0:0] direct_out_flds_we; + assign direct_out_qe = &direct_out_flds_we; + prim_subreg_ext #( + .DW (32) + ) u_direct_out ( + .re (direct_out_re), + .we (direct_out_we), + .wd (direct_out_wd), + .d (hw2reg.direct_out.d), + .qre (), + .qe (direct_out_flds_we[0]), + .q (reg2hw.direct_out.q), + .ds (), + .qs (direct_out_qs) + ); + assign reg2hw.direct_out.qe = direct_out_qe; + + + // R[masked_out_lower]: V(True) + logic masked_out_lower_qe; + logic [1:0] masked_out_lower_flds_we; + assign masked_out_lower_qe = &masked_out_lower_flds_we; + // F[data]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_masked_out_lower_data ( + .re (masked_out_lower_re), + .we (masked_out_lower_we), + .wd (masked_out_lower_data_wd), + .d (hw2reg.masked_out_lower.data.d), + .qre (), + .qe (masked_out_lower_flds_we[0]), + .q (reg2hw.masked_out_lower.data.q), + .ds (), + .qs (masked_out_lower_data_qs) + ); + assign reg2hw.masked_out_lower.data.qe = masked_out_lower_qe; + + // F[mask]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_masked_out_lower_mask ( + .re (1'b0), + .we (masked_out_lower_we), + .wd (masked_out_lower_mask_wd), + .d (hw2reg.masked_out_lower.mask.d), + .qre (), + .qe (masked_out_lower_flds_we[1]), + .q (reg2hw.masked_out_lower.mask.q), + .ds (), + .qs () + ); + assign reg2hw.masked_out_lower.mask.qe = masked_out_lower_qe; + + + // R[masked_out_upper]: V(True) + logic masked_out_upper_qe; + logic [1:0] masked_out_upper_flds_we; + assign masked_out_upper_qe = &masked_out_upper_flds_we; + // F[data]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_masked_out_upper_data ( + .re (masked_out_upper_re), + .we (masked_out_upper_we), + .wd (masked_out_upper_data_wd), + .d (hw2reg.masked_out_upper.data.d), + .qre (), + .qe (masked_out_upper_flds_we[0]), + .q (reg2hw.masked_out_upper.data.q), + .ds (), + .qs (masked_out_upper_data_qs) + ); + assign reg2hw.masked_out_upper.data.qe = masked_out_upper_qe; + + // F[mask]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_masked_out_upper_mask ( + .re (1'b0), + .we (masked_out_upper_we), + .wd (masked_out_upper_mask_wd), + .d (hw2reg.masked_out_upper.mask.d), + .qre (), + .qe (masked_out_upper_flds_we[1]), + .q (reg2hw.masked_out_upper.mask.q), + .ds (), + .qs () + ); + assign reg2hw.masked_out_upper.mask.qe = masked_out_upper_qe; + + + // R[direct_oe]: V(True) + logic direct_oe_qe; + logic [0:0] direct_oe_flds_we; + assign direct_oe_qe = &direct_oe_flds_we; + prim_subreg_ext #( + .DW (32) + ) u_direct_oe ( + .re (direct_oe_re), + .we (direct_oe_we), + .wd (direct_oe_wd), + .d (hw2reg.direct_oe.d), + .qre (), + .qe (direct_oe_flds_we[0]), + .q (reg2hw.direct_oe.q), + .ds (), + .qs (direct_oe_qs) + ); + assign reg2hw.direct_oe.qe = direct_oe_qe; + + + // R[masked_oe_lower]: V(True) + logic masked_oe_lower_qe; + logic [1:0] masked_oe_lower_flds_we; + assign masked_oe_lower_qe = &masked_oe_lower_flds_we; + // F[data]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_masked_oe_lower_data ( + .re (masked_oe_lower_re), + .we (masked_oe_lower_we), + .wd (masked_oe_lower_data_wd), + .d (hw2reg.masked_oe_lower.data.d), + .qre (), + .qe (masked_oe_lower_flds_we[0]), + .q (reg2hw.masked_oe_lower.data.q), + .ds (), + .qs (masked_oe_lower_data_qs) + ); + assign reg2hw.masked_oe_lower.data.qe = masked_oe_lower_qe; + + // F[mask]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_masked_oe_lower_mask ( + .re (masked_oe_lower_re), + .we (masked_oe_lower_we), + .wd (masked_oe_lower_mask_wd), + .d (hw2reg.masked_oe_lower.mask.d), + .qre (), + .qe (masked_oe_lower_flds_we[1]), + .q (reg2hw.masked_oe_lower.mask.q), + .ds (), + .qs (masked_oe_lower_mask_qs) + ); + assign reg2hw.masked_oe_lower.mask.qe = masked_oe_lower_qe; + + + // R[masked_oe_upper]: V(True) + logic masked_oe_upper_qe; + logic [1:0] masked_oe_upper_flds_we; + assign masked_oe_upper_qe = &masked_oe_upper_flds_we; + // F[data]: 15:0 + prim_subreg_ext #( + .DW (16) + ) u_masked_oe_upper_data ( + .re (masked_oe_upper_re), + .we (masked_oe_upper_we), + .wd (masked_oe_upper_data_wd), + .d (hw2reg.masked_oe_upper.data.d), + .qre (), + .qe (masked_oe_upper_flds_we[0]), + .q (reg2hw.masked_oe_upper.data.q), + .ds (), + .qs (masked_oe_upper_data_qs) + ); + assign reg2hw.masked_oe_upper.data.qe = masked_oe_upper_qe; + + // F[mask]: 31:16 + prim_subreg_ext #( + .DW (16) + ) u_masked_oe_upper_mask ( + .re (masked_oe_upper_re), + .we (masked_oe_upper_we), + .wd (masked_oe_upper_mask_wd), + .d (hw2reg.masked_oe_upper.mask.d), + .qre (), + .qe (masked_oe_upper_flds_we[1]), + .q (reg2hw.masked_oe_upper.mask.q), + .ds (), + .qs (masked_oe_upper_mask_qs) + ); + assign reg2hw.masked_oe_upper.mask.qe = masked_oe_upper_qe; + + + // R[intr_ctrl_en_rising]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_intr_ctrl_en_rising ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_ctrl_en_rising_we), + .wd (intr_ctrl_en_rising_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_ctrl_en_rising.q), + .ds (), + + // to register interface (read) + .qs (intr_ctrl_en_rising_qs) + ); + + + // R[intr_ctrl_en_falling]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_intr_ctrl_en_falling ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_ctrl_en_falling_we), + .wd (intr_ctrl_en_falling_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_ctrl_en_falling.q), + .ds (), + + // to register interface (read) + .qs (intr_ctrl_en_falling_qs) + ); + + + // R[intr_ctrl_en_lvlhigh]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_intr_ctrl_en_lvlhigh ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_ctrl_en_lvlhigh_we), + .wd (intr_ctrl_en_lvlhigh_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_ctrl_en_lvlhigh.q), + .ds (), + + // to register interface (read) + .qs (intr_ctrl_en_lvlhigh_qs) + ); + + + // R[intr_ctrl_en_lvllow]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_intr_ctrl_en_lvllow ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_ctrl_en_lvllow_we), + .wd (intr_ctrl_en_lvllow_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_ctrl_en_lvllow.q), + .ds (), + + // to register interface (read) + .qs (intr_ctrl_en_lvllow_qs) + ); + + + // R[ctrl_en_input_filter]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_ctrl_en_input_filter ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ctrl_en_input_filter_we), + .wd (ctrl_en_input_filter_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ctrl_en_input_filter.q), + .ds (), + + // to register interface (read) + .qs (ctrl_en_input_filter_qs) + ); + + + // R[hw_straps_data_in_valid]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_hw_straps_data_in_valid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.hw_straps_data_in_valid.de), + .d (hw2reg.hw_straps_data_in_valid.d), + + // to internal hardware + .qe (), + .q (reg2hw.hw_straps_data_in_valid.q), + .ds (), + + // to register interface (read) + .qs (hw_straps_data_in_valid_qs) + ); + + + // R[hw_straps_data_in]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_hw_straps_data_in ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.hw_straps_data_in.de), + .d (hw2reg.hw_straps_data_in.d), + + // to internal hardware + .qe (), + .q (reg2hw.hw_straps_data_in.q), + .ds (), + + // to register interface (read) + .qs (hw_straps_data_in_qs) + ); + + + // Subregister 0 of Multireg inp_prd_cnt_ctrl + // R[inp_prd_cnt_ctrl_0]: V(False) + // F[enable_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_0_enable_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_0_we), + .wd (inp_prd_cnt_ctrl_0_enable_0_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[0].enable.de), + .d (hw2reg.inp_prd_cnt_ctrl[0].enable.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[0].enable.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_0_enable_0_qs) + ); + + // F[continuous_mode_0]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_0_continuous_mode_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_0_we), + .wd (inp_prd_cnt_ctrl_0_continuous_mode_0_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[0].continuous_mode.de), + .d (hw2reg.inp_prd_cnt_ctrl[0].continuous_mode.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[0].continuous_mode.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_0_continuous_mode_0_qs) + ); + + // F[polarity_0]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_0_polarity_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_0_we), + .wd (inp_prd_cnt_ctrl_0_polarity_0_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[0].polarity.de), + .d (hw2reg.inp_prd_cnt_ctrl[0].polarity.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[0].polarity.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_0_polarity_0_qs) + ); + + // F[input_select_0]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_0_input_select_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_0_we), + .wd (inp_prd_cnt_ctrl_0_input_select_0_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[0].input_select.de), + .d (hw2reg.inp_prd_cnt_ctrl[0].input_select.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[0].input_select.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_0_input_select_0_qs) + ); + + // F[prescaler_0]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_0_prescaler_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_0_we), + .wd (inp_prd_cnt_ctrl_0_prescaler_0_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[0].prescaler.de), + .d (hw2reg.inp_prd_cnt_ctrl[0].prescaler.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[0].prescaler.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_0_prescaler_0_qs) + ); + + + // Subregister 1 of Multireg inp_prd_cnt_ctrl + // R[inp_prd_cnt_ctrl_1]: V(False) + // F[enable_1]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_1_enable_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_1_we), + .wd (inp_prd_cnt_ctrl_1_enable_1_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[1].enable.de), + .d (hw2reg.inp_prd_cnt_ctrl[1].enable.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[1].enable.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_1_enable_1_qs) + ); + + // F[continuous_mode_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_1_continuous_mode_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_1_we), + .wd (inp_prd_cnt_ctrl_1_continuous_mode_1_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[1].continuous_mode.de), + .d (hw2reg.inp_prd_cnt_ctrl[1].continuous_mode.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[1].continuous_mode.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_1_continuous_mode_1_qs) + ); + + // F[polarity_1]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_1_polarity_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_1_we), + .wd (inp_prd_cnt_ctrl_1_polarity_1_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[1].polarity.de), + .d (hw2reg.inp_prd_cnt_ctrl[1].polarity.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[1].polarity.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_1_polarity_1_qs) + ); + + // F[input_select_1]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_1_input_select_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_1_we), + .wd (inp_prd_cnt_ctrl_1_input_select_1_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[1].input_select.de), + .d (hw2reg.inp_prd_cnt_ctrl[1].input_select.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[1].input_select.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_1_input_select_1_qs) + ); + + // F[prescaler_1]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_1_prescaler_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_1_we), + .wd (inp_prd_cnt_ctrl_1_prescaler_1_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[1].prescaler.de), + .d (hw2reg.inp_prd_cnt_ctrl[1].prescaler.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[1].prescaler.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_1_prescaler_1_qs) + ); + + + // Subregister 2 of Multireg inp_prd_cnt_ctrl + // R[inp_prd_cnt_ctrl_2]: V(False) + // F[enable_2]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_2_enable_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_2_we), + .wd (inp_prd_cnt_ctrl_2_enable_2_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[2].enable.de), + .d (hw2reg.inp_prd_cnt_ctrl[2].enable.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[2].enable.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_2_enable_2_qs) + ); + + // F[continuous_mode_2]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_2_continuous_mode_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_2_we), + .wd (inp_prd_cnt_ctrl_2_continuous_mode_2_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[2].continuous_mode.de), + .d (hw2reg.inp_prd_cnt_ctrl[2].continuous_mode.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[2].continuous_mode.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_2_continuous_mode_2_qs) + ); + + // F[polarity_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_2_polarity_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_2_we), + .wd (inp_prd_cnt_ctrl_2_polarity_2_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[2].polarity.de), + .d (hw2reg.inp_prd_cnt_ctrl[2].polarity.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[2].polarity.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_2_polarity_2_qs) + ); + + // F[input_select_2]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_2_input_select_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_2_we), + .wd (inp_prd_cnt_ctrl_2_input_select_2_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[2].input_select.de), + .d (hw2reg.inp_prd_cnt_ctrl[2].input_select.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[2].input_select.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_2_input_select_2_qs) + ); + + // F[prescaler_2]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_2_prescaler_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_2_we), + .wd (inp_prd_cnt_ctrl_2_prescaler_2_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[2].prescaler.de), + .d (hw2reg.inp_prd_cnt_ctrl[2].prescaler.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[2].prescaler.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_2_prescaler_2_qs) + ); + + + // Subregister 3 of Multireg inp_prd_cnt_ctrl + // R[inp_prd_cnt_ctrl_3]: V(False) + // F[enable_3]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_3_enable_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_3_we), + .wd (inp_prd_cnt_ctrl_3_enable_3_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[3].enable.de), + .d (hw2reg.inp_prd_cnt_ctrl[3].enable.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[3].enable.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_3_enable_3_qs) + ); + + // F[continuous_mode_3]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_3_continuous_mode_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_3_we), + .wd (inp_prd_cnt_ctrl_3_continuous_mode_3_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[3].continuous_mode.de), + .d (hw2reg.inp_prd_cnt_ctrl[3].continuous_mode.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[3].continuous_mode.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_3_continuous_mode_3_qs) + ); + + // F[polarity_3]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_3_polarity_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_3_we), + .wd (inp_prd_cnt_ctrl_3_polarity_3_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[3].polarity.de), + .d (hw2reg.inp_prd_cnt_ctrl[3].polarity.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[3].polarity.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_3_polarity_3_qs) + ); + + // F[input_select_3]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_3_input_select_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_3_we), + .wd (inp_prd_cnt_ctrl_3_input_select_3_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[3].input_select.de), + .d (hw2reg.inp_prd_cnt_ctrl[3].input_select.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[3].input_select.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_3_input_select_3_qs) + ); + + // F[prescaler_3]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_3_prescaler_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_3_we), + .wd (inp_prd_cnt_ctrl_3_prescaler_3_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[3].prescaler.de), + .d (hw2reg.inp_prd_cnt_ctrl[3].prescaler.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[3].prescaler.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_3_prescaler_3_qs) + ); + + + // Subregister 4 of Multireg inp_prd_cnt_ctrl + // R[inp_prd_cnt_ctrl_4]: V(False) + // F[enable_4]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_4_enable_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_4_we), + .wd (inp_prd_cnt_ctrl_4_enable_4_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[4].enable.de), + .d (hw2reg.inp_prd_cnt_ctrl[4].enable.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[4].enable.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_4_enable_4_qs) + ); + + // F[continuous_mode_4]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_4_continuous_mode_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_4_we), + .wd (inp_prd_cnt_ctrl_4_continuous_mode_4_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[4].continuous_mode.de), + .d (hw2reg.inp_prd_cnt_ctrl[4].continuous_mode.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[4].continuous_mode.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_4_continuous_mode_4_qs) + ); + + // F[polarity_4]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_4_polarity_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_4_we), + .wd (inp_prd_cnt_ctrl_4_polarity_4_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[4].polarity.de), + .d (hw2reg.inp_prd_cnt_ctrl[4].polarity.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[4].polarity.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_4_polarity_4_qs) + ); + + // F[input_select_4]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_4_input_select_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_4_we), + .wd (inp_prd_cnt_ctrl_4_input_select_4_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[4].input_select.de), + .d (hw2reg.inp_prd_cnt_ctrl[4].input_select.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[4].input_select.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_4_input_select_4_qs) + ); + + // F[prescaler_4]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_4_prescaler_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_4_we), + .wd (inp_prd_cnt_ctrl_4_prescaler_4_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[4].prescaler.de), + .d (hw2reg.inp_prd_cnt_ctrl[4].prescaler.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[4].prescaler.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_4_prescaler_4_qs) + ); + + + // Subregister 5 of Multireg inp_prd_cnt_ctrl + // R[inp_prd_cnt_ctrl_5]: V(False) + // F[enable_5]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_5_enable_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_5_we), + .wd (inp_prd_cnt_ctrl_5_enable_5_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[5].enable.de), + .d (hw2reg.inp_prd_cnt_ctrl[5].enable.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[5].enable.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_5_enable_5_qs) + ); + + // F[continuous_mode_5]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_5_continuous_mode_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_5_we), + .wd (inp_prd_cnt_ctrl_5_continuous_mode_5_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[5].continuous_mode.de), + .d (hw2reg.inp_prd_cnt_ctrl[5].continuous_mode.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[5].continuous_mode.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_5_continuous_mode_5_qs) + ); + + // F[polarity_5]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_5_polarity_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_5_we), + .wd (inp_prd_cnt_ctrl_5_polarity_5_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[5].polarity.de), + .d (hw2reg.inp_prd_cnt_ctrl[5].polarity.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[5].polarity.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_5_polarity_5_qs) + ); + + // F[input_select_5]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_5_input_select_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_5_we), + .wd (inp_prd_cnt_ctrl_5_input_select_5_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[5].input_select.de), + .d (hw2reg.inp_prd_cnt_ctrl[5].input_select.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[5].input_select.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_5_input_select_5_qs) + ); + + // F[prescaler_5]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_5_prescaler_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_5_we), + .wd (inp_prd_cnt_ctrl_5_prescaler_5_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[5].prescaler.de), + .d (hw2reg.inp_prd_cnt_ctrl[5].prescaler.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[5].prescaler.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_5_prescaler_5_qs) + ); + + + // Subregister 6 of Multireg inp_prd_cnt_ctrl + // R[inp_prd_cnt_ctrl_6]: V(False) + // F[enable_6]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_6_enable_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_6_we), + .wd (inp_prd_cnt_ctrl_6_enable_6_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[6].enable.de), + .d (hw2reg.inp_prd_cnt_ctrl[6].enable.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[6].enable.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_6_enable_6_qs) + ); + + // F[continuous_mode_6]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_6_continuous_mode_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_6_we), + .wd (inp_prd_cnt_ctrl_6_continuous_mode_6_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[6].continuous_mode.de), + .d (hw2reg.inp_prd_cnt_ctrl[6].continuous_mode.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[6].continuous_mode.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_6_continuous_mode_6_qs) + ); + + // F[polarity_6]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_6_polarity_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_6_we), + .wd (inp_prd_cnt_ctrl_6_polarity_6_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[6].polarity.de), + .d (hw2reg.inp_prd_cnt_ctrl[6].polarity.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[6].polarity.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_6_polarity_6_qs) + ); + + // F[input_select_6]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_6_input_select_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_6_we), + .wd (inp_prd_cnt_ctrl_6_input_select_6_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[6].input_select.de), + .d (hw2reg.inp_prd_cnt_ctrl[6].input_select.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[6].input_select.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_6_input_select_6_qs) + ); + + // F[prescaler_6]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_6_prescaler_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_6_we), + .wd (inp_prd_cnt_ctrl_6_prescaler_6_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[6].prescaler.de), + .d (hw2reg.inp_prd_cnt_ctrl[6].prescaler.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[6].prescaler.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_6_prescaler_6_qs) + ); + + + // Subregister 7 of Multireg inp_prd_cnt_ctrl + // R[inp_prd_cnt_ctrl_7]: V(False) + // F[enable_7]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_7_enable_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_7_we), + .wd (inp_prd_cnt_ctrl_7_enable_7_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[7].enable.de), + .d (hw2reg.inp_prd_cnt_ctrl[7].enable.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[7].enable.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_7_enable_7_qs) + ); + + // F[continuous_mode_7]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_7_continuous_mode_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_7_we), + .wd (inp_prd_cnt_ctrl_7_continuous_mode_7_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[7].continuous_mode.de), + .d (hw2reg.inp_prd_cnt_ctrl[7].continuous_mode.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[7].continuous_mode.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_7_continuous_mode_7_qs) + ); + + // F[polarity_7]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_7_polarity_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_7_we), + .wd (inp_prd_cnt_ctrl_7_polarity_7_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[7].polarity.de), + .d (hw2reg.inp_prd_cnt_ctrl[7].polarity.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[7].polarity.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_7_polarity_7_qs) + ); + + // F[input_select_7]: 15:8 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_7_input_select_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_7_we), + .wd (inp_prd_cnt_ctrl_7_input_select_7_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[7].input_select.de), + .d (hw2reg.inp_prd_cnt_ctrl[7].input_select.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[7].input_select.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_7_input_select_7_qs) + ); + + // F[prescaler_7]: 23:16 + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_ctrl_7_prescaler_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_ctrl_7_we), + .wd (inp_prd_cnt_ctrl_7_prescaler_7_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_ctrl[7].prescaler.de), + .d (hw2reg.inp_prd_cnt_ctrl[7].prescaler.d), + + // to internal hardware + .qe (), + .q (reg2hw.inp_prd_cnt_ctrl[7].prescaler.q), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_ctrl_7_prescaler_7_qs) + ); + + + // Subregister 0 of Multireg inp_prd_cnt_val + // R[inp_prd_cnt_val_0]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_val_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_val_0_re), + .wd (inp_prd_cnt_val_0_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_val[0].de), + .d (hw2reg.inp_prd_cnt_val[0].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_val_0_qs) + ); + + + // Subregister 1 of Multireg inp_prd_cnt_val + // R[inp_prd_cnt_val_1]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_val_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_val_1_re), + .wd (inp_prd_cnt_val_1_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_val[1].de), + .d (hw2reg.inp_prd_cnt_val[1].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_val_1_qs) + ); + + + // Subregister 2 of Multireg inp_prd_cnt_val + // R[inp_prd_cnt_val_2]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_val_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_val_2_re), + .wd (inp_prd_cnt_val_2_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_val[2].de), + .d (hw2reg.inp_prd_cnt_val[2].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_val_2_qs) + ); + + + // Subregister 3 of Multireg inp_prd_cnt_val + // R[inp_prd_cnt_val_3]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_val_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_val_3_re), + .wd (inp_prd_cnt_val_3_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_val[3].de), + .d (hw2reg.inp_prd_cnt_val[3].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_val_3_qs) + ); + + + // Subregister 4 of Multireg inp_prd_cnt_val + // R[inp_prd_cnt_val_4]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_val_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_val_4_re), + .wd (inp_prd_cnt_val_4_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_val[4].de), + .d (hw2reg.inp_prd_cnt_val[4].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_val_4_qs) + ); + + + // Subregister 5 of Multireg inp_prd_cnt_val + // R[inp_prd_cnt_val_5]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_val_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_val_5_re), + .wd (inp_prd_cnt_val_5_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_val[5].de), + .d (hw2reg.inp_prd_cnt_val[5].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_val_5_qs) + ); + + + // Subregister 6 of Multireg inp_prd_cnt_val + // R[inp_prd_cnt_val_6]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_val_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_val_6_re), + .wd (inp_prd_cnt_val_6_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_val[6].de), + .d (hw2reg.inp_prd_cnt_val[6].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_val_6_qs) + ); + + + // Subregister 7 of Multireg inp_prd_cnt_val + // R[inp_prd_cnt_val_7]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRC), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_inp_prd_cnt_val_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (inp_prd_cnt_val_7_re), + .wd (inp_prd_cnt_val_7_wd), + + // from internal hardware + .de (hw2reg.inp_prd_cnt_val[7].de), + .d (hw2reg.inp_prd_cnt_val[7].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (inp_prd_cnt_val_7_qs) + ); + + + + logic [33:0] addr_hit; + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + + logic [33:0] racl_addr_hit_read; + logic [33:0] racl_addr_hit_write; + + if (EnableRacl) begin : gen_racl_role_logic + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + end else begin : gen_no_racl_role_logic + assign racl_role = '0; + assign racl_role_vec = '0; + end + + always_comb begin + racl_addr_hit_read = '0; + racl_addr_hit_write = '0; + addr_hit[ 0] = (reg_addr == GPIO_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == GPIO_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == GPIO_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == GPIO_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == GPIO_DATA_IN_OFFSET); + addr_hit[ 5] = (reg_addr == GPIO_DIRECT_OUT_OFFSET); + addr_hit[ 6] = (reg_addr == GPIO_MASKED_OUT_LOWER_OFFSET); + addr_hit[ 7] = (reg_addr == GPIO_MASKED_OUT_UPPER_OFFSET); + addr_hit[ 8] = (reg_addr == GPIO_DIRECT_OE_OFFSET); + addr_hit[ 9] = (reg_addr == GPIO_MASKED_OE_LOWER_OFFSET); + addr_hit[10] = (reg_addr == GPIO_MASKED_OE_UPPER_OFFSET); + addr_hit[11] = (reg_addr == GPIO_INTR_CTRL_EN_RISING_OFFSET); + addr_hit[12] = (reg_addr == GPIO_INTR_CTRL_EN_FALLING_OFFSET); + addr_hit[13] = (reg_addr == GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET); + addr_hit[14] = (reg_addr == GPIO_INTR_CTRL_EN_LVLLOW_OFFSET); + addr_hit[15] = (reg_addr == GPIO_CTRL_EN_INPUT_FILTER_OFFSET); + addr_hit[16] = (reg_addr == GPIO_HW_STRAPS_DATA_IN_VALID_OFFSET); + addr_hit[17] = (reg_addr == GPIO_HW_STRAPS_DATA_IN_OFFSET); + addr_hit[18] = (reg_addr == GPIO_INP_PRD_CNT_CTRL_0_OFFSET); + addr_hit[19] = (reg_addr == GPIO_INP_PRD_CNT_CTRL_1_OFFSET); + addr_hit[20] = (reg_addr == GPIO_INP_PRD_CNT_CTRL_2_OFFSET); + addr_hit[21] = (reg_addr == GPIO_INP_PRD_CNT_CTRL_3_OFFSET); + addr_hit[22] = (reg_addr == GPIO_INP_PRD_CNT_CTRL_4_OFFSET); + addr_hit[23] = (reg_addr == GPIO_INP_PRD_CNT_CTRL_5_OFFSET); + addr_hit[24] = (reg_addr == GPIO_INP_PRD_CNT_CTRL_6_OFFSET); + addr_hit[25] = (reg_addr == GPIO_INP_PRD_CNT_CTRL_7_OFFSET); + addr_hit[26] = (reg_addr == GPIO_INP_PRD_CNT_VAL_0_OFFSET); + addr_hit[27] = (reg_addr == GPIO_INP_PRD_CNT_VAL_1_OFFSET); + addr_hit[28] = (reg_addr == GPIO_INP_PRD_CNT_VAL_2_OFFSET); + addr_hit[29] = (reg_addr == GPIO_INP_PRD_CNT_VAL_3_OFFSET); + addr_hit[30] = (reg_addr == GPIO_INP_PRD_CNT_VAL_4_OFFSET); + addr_hit[31] = (reg_addr == GPIO_INP_PRD_CNT_VAL_5_OFFSET); + addr_hit[32] = (reg_addr == GPIO_INP_PRD_CNT_VAL_6_OFFSET); + addr_hit[33] = (reg_addr == GPIO_INP_PRD_CNT_VAL_7_OFFSET); + + if (EnableRacl) begin : gen_racl_hit + for (int unsigned slice_idx = 0; slice_idx < 34; slice_idx++) begin + racl_addr_hit_read[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].read_perm + & racl_role_vec)); + racl_addr_hit_write[slice_idx] = + addr_hit[slice_idx] & (|(racl_policies_i[RaclPolicySelVec[slice_idx]].write_perm + & racl_role_vec)); + end + end else begin : gen_no_racl + racl_addr_hit_read = addr_hit; + racl_addr_hit_write = addr_hit; + end + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + // A valid address hit, access, but failed the RACL check + assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) | + (reg_we & ~|racl_addr_hit_write)); + assign racl_error_o.request_address = top_pkg::TL_AW'(reg_addr); + assign racl_error_o.racl_role = racl_role; + assign racl_error_o.overflow = 1'b0; + + if (EnableRacl) begin : gen_racl_log + assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd); + assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get; + end else begin : gen_no_racl_log + assign racl_error_o.ctn_uid = '0; + assign racl_error_o.read_access = 1'b0; + end + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((racl_addr_hit_write[ 0] & (|(GPIO_PERMIT[ 0] & ~reg_be))) | + (racl_addr_hit_write[ 1] & (|(GPIO_PERMIT[ 1] & ~reg_be))) | + (racl_addr_hit_write[ 2] & (|(GPIO_PERMIT[ 2] & ~reg_be))) | + (racl_addr_hit_write[ 3] & (|(GPIO_PERMIT[ 3] & ~reg_be))) | + (racl_addr_hit_write[ 4] & (|(GPIO_PERMIT[ 4] & ~reg_be))) | + (racl_addr_hit_write[ 5] & (|(GPIO_PERMIT[ 5] & ~reg_be))) | + (racl_addr_hit_write[ 6] & (|(GPIO_PERMIT[ 6] & ~reg_be))) | + (racl_addr_hit_write[ 7] & (|(GPIO_PERMIT[ 7] & ~reg_be))) | + (racl_addr_hit_write[ 8] & (|(GPIO_PERMIT[ 8] & ~reg_be))) | + (racl_addr_hit_write[ 9] & (|(GPIO_PERMIT[ 9] & ~reg_be))) | + (racl_addr_hit_write[10] & (|(GPIO_PERMIT[10] & ~reg_be))) | + (racl_addr_hit_write[11] & (|(GPIO_PERMIT[11] & ~reg_be))) | + (racl_addr_hit_write[12] & (|(GPIO_PERMIT[12] & ~reg_be))) | + (racl_addr_hit_write[13] & (|(GPIO_PERMIT[13] & ~reg_be))) | + (racl_addr_hit_write[14] & (|(GPIO_PERMIT[14] & ~reg_be))) | + (racl_addr_hit_write[15] & (|(GPIO_PERMIT[15] & ~reg_be))) | + (racl_addr_hit_write[16] & (|(GPIO_PERMIT[16] & ~reg_be))) | + (racl_addr_hit_write[17] & (|(GPIO_PERMIT[17] & ~reg_be))) | + (racl_addr_hit_write[18] & (|(GPIO_PERMIT[18] & ~reg_be))) | + (racl_addr_hit_write[19] & (|(GPIO_PERMIT[19] & ~reg_be))) | + (racl_addr_hit_write[20] & (|(GPIO_PERMIT[20] & ~reg_be))) | + (racl_addr_hit_write[21] & (|(GPIO_PERMIT[21] & ~reg_be))) | + (racl_addr_hit_write[22] & (|(GPIO_PERMIT[22] & ~reg_be))) | + (racl_addr_hit_write[23] & (|(GPIO_PERMIT[23] & ~reg_be))) | + (racl_addr_hit_write[24] & (|(GPIO_PERMIT[24] & ~reg_be))) | + (racl_addr_hit_write[25] & (|(GPIO_PERMIT[25] & ~reg_be))) | + (racl_addr_hit_write[26] & (|(GPIO_PERMIT[26] & ~reg_be))) | + (racl_addr_hit_write[27] & (|(GPIO_PERMIT[27] & ~reg_be))) | + (racl_addr_hit_write[28] & (|(GPIO_PERMIT[28] & ~reg_be))) | + (racl_addr_hit_write[29] & (|(GPIO_PERMIT[29] & ~reg_be))) | + (racl_addr_hit_write[30] & (|(GPIO_PERMIT[30] & ~reg_be))) | + (racl_addr_hit_write[31] & (|(GPIO_PERMIT[31] & ~reg_be))) | + (racl_addr_hit_write[32] & (|(GPIO_PERMIT[32] & ~reg_be))) | + (racl_addr_hit_write[33] & (|(GPIO_PERMIT[33] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = racl_addr_hit_write[0] & reg_we & !reg_error; + + assign intr_state_wd = reg_wdata[31:0]; + assign intr_enable_we = racl_addr_hit_write[1] & reg_we & !reg_error; + + assign intr_enable_wd = reg_wdata[31:0]; + assign intr_test_we = racl_addr_hit_write[2] & reg_we & !reg_error; + + assign intr_test_wd = reg_wdata[31:0]; + assign alert_test_we = racl_addr_hit_write[3] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + assign direct_out_re = racl_addr_hit_read[5] & reg_re & !reg_error; + assign direct_out_we = racl_addr_hit_write[5] & reg_we & !reg_error; + + assign direct_out_wd = reg_wdata[31:0]; + assign masked_out_lower_re = racl_addr_hit_read[6] & reg_re & !reg_error; + assign masked_out_lower_we = racl_addr_hit_write[6] & reg_we & !reg_error; + + assign masked_out_lower_data_wd = reg_wdata[15:0]; + + assign masked_out_lower_mask_wd = reg_wdata[31:16]; + assign masked_out_upper_re = racl_addr_hit_read[7] & reg_re & !reg_error; + assign masked_out_upper_we = racl_addr_hit_write[7] & reg_we & !reg_error; + + assign masked_out_upper_data_wd = reg_wdata[15:0]; + + assign masked_out_upper_mask_wd = reg_wdata[31:16]; + assign direct_oe_re = racl_addr_hit_read[8] & reg_re & !reg_error; + assign direct_oe_we = racl_addr_hit_write[8] & reg_we & !reg_error; + + assign direct_oe_wd = reg_wdata[31:0]; + assign masked_oe_lower_re = racl_addr_hit_read[9] & reg_re & !reg_error; + assign masked_oe_lower_we = racl_addr_hit_write[9] & reg_we & !reg_error; + + assign masked_oe_lower_data_wd = reg_wdata[15:0]; + + assign masked_oe_lower_mask_wd = reg_wdata[31:16]; + assign masked_oe_upper_re = racl_addr_hit_read[10] & reg_re & !reg_error; + assign masked_oe_upper_we = racl_addr_hit_write[10] & reg_we & !reg_error; + + assign masked_oe_upper_data_wd = reg_wdata[15:0]; + + assign masked_oe_upper_mask_wd = reg_wdata[31:16]; + assign intr_ctrl_en_rising_we = racl_addr_hit_write[11] & reg_we & !reg_error; + + assign intr_ctrl_en_rising_wd = reg_wdata[31:0]; + assign intr_ctrl_en_falling_we = racl_addr_hit_write[12] & reg_we & !reg_error; + + assign intr_ctrl_en_falling_wd = reg_wdata[31:0]; + assign intr_ctrl_en_lvlhigh_we = racl_addr_hit_write[13] & reg_we & !reg_error; + + assign intr_ctrl_en_lvlhigh_wd = reg_wdata[31:0]; + assign intr_ctrl_en_lvllow_we = racl_addr_hit_write[14] & reg_we & !reg_error; + + assign intr_ctrl_en_lvllow_wd = reg_wdata[31:0]; + assign ctrl_en_input_filter_we = racl_addr_hit_write[15] & reg_we & !reg_error; + + assign ctrl_en_input_filter_wd = reg_wdata[31:0]; + assign inp_prd_cnt_ctrl_0_we = racl_addr_hit_write[18] & reg_we & !reg_error; + + assign inp_prd_cnt_ctrl_0_enable_0_wd = reg_wdata[0]; + + assign inp_prd_cnt_ctrl_0_continuous_mode_0_wd = reg_wdata[1]; + + assign inp_prd_cnt_ctrl_0_polarity_0_wd = reg_wdata[2]; + + assign inp_prd_cnt_ctrl_0_input_select_0_wd = reg_wdata[15:8]; + + assign inp_prd_cnt_ctrl_0_prescaler_0_wd = reg_wdata[23:16]; + assign inp_prd_cnt_ctrl_1_we = racl_addr_hit_write[19] & reg_we & !reg_error; + + assign inp_prd_cnt_ctrl_1_enable_1_wd = reg_wdata[0]; + + assign inp_prd_cnt_ctrl_1_continuous_mode_1_wd = reg_wdata[1]; + + assign inp_prd_cnt_ctrl_1_polarity_1_wd = reg_wdata[2]; + + assign inp_prd_cnt_ctrl_1_input_select_1_wd = reg_wdata[15:8]; + + assign inp_prd_cnt_ctrl_1_prescaler_1_wd = reg_wdata[23:16]; + assign inp_prd_cnt_ctrl_2_we = racl_addr_hit_write[20] & reg_we & !reg_error; + + assign inp_prd_cnt_ctrl_2_enable_2_wd = reg_wdata[0]; + + assign inp_prd_cnt_ctrl_2_continuous_mode_2_wd = reg_wdata[1]; + + assign inp_prd_cnt_ctrl_2_polarity_2_wd = reg_wdata[2]; + + assign inp_prd_cnt_ctrl_2_input_select_2_wd = reg_wdata[15:8]; + + assign inp_prd_cnt_ctrl_2_prescaler_2_wd = reg_wdata[23:16]; + assign inp_prd_cnt_ctrl_3_we = racl_addr_hit_write[21] & reg_we & !reg_error; + + assign inp_prd_cnt_ctrl_3_enable_3_wd = reg_wdata[0]; + + assign inp_prd_cnt_ctrl_3_continuous_mode_3_wd = reg_wdata[1]; + + assign inp_prd_cnt_ctrl_3_polarity_3_wd = reg_wdata[2]; + + assign inp_prd_cnt_ctrl_3_input_select_3_wd = reg_wdata[15:8]; + + assign inp_prd_cnt_ctrl_3_prescaler_3_wd = reg_wdata[23:16]; + assign inp_prd_cnt_ctrl_4_we = racl_addr_hit_write[22] & reg_we & !reg_error; + + assign inp_prd_cnt_ctrl_4_enable_4_wd = reg_wdata[0]; + + assign inp_prd_cnt_ctrl_4_continuous_mode_4_wd = reg_wdata[1]; + + assign inp_prd_cnt_ctrl_4_polarity_4_wd = reg_wdata[2]; + + assign inp_prd_cnt_ctrl_4_input_select_4_wd = reg_wdata[15:8]; + + assign inp_prd_cnt_ctrl_4_prescaler_4_wd = reg_wdata[23:16]; + assign inp_prd_cnt_ctrl_5_we = racl_addr_hit_write[23] & reg_we & !reg_error; + + assign inp_prd_cnt_ctrl_5_enable_5_wd = reg_wdata[0]; + + assign inp_prd_cnt_ctrl_5_continuous_mode_5_wd = reg_wdata[1]; + + assign inp_prd_cnt_ctrl_5_polarity_5_wd = reg_wdata[2]; + + assign inp_prd_cnt_ctrl_5_input_select_5_wd = reg_wdata[15:8]; + + assign inp_prd_cnt_ctrl_5_prescaler_5_wd = reg_wdata[23:16]; + assign inp_prd_cnt_ctrl_6_we = racl_addr_hit_write[24] & reg_we & !reg_error; + + assign inp_prd_cnt_ctrl_6_enable_6_wd = reg_wdata[0]; + + assign inp_prd_cnt_ctrl_6_continuous_mode_6_wd = reg_wdata[1]; + + assign inp_prd_cnt_ctrl_6_polarity_6_wd = reg_wdata[2]; + + assign inp_prd_cnt_ctrl_6_input_select_6_wd = reg_wdata[15:8]; + + assign inp_prd_cnt_ctrl_6_prescaler_6_wd = reg_wdata[23:16]; + assign inp_prd_cnt_ctrl_7_we = racl_addr_hit_write[25] & reg_we & !reg_error; + + assign inp_prd_cnt_ctrl_7_enable_7_wd = reg_wdata[0]; + + assign inp_prd_cnt_ctrl_7_continuous_mode_7_wd = reg_wdata[1]; + + assign inp_prd_cnt_ctrl_7_polarity_7_wd = reg_wdata[2]; + + assign inp_prd_cnt_ctrl_7_input_select_7_wd = reg_wdata[15:8]; + + assign inp_prd_cnt_ctrl_7_prescaler_7_wd = reg_wdata[23:16]; + assign inp_prd_cnt_val_0_re = racl_addr_hit_read[26] & reg_re & !reg_error; + + assign inp_prd_cnt_val_0_wd = '1; + assign inp_prd_cnt_val_1_re = racl_addr_hit_read[27] & reg_re & !reg_error; + + assign inp_prd_cnt_val_1_wd = '1; + assign inp_prd_cnt_val_2_re = racl_addr_hit_read[28] & reg_re & !reg_error; + + assign inp_prd_cnt_val_2_wd = '1; + assign inp_prd_cnt_val_3_re = racl_addr_hit_read[29] & reg_re & !reg_error; + + assign inp_prd_cnt_val_3_wd = '1; + assign inp_prd_cnt_val_4_re = racl_addr_hit_read[30] & reg_re & !reg_error; + + assign inp_prd_cnt_val_4_wd = '1; + assign inp_prd_cnt_val_5_re = racl_addr_hit_read[31] & reg_re & !reg_error; + + assign inp_prd_cnt_val_5_wd = '1; + assign inp_prd_cnt_val_6_re = racl_addr_hit_read[32] & reg_re & !reg_error; + + assign inp_prd_cnt_val_6_wd = '1; + assign inp_prd_cnt_val_7_re = racl_addr_hit_read[33] & reg_re & !reg_error; + + assign inp_prd_cnt_val_7_wd = '1; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + reg_we_check[4] = 1'b0; + reg_we_check[5] = direct_out_we; + reg_we_check[6] = masked_out_lower_we; + reg_we_check[7] = masked_out_upper_we; + reg_we_check[8] = direct_oe_we; + reg_we_check[9] = masked_oe_lower_we; + reg_we_check[10] = masked_oe_upper_we; + reg_we_check[11] = intr_ctrl_en_rising_we; + reg_we_check[12] = intr_ctrl_en_falling_we; + reg_we_check[13] = intr_ctrl_en_lvlhigh_we; + reg_we_check[14] = intr_ctrl_en_lvllow_we; + reg_we_check[15] = ctrl_en_input_filter_we; + reg_we_check[16] = 1'b0; + reg_we_check[17] = 1'b0; + reg_we_check[18] = inp_prd_cnt_ctrl_0_we; + reg_we_check[19] = inp_prd_cnt_ctrl_1_we; + reg_we_check[20] = inp_prd_cnt_ctrl_2_we; + reg_we_check[21] = inp_prd_cnt_ctrl_3_we; + reg_we_check[22] = inp_prd_cnt_ctrl_4_we; + reg_we_check[23] = inp_prd_cnt_ctrl_5_we; + reg_we_check[24] = inp_prd_cnt_ctrl_6_we; + reg_we_check[25] = inp_prd_cnt_ctrl_7_we; + reg_we_check[26] = 1'b0; + reg_we_check[27] = 1'b0; + reg_we_check[28] = 1'b0; + reg_we_check[29] = 1'b0; + reg_we_check[30] = 1'b0; + reg_we_check[31] = 1'b0; + reg_we_check[32] = 1'b0; + reg_we_check[33] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + racl_addr_hit_read[0]: begin + reg_rdata_next[31:0] = intr_state_qs; + end + + racl_addr_hit_read[1]: begin + reg_rdata_next[31:0] = intr_enable_qs; + end + + racl_addr_hit_read[2]: begin + reg_rdata_next[31:0] = '0; + end + + racl_addr_hit_read[3]: begin + reg_rdata_next[0] = '0; + end + + racl_addr_hit_read[4]: begin + reg_rdata_next[31:0] = data_in_qs; + end + + racl_addr_hit_read[5]: begin + reg_rdata_next[31:0] = direct_out_qs; + end + + racl_addr_hit_read[6]: begin + reg_rdata_next[15:0] = masked_out_lower_data_qs; + reg_rdata_next[31:16] = '0; + end + + racl_addr_hit_read[7]: begin + reg_rdata_next[15:0] = masked_out_upper_data_qs; + reg_rdata_next[31:16] = '0; + end + + racl_addr_hit_read[8]: begin + reg_rdata_next[31:0] = direct_oe_qs; + end + + racl_addr_hit_read[9]: begin + reg_rdata_next[15:0] = masked_oe_lower_data_qs; + reg_rdata_next[31:16] = masked_oe_lower_mask_qs; + end + + racl_addr_hit_read[10]: begin + reg_rdata_next[15:0] = masked_oe_upper_data_qs; + reg_rdata_next[31:16] = masked_oe_upper_mask_qs; + end + + racl_addr_hit_read[11]: begin + reg_rdata_next[31:0] = intr_ctrl_en_rising_qs; + end + + racl_addr_hit_read[12]: begin + reg_rdata_next[31:0] = intr_ctrl_en_falling_qs; + end + + racl_addr_hit_read[13]: begin + reg_rdata_next[31:0] = intr_ctrl_en_lvlhigh_qs; + end + + racl_addr_hit_read[14]: begin + reg_rdata_next[31:0] = intr_ctrl_en_lvllow_qs; + end + + racl_addr_hit_read[15]: begin + reg_rdata_next[31:0] = ctrl_en_input_filter_qs; + end + + racl_addr_hit_read[16]: begin + reg_rdata_next[0] = hw_straps_data_in_valid_qs; + end + + racl_addr_hit_read[17]: begin + reg_rdata_next[31:0] = hw_straps_data_in_qs; + end + + racl_addr_hit_read[18]: begin + reg_rdata_next[0] = inp_prd_cnt_ctrl_0_enable_0_qs; + reg_rdata_next[1] = inp_prd_cnt_ctrl_0_continuous_mode_0_qs; + reg_rdata_next[2] = inp_prd_cnt_ctrl_0_polarity_0_qs; + reg_rdata_next[15:8] = inp_prd_cnt_ctrl_0_input_select_0_qs; + reg_rdata_next[23:16] = inp_prd_cnt_ctrl_0_prescaler_0_qs; + end + + racl_addr_hit_read[19]: begin + reg_rdata_next[0] = inp_prd_cnt_ctrl_1_enable_1_qs; + reg_rdata_next[1] = inp_prd_cnt_ctrl_1_continuous_mode_1_qs; + reg_rdata_next[2] = inp_prd_cnt_ctrl_1_polarity_1_qs; + reg_rdata_next[15:8] = inp_prd_cnt_ctrl_1_input_select_1_qs; + reg_rdata_next[23:16] = inp_prd_cnt_ctrl_1_prescaler_1_qs; + end + + racl_addr_hit_read[20]: begin + reg_rdata_next[0] = inp_prd_cnt_ctrl_2_enable_2_qs; + reg_rdata_next[1] = inp_prd_cnt_ctrl_2_continuous_mode_2_qs; + reg_rdata_next[2] = inp_prd_cnt_ctrl_2_polarity_2_qs; + reg_rdata_next[15:8] = inp_prd_cnt_ctrl_2_input_select_2_qs; + reg_rdata_next[23:16] = inp_prd_cnt_ctrl_2_prescaler_2_qs; + end + + racl_addr_hit_read[21]: begin + reg_rdata_next[0] = inp_prd_cnt_ctrl_3_enable_3_qs; + reg_rdata_next[1] = inp_prd_cnt_ctrl_3_continuous_mode_3_qs; + reg_rdata_next[2] = inp_prd_cnt_ctrl_3_polarity_3_qs; + reg_rdata_next[15:8] = inp_prd_cnt_ctrl_3_input_select_3_qs; + reg_rdata_next[23:16] = inp_prd_cnt_ctrl_3_prescaler_3_qs; + end + + racl_addr_hit_read[22]: begin + reg_rdata_next[0] = inp_prd_cnt_ctrl_4_enable_4_qs; + reg_rdata_next[1] = inp_prd_cnt_ctrl_4_continuous_mode_4_qs; + reg_rdata_next[2] = inp_prd_cnt_ctrl_4_polarity_4_qs; + reg_rdata_next[15:8] = inp_prd_cnt_ctrl_4_input_select_4_qs; + reg_rdata_next[23:16] = inp_prd_cnt_ctrl_4_prescaler_4_qs; + end + + racl_addr_hit_read[23]: begin + reg_rdata_next[0] = inp_prd_cnt_ctrl_5_enable_5_qs; + reg_rdata_next[1] = inp_prd_cnt_ctrl_5_continuous_mode_5_qs; + reg_rdata_next[2] = inp_prd_cnt_ctrl_5_polarity_5_qs; + reg_rdata_next[15:8] = inp_prd_cnt_ctrl_5_input_select_5_qs; + reg_rdata_next[23:16] = inp_prd_cnt_ctrl_5_prescaler_5_qs; + end + + racl_addr_hit_read[24]: begin + reg_rdata_next[0] = inp_prd_cnt_ctrl_6_enable_6_qs; + reg_rdata_next[1] = inp_prd_cnt_ctrl_6_continuous_mode_6_qs; + reg_rdata_next[2] = inp_prd_cnt_ctrl_6_polarity_6_qs; + reg_rdata_next[15:8] = inp_prd_cnt_ctrl_6_input_select_6_qs; + reg_rdata_next[23:16] = inp_prd_cnt_ctrl_6_prescaler_6_qs; + end + + racl_addr_hit_read[25]: begin + reg_rdata_next[0] = inp_prd_cnt_ctrl_7_enable_7_qs; + reg_rdata_next[1] = inp_prd_cnt_ctrl_7_continuous_mode_7_qs; + reg_rdata_next[2] = inp_prd_cnt_ctrl_7_polarity_7_qs; + reg_rdata_next[15:8] = inp_prd_cnt_ctrl_7_input_select_7_qs; + reg_rdata_next[23:16] = inp_prd_cnt_ctrl_7_prescaler_7_qs; + end + + racl_addr_hit_read[26]: begin + reg_rdata_next[31:0] = inp_prd_cnt_val_0_qs; + end + + racl_addr_hit_read[27]: begin + reg_rdata_next[31:0] = inp_prd_cnt_val_1_qs; + end + + racl_addr_hit_read[28]: begin + reg_rdata_next[31:0] = inp_prd_cnt_val_2_qs; + end + + racl_addr_hit_read[29]: begin + reg_rdata_next[31:0] = inp_prd_cnt_val_3_qs; + end + + racl_addr_hit_read[30]: begin + reg_rdata_next[31:0] = inp_prd_cnt_val_4_qs; + end + + racl_addr_hit_read[31]: begin + reg_rdata_next[31:0] = inp_prd_cnt_val_5_qs; + end + + racl_addr_hit_read[32]: begin + reg_rdata_next[31:0] = inp_prd_cnt_val_6_qs; + end + + racl_addr_hit_read[33]: begin + reg_rdata_next[31:0] = inp_prd_cnt_val_7_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + logic unused_policy_sel; + assign unused_policy_sel = ^racl_policies_i; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/BUILD new file mode 100644 index 00000000000..46e10e1825a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/BUILD @@ -0,0 +1,25 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.svg", + ]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/README.md new file mode 100644 index 00000000000..80f25e639f6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/README.md @@ -0,0 +1,63 @@ +# OTP Controller Technical Specification + +[`otp_ctrl`](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/otp_ctrl/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/otp_ctrl/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/otp_ctrl/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/otp_ctrl/code.svg) + +# Overview + +This document specifies the functionality of the one time programmable (OTP) memory controller. +The OTP controller is a module that is a peripheral on the chip interconnect bus, and thus follows the [Comportability Specification](../../../../doc/contributing/hw/comportability/README.md). + +The OTP is a module that provides a device with one-time-programming functionality. +The result of this programming is non-volatile, and unlike flash, cannot be reversed. +The OTP functionality is constructed through an open-source OTP controller and a proprietary OTP IP. + +The OTP controller provides: +- An open-source abstraction interface that software can use to interact with a proprietary OTP block underneath. +- An open-source abstraction interface that hardware components (for example [life cycle controller](../../../ip/lc_ctrl/README.md) and [key manager](../../../ip/keymgr/README.md)) can use to interact with a proprietary OTP block underneath. +- High level logical security protection, such as integrity checks and scrambling of sensitive content. +- Software isolation for when OTP contents are readable and programmable. + +The proprietary OTP IP provides: +- Reliable, non-volatile storage. +- Technology-specific redundancy or error correction mechanisms. +- Physical defensive features such as SCA and FI resistance. +- Visual and electrical probing resistance. + +Together, the OTP controller and IP provide secure one-time-programming functionality that is used throughout the life cycle (LC) of a device. + +## Features + +- Multiple logical partitions of the underlying OTP IP + - Each partition is lockable and integrity checked + - Integrity digests are stored alongside each logical bank +- Periodic / persistent checks of OTP values + - Periodic checks of shadowed content vs digests + - Periodic checks of OTP stored content and shadowed content + - Persistent checks for immediate errors +- Separate life cycle partition and interface to life cycle controller + - Supports life cycle functions, but cannot be integrity locked +- Lightweight scrambling of secret OTP partition using a global netlist constant +- Lightweight ephemeral key derivation function for RAM scrambling mechanisms +- Lightweight key derivation function for FLASH scrambling mechanism + +## OTP Controller Overview + +The functionality of OTP is split into an open-source and a closed-source part, with a clearly defined boundary in between, as illustrated in the simplified high-level block diagram below. + +![OTP Controller Overview](./doc/otp_ctrl_overview.svg) + +It is the task of the open-source controller to provide a common, non-technology specific interface to OTP users with a common register interface and a clearly defined I/O interface to hardware. +The open-source controller implements logical isolation and partitioning of OTP storage that enables users to separate different functions of the OTP into "partitions" with different properties. +Finally, the open-source controller provides a high level of security for specific partitions by provisioning integrity digests for each partition, and scrambling of partitions where required. + +The proprietary IP on the other hand translates a common access interface to the technology-specific OTP interface, both for functional and debug accesses (for example register accesses to the macro-internal control structure). + +This split implies that every proprietary OTP IP must implement a translation layer from a standardized OpenTitan interface to the module underneath. +It also implies that no matter how the OTP storage or word size may change underneath, the open-source controller must present a consistent and coherent software and hardware interface. +This standardized interface is defined further below, and the wrapper leverages the same [technology primitive mechanism](../../../ip/prim/README.md) that is employed in other parts of OpenTitan in order to wrap and abstract technology-specific macros (such as memories and clocking cells) that are potentially closed-source. + +In order to enable simulation and FPGA emulation of the OTP controller even without access to the proprietary OTP IP, a generalized and synthesizable model of the OTP IP is provided in the form of a [OTP MACRO hardware IP](https://github.com/lowRISC/opentitan/blob/master/hw/ip/otp_macro/rtl/otp_macro.sv). diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/BUILD new file mode 100644 index 00000000000..ad8c79e8251 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/BUILD @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_otp_ctrl.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = glob([ + "otp_ctrl.hjson", + "*_testplan.hjson", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/dif_otp_ctrl.c.tpl.not_yet b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/dif_otp_ctrl.c.tpl.not_yet new file mode 100644 index 00000000000..766a1a333d5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/dif_otp_ctrl.c.tpl.not_yet @@ -0,0 +1,684 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +<% +from topgen.lib import Name + +parts = otp_mmap["partitions"] +digest_parts = [part for part in parts if + part["hw_digest"] or part["sw_digest"]] +read_locked_csr_parts = [part for part in parts if part["read_lock"] == "CSR"] +secret_parts = [part for part in parts if part["secret"]] +%>\ +#include "sw/device/lib/dif/dif_otp_ctrl.h" + +#include + +#include "sw/device/lib/base/bitfield.h" +#include "sw/device/lib/base/macros.h" +#include "sw/device/lib/dif/dif_base.h" + +#include "otp_ctrl_regs.h" // Generated. + +/** + * Checks if integrity/consistency-check-related operations are locked. + * + * This is a convenience function to avoid superfluous error-checking in all the + * functions that can be locked out by this register. + * + * @param check_config True to check the config regwen. False to check the + * trigger regwen. + */ +static bool checks_are_locked(const dif_otp_ctrl_t *otp, bool check_config) { + ptrdiff_t reg_offset = check_config + ? OTP_CTRL_CHECK_REGWEN_REG_OFFSET + : OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET; + size_t regwen_bit = + check_config ? OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT + : OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT; + uint32_t locked = mmio_region_read32(otp->base_addr, reg_offset); + return !bitfield_bit32_read(locked, regwen_bit); +} + +dif_result_t dif_otp_ctrl_configure(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_config_t config) { + if (otp == NULL) { + return kDifBadArg; + } + if (checks_are_locked(otp, /*check_config=*/true)) { + return kDifLocked; + } + + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_TIMEOUT_REG_OFFSET, + config.check_timeout); + mmio_region_write32(otp->base_addr, + OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_OFFSET, + config.integrity_period_mask); + mmio_region_write32(otp->base_addr, + OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_OFFSET, + config.consistency_period_mask); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_check_integrity(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + if (checks_are_locked(otp, /*check_config=*/false)) { + return kDifLocked; + } + + uint32_t reg = + bitfield_bit32_write(0, OTP_CTRL_CHECK_TRIGGER_INTEGRITY_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_TRIGGER_REG_OFFSET, reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_check_consistency(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + if (checks_are_locked(otp, /*check_config=*/false)) { + return kDifLocked; + } + + uint32_t reg = + bitfield_bit32_write(0, OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_TRIGGER_REG_OFFSET, reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_lock(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + + uint32_t reg = bitfield_bit32_write( + 0, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked) { + if (otp == NULL || is_locked == NULL) { + return kDifBadArg; + } + + uint32_t reg = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET); + *is_locked = !bitfield_bit32_read( + reg, OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_lock_config(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + + uint32_t reg = + bitfield_bit32_write(0, OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, false); + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_REGWEN_REG_OFFSET, reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_config_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked) { + if (otp == NULL || is_locked == NULL) { + return kDifBadArg; + } + + *is_locked = checks_are_locked(otp, /*check_config=*/true); + return kDifOk; +} + +dif_result_t dif_otp_ctrl_lock_check_trigger(const dif_otp_ctrl_t *otp) { + if (otp == NULL) { + return kDifBadArg; + } + + uint32_t reg = bitfield_bit32_write( + 0, OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, false); + mmio_region_write32(otp->base_addr, OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_check_trigger_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked) { + if (otp == NULL || is_locked == NULL) { + return kDifBadArg; + } + + *is_locked = checks_are_locked(otp, /*check_config=*/false); + return kDifOk; +} + +static bool sw_read_lock_reg_offset(dif_otp_ctrl_partition_t partition, + ptrdiff_t *reg_offset, + bitfield_bit32_index_t *index) { + switch (partition) { +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_define = part_name.as_c_define() + index_line = f"*index = OTP_CTRL_{part_name_define}_READ_LOCK_{part_name_define}_READ_LOCK_BIT;" +%>\ + case kDifOtpCtrlPartition${part_name.as_camel_case()}: + *reg_offset = OTP_CTRL_${part_name_define}_READ_LOCK_REG_OFFSET; + % if len(index_line) > 80 - 6: + *index = + OTP_CTRL_${part_name_define}_READ_LOCK_${part_name_define}_READ_LOCK_BIT; + % else: + ${index_line} + % endif + break; +% endfor + default: + return false; + } + return true; +} + +dif_result_t dif_otp_ctrl_lock_reading(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition) { + if (otp == NULL) { + return kDifBadArg; + } + + ptrdiff_t offset; + bitfield_bit32_index_t index; + if (!sw_read_lock_reg_offset(partition, &offset, &index)) { + return kDifBadArg; + } + + uint32_t reg = bitfield_bit32_write(0, index, false); + mmio_region_write32(otp->base_addr, offset, reg); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_reading_is_locked(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + bool *is_locked) { + if (otp == NULL || is_locked == NULL) { + return kDifBadArg; + } + + ptrdiff_t offset; + bitfield_bit32_index_t index; + if (!sw_read_lock_reg_offset(partition, &offset, &index)) { + return kDifBadArg; + } + + uint32_t reg = mmio_region_read32(otp->base_addr, offset); + *is_locked = !bitfield_bit32_read(reg, index); + return kDifOk; +} + +dif_result_t dif_otp_ctrl_get_status(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_status_t *status) { + if (otp == NULL || status == NULL) { + return kDifBadArg; + } + + static const bitfield_bit32_index_t kIndices[] = { +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + lhs = f'[kDifOtpCtrlStatusCode{part_name.as_camel_case()}Error]' + rhs = f'OTP_CTRL_STATUS_{part_name.as_c_define()}_ERROR_BIT' + line = f'{lhs} = {rhs},' +%>\ + % if len(line) > 80 - 6: + ${lhs} = + ${rhs}, + % else: + ${line} + % endif +% endfor + [kDifOtpCtrlStatusCodeDaiError] = OTP_CTRL_STATUS_DAI_ERROR_BIT, + [kDifOtpCtrlStatusCodeLciError] = OTP_CTRL_STATUS_LCI_ERROR_BIT, + [kDifOtpCtrlStatusCodeTimeoutError] = OTP_CTRL_STATUS_TIMEOUT_ERROR_BIT, + [kDifOtpCtrlStatusCodeLfsrError] = OTP_CTRL_STATUS_LFSR_FSM_ERROR_BIT, + [kDifOtpCtrlStatusCodeScramblingError] = + OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_BIT, + [kDifOtpCtrlStatusCodeKdfError] = OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_BIT, + [kDifOtpCtrlStatusCodeBusIntegError] = + OTP_CTRL_STATUS_BUS_INTEG_ERROR_BIT, + [kDifOtpCtrlStatusCodeDaiIdle] = OTP_CTRL_STATUS_DAI_IDLE_BIT, + [kDifOtpCtrlStatusCodeCheckPending] = OTP_CTRL_STATUS_CHECK_PENDING_BIT, + }; + + status->codes = 0; + uint32_t status_code = + mmio_region_read32(otp->base_addr, OTP_CTRL_STATUS_REG_OFFSET); + for (int i = 0; i < ARRAYSIZE(kIndices); ++i) { + // If the error is not present at all, we clear its cause bit if relevant, + // and bail immediately. + if (!bitfield_bit32_read(status_code, kIndices[i])) { + if (i <= kDifOtpCtrlStatusCodeHasCauseLast) { + status->causes[i] = kDifOtpCtrlErrorOk; + } + continue; + } + + status->codes = + bitfield_bit32_write(status->codes, (bitfield_bit32_index_t)i, true); + + if (i <= kDifOtpCtrlStatusCodeHasCauseLast) { + bitfield_field32_t field; + field = (bitfield_field32_t){ + .mask = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_MASK, + .index = OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET, + }; + + ptrdiff_t address = + OTP_CTRL_ERR_CODE_0_REG_OFFSET + i * (ptrdiff_t)sizeof(uint32_t); + uint32_t error_code = mmio_region_read32(otp->base_addr, address); + + dif_otp_ctrl_error_t err; + switch (bitfield_field32_read(error_code, field)) { + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_NO_ERROR: + err = kDifOtpCtrlErrorOk; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ERROR: + err = kDifOtpCtrlErrorMacroUnspecified; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR: + err = kDifOtpCtrlErrorMacroRecoverableRead; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_UNCORR_ERROR: + err = kDifOtpCtrlErrorMacroUnrecoverableRead; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_WRITE_BLANK_ERROR: + err = kDifOtpCtrlErrorMacroBlankCheckFailed; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_ACCESS_ERROR: + err = kDifOtpCtrlErrorLockedAccess; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_CHECK_FAIL_ERROR: + err = kDifOtpCtrlErrorBackgroundCheckFailed; + break; + case OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_FSM_STATE_ERROR: + err = kDifOtpCtrlErrorFsmBadState; + break; + default: + return kDifError; + } + status->causes[i] = err; + } + } + + return kDifOk; +} + +typedef struct partition_info { + /** + * The absolute OTP address at which this partition starts. + */ + uint32_t start_addr; + /** + * The length of this partition, in bytes, including the digest. + * + * If the partition has a digest, it is expected to be at address + * `start_addr + len - sizeof(uint64_t)`. + */ + uint32_t len; + /** + * The alignment mask for this partition. + * + * A valid address for this partition must be such that + * `addr & align_mask == 0`. + */ + uint32_t align_mask; + + /** + * Whether this is a software-managed partition with a software-managed + * digest. + */ + bool is_software; + + /** + * Whether this partition has a digest field. + */ + bool has_digest; + + /** + * Whether this partition is the lifecycle partition. + */ + bool is_lifecycle; +} partition_info_t; + +// This is generates too many lines with different formatting variants, so +// We opt to just disable formatting. +// clang-format off +static const partition_info_t kPartitions[] = { +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() + has_digest = part["hw_digest"] or part["sw_digest"] + is_lifecycle = part["variant"] == "LifeCycle" + is_software = part["variant"] == "Unbuffered" +%>\ + [kDifOtpCtrlPartition${part_name_camel}] = { + .start_addr = OTP_CTRL_PARAM_${part_name_define}_OFFSET, + .len = OTP_CTRL_PARAM_${part_name_define}_SIZE, + .align_mask = ${"0x7" if part in secret_parts else "0x3"}, + .is_software = ${"true" if is_software else "false"}, + .has_digest = ${"true" if has_digest else "false"}, + .is_lifecycle = ${"true" if is_lifecycle else "false"}}, +% endfor +}; +// clang-format on + +dif_result_t dif_otp_ctrl_relative_address(dif_otp_ctrl_partition_t partition, + uint32_t abs_address, + uint32_t *relative_address) { + *relative_address = 0; + + if (partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + if ((abs_address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + if (abs_address < kPartitions[partition].start_addr) { + return kDifOutOfRange; + } + + *relative_address = abs_address - kPartitions[partition].start_addr; + if (*relative_address >= kPartitions[partition].len) { + *relative_address = 0; + return kDifOutOfRange; + } + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_read_start(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + if ((address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + if (address >= kPartitions[partition].len) { + return kDifOutOfRange; + } + + address += kPartitions[partition].start_addr; + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + address); + + uint32_t cmd = + bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + cmd); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_read32_end(const dif_otp_ctrl_t *otp, + uint32_t *value) { + if (otp == NULL || value == NULL) { + return kDifBadArg; + } + + *value = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET); + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_read64_end(const dif_otp_ctrl_t *otp, + uint64_t *value) { + if (otp == NULL || value == NULL) { + return kDifBadArg; + } + + *value = mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_OFFSET); + *value <<= 32; + *value |= mmio_region_read32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET); + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_program32(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint32_t value) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + // Ensure that we are writing to a 32-bit-access partition by checking that + // the alignment mask is 0b11. + // + // Note furthermore that the LC partition is *not* writeable, so we eject + // here. + if (kPartitions[partition].align_mask != 0x3 || + kPartitions[partition].is_lifecycle) { + return kDifError; + } + + if ((address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + // NOTE: The bounds check is tightened here, since we disallow writing the + // digest directly. If the partition does not have a digest, no tightening is + // needed. + size_t digest_size = kPartitions[partition].has_digest * sizeof(uint64_t); + if (address >= kPartitions[partition].len - digest_size) { + return kDifOutOfRange; + } + + address += kPartitions[partition].start_addr; + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + address); + + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, + value); + + uint32_t cmd = + bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + cmd); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_program64(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint64_t value) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + // Ensure that we are writing to a 64-bit-access partition by checking that + // the alignment mask is 0b111. + if (kPartitions[partition].align_mask != 0x7) { + return kDifError; + } + + if ((address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + // NOTE: The bounds check is tightened here, since we disallow writing the + // digest directly. + size_t digest_size = sizeof(uint64_t); + if (address >= kPartitions[partition].len - digest_size) { + return kDifOutOfRange; + } + + address += kPartitions[partition].start_addr; + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + address); + + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, + value & UINT32_MAX); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, + value >> 32); + + uint32_t cmd = + bitfield_bit32_write(0, OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + cmd); + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_dai_digest(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint64_t digest) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions)) { + return kDifBadArg; + } + + // Not all partitions have a digest. + if (!kPartitions[partition].has_digest) { + return kDifError; + } + + // For software partitions, the digest must be nonzero; for all other + // partitions it must be zero. + bool is_sw = kPartitions[partition].is_software; + if (is_sw == (digest == 0)) { + return kDifBadArg; + } + + uint32_t address = kPartitions[partition].start_addr; + if (is_sw) { + address += kPartitions[partition].len - sizeof(digest); + } + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + address); + + if (digest != 0) { + mmio_region_write32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, + digest & 0xffffffff); + mmio_region_write32(otp->base_addr, + OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, + digest >> 32); + } + + bitfield_bit32_index_t cmd_bit = is_sw + ? OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT + : OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_BIT; + uint32_t cmd = bitfield_bit32_write(0, cmd_bit, true); + mmio_region_write32(otp->base_addr, OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + cmd); + + return kDifOk; +} + +static bool get_digest_regs(dif_otp_ctrl_partition_t partition, ptrdiff_t *reg0, + ptrdiff_t *reg1) { + switch (partition) { +% for part in digest_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_define = part_name.as_c_define() +%>\ + case kDifOtpCtrlPartition${part_name.as_camel_case()}: + *reg0 = OTP_CTRL_${part_name_define}_DIGEST_0_REG_OFFSET; + *reg1 = OTP_CTRL_${part_name_define}_DIGEST_1_REG_OFFSET; + break; +% endfor + default: + return false; + } + + return true; +} + +dif_result_t dif_otp_ctrl_is_digest_computed(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + bool *is_computed) { + if (otp == NULL || is_computed == NULL) { + return kDifBadArg; + } + + ptrdiff_t reg0, reg1; + if (!get_digest_regs(partition, ®0, ®1)) { + return kDifBadArg; + } + + uint64_t value = mmio_region_read32(otp->base_addr, reg1); + value <<= 32; + value |= mmio_region_read32(otp->base_addr, reg0); + + *is_computed = value != 0; + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_get_digest(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint64_t *digest) { + if (otp == NULL || digest == NULL) { + return kDifBadArg; + } + + ptrdiff_t reg0, reg1; + if (!get_digest_regs(partition, ®0, ®1)) { + return kDifBadArg; + } + + uint64_t value = mmio_region_read32(otp->base_addr, reg1); + value <<= 32; + value |= mmio_region_read32(otp->base_addr, reg0); + + if (value == 0) { + return kDifError; + } + *digest = value; + + return kDifOk; +} + +dif_result_t dif_otp_ctrl_read_blocking(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint32_t *buf, + size_t len) { + if (otp == NULL || partition >= ARRAYSIZE(kPartitions) || buf == NULL) { + return kDifBadArg; + } + + if (!kPartitions[partition].is_software) { + return kDifError; + } + + if ((address & kPartitions[partition].align_mask) != 0) { + return kDifUnaligned; + } + + if (address + len >= kPartitions[partition].len) { + return kDifOutOfRange; + } + + uint32_t reg_offset = OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET + + kPartitions[partition].start_addr + address; + mmio_region_memcpy_from_mmio32(otp->base_addr, reg_offset, buf, + len * sizeof(uint32_t)); + return kDifOk; +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/dif_otp_ctrl.h.tpl.not_yet b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/dif_otp_ctrl.h.tpl.not_yet new file mode 100644 index 00000000000..33ee5180042 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/dif_otp_ctrl.h.tpl.not_yet @@ -0,0 +1,613 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +<% +from topgen.lib import Name + +parts = otp_mmap["partitions"] +digest_parts = [part for part in parts if + part["hw_digest"] == "true" or part["sw_digest"] == "true"] +read_locked_csr_parts = [part for part in parts if part["read_lock"] == "CSR"] +secret_parts = [part for part in parts if part["secret"] == "true"] +%>\ +#ifndef OPENTITAN_SW_DEVICE_LIB_DIF_DIF_OTP_CTRL_H_ +#define OPENTITAN_SW_DEVICE_LIB_DIF_DIF_OTP_CTRL_H_ + +/** + * @file + * @brief + * OTP Controller Device Interface Functions + */ + +#include + +#include "sw/device/lib/base/macros.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/dif_base.h" + +#include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h" + +// Header Extern Guard (so header can be used from C and C++) +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/** + * A partition within OTP memory. + */ +typedef enum dif_otp_ctrl_partition { +% for part in parts: +<% + part_name_camel = Name.to_camel_case(part["name"]) + short_desc = part["desc"].split(".")[0].strip().replace("\n", " ") + long_desc_lines = part["desc"].split(".", 1)[1].strip().splitlines() + long_desc = "\n".join([" *" + (" " if line else "") + line for + line in long_desc_lines]) +%>\ + /** + * ${short_desc}. + * + % if long_desc: +${long_desc} + %endif + */ + kDifOtpCtrlPartition${part_name_camel}, +% endfor +} dif_otp_ctrl_partition_t; + +/** + * Runtime configuration for OTP. + * + * This struct describes runtime information for one-time configuration of the + * hardware. + */ +typedef struct dif_otp_ctrl_config { + /** + * The timeout for an integrity or consistency check to succeed, in cycles. + * + * 100'000 is recommended as a minimum safe value. + */ + uint32_t check_timeout; + /** + * A mask for the pseudo-random integrity check period. + * + * The value of this mask limits the period of the integrity check; when the + * pseudo-random period is computed, this mask is applied to limit it. For + * example, a value of 0x3'ffff would correspond to a maximum period of about + * 2.8s at 24MHz. + * + * A value of zero disables the check. + */ + uint32_t integrity_period_mask; + /** + * A mask for the pseudo-random consistency check period. + * + * The value of this mask limits the period of the consistency check; when the + * pseudo-random period is computed, this mask is applied to limit it. For + * example, a value of 0x3ff'ffff would correspond to a maximum period of + * about 716s at 24MHz. + * + * A value of zero disables the check. + */ + uint32_t consistency_period_mask; +} dif_otp_ctrl_config_t; + +/** + * A hardware-level status code. + */ +typedef enum dif_otp_ctrl_status_code { + // NOTE: This enum's API *requires* that all "error"-like codes (that is, + // those which have associated cause registers) be a prefix of the enum + // values. + // + // Note furthermore that these enum variants are intended as bit indices, so + // their values should not be randomized. +% for part in parts: +<% + part_name_camel = Name.to_camel_case(part["name"]) +%>\ + /** + * Indicates an error occurred in the `${part_name_camel}` partition. + */ + kDifOtpCtrlStatusCode${part_name_camel}Error${" = 0" if loop.first else ""}, +% endfor + /** + * Indicates an error occurred in the direct access interface. + */ + kDifOtpCtrlStatusCodeDaiError, + /** + * Indicates an error occurred in the lifecycle interface. + */ + kDifOtpCtrlStatusCodeLciError, + /** + * This is not a status code; rather, it represents the last error code which + * has a corresponding "cause" register. + * + * See `dif_otp_ctrl_status_t` for information on how to use this. + */ + kDifOtpCtrlStatusCodeHasCauseLast = kDifOtpCtrlStatusCodeLciError, + /** + * Indicates that an integrity or consistency check has timed out. + * + * This error is unrecoverable. + */ + kDifOtpCtrlStatusCodeTimeoutError, + /** + * Indicates that the LFSR that generates pseudo-random integrity and + * consistency checks is in a bad state. + * + * This error is unrecoverable. + */ + kDifOtpCtrlStatusCodeLfsrError, + /** + * Indicates that the scrambling hardware is in a bad state. + * + * This error is unrecoverable. + */ + kDifOtpCtrlStatusCodeScramblingError, + /** + * Indicates that the key derivation hardware is in a bad state. + * + * This error is unrecoverable. + */ + kDifOtpCtrlStatusCodeKdfError, + /** + * Indicates a bus integrity error. + * + * This error will raise an alert. + */ + kDifOtpCtrlStatusCodeBusIntegError, + /** + * Indicates that the direct access interface is idle. + */ + kDifOtpCtrlStatusCodeDaiIdle, + /** + * Indicates that an integrity or consistency check is currently pending. + */ + kDifOtpCtrlStatusCodeCheckPending, +} dif_otp_ctrl_status_code_t; + +/** + * A hardware-level error code, associated with a particular error defined in + * `dif_otp_ctrl_status_t`. + */ +typedef enum dif_otp_ctrl_error { + /** + * Indicates no error. + */ + kDifOtpCtrlErrorOk, + /** + * Indicates that an OTP macro command was invalid or did not + * complete successfully. + * + * This error indicates non-recoverable hardware malfunction. + */ + kDifOtpCtrlErrorMacroUnspecified, + /** + * Indicates a recoverable error during a read operation. + * + * A followup read should work as expected. + */ + kDifOtpCtrlErrorMacroRecoverableRead, + /** + * Indicates an unrecoverable error during a read operation. + * + * This error indicates non-recoverable hardware malfunction. + */ + kDifOtpCtrlErrorMacroUnrecoverableRead, + /** + * Indicates that the blank write check failed during a write operation. + */ + kDifOtpCtrlErrorMacroBlankCheckFailed, + /** + * Indicates a locked memory region was accessed. + */ + kDifOtpCtrlErrorLockedAccess, + /** + * Indicates a parity, integrity or consistency check failed in the buffer + * registers. + * + * This error indicates non-recoverable hardware malfunction. + */ + kDifOtpCtrlErrorBackgroundCheckFailed, + /** + * Indicates that the FSM of the controller is in a bad state or that the + * controller's FSM has been moved into its terminal state due to escalation + * via the alert subsystem. + * + * This error indicates that the device has been glitched by an attacker. + */ + kDifOtpCtrlErrorFsmBadState, +} dif_otp_ctrl_error_t; + +/** + * The overall status of the OTP controller. + * + * See `dif_otp_ctrl_get_status()`. + */ +typedef struct dif_otp_ctrl_status { + /** + * Currently active statuses, given as a bit vector. To check whether a + * particular status code was returned, write + * + * bool has_code = (status.codes >> kMyStatusCode) & 1; + * + * Note that it is possible to quickly check that the controller is idle and + * error-free by writing + * + * bool is_ok = status.codes == (1 << kDifOtpStatusCodeDaiIdle); + */ + uint32_t codes; + /** + * A list of root causes for each error status code. + * + * If the error status code `error` is present in `codes`, and + * `error <= kDifOtpCtrlStatusCodeHasCauseLast`, then `causes[error]` + * will contain its root cause. + */ + dif_otp_ctrl_error_t causes[kDifOtpCtrlStatusCodeHasCauseLast + 1]; +} dif_otp_ctrl_status_t; + +/** + * Configures OTP with runtime information. + * + * This function should need to be called at most once for the lifetime of + * `otp`. + * + * @param otp An OTP handle. + * @param config Runtime configuration parameters. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_configure(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_config_t config); + +/** + * Runs an integrity check on the OTP hardware. + * + * This function can be used to trigger an integrity check independent of the + * pseudo-random hardware-generated checks. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_check_integrity(const dif_otp_ctrl_t *otp); + +/** + * Runs a consistency check on the OTP hardware. + * + * This function can be used to trigger a consistency check independent of the + * pseudo-random hardware-generated checks. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_check_consistency(const dif_otp_ctrl_t *otp); + +/** + * Locks out access to the direct access interface registers. + * + * This function is idempotent: calling it while functionality is locked will + * have no effect and return `kDifOk`. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_lock(const dif_otp_ctrl_t *otp); + +/** + * Checks whether access to the direct access interface is locked. + * + * Note that besides locking the DAI out until the next reset using the + * dif_otp_ctrl_dai_lock function, the DAI is also temporarily locked by the + * HW itself when it is busy processing a DAI command. In such a case, the + * kDifOtpCtrlStatusCodeDaiIdle status bit will be set to 0 as well. + * + * @param otp An OTP handle. + * @param[out] is_locked Out-param for the locked state. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked); + +/** + * Locks out `dif_otp_ctrl_configure()` function. + * + * This function is idempotent: calling it while functionality is locked will + * have no effect and return `kDifOk`. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_lock_config(const dif_otp_ctrl_t *otp); + +/** + * Checks whether `dif_otp_ctrl_configure()` function is locked-out. + * + * @param otp An OTP handle. + * @param[out] is_locked Out-param for the locked state. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_config_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked); + +/** + * Locks out `dif_otp_ctrl_check_*()` functions. + * + * This function is idempotent: calling it while functionality is locked will + * have no effect and return `kDifOk`. + * + * @param otp An OTP handle. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_lock_check_trigger(const dif_otp_ctrl_t *otp); + +/** + * Checks whether the `dif_otp_ctrl_check_*()` functions are locked-out. + * + * @param otp An OTP handle. + * @param[out] is_locked Out-param for the locked state. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_check_trigger_is_locked(const dif_otp_ctrl_t *otp, + bool *is_locked); + +/** + * Locks out reads to a SW partition. + * + * This function should only be called on SW partitions; doing otherwise will + * return an error. + * + * Note that this is distinct from the write-locking performed by calling + * `dif_otp_ctrl_dai_digest()`. In particular, the effects of this function will + * not persist past a system reset. + * + * This function is idempotent: calling it while functionality is locked will + * have no effect and return `kDifOk`. + * + * @param otp An OTP handle. + * @param partition The SW partition to lock. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_lock_reading(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition); + +/** + * Checks whether reads to a SW partition are locked out. + * + * This function should only be called on SW partitions; doing otherwise will + * return an error. + * + * @param otp An OTP handle. + * @param partition the SW partition to check for locking. + * @param[out] is_locked Out-param for the locked state. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_reading_is_locked(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + bool *is_locked); + +/** + * Gets the current status of the OTP controller. + * + * @param otp An OTP handle. + * @param[out] status Out-param for the controller's status. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_get_status(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_status_t *status); + +/** + * Calculates a `relative_address` with respect to a `partition` start + * address. + * + * @param partition The partition to use to calculate the reference start + * address. + * @param abs_address Input address relative to the OTP memory start address. + * @param[out] relative_address The result relative address with respect to the + * `partition` start address. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_relative_address(dif_otp_ctrl_partition_t partition, + uint32_t abs_address, + uint32_t *relative_address); + +/** + * Schedules a read on the Direct Access Interface. + * + * Reads are performed relative to a partition; `address` should be given + * relative to the start of `partition`. An error is returned for out-of-bounds + * access. + * + * Furthermore, `address` must be well-aligned: it must be four-byte aligned for + * normal partitions and eight-byte-aligned for secret partitions. An error is + * returned for unaligned access. + * + * @param otp An OTP handle. + * @param partition The partition to read from. + * @param address A partition-relative address to read from. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_read_start(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address); + +/** + * Gets the result of a completed 32-bit read operation on the Direct Access + * Interface. + * + * Whether this function or its 64-bit variant should be called is dependent on + * the most recent partition read from. + * + * @param otp An OTP handle. + * @param[out] value Out-param for the read value. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_read32_end(const dif_otp_ctrl_t *otp, + uint32_t *value); + +/** + * Gets the result of a completed 64-bit read operation on the Direct Access + * Interface. + * + * Whether this function or its 32-bit variant should be called is dependent on + * the most recent partition read from. + * + * @param otp An OTP handle. + * @param[out] value Out-param for the read value. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_read64_end(const dif_otp_ctrl_t *otp, + uint64_t *value); + +/** + * Schedules a 32-bit write on the Direct Access Interface. + * + * Writes are performed relative to a partition; `address` should be given + * relative to the start of `partition`. An error is returned for out-of-bounds + * access. + * + * Furthermore, `address` must be four-byte-aligned, and `partition` must not be + * a secret partition. An error is returned if neither condition is met. + * + * Note that this function cannot be used to program the digest at the end of a + * `SW` partition; `dif_otp_ctrl_dai_digest()` must be used instead. + * + * @param otp An OTP handle. + * @param partition The partition to program. + * @param address A partition-relative address to program. + * @param value The value to program into the OTP. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_program32(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint32_t value); + +/** + * Schedules a 64-bit write on the Direct Access Interface. + * + * Writes are performed relative to a partition; `address` should be given + * relative to the start of `partition`. An error is returned for out-of-bounds + * access. + * + * Furthermore, `address` must be eight-byte-aligned, and `partition` must be + * a secret partition. An error is returned if neither condition is met. + * + * @param otp An OTP handle. + * @param partition The partition to program. + * @param address A partition-relative address to program. + * @param value The value to program into the OTP. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_program64(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint64_t value); + +/** + * Schedules a hardware digest operation on the Direct Access Interface. + * + * **This operation will also lock writes for the given partition.** + * + * If `partition` is a SW partition, `digest` must be non-zero; if it is a + * partition with a hardware-managed digest, `digest` *must* be zero (since the + * digest will be generated by the hardware). An error is returned if either + * precondition is not met. + * + * This function does not work with the lifecycle state partition, and will + * return an error in that case. + * + * @param otp An OTP handle. + * @param partition The partition to digest and lock. + * @param digest The digest to program (for SW partitions). + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_dai_digest(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint64_t digest); + +/** + * Checks if the digest value for the given partition has been computed. Once a + * digest has been computed for a partition, the partition is write-locked + * (additionally, read-locked if the partition is secret). + * + * The lifecycle partition does not have a digest, and checking if this region + * has a computed digest will return an error. + * + * @param otp An OTP handle. + * @param partition The partition to check the digest of. + * @param[out] is_computed Indicates if the digest has been computed. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_is_digest_computed(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + bool *is_computed); + +/** + * Gets the buffered digest value for the given partition. + * + * Note that this value is only updated when the device is reset; if the digest + * has not been computed yet, or has been computed but not since device reset, + * this function will return an error. + * + * The lifecycle partition does not have a digest and will result in an error + * being returned. + * + * @param otp An OTP handle. + * @param partition The partition to get a digest for. + * @param[out] digest Out-param for the digest. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_get_digest(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint64_t *digest); + +/** + * Performs a memory-mapped read of the given partition, if it supports them. + * + * In particular, this function will read `len` words, starting at `address`, + * relative to the start of `partition`. + * + * The same caveats for `dif_otp_ctrl_dai_read_start()` apply to `address`; in + * addition, `address + len` must also be in-range and must not overflow. + * + * This function will block until the read completes, unlike Direct Access + * Interface functions. + * + * @param otp An OTP handle. + * @param partition The partition to read from. + * @param address A partition-relative address to read from. + * @param[out] buf A buffer of words to write read values to. + * @param len The number of words to read. + * @return The result of the operation. + */ +OT_WARN_UNUSED_RESULT +dif_result_t dif_otp_ctrl_read_blocking(const dif_otp_ctrl_t *otp, + dif_otp_ctrl_partition_t partition, + uint32_t address, uint32_t *buf, + size_t len); + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // OPENTITAN_SW_DEVICE_LIB_DIF_DIF_OTP_CTRL_H_ diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/dif_otp_ctrl_unittest.cc.tpl.not_yet b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/dif_otp_ctrl_unittest.cc.tpl.not_yet new file mode 100644 index 00000000000..8f1a8e99005 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/dif_otp_ctrl_unittest.cc.tpl.not_yet @@ -0,0 +1,787 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +<% +from topgen.lib import Name + +parts = otp_mmap["partitions"] +digest_parts = [part for part in parts if + part["hw_digest"] or part["sw_digest"]] +hw_digest_parts = [part for part in parts if part["hw_digest"]] +sw_digest_parts = [part for part in parts if part["sw_digest"]] +read_locked_csr_parts = [part for part in parts if part["read_lock"] == "CSR"] +secret_parts = [part for part in parts if part["secret"]] +%>\ +#include "sw/device/lib/dif/dif_otp_ctrl.h" + +#include +#include +#include + +#include "gtest/gtest.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/base/mock_mmio.h" +#include "sw/device/lib/dif/dif_test_base.h" + +#include "otp_ctrl_regs.h" // Generated. + +namespace dif_otp_ctrl_unittest { +namespace { +using ::mock_mmio::LeInt; +using ::mock_mmio::MmioTest; +using ::mock_mmio::MockDevice; +using ::testing::Each; +using ::testing::ElementsAre; + +class OtpTest : public testing::Test, public MmioTest { + protected: + dif_otp_ctrl_t otp_ = {.base_addr = dev().region()}; +}; + +class DaiRegwenTest : public OtpTest {}; + +TEST_F(DaiRegwenTest, LockDai) { + EXPECT_WRITE32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_dai_lock(&otp_)); +} + +TEST_F(DaiRegwenTest, IsDaiLocked) { + bool flag; + + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, true}}); + EXPECT_DIF_OK(dif_otp_ctrl_dai_is_locked(&otp_, &flag)); + EXPECT_FALSE(flag); + + EXPECT_READ32( + OTP_CTRL_DIRECT_ACCESS_REGWEN_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_dai_is_locked(&otp_, &flag)); + EXPECT_TRUE(flag); +} + +TEST_F(DaiRegwenTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_lock(nullptr)); + + bool flag; + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_is_locked(nullptr, &flag)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_is_locked(&otp_, nullptr)); +} + +class ConfigTest : public OtpTest {}; + +TEST_F(ConfigTest, Basic) { + dif_otp_ctrl_config_t config = { + .check_timeout = 100'000, + .integrity_period_mask = 0x3'ffff, + .consistency_period_mask = 0x3ff'ffff, + }; + + EXPECT_READ32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, true}}); + + EXPECT_WRITE32(OTP_CTRL_CHECK_TIMEOUT_REG_OFFSET, config.check_timeout); + EXPECT_WRITE32(OTP_CTRL_INTEGRITY_CHECK_PERIOD_REG_OFFSET, + config.integrity_period_mask); + EXPECT_WRITE32(OTP_CTRL_CONSISTENCY_CHECK_PERIOD_REG_OFFSET, + config.consistency_period_mask); + + EXPECT_DIF_OK(dif_otp_ctrl_configure(&otp_, config)); +} + +TEST_F(ConfigTest, Locked) { + EXPECT_READ32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, false}}); + + EXPECT_EQ(dif_otp_ctrl_configure(&otp_, {}), kDifLocked); +} + +TEST_F(ConfigTest, IsConfigLocked) { + bool flag; + + EXPECT_READ32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, true}}); + EXPECT_DIF_OK(dif_otp_ctrl_config_is_locked(&otp_, &flag)); + EXPECT_FALSE(flag); + + EXPECT_READ32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_config_is_locked(&otp_, &flag)); + EXPECT_TRUE(flag); +} + +TEST_F(ConfigTest, LockConfig) { + EXPECT_WRITE32(OTP_CTRL_CHECK_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_REGWEN_CHECK_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_lock_config(&otp_)); +} + +TEST_F(ConfigTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_configure(nullptr, {})); + + bool flag; + EXPECT_DIF_BADARG(dif_otp_ctrl_config_is_locked(nullptr, &flag)); + EXPECT_DIF_BADARG(dif_otp_ctrl_config_is_locked(&otp_, nullptr)); + + EXPECT_DIF_BADARG(dif_otp_ctrl_lock_config(nullptr)); +} + +class CheckTest : public OtpTest {}; + +TEST_F(CheckTest, Integrity) { + EXPECT_READ32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_CHECK_TRIGGER_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_INTEGRITY_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_check_integrity(&otp_)); +} + +TEST_F(CheckTest, Consistency) { + EXPECT_READ32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, true}}); + EXPECT_WRITE32(OTP_CTRL_CHECK_TRIGGER_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_check_consistency(&otp_)); +} + +TEST_F(CheckTest, LockTrigger) { + EXPECT_WRITE32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, false}}); + EXPECT_DIF_OK(dif_otp_ctrl_lock_check_trigger(&otp_)); +} + +TEST_F(CheckTest, Locked) { + EXPECT_READ32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, false}}); + EXPECT_EQ(dif_otp_ctrl_check_integrity(&otp_), kDifLocked); + + EXPECT_READ32( + OTP_CTRL_CHECK_TRIGGER_REGWEN_REG_OFFSET, + {{OTP_CTRL_CHECK_TRIGGER_REGWEN_CHECK_TRIGGER_REGWEN_BIT, false}}); + EXPECT_EQ(dif_otp_ctrl_check_consistency(&otp_), kDifLocked); +} + +TEST_F(CheckTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_check_integrity(nullptr)); + EXPECT_DIF_BADARG(dif_otp_ctrl_check_consistency(nullptr)); +} + +class ReadLockTest : public OtpTest {}; + +// Too many formatting variants in template code, so disabling clang-format. +// clang-format off +TEST_F(ReadLockTest, IsLocked) { + bool flag; + +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() +%>\ + EXPECT_READ32( + OTP_CTRL_${part_name_define}_READ_LOCK_REG_OFFSET, + {{OTP_CTRL_${part_name_define}_READ_LOCK_${part_name_define}_READ_LOCK_BIT, + true}}); + EXPECT_DIF_OK(dif_otp_ctrl_reading_is_locked( + &otp_, kDifOtpCtrlPartition${part_name_camel}, &flag)); + EXPECT_FALSE(flag); + + EXPECT_READ32( + OTP_CTRL_${part_name_define}_READ_LOCK_REG_OFFSET, + {{OTP_CTRL_${part_name_define}_READ_LOCK_${part_name_define}_READ_LOCK_BIT, + false}}); + EXPECT_DIF_OK(dif_otp_ctrl_reading_is_locked( + &otp_, kDifOtpCtrlPartition${part_name_camel}, &flag)); + EXPECT_TRUE(flag); + % if not loop.last: + + %endif +% endfor +} + +TEST_F(ReadLockTest, Lock) { +% for part in read_locked_csr_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() +%>\ + EXPECT_WRITE32( + OTP_CTRL_${part_name_define}_READ_LOCK_REG_OFFSET, + {{OTP_CTRL_${part_name_define}_READ_LOCK_${part_name_define}_READ_LOCK_BIT, + false}}); + EXPECT_DIF_OK(dif_otp_ctrl_lock_reading( + &otp_, kDifOtpCtrlPartition${part_name_camel})); + % if not loop.last: + + %endif +% endfor +} + +TEST_F(ReadLockTest, NotLockablePartitions) { + bool flag; +% for part in [p for p in parts if p not in read_locked_csr_parts]: +<% + part_name_camel = Name.to_camel_case(part["name"]) +%>\ + EXPECT_DIF_BADARG( + dif_otp_ctrl_lock_reading(&otp_, kDifOtpCtrlPartition${part_name_camel})); + EXPECT_DIF_BADARG(dif_otp_ctrl_reading_is_locked( + &otp_, kDifOtpCtrlPartition${part_name_camel}, &flag)); + % if not loop.last: + + %endif +% endfor +} +// clang-format on + +TEST_F(ReadLockTest, NullArgs) { + bool flag; +% for part in read_locked_csr_parts: +<% + part_name_camel = Name.to_camel_case(part["name"]) + lock_reading_line = f"dif_otp_ctrl_lock_reading(nullptr, kDifOtpCtrlPartition{part_name_camel}));" +%>\ + EXPECT_DIF_BADARG(dif_otp_ctrl_reading_is_locked( + nullptr, kDifOtpCtrlPartition${part_name_camel}, &flag)); + EXPECT_DIF_BADARG(dif_otp_ctrl_reading_is_locked( + &otp_, kDifOtpCtrlPartition${part_name_camel}, nullptr)); + % if len(lock_reading_line) > 80 - 6: + EXPECT_DIF_BADARG(dif_otp_ctrl_lock_reading( + nullptr, kDifOtpCtrlPartition${part_name_camel})); + % else: + EXPECT_DIF_BADARG( + ${lock_reading_line} + % endif + % if not loop.last: + + %endif +% endfor +} + +class StatusTest : public OtpTest {}; + +TEST_F(StatusTest, Idle) { + dif_otp_ctrl_status_t status; + + EXPECT_READ32(OTP_CTRL_STATUS_REG_OFFSET, + {{OTP_CTRL_STATUS_DAI_IDLE_BIT, true}}); + EXPECT_DIF_OK(dif_otp_ctrl_get_status(&otp_, &status)); + + EXPECT_EQ(status.codes, 1 << kDifOtpCtrlStatusCodeDaiIdle); + EXPECT_THAT(status.causes, Each(kDifOtpCtrlErrorOk)); +} + +TEST_F(StatusTest, Errors) { + dif_otp_ctrl_status_t status; + + EXPECT_READ32(OTP_CTRL_STATUS_REG_OFFSET, + { + {OTP_CTRL_STATUS_DAI_IDLE_BIT, true}, + {OTP_CTRL_STATUS_HW_CFG0_ERROR_BIT, true}, + {OTP_CTRL_STATUS_LCI_ERROR_BIT, true}, + }); + +<% + hw_cfg0_error_index = [i for i, p in enumerate(parts) + if p["name"] == "HW_CFG0"][0] + lci_error_index = len(parts) + 1 +%>\ + EXPECT_READ32(OTP_CTRL_ERR_CODE_${hw_cfg0_error_index}_REG_OFFSET, + {{OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET, + OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ECC_CORR_ERROR}}); + EXPECT_READ32(OTP_CTRL_ERR_CODE_${lci_error_index}_REG_OFFSET, + {{OTP_CTRL_ERR_CODE_0_ERR_CODE_0_OFFSET, + OTP_CTRL_ERR_CODE_0_ERR_CODE_0_VALUE_MACRO_ERROR}}); + + EXPECT_DIF_OK(dif_otp_ctrl_get_status(&otp_, &status)); + EXPECT_EQ(status.codes, (1 << kDifOtpCtrlStatusCodeDaiIdle) | + (1 << kDifOtpCtrlStatusCodeHwCfg0Error) | + (1 << kDifOtpCtrlStatusCodeLciError)); + EXPECT_EQ(status.causes[kDifOtpCtrlStatusCodeHwCfg0Error], + kDifOtpCtrlErrorMacroRecoverableRead); + EXPECT_EQ(status.causes[kDifOtpCtrlStatusCodeLciError], + kDifOtpCtrlErrorMacroUnspecified); +} + +TEST_F(StatusTest, NullArgs) { + dif_otp_ctrl_status_t status; + + EXPECT_DIF_BADARG(dif_otp_ctrl_get_status(nullptr, &status)); + EXPECT_DIF_BADARG(dif_otp_ctrl_get_status(&otp_, nullptr)); +} + +struct RelativeAddressParams { + std::string name; + dif_otp_ctrl_partition_t partition; + uint32_t abs_address; + dif_result_t expected_result; + uint32_t expected_relative_address; +}; + +class RelativeAddress + : public OtpTest, + public testing::WithParamInterface {}; + +TEST_P(RelativeAddress, RelativeAddress) { + uint32_t got_relative_address; + dif_result_t got_result = dif_otp_ctrl_relative_address( + GetParam().partition, GetParam().abs_address, &got_relative_address); + EXPECT_EQ(got_result, GetParam().expected_result); + EXPECT_EQ(got_relative_address, GetParam().expected_relative_address); +} + +INSTANTIATE_TEST_SUITE_P( + AllPartitions, RelativeAddress, + testing::Values( +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() + step = 8 if part["secret"] else 4 +%>\ + RelativeAddressParams{ + "${part_name_camel}Okay", + kDifOtpCtrlPartition${part_name_camel}, + OTP_CTRL_PARAM_${part_name_define}_OFFSET + ${step}, + kDifOk, + ${step}, + }, + RelativeAddressParams{ + "${part_name_camel}Unaligned", + kDifOtpCtrlPartition${part_name_camel}, + OTP_CTRL_PARAM_${part_name_define}_OFFSET + 1, + kDifUnaligned, + 0, + }, +<% + ## Exclude first partition to avoid a negative offset. +%>\ + % if not loop.first: + RelativeAddressParams{ + "${part_name_camel}OutOfRangeBeforeStart", + kDifOtpCtrlPartition${part_name_camel}, + OTP_CTRL_PARAM_${part_name_define}_OFFSET - ${step}, + kDifOutOfRange, + 0, + }, + % endif + RelativeAddressParams{ + "${part_name_camel}OutOfRangePastEnd", + kDifOtpCtrlPartition${part_name_camel}, + % if len(f"OTP_CTRL_PARAM_{part_name_define}_OFFSET + OTP_CTRL_PARAM_{part_name_define}_SIZE,") <= 80 - 12: + OTP_CTRL_PARAM_${part_name_define}_OFFSET + OTP_CTRL_PARAM_${part_name_define}_SIZE, + % else: + OTP_CTRL_PARAM_${part_name_define}_OFFSET + + OTP_CTRL_PARAM_${part_name_define}_SIZE, + % endif + kDifOutOfRange, + 0, + }${")," if loop.last else ","} +% endfor + [](const testing::TestParamInfo &info) { + return info.param.name; + }); + +class DaiReadTest : public OtpTest {}; + +TEST_F(DaiReadTest, Read32) { + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_MANUF_STATE_OFFSET); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x20)); + + EXPECT_READ32(OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET, 0x12345678); + + uint32_t val; + EXPECT_DIF_OK(dif_otp_ctrl_dai_read32_end(&otp_, &val)); + EXPECT_EQ(val, 0x12345678); +} + +TEST_F(DaiReadTest, Read64) { + uint64_t val; +% for part in secret_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() +%>\ + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_${part_name_define}_OFFSET + 0x8); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_RD_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartition${part_name_camel}, + /*address=*/0x8)); + + EXPECT_READ32(OTP_CTRL_DIRECT_ACCESS_RDATA_1_REG_OFFSET, 0x12345678); + EXPECT_READ32(OTP_CTRL_DIRECT_ACCESS_RDATA_0_REG_OFFSET, 0x90abcdef); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_read64_end(&otp_, &val)); + EXPECT_EQ(val, 0x1234567890abcdef); + % if not loop.last: + + % endif +% endfor +} + +TEST_F(DaiReadTest, Unaligned) { + EXPECT_EQ(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0b01), + kDifUnaligned); + EXPECT_EQ(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionSecret2, + /*address=*/0b100), + kDifUnaligned); +} + +TEST_F(DaiReadTest, OutOfRange) { + EXPECT_EQ(dif_otp_ctrl_dai_read_start(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x100), + kDifOutOfRange); +} + +TEST_F(DaiReadTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read_start(nullptr, + kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x0)); + + uint32_t val32; + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read32_end(nullptr, &val32)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read32_end(&otp_, nullptr)); + + uint64_t val64; + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read64_end(nullptr, &val64)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_read64_end(&otp_, nullptr)); +} + +class DaiProgramTest : public OtpTest {}; + +TEST_F(DaiProgramTest, Program32) { + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_MANUF_STATE_OFFSET); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, 0x12345678); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x20, + /*value=*/0x12345678)); +} + +TEST_F(DaiProgramTest, Program64) { + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_SECRET2_OFFSET + 0x8); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, 0x90abcdef); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, 0x12345678); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_program64(&otp_, kDifOtpCtrlPartitionSecret2, + /*address=*/0x8, + /*value=*/0x1234567890abcdef)); +} + +TEST_F(DaiProgramTest, BadPartition) { + EXPECT_EQ(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionSecret1, + /*address=*/0x0, /*value=*/42), + kDifError); + EXPECT_EQ(dif_otp_ctrl_dai_program64(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x0, /*value=*/42), + kDifError); + + // LC is never writeable. + EXPECT_EQ(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionLifeCycle, + /*address=*/0x0, /*value=*/42), + kDifError); +} + +TEST_F(DaiProgramTest, Unaligned) { + EXPECT_EQ(dif_otp_ctrl_dai_program32(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*address=*/0b01, /*value=*/42), + kDifUnaligned); + EXPECT_EQ(dif_otp_ctrl_dai_program64(&otp_, kDifOtpCtrlPartitionSecret2, + /*address=*/0b100, /*value=*/42), + kDifUnaligned); +} + +TEST_F(DaiProgramTest, OutOfRange) { + // Check that we can't write a digest directly. + EXPECT_EQ(dif_otp_ctrl_dai_program32( + &otp_, kDifOtpCtrlPartitionCreatorSwCfg, + /*address=*/OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_OFFSET, + /*value=*/42), + kDifOutOfRange); + + // Same digest check for 64-bit. + EXPECT_EQ(dif_otp_ctrl_dai_program64( + &otp_, kDifOtpCtrlPartitionSecret2, + /*address=*/OTP_CTRL_PARAM_SECRET2_DIGEST_OFFSET, /*value=*/42), + kDifOutOfRange); +} + +TEST_F(DaiProgramTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_program32(nullptr, + kDifOtpCtrlPartitionHwCfg0, + /*address=*/0x0, /*value=*/42)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_program64(nullptr, + kDifOtpCtrlPartitionSecret0, + /*address=*/0x0, /*value=*/42)); +} + +class DaiDigestTest : public OtpTest {}; + +TEST_F(DaiDigestTest, DigestSw) { +% for part in sw_digest_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_define = part_name.as_c_define() + part_name_camel = part_name.as_camel_case() + dai_digest_line = ("EXPECT_DIF_OK(dif_otp_ctrl_dai_digest(&otp_, " + + f"kDifOtpCtrlPartition{part_name_camel},") +%>\ + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_${part_name.as_c_define()}_DIGEST_OFFSET); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_0_REG_OFFSET, 0x00abcdef); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_WDATA_1_REG_OFFSET, 0xabcdef00); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_WR_BIT, true}}); + + % if len(dai_digest_line) > 80 - 2: +<% dai_digest_line = (f"kDifOtpCtrlPartition{part_name_camel},") %>\ + % if len(dai_digest_line) > 80 - 40: + EXPECT_DIF_OK( + dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartition${part_name_camel}, + /*digest=*/0xabcdef0000abcdef)); + % else: + EXPECT_DIF_OK(dif_otp_ctrl_dai_digest(&otp_, + kDifOtpCtrlPartition${part_name_camel}, + /*digest=*/0xabcdef0000abcdef)); + % endif + % else: + ${dai_digest_line} + /*digest=*/0xabcdef0000abcdef)); + % endif + % if not loop.last: + + % endif +% endfor +} + +TEST_F(DaiDigestTest, DigestHw) { +% for part in hw_digest_parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_define = part_name.as_c_define() + part_name_camel = part_name.as_camel_case() + dai_digest_line = ("EXPECT_DIF_OK(dif_otp_ctrl_dai_digest(&otp_, " + + f"kDifOtpCtrlPartition{part_name_camel},") +%>\ + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_ADDRESS_REG_OFFSET, + OTP_CTRL_PARAM_${part_name_define}_OFFSET); + EXPECT_WRITE32(OTP_CTRL_DIRECT_ACCESS_CMD_REG_OFFSET, + {{OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_BIT, true}}); + + EXPECT_DIF_OK(dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartition${part_name_camel}, + /*digest=*/0)); + % if not loop.last: + + % endif +% endfor +} + +TEST_F(DaiDigestTest, BadPartition) { + EXPECT_EQ(dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartitionLifeCycle, + /*digest=*/0), + kDifError); +} + +TEST_F(DaiDigestTest, BadDigest) { + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_digest(&otp_, kDifOtpCtrlPartitionHwCfg0, + /*digest=*/0xabcdef0000abcdef)); + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_digest(&otp_, + kDifOtpCtrlPartitionCreatorSwCfg, + /*digest=*/0)); +} + +TEST_F(DaiDigestTest, NullArgs) { + EXPECT_DIF_BADARG(dif_otp_ctrl_dai_digest(nullptr, + kDifOtpCtrlPartitionCreatorSwCfg, + /*digest=*/0xabcdef0000abcdef)); +} + +class IsDigestComputed : public OtpTest {}; + +TEST_F(IsDigestComputed, NullArgs) { + bool is_computed; + EXPECT_DIF_BADARG(dif_otp_ctrl_is_digest_computed( + nullptr, kDifOtpCtrlPartitionSecret2, &is_computed)); + EXPECT_DIF_BADARG(dif_otp_ctrl_is_digest_computed( + &otp_, kDifOtpCtrlPartitionSecret2, nullptr)); + EXPECT_DIF_BADARG(dif_otp_ctrl_is_digest_computed( + nullptr, kDifOtpCtrlPartitionSecret2, nullptr)); +} + +TEST_F(IsDigestComputed, BadPartition) { + bool is_computed; + EXPECT_DIF_BADARG(dif_otp_ctrl_is_digest_computed( + &otp_, kDifOtpCtrlPartitionLifeCycle, &is_computed)); +} + +TEST_F(IsDigestComputed, Success) { + bool is_computed; + + EXPECT_READ32(OTP_CTRL_SECRET2_DIGEST_1_REG_OFFSET, 0x98abcdef); + EXPECT_READ32(OTP_CTRL_SECRET2_DIGEST_0_REG_OFFSET, 0xabcdef01); + EXPECT_DIF_OK(dif_otp_ctrl_is_digest_computed( + &otp_, kDifOtpCtrlPartitionSecret2, &is_computed)); + EXPECT_TRUE(is_computed); + + EXPECT_READ32(OTP_CTRL_SECRET2_DIGEST_1_REG_OFFSET, 0); + EXPECT_READ32(OTP_CTRL_SECRET2_DIGEST_0_REG_OFFSET, 0); + EXPECT_DIF_OK(dif_otp_ctrl_is_digest_computed( + &otp_, kDifOtpCtrlPartitionSecret2, &is_computed)); + EXPECT_FALSE(is_computed); +} + +struct DigestParams { + dif_otp_ctrl_partition_t partition; + bool has_digest; + ptrdiff_t reg0, reg1; +}; + +class GetDigest : public OtpTest, + public testing::WithParamInterface {}; + +TEST_P(GetDigest, GetDigest) { + if (!GetParam().has_digest) { + uint64_t digest; + EXPECT_DIF_BADARG( + dif_otp_ctrl_get_digest(&otp_, GetParam().partition, &digest)); + return; + } + + EXPECT_READ32(GetParam().reg1, 0xabcdef99); + EXPECT_READ32(GetParam().reg0, 0x99abcdef); + + uint64_t digest; + EXPECT_DIF_OK(dif_otp_ctrl_get_digest(&otp_, GetParam().partition, &digest)); + EXPECT_EQ(digest, 0xabcdef9999abcdef); +} + +TEST_P(GetDigest, BadDigest) { + if (!GetParam().has_digest) { + return; + } + + EXPECT_READ32(GetParam().reg1, 0x0); + EXPECT_READ32(GetParam().reg0, 0x0); + + uint64_t digest; + EXPECT_EQ(dif_otp_ctrl_get_digest(&otp_, GetParam().partition, &digest), + kDifError); +} + +TEST_P(GetDigest, NullArgs) { + uint64_t digest; + EXPECT_DIF_BADARG( + dif_otp_ctrl_get_digest(nullptr, GetParam().partition, &digest)); + EXPECT_DIF_BADARG( + dif_otp_ctrl_get_digest(&otp_, GetParam().partition, nullptr)); +} + +// This depends on the maximum length of partition names, which will +// be changing, so turn formatting off. +// clang-format off +INSTANTIATE_TEST_SUITE_P( + AllDigests, GetDigest, + testing::Values( +% for part in parts: +<% + part_name = Name.from_snake_case(part["name"]) + part_name_camel = part_name.as_camel_case() + part_name_define = part_name.as_c_define() +%>\ + % if part in digest_parts: + DigestParams{ + kDifOtpCtrlPartition${part_name_camel}, + true, + OTP_CTRL_${part_name_define}_DIGEST_0_REG_OFFSET, + OTP_CTRL_${part_name_define}_DIGEST_1_REG_OFFSET, + }${"" if loop.last else ","} + % else: + DigestParams{ + kDifOtpCtrlPartition${part_name_camel}, + false, + 0, + 0, + }${"));" if loop.last else ","} + % endif +% endfor +// clang-format on + +class BlockingIoTest : public OtpTest { + protected: + static constexpr size_t kWords = 4; +}; + +TEST_F(BlockingIoTest, Read) { + for (size_t i = 0; i < kWords; ++i) { + auto offset = + OTP_CTRL_PARAM_OWNER_SW_CFG_OFFSET + 0x10 + i * sizeof(uint32_t); + EXPECT_READ32(OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET + offset, i + 1); + } + + std::vector buf(kWords); + EXPECT_DIF_OK(dif_otp_ctrl_read_blocking( + &otp_, kDifOtpCtrlPartitionOwnerSwCfg, 0x10, buf.data(), buf.size())); + EXPECT_THAT(buf, ElementsAre(1, 2, 3, 4)); +} + +TEST_F(BlockingIoTest, BadPartition) { + std::vector buf(kWords); + EXPECT_EQ(dif_otp_ctrl_read_blocking(&otp_, kDifOtpCtrlPartitionHwCfg0, 0x10, + buf.data(), buf.size()), + kDifError); +} + +TEST_F(BlockingIoTest, Unaligned) { + std::vector buf(kWords); + EXPECT_EQ(dif_otp_ctrl_read_blocking(&otp_, kDifOtpCtrlPartitionOwnerSwCfg, + 0x11, buf.data(), buf.size()), + kDifUnaligned); +} + +TEST_F(BlockingIoTest, OutOfRange) { + std::vector buf(0x2f0); + EXPECT_EQ(dif_otp_ctrl_read_blocking(&otp_, kDifOtpCtrlPartitionOwnerSwCfg, + 0x300, buf.data(), buf.size()), + kDifOutOfRange); + EXPECT_EQ(dif_otp_ctrl_read_blocking(&otp_, kDifOtpCtrlPartitionOwnerSwCfg, + 0x10, buf.data(), 0x330), + kDifOutOfRange); +} + +TEST_F(BlockingIoTest, NullArgs) { + std::vector buf(kWords); + EXPECT_DIF_BADARG(dif_otp_ctrl_read_blocking( + nullptr, kDifOtpCtrlPartitionOwnerSwCfg, 0x10, buf.data(), buf.size())); + EXPECT_DIF_BADARG(dif_otp_ctrl_read_blocking( + &otp_, kDifOtpCtrlPartitionOwnerSwCfg, 0x10, nullptr, buf.size())); +} + +} // namespace +} // namespace dif_otp_ctrl_unittest diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/otp_ctrl.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/otp_ctrl.hjson new file mode 100644 index 00000000000..f7bb153631a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/otp_ctrl.hjson @@ -0,0 +1,3544 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// HJSON with partition metadata. +// +{ + name: "otp_ctrl", + human_name: "One-Time Programmable Memory Controller", + one_line_desc: "Interfaces integrated one-time programmable memory, supports scrambling, integrity and secure wipe", + one_paragraph_desc: ''' + One-Time Programmable (OTP) Memory Controller provides an open source abstraction interface for software and other hardware components such as Life Cycle Controller and Key Manager to interact with an integrated, closed source, proprietary OTP memory. + On top of defensive features provided by the proprietary OTP memory to deter side-channel analysis (SCA), fault injection (FI) attacks, and visual and electrical probing, the open source OTP controller features high-level logical security protection such as integrity checks and scrambling, as well as software isolation for when OTP contents are readable and programmable. + It features multiple individually-lockable logical partitions, periodic / persistent checking of OTP values, and a separate partition and interface for Life Cycle Controller. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "16", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_otp_ctrl", + revisions: [ + { + version: "0.1.0", + life_stage: "L1", + design_stage: "D2", + verification_stage: "V2", + dif_stage: "S1", + commit_id: "127b109e2fab9336e830158abe449a3922544ded", + notes: "", + } + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + { + version: "2.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_edn_i", reset: "rst_edn_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device", name: "core" } + ], + + /////////////////////////// + // Interrupts and Alerts // + /////////////////////////// + + interrupt_list: [ + { name: "otp_operation_done", + desc: "A direct access command or digest calculation operation has completed." + } + { name: "otp_error", + desc: "An error has occurred in the OTP controller. Check the !!ERR_CODE register to get more information." + } + ], + + alert_list: [ + { name: "fatal_macro_error", + desc: "This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array.", + } + { name: "fatal_check_error", + desc: "This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers.", + } + { name: "fatal_bus_integ_error", + desc: "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + } + { name: "fatal_prim_otp_alert", + desc: "Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface." + } + { name: "recov_prim_otp_alert", + desc: "Recoverable alert triggered inside the OTP primitive." + } + ], + + //////////////// + // Parameters // + //////////////// + param_list: [ + // Random netlist constants + { name: "RndCnstLfsrSeed", + desc: "Compile-time random bits for initial LFSR seed", + type: "otp_ctrl_top_specific_pkg::lfsr_seed_t" + randcount: "40", + randtype: "data", // randomize randcount databits + } + { name: "RndCnstLfsrPerm", + desc: "Compile-time random permutation for LFSR output", + type: "otp_ctrl_top_specific_pkg::lfsr_perm_t" + randcount: "40", + randtype: "perm", // random permutation for randcount elements + } + { name: "RndCnstScrmblKeyInit", + desc: "Compile-time random permutation for scrambling key/nonce register reset value", + type: "otp_ctrl_top_specific_pkg::scrmbl_key_init_t" + randcount: "256", + randtype: "data", // random permutation for randcount elements + } + // Normal parameters + { name: "NumSramKeyReqSlots", + desc: "Number of key slots", + type: "int", + default: "4", + local: "true" + }, + // Macro parameters + { + name: "OtpDepth", + desc: "Number of native words.", + default: "8192", + local: "true" + }, + { + name: "OtpWidth", + desc: "Number of bytes in native words.", + default: "2", + local: "true" + }, + { + name: "OtpSizeWidth", + desc: "Number of bits to represent the native words per transaction.", + default: "2", + local: "true" + }, + { name: "OtpByteAddrWidth", + desc: "Width of the OTP byte address.", + type: "int", + default: "14", + local: "true" + }, + { name: "NumErrorEntries", + desc: "Number of error register entries.", + type: "int", + default: "24", // partitions + DAI/LCI + local: "true" + }, + { name: "NumDaiWords", + desc: "Number of 32bit words in the DAI.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumDigestWords", + desc: "Size of the digest fields in 32bit words.", + type: "int", + default: "2", + local: "true" + }, + { name: "NumSwCfgWindowWords", + desc: "Size of the TL-UL window in 32bit words. Note that the effective partition size is smaller than that.", + type: "int", + default: "4096", + local: "true" + } + + // Memory map Info + { name: "NumPart", + desc: "Number of partitions", + type: "int", + default: "22", + local: "true" + }, + { name: "NumPartUnbuf", + desc: "Number of unbuffered partitions", + type: "int", + default: "15", + local: "true" + }, + { name: "NumPartBuf", + desc: "Number of buffered partitions (including 1 lifecycle partition)", + type: "int", + default: "7", + local: "true" + }, + { name: "VendorTestOffset", + desc: "Offset of the VENDOR_TEST partition", + type: "int", + default: "0", + local: "true" + }, + { name: "VendorTestSize", + desc: "Size of the VENDOR_TEST partition", + type: "int", + default: "64", + local: "true" + }, + { name: "ScratchOffset", + desc: "Offset of SCRATCH", + type: "int", + default: "0", + local: "true" + }, + { name: "ScratchSize", + desc: "Size of SCRATCH", + type: "int", + default: "56", + local: "true" + }, + { name: "VendorTestDigestOffset", + desc: "Offset of VENDOR_TEST_DIGEST", + type: "int", + default: "56", + local: "true" + }, + { name: "VendorTestDigestSize", + desc: "Size of VENDOR_TEST_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "CreatorSwCfgOffset", + desc: "Offset of the CREATOR_SW_CFG partition", + type: "int", + default: "64", + local: "true" + }, + { name: "CreatorSwCfgSize", + desc: "Size of the CREATOR_SW_CFG partition", + type: "int", + default: "320", + local: "true" + }, + { name: "CreatorSwCfgAstCfgOffset", + desc: "Offset of CREATOR_SW_CFG_AST_CFG", + type: "int", + default: "64", + local: "true" + }, + { name: "CreatorSwCfgAstCfgSize", + desc: "Size of CREATOR_SW_CFG_AST_CFG", + type: "int", + default: "124", + local: "true" + }, + { name: "CreatorSwCfgAstInitEnOffset", + desc: "Offset of CREATOR_SW_CFG_AST_INIT_EN", + type: "int", + default: "188", + local: "true" + }, + { name: "CreatorSwCfgAstInitEnSize", + desc: "Size of CREATOR_SW_CFG_AST_INIT_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgOverridesOffset", + desc: "Offset of CREATOR_SW_CFG_OVERRIDES", + type: "int", + default: "192", + local: "true" + }, + { name: "CreatorSwCfgOverridesSize", + desc: "Size of CREATOR_SW_CFG_OVERRIDES", + type: "int", + default: "32", + local: "true" + }, + { name: "CreatorSwCfgRomExtSkuOffset", + desc: "Offset of CREATOR_SW_CFG_ROM_EXT_SKU", + type: "int", + default: "224", + local: "true" + }, + { name: "CreatorSwCfgRomExtSkuSize", + desc: "Size of CREATOR_SW_CFG_ROM_EXT_SKU", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgSigverifyRsaModExpIbexEnOffset", + desc: "Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN", + type: "int", + default: "228", + local: "true" + }, + { name: "CreatorSwCfgSigverifyRsaModExpIbexEnSize", + desc: "Size of CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgSigverifyRsaKeyEnOffset", + desc: "Offset of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN", + type: "int", + default: "232", + local: "true" + }, + { name: "CreatorSwCfgSigverifyRsaKeyEnSize", + desc: "Size of CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN", + type: "int", + default: "8", + local: "true" + }, + { name: "CreatorSwCfgSigverifySpxEnOffset", + desc: "Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_EN", + type: "int", + default: "240", + local: "true" + }, + { name: "CreatorSwCfgSigverifySpxEnSize", + desc: "Size of CREATOR_SW_CFG_SIGVERIFY_SPX_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgSigverifySpxKeyEnOffset", + desc: "Offset of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN", + type: "int", + default: "244", + local: "true" + }, + { name: "CreatorSwCfgSigverifySpxKeyEnSize", + desc: "Size of CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN", + type: "int", + default: "8", + local: "true" + }, + { name: "CreatorSwCfgFlashDataDefaultCfgOffset", + desc: "Offset of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG", + type: "int", + default: "252", + local: "true" + }, + { name: "CreatorSwCfgFlashDataDefaultCfgSize", + desc: "Size of CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgFlashInfoBootDataCfgOffset", + desc: "Offset of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG", + type: "int", + default: "256", + local: "true" + }, + { name: "CreatorSwCfgFlashInfoBootDataCfgSize", + desc: "Size of CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgFlashHwInfoCfgOverrideOffset", + desc: "Offset of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE", + type: "int", + default: "260", + local: "true" + }, + { name: "CreatorSwCfgFlashHwInfoCfgOverrideSize", + desc: "Size of CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngEnOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_EN", + type: "int", + default: "264", + local: "true" + }, + { name: "CreatorSwCfgRngEnSize", + desc: "Size of CREATOR_SW_CFG_RNG_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgJitterEnOffset", + desc: "Offset of CREATOR_SW_CFG_JITTER_EN", + type: "int", + default: "268", + local: "true" + }, + { name: "CreatorSwCfgJitterEnSize", + desc: "Size of CREATOR_SW_CFG_JITTER_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRetRamResetMaskOffset", + desc: "Offset of CREATOR_SW_CFG_RET_RAM_RESET_MASK", + type: "int", + default: "272", + local: "true" + }, + { name: "CreatorSwCfgRetRamResetMaskSize", + desc: "Size of CREATOR_SW_CFG_RET_RAM_RESET_MASK", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgManufStateOffset", + desc: "Offset of CREATOR_SW_CFG_MANUF_STATE", + type: "int", + default: "276", + local: "true" + }, + { name: "CreatorSwCfgManufStateSize", + desc: "Size of CREATOR_SW_CFG_MANUF_STATE", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRomExecEnOffset", + desc: "Offset of CREATOR_SW_CFG_ROM_EXEC_EN", + type: "int", + default: "280", + local: "true" + }, + { name: "CreatorSwCfgRomExecEnSize", + desc: "Size of CREATOR_SW_CFG_ROM_EXEC_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgCpuctrlOffset", + desc: "Offset of CREATOR_SW_CFG_CPUCTRL", + type: "int", + default: "284", + local: "true" + }, + { name: "CreatorSwCfgCpuctrlSize", + desc: "Size of CREATOR_SW_CFG_CPUCTRL", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgMinSecVerRomExtOffset", + desc: "Offset of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT", + type: "int", + default: "288", + local: "true" + }, + { name: "CreatorSwCfgMinSecVerRomExtSize", + desc: "Size of CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgMinSecVerBl0Offset", + desc: "Offset of CREATOR_SW_CFG_MIN_SEC_VER_BL0", + type: "int", + default: "292", + local: "true" + }, + { name: "CreatorSwCfgMinSecVerBl0Size", + desc: "Size of CREATOR_SW_CFG_MIN_SEC_VER_BL0", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgDefaultBootDataInProdEnOffset", + desc: "Offset of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN", + type: "int", + default: "296", + local: "true" + }, + { name: "CreatorSwCfgDefaultBootDataInProdEnSize", + desc: "Size of CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRmaSpinEnOffset", + desc: "Offset of CREATOR_SW_CFG_RMA_SPIN_EN", + type: "int", + default: "300", + local: "true" + }, + { name: "CreatorSwCfgRmaSpinEnSize", + desc: "Size of CREATOR_SW_CFG_RMA_SPIN_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRmaSpinCyclesOffset", + desc: "Offset of CREATOR_SW_CFG_RMA_SPIN_CYCLES", + type: "int", + default: "304", + local: "true" + }, + { name: "CreatorSwCfgRmaSpinCyclesSize", + desc: "Size of CREATOR_SW_CFG_RMA_SPIN_CYCLES", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngRepcntThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS", + type: "int", + default: "308", + local: "true" + }, + { name: "CreatorSwCfgRngRepcntThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngRepcntsThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS", + type: "int", + default: "312", + local: "true" + }, + { name: "CreatorSwCfgRngRepcntsThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngAdaptpHiThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS", + type: "int", + default: "316", + local: "true" + }, + { name: "CreatorSwCfgRngAdaptpHiThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngAdaptpLoThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS", + type: "int", + default: "320", + local: "true" + }, + { name: "CreatorSwCfgRngAdaptpLoThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngBucketThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS", + type: "int", + default: "324", + local: "true" + }, + { name: "CreatorSwCfgRngBucketThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngMarkovHiThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS", + type: "int", + default: "328", + local: "true" + }, + { name: "CreatorSwCfgRngMarkovHiThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngMarkovLoThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS", + type: "int", + default: "332", + local: "true" + }, + { name: "CreatorSwCfgRngMarkovLoThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngExthtHiThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS", + type: "int", + default: "336", + local: "true" + }, + { name: "CreatorSwCfgRngExthtHiThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngExthtLoThresholdsOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS", + type: "int", + default: "340", + local: "true" + }, + { name: "CreatorSwCfgRngExthtLoThresholdsSize", + desc: "Size of CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngAlertThresholdOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD", + type: "int", + default: "344", + local: "true" + }, + { name: "CreatorSwCfgRngAlertThresholdSize", + desc: "Size of CREATOR_SW_CFG_RNG_ALERT_THRESHOLD", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgRngHealthConfigDigestOffset", + desc: "Offset of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST", + type: "int", + default: "348", + local: "true" + }, + { name: "CreatorSwCfgRngHealthConfigDigestSize", + desc: "Size of CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgSramKeyRenewEnOffset", + desc: "Offset of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN", + type: "int", + default: "352", + local: "true" + }, + { name: "CreatorSwCfgSramKeyRenewEnSize", + desc: "Size of CREATOR_SW_CFG_SRAM_KEY_RENEW_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "CreatorSwCfgDigestOffset", + desc: "Offset of CREATOR_SW_CFG_DIGEST", + type: "int", + default: "376", + local: "true" + }, + { name: "CreatorSwCfgDigestSize", + desc: "Size of CREATOR_SW_CFG_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "OwnerSwCfgOffset", + desc: "Offset of the OWNER_SW_CFG partition", + type: "int", + default: "384", + local: "true" + }, + { name: "OwnerSwCfgSize", + desc: "Size of the OWNER_SW_CFG partition", + type: "int", + default: "632", + local: "true" + }, + { name: "OwnerSwCfgRomErrorReportingOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ERROR_REPORTING", + type: "int", + default: "384", + local: "true" + }, + { name: "OwnerSwCfgRomErrorReportingSize", + desc: "Size of OWNER_SW_CFG_ROM_ERROR_REPORTING", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomBootstrapDisOffset", + desc: "Offset of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS", + type: "int", + default: "388", + local: "true" + }, + { name: "OwnerSwCfgRomBootstrapDisSize", + desc: "Size of OWNER_SW_CFG_ROM_BOOTSTRAP_DIS", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertClassEnOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_CLASS_EN", + type: "int", + default: "392", + local: "true" + }, + { name: "OwnerSwCfgRomAlertClassEnSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_CLASS_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertEscalationOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_ESCALATION", + type: "int", + default: "396", + local: "true" + }, + { name: "OwnerSwCfgRomAlertEscalationSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_ESCALATION", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertClassificationOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION", + type: "int", + default: "400", + local: "true" + }, + { name: "OwnerSwCfgRomAlertClassificationSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION", + type: "int", + default: "400", + local: "true" + }, + { name: "OwnerSwCfgRomLocalAlertClassificationOffset", + desc: "Offset of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION", + type: "int", + default: "800", + local: "true" + }, + { name: "OwnerSwCfgRomLocalAlertClassificationSize", + desc: "Size of OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION", + type: "int", + default: "64", + local: "true" + }, + { name: "OwnerSwCfgRomAlertAccumThreshOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH", + type: "int", + default: "864", + local: "true" + }, + { name: "OwnerSwCfgRomAlertAccumThreshSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH", + type: "int", + default: "16", + local: "true" + }, + { name: "OwnerSwCfgRomAlertTimeoutCyclesOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES", + type: "int", + default: "880", + local: "true" + }, + { name: "OwnerSwCfgRomAlertTimeoutCyclesSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES", + type: "int", + default: "16", + local: "true" + }, + { name: "OwnerSwCfgRomAlertPhaseCyclesOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES", + type: "int", + default: "896", + local: "true" + }, + { name: "OwnerSwCfgRomAlertPhaseCyclesSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES", + type: "int", + default: "64", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestProdOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", + type: "int", + default: "960", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestProdSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestProdEndOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", + type: "int", + default: "964", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestProdEndSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestDevOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", + type: "int", + default: "968", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestDevSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestRmaOffset", + desc: "Offset of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", + type: "int", + default: "972", + local: "true" + }, + { name: "OwnerSwCfgRomAlertDigestRmaSize", + desc: "Size of OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomWatchdogBiteThresholdCyclesOffset", + desc: "Offset of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES", + type: "int", + default: "976", + local: "true" + }, + { name: "OwnerSwCfgRomWatchdogBiteThresholdCyclesSize", + desc: "Size of OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomKeymgrRomExtMeasEnOffset", + desc: "Offset of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN", + type: "int", + default: "980", + local: "true" + }, + { name: "OwnerSwCfgRomKeymgrRomExtMeasEnSize", + desc: "Size of OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgManufStateOffset", + desc: "Offset of OWNER_SW_CFG_MANUF_STATE", + type: "int", + default: "984", + local: "true" + }, + { name: "OwnerSwCfgManufStateSize", + desc: "Size of OWNER_SW_CFG_MANUF_STATE", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgRomRstmgrInfoEnOffset", + desc: "Offset of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN", + type: "int", + default: "988", + local: "true" + }, + { name: "OwnerSwCfgRomRstmgrInfoEnSize", + desc: "Size of OWNER_SW_CFG_ROM_RSTMGR_INFO_EN", + type: "int", + default: "4", + local: "true" + }, + { name: "OwnerSwCfgDigestOffset", + desc: "Offset of OWNER_SW_CFG_DIGEST", + type: "int", + default: "1008", + local: "true" + }, + { name: "OwnerSwCfgDigestSize", + desc: "Size of OWNER_SW_CFG_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "OwnershipSlotStateOffset", + desc: "Offset of the OWNERSHIP_SLOT_STATE partition", + type: "int", + default: "1016", + local: "true" + }, + { name: "OwnershipSlotStateSize", + desc: "Size of the OWNERSHIP_SLOT_STATE partition", + type: "int", + default: "48", + local: "true" + }, + { name: "OwnershipSlotStateRotOwnerAuthOffset", + desc: "Offset of OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH", + type: "int", + default: "1016", + local: "true" + }, + { name: "OwnershipSlotStateRotOwnerAuthSize", + desc: "Size of OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH", + type: "int", + default: "16", + local: "true" + }, + { name: "OwnershipSlotStatePlatIntegAuthOffset", + desc: "Offset of OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH", + type: "int", + default: "1032", + local: "true" + }, + { name: "OwnershipSlotStatePlatIntegAuthSize", + desc: "Size of OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH", + type: "int", + default: "16", + local: "true" + }, + { name: "OwnershipSlotStatePlatOwnerAuthOffset", + desc: "Offset of OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH", + type: "int", + default: "1048", + local: "true" + }, + { name: "OwnershipSlotStatePlatOwnerAuthSize", + desc: "Size of OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH", + type: "int", + default: "16", + local: "true" + }, + { name: "RotCreatorAuthOffset", + desc: "Offset of the ROT_CREATOR_AUTH partition", + type: "int", + default: "1064", + local: "true" + }, + { name: "RotCreatorAuthSize", + desc: "Size of the ROT_CREATOR_AUTH partition", + type: "int", + default: "1424", + local: "true" + }, + { name: "RotCreatorAuthNonRawMfwCodesignKeyOffset", + desc: "Offset of ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY", + type: "int", + default: "1064", + local: "true" + }, + { name: "RotCreatorAuthNonRawMfwCodesignKeySize", + desc: "Size of ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "RotCreatorAuthOwnershipStateOffset", + desc: "Offset of ROT_CREATOR_AUTH_OWNERSHIP_STATE", + type: "int", + default: "1224", + local: "true" + }, + { name: "RotCreatorAuthOwnershipStateSize", + desc: "Size of ROT_CREATOR_AUTH_OWNERSHIP_STATE", + type: "int", + default: "4", + local: "true" + }, + { name: "RotCreatorAuthRom2PatchSigverifyKeyOffset", + desc: "Offset of ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY", + type: "int", + default: "1228", + local: "true" + }, + { name: "RotCreatorAuthRom2PatchSigverifyKeySize", + desc: "Size of ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "RotCreatorAuthKeymanifestKeyOffset", + desc: "Offset of ROT_CREATOR_AUTH_KEYMANIFEST_KEY", + type: "int", + default: "1388", + local: "true" + }, + { name: "RotCreatorAuthKeymanifestKeySize", + desc: "Size of ROT_CREATOR_AUTH_KEYMANIFEST_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "RotCreatorAuthUnlock4xferKeyOffset", + desc: "Offset of ROT_CREATOR_AUTH_UNLOCK4XFER_KEY", + type: "int", + default: "1548", + local: "true" + }, + { name: "RotCreatorAuthUnlock4xferKeySize", + desc: "Size of ROT_CREATOR_AUTH_UNLOCK4XFER_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "RotCreatorAuthIdentityCertOffset", + desc: "Offset of ROT_CREATOR_AUTH_IDENTITY_CERT", + type: "int", + default: "1708", + local: "true" + }, + { name: "RotCreatorAuthIdentityCertSize", + desc: "Size of ROT_CREATOR_AUTH_IDENTITY_CERT", + type: "int", + default: "768", + local: "true" + }, + { name: "RotCreatorAuthDigestOffset", + desc: "Offset of ROT_CREATOR_AUTH_DIGEST", + type: "int", + default: "2480", + local: "true" + }, + { name: "RotCreatorAuthDigestSize", + desc: "Size of ROT_CREATOR_AUTH_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "RotOwnerAuthSlot0Offset", + desc: "Offset of the ROT_OWNER_AUTH_SLOT0 partition", + type: "int", + default: "2488", + local: "true" + }, + { name: "RotOwnerAuthSlot0Size", + desc: "Size of the ROT_OWNER_AUTH_SLOT0 partition", + type: "int", + default: "328", + local: "true" + }, + { name: "RotOwnerAuthSlot0KeymanifestKeyOffset", + desc: "Offset of ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY", + type: "int", + default: "2488", + local: "true" + }, + { name: "RotOwnerAuthSlot0KeymanifestKeySize", + desc: "Size of ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "RotOwnerAuthSlot0Unlock4xferKeyOffset", + desc: "Offset of ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY", + type: "int", + default: "2648", + local: "true" + }, + { name: "RotOwnerAuthSlot0Unlock4xferKeySize", + desc: "Size of ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "RotOwnerAuthSlot0DigestOffset", + desc: "Offset of ROT_OWNER_AUTH_SLOT0_DIGEST", + type: "int", + default: "2808", + local: "true" + }, + { name: "RotOwnerAuthSlot0DigestSize", + desc: "Size of ROT_OWNER_AUTH_SLOT0_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "RotOwnerAuthSlot1Offset", + desc: "Offset of the ROT_OWNER_AUTH_SLOT1 partition", + type: "int", + default: "2816", + local: "true" + }, + { name: "RotOwnerAuthSlot1Size", + desc: "Size of the ROT_OWNER_AUTH_SLOT1 partition", + type: "int", + default: "328", + local: "true" + }, + { name: "RotOwnerAuthSlot1KeymanifestKeyOffset", + desc: "Offset of ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY", + type: "int", + default: "2816", + local: "true" + }, + { name: "RotOwnerAuthSlot1KeymanifestKeySize", + desc: "Size of ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "RotOwnerAuthSlot1Unlock4xferKeyOffset", + desc: "Offset of ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY", + type: "int", + default: "2976", + local: "true" + }, + { name: "RotOwnerAuthSlot1Unlock4xferKeySize", + desc: "Size of ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "RotOwnerAuthSlot1DigestOffset", + desc: "Offset of ROT_OWNER_AUTH_SLOT1_DIGEST", + type: "int", + default: "3136", + local: "true" + }, + { name: "RotOwnerAuthSlot1DigestSize", + desc: "Size of ROT_OWNER_AUTH_SLOT1_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "PlatIntegAuthSlot0Offset", + desc: "Offset of the PLAT_INTEG_AUTH_SLOT0 partition", + type: "int", + default: "3144", + local: "true" + }, + { name: "PlatIntegAuthSlot0Size", + desc: "Size of the PLAT_INTEG_AUTH_SLOT0 partition", + type: "int", + default: "328", + local: "true" + }, + { name: "PlatIntegAuthSlot0KeymanifestKeyOffset", + desc: "Offset of PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY", + type: "int", + default: "3144", + local: "true" + }, + { name: "PlatIntegAuthSlot0KeymanifestKeySize", + desc: "Size of PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatIntegAuthSlot0Unlock4xferKeyOffset", + desc: "Offset of PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY", + type: "int", + default: "3304", + local: "true" + }, + { name: "PlatIntegAuthSlot0Unlock4xferKeySize", + desc: "Size of PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatIntegAuthSlot0DigestOffset", + desc: "Offset of PLAT_INTEG_AUTH_SLOT0_DIGEST", + type: "int", + default: "3464", + local: "true" + }, + { name: "PlatIntegAuthSlot0DigestSize", + desc: "Size of PLAT_INTEG_AUTH_SLOT0_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "PlatIntegAuthSlot1Offset", + desc: "Offset of the PLAT_INTEG_AUTH_SLOT1 partition", + type: "int", + default: "3472", + local: "true" + }, + { name: "PlatIntegAuthSlot1Size", + desc: "Size of the PLAT_INTEG_AUTH_SLOT1 partition", + type: "int", + default: "328", + local: "true" + }, + { name: "PlatIntegAuthSlot1KeymanifestKeyOffset", + desc: "Offset of PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY", + type: "int", + default: "3472", + local: "true" + }, + { name: "PlatIntegAuthSlot1KeymanifestKeySize", + desc: "Size of PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatIntegAuthSlot1Unlock4xferKeyOffset", + desc: "Offset of PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY", + type: "int", + default: "3632", + local: "true" + }, + { name: "PlatIntegAuthSlot1Unlock4xferKeySize", + desc: "Size of PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatIntegAuthSlot1DigestOffset", + desc: "Offset of PLAT_INTEG_AUTH_SLOT1_DIGEST", + type: "int", + default: "3792", + local: "true" + }, + { name: "PlatIntegAuthSlot1DigestSize", + desc: "Size of PLAT_INTEG_AUTH_SLOT1_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "PlatOwnerAuthSlot0Offset", + desc: "Offset of the PLAT_OWNER_AUTH_SLOT0 partition", + type: "int", + default: "3800", + local: "true" + }, + { name: "PlatOwnerAuthSlot0Size", + desc: "Size of the PLAT_OWNER_AUTH_SLOT0 partition", + type: "int", + default: "328", + local: "true" + }, + { name: "PlatOwnerAuthSlot0KeymanifestKeyOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY", + type: "int", + default: "3800", + local: "true" + }, + { name: "PlatOwnerAuthSlot0KeymanifestKeySize", + desc: "Size of PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatOwnerAuthSlot0Unlock4xferKeyOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY", + type: "int", + default: "3960", + local: "true" + }, + { name: "PlatOwnerAuthSlot0Unlock4xferKeySize", + desc: "Size of PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatOwnerAuthSlot0DigestOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT0_DIGEST", + type: "int", + default: "4120", + local: "true" + }, + { name: "PlatOwnerAuthSlot0DigestSize", + desc: "Size of PLAT_OWNER_AUTH_SLOT0_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "PlatOwnerAuthSlot1Offset", + desc: "Offset of the PLAT_OWNER_AUTH_SLOT1 partition", + type: "int", + default: "4128", + local: "true" + }, + { name: "PlatOwnerAuthSlot1Size", + desc: "Size of the PLAT_OWNER_AUTH_SLOT1 partition", + type: "int", + default: "328", + local: "true" + }, + { name: "PlatOwnerAuthSlot1KeymanifestKeyOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY", + type: "int", + default: "4128", + local: "true" + }, + { name: "PlatOwnerAuthSlot1KeymanifestKeySize", + desc: "Size of PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatOwnerAuthSlot1Unlock4xferKeyOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY", + type: "int", + default: "4288", + local: "true" + }, + { name: "PlatOwnerAuthSlot1Unlock4xferKeySize", + desc: "Size of PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatOwnerAuthSlot1DigestOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT1_DIGEST", + type: "int", + default: "4448", + local: "true" + }, + { name: "PlatOwnerAuthSlot1DigestSize", + desc: "Size of PLAT_OWNER_AUTH_SLOT1_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "PlatOwnerAuthSlot2Offset", + desc: "Offset of the PLAT_OWNER_AUTH_SLOT2 partition", + type: "int", + default: "4456", + local: "true" + }, + { name: "PlatOwnerAuthSlot2Size", + desc: "Size of the PLAT_OWNER_AUTH_SLOT2 partition", + type: "int", + default: "328", + local: "true" + }, + { name: "PlatOwnerAuthSlot2KeymanifestKeyOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY", + type: "int", + default: "4456", + local: "true" + }, + { name: "PlatOwnerAuthSlot2KeymanifestKeySize", + desc: "Size of PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatOwnerAuthSlot2Unlock4xferKeyOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY", + type: "int", + default: "4616", + local: "true" + }, + { name: "PlatOwnerAuthSlot2Unlock4xferKeySize", + desc: "Size of PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatOwnerAuthSlot2DigestOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT2_DIGEST", + type: "int", + default: "4776", + local: "true" + }, + { name: "PlatOwnerAuthSlot2DigestSize", + desc: "Size of PLAT_OWNER_AUTH_SLOT2_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "PlatOwnerAuthSlot3Offset", + desc: "Offset of the PLAT_OWNER_AUTH_SLOT3 partition", + type: "int", + default: "4784", + local: "true" + }, + { name: "PlatOwnerAuthSlot3Size", + desc: "Size of the PLAT_OWNER_AUTH_SLOT3 partition", + type: "int", + default: "328", + local: "true" + }, + { name: "PlatOwnerAuthSlot3KeymanifestKeyOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY", + type: "int", + default: "4784", + local: "true" + }, + { name: "PlatOwnerAuthSlot3KeymanifestKeySize", + desc: "Size of PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatOwnerAuthSlot3Unlock4xferKeyOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY", + type: "int", + default: "4944", + local: "true" + }, + { name: "PlatOwnerAuthSlot3Unlock4xferKeySize", + desc: "Size of PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY", + type: "int", + default: "160", + local: "true" + }, + { name: "PlatOwnerAuthSlot3DigestOffset", + desc: "Offset of PLAT_OWNER_AUTH_SLOT3_DIGEST", + type: "int", + default: "5104", + local: "true" + }, + { name: "PlatOwnerAuthSlot3DigestSize", + desc: "Size of PLAT_OWNER_AUTH_SLOT3_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "ExtNvmOffset", + desc: "Offset of the EXT_NVM partition", + type: "int", + default: "5112", + local: "true" + }, + { name: "ExtNvmSize", + desc: "Size of the EXT_NVM partition", + type: "int", + default: "1024", + local: "true" + }, + { name: "ExtNvmAntireplayFreshnessCntOffset", + desc: "Offset of EXT_NVM_ANTIREPLAY_FRESHNESS_CNT", + type: "int", + default: "5112", + local: "true" + }, + { name: "ExtNvmAntireplayFreshnessCntSize", + desc: "Size of EXT_NVM_ANTIREPLAY_FRESHNESS_CNT", + type: "int", + default: "1024", + local: "true" + }, + { name: "RomPatchOffset", + desc: "Offset of the ROM_PATCH partition", + type: "int", + default: "6136", + local: "true" + }, + { name: "RomPatchSize", + desc: "Size of the ROM_PATCH partition", + type: "int", + default: "9848", + local: "true" + }, + { name: "RomPatchDataOffset", + desc: "Offset of ROM_PATCH_DATA", + type: "int", + default: "6136", + local: "true" + }, + { name: "RomPatchDataSize", + desc: "Size of ROM_PATCH_DATA", + type: "int", + default: "9192", + local: "true" + }, + { name: "RomPatchDigestOffset", + desc: "Offset of ROM_PATCH_DIGEST", + type: "int", + default: "15976", + local: "true" + }, + { name: "RomPatchDigestSize", + desc: "Size of ROM_PATCH_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "HwCfg0Offset", + desc: "Offset of the HW_CFG0 partition", + type: "int", + default: "15984", + local: "true" + }, + { name: "HwCfg0Size", + desc: "Size of the HW_CFG0 partition", + type: "int", + default: "72", + local: "true" + }, + { name: "DeviceIdOffset", + desc: "Offset of DEVICE_ID", + type: "int", + default: "15984", + local: "true" + }, + { name: "DeviceIdSize", + desc: "Size of DEVICE_ID", + type: "int", + default: "32", + local: "true" + }, + { name: "ManufStateOffset", + desc: "Offset of MANUF_STATE", + type: "int", + default: "16016", + local: "true" + }, + { name: "ManufStateSize", + desc: "Size of MANUF_STATE", + type: "int", + default: "32", + local: "true" + }, + { name: "HwCfg0DigestOffset", + desc: "Offset of HW_CFG0_DIGEST", + type: "int", + default: "16048", + local: "true" + }, + { name: "HwCfg0DigestSize", + desc: "Size of HW_CFG0_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "HwCfg1Offset", + desc: "Offset of the HW_CFG1 partition", + type: "int", + default: "16056", + local: "true" + }, + { name: "HwCfg1Size", + desc: "Size of the HW_CFG1 partition", + type: "int", + default: "16", + local: "true" + }, + { name: "SocDbgStateOffset", + desc: "Offset of SOC_DBG_STATE", + type: "int", + default: "16056", + local: "true" + }, + { name: "SocDbgStateSize", + desc: "Size of SOC_DBG_STATE", + type: "int", + default: "4", + local: "true" + }, + { name: "EnCsrngSwAppReadOffset", + desc: "Offset of EN_CSRNG_SW_APP_READ", + type: "int", + default: "16060", + local: "true" + }, + { name: "EnCsrngSwAppReadSize", + desc: "Size of EN_CSRNG_SW_APP_READ", + type: "int", + default: "1", + local: "true" + }, + { name: "EnSramIfetchOffset", + desc: "Offset of EN_SRAM_IFETCH", + type: "int", + default: "16061", + local: "true" + }, + { name: "EnSramIfetchSize", + desc: "Size of EN_SRAM_IFETCH", + type: "int", + default: "1", + local: "true" + }, + { name: "HwCfg1DigestOffset", + desc: "Offset of HW_CFG1_DIGEST", + type: "int", + default: "16064", + local: "true" + }, + { name: "HwCfg1DigestSize", + desc: "Size of HW_CFG1_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret0Offset", + desc: "Offset of the SECRET0 partition", + type: "int", + default: "16072", + local: "true" + }, + { name: "Secret0Size", + desc: "Size of the SECRET0 partition", + type: "int", + default: "40", + local: "true" + }, + { name: "TestUnlockTokenOffset", + desc: "Offset of TEST_UNLOCK_TOKEN", + type: "int", + default: "16072", + local: "true" + }, + { name: "TestUnlockTokenSize", + desc: "Size of TEST_UNLOCK_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "TestExitTokenOffset", + desc: "Offset of TEST_EXIT_TOKEN", + type: "int", + default: "16088", + local: "true" + }, + { name: "TestExitTokenSize", + desc: "Size of TEST_EXIT_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "Secret0DigestOffset", + desc: "Offset of SECRET0_DIGEST", + type: "int", + default: "16104", + local: "true" + }, + { name: "Secret0DigestSize", + desc: "Size of SECRET0_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret1Offset", + desc: "Offset of the SECRET1 partition", + type: "int", + default: "16112", + local: "true" + }, + { name: "Secret1Size", + desc: "Size of the SECRET1 partition", + type: "int", + default: "24", + local: "true" + }, + { name: "SramDataKeySeedOffset", + desc: "Offset of SRAM_DATA_KEY_SEED", + type: "int", + default: "16112", + local: "true" + }, + { name: "SramDataKeySeedSize", + desc: "Size of SRAM_DATA_KEY_SEED", + type: "int", + default: "16", + local: "true" + }, + { name: "Secret1DigestOffset", + desc: "Offset of SECRET1_DIGEST", + type: "int", + default: "16128", + local: "true" + }, + { name: "Secret1DigestSize", + desc: "Size of SECRET1_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret2Offset", + desc: "Offset of the SECRET2 partition", + type: "int", + default: "16136", + local: "true" + }, + { name: "Secret2Size", + desc: "Size of the SECRET2 partition", + type: "int", + default: "120", + local: "true" + }, + { name: "RmaTokenOffset", + desc: "Offset of RMA_TOKEN", + type: "int", + default: "16136", + local: "true" + }, + { name: "RmaTokenSize", + desc: "Size of RMA_TOKEN", + type: "int", + default: "16", + local: "true" + }, + { name: "CreatorRootKeyShare0Offset", + desc: "Offset of CREATOR_ROOT_KEY_SHARE0", + type: "int", + default: "16152", + local: "true" + }, + { name: "CreatorRootKeyShare0Size", + desc: "Size of CREATOR_ROOT_KEY_SHARE0", + type: "int", + default: "32", + local: "true" + }, + { name: "CreatorRootKeyShare1Offset", + desc: "Offset of CREATOR_ROOT_KEY_SHARE1", + type: "int", + default: "16184", + local: "true" + }, + { name: "CreatorRootKeyShare1Size", + desc: "Size of CREATOR_ROOT_KEY_SHARE1", + type: "int", + default: "32", + local: "true" + }, + { name: "CreatorSeedOffset", + desc: "Offset of CREATOR_SEED", + type: "int", + default: "16216", + local: "true" + }, + { name: "CreatorSeedSize", + desc: "Size of CREATOR_SEED", + type: "int", + default: "32", + local: "true" + }, + { name: "Secret2DigestOffset", + desc: "Offset of SECRET2_DIGEST", + type: "int", + default: "16248", + local: "true" + }, + { name: "Secret2DigestSize", + desc: "Size of SECRET2_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "Secret3Offset", + desc: "Offset of the SECRET3 partition", + type: "int", + default: "16256", + local: "true" + }, + { name: "Secret3Size", + desc: "Size of the SECRET3 partition", + type: "int", + default: "40", + local: "true" + }, + { name: "OwnerSeedOffset", + desc: "Offset of OWNER_SEED", + type: "int", + default: "16256", + local: "true" + }, + { name: "OwnerSeedSize", + desc: "Size of OWNER_SEED", + type: "int", + default: "32", + local: "true" + }, + { name: "Secret3DigestOffset", + desc: "Offset of SECRET3_DIGEST", + type: "int", + default: "16288", + local: "true" + }, + { name: "Secret3DigestSize", + desc: "Size of SECRET3_DIGEST", + type: "int", + default: "8", + local: "true" + }, + { name: "LifeCycleOffset", + desc: "Offset of the LIFE_CYCLE partition", + type: "int", + default: "16296", + local: "true" + }, + { name: "LifeCycleSize", + desc: "Size of the LIFE_CYCLE partition", + type: "int", + default: "88", + local: "true" + }, + { name: "LcTransitionCntOffset", + desc: "Offset of LC_TRANSITION_CNT", + type: "int", + default: "16296", + local: "true" + }, + { name: "LcTransitionCntSize", + desc: "Size of LC_TRANSITION_CNT", + type: "int", + default: "48", + local: "true" + }, + { name: "LcStateOffset", + desc: "Offset of LC_STATE", + type: "int", + default: "16344", + local: "true" + }, + { name: "LcStateSize", + desc: "Size of LC_STATE", + type: "int", + default: "40", + local: "true" + }, + ] + + ///////////////////////////// + // Intermodule Connections // + ///////////////////////////// + + inter_signal_list: [ + // EDN interface + { struct: "edn" + type: "req_rsp" + name: "edn" + act: "req" + package: "edn_pkg" + desc: "Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation." + } + // Power manager init command + { struct: "pwr_otp" + type: "req_rsp" + name: "pwr_otp" + act: "rsp" + default: "'0" + package: "pwrmgr_pkg" + desc: "Initialization request/acknowledge from/to power manager." + } + // LC transition command + { struct: "lc_otp_program" + type: "req_rsp" + name: "lc_otp_program" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Life cycle state transition interface." + } + // Broadcast to LC + { struct: "otp_lc_data" + type: "uni" + name: "otp_lc_data" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: ''' + Life cycle state output holding the current life cycle state, + the value of the transition counter and the tokens needed for life cycle transitions. + ''' + } + // Broadcast from LC + { struct: "lc_tx" + type: "uni" + name: "lc_escalate_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle escalation enable coming from life cycle controller. + This signal moves all FSMs within OTP into the error state. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_creator_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_owner_seed_sw_rw_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Provision enable qualifier coming from life cycle controller. + This signal enables SW read / write access to the OWNER_SEED. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_seed_hw_rd_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Seed read enable coming from life cycle controller. + This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. + ''' + } + { struct: "lc_tx" + type: "uni" + name: "lc_check_byp_en" + act: "rcv" + default: "lc_ctrl_pkg::Off" + package: "lc_ctrl_pkg" + desc: ''' + Life cycle partition check bypass signal. + This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. + ''' + } + // Broadcast to Key Manager + { struct: "otp_keymgr_key" + type: "uni" + name: "otp_keymgr_key" + act: "req" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1." + } + // Key request from SRAM scramblers + { struct: "sram_otp_key" + // TODO: would be nice if this could accept parameters. + // Split this out into an issue. + width: "4" + type: "req_rsp" + name: "sram_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Array with key derivation interfaces for SRAM scrambling devices." + } + // Key request from OTBN RAM Scrambler + { struct: "otbn_otp_key" + type: "req_rsp" + name: "otbn_otp_key" + act: "rsp" + default: "'0" + package: "otp_ctrl_pkg" + desc: "Key derivation interface for OTBN scrambling devices." + } + // Hardware config partition + { struct: "otp_broadcast" + type: "uni" + name: "otp_broadcast" + act: "req" + default: "'0" + package: "otp_ctrl_part_pkg" + desc: "Output of the HW partitions with breakout data types." + } + // OTP_MACRO Interface + { struct: "otp_ctrl_macro" + type: "req_rsp" + name: "otp_macro" + act: "req" + default: "'0" + package: "otp_ctrl_macro_pkg" + desc: "Data interface for the OTP macro." + } + ] // inter_signal_list + + ///////////////////// + // Countermeasures // + ///////////////////// + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "SECRET.MEM.SCRAMBLE", + desc: "Secret partitions are scrambled with a full-round PRESENT cipher." + } + { name: "PART.MEM.DIGEST", + desc: "Integrity of buffered partitions is ensured via a 64bit digest." + } + { name: "DAI.FSM.SPARSE", + desc: "The direct access interface FSM is sparsely encoded." + } + { name: "KDI.FSM.SPARSE", + desc: "The key derivation interface FSM is sparsely encoded." + } + { name: "LCI.FSM.SPARSE", + desc: "The life cycle interface FSM is sparsely encoded." + } + { name: "PART.FSM.SPARSE", + desc: "The partition FSMs are sparsely encoded." + } + { name: "SCRMBL.FSM.SPARSE", + desc: "The scramble datapath FSM is sparsely encoded." + } + { name: "TIMER.FSM.SPARSE", + desc: "The background check timer FSM is sparsely encoded." + } + { name: "DAI.CTR.REDUN", + desc: "The direct access interface address counter employs a cross-counter implementation." + } + { name: "KDI_SEED.CTR.REDUN", + desc: "The key derivation interface counter employs a cross-counter implementation." + } + { name: "KDI_ENTROPY.CTR.REDUN", + desc: "The key derivation entropy counter employs a cross-counter implementation." + } + { name: "LCI.CTR.REDUN", + desc: "The life cycle interface address counter employs a cross-counter implementation." + } + { name: "PART.CTR.REDUN", + desc: "The address counter of buffered partitions employs a cross-counter implementation." + } + { name: "SCRMBL.CTR.REDUN", + desc: "The srambling datapath counter employs a cross-counter implementation." + } + { name: "TIMER_INTEG.CTR.REDUN", + desc: "The background integrity check timer employs a duplicated counter implementation." + } + { name: "TIMER_CNSTY.CTR.REDUN", + desc: "The background consistency check timer employs a duplicated counter implementation." + } + { name: "TIMER.LFSR.REDUN", + desc: "The background check LFSR is duplicated." + } + { name: "DAI.FSM.LOCAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon local escalation." + } + { name: "LCI.FSM.LOCAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon local escalation." + } + { name: "KDI.FSM.LOCAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon local escalation." + } + { name: "PART.FSM.LOCAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon local escalation." + } + { name: "SCRMBL.FSM.LOCAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon local escalation." + } + { name: "TIMER.FSM.LOCAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon local escalation." + } + { name: "DAI.FSM.GLOBAL_ESC", + desc: "The direct access interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "LCI.FSM.GLOBAL_ESC", + desc: "The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "KDI.FSM.GLOBAL_ESC", + desc: "The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.FSM.GLOBAL_ESC", + desc: "The partition FSMs are moved into an invalid state upon global escalation via life cycle." + } + { name: "SCRMBL.FSM.GLOBAL_ESC", + desc: "The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "TIMER.FSM.GLOBAL_ESC", + desc: "The background check timer FSM is moved into an invalid state upon global escalation via life cycle." + } + { name: "PART.DATA_REG.INTEGRITY", + desc: "All partition buffer registers are protected with ECC on 64bit blocks." + } + { name: "PART.DATA_REG.BKGN_CHK", + desc: "The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background." + } + { name: "PART.MEM.REGREN" + desc: "Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset." + } + { name: "PART.MEM.SW_UNREADABLE" + desc: "Secret buffered partitions become unreadable to software once they are locked via the digest." + } + { name: "PART.MEM.SW_UNWRITABLE" + desc: "All partitions become unwritable by software once they are locked via the digest." + } + { name: "LC_PART.MEM.SW_NOACCESS" + desc: "The life cycle partition is not directly readable nor writable via software." + } + { name: "ACCESS.CTRL.MUBI", + desc: "The access control signals going from the partitions to the DAI are MUBI encoded." + } + { name: "TOKEN_VALID.CTRL.MUBI", + desc: "The token valid signals going to the life cycle controller are MUBI encoded." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "The life cycle control signals are multibit encoded." + } + { name: "DIRECT_ACCESS.CONFIG.REGWEN", + desc: "The direct access CSRs are REGWEN protected." + } + { name: "CHECK_TRIGGER.CONFIG.REGWEN", + desc: "The check trigger CSR is REGWEN protected." + } + { name: "CHECK.CONFIG.REGWEN", + desc: "The check CSR is REGWEN protected." + } + ] + + features: [ + { + name: "OTP_CTRL.PARTITION.VENDOR_TEST" + desc: '''Vendor test partition is used for OTP programming smoke check during manufacturing flow. + In this partition, ECC uncorrectable errors will not lead to fatal errors and alerts. + Instead the error will be reported as correctable ECC error. + ''' + } + { + name: "OTP_CTRL.PARTITION.CREATOR_SW_CFG" + desc: '''During calibration stage, various parameters (clock, voltage, and timing sources) are calibrated and recorded to CREATOR_SW_CFG partition. + ''' + } + { + name: "OTP_CTRL.PARTITION.OWNER_SW_CFG" + desc: "Define attributes for rom code execution" + } + { + name: "OTP_CTRL.INIT" + desc: '''When power is up, OTP controller reads devices status. + After all reads complete, the controller performs integrity check on the HW_CFG* and SECRET partitions. + Once all integrity checks are complete, the controller marks outputs as valid. + ''' + } + { + name: "OTP_CTRL.ENTROPY_READ" + desc: '''Firmware can read entropy from ENTROPY_SRC block by configuring following field of HW_CFG* partition. + - EN_CSRNG_SW_APP_READ + ''' + } + { + name: "OTP_CTRL.KEY_DERIVATION" + desc: "OTP controller participate key derivation process by providing scramble key seed to SRAM_CTRL." + } + { + name: "OTP_CTRL.PROGRAM" + desc: '''All other partitions except life cycle partition are programmed through DAI interface. + And once non-zero digest is programmed to these partition, no further write access is allowed. + Life cycle partition is programmed by LC_CTRL. + ''' + } + { + name: "OTP_CTRL.PARTITION.SECRET0" + desc: "Test unlock tokens, Test exit token" + } + { + name: "OTP_CTRL.PARTITION.SECRET1" + desc: "SRAM scrambling key" + } + { + name: "OTP_CTRL.PARTITION.SECRET2" + desc: "RMA unlock token and creator root key" + } + { + name: "OTP_CTRL.PARTITION.LIFE_CYCLE" + desc: '''LC state, LC transition count. + This feature is owned by the LC_CTRL and cannot be tested well through the OTP_CTRL CSR interface. + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.READ_LOCK" + desc: '''Following partitions can be read lockable by CSR. + - VENDOR_TEST + - CREATOR_SW_CFG + - OWNER_SW_CFG + Following partitions can be read lockable by writing digest. + - SECRET0 + - SECRET1 + - RECRET2 + All read attempt to these partitions after read is locked will trigger AccessError (recoverable). + ''' + } + { + name: "OTP_CTRL.PARTITIONS_FEATURE.WRITE_LOCK" + desc: "All partitions except LIFE_CYCLE can be write lockable by writing digest." + } + { + name: "OTP_CTRL.ERROR_HANDLING.RECOVERABLE" + desc: "Recoverable error is created when unauthorized access attempt are detected via dai interface." + } + { + name: "OTP_CTRL.ERROR_HANDLING.FATAL" + desc: "Unrecoverable errors are created for uncorrectable ecc error, otp macro malfunction and unauthorized access via lc_ctrl." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CHECK_TIMEOUT" + desc: "Timeout value for the integrity and consistency checks." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.INTEGRITY_CHECK_PERIOD" + desc: "The interval which the digest of the partition is recomputed to check integrity of locked partition." + } + { + name: "OTP_CTRL.BACKGROUND_CHECK.CONSISTENCY_CHECK_PERIOD" + desc: "Re-read period of the buffer registers to ensure data is matched with the associated OTP partition." + } + ] + + /////////////// + // Registers // + /////////////// + + regwidth: "32", + registers: { + core: [ + //////////////////////// + // Ctrl / Status CSRs // + //////////////////////// + + { name: "STATUS", + desc: "OTP status register.", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + resval: 0, + tags: [ // OTP internal HW can modify status register + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "0" + name: "VENDOR_TEST_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "1" + name: "CREATOR_SW_CFG_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "2" + name: "OWNER_SW_CFG_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "3" + name: "OWNERSHIP_SLOT_STATE_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "4" + name: "ROT_CREATOR_AUTH_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "5" + name: "ROT_OWNER_AUTH_SLOT0_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "6" + name: "ROT_OWNER_AUTH_SLOT1_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "7" + name: "PLAT_INTEG_AUTH_SLOT0_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "8" + name: "PLAT_INTEG_AUTH_SLOT1_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "9" + name: "PLAT_OWNER_AUTH_SLOT0_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "10" + name: "PLAT_OWNER_AUTH_SLOT1_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "11" + name: "PLAT_OWNER_AUTH_SLOT2_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "12" + name: "PLAT_OWNER_AUTH_SLOT3_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "13" + name: "EXT_NVM_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "14" + name: "ROM_PATCH_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "15" + name: "HW_CFG0_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "16" + name: "HW_CFG1_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "17" + name: "SECRET0_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "18" + name: "SECRET1_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "19" + name: "SECRET2_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "20" + name: "SECRET3_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "21" + name: "LIFE_CYCLE_ERROR" + desc: ''' + Set to 1 if an error occurred in this partition. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "22" + name: "DAI_ERROR" + desc: ''' + Set to 1 if an error occurred in the DAI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "23" + name: "LCI_ERROR" + desc: ''' + Set to 1 if an error occurred in the LCI. + If set to 1, SW should check the !!ERR_CODE register at the corresponding index. + ''' + } + { bits: "24" + name: "TIMEOUT_ERROR" + desc: ''' + Set to 1 if an integrity or consistency check times out. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "25" + name: "LFSR_FSM_ERROR" + desc: ''' + Set to 1 if the LFSR timer FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "26" + name: "SCRAMBLING_FSM_ERROR" + desc: ''' + Set to 1 if the scrambling datapath FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "27" + name: "KEY_DERIV_FSM_ERROR" + desc: ''' + Set to 1 if the key derivation FSM has reached an invalid state. + This raises an fatal_check_error alert and is an unrecoverable error condition. + ''' + } + { bits: "28" + name: "BUS_INTEG_ERROR" + desc: ''' + This bit is set to 1 if a fatal bus integrity fault is detected. + This error triggers a fatal_bus_integ_error alert. + ''' + } + { bits: "29" + name: "DAI_IDLE" + desc: "Set to 1 if the DAI is idle and ready to accept commands." + } + { bits: "30" + name: "CHECK_PENDING" + desc: "Set to 1 if an integrity or consistency check triggered by the LFSR timer or via !!CHECK_TRIGGER is pending." + } + ] + } + { multireg: { + name: "ERR_CODE", + desc: ''' + This register holds information about error conditions that occurred in the agents + interacting with the OTP macro via the internal bus. The error codes should be checked + if the partitions, DAI or LCI flag an error in the !!STATUS register, or when an + !!INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error + interrupt, and in addition some errors may trigger either an fatal_macro_error or an + fatal_check_error alert. + ''', + count: "NumErrorEntries", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "AGENT", + compact: "false", + resval: 0, + tags: [ // OTP internal HW can modify the error code registers + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { + bits: "2:0" + enum: [ + { value: "0", + name: "NO_ERROR", + desc: ''' + No error condition has occurred. + ''' + }, + { value: "1", + name: "MACRO_ERROR", + desc: ''' + Returned if the OTP macro command was invalid or did not complete successfully + due to a macro malfunction. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "2", + name: "MACRO_ECC_CORR_ERROR", + desc: ''' + A correctable ECC error has occurred during an OTP read operation. + The corresponding controller automatically recovers from this error when + issuing a new command. + ''' + }, + { value: "3", + name: "MACRO_ECC_UNCORR_ERROR", + desc: ''' + An uncorrectable ECC error has occurred during an OTP read operation. + This error should never occur during normal operation and is not recoverable. + If this error is present this may be a sign that the device is malfunctioning. + This error triggers an fatal_macro_error alert. + ''' + }, + { value: "4", + name: "MACRO_WRITE_BLANK_ERROR", + desc: ''' + This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1. + The corresponding controller automatically recovers from this error when issuing a new command. + + Note however that the affected OTP word may be left in an inconsistent state if this error occurs. + This can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check). + + It is important that SW ensures that each word is only written once, since this can render the device useless. + ''' + }, + { value: "5", + name: "ACCESS_ERROR", + desc: ''' + This error indicates that a locked memory region has been accessed. + The corresponding controller automatically recovers from this error when issuing a new command. + ''' + }, + { value: "6", + name: "CHECK_FAIL_ERROR", + desc: ''' + An ECC, integrity or consistency mismatch has been detected in the buffer registers. + This error should never occur during normal operation and is not recoverable. + This error triggers an fatal_check_error alert. + ''' + }, + { value: "7", + name: "FSM_STATE_ERROR", + desc: ''' + The FSM of the corresponding controller has reached an invalid state, or the FSM has + been moved into a terminal error state due to an escalation action via lc_escalate_en_i. + This error should never occur during normal operation and is not recoverable. + If this error is present, this is a sign that the device has fallen victim to + an invasive attack. This error triggers an fatal_check_error alert. + ''' + }, + ] + } + ] + } + } + { name: "DIRECT_ACCESS_REGWEN", + desc: ''' + Register write enable for all direct access interface registers. + ''', + swaccess: "rw0c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + tags: [ // OTP internal HW will set this enable register to 0 when OTP is not under IDLE + // state, so could not auto-predict its value + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { + bits: "0", + desc: ''' + This bit controls whether the DAI registers can be written. + Write 0 to it in order to clear the bit. + + Note that the hardware also modulates this bit and sets it to 0 temporarily + during an OTP operation such that the corresponding address and data registers + cannot be modified while an operation is pending. The !!DAI_IDLE status bit + will also be set to 0 in such a case. + ''' + resval: 1, + }, + ] + }, + { name: "DIRECT_ACCESS_CMD", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // Write to DIRECT_ACCESS_CMD randomly might cause OTP_ERRORs and illegal sequences + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + name: "RD", + desc: ''' + Initiates a readout sequence that reads the location specified + by !!DIRECT_ACCESS_ADDRESS. The command places the data read into + !!DIRECT_ACCESS_RDATA_0 and !!DIRECT_ACCESS_RDATA_1 (for 64bit partitions). + ''' + } + { bits: "1", + name: "WR", + desc: ''' + Initiates a programming sequence that writes the data in !!DIRECT_ACCESS_WDATA_0 + and !!DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + { bits: "2", + name: "DIGEST", + desc: ''' + Initiates the digest calculation and locking sequence for the partition specified by + !!DIRECT_ACCESS_ADDRESS. + ''' + } + ] + } + { name: "DIRECT_ACCESS_ADDRESS", + desc: "Address register for direct accesses.", + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + resval: 0, + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The enable register "DIRECT_ACCESS_REGWEN" is HW controlled, + // so not able to predict this register value automatically + "excl:CsrNonInitTests:CsrExclCheck"], + fields: [ + { bits: "OtpByteAddrWidth-1:0", + desc: ''' + This is the address for the OTP word to be read or written through + the direct access interface. Note that the address is aligned to the access size + internally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored + for 64bit accesses. + + For the digest calculation command, set this register to the partition base offset. + ''' + } + ] + } + { multireg: { + name: "DIRECT_ACCESS_WDATA", + desc: '''Write data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is being written to. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "rw", + hwaccess: "hro", + hwqe: "false", + regwen: "DIRECT_ACCESS_REGWEN", + cname: "WORD", + resval: 0, + tags: [ // The value of this register is written from "DIRECT_ACCESS_RDATA", + // so could not predict this register value automatically + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "DIRECT_ACCESS_RDATA", + desc: '''Read data for direct accesses. + Hardware automatically determines the access granule (32bit or 64bit) based on which + partition is read from. + ''', + count: "NumDaiWords", // 2 x 32bit = 64bit + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + fields: [ + { bits: "31:0" + } + ] + } + }, + + ////////////////////////////////////// + // Integrity and Consistency Checks // + ////////////////////////////////////// + { name: "CHECK_TRIGGER_REGWEN", + desc: ''' + Register write enable for !!CHECK_TRIGGER. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, the !!CHECK_TRIGGER register cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TRIGGER", + desc: "Command register for direct accesses.", + swaccess: "r0w1c", + hwaccess: "hro", + hwqe: "true", + hwext: "true", + resval: 0, + regwen: "CHECK_TRIGGER_REGWEN", + fields: [ + { bits: "0", + name: "INTEGRITY", + desc: ''' + Writing 1 to this bit triggers an integrity check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via the interrupts and alerts. + ''' + } + { bits: "1", + name: "CONSISTENCY", + desc: ''' + Writing 1 to this bit triggers a consistency check. SW should monitor !!STATUS.CHECK_PENDING + and wait until the check has been completed. If there are any errors, those will be flagged + in the !!STATUS and !!ERR_CODE registers, and via interrupts and alerts. + ''' + } + ] + }, + { name: "CHECK_REGWEN", + desc: ''' + Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD. + ''', + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD registers cannot be written anymore. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CHECK_TIMEOUT", + desc: ''' + Timeout value for the integrity and consistency checks. + ''', + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + tags: [ // Do not write to this automatically, as it may trigger fatal alert, and cause + // escalation. + "excl:CsrAllTests:CsrExclWrite"], + fields: [ + { bits: "31:0", + desc: ''' + Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency + check does not complete within the timeout window, an error will be flagged in the !!STATUS register, + an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should + be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the + number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to + roughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the + safe side. A value of zero disables the timeout mechanism (default). + ''' + resval: 0, + }, + ] + }, + { name: "INTEGRITY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + Only applies to the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.INTEGRITY. + ''' + resval: "0" + } + ] + } + { name: "CONSISTENCY_CHECK_PERIOD", + desc: ''' + This value specifies the maximum period that can be generated pseudo-randomly. + This applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked. + ''' + swaccess: "rw", + hwaccess: "hro", + regwen: "CHECK_REGWEN", + fields: [ + { bits: "31:0", + desc: ''' + The pseudo-random period is generated using a 40bit LFSR internally, and this register defines + the bit mask to be applied to the LFSR output in order to limit its range. The value of this + register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. + A recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz. + A value of zero disables the timer (default). Note that a one-off check can always be triggered via + !!CHECK_TRIGGER.CONSISTENCY. + ''' + resval: "0" + } + ] + } + + //////////////////////////////////// + // Dynamic Locks of SW Parititons // + //////////////////////////////////// + { name: "VENDOR_TEST_READ_LOCK", + desc: ''' + Runtime read lock for the VENDOR_TEST partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the VENDOR_TEST partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "CREATOR_SW_CFG_READ_LOCK", + desc: ''' + Runtime read lock for the CREATOR_SW_CFG partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the CREATOR_SW_CFG partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "OWNER_SW_CFG_READ_LOCK", + desc: ''' + Runtime read lock for the OWNER_SW_CFG partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the OWNER_SW_CFG partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "OWNERSHIP_SLOT_STATE_READ_LOCK", + desc: ''' + Runtime read lock for the OWNERSHIP_SLOT_STATE partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the OWNERSHIP_SLOT_STATE partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "ROT_CREATOR_AUTH_READ_LOCK", + desc: ''' + Runtime read lock for the ROT_CREATOR_AUTH partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the ROT_CREATOR_AUTH partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "ROT_OWNER_AUTH_SLOT0_READ_LOCK", + desc: ''' + Runtime read lock for the ROT_OWNER_AUTH_SLOT0 partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the ROT_OWNER_AUTH_SLOT0 partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "ROT_OWNER_AUTH_SLOT1_READ_LOCK", + desc: ''' + Runtime read lock for the ROT_OWNER_AUTH_SLOT1 partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the ROT_OWNER_AUTH_SLOT1 partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "PLAT_INTEG_AUTH_SLOT0_READ_LOCK", + desc: ''' + Runtime read lock for the PLAT_INTEG_AUTH_SLOT0 partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the PLAT_INTEG_AUTH_SLOT0 partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "PLAT_INTEG_AUTH_SLOT1_READ_LOCK", + desc: ''' + Runtime read lock for the PLAT_INTEG_AUTH_SLOT1 partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the PLAT_INTEG_AUTH_SLOT1 partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "PLAT_OWNER_AUTH_SLOT0_READ_LOCK", + desc: ''' + Runtime read lock for the PLAT_OWNER_AUTH_SLOT0 partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the PLAT_OWNER_AUTH_SLOT0 partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "PLAT_OWNER_AUTH_SLOT1_READ_LOCK", + desc: ''' + Runtime read lock for the PLAT_OWNER_AUTH_SLOT1 partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the PLAT_OWNER_AUTH_SLOT1 partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "PLAT_OWNER_AUTH_SLOT2_READ_LOCK", + desc: ''' + Runtime read lock for the PLAT_OWNER_AUTH_SLOT2 partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the PLAT_OWNER_AUTH_SLOT2 partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "PLAT_OWNER_AUTH_SLOT3_READ_LOCK", + desc: ''' + Runtime read lock for the PLAT_OWNER_AUTH_SLOT3 partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the PLAT_OWNER_AUTH_SLOT3 partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "EXT_NVM_READ_LOCK", + desc: ''' + Runtime read lock for the EXT_NVM partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the EXT_NVM partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + { name: "ROM_PATCH_READ_LOCK", + desc: ''' + Runtime read lock for the ROM_PATCH partition. + ''', + swaccess: "rw0c", + hwaccess: "hro", + regwen: "DIRECT_ACCESS_REGWEN", + tags: [ // The value of this register can affect the read access of the this + // partition's memory window. Excluding this register from writing can ensure + // memories have read and write access. + "excl:CsrNonInitTests:CsrExclWrite"], + fields: [ + { bits: "0", + desc: ''' + When cleared to 0, read access to the ROM_PATCH partition is locked. + Write 0 to clear this bit. + ''' + resval: 1, + }, + ] + }, + + /////////////////////// + // Integrity Digests // + /////////////////////// + { multireg: { + name: "VENDOR_TEST_DIGEST", + desc: ''' + Integrity digest for the VENDOR_TEST partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the VENDOR_TEST partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "CREATOR_SW_CFG_DIGEST", + desc: ''' + Integrity digest for the CREATOR_SW_CFG partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the CREATOR_SW_CFG partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "OWNER_SW_CFG_DIGEST", + desc: ''' + Integrity digest for the OWNER_SW_CFG partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the OWNER_SW_CFG partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "ROT_CREATOR_AUTH_DIGEST", + desc: ''' + Integrity digest for the ROT_CREATOR_AUTH partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the ROT_CREATOR_AUTH partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "ROT_OWNER_AUTH_SLOT0_DIGEST", + desc: ''' + Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the ROT_OWNER_AUTH_SLOT0 partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "ROT_OWNER_AUTH_SLOT1_DIGEST", + desc: ''' + Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the ROT_OWNER_AUTH_SLOT1 partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "PLAT_INTEG_AUTH_SLOT0_DIGEST", + desc: ''' + Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the PLAT_INTEG_AUTH_SLOT0 partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "PLAT_INTEG_AUTH_SLOT1_DIGEST", + desc: ''' + Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the PLAT_INTEG_AUTH_SLOT1 partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "PLAT_OWNER_AUTH_SLOT0_DIGEST", + desc: ''' + Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the PLAT_OWNER_AUTH_SLOT0 partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "PLAT_OWNER_AUTH_SLOT1_DIGEST", + desc: ''' + Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the PLAT_OWNER_AUTH_SLOT1 partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "PLAT_OWNER_AUTH_SLOT2_DIGEST", + desc: ''' + Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the PLAT_OWNER_AUTH_SLOT2 partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "PLAT_OWNER_AUTH_SLOT3_DIGEST", + desc: ''' + Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the PLAT_OWNER_AUTH_SLOT3 partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "ROM_PATCH_DIGEST", + desc: ''' + Integrity digest for the ROM_PATCH partition. + The integrity digest is 0 by default. Software must write this + digest value via the direct access interface in order to lock the partition. + After a reset, write access to the ROM_PATCH partition is locked and + the digest becomes visible in this CSR. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "HW_CFG0_DIGEST", + desc: ''' + Integrity digest for the HW_CFG0 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "HW_CFG1_DIGEST", + desc: ''' + Integrity digest for the HW_CFG1 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET0_DIGEST", + desc: ''' + Integrity digest for the SECRET0 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET1_DIGEST", + desc: ''' + Integrity digest for the SECRET1 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET2_DIGEST", + desc: ''' + Integrity digest for the SECRET2 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + { multireg: { + name: "SECRET3_DIGEST", + desc: ''' + Integrity digest for the SECRET3 partition. + The integrity digest is 0 by default. The digest calculation can be triggered via the !!DIRECT_ACCESS_CMD. + After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. + ''', + count: "NumDigestWords", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + cname: "WORD", + resval: 0, + tags: [ // OTP internal HW will update status so can not auto-predict its value. + "excl:CsrAllTests:CsrExclCheck"], + fields: [ + { bits: "31:0" + } + ] + } + }, + + //////////////////////////////// + // Software Config Partitions // + //////////////////////////////// + { skipto: "0x4000" } + + { window: { + name: "SW_CFG_WINDOW" + items: "NumSwCfgWindowWords" + swaccess: "ro", + desc: ''' + Any read to this window directly maps to the corresponding offset in the creator and owner software + config partitions, and triggers an OTP readout of the bytes requested. Note that the transaction + will block until OTP readout has completed. + ''' + } + } + ], + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/otp_ctrl_sec_cm_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/otp_ctrl_sec_cm_testplan.hjson new file mode 100644 index 00000000000..650a36067a4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/otp_ctrl_sec_cm_testplan.hjson @@ -0,0 +1,303 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../otp_ctrl/data/otp_ctrl.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../otp_ctrl/data/otp_ctrl_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: "Verify the countermeasure(s) BUS.INTEGRITY." + stage: V2S + tests: ["otp_ctrl_tl_intg_err"] + } + { + name: sec_cm_secret_mem_scramble + desc: "Verify the countermeasure(s) SECRET.MEM.SCRAMBLE." + stage: V2S + tests: ["otp_ctrl_smoke"] + } + { + name: sec_cm_part_mem_digest + desc: "Verify the countermeasure(s) PART.MEM.DIGEST." + stage: V2S + tests: ["otp_ctrl_smoke"] + } + { + name: sec_cm_dai_fsm_sparse + desc: "Verify the countermeasure(s) DAI.FSM.SPARSE." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_kdi_fsm_sparse + desc: "Verify the countermeasure(s) KDI.FSM.SPARSE." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_lci_fsm_sparse + desc: "Verify the countermeasure(s) LCI.FSM.SPARSE." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_part_fsm_sparse + desc: "Verify the countermeasure(s) PART.FSM.SPARSE." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_scrmbl_fsm_sparse + desc: "Verify the countermeasure(s) SCRMBL.FSM.SPARSE." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_timer_fsm_sparse + desc: "Verify the countermeasure(s) TIMER.FSM.SPARSE." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_dai_ctr_redun + desc: "Verify the countermeasure(s) DAI.CTR.REDUN." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_kdi_seed_ctr_redun + desc: "Verify the countermeasure(s) KDI_SEED.CTR.REDUN." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_kdi_entropy_ctr_redun + desc: "Verify the countermeasure(s) KDI_ENTROPY.CTR.REDUN." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_lci_ctr_redun + desc: "Verify the countermeasure(s) LCI.CTR.REDUN." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_part_ctr_redun + desc: "Verify the countermeasure(s) PART.CTR.REDUN." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_scrmbl_ctr_redun + desc: "Verify the countermeasure(s) SCRMBL.CTR.REDUN." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_timer_integ_ctr_redun + desc: "Verify the countermeasure(s) TIMER_INTEG.CTR.REDUN." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_timer_cnsty_ctr_redun + desc: "Verify the countermeasure(s) TIMER_CNSTY.CTR.REDUN." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_timer_lfsr_redun + desc: "Verify the countermeasure(s) TIMER.LFSR.REDUN." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_dai_fsm_local_esc + desc: "Verify the countermeasure(s) DAI.FSM.LOCAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc", "otp_ctrl_sec_cm"] + } + { + name: sec_cm_lci_fsm_local_esc + desc: "Verify the countermeasure(s) LCI.FSM.LOCAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc"] + } + { + name: sec_cm_kdi_fsm_local_esc + desc: "Verify the countermeasure(s) KDI.FSM.LOCAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc"] + } + { + name: sec_cm_part_fsm_local_esc + desc: "Verify the countermeasure(s) PART.FSM.LOCAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc", "otp_ctrl_macro_errs"] + } + { + name: sec_cm_scrmbl_fsm_local_esc + desc: "Verify the countermeasure(s) SCRMBL.FSM.LOCAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc"] + } + { + name: sec_cm_timer_fsm_local_esc + desc: "Verify the countermeasure(s) TIMER.FSM.LOCAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc", "otp_ctrl_sec_cm"] + } + { + name: sec_cm_dai_fsm_global_esc + desc: "Verify the countermeasure(s) DAI.FSM.GLOBAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc", "otp_ctrl_sec_cm"] + } + { + name: sec_cm_lci_fsm_global_esc + desc: "Verify the countermeasure(s) LCI.FSM.GLOBAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc"] + } + { + name: sec_cm_kdi_fsm_global_esc + desc: "Verify the countermeasure(s) KDI.FSM.GLOBAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc"] + } + { + name: sec_cm_part_fsm_global_esc + desc: "Verify the countermeasure(s) PART.FSM.GLOBAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc", "otp_ctrl_macro_errs"] + } + { + name: sec_cm_scrmbl_fsm_global_esc + desc: "Verify the countermeasure(s) SCRMBL.FSM.GLOBAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc"] + } + { + name: sec_cm_timer_fsm_global_esc + desc: "Verify the countermeasure(s) TIMER.FSM.GLOBAL_ESC." + stage: V2S + tests: ["otp_ctrl_parallel_lc_esc", "otp_ctrl_sec_cm"] + } + { + name: sec_cm_part_data_reg_integrity + desc: "Verify the countermeasure(s) PART.DATA_REG.INTEGRITY." + stage: V2S + tests: ["otp_ctrl_init_fail"] + } + { + name: sec_cm_part_data_reg_bkgn_chk + desc: "Verify the countermeasure(s) PART.DATA_REG.BKGN_CHK." + stage: V2S + tests: ["otp_ctrl_check_fail"] + } + { + name: sec_cm_part_mem_regren + desc: "Verify the countermeasure(s) PART.MEM.REGREN." + stage: V2S + tests: ["otp_ctrl_dai_lock"] + } + { + name: sec_cm_part_mem_sw_unreadable + desc: "Verify the countermeasure(s) PART.MEM.SW_UNREADABLE." + stage: V2S + tests: ["otp_ctrl_dai_lock"] + } + { + name: sec_cm_part_mem_sw_unwritable + desc: "Verify the countermeasure(s) PART.MEM.SW_UNWRITABLE." + stage: V2S + tests: ["otp_ctrl_dai_lock"] + } + { + name: sec_cm_lc_part_mem_sw_noaccess + desc: "Verify the countermeasure(s) LC_PART.MEM.SW_NOACCESS." + stage: V2S + tests: ["otp_ctrl_dai_lock"] + } + { + name: sec_cm_access_ctrl_mubi + desc: "Verify the countermeasure(s) ACCESS.CTRL.MUBI." + stage: V2S + tests: ["otp_ctrl_dai_lock"] + } + { + name: sec_cm_token_valid_ctrl_mubi + desc: "Verify the countermeasure(s) TOKEN_VALID.CTRL.MUBI." + stage: V2S + tests: ["otp_ctrl_smoke"] + } + { + name: sec_cm_lc_ctrl_intersig_mubi + desc: "Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI." + stage: V2S + tests: ["otp_ctrl_dai_lock"] + } + { + name: sec_cm_test_bus_lc_gated + desc: "Verify the countermeasure(s) TEST.BUS.LC_GATED." + stage: V2S + tests: ["otp_ctrl_smoke"] + } + { + name: sec_cm_test_tl_lc_gate_fsm_sparse + desc: "Verify the countermeasure(s) TEST_TL_LC_GATE.FSM.SPARSE." + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: sec_cm_direct_access_config_regwen + desc: "Verify the countermeasure(s) DIRECT_ACCESS.CONFIG.REGWEN." + stage: V2S + tests: ["otp_ctrl_regwen"] + } + { + name: sec_cm_check_trigger_config_regwen + desc: "Verify the countermeasure(s) CHECK_TRIGGER.CONFIG.REGWEN." + stage: V2S + tests: ["otp_ctrl_smoke"] + } + { + name: sec_cm_check_config_regwen + desc: "Verify the countermeasure(s) CHECK.CONFIG.REGWEN." + stage: V2S + tests: ["otp_ctrl_smoke"] + } + { + name: sec_cm_macro_mem_integrity + desc: "Verify the countermeasure(s) MACRO.MEM.INTEGRITY." + stage: V2S + tests: ["otp_ctrl_macro_errs"] + } + { + name: sec_cm_macro_mem_cm + desc: "Verify the countermeasure(s) MACRO.MEM.CM." + stage: V2S + tests: ["N/A"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson new file mode 100644 index 00000000000..fa243c7b4ec --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/otp_ctrl_testplan.hjson @@ -0,0 +1,383 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "otp_ctrl" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/mem_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "otp_ctrl_sec_cm_testplan.hjson"] + testpoints: [ + { + name: wake_up + desc: ''' + Wake_up test walks through otp_ctrl's power-on initialization, read, program, and + digest functionalities. + + - drive pwrmgr's request pin to trigger OTP initialization after reset, check status + after OTP initialization + - write all-ones to a random address within OTP partition 0, wait until this operation + completes + - read out the random selected write address, check if the readout value is all-ones + - trigger a digest calculation for a Software partition, check if the OtpError + interrupt is set + - trigger a digest calculation for a non-software partition, expect operation completes + without the OtpError interrupt + - read out secrets through the hardware interfaces + ''' + stage: V1 + tests: ["otp_ctrl_wake_up"] + } + { + name: smoke + desc: ''' + OTP_CTRL smoke test provisions and locks partitions. + + - drive pwrmgr's request pin to trigger OTP initialization after reset, check status + after OTP initialization + - randomly read out keys pertaining to `key_manager`, `flash`, `sram`, `otbn` + - randomly issue LC program request + - write random values to random addresses within each OTP partition + - read out the random selected write addresses, check if the readout values are expected + - during read and write operations, check if direct_access_regwen is correctly set by HW + - perform a system-level reset and check corresponding CSRs are set correctly + - lock all partitions except life_cycle by triggering digest calculations + - read back and verify the digest + - perform a system-level reset to verify the corresponding CSRs exposing the digests + have been populated + + **Checks**: + - Assertion checks to ensure vendor specific I/Os: `otp_vendor_test_status_o`, + `otp_vendor_test_ctrl_i`, `cio_test_o`, and `cio_test_en_o` are connected currently + with `lc_dft_en_i` On and Off. + ''' + stage: V1 + tests: ["otp_ctrl_smoke"] + } + { + name: dai_access_partition_walk + desc: ''' + Similar to UVM's memory walk test, this test ensures every address in each partition + can be accessed successfully via DAI and TLUL interfaces according to its access policy. + ''' + stage: V2 + tests: ["otp_ctrl_partition_walk"] + } + { + name: init_fail + desc: ''' + Based on OTP_CTRL smoke test, this test creates OTP_CTRL's initialization failure: + - write and read OTP memory via DAI interface + - randomly issue DAI digest command to lock HW partitions + - keep writing to OTP memory via DAI interface without asserting reset + - if digests are not locked, backdoor inject ECC correctable or uncorrectable errors + - issue reset and power initialization + - if the injected errors are all correctable errors, disable the `lc_bypass_chk_en` + after LC program request to create an LC partition check failure + + If fatal error is triggered, this test will check: + - OTP initialization failure triggers fatal alert + - `status`, `intr_state`, `err_code` CSRs reflect correct fatal error + + If OTP initialization finished without any fatal error, this test will check: + - OTP initialization finishes with power init output goes to 1 + - `status`, `intr_state`, `err_code` CSRs reflect ECC correctable error + ''' + stage: V2 + tests: ["otp_ctrl_init_fail"] + } + { + name: partition_check + desc: ''' + Randomly program the partition check related CSRs including: + - `check_timeout` + - `integrity_check_period` + - `consistency_check_period` + - `check_trigger` + + Create a failure scenario by randomly picking one of these three methods: + - inject ECC errors into the OTP macro via backdoor + - set the `check_timeout` CSR with a very small value + - write to a random OTP partition after digest is issued but before reset is asserted + + **Checks**: + - the corresponding alerts are triggered + - the error_code register is set correctly + Note that due to limited simulation time, for background checks, this test only write + random value that is less than 20 to the check period. + ''' + stage: V2 + tests: ["otp_ctrl_check_fail", "otp_ctrl_background_chks"] + } + { + name: regwen_during_otp_init + desc: ''' + The `direct_access_regwen` is a RO register which controls the write-enable of other + registers. It is not verified by the common CSR tests. HW sets it to 0 when the DAI + interface is busy. + + Stimulus and checks: + - randomly read `direct_access_regwen` and verify that it returns 0 during OTP + initialization + - verify that the writes to the registers controlled by it do not go through during OTP + initialization + ''' + stage: V2 + tests: ["otp_ctrl_regwen"] + } + { + name: partition_lock + desc: ''' + This test will cover two methods of locking read and write: digest calculation and CSR + write. After locking the partitions, issue read or program sequences and check if the + operations are locked correctly, and check if the `AccessError` is set. + ''' + stage: V2 + tests: ["otp_ctrl_dai_lock"] + } + { + name: interface_key_check + desc: ''' + OTP_CTRL will generate keys to `flash`, `sram`, and `otbn` upon their requests. + Based on the DAI access sequence, this test will run key requests sequence in + parallel, and check if correct keys are generated. + ''' + stage: V2 + tests: ["otp_ctrl_parallel_key_req"] + } + { + name: lc_interactions + desc: ''' + Verify the protocols between OTP_CTRL and LC_CTRL. Based on the DAI access sequence, + run the following sequences in parallel: + + - request a LC state transition via the programming interface + - enable the `lc_escalation_en` signal + + **Checks**: + - if the LC program request has `AccessError`, check the LC program response sets + the `error` bit to 1 + - if `lc_escalation_en` is enabled, verify that alert is triggered and OTP_CTRL entered + terminal state + ''' + stage: V2 + tests: ["otp_ctrl_parallel_lc_req", "otp_ctrl_parallel_lc_esc"] + } + { name: otp_dai_errors + desc: ''' + Based on the otp_dai_lock test, this test will randomly run the following OTP errors: + - DAI interface writes non-blank OTP address + - DAI interface accesses LC partition + - DAI interface writes HW digests + - DAI interface writes non-empty memory + + **Checks**: + - `err_code` and `status` CSRs + - `otp_error` interrupt + ''' + stage: V2 + tests: ["otp_ctrl_dai_errs"] + } + { name: otp_macro_errors + desc: ''' + Randomly run the following OTP errors: + - MacroError + - MacroEccCorrError + - MacroEccUncorrError + + **Checks**: + - `err_code` and `status` CSRs + - `otp_error` interrupt + - if the error is unrecoverable, verify that alert is triggered and OTP_CTRL entered + terminal state + ''' + stage: V2 + tests: ["otp_ctrl_macro_errs"] + } + { + name: test_access + desc: ''' + This test checks if the test access to OTP macro is connected correctly. + + **Stimulus and Checks**: + - Write and check read results from the prim_tl_i/o. + - Ensure no error or alert occurs from DUT. + ''' + stage: V2 + tests: ["otp_ctrl_test_access"] + } + { + name: stress_all + desc: ''' + - combine above sequences in one test to run sequentially, except csr sequence + - randomly add reset between each sequence + ''' + stage: V2 + tests: ["{name}_stress_all"] + } + { + name: sec_cm_additional_check + desc: ''' + Verify the outcome of injecting faults to security countermeasures. + + Stimulus: + As mentioned in `prim_count_check`, `prim_fsm_check` and `prim_double_lfsr_check`. + + Checks: + - Check the value of status register according to where the fault is injected. + - Check OTP_CTRL is locked after the fatal fault injection by trying to access OTP_CTRL + via dai, kdi, and lci interfaces. + ''' + stage: V2S + tests: ["otp_ctrl_sec_cm"] + } + { + name: otp_ctrl_low_freq_read + desc: ''' + This test checks if OTP's read operation can operate successfully in a low clock + frequency before the clock is calibrated. + + **Stimulus and Checks**: + - Configure OTP_CTRL's clock to 6MHz low frequency. + - Backdoor write OTP memory. + - Use DAI access to read each memory address and compare if the value is correct. + - If DAI address is in a SW partition, read and check again via TLUL interface. + ''' + stage: V3 + tests: ["otp_ctrl_low_freq_read"] + } + ] + + covergroups: [ + { + name: power_on_cg + desc: '''Covers the following conditions when OTP_CTRL finishes power-on initialization: + - whether `lc_escalation_en` is On + - whether any partition (except life cycle partition) is locked + ''' + } + { + name: sram_req_cg + desc: '''Covers whether secret1 partition is locked during all `srams` key request.''' + } + { + name: otbn_req_cg + desc: '''Covers whether secret1 partition is locked during `otbn` key request.''' + } + { + name: lc_prog_cg + desc: '''Covers whether the error bit is set during LC program request.''' + } + { + name: keymgr_o_cg + desc: '''Covers the following conditions when scoreboard checks `keymgr_o` value: + - whether secret2 partition is locked + - whether `lc_seed_hw_rd_en_i` is On + ''' + } + { + name: req_dai_access_after_alert_cg + desc: '''Covers if sequence issued various DAI requests after any fatal alert is + triggered.''' + } + { + name: issue_checks_after_alert_cg + desc: '''Covers if sequence issued various OTP_CTRL's background checks after any fatal alert + is triggered.''' + } + { + name: csr_rd_after_alert_cg + desc: '''Covers if the following CSRs are being read and the value is checked in scoreboard + after any fatal alert is triggered: + - unbuffered partitions' digest CSRs + - HW partition's digest CSRs + - secrets partitions' digest CSRs + - direct_access read data CSRs + - status CSR + - error_code CSR + ''' + } + { + name: dai_err_code_cg + desc: '''Covers all applicable error codes in DAI, and cross each error code with all + 7 partitions.''' + } + { + name: lci_err_code_cg + desc: '''Covers all applicable error codes in LCI.''' + } + { + name: unbuf_err_code_cg + desc: '''This is an array of covergroups to cover all applicable error codes in three + unbuffered partitions.''' + } + { + name: buf_err_code_cg + desc: '''This is an array of covergroups to cover all applicable error codes in five + buffered partitions.''' + } + { + name: unbuf_access_lock_cg_wrap_cg + desc: '''This is an array of covergroups to cover lock conditions below in three + unbuffered partitions: + - the partition is write-locked + - the partition is read-locked + - the current operation type + Then cross the three coverpoints.''' + } + { + name: dai_access_secret2_cg + desc: '''Covers whether `lc_creator_seed_sw_rw_en` is On during any DAI accesses.''' + } + { + name: status_csr_cg + desc: '''Covers the value of every bit in `status` CSR.''' + } + // The following covergroups are implemented in `otp_ctrl_cov_if.sv`. + { + name: lc_esc_en_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether LC program request is in progress + - whether DAI interface is busy + ''' + } + { + name: sram_0_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + { + name: sram_1_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + { + name: otbn_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + { + name: lc_prog_req_condition_cg + desc: '''Covers the following conditions when `lc_escalation_en` is On: + - whether any key requests is in progress + - whether DAI interface is busy + - whether lc_esc_en is On + ''' + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/top_darjeeling_no_ibex_otp_ctrl.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/top_darjeeling_no_ibex_otp_ctrl.ipconfig.hjson new file mode 100644 index 00000000000..b107647ec08 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data/top_darjeeling_no_ibex_otp_ctrl.ipconfig.hjson @@ -0,0 +1,1982 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_otp_ctrl + param_values: + { + otp_mmap: + { + seed: 36021179872380457113239299468132194022238108125576166239904535336103582949069 + otp: + { + width: 2 + depth: 8192 + size: 16384 + addr_width: 13 + byte_addr_width: 14 + } + scrambling: + { + key_size: 16 + iv_size: 8 + cnst_size: 16 + keys: + [ + { + name: Secret0Key + value: 79261096542507317550041524418378318810 + } + { + name: Secret1Key + value: 318985785134653313354004803705056942690 + } + { + name: Secret2Key + value: 177669530988656006400383198120896388291 + } + { + name: Secret3Key + value: 253454544458117277620971692296657999195 + } + ] + digests: + [ + { + name: CnstyDigest + iv_value: 5573918854495152458 + cnst_value: 298124614738804023684088847145512094502 + } + { + name: SramDataKey + iv_value: 13142649492737956675 + cnst_value: 15226184123672563655096903138034867314 + } + ] + } + partitions: + [ + { + name: VENDOR_TEST + variant: Unbuffered + absorb: false + size: 64 + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: false + bkout_type: false + items: + [ + { + name: SCRATCH + size: 56 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 0 + } + { + name: VENDOR_TEST_DIGEST + size: 8 + offset: 56 + ismubi: false + isdigest: true + inv_default: 10810310715135719883 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: + ''' + Vendor test partition. + This is reserved for manufacturing smoke checks. The OTP wrapper + control logic inside prim_otp is allowed to read/write to this + region. ECC uncorrectable errors seen on the functional prim_otp + interface will not lead to an alert for this partition. + Instead, such errors will be reported as correctable ECC errors. + ''' + iskeymgr_creator: false + iskeymgr_owner: false + offset: 0 + } + { + name: CREATOR_SW_CFG + variant: Unbuffered + absorb: false + size: 320 + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: CREATOR_SW_CFG_AST_CFG + size: 124 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 64 + } + { + name: CREATOR_SW_CFG_AST_INIT_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 188 + } + { + name: CREATOR_SW_CFG_OVERRIDES + size: 32 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 192 + } + { + name: CREATOR_SW_CFG_ROM_EXT_SKU + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 224 + } + { + name: CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 228 + } + { + name: CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN + size: 8 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 232 + } + { + name: CREATOR_SW_CFG_SIGVERIFY_SPX_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 240 + } + { + name: CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN + size: 8 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 244 + } + { + name: CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 252 + } + { + name: CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 256 + } + { + name: CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 260 + } + { + name: CREATOR_SW_CFG_RNG_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 264 + } + { + name: CREATOR_SW_CFG_JITTER_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 268 + } + { + name: CREATOR_SW_CFG_RET_RAM_RESET_MASK + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 272 + } + { + name: CREATOR_SW_CFG_MANUF_STATE + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 276 + } + { + name: CREATOR_SW_CFG_ROM_EXEC_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 280 + } + { + name: CREATOR_SW_CFG_CPUCTRL + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 284 + } + { + name: CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 288 + } + { + name: CREATOR_SW_CFG_MIN_SEC_VER_BL0 + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 292 + } + { + name: CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 296 + } + { + name: CREATOR_SW_CFG_RMA_SPIN_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 300 + } + { + name: CREATOR_SW_CFG_RMA_SPIN_CYCLES + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 304 + } + { + name: CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 308 + } + { + name: CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 312 + } + { + name: CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 316 + } + { + name: CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 320 + } + { + name: CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 324 + } + { + name: CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 328 + } + { + name: CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 332 + } + { + name: CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 336 + } + { + name: CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 340 + } + { + name: CREATOR_SW_CFG_RNG_ALERT_THRESHOLD + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 344 + } + { + name: CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 348 + } + { + name: CREATOR_SW_CFG_SRAM_KEY_RENEW_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 352 + } + { + name: CREATOR_SW_CFG_DIGEST + size: 8 + offset: 376 + ismubi: false + isdigest: true + inv_default: 14728343938218768996 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: + ''' + Software configuration partition. + This is for device-specific calibration data. For example, clock, + LDO, RNG. + ''' + iskeymgr_creator: false + iskeymgr_owner: false + offset: 64 + } + { + name: OWNER_SW_CFG + variant: Unbuffered + absorb: false + size: 632 + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: OWNER_SW_CFG_ROM_ERROR_REPORTING + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 384 + } + { + name: OWNER_SW_CFG_ROM_BOOTSTRAP_DIS + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 388 + } + { + name: OWNER_SW_CFG_ROM_ALERT_CLASS_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 392 + } + { + name: OWNER_SW_CFG_ROM_ALERT_ESCALATION + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 396 + } + { + name: OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION + size: 400 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 400 + } + { + name: OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION + size: 64 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 800 + } + { + name: OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH + size: 16 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 864 + } + { + name: OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES + size: 16 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 880 + } + { + name: OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES + size: 64 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 896 + } + { + name: OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 960 + } + { + name: OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 964 + } + { + name: OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 968 + } + { + name: OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 972 + } + { + name: OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 976 + } + { + name: OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 980 + } + { + name: OWNER_SW_CFG_MANUF_STATE + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 984 + } + { + name: OWNER_SW_CFG_ROM_RSTMGR_INFO_EN + size: 4 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 988 + } + { + name: OWNER_SW_CFG_DIGEST + size: 8 + offset: 1008 + ismubi: false + isdigest: true + inv_default: 4499762633768516743 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: + ''' + Software configuration partition. + This contains data that changes software behavior in the ROM, for + example enabling defensive features in ROM or selecting failure + modes if verification fails. + ''' + iskeymgr_creator: false + iskeymgr_owner: false + offset: 384 + } + { + name: OWNERSHIP_SLOT_STATE + variant: Unbuffered + absorb: false + secret: false + sw_digest: false + hw_digest: false + write_lock: None + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH + size: 16 + desc: + ''' + Creator Ownership transfer state management + OWNERSHIP_ST_RAW: ownership not yet claimed (factory default) + OWNERSHIP_ST_LOCKED0: first ownership slot claimed + OWNERSHIP_ST_RELEASED0: first ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED1: second ownership slot claimed + OWNERSHIP_ST_SCRAPPED: scrap state - terminal + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 1016 + } + { + name: OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH + size: 16 + desc: + ''' + Creator Ownership transfer state management + OWNERSHIP_ST_RAW: ownership not yet claimed (factory default) + OWNERSHIP_ST_LOCKED0: first ownership slot claimed + OWNERSHIP_ST_RELEASED0: first ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED1: second ownership slot claimed + OWNERSHIP_ST_SCRAPPED: scrap state - terminal + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 1032 + } + { + name: OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH + size: 16 + desc: + ''' + Creator Ownership transfer state management + OWNERSHIP_ST_RAW: ownership not yet claimed (factory default) + OWNERSHIP_ST_LOCKED0: first ownership slot claimed + OWNERSHIP_ST_RELEASED0: first ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED1: second ownership slot claimed + OWNERSHIP_ST_RELEASED1: second ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED2: third ownership slot claimed + OWNERSHIP_ST_RELEASED2: third ownership slot released (assets have been cleared, ready to xfer) + OWNERSHIP_ST_LOCKED3: fourth ownership slot claimed + OWNERSHIP_ST_SCRAPPED: scrap state - terminal + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 1048 + } + ] + desc: + ''' + SW managed asset ownership states partition. + + Multibit enable value for the tracking the asset ownership states. + Note that the states can be written multiple times in a device lifetime. + The values to be written are engineered in the same way as the LC_CTRL + state encoding words so that the ECC encoding remains valid even after + updating the values. + + The constants can be found in the lc_ctrl_state_pkg.sv package. + + The programming order has to adhere to: + + OWNERSHIP_ST_RAW (factory all-zero state) -> + OWNERSHIP_ST_LOCKED0 -> + OWNERSHIP_ST_RELEASED0 -> + ... + OWNERSHIP_ST_SCRAPPED + + Note that if there are less than 4 slots available the higher slot states + become logically equivalent to OWNERSHIP_SCRAPPED (firmware has to handle + this correctly). + ''' + iskeymgr_creator: false + iskeymgr_owner: false + size: 48 + offset: 1016 + } + { + name: ROT_CREATOR_AUTH + variant: Unbuffered + absorb: false + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY + size: 160 + desc: + ''' + Pub Key used to verify the manufacturing provisioning Software container + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 1064 + } + { + name: ROT_CREATOR_AUTH_OWNERSHIP_STATE + size: 4 + desc: + ''' + Creator Ownership transfer state management + UNLOCKED - ownership of ROT not yet claimed + LOCKED - ownership claimed and + RELEASED - Release ownership (assets have been cleared, ready to xfer) + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 1224 + } + { + name: ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROM2 OTP based patch + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + OTP based key (instead of ROM) facilitates easy key rotation + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 1228 + } + { + name: ROT_CREATOR_AUTH_KEYMANIFEST_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT CREATOR KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 1388 + } + { + name: ROT_CREATOR_AUTH_UNLOCK4XFER_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT CREATOR KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 1548 + } + { + name: ROT_CREATOR_AUTH_IDENTITY_CERT + size: 768 + desc: ROT Device Identity Certificate endorsed by Silicon Creator stable off device PKI + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 1708 + } + { + name: ROT_CREATOR_AUTH_DIGEST + size: 8 + offset: 2480 + ismubi: false + isdigest: true + inv_default: 11837082436279312982 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: Software managed creator partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 1424 + offset: 1064 + } + { + name: ROT_OWNER_AUTH_SLOT0 + variant: Unbuffered + absorb: false + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 2488 + } + { + name: ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 2648 + } + { + name: ROT_OWNER_AUTH_SLOT0_DIGEST + size: 8 + offset: 2808 + ismubi: false + isdigest: true + inv_default: 5280432312436422266 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: Software managed owner slot 0 partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 328 + offset: 2488 + } + { + name: ROT_OWNER_AUTH_SLOT1 + variant: Unbuffered + absorb: false + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 2816 + } + { + name: ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 2976 + } + { + name: ROT_OWNER_AUTH_SLOT1_DIGEST + size: 8 + offset: 3136 + ismubi: false + isdigest: true + inv_default: 234369395612291906 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: Software managed owner slot 1 partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 328 + offset: 2816 + } + { + name: PLAT_INTEG_AUTH_SLOT0 + variant: Unbuffered + absorb: false + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 3144 + } + { + name: PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 3304 + } + { + name: PLAT_INTEG_AUTH_SLOT0_DIGEST + size: 8 + offset: 3464 + ismubi: false + isdigest: true + inv_default: 16327599381873551525 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: Software managed platform integrator slot 0 partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 328 + offset: 3144 + } + { + name: PLAT_INTEG_AUTH_SLOT1 + variant: Unbuffered + absorb: false + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 3472 + } + { + name: PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 3632 + } + { + name: PLAT_INTEG_AUTH_SLOT1_DIGEST + size: 8 + offset: 3792 + ismubi: false + isdigest: true + inv_default: 1581155821231578393 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: Software managed platform integrator slot 1 partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 328 + offset: 3472 + } + { + name: PLAT_OWNER_AUTH_SLOT0 + variant: Unbuffered + absorb: false + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 3800 + } + { + name: PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 3960 + } + { + name: PLAT_OWNER_AUTH_SLOT0_DIGEST + size: 8 + offset: 4120 + ismubi: false + isdigest: true + inv_default: 2324999962355908533 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: Software managed platform owner slot 0 partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 328 + offset: 3800 + } + { + name: PLAT_OWNER_AUTH_SLOT1 + variant: Unbuffered + absorb: false + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 4128 + } + { + name: PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 4288 + } + { + name: PLAT_OWNER_AUTH_SLOT1_DIGEST + size: 8 + offset: 4448 + ismubi: false + isdigest: true + inv_default: 17905165971232536359 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: Software managed platform owner slot 1 partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 328 + offset: 4128 + } + { + name: PLAT_OWNER_AUTH_SLOT2 + variant: Unbuffered + absorb: false + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 4456 + } + { + name: PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 4616 + } + { + name: PLAT_OWNER_AUTH_SLOT2_DIGEST + size: 8 + offset: 4776 + ismubi: false + isdigest: true + inv_default: 13543634046774891762 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: Software managed platform owner slot 2 partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 328 + offset: 4456 + } + { + name: PLAT_OWNER_AUTH_SLOT3 + variant: Unbuffered + absorb: false + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + KM is used to provisioning additional keys in (external) flash + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + It is expected to be provisioned at Chip Probe stage when LC = TEST + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 4784 + } + { + name: PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY + size: 160 + desc: + ''' + Pub Key used to verify the ROT OWNER KEY MANIFEST. + Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. + 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} + Can be made part bound i.e. unique per part key cert + i.e. provisioning protected under proper lifecycle logistics / secure supplychain management + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 4944 + } + { + name: PLAT_OWNER_AUTH_SLOT3_DIGEST + size: 8 + offset: 5104 + ismubi: false + isdigest: true + inv_default: 13698041678974836896 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: Software managed platform owner slot 3 partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 328 + offset: 4784 + } + { + name: EXT_NVM + variant: Unbuffered + absorb: false + secret: false + sw_digest: false + hw_digest: false + write_lock: None + read_lock: CSR + key_sel: NoKey + integrity: false + bkout_type: false + items: + [ + { + name: EXT_NVM_ANTIREPLAY_FRESHNESS_CNT + size: 1024 + desc: + ''' + Fully SW managed patition + 1 bit (double bit allocated for redundancy - i.e. 2 physical bits for every logical bit) per day + assuming 10 year product lifecycle, allocating 8192 bits of freshness protection. + Implemented as thermometer encoding. Redundant bit programming & logical OR-ing managed by + software. Cannot be ECC protected since different bits in a fuse row are programmed at different times. + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 5112 + } + ] + desc: Anti-replay protection Strike Counters partition. + iskeymgr_creator: false + iskeymgr_owner: false + size: 1024 + offset: 5112 + } + { + name: ROM_PATCH + variant: Unbuffered + absorb: true + secret: false + sw_digest: true + hw_digest: false + write_lock: Digest + read_lock: CSR + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: ROM_PATCH_DATA + size: 9192 + desc: + ''' + Fully SW managed patition + ROM patch section + signed patch(es) + Each patch Contains header, signature, patch match/redirect configuration and patch code + Please refer to the ROM boot & patching specification for Integrated OT for more details + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + inv_default: 0 + offset: 6136 + } + { + name: ROM_PATCH_DIGEST + size: 8 + offset: 15976 + ismubi: false + isdigest: true + inv_default: 14153060542995762600 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: ROM Patch Code section. May contain multiple signed ROM2 patches. + iskeymgr_creator: false + iskeymgr_owner: false + size: 9848 + offset: 6136 + } + { + name: HW_CFG0 + variant: Buffered + secret: false + sw_digest: false + hw_digest: true + write_lock: Digest + read_lock: None + key_sel: NoKey + integrity: true + bkout_type: true + items: + [ + { + name: DEVICE_ID + size: 32 + inv_default: 65486323830591328446043131873451991034742910176203639508789261283277535351707 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 15984 + } + { + name: MANUF_STATE + size: 32 + inv_default: 45106338074792724304821242469256559359553488864622296623233734261107367140478 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16016 + } + { + name: HW_CFG0_DIGEST + size: 8 + offset: 16048 + ismubi: false + isdigest: true + inv_default: 10140889213198706984 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: + ''' + Hardware configuration 0 partition. + This contains + - DEVICE_ID: Unique device identifier. + - MANUF_STATE: Vector for capturing the manufacturing status. + ''' + absorb: false + iskeymgr_creator: false + iskeymgr_owner: false + size: 72 + offset: 15984 + } + { + name: HW_CFG1 + variant: Buffered + secret: false + sw_digest: false + hw_digest: true + write_lock: Digest + read_lock: None + key_sel: NoKey + integrity: true + bkout_type: true + items: + [ + { + name: SOC_DBG_STATE + size: 4 + inv_default: 0 + desc: + ''' + Multibit enable value for the SOC debug authorization. + Encoding: + SOC_DBG_RAW: this value is all-zeroes and will be the NOP state; + the LC controller will take precedence. + SOC_DBG_PRE_PROD: this is where the ROT will be in PROD state + but SOC will be in the pre-production unlock state + SOC_DBG_PROD: this is the state where the SOC moves to production, + and the challenge-response based authentication protocol is + required to unlock SOC debug features + ''' + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16056 + } + { + name: EN_CSRNG_SW_APP_READ + size: 1 + ismubi: true + inv_default: 105 + desc: + ''' + Enablement of CSRNG software application interface. A + kMultiBitBool8True value enables, while all other values + disable. Enablement is required to extract output from + CSRNG via software. + ''' + isdigest: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16060 + } + { + name: EN_SRAM_IFETCH + size: 1 + ismubi: true + inv_default: 105 + isdigest: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16061 + } + { + name: HW_CFG1_DIGEST + size: 8 + offset: 16064 + ismubi: false + isdigest: true + inv_default: 12267607958787918204 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: + ''' + Hardware configuration 1 partition. + This contains + EN_SRAM_IFETCH: Enable / disable execute from SRAM CSR switch. + SOC_DBG_STATE: Multibit enable value for the SOC debug authorization. + Note SOC_DBG_STATE will be written twice in a device lifetime. The + values to be written are engineered in the same way as the LC_CTRL + state encoding words: the ECC encoding remains valid even after + writing the second value on top of the first. + + The constants can be found in the lc_ctrl_state_pkg.sv package. + + The programming order has to adhere to: + + SOC_DBG_RAW -> SOC_DBG_PRE_PROD -> SOC_DBG_PROD. + ''' + absorb: false + iskeymgr_creator: false + iskeymgr_owner: false + size: 16 + offset: 16056 + } + { + name: SECRET0 + variant: Buffered + secret: true + sw_digest: false + hw_digest: true + write_lock: Digest + read_lock: Digest + key_sel: Secret0Key + integrity: true + bkout_type: false + items: + [ + { + name: TEST_UNLOCK_TOKEN + inv_default: 296711380900218015171120952374769035694 + size: 16 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16072 + } + { + name: TEST_EXIT_TOKEN + inv_default: 85161989055762428459190056485751105958 + size: 16 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16088 + } + { + name: SECRET0_DIGEST + size: 8 + offset: 16104 + ismubi: false + isdigest: true + inv_default: 7474818370217309020 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: + ''' + Secret partition 0. + This contains TEST lifecycle unlock tokens. + ''' + absorb: false + iskeymgr_creator: false + iskeymgr_owner: false + size: 40 + offset: 16072 + } + { + name: SECRET1 + variant: Buffered + secret: true + sw_digest: false + hw_digest: true + write_lock: Digest + read_lock: Digest + key_sel: Secret1Key + integrity: true + bkout_type: false + items: + [ + { + name: SRAM_DATA_KEY_SEED + inv_default: 241483977691757977923367841809339206658 + size: 16 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16112 + } + { + name: SECRET1_DIGEST + size: 8 + offset: 16128 + ismubi: false + isdigest: true + inv_default: 503838644190341903 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: + ''' + Secret partition 1. + This contains the SRAM scrambling key seed. + ''' + absorb: false + iskeymgr_creator: false + iskeymgr_owner: false + size: 24 + offset: 16112 + } + { + name: SECRET2 + variant: Buffered + secret: true + sw_digest: false + hw_digest: true + write_lock: Digest + read_lock: Digest + key_sel: Secret2Key + integrity: true + bkout_type: false + items: + [ + { + name: RMA_TOKEN + inv_default: 150353733052794565317978902093985221175 + size: 16 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16136 + } + { + name: CREATOR_ROOT_KEY_SHARE0 + inv_default: 99410155969389534278404680059562745406179175357375916509714598543499986721841 + size: 32 + iskeymgr_creator: true + isdigest: false + ismubi: false + iskeymgr_owner: false + offset: 16152 + } + { + name: CREATOR_ROOT_KEY_SHARE1 + inv_default: 7391079586881058628634247621478375370202976073106929415694865999470879218122 + size: 32 + iskeymgr_creator: true + isdigest: false + ismubi: false + iskeymgr_owner: false + offset: 16184 + } + { + name: CREATOR_SEED + inv_default: 101343852674351727018162199551656737563182757336330864139602722951993660546186 + size: 32 + iskeymgr_creator: true + isdigest: false + ismubi: false + iskeymgr_owner: false + offset: 16216 + } + { + name: SECRET2_DIGEST + size: 8 + offset: 16248 + ismubi: false + isdigest: true + inv_default: 4720744928697992353 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: + ''' + Secret partition 2. + This contains RMA unlock token, creator root key, and creator seed. + ''' + absorb: false + iskeymgr_creator: true + iskeymgr_owner: false + size: 120 + offset: 16136 + } + { + name: SECRET3 + variant: Buffered + secret: true + sw_digest: false + hw_digest: true + write_lock: Digest + read_lock: Digest + key_sel: Secret3Key + integrity: true + bkout_type: false + items: + [ + { + name: OWNER_SEED + inv_default: 94411066183681302546622452158435937172067990320926238136744201607471434110567 + size: 32 + iskeymgr_owner: true + isdigest: false + ismubi: false + iskeymgr_creator: false + offset: 16256 + } + { + name: SECRET3_DIGEST + size: 8 + offset: 16288 + ismubi: false + isdigest: true + inv_default: 4321159426593998838 + iskeymgr_creator: false + iskeymgr_owner: false + } + ] + desc: + ''' + Secret partition 3. + This contains the owner seed. + ''' + absorb: false + iskeymgr_creator: false + iskeymgr_owner: true + size: 40 + offset: 16256 + } + { + name: LIFE_CYCLE + variant: LifeCycle + secret: false + sw_digest: false + hw_digest: false + write_lock: None + read_lock: None + key_sel: NoKey + integrity: true + bkout_type: false + items: + [ + { + name: LC_TRANSITION_CNT + inv_default: 33022140810555236579668719714372256268318002252766629331496500220362429561986227479059320688363086585586147527154004 + size: 48 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16296 + } + { + name: LC_STATE + inv_default: 8976759128772494558324922685029952774256516170895712485227985363288402422095425232881151769395 + size: 40 + isdigest: false + ismubi: false + iskeymgr_creator: false + iskeymgr_owner: false + offset: 16344 + } + ] + desc: + ''' + Lifecycle partition. + This contains lifecycle transition count and state. This partition + cannot be locked since the life cycle state needs to advance to RMA + in-field. Note that while this partition is not marked secret, it + is not readable nor writeable via the DAI. Only the LC controller + can access this partition, and even via the LC controller it is not + possible to read the raw manufacturing life cycle state in encoded + form, since that encoding is considered a netlist secret. The LC + controller only exposes a decoded version of this state. + ''' + absorb: false + iskeymgr_creator: false + iskeymgr_owner: false + size: 88 + offset: 16296 + } + ] + } + enable_flash_key: false + topname: darjeeling_no_ibex + uniquified_modules: {} + module_instance_name: otp_ctrl + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/defs.bzl new file mode 100644 index 00000000000..8f0dc011eb4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/defs.bzl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +OTP_CTRL = opentitan_ip( + name = "otp_ctrl", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/data:otp_ctrl.hjson", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/checklist.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/checklist.md new file mode 100644 index 00000000000..117db7dd8d6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/checklist.md @@ -0,0 +1,271 @@ +# OTP_CTRL Checklist + + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [OTP_CTRL peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [OTP_CTRL Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Done | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#mem_instanced_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | N/A | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | Done | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | Waiver files approved by TC on 2024-08-08. +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | adk@ vogelpi@ +Review | Signoff date | Done | 2024-08-08 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTP_CTRL DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | [OTP_CTRL Testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | Exception for IP modules +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug) +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | `prim_tl_o/i` has a simple prim_tl_agent support, but need to be replaced with auto-generated tl_agent once reggen tool is optimized. +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | N/A | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | N/A | +Tests | [SIM_FW_SIMULATED][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | N/A | +Coverage | [FPV_COI_COVERAGE_V2][] | N/A | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Done | Waived `prim_alert_sender` and `prim_lfsr` +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | Reviewed on 05/24/2021 +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_VERIFIED][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/interfaces.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/interfaces.md new file mode 100644 index 00000000000..005c212869e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/interfaces.md @@ -0,0 +1,259 @@ +# Hardware Interfaces + +## Parameters + +The following table lists the instantiation parameters of OTP. +Note that parameters prefixed with `RndCnst` are random netlist constants that need to be regenerated via topgen before the tapeout (typically by the silicon creator). + +Parameter | Default (Max) | Top Earlgrey | Description +----------------------------|---------------|--------------|--------------- +`AlertAsyncOn` | 2'b11 | 2'b11 | +`RndCnstLfsrSeed` | (see RTL) | (see RTL) | Seed to be used for the internal 40bit partition check timer LFSR. This needs to be replaced by the silicon creator before the tapeout. +`RndCnstLfsrPerm` | (see RTL) | (see RTL) | Permutation to be used for the internal 40bit partition check timer LFSR. This needs to be replaced by the silicon creator before the tapeout. +`RndCnstKey` | (see RTL) | (see RTL) | Random scrambling keys for secret partitions, to be used in the [scrambling datapath](#scrambling-datapath). +`RndCnstDigestConst` | (see RTL) | (see RTL) | Random digest finalization constants, to be used in the [scrambling datapath](#scrambling-datapath). +`RndCnstDigestIV` | (see RTL) | (see RTL) | Random digest initialization vectors, to be used in the [scrambling datapath](#scrambling-datapath). +`RndCnstRawUnlockToken` | (see RTL) | (see RTL) | Global RAW unlock token to be used for the first life cycle transition. See also [conditional life cycle transitions](../../../../ip/lc_ctrl/doc/theory_of_operation.md#conditional-transitions). + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`otp_ctrl`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_edn_i`** +- Bus Device Interfaces (TL-UL): **`core_tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:-------------------------|:-----------------------------------|:--------|:------|--------:|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| edn | edn_pkg::edn | req_rsp | req | 1 | Entropy request to the entropy distribution network for LFSR reseeding and ephemeral key derivation. | +| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | rsp | 1 | Initialization request/acknowledge from/to power manager. | +| lc_otp_program | otp_ctrl_pkg::lc_otp_program | req_rsp | rsp | 1 | Life cycle state transition interface. | +| otp_lc_data | otp_ctrl_pkg::otp_lc_data | uni | req | 1 | Life cycle state output holding the current life cycle state, the value of the transition counter and the tokens needed for life cycle transitions. | +| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Life cycle escalation enable coming from life cycle controller. This signal moves all FSMs within OTP into the error state. | +| lc_creator_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Provision enable qualifier coming from life cycle controller. This signal enables SW read / write access to the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. | +| lc_owner_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Provision enable qualifier coming from life cycle controller. This signal enables SW read / write access to the OWNER_SEED. | +| lc_seed_hw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Seed read enable coming from life cycle controller. This signal enables HW read access to the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. | +| lc_check_byp_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | Life cycle partition check bypass signal. This signal causes the life cycle partition to bypass consistency checks during life cycle state transitions in order to prevent spurious consistency check failures. | +| otp_keymgr_key | otp_ctrl_pkg::otp_keymgr_key | uni | req | 1 | Key output to the key manager holding CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1. | +| sram_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | rsp | 4 | Array with key derivation interfaces for SRAM scrambling devices. | +| otbn_otp_key | otp_ctrl_pkg::otbn_otp_key | req_rsp | rsp | 1 | Key derivation interface for OTBN scrambling devices. | +| otp_broadcast | otp_ctrl_part_pkg::otp_broadcast | uni | req | 1 | Output of the HW partitions with breakout data types. | +| otp_macro | otp_ctrl_macro_pkg::otp_ctrl_macro | req_rsp | req | 1 | Data interface for the OTP macro. | +| core_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Interrupts + +| Interrupt Name | Type | Description | +|:-------------------|:-------|:-----------------------------------------------------------------------------------------------------------------------------| +| otp_operation_done | Event | A direct access command or digest calculation operation has completed. | +| otp_error | Event | An error has occurred in the OTP controller. Check the [`ERR_CODE`](registers.md#err_code) register to get more information. | + +## Security Alerts + +| Alert Name | Description | +|:----------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------| +| fatal_macro_error | This alert triggers if hardware detects an uncorrectable error during an OTP transaction, for example an uncorrectable ECC error in the OTP array. | +| fatal_check_error | This alert triggers if any of the background checks fails. This includes the digest checks and concurrent ECC checks in the buffer registers. | +| fatal_bus_integ_error | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | +| fatal_prim_otp_alert | Fatal alert triggered inside the OTP primitive, including fatal TL-UL bus integrity faults of the test interface. | +| recov_prim_otp_alert | Recoverable alert triggered inside the OTP primitive. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:-------------------------------------|:---------------------------------------------------------------------------------------------------------| +| OTP_CTRL.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| OTP_CTRL.SECRET.MEM.SCRAMBLE | Secret partitions are scrambled with a full-round PRESENT cipher. | +| OTP_CTRL.PART.MEM.DIGEST | Integrity of buffered partitions is ensured via a 64bit digest. | +| OTP_CTRL.DAI.FSM.SPARSE | The direct access interface FSM is sparsely encoded. | +| OTP_CTRL.KDI.FSM.SPARSE | The key derivation interface FSM is sparsely encoded. | +| OTP_CTRL.LCI.FSM.SPARSE | The life cycle interface FSM is sparsely encoded. | +| OTP_CTRL.PART.FSM.SPARSE | The partition FSMs are sparsely encoded. | +| OTP_CTRL.SCRMBL.FSM.SPARSE | The scramble datapath FSM is sparsely encoded. | +| OTP_CTRL.TIMER.FSM.SPARSE | The background check timer FSM is sparsely encoded. | +| OTP_CTRL.DAI.CTR.REDUN | The direct access interface address counter employs a cross-counter implementation. | +| OTP_CTRL.KDI_SEED.CTR.REDUN | The key derivation interface counter employs a cross-counter implementation. | +| OTP_CTRL.KDI_ENTROPY.CTR.REDUN | The key derivation entropy counter employs a cross-counter implementation. | +| OTP_CTRL.LCI.CTR.REDUN | The life cycle interface address counter employs a cross-counter implementation. | +| OTP_CTRL.PART.CTR.REDUN | The address counter of buffered partitions employs a cross-counter implementation. | +| OTP_CTRL.SCRMBL.CTR.REDUN | The srambling datapath counter employs a cross-counter implementation. | +| OTP_CTRL.TIMER_INTEG.CTR.REDUN | The background integrity check timer employs a duplicated counter implementation. | +| OTP_CTRL.TIMER_CNSTY.CTR.REDUN | The background consistency check timer employs a duplicated counter implementation. | +| OTP_CTRL.TIMER.LFSR.REDUN | The background check LFSR is duplicated. | +| OTP_CTRL.DAI.FSM.LOCAL_ESC | The direct access interface FSM is moved into an invalid state upon local escalation. | +| OTP_CTRL.LCI.FSM.LOCAL_ESC | The life cycle interface FSM is moved into an invalid state upon local escalation. | +| OTP_CTRL.KDI.FSM.LOCAL_ESC | The key derivation interface FSM is moved into an invalid state upon local escalation. | +| OTP_CTRL.PART.FSM.LOCAL_ESC | The partition FSMs are moved into an invalid state upon local escalation. | +| OTP_CTRL.SCRMBL.FSM.LOCAL_ESC | The scramble datapath FSM is moved into an invalid state upon local escalation. | +| OTP_CTRL.TIMER.FSM.LOCAL_ESC | The background check timer FSM is moved into an invalid state upon local escalation. | +| OTP_CTRL.DAI.FSM.GLOBAL_ESC | The direct access interface FSM is moved into an invalid state upon global escalation via life cycle. | +| OTP_CTRL.LCI.FSM.GLOBAL_ESC | The life cycle interface FSM is moved into an invalid state upon global escalation via life cycle. | +| OTP_CTRL.KDI.FSM.GLOBAL_ESC | The key derivation interface FSM is moved into an invalid state upon global escalation via life cycle. | +| OTP_CTRL.PART.FSM.GLOBAL_ESC | The partition FSMs are moved into an invalid state upon global escalation via life cycle. | +| OTP_CTRL.SCRMBL.FSM.GLOBAL_ESC | The scramble datapath FSM is moved into an invalid state upon global escalation via life cycle. | +| OTP_CTRL.TIMER.FSM.GLOBAL_ESC | The background check timer FSM is moved into an invalid state upon global escalation via life cycle. | +| OTP_CTRL.PART.DATA_REG.INTEGRITY | All partition buffer registers are protected with ECC on 64bit blocks. | +| OTP_CTRL.PART.DATA_REG.BKGN_CHK | The digest of buffered partitions is recomputed and checked at pseudorandom intervals in the background. | +| OTP_CTRL.PART.MEM.REGREN | Unbuffered ('software') partitions can be read-locked via a CSR until the next system reset. | +| OTP_CTRL.PART.MEM.SW_UNREADABLE | Secret buffered partitions become unreadable to software once they are locked via the digest. | +| OTP_CTRL.PART.MEM.SW_UNWRITABLE | All partitions become unwritable by software once they are locked via the digest. | +| OTP_CTRL.LC_PART.MEM.SW_NOACCESS | The life cycle partition is not directly readable nor writable via software. | +| OTP_CTRL.ACCESS.CTRL.MUBI | The access control signals going from the partitions to the DAI are MUBI encoded. | +| OTP_CTRL.TOKEN_VALID.CTRL.MUBI | The token valid signals going to the life cycle controller are MUBI encoded. | +| OTP_CTRL.LC_CTRL.INTERSIG.MUBI | The life cycle control signals are multibit encoded. | +| OTP_CTRL.DIRECT_ACCESS.CONFIG.REGWEN | The direct access CSRs are REGWEN protected. | +| OTP_CTRL.CHECK_TRIGGER.CONFIG.REGWEN | The check trigger CSR is REGWEN protected. | +| OTP_CTRL.CHECK.CONFIG.REGWEN | The check CSR is REGWEN protected. | + + + + +The OTP controller contains various interfaces that connect to other comportable IPs within OpenTitan, and these are briefly explained further below. + +### EDN Interface + +The entropy request interface that talks to EDN in order to fetch fresh entropy for ephemeral SRAM scrambling key derivation and the LFSR counters for background checks. +It is comprised of the `otp_edn_o` and `otp_edn_i` signals and follows a req / ack protocol. + +See also [EDN documentation](../../../../ip/edn/README.md). + +### Power Manager Interface + +The power manager interface is comprised of three signals overall: an initialization request (`pwr_otp_i.otp_init`), an initialization done response (`pwr_otp_o.otp_done`) and an idle indicator (`pwr_otp_o.otp_idle`). + +The power manager asserts `pwr_otp_i.otp_init` in order to signal to the OTP controller that it can start initialization, and the OTP controller signals completion of the initialization sequence by asserting `pwr_otp_o.otp_done` (the signal will remain high until reset). + +The idle indication signal `pwr_otp_o.otp_idle` indicates whether there is an ongoing write operation in the Direct Access Interface (DAI) or Life Cycle Interface (LCI), and the power manager uses that indication to determine whether a power down request needs to be aborted. + +Since the power manager may run in a different clock domain, the `pwr_otp_i.otp_init` signal is synchronized within the OTP controller. +The power manager is responsible for synchronizing the `pwr_otp_o.otp_done` and `pwr_otp_o.otp_idle` signals. + +See also [power manager documentation](../../pwrmgr/README.md). + +### Life Cycle Interfaces + +The interface to the life cycle controller can be split into three functional sub-interfaces (vendor test, state output, state transitions), and these are explained in more detail below. +Note that the OTP and life cycle controllers are supposed to be in the same clock domain, hence no additional signal synchronization is required. +See also [life cycle controller documentation](../../../../ip/lc_ctrl/README.md) for more details. + +#### Vendor Test Signals + +The `lc_otp_vendor_test_i` and `lc_otp_vendor_test_o` signals are connected to a 32bit control and a 32bit status register in the life cycle TAP, respectively, and are directly routed to the `prim_otp` wrapper. +These control and status signals may be used by the silicon creator to exercise the OTP programming smoke checks on the VENDOR_TEST partition. +The signals are gated with the life cycle state inside the life cycle controller such that they do not have any effect in production life cycle states. + +#### State, Counter and Token Output + +After initialization, the life cycle partition contents, as well as the tokens and personalization status is output to the life cycle controller via the `otp_lc_data_o` struct. +The life cycle controller uses this information to determine the life cycle state, and steer the appropriate qualifier signals. +Some of these qualifier signals (`lc_dft_en_i`, `lc_creator_seed_sw_rw_en_i`, `lc_seed_hw_rd_en_i` and `lc_escalate_en_i`) are fed back to the OTP controller in order to ungate testing logic to the OTP macro; enable SW write access to the `SECRET2` partition; enable hardware read access to the root key in the `SECRET2` partition; or to push the OTP controller into escalation state. + +A possible sequence for the signals described is illustrated below. +```wavejson +{signal: [ + {name: 'clk_i', wave: 'p.................'}, + {name: 'otp_lc_data_o.valid', wave: '0.|...|.1.|...|...'}, + {name: 'otp_lc_data_o.state', wave: '03|...|...|...|...'}, + {name: 'otp_lc_data_o.count', wave: '03|...|...|...|...'}, + {}, + {name: 'otp_lc_data_o.test_unlock_token', wave: '0.|...|.3.|...|...'}, + {name: 'otp_lc_data_o.test_exit_token', wave: '0.|...|.3.|...|...'}, + {name: 'otp_lc_data_o.test_tokens_valid', wave: '0.|...|.3.|...|...'}, + {}, + {name: 'otp_lc_data_o.rma_token', wave: '0.|.3.|...|...|...'}, + {name: 'otp_lc_data_o.rma_token_valid', wave: '0.|.3.|...|...|...'}, + {}, + {name: 'otp_lc_data_o.secrets_valid', wave: '0.|.3.|...|...|...'}, + {}, + {name: 'lc_creator_seed_sw_rw_en_i', wave: '0.|...|...|.4.|...'}, + {name: 'lc_seed_hw_rd_en_i', wave: '0.|...|...|.4.|...'}, + {name: 'lc_dft_en_i', wave: '0.|...|...|.4.|...'}, + {}, + {name: 'lc_escalate_en_i', wave: '0.|...|...|...|.5.'}, +]} +``` + +Note that the `otp_lc_data_o.valid` signal is only asserted after the `LIFE_CYCLE`, `SECRET0` and `SECRET2` partitions have successfully initialized, since the life cycle collateral contains information from all three partitions. +The `otp_lc_data_o.test_tokens_valid` and `otp_lc_data_o.rma_token_valid` signals are multibit valid signals indicating whether the corresponding tokens are valid. +The ``otp_lc_data_o.secrets_valid`` signal is a multibit valid signal that is set to `lc_ctrl_pkg::On` iff the `SECRET2` partition containing the root keys has been locked with a digest. + + +#### State Transitions + +In order to perform life cycle state transitions, the life cycle controller can present the new value of the life cycle state and counter via the programming interface as shown below: + +```wavejson +{signal: [ + {name: 'clk_i', wave: 'p.......'}, + {name: 'lc_otp_program_i.req', wave: '01.|..0.'}, + {name: 'lc_otp_program_i.state', wave: '03.|..0.'}, + {name: 'lc_otp_program_i.count', wave: '03.|..0.'}, + {name: 'lc_otp_program_o.ack', wave: '0..|.10.'}, + {name: 'lc_otp_program_o.err', wave: '0..|.40.'}, +]} +``` + +The request must remain asserted until the life cycle controller has responded. +An error is fatal and indicates that the OTP programming operation has failed. + +Note that the new state must not clear any bits that have already been programmed to OTP - i.e., the new state must be incrementally programmable on top of the previous state. +There are hence some implications on the life cycle encoding due to the ECC employed, see [life cycle state encoding](../../../../ip/lc_ctrl/doc/theory_of_operation.md#life-cycle-manufacturing-state-encodings) for details. + +Note that the behavior of the `lc_otp_program_i.otp_test_ctrl` signal is vendor-specific, and hence the signal is set to `x` in the timing diagram above. +The purpose of this signal is to control vendor-specific test mechanisms, and its value will only be forwarded to the OTP macro in RAW, TEST_* and RMA states. +In all other life cycle states this signal will be clamped to zero. + +### Interface to Key Manager + +The interface to the key manager is a simple struct that outputs the CREATOR_ROOT_KEY_SHARE0 and CREATOR_ROOT_KEY_SHARE1 keys via `otp_keymgr_key_o` if these secrets have been provisioned and locked (via CREATOR_KEY_LOCK). +Otherwise, this signal is tied to a random netlist constant. + +Since the key manager may run in a different clock domain, key manager is responsible for synchronizing the `otp_keymgr_key_o` signals. + +### Interfaces to SRAM and OTBN Scramblers + +The interfaces to the SRAM and OTBN scrambling devices follow a req / ack protocol, where the scrambling device first requests a new ephemeral key by asserting the request channel (`sram_otp_key_i[*]`, `otbn_otp_key_i`). +The OTP controller then fetches entropy from EDN and derives an ephemeral key using the SRAM_DATA_KEY_SEED and the [PRESENT scrambling data path](#scrambling-datapath). +Finally, the OTP controller returns a fresh ephemeral key via the response channels (`sram_otp_key_o[*]`, `otbn_otp_key_o`), which complete the req / ack handshake. +The wave diagram below illustrates this process for the OTBN scrambling device. + +```wavejson +{signal: [ + {name: 'clk_i', wave: 'p.......'}, + {name: 'otbn_otp_key_i.req', wave: '01.|..0.'}, + {name: 'otbn_otp_key_o.ack', wave: '0..|.10.'}, + {name: 'otbn_otp_key_o.nonce', wave: '0..|.30.'}, + {name: 'otbn_otp_key_o.key', wave: '0..|.30.'}, + {name: 'otbn_otp_key_o.seed_valid', wave: '0..|.10.'}, +]} +``` + +If the key seeds have not yet been provisioned, the keys are derived from all-zero constants, and the `*.seed_valid` signal will be set to 0 in the response. +The resulting scrambling key is still ephemeral (i.e., it is derived using entropy from CSRNG) and okay to be used. +It should be noted that this mechanism requires the EDN and entropy distribution network to be operational, and a key derivation request will block if they are not. + +Note that the req/ack protocol runs on the OTP clock. +It is the task of the scrambling device to synchronize the handshake protocol by instantiating the `prim_sync_reqack.sv` primitive as shown below. + +![OTP Key Req Ack](../doc/otp_ctrl_key_req_ack.svg) + +Note that the key and nonce output signals on the OTP controller side are guaranteed to remain stable for at least 62 OTP clock cycles after the `ack` signal is pulsed high, because the derivation of a 64bit half-key takes at least two passes through the 31-cycle PRESENT primitive. +Hence, if the scrambling device clock is faster or in the same order of magnitude as the OTP clock, the data can be directly sampled upon assertion of `src_ack_o`. +If the scrambling device runs on a significantly slower clock than OTP, an additional register (as indicated with dashed grey lines in the figure) has to be added. + +### Hardware Config Bits + +The bits of the HW_CFG* partitions are output via the `otp_ctrl_otp_broadcast_o` struct. +IPs that consume collateral stored in this partition shall connect to this struct via the topgen feature, and break out the appropriate bits by either accessing the correct index or using the struct fields. +These fields are autogenerated from the memory map items allocated to the HW_CFG* partitions, and the autogenerated struct type can be found in the `otp_ctrl_part_pkg.sv` package. +Note that it is the task of the receiving IP to synchronize these bits accordingly to the local clock. +For convenience, a valid bit is also available in that struct. +The valid bit indicates that the HW_CFG* partitions have initialized. + +## Parameter and Memory Map Changes after D3/V3 + +Note that all instantiation parameters can be changed without affecting D3/V3 status of the module. +Similarly, it is permissible to change the contents (partition size, adding and removing items) of the `CREATOR_SW_CFG`, `OWNER_SW_CFG` and `HW_CFG*` partitions without affecting D3 status. +Note however that partition size changes may affect V3 coverage metrics, hence if the size any of the above three partitions is changed, V3 needs to be re-assessed. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_behavioral_model.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_behavioral_model.svg new file mode 100644 index 00000000000..a5dab4a4bfc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_behavioral_model.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_blockdiag.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_blockdiag.svg new file mode 100644 index 00000000000..f2169883ce4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_blockdiag.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_buf_part_fsm.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_buf_part_fsm.svg new file mode 100644 index 00000000000..d06037468e3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_buf_part_fsm.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_dai_fsm.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_dai_fsm.svg new file mode 100644 index 00000000000..f84a80cc0f0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_dai_fsm.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_digest_mechanism.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_digest_mechanism.svg new file mode 100644 index 00000000000..dac2323afce --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_digest_mechanism.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_digests.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_digests.md new file mode 100644 index 00000000000..162f46f3f8f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_digests.md @@ -0,0 +1,26 @@ + + +| Digest Name | Affected Partition | Calculated by HW | +|:-------------------------------------------------------------------:|:---------------------:|:------------------:| +| [VENDOR_TEST_DIGEST](#Reg_vendor_test_digest_0) | VENDOR_TEST | no | +| [CREATOR_SW_CFG_DIGEST](#Reg_creator_sw_cfg_digest_0) | CREATOR_SW_CFG | no | +| [OWNER_SW_CFG_DIGEST](#Reg_owner_sw_cfg_digest_0) | OWNER_SW_CFG | no | +| [ROT_CREATOR_AUTH_DIGEST](#Reg_rot_creator_auth_digest_0) | ROT_CREATOR_AUTH | no | +| [ROT_OWNER_AUTH_SLOT0_DIGEST](#Reg_rot_owner_auth_slot0_digest_0) | ROT_OWNER_AUTH_SLOT0 | no | +| [ROT_OWNER_AUTH_SLOT1_DIGEST](#Reg_rot_owner_auth_slot1_digest_0) | ROT_OWNER_AUTH_SLOT1 | no | +| [PLAT_INTEG_AUTH_SLOT0_DIGEST](#Reg_plat_integ_auth_slot0_digest_0) | PLAT_INTEG_AUTH_SLOT0 | no | +| [PLAT_INTEG_AUTH_SLOT1_DIGEST](#Reg_plat_integ_auth_slot1_digest_0) | PLAT_INTEG_AUTH_SLOT1 | no | +| [PLAT_OWNER_AUTH_SLOT0_DIGEST](#Reg_plat_owner_auth_slot0_digest_0) | PLAT_OWNER_AUTH_SLOT0 | no | +| [PLAT_OWNER_AUTH_SLOT1_DIGEST](#Reg_plat_owner_auth_slot1_digest_0) | PLAT_OWNER_AUTH_SLOT1 | no | +| [PLAT_OWNER_AUTH_SLOT2_DIGEST](#Reg_plat_owner_auth_slot2_digest_0) | PLAT_OWNER_AUTH_SLOT2 | no | +| [PLAT_OWNER_AUTH_SLOT3_DIGEST](#Reg_plat_owner_auth_slot3_digest_0) | PLAT_OWNER_AUTH_SLOT3 | no | +| [ROM_PATCH_DIGEST](#Reg_rom_patch_digest_0) | ROM_PATCH | no | +| [HW_CFG0_DIGEST](#Reg_hw_cfg0_digest_0) | HW_CFG0 | yes | +| [HW_CFG1_DIGEST](#Reg_hw_cfg1_digest_0) | HW_CFG1 | yes | +| [SECRET0_DIGEST](#Reg_secret0_digest_0) | SECRET0 | yes | +| [SECRET1_DIGEST](#Reg_secret1_digest_0) | SECRET1 | yes | +| [SECRET2_DIGEST](#Reg_secret2_digest_0) | SECRET2 | yes | +| [SECRET3_DIGEST](#Reg_secret3_digest_0) | SECRET3 | yes | diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_field_descriptions.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_field_descriptions.md new file mode 100644 index 00000000000..39b026849eb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_field_descriptions.md @@ -0,0 +1,90 @@ + + +| Partition | Item | Size [B] | Description | +|:---------------------:|:-----------------------------------------------:|:----------:|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| CREATOR_SW_CFG | CREATOR_SW_CFG_AST_CFG | 124 | | +| | CREATOR_SW_CFG_AST_INIT_EN | 4 | | +| | CREATOR_SW_CFG_OVERRIDES | 32 | | +| | CREATOR_SW_CFG_ROM_EXT_SKU | 4 | | +| | CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN | 4 | | +| | CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN | 8 | | +| | CREATOR_SW_CFG_SIGVERIFY_SPX_EN | 4 | | +| | CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN | 8 | | +| | CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG | 4 | | +| | CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG | 4 | | +| | CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE | 4 | | +| | CREATOR_SW_CFG_RNG_EN | 4 | | +| | CREATOR_SW_CFG_JITTER_EN | 4 | | +| | CREATOR_SW_CFG_RET_RAM_RESET_MASK | 4 | | +| | CREATOR_SW_CFG_MANUF_STATE | 4 | | +| | CREATOR_SW_CFG_ROM_EXEC_EN | 4 | | +| | CREATOR_SW_CFG_CPUCTRL | 4 | | +| | CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT | 4 | | +| | CREATOR_SW_CFG_MIN_SEC_VER_BL0 | 4 | | +| | CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN | 4 | | +| | CREATOR_SW_CFG_RMA_SPIN_EN | 4 | | +| | CREATOR_SW_CFG_RMA_SPIN_CYCLES | 4 | | +| | CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS | 4 | | +| | CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS | 4 | | +| | CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS | 4 | | +| | CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS | 4 | | +| | CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS | 4 | | +| | CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS | 4 | | +| | CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS | 4 | | +| | CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS | 4 | | +| | CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS | 4 | | +| | CREATOR_SW_CFG_RNG_ALERT_THRESHOLD | 4 | | +| | CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST | 4 | | +| | CREATOR_SW_CFG_SRAM_KEY_RENEW_EN | 4 | | +| OWNER_SW_CFG | OWNER_SW_CFG_ROM_ERROR_REPORTING | 4 | | +| | OWNER_SW_CFG_ROM_BOOTSTRAP_DIS | 4 | | +| | OWNER_SW_CFG_ROM_ALERT_CLASS_EN | 4 | | +| | OWNER_SW_CFG_ROM_ALERT_ESCALATION | 4 | | +| | OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION | 400 | | +| | OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION | 64 | | +| | OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH | 16 | | +| | OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES | 16 | | +| | OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES | 64 | | +| | OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD | 4 | | +| | OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END | 4 | | +| | OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV | 4 | | +| | OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA | 4 | | +| | OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES | 4 | | +| | OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN | 4 | | +| | OWNER_SW_CFG_MANUF_STATE | 4 | | +| | OWNER_SW_CFG_ROM_RSTMGR_INFO_EN | 4 | | +| OWNERSHIP_SLOT_STATE | OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH | 16 | Creator Ownership transfer state management OWNERSHIP_ST_RAW: ownership not yet claimed (factory default) OWNERSHIP_ST_LOCKED0: first ownership slot claimed OWNERSHIP_ST_RELEASED0: first ownership slot released (assets have been cleared, ready to xfer) OWNERSHIP_ST_LOCKED1: second ownership slot claimed OWNERSHIP_ST_SCRAPPED: scrap state - terminal | +| | OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH | 16 | Creator Ownership transfer state management OWNERSHIP_ST_RAW: ownership not yet claimed (factory default) OWNERSHIP_ST_LOCKED0: first ownership slot claimed OWNERSHIP_ST_RELEASED0: first ownership slot released (assets have been cleared, ready to xfer) OWNERSHIP_ST_LOCKED1: second ownership slot claimed OWNERSHIP_ST_SCRAPPED: scrap state - terminal | +| | OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH | 16 | Creator Ownership transfer state management OWNERSHIP_ST_RAW: ownership not yet claimed (factory default) OWNERSHIP_ST_LOCKED0: first ownership slot claimed OWNERSHIP_ST_RELEASED0: first ownership slot released (assets have been cleared, ready to xfer) OWNERSHIP_ST_LOCKED1: second ownership slot claimed OWNERSHIP_ST_RELEASED1: second ownership slot released (assets have been cleared, ready to xfer) OWNERSHIP_ST_LOCKED2: third ownership slot claimed OWNERSHIP_ST_RELEASED2: third ownership slot released (assets have been cleared, ready to xfer) OWNERSHIP_ST_LOCKED3: fourth ownership slot claimed OWNERSHIP_ST_SCRAPPED: scrap state - terminal | +| ROT_CREATOR_AUTH | ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY | 160 | Pub Key used to verify the manufacturing provisioning Software container 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | ROT_CREATOR_AUTH_OWNERSHIP_STATE | 4 | Creator Ownership transfer state management UNLOCKED - ownership of ROT not yet claimed LOCKED - ownership claimed and RELEASED - Release ownership (assets have been cleared, ready to xfer) | +| | ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY | 160 | Pub Key used to verify the ROM2 OTP based patch 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management OTP based key (instead of ROM) facilitates easy key rotation | +| | ROT_CREATOR_AUTH_KEYMANIFEST_KEY | 160 | Pub Key used to verify the ROT CREATOR KEY MANIFEST. KM is used to provisioning additional keys in (external) flash 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | ROT_CREATOR_AUTH_UNLOCK4XFER_KEY | 160 | Pub Key used to verify the ROT CREATOR KEY MANIFEST. Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} Can be made part bound i.e. unique per part key cert i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | ROT_CREATOR_AUTH_IDENTITY_CERT | 768 | ROT Device Identity Certificate endorsed by Silicon Creator stable off device PKI | +| ROT_OWNER_AUTH_SLOT0 | ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. KM is used to provisioning additional keys in (external) flash 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} Can be made part bound i.e. unique per part key cert i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| ROT_OWNER_AUTH_SLOT1 | ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. KM is used to provisioning additional keys in (external) flash 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} Can be made part bound i.e. unique per part key cert i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| PLAT_INTEG_AUTH_SLOT0 | PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. KM is used to provisioning additional keys in (external) flash 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} Can be made part bound i.e. unique per part key cert i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| PLAT_INTEG_AUTH_SLOT1 | PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. KM is used to provisioning additional keys in (external) flash 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} Can be made part bound i.e. unique per part key cert i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| PLAT_OWNER_AUTH_SLOT0 | PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. KM is used to provisioning additional keys in (external) flash 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} Can be made part bound i.e. unique per part key cert i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| PLAT_OWNER_AUTH_SLOT1 | PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. KM is used to provisioning additional keys in (external) flash 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} Can be made part bound i.e. unique per part key cert i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| PLAT_OWNER_AUTH_SLOT2 | PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. KM is used to provisioning additional keys in (external) flash 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} Can be made part bound i.e. unique per part key cert i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| PLAT_OWNER_AUTH_SLOT3 | PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. KM is used to provisioning additional keys in (external) flash 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} It is expected to be provisioned at Chip Probe stage when LC = TEST i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| | PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY | 160 | Pub Key used to verify the ROT OWNER KEY MANIFEST. Used to authenticate the Unlock Ownership payload. Key Type: ECC NIST-P384 Curve. 160B = Custom Cert --> {PubKey:48, Signature:48, Device ID:32, metadata:16} Can be made part bound i.e. unique per part key cert i.e. provisioning protected under proper lifecycle logistics / secure supplychain management | +| EXT_NVM | EXT_NVM_ANTIREPLAY_FRESHNESS_CNT | 1024 | Fully SW managed patition 1 bit (double bit allocated for redundancy - i.e. 2 physical bits for every logical bit) per day assuming 10 year product lifecycle, allocating 8192 bits of freshness protection. Implemented as thermometer encoding. Redundant bit programming & logical OR-ing managed by software. Cannot be ECC protected since different bits in a fuse row are programmed at different times. | +| ROM_PATCH | ROM_PATCH_DATA | 9192 | Fully SW managed patition ROM patch section signed patch(es) Each patch Contains header, signature, patch match/redirect configuration and patch code Please refer to the ROM boot & patching specification for Integrated OT for more details | +| HW_CFG0 | DEVICE_ID | 32 | | +| | MANUF_STATE | 32 | | +| HW_CFG1 | SOC_DBG_STATE | 4 | Multibit enable value for the SOC debug authorization. Encoding: SOC_DBG_RAW: this value is all-zeroes and will be the NOP state; the LC controller will take precedence. SOC_DBG_PRE_PROD: this is where the ROT will be in PROD state but SOC will be in the pre-production unlock state SOC_DBG_PROD: this is the state where the SOC moves to production, and the challenge-response based authentication protocol is required to unlock SOC debug features | +| | EN_CSRNG_SW_APP_READ | 1 | Enablement of CSRNG software application interface. A kMultiBitBool8True value enables, while all other values disable. Enablement is required to extract output from CSRNG via software. | +| | EN_SRAM_IFETCH | 1 | | diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_kdi_fsm.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_kdi_fsm.svg new file mode 100644 index 00000000000..0f91a212c44 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_kdi_fsm.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_key_req_ack.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_key_req_ack.svg new file mode 100644 index 00000000000..c5cd58b5c15 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_key_req_ack.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_lci_fsm.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_lci_fsm.svg new file mode 100644 index 00000000000..63459e87af2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_lci_fsm.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_mmap.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_mmap.md new file mode 100644 index 00000000000..e5f98246a35 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_mmap.md @@ -0,0 +1,120 @@ + + +| Index | Partition | Size [B] | Access Granule | Item | Byte Address | Size [B] | +|:-------:|:---------------------:|:----------:|:----------------:|:-------------------------------------------------------------------:|:--------------:|:----------:| +| 0 | VENDOR_TEST | 64 | 32bit | SCRATCH | 0x000 | 56 | +| | | | 64bit | [VENDOR_TEST_DIGEST](#Reg_vendor_test_digest_0) | 0x038 | 8 | +| 1 | CREATOR_SW_CFG | 320 | 32bit | CREATOR_SW_CFG_AST_CFG | 0x040 | 124 | +| | | | 32bit | CREATOR_SW_CFG_AST_INIT_EN | 0x0BC | 4 | +| | | | 32bit | CREATOR_SW_CFG_OVERRIDES | 0x0C0 | 32 | +| | | | 32bit | CREATOR_SW_CFG_ROM_EXT_SKU | 0x0E0 | 4 | +| | | | 32bit | CREATOR_SW_CFG_SIGVERIFY_RSA_MOD_EXP_IBEX_EN | 0x0E4 | 4 | +| | | | 32bit | CREATOR_SW_CFG_SIGVERIFY_RSA_KEY_EN | 0x0E8 | 8 | +| | | | 32bit | CREATOR_SW_CFG_SIGVERIFY_SPX_EN | 0x0F0 | 4 | +| | | | 32bit | CREATOR_SW_CFG_SIGVERIFY_SPX_KEY_EN | 0x0F4 | 8 | +| | | | 32bit | CREATOR_SW_CFG_FLASH_DATA_DEFAULT_CFG | 0x0FC | 4 | +| | | | 32bit | CREATOR_SW_CFG_FLASH_INFO_BOOT_DATA_CFG | 0x100 | 4 | +| | | | 32bit | CREATOR_SW_CFG_FLASH_HW_INFO_CFG_OVERRIDE | 0x104 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_EN | 0x108 | 4 | +| | | | 32bit | CREATOR_SW_CFG_JITTER_EN | 0x10C | 4 | +| | | | 32bit | CREATOR_SW_CFG_RET_RAM_RESET_MASK | 0x110 | 4 | +| | | | 32bit | CREATOR_SW_CFG_MANUF_STATE | 0x114 | 4 | +| | | | 32bit | CREATOR_SW_CFG_ROM_EXEC_EN | 0x118 | 4 | +| | | | 32bit | CREATOR_SW_CFG_CPUCTRL | 0x11C | 4 | +| | | | 32bit | CREATOR_SW_CFG_MIN_SEC_VER_ROM_EXT | 0x120 | 4 | +| | | | 32bit | CREATOR_SW_CFG_MIN_SEC_VER_BL0 | 0x124 | 4 | +| | | | 32bit | CREATOR_SW_CFG_DEFAULT_BOOT_DATA_IN_PROD_EN | 0x128 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RMA_SPIN_EN | 0x12C | 4 | +| | | | 32bit | CREATOR_SW_CFG_RMA_SPIN_CYCLES | 0x130 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_REPCNT_THRESHOLDS | 0x134 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_REPCNTS_THRESHOLDS | 0x138 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_ADAPTP_HI_THRESHOLDS | 0x13C | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_ADAPTP_LO_THRESHOLDS | 0x140 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_BUCKET_THRESHOLDS | 0x144 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_MARKOV_HI_THRESHOLDS | 0x148 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_MARKOV_LO_THRESHOLDS | 0x14C | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_EXTHT_HI_THRESHOLDS | 0x150 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_EXTHT_LO_THRESHOLDS | 0x154 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_ALERT_THRESHOLD | 0x158 | 4 | +| | | | 32bit | CREATOR_SW_CFG_RNG_HEALTH_CONFIG_DIGEST | 0x15C | 4 | +| | | | 32bit | CREATOR_SW_CFG_SRAM_KEY_RENEW_EN | 0x160 | 4 | +| | | | 64bit | [CREATOR_SW_CFG_DIGEST](#Reg_creator_sw_cfg_digest_0) | 0x178 | 8 | +| 2 | OWNER_SW_CFG | 632 | 32bit | OWNER_SW_CFG_ROM_ERROR_REPORTING | 0x180 | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_BOOTSTRAP_DIS | 0x184 | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_CLASS_EN | 0x188 | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_ESCALATION | 0x18C | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_CLASSIFICATION | 0x190 | 400 | +| | | | 32bit | OWNER_SW_CFG_ROM_LOCAL_ALERT_CLASSIFICATION | 0x320 | 64 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_ACCUM_THRESH | 0x360 | 16 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_TIMEOUT_CYCLES | 0x370 | 16 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_PHASE_CYCLES | 0x380 | 64 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD | 0x3C0 | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_DIGEST_PROD_END | 0x3C4 | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_DIGEST_DEV | 0x3C8 | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_ALERT_DIGEST_RMA | 0x3CC | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_WATCHDOG_BITE_THRESHOLD_CYCLES | 0x3D0 | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_KEYMGR_ROM_EXT_MEAS_EN | 0x3D4 | 4 | +| | | | 32bit | OWNER_SW_CFG_MANUF_STATE | 0x3D8 | 4 | +| | | | 32bit | OWNER_SW_CFG_ROM_RSTMGR_INFO_EN | 0x3DC | 4 | +| | | | 64bit | [OWNER_SW_CFG_DIGEST](#Reg_owner_sw_cfg_digest_0) | 0x3F0 | 8 | +| 3 | OWNERSHIP_SLOT_STATE | 48 | 32bit | OWNERSHIP_SLOT_STATE_ROT_OWNER_AUTH | 0x3F8 | 16 | +| | | | 32bit | OWNERSHIP_SLOT_STATE_PLAT_INTEG_AUTH | 0x408 | 16 | +| | | | 32bit | OWNERSHIP_SLOT_STATE_PLAT_OWNER_AUTH | 0x418 | 16 | +| 4 | ROT_CREATOR_AUTH | 1424 | 32bit | ROT_CREATOR_AUTH_NON_RAW_MFW_CODESIGN_KEY | 0x428 | 160 | +| | | | 32bit | ROT_CREATOR_AUTH_OWNERSHIP_STATE | 0x4C8 | 4 | +| | | | 32bit | ROT_CREATOR_AUTH_ROM2_PATCH_SIGVERIFY_KEY | 0x4CC | 160 | +| | | | 32bit | ROT_CREATOR_AUTH_KEYMANIFEST_KEY | 0x56C | 160 | +| | | | 32bit | ROT_CREATOR_AUTH_UNLOCK4XFER_KEY | 0x60C | 160 | +| | | | 32bit | ROT_CREATOR_AUTH_IDENTITY_CERT | 0x6AC | 768 | +| | | | 64bit | [ROT_CREATOR_AUTH_DIGEST](#Reg_rot_creator_auth_digest_0) | 0x9B0 | 8 | +| 5 | ROT_OWNER_AUTH_SLOT0 | 328 | 32bit | ROT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY | 0x9B8 | 160 | +| | | | 32bit | ROT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY | 0xA58 | 160 | +| | | | 64bit | [ROT_OWNER_AUTH_SLOT0_DIGEST](#Reg_rot_owner_auth_slot0_digest_0) | 0xAF8 | 8 | +| 6 | ROT_OWNER_AUTH_SLOT1 | 328 | 32bit | ROT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY | 0xB00 | 160 | +| | | | 32bit | ROT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY | 0xBA0 | 160 | +| | | | 64bit | [ROT_OWNER_AUTH_SLOT1_DIGEST](#Reg_rot_owner_auth_slot1_digest_0) | 0xC40 | 8 | +| 7 | PLAT_INTEG_AUTH_SLOT0 | 328 | 32bit | PLAT_INTEG_AUTH_SLOT0_KEYMANIFEST_KEY | 0xC48 | 160 | +| | | | 32bit | PLAT_INTEG_AUTH_SLOT0_UNLOCK4XFER_KEY | 0xCE8 | 160 | +| | | | 64bit | [PLAT_INTEG_AUTH_SLOT0_DIGEST](#Reg_plat_integ_auth_slot0_digest_0) | 0xD88 | 8 | +| 8 | PLAT_INTEG_AUTH_SLOT1 | 328 | 32bit | PLAT_INTEG_AUTH_SLOT1_KEYMANIFEST_KEY | 0xD90 | 160 | +| | | | 32bit | PLAT_INTEG_AUTH_SLOT1_UNLOCK4XFER_KEY | 0xE30 | 160 | +| | | | 64bit | [PLAT_INTEG_AUTH_SLOT1_DIGEST](#Reg_plat_integ_auth_slot1_digest_0) | 0xED0 | 8 | +| 9 | PLAT_OWNER_AUTH_SLOT0 | 328 | 32bit | PLAT_OWNER_AUTH_SLOT0_KEYMANIFEST_KEY | 0xED8 | 160 | +| | | | 32bit | PLAT_OWNER_AUTH_SLOT0_UNLOCK4XFER_KEY | 0xF78 | 160 | +| | | | 64bit | [PLAT_OWNER_AUTH_SLOT0_DIGEST](#Reg_plat_owner_auth_slot0_digest_0) | 0x1018 | 8 | +| 10 | PLAT_OWNER_AUTH_SLOT1 | 328 | 32bit | PLAT_OWNER_AUTH_SLOT1_KEYMANIFEST_KEY | 0x1020 | 160 | +| | | | 32bit | PLAT_OWNER_AUTH_SLOT1_UNLOCK4XFER_KEY | 0x10C0 | 160 | +| | | | 64bit | [PLAT_OWNER_AUTH_SLOT1_DIGEST](#Reg_plat_owner_auth_slot1_digest_0) | 0x1160 | 8 | +| 11 | PLAT_OWNER_AUTH_SLOT2 | 328 | 32bit | PLAT_OWNER_AUTH_SLOT2_KEYMANIFEST_KEY | 0x1168 | 160 | +| | | | 32bit | PLAT_OWNER_AUTH_SLOT2_UNLOCK4XFER_KEY | 0x1208 | 160 | +| | | | 64bit | [PLAT_OWNER_AUTH_SLOT2_DIGEST](#Reg_plat_owner_auth_slot2_digest_0) | 0x12A8 | 8 | +| 12 | PLAT_OWNER_AUTH_SLOT3 | 328 | 32bit | PLAT_OWNER_AUTH_SLOT3_KEYMANIFEST_KEY | 0x12B0 | 160 | +| | | | 32bit | PLAT_OWNER_AUTH_SLOT3_UNLOCK4XFER_KEY | 0x1350 | 160 | +| | | | 64bit | [PLAT_OWNER_AUTH_SLOT3_DIGEST](#Reg_plat_owner_auth_slot3_digest_0) | 0x13F0 | 8 | +| 13 | EXT_NVM | 1024 | 32bit | EXT_NVM_ANTIREPLAY_FRESHNESS_CNT | 0x13F8 | 1024 | +| 14 | ROM_PATCH | 9848 | 32bit | ROM_PATCH_DATA | 0x17F8 | 9192 | +| | | | 64bit | [ROM_PATCH_DIGEST](#Reg_rom_patch_digest_0) | 0x3E68 | 8 | +| 15 | HW_CFG0 | 72 | 32bit | DEVICE_ID | 0x3E70 | 32 | +| | | | 32bit | MANUF_STATE | 0x3E90 | 32 | +| | | | 64bit | [HW_CFG0_DIGEST](#Reg_hw_cfg0_digest_0) | 0x3EB0 | 8 | +| 16 | HW_CFG1 | 16 | 32bit | SOC_DBG_STATE | 0x3EB8 | 4 | +| | | | 32bit | EN_CSRNG_SW_APP_READ | 0x3EBC | 1 | +| | | | 32bit | EN_SRAM_IFETCH | 0x3EBD | 1 | +| | | | 64bit | [HW_CFG1_DIGEST](#Reg_hw_cfg1_digest_0) | 0x3EC0 | 8 | +| 17 | SECRET0 | 40 | 64bit | TEST_UNLOCK_TOKEN | 0x3EC8 | 16 | +| | | | 64bit | TEST_EXIT_TOKEN | 0x3ED8 | 16 | +| | | | 64bit | [SECRET0_DIGEST](#Reg_secret0_digest_0) | 0x3EE8 | 8 | +| 18 | SECRET1 | 24 | 64bit | SRAM_DATA_KEY_SEED | 0x3EF0 | 16 | +| | | | 64bit | [SECRET1_DIGEST](#Reg_secret1_digest_0) | 0x3F00 | 8 | +| 19 | SECRET2 | 120 | 64bit | RMA_TOKEN | 0x3F08 | 16 | +| | | | 64bit | CREATOR_ROOT_KEY_SHARE0 | 0x3F18 | 32 | +| | | | 64bit | CREATOR_ROOT_KEY_SHARE1 | 0x3F38 | 32 | +| | | | 64bit | CREATOR_SEED | 0x3F58 | 32 | +| | | | 64bit | [SECRET2_DIGEST](#Reg_secret2_digest_0) | 0x3F78 | 8 | +| 20 | SECRET3 | 40 | 64bit | OWNER_SEED | 0x3F80 | 32 | +| | | | 64bit | [SECRET3_DIGEST](#Reg_secret3_digest_0) | 0x3FA0 | 8 | +| 21 | LIFE_CYCLE | 88 | 32bit | LC_TRANSITION_CNT | 0x3FA8 | 48 | +| | | | 32bit | LC_STATE | 0x3FD8 | 40 | diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_overview.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_overview.svg new file mode 100644 index 00000000000..ef2adaf1f99 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_overview.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_partitions.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_partitions.md new file mode 100644 index 00000000000..4e03e0b1a5d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_partitions.md @@ -0,0 +1,29 @@ + + +| Partition | Secret | Buffered | Integrity | WR Lockable | RD Lockable | Description | +|:---------------------:|:--------:|:----------:|:-----------:|:-------------:|:-------------:|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| VENDOR_TEST | no | no | no | yes (Digest) | yes (CSR) | Vendor test partition. This is reserved for manufacturing smoke checks. The OTP wrapper control logic inside prim_otp is allowed to read/write to this region. ECC uncorrectable errors seen on the functional prim_otp interface will not lead to an alert for this partition. Instead, such errors will be reported as correctable ECC errors. | +| CREATOR_SW_CFG | no | no | yes | yes (Digest) | yes (CSR) | Software configuration partition. This is for device-specific calibration data. For example, clock, LDO, RNG. | +| OWNER_SW_CFG | no | no | yes | yes (Digest) | yes (CSR) | Software configuration partition. This contains data that changes software behavior in the ROM, for example enabling defensive features in ROM or selecting failure modes if verification fails. | +| OWNERSHIP_SLOT_STATE | no | no | yes | no | yes (CSR) | SW managed asset ownership states partition. Multibit enable value for the tracking the asset ownership states. Note that the states can be written multiple times in a device lifetime. The values to be written are engineered in the same way as the LC_CTRL state encoding words so that the ECC encoding remains valid even after updating the values. The constants can be found in the lc_ctrl_state_pkg.sv package. The programming order has to adhere to: OWNERSHIP_ST_RAW (factory all-zero state) -> OWNERSHIP_ST_LOCKED0 -> OWNERSHIP_ST_RELEASED0 -> ... OWNERSHIP_ST_SCRAPPED Note that if there are less than 4 slots available the higher slot states become logically equivalent to OWNERSHIP_SCRAPPED (firmware has to handle this correctly). | +| ROT_CREATOR_AUTH | no | no | yes | yes (Digest) | yes (CSR) | Software managed creator partition. | +| ROT_OWNER_AUTH_SLOT0 | no | no | yes | yes (Digest) | yes (CSR) | Software managed owner slot 0 partition. | +| ROT_OWNER_AUTH_SLOT1 | no | no | yes | yes (Digest) | yes (CSR) | Software managed owner slot 1 partition. | +| PLAT_INTEG_AUTH_SLOT0 | no | no | yes | yes (Digest) | yes (CSR) | Software managed platform integrator slot 0 partition. | +| PLAT_INTEG_AUTH_SLOT1 | no | no | yes | yes (Digest) | yes (CSR) | Software managed platform integrator slot 1 partition. | +| PLAT_OWNER_AUTH_SLOT0 | no | no | yes | yes (Digest) | yes (CSR) | Software managed platform owner slot 0 partition. | +| PLAT_OWNER_AUTH_SLOT1 | no | no | yes | yes (Digest) | yes (CSR) | Software managed platform owner slot 1 partition. | +| PLAT_OWNER_AUTH_SLOT2 | no | no | yes | yes (Digest) | yes (CSR) | Software managed platform owner slot 2 partition. | +| PLAT_OWNER_AUTH_SLOT3 | no | no | yes | yes (Digest) | yes (CSR) | Software managed platform owner slot 3 partition. | +| EXT_NVM | no | no | no | no | yes (CSR) | Anti-replay protection Strike Counters partition. | +| ROM_PATCH | no | no | yes | yes (Digest) | yes (CSR) | ROM Patch Code section. May contain multiple signed ROM2 patches. | +| HW_CFG0 | no | yes | yes | yes (Digest) | no | Hardware configuration 0 partition. This contains - DEVICE_ID: Unique device identifier. - MANUF_STATE: Vector for capturing the manufacturing status. | +| HW_CFG1 | no | yes | yes | yes (Digest) | no | Hardware configuration 1 partition. This contains EN_SRAM_IFETCH: Enable / disable execute from SRAM CSR switch. SOC_DBG_STATE: Multibit enable value for the SOC debug authorization. Note SOC_DBG_STATE will be written twice in a device lifetime. The values to be written are engineered in the same way as the LC_CTRL state encoding words: the ECC encoding remains valid even after writing the second value on top of the first. The constants can be found in the lc_ctrl_state_pkg.sv package. The programming order has to adhere to: SOC_DBG_RAW -> SOC_DBG_PRE_PROD -> SOC_DBG_PROD. | +| SECRET0 | yes | yes | yes | yes (Digest) | yes (Digest) | Secret partition 0. This contains TEST lifecycle unlock tokens. | +| SECRET1 | yes | yes | yes | yes (Digest) | yes (Digest) | Secret partition 1. This contains the SRAM scrambling key seed. | +| SECRET2 | yes | yes | yes | yes (Digest) | yes (Digest) | Secret partition 2. This contains RMA unlock token, creator root key, and creator seed. | +| SECRET3 | yes | yes | yes | yes (Digest) | yes (Digest) | Secret partition 3. This contains the owner seed. | +| LIFE_CYCLE | no | yes | yes | no | no | Lifecycle partition. This contains lifecycle transition count and state. This partition cannot be locked since the life cycle state needs to advance to RMA in-field. Note that while this partition is not marked secret, it is not readable nor writeable via the DAI. Only the LC controller can access this partition, and even via the LC controller it is not possible to read the raw manufacturing life cycle state in encoded form, since that encoding is considered a netlist secret. The LC controller only exposes a decoded version of this state. | diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_prim_otp.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_prim_otp.svg new file mode 100644 index 00000000000..df6b31f078e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_prim_otp.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_unbuf_part_fsm.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_unbuf_part_fsm.svg new file mode 100644 index 00000000000..cd1a7ca1d70 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/otp_ctrl_unbuf_part_fsm.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/programmers_guide.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/programmers_guide.md new file mode 100644 index 00000000000..bf3a664f048 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/programmers_guide.md @@ -0,0 +1,262 @@ +# Programmer's Guide + +During provisioning and manufacturing, SW interacts with the OTP controller mostly through the Direct Access Interface (DAI), which is described below. +Afterwards during production, SW is expected to perform only read accesses via the exposed CSRs and CSR windows, since all write access to the partitions has been locked down. + +The following sections provide some general guidance, followed by an explanation of the DAI and a detailed OTP memory map. +Typical programming sequences are explained at the end of the Programmer's guide. + +## General Guidance + +### Initialization + +The OTP controller initializes automatically upon power-up and is fully operational by the time the processor boots. +The only initialization steps that SW should perform are: + +1. Check that the OTP controller has successfully initialized by reading [`STATUS`](registers.md#status). I.e., make sure that none of the ERROR bits are set, and that the DAI is idle ([`STATUS.DAI_IDLE`](registers.md#status)). +2. Set up the periodic background checks: + - Choose whether the periodic [background checks](theory_of_operation.md#partition-checks) shall be subject to a timeout by programming a nonzero timeout cycle count to [`CHECK_TIMEOUT`](registers.md#check_timeout). + In this case, the [`CHECK_TIMEOUT`](registers.md#check_timeout) register must be set before the [`INTEGRITY_CHECK_PERIOD`](registers.md#integrity_check_period) and [`CONSISTENCY_CHECK_PERIOD`](registers.md#consistency_check_period) registers (see next point). + - Enable periodic [background checks](theory_of_operation.md#partition-checks) by programming nonzero mask values to [`INTEGRITY_CHECK_PERIOD`](registers.md#integrity_check_period) and [`CONSISTENCY_CHECK_PERIOD`](registers.md#consistency_check_period). + - It is recommended to lock down the background check registers via [`CHECK_REGWEN`](registers.md#check_regwen), once the background checks have been set up. + +If needed, one-off integrity and consistency checks can be triggered via [`CHECK_TRIGGER`](registers.md#check_trigger). +If this functionality is not needed, it is recommended to lock down the trigger register via [`CHECK_TRIGGER_REGWEN`](registers.md#check_trigger_regwen). + +Later on during the boot process, SW may also choose to block read access to the SW managed partitions via the associated partition lock registers, e.g. [`CREATOR_SW_CFG_READ_LOCK`](registers.md#creator_sw_cfg_read_lock) or [`OWNER_SW_CFG_READ_LOCK`](registers.md#owner_sw_cfg_read_lock). + +### Reset Considerations + +It is important to note that values in OTP **can be corrupted** if a reset occurs during a programming operation. +This should be of minor concern for SW, however, since all partitions except for the LIFE_CYCLE partition are being provisioned in secure and controlled environments, and not in the field. +The LIFE_CYCLE partition is the only partition that is modified in the field - but that partition is entirely owned by the life cycle controller and not by SW. + +### Programming Already Programmed Regions + +OTP words cannot be programmed twice, and doing so may damage the memory array. +Hence the OTP controller performs a blank check and returns an error if a write operation is issued to an already programmed location. + +### Potential Side-Effects on Flash via Life Cycle + +It should be noted that the locked status of the partition holding the creator root key (i.e., the value of the [`SECRET2_DIGEST_0`](registers.md#secret2_digest)) determines the ID_STATUS of the device, which in turn determines SW accessibility of creator seed material in flash and OTP. +That means that creator-seed-related collateral needs to be provisioned to Flash **before** the OTP digest lockdown mechanism is triggered, since otherwise accessibility to the corresponding flash region is lost. +See the [life cycle controller documentation](../../../../ip/lc_ctrl/README.md#id-state-of-the-device) for more details. + +## Direct Access Interface + +OTP has to be programmed via the Direct Access Interface, which is comprised of the following CSRs: + +CSR Name | Description +-------------------------------------|------------------------------------ +[`DIRECT_ACCESS_WDATA_0`](registers.md#direct_access_wdata) | Low 32bit word to be written. +[`DIRECT_ACCESS_WDATA_1`](registers.md#direct_access_wdata) | High 32bit word to be written. +[`DIRECT_ACCESS_RDATA_0`](registers.md#direct_access_rdata) | Low 32bit word that has been read. +[`DIRECT_ACCESS_RDATA_1`](registers.md#direct_access_rdata) | High 32bit word that has been read. +[`DIRECT_ACCESS_ADDRESS`](registers.md#direct_access_address) | byte address for the access. +[`DIRECT_ACCESS_CMD`](registers.md#direct_access_cmd) | Command register to trigger a read or a write access. +[`DIRECT_ACCESS_REGWEN`](registers.md#direct_access_regwen) | Write protection register for DAI. + +See further below for a detailed [Memory Map](#direct-access-memory-map) of the address space accessible via the DAI. + +### Readout Sequence + +A typical readout sequence looks as follows: + +1. Check whether the DAI is idle by reading the [`STATUS`](registers.md#status) register. +2. Write the byte address for the access to [`DIRECT_ACCESS_ADDRESS`](registers.md#direct_access_address). +Note that the address is aligned with the granule, meaning that either 2 or 3 LSBs of the address are ignored, depending on whether the access granule is 32 or 64bit. +3. Trigger a read command by writing 0x1 to [`DIRECT_ACCESS_CMD`](registers.md#direct_access_cmd). +4. Poll the [`STATUS`](registers.md#status) until the DAI state goes back to idle. +Alternatively, the `otp_operation_done` interrupt can be enabled up to notify the processor once an access has completed. +5. If the status register flags a DAI error, additional handling is required (see [Error handling](#error-handling)). +6. If the region accessed has a 32bit access granule, the 32bit chunk of read data can be read from [`DIRECT_ACCESS_RDATA_0`](registers.md#direct_access_rdata). +If the region accessed has a 64bit access granule, the 64bit chunk of read data can be read from the [`DIRECT_ACCESS_RDATA_0`](registers.md#direct_access_rdata) and [`DIRECT_ACCESS_RDATA_1`](registers.md#direct_access_rdata) registers. +7. Go back to 1. and repeat until all data has been read. + +The hardware will set [`DIRECT_ACCESS_REGWEN`](registers.md#direct_access_regwen) to 0x0 while an operation is pending in order to temporarily lock write access to the CSRs registers. + +### Programming Sequence + +A typical programming sequence looks as follows: + +1. Check whether the DAI is idle by reading the [`STATUS`](registers.md#status) register. +2. If the region to be accessed has a 32bit access granule, place a 32bit chunk of data into [`DIRECT_ACCESS_WDATA_0`](registers.md#direct_access_wdata). +If the region to be accessed has a 64bit access granule, both the [`DIRECT_ACCESS_WDATA_0`](registers.md#direct_access_wdata) and [`DIRECT_ACCESS_WDATA_1`](registers.md#direct_access_wdata) registers have to be used. +3. Write the byte address for the access to [`DIRECT_ACCESS_ADDRESS`](registers.md#direct_access_address). +Note that the address is aligned with the granule, meaning that either 2 or 3 LSBs of the address are ignored, depending on whether the access granule is 32 or 64bit. +4. Trigger a write command by writing 0x2 to [`DIRECT_ACCESS_CMD`](registers.md#direct_access_cmd). +5. Poll the [`STATUS`](registers.md#status) until the DAI state goes back to idle. +Alternatively, the `otp_operation_done` interrupt can be enabled up to notify the processor once an access has completed. +6. If the status register flags a DAI error, additional handling is required (see [Error handling](#error-handling)). +7. Go back to 1. and repeat until all data has been written. + +The hardware will set [`DIRECT_ACCESS_REGWEN`](registers.md#direct_access_regwen) to 0x0 while an operation is pending in order to temporarily lock write access to the CSRs registers. + +Note that SW is responsible for keeping track of already programmed OTP word locations during the provisioning phase. +**It is imperative that SW does not write the same word location twice**, since this can lead to ECC inconsistencies, thereby potentially rendering the device useless. + +### Digest Calculation Sequence + +The hardware digest computation for the hardware and secret partitions can be triggered as follows: + +1. Check whether the DAI is idle by reading the [`STATUS`](registers.md#status) register. +3. Write the partition base address to [`DIRECT_ACCESS_ADDRESS`](registers.md#direct_access_address). +4. Trigger a digest calculation command by writing 0x4 to [`DIRECT_ACCESS_CMD`](registers.md#direct_access_cmd). +5. Poll the [`STATUS`](registers.md#status) until the DAI state goes back to idle. +Alternatively, the `otp_operation_done` interrupt can be enabled up to notify the processor once an access has completed. +6. If the status register flags a DAI error, additional handling is required (see [Error handling](#error-handling)). + +The hardware will set [`DIRECT_ACCESS_REGWEN`](registers.md#direct_access_regwen) to 0x0 while an operation is pending in order to temporarily lock write access to the CSRs registers. + +It should also be noted that the effect of locking a partition via the digest only takes effect **after** the next system reset. +To prevent integrity check failures SW must therefore ensure that no more programming operations are issued to the affected partition after initiating the digest calculation sequence. + +### Software Integrity Handling + +As opposed to buffered partitions, the digest and integrity handling of unbuffered partitions is entirely up to software. +The only hardware-assisted feature in unbuffered partitions is the digest lock, which locks write access to an unbuffered partition once a nonzero value has been programmed to the 64bit digest location. + +In a similar vein, it should be noted that the system-wide bus-integrity metadata does not travel alongside the data end-to-end in the OTP controller (i.e., the bus-integrity metadata bits are not stored into the OTP memory array). +This means that data written to and read from the OTP macro is not protected by the bus integrity feature at all stages. +In case of buffered partitions this does not pose a concern since data integrity in these partitions is checked via the hardware assisted digest mechanism. +In case of unbuffered partitions however, the data integrity checking is entirely up to software. +I.e., if data is read from an unbuffered partition (either through the DAI or CSR windows), software should perform an integrity check on that data. + +## Error Handling + +The agents that can access the OTP macro (DAI, LCI, buffered/unbuffered partitions) expose detailed error codes that can be used to root cause any failure. +The error codes are defined in the table below, and the corresponding `otp_err_e` enum type can be found in the `otp_ctrl_pkg`. +The table also lists which error codes are supported by which agent. + +Errors that are not "recoverable" are severe errors that move the corresponding partition or DAI/LCI FSM into a terminal error state, where no more commands can be accepted (a system reset is required to restore functionality in that case). +Errors that are "recoverable" are less severe and do not cause the FSM to jump into a terminal error state. + +Note that error codes that originate in the physical OTP macro are prefixed with `Macro*`. + +Error Code | Enum Name | Recoverable | DAI | LCI | Unbuf | Buf | Description +-----------|------------------------|-------------|-----|-----|-------|-------|------------- +0x0 | `NoError` | - | x | x | x | x | No error has occurred. +0x1 | `MacroError` | no | x | x | x | x | Returned if the OTP macro command did not complete successfully due to a macro malfunction. +0x2 | `MacroEccCorrError` | yes | x | - | x | x | A correctable ECC error has occurred during a read operation in the OTP macro. +0x3 | `MacroEccUncorrError` | no | x | - | x* | x | An uncorrectable ECC error has occurred during a read operation in the OTP macro. Note (*): This error is collapsed into `MacroEccCorrError` if the partition is a vendor test partition. It then becomes a recoverable error. +0x4 | `MacroWriteBlankError` | yes / no* | x | x | - | - | This error is returned if a write operation attempted to clear an already programmed bit location. Note (*): This error is recoverable if encountered in the DAI, but unrecoverable if encountered in the LCI. +0x5 | `AccessError` | yes | x | - | x | - | An access error has occurred (e.g. write to write-locked region, or read to a read-locked region). +0x6 | `CheckFailError` | no | - | - | x | x | An unrecoverable ECC, integrity or consistency error has been detected. +0x7 | `FsmStateError` | no | x | x | x | x | The FSM has been glitched into an invalid state, or escalation has been triggered and the FSM has been moved into a terminal error state. + +All non-zero error codes listed above trigger an `otp_error` interrupt. +In addition, all unrecoverable OTP `Macro*` errors (codes 0x1, 0x3) trigger a `fatal_macro_error` alert, while all remaining unrecoverable errors trigger a `fatal_check_error` alert. + +If software receives an `otp_error` interrupt, but all error codes read back as 0x0 (`NoError`), this should be treated as a fatal error condition, and the system should be shut down as soon as possible. + +Note that the `MacroWriteBlankError` will only be generated if the write attempt over already written data fails within the OTP macro after applying any means supported within it to enable a write on existing data, e.g., a bit-reversal option. +Also note that while this error is marked as a recoverable error, the affected OTP word may be in an inconsistent state after this error has been returned. +This can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check). +It is important that SW ensures that each word is only written once, since this can render the device useless. + +## Direct Access Memory Map + +The table below provides a detailed overview of the items stored in the OTP partitions. +Some of the items that are buffered in registers is readable via memory mapped CSRs, and these CSRs are linked in the table below. +Items that are not linked can only be accessed via the direct programming interface (if the partition is not locked via the corresponding digest). +It should be noted that CREATOR_SW_CFG and OWNER_SW_CFG are accessible through a memory mapped window, and content of these partitions is not buffered. +Hence, a read access to those windows will take in the order of 10-20 cycles until the read returns. + +Sizes below are specified in multiples of 32bit words. + +{{#include otp_ctrl_mmap.md}} + +Note that since the content in the SECRET* partitions are scrambled using a 64bit PRESENT cipher, read and write access through the DAI needs to occur at a 64bit granularity. +Also, all digests (no matter whether they are SW or HW digests) have an access granule of 64bit. + +The table below lists digests locations, and the corresponding locked partitions. + +{{#include otp_ctrl_digests.md}} + +Write access to the affected partition will be locked if the digest has a nonzero value. + +For the software partition digests, it is entirely up to software to decide on the digest algorithm to be used. +Hardware will determine the lock condition only based on whether a non-zero value is present at that location or not. + +For the hardware partitions, hardware calculates this digest and uses it for [background verification](theory_of_operation.md#partition-checks). +Digest calculation can be triggered via the DAI. + +Finally, it should be noted that the RMA_TOKEN and CREATOR_ROOT_KEY_SHARE0 / CREATOR_ROOT_KEY_SHARE1 items can only be programmed when the device is in the DEV, PROD, PROD_END and RMA stages. +Please consult the [life cycle controller documentation](../../../../ip/lc_ctrl/README.md) documentation for more information. + +## OTP Field Descriptions + +The table below describes what each field in the OTP partitions is used for. + +{{#include otp_ctrl_field_descriptions.md}} + +## Examples + +### Provisioning Items + +The following represents a typical provisioning sequence for items in all partitions (except for the LIFE_CYCLE partition, which is not software-programmable): + +1. [Program](#programming-sequence) the item in 32bit or 64bit chunks via the DAI. +2. [Read back](#readout-sequence) and verify the item via the DAI. +3. If the item is exposed via CSRs or a CSR window, perform a full-system reset and verify whether those fields are correctly populated. + +Note that any unrecoverable errors during the programming steps, or mismatches during the readback and verification steps indicate that the device might be malfunctioning (possibly due to fabrication defects) and hence the device may have to be scrapped. +This is however rare and should not happen after fabrication testing. + +### Locking Partitions + +Once a partition has been fully populated, write access to that partition has to be permanently locked. +For the HW_CFG* and SECRET* partitions, this can be achieved as follows: + +1. [Trigger](#digest-calculation-sequence) a digest calculation via the DAI. +2. [Read back](#readout-sequence) and verify the digest location via the DAI. +3. Perform a full-system reset and verify that the corresponding CSRs exposing the 64bit digest have been populated ([`HW_CFG_DIGEST_0`](registers.md#hw_cfg_digest), [`SECRET0_DIGEST_0`](registers.md#secret0_digest), [`SECRET1_DIGEST_0`](registers.md#secret1_digest) or [`SECRET2_DIGEST_0`](registers.md#secret2_digest)). + +It should be noted that locking only takes effect after a system reset since the affected partitions first have to re-sense the digest values. +Hence, it is critical that SW ensures that no more data is written to the partition to be locked after triggering the hardware digest calculation. +Otherwise, the device will likely be rendered inoperable as this can lead to permanent digest mismatch errors after system reboot. + +For the [`CREATOR_SW_CFG`](registers.md#creator_sw_cfg) and [`OWNER_SW_CFG`](registers.md#owner_sw_cfg) partitions, the process is similar, but computation and programming of the digest is entirely up to software: + +1. Compute a 64bit digest over the relevant parts of the partition, and [program](#programming-sequence) that value to [`CREATOR_SW_CFG_DIGEST_0`](registers.md#creator_sw_cfg_digest) or [`OWNER_SW_CFG_DIGEST_0`](registers.md#owner_sw_cfg_digest) via the DAI. Note that digest accesses through the DAI have an access granule of 64bit. +2. [Read back](#readout-sequence) and verify the digest location via the DAI. +3. Perform a full-system reset and verify that the corresponding digest CSRs [`CREATOR_SW_CFG_DIGEST_0`](registers.md#creator_sw_cfg_digest) or [`OWNER_SW_CFG_DIGEST_0`](registers.md#owner_sw_cfg_digest) have been populated with the correct 64bit value. + +Note that any unrecoverable errors during the programming steps, or mismatches during the read-back and verification steps indicate that the device might be malfunctioning (possibly due to fabrication defects) and hence the device may have to be scrapped. +This is however rare and should not happen after fabrication testing. + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_otp_ctrl.h) + +# Additional Notes + +## OTP IP Assumptions + +It is assumed the OTP IP employed in production has reasonable physical defense characteristics. +Specifically which defensive features will likely be use case dependent, but at a minimum they should have the properties below. +Note some properties are worded with "SHALL" and others with "SHOULD". +"SHALL" refers to features that must be present, while "SHOULD" refers to features that are ideal, but optional. + +- The contents shall not be observable via optical microscopy (for example anti-fuse technology). +- The IP lifetime shall not be limited by the amount of read cycles performed. +- If the IP contains field programmability (internal charge pumps and LDOs), there shall be mechanisms in place to selectively disable this function based on device context. +- If the IP contains redundant columns, rows, pages or banks for yield improvement, it shall provide a mechanism to lock down arbitrary manipulation of page / bank swapping during run-time. +- The IP shall be clear on what bits must be manipulated by the user, what bits are automatically manipulated by hardware (for example ECC or redundancy) and what areas the user can influence. +- The IP shall be compatible, through the use of a proprietary wrapper or shim, with an open-source friendly IO interface. +- The IP should functionally support the programming of already programmed bits without information leakage. +- The IP should offer SCA resistance: + - For example, the content may be stored differentially. + - For example, the sensing exhibits similar power signatures no matter if the stored bit is 0 or 1. +- The IP interface shall be memory-like if beyond a certain size. +- When a particular location is read, a fixed width output is returned; similar when a particular location is programmed, a fixed width input is supplied. +- The IP does not output all stored bits in parallel. +- The contents should be electrically hidden. For example, it should be difficult for an attacker to energize the fuse array and observe how the charge leaks. +- The IP should route critical nets at lower metal levels to avoid probing. +- The IP should contain native detectors for fault injection attacks. +- The IP should contain mechanisms to guard against interrupted programming - either through malicious intent or unexpected power loss and glitched address lines. +- The IP should contain mechanisms for error corrections (single bit errors). + - For example ECC or redundant bits voting / or-ing. + - As error correction mechanisms are technology dependent, that information should not be exposed to the open-source controller, instead the controller should simply receive information on whether a read / program was successful. +- The IP should have self-test functionality to assess the health of the storage and analog structures. +- The IP may contain native PUF-like functionality. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/registers.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/registers.md new file mode 100644 index 00000000000..88068adbea9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/registers.md @@ -0,0 +1,1338 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:-------------------------------------------------------------------------------|:---------|---------:|:-------------------------------------------------------------------------------------------------------------------------------------------| +| otp_ctrl.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | +| otp_ctrl.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | +| otp_ctrl.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | +| otp_ctrl.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | +| otp_ctrl.[`STATUS`](#status) | 0x10 | 4 | OTP status register. | +| otp_ctrl.[`ERR_CODE_0`](#err_code) | 0x14 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_1`](#err_code) | 0x18 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_2`](#err_code) | 0x1c | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_3`](#err_code) | 0x20 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_4`](#err_code) | 0x24 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_5`](#err_code) | 0x28 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_6`](#err_code) | 0x2c | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_7`](#err_code) | 0x30 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_8`](#err_code) | 0x34 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_9`](#err_code) | 0x38 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_10`](#err_code) | 0x3c | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_11`](#err_code) | 0x40 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_12`](#err_code) | 0x44 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_13`](#err_code) | 0x48 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_14`](#err_code) | 0x4c | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_15`](#err_code) | 0x50 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_16`](#err_code) | 0x54 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_17`](#err_code) | 0x58 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_18`](#err_code) | 0x5c | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_19`](#err_code) | 0x60 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_20`](#err_code) | 0x64 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_21`](#err_code) | 0x68 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_22`](#err_code) | 0x6c | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`ERR_CODE_23`](#err_code) | 0x70 | 4 | This register holds information about error conditions that occurred in the agents | +| otp_ctrl.[`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) | 0x74 | 4 | Register write enable for all direct access interface registers. | +| otp_ctrl.[`DIRECT_ACCESS_CMD`](#direct_access_cmd) | 0x78 | 4 | Command register for direct accesses. | +| otp_ctrl.[`DIRECT_ACCESS_ADDRESS`](#direct_access_address) | 0x7c | 4 | Address register for direct accesses. | +| otp_ctrl.[`DIRECT_ACCESS_WDATA_0`](#direct_access_wdata) | 0x80 | 4 | Write data for direct accesses. | +| otp_ctrl.[`DIRECT_ACCESS_WDATA_1`](#direct_access_wdata) | 0x84 | 4 | Write data for direct accesses. | +| otp_ctrl.[`DIRECT_ACCESS_RDATA_0`](#direct_access_rdata) | 0x88 | 4 | Read data for direct accesses. | +| otp_ctrl.[`DIRECT_ACCESS_RDATA_1`](#direct_access_rdata) | 0x8c | 4 | Read data for direct accesses. | +| otp_ctrl.[`CHECK_TRIGGER_REGWEN`](#check_trigger_regwen) | 0x90 | 4 | Register write enable for [`CHECK_TRIGGER.`](#check_trigger) | +| otp_ctrl.[`CHECK_TRIGGER`](#check_trigger) | 0x94 | 4 | Command register for direct accesses. | +| otp_ctrl.[`CHECK_REGWEN`](#check_regwen) | 0x98 | 4 | Register write enable for [`INTEGRITY_CHECK_PERIOD`](#integrity_check_period) and [`CONSISTENCY_CHECK_PERIOD.`](#consistency_check_period) | +| otp_ctrl.[`CHECK_TIMEOUT`](#check_timeout) | 0x9c | 4 | Timeout value for the integrity and consistency checks. | +| otp_ctrl.[`INTEGRITY_CHECK_PERIOD`](#integrity_check_period) | 0xa0 | 4 | This value specifies the maximum period that can be generated pseudo-randomly. | +| otp_ctrl.[`CONSISTENCY_CHECK_PERIOD`](#consistency_check_period) | 0xa4 | 4 | This value specifies the maximum period that can be generated pseudo-randomly. | +| otp_ctrl.[`VENDOR_TEST_READ_LOCK`](#vendor_test_read_lock) | 0xa8 | 4 | Runtime read lock for the VENDOR_TEST partition. | +| otp_ctrl.[`CREATOR_SW_CFG_READ_LOCK`](#creator_sw_cfg_read_lock) | 0xac | 4 | Runtime read lock for the CREATOR_SW_CFG partition. | +| otp_ctrl.[`OWNER_SW_CFG_READ_LOCK`](#owner_sw_cfg_read_lock) | 0xb0 | 4 | Runtime read lock for the OWNER_SW_CFG partition. | +| otp_ctrl.[`OWNERSHIP_SLOT_STATE_READ_LOCK`](#ownership_slot_state_read_lock) | 0xb4 | 4 | Runtime read lock for the OWNERSHIP_SLOT_STATE partition. | +| otp_ctrl.[`ROT_CREATOR_AUTH_READ_LOCK`](#rot_creator_auth_read_lock) | 0xb8 | 4 | Runtime read lock for the ROT_CREATOR_AUTH partition. | +| otp_ctrl.[`ROT_OWNER_AUTH_SLOT0_READ_LOCK`](#rot_owner_auth_slot0_read_lock) | 0xbc | 4 | Runtime read lock for the ROT_OWNER_AUTH_SLOT0 partition. | +| otp_ctrl.[`ROT_OWNER_AUTH_SLOT1_READ_LOCK`](#rot_owner_auth_slot1_read_lock) | 0xc0 | 4 | Runtime read lock for the ROT_OWNER_AUTH_SLOT1 partition. | +| otp_ctrl.[`PLAT_INTEG_AUTH_SLOT0_READ_LOCK`](#plat_integ_auth_slot0_read_lock) | 0xc4 | 4 | Runtime read lock for the PLAT_INTEG_AUTH_SLOT0 partition. | +| otp_ctrl.[`PLAT_INTEG_AUTH_SLOT1_READ_LOCK`](#plat_integ_auth_slot1_read_lock) | 0xc8 | 4 | Runtime read lock for the PLAT_INTEG_AUTH_SLOT1 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT0_READ_LOCK`](#plat_owner_auth_slot0_read_lock) | 0xcc | 4 | Runtime read lock for the PLAT_OWNER_AUTH_SLOT0 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT1_READ_LOCK`](#plat_owner_auth_slot1_read_lock) | 0xd0 | 4 | Runtime read lock for the PLAT_OWNER_AUTH_SLOT1 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT2_READ_LOCK`](#plat_owner_auth_slot2_read_lock) | 0xd4 | 4 | Runtime read lock for the PLAT_OWNER_AUTH_SLOT2 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT3_READ_LOCK`](#plat_owner_auth_slot3_read_lock) | 0xd8 | 4 | Runtime read lock for the PLAT_OWNER_AUTH_SLOT3 partition. | +| otp_ctrl.[`EXT_NVM_READ_LOCK`](#ext_nvm_read_lock) | 0xdc | 4 | Runtime read lock for the EXT_NVM partition. | +| otp_ctrl.[`ROM_PATCH_READ_LOCK`](#rom_patch_read_lock) | 0xe0 | 4 | Runtime read lock for the ROM_PATCH partition. | +| otp_ctrl.[`VENDOR_TEST_DIGEST_0`](#vendor_test_digest) | 0xe4 | 4 | Integrity digest for the VENDOR_TEST partition. | +| otp_ctrl.[`VENDOR_TEST_DIGEST_1`](#vendor_test_digest) | 0xe8 | 4 | Integrity digest for the VENDOR_TEST partition. | +| otp_ctrl.[`CREATOR_SW_CFG_DIGEST_0`](#creator_sw_cfg_digest) | 0xec | 4 | Integrity digest for the CREATOR_SW_CFG partition. | +| otp_ctrl.[`CREATOR_SW_CFG_DIGEST_1`](#creator_sw_cfg_digest) | 0xf0 | 4 | Integrity digest for the CREATOR_SW_CFG partition. | +| otp_ctrl.[`OWNER_SW_CFG_DIGEST_0`](#owner_sw_cfg_digest) | 0xf4 | 4 | Integrity digest for the OWNER_SW_CFG partition. | +| otp_ctrl.[`OWNER_SW_CFG_DIGEST_1`](#owner_sw_cfg_digest) | 0xf8 | 4 | Integrity digest for the OWNER_SW_CFG partition. | +| otp_ctrl.[`ROT_CREATOR_AUTH_DIGEST_0`](#rot_creator_auth_digest) | 0xfc | 4 | Integrity digest for the ROT_CREATOR_AUTH partition. | +| otp_ctrl.[`ROT_CREATOR_AUTH_DIGEST_1`](#rot_creator_auth_digest) | 0x100 | 4 | Integrity digest for the ROT_CREATOR_AUTH partition. | +| otp_ctrl.[`ROT_OWNER_AUTH_SLOT0_DIGEST_0`](#rot_owner_auth_slot0_digest) | 0x104 | 4 | Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition. | +| otp_ctrl.[`ROT_OWNER_AUTH_SLOT0_DIGEST_1`](#rot_owner_auth_slot0_digest) | 0x108 | 4 | Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition. | +| otp_ctrl.[`ROT_OWNER_AUTH_SLOT1_DIGEST_0`](#rot_owner_auth_slot1_digest) | 0x10c | 4 | Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition. | +| otp_ctrl.[`ROT_OWNER_AUTH_SLOT1_DIGEST_1`](#rot_owner_auth_slot1_digest) | 0x110 | 4 | Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition. | +| otp_ctrl.[`PLAT_INTEG_AUTH_SLOT0_DIGEST_0`](#plat_integ_auth_slot0_digest) | 0x114 | 4 | Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition. | +| otp_ctrl.[`PLAT_INTEG_AUTH_SLOT0_DIGEST_1`](#plat_integ_auth_slot0_digest) | 0x118 | 4 | Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition. | +| otp_ctrl.[`PLAT_INTEG_AUTH_SLOT1_DIGEST_0`](#plat_integ_auth_slot1_digest) | 0x11c | 4 | Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition. | +| otp_ctrl.[`PLAT_INTEG_AUTH_SLOT1_DIGEST_1`](#plat_integ_auth_slot1_digest) | 0x120 | 4 | Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT0_DIGEST_0`](#plat_owner_auth_slot0_digest) | 0x124 | 4 | Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT0_DIGEST_1`](#plat_owner_auth_slot0_digest) | 0x128 | 4 | Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT1_DIGEST_0`](#plat_owner_auth_slot1_digest) | 0x12c | 4 | Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT1_DIGEST_1`](#plat_owner_auth_slot1_digest) | 0x130 | 4 | Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT2_DIGEST_0`](#plat_owner_auth_slot2_digest) | 0x134 | 4 | Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT2_DIGEST_1`](#plat_owner_auth_slot2_digest) | 0x138 | 4 | Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT3_DIGEST_0`](#plat_owner_auth_slot3_digest) | 0x13c | 4 | Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition. | +| otp_ctrl.[`PLAT_OWNER_AUTH_SLOT3_DIGEST_1`](#plat_owner_auth_slot3_digest) | 0x140 | 4 | Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition. | +| otp_ctrl.[`ROM_PATCH_DIGEST_0`](#rom_patch_digest) | 0x144 | 4 | Integrity digest for the ROM_PATCH partition. | +| otp_ctrl.[`ROM_PATCH_DIGEST_1`](#rom_patch_digest) | 0x148 | 4 | Integrity digest for the ROM_PATCH partition. | +| otp_ctrl.[`HW_CFG0_DIGEST_0`](#hw_cfg0_digest) | 0x14c | 4 | Integrity digest for the HW_CFG0 partition. | +| otp_ctrl.[`HW_CFG0_DIGEST_1`](#hw_cfg0_digest) | 0x150 | 4 | Integrity digest for the HW_CFG0 partition. | +| otp_ctrl.[`HW_CFG1_DIGEST_0`](#hw_cfg1_digest) | 0x154 | 4 | Integrity digest for the HW_CFG1 partition. | +| otp_ctrl.[`HW_CFG1_DIGEST_1`](#hw_cfg1_digest) | 0x158 | 4 | Integrity digest for the HW_CFG1 partition. | +| otp_ctrl.[`SECRET0_DIGEST_0`](#secret0_digest) | 0x15c | 4 | Integrity digest for the SECRET0 partition. | +| otp_ctrl.[`SECRET0_DIGEST_1`](#secret0_digest) | 0x160 | 4 | Integrity digest for the SECRET0 partition. | +| otp_ctrl.[`SECRET1_DIGEST_0`](#secret1_digest) | 0x164 | 4 | Integrity digest for the SECRET1 partition. | +| otp_ctrl.[`SECRET1_DIGEST_1`](#secret1_digest) | 0x168 | 4 | Integrity digest for the SECRET1 partition. | +| otp_ctrl.[`SECRET2_DIGEST_0`](#secret2_digest) | 0x16c | 4 | Integrity digest for the SECRET2 partition. | +| otp_ctrl.[`SECRET2_DIGEST_1`](#secret2_digest) | 0x170 | 4 | Integrity digest for the SECRET2 partition. | +| otp_ctrl.[`SECRET3_DIGEST_0`](#secret3_digest) | 0x174 | 4 | Integrity digest for the SECRET3 partition. | +| otp_ctrl.[`SECRET3_DIGEST_1`](#secret3_digest) | 0x178 | 4 | Integrity digest for the SECRET3 partition. | +| otp_ctrl.[`SW_CFG_WINDOW`](#sw_cfg_window) | 0x4000 | 16384 | Any read to this window directly maps to the corresponding offset in the creator and owner software | + +## INTR_STATE +Interrupt State Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "otp_operation_done", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "otp_error", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------|:-----------------------------------------------------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw1c | 0x0 | otp_error | An error has occurred in the OTP controller. Check the [`ERR_CODE`](#err_code) register to get more information. | +| 0 | rw1c | 0x0 | otp_operation_done | A direct access command or digest calculation operation has completed. | + +## INTR_ENABLE +Interrupt Enable Register +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "otp_operation_done", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "otp_error", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------|:-----------------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw | 0x0 | otp_error | Enable interrupt when [`INTR_STATE.otp_error`](#intr_state) is set. | +| 0 | rw | 0x0 | otp_operation_done | Enable interrupt when [`INTR_STATE.otp_operation_done`](#intr_state) is set. | + +## INTR_TEST +Interrupt Test Register +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "otp_operation_done", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "otp_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------|:----------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | wo | 0x0 | otp_error | Write 1 to force [`INTR_STATE.otp_error`](#intr_state) to 1. | +| 0 | wo | 0x0 | otp_operation_done | Write 1 to force [`INTR_STATE.otp_operation_done`](#intr_state) to 1. | + +## ALERT_TEST +Alert Test Register +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x1f` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_macro_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_check_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_bus_integ_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_prim_otp_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "recov_prim_otp_alert", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------|:-------------------------------------------------| +| 31:5 | | | | Reserved | +| 4 | wo | 0x0 | recov_prim_otp_alert | Write 1 to trigger one alert event of this kind. | +| 3 | wo | 0x0 | fatal_prim_otp_alert | Write 1 to trigger one alert event of this kind. | +| 2 | wo | 0x0 | fatal_bus_integ_error | Write 1 to trigger one alert event of this kind. | +| 1 | wo | 0x0 | fatal_check_error | Write 1 to trigger one alert event of this kind. | +| 0 | wo | 0x0 | fatal_macro_error | Write 1 to trigger one alert event of this kind. | + +## STATUS +OTP status register. +- Offset: `0x10` +- Reset default: `0x0` +- Reset mask: `0x7fffffff` + +### Fields + +```wavejson +{"reg": [{"name": "VENDOR_TEST_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CREATOR_SW_CFG_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "OWNER_SW_CFG_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "OWNERSHIP_SLOT_STATE_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ROT_CREATOR_AUTH_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ROT_OWNER_AUTH_SLOT0_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ROT_OWNER_AUTH_SLOT1_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "PLAT_INTEG_AUTH_SLOT0_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "PLAT_INTEG_AUTH_SLOT1_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "PLAT_OWNER_AUTH_SLOT0_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "PLAT_OWNER_AUTH_SLOT1_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "PLAT_OWNER_AUTH_SLOT2_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "PLAT_OWNER_AUTH_SLOT3_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "EXT_NVM_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ROM_PATCH_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HW_CFG0_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HW_CFG1_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SECRET0_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SECRET1_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SECRET2_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SECRET3_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "LIFE_CYCLE_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DAI_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "LCI_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TIMEOUT_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "LFSR_FSM_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SCRAMBLING_FSM_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "KEY_DERIV_FSM_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "BUS_INTEG_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DAI_IDLE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CHECK_PENDING", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------------|:------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31 | | | | Reserved | +| 30 | ro | 0x0 | CHECK_PENDING | Set to 1 if an integrity or consistency check triggered by the LFSR timer or via [`CHECK_TRIGGER`](#check_trigger) is pending. | +| 29 | ro | 0x0 | DAI_IDLE | Set to 1 if the DAI is idle and ready to accept commands. | +| 28 | ro | 0x0 | BUS_INTEG_ERROR | This bit is set to 1 if a fatal bus integrity fault is detected. This error triggers a fatal_bus_integ_error alert. | +| 27 | ro | 0x0 | KEY_DERIV_FSM_ERROR | Set to 1 if the key derivation FSM has reached an invalid state. This raises an fatal_check_error alert and is an unrecoverable error condition. | +| 26 | ro | 0x0 | SCRAMBLING_FSM_ERROR | Set to 1 if the scrambling datapath FSM has reached an invalid state. This raises an fatal_check_error alert and is an unrecoverable error condition. | +| 25 | ro | 0x0 | LFSR_FSM_ERROR | Set to 1 if the LFSR timer FSM has reached an invalid state. This raises an fatal_check_error alert and is an unrecoverable error condition. | +| 24 | ro | 0x0 | TIMEOUT_ERROR | Set to 1 if an integrity or consistency check times out. This raises an fatal_check_error alert and is an unrecoverable error condition. | +| 23 | ro | 0x0 | LCI_ERROR | Set to 1 if an error occurred in the LCI. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 22 | ro | 0x0 | DAI_ERROR | Set to 1 if an error occurred in the DAI. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 21 | ro | 0x0 | LIFE_CYCLE_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 20 | ro | 0x0 | SECRET3_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 19 | ro | 0x0 | SECRET2_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 18 | ro | 0x0 | SECRET1_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 17 | ro | 0x0 | SECRET0_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 16 | ro | 0x0 | HW_CFG1_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 15 | ro | 0x0 | HW_CFG0_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 14 | ro | 0x0 | ROM_PATCH_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 13 | ro | 0x0 | EXT_NVM_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 12 | ro | 0x0 | PLAT_OWNER_AUTH_SLOT3_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 11 | ro | 0x0 | PLAT_OWNER_AUTH_SLOT2_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 10 | ro | 0x0 | PLAT_OWNER_AUTH_SLOT1_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 9 | ro | 0x0 | PLAT_OWNER_AUTH_SLOT0_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 8 | ro | 0x0 | PLAT_INTEG_AUTH_SLOT1_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 7 | ro | 0x0 | PLAT_INTEG_AUTH_SLOT0_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 6 | ro | 0x0 | ROT_OWNER_AUTH_SLOT1_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 5 | ro | 0x0 | ROT_OWNER_AUTH_SLOT0_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 4 | ro | 0x0 | ROT_CREATOR_AUTH_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 3 | ro | 0x0 | OWNERSHIP_SLOT_STATE_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 2 | ro | 0x0 | OWNER_SW_CFG_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 1 | ro | 0x0 | CREATOR_SW_CFG_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | +| 0 | ro | 0x0 | VENDOR_TEST_ERROR | Set to 1 if an error occurred in this partition. If set to 1, SW should check the [`ERR_CODE`](#err_code) register at the corresponding index. | + +## ERR_CODE +This register holds information about error conditions that occurred in the agents +interacting with the OTP macro via the internal bus. The error codes should be checked +if the partitions, DAI or LCI flag an error in the [`STATUS`](#status) register, or when an +[`INTR_STATE.otp_error`](#intr_state) has been triggered. Note that all errors trigger an otp_error +interrupt, and in addition some errors may trigger either an fatal_macro_error or an +fatal_check_error alert. +- Reset default: `0x0` +- Reset mask: `0x7` + +### Instances + +| Name | Offset | +|:------------|:---------| +| ERR_CODE_0 | 0x14 | +| ERR_CODE_1 | 0x18 | +| ERR_CODE_2 | 0x1c | +| ERR_CODE_3 | 0x20 | +| ERR_CODE_4 | 0x24 | +| ERR_CODE_5 | 0x28 | +| ERR_CODE_6 | 0x2c | +| ERR_CODE_7 | 0x30 | +| ERR_CODE_8 | 0x34 | +| ERR_CODE_9 | 0x38 | +| ERR_CODE_10 | 0x3c | +| ERR_CODE_11 | 0x40 | +| ERR_CODE_12 | 0x44 | +| ERR_CODE_13 | 0x48 | +| ERR_CODE_14 | 0x4c | +| ERR_CODE_15 | 0x50 | +| ERR_CODE_16 | 0x54 | +| ERR_CODE_17 | 0x58 | +| ERR_CODE_18 | 0x5c | +| ERR_CODE_19 | 0x60 | +| ERR_CODE_20 | 0x64 | +| ERR_CODE_21 | 0x68 | +| ERR_CODE_22 | 0x6c | +| ERR_CODE_23 | 0x70 | + + +### Fields + +```wavejson +{"reg": [{"name": "ERR_CODE", "bits": 3, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:--------------------------------| +| 31:3 | | | Reserved | +| 2:0 | ro | 0x0 | [ERR_CODE](#err_code--err_code) | + +### ERR_CODE . ERR_CODE + +| Value | Name | Description | +|:--------|:------------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | NO_ERROR | No error condition has occurred. | +| 0x1 | MACRO_ERROR | Returned if the OTP macro command was invalid or did not complete successfully due to a macro malfunction. This error should never occur during normal operation and is not recoverable. This error triggers an fatal_macro_error alert. | +| 0x2 | MACRO_ECC_CORR_ERROR | A correctable ECC error has occurred during an OTP read operation. The corresponding controller automatically recovers from this error when issuing a new command. | +| 0x3 | MACRO_ECC_UNCORR_ERROR | An uncorrectable ECC error has occurred during an OTP read operation. This error should never occur during normal operation and is not recoverable. If this error is present this may be a sign that the device is malfunctioning. This error triggers an fatal_macro_error alert. | +| 0x4 | MACRO_WRITE_BLANK_ERROR | This error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1. The corresponding controller automatically recovers from this error when issuing a new command. Note however that the affected OTP word may be left in an inconsistent state if this error occurs. This can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check). It is important that SW ensures that each word is only written once, since this can render the device useless. | +| 0x5 | ACCESS_ERROR | This error indicates that a locked memory region has been accessed. The corresponding controller automatically recovers from this error when issuing a new command. | +| 0x6 | CHECK_FAIL_ERROR | An ECC, integrity or consistency mismatch has been detected in the buffer registers. This error should never occur during normal operation and is not recoverable. This error triggers an fatal_check_error alert. | +| 0x7 | FSM_STATE_ERROR | The FSM of the corresponding controller has reached an invalid state, or the FSM has been moved into a terminal error state due to an escalation action via lc_escalate_en_i. This error should never occur during normal operation and is not recoverable. If this error is present, this is a sign that the device has fallen victim to an invasive attack. This error triggers an fatal_check_error alert. | + + +## DIRECT_ACCESS_REGWEN +Register write enable for all direct access interface registers. +- Offset: `0x74` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "DIRECT_ACCESS_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:--------------------------------------------------------------------| +| 31:1 | | | Reserved | +| 0 | rw0c | 0x1 | [DIRECT_ACCESS_REGWEN](#direct_access_regwen--direct_access_regwen) | + +### DIRECT_ACCESS_REGWEN . DIRECT_ACCESS_REGWEN +This bit controls whether the DAI registers can be written. +Write 0 to it in order to clear the bit. + +Note that the hardware also modulates this bit and sets it to 0 temporarily +during an OTP operation such that the corresponding address and data registers +cannot be modified while an operation is pending. The [`DAI_IDLE`](#dai_idle) status bit +will also be set to 0 in such a case. + +## DIRECT_ACCESS_CMD +Command register for direct accesses. +- Offset: `0x78` +- Reset default: `0x0` +- Reset mask: `0x7` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "RD", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"name": "WR", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"name": "DIGEST", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2 | r0w1c | 0x0 | DIGEST | Initiates the digest calculation and locking sequence for the partition specified by [`DIRECT_ACCESS_ADDRESS.`](#direct_access_address) | +| 1 | r0w1c | 0x0 | WR | Initiates a programming sequence that writes the data in [`DIRECT_ACCESS_WDATA_0`](#direct_access_wdata_0) and [`DIRECT_ACCESS_WDATA_1`](#direct_access_wdata_1) (for 64bit partitions) to the location specified by [`DIRECT_ACCESS_ADDRESS.`](#direct_access_address) | +| 0 | r0w1c | 0x0 | RD | Initiates a readout sequence that reads the location specified by [`DIRECT_ACCESS_ADDRESS.`](#direct_access_address) The command places the data read into [`DIRECT_ACCESS_RDATA_0`](#direct_access_rdata_0) and [`DIRECT_ACCESS_RDATA_1`](#direct_access_rdata_1) (for 64bit partitions). | + +## DIRECT_ACCESS_ADDRESS +Address register for direct accesses. +- Offset: `0x7c` +- Reset default: `0x0` +- Reset mask: `0x3fff` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "DIRECT_ACCESS_ADDRESS", "bits": 14, "attr": ["rw"], "rotate": 0}, {"bits": 18}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-----------------------------------------------------------------------| +| 31:14 | | | Reserved | +| 13:0 | rw | 0x0 | [DIRECT_ACCESS_ADDRESS](#direct_access_address--direct_access_address) | + +### DIRECT_ACCESS_ADDRESS . DIRECT_ACCESS_ADDRESS +This is the address for the OTP word to be read or written through +the direct access interface. Note that the address is aligned to the access size +internally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored +for 64bit accesses. + +For the digest calculation command, set this register to the partition base offset. + +## DIRECT_ACCESS_WDATA +Write data for direct accesses. +Hardware automatically determines the access granule (32bit or 64bit) based on which +partition is being written to. +- Reset default: `0x0` +- Reset mask: `0xffffffff` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Instances + +| Name | Offset | +|:----------------------|:---------| +| DIRECT_ACCESS_WDATA_0 | 0x80 | +| DIRECT_ACCESS_WDATA_1 | 0x84 | + + +### Fields + +```wavejson +{"reg": [{"name": "DIRECT_ACCESS_WDATA", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:--------------| +| 31:0 | rw | 0x0 | DIRECT_ACCESS_WDATA | | + +## DIRECT_ACCESS_RDATA +Read data for direct accesses. +Hardware automatically determines the access granule (32bit or 64bit) based on which +partition is read from. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:----------------------|:---------| +| DIRECT_ACCESS_RDATA_0 | 0x88 | +| DIRECT_ACCESS_RDATA_1 | 0x8c | + + +### Fields + +```wavejson +{"reg": [{"name": "DIRECT_ACCESS_RDATA", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:--------------| +| 31:0 | ro | 0x0 | DIRECT_ACCESS_RDATA | | + +## CHECK_TRIGGER_REGWEN +Register write enable for [`CHECK_TRIGGER.`](#check_trigger) +- Offset: `0x90` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "CHECK_TRIGGER_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------------|:------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | CHECK_TRIGGER_REGWEN | When cleared to 0, the [`CHECK_TRIGGER`](#check_trigger) register cannot be written anymore. Write 0 to clear this bit. | + +## CHECK_TRIGGER +Command register for direct accesses. +- Offset: `0x94` +- Reset default: `0x0` +- Reset mask: `0x3` +- Register enable: [`CHECK_TRIGGER_REGWEN`](#check_trigger_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "INTEGRITY", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"name": "CONSISTENCY", "bits": 1, "attr": ["r0w1c"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-------------------------------------------| +| 31:2 | | | Reserved | +| 1 | r0w1c | 0x0 | [CONSISTENCY](#check_trigger--consistency) | +| 0 | r0w1c | 0x0 | [INTEGRITY](#check_trigger--integrity) | + +### CHECK_TRIGGER . CONSISTENCY +Writing 1 to this bit triggers a consistency check. SW should monitor [`STATUS.CHECK_PENDING`](#status) +and wait until the check has been completed. If there are any errors, those will be flagged +in the [`STATUS`](#status) and [`ERR_CODE`](#err_code) registers, and via interrupts and alerts. + +### CHECK_TRIGGER . INTEGRITY +Writing 1 to this bit triggers an integrity check. SW should monitor [`STATUS.CHECK_PENDING`](#status) +and wait until the check has been completed. If there are any errors, those will be flagged +in the [`STATUS`](#status) and [`ERR_CODE`](#err_code) registers, and via the interrupts and alerts. + +## CHECK_REGWEN +Register write enable for [`INTEGRITY_CHECK_PERIOD`](#integrity_check_period) and [`CONSISTENCY_CHECK_PERIOD.`](#consistency_check_period) +- Offset: `0x98` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "CHECK_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | CHECK_REGWEN | When cleared to 0, [`INTEGRITY_CHECK_PERIOD`](#integrity_check_period) and [`CONSISTENCY_CHECK_PERIOD`](#consistency_check_period) registers cannot be written anymore. Write 0 to clear this bit. | + +## CHECK_TIMEOUT +Timeout value for the integrity and consistency checks. +- Offset: `0x9c` +- Reset default: `0x0` +- Reset mask: `0xffffffff` +- Register enable: [`CHECK_REGWEN`](#check_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "CHECK_TIMEOUT", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-----------------------------------------------| +| 31:0 | rw | 0x0 | [CHECK_TIMEOUT](#check_timeout--check_timeout) | + +### CHECK_TIMEOUT . CHECK_TIMEOUT +Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency +check does not complete within the timeout window, an error will be flagged in the [`STATUS`](#status) register, +an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should +be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the +number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to +roughly 25k cycles, it is recommended to set this value to at least 100'000 cycles in order to stay on the +safe side. A value of zero disables the timeout mechanism (default). + +## INTEGRITY_CHECK_PERIOD +This value specifies the maximum period that can be generated pseudo-randomly. +Only applies to the HW_CFG* and SECRET* partitions once they are locked. +- Offset: `0xa0` +- Reset default: `0x0` +- Reset mask: `0xffffffff` +- Register enable: [`CHECK_REGWEN`](#check_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "INTEGRITY_CHECK_PERIOD", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:--------------------------------------------------------------------------| +| 31:0 | rw | 0x0 | [INTEGRITY_CHECK_PERIOD](#integrity_check_period--integrity_check_period) | + +### INTEGRITY_CHECK_PERIOD . INTEGRITY_CHECK_PERIOD +The pseudo-random period is generated using a 40bit LFSR internally, and this register defines +the bit mask to be applied to the LFSR output in order to limit its range. The value of this +register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. +A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. +A value of zero disables the timer (default). Note that a one-off check can always be triggered via +[`CHECK_TRIGGER.INTEGRITY.`](#check_trigger) + +## CONSISTENCY_CHECK_PERIOD +This value specifies the maximum period that can be generated pseudo-randomly. +This applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked. +- Offset: `0xa4` +- Reset default: `0x0` +- Reset mask: `0xffffffff` +- Register enable: [`CHECK_REGWEN`](#check_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "CONSISTENCY_CHECK_PERIOD", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:--------------------------------------------------------------------------------| +| 31:0 | rw | 0x0 | [CONSISTENCY_CHECK_PERIOD](#consistency_check_period--consistency_check_period) | + +### CONSISTENCY_CHECK_PERIOD . CONSISTENCY_CHECK_PERIOD +The pseudo-random period is generated using a 40bit LFSR internally, and this register defines +the bit mask to be applied to the LFSR output in order to limit its range. The value of this +register is left shifted by 8bits and the lower bits are set to 8'hFF in order to form the 40bit mask. +A recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz. +A value of zero disables the timer (default). Note that a one-off check can always be triggered via +[`CHECK_TRIGGER.CONSISTENCY.`](#check_trigger) + +## VENDOR_TEST_READ_LOCK +Runtime read lock for the VENDOR_TEST partition. +- Offset: `0xa8` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "VENDOR_TEST_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------|:--------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | VENDOR_TEST_READ_LOCK | When cleared to 0, read access to the VENDOR_TEST partition is locked. Write 0 to clear this bit. | + +## CREATOR_SW_CFG_READ_LOCK +Runtime read lock for the CREATOR_SW_CFG partition. +- Offset: `0xac` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "CREATOR_SW_CFG_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------------|:-----------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | CREATOR_SW_CFG_READ_LOCK | When cleared to 0, read access to the CREATOR_SW_CFG partition is locked. Write 0 to clear this bit. | + +## OWNER_SW_CFG_READ_LOCK +Runtime read lock for the OWNER_SW_CFG partition. +- Offset: `0xb0` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "OWNER_SW_CFG_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------------|:---------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | OWNER_SW_CFG_READ_LOCK | When cleared to 0, read access to the OWNER_SW_CFG partition is locked. Write 0 to clear this bit. | + +## OWNERSHIP_SLOT_STATE_READ_LOCK +Runtime read lock for the OWNERSHIP_SLOT_STATE partition. +- Offset: `0xb4` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "OWNERSHIP_SLOT_STATE_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 320}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------------------|:-----------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | OWNERSHIP_SLOT_STATE_READ_LOCK | When cleared to 0, read access to the OWNERSHIP_SLOT_STATE partition is locked. Write 0 to clear this bit. | + +## ROT_CREATOR_AUTH_READ_LOCK +Runtime read lock for the ROT_CREATOR_AUTH partition. +- Offset: `0xb8` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "ROT_CREATOR_AUTH_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 280}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------------------|:-------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | ROT_CREATOR_AUTH_READ_LOCK | When cleared to 0, read access to the ROT_CREATOR_AUTH partition is locked. Write 0 to clear this bit. | + +## ROT_OWNER_AUTH_SLOT0_READ_LOCK +Runtime read lock for the ROT_OWNER_AUTH_SLOT0 partition. +- Offset: `0xbc` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "ROT_OWNER_AUTH_SLOT0_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 320}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------------------|:-----------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | ROT_OWNER_AUTH_SLOT0_READ_LOCK | When cleared to 0, read access to the ROT_OWNER_AUTH_SLOT0 partition is locked. Write 0 to clear this bit. | + +## ROT_OWNER_AUTH_SLOT1_READ_LOCK +Runtime read lock for the ROT_OWNER_AUTH_SLOT1 partition. +- Offset: `0xc0` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "ROT_OWNER_AUTH_SLOT1_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 320}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------------------|:-----------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | ROT_OWNER_AUTH_SLOT1_READ_LOCK | When cleared to 0, read access to the ROT_OWNER_AUTH_SLOT1 partition is locked. Write 0 to clear this bit. | + +## PLAT_INTEG_AUTH_SLOT0_READ_LOCK +Runtime read lock for the PLAT_INTEG_AUTH_SLOT0 partition. +- Offset: `0xc4` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_INTEG_AUTH_SLOT0_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 330}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------------------|:------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | PLAT_INTEG_AUTH_SLOT0_READ_LOCK | When cleared to 0, read access to the PLAT_INTEG_AUTH_SLOT0 partition is locked. Write 0 to clear this bit. | + +## PLAT_INTEG_AUTH_SLOT1_READ_LOCK +Runtime read lock for the PLAT_INTEG_AUTH_SLOT1 partition. +- Offset: `0xc8` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_INTEG_AUTH_SLOT1_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 330}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------------------|:------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | PLAT_INTEG_AUTH_SLOT1_READ_LOCK | When cleared to 0, read access to the PLAT_INTEG_AUTH_SLOT1 partition is locked. Write 0 to clear this bit. | + +## PLAT_OWNER_AUTH_SLOT0_READ_LOCK +Runtime read lock for the PLAT_OWNER_AUTH_SLOT0 partition. +- Offset: `0xcc` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_OWNER_AUTH_SLOT0_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 330}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------------------|:------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | PLAT_OWNER_AUTH_SLOT0_READ_LOCK | When cleared to 0, read access to the PLAT_OWNER_AUTH_SLOT0 partition is locked. Write 0 to clear this bit. | + +## PLAT_OWNER_AUTH_SLOT1_READ_LOCK +Runtime read lock for the PLAT_OWNER_AUTH_SLOT1 partition. +- Offset: `0xd0` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_OWNER_AUTH_SLOT1_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 330}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------------------|:------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | PLAT_OWNER_AUTH_SLOT1_READ_LOCK | When cleared to 0, read access to the PLAT_OWNER_AUTH_SLOT1 partition is locked. Write 0 to clear this bit. | + +## PLAT_OWNER_AUTH_SLOT2_READ_LOCK +Runtime read lock for the PLAT_OWNER_AUTH_SLOT2 partition. +- Offset: `0xd4` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_OWNER_AUTH_SLOT2_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 330}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------------------|:------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | PLAT_OWNER_AUTH_SLOT2_READ_LOCK | When cleared to 0, read access to the PLAT_OWNER_AUTH_SLOT2 partition is locked. Write 0 to clear this bit. | + +## PLAT_OWNER_AUTH_SLOT3_READ_LOCK +Runtime read lock for the PLAT_OWNER_AUTH_SLOT3 partition. +- Offset: `0xd8` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_OWNER_AUTH_SLOT3_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 330}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------------------|:------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | PLAT_OWNER_AUTH_SLOT3_READ_LOCK | When cleared to 0, read access to the PLAT_OWNER_AUTH_SLOT3 partition is locked. Write 0 to clear this bit. | + +## EXT_NVM_READ_LOCK +Runtime read lock for the EXT_NVM partition. +- Offset: `0xdc` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EXT_NVM_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------|:----------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EXT_NVM_READ_LOCK | When cleared to 0, read access to the EXT_NVM partition is locked. Write 0 to clear this bit. | + +## ROM_PATCH_READ_LOCK +Runtime read lock for the ROM_PATCH partition. +- Offset: `0xe0` +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`DIRECT_ACCESS_REGWEN`](#direct_access_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "ROM_PATCH_READ_LOCK", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | ROM_PATCH_READ_LOCK | When cleared to 0, read access to the ROM_PATCH partition is locked. Write 0 to clear this bit. | + +## VENDOR_TEST_DIGEST +Integrity digest for the VENDOR_TEST partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the VENDOR_TEST partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:---------------------|:---------| +| VENDOR_TEST_DIGEST_0 | 0xe4 | +| VENDOR_TEST_DIGEST_1 | 0xe8 | + + +### Fields + +```wavejson +{"reg": [{"name": "VENDOR_TEST_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------------------|:--------------| +| 31:0 | ro | 0x0 | VENDOR_TEST_DIGEST | | + +## CREATOR_SW_CFG_DIGEST +Integrity digest for the CREATOR_SW_CFG partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the CREATOR_SW_CFG partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:------------------------|:---------| +| CREATOR_SW_CFG_DIGEST_0 | 0xec | +| CREATOR_SW_CFG_DIGEST_1 | 0xf0 | + + +### Fields + +```wavejson +{"reg": [{"name": "CREATOR_SW_CFG_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------|:--------------| +| 31:0 | ro | 0x0 | CREATOR_SW_CFG_DIGEST | | + +## OWNER_SW_CFG_DIGEST +Integrity digest for the OWNER_SW_CFG partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the OWNER_SW_CFG partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:----------------------|:---------| +| OWNER_SW_CFG_DIGEST_0 | 0xf4 | +| OWNER_SW_CFG_DIGEST_1 | 0xf8 | + + +### Fields + +```wavejson +{"reg": [{"name": "OWNER_SW_CFG_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------------------|:--------------| +| 31:0 | ro | 0x0 | OWNER_SW_CFG_DIGEST | | + +## ROT_CREATOR_AUTH_DIGEST +Integrity digest for the ROT_CREATOR_AUTH partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the ROT_CREATOR_AUTH partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:--------------------------|:---------| +| ROT_CREATOR_AUTH_DIGEST_0 | 0xfc | +| ROT_CREATOR_AUTH_DIGEST_1 | 0x100 | + + +### Fields + +```wavejson +{"reg": [{"name": "ROT_CREATOR_AUTH_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------------|:--------------| +| 31:0 | ro | 0x0 | ROT_CREATOR_AUTH_DIGEST | | + +## ROT_OWNER_AUTH_SLOT0_DIGEST +Integrity digest for the ROT_OWNER_AUTH_SLOT0 partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the ROT_OWNER_AUTH_SLOT0 partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:------------------------------|:---------| +| ROT_OWNER_AUTH_SLOT0_DIGEST_0 | 0x104 | +| ROT_OWNER_AUTH_SLOT0_DIGEST_1 | 0x108 | + + +### Fields + +```wavejson +{"reg": [{"name": "ROT_OWNER_AUTH_SLOT0_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------------|:--------------| +| 31:0 | ro | 0x0 | ROT_OWNER_AUTH_SLOT0_DIGEST | | + +## ROT_OWNER_AUTH_SLOT1_DIGEST +Integrity digest for the ROT_OWNER_AUTH_SLOT1 partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the ROT_OWNER_AUTH_SLOT1 partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:------------------------------|:---------| +| ROT_OWNER_AUTH_SLOT1_DIGEST_0 | 0x10c | +| ROT_OWNER_AUTH_SLOT1_DIGEST_1 | 0x110 | + + +### Fields + +```wavejson +{"reg": [{"name": "ROT_OWNER_AUTH_SLOT1_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------------|:--------------| +| 31:0 | ro | 0x0 | ROT_OWNER_AUTH_SLOT1_DIGEST | | + +## PLAT_INTEG_AUTH_SLOT0_DIGEST +Integrity digest for the PLAT_INTEG_AUTH_SLOT0 partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the PLAT_INTEG_AUTH_SLOT0 partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-------------------------------|:---------| +| PLAT_INTEG_AUTH_SLOT0_DIGEST_0 | 0x114 | +| PLAT_INTEG_AUTH_SLOT0_DIGEST_1 | 0x118 | + + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_INTEG_AUTH_SLOT0_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------------------|:--------------| +| 31:0 | ro | 0x0 | PLAT_INTEG_AUTH_SLOT0_DIGEST | | + +## PLAT_INTEG_AUTH_SLOT1_DIGEST +Integrity digest for the PLAT_INTEG_AUTH_SLOT1 partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the PLAT_INTEG_AUTH_SLOT1 partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-------------------------------|:---------| +| PLAT_INTEG_AUTH_SLOT1_DIGEST_0 | 0x11c | +| PLAT_INTEG_AUTH_SLOT1_DIGEST_1 | 0x120 | + + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_INTEG_AUTH_SLOT1_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------------------|:--------------| +| 31:0 | ro | 0x0 | PLAT_INTEG_AUTH_SLOT1_DIGEST | | + +## PLAT_OWNER_AUTH_SLOT0_DIGEST +Integrity digest for the PLAT_OWNER_AUTH_SLOT0 partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the PLAT_OWNER_AUTH_SLOT0 partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-------------------------------|:---------| +| PLAT_OWNER_AUTH_SLOT0_DIGEST_0 | 0x124 | +| PLAT_OWNER_AUTH_SLOT0_DIGEST_1 | 0x128 | + + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_OWNER_AUTH_SLOT0_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------------------|:--------------| +| 31:0 | ro | 0x0 | PLAT_OWNER_AUTH_SLOT0_DIGEST | | + +## PLAT_OWNER_AUTH_SLOT1_DIGEST +Integrity digest for the PLAT_OWNER_AUTH_SLOT1 partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the PLAT_OWNER_AUTH_SLOT1 partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-------------------------------|:---------| +| PLAT_OWNER_AUTH_SLOT1_DIGEST_0 | 0x12c | +| PLAT_OWNER_AUTH_SLOT1_DIGEST_1 | 0x130 | + + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_OWNER_AUTH_SLOT1_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------------------|:--------------| +| 31:0 | ro | 0x0 | PLAT_OWNER_AUTH_SLOT1_DIGEST | | + +## PLAT_OWNER_AUTH_SLOT2_DIGEST +Integrity digest for the PLAT_OWNER_AUTH_SLOT2 partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the PLAT_OWNER_AUTH_SLOT2 partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-------------------------------|:---------| +| PLAT_OWNER_AUTH_SLOT2_DIGEST_0 | 0x134 | +| PLAT_OWNER_AUTH_SLOT2_DIGEST_1 | 0x138 | + + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_OWNER_AUTH_SLOT2_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------------------|:--------------| +| 31:0 | ro | 0x0 | PLAT_OWNER_AUTH_SLOT2_DIGEST | | + +## PLAT_OWNER_AUTH_SLOT3_DIGEST +Integrity digest for the PLAT_OWNER_AUTH_SLOT3 partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the PLAT_OWNER_AUTH_SLOT3 partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-------------------------------|:---------| +| PLAT_OWNER_AUTH_SLOT3_DIGEST_0 | 0x13c | +| PLAT_OWNER_AUTH_SLOT3_DIGEST_1 | 0x140 | + + +### Fields + +```wavejson +{"reg": [{"name": "PLAT_OWNER_AUTH_SLOT3_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------------------|:--------------| +| 31:0 | ro | 0x0 | PLAT_OWNER_AUTH_SLOT3_DIGEST | | + +## ROM_PATCH_DIGEST +Integrity digest for the ROM_PATCH partition. +The integrity digest is 0 by default. Software must write this +digest value via the direct access interface in order to lock the partition. +After a reset, write access to the ROM_PATCH partition is locked and +the digest becomes visible in this CSR. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-------------------|:---------| +| ROM_PATCH_DIGEST_0 | 0x144 | +| ROM_PATCH_DIGEST_1 | 0x148 | + + +### Fields + +```wavejson +{"reg": [{"name": "ROM_PATCH_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------------|:--------------| +| 31:0 | ro | 0x0 | ROM_PATCH_DIGEST | | + +## HW_CFG0_DIGEST +Integrity digest for the HW_CFG0 partition. +The integrity digest is 0 by default. The digest calculation can be triggered via the [`DIRECT_ACCESS_CMD.`](#direct_access_cmd) +After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------------|:---------| +| HW_CFG0_DIGEST_0 | 0x14c | +| HW_CFG0_DIGEST_1 | 0x150 | + + +### Fields + +```wavejson +{"reg": [{"name": "HW_CFG0_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------|:--------------| +| 31:0 | ro | 0x0 | HW_CFG0_DIGEST | | + +## HW_CFG1_DIGEST +Integrity digest for the HW_CFG1 partition. +The integrity digest is 0 by default. The digest calculation can be triggered via the [`DIRECT_ACCESS_CMD.`](#direct_access_cmd) +After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------------|:---------| +| HW_CFG1_DIGEST_0 | 0x154 | +| HW_CFG1_DIGEST_1 | 0x158 | + + +### Fields + +```wavejson +{"reg": [{"name": "HW_CFG1_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------|:--------------| +| 31:0 | ro | 0x0 | HW_CFG1_DIGEST | | + +## SECRET0_DIGEST +Integrity digest for the SECRET0 partition. +The integrity digest is 0 by default. The digest calculation can be triggered via the [`DIRECT_ACCESS_CMD.`](#direct_access_cmd) +After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------------|:---------| +| SECRET0_DIGEST_0 | 0x15c | +| SECRET0_DIGEST_1 | 0x160 | + + +### Fields + +```wavejson +{"reg": [{"name": "SECRET0_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------|:--------------| +| 31:0 | ro | 0x0 | SECRET0_DIGEST | | + +## SECRET1_DIGEST +Integrity digest for the SECRET1 partition. +The integrity digest is 0 by default. The digest calculation can be triggered via the [`DIRECT_ACCESS_CMD.`](#direct_access_cmd) +After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------------|:---------| +| SECRET1_DIGEST_0 | 0x164 | +| SECRET1_DIGEST_1 | 0x168 | + + +### Fields + +```wavejson +{"reg": [{"name": "SECRET1_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------|:--------------| +| 31:0 | ro | 0x0 | SECRET1_DIGEST | | + +## SECRET2_DIGEST +Integrity digest for the SECRET2 partition. +The integrity digest is 0 by default. The digest calculation can be triggered via the [`DIRECT_ACCESS_CMD.`](#direct_access_cmd) +After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------------|:---------| +| SECRET2_DIGEST_0 | 0x16c | +| SECRET2_DIGEST_1 | 0x170 | + + +### Fields + +```wavejson +{"reg": [{"name": "SECRET2_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------|:--------------| +| 31:0 | ro | 0x0 | SECRET2_DIGEST | | + +## SECRET3_DIGEST +Integrity digest for the SECRET3 partition. +The integrity digest is 0 by default. The digest calculation can be triggered via the [`DIRECT_ACCESS_CMD.`](#direct_access_cmd) +After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked. +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------------|:---------| +| SECRET3_DIGEST_0 | 0x174 | +| SECRET3_DIGEST_1 | 0x178 | + + +### Fields + +```wavejson +{"reg": [{"name": "SECRET3_DIGEST", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------|:--------------| +| 31:0 | ro | 0x0 | SECRET3_DIGEST | | + +## SW_CFG_WINDOW +Any read to this window directly maps to the corresponding offset in the creator and owner software +config partitions, and triggers an OTP readout of the bytes requested. Note that the transaction +will block until OTP readout has completed. + +- Word Aligned Offset Range: `0x4000`to`0x7ffc` +- Size (words): `4096` +- Access: `ro` +- Byte writes are *not* supported. + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/theory_of_operation.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/theory_of_operation.md new file mode 100644 index 00000000000..b7673440598 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/doc/theory_of_operation.md @@ -0,0 +1,517 @@ +# Theory of Operation + +Conceptually speaking, the OTP functionality is at a high level split into "front-end" and "back-end". +The "front-end" contains the logical partitions that feed the hardware and software consumer interfaces of the system. +The "back-end" represents the programming interface used by hardware and software components to stage the upcoming values. +The diagram below illustrates this behavioral model. + +![OTP Controller Block Diagram](otp_ctrl_behavioral_model.svg) + +Note that the front-end contains both buffered and unbuffered partitions. +Buffered partitions are sensed once per power cycle and their contents are stored in registers, whereas unbuffered partitions are read on-demand. +The former are typically partitions that contain data like hardware configuration bits, key material and the life cycle state that need to be always available to the hardware, whereas the latter are large partitions that are accessed infrequently, such as the software configurations. +Values that are programmed into a buffered partition via the programming interface (coupled with read verification) are merely "staged", and do not take effect until the next power cycle. + +The sections below describe the operation of various pieces of the OTP controller and how it supports the described functionality. + +## Logical Partitions + +The OTP is logically separated into partitions that represent different functions. +This means the isolation is virtual and maintained by the OTP controller instead of the underlying OTP IP. + +Within each logical partition, there are specific enforceable properties + +- Confidentiality via secret partitions + - This controls whether a particular partition contains secret data. + - If secret, a partition is not readable by software once locked, and is scrambled in storage. +- Read lockability + - This controls whether a particular partition disables software readability for later stage software. + - Some partitions can be locked statically (by computing and storing an associated digest in OTP), others can be read locked at runtime via CSRs. +- Write lockability + - This controls whether a partition is locked and prevented from future updates. + - A locked partition is stored alongside a digest to be used later for integrity verification. +- Integrity Verification + - Once a partition is write-locked by calculating and writing a non-zero [digest](#locking-a-partition) to it, it can undergo periodic verification (time-scale configurable by software). +This verification takes two forms, partition integrity checks, and storage consistency checks. + +Since the OTP is memory-like in nature (it only outputs a certain number of bits per address location), some of the logical partitions are buffered in registers for instantaneous and parallel access by hardware. +This is a critical point, since after power-up, these particular OTP contents are stored in flip flops and sourced to the system. +I.e., buffered partitions are **NOT** directly sourced from the OTP macro itself. +Thus the security of both volatile (OTP controller) and non-volatile (OTP IP) storage becomes important. + +### Partition Listing and Description + +The OTP controller for this OpenTitan top-level contains the logical partitions shown below. + +{{#include otp_ctrl_partitions.md}} + +Generally speaking, the production life cycle of a device is split into 5 stages "Manufacturing" -> "Calibration and Testing" -> "Provisioning" -> "Mission" -> "RMA". +OTP values are usually programmed during "Calibration and Testing", "Provisioning" and "RMA" stages, as explained below. +A detailed listing of all the items and the corresponding memory map can be found in the [Programmer's Guide](programmers_guide.md). + +### Calibration and Test + +During this stage, the device is tested for functionality and calibrated to ensure uniformity. +The calibration can focus on a number of things, but usually is centered around adjusting clock, voltage and timing sources to remove process variation. +These calibration values are programmed into the CREATOR_SW_CFG partition, as they are non-secret values meant to be read out by software and programmed into respective peripherals. + +Early on during this stage, the various tokens are also programmed into the secret partitions and harvested by the silicon creator. + +### Provisioning + +During this stage, the device is provisioned with the final firmware and a "unique" seed or identity. +The secret partitions are populated with root secrets and keys that are critical to establishing the device identity. + +As part of injecting the final firmware, the stock-keeping-unit-specific hardware and software configurations are also programmed. + +### Life Cycle Partition + +The life cycle partition is active throughout all stages and hence it is the **ONLY** partition that cannot be locked. +After the device finishes provisioning and goes into production, it must retain the ability to transition back to RMA in case of unexpected failures. + +In order to support this transition, the [life cycle state](../../../../ip/lc_ctrl/README.md) and counters must always be update-able. + +## Locking a Partition + +Write access to a partition can be permanently locked when software determines it will no longer make any updates to that partition. +To lock, an integrity constant is calculated and programmed alongside the other data of that partition. +The size of that integrity constant depends on the partition size granule, and is either 32bit or 64bit. +The memory map detailing these can be found in the [Programmer's Guide](programmers_guide.md#direct-access-memory-map). + +Once the "integrity digest" is non-zero, no further updates are allowed. +If the partition is secret, software is in addition no longer able to read its contents (see [Secret vs Non-Secret Partitions](#secret-vs-non-secret-partitions)). + +Note however, in all partitions, the digest itself is **ALWAYS** readable. +This gives software an opportunity to confirm that the locking operation has proceeded correctly, and if not, scrap the part immediately. + +Calculation of the integrity digest depends on whether the partition requires periodic background verification. + +### Vendor Test Partition + +The vendor test partition is intended to be used for OTP programming smoke checks during the manufacturing flow. +The silicon creator may implement these checks inside the proprietary version of the `otp_macro` wrapper. +This partition behaves like any other SW partition, with the exception that ECC uncorrectable errors will not lead to fatal errors / alerts as they do in all other partitions. +This is due to the nature of the OTP programming smoke checks, which may leave certain OTP words in a state inconsistent with the ECC polynomial employed upon OTP readout. + +### Software Configuration Partitions + +The software configuration partitions are used as non-volatile storage for flags, configuration and calibration data. +As such, the contents of this partition are usually consumed once as part of code execution, or moved to another storage compartment somewhere in the design. +For example, the clock calibration values and the LDO calibration values are programmed to the analog sensor top (AST) at startup. + +As such, it is not necessary to check periodically at the OTP source. +Instead, software can simply check as part of secure boot and take other measures when these values are programmed into peripherals. + +For this partition it is thus the responsibility of software to calculate the integrity digest and program it into the OTP. +It is also reasonable to shadow (parts of) this partition in main memory, and there is not an immediate impact from OTP contents to hardware. + +### Hardware Configuration and Secret Partitions + +The hardware and secret partitions directly affect downstream hardware. +The contents must go through periodic integrity checks and therefore the stored digest is calculated by hardware when software provides the intent to lock (as opposed to the software partitions where the digest has to be calculated by software). + +### Life Cycle Partition + +The life cycle partition cannot be locked and will therefore not contain a stored digest. +Note however that only the life cycle controller has access to this partition, i.e., the Direct Access Interface (DAI) cannot read nor write from/to the life cycle partition. + +## Secret vs Non-Secret Partitions + +Non-secret OTP partitions hold data that can be public; or data that has no impact on security. +For example, the current value of lock bits or clock calibration values. +These values are stored in OTP as plaintext. + +Secret partitions contain data that are critical to security, for example FLASH scrambling keys, device root secret and unlock tokens. +These values are stored scrambled in OTP, and are descrambled upon read. +The currently employed cipher is PRESENT, as it lends itself well to iterative decomposition, and it is a proven lightweight block cipher (see also [PRESENT Scrambling Primitive](../../../../ip/prim/doc/prim_present.md). +The usage of a block cipher however implies that the secret partitions can only be written in 64bit chunks. + +Further, the contents of a particular secret partition are not readable by software once locked (other than the digest which must be always readable); while non-secret partitions are always readable unless read accessibility is explicitly removed by software. + +Unfortunately, secret partitions must utilize a global netlist key for the scrambling operation, as there is no other non-volatile storage to store a unique key. + + +## Partition Checks + +### Integrity + +Once the appropriate partitions have been locked, the hardware integrity checker employs two integrity checks to verify the content of the volatile buffer registers: + +1. All buffered partitions have additional ECC protection (8bit ECC for each 64bit block) that is concurrently monitored. +2. The digest of the partition is recomputed at semi-random intervals and compared to the digest stored alongside the partition. + +The purpose of this check is NOT to check between the storage flops and the OTP, but whether the buffer register contents remain consistent with the calculated digest. +This verification is primarily concerned with whether the storage flops have experienced fault attacks. +This check applies to only the HW_CFG* and SECRET* partitions. +If a failure is encountered, the OTP controller will send out a `fatal_check_error` alert and reset all of its hardware outputs to their defaults. + +### Storage Consistency + +This verification ensures the value stored in the buffer registers remain consistent with those in the OTP. +This process re-reads the OTP at semi-random intervals and confirms the value read is the same as the value stored. +Note, given there are integrity checks in parallel, it is not necessary for some partitions to check ALL read contents for consistency. +If there is an integrity digest, only the digest needs to be read; otherwise, all values must be read. + + +This check applies to LIFE_CYCLE, HW_CFG* and SECRET* partitions. +If a failure is encountered, the OTP controller will send out a `fatal_check_error` alert and reset all of its hardware outputs to their defaults. + +Note that checks applied to life cycle could cause a failure if life cycle is updated, because life cycle is the only partition that may contain live updates. +The controller hence detects this condition based on the `lc_check_byp_en_i` signal coming from the life cycle controller, and pauses background checks on this partition in order to prevent false positives. + +### Secret Partition Integrity Checks + +Since the secret partitions are stored scrambled, this also implies the integrity digest is calculated over the scrambled form. +In order to balance the amount of buffer registers needed, only the decrypted form of the secret partitions is held in buffer registers. +Hardware calculates the digest by re-scrambling the data before passing it through the digest. + + +## Power-up and Sense + +The OTP controller partition storage must output a specified safe default (it is not always 0 like a blank OTP) upon reset release. +This default output must remain until the OTP controller completes all checks. + +The OTP controller reads from the OTP IP. +If the reads pass OTP IP internal checks (for example ECC or redundancy), the partition storage is updated; however the output is still held at the default state via an output mux. +After all read is complete, the OTP controller performs integrity checks on the HW_CFG* and SECRET* partitions. +If a partition fails the integrity checks at this point it would signal an initialization error in the status CSR and abort further initialization. + +After all integrity checks are complete, the OTP controller releases the output gating and marks outputs as valid. +However, any partition marked with "error" continues to hold its output in the default state. + +Once the above steps are complete, the partition storage in buffered registers is not updated again (except for updates to the life cycle partition through the life cycle interface). +I.e., values programmed to OTP via the programming interface will not be visible in buffered registers until after the next power cycle. + +At this point, outputs of the partition storage are NOT expected to change unless a periodic check suddenly fails. +When this failure occurs, all outputs are reverted to their default state, and an alert is immediately triggered to the alert handler. +For timing purposes, OTP outputs can be treated as semi-static, as this error event should be rare and exceptional. + + +## Partition Defaults + +Partition defaults are context specific. +For example, a hardware configuration item that locks down specific access should default to "no access". +This ensures that a glitch attack on the OTP cannot easily revert the design to an insecure state. + +This hence suggests that when an OTP is all 0's and all 1's, it should, whenever possible, reflect an invalid or inert state in the encoding space of the affected item. +This also implies the reset state of consuming agents (for example key manager and life cycle), should default to invalid / inert state as well. + + +## Program and Read Ports + +As shown previously, the OTP is split into a front and back end. +The back-end interface is primarily used to update OTP contents, and read back for debug and verification purposes. +Despite being a separate functional access port from the logical partitions, the program and read ports are subjected to the same access controls. + +When a partition is write-locked, programming accesses are disallowed. +If the partition is secret, read accesses by the back-end interface are also disallowed (except for the digest which must always be readable). +Software can also disable any read accesses to the software configuration partitions via CSR settings to prevent later stage software from reading any content. + +The exception to the above is the life cycle partition. +The life cycle controller interface also acts as a "back-end" interface that always has programming access to ensure life cycle state can be advanced. + +Note, the program and read ports can conflict with ongoing background storage checks, and the OTP controller arbitrates between these two sides. +An in-progress operation will always be completed. +Afterwards, or when two requests arrive at the same time, the priority is life cycle > programming interface > on-demand read accesses via CSR windows > background checks. + + +## Programming the OTP + +The OTP controller has two programming paths: + +1. a functional programming path through software (the program port), +2. Life cycle programming path through hardware. + +The functional interface is used to update all partitions except for life cycle. +As mentioned previously, any updates made during the current power cycle are **NOT** reflected in the buffered partitions until the next reboot. + +The life cycle interface is used to update the life cycle state and transition counter only. +The commands are issued from the [life cycle controller](../../../../ip/lc_ctrl/README.md), and similarly, successful or failed indications are also sent back to the life cycle controller. +Similar to the functional interface, the life cycle controller allows only one update per power cycle, and after a requested transition reverts to an inert state until reboot. + +For more details on how the software programs the OTP, please refer to the [Programmer's Guide](programmers_guide.md). + + +## Design Details + +### Block Diagram + +The following is a high-level block diagram of the Earlygrey OTP that illustrates everything that has been discussed. + +![OTP Controller Block Diagram](otp_ctrl_blockdiag.svg) + +Each of the partitions (e.g. P0-P7 for Earlgrey) has its [own controller FSM](#partition-implementations) that interacts with the OTP wrapper and the [scrambling datapath](#scrambling-datapath) to fulfil its tasks. +The partitions expose the address ranges and access control information to the Direct Access Interface (DAI) in order to block accesses that go to locked address ranges. +Further, the only two blocks that have (conditional) write access to the OTP are the DAI and the Life Cycle Interface (LCI) blocks. +The partitions can only issue read transactions to the OTP macro. +Note that the access ranges of the DAI and the LCI are mutually exclusive. +I.e., the DAI cannot read from nor write to the life cycle partition. +The LCI cannot read the OTP, but is allowed to write to the life cycle partition. + +The CSR node on the left side of this diagram connects to the DAI, the OTP partitions (e.g. P0-P7 for Earlgrey) and the OTP wrapper through a gated TL-UL interface. +All connections from the partitions to the CSR node are read-only, and typically only carry a subset of the information available. +E.g., the secret partitions only expose their digest value via the CSRs. + +The Key Derivation Interface (KDI) on the bottom right side interacts with the scrambling datapath, the EDN and the partition holding the scrambling root keys in order to derive static and ephemeral scrambling keys for FLASH and SRAM scrambling. + +The test access gate shown at the top of the block diagram is governed by the life cycle qualification signal `dft_en_i`, which is only enabled during the TEST_UNLOCKED* life cycle states. +Otherwise, test access via this TL-UL window is locked down. + +In addition to the blocks mentioned so far, the OTP controller also contains an LFSR timer that creates pseudo-randomly distributed partition check requests, and provides pseudo random data at high bandwidth in the event of a secure erase request due to chip-wide alert escalation. +For security reasons, the LFSR is periodically reseeded with entropy coming from EDN. + +### Data Allocation and Packing +#### Software View + +The effective word width of an OTP IP typically depends on a couple of factors, including the redundancy scheme employed. +For this the design at hand, it is assumed that this native OTP word-width is 16bit. +For software convenience, however, these details are abstracted and the open-source OTP controller exposes the OTP storage as a linear address space of 32bit words, which is aligned with the machine word size of the Ibex processor. +Since the OTP IP employs a redundancy mechanism similar to ECC, this implies however that write operations take place at a granularity of 32bit blocks for non-secret and 64bit blocks for secret partitions (due to the scrambling). +Hence, software is responsible to appropriately pack and program items, since each 32bit location can only be programmed once. + +#### Life Cycle View + +Since the life cycle partition is the only partition that needs live updates in-field, proper care must be taken to properly encode data in this partition such that incremental updates are possible. +The life cycle state is hence encoded such that incremental updates to the state are always carried out at the granularity of a 16bit word. +Further, the life cycle transition counter is encoded such that each stroke consumes a full 16bit word for the same reason. + +See the [life cycle controller documentation](../../../../ip/lc_ctrl/README.md) for more details on the life cycle encoding. + +### Partition Controllers + +In RTL, we distinguish between buffered and unbuffered partition modules. +These are parameterized, such that we can assemble the array of OTP partitions with these two modules only. +The corresponding controller FSMs are explained in more detail below. + +#### Unbuffered Partition + +![Unbuffered Partition FSM](otp_ctrl_unbuf_part_fsm.svg) + +As shown above, the unbuffered partition module has a relatively simple controller FSM that only reads out the digest value of the partition upon initialization, and then basically waits for TL-UL read transactions to its corresponding window in the CSR space. + +Write access through the DAI will be locked in case the digest is set to a non-zero value. +Also, read access through the DAI and the CSR window can be locked at runtime via a CSR. +Read transactions through the CSR window will error out if they are out of bounds, or if read access is locked. + +Note that unrecoverable OTP errors, ECC failures in the digest register or external escalation via `lc_escalate_en` will move the partition controller into a terminal error state. + +#### Buffered Partition + +![Buffered Partition FSM](otp_ctrl_buf_part_fsm.svg) + +The controller FSM of the buffered partition module is more complex than the unbuffered counterpart, since it has to account for scrambling and digest calculation. + +Upon initialization, the controller reads out the whole partition and descrambles it on the fly if needed. + +Then, right after the initial readout, the partition controller jumps into the first integrity check, which behaves somewhat differently, depending on whether the partition is digest protected (or not) and/or scrambled (or not). +If the partition is not digest protected, or if the digest has not yet been computed, the check completes right away, and the buffered values are released for hardware broadcast. +Otherwise, the partition contents in the buffer registers are re-scrambled if needed, and a digest is computed on the fly. +If the computed digest matches with the one that has been read out before, the buffered registers are released for hardware broadcast. +Otherwise, the buffered values are gated to their default, and an alert is triggered through the error handling logic. + +After initialization, the integrity check (as described above) and the consistency check can be triggered by the LFSR timer mechanism on a periodic basis. + +The consistency check behaves differently, depending on whether the partition is digest protected or not. +If it is, the consistency check will read out the digest stored in OTP and compare it with the value stored in the buffer register. +Otherwise, if no digest is available, the controller will read out the whole partition from OTP, and compare it to the contents stored in the buffer registers. +In case of a mismatch, the buffered values are gated to their default, and an alert is triggered through the error handling logic. + +Note that in case of unrecoverable OTP errors or ECC failures in the buffer registers, the partition controller FSM is moved into a terminal error state, which locks down all access through DAI and clamps the values that are broadcast in hardware to their defaults. + +External escalation via the `lc_escalate_en` signal will move the partition controller FSM into the terminal error state as well. +See the [life cycle controller documentation](../../../../ip/lc_ctrl/README.md) for more details. + +### Direct Access Interface Control + +![Direct Access Interface FSM](otp_ctrl_dai_fsm.svg) + +Upon reset release, the DAI controller first sends an initialization command to the OTP macro. +Once the OTP macro becomes operational, an initialization request is sent to all partition controllers, which will read out and initialize the corresponding buffer registers. +The DAI then becomes operational once all partitions have initialized, and supports read, write and digest calculation commands. +More information about how to interact with the DAI through the CSRs can be found in the [Programmer's Guide](programmers_guide.md#direct-access-interface). + +Read and write commands transfer either 32bit or 64bit of data from the OTP to the corresponding CSR and vice versa. The access size is determined automatically, depending on whether the partition is scrambled or not. Also, (de)scrambling is performed transparently, depending on whether the partition is scrambled or not. + +Digest calculation commands read out the complete contents of a particular partition, compute a digest and write that digest value to the predefined location at the end of the partition. + +Note that any unrecoverable OTP error will move the DAI into a terminal error state, where all access through the DAI will be locked. +Also, the DAI consumes the read and write access information provided by the partition controller, and if a certain read or write access is not permitted, a recoverable error will be flagged in the status / error CSRs. + +### Life Cycle Interface Control + +![Life Cycle Interface FSM](otp_ctrl_lci_fsm.svg) + +Upon reset release the LCI FSM waits until the OTP controller has initialized and the LCI gets enabled. +Once it is in the idle state, life cycle state updates can be initiated via the life cycle interface (described in the [Hardware Interfaces](interfaces.md#state-transitions)). +The LCI controller takes the life cycle state to be programmed and writes all 16bit words to OTP. +In case of unrecoverable OTP errors, the FSM signals an error to the life cycle controller and moves into a terminal error state. + +### Key Derivation Interface + +![Key Derivation Interface FSM](otp_ctrl_kdi_fsm.svg) + +Upon reset release the KDI FSM waits until the OTP controller has initialized and the KDI gets enabled. +Once it is in the idle state, key derivation can be requested via the [flash](interfaces.md#interface-to-flash-scrambler) and [sram](interfaces.md#interface-to-sram-and-otbn-scramblers) interfaces. +Based on which interface makes the request, the KDI controller will evaluate a variant of the PRESENT digest mechanism as described in more detail below. + +### Scrambling Datapath + +![OTP Digest Mechanism](otp_ctrl_digest_mechanism.svg) + +The scrambling datapath is built around an iterative implementation of the [PRESENT lightweight cipher](../../../../ip/prim/doc/prim_present.md) that performs one round per cycle. +The datapath contains some additional multiplexing circuitry to enable the DAI, KDI and partition controllers to evaluate different functions with the same datapath. +The algorithmic steps of these functions are explained in more detail below. + +#### Scrambling + +As illustrated in subfigure a) in the diagram above, the standard 128bit-key PRESENT configuration with 31 rounds is used for scrambling operations. +The key used for scrambling is a global netlist constant chosen by the silicon creator, and all secret partitions are encrypted using the their own distinct netlist constant. +Note that the amount of data that is being scrambled is small (160byte = 20 x 64bit blocks) and the scrambled data remains constant. +Hence, no additional masking or diversification scheme is applied since only a very limited amount of information can be gathered by observing the scrambling operation via side-channels. + +#### Digest Calculation + +The integrity digests used in the [partition checks](#partition-checks) are computed using a custom [Merkle-Damgard](https://en.wikipedia.org/wiki/Merkle%E2%80%93Damg%C3%A5rd_construction) scheme, where the employed one-way compression function F is constructed by using PRESENT in a [Davies-Meyer arrangement](https://en.wikipedia.org/wiki/One-way_compression_function#Davies%E2%80%93Meyer). +This is illustrated in subfigure b). + +At the beginning of the digest calculation the 64bit state is initialized with an initialization vector (IV). +Then, the data to be digested is split into 128bit chunks, each of which is used as a 128bit key input for updating the 64bit state with the compression function F. +If a chunk is not an even number of 64bit blocks, its length is aligned to a multiple of 128 bits by repeating the last block. +After the blocks have been included, there is a finalization operation that consists of another 31-round encryption pass but with a finalization constant. +Note that both the IV as well as the finalization constant are global netlist constants chosen by the silicon creator. + +#### Scrambling Key Derivation + +The key derivation functions for ephemeral SRAM and static FLASH scrambling keys employ a similar construction as the digest calculation function. +In particular, the keys are derived by repeatedly reducing a (partially random) block of data into a 64bit block, as illustrated in subfigures c) and d). + +For ephemeral SRAM scrambling keys, the data block is composed of the 128bit SRAM_DATA_KEY_SEED stored in OTP, as well as 128bit of fresh entropy fetched from the EDN. +This process is repeated twice in order to produce a 128bit key. + +For static FLASH scrambling keys, the data block is composed of a 128bit part of either the FLASH_DATA_KEY_SEED or the FLASH_ADDR_KEY_SEED stored in OTP. +These key seeds are 256bit in size, allowing to use a unique chunk of 128bit of key seed data to derive a 64bit halve of a particular scrambling key. + +Note that the IV and finalization constants are distinct for SRAM and FLASH data and FLASH address scrambling keys. +These constants are chosen by the silicon creator prior to the tapeout. + +### Access Arbitration + +Access to the OTP wrapper and the scrambling datapath are both round-robin arbitrated, where the former arbitration occurs at cycle level (i.e., individual OTP memory accesses), and the latter occurs at the level of complete transactions (i.e., full digest or encryption). +Arbitration at transaction level is implemented similarly to cycle-based arbitration, with the difference that the grant signals remain asserted until the requestor deasserts the request (thereby releasing the arbiter, which acts as a mutex in this case). +This is behavior illustrated in the example below. + +```wavejson +{signal: [ + {name: 'clk_i', wave: 'p............'}, + {name: 'part_scrmbl_mtx_req[0]', wave: '01....0.1....'}, + {name: 'part_scrmbl_mtx_req[1]', wave: '0.1......0...'}, + {name: 'part_scrmbl_mtx_req[2]', wave: '0.1........0.'}, + {}, + {name: 'part_scrmbl_mtx_gnt[0]', wave: '01....0....1.'}, + {name: 'part_scrmbl_mtx_gnt[1]', wave: '0.....1..0...'}, + {name: 'part_scrmbl_mtx_gnt[2]', wave: '0........1.0.'}, +]} +``` + +### Primitive Wrapper and FPGA Emulation + +![OTP Wrapper Block Diagram](otp_ctrl_prim_otp.svg) + +The OTP IP is wrapped up in a primitive wrapper that exposes a TL-UL interface for testing purposes, and a generalized open-source interface for functional operation (described below). +Any OTP redundancy mechanism like per-word ECC is assumed to be handled inside the wrapper, which means that the word width exposed as part of the generalized interface is the effective word width. + +Note that the register space exposed via the TL-UL test interface, as well as DFT and power-related signals are dependent on the underlying proprietary OTP IP. +They are therefore not further described in this document. + +#### Generalized Open-source Interface + +The generalized open-source interface uses a couple of parameters (defaults set for Earlgrey configuration). + +Parameter | Default | Top Earlgrey | Description +---------------|-------------------------|-------------------------|--------------- +`Width` | 16 | 16 | Native OTP word width. +`Depth` | 1024 | 1024 | Depth of OTP macro. +`CmdWidth` | 7 | 7 | Width of the OTP command. +`ErrWidth` | 3 | 3 | Width of error code output signal. +`PwrSeqWidth` | 2 | 2 | Width of power sequencing signals to/from AST. +`SizeWidth` | 2 | 2 | Width of the size field. +`IfWidth` | 2^`SizeWidth` * `Width` | 2^`SizeWidth` * `Width` | Data interface width. + +The generalized open-source interface is a simple command interface with a ready / valid handshake that makes it possible to introduce back pressure if the OTP macro is not able to accept a command due to an ongoing operation. + +In order to facilitate the scrambling and digest operations, the data width has been sized such that data blocks up to the PRESENT block size (64bit) can be transferred across the generalized interface. The actual size of a transfer is determined via the size_i field. Transfer sizes are specified in multiples of the native OTP block size, as listed below. + +Value of `size_i` | #Native OTP Words | Bit Slice +------------------|-------------------|------------ +2'b00 | 1 | `{word0} = data[15:0]` +2'b01 | 2 | `{word1, word0} = data[31:0]` +2'b10 | 3 | `{word2, word1, word0} = data[47:0]` +2'b11 | 4 | `{word3, word2, word1, word0} = data[63:0]` + +Responses are returned in-order via an unidirectional response interface (i.e., without back pressure capability). +Downstream logic must be able to sink the response in any case. +The response optionally carries read data, depending on whether the operation that took place was a read or not. +Also, an error signal returns a non-zero error code in case an error occurred while carrying out the OTP command. + +The signals pertaining to the generalized open-source interface are listed below. + +Signal | Direction | Type | Description +------------------------|------------------|-----------------------------|--------------- +`fatal_alert_o` | `output` | `logic` | Fatal alert output from the primitive. This is connected to a separate alert channel in the instantiating IP. The instantiating IP latches the alert indication and continuously outputs alert events until reset. +`recov_alert_o` | `output` | `logic` | Recoverable alert output from the primitive. This is connected to a separate alert channel in the instantiating IP. Should only be pulsed high for each alert occurrence. The instantiating IP then sends out a single alert event for each pulse. +`ready_o` | `output` | `logic` | Ready signal for the command handshake. +`valid_i` | `input` | `logic` | Valid signal for the command handshake. +`size_i` | `input` | `logic [SizeWidth-1:0]` | Number of native OTP words to transfer, minus one: `2'b00 = 1 native word` ... `2'b11 = 4 native words`. +`cmd_i` | `input` | `logic [CmdWidth-1:0]` | OTP command: `7'b1000101 = read`, `7'b0110111 = write`, `7'b1111001 = read raw`, `7'b1100010 = write raw`, `7'b0101100 = initialize` +`addr_i` | `input` | `logic [$clog2(Depth)-1:0]` | OTP word address. +`wdata_i` | `input` | `logic [IfWidth-1:0]` | Write data for write commands. +`valid_o` | `output` | `logic` | Valid signal for command response. +`rdata_o` | `output` | `logic [IfWidth-1:0]` | Read data from read commands. +`err_o` | `output` | `logic [ErrWidth-1:0]` | Error code. + +The `write raw` and `read raw` command instructs the `otp_macro` wrapper to store / read the data in raw format without generating nor checking integrity information. +That means that the wrapper must return the raw, uncorrected data and no integrity errors. + +The `otp_macro` wrapper implements the `Macro*` error codes (0x0 - 0x4) defined in the [Programmer's Guide](programmers_guide.md#error-handling). + +The timing diagram below illustrates the timing of a command. +Note that both read and write commands return a response, and each command is independent of the previously issued commands. +The latency from accepting a command to returning a response depends on the underlying OTP IP and is typically larger than 10 cycles. +The returned values depend on the command type and whether an error occurred or not. + +```wavejson +{ + signal: [ + { name: 'clk_i', wave: 'p.............' }, + { name: 'ready_o', wave: '0..10|.10.|...' , node: '...a...c'}, + { name: 'valid_i', wave: '01..0|1.0.|...' }, + { name: 'size_i', wave: '03..0|3.0.|...' }, + { name: 'cmd_i', wave: '04..0|4.0.|...' }, + { name: 'wdata_i', wave: '05..0|5.0.|...' }, + { name: 'valid_o', wave: '0....|..10|.10' , node: '........b...d'}, + { name: 'rdata_o', wave: '0....|..50|.50' }, + { name: 'err_o', wave: '0....|..40|.40' }, + ], + edge: [ + 'a~>b', + 'c~>d', + ], + head: { + text: 'Timing of an OTP command.', + }, + foot: { + text: "Cmd's are accepted in cycles 3/7, and the corresponding responses return in cycles 8/12.", + tick: 0, + } +} +``` + +Note that the open source OTP controller allows up to two outstanding OTP commands, meaning that it is permissible to acknowledge an incoming command and start working on it while the results of the last command are still in the process of being output (e.g., due to an output register stage). + +#### Generic Simulation and FPGA Emulation Model + +For open-source simulation and FPGA emulation, a synthesizable and generic OTP wrapper module is provided (`otp_macro`). +This is automatically selected in the OpenTitan build flow via the technology primitive mechanism if no proprietary OTP macro is available for a specific technology. +The OTP storage in `otp_macro` is emulated using a standard RAM primitive `prim_generic_ram_1p`. +While this storage element is volatile, the primitive is constructed such that the contents are not wiped upon a system-wide reset. +I.e., only a power-cycle wipes the RAM primitive, thereby enabling limited emulation of the OTP function and life cycle transitions also on an FPGA device. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/README.md new file mode 100644 index 00000000000..9379ba9d93b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/README.md @@ -0,0 +1,144 @@ +# OTP_CTRL DV document + +## Goals +* **DV** + * Verify all OTP_CTRL IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + +## Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/latest/report.html) + +## Design features +For detailed information on OTP_CTRL design features, please see the [OTP_CTRL HW IP technical specification](../README.md). + +## Testbench architecture +OTP_CTRL testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at `hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tb.sv`. It instantiates the OTP_CTRL DUT module `hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv`. +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* OTP_CTRL IOs +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Global types & methods +All common types and methods defined at the package level can be found in +`otp_ctrl_env_pkg`. Some of them in use are: +```systemverilog + parameter uint SCRAMBLE_DATA_SIZE = 64; + parameter uint SCRAMBLE_KEY_SIZE = 128; + parameter uint NUM_ROUND = 31; + + typedef enum bit [2:0] { + OtpNoError, + OtpMacroError, + OtpMacroEccCorrError, + OtpMacroEccUncorrError, + OtpMacroWriteBlankError, + OtpAccessError, + OtpCheckFailError, + OtpFsmStateError + } otp_err_code_e; +``` + +### TL_agent +OTP_CTRL testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md), which provides the ability to drive and independently monitor random traffic via TL host interface into OTP_CTRL device. + +### Alert_agents +OTP_CTRL testbench instantiates (already handled in CIP base env) two [alert_agents](../../../../dv/sv/alert_esc_agent/README.md): +fatal_check_alert and fatal_macro_alert. +The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in OTP_CTRL device. + +### OTP_CTRL interface +OTP_CTRL design has specific inputs and outputs to communicate with other IPs including LC_CTRL, OTBN, SRAM, FLASH etc. +This interface is created to initialize, use simple task to drive, and use assertions to monitor these signals. + +### Memory backdoor interface +OTP_CTRL testbench binds design's non-volatile OTP memory with a [`mem_bkdr_util`](../../../../dv/sv/mem_bkdr_util/README.md), which supports read, write, and injection of ECC errors to design's OTP memory. + +### UVM RAL model +The OTP_CTRL RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md). + +### Reference models +The OTP_CTRL's utilizes [PRESENT](../../../../ip/prim/doc/prim_present.md as the cipher to scramble and protect secrets. +Thus OTP_CTRL's scoreboard adopted PRESENT's C reference model, located under `hw/ip/prim/dv/prim_present/` folder, for encryption and decryption purpose. + +### Stimulus strategy +#### Test sequences +All test sequences reside in `hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib`. +The `otp_ctrl_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +All test sequences are extended from `otp_ctrl_base_vseq`. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: +* dai_wr: This task triggers an OTP write sequence via the DAI interface. +* dai_rd: This task triggers an OTP read sequence via the DAI interface. +* trigger_checks: This task triggers a one-time OTP check and user can choose to trigger consistency check or integrity check. +* randomize_dai_addr: This task takes a DAI address as input and randomize its last two bits, because the last two bits should be ignored in design. + +#### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following two files declared OTP_CTRL's covergroups: +- `dv/env/otp_ctrl_env_cov.sv` declares functional or CSR related covergroups. +The functional coverage is collected manually inside OTP_CTRL's scoreboard by invoking the `sample` function. +- `dv/cov/otp_ctrl_cov_if.sv` declares interface signal related covergroups. +The functional coverage is collected automatically when the sampled signal is active. + +### Self-checking strategy +#### Scoreboard +The `otp_ctrl_scoreboard` is primarily used for end to end checking. +It creates the following analysis ports to retrieve the data monitored by corresponding interface agents: +* tl_a_chan_fifo: tl address channel +* tl_d_chan_fifo: tl data channel +* alert_fifos: alert handshakes +* sram_fifos: sram requests +* otbn_fifo: otbn request +* lc_prog_fifo: life cycle programming request +* lc_token_fifo: life cycle token request +* edn_fifo: edn response to OTP_CTRL + +For all requests to OTP_CTRL as listed above, scoreboard has a corresponding task to process request, check OTP_CTRL's response value against encryption, and collect coverage. + +OTP_CTRL's scoreboard has an internal array `otp_a` that tracks OTP memory data. +Every successful OTP write operation will update this internal array, and every successful OTP read operation will check the readout value against this internal array. +Note that in design, secret partitions will go through a encryption before writing to the actually OTP memory, and will be decrypted upon a read request. +For the simplicity of this internal array, we will skip this procedure. +However, if scoreboard backdoor read any secret partitions, we will decrypt the data then write the decrypted data to the internal array. +For any operation that fails, the scoreboard will predict the status and err_code according to the failure type. +If the error can trigger alert, scoreboard will use `set_exp_alert` task to check if the alert is firing correctly. +If a HW digest operation is triggered by sequence, scoreboard will calculate digest value with partition data from its internal array and update the digest value. +According to design spec, scoreboard won't lock the partition and predict the digest value to digest registers until next power cycle. + +If a reset or lc_escalation_en is issued during an OTP_CTRL write operation, scoreboard cannot accurately predict how many bits have been programmed into OTP memory. +To avoid mismatches, scoreboard utilizes flags `dai_wr_ip` and `dai_digest_ip` to track otp write operations, and issue a backdoor read if the write operation is interrupted. + +#### Assertions +* TLUL assertions: The `tb/otp_ctrl_bind.sv` binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. +* OTP_CTRL_IF assertions: This interface has assertions to ensure certain OTP_CTRL's outputs (such as: otp_broadcast_o, keymgr_key_o) are stable after OTP initialization. + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/otp_ctrl_sim_cfg.hjson -i otp_ctrl_smoke +``` + +## Testplan +[Testplan](../data/otp_ctrl_testplan.hjson) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov.core b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov.core new file mode 100644 index 00000000000..f49c3bb89a2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov.core @@ -0,0 +1,26 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:otp_ctrl_cov +description: "OTP_CTRL functional coverage and bind files" + +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg + - lowrisc:darjeeling_no_ibex_ip:otp_ctrl_top_specific_pkg + + files_dv: + depend: + - lowrisc:dv:dv_utils + files: + - otp_ctrl_cov_if.sv + - otp_ctrl_cov_bind.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv new file mode 100644 index 00000000000..8193cfe9662 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_bind.sv @@ -0,0 +1,111 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Binds OTP_CTRL functional coverage interface to the top level OTP_CTRL module. +// +`define PART_MUBI_COV(__part_name, __index) \ + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) ``__part_name``_read_lock_mubi_cov_if ( \ + .rst_ni (rst_ni), \ + .mubi (part_access[``__index``].read_lock) \ + ); \ + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) ``__part_name``_write_lock_mubi_cov_if ( \ + .rst_ni (rst_ni), \ + .mubi (part_access[``__index``].write_lock) \ + ); + +`define DAI_MUBI_COV(__part_name, __index) \ + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) dai_``__part_name``_read_lock_mubi_cov_if ( \ + .rst_ni (rst_ni), \ + .mubi (part_access_dai[``__index``].read_lock) \ + ); \ + bind otp_ctrl cip_mubi_cov_if #(.Width(8)) dai_``__part_name``_write_lock_mubi_cov_if ( \ + .rst_ni (rst_ni), \ + .mubi (part_access_dai[``__index``].write_lock) \ + ); + +module otp_ctrl_cov_bind; + import otp_ctrl_part_pkg::*; + + bind otp_ctrl otp_ctrl_cov_if u_otp_ctrl_cov_if ( + .pwr_otp_o (pwr_otp_o), + .lc_otp_program_i (lc_otp_program_i), + .lc_escalate_en_i (lc_escalate_en_i), + .sram_otp_key_i (sram_otp_key_i), + .otbn_otp_key_i (otbn_otp_key_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_creator_seed_sw_rw_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_creator_seed_sw_rw_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_seed_hw_rd_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_seed_hw_rd_en_i) + ); + + bind otp_macro cip_lc_tx_cov_if u_lc_dft_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_dft_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_escalate_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_escalate_en_i) + ); + + bind otp_ctrl cip_lc_tx_cov_if u_lc_check_byp_en_cov_if ( + .rst_ni (rst_ni), + .val (lc_check_byp_en_i) + ); + + // Mubi internal coverage for buffered and unbuffered partitions. + `PART_MUBI_COV(vendor_test, otp_ctrl_part_pkg::VendorTestIdx) + `PART_MUBI_COV(creator_sw_cfg, otp_ctrl_part_pkg::CreatorSwCfgIdx) + `PART_MUBI_COV(owner_sw_cfg, otp_ctrl_part_pkg::OwnerSwCfgIdx) + `PART_MUBI_COV(ownership_slot_state, otp_ctrl_part_pkg::OwnershipSlotStateIdx) + `PART_MUBI_COV(rot_creator_auth, otp_ctrl_part_pkg::RotCreatorAuthIdx) + `PART_MUBI_COV(rot_owner_auth_slot0, otp_ctrl_part_pkg::RotOwnerAuthSlot0Idx) + `PART_MUBI_COV(rot_owner_auth_slot1, otp_ctrl_part_pkg::RotOwnerAuthSlot1Idx) + `PART_MUBI_COV(plat_integ_auth_slot0, otp_ctrl_part_pkg::PlatIntegAuthSlot0Idx) + `PART_MUBI_COV(plat_integ_auth_slot1, otp_ctrl_part_pkg::PlatIntegAuthSlot1Idx) + `PART_MUBI_COV(plat_owner_auth_slot0, otp_ctrl_part_pkg::PlatOwnerAuthSlot0Idx) + `PART_MUBI_COV(plat_owner_auth_slot1, otp_ctrl_part_pkg::PlatOwnerAuthSlot1Idx) + `PART_MUBI_COV(plat_owner_auth_slot2, otp_ctrl_part_pkg::PlatOwnerAuthSlot2Idx) + `PART_MUBI_COV(plat_owner_auth_slot3, otp_ctrl_part_pkg::PlatOwnerAuthSlot3Idx) + `PART_MUBI_COV(ext_nvm, otp_ctrl_part_pkg::ExtNvmIdx) + `PART_MUBI_COV(rom_patch, otp_ctrl_part_pkg::RomPatchIdx) + `PART_MUBI_COV(hw_cfg0, otp_ctrl_part_pkg::HwCfg0Idx) + `PART_MUBI_COV(hw_cfg1, otp_ctrl_part_pkg::HwCfg1Idx) + `PART_MUBI_COV(secret0, otp_ctrl_part_pkg::Secret0Idx) + `PART_MUBI_COV(secret1, otp_ctrl_part_pkg::Secret1Idx) + `PART_MUBI_COV(secret2, otp_ctrl_part_pkg::Secret2Idx) + `PART_MUBI_COV(secret3, otp_ctrl_part_pkg::Secret3Idx) + + // Mubi internal coverage for DAI interface access + `DAI_MUBI_COV(vendor_test, otp_ctrl_part_pkg::VendorTestIdx) + `DAI_MUBI_COV(creator_sw_cfg, otp_ctrl_part_pkg::CreatorSwCfgIdx) + `DAI_MUBI_COV(owner_sw_cfg, otp_ctrl_part_pkg::OwnerSwCfgIdx) + `DAI_MUBI_COV(ownership_slot_state, otp_ctrl_part_pkg::OwnershipSlotStateIdx) + `DAI_MUBI_COV(rot_creator_auth, otp_ctrl_part_pkg::RotCreatorAuthIdx) + `DAI_MUBI_COV(rot_owner_auth_slot0, otp_ctrl_part_pkg::RotOwnerAuthSlot0Idx) + `DAI_MUBI_COV(rot_owner_auth_slot1, otp_ctrl_part_pkg::RotOwnerAuthSlot1Idx) + `DAI_MUBI_COV(plat_integ_auth_slot0, otp_ctrl_part_pkg::PlatIntegAuthSlot0Idx) + `DAI_MUBI_COV(plat_integ_auth_slot1, otp_ctrl_part_pkg::PlatIntegAuthSlot1Idx) + `DAI_MUBI_COV(plat_owner_auth_slot0, otp_ctrl_part_pkg::PlatOwnerAuthSlot0Idx) + `DAI_MUBI_COV(plat_owner_auth_slot1, otp_ctrl_part_pkg::PlatOwnerAuthSlot1Idx) + `DAI_MUBI_COV(plat_owner_auth_slot2, otp_ctrl_part_pkg::PlatOwnerAuthSlot2Idx) + `DAI_MUBI_COV(plat_owner_auth_slot3, otp_ctrl_part_pkg::PlatOwnerAuthSlot3Idx) + `DAI_MUBI_COV(ext_nvm, otp_ctrl_part_pkg::ExtNvmIdx) + `DAI_MUBI_COV(rom_patch, otp_ctrl_part_pkg::RomPatchIdx) + `DAI_MUBI_COV(hw_cfg0, otp_ctrl_part_pkg::HwCfg0Idx) + `DAI_MUBI_COV(hw_cfg1, otp_ctrl_part_pkg::HwCfg1Idx) + `DAI_MUBI_COV(secret0, otp_ctrl_part_pkg::Secret0Idx) + `DAI_MUBI_COV(secret1, otp_ctrl_part_pkg::Secret1Idx) + `DAI_MUBI_COV(secret2, otp_ctrl_part_pkg::Secret2Idx) + `DAI_MUBI_COV(secret3, otp_ctrl_part_pkg::Secret3Idx) + +`undef PART_MUBI_COV +`undef DAI_MUBI_COV +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_fsm_unr_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_fsm_unr_excl.el new file mode 100644 index 00000000000..1c3412b6954 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_fsm_unr_excl.el @@ -0,0 +1,199 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The current UNR flow marks some transition to reset states as unreachable. +// This file manually removed the reset transition states. +//================================================== +// This file contains the Excluded objects +// Generated By User: chencindy +// Format Version: 2 +// Date: Fri Jan 6 11:14:02 2023 +// ExclMode: default +//================================================== +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[3].gen_buffered.u_part_buf +Fsm state_q "441128463" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +Transition IntegDigSt->IntegDigFinSt "1890->1765" +Fsm state_q "441128463" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +State IntegScrSt "3418" +Fsm state_q "441128463" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +State InitDescrSt "3204" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[4].gen_buffered.u_part_buf +Fsm state_q "441128463" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm state_q "441128463" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +State IntegDigPadSt "855" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +Fsm state_q "441128463" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm state_q "441128463" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +State IntegDigPadSt "855" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +Fsm state_q "441128463" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm state_q "441128463" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +State IntegDigPadSt "855" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2063559012 2582220255" +INSTANCE: tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf +Fsm state_q "441128463" +Transition IdleSt->IntegDigClrSt "1357->2625" +Fsm state_q "441128463" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +State IntegDigFinSt "1765" +Fsm state_q "441128463" +State IntegDigPadSt "855" +Fsm state_q "441128463" +State IntegDigSt "1890" +Fsm state_q "441128463" +State IntegDigWaitSt "2290" +Fsm state_q "441128463" +State IntegScrSt "3418" +Fsm state_q "441128463" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +State InitDescrSt "3204" +Fsm error_q "2410907799" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2410907799" +Transition CheckFailError->FsmStateError "6->7" +CHECKSUM: "2940612991 27342893" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +Fsm error_q "2210720134" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +Transition MacroEccCorrError->AccessError "2->5" +Fsm error_q "2210720134" +Transition AccessError->CheckFailError "5->6" +CHECKSUM: "2940612991 27342893" +INSTANCE: tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf +Fsm error_q "2210720134" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +Transition MacroEccCorrError->AccessError "2->5" +Fsm error_q "2210720134" +Transition AccessError->CheckFailError "5->6" +CHECKSUM: "2940612991 27342893" +INSTANCE: tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf +Fsm error_q "2210720134" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +Transition MacroEccCorrError->AccessError "2->5" +Fsm error_q "2210720134" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +Transition AccessError->CheckFailError "5->6" +CHECKSUM: "4205406832 4258846959" +INSTANCE: tb.dut.u_otp_ctrl_dai +Fsm error_q "1085514286" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "1085514286" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "1085514286" +Transition AccessError->MacroEccCorrError "5->2" +CHECKSUM: "761735614 2379312231" +INSTANCE: tb.dut.u_otp_ctrl_kdi +Fsm state_q "2979668442" +Transition DigWaitSt->FinishSt "913->760" +Fsm state_q "2979668442" +Transition DigWaitSt->DigLoadSt "913->183" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv new file mode 100644 index 00000000000..344adf6845b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_if.sv @@ -0,0 +1,77 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Implements functional coverage for OTP_CTRL + +interface otp_ctrl_cov_if + import otp_ctrl_reg_pkg::*; + ( + input pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o, + input otp_ctrl_pkg::lc_otp_program_req_t lc_otp_program_i, + input bit [3:0] lc_escalate_en_i, + input otp_ctrl_pkg::sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, + input otp_ctrl_pkg::otbn_otp_key_req_t otbn_otp_key_i + ); + + import uvm_pkg::*; + import dv_utils_pkg::*; + `include "dv_fcov_macros.svh" + + covergroup lc_esc_en_condition_cg @(lc_escalate_en_i == lc_ctrl_pkg::On); + lc_esc_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + lc_esc_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + lc_esc_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_esc_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + lc_esc_during_lc_otp_prog_req: coverpoint lc_otp_program_i.req; + endgroup + + + covergroup sram_0_req_condition_cg @(sram_otp_key_i[0].req); + sram_0_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + sram_0_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + sram_0_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_0_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + covergroup sram_1_req_condition_cg @(sram_otp_key_i[1].req); + sram_1_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + sram_1_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + sram_1_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + sram_1_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + covergroup otbn_req_condition_cg @(otbn_otp_key_i.req); + otbn_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + otbn_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + otbn_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + otbn_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + covergroup lc_prog_req_condition_cg @(lc_otp_program_i.req); + lc_prog_req_during_lc_esc: coverpoint lc_escalate_en_i { + bins lc_esc_on = {lc_ctrl_pkg::On}; + bins lc_esc_off = {[0 : lc_ctrl_pkg::On-1], [lc_ctrl_pkg::On+1 : '1]}; + } + lc_prog_req_during_sram_0_req: coverpoint sram_otp_key_i[0].req; + lc_prog_req_during_sram_1_req: coverpoint sram_otp_key_i[1].req; + lc_prog_req_during_otbn_req: coverpoint otbn_otp_key_i.req; + lc_prog_req_during_otp_idle: coverpoint pwr_otp_o.otp_idle; + endgroup + + `DV_FCOV_INSTANTIATE_CG(lc_esc_en_condition_cg) + `DV_FCOV_INSTANTIATE_CG(sram_0_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(sram_1_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(otbn_req_condition_cg) + `DV_FCOV_INSTANTIATE_CG(lc_prog_req_condition_cg) + +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el new file mode 100644 index 00000000000..b622e16e90f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cov_unr_excl.el @@ -0,0 +1,6133 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Generated UNR file from Synopsys UNR tool with security modules being black-boxed. +//================================================== +// This file contains the Excluded objects +// Generated By User: miguelosorio +// Format Version: 2 +// Date: Fri Aug 30 23:42:43 2024 +// ExclMode: default +//================================================== +CHECKSUM: "2868806991 3096942133" +INSTANCE: tb.dut.gen_alert_tx[4].u_prim_alert_sender +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 alert_ack_o "logic alert_ack_o" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 alert_ack_o "logic alert_ack_o" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 alert_state_o "logic alert_state_o" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 alert_state_o "logic alert_state_o" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "1436819047 249500095" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [0] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [1] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [2] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [3] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [4] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [5] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [6] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 syndrome_o [7] "logic syndrome_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [0] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 err_o [1] "logic err_o[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o [1] "logic err_o[1:0]" +CHECKSUM: "3215070453 3446030929" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Block 19 "4019242409" "wptr_wrap_cnt_q <= (wptr_wrap_cnt_q + {{(WrapPtrW - 1) {1'b0}}, 1'b1});" +ANNOTATION: "VC_COV_UNR" +Block 28 "1113085816" "rptr_wrap_cnt_q <= (rptr_wrap_cnt_q + {{(WrapPtrW - 1) {1'b0}}, 1'b1});" +CHECKSUM: "3215070453 3446030929" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Block 19 "4019242409" "wptr_wrap_cnt_q <= (wptr_wrap_cnt_q + {{(WrapPtrW - 1) {1'b0}}, 1'b1});" +ANNOTATION: "VC_COV_UNR" +Block 28 "1113085816" "rptr_wrap_cnt_q <= (rptr_wrap_cnt_q + {{(WrapPtrW - 1) {1'b0}}, 1'b1});" +CHECKSUM: "3215070453 3446030929" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Block 19 "4019242409" "wptr_wrap_cnt_q <= (wptr_wrap_cnt_q + {{(WrapPtrW - 1) {1'b0}}, 1'b1});" +ANNOTATION: "VC_COV_UNR" +Block 28 "1113085816" "rptr_wrap_cnt_q <= (rptr_wrap_cnt_q + {{(WrapPtrW - 1) {1'b0}}, 1'b1});" +CHECKSUM: "3171246264 1537087436" +INSTANCE: tb.dut.u_otp +ANNOTATION: "VC_COV_UNR" +Block 24 "3494210324" ";" +CHECKSUM: "3665351474 3190968676" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 22 "662519215" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 23 "617613755" "state_d = InitDescrWaitSt;" +ANNOTATION: "VC_COV_UNR" +Block 25 "2942482414" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 26 "3475289755" "state_d = InitSt;" +ANNOTATION: "VC_COV_UNR" +Block 68 "746922678" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 69 "369318088" "state_d = IntegScrWaitSt;" +ANNOTATION: "VC_COV_UNR" +Block 71 "1545788457" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 72 "2540127236" "state_d = IntegDigSt;" +ANNOTATION: "VC_COV_UNR" +Block 78 "4176855572" "state_d = IntegDigPadSt;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 87 "984470440" "state_d = IntegDigFinSt;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3665351474 328877407" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 22 "662519215" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 23 "617613755" "state_d = InitDescrWaitSt;" +ANNOTATION: "VC_COV_UNR" +Block 25 "2942482414" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 26 "3475289755" "state_d = InitSt;" +ANNOTATION: "VC_COV_UNR" +Block 68 "746922678" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 69 "369318088" "state_d = IntegScrWaitSt;" +ANNOTATION: "VC_COV_UNR" +Block 71 "1545788457" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 72 "2540127236" "state_d = IntegDigSt;" +ANNOTATION: "VC_COV_UNR" +Block 77 "3141955456" "scrmbl_cmd_o = Digest;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3665351474 4034042967" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 78 "4176855572" "state_d = IntegDigPadSt;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 87 "984470440" "state_d = IntegDigFinSt;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3665351474 2385925532" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 78 "4176855572" "state_d = IntegDigPadSt;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 87 "984470440" "state_d = IntegDigFinSt;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3665351474 2380508828" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 78 "4176855572" "state_d = IntegDigPadSt;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 87 "984470440" "state_d = IntegDigFinSt;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3665351474 3973220603" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf +ANNOTATION: "VC_COV_UNR" +Block 22 "662519215" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 25 "2942482414" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 68 "746922678" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 71 "1545788457" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 74 "736744825" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 86 "1288945484" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 89 "967932616" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 92 "3253244488" "scrmbl_mtx_req_o = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 105 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 106 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "3882079776 1965827338" +INSTANCE: tb.dut.u_otp_ctrl_scrmbl +ANNOTATION: "VC_COV_UNR" +Block 28 "3494210324" ";" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field3 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field4 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field5 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field6 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field7 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field8 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field2 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field3 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field4 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field5 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field0 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field1 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field2 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "4255502330 223073768" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field3 +ANNOTATION: "VC_COV_UNR" +Block 4 "1824183207" "q <= wr_data;" +CHECKSUM: "3162909804 919553166" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Block 17 "814628507" "error_d = MacroEccCorrError;" +ANNOTATION: "VC_COV_UNR" +Block 32 "3415759745" "error_d = MacroEccCorrError;" +CHECKSUM: "3162909804 2229302740" +INSTANCE: tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Block 44 "1192338528" "state_d = ErrorSt;" +ANNOTATION: "VC_COV_UNR" +Block 45 "2515805717" "error_d = CheckFailError;" +CHECKSUM: "662936270 450589591" +INSTANCE: tb.dut.u_tlul_adapter_sram +ANNOTATION: "VC_COV_UNR" +Block 22 "3478134645" "d_valid = 1'b1;" +CHECKSUM: "3436844037 1915699783" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Block 15 "1636116421" "tlul_oob_err_d = 1'b1;" +ANNOTATION: "VC_COV_UNR" +Block 32 "3434355351" "part_access_pre[k] = {2 {MuBi8True}};" +CHECKSUM: "1158524476 3747170265" +INSTANCE: tb.dut.u_otp_ctrl_kdi +ANNOTATION: "VC_COV_UNR" +Block 88 "3038555774" "state_d = DigLoadSt;" +CHECKSUM: "1611327958 113940473" +INSTANCE: tb.dut.u_otp.u_reg_top +ANNOTATION: "VC_COV_UNR" +Condition 20 "3585319611" "(reg_we && ((!addrmiss))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 22 "1026062099" "(addrmiss | wr_err | intg_err) 1 -1" (4 "100") +CHECKSUM: "3171246264 2882888745" +INSTANCE: tb.dut.u_otp +ANNOTATION: "VC_COV_UNR" +Condition 1 "2104830463" "(cmd_i == Init) 1 -1" (1 "0") +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->CheckFailError "5->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition MacroEccCorrError->AccessError "2->5" +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->CheckFailError "5->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition MacroEccCorrError->AccessError "2->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition MacroEccCorrError->CheckFailError "2->6" +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->CheckFailError "5->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition MacroEccCorrError->AccessError "2->5" +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +State CheckFailError "6" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition MacroEccCorrError->AccessError "2->5" +CHECKSUM: "3436844037 2267239089" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_ast_pwr_seq_o.pwr_seq [0] "logic otp_ast_pwr_seq_o.pwr_seq[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_ast_pwr_seq_o.pwr_seq [0] "logic otp_ast_pwr_seq_o.pwr_seq[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_ast_pwr_seq_o.pwr_seq [1] "logic otp_ast_pwr_seq_o.pwr_seq[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_ast_pwr_seq_o.pwr_seq [1] "logic otp_ast_pwr_seq_o.pwr_seq[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [0] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [0] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [1] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [1] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [2] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [2] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [3] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [3] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [4] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [4] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [5] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [5] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [6] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [6] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [7] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [7] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [8] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [8] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [9] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [9] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [10] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [10] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [11] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [11] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [12] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [12] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [13] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [13] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [14] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [14] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [15] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [15] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [16] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [16] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [17] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [17] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [18] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [18] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [19] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [19] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [20] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [20] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [21] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [21] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [22] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [22] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [23] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [23] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [24] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [24] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [25] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [25] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [26] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [26] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [27] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [27] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [28] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [28] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [29] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [29] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [30] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [30] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 lc_otp_vendor_test_o.status [31] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 lc_otp_vendor_test_o.status [31] "logic lc_otp_vendor_test_o.status[31:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed_valid "logic otp_keymgr_key_o.owner_seed_valid" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed_valid "logic otp_keymgr_key_o.owner_seed_valid" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [0] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [0] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [1] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [1] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [2] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [2] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [3] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [3] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [4] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [4] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [5] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [5] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [6] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [6] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [7] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [7] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [8] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [8] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [9] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [9] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [10] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [10] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [11] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [11] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [12] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [12] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [13] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [13] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [14] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [14] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [15] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [15] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [16] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [16] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [17] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [17] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [18] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [18] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [19] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [19] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [20] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [20] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [21] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [21] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [22] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [22] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [23] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [23] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [24] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [24] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [25] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [25] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [26] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [26] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [27] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [27] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [28] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [28] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [29] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [29] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [30] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [30] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [31] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [31] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [32] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [32] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [33] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [33] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [34] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [34] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [35] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [35] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [36] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [36] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [37] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [37] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [38] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [38] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [39] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [39] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [40] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [40] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [41] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [41] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [42] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [42] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [43] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [43] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [44] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [44] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [45] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [45] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [46] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [46] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [47] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [47] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [48] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [48] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [49] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [49] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [50] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [50] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [51] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [51] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [52] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [52] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [53] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [53] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [54] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [54] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [55] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [55] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [56] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [56] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [57] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [57] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [58] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [58] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [59] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [59] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [60] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [60] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [61] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [61] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [62] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [62] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [63] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [63] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [64] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [64] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [65] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [65] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [66] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [66] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [67] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [67] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [68] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [68] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [69] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [69] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [70] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [70] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [71] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [71] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [72] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [72] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [73] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [73] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [74] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [74] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [75] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [75] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [76] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [76] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [77] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [77] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [78] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [78] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [79] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [79] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [80] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [80] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [81] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [81] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [82] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [82] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [83] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [83] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [84] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [84] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [85] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [85] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [86] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [86] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [87] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [87] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [88] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [88] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [89] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [89] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [90] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [90] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [91] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [91] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [92] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [92] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [93] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [93] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [94] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [94] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [95] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [95] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [96] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [96] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [97] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [97] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [98] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [98] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [99] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [99] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [100] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [100] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [101] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [101] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [102] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [102] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [103] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [103] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [104] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [104] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [105] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [105] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [106] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [106] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [107] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [107] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [108] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [108] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [109] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [109] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [110] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [110] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [111] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [111] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [112] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [112] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [113] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [113] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [114] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [114] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [115] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [115] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [116] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [116] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [117] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [117] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [118] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [118] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [119] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [119] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [120] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [120] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [121] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [121] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [122] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [122] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [123] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [123] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [124] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [124] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [125] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [125] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [126] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [126] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [127] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [127] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [128] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [128] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [129] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [129] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [130] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [130] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [131] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [131] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [132] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [132] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [133] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [133] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [134] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [134] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [135] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [135] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [136] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [136] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [137] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [137] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [138] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [138] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [139] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [139] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [140] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [140] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [141] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [141] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [142] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [142] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [143] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [143] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [144] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [144] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [145] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [145] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [146] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [146] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [147] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [147] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [148] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [148] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [149] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [149] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [150] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [150] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [151] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [151] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [152] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [152] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [153] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [153] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [154] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [154] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [155] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [155] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [156] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [156] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [157] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [157] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [158] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [158] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [159] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [159] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [160] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [160] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [161] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [161] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [162] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [162] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [163] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [163] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [164] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [164] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [165] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [165] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [166] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [166] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [167] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [167] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [168] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [168] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [169] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [169] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [170] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [170] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [171] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [171] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [172] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [172] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [173] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [173] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [174] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [174] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [175] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [175] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [176] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [176] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [177] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [177] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [178] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [178] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [179] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [179] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [180] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [180] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [181] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [181] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [182] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [182] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [183] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [183] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [184] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [184] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [185] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [185] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [186] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [186] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [187] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [187] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [188] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [188] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [189] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [189] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [190] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [190] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [191] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [191] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [192] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [192] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [193] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [193] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [194] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [194] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [195] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [195] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [196] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [196] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [197] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [197] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [198] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [198] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [199] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [199] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [200] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [200] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [201] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [201] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [202] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [202] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [203] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [203] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [204] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [204] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [205] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [205] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [206] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [206] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [207] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [207] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [208] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [208] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [209] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [209] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [210] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [210] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [211] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [211] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [212] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [212] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [213] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [213] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [214] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [214] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [215] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [215] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [216] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [216] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [217] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [217] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [218] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [218] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [219] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [219] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [220] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [220] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [221] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [221] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [222] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [222] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [223] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [223] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [224] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [224] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [225] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [225] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [226] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [226] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [227] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [227] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [228] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [228] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [229] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [229] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [230] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [230] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [231] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [231] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [232] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [232] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [233] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [233] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [234] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [234] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [235] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [235] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [236] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [236] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [237] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [237] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [238] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [238] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [239] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [239] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [240] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [240] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [241] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [241] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [242] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [242] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [243] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [243] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [244] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [244] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [245] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [245] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [246] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [246] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [247] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [247] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [248] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [248] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [249] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [249] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [250] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [250] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [251] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [251] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [252] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [252] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [253] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [253] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [254] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [254] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.owner_seed [255] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.owner_seed [255] "logic otp_keymgr_key_o.owner_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed_valid "logic otp_keymgr_key_o.creator_seed_valid" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed_valid "logic otp_keymgr_key_o.creator_seed_valid" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [0] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [0] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [1] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [1] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [2] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [2] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [3] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [3] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [4] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [4] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [5] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [5] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [6] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [6] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [7] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [7] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [8] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [8] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [9] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [9] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [10] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [10] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [11] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [11] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [12] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [12] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [13] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [13] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [14] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [14] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [15] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [15] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [16] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [16] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [17] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [17] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [18] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [18] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [19] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [19] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [20] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [20] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [21] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [21] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [22] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [22] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [23] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [23] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [24] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [24] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [25] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [25] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [26] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [26] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [27] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [27] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [28] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [28] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [29] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [29] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [30] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [30] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [31] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [31] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [32] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [32] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [33] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [33] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [34] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [34] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [35] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [35] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [36] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [36] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [37] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [37] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [38] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [38] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [39] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [39] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [40] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [40] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [41] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [41] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [42] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [42] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [43] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [43] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [44] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [44] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [45] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [45] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [46] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [46] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [47] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [47] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [48] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [48] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [49] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [49] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [50] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [50] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [51] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [51] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [52] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [52] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [53] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [53] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [54] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [54] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [55] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [55] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [56] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [56] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [57] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [57] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [58] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [58] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [59] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [59] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [60] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [60] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [61] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [61] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [62] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [62] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [63] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [63] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [64] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [64] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [65] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [65] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [66] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [66] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [67] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [67] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [68] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [68] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [69] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [69] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [70] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [70] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [71] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [71] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [72] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [72] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [73] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [73] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [74] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [74] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [75] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [75] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [76] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [76] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [77] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [77] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [78] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [78] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [79] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [79] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [80] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [80] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [81] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [81] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [82] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [82] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [83] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [83] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [84] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [84] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [85] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [85] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [86] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [86] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [87] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [87] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [88] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [88] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [89] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [89] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [90] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [90] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [91] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [91] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [92] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [92] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [93] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [93] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [94] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [94] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [95] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [95] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [96] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [96] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [97] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [97] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [98] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [98] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [99] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [99] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [100] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [100] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [101] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [101] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [102] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [102] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [103] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [103] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [104] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [104] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [105] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [105] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [106] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [106] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [107] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [107] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [108] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [108] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [109] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [109] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [110] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [110] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [111] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [111] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [112] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [112] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [113] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [113] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [114] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [114] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [115] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [115] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [116] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [116] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [117] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [117] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [118] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [118] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [119] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [119] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [120] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [120] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [121] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [121] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [122] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [122] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [123] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [123] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [124] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [124] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [125] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [125] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [126] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [126] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [127] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [127] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [128] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [128] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [129] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [129] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [130] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [130] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [131] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [131] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [132] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [132] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [133] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [133] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [134] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [134] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [135] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [135] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [136] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [136] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [137] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [137] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [138] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [138] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [139] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [139] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [140] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [140] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [141] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [141] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [142] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [142] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [143] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [143] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [144] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [144] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [145] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [145] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [146] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [146] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [147] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [147] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [148] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [148] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [149] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [149] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [150] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [150] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [151] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [151] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [152] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [152] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [153] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [153] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [154] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [154] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [155] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [155] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [156] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [156] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [157] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [157] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [158] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [158] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [159] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [159] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [160] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [160] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [161] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [161] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [162] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [162] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [163] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [163] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [164] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [164] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [165] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [165] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [166] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [166] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [167] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [167] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [168] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [168] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [169] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [169] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [170] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [170] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [171] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [171] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [172] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [172] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [173] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [173] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [174] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [174] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [175] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [175] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [176] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [176] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [177] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [177] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [178] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [178] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [179] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [179] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [180] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [180] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [181] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [181] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [182] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [182] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [183] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [183] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [184] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [184] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [185] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [185] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [186] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [186] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [187] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [187] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [188] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [188] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [189] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [189] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [190] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [190] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [191] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [191] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [192] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [192] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [193] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [193] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [194] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [194] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [195] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [195] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [196] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [196] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [197] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [197] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [198] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [198] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [199] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [199] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [200] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [200] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [201] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [201] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [202] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [202] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [203] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [203] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [204] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [204] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [205] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [205] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [206] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [206] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [207] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [207] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [208] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [208] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [209] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [209] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [210] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [210] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [211] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [211] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [212] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [212] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [213] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [213] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [214] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [214] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [215] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [215] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [216] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [216] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [217] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [217] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [218] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [218] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [219] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [219] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [220] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [220] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [221] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [221] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [222] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [222] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [223] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [223] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [224] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [224] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [225] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [225] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [226] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [226] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [227] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [227] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [228] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [228] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [229] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [229] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [230] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [230] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [231] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [231] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [232] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [232] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [233] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [233] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [234] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [234] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [235] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [235] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [236] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [236] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [237] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [237] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [238] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [238] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [239] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [239] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [240] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [240] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [241] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [241] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [242] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [242] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [243] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [243] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [244] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [244] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [245] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [245] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [246] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [246] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [247] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [247] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [248] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [248] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [249] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [249] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [250] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [250] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [251] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [251] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [252] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [252] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [253] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [253] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [254] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [254] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 otp_keymgr_key_o.creator_seed [255] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 otp_keymgr_key_o.creator_seed [255] "logic otp_keymgr_key_o.creator_seed[255:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [0] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [0] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [1] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [1] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [2] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [2] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [3] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [3] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [4] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [4] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [5] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [5] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [6] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [6] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 cio_test_o [7] "logic cio_test_o[7:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 cio_test_o [7] "logic cio_test_o[7:0]" +CHECKSUM: "3665351474 2582220255" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrSt "3204" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrSt "3418" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3665351474 2582220255" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrSt "3204" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrSt "3418" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigSt->IntegDigFinSt "1890->1765" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3665351474 2582220255" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3665351474 2582220255" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3665351474 2582220255" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition CnstyReadWaitSt->CnstyReadSt "2684->107" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition InitWaitSt->InitSt "945->3367" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IdleSt "2625->1357" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IntegDigClrSt->IntegDigSt "2625->1890" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3665351474 2582220255" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrSt "3204" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State InitDescrWaitSt "2472" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigFinSt "1765" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigPadSt "855" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigSt "1890" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegDigWaitSt "2290" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrSt "3418" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +State IntegScrWaitSt "2207" +Fsm state_q "441128463" +ANNOTATION: "VC_COV_UNR" +Transition IdleSt->IntegDigClrSt "1357->2625" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->MacroEccCorrError "6->2" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +Fsm error_q "2410907799" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "3162909804 3458814989" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +Fsm state_q "4141872371" +ANNOTATION: "VC_COV_UNR" +Transition ResetSt->IdleSt "694->745" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +State MacroEccCorrError "2" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->AccessError "6->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition CheckFailError->FsmStateError "6->7" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "2210720134" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->CheckFailError "7->6" +CHECKSUM: "903559179 4258846959" +INSTANCE: tb.dut.u_otp_ctrl_dai +Fsm error_q "1085514286" +ANNOTATION: "VC_COV_UNR" +Transition AccessError->MacroEccCorrError "5->2" +Fsm error_q "1085514286" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->AccessError "7->5" +Fsm error_q "1085514286" +ANNOTATION: "VC_COV_UNR" +Transition FsmStateError->MacroEccCorrError "7->2" +CHECKSUM: "1158524476 2379312231" +INSTANCE: tb.dut.u_otp_ctrl_kdi +Fsm state_q "2979668442" +ANNOTATION: "VC_COV_UNR" +Transition DigWaitSt->DigLoadSt "913->183" +CHECKSUM: "165375753 2072593586" +INSTANCE: tb.dut.u_otp_ctrl_lfsr_timer +ANNOTATION: "VC_COV_UNR" +Condition 15 "1557524712" "(edn_req_o & edn_ack_i) 1 -1" (1 "01") +CHECKSUM: "3436844037 2360113432" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Condition 1 "83486244" "(tlul_part_sel_oh != '0) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 2 "1218027842" "(((|part_tlul_gnt)) | tlul_oob_err_q) 1 -1" (2 "01") +ANNOTATION: "VC_COV_UNR" +Condition 3 "3291433605" "(((|part_tlul_rvalid)) | tlul_oob_err_q) 1 -1" (2 "01") +ANNOTATION: "VC_COV_UNR" +Condition 4 "3779635843" "(fatal_bus_integ_error_q | ((|intg_error))) 1 -1" (3 "10") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1876397257" "(part_error[k] == MacroError) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 10 "2334459673" "(otp_rvalid & otp_fifo_valid) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 13 "1319238213" "(reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe) 1 -1" (2 "001") +ANNOTATION: "VC_COV_UNR" +Condition 13 "1319238213" "(reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe) 1 -1" (3 "010") +ANNOTATION: "VC_COV_UNR" +Condition 13 "1319238213" "(reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe) 1 -1" (4 "100") +ANNOTATION: "vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR" +Condition 42 "1479216946" "(({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[10].PartEnd)) 1 -1" (2 "10") +CHECKSUM: "1746381268 1271541636" +INSTANCE: tb.dut.u_reg_core.u_socket +ANNOTATION: "VC_COV_UNR" +Condition 3 "118253128" "(tl_t_o.a_valid & tl_t_i.a_ready) 1 -1" (1 "01") +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_reg_core.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_otp.u_reg_top.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field3 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field4 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field5 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field6 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field7 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field8 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field2 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field4 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field5 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field2 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3274445021" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field3 +ANNOTATION: "VC_COV_UNR" +Condition 1 "2397158838" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3858770513" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field3 +ANNOTATION: "VC_COV_UNR" +Condition 1 "1301967206" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3858770513" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field1 +ANNOTATION: "VC_COV_UNR" +Condition 1 "1301967206" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "4255502330 3201188367" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field0 +ANNOTATION: "VC_COV_UNR" +Condition 1 "1807203824" "(wr_en ? wr_data : qs) 1 -1" (2 "1") +CHECKSUM: "2099741489 1445279304" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field0.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "2099741489 1445279304" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field1.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "2099741489 3636044484" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field2.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "2306794614" "((de ? d : q) & (we ? ((~wd)) : '1)) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 2 "2306794614" "((de ? d : q) & (we ? ((~wd)) : '1)) 1 -1" (3 "11") +ANNOTATION: "VC_COV_UNR" +Condition 3 "2289961458" "(de ? d : q) 1 -1" (2 "1") +CHECKSUM: "2099741489 1283100255" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field6.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "2099741489 1077956591" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field0.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "2099741489 4164822555" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field1.wr_en_data_arb +ANNOTATION: "VC_COV_UNR" +Condition 1 "505266581" "(we | de) 1 -1" (2 "01") +CHECKSUM: "662936270 2081652359" +INSTANCE: tb.dut.u_tlul_adapter_sram +ANNOTATION: "VC_COV_UNR" +Condition 2 "3455933711" "(reqfifo_rdata.op == OpRead) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 8 "3066913128" "(intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q) 1 -1" (2 "00001") +ANNOTATION: "VC_COV_UNR" +Condition 17 "3469950311" "(wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error) 1 -1" (7 "100000") +ANNOTATION: "VC_COV_UNR" +Condition 20 "709191362" "(req_o & gnt_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 21 "3623514242" "(d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead)) 1 -1" (1 "0111") +ANNOTATION: "VC_COV_UNR" +Condition 21 "3623514242" "(d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead)) 1 -1" (2 "1011") +ANNOTATION: "VC_COV_UNR" +Condition 21 "3623514242" "(d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead)) 1 -1" (4 "1110") +ANNOTATION: "VC_COV_UNR" +Condition 25 "2807788926" "((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 26 "561780173" "(vld_rd_rsp && reqfifo_rdata.error) 1 -1" (3 "11") +ANNOTATION: "VC_COV_UNR" +Condition 34 "201396280" "(d_valid && d_error) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 35 "3680494467" "((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready) 1 -1" (3 "1101") +ANNOTATION: "VC_COV_UNR" +Condition 37 "2164803938" "(tl_i_int.a_valid & reqfifo_wready & ((~error_internal))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 42 "2041272341" "(sram_ack & ((~we_o))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 43 "721931741" "(rvalid_i & reqfifo_rvalid) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:i=0:vcs_gen_end:VC_COV_UNR" +Condition 48 "3548937587" "(((|wmask_intg)) & ((|wdata_intg))) 1 -1" (1 "01") +CHECKSUM: "2974379282 2951929728" +INSTANCE: tb.dut.u_part_sel_idx +ANNOTATION: "vcs_gen_start:level=0,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 1 "2750612666" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]) 1 -1" (1 "00") +CHECKSUM: "2974379282 2951929728" +INSTANCE: tb.dut.u_otp_ctrl_dai.u_part_sel_idx +ANNOTATION: "vcs_gen_start:level=0,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 1 "2750612666" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1]) 1 -1" (1 "00") +CHECKSUM: "2032872600 2493710885" +INSTANCE: tb.dut.u_edn_arb +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 10 "635964333" "(req_i[0] & gen_normal_case.prio_mask_q[0]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 11 "2124571033" "(req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ready_i) 1 -1" (1 "011") +CHECKSUM: "2032872600 3068670743" +INSTANCE: tb.dut.u_otp_arb +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 118 "3667925887" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 119 "2125455247" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 119 "2125455247" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 120 "2371949082" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 121 "4111290463" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 124 "2230658126" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 125 "1884579875" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 137 "1731868698" "(req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 142 "1060032545" "(req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 147 "1299459822" "(req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 152 "358663893" "(req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 157 "2252512415" "(req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 162 "3730207908" "(req_i[5] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 167 "2886503019" "(req_i[6] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[6].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=7:vcs_gen_end:VC_COV_UNR" +Condition 172 "4095238736" "(req_i[7] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[7].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=8:vcs_gen_end:VC_COV_UNR" +Condition 177 "296455364" "(req_i[8] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[8].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=9:vcs_gen_end:VC_COV_UNR" +Condition 182 "1237279999" "(req_i[9] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[9].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 187 "565898016" "(req_i[10] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=11:vcs_gen_end:VC_COV_UNR" +Condition 192 "2218826282" "(req_i[11] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[11].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 197 "4217824807" "(req_i[12] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 201 "1343278836" "(req_i[13] & gen_normal_case.prio_mask_q[13]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 201 "1343278836" "(req_i[13] & gen_normal_case.prio_mask_q[13]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 202 "1587320621" "(req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 202 "1587320621" "(req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i) 1 -1" (2 "101") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 202 "1587320621" "(req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 202 "1587320621" "(req_i[13] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ready_i) 1 -1" (4 "111") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 204 "3359315662" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 204 "3359315662" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 205 "87484194" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 205 "87484194" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i))) 1 -1" (3 "11") +CHECKSUM: "2032872600 835765284" +INSTANCE: tb.dut.u_scrmbl_mtx +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 10 "1993460578" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 10 "1993460578" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 11 "1567077924" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 12 "3158492049" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[1].gen_level[0].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 13 "96040801" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[1].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 14 "1193252123" "(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[1].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 15 "445016888" "(gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[1].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 16 "1314162940" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 16 "1314162940" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 17 "2175331913" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] & gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 18 "2134997267" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[1].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[1].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 28 "2070917326" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 28 "2070917326" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 29 "3264610632" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 29 "3264610632" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 30 "1496330476" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 30 "1496330476" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[2].gen_level[0].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 31 "475390859" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 31 "475390859" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 32 "3851361741" "(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 33 "834897871" "(gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 34 "827710109" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 34 "827710109" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 34 "827710109" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 35 "1296065718" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 35 "1296065718" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] & gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 36 "2587069038" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=2,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 45 "1389557192" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[2].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[2].gen_level[1].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 64 "210767427" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 64 "210767427" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 65 "433071849" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 65 "433071849" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 66 "676485814" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 66 "676485814" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[0].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 67 "2859603461" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 67 "2859603461" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 68 "499725081" "(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 69 "2136469291" "(gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 70 "3457930055" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 70 "3457930055" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 70 "3457930055" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 71 "1202012" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 71 "1202012" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 72 "3948011572" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 73 "2058222911" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 73 "2058222911" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 74 "3215638766" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 74 "3215638766" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 75 "3769836816" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 75 "3769836816" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[1].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 76 "2034837615" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 76 "2034837615" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 77 "2239186227" "(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 78 "2004432906" "(gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 79 "1357880086" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 79 "1357880086" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel))) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 79 "1357880086" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 80 "3927989974" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 80 "3927989974" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 81 "598777746" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 81 "598777746" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 82 "3219580251" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 82 "3219580251" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 83 "26276459" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 84 "1842145640" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[2].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 85 "147158886" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 86 "2038251222" "(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 87 "1520563742" "(gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 88 "2599996672" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 88 "2599996672" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 89 "193340754" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 90 "2932823018" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 90 "2932823018" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].C0]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 109 "535495451" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 109 "535495451" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 110 "3231051018" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 111 "2023010" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[5].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 112 "2223050582" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[5].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 113 "1661998521" "(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[5].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 114 "328876404" "(gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[5].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 115 "1323463256" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 115 "1323463256" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 116 "2448561063" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 117 "3273483488" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 118 "3667925887" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])) 1 -1" (1 "00") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 118 "3667925887" "(((~gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) | (((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1])) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 119 "2125455247" "(((~gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0])) & gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 120 "2371949082" "(gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[3].gen_level[6].C1]) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 121 "4111290463" "(gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] | gen_normal_case.prio_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 122 "2669309532" "(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 123 "1044549472" "(gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (1 "0") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 124 "2230658126" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel))) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 124 "2230658126" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ((~gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 125 "1884579875" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 126 "1315088536" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] | gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].C0]) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 136 "2430171309" "(req_i[0] & gen_normal_case.prio_mask_q[0]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 136 "2430171309" "(req_i[0] & gen_normal_case.prio_mask_q[0]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 136 "2430171309" "(req_i[0] & gen_normal_case.prio_mask_q[0]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 137 "1731868698" "(req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 139 "4029129651" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 140 "2870412309" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[0].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 141 "2424159075" "(req_i[1] & gen_normal_case.prio_mask_q[1]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 141 "2424159075" "(req_i[1] & gen_normal_case.prio_mask_q[1]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 141 "2424159075" "(req_i[1] & gen_normal_case.prio_mask_q[1]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 142 "1060032545" "(req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 144 "2044991706" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 144 "2044991706" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 145 "3094700199" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[1].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 146 "2442198833" "(req_i[2] & gen_normal_case.prio_mask_q[2]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 146 "2442198833" "(req_i[2] & gen_normal_case.prio_mask_q[2]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 146 "2442198833" "(req_i[2] & gen_normal_case.prio_mask_q[2]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 147 "1299459822" "(req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 149 "303405805" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 149 "303405805" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 150 "3088640414" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[2].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 151 "2436119807" "(req_i[3] & gen_normal_case.prio_mask_q[3]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 151 "2436119807" "(req_i[3] & gen_normal_case.prio_mask_q[3]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 151 "2436119807" "(req_i[3] & gen_normal_case.prio_mask_q[3]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 152 "358663893" "(req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 154 "2614501764" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 154 "2614501764" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 155 "2876935468" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[3].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 156 "1150101804" "(req_i[4] & gen_normal_case.prio_mask_q[4]) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 156 "1150101804" "(req_i[4] & gen_normal_case.prio_mask_q[4]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 156 "1150101804" "(req_i[4] & gen_normal_case.prio_mask_q[4]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 157 "2252512415" "(req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 159 "2077403342" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 159 "2077403342" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 160 "362208751" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[4].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 164 "4061205415" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[5].Pa] & ((~ready_i)))) 1 -1" (3 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 186 "1702269588" "(req_i[10] & gen_normal_case.prio_mask_q[10]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 186 "1702269588" "(req_i[10] & gen_normal_case.prio_mask_q[10]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 187 "565898016" "(req_i[10] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 189 "2771416427" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=10:vcs_gen_end:VC_COV_UNR" +Condition 190 "2876058957" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[10].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 196 "3119114945" "(req_i[12] & gen_normal_case.prio_mask_q[12]) 1 -1" (2 "10") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 196 "3119114945" "(req_i[12] & gen_normal_case.prio_mask_q[12]) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 197 "4217824807" "(req_i[12] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ready_i) 1 -1" (3 "110") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 199 "2102103111" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i)))) 1 -1" (2 "01") +ANNOTATION: "vcs_gen_start:level=4,offset=12:vcs_gen_end:VC_COV_UNR" +Condition 200 "3779810229" "(gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[12].Pa] & ((~ready_i))) 1 -1" (3 "11") +ANNOTATION: "vcs_gen_start:level=4,offset=13:vcs_gen_end:VC_COV_UNR" +Condition 204 "3359315662" "(gen_normal_case.mask_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] | (gen_normal_case.sel_tree[gen_normal_case.gen_tree[4].gen_level[13].Pa] & ((~ready_i)))) 1 -1" (1 "00") +CHECKSUM: "2032872600 3109464092" +INSTANCE: tb.dut.u_otp_ctrl_kdi.u_req_arb +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Condition 65 "2951635521" "(req_i[0] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[0].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Condition 70 "4160391802" "(req_i[1] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[1].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Condition 75 "2241885365" "(req_i[2] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[2].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=3:vcs_gen_end:VC_COV_UNR" +Condition 80 "3719601294" "(req_i[3] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[3].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=4:vcs_gen_end:VC_COV_UNR" +Condition 85 "1318504132" "(req_i[4] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[4].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Condition 90 "377630463" "(req_i[5] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[5].Pa] & ready_i) 1 -1" (1 "011") +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Condition 95 "1691930672" "(req_i[6] & gen_normal_case.sel_tree[gen_normal_case.gen_tree[3].gen_level[6].Pa] & ready_i) 1 -1" (1 "011") +CHECKSUM: "3655552781 2309055648" +INSTANCE: tb.dut.u_prim_edn_req.u_prim_packer_fifo +ANNOTATION: "VC_COV_UNR" +Condition 12 "2853235687" "((depth_q == FullDepth) && ((!clr_q))) 1 -1" (2 "10") +CHECKSUM: "4224194069 639524789" +INSTANCE: tb.dut.u_tlul_lc_gate +ANNOTATION: "VC_COV_UNR" +Condition 1 "1380914983" "(a_ack && ((!d_ack))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 2 "2824798557" "(d_ack && ((!a_ack))) 1 -1" (2 "10") +CHECKSUM: "903559179 1044941866" +INSTANCE: tb.dut.u_otp_ctrl_dai +ANNOTATION: "VC_COV_UNR" +Condition 6 "3686409107" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 8 "4163455672" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 9 "1539831361" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "vcs_gen_start:k=10:vcs_gen_end:VC_COV_UNR" +Condition 33 "138415549" "((dai_addr_i >= 11'b11110101000) & ({1'b0, dai_addr_i} < gen_part_sel[10].PartEndInt[otp_ctrl_reg_pkg::OtpByteAddrWidth:0])) 1 -1" (2 "10") +CHECKSUM: "1158524476 2909360515" +INSTANCE: tb.dut.u_otp_ctrl_kdi +ANNOTATION: "VC_COV_UNR" +Condition 2 "1539831361" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +CHECKSUM: "3162909804 4223786199" +INSTANCE: tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 14 "2502713177" "(({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) 1 -1" (2 "10") +CHECKSUM: "3162909804 475089886" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 1 "1099175909" "(otp_err != NoError) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 2 "2883220586" "(otp_err != NoError) 1 -1" (2 "1") +CHECKSUM: "3162909804 1722272287" +INSTANCE: tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 14 "478960819" "(({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) 1 -1" (2 "10") +CHECKSUM: "3162909804 1775057944" +INSTANCE: tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 14 "673734063" "(({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) 1 -1" (2 "10") +CHECKSUM: "3162909804 4078376581" +INSTANCE: tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Condition 4 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 4 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 14 "677249997" "(({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) 1 -1" (2 "10") +CHECKSUM: "3665351474 720525075" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (3 "11") +ANNOTATION: "VC_COV_UNR" +Condition 10 "4291765346" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "3665351474 384791011" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 9 "1580211052" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "3665351474 599055118" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (3 "11") +ANNOTATION: "VC_COV_UNR" +Condition 10 "4291765346" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "3665351474 698462587" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 9 "1580211052" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "3665351474 2302263073" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 18 "624370688" "((base_sel == DigOffset) ? DigestOffset : 11'b11110101000) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 19 "4038180897" "(base_sel == DigOffset) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 20 "705391888" "((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 21 "1499701630" "(data_sel == ScrmblData) 1 -1" (2 "1") +CHECKSUM: "3665351474 691864715" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Condition 3 "1999344180" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 9 "1580211052" "(scrmbl_mtx_gnt_i && scrmbl_ready_i) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 16 "3809681040" "(state_q != ErrorSt) 1 -1" (2 "1") +CHECKSUM: "7115036 2825631531" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sramreqfifo +ANNOTATION: "VC_COV_UNR" +Condition 2 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 3 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 4 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 4 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +CHECKSUM: "7115036 2432857915" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_rspfifo +ANNOTATION: "VC_COV_UNR" +Condition 2 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 3 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 4 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 4 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 6 "4208363759" "(gen_normal_fifo.fifo_empty && wvalid_i) 1 -1" (1 "01") +CHECKSUM: "7115036 3923796707" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_reqfifo +ANNOTATION: "VC_COV_UNR" +Condition 2 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 3 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 4 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 4 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +CHECKSUM: "7115036 2279662283" +INSTANCE: tb.dut.u_otp_rsp_fifo +ANNOTATION: "VC_COV_UNR" +Condition 1 "2400173860" "(((~full_o)) & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "01") +ANNOTATION: "VC_COV_UNR" +Condition 2 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "101") +ANNOTATION: "VC_COV_UNR" +Condition 3 "786039886" "(wvalid_i & wready_o & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +ANNOTATION: "VC_COV_UNR" +Condition 4 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (1 "011") +ANNOTATION: "VC_COV_UNR" +Condition 4 "1324655787" "(rvalid_o & rready_i & ((~gen_normal_fifo.under_rst))) 1 -1" (3 "110") +CHECKSUM: "3215070453 33318353" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Condition 1 "2532211833" "(incr_wptr_i & (wptr_o == 1'((Depth - 1)))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "2597027294" "(incr_rptr_i & (rptr_o == 1'((Depth - 1)))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 8 "1599734576" "((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 9 "446195871" "(wptr_wrap_msb == rptr_wrap_msb) 1 -1" (1 "0") +CHECKSUM: "3215070453 33318353" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Condition 1 "2532211833" "(incr_wptr_i & (wptr_o == 1'((Depth - 1)))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "2597027294" "(incr_rptr_i & (rptr_o == 1'((Depth - 1)))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 8 "1599734576" "((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 9 "446195871" "(wptr_wrap_msb == rptr_wrap_msb) 1 -1" (1 "0") +CHECKSUM: "3215070453 33318353" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Condition 1 "2532211833" "(incr_wptr_i & (wptr_o == 1'((Depth - 1)))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 3 "2597027294" "(incr_rptr_i & (rptr_o == 1'((Depth - 1)))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 8 "1599734576" "((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))) 1 -1" (1 "0") +ANNOTATION: "VC_COV_UNR" +Condition 9 "446195871" "(wptr_wrap_msb == rptr_wrap_msb) 1 -1" (1 "0") +CHECKSUM: "3215070453 563859410" +INSTANCE: tb.dut.u_otp_rsp_fifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Condition 5 "3619927060" "(wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}})) 1 -1" (2 "1") +ANNOTATION: "VC_COV_UNR" +Condition 7 "4040012966" "(full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))) 1 -1" (2 "1") +CHECKSUM: "3171246264 3336016746" +INSTANCE: tb.dut.u_otp +ANNOTATION: "VC_COV_UNR" +Branch 3 "1554177250" "state_q" (1) "state_q ResetSt ,1,0,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1554177250" "state_q" (8) "state_q IdleSt ,-,-,1,default,-,-,-,-,-,-,-,-" +CHECKSUM: "3436844037 1401458059" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Branch 4 "1264131593" "tlul_req" (1) "tlul_req 1,0" +CHECKSUM: "1746381268 3161287359" +INSTANCE: tb.dut.u_reg_core.u_socket +ANNOTATION: "VC_COV_UNR" +Branch 4 "3202860295" "(!rst_ni)" (2) "(!rst_ni) 0,1,0,-" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field3 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field4 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field5 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field6 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field7 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr3_field8 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field2 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field3 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field4 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr5_field5 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field0 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field1 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field2 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "4255502330 3554514034" +INSTANCE: tb.dut.u_otp.u_reg_top.u_csr7_field3 +ANNOTATION: "VC_COV_UNR" +Branch 0 "3759852512" "wr_en" (0) "wr_en 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "1017474648" "(!rst_ni)" (1) "(!rst_ni) 0,1" +CHECKSUM: "662936270 1924774061" +INSTANCE: tb.dut.u_tlul_adapter_sram +ANNOTATION: "VC_COV_UNR" +Branch 2 "1058271942" "(vld_rd_rsp && reqfifo_rdata.error)" (0) "(vld_rd_rsp && reqfifo_rdata.error) 1,-" +ANNOTATION: "VC_COV_UNR" +Branch 6 "744749108" "reqfifo_rvalid" (2) "reqfifo_rvalid 1,0,0" +CHECKSUM: "2032872600 3832429488" +INSTANCE: tb.dut.u_scrmbl_mtx +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 2 "1747167515" "gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=1,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 3 "1747167515" "gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[1].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 6 "3123337246" "gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=2,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 7 "3123337246" "gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[2].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 14 "840384514" "gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=0:vcs_gen_end:VC_COV_UNR" +Branch 15 "840384514" "gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[0].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Branch 16 "2813219087" "gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=1:vcs_gen_end:VC_COV_UNR" +Branch 17 "2813219087" "gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[1].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Branch 18 "2452890474" "gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=2:vcs_gen_end:VC_COV_UNR" +Branch 19 "2452890474" "gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[2].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Branch 24 "3811150440" "gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=5:vcs_gen_end:VC_COV_UNR" +Branch 25 "3811150440" "gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[5].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Branch 26 "3602118669" "gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel 0" +ANNOTATION: "vcs_gen_start:level=3,offset=6:vcs_gen_end:VC_COV_UNR" +Branch 27 "3602118669" "gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel" (1) "gen_normal_case.gen_tree[3].gen_level[6].gen_nodes.sel 0" +CHECKSUM: "4224194069 3219254590" +INSTANCE: tb.dut.u_tlul_lc_gate +ANNOTATION: "VC_COV_UNR" +Branch 2 "1850090820" "state_q" (8) "state_q StFlush ,-,-,-,0,0,-,-" +CHECKSUM: "3882079776 3692779052" +INSTANCE: tb.dut.u_otp_ctrl_scrmbl +ANNOTATION: "VC_COV_UNR" +Branch 5 "2137472258" "state_q" (8) "state_q IdleSt ,1,default,-,-,-,-,-" +CHECKSUM: "903559179 3978479804" +INSTANCE: tb.dut.u_otp_ctrl_dai +ANNOTATION: "VC_COV_UNR" +Branch 2 "2060689171" "state_q" (1) "state_q ResetSt ,1,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +CHECKSUM: "1158524476 2213598664" +INSTANCE: tb.dut.u_otp_ctrl_kdi +ANNOTATION: "VC_COV_UNR" +Branch 4 "853326673" "state_q" (20) "state_q DigWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,1,-,-,-" +CHECKSUM: "3162909804 3977884699" +INSTANCE: tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Branch 5 "490981166" "state_q" (4) "state_q InitSt ,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "490981166" "state_q" (5) "state_q InitWaitSt ,-,-,-,1,1,1,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "490981166" "state_q" (14) "state_q ReadWaitSt ,-,-,-,-,-,-,-,-,-,1,1,1,-,-,-" +CHECKSUM: "3162909804 1847756134" +INSTANCE: tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3665351474 3964686460" +INSTANCE: tb.dut.gen_partitions[7].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (35) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (43) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (47) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,-,0,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (49) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3665351474 3964686460" +INSTANCE: tb.dut.gen_partitions[8].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (35) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (43) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (47) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,-,0,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (49) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3665351474 3964686460" +INSTANCE: tb.dut.gen_partitions[9].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (35) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (43) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (47) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,-,0,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (49) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "3673468110" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 6 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3665351474 2334161493" +INSTANCE: tb.dut.gen_partitions[5].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (11) "state_q InitDescrSt ,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (12) "state_q InitDescrSt ,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (13) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (14) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (33) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (38) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (39) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (40) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (41) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (43) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (49) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 5 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3665351474 2334161493" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (11) "state_q InitDescrSt ,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (12) "state_q InitDescrSt ,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (13) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (14) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (20) "state_q CnstyReadSt ,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (33) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (38) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (39) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (40) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (41) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (42) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,1,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "344890278" "state_q" (45) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 5 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 5 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3665351474 2810977924" +INSTANCE: tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf +ANNOTATION: "VC_COV_UNR" +Branch 0 "2541341865" "(base_sel == DigOffset)" (0) "(base_sel == DigOffset) 1" +ANNOTATION: "VC_COV_UNR" +Branch 1 "341865418" "(data_sel == ScrmblData)" (0) "(data_sel == ScrmblData) 1" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (12) "state_q InitDescrSt ,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (14) "state_q InitDescrWaitSt ,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (33) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,1,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (35) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (37) "state_q IntegDigClrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (39) "state_q IntegScrSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (41) "state_q IntegScrWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (45) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,0,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (47) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,1,0,-,-,0,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (48) "state_q IntegDigSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (50) "state_q IntegDigPadSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (52) "state_q IntegDigFinSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 3 "1949926999" "state_q" (56) "state_q IntegDigWaitSt ,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,0,-,-,-" +ANNOTATION: "VC_COV_UNR" +Branch 4 "375157548" "ecc_err" (0) "ecc_err 1,1" +ANNOTATION: "VC_COV_UNR" +Branch 4 "375157548" "ecc_err" (1) "ecc_err 1,0" +CHECKSUM: "3818998033 3877782530" +INSTANCE: tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg +ANNOTATION: "VC_COV_UNR" +Branch 1 "2154824802" "(32'(addr_i) < Depth)" (2) "(32'(addr_i) < Depth) 0,-" +CHECKSUM: "3215070453 1827096802" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Branch 0 "721764659" "full_o" (2) "full_o 0,0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "2417346495" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +ANNOTATION: "VC_COV_UNR" +Branch 2 "456961687" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +CHECKSUM: "3215070453 1827096802" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Branch 0 "721764659" "full_o" (2) "full_o 0,0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "2417346495" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +ANNOTATION: "VC_COV_UNR" +Branch 2 "456961687" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +CHECKSUM: "3215070453 1827096802" +INSTANCE: tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Branch 0 "721764659" "full_o" (2) "full_o 0,0" +ANNOTATION: "VC_COV_UNR" +Branch 1 "2417346495" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +ANNOTATION: "VC_COV_UNR" +Branch 2 "456961687" "(!rst_ni)" (3) "(!rst_ni) 0,0,0,1" +CHECKSUM: "3215070453 1827096802" +INSTANCE: tb.dut.u_otp_rsp_fifo.gen_normal_fifo.u_fifo_cnt +ANNOTATION: "VC_COV_UNR" +Branch 0 "721764659" "full_o" (0) "full_o 1,-" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cover.cfg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cover.cfg new file mode 100644 index 00000000000..d69a1932762 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/cov/otp_ctrl_cover.cfg @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + +// The modules below are preverified in FPV testbench. +// There are many conditional coverage and hard to them all. +-moduletree prim_secded_inv_72_64_dec +-moduletree prim_secded_inv_72_64_enc + +begin tgl + +module prim_secded_inv_72_64_dec + +module prim_secded_inv_72_64_enc +end diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/doc/tb.svg b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/doc/tb.svg new file mode 100644 index 00000000000..a910d806170 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_ast_inputs_cfg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_ast_inputs_cfg.sv new file mode 100644 index 00000000000..1178203c3e3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_ast_inputs_cfg.sv @@ -0,0 +1,35 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// +// Configuration values for DUT input signals +// +// +// This class randomizes values for DUT signal inputs +// and sets constraints on these values. +// +// This class will be instantiated inside otp_ctrl_env_cfg object, and will connect +// to it's otp_ctrl_vif signals and drive them each reset event +// +// The constraints can be hardened and softened as needed in +// closed-source environment. +// In order to override these constraints, please inherit this class +// and set a type override in the closed source environment + +class otp_ctrl_ast_inputs_cfg extends uvm_object; + `uvm_object_utils(otp_ctrl_ast_inputs_cfg) + `uvm_object_new + + // Group: Variables + rand otp_macro_pkg::otp_ast_rsp_t otp_ast_pwr_seq_h; + rand otp_macro_pkg::otp_test_ctrl_t otp_vendor_test_ctrl; + rand prim_mubi_pkg::mubi4_t scanmode; + rand logic scan_en, scan_rst_n; + + // Group: Constraints + constraint dut_values_c { + otp_vendor_test_ctrl == 32'h0; + } + +endclass: otp_ctrl_ast_inputs_cfg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.core b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.core new file mode 100644 index 00000000000..5257c3227f9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.core @@ -0,0 +1,64 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:otp_ctrl_env:0.1 +description: "OTP_CTRL DV UVM environment" + +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:dv:mem_bkdr_util + - lowrisc:dv:crypto_dpi_present + - lowrisc:dv:lc_ctrl_dv_utils + - lowrisc:ip:otp_macro_pkg + - lowrisc:dv:otp_macro_env + files: + - otp_scrambler_pkg.sv + - otp_ctrl_env_pkg.sv + - otp_ctrl_if.sv + - otp_ctrl_ast_inputs_cfg.sv: {is_include_file: true} + - otp_ctrl_env_cfg.sv: {is_include_file: true} + - otp_ctrl_env_cov.sv: {is_include_file: true} + - otp_ctrl_virtual_sequencer.sv: {is_include_file: true} + - otp_ctrl_scoreboard.sv: {is_include_file: true} + - otp_ctrl_env.sv: {is_include_file: true} + - seq_lib/otp_ctrl_vseq_list.sv: {is_include_file: true} + - seq_lib/otp_ctrl_callback_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_base_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_common_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_wake_up_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_smoke_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_partition_walk_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_low_freq_read_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_init_fail_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_dai_lock_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_dai_errs_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_macro_errs_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_background_chks_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_check_fail_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_parallel_base_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_regwen_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_parallel_key_req_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_parallel_lc_req_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_parallel_lc_esc_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_test_access_vseq.sv: {is_include_file: true} + - seq_lib/otp_ctrl_stress_all_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: otp_ctrl + ip_hjson: ../../data/otp_ctrl.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv new file mode 100644 index 00000000000..da818238122 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env.sv @@ -0,0 +1,88 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class otp_ctrl_env #( + type CFG_T = otp_ctrl_env_cfg, + type COV_T = otp_ctrl_env_cov, + type VIRTUAL_SEQUENCER_T = otp_ctrl_virtual_sequencer, + type SCOREBOARD_T = otp_ctrl_scoreboard + ) + extends cip_base_env #( + .CFG_T (CFG_T), + .COV_T (COV_T), + .VIRTUAL_SEQUENCER_T(VIRTUAL_SEQUENCER_T), + .SCOREBOARD_T (SCOREBOARD_T) + ); + `uvm_component_param_utils(otp_ctrl_env #(CFG_T, COV_T, VIRTUAL_SEQUENCER_T, SCOREBOARD_T)) + + `uvm_component_new + + push_pull_agent#(.DeviceDataWidth(SRAM_DATA_SIZE)) m_sram_pull_agent[NumSramKeyReqSlots]; + push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent; + push_pull_agent#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) m_lc_prog_pull_agent; + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + // build sram-otp pull agent + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + string sram_agent_name = $sformatf("m_sram_pull_agent[%0d]", i); + m_sram_pull_agent[i] = push_pull_agent#(.DeviceDataWidth(SRAM_DATA_SIZE))::type_id::create( + sram_agent_name, this); + uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(SRAM_DATA_SIZE)))::set(this, + $sformatf("%0s*", sram_agent_name), "cfg", cfg.m_sram_pull_agent_cfg[i]); + end + + // build otbn-otp pull agent + m_otbn_pull_agent = push_pull_agent#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id::create( + "m_otbn_pull_agent", this); + uvm_config_db#(push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set( + this, "m_otbn_pull_agent", "cfg", cfg.m_otbn_pull_agent_cfg); + + // build lc-otp program pull agent + m_lc_prog_pull_agent = push_pull_agent#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1)) + ::type_id::create("m_lc_prog_pull_agent", this); + uvm_config_db#(push_pull_agent_cfg#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1))):: + set(this, "m_lc_prog_pull_agent", "cfg", cfg.m_lc_prog_pull_agent_cfg); + + // config mem virtual interface + if (!uvm_config_db#(mem_bkdr_util)::get(this, "", "mem_bkdr_util", cfg.mem_bkdr_util_h)) begin + `uvm_fatal(`gfn, "failed to get mem_bkdr_util from uvm_config_db") + end + + // config otp_ctrl output data virtual interface + if (!uvm_config_db#(otp_ctrl_vif)::get(this, "", "otp_ctrl_vif", cfg.otp_ctrl_vif)) begin + `uvm_fatal(`gfn, "failed to get otp_ctrl_vif from uvm_config_db") + end + + // Check if `NumPart` constant is assigned to the correct value. + `DV_CHECK(NumPart == (LifeCycleIdx + 1)) + + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + + // connect SRAM sequencer and analysis ports + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + virtual_sequencer.sram_pull_sequencer_h[i] = m_sram_pull_agent[i].sequencer; + if (cfg.en_scb) begin + m_sram_pull_agent[i].monitor.analysis_port.connect( + scoreboard.sram_fifos[i].analysis_export); + end + end + + virtual_sequencer.otbn_pull_sequencer_h = m_otbn_pull_agent.sequencer; + virtual_sequencer.lc_prog_pull_sequencer_h = m_lc_prog_pull_agent.sequencer; + + if (cfg.en_scb) begin + m_otbn_pull_agent.monitor.analysis_port.connect(scoreboard.otbn_fifo.analysis_export); + m_lc_prog_pull_agent.monitor.analysis_port.connect(scoreboard.lc_prog_fifo.analysis_export); + end + + // connect the DUT cfg instance to the handle in the otp_ctrl_vif + this.cfg.otp_ctrl_vif.dut_cfg = this.cfg.dut_cfg; + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv new file mode 100644 index 00000000000..cb4335d2809 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cfg.sv @@ -0,0 +1,98 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`define OTP_CLK_CONSTRAINT(FREQ_) \ + FREQ_ dist { \ + 6 :/ 2, \ + [24:25] :/ 2, \ + [26:47] :/ 1, \ + [48:50] :/ 2, \ + [51:95] :/ 1, \ + 96 :/ 1, \ + [97:99] :/ 1, \ + 100 :/ 1 \ + }; + +class otp_ctrl_env_cfg extends cip_base_env_cfg #(.RAL_T(otp_ctrl_core_reg_block)); + + // ext component cfgs + rand push_pull_agent_cfg#(.DeviceDataWidth(SRAM_DATA_SIZE)) + m_sram_pull_agent_cfg[NumSramKeyReqSlots]; + rand push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE)) m_otbn_pull_agent_cfg; + rand push_pull_agent_cfg#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) + m_lc_prog_pull_agent_cfg; + + // Memory backdoor util instance for OTP. + mem_bkdr_util mem_bkdr_util_h; + + // ext interfaces + otp_ctrl_vif otp_ctrl_vif; + virtual clk_rst_if clk_rst_vif_otp_macro_prim_reg_block; + + bit backdoor_clear_mem; + + // Check ECC errors + otp_ecc_err_e ecc_chk_err [NumPart] = '{default:OtpNoEccErr}; + + // values for otp_ctrl_if signals connected to DUT + rand otp_ctrl_ast_inputs_cfg dut_cfg; + + // Introduce this flag to avoid close source conflict. + bit create_prim_tl_agent = 1; + + `uvm_object_utils_begin(otp_ctrl_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + constraint clk_freq_mhz_c { + `OTP_CLK_CONSTRAINT(clk_freq_mhz) + foreach (clk_freqs_mhz[i]) { + `OTP_CLK_CONSTRAINT(clk_freqs_mhz[i]) + } + } + + virtual function void initialize(bit [31:0] csr_base_addr = '1); + string prim_ral_name = "otp_macro_prim_reg_block"; + ral_model_names.push_back(prim_ral_name); + clk_freqs_mhz[prim_ral_name] = clk_freq_mhz; + + list_of_alerts = otp_ctrl_env_pkg::LIST_OF_ALERTS; + num_edn = 1; + tl_intg_alert_name = "fatal_bus_integ_error"; + sec_cm_alert_name = "fatal_check_error"; + + super.initialize(csr_base_addr); + + // create push_pull agent config obj + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + string cfg_name = $sformatf("sram_pull_agent_cfg[%0d]", i); + m_sram_pull_agent_cfg[i] = push_pull_agent_cfg#(.DeviceDataWidth(SRAM_DATA_SIZE))::type_id + ::create(cfg_name); + m_sram_pull_agent_cfg[i].agent_type = PullAgent; + end + + m_otbn_pull_agent_cfg = push_pull_agent_cfg#(.DeviceDataWidth(OTBN_DATA_SIZE))::type_id + ::create("m_otbn_pull_agent_cfg"); + m_otbn_pull_agent_cfg.agent_type = PullAgent; + + + m_lc_prog_pull_agent_cfg = push_pull_agent_cfg#(.HostDataWidth(LC_PROG_DATA_SIZE), + .DeviceDataWidth(1))::type_id::create("m_lc_prog_pull_agent_cfg"); + m_lc_prog_pull_agent_cfg.agent_type = PullAgent; + + // set num_interrupts & num_alerts + num_interrupts = ral.intr_state.get_n_used_bits(); + + // only support 1 outstanding TL items in tlul_adapter + m_tl_agent_cfg.max_outstanding_req = 1; + m_tl_agent_cfgs["otp_macro_prim_reg_block"].max_outstanding_req = 1; + + // create the inputs cfg instance + dut_cfg = otp_ctrl_ast_inputs_cfg::type_id::create("dut_cfg"); + endfunction + +endclass + +`undef OTP_CLK_CONSTRAINT diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv new file mode 100644 index 00000000000..0e5ba6bf3ca --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_cov.sv @@ -0,0 +1,458 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +/** + * Covergroups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ +class otp_ctrl_unbuf_err_code_cg_wrap; + // Unbuffered partition can use TLUL interface to read out but cannot write, thus error_code does + // not have write_blank_err. + covergroup unbuf_err_code_cg(string name) with function sample(bit [TL_DW-1:0] val); + option.per_instance = 1; + option.name = name; + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins ecc_corr_err = {OtpMacroEccCorrError}; + bins ecc_uncorr_err = {OtpMacroEccUncorrError}; + bins access_err = {OtpAccessError}; + bins check_fail = {OtpCheckFailError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + endgroup + + function new(string name); + unbuf_err_code_cg = new(name); + endfunction +endclass + +class otp_ctrl_buf_err_code_cg_wrap; + // Buffered partition must use DAI interface to access partition, so it does not have access_err + // and write_blank err. + covergroup buf_err_code_cg(string name) with function sample(bit [TL_DW-1:0] val); + option.per_instance = 1; + option.name = name; + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins ecc_corr_err = {OtpMacroEccCorrError}; + bins ecc_uncorr_err = {OtpMacroEccUncorrError}; + bins check_fail = {OtpCheckFailError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + endgroup + + function new(string name); + buf_err_code_cg = new(name); + endfunction +endclass + +class otp_ctrl_csr_rd_after_alert_cg_wrap; + // This covergroup samples CSRs being checked (via CSR read) after fatal alert is issued. + covergroup csr_rd_after_alert_cg(otp_ctrl_core_reg_block ral) with function sample(bit[TL_DW-1:0] + csr_offset); + read_csr_after_alert_issued: coverpoint csr_offset { + bins unbuffered_digests = { + ral.vendor_test_digest[0].get_offset(), + ral.vendor_test_digest[1].get_offset(), + ral.creator_sw_cfg_digest[0].get_offset(), + ral.creator_sw_cfg_digest[1].get_offset(), + ral.owner_sw_cfg_digest[0].get_offset(), + ral.owner_sw_cfg_digest[1].get_offset(), + ral.rot_creator_auth_digest[0].get_offset(), + ral.rot_creator_auth_digest[1].get_offset(), + ral.rot_owner_auth_slot0_digest[0].get_offset(), + ral.rot_owner_auth_slot0_digest[1].get_offset(), + ral.rot_owner_auth_slot1_digest[0].get_offset(), + ral.rot_owner_auth_slot1_digest[1].get_offset(), + ral.plat_integ_auth_slot0_digest[0].get_offset(), + ral.plat_integ_auth_slot0_digest[1].get_offset(), + ral.plat_integ_auth_slot1_digest[0].get_offset(), + ral.plat_integ_auth_slot1_digest[1].get_offset(), + ral.plat_owner_auth_slot0_digest[0].get_offset(), + ral.plat_owner_auth_slot0_digest[1].get_offset(), + ral.plat_owner_auth_slot1_digest[0].get_offset(), + ral.plat_owner_auth_slot1_digest[1].get_offset(), + ral.plat_owner_auth_slot2_digest[0].get_offset(), + ral.plat_owner_auth_slot2_digest[1].get_offset(), + ral.plat_owner_auth_slot3_digest[0].get_offset(), + ral.plat_owner_auth_slot3_digest[1].get_offset(), + ral.rom_patch_digest[0].get_offset(), + ral.rom_patch_digest[1].get_offset() + }; + bins hw_digests = { + ral.hw_cfg0_digest[0].get_offset(), + ral.hw_cfg0_digest[1].get_offset(), + ral.hw_cfg1_digest[0].get_offset(), + ral.hw_cfg1_digest[1].get_offset() + }; + bins secret_digests = { + ral.secret0_digest[0].get_offset(), + ral.secret0_digest[1].get_offset(), + ral.secret1_digest[0].get_offset(), + ral.secret1_digest[1].get_offset(), + ral.secret2_digest[0].get_offset(), + ral.secret2_digest[1].get_offset(), + ral.secret3_digest[0].get_offset(), + ral.secret3_digest[1].get_offset() + }; + bins direct_access_rdata = { + ral.direct_access_rdata[0].get_offset(), + ral.direct_access_rdata[1].get_offset() + }; + bins status = { + ral.status.get_offset() + }; + bins error_code = { + ral.err_code[0].get_offset(), + ral.err_code[1].get_offset(), + ral.err_code[2].get_offset(), + ral.err_code[3].get_offset(), + ral.err_code[4].get_offset(), + ral.err_code[5].get_offset(), + ral.err_code[6].get_offset(), + ral.err_code[7].get_offset(), + ral.err_code[8].get_offset(), + ral.err_code[9].get_offset(), + ral.err_code[10].get_offset(), + ral.err_code[11].get_offset(), + ral.err_code[12].get_offset(), + ral.err_code[13].get_offset(), + ral.err_code[14].get_offset(), + ral.err_code[15].get_offset(), + ral.err_code[16].get_offset(), + ral.err_code[17].get_offset(), + ral.err_code[18].get_offset(), + ral.err_code[19].get_offset(), + ral.err_code[20].get_offset(), + ral.err_code[21].get_offset(), + ral.err_code[22].get_offset(), + ral.err_code[23].get_offset() + }; + } + endgroup + + function new(otp_ctrl_core_reg_block ral); + csr_rd_after_alert_cg = new(ral); + endfunction + + function void sample(bit[TL_DW-1:0] csr_offset); + csr_rd_after_alert_cg.sample(csr_offset); + endfunction +endclass + +class otp_ctrl_unbuf_access_lock_cg_wrap; + covergroup unbuf_access_lock_cg(string name) with function sample(bit read_lock, bit write_lock, + bit is_write); + option.per_instance = 1; + option.name = name; + read_access_locked: coverpoint read_lock; + write_access_locked: coverpoint write_lock; + operation_type: coverpoint is_write { + bins write_op = {1}; + bins read_op = {0}; + } + unbuf_part_access_cross: cross read_access_locked, write_access_locked, operation_type; + endgroup + + function new(string name); + unbuf_access_lock_cg = new(name); + endfunction + + function void sample(bit read_lock, bit write_lock, bit is_write); + unbuf_access_lock_cg.sample(read_lock, write_lock, is_write); + endfunction +endclass + +class otp_ctrl_env_cov extends cip_base_env_cov #(.CFG_T(otp_ctrl_env_cfg)); + `uvm_component_utils(otp_ctrl_env_cov) + + // the base class provides the following handles for use: + // otp_ctrl_env_cfg: cfg + + otp_ctrl_unbuf_err_code_cg_wrap unbuf_err_code_cg_wrap[NumPartUnbuf]; + otp_ctrl_buf_err_code_cg_wrap buf_err_code_cg_wrap[NumPartBuf]; + otp_ctrl_csr_rd_after_alert_cg_wrap csr_rd_after_alert_cg_wrap; + otp_ctrl_unbuf_access_lock_cg_wrap unbuf_access_lock_cg_wrap[NumPartUnbuf]; + + bit_toggle_cg_wrap lc_prog_cg; + bit_toggle_cg_wrap otbn_req_cg; + bit_toggle_cg_wrap status_csr_cg[OtpStatusFieldSize]; + + // covergroups + // This covergroup collects different conditions when outputs (hwcfg_o, keymgr_key_o) are checked + // in scb: + // - If lc_esc_en is On + // - If each partition is locked (expect LC) + covergroup power_on_cg with function sample (bit lc_esc_en, bit[NumPart-2:0] parts_locked); + lc_esc: coverpoint lc_esc_en; + vendor_test_lock: coverpoint parts_locked[0]; + creator_sw_cfg_lock: coverpoint parts_locked[1]; + owner_sw_cfg_lock: coverpoint parts_locked[2]; + ownership_slot_state_lock: coverpoint parts_locked[3]; + rot_creator_auth_lock: coverpoint parts_locked[4]; + rot_owner_auth_slot0_lock: coverpoint parts_locked[5]; + rot_owner_auth_slot1_lock: coverpoint parts_locked[6]; + plat_integ_auth_slot0_lock: coverpoint parts_locked[7]; + plat_integ_auth_slot1_lock: coverpoint parts_locked[8]; + plat_owner_auth_slot0_lock: coverpoint parts_locked[9]; + plat_owner_auth_slot1_lock: coverpoint parts_locked[10]; + plat_owner_auth_slot2_lock: coverpoint parts_locked[11]; + plat_owner_auth_slot3_lock: coverpoint parts_locked[12]; + ext_nvm_lock: coverpoint parts_locked[13]; + rom_patch_lock: coverpoint parts_locked[14]; + hw_cfg0_lock: coverpoint parts_locked[15]; + hw_cfg1_lock: coverpoint parts_locked[16]; + secret0_lock: coverpoint parts_locked[17]; + secret1_lock: coverpoint parts_locked[18]; + secret2_lock: coverpoint parts_locked[19]; + secret3_lock: coverpoint parts_locked[20]; + endgroup + + // This covergroup is sampled only if sram request passed scb check. + covergroup sram_req_cg with function sample (int index, bit locked); + sram_index: coverpoint index { + bins sram_key[NumSramKeyReqSlots] = {[0:(NumSramKeyReqSlots-1)]}; + illegal_bins il = default; + } + secret1_lock: coverpoint locked; + sram_req_lock_cross: cross sram_index, secret1_lock; + endgroup + + // This covergroup is sampled only if keymgr output passed scb check. + covergroup keymgr_o_cg with function sample (bit lc_seed_hw_rd_en, bit locked); + keymgr_rd_en: coverpoint lc_seed_hw_rd_en; + // TODO: probably should add all partitions with keymgr material here. + secret2_lock: coverpoint locked; + keymgr_output_conditions: cross keymgr_rd_en, secret2_lock; + endgroup + + // This covergroup samples dai request being issued after fatal alert is issued. + covergroup req_dai_access_after_alert_cg with function sample(bit [TL_DW-1:0] val); + req_dai_access_after_alert_issued: coverpoint val { + bins dai_write = {DaiWrite}; + bins dai_read = {DaiRead}; + bins dai_digest = {DaiDigest}; + } + endgroup + + // This covergroup samples background check being issued after fatal alert is issued. + covergroup issue_checks_after_alert_cg with function sample(bit [TL_DW-1:0] val); + issue_checks_after_alert_issued: coverpoint val { + bins integrity_check = {1}; + bins consistency_check = {2}; + } + endgroup + + // This covergroup collects DAI err_code value. + // DAI access does not have checks, thus no check_fail error. + covergroup dai_err_code_cg with function sample(bit [TL_DW-1:0] val, int part_idx); + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins ecc_corr_err = {OtpMacroEccCorrError}; + bins ecc_uncorr_err = {OtpMacroEccUncorrError}; + bins write_blank_err = {OtpMacroWriteBlankError}; + bins access_err = {OtpAccessError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + partition: coverpoint part_idx { + bins vendor_test = {VendorTestIdx}; + bins creator_sw_cfg = {CreatorSwCfgIdx}; + bins owner_sw_cfg = {OwnerSwCfgIdx}; + bins ownership_slot_state = {OwnershipSlotStateIdx}; + bins rot_creator_auth = {RotCreatorAuthIdx}; + bins rot_owner_auth_slot0 = {RotOwnerAuthSlot0Idx}; + bins rot_owner_auth_slot1 = {RotOwnerAuthSlot1Idx}; + bins plat_integ_auth_slot0 = {PlatIntegAuthSlot0Idx}; + bins plat_integ_auth_slot1 = {PlatIntegAuthSlot1Idx}; + bins plat_owner_auth_slot0 = {PlatOwnerAuthSlot0Idx}; + bins plat_owner_auth_slot1 = {PlatOwnerAuthSlot1Idx}; + bins plat_owner_auth_slot2 = {PlatOwnerAuthSlot2Idx}; + bins plat_owner_auth_slot3 = {PlatOwnerAuthSlot3Idx}; + bins ext_nvm = {ExtNvmIdx}; + bins rom_patch = {RomPatchIdx}; + bins hw_cfg0 = {HwCfg0Idx}; + bins hw_cfg1 = {HwCfg1Idx}; + bins secret0 = {Secret0Idx}; + bins secret1 = {Secret1Idx}; + bins secret2 = {Secret2Idx}; + bins secret3 = {Secret3Idx}; + bins life_cycle = {LifeCycleIdx}; + bins illegal_idx = default; + } + // LC partition has a separate LCI err_code to collect macro related errors. + dai_err_code_for_all_partitions: cross err_code_vals, partition { + // Illegal bin - vendor_test partition does not have EccUncorrectable error. + illegal_bins vendor_test_ecc_uncorrectable_err = + binsof (partition.vendor_test) && binsof (err_code_vals.ecc_uncorr_err); + ignore_bins life_cycle_ignore = binsof (partition.life_cycle) && + binsof(err_code_vals) intersect {[OtpMacroError:OtpMacroWriteBlankError]}; + } + endgroup + + // This covergroup collects LCI err_code value. + // LCI access does not have digest, thus no access_err. Check_fail, ecc_errors are covered in lc + // buffered partition instead of LCI here. + covergroup lci_err_code_cg with function sample(bit [TL_DW-1:0] val); + err_code_vals: coverpoint val { + bins no_err = {OtpNoError}; + bins macro_err = {OtpMacroError}; + bins write_blank_err = {OtpMacroWriteBlankError}; + bins fsm_err = {OtpFsmStateError}; + illegal_bins illegal_err = default; + } + endgroup + + covergroup dai_access_secret2_cg with function sample(bit lc_rw_en, dai_cmd_e dai_cmd); + lc_creator_seed_sw_rw_en: coverpoint lc_rw_en; + dai_access_cmd: coverpoint dai_cmd { + bins dai_rd = {DaiRead}; + bins dai_wr = {DaiWrite}; + bins dai_digest = {DaiDigest}; + } + dai_access_secret2: cross lc_creator_seed_sw_rw_en, dai_access_cmd; + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + // Create coverage from local covergroups. + power_on_cg = new(); + sram_req_cg = new(); + keymgr_o_cg = new(); + req_dai_access_after_alert_cg = new(); + issue_checks_after_alert_cg = new(); + dai_err_code_cg = new(); + lci_err_code_cg = new(); + dai_access_secret2_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // Create instances from bit_toggle_cg_wrapper. + lc_prog_cg = new("lc_prog_cg", "", 0); + otbn_req_cg = new("otbn_req_cg", "", 0); + foreach (status_csr_cg[i]) begin + otp_status_e index = otp_status_e'(i); + status_csr_cg[i]= new(index.name, "status_csr_cg", 0); + end + + // Create instances from external wrapper classes. + csr_rd_after_alert_cg_wrap = new(cfg.ral); + foreach (unbuf_err_code_cg_wrap[i]) begin + otp_status_e index = otp_status_e'(i); + unbuf_err_code_cg_wrap[i] = new($sformatf("unbuf_err_code_cg_wrap[%0s]", index.name)); + end + foreach (buf_err_code_cg_wrap[i]) begin + otp_status_e index = otp_status_e'(i + 2); + buf_err_code_cg_wrap[i] = new($sformatf("buf_err_code_cg_wrap[%0s]", index.name)); + end + foreach (unbuf_access_lock_cg_wrap[i]) begin + part_idx_e index = part_idx_e'(i); + unbuf_access_lock_cg_wrap[i] = new($sformatf("buf_err_code_cg_wrap[%0s]", index.name)); + end + endfunction + + function void collect_status_cov(bit [TL_DW-1:0] val); + foreach (status_csr_cg[i]) begin + status_csr_cg[i].sample(val[i]); + end + endfunction + + // Collect coverage for err_code when it is a compact multi-reg. For DAI error it uses the given + // access_part_idx as the target of the DAI access. + function void collect_compact_err_code_cov(bit [TL_DW-1:0] val, int access_part_idx = DaiIdx); + dv_base_reg_field err_code_flds[$]; + cfg.ral.err_code[0].get_dv_base_reg_fields(err_code_flds); + foreach (err_code_flds[part]) begin + collect_err_code_cov(part, get_field_val(err_code_flds[part], val), access_part_idx); + end + endfunction + + // Collect coverage for a given partition error_code. For DAI error it uses the given + // access_part_idx as the target of the DAI access. + function void collect_err_code_cov(int part_idx, bit [TL_DW-1:0] val, + int access_part_idx = DaiIdx); + case (part_idx) + OtpVendorTestErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpCreatorSwCfgErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpOwnerSwCfgErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpOwnershipSlotStateErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpRotCreatorAuthErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpRotOwnerAuthSlot0ErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpRotOwnerAuthSlot1ErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpPlatIntegAuthSlot0ErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpPlatIntegAuthSlot1ErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpPlatOwnerAuthSlot0ErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpPlatOwnerAuthSlot1ErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpPlatOwnerAuthSlot2ErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpPlatOwnerAuthSlot3ErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpExtNvmErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpRomPatchErrIdx: begin + unbuf_err_code_cg_wrap[part_idx].unbuf_err_code_cg.sample(val); + end + OtpHwCfg0ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpHwCfg1ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpSecret0ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpSecret1ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpSecret2ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpSecret3ErrIdx: begin + buf_err_code_cg_wrap[part_idx - NumPartUnbuf].buf_err_code_cg.sample(val); + end + OtpLifeCycleErrIdx: begin + end + OtpDaiErrIdx: begin + dai_err_code_cg.sample(val, access_part_idx); + end + OtpLciErrIdx: begin + lci_err_code_cg.sample(val); + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid err_code index %0d", part_idx)) + end + endcase + endfunction +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv new file mode 100644 index 00000000000..12b50fd7d59 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_env_pkg.sv @@ -0,0 +1,299 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +package otp_ctrl_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import dv_base_reg_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import csr_utils_pkg::*; + import push_pull_agent_pkg::*; + import otp_ctrl_core_ral_pkg::*; + import otp_macro_prim_ral_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_pkg::*; + import otp_ctrl_part_pkg::*; + import otp_ctrl_top_specific_pkg::*; + import lc_ctrl_pkg::*; + import lc_ctrl_state_pkg::*; + import lc_ctrl_dv_utils_pkg::*; + import mem_bkdr_util_pkg::*; + import otp_scrambler_pkg::*; + import sec_cm_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter uint NUM_ALERTS = 5; + parameter string LIST_OF_ALERTS[NUM_ALERTS] = {"fatal_macro_error", + "fatal_check_error", + "fatal_bus_integ_error", + "fatal_prim_otp_alert", + "recov_prim_otp_alert"}; + parameter uint NUM_EDN = 1; + + parameter uint DIGEST_SIZE = 8; + parameter uint SW_WINDOW_BASE_ADDR = 'h4000; + parameter uint SW_WINDOW_SIZE = NumSwCfgWindowWords * 4; + + parameter uint TL_SIZE = (TL_DW / 8); + // LC has its own storage in scb + // we can use the LC offset here because it will always be the last partition. + parameter uint OTP_ARRAY_SIZE = LcTransitionCntOffset / TL_SIZE; + + parameter int OTP_ADDR_WIDTH = OtpByteAddrWidth-2; + + parameter uint NUM_PRIM_REG = 8; + + // sram rsp data has 1 bit for seed_valid, the rest are for key and nonce + parameter uint SRAM_DATA_SIZE = 1 + SramKeyWidth + SramNonceWidth; + // otbn rsp data has 1 bit for seed_valid, the rest are for key and nonce + parameter uint OTBN_DATA_SIZE = 1 + OtbnKeyWidth + OtbnNonceWidth; + // lc program data has lc_state data and lc_cnt data + parameter uint LC_PROG_DATA_SIZE = LcStateWidth + LcCountWidth; + + parameter uint NUM_SRAM_EDN_REQ = 12; + parameter uint NUM_OTBN_EDN_REQ = 10; + + // This is used to randomize CHECK_TIMEOUT in sequences, set to a low value + // so it will certainly cause a check error due to a timeout. + parameter uint CHK_TIMEOUT_CYC = 40; + // This is some slack for a timeout error propagation to become an alert. + parameter uint CHK_TIMEOUT_SLACK = 4; + + // When fatal alert triggered, all partitions and the DAI & LCI go to error state and status will + // be set to 1. + parameter bit [NumErrorEntries-1:0] FATAL_EXP_STATUS = '1; + + // lc does not have dai access + parameter int PART_BASE_ADDRS [NumPart-1] = { + VendorTestOffset, + CreatorSwCfgOffset, + OwnerSwCfgOffset, + OwnershipSlotStateOffset, + RotCreatorAuthOffset, + RotOwnerAuthSlot0Offset, + RotOwnerAuthSlot1Offset, + PlatIntegAuthSlot0Offset, + PlatIntegAuthSlot1Offset, + PlatOwnerAuthSlot0Offset, + PlatOwnerAuthSlot1Offset, + PlatOwnerAuthSlot2Offset, + PlatOwnerAuthSlot3Offset, + ExtNvmOffset, + RomPatchOffset, + HwCfg0Offset, + HwCfg1Offset, + Secret0Offset, + Secret1Offset, + Secret2Offset, + Secret3Offset + }; + + // lc does not have digest + parameter int PART_OTP_DIGEST_ADDRS [NumPart-1] = { + VendorTestDigestOffset >> 2, + CreatorSwCfgDigestOffset >> 2, + OwnerSwCfgDigestOffset >> 2, + -1, // This partition does not have a digest. + RotCreatorAuthDigestOffset >> 2, + RotOwnerAuthSlot0DigestOffset >> 2, + RotOwnerAuthSlot1DigestOffset >> 2, + PlatIntegAuthSlot0DigestOffset >> 2, + PlatIntegAuthSlot1DigestOffset >> 2, + PlatOwnerAuthSlot0DigestOffset >> 2, + PlatOwnerAuthSlot1DigestOffset >> 2, + PlatOwnerAuthSlot2DigestOffset >> 2, + PlatOwnerAuthSlot3DigestOffset >> 2, + -1, // This partition does not have a digest. + RomPatchDigestOffset >> 2, + HwCfg0DigestOffset >> 2, + HwCfg1DigestOffset >> 2, + Secret0DigestOffset >> 2, + Secret1DigestOffset >> 2, + Secret2DigestOffset >> 2, + Secret3DigestOffset >> 2 + }; + + // types + typedef enum bit [1:0] { + OtpOperationDone, + OtpErr, + NumOtpCtrlIntr + } otp_intr_e; + + typedef enum bit [5:0] { + OtpVendorTestErrIdx, + OtpCreatorSwCfgErrIdx, + OtpOwnerSwCfgErrIdx, + OtpOwnershipSlotStateErrIdx, + OtpRotCreatorAuthErrIdx, + OtpRotOwnerAuthSlot0ErrIdx, + OtpRotOwnerAuthSlot1ErrIdx, + OtpPlatIntegAuthSlot0ErrIdx, + OtpPlatIntegAuthSlot1ErrIdx, + OtpPlatOwnerAuthSlot0ErrIdx, + OtpPlatOwnerAuthSlot1ErrIdx, + OtpPlatOwnerAuthSlot2ErrIdx, + OtpPlatOwnerAuthSlot3ErrIdx, + OtpExtNvmErrIdx, + OtpRomPatchErrIdx, + OtpHwCfg0ErrIdx, + OtpHwCfg1ErrIdx, + OtpSecret0ErrIdx, + OtpSecret1ErrIdx, + OtpSecret2ErrIdx, + OtpSecret3ErrIdx, + OtpLifeCycleErrIdx, + OtpDaiErrIdx, + OtpLciErrIdx, + OtpTimeoutErrIdx, + OtpLfsrFsmErrIdx, + OtpScramblingFsmErrIdx, + OtpDerivKeyFsmErrIdx, + OtpBusIntegErrorIdx, + OtpDaiIdleIdx, + OtpCheckPendingIdx, + OtpStatusFieldSize + } otp_status_e; + + typedef enum bit [2:0] { + OtpNoError, + OtpMacroError, + OtpMacroEccCorrError, + OtpMacroEccUncorrError, + OtpMacroWriteBlankError, + OtpAccessError, + OtpCheckFailError, + OtpFsmStateError + } otp_err_code_e; + + typedef enum bit [1:0] { + OtpNoEccErr, + OtpEccCorrErr, + OtpEccUncorrErr + } otp_ecc_err_e; + + typedef enum bit [1:0] { + OtpNoAlert, + OtpCheckAlert, + OtpMacroAlert + } otp_alert_e; + + typedef struct packed { + bit read_lock; + bit write_lock; + } otp_part_access_lock_t; + + // OTP conditions when driving specific port. + typedef enum bit [2:0] { + DuringOTPInit, + DuringOTPDaiBusy, + DuringOTPDaiDigest, + DuringOTPRead, + DriveRandomly + } port_drive_condition_e; + + typedef virtual otp_ctrl_if otp_ctrl_vif; + + parameter otp_err_code_e OTP_TERMINAL_ERRS[4] = {OtpMacroEccUncorrError, + OtpCheckFailError, + OtpFsmStateError, + OtpMacroError}; + + // functions + function automatic int get_part_index(bit [TL_DW-1:0] addr); + int index; + for (index = 0; index < NumPart; index++) begin + if (PartInfo[index].offset > addr) begin + index--; + break; + end + end + if (index == NumPart) index--; + return index; + endfunction + + function automatic bit is_secret(bit [TL_DW-1:0] addr); + int part_index = get_part_index(addr); + return PartInfo[part_index].secret; + endfunction + + function automatic bit part_has_digest(int part_idx); + return PartInfo[part_idx].hw_digest || PartInfo[part_idx].sw_digest; + endfunction + + function automatic bit part_has_hw_digest(int part_idx); + return PartInfo[part_idx].hw_digest; + endfunction + + function automatic bit is_sw_digest(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + if (PartInfo[part_idx].sw_digest) begin + // If the partition contains a digest, it will be located in the last 64bit of the partition. + return {addr[TL_DW-1:3], 3'b0} == ((PartInfo[part_idx].offset + PartInfo[part_idx].size) - 8); + end else begin + return 0; + end + endfunction + + function automatic bit is_digest(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + if (PartInfo[part_idx].sw_digest || PartInfo[part_idx].hw_digest) begin + // If the partition contains a digest, it will be located in the last 64bit of the partition. + return {addr[TL_DW-1:3], 3'b0} == ((PartInfo[part_idx].offset + PartInfo[part_idx].size) - 8); + end else begin + return 0; + end + endfunction + + function automatic bit is_sw_part(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + return is_sw_part_idx(part_idx); + endfunction + + function automatic bit is_sw_part_idx(int part_idx); + return (PartInfo[part_idx].variant == Unbuffered); + endfunction + + function automatic bit is_hw_part(bit [TL_DW-1:0] addr); + int part_idx = get_part_index(addr); + return is_hw_part_idx(part_idx); + endfunction + + function automatic bit is_hw_part_idx(int part_idx); + return (PartInfo[part_idx].variant == Buffered); + endfunction + + // Returns true if this partition supports ECC. Otherwise, no ECC errors are reported, and + // the single bit errors are not corrected. + function automatic bit part_has_integrity(int part_idx); + return PartInfo[part_idx].integrity; + endfunction + + // Resolve an offset within the software window as an offset within the whole otp_ctrl block. + function automatic bit [TL_AW-1:0] get_sw_window_offset(bit [TL_AW-1:0] dai_addr); + return dai_addr + SW_WINDOW_BASE_ADDR; + endfunction + + function automatic bit [TL_DW-1:0] normalize_dai_addr(bit [TL_DW-1:0] dai_addr); + normalize_dai_addr = (is_secret(dai_addr) || is_digest(dai_addr)) ? dai_addr >> 3 << 3 : + dai_addr >> 2 << 2; + endfunction + + // package sources + `include "otp_ctrl_ast_inputs_cfg.sv" + `include "otp_ctrl_env_cfg.sv" + `include "otp_ctrl_env_cov.sv" + `include "otp_ctrl_virtual_sequencer.sv" + `include "otp_ctrl_scoreboard.sv" + `include "otp_ctrl_env.sv" + `include "otp_ctrl_vseq_list.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv new file mode 100644 index 00000000000..08c45a63065 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_if.sv @@ -0,0 +1,458 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// This interface collect the broadcast output data from OTP, +// and drive input requests coming into OTP. +`define ECC_REG_PATH gen_ecc_reg.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec + +// This only supports buffered partitions. +`define BUF_PART_OTP_CMD_PATH(i) \ + tb.dut.gen_partitions[``i``].gen_buffered.u_part_buf.otp_cmd_o + +`define LC_PART_OTP_CMD_PATH \ + tb.dut.gen_partitions[LifeCycleIdx].gen_lifecycle.u_part_buf.otp_cmd_o + +`define FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(i) \ + if (forced_part_access_sel[``i``].read_lock) begin \ + force tb.dut.part_access[``i``].read_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + force tb.dut.part_access_dai[``i``].read_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + end \ + if (forced_part_access_sel[``i``].write_lock) begin \ + force tb.dut.part_access[``i``].write_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + force tb.dut.part_access_dai[``i``].write_lock = get_rand_mubi8_val(.t_weight(0), .f_weight(0)); \ + end + +`ifndef PRIM_GENERIC_OTP_PATH + `define PRIM_GENERIC_OTP_PATH\ + tb.otp_macro +`endif + +`ifndef PRIM_GENERIC_OTP_CMD_I_PATH + `define PRIM_GENERIC_OTP_CMD_I_PATH \ + `PRIM_GENERIC_OTP_PATH.otp_i.cmd +`endif + +interface otp_ctrl_if(input clk_i, input rst_ni); + import uvm_pkg::*; + import otp_ctrl_env_pkg::*; + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import otp_macro_pkg::*; + import cip_base_pkg::*; + + // Output from DUT + otp_broadcast_t otp_broadcast_o; + otp_keymgr_key_t keymgr_key_o; + otp_lc_data_t lc_data_o; + logic pwr_otp_done_o, pwr_otp_idle_o; + + // Inputs to DUT + logic pwr_otp_init_i, scan_en_i, scan_rst_ni, ext_voltage_h_io; + lc_ctrl_pkg::lc_tx_t lc_dft_en_i, lc_escalate_en_i, lc_check_byp_en_i, + lc_creator_seed_sw_rw_en_i, lc_owner_seed_sw_rw_en_i, + lc_seed_hw_rd_en_i; + prim_mubi_pkg::mubi4_t scanmode_i; + otp_ast_rsp_t otp_ast_pwr_seq_h_i; + ast_pkg::ast_obs_ctrl_t obs_ctrl_i; + + // Unused in prim_generic_otp memory. + logic [OtpTestCtrlWidth-1:0] otp_vendor_test_ctrl_i; + logic [OtpTestStatusWidth-1:0] otp_vendor_test_status_o; + logic [OtpTestVectWidth-1:0] cio_test_o; + logic [OtpTestVectWidth-1:0] cio_test_en_o; + + // Connect with lc_prog push_pull interface. + logic lc_prog_req, lc_prog_err; + logic lc_prog_err_dly1, lc_prog_no_sta_check; + + // Connect push_pull interfaces ack signals for assertion checks. + logic otbn_ack, lc_prog_ack; + logic [NumSramKeyReqSlots-1:0] sram_acks; + + // Variables for internal interface logic. + // `lc_escalate_en` is async, take two clock cycles to synchronize. + lc_ctrl_pkg::lc_tx_t lc_esc_dly1, lc_esc_dly2; + + // Variable for scoreboard. + // For `lc_escalate_en`, any value that is not `Off` is a `On`. + bit lc_esc_on; + + // Probe design signal for alert request. + logic alert_reqs; + + // Usually the `lc_check_byp_en` will be automatically set to `On` when LC program request is + // issued, and stays `On` until reset is issued. + // Set this variable to 0 after a LC program request might cause otp checks to fail. + bit lc_check_byp_en = 1; + + // Internal variable to track which sw partitions have ECC reg error. + bit [NumPartUnbuf-1:0] force_sw_parts_ecc_reg; + + // DUT configuration object + otp_ctrl_ast_inputs_cfg dut_cfg; + + // for DV macros ID + string msg_id = "otp_ctrl_if"; + + // Lc_err could trigger during LC program, so check intr and status after lc_req is finished. + // Lc_err takes one clock cycle to propagate to intr signal. So avoid intr check if it happens + // during the transition. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + lc_prog_err_dly1 <= 0; + lc_esc_dly1 <= lc_ctrl_pkg::Off; + lc_esc_dly2 <= lc_ctrl_pkg::Off; + lc_check_byp_en_i <= get_rand_lc_tx_val(); + lc_esc_on <= 0; + end else begin + lc_prog_err_dly1 <= lc_prog_err; + lc_esc_dly1 <= lc_escalate_en_i; + lc_esc_dly2 <= lc_esc_dly1; + if (lc_prog_req) begin + lc_check_byp_en_i <= lc_check_byp_en ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + end + if (lc_esc_dly2 != lc_ctrl_pkg::Off && !lc_esc_on) begin + lc_esc_on <= 1; + end + end + end + + assign lc_prog_no_sta_check = lc_prog_err | lc_prog_err_dly1 | lc_prog_req | lc_esc_on; + + function automatic void drive_pwr_otp_init(logic val); + pwr_otp_init_i = val; + endfunction + + function automatic void drive_ext_voltage_h_io(logic val); + ext_voltage_h_io = val; + endfunction + + function automatic void drive_lc_creator_seed_sw_rw_en(lc_ctrl_pkg::lc_tx_t val); + lc_creator_seed_sw_rw_en_i = val; + endfunction + + function automatic void drive_lc_owner_seed_sw_rw_en(lc_ctrl_pkg::lc_tx_t val); + lc_owner_seed_sw_rw_en_i = val; + endfunction + + function automatic void drive_lc_dft_en(lc_ctrl_pkg::lc_tx_t val); + lc_dft_en_i = val; + endfunction + + function automatic void drive_lc_escalate_en(lc_ctrl_pkg::lc_tx_t val); + lc_escalate_en_i = val; + endfunction + + function automatic void drive_lc_seed_hw_rd_en(lc_ctrl_pkg::lc_tx_t val); + lc_seed_hw_rd_en_i = val; + endfunction + + function automatic bit under_error_states(); + return lc_esc_on | alert_reqs; + endfunction + + // SW partitions do not have any internal checks. + // Here we force internal ECC check to fail. + task automatic force_sw_check_fail( + bit[NumPartUnbuf-1:0] fail_idx = $urandom_range(1, (1'b1 << NumPartUnbuf) - 1)); + @(posedge clk_i); + if (fail_idx[VendorTestIdx]) begin + force tb.dut.gen_partitions[VendorTestIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[VendorTestIdx] = 1; + end + if (fail_idx[CreatorSwCfgIdx]) begin + force tb.dut.gen_partitions[CreatorSwCfgIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[CreatorSwCfgIdx] = 1; + end + if (fail_idx[OwnerSwCfgIdx]) begin + force tb.dut.gen_partitions[OwnerSwCfgIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[OwnerSwCfgIdx] = 1; + end + if (fail_idx[RotCreatorAuthIdx]) begin + force tb.dut.gen_partitions[RotCreatorAuthIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[RotCreatorAuthIdx] = 1; + end + if (fail_idx[RotOwnerAuthSlot0Idx]) begin + force tb.dut.gen_partitions[RotOwnerAuthSlot0Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[RotOwnerAuthSlot0Idx] = 1; + end + if (fail_idx[RotOwnerAuthSlot1Idx]) begin + force tb.dut.gen_partitions[RotOwnerAuthSlot1Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[RotOwnerAuthSlot1Idx] = 1; + end + if (fail_idx[PlatIntegAuthSlot0Idx]) begin + force tb.dut.gen_partitions[PlatIntegAuthSlot0Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[PlatIntegAuthSlot0Idx] = 1; + end + if (fail_idx[PlatIntegAuthSlot1Idx]) begin + force tb.dut.gen_partitions[PlatIntegAuthSlot1Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[PlatIntegAuthSlot1Idx] = 1; + end + if (fail_idx[PlatOwnerAuthSlot0Idx]) begin + force tb.dut.gen_partitions[PlatOwnerAuthSlot0Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[PlatOwnerAuthSlot0Idx] = 1; + end + if (fail_idx[PlatOwnerAuthSlot1Idx]) begin + force tb.dut.gen_partitions[PlatOwnerAuthSlot1Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[PlatOwnerAuthSlot1Idx] = 1; + end + if (fail_idx[PlatOwnerAuthSlot2Idx]) begin + force tb.dut.gen_partitions[PlatOwnerAuthSlot2Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[PlatOwnerAuthSlot2Idx] = 1; + end + if (fail_idx[PlatOwnerAuthSlot3Idx]) begin + force tb.dut.gen_partitions[PlatOwnerAuthSlot3Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[PlatOwnerAuthSlot3Idx] = 1; + end + if (fail_idx[RomPatchIdx]) begin + force tb.dut.gen_partitions[RomPatchIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0] = 1; + force_sw_parts_ecc_reg[RomPatchIdx] = 1; + end + endtask + + task automatic release_sw_check_fail(); + @(posedge clk_i); + if (force_sw_parts_ecc_reg[VendorTestIdx]) begin + release tb.dut.gen_partitions[VendorTestIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[VendorTestIdx] = 0; + end + if (force_sw_parts_ecc_reg[CreatorSwCfgIdx]) begin + release tb.dut.gen_partitions[CreatorSwCfgIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[CreatorSwCfgIdx] = 0; + end + if (force_sw_parts_ecc_reg[OwnerSwCfgIdx]) begin + release tb.dut.gen_partitions[OwnerSwCfgIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[OwnerSwCfgIdx] = 0; + end + if (force_sw_parts_ecc_reg[RotCreatorAuthIdx]) begin + release tb.dut.gen_partitions[RotCreatorAuthIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[RotCreatorAuthIdx] = 0; + end + if (force_sw_parts_ecc_reg[RotOwnerAuthSlot0Idx]) begin + release tb.dut.gen_partitions[RotOwnerAuthSlot0Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[RotOwnerAuthSlot0Idx] = 0; + end + if (force_sw_parts_ecc_reg[RotOwnerAuthSlot1Idx]) begin + release tb.dut.gen_partitions[RotOwnerAuthSlot1Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[RotOwnerAuthSlot1Idx] = 0; + end + if (force_sw_parts_ecc_reg[PlatIntegAuthSlot0Idx]) begin + release tb.dut.gen_partitions[PlatIntegAuthSlot0Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[PlatIntegAuthSlot0Idx] = 0; + end + if (force_sw_parts_ecc_reg[PlatIntegAuthSlot1Idx]) begin + release tb.dut.gen_partitions[PlatIntegAuthSlot1Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[PlatIntegAuthSlot1Idx] = 0; + end + if (force_sw_parts_ecc_reg[PlatOwnerAuthSlot0Idx]) begin + release tb.dut.gen_partitions[PlatOwnerAuthSlot0Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[PlatOwnerAuthSlot0Idx] = 0; + end + if (force_sw_parts_ecc_reg[PlatOwnerAuthSlot1Idx]) begin + release tb.dut.gen_partitions[PlatOwnerAuthSlot1Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[PlatOwnerAuthSlot1Idx] = 0; + end + if (force_sw_parts_ecc_reg[PlatOwnerAuthSlot2Idx]) begin + release tb.dut.gen_partitions[PlatOwnerAuthSlot2Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[PlatOwnerAuthSlot2Idx] = 0; + end + if (force_sw_parts_ecc_reg[PlatOwnerAuthSlot3Idx]) begin + release tb.dut.gen_partitions[PlatOwnerAuthSlot3Idx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[PlatOwnerAuthSlot3Idx] = 0; + end + if (force_sw_parts_ecc_reg[RomPatchIdx]) begin + release tb.dut.gen_partitions[RomPatchIdx].gen_unbuffered. + u_part_unbuf.`ECC_REG_PATH.data_i[0]; + force_sw_parts_ecc_reg[RomPatchIdx] = 0; + end + endtask + + // Force prim_generic_otp input cmd_i to a invalid value. + task automatic force_invalid_otp_cmd_i(); + @(posedge clk_i); + force `PRIM_GENERIC_OTP_CMD_I_PATH = otp_ctrl_macro_pkg::cmd_e'(2'b10); + endtask + + task automatic release_invalid_otp_cmd_i(); + @(posedge clk_i); + release `PRIM_GENERIC_OTP_CMD_I_PATH; + endtask + + // Force part_buf partitions output otp_cmd_o to a invalid value. + task automatic force_invalid_part_cmd_o(int part_idx); + @(posedge clk_i); + case (part_idx) + HwCfg0Idx: force `BUF_PART_OTP_CMD_PATH(HwCfg0Idx) = otp_ctrl_macro_pkg::cmd_e'(2'b10); + HwCfg1Idx: force `BUF_PART_OTP_CMD_PATH(HwCfg1Idx) = otp_ctrl_macro_pkg::cmd_e'(2'b10); + Secret0Idx: force `BUF_PART_OTP_CMD_PATH(Secret0Idx) = otp_ctrl_macro_pkg::cmd_e'(2'b10); + Secret1Idx: force `BUF_PART_OTP_CMD_PATH(Secret1Idx) = otp_ctrl_macro_pkg::cmd_e'(2'b10); + Secret2Idx: force `BUF_PART_OTP_CMD_PATH(Secret2Idx) = otp_ctrl_macro_pkg::cmd_e'(2'b10); + Secret3Idx: force `BUF_PART_OTP_CMD_PATH(Secret3Idx) = otp_ctrl_macro_pkg::cmd_e'(2'b10); + LifeCycleIdx: force `LC_PART_OTP_CMD_PATH = otp_ctrl_macro_pkg::cmd_e'(2'b10); + default: begin + `uvm_fatal("otp_ctrl_if", + $sformatf("force invalid otp_cmd_o only supports buffered partitions: %0d", part_idx)) + end + endcase + endtask + + task automatic release_invalid_part_cmd_o(int part_idx); + @(posedge clk_i); + case (part_idx) + HwCfg0Idx: release `BUF_PART_OTP_CMD_PATH(HwCfg0Idx); + HwCfg1Idx: release `BUF_PART_OTP_CMD_PATH(HwCfg1Idx); + Secret0Idx: release `BUF_PART_OTP_CMD_PATH(Secret0Idx); + Secret1Idx: release `BUF_PART_OTP_CMD_PATH(Secret1Idx); + Secret2Idx: release `BUF_PART_OTP_CMD_PATH(Secret2Idx); + Secret3Idx: release `BUF_PART_OTP_CMD_PATH(Secret3Idx); + LifeCycleIdx: release `LC_PART_OTP_CMD_PATH; + default: begin + `uvm_fatal("otp_ctrl_if", + $sformatf("release invalid otp_cmd_o only supports buffered partitions: %0d", + part_idx)) + end + endcase + endtask + + // This task forces otp_ctrl's internal mubi signals to values that are not mubi::true or mubi:: + // false. Then scb will check if design treats these values as locking the partition access. + task automatic force_part_access_mubi(otp_part_access_lock_t forced_part_access_sel[NumPart-1]); + @(posedge clk_i); + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(VendorTestIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(CreatorSwCfgIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(OwnerSwCfgIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(OwnershipSlotStateIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(RotCreatorAuthIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(RotOwnerAuthSlot0Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(RotOwnerAuthSlot1Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(PlatIntegAuthSlot0Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(PlatIntegAuthSlot1Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(PlatOwnerAuthSlot0Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(PlatOwnerAuthSlot1Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(PlatOwnerAuthSlot2Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(PlatOwnerAuthSlot3Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(ExtNvmIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(RomPatchIdx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(HwCfg0Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(HwCfg1Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(Secret0Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(Secret1Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(Secret2Idx) + `FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL(Secret3Idx) + endtask + + task automatic release_part_access_mubi(); + @(posedge clk_i); + release tb.dut.part_access; + release tb.dut.part_access_dai; + endtask + + // Connectivity assertions for test related I/Os. +// `ASSERT(LcOtpTestStatusO_A, otp_vendor_test_status_o == `PRIM_GENERIC_OTP_PATH.test_status_o) +// `ASSERT(LcOtpTestCtrlI_A, otp_vendor_test_ctrl_i == `PRIM_GENERIC_OTP_PATH.test_ctrl_i) + +// `ASSERT(CioTestOWithDftOn_A, lc_dft_en_i == lc_ctrl_pkg::On |-> +// ##[2:3] cio_test_o == `PRIM_GENERIC_OTP_PATH.test_vect_o) + `ASSERT(CioTestOWithDftOff_A, lc_dft_en_i != lc_ctrl_pkg::On |-> ##[2:3] cio_test_o == 0) + `ASSERT(CioTestEnOWithDftOn_A, lc_dft_en_i == lc_ctrl_pkg::On |-> ##[2:3] cio_test_en_o == '1) + `ASSERT(CioTestEnOWithDftOff_A, lc_dft_en_i != lc_ctrl_pkg::On |-> ##[2:3] cio_test_en_o == 0) + + + `define OTP_ASSERT_WO_LC_ESC(NAME, SEQ) \ + `ASSERT(NAME, SEQ, clk_i, !rst_ni || lc_esc_on || alert_reqs) + + // If pwr_otp_idle is set only if pwr_otp init is done + `OTP_ASSERT_WO_LC_ESC(OtpPwrDoneWhenIdle_A, pwr_otp_idle_o |-> pwr_otp_done_o) + + // otp_broadcast_o is valid only when otp init is done + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgValidOn_A, pwr_otp_done_o |-> + otp_broadcast_o.valid == lc_ctrl_pkg::On) + // If otp_broadcast is Off, then hw partition is not finished calculation, + // then otp init is not done + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgValidOff_A, otp_broadcast_o.valid == lc_ctrl_pkg::Off |-> + pwr_otp_done_o == 0) + // Once OTP init is done, otp_broadcast_o output value stays stable until next power cycle + `OTP_ASSERT_WO_LC_ESC(OtpHwCfgStable_A, otp_broadcast_o.valid == lc_ctrl_pkg::On |=> + $stable(otp_broadcast_o)) + + // Otp_keymgr valid is related to part_digest, should not be changed after otp_pwr_init + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable0_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_root_key_share0_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable1_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_root_key_share1_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable2_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.creator_seed_valid)) + `OTP_ASSERT_WO_LC_ESC(OtpKeymgrValidStable3_A, pwr_otp_done_o |-> + $stable(keymgr_key_o.owner_seed_valid)) + + // During lc_prog_req, either otp_idle will be reset or lc_error is set + `OTP_ASSERT_WO_LC_ESC(LcProgReq_A, $rose(lc_prog_req) |=> + (pwr_otp_idle_o == 0 || $rose(lc_prog_err)) within lc_prog_req[*1:$]) + + // During fatal alert, check if otp outputs revert back to default value. + // Wait three clock cycles until error propagates to each FSM states and regs. + `define OTP_FATAL_ERR_ASSERT(NAME, SEQ) \ + `ASSERT(FatalErr``NAME``, alert_reqs |-> ##3 SEQ) + + `OTP_FATAL_ERR_ASSERT(LcDataValid_A, lc_data_o.valid == 0 && lc_data_o.error == 1) + `OTP_FATAL_ERR_ASSERT(LcDataState_A, lc_data_o.state == + PartInvDefault[LcStateOffset*8+:LcStateSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataCount_A, lc_data_o.count == + PartInvDefault[LcTransitionCntOffset*8+:LcTransitionCntSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataTestUnlockToken_A, lc_data_o.test_unlock_token == + PartInvDefault[TestUnlockTokenOffset*8+:TestUnlockTokenSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataTestExitToken_A, lc_data_o.test_exit_token == + PartInvDefault[TestExitTokenOffset*8+:TestExitTokenSize*8]) + `OTP_FATAL_ERR_ASSERT(LcDataRmaToken_A, lc_data_o.rma_token == + PartInvDefault[RmaTokenOffset*8+:RmaTokenSize*8]) + + `OTP_FATAL_ERR_ASSERT(KeymgrKeyData_A, keymgr_key_o.creator_root_key_share0 == + PartInvDefault[CreatorRootKeyShare0Offset*8+:CreatorRootKeyShare0Size*8] && + keymgr_key_o.creator_root_key_share1 == + PartInvDefault[CreatorRootKeyShare1Offset*8+:CreatorRootKeyShare1Size*8]) + + `OTP_FATAL_ERR_ASSERT(HwCfgOValid_A, otp_broadcast_o.valid == lc_ctrl_pkg::Off) + `OTP_FATAL_ERR_ASSERT(HwCfg0OData_A, otp_broadcast_o.hw_cfg0_data == + PartInvDefault[HwCfg0Offset*8+:HwCfg0Size*8]) + `OTP_FATAL_ERR_ASSERT(HwCfg1OData_A, otp_broadcast_o.hw_cfg1_data == + PartInvDefault[HwCfg1Offset*8+:HwCfg1Size*8]) + + `OTP_FATAL_ERR_ASSERT(LcProgAck_A, lc_prog_ack == 0) + `OTP_FATAL_ERR_ASSERT(SramAcks_A, sram_acks == 0) + `OTP_FATAL_ERR_ASSERT(OtbnAck_A, otbn_ack == 0) + + `undef OTP_ASSERT_WO_LC_ESC + `undef OTP_FATAL_ERR_ASSERT + `undef ECC_REG_PATH + `undef BUF_PART_OTP_CMD_PATH + `undef LC_PART_OTP_CMD_PATH + `undef PRIM_GENERIC_OTP_PATH + `undef PRIM_GENERIC_OTP_CMD_I_PATH + `undef FORCE_OTP_PART_LOCK_WITH_RAND_NON_MUBI_VAL +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_mem_bkdr_util.core b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_mem_bkdr_util.core new file mode 100644 index 00000000000..591c54a83d9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_mem_bkdr_util.core @@ -0,0 +1,23 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:otp_ctrl_mem_bkdr_util:0.1 +description: "OTP_CTRL mem_bkdr_util support package" + +filesets: + files_dv: + depend: + - lowrisc:dv:mem_bkdr_util + - lowrisc:dv:crypto_dpi_present + - lowrisc:dv:lc_ctrl_dv_utils + - lowrisc:darjeeling_no_ibex_ip:otp_ctrl_top_specific_pkg:1.0 + files: + - otp_scrambler_pkg.sv + - otp_ctrl_mem_bkdr_util_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_mem_bkdr_util_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_mem_bkdr_util_pkg.sv new file mode 100644 index 00000000000..4264ae32fb2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_mem_bkdr_util_pkg.sv @@ -0,0 +1,298 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This package has functions that perform mem_bkdr_util accesses to different partitions in OTP. +// These functions end up performing reads and writes to the underlying simulated otp memory, so +// the functions must get a handle to the mem_bkdr_util instance for otp_ctrl as an argument. +// +// NB: this package is only suitable for top-level environments since it depends on SKU-dependent +// OTP ctrl fields. + +package otp_ctrl_mem_bkdr_util_pkg; + + import otp_ctrl_part_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_scrambler_pkg::*; + + function automatic void otp_write_lc_partition_state( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h, + lc_ctrl_state_pkg::lc_state_e lc_state + ); + for (int i = 0; i < LcStateSize; i += 4) begin + mem_bkdr_util_h.write32(i + LcStateOffset, lc_state[i*8+:32]); + end + endfunction : otp_write_lc_partition_state + + function automatic lc_ctrl_state_pkg::lc_state_e otp_read_lc_partition_state( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h + ); + lc_ctrl_state_pkg::lc_state_e lc_state; + for (int i = 0; i < LcStateSize; i += 4) begin + lc_state[i*8 +: 32] = mem_bkdr_util_h.read32(i + LcStateOffset); + end + + return lc_state; + endfunction : otp_read_lc_partition_state + + function automatic void otp_write_lc_partition_cnt( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h, + lc_ctrl_state_pkg::lc_cnt_e lc_cnt + ); + for (int i = 0; i < LcTransitionCntSize; i += 4) begin + mem_bkdr_util_h.write32(i + LcTransitionCntOffset, lc_cnt[i*8+:32]); + end + endfunction : otp_write_lc_partition_cnt + + function automatic void otp_write_lc_partition(mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h, + lc_ctrl_state_pkg::lc_cnt_e lc_cnt, + lc_ctrl_state_pkg::lc_state_e lc_state); + + otp_write_lc_partition_cnt(mem_bkdr_util_h, lc_cnt); + otp_write_lc_partition_state(mem_bkdr_util_h, lc_state); + endfunction : otp_write_lc_partition + + // The following steps are needed to backdoor write a non-secret partition: + // 1). Backdoor write the input data to OTP memory. + // 2). Calculate the correct digest for the secret partition. + // 3). Backdoor write digest data to OTP memory. + + // The following steps are needed to backdoor write a secret partition: + // 1). Scramble the RAW input data. + // 2). Backdoor write the scrambled input data to OTP memory. + // 3). Calculate the correct digest for the secret partition. + // 4). Backdoor write digest data to OTP memory. + + // The HW_CFG1 partition needs to be a special case since it has items + // smaller than 4 bytes and need to be concatenated. To make sure + // this special case won't end up broken if the OTP layout changes + // beyond what this supports the following checks are in place and + // will cause a failure. + // - No other partition except for HW_CFG1 has such small items. + // - The small items in HW_CFG1 will be contained within 32 bits. + + function automatic void otp_write_hw_cfg0_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h, + bit [DeviceIdSize*8-1:0] device_id, + bit [ManufStateSize*8-1:0] manuf_state + ); + bit [HwCfg0DigestSize*8-1:0] digest; + bit [bus_params_pkg::BUS_DW-1:0] partition_data[$]; + + for (int i = 0; i < DeviceIdSize; i += 4) begin + mem_bkdr_util_h.write32(i + DeviceIdOffset, device_id[i*8+:32]); + end + for (int i = 0; i < ManufStateSize; i += 4) begin + mem_bkdr_util_h.write32(i + ManufStateOffset, manuf_state[i*8+:32]); + end + + partition_data = {<<32{ + manuf_state, + device_id + }}; + digest = cal_digest(HwCfg0Idx, partition_data); + mem_bkdr_util_h.write64(HwCfg0DigestOffset, digest); + endfunction + + function automatic void otp_write_hw_cfg1_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h, + bit [SocDbgStateSize*8-1:0] soc_dbg_state, + bit [EnCsrngSwAppReadSize*8-1:0] en_csrng_sw_app_read, + bit [EnSramIfetchSize*8-1:0] en_sram_ifetch + ); + bit [HwCfg1DigestSize*8-1:0] digest; + bit [bus_params_pkg::BUS_DW-1:0] partition_data[$]; + bit [bus_params_pkg::BUS_DW-1:0] concat_data[$]; + bit [31:0] word; + + for (int i = 0; i < SocDbgStateSize; i += 4) begin + mem_bkdr_util_h.write32(i + SocDbgStateOffset, soc_dbg_state[i*8+:32]); + concat_data.push_front(soc_dbg_state[i*8+:32]); + end + word = { + en_sram_ifetch, + en_csrng_sw_app_read + }; + mem_bkdr_util_h.write32(1 + EnCsrngSwAppReadOffset, word); + concat_data.push_front(word); + + partition_data = {<<32{concat_data}}; + digest = cal_digest(HwCfg1Idx, partition_data); + mem_bkdr_util_h.write64(HwCfg1DigestOffset, digest); + endfunction + + function automatic void otp_write_secret0_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h, + bit [TestUnlockTokenSize*8-1:0] test_unlock_token, + bit [TestExitTokenSize*8-1:0] test_exit_token + ); + bit [Secret0DigestSize*8-1:0] digest; + bit [bus_params_pkg::BUS_DW-1:0] partition_data[$]; + bit [TestUnlockTokenSize*8-1:0] scrambled_test_unlock_token; + bit [TestExitTokenSize*8-1:0] scrambled_test_exit_token; + + for (int i = 0; i < TestUnlockTokenSize; i += 8) begin + scrambled_test_unlock_token[i*8+:64] = scramble_data( + test_unlock_token[i*8+:64], Secret0Idx); + mem_bkdr_util_h.write64(i + TestUnlockTokenOffset, + scrambled_test_unlock_token[i*8+:64]); + end + for (int i = 0; i < TestExitTokenSize; i += 8) begin + scrambled_test_exit_token[i*8+:64] = scramble_data( + test_exit_token[i*8+:64], Secret0Idx); + mem_bkdr_util_h.write64(i + TestExitTokenOffset, + scrambled_test_exit_token[i*8+:64]); + end + + partition_data = {<<32{ + scrambled_test_exit_token, + scrambled_test_unlock_token + }}; + digest = cal_digest(Secret0Idx, partition_data); + mem_bkdr_util_h.write64(Secret0DigestOffset, digest); + endfunction + + function automatic void otp_write_secret1_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h, + bit [SramDataKeySeedSize*8-1:0] sram_data_key_seed + ); + bit [Secret1DigestSize*8-1:0] digest; + bit [bus_params_pkg::BUS_DW-1:0] partition_data[$]; + bit [SramDataKeySeedSize*8-1:0] scrambled_sram_data_key_seed; + + for (int i = 0; i < SramDataKeySeedSize; i += 8) begin + scrambled_sram_data_key_seed[i*8+:64] = scramble_data( + sram_data_key_seed[i*8+:64], Secret1Idx); + mem_bkdr_util_h.write64(i + SramDataKeySeedOffset, + scrambled_sram_data_key_seed[i*8+:64]); + end + + partition_data = {<<32{ + scrambled_sram_data_key_seed + }}; + digest = cal_digest(Secret1Idx, partition_data); + mem_bkdr_util_h.write64(Secret1DigestOffset, digest); + endfunction + + function automatic void otp_write_secret2_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h, + bit [RmaTokenSize*8-1:0] rma_token, + bit [CreatorRootKeyShare0Size*8-1:0] creator_root_key_share0, + bit [CreatorRootKeyShare1Size*8-1:0] creator_root_key_share1, + bit [CreatorSeedSize*8-1:0] creator_seed + ); + bit [Secret2DigestSize*8-1:0] digest; + bit [bus_params_pkg::BUS_DW-1:0] partition_data[$]; + bit [RmaTokenSize*8-1:0] scrambled_rma_token; + bit [CreatorRootKeyShare0Size*8-1:0] scrambled_creator_root_key_share0; + bit [CreatorRootKeyShare1Size*8-1:0] scrambled_creator_root_key_share1; + bit [CreatorSeedSize*8-1:0] scrambled_creator_seed; + + for (int i = 0; i < RmaTokenSize; i += 8) begin + scrambled_rma_token[i*8+:64] = scramble_data( + rma_token[i*8+:64], Secret2Idx); + mem_bkdr_util_h.write64(i + RmaTokenOffset, + scrambled_rma_token[i*8+:64]); + end + for (int i = 0; i < CreatorRootKeyShare0Size; i += 8) begin + scrambled_creator_root_key_share0[i*8+:64] = scramble_data( + creator_root_key_share0[i*8+:64], Secret2Idx); + mem_bkdr_util_h.write64(i + CreatorRootKeyShare0Offset, + scrambled_creator_root_key_share0[i*8+:64]); + end + for (int i = 0; i < CreatorRootKeyShare1Size; i += 8) begin + scrambled_creator_root_key_share1[i*8+:64] = scramble_data( + creator_root_key_share1[i*8+:64], Secret2Idx); + mem_bkdr_util_h.write64(i + CreatorRootKeyShare1Offset, + scrambled_creator_root_key_share1[i*8+:64]); + end + for (int i = 0; i < CreatorSeedSize; i += 8) begin + scrambled_creator_seed[i*8+:64] = scramble_data( + creator_seed[i*8+:64], Secret2Idx); + mem_bkdr_util_h.write64(i + CreatorSeedOffset, + scrambled_creator_seed[i*8+:64]); + end + + partition_data = {<<32{ + scrambled_creator_seed, + scrambled_creator_root_key_share1, + scrambled_creator_root_key_share0, + scrambled_rma_token + }}; + digest = cal_digest(Secret2Idx, partition_data); + mem_bkdr_util_h.write64(Secret2DigestOffset, digest); + endfunction + + function automatic void otp_write_secret3_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h, + bit [OwnerSeedSize*8-1:0] owner_seed + ); + bit [Secret3DigestSize*8-1:0] digest; + bit [bus_params_pkg::BUS_DW-1:0] partition_data[$]; + bit [OwnerSeedSize*8-1:0] scrambled_owner_seed; + + for (int i = 0; i < OwnerSeedSize; i += 8) begin + scrambled_owner_seed[i*8+:64] = scramble_data( + owner_seed[i*8+:64], Secret3Idx); + mem_bkdr_util_h.write64(i + OwnerSeedOffset, + scrambled_owner_seed[i*8+:64]); + end + + partition_data = {<<32{ + scrambled_owner_seed + }}; + digest = cal_digest(Secret3Idx, partition_data); + mem_bkdr_util_h.write64(Secret3DigestOffset, digest); + endfunction + + // Functions that clear the provisioning state of the buffered partitions. + // This is useful in tests that make front-door accesses for provisioning purposes. + function automatic void otp_clear_hw_cfg0_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h + ); + for (int i = 0; i < HwCfg0Size; i += 4) begin + mem_bkdr_util_h.write32(i + HwCfg0Offset, 32'h0); + end + endfunction + + function automatic void otp_clear_hw_cfg1_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h + ); + for (int i = 0; i < HwCfg1Size; i += 4) begin + mem_bkdr_util_h.write32(i + HwCfg1Offset, 32'h0); + end + endfunction + + function automatic void otp_clear_secret0_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h + ); + for (int i = 0; i < Secret0Size; i += 4) begin + mem_bkdr_util_h.write32(i + Secret0Offset, 32'h0); + end + endfunction + + function automatic void otp_clear_secret1_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h + ); + for (int i = 0; i < Secret1Size; i += 4) begin + mem_bkdr_util_h.write32(i + Secret1Offset, 32'h0); + end + endfunction + + function automatic void otp_clear_secret2_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h + ); + for (int i = 0; i < Secret2Size; i += 4) begin + mem_bkdr_util_h.write32(i + Secret2Offset, 32'h0); + end + endfunction + + function automatic void otp_clear_secret3_partition( + mem_bkdr_util_pkg::mem_bkdr_util mem_bkdr_util_h + ); + for (int i = 0; i < Secret3Size; i += 4) begin + mem_bkdr_util_h.write32(i + Secret3Offset, 32'h0); + end + endfunction + +endpackage : otp_ctrl_mem_bkdr_util_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv new file mode 100644 index 00000000000..f1b6542017d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_scoreboard.sv @@ -0,0 +1,2053 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +class otp_ctrl_scoreboard #(type CFG_T = otp_ctrl_env_cfg) + extends cip_base_scoreboard #( + .CFG_T(CFG_T), + .RAL_T(otp_ctrl_core_reg_block), + .COV_T(otp_ctrl_env_cov) + ); + `uvm_component_param_utils(otp_ctrl_scoreboard #(CFG_T)) + + // local variables + bit [TL_DW-1:0] otp_a [OTP_ARRAY_SIZE]; + + // lc_state and lc_cnt that stored in OTP + bit [LC_PROG_DATA_SIZE-1:0] otp_lc_data; + bit [EDN_BUS_WIDTH-1:0] edn_data_q[$]; + + // This flag is used when reset is issued during otp dai write access. + bit dai_wr_ip; + int dai_digest_ip = LifeCycleIdx; // Default to LC as it does not have digest. + bit ignore_digest_chk = 0; + + // This bit is used for DAI interface to mark if the read access is valid. + bit dai_read_valid; + + // This captures the regwen state as configured by the SW side (i.e. without HW modulation + // with the idle signal overlaid). + bit direct_access_regwen_state = 1; + + // ICEBOX(#17798): currently scb will skip checking the readout value if the ECC error is + // uncorrectable. Because if the error is uncorrectable, current scb does not track all the + // backdoor injected values. + // This issue proposes to track the otp_memory_array in mem_bkdr_if and once backdoor inject any + // value, mem_bkdr_if will update its otp_memory_array. + bit check_dai_rd_data = 1; + + // Status related variables + bit under_chk, under_dai_access; + bit [TL_DW-1:0] exp_status, status_mask; + + otp_alert_e exp_alert = OtpNoAlert; + + // TLM agent fifos + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(SRAM_DATA_SIZE))) + sram_fifos[NumSramKeyReqSlots]; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE))) otbn_fifo; + uvm_tlm_analysis_fifo #(push_pull_item#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE))) + lc_prog_fifo; + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + sram_fifos[i] = new($sformatf("sram_fifos[%0d]", i), this); + end + otbn_fifo = new("otbn_fifo", this); + lc_prog_fifo = new("lc_prog_fifo", this); + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + fork + process_wipe_mem(); + process_otp_power_up(); + process_lc_esc(); + process_lc_prog_req(); + process_edn_req(); + check_otbn_rsp(); + check_sram_rsps(); + recover_lc_prog_req(); + join_none + endtask + + // Once sequence uses backdoor method to clear memory, this task resets internal otp_a and + // resets `cfg.backdoor_clear_mem` to 0. + virtual task process_wipe_mem(); + forever begin + @(posedge cfg.backdoor_clear_mem) begin + bit [SCRAMBLE_DATA_SIZE-1:0] data; + otp_a = '{default:0}; + otp_lc_data = '{default:0}; + // secret partitions have been scrambled before writing to OTP. + // here calculate the pre-scrambled raw data when clearing internal OTP to all 0s. + data = descramble_data(0, Secret0Idx); + for (int i = Secret0Offset / TL_SIZE; + i <= Secret0DigestOffset / TL_SIZE - 1; + i++) begin + otp_a[i] = ((i - Secret0Offset / TL_SIZE) % 2) ? + data[SCRAMBLE_DATA_SIZE-1:TL_DW] : data[TL_DW-1:0]; + end + // secret partitions have been scrambled before writing to OTP. + // here calculate the pre-scrambled raw data when clearing internal OTP to all 0s. + data = descramble_data(0, Secret1Idx); + for (int i = Secret1Offset / TL_SIZE; + i <= Secret1DigestOffset / TL_SIZE - 1; + i++) begin + otp_a[i] = ((i - Secret1Offset / TL_SIZE) % 2) ? + data[SCRAMBLE_DATA_SIZE-1:TL_DW] : data[TL_DW-1:0]; + end + // secret partitions have been scrambled before writing to OTP. + // here calculate the pre-scrambled raw data when clearing internal OTP to all 0s. + data = descramble_data(0, Secret2Idx); + for (int i = Secret2Offset / TL_SIZE; + i <= Secret2DigestOffset / TL_SIZE - 1; + i++) begin + otp_a[i] = ((i - Secret2Offset / TL_SIZE) % 2) ? + data[SCRAMBLE_DATA_SIZE-1:TL_DW] : data[TL_DW-1:0]; + end + // secret partitions have been scrambled before writing to OTP. + // here calculate the pre-scrambled raw data when clearing internal OTP to all 0s. + data = descramble_data(0, Secret3Idx); + for (int i = Secret3Offset / TL_SIZE; + i <= Secret3DigestOffset / TL_SIZE - 1; + i++) begin + otp_a[i] = ((i - Secret3Offset / TL_SIZE) % 2) ? + data[SCRAMBLE_DATA_SIZE-1:TL_DW] : data[TL_DW-1:0]; + end + `uvm_info(`gfn, "clear internal memory and digest", UVM_HIGH) + cfg.backdoor_clear_mem = 0; + dai_wr_ip = 0; + dai_digest_ip = LifeCycleIdx; + end + end + endtask + + // This task process the following logic in during otp_power_up: + // 1. After reset deasserted, otp access is locked until pwr_otp_done_o is set + // 2. After reset deasserted, if power otp_init request is on, and if testbench uses backdoor to + // clear OTP memory to all zeros, clear all digests and re-calculate secret partitions + virtual task process_otp_power_up(); + forever begin + wait (cfg.en_scb); + @(posedge cfg.otp_ctrl_vif.pwr_otp_done_o || cfg.under_reset || + cfg.otp_ctrl_vif.alert_reqs) begin + if (!cfg.under_reset && !cfg.otp_ctrl_vif.alert_reqs && cfg.en_scb) begin + otp_ctrl_part_pkg::otp_hw_cfg0_data_t exp_hw_cfg0_data; + otp_ctrl_part_pkg::otp_hw_cfg1_data_t exp_hw_cfg1_data; + otp_ctrl_pkg::otp_keymgr_key_t exp_keymgr_data; + otp_ctrl_pkg::otp_lc_data_t exp_lc_data; + bit [otp_ctrl_pkg::KeyMgrKeyWidth-1:0] exp_keymgr_key0, exp_keymgr_key1; + + if (PartInfo[dai_digest_ip].sw_digest || PartInfo[dai_digest_ip].hw_digest) begin + bit [TL_DW-1:0] otp_addr = PART_OTP_DIGEST_ADDRS[dai_digest_ip]; + otp_a[otp_addr] = cfg.mem_bkdr_util_h.read32(otp_addr << 2); + otp_a[otp_addr+1] = cfg.mem_bkdr_util_h.read32((otp_addr << 2) + 4); + dai_digest_ip = LifeCycleIdx; + end + predict_digest_csrs(); + + if (cfg.otp_ctrl_vif.under_error_states() == 0) begin + // Dai access is unlocked because the power init is done + void'(ral.direct_access_regwen.predict(direct_access_regwen_state)); + + // Dai idle is set because the otp init is done + exp_status[OtpDaiIdleIdx] = 1; + end + + // Hwcfg_o gets data from OTP HW cfg partition + exp_hw_cfg0_data = cfg.otp_ctrl_vif.under_error_states() ? + otp_ctrl_part_pkg::PartInvDefault[HwCfg0Offset*8 +: HwCfg0Size*8] : + otp_hw_cfg0_data_t'({<<32 {otp_a[HwCfg0Offset/4 +: HwCfg0Size/4]}}); + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.valid, lc_ctrl_pkg::On) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.hw_cfg0_data, exp_hw_cfg0_data) + + // Hwcfg_o gets data from OTP HW cfg partition + exp_hw_cfg1_data = cfg.otp_ctrl_vif.under_error_states() ? + otp_ctrl_part_pkg::PartInvDefault[HwCfg1Offset*8 +: HwCfg1Size*8] : + otp_hw_cfg1_data_t'({<<32 {otp_a[HwCfg1Offset/4 +: HwCfg1Size/4]}}); + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.valid, lc_ctrl_pkg::On) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.otp_broadcast_o.hw_cfg1_data, exp_hw_cfg1_data) + + if (!cfg.otp_ctrl_vif.under_error_states()) begin + // ---------------------- Check lc_data_o output ----------------------------------- + // Because initialization was successful, the valid should be set and error should be + // reset. + exp_lc_data.valid = 1; + exp_lc_data.error = 0; + + // Secrets and tokens valid signals are depend on whether secret partitions are + // locked. + exp_lc_data.secrets_valid = get_otp_digest_val(Secret2Idx) ? On : Off; + exp_lc_data.test_tokens_valid = get_otp_digest_val(Secret0Idx) ? On : Off; + exp_lc_data.rma_token_valid = get_otp_digest_val(Secret2Idx) ? On : Off; + + // LC output is depend on LC partitions value. + exp_lc_data.count = otp_lc_data[0 +: LcCountWidth]; + exp_lc_data.state = otp_lc_data[LcCountWidth +: LcStateWidth]; + + // Token values are depend on secret partitions value. + exp_lc_data.test_unlock_token = + {<<32 {otp_a[TestUnlockTokenOffset/4 +: TestUnlockTokenSize/4]}}; + exp_lc_data.test_exit_token = + {<<32 {otp_a[TestExitTokenOffset/4 +: TestExitTokenSize/4]}}; + exp_lc_data.rma_token = {<<32 {otp_a[RmaTokenOffset/4 +: RmaTokenSize/4]}}; + + // Check otp_lc_data_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.valid, exp_lc_data.valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.error, exp_lc_data.error) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.state, exp_lc_data.state) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.count, exp_lc_data.count) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.secrets_valid, exp_lc_data.secrets_valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.test_tokens_valid, + exp_lc_data.test_tokens_valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.test_unlock_token, + exp_lc_data.test_unlock_token) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.test_exit_token, exp_lc_data.test_exit_token) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.rma_token_valid, exp_lc_data.rma_token_valid) + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o.rma_token, exp_lc_data.rma_token) + + // Check otp_lc_data_t all together in case there is any missed item. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.lc_data_o, exp_lc_data) + + // ---------------------- Check keymgr_key_o output --------------------------------- + // Otp_keymgr outputs creator and owner keys from secret partitions. + // Depends on lc_seed_hw_rd_en_i, it will output the real keys or a constant + exp_keymgr_data = '0; + exp_keymgr_data.creator_root_key_share0_valid = get_otp_digest_val(Secret2Idx) != 0; + if (cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On) begin + exp_keymgr_data.creator_root_key_share0 = + {<<32 {otp_a[CreatorRootKeyShare0Offset/4 +: CreatorRootKeyShare0Size/4]}}; + end else begin + exp_keymgr_data.creator_root_key_share0 = + PartInvDefault[CreatorRootKeyShare0Offset*8 +: CreatorRootKeyShare0Size*8]; + end + // Check otp_keymgr_key_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o.creator_root_key_share0_valid, + exp_keymgr_data.creator_root_key_share0_valid) + exp_keymgr_data.creator_root_key_share1_valid = get_otp_digest_val(Secret2Idx) != 0; + if (cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On) begin + exp_keymgr_data.creator_root_key_share1 = + {<<32 {otp_a[CreatorRootKeyShare1Offset/4 +: CreatorRootKeyShare1Size/4]}}; + end else begin + exp_keymgr_data.creator_root_key_share1 = + PartInvDefault[CreatorRootKeyShare1Offset*8 +: CreatorRootKeyShare1Size*8]; + end + // Check otp_keymgr_key_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o.creator_root_key_share1_valid, + exp_keymgr_data.creator_root_key_share1_valid) + exp_keymgr_data.creator_seed_valid = get_otp_digest_val(Secret2Idx) != 0; + if (cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On) begin + exp_keymgr_data.creator_seed = + {<<32 {otp_a[CreatorSeedOffset/4 +: CreatorSeedSize/4]}}; + end else begin + exp_keymgr_data.creator_seed = + PartInvDefault[CreatorSeedOffset*8 +: CreatorSeedSize*8]; + end + // Check otp_keymgr_key_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o.creator_seed_valid, + exp_keymgr_data.creator_seed_valid) + exp_keymgr_data.owner_seed_valid = get_otp_digest_val(Secret3Idx) != 0; + if (cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On) begin + exp_keymgr_data.owner_seed = + {<<32 {otp_a[OwnerSeedOffset/4 +: OwnerSeedSize/4]}}; + end else begin + exp_keymgr_data.owner_seed = + PartInvDefault[OwnerSeedOffset*8 +: OwnerSeedSize*8]; + end + // Check otp_keymgr_key_t struct by item is easier to debug. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o.owner_seed_valid, + exp_keymgr_data.owner_seed_valid) + + // Check otp_keymgr_key_t struct all together in case there is any missed item. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.keymgr_key_o, exp_keymgr_data) + + if (cfg.en_cov) begin + cov.keymgr_o_cg.sample(cfg.otp_ctrl_vif.lc_seed_hw_rd_en_i == lc_ctrl_pkg::On, + exp_keymgr_data.creator_root_key_share0_valid); + end + end + end else if (cfg.otp_ctrl_vif.alert_reqs) begin + // Ignore digest CSR check when otp_ctrl initialization is interrupted by fatal errors. + // SCB cannot predict how many partitions already finished initialization and updated + // the digest value to CSRs. + ignore_digest_chk = 1; + end + if (cfg.en_cov) begin + bit [NumPart-2:0] parts_locked; + foreach (parts_locked[i]) parts_locked[i] = (get_otp_digest_val(i) != 0); + cov.power_on_cg.sample(cfg.otp_ctrl_vif.lc_esc_on, parts_locked); + end + end + end + endtask + + // This task monitors internal escalation triggered by two methods: + // 1. Externally lc_escalation_en is set to lc_ctrl_pkg::On. + // 2. Internal fatal alert triggered and all partitions are driven to error states. + virtual task process_lc_esc(); + forever begin + wait(cfg.otp_ctrl_vif.alert_reqs == 1 && cfg.en_scb); + + if (cfg.otp_ctrl_vif.lc_esc_on == 0) `DV_CHECK_NE(exp_alert, OtpNoAlert) + + if (exp_alert != OtpCheckAlert) set_exp_alert("fatal_check_error", 1, 5); + + // If the lc_escalation is triggered by internal fatal alert, wait 2 negedge until status is + // updated internally + if (cfg.otp_ctrl_vif.lc_esc_on == 0) begin + cfg.clk_rst_vif.wait_n_clks(2); + exp_status[OtpCheckPendingIdx] = 0; + exp_status[OtpDaiIdleIdx] = 0; + end else begin + exp_status = '0; + // Only lc_esc_on will set these bits to 1. + exp_status[OtpDerivKeyFsmErrIdx:OtpLfsrFsmErrIdx] = '1; + end + + // Update status bits. + foreach (FATAL_EXP_STATUS[i]) begin + if (FATAL_EXP_STATUS[i]) begin + predict_err(.status_err_idx(otp_status_e'(i)), .err_code(OtpFsmStateError), + .update_esc_err(1)); + end + end + + // Update digest values and direct_access_regwen. + predict_rdata(1, 0, 0); + void'(ral.direct_access_regwen.predict(.value(0), .kind(UVM_PREDICT_READ))); + + // DAI access is locked until reset, so no need to backdoor read otp write value until reset. + + wait(cfg.otp_ctrl_vif.alert_reqs == 0); + end + endtask + + // This task monitors if lc_program req is interrupted by reset. + // If it happens, scb cannot predict how many bits have been written to OTP_CTRL. + // So here we will backdoor read back OTP lc partitions bits. + virtual task recover_lc_prog_req(); + forever begin + wait(cfg.otp_ctrl_vif.lc_prog_req == 1); + wait(cfg.otp_ctrl_vif.lc_prog_req == 0); + // Wait one 1ps to avoid race condition. + #1ps; + if (cfg.otp_ctrl_vif.rst_ni == 0) begin + for (int i = 0; i < LC_PROG_DATA_SIZE/32; i++) begin + otp_lc_data[i*32+:32] = cfg.mem_bkdr_util_h.read32(LifeCycleOffset + i * 4); + end + end + end + endtask + + virtual task process_lc_prog_req(); + forever begin + push_pull_item#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) rcv_item; + bit exp_err_bit; + bit [15:0] rcv_words [LC_PROG_DATA_SIZE/16]; + + lc_prog_fifo.get(rcv_item); + + // LCI is updated by OTP word. + rcv_words = {<< 16{rcv_item.h_data}}; + foreach (rcv_words[i]) begin + bit [15:0] curr_word = otp_lc_data[i*16 +: 16]; + if ((curr_word & rcv_words[i]) == curr_word) otp_lc_data[i*16 +: 16] = rcv_words[i]; + else exp_err_bit = 1; + end + + if (exp_err_bit) predict_err(OtpLciErrIdx, OtpMacroWriteBlankError); + else predict_no_err(OtpLciErrIdx); + + // LC program request data is valid means no OTP macro error. + `DV_CHECK_EQ(rcv_item.d_data, exp_err_bit) + + if (cfg.en_cov) cov.lc_prog_cg.sample(exp_err_bit); + end + endtask + + virtual task process_edn_req(); + forever begin + push_pull_item#(.DeviceDataWidth(EDN_DATA_WIDTH)) edn_item; + edn_fifos[0].get(edn_item); + edn_data_q.push_back(edn_item.d_data[EDN_BUS_WIDTH-1:0]); + end + endtask + + virtual task check_otbn_rsp(); + forever begin + push_pull_item#(.DeviceDataWidth(OTBN_DATA_SIZE)) rcv_item; + bit [SCRAMBLE_KEY_SIZE-1:0] edn_key2, edn_key1; + bit [SCRAMBLE_KEY_SIZE-1:0] sram_key; + bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; + bit [OtbnKeyWidth-1:0] key, exp_key; + bit [OtbnNonceWidth-1:0] nonce, exp_nonce; + bit seed_valid; + bit part_locked; + + otbn_fifo.get(rcv_item); + seed_valid = rcv_item.d_data[0]; + nonce = rcv_item.d_data[1+:OtbnNonceWidth]; + key = rcv_item.d_data[OtbnNonceWidth+1+:OtbnKeyWidth]; + part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; + + // seed is valid as long as secret1 is locked + `DV_CHECK_EQ(seed_valid, part_locked, "otbn seed_valid mismatch") + + // If edn_data_q matches the OTBN requested size, check OTBN outputs + if (edn_data_q.size() == NUM_OTBN_EDN_REQ) begin + {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; + + // check nonce value + `DV_CHECK_EQ(nonce, exp_nonce, "otbn nonce mismatch") + + // calculate key + sram_key = get_key_from_otp(part_locked, SramDataKeySeedOffset / 4); + exp_key_lower = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key1), + .num_round(2)); + + exp_key_higher = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key2), + .num_round(2)); + exp_key = {exp_key_higher, exp_key_lower}; + `DV_CHECK_EQ(key, exp_key, "otbn key mismatch") + + if (cfg.en_cov) cov.otbn_req_cg.sample(part_locked); + + // If during OTBN key request, the LFSR timer expired and trigger an EDN request to acquire + // two EDN keys, then ignore the OTBN output checking, because scb did not know which EDN + // keys are used for LFSR. + // Thus any edn_data_q size equal to (16+2*N) is exempted from checking. + end else if ((edn_data_q.size() - NUM_OTBN_EDN_REQ) % 2 != 0) begin + `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during OTBN request", + edn_data_q.size())) + end + edn_data_q.delete(); + end + endtask + + virtual task check_sram_rsps(); + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + automatic int index = i; + fork + forever begin + push_pull_item#(.DeviceDataWidth(SRAM_DATA_SIZE)) rcv_item; + sram_key_t key, exp_key; + sram_nonce_t nonce, exp_nonce; + bit seed_valid, part_locked; + bit [SCRAMBLE_KEY_SIZE-1:0] edn_key2, edn_key1; + bit [SCRAMBLE_KEY_SIZE-1:0] sram_key; // key used as input to present algo + bit [SCRAMBLE_DATA_SIZE-1:0] exp_key_lower, exp_key_higher; + + sram_fifos[index].get(rcv_item); + seed_valid = rcv_item.d_data[0]; + nonce = rcv_item.d_data[1+:SramNonceWidth]; + key = rcv_item.d_data[SramNonceWidth+1+:SramKeyWidth]; + part_locked = {`gmv(ral.secret1_digest[0]), `gmv(ral.secret1_digest[1])} != '0; + + // seed is valid as long as secret1 is locked + `DV_CHECK_EQ(seed_valid, part_locked, $sformatf("sram_%0d seed_valid mismatch", index)) + + // If edn_data_q matches the OTBN requested size, check OTBN outputs + if (edn_data_q.size() == NUM_SRAM_EDN_REQ) begin + {exp_nonce, edn_key2, edn_key1} = {<<32{edn_data_q}}; + + // check nonce value + `DV_CHECK_EQ(nonce, exp_nonce, $sformatf("sram_%0d nonce mismatch", index)) + + // calculate key + sram_key = get_key_from_otp(part_locked, SramDataKeySeedOffset / 4); + exp_key_lower = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key1), + .num_round(2)); + + exp_key_higher = present_encode_with_final_const( + .data(RndCnstDigestIV[SramDataKey]), + .key(sram_key), + .final_const(RndCnstDigestConst[SramDataKey]), + .second_key(edn_key2), + .num_round(2)); + exp_key = {exp_key_higher, exp_key_lower}; + `DV_CHECK_EQ(key, exp_key, $sformatf("sram_%0d key mismatch", index)) + if (cfg.en_cov) cov.sram_req_cg.sample(index, part_locked); + + end else if ((edn_data_q.size() - NUM_SRAM_EDN_REQ) % 2 != 0) begin + `uvm_error(`gfn, $sformatf("Unexpected edn_data_q size (%0d) during SRAM request", + edn_data_q.size())) + end + edn_data_q.delete(); + end + join_none + end + endtask + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + bit [TL_AW-1:0] addr_mask = ral.get_addr_mask(); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + if (ral_name != "otp_macro_prim_reg_block") begin + process_core_tl_access(item, csr_addr, ral_name, addr_mask, + addr_phase_read, addr_phase_write, data_phase_read, data_phase_write); + end else begin + process_prim_tl_access(item, csr_addr, ral_name, addr_phase_write, data_phase_read); + end + endtask + + virtual function void process_prim_tl_access(tl_seq_item item, uvm_reg_addr_t csr_addr, + string ral_name, bit addr_phase_write, bit data_phase_read); + + uvm_reg csr; + dv_base_reg dv_reg; + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + `downcast(dv_reg, csr) + + if (addr_phase_write) begin + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end else if (data_phase_read) begin + `DV_CHECK_EQ((csr.get_mirrored_value() | status_mask), (item.d_data | status_mask), + $sformatf("reg name: status, compare_mask %0h", status_mask)) + end + endfunction + + virtual function void process_core_tl_access(tl_seq_item item, uvm_reg_addr_t csr_addr, + string ral_name, bit [TL_AW-1:0] addr_mask, bit addr_phase_read, bit addr_phase_write, + bit data_phase_read, bit data_phase_write); + + bit do_read_check = 1; + uvm_reg csr; + dv_base_reg dv_reg; + string csr_name; + + `uvm_info(`gfn, $sformatf("sw state %d, reg state %d", direct_access_regwen_state, + `gmv(ral.direct_access_regwen)), UVM_LOW); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + `downcast(dv_reg, csr) + // SW CFG window + end else if ((csr_addr & addr_mask) inside + {[SW_WINDOW_BASE_ADDR : SW_WINDOW_BASE_ADDR + SW_WINDOW_SIZE]}) begin + if (data_phase_read) begin + bit [TL_AW-1:0] dai_addr = (csr_addr & addr_mask - SW_WINDOW_BASE_ADDR); + bit [TL_AW-1:0] otp_addr = dai_addr >> 2; + int part_idx = get_part_index(dai_addr); + bit [TL_DW-1:0] read_out; + int ecc_err = OtpNoEccErr; + + // We can't get an ECC error if the partition does not have integrity. + if (part_has_integrity(part_idx)) begin + ecc_err = read_a_word_with_ecc(dai_addr, read_out); + end else begin + ecc_err = read_a_word_with_ecc_raw(dai_addr, read_out); + end + + if (part_has_digest(part_idx) && cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[part_idx].sample(.read_lock(0), + .write_lock(get_digest_reg_val(part_idx) != 0), .is_write(0)); + end + + // Any alert that indicates the OTP block is in the final error state should not enter the + // logic here, but gated at `is_tl_mem_access_allowed` function. + `DV_CHECK_EQ(cfg.otp_ctrl_vif.alert_reqs, 0) + + // ECC uncorrectable errors are gated by `is_tl_mem_access_allowed` function. + if (ecc_err != OtpNoEccErr && part_has_integrity(part_idx)) begin + + predict_err(otp_status_e'(part_idx), OtpMacroEccCorrError); + if (ecc_err == OtpEccCorrErr) begin + `DV_CHECK_EQ(item.d_data, otp_a[otp_addr], + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + end else begin + // Only check the first 16 bits because if ECC readout detects uncorrectable error, it + // won't continue read the remaining 16 bits. + `DV_CHECK_EQ(item.d_data & 16'hffff, read_out & 16'hffff, + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + end + // If there is an injected error, but the partition cannot detect it, we have to compare + // to the value read via the backdoor instead of otp_a[otp_addr] since otherwise the + // perturbed value does not get modelled correctly. + end else if (ecc_err != OtpNoEccErr && !part_has_integrity(part_idx)) begin + `DV_CHECK_EQ(item.d_data, read_out, + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + predict_no_err(otp_status_e'(part_idx)); + end else if (ecc_err == OtpNoEccErr) begin + `DV_CHECK_EQ(item.d_data, otp_a[otp_addr], + $sformatf("mem read mismatch at TLUL addr %0h, csr_addr %0h", + csr_addr, dai_addr)) + predict_no_err(otp_status_e'(part_idx)); + end + end + return; + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + csr_name = csr.get_name(); + + if (addr_phase_write) begin + if (cfg.en_cov && cfg.otp_ctrl_vif.alert_reqs && csr_name == "direct_access_cmd") begin + cov.req_dai_access_after_alert_cg.sample(item.a_data); + end + + // Skip predict if the register is locked by `direct_access_regwen`. + // An exception is the direct_access_regwen which may always be written. + if (ral.direct_access_regwen.locks_reg_or_fld(dv_reg) && + `gmv(ral.direct_access_regwen) == 0 && + csr_name != "direct_access_regwen") return; + + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // process the csr req + // for write, update local variable and fifo at address phase + // for read, update prediction at address phase and compare at data phase + case (csr_name) + // add individual case item for each csr + "intr_state": begin + if (data_phase_read) begin + // Disable intr_state checking when lc_program is in progress, because scb cannot + // accurately predict when program_error will be triggered. + // We will check the intr_state after lc_program request is done, and the error bit will + // be checked in the `process_lc_prog_req` task. + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check) do_read_check = 0; + if (do_read_check) begin + bit [TL_DW-1:0] intr_en = `gmv(ral.intr_enable); + bit [NumOtpCtrlIntr-1:0] intr_exp = `gmv(ral.intr_state); + + foreach (intr_exp[i]) begin + otp_intr_e intr = otp_intr_e'(i); + `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[i], (intr_en[i] & intr_exp[i]), + $sformatf("Interrupt_pin: %0s", intr.name)); + if (cfg.en_cov) begin + cov.intr_cg.sample(i, intr_en[i], item.d_data[i]); + cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]); + end + end + end + end + end + "intr_test": begin + if (addr_phase_write) begin + bit [TL_DW-1:0] intr_en = `gmv(ral.intr_enable); + bit [NumOtpCtrlIntr-1:0] intr_exp = `gmv(ral.intr_state) | item.a_data; + + void'(ral.intr_state.predict(.value(intr_exp))); + if (cfg.en_cov) begin + foreach (intr_exp[i]) begin + cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], intr_exp[i]); + end + end + end + end + "direct_access_cmd": begin + if (addr_phase_write && !cfg.otp_ctrl_vif.under_error_states()) begin + // here only normalize to 2 lsb, if is secret, will be reduced further + bit [TL_AW-1:0] dai_addr = normalize_dai_addr(`gmv(ral.direct_access_address)); + int part_idx = get_part_index(dai_addr); + bit sw_read_lock = 0; + void'(ral.direct_access_regwen.predict(0)); + under_dai_access = 1; + + // Check if it is sw partition read lock - this can be used in `DaiRead` branch and also + // coverage collection. + if (part_idx == VendorTestIdx) begin + sw_read_lock = `gmv(ral.vendor_test_read_lock) == 0; + end else if (part_idx == CreatorSwCfgIdx) begin + sw_read_lock = `gmv(ral.creator_sw_cfg_read_lock) == 0; + end else if (part_idx == OwnerSwCfgIdx) begin + sw_read_lock = `gmv(ral.owner_sw_cfg_read_lock) == 0; + end else if (part_idx == OwnershipSlotStateIdx) begin + sw_read_lock = `gmv(ral.ownership_slot_state_read_lock) == 0; + end else if (part_idx == RotCreatorAuthIdx) begin + sw_read_lock = `gmv(ral.rot_creator_auth_read_lock) == 0; + end else if (part_idx == RotOwnerAuthSlot0Idx) begin + sw_read_lock = `gmv(ral.rot_owner_auth_slot0_read_lock) == 0; + end else if (part_idx == RotOwnerAuthSlot1Idx) begin + sw_read_lock = `gmv(ral.rot_owner_auth_slot1_read_lock) == 0; + end else if (part_idx == PlatIntegAuthSlot0Idx) begin + sw_read_lock = `gmv(ral.plat_integ_auth_slot0_read_lock) == 0; + end else if (part_idx == PlatIntegAuthSlot1Idx) begin + sw_read_lock = `gmv(ral.plat_integ_auth_slot1_read_lock) == 0; + end else if (part_idx == PlatOwnerAuthSlot0Idx) begin + sw_read_lock = `gmv(ral.plat_owner_auth_slot0_read_lock) == 0; + end else if (part_idx == PlatOwnerAuthSlot1Idx) begin + sw_read_lock = `gmv(ral.plat_owner_auth_slot1_read_lock) == 0; + end else if (part_idx == PlatOwnerAuthSlot2Idx) begin + sw_read_lock = `gmv(ral.plat_owner_auth_slot2_read_lock) == 0; + end else if (part_idx == PlatOwnerAuthSlot3Idx) begin + sw_read_lock = `gmv(ral.plat_owner_auth_slot3_read_lock) == 0; + end else if (part_idx == ExtNvmIdx) begin + sw_read_lock = `gmv(ral.ext_nvm_read_lock) == 0; + end else if (part_idx == RomPatchIdx) begin + sw_read_lock = `gmv(ral.rom_patch_read_lock) == 0; + end + + // LC partition cannot be access via DAI + if (part_idx == LifeCycleIdx) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + if (item.a_data == DaiRead) predict_rdata(is_secret(dai_addr), 0, 0); + end else begin + // Collect coverage. + if (cfg.en_cov) begin + if (part_idx == Secret2Idx) begin + cov.dai_access_secret2_cg.sample( + !(cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On), + dai_cmd_e'(item.a_data)); + end else if (is_sw_part_idx(part_idx) && part_has_digest(part_idx) && + item.a_data inside {DaiRead, DaiWrite}) begin + cov.unbuf_access_lock_cg_wrap[part_idx].sample(.read_lock(sw_read_lock), + .write_lock(get_digest_reg_val(part_idx) != 0), + .is_write(item.a_data == DaiWrite)); + + end + end + + case (item.a_data) + DaiDigest: cal_digest_val(part_idx); + DaiRead: begin + // Check if it is sw partition read lock + check_dai_rd_data = 1; + + // SW partitions write read_lock_csr can lock read access. + if (sw_read_lock || + // Secret partitions cal digest can also lock read access. + // However, digest is always readable except SW partitions (Issue #5752). + (is_secret(dai_addr) && get_digest_reg_val(part_idx) != 0 && + !is_digest(dai_addr)) || + // If the partition has creator key material and lc_creator_seed_sw_rw is + // disable, then return access error. + (PartInfo[part_idx].iskeymgr_creator && !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), 0, 0); + end else if (sw_read_lock || + // Secret partitions cal digest can also lock read access. + // However, digest is always readable except SW partitions (Issue #5752). + (is_secret(dai_addr) && get_digest_reg_val(part_idx) != 0 && + !is_digest(dai_addr)) || + // If the partition has owner key material and lc_owner_seed_sw_rw is disable, + // then return access error. + (PartInfo[part_idx].iskeymgr_owner && !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_owner_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), 0, 0); + + end else begin + bit [TL_DW-1:0] read_out0, read_out1; + bit [TL_AW-1:0] otp_addr = get_scb_otp_addr(); + int ecc_err = 0; + + // Backdoor read to check if there is any ECC error. + if (part_has_integrity(part_idx)) begin + ecc_err = read_a_word_with_ecc(dai_addr, read_out0); + if (is_secret(dai_addr) || is_digest(dai_addr)) begin + ecc_err = max2(read_a_word_with_ecc(dai_addr + 4, read_out1), ecc_err); + end + end else begin + ecc_err = read_a_word_with_ecc_raw(dai_addr, read_out0); + if (is_secret(dai_addr) || is_digest(dai_addr)) begin + ecc_err = max2(read_a_word_with_ecc_raw(dai_addr + 4, read_out1), ecc_err); + end + end + + if (ecc_err == OtpEccCorrErr && part_has_integrity(part_idx)) begin + predict_err(OtpDaiErrIdx, OtpMacroEccCorrError); + backdoor_update_otp_array(dai_addr); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), + otp_a[otp_addr], otp_a[otp_addr+1]); + end else if (ecc_err == OtpEccUncorrErr && part_has_integrity(part_idx)) begin + predict_err(OtpDaiErrIdx, OtpMacroEccUncorrError); + // Max wait 20 clock cycles because scb did not know when exactly OTP will + // finish reading and reporting the uncorrectable error. + set_exp_alert("fatal_macro_error", 1, 20); + predict_rdata(1, 0, 0); + // Some partitions do not interpret/report ECC errors. In those cases + // we still need to model the read data correctly if it has been perturbed. + end else if (ecc_err inside {OtpEccCorrErr, OtpEccUncorrErr} && + !part_has_integrity(part_idx)) begin + predict_no_err(OtpDaiErrIdx); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), + read_out0, read_out1); + // do not check direct_access_rdata_* on ECC errors in + // non-integrity partitions + check_dai_rd_data = 0; + end else begin + predict_no_err(OtpDaiErrIdx); + predict_rdata(is_secret(dai_addr) || is_digest(dai_addr), + otp_a[otp_addr], otp_a[otp_addr+1]); + end + end + end + DaiWrite: begin + bit[TL_AW-1:0] otp_addr = get_scb_otp_addr(); + bit is_write_locked; + // check if write locked + if (part_has_digest(part_idx)) begin + is_write_locked = get_digest_reg_val(part_idx) != 0; + end else begin + is_write_locked = 0; + end + + if (is_write_locked || (PartInfo[part_idx].iskeymgr_creator && + !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + end else if (is_write_locked || (PartInfo[part_idx].iskeymgr_owner && + !is_digest(dai_addr) && + cfg.otp_ctrl_vif.lc_owner_seed_sw_rw_en_i != lc_ctrl_pkg::On)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + end else begin + predict_no_err(OtpDaiErrIdx); + // write digest + if (is_sw_digest(dai_addr)) begin + bit [TL_DW*2-1:0] curr_digest, prev_digest; + curr_digest = {`gmv(ral.direct_access_wdata[1]), + `gmv(ral.direct_access_wdata[0])}; + prev_digest = {otp_a[otp_addr+1], otp_a[otp_addr]}; + dai_wr_ip = 1; + // allow bit write + if ((prev_digest & curr_digest) == prev_digest) begin + update_digest_to_otp(part_idx, curr_digest); + end else begin + predict_err(OtpDaiErrIdx, OtpMacroWriteBlankError); + end + end else if (is_digest(dai_addr)) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + // write OTP memory + end else begin + dai_wr_ip = 1; + if (!is_secret(dai_addr)) begin + bit [TL_DW-1:0] wr_data = `gmv(ral.direct_access_wdata[0]); + // allow bit write + if ((otp_a[otp_addr] & wr_data) == otp_a[otp_addr]) begin + otp_a[otp_addr] = wr_data; + check_otp_idle(.val(0), .wait_clks(3)); + end else begin + predict_err(OtpDaiErrIdx, OtpMacroWriteBlankError); + end + end else begin + bit [SCRAMBLE_DATA_SIZE-1:0] secret_data = {otp_a[otp_addr + 1], + otp_a[otp_addr]}; + bit [SCRAMBLE_DATA_SIZE-1:0] wr_data = {`gmv(ral.direct_access_wdata[1]), + `gmv(ral.direct_access_wdata[0])}; + wr_data = scramble_data(wr_data, part_idx); + secret_data = scramble_data(secret_data, part_idx); + if ((secret_data & wr_data) == secret_data) begin + otp_a[otp_addr] = `gmv(ral.direct_access_wdata[0]); + otp_a[otp_addr + 1] = `gmv(ral.direct_access_wdata[1]); + // wait until secret scrambling is done + check_otp_idle(.val(0), .wait_clks(34)); + end else begin + predict_err(OtpDaiErrIdx, OtpMacroWriteBlankError); + end + end + end + end + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid cmd: %0d", item.a_data)) + end + endcase + // regwen is set to 0 only if the dai operation is successfully + if (`gmv(ral.intr_state.otp_error) == 0) void'(ral.direct_access_regwen.predict(0)); + end + end + end + "status": begin + if (addr_phase_read) begin + void'(ral.status.predict(.value(exp_status), .kind(UVM_PREDICT_READ))); + + // update status mask + status_mask = 0; + // Mask out check_pending field - we do not know how long it takes to process checks. + // Check failure can trigger all kinds of errors. + if (under_chk) status_mask = '1; + + // Mask out otp_dai access related field - we do not know how long it takes to finish + // DAI access. + if (under_dai_access) begin + status_mask[OtpDaiIdleIdx] = 1; + status_mask[OtpDaiErrIdx] = 1; + end + + // Mask out LCI error bit if lc_req is set. + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check) status_mask[OtpLciErrIdx] = 1; + + end else if (data_phase_read) begin + if (cfg.en_cov) begin + cov.collect_status_cov(item.d_data); + if (cfg.otp_ctrl_vif.alert_reqs) begin + cov.csr_rd_after_alert_cg_wrap.sample(csr.get_offset()); + end + end + + if (item.d_data[OtpDaiIdleIdx]) begin + check_otp_idle(1); + dai_wr_ip = 0; + dai_digest_ip = LifeCycleIdx; + end + + // STATUS register check with mask + if (do_read_check) begin + `DV_CHECK_EQ((csr.get_mirrored_value() | status_mask), (item.d_data | status_mask), + $sformatf("reg name: status, compare_mask %0h", status_mask)) + end + + // Check if OtpCheckPending is set correctly, then ignore checking until check is done + if (under_chk) begin + if (item.d_data[OtpCheckPendingIdx] == 0) begin + exp_status[OtpCheckPendingIdx] = 0; + under_chk = 0; + end + end + + if (under_dai_access && !cfg.otp_ctrl_vif.under_error_states()) begin + if (item.d_data[OtpDaiIdleIdx]) begin + under_dai_access = 0; + void'(ral.direct_access_regwen.predict(direct_access_regwen_state)); + void'(ral.intr_state.otp_operation_done.predict(1)); + end + end + end + // checked in this block above + do_read_check = 0; + end + "check_trigger": begin + if (addr_phase_write && cfg.en_cov && cfg.otp_ctrl_vif.alert_reqs) begin + cov.issue_checks_after_alert_cg.sample(item.a_data); + end + + if (addr_phase_write && `gmv(ral.check_trigger_regwen) && item.a_data inside {[1:3]}) begin + bit [TL_DW-1:0] check_timeout = `gmv(ral.check_timeout) == 0 ? '1 : + `gmv(ral.check_timeout); + exp_status[OtpCheckPendingIdx] = 1; + under_chk = 1; + if (check_timeout <= CHK_TIMEOUT_CYC) begin + set_exp_alert("fatal_check_error", 1, `gmv(ral.check_timeout) + CHK_TIMEOUT_SLACK); + predict_err(OtpTimeoutErrIdx); + end else begin + if (get_field_val(ral.check_trigger.consistency, item.a_data)) begin + foreach (cfg.ecc_chk_err[i]) begin + if (cfg.ecc_chk_err[i] == OtpEccCorrErr && part_has_integrity(i)) begin + predict_err(otp_status_e'(i), OtpMacroEccCorrError); + end else if (cfg.ecc_chk_err[i] == OtpEccUncorrErr && + part_has_integrity(i)) begin + set_exp_alert("fatal_macro_error", 1, 40_000); + predict_err(otp_status_e'(i), OtpMacroEccUncorrError); + end + end + end + end + end + end + "direct_access_regwen": begin + if (addr_phase_write) begin + // This locks the DAI until the next reset. + if (!item.a_data[0]) begin + direct_access_regwen_state = 0; + void'(ral.direct_access_regwen.predict(0)); + end + end + end + // For error codes, if lc_prog in progress, err_code might update anytime in DUT. Ignore + // checking until req is acknowledged. + + "err_code_0": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(0, item.d_data, access_part_idx); + end + end + "err_code_1": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(1, item.d_data, access_part_idx); + end + end + "err_code_2": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(2, item.d_data, access_part_idx); + end + end + "err_code_3": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(3, item.d_data, access_part_idx); + end + end + "err_code_4": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(4, item.d_data, access_part_idx); + end + end + "err_code_5": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(5, item.d_data, access_part_idx); + end + end + "err_code_6": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(6, item.d_data, access_part_idx); + end + end + "err_code_7": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(7, item.d_data, access_part_idx); + end + end + "err_code_8": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(8, item.d_data, access_part_idx); + end + end + "err_code_9": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(9, item.d_data, access_part_idx); + end + end + "err_code_10": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(10, item.d_data, access_part_idx); + end + end + "err_code_11": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(11, item.d_data, access_part_idx); + end + end + "err_code_12": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(12, item.d_data, access_part_idx); + end + end + "err_code_13": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(13, item.d_data, access_part_idx); + end + end + "err_code_14": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(14, item.d_data, access_part_idx); + end + end + "err_code_15": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(15, item.d_data, access_part_idx); + end + end + "err_code_16": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(16, item.d_data, access_part_idx); + end + end + "err_code_17": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(17, item.d_data, access_part_idx); + end + end + "err_code_18": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(18, item.d_data, access_part_idx); + end + end + "err_code_19": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(19, item.d_data, access_part_idx); + end + end + "err_code_20": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(20, item.d_data, access_part_idx); + end + end + "err_code_21": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(21, item.d_data, access_part_idx); + end + end + "err_code_22": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(22, item.d_data, access_part_idx); + end + end + "err_code_23": begin + if (cfg.m_lc_prog_pull_agent_cfg.vif.req) do_read_check = 0; + if (cfg.en_cov && do_read_check && data_phase_read) begin + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address) >> 2 << 2; + int access_part_idx = get_part_index(dai_addr); + cov.collect_err_code_cov(23, item.d_data, access_part_idx); + end + end + "vendor_test_digest_0", "vendor_test_digest_1", + "creator_sw_cfg_digest_0", "creator_sw_cfg_digest_1", + "owner_sw_cfg_digest_0", "owner_sw_cfg_digest_1", + "rot_creator_auth_digest_0", "rot_creator_auth_digest_1", + "rot_owner_auth_slot0_digest_0", "rot_owner_auth_slot0_digest_1", + "rot_owner_auth_slot1_digest_0", "rot_owner_auth_slot1_digest_1", + "plat_integ_auth_slot0_digest_0", "plat_integ_auth_slot0_digest_1", + "plat_integ_auth_slot1_digest_0", "plat_integ_auth_slot1_digest_1", + "plat_owner_auth_slot0_digest_0", "plat_owner_auth_slot0_digest_1", + "plat_owner_auth_slot1_digest_0", "plat_owner_auth_slot1_digest_1", + "plat_owner_auth_slot2_digest_0", "plat_owner_auth_slot2_digest_1", + "plat_owner_auth_slot3_digest_0", "plat_owner_auth_slot3_digest_1", + "rom_patch_digest_0", "rom_patch_digest_1", + "hw_cfg0_digest_0", "hw_cfg0_digest_1", + "hw_cfg1_digest_0", "hw_cfg1_digest_1", + "secret0_digest_0", "secret0_digest_1", + "secret1_digest_0", "secret1_digest_1", + "secret2_digest_0", "secret2_digest_1", + "secret3_digest_0", "secret3_digest_1": begin + if (ignore_digest_chk) do_read_check = 0; + end + "vendor_test_read_lock", + "creator_sw_cfg_read_lock", + "owner_sw_cfg_read_lock", + "ownership_slot_state_read_lock", + "rot_creator_auth_read_lock", + "rot_owner_auth_slot0_read_lock", + "rot_owner_auth_slot1_read_lock", + "plat_integ_auth_slot0_read_lock", + "plat_integ_auth_slot1_read_lock", + "plat_owner_auth_slot0_read_lock", + "plat_owner_auth_slot1_read_lock", + "plat_owner_auth_slot2_read_lock", + "plat_owner_auth_slot3_read_lock", + "ext_nvm_read_lock", + "rom_patch_read_lock", + "direct_access_wdata_0", + "direct_access_wdata_1", + "direct_access_address", + "check_regwen", + "check_trigger_regwen", + "check_trigger", + "check_timeout", + "intr_enable", + "integrity_check_period", + "consistency_check_period", + "alert_test": begin + // Do nothing + end + // DAI read data + "direct_access_rdata_0", "direct_access_rdata_1": do_read_check = check_dai_rd_data; + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, + $sformatf("reg name: %0s", csr.get_full_name())) + if (cfg.en_cov && cfg.otp_ctrl_vif.alert_reqs) begin + cov.csr_rd_after_alert_cg_wrap.sample(csr.get_offset()); + end + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endfunction + + // If reset or lc_escalate_en is issued during otp program, this function will backdoor update + // otp memory write value because scb did not know how many cells haven been written. + // We won't update csr `direct_access_address` after fatal alert happened, so in this function + // we can directly call method `get_scb_otp_addr` to get the interrupted dai address. + virtual function void recover_interrupted_op(); + if (dai_wr_ip) begin + bit [TL_DW-1:0] otp_addr = get_scb_otp_addr(); + bit [TL_DW-1:0] dai_addr = otp_addr << 2; + backdoor_update_otp_array(dai_addr); + dai_wr_ip = 0; + end + endfunction + + virtual function void backdoor_update_otp_array(bit [TL_DW-1:0] dai_addr); + bit [TL_DW-1:0] otp_addr = dai_addr >> 2; + bit [TL_DW-1:0] readout_word, readout_word1; + int part_idx = get_part_index(dai_addr); + if (part_has_integrity(part_idx)) begin + void'(read_a_word_with_ecc(dai_addr, readout_word)); + void'(read_a_word_with_ecc(dai_addr + 4, readout_word1)); + end else begin + void'(read_a_word_with_ecc_raw(dai_addr, readout_word)); + void'(read_a_word_with_ecc_raw(dai_addr + 4, readout_word1)); + end + + otp_a[otp_addr] = readout_word; + + if (is_digest(dai_addr)) begin + otp_a[otp_addr+1] = readout_word1; + end else if (is_secret(dai_addr)) begin + bit [TL_DW*2-1:0] mem_rd_val, descrambled_val; + mem_rd_val = {readout_word1 ,readout_word}; + descrambled_val = descramble_data(mem_rd_val, part_idx); + otp_a[otp_addr+1] = descrambled_val[TL_DW*2-1:TL_DW]; + otp_a[otp_addr] = descrambled_val[TL_DW-1:0]; + end + endfunction + + virtual function bit [1:0] read_a_word_with_ecc(bit [TL_DW-1:0] dai_addr, + ref bit [TL_DW-1:0] readout_word); + prim_secded_pkg::secded_22_16_t ecc_rd_data0 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr); + prim_secded_pkg::secded_22_16_t ecc_rd_data1 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr + 2); + readout_word[15:0] = ecc_rd_data0.data; + readout_word[31:16] = ecc_rd_data1.data; + return max2(ecc_rd_data0.err, ecc_rd_data1.err); + endfunction + + // Returns the ECC error but does not correct the data bits (i.e. returns the raw data). + virtual function bit [1:0] read_a_word_with_ecc_raw(bit [TL_DW-1:0] dai_addr, + ref bit [TL_DW-1:0] readout_word); + prim_secded_pkg::secded_22_16_t ecc_rd_data0 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr); + prim_secded_pkg::secded_22_16_t ecc_rd_data1 = cfg.mem_bkdr_util_h.ecc_read16(dai_addr + 2); + readout_word[15:0] = 16'hFFFF & cfg.mem_bkdr_util_h.read(dai_addr); + readout_word[31:16] = 16'hFFFF & cfg.mem_bkdr_util_h.read(dai_addr + 2); + return max2(ecc_rd_data0.err, ecc_rd_data1.err); + endfunction + + + virtual function void reset(string kind = "HARD"); + recover_interrupted_op(); + super.reset(kind); + // flush fifos + otbn_fifo.flush(); + lc_prog_fifo.flush(); + for (int i = 0; i < NumSramKeyReqSlots; i++) begin + sram_fifos[i].flush(); + end + + direct_access_regwen_state = 1; + under_chk = 0; + under_dai_access = 0; + ignore_digest_chk = 0; + exp_status = `gmv(ral.status); + exp_alert = OtpNoAlert; + + edn_data_q.delete(); + + // Out of reset: lock dai access until power init is done + if (cfg.en_scb) void'(ral.direct_access_regwen.predict(0)); + endfunction + + virtual function void check_otp_idle(bit val, int wait_clks = 0); + fork + begin + fork + begin + // use negedge to avoid race condition + cfg.clk_rst_vif.wait_n_clks(wait_clks + 1); + `uvm_error(`gfn, + $sformatf("pwr_otp_idle output is %0b while expect %0b within %0d cycles", + cfg.otp_ctrl_vif.pwr_otp_idle_o, val, wait_clks)) + end + begin + wait(cfg.under_reset || cfg.otp_ctrl_vif.pwr_otp_idle_o == val || + // Due to OTP access arbitration, any KDI request during DAI access might block + // write secret until KDI request is completed. Since the KDI process time could + // vary depends on the push-pull-agent, we are going to ignore the checking if + // this scenario happens. + cfg.m_otbn_pull_agent_cfg.vif.req || + cfg.m_sram_pull_agent_cfg[0].vif.req || + cfg.m_sram_pull_agent_cfg[1].vif.req || + cfg.m_sram_pull_agent_cfg[2].vif.req || + cfg.m_sram_pull_agent_cfg[3].vif.req || + cfg.m_lc_prog_pull_agent_cfg.vif.req || + // When lc_escalation is on, the DAI interface goes to ErrorSt, so ignore + // otp_idle checking. + cfg.otp_ctrl_vif.alert_reqs || + // Check timeout will keep doing background check, issue #5616 + exp_status[OtpTimeoutErrIdx]); + end + join_any + disable fork; + end + join_none + endfunction + + // predict digest registers + virtual function void predict_digest_csrs(); + void'(ral.vendor_test_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[VendorTestIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.vendor_test_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[VendorTestIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.creator_sw_cfg_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[CreatorSwCfgIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.creator_sw_cfg_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[CreatorSwCfgIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.owner_sw_cfg_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[OwnerSwCfgIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.owner_sw_cfg_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[OwnerSwCfgIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.rot_creator_auth_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotCreatorAuthIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.rot_creator_auth_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotCreatorAuthIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.rot_owner_auth_slot0_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotOwnerAuthSlot0Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.rot_owner_auth_slot0_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotOwnerAuthSlot0Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.rot_owner_auth_slot1_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotOwnerAuthSlot1Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.rot_owner_auth_slot1_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RotOwnerAuthSlot1Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.plat_integ_auth_slot0_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatIntegAuthSlot0Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.plat_integ_auth_slot0_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatIntegAuthSlot0Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.plat_integ_auth_slot1_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatIntegAuthSlot1Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.plat_integ_auth_slot1_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatIntegAuthSlot1Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.plat_owner_auth_slot0_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatOwnerAuthSlot0Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.plat_owner_auth_slot0_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatOwnerAuthSlot0Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.plat_owner_auth_slot1_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatOwnerAuthSlot1Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.plat_owner_auth_slot1_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatOwnerAuthSlot1Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.plat_owner_auth_slot2_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatOwnerAuthSlot2Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.plat_owner_auth_slot2_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatOwnerAuthSlot2Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.plat_owner_auth_slot3_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatOwnerAuthSlot3Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.plat_owner_auth_slot3_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[PlatOwnerAuthSlot3Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.rom_patch_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RomPatchIdx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.rom_patch_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[RomPatchIdx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.hw_cfg0_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[HwCfg0Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.hw_cfg0_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[HwCfg0Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.hw_cfg1_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[HwCfg1Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.hw_cfg1_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[HwCfg1Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.secret0_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret0Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.secret0_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret0Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.secret1_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret1Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.secret1_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret1Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.secret2_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret2Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.secret2_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret2Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + + void'(ral.secret3_digest[0].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret3Idx]]), + .kind(UVM_PREDICT_DIRECT))); + void'(ral.secret3_digest[1].predict( + .value(otp_a[PART_OTP_DIGEST_ADDRS[Secret3Idx] + 1]), + .kind(UVM_PREDICT_DIRECT))); + endfunction + + function void update_digest_to_otp(int part_idx, bit [TL_DW*2-1:0] digest); + otp_a[PART_OTP_DIGEST_ADDRS[part_idx]] = digest[31:0]; + otp_a[PART_OTP_DIGEST_ADDRS[part_idx] + 1] = digest[63:32]; + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + + // Calculate digest value for each partition + // According to the design spec, the calculation is based on 64-rounds of PRESENT cipher + // The 64-bit data_in state is initialized with a silicon creator constant, and each 128 bit + // chunk of partition data are fed in as keys + // The last 64-round PRESENT calculation will use a global digest constant as key input + function void cal_digest_val(int part_idx); + bit [TL_DW-1:0] mem_q[$]; + int array_size; + bit [SCRAMBLE_DATA_SIZE-1:0] digest; + + if (cfg.otp_ctrl_vif.under_error_states()) return; + + if (!part_has_hw_digest(part_idx) || get_digest_reg_val(part_idx) != 0) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + return; + end else if (PartInfo[part_idx].iskeymgr_creator && + cfg.otp_ctrl_vif.lc_creator_seed_sw_rw_en_i != lc_ctrl_pkg::On) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + return; + end else if (PartInfo[part_idx].iskeymgr_owner && + cfg.otp_ctrl_vif.lc_owner_seed_sw_rw_en_i != lc_ctrl_pkg::On) begin + predict_err(OtpDaiErrIdx, OtpAccessError); + return; + end else begin + predict_no_err(OtpDaiErrIdx); + dai_digest_ip = part_idx; + end + case (part_idx) + HwCfg0Idx: mem_q = otp_a[HwCfg0Offset / TL_SIZE : HwCfg0DigestOffset / TL_SIZE - 1]; + HwCfg1Idx: mem_q = otp_a[HwCfg1Offset / TL_SIZE : HwCfg1DigestOffset / TL_SIZE - 1]; + Secret0Idx: mem_q = otp_a[Secret0Offset / TL_SIZE : Secret0DigestOffset / TL_SIZE - 1]; + Secret1Idx: mem_q = otp_a[Secret1Offset / TL_SIZE : Secret1DigestOffset / TL_SIZE - 1]; + Secret2Idx: mem_q = otp_a[Secret2Offset / TL_SIZE : Secret2DigestOffset / TL_SIZE - 1]; + Secret3Idx: mem_q = otp_a[Secret3Offset / TL_SIZE : Secret3DigestOffset / TL_SIZE - 1]; + default: begin + `uvm_fatal(`gfn, $sformatf("Access unexpected partition %0d", part_idx)) + end + endcase + + array_size = mem_q.size(); + + // for secret partitions, need to use otp scrambled value as data input + if (PartInfo[part_idx].secret) begin + bit [TL_DW-1:0] scrambled_mem_q[$]; + for (int i = 0; i < array_size/2; i++) begin + bit [SCRAMBLE_DATA_SIZE-1:0] scrambled_data; + scrambled_data = scramble_data({mem_q[i*2+1], mem_q[i*2]}, part_idx); + scrambled_mem_q.push_back(scrambled_data[TL_DW-1:0]); + scrambled_mem_q.push_back(scrambled_data[SCRAMBLE_DATA_SIZE-1:TL_DW]); + end + mem_q = scrambled_mem_q; + end + + digest = otp_scrambler_pkg::cal_digest(part_idx, mem_q); + update_digest_to_otp(part_idx, digest); + endfunction + + + // this function go through present encode algo two or three iterations: + // first iteration with input key, + // second iteration with second_key, this iteration only happens if num_round is 2 + // third iteration with a final constant as key + // this is mainly used for unlock token hashing, key derivation + virtual function bit [SCRAMBLE_DATA_SIZE-1:0] present_encode_with_final_const( + bit [SCRAMBLE_DATA_SIZE-1:0] data, + bit [SCRAMBLE_KEY_SIZE-1:0] key, + bit [SCRAMBLE_KEY_SIZE-1:0] final_const, + bit [SCRAMBLE_KEY_SIZE-1:0] second_key = '0, + int num_round = 1); + bit [SCRAMBLE_DATA_SIZE-1:0] enc_data; + bit [SCRAMBLE_DATA_SIZE-1:0] intermediate_state; + crypto_dpi_present_pkg::sv_dpi_present_encrypt(data, key, + SCRAMBLE_KEY_SIZE, NUM_ROUND, enc_data); + // XOR the previous state into the digest result according to the Davies-Meyer scheme. + intermediate_state = data ^ enc_data; + + if (num_round == 2) begin + crypto_dpi_present_pkg::sv_dpi_present_encrypt(intermediate_state, second_key, + SCRAMBLE_KEY_SIZE, NUM_ROUND, enc_data); + intermediate_state = intermediate_state ^ enc_data; + end else if (num_round > 2) begin + `uvm_fatal(`gfn, $sformatf("does not support num_round: %0d > 2", num_round)) + end + + crypto_dpi_present_pkg::sv_dpi_present_encrypt(intermediate_state, final_const, + SCRAMBLE_KEY_SIZE, NUM_ROUND, enc_data); + // XOR the previous state into the digest result according to the Davies-Meyer scheme. + present_encode_with_final_const = intermediate_state ^ enc_data; + endfunction + + // Get address for scoreboard's otp_a array from the `direct_access_address` CSR + function bit [TL_DW-1:0] get_scb_otp_addr(); + bit [TL_DW-1:0] dai_addr = `gmv(ral.direct_access_address); + get_scb_otp_addr = normalize_dai_addr(dai_addr) >> 2; + endfunction + + // This function predict OTP error related registers: intr_state, status, and err_code + virtual function void predict_err(otp_status_e status_err_idx, + otp_err_code_e err_code = OtpNoError, + bit update_esc_err = 0); + if (cfg.otp_ctrl_vif.under_error_states() && !update_esc_err) return; + + // Update intr_state + void'(ral.intr_state.otp_error.predict(.value(1), .kind(UVM_PREDICT_READ))); + // Update status + exp_status[status_err_idx] = 1; + + // Only first status errors up to the LCI have corresponding err_code + if (status_err_idx <= OtpLciErrIdx) begin + dv_base_reg_field err_code_flds[$]; + if (err_code == OtpNoError) begin + `uvm_error(`gfn, $sformatf("please set status error: %0s error code", status_err_idx.name)) + end + ral.err_code[status_err_idx].get_dv_base_reg_fields(err_code_flds); + + if (`gmv(err_code_flds[0]) inside {OTP_TERMINAL_ERRS}) begin + `uvm_info(`gfn, "terminal error cannot be updated", UVM_HIGH) + end else if (status_err_idx == OtpLciErrIdx && + `gmv(err_code_flds[0]) != OtpNoError) begin + `uvm_info(`gfn, "For LC partition, all errors are terminal error!", UVM_HIGH) + end else begin + void'(err_code_flds[0].predict(.value(err_code), .kind(UVM_PREDICT_READ))); + end + end + + endfunction + + virtual function void predict_no_err(otp_status_e status_err_idx); + if (cfg.otp_ctrl_vif.under_error_states()) return; + + exp_status[status_err_idx] = 0; + if (status_err_idx == OtpDaiErrIdx) exp_status[OtpDaiIdleIdx] = 1; + + if (status_err_idx <= OtpLciErrIdx) begin + dv_base_reg_field err_code_flds[$]; + ral.err_code[status_err_idx].get_dv_base_reg_fields(err_code_flds); + void'(err_code_flds[0].predict(OtpNoError)); + end + endfunction + + virtual function void predict_rdata(bit is_64_bits, bit [TL_DW-1:0] rdata0, + bit [TL_DW-1:0] rdata1 = 0); + void'(ral.direct_access_rdata[0].predict(.value(rdata0), .kind(UVM_PREDICT_READ))); + if (is_64_bits) begin + void'(ral.direct_access_rdata[1].predict(.value(rdata1), .kind(UVM_PREDICT_READ))); + end + endfunction + + // this function retrieves keys (128 bits) from scb's otp_array with a starting address + // if not locked, it will return 0 + // this is mainly used for scrambling key algo + virtual function bit [SCRAMBLE_KEY_SIZE-1:0] get_key_from_otp(bit locked, int start_i); + bit [SCRAMBLE_KEY_SIZE-1:0] key; + if (!locked) return 0; + for (int i = 0; i < 4; i++) key |= otp_a[i + start_i] << (TL_DW * i); + return key; + endfunction + + // The following two methods are all retrieving digest val. + // get_otp_digest_val: is the digest value from OTP memory + // get_digest_reg_val: is the digest value in register. This value is identical to OTP + // memory's digest value after a power cycle reset. + virtual function bit [TL_DW*2-1:0] get_otp_digest_val(int part_idx); + get_otp_digest_val[31:0] = otp_a[PART_OTP_DIGEST_ADDRS[part_idx]]; + get_otp_digest_val[63:32] = otp_a[PART_OTP_DIGEST_ADDRS[part_idx] + 1]; + endfunction + + virtual function bit [TL_DW*2-1:0] get_digest_reg_val(int part_idx); + bit [TL_DW*2-1:0] digest; + case (part_idx) + VendorTestIdx: begin + digest = {`gmv(ral.vendor_test_digest[1]), + `gmv(ral.vendor_test_digest[0])}; + end + CreatorSwCfgIdx: begin + digest = {`gmv(ral.creator_sw_cfg_digest[1]), + `gmv(ral.creator_sw_cfg_digest[0])}; + end + OwnerSwCfgIdx: begin + digest = {`gmv(ral.owner_sw_cfg_digest[1]), + `gmv(ral.owner_sw_cfg_digest[0])}; + end + RotCreatorAuthIdx: begin + digest = {`gmv(ral.rot_creator_auth_digest[1]), + `gmv(ral.rot_creator_auth_digest[0])}; + end + RotOwnerAuthSlot0Idx: begin + digest = {`gmv(ral.rot_owner_auth_slot0_digest[1]), + `gmv(ral.rot_owner_auth_slot0_digest[0])}; + end + RotOwnerAuthSlot1Idx: begin + digest = {`gmv(ral.rot_owner_auth_slot1_digest[1]), + `gmv(ral.rot_owner_auth_slot1_digest[0])}; + end + PlatIntegAuthSlot0Idx: begin + digest = {`gmv(ral.plat_integ_auth_slot0_digest[1]), + `gmv(ral.plat_integ_auth_slot0_digest[0])}; + end + PlatIntegAuthSlot1Idx: begin + digest = {`gmv(ral.plat_integ_auth_slot1_digest[1]), + `gmv(ral.plat_integ_auth_slot1_digest[0])}; + end + PlatOwnerAuthSlot0Idx: begin + digest = {`gmv(ral.plat_owner_auth_slot0_digest[1]), + `gmv(ral.plat_owner_auth_slot0_digest[0])}; + end + PlatOwnerAuthSlot1Idx: begin + digest = {`gmv(ral.plat_owner_auth_slot1_digest[1]), + `gmv(ral.plat_owner_auth_slot1_digest[0])}; + end + PlatOwnerAuthSlot2Idx: begin + digest = {`gmv(ral.plat_owner_auth_slot2_digest[1]), + `gmv(ral.plat_owner_auth_slot2_digest[0])}; + end + PlatOwnerAuthSlot3Idx: begin + digest = {`gmv(ral.plat_owner_auth_slot3_digest[1]), + `gmv(ral.plat_owner_auth_slot3_digest[0])}; + end + RomPatchIdx: begin + digest = {`gmv(ral.rom_patch_digest[1]), + `gmv(ral.rom_patch_digest[0])}; + end + HwCfg0Idx: begin + digest = {`gmv(ral.hw_cfg0_digest[1]), + `gmv(ral.hw_cfg0_digest[0])}; + end + HwCfg1Idx: begin + digest = {`gmv(ral.hw_cfg1_digest[1]), + `gmv(ral.hw_cfg1_digest[0])}; + end + Secret0Idx: begin + digest = {`gmv(ral.secret0_digest[1]), + `gmv(ral.secret0_digest[0])}; + end + Secret1Idx: begin + digest = {`gmv(ral.secret1_digest[1]), + `gmv(ral.secret1_digest[0])}; + end + Secret2Idx: begin + digest = {`gmv(ral.secret2_digest[1]), + `gmv(ral.secret2_digest[0])}; + end + Secret3Idx: begin + digest = {`gmv(ral.secret3_digest[1]), + `gmv(ral.secret3_digest[0])}; + end + default: `uvm_fatal(`gfn, $sformatf("Partition %0d does not have digest", part_idx)) + endcase + return digest; + endfunction + + virtual function bit is_tl_mem_access_allowed(input tl_seq_item item, input string ral_name, + output bit mem_byte_access_err, + output bit mem_wo_err, + output bit mem_ro_err, + output bit custom_err); + + uvm_reg_addr_t addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + bit [TL_AW-1:0] addr_mask = ral.get_addr_mask(); + bit [TL_AW-1:0] dai_addr = (csr_addr & addr_mask - SW_WINDOW_BASE_ADDR); + + bit mem_access_allowed = super.is_tl_mem_access_allowed(item, ral_name, mem_byte_access_err, + mem_wo_err, mem_ro_err, custom_err); + + if (ral_name == "otp_macro_prim_reg_block") return mem_access_allowed; + + // Ensure the address is within the memory window range. + // Also will skip checking if memory access is not allowed due to TLUL bus error. + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr : + cfg.ral_models[ral_name].mem_ranges[0].end_addr]} && + mem_access_allowed) begin + + // If sw partition is read locked, then access policy changes from RO to no access + if (`gmv(ral.vendor_test_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + VendorTestOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + VendorTestOffset + + VendorTestSize - 1]}) begin + predict_err(OtpVendorTestErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[VendorTestIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(VendorTestIdx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.creator_sw_cfg_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + CreatorSwCfgOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + CreatorSwCfgOffset + + CreatorSwCfgSize - 1]}) begin + predict_err(OtpCreatorSwCfgErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[CreatorSwCfgIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(CreatorSwCfgIdx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.owner_sw_cfg_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + OwnerSwCfgOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + OwnerSwCfgOffset + + OwnerSwCfgSize - 1]}) begin + predict_err(OtpOwnerSwCfgErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[OwnerSwCfgIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(OwnerSwCfgIdx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.ownership_slot_state_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + OwnershipSlotStateOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + OwnershipSlotStateOffset + + OwnershipSlotStateSize - 1]}) begin + predict_err(OtpOwnershipSlotStateErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + // TODO: we should probably create a different covergroup + // for unbuffered partitions without digest. + cov.unbuf_access_lock_cg_wrap[OwnershipSlotStateIdx].sample(.read_lock(1), + .write_lock(0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.rot_creator_auth_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotCreatorAuthOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotCreatorAuthOffset + + RotCreatorAuthSize - 1]}) begin + predict_err(OtpRotCreatorAuthErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[RotCreatorAuthIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(RotCreatorAuthIdx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.rot_owner_auth_slot0_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotOwnerAuthSlot0Offset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotOwnerAuthSlot0Offset + + RotOwnerAuthSlot0Size - 1]}) begin + predict_err(OtpRotOwnerAuthSlot0ErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[RotOwnerAuthSlot0Idx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(RotOwnerAuthSlot0Idx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.rot_owner_auth_slot1_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotOwnerAuthSlot1Offset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + RotOwnerAuthSlot1Offset + + RotOwnerAuthSlot1Size - 1]}) begin + predict_err(OtpRotOwnerAuthSlot1ErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[RotOwnerAuthSlot1Idx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(RotOwnerAuthSlot1Idx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.plat_integ_auth_slot0_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatIntegAuthSlot0Offset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatIntegAuthSlot0Offset + + PlatIntegAuthSlot0Size - 1]}) begin + predict_err(OtpPlatIntegAuthSlot0ErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[PlatIntegAuthSlot0Idx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(PlatIntegAuthSlot0Idx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.plat_integ_auth_slot1_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatIntegAuthSlot1Offset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatIntegAuthSlot1Offset + + PlatIntegAuthSlot1Size - 1]}) begin + predict_err(OtpPlatIntegAuthSlot1ErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[PlatIntegAuthSlot1Idx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(PlatIntegAuthSlot1Idx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.plat_owner_auth_slot0_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatOwnerAuthSlot0Offset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatOwnerAuthSlot0Offset + + PlatOwnerAuthSlot0Size - 1]}) begin + predict_err(OtpPlatOwnerAuthSlot0ErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[PlatOwnerAuthSlot0Idx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(PlatOwnerAuthSlot0Idx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.plat_owner_auth_slot1_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatOwnerAuthSlot1Offset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatOwnerAuthSlot1Offset + + PlatOwnerAuthSlot1Size - 1]}) begin + predict_err(OtpPlatOwnerAuthSlot1ErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[PlatOwnerAuthSlot1Idx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(PlatOwnerAuthSlot1Idx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.plat_owner_auth_slot2_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatOwnerAuthSlot2Offset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatOwnerAuthSlot2Offset + + PlatOwnerAuthSlot2Size - 1]}) begin + predict_err(OtpPlatOwnerAuthSlot2ErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[PlatOwnerAuthSlot2Idx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(PlatOwnerAuthSlot2Idx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.plat_owner_auth_slot3_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatOwnerAuthSlot3Offset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + PlatOwnerAuthSlot3Offset + + PlatOwnerAuthSlot3Size - 1]}) begin + predict_err(OtpPlatOwnerAuthSlot3ErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[PlatOwnerAuthSlot3Idx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(PlatOwnerAuthSlot3Idx) != 0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.ext_nvm_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + ExtNvmOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + ExtNvmOffset + + ExtNvmSize - 1]}) begin + predict_err(OtpExtNvmErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + // TODO: we should probably create a different covergroup + // for unbuffered partitions without digest. + cov.unbuf_access_lock_cg_wrap[ExtNvmIdx].sample(.read_lock(1), + .write_lock(0), .is_write(0)); + end + return 0; + end + end + if (`gmv(ral.rom_patch_read_lock) == 0 || + cfg.otp_ctrl_vif.under_error_states()) begin + if (addr inside { + [cfg.ral_models[ral_name].mem_ranges[0].start_addr + RomPatchOffset : + cfg.ral_models[ral_name].mem_ranges[0].start_addr + RomPatchOffset + + RomPatchSize - 1]}) begin + predict_err(OtpRomPatchErrIdx, OtpAccessError); + custom_err = 1; + if (cfg.en_cov) begin + cov.unbuf_access_lock_cg_wrap[RomPatchIdx].sample(.read_lock(1), + .write_lock(get_digest_reg_val(RomPatchIdx) != 0), .is_write(0)); + end + return 0; + end + end + + // Check ECC uncorrectable fatal error. + if (dai_addr < LifeCycleOffset) begin + int part_idx = get_part_index(dai_addr); + bit [TL_DW-1:0] read_out; + int ecc_err = read_a_word_with_ecc(dai_addr, read_out); + if (ecc_err == OtpEccUncorrErr && part_has_integrity(part_idx)) begin + predict_err(otp_status_e'(part_idx), OtpMacroEccUncorrError); + set_exp_alert("fatal_macro_error", 1, 20); + custom_err = 1; + return 0; + end + end + end + + return mem_access_allowed; + endfunction + + virtual function bit predict_tl_err(tl_seq_item item, tl_channels_e channel, string ral_name); + if (ral_name == "otp_macro_prim_reg_block" && + cfg.otp_ctrl_vif.lc_dft_en_i != lc_ctrl_pkg::On) begin + if (channel == DataChannel) begin + `DV_CHECK_EQ(item.d_error, 1, + $sformatf({"On interface %0s, TL item: %0s, access gated by lc_dft_en_i"}, + ral_name, item.sprint(uvm_default_line_printer))) + + // In data read phase, check d_data when d_error = 1. + if (item.d_error && (item.d_opcode == tlul_pkg::AccessAckData)) begin + check_tl_read_value_after_error(item, ral_name); + end + end + return 1; + end + return super.predict_tl_err(item, channel, ral_name); + endfunction + + virtual function void set_exp_alert(string alert_name, bit is_fatal = 0, int max_delay = 0); + exp_alert = alert_name == "fatal_check_error" ? OtpCheckAlert : OtpMacroAlert; + super.set_exp_alert(alert_name, is_fatal, max_delay); + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv new file mode 100644 index 00000000000..399df4a830c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_ctrl_virtual_sequencer.sv @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class otp_ctrl_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(otp_ctrl_env_cfg), + .COV_T(otp_ctrl_env_cov) + ); + `uvm_component_utils(otp_ctrl_virtual_sequencer) + + `uvm_component_new + + push_pull_sequencer#(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_pull_sequencer_h[NumSramKeyReqSlots]; + push_pull_sequencer#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_sequencer_h; + push_pull_sequencer#(.DeviceDataWidth(1), .HostDataWidth(LC_PROG_DATA_SIZE)) + lc_prog_pull_sequencer_h; +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_scrambler_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_scrambler_pkg.sv new file mode 100644 index 00000000000..91812a0f0e2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/otp_scrambler_pkg.sv @@ -0,0 +1,88 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +///////////////////////////////////////////////// +// OTP secret data and digest scrambling logic // +///////////////////////////////////////////////// + +package otp_scrambler_pkg; + + import uvm_pkg::*; + import otp_ctrl_part_pkg::*; + import bus_params_pkg::*; + + `include "uvm_macros.svh" + + parameter int SCRAMBLE_DATA_SIZE = 64; + parameter int SCRAMBLE_KEY_SIZE = 128; + parameter int NUM_ROUND = 31; + string path = "otp_scrambler_pkg"; + + // When secret data write into otp_array, it will be scrambled. + function automatic bit [SCRAMBLE_DATA_SIZE-1:0] scramble_data( + bit [SCRAMBLE_DATA_SIZE-1:0] input_data, + int part_idx + ); + + int secret_idx = part_idx - Secret0Idx; + crypto_dpi_present_pkg::sv_dpi_present_encrypt(input_data, + RndCnstKey[secret_idx], + SCRAMBLE_KEY_SIZE, + NUM_ROUND, + scramble_data); + endfunction + + // When secret data read out of otp_array, it will be descrambled. + function automatic bit [SCRAMBLE_DATA_SIZE-1:0] descramble_data( + bit [SCRAMBLE_DATA_SIZE-1:0] input_data, + int part_idx + ); + + int secret_idx = part_idx - Secret0Idx; + + crypto_dpi_present_pkg::sv_dpi_present_decrypt(input_data, + RndCnstKey[secret_idx], + SCRAMBLE_KEY_SIZE, + NUM_ROUND, + descramble_data); + endfunction + + function automatic bit [SCRAMBLE_DATA_SIZE-1:0] cal_digest(int part_idx, + ref bit [BUS_DW-1:0] mem_q[$]); + int array_size = mem_q.size(); + real key_factor = SCRAMBLE_KEY_SIZE / BUS_DW; + bit [SCRAMBLE_DATA_SIZE-1:0] init_vec = RndCnstDigestIV[0]; + bit [SCRAMBLE_DATA_SIZE-1:0] enc_data; + bit [SCRAMBLE_DATA_SIZE-1:0] digest; + + for (int i = 0; i < $ceil(array_size / key_factor); i++) begin + bit [SCRAMBLE_DATA_SIZE-1:0] input_data = (i == 0) ? init_vec : digest; + bit [SCRAMBLE_KEY_SIZE-1:0] key; + + // Pad 32-bit partition data into 128-bit key input. + // Because the mem_q size is a multiple of 64-bit, so if the last round only has 64-bits key, + // it will repeat the last 64-bits twice. + for (int j = 0; j < key_factor; j++) begin + int index = i * key_factor + j; + key |= ((index >= array_size ? mem_q[index-2] : mem_q[index]) << (j * BUS_DW)); + end + + // Trigger 32 round of PRESENT encrypt. + crypto_dpi_present_pkg::sv_dpi_present_encrypt(input_data, key, SCRAMBLE_KEY_SIZE, + NUM_ROUND, enc_data); + // XOR the previous state into the digest result according to the Davies-Meyer scheme. + digest = enc_data ^ input_data; + end + + // Last 32 round of digest is calculated with a digest constant. + crypto_dpi_present_pkg::sv_dpi_present_encrypt(digest, + RndCnstDigestConst[0], + SCRAMBLE_KEY_SIZE, NUM_ROUND, + enc_data); + // XOR the previous state into the digest result according to the Davies-Meyer scheme. + digest ^= enc_data; + return digest; + endfunction + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_background_chks_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_background_chks_vseq.sv new file mode 100644 index 00000000000..d316e1a12a5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_background_chks_vseq.sv @@ -0,0 +1,73 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This simple sequence checks if the background check can be triggered once the period is set. + +class otp_ctrl_background_chks_vseq extends otp_ctrl_dai_lock_vseq; + `uvm_object_utils(otp_ctrl_background_chks_vseq) + + `uvm_object_new + + rand bit [1:0] trigger_chks; + rand uint check_period; + + constraint regwens_c {check_regwen_val == 1;} + + // At least one check will be triggered + constraint check_triggers_c {trigger_chks > 0;} + + constraint check_period_c { + check_period < 20; + check_period > 0; + } + + task body(); + int check_wait_cycles; + super.body(); + + // For stress_all_with_rand_reset test, if previous lc_esc_en is not cleared, then skip the + // background check. + if (cfg.otp_ctrl_vif.lc_esc_on == 0) begin + + // Write background check + if (trigger_chks[0]) csr_wr(ral.integrity_check_period, check_period); + if (trigger_chks[1]) csr_wr(ral.consistency_check_period, check_period); + `uvm_info(`gfn, $sformatf("trigger background check %0h", trigger_chks), UVM_LOW) + + cfg.en_scb = 0; + // According to spec, check period will append an 'hFF from the LSF. Add 10 cycle buffers for + // register updates. + check_wait_cycles = (check_period + 1) << 8 + 10; + + // Wait for first check done + repeat($countones(trigger_chks)) begin + csr_spinwait(.ptr(ral.status.check_pending), .exp_data(1), + .timeout_ns(cfg.clk_rst_vif.clk_period_ps / 1000 * check_wait_cycles)); + + csr_spinwait(.ptr(ral.status.check_pending), .exp_data(0)); + end + + // Configure timeout settings to trigger check error + csr_wr(ral.check_timeout, $urandom_range(1, 5)); + `uvm_info(`gfn, "trigger check timeout error", UVM_LOW) + + // Wait for fatal alert + `DV_SPINWAIT_EXIT( + wait(cfg.m_alert_agent_cfgs["fatal_check_error"].vif.alert_tx_final.alert_p);, + cfg.clk_rst_vif.wait_clks(check_wait_cycles);, + $sformatf("Timeout waiting for alert %0s", "fatal_check_error")) + check_fatal_alert_nonblocking("fatal_check_error"); + + cfg.clk_rst_vif.wait_clks($urandom_range(50, 1000)); + csr_rd_check(.ptr(ral.status.timeout_error), .compare_value(1)); + end + endtask + + // Enable scoreboard is done in stress_all sequence and `apply_resets_concurrently` task to + // avoid otp_ctrl_scoreboard reporting failures when reset has not been issued. + virtual task post_start(); + expect_fatal_alerts = 1; + super.post_start(); + endtask +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv new file mode 100644 index 00000000000..40252520154 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv @@ -0,0 +1,794 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +class otp_ctrl_base_vseq extends cip_base_vseq #( + .RAL_T (otp_ctrl_core_reg_block), + .CFG_T (otp_ctrl_env_cfg), + .COV_T (otp_ctrl_env_cov), + .VIRTUAL_SEQUENCER_T (otp_ctrl_virtual_sequencer) + ); + `uvm_object_utils(otp_ctrl_base_vseq) + `uvm_object_new + + // various knobs to enable certain routines + bit do_otp_ctrl_init = 1'b1; + bit do_otp_pwr_init = 1'b1; + + // To only write unused OTP address, sequence will collect all the written addresses to an + // associative array to avoid `write_blank_addr_error`. + bit write_unused_addr = 1; + static bit used_dai_addrs[bit [OTP_ADDR_WIDTH - 1 : 0]]; + + rand bit [NumOtpCtrlIntr-1:0] en_intr; + + rand int apply_reset_during_pwr_init_cycles; + + bit is_valid_dai_op = 1; + + // According to spec, the period between digest calculation and reset should not issue any write. + bit [NumPart-2:0] digest_calculated; + + // For stress_all_with_rand reset sequence to issue reset during OTP operations. + bit do_digest_cal, do_otp_rd, do_otp_wr; + + // LC program request will use a separate variable to automatically set to non-blocking setting + // when LC error bit is set. + bit default_req_blocking = 1; + bit lc_prog_blocking = 1; + bit dai_wr_inprogress = 0; + uint32_t op_done_spinwait_timeout_ns = 20_000_000; + + // Collect current lc_state and lc_cnt. This is used to create next lc_state and lc_cnt without + // error. + lc_ctrl_state_pkg::lc_state_e lc_state; + lc_ctrl_state_pkg::lc_cnt_e lc_cnt; + + otp_ctrl_callback_vseq callback_vseq; + + constraint apply_reset_during_pwr_init_cycles_c { + apply_reset_during_pwr_init_cycles == 0; + } + + virtual task pre_start(); + `uvm_create_on(callback_vseq, p_sequencer); + super.pre_start(); + endtask + + virtual task dut_init(string reset_kind = "HARD"); + // OTP has dut and edn reset. If assign OTP values after `super.dut_init()`, and if dut reset + // deasserts earlier than edn reset, some OTP outputs might remain X or Z when dut clock is + // running. + otp_ctrl_vif_init(); + super.dut_init(reset_kind); + callback_vseq.dut_init_callback(); + + cfg.backdoor_clear_mem = 0; + // reset power init pin and lc pins + if (do_otp_ctrl_init && do_apply_reset) otp_ctrl_init(); + cfg.clk_rst_vif.wait_clks($urandom_range(0, 10)); + if (do_otp_pwr_init && do_apply_reset) otp_pwr_init(); + callback_vseq.post_otp_pwr_init(); + endtask + + // Cfg errors are cleared after reset + virtual task apply_reset(string kind = "HARD"); + super.apply_reset(kind); + cfg.otp_ctrl_vif.release_part_access_mubi(); + clear_seq_flags(); + endtask + + virtual function void clear_seq_flags(); + do_digest_cal = 0; + do_otp_rd = 0; + do_otp_wr = 0; + endfunction + + virtual task otp_ctrl_vif_init(); + cfg.otp_ctrl_vif.drive_lc_creator_seed_sw_rw_en(lc_ctrl_pkg::On); + cfg.otp_ctrl_vif.drive_lc_owner_seed_sw_rw_en(lc_ctrl_pkg::On); + cfg.otp_ctrl_vif.drive_lc_seed_hw_rd_en(get_rand_lc_tx_val()); + cfg.otp_ctrl_vif.drive_lc_dft_en(get_rand_lc_tx_val(.t_weight(0))); + cfg.otp_ctrl_vif.drive_lc_escalate_en(lc_ctrl_pkg::Off); + cfg.otp_ctrl_vif.drive_pwr_otp_init(0); + cfg.otp_ctrl_vif.drive_ext_voltage_h_io(1'bz); + + // Unused signals in open sourced OTP memory + `DV_CHECK_RANDOMIZE_FATAL(cfg.dut_cfg) + cfg.otp_ctrl_vif.otp_ast_pwr_seq_h_i = cfg.dut_cfg.otp_ast_pwr_seq_h; + cfg.otp_ctrl_vif.scan_en_i = cfg.dut_cfg.scan_en; + cfg.otp_ctrl_vif.scan_rst_ni = cfg.dut_cfg.scan_rst_n; + cfg.otp_ctrl_vif.scanmode_i = cfg.dut_cfg.scanmode; + cfg.otp_ctrl_vif.otp_vendor_test_ctrl_i = cfg.dut_cfg.otp_vendor_test_ctrl; + endtask + + // drive otp_pwr req pin to initialize OTP, and wait until init is done + virtual task otp_pwr_init(); + cfg.otp_ctrl_vif.drive_pwr_otp_init(1); + if (apply_reset_during_pwr_init_cycles > 0) begin + `DV_SPINWAIT_EXIT( + cfg.clk_rst_vif.wait_clks(apply_reset_during_pwr_init_cycles);, + wait (cfg.otp_ctrl_vif.pwr_otp_done_o == 1);) + if (cfg.otp_ctrl_vif.pwr_otp_done_o == 0) begin + cfg.otp_ctrl_vif.drive_pwr_otp_init(0); + apply_reset(); + cfg.otp_ctrl_vif.drive_pwr_otp_init(1); + end + end + wait (cfg.otp_ctrl_vif.pwr_otp_done_o == 1); + cfg.otp_ctrl_vif.drive_pwr_otp_init(0); + digest_calculated = 0; + endtask + + // setup basic otp_ctrl features + virtual task otp_ctrl_init(); + // reset memory to avoid readout X + clear_otp_memory(); + lc_state = lc_state_e'(0); + lc_cnt = lc_cnt_e'(0); + endtask + + virtual function void clear_otp_memory(); + cfg.mem_bkdr_util_h.clear_mem(); + cfg.backdoor_clear_mem = 1; + used_dai_addrs.delete(); + endfunction + + // Override this task for otp_ctrl_common_vseq and otp_ctrl_stress_all_with_rand_reset_vseq + // because some registers won't set to default value until otp_init is done. + virtual task read_and_check_all_csrs_after_reset(); + cfg.otp_ctrl_vif.drive_lc_escalate_en(lc_ctrl_pkg::Off); + otp_pwr_init(); + super.read_and_check_all_csrs_after_reset(); + endtask + + // this task triggers an OTP write sequence via the DAI interface + virtual task dai_wr(bit [TL_DW-1:0] addr, + bit [TL_DW-1:0] wdata0, + bit [TL_DW-1:0] wdata1 = 0); + bit [TL_DW-1:0] val; + dai_wr_inprogress = 1; + if (write_unused_addr) begin + if (used_dai_addrs.exists(addr[OTP_ADDR_WIDTH - 1 : 0])) begin + `uvm_info(`gfn, $sformatf("addr %0h is already written!", addr), UVM_MEDIUM) + dai_wr_inprogress = 0; + return; + end else begin + used_dai_addrs[addr] = 1; + end + end + addr = randomize_dai_addr(addr); + `uvm_info(`gfn, $sformatf("dai write addr %0h, data %0h", addr, wdata0), UVM_HIGH) + csr_wr(ral.direct_access_address, addr); + csr_wr(ral.direct_access_wdata[0], wdata0); + if (is_secret(addr) || is_sw_digest(addr)) csr_wr(ral.direct_access_wdata[1], wdata1); + + do_otp_wr = 1; + csr_wr(ral.direct_access_cmd, int'(otp_ctrl_top_specific_pkg::DaiWrite)); + `uvm_info(`gfn, $sformatf("DAI write, address %0h, data0 %0h data1 %0h, is_secret = %0b", + addr, wdata0, wdata1, is_secret(addr)), UVM_DEBUG) + + // Direct_access_regwen and dai_idle are checked only when following conditions are met: + // - the dai operation is valid, otherwise it is hard to predict which cycle the error is + // detected + // - zero delays in TLUL interface, otherwise dai operation might be finished before reading + // these two CSRs + if (cfg.zero_delays && is_valid_dai_op && + cfg.otp_ctrl_vif.lc_escalate_en_i == lc_ctrl_pkg::Off) begin + csr_rd_check(ral.status.dai_idle, .compare_value(0), .backdoor(1)); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.direct_access_regwen), .value(val)); + end + wait_dai_op_done(); + rd_and_clear_intrs(); + dai_wr_inprogress = 0; + endtask : dai_wr + + // This task triggers an OTP readout sequence via the DAI interface + virtual task dai_rd(input bit [TL_DW-1:0] addr, + output bit [TL_DW-1:0] rdata0, + output bit [TL_DW-1:0] rdata1); + bit [TL_DW-1:0] val; + addr = randomize_dai_addr(addr); + + csr_wr(ral.direct_access_address, addr); + do_otp_rd = 1; + csr_wr(ral.direct_access_cmd, int'(otp_ctrl_top_specific_pkg::DaiRead)); + + if (cfg.zero_delays && is_valid_dai_op && + cfg.otp_ctrl_vif.lc_escalate_en_i == lc_ctrl_pkg::Off) begin + csr_rd_check(ral.status.dai_idle, .compare_value(0), .backdoor(1)); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.direct_access_regwen), .value(val)); + end + + wait_dai_op_done(); + csr_rd(ral.direct_access_rdata[0], rdata0); + if (is_secret(addr) || is_digest(addr)) csr_rd(ral.direct_access_rdata[1], rdata1); + rd_and_clear_intrs(); + endtask : dai_rd + + virtual task dai_rd_check(bit [TL_DW-1:0] addr, + bit [TL_DW-1:0] exp_data0, + bit [TL_DW-1:0] exp_data1 = 0); + bit [TL_DW-1:0] rdata0, rdata1; + dai_rd(addr, rdata0, rdata1); + if (!cfg.under_reset) begin + `DV_CHECK_EQ(rdata0, exp_data0, $sformatf("dai addr %0h rdata0 readout mismatch", addr)) + if (is_secret(addr) || is_digest(addr)) begin + `DV_CHECK_EQ(rdata1, exp_data1, $sformatf("dai addr %0h rdata1 readout mismatch", addr)) + end + end + endtask: dai_rd_check + + // this task exercises an OTP digest calculation via the DAI interface + virtual task cal_digest(int part_idx); + bit [TL_DW-1:0] val; + csr_wr(ral.direct_access_address, PART_BASE_ADDRS[part_idx]); + csr_wr(ral.direct_access_cmd, otp_ctrl_top_specific_pkg::DaiDigest); + + if (cfg.zero_delays && is_valid_dai_op && + cfg.otp_ctrl_vif.lc_escalate_en_i == lc_ctrl_pkg::Off) begin + csr_rd_check(ral.status.dai_idle, .compare_value(0), .backdoor(1)); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.direct_access_regwen), .value(val)); + end + do_digest_cal = 1; + wait_dai_op_done(); + digest_calculated[part_idx] = 1; + rd_and_clear_intrs(); + endtask + + // this task provisions all HW partitions + // SW partitions could not be provisioned via DAI interface + // LC partitions cannot be locked + virtual task cal_hw_digests(bit [NumPart-1:0] trigger_digest = $urandom()); + foreach (PartInfo[i]) begin + if (PartInfo[i].hw_digest && trigger_digest[i]) begin + cal_digest(i); + end + end + endtask + + // SW digest data are calculated in sw and won't be checked in OTP. + // Here to simplify testbench, write random data to sw digest. + virtual task write_sw_digests(bit [NumPartUnbuf-1:0] wr_digest = $urandom()); + bit [TL_DW*2-1:0] wdata; + if (wr_digest[VendorTestIdx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(VendorTestDigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[CreatorSwCfgIdx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(CreatorSwCfgDigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[OwnerSwCfgIdx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(OwnerSwCfgDigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[RotCreatorAuthIdx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(RotCreatorAuthDigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[RotOwnerAuthSlot0Idx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(RotOwnerAuthSlot0DigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[RotOwnerAuthSlot1Idx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(RotOwnerAuthSlot1DigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[PlatIntegAuthSlot0Idx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(PlatIntegAuthSlot0DigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[PlatIntegAuthSlot1Idx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(PlatIntegAuthSlot1DigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[PlatOwnerAuthSlot0Idx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(PlatOwnerAuthSlot0DigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[PlatOwnerAuthSlot1Idx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(PlatOwnerAuthSlot1DigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[PlatOwnerAuthSlot2Idx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(PlatOwnerAuthSlot2DigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[PlatOwnerAuthSlot3Idx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(PlatOwnerAuthSlot3DigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + if (wr_digest[RomPatchIdx]) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata); + dai_wr(RomPatchDigestOffset, wdata[TL_DW-1:0], wdata[TL_DW*2-1:TL_DW]); + end + endtask + + virtual task write_sw_rd_locks(bit [NumPartUnbuf-1:0] do_rd_lock= $urandom()); + if (do_rd_lock[VendorTestIdx]) csr_wr(ral.vendor_test_read_lock, 0); + if (do_rd_lock[CreatorSwCfgIdx]) csr_wr(ral.creator_sw_cfg_read_lock, 0); + if (do_rd_lock[OwnerSwCfgIdx]) csr_wr(ral.owner_sw_cfg_read_lock, 0); + if (do_rd_lock[OwnershipSlotStateIdx]) csr_wr(ral.ownership_slot_state_read_lock, 0); + if (do_rd_lock[RotCreatorAuthIdx]) csr_wr(ral.rot_creator_auth_read_lock, 0); + if (do_rd_lock[RotOwnerAuthSlot0Idx]) csr_wr(ral.rot_owner_auth_slot0_read_lock, 0); + if (do_rd_lock[RotOwnerAuthSlot1Idx]) csr_wr(ral.rot_owner_auth_slot1_read_lock, 0); + if (do_rd_lock[PlatIntegAuthSlot0Idx]) csr_wr(ral.plat_integ_auth_slot0_read_lock, 0); + if (do_rd_lock[PlatIntegAuthSlot1Idx]) csr_wr(ral.plat_integ_auth_slot1_read_lock, 0); + if (do_rd_lock[PlatOwnerAuthSlot0Idx]) csr_wr(ral.plat_owner_auth_slot0_read_lock, 0); + if (do_rd_lock[PlatOwnerAuthSlot1Idx]) csr_wr(ral.plat_owner_auth_slot1_read_lock, 0); + if (do_rd_lock[PlatOwnerAuthSlot2Idx]) csr_wr(ral.plat_owner_auth_slot2_read_lock, 0); + if (do_rd_lock[PlatOwnerAuthSlot3Idx]) csr_wr(ral.plat_owner_auth_slot3_read_lock, 0); + if (do_rd_lock[ExtNvmIdx]) csr_wr(ral.ext_nvm_read_lock, 0); + if (do_rd_lock[RomPatchIdx]) csr_wr(ral.rom_patch_read_lock, 0); + endtask + + // The digest CSR values are verified in otp_ctrl_scoreboard + virtual task rd_digests(); + bit [TL_DW-1:0] val; + csr_rd(.ptr(ral.vendor_test_digest[0]), .value(val)); + csr_rd(.ptr(ral.vendor_test_digest[1]), .value(val)); + csr_rd(.ptr(ral.creator_sw_cfg_digest[0]), .value(val)); + csr_rd(.ptr(ral.creator_sw_cfg_digest[1]), .value(val)); + csr_rd(.ptr(ral.owner_sw_cfg_digest[0]), .value(val)); + csr_rd(.ptr(ral.owner_sw_cfg_digest[1]), .value(val)); + csr_rd(.ptr(ral.rot_creator_auth_digest[0]), .value(val)); + csr_rd(.ptr(ral.rot_creator_auth_digest[1]), .value(val)); + csr_rd(.ptr(ral.rot_owner_auth_slot0_digest[0]), .value(val)); + csr_rd(.ptr(ral.rot_owner_auth_slot0_digest[1]), .value(val)); + csr_rd(.ptr(ral.rot_owner_auth_slot1_digest[0]), .value(val)); + csr_rd(.ptr(ral.rot_owner_auth_slot1_digest[1]), .value(val)); + csr_rd(.ptr(ral.plat_integ_auth_slot0_digest[0]), .value(val)); + csr_rd(.ptr(ral.plat_integ_auth_slot0_digest[1]), .value(val)); + csr_rd(.ptr(ral.plat_integ_auth_slot1_digest[0]), .value(val)); + csr_rd(.ptr(ral.plat_integ_auth_slot1_digest[1]), .value(val)); + csr_rd(.ptr(ral.plat_owner_auth_slot0_digest[0]), .value(val)); + csr_rd(.ptr(ral.plat_owner_auth_slot0_digest[1]), .value(val)); + csr_rd(.ptr(ral.plat_owner_auth_slot1_digest[0]), .value(val)); + csr_rd(.ptr(ral.plat_owner_auth_slot1_digest[1]), .value(val)); + csr_rd(.ptr(ral.plat_owner_auth_slot2_digest[0]), .value(val)); + csr_rd(.ptr(ral.plat_owner_auth_slot2_digest[1]), .value(val)); + csr_rd(.ptr(ral.plat_owner_auth_slot3_digest[0]), .value(val)); + csr_rd(.ptr(ral.plat_owner_auth_slot3_digest[1]), .value(val)); + csr_rd(.ptr(ral.rom_patch_digest[0]), .value(val)); + csr_rd(.ptr(ral.rom_patch_digest[1]), .value(val)); + csr_rd(.ptr(ral.hw_cfg0_digest[0]), .value(val)); + csr_rd(.ptr(ral.hw_cfg0_digest[1]), .value(val)); + csr_rd(.ptr(ral.hw_cfg1_digest[0]), .value(val)); + csr_rd(.ptr(ral.hw_cfg1_digest[1]), .value(val)); + csr_rd(.ptr(ral.secret0_digest[0]), .value(val)); + csr_rd(.ptr(ral.secret0_digest[1]), .value(val)); + csr_rd(.ptr(ral.secret1_digest[0]), .value(val)); + csr_rd(.ptr(ral.secret1_digest[1]), .value(val)); + csr_rd(.ptr(ral.secret2_digest[0]), .value(val)); + csr_rd(.ptr(ral.secret2_digest[1]), .value(val)); + csr_rd(.ptr(ral.secret3_digest[0]), .value(val)); + csr_rd(.ptr(ral.secret3_digest[1]), .value(val)); + endtask + + // If the partition is read/write locked, there is 20% chance we will force the internal mubi + // access signal to the values other than mubi::true or mubi::false. + virtual task force_mubi_part_access(); + // Stress_all_with_rand_reset seq will issue reset and wait until reset is done then kill the + // parallel sequence. This gating logic avoid injecting error during reset active. + if (cfg.otp_ctrl_vif.alert_reqs == 0 && !cfg.under_reset) begin + otp_part_access_lock_t forced_mubi_part_access[NumPart-1]; + + // Digest write locks + if ((`gmv(ral.vendor_test_digest[0]) || + `gmv(ral.vendor_test_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[VendorTestIdx].write_lock = 1; + end + if ((`gmv(ral.creator_sw_cfg_digest[0]) || + `gmv(ral.creator_sw_cfg_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[CreatorSwCfgIdx].write_lock = 1; + end + if ((`gmv(ral.owner_sw_cfg_digest[0]) || + `gmv(ral.owner_sw_cfg_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[OwnerSwCfgIdx].write_lock = 1; + end + if ((`gmv(ral.rot_creator_auth_digest[0]) || + `gmv(ral.rot_creator_auth_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[RotCreatorAuthIdx].write_lock = 1; + end + if ((`gmv(ral.rot_owner_auth_slot0_digest[0]) || + `gmv(ral.rot_owner_auth_slot0_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[RotOwnerAuthSlot0Idx].write_lock = 1; + end + if ((`gmv(ral.rot_owner_auth_slot1_digest[0]) || + `gmv(ral.rot_owner_auth_slot1_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[RotOwnerAuthSlot1Idx].write_lock = 1; + end + if ((`gmv(ral.plat_integ_auth_slot0_digest[0]) || + `gmv(ral.plat_integ_auth_slot0_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatIntegAuthSlot0Idx].write_lock = 1; + end + if ((`gmv(ral.plat_integ_auth_slot1_digest[0]) || + `gmv(ral.plat_integ_auth_slot1_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatIntegAuthSlot1Idx].write_lock = 1; + end + if ((`gmv(ral.plat_owner_auth_slot0_digest[0]) || + `gmv(ral.plat_owner_auth_slot0_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatOwnerAuthSlot0Idx].write_lock = 1; + end + if ((`gmv(ral.plat_owner_auth_slot1_digest[0]) || + `gmv(ral.plat_owner_auth_slot1_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatOwnerAuthSlot1Idx].write_lock = 1; + end + if ((`gmv(ral.plat_owner_auth_slot2_digest[0]) || + `gmv(ral.plat_owner_auth_slot2_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatOwnerAuthSlot2Idx].write_lock = 1; + end + if ((`gmv(ral.plat_owner_auth_slot3_digest[0]) || + `gmv(ral.plat_owner_auth_slot3_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatOwnerAuthSlot3Idx].write_lock = 1; + end + if ((`gmv(ral.rom_patch_digest[0]) || + `gmv(ral.rom_patch_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[RomPatchIdx].write_lock = 1; + end + if ((`gmv(ral.hw_cfg0_digest[0]) || + `gmv(ral.hw_cfg0_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[HwCfg0Idx].write_lock = 1; + end + if ((`gmv(ral.hw_cfg1_digest[0]) || + `gmv(ral.hw_cfg1_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[HwCfg1Idx].write_lock = 1; + end + if ((`gmv(ral.secret0_digest[0]) || + `gmv(ral.secret0_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[Secret0Idx].write_lock = 1; + end + if ((`gmv(ral.secret1_digest[0]) || + `gmv(ral.secret1_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[Secret1Idx].write_lock = 1; + end + if ((`gmv(ral.secret2_digest[0]) || + `gmv(ral.secret2_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[Secret2Idx].write_lock = 1; + end + if ((`gmv(ral.secret3_digest[0]) || + `gmv(ral.secret3_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[Secret3Idx].write_lock = 1; + end + + // CSR read locks + if ((`gmv(ral.vendor_test_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[VendorTestIdx].read_lock = 1; + end + if ((`gmv(ral.creator_sw_cfg_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[CreatorSwCfgIdx].read_lock = 1; + end + if ((`gmv(ral.owner_sw_cfg_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[OwnerSwCfgIdx].read_lock = 1; + end + if ((`gmv(ral.ownership_slot_state_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[OwnershipSlotStateIdx].read_lock = 1; + end + if ((`gmv(ral.rot_creator_auth_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[RotCreatorAuthIdx].read_lock = 1; + end + if ((`gmv(ral.rot_owner_auth_slot0_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[RotOwnerAuthSlot0Idx].read_lock = 1; + end + if ((`gmv(ral.rot_owner_auth_slot1_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[RotOwnerAuthSlot1Idx].read_lock = 1; + end + if ((`gmv(ral.plat_integ_auth_slot0_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatIntegAuthSlot0Idx].read_lock = 1; + end + if ((`gmv(ral.plat_integ_auth_slot1_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatIntegAuthSlot1Idx].read_lock = 1; + end + if ((`gmv(ral.plat_owner_auth_slot0_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatOwnerAuthSlot0Idx].read_lock = 1; + end + if ((`gmv(ral.plat_owner_auth_slot1_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatOwnerAuthSlot1Idx].read_lock = 1; + end + if ((`gmv(ral.plat_owner_auth_slot2_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatOwnerAuthSlot2Idx].read_lock = 1; + end + if ((`gmv(ral.plat_owner_auth_slot3_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[PlatOwnerAuthSlot3Idx].read_lock = 1; + end + if ((`gmv(ral.ext_nvm_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[ExtNvmIdx].read_lock = 1; + end + if ((`gmv(ral.rom_patch_read_lock) == 0) && !$urandom_range(0, 4)) begin + forced_mubi_part_access[RomPatchIdx].read_lock = 1; + end + + + // Digest read locks + if ((`gmv(ral.secret0_digest[0]) || + `gmv(ral.secret0_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[Secret0Idx].read_lock = 1; + end + if ((`gmv(ral.secret1_digest[0]) || + `gmv(ral.secret1_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[Secret1Idx].read_lock = 1; + end + if ((`gmv(ral.secret2_digest[0]) || + `gmv(ral.secret2_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[Secret2Idx].read_lock = 1; + end + if ((`gmv(ral.secret3_digest[0]) || + `gmv(ral.secret3_digest[1])) && + !$urandom_range(0, 4)) begin + forced_mubi_part_access[Secret3Idx].read_lock = 1; + end + + foreach (forced_mubi_part_access[i]) begin + `uvm_info(`gfn, $sformatf("partition %0d inject mubi value: read=%0b, write=%0b", i, + forced_mubi_part_access[i].read_lock, forced_mubi_part_access[i].write_lock), UVM_HIGH) + end + + cfg.otp_ctrl_vif.force_part_access_mubi(forced_mubi_part_access); + end + endtask + + // This function backdoor inject error according to ecc_err: + // - for OtpEccUncorrErr it injects a 2 bit error + // - for OtpEccCorrErr it injects a 1 bit error + // This function will output original backdoor read data for the given address + // so the error can be cleared. + virtual function bit [TL_DW-1:0] backdoor_inject_ecc_err(bit [TL_DW-1:0] addr, + otp_ecc_err_e ecc_err); + bit [TL_DW-1:0] val; + addr = {addr[TL_DW-1:2], 2'b00}; + val = cfg.mem_bkdr_util_h.read32(addr); + if (ecc_err == OtpNoEccErr || addr >= (LifeCycleOffset + LifeCycleSize)) return val; + + // Backdoor read and write back with error bits + cfg.mem_bkdr_util_h.inject_errors(addr, (ecc_err == OtpEccUncorrErr) ? 2 : 1); + `uvm_info(`gfn, $sformatf("original val %0h, addr %0h, err_type %0s", + val, addr, ecc_err.name), UVM_HIGH) + return val; + endfunction + + virtual task trigger_checks(bit [1:0] val, + bit wait_done = 1, + otp_ecc_err_e ecc_err = OtpNoEccErr); + bit [TL_DW-1:0] backdoor_rd_val, addr; + + // If ECC and check error happens in the same consistency check, the scb cannot predict which + // error will happen first, so it cannot correctly predict the error status and alert + // triggered. + // So the sequence only allows one error at a time. + if (get_field_val(ral.check_trigger.consistency, val) && + `gmv(ral.check_timeout) > 0 && `gmv(ral.check_timeout) <= CHK_TIMEOUT_CYC) begin + ecc_err = OtpNoEccErr; + end + + // Backdoor write ECC errors + if (ecc_err != OtpNoEccErr) begin + int part_idx = $urandom_range(HwCfg0Idx, LifeCycleIdx); + + // Only HW cfgs check digest correctness + if (part_idx != LifeCycleIdx) begin + addr = $urandom_range(0, 1) ? PART_OTP_DIGEST_ADDRS[part_idx] << 2 : + (PART_OTP_DIGEST_ADDRS[part_idx] + 1) << 2; + end else begin + addr = $urandom_range(LifeCycleOffset, LifeCycleOffset + LifeCycleSize - 1); + addr = {addr[TL_DW-1:2], 2'b00}; + end + backdoor_rd_val = backdoor_inject_ecc_err(addr, ecc_err); + cfg.ecc_chk_err[part_idx] = ecc_err; + end + + csr_wr(ral.check_trigger, val); + if (wait_done && val) csr_spinwait(ral.status.check_pending, 0); + + if (ecc_err != OtpNoEccErr) begin + cfg.mem_bkdr_util_h.write32(addr, backdoor_rd_val); + cfg.ecc_chk_err = '{default: OtpNoEccErr}; + end + endtask + + // For a DAI interface operation to finish, either way until status dai_idle is set, or check + // err_code and see if fatal error happened. In any case, break out of this wait if there + // is a need to stop transaction generators, since a spinwait will otherwise just stop + // when it times-out. + virtual task wait_dai_op_done(); + if (cfg.stop_transaction_generators()) return; + fork begin + fork + begin + csr_spinwait(.ptr(ral.status.dai_idle), + .exp_data(1), + .timeout_ns(op_done_spinwait_timeout_ns), + .spinwait_delay_ns($urandom_range(0, 5))); + end + begin + forever begin + bit [TL_DW-1:0] err_val; + cfg.clk_rst_vif.wait_clks(1); + csr_rd(.ptr(ral.err_code[DaiIdx].err_code), .value(err_val), .backdoor(1)); + // Break if error will cause fatal alerts + if (err_val inside {OTP_TERMINAL_ERRS}) break; + end + end + begin + forever begin + cfg.clk_rst_vif.wait_clks(1); + if (cfg.stop_transaction_generators()) break; + end + end + join_any + wait_no_outstanding_access(); + disable fork; + end join + endtask + + virtual task rd_and_clear_intrs(); + bit [TL_DW-1:0] val; + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check == 0) begin + csr_rd(ral.intr_state, val); + // In case lc_program request is issued after intr_state read + if (cfg.otp_ctrl_vif.lc_prog_no_sta_check == 0) csr_wr(ral.intr_state, val); + end + endtask + + // first two or three LSB bits of DAI address can be randomized based on if it is secret + virtual function bit [TL_AW-1:0] randomize_dai_addr(bit [TL_AW-1:0] dai_addr); + if (is_secret(dai_addr)) begin + bit [2:0] rand_addr = $urandom(); + randomize_dai_addr = {dai_addr[TL_DW-1:3], rand_addr}; + end else begin + bit [1:0] rand_addr = $urandom(); + randomize_dai_addr = {dai_addr[TL_DW-1:2], rand_addr}; + end + endfunction + + // The following interface requests are separated to blocking and non-blocking accesses. + // The non-blocking access is mainly used when lc_escalate_en is On, which acts like a reset and + // move all design state machines to ErrorSt. Thus pending request will never get a response + // until reset. + virtual task req_sram_key(int index, bit blocking = default_req_blocking); + // Return if the request is already high, this is mainly due to lc_escalate_en On. + if (cfg.m_sram_pull_agent_cfg[index].vif.req === 1'b1) return; + + if (blocking) begin + req_sram_key_sub(index); + end else begin + fork + begin + req_sram_key_sub(index); + end + join_none; + // Add #0 to ensure that this thread starts executing before any subsequent call + #0; + end + endtask + + virtual task req_sram_key_sub(int index); + push_pull_host_seq#(.DeviceDataWidth(SRAM_DATA_SIZE)) sram_pull_seq; + wait(cfg.under_reset == 0); + `uvm_create_on(sram_pull_seq, p_sequencer.sram_pull_sequencer_h[index]); + `DV_CHECK_RANDOMIZE_FATAL(sram_pull_seq) + `uvm_send(sram_pull_seq) + endtask + + virtual task req_all_sram_keys(bit blocking = default_req_blocking); + for (int i = 0; i < NumSramKeyReqSlots; i++) req_sram_key(i, blocking); + endtask + + virtual task req_otbn_key(bit blocking = default_req_blocking); + if (cfg.m_otbn_pull_agent_cfg.vif.req === 1'b1) return; + + if (blocking) begin + req_otbn_key_sub(); + end else begin + fork + begin + req_otbn_key_sub(); + end + join_none; + // Add #0 to ensure that this thread starts executing before any subsequent call + #0; + end + endtask + + virtual task req_otbn_key_sub(); + push_pull_host_seq#(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_pull_seq; + wait(cfg.under_reset == 0); + `uvm_create_on(otbn_pull_seq, p_sequencer.otbn_pull_sequencer_h); + `DV_CHECK_RANDOMIZE_FATAL(otbn_pull_seq) + `uvm_send(otbn_pull_seq) + endtask + + virtual task req_lc_transition(bit check_intr = 0, + bit blocking = default_req_blocking, + bit wr_blank_err = !write_unused_addr); + if (cfg.m_lc_prog_pull_agent_cfg.vif.req === 1'b1) return; + + if (blocking) begin + req_lc_transition_sub(check_intr, wr_blank_err); + end else begin + fork + begin + req_lc_transition_sub(check_intr, wr_blank_err); + end + join_none; + // Add #0 to ensure that this thread starts executing before any subsequent call + #0; + end + endtask + + virtual task req_lc_transition_sub(bit check_intr = 0, bit wr_blank_err = !write_unused_addr); + lc_ctrl_state_pkg::lc_cnt_e next_lc_cnt; + lc_ctrl_state_pkg::dec_lc_state_e next_lc_state, lc_state_dec; + bit [TL_DW-1:0] intr_val; + push_pull_host_seq#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1)) + lc_prog_pull_seq; + wait(cfg.under_reset == 0); + `uvm_create_on(lc_prog_pull_seq, p_sequencer.lc_prog_pull_sequencer_h); + + if (!wr_blank_err) begin + // Find valid next state and next cnt using lc_ctrl_dv_utils_pkg. + // If terminal state or max LcCnt reaches, will not program any new data. + if ((lc_state != LcStScrap) && (lc_cnt != LcCnt24)) begin + lc_state_dec = lc_ctrl_dv_utils_pkg::dec_lc_state(lc_state); + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(next_lc_state, + next_lc_state inside {VALID_NEXT_STATES[lc_state_dec]};) + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(next_lc_cnt, next_lc_cnt > lc_cnt;) + lc_state = lc_ctrl_dv_utils_pkg::encode_lc_state(next_lc_state); + lc_cnt = next_lc_cnt; + end + cfg.m_lc_prog_pull_agent_cfg.add_h_user_data({lc_cnt, lc_state}); + end + + `DV_CHECK_RANDOMIZE_FATAL(lc_prog_pull_seq) + `uvm_send(lc_prog_pull_seq) + + if (check_intr) rd_and_clear_intrs(); + endtask + + // This test access OTP_CTRL's test_access memory. The open-sourced code only test if the access + // is valid. Please override this task in proprietary OTP. + virtual task otp_test_access(); + if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin + repeat (10) begin + bit [TL_DW-1:0] data; + bit test_access_en; + bit [TL_AW-1:0] rand_addr = $urandom_range(0, NUM_PRIM_REG - 1) * 4; + bit [TL_AW-1:0] tlul_addr = + cfg.ral_models["otp_macro_prim_reg_block"].get_addr_from_offset(rand_addr); + if (cfg.stop_transaction_generators()) break; + rand_drive_dft_en(); + `DV_CHECK_STD_RANDOMIZE_FATAL(data) + test_access_en = cfg.otp_ctrl_vif.lc_dft_en_i == lc_ctrl_pkg::On; + tl_access(.addr(tlul_addr), .write(1), .data(data), .exp_err_rsp(~test_access_en), + .tl_sequencer_h(p_sequencer.tl_sequencer_hs["otp_macro_prim_reg_block"])); + tl_access(.addr(tlul_addr), .write(0), .data(data), .exp_err_rsp(~test_access_en), + .tl_sequencer_h(p_sequencer.tl_sequencer_hs["otp_macro_prim_reg_block"])); + end + end + endtask + + // Empty task, only drive it under `otp_ctrl_test_access_vseq` + virtual task rand_drive_dft_en(); + endtask +endclass : otp_ctrl_base_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_callback_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_callback_vseq.sv new file mode 100644 index 00000000000..155e6f5e361 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_callback_vseq.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// A sequence hook to attach to otp_ctrl_base_vseq. +class otp_ctrl_callback_vseq extends cip_base_vseq #( + .RAL_T (otp_ctrl_core_reg_block), + .CFG_T (otp_ctrl_env_cfg), + .COV_T (otp_ctrl_env_cov), + .VIRTUAL_SEQUENCER_T (otp_ctrl_virtual_sequencer) + ); + `uvm_object_utils(otp_ctrl_callback_vseq) + `uvm_object_new + + virtual task dut_init_callback(); + // Do nothing but can be overridden in closed source environment. + endtask + + virtual task post_otp_pwr_init(); + // Do nothing but can be overridden in closed source environment. + endtask : post_otp_pwr_init +endclass : otp_ctrl_callback_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_check_fail_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_check_fail_vseq.sv new file mode 100644 index 00000000000..061ebe96a30 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_check_fail_vseq.sv @@ -0,0 +1,32 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This sequence creates the following check failure scenarios: +// 1. Check timeout +// 2. Correctable ECC check error +// 3. Uncorrectable ECC error +class otp_ctrl_check_fail_vseq extends otp_ctrl_dai_lock_vseq; + `uvm_object_utils(otp_ctrl_check_fail_vseq) + + `uvm_object_new + + constraint ecc_otp_err_c { + ecc_otp_err inside {OtpEccCorrErr, OtpNoEccErr}; + } + + constraint ecc_chk_err_c { + ecc_chk_err dist {OtpNoEccErr :/ 1, + OtpEccCorrErr :/ 1, + OtpEccUncorrErr :/1 }; + } + + // 50% chance of having a check timeout + // Because of the regwen, even though we constrain the timeout value, it might not apply to the + // DUT. + constraint check_timeout_val_c { + check_timeout_val dist {[1 : CHK_TIMEOUT_CYC] :/ 1, + [100_000 :'1] :/ 1}; + } + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv new file mode 100644 index 00000000000..9c02a91675a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv @@ -0,0 +1,235 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class otp_ctrl_common_vseq extends otp_ctrl_base_vseq; + `uvm_object_utils(otp_ctrl_common_vseq) + + rand bit [TL_DW-1:0] dai_addr, wdata0, wdata1; + rand port_drive_condition_e reset_drive_cond; + + string prim_otp_alert_name = "fatal_prim_otp_alert"; + string integ_err_alert_name = "fatal_bus_integ_error"; + + // This flag is used to identify if the sec_cm or tl_intg_err uses prim_otp_tl_i/o. + protected bit is_prim_otp; + + constraint dai_addr_c { + dai_addr dist { + [0 : (PartInfo[LifeCycleIdx].offset - 1)] :/ 1, + [PartInfo[LifeCycleIdx].offset : {OTP_ADDR_WIDTH{1'b1}}] :/ 1}; + } + + constraint reset_drive_cond_c { + reset_drive_cond dist { + DriveRandomly :/ 7, + DuringOTPDaiBusy :/ 1, + DuringOTPRead :/ 1, + DuringOTPDaiDigest :/ 1 + }; + } + + constraint num_trans_c { + num_trans inside {[1:2]}; + } + `uvm_object_new + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(reset_kind); + // drive dft_en pins to access the test_access memory + cfg.otp_ctrl_vif.drive_lc_dft_en(lc_ctrl_pkg::On); + // once turn on lc_dft_en register, will need some time to update the state register + // two clock cycles for lc_async mode, one clock cycle for driving dft_en, one more clock cycle + // so there is no racing condition. + if (cfg.en_dv_cdc) cfg.clk_rst_vif.wait_clks(5); + else cfg.clk_rst_vif.wait_clks(3); + endtask + + virtual task body(); + if (common_seq_type == "sec_cm_fi") begin + // OTP_CTRL has many sec_cm items, so too many iterations of this test will consume too much + // simulation time and eventually causes timeout. So we reduce to 10 iterations. + run_sec_cm_fi_vseq(10); + end else begin + run_common_vseq_wrapper(num_trans); + end + endtask : body + + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + // For stress_all_with_rand_reset test only - backdoor clear OTP memory, + // and re-initialize OTP_ctrl after reset. + if (common_seq_type == "stress_all_with_rand_reset") begin + cfg.otp_ctrl_vif.release_part_access_mubi(); + cfg.otp_ctrl_vif.drive_lc_escalate_en(lc_ctrl_pkg::Off); + // Set dft_en to On to allow the csr_test to check all registers' default value after reset. + cfg.otp_ctrl_vif.drive_lc_dft_en(lc_ctrl_pkg::On); + otp_ctrl_init(); + otp_pwr_init(); + super.apply_resets_concurrently(reset_duration_ps); + cfg.en_scb = 1; + end else begin + super.apply_resets_concurrently(reset_duration_ps); + end + clear_seq_flags(); + endtask + + virtual task wait_to_issue_reset(uint reset_delay_bound); + `DV_CHECK_MEMBER_RANDOMIZE_FATAL(reset_drive_cond) + case (reset_drive_cond) + DriveRandomly: begin + super.wait_to_issue_reset(reset_delay_bound); + end + DuringOTPDaiBusy: begin + `DV_SPINWAIT_EXIT( + wait (do_otp_wr); + cfg.clk_rst_vif.wait_clks($urandom_range(1, 70));, + super.wait_to_issue_reset(reset_delay_bound);) + #($urandom_range(0, cfg.clk_rst_vif.clk_period_ps) * 1ps); + end + DuringOTPDaiDigest: begin + `DV_SPINWAIT_EXIT( + wait (do_digest_cal); + cfg.clk_rst_vif.wait_clks($urandom_range(1, 350));, + super.wait_to_issue_reset(reset_delay_bound);) + #($urandom_range(0, cfg.clk_rst_vif.clk_period_ps) * 1ps); + end + DuringOTPRead: begin + `DV_SPINWAIT_EXIT( + wait (do_otp_rd); + cfg.clk_rst_vif.wait_clks($urandom_range(1, 10));, + super.wait_to_issue_reset(reset_delay_bound);) + #($urandom_range(0, cfg.clk_rst_vif.clk_period_ps) * 1ps); + end + default: `uvm_fatal(`gfn, $sformatf("Unsupported reset_drive_cond %0d", reset_drive_cond)) + endcase + endtask : wait_to_issue_reset + + // This task overrides the check for `prim_onehot_check` and `tl_intg_error`. + // Alerts coming from the `prim_otp` module will only bypass OTP_CTRL, it won't affect the + // OTP_CTRL and will fire its own alerts. + virtual task check_tl_intg_error_response(); + if (is_prim_otp) begin + repeat ($urandom_range(5, 20)) begin + wait_alert_trigger(prim_otp_alert_name, .wait_complete(1)); + end + end else begin + super.check_tl_intg_error_response(); + end + endtask + + virtual task check_sec_cm_alert(string sec_type_name, string alert_name); + `uvm_info(`gfn, $sformatf("expected fatal alert is triggered for %s", + sec_type_name), UVM_LOW) + + // This is a fatal alert and design keeps sending it until reset is issued. + // Check alerts are triggered for a few times + repeat (5) begin + wait_alert_trigger(alert_name, .wait_complete(1)); + end + endtask + + // In tl_intg_err test, override this task to set is_prim_otp flag. + virtual task run_tl_intg_err_vseq_sub(string ral_name); + if (ral_name == "otp_ctrl_core_reg_block") is_prim_otp = 0; + else is_prim_otp = 1; + super.run_tl_intg_err_vseq_sub(ral_name); + endtask + + virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy); + bit [TL_DW-1:0] exp_status_val, rdata0, rdata1; + string prim_otp_alert_name = "fatal_prim_otp_alert"; + string integ_err_alert_name = "fatal_bus_integ_error"; + + // Alerts coming from the `u_tlul_lc_gate` module will only trigger bus_integrity alerts, and + // bus_integrity related status. + // This error won't local escalate to OTP partitions. + if (!uvm_re_match("*.u_tlul_lc_gate*", if_proxy.path)) begin + check_sec_cm_alert(if_proxy.sec_cm_type.name, integ_err_alert_name); + + exp_status_val[OtpBusIntegErrorIdx] = 1; + exp_status_val[OtpDaiIdleIdx] = 1; + + // Alerts coming from the `otp_macro` module will only bypass OTP_CTRL, it won't affect the + // OTP_CTRL and will fire its own alerts. + end else if (is_prim_otp) begin + `uvm_info(`gfn, $sformatf("check otp_macro alert %s", if_proxy.sec_cm_type.name), + UVM_MEDIUM) + check_sec_cm_alert(if_proxy.sec_cm_type.name, prim_otp_alert_name); + + // All other errors triggers normal fatal alerts, and will locally escalate to other + // partitions. + end else begin + super.check_sec_cm_fi_resp(if_proxy); + + // Set expected status error val. + for (int i = 0; i <= OtpLciErrIdx; i++) exp_status_val[i] = 1; + if (!uvm_re_match("*.u_otp_ctrl_lfsr_timer*", if_proxy.path)) begin + exp_status_val[OtpLfsrFsmErrIdx] = 1; + end else if (!uvm_re_match("*u_otp_ctrl_kdi*", if_proxy.path)) begin + exp_status_val[OtpDerivKeyFsmErrIdx] = 1; + end else if (!uvm_re_match("*u_otp_ctrl_scrmbl*", if_proxy.path)) begin + exp_status_val[OtpScramblingFsmErrIdx] = 1; + end + + csr_rd_check(.ptr(ral.status), .compare_value(exp_status_val), .err_msg( + $sformatf("cm_fi status failed at injection %0s", if_proxy.sec_cm_type.name))); + + // Check OTP is locked after fault error. + `DV_CHECK_RANDOMIZE_FATAL(this) + is_valid_dai_op = 0; + + // Access OTP via DAI interface. + dai_wr(dai_addr, wdata0, wdata1); + dai_rd(dai_addr, rdata0, rdata1); + `DV_CHECK_EQ(rdata0, 0) + `DV_CHECK_EQ(rdata1, 0) + if (is_sw_part(dai_addr)) begin + uvm_reg_addr_t tlul_addr = cfg.ral.get_addr_from_offset(get_sw_window_offset(dai_addr)); + tl_access(.addr(tlul_addr), .write(0), .data(rdata0), .blocking(1), .check_rsp(1), + .exp_err_rsp(1), .exp_data('1)); + end + cal_hw_digests(); + write_sw_digests(); + + // Access OTP via app interface. + if ($urandom_range(0, 1)) req_otbn_key(0); + if ($urandom_range(0, 1)) req_all_sram_keys(0); + cfg.clk_rst_vif.wait_clks($urandom_range(10, 20)); + + csr_rd_check(.ptr(ral.status), .compare_value(exp_status_val), + .err_msg("status failure after OTP fatal fault error")); + end + endtask : check_sec_cm_fi_resp + + virtual function void sec_cm_fi_ctrl_svas(sec_cm_base_if_proxy if_proxy, bit enable); + case (if_proxy.sec_cm_type) + SecCmPrimCount: begin + if (!enable) begin + $assertoff(0, "tb.dut.gen_partitions[15].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $assertoff(0, "tb.dut.gen_partitions[16].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $assertoff(0, "tb.dut.gen_partitions[17].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $assertoff(0, "tb.dut.gen_partitions[18].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $assertoff(0, "tb.dut.gen_partitions[19].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $assertoff(0, "tb.dut.gen_partitions[20].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + end else begin + $asserton(0, "tb.dut.gen_partitions[15].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $asserton(0, "tb.dut.gen_partitions[16].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $asserton(0, "tb.dut.gen_partitions[17].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $asserton(0, "tb.dut.gen_partitions[18].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $asserton(0, "tb.dut.gen_partitions[19].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + $asserton(0, "tb.dut.gen_partitions[20].gen_buffered.u_part_buf.ScrmblDataKnown_A"); + end + end + SecCmPrimSparseFsmFlop, SecCmPrimDoubleLfsr, SecCmPrimOnehot: begin + // No assertion error. + end + default: `uvm_fatal(`gfn, $sformatf("unexpected sec_cm_type %s", if_proxy.sec_cm_type.name)) + endcase + + // Set the flag to store if the error injection is on prim_tlul_if or core_tlul_if and to + // discriminate between ctrl vs. macro fsm error. + if (!uvm_re_match("*.otp_macro.*", if_proxy.path)) is_prim_otp = 1; + else is_prim_otp = 0; + endfunction: sec_cm_fi_ctrl_svas + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_dai_errs_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_dai_errs_vseq.sv new file mode 100644 index 00000000000..c8ea43b32a6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_dai_errs_vseq.sv @@ -0,0 +1,51 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// otp_ctrl_dai_errs_vseq is developed to randomly read/write to any address within OTP: +// - A writeblank error will be triggered if write to a non-empty address +// - An access error will be triggered if write to lc partition via DAI interface, or if DAI write +// to digest addrs for non-sw partitions +class otp_ctrl_dai_errs_vseq extends otp_ctrl_dai_lock_vseq; + `uvm_object_utils(otp_ctrl_dai_errs_vseq) + + bit[31:0] exp_status; + `uvm_object_new + + // Only run one transition to avoid dut_init in the sequence. Because write-blank-error can cause + // otp_init failure. + constraint num_trans_c { + num_trans == 1; + num_dai_op inside {[100:500]}; + } + + constraint regwens_c { + check_trigger_regwen_val == 0; + } + + constraint rd_check_after_wr_c { + rand_wr == rand_rd; + } + + function void pre_randomize(); + this.dai_wr_blank_addr_c.constraint_mode(0); + this.no_access_err_c.constraint_mode(0); + this.dai_wr_digests_c.constraint_mode(0); + write_unused_addr = 0; + endfunction + + task body(); + do_apply_reset = 0; + if (do_lc_trans && !cfg.otp_ctrl_vif.alert_reqs) begin + req_lc_transition(do_lc_trans, lc_prog_blocking); + end + super.body(); + endtask + + virtual task post_start(); + expect_fatal_alerts = 1; + do_apply_reset = 1; + do_otp_ctrl_init = 1; + super.post_start(); + endtask +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_dai_lock_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_dai_lock_vseq.sv new file mode 100644 index 00000000000..a482363f850 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_dai_lock_vseq.sv @@ -0,0 +1,146 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// otp_ctrl_dai_lock_vseq is developed to read/write lock DAI interface by partitions, and request +// read/write access to check if correct status and error code is triggered + +// Partition's legal range covers offset to digest addresses, dai_rd/dai_wr function will +// randomize the address based on the granularity. +`define PART_ADDR_RANGE(i) \ + {[PartInfo[``i``].offset : (PartInfo[``i``].offset + PartInfo[``i``].size - 8)]} + +class otp_ctrl_dai_lock_vseq extends otp_ctrl_smoke_vseq; + `uvm_object_utils(otp_ctrl_dai_lock_vseq) + + `uvm_object_new + + // enable access_err for each cycle + constraint no_access_err_c {access_locked_parts == 1;} + + constraint num_trans_c { + num_trans inside {[1:10]}; + num_dai_op inside {[1:50]}; + } + + // the LC partition is always the last one + constraint partition_index_c {part_idx inside {[0:LifeCycleIdx]};} + + constraint dai_wr_legal_addr_c { + if (part_idx == VendorTestIdx) { + dai_addr inside `PART_ADDR_RANGE(VendorTestIdx); + } + if (part_idx == CreatorSwCfgIdx) { + dai_addr inside `PART_ADDR_RANGE(CreatorSwCfgIdx); + } + if (part_idx == OwnerSwCfgIdx) { + dai_addr inside `PART_ADDR_RANGE(OwnerSwCfgIdx); + } + if (part_idx == OwnershipSlotStateIdx) { + dai_addr inside `PART_ADDR_RANGE(OwnershipSlotStateIdx); + } + if (part_idx == RotCreatorAuthIdx) { + dai_addr inside `PART_ADDR_RANGE(RotCreatorAuthIdx); + } + if (part_idx == RotOwnerAuthSlot0Idx) { + dai_addr inside `PART_ADDR_RANGE(RotOwnerAuthSlot0Idx); + } + if (part_idx == RotOwnerAuthSlot1Idx) { + dai_addr inside `PART_ADDR_RANGE(RotOwnerAuthSlot1Idx); + } + if (part_idx == PlatIntegAuthSlot0Idx) { + dai_addr inside `PART_ADDR_RANGE(PlatIntegAuthSlot0Idx); + } + if (part_idx == PlatIntegAuthSlot1Idx) { + dai_addr inside `PART_ADDR_RANGE(PlatIntegAuthSlot1Idx); + } + if (part_idx == PlatOwnerAuthSlot0Idx) { + dai_addr inside `PART_ADDR_RANGE(PlatOwnerAuthSlot0Idx); + } + if (part_idx == PlatOwnerAuthSlot1Idx) { + dai_addr inside `PART_ADDR_RANGE(PlatOwnerAuthSlot1Idx); + } + if (part_idx == PlatOwnerAuthSlot2Idx) { + dai_addr inside `PART_ADDR_RANGE(PlatOwnerAuthSlot2Idx); + } + if (part_idx == PlatOwnerAuthSlot3Idx) { + dai_addr inside `PART_ADDR_RANGE(PlatOwnerAuthSlot3Idx); + } + if (part_idx == ExtNvmIdx) { + dai_addr inside `PART_ADDR_RANGE(ExtNvmIdx); + } + if (part_idx == RomPatchIdx) { + dai_addr inside `PART_ADDR_RANGE(RomPatchIdx); + } + if (part_idx == HwCfg0Idx) { + dai_addr inside `PART_ADDR_RANGE(HwCfg0Idx); + } + if (part_idx == HwCfg1Idx) { + dai_addr inside `PART_ADDR_RANGE(HwCfg1Idx); + } + if (part_idx == Secret0Idx) { + dai_addr inside `PART_ADDR_RANGE(Secret0Idx); + } + if (part_idx == Secret1Idx) { + dai_addr inside `PART_ADDR_RANGE(Secret1Idx); + } + if (part_idx == Secret2Idx) { + dai_addr inside `PART_ADDR_RANGE(Secret2Idx); + } + if (part_idx == Secret3Idx) { + dai_addr inside `PART_ADDR_RANGE(Secret3Idx); + } + if (part_idx == LifeCycleIdx) { + if (write_unused_addr) { + dai_addr inside {[PartInfo[LifeCycleIdx].offset : {OTP_ADDR_WIDTH{1'b1}}]}; + } else { + dai_addr inside `PART_ADDR_RANGE(LifeCycleIdx); + } + } + solve part_idx before dai_addr; + } + + constraint dai_wr_digests_c { + {dai_addr[TL_AW-1:2], 2'b0} dist { + { + VendorTestDigestOffset, + CreatorSwCfgDigestOffset, + OwnerSwCfgDigestOffset, + RotCreatorAuthDigestOffset, + RotOwnerAuthSlot0DigestOffset, + RotOwnerAuthSlot1DigestOffset, + PlatIntegAuthSlot0DigestOffset, + PlatIntegAuthSlot1DigestOffset, + PlatOwnerAuthSlot0DigestOffset, + PlatOwnerAuthSlot1DigestOffset, + PlatOwnerAuthSlot2DigestOffset, + PlatOwnerAuthSlot3DigestOffset, + RomPatchDigestOffset, + HwCfg0DigestOffset, + HwCfg1DigestOffset, + Secret0DigestOffset, + Secret1DigestOffset, + Secret2DigestOffset, + Secret3DigestOffset + } :/ 1, + [VendorTestOffset : '1] :/ 9 + }; + } + + virtual task pre_start(); + super.pre_start(); + is_valid_dai_op = 0; + endtask + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(reset_kind); + if ($urandom_range(0, 1)) begin + cfg.otp_ctrl_vif.drive_lc_creator_seed_sw_rw_en(get_rand_lc_tx_val(.t_weight(0))); + end + if ($urandom_range(0, 1)) begin + cfg.otp_ctrl_vif.drive_lc_owner_seed_sw_rw_en(get_rand_lc_tx_val(.t_weight(0))); + end + endtask + +endclass + +`undef PART_ADDR_RANGE diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_init_fail_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_init_fail_vseq.sv new file mode 100644 index 00000000000..19abb5e34c7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_init_fail_vseq.sv @@ -0,0 +1,235 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Otp_ctrl_init_fail_vseq is developed to check if otp_ctrl reacts correctly if initialization +// failed. +// Note that scoreboard is disabled in this test and all checks are done within this sequence. +// This test writes and reads to OTP_memory via DAI interface, then triggers digest calculations. +// Afterwards instead of issuing reset, this sequence continues to write to DAI interface. +// If any of the hardware partition is updated, then in next power cycle, the initialization will +// fail. +// If no check failure, we will random inject ECC errors to create init macro errors. +// We will also trigger sw partition ECC reg failure by forcing the ECC reg error output. +// +// This sequence will check the following items if OTP init failed with fatal error: +// - Otp_initialization failure triggers fatal alert +// - Status register reflect the correct error +// - Otp_ctrl's power init output stays 0 +// This sequence will check the following items if OTP init failed with correctable error: +// - Otp_initialization passed with power init output changes to 1 +// - Otp status and interrupt reflect the correct error message + +class otp_ctrl_init_fail_vseq extends otp_ctrl_smoke_vseq; + `uvm_object_utils(otp_ctrl_init_fail_vseq) + + `uvm_object_new + + rand uint num_to_lock_digests; + bit [NumPart-1:0] init_chk_err; + bit part_locked; + + // If num_to_lock_digests is larger than num_dai_op, that means there won't be OTP init check + // error, so this sequence will trigger ECC error instead. + // We set 25% possibility that OTP init check fails due to writing OTP after digest is locked. + constraint lock_digest_c {num_to_lock_digests < num_dai_op * 4;} + constraint num_iterations_c {num_dai_op inside {[20:100]};} + constraint ecc_otp_err_c { + $countones(ecc_otp_err) dist {OtpNoEccErr :/ 2, + OtpEccCorrErr :/ 2, + OtpEccUncorrErr :/ 1}; + } + + virtual task pre_start(); + super.pre_start(); + num_to_lock_digests.rand_mode(0); + endtask + + task body(); + bit [TL_DW-1:0] exp_status; + `uvm_info(`gfn, $sformatf("Number of dai operation is %0d, number to lock digest is %0d", + num_dai_op, num_to_lock_digests), UVM_MEDIUM) + + for (uint i = 0; i <= num_dai_op; i++) begin + bit [TL_DW-1:0] tlul_val; + if (cfg.stop_transaction_generators()) return; + + `DV_CHECK_RANDOMIZE_FATAL(this) + `uvm_info(`gfn, $sformatf("starting dai access seq %0d/%0d with addr %0h in partition %0d", + i, num_dai_op, dai_addr, part_idx), UVM_MEDIUM) + + if (i > num_to_lock_digests && PartInfo[part_idx].hw_digest && + !used_dai_addrs.exists(dai_addr)) begin + init_chk_err[part_idx] = 1; + end + + // OTP write via DAI + dai_wr(dai_addr, wdata0, wdata1); + + // OTP read via DAI, check data in scb + dai_rd(dai_addr, wdata0, wdata1); + + // If write sw partitions, check tlul window + if (is_sw_part(dai_addr)) begin + uvm_reg_addr_t tlul_addr = cfg.ral.get_addr_from_offset(get_sw_window_offset(dai_addr)); + tl_access(.addr(tlul_addr), .write(0), .data(tlul_val), .blocking(1), .check_rsp(0)); + end + + if (i == num_to_lock_digests) begin + cal_hw_digests('1); + part_locked = 1; + end + + csr_rd(ral.status, tlul_val); + end + + do_otp_ctrl_init = 0; + do_otp_pwr_init = 0; + cfg.en_scb = 0; + dut_init(); + + if (init_chk_err) begin + `uvm_info(`gfn, $sformatf("OTP_init check failure with init error = %0h", init_chk_err), + UVM_LOW) + foreach(init_chk_err[i]) begin + if (cfg.stop_transaction_generators()) break; + if (init_chk_err[i]) exp_status |= 1'b1 << i; + end + + check_otp_fatal_err("fatal_check_error", exp_status); + + // If not check error, force ECC correctable and uncorrectable error + end else begin + bit is_fatal, is_correctable; + bit [TL_DW-1:0] addr; + + for (int i = 0; i < NumPart; i++) begin + if (cfg.stop_transaction_generators()) return; + `DV_CHECK_RANDOMIZE_FATAL(this); + + if (PartInfo[i].sw_digest) begin + // During OTP init, SW partitions only read digest value + addr = PART_OTP_DIGEST_ADDRS[i] << 2; + end else begin + // During OTP init, non SW partitions read all value + addr = PartInfo[i].offset + $urandom_range(0, PartInfo[i].size - 1); + end + + void'(backdoor_inject_ecc_err(addr, ecc_otp_err)); + // VendorTest partition's ECC error is not fatal. + if (!is_fatal && ecc_otp_err == OtpEccUncorrErr && part_has_integrity(i)) begin + is_fatal = 1; + end else if (!is_correctable && ecc_otp_err == OtpEccCorrErr && part_has_integrity(i)) begin + is_correctable = 1; + end + if (ecc_otp_err != OtpNoEccErr && part_has_integrity(i)) exp_status[i] = 1; + end + + if (is_fatal) begin + // ECC uncorrectable error. + `uvm_info(`gfn, "OTP_init macro ECC uncorrectable failure", UVM_LOW) + check_otp_fatal_err("fatal_macro_error", exp_status); + end else if ($urandom_range(0, 1)) begin + + // Randomly force ECC reg in sw partitions to create a check failure. + // Totally three sw partitions, and each bit indexes a partition. + bit [NumPartUnbuf-1:0] sw_check_fail = $urandom_range(1, (1'b1< 1 && do_dut_init) dut_init(); + // after otp-init done, check status + cfg.clk_rst_vif.wait_clks(1); + if (!cfg.otp_ctrl_vif.lc_esc_on) begin + csr_rd_check(.ptr(ral.status.dai_idle), .compare_value(1)); + end + end + do_otp_ctrl_init = 0; + + `DV_CHECK_RANDOMIZE_FATAL(this) + // set consistency and integrity checks + csr_wr(ral.check_regwen, check_regwen_val); + csr_wr(ral.check_trigger_regwen, check_trigger_regwen_val); + csr_wr(ral.check_timeout, check_timeout_val); + trigger_checks(.val(check_trigger_val), .wait_done(1), .ecc_err(ecc_chk_err)); + + if (!$urandom_range(0, 9) && access_locked_parts) write_sw_rd_locks(); + + // Backdoor write mubi to values that are not true or false. + force_mubi_part_access(); + + if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs) begin + req_otbn_key(); + req_all_sram_keys(); + end + if (do_lc_trans && !cfg.otp_ctrl_vif.alert_reqs) begin + req_lc_transition(do_lc_trans, lc_prog_blocking); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + end + + for (int i = 0; i < num_dai_op; i++) begin + bit [TL_DW-1:0] rdata0, rdata1, backdoor_rd_val; + if (cfg.stop_transaction_generators()) break; + + `DV_CHECK_RANDOMIZE_FATAL(this) + // recalculate part_idx in case some test turn off constraint dai_wr_legal_addr_c + part_idx = part_idx_e'(get_part_index(dai_addr)); + `uvm_info(`gfn, $sformatf("starting dai access seq %0d/%0d with addr %0h in partition %0d", + i, num_dai_op, dai_addr, part_idx), UVM_HIGH) + + // OTP write via DAI + if (rand_wr && !digest_calculated[part_idx]) begin + dai_wr(dai_addr, wdata0, wdata1); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + end + + // Inject ECC error. + if (ecc_otp_err != OtpNoEccErr && dai_addr < LifeCycleOffset) begin + `uvm_info(`gfn, $sformatf("Injecting ecc error %0d at 0x%x", ecc_otp_err, dai_addr), + UVM_HIGH) + backdoor_rd_val = backdoor_inject_ecc_err(dai_addr, ecc_otp_err); + end + + if (rand_rd) begin + // OTP read via DAI, check data in scb + dai_rd(dai_addr, rdata0, rdata1); + end + + // if write sw partitions, check tlul window + if (is_sw_part(dai_addr) && rd_sw_tlul_rd) begin + uvm_reg_addr_t tlul_addr = cfg.ral.get_addr_from_offset(get_sw_window_offset(dai_addr)); + // tlul error rsp is checked in scoreboard + do_otp_rd = 1; + tl_access(.addr(tlul_addr), .write(0), .data(tlul_val), .blocking(1), .check_rsp(0)); + end + + // Backdoor restore injected ECC error, but should not affect fatal alerts. + if (ecc_otp_err != OtpNoEccErr && dai_addr < LifeCycleOffset) begin + `uvm_info(`gfn, $sformatf("Injecting ecc error %0d at 0x%x", ecc_otp_err, dai_addr), + UVM_HIGH) + cfg.mem_bkdr_util_h.write32({dai_addr[TL_DW-3:2], 2'b00}, backdoor_rd_val); + // Wait for two lock cycles to make sure the local escalation error propagates to other + // partitions and err_code reg. + cfg.clk_rst_vif.wait_clks(2); + end + + // Random lock sw partitions + if (!$urandom_range(0, 9) && access_locked_parts) write_sw_rd_locks(); + if (!$urandom_range(0, 9) && access_locked_parts) write_sw_digests(); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.direct_access_regwen), .value(tlul_val)); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.status), .value(tlul_val)); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + end + + // Read/write test access memory + otp_test_access(); + + // lock digests + `uvm_info(`gfn, "Trigger HW digest calculation", UVM_HIGH) + cal_hw_digests(); + if ($urandom_range(0, 1)) csr_rd(.ptr(ral.status), .value(tlul_val)); + + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + + if ($urandom_range(0, 1)) rd_digests(); + if (do_dut_init) dut_init(); + + // read and check digest in scb + rd_digests(); + + // send request to the interfaces again after partitions are locked + if (do_lc_trans && !cfg.otp_ctrl_vif.alert_reqs) begin + req_lc_transition(do_lc_trans, lc_prog_blocking); + if (cfg.otp_ctrl_vif.lc_prog_req == 0) begin + for (int k = 0; k <= LciIdx; k++) begin + csr_rd(.ptr(ral.err_code[k]), .value(tlul_val)); + end + end + end + + if (do_req_keys && !cfg.otp_ctrl_vif.alert_reqs && !cfg.smoke_test) begin + req_otbn_key(); + req_all_sram_keys(); + end + + end + + endtask : body + +endclass : otp_ctrl_smoke_vseq + +`undef PART_CONTENT_RANGE diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_stress_all_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_stress_all_vseq.sv new file mode 100644 index 00000000000..031f5a15d20 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_stress_all_vseq.sv @@ -0,0 +1,81 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Combine all otp_ctrl seqs (except below seqs) in one seq to run sequentially. +// Exception: - csr seq: requires scb to be disabled +// - regwen_vseq and parallel_lc_vseq: time sensitive thus require zero_delays +// - macro_errs_vseq and check_fail_vseq: require to write back to OTP once fatal +// error is triggered, thus does not handle random reset +// - partition_walk_vseq: assume OTP initial value is 0 +// - init_fail: requires resets in the middle of the sequence +class otp_ctrl_stress_all_vseq extends otp_ctrl_base_vseq; + `uvm_object_utils(otp_ctrl_stress_all_vseq) + + string seq_names[]; + + `uvm_object_new + + virtual function void assign_seq_names(); + seq_names = {"otp_ctrl_common_vseq", + "otp_ctrl_dai_lock_vseq", + "otp_ctrl_smoke_vseq", + "otp_ctrl_test_access_vseq", + "otp_ctrl_background_chks_vseq", + "otp_ctrl_parallel_lc_esc_vseq", + "otp_ctrl_parallel_lc_req_vseq", + "otp_ctrl_parallel_key_req_vseq", + "otp_ctrl_dai_errs_vseq", + "otp_ctrl_low_freq_read_vseq"}; + endfunction + + task body(); + assign_seq_names(); + + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + otp_ctrl_base_vseq otp_ctrl_vseq; + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(otp_ctrl_vseq, seq) + `uvm_info(`gfn, $sformatf("Starting sequence %s in stress_all", otp_ctrl_vseq.get_name()), + UVM_MEDIUM) + + // At the end of each vseq, design might enter terminal Error State, need to reset to + // recover. If upper seq disables do_apply_reset for this seq, then can't issue reset + // as upper seq may drive reset. + if (do_apply_reset) otp_ctrl_vseq.do_apply_reset = 1; + else otp_ctrl_vseq.do_apply_reset = 0; + + otp_ctrl_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(otp_ctrl_vseq) + if (seq_names[seq_idx] == "otp_ctrl_common_vseq") begin + otp_ctrl_common_vseq common_vseq; + `downcast(common_vseq, otp_ctrl_vseq); + common_vseq.common_seq_type = "intr_test"; + end + + // Pass local variables to next sequence due to randomly issued reset. + otp_ctrl_vseq.is_valid_dai_op = 0; + otp_ctrl_vseq.lc_prog_blocking = this.lc_prog_blocking; + otp_ctrl_vseq.digest_calculated = this.digest_calculated; + otp_ctrl_vseq.start(p_sequencer); + + this.lc_prog_blocking = otp_ctrl_vseq.lc_prog_blocking; + this.digest_calculated = otp_ctrl_vseq.digest_calculated; + + // This is for otp_ctrl_stress_all_with_rand_reset. + // We need to reset for each vseq, but in otp_ctrl_stress_all_with_rand_reset, reset should be + // issued in upper seq. So, wait forever until reset is issued and this vseq is killed by + // upper seq. + if (!do_apply_reset) wait(0); + + // This is only valid for stress_all sequence. + // For stress_all_with_rand_reset sequence, the logic will be gated at previous line and will + // enable scb again at `apply_resets_concurrently` task. + cfg.en_scb = 1; + end + endtask : body + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_test_access_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_test_access_vseq.sv new file mode 100644 index 00000000000..9a32ea14e50 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_test_access_vseq.sv @@ -0,0 +1,44 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class otp_ctrl_test_access_vseq extends otp_ctrl_dai_lock_vseq; + `uvm_object_utils(otp_ctrl_test_access_vseq) + + `uvm_object_new + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(reset_kind); + + // Drive dft_en pins to access the test_access memory. + cfg.otp_ctrl_vif.drive_lc_dft_en(lc_ctrl_pkg::On); + + // Once turn on lc_dft_en register, will need some time to update the state register + // two clock cycles for lc_async mode, one clock cycle for driving dft_en. + if (cfg.en_dv_cdc) cfg.clk_rst_vif.wait_clks(4); + else cfg.clk_rst_vif.wait_clks(3); + endtask + + // Avoid back-to-back lc_dft_en initializations with random values since CDC can cause + // temporary On values when transitioning between arbitrary values. This is not a realistic + // attack mode since + // - The value is always driven as On or Off in hardware, + // - Mubi cannot protect against all bits being glitched, + // - getting an ON value due to CDC requires the mubi values before and after the CDC transition + // to have close enough Hamming distance to On, and is as hard or harder than glitching all + // bits to On. + virtual task rand_drive_dft_en(); + static bit phase; + super.rand_drive_dft_en(); + // 25% chance drive lc_dft_en to a random value. + if ($urandom_range(0, 3) == 3) begin + cfg.otp_ctrl_vif.drive_lc_dft_en(get_rand_lc_tx_val( + .t_weight(1), .f_weight(1), .other_weight(phase))); + phase = !phase; + // Once turn on lc_dft_en register, will need some time to update the state register + // two clock cycles for lc_async mode, one clock cycle for driving dft_en. + if (cfg.en_dv_cdc) cfg.clk_rst_vif.wait_clks(4); + else cfg.clk_rst_vif.wait_clks(3); + end + endtask +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_vseq_list.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_vseq_list.sv new file mode 100644 index 00000000000..3cf96c1b521 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_vseq_list.sv @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "otp_ctrl_callback_vseq.sv" +`include "otp_ctrl_base_vseq.sv" +`include "otp_ctrl_wake_up_vseq.sv" +`include "otp_ctrl_smoke_vseq.sv" +`include "otp_ctrl_common_vseq.sv" +`include "otp_ctrl_partition_walk_vseq.sv" +`include "otp_ctrl_low_freq_read_vseq.sv" +`include "otp_ctrl_init_fail_vseq.sv" +`include "otp_ctrl_dai_lock_vseq.sv" +`include "otp_ctrl_dai_errs_vseq.sv" +`include "otp_ctrl_macro_errs_vseq.sv" +`include "otp_ctrl_background_chks_vseq.sv" +`include "otp_ctrl_check_fail_vseq.sv" +`include "otp_ctrl_parallel_base_vseq.sv" +`include "otp_ctrl_parallel_key_req_vseq.sv" +`include "otp_ctrl_parallel_lc_req_vseq.sv" +`include "otp_ctrl_parallel_lc_esc_vseq.sv" +`include "otp_ctrl_regwen_vseq.sv" +`include "otp_ctrl_test_access_vseq.sv" +`include "otp_ctrl_stress_all_vseq.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_wake_up_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_wake_up_vseq.sv new file mode 100644 index 00000000000..8a048e5e560 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/env/seq_lib/otp_ctrl_wake_up_vseq.sv @@ -0,0 +1,56 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class otp_ctrl_wake_up_vseq extends otp_ctrl_base_vseq; + `uvm_object_utils(otp_ctrl_wake_up_vseq) + + `uvm_object_new + + virtual task otp_ctrl_init(); + super.otp_ctrl_init(); + csr_wr(ral.intr_enable, en_intr); + endtask + + task body(); + bit [TL_DW-1:0] rand_addr = $urandom_range(CreatorSwCfgOffset, + CreatorSwCfgOffset + CreatorSwCfgSize); + // check status + cfg.clk_rst_vif.wait_clks(1); + + // turn on all intr_enable + csr_wr(ral.intr_enable, (1'b1 << NumOtpCtrlIntr) - 1); + csr_rd_check(.ptr(ral.status.dai_idle), .compare_value(1)); + + // write seq + csr_wr(ral.direct_access_address, rand_addr); + csr_wr(ral.direct_access_wdata[0], '1); + csr_wr(ral.direct_access_cmd, 2); + wait(cfg.intr_vif.pins[OtpOperationDone] == 1); + csr_wr(ral.intr_state, 1'b1 << OtpOperationDone); + + // read seq + csr_wr(ral.direct_access_address, rand_addr); + csr_wr(ral.direct_access_cmd, 1); + wait(cfg.intr_vif.pins[OtpOperationDone] == 1); + csr_rd_check(.ptr(ral.direct_access_rdata[0]), .compare_value('1)); + csr_wr(ral.intr_state, 1'b1 << OtpOperationDone); + + // digest sw error seq + csr_wr(ral.direct_access_address, CreatorSwCfgOffset + 2); + csr_wr(ral.direct_access_cmd, 4); + wait(cfg.intr_vif.pins[OtpOperationDone] == 1); + wait(cfg.intr_vif.pins[OtpErr] == 1); + csr_wr(ral.intr_state, (1'b1 << NumOtpCtrlIntr) - 1); + + // digest hw seq + csr_wr(ral.direct_access_address, HwCfg0DigestOffset); + csr_wr(ral.direct_access_cmd, 4); + wait(cfg.intr_vif.pins[OtpOperationDone] == 1); + csr_wr(ral.intr_state, 1'b1 << OtpOperationDone); + + // check all interrupts are cleared + csr_rd_check(.ptr(ral.intr_state), .compare_value(0)); + endtask : body + +endclass : otp_ctrl_wake_up_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/otp_ctrl_sim.core b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/otp_ctrl_sim.core new file mode 100644 index 00000000000..4b695b5e35a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/otp_ctrl_sim.core @@ -0,0 +1,39 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:otp_ctrl_sim:0.1 +description: "OTP_CTRL DV sim target" + +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:otp_ctrl_macro_pkg + - lowrisc:darjeeling_no_ibex_ip:otp_ctrl + - lowrisc:ip:otp_macro + + files_dv: + depend: + - lowrisc:dv:mem_bkdr_util + - lowrisc:darjeeling_no_ibex_dv:otp_ctrl_test + - lowrisc:darjeeling_no_ibex_dv:otp_ctrl_sva + - lowrisc:darjeeling_no_ibex_dv:otp_ctrl_cov + # TODO(#27347): prim_pkg is deprecated + - lowrisc:prim:prim_pkg + files: + - tb.sv + file_type: systemVerilogSource + +targets: + default: &default_target + toplevel: tb + filesets: + - files_rtl + - files_dv + + sim: + <<: *default_target + default_tool: vcs + + lint: + <<: *default_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/otp_ctrl_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/otp_ctrl_sim_cfg.hjson new file mode 100644 index 00000000000..129182d4937 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/otp_ctrl_sim_cfg.hjson @@ -0,0 +1,179 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: otp_ctrl + + // Top level dut name (sv module). + dut: otp_ctrl + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_dv:otp_ctrl_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/otp_ctrl_testplan.hjson" + + // RAL spec - used to generate the RAL model. + ral_spec: "{self_dir}/../data/otp_ctrl.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Config files to get the correct flags for crypto_dpi_prince + "{proj_root}/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"] + + en_build_modes: ["{tool}_crypto_dpi_prince_build_opts"] + + build_modes: [ + // Sim mode that enables build randomization. See the `build_seed` mode + // defined in `hw/dv/tools/dvsim/common_modes.hjson` for more details. + { + name: build_seed + pre_build_cmds: ["cd {proj_root} && ./util/design/gen-otp-mmap.py --seed {seed} --topname darjeeling_no_ibex"] + is_sim_mode: 1 + } + ] + + // Add additional tops for simulation. + sim_tops: ["otp_ctrl_bind", "otp_ctrl_cov_bind", + "sec_cm_prim_sparse_fsm_flop_bind", + "sec_cm_prim_count_bind", + "sec_cm_prim_double_lfsr_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Add OTP_CTRL specific exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov/otp_ctrl_cov_unr_excl.el", + "{self_dir}/cov/otp_ctrl_cov_fsm_unr_excl.el"] + + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {dv_root}/tools/vcs/cover.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/otp_ctrl_cover.cfg" + } + ] + + // Default UVM test and seq class name. + uvm_test: otp_ctrl_base_test + uvm_test_seq: otp_ctrl_base_vseq + + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: otp_ctrl_wake_up + uvm_test_seq: otp_ctrl_wake_up_vseq + run_opts: ["+en_scb=0"] + reseed: 1 + } + + { + name: otp_ctrl_smoke + uvm_test_seq: otp_ctrl_smoke_vseq + } + + { + name: otp_ctrl_partition_walk + uvm_test_seq: otp_ctrl_partition_walk_vseq + reseed: 1 + } + + { + name: otp_ctrl_low_freq_read + uvm_test_seq: otp_ctrl_low_freq_read_vseq + reseed: 1 + } + + { + name: otp_ctrl_init_fail + uvm_test_seq: otp_ctrl_init_fail_vseq + reseed: 300 + } + { + name: otp_ctrl_background_chks + uvm_test_seq: otp_ctrl_background_chks_vseq + reseed: 10 + } + + { + name: otp_ctrl_parallel_lc_req + uvm_test_seq: otp_ctrl_parallel_lc_req_vseq + run_opts: ["+zero_delays=1"] + } + + { + name: otp_ctrl_parallel_lc_esc + uvm_test_seq: otp_ctrl_parallel_lc_esc_vseq + reseed: 200 + } + + { + name: otp_ctrl_dai_lock + uvm_test_seq: otp_ctrl_dai_lock_vseq + } + + { + name: otp_ctrl_dai_errs + uvm_test_seq: otp_ctrl_dai_errs_vseq + } + + { + name: otp_ctrl_check_fail + uvm_test_seq: otp_ctrl_check_fail_vseq + } + + { + name: otp_ctrl_macro_errs + uvm_test_seq: otp_ctrl_macro_errs_vseq + } + + { + name: otp_ctrl_parallel_key_req + uvm_test_seq: otp_ctrl_parallel_key_req_vseq + } + + { + name: otp_ctrl_regwen + uvm_test_seq: otp_ctrl_regwen_vseq + // This test is to check reg programming is gated when direct_access_regwen=0 + // Thus this test is timing sensitive + run_opts: ["+zero_delays=1"] + } + + { + name: otp_ctrl_test_access + uvm_test_seq: otp_ctrl_test_access_vseq + } + + { + name: "{name}_stress_all_with_rand_reset" + reseed: 100 + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["otp_ctrl_smoke"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/sva/otp_ctrl_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/sva/otp_ctrl_bind.sv new file mode 100644 index 00000000000..ec0def2037b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/sva/otp_ctrl_bind.sv @@ -0,0 +1,32 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module otp_ctrl_bind; + + bind otp_ctrl tlul_assert #( + .EndpointType("Device") + ) core_tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (core_tl_i), + .d2h (core_tl_o) + ); + + bind otp_macro tlul_assert #( + .EndpointType("Device") + ) prim_tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (prim_tl_i), + .d2h (prim_tl_o) + ); + + bind otp_ctrl otp_ctrl_core_csr_assert_fpv otp_ctrl_core_csr_assert ( + .clk_i, + .rst_ni, + .h2d (core_tl_i), + .d2h (core_tl_o) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/sva/otp_ctrl_sva.core b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/sva/otp_ctrl_sva.core new file mode 100644 index 00000000000..b1c6d490bc8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/sva/otp_ctrl_sva.core @@ -0,0 +1,39 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:otp_ctrl_sva:0.1 +description: "OTP_CTRL assertion modules and bind file." + +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - otp_ctrl_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:darjeeling_no_ibex_ip:otp_ctrl + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/otp_ctrl.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: otp_ctrl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tb.sv new file mode 100644 index 00000000000..caf1435deaa --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tb.sv @@ -0,0 +1,246 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import otp_ctrl_env_pkg::*; + import otp_ctrl_test_pkg::*; + import otp_ctrl_reg_pkg::*; + import mem_bkdr_util_pkg::mem_bkdr_util; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // TB base test ENV_T & CFG_T specification + // + // Specify the parameters for the otp_ctrl_base_test + // This will invoke the UVM registry and link this test type to + // the name 'otp_ctrl_base_test' as a test name passed by UVM_TESTNAME + // + // This is done explicitly only for the prim_pkg::ImplGeneric implementation + // since partner base tests inherit from otp_ctrl_base_test#(CFG_T, ENV_T) and + // specify directly (CFG_T, ENV_T) via the class extension and use a different + // UVM_TESTNAME + if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_spec_base_test_params + typedef otp_ctrl_base_test #(.CFG_T(otp_ctrl_env_cfg), + .ENV_T(otp_ctrl_env)) otp_ctrl_base_test_t; + end + + wire clk, rst_n; + + // These connect the controller to the macro. + wire otp_ctrl_macro_pkg::otp_ctrl_macro_req_t otp_ctrl_macro_req; + wire otp_ctrl_macro_pkg::otp_ctrl_macro_rsp_t otp_ctrl_macro_rsp; + + wire otp_ctrl_pkg::otbn_otp_key_req_t otbn_req; + wire otp_ctrl_pkg::otbn_otp_key_rsp_t otbn_rsp; + wire otp_ctrl_pkg::sram_otp_key_req_t[NumSramKeyReqSlots-1:0] sram_req; + wire otp_ctrl_pkg::sram_otp_key_rsp_t[NumSramKeyReqSlots-1:0] sram_rsp; + + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire intr_otp_operation_done, intr_otp_error; + + // Output from close-source OTP, not checked in open-source env. + wire otp_macro_pkg::otp_ast_req_t ast_req; + wire [7:0] otp_obs_o; + + tlul_pkg::tl_d2h_t prim_tl_o; + + // interfaces + clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n)); + pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts); + + // lc_otp interfaces + push_pull_if #(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1)) + lc_prog_if(.clk(clk), .rst_n(rst_n)); + push_pull_if #(.DeviceDataWidth(SRAM_DATA_SIZE)) + sram_if[NumSramKeyReqSlots](.clk(clk), .rst_n(rst_n)); + push_pull_if #(.DeviceDataWidth(OTBN_DATA_SIZE)) otbn_if(.clk(clk), .rst_n(rst_n)); + + tl_if tl_if(.clk(clk), .rst_n(rst_n)); + tl_if prim_tl_if(.clk(clk), .rst_n(rst_n)); + + otp_ctrl_if otp_ctrl_if(.clk_i(clk), .rst_ni(rst_n)); + + `DV_ALERT_IF_CONNECT() + + // edn_clk, edn_rst_n and edn_if are defined and driven in below macro + `DV_EDN_IF_CONNECT + + assign otp_ctrl_if.lc_prog_req = lc_prog_if.req; + assign otp_ctrl_if.lc_prog_err = lc_prog_if.d_data; + + // Assign to otp_ctrl_if for assertion checks. + assign otp_ctrl_if.lc_prog_ack = lc_prog_if.ack; + assign otp_ctrl_if.otbn_ack = otbn_if.ack; + + // This signal probes design's alert request to avoid additional logic for triggering alert and + // disable assertions. + // Alert checks are done independently in otp_ctrl's scb. + // The correctness of this probed signal is checked in otp_ctrl's scb as well. + assign otp_ctrl_if.alert_reqs = dut.alerts[0] | dut.alerts[1]; + + // connected to interface + wire otp_ext_voltage_h = otp_ctrl_if.ext_voltage_h_io; + + // dut + otp_ctrl dut ( + .clk_i (clk ), + .rst_ni (rst_n ), + // edn + .clk_edn_i (edn_clk ), + .rst_edn_ni (edn_rst_n ), + .edn_o (edn_if[0].req ), + .edn_i ({edn_if[0].ack, edn_if[0].d_data}), + // bus interfaces + .core_tl_i (tl_if.h2d ), + .core_tl_o (tl_if.d2h ), + // interrupt + .intr_otp_operation_done_o (intr_otp_operation_done), + .intr_otp_error_o (intr_otp_error), + // alert + .alert_rx_i (alert_rx ), + .alert_tx_o (alert_tx ), + // pwrmgr + .pwr_otp_i (otp_ctrl_if.pwr_otp_init_i), + .pwr_otp_o ({otp_ctrl_if.pwr_otp_done_o, otp_ctrl_if.pwr_otp_idle_o}), + // lc + .lc_otp_program_i ({lc_prog_if.req, lc_prog_if.h_data}), + .lc_otp_program_o ({lc_prog_if.d_data, lc_prog_if.ack}), + .lc_creator_seed_sw_rw_en_i (otp_ctrl_if.lc_creator_seed_sw_rw_en_i), + .lc_owner_seed_sw_rw_en_i (otp_ctrl_if.lc_owner_seed_sw_rw_en_i), + .lc_seed_hw_rd_en_i (otp_ctrl_if.lc_seed_hw_rd_en_i), + .lc_escalate_en_i (otp_ctrl_if.lc_escalate_en_i), + .lc_check_byp_en_i (otp_ctrl_if.lc_check_byp_en_i), + .otp_lc_data_o (otp_ctrl_if.lc_data_o), + // keymgr + .otp_keymgr_key_o (otp_ctrl_if.keymgr_key_o), + // sram + .sram_otp_key_i (sram_req), + .sram_otp_key_o (sram_rsp), + // otbn + .otbn_otp_key_i (otbn_req), + .otbn_otp_key_o (otbn_rsp), + + .otp_broadcast_o (otp_ctrl_if.otp_broadcast_o), + + .otp_macro_o (otp_ctrl_macro_req), + .otp_macro_i (otp_ctrl_macro_rsp) + ); + + otp_macro #( + .Width(otp_ctrl_macro_pkg::OtpWidth), + .Depth(otp_ctrl_macro_pkg::OtpDepth), + .SizeWidth(otp_ctrl_macro_pkg::OtpSizeWidth), +// .MemInitFile(), + .VendorTestOffset(otp_ctrl_reg_pkg::VendorTestOffset), + .VendorTestSize(otp_ctrl_reg_pkg::VendorTestSize) + ) otp_macro ( + + // Output + .cio_test_o (otp_ctrl_if.cio_test_o), + .cio_test_en_o (otp_ctrl_if.cio_test_en_o), + + // Inter-module signals + .obs_ctrl_i('0), + .otp_obs_o ( ), + .pwr_seq_o(ast_req), + .pwr_seq_h_i(otp_ctrl_if.otp_ast_pwr_seq_h_i), + .ext_voltage_h_io(otp_ext_voltage_h), + .lc_dft_en_i(otp_ctrl_if.lc_dft_en_i), + .test_i (otp_ctrl_if.otp_vendor_test_ctrl_i), + .test_o (otp_ctrl_if.otp_vendor_test_status_o), + .otp_i(otp_ctrl_macro_req), + .otp_o(otp_ctrl_macro_rsp), + .cfg_i('0), + .cfg_rsp_o(), + .prim_tl_i(prim_tl_if.h2d), + .prim_tl_o(prim_tl_if.d2h), + .scanmode_i (otp_ctrl_if.scanmode_i), + .scan_rst_ni (otp_ctrl_if.scan_rst_ni), + .scan_en_i (otp_ctrl_if.scan_en_i), + + // Clock and reset connections + .clk_i (clk), + .rst_ni (rst_n) + ); + + for (genvar i = 0; i < NumSramKeyReqSlots; i++) begin : gen_sram_pull_if + assign sram_req[i] = sram_if[i].req; + assign sram_if[i].ack = sram_rsp[i].ack; + assign sram_if[i].d_data = {sram_rsp[i].key, sram_rsp[i].nonce, sram_rsp[i].seed_valid}; + assign otp_ctrl_if.sram_acks[i] = sram_rsp[i].ack; + initial begin + uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(SRAM_DATA_SIZE)))::set(null, + $sformatf("*env.m_sram_pull_agent[%0d]*", i), "vif", sram_if[i]); + end + end + assign otbn_req = otbn_if.req; + assign otbn_if.ack = otbn_rsp.ack; + assign otbn_if.d_data = {otbn_rsp.key, otbn_rsp.nonce, otbn_rsp.seed_valid}; + + + assign interrupts[OtpOperationDone] = intr_otp_operation_done; + assign interrupts[OtpErr] = intr_otp_error; + + // Instantiate the memory backdoor util instance only for OS implementation + // Proprietary IP will instantiate their own backdoor util + + if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_impl_generic + `define MEM_MODULE_PATH \ + tb.otp_macro.u_prim_ram_1p_adv.gen_ram_inst[0] + + `define MEM_ARRAY_PATH \ + `MEM_MODULE_PATH.u_mem.mem + + initial begin : mem_bkdr_util_gen + mem_bkdr_util m_mem_bkdr_util; + m_mem_bkdr_util = new(.name("mem_bkdr_util"), + .path(`DV_STRINGIFY(`MEM_ARRAY_PATH)), + .depth($size(`MEM_ARRAY_PATH)), + .n_bits($bits(`MEM_ARRAY_PATH)), + .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_22_16)); + + uvm_config_db#(mem_bkdr_util)::set(null, "*.env", "mem_bkdr_util", m_mem_bkdr_util); + end : mem_bkdr_util_gen + + `undef MEM_ARRAY_PATH + `undef MEM_MODULE_PATH + end : gen_impl_generic + + // DV forced otp_cmd_i to reach invalid state, thus violate the assertions + for (genvar idx = 0; idx < NumPart; idx++) begin : gen_assertoff_loop + if (is_hw_part_idx(idx)) begin : gen_assertoff + initial begin + $assertoff(0, tb.dut.gen_partitions[idx].gen_buffered.u_part_buf.OtpErrorState_A); + end + end + end + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", + "clk_rst_vif_otp_macro_prim_reg_block", clk_rst_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_otp_ctrl_core_reg_block*", + "vif", tl_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_otp_macro_prim_reg_block", + "vif", prim_tl_if); + uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(OTBN_DATA_SIZE)))::set(null, + "*env.m_otbn_pull_agent*", "vif", otbn_if); + uvm_config_db#(virtual push_pull_if#(.HostDataWidth(LC_PROG_DATA_SIZE), .DeviceDataWidth(1))):: + set(null, "*env.m_lc_prog_pull_agent*", "vif", lc_prog_if); + + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + + uvm_config_db#(virtual otp_ctrl_if)::set(null, "*.env", "otp_ctrl_vif", otp_ctrl_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tests/otp_ctrl_base_test.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tests/otp_ctrl_base_test.sv new file mode 100644 index 00000000000..284c5e0cdfe --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tests/otp_ctrl_base_test.sv @@ -0,0 +1,51 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class otp_ctrl_base_test #( + type CFG_T = otp_ctrl_env_cfg, + type ENV_T = otp_ctrl_env + ) extends cip_base_test #( + .CFG_T(CFG_T), + .ENV_T(ENV_T) + ); + + // A prototype for the registry to associate the parameterized base test + // with the name 'otp_ctrl_base_test' + // + // Register the name 'otp_ctrl_base_test' with the UVM factory to be associated + // with the template base test class parameterized with the default types (see + // declaration. We cannot invoke the standard UVM factory automation macro t + // (uvm_component_param_utils) to register a parameterized test class with the + // factory because the creation of the test by name (via the UVM_TESTNAME + // plusarg) does not work. We expand the contents of the automation macro + // here instead. See the following paper for details: + // https://verificationacademy-news.s3.amazonaws.com/DVCon2016/Papers/ + // dvcon-2016_paramaters-uvm-coverage-and-emulation-take-two-and-call-me-in-the-morning_paper.pdf + typedef uvm_component_registry#(otp_ctrl_base_test#(CFG_T, ENV_T), "otp_ctrl_base_test") type_id; + + // functions to support the component registry above + static function type_id get_type(); + return type_id::get(); + endfunction : get_type + + virtual function uvm_object_wrapper get_object_type(); + return type_id::get(); + endfunction : get_object_type + + const static string type_name = "otp_ctrl_base_test"; + + virtual function string get_type_name(); + return type_name; + endfunction : get_type_name + + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // otp_ctrl_env_cfg: cfg + // otp_ctrl_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : otp_ctrl_base_test diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tests/otp_ctrl_test.core b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tests/otp_ctrl_test.core new file mode 100644 index 00000000000..d92ba2ee82e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tests/otp_ctrl_test.core @@ -0,0 +1,20 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:otp_ctrl_test:0.1 +description: "OTP_CTRL DV UVM test" + +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:otp_ctrl_env + files: + - otp_ctrl_test_pkg.sv + - otp_ctrl_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tests/otp_ctrl_test_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tests/otp_ctrl_test_pkg.sv new file mode 100644 index 00000000000..3d5703d49e6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/dv/tests/otp_ctrl_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package otp_ctrl_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import otp_ctrl_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "otp_ctrl_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl.vbl b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl.vbl new file mode 100644 index 00000000000..33b74bcc954 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl.vbl @@ -0,0 +1,8 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for OTP controller + +# waive long line violations in generated code +waive --rule=line-length --location="otp_ctrl_part_pkg.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl.vlt new file mode 100644 index 00000000000..0f4180cb5e3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl.vlt @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for OTP controller + +`verilator_config + +// Some code in this block checks that an address is greater than or equal to +// the offset of a fixed part_info_t (supplied via a parameter). If that +// part_info_t happens to have a zero offset, Verilator warns that the +// comparison is always true. Waive the warning. +lint_off -rule UNSIGNED -file "*/rtl/otp_ctrl.sv" +lint_off -rule UNSIGNED -file "*/rtl/otp_ctrl_dai.sv" +lint_off -rule UNSIGNED -file "*/rtl/otp_ctrl_part_unbuf.sv" + +// In otp_ctrl_scrmbl, there are some comparisons between the "sel_i" signal +// and LastDigestSet. If the parameter NumDigestSets is a power of 2 (which it +// is at the moment), these checks will always be true, causing a Verilator +// warning. +lint_off -rule CMPCONST -file "*/rtl/otp_ctrl_scrmbl.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl.waiver new file mode 100644 index 00000000000..b97042a7aec --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl.waiver @@ -0,0 +1,26 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for OTP controller + +waive -rules {TERMINAL_STATE} -location {otp_ctrl_dai.sv \ + otp_ctrl_lci.sv \ + otp_ctrl_lfsr_timer.sv \ + otp_ctrl_part_buf.sv \ + otp_ctrl_part_unbuf.sv \ + otp_ctrl_scrmbl.sv} \ + -msg {Terminal state 'ErrorSt' is detected. Next state register 'state_d' is not assigned in this state.} \ + -comment "All these FSMs have a valid, terminal error state." + +waive -rules {INVALID_COMPARE} -location {otp_ctrl_dai.sv} -regexp {.*dai_addr_i >= PartInfo\[0\]\.offset.*} \ + -comment "This invalid compare is due to the first partition offset being zero." + +waive -rules {INVALID_COMPARE} -location {otp_ctrl.sv} -regexp {.*tlul_addr.* >= PartInfo\[0\]\.offset.*} \ + -comment "This invalid compare is due to the first partition offset being zero." + +waive -rules {LOOP_VAR_OP FOR_LOOP_BOUNDS} -location {prim_cipher_pkg.sv} -regexp {Loop.*round_cnt.*constant.*} \ + -comment "This function needs to iterate over the key schedule function in order to derive the decryption key." + +waive -rules {ASSIGN_SIGN} -location {otp_ctrl_part_buf.sv} -regexp {Unsigned target 'step_i' assigned signed value 'CntWidth'\(1\)'} \ + -comment "This is fine as long as CntWidth is greater equal 2 which is checked using an SVA." diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl_top_specific_pkg.vbl b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl_top_specific_pkg.vbl new file mode 100644 index 00000000000..dadab89d18e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl_top_specific_pkg.vbl @@ -0,0 +1,8 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for OTP controller top-specific package + +# waive long line violations in generated code +waive --rule=line-length --location="otp_ctrl_part_pkg.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl_top_specific_pkg.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl_top_specific_pkg.vlt new file mode 100644 index 00000000000..06603a4760c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl_top_specific_pkg.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for OTP controller top-specific package diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl_top_specific_pkg.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl_top_specific_pkg.waiver new file mode 100644 index 00000000000..69259ce4b16 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/lint/otp_ctrl_top_specific_pkg.waiver @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for OTP controller top-specific package + +# waive line length violations in generated code +waive -rules LINE_LENGTH -location {otp_ctrl_part_pkg.sv} \ + -comment "Waive line length violations in generated code." diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/otp_ctrl.core b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/otp_ctrl.core new file mode 100644 index 00000000000..0923bd334e5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/otp_ctrl.core @@ -0,0 +1,107 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:otp_ctrl:1.0 +description: "OTP Controller" + +filesets: + files_rtl: + depend: + - lowrisc:ip:otp_ctrl_pkg + - lowrisc:darjeeling_no_ibex_ip:otp_ctrl_macro_pkg + - lowrisc:darjeeling_no_ibex_ip:otp_ctrl_top_specific_pkg + - lowrisc:ip:otp_macro_pkg + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:prim:ram_1p + - lowrisc:prim:double_lfsr + - lowrisc:prim:count + - lowrisc:prim:lc_sender + - lowrisc:prim:lc_sync + - lowrisc:prim:buf + - lowrisc:prim:flop + - lowrisc:prim:secded + - lowrisc:prim:edn_req + - lowrisc:prim:sec_anchor + # TODO(#27347): prim_pkg is deprecated + - lowrisc:prim:prim_pkg + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg + - lowrisc:ip:edn_pkg + - lowrisc:prim:sparse_fsm + - "fileset_partner ? (partner:systems:ast_pkg)" + - "!fileset_partner ? (lowrisc:systems:ast_pkg)" + files: + - rtl/otp_ctrl_core_reg_top.sv + - rtl/otp_ctrl_ecc_reg.sv + - rtl/otp_ctrl_scrmbl.sv + - rtl/otp_ctrl_lfsr_timer.sv + - rtl/otp_ctrl_part_unbuf.sv + - rtl/otp_ctrl_part_buf.sv + - rtl/otp_ctrl_dai.sv + - rtl/otp_ctrl_kdi.sv + - rtl/otp_ctrl_lci.sv + - rtl/otp_ctrl.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/otp_ctrl.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/otp_ctrl.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/otp_ctrl.vbl + file_type: veribleLintWaiver + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: otp_ctrl + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" + + syn: + <<: *default_target + # TODO: set default to DC once + # this option is available + # olofk/edalize#89 + default_tool: icarus + parameters: + - SYNTHESIS=true diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/otp_ctrl_macro_pkg.core b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/otp_ctrl_macro_pkg.core new file mode 100644 index 00000000000..44d26aa47f3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/otp_ctrl_macro_pkg.core @@ -0,0 +1,49 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: lowrisc:darjeeling_no_ibex_ip:otp_ctrl_macro_pkg:0.1 +description: "Package with common interface definitions for OTP primitive." +virtual: + - lowrisc:virtual_ip:otp_ctrl_macro_pkg + +filesets: + files_rtl: + files: + - rtl/otp_ctrl_macro_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/otp_ctrl_top_specific_pkg.core b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/otp_ctrl_top_specific_pkg.core new file mode 100644 index 00000000000..8d781461365 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/otp_ctrl_top_specific_pkg.core @@ -0,0 +1,75 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:otp_ctrl_top_specific_pkg:1.0 +description: "OTP Controller Top Specific Packages" +virtual: + - lowrisc:virtual_ip:otp_ctrl_top_specific_pkg + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:ip:otp_ctrl_pkg + - lowrisc:prim:mubi + + files: + - rtl/otp_ctrl_reg_pkg.sv + - rtl/otp_ctrl_top_specific_pkg.sv + - rtl/otp_ctrl_part_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/otp_ctrl_top_specific_pkg.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/otp_ctrl_top_specific_pkg.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/otp_ctrl_top_specific_pkg.vbl + file_type: veribleLintWaiver + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: lc_ctrl + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv new file mode 100644 index 00000000000..65d1ce162a7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl.sv @@ -0,0 +1,1489 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// OTP Controller top. +// + +`include "prim_assert.sv" + +module otp_ctrl + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import otp_ctrl_macro_pkg::OtpAddrWidth; + import otp_ctrl_macro_pkg::OtpDepth; + import otp_ctrl_macro_pkg::OtpErrWidth; + import otp_ctrl_macro_pkg::OtpIfWidth; + import otp_ctrl_macro_pkg::OtpSizeWidth; + import otp_ctrl_macro_pkg::OtpWidth; + import otp_ctrl_top_specific_pkg::*; + import otp_macro_pkg::OtpTestVectWidth; +#( + // Enable asynchronous transitions on alerts. + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert signal + parameter int unsigned AlertSkewCycles = 1, + // Compile time random constants, to be overridden by topgen. + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault, + parameter scrmbl_key_init_t RndCnstScrmblKeyInit = RndCnstScrmblKeyInitDefault +) ( + // OTP clock + input clk_i, + input rst_ni, + // EDN clock and interface + logic clk_edn_i, + logic rst_edn_ni, + output edn_pkg::edn_req_t edn_o, + input edn_pkg::edn_rsp_t edn_i, + // Bus Interface + input tlul_pkg::tl_h2d_t core_tl_i, + output tlul_pkg::tl_d2h_t core_tl_o, + // Interrupt Requests + output logic intr_otp_operation_done_o, + output logic intr_otp_error_o, + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // Power manager interface (inputs are synced to OTP clock domain) + input pwrmgr_pkg::pwr_otp_req_t pwr_otp_i, + output pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_o, + // Lifecycle transition command interface + input lc_otp_program_req_t lc_otp_program_i, + output lc_otp_program_rsp_t lc_otp_program_o, + // Lifecycle broadcast inputs + // SEC_CM: LC_CTRL.INTERSIG.MUBI + input lc_ctrl_pkg::lc_tx_t lc_creator_seed_sw_rw_en_i, + input lc_ctrl_pkg::lc_tx_t lc_owner_seed_sw_rw_en_i, + input lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en_i, + input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, + input lc_ctrl_pkg::lc_tx_t lc_check_byp_en_i, + // OTP broadcast outputs + // SEC_CM: TOKEN_VALID.CTRL.MUBI + output otp_lc_data_t otp_lc_data_o, + output otp_keymgr_key_t otp_keymgr_key_o, + // Scrambling key requests + input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, + output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, + input otbn_otp_key_req_t otbn_otp_key_i, + output otbn_otp_key_rsp_t otbn_otp_key_o, + + // Interface to OTP_MACRO + output otp_ctrl_macro_pkg::otp_ctrl_macro_req_t otp_macro_o, + input otp_ctrl_macro_pkg::otp_ctrl_macro_rsp_t otp_macro_i, + + // Hardware config bits + output otp_broadcast_t otp_broadcast_o +); + + import prim_mubi_pkg::*; + import prim_util_pkg::vbits; + + //////////////////////// + // Integration Checks // + //////////////////////// + + // This ensures that we can transfer scrambler data blocks in and out of OTP atomically. + `ASSERT_INIT(OtpIfWidth_A, OtpIfWidth == ScrmblBlockWidth) + + // These error codes need to be identical. + `ASSERT_INIT(OtpErrorCode0_A, int'(NoError) == int'(otp_ctrl_macro_pkg::NoError)) + `ASSERT_INIT(OtpErrorCode1_A, int'(MacroError) == int'(otp_ctrl_macro_pkg::MacroError)) + `ASSERT_INIT(OtpErrorCode2_A, + int'(MacroEccCorrError) == int'(otp_ctrl_macro_pkg::MacroEccCorrError)) + `ASSERT_INIT(OtpErrorCode3_A, + int'(MacroEccUncorrError) == int'(otp_ctrl_macro_pkg::MacroEccUncorrError)) + `ASSERT_INIT(OtpErrorCode4_A, + int'(MacroWriteBlankError) == int'(otp_ctrl_macro_pkg::MacroWriteBlankError)) + + ///////////// + // Regfile // + ///////////// + + // We have one CSR node, one functional TL-UL window and a gate module for that window + logic [2:0] intg_error; + assign intg_error[2] = otp_macro_i.fatal_lc_fsm_err; + + tlul_pkg::tl_h2d_t tl_win_h2d; + tlul_pkg::tl_d2h_t tl_win_d2h; + + otp_ctrl_reg_pkg::otp_ctrl_core_reg2hw_t reg2hw; + otp_ctrl_reg_pkg::otp_ctrl_core_hw2reg_t hw2reg; + + // SEC_CM: DIRECT_ACCESS.CONFIG.REGWEN, CHECK_TRIGGER.CONFIG.REGWEN, CHECK.CONFIG.REGWEN + otp_ctrl_core_reg_top u_reg_core ( + .clk_i, + .rst_ni, + .tl_i ( core_tl_i ), + .tl_o ( core_tl_o ), + .tl_win_o ( tl_win_h2d ), + .tl_win_i ( tl_win_d2h ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + // SEC_CM: BUS.INTEGRITY + .intg_err_o( intg_error[0] ) + ); + + /////////////////////////////////////// + // Life Cycle Signal Synchronization // + /////////////////////////////////////// + + lc_ctrl_pkg::lc_tx_t lc_creator_seed_sw_rw_en, lc_owner_seed_sw_rw_en, + lc_seed_hw_rd_en, lc_check_byp_en; + // NumAgents + lfsr timer and scrambling datapath. + lc_ctrl_pkg::lc_tx_t [NumAgentsIdx+1:0] lc_escalate_en, lc_escalate_en_synced; + // Single wire for gating assertions in arbitration and CDC primitives. + logic lc_escalate_en_any; + + prim_lc_sync #( + .NumCopies(NumAgentsIdx+2) + ) u_prim_lc_sync_escalate_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_escalate_en_i), + .lc_en_o(lc_escalate_en_synced) + ); + + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_creator_seed_sw_rw_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_creator_seed_sw_rw_en_i), + .lc_en_o({lc_creator_seed_sw_rw_en}) + ); + + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_owner_seed_sw_rw_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_owner_seed_sw_rw_en_i), + .lc_en_o({lc_owner_seed_sw_rw_en}) + ); + + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_seed_hw_rd_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_seed_hw_rd_en_i), + .lc_en_o({lc_seed_hw_rd_en}) + ); + + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_check_byp_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_check_byp_en_i), + .lc_en_o({lc_check_byp_en}) + ); + + ///////////////////////////////////// + // TL-UL SW partition select logic // + ///////////////////////////////////// + + // The SW partitions share the same TL-UL adapter. + logic tlul_req, tlul_gnt, tlul_rvalid; + logic [SwWindowAddrWidth-1:0] tlul_addr; + logic [1:0] tlul_rerror; + logic [31:0] tlul_rdata; + + import prim_mubi_pkg::MuBi4False; + tlul_adapter_sram #( + .SramAw ( SwWindowAddrWidth ), + .SramDw ( 32 ), + .Outstanding ( 1 ), + .ByteAccess ( 0 ), + .ErrOnWrite ( 1 ) // No write accesses allowed here. + ) u_tlul_adapter_sram ( + .clk_i, + .rst_ni, + .en_ifetch_i ( MuBi4False ), + .tl_i ( tl_win_h2d ), + .tl_o ( tl_win_d2h ), + .req_o ( tlul_req ), + .gnt_i ( tlul_gnt ), + .we_o ( ), // unused + .addr_o ( tlul_addr ), + .wdata_o ( ), // unused + .wmask_o ( ), // unused + // SEC_CM: BUS.INTEGRITY + .intg_error_o ( intg_error[1] ), + .user_rsvd_o ( ), + .rdata_i ( tlul_rdata ), + .rvalid_i ( tlul_rvalid ), + .rerror_i ( tlul_rerror ), + .req_type_o ( ), + .compound_txn_in_progress_o ( ), + .readback_en_i ( MuBi4False ), + .readback_error_o ( ), + .wr_collision_i ( 1'b0 ), + .write_pending_i ( 1'b0 ) + ); + + logic [NumPart-1:0] tlul_part_sel_oh; + for (genvar k = 0; k < NumPart; k++) begin : gen_part_sel + localparam logic [OtpByteAddrWidth:0] PartEnd = (OtpByteAddrWidth+1)'(PartInfo[k].offset) + + (OtpByteAddrWidth+1)'(PartInfo[k].size); + if (PartInfo[k].offset == 0) begin : gen_zero_offset + assign tlul_part_sel_oh[k] = ({1'b0, {tlul_addr, 2'b00}} < PartEnd); + end else begin : gen_nonzero_offset + assign tlul_part_sel_oh[k] = ({tlul_addr, 2'b00} >= PartInfo[k].offset) & + ({1'b0, {tlul_addr, 2'b00}} < PartEnd); + end + end + + `ASSERT(PartSelMustBeOnehot_A, $onehot0(tlul_part_sel_oh)) + + logic [NumPartWidth-1:0] tlul_part_idx; + prim_arbiter_fixed #( + .N(NumPart), + .EnDataPort(0) + ) u_part_sel_idx ( + .clk_i, + .rst_ni, + .req_i ( tlul_part_sel_oh ), + .data_i ( '{default: '0} ), + .gnt_o ( ), // unused + .idx_o ( tlul_part_idx ), + .valid_o ( ), // unused + .data_o ( ), // unused + .ready_i ( 1'b0 ) + ); + + logic tlul_oob_err_d, tlul_oob_err_q; + logic [NumPart-1:0] part_tlul_req, part_tlul_gnt, part_tlul_rvalid; + logic [SwWindowAddrWidth-1:0] part_tlul_addr; + logic [NumPart-1:0][1:0] part_tlul_rerror; + logic [NumPart-1:0][31:0] part_tlul_rdata; + + always_comb begin : p_tlul_assign + // Send request to the correct partition. + part_tlul_addr = tlul_addr; + part_tlul_req = '0; + tlul_oob_err_d = 1'b0; + if (tlul_req) begin + if (tlul_part_sel_oh != '0) begin + part_tlul_req[tlul_part_idx] = 1'b1; + end else begin + // Error out in the next cycle if address was out of bounds. + tlul_oob_err_d = 1'b1; + end + end + + // aggregate TL-UL responses + tlul_gnt = |part_tlul_gnt | tlul_oob_err_q; + tlul_rvalid = |part_tlul_rvalid | tlul_oob_err_q; + tlul_rerror = '0; + tlul_rdata = '0; + for (int k = 0; k < NumPart; k++) begin + tlul_rerror |= part_tlul_rerror[k]; + tlul_rdata |= part_tlul_rdata[k]; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlul_reg + if (!rst_ni) begin + tlul_oob_err_q <= 1'b0; + end else begin + tlul_oob_err_q <= tlul_oob_err_d; + end + end + + ////////////////////////////// + // Access Defaults and CSRs // + ////////////////////////////// + + // SEC_CM: ACCESS.CTRL.MUBI + part_access_t [NumPart-1:0] part_access_pre, part_access; + always_comb begin : p_access_control + // Assigns default and extracts named CSR read enables for SW_CFG partitions. + // SEC_CM: PART.MEM.REGREN + part_access_pre = named_part_access_pre(reg2hw); + + // Permanently lock DAI write and read access to the life cycle partition. + // The LC partition can only be read from and written to via the LC controller. + // SEC_CM: LC_PART.MEM.SW_NOACCESS + part_access_pre[LifeCycleIdx].write_lock = MuBi8True; + part_access_pre[LifeCycleIdx].read_lock = MuBi8True; + + // Special partitions for keymgr material only become writable when + // provisioning is enabled. + if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en)) begin + for (int k = 0; k < NumPart; k++) begin + if (PartInfo[k].iskeymgr_creator) begin + part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}}; + end + end + end + if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_owner_seed_sw_rw_en)) begin + for (int k = 0; k < NumPart; k++) begin + if (PartInfo[k].iskeymgr_owner) begin + part_access_pre[k] = {2{prim_mubi_pkg::MuBi8True}}; + end + end + end + end + + // This prevents the synthesis tool from optimizing the multibit signals. + for (genvar k = 0; k < NumPart; k++) begin : gen_bufs + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock ( + .clk_i, + .rst_ni, + .mubi_i(part_access_pre[k].write_lock), + .mubi_o(part_access[k].write_lock) + ); + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock ( + .clk_i, + .rst_ni, + .mubi_i(part_access_pre[k].read_lock), + .mubi_o(part_access[k].read_lock) + ); + end + + ////////////////////// + // DAI-related CSRs // + ////////////////////// + + logic dai_idle; + logic dai_req; + dai_cmd_e dai_cmd; + logic [OtpByteAddrWidth-1:0] dai_addr; + logic [NumDaiWords-1:0][31:0] dai_wdata, dai_rdata; + logic direct_access_regwen_d, direct_access_regwen_q; + + // This is the HWEXT implementation of a RW0C regwen bit. + assign direct_access_regwen_d = (reg2hw.direct_access_regwen.qe && + !reg2hw.direct_access_regwen.q) ? 1'b0 : direct_access_regwen_q; + + // Any write to this register triggers a DAI command. + assign dai_req = reg2hw.direct_access_cmd.digest.qe | + reg2hw.direct_access_cmd.wr.qe | + reg2hw.direct_access_cmd.rd.qe; + + assign dai_cmd = dai_cmd_e'({reg2hw.direct_access_cmd.digest.q, + reg2hw.direct_access_cmd.wr.q, + reg2hw.direct_access_cmd.rd.q}); + + assign dai_addr = reg2hw.direct_access_address.q; + assign dai_wdata = reg2hw.direct_access_wdata; + + // The DAI and the LCI can initiate write transactions, which + // are critical and we must not power down if such transactions + // are pending. Hence, we signal the LCI/DAI idle state to the + // power manager. This signal is flopped here as it has to + // cross a clock boundary to the power manager. + logic dai_prog_idle, lci_prog_idle, otp_idle_d, otp_idle_q; + assign otp_idle_d = lci_prog_idle & dai_prog_idle; + assign pwr_otp_o.otp_idle = otp_idle_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_idle_regwen_regs + if (!rst_ni) begin + otp_idle_q <= 1'b0; + // The regwen bit has to reset to 1 so that CSR accesses are enabled by default. + direct_access_regwen_q <= 1'b1; + end else begin + otp_idle_q <= otp_idle_d; + direct_access_regwen_q <= direct_access_regwen_d; + end + end + + ////////////////////////////////////// + // Ctrl/Status CSRs, Errors, Alerts // + ////////////////////////////////////// + + // Status and error reporting CSRs, error interrupt generation and alerts. + otp_err_e [NumPart+1:0] part_error; + logic [NumAgents-1:0] part_fsm_err; + logic [NumPart+1:0] part_errors_reduced; + logic otp_operation_done, otp_error; + logic fatal_macro_error_d, fatal_macro_error_q; + logic fatal_check_error_d, fatal_check_error_q; + logic fatal_bus_integ_error_d, fatal_bus_integ_error_q; + logic chk_pending, chk_timeout; + logic lfsr_fsm_err, scrmbl_fsm_err; + always_comb begin : p_errors_alerts + // Note: since these are all fatal alert events, we latch them and keep on sending + // alert events via the alert senders. These regs can only be cleared via a system reset. + fatal_macro_error_d = fatal_macro_error_q; + fatal_check_error_d = fatal_check_error_q; + fatal_bus_integ_error_d = fatal_bus_integ_error_q | (|intg_error); + // These are the per-partition buffered escalation inputs + lc_escalate_en = lc_escalate_en_synced; + // Need a single wire for gating assertions in arbitration and CDC primitives. + lc_escalate_en_any = 1'b0; + + // Aggregate all the macro alerts from the partitions + for (int k = 0; k < NumPart; k++) begin + // Filter for critical error codes that should not occur in the field. + fatal_macro_error_d |= part_error[k] == MacroError; + // While uncorrectable ECC errors are always reported, they do not trigger a fatal alert + // event in some partitions like the VENDOR_TEST partition. + if (PartInfo[k].integrity) begin + fatal_macro_error_d |= part_error[k] == MacroEccUncorrError; + end + end + // Aggregate all the macro alerts from the DAI/LCI + for (int k = NumPart; k < NumPart+2; k++) begin + // Filter for critical error codes that should not occur in the field. + fatal_macro_error_d |= part_error[k] inside {MacroError, MacroEccUncorrError}; + end + + // Aggregate all the remaining errors / alerts from the partitions and the DAI/LCI + for (int k = 0; k < NumPart+2; k++) begin + // Set the error bit if the error status of the corresponding partition is nonzero. + part_errors_reduced[k] = |part_error[k]; + // Filter for integrity and consistency check failures. + fatal_check_error_d |= part_error[k] inside {CheckFailError, FsmStateError}; + + // If a fatal alert has been observed in any of the partitions/FSMs, + // we locally trigger escalation within OTP, which moves all FSMs + // to a terminal error state. + if (fatal_macro_error_q || fatal_check_error_q) begin + lc_escalate_en[k] = lc_ctrl_pkg::On; + end + if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k])) begin + lc_escalate_en_any = 1'b1; + end + end + + // Errors from other non-partition FSMs. + fatal_check_error_d |= chk_timeout | + lfsr_fsm_err | + scrmbl_fsm_err | + (|part_fsm_err); + end + + // If we got an error, we trigger an interrupt. + logic [$bits(part_errors_reduced)+4-1:0] interrupt_triggers_d, interrupt_triggers_q; + + // This makes sure that interrupts are not sticky. + assign interrupt_triggers_d = { + part_errors_reduced, + chk_timeout, + lfsr_fsm_err, + scrmbl_fsm_err, + |part_fsm_err + }; + + assign otp_error = |(interrupt_triggers_d & ~interrupt_triggers_q); + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_alert_regs + if (!rst_ni) begin + fatal_macro_error_q <= '0; + fatal_check_error_q <= '0; + fatal_bus_integ_error_q <= '0; + interrupt_triggers_q <= '0; + end else begin + fatal_macro_error_q <= fatal_macro_error_d; + fatal_check_error_q <= fatal_check_error_d; + fatal_bus_integ_error_q <= fatal_bus_integ_error_d; + interrupt_triggers_q <= interrupt_triggers_d; + end + end + + // CSR assignments are done in one combo process so that we can use + // the parameterized digest_assign task below without multiple driver issues. + logic unused_part_digest; + logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest; + logic intr_state_otp_operation_done_d, intr_state_otp_operation_done_de; + logic intr_state_otp_error_d, intr_state_otp_error_de; + always_comb begin : p_csr_assign + // Not all partition digests are consumed, and assigning them to an unused_* signal in the + // function below does not seem to work for some linters. + unused_part_digest = ^part_digest; + // Assign named CSRs (like digests). + hw2reg = named_reg_assign(part_digest); + // DAI related CSRs + hw2reg.direct_access_rdata = dai_rdata; + // ANDing this state with dai_idle write-protects all DAI regs during pending operations. + hw2reg.direct_access_regwen.d = direct_access_regwen_q & dai_idle; + // Report partition errors in the status register; relies upon the field ordering and the + // presence of only the scalar signal 'd' in each partition-specific field. + hw2reg.status = otp_ctrl_hw2reg_status_reg_t'(part_errors_reduced); + // Overwrite the other fields of the status register with specific error conditions. + hw2reg.status.timeout_error.d = chk_timeout; + hw2reg.status.lfsr_fsm_error.d = lfsr_fsm_err; + hw2reg.status.scrambling_fsm_error.d = scrmbl_fsm_err; + hw2reg.status.key_deriv_fsm_error.d = part_fsm_err[KdiIdx]; + hw2reg.status.bus_integ_error.d = fatal_bus_integ_error_q; + hw2reg.status.dai_idle.d = dai_idle; + hw2reg.status.check_pending.d = chk_pending; + // Error code registers. + hw2reg.err_code = part_error; + // Interrupt signals + hw2reg.intr_state.otp_operation_done.de = intr_state_otp_operation_done_de; + hw2reg.intr_state.otp_operation_done.d = intr_state_otp_operation_done_d; + hw2reg.intr_state.otp_error.de = intr_state_otp_error_de; + hw2reg.intr_state.otp_error.d = intr_state_otp_error_d; +end + + + ////////////////////////////////// + // Interrupts and Alert Senders // + ////////////////////////////////// + + prim_intr_hw #( + .Width(1) + ) u_intr_operation_done ( + .clk_i, + .rst_ni, + .event_intr_i ( otp_operation_done ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.otp_operation_done.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.otp_operation_done.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.otp_operation_done.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.otp_operation_done.q ), + .hw2reg_intr_state_de_o ( intr_state_otp_operation_done_de ), + .hw2reg_intr_state_d_o ( intr_state_otp_operation_done_d ), + .intr_o ( intr_otp_operation_done_o ) + ); + + prim_intr_hw #( + .Width(1) + ) u_intr_error ( + .clk_i, + .rst_ni, + .event_intr_i ( otp_error ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.otp_error.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.otp_error.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.otp_error.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.otp_error.q ), + .hw2reg_intr_state_de_o ( intr_state_otp_error_de ), + .hw2reg_intr_state_d_o ( intr_state_otp_error_d ), + .intr_o ( intr_otp_error_o ) + ); + + logic [NumAlerts-1:0] alerts; + logic [NumAlerts-1:0] alert_test; + logic fatal_prim_otp_alert, recov_prim_otp_alert; + + assign alerts = { + recov_prim_otp_alert, + fatal_prim_otp_alert, + fatal_bus_integ_error_q, + fatal_check_error_q, + fatal_macro_error_q + }; + + assign alert_test = { + reg2hw.alert_test.recov_prim_otp_alert.q & + reg2hw.alert_test.recov_prim_otp_alert.qe, + reg2hw.alert_test.fatal_prim_otp_alert.q & + reg2hw.alert_test.fatal_prim_otp_alert.qe, + reg2hw.alert_test.fatal_bus_integ_error.q & + reg2hw.alert_test.fatal_bus_integ_error.qe, + reg2hw.alert_test.fatal_check_error.q & + reg2hw.alert_test.fatal_check_error.qe, + reg2hw.alert_test.fatal_macro_error.q & + reg2hw.alert_test.fatal_macro_error.qe + }; + + localparam logic [NumAlerts-1:0] AlertIsFatal = { + 1'b0, // recov_prim_otp_alert + 1'b1, // fatal_prim_otp_alert + 1'b1, // fatal_bus_integ_error_q + 1'b1, // fatal_check_error_q + 1'b1 // fatal_macro_error_q + }; + + for (genvar k = 0; k < NumAlerts; k++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[k]), + .SkewCycles(AlertSkewCycles), + .IsFatal(AlertIsFatal[k]) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[k] ), + .alert_req_i ( alerts[k] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[k] ), + .alert_tx_o ( alert_tx_o[k] ) + ); + end + + //////////////////////////////// + // LFSR Timer and CSR mapping // + //////////////////////////////// + + logic integ_chk_trig, cnsty_chk_trig; + logic [NumPart-1:0] integ_chk_req, integ_chk_ack; + logic [NumPart-1:0] cnsty_chk_req, cnsty_chk_ack; + logic lfsr_edn_req, lfsr_edn_ack; + logic [EdnDataWidth-1:0] edn_data; + + assign integ_chk_trig = reg2hw.check_trigger.integrity.q & + reg2hw.check_trigger.integrity.qe; + assign cnsty_chk_trig = reg2hw.check_trigger.consistency.q & + reg2hw.check_trigger.consistency.qe; + + // SEC_CM: PART.DATA_REG.BKGN_CHK + otp_ctrl_lfsr_timer #( + .RndCnstLfsrSeed(RndCnstLfsrSeed), + .RndCnstLfsrPerm(RndCnstLfsrPerm) + ) u_otp_ctrl_lfsr_timer ( + .clk_i, + .rst_ni, + .edn_req_o ( lfsr_edn_req ), + .edn_ack_i ( lfsr_edn_ack ), + .edn_data_i ( edn_data ), + // We can enable the timer once OTP has initialized. + // Note that this is only the initial release that gets + // the timer FSM into an operational state. + // Whether or not the timers / background checks are + // activated depends on the CSR configuration (by default + // they are switched off). + .timer_en_i ( pwr_otp_o.otp_done ), + // This idle signal is the same that is output to the power + // manager, and indicates whether there is an ongoing OTP programming + // operation. It is used to pause the consistency check timeout + // counter in order to prevent spurious timeouts (OTP programming + // operations are very slow compared to readout operations and can + // hence interfere with the timeout mechanism). + .otp_prog_busy_i ( ~otp_idle_d ), + .integ_chk_trig_i ( integ_chk_trig ), + .cnsty_chk_trig_i ( cnsty_chk_trig ), + .chk_pending_o ( chk_pending ), + .timeout_i ( reg2hw.check_timeout.q ), + .integ_period_msk_i ( reg2hw.integrity_check_period.q ), + .cnsty_period_msk_i ( reg2hw.consistency_check_period.q ), + .integ_chk_req_o ( integ_chk_req ), + .cnsty_chk_req_o ( cnsty_chk_req ), + .integ_chk_ack_i ( integ_chk_ack ), + .cnsty_chk_ack_i ( cnsty_chk_ack ), + .escalate_en_i ( lc_escalate_en[NumAgents] ), + .chk_timeout_o ( chk_timeout ), + .fsm_err_o ( lfsr_fsm_err ) + ); + + /////////////////////////////////////// + // EDN Arbitration, Request and Sync // + /////////////////////////////////////// + + // Both the key derivation and LFSR reseeding are low bandwidth, + // hence they can share the same EDN interface. + logic edn_req, edn_ack; + logic key_edn_req, key_edn_ack; + prim_arbiter_tree #( + .N(2), + .EnDataPort(0) + ) u_edn_arb ( + .clk_i, + .rst_ni, + .req_chk_i ( ~lc_escalate_en_any ), + .req_i ( {lfsr_edn_req, key_edn_req} ), + .data_i ( '{default: '0} ), + .gnt_o ( {lfsr_edn_ack, key_edn_ack} ), + .idx_o ( ), // unused + .valid_o ( edn_req ), + .data_o ( ), // unused + .ready_i ( edn_ack ) + ); + + // This synchronizes the data coming from EDN and stacks the + // 32bit EDN words to achieve an internal entropy width of 64bit. + prim_edn_req #( + .OutWidth(EdnDataWidth) + ) u_prim_edn_req ( + .clk_i, + .rst_ni, + .req_chk_i ( ~lc_escalate_en_any ), + .req_i ( edn_req ), + .ack_o ( edn_ack ), + .data_o ( edn_data ), + .fips_o ( ), // unused + .err_o ( ), // unused + .clk_edn_i, + .rst_edn_ni, + .edn_o, + .edn_i + ); + + /////////////////////////////// + // OTP Macro and Arbitration // + /////////////////////////////// + + typedef struct packed { + otp_ctrl_macro_pkg::cmd_e cmd; + logic [OtpSizeWidth-1:0] size; // Number of native words to write. + logic [OtpIfWidth-1:0] wdata; + logic [OtpAddrWidth-1:0] addr; // Halfword address. + } otp_bundle_t; + + logic [NumAgents-1:0] part_otp_arb_req, part_otp_arb_gnt; + otp_bundle_t part_otp_arb_bundle [NumAgents]; + logic otp_arb_valid, otp_arb_ready; + logic otp_prim_valid, otp_prim_ready; + logic otp_rsp_fifo_valid, otp_rsp_fifo_ready; + logic [vbits(NumAgents)-1:0] otp_arb_idx; + otp_bundle_t otp_arb_bundle; + + // The OTP interface is arbitrated on a per-cycle basis, meaning that back-to-back + // transactions can be completely independent. + prim_arbiter_tree #( + .N(NumAgents), + .DW($bits(otp_bundle_t)) + ) u_otp_arb ( + .clk_i, + .rst_ni, + .req_chk_i ( ~lc_escalate_en_any ), + .req_i ( part_otp_arb_req ), + .data_i ( part_otp_arb_bundle ), + .gnt_o ( part_otp_arb_gnt ), + .idx_o ( otp_arb_idx ), + .valid_o ( otp_arb_valid ), + .data_o ( otp_arb_bundle ), + .ready_i ( otp_arb_ready ) + ); + + // Don't issue more transactions than what the rsp_fifo can keep track of. + assign otp_arb_ready = otp_prim_ready & otp_rsp_fifo_ready; + assign otp_prim_valid = otp_arb_valid & otp_rsp_fifo_ready; + assign otp_rsp_fifo_valid = otp_prim_ready & otp_prim_valid; + + otp_ctrl_macro_pkg::err_e part_otp_err; + logic [OtpIfWidth-1:0] part_otp_rdata; + logic otp_rvalid; + + assign otp_macro_o = '{ + valid: otp_prim_valid, + cmd: otp_arb_bundle.cmd, + size: otp_arb_bundle.size, + addr: otp_arb_bundle.addr, + wdata: otp_arb_bundle.wdata + }; + + assign otp_prim_ready = otp_macro_i.ready; + assign otp_rvalid = otp_macro_i.rvalid; + assign part_otp_rdata = otp_macro_i.rdata; + assign part_otp_err = otp_macro_i.err; + assign fatal_prim_otp_alert = otp_macro_i.fatal_alert; + assign recov_prim_otp_alert = otp_macro_i.recov_alert; + + logic otp_fifo_valid; + logic [vbits(NumAgents)-1:0] otp_part_idx; + logic [NumAgents-1:0] part_otp_rvalid; + + // We can have up to two OTP commands in flight, hence we size this to be 2 deep. + // The partitions can unconditionally sink requested data. + prim_fifo_sync #( + .Width (vbits(NumAgents)), + .Depth (2), + .NeverClears (1'b1) + ) u_otp_rsp_fifo ( + .clk_i, + .rst_ni, + .clr_i ( 1'b0 ), + .wvalid_i ( otp_rsp_fifo_valid ), + .wready_o ( otp_rsp_fifo_ready ), + .wdata_i ( otp_arb_idx ), + .rvalid_o ( otp_fifo_valid ), + .rready_i ( otp_rvalid ), + .rdata_o ( otp_part_idx ), + .depth_o ( ), + .full_o ( ), + .err_o ( ) + ); + + // Steer response back to the partition where this request originated. + always_comb begin : p_rvalid + part_otp_rvalid = '0; + part_otp_rvalid[otp_part_idx] = otp_rvalid & otp_fifo_valid; + end + + // Note that this must be true by construction. + `ASSERT(OtpRespFifoUnderflow_A, otp_rvalid |-> otp_fifo_valid) + + ///////////////////////////////////////// + // Scrambling Datapath and Arbitration // + ///////////////////////////////////////// + + // This is specialised for different tops that use it but the req/ack protocol is the same in each + // case. For one example, see + // + // https://opentitan.org/book/hw/top_earlgrey/ + // ip_autogen/otp_ctrl/doc/interfaces.html#interfaces-to-sram-and-otbn-scramblers + + + // Note: as opposed to the OTP arbitration above, we do not perform cycle-wise arbitration, but + // transaction-wise arbitration. This is implemented using a RR arbiter that acts as a mutex. + // I.e., each agent (e.g. the DAI or a partition) can request a lock on the mutex. Once granted, + // the partition can keep the lock as long as needed for the transaction to complete. The + // partition must yield its lock by deasserting the request signal for the arbiter to proceed. + // Since this scheme does not have built-in preemption, it must be ensured that the agents + // eventually release their locks for this to be fair. + // + // This is documented in ../README.md (generated from hw/ip_templates/otp_ctrl/README.md.tpl) see + // that document for details. + typedef struct packed { + otp_scrmbl_cmd_e cmd; + digest_mode_e mode; + logic [ConstSelWidth-1:0] sel; + logic [ScrmblBlockWidth-1:0] data; + logic valid; + } scrmbl_bundle_t; + + logic [NumAgents-1:0] part_scrmbl_mtx_req, part_scrmbl_mtx_gnt; + scrmbl_bundle_t part_scrmbl_req_bundle [NumAgents]; + scrmbl_bundle_t scrmbl_req_bundle; + logic [vbits(NumAgents)-1:0] scrmbl_mtx_idx; + logic scrmbl_mtx_valid; + + // Note that arbiter decisions do not change when backpressured. + // Hence, the idx_o signal is guaranteed to remain stable until ack'ed. + prim_arbiter_tree #( + .N(NumAgents), + .DW($bits(scrmbl_bundle_t)) + ) u_scrmbl_mtx ( + .clk_i, + .rst_ni, + .req_chk_i ( 1'b0 ), // REQ is allowed to go low again without ACK even + // during normal operation. + .req_i ( part_scrmbl_mtx_req ), + .data_i ( part_scrmbl_req_bundle ), + .gnt_o ( ), + .idx_o ( scrmbl_mtx_idx ), + .valid_o ( scrmbl_mtx_valid ), + .data_o ( scrmbl_req_bundle ), + .ready_i ( 1'b0 ) + ); + + // Since the ready_i signal of the arbiter is statically set to 1'b0 above, we are always in a + // "backpressure" situation, where the RR arbiter will automatically advance the internal RR state + // to give the current winner max priority in subsequent cycles in order to keep the decision + // stable. Rearbitration occurs once the winning agent deasserts its request. + always_comb begin : p_mutex + part_scrmbl_mtx_gnt = '0; + part_scrmbl_mtx_gnt[scrmbl_mtx_idx] = scrmbl_mtx_valid; + end + + logic [ScrmblBlockWidth-1:0] part_scrmbl_rsp_data; + logic scrmbl_arb_req_ready, scrmbl_arb_rsp_valid; + logic [NumAgents-1:0] part_scrmbl_req_ready, part_scrmbl_rsp_valid; + + // SEC_CM: SECRET.MEM.SCRAMBLE + // SEC_CM: PART.MEM.DIGEST + otp_ctrl_scrmbl u_otp_ctrl_scrmbl ( + .clk_i, + .rst_ni, + .cmd_i ( scrmbl_req_bundle.cmd ), + .mode_i ( scrmbl_req_bundle.mode ), + .sel_i ( scrmbl_req_bundle.sel ), + .data_i ( scrmbl_req_bundle.data ), + .valid_i ( scrmbl_req_bundle.valid ), + .ready_o ( scrmbl_arb_req_ready ), + .data_o ( part_scrmbl_rsp_data ), + .valid_o ( scrmbl_arb_rsp_valid ), + .escalate_en_i ( lc_escalate_en[NumAgents+1] ), + .fsm_err_o ( scrmbl_fsm_err ) + ); + + // steer back responses + always_comb begin : p_scmrbl_resp + part_scrmbl_req_ready = '0; + part_scrmbl_rsp_valid = '0; + part_scrmbl_req_ready[scrmbl_mtx_idx] = scrmbl_arb_req_ready; + part_scrmbl_rsp_valid[scrmbl_mtx_idx] = scrmbl_arb_rsp_valid; + end + + ///////////////////////////// + // Direct Access Interface // + ///////////////////////////// + + logic part_init_req; + logic [NumPart-1:0] part_init_done; + part_access_t [NumPart-1:0] part_access_dai; + + // The init request comes from the power manager, which lives in the AON clock domain. + logic pwr_otp_req_synced; + prim_flop_2sync #( + .Width(1) + ) u_otp_init_sync ( + .clk_i, + .rst_ni, + .d_i ( pwr_otp_i.otp_init ), + .q_o ( pwr_otp_req_synced ) + ); + + // Register this signal as it has to cross a clock boundary. + logic pwr_otp_rsp_d, pwr_otp_rsp_q; + assign pwr_otp_o.otp_done = pwr_otp_rsp_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_init_reg + if (!rst_ni) begin + pwr_otp_rsp_q <= 1'b0; + end else begin + pwr_otp_rsp_q <= pwr_otp_rsp_d; + end + end + + otp_ctrl_dai u_otp_ctrl_dai ( + .clk_i, + .rst_ni, + .init_req_i ( pwr_otp_req_synced ), + .init_done_o ( pwr_otp_rsp_d ), + .part_init_req_o ( part_init_req ), + .part_init_done_i ( part_init_done ), + .escalate_en_i ( lc_escalate_en[DaiIdx] ), + .error_o ( part_error[DaiIdx] ), + .fsm_err_o ( part_fsm_err[DaiIdx] ), + .part_access_i ( part_access_dai ), + .dai_addr_i ( dai_addr ), + .dai_cmd_i ( dai_cmd ), + .dai_req_i ( dai_req ), + .dai_wdata_i ( dai_wdata ), + .dai_idle_o ( dai_idle ), + .dai_prog_idle_o ( dai_prog_idle ), + .dai_cmd_done_o ( otp_operation_done ), + .dai_rdata_o ( dai_rdata ), + .otp_req_o ( part_otp_arb_req[DaiIdx] ), + .otp_cmd_o ( part_otp_arb_bundle[DaiIdx].cmd ), + .otp_size_o ( part_otp_arb_bundle[DaiIdx].size ), + .otp_wdata_o ( part_otp_arb_bundle[DaiIdx].wdata ), + .otp_addr_o ( part_otp_arb_bundle[DaiIdx].addr ), + .otp_gnt_i ( part_otp_arb_gnt[DaiIdx] ), + .otp_rvalid_i ( part_otp_rvalid[DaiIdx] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ), + .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[DaiIdx] ), + .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[DaiIdx] ), + .scrmbl_cmd_o ( part_scrmbl_req_bundle[DaiIdx].cmd ), + .scrmbl_mode_o ( part_scrmbl_req_bundle[DaiIdx].mode ), + .scrmbl_sel_o ( part_scrmbl_req_bundle[DaiIdx].sel ), + .scrmbl_data_o ( part_scrmbl_req_bundle[DaiIdx].data ), + .scrmbl_valid_o ( part_scrmbl_req_bundle[DaiIdx].valid ), + .scrmbl_ready_i ( part_scrmbl_req_ready[DaiIdx] ), + .scrmbl_valid_i ( part_scrmbl_rsp_valid[DaiIdx] ), + .scrmbl_data_i ( part_scrmbl_rsp_data ) + ); + + //////////////////////////////////// + // Lifecycle Transition Interface // + //////////////////////////////////// + + logic [PartInfo[LifeCycleIdx].size-1:0][7:0] lc_otp_program_data; + assign lc_otp_program_data[LcStateOffset-LifeCycleOffset +: LcStateSize] = + lc_otp_program_i.state; + assign lc_otp_program_data[LcTransitionCntOffset-LifeCycleOffset +: LcTransitionCntSize] = + lc_otp_program_i.count; + + otp_ctrl_lci #( + .Info(PartInfo[LifeCycleIdx]) + ) u_otp_ctrl_lci ( + .clk_i, + .rst_ni, + .lci_en_i ( pwr_otp_o.otp_done ), + .escalate_en_i ( lc_escalate_en[LciIdx] ), + .error_o ( part_error[LciIdx] ), + .fsm_err_o ( part_fsm_err[LciIdx] ), + .lci_prog_idle_o ( lci_prog_idle ), + .lc_req_i ( lc_otp_program_i.req ), + .lc_data_i ( lc_otp_program_data ), + .lc_ack_o ( lc_otp_program_o.ack ), + .lc_err_o ( lc_otp_program_o.err ), + .otp_req_o ( part_otp_arb_req[LciIdx] ), + .otp_cmd_o ( part_otp_arb_bundle[LciIdx].cmd ), + .otp_size_o ( part_otp_arb_bundle[LciIdx].size ), + .otp_wdata_o ( part_otp_arb_bundle[LciIdx].wdata ), + .otp_addr_o ( part_otp_arb_bundle[LciIdx].addr ), + .otp_gnt_i ( part_otp_arb_gnt[LciIdx] ), + .otp_rvalid_i ( part_otp_rvalid[LciIdx] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ) + ); + + // Tie off unused connections. + assign part_scrmbl_mtx_req[LciIdx] = '0; + assign part_scrmbl_req_bundle[LciIdx] = '0; + + // This stops lint from complaining about unused signals. + logic unused_lci_scrmbl_sigs; + assign unused_lci_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[LciIdx], + part_scrmbl_req_ready[LciIdx], + part_scrmbl_rsp_valid[LciIdx]}; + + //////////////////////////////////// + // Key Derivation Interface (KDI) // + //////////////////////////////////// + + logic scrmbl_key_seed_valid; + logic [SramKeySeedWidth-1:0] sram_data_key_seed; + + otp_ctrl_kdi #( + .RndCnstScrmblKeyInit(RndCnstScrmblKeyInit) + ) u_otp_ctrl_kdi ( + .clk_i, + .rst_ni, + .kdi_en_i ( pwr_otp_o.otp_done ), + .escalate_en_i ( lc_escalate_en[KdiIdx] ), + .fsm_err_o ( part_fsm_err[KdiIdx] ), + .scrmbl_key_seed_valid_i ( scrmbl_key_seed_valid ), + .sram_data_key_seed_i ( sram_data_key_seed ), + .edn_req_o ( key_edn_req ), + .edn_ack_i ( key_edn_ack ), + .edn_data_i ( edn_data ), + .sram_otp_key_i, + .sram_otp_key_o, + .otbn_otp_key_i, + .otbn_otp_key_o, + .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[KdiIdx] ), + .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[KdiIdx] ), + .scrmbl_cmd_o ( part_scrmbl_req_bundle[KdiIdx].cmd ), + .scrmbl_mode_o ( part_scrmbl_req_bundle[KdiIdx].mode ), + .scrmbl_sel_o ( part_scrmbl_req_bundle[KdiIdx].sel ), + .scrmbl_data_o ( part_scrmbl_req_bundle[KdiIdx].data ), + .scrmbl_valid_o ( part_scrmbl_req_bundle[KdiIdx].valid ), + .scrmbl_ready_i ( part_scrmbl_req_ready[KdiIdx] ), + .scrmbl_valid_i ( part_scrmbl_rsp_valid[KdiIdx] ), + .scrmbl_data_i ( part_scrmbl_rsp_data ) + ); + + // Tie off OTP bus access, since this is not needed. + assign part_otp_arb_req[KdiIdx] = 1'b0; + assign part_otp_arb_bundle[KdiIdx] = '0; + + // This stops lint from complaining about unused signals. + logic unused_kdi_otp_sigs; + assign unused_kdi_otp_sigs = ^{part_otp_arb_gnt[KdiIdx], + part_otp_rvalid[KdiIdx]}; + + ///////////////////////// + // Partition Instances // + ///////////////////////// + + logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data; + + for (genvar k = 0; k < NumPart; k ++) begin : gen_partitions + //////////////////////////////////////////////////////////////////////////////////////////////// + if (PartInfo[k].variant == Unbuffered) begin : gen_unbuffered + otp_ctrl_part_unbuf #( + .Info(PartInfo[k]) + ) u_part_unbuf ( + .clk_i, + .rst_ni, + .init_req_i ( part_init_req ), + .init_done_o ( part_init_done[k] ), + .escalate_en_i ( lc_escalate_en[k] ), + .error_o ( part_error[k] ), + .fsm_err_o ( part_fsm_err[k] ), + .access_i ( part_access[k] ), + .access_o ( part_access_dai[k] ), + .digest_o ( part_digest[k] ), + .tlul_req_i ( part_tlul_req[k] ), + .tlul_gnt_o ( part_tlul_gnt[k] ), + .tlul_addr_i ( part_tlul_addr ), + .tlul_rerror_o ( part_tlul_rerror[k] ), + .tlul_rvalid_o ( part_tlul_rvalid[k] ), + .tlul_rdata_o ( part_tlul_rdata[k] ), + .otp_req_o ( part_otp_arb_req[k] ), + .otp_cmd_o ( part_otp_arb_bundle[k].cmd ), + .otp_size_o ( part_otp_arb_bundle[k].size ), + .otp_wdata_o ( part_otp_arb_bundle[k].wdata ), + .otp_addr_o ( part_otp_arb_bundle[k].addr ), + .otp_gnt_i ( part_otp_arb_gnt[k] ), + .otp_rvalid_i ( part_otp_rvalid[k] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ) + ); + + // Tie off unused connections. + assign part_scrmbl_mtx_req[k] = '0; + assign part_scrmbl_req_bundle[k] = '0; + // These checks do not exist in this partition type, + // so we always acknowledge the request. + assign integ_chk_ack[k] = 1'b1; + assign cnsty_chk_ack[k] = 1'b1; + + // No buffered data to expose. + assign part_buf_data[PartInfo[k].offset +: PartInfo[k].size] = '0; + + // This stops lint from complaining about unused signals. + logic unused_part_scrmbl_sigs; + assign unused_part_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[k], + part_scrmbl_req_ready[k], + part_scrmbl_rsp_valid[k], + integ_chk_req[k], + cnsty_chk_req[k]}; + + // Alert assertion for sparse FSM. + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartUnbufFsmCheck_A, + u_part_unbuf.u_state_regs, alert_tx_o[1]) + //////////////////////////////////////////////////////////////////////////////////////////////// + end else if (PartInfo[k].variant == Buffered) begin : gen_buffered + otp_ctrl_part_buf #( + .Info(PartInfo[k]), + .DataDefault(PartInvDefault[PartInfo[k].offset*8 +: PartInfo[k].size*8]) + ) u_part_buf ( + .clk_i, + .rst_ni, + .init_req_i ( part_init_req ), + .init_done_o ( part_init_done[k] ), + .integ_chk_req_i ( integ_chk_req[k] ), + .integ_chk_ack_o ( integ_chk_ack[k] ), + .cnsty_chk_req_i ( cnsty_chk_req[k] ), + .cnsty_chk_ack_o ( cnsty_chk_ack[k] ), + .escalate_en_i ( lc_escalate_en[k] ), + // Only supported by life cycle partition (see further below). + .check_byp_en_i ( lc_ctrl_pkg::Off ), + .error_o ( part_error[k] ), + .fsm_err_o ( part_fsm_err[k] ), + .access_i ( part_access[k] ), + .access_o ( part_access_dai[k] ), + .digest_o ( part_digest[k] ), + .data_o ( part_buf_data[PartInfo[k].offset +: PartInfo[k].size] ), + .otp_req_o ( part_otp_arb_req[k] ), + .otp_cmd_o ( part_otp_arb_bundle[k].cmd ), + .otp_size_o ( part_otp_arb_bundle[k].size ), + .otp_wdata_o ( part_otp_arb_bundle[k].wdata ), + .otp_addr_o ( part_otp_arb_bundle[k].addr ), + .otp_gnt_i ( part_otp_arb_gnt[k] ), + .otp_rvalid_i ( part_otp_rvalid[k] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ), + .scrmbl_mtx_req_o ( part_scrmbl_mtx_req[k] ), + .scrmbl_mtx_gnt_i ( part_scrmbl_mtx_gnt[k] ), + .scrmbl_cmd_o ( part_scrmbl_req_bundle[k].cmd ), + .scrmbl_mode_o ( part_scrmbl_req_bundle[k].mode ), + .scrmbl_sel_o ( part_scrmbl_req_bundle[k].sel ), + .scrmbl_data_o ( part_scrmbl_req_bundle[k].data ), + .scrmbl_valid_o ( part_scrmbl_req_bundle[k].valid ), + .scrmbl_ready_i ( part_scrmbl_req_ready[k] ), + .scrmbl_valid_i ( part_scrmbl_rsp_valid[k] ), + .scrmbl_data_i ( part_scrmbl_rsp_data ) + ); + + // Buffered partitions are not accessible via the TL-UL window. + logic unused_part_tlul_sigs; + assign unused_part_tlul_sigs = ^part_tlul_req[k]; + assign part_tlul_gnt[k] = 1'b0; + assign part_tlul_rerror[k] = '0; + assign part_tlul_rvalid[k] = 1'b0; + assign part_tlul_rdata[k] = '0; + + // Alert assertion for sparse FSM. + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartBufFsmCheck_A, + u_part_buf.u_state_regs, alert_tx_o[1]) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntPartBufCheck_A, + u_part_buf.u_prim_count, alert_tx_o[1]) + //////////////////////////////////////////////////////////////////////////////////////////////// + end else if (PartInfo[k].variant == LifeCycle) begin : gen_lifecycle + otp_ctrl_part_buf #( + .Info(PartInfo[k]), + .DataDefault(PartInvDefault[PartInfo[k].offset*8 +: PartInfo[k].size*8]) + ) u_part_buf ( + .clk_i, + .rst_ni, + .init_req_i ( part_init_req ), + .init_done_o ( part_init_done[k] ), + .integ_chk_req_i ( integ_chk_req[k] ), + .integ_chk_ack_o ( integ_chk_ack[k] ), + .cnsty_chk_req_i ( cnsty_chk_req[k] ), + .cnsty_chk_ack_o ( cnsty_chk_ack[k] ), + .escalate_en_i ( lc_escalate_en[k] ), + // This is only supported by the life cycle partition. We need to prevent this partition + // from escalating once the life cycle state in memory is being updated (and hence not + // consistent with the values in the buffer regs anymore). + .check_byp_en_i ( lc_check_byp_en ), + .error_o ( part_error[k] ), + .fsm_err_o ( part_fsm_err[k] ), + .access_i ( part_access[k] ), + .access_o ( part_access_dai[k] ), + .digest_o ( part_digest[k] ), + .data_o ( part_buf_data[PartInfo[k].offset +: PartInfo[k].size] ), + .otp_req_o ( part_otp_arb_req[k] ), + .otp_cmd_o ( part_otp_arb_bundle[k].cmd ), + .otp_size_o ( part_otp_arb_bundle[k].size ), + .otp_wdata_o ( part_otp_arb_bundle[k].wdata ), + .otp_addr_o ( part_otp_arb_bundle[k].addr ), + .otp_gnt_i ( part_otp_arb_gnt[k] ), + .otp_rvalid_i ( part_otp_rvalid[k] ), + .otp_rdata_i ( part_otp_rdata ), + .otp_err_i ( part_otp_err ), + // The LC partition does not need any scrambling features. + .scrmbl_mtx_req_o ( ), + .scrmbl_mtx_gnt_i ( 1'b0 ), + .scrmbl_cmd_o ( ), + .scrmbl_mode_o ( ), + .scrmbl_sel_o ( ), + .scrmbl_data_o ( ), + .scrmbl_valid_o ( ), + .scrmbl_ready_i ( 1'b0 ), + .scrmbl_valid_i ( 1'b0 ), + .scrmbl_data_i ( '0 ) + ); + + // Buffered partitions are not accessible via the TL-UL window. + logic unused_part_tlul_sigs; + assign unused_part_tlul_sigs = ^part_tlul_req[k]; + assign part_tlul_gnt[k] = 1'b0; + assign part_tlul_rerror[k] = '0; + assign part_tlul_rvalid[k] = 1'b0; + assign part_tlul_rdata[k] = '0; + + // Tie off unused connections. + assign part_scrmbl_mtx_req[k] = '0; + assign part_scrmbl_req_bundle[k] = '0; + + // This stops lint from complaining about unused signals. + logic unused_part_scrmbl_sigs; + assign unused_part_scrmbl_sigs = ^{part_scrmbl_mtx_gnt[k], + part_scrmbl_req_ready[k], + part_scrmbl_rsp_valid[k]}; + // Alert assertion for sparse FSM. + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlPartLcFsmCheck_A, + u_part_buf.u_state_regs, alert_tx_o[1]) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntPartLcCheck_A, + u_part_buf.u_prim_count, alert_tx_o[1]) + //////////////////////////////////////////////////////////////////////////////////////////////// + end else begin : gen_invalid + // This is invalid and should break elaboration + assert_static_in_generate_invalid assert_static_in_generate_invalid(); + end + //////////////////////////////////////////////////////////////////////////////////////////////// + end + + ////////////////////////////////// + // Buffered Data Output Mapping // + ////////////////////////////////// + + // Output complete hardware config partition. + // Actual mapping to other IPs is done via the intersignal topgen feature, + // selection of fields can be done using the otp_hw_cfg_t struct fields. + otp_broadcast_t otp_broadcast; + assign otp_broadcast = named_broadcast_assign(part_init_done, part_buf_data); + + // Make sure the broadcast valid is flopped before sending it out. + lc_ctrl_pkg::lc_tx_t otp_broadcast_valid_q; + prim_lc_sender u_prim_lc_sender_otp_broadcast_valid ( + .clk_i, + .rst_ni, + .lc_en_i(otp_broadcast.valid), + .lc_en_o(otp_broadcast_valid_q) + ); + + always_comb begin : p_otp_broadcast_valid + otp_broadcast_o = otp_broadcast; + otp_broadcast_o.valid = otp_broadcast_valid_q; + end + + // Root keys and seeds. + // This uses a generated function to assign all collateral that is marked with "iskeymgr" in + // the memory map. Note that in this case the type is static and represents a superset of all + // options so that we can maintain a stable interface with keymgr (otherwise keymgr will have + // to be templated as well. Unused key material will be tied off to '0. The keymgr has to be + // parameterized accordingly (via SV parameters) to consume the correct key material. + // + // The key material valid signals are set to true if the corresponding digest is nonzero and the + // partition is initialized. On top of that, the entire output is gated by lc_seed_hw_rd_en. + otp_keymgr_key_t otp_keymgr_key; + assign otp_keymgr_key = named_keymgr_key_assign(part_digest, + part_buf_data, + lc_seed_hw_rd_en); + + // Note regarding these breakouts: named_keymgr_key_assign will tie off unused key material / + // valid signals to '0. This is the case for instance in system configurations that keep the seed + // material in the flash instead of OTP. + logic creator_root_key_share0_valid_d, creator_root_key_share0_valid_q; + logic creator_root_key_share1_valid_d, creator_root_key_share1_valid_q; + logic creator_seed_valid_d, creator_seed_valid_q; + logic owner_seed_valid_d, owner_seed_valid_q; + prim_flop #( + .Width(4) + ) u_keygmr_key_valid ( + .clk_i, + .rst_ni, + .d_i ({creator_root_key_share0_valid_d, + creator_root_key_share1_valid_d, + creator_seed_valid_d, + owner_seed_valid_d}), + .q_o ({creator_root_key_share0_valid_q, + creator_root_key_share1_valid_q, + creator_seed_valid_q, + owner_seed_valid_q}) + ); + + always_comb begin : p_otp_keymgr_key_valid + // Valid reg inputs + creator_root_key_share0_valid_d = otp_keymgr_key.creator_root_key_share0_valid; + creator_root_key_share1_valid_d = otp_keymgr_key.creator_root_key_share1_valid; + creator_seed_valid_d = otp_keymgr_key.creator_seed_valid; + owner_seed_valid_d = otp_keymgr_key.owner_seed_valid; + // Output to keymgr + otp_keymgr_key_o = otp_keymgr_key; + otp_keymgr_key_o.creator_root_key_share0_valid = creator_root_key_share0_valid_q; + otp_keymgr_key_o.creator_root_key_share1_valid = creator_root_key_share1_valid_q; + otp_keymgr_key_o.creator_seed_valid = creator_seed_valid_q; + otp_keymgr_key_o.owner_seed_valid = owner_seed_valid_q; + end + + // Check that the lc_seed_hw_rd_en remains stable, once the key material is valid. + `ASSERT(LcSeedHwRdEnStable0_A, + $rose(creator_root_key_share0_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$], + clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating + ) + `ASSERT(LcSeedHwRdEnStable1_A, + $rose(creator_root_key_share1_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$], + clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating + ) + `ASSERT(LcSeedHwRdEnStable2_A, + $rose(creator_seed_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$], + clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating + ) + `ASSERT(LcSeedHwRdEnStable3_A, + $rose(owner_seed_valid_q) |=> $stable(lc_seed_hw_rd_en) [*1:$], + clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i) // Disable if escalating + ) + + // Scrambling Keys + assign scrmbl_key_seed_valid = part_digest[Secret1Idx] != '0; + assign sram_data_key_seed = part_buf_data[SramDataKeySeedOffset +: + SramDataKeySeedSize]; + + // Test unlock and exit tokens and RMA token + assign otp_lc_data_o.test_exit_token = part_buf_data[TestExitTokenOffset +: + TestExitTokenSize]; + assign otp_lc_data_o.test_unlock_token = part_buf_data[TestUnlockTokenOffset +: + TestUnlockTokenSize]; + assign otp_lc_data_o.rma_token = part_buf_data[RmaTokenOffset +: + RmaTokenSize]; + + lc_ctrl_pkg::lc_tx_t test_tokens_valid, rma_token_valid, secrets_valid; + // The test tokens have been provisioned. + assign test_tokens_valid = (part_digest[Secret0Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + // The rma token has been provisioned. + assign rma_token_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + // The device is personalized if the root key has been provisioned and locked. + assign secrets_valid = (part_digest[Secret2Idx] != '0) ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + + // Buffer these constants in order to ensure that synthesis does not try to optimize the encoding. + // SEC_CM: TOKEN_VALID.CTRL.MUBI + prim_lc_sender #( + .AsyncOn(0) + ) u_prim_lc_sender_test_tokens_valid ( + .clk_i, + .rst_ni, + .lc_en_i(test_tokens_valid), + .lc_en_o(otp_lc_data_o.test_tokens_valid) + ); + + prim_lc_sender #( + .AsyncOn(0) + ) u_prim_lc_sender_rma_token_valid ( + .clk_i, + .rst_ni, + .lc_en_i(rma_token_valid), + .lc_en_o(otp_lc_data_o.rma_token_valid) + ); + + prim_lc_sender #( + .AsyncOn(0) + ) u_prim_lc_sender_secrets_valid ( + .clk_i, + .rst_ni, + .lc_en_i(secrets_valid), + .lc_en_o(otp_lc_data_o.secrets_valid) + ); + + // Lifecycle state + assign otp_lc_data_o.state = lc_ctrl_state_pkg::lc_state_e'(part_buf_data[LcStateOffset +: + LcStateSize]); + assign otp_lc_data_o.count = lc_ctrl_state_pkg::lc_cnt_e'(part_buf_data[LcTransitionCntOffset +: + LcTransitionCntSize]); + + // Assert life cycle state valid signal only when all partitions have initialized. + assign otp_lc_data_o.valid = &part_init_done; + // Signal whether there are any errors in the life cycle partition (both correctable and + // uncorrectable ones). This bit is made available via the JTAG TAP, which is useful for + // production testing in RAW life cycle state where the OTP regs are not accessible. + assign otp_lc_data_o.error = |part_error[LifeCycleIdx]; + + // Not all bits of part_buf_data are used here. + logic unused_buf_data; + assign unused_buf_data = ^part_buf_data; + + //////////////// + // Assertions // + //////////////// + + `ASSERT_INIT(CreatorRootKeyShare0Size_A, KeyMgrKeyWidth == CreatorRootKeyShare0Size * 8) + `ASSERT_INIT(CreatorRootKeyShare1Size_A, KeyMgrKeyWidth == CreatorRootKeyShare1Size * 8) + `ASSERT_INIT(SramDataKeySeedSize_A, SramKeySeedWidth == SramDataKeySeedSize * 8) + + `ASSERT_INIT(RmaTokenSize_A, lc_ctrl_state_pkg::LcTokenWidth == RmaTokenSize * 8) + `ASSERT_INIT(TestUnlockTokenSize_A, lc_ctrl_state_pkg::LcTokenWidth == TestUnlockTokenSize * 8) + `ASSERT_INIT(TestExitTokenSize_A, lc_ctrl_state_pkg::LcTokenWidth == TestExitTokenSize * 8) + `ASSERT_INIT(LcStateSize_A, lc_ctrl_state_pkg::LcStateWidth == LcStateSize * 8) + `ASSERT_INIT(LcTransitionCntSize_A, lc_ctrl_state_pkg::LcCountWidth == LcTransitionCntSize * 8) + + `ASSERT_KNOWN(CoreTlOutKnown_A, core_tl_o) + `ASSERT_KNOWN(IntrOtpOperationDoneKnown_A, intr_otp_operation_done_o) + `ASSERT_KNOWN(IntrOtpErrorKnown_A, intr_otp_error_o) + `ASSERT_KNOWN(AlertTxKnown_A, alert_tx_o) + `ASSERT_KNOWN(PwrOtpInitRspKnown_A, pwr_otp_o) + `ASSERT_KNOWN(LcOtpProgramRspKnown_A, lc_otp_program_o) + `ASSERT_KNOWN(OtpLcDataKnown_A, otp_lc_data_o) + `ASSERT_KNOWN(OtpKeymgrKeyKnown_A, otp_keymgr_key_o) + `ASSERT_KNOWN(OtpSramKeyKnown_A, sram_otp_key_o) + `ASSERT_KNOWN(OtpOtgnKeyKnown_A, otbn_otp_key_o) + `ASSERT_KNOWN(OtpBroadcastKnown_A, otp_broadcast_o) + + // Alert assertions for sparse FSMs. + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlDaiFsmCheck_A, + u_otp_ctrl_dai.u_state_regs, alert_tx_o[1]) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlKdiFsmCheck_A, + u_otp_ctrl_kdi.u_state_regs, alert_tx_o[1]) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlLciFsmCheck_A, + u_otp_ctrl_lci.u_state_regs, alert_tx_o[1]) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlLfsrTimerFsmCheck_A, + u_otp_ctrl_lfsr_timer.u_state_regs, alert_tx_o[1]) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(CtrlScrambleFsmCheck_A, + u_otp_ctrl_scrmbl.u_state_regs, alert_tx_o[1]) + + // Alert assertions for redundant counters. + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntIntegCheck_A, + u_otp_ctrl_lfsr_timer.u_prim_count_integ, alert_tx_o[1]) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntCnstyCheck_A, + u_otp_ctrl_lfsr_timer.u_prim_count_cnsty, alert_tx_o[1]) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntDaiCheck_A, + u_otp_ctrl_dai.u_prim_count, alert_tx_o[1]) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntKdiSeedCheck_A, + u_otp_ctrl_kdi.u_prim_count_seed, alert_tx_o[1]) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntKdiEntropyCheck_A, + u_otp_ctrl_kdi.u_prim_count_entropy, alert_tx_o[1]) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntLciCheck_A, + u_otp_ctrl_lci.u_prim_count, alert_tx_o[1]) + `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(CntScrmblCheck_A, + u_otp_ctrl_scrmbl.u_prim_count, alert_tx_o[1]) + + // Alert assertions for double LFSR. + `ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ALERT(DoubleLfsrCheck_A, + u_otp_ctrl_lfsr_timer.u_prim_double_lfsr, alert_tx_o[1]) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg_core, alert_tx_o[2]) + + // IMPORTANT TODO: + // Add checks that the incoming fatal conditions from prim_otp trigger alerts. + + // Assertions for countermeasures inside prim_otp + // `ifndef PRIM_DEFAULT_IMPL + // `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric + // `endif + // if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_reg_we_assert_generic + // `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(TlLcGateFsm_A, + // u_tlul_lc_gate.u_state_regs, alert_tx_o[2]) + // `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(PrimFsmCheck_A, + // u_otp.gen_generic.u_impl_generic.u_state_regs, alert_tx_o[3]) + // `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A, + // u_otp.gen_generic.u_impl_generic.u_reg_top, alert_tx_o[3]) + // end +endmodule : otp_ctrl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_core_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_core_reg_top.sv new file mode 100644 index 00000000000..d68d7ba1c73 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_core_reg_top.sv @@ -0,0 +1,3995 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module otp_ctrl_core_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Output port for window + output tlul_pkg::tl_h2d_t tl_win_o, + input tlul_pkg::tl_d2h_t tl_win_i, + + // To HW + output otp_ctrl_reg_pkg::otp_ctrl_core_reg2hw_t reg2hw, // Write + input otp_ctrl_reg_pkg::otp_ctrl_core_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import otp_ctrl_reg_pkg::* ; + + localparam int AW = 15; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [94:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(95) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + tlul_pkg::tl_h2d_t tl_socket_h2d [2]; + tlul_pkg::tl_d2h_t tl_socket_d2h [2]; + + logic [0:0] reg_steer; + + // socket_1n connection + assign tl_reg_h2d = tl_socket_h2d[1]; + assign tl_socket_d2h[1] = tl_reg_d2h; + + assign tl_win_o = tl_socket_h2d[0]; + assign tl_socket_d2h[0] = tl_win_i; + + // Create Socket_1n + tlul_socket_1n #( + .N (2), + .HReqPass (1'b1), + .HRspPass (1'b1), + .DReqPass ({2{1'b1}}), + .DRspPass ({2{1'b1}}), + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth ({2{4'h0}}), + .DRspDepth ({2{4'h0}}), + .ExplicitErrs (1'b0) + ) u_socket ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .tl_h_i (tl_i), + .tl_h_o (tl_o_pre), + .tl_d_o (tl_socket_h2d), + .tl_d_i (tl_socket_d2h), + .dev_select_i (reg_steer) + ); + + // Create steering logic + always_comb begin + reg_steer = + tl_i.a_address[AW-1:0] inside {[16384:32767]} ? 1'd0 : + // Default set to register + 1'd1; + + // Override this in case of an integrity error + if (intg_err) begin + reg_steer = 1'd1; + end + end + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic intr_state_otp_operation_done_qs; + logic intr_state_otp_operation_done_wd; + logic intr_state_otp_error_qs; + logic intr_state_otp_error_wd; + logic intr_enable_we; + logic intr_enable_otp_operation_done_qs; + logic intr_enable_otp_operation_done_wd; + logic intr_enable_otp_error_qs; + logic intr_enable_otp_error_wd; + logic intr_test_we; + logic intr_test_otp_operation_done_wd; + logic intr_test_otp_error_wd; + logic alert_test_we; + logic alert_test_fatal_macro_error_wd; + logic alert_test_fatal_check_error_wd; + logic alert_test_fatal_bus_integ_error_wd; + logic alert_test_fatal_prim_otp_alert_wd; + logic alert_test_recov_prim_otp_alert_wd; + logic status_re; + logic status_vendor_test_error_qs; + logic status_creator_sw_cfg_error_qs; + logic status_owner_sw_cfg_error_qs; + logic status_ownership_slot_state_error_qs; + logic status_rot_creator_auth_error_qs; + logic status_rot_owner_auth_slot0_error_qs; + logic status_rot_owner_auth_slot1_error_qs; + logic status_plat_integ_auth_slot0_error_qs; + logic status_plat_integ_auth_slot1_error_qs; + logic status_plat_owner_auth_slot0_error_qs; + logic status_plat_owner_auth_slot1_error_qs; + logic status_plat_owner_auth_slot2_error_qs; + logic status_plat_owner_auth_slot3_error_qs; + logic status_ext_nvm_error_qs; + logic status_rom_patch_error_qs; + logic status_hw_cfg0_error_qs; + logic status_hw_cfg1_error_qs; + logic status_secret0_error_qs; + logic status_secret1_error_qs; + logic status_secret2_error_qs; + logic status_secret3_error_qs; + logic status_life_cycle_error_qs; + logic status_dai_error_qs; + logic status_lci_error_qs; + logic status_timeout_error_qs; + logic status_lfsr_fsm_error_qs; + logic status_scrambling_fsm_error_qs; + logic status_key_deriv_fsm_error_qs; + logic status_bus_integ_error_qs; + logic status_dai_idle_qs; + logic status_check_pending_qs; + logic err_code_0_re; + logic [2:0] err_code_0_qs; + logic err_code_1_re; + logic [2:0] err_code_1_qs; + logic err_code_2_re; + logic [2:0] err_code_2_qs; + logic err_code_3_re; + logic [2:0] err_code_3_qs; + logic err_code_4_re; + logic [2:0] err_code_4_qs; + logic err_code_5_re; + logic [2:0] err_code_5_qs; + logic err_code_6_re; + logic [2:0] err_code_6_qs; + logic err_code_7_re; + logic [2:0] err_code_7_qs; + logic err_code_8_re; + logic [2:0] err_code_8_qs; + logic err_code_9_re; + logic [2:0] err_code_9_qs; + logic err_code_10_re; + logic [2:0] err_code_10_qs; + logic err_code_11_re; + logic [2:0] err_code_11_qs; + logic err_code_12_re; + logic [2:0] err_code_12_qs; + logic err_code_13_re; + logic [2:0] err_code_13_qs; + logic err_code_14_re; + logic [2:0] err_code_14_qs; + logic err_code_15_re; + logic [2:0] err_code_15_qs; + logic err_code_16_re; + logic [2:0] err_code_16_qs; + logic err_code_17_re; + logic [2:0] err_code_17_qs; + logic err_code_18_re; + logic [2:0] err_code_18_qs; + logic err_code_19_re; + logic [2:0] err_code_19_qs; + logic err_code_20_re; + logic [2:0] err_code_20_qs; + logic err_code_21_re; + logic [2:0] err_code_21_qs; + logic err_code_22_re; + logic [2:0] err_code_22_qs; + logic err_code_23_re; + logic [2:0] err_code_23_qs; + logic direct_access_regwen_re; + logic direct_access_regwen_we; + logic direct_access_regwen_qs; + logic direct_access_regwen_wd; + logic direct_access_cmd_we; + logic direct_access_cmd_rd_wd; + logic direct_access_cmd_wr_wd; + logic direct_access_cmd_digest_wd; + logic direct_access_address_we; + logic [13:0] direct_access_address_qs; + logic [13:0] direct_access_address_wd; + logic direct_access_wdata_0_we; + logic [31:0] direct_access_wdata_0_qs; + logic [31:0] direct_access_wdata_0_wd; + logic direct_access_wdata_1_we; + logic [31:0] direct_access_wdata_1_qs; + logic [31:0] direct_access_wdata_1_wd; + logic direct_access_rdata_0_re; + logic [31:0] direct_access_rdata_0_qs; + logic direct_access_rdata_1_re; + logic [31:0] direct_access_rdata_1_qs; + logic check_trigger_regwen_we; + logic check_trigger_regwen_qs; + logic check_trigger_regwen_wd; + logic check_trigger_we; + logic check_trigger_integrity_wd; + logic check_trigger_consistency_wd; + logic check_regwen_we; + logic check_regwen_qs; + logic check_regwen_wd; + logic check_timeout_we; + logic [31:0] check_timeout_qs; + logic [31:0] check_timeout_wd; + logic integrity_check_period_we; + logic [31:0] integrity_check_period_qs; + logic [31:0] integrity_check_period_wd; + logic consistency_check_period_we; + logic [31:0] consistency_check_period_qs; + logic [31:0] consistency_check_period_wd; + logic vendor_test_read_lock_we; + logic vendor_test_read_lock_qs; + logic vendor_test_read_lock_wd; + logic creator_sw_cfg_read_lock_we; + logic creator_sw_cfg_read_lock_qs; + logic creator_sw_cfg_read_lock_wd; + logic owner_sw_cfg_read_lock_we; + logic owner_sw_cfg_read_lock_qs; + logic owner_sw_cfg_read_lock_wd; + logic ownership_slot_state_read_lock_we; + logic ownership_slot_state_read_lock_qs; + logic ownership_slot_state_read_lock_wd; + logic rot_creator_auth_read_lock_we; + logic rot_creator_auth_read_lock_qs; + logic rot_creator_auth_read_lock_wd; + logic rot_owner_auth_slot0_read_lock_we; + logic rot_owner_auth_slot0_read_lock_qs; + logic rot_owner_auth_slot0_read_lock_wd; + logic rot_owner_auth_slot1_read_lock_we; + logic rot_owner_auth_slot1_read_lock_qs; + logic rot_owner_auth_slot1_read_lock_wd; + logic plat_integ_auth_slot0_read_lock_we; + logic plat_integ_auth_slot0_read_lock_qs; + logic plat_integ_auth_slot0_read_lock_wd; + logic plat_integ_auth_slot1_read_lock_we; + logic plat_integ_auth_slot1_read_lock_qs; + logic plat_integ_auth_slot1_read_lock_wd; + logic plat_owner_auth_slot0_read_lock_we; + logic plat_owner_auth_slot0_read_lock_qs; + logic plat_owner_auth_slot0_read_lock_wd; + logic plat_owner_auth_slot1_read_lock_we; + logic plat_owner_auth_slot1_read_lock_qs; + logic plat_owner_auth_slot1_read_lock_wd; + logic plat_owner_auth_slot2_read_lock_we; + logic plat_owner_auth_slot2_read_lock_qs; + logic plat_owner_auth_slot2_read_lock_wd; + logic plat_owner_auth_slot3_read_lock_we; + logic plat_owner_auth_slot3_read_lock_qs; + logic plat_owner_auth_slot3_read_lock_wd; + logic ext_nvm_read_lock_we; + logic ext_nvm_read_lock_qs; + logic ext_nvm_read_lock_wd; + logic rom_patch_read_lock_we; + logic rom_patch_read_lock_qs; + logic rom_patch_read_lock_wd; + logic vendor_test_digest_0_re; + logic [31:0] vendor_test_digest_0_qs; + logic vendor_test_digest_1_re; + logic [31:0] vendor_test_digest_1_qs; + logic creator_sw_cfg_digest_0_re; + logic [31:0] creator_sw_cfg_digest_0_qs; + logic creator_sw_cfg_digest_1_re; + logic [31:0] creator_sw_cfg_digest_1_qs; + logic owner_sw_cfg_digest_0_re; + logic [31:0] owner_sw_cfg_digest_0_qs; + logic owner_sw_cfg_digest_1_re; + logic [31:0] owner_sw_cfg_digest_1_qs; + logic rot_creator_auth_digest_0_re; + logic [31:0] rot_creator_auth_digest_0_qs; + logic rot_creator_auth_digest_1_re; + logic [31:0] rot_creator_auth_digest_1_qs; + logic rot_owner_auth_slot0_digest_0_re; + logic [31:0] rot_owner_auth_slot0_digest_0_qs; + logic rot_owner_auth_slot0_digest_1_re; + logic [31:0] rot_owner_auth_slot0_digest_1_qs; + logic rot_owner_auth_slot1_digest_0_re; + logic [31:0] rot_owner_auth_slot1_digest_0_qs; + logic rot_owner_auth_slot1_digest_1_re; + logic [31:0] rot_owner_auth_slot1_digest_1_qs; + logic plat_integ_auth_slot0_digest_0_re; + logic [31:0] plat_integ_auth_slot0_digest_0_qs; + logic plat_integ_auth_slot0_digest_1_re; + logic [31:0] plat_integ_auth_slot0_digest_1_qs; + logic plat_integ_auth_slot1_digest_0_re; + logic [31:0] plat_integ_auth_slot1_digest_0_qs; + logic plat_integ_auth_slot1_digest_1_re; + logic [31:0] plat_integ_auth_slot1_digest_1_qs; + logic plat_owner_auth_slot0_digest_0_re; + logic [31:0] plat_owner_auth_slot0_digest_0_qs; + logic plat_owner_auth_slot0_digest_1_re; + logic [31:0] plat_owner_auth_slot0_digest_1_qs; + logic plat_owner_auth_slot1_digest_0_re; + logic [31:0] plat_owner_auth_slot1_digest_0_qs; + logic plat_owner_auth_slot1_digest_1_re; + logic [31:0] plat_owner_auth_slot1_digest_1_qs; + logic plat_owner_auth_slot2_digest_0_re; + logic [31:0] plat_owner_auth_slot2_digest_0_qs; + logic plat_owner_auth_slot2_digest_1_re; + logic [31:0] plat_owner_auth_slot2_digest_1_qs; + logic plat_owner_auth_slot3_digest_0_re; + logic [31:0] plat_owner_auth_slot3_digest_0_qs; + logic plat_owner_auth_slot3_digest_1_re; + logic [31:0] plat_owner_auth_slot3_digest_1_qs; + logic rom_patch_digest_0_re; + logic [31:0] rom_patch_digest_0_qs; + logic rom_patch_digest_1_re; + logic [31:0] rom_patch_digest_1_qs; + logic hw_cfg0_digest_0_re; + logic [31:0] hw_cfg0_digest_0_qs; + logic hw_cfg0_digest_1_re; + logic [31:0] hw_cfg0_digest_1_qs; + logic hw_cfg1_digest_0_re; + logic [31:0] hw_cfg1_digest_0_qs; + logic hw_cfg1_digest_1_re; + logic [31:0] hw_cfg1_digest_1_qs; + logic secret0_digest_0_re; + logic [31:0] secret0_digest_0_qs; + logic secret0_digest_1_re; + logic [31:0] secret0_digest_1_qs; + logic secret1_digest_0_re; + logic [31:0] secret1_digest_0_qs; + logic secret1_digest_1_re; + logic [31:0] secret1_digest_1_qs; + logic secret2_digest_0_re; + logic [31:0] secret2_digest_0_qs; + logic secret2_digest_1_re; + logic [31:0] secret2_digest_1_qs; + logic secret3_digest_0_re; + logic [31:0] secret3_digest_0_qs; + logic secret3_digest_1_re; + logic [31:0] secret3_digest_1_qs; + + // Register instances + // R[intr_state]: V(False) + // F[otp_operation_done]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_otp_operation_done ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_otp_operation_done_wd), + + // from internal hardware + .de (hw2reg.intr_state.otp_operation_done.de), + .d (hw2reg.intr_state.otp_operation_done.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.otp_operation_done.q), + .ds (), + + // to register interface (read) + .qs (intr_state_otp_operation_done_qs) + ); + + // F[otp_error]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state_otp_error ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_otp_error_wd), + + // from internal hardware + .de (hw2reg.intr_state.otp_error.de), + .d (hw2reg.intr_state.otp_error.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.otp_error.q), + .ds (), + + // to register interface (read) + .qs (intr_state_otp_error_qs) + ); + + + // R[intr_enable]: V(False) + // F[otp_operation_done]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_otp_operation_done ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_otp_operation_done_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.otp_operation_done.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_otp_operation_done_qs) + ); + + // F[otp_error]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable_otp_error ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_otp_error_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.otp_error.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_otp_error_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [1:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + // F[otp_operation_done]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_otp_operation_done ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_otp_operation_done_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.otp_operation_done.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.otp_operation_done.qe = intr_test_qe; + + // F[otp_error]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_intr_test_otp_error ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_otp_error_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[1]), + .q (reg2hw.intr_test.otp_error.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.otp_error.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [4:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[fatal_macro_error]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_macro_error ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_macro_error_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.fatal_macro_error.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_macro_error.qe = alert_test_qe; + + // F[fatal_check_error]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_check_error ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_check_error_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_check_error.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_check_error.qe = alert_test_qe; + + // F[fatal_bus_integ_error]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_bus_integ_error ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_bus_integ_error_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[2]), + .q (reg2hw.alert_test.fatal_bus_integ_error.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_bus_integ_error.qe = alert_test_qe; + + // F[fatal_prim_otp_alert]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_prim_otp_alert ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_prim_otp_alert_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[3]), + .q (reg2hw.alert_test.fatal_prim_otp_alert.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_prim_otp_alert.qe = alert_test_qe; + + // F[recov_prim_otp_alert]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_prim_otp_alert ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_prim_otp_alert_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[4]), + .q (reg2hw.alert_test.recov_prim_otp_alert.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_prim_otp_alert.qe = alert_test_qe; + + + // R[status]: V(True) + // F[vendor_test_error]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_status_vendor_test_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.vendor_test_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_vendor_test_error_qs) + ); + + // F[creator_sw_cfg_error]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_status_creator_sw_cfg_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.creator_sw_cfg_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_creator_sw_cfg_error_qs) + ); + + // F[owner_sw_cfg_error]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_status_owner_sw_cfg_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.owner_sw_cfg_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_owner_sw_cfg_error_qs) + ); + + // F[ownership_slot_state_error]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_status_ownership_slot_state_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.ownership_slot_state_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_ownership_slot_state_error_qs) + ); + + // F[rot_creator_auth_error]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_status_rot_creator_auth_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.rot_creator_auth_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_rot_creator_auth_error_qs) + ); + + // F[rot_owner_auth_slot0_error]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_status_rot_owner_auth_slot0_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.rot_owner_auth_slot0_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_rot_owner_auth_slot0_error_qs) + ); + + // F[rot_owner_auth_slot1_error]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_status_rot_owner_auth_slot1_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.rot_owner_auth_slot1_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_rot_owner_auth_slot1_error_qs) + ); + + // F[plat_integ_auth_slot0_error]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_status_plat_integ_auth_slot0_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.plat_integ_auth_slot0_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_plat_integ_auth_slot0_error_qs) + ); + + // F[plat_integ_auth_slot1_error]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_status_plat_integ_auth_slot1_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.plat_integ_auth_slot1_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_plat_integ_auth_slot1_error_qs) + ); + + // F[plat_owner_auth_slot0_error]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_status_plat_owner_auth_slot0_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.plat_owner_auth_slot0_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_plat_owner_auth_slot0_error_qs) + ); + + // F[plat_owner_auth_slot1_error]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_status_plat_owner_auth_slot1_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.plat_owner_auth_slot1_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_plat_owner_auth_slot1_error_qs) + ); + + // F[plat_owner_auth_slot2_error]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_status_plat_owner_auth_slot2_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.plat_owner_auth_slot2_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_plat_owner_auth_slot2_error_qs) + ); + + // F[plat_owner_auth_slot3_error]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_status_plat_owner_auth_slot3_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.plat_owner_auth_slot3_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_plat_owner_auth_slot3_error_qs) + ); + + // F[ext_nvm_error]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_status_ext_nvm_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.ext_nvm_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_ext_nvm_error_qs) + ); + + // F[rom_patch_error]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_status_rom_patch_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.rom_patch_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_rom_patch_error_qs) + ); + + // F[hw_cfg0_error]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_status_hw_cfg0_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.hw_cfg0_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_hw_cfg0_error_qs) + ); + + // F[hw_cfg1_error]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_status_hw_cfg1_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.hw_cfg1_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_hw_cfg1_error_qs) + ); + + // F[secret0_error]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_status_secret0_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.secret0_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_secret0_error_qs) + ); + + // F[secret1_error]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_status_secret1_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.secret1_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_secret1_error_qs) + ); + + // F[secret2_error]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_status_secret2_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.secret2_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_secret2_error_qs) + ); + + // F[secret3_error]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_status_secret3_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.secret3_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_secret3_error_qs) + ); + + // F[life_cycle_error]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_status_life_cycle_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.life_cycle_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_life_cycle_error_qs) + ); + + // F[dai_error]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_status_dai_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.dai_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_dai_error_qs) + ); + + // F[lci_error]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_status_lci_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.lci_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_lci_error_qs) + ); + + // F[timeout_error]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_status_timeout_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.timeout_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_timeout_error_qs) + ); + + // F[lfsr_fsm_error]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_status_lfsr_fsm_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.lfsr_fsm_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_lfsr_fsm_error_qs) + ); + + // F[scrambling_fsm_error]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_status_scrambling_fsm_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.scrambling_fsm_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_scrambling_fsm_error_qs) + ); + + // F[key_deriv_fsm_error]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_status_key_deriv_fsm_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.key_deriv_fsm_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_key_deriv_fsm_error_qs) + ); + + // F[bus_integ_error]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_status_bus_integ_error ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.bus_integ_error.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_bus_integ_error_qs) + ); + + // F[dai_idle]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_status_dai_idle ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.dai_idle.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_dai_idle_qs) + ); + + // F[check_pending]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_status_check_pending ( + .re (status_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.status.check_pending.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (status_check_pending_qs) + ); + + + // Subregister 0 of Multireg err_code + // R[err_code_0]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_0 ( + .re (err_code_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_0_qs) + ); + + + // Subregister 1 of Multireg err_code + // R[err_code_1]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_1 ( + .re (err_code_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_1_qs) + ); + + + // Subregister 2 of Multireg err_code + // R[err_code_2]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_2 ( + .re (err_code_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[2].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_2_qs) + ); + + + // Subregister 3 of Multireg err_code + // R[err_code_3]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_3 ( + .re (err_code_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[3].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_3_qs) + ); + + + // Subregister 4 of Multireg err_code + // R[err_code_4]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_4 ( + .re (err_code_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[4].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_4_qs) + ); + + + // Subregister 5 of Multireg err_code + // R[err_code_5]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_5 ( + .re (err_code_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[5].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_5_qs) + ); + + + // Subregister 6 of Multireg err_code + // R[err_code_6]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_6 ( + .re (err_code_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[6].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_6_qs) + ); + + + // Subregister 7 of Multireg err_code + // R[err_code_7]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_7 ( + .re (err_code_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[7].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_7_qs) + ); + + + // Subregister 8 of Multireg err_code + // R[err_code_8]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_8 ( + .re (err_code_8_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[8].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_8_qs) + ); + + + // Subregister 9 of Multireg err_code + // R[err_code_9]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_9 ( + .re (err_code_9_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[9].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_9_qs) + ); + + + // Subregister 10 of Multireg err_code + // R[err_code_10]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_10 ( + .re (err_code_10_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[10].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_10_qs) + ); + + + // Subregister 11 of Multireg err_code + // R[err_code_11]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_11 ( + .re (err_code_11_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[11].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_11_qs) + ); + + + // Subregister 12 of Multireg err_code + // R[err_code_12]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_12 ( + .re (err_code_12_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[12].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_12_qs) + ); + + + // Subregister 13 of Multireg err_code + // R[err_code_13]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_13 ( + .re (err_code_13_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[13].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_13_qs) + ); + + + // Subregister 14 of Multireg err_code + // R[err_code_14]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_14 ( + .re (err_code_14_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[14].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_14_qs) + ); + + + // Subregister 15 of Multireg err_code + // R[err_code_15]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_15 ( + .re (err_code_15_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[15].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_15_qs) + ); + + + // Subregister 16 of Multireg err_code + // R[err_code_16]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_16 ( + .re (err_code_16_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[16].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_16_qs) + ); + + + // Subregister 17 of Multireg err_code + // R[err_code_17]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_17 ( + .re (err_code_17_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[17].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_17_qs) + ); + + + // Subregister 18 of Multireg err_code + // R[err_code_18]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_18 ( + .re (err_code_18_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[18].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_18_qs) + ); + + + // Subregister 19 of Multireg err_code + // R[err_code_19]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_19 ( + .re (err_code_19_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[19].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_19_qs) + ); + + + // Subregister 20 of Multireg err_code + // R[err_code_20]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_20 ( + .re (err_code_20_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[20].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_20_qs) + ); + + + // Subregister 21 of Multireg err_code + // R[err_code_21]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_21 ( + .re (err_code_21_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[21].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_21_qs) + ); + + + // Subregister 22 of Multireg err_code + // R[err_code_22]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_22 ( + .re (err_code_22_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[22].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_22_qs) + ); + + + // Subregister 23 of Multireg err_code + // R[err_code_23]: V(True) + prim_subreg_ext #( + .DW (3) + ) u_err_code_23 ( + .re (err_code_23_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.err_code[23].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (err_code_23_qs) + ); + + + // R[direct_access_regwen]: V(True) + logic direct_access_regwen_qe; + logic [0:0] direct_access_regwen_flds_we; + assign direct_access_regwen_qe = &direct_access_regwen_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_direct_access_regwen ( + .re (direct_access_regwen_re), + .we (direct_access_regwen_we), + .wd (direct_access_regwen_wd), + .d (hw2reg.direct_access_regwen.d), + .qre (), + .qe (direct_access_regwen_flds_we[0]), + .q (reg2hw.direct_access_regwen.q), + .ds (), + .qs (direct_access_regwen_qs) + ); + assign reg2hw.direct_access_regwen.qe = direct_access_regwen_qe; + + + // R[direct_access_cmd]: V(True) + logic direct_access_cmd_qe; + logic [2:0] direct_access_cmd_flds_we; + assign direct_access_cmd_qe = &direct_access_cmd_flds_we; + // Create REGWEN-gated WE signal + logic direct_access_cmd_gated_we; + assign direct_access_cmd_gated_we = direct_access_cmd_we & direct_access_regwen_qs; + // F[rd]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_direct_access_cmd_rd ( + .re (1'b0), + .we (direct_access_cmd_gated_we), + .wd (direct_access_cmd_rd_wd), + .d ('0), + .qre (), + .qe (direct_access_cmd_flds_we[0]), + .q (reg2hw.direct_access_cmd.rd.q), + .ds (), + .qs () + ); + assign reg2hw.direct_access_cmd.rd.qe = direct_access_cmd_qe; + + // F[wr]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_direct_access_cmd_wr ( + .re (1'b0), + .we (direct_access_cmd_gated_we), + .wd (direct_access_cmd_wr_wd), + .d ('0), + .qre (), + .qe (direct_access_cmd_flds_we[1]), + .q (reg2hw.direct_access_cmd.wr.q), + .ds (), + .qs () + ); + assign reg2hw.direct_access_cmd.wr.qe = direct_access_cmd_qe; + + // F[digest]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_direct_access_cmd_digest ( + .re (1'b0), + .we (direct_access_cmd_gated_we), + .wd (direct_access_cmd_digest_wd), + .d ('0), + .qre (), + .qe (direct_access_cmd_flds_we[2]), + .q (reg2hw.direct_access_cmd.digest.q), + .ds (), + .qs () + ); + assign reg2hw.direct_access_cmd.digest.qe = direct_access_cmd_qe; + + + // R[direct_access_address]: V(False) + // Create REGWEN-gated WE signal + logic direct_access_address_gated_we; + assign direct_access_address_gated_we = direct_access_address_we & direct_access_regwen_qs; + prim_subreg #( + .DW (14), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (14'h0), + .Mubi (1'b0) + ) u_direct_access_address ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (direct_access_address_gated_we), + .wd (direct_access_address_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.direct_access_address.q), + .ds (), + + // to register interface (read) + .qs (direct_access_address_qs) + ); + + + // Subregister 0 of Multireg direct_access_wdata + // R[direct_access_wdata_0]: V(False) + // Create REGWEN-gated WE signal + logic direct_access_wdata_0_gated_we; + assign direct_access_wdata_0_gated_we = direct_access_wdata_0_we & direct_access_regwen_qs; + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_direct_access_wdata_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (direct_access_wdata_0_gated_we), + .wd (direct_access_wdata_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.direct_access_wdata[0].q), + .ds (), + + // to register interface (read) + .qs (direct_access_wdata_0_qs) + ); + + + // Subregister 1 of Multireg direct_access_wdata + // R[direct_access_wdata_1]: V(False) + // Create REGWEN-gated WE signal + logic direct_access_wdata_1_gated_we; + assign direct_access_wdata_1_gated_we = direct_access_wdata_1_we & direct_access_regwen_qs; + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_direct_access_wdata_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (direct_access_wdata_1_gated_we), + .wd (direct_access_wdata_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.direct_access_wdata[1].q), + .ds (), + + // to register interface (read) + .qs (direct_access_wdata_1_qs) + ); + + + // Subregister 0 of Multireg direct_access_rdata + // R[direct_access_rdata_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_direct_access_rdata_0 ( + .re (direct_access_rdata_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.direct_access_rdata[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (direct_access_rdata_0_qs) + ); + + + // Subregister 1 of Multireg direct_access_rdata + // R[direct_access_rdata_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_direct_access_rdata_1 ( + .re (direct_access_rdata_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.direct_access_rdata[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (direct_access_rdata_1_qs) + ); + + + // R[check_trigger_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_check_trigger_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (check_trigger_regwen_we), + .wd (check_trigger_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (check_trigger_regwen_qs) + ); + + + // R[check_trigger]: V(True) + logic check_trigger_qe; + logic [1:0] check_trigger_flds_we; + assign check_trigger_qe = &check_trigger_flds_we; + // Create REGWEN-gated WE signal + logic check_trigger_gated_we; + assign check_trigger_gated_we = check_trigger_we & check_trigger_regwen_qs; + // F[integrity]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_check_trigger_integrity ( + .re (1'b0), + .we (check_trigger_gated_we), + .wd (check_trigger_integrity_wd), + .d ('0), + .qre (), + .qe (check_trigger_flds_we[0]), + .q (reg2hw.check_trigger.integrity.q), + .ds (), + .qs () + ); + assign reg2hw.check_trigger.integrity.qe = check_trigger_qe; + + // F[consistency]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_check_trigger_consistency ( + .re (1'b0), + .we (check_trigger_gated_we), + .wd (check_trigger_consistency_wd), + .d ('0), + .qre (), + .qe (check_trigger_flds_we[1]), + .q (reg2hw.check_trigger.consistency.q), + .ds (), + .qs () + ); + assign reg2hw.check_trigger.consistency.qe = check_trigger_qe; + + + // R[check_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_check_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (check_regwen_we), + .wd (check_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (check_regwen_qs) + ); + + + // R[check_timeout]: V(False) + // Create REGWEN-gated WE signal + logic check_timeout_gated_we; + assign check_timeout_gated_we = check_timeout_we & check_regwen_qs; + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_check_timeout ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (check_timeout_gated_we), + .wd (check_timeout_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.check_timeout.q), + .ds (), + + // to register interface (read) + .qs (check_timeout_qs) + ); + + + // R[integrity_check_period]: V(False) + // Create REGWEN-gated WE signal + logic integrity_check_period_gated_we; + assign integrity_check_period_gated_we = integrity_check_period_we & check_regwen_qs; + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_integrity_check_period ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (integrity_check_period_gated_we), + .wd (integrity_check_period_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.integrity_check_period.q), + .ds (), + + // to register interface (read) + .qs (integrity_check_period_qs) + ); + + + // R[consistency_check_period]: V(False) + // Create REGWEN-gated WE signal + logic consistency_check_period_gated_we; + assign consistency_check_period_gated_we = consistency_check_period_we & check_regwen_qs; + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_consistency_check_period ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (consistency_check_period_gated_we), + .wd (consistency_check_period_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.consistency_check_period.q), + .ds (), + + // to register interface (read) + .qs (consistency_check_period_qs) + ); + + + // R[vendor_test_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic vendor_test_read_lock_gated_we; + assign vendor_test_read_lock_gated_we = vendor_test_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_vendor_test_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (vendor_test_read_lock_gated_we), + .wd (vendor_test_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.vendor_test_read_lock.q), + .ds (), + + // to register interface (read) + .qs (vendor_test_read_lock_qs) + ); + + + // R[creator_sw_cfg_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic creator_sw_cfg_read_lock_gated_we; + assign creator_sw_cfg_read_lock_gated_we = creator_sw_cfg_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_creator_sw_cfg_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (creator_sw_cfg_read_lock_gated_we), + .wd (creator_sw_cfg_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.creator_sw_cfg_read_lock.q), + .ds (), + + // to register interface (read) + .qs (creator_sw_cfg_read_lock_qs) + ); + + + // R[owner_sw_cfg_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic owner_sw_cfg_read_lock_gated_we; + assign owner_sw_cfg_read_lock_gated_we = owner_sw_cfg_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_owner_sw_cfg_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (owner_sw_cfg_read_lock_gated_we), + .wd (owner_sw_cfg_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.owner_sw_cfg_read_lock.q), + .ds (), + + // to register interface (read) + .qs (owner_sw_cfg_read_lock_qs) + ); + + + // R[ownership_slot_state_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic ownership_slot_state_read_lock_gated_we; + assign ownership_slot_state_read_lock_gated_we = + ownership_slot_state_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_ownership_slot_state_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ownership_slot_state_read_lock_gated_we), + .wd (ownership_slot_state_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ownership_slot_state_read_lock.q), + .ds (), + + // to register interface (read) + .qs (ownership_slot_state_read_lock_qs) + ); + + + // R[rot_creator_auth_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic rot_creator_auth_read_lock_gated_we; + assign rot_creator_auth_read_lock_gated_we = + rot_creator_auth_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_rot_creator_auth_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rot_creator_auth_read_lock_gated_we), + .wd (rot_creator_auth_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rot_creator_auth_read_lock.q), + .ds (), + + // to register interface (read) + .qs (rot_creator_auth_read_lock_qs) + ); + + + // R[rot_owner_auth_slot0_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic rot_owner_auth_slot0_read_lock_gated_we; + assign rot_owner_auth_slot0_read_lock_gated_we = + rot_owner_auth_slot0_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_rot_owner_auth_slot0_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rot_owner_auth_slot0_read_lock_gated_we), + .wd (rot_owner_auth_slot0_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rot_owner_auth_slot0_read_lock.q), + .ds (), + + // to register interface (read) + .qs (rot_owner_auth_slot0_read_lock_qs) + ); + + + // R[rot_owner_auth_slot1_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic rot_owner_auth_slot1_read_lock_gated_we; + assign rot_owner_auth_slot1_read_lock_gated_we = + rot_owner_auth_slot1_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_rot_owner_auth_slot1_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rot_owner_auth_slot1_read_lock_gated_we), + .wd (rot_owner_auth_slot1_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rot_owner_auth_slot1_read_lock.q), + .ds (), + + // to register interface (read) + .qs (rot_owner_auth_slot1_read_lock_qs) + ); + + + // R[plat_integ_auth_slot0_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic plat_integ_auth_slot0_read_lock_gated_we; + assign plat_integ_auth_slot0_read_lock_gated_we = + plat_integ_auth_slot0_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_plat_integ_auth_slot0_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (plat_integ_auth_slot0_read_lock_gated_we), + .wd (plat_integ_auth_slot0_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.plat_integ_auth_slot0_read_lock.q), + .ds (), + + // to register interface (read) + .qs (plat_integ_auth_slot0_read_lock_qs) + ); + + + // R[plat_integ_auth_slot1_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic plat_integ_auth_slot1_read_lock_gated_we; + assign plat_integ_auth_slot1_read_lock_gated_we = + plat_integ_auth_slot1_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_plat_integ_auth_slot1_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (plat_integ_auth_slot1_read_lock_gated_we), + .wd (plat_integ_auth_slot1_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.plat_integ_auth_slot1_read_lock.q), + .ds (), + + // to register interface (read) + .qs (plat_integ_auth_slot1_read_lock_qs) + ); + + + // R[plat_owner_auth_slot0_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic plat_owner_auth_slot0_read_lock_gated_we; + assign plat_owner_auth_slot0_read_lock_gated_we = + plat_owner_auth_slot0_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_plat_owner_auth_slot0_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (plat_owner_auth_slot0_read_lock_gated_we), + .wd (plat_owner_auth_slot0_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.plat_owner_auth_slot0_read_lock.q), + .ds (), + + // to register interface (read) + .qs (plat_owner_auth_slot0_read_lock_qs) + ); + + + // R[plat_owner_auth_slot1_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic plat_owner_auth_slot1_read_lock_gated_we; + assign plat_owner_auth_slot1_read_lock_gated_we = + plat_owner_auth_slot1_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_plat_owner_auth_slot1_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (plat_owner_auth_slot1_read_lock_gated_we), + .wd (plat_owner_auth_slot1_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.plat_owner_auth_slot1_read_lock.q), + .ds (), + + // to register interface (read) + .qs (plat_owner_auth_slot1_read_lock_qs) + ); + + + // R[plat_owner_auth_slot2_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic plat_owner_auth_slot2_read_lock_gated_we; + assign plat_owner_auth_slot2_read_lock_gated_we = + plat_owner_auth_slot2_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_plat_owner_auth_slot2_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (plat_owner_auth_slot2_read_lock_gated_we), + .wd (plat_owner_auth_slot2_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.plat_owner_auth_slot2_read_lock.q), + .ds (), + + // to register interface (read) + .qs (plat_owner_auth_slot2_read_lock_qs) + ); + + + // R[plat_owner_auth_slot3_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic plat_owner_auth_slot3_read_lock_gated_we; + assign plat_owner_auth_slot3_read_lock_gated_we = + plat_owner_auth_slot3_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_plat_owner_auth_slot3_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (plat_owner_auth_slot3_read_lock_gated_we), + .wd (plat_owner_auth_slot3_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.plat_owner_auth_slot3_read_lock.q), + .ds (), + + // to register interface (read) + .qs (plat_owner_auth_slot3_read_lock_qs) + ); + + + // R[ext_nvm_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic ext_nvm_read_lock_gated_we; + assign ext_nvm_read_lock_gated_we = ext_nvm_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_ext_nvm_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ext_nvm_read_lock_gated_we), + .wd (ext_nvm_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ext_nvm_read_lock.q), + .ds (), + + // to register interface (read) + .qs (ext_nvm_read_lock_qs) + ); + + + // R[rom_patch_read_lock]: V(False) + // Create REGWEN-gated WE signal + logic rom_patch_read_lock_gated_we; + assign rom_patch_read_lock_gated_we = rom_patch_read_lock_we & direct_access_regwen_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_rom_patch_read_lock ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (rom_patch_read_lock_gated_we), + .wd (rom_patch_read_lock_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.rom_patch_read_lock.q), + .ds (), + + // to register interface (read) + .qs (rom_patch_read_lock_qs) + ); + + + // Subregister 0 of Multireg vendor_test_digest + // R[vendor_test_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_vendor_test_digest_0 ( + .re (vendor_test_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.vendor_test_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (vendor_test_digest_0_qs) + ); + + + // Subregister 1 of Multireg vendor_test_digest + // R[vendor_test_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_vendor_test_digest_1 ( + .re (vendor_test_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.vendor_test_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (vendor_test_digest_1_qs) + ); + + + // Subregister 0 of Multireg creator_sw_cfg_digest + // R[creator_sw_cfg_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_creator_sw_cfg_digest_0 ( + .re (creator_sw_cfg_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.creator_sw_cfg_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (creator_sw_cfg_digest_0_qs) + ); + + + // Subregister 1 of Multireg creator_sw_cfg_digest + // R[creator_sw_cfg_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_creator_sw_cfg_digest_1 ( + .re (creator_sw_cfg_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.creator_sw_cfg_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (creator_sw_cfg_digest_1_qs) + ); + + + // Subregister 0 of Multireg owner_sw_cfg_digest + // R[owner_sw_cfg_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_owner_sw_cfg_digest_0 ( + .re (owner_sw_cfg_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.owner_sw_cfg_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (owner_sw_cfg_digest_0_qs) + ); + + + // Subregister 1 of Multireg owner_sw_cfg_digest + // R[owner_sw_cfg_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_owner_sw_cfg_digest_1 ( + .re (owner_sw_cfg_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.owner_sw_cfg_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (owner_sw_cfg_digest_1_qs) + ); + + + // Subregister 0 of Multireg rot_creator_auth_digest + // R[rot_creator_auth_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_rot_creator_auth_digest_0 ( + .re (rot_creator_auth_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_creator_auth_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_creator_auth_digest_0_qs) + ); + + + // Subregister 1 of Multireg rot_creator_auth_digest + // R[rot_creator_auth_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_rot_creator_auth_digest_1 ( + .re (rot_creator_auth_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_creator_auth_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_creator_auth_digest_1_qs) + ); + + + // Subregister 0 of Multireg rot_owner_auth_slot0_digest + // R[rot_owner_auth_slot0_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_rot_owner_auth_slot0_digest_0 ( + .re (rot_owner_auth_slot0_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_owner_auth_slot0_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_owner_auth_slot0_digest_0_qs) + ); + + + // Subregister 1 of Multireg rot_owner_auth_slot0_digest + // R[rot_owner_auth_slot0_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_rot_owner_auth_slot0_digest_1 ( + .re (rot_owner_auth_slot0_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_owner_auth_slot0_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_owner_auth_slot0_digest_1_qs) + ); + + + // Subregister 0 of Multireg rot_owner_auth_slot1_digest + // R[rot_owner_auth_slot1_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_rot_owner_auth_slot1_digest_0 ( + .re (rot_owner_auth_slot1_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_owner_auth_slot1_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_owner_auth_slot1_digest_0_qs) + ); + + + // Subregister 1 of Multireg rot_owner_auth_slot1_digest + // R[rot_owner_auth_slot1_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_rot_owner_auth_slot1_digest_1 ( + .re (rot_owner_auth_slot1_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rot_owner_auth_slot1_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rot_owner_auth_slot1_digest_1_qs) + ); + + + // Subregister 0 of Multireg plat_integ_auth_slot0_digest + // R[plat_integ_auth_slot0_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_integ_auth_slot0_digest_0 ( + .re (plat_integ_auth_slot0_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_integ_auth_slot0_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_integ_auth_slot0_digest_0_qs) + ); + + + // Subregister 1 of Multireg plat_integ_auth_slot0_digest + // R[plat_integ_auth_slot0_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_integ_auth_slot0_digest_1 ( + .re (plat_integ_auth_slot0_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_integ_auth_slot0_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_integ_auth_slot0_digest_1_qs) + ); + + + // Subregister 0 of Multireg plat_integ_auth_slot1_digest + // R[plat_integ_auth_slot1_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_integ_auth_slot1_digest_0 ( + .re (plat_integ_auth_slot1_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_integ_auth_slot1_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_integ_auth_slot1_digest_0_qs) + ); + + + // Subregister 1 of Multireg plat_integ_auth_slot1_digest + // R[plat_integ_auth_slot1_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_integ_auth_slot1_digest_1 ( + .re (plat_integ_auth_slot1_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_integ_auth_slot1_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_integ_auth_slot1_digest_1_qs) + ); + + + // Subregister 0 of Multireg plat_owner_auth_slot0_digest + // R[plat_owner_auth_slot0_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_owner_auth_slot0_digest_0 ( + .re (plat_owner_auth_slot0_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_owner_auth_slot0_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_owner_auth_slot0_digest_0_qs) + ); + + + // Subregister 1 of Multireg plat_owner_auth_slot0_digest + // R[plat_owner_auth_slot0_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_owner_auth_slot0_digest_1 ( + .re (plat_owner_auth_slot0_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_owner_auth_slot0_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_owner_auth_slot0_digest_1_qs) + ); + + + // Subregister 0 of Multireg plat_owner_auth_slot1_digest + // R[plat_owner_auth_slot1_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_owner_auth_slot1_digest_0 ( + .re (plat_owner_auth_slot1_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_owner_auth_slot1_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_owner_auth_slot1_digest_0_qs) + ); + + + // Subregister 1 of Multireg plat_owner_auth_slot1_digest + // R[plat_owner_auth_slot1_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_owner_auth_slot1_digest_1 ( + .re (plat_owner_auth_slot1_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_owner_auth_slot1_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_owner_auth_slot1_digest_1_qs) + ); + + + // Subregister 0 of Multireg plat_owner_auth_slot2_digest + // R[plat_owner_auth_slot2_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_owner_auth_slot2_digest_0 ( + .re (plat_owner_auth_slot2_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_owner_auth_slot2_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_owner_auth_slot2_digest_0_qs) + ); + + + // Subregister 1 of Multireg plat_owner_auth_slot2_digest + // R[plat_owner_auth_slot2_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_owner_auth_slot2_digest_1 ( + .re (plat_owner_auth_slot2_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_owner_auth_slot2_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_owner_auth_slot2_digest_1_qs) + ); + + + // Subregister 0 of Multireg plat_owner_auth_slot3_digest + // R[plat_owner_auth_slot3_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_owner_auth_slot3_digest_0 ( + .re (plat_owner_auth_slot3_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_owner_auth_slot3_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_owner_auth_slot3_digest_0_qs) + ); + + + // Subregister 1 of Multireg plat_owner_auth_slot3_digest + // R[plat_owner_auth_slot3_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_plat_owner_auth_slot3_digest_1 ( + .re (plat_owner_auth_slot3_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.plat_owner_auth_slot3_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (plat_owner_auth_slot3_digest_1_qs) + ); + + + // Subregister 0 of Multireg rom_patch_digest + // R[rom_patch_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_rom_patch_digest_0 ( + .re (rom_patch_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rom_patch_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rom_patch_digest_0_qs) + ); + + + // Subregister 1 of Multireg rom_patch_digest + // R[rom_patch_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_rom_patch_digest_1 ( + .re (rom_patch_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.rom_patch_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (rom_patch_digest_1_qs) + ); + + + // Subregister 0 of Multireg hw_cfg0_digest + // R[hw_cfg0_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_hw_cfg0_digest_0 ( + .re (hw_cfg0_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_cfg0_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_cfg0_digest_0_qs) + ); + + + // Subregister 1 of Multireg hw_cfg0_digest + // R[hw_cfg0_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_hw_cfg0_digest_1 ( + .re (hw_cfg0_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_cfg0_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_cfg0_digest_1_qs) + ); + + + // Subregister 0 of Multireg hw_cfg1_digest + // R[hw_cfg1_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_hw_cfg1_digest_0 ( + .re (hw_cfg1_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_cfg1_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_cfg1_digest_0_qs) + ); + + + // Subregister 1 of Multireg hw_cfg1_digest + // R[hw_cfg1_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_hw_cfg1_digest_1 ( + .re (hw_cfg1_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.hw_cfg1_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (hw_cfg1_digest_1_qs) + ); + + + // Subregister 0 of Multireg secret0_digest + // R[secret0_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_secret0_digest_0 ( + .re (secret0_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret0_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret0_digest_0_qs) + ); + + + // Subregister 1 of Multireg secret0_digest + // R[secret0_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_secret0_digest_1 ( + .re (secret0_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret0_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret0_digest_1_qs) + ); + + + // Subregister 0 of Multireg secret1_digest + // R[secret1_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_secret1_digest_0 ( + .re (secret1_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret1_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret1_digest_0_qs) + ); + + + // Subregister 1 of Multireg secret1_digest + // R[secret1_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_secret1_digest_1 ( + .re (secret1_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret1_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret1_digest_1_qs) + ); + + + // Subregister 0 of Multireg secret2_digest + // R[secret2_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_secret2_digest_0 ( + .re (secret2_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret2_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret2_digest_0_qs) + ); + + + // Subregister 1 of Multireg secret2_digest + // R[secret2_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_secret2_digest_1 ( + .re (secret2_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret2_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret2_digest_1_qs) + ); + + + // Subregister 0 of Multireg secret3_digest + // R[secret3_digest_0]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_secret3_digest_0 ( + .re (secret3_digest_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret3_digest[0].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret3_digest_0_qs) + ); + + + // Subregister 1 of Multireg secret3_digest + // R[secret3_digest_1]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_secret3_digest_1 ( + .re (secret3_digest_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.secret3_digest[1].d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (secret3_digest_1_qs) + ); + + + + logic [94:0] addr_hit; + always_comb begin + addr_hit[ 0] = (reg_addr == OTP_CTRL_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == OTP_CTRL_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == OTP_CTRL_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == OTP_CTRL_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == OTP_CTRL_STATUS_OFFSET); + addr_hit[ 5] = (reg_addr == OTP_CTRL_ERR_CODE_0_OFFSET); + addr_hit[ 6] = (reg_addr == OTP_CTRL_ERR_CODE_1_OFFSET); + addr_hit[ 7] = (reg_addr == OTP_CTRL_ERR_CODE_2_OFFSET); + addr_hit[ 8] = (reg_addr == OTP_CTRL_ERR_CODE_3_OFFSET); + addr_hit[ 9] = (reg_addr == OTP_CTRL_ERR_CODE_4_OFFSET); + addr_hit[10] = (reg_addr == OTP_CTRL_ERR_CODE_5_OFFSET); + addr_hit[11] = (reg_addr == OTP_CTRL_ERR_CODE_6_OFFSET); + addr_hit[12] = (reg_addr == OTP_CTRL_ERR_CODE_7_OFFSET); + addr_hit[13] = (reg_addr == OTP_CTRL_ERR_CODE_8_OFFSET); + addr_hit[14] = (reg_addr == OTP_CTRL_ERR_CODE_9_OFFSET); + addr_hit[15] = (reg_addr == OTP_CTRL_ERR_CODE_10_OFFSET); + addr_hit[16] = (reg_addr == OTP_CTRL_ERR_CODE_11_OFFSET); + addr_hit[17] = (reg_addr == OTP_CTRL_ERR_CODE_12_OFFSET); + addr_hit[18] = (reg_addr == OTP_CTRL_ERR_CODE_13_OFFSET); + addr_hit[19] = (reg_addr == OTP_CTRL_ERR_CODE_14_OFFSET); + addr_hit[20] = (reg_addr == OTP_CTRL_ERR_CODE_15_OFFSET); + addr_hit[21] = (reg_addr == OTP_CTRL_ERR_CODE_16_OFFSET); + addr_hit[22] = (reg_addr == OTP_CTRL_ERR_CODE_17_OFFSET); + addr_hit[23] = (reg_addr == OTP_CTRL_ERR_CODE_18_OFFSET); + addr_hit[24] = (reg_addr == OTP_CTRL_ERR_CODE_19_OFFSET); + addr_hit[25] = (reg_addr == OTP_CTRL_ERR_CODE_20_OFFSET); + addr_hit[26] = (reg_addr == OTP_CTRL_ERR_CODE_21_OFFSET); + addr_hit[27] = (reg_addr == OTP_CTRL_ERR_CODE_22_OFFSET); + addr_hit[28] = (reg_addr == OTP_CTRL_ERR_CODE_23_OFFSET); + addr_hit[29] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET); + addr_hit[30] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET); + addr_hit[31] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET); + addr_hit[32] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET); + addr_hit[33] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET); + addr_hit[34] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET); + addr_hit[35] = (reg_addr == OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET); + addr_hit[36] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET); + addr_hit[37] = (reg_addr == OTP_CTRL_CHECK_TRIGGER_OFFSET); + addr_hit[38] = (reg_addr == OTP_CTRL_CHECK_REGWEN_OFFSET); + addr_hit[39] = (reg_addr == OTP_CTRL_CHECK_TIMEOUT_OFFSET); + addr_hit[40] = (reg_addr == OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET); + addr_hit[41] = (reg_addr == OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET); + addr_hit[42] = (reg_addr == OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET); + addr_hit[43] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET); + addr_hit[44] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET); + addr_hit[45] = (reg_addr == OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_OFFSET); + addr_hit[46] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_OFFSET); + addr_hit[47] = (reg_addr == OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_OFFSET); + addr_hit[48] = (reg_addr == OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_OFFSET); + addr_hit[49] = (reg_addr == OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_OFFSET); + addr_hit[50] = (reg_addr == OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_OFFSET); + addr_hit[51] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_OFFSET); + addr_hit[52] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_OFFSET); + addr_hit[53] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_OFFSET); + addr_hit[54] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_OFFSET); + addr_hit[55] = (reg_addr == OTP_CTRL_EXT_NVM_READ_LOCK_OFFSET); + addr_hit[56] = (reg_addr == OTP_CTRL_ROM_PATCH_READ_LOCK_OFFSET); + addr_hit[57] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET); + addr_hit[58] = (reg_addr == OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET); + addr_hit[59] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET); + addr_hit[60] = (reg_addr == OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET); + addr_hit[61] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET); + addr_hit[62] = (reg_addr == OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET); + addr_hit[63] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_OFFSET); + addr_hit[64] = (reg_addr == OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_OFFSET); + addr_hit[65] = (reg_addr == OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_OFFSET); + addr_hit[66] = (reg_addr == OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_OFFSET); + addr_hit[67] = (reg_addr == OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_OFFSET); + addr_hit[68] = (reg_addr == OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_OFFSET); + addr_hit[69] = (reg_addr == OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_OFFSET); + addr_hit[70] = (reg_addr == OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_OFFSET); + addr_hit[71] = (reg_addr == OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_OFFSET); + addr_hit[72] = (reg_addr == OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_OFFSET); + addr_hit[73] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_OFFSET); + addr_hit[74] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_OFFSET); + addr_hit[75] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_OFFSET); + addr_hit[76] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_OFFSET); + addr_hit[77] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_OFFSET); + addr_hit[78] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_OFFSET); + addr_hit[79] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_OFFSET); + addr_hit[80] = (reg_addr == OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_OFFSET); + addr_hit[81] = (reg_addr == OTP_CTRL_ROM_PATCH_DIGEST_0_OFFSET); + addr_hit[82] = (reg_addr == OTP_CTRL_ROM_PATCH_DIGEST_1_OFFSET); + addr_hit[83] = (reg_addr == OTP_CTRL_HW_CFG0_DIGEST_0_OFFSET); + addr_hit[84] = (reg_addr == OTP_CTRL_HW_CFG0_DIGEST_1_OFFSET); + addr_hit[85] = (reg_addr == OTP_CTRL_HW_CFG1_DIGEST_0_OFFSET); + addr_hit[86] = (reg_addr == OTP_CTRL_HW_CFG1_DIGEST_1_OFFSET); + addr_hit[87] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_0_OFFSET); + addr_hit[88] = (reg_addr == OTP_CTRL_SECRET0_DIGEST_1_OFFSET); + addr_hit[89] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_0_OFFSET); + addr_hit[90] = (reg_addr == OTP_CTRL_SECRET1_DIGEST_1_OFFSET); + addr_hit[91] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_0_OFFSET); + addr_hit[92] = (reg_addr == OTP_CTRL_SECRET2_DIGEST_1_OFFSET); + addr_hit[93] = (reg_addr == OTP_CTRL_SECRET3_DIGEST_0_OFFSET); + addr_hit[94] = (reg_addr == OTP_CTRL_SECRET3_DIGEST_1_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(OTP_CTRL_CORE_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(OTP_CTRL_CORE_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(OTP_CTRL_CORE_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(OTP_CTRL_CORE_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(OTP_CTRL_CORE_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(OTP_CTRL_CORE_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(OTP_CTRL_CORE_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(OTP_CTRL_CORE_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(OTP_CTRL_CORE_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(OTP_CTRL_CORE_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(OTP_CTRL_CORE_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(OTP_CTRL_CORE_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(OTP_CTRL_CORE_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(OTP_CTRL_CORE_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(OTP_CTRL_CORE_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(OTP_CTRL_CORE_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(OTP_CTRL_CORE_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(OTP_CTRL_CORE_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(OTP_CTRL_CORE_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(OTP_CTRL_CORE_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(OTP_CTRL_CORE_PERMIT[20] & ~reg_be))) | + (addr_hit[21] & (|(OTP_CTRL_CORE_PERMIT[21] & ~reg_be))) | + (addr_hit[22] & (|(OTP_CTRL_CORE_PERMIT[22] & ~reg_be))) | + (addr_hit[23] & (|(OTP_CTRL_CORE_PERMIT[23] & ~reg_be))) | + (addr_hit[24] & (|(OTP_CTRL_CORE_PERMIT[24] & ~reg_be))) | + (addr_hit[25] & (|(OTP_CTRL_CORE_PERMIT[25] & ~reg_be))) | + (addr_hit[26] & (|(OTP_CTRL_CORE_PERMIT[26] & ~reg_be))) | + (addr_hit[27] & (|(OTP_CTRL_CORE_PERMIT[27] & ~reg_be))) | + (addr_hit[28] & (|(OTP_CTRL_CORE_PERMIT[28] & ~reg_be))) | + (addr_hit[29] & (|(OTP_CTRL_CORE_PERMIT[29] & ~reg_be))) | + (addr_hit[30] & (|(OTP_CTRL_CORE_PERMIT[30] & ~reg_be))) | + (addr_hit[31] & (|(OTP_CTRL_CORE_PERMIT[31] & ~reg_be))) | + (addr_hit[32] & (|(OTP_CTRL_CORE_PERMIT[32] & ~reg_be))) | + (addr_hit[33] & (|(OTP_CTRL_CORE_PERMIT[33] & ~reg_be))) | + (addr_hit[34] & (|(OTP_CTRL_CORE_PERMIT[34] & ~reg_be))) | + (addr_hit[35] & (|(OTP_CTRL_CORE_PERMIT[35] & ~reg_be))) | + (addr_hit[36] & (|(OTP_CTRL_CORE_PERMIT[36] & ~reg_be))) | + (addr_hit[37] & (|(OTP_CTRL_CORE_PERMIT[37] & ~reg_be))) | + (addr_hit[38] & (|(OTP_CTRL_CORE_PERMIT[38] & ~reg_be))) | + (addr_hit[39] & (|(OTP_CTRL_CORE_PERMIT[39] & ~reg_be))) | + (addr_hit[40] & (|(OTP_CTRL_CORE_PERMIT[40] & ~reg_be))) | + (addr_hit[41] & (|(OTP_CTRL_CORE_PERMIT[41] & ~reg_be))) | + (addr_hit[42] & (|(OTP_CTRL_CORE_PERMIT[42] & ~reg_be))) | + (addr_hit[43] & (|(OTP_CTRL_CORE_PERMIT[43] & ~reg_be))) | + (addr_hit[44] & (|(OTP_CTRL_CORE_PERMIT[44] & ~reg_be))) | + (addr_hit[45] & (|(OTP_CTRL_CORE_PERMIT[45] & ~reg_be))) | + (addr_hit[46] & (|(OTP_CTRL_CORE_PERMIT[46] & ~reg_be))) | + (addr_hit[47] & (|(OTP_CTRL_CORE_PERMIT[47] & ~reg_be))) | + (addr_hit[48] & (|(OTP_CTRL_CORE_PERMIT[48] & ~reg_be))) | + (addr_hit[49] & (|(OTP_CTRL_CORE_PERMIT[49] & ~reg_be))) | + (addr_hit[50] & (|(OTP_CTRL_CORE_PERMIT[50] & ~reg_be))) | + (addr_hit[51] & (|(OTP_CTRL_CORE_PERMIT[51] & ~reg_be))) | + (addr_hit[52] & (|(OTP_CTRL_CORE_PERMIT[52] & ~reg_be))) | + (addr_hit[53] & (|(OTP_CTRL_CORE_PERMIT[53] & ~reg_be))) | + (addr_hit[54] & (|(OTP_CTRL_CORE_PERMIT[54] & ~reg_be))) | + (addr_hit[55] & (|(OTP_CTRL_CORE_PERMIT[55] & ~reg_be))) | + (addr_hit[56] & (|(OTP_CTRL_CORE_PERMIT[56] & ~reg_be))) | + (addr_hit[57] & (|(OTP_CTRL_CORE_PERMIT[57] & ~reg_be))) | + (addr_hit[58] & (|(OTP_CTRL_CORE_PERMIT[58] & ~reg_be))) | + (addr_hit[59] & (|(OTP_CTRL_CORE_PERMIT[59] & ~reg_be))) | + (addr_hit[60] & (|(OTP_CTRL_CORE_PERMIT[60] & ~reg_be))) | + (addr_hit[61] & (|(OTP_CTRL_CORE_PERMIT[61] & ~reg_be))) | + (addr_hit[62] & (|(OTP_CTRL_CORE_PERMIT[62] & ~reg_be))) | + (addr_hit[63] & (|(OTP_CTRL_CORE_PERMIT[63] & ~reg_be))) | + (addr_hit[64] & (|(OTP_CTRL_CORE_PERMIT[64] & ~reg_be))) | + (addr_hit[65] & (|(OTP_CTRL_CORE_PERMIT[65] & ~reg_be))) | + (addr_hit[66] & (|(OTP_CTRL_CORE_PERMIT[66] & ~reg_be))) | + (addr_hit[67] & (|(OTP_CTRL_CORE_PERMIT[67] & ~reg_be))) | + (addr_hit[68] & (|(OTP_CTRL_CORE_PERMIT[68] & ~reg_be))) | + (addr_hit[69] & (|(OTP_CTRL_CORE_PERMIT[69] & ~reg_be))) | + (addr_hit[70] & (|(OTP_CTRL_CORE_PERMIT[70] & ~reg_be))) | + (addr_hit[71] & (|(OTP_CTRL_CORE_PERMIT[71] & ~reg_be))) | + (addr_hit[72] & (|(OTP_CTRL_CORE_PERMIT[72] & ~reg_be))) | + (addr_hit[73] & (|(OTP_CTRL_CORE_PERMIT[73] & ~reg_be))) | + (addr_hit[74] & (|(OTP_CTRL_CORE_PERMIT[74] & ~reg_be))) | + (addr_hit[75] & (|(OTP_CTRL_CORE_PERMIT[75] & ~reg_be))) | + (addr_hit[76] & (|(OTP_CTRL_CORE_PERMIT[76] & ~reg_be))) | + (addr_hit[77] & (|(OTP_CTRL_CORE_PERMIT[77] & ~reg_be))) | + (addr_hit[78] & (|(OTP_CTRL_CORE_PERMIT[78] & ~reg_be))) | + (addr_hit[79] & (|(OTP_CTRL_CORE_PERMIT[79] & ~reg_be))) | + (addr_hit[80] & (|(OTP_CTRL_CORE_PERMIT[80] & ~reg_be))) | + (addr_hit[81] & (|(OTP_CTRL_CORE_PERMIT[81] & ~reg_be))) | + (addr_hit[82] & (|(OTP_CTRL_CORE_PERMIT[82] & ~reg_be))) | + (addr_hit[83] & (|(OTP_CTRL_CORE_PERMIT[83] & ~reg_be))) | + (addr_hit[84] & (|(OTP_CTRL_CORE_PERMIT[84] & ~reg_be))) | + (addr_hit[85] & (|(OTP_CTRL_CORE_PERMIT[85] & ~reg_be))) | + (addr_hit[86] & (|(OTP_CTRL_CORE_PERMIT[86] & ~reg_be))) | + (addr_hit[87] & (|(OTP_CTRL_CORE_PERMIT[87] & ~reg_be))) | + (addr_hit[88] & (|(OTP_CTRL_CORE_PERMIT[88] & ~reg_be))) | + (addr_hit[89] & (|(OTP_CTRL_CORE_PERMIT[89] & ~reg_be))) | + (addr_hit[90] & (|(OTP_CTRL_CORE_PERMIT[90] & ~reg_be))) | + (addr_hit[91] & (|(OTP_CTRL_CORE_PERMIT[91] & ~reg_be))) | + (addr_hit[92] & (|(OTP_CTRL_CORE_PERMIT[92] & ~reg_be))) | + (addr_hit[93] & (|(OTP_CTRL_CORE_PERMIT[93] & ~reg_be))) | + (addr_hit[94] & (|(OTP_CTRL_CORE_PERMIT[94] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = addr_hit[0] & reg_we & !reg_error; + + assign intr_state_otp_operation_done_wd = reg_wdata[0]; + + assign intr_state_otp_error_wd = reg_wdata[1]; + assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; + + assign intr_enable_otp_operation_done_wd = reg_wdata[0]; + + assign intr_enable_otp_error_wd = reg_wdata[1]; + assign intr_test_we = addr_hit[2] & reg_we & !reg_error; + + assign intr_test_otp_operation_done_wd = reg_wdata[0]; + + assign intr_test_otp_error_wd = reg_wdata[1]; + assign alert_test_we = addr_hit[3] & reg_we & !reg_error; + + assign alert_test_fatal_macro_error_wd = reg_wdata[0]; + + assign alert_test_fatal_check_error_wd = reg_wdata[1]; + + assign alert_test_fatal_bus_integ_error_wd = reg_wdata[2]; + + assign alert_test_fatal_prim_otp_alert_wd = reg_wdata[3]; + + assign alert_test_recov_prim_otp_alert_wd = reg_wdata[4]; + assign status_re = addr_hit[4] & reg_re & !reg_error; + assign err_code_0_re = addr_hit[5] & reg_re & !reg_error; + assign err_code_1_re = addr_hit[6] & reg_re & !reg_error; + assign err_code_2_re = addr_hit[7] & reg_re & !reg_error; + assign err_code_3_re = addr_hit[8] & reg_re & !reg_error; + assign err_code_4_re = addr_hit[9] & reg_re & !reg_error; + assign err_code_5_re = addr_hit[10] & reg_re & !reg_error; + assign err_code_6_re = addr_hit[11] & reg_re & !reg_error; + assign err_code_7_re = addr_hit[12] & reg_re & !reg_error; + assign err_code_8_re = addr_hit[13] & reg_re & !reg_error; + assign err_code_9_re = addr_hit[14] & reg_re & !reg_error; + assign err_code_10_re = addr_hit[15] & reg_re & !reg_error; + assign err_code_11_re = addr_hit[16] & reg_re & !reg_error; + assign err_code_12_re = addr_hit[17] & reg_re & !reg_error; + assign err_code_13_re = addr_hit[18] & reg_re & !reg_error; + assign err_code_14_re = addr_hit[19] & reg_re & !reg_error; + assign err_code_15_re = addr_hit[20] & reg_re & !reg_error; + assign err_code_16_re = addr_hit[21] & reg_re & !reg_error; + assign err_code_17_re = addr_hit[22] & reg_re & !reg_error; + assign err_code_18_re = addr_hit[23] & reg_re & !reg_error; + assign err_code_19_re = addr_hit[24] & reg_re & !reg_error; + assign err_code_20_re = addr_hit[25] & reg_re & !reg_error; + assign err_code_21_re = addr_hit[26] & reg_re & !reg_error; + assign err_code_22_re = addr_hit[27] & reg_re & !reg_error; + assign err_code_23_re = addr_hit[28] & reg_re & !reg_error; + assign direct_access_regwen_re = addr_hit[29] & reg_re & !reg_error; + assign direct_access_regwen_we = addr_hit[29] & reg_we & !reg_error; + + assign direct_access_regwen_wd = reg_wdata[0]; + assign direct_access_cmd_we = addr_hit[30] & reg_we & !reg_error; + + assign direct_access_cmd_rd_wd = reg_wdata[0]; + + assign direct_access_cmd_wr_wd = reg_wdata[1]; + + assign direct_access_cmd_digest_wd = reg_wdata[2]; + assign direct_access_address_we = addr_hit[31] & reg_we & !reg_error; + + assign direct_access_address_wd = reg_wdata[13:0]; + assign direct_access_wdata_0_we = addr_hit[32] & reg_we & !reg_error; + + assign direct_access_wdata_0_wd = reg_wdata[31:0]; + assign direct_access_wdata_1_we = addr_hit[33] & reg_we & !reg_error; + + assign direct_access_wdata_1_wd = reg_wdata[31:0]; + assign direct_access_rdata_0_re = addr_hit[34] & reg_re & !reg_error; + assign direct_access_rdata_1_re = addr_hit[35] & reg_re & !reg_error; + assign check_trigger_regwen_we = addr_hit[36] & reg_we & !reg_error; + + assign check_trigger_regwen_wd = reg_wdata[0]; + assign check_trigger_we = addr_hit[37] & reg_we & !reg_error; + + assign check_trigger_integrity_wd = reg_wdata[0]; + + assign check_trigger_consistency_wd = reg_wdata[1]; + assign check_regwen_we = addr_hit[38] & reg_we & !reg_error; + + assign check_regwen_wd = reg_wdata[0]; + assign check_timeout_we = addr_hit[39] & reg_we & !reg_error; + + assign check_timeout_wd = reg_wdata[31:0]; + assign integrity_check_period_we = addr_hit[40] & reg_we & !reg_error; + + assign integrity_check_period_wd = reg_wdata[31:0]; + assign consistency_check_period_we = addr_hit[41] & reg_we & !reg_error; + + assign consistency_check_period_wd = reg_wdata[31:0]; + assign vendor_test_read_lock_we = addr_hit[42] & reg_we & !reg_error; + + assign vendor_test_read_lock_wd = reg_wdata[0]; + assign creator_sw_cfg_read_lock_we = addr_hit[43] & reg_we & !reg_error; + + assign creator_sw_cfg_read_lock_wd = reg_wdata[0]; + assign owner_sw_cfg_read_lock_we = addr_hit[44] & reg_we & !reg_error; + + assign owner_sw_cfg_read_lock_wd = reg_wdata[0]; + assign ownership_slot_state_read_lock_we = addr_hit[45] & reg_we & !reg_error; + + assign ownership_slot_state_read_lock_wd = reg_wdata[0]; + assign rot_creator_auth_read_lock_we = addr_hit[46] & reg_we & !reg_error; + + assign rot_creator_auth_read_lock_wd = reg_wdata[0]; + assign rot_owner_auth_slot0_read_lock_we = addr_hit[47] & reg_we & !reg_error; + + assign rot_owner_auth_slot0_read_lock_wd = reg_wdata[0]; + assign rot_owner_auth_slot1_read_lock_we = addr_hit[48] & reg_we & !reg_error; + + assign rot_owner_auth_slot1_read_lock_wd = reg_wdata[0]; + assign plat_integ_auth_slot0_read_lock_we = addr_hit[49] & reg_we & !reg_error; + + assign plat_integ_auth_slot0_read_lock_wd = reg_wdata[0]; + assign plat_integ_auth_slot1_read_lock_we = addr_hit[50] & reg_we & !reg_error; + + assign plat_integ_auth_slot1_read_lock_wd = reg_wdata[0]; + assign plat_owner_auth_slot0_read_lock_we = addr_hit[51] & reg_we & !reg_error; + + assign plat_owner_auth_slot0_read_lock_wd = reg_wdata[0]; + assign plat_owner_auth_slot1_read_lock_we = addr_hit[52] & reg_we & !reg_error; + + assign plat_owner_auth_slot1_read_lock_wd = reg_wdata[0]; + assign plat_owner_auth_slot2_read_lock_we = addr_hit[53] & reg_we & !reg_error; + + assign plat_owner_auth_slot2_read_lock_wd = reg_wdata[0]; + assign plat_owner_auth_slot3_read_lock_we = addr_hit[54] & reg_we & !reg_error; + + assign plat_owner_auth_slot3_read_lock_wd = reg_wdata[0]; + assign ext_nvm_read_lock_we = addr_hit[55] & reg_we & !reg_error; + + assign ext_nvm_read_lock_wd = reg_wdata[0]; + assign rom_patch_read_lock_we = addr_hit[56] & reg_we & !reg_error; + + assign rom_patch_read_lock_wd = reg_wdata[0]; + assign vendor_test_digest_0_re = addr_hit[57] & reg_re & !reg_error; + assign vendor_test_digest_1_re = addr_hit[58] & reg_re & !reg_error; + assign creator_sw_cfg_digest_0_re = addr_hit[59] & reg_re & !reg_error; + assign creator_sw_cfg_digest_1_re = addr_hit[60] & reg_re & !reg_error; + assign owner_sw_cfg_digest_0_re = addr_hit[61] & reg_re & !reg_error; + assign owner_sw_cfg_digest_1_re = addr_hit[62] & reg_re & !reg_error; + assign rot_creator_auth_digest_0_re = addr_hit[63] & reg_re & !reg_error; + assign rot_creator_auth_digest_1_re = addr_hit[64] & reg_re & !reg_error; + assign rot_owner_auth_slot0_digest_0_re = addr_hit[65] & reg_re & !reg_error; + assign rot_owner_auth_slot0_digest_1_re = addr_hit[66] & reg_re & !reg_error; + assign rot_owner_auth_slot1_digest_0_re = addr_hit[67] & reg_re & !reg_error; + assign rot_owner_auth_slot1_digest_1_re = addr_hit[68] & reg_re & !reg_error; + assign plat_integ_auth_slot0_digest_0_re = addr_hit[69] & reg_re & !reg_error; + assign plat_integ_auth_slot0_digest_1_re = addr_hit[70] & reg_re & !reg_error; + assign plat_integ_auth_slot1_digest_0_re = addr_hit[71] & reg_re & !reg_error; + assign plat_integ_auth_slot1_digest_1_re = addr_hit[72] & reg_re & !reg_error; + assign plat_owner_auth_slot0_digest_0_re = addr_hit[73] & reg_re & !reg_error; + assign plat_owner_auth_slot0_digest_1_re = addr_hit[74] & reg_re & !reg_error; + assign plat_owner_auth_slot1_digest_0_re = addr_hit[75] & reg_re & !reg_error; + assign plat_owner_auth_slot1_digest_1_re = addr_hit[76] & reg_re & !reg_error; + assign plat_owner_auth_slot2_digest_0_re = addr_hit[77] & reg_re & !reg_error; + assign plat_owner_auth_slot2_digest_1_re = addr_hit[78] & reg_re & !reg_error; + assign plat_owner_auth_slot3_digest_0_re = addr_hit[79] & reg_re & !reg_error; + assign plat_owner_auth_slot3_digest_1_re = addr_hit[80] & reg_re & !reg_error; + assign rom_patch_digest_0_re = addr_hit[81] & reg_re & !reg_error; + assign rom_patch_digest_1_re = addr_hit[82] & reg_re & !reg_error; + assign hw_cfg0_digest_0_re = addr_hit[83] & reg_re & !reg_error; + assign hw_cfg0_digest_1_re = addr_hit[84] & reg_re & !reg_error; + assign hw_cfg1_digest_0_re = addr_hit[85] & reg_re & !reg_error; + assign hw_cfg1_digest_1_re = addr_hit[86] & reg_re & !reg_error; + assign secret0_digest_0_re = addr_hit[87] & reg_re & !reg_error; + assign secret0_digest_1_re = addr_hit[88] & reg_re & !reg_error; + assign secret1_digest_0_re = addr_hit[89] & reg_re & !reg_error; + assign secret1_digest_1_re = addr_hit[90] & reg_re & !reg_error; + assign secret2_digest_0_re = addr_hit[91] & reg_re & !reg_error; + assign secret2_digest_1_re = addr_hit[92] & reg_re & !reg_error; + assign secret3_digest_0_re = addr_hit[93] & reg_re & !reg_error; + assign secret3_digest_1_re = addr_hit[94] & reg_re & !reg_error; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + reg_we_check[4] = 1'b0; + reg_we_check[5] = 1'b0; + reg_we_check[6] = 1'b0; + reg_we_check[7] = 1'b0; + reg_we_check[8] = 1'b0; + reg_we_check[9] = 1'b0; + reg_we_check[10] = 1'b0; + reg_we_check[11] = 1'b0; + reg_we_check[12] = 1'b0; + reg_we_check[13] = 1'b0; + reg_we_check[14] = 1'b0; + reg_we_check[15] = 1'b0; + reg_we_check[16] = 1'b0; + reg_we_check[17] = 1'b0; + reg_we_check[18] = 1'b0; + reg_we_check[19] = 1'b0; + reg_we_check[20] = 1'b0; + reg_we_check[21] = 1'b0; + reg_we_check[22] = 1'b0; + reg_we_check[23] = 1'b0; + reg_we_check[24] = 1'b0; + reg_we_check[25] = 1'b0; + reg_we_check[26] = 1'b0; + reg_we_check[27] = 1'b0; + reg_we_check[28] = 1'b0; + reg_we_check[29] = direct_access_regwen_we; + reg_we_check[30] = direct_access_cmd_gated_we; + reg_we_check[31] = direct_access_address_gated_we; + reg_we_check[32] = direct_access_wdata_0_gated_we; + reg_we_check[33] = direct_access_wdata_1_gated_we; + reg_we_check[34] = 1'b0; + reg_we_check[35] = 1'b0; + reg_we_check[36] = check_trigger_regwen_we; + reg_we_check[37] = check_trigger_gated_we; + reg_we_check[38] = check_regwen_we; + reg_we_check[39] = check_timeout_gated_we; + reg_we_check[40] = integrity_check_period_gated_we; + reg_we_check[41] = consistency_check_period_gated_we; + reg_we_check[42] = vendor_test_read_lock_gated_we; + reg_we_check[43] = creator_sw_cfg_read_lock_gated_we; + reg_we_check[44] = owner_sw_cfg_read_lock_gated_we; + reg_we_check[45] = ownership_slot_state_read_lock_gated_we; + reg_we_check[46] = rot_creator_auth_read_lock_gated_we; + reg_we_check[47] = rot_owner_auth_slot0_read_lock_gated_we; + reg_we_check[48] = rot_owner_auth_slot1_read_lock_gated_we; + reg_we_check[49] = plat_integ_auth_slot0_read_lock_gated_we; + reg_we_check[50] = plat_integ_auth_slot1_read_lock_gated_we; + reg_we_check[51] = plat_owner_auth_slot0_read_lock_gated_we; + reg_we_check[52] = plat_owner_auth_slot1_read_lock_gated_we; + reg_we_check[53] = plat_owner_auth_slot2_read_lock_gated_we; + reg_we_check[54] = plat_owner_auth_slot3_read_lock_gated_we; + reg_we_check[55] = ext_nvm_read_lock_gated_we; + reg_we_check[56] = rom_patch_read_lock_gated_we; + reg_we_check[57] = 1'b0; + reg_we_check[58] = 1'b0; + reg_we_check[59] = 1'b0; + reg_we_check[60] = 1'b0; + reg_we_check[61] = 1'b0; + reg_we_check[62] = 1'b0; + reg_we_check[63] = 1'b0; + reg_we_check[64] = 1'b0; + reg_we_check[65] = 1'b0; + reg_we_check[66] = 1'b0; + reg_we_check[67] = 1'b0; + reg_we_check[68] = 1'b0; + reg_we_check[69] = 1'b0; + reg_we_check[70] = 1'b0; + reg_we_check[71] = 1'b0; + reg_we_check[72] = 1'b0; + reg_we_check[73] = 1'b0; + reg_we_check[74] = 1'b0; + reg_we_check[75] = 1'b0; + reg_we_check[76] = 1'b0; + reg_we_check[77] = 1'b0; + reg_we_check[78] = 1'b0; + reg_we_check[79] = 1'b0; + reg_we_check[80] = 1'b0; + reg_we_check[81] = 1'b0; + reg_we_check[82] = 1'b0; + reg_we_check[83] = 1'b0; + reg_we_check[84] = 1'b0; + reg_we_check[85] = 1'b0; + reg_we_check[86] = 1'b0; + reg_we_check[87] = 1'b0; + reg_we_check[88] = 1'b0; + reg_we_check[89] = 1'b0; + reg_we_check[90] = 1'b0; + reg_we_check[91] = 1'b0; + reg_we_check[92] = 1'b0; + reg_we_check[93] = 1'b0; + reg_we_check[94] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = intr_state_otp_operation_done_qs; + reg_rdata_next[1] = intr_state_otp_error_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_otp_operation_done_qs; + reg_rdata_next[1] = intr_enable_otp_error_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + end + + addr_hit[4]: begin + reg_rdata_next[0] = status_vendor_test_error_qs; + reg_rdata_next[1] = status_creator_sw_cfg_error_qs; + reg_rdata_next[2] = status_owner_sw_cfg_error_qs; + reg_rdata_next[3] = status_ownership_slot_state_error_qs; + reg_rdata_next[4] = status_rot_creator_auth_error_qs; + reg_rdata_next[5] = status_rot_owner_auth_slot0_error_qs; + reg_rdata_next[6] = status_rot_owner_auth_slot1_error_qs; + reg_rdata_next[7] = status_plat_integ_auth_slot0_error_qs; + reg_rdata_next[8] = status_plat_integ_auth_slot1_error_qs; + reg_rdata_next[9] = status_plat_owner_auth_slot0_error_qs; + reg_rdata_next[10] = status_plat_owner_auth_slot1_error_qs; + reg_rdata_next[11] = status_plat_owner_auth_slot2_error_qs; + reg_rdata_next[12] = status_plat_owner_auth_slot3_error_qs; + reg_rdata_next[13] = status_ext_nvm_error_qs; + reg_rdata_next[14] = status_rom_patch_error_qs; + reg_rdata_next[15] = status_hw_cfg0_error_qs; + reg_rdata_next[16] = status_hw_cfg1_error_qs; + reg_rdata_next[17] = status_secret0_error_qs; + reg_rdata_next[18] = status_secret1_error_qs; + reg_rdata_next[19] = status_secret2_error_qs; + reg_rdata_next[20] = status_secret3_error_qs; + reg_rdata_next[21] = status_life_cycle_error_qs; + reg_rdata_next[22] = status_dai_error_qs; + reg_rdata_next[23] = status_lci_error_qs; + reg_rdata_next[24] = status_timeout_error_qs; + reg_rdata_next[25] = status_lfsr_fsm_error_qs; + reg_rdata_next[26] = status_scrambling_fsm_error_qs; + reg_rdata_next[27] = status_key_deriv_fsm_error_qs; + reg_rdata_next[28] = status_bus_integ_error_qs; + reg_rdata_next[29] = status_dai_idle_qs; + reg_rdata_next[30] = status_check_pending_qs; + end + + addr_hit[5]: begin + reg_rdata_next[2:0] = err_code_0_qs; + end + + addr_hit[6]: begin + reg_rdata_next[2:0] = err_code_1_qs; + end + + addr_hit[7]: begin + reg_rdata_next[2:0] = err_code_2_qs; + end + + addr_hit[8]: begin + reg_rdata_next[2:0] = err_code_3_qs; + end + + addr_hit[9]: begin + reg_rdata_next[2:0] = err_code_4_qs; + end + + addr_hit[10]: begin + reg_rdata_next[2:0] = err_code_5_qs; + end + + addr_hit[11]: begin + reg_rdata_next[2:0] = err_code_6_qs; + end + + addr_hit[12]: begin + reg_rdata_next[2:0] = err_code_7_qs; + end + + addr_hit[13]: begin + reg_rdata_next[2:0] = err_code_8_qs; + end + + addr_hit[14]: begin + reg_rdata_next[2:0] = err_code_9_qs; + end + + addr_hit[15]: begin + reg_rdata_next[2:0] = err_code_10_qs; + end + + addr_hit[16]: begin + reg_rdata_next[2:0] = err_code_11_qs; + end + + addr_hit[17]: begin + reg_rdata_next[2:0] = err_code_12_qs; + end + + addr_hit[18]: begin + reg_rdata_next[2:0] = err_code_13_qs; + end + + addr_hit[19]: begin + reg_rdata_next[2:0] = err_code_14_qs; + end + + addr_hit[20]: begin + reg_rdata_next[2:0] = err_code_15_qs; + end + + addr_hit[21]: begin + reg_rdata_next[2:0] = err_code_16_qs; + end + + addr_hit[22]: begin + reg_rdata_next[2:0] = err_code_17_qs; + end + + addr_hit[23]: begin + reg_rdata_next[2:0] = err_code_18_qs; + end + + addr_hit[24]: begin + reg_rdata_next[2:0] = err_code_19_qs; + end + + addr_hit[25]: begin + reg_rdata_next[2:0] = err_code_20_qs; + end + + addr_hit[26]: begin + reg_rdata_next[2:0] = err_code_21_qs; + end + + addr_hit[27]: begin + reg_rdata_next[2:0] = err_code_22_qs; + end + + addr_hit[28]: begin + reg_rdata_next[2:0] = err_code_23_qs; + end + + addr_hit[29]: begin + reg_rdata_next[0] = direct_access_regwen_qs; + end + + addr_hit[30]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + end + + addr_hit[31]: begin + reg_rdata_next[13:0] = direct_access_address_qs; + end + + addr_hit[32]: begin + reg_rdata_next[31:0] = direct_access_wdata_0_qs; + end + + addr_hit[33]: begin + reg_rdata_next[31:0] = direct_access_wdata_1_qs; + end + + addr_hit[34]: begin + reg_rdata_next[31:0] = direct_access_rdata_0_qs; + end + + addr_hit[35]: begin + reg_rdata_next[31:0] = direct_access_rdata_1_qs; + end + + addr_hit[36]: begin + reg_rdata_next[0] = check_trigger_regwen_qs; + end + + addr_hit[37]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[38]: begin + reg_rdata_next[0] = check_regwen_qs; + end + + addr_hit[39]: begin + reg_rdata_next[31:0] = check_timeout_qs; + end + + addr_hit[40]: begin + reg_rdata_next[31:0] = integrity_check_period_qs; + end + + addr_hit[41]: begin + reg_rdata_next[31:0] = consistency_check_period_qs; + end + + addr_hit[42]: begin + reg_rdata_next[0] = vendor_test_read_lock_qs; + end + + addr_hit[43]: begin + reg_rdata_next[0] = creator_sw_cfg_read_lock_qs; + end + + addr_hit[44]: begin + reg_rdata_next[0] = owner_sw_cfg_read_lock_qs; + end + + addr_hit[45]: begin + reg_rdata_next[0] = ownership_slot_state_read_lock_qs; + end + + addr_hit[46]: begin + reg_rdata_next[0] = rot_creator_auth_read_lock_qs; + end + + addr_hit[47]: begin + reg_rdata_next[0] = rot_owner_auth_slot0_read_lock_qs; + end + + addr_hit[48]: begin + reg_rdata_next[0] = rot_owner_auth_slot1_read_lock_qs; + end + + addr_hit[49]: begin + reg_rdata_next[0] = plat_integ_auth_slot0_read_lock_qs; + end + + addr_hit[50]: begin + reg_rdata_next[0] = plat_integ_auth_slot1_read_lock_qs; + end + + addr_hit[51]: begin + reg_rdata_next[0] = plat_owner_auth_slot0_read_lock_qs; + end + + addr_hit[52]: begin + reg_rdata_next[0] = plat_owner_auth_slot1_read_lock_qs; + end + + addr_hit[53]: begin + reg_rdata_next[0] = plat_owner_auth_slot2_read_lock_qs; + end + + addr_hit[54]: begin + reg_rdata_next[0] = plat_owner_auth_slot3_read_lock_qs; + end + + addr_hit[55]: begin + reg_rdata_next[0] = ext_nvm_read_lock_qs; + end + + addr_hit[56]: begin + reg_rdata_next[0] = rom_patch_read_lock_qs; + end + + addr_hit[57]: begin + reg_rdata_next[31:0] = vendor_test_digest_0_qs; + end + + addr_hit[58]: begin + reg_rdata_next[31:0] = vendor_test_digest_1_qs; + end + + addr_hit[59]: begin + reg_rdata_next[31:0] = creator_sw_cfg_digest_0_qs; + end + + addr_hit[60]: begin + reg_rdata_next[31:0] = creator_sw_cfg_digest_1_qs; + end + + addr_hit[61]: begin + reg_rdata_next[31:0] = owner_sw_cfg_digest_0_qs; + end + + addr_hit[62]: begin + reg_rdata_next[31:0] = owner_sw_cfg_digest_1_qs; + end + + addr_hit[63]: begin + reg_rdata_next[31:0] = rot_creator_auth_digest_0_qs; + end + + addr_hit[64]: begin + reg_rdata_next[31:0] = rot_creator_auth_digest_1_qs; + end + + addr_hit[65]: begin + reg_rdata_next[31:0] = rot_owner_auth_slot0_digest_0_qs; + end + + addr_hit[66]: begin + reg_rdata_next[31:0] = rot_owner_auth_slot0_digest_1_qs; + end + + addr_hit[67]: begin + reg_rdata_next[31:0] = rot_owner_auth_slot1_digest_0_qs; + end + + addr_hit[68]: begin + reg_rdata_next[31:0] = rot_owner_auth_slot1_digest_1_qs; + end + + addr_hit[69]: begin + reg_rdata_next[31:0] = plat_integ_auth_slot0_digest_0_qs; + end + + addr_hit[70]: begin + reg_rdata_next[31:0] = plat_integ_auth_slot0_digest_1_qs; + end + + addr_hit[71]: begin + reg_rdata_next[31:0] = plat_integ_auth_slot1_digest_0_qs; + end + + addr_hit[72]: begin + reg_rdata_next[31:0] = plat_integ_auth_slot1_digest_1_qs; + end + + addr_hit[73]: begin + reg_rdata_next[31:0] = plat_owner_auth_slot0_digest_0_qs; + end + + addr_hit[74]: begin + reg_rdata_next[31:0] = plat_owner_auth_slot0_digest_1_qs; + end + + addr_hit[75]: begin + reg_rdata_next[31:0] = plat_owner_auth_slot1_digest_0_qs; + end + + addr_hit[76]: begin + reg_rdata_next[31:0] = plat_owner_auth_slot1_digest_1_qs; + end + + addr_hit[77]: begin + reg_rdata_next[31:0] = plat_owner_auth_slot2_digest_0_qs; + end + + addr_hit[78]: begin + reg_rdata_next[31:0] = plat_owner_auth_slot2_digest_1_qs; + end + + addr_hit[79]: begin + reg_rdata_next[31:0] = plat_owner_auth_slot3_digest_0_qs; + end + + addr_hit[80]: begin + reg_rdata_next[31:0] = plat_owner_auth_slot3_digest_1_qs; + end + + addr_hit[81]: begin + reg_rdata_next[31:0] = rom_patch_digest_0_qs; + end + + addr_hit[82]: begin + reg_rdata_next[31:0] = rom_patch_digest_1_qs; + end + + addr_hit[83]: begin + reg_rdata_next[31:0] = hw_cfg0_digest_0_qs; + end + + addr_hit[84]: begin + reg_rdata_next[31:0] = hw_cfg0_digest_1_qs; + end + + addr_hit[85]: begin + reg_rdata_next[31:0] = hw_cfg1_digest_0_qs; + end + + addr_hit[86]: begin + reg_rdata_next[31:0] = hw_cfg1_digest_1_qs; + end + + addr_hit[87]: begin + reg_rdata_next[31:0] = secret0_digest_0_qs; + end + + addr_hit[88]: begin + reg_rdata_next[31:0] = secret0_digest_1_qs; + end + + addr_hit[89]: begin + reg_rdata_next[31:0] = secret1_digest_0_qs; + end + + addr_hit[90]: begin + reg_rdata_next[31:0] = secret1_digest_1_qs; + end + + addr_hit[91]: begin + reg_rdata_next[31:0] = secret2_digest_0_qs; + end + + addr_hit[92]: begin + reg_rdata_next[31:0] = secret2_digest_1_qs; + end + + addr_hit[93]: begin + reg_rdata_next[31:0] = secret3_digest_0_qs; + end + + addr_hit[94]: begin + reg_rdata_next[31:0] = secret3_digest_1_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_dai.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_dai.sv new file mode 100644 index 00000000000..5ffad06dfbd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_dai.sv @@ -0,0 +1,864 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Direct access interface for OTP controller. +// + +`include "prim_flop_macros.sv" + +module otp_ctrl_dai + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import otp_ctrl_macro_pkg::OtpAddrShift; + import otp_ctrl_macro_pkg::OtpAddrWidth; + import otp_ctrl_macro_pkg::OtpIfWidth; + import otp_ctrl_macro_pkg::OtpSizeWidth; + import otp_ctrl_macro_pkg::OtpWidth; + import otp_ctrl_top_specific_pkg::*; +( + input clk_i, + input rst_ni, + // Init request from power manager + input init_req_i, + output logic init_done_o, + // Init request going to partitions + output logic part_init_req_o, + input [NumPart-1:0] part_init_done_i, + // Escalation input. This moves the FSM into a terminal state and locks down + // the DAI. + input lc_ctrl_pkg::lc_tx_t escalate_en_i, + // Output error state of DAI, to be consumed by OTP error/alert logic. + // Note that most errors are not recoverable and move the DAI FSM into + // a terminal error state. + output otp_err_e error_o, + // This error signal is pulsed high if the FSM has been glitched into an invalid state. + // Although it is somewhat redundant with the error code in error_o above, it is + // meant to cover cases where we already latched an error code while the FSM is + // glitched into an invalid state (since in that case, the error code will not be + // overridden with the FSM error code so that the original error code is still + // discoverable). + output logic fsm_err_o, + // Access/lock status from partitions + // SEC_CM: ACCESS.CTRL.MUBI + input part_access_t [NumPart-1:0] part_access_i, + // CSR interface + input [OtpByteAddrWidth-1:0] dai_addr_i, + input dai_cmd_e dai_cmd_i, + input logic dai_req_i, + input [NumDaiWords-1:0][31:0] dai_wdata_i, + output logic dai_idle_o, // wired to the status CSRs + output logic dai_prog_idle_o, // wired to lfsr timer and pwrmgr + output logic dai_cmd_done_o, // this is used to raise an IRQ + output logic [NumDaiWords-1:0][31:0] dai_rdata_o, + // OTP interface + output logic otp_req_o, + output otp_ctrl_macro_pkg::cmd_e otp_cmd_o, + output logic [OtpSizeWidth-1:0] otp_size_o, + output logic [OtpIfWidth-1:0] otp_wdata_o, + output logic [OtpAddrWidth-1:0] otp_addr_o, + input otp_gnt_i, + input otp_rvalid_i, + input [ScrmblBlockWidth-1:0] otp_rdata_i, + input otp_ctrl_macro_pkg::err_e otp_err_i, + // Scrambling mutex request + output logic scrmbl_mtx_req_o, + input scrmbl_mtx_gnt_i, + // Scrambling datapath interface + output otp_scrmbl_cmd_e scrmbl_cmd_o, + output digest_mode_e scrmbl_mode_o, + output logic [ConstSelWidth-1:0] scrmbl_sel_o, + output logic [ScrmblBlockWidth-1:0] scrmbl_data_o, + output logic scrmbl_valid_o, + input logic scrmbl_ready_i, + input logic scrmbl_valid_i, + input logic [ScrmblBlockWidth-1:0] scrmbl_data_i +); + + //////////////////////// + // Integration Checks // + //////////////////////// + + import prim_mubi_pkg::*; + import prim_util_pkg::vbits; + + localparam int CntWidth = OtpByteAddrWidth - $clog2(ScrmblBlockWidth/8); + + // Integration checks for parameters. + `ASSERT_INIT(CheckNativeOtpWidth0_A, (ScrmblBlockWidth % OtpWidth) == 0) + `ASSERT_INIT(CheckNativeOtpWidth1_A, (32 % OtpWidth) == 0) + + ///////////////////// + // DAI Control FSM // + ///////////////////// + + // SEC_CM: DAI.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 20 -n 12 \ + // -s 3011551511 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||| (31.05%) + // 6: |||||||||||||||||||| (36.84%) + // 7: |||||||| (15.26%) + // 8: |||| (8.95%) + // 9: || (5.26%) + // 10: (1.58%) + // 11: (1.05%) + // 12: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 11 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 9 + // + localparam int StateWidth = 12; + typedef enum logic [StateWidth-1:0] { + ResetSt = 12'b101111010100, + InitOtpSt = 12'b110000110010, + InitPartSt = 12'b000111111001, + IdleSt = 12'b111010000011, + ErrorSt = 12'b100010001110, + ReadSt = 12'b100101100110, + ReadWaitSt = 12'b001100000000, + DescrSt = 12'b011000101111, + DescrWaitSt = 12'b110101011111, + WriteSt = 12'b110111001000, + WriteWaitSt = 12'b111001111100, + ScrSt = 12'b000000010101, + ScrWaitSt = 12'b010110110100, + DigClrSt = 12'b001111001111, + DigReadSt = 12'b001001110011, + DigReadWaitSt = 12'b101110111010, + DigSt = 12'b011111100010, + DigPadSt = 12'b011010011000, + DigFinSt = 12'b110011100101, + DigWaitSt = 12'b100000101001 + } state_e; + + typedef enum logic [1:0] { + OtpData = 2'b00, + DaiData = 2'b01, + ScrmblData = 2'b10 + } data_sel_e; + + + typedef enum logic { + PartOffset = 1'b0, + DaiOffset = 1'b1 + } addr_sel_e; + + state_e state_d, state_q; + logic [CntWidth-1:0] cnt; + logic cnt_en, cnt_clr, cnt_err; + otp_err_e error_d, error_q; + logic data_en, data_clr; + data_sel_e data_sel; + addr_sel_e base_sel_d, base_sel_q; + logic [ScrmblBlockWidth-1:0] data_q; + logic [NumPartWidth-1:0] part_idx; + logic [NumPart-1:0][OtpAddrWidth-1:0] digest_addr_lut; + logic part_sel_valid; + + // Depending on the partition configuration, the wrapper is instructed to ignore integrity + // calculations and checks. To be on the safe side, the partition filters error responses at this + // point and does not report any integrity errors if integrity is disabled. + otp_err_e otp_err; + always_comb begin + otp_err = otp_err_e'(otp_err_i); + if (!PartInfo[part_idx].integrity && + otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin + otp_err = NoError; + end + end + + // Output partition error state. + assign error_o = error_q; + // Working register is connected to data outputs. + assign otp_wdata_o = data_q; + assign scrmbl_data_o = data_q; + // Only expose this working register in IdleSt. + // The FSM below makes sure to clear this register + // after digest and write ops. + assign dai_rdata_o = (state_q == IdleSt) ? data_q : '0; + + always_comb begin : p_fsm + state_d = state_q; + + // Init signals + init_done_o = 1'b1; + part_init_req_o = 1'b0; + + // DAI signals + dai_idle_o = 1'b0; + dai_prog_idle_o = 1'b1; + dai_cmd_done_o = 1'b0; + + // OTP signals + otp_req_o = 1'b0; + otp_cmd_o = otp_ctrl_macro_pkg::Init; + + // Scrambling mutex + scrmbl_mtx_req_o = 1'b0; + + // Scrambling datapath + scrmbl_cmd_o = LoadShadow; + scrmbl_sel_o = CnstyDigest; + scrmbl_mode_o = StandardMode; + scrmbl_valid_o = 1'b0; + + // Counter + cnt_en = 1'b0; + cnt_clr = 1'b0; + base_sel_d = base_sel_q; + + // Temporary data register + data_en = 1'b0; + data_clr = 1'b0; + data_sel = OtpData; + + // Error Register + error_d = error_q; + fsm_err_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // We get here after reset and wait until the power manager + // requests OTP initialization. If initialization is requested, + // an init command is written to the OTP macro, and we move on + // to the InitOtpSt waiting state. + ResetSt: begin + init_done_o = 1'b0; + dai_prog_idle_o = 1'b0; + data_clr = 1'b1; + if (init_req_i) begin + otp_req_o = 1'b1; + if (otp_gnt_i) begin + state_d = InitOtpSt; + end + end + end + /////////////////////////////////////////////////////////////////// + // We wait here until the OTP macro has initialized without + // error. If an error occurred during this stage, we latch that + // error and move into a terminal error state. + InitOtpSt: begin + init_done_o = 1'b0; + dai_prog_idle_o = 1'b0; + if (otp_rvalid_i) begin + if ((!(otp_err inside {NoError, MacroEccCorrError}))) begin + state_d = ErrorSt; + error_d = otp_err; + end else begin + state_d = InitPartSt; + end + end + end + /////////////////////////////////////////////////////////////////// + // Since the OTP macro is now functional, we can send out an + // initialization request to all partitions and wait until they + // all have initialized. + InitPartSt: begin + init_done_o = 1'b0; + dai_prog_idle_o = 1'b0; + part_init_req_o = 1'b1; + if (part_init_done_i == {NumPart{1'b1}}) begin + state_d = IdleSt; + end + end + /////////////////////////////////////////////////////////////////// + // Idle state where we wait for incoming commands. + // Invalid commands trigger a CmdInvErr, which is recoverable. + IdleSt: begin + dai_idle_o = 1'b1; + if (dai_req_i) begin + // This clears previous (recoverable) and reset the counter. + error_d = NoError; + cnt_clr = 1'b1; + unique case (dai_cmd_i) + DaiRead: begin + state_d = ReadSt; + // Clear the temporary data register. + data_clr = 1'b1; + base_sel_d = DaiOffset; + end + DaiWrite: begin + data_sel = DaiData; + // Fetch data block. + data_en = 1'b1; + base_sel_d = DaiOffset; + // If this partition is scrambled, directly go to write scrambling first. + if (PartInfo[part_idx].secret) begin + state_d = ScrSt; + end else begin + state_d = WriteSt; + end + end + DaiDigest: begin + state_d = DigClrSt; + scrmbl_mtx_req_o = 1'b1; + base_sel_d = PartOffset; + end + default: ; // Ignore invalid commands + endcase // dai_cmd_i + end // dai_req_i + end + /////////////////////////////////////////////////////////////////// + // Each time we request a block of data from OTP, we re-check + // whether read access has been locked for this partition. If + // that is the case, we immediately bail out. Otherwise, we + // request a block of data from OTP. + ReadSt: begin + if (part_sel_valid && (mubi8_test_false_strict(part_access_i[part_idx].read_lock) || + // HW digests always remain readable. + PartInfo[part_idx].hw_digest && otp_addr_o == + digest_addr_lut[part_idx])) begin + otp_req_o = 1'b1; + // Depending on the partition configuration, + // the wrapper is instructed to ignore integrity errors. + if (PartInfo[part_idx].integrity) begin + otp_cmd_o = otp_ctrl_macro_pkg::Read; + end else begin + otp_cmd_o = otp_ctrl_macro_pkg::ReadRaw; + end + if (otp_gnt_i) begin + state_d = ReadWaitSt; + end + end else begin + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and write to readout register. Check + // whether descrambling is required or not. In case an OTP + // transaction fails, latch the OTP error code, and jump to + // terminal error state. + ReadWaitSt: begin + // Continuously check read access and bail out if this is not consistent. + if (part_sel_valid && (mubi8_test_false_strict(part_access_i[part_idx].read_lock) || + // HW digests always remain readable. + PartInfo[part_idx].hw_digest && otp_addr_o == + digest_addr_lut[part_idx])) begin + if (otp_rvalid_i) begin + // Check OTP return code. + if (otp_err inside {NoError, MacroEccCorrError}) begin + data_en = 1'b1; + // We do not need to descramble the digest values. + if (PartInfo[part_idx].secret && otp_addr_o != digest_addr_lut[part_idx]) begin + state_d = DescrSt; + end else begin + state_d = IdleSt; + dai_cmd_done_o = 1'b1; + end + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + end + end + // At this point, this check MUST succeed - otherwise this means that + // there was a tampering attempt. Hence we go into a terminal error state + // when this check fails. + end else begin + state_d = ErrorSt; + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // Descrambling state. This first acquires the scrambling + // datapath mutex. Note that once the mutex is acquired, we have + // exclusive access to the scrambling datapath until we release + // the mutex by deasserting scrmbl_mtx_req_o. + // SEC_CM: SECRET.MEM.SCRAMBLE + DescrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Decrypt; + scrmbl_sel_o = PartInfo[part_idx].key_sel; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = DescrWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the descrambled data to return. Note that we release + // the mutex lock upon leaving this state. + // SEC_CM: SECRET.MEM.SCRAMBLE + DescrWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_sel_o = PartInfo[part_idx].key_sel; + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + state_d = IdleSt; + data_en = 1'b1; + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // First, check whether write accesses are allowed to this + // partition, and error out otherwise. Note that for buffered + // partitions, we do not allow DAI writes to the digest offset. + // Unbuffered partitions have SW managed digests, hence that + // check is not needed in that case. The LC partition is + // permanently write locked and can hence not be written via the DAI. + WriteSt: begin + dai_prog_idle_o = 1'b0; + if (part_sel_valid && mubi8_test_false_strict(part_access_i[part_idx].write_lock) && + // If this is a HW digest write to a buffered partition. + ((PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].hw_digest && + base_sel_q == PartOffset && otp_addr_o == digest_addr_lut[part_idx]) || + // If this is a non HW digest write to a buffered partition. + (PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].hw_digest && + base_sel_q == DaiOffset && otp_addr_o < digest_addr_lut[part_idx]) || + // If this is a write to an unbuffered partition + (PartInfo[part_idx].variant != Buffered && base_sel_q == DaiOffset))) begin + otp_req_o = 1'b1; + // Depending on the partition configuration, + // the wrapper is instructed to ignore integrity errors. + if (PartInfo[part_idx].integrity) begin + otp_cmd_o = otp_ctrl_macro_pkg::Write; + end else begin + otp_cmd_o = otp_ctrl_macro_pkg::WriteRaw; + end + if (otp_gnt_i) begin + state_d = WriteWaitSt; + end + end else begin + // Clear working register state. + data_clr = 1'b1; + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response, and then go back to idle. In case an + // OTP transaction fails, latch the OTP error code, and jump to + // terminal error state. + WriteWaitSt: begin + dai_prog_idle_o = 1'b0; + // Continuously check write access and bail out if this is not consistent. + if (part_sel_valid && mubi8_test_false_strict(part_access_i[part_idx].write_lock) && + // If this is a HW digest write to a buffered partition. + ((PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].hw_digest && + base_sel_q == PartOffset && otp_addr_o == digest_addr_lut[part_idx]) || + // If this is a non HW digest write to a buffered partition. + (PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].hw_digest && + base_sel_q == DaiOffset && otp_addr_o < digest_addr_lut[part_idx]) || + // If this is a write to an unbuffered partition + (PartInfo[part_idx].variant != Buffered && base_sel_q == DaiOffset))) begin + + if (otp_rvalid_i) begin + // Check OTP return code. Note that non-blank errors are recoverable. + if ((!(otp_err inside {NoError, MacroWriteBlankError}))) begin + state_d = ErrorSt; + error_d = otp_err; + end else begin + // Clear working register state. + data_clr = 1'b1; + state_d = IdleSt; + dai_cmd_done_o = 1'b1; + // Signal non-blank state, but do not go to terminal error state. + if (otp_err == MacroWriteBlankError) begin + error_d = otp_err; + end + end + end + // At this point, this check MUST succeed - otherwise this means that + // there was a tampering attempt. Hence we go into a terminal error state + // when this check fails. + end else begin + state_d = ErrorSt; + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // Scrambling state. This first acquires the scrambling + // datapath mutex. Note that once the mutex is acquired, we have + // exclusive access to the scrambling datapath until we release + // the mutex by deasserting scrmbl_mtx_req_o. + // SEC_CM: SECRET.MEM.SCRAMBLE + ScrSt: begin + scrmbl_mtx_req_o = 1'b1; + // Check write access and bail out if this is not consistent. + if (part_sel_valid && mubi8_test_false_strict(part_access_i[part_idx].write_lock) && + // If this is a non HW digest write to a buffered partition. + (PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].secret && + PartInfo[part_idx].hw_digest && base_sel_q == DaiOffset && + otp_addr_o < digest_addr_lut[part_idx])) begin + + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Encrypt; + scrmbl_sel_o = PartInfo[part_idx].key_sel; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = ScrWaitSt; + end + end else begin + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the scrambled data to return. Note that we release + // the mutex lock upon leaving this state. + // SEC_CM: SECRET.MEM.SCRAMBLE + ScrWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + // Continuously check write access and bail out if this is not consistent. + if (part_sel_valid && mubi8_test_false_strict(part_access_i[part_idx].write_lock) && + // If this is a non HW digest write to a buffered partition. + (PartInfo[part_idx].variant == Buffered && PartInfo[part_idx].secret && + PartInfo[part_idx].hw_digest && base_sel_q == DaiOffset && + otp_addr_o < digest_addr_lut[part_idx])) begin + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + state_d = WriteSt; + data_en = 1'b1; + end + // At this point, this check MUST succeed - otherwise this means that + // there was a tampering attempt. Hence we go into a terminal error state + // when this check fails. + end else begin + state_d = ErrorSt; + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // First, acquire the mutex for the digest and clear the digest state. + // SEC_CM: PART.MEM.DIGEST + DigClrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + // Need to reset the digest state and set digest mode to "standard". + scrmbl_cmd_o = DigestInit; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = DigReadSt; + end + end + /////////////////////////////////////////////////////////////////// + // This requests a 64bit block to be pushed into the digest datapath. + // We also check here whether the partition has been write locked. + // SEC_CM: PART.MEM.DIGEST + DigReadSt: begin + scrmbl_mtx_req_o = 1'b1; + if (part_sel_valid && + mubi8_test_false_strict(part_access_i[part_idx].read_lock) && + mubi8_test_false_strict(part_access_i[part_idx].write_lock)) begin + otp_req_o = 1'b1; + // Depending on the partition configuration, + // the wrapper is instructed to ignore integrity errors. + if (PartInfo[part_idx].integrity) begin + otp_cmd_o = otp_ctrl_macro_pkg::Read; + end else begin + otp_cmd_o = otp_ctrl_macro_pkg::ReadRaw; + end + if (otp_gnt_i) begin + state_d = DigReadWaitSt; + end + end else begin + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + dai_cmd_done_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and write to readout register. Check + // whether descrambling is required or not. In case an OTP + // transaction fails, latch the OTP error code, and jump to + // terminal error state. + // SEC_CM: PART.MEM.DIGEST + DigReadWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + if (otp_rvalid_i) begin + cnt_en = 1'b1; + // Check OTP return code. + if ((!(otp_err inside {NoError, MacroEccCorrError}))) begin + state_d = ErrorSt; + error_d = otp_err; + end else begin + data_en = 1'b1; + state_d = DigSt; + // Signal soft ECC errors, but do not go into terminal error state. + if (otp_err == MacroEccCorrError) begin + error_d = otp_err; + end + end + end + end + /////////////////////////////////////////////////////////////////// + // Push the word read into the scrambling datapath. The last + // block is repeated in case the number blocks in this partition + // is odd. + // SEC_CM: PART.MEM.DIGEST + DigSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + // No need to digest the digest value itself + if (otp_addr_o == digest_addr_lut[part_idx]) begin + // Trigger digest round in case this is the second block in a row. + if (!cnt[0]) begin + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + state_d = DigFinSt; + end + // Otherwise, just load low word and go to padding state. + end else if (scrmbl_ready_i) begin + state_d = DigPadSt; + end + end else begin + // Trigger digest round in case this is the second block in a row. + if (!cnt[0]) begin + scrmbl_cmd_o = Digest; + end + // Go back and fetch more data blocks. + if (scrmbl_ready_i) begin + state_d = DigReadSt; + end + end + end + /////////////////////////////////////////////////////////////////// + // Padding state, just repeat the last block and go to digest + // finalization. + // SEC_CM: PART.MEM.DIGEST + DigPadSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + state_d = DigFinSt; + end + end + /////////////////////////////////////////////////////////////////// + // Trigger digest finalization and go wait for the result. + // SEC_CM: PART.MEM.DIGEST + DigFinSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = DigestFinalize; + if (scrmbl_ready_i) begin + state_d = DigWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the digest to return, and write the result to OTP. + // Note that the write address will be correct in this state, + // since the counter has been stepped to the correct address as + // part of the readout sequence, and the correct size for this + // access has been loaded before. + // SEC_CM: PART.MEM.DIGEST + DigWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + state_d = WriteSt; + data_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Terminal Error State. This locks access to the DAI. Make sure + // an FsmStateError error code is assigned here, in case no error code has + // been assigned yet. + ErrorSt: begin + if (error_q == NoError) begin + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // We should never get here. If we do (e.g. via a malicious + // glitch), error out immediately. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation. + // SEC_CM: DAI.FSM.LOCAL_ESC, DAI.FSM.GLOBAL_ESC + if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + if (state_q != ErrorSt) begin + error_d = FsmStateError; + end + end + end + + //////////////////////////// + // Partition Select Logic // + //////////////////////////// + + // This checks which partition the address belongs to by comparing + // the incoming address to the partition address ranges. The onehot + // bitvector generated by the parallel comparisons is fed into a + // binary tree that determines the partition index with O(log(N)) delay. + + logic [NumPart-1:0] part_sel_oh; + for (genvar k = 0; k < NumPart; k++) begin : gen_part_sel + localparam int unsigned PartEndInt = 32'(PartInfo[k].offset) + 32'(PartInfo[k].size); + localparam int unsigned DigestOffsetInt = PartEndInt - ScrmblBlockWidth / 8; + localparam int unsigned DigestAddrLutInt = DigestOffsetInt >> OtpAddrShift; + + // PartEnd has an extra bit to cope with the case where offset + size overflows. However, we + // arrange the address map to make sure that PartEndInt is at most 1 << OtpByteAddrWidth. Check + // that here. + `ASSERT_INIT(PartEndMax_A, PartEndInt <= (1 << OtpByteAddrWidth)) + + // The shift right by OtpAddrShift drops exactly the bottom bits that are needed to convert + // between OtpAddrWidth and OtpByteAddrWidth, so we know that we can slice safely here. + localparam bit [OtpAddrWidth-1:0] DigestAddrLut = DigestAddrLutInt[OtpAddrWidth-1:0]; + + if (PartInfo[k].offset == 0) begin : gen_zero_offset + assign part_sel_oh[k] = ({1'b0, dai_addr_i} < PartEndInt[OtpByteAddrWidth:0]); + + end else begin : gen_nonzero_offset + assign part_sel_oh[k] = (dai_addr_i >= PartInfo[k].offset) & + ({1'b0, dai_addr_i} < PartEndInt[OtpByteAddrWidth:0]); + end + assign digest_addr_lut[k] = DigestAddrLut; + end + + `ASSERT(ScrmblBlockWidthGe8_A, ScrmblBlockWidth >= 8) + `ASSERT(PartSelMustBeOnehot_A, $onehot0(part_sel_oh)) + + prim_arbiter_fixed #( + .N(NumPart), + .EnDataPort(0) + ) u_part_sel_idx ( + .clk_i, + .rst_ni, + .req_i ( part_sel_oh ), + .data_i ( '{default: '0} ), + .gnt_o ( ), // unused + .idx_o ( part_idx ), + .valid_o ( part_sel_valid ), // used for detecting OOB addresses + .data_o ( ), // unused + .ready_i ( 1'b0 ) + ); + + ///////////////////////////////////// + // Address Calculations for Digest // + ///////////////////////////////////// + + // Depending on whether this is a 32bit or 64bit partition, we cut off the lower address bits. + // Access sizes are either 64bit or 32bit, depending on what region the access goes to. + logic [OtpByteAddrWidth-1:0] addr_base; + always_comb begin : p_size_sel + otp_size_o = OtpSizeWidth'(unsigned'(32 / OtpWidth - 1)); + addr_base = {dai_addr_i[OtpByteAddrWidth-1:2], 2'h0}; + + // 64bit transaction for scrambled partitions. + if (PartInfo[part_idx].secret) begin + otp_size_o = OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)); + addr_base = {dai_addr_i[OtpByteAddrWidth-1:3], 3'h0}; + // 64bit transaction if computing a digest. + end else if (PartInfo[part_idx].hw_digest && (base_sel_q == PartOffset)) begin + otp_size_o = OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)); + addr_base = PartInfo[part_idx].offset; + // 64bit transaction if the DAI address points to the partition's digest offset. + end else if ((PartInfo[part_idx].hw_digest || PartInfo[part_idx].sw_digest) && + (base_sel_q == DaiOffset) && + ({dai_addr_i[OtpByteAddrWidth-1:3], 2'b0} == digest_addr_lut[part_idx])) begin + otp_size_o = OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)); + addr_base = {dai_addr_i[OtpByteAddrWidth-1:3], 3'h0}; + end + end + + // Address counter - this is only used for computing a digest, hence the increment is + // fixed to 8 byte. + // SEC_CM: DAI.CTR.REDUN + prim_count #( + .Width(CntWidth) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + // Note that OTP works on halfword (16bit) addresses, hence need to + // shift the addresses appropriately. + logic [OtpByteAddrWidth-1:0] addr_calc; + assign addr_calc = {cnt, {$clog2(ScrmblBlockWidth/8){1'b0}}} + addr_base; + assign otp_addr_o = OtpAddrWidth'(addr_calc >> OtpAddrShift); + + /////////////// + // Registers // + /////////////// + + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + error_q <= NoError; + data_q <= '0; + base_sel_q <= DaiOffset; + end else begin + error_q <= error_d; + base_sel_q <= base_sel_d; + + // Working register + if (data_clr) begin + data_q <= '0; + end else if (data_en) begin + if (data_sel == ScrmblData) begin + data_q <= scrmbl_data_i; + end else if (data_sel == DaiData) begin + data_q <= dai_wdata_i; + end else begin + data_q <= otp_rdata_i; + end + end + end + end + + //////////////// + // Assertions // + //////////////// + + // Known assertions + `ASSERT_KNOWN(InitDoneKnown_A, init_done_o) + `ASSERT_KNOWN(PartInitReqKnown_A, part_init_req_o) + `ASSERT_KNOWN(ErrorKnown_A, error_o) + `ASSERT_KNOWN(DaiIdleKnown_A, dai_idle_o) + `ASSERT_KNOWN(DaiRdataKnown_A, dai_rdata_o) + `ASSERT_KNOWN(OtpReqKnown_A, otp_req_o) + `ASSERT_KNOWN(OtpCmdKnown_A, otp_cmd_o) + `ASSERT_KNOWN(OtpSizeKnown_A, otp_size_o) + `ASSERT_KNOWN(OtpWdataKnown_A, otp_wdata_o) + `ASSERT_KNOWN(OtpAddrKnown_A, otp_addr_o) + `ASSERT_KNOWN(ScrmblMtxReqKnown_A, scrmbl_mtx_req_o) + `ASSERT_KNOWN(ScrmblCmdKnown_A, scrmbl_cmd_o) + `ASSERT_KNOWN(ScrmblModeKnown_A, scrmbl_mode_o) + `ASSERT_KNOWN(ScrmblSelKnown_A, scrmbl_sel_o) + `ASSERT_KNOWN(ScrmblDataKnown_A, scrmbl_data_o) + `ASSERT_KNOWN(ScrmblValidKnown_A, scrmbl_valid_o) + + // OTP error response + `ASSERT(OtpErrorState_A, + state_q inside {InitOtpSt, ReadWaitSt, WriteWaitSt, DigReadWaitSt} && otp_rvalid_i && + !(otp_err inside {NoError, MacroEccCorrError, MacroWriteBlankError}) + |=> + state_q == ErrorSt && error_o == $past(otp_err)) + +endmodule : otp_ctrl_dai diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_ecc_reg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_ecc_reg.sv new file mode 100644 index 00000000000..2199a7cc602 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_ecc_reg.sv @@ -0,0 +1,105 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register file for buffered OTP partitions. ECC is used to detect up +// to two simultaneous errors within each 64bit word. + +`include "prim_assert.sv" + +module otp_ctrl_ecc_reg #( + parameter int Width = 64, // bit + parameter int Depth = 128, + localparam int Aw = prim_util_pkg::vbits(Depth) // derived parameter +) ( + input logic clk_i, + input logic rst_ni, + + input logic wren_i, + input logic [Aw-1:0] addr_i, + input logic [Width-1:0] wdata_i, + output logic [Width-1:0] rdata_o, + + // Concurrent output of the register state. + output logic [Depth-1:0][Width-1:0] data_o, + // Concurrent ECC check error is flagged via this signal. + output logic ecc_err_o +); + + // Integration checks for parameters. + `ASSERT_INIT(WidthMustBe64bit_A, Width == 64) + + localparam int EccWidth = 8; + + logic [Depth-1:0][Width-1:0] data_d, data_q; + logic [Depth-1:0][EccWidth-1:0] ecc_d, ecc_q; + logic [Width+EccWidth-1:0] ecc_enc; + + // Only one encoder is needed. + prim_secded_inv_72_64_enc u_prim_secded_inv_72_64_enc ( + .data_i(wdata_i), + .data_o(ecc_enc) + ); + + if (Depth == 1) begin : gen_one_word_only + always_comb begin : p_write + data_o = data_q; + data_d = data_q; + ecc_d = ecc_q; + + rdata_o = '0; + if (32'(addr_i) < Depth) begin + rdata_o = data_q[0]; + if (wren_i) begin + {ecc_d[0], data_d[0]} = ecc_enc; + end + end + end + end else begin : gen_multiple_words + always_comb begin : p_write + data_o = data_q; + data_d = data_q; + ecc_d = ecc_q; + + rdata_o = '0; + if (32'(addr_i) < Depth) begin + rdata_o = data_q[addr_i]; + if (wren_i) begin + {ecc_d[addr_i], data_d[addr_i]} = ecc_enc; + end + end + end + end + + // Concurrent ECC checks. + logic [Depth-1:0][1:0] err; + for (genvar k = 0; k < Depth; k++) begin : gen_ecc_dec + prim_secded_inv_72_64_dec u_prim_secded_inv_72_64_dec ( + .data_i({ecc_q[k], data_q[k]}), + // We only rely on the error detection mechanism, + // and not on error correction. + .data_o(), + .syndrome_o(), + .err_o(err[k]) + ); + end + + assign ecc_err_o = |err; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + ecc_q <= {Depth{prim_secded_pkg::SecdedInv7264ZeroEcc}}; + data_q <= '0; + end else begin + ecc_q <= ecc_d; + data_q <= data_d; + end + end + + `ASSERT_KNOWN(EccKnown_A, ecc_q) + `ASSERT_KNOWN(DataKnown_A, data_q) + `ASSERT_KNOWN(RDataOutKnown_A, rdata_o) + `ASSERT_KNOWN(DataOutKnown_A, data_o) + `ASSERT_KNOWN(EccErrKnown_A, ecc_err_o) + +endmodule : otp_ctrl_ecc_reg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv new file mode 100644 index 00000000000..8e2b4ed7aca --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_kdi.sv @@ -0,0 +1,558 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Scrambling key derivation module for OTP. +// + +`include "prim_flop_macros.sv" + +module otp_ctrl_kdi + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import otp_ctrl_top_specific_pkg::*; +#( + parameter scrmbl_key_init_t RndCnstScrmblKeyInit = RndCnstScrmblKeyInitDefault +) ( + input clk_i, + input rst_ni, + // Pulse to enable this module after OTP partitions have + // been initialized. + input kdi_en_i, + // Escalation input. This moves the FSM into a terminal state. + input lc_ctrl_pkg::lc_tx_t escalate_en_i, + // FSM is in error state + output logic fsm_err_o, + // Key seed inputs from OTP + input logic scrmbl_key_seed_valid_i, + input logic [SramKeySeedWidth-1:0] sram_data_key_seed_i, + // EDN interface for requesting entropy + output logic edn_req_o, + input edn_ack_i, + input [EdnDataWidth-1:0] edn_data_i, + // Scrambling key requests + input sram_otp_key_req_t [NumSramKeyReqSlots-1:0] sram_otp_key_i, + output sram_otp_key_rsp_t [NumSramKeyReqSlots-1:0] sram_otp_key_o, + input otbn_otp_key_req_t otbn_otp_key_i, + output otbn_otp_key_rsp_t otbn_otp_key_o, + // Scrambling mutex request + output logic scrmbl_mtx_req_o, + input scrmbl_mtx_gnt_i, + // Scrambling datapath interface + output otp_scrmbl_cmd_e scrmbl_cmd_o, + output digest_mode_e scrmbl_mode_o, + output logic [ConstSelWidth-1:0] scrmbl_sel_o, + output logic [ScrmblBlockWidth-1:0] scrmbl_data_o, + output logic scrmbl_valid_o, + input logic scrmbl_ready_i, + input logic scrmbl_valid_i, + input logic [ScrmblBlockWidth-1:0] scrmbl_data_i +); + + import prim_util_pkg::vbits; + + //////////////////////// + // Integration Checks // + //////////////////////// + + // OTBN + SRAM slots + localparam int NumReq = 1 + NumSramKeyReqSlots; + // Make sure key sizes in the system are multiples of 64bit and not larger than 256bit. + `ASSERT_INIT(KeyNonceSize1_A, (SramKeySeedWidth <= 256) && ((SramKeySeedWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize3_A, (SramKeyWidth <= 256) && ((SramKeyWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize4_A, (SramNonceWidth <= 256) && ((SramNonceWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize5_A, (OtbnKeyWidth <= 256) && ((OtbnKeyWidth % 64) == 0)) + `ASSERT_INIT(KeyNonceSize6_A, (OtbnNonceWidth <= 256) && ((OtbnNonceWidth % 64) == 0)) + + // Make sure EDN interface has compatible width. + `ASSERT_INIT(EntropyWidthDividesDigestBlockWidth_A, (ScrmblKeyWidth % EdnDataWidth) == 0) + + // Currently the assumption is that the SRAM nonce is the widest. + `ASSERT_INIT(NonceWidth_A, NumNonceChunks * ScrmblBlockWidth == SramNonceWidth) + + /////////////////////////////////// + // Input Mapping and Arbitration // + /////////////////////////////////// + + // The key derivation and token hashing functions are aligned such that 2 x 128bit key + // seeds / token blocks are processed in two subsequent steps using the digest primitive. + // This effectively compresses these blocks down into 2 x 64bit blocks, thereby creating + // one 128bit key or token output. + // + // The same FSM is shared among the different flavors of key derivation and token + // hashing functions, and the following configuration options are available: + // + // 1) ingest an additional 128bit entropy block after ingesting a 128bit key seed. + // 2) keep digest state after producing the first 64bit block instead of reverting to the IV. + // 3) netlist constant index. + // 4) fetch additional entropy for the nonce output. + // 5) whether or not the key seed is valid. if not, it will be defaulted to '0. + // 6) 256bit key seed / token input. + // + // The configuration options are set further below, depending on the request type. + + typedef struct packed { + logic ingest_entropy; // 1) + logic chained_digest; // 2) + digest_sel_e digest_sel; // 3) + logic fetch_nonce; // 4) + logic [1:0] nonce_size; // 4) + logic seed_valid; // 5) + logic [3:0][ScrmblBlockWidth-1:0] seed; // 6) + } req_bundle_t; + + logic [NumReq-1:0] req, gnt; + req_bundle_t req_bundles [NumReq]; + + assign req[0] = otbn_otp_key_i.req; + + assign otbn_otp_key_o.ack = gnt[0]; + + // anchored seeds + logic [SramKeySeedWidth-1:0] sram_data_key_seed; + + + prim_sec_anchor_buf #( + .Width(SramKeySeedWidth) + ) u_sram_data_key_anchor ( + .in_i(sram_data_key_seed_i), + .out_o(sram_data_key_seed) + ); + + // OTBN key + assign req_bundles[0] = '{ingest_entropy: 1'b1, // ingest random data + chained_digest: 1'b0, // revert to netlist IV between blocks + digest_sel: SramDataKey, + fetch_nonce: 1'b1, // fetch nonce + nonce_size: 2'(OtbnNonceWidth/EdnDataWidth-1), + seed_valid: scrmbl_key_seed_valid_i, + seed: {sram_data_key_seed, // reuse same seed + sram_data_key_seed}}; + + // SRAM keys + for (genvar k = 1; k < NumReq; k++) begin : gen_req_assign + assign req[k] = sram_otp_key_i[k-1].req; + assign sram_otp_key_o[k-1].ack = gnt[k]; + assign req_bundles[k] = '{ingest_entropy: 1'b1, // ingest random data + chained_digest: 1'b0, // revert to netlist IV between blocks + digest_sel: SramDataKey, + fetch_nonce: 1'b1, // fetch nonce + nonce_size: 2'(SramNonceWidth/EdnDataWidth-1), + seed_valid: scrmbl_key_seed_valid_i, + seed: {sram_data_key_seed, // reuse same seed + sram_data_key_seed}}; + end + + // This arbitrates among incoming key derivation requests on a + // round robin basis to prevent deadlock. + logic req_valid, req_ready; + req_bundle_t req_bundle; + + prim_arbiter_tree #( + .N(NumReq), + .DW($bits(req_bundle_t))) + u_req_arb ( + .clk_i, + .rst_ni, + .req_chk_i ( 1'b1 ), + .req_i ( req ), + .data_i ( req_bundles ), + .gnt_o ( gnt ), + .idx_o ( ), + .valid_o ( req_valid ), + .data_o ( req_bundle ), + .ready_i ( req_ready ) + ); + + ////////////////////////////// + // Temporary Regs and Muxes // + ////////////////////////////// + + localparam int CntWidth = 2; + logic seed_cnt_clr, seed_cnt_en, entropy_cnt_clr, entropy_cnt_en, seed_cnt_err, entropy_cnt_err; + logic [CntWidth-1:0] seed_cnt, entropy_cnt; + + // SEC_CM: KDI_SEED.CTR.REDUN + prim_count #( + .Width(CntWidth) + ) u_prim_count_seed ( + .clk_i, + .rst_ni, + .clr_i(seed_cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(seed_cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(seed_cnt), + .cnt_after_commit_o(), + .err_o(seed_cnt_err) + ); + + // SEC_CM: KDI_ENTROPY.CTR.REDUN + prim_count #( + .Width(CntWidth) + ) u_prim_count_entropy ( + .clk_i, + .rst_ni, + .clr_i(entropy_cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(entropy_cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(entropy_cnt), + .cnt_after_commit_o(), + .err_o(entropy_cnt_err) + ); + + logic seed_valid_reg_en; + logic key_reg_en, nonce_reg_en; + logic seed_valid_d, seed_valid_q; + logic [ScrmblKeyWidth/ScrmblBlockWidth-1:0][ScrmblBlockWidth-1:0] key_out_d, key_out_q; + logic [NumNonceChunks-1:0][ScrmblBlockWidth-1:0] nonce_out_d, nonce_out_q; + + always_comb begin : p_outregs + key_out_d = key_out_q; + nonce_out_d = nonce_out_q; + seed_valid_d = seed_valid_q; + if (key_reg_en) begin + key_out_d[seed_cnt[1]] = scrmbl_data_i; + end + if (nonce_reg_en) begin + nonce_out_d[entropy_cnt[$clog2(NumNonceChunks)-1:0]] = edn_data_i; + end + if (seed_valid_reg_en) begin + seed_valid_d = req_bundle.seed_valid; + end + end + + // Connect keys/nonce outputs to output regs. + prim_sec_anchor_flop #( + .Width(ScrmblKeyWidth), + .ResetValue(RndCnstScrmblKeyInit.key) + ) u_key_out_anchor ( + .clk_i, + .rst_ni, + .d_i(key_out_d), + .q_o(key_out_q) + ); + + assign otbn_otp_key_o.key = key_out_q; + assign otbn_otp_key_o.nonce = nonce_out_q[OtbnNonceSel-1:0]; + assign otbn_otp_key_o.seed_valid = seed_valid_q; + + for (genvar k = 0; k < NumSramKeyReqSlots; k++) begin : gen_out_assign + assign sram_otp_key_o[k].key = key_out_q; + assign sram_otp_key_o[k].nonce = nonce_out_q[SramNonceSel-1:0]; + assign sram_otp_key_o[k].seed_valid = seed_valid_q; + end + + typedef enum logic { + SeedData, + EntropyData + } data_sel_e; + + // Select correct 64bit block. + data_sel_e data_sel; + assign scrmbl_data_o = (data_sel == EntropyData) ? nonce_out_q[entropy_cnt[0]] : + // Gate seed value to '0 if invalid. + (req_bundle.seed_valid) ? req_bundle.seed[seed_cnt] : '0; + + ///////////////// + // Control FSM // + ///////////////// + + // SEC_CM: KDI.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 11 -n 10 \ + // -s 2544133835 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (54.55%) + // 6: |||||||||||||||| (45.45%) + // 7: -- + // 8: -- + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 9 + // + localparam int StateWidth = 10; + typedef enum logic [StateWidth-1:0] { + ResetSt = 10'b0101100001, + IdleSt = 10'b0001011011, + DigClrSt = 10'b1101010110, + DigLoadSt = 10'b0010110111, + FetchEntropySt = 10'b1000001101, + DigEntropySt = 10'b0100111100, + DigFinSt = 10'b1000100010, + DigWaitSt = 10'b1110010001, + FetchNonceSt = 10'b0011000100, + FinishSt = 10'b1011111000, + ErrorSt = 10'b1111101111 + } state_e; + + state_e state_d, state_q; + logic edn_req_d, edn_req_q; + assign edn_req_o = edn_req_q; + + always_comb begin : p_fsm + state_d = state_q; + + // FSM Error output + fsm_err_o = 1'b0; + + // Counters + seed_cnt_en = 1'b0; + seed_cnt_clr = 1'b0; + entropy_cnt_en = 1'b0; + entropy_cnt_clr = 1'b0; + + // EDN 128bit block fetch request. + // This keeps the request alive until it has + // been acked to adhere to the req/ack protocol + // even in cases where the FSM jumps into + // an error state while waiting for a request. + edn_req_d = edn_req_q & ~edn_ack_i; + + // Data selection and temp registers + data_sel = SeedData; + key_reg_en = 1'b0; + nonce_reg_en = 1'b0; + seed_valid_reg_en = 1'b0; + + // Scrambling datapath + scrmbl_mtx_req_o = 1'b0; + scrmbl_sel_o = req_bundle.digest_sel; + scrmbl_cmd_o = LoadShadow; + scrmbl_mode_o = StandardMode; + + scrmbl_valid_o = 1'b0; + + // Request acknowledgement + req_ready = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // State right after reset. Wait here until KDI gets enabled. + ResetSt: begin + if (kdi_en_i) begin + state_d = IdleSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for a request, then go and acquire the mutex. + IdleSt: begin + if (req_valid) begin + state_d = DigClrSt; + seed_cnt_clr = 1'b1; + entropy_cnt_clr = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // First, acquire the mutex for the digest and clear the digest state. + DigClrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + // Need to reset the digest state and set digest mode to "standard". + scrmbl_cmd_o = DigestInit; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = DigLoadSt; + end + end + /////////////////////////////////////////////////////////////////// + // Load two 64bit blocks of the seed, and trigger digest calculation. + DigLoadSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + // Trigger digest round in case this is the second block in a row. + if (seed_cnt[0]) begin + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + // Go and ingest a block of entropy if required. + if (req_bundle.ingest_entropy) begin + state_d = FetchEntropySt; + // Otherwise go to digest finalization state. + end else begin + state_d = DigFinSt; + end + end + // Just load first 64bit block and stay here. + end else if (scrmbl_ready_i) begin + seed_cnt_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Fetch random data to ingest for key derivation. + FetchEntropySt: begin + scrmbl_mtx_req_o = 1'b1; + edn_req_d = 1'b1; + if (edn_ack_i) begin + nonce_reg_en = 1'b1; + // Finished, go and acknowledge this request. + if (entropy_cnt == 2'h1) begin + state_d = DigEntropySt; + entropy_cnt_clr = 1'b1; + // Keep on requesting entropy. + end else begin + entropy_cnt_en = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Load two 64bit blocks of entropy data. + DigEntropySt: begin + scrmbl_mtx_req_o = 1'b1; + data_sel = EntropyData; + scrmbl_valid_o = 1'b1; + // Trigger digest round in case this is the second block in a row, + // and go to digest finalization. + if (entropy_cnt[0]) begin + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + state_d = DigFinSt; + entropy_cnt_clr = 1'b1; + end + // Just load first 64bit block and stay here. + end else if (scrmbl_ready_i) begin + entropy_cnt_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Trigger digest finalization and go wait for the result. + DigFinSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = DigestFinalize; + if (scrmbl_ready_i) begin + state_d = DigWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the digest to return, and write the result to the key + // output register. Go back and process the second part of the + // input seed if needed. + DigWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + if (scrmbl_valid_i) begin + key_reg_en = 1'b1; + // Not finished yet, need to go back and produce second 64bit block. + if (seed_cnt == 2'h1) begin + seed_cnt_en = 1'b1; + // In this case the previous digest state is kept, + // which leads to a chained digest. + if (req_bundle.chained_digest) begin + state_d = DigLoadSt; + // In this case we revert the digest state to the netlist IV. + end else begin + state_d = DigClrSt; + end + // This was the second 64bit output block. + end else begin + seed_cnt_clr = 1'b1; + // Make sure we output the status of the key seed in OTP. + seed_valid_reg_en = 1'b1; + // Check whether we need to fetch additional nonce data. + if (req_bundle.fetch_nonce) begin + state_d = FetchNonceSt; + end else begin + // Finished, go and acknowledge this request. + state_d = FinishSt; + end + end + end + end + /////////////////////////////////////////////////////////////////// + // Fetch additional nonce data. Note that the mutex is released in + // this state. + FetchNonceSt: begin + edn_req_d = 1'b1; + if (edn_ack_i) begin + nonce_reg_en = 1'b1; + // Finished, go and acknowledge this request. + if (entropy_cnt == req_bundle.nonce_size) begin + state_d = FinishSt; + entropy_cnt_clr = 1'b1; + // Keep on requesting entropy. + end else begin + entropy_cnt_en = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Acknowledge request and go back to IdleSt. + FinishSt: begin + state_d = IdleSt; + req_ready = 1'b1; + end + /////////////////////////////////////////////////////////////////// + // Terminal error state. This raises an alert. + ErrorSt: begin + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + // This should never happen, hence we directly jump into the + // error state, where an alert will be triggered. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation. + // SEC_CM: KDI.FSM.LOCAL_ESC, KDI.FSM.GLOBAL_ESC + if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || + seed_cnt_err || entropy_cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + end + + /////////////// + // Registers // + /////////////// + + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + nonce_out_q <= RndCnstScrmblKeyInit.nonce; + seed_valid_q <= 1'b0; + edn_req_q <= 1'b0; + end else begin + nonce_out_q <= nonce_out_d; + seed_valid_q <= seed_valid_d; + edn_req_q <= edn_req_d; + end + end + + //////////////// + // Assertions // + //////////////// + + `ASSERT_KNOWN(FsmErrKnown_A, fsm_err_o) + `ASSERT_KNOWN(EdnReqKnown_A, edn_req_o) + `ASSERT_KNOWN(SramOtpKeyRspKnown_A, sram_otp_key_o) + `ASSERT_KNOWN(OtbnOtpKeyRspKnown_A, otbn_otp_key_o) + `ASSERT_KNOWN(ScrmblMtxReqKnown_A, scrmbl_mtx_req_o) + `ASSERT_KNOWN(ScrmblCmdKnown_A, scrmbl_cmd_o) + `ASSERT_KNOWN(ScrmblModeKnown_A, scrmbl_mode_o) + `ASSERT_KNOWN(ScrmblSelKnown_A, scrmbl_sel_o) + `ASSERT_KNOWN(ScrmblDataKnown_A, scrmbl_data_o) + `ASSERT_KNOWN(ScrmblValidKnown_A, scrmbl_valid_o) + +endmodule : otp_ctrl_kdi diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_lci.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_lci.sv new file mode 100644 index 00000000000..f15e49eb781 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_lci.sv @@ -0,0 +1,304 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Life cycle interface for performing life cycle transitions in OTP. +// + +`include "prim_flop_macros.sv" + +module otp_ctrl_lci + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import otp_ctrl_macro_pkg::OtpAddrShift; + import otp_ctrl_macro_pkg::OtpAddrWidth; + import otp_ctrl_macro_pkg::OtpIfWidth; + import otp_ctrl_macro_pkg::OtpSizeWidth; + import otp_ctrl_macro_pkg::OtpWidth; + import otp_ctrl_top_specific_pkg::*; +#( + // Lifecycle partition information + parameter part_info_t Info = PartInfoDefault +) ( + input clk_i, + input rst_ni, + input lci_en_i, + // Escalation input. This moves the FSM into a terminal state and locks down + // the partition. + input lc_ctrl_pkg::lc_tx_t escalate_en_i, + // Life cycle transition request. In order to perform a state transition, + // the LC controller signals the new count and state. The OTP wrapper then + // only programs bits that have not been programmed before. + // Note that a transition request will fail if the request attempts to + // clear already programmed bits within OTP. + input lc_req_i, + input logic [Info.size*8-1:0] lc_data_i, + output logic lc_ack_o, + output logic lc_err_o, + // Output error state of partition, to be consumed by OTP error/alert logic. + // Note that most errors are not recoverable and move the partition FSM into + // a terminal error state. + output otp_err_e error_o, + // This error signal is pulsed high if the FSM has been glitched into an invalid state. + // Although it is somewhat redundant with the error code in error_o above, it is + // meant to cover cases where we already latched an error code while the FSM is + // glitched into an invalid state (since in that case, the error code will not be + // overridden with the FSM error code so that the original error code is still + // discoverable). + output logic fsm_err_o, + output logic lci_prog_idle_o, + // OTP interface + output logic otp_req_o, + output otp_ctrl_macro_pkg::cmd_e otp_cmd_o, + output logic [OtpSizeWidth-1:0] otp_size_o, + output logic [OtpIfWidth-1:0] otp_wdata_o, + output logic [OtpAddrWidth-1:0] otp_addr_o, + input otp_gnt_i, + input otp_rvalid_i, + input [ScrmblBlockWidth-1:0] otp_rdata_i, + input otp_ctrl_macro_pkg::err_e otp_err_i +); + + //////////////////////// + // Integration Checks // + //////////////////////// + + import prim_util_pkg::vbits; + + localparam int NumLcOtpWords = int'(Info.size) >> OtpAddrShift; + localparam int CntWidth = vbits(NumLcOtpWords); + + localparam int unsigned LastLcOtpWordInt = NumLcOtpWords - 1; + localparam bit [CntWidth-1:0] LastLcOtpWord = LastLcOtpWordInt[CntWidth-1:0]; + + // This is required, since each native OTP word can only be programmed once. + `ASSERT_INIT(LcValueMustBeWiderThanNativeOtpWidth_A, lc_ctrl_state_pkg::LcValueWidth >= OtpWidth) + + //////////////////// + // Controller FSM // + //////////////////// + + // SEC_CM: LCI.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ + // -s 558234734 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 7 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + ResetSt = 9'b000101011, + IdleSt = 9'b110011110, + WriteSt = 9'b101010001, + WriteWaitSt = 9'b010000000, + ErrorSt = 9'b011111101 + } state_e; + + state_e state_d, state_q; + logic cnt_clr, cnt_en, cnt_err; + logic [CntWidth-1:0] cnt; + otp_err_e error_d, error_q; + + // Output LCI errors + assign error_o = error_q; + + always_comb begin : p_fsm + state_d = state_q; + + // Counter + cnt_en = 1'b0; + cnt_clr = 1'b0; + + // Idle status + lci_prog_idle_o = 1'b1; + + // OTP signals + otp_req_o = 1'b0; + otp_cmd_o = otp_ctrl_macro_pkg::Read; + + // Response to LC controller + lc_err_o = 1'b0; + lc_ack_o = 1'b0; + + // Error Register + error_d = error_q; + fsm_err_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // State right after reset. Wait here until LCI gets enabled. + ResetSt: begin + lci_prog_idle_o = 1'b0; + if (lci_en_i) begin + state_d = IdleSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for a request from the life cycle controller + IdleSt: begin + if (lc_req_i) begin + state_d = WriteSt; + cnt_clr = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Loop through the lifecycle sate and burn in all words. + // If the write data contains a 0 bit in a position where a bit has already been + // programmed to 1 before, the OTP errors out. + WriteSt: begin + otp_req_o = 1'b1; + otp_cmd_o = otp_ctrl_macro_pkg::Write; + lci_prog_idle_o = 1'b0; + if (otp_gnt_i) begin + state_d = WriteWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response, and check whether there are more words to burn in. + // In case an OTP transaction fails, latch the OTP error code, and jump to + // terminal error state. + WriteWaitSt: begin + lci_prog_idle_o = 1'b0; + if (otp_rvalid_i) begin + // Check OTP return code. + // Note that if errors occur, we aggregate the error code + // but still attempt to program all remaining words. + // This is done to ensure that a life cycle state with + // ECC correctable errors in some words can still be scrapped. + if (otp_err_e'(otp_err_i) != NoError) begin + error_d = otp_err_e'(otp_err_i); + end + + // Check whether we programmed all OTP words. + // If yes, we are done and can go back to idle. + if (cnt == LastLcOtpWord) begin + state_d = IdleSt; + lc_ack_o = 1'b1; + // If in any of the words a programming error has occurred, + // we signal that accordingly and go to the error state. + if (error_d != NoError) begin + lc_err_o = 1'b1; + state_d = ErrorSt; + end + // Otherwise we increase the OTP word counter. + end else begin + state_d = WriteSt; + cnt_en = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Terminal Error State. This locks access to the partition. + // Make sure the partition signals an error state if no error + // code has been latched so far, and lock the buffer regs down. + ErrorSt: begin + if (error_q == NoError) begin + error_d = FsmStateError; + end + end + /////////////////////////////////////////////////////////////////// + // We should never get here. If we do (e.g. via a malicious + // glitch), error out immediately. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation. + // SEC_CM: LCI.FSM.LOCAL_ESC, LCI.FSM.GLOBAL_ESC + if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + if (error_q == NoError) begin + error_d = FsmStateError; + end + end + + end + + ////////////////////////////// + // Counter and address calc // + ////////////////////////////// + + // Native OTP word counter + // SEC_CM: LCI.CTR.REDUN + prim_count #( + .Width(CntWidth) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + // The output address is "offset + count", but we have to convert Info.offset from a byte address + // to a halfword (16-bit) address by discarding the bottom OtpAddrShift bits. We also make the + // zero-extension of cnt explicit (to avoid width mismatch warnings). + assign otp_addr_o = Info.offset[OtpByteAddrWidth-1:OtpAddrShift] + OtpAddrWidth'(cnt); + + // Always transfer 16bit blocks. + assign otp_size_o = '0; + + logic [NumLcOtpWords-1:0][OtpWidth-1:0] data; + assign data = lc_data_i; + assign otp_wdata_o = (otp_req_o) ? OtpIfWidth'(data[cnt]) : '0; + + logic unused_rdata; + assign unused_rdata = ^otp_rdata_i; + + /////////////// + // Registers // + /////////////// + + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + error_q <= NoError; + end else begin + error_q <= error_d; + end + end + + //////////////// + // Assertions // + //////////////// + + `ASSERT_KNOWN(LcAckKnown_A, lc_ack_o) + `ASSERT_KNOWN(LcErrKnown_A, lc_err_o) + `ASSERT_KNOWN(ErrorKnown_A, error_o) + `ASSERT_KNOWN(LciIdleKnown_A, lci_prog_idle_o) + `ASSERT_KNOWN(OtpReqKnown_A, otp_req_o) + `ASSERT_KNOWN(OtpCmdKnown_A, otp_cmd_o) + `ASSERT_KNOWN(OtpSizeKnown_A, otp_size_o) + `ASSERT_KNOWN(OtpWdataKnown_A, otp_wdata_o) + `ASSERT_KNOWN(OtpAddrKnown_A, otp_addr_o) + +endmodule : otp_ctrl_lci diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_lfsr_timer.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_lfsr_timer.sv new file mode 100644 index 00000000000..35bfd24b170 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_lfsr_timer.sv @@ -0,0 +1,398 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements the LFSR timer for triggering periodic consistency and integrity checks in +// OTP. In particular, this module contains two 40bit counters (one for the consistency and one +// for the integrity checks) and a 40bit LFSR to draw pseudo random wait counts. +// +// The integ_period_msk_i and cnsty_period_msk_i mask signals are used to mask off the LFSR outputs +// and hence determine the maximum wait count that can be drawn. If these values are set to +// zero, the corresponding timer is disabled. +// +// Once a particular check timer has expired, the module will send out a check request to all +// partitions and wait for an acknowledgment. If a particular partition encounters an integrity or +// consistency mismatch, this will be directly reported via the error and alert logic. +// +// In order to guard against wedged partition controllers or arbitration lock ups due to tampering +// attempts, this check timer module also supports a 32bit timeout that can optionally be +// programmed. If a particular check times out, chk_timeout_o will be asserted, which will raise +// an alert via the error logic. +// +// The EntropyWidth LSBs of the LFSR are reseeded with fresh entropy from EDN once +// LfsrUsageThreshold values have been drawn from the LFSR. +// +// It is also possible to trigger one-off checks via integ_chk_trig_i and cnsty_chk_trig_i. +// This can be useful if SW chooses to leave the periodic checks disabled. +// + +`include "prim_flop_macros.sv" + +module otp_ctrl_lfsr_timer + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_top_specific_pkg::*; +#( + // Compile time random constants, to be overridden by topgen. + parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault, + parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault +) ( + input clk_i, + input rst_ni, + output logic edn_req_o, // request to EDN + input edn_ack_i, // ack from EDN + input [EdnDataWidth-1:0] edn_data_i, // from EDN + input timer_en_i, // enable timer + input otp_prog_busy_i, // indicates whether prog ops are in progress + input integ_chk_trig_i, // one-off trigger for integrity check + input cnsty_chk_trig_i, // one-off trigger for consistency check + output logic chk_pending_o, // indicates whether there are pending checks + input [31:0] timeout_i, // check timeout + input [31:0] integ_period_msk_i, // maximum integrity check mask + input [31:0] cnsty_period_msk_i, // maximum consistency check mask + output logic [NumPart-1:0] integ_chk_req_o, // request to all partitions + output logic [NumPart-1:0] cnsty_chk_req_o, // request to all partitions + input [NumPart-1:0] integ_chk_ack_i, // response from partitions + input [NumPart-1:0] cnsty_chk_ack_i, // response from partitions + input lc_ctrl_pkg::lc_tx_t escalate_en_i, // escalation input, moves FSM into ErrorSt + output logic chk_timeout_o, // a check has timed out + output logic fsm_err_o // the FSM has reached an invalid state +); + + //////////////////// + // Reseed counter // + //////////////////// + + // Count how many times the LFSR has been used to generate a value. + // Once we've reached the limit, we request new entropy from EDN to reseed + // the LFSR. Note that this is not a blocking operation for the timer below. + // I.e., the timer is allowed to continue its operation, and may draw more + // values, even if the EDN reseed request is still in progress. + logic reseed_en, lfsr_en; + logic [$clog2(LfsrUsageThreshold+1)-1:0] reseed_cnt_d, reseed_cnt_q; + assign reseed_cnt_d = (reseed_en) ? '0 : + (edn_req_o) ? reseed_cnt_q : + (lfsr_en) ? reseed_cnt_q + 1'b1 : + reseed_cnt_q; + + assign edn_req_o = (reseed_cnt_q >= LfsrUsageThreshold); + assign reseed_en = edn_req_o & edn_ack_i; + + /////////////////////////// + // Tandem LFSR Instances // + /////////////////////////// + + logic lfsr_err; + logic [LfsrWidth-1:0] entropy; + logic [LfsrWidth-1:0] lfsr_state; + assign entropy = (reseed_en) ? edn_data_i[LfsrWidth-1:0] : '0; + + // We employ two redundant LFSRs to guard against FI attacks. + // If any of the two is glitched and the two LFSR states do not agree, + // the FSM below is moved into a terminal error state. + // SEC_CM: TIMER.LFSR.REDUN + prim_double_lfsr #( + .LfsrDw ( LfsrWidth ), + .EntropyDw ( LfsrWidth ), + .StateOutDw ( LfsrWidth ), + .DefaultSeed ( RndCnstLfsrSeed ), + .StatePermEn ( 1'b1 ), + .StatePerm ( RndCnstLfsrPerm ), + .ExtSeedSVA ( 1'b0 ) + ) u_prim_double_lfsr ( + .clk_i, + .rst_ni, + .seed_en_i ( 1'b0 ), + .seed_i ( '0 ), + .lfsr_en_i ( reseed_en || lfsr_en ), + .entropy_i ( entropy ), + .state_o ( lfsr_state ), + .err_o ( lfsr_err ) + ); + + // Not all entropy bits are used. + logic unused_seed; + assign unused_seed = ^edn_data_i; + + `ASSERT_INIT(EdnIsWideEnough_A, EdnDataWidth >= LfsrWidth) + + ////////////////////////////// + // Tandem Counter Instances // + ////////////////////////////// + + // We employ redundant counters to guard against FI attacks. + // If any of them is glitched and the redundant counter states do not agree, + // the FSM below is moved into a terminal error state. + logic [LfsrWidth-1:0] integ_cnt, cnsty_cnt, integ_cnt_set_val, cnsty_cnt_set_val; + logic [LfsrWidth-1:0] integ_mask, cnsty_mask; + logic integ_set_period, integ_set_timeout, integ_cnt_zero; + logic cnsty_set_period, cnsty_set_timeout, cnsty_cnt_zero; + logic integ_cnt_set, cnsty_cnt_set, integ_cnt_err, cnsty_cnt_err; + logic timeout_zero, integ_msk_zero, cnsty_msk_zero, cnsty_cnt_pause; + + assign timeout_zero = (timeout_i == '0); + assign integ_msk_zero = (integ_period_msk_i == '0); + assign cnsty_msk_zero = (cnsty_period_msk_i == '0); + assign integ_cnt_zero = (integ_cnt == '0); + assign cnsty_cnt_zero = (cnsty_cnt == '0); + + assign integ_cnt_set = integ_set_period || integ_set_timeout; + assign cnsty_cnt_set = cnsty_set_period || cnsty_set_timeout; + + assign integ_mask = {integ_period_msk_i, {LfsrWidth-32{1'b1}}}; + assign cnsty_mask = {cnsty_period_msk_i, {LfsrWidth-32{1'b1}}}; + assign integ_cnt_set_val = (integ_set_period) ? (lfsr_state & integ_mask) : LfsrWidth'(timeout_i); + assign cnsty_cnt_set_val = (cnsty_set_period) ? (lfsr_state & cnsty_mask) : LfsrWidth'(timeout_i); + + // SEC_CM: TIMER_INTEG.CTR.REDUN + prim_count #( + .Width(LfsrWidth) + ) u_prim_count_integ ( + .clk_i, + .rst_ni, + .clr_i(1'b0), + .set_i(integ_cnt_set), + .set_cnt_i(integ_cnt_set_val), + .incr_en_i(1'b0), + .decr_en_i(!integ_cnt_zero), + .step_i(LfsrWidth'(1)), + .commit_i(1'b1), + .cnt_o(integ_cnt), + .cnt_after_commit_o(), + .err_o(integ_cnt_err) + ); + + // SEC_CM: TIMER_CNSTY.CTR.REDUN + prim_count #( + .Width(LfsrWidth) + ) u_prim_count_cnsty ( + .clk_i, + .rst_ni, + .clr_i(1'b0), + .set_i(cnsty_cnt_set), + .set_cnt_i(cnsty_cnt_set_val), + .incr_en_i(1'b0), + .decr_en_i(!cnsty_cnt_zero && !cnsty_cnt_pause), + .step_i(LfsrWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnsty_cnt), + .cnt_after_commit_o(), + .err_o(cnsty_cnt_err) + ); + + ///////////////////// + // Request signals // + ///////////////////// + + logic set_all_integ_reqs, set_all_cnsty_reqs; + logic [NumPart-1:0] integ_chk_req_d, integ_chk_req_q; + logic [NumPart-1:0] cnsty_chk_req_d, cnsty_chk_req_q; + assign integ_chk_req_o = integ_chk_req_q; + assign cnsty_chk_req_o = cnsty_chk_req_q; + assign integ_chk_req_d = (set_all_integ_reqs) ? {NumPart{1'b1}} : + integ_chk_req_q & ~integ_chk_ack_i; + assign cnsty_chk_req_d = (set_all_cnsty_reqs) ? {NumPart{1'b1}} : + cnsty_chk_req_q & ~cnsty_chk_ack_i; + + + // external triggers + logic clr_integ_chk_trig, clr_cnsty_chk_trig; + logic integ_chk_trig_d, integ_chk_trig_q; + logic cnsty_chk_trig_d, cnsty_chk_trig_q; + assign integ_chk_trig_d = (integ_chk_trig_q & ~clr_integ_chk_trig) | integ_chk_trig_i; + assign cnsty_chk_trig_d = (cnsty_chk_trig_q & ~clr_cnsty_chk_trig) | cnsty_chk_trig_i; + + //////////////////////////// + // Ping and Timeout Logic // + //////////////////////////// + + // SEC_CM: TIMER.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ + // -s 628816752 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 4 + // Maximum Hamming weight: 6 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + ResetSt = 9'b100100101, + IdleSt = 9'b001101110, + IntegWaitSt = 9'b010110011, + CnstyWaitSt = 9'b111010110, + ErrorSt = 9'b001011001 + } state_e; + + state_e state_d, state_q; + logic chk_timeout_d, chk_timeout_q; + + assign chk_timeout_o = chk_timeout_q; + + always_comb begin : p_fsm + state_d = state_q; + + // LFSR and counter signals + lfsr_en = 1'b0; + integ_set_period = 1'b0; + cnsty_set_period = 1'b0; + integ_set_timeout = 1'b0; + cnsty_set_timeout = 1'b0; + cnsty_cnt_pause = 1'b0; + + // Requests going to partitions. + set_all_integ_reqs = '0; + set_all_cnsty_reqs = '0; + + // Status signals going to CSRs and error logic. + chk_timeout_d = chk_timeout_q; + chk_pending_o = cnsty_chk_trig_q || integ_chk_trig_q; + fsm_err_o = 1'b0; + + // Clear signals for external triggers + clr_integ_chk_trig = 1'b0; + clr_cnsty_chk_trig = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // Wait until enabled. We never return to this state + // once enabled! + ResetSt: begin + if (timer_en_i) begin + state_d = IdleSt; + lfsr_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait here until one of the two timers expires (if enabled) or if + // a check is triggered externally. + IdleSt: begin + if ((!integ_msk_zero && integ_cnt_zero) || integ_chk_trig_q) begin + state_d = IntegWaitSt; + integ_set_timeout = 1'b1; + set_all_integ_reqs = 1'b1; + clr_integ_chk_trig = integ_chk_trig_q; + end else if ((!cnsty_msk_zero && cnsty_cnt_zero) || cnsty_chk_trig_q) begin + state_d = CnstyWaitSt; + cnsty_set_timeout = 1'b1; + set_all_cnsty_reqs = 1'b1; + clr_cnsty_chk_trig = cnsty_chk_trig_q; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for all the partitions to respond and go back to idle. + // If the timeout is enabled, bail out into terminal error state + // if the timeout counter expires (this will raise an alert). + IntegWaitSt: begin + chk_pending_o = 1'b1; + if (!timeout_zero && integ_cnt_zero) begin + state_d = ErrorSt; + chk_timeout_d = 1'b1; + end else if (integ_chk_req_q == '0) begin + state_d = IdleSt; + // This draws the next wait period. + integ_set_period = 1'b1; + lfsr_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for all the partitions to respond and go back to idle. + // If the timeout is enabled, bail out into terminal error state + // if the timeout counter expires (this will raise an alert). + CnstyWaitSt: begin + chk_pending_o = 1'b1; + // Note that consistency checks go back and read from OTP. Hence, + // life cycle transitions and DAI programming operations + // may interfere with these checks and cause them to take longer + // than typically expected. Therefore, the timeout counter is stopped + // during programming operations. + cnsty_cnt_pause = otp_prog_busy_i; + if (!timeout_zero && cnsty_cnt_zero) begin + state_d = ErrorSt; + chk_timeout_d = 1'b1; + end else if (cnsty_chk_req_q == '0) begin + state_d = IdleSt; + // This draws the next wait period. + cnsty_set_period = 1'b1; + lfsr_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Terminal error state. This raises an alert. + ErrorSt: begin + // Continuously clear pending checks. + clr_integ_chk_trig = 1'b1; + clr_cnsty_chk_trig = 1'b1; + if (!chk_timeout_q) begin + fsm_err_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // This should never happen, hence we directly jump into the + // error state, where an alert will be triggered. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation, + // or if the two LFSR or counter states do not agree. + // SEC_CM: TIMER.FSM.LOCAL_ESC, TIMER.FSM.GLOBAL_ESC + if (lfsr_err || integ_cnt_err || cnsty_cnt_err || + lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + end + + /////////////// + // Registers // + /////////////// + + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + integ_chk_req_q <= '0; + cnsty_chk_req_q <= '0; + chk_timeout_q <= 1'b0; + reseed_cnt_q <= '0; + integ_chk_trig_q <= 1'b0; + cnsty_chk_trig_q <= 1'b0; + end else begin + integ_chk_req_q <= integ_chk_req_d; + cnsty_chk_req_q <= cnsty_chk_req_d; + chk_timeout_q <= chk_timeout_d; + reseed_cnt_q <= reseed_cnt_d; + integ_chk_trig_q <= integ_chk_trig_d; + cnsty_chk_trig_q <= cnsty_chk_trig_d; + end + end + + //////////////// + // Assertions // + //////////////// + + `ASSERT_KNOWN(EdnReqKnown_A, edn_req_o) + `ASSERT_KNOWN(ChkPendingKnown_A, chk_pending_o) + `ASSERT_KNOWN(IntegChkReqKnown_A, integ_chk_req_o) + `ASSERT_KNOWN(CnstyChkReqKnown_A, cnsty_chk_req_o) + `ASSERT_KNOWN(ChkTimeoutKnown_A, chk_timeout_o) + +endmodule : otp_ctrl_lfsr_timer diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_macro_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_macro_pkg.sv new file mode 100644 index 00000000000..7b7ca1b19f1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_macro_pkg.sv @@ -0,0 +1,94 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Common interface definitions for OTP macro. + +package otp_ctrl_macro_pkg; + + ////////////////////////////////////// + // Typedefs for OTP Macro Interface // + ////////////////////////////////////// + + // OTP-macro specific + + // The bit-width of the macro words. + parameter int OtpWidth = 16; + // The total number of words. + parameter int OtpDepth = 8192; + // The macro can transfer up to 4 native words per request, which is encoded + // in 2 bits. + parameter int OtpSizeWidth = 2; + parameter int OtpPwrSeqWidth = 2; + + parameter int OtpAddrWidth = 13; + parameter int OtpIfWidth = 2**OtpSizeWidth*OtpWidth; + // Number of Byte address bits to cut off in order to get the native OTP word address. + parameter int OtpAddrShift = 1; + + typedef logic [OtpSizeWidth-1:0] otp_macro_size_t; + typedef logic [OtpAddrWidth-1:0] otp_macro_addr_t; + typedef logic [OtpIfWidth-1:0] otp_macro_data_t; + + // Command codes + + // The command is sparsely encoded to make it more difficult to tamper with. + parameter int OtpCmdWidth = 7; + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 4 -m 5 -n 7 // -s 696743973 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: |||||||||||||||||||| (100.00%) + // 5: -- + // 6: -- + // 7: -- + // + // Minimum Hamming distance: 4 + // Maximum Hamming distance: 4 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 5 + // + typedef enum logic [OtpCmdWidth-1:0] { + Read = 7'b1000101, + Write = 7'b0110111, + // Raw commands ignore integrity + ReadRaw = 7'b1111001, + WriteRaw = 7'b1100010, + Init = 7'b0101100 + } cmd_e; + parameter int OtpErrWidth = 3; + + // Error codes + typedef enum logic [OtpErrWidth-1:0] { + NoError = 3'h0, + MacroError = 3'h1, + MacroEccCorrError = 3'h2, + MacroEccUncorrError = 3'h3, + MacroWriteBlankError = 3'h4 + } err_e; + + typedef struct packed { + logic valid; + cmd_e cmd; + otp_macro_size_t size; + otp_macro_addr_t addr; + otp_macro_data_t wdata; + } otp_ctrl_macro_req_t; + + typedef struct packed { + logic ready; + logic rvalid; + otp_macro_data_t rdata; + err_e err; + logic fatal_lc_fsm_err; + logic fatal_alert; + logic recov_alert; + } otp_ctrl_macro_rsp_t; + +endpackage : otp_ctrl_macro_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_buf.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_buf.sv new file mode 100644 index 00000000000..ce1e2678091 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_buf.sv @@ -0,0 +1,827 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Buffered partition for OTP controller. +// + +`include "prim_flop_macros.sv" + +module otp_ctrl_part_buf + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import otp_ctrl_macro_pkg::OtpAddrShift; + import otp_ctrl_macro_pkg::OtpAddrWidth; + import otp_ctrl_macro_pkg::OtpIfWidth; + import otp_ctrl_macro_pkg::OtpSizeWidth; + import otp_ctrl_macro_pkg::OtpWidth; + import otp_ctrl_top_specific_pkg::*; +#( + // Partition information. + parameter part_info_t Info = PartInfoDefault, + parameter logic [Info.size*8-1:0] DataDefault = '0 +) ( + input clk_i, + input rst_ni, + // Pulse to start partition initialisation (required once per power cycle). + input init_req_i, + output logic init_done_o, + // Integrity check requests + input integ_chk_req_i, + output logic integ_chk_ack_o, + // Consistency check requests + input cnsty_chk_req_i, + output logic cnsty_chk_ack_o, + // Escalation input. This moves the FSM into a terminal state and locks down + // the partition. + input lc_ctrl_pkg::lc_tx_t escalate_en_i, + // Check bypass enable. This bypasses integrity and consistency checks and + // acknowledges all incoming check requests (only used by life cycle). + input lc_ctrl_pkg::lc_tx_t check_byp_en_i, + // Output error state of partition, to be consumed by OTP error/alert logic. + // Note that most errors are not recoverable and move the partition FSM into + // a terminal error state. + output otp_err_e error_o, + // This error signal is pulsed high if the FSM has been glitched into an invalid state. + // Although it is somewhat redundant with the error code in error_o above, it is + // meant to cover cases where we already latched an error code while the FSM is + // glitched into an invalid state (since in that case, the error code will not be + // overridden with the FSM error code so that the original error code is still + // discoverable). + output logic fsm_err_o, + // Access/lock status + // SEC_CM: ACCESS.CTRL.MUBI + input part_access_t access_i, // runtime lock from CSRs + output part_access_t access_o, + // Buffered 64bit digest output. + output logic [ScrmblBlockWidth-1:0] digest_o, + output logic [Info.size*8-1:0] data_o, + // OTP interface + output logic otp_req_o, + output otp_ctrl_macro_pkg::cmd_e otp_cmd_o, + output logic [OtpSizeWidth-1:0] otp_size_o, + output logic [OtpIfWidth-1:0] otp_wdata_o, + output logic [OtpAddrWidth-1:0] otp_addr_o, + input otp_gnt_i, + input otp_rvalid_i, + input [ScrmblBlockWidth-1:0] otp_rdata_i, + input otp_ctrl_macro_pkg::err_e otp_err_i, + // Scrambling mutex request + output logic scrmbl_mtx_req_o, + input scrmbl_mtx_gnt_i, + // Scrambling datapath interface + output otp_scrmbl_cmd_e scrmbl_cmd_o, + output digest_mode_e scrmbl_mode_o, + output logic [ConstSelWidth-1:0] scrmbl_sel_o, + output logic [ScrmblBlockWidth-1:0] scrmbl_data_o, + output logic scrmbl_valid_o, + input logic scrmbl_ready_i, + input logic scrmbl_valid_i, + input logic [ScrmblBlockWidth-1:0] scrmbl_data_i +); + + //////////////////////// + // Integration Checks // + //////////////////////// + + import prim_mubi_pkg::*; + import prim_util_pkg::vbits; + + localparam int unsigned DigestOffsetInt = (int'(Info.offset) + + int'(Info.size) - ScrmblBlockWidth/8); + localparam int NumScrmblBlocks = int'(Info.size) / (ScrmblBlockWidth/8); + localparam int CntWidth = vbits(NumScrmblBlocks); + + localparam bit [OtpByteAddrWidth-1:0] DigestOffset = DigestOffsetInt[OtpByteAddrWidth-1:0]; + + localparam int unsigned LastScrmblBlockInt = NumScrmblBlocks - 1; + localparam int unsigned PenultimateScrmblBlockInt = NumScrmblBlocks - 2; + localparam bit [CntWidth-1:0] LastScrmblBlock = LastScrmblBlockInt[CntWidth-1:0]; + localparam bit [CntWidth-1:0] PenultimateScrmblBlock = PenultimateScrmblBlockInt[CntWidth-1:0]; + + // Integration checks for parameters. + `ASSERT_INIT(OffsetMustBeBlockAligned_A, (Info.offset % (ScrmblBlockWidth/8)) == 0) + `ASSERT_INIT(SizeMustBeBlockAligned_A, (Info.size % (ScrmblBlockWidth/8)) == 0) + `ASSERT_INIT(DigestOffsetMustBeRepresentable_A, DigestOffsetInt == int'(DigestOffset)) + `ASSERT(ScrambledImpliesDigest_A, Info.secret |-> Info.hw_digest) + `ASSERT(WriteLockImpliesDigest_A, Info.read_lock |-> Info.hw_digest) + `ASSERT(ReadLockImpliesDigest_A, Info.write_lock |-> Info.hw_digest) + + // This feature is only supposed to be used with partitions that are not scrambled + // and that do not have a digest. + `ASSERT(BypassEnable0_A, Info.secret |-> lc_ctrl_pkg::lc_tx_test_false_strict(check_byp_en_i)) + `ASSERT(BypassEnable1_A, Info.hw_digest |-> lc_ctrl_pkg::lc_tx_test_false_strict(check_byp_en_i)) + + /////////////////////// + // OTP Partition FSM // + /////////////////////// + + // SEC_CM: PART.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 16 -n 12 \ + // -s 3370657881 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||| (28.33%) + // 6: |||||||||||||||||||| (38.33%) + // 7: |||||||||| (19.17%) + // 8: ||| (5.83%) + // 9: || (4.17%) + // 10: | (2.50%) + // 11: (0.83%) + // 12: (0.83%) + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 12 + // Minimum Hamming weight: 4 + // Maximum Hamming weight: 8 + // + localparam int StateWidth = 12; + typedef enum logic [StateWidth-1:0] { + ResetSt = 12'b011000001110, + InitSt = 12'b110100100111, + InitWaitSt = 12'b001110110001, + InitDescrSt = 12'b110010000100, + InitDescrWaitSt = 12'b100110101000, + IdleSt = 12'b010101001101, + IntegScrSt = 12'b110101011010, + IntegScrWaitSt = 12'b100010011111, + IntegDigClrSt = 12'b101001000001, + IntegDigSt = 12'b011101100010, + IntegDigPadSt = 12'b001101010111, + IntegDigFinSt = 12'b011011100101, + IntegDigWaitSt = 12'b100011110010, + CnstyReadSt = 12'b000001101011, + CnstyReadWaitSt = 12'b101001111100, + ErrorSt = 12'b010110111110 + } state_e; + + typedef enum logic { + ScrmblData, + OtpData + } data_sel_e; + + typedef enum logic { + PartOffset, + DigOffset + } base_sel_e; + + state_e state_d, state_q; + otp_err_e error_d, error_q; + data_sel_e data_sel; + base_sel_e base_sel; + mubi8_t dout_locked_d, dout_locked_q; + logic [CntWidth-1:0] cnt; + logic cnt_en, cnt_clr, cnt_err; + logic ecc_err; + logic buffer_reg_en; + logic [ScrmblBlockWidth-1:0] data_mux; + + // Output partition error state. + assign error_o = error_q; + + // This partition cannot do any write accesses, hence we tie this + // constantly off. + assign otp_wdata_o = '0; + // Depending on the partition configuration, the wrapper is instructed to ignore integrity + // calculations and checks. To be on the safe side, the partition filters error responses at this + // point and does not report any integrity errors if integrity is disabled. + otp_err_e otp_err; + if (Info.integrity) begin : gen_integrity + assign otp_cmd_o = otp_ctrl_macro_pkg::Read; + assign otp_err = otp_err_e'(otp_err_i); + end else begin : gen_no_integrity + assign otp_cmd_o = otp_ctrl_macro_pkg::ReadRaw; + always_comb begin + if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin + otp_err = NoError; + end else begin + otp_err = otp_err_e'(otp_err_i); + end + end + end + + always_comb begin : p_fsm + state_d = state_q; + + // Redundantly encoded lock signal for buffer regs. + dout_locked_d = dout_locked_q; + + // OTP signals + otp_req_o = 1'b0; + + // Scrambling mutex + scrmbl_mtx_req_o = 1'b0; + + // Scrambling datapath + scrmbl_cmd_o = LoadShadow; + scrmbl_sel_o = CnstyDigest; + scrmbl_mode_o = StandardMode; + scrmbl_valid_o = 1'b0; + + // Counter + cnt_en = 1'b0; + cnt_clr = 1'b0; + base_sel = PartOffset; + + // Buffer register + buffer_reg_en = 1'b0; + data_sel = OtpData; + + // Error Register + error_d = error_q; + fsm_err_o = 1'b0; + + // Integrity/Consistency check responses + cnsty_chk_ack_o = 1'b0; + integ_chk_ack_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // State right after reset. Wait here until we get a an + // initialization request. + ResetSt: begin + if (init_req_i) begin + state_d = InitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Initialization reads out the digest only in unbuffered + // partitions. Wait here until the OTP request has been granted. + // And then wait until the OTP word comes back. + InitSt: begin + otp_req_o = 1'b1; + if (otp_gnt_i) begin + state_d = InitWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and write to buffer register, then go to + // descrambling state. In case an OTP transaction fails, latch the + // OTP error code and jump to a + // terminal error state. + InitWaitSt: begin + if (otp_rvalid_i) begin + buffer_reg_en = 1'b1; + if (otp_err inside {NoError, MacroEccCorrError}) begin + // Once we've read and descrambled the whole partition, we can go to integrity + // verification. Note that the last block is the digest value, which does not + // have to be descrambled. + if (cnt == LastScrmblBlock) begin + state_d = IntegDigClrSt; + // Only need to descramble if this is a scrambled partition. + // Otherwise, we can just go back to InitSt and read the next block. + end else if (Info.secret) begin + state_d = InitDescrSt; + end else begin + state_d = InitSt; + cnt_en = 1'b1; + end + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + end + end + end + /////////////////////////////////////////////////////////////////// + // Descrambling state. This first acquires the scrambling + // datapath mutex. Note that once the mutex is acquired, we have + // exclusive access to the scrambling datapath until we release + // the mutex by deasserting scrmbl_mtx_req_o. + // SEC_CM: SECRET.MEM.SCRAMBLE + InitDescrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Decrypt; + scrmbl_sel_o = Info.key_sel; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = InitDescrWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the descrambled data to return. Note that we release + // the mutex lock upon leaving this state. + // SEC_CM: SECRET.MEM.SCRAMBLE + InitDescrWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_sel_o = Info.key_sel; + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + state_d = InitSt; + buffer_reg_en = 1'b1; + cnt_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Idle state. We basically wait for integrity and consistency check + // triggers in this state. + IdleSt: begin + if (integ_chk_req_i) begin + if (Info.hw_digest) begin + state_d = IntegDigClrSt; + // In case there is nothing to check we can just + // acknowledge the request right away, without going to the + // integrity check. + end else begin + integ_chk_ack_o = 1'b1; + end + end else if (cnsty_chk_req_i) begin + state_d = CnstyReadSt; + cnt_clr = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Read the digest. Wait here until the OTP request has been granted. + // And then wait until the OTP word comes back. + // SEC_CM: PART.DATA_REG.BKGN_CHK + CnstyReadSt: begin + otp_req_o = 1'b1; + // In case this partition has a hardware digest, we only have to read + // and compare the digest value. In that case we select the digest offset here. + // Otherwise we have to read and compare the whole partition, in which case we + // select the partition offset, which is the default assignment of base_sel. + if (Info.hw_digest) begin + base_sel = DigOffset; + end + if (otp_gnt_i) begin + state_d = CnstyReadWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and compare the digest. In case there is + // a mismatch, lock down the partition and go into the terminal error + // state. In case an OTP transaction fails, latch the OTP error code + // and jump to a terminal error state. + // SEC_CM: PART.DATA_REG.BKGN_CHK + CnstyReadWaitSt: begin + if (otp_rvalid_i) begin + if (otp_err inside {NoError, MacroEccCorrError}) begin + // Check whether we need to compare the digest or the full partition + // contents here. + if (Info.hw_digest) begin + // Note that we ignore this check if the digest is still blank. + if (digest_o == data_mux || digest_o == '0) begin + state_d = IdleSt; + cnsty_chk_ack_o = 1'b1; + // Error out and lock the partition if this check fails. + end else begin + state_d = ErrorSt; + error_d = CheckFailError; + // The check has finished and found an error. + cnsty_chk_ack_o = 1'b1; + end + end else begin + // Check whether the read data corresponds with the data buffered in regs. + // Note that this particular check can be bypassed in case a transition is ongoing. + if (scrmbl_data_o == data_mux || + lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)) begin + // Can go back to idle and acknowledge the + // request if this is the last block. + if (cnt == LastScrmblBlock) begin + state_d = IdleSt; + cnsty_chk_ack_o = 1'b1; + // Need to go back and read out more blocks. + end else begin + state_d = CnstyReadSt; + cnt_en = 1'b1; + end + end else begin + state_d = ErrorSt; + error_d = CheckFailError; + // The check has finished and found an error. + cnsty_chk_ack_o = 1'b1; + end + end + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + // The check has finished and found an error. + cnsty_chk_ack_o = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // First, acquire the mutex for the digest and clear the digest state. + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigClrSt: begin + // Check whether this partition requires checking at all. + if (Info.hw_digest) begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + cnt_clr = 1'b1; + // Need to reset the digest state and set it to chained + // mode if this partition is scrambled. + scrmbl_cmd_o = DigestInit; + if (Info.secret) begin + scrmbl_mode_o = ChainedMode; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = IntegScrSt; + end + // If this partition is not scrambled, we can just directly + // jump to the digest state. + end else begin + scrmbl_mode_o = StandardMode; + if (scrmbl_mtx_gnt_i && scrmbl_ready_i) begin + state_d = IntegDigSt; + end + end + // Otherwise, if this partition is not digest protected, + // we can just go to idle, since there is nothing to check. + // Note that we do not come back to this state in case there is no + // digest, and hence it is safe to unlock the buffer regs at this point. + // This is the only way the buffer regs can get unlocked. + end else begin + state_d = IdleSt; + if (mubi8_test_true_strict(dout_locked_q)) begin + dout_locked_d = MuBi8False; + end + end + end + /////////////////////////////////////////////////////////////////// + // Scramble buffered data (which is held in plaintext form). + // This moves the previous scrambling result into the shadow reg + // for later use. + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegScrSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Encrypt; + scrmbl_sel_o = Info.key_sel; + if (scrmbl_ready_i) begin + state_d = IntegScrWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the scrambled data to return. + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegScrWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_sel_o = Info.key_sel; + if (scrmbl_valid_i) begin + state_d = IntegDigSt; + end + end + /////////////////////////////////////////////////////////////////// + // Push the word read into the scrambling datapath. The last + // block is repeated in case the number blocks in this partition + // is odd. + // SEC_CM: PART.MEM.DIGEST + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + if (scrmbl_ready_i) begin + cnt_en = 1'b1; + // No need to digest the digest value itself + if (cnt == PenultimateScrmblBlock) begin + // Note that the digest operates on 128bit blocks since the data is fed in via the + // PRESENT key input. Therefore, we only trigger a digest update on every second + // 64bit block that is pushed into the scrambling datapath. + if (cnt[0]) begin + scrmbl_cmd_o = Digest; + state_d = IntegDigFinSt; + end else begin + state_d = IntegDigPadSt; + cnt_en = 1'b0; + end + end else begin + // Trigger digest round in case this is the second block in a row. + if (cnt[0]) begin + scrmbl_cmd_o = Digest; + end + // Go back and scramble the next data block if this is + // a scrambled partition. Otherwise just stay here. + if (Info.secret) begin + state_d = IntegScrSt; + end + end + end + end + /////////////////////////////////////////////////////////////////// + // Padding state. When we get here, we've copied the last encryption + // result into the shadow register such that we've effectively + // repeated the last block twice in order to pad the data to 128bit. + // SEC_CM: PART.MEM.DIGEST + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigPadSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = Digest; + if (scrmbl_ready_i) begin + state_d = IntegDigFinSt; + end + end + /////////////////////////////////////////////////////////////////// + // Trigger digest finalization and go wait for the result. + // SEC_CM: PART.MEM.DIGEST + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigFinSt: begin + scrmbl_mtx_req_o = 1'b1; + scrmbl_valid_o = 1'b1; + scrmbl_cmd_o = DigestFinalize; + if (scrmbl_ready_i) begin + state_d = IntegDigWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for the digest to return, and double check whether the digest + // matches. If yes, unlock the partition. Otherwise, go into the terminal + // error state, where the partition will be locked down. + // SEC_CM: PART.MEM.DIGEST + // SEC_CM: PART.DATA_REG.BKGN_CHK + IntegDigWaitSt: begin + scrmbl_mtx_req_o = 1'b1; + data_sel = ScrmblData; + if (scrmbl_valid_i) begin + // This is the only way the buffer regs can get unlocked. + // Note that we ignore this check if the digest is still blank. + if (digest_o == data_mux || digest_o == '0) begin + state_d = IdleSt; + // If the partition is still locked, this is the first integrity check after + // initialization. This is the only way the buffer regs can get unlocked. + if (mubi8_test_true_strict(dout_locked_q)) begin + dout_locked_d = MuBi8False; + // Otherwise, this integrity check has requested by the LFSR timer, and we have + // to acknowledge its completion. + end else begin + integ_chk_ack_o = 1'b1; + end + // Error out and lock the partition if this check fails. + end else begin + state_d = ErrorSt; + error_d = CheckFailError; + // The check has finished and found an error. + integ_chk_ack_o = 1'b1; + end + end + end + /////////////////////////////////////////////////////////////////// + // Terminal Error State. This locks access to the partition. + // Make sure the partition signals an error state if no error + // code has been latched so far, and lock the buffer regs down. + ErrorSt: begin + dout_locked_d = MuBi8True; + if (error_q == NoError) begin + error_d = FsmStateError; + end + // If we are in error state, we cannot execute the checks anymore. + // Hence the acknowledgements are returned immediately. + cnsty_chk_ack_o = 1'b1; + integ_chk_ack_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + // We should never get here. If we do (e.g. via a malicious + // glitch), error out immediately. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + + // Unconditionally jump into the terminal error state in case of + // an ECC error or escalation, and lock access to the partition down. + // SEC_CM: PART.FSM.LOCAL_ESC + if (ecc_err) begin + state_d = ErrorSt; + if (state_q != ErrorSt) begin + error_d = CheckFailError; + end + end + // SEC_CM: PART.FSM.LOCAL_ESC, PART.FSM.GLOBAL_ESC + if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + if (state_q != ErrorSt) begin + error_d = FsmStateError; + end + end + end + + //////////////////////////// + // Address Calc and Muxes // + //////////////////////////// + + // Address counter - this is only used for computing a digest, hence the increment is + // fixed to 8 byte. + // SEC_CM: PART.CTR.REDUN + prim_count #( + .Width(CntWidth) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + logic [OtpByteAddrWidth-1:0] addr_base; + assign addr_base = (base_sel == DigOffset) ? DigestOffset : Info.offset; + + // Note that OTP works on halfword (16bit) addresses, hence need to + // shift the addresses appropriately. + logic [OtpByteAddrWidth-1:0] addr_calc; + assign addr_calc = OtpByteAddrWidth'({cnt, {$clog2(ScrmblBlockWidth/8){1'b0}}}) + addr_base; + assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift]; + + if (OtpAddrShift > 0) begin : gen_unused + logic unused_bits; + assign unused_bits = ^addr_calc[OtpAddrShift-1:0]; + end + + // Always transfer 64bit blocks. + assign otp_size_o = OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth) - 1); + + assign data_mux = (data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i; + + ///////////////// + // Buffer Regs // + ///////////////// + + // SEC_CM: PART.DATA_REG.INTEGRITY + logic [Info.size*8-1:0] data; + otp_ctrl_ecc_reg #( + .Width ( ScrmblBlockWidth ), + .Depth ( NumScrmblBlocks ) + ) u_otp_ctrl_ecc_reg ( + .clk_i, + .rst_ni, + .wren_i ( buffer_reg_en ), + .addr_i ( cnt ), + .wdata_i ( data_mux ), + .rdata_o ( scrmbl_data_o ), + .data_o ( data ), + .ecc_err_o ( ecc_err ) + ); + + // We have successfully initialized the partition once it has been unlocked. + assign init_done_o = mubi8_test_false_strict(dout_locked_q); + // Hardware output gating. + // Note that this is decoupled from the DAI access rules further below. + assign data_o = (init_done_o) ? data : DataDefault; + // The digest does not have to be gated. + assign digest_o = data[$high(data_o) -: ScrmblBlockWidth]; + + //////////////////////// + // DAI Access Control // + //////////////////////// + + // Aggregate all possible DAI write /readlocks. The partition is also locked when uninitialized. + // Note that the locks are redundantly encoded values. + part_access_t access_pre; + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock_pre ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(dout_locked_q, access_i.write_lock)), + .mubi_o(access_pre.write_lock) + ); + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock_pre ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(dout_locked_q, access_i.read_lock)), + .mubi_o(access_pre.read_lock) + ); + + // SEC_CM: PART.MEM.SW_UNWRITABLE + if (Info.write_lock) begin : gen_digest_write_lock + mubi8_t digest_locked; + assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; + + // This prevents the synthesis tool from optimizing the multibit signal. + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)), + .mubi_o(access_o.write_lock) + ); + + `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock)) + end else begin : gen_no_digest_write_lock + assign access_o.write_lock = access_pre.write_lock; + end + + // SEC_CM: PART.MEM.SW_UNREADABLE + if (Info.read_lock) begin : gen_digest_read_lock + mubi8_t digest_locked; + assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; + + // This prevents the synthesis tool from optimizing the multibit signal. + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)), + .mubi_o(access_o.read_lock) + ); + + `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock)) + end else begin : gen_no_digest_read_lock + assign access_o.read_lock = access_pre.read_lock; + end + + /////////////// + // Registers // + /////////////// + + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + error_q <= NoError; + // data output is locked by default + dout_locked_q <= MuBi8True; + end else begin + error_q <= error_d; + dout_locked_q <= dout_locked_d; + end + end + + //////////////// + // Assertions // + //////////////// + + // Known assertions + `ASSERT_KNOWN(InitDoneKnown_A, init_done_o) + `ASSERT_KNOWN(IntegChkAckKnown_A, integ_chk_ack_o) + `ASSERT_KNOWN(CnstyChkAckKnown_A, cnsty_chk_ack_o) + `ASSERT_KNOWN(ErrorKnown_A, error_o) + `ASSERT_KNOWN(AccessKnown_A, access_o) + `ASSERT_KNOWN(DigestKnown_A, digest_o) + `ASSERT_KNOWN(DataKnown_A, data_o) + `ASSERT_KNOWN(OtpReqKnown_A, otp_req_o) + `ASSERT_KNOWN(OtpCmdKnown_A, otp_cmd_o) + `ASSERT_KNOWN(OtpSizeKnown_A, otp_size_o) + `ASSERT_KNOWN(OtpWdataKnown_A, otp_wdata_o) + `ASSERT_KNOWN(OtpAddrKnown_A, otp_addr_o) + `ASSERT_KNOWN(ScrmblMtxReqKnown_A, scrmbl_mtx_req_o) + `ASSERT_KNOWN(ScrmblCmdKnown_A, scrmbl_cmd_o) + `ASSERT_KNOWN(ScrmblModeKnown_A, scrmbl_mode_o) + `ASSERT_KNOWN(ScrmblSelKnown_A, scrmbl_sel_o) + `ASSERT_KNOWN(ScrmblDataKnown_A, scrmbl_data_o) + `ASSERT_KNOWN(ScrmblValidKnown_A, scrmbl_valid_o) + + // Uninitialized partitions should always be locked, no matter what. + `ASSERT(InitWriteLocksPartition_A, + mubi8_test_true_loose(dout_locked_q) + |-> + mubi8_test_true_loose(access_o.write_lock)) + `ASSERT(InitReadLocksPartition_A, + mubi8_test_true_loose(dout_locked_q) + |-> + mubi8_test_true_loose(access_o.read_lock)) + // Incoming Lock propagation + `ASSERT(WriteLockPropagation_A, + mubi8_test_true_loose(access_i.write_lock) + |-> + mubi8_test_true_loose(access_o.write_lock)) + `ASSERT(ReadLockPropagation_A, + mubi8_test_true_loose(access_i.read_lock) + |-> + mubi8_test_true_loose(access_o.read_lock)) + // ECC error in buffer regs + `ASSERT(EccErrorState_A, + ecc_err + |=> + state_q == ErrorSt) + // OTP error response + `ASSERT(OtpErrorState_A, + state_q inside {InitWaitSt, CnstyReadWaitSt} && otp_rvalid_i && + !(otp_err inside {NoError, MacroEccCorrError}) && !ecc_err + |=> + state_q == ErrorSt && error_o == $past(otp_err)) + + // The partition size must be greater than one scrambling block for the address calculation + // and muxing to work correctly. + `ASSERT_INIT(OtpPartBufSize_A, Info.size > (ScrmblBlockWidth/8)) + +endmodule : otp_ctrl_part_buf diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv new file mode 100644 index 00000000000..18393d859ba --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv @@ -0,0 +1,993 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Package partition metadata. +// +package otp_ctrl_part_pkg; + + import prim_util_pkg::vbits; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_pkg::*; + import otp_ctrl_top_specific_pkg::*; + + //////////////////////////////////// + // Scrambling Constants and Types // + //////////////////////////////////// + + parameter int NumScrmblKeys = 4; + parameter int NumDigestSets = 2; + + parameter int ScrmblKeySelWidth = vbits(NumScrmblKeys); + parameter int DigestSetSelWidth = vbits(NumDigestSets); + parameter int ConstSelWidth = (ScrmblKeySelWidth > DigestSetSelWidth) ? + ScrmblKeySelWidth : + DigestSetSelWidth; + + typedef enum logic [ConstSelWidth-1:0] { + StandardMode, + ChainedMode + } digest_mode_e; + + typedef logic [NumScrmblKeys-1:0][ScrmblKeyWidth-1:0] key_array_t; + typedef logic [NumDigestSets-1:0][ScrmblKeyWidth-1:0] digest_const_array_t; + typedef logic [NumDigestSets-1:0][ScrmblBlockWidth-1:0] digest_iv_array_t; + + typedef enum logic [ConstSelWidth-1:0] { + Secret0Key, + Secret1Key, + Secret2Key, + Secret3Key + } key_sel_e; + + typedef enum logic [ConstSelWidth-1:0] { + CnstyDigest, + SramDataKey + } digest_sel_e; + + // SEC_CM: SECRET.MEM.SCRAMBLE + parameter key_array_t RndCnstKey = { + 128'hBEAD91D5FA4E09150E95F517CB98955B, + 128'h85A9E830BC059BA9286D6E2856A05CC3, + 128'hEFFA6D736C5EFF49AE7B70F9C46E5A62, + 128'h3BA121C5E097DDEB7768B4C666E9C3DA + }; + + // SEC_CM: PART.MEM.DIGEST + // Note: digest set 0 is used for computing the partition digests. Constants at + // higher indices are used to compute the scrambling keys. + parameter digest_const_array_t RndCnstDigestConst = { + 128'hB7474D640F8A7F5D60822E1FAEC5C72, + 128'hE048B657396B4B83277195FC471E4B26 + }; + + parameter digest_iv_array_t RndCnstDigestIV = { + 64'hB6641214B61D1B43, + 64'h4D5A89AA9109294A + }; + + + ///////////////////////////////////// + // Typedefs for Partition Metadata // + ///////////////////////////////////// + + typedef enum logic [1:0] { + Unbuffered, + Buffered, + LifeCycle + } part_variant_e; + + typedef struct packed { + part_variant_e variant; + // Offset and size within the OTP array, in Bytes. + logic [OtpByteAddrWidth-1:0] offset; + logic [OtpByteAddrWidth-1:0] size; + // Key index to use for scrambling. + key_sel_e key_sel; + // Attributes + logic secret; // Whether the partition is secret (and hence scrambled) + logic sw_digest; // Whether the partition has a software digest + logic hw_digest; // Whether the partition has a hardware digest + logic write_lock; // Whether the partition is write lockable (via digest) + logic read_lock; // Whether the partition is read lockable (via digest) + logic integrity; // Whether the partition is integrity protected + logic iskeymgr_creator; // Whether the partition has any creator key material + logic iskeymgr_owner; // Whether the partition has any owner key material + } part_info_t; + + parameter part_info_t PartInfoDefault = '{ + variant: Unbuffered, + offset: '0, + size: OtpByteAddrWidth'('hFF), + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b0, + write_lock: 1'b0, + read_lock: 1'b0, + integrity: 1'b0, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }; + + //////////////////////// + // Partition Metadata // + //////////////////////// + + localparam part_info_t PartInfo [NumPart] = '{ + // VENDOR_TEST + '{ + variant: Unbuffered, + offset: 14'd0, + size: 64, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b0, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // CREATOR_SW_CFG + '{ + variant: Unbuffered, + offset: 14'd64, + size: 320, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // OWNER_SW_CFG + '{ + variant: Unbuffered, + offset: 14'd384, + size: 632, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // OWNERSHIP_SLOT_STATE + '{ + variant: Unbuffered, + offset: 14'd1016, + size: 48, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b0, + write_lock: 1'b0, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // ROT_CREATOR_AUTH + '{ + variant: Unbuffered, + offset: 14'd1064, + size: 1424, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // ROT_OWNER_AUTH_SLOT0 + '{ + variant: Unbuffered, + offset: 14'd2488, + size: 328, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // ROT_OWNER_AUTH_SLOT1 + '{ + variant: Unbuffered, + offset: 14'd2816, + size: 328, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // PLAT_INTEG_AUTH_SLOT0 + '{ + variant: Unbuffered, + offset: 14'd3144, + size: 328, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // PLAT_INTEG_AUTH_SLOT1 + '{ + variant: Unbuffered, + offset: 14'd3472, + size: 328, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // PLAT_OWNER_AUTH_SLOT0 + '{ + variant: Unbuffered, + offset: 14'd3800, + size: 328, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // PLAT_OWNER_AUTH_SLOT1 + '{ + variant: Unbuffered, + offset: 14'd4128, + size: 328, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // PLAT_OWNER_AUTH_SLOT2 + '{ + variant: Unbuffered, + offset: 14'd4456, + size: 328, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // PLAT_OWNER_AUTH_SLOT3 + '{ + variant: Unbuffered, + offset: 14'd4784, + size: 328, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // EXT_NVM + '{ + variant: Unbuffered, + offset: 14'd5112, + size: 1024, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b0, + write_lock: 1'b0, + read_lock: 1'b0, + integrity: 1'b0, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // ROM_PATCH + '{ + variant: Unbuffered, + offset: 14'd6136, + size: 9848, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b1, + hw_digest: 1'b0, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // HW_CFG0 + '{ + variant: Buffered, + offset: 14'd15984, + size: 72, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // HW_CFG1 + '{ + variant: Buffered, + offset: 14'd16056, + size: 16, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // SECRET0 + '{ + variant: Buffered, + offset: 14'd16072, + size: 40, + key_sel: Secret0Key, + secret: 1'b1, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b1, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // SECRET1 + '{ + variant: Buffered, + offset: 14'd16112, + size: 24, + key_sel: Secret1Key, + secret: 1'b1, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b1, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + }, + // SECRET2 + '{ + variant: Buffered, + offset: 14'd16136, + size: 120, + key_sel: Secret2Key, + secret: 1'b1, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b1, + integrity: 1'b1, + iskeymgr_creator: 1'b1, + iskeymgr_owner: 1'b0 + }, + // SECRET3 + '{ + variant: Buffered, + offset: 14'd16256, + size: 40, + key_sel: Secret3Key, + secret: 1'b1, + sw_digest: 1'b0, + hw_digest: 1'b1, + write_lock: 1'b1, + read_lock: 1'b1, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b1 + }, + // LIFE_CYCLE + '{ + variant: LifeCycle, + offset: 14'd16296, + size: 88, + key_sel: key_sel_e'('0), + secret: 1'b0, + sw_digest: 1'b0, + hw_digest: 1'b0, + write_lock: 1'b0, + read_lock: 1'b0, + integrity: 1'b1, + iskeymgr_creator: 1'b0, + iskeymgr_owner: 1'b0 + } + }; + + typedef enum { + VendorTestIdx, + CreatorSwCfgIdx, + OwnerSwCfgIdx, + OwnershipSlotStateIdx, + RotCreatorAuthIdx, + RotOwnerAuthSlot0Idx, + RotOwnerAuthSlot1Idx, + PlatIntegAuthSlot0Idx, + PlatIntegAuthSlot1Idx, + PlatOwnerAuthSlot0Idx, + PlatOwnerAuthSlot1Idx, + PlatOwnerAuthSlot2Idx, + PlatOwnerAuthSlot3Idx, + ExtNvmIdx, + RomPatchIdx, + HwCfg0Idx, + HwCfg1Idx, + Secret0Idx, + Secret1Idx, + Secret2Idx, + Secret3Idx, + LifeCycleIdx, + // These are not "real partitions", but in terms of implementation it is convenient to + // add these at the end of certain arrays. + DaiIdx, + LciIdx, + KdiIdx, + // Number of agents is the last idx+1. + NumAgentsIdx + } part_idx_e; + + parameter int NumAgents = int'(NumAgentsIdx); + + // Breakout types for easier access of individual items. + typedef struct packed { + logic [63:0] hw_cfg0_digest; + logic [255:0] manuf_state; + logic [255:0] device_id; + } otp_hw_cfg0_data_t; + + // default value used for intermodule + parameter otp_hw_cfg0_data_t OTP_HW_CFG0_DATA_DEFAULT = '{ + hw_cfg0_digest: 64'h8CBBAD02BB4CA928, + manuf_state: 256'h63B9485A3856C417CF7A50A9A91EF7F7B3A5B4421F462370FFF698183664DC7E, + device_id: 256'h90C7F21F6224F027F98C48B1F93772844A22D4B78FE0266FBEE3958332F2939B + }; + typedef struct packed { + logic [63:0] hw_cfg1_digest; + logic [15:0] unallocated; + prim_mubi_pkg::mubi8_t en_sram_ifetch; + prim_mubi_pkg::mubi8_t en_csrng_sw_app_read; + logic [31:0] soc_dbg_state; + } otp_hw_cfg1_data_t; + + // default value used for intermodule + parameter otp_hw_cfg1_data_t OTP_HW_CFG1_DATA_DEFAULT = '{ + hw_cfg1_digest: 64'hAA3F4C71234F097C, + unallocated: 16'h0, + en_sram_ifetch: prim_mubi_pkg::mubi8_t'(8'h69), + en_csrng_sw_app_read: prim_mubi_pkg::mubi8_t'(8'h69), + soc_dbg_state: 32'h0 + }; + typedef struct packed { + // This reuses the same encoding as the life cycle signals for indicating valid status. + lc_ctrl_pkg::lc_tx_t valid; + otp_hw_cfg1_data_t hw_cfg1_data; + otp_hw_cfg0_data_t hw_cfg0_data; + } otp_broadcast_t; + + // default value for intermodule + parameter otp_broadcast_t OTP_BROADCAST_DEFAULT = '{ + valid: lc_ctrl_pkg::Off, + hw_cfg1_data: OTP_HW_CFG1_DATA_DEFAULT, + hw_cfg0_data: OTP_HW_CFG0_DATA_DEFAULT + }; + + + // OTP invalid partition default for buffered partitions. + parameter logic [131071:0] PartInvDefault = 131072'({ + 704'({ + 320'h1136C663A36C3E3E817E760B27AE937BFCDF15A3429452A851B80674A2B6FBE93B61DE417B9FB33, + 384'hD68C96F0B3D1FEED688098A43C33459F0279FC51CC7C626E315FD2B871D88819A0D1E90E8C9FDDFA01E46311FD36D954 + }), + 320'({ + 64'h3BF7D79A9FF747F6, + 256'hD0BAC511D08ECE0E2C0DBDDEDF7A854D5E58D0AA97A0F8F6D3D58610F4851667 + }), + 960'({ + 64'h41837480464544A1, + 256'hE00E9680BD9B70291C752824C7DDC89694CD3DED94B578192A4D8B51F5D41C8A, + 256'h105733EAA3880C5A234729143F97B62A55D0320379A0D260426D99D374E699CA, + 256'hDBC827839FE2DCC27E17D06B5D4E0DDDDBB9844327F20FB5D396D1CE085BDC31, + 128'h711D135F59A50322B6711DB6F5D40A37 + }), + 192'({ + 64'h6FDFE93D3146B0F, + 128'hB5AC1F53D00A08C3B28B5C0FEE5F4C02 + }), + 320'({ + 64'h67BBE3B4555DF35C, + 128'h40119A3C6E63CDF358840E458E4029A6, + 128'hDF3888886BD10DC67ABB319BDA0529AE + }), + 128'({ + 64'hAA3F4C71234F097C, + 16'h0, // unallocated space + 8'h69, + 8'h69, + 32'h0 + }), + 576'({ + 64'h8CBBAD02BB4CA928, + 256'h63B9485A3856C417CF7A50A9A91EF7F7B3A5B4421F462370FFF698183664DC7E, + 256'h90C7F21F6224F027F98C48B1F93772844A22D4B78FE0266FBEE3958332F2939B + }), + 78784'({ + 64'hC469C593E5DC0DA8, + 5184'h0, // unallocated space + {8000'h0, 65536'h0} + }), + 8192'({ + 8192'h0 + }), + 2624'({ + 64'hBE193854E9CA60A0, + 1280'h0, + 1280'h0 + }), + 2624'({ + 64'hBBF4A76885E754F2, + 1280'h0, + 1280'h0 + }), + 2624'({ + 64'hF87BED95CFBA3727, + 1280'h0, + 1280'h0 + }), + 2624'({ + 64'h20440F25BB053FB5, + 1280'h0, + 1280'h0 + }), + 2624'({ + 64'h15F164D7930C9D19, + 1280'h0, + 1280'h0 + }), + 2624'({ + 64'hE29749216775E8A5, + 1280'h0, + 1280'h0 + }), + 2624'({ + 64'h340A5B93BB19342, + 1280'h0, + 1280'h0 + }), + 2624'({ + 64'h4947DD361344767A, + 1280'h0, + 1280'h0 + }), + 11392'({ + 64'hA445C3C29F71A256, + 32'h0, // unallocated space + 6144'h0, + 1280'h0, + 1280'h0, + 1280'h0, + 32'h0, + 1280'h0 + }), + 384'({ + 128'h0, + 128'h0, + 128'h0 + }), + 5056'({ + 64'h3E725E464F593C87, + 128'h0, // unallocated space + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 512'h0, + 128'h0, + 128'h0, + 512'h0, + 3200'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0 + }), + 2560'({ + 64'hCC6596C7174EBA64, + 160'h0, // unallocated space + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 32'h0, + 64'h0, + 32'h0, + 64'h0, + 32'h0, + 32'h0, + 256'h0, + 32'h0, + 992'h0 + }), + 512'({ + 64'h9605F051E74379CB, + 448'h0 + })}); + + /////////////////////////////////////////////// + // Parameterized Assignment Helper Functions // + /////////////////////////////////////////////// + + function automatic otp_ctrl_core_hw2reg_t named_reg_assign( + logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest); + otp_ctrl_core_hw2reg_t hw2reg; + logic unused_sigs; + unused_sigs = ^part_digest; + hw2reg = '0; + hw2reg.vendor_test_digest = part_digest[VendorTestIdx]; + hw2reg.creator_sw_cfg_digest = part_digest[CreatorSwCfgIdx]; + hw2reg.owner_sw_cfg_digest = part_digest[OwnerSwCfgIdx]; + hw2reg.rot_creator_auth_digest = part_digest[RotCreatorAuthIdx]; + hw2reg.rot_owner_auth_slot0_digest = part_digest[RotOwnerAuthSlot0Idx]; + hw2reg.rot_owner_auth_slot1_digest = part_digest[RotOwnerAuthSlot1Idx]; + hw2reg.plat_integ_auth_slot0_digest = part_digest[PlatIntegAuthSlot0Idx]; + hw2reg.plat_integ_auth_slot1_digest = part_digest[PlatIntegAuthSlot1Idx]; + hw2reg.plat_owner_auth_slot0_digest = part_digest[PlatOwnerAuthSlot0Idx]; + hw2reg.plat_owner_auth_slot1_digest = part_digest[PlatOwnerAuthSlot1Idx]; + hw2reg.plat_owner_auth_slot2_digest = part_digest[PlatOwnerAuthSlot2Idx]; + hw2reg.plat_owner_auth_slot3_digest = part_digest[PlatOwnerAuthSlot3Idx]; + hw2reg.rom_patch_digest = part_digest[RomPatchIdx]; + hw2reg.hw_cfg0_digest = part_digest[HwCfg0Idx]; + hw2reg.hw_cfg1_digest = part_digest[HwCfg1Idx]; + hw2reg.secret0_digest = part_digest[Secret0Idx]; + hw2reg.secret1_digest = part_digest[Secret1Idx]; + hw2reg.secret2_digest = part_digest[Secret2Idx]; + hw2reg.secret3_digest = part_digest[Secret3Idx]; + return hw2reg; + endfunction : named_reg_assign + + function automatic part_access_t [NumPart-1:0] named_part_access_pre( + otp_ctrl_core_reg2hw_t reg2hw); + part_access_t [NumPart-1:0] part_access_pre; + logic unused_sigs; + unused_sigs = ^reg2hw; + // Default (this will be overridden by partition-internal settings). + part_access_pre = {{32'(2*NumPart)}{prim_mubi_pkg::MuBi8False}}; + // Note: these could be made a MuBi CSRs in the future. + // The main thing that is missing right now is proper support for W0C. + // VENDOR_TEST + if (!reg2hw.vendor_test_read_lock) begin + part_access_pre[VendorTestIdx].read_lock = prim_mubi_pkg::MuBi8True; + end + // CREATOR_SW_CFG + if (!reg2hw.creator_sw_cfg_read_lock) begin + part_access_pre[CreatorSwCfgIdx].read_lock = prim_mubi_pkg::MuBi8True; + end + // OWNER_SW_CFG + if (!reg2hw.owner_sw_cfg_read_lock) begin + part_access_pre[OwnerSwCfgIdx].read_lock = prim_mubi_pkg::MuBi8True; + end + // OWNERSHIP_SLOT_STATE + if (!reg2hw.ownership_slot_state_read_lock) begin + part_access_pre[OwnershipSlotStateIdx].read_lock = prim_mubi_pkg::MuBi8True; + end + // ROT_CREATOR_AUTH + if (!reg2hw.rot_creator_auth_read_lock) begin + part_access_pre[RotCreatorAuthIdx].read_lock = prim_mubi_pkg::MuBi8True; + end + // ROT_OWNER_AUTH_SLOT0 + if (!reg2hw.rot_owner_auth_slot0_read_lock) begin + part_access_pre[RotOwnerAuthSlot0Idx].read_lock = prim_mubi_pkg::MuBi8True; + end + // ROT_OWNER_AUTH_SLOT1 + if (!reg2hw.rot_owner_auth_slot1_read_lock) begin + part_access_pre[RotOwnerAuthSlot1Idx].read_lock = prim_mubi_pkg::MuBi8True; + end + // PLAT_INTEG_AUTH_SLOT0 + if (!reg2hw.plat_integ_auth_slot0_read_lock) begin + part_access_pre[PlatIntegAuthSlot0Idx].read_lock = prim_mubi_pkg::MuBi8True; + end + // PLAT_INTEG_AUTH_SLOT1 + if (!reg2hw.plat_integ_auth_slot1_read_lock) begin + part_access_pre[PlatIntegAuthSlot1Idx].read_lock = prim_mubi_pkg::MuBi8True; + end + // PLAT_OWNER_AUTH_SLOT0 + if (!reg2hw.plat_owner_auth_slot0_read_lock) begin + part_access_pre[PlatOwnerAuthSlot0Idx].read_lock = prim_mubi_pkg::MuBi8True; + end + // PLAT_OWNER_AUTH_SLOT1 + if (!reg2hw.plat_owner_auth_slot1_read_lock) begin + part_access_pre[PlatOwnerAuthSlot1Idx].read_lock = prim_mubi_pkg::MuBi8True; + end + // PLAT_OWNER_AUTH_SLOT2 + if (!reg2hw.plat_owner_auth_slot2_read_lock) begin + part_access_pre[PlatOwnerAuthSlot2Idx].read_lock = prim_mubi_pkg::MuBi8True; + end + // PLAT_OWNER_AUTH_SLOT3 + if (!reg2hw.plat_owner_auth_slot3_read_lock) begin + part_access_pre[PlatOwnerAuthSlot3Idx].read_lock = prim_mubi_pkg::MuBi8True; + end + // EXT_NVM + if (!reg2hw.ext_nvm_read_lock) begin + part_access_pre[ExtNvmIdx].read_lock = prim_mubi_pkg::MuBi8True; + end + // ROM_PATCH + if (!reg2hw.rom_patch_read_lock) begin + part_access_pre[RomPatchIdx].read_lock = prim_mubi_pkg::MuBi8True; + end + return part_access_pre; + endfunction : named_part_access_pre + + function automatic otp_broadcast_t named_broadcast_assign( + logic [NumPart-1:0] part_init_done, + logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data); + otp_broadcast_t otp_broadcast; + logic valid, unused; + unused = 1'b0; + valid = 1'b1; + // VENDOR_TEST + unused ^= ^{part_init_done[VendorTestIdx], + part_buf_data[VendorTestOffset +: VendorTestSize]}; + // CREATOR_SW_CFG + unused ^= ^{part_init_done[CreatorSwCfgIdx], + part_buf_data[CreatorSwCfgOffset +: CreatorSwCfgSize]}; + // OWNER_SW_CFG + unused ^= ^{part_init_done[OwnerSwCfgIdx], + part_buf_data[OwnerSwCfgOffset +: OwnerSwCfgSize]}; + // OWNERSHIP_SLOT_STATE + unused ^= ^{part_init_done[OwnershipSlotStateIdx], + part_buf_data[OwnershipSlotStateOffset +: OwnershipSlotStateSize]}; + // ROT_CREATOR_AUTH + unused ^= ^{part_init_done[RotCreatorAuthIdx], + part_buf_data[RotCreatorAuthOffset +: RotCreatorAuthSize]}; + // ROT_OWNER_AUTH_SLOT0 + unused ^= ^{part_init_done[RotOwnerAuthSlot0Idx], + part_buf_data[RotOwnerAuthSlot0Offset +: RotOwnerAuthSlot0Size]}; + // ROT_OWNER_AUTH_SLOT1 + unused ^= ^{part_init_done[RotOwnerAuthSlot1Idx], + part_buf_data[RotOwnerAuthSlot1Offset +: RotOwnerAuthSlot1Size]}; + // PLAT_INTEG_AUTH_SLOT0 + unused ^= ^{part_init_done[PlatIntegAuthSlot0Idx], + part_buf_data[PlatIntegAuthSlot0Offset +: PlatIntegAuthSlot0Size]}; + // PLAT_INTEG_AUTH_SLOT1 + unused ^= ^{part_init_done[PlatIntegAuthSlot1Idx], + part_buf_data[PlatIntegAuthSlot1Offset +: PlatIntegAuthSlot1Size]}; + // PLAT_OWNER_AUTH_SLOT0 + unused ^= ^{part_init_done[PlatOwnerAuthSlot0Idx], + part_buf_data[PlatOwnerAuthSlot0Offset +: PlatOwnerAuthSlot0Size]}; + // PLAT_OWNER_AUTH_SLOT1 + unused ^= ^{part_init_done[PlatOwnerAuthSlot1Idx], + part_buf_data[PlatOwnerAuthSlot1Offset +: PlatOwnerAuthSlot1Size]}; + // PLAT_OWNER_AUTH_SLOT2 + unused ^= ^{part_init_done[PlatOwnerAuthSlot2Idx], + part_buf_data[PlatOwnerAuthSlot2Offset +: PlatOwnerAuthSlot2Size]}; + // PLAT_OWNER_AUTH_SLOT3 + unused ^= ^{part_init_done[PlatOwnerAuthSlot3Idx], + part_buf_data[PlatOwnerAuthSlot3Offset +: PlatOwnerAuthSlot3Size]}; + // EXT_NVM + unused ^= ^{part_init_done[ExtNvmIdx], + part_buf_data[ExtNvmOffset +: ExtNvmSize]}; + // ROM_PATCH + unused ^= ^{part_init_done[RomPatchIdx], + part_buf_data[RomPatchOffset +: RomPatchSize]}; + // HW_CFG0 + valid &= part_init_done[HwCfg0Idx]; + otp_broadcast.hw_cfg0_data = otp_hw_cfg0_data_t'(part_buf_data[HwCfg0Offset +: HwCfg0Size]); + // HW_CFG1 + valid &= part_init_done[HwCfg1Idx]; + otp_broadcast.hw_cfg1_data = otp_hw_cfg1_data_t'(part_buf_data[HwCfg1Offset +: HwCfg1Size]); + // SECRET0 + unused ^= ^{part_init_done[Secret0Idx], + part_buf_data[Secret0Offset +: Secret0Size]}; + // SECRET1 + unused ^= ^{part_init_done[Secret1Idx], + part_buf_data[Secret1Offset +: Secret1Size]}; + // SECRET2 + unused ^= ^{part_init_done[Secret2Idx], + part_buf_data[Secret2Offset +: Secret2Size]}; + // SECRET3 + unused ^= ^{part_init_done[Secret3Idx], + part_buf_data[Secret3Offset +: Secret3Size]}; + // LIFE_CYCLE + unused ^= ^{part_init_done[LifeCycleIdx], + part_buf_data[LifeCycleOffset +: LifeCycleSize]}; + otp_broadcast.valid = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(valid); + return otp_broadcast; + endfunction : named_broadcast_assign + + function automatic otp_keymgr_key_t named_keymgr_key_assign( + logic [NumPart-1:0][ScrmblBlockWidth-1:0] part_digest, + logic [$bits(PartInvDefault)/8-1:0][7:0] part_buf_data, + lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en); + otp_keymgr_key_t otp_keymgr_key; + logic valid, unused; + unused = 1'b0; + // For now we use a fixed struct type here so that the + // interface to the keymgr remains stable. The type contains + // a superset of all options, so we have to initialize it to '0 here. + otp_keymgr_key = '0; + // VENDOR_TEST + unused ^= ^{part_digest[VendorTestIdx], + part_buf_data[VendorTestOffset +: VendorTestSize]}; + // CREATOR_SW_CFG + unused ^= ^{part_digest[CreatorSwCfgIdx], + part_buf_data[CreatorSwCfgOffset +: CreatorSwCfgSize]}; + // OWNER_SW_CFG + unused ^= ^{part_digest[OwnerSwCfgIdx], + part_buf_data[OwnerSwCfgOffset +: OwnerSwCfgSize]}; + // OWNERSHIP_SLOT_STATE + unused ^= ^{part_digest[OwnershipSlotStateIdx], + part_buf_data[OwnershipSlotStateOffset +: OwnershipSlotStateSize]}; + // ROT_CREATOR_AUTH + unused ^= ^{part_digest[RotCreatorAuthIdx], + part_buf_data[RotCreatorAuthOffset +: RotCreatorAuthSize]}; + // ROT_OWNER_AUTH_SLOT0 + unused ^= ^{part_digest[RotOwnerAuthSlot0Idx], + part_buf_data[RotOwnerAuthSlot0Offset +: RotOwnerAuthSlot0Size]}; + // ROT_OWNER_AUTH_SLOT1 + unused ^= ^{part_digest[RotOwnerAuthSlot1Idx], + part_buf_data[RotOwnerAuthSlot1Offset +: RotOwnerAuthSlot1Size]}; + // PLAT_INTEG_AUTH_SLOT0 + unused ^= ^{part_digest[PlatIntegAuthSlot0Idx], + part_buf_data[PlatIntegAuthSlot0Offset +: PlatIntegAuthSlot0Size]}; + // PLAT_INTEG_AUTH_SLOT1 + unused ^= ^{part_digest[PlatIntegAuthSlot1Idx], + part_buf_data[PlatIntegAuthSlot1Offset +: PlatIntegAuthSlot1Size]}; + // PLAT_OWNER_AUTH_SLOT0 + unused ^= ^{part_digest[PlatOwnerAuthSlot0Idx], + part_buf_data[PlatOwnerAuthSlot0Offset +: PlatOwnerAuthSlot0Size]}; + // PLAT_OWNER_AUTH_SLOT1 + unused ^= ^{part_digest[PlatOwnerAuthSlot1Idx], + part_buf_data[PlatOwnerAuthSlot1Offset +: PlatOwnerAuthSlot1Size]}; + // PLAT_OWNER_AUTH_SLOT2 + unused ^= ^{part_digest[PlatOwnerAuthSlot2Idx], + part_buf_data[PlatOwnerAuthSlot2Offset +: PlatOwnerAuthSlot2Size]}; + // PLAT_OWNER_AUTH_SLOT3 + unused ^= ^{part_digest[PlatOwnerAuthSlot3Idx], + part_buf_data[PlatOwnerAuthSlot3Offset +: PlatOwnerAuthSlot3Size]}; + // EXT_NVM + unused ^= ^{part_digest[ExtNvmIdx], + part_buf_data[ExtNvmOffset +: ExtNvmSize]}; + // ROM_PATCH + unused ^= ^{part_digest[RomPatchIdx], + part_buf_data[RomPatchOffset +: RomPatchSize]}; + // HW_CFG0 + unused ^= ^{part_digest[HwCfg0Idx], + part_buf_data[HwCfg0Offset +: HwCfg0Size]}; + // HW_CFG1 + unused ^= ^{part_digest[HwCfg1Idx], + part_buf_data[HwCfg1Offset +: HwCfg1Size]}; + // SECRET0 + unused ^= ^{part_digest[Secret0Idx], + part_buf_data[Secret0Offset +: Secret0Size]}; + // SECRET1 + unused ^= ^{part_digest[Secret1Idx], + part_buf_data[Secret1Offset +: Secret1Size]}; + // SECRET2 + valid = (part_digest[Secret2Idx] != 0); + unused ^= ^part_buf_data[RmaTokenOffset +: RmaTokenSize]; + otp_keymgr_key.creator_root_key_share0_valid = valid; + if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_seed_hw_rd_en)) begin + otp_keymgr_key.creator_root_key_share0 = + part_buf_data[CreatorRootKeyShare0Offset +: CreatorRootKeyShare0Size]; + end else begin + otp_keymgr_key.creator_root_key_share0 = + PartInvDefault[CreatorRootKeyShare0Offset*8 +: CreatorRootKeyShare0Size*8]; + end + otp_keymgr_key.creator_root_key_share1_valid = valid; + if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_seed_hw_rd_en)) begin + otp_keymgr_key.creator_root_key_share1 = + part_buf_data[CreatorRootKeyShare1Offset +: CreatorRootKeyShare1Size]; + end else begin + otp_keymgr_key.creator_root_key_share1 = + PartInvDefault[CreatorRootKeyShare1Offset*8 +: CreatorRootKeyShare1Size*8]; + end + otp_keymgr_key.creator_seed_valid = valid; + if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_seed_hw_rd_en)) begin + otp_keymgr_key.creator_seed = + part_buf_data[CreatorSeedOffset +: CreatorSeedSize]; + end else begin + otp_keymgr_key.creator_seed = + PartInvDefault[CreatorSeedOffset*8 +: CreatorSeedSize*8]; + end + // This is not used since we consume the + // ungated digest values from the part_digest array. + unused ^= ^part_buf_data[Secret2DigestOffset +: Secret2DigestSize]; + // SECRET3 + valid = (part_digest[Secret3Idx] != 0); + otp_keymgr_key.owner_seed_valid = valid; + if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_seed_hw_rd_en)) begin + otp_keymgr_key.owner_seed = + part_buf_data[OwnerSeedOffset +: OwnerSeedSize]; + end else begin + otp_keymgr_key.owner_seed = + PartInvDefault[OwnerSeedOffset*8 +: OwnerSeedSize*8]; + end + // This is not used since we consume the + // ungated digest values from the part_digest array. + unused ^= ^part_buf_data[Secret3DigestOffset +: Secret3DigestSize]; + // LIFE_CYCLE + unused ^= ^{part_digest[LifeCycleIdx], + part_buf_data[LifeCycleOffset +: LifeCycleSize]}; + unused ^= valid; + return otp_keymgr_key; + endfunction : named_keymgr_key_assign + +endpackage : otp_ctrl_part_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_unbuf.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_unbuf.sv new file mode 100644 index 00000000000..cd837ef0867 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_unbuf.sv @@ -0,0 +1,537 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Unbuffered partition for OTP controller. +// + +`include "prim_flop_macros.sv" + +module otp_ctrl_part_unbuf + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_part_pkg::*; + import otp_ctrl_macro_pkg::OtpAddrShift; + import otp_ctrl_macro_pkg::OtpAddrWidth; + import otp_ctrl_macro_pkg::OtpIfWidth; + import otp_ctrl_macro_pkg::OtpSizeWidth; + import otp_ctrl_macro_pkg::OtpWidth; + import otp_ctrl_top_specific_pkg::*; +#( + // Partition information. + parameter part_info_t Info = PartInfoDefault +) ( + input clk_i, + input rst_ni, + // Pulse to start partition initialisation (required once per power cycle). + input init_req_i, + output logic init_done_o, + // Escalation input. This moves the FSM into a terminal state and locks down + // the partition. + input lc_ctrl_pkg::lc_tx_t escalate_en_i, + // Output error state of partition, to be consumed by OTP error/alert logic. + // Note that most errors are not recoverable and move the partition FSM into + // a terminal error state. + output otp_err_e error_o, + // This error signal is pulsed high if the FSM has been glitched into an invalid state. + // Although it is somewhat redundant with the error code in error_o above, it is + // meant to cover cases where we already latched an error code while the FSM is + // glitched into an invalid state (since in that case, the error code will not be + // overridden with the FSM error code so that the original error code is still + // discoverable). + output logic fsm_err_o, + // Access/lock status + // SEC_CM: ACCESS.CTRL.MUBI + input part_access_t access_i, // runtime lock from CSRs + output part_access_t access_o, + // Buffered 64bit digest output. + output logic [ScrmblBlockWidth-1:0] digest_o, + // Interface to TL-UL adapter + input logic tlul_req_i, + output logic tlul_gnt_o, + input [SwWindowAddrWidth-1:0] tlul_addr_i, + output logic [1:0] tlul_rerror_o, + output logic tlul_rvalid_o, + output logic [31:0] tlul_rdata_o, + // OTP interface + output logic otp_req_o, + output otp_ctrl_macro_pkg::cmd_e otp_cmd_o, + output logic [OtpSizeWidth-1:0] otp_size_o, + output logic [OtpIfWidth-1:0] otp_wdata_o, + output logic [OtpAddrWidth-1:0] otp_addr_o, + input otp_gnt_i, + input otp_rvalid_i, + input [ScrmblBlockWidth-1:0] otp_rdata_i, + input otp_ctrl_macro_pkg::err_e otp_err_i +); + + //////////////////////// + // Integration Checks // + //////////////////////// + + import prim_mubi_pkg::*; + import prim_util_pkg::vbits; + + localparam logic [OtpByteAddrWidth:0] PartEnd = (OtpByteAddrWidth+1)'(Info.offset) + + (OtpByteAddrWidth+1)'(Info.size); + localparam int unsigned DigestOffsetInt = int'(PartEnd) - ScrmblBlockWidth/8; + + localparam bit [OtpByteAddrWidth-1:0] DigestOffset = DigestOffsetInt[OtpByteAddrWidth-1:0]; + + // Integration checks for parameters. + `ASSERT_INIT(OffsetMustBeBlockAligned_A, (Info.offset % (ScrmblBlockWidth/8)) == 0) + `ASSERT_INIT(SizeMustBeBlockAligned_A, (Info.size % (ScrmblBlockWidth/8)) == 0) + `ASSERT_INIT(DigestOffsetMustBeRepresentable_A, DigestOffsetInt == int'(DigestOffset)) + + /////////////////////// + // OTP Partition FSM // + /////////////////////// + + // SEC_CM: PART.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 7 -n 10 \ + // -s 4247417884 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (52.38%) + // 6: |||||||||||| (33.33%) + // 7: | (4.76%) + // 8: ||| (9.52%) + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 8 + // Minimum Hamming weight: 3 + // Maximum Hamming weight: 9 + // + localparam int StateWidth = 10; + typedef enum logic [StateWidth-1:0] { + ResetSt = 10'b1010110110, + InitSt = 10'b0100010011, + InitWaitSt = 10'b0001011000, + IdleSt = 10'b1011101001, + ReadSt = 10'b0101101110, + ReadWaitSt = 10'b0110100101, + ErrorSt = 10'b1111011111 + } state_e; + + typedef enum logic { + DigestAddrSel = 1'b0, + DataAddrSel = 1'b1 + } addr_sel_e; + + state_e state_d, state_q; + addr_sel_e otp_addr_sel; + otp_err_e error_d, error_q; + + logic digest_reg_en; + logic ecc_err; + + logic tlul_addr_in_range; + logic [SwWindowAddrWidth-1:0] tlul_addr_d, tlul_addr_q; + + // This is only used to return bus errors when the FSM is in ErrorSt. + logic pending_tlul_error_d, pending_tlul_error_q; + + // Output partition error state. + assign error_o = error_q; + + // This partition cannot do any write accesses, hence we tie this + // constantly off. + assign otp_wdata_o = '0; + // Depending on the partition configuration, the wrapper is instructed to ignore integrity + // calculations and checks. To be on the safe side, the partition filters error responses at this + // point and does not report any integrity errors if integrity is disabled. + otp_err_e otp_err; + if (Info.integrity) begin : gen_integrity + assign otp_cmd_o = otp_ctrl_macro_pkg::Read; + assign otp_err = otp_err_e'(otp_err_i); + end else begin : gen_no_integrity + assign otp_cmd_o = otp_ctrl_macro_pkg::ReadRaw; + always_comb begin + if (otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}) begin + otp_err = NoError; + end else begin + otp_err = otp_err_e'(otp_err_i); + end + end + end + + `ASSERT_KNOWN(FsmStateKnown_A, state_q) + always_comb begin : p_fsm + // Default assignments + state_d = state_q; + + // Response to init request + init_done_o = 1'b0; + + // OTP signals + otp_req_o = 1'b0; + otp_addr_sel = DigestAddrSel; + + // TL-UL signals + tlul_gnt_o = 1'b0; + tlul_rvalid_o = 1'b0; + tlul_rerror_o = '0; + + // Enable for buffered digest register + digest_reg_en = 1'b0; + + // Error Register + error_d = error_q; + pending_tlul_error_d = 1'b0; + fsm_err_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // State right after reset. Wait here until we get a an + // initialization request. + ResetSt: begin + if (init_req_i) begin + // If the partition does not have a digest, no initialization is necessary. + if (Info.sw_digest) begin + state_d = InitSt; + end else begin + state_d = IdleSt; + end + end + end + /////////////////////////////////////////////////////////////////// + // Initialization reads out the digest only in unbuffered + // partitions. Wait here until the OTP request has been granted. + // And then wait until the OTP word comes back. + InitSt: begin + otp_req_o = 1'b1; + if (otp_gnt_i) begin + state_d = InitWaitSt; + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and write to digest buffer register. In + // case an OTP transaction fails, latch the OTP error code and + // jump to a terminal error state. + InitWaitSt: begin + if (otp_rvalid_i) begin + digest_reg_en = 1'b1; + if (otp_err inside {NoError, MacroEccCorrError}) begin + state_d = IdleSt; + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + end + end + end + /////////////////////////////////////////////////////////////////// + // Wait for TL-UL requests coming in. + // Then latch address and go to readout state. + IdleSt: begin + init_done_o = 1'b1; + if (tlul_req_i) begin + error_d = NoError; // clear recoverable soft errors. + state_d = ReadSt; + tlul_gnt_o = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // If the address is out of bounds, or if the partition is + // locked, signal back a bus error. Note that such an error does + // not cause the partition to go into error state. Otherwise if + // these checks pass, an OTP word is requested. + ReadSt: begin + init_done_o = 1'b1; + // Double check the address range. + if (tlul_addr_in_range && mubi8_test_false_strict(access_o.read_lock)) begin + otp_req_o = 1'b1; + otp_addr_sel = DataAddrSel; + if (otp_gnt_i) begin + state_d = ReadWaitSt; + end + end else begin + state_d = IdleSt; + error_d = AccessError; // Signal this error, but do not go into terminal error state. + tlul_rvalid_o = 1'b1; + tlul_rerror_o = 2'b11; // This causes the TL-UL adapter to return a bus error. + end + end + /////////////////////////////////////////////////////////////////// + // Wait for OTP response and release the TL-UL response. In + // case an OTP transaction fails, latch the OTP error code, + // signal a TL-Ul bus error and jump to a terminal error state. + ReadWaitSt: begin + init_done_o = 1'b1; + if (otp_rvalid_i) begin + tlul_rvalid_o = 1'b1; + if (otp_err inside {NoError, MacroEccCorrError}) begin + state_d = IdleSt; + // At this point the only error that we could have gotten are correctable ECC errors. + if (otp_err != NoError) begin + error_d = MacroEccCorrError; + end + end else begin + state_d = ErrorSt; + error_d = otp_err; + // This causes the TL-UL adapter to return a bus error. + tlul_rerror_o = 2'b11; + end + end + end + /////////////////////////////////////////////////////////////////// + // Terminal Error State. This locks access to the partition. + // Make sure the partition signals an error state if no error + // code has been latched so far. + ErrorSt: begin + if (error_q == NoError) begin + error_d = FsmStateError; + end + + // Return bus errors if there are pending TL-UL requests. + if (pending_tlul_error_q) begin + tlul_rerror_o = 2'b11; + tlul_rvalid_o = 1'b1; + end else if (tlul_req_i) begin + tlul_gnt_o = 1'b1; + pending_tlul_error_d = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // We should never get here. If we do (e.g. via a malicious + // glitch), error out immediately. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of + // an ECC error or escalation, and lock access to the partition down. + // SEC_CM: PART.FSM.LOCAL_ESC + if (ecc_err) begin + state_d = ErrorSt; + if (state_q != ErrorSt) begin + error_d = CheckFailError; + end + end + // SEC_CM: PART.FSM.GLOBAL_ESC + if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + if (state_q != ErrorSt) begin + error_d = FsmStateError; + end + end + end + + /////////////////////////////////// + // Signals to/from TL-UL Adapter // + /////////////////////////////////// + + assign tlul_addr_d = tlul_addr_i; + // Do not forward data in case of an error. + assign tlul_rdata_o = (tlul_rvalid_o && tlul_rerror_o == '0) ? otp_rdata_i[31:0] : '0; + + if (Info.offset == 0) begin : gen_zero_offset + assign tlul_addr_in_range = {1'b0, tlul_addr_q, 2'b00} < PartEnd; + + end else begin : gen_nonzero_offset + assign tlul_addr_in_range = {tlul_addr_q, 2'b00} >= Info.offset && + {1'b0, tlul_addr_q, 2'b00} < PartEnd; + end + + // Note that OTP works on halfword (16bit) addresses, hence need to + // shift the addresses appropriately. + logic [OtpByteAddrWidth-1:0] addr_calc; + assign addr_calc = (otp_addr_sel == DigestAddrSel) ? DigestOffset : {tlul_addr_q, 2'b00}; + assign otp_addr_o = addr_calc[OtpByteAddrWidth-1:OtpAddrShift]; + + if (OtpAddrShift > 0) begin : gen_unused + logic unused_bits; + assign unused_bits = ^addr_calc[OtpAddrShift-1:0]; + end + + // Request 32bit except in case of the digest. + assign otp_size_o = (otp_addr_sel == DigestAddrSel) ? + OtpSizeWidth'(unsigned'(ScrmblBlockWidth / OtpWidth - 1)) : + OtpSizeWidth'(unsigned'(32 / OtpWidth - 1)); + + //////////////// + // Digest Reg // + //////////////// + + if (Info.sw_digest) begin : gen_ecc_reg + // SEC_CM: PART.DATA_REG.INTEGRITY + otp_ctrl_ecc_reg #( + .Width ( ScrmblBlockWidth ), + .Depth ( 1 ) + ) u_otp_ctrl_ecc_reg ( + .clk_i, + .rst_ni, + .wren_i ( digest_reg_en ), + .addr_i ( '0 ), + .wdata_i ( otp_rdata_i ), + .rdata_o ( ), + .data_o ( digest_o ), + .ecc_err_o ( ecc_err ) + ); + end else begin : gen_no_ecc_reg + logic unused_digest_reg_en; + logic unused_rdata; + assign unused_digest_reg_en = digest_reg_en; + assign unused_rdata = ^otp_rdata_i[32 +: 32]; // Upper word is not connected in this case. + assign digest_o = '0; + assign ecc_err = 1'b0; + end + + //////////////////////// + // DAI Access Control // + //////////////////////// + + mubi8_t init_locked; + assign init_locked = (~init_done_o) ? MuBi8True : MuBi8False; + + // Aggregate all possible DAI write locks. The partition is also locked when uninitialized. + // Note that the locks are redundantly encoded values. + part_access_t access_pre; + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock_pre ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(init_locked, access_i.write_lock)), + .mubi_o(access_pre.write_lock) + ); + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock_pre ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(init_locked, access_i.read_lock)), + .mubi_o(access_pre.read_lock) + ); + + // SEC_CM: PART.MEM.SW_UNWRITABLE + if (Info.write_lock) begin : gen_digest_write_lock + mubi8_t digest_locked; + assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; + + // This prevents the synthesis tool from optimizing the multibit signal. + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_write_lock ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(access_pre.write_lock, digest_locked)), + .mubi_o(access_o.write_lock) + ); + + `ASSERT(DigestWriteLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.write_lock)) + end else begin : gen_no_digest_write_lock + assign access_o.write_lock = access_pre.write_lock; + end + + // SEC_CM: PART.MEM.SW_UNREADABLE + if (Info.read_lock) begin : gen_digest_read_lock + mubi8_t digest_locked; + assign digest_locked = (digest_o != '0) ? MuBi8True : MuBi8False; + + // This prevents the synthesis tool from optimizing the multibit signal. + prim_mubi8_sender #( + .AsyncOn(0) + ) u_prim_mubi8_sender_read_lock ( + .clk_i, + .rst_ni, + .mubi_i(mubi8_and_lo(access_pre.read_lock, digest_locked)), + .mubi_o(access_o.read_lock) + ); + + `ASSERT(DigestReadLocksPartition_A, digest_o |-> mubi8_test_true_loose(access_o.read_lock)) + end else begin : gen_no_digest_read_lock + assign access_o.read_lock = access_pre.read_lock; + end + + /////////////// + // Registers // + /////////////// + + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ResetSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + error_q <= NoError; + tlul_addr_q <= '0; + pending_tlul_error_q <= 1'b0; + end else begin + error_q <= error_d; + pending_tlul_error_q <= pending_tlul_error_d; + if (tlul_gnt_o) begin + tlul_addr_q <= tlul_addr_d; + end + end + end + + //////////////// + // Assertions // + //////////////// + + // Known assertions + `ASSERT_KNOWN(InitDoneKnown_A, init_done_o) + `ASSERT_KNOWN(ErrorKnown_A, error_o) + `ASSERT_KNOWN(AccessKnown_A, access_o) + `ASSERT_KNOWN(DigestKnown_A, digest_o) + `ASSERT_KNOWN(TlulGntKnown_A, tlul_gnt_o) + `ASSERT_KNOWN(TlulRerrorKnown_A, tlul_rerror_o) + `ASSERT_KNOWN(TlulRvalidKnown_A, tlul_rvalid_o) + `ASSERT_KNOWN(TlulRdataKnown_A, tlul_rdata_o) + `ASSERT_KNOWN(OtpReqKnown_A, otp_req_o) + `ASSERT_KNOWN(OtpCmdKnown_A, otp_cmd_o) + `ASSERT_KNOWN(OtpSizeKnown_A, otp_size_o) + `ASSERT_KNOWN(OtpWdataKnown_A, otp_wdata_o) + `ASSERT_KNOWN(OtpAddrKnown_A, otp_addr_o) + + // Uninitialized partitions should always be locked, no matter what. + `ASSERT(InitWriteLocksPartition_A, + ~init_done_o + |-> + mubi8_test_true_loose(access_o.write_lock)) + `ASSERT(InitReadLocksPartition_A, + ~init_done_o + |-> + mubi8_test_true_loose(access_o.read_lock)) + // Incoming Lock propagation + `ASSERT(WriteLockPropagation_A, + mubi8_test_true_loose(access_i.write_lock) + |-> + mubi8_test_true_loose(access_o.write_lock)) + `ASSERT(ReadLockPropagation_A, + mubi8_test_true_loose(access_i.read_lock) + |-> + mubi8_test_true_loose(access_o.read_lock)) + // If the partition is read locked, the TL-UL access must error out + `ASSERT(TlulReadOnReadLock_A, + tlul_req_i && tlul_gnt_o ##1 mubi8_test_true_loose(access_o.read_lock) + |-> + tlul_rerror_o > '0 && tlul_rvalid_o) + // ECC error in buffer regs. + `ASSERT(EccErrorState_A, + ecc_err + |=> + state_q == ErrorSt) + // OTP error response + `ASSERT(OtpErrorState_A, + state_q inside {InitWaitSt, ReadWaitSt} && otp_rvalid_i && + !(otp_err inside {NoError, MacroEccCorrError}) && !ecc_err + |=> + state_q == ErrorSt && error_o == $past(otp_err)) + +endmodule : otp_ctrl_part_unbuf diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv new file mode 100644 index 00000000000..4f5ed0394ac --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv @@ -0,0 +1,1254 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package otp_ctrl_reg_pkg; + + // Param list + parameter int NumSramKeyReqSlots = 4; + parameter int OtpDepth = 8192; + parameter int OtpWidth = 2; + parameter int OtpSizeWidth = 2; + parameter int OtpByteAddrWidth = 14; + parameter int NumErrorEntries = 24; + parameter int NumDaiWords = 2; + parameter int NumDigestWords = 2; + parameter int NumSwCfgWindowWords = 4096; + parameter int NumPart = 22; + parameter int NumPartUnbuf = 15; + parameter int NumPartBuf = 7; + parameter int VendorTestOffset = 0; + parameter int VendorTestSize = 64; + parameter int ScratchOffset = 0; + parameter int ScratchSize = 56; + parameter int VendorTestDigestOffset = 56; + parameter int VendorTestDigestSize = 8; + parameter int CreatorSwCfgOffset = 64; + parameter int CreatorSwCfgSize = 320; + parameter int CreatorSwCfgAstCfgOffset = 64; + parameter int CreatorSwCfgAstCfgSize = 124; + parameter int CreatorSwCfgAstInitEnOffset = 188; + parameter int CreatorSwCfgAstInitEnSize = 4; + parameter int CreatorSwCfgOverridesOffset = 192; + parameter int CreatorSwCfgOverridesSize = 32; + parameter int CreatorSwCfgRomExtSkuOffset = 224; + parameter int CreatorSwCfgRomExtSkuSize = 4; + parameter int CreatorSwCfgSigverifyRsaModExpIbexEnOffset = 228; + parameter int CreatorSwCfgSigverifyRsaModExpIbexEnSize = 4; + parameter int CreatorSwCfgSigverifyRsaKeyEnOffset = 232; + parameter int CreatorSwCfgSigverifyRsaKeyEnSize = 8; + parameter int CreatorSwCfgSigverifySpxEnOffset = 240; + parameter int CreatorSwCfgSigverifySpxEnSize = 4; + parameter int CreatorSwCfgSigverifySpxKeyEnOffset = 244; + parameter int CreatorSwCfgSigverifySpxKeyEnSize = 8; + parameter int CreatorSwCfgFlashDataDefaultCfgOffset = 252; + parameter int CreatorSwCfgFlashDataDefaultCfgSize = 4; + parameter int CreatorSwCfgFlashInfoBootDataCfgOffset = 256; + parameter int CreatorSwCfgFlashInfoBootDataCfgSize = 4; + parameter int CreatorSwCfgFlashHwInfoCfgOverrideOffset = 260; + parameter int CreatorSwCfgFlashHwInfoCfgOverrideSize = 4; + parameter int CreatorSwCfgRngEnOffset = 264; + parameter int CreatorSwCfgRngEnSize = 4; + parameter int CreatorSwCfgJitterEnOffset = 268; + parameter int CreatorSwCfgJitterEnSize = 4; + parameter int CreatorSwCfgRetRamResetMaskOffset = 272; + parameter int CreatorSwCfgRetRamResetMaskSize = 4; + parameter int CreatorSwCfgManufStateOffset = 276; + parameter int CreatorSwCfgManufStateSize = 4; + parameter int CreatorSwCfgRomExecEnOffset = 280; + parameter int CreatorSwCfgRomExecEnSize = 4; + parameter int CreatorSwCfgCpuctrlOffset = 284; + parameter int CreatorSwCfgCpuctrlSize = 4; + parameter int CreatorSwCfgMinSecVerRomExtOffset = 288; + parameter int CreatorSwCfgMinSecVerRomExtSize = 4; + parameter int CreatorSwCfgMinSecVerBl0Offset = 292; + parameter int CreatorSwCfgMinSecVerBl0Size = 4; + parameter int CreatorSwCfgDefaultBootDataInProdEnOffset = 296; + parameter int CreatorSwCfgDefaultBootDataInProdEnSize = 4; + parameter int CreatorSwCfgRmaSpinEnOffset = 300; + parameter int CreatorSwCfgRmaSpinEnSize = 4; + parameter int CreatorSwCfgRmaSpinCyclesOffset = 304; + parameter int CreatorSwCfgRmaSpinCyclesSize = 4; + parameter int CreatorSwCfgRngRepcntThresholdsOffset = 308; + parameter int CreatorSwCfgRngRepcntThresholdsSize = 4; + parameter int CreatorSwCfgRngRepcntsThresholdsOffset = 312; + parameter int CreatorSwCfgRngRepcntsThresholdsSize = 4; + parameter int CreatorSwCfgRngAdaptpHiThresholdsOffset = 316; + parameter int CreatorSwCfgRngAdaptpHiThresholdsSize = 4; + parameter int CreatorSwCfgRngAdaptpLoThresholdsOffset = 320; + parameter int CreatorSwCfgRngAdaptpLoThresholdsSize = 4; + parameter int CreatorSwCfgRngBucketThresholdsOffset = 324; + parameter int CreatorSwCfgRngBucketThresholdsSize = 4; + parameter int CreatorSwCfgRngMarkovHiThresholdsOffset = 328; + parameter int CreatorSwCfgRngMarkovHiThresholdsSize = 4; + parameter int CreatorSwCfgRngMarkovLoThresholdsOffset = 332; + parameter int CreatorSwCfgRngMarkovLoThresholdsSize = 4; + parameter int CreatorSwCfgRngExthtHiThresholdsOffset = 336; + parameter int CreatorSwCfgRngExthtHiThresholdsSize = 4; + parameter int CreatorSwCfgRngExthtLoThresholdsOffset = 340; + parameter int CreatorSwCfgRngExthtLoThresholdsSize = 4; + parameter int CreatorSwCfgRngAlertThresholdOffset = 344; + parameter int CreatorSwCfgRngAlertThresholdSize = 4; + parameter int CreatorSwCfgRngHealthConfigDigestOffset = 348; + parameter int CreatorSwCfgRngHealthConfigDigestSize = 4; + parameter int CreatorSwCfgSramKeyRenewEnOffset = 352; + parameter int CreatorSwCfgSramKeyRenewEnSize = 4; + parameter int CreatorSwCfgDigestOffset = 376; + parameter int CreatorSwCfgDigestSize = 8; + parameter int OwnerSwCfgOffset = 384; + parameter int OwnerSwCfgSize = 632; + parameter int OwnerSwCfgRomErrorReportingOffset = 384; + parameter int OwnerSwCfgRomErrorReportingSize = 4; + parameter int OwnerSwCfgRomBootstrapDisOffset = 388; + parameter int OwnerSwCfgRomBootstrapDisSize = 4; + parameter int OwnerSwCfgRomAlertClassEnOffset = 392; + parameter int OwnerSwCfgRomAlertClassEnSize = 4; + parameter int OwnerSwCfgRomAlertEscalationOffset = 396; + parameter int OwnerSwCfgRomAlertEscalationSize = 4; + parameter int OwnerSwCfgRomAlertClassificationOffset = 400; + parameter int OwnerSwCfgRomAlertClassificationSize = 400; + parameter int OwnerSwCfgRomLocalAlertClassificationOffset = 800; + parameter int OwnerSwCfgRomLocalAlertClassificationSize = 64; + parameter int OwnerSwCfgRomAlertAccumThreshOffset = 864; + parameter int OwnerSwCfgRomAlertAccumThreshSize = 16; + parameter int OwnerSwCfgRomAlertTimeoutCyclesOffset = 880; + parameter int OwnerSwCfgRomAlertTimeoutCyclesSize = 16; + parameter int OwnerSwCfgRomAlertPhaseCyclesOffset = 896; + parameter int OwnerSwCfgRomAlertPhaseCyclesSize = 64; + parameter int OwnerSwCfgRomAlertDigestProdOffset = 960; + parameter int OwnerSwCfgRomAlertDigestProdSize = 4; + parameter int OwnerSwCfgRomAlertDigestProdEndOffset = 964; + parameter int OwnerSwCfgRomAlertDigestProdEndSize = 4; + parameter int OwnerSwCfgRomAlertDigestDevOffset = 968; + parameter int OwnerSwCfgRomAlertDigestDevSize = 4; + parameter int OwnerSwCfgRomAlertDigestRmaOffset = 972; + parameter int OwnerSwCfgRomAlertDigestRmaSize = 4; + parameter int OwnerSwCfgRomWatchdogBiteThresholdCyclesOffset = 976; + parameter int OwnerSwCfgRomWatchdogBiteThresholdCyclesSize = 4; + parameter int OwnerSwCfgRomKeymgrRomExtMeasEnOffset = 980; + parameter int OwnerSwCfgRomKeymgrRomExtMeasEnSize = 4; + parameter int OwnerSwCfgManufStateOffset = 984; + parameter int OwnerSwCfgManufStateSize = 4; + parameter int OwnerSwCfgRomRstmgrInfoEnOffset = 988; + parameter int OwnerSwCfgRomRstmgrInfoEnSize = 4; + parameter int OwnerSwCfgDigestOffset = 1008; + parameter int OwnerSwCfgDigestSize = 8; + parameter int OwnershipSlotStateOffset = 1016; + parameter int OwnershipSlotStateSize = 48; + parameter int OwnershipSlotStateRotOwnerAuthOffset = 1016; + parameter int OwnershipSlotStateRotOwnerAuthSize = 16; + parameter int OwnershipSlotStatePlatIntegAuthOffset = 1032; + parameter int OwnershipSlotStatePlatIntegAuthSize = 16; + parameter int OwnershipSlotStatePlatOwnerAuthOffset = 1048; + parameter int OwnershipSlotStatePlatOwnerAuthSize = 16; + parameter int RotCreatorAuthOffset = 1064; + parameter int RotCreatorAuthSize = 1424; + parameter int RotCreatorAuthNonRawMfwCodesignKeyOffset = 1064; + parameter int RotCreatorAuthNonRawMfwCodesignKeySize = 160; + parameter int RotCreatorAuthOwnershipStateOffset = 1224; + parameter int RotCreatorAuthOwnershipStateSize = 4; + parameter int RotCreatorAuthRom2PatchSigverifyKeyOffset = 1228; + parameter int RotCreatorAuthRom2PatchSigverifyKeySize = 160; + parameter int RotCreatorAuthKeymanifestKeyOffset = 1388; + parameter int RotCreatorAuthKeymanifestKeySize = 160; + parameter int RotCreatorAuthUnlock4xferKeyOffset = 1548; + parameter int RotCreatorAuthUnlock4xferKeySize = 160; + parameter int RotCreatorAuthIdentityCertOffset = 1708; + parameter int RotCreatorAuthIdentityCertSize = 768; + parameter int RotCreatorAuthDigestOffset = 2480; + parameter int RotCreatorAuthDigestSize = 8; + parameter int RotOwnerAuthSlot0Offset = 2488; + parameter int RotOwnerAuthSlot0Size = 328; + parameter int RotOwnerAuthSlot0KeymanifestKeyOffset = 2488; + parameter int RotOwnerAuthSlot0KeymanifestKeySize = 160; + parameter int RotOwnerAuthSlot0Unlock4xferKeyOffset = 2648; + parameter int RotOwnerAuthSlot0Unlock4xferKeySize = 160; + parameter int RotOwnerAuthSlot0DigestOffset = 2808; + parameter int RotOwnerAuthSlot0DigestSize = 8; + parameter int RotOwnerAuthSlot1Offset = 2816; + parameter int RotOwnerAuthSlot1Size = 328; + parameter int RotOwnerAuthSlot1KeymanifestKeyOffset = 2816; + parameter int RotOwnerAuthSlot1KeymanifestKeySize = 160; + parameter int RotOwnerAuthSlot1Unlock4xferKeyOffset = 2976; + parameter int RotOwnerAuthSlot1Unlock4xferKeySize = 160; + parameter int RotOwnerAuthSlot1DigestOffset = 3136; + parameter int RotOwnerAuthSlot1DigestSize = 8; + parameter int PlatIntegAuthSlot0Offset = 3144; + parameter int PlatIntegAuthSlot0Size = 328; + parameter int PlatIntegAuthSlot0KeymanifestKeyOffset = 3144; + parameter int PlatIntegAuthSlot0KeymanifestKeySize = 160; + parameter int PlatIntegAuthSlot0Unlock4xferKeyOffset = 3304; + parameter int PlatIntegAuthSlot0Unlock4xferKeySize = 160; + parameter int PlatIntegAuthSlot0DigestOffset = 3464; + parameter int PlatIntegAuthSlot0DigestSize = 8; + parameter int PlatIntegAuthSlot1Offset = 3472; + parameter int PlatIntegAuthSlot1Size = 328; + parameter int PlatIntegAuthSlot1KeymanifestKeyOffset = 3472; + parameter int PlatIntegAuthSlot1KeymanifestKeySize = 160; + parameter int PlatIntegAuthSlot1Unlock4xferKeyOffset = 3632; + parameter int PlatIntegAuthSlot1Unlock4xferKeySize = 160; + parameter int PlatIntegAuthSlot1DigestOffset = 3792; + parameter int PlatIntegAuthSlot1DigestSize = 8; + parameter int PlatOwnerAuthSlot0Offset = 3800; + parameter int PlatOwnerAuthSlot0Size = 328; + parameter int PlatOwnerAuthSlot0KeymanifestKeyOffset = 3800; + parameter int PlatOwnerAuthSlot0KeymanifestKeySize = 160; + parameter int PlatOwnerAuthSlot0Unlock4xferKeyOffset = 3960; + parameter int PlatOwnerAuthSlot0Unlock4xferKeySize = 160; + parameter int PlatOwnerAuthSlot0DigestOffset = 4120; + parameter int PlatOwnerAuthSlot0DigestSize = 8; + parameter int PlatOwnerAuthSlot1Offset = 4128; + parameter int PlatOwnerAuthSlot1Size = 328; + parameter int PlatOwnerAuthSlot1KeymanifestKeyOffset = 4128; + parameter int PlatOwnerAuthSlot1KeymanifestKeySize = 160; + parameter int PlatOwnerAuthSlot1Unlock4xferKeyOffset = 4288; + parameter int PlatOwnerAuthSlot1Unlock4xferKeySize = 160; + parameter int PlatOwnerAuthSlot1DigestOffset = 4448; + parameter int PlatOwnerAuthSlot1DigestSize = 8; + parameter int PlatOwnerAuthSlot2Offset = 4456; + parameter int PlatOwnerAuthSlot2Size = 328; + parameter int PlatOwnerAuthSlot2KeymanifestKeyOffset = 4456; + parameter int PlatOwnerAuthSlot2KeymanifestKeySize = 160; + parameter int PlatOwnerAuthSlot2Unlock4xferKeyOffset = 4616; + parameter int PlatOwnerAuthSlot2Unlock4xferKeySize = 160; + parameter int PlatOwnerAuthSlot2DigestOffset = 4776; + parameter int PlatOwnerAuthSlot2DigestSize = 8; + parameter int PlatOwnerAuthSlot3Offset = 4784; + parameter int PlatOwnerAuthSlot3Size = 328; + parameter int PlatOwnerAuthSlot3KeymanifestKeyOffset = 4784; + parameter int PlatOwnerAuthSlot3KeymanifestKeySize = 160; + parameter int PlatOwnerAuthSlot3Unlock4xferKeyOffset = 4944; + parameter int PlatOwnerAuthSlot3Unlock4xferKeySize = 160; + parameter int PlatOwnerAuthSlot3DigestOffset = 5104; + parameter int PlatOwnerAuthSlot3DigestSize = 8; + parameter int ExtNvmOffset = 5112; + parameter int ExtNvmSize = 1024; + parameter int ExtNvmAntireplayFreshnessCntOffset = 5112; + parameter int ExtNvmAntireplayFreshnessCntSize = 1024; + parameter int RomPatchOffset = 6136; + parameter int RomPatchSize = 9848; + parameter int RomPatchDataOffset = 6136; + parameter int RomPatchDataSize = 9192; + parameter int RomPatchDigestOffset = 15976; + parameter int RomPatchDigestSize = 8; + parameter int HwCfg0Offset = 15984; + parameter int HwCfg0Size = 72; + parameter int DeviceIdOffset = 15984; + parameter int DeviceIdSize = 32; + parameter int ManufStateOffset = 16016; + parameter int ManufStateSize = 32; + parameter int HwCfg0DigestOffset = 16048; + parameter int HwCfg0DigestSize = 8; + parameter int HwCfg1Offset = 16056; + parameter int HwCfg1Size = 16; + parameter int SocDbgStateOffset = 16056; + parameter int SocDbgStateSize = 4; + parameter int EnCsrngSwAppReadOffset = 16060; + parameter int EnCsrngSwAppReadSize = 1; + parameter int EnSramIfetchOffset = 16061; + parameter int EnSramIfetchSize = 1; + parameter int HwCfg1DigestOffset = 16064; + parameter int HwCfg1DigestSize = 8; + parameter int Secret0Offset = 16072; + parameter int Secret0Size = 40; + parameter int TestUnlockTokenOffset = 16072; + parameter int TestUnlockTokenSize = 16; + parameter int TestExitTokenOffset = 16088; + parameter int TestExitTokenSize = 16; + parameter int Secret0DigestOffset = 16104; + parameter int Secret0DigestSize = 8; + parameter int Secret1Offset = 16112; + parameter int Secret1Size = 24; + parameter int SramDataKeySeedOffset = 16112; + parameter int SramDataKeySeedSize = 16; + parameter int Secret1DigestOffset = 16128; + parameter int Secret1DigestSize = 8; + parameter int Secret2Offset = 16136; + parameter int Secret2Size = 120; + parameter int RmaTokenOffset = 16136; + parameter int RmaTokenSize = 16; + parameter int CreatorRootKeyShare0Offset = 16152; + parameter int CreatorRootKeyShare0Size = 32; + parameter int CreatorRootKeyShare1Offset = 16184; + parameter int CreatorRootKeyShare1Size = 32; + parameter int CreatorSeedOffset = 16216; + parameter int CreatorSeedSize = 32; + parameter int Secret2DigestOffset = 16248; + parameter int Secret2DigestSize = 8; + parameter int Secret3Offset = 16256; + parameter int Secret3Size = 40; + parameter int OwnerSeedOffset = 16256; + parameter int OwnerSeedSize = 32; + parameter int Secret3DigestOffset = 16288; + parameter int Secret3DigestSize = 8; + parameter int LifeCycleOffset = 16296; + parameter int LifeCycleSize = 88; + parameter int LcTransitionCntOffset = 16296; + parameter int LcTransitionCntSize = 48; + parameter int LcStateOffset = 16344; + parameter int LcStateSize = 40; + parameter int NumAlerts = 5; + + // Address widths within the block + parameter int CoreAw = 15; + + // Number of registers for every interface + parameter int NumRegsCore = 95; + + // Alert indices + typedef enum int { + AlertFatalMacroErrorIdx = 0, + AlertFatalCheckErrorIdx = 1, + AlertFatalBusIntegErrorIdx = 2, + AlertFatalPrimOtpAlertIdx = 3, + AlertRecovPrimOtpAlertIdx = 4 + } otp_ctrl_alert_idx_t; + + /////////////////////////////////////////////// + // Typedefs for registers for core interface // + /////////////////////////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } otp_error; + struct packed { + logic q; + } otp_operation_done; + } otp_ctrl_reg2hw_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic q; + } otp_error; + struct packed { + logic q; + } otp_operation_done; + } otp_ctrl_reg2hw_intr_enable_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } otp_error; + struct packed { + logic q; + logic qe; + } otp_operation_done; + } otp_ctrl_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } recov_prim_otp_alert; + struct packed { + logic q; + logic qe; + } fatal_prim_otp_alert; + struct packed { + logic q; + logic qe; + } fatal_bus_integ_error; + struct packed { + logic q; + logic qe; + } fatal_check_error; + struct packed { + logic q; + logic qe; + } fatal_macro_error; + } otp_ctrl_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic q; + logic qe; + } otp_ctrl_reg2hw_direct_access_regwen_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } digest; + struct packed { + logic q; + logic qe; + } wr; + struct packed { + logic q; + logic qe; + } rd; + } otp_ctrl_reg2hw_direct_access_cmd_reg_t; + + typedef struct packed { + logic [13:0] q; + } otp_ctrl_reg2hw_direct_access_address_reg_t; + + typedef struct packed { + logic [31:0] q; + } otp_ctrl_reg2hw_direct_access_wdata_mreg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } consistency; + struct packed { + logic q; + logic qe; + } integrity; + } otp_ctrl_reg2hw_check_trigger_reg_t; + + typedef struct packed { + logic [31:0] q; + } otp_ctrl_reg2hw_check_timeout_reg_t; + + typedef struct packed { + logic [31:0] q; + } otp_ctrl_reg2hw_integrity_check_period_reg_t; + + typedef struct packed { + logic [31:0] q; + } otp_ctrl_reg2hw_consistency_check_period_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_vendor_test_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_ownership_slot_state_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_rot_creator_auth_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_rot_owner_auth_slot0_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_rot_owner_auth_slot1_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_plat_integ_auth_slot0_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_plat_integ_auth_slot1_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_plat_owner_auth_slot0_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_plat_owner_auth_slot1_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_plat_owner_auth_slot2_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_plat_owner_auth_slot3_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_ext_nvm_read_lock_reg_t; + + typedef struct packed { + logic q; + } otp_ctrl_reg2hw_rom_patch_read_lock_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } otp_error; + struct packed { + logic d; + logic de; + } otp_operation_done; + } otp_ctrl_hw2reg_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic d; + } check_pending; + struct packed { + logic d; + } dai_idle; + struct packed { + logic d; + } bus_integ_error; + struct packed { + logic d; + } key_deriv_fsm_error; + struct packed { + logic d; + } scrambling_fsm_error; + struct packed { + logic d; + } lfsr_fsm_error; + struct packed { + logic d; + } timeout_error; + struct packed { + logic d; + } lci_error; + struct packed { + logic d; + } dai_error; + struct packed { + logic d; + } life_cycle_error; + struct packed { + logic d; + } secret3_error; + struct packed { + logic d; + } secret2_error; + struct packed { + logic d; + } secret1_error; + struct packed { + logic d; + } secret0_error; + struct packed { + logic d; + } hw_cfg1_error; + struct packed { + logic d; + } hw_cfg0_error; + struct packed { + logic d; + } rom_patch_error; + struct packed { + logic d; + } ext_nvm_error; + struct packed { + logic d; + } plat_owner_auth_slot3_error; + struct packed { + logic d; + } plat_owner_auth_slot2_error; + struct packed { + logic d; + } plat_owner_auth_slot1_error; + struct packed { + logic d; + } plat_owner_auth_slot0_error; + struct packed { + logic d; + } plat_integ_auth_slot1_error; + struct packed { + logic d; + } plat_integ_auth_slot0_error; + struct packed { + logic d; + } rot_owner_auth_slot1_error; + struct packed { + logic d; + } rot_owner_auth_slot0_error; + struct packed { + logic d; + } rot_creator_auth_error; + struct packed { + logic d; + } ownership_slot_state_error; + struct packed { + logic d; + } owner_sw_cfg_error; + struct packed { + logic d; + } creator_sw_cfg_error; + struct packed { + logic d; + } vendor_test_error; + } otp_ctrl_hw2reg_status_reg_t; + + typedef struct packed { + logic [2:0] d; + } otp_ctrl_hw2reg_err_code_mreg_t; + + typedef struct packed { + logic d; + } otp_ctrl_hw2reg_direct_access_regwen_reg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_direct_access_rdata_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_vendor_test_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_rot_creator_auth_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_rot_owner_auth_slot0_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_rot_owner_auth_slot1_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_plat_integ_auth_slot0_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_plat_integ_auth_slot1_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_plat_owner_auth_slot0_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_plat_owner_auth_slot1_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_plat_owner_auth_slot2_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_plat_owner_auth_slot3_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_rom_patch_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_hw_cfg0_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_hw_cfg1_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_secret0_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_secret1_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_secret2_digest_mreg_t; + + typedef struct packed { + logic [31:0] d; + } otp_ctrl_hw2reg_secret3_digest_mreg_t; + + // Register -> HW type for core interface + typedef struct packed { + otp_ctrl_reg2hw_intr_state_reg_t intr_state; // [218:217] + otp_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [216:215] + otp_ctrl_reg2hw_intr_test_reg_t intr_test; // [214:211] + otp_ctrl_reg2hw_alert_test_reg_t alert_test; // [210:201] + otp_ctrl_reg2hw_direct_access_regwen_reg_t direct_access_regwen; // [200:199] + otp_ctrl_reg2hw_direct_access_cmd_reg_t direct_access_cmd; // [198:193] + otp_ctrl_reg2hw_direct_access_address_reg_t direct_access_address; // [192:179] + otp_ctrl_reg2hw_direct_access_wdata_mreg_t [1:0] direct_access_wdata; // [178:115] + otp_ctrl_reg2hw_check_trigger_reg_t check_trigger; // [114:111] + otp_ctrl_reg2hw_check_timeout_reg_t check_timeout; // [110:79] + otp_ctrl_reg2hw_integrity_check_period_reg_t integrity_check_period; // [78:47] + otp_ctrl_reg2hw_consistency_check_period_reg_t consistency_check_period; // [46:15] + otp_ctrl_reg2hw_vendor_test_read_lock_reg_t vendor_test_read_lock; // [14:14] + otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t creator_sw_cfg_read_lock; // [13:13] + otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t owner_sw_cfg_read_lock; // [12:12] + otp_ctrl_reg2hw_ownership_slot_state_read_lock_reg_t ownership_slot_state_read_lock; // [11:11] + otp_ctrl_reg2hw_rot_creator_auth_read_lock_reg_t rot_creator_auth_read_lock; // [10:10] + otp_ctrl_reg2hw_rot_owner_auth_slot0_read_lock_reg_t rot_owner_auth_slot0_read_lock; // [9:9] + otp_ctrl_reg2hw_rot_owner_auth_slot1_read_lock_reg_t rot_owner_auth_slot1_read_lock; // [8:8] + otp_ctrl_reg2hw_plat_integ_auth_slot0_read_lock_reg_t plat_integ_auth_slot0_read_lock; // [7:7] + otp_ctrl_reg2hw_plat_integ_auth_slot1_read_lock_reg_t plat_integ_auth_slot1_read_lock; // [6:6] + otp_ctrl_reg2hw_plat_owner_auth_slot0_read_lock_reg_t plat_owner_auth_slot0_read_lock; // [5:5] + otp_ctrl_reg2hw_plat_owner_auth_slot1_read_lock_reg_t plat_owner_auth_slot1_read_lock; // [4:4] + otp_ctrl_reg2hw_plat_owner_auth_slot2_read_lock_reg_t plat_owner_auth_slot2_read_lock; // [3:3] + otp_ctrl_reg2hw_plat_owner_auth_slot3_read_lock_reg_t plat_owner_auth_slot3_read_lock; // [2:2] + otp_ctrl_reg2hw_ext_nvm_read_lock_reg_t ext_nvm_read_lock; // [1:1] + otp_ctrl_reg2hw_rom_patch_read_lock_reg_t rom_patch_read_lock; // [0:0] + } otp_ctrl_core_reg2hw_t; + + // HW -> register type for core interface + typedef struct packed { + otp_ctrl_hw2reg_intr_state_reg_t intr_state; // [1387:1384] + otp_ctrl_hw2reg_status_reg_t status; // [1383:1353] + otp_ctrl_hw2reg_err_code_mreg_t [23:0] err_code; // [1352:1281] + otp_ctrl_hw2reg_direct_access_regwen_reg_t direct_access_regwen; // [1280:1280] + otp_ctrl_hw2reg_direct_access_rdata_mreg_t [1:0] direct_access_rdata; // [1279:1216] + otp_ctrl_hw2reg_vendor_test_digest_mreg_t [1:0] vendor_test_digest; // [1215:1152] + otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t [1:0] creator_sw_cfg_digest; // [1151:1088] + otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t [1:0] owner_sw_cfg_digest; // [1087:1024] + otp_ctrl_hw2reg_rot_creator_auth_digest_mreg_t [1:0] rot_creator_auth_digest; // [1023:960] + otp_ctrl_hw2reg_rot_owner_auth_slot0_digest_mreg_t [1:0] + rot_owner_auth_slot0_digest; // [959:896] + otp_ctrl_hw2reg_rot_owner_auth_slot1_digest_mreg_t [1:0] + rot_owner_auth_slot1_digest; // [895:832] + otp_ctrl_hw2reg_plat_integ_auth_slot0_digest_mreg_t [1:0] + plat_integ_auth_slot0_digest; // [831:768] + otp_ctrl_hw2reg_plat_integ_auth_slot1_digest_mreg_t [1:0] + plat_integ_auth_slot1_digest; // [767:704] + otp_ctrl_hw2reg_plat_owner_auth_slot0_digest_mreg_t [1:0] + plat_owner_auth_slot0_digest; // [703:640] + otp_ctrl_hw2reg_plat_owner_auth_slot1_digest_mreg_t [1:0] + plat_owner_auth_slot1_digest; // [639:576] + otp_ctrl_hw2reg_plat_owner_auth_slot2_digest_mreg_t [1:0] + plat_owner_auth_slot2_digest; // [575:512] + otp_ctrl_hw2reg_plat_owner_auth_slot3_digest_mreg_t [1:0] + plat_owner_auth_slot3_digest; // [511:448] + otp_ctrl_hw2reg_rom_patch_digest_mreg_t [1:0] rom_patch_digest; // [447:384] + otp_ctrl_hw2reg_hw_cfg0_digest_mreg_t [1:0] hw_cfg0_digest; // [383:320] + otp_ctrl_hw2reg_hw_cfg1_digest_mreg_t [1:0] hw_cfg1_digest; // [319:256] + otp_ctrl_hw2reg_secret0_digest_mreg_t [1:0] secret0_digest; // [255:192] + otp_ctrl_hw2reg_secret1_digest_mreg_t [1:0] secret1_digest; // [191:128] + otp_ctrl_hw2reg_secret2_digest_mreg_t [1:0] secret2_digest; // [127:64] + otp_ctrl_hw2reg_secret3_digest_mreg_t [1:0] secret3_digest; // [63:0] + } otp_ctrl_core_hw2reg_t; + + // Register offsets for core interface + parameter logic [CoreAw-1:0] OTP_CTRL_INTR_STATE_OFFSET = 15'h 0; + parameter logic [CoreAw-1:0] OTP_CTRL_INTR_ENABLE_OFFSET = 15'h 4; + parameter logic [CoreAw-1:0] OTP_CTRL_INTR_TEST_OFFSET = 15'h 8; + parameter logic [CoreAw-1:0] OTP_CTRL_ALERT_TEST_OFFSET = 15'h c; + parameter logic [CoreAw-1:0] OTP_CTRL_STATUS_OFFSET = 15'h 10; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_0_OFFSET = 15'h 14; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_1_OFFSET = 15'h 18; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_2_OFFSET = 15'h 1c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_3_OFFSET = 15'h 20; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_4_OFFSET = 15'h 24; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_5_OFFSET = 15'h 28; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_6_OFFSET = 15'h 2c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_7_OFFSET = 15'h 30; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_8_OFFSET = 15'h 34; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_9_OFFSET = 15'h 38; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_10_OFFSET = 15'h 3c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_11_OFFSET = 15'h 40; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_12_OFFSET = 15'h 44; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_13_OFFSET = 15'h 48; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_14_OFFSET = 15'h 4c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_15_OFFSET = 15'h 50; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_16_OFFSET = 15'h 54; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_17_OFFSET = 15'h 58; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_18_OFFSET = 15'h 5c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_19_OFFSET = 15'h 60; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_20_OFFSET = 15'h 64; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_21_OFFSET = 15'h 68; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_22_OFFSET = 15'h 6c; + parameter logic [CoreAw-1:0] OTP_CTRL_ERR_CODE_23_OFFSET = 15'h 70; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET = 15'h 74; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET = 15'h 78; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET = 15'h 7c; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET = 15'h 80; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET = 15'h 84; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET = 15'h 88; + parameter logic [CoreAw-1:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET = 15'h 8c; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET = 15'h 90; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TRIGGER_OFFSET = 15'h 94; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_REGWEN_OFFSET = 15'h 98; + parameter logic [CoreAw-1:0] OTP_CTRL_CHECK_TIMEOUT_OFFSET = 15'h 9c; + parameter logic [CoreAw-1:0] OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET = 15'h a0; + parameter logic [CoreAw-1:0] OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET = 15'h a4; + parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET = 15'h a8; + parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET = 15'h ac; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET = 15'h b0; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK_OFFSET = 15'h b4; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK_OFFSET = 15'h b8; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK_OFFSET = 15'h bc; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK_OFFSET = 15'h c0; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK_OFFSET = 15'h c4; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK_OFFSET = 15'h c8; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK_OFFSET = 15'h cc; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK_OFFSET = 15'h d0; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK_OFFSET = 15'h d4; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK_OFFSET = 15'h d8; + parameter logic [CoreAw-1:0] OTP_CTRL_EXT_NVM_READ_LOCK_OFFSET = 15'h dc; + parameter logic [CoreAw-1:0] OTP_CTRL_ROM_PATCH_READ_LOCK_OFFSET = 15'h e0; + parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET = 15'h e4; + parameter logic [CoreAw-1:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET = 15'h e8; + parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET = 15'h ec; + parameter logic [CoreAw-1:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET = 15'h f0; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET = 15'h f4; + parameter logic [CoreAw-1:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET = 15'h f8; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_OFFSET = 15'h fc; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_OFFSET = 15'h 100; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_OFFSET = 15'h 104; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_OFFSET = 15'h 108; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_OFFSET = 15'h 10c; + parameter logic [CoreAw-1:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_OFFSET = 15'h 110; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_OFFSET = 15'h 114; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_OFFSET = 15'h 118; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_OFFSET = 15'h 11c; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_OFFSET = 15'h 120; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_OFFSET = 15'h 124; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_OFFSET = 15'h 128; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_OFFSET = 15'h 12c; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_OFFSET = 15'h 130; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_OFFSET = 15'h 134; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_OFFSET = 15'h 138; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_OFFSET = 15'h 13c; + parameter logic [CoreAw-1:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_OFFSET = 15'h 140; + parameter logic [CoreAw-1:0] OTP_CTRL_ROM_PATCH_DIGEST_0_OFFSET = 15'h 144; + parameter logic [CoreAw-1:0] OTP_CTRL_ROM_PATCH_DIGEST_1_OFFSET = 15'h 148; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG0_DIGEST_0_OFFSET = 15'h 14c; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG0_DIGEST_1_OFFSET = 15'h 150; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG1_DIGEST_0_OFFSET = 15'h 154; + parameter logic [CoreAw-1:0] OTP_CTRL_HW_CFG1_DIGEST_1_OFFSET = 15'h 158; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_0_OFFSET = 15'h 15c; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET0_DIGEST_1_OFFSET = 15'h 160; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_0_OFFSET = 15'h 164; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET1_DIGEST_1_OFFSET = 15'h 168; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_0_OFFSET = 15'h 16c; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET2_DIGEST_1_OFFSET = 15'h 170; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET3_DIGEST_0_OFFSET = 15'h 174; + parameter logic [CoreAw-1:0] OTP_CTRL_SECRET3_DIGEST_1_OFFSET = 15'h 178; + + // Reset values for hwext registers and their fields for core interface + parameter logic [1:0] OTP_CTRL_INTR_TEST_RESVAL = 2'h 0; + parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL = 1'h 0; + parameter logic [4:0] OTP_CTRL_ALERT_TEST_RESVAL = 5'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_FATAL_PRIM_OTP_ALERT_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_ALERT_TEST_RECOV_PRIM_OTP_ALERT_RESVAL = 1'h 0; + parameter logic [30:0] OTP_CTRL_STATUS_RESVAL = 31'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_OWNERSHIP_SLOT_STATE_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_ROT_CREATOR_AUTH_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_ROT_OWNER_AUTH_SLOT0_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_ROT_OWNER_AUTH_SLOT1_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_PLAT_INTEG_AUTH_SLOT0_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_PLAT_INTEG_AUTH_SLOT1_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT0_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT1_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT2_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_PLAT_OWNER_AUTH_SLOT3_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_EXT_NVM_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_ROM_PATCH_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_HW_CFG0_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_HW_CFG1_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_SECRET3_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_DAI_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_LCI_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_DAI_IDLE_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_STATUS_CHECK_PENDING_RESVAL = 1'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_0_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_0_ERR_CODE_0_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_1_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_1_ERR_CODE_1_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_2_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_2_ERR_CODE_2_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_3_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_3_ERR_CODE_3_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_4_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_4_ERR_CODE_4_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_5_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_5_ERR_CODE_5_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_6_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_6_ERR_CODE_6_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_7_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_7_ERR_CODE_7_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_8_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_8_ERR_CODE_8_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_9_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_9_ERR_CODE_9_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_10_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_10_ERR_CODE_10_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_11_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_11_ERR_CODE_11_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_12_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_12_ERR_CODE_12_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_13_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_13_ERR_CODE_13_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_14_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_14_ERR_CODE_14_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_15_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_15_ERR_CODE_15_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_16_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_16_ERR_CODE_16_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_17_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_17_ERR_CODE_17_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_18_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_18_ERR_CODE_18_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_19_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_19_ERR_CODE_19_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_20_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_20_ERR_CODE_20_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_21_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_21_ERR_CODE_21_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_22_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_22_ERR_CODE_22_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_23_RESVAL = 3'h 0; + parameter logic [2:0] OTP_CTRL_ERR_CODE_23_ERR_CODE_23_RESVAL = 3'h 0; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL = 1'h 1; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL = 1'h 1; + parameter logic [2:0] OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL = 3'h 0; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL = 1'h 0; + parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL = 32'h 0; + parameter logic [1:0] OTP_CTRL_CHECK_TRIGGER_RESVAL = 2'h 0; + parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL = 1'h 0; + parameter logic [0:0] OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL = 1'h 0; + parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_ROT_CREATOR_AUTH_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1_ROT_CREATOR_AUTH_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_ROT_OWNER_AUTH_SLOT0_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1_ROT_OWNER_AUTH_SLOT0_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_ROT_OWNER_AUTH_SLOT1_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1_ROT_OWNER_AUTH_SLOT1_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_PLAT_INTEG_AUTH_SLOT0_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_PLAT_INTEG_AUTH_SLOT1_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_PLAT_OWNER_AUTH_SLOT0_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_PLAT_OWNER_AUTH_SLOT1_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_PLAT_OWNER_AUTH_SLOT2_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] + OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_PLAT_OWNER_AUTH_SLOT3_DIGEST_1_RESVAL = + 32'h 0; + parameter logic [31:0] OTP_CTRL_ROM_PATCH_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_ROM_PATCH_DIGEST_0_ROM_PATCH_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_ROM_PATCH_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_ROM_PATCH_DIGEST_1_ROM_PATCH_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG0_DIGEST_0_HW_CFG0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG0_DIGEST_1_HW_CFG0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG1_DIGEST_0_HW_CFG1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_HW_CFG1_DIGEST_1_HW_CFG1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET3_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET3_DIGEST_0_SECRET3_DIGEST_0_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET3_DIGEST_1_RESVAL = 32'h 0; + parameter logic [31:0] OTP_CTRL_SECRET3_DIGEST_1_SECRET3_DIGEST_1_RESVAL = 32'h 0; + + // Window parameters for core interface + parameter logic [CoreAw-1:0] OTP_CTRL_SW_CFG_WINDOW_OFFSET = 15'h 4000; + parameter int unsigned OTP_CTRL_SW_CFG_WINDOW_SIZE = 'h 4000; + parameter int unsigned OTP_CTRL_SW_CFG_WINDOW_IDX = 0; + + // Register index for core interface + typedef enum int { + OTP_CTRL_INTR_STATE, + OTP_CTRL_INTR_ENABLE, + OTP_CTRL_INTR_TEST, + OTP_CTRL_ALERT_TEST, + OTP_CTRL_STATUS, + OTP_CTRL_ERR_CODE_0, + OTP_CTRL_ERR_CODE_1, + OTP_CTRL_ERR_CODE_2, + OTP_CTRL_ERR_CODE_3, + OTP_CTRL_ERR_CODE_4, + OTP_CTRL_ERR_CODE_5, + OTP_CTRL_ERR_CODE_6, + OTP_CTRL_ERR_CODE_7, + OTP_CTRL_ERR_CODE_8, + OTP_CTRL_ERR_CODE_9, + OTP_CTRL_ERR_CODE_10, + OTP_CTRL_ERR_CODE_11, + OTP_CTRL_ERR_CODE_12, + OTP_CTRL_ERR_CODE_13, + OTP_CTRL_ERR_CODE_14, + OTP_CTRL_ERR_CODE_15, + OTP_CTRL_ERR_CODE_16, + OTP_CTRL_ERR_CODE_17, + OTP_CTRL_ERR_CODE_18, + OTP_CTRL_ERR_CODE_19, + OTP_CTRL_ERR_CODE_20, + OTP_CTRL_ERR_CODE_21, + OTP_CTRL_ERR_CODE_22, + OTP_CTRL_ERR_CODE_23, + OTP_CTRL_DIRECT_ACCESS_REGWEN, + OTP_CTRL_DIRECT_ACCESS_CMD, + OTP_CTRL_DIRECT_ACCESS_ADDRESS, + OTP_CTRL_DIRECT_ACCESS_WDATA_0, + OTP_CTRL_DIRECT_ACCESS_WDATA_1, + OTP_CTRL_DIRECT_ACCESS_RDATA_0, + OTP_CTRL_DIRECT_ACCESS_RDATA_1, + OTP_CTRL_CHECK_TRIGGER_REGWEN, + OTP_CTRL_CHECK_TRIGGER, + OTP_CTRL_CHECK_REGWEN, + OTP_CTRL_CHECK_TIMEOUT, + OTP_CTRL_INTEGRITY_CHECK_PERIOD, + OTP_CTRL_CONSISTENCY_CHECK_PERIOD, + OTP_CTRL_VENDOR_TEST_READ_LOCK, + OTP_CTRL_CREATOR_SW_CFG_READ_LOCK, + OTP_CTRL_OWNER_SW_CFG_READ_LOCK, + OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK, + OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK, + OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK, + OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK, + OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK, + OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK, + OTP_CTRL_EXT_NVM_READ_LOCK, + OTP_CTRL_ROM_PATCH_READ_LOCK, + OTP_CTRL_VENDOR_TEST_DIGEST_0, + OTP_CTRL_VENDOR_TEST_DIGEST_1, + OTP_CTRL_CREATOR_SW_CFG_DIGEST_0, + OTP_CTRL_CREATOR_SW_CFG_DIGEST_1, + OTP_CTRL_OWNER_SW_CFG_DIGEST_0, + OTP_CTRL_OWNER_SW_CFG_DIGEST_1, + OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0, + OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1, + OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0, + OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1, + OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0, + OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1, + OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0, + OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1, + OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0, + OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0, + OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1, + OTP_CTRL_ROM_PATCH_DIGEST_0, + OTP_CTRL_ROM_PATCH_DIGEST_1, + OTP_CTRL_HW_CFG0_DIGEST_0, + OTP_CTRL_HW_CFG0_DIGEST_1, + OTP_CTRL_HW_CFG1_DIGEST_0, + OTP_CTRL_HW_CFG1_DIGEST_1, + OTP_CTRL_SECRET0_DIGEST_0, + OTP_CTRL_SECRET0_DIGEST_1, + OTP_CTRL_SECRET1_DIGEST_0, + OTP_CTRL_SECRET1_DIGEST_1, + OTP_CTRL_SECRET2_DIGEST_0, + OTP_CTRL_SECRET2_DIGEST_1, + OTP_CTRL_SECRET3_DIGEST_0, + OTP_CTRL_SECRET3_DIGEST_1 + } otp_ctrl_core_id_e; + + // Register width information to check illegal writes for core interface + parameter logic [3:0] OTP_CTRL_CORE_PERMIT [95] = '{ + 4'b 0001, // index[ 0] OTP_CTRL_INTR_STATE + 4'b 0001, // index[ 1] OTP_CTRL_INTR_ENABLE + 4'b 0001, // index[ 2] OTP_CTRL_INTR_TEST + 4'b 0001, // index[ 3] OTP_CTRL_ALERT_TEST + 4'b 1111, // index[ 4] OTP_CTRL_STATUS + 4'b 0001, // index[ 5] OTP_CTRL_ERR_CODE_0 + 4'b 0001, // index[ 6] OTP_CTRL_ERR_CODE_1 + 4'b 0001, // index[ 7] OTP_CTRL_ERR_CODE_2 + 4'b 0001, // index[ 8] OTP_CTRL_ERR_CODE_3 + 4'b 0001, // index[ 9] OTP_CTRL_ERR_CODE_4 + 4'b 0001, // index[10] OTP_CTRL_ERR_CODE_5 + 4'b 0001, // index[11] OTP_CTRL_ERR_CODE_6 + 4'b 0001, // index[12] OTP_CTRL_ERR_CODE_7 + 4'b 0001, // index[13] OTP_CTRL_ERR_CODE_8 + 4'b 0001, // index[14] OTP_CTRL_ERR_CODE_9 + 4'b 0001, // index[15] OTP_CTRL_ERR_CODE_10 + 4'b 0001, // index[16] OTP_CTRL_ERR_CODE_11 + 4'b 0001, // index[17] OTP_CTRL_ERR_CODE_12 + 4'b 0001, // index[18] OTP_CTRL_ERR_CODE_13 + 4'b 0001, // index[19] OTP_CTRL_ERR_CODE_14 + 4'b 0001, // index[20] OTP_CTRL_ERR_CODE_15 + 4'b 0001, // index[21] OTP_CTRL_ERR_CODE_16 + 4'b 0001, // index[22] OTP_CTRL_ERR_CODE_17 + 4'b 0001, // index[23] OTP_CTRL_ERR_CODE_18 + 4'b 0001, // index[24] OTP_CTRL_ERR_CODE_19 + 4'b 0001, // index[25] OTP_CTRL_ERR_CODE_20 + 4'b 0001, // index[26] OTP_CTRL_ERR_CODE_21 + 4'b 0001, // index[27] OTP_CTRL_ERR_CODE_22 + 4'b 0001, // index[28] OTP_CTRL_ERR_CODE_23 + 4'b 0001, // index[29] OTP_CTRL_DIRECT_ACCESS_REGWEN + 4'b 0001, // index[30] OTP_CTRL_DIRECT_ACCESS_CMD + 4'b 0011, // index[31] OTP_CTRL_DIRECT_ACCESS_ADDRESS + 4'b 1111, // index[32] OTP_CTRL_DIRECT_ACCESS_WDATA_0 + 4'b 1111, // index[33] OTP_CTRL_DIRECT_ACCESS_WDATA_1 + 4'b 1111, // index[34] OTP_CTRL_DIRECT_ACCESS_RDATA_0 + 4'b 1111, // index[35] OTP_CTRL_DIRECT_ACCESS_RDATA_1 + 4'b 0001, // index[36] OTP_CTRL_CHECK_TRIGGER_REGWEN + 4'b 0001, // index[37] OTP_CTRL_CHECK_TRIGGER + 4'b 0001, // index[38] OTP_CTRL_CHECK_REGWEN + 4'b 1111, // index[39] OTP_CTRL_CHECK_TIMEOUT + 4'b 1111, // index[40] OTP_CTRL_INTEGRITY_CHECK_PERIOD + 4'b 1111, // index[41] OTP_CTRL_CONSISTENCY_CHECK_PERIOD + 4'b 0001, // index[42] OTP_CTRL_VENDOR_TEST_READ_LOCK + 4'b 0001, // index[43] OTP_CTRL_CREATOR_SW_CFG_READ_LOCK + 4'b 0001, // index[44] OTP_CTRL_OWNER_SW_CFG_READ_LOCK + 4'b 0001, // index[45] OTP_CTRL_OWNERSHIP_SLOT_STATE_READ_LOCK + 4'b 0001, // index[46] OTP_CTRL_ROT_CREATOR_AUTH_READ_LOCK + 4'b 0001, // index[47] OTP_CTRL_ROT_OWNER_AUTH_SLOT0_READ_LOCK + 4'b 0001, // index[48] OTP_CTRL_ROT_OWNER_AUTH_SLOT1_READ_LOCK + 4'b 0001, // index[49] OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_READ_LOCK + 4'b 0001, // index[50] OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_READ_LOCK + 4'b 0001, // index[51] OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_READ_LOCK + 4'b 0001, // index[52] OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_READ_LOCK + 4'b 0001, // index[53] OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_READ_LOCK + 4'b 0001, // index[54] OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_READ_LOCK + 4'b 0001, // index[55] OTP_CTRL_EXT_NVM_READ_LOCK + 4'b 0001, // index[56] OTP_CTRL_ROM_PATCH_READ_LOCK + 4'b 1111, // index[57] OTP_CTRL_VENDOR_TEST_DIGEST_0 + 4'b 1111, // index[58] OTP_CTRL_VENDOR_TEST_DIGEST_1 + 4'b 1111, // index[59] OTP_CTRL_CREATOR_SW_CFG_DIGEST_0 + 4'b 1111, // index[60] OTP_CTRL_CREATOR_SW_CFG_DIGEST_1 + 4'b 1111, // index[61] OTP_CTRL_OWNER_SW_CFG_DIGEST_0 + 4'b 1111, // index[62] OTP_CTRL_OWNER_SW_CFG_DIGEST_1 + 4'b 1111, // index[63] OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0 + 4'b 1111, // index[64] OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_1 + 4'b 1111, // index[65] OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0 + 4'b 1111, // index[66] OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_1 + 4'b 1111, // index[67] OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0 + 4'b 1111, // index[68] OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_1 + 4'b 1111, // index[69] OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0 + 4'b 1111, // index[70] OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_1 + 4'b 1111, // index[71] OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0 + 4'b 1111, // index[72] OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_1 + 4'b 1111, // index[73] OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0 + 4'b 1111, // index[74] OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_1 + 4'b 1111, // index[75] OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0 + 4'b 1111, // index[76] OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_1 + 4'b 1111, // index[77] OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0 + 4'b 1111, // index[78] OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_1 + 4'b 1111, // index[79] OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0 + 4'b 1111, // index[80] OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_1 + 4'b 1111, // index[81] OTP_CTRL_ROM_PATCH_DIGEST_0 + 4'b 1111, // index[82] OTP_CTRL_ROM_PATCH_DIGEST_1 + 4'b 1111, // index[83] OTP_CTRL_HW_CFG0_DIGEST_0 + 4'b 1111, // index[84] OTP_CTRL_HW_CFG0_DIGEST_1 + 4'b 1111, // index[85] OTP_CTRL_HW_CFG1_DIGEST_0 + 4'b 1111, // index[86] OTP_CTRL_HW_CFG1_DIGEST_1 + 4'b 1111, // index[87] OTP_CTRL_SECRET0_DIGEST_0 + 4'b 1111, // index[88] OTP_CTRL_SECRET0_DIGEST_1 + 4'b 1111, // index[89] OTP_CTRL_SECRET1_DIGEST_0 + 4'b 1111, // index[90] OTP_CTRL_SECRET1_DIGEST_1 + 4'b 1111, // index[91] OTP_CTRL_SECRET2_DIGEST_0 + 4'b 1111, // index[92] OTP_CTRL_SECRET2_DIGEST_1 + 4'b 1111, // index[93] OTP_CTRL_SECRET3_DIGEST_0 + 4'b 1111 // index[94] OTP_CTRL_SECRET3_DIGEST_1 + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_scrmbl.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_scrmbl.sv new file mode 100644 index 00000000000..56ee61f0bc2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_scrmbl.sv @@ -0,0 +1,512 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This module contains the scrambling datapath for the OTP controller. It basically consists of +// two single-round PRESENT primitives (one for encryption and one for decryption mode), a counter +// with a simple FSM and four working registers, as listed below. +// +// key_state_q (128bit): working register to hold the round key (needed for the key schedule). +// +// data_state_q (64bit): working register to hold the data state in between rounds. +// +// data_shadow_q (64bit): shadow register for holding a second 64bit block of input data. This is +// used to form a 128bit data block for the digest mode, which has a block +// size of 128bit. +// +// digest_state_q (64bit): register to hold the digest state in between digest updates. Technically, +// this is not needed when the data for the digest is fed into this block +// back-to-back. However, the partition integrity checks require that it is +// possible to interleave encryption operations and digest update steps, +// hence an additional state register is needed, as otherwise the digest +// state would be lost. +// +// The scrambling datapath is arranged such that it can also be used for calculating a digest using +// the encryption primitive in a Merkle-Damgard construction. To that end, the PRESENT block cipher +// is turned into a one way function according to the Davies-Meyer scheme. Note however that this +// makes the digest block size 128bit wide, since the Merkle-Damgard construction leverages the +// cipher key input to ingest data. +// +// The scrambling datapath exposes a few simple commands and the FSM hides the complexity +// of steering the appropriate muxes and keeping track of the cipher rounds. These commands are +// briefly explained below. +// +// Decrypt: This decrypts the data block provided via data_i with the key at index sel_i. +// +// Encrypt: This encrypts the data block provided via data_i with the key at index sel_i. +// In addition, this command copies the prvious result into a shadow register before +// the first encryption round for later use in the digest (see description further below). +// This enables interleaved encrypt/digest operation needed for the integrity checks of +// the secret partitions. +// +// LoadShadow: In "StandardMode", the LoadShadow command loads the data provided via data_i into a +// shadow register that is mapped to the lower 64bit of the 128bit digest input data +// block. In "ChainedMode", this command copies the contents of the data state register +// into the shadow register. +// +// DigestInit: This ensures that the digest initialization vector (IV) is selected upon the next +// call of the Digest command. Also, mode_i can be used to set the digest mode. If +// mode_i is set to "StandardMode", the data to be digested has to be provided via +// data_i and LoadShadow. If mode_i is set to "ChainedMode", the digest input is formed +// by concatenating the results of the previous two encryption commands. +// +// Digest: In "StandardMode", this command concatenates the data input supplied via data_i with +// the shadow register in order to form a 128bit block ({data_i, data_shadow_q}). This block +// is then used to encrypt the digest state. In "ChainedMode" digest mode, the 128bit block +// to be digested is formed by concatenating {data_state_q, data_shadow_q}. If a DigestInit +// command has been executed right before calling Digest, the IV selected with sel_i is +// used to initialize the state. +// +// DigestFinalize: This command encrypts the digest state with the finalization constant selected +// by sel_i in order to form the final digest. +// +// References: +// - The block diagram in ../doc/theory_of_operation.md +// - https://opentitan.org/book/hw/ip/prim/doc/prim_present.html +// - https://en.wikipedia.org/wiki/Merkle-Damgard_construction +// - https://en.wikipedia.org/wiki/One-way_compression_function#Davies%E2%80%93Meyer +// - https://en.wikipedia.org/wiki/PRESENT +// - http://www.lightweightcrypto.org/present/present_ches2007.pdf +// + +`include "prim_flop_macros.sv" + +module otp_ctrl_scrmbl + import otp_ctrl_pkg::*; + import otp_ctrl_top_specific_pkg::*; + import otp_ctrl_part_pkg::*; +( + input clk_i, + input rst_ni, + // input data and command + input otp_scrmbl_cmd_e cmd_i, + input digest_mode_e mode_i, + input [ConstSelWidth-1:0] sel_i, + input [ScrmblBlockWidth-1:0] data_i, + input valid_i, + output logic ready_o, + // output data + output logic [ScrmblBlockWidth-1:0] data_o, + output logic valid_o, + // escalation input and FSM error indication + input lc_ctrl_pkg::lc_tx_t escalate_en_i, + output logic fsm_err_o +); + + import prim_util_pkg::vbits; + + //////////////////////// + // Decryption Key LUT // + //////////////////////// + + // Anchor keys, constants and IVs + key_array_t rnd_cnst_key_anchor; + digest_const_array_t rnd_cnst_digest_anchor; + digest_iv_array_t rnd_cnst_digest_iv_anchor; + + for (genvar i = 0; i < NumScrmblKeys; i++) begin : gen_anchor_keys + prim_sec_anchor_buf #( + .Width(ScrmblKeyWidth) + ) u_key_anchor_buf ( + .in_i(RndCnstKey[i]), + .out_o(rnd_cnst_key_anchor[i]) + ); + end + + for (genvar i = 0; i < NumDigestSets; i++) begin : gen_anchor_digests + prim_sec_anchor_buf #( + .Width(ScrmblKeyWidth) + ) u_const_anchor_buf ( + .in_i(RndCnstDigestConst[i]), + .out_o(rnd_cnst_digest_anchor[i]) + ); + + prim_sec_anchor_buf #( + .Width(ScrmblBlockWidth) + ) u_iv_anchor_buf ( + .in_i(RndCnstDigestIV[i]), + .out_o(rnd_cnst_digest_iv_anchor[i]) + ); + end + + + // Align these arrays to power of 2's to prevent X's in the muxing operations further below. + logic [2**$clog2(NumScrmblKeys)-1:0][ScrmblKeyWidth-1:0] otp_enc_key_lut; + logic [2**$clog2(NumScrmblKeys)-1:0][ScrmblKeyWidth-1:0] otp_dec_key_lut; + logic [2**$clog2(NumDigestSets)-1:0][ScrmblKeyWidth-1:0] digest_const_lut; + logic [2**$clog2(NumDigestSets)-1:0][ScrmblBlockWidth-1:0] digest_iv_lut; + + // This pre-calculates the inverse scrambling keys at elab time. + `ASSERT_INIT(NumMaxPresentRounds_A, NumPresentRounds <= 31) + + always_comb begin : p_luts + otp_enc_key_lut = '0; + otp_dec_key_lut = '0; + digest_const_lut = '0; + digest_iv_lut = '0; + + for (int k = 0; k < NumScrmblKeys; k++) begin + localparam logic [4:0] NumRounds = 5'(unsigned'(NumPresentRounds)); + otp_enc_key_lut[k] = rnd_cnst_key_anchor[k]; + // Due to the PRESENT key schedule, we have to step the key schedule function by + // NumPresentRounds forwards to get the decryption key. + otp_dec_key_lut[k] = + prim_cipher_pkg::present_get_dec_key128(rnd_cnst_key_anchor[k], NumRounds); + end + + for (int k = 0; k < NumDigestSets; k++) begin + digest_const_lut[k] = rnd_cnst_digest_anchor[k]; + digest_iv_lut[k] = rnd_cnst_digest_iv_anchor[k]; + end + end + `ASSERT_KNOWN(EncKeyLutKnown_A, otp_enc_key_lut) + `ASSERT_KNOWN(DecKeyLutKnown_A, otp_dec_key_lut) + `ASSERT_KNOWN(DigestConstLutKnown_A, digest_const_lut) + `ASSERT_KNOWN(DigestIvLutKnown_A, digest_iv_lut) + + ////////////// + // Datapath // + ////////////// + + logic [4:0] idx_state_d, idx_state_q; + logic [ScrmblKeyWidth-1:0] key_state_d, key_state_q; + logic [ScrmblBlockWidth-1:0] data_state_d, data_state_q, data_shadow_q; + logic [ScrmblBlockWidth-1:0] digest_state_d, digest_state_q; + logic [ScrmblBlockWidth-1:0] enc_data_out, enc_data_out_xor, dec_data_out; + logic [ScrmblKeyWidth-1:0] dec_key_out, enc_key_out; + logic [4:0] dec_idx_out, enc_idx_out; + logic [ScrmblKeyWidth-1:0] otp_digest_const_mux, otp_enc_key_mux, otp_dec_key_mux; + logic [ScrmblBlockWidth-1:0] otp_digest_iv_mux; + + typedef enum logic [2:0] {SelEncDataOut, + SelDecDataOut, + SelDigestState, + SelEncDataOutXor, + SelDataInput} data_state_sel_e; + + typedef enum logic [2:0] {SelDecKeyOut, + SelEncKeyOut, + SelDecKeyInit, + SelEncKeyInit, + SelDigestConst, + SelDigestInput, + SelDigestChained} key_state_sel_e; + + logic digest_init; + data_state_sel_e data_state_sel; + key_state_sel_e key_state_sel; + logic data_state_en, data_shadow_copy, data_shadow_load, digest_state_en, key_state_en; + digest_mode_e digest_mode_d, digest_mode_q; + + assign otp_enc_key_mux = otp_enc_key_lut[ScrmblKeySelWidth'(sel_i)]; + assign otp_dec_key_mux = otp_dec_key_lut[ScrmblKeySelWidth'(sel_i)]; + assign otp_digest_const_mux = digest_const_lut[DigestSetSelWidth'(sel_i)]; + assign otp_digest_iv_mux = digest_iv_lut[DigestSetSelWidth'(sel_i)]; + + // Make sure we always select a valid key / digest constant. + `ASSERT(CheckNumEncKeys_A, key_state_sel == SelEncKeyInit |-> sel_i < NumScrmblKeys) + `ASSERT(CheckNumDecKeys_A, key_state_sel == SelDecKeyInit |-> sel_i < NumScrmblKeys) + `ASSERT(CheckNumDigest1_A, key_state_sel == SelDigestConst |-> sel_i < NumDigestSets) + + assign data_state_d = (data_state_sel == SelEncDataOut) ? enc_data_out : + (data_state_sel == SelDecDataOut) ? dec_data_out : + (data_state_sel == SelDigestState) ? digest_state_q : + (data_state_sel == SelEncDataOutXor) ? enc_data_out_xor : + data_i; + + assign key_state_d = (key_state_sel == SelDecKeyOut) ? dec_key_out : + (key_state_sel == SelEncKeyOut) ? enc_key_out : + (key_state_sel == SelDecKeyInit) ? otp_dec_key_mux : + (key_state_sel == SelEncKeyInit) ? otp_enc_key_mux : + (key_state_sel == SelDigestConst) ? otp_digest_const_mux : + (key_state_sel == SelDigestChained) ? {data_state_q, data_shadow_q} : + {data_i, data_shadow_q}; + + // Initialize the round index state with 1 in all cases, except for the decrypt operation. + assign idx_state_d = (key_state_sel == SelDecKeyOut) ? dec_idx_out : + (key_state_sel == SelEncKeyOut) ? enc_idx_out : + (key_state_sel == SelDecKeyInit) ? unsigned'(5'(NumPresentRounds)) : + 5'd1; + + // The XOR is for the Davies-Mayer one-way function construction. + assign enc_data_out_xor = enc_data_out ^ digest_state_q; + assign digest_state_d = (digest_init) ? otp_digest_iv_mux : enc_data_out_xor; + + logic valid_q; //valid_d defined below + assign data_o = (valid_q) ? data_state_q : 0; + + ///////// + // FSM // + ///////// + + // SEC_CM: SCRMBL.FSM.SPARSE + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 5 -n 9 \ + // -s 2193087944 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (60.00%) + // 6: ||||||||||||| (40.00%) + // 7: -- + // 8: -- + // 9: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 4 + // Maximum Hamming weight: 7 + // + localparam int StateWidth = 9; + typedef enum logic [StateWidth-1:0] { + IdleSt = 9'b100011001, + DecryptSt = 9'b101101111, + EncryptSt = 9'b010010111, + DigestSt = 9'b111000010, + ErrorSt = 9'b011111000 + } state_e; + + localparam int CntWidth = $clog2(NumPresentRounds+1); + localparam int unsigned LastPresentRoundInt = NumPresentRounds - 1; + localparam bit [CntWidth-1:0] LastPresentRound = LastPresentRoundInt[CntWidth-1:0]; + + state_e state_d, state_q; + logic [CntWidth-1:0] cnt; + logic cnt_clr, cnt_en, cnt_err; + logic valid_d; //valid_q defined above + + assign valid_o = valid_q; + + // SEC_CM: SCRMBL.CTR.REDUN + prim_count #( + .Width(CntWidth) + ) u_prim_count ( + .clk_i, + .rst_ni, + .clr_i(cnt_clr), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(cnt_en), + .decr_en_i(1'b0), + .step_i(CntWidth'(1)), + .commit_i(1'b1), + .cnt_o(cnt), + .cnt_after_commit_o(), + .err_o(cnt_err) + ); + + always_comb begin : p_fsm + state_d = state_q; + digest_mode_d = digest_mode_q; + data_state_sel = SelDataInput; + key_state_sel = SelDigestInput; + digest_init = 1'b0; + data_state_en = 1'b0; + data_shadow_copy = 1'b0; + data_shadow_load = 1'b0; + key_state_en = 1'b0; + digest_state_en = 1'b0; + cnt_en = 1'b0; + cnt_clr = 1'b0; + valid_d = 1'b0; + ready_o = 1'b0; + fsm_err_o = 1'b0; + + unique case (state_q) + /////////////////////////////////////////////////////////////////// + // Idle State: decode command and + // load working regs accordingly + IdleSt: begin + cnt_clr = 1'b1; + ready_o = 1'b1; + + if (valid_i) begin + unique case (cmd_i) + Decrypt: begin + state_d = DecryptSt; + key_state_sel = SelDecKeyInit; + data_state_en = 1'b1; + key_state_en = 1'b1; + end + Encrypt: begin + state_d = EncryptSt; + key_state_sel = SelEncKeyInit; + data_state_en = 1'b1; + key_state_en = 1'b1; + end + LoadShadow: begin + if (digest_mode_q == ChainedMode) begin + data_shadow_copy = 1'b1; + end else begin + data_shadow_load = 1'b1; + end + end + Digest: begin + state_d = DigestSt; + data_state_sel = SelDigestState; + key_state_sel = (digest_mode_q == ChainedMode) ? SelDigestChained : SelDigestInput; + data_state_en = 1'b1; + key_state_en = 1'b1; + end + DigestInit: begin + digest_mode_d = mode_i; + digest_init = 1'b1; + digest_state_en = 1'b1; + end + DigestFinalize: begin + state_d = DigestSt; + data_state_sel = SelDigestState; + key_state_sel = SelDigestConst; + data_state_en = 1'b1; + key_state_en = 1'b1; + digest_mode_d = StandardMode; + end + default: ; // ignore + endcase // cmd_i + end + end + /////////////////////////////////////////////////////////////////// + // Perform decrypt rounds. + DecryptSt: begin + data_state_sel = SelDecDataOut; + key_state_sel = SelDecKeyOut; + data_state_en = 1'b1; + key_state_en = 1'b1; + cnt_en = 1'b1; + if (cnt == LastPresentRound) begin + state_d = IdleSt; + valid_d = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Perform encrypt rounds. + EncryptSt: begin + data_state_sel = SelEncDataOut; + key_state_sel = SelEncKeyOut; + data_state_en = 1'b1; + key_state_en = 1'b1; + cnt_en = 1'b1; + if (cnt == LastPresentRound) begin + state_d = IdleSt; + valid_d = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // The digest is calculated with a Merkle-Damgard construction that + // employs the PRESENT encryption datapath. + DigestSt: begin + data_state_sel = SelEncDataOut; + key_state_sel = SelEncKeyOut; + data_state_en = 1'b1; + key_state_en = 1'b1; + cnt_en = 1'b1; + if (cnt == LastPresentRound) begin + state_d = IdleSt; + valid_d = 1'b1; + // Apply XOR for Davies-Meyer construction. + data_state_sel = SelEncDataOutXor; + // Backup digest state for next round of updates. We can't keep this state in the + // data state register as a digest may be calculated together with encryption + // operations in an interleaved way. + digest_state_en = 1'b1; + end + end + /////////////////////////////////////////////////////////////////// + // Terminal error state. This raises an alert. + ErrorSt: begin + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + // This should never happen, hence we directly jump into the + // error state, where an alert will be triggered. + default: begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + /////////////////////////////////////////////////////////////////// + endcase // state_q + + // Unconditionally jump into the terminal error state in case of escalation. + // SEC_CM: SCRMBL.FSM.LOCAL_ESC, SCRMBL.FSM.GLOBAL_ESC + if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err) begin + state_d = ErrorSt; + fsm_err_o = 1'b1; + end + end + + ///////////////////////////// + // PRESENT DEC/ENC Modules // + ///////////////////////////// + + prim_present #( + .KeyWidth(128), + .NumRounds(NumPresentRounds), + .NumPhysRounds(1) + ) u_prim_present_enc ( + .data_i ( data_state_q ), + .key_i ( key_state_q ), + .idx_i ( idx_state_q ), + .data_o ( enc_data_out ), + .key_o ( enc_key_out ), + .idx_o ( enc_idx_out ) + ); + + prim_present #( + .KeyWidth(128), + // We are using an iterative full-round implementation here. + .NumRounds(NumPresentRounds), + .NumPhysRounds(1), + .Decrypt(1) + ) u_prim_present_dec ( + .data_i ( data_state_q ), + .key_i ( key_state_q ), + .idx_i ( idx_state_q ), + .data_o ( dec_data_out ), + .key_o ( dec_key_out ), + .idx_o ( dec_idx_out ) + ); + + /////////////// + // Registers // + /////////////// + + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt) + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + key_state_q <= '0; + idx_state_q <= '0; + data_state_q <= '0; + data_shadow_q <= '0; + digest_state_q <= '0; + valid_q <= 1'b0; + digest_mode_q <= StandardMode; + end else begin + valid_q <= valid_d; + digest_mode_q <= digest_mode_d; + + // enable regs + if (key_state_en) begin + key_state_q <= key_state_d; + idx_state_q <= idx_state_d; + end + if (data_state_en) begin + data_state_q <= data_state_d; + end + if (data_shadow_copy) begin + data_shadow_q <= data_state_q; + end else if (data_shadow_load) begin + data_shadow_q <= data_state_d; + end + if (digest_state_en) begin + digest_state_q <= digest_state_d; + end + end + end + +endmodule : otp_ctrl_scrmbl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_token_const.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_token_const.sv new file mode 100644 index 00000000000..453cdb7bb48 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_token_const.sv @@ -0,0 +1,65 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This module contains the hash post-image constants for the all-zero and raw unlock tokens. +// This implementation relies on constant propagation to precompute these constants from the +// random netlist constants at compile time, and hence does not contain any "real" logic. + +module otp_ctrl_token_const import otp_ctrl_pkg::*; #( + // Compile time random constants, to be overridden by topgen. + parameter digest_const_array_t RndCnstDigestConst = RndCnstDigestConstDefault, + parameter digest_iv_array_t RndCnstDigestIV = RndCnstDigestIVDefault, + parameter lc_ctrl_pkg::lc_token_t RndCnstRawUnlockToken = RndCnstRawUnlockTokenDefault +) ( + output lc_ctrl_pkg::lc_token_t all_zero_token_hashed_o, + output lc_ctrl_pkg::lc_token_t raw_unlock_token_hashed_o +); + + localparam int NumHashes = 2; + localparam int AllZeroIdx = 0; + localparam int RawUnlockIdx = 1; + + logic [NumHashes-1:0][1:0][ScrmblKeyWidth-1:0] data; + logic [NumHashes-1:0][4:0][ScrmblBlockWidth-1:0] state; + + // First digest is for the all zero token, the second is for the raw unlock token. + assign data[AllZeroIdx][0] = '0; + assign data[RawUnlockIdx][0] = RndCnstRawUnlockToken; + + // Repeat for all precomputed hashes. + for (genvar j = 0; j < NumHashes; j++) begin : gen_hashes + // Initialize all hashes with digest IV. + assign state[j][0] = RndCnstDigestIV[LcRawDigest]; + // Second data block is always the digest finalization constant. + assign data[j][1] = RndCnstDigestConst[LcRawDigest]; + + // Each hash takes four invocations, see section c) of the diagram in the Scrambling Datapath + // section of ../doc/theory_of_operation.md. + for (genvar k = 0; k < 4; k++) begin : gen_invocations + logic [ScrmblBlockWidth-1:0] next_state; + + // This relies on constant propagation to + // statically precompute the hashed token values. + prim_present #( + .KeyWidth(128), + .NumRounds(NumPresentRounds) + ) u_prim_present_enc_0 ( + .data_i ( state[j][k] ), + .key_i ( data[j][k%2] ), + .idx_i ( 5'h1 ), + .data_o ( next_state ), + .key_o ( ), + .idx_o ( ) + ); + + // XOR in last state according to the Davies-Meyer scheme. + assign state[j][k+1] = next_state ^ state[j][k]; + end + end + + // Concatenate the two 64bit hash results to form the final digests. + assign all_zero_token_hashed_o = {state[AllZeroIdx][4], state[AllZeroIdx][2]}; + assign raw_unlock_token_hashed_o = {state[RawUnlockIdx][4], state[RawUnlockIdx][2]}; + +endmodule : otp_ctrl_token_const diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv new file mode 100644 index 00000000000..944fd8da46e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/rtl/otp_ctrl_top_specific_pkg.sv @@ -0,0 +1,105 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +// This package contains top specific and implementation items. +// +// It imports otp_ctrl_reg_pkg, which is generated from the top specific hjson file. +// The items that are generic and used by top-independent IPs are placed in otp_ctrl_pkg. +package otp_ctrl_top_specific_pkg; + + import prim_util_pkg::vbits; + import otp_ctrl_pkg::*; + import otp_ctrl_reg_pkg::*; + import otp_ctrl_macro_pkg::OtpWidth; + import otp_ctrl_macro_pkg::OtpErrWidth; + + //////////////////////// + // General Parameters // + //////////////////////// + + // Width of entropy input + parameter int EdnDataWidth = 64; + + parameter int NumPartWidth = vbits(NumPart); + + parameter int SwWindowAddrWidth = vbits(NumSwCfgWindowWords); + + // Background check timer LFSR width. + parameter int LfsrWidth = 40; + // The LFSR will be reseeded once LfsrUsageThreshold + // values have been drawn from it. + parameter int LfsrUsageThreshold = 16; + + // Redundantly encoded and complementary values are used to for signalling to the partition + // controller FSMs and the DAI whether a partition is locked or not. Any other value than + // "Mubi8Lo" is interpreted as "Locked" in those FSMs. + typedef struct packed { + prim_mubi_pkg::mubi8_t read_lock; + prim_mubi_pkg::mubi8_t write_lock; + } part_access_t; + + parameter int DaiCmdWidth = 3; + typedef enum logic [DaiCmdWidth-1:0] { + DaiRead = 3'b001, + DaiWrite = 3'b010, + DaiDigest = 3'b100 + } dai_cmd_e; + + // Typedef for extended OTP Error. This extends the OTP macro errors. + typedef enum logic [OtpErrWidth-1:0] { + NoError = 3'h0, + MacroError = 3'h1, + MacroEccCorrError = 3'h2, + MacroEccUncorrError = 3'h3, + MacroWriteBlankError = 3'h4, + AccessError = 3'h5, + CheckFailError = 3'h6, + FsmStateError = 3'h7 + } otp_err_e; + + ///////////////////////////////// + // Typedefs for OTP Scrambling // + ///////////////////////////////// + + parameter int NumPresentRounds = 31; + parameter int ScrmblBlockHalfWords = ScrmblBlockWidth / OtpWidth; + + typedef enum logic [2:0] { + Decrypt, + Encrypt, + LoadShadow, + Digest, + DigestInit, + DigestFinalize + } otp_scrmbl_cmd_e; + + //////////////////////////////// + // Typedefs for Key Broadcast // + //////////////////////////////// + + // Get maximum nonce width + localparam int NumNonceChunks = + (OtbnNonceWidth > SramNonceWidth) ? OtbnNonceSel : SramNonceSel; + + /////////////////////////////////////////// + // Defaults for random netlist constants // + /////////////////////////////////////////// + + // These LFSR parameters have been generated with + // $ util/design/gen-lfsr-seed.py --width 40 --seed 4247488366 + typedef logic [LfsrWidth-1:0] lfsr_seed_t; + typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t; + localparam lfsr_seed_t RndCnstLfsrSeedDefault = 40'h453d28ea98; + localparam lfsr_perm_t RndCnstLfsrPermDefault = + 240'h4235171482c225f79289b32181a0163a760355d3447063d16661e44c12a5; + + typedef struct packed { + sram_key_t key; + sram_nonce_t nonce; + } scrmbl_key_init_t; + localparam scrmbl_key_init_t RndCnstScrmblKeyInitDefault = + 256'hcebeb96ffe0eced795f8b2cfe23c1e519e4fa08047a6bcfb811b04f0a479006e; + +endpackage : otp_ctrl_top_specific_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/constraints.sdc b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/constraints.sdc new file mode 100644 index 00000000000..0b119da9708 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/constraints.sdc @@ -0,0 +1,50 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Generic constraints file for simple testsynthesis flow + +# note that we do not fix hold timing in this flow +set SETUP_CLOCK_UNCERTAINTY 0.5 + +##################### +# main clock # +##################### +set MAIN_CLK_PIN clk_i +set MAIN_RST_PIN rst_ni +# set main clock to 125 MHz +set MAIN_TCK 8.0 +set_ideal_network ${MAIN_CLK_PIN} +set_ideal_network ${MAIN_RST_PIN} +set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${MAIN_CLK_PIN} + +# other timing constraint in ns +set IN_DEL 1.0 +set OUT_DEL 1.0 +set DELAY ${MAIN_TCK} + +create_clock ${MAIN_CLK_PIN} -period ${MAIN_TCK} + +# in to out +set_max_delay ${DELAY} -from [all_inputs] -to [all_outputs] +# in to reg / reg to out +set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] {${MAIN_CLK_PIN}}] -clock ${MAIN_CLK_PIN} +set_output_delay ${OUT_DEL} [all_outputs] -clock ${MAIN_CLK_PIN} + +##################### +# I/O drive/load # +##################### + +# attach load and drivers to IOs to get a more realistic estimate +set_driving_cell -no_design_rule -lib_cell ${DRIVING_CELL} -pin ${DRIVING_CELL_PIN} [all_inputs] +set_load [load_of ${LOAD_CELL_LIB}/${LOAD_CELL}/${LOAD_CELL_PIN}] [all_outputs] + +# set a nonzero critical range to be able to spot the violating paths better +# in the report +set_critical_range 0.5 ${DUT} + +##################### +# Size Only Cells # +##################### + +set_size_only -all_instances [get_cells -h *u_size_only*] true diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/otp_ctrl_gtech_syn_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/otp_ctrl_gtech_syn_cfg.hjson new file mode 100644 index 00000000000..c4603569232 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/otp_ctrl_gtech_syn_cfg.hjson @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Top level dut name (sv module). + name: otp_ctrl + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_ip:{name}:0.1 + + import_cfgs: [// Project wide common GTECH synthesis config file + "{proj_root}/hw/syn/tools/dvsim/common_gtech_syn_cfg.hjson"] + + overrides: [ + { // Deletes black-boxed hierarchies before writing out the unmapped netlist + name: post_elab_script + value: "{proj_root}/hw/top_darjeeling_no_ibex/ip_autogen/{name}/syn/post_elab_gtech.tcl" + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson new file mode 100644 index 00000000000..e4ee63b99cb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/otp_ctrl_syn_cfg.hjson @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Top level dut name (sv module). + name: otp_ctrl + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_ip:{name}:0.1 + + import_cfgs: [// Project wide common synthesis config file + "{proj_root}/hw/syn/tools/dvsim/common_syn_cfg.hjson"] + + // Timing constraints for this module + sdc_file: "{proj_root}/hw/top_darjeeling_no_ibex/ip_autogen/{name}/syn/constraints.sdc" + + // This is not needed for this module + foundry_sdc_file: "" +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/post_elab_gtech.tcl b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/post_elab_gtech.tcl new file mode 100644 index 00000000000..abe1a8c181f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/otp_ctrl/syn/post_elab_gtech.tcl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Post elab script, used in GTECH runs to modify the unmapped netlist before +# writing it out. + +# Remove generic views of ram macros +remove_design prim_generic_ram_1p_Width* diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/BUILD new file mode 100644 index 00000000000..3bf8a44fdc5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/BUILD @@ -0,0 +1,25 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.svg", + ]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/README.md new file mode 100644 index 00000000000..d247e97a2c2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/README.md @@ -0,0 +1,29 @@ +# Pinmux Technical Specification + + +# Overview + +This document specifies the functionality of the pin multiplexer (`pinmux`) peripheral. +This module conforms to the [OpenTitan guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability). +See that document for integration overview within the broader OpenTitan top level system. +The module provides a mechanism to reconfigure the peripheral-to-pin mapping at runtime, which greatly enhances the system flexibility. +In addition to that, the `pinmux` also allows the user to control pad attributes (such as pull-up, pull-down, open-drain, drive-strength, keeper and inversion), and it contains features that facilitate low-power modes of the system. +For example, the sleep behavior of each pad can be programmed individually, and the module contains additional pattern detectors that can listen on any IO and wake up the system if a specific pattern has been detected. + +## Features + +- Configurable number of chip bidirectional IOs + +- Configurable number of peripheral inputs and outputs + +- Programmable mapping from peripheral outputs (and output enables) to top-level outputs (and output enables) + +- Programmable mapping from top-level inputs to peripheral inputs + +- Programmable control of chip pad attributes like output drive-strength, pull-up, pull-down and virtual open-drain + +- Programmable pattern detectors to detect wakeup conditions during sleep mode + +- Programmable sleep mode behavior + +- Support for life-cycle-based JTAG (TAP) isolation and muxing diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/BUILD new file mode 100644 index 00000000000..09b9328d303 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/BUILD @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_pinmux.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = glob([ + "pinmux.hjson", + "*_testplan.hjson", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/pinmux.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/pinmux.hjson new file mode 100644 index 00000000000..b7320cf21fe --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/pinmux.hjson @@ -0,0 +1,864 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +{ + name: "pinmux", + human_name: "Pin Multiplexer", + one_line_desc: "Multiplexes between on-chip hardware blocks and pins, and can be configured at runtime", + one_paragraph_desc: ''' + Pin Multiplexer connects on-chip hardware blocks to IC pins and controls the attributes of the pin drivers (such as pull-up/down, open-drain, and drive strength). + Large parts of its functionality can be controlled by software through registers. + Further features include per-pin programmable sleep behavior and wakeup pattern detectors as well as support for life-cycle-based JTAG (TAP) isolation and muxing. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "18", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_pinmux", + version: "1.1.1", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + notes: "Use FPV to perform block level verification.", + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_aon_i", reset: "rst_aon_ni"}, + {reset: "rst_sys_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + regwidth: "32", + scan: "true", + + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + + wakeup_list: [ + { name: "pin_wkup_req", + desc: "pin wake request" + }, + ], + + inter_signal_list: [ + // Define pwr mgr <-> pinmux signals + { struct: "logic", + type: "uni", + name: "sleep_en", + act: "rcv", + package: "", + desc: ''' + Level signal that is asserted when the power manager enters sleep. + ''', + default: "1'b0" + }, + { struct: "logic", + type: "uni", + name: "pin_wkup_req", + act: "req", + package: "", + desc: ''' + Wakeup request from wakeup detectors, to the power manager, running on the AON clock. + ''', + default: "1'b0" + }, + ] + + param_list: [ + { name: "NMioPeriphIn", + desc: "Number of muxed peripheral inputs", + type: "int", + default: "4", + local: "true" + }, + { name: "NMioPeriphOut", + desc: "Number of muxed peripheral outputs", + type: "int", + default: "5", + local: "true" + }, + { name: "NMioPads", + desc: "Number of muxed IO pads", + type: "int", + default: "12", + local: "true" + }, + { name: "NDioPads", + desc: "Number of dedicated IO pads", + type: "int", + default: "73", + local: "true" + }, + { name: "NWkupDetect", + desc: "Number of wakeup detectors", + type: "int", + default: "8", + local: "true" + }, + { name: "WkupCntWidth", + desc: "Number of wakeup counter bits", + type: "int", + default: "8", + local: "true" + }, + // Since the target-specific top-levels often have slightly + // different debug signal positions, we need a way to pass + // this info from the target specific top-level into the pinmux + // logic. The parameter struct below serves this purpose. + { name: "TargetCfg", + desc: "Target specific pinmux configuration.", + type: "pinmux_pkg::target_cfg_t", + default: "pinmux_pkg::DefaultTargetCfg", + local: "false", + expose: "true" + }, + ], + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + ] + + registers: [ +////////////////////////// +// MIO Inputs // +////////////////////////// + { multireg: { name: "MIO_PERIPH_INSEL_REGWEN", + desc: "Register write enable for MIO peripheral input selects.", + count: "NMioPeriphIn", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_PERIPH_INSEL", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding MIO_PERIPH_INSEL + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_PERIPH_INSEL", + desc: "For each peripheral input, this selects the muxable pad input.", + count: "NMioPeriphIn", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PERIPH_INSEL_REGWEN", + regwen_multi: "true", + cname: "IN", + fields: [ + { bits: "3:0", + name: "IN", + desc: ''' + 0: tie constantly to zero, 1: tie constantly to 1, + >=2: MIO pads (i.e., add 2 to the native MIO pad index). + ''' + resval: 0, + } + ] + } + }, + +////////////////////////// +// MIO Outputs // +////////////////////////// + { multireg: { name: "MIO_OUTSEL_REGWEN", + desc: "Register write enable for MIO output selects.", + count: "NMioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_OUTSEL", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding MIO_OUTSEL + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_OUTSEL", + desc: "For each muxable pad, this selects the peripheral output.", + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_OUTSEL_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "2:0", + name: "OUT", + desc: ''' + 0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, + >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). + ''' + resval: 2, + } + ] + // Random writes to this field may result in pad drive conflicts, + // which in turn leads to propagating Xes and assertion failures. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + }, + +////////////////////////// +// MIO PAD attributes // +////////////////////////// + { multireg: { name: "MIO_PAD_ATTR_REGWEN", + desc: "Register write enable for MIO PAD attributes.", + count: "NMioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!MIO_PAD_ATTR + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_PAD_ATTR", + desc: ''' + Muxed pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + The muxed pad that is used for TAP strap 0 has a different reset value, with `pull_en` set to 1. + ''', + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + regwen: "MIO_PAD_ATTR_REGWEN", + regwen_multi: "true", + cname: "MIO_PAD", + resval: 0 + fields: [ + { bits: "0", + name: "invert", + desc: "Invert input and output levels." + }, + { bits: "1", + name: "virtual_od_en", + desc: "Enable virtual open drain." + }, + { bits: "2", + name: "pull_en", + desc: "Enable pull-up or pull-down resistor." + }, + { bits: "3", + name: "pull_select", + desc: "Pull select (0: pull-down, 1: pull-up)." + enum: [ + { value: "0", + name: "pull_down", + desc: "Select the pull-down resistor." + }, + { value: "1", + name: "pull_up", + desc: "Select the pull-up resistor." + } + ] + }, + { bits: "4", + name: "keeper_en", + desc: "Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog `trireg`." + }, + { bits: "5", + name: "schmitt_en", + desc: "Enable the schmitt trigger." + }, + { bits: "6", + name: "od_en", + desc: "Enable open drain." + }, + { bits: "7", + name: "input_disable", + desc: ''' + Disable input drivers. + Setting this to 1 for pads that are not used as input can reduce their leakage current. + ''' + }, + { bits: "17:16", + name: "slew_rate", + desc: "Slew rate (0x0: slowest, 0x3: fastest)." + }, + { bits: "23:20", + name: "drive_strength", + desc: "Drive strength (0x0: weakest, 0xf: strongest)" + } + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + // Additionally, their reset value is defined by the RTL implementation and may not equal `resval` for all instances (#24621). + tags: ["excl:CsrAllTests:CsrExclAll"] + } + }, + +////////////////////////// +// DIO PAD attributes // +////////////////////////// + { multireg: { name: "DIO_PAD_ATTR_REGWEN", + desc: "Register write enable for DIO PAD attributes.", + count: "NDioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!DIO_PAD_ATTR + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "DIO_PAD_ATTR", + desc: ''' + Dedicated pad attributes. + This register has WARL behavior since not each pad type may support + all attributes. + ''', + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + regwen: "DIO_PAD_ATTR_REGWEN", + regwen_multi: "true", + cname: "DIO_PAD", + resval: 0, + fields: [ + { bits: "0", + name: "invert", + desc: "Invert input and output levels." + }, + { bits: "1", + name: "virtual_od_en", + desc: "Enable virtual open drain." + }, + { bits: "2", + name: "pull_en", + desc: "Enable pull-up or pull-down resistor." + }, + { bits: "3", + name: "pull_select", + desc: "Pull select (0: pull-down, 1: pull-up)." + enum: [ + { value: "0", + name: "pull_down", + desc: "Select the pull-down resistor." + }, + { value: "1", + name: "pull_up", + desc: "Select the pull-up resistor." + } + ] + }, + { bits: "4", + name: "keeper_en", + desc: "Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog `trireg`." + }, + { bits: "5", + name: "schmitt_en", + desc: "Enable the schmitt trigger." + }, + { bits: "6", + name: "od_en", + desc: "Enable open drain." + }, + { bits: "7", + name: "input_disable", + desc: ''' + Disable input drivers. + Setting this to 1 for pads that are not used as input can reduce their leakage current. + ''' + }, + { bits: "17:16", + name: "slew_rate", + desc: "Slew rate (0x0: slowest, 0x3: fastest)." + }, + { bits: "23:20", + name: "drive_strength", + desc: "Drive strength (0x0: weakest, 0xf: strongest)" + } + ], + // these CSRs have WARL behavior and may not + // read back the same value that was written to them. + // further, they have hardware side effects since they drive the + // pad attributes, and hence no random data should be written to them. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + }, + +////////////////////////// +// MIO PAD sleep mode // +////////////////////////// + { multireg: { name: "MIO_PAD_SLEEP_STATUS", + desc: "Register indicating whether the corresponding pad is in sleep mode.", + count: "NMioPads", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + This register is set to 1 if the deep sleep mode of the corresponding + pad has been enabled (!!MIO_PAD_SLEEP_EN) upon deep sleep entry. + The sleep mode of the corresponding pad will remain active until SW + clears this bit. + ''', + resval: "0", + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_REGWEN", + desc: "Register write enable for MIO sleep value configuration.", + count: "NMioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "MIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!MIO_PAD_SLEEP_MODE + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_EN", + desc: '''Enables the sleep mode of the corresponding muxed pad. + ''' + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "0", + name: "EN", + resval: 0, + desc: ''' + Deep sleep mode enable. + If this bit is set to 1 the corresponding pad will enable the sleep behavior + specified in !!MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit + in !!MIO_PAD_SLEEP_STATUS will be set to 1. + The pad remains in deep sleep mode until the corresponding bit in + !!MIO_PAD_SLEEP_STATUS is cleared by SW. + Note that if an always on peripheral is connected to a specific MIO pad, + the corresponding !!MIO_PAD_SLEEP_EN bit should be set to 0. + ''' + } + ] + } + }, + { multireg: { name: "MIO_PAD_SLEEP_MODE", + desc: '''Defines sleep behavior of the corresponding muxed pad. + ''' + count: "NMioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "MIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "1:0", + name: "OUT", + resval: 2, + desc: "Value to drive in deep sleep." + enum: [ + { value: "0", + name: "Tie-Low", + desc: "The pad is driven actively to zero in deep sleep mode." + }, + { value: "1", + name: "Tie-High", + desc: "The pad is driven actively to one in deep sleep mode." + }, + { value: "2", + name: "High-Z", + desc: ''' + The pad is left undriven in deep sleep mode. Note that the actual + driving behavior during deep sleep will then depend on the pull-up/-down + configuration of in !!MIO_PAD_ATTR. + ''' + }, + { value: "3", + name: "Keep", + desc: "Keep last driven value (including high-Z)." + }, + ] + } + ] + } + }, +////////////////////////// +// DIO PAD sleep mode // +////////////////////////// + { multireg: { name: "DIO_PAD_SLEEP_STATUS", + desc: "Register indicating whether the corresponding pad is in sleep mode.", + count: "NDioPads", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + This register is set to 1 if the deep sleep mode of the corresponding + pad has been enabled (!!DIO_PAD_SLEEP_MODE) upon deep sleep entry. + The sleep mode of the corresponding pad will remain active until SW + clears this bit. + ''', + resval: "0", + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_REGWEN", + desc: "Register write enable for DIO sleep value configuration.", + count: "NDioPads", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "DIO_PAD", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding !!DIO_PAD_SLEEP_MODE + is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_EN", + desc: '''Enables the sleep mode of the corresponding dedicated pad. + ''' + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "DIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "0", + name: "EN", + resval: 0, + desc: ''' + Deep sleep mode enable. + If this bit is set to 1 the corresponding pad will enable the sleep behavior + specified in !!DIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit + in !!DIO_PAD_SLEEP_STATUS will be set to 1. + The pad remains in deep sleep mode until the corresponding bit in + !!DIO_PAD_SLEEP_STATUS is cleared by SW. + Note that if an always on peripheral is connected to a specific DIO pad, + the corresponding !!DIO_PAD_SLEEP_EN bit should be set to 0. + ''' + } + ] + } + }, + { multireg: { name: "DIO_PAD_SLEEP_MODE", + desc: '''Defines sleep behavior of the corresponding dedicated pad. + ''' + count: "NDioPads", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "DIO_PAD_SLEEP_REGWEN", + regwen_multi: "true", + cname: "OUT", + fields: [ + { bits: "1:0", + name: "OUT", + resval: 2, + desc: "Value to drive in deep sleep." + enum: [ + { value: "0", + name: "Tie-Low", + desc: "The pad is driven actively to zero in deep sleep mode." + }, + { value: "1", + name: "Tie-High", + desc: "The pad is driven actively to one in deep sleep mode." + }, + { value: "2", + name: "High-Z", + desc: ''' + The pad is left undriven in deep sleep mode. Note that the actual + driving behavior during deep sleep will then depend on the pull-up/-down + configuration of in !!DIO_PAD_ATTR. + ''' + }, + { value: "3", + name: "Keep", + desc: "Keep last driven value (including high-Z)." + }, + ] + } + ] + } + }, +//////////////////////// +// Wakeup detectors // +//////////////////////// + { multireg: { name: "WKUP_DETECTOR_REGWEN", + desc: "Register write enable for wakeup detectors.", + count: "NWkupDetect", + compact: "false", + swaccess: "rw0c", + hwaccess: "none", + cname: "WKUP_DETECTOR", + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Register write enable bit. + If this is cleared to 0, the corresponding WKUP_DETECTOR + configuration is not writable anymore. + ''', + resval: "1", + } + ] + } + }, + { multireg: { name: "WKUP_DETECTOR_EN", + desc: ''' + Enables for the wakeup detectors. + Note that these registers are synced to the always-on clock. + The first write access always completes immediately. + However, read/write accesses following a write will block until that write has completed. + ''' + count: "NWkupDetect", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "WKUP_DETECTOR_REGWEN", + regwen_multi: "true", + cname: "DETECTOR", + async: "clk_aon_i", + fields: [ + { bits: "0:0", + name: "EN", + resval: 0, + desc: ''' + Setting this bit activates the corresponding wakeup detector. + The behavior is as specified in !!WKUP_DETECTOR, + !!WKUP_DETECTOR_CNT_TH and !!WKUP_DETECTOR_PADSEL. + ''' + // In CSR tests, we do not touch the chip IOs. Thet are either pulled low or + // or undriven. + // + // Random writes to the wkup detect CSRs may result in the case where the + // wakeup gets enabled and signaled due to a pin being low for a programmed + // time, which results in wkup_cause register to mismatch, OR, result in + // assertion error due to a pin programmed for wakeup detection is undriven + // Also exclude write for csr_hw_reset, otherwise, X may be detected and propagating. + tags: ["excl:CsrAllTests:CsrExclWrite"] + } + ] + } + + }, + { multireg: { name: "WKUP_DETECTOR", + desc: ''' + Configuration of wakeup condition detectors. + Note that these registers are synced to the always-on clock. + The first write access always completes immediately. + However, read/write accesses following a write will block until that write has completed. + + Note that the wkup detector should be disabled by setting !!WKUP_DETECTOR_EN_0 before changing the detection mode. + The reason for that is that the pulse width counter is NOT cleared upon a mode change while the detector is enabled. + ''' + count: "NWkupDetect", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "WKUP_DETECTOR_REGWEN", + regwen_multi: "true", + cname: "DETECTOR", + async: "clk_aon_i", + fields: [ + { bits: "2:0", + name: "MODE", + resval: 0, + desc: "Wakeup detection mode. Out of range values default to Posedge." + enum: [ + { value: "0", + name: "Posedge", + desc: "Trigger a wakeup request when observing a positive edge." + }, + { value: "1", + name: "Negedge", + desc: "Trigger a wakeup request when observing a negative edge." + }, + { value: "2", + name: "Edge", + desc: "Trigger a wakeup request when observing an edge in any direction." + }, + { value: "3", + name: "TimedHigh", + desc: ''' + Trigger a wakeup request when pin is driven HIGH for a certain amount + of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH. + ''' + }, + { value: "4", + name: "TimedLow", + desc: ''' + Trigger a wakeup request when pin is driven LOW for a certain amount + of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH. + ''' + }, + + ] + } + { bits: "3", + name: "FILTER", + resval: 0, + desc: '''0: signal filter disabled, 1: signal filter enabled. the signal must + be stable for 4 always-on clock cycles before the value is being forwarded. + can be used for debouncing. + ''' + } + { bits: "4", + name: "MIODIO", + resval: 0, + desc: '''0: select index !!WKUP_DETECTOR_PADSEL from MIO pads, + 1: select index !!WKUP_DETECTOR_PADSEL from DIO pads. + ''' + } + ] + } + + }, + { multireg: { name: "WKUP_DETECTOR_CNT_TH", + desc: ''' + Counter thresholds for wakeup condition detectors. + Note that these registers are synced to the always-on clock. + The first write access always completes immediately. + However, read/write accesses following a write will block until that write has completed. + ''' + count: "NWkupDetect", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "WKUP_DETECTOR_REGWEN", + regwen_multi: "true", + cname: "DETECTOR", + async: "clk_aon_i", + fields: [ + { bits: "WkupCntWidth-1:0", + name: "TH", + resval: 0, + desc: '''Counter threshold for TimedLow and TimedHigh wakeup detector modes (see !!WKUP_DETECTOR). + The threshold is in terms of always-on clock cycles. + ''' + } + ] + } + + }, + { multireg: { name: "WKUP_DETECTOR_PADSEL", + desc: ''' + Pad selects for pad wakeup condition detectors. + This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix. + ''' + count: "NWkupDetect", + compact: "false", + swaccess: "rw", + hwaccess: "hro", + regwen: "WKUP_DETECTOR_REGWEN", + regwen_multi: "true", + cname: "DETECTOR", + fields: [ + { bits: "6:0", + name: "SEL", + resval: 0, + desc: '''Selects a specific MIO or DIO pad (depending on !!WKUP_DETECTOR configuration). + In case of MIO, the pad select index is the same as used for !!MIO_PERIPH_INSEL, meaning that index + 0 and 1 just select constants 0 and 1, and the MIO pads live at indices >= 2. In case of DIO pads, + the pad select index corresponds 1:1 to the DIO pad to be selected. + ''' + } + ] + } + + }, + { multireg: { name: "WKUP_CAUSE", + desc: ''' + Cause registers for wakeup detectors. + Note that these registers are synced to the always-on clock. + The first write access always completes immediately. + However, read/write accesses following a write will block until that write has completed. + ''' + count: "NWkupDetect", + swaccess: "rw0c", + hwaccess: "hrw", + cname: "DETECTOR", + async: "clk_aon_i", + fields: [ + { bits: "0", + name: "CAUSE", + resval: 0, + desc: '''Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. + ''' + } + ] + } + + }, + ], +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/pinmux_fpv_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/pinmux_fpv_testplan.hjson new file mode 100644 index 00000000000..c7b93e78e28 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/pinmux_fpv_testplan.hjson @@ -0,0 +1,883 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "pinmux" + import_testplans: ["hw/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson"] + testpoints: [ + // `mio_to_periph_o` tests. + // Symbolic variable `periph_sel_i` is used to select a specific `mio_to_periph_o` pin. + { + name: InSel0_A + desc: '''When register `periph_insel` is set to 0, which means the selected input is constant + zero, the corresponding `mio_to_periph_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: InSel1_A + desc: '''When register `periph_insel` is set to 1, which means the selected input is constant + one, the corresponding `mio_to_periph_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: InSelN_A + desc: '''When register `periph_insel` is set to any value between 2 and + (2 + number of MioPads) and the select index is not jtag, the corresponding + `mio_to_periph_o` must be equal to the related `mio_in_i` value.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: InSelOOB_A + desc: '''When register `periph_insel` is set to any value larger than + (2 + number of MioPads), the corresponding `mio_to_periph_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_to_periph_o` backward tests + // Symbolic variable `periph_sel_i` is used to select a specific `mio_to_periph_o` pin. + { + name: MioToPeriph0Backward_A + desc: '''`mio_to_periph_o` should output 0 only if one of the following conditions meets: + - Register `periph_insel` is set to 0. + - The corresponding `mio_in_i` is 0. + - Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioToPeriph1Backward_A + desc: '''`mio_to_periph_o` should output 1 only if one of the following conditions meets: + - Register `periph_insel` is set to 1. + - The corresponding `mio_in_i` is 1. + - Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `dio_to_periph_o` tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_to_periph_o` pin. + { + name: DioInSelN_A + desc: "This assertion checks that `dio_to_periph_o` is directly connected to `dio_in_i`." + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_out_o` not in sleep_mode tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: OutSel0_A + desc: '''When register `mio_outsel` is set to 0 and is not in sleep mode or jtag, which means + the selected output is constant zero, the corresponding `mio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSel1_A + desc: '''When register `mio_outsel` is set to 1 and is not in sleep mode or jtag, which means + the selected output is constant one, the corresponding `mio_out_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSel2_A + desc: '''When register `mio_outsel` is set to 2 and is not in sleep mode or jtag, which means + the selected output is driving high-Z, the corresponding `mio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelN_A + desc: '''When register `mio_outsel` is set to any value between 3 and + (3 + Number of periph out) and is not in sleep mode or jtag, the corresponding + `mio_out_o` must be equal to the related `periph_to_mio_i` value.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOOB_A + desc: '''When register `mio_outsel` is set to any value larger than + (3 + Number of periph out) and is not in sleep mode, the corresponding `mio_out_o` must + be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_out_o` backward tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: MioOut0Backward_A + desc: '''`mio_out_o` should output 0 only if one of the following conditions meets: + - Register `mio_insel` is set to 0 or 2. + - The corresponding `periph_to_mio_i` is 0. + - Sleep mode is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioOut1Backward_A + desc: '''`mio_out_o` should output 1 only if one of the following conditions meets: + - Register `mio_insel` is set to 1. + - The corresponding `periph_to_mio_i` is 1. + - Sleep mode is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `mio_oe_o` not in sleep_mode tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: OutSelOe0_A + desc: '''When register `mio_outsel` is set to 0 and is not in sleep mode or jtag, the + corresponding `mio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOe1_A + desc: '''When register `mio_outsel` is set to 1 and is not in sleep mode or jtag, the + corresponding `mio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOe2_A + desc: '''When register `mio_outsel` is set to 2 and is not in sleep mode or jtag, which + indicates driving high-Z to the selected output, the corresponding `mio_oe_o` must + be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOeN_A + desc: '''When register `mio_outsel` is set to any value between 3 and + (3 + Number of periph out) and is not in sleep mode or jtag, the corresponding + `mio_oe_o` must be equal to the related `periph_to_mio_oe_i` value.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: OutSelOeOOB_A + desc: '''When register `mio_outsel` is set to any value larger than + (3 + Number of periph out) and is not in sleep mode, the corresponding `mio_oe_o` must + be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_oe_o` backward tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_oe_o` pin. + { + name: MioOe0Backward_A + desc: '''`mio_oe_o` should output 0 only if one of the following conditions meets: + - Register `mio_insel` is set to 2. + - The corresponding `periph_to_mio_oe_i` is 0. + - Sleep mode is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioOe1Backward_A + desc: '''`mio_oe_o` should output 1 only if one of the following conditions meets: + - Register `mio_insel` is set to 0 or 1. + - The corresponding `periph_to_mio_oe_i` is 1. + - Sleep mode is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `mio_out_o` in sleep mode tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: MioSleepMode0_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 0, which means the pad is driven zero in deep sleep mode. + If, in the meantime, register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioSleepMode1_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 1, which means the pad is driven one in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_out_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioSleepMode2_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 2, which means the pad is driven high-Z in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioSleepMode3_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 3, which means the pad keeps last driven value in deep sleep + mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_out_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioSleepStable_A + desc: '''If not at posedge of `sleep_en_i`, and in the meantime register + `mio_pad_sleep_status` is not written via TLUL interface to clear the sleep status, the + corresponding `mio_out_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_oe_o` in sleep mode tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_oe_o` pin. + { + name: MioOeSleepMode0_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 0, which means the pad is driven zero in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioOeSleepMode1_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 1, which means the pad is driven one in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioOeSleepMode2_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 2, which means the pad is driven high-Z in deep sleep mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_oe_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioOeSleepMode3_A + desc: '''At posedge of `sleep_en_i`, if register `mio_pad_sleep_en` is 1 and + `mio_pad_sleep_mode` is 3, which means the pad keeps last driven value in deep sleep + mode. + In the meantime, if register `mio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `mio_oe_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioOeSleepStable_A + desc: '''If not at posedge of `sleep_en_i`, and in the meantime, if register + `mio_pad_sleep_status` is not written via TLUL interface to clear the sleep status, the + corresponding `mio_oe_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `mio_out_o` sleep mode related backward tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_out_o` pin. + { + name: MioSleep0Backward_A + desc: '''`mio_out_o` should output 0 only if one of the following conditions meets: + - In sleep mode, register `mio_pad_sleep_mode` is set to 0 or 2. + - In sleep mode, previous `mio_out_o` is 0 and `mio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `mio_out_o` is 0 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioSleep1Backward_A + desc: '''`mio_out_o` should output 1 only if one of the following conditions meets: + - In sleep mode, register `mio_pad_sleep_mode` is set to 1. + - In sleep mode, previous `mio_out_o` is 1 and `mio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `mio_out_o` is 1 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `mio_oe_o` sleep mode related backward tests + // Symbolic variable `mio_sel_i` is used to select a specific `mio_oe_o` pin. + { + name: MioOeSleep0Backward_A + desc: '''`mio_oe_o` should output 0 only if one of the following conditions meets: + - In sleep mode, register `mio_pad_sleep_mode` is set to 2. + - In sleep mode, previous `mio_oe_o` is 0 and `mio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `mio_oe_o` is 0 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: MioOeSleep1Backward_A + desc: '''`mio_oe_o` should output 1 only if one of the following conditions meets: + - In sleep mode, register `mio_pad_sleep_mode` is set to 0 or 1. + - In sleep mode, previous `mio_oe_o` is 1 and `mio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `mio_oe_o` is 1 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `dio_out_o` not in sleep mode tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_out_o` pin. + { + name: DOutSelN_A + desc: "`dio_out_o` is connected to `periph_to_dio_i` if not in sleep mode." + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_oe_o` not in sleep mode tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_oe_o` pin. + { + name: DOutSelOeN_A + desc: "`dio_oe_o` is connected to `periph_to_dio_oe_i` if not in sleep mode." + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_out_o` in sleep mode tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_out_o` pin. + { + name: DioSleepMode0_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 0, which means the pad is driven zero in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioSleepMode1_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 1, which means the pad is driven one in deep sleep mode. + In the meantime, if register `dmio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_out_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioSleepMode2_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 2, which means the pad is driven high-Z in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_out_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioSleepMode3_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 3, which means the pad keeps last driven value in deep sleep + mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_out_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioSleepStable_A + desc: '''If not at posedge of `sleep_en_i`, and in the meantime, if register + `dio_pad_sleep_status` is not written via TLUL interface to clear the sleep status, the + corresponding `dio_out_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_oe_o` in sleep mode tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_oe_o` pin. + { + name: DioOeSleepMode0_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 0, which means the pad is driven zero in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioOeSleepMode1_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 1, which means the pad is driven one in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_oe_o` must be 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioOeSleepMode2_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 2, which means the pad is driven high-Z in deep sleep mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_oe_o` must be 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioOeSleepMode3_A + desc: '''At posedge of `sleep_en_i`, if register `dio_pad_sleep_en` is 1 and + `dio_pad_sleep_mode` is 3, which means the pad keeps last driven value in deep sleep + mode. + In the meantime, if register `dio_pad_sleep_status` is not written via TLUL interface + to clear the sleep status, the corresponding `dio_oe_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DioOeSleepStable_A + desc: '''If not at posedge of `sleep_en_i`, and in the meantime, if register + `dio_pad_sleep_status` is not written via TLUL interface to clear the sleep status, the + corresponding `dio_oe_o` should be stable. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_out_o` backward tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_out_o` pin. + { + name: Dio0Backward_A + desc: '''`dio_out_o` should output 0 only if one of the following conditions meets: + - The corresponding `periph_to_dio_i` is 0. + - In sleep mode, register `dio_pad_sleep_mode` is set to 0 or 2. + - In sleep mode, previous `dio_out_o` is 0 and `dio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `dio_out_o` is 0 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: Dio1Backward_A + desc: '''`dio_out_o` should output 1 only if one of the following conditions meets: + - The corresponding `periph_to_dio_i` is 1. + - In sleep mode, register `dio_pad_sleep_mode` is set to 1. + - In sleep mode, previous `dio_out_o` is 1 and `dio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `dio_out_o` is 1 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `dio_oe_o` backward tests + // Symbolic variable `dio_sel_i` is used to select a specific `dio_oe_o` pin. + { + name: DioOe0Backward_A + desc: '''`dio_oe_o` should output 0 only if one of the following conditions meets: + - The corresponding `periph_to_dio_i` is 0. + - In sleep mode, register `dio_pad_sleep_mode` is set to 2. + - In sleep mode, previous `dio_oe_o` is 0 and `dio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `dio_oe_o` is 0 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: DioOe1Backward_A + desc: '''`dio_oe_o` should output 1 only if one of the following conditions meets: + - The corresponding `periph_to_dio_i` is 1. + - In sleep mode, register `dio_pad_sleep_mode` is set to 0 or 1. + - In sleep mode, previous `dio_oe_o` is 1 and `dio_pad_sleep_mode` is set to 3. + - In sleep mode, previous `dio_oe_o` is 1 and input `sleep_en_i` is not at posedge. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `mio_pad_attr_o` tests + { + name: MioAttrO_A + desc: '''`mio_attr_o` should be equal to corresponding `mio_pad_attr` register value and + TargetCfg's mio_pad_type configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: MioJtagAttrO_A + desc: "If jtag is enabled, the jtag `mio_attr_o` index should be equal to 0." + stage: V1 + tests: ["pinmux_assert"] + } + + // `dio_pad_attr_o` tests + { + name: DioAttrO_A + desc: '''`dio_attr_o` should be equal to corresponding `dio_pad_attr` register value and + TargetCfg's dio_pad_type configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `pin_wkup_req_o` tests + // Symbolic variable `wkup_sel_i` is used to select a specific wkup_cause. + // Variable `final_pin_val` is created to capture selected wakeup pins based on register + // `wkup_detector_padsel` and `wkup_detector.filter`. + { + name: WkupPosedge_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 0, + which means rising edge is used to detect wakeup. If variable `final_pin_val` is at + posedge then `wkup_cause` register's `de` attribute should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupNegedge_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 1, + which means falling edge is used to detect wakeup. If variable `final_pin_val` is at + negedge, then `wkup_cause` register's `de` attribute should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupEdge_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 2, + which means either rising or falling edge is used to detect wakeup. If variable + `final_pin_val` is at posedge or negedge, then `wkup_cause` register's `de` attribute + should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupTimedHigh_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 3, + which means postive pulse cycles are used to detect wakeup. If variable `final_pin_val` + stays high longer than the threshold, then `wkup_cause` register's `de` attribute + should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupTimedLow_A + desc: '''When register `wkup_detector_en` is set to 1 and `wkup_detector.mode` is set to 4, + which means negative pulse cycles are used to detect wakeup. If variable `final_pin_val` + stays low longer than the threshold, then `wkup_cause` register's `de` attribute should + be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: WkupCauseQ_A + desc: '''When `wkup_cause` register's `de` attribute is set to 1 and user is not writing to + `wkup_cause` at the same cycle, then `wkup_cause.q` should be set to 1.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: AonWkupO_A + desc: '''When register `wkup_cause` is 1, `pin_wkup_req_o` should also be 1. + `pin_wkup_req_o` is 0 only when all `wkup_cause` registers are 0.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // `pin_wkup_req_o` backward tests + { + name: WkupCause0_A + desc: "Register `wkup_cause` is 0 only when none of the above wakeup conditions is met." + stage: V2 + tests: ["pinmux_assert"] + } + { + name: WkupCause1_A + desc: "Register `wkup_cause` is 1 when at least one of the above wakeup conditions is met." + stage: V2 + tests: ["pinmux_assert"] + } + + // `lc_jtag_o` tests + { + name: LcJtagWoScanmode_A + desc: '''Not in scanmode, when tap_strap select LC_tap, `lc_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: LcJtagWScanmode_A + desc: '''In scanmode, when tap_strap select LC_tap, `lc_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration except the + `jtag_trst` pin, which must be equal to `rst_ni`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: LcJtagODefault_A + desc: "`lc_jtag_o` should stay 0 if tap_strap did not select LC_tap." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: LcJtagOBackward_A + desc: '''`lc_jtag_o` pins are equal to the corresponding `mio_in_i` inputs if one of the + following conditions are met: + - Lc Jtag is disabled and the corresponding pins are 0. + - Lc Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `rv_jtag_o` tests + { + name: RvJtagWoScanmode_A + desc: '''Not in scanmode, when tap_strap select RV_tap and `lc_hw_debug_en_i` input is On for + the past two clock cycles due to the synchronizer, then `rv_jtag_o` must be equal to + the corresponding `mio_in_i` pins based on the `TargetCfg` configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: RvJtagWScanmode_A + desc: '''In scanmode, When tap_strap select RV_tap and `lc_hw_debug_en_i` is On for the past + two clock cycles due to the synchronizer, then `rv_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration except the + `jtag_trst` pin, which must be equal to `rst_ni`. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: RvJtagODefault_A + desc: '''`rv_jtag_o` should stay 0 if tap_strap did not select RV_tap or `lc_hw_debug_en_i` + input is Off for the past two clock cycles due to the synchronizer.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: RvJtagOBackward_A + desc: '''`rv_jtag_o` pins are equal to the corresponding `mio_in_i` inputs if one of the + following conditions are met: + - Rv Jtag is disabled and the corresponding pins are 0. + - Rv Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + // `dft_jtag_o` tests + { + name: DftJtagWoScanmode_A + desc: '''Not in scanmode, when tap_strap select DFT_tap and `lc_dft_en_i` is On for the past + two clock cycles due to the synchronizer, `lc_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftJtagWScanmode_A + desc: '''In scanmode, when tap_strap select DFT_tap and `lc_dft_en_i` is On for the past + two clock cycles due to the synchronizer, `lc_jtag_o` must be equal to the + corresponding `mio_in_i` pins based on the `TargetCfg` configuration except the + `jtag_trst` pin, which must be equal to `rst_ni`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftJtagODefault_A + desc: '''`dft_jtag_o` should stay 0 if tap_strap did not select DFT_tap or the `lc_dft_en_i` + input is Off for the past two clock cycles due to the synchronizer.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftJtagOBackward_A + desc: '''`dft_jtag_o` pins are equal to the corresponding `mio_in_i` inputs if one of the + following conditions are met: + - Dft Jtag is disabled and the corresponding pins are 0. + - Dft Jtag is enabled. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + { + name: DftJtagO1Backward_A + desc: '''`dft_jtag_o` pins are ones if one of the following conditions are met: + - Dft Jtag is enabled and the corresponding pins are 1. + ''' + stage: V2 + tests: ["pinmux_assert"] + } + + { + name: TapStrap_A + desc: '''If `dft_hold_tap_sel_i` is 0 and `lc_dft_en_i` is On for the past two clock cycles + due to the synchronizer, or `strap_en_i` is 1. + And in the meantime, if `lc_hw_debug_en_i` is On for the past two clock cycles due to + the synchronizer, then tap_strap must be equal to the past value of corresponding + `mio_in_i`. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: TapStrap0_A + desc: '''If `dft_hold_tap_sel_i` is 0 and `lc_dft_en_i` is On for the past two clock cycles + due to the synchronizer, or `strap_en_i` is 1. + Then tap_strap[0] must be equal to the past value of corresponding `mio_in_i`. + ''' + stage: V1 + tests: ["pinmux_assert"] + } + + // Jtag pinmux output tests + { + name: LcJtagI_A + desc: '''When Lc tap is selected, the corresponding `mio_out_o` and `mio_out_oe` should be + equal to `lc_jtag_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: RvJtagI_A + desc: '''When Rv tap is selected and `lc_hw_debug_en_i` is On for the past two clock cycles + due to the synchronizer, the corresponding `mio_out_o` and `mio_out_oe` should be equal + to `rv_jtag_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftJtagI_A + desc: '''When Dft tap is selected and `lc_dft_en_i` is On for the past two clock cycles + due to the synchronizer, the corresponding `mio_out_o` and `mio_out_oe` should be equal + to `dft_jtag_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + + // Dft `strap_test_o` tests + { + name: DftStrapTestO_A + desc: '''When `lc_dft_en_i` is On for the past two clock cycles due to the synchronizer, + `dft_strap_test_o.valid` must be 1, and `dft_strap_test_o.straps` should be equal to + the corresponding `mio_in_i` index.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftStrapTestOValidStable_A + desc: "`dft_strap_test_o.valid` once set to 1 will stay high until reset." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: DftStrapTestOStrapStable_A + desc: "`dft_strap_test_o.valid` once set, `dft_strap_test_o.straps` should stay stable." + stage: V1 + tests: ["pinmux_assert"] + } + + // USB related IOs. + // Current plan is to only check connectivity via assertions because usbdev design is fully + // verified separately in a DV testbench. + { + name: UsbSleepEnI_A + desc: "`sleep_en_i` should be connected directly to usbdev's `low_power_alw_i`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbDppullupEnUpwrI_A + desc: '''`usb_dppullup_en_upwr_i` should be connected directly to usbdev's + `usb_dppullup_en_upwr_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbDnpullupEnUpwrI_A + desc: '''`usb_dnpullup_en_upwr_i` should be connected directly to usbdev's + `usb_dnpullup_en_upwr_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbDppullupEnO_A + desc: '''`usb_dppullup_en_o` should be connected directly to usbdev's + `usb_dppullup_en_o`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbDnpullupEnO_A + desc: '''`usb_dnpullup_en_o` should be connected directly to usbdev's + `usb_dnpullup_en_o`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbOutOfRstI_A + desc: "`usb_out_of_rst_i` should be connected directly to usbdev's `usb_out_of_rst_upwr_i`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbAonWakeEnUpwrI_A + desc: '''`usb_aon_wake_en_i` should be connected directly to usbdev's + `usb_aon_wake_en_upwr_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbAonWakeAckUpwrI_A + desc: '''`usb_aon_wake_ack_i` should be connected directly to usbdev's + `usb_aon_woken_upwr_i`.''' + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbSuspendI_A + desc: "`usb_suspend_i` should be connected directly to usbdev's `usb_suspended_upwr_i`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbWkupReqO_A + desc: "`usb_wkup_req_o` should be connected directly to usbdev's `wake_rep_alw_o`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbBusResetO_A + desc: "`usb_bus_reset_o` should be connected directly to usbdev's `bus_reset_alw_o`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbSenseLostO_A + desc: "`usb_sense_lost_o` should be connected directly to usbdev's `bus_lost_alw_o`." + stage: V1 + tests: ["pinmux_assert"] + } + { + name: UsbStateDebugO_A + desc: "`usb_state_debug_o` should be connected directly to usbdev's `bus_debug_o`." + stage: V1 + tests: ["pinmux_assert"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/pinmux_sec_cm_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/pinmux_sec_cm_testplan.hjson new file mode 100644 index 00000000000..9111fdccf49 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/pinmux_sec_cm_testplan.hjson @@ -0,0 +1,33 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../pinmux/data/pinmux.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../pinmux/data/pinmux_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: "Verify the countermeasure(s) BUS.INTEGRITY." + stage: V2S + tests: [] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/top_darjeeling_no_ibex_pinmux.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/top_darjeeling_no_ibex_pinmux.ipconfig.hjson new file mode 100644 index 00000000000..6a818deff2c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data/top_darjeeling_no_ibex_pinmux.ipconfig.hjson @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_pinmux + param_values: + { + n_wkup_detect: 8 + wkup_cnt_width: 8 + n_mio_pads: 12 + n_mio_periph_in: 4 + n_mio_periph_out: 5 + n_dio_pads: 73 + n_dio_periph_in: 58 + n_dio_periph_out: 57 + enable_usb_wakeup: false + enable_strap_sampling: false + topname: darjeeling_no_ibex + uniquified_modules: {} + module_instance_name: pinmux + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/defs.bzl new file mode 100644 index 00000000000..5fbfe883127 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/defs.bzl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +PINMUX = opentitan_ip( + name = "pinmux", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/pinmux/data:pinmux.hjson", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/checklist.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/checklist.md new file mode 100644 index 00000000000..37f48b1992d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/checklist.md @@ -0,0 +1,267 @@ +# Pinmux Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [Pinmux peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [Pinmux spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Done | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | Primary I/Os are exempted from KNOWN assertions since the chip-level testbench may drive X'es onto some of these signals. +Code Quality | [LINT_SETUP][] | Done | + + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | N/A | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | N/A | +Security | [SEC_CM_SHADOW_REGS][] | N/A | +Security | [SEC_CM_RTL_REVIEWED][] | N/A | +Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A | This block only contains the bus-integrity CM. + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | Note that the USB wakeup detector submodule `u_usbdev_aon_wake` is excluded in this review as it will be reviewed as part of the USB sign-off process. +Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | msf@ tjaychen@ chencindy@ awill@ +Review | Signoff date | Done | 2022-08-17 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | +Documentation | [TESTPLAN_COMPLETED][] | Done | +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | N/A | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | N/A | This block uses FPV +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | N/A | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | N/A | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Done | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | N/A | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | N/A | +Regression | [FPV_REGRESSION_SETUP][] | Done | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | N/A | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Waived | usbdev will be verified by a separate DV testbench. +Review | [DESIGN_SPEC_REVIEWED][] | Not Started | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | N/A | +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | N/A | +Tests | [SIM_ALL_TESTS_PASSING][] | N/A | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Done | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Done | +Tests | [SIM_FW_SIMULATED][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | N/A | +Coverage | [SIM_CODE_COVERAGE_V2][] | N/A | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | N/A | +Coverage | [FPV_CODE_COVERAGE_V2][] | Done | +Coverage | [FPV_COI_COVERAGE_V2][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Waived | usbdev will be verified by a separate DV testbench. +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | The testplan has been generated, but there is no DV environment to test these CMs. The CMs (bus integrity and LC gated TAP muxing/demuxing) are tested with the FPV testbench instead. +Tests | [FPV_SEC_CM_PROVEN][] | Done | The SEC_CM behavior has been proven with formal. +Tests | [SIM_SEC_CM_VERIFIED][] | N/A | This module only has an FPV testbench. +Coverage | [SIM_COVERAGE_REVIEWED][] | N/A | This module only has an FPV testbench. +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pendingg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/dv/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/dv/README.md new file mode 100644 index 00000000000..95737f5ff9c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/dv/README.md @@ -0,0 +1,35 @@ +# PINMUX DV document + +* **DV**: + * TODO: Add a UVM testbench to reuse auto-generated common tests for TLUL and alerts. + +* **FPV**: + * Verify all the PINMUX outputs by writing assumptions and assertions with a FPV based testbench + * Verify TileLink device protocol compliance with a FPV based testbench + +* [Design & verification stage](../../../../../README.md) + * [HW development stages](../../../../../../doc/project_governance/development_stages.md) +* [FPV dashboard](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/formal/summary.html) + +For detailed information on PINMUX design features, please see the +[PINMUX design specification](../../README.md). + +PINMUX FPV testbench has been constructed based on the [formal architecture](../../../../../formal/README.md). + +![Block diagram](fpv.svg) + +* The `../fpv/tb/pinmux_bind.sv` binds the `tlul_assert` [assertions](../../../../../ip/tlul/doc/TlulProtocolChecker.md) with pinmux to ensure TileLink interface protocol compliance. +* The `../fpv/tb/pinmux_bind.sv` also binds the `pinmux_csr_assert_fpv` to assert the TileLink writes and reads correctly. + +* The `../fpv/tb/pinmux_bind_fpv.sv` binds module `pinmux_assert_fpv` with the pinmux RTL. +The assertion file ensures all pinmux's outputs are verified based on the [testplan](#testplan). + +In the pinmux design, it includes usbdev logic because it operates on an always-on domain. +Pinmux FPV assertions will only cover the connectivities between usbdev IOs and pinmux IOs. +All functional checks will be implemented in the usbdev testbench. + +Due to the large number of peripheral, muxed, dedicated IOs, and wakeup causes, symbolic variables are used to reduce the number of repeated assertions code. +In the pinmux_assert_fpv module, we declared four symbolic variables (`mio_sel_i`, `periph_sel_i`, `dio_sel_i`, `wkup_sel_i`) to represent the index for muxed IOs, peripheral IOs, dedicated IOs, and wakeup causes. +Detailed explanation is listed in the [Symbolic Variables](../../../../../formal/README.md#symbolic-variables) section. + +[Testplan](../../data/pinmux_fpv_testplan.hjson) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/dv/fpv.svg b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/dv/fpv.svg new file mode 100644 index 00000000000..0061e7fd012 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/dv/fpv.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/generic_pad_wrapper.svg b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/generic_pad_wrapper.svg new file mode 100644 index 00000000000..bd95569d8ea --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/generic_pad_wrapper.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/interfaces.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/interfaces.md new file mode 100644 index 00000000000..7452d75aed1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/interfaces.md @@ -0,0 +1,68 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`pinmux`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_aon_i`** +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* +- Interrupts: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:-------------|:------------------|:--------|:------|--------:|:--------------------------------------------------------------------------------------| +| sleep_en | logic | uni | rcv | 1 | Level signal that is asserted when the power manager enters sleep. | +| pin_wkup_req | logic | uni | req | 1 | Wakeup request from wakeup detectors, to the power manager, running on the AON clock. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Security Alerts + +| Alert Name | Description | +|:-------------|:----------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:---------------------|:---------------------------------| +| PINMUX.BUS.INTEGRITY | End-to-end bus integrity scheme. | + + + + +## Parameters + +The following table lists the main parameters used throughout the `pinmux` design. +Note that the `pinmux` is generated based on the system configuration, and hence these parameters are placed into a package. +The pinout and `pinmux` mappings are listed under [Pinout and Pinmux Mapping](#pinout-and-pinmux-mapping) for specific top-level configurations. + +Parameter | Description +---------------|--------------- +`NPeriphOut` | Number of peripheral outputs. +`NPeriphIn` | Number of peripheral input. +`NMioPads` | Number of muxed bidirectional pads. +`NDioPads` | Number of dedicated pads. + +## Primary IO Signals + +The table below lists the primary `pinmux` IO signals to/from the pad ring. +The number of dedicated and muxed IOs is parametric, and hence the signals are stacked in packed arrays. + +Signal | Direction | Type | Description +---------------------------------------|-----------|------------------------------------|--------------- +`periph_to_mio_i[NPeriphOut-1:0]` | `input` | packed `logic` | Signals from `NPeriphOut` muxed peripheral outputs coming into the `pinmux`. +`periph_to_mio_oe_i[NPeriphOut-1:0]` | `input` | packed `logic` | Signals from `NPeriphOut` muxed peripheral output enables coming into the `pinmux`. +`mio_to_periph_o[NPeriphIn-1:0]` | `output` | packed `logic` | Signals to `NPeriphIn` muxed peripherals coming from the `pinmux`. +`periph_to_dio_i[NDioPads-1:0]` | `input` | packed `logic` | Signals from `NDioPads` dedicated peripheral outputs coming into the `pinmux`. +`periph_to_dio_oe_i[NDioPads-1:0]` | `input` | packed `logic` | Signals from `NDioPads` dedicated peripheral output enables coming into the `pinmux`. +`dio_to_periph_o[NDioPads-1:0]` | `output` | packed `logic` | Signals to `NDioPads` dedicated peripherals coming from the `pinmux`. +`mio_attr_o[NMioPads-1:0]` | `output` | prim_pad_wrapper_pkg::pad_attr_t | Packed array containing the pad attributes of all muxed IOs. +`mio_out_o[NMioPads-1:0]` | `output` | packed `logic` | Signals to `NMioPads` bidirectional muxed pads as output data. +`mio_oe_o[NMioPads-1:0]` | `output` | packed `logic` | Signals to `NMioPads` bidirectional muxed pads as output enables. +`mio_in_i[NMioPads-1:0]` | `input` | packed `logic` | Signals from `NMioPads` bidirectional muxed pads as input data. +`dio_attr_o[NDioPads-1:0]` | `output` | prim_pad_wrapper_pkg::pad_attr_t | Packed array containing the pad attributes of all dedicated IOs. +`dio_out_o[NDioPads-1:0]` | `output` | packed `logic` | Signals to `NDioPads` bidirectional dedicated pads as output data. +`dio_oe_o[NDioPads-1:0]` | `output` | packed `logic` | Signals to `NDioPads` bidirectional dedicated pads as output enables. +`dio_in_i[NDioPads-1:0]` | `input` | packed `logic` | Signals from `NDioPads` bidirectional dedicated pads as input data. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinmux_muxing_matrix.svg b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinmux_muxing_matrix.svg new file mode 100644 index 00000000000..0cd96b99002 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinmux_muxing_matrix.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinmux_overview_block_diagram.svg b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinmux_overview_block_diagram.svg new file mode 100644 index 00000000000..895eec6e6da --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinmux_overview_block_diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinout_asic.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinout_asic.md new file mode 100644 index 00000000000..0cfb7a17ec5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinout_asic.md @@ -0,0 +1,188 @@ +# "ASIC" Target : Pinout and Pinmux Connectivity + +## Pinout Table + +|

Pad Name

|

Type

|

Bank

|

Connection

|

Special Function

|

Pinmux Insel Constant / Muxed Output Index

|

Description

| +|:-------------------------------------------------:|:------------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:-------------------------------------------------------------------------------------------------------------:|:-------------------------------------------------------------------:| +|

POR_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

System reset

| +|

JTAG_TCK

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TCK signal

| +|

JTAG_TMS

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TMS signal

| +|

JTAG_TDI

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TDI signal

| +|

JTAG_TDO

|

BidirStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TDO signal

| +|

JTAG_TRST_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TRST_N signal

| +|

OTP_EXT_VOLT

|

AnalogIn1

|

VIO

|

manual

|

-

|

- / -

|

OTP external voltage input

| +|

SPI_HOST_D0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_CLK

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host clock

| +|

SPI_HOST_CS_L

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host chip select

| +|

SPI_DEV_D0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_CLK

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device clock

| +|

SPI_DEV_CS_L

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device chip select

| +|

SPI_DEV_TPM_CS_L

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device TPM chip select

| +|

UART_RX

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

UART receive

| +|

UART_TX

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

UART transmit

| +|

I2C_SCL

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

I2C clock

| +|

I2C_SDA

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

I2C data

| +|

GPIO0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO4

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO5

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO6

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO7

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO8

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO9

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO10

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO11

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO12

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO13

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO14

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO15

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO16

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO17

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO18

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO19

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO20

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO21

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO22

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO23

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO24

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO25

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO26

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO27

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO28

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO29

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO30

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO31

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

SOC_GPI0

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI1

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI2

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI3

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI4

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI5

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI6

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI7

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI8

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI9

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI10

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI11

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPO0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO4

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO5

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO6

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO7

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO8

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO9

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO10

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO11

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

MIO0

|

BidirStd

|

VIO

|

muxed

|

tap0

|

kTopDarjeelingNoIbexPinmuxInselMio0 / kTopDarjeelingNoIbexPinmuxMioOutMio0

|

Muxed IO pad / TAP strap signal.

| +|

MIO1

|

BidirStd

|

VIO

|

muxed

|

tap1

|

kTopDarjeelingNoIbexPinmuxInselMio1 / kTopDarjeelingNoIbexPinmuxMioOutMio1

|

Muxed IO pad / TAP strap signal.

| +|

MIO2

|

BidirStd

|

VIO

|

muxed

|

dft0

|

kTopDarjeelingNoIbexPinmuxInselMio2 / kTopDarjeelingNoIbexPinmuxMioOutMio2

|

Muxed IO pad / DFT strap signal.

| +|

MIO3

|

BidirStd

|

VIO

|

muxed

|

dft1

|

kTopDarjeelingNoIbexPinmuxInselMio3 / kTopDarjeelingNoIbexPinmuxMioOutMio3

|

Muxed IO pad / DFT strap signal.

| +|

MIO4

|

BidirStd

|

VIO

|

muxed

|

tck

|

kTopDarjeelingNoIbexPinmuxInselMio4 / kTopDarjeelingNoIbexPinmuxMioOutMio4

|

Muxed IO pad / JTAG tck signal.

| +|

MIO5

|

BidirStd

|

VIO

|

muxed

|

tms

|

kTopDarjeelingNoIbexPinmuxInselMio5 / kTopDarjeelingNoIbexPinmuxMioOutMio5

|

Muxed IO pad / JTAG tms signal.

| +|

MIO6

|

BidirStd

|

VIO

|

muxed

|

trst_n

|

kTopDarjeelingNoIbexPinmuxInselMio6 / kTopDarjeelingNoIbexPinmuxMioOutMio6

|

Muxed IO pad / JTAG trst_n signal.

| +|

MIO7

|

BidirStd

|

VIO

|

muxed

|

tdi

|

kTopDarjeelingNoIbexPinmuxInselMio7 / kTopDarjeelingNoIbexPinmuxMioOutMio7

|

Muxed IO pad / JTAG tdi signal.

| +|

MIO8

|

BidirStd

|

VIO

|

muxed

|

tdo

|

kTopDarjeelingNoIbexPinmuxInselMio8 / kTopDarjeelingNoIbexPinmuxMioOutMio8

|

Muxed IO pad / JTAG tdo signal.

| +|

MIO9

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxInselMio9 / kTopDarjeelingNoIbexPinmuxMioOutMio9

|

Muxed IO pad

| +|

MIO10

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxInselMio10 / kTopDarjeelingNoIbexPinmuxMioOutMio10

|

Muxed IO pad

| +|

MIO11

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxInselMio11 / kTopDarjeelingNoIbexPinmuxMioOutMio11

|

Muxed IO pad

| +## Pinmux Connectivity + +|

Module / Signal

|

Connection

|

Pad

|

Pinmux Outsel Constant / Peripheral Input Index

|

Description

| +|:------------------------------------------------------:|:---------------------------------------------:|:-------------------------------------------------:|:-------------------------------------------------------------------------------------------:|:----------------------------------------------:| +|

spi_host0_sd[0]

|

direct

|

SPI_HOST_D0

|

- / -

|

| +|

spi_host0_sd[1]

|

direct

|

SPI_HOST_D1

|

- / -

|

| +|

spi_host0_sd[2]

|

direct

|

SPI_HOST_D2

|

- / -

|

| +|

spi_host0_sd[3]

|

direct

|

SPI_HOST_D3

|

- / -

|

| +|

spi_device_sd[0]

|

direct

|

SPI_DEV_D0

|

- / -

|

| +|

spi_device_sd[1]

|

direct

|

SPI_DEV_D1

|

- / -

|

| +|

spi_device_sd[2]

|

direct

|

SPI_DEV_D2

|

- / -

|

| +|

spi_device_sd[3]

|

direct

|

SPI_DEV_D3

|

- / -

|

| +|

i2c0_scl

|

direct

|

I2C_SCL

|

- / -

|

| +|

i2c0_sda

|

direct

|

I2C_SDA

|

- / -

|

| +|

gpio_gpio[0]

|

direct

|

GPIO0

|

- / -

|

| +|

gpio_gpio[1]

|

direct

|

GPIO1

|

- / -

|

| +|

gpio_gpio[2]

|

direct

|

GPIO2

|

- / -

|

| +|

gpio_gpio[3]

|

direct

|

GPIO3

|

- / -

|

| +|

gpio_gpio[4]

|

direct

|

GPIO4

|

- / -

|

| +|

gpio_gpio[5]

|

direct

|

GPIO5

|

- / -

|

| +|

gpio_gpio[6]

|

direct

|

GPIO6

|

- / -

|

| +|

gpio_gpio[7]

|

direct

|

GPIO7

|

- / -

|

| +|

gpio_gpio[8]

|

direct

|

GPIO8

|

- / -

|

| +|

gpio_gpio[9]

|

direct

|

GPIO9

|

- / -

|

| +|

gpio_gpio[10]

|

direct

|

GPIO10

|

- / -

|

| +|

gpio_gpio[11]

|

direct

|

GPIO11

|

- / -

|

| +|

gpio_gpio[12]

|

direct

|

GPIO12

|

- / -

|

| +|

gpio_gpio[13]

|

direct

|

GPIO13

|

- / -

|

| +|

gpio_gpio[14]

|

direct

|

GPIO14

|

- / -

|

| +|

gpio_gpio[15]

|

direct

|

GPIO15

|

- / -

|

| +|

gpio_gpio[16]

|

direct

|

GPIO16

|

- / -

|

| +|

gpio_gpio[17]

|

direct

|

GPIO17

|

- / -

|

| +|

gpio_gpio[18]

|

direct

|

GPIO18

|

- / -

|

| +|

gpio_gpio[19]

|

direct

|

GPIO19

|

- / -

|

| +|

gpio_gpio[20]

|

direct

|

GPIO20

|

- / -

|

| +|

gpio_gpio[21]

|

direct

|

GPIO21

|

- / -

|

| +|

gpio_gpio[22]

|

direct

|

GPIO22

|

- / -

|

| +|

gpio_gpio[23]

|

direct

|

GPIO23

|

- / -

|

| +|

gpio_gpio[24]

|

direct

|

GPIO24

|

- / -

|

| +|

gpio_gpio[25]

|

direct

|

GPIO25

|

- / -

|

| +|

gpio_gpio[26]

|

direct

|

GPIO26

|

- / -

|

| +|

gpio_gpio[27]

|

direct

|

GPIO27

|

- / -

|

| +|

gpio_gpio[28]

|

direct

|

GPIO28

|

- / -

|

| +|

gpio_gpio[29]

|

direct

|

GPIO29

|

- / -

|

| +|

gpio_gpio[30]

|

direct

|

GPIO30

|

- / -

|

| +|

gpio_gpio[31]

|

direct

|

GPIO31

|

- / -

|

| +|

spi_device_sck

|

direct

|

SPI_DEV_CLK

|

- / -

|

| +|

spi_device_csb

|

direct

|

SPI_DEV_CS_L

|

- / -

|

| +|

spi_device_tpm_csb

|

direct

|

SPI_DEV_TPM_CS_L

|

- / -

|

| +|

uart0_rx

|

direct

|

UART_RX

|

- / -

|

| +|

soc_proxy_soc_gpi[0]

|

direct

|

SOC_GPI0

|

- / -

|

| +|

soc_proxy_soc_gpi[1]

|

direct

|

SOC_GPI1

|

- / -

|

| +|

soc_proxy_soc_gpi[2]

|

direct

|

SOC_GPI2

|

- / -

|

| +|

soc_proxy_soc_gpi[3]

|

direct

|

SOC_GPI3

|

- / -

|

| +|

soc_proxy_soc_gpi[4]

|

direct

|

SOC_GPI4

|

- / -

|

| +|

soc_proxy_soc_gpi[5]

|

direct

|

SOC_GPI5

|

- / -

|

| +|

soc_proxy_soc_gpi[6]

|

direct

|

SOC_GPI6

|

- / -

|

| +|

soc_proxy_soc_gpi[7]

|

direct

|

SOC_GPI7

|

- / -

|

| +|

soc_proxy_soc_gpi[8]

|

direct

|

SOC_GPI8

|

- / -

|

| +|

soc_proxy_soc_gpi[9]

|

direct

|

SOC_GPI9

|

- / -

|

| +|

soc_proxy_soc_gpi[10]

|

direct

|

SOC_GPI10

|

- / -

|

| +|

soc_proxy_soc_gpi[11]

|

direct

|

SOC_GPI11

|

- / -

|

| +|

soc_proxy_soc_gpi[12]

|

muxed

|

-

|

- / kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi12

|

| +|

soc_proxy_soc_gpi[13]

|

muxed

|

-

|

- / kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi13

|

| +|

soc_proxy_soc_gpi[14]

|

muxed

|

-

|

- / kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi14

|

| +|

soc_proxy_soc_gpi[15]

|

muxed

|

-

|

- / kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi15

|

| +|

spi_host0_sck

|

direct

|

SPI_HOST_CLK

|

- / -

|

| +|

spi_host0_csb

|

direct

|

SPI_HOST_CS_L

|

- / -

|

| +|

uart0_tx

|

direct

|

UART_TX

|

- / -

|

| +|

soc_proxy_soc_gpo[0]

|

direct

|

SOC_GPO0

|

- / -

|

| +|

soc_proxy_soc_gpo[1]

|

direct

|

SOC_GPO1

|

- / -

|

| +|

soc_proxy_soc_gpo[2]

|

direct

|

SOC_GPO2

|

- / -

|

| +|

soc_proxy_soc_gpo[3]

|

direct

|

SOC_GPO3

|

- / -

|

| +|

soc_proxy_soc_gpo[4]

|

direct

|

SOC_GPO4

|

- / -

|

| +|

soc_proxy_soc_gpo[5]

|

direct

|

SOC_GPO5

|

- / -

|

| +|

soc_proxy_soc_gpo[6]

|

direct

|

SOC_GPO6

|

- / -

|

| +|

soc_proxy_soc_gpo[7]

|

direct

|

SOC_GPO7

|

- / -

|

| +|

soc_proxy_soc_gpo[8]

|

direct

|

SOC_GPO8

|

- / -

|

| +|

soc_proxy_soc_gpo[9]

|

direct

|

SOC_GPO9

|

- / -

|

| +|

soc_proxy_soc_gpo[10]

|

direct

|

SOC_GPO10

|

- / -

|

| +|

soc_proxy_soc_gpo[11]

|

direct

|

SOC_GPO11

|

- / -

|

| +|

soc_proxy_soc_gpo[12]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo12 / -

|

| +|

soc_proxy_soc_gpo[13]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo13 / -

|

| +|

soc_proxy_soc_gpo[14]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo14 / -

|

| +|

soc_proxy_soc_gpo[15]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo15 / -

|

| +|

otp_macro_test[0]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselOtpMacroTest0 / -

|

| diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinout_cw310.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinout_cw310.md new file mode 100644 index 00000000000..e6fbcee8a49 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/pinout_cw310.md @@ -0,0 +1,191 @@ +# "CW310" Target : Pinout and Pinmux Connectivity + +## Pinout Table + +|

Pad Name

|

Type

|

Bank

|

Connection

|

Special Function

|

Pinmux Insel Constant / Muxed Output Index

|

Description

| +|:-------------------------------------------------:|:-----------------------------------------:|:---------------------------------------:|:---------------------------------------------:|:---------------------------------------------------:|:-------------------------------------------------------------------------------------------------------------:|:--------------------------------------------------------------------:| +|

POR_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

System reset

| +|

JTAG_TCK

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TCK signal

| +|

JTAG_TMS

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TMS signal

| +|

JTAG_TDI

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TDI signal

| +|

JTAG_TDO

|

BidirStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TDO signal

| +|

JTAG_TRST_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

JTAG TRST_N signal

| +|

SPI_HOST_D0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_D3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host data

| +|

SPI_HOST_CLK

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host clock

| +|

SPI_HOST_CS_L

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI host chip select

| +|

SPI_DEV_D0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_D3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device data

| +|

SPI_DEV_CLK

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device clock

| +|

SPI_DEV_CS_L

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device chip select

| +|

SPI_DEV_TPM_CS_L

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SPI device TPM chip select

| +|

UART_RX

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

UART receive

| +|

UART_TX

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

UART transmit

| +|

I2C_SCL

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

I2C clock

| +|

I2C_SDA

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

I2C data

| +|

GPIO0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO4

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO5

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO6

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO7

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO8

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO9

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO10

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO11

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO12

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO13

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO14

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO15

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO16

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO17

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO18

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO19

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO20

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO21

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO22

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO23

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO24

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO25

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO26

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO27

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO28

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO29

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO30

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

GPIO31

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

GPIO pad

| +|

SOC_GPI0

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI1

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI2

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI3

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI4

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI5

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI6

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI7

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI8

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI9

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI10

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPI11

|

InputStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose input

| +|

SOC_GPO0

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO1

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO2

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO3

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO4

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO5

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO6

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO7

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO8

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO9

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO10

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

SOC_GPO11

|

BidirStd

|

VIO

|

direct

|

-

|

- / -

|

SoC general purpose output

| +|

MIO0

|

BidirStd

|

VIO

|

muxed

|

tap0

|

kTopDarjeelingNoIbexPinmuxInselMio0 / kTopDarjeelingNoIbexPinmuxMioOutMio0

|

Muxed IO pad / TAP strap signal.

| +|

MIO1

|

BidirStd

|

VIO

|

muxed

|

tap1

|

kTopDarjeelingNoIbexPinmuxInselMio1 / kTopDarjeelingNoIbexPinmuxMioOutMio1

|

Muxed IO pad / TAP strap signal.

| +|

MIO2

|

BidirStd

|

VIO

|

muxed

|

dft0

|

kTopDarjeelingNoIbexPinmuxInselMio2 / kTopDarjeelingNoIbexPinmuxMioOutMio2

|

Muxed IO pad / DFT strap signal.

| +|

MIO3

|

BidirStd

|

VIO

|

muxed

|

dft1

|

kTopDarjeelingNoIbexPinmuxInselMio3 / kTopDarjeelingNoIbexPinmuxMioOutMio3

|

Muxed IO pad / DFT strap signal.

| +|

MIO4

|

BidirStd

|

VIO

|

muxed

|

tck

|

kTopDarjeelingNoIbexPinmuxInselMio4 / kTopDarjeelingNoIbexPinmuxMioOutMio4

|

Muxed IO pad / JTAG tck signal.

| +|

MIO5

|

BidirStd

|

VIO

|

muxed

|

tms

|

kTopDarjeelingNoIbexPinmuxInselMio5 / kTopDarjeelingNoIbexPinmuxMioOutMio5

|

Muxed IO pad / JTAG tms signal.

| +|

MIO6

|

BidirStd

|

VIO

|

muxed

|

trst_n

|

kTopDarjeelingNoIbexPinmuxInselMio6 / kTopDarjeelingNoIbexPinmuxMioOutMio6

|

Muxed IO pad / JTAG trst_n signal.

| +|

MIO7

|

BidirStd

|

VIO

|

muxed

|

tdi

|

kTopDarjeelingNoIbexPinmuxInselMio7 / kTopDarjeelingNoIbexPinmuxMioOutMio7

|

Muxed IO pad / JTAG tdi signal.

| +|

MIO8

|

BidirStd

|

VIO

|

muxed

|

tdo

|

kTopDarjeelingNoIbexPinmuxInselMio8 / kTopDarjeelingNoIbexPinmuxMioOutMio8

|

Muxed IO pad / JTAG tdo signal.

| +|

MIO9

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxInselMio9 / kTopDarjeelingNoIbexPinmuxMioOutMio9

|

Muxed IO pad

| +|

MIO10

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxInselMio10 / kTopDarjeelingNoIbexPinmuxMioOutMio10

|

Muxed IO pad

| +|

MIO11

|

BidirStd

|

VIO

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxInselMio11 / kTopDarjeelingNoIbexPinmuxMioOutMio11

|

Muxed IO pad

| +|

IO_CLK

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

Extra clock input for FPGA target

| +|

POR_BUTTON_N

|

InputStd

|

VIO

|

manual

|

-

|

- / -

|

Power-on reset button input

| +|

IO_CLKOUT

|

BidirStd

|

VIO

|

manual

|

-

|

- / -

|

Manual clock output for SCA setup

| +|

IO_TRIGGER

|

BidirStd

|

VIO

|

manual

|

-

|

- / -

|

Manual trigger output for SCA setup

| +## Pinmux Connectivity + +|

Module / Signal

|

Connection

|

Pad

|

Pinmux Outsel Constant / Peripheral Input Index

|

Description

| +|:------------------------------------------------------:|:---------------------------------------------:|:-------------------------------------------------:|:-------------------------------------------------------------------------------------------:|:----------------------------------------------:| +|

spi_host0_sd[0]

|

direct

|

SPI_HOST_D0

|

- / -

|

| +|

spi_host0_sd[1]

|

direct

|

SPI_HOST_D1

|

- / -

|

| +|

spi_host0_sd[2]

|

direct

|

SPI_HOST_D2

|

- / -

|

| +|

spi_host0_sd[3]

|

direct

|

SPI_HOST_D3

|

- / -

|

| +|

spi_device_sd[0]

|

direct

|

SPI_DEV_D0

|

- / -

|

| +|

spi_device_sd[1]

|

direct

|

SPI_DEV_D1

|

- / -

|

| +|

spi_device_sd[2]

|

direct

|

SPI_DEV_D2

|

- / -

|

| +|

spi_device_sd[3]

|

direct

|

SPI_DEV_D3

|

- / -

|

| +|

i2c0_scl

|

direct

|

I2C_SCL

|

- / -

|

| +|

i2c0_sda

|

direct

|

I2C_SDA

|

- / -

|

| +|

gpio_gpio[0]

|

direct

|

GPIO0

|

- / -

|

| +|

gpio_gpio[1]

|

direct

|

GPIO1

|

- / -

|

| +|

gpio_gpio[2]

|

direct

|

GPIO2

|

- / -

|

| +|

gpio_gpio[3]

|

direct

|

GPIO3

|

- / -

|

| +|

gpio_gpio[4]

|

direct

|

GPIO4

|

- / -

|

| +|

gpio_gpio[5]

|

direct

|

GPIO5

|

- / -

|

| +|

gpio_gpio[6]

|

direct

|

GPIO6

|

- / -

|

| +|

gpio_gpio[7]

|

direct

|

GPIO7

|

- / -

|

| +|

gpio_gpio[8]

|

direct

|

GPIO8

|

- / -

|

| +|

gpio_gpio[9]

|

direct

|

GPIO9

|

- / -

|

| +|

gpio_gpio[10]

|

direct

|

GPIO10

|

- / -

|

| +|

gpio_gpio[11]

|

direct

|

GPIO11

|

- / -

|

| +|

gpio_gpio[12]

|

direct

|

GPIO12

|

- / -

|

| +|

gpio_gpio[13]

|

direct

|

GPIO13

|

- / -

|

| +|

gpio_gpio[14]

|

direct

|

GPIO14

|

- / -

|

| +|

gpio_gpio[15]

|

direct

|

GPIO15

|

- / -

|

| +|

gpio_gpio[16]

|

direct

|

GPIO16

|

- / -

|

| +|

gpio_gpio[17]

|

direct

|

GPIO17

|

- / -

|

| +|

gpio_gpio[18]

|

direct

|

GPIO18

|

- / -

|

| +|

gpio_gpio[19]

|

direct

|

GPIO19

|

- / -

|

| +|

gpio_gpio[20]

|

direct

|

GPIO20

|

- / -

|

| +|

gpio_gpio[21]

|

direct

|

GPIO21

|

- / -

|

| +|

gpio_gpio[22]

|

direct

|

GPIO22

|

- / -

|

| +|

gpio_gpio[23]

|

direct

|

GPIO23

|

- / -

|

| +|

gpio_gpio[24]

|

direct

|

GPIO24

|

- / -

|

| +|

gpio_gpio[25]

|

direct

|

GPIO25

|

- / -

|

| +|

gpio_gpio[26]

|

direct

|

GPIO26

|

- / -

|

| +|

gpio_gpio[27]

|

direct

|

GPIO27

|

- / -

|

| +|

gpio_gpio[28]

|

direct

|

GPIO28

|

- / -

|

| +|

gpio_gpio[29]

|

direct

|

GPIO29

|

- / -

|

| +|

gpio_gpio[30]

|

direct

|

GPIO30

|

- / -

|

| +|

gpio_gpio[31]

|

direct

|

GPIO31

|

- / -

|

| +|

spi_device_sck

|

direct

|

SPI_DEV_CLK

|

- / -

|

| +|

spi_device_csb

|

direct

|

SPI_DEV_CS_L

|

- / -

|

| +|

spi_device_tpm_csb

|

direct

|

SPI_DEV_TPM_CS_L

|

- / -

|

| +|

uart0_rx

|

direct

|

UART_RX

|

- / -

|

| +|

soc_proxy_soc_gpi[0]

|

direct

|

SOC_GPI0

|

- / -

|

| +|

soc_proxy_soc_gpi[1]

|

direct

|

SOC_GPI1

|

- / -

|

| +|

soc_proxy_soc_gpi[2]

|

direct

|

SOC_GPI2

|

- / -

|

| +|

soc_proxy_soc_gpi[3]

|

direct

|

SOC_GPI3

|

- / -

|

| +|

soc_proxy_soc_gpi[4]

|

direct

|

SOC_GPI4

|

- / -

|

| +|

soc_proxy_soc_gpi[5]

|

direct

|

SOC_GPI5

|

- / -

|

| +|

soc_proxy_soc_gpi[6]

|

direct

|

SOC_GPI6

|

- / -

|

| +|

soc_proxy_soc_gpi[7]

|

direct

|

SOC_GPI7

|

- / -

|

| +|

soc_proxy_soc_gpi[8]

|

direct

|

SOC_GPI8

|

- / -

|

| +|

soc_proxy_soc_gpi[9]

|

direct

|

SOC_GPI9

|

- / -

|

| +|

soc_proxy_soc_gpi[10]

|

direct

|

SOC_GPI10

|

- / -

|

| +|

soc_proxy_soc_gpi[11]

|

direct

|

SOC_GPI11

|

- / -

|

| +|

soc_proxy_soc_gpi[12]

|

muxed

|

-

|

- / kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi12

|

| +|

soc_proxy_soc_gpi[13]

|

muxed

|

-

|

- / kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi13

|

| +|

soc_proxy_soc_gpi[14]

|

muxed

|

-

|

- / kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi14

|

| +|

soc_proxy_soc_gpi[15]

|

muxed

|

-

|

- / kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi15

|

| +|

spi_host0_sck

|

direct

|

SPI_HOST_CLK

|

- / -

|

| +|

spi_host0_csb

|

direct

|

SPI_HOST_CS_L

|

- / -

|

| +|

uart0_tx

|

direct

|

UART_TX

|

- / -

|

| +|

soc_proxy_soc_gpo[0]

|

direct

|

SOC_GPO0

|

- / -

|

| +|

soc_proxy_soc_gpo[1]

|

direct

|

SOC_GPO1

|

- / -

|

| +|

soc_proxy_soc_gpo[2]

|

direct

|

SOC_GPO2

|

- / -

|

| +|

soc_proxy_soc_gpo[3]

|

direct

|

SOC_GPO3

|

- / -

|

| +|

soc_proxy_soc_gpo[4]

|

direct

|

SOC_GPO4

|

- / -

|

| +|

soc_proxy_soc_gpo[5]

|

direct

|

SOC_GPO5

|

- / -

|

| +|

soc_proxy_soc_gpo[6]

|

direct

|

SOC_GPO6

|

- / -

|

| +|

soc_proxy_soc_gpo[7]

|

direct

|

SOC_GPO7

|

- / -

|

| +|

soc_proxy_soc_gpo[8]

|

direct

|

SOC_GPO8

|

- / -

|

| +|

soc_proxy_soc_gpo[9]

|

direct

|

SOC_GPO9

|

- / -

|

| +|

soc_proxy_soc_gpo[10]

|

direct

|

SOC_GPO10

|

- / -

|

| +|

soc_proxy_soc_gpo[11]

|

direct

|

SOC_GPO11

|

- / -

|

| +|

soc_proxy_soc_gpo[12]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo12 / -

|

| +|

soc_proxy_soc_gpo[13]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo13 / -

|

| +|

soc_proxy_soc_gpo[14]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo14 / -

|

| +|

soc_proxy_soc_gpo[15]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo15 / -

|

| +|

otp_macro_test[0]

|

muxed

|

-

|

kTopDarjeelingNoIbexPinmuxOutselOtpMacroTest0 / -

|

| diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/programmers_guide.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/programmers_guide.md new file mode 100644 index 00000000000..6bff0cd8587 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/programmers_guide.md @@ -0,0 +1,115 @@ +# Programmer's Guide + +## Pad Attributes + +Software should determine and program the pad attributes at startup, or reprogram the attributes when the functionality requirements change at runtime. + +This can be achieved by writing to the [`MIO_PAD_ATTR_0`](registers.md#mio_pad_attr) and [`DIO_PAD_ATTR_0`](registers.md#dio_pad_attr) registers. +Note that the IO attributes should be configured before enabling muxed IOs going through the `pinmux` matrix in order to avoid undesired electrical behavior and/or contention at the pads. + +The pad attributes configuration can be locked down individually for each pad via the [`MIO_PAD_ATTR_REGWEN_0`](registers.md#mio_pad_attr_regwen) and [`DIO_PAD_ATTR_REGWEN_0`](registers.md#dio_pad_attr_regwen) registers. +The configuration can then not be altered anymore until the next system reset. + +The following pad attributes are supported by this register layout by default: + +ATTR Bits | Description | Access +----------|-----------------------------------------------|--------- +0 | Input/output inversion | WARL +1 | Virtual open drain enable | WARL +2 | Pull enable | WARL +3 | Pull select (0: down, 1: up) | WARL +4 | Keeper enable | WARL +5 | Schmitt trigger enable | WARL +6 | Open drain enable | WARL +8:7 | Slew rate (0x0: slowest, 0x3: fastest) | WARL +12:9 | Drive strength (0x0: weakest, 0xf: strongest) | WARL + +Since some of the pad attributes may not be implemented, SW can probe this capability by writing the CSRs and read them back to determine whether the value was legal. +This behavior is also referred to as "writes-any-reads-legal" or "WARL" in the RISC-V world. +For example, certain pads may only support two drive-strength bits, instead of four. +The unsupported drive-strength bits in the corresponding CSRs would then always read as zero, even if SW attempts to set them to 1. + +## Pinmux Configuration + +Upon POR, the `pinmux` state is such that all MIO outputs are high-Z, and all MIO peripheral inputs are tied off to 0. +Software should determine and program the `pinmux` mapping at startup, or reprogram it when the functionality requirements change at runtime. +This can be achieved by writing the following values to the [`PERIPH_INSEL_0`](registers.md#periph_insel_0) and [`MIO_OUTSEL_0`](registers.md#mio_outsel) registers. + +`periph_insel` Value | Selected Input Signal +----------------------|----------------------- +0 | Constant zero (default) +1 | Constant one +2 + k | Corresponding MIO input signal at index k + +The global default at reset is `0`, but the default of individual signals can be overridden at design time, if needed. + +`mio_outsel` Value | Selected Output signal +----------------------|----------------------- +0 | Constant zero (default) +1 | Constant one +2 | High-Z +3 + k | Corresponding peripheral output signal at index k + +The global default at reset is `2`, but the default of individual signals can be overridden at design time, if needed. + +Note that the `pinmux` configuration should be sequenced after any IO attribute-specific configuration in the [`MIO_PAD_ATTR_0`](registers.md#mio_pad_attr) and [`DIO_PAD_ATTR_0`](registers.md#dio_pad_attr) registers to avoid any unwanted electric behavior and/or contention. +If needed, each select signal can be individually locked down via [`MIO_PERIPH_INSEL_REGWEN_0`](registers.md#mio_periph_insel_regwen) or [`MIO_OUTSEL_REGWEN_0`](registers.md#mio_outsel_regwen). +The configuration can then not be altered anymore until the next system reset. + +## Sleep Features + +The sleep behavior of each individual MIO or DIO can be defined via the (registers.md#mio_pad_sleep_en), [`DIO_PAD_SLEEP_EN_0`](registers.md#dio_pad_sleep_en), [`MIO_PAD_SLEEP_MODE_0`](registers.md#mio_pad_sleep_mode) and [`DIO_PAD_SLEEP_MODE_0`](registers.md#dio_pad_sleep_mode)) registers. +Available sleep behaviors are: + +`dio/mio_pad_sleep_en` Value | `dio/mio_pad_sleep_mode` Value | Sleep Behavior +------------------------------|--------------------------------|----------------------- +0 | - | Drive (default) +1 | 0 | Tie-low +1 | 1 | Tie-high +1 | 2 | High-Z +1 | 3 | Keep last value + +Note that if the behavior is set to "Drive", the sleep mode will not be activated upon sleep entry. +Rather, the retention logic continues to drive the value coming from the peripheral side. +Also note that the sleep logic is located after the `pinmux` matrix, hence the sleep configuration is per MIO pad and not per MIO peripheral. + +Before sleep entry, SW should configure the appropriate sleep behavior of all MIOs/DIOs via [`MIO_PAD_SLEEP_MODE_0`](registers.md#mio_pad_sleep_mode), [`DIO_PAD_SLEEP_MODE_0`](registers.md#dio_pad_sleep_mode). +This configuration can be optionally locked down, in which case it cannot be modified again until POR. +The configured behavior is then activated for all pads that have sleep mode set to enabled (registers.md#mio_pad_sleep_en) and [`DIO_PAD_SLEEP_EN_0`](registers.md#dio_pad_sleep_en)) at once by the power manager during the sleep entry sequence. + +When exiting sleep, the task of disabling the sleep behavior is however up to SW. +I.e., it must clear the per-pad sleep status bits in registers [`MIO_PAD_SLEEP_STATUS_0`](registers.md#mio_pad_sleep_status) and [`DIO_PAD_SLEEP_STATUS_0`](registers.md#dio_pad_sleep_status) that have been set upon sleep entry. +The rationale for this is that it may not be desirable to disable sleep behavior on all pads at once due to some additional book keeping / re-initialization that needs to be performed while exiting sleep. + +## Wakeup Features + +The `pinmux` contains eight wakeup detectors. +These detectors can be individually enabled and disabled regardless of the sleep state. +This ensures that SW can set them up before and disable them after sleep in order to ensure that no events are missed during sleep entry and exit. + +For more information on the patterns supported by the wakeup detectors, see [wakeup detectors](theory_of_operation.md#wakeup-detectors). + +A typical programming sequence for the wakeup detectors looks as follows: + +1. Before initiating any sleep mode, SW should configure the wakeup detectors appropriately and enable them via the [`WKUP_DETECTOR_0`](registers.md#wkup_detector), [`WKUP_DETECTOR_CNT_TH_0`](registers.md#wkup_detector_cnt_th) and [`WKUP_DETECTOR_PADSEL_0`](registers.md#wkup_detector_padsel) registers. + +2. Optionally, lock the wakeup detector configuration via the [`WKUP_DETECTOR_REGWEN_0`](registers.md#wkup_detector_regwen) registers. + +3. During sleep, the wakeup detectors will trigger a wakeup request if a matching pattern has been observed. + A bit corresponding to the wakeup detector that has observed the pattern will be set in the [`WKUP_CAUSE`](registers.md#wkup_cause) register. + +4. When exiting sleep, SW should read the wake info register in the [power manager](../../pwrmgr/README.md) to determine the reason(s) for the wakeup request. + +5. If the wakeup request was due to a pin wakeup pattern detector, SW should inspect the [`WKUP_CAUSE`](registers.md#wkup_cause) registers in order to determine the exact cause. + +6. SW should in any case disable the wakeup detectors and clear the [`WKUP_CAUSE`](registers.md#wkup_cause) registers once it is safe to do so (in order to not miss any events). + Note that the [`WKUP_CAUSE`](registers.md#wkup_cause) registers reside in the slow AON clock domain, and hence clearing them takes a few uS to take effect. + If needed, a SW readback can be performed to ensure that the clear operation has completed successfully. + +## Pinout and Pinmux Mapping + +Please see the specific documentation for detailed pinout and pinmux mapping tables for [this top](../doc/targets.md). + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_pinmux.h) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/registers.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/registers.md new file mode 100644 index 00000000000..ee4d330b855 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/registers.md @@ -0,0 +1,1817 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------| +| pinmux.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_0`](#mio_periph_insel_regwen) | 0x4 | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_1`](#mio_periph_insel_regwen) | 0x8 | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_2`](#mio_periph_insel_regwen) | 0xc | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_REGWEN_3`](#mio_periph_insel_regwen) | 0x10 | 4 | Register write enable for MIO peripheral input selects. | +| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0x14 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0x18 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0x1c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0x20 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x24 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x28 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x2c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x30 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x34 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x38 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x3c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x40 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x44 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x48 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x4c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x50 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x54 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x58 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x5c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x60 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x64 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x68 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x6c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x70 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x74 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x78 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x7c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x80 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x84 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x88 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x8c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x90 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x94 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x98 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x9c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0xa0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0xa4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0xa8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0xac | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0xb0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0xb4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0xb8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0xbc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0xc0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0xc4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0xc8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0xcc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0xd0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0xd4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0xd8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0xdc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0xe0 | 4 | Muxed pad attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0xe4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0xe8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0xec | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0xf0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0xf4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0xf8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0xfc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x100 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x104 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x108 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x10c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x110 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x114 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x118 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_14`](#dio_pad_attr_regwen) | 0x11c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_15`](#dio_pad_attr_regwen) | 0x120 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_16`](#dio_pad_attr_regwen) | 0x124 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_17`](#dio_pad_attr_regwen) | 0x128 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_18`](#dio_pad_attr_regwen) | 0x12c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_19`](#dio_pad_attr_regwen) | 0x130 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_20`](#dio_pad_attr_regwen) | 0x134 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_21`](#dio_pad_attr_regwen) | 0x138 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_22`](#dio_pad_attr_regwen) | 0x13c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_23`](#dio_pad_attr_regwen) | 0x140 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_24`](#dio_pad_attr_regwen) | 0x144 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_25`](#dio_pad_attr_regwen) | 0x148 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_26`](#dio_pad_attr_regwen) | 0x14c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_27`](#dio_pad_attr_regwen) | 0x150 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_28`](#dio_pad_attr_regwen) | 0x154 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_29`](#dio_pad_attr_regwen) | 0x158 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_30`](#dio_pad_attr_regwen) | 0x15c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_31`](#dio_pad_attr_regwen) | 0x160 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_32`](#dio_pad_attr_regwen) | 0x164 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_33`](#dio_pad_attr_regwen) | 0x168 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_34`](#dio_pad_attr_regwen) | 0x16c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_35`](#dio_pad_attr_regwen) | 0x170 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_36`](#dio_pad_attr_regwen) | 0x174 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_37`](#dio_pad_attr_regwen) | 0x178 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_38`](#dio_pad_attr_regwen) | 0x17c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_39`](#dio_pad_attr_regwen) | 0x180 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_40`](#dio_pad_attr_regwen) | 0x184 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_41`](#dio_pad_attr_regwen) | 0x188 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_42`](#dio_pad_attr_regwen) | 0x18c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_43`](#dio_pad_attr_regwen) | 0x190 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_44`](#dio_pad_attr_regwen) | 0x194 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_45`](#dio_pad_attr_regwen) | 0x198 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_46`](#dio_pad_attr_regwen) | 0x19c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_47`](#dio_pad_attr_regwen) | 0x1a0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_48`](#dio_pad_attr_regwen) | 0x1a4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_49`](#dio_pad_attr_regwen) | 0x1a8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_50`](#dio_pad_attr_regwen) | 0x1ac | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_51`](#dio_pad_attr_regwen) | 0x1b0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_52`](#dio_pad_attr_regwen) | 0x1b4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_53`](#dio_pad_attr_regwen) | 0x1b8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_54`](#dio_pad_attr_regwen) | 0x1bc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_55`](#dio_pad_attr_regwen) | 0x1c0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_56`](#dio_pad_attr_regwen) | 0x1c4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_57`](#dio_pad_attr_regwen) | 0x1c8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_58`](#dio_pad_attr_regwen) | 0x1cc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_59`](#dio_pad_attr_regwen) | 0x1d0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_60`](#dio_pad_attr_regwen) | 0x1d4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_61`](#dio_pad_attr_regwen) | 0x1d8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_62`](#dio_pad_attr_regwen) | 0x1dc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_63`](#dio_pad_attr_regwen) | 0x1e0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_64`](#dio_pad_attr_regwen) | 0x1e4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_65`](#dio_pad_attr_regwen) | 0x1e8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_66`](#dio_pad_attr_regwen) | 0x1ec | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_67`](#dio_pad_attr_regwen) | 0x1f0 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_68`](#dio_pad_attr_regwen) | 0x1f4 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_69`](#dio_pad_attr_regwen) | 0x1f8 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_70`](#dio_pad_attr_regwen) | 0x1fc | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_71`](#dio_pad_attr_regwen) | 0x200 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_72`](#dio_pad_attr_regwen) | 0x204 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x208 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x20c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x210 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x214 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x218 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x21c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x220 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x224 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x228 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x22c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x230 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x234 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x238 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x23c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_14`](#dio_pad_attr) | 0x240 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_15`](#dio_pad_attr) | 0x244 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_16`](#dio_pad_attr) | 0x248 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_17`](#dio_pad_attr) | 0x24c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_18`](#dio_pad_attr) | 0x250 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_19`](#dio_pad_attr) | 0x254 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_20`](#dio_pad_attr) | 0x258 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_21`](#dio_pad_attr) | 0x25c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_22`](#dio_pad_attr) | 0x260 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_23`](#dio_pad_attr) | 0x264 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_24`](#dio_pad_attr) | 0x268 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_25`](#dio_pad_attr) | 0x26c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_26`](#dio_pad_attr) | 0x270 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_27`](#dio_pad_attr) | 0x274 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_28`](#dio_pad_attr) | 0x278 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_29`](#dio_pad_attr) | 0x27c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_30`](#dio_pad_attr) | 0x280 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_31`](#dio_pad_attr) | 0x284 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_32`](#dio_pad_attr) | 0x288 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_33`](#dio_pad_attr) | 0x28c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_34`](#dio_pad_attr) | 0x290 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_35`](#dio_pad_attr) | 0x294 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_36`](#dio_pad_attr) | 0x298 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_37`](#dio_pad_attr) | 0x29c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_38`](#dio_pad_attr) | 0x2a0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_39`](#dio_pad_attr) | 0x2a4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_40`](#dio_pad_attr) | 0x2a8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_41`](#dio_pad_attr) | 0x2ac | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_42`](#dio_pad_attr) | 0x2b0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_43`](#dio_pad_attr) | 0x2b4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_44`](#dio_pad_attr) | 0x2b8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_45`](#dio_pad_attr) | 0x2bc | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_46`](#dio_pad_attr) | 0x2c0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_47`](#dio_pad_attr) | 0x2c4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_48`](#dio_pad_attr) | 0x2c8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_49`](#dio_pad_attr) | 0x2cc | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_50`](#dio_pad_attr) | 0x2d0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_51`](#dio_pad_attr) | 0x2d4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_52`](#dio_pad_attr) | 0x2d8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_53`](#dio_pad_attr) | 0x2dc | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_54`](#dio_pad_attr) | 0x2e0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_55`](#dio_pad_attr) | 0x2e4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_56`](#dio_pad_attr) | 0x2e8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_57`](#dio_pad_attr) | 0x2ec | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_58`](#dio_pad_attr) | 0x2f0 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_59`](#dio_pad_attr) | 0x2f4 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_60`](#dio_pad_attr) | 0x2f8 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_61`](#dio_pad_attr) | 0x2fc | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_62`](#dio_pad_attr) | 0x300 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_63`](#dio_pad_attr) | 0x304 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_64`](#dio_pad_attr) | 0x308 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_65`](#dio_pad_attr) | 0x30c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_66`](#dio_pad_attr) | 0x310 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_67`](#dio_pad_attr) | 0x314 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_68`](#dio_pad_attr) | 0x318 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_69`](#dio_pad_attr) | 0x31c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_70`](#dio_pad_attr) | 0x320 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_71`](#dio_pad_attr) | 0x324 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_72`](#dio_pad_attr) | 0x328 | 4 | Dedicated pad attributes. | +| pinmux.[`MIO_PAD_SLEEP_STATUS`](#mio_pad_sleep_status) | 0x32c | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x330 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x334 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x338 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x33c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x340 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x344 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x348 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x34c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x350 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x354 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x358 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x35c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x360 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x364 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x368 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x36c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x370 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x374 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x378 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x37c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x380 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x384 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x388 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x38c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x390 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x394 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x398 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x39c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x3a0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x3a4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x3a8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x3ac | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x3b0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x3b4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x3b8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x3bc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`DIO_PAD_SLEEP_STATUS_0`](#dio_pad_sleep_status_0) | 0x3c0 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_STATUS_1`](#dio_pad_sleep_status_1) | 0x3c4 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_STATUS_2`](#dio_pad_sleep_status_2) | 0x3c8 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x3cc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x3d0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x3d4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x3d8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x3dc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x3e0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x3e4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x3e8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x3ec | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x3f0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x3f4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x3f8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x3fc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x400 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_14`](#dio_pad_sleep_regwen) | 0x404 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_15`](#dio_pad_sleep_regwen) | 0x408 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_16`](#dio_pad_sleep_regwen) | 0x40c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_17`](#dio_pad_sleep_regwen) | 0x410 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_18`](#dio_pad_sleep_regwen) | 0x414 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_19`](#dio_pad_sleep_regwen) | 0x418 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_20`](#dio_pad_sleep_regwen) | 0x41c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_21`](#dio_pad_sleep_regwen) | 0x420 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_22`](#dio_pad_sleep_regwen) | 0x424 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_23`](#dio_pad_sleep_regwen) | 0x428 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_24`](#dio_pad_sleep_regwen) | 0x42c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_25`](#dio_pad_sleep_regwen) | 0x430 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_26`](#dio_pad_sleep_regwen) | 0x434 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_27`](#dio_pad_sleep_regwen) | 0x438 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_28`](#dio_pad_sleep_regwen) | 0x43c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_29`](#dio_pad_sleep_regwen) | 0x440 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_30`](#dio_pad_sleep_regwen) | 0x444 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_31`](#dio_pad_sleep_regwen) | 0x448 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_32`](#dio_pad_sleep_regwen) | 0x44c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_33`](#dio_pad_sleep_regwen) | 0x450 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_34`](#dio_pad_sleep_regwen) | 0x454 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_35`](#dio_pad_sleep_regwen) | 0x458 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_36`](#dio_pad_sleep_regwen) | 0x45c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_37`](#dio_pad_sleep_regwen) | 0x460 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_38`](#dio_pad_sleep_regwen) | 0x464 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_39`](#dio_pad_sleep_regwen) | 0x468 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_40`](#dio_pad_sleep_regwen) | 0x46c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_41`](#dio_pad_sleep_regwen) | 0x470 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_42`](#dio_pad_sleep_regwen) | 0x474 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_43`](#dio_pad_sleep_regwen) | 0x478 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_44`](#dio_pad_sleep_regwen) | 0x47c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_45`](#dio_pad_sleep_regwen) | 0x480 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_46`](#dio_pad_sleep_regwen) | 0x484 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_47`](#dio_pad_sleep_regwen) | 0x488 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_48`](#dio_pad_sleep_regwen) | 0x48c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_49`](#dio_pad_sleep_regwen) | 0x490 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_50`](#dio_pad_sleep_regwen) | 0x494 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_51`](#dio_pad_sleep_regwen) | 0x498 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_52`](#dio_pad_sleep_regwen) | 0x49c | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_53`](#dio_pad_sleep_regwen) | 0x4a0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_54`](#dio_pad_sleep_regwen) | 0x4a4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_55`](#dio_pad_sleep_regwen) | 0x4a8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_56`](#dio_pad_sleep_regwen) | 0x4ac | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_57`](#dio_pad_sleep_regwen) | 0x4b0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_58`](#dio_pad_sleep_regwen) | 0x4b4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_59`](#dio_pad_sleep_regwen) | 0x4b8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_60`](#dio_pad_sleep_regwen) | 0x4bc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_61`](#dio_pad_sleep_regwen) | 0x4c0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_62`](#dio_pad_sleep_regwen) | 0x4c4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_63`](#dio_pad_sleep_regwen) | 0x4c8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_64`](#dio_pad_sleep_regwen) | 0x4cc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_65`](#dio_pad_sleep_regwen) | 0x4d0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_66`](#dio_pad_sleep_regwen) | 0x4d4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_67`](#dio_pad_sleep_regwen) | 0x4d8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_68`](#dio_pad_sleep_regwen) | 0x4dc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_69`](#dio_pad_sleep_regwen) | 0x4e0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_70`](#dio_pad_sleep_regwen) | 0x4e4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_71`](#dio_pad_sleep_regwen) | 0x4e8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_72`](#dio_pad_sleep_regwen) | 0x4ec | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x4f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x4f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x4f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x4fc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x500 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x504 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x508 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x50c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x510 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x514 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x518 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x51c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x520 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x524 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_14`](#dio_pad_sleep_en) | 0x528 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_15`](#dio_pad_sleep_en) | 0x52c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_16`](#dio_pad_sleep_en) | 0x530 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_17`](#dio_pad_sleep_en) | 0x534 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_18`](#dio_pad_sleep_en) | 0x538 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_19`](#dio_pad_sleep_en) | 0x53c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_20`](#dio_pad_sleep_en) | 0x540 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_21`](#dio_pad_sleep_en) | 0x544 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_22`](#dio_pad_sleep_en) | 0x548 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_23`](#dio_pad_sleep_en) | 0x54c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_24`](#dio_pad_sleep_en) | 0x550 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_25`](#dio_pad_sleep_en) | 0x554 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_26`](#dio_pad_sleep_en) | 0x558 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_27`](#dio_pad_sleep_en) | 0x55c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_28`](#dio_pad_sleep_en) | 0x560 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_29`](#dio_pad_sleep_en) | 0x564 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_30`](#dio_pad_sleep_en) | 0x568 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_31`](#dio_pad_sleep_en) | 0x56c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_32`](#dio_pad_sleep_en) | 0x570 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_33`](#dio_pad_sleep_en) | 0x574 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_34`](#dio_pad_sleep_en) | 0x578 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_35`](#dio_pad_sleep_en) | 0x57c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_36`](#dio_pad_sleep_en) | 0x580 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_37`](#dio_pad_sleep_en) | 0x584 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_38`](#dio_pad_sleep_en) | 0x588 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_39`](#dio_pad_sleep_en) | 0x58c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_40`](#dio_pad_sleep_en) | 0x590 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_41`](#dio_pad_sleep_en) | 0x594 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_42`](#dio_pad_sleep_en) | 0x598 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_43`](#dio_pad_sleep_en) | 0x59c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_44`](#dio_pad_sleep_en) | 0x5a0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_45`](#dio_pad_sleep_en) | 0x5a4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_46`](#dio_pad_sleep_en) | 0x5a8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_47`](#dio_pad_sleep_en) | 0x5ac | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_48`](#dio_pad_sleep_en) | 0x5b0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_49`](#dio_pad_sleep_en) | 0x5b4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_50`](#dio_pad_sleep_en) | 0x5b8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_51`](#dio_pad_sleep_en) | 0x5bc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_52`](#dio_pad_sleep_en) | 0x5c0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_53`](#dio_pad_sleep_en) | 0x5c4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_54`](#dio_pad_sleep_en) | 0x5c8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_55`](#dio_pad_sleep_en) | 0x5cc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_56`](#dio_pad_sleep_en) | 0x5d0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_57`](#dio_pad_sleep_en) | 0x5d4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_58`](#dio_pad_sleep_en) | 0x5d8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_59`](#dio_pad_sleep_en) | 0x5dc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_60`](#dio_pad_sleep_en) | 0x5e0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_61`](#dio_pad_sleep_en) | 0x5e4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_62`](#dio_pad_sleep_en) | 0x5e8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_63`](#dio_pad_sleep_en) | 0x5ec | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_64`](#dio_pad_sleep_en) | 0x5f0 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_65`](#dio_pad_sleep_en) | 0x5f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_66`](#dio_pad_sleep_en) | 0x5f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_67`](#dio_pad_sleep_en) | 0x5fc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_68`](#dio_pad_sleep_en) | 0x600 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_69`](#dio_pad_sleep_en) | 0x604 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_70`](#dio_pad_sleep_en) | 0x608 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_71`](#dio_pad_sleep_en) | 0x60c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_72`](#dio_pad_sleep_en) | 0x610 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x614 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x618 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x61c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x620 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x624 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x628 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x62c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x630 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x634 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x638 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x63c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x640 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x644 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x648 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_14`](#dio_pad_sleep_mode) | 0x64c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_15`](#dio_pad_sleep_mode) | 0x650 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_16`](#dio_pad_sleep_mode) | 0x654 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_17`](#dio_pad_sleep_mode) | 0x658 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_18`](#dio_pad_sleep_mode) | 0x65c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_19`](#dio_pad_sleep_mode) | 0x660 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_20`](#dio_pad_sleep_mode) | 0x664 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_21`](#dio_pad_sleep_mode) | 0x668 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_22`](#dio_pad_sleep_mode) | 0x66c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_23`](#dio_pad_sleep_mode) | 0x670 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_24`](#dio_pad_sleep_mode) | 0x674 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_25`](#dio_pad_sleep_mode) | 0x678 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_26`](#dio_pad_sleep_mode) | 0x67c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_27`](#dio_pad_sleep_mode) | 0x680 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_28`](#dio_pad_sleep_mode) | 0x684 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_29`](#dio_pad_sleep_mode) | 0x688 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_30`](#dio_pad_sleep_mode) | 0x68c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_31`](#dio_pad_sleep_mode) | 0x690 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_32`](#dio_pad_sleep_mode) | 0x694 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_33`](#dio_pad_sleep_mode) | 0x698 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_34`](#dio_pad_sleep_mode) | 0x69c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_35`](#dio_pad_sleep_mode) | 0x6a0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_36`](#dio_pad_sleep_mode) | 0x6a4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_37`](#dio_pad_sleep_mode) | 0x6a8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_38`](#dio_pad_sleep_mode) | 0x6ac | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_39`](#dio_pad_sleep_mode) | 0x6b0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_40`](#dio_pad_sleep_mode) | 0x6b4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_41`](#dio_pad_sleep_mode) | 0x6b8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_42`](#dio_pad_sleep_mode) | 0x6bc | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_43`](#dio_pad_sleep_mode) | 0x6c0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_44`](#dio_pad_sleep_mode) | 0x6c4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_45`](#dio_pad_sleep_mode) | 0x6c8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_46`](#dio_pad_sleep_mode) | 0x6cc | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_47`](#dio_pad_sleep_mode) | 0x6d0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_48`](#dio_pad_sleep_mode) | 0x6d4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_49`](#dio_pad_sleep_mode) | 0x6d8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_50`](#dio_pad_sleep_mode) | 0x6dc | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_51`](#dio_pad_sleep_mode) | 0x6e0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_52`](#dio_pad_sleep_mode) | 0x6e4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_53`](#dio_pad_sleep_mode) | 0x6e8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_54`](#dio_pad_sleep_mode) | 0x6ec | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_55`](#dio_pad_sleep_mode) | 0x6f0 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_56`](#dio_pad_sleep_mode) | 0x6f4 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_57`](#dio_pad_sleep_mode) | 0x6f8 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_58`](#dio_pad_sleep_mode) | 0x6fc | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_59`](#dio_pad_sleep_mode) | 0x700 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_60`](#dio_pad_sleep_mode) | 0x704 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_61`](#dio_pad_sleep_mode) | 0x708 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_62`](#dio_pad_sleep_mode) | 0x70c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_63`](#dio_pad_sleep_mode) | 0x710 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_64`](#dio_pad_sleep_mode) | 0x714 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_65`](#dio_pad_sleep_mode) | 0x718 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_66`](#dio_pad_sleep_mode) | 0x71c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_67`](#dio_pad_sleep_mode) | 0x720 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_68`](#dio_pad_sleep_mode) | 0x724 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_69`](#dio_pad_sleep_mode) | 0x728 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_70`](#dio_pad_sleep_mode) | 0x72c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_71`](#dio_pad_sleep_mode) | 0x730 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_72`](#dio_pad_sleep_mode) | 0x734 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x738 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x73c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x740 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x744 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x748 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x74c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x750 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x754 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x758 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x75c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x760 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x764 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x768 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x76c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x770 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x774 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x778 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x77c | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x780 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x784 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x788 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x78c | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x790 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x794 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x798 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x79c | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x7a0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x7a4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x7a8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x7ac | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x7b0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x7b4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x7b8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x7bc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x7c0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x7c4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x7c8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x7cc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x7d0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x7d4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_CAUSE`](#wkup_cause) | 0x7d8 | 4 | Cause registers for wakeup detectors. | + +## ALERT_TEST +Alert Test Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:-------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | + +## MIO_PERIPH_INSEL_REGWEN +Register write enable for MIO peripheral input selects. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:--------------------------|:---------| +| MIO_PERIPH_INSEL_REGWEN_0 | 0x4 | +| MIO_PERIPH_INSEL_REGWEN_1 | 0x8 | +| MIO_PERIPH_INSEL_REGWEN_2 | 0xc | +| MIO_PERIPH_INSEL_REGWEN_3 | 0x10 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding MIO_PERIPH_INSEL is not writable anymore. | + +## MIO_PERIPH_INSEL +For each peripheral input, this selects the muxable pad input. +- Reset default: `0x0` +- Reset mask: `0xf` +- Register enable: [`MIO_PERIPH_INSEL_REGWEN`](#mio_periph_insel_regwen) + +### Instances + +| Name | Offset | +|:-------------------|:---------| +| MIO_PERIPH_INSEL_0 | 0x14 | +| MIO_PERIPH_INSEL_1 | 0x18 | +| MIO_PERIPH_INSEL_2 | 0x1c | +| MIO_PERIPH_INSEL_3 | 0x20 | + + +### Fields + +```wavejson +{"reg": [{"name": "IN", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x0 | IN | 0: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index). | + +## MIO_OUTSEL_REGWEN +Register write enable for MIO output selects. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:---------------------|:---------| +| MIO_OUTSEL_REGWEN_0 | 0x24 | +| MIO_OUTSEL_REGWEN_1 | 0x28 | +| MIO_OUTSEL_REGWEN_2 | 0x2c | +| MIO_OUTSEL_REGWEN_3 | 0x30 | +| MIO_OUTSEL_REGWEN_4 | 0x34 | +| MIO_OUTSEL_REGWEN_5 | 0x38 | +| MIO_OUTSEL_REGWEN_6 | 0x3c | +| MIO_OUTSEL_REGWEN_7 | 0x40 | +| MIO_OUTSEL_REGWEN_8 | 0x44 | +| MIO_OUTSEL_REGWEN_9 | 0x48 | +| MIO_OUTSEL_REGWEN_10 | 0x4c | +| MIO_OUTSEL_REGWEN_11 | 0x50 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding MIO_OUTSEL is not writable anymore. | + +## MIO_OUTSEL +For each muxable pad, this selects the peripheral output. +- Reset default: `0x2` +- Reset mask: `0x7` +- Register enable: [`MIO_OUTSEL_REGWEN`](#mio_outsel_regwen) + +### Instances + +| Name | Offset | +|:--------------|:---------| +| MIO_OUTSEL_0 | 0x54 | +| MIO_OUTSEL_1 | 0x58 | +| MIO_OUTSEL_2 | 0x5c | +| MIO_OUTSEL_3 | 0x60 | +| MIO_OUTSEL_4 | 0x64 | +| MIO_OUTSEL_5 | 0x68 | +| MIO_OUTSEL_6 | 0x6c | +| MIO_OUTSEL_7 | 0x70 | +| MIO_OUTSEL_8 | 0x74 | +| MIO_OUTSEL_9 | 0x78 | +| MIO_OUTSEL_10 | 0x7c | +| MIO_OUTSEL_11 | 0x80 | + + +### Fields + +```wavejson +{"reg": [{"name": "OUT", "bits": 3, "attr": ["rw"], "rotate": 0}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2:0 | rw | 0x2 | OUT | 0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index). | + +## MIO_PAD_ATTR_REGWEN +Register write enable for MIO PAD attributes. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| MIO_PAD_ATTR_REGWEN_0 | 0x84 | +| MIO_PAD_ATTR_REGWEN_1 | 0x88 | +| MIO_PAD_ATTR_REGWEN_2 | 0x8c | +| MIO_PAD_ATTR_REGWEN_3 | 0x90 | +| MIO_PAD_ATTR_REGWEN_4 | 0x94 | +| MIO_PAD_ATTR_REGWEN_5 | 0x98 | +| MIO_PAD_ATTR_REGWEN_6 | 0x9c | +| MIO_PAD_ATTR_REGWEN_7 | 0xa0 | +| MIO_PAD_ATTR_REGWEN_8 | 0xa4 | +| MIO_PAD_ATTR_REGWEN_9 | 0xa8 | +| MIO_PAD_ATTR_REGWEN_10 | 0xac | +| MIO_PAD_ATTR_REGWEN_11 | 0xb0 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding [`MIO_PAD_ATTR`](#mio_pad_attr) is not writable anymore. | + +## MIO_PAD_ATTR +Muxed pad attributes. +This register has WARL behavior since not each pad type may support +all attributes. +The muxed pad that is used for TAP strap 0 has a different reset value, with `pull_en` set to 1. +- Reset default: `0x0` +- Reset mask: `0xf300ff` +- Register enable: [`MIO_PAD_ATTR_REGWEN`](#mio_pad_attr_regwen) + +### Instances + +| Name | Offset | +|:----------------|:---------| +| MIO_PAD_ATTR_0 | 0xb4 | +| MIO_PAD_ATTR_1 | 0xb8 | +| MIO_PAD_ATTR_2 | 0xbc | +| MIO_PAD_ATTR_3 | 0xc0 | +| MIO_PAD_ATTR_4 | 0xc4 | +| MIO_PAD_ATTR_5 | 0xc8 | +| MIO_PAD_ATTR_6 | 0xcc | +| MIO_PAD_ATTR_7 | 0xd0 | +| MIO_PAD_ATTR_8 | 0xd4 | +| MIO_PAD_ATTR_9 | 0xd8 | +| MIO_PAD_ATTR_10 | 0xdc | +| MIO_PAD_ATTR_11 | 0xe0 | + + +### Fields + +```wavejson +{"reg": [{"name": "invert", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "virtual_od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_select", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "keeper_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "schmitt_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "input_disable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 8}, {"name": "slew_rate", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 2}, {"name": "drive_strength", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:------------------------------------------------| +| 31:24 | | | Reserved | +| 23:20 | rw | 0x0 | [drive_strength](#mio_pad_attr--drive_strength) | +| 19:18 | | | Reserved | +| 17:16 | rw | 0x0 | [slew_rate](#mio_pad_attr--slew_rate) | +| 15:8 | | | Reserved | +| 7 | rw | 0x0 | [input_disable](#mio_pad_attr--input_disable) | +| 6 | rw | 0x0 | [od_en](#mio_pad_attr--od_en) | +| 5 | rw | 0x0 | [schmitt_en](#mio_pad_attr--schmitt_en) | +| 4 | rw | 0x0 | [keeper_en](#mio_pad_attr--keeper_en) | +| 3 | rw | 0x0 | [pull_select](#mio_pad_attr--pull_select) | +| 2 | rw | 0x0 | [pull_en](#mio_pad_attr--pull_en) | +| 1 | rw | 0x0 | [virtual_od_en](#mio_pad_attr--virtual_od_en) | +| 0 | rw | 0x0 | [invert](#mio_pad_attr--invert) | + +### MIO_PAD_ATTR . drive_strength +Drive strength (0x0: weakest, 0xf: strongest) + +### MIO_PAD_ATTR . slew_rate +Slew rate (0x0: slowest, 0x3: fastest). + +### MIO_PAD_ATTR . input_disable +Disable input drivers. +Setting this to 1 for pads that are not used as input can reduce their leakage current. + +### MIO_PAD_ATTR . od_en +Enable open drain. + +### MIO_PAD_ATTR . schmitt_en +Enable the schmitt trigger. + +### MIO_PAD_ATTR . keeper_en +Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog `trireg`. + +### MIO_PAD_ATTR . pull_select +Pull select (0: pull-down, 1: pull-up). + +| Value | Name | Description | +|:--------|:----------|:-------------------------------| +| 0x0 | pull_down | Select the pull-down resistor. | +| 0x1 | pull_up | Select the pull-up resistor. | + + +### MIO_PAD_ATTR . pull_en +Enable pull-up or pull-down resistor. + +### MIO_PAD_ATTR . virtual_od_en +Enable virtual open drain. + +### MIO_PAD_ATTR . invert +Invert input and output levels. + +## DIO_PAD_ATTR_REGWEN +Register write enable for DIO PAD attributes. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| DIO_PAD_ATTR_REGWEN_0 | 0xe4 | +| DIO_PAD_ATTR_REGWEN_1 | 0xe8 | +| DIO_PAD_ATTR_REGWEN_2 | 0xec | +| DIO_PAD_ATTR_REGWEN_3 | 0xf0 | +| DIO_PAD_ATTR_REGWEN_4 | 0xf4 | +| DIO_PAD_ATTR_REGWEN_5 | 0xf8 | +| DIO_PAD_ATTR_REGWEN_6 | 0xfc | +| DIO_PAD_ATTR_REGWEN_7 | 0x100 | +| DIO_PAD_ATTR_REGWEN_8 | 0x104 | +| DIO_PAD_ATTR_REGWEN_9 | 0x108 | +| DIO_PAD_ATTR_REGWEN_10 | 0x10c | +| DIO_PAD_ATTR_REGWEN_11 | 0x110 | +| DIO_PAD_ATTR_REGWEN_12 | 0x114 | +| DIO_PAD_ATTR_REGWEN_13 | 0x118 | +| DIO_PAD_ATTR_REGWEN_14 | 0x11c | +| DIO_PAD_ATTR_REGWEN_15 | 0x120 | +| DIO_PAD_ATTR_REGWEN_16 | 0x124 | +| DIO_PAD_ATTR_REGWEN_17 | 0x128 | +| DIO_PAD_ATTR_REGWEN_18 | 0x12c | +| DIO_PAD_ATTR_REGWEN_19 | 0x130 | +| DIO_PAD_ATTR_REGWEN_20 | 0x134 | +| DIO_PAD_ATTR_REGWEN_21 | 0x138 | +| DIO_PAD_ATTR_REGWEN_22 | 0x13c | +| DIO_PAD_ATTR_REGWEN_23 | 0x140 | +| DIO_PAD_ATTR_REGWEN_24 | 0x144 | +| DIO_PAD_ATTR_REGWEN_25 | 0x148 | +| DIO_PAD_ATTR_REGWEN_26 | 0x14c | +| DIO_PAD_ATTR_REGWEN_27 | 0x150 | +| DIO_PAD_ATTR_REGWEN_28 | 0x154 | +| DIO_PAD_ATTR_REGWEN_29 | 0x158 | +| DIO_PAD_ATTR_REGWEN_30 | 0x15c | +| DIO_PAD_ATTR_REGWEN_31 | 0x160 | +| DIO_PAD_ATTR_REGWEN_32 | 0x164 | +| DIO_PAD_ATTR_REGWEN_33 | 0x168 | +| DIO_PAD_ATTR_REGWEN_34 | 0x16c | +| DIO_PAD_ATTR_REGWEN_35 | 0x170 | +| DIO_PAD_ATTR_REGWEN_36 | 0x174 | +| DIO_PAD_ATTR_REGWEN_37 | 0x178 | +| DIO_PAD_ATTR_REGWEN_38 | 0x17c | +| DIO_PAD_ATTR_REGWEN_39 | 0x180 | +| DIO_PAD_ATTR_REGWEN_40 | 0x184 | +| DIO_PAD_ATTR_REGWEN_41 | 0x188 | +| DIO_PAD_ATTR_REGWEN_42 | 0x18c | +| DIO_PAD_ATTR_REGWEN_43 | 0x190 | +| DIO_PAD_ATTR_REGWEN_44 | 0x194 | +| DIO_PAD_ATTR_REGWEN_45 | 0x198 | +| DIO_PAD_ATTR_REGWEN_46 | 0x19c | +| DIO_PAD_ATTR_REGWEN_47 | 0x1a0 | +| DIO_PAD_ATTR_REGWEN_48 | 0x1a4 | +| DIO_PAD_ATTR_REGWEN_49 | 0x1a8 | +| DIO_PAD_ATTR_REGWEN_50 | 0x1ac | +| DIO_PAD_ATTR_REGWEN_51 | 0x1b0 | +| DIO_PAD_ATTR_REGWEN_52 | 0x1b4 | +| DIO_PAD_ATTR_REGWEN_53 | 0x1b8 | +| DIO_PAD_ATTR_REGWEN_54 | 0x1bc | +| DIO_PAD_ATTR_REGWEN_55 | 0x1c0 | +| DIO_PAD_ATTR_REGWEN_56 | 0x1c4 | +| DIO_PAD_ATTR_REGWEN_57 | 0x1c8 | +| DIO_PAD_ATTR_REGWEN_58 | 0x1cc | +| DIO_PAD_ATTR_REGWEN_59 | 0x1d0 | +| DIO_PAD_ATTR_REGWEN_60 | 0x1d4 | +| DIO_PAD_ATTR_REGWEN_61 | 0x1d8 | +| DIO_PAD_ATTR_REGWEN_62 | 0x1dc | +| DIO_PAD_ATTR_REGWEN_63 | 0x1e0 | +| DIO_PAD_ATTR_REGWEN_64 | 0x1e4 | +| DIO_PAD_ATTR_REGWEN_65 | 0x1e8 | +| DIO_PAD_ATTR_REGWEN_66 | 0x1ec | +| DIO_PAD_ATTR_REGWEN_67 | 0x1f0 | +| DIO_PAD_ATTR_REGWEN_68 | 0x1f4 | +| DIO_PAD_ATTR_REGWEN_69 | 0x1f8 | +| DIO_PAD_ATTR_REGWEN_70 | 0x1fc | +| DIO_PAD_ATTR_REGWEN_71 | 0x200 | +| DIO_PAD_ATTR_REGWEN_72 | 0x204 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding [`DIO_PAD_ATTR`](#dio_pad_attr) is not writable anymore. | + +## DIO_PAD_ATTR +Dedicated pad attributes. +This register has WARL behavior since not each pad type may support +all attributes. +- Reset default: `0x0` +- Reset mask: `0xf300ff` +- Register enable: [`DIO_PAD_ATTR_REGWEN`](#dio_pad_attr_regwen) + +### Instances + +| Name | Offset | +|:----------------|:---------| +| DIO_PAD_ATTR_0 | 0x208 | +| DIO_PAD_ATTR_1 | 0x20c | +| DIO_PAD_ATTR_2 | 0x210 | +| DIO_PAD_ATTR_3 | 0x214 | +| DIO_PAD_ATTR_4 | 0x218 | +| DIO_PAD_ATTR_5 | 0x21c | +| DIO_PAD_ATTR_6 | 0x220 | +| DIO_PAD_ATTR_7 | 0x224 | +| DIO_PAD_ATTR_8 | 0x228 | +| DIO_PAD_ATTR_9 | 0x22c | +| DIO_PAD_ATTR_10 | 0x230 | +| DIO_PAD_ATTR_11 | 0x234 | +| DIO_PAD_ATTR_12 | 0x238 | +| DIO_PAD_ATTR_13 | 0x23c | +| DIO_PAD_ATTR_14 | 0x240 | +| DIO_PAD_ATTR_15 | 0x244 | +| DIO_PAD_ATTR_16 | 0x248 | +| DIO_PAD_ATTR_17 | 0x24c | +| DIO_PAD_ATTR_18 | 0x250 | +| DIO_PAD_ATTR_19 | 0x254 | +| DIO_PAD_ATTR_20 | 0x258 | +| DIO_PAD_ATTR_21 | 0x25c | +| DIO_PAD_ATTR_22 | 0x260 | +| DIO_PAD_ATTR_23 | 0x264 | +| DIO_PAD_ATTR_24 | 0x268 | +| DIO_PAD_ATTR_25 | 0x26c | +| DIO_PAD_ATTR_26 | 0x270 | +| DIO_PAD_ATTR_27 | 0x274 | +| DIO_PAD_ATTR_28 | 0x278 | +| DIO_PAD_ATTR_29 | 0x27c | +| DIO_PAD_ATTR_30 | 0x280 | +| DIO_PAD_ATTR_31 | 0x284 | +| DIO_PAD_ATTR_32 | 0x288 | +| DIO_PAD_ATTR_33 | 0x28c | +| DIO_PAD_ATTR_34 | 0x290 | +| DIO_PAD_ATTR_35 | 0x294 | +| DIO_PAD_ATTR_36 | 0x298 | +| DIO_PAD_ATTR_37 | 0x29c | +| DIO_PAD_ATTR_38 | 0x2a0 | +| DIO_PAD_ATTR_39 | 0x2a4 | +| DIO_PAD_ATTR_40 | 0x2a8 | +| DIO_PAD_ATTR_41 | 0x2ac | +| DIO_PAD_ATTR_42 | 0x2b0 | +| DIO_PAD_ATTR_43 | 0x2b4 | +| DIO_PAD_ATTR_44 | 0x2b8 | +| DIO_PAD_ATTR_45 | 0x2bc | +| DIO_PAD_ATTR_46 | 0x2c0 | +| DIO_PAD_ATTR_47 | 0x2c4 | +| DIO_PAD_ATTR_48 | 0x2c8 | +| DIO_PAD_ATTR_49 | 0x2cc | +| DIO_PAD_ATTR_50 | 0x2d0 | +| DIO_PAD_ATTR_51 | 0x2d4 | +| DIO_PAD_ATTR_52 | 0x2d8 | +| DIO_PAD_ATTR_53 | 0x2dc | +| DIO_PAD_ATTR_54 | 0x2e0 | +| DIO_PAD_ATTR_55 | 0x2e4 | +| DIO_PAD_ATTR_56 | 0x2e8 | +| DIO_PAD_ATTR_57 | 0x2ec | +| DIO_PAD_ATTR_58 | 0x2f0 | +| DIO_PAD_ATTR_59 | 0x2f4 | +| DIO_PAD_ATTR_60 | 0x2f8 | +| DIO_PAD_ATTR_61 | 0x2fc | +| DIO_PAD_ATTR_62 | 0x300 | +| DIO_PAD_ATTR_63 | 0x304 | +| DIO_PAD_ATTR_64 | 0x308 | +| DIO_PAD_ATTR_65 | 0x30c | +| DIO_PAD_ATTR_66 | 0x310 | +| DIO_PAD_ATTR_67 | 0x314 | +| DIO_PAD_ATTR_68 | 0x318 | +| DIO_PAD_ATTR_69 | 0x31c | +| DIO_PAD_ATTR_70 | 0x320 | +| DIO_PAD_ATTR_71 | 0x324 | +| DIO_PAD_ATTR_72 | 0x328 | + + +### Fields + +```wavejson +{"reg": [{"name": "invert", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "virtual_od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_select", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "keeper_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "schmitt_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "input_disable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 8}, {"name": "slew_rate", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 2}, {"name": "drive_strength", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:------------------------------------------------| +| 31:24 | | | Reserved | +| 23:20 | rw | 0x0 | [drive_strength](#dio_pad_attr--drive_strength) | +| 19:18 | | | Reserved | +| 17:16 | rw | 0x0 | [slew_rate](#dio_pad_attr--slew_rate) | +| 15:8 | | | Reserved | +| 7 | rw | 0x0 | [input_disable](#dio_pad_attr--input_disable) | +| 6 | rw | 0x0 | [od_en](#dio_pad_attr--od_en) | +| 5 | rw | 0x0 | [schmitt_en](#dio_pad_attr--schmitt_en) | +| 4 | rw | 0x0 | [keeper_en](#dio_pad_attr--keeper_en) | +| 3 | rw | 0x0 | [pull_select](#dio_pad_attr--pull_select) | +| 2 | rw | 0x0 | [pull_en](#dio_pad_attr--pull_en) | +| 1 | rw | 0x0 | [virtual_od_en](#dio_pad_attr--virtual_od_en) | +| 0 | rw | 0x0 | [invert](#dio_pad_attr--invert) | + +### DIO_PAD_ATTR . drive_strength +Drive strength (0x0: weakest, 0xf: strongest) + +### DIO_PAD_ATTR . slew_rate +Slew rate (0x0: slowest, 0x3: fastest). + +### DIO_PAD_ATTR . input_disable +Disable input drivers. +Setting this to 1 for pads that are not used as input can reduce their leakage current. + +### DIO_PAD_ATTR . od_en +Enable open drain. + +### DIO_PAD_ATTR . schmitt_en +Enable the schmitt trigger. + +### DIO_PAD_ATTR . keeper_en +Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog `trireg`. + +### DIO_PAD_ATTR . pull_select +Pull select (0: pull-down, 1: pull-up). + +| Value | Name | Description | +|:--------|:----------|:-------------------------------| +| 0x0 | pull_down | Select the pull-down resistor. | +| 0x1 | pull_up | Select the pull-up resistor. | + + +### DIO_PAD_ATTR . pull_en +Enable pull-up or pull-down resistor. + +### DIO_PAD_ATTR . virtual_od_en +Enable virtual open drain. + +### DIO_PAD_ATTR . invert +Invert input and output levels. + +## MIO_PAD_SLEEP_STATUS +Register indicating whether the corresponding pad is in sleep mode. +- Offset: `0x32c` +- Reset default: `0x0` +- Reset mask: `0xfff` + +### Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_6", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_7", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_8", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_9", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_10", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_11", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:12 | | | | Reserved | +| 11 | rw0c | 0x0 | EN_11 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 10 | rw0c | 0x0 | EN_10 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 9 | rw0c | 0x0 | EN_9 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 8 | rw0c | 0x0 | EN_8 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 7 | rw0c | 0x0 | EN_7 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 6 | rw0c | 0x0 | EN_6 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 5 | rw0c | 0x0 | EN_5 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 4 | rw0c | 0x0 | EN_4 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 3 | rw0c | 0x0 | EN_3 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 2 | rw0c | 0x0 | EN_2 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 1 | rw0c | 0x0 | EN_1 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 0 | rw0c | 0x0 | EN_0 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | + +## MIO_PAD_SLEEP_REGWEN +Register write enable for MIO sleep value configuration. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:------------------------|:---------| +| MIO_PAD_SLEEP_REGWEN_0 | 0x330 | +| MIO_PAD_SLEEP_REGWEN_1 | 0x334 | +| MIO_PAD_SLEEP_REGWEN_2 | 0x338 | +| MIO_PAD_SLEEP_REGWEN_3 | 0x33c | +| MIO_PAD_SLEEP_REGWEN_4 | 0x340 | +| MIO_PAD_SLEEP_REGWEN_5 | 0x344 | +| MIO_PAD_SLEEP_REGWEN_6 | 0x348 | +| MIO_PAD_SLEEP_REGWEN_7 | 0x34c | +| MIO_PAD_SLEEP_REGWEN_8 | 0x350 | +| MIO_PAD_SLEEP_REGWEN_9 | 0x354 | +| MIO_PAD_SLEEP_REGWEN_10 | 0x358 | +| MIO_PAD_SLEEP_REGWEN_11 | 0x35c | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding [`MIO_PAD_SLEEP_MODE`](#mio_pad_sleep_mode) is not writable anymore. | + +## MIO_PAD_SLEEP_EN +Enables the sleep mode of the corresponding muxed pad. +- Reset default: `0x0` +- Reset mask: `0x1` +- Register enable: [`MIO_PAD_SLEEP_REGWEN`](#mio_pad_sleep_regwen) + +### Instances + +| Name | Offset | +|:--------------------|:---------| +| MIO_PAD_SLEEP_EN_0 | 0x360 | +| MIO_PAD_SLEEP_EN_1 | 0x364 | +| MIO_PAD_SLEEP_EN_2 | 0x368 | +| MIO_PAD_SLEEP_EN_3 | 0x36c | +| MIO_PAD_SLEEP_EN_4 | 0x370 | +| MIO_PAD_SLEEP_EN_5 | 0x374 | +| MIO_PAD_SLEEP_EN_6 | 0x378 | +| MIO_PAD_SLEEP_EN_7 | 0x37c | +| MIO_PAD_SLEEP_EN_8 | 0x380 | +| MIO_PAD_SLEEP_EN_9 | 0x384 | +| MIO_PAD_SLEEP_EN_10 | 0x388 | +| MIO_PAD_SLEEP_EN_11 | 0x38c | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------| +| 31:1 | | | Reserved | +| 0 | rw | 0x0 | [EN](#mio_pad_sleep_en--en) | + +### MIO_PAD_SLEEP_EN . EN +Deep sleep mode enable. +If this bit is set to 1 the corresponding pad will enable the sleep behavior +specified in [`MIO_PAD_SLEEP_MODE`](#mio_pad_sleep_mode) upon deep sleep entry, and the corresponding bit +in [`MIO_PAD_SLEEP_STATUS`](#mio_pad_sleep_status) will be set to 1. +The pad remains in deep sleep mode until the corresponding bit in +[`MIO_PAD_SLEEP_STATUS`](#mio_pad_sleep_status) is cleared by SW. +Note that if an always on peripheral is connected to a specific MIO pad, +the corresponding [`MIO_PAD_SLEEP_EN`](#mio_pad_sleep_en) bit should be set to 0. + +## MIO_PAD_SLEEP_MODE +Defines sleep behavior of the corresponding muxed pad. +- Reset default: `0x2` +- Reset mask: `0x3` +- Register enable: [`MIO_PAD_SLEEP_REGWEN`](#mio_pad_sleep_regwen) + +### Instances + +| Name | Offset | +|:----------------------|:---------| +| MIO_PAD_SLEEP_MODE_0 | 0x390 | +| MIO_PAD_SLEEP_MODE_1 | 0x394 | +| MIO_PAD_SLEEP_MODE_2 | 0x398 | +| MIO_PAD_SLEEP_MODE_3 | 0x39c | +| MIO_PAD_SLEEP_MODE_4 | 0x3a0 | +| MIO_PAD_SLEEP_MODE_5 | 0x3a4 | +| MIO_PAD_SLEEP_MODE_6 | 0x3a8 | +| MIO_PAD_SLEEP_MODE_7 | 0x3ac | +| MIO_PAD_SLEEP_MODE_8 | 0x3b0 | +| MIO_PAD_SLEEP_MODE_9 | 0x3b4 | +| MIO_PAD_SLEEP_MODE_10 | 0x3b8 | +| MIO_PAD_SLEEP_MODE_11 | 0x3bc | + + +### Fields + +```wavejson +{"reg": [{"name": "OUT", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:--------------------------------| +| 31:2 | | | Reserved | +| 1:0 | rw | 0x2 | [OUT](#mio_pad_sleep_mode--out) | + +### MIO_PAD_SLEEP_MODE . OUT +Value to drive in deep sleep. + +| Value | Name | Description | +|:--------|:---------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | Tie-Low | The pad is driven actively to zero in deep sleep mode. | +| 0x1 | Tie-High | The pad is driven actively to one in deep sleep mode. | +| 0x2 | High-Z | The pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in [`MIO_PAD_ATTR.`](#mio_pad_attr) | +| 0x3 | Keep | Keep last driven value (including high-Z). | + + +## DIO_PAD_SLEEP_STATUS_0 +Register indicating whether the corresponding pad is in sleep mode. +- Offset: `0x3c0` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_6", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_7", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_8", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_9", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_10", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_11", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_12", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_13", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_14", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_15", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_16", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_17", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_18", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_19", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_20", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_21", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_22", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_23", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_24", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_25", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_26", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_27", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_28", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_29", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_30", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_31", "bits": 1, "attr": ["rw0c"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31 | rw0c | 0x0 | EN_31 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 30 | rw0c | 0x0 | EN_30 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 29 | rw0c | 0x0 | EN_29 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 28 | rw0c | 0x0 | EN_28 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 27 | rw0c | 0x0 | EN_27 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 26 | rw0c | 0x0 | EN_26 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 25 | rw0c | 0x0 | EN_25 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 24 | rw0c | 0x0 | EN_24 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 23 | rw0c | 0x0 | EN_23 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 22 | rw0c | 0x0 | EN_22 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 21 | rw0c | 0x0 | EN_21 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 20 | rw0c | 0x0 | EN_20 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 19 | rw0c | 0x0 | EN_19 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 18 | rw0c | 0x0 | EN_18 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 17 | rw0c | 0x0 | EN_17 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 16 | rw0c | 0x0 | EN_16 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 15 | rw0c | 0x0 | EN_15 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 14 | rw0c | 0x0 | EN_14 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 13 | rw0c | 0x0 | EN_13 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 12 | rw0c | 0x0 | EN_12 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 11 | rw0c | 0x0 | EN_11 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 10 | rw0c | 0x0 | EN_10 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 9 | rw0c | 0x0 | EN_9 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 8 | rw0c | 0x0 | EN_8 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 7 | rw0c | 0x0 | EN_7 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 6 | rw0c | 0x0 | EN_6 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 5 | rw0c | 0x0 | EN_5 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 4 | rw0c | 0x0 | EN_4 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 3 | rw0c | 0x0 | EN_3 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 2 | rw0c | 0x0 | EN_2 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 1 | rw0c | 0x0 | EN_1 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | +| 0 | rw0c | 0x0 | EN_0 | This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled ([`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode)) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit. | + +## DIO_PAD_SLEEP_STATUS_1 +Register indicating whether the corresponding pad is in sleep mode. +- Offset: `0x3c4` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "EN_32", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_33", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_34", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_35", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_36", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_37", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_38", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_39", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_40", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_41", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_42", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_43", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_44", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_45", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_46", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_47", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_48", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_49", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_50", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_51", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_52", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_53", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_54", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_55", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_56", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_57", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_58", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_59", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_60", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_61", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_62", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_63", "bits": 1, "attr": ["rw0c"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31 | rw0c | 0x0 | EN_63 | For DIO_PAD1 | +| 30 | rw0c | 0x0 | EN_62 | For DIO_PAD1 | +| 29 | rw0c | 0x0 | EN_61 | For DIO_PAD1 | +| 28 | rw0c | 0x0 | EN_60 | For DIO_PAD1 | +| 27 | rw0c | 0x0 | EN_59 | For DIO_PAD1 | +| 26 | rw0c | 0x0 | EN_58 | For DIO_PAD1 | +| 25 | rw0c | 0x0 | EN_57 | For DIO_PAD1 | +| 24 | rw0c | 0x0 | EN_56 | For DIO_PAD1 | +| 23 | rw0c | 0x0 | EN_55 | For DIO_PAD1 | +| 22 | rw0c | 0x0 | EN_54 | For DIO_PAD1 | +| 21 | rw0c | 0x0 | EN_53 | For DIO_PAD1 | +| 20 | rw0c | 0x0 | EN_52 | For DIO_PAD1 | +| 19 | rw0c | 0x0 | EN_51 | For DIO_PAD1 | +| 18 | rw0c | 0x0 | EN_50 | For DIO_PAD1 | +| 17 | rw0c | 0x0 | EN_49 | For DIO_PAD1 | +| 16 | rw0c | 0x0 | EN_48 | For DIO_PAD1 | +| 15 | rw0c | 0x0 | EN_47 | For DIO_PAD1 | +| 14 | rw0c | 0x0 | EN_46 | For DIO_PAD1 | +| 13 | rw0c | 0x0 | EN_45 | For DIO_PAD1 | +| 12 | rw0c | 0x0 | EN_44 | For DIO_PAD1 | +| 11 | rw0c | 0x0 | EN_43 | For DIO_PAD1 | +| 10 | rw0c | 0x0 | EN_42 | For DIO_PAD1 | +| 9 | rw0c | 0x0 | EN_41 | For DIO_PAD1 | +| 8 | rw0c | 0x0 | EN_40 | For DIO_PAD1 | +| 7 | rw0c | 0x0 | EN_39 | For DIO_PAD1 | +| 6 | rw0c | 0x0 | EN_38 | For DIO_PAD1 | +| 5 | rw0c | 0x0 | EN_37 | For DIO_PAD1 | +| 4 | rw0c | 0x0 | EN_36 | For DIO_PAD1 | +| 3 | rw0c | 0x0 | EN_35 | For DIO_PAD1 | +| 2 | rw0c | 0x0 | EN_34 | For DIO_PAD1 | +| 1 | rw0c | 0x0 | EN_33 | For DIO_PAD1 | +| 0 | rw0c | 0x0 | EN_32 | For DIO_PAD1 | + +## DIO_PAD_SLEEP_STATUS_2 +Register indicating whether the corresponding pad is in sleep mode. +- Offset: `0x3c8` +- Reset default: `0x0` +- Reset mask: `0x1ff` + +### Fields + +```wavejson +{"reg": [{"name": "EN_64", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_65", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_66", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_67", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_68", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_69", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_70", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_71", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_72", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:9 | | | | Reserved | +| 8 | rw0c | 0x0 | EN_72 | For DIO_PAD2 | +| 7 | rw0c | 0x0 | EN_71 | For DIO_PAD2 | +| 6 | rw0c | 0x0 | EN_70 | For DIO_PAD2 | +| 5 | rw0c | 0x0 | EN_69 | For DIO_PAD2 | +| 4 | rw0c | 0x0 | EN_68 | For DIO_PAD2 | +| 3 | rw0c | 0x0 | EN_67 | For DIO_PAD2 | +| 2 | rw0c | 0x0 | EN_66 | For DIO_PAD2 | +| 1 | rw0c | 0x0 | EN_65 | For DIO_PAD2 | +| 0 | rw0c | 0x0 | EN_64 | For DIO_PAD2 | + +## DIO_PAD_SLEEP_REGWEN +Register write enable for DIO sleep value configuration. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:------------------------|:---------| +| DIO_PAD_SLEEP_REGWEN_0 | 0x3cc | +| DIO_PAD_SLEEP_REGWEN_1 | 0x3d0 | +| DIO_PAD_SLEEP_REGWEN_2 | 0x3d4 | +| DIO_PAD_SLEEP_REGWEN_3 | 0x3d8 | +| DIO_PAD_SLEEP_REGWEN_4 | 0x3dc | +| DIO_PAD_SLEEP_REGWEN_5 | 0x3e0 | +| DIO_PAD_SLEEP_REGWEN_6 | 0x3e4 | +| DIO_PAD_SLEEP_REGWEN_7 | 0x3e8 | +| DIO_PAD_SLEEP_REGWEN_8 | 0x3ec | +| DIO_PAD_SLEEP_REGWEN_9 | 0x3f0 | +| DIO_PAD_SLEEP_REGWEN_10 | 0x3f4 | +| DIO_PAD_SLEEP_REGWEN_11 | 0x3f8 | +| DIO_PAD_SLEEP_REGWEN_12 | 0x3fc | +| DIO_PAD_SLEEP_REGWEN_13 | 0x400 | +| DIO_PAD_SLEEP_REGWEN_14 | 0x404 | +| DIO_PAD_SLEEP_REGWEN_15 | 0x408 | +| DIO_PAD_SLEEP_REGWEN_16 | 0x40c | +| DIO_PAD_SLEEP_REGWEN_17 | 0x410 | +| DIO_PAD_SLEEP_REGWEN_18 | 0x414 | +| DIO_PAD_SLEEP_REGWEN_19 | 0x418 | +| DIO_PAD_SLEEP_REGWEN_20 | 0x41c | +| DIO_PAD_SLEEP_REGWEN_21 | 0x420 | +| DIO_PAD_SLEEP_REGWEN_22 | 0x424 | +| DIO_PAD_SLEEP_REGWEN_23 | 0x428 | +| DIO_PAD_SLEEP_REGWEN_24 | 0x42c | +| DIO_PAD_SLEEP_REGWEN_25 | 0x430 | +| DIO_PAD_SLEEP_REGWEN_26 | 0x434 | +| DIO_PAD_SLEEP_REGWEN_27 | 0x438 | +| DIO_PAD_SLEEP_REGWEN_28 | 0x43c | +| DIO_PAD_SLEEP_REGWEN_29 | 0x440 | +| DIO_PAD_SLEEP_REGWEN_30 | 0x444 | +| DIO_PAD_SLEEP_REGWEN_31 | 0x448 | +| DIO_PAD_SLEEP_REGWEN_32 | 0x44c | +| DIO_PAD_SLEEP_REGWEN_33 | 0x450 | +| DIO_PAD_SLEEP_REGWEN_34 | 0x454 | +| DIO_PAD_SLEEP_REGWEN_35 | 0x458 | +| DIO_PAD_SLEEP_REGWEN_36 | 0x45c | +| DIO_PAD_SLEEP_REGWEN_37 | 0x460 | +| DIO_PAD_SLEEP_REGWEN_38 | 0x464 | +| DIO_PAD_SLEEP_REGWEN_39 | 0x468 | +| DIO_PAD_SLEEP_REGWEN_40 | 0x46c | +| DIO_PAD_SLEEP_REGWEN_41 | 0x470 | +| DIO_PAD_SLEEP_REGWEN_42 | 0x474 | +| DIO_PAD_SLEEP_REGWEN_43 | 0x478 | +| DIO_PAD_SLEEP_REGWEN_44 | 0x47c | +| DIO_PAD_SLEEP_REGWEN_45 | 0x480 | +| DIO_PAD_SLEEP_REGWEN_46 | 0x484 | +| DIO_PAD_SLEEP_REGWEN_47 | 0x488 | +| DIO_PAD_SLEEP_REGWEN_48 | 0x48c | +| DIO_PAD_SLEEP_REGWEN_49 | 0x490 | +| DIO_PAD_SLEEP_REGWEN_50 | 0x494 | +| DIO_PAD_SLEEP_REGWEN_51 | 0x498 | +| DIO_PAD_SLEEP_REGWEN_52 | 0x49c | +| DIO_PAD_SLEEP_REGWEN_53 | 0x4a0 | +| DIO_PAD_SLEEP_REGWEN_54 | 0x4a4 | +| DIO_PAD_SLEEP_REGWEN_55 | 0x4a8 | +| DIO_PAD_SLEEP_REGWEN_56 | 0x4ac | +| DIO_PAD_SLEEP_REGWEN_57 | 0x4b0 | +| DIO_PAD_SLEEP_REGWEN_58 | 0x4b4 | +| DIO_PAD_SLEEP_REGWEN_59 | 0x4b8 | +| DIO_PAD_SLEEP_REGWEN_60 | 0x4bc | +| DIO_PAD_SLEEP_REGWEN_61 | 0x4c0 | +| DIO_PAD_SLEEP_REGWEN_62 | 0x4c4 | +| DIO_PAD_SLEEP_REGWEN_63 | 0x4c8 | +| DIO_PAD_SLEEP_REGWEN_64 | 0x4cc | +| DIO_PAD_SLEEP_REGWEN_65 | 0x4d0 | +| DIO_PAD_SLEEP_REGWEN_66 | 0x4d4 | +| DIO_PAD_SLEEP_REGWEN_67 | 0x4d8 | +| DIO_PAD_SLEEP_REGWEN_68 | 0x4dc | +| DIO_PAD_SLEEP_REGWEN_69 | 0x4e0 | +| DIO_PAD_SLEEP_REGWEN_70 | 0x4e4 | +| DIO_PAD_SLEEP_REGWEN_71 | 0x4e8 | +| DIO_PAD_SLEEP_REGWEN_72 | 0x4ec | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding [`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode) is not writable anymore. | + +## DIO_PAD_SLEEP_EN +Enables the sleep mode of the corresponding dedicated pad. +- Reset default: `0x0` +- Reset mask: `0x1` +- Register enable: [`DIO_PAD_SLEEP_REGWEN`](#dio_pad_sleep_regwen) + +### Instances + +| Name | Offset | +|:--------------------|:---------| +| DIO_PAD_SLEEP_EN_0 | 0x4f0 | +| DIO_PAD_SLEEP_EN_1 | 0x4f4 | +| DIO_PAD_SLEEP_EN_2 | 0x4f8 | +| DIO_PAD_SLEEP_EN_3 | 0x4fc | +| DIO_PAD_SLEEP_EN_4 | 0x500 | +| DIO_PAD_SLEEP_EN_5 | 0x504 | +| DIO_PAD_SLEEP_EN_6 | 0x508 | +| DIO_PAD_SLEEP_EN_7 | 0x50c | +| DIO_PAD_SLEEP_EN_8 | 0x510 | +| DIO_PAD_SLEEP_EN_9 | 0x514 | +| DIO_PAD_SLEEP_EN_10 | 0x518 | +| DIO_PAD_SLEEP_EN_11 | 0x51c | +| DIO_PAD_SLEEP_EN_12 | 0x520 | +| DIO_PAD_SLEEP_EN_13 | 0x524 | +| DIO_PAD_SLEEP_EN_14 | 0x528 | +| DIO_PAD_SLEEP_EN_15 | 0x52c | +| DIO_PAD_SLEEP_EN_16 | 0x530 | +| DIO_PAD_SLEEP_EN_17 | 0x534 | +| DIO_PAD_SLEEP_EN_18 | 0x538 | +| DIO_PAD_SLEEP_EN_19 | 0x53c | +| DIO_PAD_SLEEP_EN_20 | 0x540 | +| DIO_PAD_SLEEP_EN_21 | 0x544 | +| DIO_PAD_SLEEP_EN_22 | 0x548 | +| DIO_PAD_SLEEP_EN_23 | 0x54c | +| DIO_PAD_SLEEP_EN_24 | 0x550 | +| DIO_PAD_SLEEP_EN_25 | 0x554 | +| DIO_PAD_SLEEP_EN_26 | 0x558 | +| DIO_PAD_SLEEP_EN_27 | 0x55c | +| DIO_PAD_SLEEP_EN_28 | 0x560 | +| DIO_PAD_SLEEP_EN_29 | 0x564 | +| DIO_PAD_SLEEP_EN_30 | 0x568 | +| DIO_PAD_SLEEP_EN_31 | 0x56c | +| DIO_PAD_SLEEP_EN_32 | 0x570 | +| DIO_PAD_SLEEP_EN_33 | 0x574 | +| DIO_PAD_SLEEP_EN_34 | 0x578 | +| DIO_PAD_SLEEP_EN_35 | 0x57c | +| DIO_PAD_SLEEP_EN_36 | 0x580 | +| DIO_PAD_SLEEP_EN_37 | 0x584 | +| DIO_PAD_SLEEP_EN_38 | 0x588 | +| DIO_PAD_SLEEP_EN_39 | 0x58c | +| DIO_PAD_SLEEP_EN_40 | 0x590 | +| DIO_PAD_SLEEP_EN_41 | 0x594 | +| DIO_PAD_SLEEP_EN_42 | 0x598 | +| DIO_PAD_SLEEP_EN_43 | 0x59c | +| DIO_PAD_SLEEP_EN_44 | 0x5a0 | +| DIO_PAD_SLEEP_EN_45 | 0x5a4 | +| DIO_PAD_SLEEP_EN_46 | 0x5a8 | +| DIO_PAD_SLEEP_EN_47 | 0x5ac | +| DIO_PAD_SLEEP_EN_48 | 0x5b0 | +| DIO_PAD_SLEEP_EN_49 | 0x5b4 | +| DIO_PAD_SLEEP_EN_50 | 0x5b8 | +| DIO_PAD_SLEEP_EN_51 | 0x5bc | +| DIO_PAD_SLEEP_EN_52 | 0x5c0 | +| DIO_PAD_SLEEP_EN_53 | 0x5c4 | +| DIO_PAD_SLEEP_EN_54 | 0x5c8 | +| DIO_PAD_SLEEP_EN_55 | 0x5cc | +| DIO_PAD_SLEEP_EN_56 | 0x5d0 | +| DIO_PAD_SLEEP_EN_57 | 0x5d4 | +| DIO_PAD_SLEEP_EN_58 | 0x5d8 | +| DIO_PAD_SLEEP_EN_59 | 0x5dc | +| DIO_PAD_SLEEP_EN_60 | 0x5e0 | +| DIO_PAD_SLEEP_EN_61 | 0x5e4 | +| DIO_PAD_SLEEP_EN_62 | 0x5e8 | +| DIO_PAD_SLEEP_EN_63 | 0x5ec | +| DIO_PAD_SLEEP_EN_64 | 0x5f0 | +| DIO_PAD_SLEEP_EN_65 | 0x5f4 | +| DIO_PAD_SLEEP_EN_66 | 0x5f8 | +| DIO_PAD_SLEEP_EN_67 | 0x5fc | +| DIO_PAD_SLEEP_EN_68 | 0x600 | +| DIO_PAD_SLEEP_EN_69 | 0x604 | +| DIO_PAD_SLEEP_EN_70 | 0x608 | +| DIO_PAD_SLEEP_EN_71 | 0x60c | +| DIO_PAD_SLEEP_EN_72 | 0x610 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------| +| 31:1 | | | Reserved | +| 0 | rw | 0x0 | [EN](#dio_pad_sleep_en--en) | + +### DIO_PAD_SLEEP_EN . EN +Deep sleep mode enable. +If this bit is set to 1 the corresponding pad will enable the sleep behavior +specified in [`DIO_PAD_SLEEP_MODE`](#dio_pad_sleep_mode) upon deep sleep entry, and the corresponding bit +in [`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) will be set to 1. +The pad remains in deep sleep mode until the corresponding bit in +[`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) is cleared by SW. +Note that if an always on peripheral is connected to a specific DIO pad, +the corresponding [`DIO_PAD_SLEEP_EN`](#dio_pad_sleep_en) bit should be set to 0. + +## DIO_PAD_SLEEP_MODE +Defines sleep behavior of the corresponding dedicated pad. +- Reset default: `0x2` +- Reset mask: `0x3` +- Register enable: [`DIO_PAD_SLEEP_REGWEN`](#dio_pad_sleep_regwen) + +### Instances + +| Name | Offset | +|:----------------------|:---------| +| DIO_PAD_SLEEP_MODE_0 | 0x614 | +| DIO_PAD_SLEEP_MODE_1 | 0x618 | +| DIO_PAD_SLEEP_MODE_2 | 0x61c | +| DIO_PAD_SLEEP_MODE_3 | 0x620 | +| DIO_PAD_SLEEP_MODE_4 | 0x624 | +| DIO_PAD_SLEEP_MODE_5 | 0x628 | +| DIO_PAD_SLEEP_MODE_6 | 0x62c | +| DIO_PAD_SLEEP_MODE_7 | 0x630 | +| DIO_PAD_SLEEP_MODE_8 | 0x634 | +| DIO_PAD_SLEEP_MODE_9 | 0x638 | +| DIO_PAD_SLEEP_MODE_10 | 0x63c | +| DIO_PAD_SLEEP_MODE_11 | 0x640 | +| DIO_PAD_SLEEP_MODE_12 | 0x644 | +| DIO_PAD_SLEEP_MODE_13 | 0x648 | +| DIO_PAD_SLEEP_MODE_14 | 0x64c | +| DIO_PAD_SLEEP_MODE_15 | 0x650 | +| DIO_PAD_SLEEP_MODE_16 | 0x654 | +| DIO_PAD_SLEEP_MODE_17 | 0x658 | +| DIO_PAD_SLEEP_MODE_18 | 0x65c | +| DIO_PAD_SLEEP_MODE_19 | 0x660 | +| DIO_PAD_SLEEP_MODE_20 | 0x664 | +| DIO_PAD_SLEEP_MODE_21 | 0x668 | +| DIO_PAD_SLEEP_MODE_22 | 0x66c | +| DIO_PAD_SLEEP_MODE_23 | 0x670 | +| DIO_PAD_SLEEP_MODE_24 | 0x674 | +| DIO_PAD_SLEEP_MODE_25 | 0x678 | +| DIO_PAD_SLEEP_MODE_26 | 0x67c | +| DIO_PAD_SLEEP_MODE_27 | 0x680 | +| DIO_PAD_SLEEP_MODE_28 | 0x684 | +| DIO_PAD_SLEEP_MODE_29 | 0x688 | +| DIO_PAD_SLEEP_MODE_30 | 0x68c | +| DIO_PAD_SLEEP_MODE_31 | 0x690 | +| DIO_PAD_SLEEP_MODE_32 | 0x694 | +| DIO_PAD_SLEEP_MODE_33 | 0x698 | +| DIO_PAD_SLEEP_MODE_34 | 0x69c | +| DIO_PAD_SLEEP_MODE_35 | 0x6a0 | +| DIO_PAD_SLEEP_MODE_36 | 0x6a4 | +| DIO_PAD_SLEEP_MODE_37 | 0x6a8 | +| DIO_PAD_SLEEP_MODE_38 | 0x6ac | +| DIO_PAD_SLEEP_MODE_39 | 0x6b0 | +| DIO_PAD_SLEEP_MODE_40 | 0x6b4 | +| DIO_PAD_SLEEP_MODE_41 | 0x6b8 | +| DIO_PAD_SLEEP_MODE_42 | 0x6bc | +| DIO_PAD_SLEEP_MODE_43 | 0x6c0 | +| DIO_PAD_SLEEP_MODE_44 | 0x6c4 | +| DIO_PAD_SLEEP_MODE_45 | 0x6c8 | +| DIO_PAD_SLEEP_MODE_46 | 0x6cc | +| DIO_PAD_SLEEP_MODE_47 | 0x6d0 | +| DIO_PAD_SLEEP_MODE_48 | 0x6d4 | +| DIO_PAD_SLEEP_MODE_49 | 0x6d8 | +| DIO_PAD_SLEEP_MODE_50 | 0x6dc | +| DIO_PAD_SLEEP_MODE_51 | 0x6e0 | +| DIO_PAD_SLEEP_MODE_52 | 0x6e4 | +| DIO_PAD_SLEEP_MODE_53 | 0x6e8 | +| DIO_PAD_SLEEP_MODE_54 | 0x6ec | +| DIO_PAD_SLEEP_MODE_55 | 0x6f0 | +| DIO_PAD_SLEEP_MODE_56 | 0x6f4 | +| DIO_PAD_SLEEP_MODE_57 | 0x6f8 | +| DIO_PAD_SLEEP_MODE_58 | 0x6fc | +| DIO_PAD_SLEEP_MODE_59 | 0x700 | +| DIO_PAD_SLEEP_MODE_60 | 0x704 | +| DIO_PAD_SLEEP_MODE_61 | 0x708 | +| DIO_PAD_SLEEP_MODE_62 | 0x70c | +| DIO_PAD_SLEEP_MODE_63 | 0x710 | +| DIO_PAD_SLEEP_MODE_64 | 0x714 | +| DIO_PAD_SLEEP_MODE_65 | 0x718 | +| DIO_PAD_SLEEP_MODE_66 | 0x71c | +| DIO_PAD_SLEEP_MODE_67 | 0x720 | +| DIO_PAD_SLEEP_MODE_68 | 0x724 | +| DIO_PAD_SLEEP_MODE_69 | 0x728 | +| DIO_PAD_SLEEP_MODE_70 | 0x72c | +| DIO_PAD_SLEEP_MODE_71 | 0x730 | +| DIO_PAD_SLEEP_MODE_72 | 0x734 | + + +### Fields + +```wavejson +{"reg": [{"name": "OUT", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:--------------------------------| +| 31:2 | | | Reserved | +| 1:0 | rw | 0x2 | [OUT](#dio_pad_sleep_mode--out) | + +### DIO_PAD_SLEEP_MODE . OUT +Value to drive in deep sleep. + +| Value | Name | Description | +|:--------|:---------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | Tie-Low | The pad is driven actively to zero in deep sleep mode. | +| 0x1 | Tie-High | The pad is driven actively to one in deep sleep mode. | +| 0x2 | High-Z | The pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in [`DIO_PAD_ATTR.`](#dio_pad_attr) | +| 0x3 | Keep | Keep last driven value (including high-Z). | + + +## WKUP_DETECTOR_REGWEN +Register write enable for wakeup detectors. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| WKUP_DETECTOR_REGWEN_0 | 0x738 | +| WKUP_DETECTOR_REGWEN_1 | 0x73c | +| WKUP_DETECTOR_REGWEN_2 | 0x740 | +| WKUP_DETECTOR_REGWEN_3 | 0x744 | +| WKUP_DETECTOR_REGWEN_4 | 0x748 | +| WKUP_DETECTOR_REGWEN_5 | 0x74c | +| WKUP_DETECTOR_REGWEN_6 | 0x750 | +| WKUP_DETECTOR_REGWEN_7 | 0x754 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable bit. If this is cleared to 0, the corresponding WKUP_DETECTOR configuration is not writable anymore. | + +## WKUP_DETECTOR_EN +Enables for the wakeup detectors. +Note that these registers are synced to the always-on clock. +The first write access always completes immediately. +However, read/write accesses following a write will block until that write has completed. +- Reset default: `0x0` +- Reset mask: `0x1` +- Register enable: [`WKUP_DETECTOR_REGWEN`](#wkup_detector_regwen) + +### Instances + +| Name | Offset | +|:-------------------|:---------| +| WKUP_DETECTOR_EN_0 | 0x758 | +| WKUP_DETECTOR_EN_1 | 0x75c | +| WKUP_DETECTOR_EN_2 | 0x760 | +| WKUP_DETECTOR_EN_3 | 0x764 | +| WKUP_DETECTOR_EN_4 | 0x768 | +| WKUP_DETECTOR_EN_5 | 0x76c | +| WKUP_DETECTOR_EN_6 | 0x770 | +| WKUP_DETECTOR_EN_7 | 0x774 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | EN | Setting this bit activates the corresponding wakeup detector. The behavior is as specified in [`WKUP_DETECTOR`](#wkup_detector), [`WKUP_DETECTOR_CNT_TH`](#wkup_detector_cnt_th) and [`WKUP_DETECTOR_PADSEL.`](#wkup_detector_padsel) | + +## WKUP_DETECTOR +Configuration of wakeup condition detectors. +Note that these registers are synced to the always-on clock. +The first write access always completes immediately. +However, read/write accesses following a write will block until that write has completed. + +Note that the wkup detector should be disabled by setting [`WKUP_DETECTOR_EN_0`](#wkup_detector_en_0) before changing the detection mode. +The reason for that is that the pulse width counter is NOT cleared upon a mode change while the detector is enabled. +- Reset default: `0x0` +- Reset mask: `0x1f` +- Register enable: [`WKUP_DETECTOR_REGWEN`](#wkup_detector_regwen) + +### Instances + +| Name | Offset | +|:----------------|:---------| +| WKUP_DETECTOR_0 | 0x778 | +| WKUP_DETECTOR_1 | 0x77c | +| WKUP_DETECTOR_2 | 0x780 | +| WKUP_DETECTOR_3 | 0x784 | +| WKUP_DETECTOR_4 | 0x788 | +| WKUP_DETECTOR_5 | 0x78c | +| WKUP_DETECTOR_6 | 0x790 | +| WKUP_DETECTOR_7 | 0x794 | + + +### Fields + +```wavejson +{"reg": [{"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "FILTER", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MIODIO", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:---------------------------------| +| 31:5 | | | Reserved | +| 4 | rw | 0x0 | [MIODIO](#wkup_detector--miodio) | +| 3 | rw | 0x0 | [FILTER](#wkup_detector--filter) | +| 2:0 | rw | 0x0 | [MODE](#wkup_detector--mode) | + +### WKUP_DETECTOR . MIODIO +0: select index [`WKUP_DETECTOR_PADSEL`](#wkup_detector_padsel) from MIO pads, +1: select index [`WKUP_DETECTOR_PADSEL`](#wkup_detector_padsel) from DIO pads. + +### WKUP_DETECTOR . FILTER +0: signal filter disabled, 1: signal filter enabled. the signal must +be stable for 4 always-on clock cycles before the value is being forwarded. +can be used for debouncing. + +### WKUP_DETECTOR . MODE +Wakeup detection mode. Out of range values default to Posedge. + +| Value | Name | Description | +|:--------|:----------|:------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 0x0 | Posedge | Trigger a wakeup request when observing a positive edge. | +| 0x1 | Negedge | Trigger a wakeup request when observing a negative edge. | +| 0x2 | Edge | Trigger a wakeup request when observing an edge in any direction. | +| 0x3 | TimedHigh | Trigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in [`WKUP_DETECTOR_CNT_TH.`](#wkup_detector_cnt_th) | +| 0x4 | TimedLow | Trigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in [`WKUP_DETECTOR_CNT_TH.`](#wkup_detector_cnt_th) | + +Other values are reserved. + +## WKUP_DETECTOR_CNT_TH +Counter thresholds for wakeup condition detectors. +Note that these registers are synced to the always-on clock. +The first write access always completes immediately. +However, read/write accesses following a write will block until that write has completed. +- Reset default: `0x0` +- Reset mask: `0xff` +- Register enable: [`WKUP_DETECTOR_REGWEN`](#wkup_detector_regwen) + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| WKUP_DETECTOR_CNT_TH_0 | 0x798 | +| WKUP_DETECTOR_CNT_TH_1 | 0x79c | +| WKUP_DETECTOR_CNT_TH_2 | 0x7a0 | +| WKUP_DETECTOR_CNT_TH_3 | 0x7a4 | +| WKUP_DETECTOR_CNT_TH_4 | 0x7a8 | +| WKUP_DETECTOR_CNT_TH_5 | 0x7ac | +| WKUP_DETECTOR_CNT_TH_6 | 0x7b0 | +| WKUP_DETECTOR_CNT_TH_7 | 0x7b4 | + + +### Fields + +```wavejson +{"reg": [{"name": "TH", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:8 | | | | Reserved | +| 7:0 | rw | 0x0 | TH | Counter threshold for TimedLow and TimedHigh wakeup detector modes (see [`WKUP_DETECTOR`](#wkup_detector)). The threshold is in terms of always-on clock cycles. | + +## WKUP_DETECTOR_PADSEL +Pad selects for pad wakeup condition detectors. +This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix. +- Reset default: `0x0` +- Reset mask: `0x7f` +- Register enable: [`WKUP_DETECTOR_REGWEN`](#wkup_detector_regwen) + +### Instances + +| Name | Offset | +|:-----------------------|:---------| +| WKUP_DETECTOR_PADSEL_0 | 0x7b8 | +| WKUP_DETECTOR_PADSEL_1 | 0x7bc | +| WKUP_DETECTOR_PADSEL_2 | 0x7c0 | +| WKUP_DETECTOR_PADSEL_3 | 0x7c4 | +| WKUP_DETECTOR_PADSEL_4 | 0x7c8 | +| WKUP_DETECTOR_PADSEL_5 | 0x7cc | +| WKUP_DETECTOR_PADSEL_6 | 0x7d0 | +| WKUP_DETECTOR_PADSEL_7 | 0x7d4 | + + +### Fields + +```wavejson +{"reg": [{"name": "SEL", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------------| +| 31:7 | | | Reserved | +| 6:0 | rw | 0x0 | [SEL](#wkup_detector_padsel--sel) | + +### WKUP_DETECTOR_PADSEL . SEL +Selects a specific MIO or DIO pad (depending on [`WKUP_DETECTOR`](#wkup_detector) configuration). +In case of MIO, the pad select index is the same as used for [`MIO_PERIPH_INSEL`](#mio_periph_insel), meaning that index +0 and 1 just select constants 0 and 1, and the MIO pads live at indices >= 2. In case of DIO pads, +the pad select index corresponds 1:1 to the DIO pad to be selected. + +## WKUP_CAUSE +Cause registers for wakeup detectors. +Note that these registers are synced to the always-on clock. +The first write access always completes immediately. +However, read/write accesses following a write will block until that write has completed. +- Offset: `0x7d8` +- Reset default: `0x0` +- Reset mask: `0xff` + +### Fields + +```wavejson +{"reg": [{"name": "CAUSE_0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_1", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_2", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_3", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_4", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_5", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_6", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_7", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:----------------------------------------------------------------------------------------| +| 31:8 | | | | Reserved | +| 7 | rw0c | 0x0 | CAUSE_7 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 6 | rw0c | 0x0 | CAUSE_6 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 5 | rw0c | 0x0 | CAUSE_5 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 4 | rw0c | 0x0 | CAUSE_4 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 3 | rw0c | 0x0 | CAUSE_3 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 2 | rw0c | 0x0 | CAUSE_2 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 1 | rw0c | 0x0 | CAUSE_1 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | +| 0 | rw0c | 0x0 | CAUSE_0 | Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/targets.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/targets.md new file mode 100644 index 00000000000..3e1c97c1346 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/targets.md @@ -0,0 +1,10 @@ +# Darjeeling_no_ibex Pinout and Pinmux Connectivity Tables + +| Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables | +|:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:---------------------------------:| +| ASIC | 1 | 12 | 73 | 7 | 92 | [Pinout Table](./pinout_asic.md) | +| CW310 | 1 | 12 | 73 | 10 | 95 | [Pinout Table](./pinout_cw310.md) | diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/theory_of_operation.md b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/theory_of_operation.md new file mode 100644 index 00000000000..fa1200779d0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/doc/theory_of_operation.md @@ -0,0 +1,215 @@ +# Theory of Operation + +## Block Diagram and Overview + +The `pinmux` peripheral is a programmable module designed to wire arbitrary peripheral inputs and outputs to arbitrary multiplexable chip bidirectional pins. +It gives much flexibility at the top level of the device, allowing most data pins to be flexibly wired and controlled by many peripherals. +Even though the `pinmux` is referred to as one IP, it is logically split into two modules that are instantiated on the top-level and the chip-level, respectively, as can be seen in the block diagram below. +The top-level module `pinmux` contains the CSRs accessible via the TL-UL interface, the main muxing matrix, retention registers, a set of programmable wakeup detectors, and the HW strap sampling and TAP / JTAG muxing logic. +The chip-level module `padring` instantiates the bidirectional pads and connects the physical pad attributes. + +![Pinmux Block Diagram](../doc/pinmux_overview_block_diagram.svg) + +### MIO and DIO Signal Categories + +The `pinmux` supports two different IO signal categories: +Muxed IO (MIO) signals that are routed through the `pinmux` matrix, and dedicated IO (DIO) signals that bypass the `pinmux` matrix. +This distinction is useful for accommodating IO signals that are timing critical or that must have a fixed IO mapping for another reason. +Note that although DIO signals are not routed through the `pinmux` matrix, they are still connected to the retention logic and the wakeup detectors (see next section below). + +The number of available peripheral IOs, pads, and their assignment to the MIO / DIO categories is done at design time as part of the top-level configuration. +This configurability is achieved by representing inputs / outputs as packed arrays, in combination with the SystemVerilog parameters `NPeriphIn`, `NPeriphOut`, `NMioPads` and `NDioPads`. +Note however that the register file is also affected by this configuration and needs to be regenerated for each design instance. + +It is assumed that all available pins that the `pinmux` connects to are bidirectional, controlled by logic within this module. +By default, all muxed peripheral inputs are tied to zero. +Further, all output enables are set to zero, which essentially causes all pads to be in high-Z state after reset. +In addition to wiring programmability, each muxed peripheral input can be set constantly to 0 or 1, and each muxed chip output can be set constantly to 0, 1 or high-Z. + +See the [muxing matrix](#muxing-matrix) section for more details about the mux implementation. + +### Retention and Wakeup Features + +The retention logic allows SW to specify a certain behavior during sleep for each muxed and dedicated output. +Legal behaviors are tie low, tie high, high-Z, keeping the previous state, or driving the current value (useful for peripherals that are always on). + +The wakeup detectors can detect patterns such as rising / falling edges and pulses of a certain width up to 255 AON clock cycles. +Each wakeup detector can listen on any one of the MIO / DIO signals that are routed through the `pinmux`, and if a pattern is detected, the power manager is informed of that event via a wakeup request. + +The `pinmux` module itself is in the always-on (AON) power domain, and as such does not loose configuration state when a sleep power cycle is performed. +However, only the wakeup detector logic will be actively clocked during sleep in order to save power. + +See the [retention logic](#retention-logic) and [wakeup detectors](#wakeup-detectors) sections for more details about the mux implementation. + +### USB Wakeup Detection Module + +The USB device in the Earlgrey top-level is not in the AON power domain and hence the associated wakeup detection module is placed inside the pinmux IP in that top-level. +The USB wakeup module is not connected to any pinmux infrastructure or CSRs except for the `usb_wkup_req` signal going to the power manager. +See [USB device documentation](../../../../ip/usbdev/README.md) for more information on the USB wakeup mechanism. + +### Test and Debug Access + +The hardware strap sampling and TAP isolation logic provides test and debug access to the chip during specific life cycle states. +This mechanism is explained in more detail in the [strap sampling and TAP isolation](#strap-sampling-and-tap-isolation) section. + +### Pad Attributes + +Additional pad-specific features such as inversion, pull-up, pull-down, virtual open-drain, drive-strength and input/output inversion etc. can be exercise via the pad attribute CSRs. +The `pinmux` module supports a comprehensive set of such pad attributes, but it is permissible that some of them may not be supported by the underlying pad implementation. +For example, certain ASIC libraries may not provide open-drain outputs, and FPGAs typically do not allow all of these attributes to be programmed dynamically at runtime. +See the [generic pad wrapper](#generic-pad-wrapper) section below for more details. +Note that static pad attributes for FPGAs are currently not covered in this specification. + +## Muxing Matrix + +The diagram below shows connectivity between four arbitrary chip pins, named `MIO0` .. `MIO3`, and several muxed peripheral inputs and outputs. +This shows the connectivity available in all directions, as well as the control registers described later in this document. +Two example peripherals (`uart` and `spidev`) are attached to the `pinmux` in this example, one with one input and one output, the other with three inputs and one output. +The diagram also shows the `padring` module which instantiates the bidirectional chip pads with output enable control. + +![Pinmux Block Diagram](../doc/pinmux_muxing_matrix.svg) + +Note that apart from selecting a specific input pad, the `periph_insel[*]` signals can also be used to tie the peripheral input to 0 or 1. +Likewise, the output select signals `mio_outsel[*]` can also be used to constantly drive an output pin to 0/1 or to put it into high-Z state (default). +The output enable and the associated data signal (i.e. `periph_to_mio` and `periph_to_mio_oe`) are indexed with the same select signal to allow the peripheral hardware to determine the pad direction instead of demoting that control to SW. + +## Retention Logic + +As illustrated in the picture above, all muxing matrix and DIO outputs are routed through the retention logic, which essentially consists of a set of multiplexors and two retention registers per output (one register is for the output data and one for the output enable). +This multiplexor can be configured to be automatically activated upon sleep entry in order to either drive the output low, high, high-Z or to the last seen value (keep). +If no sleep behavior is specified, the retention logic will continue to drive out the value coming from the peripheral side, which can be useful for peripherals that reside in the AON domain. + +The sleep behavior of all outputs is activated in parallel via a trigger signal asserted by the power manager. +Once activated, it is the task of SW to disable the sleep behavior for each individual pin when waking up from sleep. +This ensures that the output values remain stable until the system and its peripherals have been re-initialized. + +## Wakeup Detectors + +The `pinmux` contains eight programmable wakeup detector modules that can listen on any of the MIO or DIO pins. +Each detector contains a debounce filter and an 8bit counter running on the AON clock domain. +The detectors can be programmed via the [`WKUP_DETECTOR_0`](registers.md#wkup_detector) and [`WKUP_DETECTOR_CNT_TH_0`](registers.md#wkup_detector_cnt_th) registers to detect the following patterns: + +- rising edge +- falling edge +- rising or falling edge +- positive pulse up to 255 AON clock cycles in length +- negative pulse up to 255 AON clock cycles in length + +Note that for all patterns listed above, the input signal is sampled with the AON clock. +This means that the input signal needs to remain stable for at least one AON clock cycle after a level change for the detector to recognize the event (depending on the debounce filter configuration, the signal needs to remain stable for multiple clock cycles). + +If a pattern is detected, the wakeup detector will send a wakeup request to the power manager, and the cause bit corresponding to that detector will be set in the [`WKUP_CAUSE`](registers.md#wkup_cause) register. + +Note that the wkup detector should be disabled by setting [`WKUP_DETECTOR_EN_0`](registers.md#wkup_detector_en) before changing the detection mode. +The reason for that is that the pulse width counter is NOT cleared upon a mode change while the detector is enabled. + +## Strap Sampling and TAP Isolation + +The `pinmux` contains a set of dedicated HW "straps", which are essentially signals that are multiplexed onto fixed MIO pad locations. +Depending on the life cycle state, these straps are either continuously sampled, or latched right after POR. + +There are two groups of HW straps: +1. Three DFT straps that determine the DFT mode. + These bits are output via the `dft_strap_test_o` signal such that they can be routed to the tool-inserted DFT controller. +2. Two TAP selection straps for determining which TAP should be multiplexed onto the JTAG IOs. + +The conditions under which these two strap groups are sampled are listed in the tables below. +Note that the HW straps can be used just like regular GPIOs once they have been sampled. + +Strap Group \ Life Cycle State | TEST_UNLOCKED* | RMA | DEV | All Other States +--------------------------------|----------------|--------------|--------------|------------------ +DFT straps | Once at boot | Once at boot | - | - +TAP strap 0 | Continuously | Continuously | Once at boot | Once at boot +TAP strap 1 | Continuously | Continuously | Once at boot | - + +*Once at boot:* Sampled once after life cycle initialization (sampling event is initiated by pwrmgr). + +*Continuously:* Sampled continuously after life cycle initialization. + +The TAP muxing logic is further qualified by the life cycle state in order to isolate the TAPs in certain life cycle states. +The following table lists the TAP strap encoding and the life cycle states in which the associated TAPs can be selected and accessed. + +TAP strap 1 | TAP strap 0 | Life Cycle State | Selected TAP +------------|--------------|--------------------------|--------------- +0 | 0 | All states | - +0 | 1 | All states | Life Cycle +1 | 0 | TEST_UNLOCKED*, RMA, DEV | RISC-V +1 | 1 | TEST_UNLOCKED*, RMA | DFT + +Note that the tool-inserted DFT controller may assert the `dft_hold_tap_sel_i` during a test (e.g. boundary scan) in which case the `pinmux` will temporarily pause sampling of the TAP selection straps. + +It should be noted that the TAP straps are muxed with MIOs and that the pad attributes will take effect even in life cycles states that +continuously sample the straps. As a result, pad attributes can interfere or even disable tap selection entirely in those life cycle states. + +Also, it should be noted that the pad attributes of all JTAG IOs will be gated to all-zero temporarily, while the JTAG is enabled (this does not affect the values in the CSRs). +This is to ensure that any functional attributes like inversion or pull-ups / pull-downs do not interfere with the JTAG while it is in use. + +For more information about the life cycle states, see [Life Cycle Controller Specification](../../../../ip/lc_ctrl/README.md) and the [Life Cycle Definition Table](../../../../../doc/security/specs/device_life_cycle/README.md#manufacturing-states). + +### Non-debug Module Reset + +The only parts of the system that are not reset as part of a non-debug module (NDM) reset are in this strap sampling and TAP selection module, and in the `rv_dm`, power, reset and clock managers. +Hence, in order to keep a `rv_dm` JTAG debug session alive during an NDM reset, the `lc_hw_debug_en` state needs to be memorized. + +To that end, the TAP isolation logic in the pinmux samples the `lc_hw_debug_en` state when the strap sampling pulse is asserted by the power manager. +This pulse is asserted once during boot (and not after an NDM reset). + +Note that DFT TAP selection is not affected by this since the TAP selection logic always consumes the live value for `lc_dft_en`. +The TAP selection logic also invalidates the sampled `lc_hw_debug_en` whenever a life cycle transition is initiated or an escalation is triggered via `lc_escalate_en`. +This ensures that the sampled `lc_hw_debug_en` value does not survive a life cycle transition. + +Finally, note that there is secondary gating on the `rv_dm` and DFT TAPs that is always consuming live `lc_hw_debug_en` and `lc_dft_en` signals for added protection. + +See also [rv_dm documentation](../../../../ip/rv_dm/doc/theory_of_operation.md#non-debug-module-reset-support). + +## Generic Pad Wrapper + +
+ +
+ +The generic pad wrapper is intended to abstract away implementation differences between the target technologies by providing a generic interface that is compatible with the `padring` module. +It is the task of the RTL build flow to select the appropriate pad wrapper implementation. + +A specific implementation of a pad wrapper may choose to instantiate a technology primitive (as it is common in ASIC flows), or it may choose to model the functionality behaviorally such that it can be inferred by the technology mapping tool (e.g., in the case of an FPGA target). +It is permissible to omit the implementation of all IO attributes except input/output inversion. + +The generic pad wrapper must expose the following IOs and parameters, even if they are not connected internally. +In particular, the pad attribute struct `attr_i` must contain all fields listed below, even if not all attributes are supported (it is permissible to just leave them unconnected in the pad wrapper implementation). + +Parameter | Default | Description +---------------|------------|----------------------------------------------------- +`PadType` | `BidirStd` | Pad variant to be instantiated (technology-specific) +`ScanRole` | `NoScan` | Scan role, can be `NoScan`, `ScanIn` or `ScanOut` + +Note that `PadType` is a technology-specific parameter. +The generic pad wrapper only implements variant `BidirStd`, but for other target technologies, this parameter can be used to select among a variety of different pad flavors. + +The `ScanRole` parameter determines the behavior when scanmode is enabled. +Depending on whether a given pad acts as a scan input or output, certain pad attributes and functionalities need to be bypassed. +This parameter is typically only relevant for ASIC targets and therefore not modeled in the generic pad model. + +Also note that the pad wrapper may implement a "virtual" open-drain termination, where standard bidirectional pads are employed, but instead of driving the output high for a logic 1 the pad is put into tristate mode. + +Signal | Direction | Type | Description +---------------------|------------|-------------|----------------------------------------------- +`clk_scan_i` | `input` | `logic` | Scan clock of the pad +`scanmode_i` | `input` | `logic` | Scan mode enable of the pad +`pok_i` | `input` | `pad_pok_t` | Technology-specific power sequencing signals +`inout_io` | `inout` | `wire` | Bidirectional inout of the pad +`in_o` | `output` | `logic` | Input data signal +`in_raw_o` | `output` | `logic` | Un-inverted input data signal +`out_i` | `input` | `logic` | Output data signal +`oe_i` | `input` | `logic` | Output data enable +`attr_i[0]` | `input` | `logic` | Input/output inversion +`attr_i[1]` | `input` | `logic` | Virtual open-drain enable +`attr_i[2]` | `input` | `logic` | Pull enable +`attr_i[3]` | `input` | `logic` | Pull select (0: pull-down, 1: pull-up) +`attr_i[4]` | `input` | `logic` | Keeper enable +`attr_i[5]` | `input` | `logic` | Schmitt trigger enable +`attr_i[6]` | `input` | `logic` | Open drain enable +`attr_i[7]` | `input` | `logic` | Input disable (0: input enabled, 1: input disabled) +`attr_i[9:8]` | `input` | `logic` | Slew rate (0x0: slowest, 0x3: fastest) +`attr_i[13:10]` | `input` | `logic` | Drive strength (0x0: weakest, 0xf: strongest) + +Note that the corresponding pad attribute registers [`MIO_PAD_ATTR_0`](registers.md#mio_pad_attr) and [`DIO_PAD_ATTR_0`](registers.md#dio_pad_attr) have "writes-any-reads-legal" (WARL) behavior (see also [pad attributes](#pad-attributes)). diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_chip_expected_failure.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_chip_expected_failure.hjson new file mode 100644 index 00000000000..c6d4640f00f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_chip_expected_failure.hjson @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +{ + unreachable: + [ + pinmux_chip_tb.dut_asic.FpvSecCmRegWeOnehotCheck_A:precondition1 + pinmux_chip_tb.dut_asic.u_reg.u_prim_reg_we_check.u_prim_onehot_check.Onehot0Check_A:precondition1 + pinmux_chip_tb.dut_asic.u_reg.u_prim_reg_we_check.u_prim_onehot_check.gen_enable_check.gen_not_strict.EnableCheck_A:precondition1 + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core new file mode 100644 index 00000000000..b45bee92fc0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_chip_fpv.core @@ -0,0 +1,44 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_systems:pinmux_chip_fpv:0.1 +description: "pinmux FPV target with chip_earlgrey parameters" + +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:ip:tlul + - lowrisc:ip:jtag_pkg + - lowrisc:prim:mubi_pkg + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:darjeeling_no_ibex_ip:pinmux:0.1 + - lowrisc:fpv:csr_assert_gen + - lowrisc:darjeeling_no_ibex_fpv:pinmux_common_fpv:0.1 + - lowrisc:darjeeling_no_ibex_constants:top_pkg + - lowrisc:darjeeling_no_ibex_systems:scan_role_pkg + files: + - tb/pinmux_chip_tb.sv + file_type: systemVerilogSource + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../data/pinmux.hjson + +targets: + default: &default_target + default_tool: icarus + filesets: + - files_formal + generate: + - csr_assert_gen + toplevel: pinmux_chip_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_common_fpv.core b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_common_fpv.core new file mode 100644 index 00000000000..07ee28da389 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_common_fpv.core @@ -0,0 +1,28 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_fpv:pinmux_common_fpv:0.1 +description: "pinmux common FPV target" +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:ip:tlul + - lowrisc:darjeeling_no_ibex_ip:pinmux:0.1 + files: + - vip/pinmux_assert_fpv.sv + - tb/pinmux_bind_fpv.sv + file_type: systemVerilogSource + +targets: + default: &default_target + default_tool: icarus + filesets: + - files_formal + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_expected_failure.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_expected_failure.hjson new file mode 100644 index 00000000000..ccbda769beb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_expected_failure.hjson @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +{ + unreachable: + [ + pinmux_tb.dut.FpvSecCmRegWeOnehotCheck_A:precondition1 + pinmux_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.Onehot0Check_A:precondition1 + pinmux_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.gen_enable_check.gen_not_strict.EnableCheck_A:precondition1 + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_fpv.core b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_fpv.core new file mode 100644 index 00000000000..43b9d3fe5a3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/pinmux_fpv.core @@ -0,0 +1,38 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_fpv:pinmux_fpv:0.1 +description: "pinmux FPV target" +filesets: + files_formal: + depend: + - lowrisc:prim:all + - lowrisc:ip:tlul + - lowrisc:darjeeling_no_ibex_ip:pinmux:0.1 + - lowrisc:fpv:csr_assert_gen + - lowrisc:darjeeling_no_ibex_fpv:pinmux_common_fpv + files: + - tb/pinmux_tb.sv + file_type: systemVerilogSource + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../data/pinmux.hjson + +targets: + default: &default_target + default_tool: icarus + filesets: + - files_formal + generate: + - csr_assert_gen + toplevel: pinmux_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/tb/pinmux_bind_fpv.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/tb/pinmux_bind_fpv.sv new file mode 100644 index 00000000000..6667a58b320 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/tb/pinmux_bind_fpv.sv @@ -0,0 +1,60 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +module pinmux_bind_fpv; + + + bind pinmux pinmux_assert_fpv #( + .TargetCfg(TargetCfg), + .AlertAsyncOn(AlertAsyncOn), + .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn) + ) i_pinmux_assert_fpv ( + .clk_i, + .rst_ni, + .rst_sys_ni, + .scanmode_i, + .clk_aon_i, + .rst_aon_ni, + .pin_wkup_req_o, + .sleep_en_i, + .tl_i, + .tl_o, + .alert_rx_i, + .alert_tx_o, + .periph_to_mio_i, + .periph_to_mio_oe_i, + .mio_to_periph_o, + .periph_to_dio_i, + .periph_to_dio_oe_i, + .dio_to_periph_o, + .mio_attr_o, + .mio_out_o, + .mio_oe_o, + .mio_in_i, + .dio_attr_o, + .dio_out_o, + .dio_oe_o, + .dio_in_i + ); + + + bind pinmux tlul_assert #( + .EndpointType("Device") + ) i_tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o), + .* + ); + + bind pinmux pinmux_csr_assert_fpv i_pinmux_csr_assert_fpv ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule : pinmux_bind_fpv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/tb/pinmux_chip_tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/tb/pinmux_chip_tb.sv new file mode 100644 index 00000000000..02e5770918c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/tb/pinmux_chip_tb.sv @@ -0,0 +1,216 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for pinmux. +// Intended to be used with a formal tool. + +module pinmux_chip_tb + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; + import top_darjeeling_no_ibex_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit SecVolatileRawUnlockEn = 1 +) ( + input clk_i, + input rst_ni, + input rst_sys_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + input clk_aon_i, + input rst_aon_ni, + output logic pin_wkup_req_o, + input sleep_en_i, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + input prim_alert_pkg::alert_rx_t[NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t[NumAlerts-1:0] alert_tx_o, + input [NMioPeriphOut-1:0] periph_to_mio_i, + input [NMioPeriphOut-1:0] periph_to_mio_oe_i, + output logic[NMioPeriphIn-1:0] mio_to_periph_o, + input [NDioPads-1:0] periph_to_dio_i, + input [NDioPads-1:0] periph_to_dio_oe_i, + output logic[NDioPads-1:0] dio_to_periph_o, + output prim_pad_wrapper_pkg::pad_attr_t[NMioPads-1:0] mio_attr_o, + output logic[NMioPads-1:0] mio_out_o, + output logic[NMioPads-1:0] mio_oe_o, + input [NMioPads-1:0] mio_in_i, + output prim_pad_wrapper_pkg::pad_attr_t[NDioPads-1:0] dio_attr_o, + output logic[NDioPads-1:0] dio_out_o, + output logic[NDioPads-1:0] dio_oe_o, + input [NDioPads-1:0] dio_in_i +); + + import top_darjeeling_no_ibex_pkg::*; + + // Copied from chip_darjeeling_no_ibex_asic.sv + // TODO: find a better way to automatically generate this FPV testbench via topgen/ipgen. + localparam int Tap0PadIdx = 30; + localparam int Tap1PadIdx = 27; + localparam int Dft0PadIdx = 25; + localparam int Dft1PadIdx = 26; + localparam int TckPadIdx = 38; + localparam int TmsPadIdx = 35; + localparam int TrstNPadIdx = 39; + localparam int TdiPadIdx = 37; + localparam int TdoPadIdx = 36; + // DFT and Debug signal positions in the pinout. + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + // TODO: check whether there is a better way to pass these USB-specific params + usb_dp_idx: DioUsbdevUsbDp, + usb_dn_idx: DioUsbdevUsbDn, + usb_sense_idx: MioInUsbdevSense, + // Pad types for attribute WARL behavior + dio_pad_type: { + BidirStd, // DIO spi_host0_csb + BidirStd, // DIO spi_host0_sck + InputStd, // DIO spi_device_csb + InputStd, // DIO spi_device_sck + BidirOd, // DIO sysrst_ctrl_aon_flash_wp_l + BidirOd, // DIO sysrst_ctrl_aon_ec_rst_l + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO usbdev_usb_dn + BidirStd // DIO usbdev_usb_dp + }, + mio_pad_type: { + BidirOd, // MIO Pad 46 + BidirOd, // MIO Pad 45 + BidirOd, // MIO Pad 44 + BidirOd, // MIO Pad 43 + BidirStd, // MIO Pad 42 + BidirStd, // MIO Pad 41 + BidirStd, // MIO Pad 40 + BidirStd, // MIO Pad 39 + BidirStd, // MIO Pad 38 + BidirStd, // MIO Pad 37 + BidirStd, // MIO Pad 36 + BidirStd, // MIO Pad 35 + BidirOd, // MIO Pad 34 + BidirOd, // MIO Pad 33 + BidirOd, // MIO Pad 32 + BidirStd, // MIO Pad 31 + BidirStd, // MIO Pad 30 + BidirStd, // MIO Pad 29 + BidirStd, // MIO Pad 28 + BidirStd, // MIO Pad 27 + BidirStd, // MIO Pad 26 + BidirStd, // MIO Pad 25 + BidirStd, // MIO Pad 24 + BidirStd, // MIO Pad 23 + BidirStd, // MIO Pad 22 + BidirOd, // MIO Pad 21 + BidirOd, // MIO Pad 20 + BidirOd, // MIO Pad 19 + BidirOd, // MIO Pad 18 + BidirStd, // MIO Pad 17 + BidirStd, // MIO Pad 16 + BidirStd, // MIO Pad 15 + BidirStd, // MIO Pad 14 + BidirStd, // MIO Pad 13 + BidirStd, // MIO Pad 12 + BidirStd, // MIO Pad 11 + BidirStd, // MIO Pad 10 + BidirStd, // MIO Pad 9 + BidirOd, // MIO Pad 8 + BidirOd, // MIO Pad 7 + BidirOd, // MIO Pad 6 + BidirStd, // MIO Pad 5 + BidirStd, // MIO Pad 4 + BidirStd, // MIO Pad 3 + BidirStd, // MIO Pad 2 + BidirStd, // MIO Pad 1 + BidirStd // MIO Pad 0 + }, + dio_scan_role: { + scan_role_pkg::DioPadSpiHostCsLScanRole, // DIO spi_host0_csb + scan_role_pkg::DioPadSpiHostClkScanRole, // DIO spi_host0_sck + scan_role_pkg::DioPadSpiDevCsLScanRole, // DIO spi_device_csb + scan_role_pkg::DioPadSpiDevClkScanRole, // DIO spi_device_sck + scan_role_pkg::DioPadIor9ScanRole, // DIO sysrst_ctrl_aon_flash_wp_l + scan_role_pkg::DioPadIor8ScanRole, // DIO sysrst_ctrl_aon_ec_rst_l + scan_role_pkg::DioPadSpiDevD3ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD2ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD1ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD0ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiHostD3ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD2ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD1ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD0ScanRole, // DIO spi_host0_sd + NoScan, // DIO usbdev_usb_dn + NoScan // DIO usbdev_usb_dp + }, + mio_scan_role: { + scan_role_pkg::MioPadIor13ScanRole, + scan_role_pkg::MioPadIor12ScanRole, + scan_role_pkg::MioPadIor11ScanRole, + scan_role_pkg::MioPadIor10ScanRole, + scan_role_pkg::MioPadIor7ScanRole, + scan_role_pkg::MioPadIor6ScanRole, + scan_role_pkg::MioPadIor5ScanRole, + scan_role_pkg::MioPadIor4ScanRole, + scan_role_pkg::MioPadIor3ScanRole, + scan_role_pkg::MioPadIor2ScanRole, + scan_role_pkg::MioPadIor1ScanRole, + scan_role_pkg::MioPadIor0ScanRole, + scan_role_pkg::MioPadIoc12ScanRole, + scan_role_pkg::MioPadIoc11ScanRole, + scan_role_pkg::MioPadIoc10ScanRole, + scan_role_pkg::MioPadIoc9ScanRole, + scan_role_pkg::MioPadIoc8ScanRole, + scan_role_pkg::MioPadIoc7ScanRole, + scan_role_pkg::MioPadIoc6ScanRole, + scan_role_pkg::MioPadIoc5ScanRole, + scan_role_pkg::MioPadIoc4ScanRole, + scan_role_pkg::MioPadIoc3ScanRole, + scan_role_pkg::MioPadIoc2ScanRole, + scan_role_pkg::MioPadIoc1ScanRole, + scan_role_pkg::MioPadIoc0ScanRole, + scan_role_pkg::MioPadIob12ScanRole, + scan_role_pkg::MioPadIob11ScanRole, + scan_role_pkg::MioPadIob10ScanRole, + scan_role_pkg::MioPadIob9ScanRole, + scan_role_pkg::MioPadIob8ScanRole, + scan_role_pkg::MioPadIob7ScanRole, + scan_role_pkg::MioPadIob6ScanRole, + scan_role_pkg::MioPadIob5ScanRole, + scan_role_pkg::MioPadIob4ScanRole, + scan_role_pkg::MioPadIob3ScanRole, + scan_role_pkg::MioPadIob2ScanRole, + scan_role_pkg::MioPadIob1ScanRole, + scan_role_pkg::MioPadIob0ScanRole, + scan_role_pkg::MioPadIoa8ScanRole, + scan_role_pkg::MioPadIoa7ScanRole, + scan_role_pkg::MioPadIoa6ScanRole, + scan_role_pkg::MioPadIoa5ScanRole, + scan_role_pkg::MioPadIoa4ScanRole, + scan_role_pkg::MioPadIoa3ScanRole, + scan_role_pkg::MioPadIoa2ScanRole, + scan_role_pkg::MioPadIoa1ScanRole, + scan_role_pkg::MioPadIoa0ScanRole + } + }; + + pinmux #( + .TargetCfg(PinmuxTargetCfg), + .AlertAsyncOn(AlertAsyncOn), + .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn) + ) dut_asic (.*); + +endmodule : pinmux_chip_tb diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/tb/pinmux_tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/tb/pinmux_tb.sv new file mode 100644 index 00000000000..9e4ce306f14 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/tb/pinmux_tb.sv @@ -0,0 +1,82 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for pinmux. +// Intended to be used with a formal tool. + +module pinmux_tb + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; +#( + parameter int Tap0PadIdx = 0, + parameter int Tap1PadIdx = 1, + parameter int Dft0PadIdx = 2, + parameter int Dft1PadIdx = 3, + parameter int TckPadIdx = 4, + parameter int TmsPadIdx = 5, + parameter int TrstNPadIdx = 6, + parameter int TdiPadIdx = 7, + parameter int TdoPadIdx = 8, + parameter int DioUsbdevDp = 9, + parameter int DioUsbdevDn = 10, + parameter int MioInUsbdevSense = 11, + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit SecVolatileRawUnlockEn = 1 +) ( + input clk_i, + input rst_ni, + input rst_sys_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + input clk_aon_i, + input rst_aon_ni, + output logic pin_wkup_req_o, + input sleep_en_i, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + input prim_alert_pkg::alert_rx_t[NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t[NumAlerts-1:0] alert_tx_o, + input [NMioPeriphOut-1:0] periph_to_mio_i, + input [NMioPeriphOut-1:0] periph_to_mio_oe_i, + output logic[NMioPeriphIn-1:0] mio_to_periph_o, + input [NDioPads-1:0] periph_to_dio_i, + input [NDioPads-1:0] periph_to_dio_oe_i, + output logic[NDioPads-1:0] dio_to_periph_o, + output prim_pad_wrapper_pkg::pad_attr_t[NMioPads-1:0] mio_attr_o, + output logic[NMioPads-1:0] mio_out_o, + output logic[NMioPads-1:0] mio_oe_o, + input [NMioPads-1:0] mio_in_i, + output prim_pad_wrapper_pkg::pad_attr_t[NDioPads-1:0] dio_attr_o, + output logic[NDioPads-1:0] dio_out_o, + output logic[NDioPads-1:0] dio_oe_o, + input [NDioPads-1:0] dio_in_i +); + + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + usb_dp_idx: DioUsbdevDp, + usb_dn_idx: DioUsbdevDn, + usb_sense_idx: MioInUsbdevSense, + // Pad types for attribute WARL behavior + dio_pad_type: {NDioPads{BidirStd}}, + mio_pad_type: {NMioPads{BidirStd}}, + dio_scan_role: {NDioPads{NoScan}}, + mio_scan_role: {NMioPads{NoScan}} + }; + + pinmux #( + .TargetCfg(PinmuxTargetCfg), + .AlertAsyncOn(AlertAsyncOn), + .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn) + ) dut (.*); + +endmodule : pinmux_tb diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/vip/pinmux_assert_fpv.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/vip/pinmux_assert_fpv.sv new file mode 100644 index 00000000000..b8c72dd8d68 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/fpv/vip/pinmux_assert_fpv.sv @@ -0,0 +1,556 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Assertions for pinmux. +// Intended to be used with a formal tool. + +`include "prim_assert.sv" + +module pinmux_assert_fpv + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; +#( + parameter target_cfg_t TargetCfg = DefaultTargetCfg, + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + parameter bit SecVolatileRawUnlockEn = 0 +) ( + input clk_i, + input rst_ni, + input rst_sys_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + input clk_aon_i, + input rst_aon_ni, + input logic pin_wkup_req_o, + input sleep_en_i, + input tlul_pkg::tl_h2d_t tl_i, + input tlul_pkg::tl_d2h_t tl_o, + input prim_alert_pkg::alert_rx_t[NumAlerts-1:0] alert_rx_i, + input prim_alert_pkg::alert_tx_t[NumAlerts-1:0] alert_tx_o, + input [NMioPeriphOut-1:0] periph_to_mio_i, + input [NMioPeriphOut-1:0] periph_to_mio_oe_i, + input logic[NMioPeriphIn-1:0] mio_to_periph_o, + input [NDioPads-1:0] periph_to_dio_i, + input [NDioPads-1:0] periph_to_dio_oe_i, + input logic[NDioPads-1:0] dio_to_periph_o, + input prim_pad_wrapper_pkg::pad_attr_t[NMioPads-1:0] mio_attr_o, + input logic[NMioPads-1:0] mio_out_o, + input logic[NMioPads-1:0] mio_oe_o, + input [NMioPads-1:0] mio_in_i, + input prim_pad_wrapper_pkg::pad_attr_t[NDioPads-1:0] dio_attr_o, + input logic[NDioPads-1:0] dio_out_o, + input logic[NDioPads-1:0] dio_oe_o, + input [NDioPads-1:0] dio_in_i +); + + /////////////////////////////// + // Declarations & Parameters // + /////////////////////////////// + + ///////////////// + // Assumptions // + ///////////////// + + // Symbolic inputs for FPV + logic [$clog2(pinmux_reg_pkg::NMioPeriphIn)-1:0] periph_sel_i; + logic [$clog2(pinmux_reg_pkg::NMioPads)-1:0] mio_sel_i; + logic [$clog2(pinmux_reg_pkg::NDioPads)-1:0] dio_sel_i; + logic [$clog2(pinmux_reg_pkg::NWkupDetect)-1:0] wkup_sel_i; + + `ASSUME(PeriphSelRange_M, periph_sel_i < pinmux_reg_pkg::NMioPeriphIn) + `ASSUME(PeriphSelStable_M, ##1 $stable(periph_sel_i)) + + `ASSUME(MioSelRange_M, mio_sel_i < pinmux_reg_pkg::NMioPads && !(mio_sel_i inside + {TargetCfg.tck_idx, TargetCfg.tms_idx, TargetCfg.trst_idx, TargetCfg.tdi_idx, + TargetCfg.tdo_idx})) + `ASSUME(MioSelStable_M, ##1 $stable(mio_sel_i)) + + `ASSUME(DioSelRange_M, dio_sel_i < pinmux_reg_pkg::NDioPads) + `ASSUME(DioSelStable_M, ##1 $stable(dio_sel_i)) + + `ASSUME(WkupSelRange_M, wkup_sel_i < pinmux_reg_pkg::NWkupDetect) + `ASSUME(WkupSelStable_M, ##1 $stable(wkup_sel_i)) + + // ------ Input mux assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_mio_periph_insel_mreg_t periph_insel; + assign periph_insel = pinmux.reg2hw.mio_periph_insel[periph_sel_i]; + + `ASSERT(InSel0_A, periph_insel.q == 0 |-> mio_to_periph_o[periph_sel_i] == 1'b0) + `ASSERT(InSel1_A, periph_insel.q == 1 |-> mio_to_periph_o[periph_sel_i] == 1'b1) + `ASSERT(InSelN_A, periph_insel.q > 1 && periph_insel.q < (pinmux_reg_pkg::NMioPads + 2) && + !((periph_insel.q - 2) inside {TargetCfg.tck_idx, TargetCfg.tms_idx, TargetCfg.trst_idx, + TargetCfg.tdi_idx, TargetCfg.tdo_idx}) |-> + mio_to_periph_o[periph_sel_i] == mio_in_i[periph_insel.q - 2]) + `ASSERT(InSelOOB_A, periph_insel.q >= (pinmux_reg_pkg::NMioPads + 2) |-> + mio_to_periph_o[periph_sel_i] == 0) + + `ASSERT(MioToPeriph0Backward_A, mio_to_periph_o[periph_sel_i] == 0 |-> + (periph_insel.q == 0) || + ((periph_insel.q > 1 && periph_insel.q < (pinmux_reg_pkg::NMioPads + 2) && + (pinmux.u_pinmux_strap_sampling.jtag_en || mio_in_i[periph_insel.q - 2] == 0)) || + periph_insel.q >= (pinmux_reg_pkg::NMioPads + 2))) + + `ASSERT(MioToPeriph1Backward_A, mio_to_periph_o[periph_sel_i] == 1 |-> + (periph_insel.q == 1) || + (periph_insel.q > 1 && periph_insel.q < (pinmux_reg_pkg::NMioPads + 2) && + (mio_in_i[periph_insel.q - 2] == 1 || pinmux.u_pinmux_strap_sampling.jtag_en))) + + `ASSERT(DioInSelN_A, dio_to_periph_o == dio_in_i) + + // ------ Output mux assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_mio_outsel_mreg_t mio_outsel; + assign mio_outsel = pinmux.reg2hw.mio_outsel[mio_sel_i]; + + pinmux_reg_pkg::pinmux_reg2hw_mio_pad_sleep_status_mreg_t mio_pad_sleep_status; + assign mio_pad_sleep_status = pinmux.reg2hw.mio_pad_sleep_status[mio_sel_i]; + + + `ASSERT(OutSel0_A, mio_outsel.q == 0 && !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == 1'b0) + `ASSERT(OutSel1_A, mio_outsel.q == 1 && !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == 1'b1) + `ASSERT(OutSel2_A, mio_outsel.q == 2 && !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == 1'b0) + `ASSERT(OutSelN_A, mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == periph_to_mio_i[mio_outsel.q - 3]) + `ASSERT(OutSelOOB_A, mio_outsel.q >= (pinmux_reg_pkg::NMioPeriphOut + 3) && + !mio_pad_sleep_status.q |-> mio_out_o[mio_sel_i] == 0) + + `ASSERT(MioOut0Backward_A, mio_out_o[mio_sel_i] == 0 |-> + mio_pad_sleep_status.q || + mio_outsel.q inside {0, 2} || + mio_outsel.q >= (pinmux_reg_pkg::NMioPeriphOut + 3) || + (mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + periph_to_mio_i[mio_outsel.q - 3] == 0)) + + `ASSERT(MioOut1Backward_A, mio_out_o[mio_sel_i] == 1 |-> + mio_pad_sleep_status.q || + mio_outsel.q == 1 || + mio_outsel.q > (pinmux_reg_pkg::NMioPeriphOut + 3) || + (mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + periph_to_mio_i[mio_outsel.q - 3] == 1)) + + `ASSERT(OutSelOe0_A, mio_outsel.q == 0 && !mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b1) + `ASSERT(OutSelOe1_A, mio_outsel.q == 1 && !mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b1) + `ASSERT(OutSelOe2_A, mio_outsel.q == 2 && !mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b0) + `ASSERT(OutSelOeN_A, mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + !mio_pad_sleep_status.q |-> mio_oe_o[mio_sel_i] == periph_to_mio_oe_i[mio_outsel.q - 3]) + `ASSERT(OutSelOeOOB_A, mio_outsel.q >= (pinmux_reg_pkg::NMioPeriphOut + 3) && + !mio_pad_sleep_status.q |-> mio_oe_o[mio_sel_i] == 0) + + `ASSERT(MioOe0Backward_A, mio_oe_o[mio_sel_i] == 0 |-> + mio_pad_sleep_status.q || + mio_outsel.q == 2 || + mio_outsel.q >= (pinmux_reg_pkg::NMioPeriphOut + 3) || + (mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + periph_to_mio_oe_i[mio_outsel.q - 3] == 0)) + + `ASSERT(MioOe1Backward_A, mio_oe_o[mio_sel_i] == 1 |-> + mio_pad_sleep_status.q || + mio_outsel.q inside {0, 1} || + mio_outsel.q > (pinmux_reg_pkg::NMioPeriphOut + 3) || + (mio_outsel.q > 2 && mio_outsel.q < (pinmux_reg_pkg::NMioPeriphOut + 3) && + periph_to_mio_oe_i[mio_outsel.q - 3] == 1)) + + // ------ Mio sleep behavior assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_mio_pad_sleep_en_mreg_t mio_pad_sleep_en; + assign mio_pad_sleep_en = pinmux.reg2hw.mio_pad_sleep_en[mio_sel_i]; + pinmux_reg_pkg::pinmux_reg2hw_mio_pad_sleep_mode_mreg_t mio_pad_sleep_mode; + assign mio_pad_sleep_mode = pinmux.reg2hw.mio_pad_sleep_mode[mio_sel_i]; + + `ASSERT(MioSleepMode0_A, ##1 mio_pad_sleep_mode.q == 0 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_out_o[mio_sel_i] == 1'b0) + `ASSERT(MioSleepMode1_A, ##1 mio_pad_sleep_mode.q == 1 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_out_o[mio_sel_i] == 1'b1) + `ASSERT(MioSleepMode2_A, ##1 mio_pad_sleep_mode.q == 2 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_out_o[mio_sel_i] == 1'b0) + `ASSERT(MioSleepMode3_A, ##1 mio_pad_sleep_mode.q == 3 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + $stable(mio_out_o[mio_sel_i])) + `ASSERT(MioSleepStable_A, ##1 !$rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + $stable(mio_out_o[mio_sel_i])) + + `ASSERT(MioOeSleepMode0_A, ##1 mio_pad_sleep_mode.q == 0 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q && sleep_en_i|-> + mio_oe_o[mio_sel_i] == 1'b1) + `ASSERT(MioOeSleepMode1_A, ##1 mio_pad_sleep_mode.q == 1 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b1) + `ASSERT(MioOeSleepMode2_A, ##1 mio_pad_sleep_mode.q == 2 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + mio_oe_o[mio_sel_i] == 1'b0) + `ASSERT(MioOeSleepMode3_A, ##1 mio_pad_sleep_mode.q == 3 && mio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + $stable(mio_oe_o[mio_sel_i])) + `ASSERT(MioOeSleepStable_A, ##1 !$rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 mio_pad_sleep_status.q |-> + $stable(mio_oe_o[mio_sel_i])) + + // ------Mio sleep enabled backward assertions ------ + `ASSERT(MioSleep0Backward_A, mio_out_o[mio_sel_i] == 0 |-> + mio_pad_sleep_status.q == 0 || + // Sleep mode set to 0 and 2. + $past(mio_pad_sleep_mode.q) inside {0, 2} || + // Previous value is 0 and sleep mode is set to 3. + ($past(mio_out_o[mio_sel_i]) == 0) && + ($past(mio_pad_sleep_mode.q) == 3 || + // Previous value is 0 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !mio_pad_sleep_en.q) && mio_pad_sleep_status.q))) + + `ASSERT(MioSleep1Backward_A, mio_out_o[mio_sel_i] == 1 |-> + mio_pad_sleep_status.q == 0 || + // Sleep mode set to 1. + $past(mio_pad_sleep_mode.q) == 1 || + // Previous value is 1 and sleep mode is set to 3. + ($past(mio_out_o[mio_sel_i]) == 1) && + ($past(mio_pad_sleep_mode.q) == 3 || + // Previous value is 1 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !mio_pad_sleep_en.q) && mio_pad_sleep_status.q))) + + `ASSERT(MioOeSleep0Backward_A, mio_oe_o[mio_sel_i] == 0 |-> + mio_pad_sleep_status.q == 0 || + // Sleep mode set to 2. + $past(mio_pad_sleep_mode.q) == 2 || + // Previous value is 0 and sleep mode is set to 3. + ($past(mio_oe_o[mio_sel_i]) == 0) && + ($past(mio_pad_sleep_mode.q) == 3 || + // Previous value is 0 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !mio_pad_sleep_en.q) && mio_pad_sleep_status.q))) + + `ASSERT(MioOeSleep1Backward_A, mio_oe_o[mio_sel_i] == 1 |-> + mio_pad_sleep_status.q == 0 || + // Sleep mode set to 0 or 1. + $past(mio_pad_sleep_mode.q) inside {0, 1} || + // Previous value is 1 and sleep mode is set to 3. + ($past(mio_oe_o[mio_sel_i]) == 1) && + ($past(mio_pad_sleep_mode.q) == 3 || + // Previous value is 1 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !mio_pad_sleep_en.q) && mio_pad_sleep_status.q))) + + // ------ Mio_attr_o ------ + pad_attr_t mio_pad_attr; + assign mio_pad_attr = pinmux.mio_pad_attr_q[mio_sel_i]; + + pad_attr_t mio_pad_attr_mask; + pad_type_e bid_pad_types[4]; + assign bid_pad_types = {BidirStd, BidirTol, DualBidirTol, BidirOd}; + assign mio_pad_attr_mask.invert = TargetCfg.mio_pad_type[mio_sel_i] != AnalogIn0; + assign mio_pad_attr_mask.virt_od_en = TargetCfg.mio_pad_type[mio_sel_i] inside {bid_pad_types}; + assign mio_pad_attr_mask.pull_en = TargetCfg.mio_pad_type[mio_sel_i] != AnalogIn0; + assign mio_pad_attr_mask.pull_select = TargetCfg.mio_pad_type[mio_sel_i] != AnalogIn0; + assign mio_pad_attr_mask.drive_strength[0] = + TargetCfg.mio_pad_type[mio_sel_i] inside {bid_pad_types}; + assign mio_pad_attr_mask.keep_en = 0; + assign mio_pad_attr_mask.schmitt_en = 0; + assign mio_pad_attr_mask.od_en = 0; + assign mio_pad_attr_mask.input_disable = 1'b1; + assign mio_pad_attr_mask.slew_rate = '0; + assign mio_pad_attr_mask.drive_strength[3:1] = '0; + + `ASSERT(MioAttrO_A, mio_attr_o[mio_sel_i] == (mio_pad_attr & mio_pad_attr_mask)) + + `ASSERT(MioJtagAttrO_A, pinmux.u_pinmux_strap_sampling.jtag_en |-> + mio_attr_o[TargetCfg.tck_idx] == 0 && + mio_attr_o[TargetCfg.tms_idx] == 0 && + mio_attr_o[TargetCfg.trst_idx] == 0 && + mio_attr_o[TargetCfg.tdi_idx] == 0 && + mio_attr_o[TargetCfg.tdo_idx] == 0) + + // ------ Dio_attr_o ------ + pinmux_reg_pkg::pinmux_reg2hw_dio_pad_attr_mreg_t dio_pad_attr; + assign dio_pad_attr = pinmux.dio_pad_attr_q[dio_sel_i]; + + pad_attr_t dio_pad_attr_mask; + assign dio_pad_attr_mask.invert = TargetCfg.dio_pad_type[dio_sel_i] != AnalogIn0; + assign dio_pad_attr_mask.virt_od_en = TargetCfg.dio_pad_type[dio_sel_i] inside {bid_pad_types}; + assign dio_pad_attr_mask.pull_en = TargetCfg.dio_pad_type[dio_sel_i] != AnalogIn0; + assign dio_pad_attr_mask.pull_select = TargetCfg.dio_pad_type[dio_sel_i] != AnalogIn0; + assign dio_pad_attr_mask.drive_strength[0] = + TargetCfg.dio_pad_type[dio_sel_i] inside {bid_pad_types}; + assign dio_pad_attr_mask.keep_en = 0; + assign dio_pad_attr_mask.schmitt_en = 0; + assign dio_pad_attr_mask.od_en = 0; + assign dio_pad_attr_mask.input_disable = 1; + assign dio_pad_attr_mask.slew_rate = '0; + assign dio_pad_attr_mask.drive_strength[3:1] = '0; + + `ASSERT(DioAttrO_A, dio_attr_o[dio_sel_i] == (dio_pad_attr & dio_pad_attr_mask)) + + // ------ Output dedicated output assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_dio_pad_sleep_status_mreg_t dio_pad_sleep_status; + assign dio_pad_sleep_status = pinmux.reg2hw.dio_pad_sleep_status[dio_sel_i]; + + `ASSERT(DOutSelN_A, !dio_pad_sleep_status.q |-> + dio_out_o[dio_sel_i] == periph_to_dio_i[dio_sel_i]) + + `ASSERT(DOutSelOeN_A, !dio_pad_sleep_status.q |-> + dio_oe_o[dio_sel_i] == periph_to_dio_oe_i[dio_sel_i]) + + // ------ Dio sleep behavior assertions ------ + pinmux_reg_pkg::pinmux_reg2hw_dio_pad_sleep_en_mreg_t dio_pad_sleep_en; + assign dio_pad_sleep_en = pinmux.reg2hw.dio_pad_sleep_en[dio_sel_i]; + pinmux_reg_pkg::pinmux_reg2hw_dio_pad_sleep_mode_mreg_t dio_pad_sleep_mode; + assign dio_pad_sleep_mode = pinmux.reg2hw.dio_pad_sleep_mode[dio_sel_i]; + + `ASSERT(DioSleepMode0_A, ##1 dio_pad_sleep_mode.q == 0 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_out_o[dio_sel_i] == 1'b0) + `ASSERT(DioSleepMode1_A, ##1 dio_pad_sleep_mode.q == 1 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_out_o[dio_sel_i] == 1'b1) + `ASSERT(DioSleepMode2_A, ##1 dio_pad_sleep_mode.q == 2 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_out_o[dio_sel_i] == 1'b0) + `ASSERT(DioSleepMode3_A, ##1 dio_pad_sleep_mode.q == 3 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + $stable(dio_out_o[dio_sel_i])) + `ASSERT(DioSleepStable_A, ##1 !$rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + $stable(dio_out_o[dio_sel_i])) + + `ASSERT(DioOeSleepMode0_A, ##1 dio_pad_sleep_mode.q == 0 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_oe_o[dio_sel_i] == 1'b1) + `ASSERT(DioOeSleepMode1_A, ##1 dio_pad_sleep_mode.q == 1 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_oe_o[dio_sel_i] == 1'b1) + `ASSERT(DioOeSleepMode2_A, ##1 dio_pad_sleep_mode.q == 2 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + dio_oe_o[dio_sel_i] == 1'b0) + `ASSERT(DioOeSleepMode3_A, ##1 dio_pad_sleep_mode.q == 3 && dio_pad_sleep_en.q == 1 && + $rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + $stable(dio_oe_o[dio_sel_i])) + `ASSERT(DioOeSleepStable_A, ##1 !$rose(sleep_en_i) + // Ensure SW does not write to sleep status register to clear sleep status. + ##1 dio_pad_sleep_status.q |-> + $stable(dio_oe_o[dio_sel_i])) + + // ------Dio backward assertions ------ + `ASSERT(Dio0Backward_A, dio_out_o[dio_sel_i] == 0 |-> + // Input is 0. + periph_to_dio_i[dio_sel_i] == 0 || + // Sleep mode set to 0 and 2. + $past(dio_pad_sleep_mode.q) inside {0, 2} || + // Previous value is 0 and sleep mode is set to 3. + ($past(dio_out_o[dio_sel_i]) == 0) && + ($past(dio_pad_sleep_mode.q) == 3 || + // Previous value is 0 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !dio_pad_sleep_en.q) && dio_pad_sleep_status.q))) + + `ASSERT(Dio1Backward_A, dio_out_o[dio_sel_i] == 1 |-> + // input is 1. + periph_to_dio_i[dio_sel_i] == 1 || + // Sleep mode set to 1. + $past(dio_pad_sleep_mode.q) == 1 || + // Previous value is 1 and sleep mode is set to 3. + ($past(dio_out_o[dio_sel_i]) == 1) && + ($past(dio_pad_sleep_mode.q) == 3 || + // Previous value is 1 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !dio_pad_sleep_en.q) && dio_pad_sleep_status.q))) + + `ASSERT(DioOe0Backward_A, dio_oe_o[dio_sel_i] == 0 |-> + // Input is 0. + periph_to_dio_oe_i[dio_sel_i] == 0 || + // Sleep mode set to 2. + $past(dio_pad_sleep_mode.q) == 2 || + // Previous value is 0 and sleep mode is set to 3. + ($past(dio_oe_o[dio_sel_i]) == 0) && + ($past(dio_pad_sleep_mode.q) == 3 || + // Previous value is 0 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !dio_pad_sleep_en.q) && dio_pad_sleep_status.q))) + + `ASSERT(DioOe1Backward_A, dio_oe_o[dio_sel_i] == 1 |-> + // input is 1. + periph_to_dio_oe_i[dio_sel_i] == 1 || + // Sleep mode set to 0 or 1. + $past(dio_pad_sleep_mode.q) inside {0, 1} || + // Previous value is 1 and sleep mode is set to 3. + ($past(dio_oe_o[dio_sel_i]) == 1) && + ($past(dio_pad_sleep_mode.q) == 3 || + // Previous value is 1 and sleep mode selection is disabled either by sleep_en_i input + // or sleep_en CSR. + ($past(!$rose(sleep_en_i) || !dio_pad_sleep_en.q) && dio_pad_sleep_status.q))) + + // ------ Wakeup assertions ------ + pinmux_reg2hw_wkup_detector_en_mreg_t wkup_detector_en; + assign wkup_detector_en = pinmux.reg2hw.wkup_detector_en[wkup_sel_i]; + pinmux_reg2hw_wkup_detector_mreg_t wkup_detector; + assign wkup_detector = pinmux.reg2hw.wkup_detector[wkup_sel_i]; + pinmux_reg2hw_wkup_detector_cnt_th_mreg_t wkup_detector_cnt_th; + assign wkup_detector_cnt_th = pinmux.reg2hw.wkup_detector_cnt_th[wkup_sel_i]; + pinmux_reg2hw_wkup_detector_padsel_mreg_t wkup_detector_padsel; + assign wkup_detector_padsel = pinmux.reg2hw.wkup_detector_padsel[wkup_sel_i]; + pinmux_hw2reg_wkup_cause_mreg_t wkup_cause; + assign wkup_cause = pinmux.hw2reg.wkup_cause[wkup_sel_i]; + pinmux_reg2hw_wkup_cause_mreg_t wkup_cause_reg2hw; + + // Variable to gether all wkup causes. + assign wkup_cause_reg2hw = pinmux.reg2hw.wkup_cause[wkup_sel_i]; + logic[pinmux_reg_pkg::NWkupDetect-1:0] wkup_cause_q; + for (genvar i = 0; i < pinmux_reg_pkg::NWkupDetect; i++) begin : gen_wkup_cause_q + assign wkup_cause_q[i] = pinmux.reg2hw.wkup_cause[i].q; + end + + // Retrieve pin value based on Mio and Dio selection. + logic pin_val; + assign pin_val = wkup_detector.miodio.q ? + (wkup_detector_padsel.q >= pinmux_reg_pkg::NDioPads ? 0 : + dio_in_i[wkup_detector_padsel.q]) : + (wkup_detector_padsel.q >= (pinmux_reg_pkg::NMioPads + 2) ? 0 : + wkup_detector_padsel == 0 ? 0 : + wkup_detector_padsel == 1 ? 1 : + mio_in_i[wkup_detector_padsel.q - 2]); + + // Retrieve filterd pin value with a 2 aon_clock synchronizer. + logic [3:0] filter_vals; + logic pin_val_sync_1, pin_val_sync_2; + + always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin + if (!rst_aon_ni) begin + pin_val_sync_1 <= 1'b0; + pin_val_sync_2 <= 1'b0; + end else begin + pin_val_sync_1 <= pin_val; + pin_val_sync_2 <= pin_val_sync_1; + end + end + + always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin + if (!rst_aon_ni) begin + filter_vals <= 4'b0; + end else if (pin_val_sync_2 == filter_vals[0]) begin + filter_vals <= (filter_vals << 1) | pin_val_sync_2; + end else begin + filter_vals <= {filter_vals[3], filter_vals[3], filter_vals[3], pin_val_sync_2}; + end + end + + logic final_pin_val; + assign final_pin_val = wkup_detector.filter.q ? filter_vals[3] : pin_val_sync_2; + + // Threshold counters. + // Adding one more bit for the counters to check overflow case. + // Issue #11194 documented design will use one counter to count for both low and high threshold. + bit [WkupCntWidth:0] cnter; + always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin + if (!rst_aon_ni || !wkup_detector_en.q) begin + cnter <= 0; + end else if (wkup_detector.mode.q == 3) begin + if (final_pin_val && (cnter < wkup_detector_cnt_th.q)) begin + cnter <= cnter + 1; + end else begin + cnter <= 0; + end + end else if (wkup_detector.mode.q == 4) begin + if (!final_pin_val && (cnter < wkup_detector_cnt_th.q)) begin + cnter <= cnter + 1; + end else begin + cnter <= 0; + end + end else begin + cnter <= 0; + end + end + + `ASSERT(WkupPosedge_A, wkup_detector_en.q && wkup_detector.mode.q == 0 && + $rose(final_pin_val) |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + `ASSERT(WkupNegedge_A, wkup_detector_en.q && wkup_detector.mode.q == 1 && + $fell(final_pin_val) |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + `ASSERT(WkupEdge_A, wkup_detector_en.q && wkup_detector.mode.q == 2 && + ($fell(final_pin_val) || $rose(final_pin_val)) |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + `ASSERT(WkupTimedHigh_A, (cnter >= wkup_detector_cnt_th.q) && wkup_detector_en.q && + wkup_detector.mode.q == 3 |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + `ASSERT(WkupTimedLow_A, (cnter >= wkup_detector_cnt_th.q) && wkup_detector_en.q && + wkup_detector.mode.q == 4 |-> wkup_cause.de, + clk_aon_i, !rst_aon_ni) + + `ASSERT(WkupCauseQ_A, wkup_cause.de && !u_reg.aon_wkup_cause_we |=> + wkup_cause_reg2hw.q, clk_aon_i, !rst_aon_ni) + + `ASSERT(AonWkupO_A, |wkup_cause_q <-> pin_wkup_req_o, clk_aon_i, !rst_aon_ni) + + `ASSERT(WkupCause0_A, wkup_cause.de == 0 |-> + (wkup_detector_en.q == 0) || + (wkup_detector_en.q == 1 && + ((wkup_detector.mode.q == 0 && !$rose(final_pin_val)) || + (wkup_detector.mode.q > 4 && !$rose(final_pin_val)) || + (wkup_detector.mode.q == 1 && !$fell(final_pin_val)) || + (wkup_detector.mode.q == 2 && !$changed(final_pin_val)) || + (wkup_detector.mode.q == 3 && (cnter < wkup_detector_cnt_th.q)) || + (wkup_detector.mode.q == 4 && (cnter < wkup_detector_cnt_th.q)))), + clk_aon_i, !rst_aon_ni) + + `ASSERT(WkupCause1_A, wkup_cause.de == 1 |-> + wkup_detector_en.q == 1 && + ((wkup_detector.mode.q == 0 && $rose(final_pin_val)) || + (wkup_detector.mode.q > 4 && $rose(final_pin_val)) || + (wkup_detector.mode.q == 1 && $fell(final_pin_val)) || + (wkup_detector.mode.q == 2 && $changed(final_pin_val)) || + (wkup_detector.mode.q == 3 && (cnter >= wkup_detector_cnt_th.q)) || + (wkup_detector.mode.q == 4 && (cnter >= wkup_detector_cnt_th.q))), + clk_aon_i, !rst_aon_ni) + + // Fatal alert related assertions + `ASSUME(TriggerAfterAlertInit_S, $stable(rst_ni) == 0 |-> + pinmux.u_reg.intg_err_o == 0 [*10]) + `ASSERT(TlIntgFatalAlert_A, pinmux.u_reg.intg_err_o |-> (##[0:7] (alert_tx_o[0].alert_p)) [*2]) + + // Since the USB wake module is blackboxed, we have to add an assumption here since the + // ASSERT_KNOWN assertions embedded in pinmux.sv would fail otherwise. + `ASSUME_FPV(UsbWkupReqKnownO_M, + !$isunknown(u_usbdev_aon_wake.wake_req_aon_o), clk_aon_i, !rst_aon_ni) + `ASSUME_FPV(UsbWakeDetectActiveKnownO_M, + !$isunknown(u_usbdev_aon_wake.wake_detect_active_aon_o), clk_aon_i, !rst_aon_ni) + +endmodule : pinmux_assert_fpv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/lint/pinmux.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/lint/pinmux.vlt new file mode 100644 index 00000000000..26ea262b5bc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/lint/pinmux.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for pinmux diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/lint/pinmux.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/lint/pinmux.waiver new file mode 100644 index 00000000000..f1569a162d0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/lint/pinmux.waiver @@ -0,0 +1,32 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for pinmux + +waive -rules NOT_READ -location {pinmux_reg_top.sv} -regexp {.*reg_wdata.*} \ + -comment "Upper bits of reg_wdata are not read" + +waive -rules HIER_NET_NOT_READ -location {pinmux_reg_top.sv} -regexp {.*reg_wdata.*} \ + -comment "Upper bits of reg_wdata are not read" + +waive -rules VAR_INDEX_RANGE -location {pinmux.sv} -regexp {.*maximum value.*} \ + -comment "Indexed arrays may not be fully populated." + +waive -rules CLOCK_MUX -location {pinmux.sv} -regexp {Clock '(in_padring_i\[38\]|mio_in_i\[38\]|jtag_req.tck)' reaches a multiplexer here, used as a clock 'tck_i' at dmi_jtag_tap.sv} \ + -comment "The 'mio_in_i[TckPadIdx]' input signal is connected to 'jtag_req.tck' which eventually feeds into the JTAG Selection Mux." + +waive -rules CLOCK_DRIVER -location {pinmux.sv} -regexp {'mio_attr\[28\].pull_select' is driven here, and used as a clock} \ + -comment "'MioPadIoc6' at index 28 may also serve as an external clock input. The 'pull_select' signal impacts the actual value obtained from the pad simulation model." + +waive -rules CLOCK_USE -location {pinmux.sv} -regexp {'hw2reg.mio_pad_attr\[28\].pull_select.d' is connected to 'pinmux_reg_top' port 'hw2reg.mio_pad_attr\[28\].pull_select.d', and used as a clock} \ + -comment "'MioPadIoc6' at index 28 may also serve as an external clock input. The 'pull_select' signal impacts the actual value obtained from the pad simulation model." + +waive -rules CLOCK_USE -location {pinmux.sv} -regexp {'(dio_wkup_mux\[12\]|dio_wkup_mux\[13\]|mio_wkup_mux\[40\])' is used for some other purpose, and as clock} \ + -comment "The wakeup detectors can be configured to observe any MIO / DIO pins. 'DioSpiDeviceSck' (index 12) is the spi_device clock, 'DioSpiDeviceCsb' (index 13) is the spi_device chip select (used as a clock for detecting toggles inside spi_device), and 'Dft0PadIdx' (index 40) controls the first TAP strap and thus the TAP selection mux driving the JTAG clocks." + +waive -rules CLOCK_MUX -location {pinmux.sv} -regexp {Clock 'dio_in_i\[12\]' reaches a multiplexer here, used as a clock 'clk_i'} \ + -comment "This mux is required to filter designated scan clock inputs (e.g. 'DioSpiDeviceSck' at index 12) from wakeup detector inputs" + +waive -rules RESET_ONLY -location {pinmux.sv} -regexp {'mio_pad_attr_q\[0\]' is asynchronously reset but has no other assignments in this block} \ + -comment "This error can safely be ignored: The signal is obviously driven further down in the very same block, changing the TargetCfg.tap_strap0_idx value to a non-zero value (which it actually is in the Earlgrey top level) makes the error go away." diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/pinmux.core b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/pinmux.core new file mode 100644 index 00000000000..c16fbf9e692 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/pinmux.core @@ -0,0 +1,92 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:pinmux:0.1 +description: "Pin Multiplexer" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:prim:clock_buf + - lowrisc:prim:buf + - lowrisc:prim:lc_dec + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:lc_or_hardened + - lowrisc:prim:pad_wrapper_pkg + - lowrisc:prim:pad_attr + - lowrisc:ip:jtag_pkg + - lowrisc:darjeeling_no_ibex_ip:pinmux_reg:0.1 + - lowrisc:darjeeling_no_ibex_ip:pinmux_pkg:0.1 + files: + - rtl/pinmux_wkup.sv + - rtl/pinmux_jtag_buf.sv + - rtl/pinmux_jtag_breakout.sv + - rtl/pinmux.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pinmux.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pinmux.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pinmux + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" + + syn: + <<: *default_target + # TODO: set default to DC once + # this option is available + # olofk/edalize#89 + default_tool: icarus + parameters: + - SYNTHESIS=true + + formal: + filesets: + - files_rtl + toplevel: pinmux_tb diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/pinmux_pkg.core b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/pinmux_pkg.core new file mode 100644 index 00000000000..034fe949583 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/pinmux_pkg.core @@ -0,0 +1,21 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:pinmux_pkg:0.1 +description: "Pinmux package" + +filesets: + files_rtl: + depend: + - lowrisc:prim:pad_wrapper_pkg + - lowrisc:tlul:headers + files: + - rtl/pinmux_reg_pkg.sv + - rtl/pinmux_pkg.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/pinmux_reg.core b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/pinmux_reg.core new file mode 100644 index 00000000000..0753d38f4e1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/pinmux_reg.core @@ -0,0 +1,21 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:pinmux_reg:0.1 +description: "Auto-generated pinmux register sources" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:subreg + - lowrisc:darjeeling_no_ibex_ip:pinmux_pkg + files: + - rtl/pinmux_reg_top.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux.sv new file mode 100644 index 00000000000..1443df3f914 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux.sv @@ -0,0 +1,523 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Pinmux toplevel. +// + +`include "prim_assert.sv" + +module pinmux + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; +#( + // Taget-specific pinmux configuration passed down from the + // target-specific top-level. + parameter target_cfg_t TargetCfg = DefaultTargetCfg, + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert signal + parameter int unsigned AlertSkewCycles = 1 +) ( + input clk_i, + input rst_ni, + input rst_sys_ni, + // Scan enable + input prim_mubi_pkg::mubi4_t scanmode_i, + // Slow always-on clock + input clk_aon_i, + input rst_aon_ni, + // Wakeup request, running on clk_aon_i + output logic pin_wkup_req_o, + // Sleep enable and strap sample enable + // from pwrmgr, running on clk_i + input sleep_en_i, + // Bus Interface (device) + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // Muxed Peripheral side + input [NMioPeriphOut-1:0] periph_to_mio_i, + input [NMioPeriphOut-1:0] periph_to_mio_oe_i, + output logic [NMioPeriphIn-1:0] mio_to_periph_o, + // Dedicated Peripheral side + input [NDioPads-1:0] periph_to_dio_i, + input [NDioPads-1:0] periph_to_dio_oe_i, + output logic [NDioPads-1:0] dio_to_periph_o, + // Pad side + // MIOs + output prim_pad_wrapper_pkg::pad_attr_t [NMioPads-1:0] mio_attr_o, + output logic [NMioPads-1:0] mio_out_o, + output logic [NMioPads-1:0] mio_oe_o, + input [NMioPads-1:0] mio_in_i, + // DIOs + output prim_pad_wrapper_pkg::pad_attr_t [NDioPads-1:0] dio_attr_o, + output logic [NDioPads-1:0] dio_out_o, + output logic [NDioPads-1:0] dio_oe_o, + input [NDioPads-1:0] dio_in_i +); + + ////////////////////////////////// + // Regfile Breakout and Mapping // + ////////////////////////////////// + + logic [NumAlerts-1:0] alert_test, alerts; + pinmux_reg2hw_t reg2hw; + pinmux_hw2reg_t hw2reg; + + pinmux_reg_top u_reg ( + .clk_i, + .rst_ni, + .clk_aon_i, + .rst_aon_ni, + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + // SEC_CM: BUS.INTEGRITY + .intg_err_o(alerts[0]) + ); + + //////////// + // Alerts // + //////////// + + assign alert_test = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .SkewCycles(AlertSkewCycles), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[0] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + ///////////////////////////// + // Pad attribute registers // + ///////////////////////////// + + prim_pad_wrapper_pkg::pad_attr_t [NDioPads-1:0] dio_pad_attr_q; + prim_pad_wrapper_pkg::pad_attr_t [NMioPads-1:0] mio_pad_attr_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + dio_pad_attr_q <= '0; + for (int kk = 0; kk < NMioPads; kk++) begin + if (kk == TargetCfg.tap_strap0_idx) begin + // TAP strap 0 is sampled after reset (and only once for life cycle states that are not + // TEST_UNLOCKED* or RMA). To ensure it gets sampled as 0 unless driven to 1 from an + // external source (and specifically that it gets sampled as 0 when left floating / not + // connected), this enables the pull-down of the pad at reset. + mio_pad_attr_q[kk] <= '{pull_en: 1'b1, default: '0}; + end else begin + mio_pad_attr_q[kk] <= '0; + end + end + end else begin + // dedicated pads + for (int kk = 0; kk < NDioPads; kk++) begin + if (reg2hw.dio_pad_attr[kk].drive_strength.qe) begin + dio_pad_attr_q[kk].drive_strength <= reg2hw.dio_pad_attr[kk].drive_strength.q; + end + if (reg2hw.dio_pad_attr[kk].slew_rate.qe) begin + dio_pad_attr_q[kk].slew_rate <= reg2hw.dio_pad_attr[kk].slew_rate.q; + end + if (reg2hw.dio_pad_attr[kk].input_disable.qe) begin + dio_pad_attr_q[kk].input_disable <= reg2hw.dio_pad_attr[kk].input_disable.q; + end + if (reg2hw.dio_pad_attr[kk].od_en.qe) begin + dio_pad_attr_q[kk].od_en <= reg2hw.dio_pad_attr[kk].od_en.q; + end + if (reg2hw.dio_pad_attr[kk].schmitt_en.qe) begin + dio_pad_attr_q[kk].schmitt_en <= reg2hw.dio_pad_attr[kk].schmitt_en.q; + end + if (reg2hw.dio_pad_attr[kk].keeper_en.qe) begin + dio_pad_attr_q[kk].keep_en <= reg2hw.dio_pad_attr[kk].keeper_en.q; + end + if (reg2hw.dio_pad_attr[kk].pull_select.qe) begin + dio_pad_attr_q[kk].pull_select <= reg2hw.dio_pad_attr[kk].pull_select.q; + end + if (reg2hw.dio_pad_attr[kk].pull_en.qe) begin + dio_pad_attr_q[kk].pull_en <= reg2hw.dio_pad_attr[kk].pull_en.q; + end + if (reg2hw.dio_pad_attr[kk].virtual_od_en.qe) begin + dio_pad_attr_q[kk].virt_od_en <= reg2hw.dio_pad_attr[kk].virtual_od_en.q; + end + if (reg2hw.dio_pad_attr[kk].invert.qe) begin + dio_pad_attr_q[kk].invert <= reg2hw.dio_pad_attr[kk].invert.q; + end + end + // muxed pads + for (int kk = 0; kk < NMioPads; kk++) begin + if (reg2hw.mio_pad_attr[kk].drive_strength.qe) begin + mio_pad_attr_q[kk].drive_strength <= reg2hw.mio_pad_attr[kk].drive_strength.q; + end + if (reg2hw.mio_pad_attr[kk].slew_rate.qe) begin + mio_pad_attr_q[kk].slew_rate <= reg2hw.mio_pad_attr[kk].slew_rate.q; + end + if (reg2hw.mio_pad_attr[kk].input_disable.qe) begin + mio_pad_attr_q[kk].input_disable <= reg2hw.mio_pad_attr[kk].input_disable.q; + end + if (reg2hw.mio_pad_attr[kk].od_en.qe) begin + mio_pad_attr_q[kk].od_en <= reg2hw.mio_pad_attr[kk].od_en.q; + end + if (reg2hw.mio_pad_attr[kk].schmitt_en.qe) begin + mio_pad_attr_q[kk].schmitt_en <= reg2hw.mio_pad_attr[kk].schmitt_en.q; + end + if (reg2hw.mio_pad_attr[kk].keeper_en.qe) begin + mio_pad_attr_q[kk].keep_en <= reg2hw.mio_pad_attr[kk].keeper_en.q; + end + if (reg2hw.mio_pad_attr[kk].pull_select.qe) begin + mio_pad_attr_q[kk].pull_select <= reg2hw.mio_pad_attr[kk].pull_select.q; + end + if (reg2hw.mio_pad_attr[kk].pull_en.qe) begin + mio_pad_attr_q[kk].pull_en <= reg2hw.mio_pad_attr[kk].pull_en.q; + end + if (reg2hw.mio_pad_attr[kk].virtual_od_en.qe) begin + mio_pad_attr_q[kk].virt_od_en <= reg2hw.mio_pad_attr[kk].virtual_od_en.q; + end + if (reg2hw.mio_pad_attr[kk].invert.qe) begin + mio_pad_attr_q[kk].invert <= reg2hw.mio_pad_attr[kk].invert.q; + end + end + end + end + + //////////////////////// + // Connect attributes // + //////////////////////// + + pad_attr_t [NDioPads-1:0] dio_attr; + for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_attr + pad_attr_t warl_mask; + + prim_pad_attr #( + .PadType(TargetCfg.dio_pad_type[k]) + ) u_prim_pad_attr ( + .attr_warl_o(warl_mask) + ); + + assign dio_attr[k] = dio_pad_attr_q[k] & warl_mask; + assign hw2reg.dio_pad_attr[k].drive_strength.d = dio_attr[k].drive_strength; + assign hw2reg.dio_pad_attr[k].slew_rate.d = dio_attr[k].slew_rate; + assign hw2reg.dio_pad_attr[k].input_disable.d = dio_attr[k].input_disable; + assign hw2reg.dio_pad_attr[k].od_en.d = dio_attr[k].od_en; + assign hw2reg.dio_pad_attr[k].schmitt_en.d = dio_attr[k].schmitt_en; + assign hw2reg.dio_pad_attr[k].keeper_en.d = dio_attr[k].keep_en; + assign hw2reg.dio_pad_attr[k].pull_select.d = dio_attr[k].pull_select; + assign hw2reg.dio_pad_attr[k].pull_en.d = dio_attr[k].pull_en; + assign hw2reg.dio_pad_attr[k].virtual_od_en.d = dio_attr[k].virt_od_en; + assign hw2reg.dio_pad_attr[k].invert.d = dio_attr[k].invert; + end + + pad_attr_t [NMioPads-1:0] mio_attr; + for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_attr + pad_attr_t warl_mask; + + prim_pad_attr #( + .PadType(TargetCfg.mio_pad_type[k]) + ) u_prim_pad_attr ( + .attr_warl_o(warl_mask) + ); + + assign mio_attr[k] = mio_pad_attr_q[k] & warl_mask; + assign hw2reg.mio_pad_attr[k].drive_strength.d = mio_attr[k].drive_strength; + assign hw2reg.mio_pad_attr[k].slew_rate.d = mio_attr[k].slew_rate; + assign hw2reg.mio_pad_attr[k].input_disable.d = mio_attr[k].input_disable; + assign hw2reg.mio_pad_attr[k].od_en.d = mio_attr[k].od_en; + assign hw2reg.mio_pad_attr[k].schmitt_en.d = mio_attr[k].schmitt_en; + assign hw2reg.mio_pad_attr[k].keeper_en.d = mio_attr[k].keep_en; + assign hw2reg.mio_pad_attr[k].pull_select.d = mio_attr[k].pull_select; + assign hw2reg.mio_pad_attr[k].pull_en.d = mio_attr[k].pull_en; + assign hw2reg.mio_pad_attr[k].virtual_od_en.d = mio_attr[k].virt_od_en; + assign hw2reg.mio_pad_attr[k].invert.d = mio_attr[k].invert; + end + + // Local versions of the input signals + logic [NMioPads-1:0] mio_out, mio_oe, mio_in; + logic [NDioPads-1:0] dio_out, dio_oe, dio_in; + + // Just pass through these signals. + assign { dio_out_o, mio_out_o } = { dio_out, mio_out }; + assign { dio_oe_o , mio_oe_o } = { dio_oe, mio_oe }; + assign { dio_in, mio_in } = { dio_in_i, mio_in_i }; + assign { dio_attr_o, mio_attr_o } = { dio_attr, mio_attr }; + + ///////////////////////// + // Retention Registers // + ///////////////////////// + + logic sleep_en_q, sleep_trig; + + logic [NMioPads-1:0] mio_sleep_trig; + logic [NMioPads-1:0] mio_out_retreg_d, mio_oe_retreg_d; + logic [NMioPads-1:0] mio_out_retreg_q, mio_oe_retreg_q; + + logic [NDioPads-1:0] dio_sleep_trig; + logic [NDioPads-1:0] dio_out_retreg_d, dio_oe_retreg_d; + logic [NDioPads-1:0] dio_out_retreg_q, dio_oe_retreg_q; + + // Sleep entry trigger + assign sleep_trig = sleep_en_i & ~sleep_en_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_sleep + if (!rst_ni) begin + sleep_en_q <= 1'b0; + mio_out_retreg_q <= '0; + mio_oe_retreg_q <= '0; + dio_out_retreg_q <= '0; + dio_oe_retreg_q <= '0; + end else begin + sleep_en_q <= sleep_en_i; + + // MIOs + for (int k = 0; k < NMioPads; k++) begin + if (mio_sleep_trig[k]) begin + mio_out_retreg_q[k] <= mio_out_retreg_d[k]; + mio_oe_retreg_q[k] <= mio_oe_retreg_d[k]; + end + end + + // DIOs + for (int k = 0; k < NDioPads; k++) begin + if (dio_sleep_trig[k]) begin + dio_out_retreg_q[k] <= dio_out_retreg_d[k]; + dio_oe_retreg_q[k] <= dio_oe_retreg_d[k]; + end + end + end + end + + ///////////////////// + // MIO Input Muxes // + ///////////////////// + + localparam int AlignedMuxSize = (NMioPads + 2 > NDioPads) ? 2**$clog2(NMioPads + 2) : + 2**$clog2(NDioPads); + + // stack input and default signals for convenient indexing below possible defaults: + // constant 0 or 1. make sure mux is aligned to a power of 2 to avoid Xes. + logic [AlignedMuxSize-1:0] mio_mux; + assign mio_mux = AlignedMuxSize'({mio_in, 1'b1, 1'b0}); + + for (genvar k = 0; k < NMioPeriphIn; k++) begin : gen_mio_periph_in + // index using configured insel + assign mio_to_periph_o[k] = mio_mux[reg2hw.mio_periph_insel[k].q]; + end + + // For configurations with NMioPads + 2 < NDioPads, mio_in is zero-extended to NDioPads bits for + // convenience. However, mio_periph_insel is sized to select the lowest NMioPads + 2 bits. Most + // of the zero bits cannot actually be selected. Tie them off to avoid lint warnings. + logic unused_mio_mux; + assign unused_mio_mux = ^{mio_mux[(AlignedMuxSize - 1):(NMioPads + 2)]}; + + ////////////////////// + // MIO Output Muxes // + ////////////////////// + + // stack output data/enable and default signals for convenient indexing below + // possible defaults: 0, 1 or 2 (high-Z). make sure mux is aligned to a power of 2 to avoid Xes. + logic [2**$clog2(NMioPeriphOut+3)-1:0] periph_data_mux, periph_oe_mux; + assign periph_data_mux = $bits(periph_data_mux)'({periph_to_mio_i, 1'b0, 1'b1, 1'b0}); + assign periph_oe_mux = $bits(periph_oe_mux)'({periph_to_mio_oe_i, 1'b0, 1'b1, 1'b1}); + + for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_out + // Check individual sleep enable status bits + assign mio_out[k] = reg2hw.mio_pad_sleep_status[k].q ? + mio_out_retreg_q[k] : + periph_data_mux[reg2hw.mio_outsel[k].q]; + + assign mio_oe[k] = reg2hw.mio_pad_sleep_status[k].q ? + mio_oe_retreg_q[k] : + periph_oe_mux[reg2hw.mio_outsel[k].q]; + + // latch state when going to sleep + // 0: drive low + // 1: drive high + // 2: high-z + // 3: previous value + assign mio_out_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b0 : + (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : + (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_out[k]; + + assign mio_oe_retreg_d[k] = (reg2hw.mio_pad_sleep_mode[k].q == 0) ? 1'b1 : + (reg2hw.mio_pad_sleep_mode[k].q == 1) ? 1'b1 : + (reg2hw.mio_pad_sleep_mode[k].q == 2) ? 1'b0 : mio_oe[k]; + + // Activate sleep behavior only if it has been enabled + assign mio_sleep_trig[k] = reg2hw.mio_pad_sleep_en[k].q & sleep_trig; + assign hw2reg.mio_pad_sleep_status[k].d = 1'b1; + assign hw2reg.mio_pad_sleep_status[k].de = mio_sleep_trig[k]; + end + + ///////////////////// + // DIO connections // + ///////////////////// + + // Inputs are just fed through + assign dio_to_periph_o = dio_in; + + for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_out + // Check individual sleep enable status bits + assign dio_out[k] = reg2hw.dio_pad_sleep_status[k].q ? + dio_out_retreg_q[k] : + periph_to_dio_i[k]; + + assign dio_oe[k] = reg2hw.dio_pad_sleep_status[k].q ? + dio_oe_retreg_q[k] : + periph_to_dio_oe_i[k]; + + // latch state when going to sleep + // 0: drive low + // 1: drive high + // 2: high-z + // 3: previous value + assign dio_out_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b0 : + (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : + (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_out[k]; + + assign dio_oe_retreg_d[k] = (reg2hw.dio_pad_sleep_mode[k].q == 0) ? 1'b1 : + (reg2hw.dio_pad_sleep_mode[k].q == 1) ? 1'b1 : + (reg2hw.dio_pad_sleep_mode[k].q == 2) ? 1'b0 : dio_oe[k]; + + // Activate sleep behavior only if it has been enabled + assign dio_sleep_trig[k] = reg2hw.dio_pad_sleep_en[k].q & sleep_trig; + assign hw2reg.dio_pad_sleep_status[k].d = 1'b1; + assign hw2reg.dio_pad_sleep_status[k].de = dio_sleep_trig[k]; + end + + ////////////////////// + // Wakeup detectors // + ////////////////////// + + // Wakeup detectors should not be connected to the scan clock, so filter + // those inputs. + logic [NDioPads-1:0] dio_wkup_no_scan; + for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_wkup_filter + if (TargetCfg.dio_scan_role[k] == ScanClock) begin : gen_dio_scan + always_comb begin + dio_wkup_no_scan[k] = dio_in_i[k]; + if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin + dio_wkup_no_scan[k] = 1'b0; + end + end + end else begin : gen_no_dio_scan + assign dio_wkup_no_scan[k] = dio_in_i[k]; + end + end + + logic [NMioPads-1:0] mio_wkup_no_scan; + for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_wkup_filter + if (TargetCfg.mio_scan_role[k] == ScanClock) begin : gen_mio_scan + always_comb begin + mio_wkup_no_scan[k] = mio_in_i[k]; + if (prim_mubi_pkg::mubi4_test_true_strict(scanmode_i)) begin + mio_wkup_no_scan[k] = 1'b0; + end + end + end else begin : gen_no_mio_scan + assign mio_wkup_no_scan[k] = mio_in_i[k]; + end + end + + // Wakeup detector taps are not affected by JTAG/strap + // selection mux. I.e., we always sample the unmuxed inputs + // that come directly from the pads. + logic [AlignedMuxSize-1:0] dio_wkup_mux; + logic [AlignedMuxSize-1:0] mio_wkup_mux; + assign dio_wkup_mux = AlignedMuxSize'(dio_wkup_no_scan); + // The two constants that are concatenated here make sure tha the selection + // indices used to index this array are the same as the ones used to index + // the mio_mux array above, where positions 0 and 1 select constant 0 and + // 1, respectively. + assign mio_wkup_mux = AlignedMuxSize'({mio_wkup_no_scan, 1'b1, 1'b0}); + + logic [NWkupDetect-1:0] aon_wkup_req; + for (genvar k = 0; k < NWkupDetect; k++) begin : gen_wkup_detect + logic pin_value; + assign pin_value = (reg2hw.wkup_detector[k].miodio.q) ? + dio_wkup_mux[reg2hw.wkup_detector_padsel[k]] : + mio_wkup_mux[reg2hw.wkup_detector_padsel[k]]; + + // This module runs on the AON clock entirely + pinmux_wkup u_pinmux_wkup ( + .clk_i (clk_aon_i ), + .rst_ni (rst_aon_ni ), + // config signals have already been synced to the AON domain inside the CSR node. + .wkup_en_i ( reg2hw.wkup_detector_en[k].q ), + .filter_en_i ( reg2hw.wkup_detector[k].filter.q ), + .wkup_mode_i ( wkup_mode_e'(reg2hw.wkup_detector[k].mode.q) ), + .wkup_cnt_th_i ( reg2hw.wkup_detector_cnt_th[k].q ), + .pin_value_i ( pin_value ), + // wakeup request pulse on clk_aon, will be synced back to the bus domain insie the CSR node. + .aon_wkup_pulse_o ( hw2reg.wkup_cause[k].de ) + ); + + assign hw2reg.wkup_cause[k].d = 1'b1; + + // This is the latched wakeup request, hence this request signal is level encoded. + assign aon_wkup_req[k] = reg2hw.wkup_cause[k].q; + end + + // OR' together all wakeup requests + assign pin_wkup_req_o = |aon_wkup_req; + + //////////////// + // Assertions // + //////////////// + + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o) + `ASSERT_KNOWN(MioOeKnownO_A, mio_oe_o) + `ASSERT_KNOWN(DioOeKnownO_A, dio_oe_o) + + `ASSERT_KNOWN(MioKnownO_A, mio_attr_o) + `ASSERT_KNOWN(DioKnownO_A, dio_attr_o) + + // running on slow AON clock + `ASSERT_KNOWN(AonWkupReqKnownO_A, pin_wkup_req_o, clk_aon_i, !rst_aon_ni) + + // The wakeup signal is not latched in the pwrmgr so must be held until acked by software + `ASSUME(PinmuxWkupStable_A, pin_wkup_req_o |=> pin_wkup_req_o || + $fell(|reg2hw.wkup_cause) && !sleep_en_i, clk_aon_i, !rst_aon_ni) + + // Some inputs at the chip-level may be forced to X in chip-level simulations. + // Therefore, we do not instantiate these assertions. + // `ASSERT_KNOWN(MioToPeriphKnownO_A, mio_to_periph_o) + // `ASSERT_KNOWN(DioToPeriphKnownO_A, dio_to_periph_o) + + // The assertions below are not instantiated for a similar reason as the assertions above. + // I.e., some IPs have pass-through paths, which may lead to X'es propagating + // from input to output. + // for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_known_if + // `ASSERT_KNOWN_IF(MioOutKnownO_A, mio_out_o[k], mio_oe_o[k]) + // end + // for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_known_if + // `ASSERT_KNOWN_IF(DioOutKnownO_A, dio_out_o[k], dio_oe_o[k]) + // end + + // Pinmux does not have a block-level DV environment, hence we add an FPV assertion to test this. + `ASSERT(FpvSecCmBusIntegrity_A, + $rose(u_reg.intg_err) + |-> + ##[0:`_SEC_CM_ALERT_MAX_CYC] (alert_tx_o[0].alert_p)) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) + +endmodule : pinmux diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_jtag_breakout.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_jtag_breakout.sv new file mode 100644 index 00000000000..2acba6ff740 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_jtag_breakout.sv @@ -0,0 +1,24 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module pinmux_jtag_breakout ( + input jtag_pkg::jtag_req_t req_i, + output jtag_pkg::jtag_rsp_t rsp_o, + + output logic tck_o, + output logic trst_no, + output logic tms_o, + output logic tdi_o, + input tdo_i, + input tdo_oe_i +); + + assign tck_o = req_i.tck; + assign trst_no = req_i.trst_n; + assign tms_o = req_i.tms; + assign tdi_o = req_i.tdi; + assign rsp_o.tdo = tdo_i; + assign rsp_o.tdo_oe = tdo_oe_i; + +endmodule : pinmux_jtag_breakout diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_jtag_buf.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_jtag_buf.sv new file mode 100644 index 00000000000..161a0cb4cbe --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_jtag_buf.sv @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module pinmux_jtag_buf ( + input jtag_pkg::jtag_req_t req_i, + output jtag_pkg::jtag_req_t req_o, + input jtag_pkg::jtag_rsp_t rsp_i, + output jtag_pkg::jtag_rsp_t rsp_o +); + + prim_clock_buf prim_clock_buf_tck ( + .clk_i(req_i.tck), + .clk_o(req_o.tck) + ); + prim_buf prim_buf_trst_n ( + .in_i (req_i.trst_n), + .out_o(req_o.trst_n) + ); + prim_buf prim_buf_tms ( + .in_i (req_i.tms), + .out_o(req_o.tms) + ); + prim_buf prim_buf_tdi ( + .in_i (req_i.tdi), + .out_o(req_o.tdi) + ); + prim_buf prim_buf_tdo ( + .in_i (rsp_i.tdo), + .out_o(rsp_o.tdo) + ); + prim_buf prim_buf_tdo_oe ( + .in_i (rsp_i.tdo_oe), + .out_o(rsp_o.tdo_oe) + ); + +endmodule : pinmux_jtag_buf diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_pkg.sv new file mode 100644 index 00000000000..d2df26f6c0c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_pkg.sv @@ -0,0 +1,78 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package pinmux_pkg; + + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; + + parameter int NumIOs = NMioPads + NDioPads; + parameter int NDFTStraps = 2; + parameter int NTapStraps = 2; + + // Since the target-specific top-levels often have slightly different debug signal positions, we + // need a way to pass this info from the target specific top-level into the pinmux logic. The + // datastructure below serves this purpose. Note that all the indices below are with respect to + // the concatenated {DIO, MIO} packed array. + typedef struct packed { + integer tck_idx; + integer tms_idx; + integer trst_idx; + integer tdi_idx; + integer tdo_idx; + integer tap_strap0_idx; + integer tap_strap1_idx; + integer dft_strap0_idx; + integer dft_strap1_idx; + integer usb_dp_idx; + integer usb_dn_idx; + integer usb_sense_idx; + pad_type_e [NDioPads-1:0] dio_pad_type; + pad_type_e [NMioPads-1:0] mio_pad_type; + scan_role_e [NDioPads-1:0] dio_scan_role; + scan_role_e [NMioPads-1:0] mio_scan_role; + } target_cfg_t; + + parameter target_cfg_t DefaultTargetCfg = '{ + tck_idx: 0, + tms_idx: 0, + trst_idx: 0, + tdi_idx: 0, + tdo_idx: 0, + tap_strap0_idx: 0, + tap_strap1_idx: 0, + dft_strap0_idx: 0, + dft_strap1_idx: 0, + usb_dp_idx: 0, + usb_dn_idx: 0, + usb_sense_idx: 0, + dio_pad_type: {NDioPads{BidirStd}}, + mio_pad_type: {NMioPads{BidirStd}}, + dio_scan_role: {NDioPads{NoScan}}, + mio_scan_role: {NMioPads{NoScan}} + }; + + // Wakeup Detector Modes + typedef enum logic [2:0] { + Posedge = 3'b000, + Negedge = 3'b001, + Edge = 3'b010, + HighTimed = 3'b011, + LowTimed = 3'b100 + } wkup_mode_e; + + // Interface with LC controller + typedef struct packed { + logic valid; + logic [NDFTStraps-1:0] straps; + } dft_strap_test_req_t; + + typedef enum logic [NTapStraps-1:0] { + FuncSel = 2'b00, + LcTapSel = 2'b01, + RvTapSel = 2'b10, + DftTapSel = 2'b11 + } tap_strap_t; + +endpackage : pinmux_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv new file mode 100644 index 00000000000..37db5111c0f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv @@ -0,0 +1,2752 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package pinmux_reg_pkg; + + // Param list + parameter int NMioPeriphIn = 4; + parameter int NMioPeriphOut = 5; + parameter int NMioPads = 12; + parameter int NDioPads = 73; + parameter int NWkupDetect = 8; + parameter int WkupCntWidth = 8; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int BlockAw = 11; + + // Number of registers for every interface + parameter int NumRegs = 503; + + // Alert indices + typedef enum int { + AlertFatalFaultIdx = 0 + } pinmux_alert_idx_t; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic q; + logic qe; + } pinmux_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic [3:0] q; + } pinmux_reg2hw_mio_periph_insel_mreg_t; + + typedef struct packed { + logic [2:0] q; + } pinmux_reg2hw_mio_outsel_mreg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + logic qe; + } drive_strength; + struct packed { + logic [1:0] q; + logic qe; + } slew_rate; + struct packed { + logic q; + logic qe; + } input_disable; + struct packed { + logic q; + logic qe; + } od_en; + struct packed { + logic q; + logic qe; + } schmitt_en; + struct packed { + logic q; + logic qe; + } keeper_en; + struct packed { + logic q; + logic qe; + } pull_select; + struct packed { + logic q; + logic qe; + } pull_en; + struct packed { + logic q; + logic qe; + } virtual_od_en; + struct packed { + logic q; + logic qe; + } invert; + } pinmux_reg2hw_mio_pad_attr_mreg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + logic qe; + } drive_strength; + struct packed { + logic [1:0] q; + logic qe; + } slew_rate; + struct packed { + logic q; + logic qe; + } input_disable; + struct packed { + logic q; + logic qe; + } od_en; + struct packed { + logic q; + logic qe; + } schmitt_en; + struct packed { + logic q; + logic qe; + } keeper_en; + struct packed { + logic q; + logic qe; + } pull_select; + struct packed { + logic q; + logic qe; + } pull_en; + struct packed { + logic q; + logic qe; + } virtual_od_en; + struct packed { + logic q; + logic qe; + } invert; + } pinmux_reg2hw_dio_pad_attr_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_mio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_mio_pad_sleep_en_mreg_t; + + typedef struct packed { + logic [1:0] q; + } pinmux_reg2hw_mio_pad_sleep_mode_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_dio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_dio_pad_sleep_en_mreg_t; + + typedef struct packed { + logic [1:0] q; + } pinmux_reg2hw_dio_pad_sleep_mode_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_wkup_detector_en_mreg_t; + + typedef struct packed { + struct packed { + logic q; + } miodio; + struct packed { + logic q; + } filter; + struct packed { + logic [2:0] q; + } mode; + } pinmux_reg2hw_wkup_detector_mreg_t; + + typedef struct packed { + logic [7:0] q; + } pinmux_reg2hw_wkup_detector_cnt_th_mreg_t; + + typedef struct packed { + logic [6:0] q; + } pinmux_reg2hw_wkup_detector_padsel_mreg_t; + + typedef struct packed { + logic q; + } pinmux_reg2hw_wkup_cause_mreg_t; + + typedef struct packed { + struct packed { + logic [3:0] d; + } drive_strength; + struct packed { + logic [1:0] d; + } slew_rate; + struct packed { + logic d; + } input_disable; + struct packed { + logic d; + } od_en; + struct packed { + logic d; + } schmitt_en; + struct packed { + logic d; + } keeper_en; + struct packed { + logic d; + } pull_select; + struct packed { + logic d; + } pull_en; + struct packed { + logic d; + } virtual_od_en; + struct packed { + logic d; + } invert; + } pinmux_hw2reg_mio_pad_attr_mreg_t; + + typedef struct packed { + struct packed { + logic [3:0] d; + } drive_strength; + struct packed { + logic [1:0] d; + } slew_rate; + struct packed { + logic d; + } input_disable; + struct packed { + logic d; + } od_en; + struct packed { + logic d; + } schmitt_en; + struct packed { + logic d; + } keeper_en; + struct packed { + logic d; + } pull_select; + struct packed { + logic d; + } pull_en; + struct packed { + logic d; + } virtual_od_en; + struct packed { + logic d; + } invert; + } pinmux_hw2reg_dio_pad_attr_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_mio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_dio_pad_sleep_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pinmux_hw2reg_wkup_cause_mreg_t; + + // Register -> HW type + typedef struct packed { + pinmux_reg2hw_alert_test_reg_t alert_test; // [2609:2608] + pinmux_reg2hw_mio_periph_insel_mreg_t [3:0] mio_periph_insel; // [2607:2592] + pinmux_reg2hw_mio_outsel_mreg_t [11:0] mio_outsel; // [2591:2556] + pinmux_reg2hw_mio_pad_attr_mreg_t [11:0] mio_pad_attr; // [2555:2268] + pinmux_reg2hw_dio_pad_attr_mreg_t [72:0] dio_pad_attr; // [2267:516] + pinmux_reg2hw_mio_pad_sleep_status_mreg_t [11:0] mio_pad_sleep_status; // [515:504] + pinmux_reg2hw_mio_pad_sleep_en_mreg_t [11:0] mio_pad_sleep_en; // [503:492] + pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [11:0] mio_pad_sleep_mode; // [491:468] + pinmux_reg2hw_dio_pad_sleep_status_mreg_t [72:0] dio_pad_sleep_status; // [467:395] + pinmux_reg2hw_dio_pad_sleep_en_mreg_t [72:0] dio_pad_sleep_en; // [394:322] + pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [72:0] dio_pad_sleep_mode; // [321:176] + pinmux_reg2hw_wkup_detector_en_mreg_t [7:0] wkup_detector_en; // [175:168] + pinmux_reg2hw_wkup_detector_mreg_t [7:0] wkup_detector; // [167:128] + pinmux_reg2hw_wkup_detector_cnt_th_mreg_t [7:0] wkup_detector_cnt_th; // [127:64] + pinmux_reg2hw_wkup_detector_padsel_mreg_t [7:0] wkup_detector_padsel; // [63:8] + pinmux_reg2hw_wkup_cause_mreg_t [7:0] wkup_cause; // [7:0] + } pinmux_reg2hw_t; + + // HW -> register type + typedef struct packed { + pinmux_hw2reg_mio_pad_attr_mreg_t [11:0] mio_pad_attr; // [1375:1208] + pinmux_hw2reg_dio_pad_attr_mreg_t [72:0] dio_pad_attr; // [1207:186] + pinmux_hw2reg_mio_pad_sleep_status_mreg_t [11:0] mio_pad_sleep_status; // [185:162] + pinmux_hw2reg_dio_pad_sleep_status_mreg_t [72:0] dio_pad_sleep_status; // [161:16] + pinmux_hw2reg_wkup_cause_mreg_t [7:0] wkup_cause; // [15:0] + } pinmux_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] PINMUX_ALERT_TEST_OFFSET = 11'h 0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET = 11'h 4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET = 11'h 8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET = 11'h c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET = 11'h 10; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 11'h 14; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 11'h 18; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 11'h 1c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 11'h 20; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 11'h 24; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 11'h 28; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 11'h 2c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 11'h 30; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 11'h 34; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 11'h 38; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 11'h 3c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 11'h 40; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 11'h 44; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 11'h 48; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 11'h 4c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 11'h 50; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 11'h 54; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 11'h 58; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 11'h 5c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 11'h 60; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 11'h 64; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 11'h 68; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 11'h 6c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 11'h 70; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 11'h 74; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 11'h 78; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 11'h 7c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 11'h 80; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 84; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 88; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 8c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 90; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 94; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 98; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 9c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 11'h b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 11'h b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 11'h bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 11'h c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 11'h c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 11'h c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 11'h cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 11'h d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 11'h d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 11'h d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 11'h dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 11'h e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 100; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 104; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 108; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 10c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 110; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 114; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 118; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 11c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 120; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET = 11'h 124; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET = 11'h 128; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET = 11'h 12c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET = 11'h 130; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET = 11'h 134; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET = 11'h 138; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET = 11'h 13c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET = 11'h 140; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_24_OFFSET = 11'h 144; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_25_OFFSET = 11'h 148; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_26_OFFSET = 11'h 14c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_27_OFFSET = 11'h 150; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_28_OFFSET = 11'h 154; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_29_OFFSET = 11'h 158; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_30_OFFSET = 11'h 15c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_31_OFFSET = 11'h 160; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_32_OFFSET = 11'h 164; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_33_OFFSET = 11'h 168; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_34_OFFSET = 11'h 16c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_35_OFFSET = 11'h 170; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_36_OFFSET = 11'h 174; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_37_OFFSET = 11'h 178; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_38_OFFSET = 11'h 17c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_39_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_40_OFFSET = 11'h 184; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_41_OFFSET = 11'h 188; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_42_OFFSET = 11'h 18c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_43_OFFSET = 11'h 190; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_44_OFFSET = 11'h 194; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_45_OFFSET = 11'h 198; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_46_OFFSET = 11'h 19c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_47_OFFSET = 11'h 1a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_48_OFFSET = 11'h 1a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_49_OFFSET = 11'h 1a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_50_OFFSET = 11'h 1ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_51_OFFSET = 11'h 1b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_52_OFFSET = 11'h 1b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_53_OFFSET = 11'h 1b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_54_OFFSET = 11'h 1bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_55_OFFSET = 11'h 1c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_56_OFFSET = 11'h 1c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_57_OFFSET = 11'h 1c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_58_OFFSET = 11'h 1cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_59_OFFSET = 11'h 1d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_60_OFFSET = 11'h 1d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_61_OFFSET = 11'h 1d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_62_OFFSET = 11'h 1dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_63_OFFSET = 11'h 1e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_64_OFFSET = 11'h 1e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_65_OFFSET = 11'h 1e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_66_OFFSET = 11'h 1ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_67_OFFSET = 11'h 1f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_68_OFFSET = 11'h 1f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_69_OFFSET = 11'h 1f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_70_OFFSET = 11'h 1fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_71_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_72_OFFSET = 11'h 204; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 11'h 208; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 11'h 20c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 11'h 210; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 11'h 214; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 11'h 218; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 11'h 21c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 11'h 220; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 11'h 224; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 11'h 228; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 11'h 22c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 11'h 230; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 11'h 234; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 11'h 238; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 11'h 23c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 11'h 240; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 11'h 244; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_16_OFFSET = 11'h 248; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_17_OFFSET = 11'h 24c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_18_OFFSET = 11'h 250; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_19_OFFSET = 11'h 254; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_20_OFFSET = 11'h 258; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_21_OFFSET = 11'h 25c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_22_OFFSET = 11'h 260; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_23_OFFSET = 11'h 264; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_24_OFFSET = 11'h 268; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_25_OFFSET = 11'h 26c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_26_OFFSET = 11'h 270; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_27_OFFSET = 11'h 274; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_28_OFFSET = 11'h 278; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_29_OFFSET = 11'h 27c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_30_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_31_OFFSET = 11'h 284; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_32_OFFSET = 11'h 288; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_33_OFFSET = 11'h 28c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_34_OFFSET = 11'h 290; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_35_OFFSET = 11'h 294; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_36_OFFSET = 11'h 298; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_37_OFFSET = 11'h 29c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_38_OFFSET = 11'h 2a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_39_OFFSET = 11'h 2a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_40_OFFSET = 11'h 2a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_41_OFFSET = 11'h 2ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_42_OFFSET = 11'h 2b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_43_OFFSET = 11'h 2b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_44_OFFSET = 11'h 2b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_45_OFFSET = 11'h 2bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_46_OFFSET = 11'h 2c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_47_OFFSET = 11'h 2c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_48_OFFSET = 11'h 2c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_49_OFFSET = 11'h 2cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_50_OFFSET = 11'h 2d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_51_OFFSET = 11'h 2d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_52_OFFSET = 11'h 2d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_53_OFFSET = 11'h 2dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_54_OFFSET = 11'h 2e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_55_OFFSET = 11'h 2e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_56_OFFSET = 11'h 2e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_57_OFFSET = 11'h 2ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_58_OFFSET = 11'h 2f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_59_OFFSET = 11'h 2f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_60_OFFSET = 11'h 2f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_61_OFFSET = 11'h 2fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_62_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_63_OFFSET = 11'h 304; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_64_OFFSET = 11'h 308; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_65_OFFSET = 11'h 30c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_66_OFFSET = 11'h 310; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_67_OFFSET = 11'h 314; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_68_OFFSET = 11'h 318; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_69_OFFSET = 11'h 31c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_70_OFFSET = 11'h 320; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_71_OFFSET = 11'h 324; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_72_OFFSET = 11'h 328; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET = 11'h 32c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 330; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 334; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 338; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 33c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 340; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 344; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 348; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 34c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 350; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 354; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 358; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 35c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 11'h 360; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 11'h 364; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 11'h 368; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 11'h 36c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 11'h 370; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 11'h 374; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 11'h 378; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 11'h 37c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 11'h 384; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 11'h 388; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 11'h 38c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 390; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 394; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 398; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 39c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 3a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 3a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 3a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 3ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 3b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 3b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 3b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 3bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_0_OFFSET = 11'h 3c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_1_OFFSET = 11'h 3c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_2_OFFSET = 11'h 3c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 3cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 3d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 3d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 3d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 3dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 3e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 3e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 3e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 3ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 3f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 3f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 3f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 3fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 404; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 408; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET = 11'h 40c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET = 11'h 410; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET = 11'h 414; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET = 11'h 418; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET = 11'h 41c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET = 11'h 420; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET = 11'h 424; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET = 11'h 428; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_24_OFFSET = 11'h 42c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_25_OFFSET = 11'h 430; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_26_OFFSET = 11'h 434; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_27_OFFSET = 11'h 438; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_28_OFFSET = 11'h 43c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_29_OFFSET = 11'h 440; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_30_OFFSET = 11'h 444; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_31_OFFSET = 11'h 448; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_32_OFFSET = 11'h 44c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_33_OFFSET = 11'h 450; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_34_OFFSET = 11'h 454; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_35_OFFSET = 11'h 458; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_36_OFFSET = 11'h 45c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_37_OFFSET = 11'h 460; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_38_OFFSET = 11'h 464; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_39_OFFSET = 11'h 468; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_40_OFFSET = 11'h 46c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_41_OFFSET = 11'h 470; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_42_OFFSET = 11'h 474; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_43_OFFSET = 11'h 478; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_44_OFFSET = 11'h 47c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_45_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_46_OFFSET = 11'h 484; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_47_OFFSET = 11'h 488; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_48_OFFSET = 11'h 48c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_49_OFFSET = 11'h 490; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_50_OFFSET = 11'h 494; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_51_OFFSET = 11'h 498; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_52_OFFSET = 11'h 49c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_53_OFFSET = 11'h 4a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_54_OFFSET = 11'h 4a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_55_OFFSET = 11'h 4a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_56_OFFSET = 11'h 4ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_57_OFFSET = 11'h 4b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_58_OFFSET = 11'h 4b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_59_OFFSET = 11'h 4b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_60_OFFSET = 11'h 4bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_61_OFFSET = 11'h 4c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_62_OFFSET = 11'h 4c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_63_OFFSET = 11'h 4c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_64_OFFSET = 11'h 4cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_65_OFFSET = 11'h 4d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_66_OFFSET = 11'h 4d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_67_OFFSET = 11'h 4d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_68_OFFSET = 11'h 4dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_69_OFFSET = 11'h 4e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_70_OFFSET = 11'h 4e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_71_OFFSET = 11'h 4e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_72_OFFSET = 11'h 4ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 11'h 4f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 11'h 4f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 11'h 4f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 11'h 4fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 11'h 504; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 11'h 508; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 11'h 50c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 11'h 510; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 11'h 514; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 11'h 518; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 11'h 51c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 11'h 520; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 11'h 524; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 11'h 528; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 11'h 52c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET = 11'h 530; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET = 11'h 534; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET = 11'h 538; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET = 11'h 53c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET = 11'h 540; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET = 11'h 544; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET = 11'h 548; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET = 11'h 54c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_24_OFFSET = 11'h 550; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_25_OFFSET = 11'h 554; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_26_OFFSET = 11'h 558; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_27_OFFSET = 11'h 55c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_28_OFFSET = 11'h 560; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_29_OFFSET = 11'h 564; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_30_OFFSET = 11'h 568; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_31_OFFSET = 11'h 56c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_32_OFFSET = 11'h 570; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_33_OFFSET = 11'h 574; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_34_OFFSET = 11'h 578; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_35_OFFSET = 11'h 57c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_36_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_37_OFFSET = 11'h 584; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_38_OFFSET = 11'h 588; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_39_OFFSET = 11'h 58c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_40_OFFSET = 11'h 590; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_41_OFFSET = 11'h 594; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_42_OFFSET = 11'h 598; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_43_OFFSET = 11'h 59c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_44_OFFSET = 11'h 5a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_45_OFFSET = 11'h 5a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_46_OFFSET = 11'h 5a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_47_OFFSET = 11'h 5ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_48_OFFSET = 11'h 5b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_49_OFFSET = 11'h 5b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_50_OFFSET = 11'h 5b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_51_OFFSET = 11'h 5bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_52_OFFSET = 11'h 5c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_53_OFFSET = 11'h 5c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_54_OFFSET = 11'h 5c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_55_OFFSET = 11'h 5cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_56_OFFSET = 11'h 5d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_57_OFFSET = 11'h 5d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_58_OFFSET = 11'h 5d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_59_OFFSET = 11'h 5dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_60_OFFSET = 11'h 5e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_61_OFFSET = 11'h 5e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_62_OFFSET = 11'h 5e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_63_OFFSET = 11'h 5ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_64_OFFSET = 11'h 5f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_65_OFFSET = 11'h 5f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_66_OFFSET = 11'h 5f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_67_OFFSET = 11'h 5fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_68_OFFSET = 11'h 600; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_69_OFFSET = 11'h 604; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_70_OFFSET = 11'h 608; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_71_OFFSET = 11'h 60c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_72_OFFSET = 11'h 610; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 614; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 618; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 61c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 620; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 624; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 628; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 62c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 630; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 634; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 638; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 63c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 640; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 644; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 648; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 64c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 650; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET = 11'h 654; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET = 11'h 658; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET = 11'h 65c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET = 11'h 660; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET = 11'h 664; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET = 11'h 668; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET = 11'h 66c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET = 11'h 670; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_24_OFFSET = 11'h 674; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_25_OFFSET = 11'h 678; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_26_OFFSET = 11'h 67c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_27_OFFSET = 11'h 680; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_28_OFFSET = 11'h 684; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_29_OFFSET = 11'h 688; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_30_OFFSET = 11'h 68c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_31_OFFSET = 11'h 690; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_32_OFFSET = 11'h 694; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_33_OFFSET = 11'h 698; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_34_OFFSET = 11'h 69c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_35_OFFSET = 11'h 6a0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_36_OFFSET = 11'h 6a4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_37_OFFSET = 11'h 6a8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_38_OFFSET = 11'h 6ac; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_39_OFFSET = 11'h 6b0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_40_OFFSET = 11'h 6b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_41_OFFSET = 11'h 6b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_42_OFFSET = 11'h 6bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_43_OFFSET = 11'h 6c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_44_OFFSET = 11'h 6c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_45_OFFSET = 11'h 6c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_46_OFFSET = 11'h 6cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_47_OFFSET = 11'h 6d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_48_OFFSET = 11'h 6d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_49_OFFSET = 11'h 6d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_50_OFFSET = 11'h 6dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_51_OFFSET = 11'h 6e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_52_OFFSET = 11'h 6e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_53_OFFSET = 11'h 6e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_54_OFFSET = 11'h 6ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_55_OFFSET = 11'h 6f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_56_OFFSET = 11'h 6f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_57_OFFSET = 11'h 6f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_58_OFFSET = 11'h 6fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_59_OFFSET = 11'h 700; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_60_OFFSET = 11'h 704; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_61_OFFSET = 11'h 708; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_62_OFFSET = 11'h 70c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_63_OFFSET = 11'h 710; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_64_OFFSET = 11'h 714; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_65_OFFSET = 11'h 718; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_66_OFFSET = 11'h 71c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_67_OFFSET = 11'h 720; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_68_OFFSET = 11'h 724; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_69_OFFSET = 11'h 728; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_70_OFFSET = 11'h 72c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_71_OFFSET = 11'h 730; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_72_OFFSET = 11'h 734; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 738; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 73c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 740; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 744; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 748; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 74c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 750; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 754; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 758; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 75c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 760; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 764; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 768; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 76c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 770; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 774; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 778; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 77c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 780; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 784; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 788; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 78c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 790; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 794; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 798; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 79c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 7a0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 7a4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 7a8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 7ac; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 7b0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 7b4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 7b8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 7bc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 7c0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 7c4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 7c8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 7cc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 7d0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 7d4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 7d8; + + // Reset values for hwext registers and their fields + parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_0_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_INVERT_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_KEEPER_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_SCHMITT_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_OD_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_0_INPUT_DISABLE_0_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_1_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_INVERT_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_SCHMITT_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_OD_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_1_INPUT_DISABLE_1_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_2_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_INVERT_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_PULL_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_PULL_SELECT_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_KEEPER_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_SCHMITT_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_OD_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_2_INPUT_DISABLE_2_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_3_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_INVERT_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_PULL_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_PULL_SELECT_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_KEEPER_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_SCHMITT_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_OD_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_3_INPUT_DISABLE_3_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_4_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_INVERT_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_PULL_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_PULL_SELECT_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_KEEPER_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_SCHMITT_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_OD_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_4_INPUT_DISABLE_4_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_5_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_INVERT_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_PULL_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_PULL_SELECT_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_KEEPER_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_SCHMITT_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_OD_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_5_INPUT_DISABLE_5_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_6_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_INVERT_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_PULL_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_PULL_SELECT_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_KEEPER_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_SCHMITT_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_OD_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_6_INPUT_DISABLE_6_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_7_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_INVERT_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_PULL_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_PULL_SELECT_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_KEEPER_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_SCHMITT_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_OD_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_7_INPUT_DISABLE_7_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_8_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_INVERT_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_PULL_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_PULL_SELECT_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_KEEPER_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_SCHMITT_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_OD_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_8_INPUT_DISABLE_8_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_9_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_INVERT_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_PULL_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_PULL_SELECT_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_KEEPER_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_SCHMITT_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_OD_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_9_INPUT_DISABLE_9_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_10_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_INVERT_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_PULL_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_PULL_SELECT_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_KEEPER_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_SCHMITT_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_OD_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_10_INPUT_DISABLE_10_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_MIO_PAD_ATTR_11_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_INVERT_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_PULL_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_PULL_SELECT_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_KEEPER_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_SCHMITT_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_OD_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_MIO_PAD_ATTR_11_INPUT_DISABLE_11_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_0_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_INVERT_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_PULL_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_KEEPER_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_SCHMITT_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_OD_EN_0_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_0_INPUT_DISABLE_0_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_1_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_INVERT_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_PULL_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_PULL_SELECT_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_KEEPER_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_SCHMITT_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_OD_EN_1_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_1_INPUT_DISABLE_1_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_2_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_INVERT_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_PULL_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_PULL_SELECT_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_KEEPER_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_SCHMITT_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_OD_EN_2_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_2_INPUT_DISABLE_2_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_3_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_INVERT_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_KEEPER_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_SCHMITT_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_OD_EN_3_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_3_INPUT_DISABLE_3_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_4_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_INVERT_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_PULL_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_PULL_SELECT_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_KEEPER_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_SCHMITT_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_OD_EN_4_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_4_INPUT_DISABLE_4_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_5_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_INVERT_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_PULL_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_PULL_SELECT_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_KEEPER_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_SCHMITT_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_OD_EN_5_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_5_INPUT_DISABLE_5_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_6_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_INVERT_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_PULL_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_PULL_SELECT_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_KEEPER_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_SCHMITT_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_OD_EN_6_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_6_INPUT_DISABLE_6_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_7_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_INVERT_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_PULL_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_PULL_SELECT_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_KEEPER_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_SCHMITT_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_OD_EN_7_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_7_INPUT_DISABLE_7_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_8_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_INVERT_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_PULL_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_PULL_SELECT_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_KEEPER_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_SCHMITT_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_OD_EN_8_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_8_INPUT_DISABLE_8_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_9_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_INVERT_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_PULL_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_PULL_SELECT_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_KEEPER_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_SCHMITT_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_OD_EN_9_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_9_INPUT_DISABLE_9_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_10_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_INVERT_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_PULL_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_PULL_SELECT_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_KEEPER_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_SCHMITT_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_OD_EN_10_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_10_INPUT_DISABLE_10_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_11_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_INVERT_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_PULL_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_PULL_SELECT_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_KEEPER_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_SCHMITT_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_OD_EN_11_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_11_INPUT_DISABLE_11_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_12_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_INVERT_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_PULL_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_PULL_SELECT_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_KEEPER_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_SCHMITT_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_OD_EN_12_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_12_INPUT_DISABLE_12_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_13_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_INVERT_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_PULL_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_PULL_SELECT_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_KEEPER_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_SCHMITT_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_OD_EN_13_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_13_INPUT_DISABLE_13_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_14_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_INVERT_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_PULL_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_PULL_SELECT_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_KEEPER_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_SCHMITT_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_OD_EN_14_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_14_INPUT_DISABLE_14_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_15_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_INVERT_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_PULL_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_PULL_SELECT_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_KEEPER_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_SCHMITT_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_OD_EN_15_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_15_INPUT_DISABLE_15_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_16_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_INVERT_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_VIRTUAL_OD_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_PULL_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_PULL_SELECT_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_KEEPER_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_SCHMITT_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_OD_EN_16_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_16_INPUT_DISABLE_16_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_17_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_INVERT_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_VIRTUAL_OD_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_PULL_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_PULL_SELECT_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_KEEPER_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_SCHMITT_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_OD_EN_17_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_17_INPUT_DISABLE_17_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_18_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_INVERT_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_VIRTUAL_OD_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_PULL_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_PULL_SELECT_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_KEEPER_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_SCHMITT_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_OD_EN_18_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_18_INPUT_DISABLE_18_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_19_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_INVERT_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_VIRTUAL_OD_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_PULL_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_PULL_SELECT_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_KEEPER_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_SCHMITT_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_OD_EN_19_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_19_INPUT_DISABLE_19_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_20_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_INVERT_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_VIRTUAL_OD_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_PULL_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_PULL_SELECT_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_KEEPER_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_SCHMITT_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_OD_EN_20_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_20_INPUT_DISABLE_20_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_21_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_INVERT_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_VIRTUAL_OD_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_PULL_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_PULL_SELECT_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_KEEPER_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_SCHMITT_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_OD_EN_21_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_21_INPUT_DISABLE_21_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_22_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_INVERT_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_VIRTUAL_OD_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_PULL_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_PULL_SELECT_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_KEEPER_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_SCHMITT_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_OD_EN_22_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_22_INPUT_DISABLE_22_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_23_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_INVERT_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_VIRTUAL_OD_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_PULL_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_PULL_SELECT_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_KEEPER_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_SCHMITT_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_OD_EN_23_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_23_INPUT_DISABLE_23_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_24_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_INVERT_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_VIRTUAL_OD_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_PULL_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_PULL_SELECT_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_KEEPER_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_SCHMITT_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_OD_EN_24_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_24_INPUT_DISABLE_24_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_25_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_INVERT_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_VIRTUAL_OD_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_PULL_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_PULL_SELECT_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_KEEPER_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_SCHMITT_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_OD_EN_25_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_25_INPUT_DISABLE_25_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_26_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_INVERT_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_VIRTUAL_OD_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_PULL_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_PULL_SELECT_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_KEEPER_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_SCHMITT_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_OD_EN_26_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_26_INPUT_DISABLE_26_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_27_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_INVERT_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_VIRTUAL_OD_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_PULL_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_PULL_SELECT_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_KEEPER_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_SCHMITT_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_OD_EN_27_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_27_INPUT_DISABLE_27_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_28_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_INVERT_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_VIRTUAL_OD_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_PULL_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_PULL_SELECT_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_KEEPER_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_SCHMITT_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_OD_EN_28_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_28_INPUT_DISABLE_28_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_29_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_INVERT_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_VIRTUAL_OD_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_PULL_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_PULL_SELECT_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_KEEPER_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_SCHMITT_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_OD_EN_29_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_29_INPUT_DISABLE_29_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_30_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_INVERT_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_VIRTUAL_OD_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_PULL_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_PULL_SELECT_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_KEEPER_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_SCHMITT_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_OD_EN_30_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_30_INPUT_DISABLE_30_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_31_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_INVERT_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_VIRTUAL_OD_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_PULL_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_PULL_SELECT_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_KEEPER_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_SCHMITT_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_OD_EN_31_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_31_INPUT_DISABLE_31_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_32_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_INVERT_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_VIRTUAL_OD_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_PULL_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_PULL_SELECT_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_KEEPER_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_SCHMITT_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_OD_EN_32_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_32_INPUT_DISABLE_32_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_33_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_INVERT_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_VIRTUAL_OD_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_PULL_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_PULL_SELECT_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_KEEPER_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_SCHMITT_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_OD_EN_33_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_33_INPUT_DISABLE_33_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_34_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_INVERT_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_VIRTUAL_OD_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_PULL_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_PULL_SELECT_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_KEEPER_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_SCHMITT_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_OD_EN_34_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_34_INPUT_DISABLE_34_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_35_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_INVERT_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_VIRTUAL_OD_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_PULL_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_PULL_SELECT_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_KEEPER_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_SCHMITT_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_OD_EN_35_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_35_INPUT_DISABLE_35_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_36_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_INVERT_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_VIRTUAL_OD_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_PULL_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_PULL_SELECT_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_KEEPER_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_SCHMITT_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_OD_EN_36_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_36_INPUT_DISABLE_36_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_37_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_INVERT_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_PULL_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_PULL_SELECT_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_KEEPER_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_SCHMITT_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_OD_EN_37_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_37_INPUT_DISABLE_37_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_38_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_INVERT_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_PULL_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_PULL_SELECT_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_KEEPER_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_SCHMITT_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_OD_EN_38_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_38_INPUT_DISABLE_38_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_39_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_INVERT_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_PULL_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_PULL_SELECT_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_KEEPER_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_SCHMITT_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_OD_EN_39_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_39_INPUT_DISABLE_39_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_40_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_INVERT_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_PULL_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_PULL_SELECT_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_KEEPER_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_SCHMITT_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_OD_EN_40_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_40_INPUT_DISABLE_40_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_41_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_INVERT_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_PULL_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_PULL_SELECT_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_KEEPER_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_SCHMITT_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_OD_EN_41_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_41_INPUT_DISABLE_41_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_42_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_INVERT_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_PULL_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_PULL_SELECT_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_KEEPER_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_SCHMITT_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_OD_EN_42_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_42_INPUT_DISABLE_42_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_43_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_INVERT_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_VIRTUAL_OD_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_PULL_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_PULL_SELECT_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_KEEPER_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_SCHMITT_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_OD_EN_43_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_43_INPUT_DISABLE_43_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_44_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_INVERT_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_VIRTUAL_OD_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_PULL_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_PULL_SELECT_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_KEEPER_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_SCHMITT_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_OD_EN_44_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_44_INPUT_DISABLE_44_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_45_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_INVERT_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_VIRTUAL_OD_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_PULL_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_PULL_SELECT_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_KEEPER_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_SCHMITT_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_OD_EN_45_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_45_INPUT_DISABLE_45_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_46_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_INVERT_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_VIRTUAL_OD_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_PULL_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_PULL_SELECT_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_KEEPER_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_SCHMITT_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_OD_EN_46_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_46_INPUT_DISABLE_46_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_47_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_INVERT_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_VIRTUAL_OD_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_PULL_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_PULL_SELECT_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_KEEPER_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_SCHMITT_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_OD_EN_47_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_47_INPUT_DISABLE_47_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_48_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_INVERT_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_VIRTUAL_OD_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_PULL_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_PULL_SELECT_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_KEEPER_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_SCHMITT_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_OD_EN_48_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_48_INPUT_DISABLE_48_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_49_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_INVERT_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_VIRTUAL_OD_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_PULL_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_PULL_SELECT_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_KEEPER_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_SCHMITT_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_OD_EN_49_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_49_INPUT_DISABLE_49_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_50_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_INVERT_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_VIRTUAL_OD_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_PULL_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_PULL_SELECT_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_KEEPER_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_SCHMITT_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_OD_EN_50_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_50_INPUT_DISABLE_50_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_51_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_INVERT_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_VIRTUAL_OD_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_PULL_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_PULL_SELECT_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_KEEPER_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_SCHMITT_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_OD_EN_51_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_51_INPUT_DISABLE_51_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_52_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_INVERT_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_VIRTUAL_OD_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_PULL_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_PULL_SELECT_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_KEEPER_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_SCHMITT_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_OD_EN_52_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_52_INPUT_DISABLE_52_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_53_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_INVERT_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_VIRTUAL_OD_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_PULL_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_PULL_SELECT_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_KEEPER_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_SCHMITT_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_OD_EN_53_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_53_INPUT_DISABLE_53_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_54_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_INVERT_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_VIRTUAL_OD_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_PULL_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_PULL_SELECT_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_KEEPER_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_SCHMITT_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_OD_EN_54_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_54_INPUT_DISABLE_54_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_55_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_INVERT_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_VIRTUAL_OD_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_PULL_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_PULL_SELECT_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_KEEPER_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_SCHMITT_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_OD_EN_55_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_55_INPUT_DISABLE_55_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_56_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_INVERT_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_VIRTUAL_OD_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_PULL_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_PULL_SELECT_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_KEEPER_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_SCHMITT_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_OD_EN_56_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_56_INPUT_DISABLE_56_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_57_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_INVERT_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_VIRTUAL_OD_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_PULL_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_PULL_SELECT_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_KEEPER_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_SCHMITT_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_OD_EN_57_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_57_INPUT_DISABLE_57_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_58_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_INVERT_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_VIRTUAL_OD_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_PULL_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_PULL_SELECT_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_KEEPER_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_SCHMITT_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_OD_EN_58_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_58_INPUT_DISABLE_58_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_59_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_INVERT_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_VIRTUAL_OD_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_PULL_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_PULL_SELECT_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_KEEPER_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_SCHMITT_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_OD_EN_59_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_59_INPUT_DISABLE_59_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_60_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_INVERT_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_VIRTUAL_OD_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_PULL_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_PULL_SELECT_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_KEEPER_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_SCHMITT_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_OD_EN_60_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_60_INPUT_DISABLE_60_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_61_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_INVERT_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_VIRTUAL_OD_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_PULL_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_PULL_SELECT_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_KEEPER_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_SCHMITT_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_OD_EN_61_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_61_INPUT_DISABLE_61_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_62_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_INVERT_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_VIRTUAL_OD_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_PULL_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_PULL_SELECT_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_KEEPER_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_SCHMITT_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_OD_EN_62_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_62_INPUT_DISABLE_62_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_63_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_INVERT_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_VIRTUAL_OD_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_PULL_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_PULL_SELECT_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_KEEPER_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_SCHMITT_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_OD_EN_63_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_63_INPUT_DISABLE_63_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_64_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_INVERT_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_VIRTUAL_OD_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_PULL_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_PULL_SELECT_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_KEEPER_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_SCHMITT_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_OD_EN_64_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_64_INPUT_DISABLE_64_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_65_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_INVERT_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_VIRTUAL_OD_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_PULL_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_PULL_SELECT_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_KEEPER_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_SCHMITT_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_OD_EN_65_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_65_INPUT_DISABLE_65_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_66_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_INVERT_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_VIRTUAL_OD_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_PULL_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_PULL_SELECT_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_KEEPER_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_SCHMITT_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_OD_EN_66_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_66_INPUT_DISABLE_66_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_67_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_INVERT_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_VIRTUAL_OD_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_PULL_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_PULL_SELECT_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_KEEPER_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_SCHMITT_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_OD_EN_67_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_67_INPUT_DISABLE_67_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_68_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_INVERT_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_VIRTUAL_OD_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_PULL_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_PULL_SELECT_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_KEEPER_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_SCHMITT_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_OD_EN_68_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_68_INPUT_DISABLE_68_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_69_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_INVERT_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_VIRTUAL_OD_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_PULL_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_PULL_SELECT_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_KEEPER_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_SCHMITT_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_OD_EN_69_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_69_INPUT_DISABLE_69_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_70_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_INVERT_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_VIRTUAL_OD_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_PULL_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_PULL_SELECT_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_KEEPER_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_SCHMITT_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_OD_EN_70_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_70_INPUT_DISABLE_70_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_71_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_INVERT_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_VIRTUAL_OD_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_PULL_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_PULL_SELECT_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_KEEPER_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_SCHMITT_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_OD_EN_71_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_71_INPUT_DISABLE_71_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_RESVAL = 4'h 0; + parameter logic [23:0] PINMUX_DIO_PAD_ATTR_72_RESVAL = 24'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_INVERT_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_VIRTUAL_OD_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_PULL_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_PULL_SELECT_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_KEEPER_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_SCHMITT_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_OD_EN_72_RESVAL = 1'h 0; + parameter logic [0:0] PINMUX_DIO_PAD_ATTR_72_INPUT_DISABLE_72_RESVAL = 1'h 0; + parameter logic [1:0] PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_RESVAL = 2'h 0; + parameter logic [3:0] PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_RESVAL = 4'h 0; + + // Register index + typedef enum int { + PINMUX_ALERT_TEST, + PINMUX_MIO_PERIPH_INSEL_REGWEN_0, + PINMUX_MIO_PERIPH_INSEL_REGWEN_1, + PINMUX_MIO_PERIPH_INSEL_REGWEN_2, + PINMUX_MIO_PERIPH_INSEL_REGWEN_3, + PINMUX_MIO_PERIPH_INSEL_0, + PINMUX_MIO_PERIPH_INSEL_1, + PINMUX_MIO_PERIPH_INSEL_2, + PINMUX_MIO_PERIPH_INSEL_3, + PINMUX_MIO_OUTSEL_REGWEN_0, + PINMUX_MIO_OUTSEL_REGWEN_1, + PINMUX_MIO_OUTSEL_REGWEN_2, + PINMUX_MIO_OUTSEL_REGWEN_3, + PINMUX_MIO_OUTSEL_REGWEN_4, + PINMUX_MIO_OUTSEL_REGWEN_5, + PINMUX_MIO_OUTSEL_REGWEN_6, + PINMUX_MIO_OUTSEL_REGWEN_7, + PINMUX_MIO_OUTSEL_REGWEN_8, + PINMUX_MIO_OUTSEL_REGWEN_9, + PINMUX_MIO_OUTSEL_REGWEN_10, + PINMUX_MIO_OUTSEL_REGWEN_11, + PINMUX_MIO_OUTSEL_0, + PINMUX_MIO_OUTSEL_1, + PINMUX_MIO_OUTSEL_2, + PINMUX_MIO_OUTSEL_3, + PINMUX_MIO_OUTSEL_4, + PINMUX_MIO_OUTSEL_5, + PINMUX_MIO_OUTSEL_6, + PINMUX_MIO_OUTSEL_7, + PINMUX_MIO_OUTSEL_8, + PINMUX_MIO_OUTSEL_9, + PINMUX_MIO_OUTSEL_10, + PINMUX_MIO_OUTSEL_11, + PINMUX_MIO_PAD_ATTR_REGWEN_0, + PINMUX_MIO_PAD_ATTR_REGWEN_1, + PINMUX_MIO_PAD_ATTR_REGWEN_2, + PINMUX_MIO_PAD_ATTR_REGWEN_3, + PINMUX_MIO_PAD_ATTR_REGWEN_4, + PINMUX_MIO_PAD_ATTR_REGWEN_5, + PINMUX_MIO_PAD_ATTR_REGWEN_6, + PINMUX_MIO_PAD_ATTR_REGWEN_7, + PINMUX_MIO_PAD_ATTR_REGWEN_8, + PINMUX_MIO_PAD_ATTR_REGWEN_9, + PINMUX_MIO_PAD_ATTR_REGWEN_10, + PINMUX_MIO_PAD_ATTR_REGWEN_11, + PINMUX_MIO_PAD_ATTR_0, + PINMUX_MIO_PAD_ATTR_1, + PINMUX_MIO_PAD_ATTR_2, + PINMUX_MIO_PAD_ATTR_3, + PINMUX_MIO_PAD_ATTR_4, + PINMUX_MIO_PAD_ATTR_5, + PINMUX_MIO_PAD_ATTR_6, + PINMUX_MIO_PAD_ATTR_7, + PINMUX_MIO_PAD_ATTR_8, + PINMUX_MIO_PAD_ATTR_9, + PINMUX_MIO_PAD_ATTR_10, + PINMUX_MIO_PAD_ATTR_11, + PINMUX_DIO_PAD_ATTR_REGWEN_0, + PINMUX_DIO_PAD_ATTR_REGWEN_1, + PINMUX_DIO_PAD_ATTR_REGWEN_2, + PINMUX_DIO_PAD_ATTR_REGWEN_3, + PINMUX_DIO_PAD_ATTR_REGWEN_4, + PINMUX_DIO_PAD_ATTR_REGWEN_5, + PINMUX_DIO_PAD_ATTR_REGWEN_6, + PINMUX_DIO_PAD_ATTR_REGWEN_7, + PINMUX_DIO_PAD_ATTR_REGWEN_8, + PINMUX_DIO_PAD_ATTR_REGWEN_9, + PINMUX_DIO_PAD_ATTR_REGWEN_10, + PINMUX_DIO_PAD_ATTR_REGWEN_11, + PINMUX_DIO_PAD_ATTR_REGWEN_12, + PINMUX_DIO_PAD_ATTR_REGWEN_13, + PINMUX_DIO_PAD_ATTR_REGWEN_14, + PINMUX_DIO_PAD_ATTR_REGWEN_15, + PINMUX_DIO_PAD_ATTR_REGWEN_16, + PINMUX_DIO_PAD_ATTR_REGWEN_17, + PINMUX_DIO_PAD_ATTR_REGWEN_18, + PINMUX_DIO_PAD_ATTR_REGWEN_19, + PINMUX_DIO_PAD_ATTR_REGWEN_20, + PINMUX_DIO_PAD_ATTR_REGWEN_21, + PINMUX_DIO_PAD_ATTR_REGWEN_22, + PINMUX_DIO_PAD_ATTR_REGWEN_23, + PINMUX_DIO_PAD_ATTR_REGWEN_24, + PINMUX_DIO_PAD_ATTR_REGWEN_25, + PINMUX_DIO_PAD_ATTR_REGWEN_26, + PINMUX_DIO_PAD_ATTR_REGWEN_27, + PINMUX_DIO_PAD_ATTR_REGWEN_28, + PINMUX_DIO_PAD_ATTR_REGWEN_29, + PINMUX_DIO_PAD_ATTR_REGWEN_30, + PINMUX_DIO_PAD_ATTR_REGWEN_31, + PINMUX_DIO_PAD_ATTR_REGWEN_32, + PINMUX_DIO_PAD_ATTR_REGWEN_33, + PINMUX_DIO_PAD_ATTR_REGWEN_34, + PINMUX_DIO_PAD_ATTR_REGWEN_35, + PINMUX_DIO_PAD_ATTR_REGWEN_36, + PINMUX_DIO_PAD_ATTR_REGWEN_37, + PINMUX_DIO_PAD_ATTR_REGWEN_38, + PINMUX_DIO_PAD_ATTR_REGWEN_39, + PINMUX_DIO_PAD_ATTR_REGWEN_40, + PINMUX_DIO_PAD_ATTR_REGWEN_41, + PINMUX_DIO_PAD_ATTR_REGWEN_42, + PINMUX_DIO_PAD_ATTR_REGWEN_43, + PINMUX_DIO_PAD_ATTR_REGWEN_44, + PINMUX_DIO_PAD_ATTR_REGWEN_45, + PINMUX_DIO_PAD_ATTR_REGWEN_46, + PINMUX_DIO_PAD_ATTR_REGWEN_47, + PINMUX_DIO_PAD_ATTR_REGWEN_48, + PINMUX_DIO_PAD_ATTR_REGWEN_49, + PINMUX_DIO_PAD_ATTR_REGWEN_50, + PINMUX_DIO_PAD_ATTR_REGWEN_51, + PINMUX_DIO_PAD_ATTR_REGWEN_52, + PINMUX_DIO_PAD_ATTR_REGWEN_53, + PINMUX_DIO_PAD_ATTR_REGWEN_54, + PINMUX_DIO_PAD_ATTR_REGWEN_55, + PINMUX_DIO_PAD_ATTR_REGWEN_56, + PINMUX_DIO_PAD_ATTR_REGWEN_57, + PINMUX_DIO_PAD_ATTR_REGWEN_58, + PINMUX_DIO_PAD_ATTR_REGWEN_59, + PINMUX_DIO_PAD_ATTR_REGWEN_60, + PINMUX_DIO_PAD_ATTR_REGWEN_61, + PINMUX_DIO_PAD_ATTR_REGWEN_62, + PINMUX_DIO_PAD_ATTR_REGWEN_63, + PINMUX_DIO_PAD_ATTR_REGWEN_64, + PINMUX_DIO_PAD_ATTR_REGWEN_65, + PINMUX_DIO_PAD_ATTR_REGWEN_66, + PINMUX_DIO_PAD_ATTR_REGWEN_67, + PINMUX_DIO_PAD_ATTR_REGWEN_68, + PINMUX_DIO_PAD_ATTR_REGWEN_69, + PINMUX_DIO_PAD_ATTR_REGWEN_70, + PINMUX_DIO_PAD_ATTR_REGWEN_71, + PINMUX_DIO_PAD_ATTR_REGWEN_72, + PINMUX_DIO_PAD_ATTR_0, + PINMUX_DIO_PAD_ATTR_1, + PINMUX_DIO_PAD_ATTR_2, + PINMUX_DIO_PAD_ATTR_3, + PINMUX_DIO_PAD_ATTR_4, + PINMUX_DIO_PAD_ATTR_5, + PINMUX_DIO_PAD_ATTR_6, + PINMUX_DIO_PAD_ATTR_7, + PINMUX_DIO_PAD_ATTR_8, + PINMUX_DIO_PAD_ATTR_9, + PINMUX_DIO_PAD_ATTR_10, + PINMUX_DIO_PAD_ATTR_11, + PINMUX_DIO_PAD_ATTR_12, + PINMUX_DIO_PAD_ATTR_13, + PINMUX_DIO_PAD_ATTR_14, + PINMUX_DIO_PAD_ATTR_15, + PINMUX_DIO_PAD_ATTR_16, + PINMUX_DIO_PAD_ATTR_17, + PINMUX_DIO_PAD_ATTR_18, + PINMUX_DIO_PAD_ATTR_19, + PINMUX_DIO_PAD_ATTR_20, + PINMUX_DIO_PAD_ATTR_21, + PINMUX_DIO_PAD_ATTR_22, + PINMUX_DIO_PAD_ATTR_23, + PINMUX_DIO_PAD_ATTR_24, + PINMUX_DIO_PAD_ATTR_25, + PINMUX_DIO_PAD_ATTR_26, + PINMUX_DIO_PAD_ATTR_27, + PINMUX_DIO_PAD_ATTR_28, + PINMUX_DIO_PAD_ATTR_29, + PINMUX_DIO_PAD_ATTR_30, + PINMUX_DIO_PAD_ATTR_31, + PINMUX_DIO_PAD_ATTR_32, + PINMUX_DIO_PAD_ATTR_33, + PINMUX_DIO_PAD_ATTR_34, + PINMUX_DIO_PAD_ATTR_35, + PINMUX_DIO_PAD_ATTR_36, + PINMUX_DIO_PAD_ATTR_37, + PINMUX_DIO_PAD_ATTR_38, + PINMUX_DIO_PAD_ATTR_39, + PINMUX_DIO_PAD_ATTR_40, + PINMUX_DIO_PAD_ATTR_41, + PINMUX_DIO_PAD_ATTR_42, + PINMUX_DIO_PAD_ATTR_43, + PINMUX_DIO_PAD_ATTR_44, + PINMUX_DIO_PAD_ATTR_45, + PINMUX_DIO_PAD_ATTR_46, + PINMUX_DIO_PAD_ATTR_47, + PINMUX_DIO_PAD_ATTR_48, + PINMUX_DIO_PAD_ATTR_49, + PINMUX_DIO_PAD_ATTR_50, + PINMUX_DIO_PAD_ATTR_51, + PINMUX_DIO_PAD_ATTR_52, + PINMUX_DIO_PAD_ATTR_53, + PINMUX_DIO_PAD_ATTR_54, + PINMUX_DIO_PAD_ATTR_55, + PINMUX_DIO_PAD_ATTR_56, + PINMUX_DIO_PAD_ATTR_57, + PINMUX_DIO_PAD_ATTR_58, + PINMUX_DIO_PAD_ATTR_59, + PINMUX_DIO_PAD_ATTR_60, + PINMUX_DIO_PAD_ATTR_61, + PINMUX_DIO_PAD_ATTR_62, + PINMUX_DIO_PAD_ATTR_63, + PINMUX_DIO_PAD_ATTR_64, + PINMUX_DIO_PAD_ATTR_65, + PINMUX_DIO_PAD_ATTR_66, + PINMUX_DIO_PAD_ATTR_67, + PINMUX_DIO_PAD_ATTR_68, + PINMUX_DIO_PAD_ATTR_69, + PINMUX_DIO_PAD_ATTR_70, + PINMUX_DIO_PAD_ATTR_71, + PINMUX_DIO_PAD_ATTR_72, + PINMUX_MIO_PAD_SLEEP_STATUS, + PINMUX_MIO_PAD_SLEEP_REGWEN_0, + PINMUX_MIO_PAD_SLEEP_REGWEN_1, + PINMUX_MIO_PAD_SLEEP_REGWEN_2, + PINMUX_MIO_PAD_SLEEP_REGWEN_3, + PINMUX_MIO_PAD_SLEEP_REGWEN_4, + PINMUX_MIO_PAD_SLEEP_REGWEN_5, + PINMUX_MIO_PAD_SLEEP_REGWEN_6, + PINMUX_MIO_PAD_SLEEP_REGWEN_7, + PINMUX_MIO_PAD_SLEEP_REGWEN_8, + PINMUX_MIO_PAD_SLEEP_REGWEN_9, + PINMUX_MIO_PAD_SLEEP_REGWEN_10, + PINMUX_MIO_PAD_SLEEP_REGWEN_11, + PINMUX_MIO_PAD_SLEEP_EN_0, + PINMUX_MIO_PAD_SLEEP_EN_1, + PINMUX_MIO_PAD_SLEEP_EN_2, + PINMUX_MIO_PAD_SLEEP_EN_3, + PINMUX_MIO_PAD_SLEEP_EN_4, + PINMUX_MIO_PAD_SLEEP_EN_5, + PINMUX_MIO_PAD_SLEEP_EN_6, + PINMUX_MIO_PAD_SLEEP_EN_7, + PINMUX_MIO_PAD_SLEEP_EN_8, + PINMUX_MIO_PAD_SLEEP_EN_9, + PINMUX_MIO_PAD_SLEEP_EN_10, + PINMUX_MIO_PAD_SLEEP_EN_11, + PINMUX_MIO_PAD_SLEEP_MODE_0, + PINMUX_MIO_PAD_SLEEP_MODE_1, + PINMUX_MIO_PAD_SLEEP_MODE_2, + PINMUX_MIO_PAD_SLEEP_MODE_3, + PINMUX_MIO_PAD_SLEEP_MODE_4, + PINMUX_MIO_PAD_SLEEP_MODE_5, + PINMUX_MIO_PAD_SLEEP_MODE_6, + PINMUX_MIO_PAD_SLEEP_MODE_7, + PINMUX_MIO_PAD_SLEEP_MODE_8, + PINMUX_MIO_PAD_SLEEP_MODE_9, + PINMUX_MIO_PAD_SLEEP_MODE_10, + PINMUX_MIO_PAD_SLEEP_MODE_11, + PINMUX_DIO_PAD_SLEEP_STATUS_0, + PINMUX_DIO_PAD_SLEEP_STATUS_1, + PINMUX_DIO_PAD_SLEEP_STATUS_2, + PINMUX_DIO_PAD_SLEEP_REGWEN_0, + PINMUX_DIO_PAD_SLEEP_REGWEN_1, + PINMUX_DIO_PAD_SLEEP_REGWEN_2, + PINMUX_DIO_PAD_SLEEP_REGWEN_3, + PINMUX_DIO_PAD_SLEEP_REGWEN_4, + PINMUX_DIO_PAD_SLEEP_REGWEN_5, + PINMUX_DIO_PAD_SLEEP_REGWEN_6, + PINMUX_DIO_PAD_SLEEP_REGWEN_7, + PINMUX_DIO_PAD_SLEEP_REGWEN_8, + PINMUX_DIO_PAD_SLEEP_REGWEN_9, + PINMUX_DIO_PAD_SLEEP_REGWEN_10, + PINMUX_DIO_PAD_SLEEP_REGWEN_11, + PINMUX_DIO_PAD_SLEEP_REGWEN_12, + PINMUX_DIO_PAD_SLEEP_REGWEN_13, + PINMUX_DIO_PAD_SLEEP_REGWEN_14, + PINMUX_DIO_PAD_SLEEP_REGWEN_15, + PINMUX_DIO_PAD_SLEEP_REGWEN_16, + PINMUX_DIO_PAD_SLEEP_REGWEN_17, + PINMUX_DIO_PAD_SLEEP_REGWEN_18, + PINMUX_DIO_PAD_SLEEP_REGWEN_19, + PINMUX_DIO_PAD_SLEEP_REGWEN_20, + PINMUX_DIO_PAD_SLEEP_REGWEN_21, + PINMUX_DIO_PAD_SLEEP_REGWEN_22, + PINMUX_DIO_PAD_SLEEP_REGWEN_23, + PINMUX_DIO_PAD_SLEEP_REGWEN_24, + PINMUX_DIO_PAD_SLEEP_REGWEN_25, + PINMUX_DIO_PAD_SLEEP_REGWEN_26, + PINMUX_DIO_PAD_SLEEP_REGWEN_27, + PINMUX_DIO_PAD_SLEEP_REGWEN_28, + PINMUX_DIO_PAD_SLEEP_REGWEN_29, + PINMUX_DIO_PAD_SLEEP_REGWEN_30, + PINMUX_DIO_PAD_SLEEP_REGWEN_31, + PINMUX_DIO_PAD_SLEEP_REGWEN_32, + PINMUX_DIO_PAD_SLEEP_REGWEN_33, + PINMUX_DIO_PAD_SLEEP_REGWEN_34, + PINMUX_DIO_PAD_SLEEP_REGWEN_35, + PINMUX_DIO_PAD_SLEEP_REGWEN_36, + PINMUX_DIO_PAD_SLEEP_REGWEN_37, + PINMUX_DIO_PAD_SLEEP_REGWEN_38, + PINMUX_DIO_PAD_SLEEP_REGWEN_39, + PINMUX_DIO_PAD_SLEEP_REGWEN_40, + PINMUX_DIO_PAD_SLEEP_REGWEN_41, + PINMUX_DIO_PAD_SLEEP_REGWEN_42, + PINMUX_DIO_PAD_SLEEP_REGWEN_43, + PINMUX_DIO_PAD_SLEEP_REGWEN_44, + PINMUX_DIO_PAD_SLEEP_REGWEN_45, + PINMUX_DIO_PAD_SLEEP_REGWEN_46, + PINMUX_DIO_PAD_SLEEP_REGWEN_47, + PINMUX_DIO_PAD_SLEEP_REGWEN_48, + PINMUX_DIO_PAD_SLEEP_REGWEN_49, + PINMUX_DIO_PAD_SLEEP_REGWEN_50, + PINMUX_DIO_PAD_SLEEP_REGWEN_51, + PINMUX_DIO_PAD_SLEEP_REGWEN_52, + PINMUX_DIO_PAD_SLEEP_REGWEN_53, + PINMUX_DIO_PAD_SLEEP_REGWEN_54, + PINMUX_DIO_PAD_SLEEP_REGWEN_55, + PINMUX_DIO_PAD_SLEEP_REGWEN_56, + PINMUX_DIO_PAD_SLEEP_REGWEN_57, + PINMUX_DIO_PAD_SLEEP_REGWEN_58, + PINMUX_DIO_PAD_SLEEP_REGWEN_59, + PINMUX_DIO_PAD_SLEEP_REGWEN_60, + PINMUX_DIO_PAD_SLEEP_REGWEN_61, + PINMUX_DIO_PAD_SLEEP_REGWEN_62, + PINMUX_DIO_PAD_SLEEP_REGWEN_63, + PINMUX_DIO_PAD_SLEEP_REGWEN_64, + PINMUX_DIO_PAD_SLEEP_REGWEN_65, + PINMUX_DIO_PAD_SLEEP_REGWEN_66, + PINMUX_DIO_PAD_SLEEP_REGWEN_67, + PINMUX_DIO_PAD_SLEEP_REGWEN_68, + PINMUX_DIO_PAD_SLEEP_REGWEN_69, + PINMUX_DIO_PAD_SLEEP_REGWEN_70, + PINMUX_DIO_PAD_SLEEP_REGWEN_71, + PINMUX_DIO_PAD_SLEEP_REGWEN_72, + PINMUX_DIO_PAD_SLEEP_EN_0, + PINMUX_DIO_PAD_SLEEP_EN_1, + PINMUX_DIO_PAD_SLEEP_EN_2, + PINMUX_DIO_PAD_SLEEP_EN_3, + PINMUX_DIO_PAD_SLEEP_EN_4, + PINMUX_DIO_PAD_SLEEP_EN_5, + PINMUX_DIO_PAD_SLEEP_EN_6, + PINMUX_DIO_PAD_SLEEP_EN_7, + PINMUX_DIO_PAD_SLEEP_EN_8, + PINMUX_DIO_PAD_SLEEP_EN_9, + PINMUX_DIO_PAD_SLEEP_EN_10, + PINMUX_DIO_PAD_SLEEP_EN_11, + PINMUX_DIO_PAD_SLEEP_EN_12, + PINMUX_DIO_PAD_SLEEP_EN_13, + PINMUX_DIO_PAD_SLEEP_EN_14, + PINMUX_DIO_PAD_SLEEP_EN_15, + PINMUX_DIO_PAD_SLEEP_EN_16, + PINMUX_DIO_PAD_SLEEP_EN_17, + PINMUX_DIO_PAD_SLEEP_EN_18, + PINMUX_DIO_PAD_SLEEP_EN_19, + PINMUX_DIO_PAD_SLEEP_EN_20, + PINMUX_DIO_PAD_SLEEP_EN_21, + PINMUX_DIO_PAD_SLEEP_EN_22, + PINMUX_DIO_PAD_SLEEP_EN_23, + PINMUX_DIO_PAD_SLEEP_EN_24, + PINMUX_DIO_PAD_SLEEP_EN_25, + PINMUX_DIO_PAD_SLEEP_EN_26, + PINMUX_DIO_PAD_SLEEP_EN_27, + PINMUX_DIO_PAD_SLEEP_EN_28, + PINMUX_DIO_PAD_SLEEP_EN_29, + PINMUX_DIO_PAD_SLEEP_EN_30, + PINMUX_DIO_PAD_SLEEP_EN_31, + PINMUX_DIO_PAD_SLEEP_EN_32, + PINMUX_DIO_PAD_SLEEP_EN_33, + PINMUX_DIO_PAD_SLEEP_EN_34, + PINMUX_DIO_PAD_SLEEP_EN_35, + PINMUX_DIO_PAD_SLEEP_EN_36, + PINMUX_DIO_PAD_SLEEP_EN_37, + PINMUX_DIO_PAD_SLEEP_EN_38, + PINMUX_DIO_PAD_SLEEP_EN_39, + PINMUX_DIO_PAD_SLEEP_EN_40, + PINMUX_DIO_PAD_SLEEP_EN_41, + PINMUX_DIO_PAD_SLEEP_EN_42, + PINMUX_DIO_PAD_SLEEP_EN_43, + PINMUX_DIO_PAD_SLEEP_EN_44, + PINMUX_DIO_PAD_SLEEP_EN_45, + PINMUX_DIO_PAD_SLEEP_EN_46, + PINMUX_DIO_PAD_SLEEP_EN_47, + PINMUX_DIO_PAD_SLEEP_EN_48, + PINMUX_DIO_PAD_SLEEP_EN_49, + PINMUX_DIO_PAD_SLEEP_EN_50, + PINMUX_DIO_PAD_SLEEP_EN_51, + PINMUX_DIO_PAD_SLEEP_EN_52, + PINMUX_DIO_PAD_SLEEP_EN_53, + PINMUX_DIO_PAD_SLEEP_EN_54, + PINMUX_DIO_PAD_SLEEP_EN_55, + PINMUX_DIO_PAD_SLEEP_EN_56, + PINMUX_DIO_PAD_SLEEP_EN_57, + PINMUX_DIO_PAD_SLEEP_EN_58, + PINMUX_DIO_PAD_SLEEP_EN_59, + PINMUX_DIO_PAD_SLEEP_EN_60, + PINMUX_DIO_PAD_SLEEP_EN_61, + PINMUX_DIO_PAD_SLEEP_EN_62, + PINMUX_DIO_PAD_SLEEP_EN_63, + PINMUX_DIO_PAD_SLEEP_EN_64, + PINMUX_DIO_PAD_SLEEP_EN_65, + PINMUX_DIO_PAD_SLEEP_EN_66, + PINMUX_DIO_PAD_SLEEP_EN_67, + PINMUX_DIO_PAD_SLEEP_EN_68, + PINMUX_DIO_PAD_SLEEP_EN_69, + PINMUX_DIO_PAD_SLEEP_EN_70, + PINMUX_DIO_PAD_SLEEP_EN_71, + PINMUX_DIO_PAD_SLEEP_EN_72, + PINMUX_DIO_PAD_SLEEP_MODE_0, + PINMUX_DIO_PAD_SLEEP_MODE_1, + PINMUX_DIO_PAD_SLEEP_MODE_2, + PINMUX_DIO_PAD_SLEEP_MODE_3, + PINMUX_DIO_PAD_SLEEP_MODE_4, + PINMUX_DIO_PAD_SLEEP_MODE_5, + PINMUX_DIO_PAD_SLEEP_MODE_6, + PINMUX_DIO_PAD_SLEEP_MODE_7, + PINMUX_DIO_PAD_SLEEP_MODE_8, + PINMUX_DIO_PAD_SLEEP_MODE_9, + PINMUX_DIO_PAD_SLEEP_MODE_10, + PINMUX_DIO_PAD_SLEEP_MODE_11, + PINMUX_DIO_PAD_SLEEP_MODE_12, + PINMUX_DIO_PAD_SLEEP_MODE_13, + PINMUX_DIO_PAD_SLEEP_MODE_14, + PINMUX_DIO_PAD_SLEEP_MODE_15, + PINMUX_DIO_PAD_SLEEP_MODE_16, + PINMUX_DIO_PAD_SLEEP_MODE_17, + PINMUX_DIO_PAD_SLEEP_MODE_18, + PINMUX_DIO_PAD_SLEEP_MODE_19, + PINMUX_DIO_PAD_SLEEP_MODE_20, + PINMUX_DIO_PAD_SLEEP_MODE_21, + PINMUX_DIO_PAD_SLEEP_MODE_22, + PINMUX_DIO_PAD_SLEEP_MODE_23, + PINMUX_DIO_PAD_SLEEP_MODE_24, + PINMUX_DIO_PAD_SLEEP_MODE_25, + PINMUX_DIO_PAD_SLEEP_MODE_26, + PINMUX_DIO_PAD_SLEEP_MODE_27, + PINMUX_DIO_PAD_SLEEP_MODE_28, + PINMUX_DIO_PAD_SLEEP_MODE_29, + PINMUX_DIO_PAD_SLEEP_MODE_30, + PINMUX_DIO_PAD_SLEEP_MODE_31, + PINMUX_DIO_PAD_SLEEP_MODE_32, + PINMUX_DIO_PAD_SLEEP_MODE_33, + PINMUX_DIO_PAD_SLEEP_MODE_34, + PINMUX_DIO_PAD_SLEEP_MODE_35, + PINMUX_DIO_PAD_SLEEP_MODE_36, + PINMUX_DIO_PAD_SLEEP_MODE_37, + PINMUX_DIO_PAD_SLEEP_MODE_38, + PINMUX_DIO_PAD_SLEEP_MODE_39, + PINMUX_DIO_PAD_SLEEP_MODE_40, + PINMUX_DIO_PAD_SLEEP_MODE_41, + PINMUX_DIO_PAD_SLEEP_MODE_42, + PINMUX_DIO_PAD_SLEEP_MODE_43, + PINMUX_DIO_PAD_SLEEP_MODE_44, + PINMUX_DIO_PAD_SLEEP_MODE_45, + PINMUX_DIO_PAD_SLEEP_MODE_46, + PINMUX_DIO_PAD_SLEEP_MODE_47, + PINMUX_DIO_PAD_SLEEP_MODE_48, + PINMUX_DIO_PAD_SLEEP_MODE_49, + PINMUX_DIO_PAD_SLEEP_MODE_50, + PINMUX_DIO_PAD_SLEEP_MODE_51, + PINMUX_DIO_PAD_SLEEP_MODE_52, + PINMUX_DIO_PAD_SLEEP_MODE_53, + PINMUX_DIO_PAD_SLEEP_MODE_54, + PINMUX_DIO_PAD_SLEEP_MODE_55, + PINMUX_DIO_PAD_SLEEP_MODE_56, + PINMUX_DIO_PAD_SLEEP_MODE_57, + PINMUX_DIO_PAD_SLEEP_MODE_58, + PINMUX_DIO_PAD_SLEEP_MODE_59, + PINMUX_DIO_PAD_SLEEP_MODE_60, + PINMUX_DIO_PAD_SLEEP_MODE_61, + PINMUX_DIO_PAD_SLEEP_MODE_62, + PINMUX_DIO_PAD_SLEEP_MODE_63, + PINMUX_DIO_PAD_SLEEP_MODE_64, + PINMUX_DIO_PAD_SLEEP_MODE_65, + PINMUX_DIO_PAD_SLEEP_MODE_66, + PINMUX_DIO_PAD_SLEEP_MODE_67, + PINMUX_DIO_PAD_SLEEP_MODE_68, + PINMUX_DIO_PAD_SLEEP_MODE_69, + PINMUX_DIO_PAD_SLEEP_MODE_70, + PINMUX_DIO_PAD_SLEEP_MODE_71, + PINMUX_DIO_PAD_SLEEP_MODE_72, + PINMUX_WKUP_DETECTOR_REGWEN_0, + PINMUX_WKUP_DETECTOR_REGWEN_1, + PINMUX_WKUP_DETECTOR_REGWEN_2, + PINMUX_WKUP_DETECTOR_REGWEN_3, + PINMUX_WKUP_DETECTOR_REGWEN_4, + PINMUX_WKUP_DETECTOR_REGWEN_5, + PINMUX_WKUP_DETECTOR_REGWEN_6, + PINMUX_WKUP_DETECTOR_REGWEN_7, + PINMUX_WKUP_DETECTOR_EN_0, + PINMUX_WKUP_DETECTOR_EN_1, + PINMUX_WKUP_DETECTOR_EN_2, + PINMUX_WKUP_DETECTOR_EN_3, + PINMUX_WKUP_DETECTOR_EN_4, + PINMUX_WKUP_DETECTOR_EN_5, + PINMUX_WKUP_DETECTOR_EN_6, + PINMUX_WKUP_DETECTOR_EN_7, + PINMUX_WKUP_DETECTOR_0, + PINMUX_WKUP_DETECTOR_1, + PINMUX_WKUP_DETECTOR_2, + PINMUX_WKUP_DETECTOR_3, + PINMUX_WKUP_DETECTOR_4, + PINMUX_WKUP_DETECTOR_5, + PINMUX_WKUP_DETECTOR_6, + PINMUX_WKUP_DETECTOR_7, + PINMUX_WKUP_DETECTOR_CNT_TH_0, + PINMUX_WKUP_DETECTOR_CNT_TH_1, + PINMUX_WKUP_DETECTOR_CNT_TH_2, + PINMUX_WKUP_DETECTOR_CNT_TH_3, + PINMUX_WKUP_DETECTOR_CNT_TH_4, + PINMUX_WKUP_DETECTOR_CNT_TH_5, + PINMUX_WKUP_DETECTOR_CNT_TH_6, + PINMUX_WKUP_DETECTOR_CNT_TH_7, + PINMUX_WKUP_DETECTOR_PADSEL_0, + PINMUX_WKUP_DETECTOR_PADSEL_1, + PINMUX_WKUP_DETECTOR_PADSEL_2, + PINMUX_WKUP_DETECTOR_PADSEL_3, + PINMUX_WKUP_DETECTOR_PADSEL_4, + PINMUX_WKUP_DETECTOR_PADSEL_5, + PINMUX_WKUP_DETECTOR_PADSEL_6, + PINMUX_WKUP_DETECTOR_PADSEL_7, + PINMUX_WKUP_CAUSE + } pinmux_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] PINMUX_PERMIT [503] = '{ + 4'b 0001, // index[ 0] PINMUX_ALERT_TEST + 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0 + 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1 + 4'b 0001, // index[ 3] PINMUX_MIO_PERIPH_INSEL_REGWEN_2 + 4'b 0001, // index[ 4] PINMUX_MIO_PERIPH_INSEL_REGWEN_3 + 4'b 0001, // index[ 5] PINMUX_MIO_PERIPH_INSEL_0 + 4'b 0001, // index[ 6] PINMUX_MIO_PERIPH_INSEL_1 + 4'b 0001, // index[ 7] PINMUX_MIO_PERIPH_INSEL_2 + 4'b 0001, // index[ 8] PINMUX_MIO_PERIPH_INSEL_3 + 4'b 0001, // index[ 9] PINMUX_MIO_OUTSEL_REGWEN_0 + 4'b 0001, // index[ 10] PINMUX_MIO_OUTSEL_REGWEN_1 + 4'b 0001, // index[ 11] PINMUX_MIO_OUTSEL_REGWEN_2 + 4'b 0001, // index[ 12] PINMUX_MIO_OUTSEL_REGWEN_3 + 4'b 0001, // index[ 13] PINMUX_MIO_OUTSEL_REGWEN_4 + 4'b 0001, // index[ 14] PINMUX_MIO_OUTSEL_REGWEN_5 + 4'b 0001, // index[ 15] PINMUX_MIO_OUTSEL_REGWEN_6 + 4'b 0001, // index[ 16] PINMUX_MIO_OUTSEL_REGWEN_7 + 4'b 0001, // index[ 17] PINMUX_MIO_OUTSEL_REGWEN_8 + 4'b 0001, // index[ 18] PINMUX_MIO_OUTSEL_REGWEN_9 + 4'b 0001, // index[ 19] PINMUX_MIO_OUTSEL_REGWEN_10 + 4'b 0001, // index[ 20] PINMUX_MIO_OUTSEL_REGWEN_11 + 4'b 0001, // index[ 21] PINMUX_MIO_OUTSEL_0 + 4'b 0001, // index[ 22] PINMUX_MIO_OUTSEL_1 + 4'b 0001, // index[ 23] PINMUX_MIO_OUTSEL_2 + 4'b 0001, // index[ 24] PINMUX_MIO_OUTSEL_3 + 4'b 0001, // index[ 25] PINMUX_MIO_OUTSEL_4 + 4'b 0001, // index[ 26] PINMUX_MIO_OUTSEL_5 + 4'b 0001, // index[ 27] PINMUX_MIO_OUTSEL_6 + 4'b 0001, // index[ 28] PINMUX_MIO_OUTSEL_7 + 4'b 0001, // index[ 29] PINMUX_MIO_OUTSEL_8 + 4'b 0001, // index[ 30] PINMUX_MIO_OUTSEL_9 + 4'b 0001, // index[ 31] PINMUX_MIO_OUTSEL_10 + 4'b 0001, // index[ 32] PINMUX_MIO_OUTSEL_11 + 4'b 0001, // index[ 33] PINMUX_MIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[ 34] PINMUX_MIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[ 35] PINMUX_MIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[ 36] PINMUX_MIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[ 37] PINMUX_MIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[ 38] PINMUX_MIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[ 39] PINMUX_MIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[ 40] PINMUX_MIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[ 41] PINMUX_MIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[ 42] PINMUX_MIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[ 43] PINMUX_MIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[ 44] PINMUX_MIO_PAD_ATTR_REGWEN_11 + 4'b 0111, // index[ 45] PINMUX_MIO_PAD_ATTR_0 + 4'b 0111, // index[ 46] PINMUX_MIO_PAD_ATTR_1 + 4'b 0111, // index[ 47] PINMUX_MIO_PAD_ATTR_2 + 4'b 0111, // index[ 48] PINMUX_MIO_PAD_ATTR_3 + 4'b 0111, // index[ 49] PINMUX_MIO_PAD_ATTR_4 + 4'b 0111, // index[ 50] PINMUX_MIO_PAD_ATTR_5 + 4'b 0111, // index[ 51] PINMUX_MIO_PAD_ATTR_6 + 4'b 0111, // index[ 52] PINMUX_MIO_PAD_ATTR_7 + 4'b 0111, // index[ 53] PINMUX_MIO_PAD_ATTR_8 + 4'b 0111, // index[ 54] PINMUX_MIO_PAD_ATTR_9 + 4'b 0111, // index[ 55] PINMUX_MIO_PAD_ATTR_10 + 4'b 0111, // index[ 56] PINMUX_MIO_PAD_ATTR_11 + 4'b 0001, // index[ 57] PINMUX_DIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[ 58] PINMUX_DIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[ 59] PINMUX_DIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[ 60] PINMUX_DIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[ 61] PINMUX_DIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[ 62] PINMUX_DIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[ 63] PINMUX_DIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[ 64] PINMUX_DIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[ 65] PINMUX_DIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[ 66] PINMUX_DIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[ 67] PINMUX_DIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[ 68] PINMUX_DIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[ 69] PINMUX_DIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[ 70] PINMUX_DIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[ 71] PINMUX_DIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[ 72] PINMUX_DIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[ 73] PINMUX_DIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[ 74] PINMUX_DIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[ 75] PINMUX_DIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[ 76] PINMUX_DIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[ 77] PINMUX_DIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[ 78] PINMUX_DIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[ 79] PINMUX_DIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[ 80] PINMUX_DIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[ 81] PINMUX_DIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[ 82] PINMUX_DIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[ 83] PINMUX_DIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[ 84] PINMUX_DIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[ 85] PINMUX_DIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[ 86] PINMUX_DIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[ 87] PINMUX_DIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[ 88] PINMUX_DIO_PAD_ATTR_REGWEN_31 + 4'b 0001, // index[ 89] PINMUX_DIO_PAD_ATTR_REGWEN_32 + 4'b 0001, // index[ 90] PINMUX_DIO_PAD_ATTR_REGWEN_33 + 4'b 0001, // index[ 91] PINMUX_DIO_PAD_ATTR_REGWEN_34 + 4'b 0001, // index[ 92] PINMUX_DIO_PAD_ATTR_REGWEN_35 + 4'b 0001, // index[ 93] PINMUX_DIO_PAD_ATTR_REGWEN_36 + 4'b 0001, // index[ 94] PINMUX_DIO_PAD_ATTR_REGWEN_37 + 4'b 0001, // index[ 95] PINMUX_DIO_PAD_ATTR_REGWEN_38 + 4'b 0001, // index[ 96] PINMUX_DIO_PAD_ATTR_REGWEN_39 + 4'b 0001, // index[ 97] PINMUX_DIO_PAD_ATTR_REGWEN_40 + 4'b 0001, // index[ 98] PINMUX_DIO_PAD_ATTR_REGWEN_41 + 4'b 0001, // index[ 99] PINMUX_DIO_PAD_ATTR_REGWEN_42 + 4'b 0001, // index[100] PINMUX_DIO_PAD_ATTR_REGWEN_43 + 4'b 0001, // index[101] PINMUX_DIO_PAD_ATTR_REGWEN_44 + 4'b 0001, // index[102] PINMUX_DIO_PAD_ATTR_REGWEN_45 + 4'b 0001, // index[103] PINMUX_DIO_PAD_ATTR_REGWEN_46 + 4'b 0001, // index[104] PINMUX_DIO_PAD_ATTR_REGWEN_47 + 4'b 0001, // index[105] PINMUX_DIO_PAD_ATTR_REGWEN_48 + 4'b 0001, // index[106] PINMUX_DIO_PAD_ATTR_REGWEN_49 + 4'b 0001, // index[107] PINMUX_DIO_PAD_ATTR_REGWEN_50 + 4'b 0001, // index[108] PINMUX_DIO_PAD_ATTR_REGWEN_51 + 4'b 0001, // index[109] PINMUX_DIO_PAD_ATTR_REGWEN_52 + 4'b 0001, // index[110] PINMUX_DIO_PAD_ATTR_REGWEN_53 + 4'b 0001, // index[111] PINMUX_DIO_PAD_ATTR_REGWEN_54 + 4'b 0001, // index[112] PINMUX_DIO_PAD_ATTR_REGWEN_55 + 4'b 0001, // index[113] PINMUX_DIO_PAD_ATTR_REGWEN_56 + 4'b 0001, // index[114] PINMUX_DIO_PAD_ATTR_REGWEN_57 + 4'b 0001, // index[115] PINMUX_DIO_PAD_ATTR_REGWEN_58 + 4'b 0001, // index[116] PINMUX_DIO_PAD_ATTR_REGWEN_59 + 4'b 0001, // index[117] PINMUX_DIO_PAD_ATTR_REGWEN_60 + 4'b 0001, // index[118] PINMUX_DIO_PAD_ATTR_REGWEN_61 + 4'b 0001, // index[119] PINMUX_DIO_PAD_ATTR_REGWEN_62 + 4'b 0001, // index[120] PINMUX_DIO_PAD_ATTR_REGWEN_63 + 4'b 0001, // index[121] PINMUX_DIO_PAD_ATTR_REGWEN_64 + 4'b 0001, // index[122] PINMUX_DIO_PAD_ATTR_REGWEN_65 + 4'b 0001, // index[123] PINMUX_DIO_PAD_ATTR_REGWEN_66 + 4'b 0001, // index[124] PINMUX_DIO_PAD_ATTR_REGWEN_67 + 4'b 0001, // index[125] PINMUX_DIO_PAD_ATTR_REGWEN_68 + 4'b 0001, // index[126] PINMUX_DIO_PAD_ATTR_REGWEN_69 + 4'b 0001, // index[127] PINMUX_DIO_PAD_ATTR_REGWEN_70 + 4'b 0001, // index[128] PINMUX_DIO_PAD_ATTR_REGWEN_71 + 4'b 0001, // index[129] PINMUX_DIO_PAD_ATTR_REGWEN_72 + 4'b 0111, // index[130] PINMUX_DIO_PAD_ATTR_0 + 4'b 0111, // index[131] PINMUX_DIO_PAD_ATTR_1 + 4'b 0111, // index[132] PINMUX_DIO_PAD_ATTR_2 + 4'b 0111, // index[133] PINMUX_DIO_PAD_ATTR_3 + 4'b 0111, // index[134] PINMUX_DIO_PAD_ATTR_4 + 4'b 0111, // index[135] PINMUX_DIO_PAD_ATTR_5 + 4'b 0111, // index[136] PINMUX_DIO_PAD_ATTR_6 + 4'b 0111, // index[137] PINMUX_DIO_PAD_ATTR_7 + 4'b 0111, // index[138] PINMUX_DIO_PAD_ATTR_8 + 4'b 0111, // index[139] PINMUX_DIO_PAD_ATTR_9 + 4'b 0111, // index[140] PINMUX_DIO_PAD_ATTR_10 + 4'b 0111, // index[141] PINMUX_DIO_PAD_ATTR_11 + 4'b 0111, // index[142] PINMUX_DIO_PAD_ATTR_12 + 4'b 0111, // index[143] PINMUX_DIO_PAD_ATTR_13 + 4'b 0111, // index[144] PINMUX_DIO_PAD_ATTR_14 + 4'b 0111, // index[145] PINMUX_DIO_PAD_ATTR_15 + 4'b 0111, // index[146] PINMUX_DIO_PAD_ATTR_16 + 4'b 0111, // index[147] PINMUX_DIO_PAD_ATTR_17 + 4'b 0111, // index[148] PINMUX_DIO_PAD_ATTR_18 + 4'b 0111, // index[149] PINMUX_DIO_PAD_ATTR_19 + 4'b 0111, // index[150] PINMUX_DIO_PAD_ATTR_20 + 4'b 0111, // index[151] PINMUX_DIO_PAD_ATTR_21 + 4'b 0111, // index[152] PINMUX_DIO_PAD_ATTR_22 + 4'b 0111, // index[153] PINMUX_DIO_PAD_ATTR_23 + 4'b 0111, // index[154] PINMUX_DIO_PAD_ATTR_24 + 4'b 0111, // index[155] PINMUX_DIO_PAD_ATTR_25 + 4'b 0111, // index[156] PINMUX_DIO_PAD_ATTR_26 + 4'b 0111, // index[157] PINMUX_DIO_PAD_ATTR_27 + 4'b 0111, // index[158] PINMUX_DIO_PAD_ATTR_28 + 4'b 0111, // index[159] PINMUX_DIO_PAD_ATTR_29 + 4'b 0111, // index[160] PINMUX_DIO_PAD_ATTR_30 + 4'b 0111, // index[161] PINMUX_DIO_PAD_ATTR_31 + 4'b 0111, // index[162] PINMUX_DIO_PAD_ATTR_32 + 4'b 0111, // index[163] PINMUX_DIO_PAD_ATTR_33 + 4'b 0111, // index[164] PINMUX_DIO_PAD_ATTR_34 + 4'b 0111, // index[165] PINMUX_DIO_PAD_ATTR_35 + 4'b 0111, // index[166] PINMUX_DIO_PAD_ATTR_36 + 4'b 0111, // index[167] PINMUX_DIO_PAD_ATTR_37 + 4'b 0111, // index[168] PINMUX_DIO_PAD_ATTR_38 + 4'b 0111, // index[169] PINMUX_DIO_PAD_ATTR_39 + 4'b 0111, // index[170] PINMUX_DIO_PAD_ATTR_40 + 4'b 0111, // index[171] PINMUX_DIO_PAD_ATTR_41 + 4'b 0111, // index[172] PINMUX_DIO_PAD_ATTR_42 + 4'b 0111, // index[173] PINMUX_DIO_PAD_ATTR_43 + 4'b 0111, // index[174] PINMUX_DIO_PAD_ATTR_44 + 4'b 0111, // index[175] PINMUX_DIO_PAD_ATTR_45 + 4'b 0111, // index[176] PINMUX_DIO_PAD_ATTR_46 + 4'b 0111, // index[177] PINMUX_DIO_PAD_ATTR_47 + 4'b 0111, // index[178] PINMUX_DIO_PAD_ATTR_48 + 4'b 0111, // index[179] PINMUX_DIO_PAD_ATTR_49 + 4'b 0111, // index[180] PINMUX_DIO_PAD_ATTR_50 + 4'b 0111, // index[181] PINMUX_DIO_PAD_ATTR_51 + 4'b 0111, // index[182] PINMUX_DIO_PAD_ATTR_52 + 4'b 0111, // index[183] PINMUX_DIO_PAD_ATTR_53 + 4'b 0111, // index[184] PINMUX_DIO_PAD_ATTR_54 + 4'b 0111, // index[185] PINMUX_DIO_PAD_ATTR_55 + 4'b 0111, // index[186] PINMUX_DIO_PAD_ATTR_56 + 4'b 0111, // index[187] PINMUX_DIO_PAD_ATTR_57 + 4'b 0111, // index[188] PINMUX_DIO_PAD_ATTR_58 + 4'b 0111, // index[189] PINMUX_DIO_PAD_ATTR_59 + 4'b 0111, // index[190] PINMUX_DIO_PAD_ATTR_60 + 4'b 0111, // index[191] PINMUX_DIO_PAD_ATTR_61 + 4'b 0111, // index[192] PINMUX_DIO_PAD_ATTR_62 + 4'b 0111, // index[193] PINMUX_DIO_PAD_ATTR_63 + 4'b 0111, // index[194] PINMUX_DIO_PAD_ATTR_64 + 4'b 0111, // index[195] PINMUX_DIO_PAD_ATTR_65 + 4'b 0111, // index[196] PINMUX_DIO_PAD_ATTR_66 + 4'b 0111, // index[197] PINMUX_DIO_PAD_ATTR_67 + 4'b 0111, // index[198] PINMUX_DIO_PAD_ATTR_68 + 4'b 0111, // index[199] PINMUX_DIO_PAD_ATTR_69 + 4'b 0111, // index[200] PINMUX_DIO_PAD_ATTR_70 + 4'b 0111, // index[201] PINMUX_DIO_PAD_ATTR_71 + 4'b 0111, // index[202] PINMUX_DIO_PAD_ATTR_72 + 4'b 0011, // index[203] PINMUX_MIO_PAD_SLEEP_STATUS + 4'b 0001, // index[204] PINMUX_MIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[205] PINMUX_MIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[206] PINMUX_MIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[207] PINMUX_MIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[208] PINMUX_MIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[209] PINMUX_MIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[210] PINMUX_MIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[211] PINMUX_MIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[212] PINMUX_MIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[213] PINMUX_MIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[214] PINMUX_MIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[215] PINMUX_MIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[216] PINMUX_MIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[217] PINMUX_MIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[218] PINMUX_MIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[219] PINMUX_MIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[220] PINMUX_MIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[221] PINMUX_MIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[222] PINMUX_MIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[223] PINMUX_MIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[224] PINMUX_MIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[225] PINMUX_MIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[226] PINMUX_MIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[227] PINMUX_MIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[228] PINMUX_MIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[229] PINMUX_MIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[230] PINMUX_MIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[231] PINMUX_MIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[232] PINMUX_MIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[233] PINMUX_MIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[234] PINMUX_MIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[235] PINMUX_MIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[236] PINMUX_MIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[237] PINMUX_MIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[238] PINMUX_MIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[239] PINMUX_MIO_PAD_SLEEP_MODE_11 + 4'b 1111, // index[240] PINMUX_DIO_PAD_SLEEP_STATUS_0 + 4'b 1111, // index[241] PINMUX_DIO_PAD_SLEEP_STATUS_1 + 4'b 0011, // index[242] PINMUX_DIO_PAD_SLEEP_STATUS_2 + 4'b 0001, // index[243] PINMUX_DIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[244] PINMUX_DIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[245] PINMUX_DIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[246] PINMUX_DIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[247] PINMUX_DIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[248] PINMUX_DIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[249] PINMUX_DIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[250] PINMUX_DIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[251] PINMUX_DIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[252] PINMUX_DIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[253] PINMUX_DIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[254] PINMUX_DIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[255] PINMUX_DIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[256] PINMUX_DIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[257] PINMUX_DIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[258] PINMUX_DIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[259] PINMUX_DIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[260] PINMUX_DIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[261] PINMUX_DIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[262] PINMUX_DIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[263] PINMUX_DIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[264] PINMUX_DIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[265] PINMUX_DIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[266] PINMUX_DIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[267] PINMUX_DIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[268] PINMUX_DIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[269] PINMUX_DIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[270] PINMUX_DIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[271] PINMUX_DIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[272] PINMUX_DIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[273] PINMUX_DIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[274] PINMUX_DIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[275] PINMUX_DIO_PAD_SLEEP_REGWEN_32 + 4'b 0001, // index[276] PINMUX_DIO_PAD_SLEEP_REGWEN_33 + 4'b 0001, // index[277] PINMUX_DIO_PAD_SLEEP_REGWEN_34 + 4'b 0001, // index[278] PINMUX_DIO_PAD_SLEEP_REGWEN_35 + 4'b 0001, // index[279] PINMUX_DIO_PAD_SLEEP_REGWEN_36 + 4'b 0001, // index[280] PINMUX_DIO_PAD_SLEEP_REGWEN_37 + 4'b 0001, // index[281] PINMUX_DIO_PAD_SLEEP_REGWEN_38 + 4'b 0001, // index[282] PINMUX_DIO_PAD_SLEEP_REGWEN_39 + 4'b 0001, // index[283] PINMUX_DIO_PAD_SLEEP_REGWEN_40 + 4'b 0001, // index[284] PINMUX_DIO_PAD_SLEEP_REGWEN_41 + 4'b 0001, // index[285] PINMUX_DIO_PAD_SLEEP_REGWEN_42 + 4'b 0001, // index[286] PINMUX_DIO_PAD_SLEEP_REGWEN_43 + 4'b 0001, // index[287] PINMUX_DIO_PAD_SLEEP_REGWEN_44 + 4'b 0001, // index[288] PINMUX_DIO_PAD_SLEEP_REGWEN_45 + 4'b 0001, // index[289] PINMUX_DIO_PAD_SLEEP_REGWEN_46 + 4'b 0001, // index[290] PINMUX_DIO_PAD_SLEEP_REGWEN_47 + 4'b 0001, // index[291] PINMUX_DIO_PAD_SLEEP_REGWEN_48 + 4'b 0001, // index[292] PINMUX_DIO_PAD_SLEEP_REGWEN_49 + 4'b 0001, // index[293] PINMUX_DIO_PAD_SLEEP_REGWEN_50 + 4'b 0001, // index[294] PINMUX_DIO_PAD_SLEEP_REGWEN_51 + 4'b 0001, // index[295] PINMUX_DIO_PAD_SLEEP_REGWEN_52 + 4'b 0001, // index[296] PINMUX_DIO_PAD_SLEEP_REGWEN_53 + 4'b 0001, // index[297] PINMUX_DIO_PAD_SLEEP_REGWEN_54 + 4'b 0001, // index[298] PINMUX_DIO_PAD_SLEEP_REGWEN_55 + 4'b 0001, // index[299] PINMUX_DIO_PAD_SLEEP_REGWEN_56 + 4'b 0001, // index[300] PINMUX_DIO_PAD_SLEEP_REGWEN_57 + 4'b 0001, // index[301] PINMUX_DIO_PAD_SLEEP_REGWEN_58 + 4'b 0001, // index[302] PINMUX_DIO_PAD_SLEEP_REGWEN_59 + 4'b 0001, // index[303] PINMUX_DIO_PAD_SLEEP_REGWEN_60 + 4'b 0001, // index[304] PINMUX_DIO_PAD_SLEEP_REGWEN_61 + 4'b 0001, // index[305] PINMUX_DIO_PAD_SLEEP_REGWEN_62 + 4'b 0001, // index[306] PINMUX_DIO_PAD_SLEEP_REGWEN_63 + 4'b 0001, // index[307] PINMUX_DIO_PAD_SLEEP_REGWEN_64 + 4'b 0001, // index[308] PINMUX_DIO_PAD_SLEEP_REGWEN_65 + 4'b 0001, // index[309] PINMUX_DIO_PAD_SLEEP_REGWEN_66 + 4'b 0001, // index[310] PINMUX_DIO_PAD_SLEEP_REGWEN_67 + 4'b 0001, // index[311] PINMUX_DIO_PAD_SLEEP_REGWEN_68 + 4'b 0001, // index[312] PINMUX_DIO_PAD_SLEEP_REGWEN_69 + 4'b 0001, // index[313] PINMUX_DIO_PAD_SLEEP_REGWEN_70 + 4'b 0001, // index[314] PINMUX_DIO_PAD_SLEEP_REGWEN_71 + 4'b 0001, // index[315] PINMUX_DIO_PAD_SLEEP_REGWEN_72 + 4'b 0001, // index[316] PINMUX_DIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[317] PINMUX_DIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[318] PINMUX_DIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[319] PINMUX_DIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[320] PINMUX_DIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[321] PINMUX_DIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[322] PINMUX_DIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[323] PINMUX_DIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[324] PINMUX_DIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[325] PINMUX_DIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[326] PINMUX_DIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[327] PINMUX_DIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[328] PINMUX_DIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[329] PINMUX_DIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[330] PINMUX_DIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[331] PINMUX_DIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[332] PINMUX_DIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[333] PINMUX_DIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[334] PINMUX_DIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[335] PINMUX_DIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[336] PINMUX_DIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[337] PINMUX_DIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[338] PINMUX_DIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[339] PINMUX_DIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[340] PINMUX_DIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[341] PINMUX_DIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[342] PINMUX_DIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[343] PINMUX_DIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[344] PINMUX_DIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[345] PINMUX_DIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[346] PINMUX_DIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[347] PINMUX_DIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[348] PINMUX_DIO_PAD_SLEEP_EN_32 + 4'b 0001, // index[349] PINMUX_DIO_PAD_SLEEP_EN_33 + 4'b 0001, // index[350] PINMUX_DIO_PAD_SLEEP_EN_34 + 4'b 0001, // index[351] PINMUX_DIO_PAD_SLEEP_EN_35 + 4'b 0001, // index[352] PINMUX_DIO_PAD_SLEEP_EN_36 + 4'b 0001, // index[353] PINMUX_DIO_PAD_SLEEP_EN_37 + 4'b 0001, // index[354] PINMUX_DIO_PAD_SLEEP_EN_38 + 4'b 0001, // index[355] PINMUX_DIO_PAD_SLEEP_EN_39 + 4'b 0001, // index[356] PINMUX_DIO_PAD_SLEEP_EN_40 + 4'b 0001, // index[357] PINMUX_DIO_PAD_SLEEP_EN_41 + 4'b 0001, // index[358] PINMUX_DIO_PAD_SLEEP_EN_42 + 4'b 0001, // index[359] PINMUX_DIO_PAD_SLEEP_EN_43 + 4'b 0001, // index[360] PINMUX_DIO_PAD_SLEEP_EN_44 + 4'b 0001, // index[361] PINMUX_DIO_PAD_SLEEP_EN_45 + 4'b 0001, // index[362] PINMUX_DIO_PAD_SLEEP_EN_46 + 4'b 0001, // index[363] PINMUX_DIO_PAD_SLEEP_EN_47 + 4'b 0001, // index[364] PINMUX_DIO_PAD_SLEEP_EN_48 + 4'b 0001, // index[365] PINMUX_DIO_PAD_SLEEP_EN_49 + 4'b 0001, // index[366] PINMUX_DIO_PAD_SLEEP_EN_50 + 4'b 0001, // index[367] PINMUX_DIO_PAD_SLEEP_EN_51 + 4'b 0001, // index[368] PINMUX_DIO_PAD_SLEEP_EN_52 + 4'b 0001, // index[369] PINMUX_DIO_PAD_SLEEP_EN_53 + 4'b 0001, // index[370] PINMUX_DIO_PAD_SLEEP_EN_54 + 4'b 0001, // index[371] PINMUX_DIO_PAD_SLEEP_EN_55 + 4'b 0001, // index[372] PINMUX_DIO_PAD_SLEEP_EN_56 + 4'b 0001, // index[373] PINMUX_DIO_PAD_SLEEP_EN_57 + 4'b 0001, // index[374] PINMUX_DIO_PAD_SLEEP_EN_58 + 4'b 0001, // index[375] PINMUX_DIO_PAD_SLEEP_EN_59 + 4'b 0001, // index[376] PINMUX_DIO_PAD_SLEEP_EN_60 + 4'b 0001, // index[377] PINMUX_DIO_PAD_SLEEP_EN_61 + 4'b 0001, // index[378] PINMUX_DIO_PAD_SLEEP_EN_62 + 4'b 0001, // index[379] PINMUX_DIO_PAD_SLEEP_EN_63 + 4'b 0001, // index[380] PINMUX_DIO_PAD_SLEEP_EN_64 + 4'b 0001, // index[381] PINMUX_DIO_PAD_SLEEP_EN_65 + 4'b 0001, // index[382] PINMUX_DIO_PAD_SLEEP_EN_66 + 4'b 0001, // index[383] PINMUX_DIO_PAD_SLEEP_EN_67 + 4'b 0001, // index[384] PINMUX_DIO_PAD_SLEEP_EN_68 + 4'b 0001, // index[385] PINMUX_DIO_PAD_SLEEP_EN_69 + 4'b 0001, // index[386] PINMUX_DIO_PAD_SLEEP_EN_70 + 4'b 0001, // index[387] PINMUX_DIO_PAD_SLEEP_EN_71 + 4'b 0001, // index[388] PINMUX_DIO_PAD_SLEEP_EN_72 + 4'b 0001, // index[389] PINMUX_DIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[390] PINMUX_DIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[391] PINMUX_DIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[392] PINMUX_DIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[393] PINMUX_DIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[394] PINMUX_DIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[395] PINMUX_DIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[396] PINMUX_DIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[397] PINMUX_DIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[398] PINMUX_DIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[399] PINMUX_DIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[400] PINMUX_DIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[401] PINMUX_DIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[402] PINMUX_DIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[403] PINMUX_DIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[404] PINMUX_DIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[405] PINMUX_DIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[406] PINMUX_DIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[407] PINMUX_DIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[408] PINMUX_DIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[409] PINMUX_DIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[410] PINMUX_DIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[411] PINMUX_DIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[412] PINMUX_DIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[413] PINMUX_DIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[414] PINMUX_DIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[415] PINMUX_DIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[416] PINMUX_DIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[417] PINMUX_DIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[418] PINMUX_DIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[419] PINMUX_DIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[420] PINMUX_DIO_PAD_SLEEP_MODE_31 + 4'b 0001, // index[421] PINMUX_DIO_PAD_SLEEP_MODE_32 + 4'b 0001, // index[422] PINMUX_DIO_PAD_SLEEP_MODE_33 + 4'b 0001, // index[423] PINMUX_DIO_PAD_SLEEP_MODE_34 + 4'b 0001, // index[424] PINMUX_DIO_PAD_SLEEP_MODE_35 + 4'b 0001, // index[425] PINMUX_DIO_PAD_SLEEP_MODE_36 + 4'b 0001, // index[426] PINMUX_DIO_PAD_SLEEP_MODE_37 + 4'b 0001, // index[427] PINMUX_DIO_PAD_SLEEP_MODE_38 + 4'b 0001, // index[428] PINMUX_DIO_PAD_SLEEP_MODE_39 + 4'b 0001, // index[429] PINMUX_DIO_PAD_SLEEP_MODE_40 + 4'b 0001, // index[430] PINMUX_DIO_PAD_SLEEP_MODE_41 + 4'b 0001, // index[431] PINMUX_DIO_PAD_SLEEP_MODE_42 + 4'b 0001, // index[432] PINMUX_DIO_PAD_SLEEP_MODE_43 + 4'b 0001, // index[433] PINMUX_DIO_PAD_SLEEP_MODE_44 + 4'b 0001, // index[434] PINMUX_DIO_PAD_SLEEP_MODE_45 + 4'b 0001, // index[435] PINMUX_DIO_PAD_SLEEP_MODE_46 + 4'b 0001, // index[436] PINMUX_DIO_PAD_SLEEP_MODE_47 + 4'b 0001, // index[437] PINMUX_DIO_PAD_SLEEP_MODE_48 + 4'b 0001, // index[438] PINMUX_DIO_PAD_SLEEP_MODE_49 + 4'b 0001, // index[439] PINMUX_DIO_PAD_SLEEP_MODE_50 + 4'b 0001, // index[440] PINMUX_DIO_PAD_SLEEP_MODE_51 + 4'b 0001, // index[441] PINMUX_DIO_PAD_SLEEP_MODE_52 + 4'b 0001, // index[442] PINMUX_DIO_PAD_SLEEP_MODE_53 + 4'b 0001, // index[443] PINMUX_DIO_PAD_SLEEP_MODE_54 + 4'b 0001, // index[444] PINMUX_DIO_PAD_SLEEP_MODE_55 + 4'b 0001, // index[445] PINMUX_DIO_PAD_SLEEP_MODE_56 + 4'b 0001, // index[446] PINMUX_DIO_PAD_SLEEP_MODE_57 + 4'b 0001, // index[447] PINMUX_DIO_PAD_SLEEP_MODE_58 + 4'b 0001, // index[448] PINMUX_DIO_PAD_SLEEP_MODE_59 + 4'b 0001, // index[449] PINMUX_DIO_PAD_SLEEP_MODE_60 + 4'b 0001, // index[450] PINMUX_DIO_PAD_SLEEP_MODE_61 + 4'b 0001, // index[451] PINMUX_DIO_PAD_SLEEP_MODE_62 + 4'b 0001, // index[452] PINMUX_DIO_PAD_SLEEP_MODE_63 + 4'b 0001, // index[453] PINMUX_DIO_PAD_SLEEP_MODE_64 + 4'b 0001, // index[454] PINMUX_DIO_PAD_SLEEP_MODE_65 + 4'b 0001, // index[455] PINMUX_DIO_PAD_SLEEP_MODE_66 + 4'b 0001, // index[456] PINMUX_DIO_PAD_SLEEP_MODE_67 + 4'b 0001, // index[457] PINMUX_DIO_PAD_SLEEP_MODE_68 + 4'b 0001, // index[458] PINMUX_DIO_PAD_SLEEP_MODE_69 + 4'b 0001, // index[459] PINMUX_DIO_PAD_SLEEP_MODE_70 + 4'b 0001, // index[460] PINMUX_DIO_PAD_SLEEP_MODE_71 + 4'b 0001, // index[461] PINMUX_DIO_PAD_SLEEP_MODE_72 + 4'b 0001, // index[462] PINMUX_WKUP_DETECTOR_REGWEN_0 + 4'b 0001, // index[463] PINMUX_WKUP_DETECTOR_REGWEN_1 + 4'b 0001, // index[464] PINMUX_WKUP_DETECTOR_REGWEN_2 + 4'b 0001, // index[465] PINMUX_WKUP_DETECTOR_REGWEN_3 + 4'b 0001, // index[466] PINMUX_WKUP_DETECTOR_REGWEN_4 + 4'b 0001, // index[467] PINMUX_WKUP_DETECTOR_REGWEN_5 + 4'b 0001, // index[468] PINMUX_WKUP_DETECTOR_REGWEN_6 + 4'b 0001, // index[469] PINMUX_WKUP_DETECTOR_REGWEN_7 + 4'b 0001, // index[470] PINMUX_WKUP_DETECTOR_EN_0 + 4'b 0001, // index[471] PINMUX_WKUP_DETECTOR_EN_1 + 4'b 0001, // index[472] PINMUX_WKUP_DETECTOR_EN_2 + 4'b 0001, // index[473] PINMUX_WKUP_DETECTOR_EN_3 + 4'b 0001, // index[474] PINMUX_WKUP_DETECTOR_EN_4 + 4'b 0001, // index[475] PINMUX_WKUP_DETECTOR_EN_5 + 4'b 0001, // index[476] PINMUX_WKUP_DETECTOR_EN_6 + 4'b 0001, // index[477] PINMUX_WKUP_DETECTOR_EN_7 + 4'b 0001, // index[478] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[479] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[480] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[481] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[482] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[483] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[484] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[485] PINMUX_WKUP_DETECTOR_7 + 4'b 0001, // index[486] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 0001, // index[487] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 0001, // index[488] PINMUX_WKUP_DETECTOR_CNT_TH_2 + 4'b 0001, // index[489] PINMUX_WKUP_DETECTOR_CNT_TH_3 + 4'b 0001, // index[490] PINMUX_WKUP_DETECTOR_CNT_TH_4 + 4'b 0001, // index[491] PINMUX_WKUP_DETECTOR_CNT_TH_5 + 4'b 0001, // index[492] PINMUX_WKUP_DETECTOR_CNT_TH_6 + 4'b 0001, // index[493] PINMUX_WKUP_DETECTOR_CNT_TH_7 + 4'b 0001, // index[494] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0001, // index[495] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001, // index[496] PINMUX_WKUP_DETECTOR_PADSEL_2 + 4'b 0001, // index[497] PINMUX_WKUP_DETECTOR_PADSEL_3 + 4'b 0001, // index[498] PINMUX_WKUP_DETECTOR_PADSEL_4 + 4'b 0001, // index[499] PINMUX_WKUP_DETECTOR_PADSEL_5 + 4'b 0001, // index[500] PINMUX_WKUP_DETECTOR_PADSEL_6 + 4'b 0001, // index[501] PINMUX_WKUP_DETECTOR_PADSEL_7 + 4'b 0001 // index[502] PINMUX_WKUP_CAUSE + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_reg_top.sv new file mode 100644 index 00000000000..405c1fda353 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_reg_top.sv @@ -0,0 +1,42192 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module pinmux_reg_top ( + input clk_i, + input rst_ni, + input clk_aon_i, + input rst_aon_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write + input pinmux_reg_pkg::pinmux_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import pinmux_reg_pkg::* ; + + localparam int AW = 11; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [502:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(503) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic alert_test_we; + logic alert_test_wd; + logic mio_periph_insel_regwen_0_we; + logic mio_periph_insel_regwen_0_qs; + logic mio_periph_insel_regwen_0_wd; + logic mio_periph_insel_regwen_1_we; + logic mio_periph_insel_regwen_1_qs; + logic mio_periph_insel_regwen_1_wd; + logic mio_periph_insel_regwen_2_we; + logic mio_periph_insel_regwen_2_qs; + logic mio_periph_insel_regwen_2_wd; + logic mio_periph_insel_regwen_3_we; + logic mio_periph_insel_regwen_3_qs; + logic mio_periph_insel_regwen_3_wd; + logic mio_periph_insel_0_we; + logic [3:0] mio_periph_insel_0_qs; + logic [3:0] mio_periph_insel_0_wd; + logic mio_periph_insel_1_we; + logic [3:0] mio_periph_insel_1_qs; + logic [3:0] mio_periph_insel_1_wd; + logic mio_periph_insel_2_we; + logic [3:0] mio_periph_insel_2_qs; + logic [3:0] mio_periph_insel_2_wd; + logic mio_periph_insel_3_we; + logic [3:0] mio_periph_insel_3_qs; + logic [3:0] mio_periph_insel_3_wd; + logic mio_outsel_regwen_0_we; + logic mio_outsel_regwen_0_qs; + logic mio_outsel_regwen_0_wd; + logic mio_outsel_regwen_1_we; + logic mio_outsel_regwen_1_qs; + logic mio_outsel_regwen_1_wd; + logic mio_outsel_regwen_2_we; + logic mio_outsel_regwen_2_qs; + logic mio_outsel_regwen_2_wd; + logic mio_outsel_regwen_3_we; + logic mio_outsel_regwen_3_qs; + logic mio_outsel_regwen_3_wd; + logic mio_outsel_regwen_4_we; + logic mio_outsel_regwen_4_qs; + logic mio_outsel_regwen_4_wd; + logic mio_outsel_regwen_5_we; + logic mio_outsel_regwen_5_qs; + logic mio_outsel_regwen_5_wd; + logic mio_outsel_regwen_6_we; + logic mio_outsel_regwen_6_qs; + logic mio_outsel_regwen_6_wd; + logic mio_outsel_regwen_7_we; + logic mio_outsel_regwen_7_qs; + logic mio_outsel_regwen_7_wd; + logic mio_outsel_regwen_8_we; + logic mio_outsel_regwen_8_qs; + logic mio_outsel_regwen_8_wd; + logic mio_outsel_regwen_9_we; + logic mio_outsel_regwen_9_qs; + logic mio_outsel_regwen_9_wd; + logic mio_outsel_regwen_10_we; + logic mio_outsel_regwen_10_qs; + logic mio_outsel_regwen_10_wd; + logic mio_outsel_regwen_11_we; + logic mio_outsel_regwen_11_qs; + logic mio_outsel_regwen_11_wd; + logic mio_outsel_0_we; + logic [2:0] mio_outsel_0_qs; + logic [2:0] mio_outsel_0_wd; + logic mio_outsel_1_we; + logic [2:0] mio_outsel_1_qs; + logic [2:0] mio_outsel_1_wd; + logic mio_outsel_2_we; + logic [2:0] mio_outsel_2_qs; + logic [2:0] mio_outsel_2_wd; + logic mio_outsel_3_we; + logic [2:0] mio_outsel_3_qs; + logic [2:0] mio_outsel_3_wd; + logic mio_outsel_4_we; + logic [2:0] mio_outsel_4_qs; + logic [2:0] mio_outsel_4_wd; + logic mio_outsel_5_we; + logic [2:0] mio_outsel_5_qs; + logic [2:0] mio_outsel_5_wd; + logic mio_outsel_6_we; + logic [2:0] mio_outsel_6_qs; + logic [2:0] mio_outsel_6_wd; + logic mio_outsel_7_we; + logic [2:0] mio_outsel_7_qs; + logic [2:0] mio_outsel_7_wd; + logic mio_outsel_8_we; + logic [2:0] mio_outsel_8_qs; + logic [2:0] mio_outsel_8_wd; + logic mio_outsel_9_we; + logic [2:0] mio_outsel_9_qs; + logic [2:0] mio_outsel_9_wd; + logic mio_outsel_10_we; + logic [2:0] mio_outsel_10_qs; + logic [2:0] mio_outsel_10_wd; + logic mio_outsel_11_we; + logic [2:0] mio_outsel_11_qs; + logic [2:0] mio_outsel_11_wd; + logic mio_pad_attr_regwen_0_we; + logic mio_pad_attr_regwen_0_qs; + logic mio_pad_attr_regwen_0_wd; + logic mio_pad_attr_regwen_1_we; + logic mio_pad_attr_regwen_1_qs; + logic mio_pad_attr_regwen_1_wd; + logic mio_pad_attr_regwen_2_we; + logic mio_pad_attr_regwen_2_qs; + logic mio_pad_attr_regwen_2_wd; + logic mio_pad_attr_regwen_3_we; + logic mio_pad_attr_regwen_3_qs; + logic mio_pad_attr_regwen_3_wd; + logic mio_pad_attr_regwen_4_we; + logic mio_pad_attr_regwen_4_qs; + logic mio_pad_attr_regwen_4_wd; + logic mio_pad_attr_regwen_5_we; + logic mio_pad_attr_regwen_5_qs; + logic mio_pad_attr_regwen_5_wd; + logic mio_pad_attr_regwen_6_we; + logic mio_pad_attr_regwen_6_qs; + logic mio_pad_attr_regwen_6_wd; + logic mio_pad_attr_regwen_7_we; + logic mio_pad_attr_regwen_7_qs; + logic mio_pad_attr_regwen_7_wd; + logic mio_pad_attr_regwen_8_we; + logic mio_pad_attr_regwen_8_qs; + logic mio_pad_attr_regwen_8_wd; + logic mio_pad_attr_regwen_9_we; + logic mio_pad_attr_regwen_9_qs; + logic mio_pad_attr_regwen_9_wd; + logic mio_pad_attr_regwen_10_we; + logic mio_pad_attr_regwen_10_qs; + logic mio_pad_attr_regwen_10_wd; + logic mio_pad_attr_regwen_11_we; + logic mio_pad_attr_regwen_11_qs; + logic mio_pad_attr_regwen_11_wd; + logic mio_pad_attr_0_re; + logic mio_pad_attr_0_we; + logic mio_pad_attr_0_invert_0_qs; + logic mio_pad_attr_0_invert_0_wd; + logic mio_pad_attr_0_virtual_od_en_0_qs; + logic mio_pad_attr_0_virtual_od_en_0_wd; + logic mio_pad_attr_0_pull_en_0_qs; + logic mio_pad_attr_0_pull_en_0_wd; + logic mio_pad_attr_0_pull_select_0_qs; + logic mio_pad_attr_0_pull_select_0_wd; + logic mio_pad_attr_0_keeper_en_0_qs; + logic mio_pad_attr_0_keeper_en_0_wd; + logic mio_pad_attr_0_schmitt_en_0_qs; + logic mio_pad_attr_0_schmitt_en_0_wd; + logic mio_pad_attr_0_od_en_0_qs; + logic mio_pad_attr_0_od_en_0_wd; + logic mio_pad_attr_0_input_disable_0_qs; + logic mio_pad_attr_0_input_disable_0_wd; + logic [1:0] mio_pad_attr_0_slew_rate_0_qs; + logic [1:0] mio_pad_attr_0_slew_rate_0_wd; + logic [3:0] mio_pad_attr_0_drive_strength_0_qs; + logic [3:0] mio_pad_attr_0_drive_strength_0_wd; + logic mio_pad_attr_1_re; + logic mio_pad_attr_1_we; + logic mio_pad_attr_1_invert_1_qs; + logic mio_pad_attr_1_invert_1_wd; + logic mio_pad_attr_1_virtual_od_en_1_qs; + logic mio_pad_attr_1_virtual_od_en_1_wd; + logic mio_pad_attr_1_pull_en_1_qs; + logic mio_pad_attr_1_pull_en_1_wd; + logic mio_pad_attr_1_pull_select_1_qs; + logic mio_pad_attr_1_pull_select_1_wd; + logic mio_pad_attr_1_keeper_en_1_qs; + logic mio_pad_attr_1_keeper_en_1_wd; + logic mio_pad_attr_1_schmitt_en_1_qs; + logic mio_pad_attr_1_schmitt_en_1_wd; + logic mio_pad_attr_1_od_en_1_qs; + logic mio_pad_attr_1_od_en_1_wd; + logic mio_pad_attr_1_input_disable_1_qs; + logic mio_pad_attr_1_input_disable_1_wd; + logic [1:0] mio_pad_attr_1_slew_rate_1_qs; + logic [1:0] mio_pad_attr_1_slew_rate_1_wd; + logic [3:0] mio_pad_attr_1_drive_strength_1_qs; + logic [3:0] mio_pad_attr_1_drive_strength_1_wd; + logic mio_pad_attr_2_re; + logic mio_pad_attr_2_we; + logic mio_pad_attr_2_invert_2_qs; + logic mio_pad_attr_2_invert_2_wd; + logic mio_pad_attr_2_virtual_od_en_2_qs; + logic mio_pad_attr_2_virtual_od_en_2_wd; + logic mio_pad_attr_2_pull_en_2_qs; + logic mio_pad_attr_2_pull_en_2_wd; + logic mio_pad_attr_2_pull_select_2_qs; + logic mio_pad_attr_2_pull_select_2_wd; + logic mio_pad_attr_2_keeper_en_2_qs; + logic mio_pad_attr_2_keeper_en_2_wd; + logic mio_pad_attr_2_schmitt_en_2_qs; + logic mio_pad_attr_2_schmitt_en_2_wd; + logic mio_pad_attr_2_od_en_2_qs; + logic mio_pad_attr_2_od_en_2_wd; + logic mio_pad_attr_2_input_disable_2_qs; + logic mio_pad_attr_2_input_disable_2_wd; + logic [1:0] mio_pad_attr_2_slew_rate_2_qs; + logic [1:0] mio_pad_attr_2_slew_rate_2_wd; + logic [3:0] mio_pad_attr_2_drive_strength_2_qs; + logic [3:0] mio_pad_attr_2_drive_strength_2_wd; + logic mio_pad_attr_3_re; + logic mio_pad_attr_3_we; + logic mio_pad_attr_3_invert_3_qs; + logic mio_pad_attr_3_invert_3_wd; + logic mio_pad_attr_3_virtual_od_en_3_qs; + logic mio_pad_attr_3_virtual_od_en_3_wd; + logic mio_pad_attr_3_pull_en_3_qs; + logic mio_pad_attr_3_pull_en_3_wd; + logic mio_pad_attr_3_pull_select_3_qs; + logic mio_pad_attr_3_pull_select_3_wd; + logic mio_pad_attr_3_keeper_en_3_qs; + logic mio_pad_attr_3_keeper_en_3_wd; + logic mio_pad_attr_3_schmitt_en_3_qs; + logic mio_pad_attr_3_schmitt_en_3_wd; + logic mio_pad_attr_3_od_en_3_qs; + logic mio_pad_attr_3_od_en_3_wd; + logic mio_pad_attr_3_input_disable_3_qs; + logic mio_pad_attr_3_input_disable_3_wd; + logic [1:0] mio_pad_attr_3_slew_rate_3_qs; + logic [1:0] mio_pad_attr_3_slew_rate_3_wd; + logic [3:0] mio_pad_attr_3_drive_strength_3_qs; + logic [3:0] mio_pad_attr_3_drive_strength_3_wd; + logic mio_pad_attr_4_re; + logic mio_pad_attr_4_we; + logic mio_pad_attr_4_invert_4_qs; + logic mio_pad_attr_4_invert_4_wd; + logic mio_pad_attr_4_virtual_od_en_4_qs; + logic mio_pad_attr_4_virtual_od_en_4_wd; + logic mio_pad_attr_4_pull_en_4_qs; + logic mio_pad_attr_4_pull_en_4_wd; + logic mio_pad_attr_4_pull_select_4_qs; + logic mio_pad_attr_4_pull_select_4_wd; + logic mio_pad_attr_4_keeper_en_4_qs; + logic mio_pad_attr_4_keeper_en_4_wd; + logic mio_pad_attr_4_schmitt_en_4_qs; + logic mio_pad_attr_4_schmitt_en_4_wd; + logic mio_pad_attr_4_od_en_4_qs; + logic mio_pad_attr_4_od_en_4_wd; + logic mio_pad_attr_4_input_disable_4_qs; + logic mio_pad_attr_4_input_disable_4_wd; + logic [1:0] mio_pad_attr_4_slew_rate_4_qs; + logic [1:0] mio_pad_attr_4_slew_rate_4_wd; + logic [3:0] mio_pad_attr_4_drive_strength_4_qs; + logic [3:0] mio_pad_attr_4_drive_strength_4_wd; + logic mio_pad_attr_5_re; + logic mio_pad_attr_5_we; + logic mio_pad_attr_5_invert_5_qs; + logic mio_pad_attr_5_invert_5_wd; + logic mio_pad_attr_5_virtual_od_en_5_qs; + logic mio_pad_attr_5_virtual_od_en_5_wd; + logic mio_pad_attr_5_pull_en_5_qs; + logic mio_pad_attr_5_pull_en_5_wd; + logic mio_pad_attr_5_pull_select_5_qs; + logic mio_pad_attr_5_pull_select_5_wd; + logic mio_pad_attr_5_keeper_en_5_qs; + logic mio_pad_attr_5_keeper_en_5_wd; + logic mio_pad_attr_5_schmitt_en_5_qs; + logic mio_pad_attr_5_schmitt_en_5_wd; + logic mio_pad_attr_5_od_en_5_qs; + logic mio_pad_attr_5_od_en_5_wd; + logic mio_pad_attr_5_input_disable_5_qs; + logic mio_pad_attr_5_input_disable_5_wd; + logic [1:0] mio_pad_attr_5_slew_rate_5_qs; + logic [1:0] mio_pad_attr_5_slew_rate_5_wd; + logic [3:0] mio_pad_attr_5_drive_strength_5_qs; + logic [3:0] mio_pad_attr_5_drive_strength_5_wd; + logic mio_pad_attr_6_re; + logic mio_pad_attr_6_we; + logic mio_pad_attr_6_invert_6_qs; + logic mio_pad_attr_6_invert_6_wd; + logic mio_pad_attr_6_virtual_od_en_6_qs; + logic mio_pad_attr_6_virtual_od_en_6_wd; + logic mio_pad_attr_6_pull_en_6_qs; + logic mio_pad_attr_6_pull_en_6_wd; + logic mio_pad_attr_6_pull_select_6_qs; + logic mio_pad_attr_6_pull_select_6_wd; + logic mio_pad_attr_6_keeper_en_6_qs; + logic mio_pad_attr_6_keeper_en_6_wd; + logic mio_pad_attr_6_schmitt_en_6_qs; + logic mio_pad_attr_6_schmitt_en_6_wd; + logic mio_pad_attr_6_od_en_6_qs; + logic mio_pad_attr_6_od_en_6_wd; + logic mio_pad_attr_6_input_disable_6_qs; + logic mio_pad_attr_6_input_disable_6_wd; + logic [1:0] mio_pad_attr_6_slew_rate_6_qs; + logic [1:0] mio_pad_attr_6_slew_rate_6_wd; + logic [3:0] mio_pad_attr_6_drive_strength_6_qs; + logic [3:0] mio_pad_attr_6_drive_strength_6_wd; + logic mio_pad_attr_7_re; + logic mio_pad_attr_7_we; + logic mio_pad_attr_7_invert_7_qs; + logic mio_pad_attr_7_invert_7_wd; + logic mio_pad_attr_7_virtual_od_en_7_qs; + logic mio_pad_attr_7_virtual_od_en_7_wd; + logic mio_pad_attr_7_pull_en_7_qs; + logic mio_pad_attr_7_pull_en_7_wd; + logic mio_pad_attr_7_pull_select_7_qs; + logic mio_pad_attr_7_pull_select_7_wd; + logic mio_pad_attr_7_keeper_en_7_qs; + logic mio_pad_attr_7_keeper_en_7_wd; + logic mio_pad_attr_7_schmitt_en_7_qs; + logic mio_pad_attr_7_schmitt_en_7_wd; + logic mio_pad_attr_7_od_en_7_qs; + logic mio_pad_attr_7_od_en_7_wd; + logic mio_pad_attr_7_input_disable_7_qs; + logic mio_pad_attr_7_input_disable_7_wd; + logic [1:0] mio_pad_attr_7_slew_rate_7_qs; + logic [1:0] mio_pad_attr_7_slew_rate_7_wd; + logic [3:0] mio_pad_attr_7_drive_strength_7_qs; + logic [3:0] mio_pad_attr_7_drive_strength_7_wd; + logic mio_pad_attr_8_re; + logic mio_pad_attr_8_we; + logic mio_pad_attr_8_invert_8_qs; + logic mio_pad_attr_8_invert_8_wd; + logic mio_pad_attr_8_virtual_od_en_8_qs; + logic mio_pad_attr_8_virtual_od_en_8_wd; + logic mio_pad_attr_8_pull_en_8_qs; + logic mio_pad_attr_8_pull_en_8_wd; + logic mio_pad_attr_8_pull_select_8_qs; + logic mio_pad_attr_8_pull_select_8_wd; + logic mio_pad_attr_8_keeper_en_8_qs; + logic mio_pad_attr_8_keeper_en_8_wd; + logic mio_pad_attr_8_schmitt_en_8_qs; + logic mio_pad_attr_8_schmitt_en_8_wd; + logic mio_pad_attr_8_od_en_8_qs; + logic mio_pad_attr_8_od_en_8_wd; + logic mio_pad_attr_8_input_disable_8_qs; + logic mio_pad_attr_8_input_disable_8_wd; + logic [1:0] mio_pad_attr_8_slew_rate_8_qs; + logic [1:0] mio_pad_attr_8_slew_rate_8_wd; + logic [3:0] mio_pad_attr_8_drive_strength_8_qs; + logic [3:0] mio_pad_attr_8_drive_strength_8_wd; + logic mio_pad_attr_9_re; + logic mio_pad_attr_9_we; + logic mio_pad_attr_9_invert_9_qs; + logic mio_pad_attr_9_invert_9_wd; + logic mio_pad_attr_9_virtual_od_en_9_qs; + logic mio_pad_attr_9_virtual_od_en_9_wd; + logic mio_pad_attr_9_pull_en_9_qs; + logic mio_pad_attr_9_pull_en_9_wd; + logic mio_pad_attr_9_pull_select_9_qs; + logic mio_pad_attr_9_pull_select_9_wd; + logic mio_pad_attr_9_keeper_en_9_qs; + logic mio_pad_attr_9_keeper_en_9_wd; + logic mio_pad_attr_9_schmitt_en_9_qs; + logic mio_pad_attr_9_schmitt_en_9_wd; + logic mio_pad_attr_9_od_en_9_qs; + logic mio_pad_attr_9_od_en_9_wd; + logic mio_pad_attr_9_input_disable_9_qs; + logic mio_pad_attr_9_input_disable_9_wd; + logic [1:0] mio_pad_attr_9_slew_rate_9_qs; + logic [1:0] mio_pad_attr_9_slew_rate_9_wd; + logic [3:0] mio_pad_attr_9_drive_strength_9_qs; + logic [3:0] mio_pad_attr_9_drive_strength_9_wd; + logic mio_pad_attr_10_re; + logic mio_pad_attr_10_we; + logic mio_pad_attr_10_invert_10_qs; + logic mio_pad_attr_10_invert_10_wd; + logic mio_pad_attr_10_virtual_od_en_10_qs; + logic mio_pad_attr_10_virtual_od_en_10_wd; + logic mio_pad_attr_10_pull_en_10_qs; + logic mio_pad_attr_10_pull_en_10_wd; + logic mio_pad_attr_10_pull_select_10_qs; + logic mio_pad_attr_10_pull_select_10_wd; + logic mio_pad_attr_10_keeper_en_10_qs; + logic mio_pad_attr_10_keeper_en_10_wd; + logic mio_pad_attr_10_schmitt_en_10_qs; + logic mio_pad_attr_10_schmitt_en_10_wd; + logic mio_pad_attr_10_od_en_10_qs; + logic mio_pad_attr_10_od_en_10_wd; + logic mio_pad_attr_10_input_disable_10_qs; + logic mio_pad_attr_10_input_disable_10_wd; + logic [1:0] mio_pad_attr_10_slew_rate_10_qs; + logic [1:0] mio_pad_attr_10_slew_rate_10_wd; + logic [3:0] mio_pad_attr_10_drive_strength_10_qs; + logic [3:0] mio_pad_attr_10_drive_strength_10_wd; + logic mio_pad_attr_11_re; + logic mio_pad_attr_11_we; + logic mio_pad_attr_11_invert_11_qs; + logic mio_pad_attr_11_invert_11_wd; + logic mio_pad_attr_11_virtual_od_en_11_qs; + logic mio_pad_attr_11_virtual_od_en_11_wd; + logic mio_pad_attr_11_pull_en_11_qs; + logic mio_pad_attr_11_pull_en_11_wd; + logic mio_pad_attr_11_pull_select_11_qs; + logic mio_pad_attr_11_pull_select_11_wd; + logic mio_pad_attr_11_keeper_en_11_qs; + logic mio_pad_attr_11_keeper_en_11_wd; + logic mio_pad_attr_11_schmitt_en_11_qs; + logic mio_pad_attr_11_schmitt_en_11_wd; + logic mio_pad_attr_11_od_en_11_qs; + logic mio_pad_attr_11_od_en_11_wd; + logic mio_pad_attr_11_input_disable_11_qs; + logic mio_pad_attr_11_input_disable_11_wd; + logic [1:0] mio_pad_attr_11_slew_rate_11_qs; + logic [1:0] mio_pad_attr_11_slew_rate_11_wd; + logic [3:0] mio_pad_attr_11_drive_strength_11_qs; + logic [3:0] mio_pad_attr_11_drive_strength_11_wd; + logic dio_pad_attr_regwen_0_we; + logic dio_pad_attr_regwen_0_qs; + logic dio_pad_attr_regwen_0_wd; + logic dio_pad_attr_regwen_1_we; + logic dio_pad_attr_regwen_1_qs; + logic dio_pad_attr_regwen_1_wd; + logic dio_pad_attr_regwen_2_we; + logic dio_pad_attr_regwen_2_qs; + logic dio_pad_attr_regwen_2_wd; + logic dio_pad_attr_regwen_3_we; + logic dio_pad_attr_regwen_3_qs; + logic dio_pad_attr_regwen_3_wd; + logic dio_pad_attr_regwen_4_we; + logic dio_pad_attr_regwen_4_qs; + logic dio_pad_attr_regwen_4_wd; + logic dio_pad_attr_regwen_5_we; + logic dio_pad_attr_regwen_5_qs; + logic dio_pad_attr_regwen_5_wd; + logic dio_pad_attr_regwen_6_we; + logic dio_pad_attr_regwen_6_qs; + logic dio_pad_attr_regwen_6_wd; + logic dio_pad_attr_regwen_7_we; + logic dio_pad_attr_regwen_7_qs; + logic dio_pad_attr_regwen_7_wd; + logic dio_pad_attr_regwen_8_we; + logic dio_pad_attr_regwen_8_qs; + logic dio_pad_attr_regwen_8_wd; + logic dio_pad_attr_regwen_9_we; + logic dio_pad_attr_regwen_9_qs; + logic dio_pad_attr_regwen_9_wd; + logic dio_pad_attr_regwen_10_we; + logic dio_pad_attr_regwen_10_qs; + logic dio_pad_attr_regwen_10_wd; + logic dio_pad_attr_regwen_11_we; + logic dio_pad_attr_regwen_11_qs; + logic dio_pad_attr_regwen_11_wd; + logic dio_pad_attr_regwen_12_we; + logic dio_pad_attr_regwen_12_qs; + logic dio_pad_attr_regwen_12_wd; + logic dio_pad_attr_regwen_13_we; + logic dio_pad_attr_regwen_13_qs; + logic dio_pad_attr_regwen_13_wd; + logic dio_pad_attr_regwen_14_we; + logic dio_pad_attr_regwen_14_qs; + logic dio_pad_attr_regwen_14_wd; + logic dio_pad_attr_regwen_15_we; + logic dio_pad_attr_regwen_15_qs; + logic dio_pad_attr_regwen_15_wd; + logic dio_pad_attr_regwen_16_we; + logic dio_pad_attr_regwen_16_qs; + logic dio_pad_attr_regwen_16_wd; + logic dio_pad_attr_regwen_17_we; + logic dio_pad_attr_regwen_17_qs; + logic dio_pad_attr_regwen_17_wd; + logic dio_pad_attr_regwen_18_we; + logic dio_pad_attr_regwen_18_qs; + logic dio_pad_attr_regwen_18_wd; + logic dio_pad_attr_regwen_19_we; + logic dio_pad_attr_regwen_19_qs; + logic dio_pad_attr_regwen_19_wd; + logic dio_pad_attr_regwen_20_we; + logic dio_pad_attr_regwen_20_qs; + logic dio_pad_attr_regwen_20_wd; + logic dio_pad_attr_regwen_21_we; + logic dio_pad_attr_regwen_21_qs; + logic dio_pad_attr_regwen_21_wd; + logic dio_pad_attr_regwen_22_we; + logic dio_pad_attr_regwen_22_qs; + logic dio_pad_attr_regwen_22_wd; + logic dio_pad_attr_regwen_23_we; + logic dio_pad_attr_regwen_23_qs; + logic dio_pad_attr_regwen_23_wd; + logic dio_pad_attr_regwen_24_we; + logic dio_pad_attr_regwen_24_qs; + logic dio_pad_attr_regwen_24_wd; + logic dio_pad_attr_regwen_25_we; + logic dio_pad_attr_regwen_25_qs; + logic dio_pad_attr_regwen_25_wd; + logic dio_pad_attr_regwen_26_we; + logic dio_pad_attr_regwen_26_qs; + logic dio_pad_attr_regwen_26_wd; + logic dio_pad_attr_regwen_27_we; + logic dio_pad_attr_regwen_27_qs; + logic dio_pad_attr_regwen_27_wd; + logic dio_pad_attr_regwen_28_we; + logic dio_pad_attr_regwen_28_qs; + logic dio_pad_attr_regwen_28_wd; + logic dio_pad_attr_regwen_29_we; + logic dio_pad_attr_regwen_29_qs; + logic dio_pad_attr_regwen_29_wd; + logic dio_pad_attr_regwen_30_we; + logic dio_pad_attr_regwen_30_qs; + logic dio_pad_attr_regwen_30_wd; + logic dio_pad_attr_regwen_31_we; + logic dio_pad_attr_regwen_31_qs; + logic dio_pad_attr_regwen_31_wd; + logic dio_pad_attr_regwen_32_we; + logic dio_pad_attr_regwen_32_qs; + logic dio_pad_attr_regwen_32_wd; + logic dio_pad_attr_regwen_33_we; + logic dio_pad_attr_regwen_33_qs; + logic dio_pad_attr_regwen_33_wd; + logic dio_pad_attr_regwen_34_we; + logic dio_pad_attr_regwen_34_qs; + logic dio_pad_attr_regwen_34_wd; + logic dio_pad_attr_regwen_35_we; + logic dio_pad_attr_regwen_35_qs; + logic dio_pad_attr_regwen_35_wd; + logic dio_pad_attr_regwen_36_we; + logic dio_pad_attr_regwen_36_qs; + logic dio_pad_attr_regwen_36_wd; + logic dio_pad_attr_regwen_37_we; + logic dio_pad_attr_regwen_37_qs; + logic dio_pad_attr_regwen_37_wd; + logic dio_pad_attr_regwen_38_we; + logic dio_pad_attr_regwen_38_qs; + logic dio_pad_attr_regwen_38_wd; + logic dio_pad_attr_regwen_39_we; + logic dio_pad_attr_regwen_39_qs; + logic dio_pad_attr_regwen_39_wd; + logic dio_pad_attr_regwen_40_we; + logic dio_pad_attr_regwen_40_qs; + logic dio_pad_attr_regwen_40_wd; + logic dio_pad_attr_regwen_41_we; + logic dio_pad_attr_regwen_41_qs; + logic dio_pad_attr_regwen_41_wd; + logic dio_pad_attr_regwen_42_we; + logic dio_pad_attr_regwen_42_qs; + logic dio_pad_attr_regwen_42_wd; + logic dio_pad_attr_regwen_43_we; + logic dio_pad_attr_regwen_43_qs; + logic dio_pad_attr_regwen_43_wd; + logic dio_pad_attr_regwen_44_we; + logic dio_pad_attr_regwen_44_qs; + logic dio_pad_attr_regwen_44_wd; + logic dio_pad_attr_regwen_45_we; + logic dio_pad_attr_regwen_45_qs; + logic dio_pad_attr_regwen_45_wd; + logic dio_pad_attr_regwen_46_we; + logic dio_pad_attr_regwen_46_qs; + logic dio_pad_attr_regwen_46_wd; + logic dio_pad_attr_regwen_47_we; + logic dio_pad_attr_regwen_47_qs; + logic dio_pad_attr_regwen_47_wd; + logic dio_pad_attr_regwen_48_we; + logic dio_pad_attr_regwen_48_qs; + logic dio_pad_attr_regwen_48_wd; + logic dio_pad_attr_regwen_49_we; + logic dio_pad_attr_regwen_49_qs; + logic dio_pad_attr_regwen_49_wd; + logic dio_pad_attr_regwen_50_we; + logic dio_pad_attr_regwen_50_qs; + logic dio_pad_attr_regwen_50_wd; + logic dio_pad_attr_regwen_51_we; + logic dio_pad_attr_regwen_51_qs; + logic dio_pad_attr_regwen_51_wd; + logic dio_pad_attr_regwen_52_we; + logic dio_pad_attr_regwen_52_qs; + logic dio_pad_attr_regwen_52_wd; + logic dio_pad_attr_regwen_53_we; + logic dio_pad_attr_regwen_53_qs; + logic dio_pad_attr_regwen_53_wd; + logic dio_pad_attr_regwen_54_we; + logic dio_pad_attr_regwen_54_qs; + logic dio_pad_attr_regwen_54_wd; + logic dio_pad_attr_regwen_55_we; + logic dio_pad_attr_regwen_55_qs; + logic dio_pad_attr_regwen_55_wd; + logic dio_pad_attr_regwen_56_we; + logic dio_pad_attr_regwen_56_qs; + logic dio_pad_attr_regwen_56_wd; + logic dio_pad_attr_regwen_57_we; + logic dio_pad_attr_regwen_57_qs; + logic dio_pad_attr_regwen_57_wd; + logic dio_pad_attr_regwen_58_we; + logic dio_pad_attr_regwen_58_qs; + logic dio_pad_attr_regwen_58_wd; + logic dio_pad_attr_regwen_59_we; + logic dio_pad_attr_regwen_59_qs; + logic dio_pad_attr_regwen_59_wd; + logic dio_pad_attr_regwen_60_we; + logic dio_pad_attr_regwen_60_qs; + logic dio_pad_attr_regwen_60_wd; + logic dio_pad_attr_regwen_61_we; + logic dio_pad_attr_regwen_61_qs; + logic dio_pad_attr_regwen_61_wd; + logic dio_pad_attr_regwen_62_we; + logic dio_pad_attr_regwen_62_qs; + logic dio_pad_attr_regwen_62_wd; + logic dio_pad_attr_regwen_63_we; + logic dio_pad_attr_regwen_63_qs; + logic dio_pad_attr_regwen_63_wd; + logic dio_pad_attr_regwen_64_we; + logic dio_pad_attr_regwen_64_qs; + logic dio_pad_attr_regwen_64_wd; + logic dio_pad_attr_regwen_65_we; + logic dio_pad_attr_regwen_65_qs; + logic dio_pad_attr_regwen_65_wd; + logic dio_pad_attr_regwen_66_we; + logic dio_pad_attr_regwen_66_qs; + logic dio_pad_attr_regwen_66_wd; + logic dio_pad_attr_regwen_67_we; + logic dio_pad_attr_regwen_67_qs; + logic dio_pad_attr_regwen_67_wd; + logic dio_pad_attr_regwen_68_we; + logic dio_pad_attr_regwen_68_qs; + logic dio_pad_attr_regwen_68_wd; + logic dio_pad_attr_regwen_69_we; + logic dio_pad_attr_regwen_69_qs; + logic dio_pad_attr_regwen_69_wd; + logic dio_pad_attr_regwen_70_we; + logic dio_pad_attr_regwen_70_qs; + logic dio_pad_attr_regwen_70_wd; + logic dio_pad_attr_regwen_71_we; + logic dio_pad_attr_regwen_71_qs; + logic dio_pad_attr_regwen_71_wd; + logic dio_pad_attr_regwen_72_we; + logic dio_pad_attr_regwen_72_qs; + logic dio_pad_attr_regwen_72_wd; + logic dio_pad_attr_0_re; + logic dio_pad_attr_0_we; + logic dio_pad_attr_0_invert_0_qs; + logic dio_pad_attr_0_invert_0_wd; + logic dio_pad_attr_0_virtual_od_en_0_qs; + logic dio_pad_attr_0_virtual_od_en_0_wd; + logic dio_pad_attr_0_pull_en_0_qs; + logic dio_pad_attr_0_pull_en_0_wd; + logic dio_pad_attr_0_pull_select_0_qs; + logic dio_pad_attr_0_pull_select_0_wd; + logic dio_pad_attr_0_keeper_en_0_qs; + logic dio_pad_attr_0_keeper_en_0_wd; + logic dio_pad_attr_0_schmitt_en_0_qs; + logic dio_pad_attr_0_schmitt_en_0_wd; + logic dio_pad_attr_0_od_en_0_qs; + logic dio_pad_attr_0_od_en_0_wd; + logic dio_pad_attr_0_input_disable_0_qs; + logic dio_pad_attr_0_input_disable_0_wd; + logic [1:0] dio_pad_attr_0_slew_rate_0_qs; + logic [1:0] dio_pad_attr_0_slew_rate_0_wd; + logic [3:0] dio_pad_attr_0_drive_strength_0_qs; + logic [3:0] dio_pad_attr_0_drive_strength_0_wd; + logic dio_pad_attr_1_re; + logic dio_pad_attr_1_we; + logic dio_pad_attr_1_invert_1_qs; + logic dio_pad_attr_1_invert_1_wd; + logic dio_pad_attr_1_virtual_od_en_1_qs; + logic dio_pad_attr_1_virtual_od_en_1_wd; + logic dio_pad_attr_1_pull_en_1_qs; + logic dio_pad_attr_1_pull_en_1_wd; + logic dio_pad_attr_1_pull_select_1_qs; + logic dio_pad_attr_1_pull_select_1_wd; + logic dio_pad_attr_1_keeper_en_1_qs; + logic dio_pad_attr_1_keeper_en_1_wd; + logic dio_pad_attr_1_schmitt_en_1_qs; + logic dio_pad_attr_1_schmitt_en_1_wd; + logic dio_pad_attr_1_od_en_1_qs; + logic dio_pad_attr_1_od_en_1_wd; + logic dio_pad_attr_1_input_disable_1_qs; + logic dio_pad_attr_1_input_disable_1_wd; + logic [1:0] dio_pad_attr_1_slew_rate_1_qs; + logic [1:0] dio_pad_attr_1_slew_rate_1_wd; + logic [3:0] dio_pad_attr_1_drive_strength_1_qs; + logic [3:0] dio_pad_attr_1_drive_strength_1_wd; + logic dio_pad_attr_2_re; + logic dio_pad_attr_2_we; + logic dio_pad_attr_2_invert_2_qs; + logic dio_pad_attr_2_invert_2_wd; + logic dio_pad_attr_2_virtual_od_en_2_qs; + logic dio_pad_attr_2_virtual_od_en_2_wd; + logic dio_pad_attr_2_pull_en_2_qs; + logic dio_pad_attr_2_pull_en_2_wd; + logic dio_pad_attr_2_pull_select_2_qs; + logic dio_pad_attr_2_pull_select_2_wd; + logic dio_pad_attr_2_keeper_en_2_qs; + logic dio_pad_attr_2_keeper_en_2_wd; + logic dio_pad_attr_2_schmitt_en_2_qs; + logic dio_pad_attr_2_schmitt_en_2_wd; + logic dio_pad_attr_2_od_en_2_qs; + logic dio_pad_attr_2_od_en_2_wd; + logic dio_pad_attr_2_input_disable_2_qs; + logic dio_pad_attr_2_input_disable_2_wd; + logic [1:0] dio_pad_attr_2_slew_rate_2_qs; + logic [1:0] dio_pad_attr_2_slew_rate_2_wd; + logic [3:0] dio_pad_attr_2_drive_strength_2_qs; + logic [3:0] dio_pad_attr_2_drive_strength_2_wd; + logic dio_pad_attr_3_re; + logic dio_pad_attr_3_we; + logic dio_pad_attr_3_invert_3_qs; + logic dio_pad_attr_3_invert_3_wd; + logic dio_pad_attr_3_virtual_od_en_3_qs; + logic dio_pad_attr_3_virtual_od_en_3_wd; + logic dio_pad_attr_3_pull_en_3_qs; + logic dio_pad_attr_3_pull_en_3_wd; + logic dio_pad_attr_3_pull_select_3_qs; + logic dio_pad_attr_3_pull_select_3_wd; + logic dio_pad_attr_3_keeper_en_3_qs; + logic dio_pad_attr_3_keeper_en_3_wd; + logic dio_pad_attr_3_schmitt_en_3_qs; + logic dio_pad_attr_3_schmitt_en_3_wd; + logic dio_pad_attr_3_od_en_3_qs; + logic dio_pad_attr_3_od_en_3_wd; + logic dio_pad_attr_3_input_disable_3_qs; + logic dio_pad_attr_3_input_disable_3_wd; + logic [1:0] dio_pad_attr_3_slew_rate_3_qs; + logic [1:0] dio_pad_attr_3_slew_rate_3_wd; + logic [3:0] dio_pad_attr_3_drive_strength_3_qs; + logic [3:0] dio_pad_attr_3_drive_strength_3_wd; + logic dio_pad_attr_4_re; + logic dio_pad_attr_4_we; + logic dio_pad_attr_4_invert_4_qs; + logic dio_pad_attr_4_invert_4_wd; + logic dio_pad_attr_4_virtual_od_en_4_qs; + logic dio_pad_attr_4_virtual_od_en_4_wd; + logic dio_pad_attr_4_pull_en_4_qs; + logic dio_pad_attr_4_pull_en_4_wd; + logic dio_pad_attr_4_pull_select_4_qs; + logic dio_pad_attr_4_pull_select_4_wd; + logic dio_pad_attr_4_keeper_en_4_qs; + logic dio_pad_attr_4_keeper_en_4_wd; + logic dio_pad_attr_4_schmitt_en_4_qs; + logic dio_pad_attr_4_schmitt_en_4_wd; + logic dio_pad_attr_4_od_en_4_qs; + logic dio_pad_attr_4_od_en_4_wd; + logic dio_pad_attr_4_input_disable_4_qs; + logic dio_pad_attr_4_input_disable_4_wd; + logic [1:0] dio_pad_attr_4_slew_rate_4_qs; + logic [1:0] dio_pad_attr_4_slew_rate_4_wd; + logic [3:0] dio_pad_attr_4_drive_strength_4_qs; + logic [3:0] dio_pad_attr_4_drive_strength_4_wd; + logic dio_pad_attr_5_re; + logic dio_pad_attr_5_we; + logic dio_pad_attr_5_invert_5_qs; + logic dio_pad_attr_5_invert_5_wd; + logic dio_pad_attr_5_virtual_od_en_5_qs; + logic dio_pad_attr_5_virtual_od_en_5_wd; + logic dio_pad_attr_5_pull_en_5_qs; + logic dio_pad_attr_5_pull_en_5_wd; + logic dio_pad_attr_5_pull_select_5_qs; + logic dio_pad_attr_5_pull_select_5_wd; + logic dio_pad_attr_5_keeper_en_5_qs; + logic dio_pad_attr_5_keeper_en_5_wd; + logic dio_pad_attr_5_schmitt_en_5_qs; + logic dio_pad_attr_5_schmitt_en_5_wd; + logic dio_pad_attr_5_od_en_5_qs; + logic dio_pad_attr_5_od_en_5_wd; + logic dio_pad_attr_5_input_disable_5_qs; + logic dio_pad_attr_5_input_disable_5_wd; + logic [1:0] dio_pad_attr_5_slew_rate_5_qs; + logic [1:0] dio_pad_attr_5_slew_rate_5_wd; + logic [3:0] dio_pad_attr_5_drive_strength_5_qs; + logic [3:0] dio_pad_attr_5_drive_strength_5_wd; + logic dio_pad_attr_6_re; + logic dio_pad_attr_6_we; + logic dio_pad_attr_6_invert_6_qs; + logic dio_pad_attr_6_invert_6_wd; + logic dio_pad_attr_6_virtual_od_en_6_qs; + logic dio_pad_attr_6_virtual_od_en_6_wd; + logic dio_pad_attr_6_pull_en_6_qs; + logic dio_pad_attr_6_pull_en_6_wd; + logic dio_pad_attr_6_pull_select_6_qs; + logic dio_pad_attr_6_pull_select_6_wd; + logic dio_pad_attr_6_keeper_en_6_qs; + logic dio_pad_attr_6_keeper_en_6_wd; + logic dio_pad_attr_6_schmitt_en_6_qs; + logic dio_pad_attr_6_schmitt_en_6_wd; + logic dio_pad_attr_6_od_en_6_qs; + logic dio_pad_attr_6_od_en_6_wd; + logic dio_pad_attr_6_input_disable_6_qs; + logic dio_pad_attr_6_input_disable_6_wd; + logic [1:0] dio_pad_attr_6_slew_rate_6_qs; + logic [1:0] dio_pad_attr_6_slew_rate_6_wd; + logic [3:0] dio_pad_attr_6_drive_strength_6_qs; + logic [3:0] dio_pad_attr_6_drive_strength_6_wd; + logic dio_pad_attr_7_re; + logic dio_pad_attr_7_we; + logic dio_pad_attr_7_invert_7_qs; + logic dio_pad_attr_7_invert_7_wd; + logic dio_pad_attr_7_virtual_od_en_7_qs; + logic dio_pad_attr_7_virtual_od_en_7_wd; + logic dio_pad_attr_7_pull_en_7_qs; + logic dio_pad_attr_7_pull_en_7_wd; + logic dio_pad_attr_7_pull_select_7_qs; + logic dio_pad_attr_7_pull_select_7_wd; + logic dio_pad_attr_7_keeper_en_7_qs; + logic dio_pad_attr_7_keeper_en_7_wd; + logic dio_pad_attr_7_schmitt_en_7_qs; + logic dio_pad_attr_7_schmitt_en_7_wd; + logic dio_pad_attr_7_od_en_7_qs; + logic dio_pad_attr_7_od_en_7_wd; + logic dio_pad_attr_7_input_disable_7_qs; + logic dio_pad_attr_7_input_disable_7_wd; + logic [1:0] dio_pad_attr_7_slew_rate_7_qs; + logic [1:0] dio_pad_attr_7_slew_rate_7_wd; + logic [3:0] dio_pad_attr_7_drive_strength_7_qs; + logic [3:0] dio_pad_attr_7_drive_strength_7_wd; + logic dio_pad_attr_8_re; + logic dio_pad_attr_8_we; + logic dio_pad_attr_8_invert_8_qs; + logic dio_pad_attr_8_invert_8_wd; + logic dio_pad_attr_8_virtual_od_en_8_qs; + logic dio_pad_attr_8_virtual_od_en_8_wd; + logic dio_pad_attr_8_pull_en_8_qs; + logic dio_pad_attr_8_pull_en_8_wd; + logic dio_pad_attr_8_pull_select_8_qs; + logic dio_pad_attr_8_pull_select_8_wd; + logic dio_pad_attr_8_keeper_en_8_qs; + logic dio_pad_attr_8_keeper_en_8_wd; + logic dio_pad_attr_8_schmitt_en_8_qs; + logic dio_pad_attr_8_schmitt_en_8_wd; + logic dio_pad_attr_8_od_en_8_qs; + logic dio_pad_attr_8_od_en_8_wd; + logic dio_pad_attr_8_input_disable_8_qs; + logic dio_pad_attr_8_input_disable_8_wd; + logic [1:0] dio_pad_attr_8_slew_rate_8_qs; + logic [1:0] dio_pad_attr_8_slew_rate_8_wd; + logic [3:0] dio_pad_attr_8_drive_strength_8_qs; + logic [3:0] dio_pad_attr_8_drive_strength_8_wd; + logic dio_pad_attr_9_re; + logic dio_pad_attr_9_we; + logic dio_pad_attr_9_invert_9_qs; + logic dio_pad_attr_9_invert_9_wd; + logic dio_pad_attr_9_virtual_od_en_9_qs; + logic dio_pad_attr_9_virtual_od_en_9_wd; + logic dio_pad_attr_9_pull_en_9_qs; + logic dio_pad_attr_9_pull_en_9_wd; + logic dio_pad_attr_9_pull_select_9_qs; + logic dio_pad_attr_9_pull_select_9_wd; + logic dio_pad_attr_9_keeper_en_9_qs; + logic dio_pad_attr_9_keeper_en_9_wd; + logic dio_pad_attr_9_schmitt_en_9_qs; + logic dio_pad_attr_9_schmitt_en_9_wd; + logic dio_pad_attr_9_od_en_9_qs; + logic dio_pad_attr_9_od_en_9_wd; + logic dio_pad_attr_9_input_disable_9_qs; + logic dio_pad_attr_9_input_disable_9_wd; + logic [1:0] dio_pad_attr_9_slew_rate_9_qs; + logic [1:0] dio_pad_attr_9_slew_rate_9_wd; + logic [3:0] dio_pad_attr_9_drive_strength_9_qs; + logic [3:0] dio_pad_attr_9_drive_strength_9_wd; + logic dio_pad_attr_10_re; + logic dio_pad_attr_10_we; + logic dio_pad_attr_10_invert_10_qs; + logic dio_pad_attr_10_invert_10_wd; + logic dio_pad_attr_10_virtual_od_en_10_qs; + logic dio_pad_attr_10_virtual_od_en_10_wd; + logic dio_pad_attr_10_pull_en_10_qs; + logic dio_pad_attr_10_pull_en_10_wd; + logic dio_pad_attr_10_pull_select_10_qs; + logic dio_pad_attr_10_pull_select_10_wd; + logic dio_pad_attr_10_keeper_en_10_qs; + logic dio_pad_attr_10_keeper_en_10_wd; + logic dio_pad_attr_10_schmitt_en_10_qs; + logic dio_pad_attr_10_schmitt_en_10_wd; + logic dio_pad_attr_10_od_en_10_qs; + logic dio_pad_attr_10_od_en_10_wd; + logic dio_pad_attr_10_input_disable_10_qs; + logic dio_pad_attr_10_input_disable_10_wd; + logic [1:0] dio_pad_attr_10_slew_rate_10_qs; + logic [1:0] dio_pad_attr_10_slew_rate_10_wd; + logic [3:0] dio_pad_attr_10_drive_strength_10_qs; + logic [3:0] dio_pad_attr_10_drive_strength_10_wd; + logic dio_pad_attr_11_re; + logic dio_pad_attr_11_we; + logic dio_pad_attr_11_invert_11_qs; + logic dio_pad_attr_11_invert_11_wd; + logic dio_pad_attr_11_virtual_od_en_11_qs; + logic dio_pad_attr_11_virtual_od_en_11_wd; + logic dio_pad_attr_11_pull_en_11_qs; + logic dio_pad_attr_11_pull_en_11_wd; + logic dio_pad_attr_11_pull_select_11_qs; + logic dio_pad_attr_11_pull_select_11_wd; + logic dio_pad_attr_11_keeper_en_11_qs; + logic dio_pad_attr_11_keeper_en_11_wd; + logic dio_pad_attr_11_schmitt_en_11_qs; + logic dio_pad_attr_11_schmitt_en_11_wd; + logic dio_pad_attr_11_od_en_11_qs; + logic dio_pad_attr_11_od_en_11_wd; + logic dio_pad_attr_11_input_disable_11_qs; + logic dio_pad_attr_11_input_disable_11_wd; + logic [1:0] dio_pad_attr_11_slew_rate_11_qs; + logic [1:0] dio_pad_attr_11_slew_rate_11_wd; + logic [3:0] dio_pad_attr_11_drive_strength_11_qs; + logic [3:0] dio_pad_attr_11_drive_strength_11_wd; + logic dio_pad_attr_12_re; + logic dio_pad_attr_12_we; + logic dio_pad_attr_12_invert_12_qs; + logic dio_pad_attr_12_invert_12_wd; + logic dio_pad_attr_12_virtual_od_en_12_qs; + logic dio_pad_attr_12_virtual_od_en_12_wd; + logic dio_pad_attr_12_pull_en_12_qs; + logic dio_pad_attr_12_pull_en_12_wd; + logic dio_pad_attr_12_pull_select_12_qs; + logic dio_pad_attr_12_pull_select_12_wd; + logic dio_pad_attr_12_keeper_en_12_qs; + logic dio_pad_attr_12_keeper_en_12_wd; + logic dio_pad_attr_12_schmitt_en_12_qs; + logic dio_pad_attr_12_schmitt_en_12_wd; + logic dio_pad_attr_12_od_en_12_qs; + logic dio_pad_attr_12_od_en_12_wd; + logic dio_pad_attr_12_input_disable_12_qs; + logic dio_pad_attr_12_input_disable_12_wd; + logic [1:0] dio_pad_attr_12_slew_rate_12_qs; + logic [1:0] dio_pad_attr_12_slew_rate_12_wd; + logic [3:0] dio_pad_attr_12_drive_strength_12_qs; + logic [3:0] dio_pad_attr_12_drive_strength_12_wd; + logic dio_pad_attr_13_re; + logic dio_pad_attr_13_we; + logic dio_pad_attr_13_invert_13_qs; + logic dio_pad_attr_13_invert_13_wd; + logic dio_pad_attr_13_virtual_od_en_13_qs; + logic dio_pad_attr_13_virtual_od_en_13_wd; + logic dio_pad_attr_13_pull_en_13_qs; + logic dio_pad_attr_13_pull_en_13_wd; + logic dio_pad_attr_13_pull_select_13_qs; + logic dio_pad_attr_13_pull_select_13_wd; + logic dio_pad_attr_13_keeper_en_13_qs; + logic dio_pad_attr_13_keeper_en_13_wd; + logic dio_pad_attr_13_schmitt_en_13_qs; + logic dio_pad_attr_13_schmitt_en_13_wd; + logic dio_pad_attr_13_od_en_13_qs; + logic dio_pad_attr_13_od_en_13_wd; + logic dio_pad_attr_13_input_disable_13_qs; + logic dio_pad_attr_13_input_disable_13_wd; + logic [1:0] dio_pad_attr_13_slew_rate_13_qs; + logic [1:0] dio_pad_attr_13_slew_rate_13_wd; + logic [3:0] dio_pad_attr_13_drive_strength_13_qs; + logic [3:0] dio_pad_attr_13_drive_strength_13_wd; + logic dio_pad_attr_14_re; + logic dio_pad_attr_14_we; + logic dio_pad_attr_14_invert_14_qs; + logic dio_pad_attr_14_invert_14_wd; + logic dio_pad_attr_14_virtual_od_en_14_qs; + logic dio_pad_attr_14_virtual_od_en_14_wd; + logic dio_pad_attr_14_pull_en_14_qs; + logic dio_pad_attr_14_pull_en_14_wd; + logic dio_pad_attr_14_pull_select_14_qs; + logic dio_pad_attr_14_pull_select_14_wd; + logic dio_pad_attr_14_keeper_en_14_qs; + logic dio_pad_attr_14_keeper_en_14_wd; + logic dio_pad_attr_14_schmitt_en_14_qs; + logic dio_pad_attr_14_schmitt_en_14_wd; + logic dio_pad_attr_14_od_en_14_qs; + logic dio_pad_attr_14_od_en_14_wd; + logic dio_pad_attr_14_input_disable_14_qs; + logic dio_pad_attr_14_input_disable_14_wd; + logic [1:0] dio_pad_attr_14_slew_rate_14_qs; + logic [1:0] dio_pad_attr_14_slew_rate_14_wd; + logic [3:0] dio_pad_attr_14_drive_strength_14_qs; + logic [3:0] dio_pad_attr_14_drive_strength_14_wd; + logic dio_pad_attr_15_re; + logic dio_pad_attr_15_we; + logic dio_pad_attr_15_invert_15_qs; + logic dio_pad_attr_15_invert_15_wd; + logic dio_pad_attr_15_virtual_od_en_15_qs; + logic dio_pad_attr_15_virtual_od_en_15_wd; + logic dio_pad_attr_15_pull_en_15_qs; + logic dio_pad_attr_15_pull_en_15_wd; + logic dio_pad_attr_15_pull_select_15_qs; + logic dio_pad_attr_15_pull_select_15_wd; + logic dio_pad_attr_15_keeper_en_15_qs; + logic dio_pad_attr_15_keeper_en_15_wd; + logic dio_pad_attr_15_schmitt_en_15_qs; + logic dio_pad_attr_15_schmitt_en_15_wd; + logic dio_pad_attr_15_od_en_15_qs; + logic dio_pad_attr_15_od_en_15_wd; + logic dio_pad_attr_15_input_disable_15_qs; + logic dio_pad_attr_15_input_disable_15_wd; + logic [1:0] dio_pad_attr_15_slew_rate_15_qs; + logic [1:0] dio_pad_attr_15_slew_rate_15_wd; + logic [3:0] dio_pad_attr_15_drive_strength_15_qs; + logic [3:0] dio_pad_attr_15_drive_strength_15_wd; + logic dio_pad_attr_16_re; + logic dio_pad_attr_16_we; + logic dio_pad_attr_16_invert_16_qs; + logic dio_pad_attr_16_invert_16_wd; + logic dio_pad_attr_16_virtual_od_en_16_qs; + logic dio_pad_attr_16_virtual_od_en_16_wd; + logic dio_pad_attr_16_pull_en_16_qs; + logic dio_pad_attr_16_pull_en_16_wd; + logic dio_pad_attr_16_pull_select_16_qs; + logic dio_pad_attr_16_pull_select_16_wd; + logic dio_pad_attr_16_keeper_en_16_qs; + logic dio_pad_attr_16_keeper_en_16_wd; + logic dio_pad_attr_16_schmitt_en_16_qs; + logic dio_pad_attr_16_schmitt_en_16_wd; + logic dio_pad_attr_16_od_en_16_qs; + logic dio_pad_attr_16_od_en_16_wd; + logic dio_pad_attr_16_input_disable_16_qs; + logic dio_pad_attr_16_input_disable_16_wd; + logic [1:0] dio_pad_attr_16_slew_rate_16_qs; + logic [1:0] dio_pad_attr_16_slew_rate_16_wd; + logic [3:0] dio_pad_attr_16_drive_strength_16_qs; + logic [3:0] dio_pad_attr_16_drive_strength_16_wd; + logic dio_pad_attr_17_re; + logic dio_pad_attr_17_we; + logic dio_pad_attr_17_invert_17_qs; + logic dio_pad_attr_17_invert_17_wd; + logic dio_pad_attr_17_virtual_od_en_17_qs; + logic dio_pad_attr_17_virtual_od_en_17_wd; + logic dio_pad_attr_17_pull_en_17_qs; + logic dio_pad_attr_17_pull_en_17_wd; + logic dio_pad_attr_17_pull_select_17_qs; + logic dio_pad_attr_17_pull_select_17_wd; + logic dio_pad_attr_17_keeper_en_17_qs; + logic dio_pad_attr_17_keeper_en_17_wd; + logic dio_pad_attr_17_schmitt_en_17_qs; + logic dio_pad_attr_17_schmitt_en_17_wd; + logic dio_pad_attr_17_od_en_17_qs; + logic dio_pad_attr_17_od_en_17_wd; + logic dio_pad_attr_17_input_disable_17_qs; + logic dio_pad_attr_17_input_disable_17_wd; + logic [1:0] dio_pad_attr_17_slew_rate_17_qs; + logic [1:0] dio_pad_attr_17_slew_rate_17_wd; + logic [3:0] dio_pad_attr_17_drive_strength_17_qs; + logic [3:0] dio_pad_attr_17_drive_strength_17_wd; + logic dio_pad_attr_18_re; + logic dio_pad_attr_18_we; + logic dio_pad_attr_18_invert_18_qs; + logic dio_pad_attr_18_invert_18_wd; + logic dio_pad_attr_18_virtual_od_en_18_qs; + logic dio_pad_attr_18_virtual_od_en_18_wd; + logic dio_pad_attr_18_pull_en_18_qs; + logic dio_pad_attr_18_pull_en_18_wd; + logic dio_pad_attr_18_pull_select_18_qs; + logic dio_pad_attr_18_pull_select_18_wd; + logic dio_pad_attr_18_keeper_en_18_qs; + logic dio_pad_attr_18_keeper_en_18_wd; + logic dio_pad_attr_18_schmitt_en_18_qs; + logic dio_pad_attr_18_schmitt_en_18_wd; + logic dio_pad_attr_18_od_en_18_qs; + logic dio_pad_attr_18_od_en_18_wd; + logic dio_pad_attr_18_input_disable_18_qs; + logic dio_pad_attr_18_input_disable_18_wd; + logic [1:0] dio_pad_attr_18_slew_rate_18_qs; + logic [1:0] dio_pad_attr_18_slew_rate_18_wd; + logic [3:0] dio_pad_attr_18_drive_strength_18_qs; + logic [3:0] dio_pad_attr_18_drive_strength_18_wd; + logic dio_pad_attr_19_re; + logic dio_pad_attr_19_we; + logic dio_pad_attr_19_invert_19_qs; + logic dio_pad_attr_19_invert_19_wd; + logic dio_pad_attr_19_virtual_od_en_19_qs; + logic dio_pad_attr_19_virtual_od_en_19_wd; + logic dio_pad_attr_19_pull_en_19_qs; + logic dio_pad_attr_19_pull_en_19_wd; + logic dio_pad_attr_19_pull_select_19_qs; + logic dio_pad_attr_19_pull_select_19_wd; + logic dio_pad_attr_19_keeper_en_19_qs; + logic dio_pad_attr_19_keeper_en_19_wd; + logic dio_pad_attr_19_schmitt_en_19_qs; + logic dio_pad_attr_19_schmitt_en_19_wd; + logic dio_pad_attr_19_od_en_19_qs; + logic dio_pad_attr_19_od_en_19_wd; + logic dio_pad_attr_19_input_disable_19_qs; + logic dio_pad_attr_19_input_disable_19_wd; + logic [1:0] dio_pad_attr_19_slew_rate_19_qs; + logic [1:0] dio_pad_attr_19_slew_rate_19_wd; + logic [3:0] dio_pad_attr_19_drive_strength_19_qs; + logic [3:0] dio_pad_attr_19_drive_strength_19_wd; + logic dio_pad_attr_20_re; + logic dio_pad_attr_20_we; + logic dio_pad_attr_20_invert_20_qs; + logic dio_pad_attr_20_invert_20_wd; + logic dio_pad_attr_20_virtual_od_en_20_qs; + logic dio_pad_attr_20_virtual_od_en_20_wd; + logic dio_pad_attr_20_pull_en_20_qs; + logic dio_pad_attr_20_pull_en_20_wd; + logic dio_pad_attr_20_pull_select_20_qs; + logic dio_pad_attr_20_pull_select_20_wd; + logic dio_pad_attr_20_keeper_en_20_qs; + logic dio_pad_attr_20_keeper_en_20_wd; + logic dio_pad_attr_20_schmitt_en_20_qs; + logic dio_pad_attr_20_schmitt_en_20_wd; + logic dio_pad_attr_20_od_en_20_qs; + logic dio_pad_attr_20_od_en_20_wd; + logic dio_pad_attr_20_input_disable_20_qs; + logic dio_pad_attr_20_input_disable_20_wd; + logic [1:0] dio_pad_attr_20_slew_rate_20_qs; + logic [1:0] dio_pad_attr_20_slew_rate_20_wd; + logic [3:0] dio_pad_attr_20_drive_strength_20_qs; + logic [3:0] dio_pad_attr_20_drive_strength_20_wd; + logic dio_pad_attr_21_re; + logic dio_pad_attr_21_we; + logic dio_pad_attr_21_invert_21_qs; + logic dio_pad_attr_21_invert_21_wd; + logic dio_pad_attr_21_virtual_od_en_21_qs; + logic dio_pad_attr_21_virtual_od_en_21_wd; + logic dio_pad_attr_21_pull_en_21_qs; + logic dio_pad_attr_21_pull_en_21_wd; + logic dio_pad_attr_21_pull_select_21_qs; + logic dio_pad_attr_21_pull_select_21_wd; + logic dio_pad_attr_21_keeper_en_21_qs; + logic dio_pad_attr_21_keeper_en_21_wd; + logic dio_pad_attr_21_schmitt_en_21_qs; + logic dio_pad_attr_21_schmitt_en_21_wd; + logic dio_pad_attr_21_od_en_21_qs; + logic dio_pad_attr_21_od_en_21_wd; + logic dio_pad_attr_21_input_disable_21_qs; + logic dio_pad_attr_21_input_disable_21_wd; + logic [1:0] dio_pad_attr_21_slew_rate_21_qs; + logic [1:0] dio_pad_attr_21_slew_rate_21_wd; + logic [3:0] dio_pad_attr_21_drive_strength_21_qs; + logic [3:0] dio_pad_attr_21_drive_strength_21_wd; + logic dio_pad_attr_22_re; + logic dio_pad_attr_22_we; + logic dio_pad_attr_22_invert_22_qs; + logic dio_pad_attr_22_invert_22_wd; + logic dio_pad_attr_22_virtual_od_en_22_qs; + logic dio_pad_attr_22_virtual_od_en_22_wd; + logic dio_pad_attr_22_pull_en_22_qs; + logic dio_pad_attr_22_pull_en_22_wd; + logic dio_pad_attr_22_pull_select_22_qs; + logic dio_pad_attr_22_pull_select_22_wd; + logic dio_pad_attr_22_keeper_en_22_qs; + logic dio_pad_attr_22_keeper_en_22_wd; + logic dio_pad_attr_22_schmitt_en_22_qs; + logic dio_pad_attr_22_schmitt_en_22_wd; + logic dio_pad_attr_22_od_en_22_qs; + logic dio_pad_attr_22_od_en_22_wd; + logic dio_pad_attr_22_input_disable_22_qs; + logic dio_pad_attr_22_input_disable_22_wd; + logic [1:0] dio_pad_attr_22_slew_rate_22_qs; + logic [1:0] dio_pad_attr_22_slew_rate_22_wd; + logic [3:0] dio_pad_attr_22_drive_strength_22_qs; + logic [3:0] dio_pad_attr_22_drive_strength_22_wd; + logic dio_pad_attr_23_re; + logic dio_pad_attr_23_we; + logic dio_pad_attr_23_invert_23_qs; + logic dio_pad_attr_23_invert_23_wd; + logic dio_pad_attr_23_virtual_od_en_23_qs; + logic dio_pad_attr_23_virtual_od_en_23_wd; + logic dio_pad_attr_23_pull_en_23_qs; + logic dio_pad_attr_23_pull_en_23_wd; + logic dio_pad_attr_23_pull_select_23_qs; + logic dio_pad_attr_23_pull_select_23_wd; + logic dio_pad_attr_23_keeper_en_23_qs; + logic dio_pad_attr_23_keeper_en_23_wd; + logic dio_pad_attr_23_schmitt_en_23_qs; + logic dio_pad_attr_23_schmitt_en_23_wd; + logic dio_pad_attr_23_od_en_23_qs; + logic dio_pad_attr_23_od_en_23_wd; + logic dio_pad_attr_23_input_disable_23_qs; + logic dio_pad_attr_23_input_disable_23_wd; + logic [1:0] dio_pad_attr_23_slew_rate_23_qs; + logic [1:0] dio_pad_attr_23_slew_rate_23_wd; + logic [3:0] dio_pad_attr_23_drive_strength_23_qs; + logic [3:0] dio_pad_attr_23_drive_strength_23_wd; + logic dio_pad_attr_24_re; + logic dio_pad_attr_24_we; + logic dio_pad_attr_24_invert_24_qs; + logic dio_pad_attr_24_invert_24_wd; + logic dio_pad_attr_24_virtual_od_en_24_qs; + logic dio_pad_attr_24_virtual_od_en_24_wd; + logic dio_pad_attr_24_pull_en_24_qs; + logic dio_pad_attr_24_pull_en_24_wd; + logic dio_pad_attr_24_pull_select_24_qs; + logic dio_pad_attr_24_pull_select_24_wd; + logic dio_pad_attr_24_keeper_en_24_qs; + logic dio_pad_attr_24_keeper_en_24_wd; + logic dio_pad_attr_24_schmitt_en_24_qs; + logic dio_pad_attr_24_schmitt_en_24_wd; + logic dio_pad_attr_24_od_en_24_qs; + logic dio_pad_attr_24_od_en_24_wd; + logic dio_pad_attr_24_input_disable_24_qs; + logic dio_pad_attr_24_input_disable_24_wd; + logic [1:0] dio_pad_attr_24_slew_rate_24_qs; + logic [1:0] dio_pad_attr_24_slew_rate_24_wd; + logic [3:0] dio_pad_attr_24_drive_strength_24_qs; + logic [3:0] dio_pad_attr_24_drive_strength_24_wd; + logic dio_pad_attr_25_re; + logic dio_pad_attr_25_we; + logic dio_pad_attr_25_invert_25_qs; + logic dio_pad_attr_25_invert_25_wd; + logic dio_pad_attr_25_virtual_od_en_25_qs; + logic dio_pad_attr_25_virtual_od_en_25_wd; + logic dio_pad_attr_25_pull_en_25_qs; + logic dio_pad_attr_25_pull_en_25_wd; + logic dio_pad_attr_25_pull_select_25_qs; + logic dio_pad_attr_25_pull_select_25_wd; + logic dio_pad_attr_25_keeper_en_25_qs; + logic dio_pad_attr_25_keeper_en_25_wd; + logic dio_pad_attr_25_schmitt_en_25_qs; + logic dio_pad_attr_25_schmitt_en_25_wd; + logic dio_pad_attr_25_od_en_25_qs; + logic dio_pad_attr_25_od_en_25_wd; + logic dio_pad_attr_25_input_disable_25_qs; + logic dio_pad_attr_25_input_disable_25_wd; + logic [1:0] dio_pad_attr_25_slew_rate_25_qs; + logic [1:0] dio_pad_attr_25_slew_rate_25_wd; + logic [3:0] dio_pad_attr_25_drive_strength_25_qs; + logic [3:0] dio_pad_attr_25_drive_strength_25_wd; + logic dio_pad_attr_26_re; + logic dio_pad_attr_26_we; + logic dio_pad_attr_26_invert_26_qs; + logic dio_pad_attr_26_invert_26_wd; + logic dio_pad_attr_26_virtual_od_en_26_qs; + logic dio_pad_attr_26_virtual_od_en_26_wd; + logic dio_pad_attr_26_pull_en_26_qs; + logic dio_pad_attr_26_pull_en_26_wd; + logic dio_pad_attr_26_pull_select_26_qs; + logic dio_pad_attr_26_pull_select_26_wd; + logic dio_pad_attr_26_keeper_en_26_qs; + logic dio_pad_attr_26_keeper_en_26_wd; + logic dio_pad_attr_26_schmitt_en_26_qs; + logic dio_pad_attr_26_schmitt_en_26_wd; + logic dio_pad_attr_26_od_en_26_qs; + logic dio_pad_attr_26_od_en_26_wd; + logic dio_pad_attr_26_input_disable_26_qs; + logic dio_pad_attr_26_input_disable_26_wd; + logic [1:0] dio_pad_attr_26_slew_rate_26_qs; + logic [1:0] dio_pad_attr_26_slew_rate_26_wd; + logic [3:0] dio_pad_attr_26_drive_strength_26_qs; + logic [3:0] dio_pad_attr_26_drive_strength_26_wd; + logic dio_pad_attr_27_re; + logic dio_pad_attr_27_we; + logic dio_pad_attr_27_invert_27_qs; + logic dio_pad_attr_27_invert_27_wd; + logic dio_pad_attr_27_virtual_od_en_27_qs; + logic dio_pad_attr_27_virtual_od_en_27_wd; + logic dio_pad_attr_27_pull_en_27_qs; + logic dio_pad_attr_27_pull_en_27_wd; + logic dio_pad_attr_27_pull_select_27_qs; + logic dio_pad_attr_27_pull_select_27_wd; + logic dio_pad_attr_27_keeper_en_27_qs; + logic dio_pad_attr_27_keeper_en_27_wd; + logic dio_pad_attr_27_schmitt_en_27_qs; + logic dio_pad_attr_27_schmitt_en_27_wd; + logic dio_pad_attr_27_od_en_27_qs; + logic dio_pad_attr_27_od_en_27_wd; + logic dio_pad_attr_27_input_disable_27_qs; + logic dio_pad_attr_27_input_disable_27_wd; + logic [1:0] dio_pad_attr_27_slew_rate_27_qs; + logic [1:0] dio_pad_attr_27_slew_rate_27_wd; + logic [3:0] dio_pad_attr_27_drive_strength_27_qs; + logic [3:0] dio_pad_attr_27_drive_strength_27_wd; + logic dio_pad_attr_28_re; + logic dio_pad_attr_28_we; + logic dio_pad_attr_28_invert_28_qs; + logic dio_pad_attr_28_invert_28_wd; + logic dio_pad_attr_28_virtual_od_en_28_qs; + logic dio_pad_attr_28_virtual_od_en_28_wd; + logic dio_pad_attr_28_pull_en_28_qs; + logic dio_pad_attr_28_pull_en_28_wd; + logic dio_pad_attr_28_pull_select_28_qs; + logic dio_pad_attr_28_pull_select_28_wd; + logic dio_pad_attr_28_keeper_en_28_qs; + logic dio_pad_attr_28_keeper_en_28_wd; + logic dio_pad_attr_28_schmitt_en_28_qs; + logic dio_pad_attr_28_schmitt_en_28_wd; + logic dio_pad_attr_28_od_en_28_qs; + logic dio_pad_attr_28_od_en_28_wd; + logic dio_pad_attr_28_input_disable_28_qs; + logic dio_pad_attr_28_input_disable_28_wd; + logic [1:0] dio_pad_attr_28_slew_rate_28_qs; + logic [1:0] dio_pad_attr_28_slew_rate_28_wd; + logic [3:0] dio_pad_attr_28_drive_strength_28_qs; + logic [3:0] dio_pad_attr_28_drive_strength_28_wd; + logic dio_pad_attr_29_re; + logic dio_pad_attr_29_we; + logic dio_pad_attr_29_invert_29_qs; + logic dio_pad_attr_29_invert_29_wd; + logic dio_pad_attr_29_virtual_od_en_29_qs; + logic dio_pad_attr_29_virtual_od_en_29_wd; + logic dio_pad_attr_29_pull_en_29_qs; + logic dio_pad_attr_29_pull_en_29_wd; + logic dio_pad_attr_29_pull_select_29_qs; + logic dio_pad_attr_29_pull_select_29_wd; + logic dio_pad_attr_29_keeper_en_29_qs; + logic dio_pad_attr_29_keeper_en_29_wd; + logic dio_pad_attr_29_schmitt_en_29_qs; + logic dio_pad_attr_29_schmitt_en_29_wd; + logic dio_pad_attr_29_od_en_29_qs; + logic dio_pad_attr_29_od_en_29_wd; + logic dio_pad_attr_29_input_disable_29_qs; + logic dio_pad_attr_29_input_disable_29_wd; + logic [1:0] dio_pad_attr_29_slew_rate_29_qs; + logic [1:0] dio_pad_attr_29_slew_rate_29_wd; + logic [3:0] dio_pad_attr_29_drive_strength_29_qs; + logic [3:0] dio_pad_attr_29_drive_strength_29_wd; + logic dio_pad_attr_30_re; + logic dio_pad_attr_30_we; + logic dio_pad_attr_30_invert_30_qs; + logic dio_pad_attr_30_invert_30_wd; + logic dio_pad_attr_30_virtual_od_en_30_qs; + logic dio_pad_attr_30_virtual_od_en_30_wd; + logic dio_pad_attr_30_pull_en_30_qs; + logic dio_pad_attr_30_pull_en_30_wd; + logic dio_pad_attr_30_pull_select_30_qs; + logic dio_pad_attr_30_pull_select_30_wd; + logic dio_pad_attr_30_keeper_en_30_qs; + logic dio_pad_attr_30_keeper_en_30_wd; + logic dio_pad_attr_30_schmitt_en_30_qs; + logic dio_pad_attr_30_schmitt_en_30_wd; + logic dio_pad_attr_30_od_en_30_qs; + logic dio_pad_attr_30_od_en_30_wd; + logic dio_pad_attr_30_input_disable_30_qs; + logic dio_pad_attr_30_input_disable_30_wd; + logic [1:0] dio_pad_attr_30_slew_rate_30_qs; + logic [1:0] dio_pad_attr_30_slew_rate_30_wd; + logic [3:0] dio_pad_attr_30_drive_strength_30_qs; + logic [3:0] dio_pad_attr_30_drive_strength_30_wd; + logic dio_pad_attr_31_re; + logic dio_pad_attr_31_we; + logic dio_pad_attr_31_invert_31_qs; + logic dio_pad_attr_31_invert_31_wd; + logic dio_pad_attr_31_virtual_od_en_31_qs; + logic dio_pad_attr_31_virtual_od_en_31_wd; + logic dio_pad_attr_31_pull_en_31_qs; + logic dio_pad_attr_31_pull_en_31_wd; + logic dio_pad_attr_31_pull_select_31_qs; + logic dio_pad_attr_31_pull_select_31_wd; + logic dio_pad_attr_31_keeper_en_31_qs; + logic dio_pad_attr_31_keeper_en_31_wd; + logic dio_pad_attr_31_schmitt_en_31_qs; + logic dio_pad_attr_31_schmitt_en_31_wd; + logic dio_pad_attr_31_od_en_31_qs; + logic dio_pad_attr_31_od_en_31_wd; + logic dio_pad_attr_31_input_disable_31_qs; + logic dio_pad_attr_31_input_disable_31_wd; + logic [1:0] dio_pad_attr_31_slew_rate_31_qs; + logic [1:0] dio_pad_attr_31_slew_rate_31_wd; + logic [3:0] dio_pad_attr_31_drive_strength_31_qs; + logic [3:0] dio_pad_attr_31_drive_strength_31_wd; + logic dio_pad_attr_32_re; + logic dio_pad_attr_32_we; + logic dio_pad_attr_32_invert_32_qs; + logic dio_pad_attr_32_invert_32_wd; + logic dio_pad_attr_32_virtual_od_en_32_qs; + logic dio_pad_attr_32_virtual_od_en_32_wd; + logic dio_pad_attr_32_pull_en_32_qs; + logic dio_pad_attr_32_pull_en_32_wd; + logic dio_pad_attr_32_pull_select_32_qs; + logic dio_pad_attr_32_pull_select_32_wd; + logic dio_pad_attr_32_keeper_en_32_qs; + logic dio_pad_attr_32_keeper_en_32_wd; + logic dio_pad_attr_32_schmitt_en_32_qs; + logic dio_pad_attr_32_schmitt_en_32_wd; + logic dio_pad_attr_32_od_en_32_qs; + logic dio_pad_attr_32_od_en_32_wd; + logic dio_pad_attr_32_input_disable_32_qs; + logic dio_pad_attr_32_input_disable_32_wd; + logic [1:0] dio_pad_attr_32_slew_rate_32_qs; + logic [1:0] dio_pad_attr_32_slew_rate_32_wd; + logic [3:0] dio_pad_attr_32_drive_strength_32_qs; + logic [3:0] dio_pad_attr_32_drive_strength_32_wd; + logic dio_pad_attr_33_re; + logic dio_pad_attr_33_we; + logic dio_pad_attr_33_invert_33_qs; + logic dio_pad_attr_33_invert_33_wd; + logic dio_pad_attr_33_virtual_od_en_33_qs; + logic dio_pad_attr_33_virtual_od_en_33_wd; + logic dio_pad_attr_33_pull_en_33_qs; + logic dio_pad_attr_33_pull_en_33_wd; + logic dio_pad_attr_33_pull_select_33_qs; + logic dio_pad_attr_33_pull_select_33_wd; + logic dio_pad_attr_33_keeper_en_33_qs; + logic dio_pad_attr_33_keeper_en_33_wd; + logic dio_pad_attr_33_schmitt_en_33_qs; + logic dio_pad_attr_33_schmitt_en_33_wd; + logic dio_pad_attr_33_od_en_33_qs; + logic dio_pad_attr_33_od_en_33_wd; + logic dio_pad_attr_33_input_disable_33_qs; + logic dio_pad_attr_33_input_disable_33_wd; + logic [1:0] dio_pad_attr_33_slew_rate_33_qs; + logic [1:0] dio_pad_attr_33_slew_rate_33_wd; + logic [3:0] dio_pad_attr_33_drive_strength_33_qs; + logic [3:0] dio_pad_attr_33_drive_strength_33_wd; + logic dio_pad_attr_34_re; + logic dio_pad_attr_34_we; + logic dio_pad_attr_34_invert_34_qs; + logic dio_pad_attr_34_invert_34_wd; + logic dio_pad_attr_34_virtual_od_en_34_qs; + logic dio_pad_attr_34_virtual_od_en_34_wd; + logic dio_pad_attr_34_pull_en_34_qs; + logic dio_pad_attr_34_pull_en_34_wd; + logic dio_pad_attr_34_pull_select_34_qs; + logic dio_pad_attr_34_pull_select_34_wd; + logic dio_pad_attr_34_keeper_en_34_qs; + logic dio_pad_attr_34_keeper_en_34_wd; + logic dio_pad_attr_34_schmitt_en_34_qs; + logic dio_pad_attr_34_schmitt_en_34_wd; + logic dio_pad_attr_34_od_en_34_qs; + logic dio_pad_attr_34_od_en_34_wd; + logic dio_pad_attr_34_input_disable_34_qs; + logic dio_pad_attr_34_input_disable_34_wd; + logic [1:0] dio_pad_attr_34_slew_rate_34_qs; + logic [1:0] dio_pad_attr_34_slew_rate_34_wd; + logic [3:0] dio_pad_attr_34_drive_strength_34_qs; + logic [3:0] dio_pad_attr_34_drive_strength_34_wd; + logic dio_pad_attr_35_re; + logic dio_pad_attr_35_we; + logic dio_pad_attr_35_invert_35_qs; + logic dio_pad_attr_35_invert_35_wd; + logic dio_pad_attr_35_virtual_od_en_35_qs; + logic dio_pad_attr_35_virtual_od_en_35_wd; + logic dio_pad_attr_35_pull_en_35_qs; + logic dio_pad_attr_35_pull_en_35_wd; + logic dio_pad_attr_35_pull_select_35_qs; + logic dio_pad_attr_35_pull_select_35_wd; + logic dio_pad_attr_35_keeper_en_35_qs; + logic dio_pad_attr_35_keeper_en_35_wd; + logic dio_pad_attr_35_schmitt_en_35_qs; + logic dio_pad_attr_35_schmitt_en_35_wd; + logic dio_pad_attr_35_od_en_35_qs; + logic dio_pad_attr_35_od_en_35_wd; + logic dio_pad_attr_35_input_disable_35_qs; + logic dio_pad_attr_35_input_disable_35_wd; + logic [1:0] dio_pad_attr_35_slew_rate_35_qs; + logic [1:0] dio_pad_attr_35_slew_rate_35_wd; + logic [3:0] dio_pad_attr_35_drive_strength_35_qs; + logic [3:0] dio_pad_attr_35_drive_strength_35_wd; + logic dio_pad_attr_36_re; + logic dio_pad_attr_36_we; + logic dio_pad_attr_36_invert_36_qs; + logic dio_pad_attr_36_invert_36_wd; + logic dio_pad_attr_36_virtual_od_en_36_qs; + logic dio_pad_attr_36_virtual_od_en_36_wd; + logic dio_pad_attr_36_pull_en_36_qs; + logic dio_pad_attr_36_pull_en_36_wd; + logic dio_pad_attr_36_pull_select_36_qs; + logic dio_pad_attr_36_pull_select_36_wd; + logic dio_pad_attr_36_keeper_en_36_qs; + logic dio_pad_attr_36_keeper_en_36_wd; + logic dio_pad_attr_36_schmitt_en_36_qs; + logic dio_pad_attr_36_schmitt_en_36_wd; + logic dio_pad_attr_36_od_en_36_qs; + logic dio_pad_attr_36_od_en_36_wd; + logic dio_pad_attr_36_input_disable_36_qs; + logic dio_pad_attr_36_input_disable_36_wd; + logic [1:0] dio_pad_attr_36_slew_rate_36_qs; + logic [1:0] dio_pad_attr_36_slew_rate_36_wd; + logic [3:0] dio_pad_attr_36_drive_strength_36_qs; + logic [3:0] dio_pad_attr_36_drive_strength_36_wd; + logic dio_pad_attr_37_re; + logic dio_pad_attr_37_we; + logic dio_pad_attr_37_invert_37_qs; + logic dio_pad_attr_37_invert_37_wd; + logic dio_pad_attr_37_virtual_od_en_37_qs; + logic dio_pad_attr_37_virtual_od_en_37_wd; + logic dio_pad_attr_37_pull_en_37_qs; + logic dio_pad_attr_37_pull_en_37_wd; + logic dio_pad_attr_37_pull_select_37_qs; + logic dio_pad_attr_37_pull_select_37_wd; + logic dio_pad_attr_37_keeper_en_37_qs; + logic dio_pad_attr_37_keeper_en_37_wd; + logic dio_pad_attr_37_schmitt_en_37_qs; + logic dio_pad_attr_37_schmitt_en_37_wd; + logic dio_pad_attr_37_od_en_37_qs; + logic dio_pad_attr_37_od_en_37_wd; + logic dio_pad_attr_37_input_disable_37_qs; + logic dio_pad_attr_37_input_disable_37_wd; + logic [1:0] dio_pad_attr_37_slew_rate_37_qs; + logic [1:0] dio_pad_attr_37_slew_rate_37_wd; + logic [3:0] dio_pad_attr_37_drive_strength_37_qs; + logic [3:0] dio_pad_attr_37_drive_strength_37_wd; + logic dio_pad_attr_38_re; + logic dio_pad_attr_38_we; + logic dio_pad_attr_38_invert_38_qs; + logic dio_pad_attr_38_invert_38_wd; + logic dio_pad_attr_38_virtual_od_en_38_qs; + logic dio_pad_attr_38_virtual_od_en_38_wd; + logic dio_pad_attr_38_pull_en_38_qs; + logic dio_pad_attr_38_pull_en_38_wd; + logic dio_pad_attr_38_pull_select_38_qs; + logic dio_pad_attr_38_pull_select_38_wd; + logic dio_pad_attr_38_keeper_en_38_qs; + logic dio_pad_attr_38_keeper_en_38_wd; + logic dio_pad_attr_38_schmitt_en_38_qs; + logic dio_pad_attr_38_schmitt_en_38_wd; + logic dio_pad_attr_38_od_en_38_qs; + logic dio_pad_attr_38_od_en_38_wd; + logic dio_pad_attr_38_input_disable_38_qs; + logic dio_pad_attr_38_input_disable_38_wd; + logic [1:0] dio_pad_attr_38_slew_rate_38_qs; + logic [1:0] dio_pad_attr_38_slew_rate_38_wd; + logic [3:0] dio_pad_attr_38_drive_strength_38_qs; + logic [3:0] dio_pad_attr_38_drive_strength_38_wd; + logic dio_pad_attr_39_re; + logic dio_pad_attr_39_we; + logic dio_pad_attr_39_invert_39_qs; + logic dio_pad_attr_39_invert_39_wd; + logic dio_pad_attr_39_virtual_od_en_39_qs; + logic dio_pad_attr_39_virtual_od_en_39_wd; + logic dio_pad_attr_39_pull_en_39_qs; + logic dio_pad_attr_39_pull_en_39_wd; + logic dio_pad_attr_39_pull_select_39_qs; + logic dio_pad_attr_39_pull_select_39_wd; + logic dio_pad_attr_39_keeper_en_39_qs; + logic dio_pad_attr_39_keeper_en_39_wd; + logic dio_pad_attr_39_schmitt_en_39_qs; + logic dio_pad_attr_39_schmitt_en_39_wd; + logic dio_pad_attr_39_od_en_39_qs; + logic dio_pad_attr_39_od_en_39_wd; + logic dio_pad_attr_39_input_disable_39_qs; + logic dio_pad_attr_39_input_disable_39_wd; + logic [1:0] dio_pad_attr_39_slew_rate_39_qs; + logic [1:0] dio_pad_attr_39_slew_rate_39_wd; + logic [3:0] dio_pad_attr_39_drive_strength_39_qs; + logic [3:0] dio_pad_attr_39_drive_strength_39_wd; + logic dio_pad_attr_40_re; + logic dio_pad_attr_40_we; + logic dio_pad_attr_40_invert_40_qs; + logic dio_pad_attr_40_invert_40_wd; + logic dio_pad_attr_40_virtual_od_en_40_qs; + logic dio_pad_attr_40_virtual_od_en_40_wd; + logic dio_pad_attr_40_pull_en_40_qs; + logic dio_pad_attr_40_pull_en_40_wd; + logic dio_pad_attr_40_pull_select_40_qs; + logic dio_pad_attr_40_pull_select_40_wd; + logic dio_pad_attr_40_keeper_en_40_qs; + logic dio_pad_attr_40_keeper_en_40_wd; + logic dio_pad_attr_40_schmitt_en_40_qs; + logic dio_pad_attr_40_schmitt_en_40_wd; + logic dio_pad_attr_40_od_en_40_qs; + logic dio_pad_attr_40_od_en_40_wd; + logic dio_pad_attr_40_input_disable_40_qs; + logic dio_pad_attr_40_input_disable_40_wd; + logic [1:0] dio_pad_attr_40_slew_rate_40_qs; + logic [1:0] dio_pad_attr_40_slew_rate_40_wd; + logic [3:0] dio_pad_attr_40_drive_strength_40_qs; + logic [3:0] dio_pad_attr_40_drive_strength_40_wd; + logic dio_pad_attr_41_re; + logic dio_pad_attr_41_we; + logic dio_pad_attr_41_invert_41_qs; + logic dio_pad_attr_41_invert_41_wd; + logic dio_pad_attr_41_virtual_od_en_41_qs; + logic dio_pad_attr_41_virtual_od_en_41_wd; + logic dio_pad_attr_41_pull_en_41_qs; + logic dio_pad_attr_41_pull_en_41_wd; + logic dio_pad_attr_41_pull_select_41_qs; + logic dio_pad_attr_41_pull_select_41_wd; + logic dio_pad_attr_41_keeper_en_41_qs; + logic dio_pad_attr_41_keeper_en_41_wd; + logic dio_pad_attr_41_schmitt_en_41_qs; + logic dio_pad_attr_41_schmitt_en_41_wd; + logic dio_pad_attr_41_od_en_41_qs; + logic dio_pad_attr_41_od_en_41_wd; + logic dio_pad_attr_41_input_disable_41_qs; + logic dio_pad_attr_41_input_disable_41_wd; + logic [1:0] dio_pad_attr_41_slew_rate_41_qs; + logic [1:0] dio_pad_attr_41_slew_rate_41_wd; + logic [3:0] dio_pad_attr_41_drive_strength_41_qs; + logic [3:0] dio_pad_attr_41_drive_strength_41_wd; + logic dio_pad_attr_42_re; + logic dio_pad_attr_42_we; + logic dio_pad_attr_42_invert_42_qs; + logic dio_pad_attr_42_invert_42_wd; + logic dio_pad_attr_42_virtual_od_en_42_qs; + logic dio_pad_attr_42_virtual_od_en_42_wd; + logic dio_pad_attr_42_pull_en_42_qs; + logic dio_pad_attr_42_pull_en_42_wd; + logic dio_pad_attr_42_pull_select_42_qs; + logic dio_pad_attr_42_pull_select_42_wd; + logic dio_pad_attr_42_keeper_en_42_qs; + logic dio_pad_attr_42_keeper_en_42_wd; + logic dio_pad_attr_42_schmitt_en_42_qs; + logic dio_pad_attr_42_schmitt_en_42_wd; + logic dio_pad_attr_42_od_en_42_qs; + logic dio_pad_attr_42_od_en_42_wd; + logic dio_pad_attr_42_input_disable_42_qs; + logic dio_pad_attr_42_input_disable_42_wd; + logic [1:0] dio_pad_attr_42_slew_rate_42_qs; + logic [1:0] dio_pad_attr_42_slew_rate_42_wd; + logic [3:0] dio_pad_attr_42_drive_strength_42_qs; + logic [3:0] dio_pad_attr_42_drive_strength_42_wd; + logic dio_pad_attr_43_re; + logic dio_pad_attr_43_we; + logic dio_pad_attr_43_invert_43_qs; + logic dio_pad_attr_43_invert_43_wd; + logic dio_pad_attr_43_virtual_od_en_43_qs; + logic dio_pad_attr_43_virtual_od_en_43_wd; + logic dio_pad_attr_43_pull_en_43_qs; + logic dio_pad_attr_43_pull_en_43_wd; + logic dio_pad_attr_43_pull_select_43_qs; + logic dio_pad_attr_43_pull_select_43_wd; + logic dio_pad_attr_43_keeper_en_43_qs; + logic dio_pad_attr_43_keeper_en_43_wd; + logic dio_pad_attr_43_schmitt_en_43_qs; + logic dio_pad_attr_43_schmitt_en_43_wd; + logic dio_pad_attr_43_od_en_43_qs; + logic dio_pad_attr_43_od_en_43_wd; + logic dio_pad_attr_43_input_disable_43_qs; + logic dio_pad_attr_43_input_disable_43_wd; + logic [1:0] dio_pad_attr_43_slew_rate_43_qs; + logic [1:0] dio_pad_attr_43_slew_rate_43_wd; + logic [3:0] dio_pad_attr_43_drive_strength_43_qs; + logic [3:0] dio_pad_attr_43_drive_strength_43_wd; + logic dio_pad_attr_44_re; + logic dio_pad_attr_44_we; + logic dio_pad_attr_44_invert_44_qs; + logic dio_pad_attr_44_invert_44_wd; + logic dio_pad_attr_44_virtual_od_en_44_qs; + logic dio_pad_attr_44_virtual_od_en_44_wd; + logic dio_pad_attr_44_pull_en_44_qs; + logic dio_pad_attr_44_pull_en_44_wd; + logic dio_pad_attr_44_pull_select_44_qs; + logic dio_pad_attr_44_pull_select_44_wd; + logic dio_pad_attr_44_keeper_en_44_qs; + logic dio_pad_attr_44_keeper_en_44_wd; + logic dio_pad_attr_44_schmitt_en_44_qs; + logic dio_pad_attr_44_schmitt_en_44_wd; + logic dio_pad_attr_44_od_en_44_qs; + logic dio_pad_attr_44_od_en_44_wd; + logic dio_pad_attr_44_input_disable_44_qs; + logic dio_pad_attr_44_input_disable_44_wd; + logic [1:0] dio_pad_attr_44_slew_rate_44_qs; + logic [1:0] dio_pad_attr_44_slew_rate_44_wd; + logic [3:0] dio_pad_attr_44_drive_strength_44_qs; + logic [3:0] dio_pad_attr_44_drive_strength_44_wd; + logic dio_pad_attr_45_re; + logic dio_pad_attr_45_we; + logic dio_pad_attr_45_invert_45_qs; + logic dio_pad_attr_45_invert_45_wd; + logic dio_pad_attr_45_virtual_od_en_45_qs; + logic dio_pad_attr_45_virtual_od_en_45_wd; + logic dio_pad_attr_45_pull_en_45_qs; + logic dio_pad_attr_45_pull_en_45_wd; + logic dio_pad_attr_45_pull_select_45_qs; + logic dio_pad_attr_45_pull_select_45_wd; + logic dio_pad_attr_45_keeper_en_45_qs; + logic dio_pad_attr_45_keeper_en_45_wd; + logic dio_pad_attr_45_schmitt_en_45_qs; + logic dio_pad_attr_45_schmitt_en_45_wd; + logic dio_pad_attr_45_od_en_45_qs; + logic dio_pad_attr_45_od_en_45_wd; + logic dio_pad_attr_45_input_disable_45_qs; + logic dio_pad_attr_45_input_disable_45_wd; + logic [1:0] dio_pad_attr_45_slew_rate_45_qs; + logic [1:0] dio_pad_attr_45_slew_rate_45_wd; + logic [3:0] dio_pad_attr_45_drive_strength_45_qs; + logic [3:0] dio_pad_attr_45_drive_strength_45_wd; + logic dio_pad_attr_46_re; + logic dio_pad_attr_46_we; + logic dio_pad_attr_46_invert_46_qs; + logic dio_pad_attr_46_invert_46_wd; + logic dio_pad_attr_46_virtual_od_en_46_qs; + logic dio_pad_attr_46_virtual_od_en_46_wd; + logic dio_pad_attr_46_pull_en_46_qs; + logic dio_pad_attr_46_pull_en_46_wd; + logic dio_pad_attr_46_pull_select_46_qs; + logic dio_pad_attr_46_pull_select_46_wd; + logic dio_pad_attr_46_keeper_en_46_qs; + logic dio_pad_attr_46_keeper_en_46_wd; + logic dio_pad_attr_46_schmitt_en_46_qs; + logic dio_pad_attr_46_schmitt_en_46_wd; + logic dio_pad_attr_46_od_en_46_qs; + logic dio_pad_attr_46_od_en_46_wd; + logic dio_pad_attr_46_input_disable_46_qs; + logic dio_pad_attr_46_input_disable_46_wd; + logic [1:0] dio_pad_attr_46_slew_rate_46_qs; + logic [1:0] dio_pad_attr_46_slew_rate_46_wd; + logic [3:0] dio_pad_attr_46_drive_strength_46_qs; + logic [3:0] dio_pad_attr_46_drive_strength_46_wd; + logic dio_pad_attr_47_re; + logic dio_pad_attr_47_we; + logic dio_pad_attr_47_invert_47_qs; + logic dio_pad_attr_47_invert_47_wd; + logic dio_pad_attr_47_virtual_od_en_47_qs; + logic dio_pad_attr_47_virtual_od_en_47_wd; + logic dio_pad_attr_47_pull_en_47_qs; + logic dio_pad_attr_47_pull_en_47_wd; + logic dio_pad_attr_47_pull_select_47_qs; + logic dio_pad_attr_47_pull_select_47_wd; + logic dio_pad_attr_47_keeper_en_47_qs; + logic dio_pad_attr_47_keeper_en_47_wd; + logic dio_pad_attr_47_schmitt_en_47_qs; + logic dio_pad_attr_47_schmitt_en_47_wd; + logic dio_pad_attr_47_od_en_47_qs; + logic dio_pad_attr_47_od_en_47_wd; + logic dio_pad_attr_47_input_disable_47_qs; + logic dio_pad_attr_47_input_disable_47_wd; + logic [1:0] dio_pad_attr_47_slew_rate_47_qs; + logic [1:0] dio_pad_attr_47_slew_rate_47_wd; + logic [3:0] dio_pad_attr_47_drive_strength_47_qs; + logic [3:0] dio_pad_attr_47_drive_strength_47_wd; + logic dio_pad_attr_48_re; + logic dio_pad_attr_48_we; + logic dio_pad_attr_48_invert_48_qs; + logic dio_pad_attr_48_invert_48_wd; + logic dio_pad_attr_48_virtual_od_en_48_qs; + logic dio_pad_attr_48_virtual_od_en_48_wd; + logic dio_pad_attr_48_pull_en_48_qs; + logic dio_pad_attr_48_pull_en_48_wd; + logic dio_pad_attr_48_pull_select_48_qs; + logic dio_pad_attr_48_pull_select_48_wd; + logic dio_pad_attr_48_keeper_en_48_qs; + logic dio_pad_attr_48_keeper_en_48_wd; + logic dio_pad_attr_48_schmitt_en_48_qs; + logic dio_pad_attr_48_schmitt_en_48_wd; + logic dio_pad_attr_48_od_en_48_qs; + logic dio_pad_attr_48_od_en_48_wd; + logic dio_pad_attr_48_input_disable_48_qs; + logic dio_pad_attr_48_input_disable_48_wd; + logic [1:0] dio_pad_attr_48_slew_rate_48_qs; + logic [1:0] dio_pad_attr_48_slew_rate_48_wd; + logic [3:0] dio_pad_attr_48_drive_strength_48_qs; + logic [3:0] dio_pad_attr_48_drive_strength_48_wd; + logic dio_pad_attr_49_re; + logic dio_pad_attr_49_we; + logic dio_pad_attr_49_invert_49_qs; + logic dio_pad_attr_49_invert_49_wd; + logic dio_pad_attr_49_virtual_od_en_49_qs; + logic dio_pad_attr_49_virtual_od_en_49_wd; + logic dio_pad_attr_49_pull_en_49_qs; + logic dio_pad_attr_49_pull_en_49_wd; + logic dio_pad_attr_49_pull_select_49_qs; + logic dio_pad_attr_49_pull_select_49_wd; + logic dio_pad_attr_49_keeper_en_49_qs; + logic dio_pad_attr_49_keeper_en_49_wd; + logic dio_pad_attr_49_schmitt_en_49_qs; + logic dio_pad_attr_49_schmitt_en_49_wd; + logic dio_pad_attr_49_od_en_49_qs; + logic dio_pad_attr_49_od_en_49_wd; + logic dio_pad_attr_49_input_disable_49_qs; + logic dio_pad_attr_49_input_disable_49_wd; + logic [1:0] dio_pad_attr_49_slew_rate_49_qs; + logic [1:0] dio_pad_attr_49_slew_rate_49_wd; + logic [3:0] dio_pad_attr_49_drive_strength_49_qs; + logic [3:0] dio_pad_attr_49_drive_strength_49_wd; + logic dio_pad_attr_50_re; + logic dio_pad_attr_50_we; + logic dio_pad_attr_50_invert_50_qs; + logic dio_pad_attr_50_invert_50_wd; + logic dio_pad_attr_50_virtual_od_en_50_qs; + logic dio_pad_attr_50_virtual_od_en_50_wd; + logic dio_pad_attr_50_pull_en_50_qs; + logic dio_pad_attr_50_pull_en_50_wd; + logic dio_pad_attr_50_pull_select_50_qs; + logic dio_pad_attr_50_pull_select_50_wd; + logic dio_pad_attr_50_keeper_en_50_qs; + logic dio_pad_attr_50_keeper_en_50_wd; + logic dio_pad_attr_50_schmitt_en_50_qs; + logic dio_pad_attr_50_schmitt_en_50_wd; + logic dio_pad_attr_50_od_en_50_qs; + logic dio_pad_attr_50_od_en_50_wd; + logic dio_pad_attr_50_input_disable_50_qs; + logic dio_pad_attr_50_input_disable_50_wd; + logic [1:0] dio_pad_attr_50_slew_rate_50_qs; + logic [1:0] dio_pad_attr_50_slew_rate_50_wd; + logic [3:0] dio_pad_attr_50_drive_strength_50_qs; + logic [3:0] dio_pad_attr_50_drive_strength_50_wd; + logic dio_pad_attr_51_re; + logic dio_pad_attr_51_we; + logic dio_pad_attr_51_invert_51_qs; + logic dio_pad_attr_51_invert_51_wd; + logic dio_pad_attr_51_virtual_od_en_51_qs; + logic dio_pad_attr_51_virtual_od_en_51_wd; + logic dio_pad_attr_51_pull_en_51_qs; + logic dio_pad_attr_51_pull_en_51_wd; + logic dio_pad_attr_51_pull_select_51_qs; + logic dio_pad_attr_51_pull_select_51_wd; + logic dio_pad_attr_51_keeper_en_51_qs; + logic dio_pad_attr_51_keeper_en_51_wd; + logic dio_pad_attr_51_schmitt_en_51_qs; + logic dio_pad_attr_51_schmitt_en_51_wd; + logic dio_pad_attr_51_od_en_51_qs; + logic dio_pad_attr_51_od_en_51_wd; + logic dio_pad_attr_51_input_disable_51_qs; + logic dio_pad_attr_51_input_disable_51_wd; + logic [1:0] dio_pad_attr_51_slew_rate_51_qs; + logic [1:0] dio_pad_attr_51_slew_rate_51_wd; + logic [3:0] dio_pad_attr_51_drive_strength_51_qs; + logic [3:0] dio_pad_attr_51_drive_strength_51_wd; + logic dio_pad_attr_52_re; + logic dio_pad_attr_52_we; + logic dio_pad_attr_52_invert_52_qs; + logic dio_pad_attr_52_invert_52_wd; + logic dio_pad_attr_52_virtual_od_en_52_qs; + logic dio_pad_attr_52_virtual_od_en_52_wd; + logic dio_pad_attr_52_pull_en_52_qs; + logic dio_pad_attr_52_pull_en_52_wd; + logic dio_pad_attr_52_pull_select_52_qs; + logic dio_pad_attr_52_pull_select_52_wd; + logic dio_pad_attr_52_keeper_en_52_qs; + logic dio_pad_attr_52_keeper_en_52_wd; + logic dio_pad_attr_52_schmitt_en_52_qs; + logic dio_pad_attr_52_schmitt_en_52_wd; + logic dio_pad_attr_52_od_en_52_qs; + logic dio_pad_attr_52_od_en_52_wd; + logic dio_pad_attr_52_input_disable_52_qs; + logic dio_pad_attr_52_input_disable_52_wd; + logic [1:0] dio_pad_attr_52_slew_rate_52_qs; + logic [1:0] dio_pad_attr_52_slew_rate_52_wd; + logic [3:0] dio_pad_attr_52_drive_strength_52_qs; + logic [3:0] dio_pad_attr_52_drive_strength_52_wd; + logic dio_pad_attr_53_re; + logic dio_pad_attr_53_we; + logic dio_pad_attr_53_invert_53_qs; + logic dio_pad_attr_53_invert_53_wd; + logic dio_pad_attr_53_virtual_od_en_53_qs; + logic dio_pad_attr_53_virtual_od_en_53_wd; + logic dio_pad_attr_53_pull_en_53_qs; + logic dio_pad_attr_53_pull_en_53_wd; + logic dio_pad_attr_53_pull_select_53_qs; + logic dio_pad_attr_53_pull_select_53_wd; + logic dio_pad_attr_53_keeper_en_53_qs; + logic dio_pad_attr_53_keeper_en_53_wd; + logic dio_pad_attr_53_schmitt_en_53_qs; + logic dio_pad_attr_53_schmitt_en_53_wd; + logic dio_pad_attr_53_od_en_53_qs; + logic dio_pad_attr_53_od_en_53_wd; + logic dio_pad_attr_53_input_disable_53_qs; + logic dio_pad_attr_53_input_disable_53_wd; + logic [1:0] dio_pad_attr_53_slew_rate_53_qs; + logic [1:0] dio_pad_attr_53_slew_rate_53_wd; + logic [3:0] dio_pad_attr_53_drive_strength_53_qs; + logic [3:0] dio_pad_attr_53_drive_strength_53_wd; + logic dio_pad_attr_54_re; + logic dio_pad_attr_54_we; + logic dio_pad_attr_54_invert_54_qs; + logic dio_pad_attr_54_invert_54_wd; + logic dio_pad_attr_54_virtual_od_en_54_qs; + logic dio_pad_attr_54_virtual_od_en_54_wd; + logic dio_pad_attr_54_pull_en_54_qs; + logic dio_pad_attr_54_pull_en_54_wd; + logic dio_pad_attr_54_pull_select_54_qs; + logic dio_pad_attr_54_pull_select_54_wd; + logic dio_pad_attr_54_keeper_en_54_qs; + logic dio_pad_attr_54_keeper_en_54_wd; + logic dio_pad_attr_54_schmitt_en_54_qs; + logic dio_pad_attr_54_schmitt_en_54_wd; + logic dio_pad_attr_54_od_en_54_qs; + logic dio_pad_attr_54_od_en_54_wd; + logic dio_pad_attr_54_input_disable_54_qs; + logic dio_pad_attr_54_input_disable_54_wd; + logic [1:0] dio_pad_attr_54_slew_rate_54_qs; + logic [1:0] dio_pad_attr_54_slew_rate_54_wd; + logic [3:0] dio_pad_attr_54_drive_strength_54_qs; + logic [3:0] dio_pad_attr_54_drive_strength_54_wd; + logic dio_pad_attr_55_re; + logic dio_pad_attr_55_we; + logic dio_pad_attr_55_invert_55_qs; + logic dio_pad_attr_55_invert_55_wd; + logic dio_pad_attr_55_virtual_od_en_55_qs; + logic dio_pad_attr_55_virtual_od_en_55_wd; + logic dio_pad_attr_55_pull_en_55_qs; + logic dio_pad_attr_55_pull_en_55_wd; + logic dio_pad_attr_55_pull_select_55_qs; + logic dio_pad_attr_55_pull_select_55_wd; + logic dio_pad_attr_55_keeper_en_55_qs; + logic dio_pad_attr_55_keeper_en_55_wd; + logic dio_pad_attr_55_schmitt_en_55_qs; + logic dio_pad_attr_55_schmitt_en_55_wd; + logic dio_pad_attr_55_od_en_55_qs; + logic dio_pad_attr_55_od_en_55_wd; + logic dio_pad_attr_55_input_disable_55_qs; + logic dio_pad_attr_55_input_disable_55_wd; + logic [1:0] dio_pad_attr_55_slew_rate_55_qs; + logic [1:0] dio_pad_attr_55_slew_rate_55_wd; + logic [3:0] dio_pad_attr_55_drive_strength_55_qs; + logic [3:0] dio_pad_attr_55_drive_strength_55_wd; + logic dio_pad_attr_56_re; + logic dio_pad_attr_56_we; + logic dio_pad_attr_56_invert_56_qs; + logic dio_pad_attr_56_invert_56_wd; + logic dio_pad_attr_56_virtual_od_en_56_qs; + logic dio_pad_attr_56_virtual_od_en_56_wd; + logic dio_pad_attr_56_pull_en_56_qs; + logic dio_pad_attr_56_pull_en_56_wd; + logic dio_pad_attr_56_pull_select_56_qs; + logic dio_pad_attr_56_pull_select_56_wd; + logic dio_pad_attr_56_keeper_en_56_qs; + logic dio_pad_attr_56_keeper_en_56_wd; + logic dio_pad_attr_56_schmitt_en_56_qs; + logic dio_pad_attr_56_schmitt_en_56_wd; + logic dio_pad_attr_56_od_en_56_qs; + logic dio_pad_attr_56_od_en_56_wd; + logic dio_pad_attr_56_input_disable_56_qs; + logic dio_pad_attr_56_input_disable_56_wd; + logic [1:0] dio_pad_attr_56_slew_rate_56_qs; + logic [1:0] dio_pad_attr_56_slew_rate_56_wd; + logic [3:0] dio_pad_attr_56_drive_strength_56_qs; + logic [3:0] dio_pad_attr_56_drive_strength_56_wd; + logic dio_pad_attr_57_re; + logic dio_pad_attr_57_we; + logic dio_pad_attr_57_invert_57_qs; + logic dio_pad_attr_57_invert_57_wd; + logic dio_pad_attr_57_virtual_od_en_57_qs; + logic dio_pad_attr_57_virtual_od_en_57_wd; + logic dio_pad_attr_57_pull_en_57_qs; + logic dio_pad_attr_57_pull_en_57_wd; + logic dio_pad_attr_57_pull_select_57_qs; + logic dio_pad_attr_57_pull_select_57_wd; + logic dio_pad_attr_57_keeper_en_57_qs; + logic dio_pad_attr_57_keeper_en_57_wd; + logic dio_pad_attr_57_schmitt_en_57_qs; + logic dio_pad_attr_57_schmitt_en_57_wd; + logic dio_pad_attr_57_od_en_57_qs; + logic dio_pad_attr_57_od_en_57_wd; + logic dio_pad_attr_57_input_disable_57_qs; + logic dio_pad_attr_57_input_disable_57_wd; + logic [1:0] dio_pad_attr_57_slew_rate_57_qs; + logic [1:0] dio_pad_attr_57_slew_rate_57_wd; + logic [3:0] dio_pad_attr_57_drive_strength_57_qs; + logic [3:0] dio_pad_attr_57_drive_strength_57_wd; + logic dio_pad_attr_58_re; + logic dio_pad_attr_58_we; + logic dio_pad_attr_58_invert_58_qs; + logic dio_pad_attr_58_invert_58_wd; + logic dio_pad_attr_58_virtual_od_en_58_qs; + logic dio_pad_attr_58_virtual_od_en_58_wd; + logic dio_pad_attr_58_pull_en_58_qs; + logic dio_pad_attr_58_pull_en_58_wd; + logic dio_pad_attr_58_pull_select_58_qs; + logic dio_pad_attr_58_pull_select_58_wd; + logic dio_pad_attr_58_keeper_en_58_qs; + logic dio_pad_attr_58_keeper_en_58_wd; + logic dio_pad_attr_58_schmitt_en_58_qs; + logic dio_pad_attr_58_schmitt_en_58_wd; + logic dio_pad_attr_58_od_en_58_qs; + logic dio_pad_attr_58_od_en_58_wd; + logic dio_pad_attr_58_input_disable_58_qs; + logic dio_pad_attr_58_input_disable_58_wd; + logic [1:0] dio_pad_attr_58_slew_rate_58_qs; + logic [1:0] dio_pad_attr_58_slew_rate_58_wd; + logic [3:0] dio_pad_attr_58_drive_strength_58_qs; + logic [3:0] dio_pad_attr_58_drive_strength_58_wd; + logic dio_pad_attr_59_re; + logic dio_pad_attr_59_we; + logic dio_pad_attr_59_invert_59_qs; + logic dio_pad_attr_59_invert_59_wd; + logic dio_pad_attr_59_virtual_od_en_59_qs; + logic dio_pad_attr_59_virtual_od_en_59_wd; + logic dio_pad_attr_59_pull_en_59_qs; + logic dio_pad_attr_59_pull_en_59_wd; + logic dio_pad_attr_59_pull_select_59_qs; + logic dio_pad_attr_59_pull_select_59_wd; + logic dio_pad_attr_59_keeper_en_59_qs; + logic dio_pad_attr_59_keeper_en_59_wd; + logic dio_pad_attr_59_schmitt_en_59_qs; + logic dio_pad_attr_59_schmitt_en_59_wd; + logic dio_pad_attr_59_od_en_59_qs; + logic dio_pad_attr_59_od_en_59_wd; + logic dio_pad_attr_59_input_disable_59_qs; + logic dio_pad_attr_59_input_disable_59_wd; + logic [1:0] dio_pad_attr_59_slew_rate_59_qs; + logic [1:0] dio_pad_attr_59_slew_rate_59_wd; + logic [3:0] dio_pad_attr_59_drive_strength_59_qs; + logic [3:0] dio_pad_attr_59_drive_strength_59_wd; + logic dio_pad_attr_60_re; + logic dio_pad_attr_60_we; + logic dio_pad_attr_60_invert_60_qs; + logic dio_pad_attr_60_invert_60_wd; + logic dio_pad_attr_60_virtual_od_en_60_qs; + logic dio_pad_attr_60_virtual_od_en_60_wd; + logic dio_pad_attr_60_pull_en_60_qs; + logic dio_pad_attr_60_pull_en_60_wd; + logic dio_pad_attr_60_pull_select_60_qs; + logic dio_pad_attr_60_pull_select_60_wd; + logic dio_pad_attr_60_keeper_en_60_qs; + logic dio_pad_attr_60_keeper_en_60_wd; + logic dio_pad_attr_60_schmitt_en_60_qs; + logic dio_pad_attr_60_schmitt_en_60_wd; + logic dio_pad_attr_60_od_en_60_qs; + logic dio_pad_attr_60_od_en_60_wd; + logic dio_pad_attr_60_input_disable_60_qs; + logic dio_pad_attr_60_input_disable_60_wd; + logic [1:0] dio_pad_attr_60_slew_rate_60_qs; + logic [1:0] dio_pad_attr_60_slew_rate_60_wd; + logic [3:0] dio_pad_attr_60_drive_strength_60_qs; + logic [3:0] dio_pad_attr_60_drive_strength_60_wd; + logic dio_pad_attr_61_re; + logic dio_pad_attr_61_we; + logic dio_pad_attr_61_invert_61_qs; + logic dio_pad_attr_61_invert_61_wd; + logic dio_pad_attr_61_virtual_od_en_61_qs; + logic dio_pad_attr_61_virtual_od_en_61_wd; + logic dio_pad_attr_61_pull_en_61_qs; + logic dio_pad_attr_61_pull_en_61_wd; + logic dio_pad_attr_61_pull_select_61_qs; + logic dio_pad_attr_61_pull_select_61_wd; + logic dio_pad_attr_61_keeper_en_61_qs; + logic dio_pad_attr_61_keeper_en_61_wd; + logic dio_pad_attr_61_schmitt_en_61_qs; + logic dio_pad_attr_61_schmitt_en_61_wd; + logic dio_pad_attr_61_od_en_61_qs; + logic dio_pad_attr_61_od_en_61_wd; + logic dio_pad_attr_61_input_disable_61_qs; + logic dio_pad_attr_61_input_disable_61_wd; + logic [1:0] dio_pad_attr_61_slew_rate_61_qs; + logic [1:0] dio_pad_attr_61_slew_rate_61_wd; + logic [3:0] dio_pad_attr_61_drive_strength_61_qs; + logic [3:0] dio_pad_attr_61_drive_strength_61_wd; + logic dio_pad_attr_62_re; + logic dio_pad_attr_62_we; + logic dio_pad_attr_62_invert_62_qs; + logic dio_pad_attr_62_invert_62_wd; + logic dio_pad_attr_62_virtual_od_en_62_qs; + logic dio_pad_attr_62_virtual_od_en_62_wd; + logic dio_pad_attr_62_pull_en_62_qs; + logic dio_pad_attr_62_pull_en_62_wd; + logic dio_pad_attr_62_pull_select_62_qs; + logic dio_pad_attr_62_pull_select_62_wd; + logic dio_pad_attr_62_keeper_en_62_qs; + logic dio_pad_attr_62_keeper_en_62_wd; + logic dio_pad_attr_62_schmitt_en_62_qs; + logic dio_pad_attr_62_schmitt_en_62_wd; + logic dio_pad_attr_62_od_en_62_qs; + logic dio_pad_attr_62_od_en_62_wd; + logic dio_pad_attr_62_input_disable_62_qs; + logic dio_pad_attr_62_input_disable_62_wd; + logic [1:0] dio_pad_attr_62_slew_rate_62_qs; + logic [1:0] dio_pad_attr_62_slew_rate_62_wd; + logic [3:0] dio_pad_attr_62_drive_strength_62_qs; + logic [3:0] dio_pad_attr_62_drive_strength_62_wd; + logic dio_pad_attr_63_re; + logic dio_pad_attr_63_we; + logic dio_pad_attr_63_invert_63_qs; + logic dio_pad_attr_63_invert_63_wd; + logic dio_pad_attr_63_virtual_od_en_63_qs; + logic dio_pad_attr_63_virtual_od_en_63_wd; + logic dio_pad_attr_63_pull_en_63_qs; + logic dio_pad_attr_63_pull_en_63_wd; + logic dio_pad_attr_63_pull_select_63_qs; + logic dio_pad_attr_63_pull_select_63_wd; + logic dio_pad_attr_63_keeper_en_63_qs; + logic dio_pad_attr_63_keeper_en_63_wd; + logic dio_pad_attr_63_schmitt_en_63_qs; + logic dio_pad_attr_63_schmitt_en_63_wd; + logic dio_pad_attr_63_od_en_63_qs; + logic dio_pad_attr_63_od_en_63_wd; + logic dio_pad_attr_63_input_disable_63_qs; + logic dio_pad_attr_63_input_disable_63_wd; + logic [1:0] dio_pad_attr_63_slew_rate_63_qs; + logic [1:0] dio_pad_attr_63_slew_rate_63_wd; + logic [3:0] dio_pad_attr_63_drive_strength_63_qs; + logic [3:0] dio_pad_attr_63_drive_strength_63_wd; + logic dio_pad_attr_64_re; + logic dio_pad_attr_64_we; + logic dio_pad_attr_64_invert_64_qs; + logic dio_pad_attr_64_invert_64_wd; + logic dio_pad_attr_64_virtual_od_en_64_qs; + logic dio_pad_attr_64_virtual_od_en_64_wd; + logic dio_pad_attr_64_pull_en_64_qs; + logic dio_pad_attr_64_pull_en_64_wd; + logic dio_pad_attr_64_pull_select_64_qs; + logic dio_pad_attr_64_pull_select_64_wd; + logic dio_pad_attr_64_keeper_en_64_qs; + logic dio_pad_attr_64_keeper_en_64_wd; + logic dio_pad_attr_64_schmitt_en_64_qs; + logic dio_pad_attr_64_schmitt_en_64_wd; + logic dio_pad_attr_64_od_en_64_qs; + logic dio_pad_attr_64_od_en_64_wd; + logic dio_pad_attr_64_input_disable_64_qs; + logic dio_pad_attr_64_input_disable_64_wd; + logic [1:0] dio_pad_attr_64_slew_rate_64_qs; + logic [1:0] dio_pad_attr_64_slew_rate_64_wd; + logic [3:0] dio_pad_attr_64_drive_strength_64_qs; + logic [3:0] dio_pad_attr_64_drive_strength_64_wd; + logic dio_pad_attr_65_re; + logic dio_pad_attr_65_we; + logic dio_pad_attr_65_invert_65_qs; + logic dio_pad_attr_65_invert_65_wd; + logic dio_pad_attr_65_virtual_od_en_65_qs; + logic dio_pad_attr_65_virtual_od_en_65_wd; + logic dio_pad_attr_65_pull_en_65_qs; + logic dio_pad_attr_65_pull_en_65_wd; + logic dio_pad_attr_65_pull_select_65_qs; + logic dio_pad_attr_65_pull_select_65_wd; + logic dio_pad_attr_65_keeper_en_65_qs; + logic dio_pad_attr_65_keeper_en_65_wd; + logic dio_pad_attr_65_schmitt_en_65_qs; + logic dio_pad_attr_65_schmitt_en_65_wd; + logic dio_pad_attr_65_od_en_65_qs; + logic dio_pad_attr_65_od_en_65_wd; + logic dio_pad_attr_65_input_disable_65_qs; + logic dio_pad_attr_65_input_disable_65_wd; + logic [1:0] dio_pad_attr_65_slew_rate_65_qs; + logic [1:0] dio_pad_attr_65_slew_rate_65_wd; + logic [3:0] dio_pad_attr_65_drive_strength_65_qs; + logic [3:0] dio_pad_attr_65_drive_strength_65_wd; + logic dio_pad_attr_66_re; + logic dio_pad_attr_66_we; + logic dio_pad_attr_66_invert_66_qs; + logic dio_pad_attr_66_invert_66_wd; + logic dio_pad_attr_66_virtual_od_en_66_qs; + logic dio_pad_attr_66_virtual_od_en_66_wd; + logic dio_pad_attr_66_pull_en_66_qs; + logic dio_pad_attr_66_pull_en_66_wd; + logic dio_pad_attr_66_pull_select_66_qs; + logic dio_pad_attr_66_pull_select_66_wd; + logic dio_pad_attr_66_keeper_en_66_qs; + logic dio_pad_attr_66_keeper_en_66_wd; + logic dio_pad_attr_66_schmitt_en_66_qs; + logic dio_pad_attr_66_schmitt_en_66_wd; + logic dio_pad_attr_66_od_en_66_qs; + logic dio_pad_attr_66_od_en_66_wd; + logic dio_pad_attr_66_input_disable_66_qs; + logic dio_pad_attr_66_input_disable_66_wd; + logic [1:0] dio_pad_attr_66_slew_rate_66_qs; + logic [1:0] dio_pad_attr_66_slew_rate_66_wd; + logic [3:0] dio_pad_attr_66_drive_strength_66_qs; + logic [3:0] dio_pad_attr_66_drive_strength_66_wd; + logic dio_pad_attr_67_re; + logic dio_pad_attr_67_we; + logic dio_pad_attr_67_invert_67_qs; + logic dio_pad_attr_67_invert_67_wd; + logic dio_pad_attr_67_virtual_od_en_67_qs; + logic dio_pad_attr_67_virtual_od_en_67_wd; + logic dio_pad_attr_67_pull_en_67_qs; + logic dio_pad_attr_67_pull_en_67_wd; + logic dio_pad_attr_67_pull_select_67_qs; + logic dio_pad_attr_67_pull_select_67_wd; + logic dio_pad_attr_67_keeper_en_67_qs; + logic dio_pad_attr_67_keeper_en_67_wd; + logic dio_pad_attr_67_schmitt_en_67_qs; + logic dio_pad_attr_67_schmitt_en_67_wd; + logic dio_pad_attr_67_od_en_67_qs; + logic dio_pad_attr_67_od_en_67_wd; + logic dio_pad_attr_67_input_disable_67_qs; + logic dio_pad_attr_67_input_disable_67_wd; + logic [1:0] dio_pad_attr_67_slew_rate_67_qs; + logic [1:0] dio_pad_attr_67_slew_rate_67_wd; + logic [3:0] dio_pad_attr_67_drive_strength_67_qs; + logic [3:0] dio_pad_attr_67_drive_strength_67_wd; + logic dio_pad_attr_68_re; + logic dio_pad_attr_68_we; + logic dio_pad_attr_68_invert_68_qs; + logic dio_pad_attr_68_invert_68_wd; + logic dio_pad_attr_68_virtual_od_en_68_qs; + logic dio_pad_attr_68_virtual_od_en_68_wd; + logic dio_pad_attr_68_pull_en_68_qs; + logic dio_pad_attr_68_pull_en_68_wd; + logic dio_pad_attr_68_pull_select_68_qs; + logic dio_pad_attr_68_pull_select_68_wd; + logic dio_pad_attr_68_keeper_en_68_qs; + logic dio_pad_attr_68_keeper_en_68_wd; + logic dio_pad_attr_68_schmitt_en_68_qs; + logic dio_pad_attr_68_schmitt_en_68_wd; + logic dio_pad_attr_68_od_en_68_qs; + logic dio_pad_attr_68_od_en_68_wd; + logic dio_pad_attr_68_input_disable_68_qs; + logic dio_pad_attr_68_input_disable_68_wd; + logic [1:0] dio_pad_attr_68_slew_rate_68_qs; + logic [1:0] dio_pad_attr_68_slew_rate_68_wd; + logic [3:0] dio_pad_attr_68_drive_strength_68_qs; + logic [3:0] dio_pad_attr_68_drive_strength_68_wd; + logic dio_pad_attr_69_re; + logic dio_pad_attr_69_we; + logic dio_pad_attr_69_invert_69_qs; + logic dio_pad_attr_69_invert_69_wd; + logic dio_pad_attr_69_virtual_od_en_69_qs; + logic dio_pad_attr_69_virtual_od_en_69_wd; + logic dio_pad_attr_69_pull_en_69_qs; + logic dio_pad_attr_69_pull_en_69_wd; + logic dio_pad_attr_69_pull_select_69_qs; + logic dio_pad_attr_69_pull_select_69_wd; + logic dio_pad_attr_69_keeper_en_69_qs; + logic dio_pad_attr_69_keeper_en_69_wd; + logic dio_pad_attr_69_schmitt_en_69_qs; + logic dio_pad_attr_69_schmitt_en_69_wd; + logic dio_pad_attr_69_od_en_69_qs; + logic dio_pad_attr_69_od_en_69_wd; + logic dio_pad_attr_69_input_disable_69_qs; + logic dio_pad_attr_69_input_disable_69_wd; + logic [1:0] dio_pad_attr_69_slew_rate_69_qs; + logic [1:0] dio_pad_attr_69_slew_rate_69_wd; + logic [3:0] dio_pad_attr_69_drive_strength_69_qs; + logic [3:0] dio_pad_attr_69_drive_strength_69_wd; + logic dio_pad_attr_70_re; + logic dio_pad_attr_70_we; + logic dio_pad_attr_70_invert_70_qs; + logic dio_pad_attr_70_invert_70_wd; + logic dio_pad_attr_70_virtual_od_en_70_qs; + logic dio_pad_attr_70_virtual_od_en_70_wd; + logic dio_pad_attr_70_pull_en_70_qs; + logic dio_pad_attr_70_pull_en_70_wd; + logic dio_pad_attr_70_pull_select_70_qs; + logic dio_pad_attr_70_pull_select_70_wd; + logic dio_pad_attr_70_keeper_en_70_qs; + logic dio_pad_attr_70_keeper_en_70_wd; + logic dio_pad_attr_70_schmitt_en_70_qs; + logic dio_pad_attr_70_schmitt_en_70_wd; + logic dio_pad_attr_70_od_en_70_qs; + logic dio_pad_attr_70_od_en_70_wd; + logic dio_pad_attr_70_input_disable_70_qs; + logic dio_pad_attr_70_input_disable_70_wd; + logic [1:0] dio_pad_attr_70_slew_rate_70_qs; + logic [1:0] dio_pad_attr_70_slew_rate_70_wd; + logic [3:0] dio_pad_attr_70_drive_strength_70_qs; + logic [3:0] dio_pad_attr_70_drive_strength_70_wd; + logic dio_pad_attr_71_re; + logic dio_pad_attr_71_we; + logic dio_pad_attr_71_invert_71_qs; + logic dio_pad_attr_71_invert_71_wd; + logic dio_pad_attr_71_virtual_od_en_71_qs; + logic dio_pad_attr_71_virtual_od_en_71_wd; + logic dio_pad_attr_71_pull_en_71_qs; + logic dio_pad_attr_71_pull_en_71_wd; + logic dio_pad_attr_71_pull_select_71_qs; + logic dio_pad_attr_71_pull_select_71_wd; + logic dio_pad_attr_71_keeper_en_71_qs; + logic dio_pad_attr_71_keeper_en_71_wd; + logic dio_pad_attr_71_schmitt_en_71_qs; + logic dio_pad_attr_71_schmitt_en_71_wd; + logic dio_pad_attr_71_od_en_71_qs; + logic dio_pad_attr_71_od_en_71_wd; + logic dio_pad_attr_71_input_disable_71_qs; + logic dio_pad_attr_71_input_disable_71_wd; + logic [1:0] dio_pad_attr_71_slew_rate_71_qs; + logic [1:0] dio_pad_attr_71_slew_rate_71_wd; + logic [3:0] dio_pad_attr_71_drive_strength_71_qs; + logic [3:0] dio_pad_attr_71_drive_strength_71_wd; + logic dio_pad_attr_72_re; + logic dio_pad_attr_72_we; + logic dio_pad_attr_72_invert_72_qs; + logic dio_pad_attr_72_invert_72_wd; + logic dio_pad_attr_72_virtual_od_en_72_qs; + logic dio_pad_attr_72_virtual_od_en_72_wd; + logic dio_pad_attr_72_pull_en_72_qs; + logic dio_pad_attr_72_pull_en_72_wd; + logic dio_pad_attr_72_pull_select_72_qs; + logic dio_pad_attr_72_pull_select_72_wd; + logic dio_pad_attr_72_keeper_en_72_qs; + logic dio_pad_attr_72_keeper_en_72_wd; + logic dio_pad_attr_72_schmitt_en_72_qs; + logic dio_pad_attr_72_schmitt_en_72_wd; + logic dio_pad_attr_72_od_en_72_qs; + logic dio_pad_attr_72_od_en_72_wd; + logic dio_pad_attr_72_input_disable_72_qs; + logic dio_pad_attr_72_input_disable_72_wd; + logic [1:0] dio_pad_attr_72_slew_rate_72_qs; + logic [1:0] dio_pad_attr_72_slew_rate_72_wd; + logic [3:0] dio_pad_attr_72_drive_strength_72_qs; + logic [3:0] dio_pad_attr_72_drive_strength_72_wd; + logic mio_pad_sleep_status_we; + logic mio_pad_sleep_status_en_0_qs; + logic mio_pad_sleep_status_en_0_wd; + logic mio_pad_sleep_status_en_1_qs; + logic mio_pad_sleep_status_en_1_wd; + logic mio_pad_sleep_status_en_2_qs; + logic mio_pad_sleep_status_en_2_wd; + logic mio_pad_sleep_status_en_3_qs; + logic mio_pad_sleep_status_en_3_wd; + logic mio_pad_sleep_status_en_4_qs; + logic mio_pad_sleep_status_en_4_wd; + logic mio_pad_sleep_status_en_5_qs; + logic mio_pad_sleep_status_en_5_wd; + logic mio_pad_sleep_status_en_6_qs; + logic mio_pad_sleep_status_en_6_wd; + logic mio_pad_sleep_status_en_7_qs; + logic mio_pad_sleep_status_en_7_wd; + logic mio_pad_sleep_status_en_8_qs; + logic mio_pad_sleep_status_en_8_wd; + logic mio_pad_sleep_status_en_9_qs; + logic mio_pad_sleep_status_en_9_wd; + logic mio_pad_sleep_status_en_10_qs; + logic mio_pad_sleep_status_en_10_wd; + logic mio_pad_sleep_status_en_11_qs; + logic mio_pad_sleep_status_en_11_wd; + logic mio_pad_sleep_regwen_0_we; + logic mio_pad_sleep_regwen_0_qs; + logic mio_pad_sleep_regwen_0_wd; + logic mio_pad_sleep_regwen_1_we; + logic mio_pad_sleep_regwen_1_qs; + logic mio_pad_sleep_regwen_1_wd; + logic mio_pad_sleep_regwen_2_we; + logic mio_pad_sleep_regwen_2_qs; + logic mio_pad_sleep_regwen_2_wd; + logic mio_pad_sleep_regwen_3_we; + logic mio_pad_sleep_regwen_3_qs; + logic mio_pad_sleep_regwen_3_wd; + logic mio_pad_sleep_regwen_4_we; + logic mio_pad_sleep_regwen_4_qs; + logic mio_pad_sleep_regwen_4_wd; + logic mio_pad_sleep_regwen_5_we; + logic mio_pad_sleep_regwen_5_qs; + logic mio_pad_sleep_regwen_5_wd; + logic mio_pad_sleep_regwen_6_we; + logic mio_pad_sleep_regwen_6_qs; + logic mio_pad_sleep_regwen_6_wd; + logic mio_pad_sleep_regwen_7_we; + logic mio_pad_sleep_regwen_7_qs; + logic mio_pad_sleep_regwen_7_wd; + logic mio_pad_sleep_regwen_8_we; + logic mio_pad_sleep_regwen_8_qs; + logic mio_pad_sleep_regwen_8_wd; + logic mio_pad_sleep_regwen_9_we; + logic mio_pad_sleep_regwen_9_qs; + logic mio_pad_sleep_regwen_9_wd; + logic mio_pad_sleep_regwen_10_we; + logic mio_pad_sleep_regwen_10_qs; + logic mio_pad_sleep_regwen_10_wd; + logic mio_pad_sleep_regwen_11_we; + logic mio_pad_sleep_regwen_11_qs; + logic mio_pad_sleep_regwen_11_wd; + logic mio_pad_sleep_en_0_we; + logic mio_pad_sleep_en_0_qs; + logic mio_pad_sleep_en_0_wd; + logic mio_pad_sleep_en_1_we; + logic mio_pad_sleep_en_1_qs; + logic mio_pad_sleep_en_1_wd; + logic mio_pad_sleep_en_2_we; + logic mio_pad_sleep_en_2_qs; + logic mio_pad_sleep_en_2_wd; + logic mio_pad_sleep_en_3_we; + logic mio_pad_sleep_en_3_qs; + logic mio_pad_sleep_en_3_wd; + logic mio_pad_sleep_en_4_we; + logic mio_pad_sleep_en_4_qs; + logic mio_pad_sleep_en_4_wd; + logic mio_pad_sleep_en_5_we; + logic mio_pad_sleep_en_5_qs; + logic mio_pad_sleep_en_5_wd; + logic mio_pad_sleep_en_6_we; + logic mio_pad_sleep_en_6_qs; + logic mio_pad_sleep_en_6_wd; + logic mio_pad_sleep_en_7_we; + logic mio_pad_sleep_en_7_qs; + logic mio_pad_sleep_en_7_wd; + logic mio_pad_sleep_en_8_we; + logic mio_pad_sleep_en_8_qs; + logic mio_pad_sleep_en_8_wd; + logic mio_pad_sleep_en_9_we; + logic mio_pad_sleep_en_9_qs; + logic mio_pad_sleep_en_9_wd; + logic mio_pad_sleep_en_10_we; + logic mio_pad_sleep_en_10_qs; + logic mio_pad_sleep_en_10_wd; + logic mio_pad_sleep_en_11_we; + logic mio_pad_sleep_en_11_qs; + logic mio_pad_sleep_en_11_wd; + logic mio_pad_sleep_mode_0_we; + logic [1:0] mio_pad_sleep_mode_0_qs; + logic [1:0] mio_pad_sleep_mode_0_wd; + logic mio_pad_sleep_mode_1_we; + logic [1:0] mio_pad_sleep_mode_1_qs; + logic [1:0] mio_pad_sleep_mode_1_wd; + logic mio_pad_sleep_mode_2_we; + logic [1:0] mio_pad_sleep_mode_2_qs; + logic [1:0] mio_pad_sleep_mode_2_wd; + logic mio_pad_sleep_mode_3_we; + logic [1:0] mio_pad_sleep_mode_3_qs; + logic [1:0] mio_pad_sleep_mode_3_wd; + logic mio_pad_sleep_mode_4_we; + logic [1:0] mio_pad_sleep_mode_4_qs; + logic [1:0] mio_pad_sleep_mode_4_wd; + logic mio_pad_sleep_mode_5_we; + logic [1:0] mio_pad_sleep_mode_5_qs; + logic [1:0] mio_pad_sleep_mode_5_wd; + logic mio_pad_sleep_mode_6_we; + logic [1:0] mio_pad_sleep_mode_6_qs; + logic [1:0] mio_pad_sleep_mode_6_wd; + logic mio_pad_sleep_mode_7_we; + logic [1:0] mio_pad_sleep_mode_7_qs; + logic [1:0] mio_pad_sleep_mode_7_wd; + logic mio_pad_sleep_mode_8_we; + logic [1:0] mio_pad_sleep_mode_8_qs; + logic [1:0] mio_pad_sleep_mode_8_wd; + logic mio_pad_sleep_mode_9_we; + logic [1:0] mio_pad_sleep_mode_9_qs; + logic [1:0] mio_pad_sleep_mode_9_wd; + logic mio_pad_sleep_mode_10_we; + logic [1:0] mio_pad_sleep_mode_10_qs; + logic [1:0] mio_pad_sleep_mode_10_wd; + logic mio_pad_sleep_mode_11_we; + logic [1:0] mio_pad_sleep_mode_11_qs; + logic [1:0] mio_pad_sleep_mode_11_wd; + logic dio_pad_sleep_status_0_we; + logic dio_pad_sleep_status_0_en_0_qs; + logic dio_pad_sleep_status_0_en_0_wd; + logic dio_pad_sleep_status_0_en_1_qs; + logic dio_pad_sleep_status_0_en_1_wd; + logic dio_pad_sleep_status_0_en_2_qs; + logic dio_pad_sleep_status_0_en_2_wd; + logic dio_pad_sleep_status_0_en_3_qs; + logic dio_pad_sleep_status_0_en_3_wd; + logic dio_pad_sleep_status_0_en_4_qs; + logic dio_pad_sleep_status_0_en_4_wd; + logic dio_pad_sleep_status_0_en_5_qs; + logic dio_pad_sleep_status_0_en_5_wd; + logic dio_pad_sleep_status_0_en_6_qs; + logic dio_pad_sleep_status_0_en_6_wd; + logic dio_pad_sleep_status_0_en_7_qs; + logic dio_pad_sleep_status_0_en_7_wd; + logic dio_pad_sleep_status_0_en_8_qs; + logic dio_pad_sleep_status_0_en_8_wd; + logic dio_pad_sleep_status_0_en_9_qs; + logic dio_pad_sleep_status_0_en_9_wd; + logic dio_pad_sleep_status_0_en_10_qs; + logic dio_pad_sleep_status_0_en_10_wd; + logic dio_pad_sleep_status_0_en_11_qs; + logic dio_pad_sleep_status_0_en_11_wd; + logic dio_pad_sleep_status_0_en_12_qs; + logic dio_pad_sleep_status_0_en_12_wd; + logic dio_pad_sleep_status_0_en_13_qs; + logic dio_pad_sleep_status_0_en_13_wd; + logic dio_pad_sleep_status_0_en_14_qs; + logic dio_pad_sleep_status_0_en_14_wd; + logic dio_pad_sleep_status_0_en_15_qs; + logic dio_pad_sleep_status_0_en_15_wd; + logic dio_pad_sleep_status_0_en_16_qs; + logic dio_pad_sleep_status_0_en_16_wd; + logic dio_pad_sleep_status_0_en_17_qs; + logic dio_pad_sleep_status_0_en_17_wd; + logic dio_pad_sleep_status_0_en_18_qs; + logic dio_pad_sleep_status_0_en_18_wd; + logic dio_pad_sleep_status_0_en_19_qs; + logic dio_pad_sleep_status_0_en_19_wd; + logic dio_pad_sleep_status_0_en_20_qs; + logic dio_pad_sleep_status_0_en_20_wd; + logic dio_pad_sleep_status_0_en_21_qs; + logic dio_pad_sleep_status_0_en_21_wd; + logic dio_pad_sleep_status_0_en_22_qs; + logic dio_pad_sleep_status_0_en_22_wd; + logic dio_pad_sleep_status_0_en_23_qs; + logic dio_pad_sleep_status_0_en_23_wd; + logic dio_pad_sleep_status_0_en_24_qs; + logic dio_pad_sleep_status_0_en_24_wd; + logic dio_pad_sleep_status_0_en_25_qs; + logic dio_pad_sleep_status_0_en_25_wd; + logic dio_pad_sleep_status_0_en_26_qs; + logic dio_pad_sleep_status_0_en_26_wd; + logic dio_pad_sleep_status_0_en_27_qs; + logic dio_pad_sleep_status_0_en_27_wd; + logic dio_pad_sleep_status_0_en_28_qs; + logic dio_pad_sleep_status_0_en_28_wd; + logic dio_pad_sleep_status_0_en_29_qs; + logic dio_pad_sleep_status_0_en_29_wd; + logic dio_pad_sleep_status_0_en_30_qs; + logic dio_pad_sleep_status_0_en_30_wd; + logic dio_pad_sleep_status_0_en_31_qs; + logic dio_pad_sleep_status_0_en_31_wd; + logic dio_pad_sleep_status_1_we; + logic dio_pad_sleep_status_1_en_32_qs; + logic dio_pad_sleep_status_1_en_32_wd; + logic dio_pad_sleep_status_1_en_33_qs; + logic dio_pad_sleep_status_1_en_33_wd; + logic dio_pad_sleep_status_1_en_34_qs; + logic dio_pad_sleep_status_1_en_34_wd; + logic dio_pad_sleep_status_1_en_35_qs; + logic dio_pad_sleep_status_1_en_35_wd; + logic dio_pad_sleep_status_1_en_36_qs; + logic dio_pad_sleep_status_1_en_36_wd; + logic dio_pad_sleep_status_1_en_37_qs; + logic dio_pad_sleep_status_1_en_37_wd; + logic dio_pad_sleep_status_1_en_38_qs; + logic dio_pad_sleep_status_1_en_38_wd; + logic dio_pad_sleep_status_1_en_39_qs; + logic dio_pad_sleep_status_1_en_39_wd; + logic dio_pad_sleep_status_1_en_40_qs; + logic dio_pad_sleep_status_1_en_40_wd; + logic dio_pad_sleep_status_1_en_41_qs; + logic dio_pad_sleep_status_1_en_41_wd; + logic dio_pad_sleep_status_1_en_42_qs; + logic dio_pad_sleep_status_1_en_42_wd; + logic dio_pad_sleep_status_1_en_43_qs; + logic dio_pad_sleep_status_1_en_43_wd; + logic dio_pad_sleep_status_1_en_44_qs; + logic dio_pad_sleep_status_1_en_44_wd; + logic dio_pad_sleep_status_1_en_45_qs; + logic dio_pad_sleep_status_1_en_45_wd; + logic dio_pad_sleep_status_1_en_46_qs; + logic dio_pad_sleep_status_1_en_46_wd; + logic dio_pad_sleep_status_1_en_47_qs; + logic dio_pad_sleep_status_1_en_47_wd; + logic dio_pad_sleep_status_1_en_48_qs; + logic dio_pad_sleep_status_1_en_48_wd; + logic dio_pad_sleep_status_1_en_49_qs; + logic dio_pad_sleep_status_1_en_49_wd; + logic dio_pad_sleep_status_1_en_50_qs; + logic dio_pad_sleep_status_1_en_50_wd; + logic dio_pad_sleep_status_1_en_51_qs; + logic dio_pad_sleep_status_1_en_51_wd; + logic dio_pad_sleep_status_1_en_52_qs; + logic dio_pad_sleep_status_1_en_52_wd; + logic dio_pad_sleep_status_1_en_53_qs; + logic dio_pad_sleep_status_1_en_53_wd; + logic dio_pad_sleep_status_1_en_54_qs; + logic dio_pad_sleep_status_1_en_54_wd; + logic dio_pad_sleep_status_1_en_55_qs; + logic dio_pad_sleep_status_1_en_55_wd; + logic dio_pad_sleep_status_1_en_56_qs; + logic dio_pad_sleep_status_1_en_56_wd; + logic dio_pad_sleep_status_1_en_57_qs; + logic dio_pad_sleep_status_1_en_57_wd; + logic dio_pad_sleep_status_1_en_58_qs; + logic dio_pad_sleep_status_1_en_58_wd; + logic dio_pad_sleep_status_1_en_59_qs; + logic dio_pad_sleep_status_1_en_59_wd; + logic dio_pad_sleep_status_1_en_60_qs; + logic dio_pad_sleep_status_1_en_60_wd; + logic dio_pad_sleep_status_1_en_61_qs; + logic dio_pad_sleep_status_1_en_61_wd; + logic dio_pad_sleep_status_1_en_62_qs; + logic dio_pad_sleep_status_1_en_62_wd; + logic dio_pad_sleep_status_1_en_63_qs; + logic dio_pad_sleep_status_1_en_63_wd; + logic dio_pad_sleep_status_2_we; + logic dio_pad_sleep_status_2_en_64_qs; + logic dio_pad_sleep_status_2_en_64_wd; + logic dio_pad_sleep_status_2_en_65_qs; + logic dio_pad_sleep_status_2_en_65_wd; + logic dio_pad_sleep_status_2_en_66_qs; + logic dio_pad_sleep_status_2_en_66_wd; + logic dio_pad_sleep_status_2_en_67_qs; + logic dio_pad_sleep_status_2_en_67_wd; + logic dio_pad_sleep_status_2_en_68_qs; + logic dio_pad_sleep_status_2_en_68_wd; + logic dio_pad_sleep_status_2_en_69_qs; + logic dio_pad_sleep_status_2_en_69_wd; + logic dio_pad_sleep_status_2_en_70_qs; + logic dio_pad_sleep_status_2_en_70_wd; + logic dio_pad_sleep_status_2_en_71_qs; + logic dio_pad_sleep_status_2_en_71_wd; + logic dio_pad_sleep_status_2_en_72_qs; + logic dio_pad_sleep_status_2_en_72_wd; + logic dio_pad_sleep_regwen_0_we; + logic dio_pad_sleep_regwen_0_qs; + logic dio_pad_sleep_regwen_0_wd; + logic dio_pad_sleep_regwen_1_we; + logic dio_pad_sleep_regwen_1_qs; + logic dio_pad_sleep_regwen_1_wd; + logic dio_pad_sleep_regwen_2_we; + logic dio_pad_sleep_regwen_2_qs; + logic dio_pad_sleep_regwen_2_wd; + logic dio_pad_sleep_regwen_3_we; + logic dio_pad_sleep_regwen_3_qs; + logic dio_pad_sleep_regwen_3_wd; + logic dio_pad_sleep_regwen_4_we; + logic dio_pad_sleep_regwen_4_qs; + logic dio_pad_sleep_regwen_4_wd; + logic dio_pad_sleep_regwen_5_we; + logic dio_pad_sleep_regwen_5_qs; + logic dio_pad_sleep_regwen_5_wd; + logic dio_pad_sleep_regwen_6_we; + logic dio_pad_sleep_regwen_6_qs; + logic dio_pad_sleep_regwen_6_wd; + logic dio_pad_sleep_regwen_7_we; + logic dio_pad_sleep_regwen_7_qs; + logic dio_pad_sleep_regwen_7_wd; + logic dio_pad_sleep_regwen_8_we; + logic dio_pad_sleep_regwen_8_qs; + logic dio_pad_sleep_regwen_8_wd; + logic dio_pad_sleep_regwen_9_we; + logic dio_pad_sleep_regwen_9_qs; + logic dio_pad_sleep_regwen_9_wd; + logic dio_pad_sleep_regwen_10_we; + logic dio_pad_sleep_regwen_10_qs; + logic dio_pad_sleep_regwen_10_wd; + logic dio_pad_sleep_regwen_11_we; + logic dio_pad_sleep_regwen_11_qs; + logic dio_pad_sleep_regwen_11_wd; + logic dio_pad_sleep_regwen_12_we; + logic dio_pad_sleep_regwen_12_qs; + logic dio_pad_sleep_regwen_12_wd; + logic dio_pad_sleep_regwen_13_we; + logic dio_pad_sleep_regwen_13_qs; + logic dio_pad_sleep_regwen_13_wd; + logic dio_pad_sleep_regwen_14_we; + logic dio_pad_sleep_regwen_14_qs; + logic dio_pad_sleep_regwen_14_wd; + logic dio_pad_sleep_regwen_15_we; + logic dio_pad_sleep_regwen_15_qs; + logic dio_pad_sleep_regwen_15_wd; + logic dio_pad_sleep_regwen_16_we; + logic dio_pad_sleep_regwen_16_qs; + logic dio_pad_sleep_regwen_16_wd; + logic dio_pad_sleep_regwen_17_we; + logic dio_pad_sleep_regwen_17_qs; + logic dio_pad_sleep_regwen_17_wd; + logic dio_pad_sleep_regwen_18_we; + logic dio_pad_sleep_regwen_18_qs; + logic dio_pad_sleep_regwen_18_wd; + logic dio_pad_sleep_regwen_19_we; + logic dio_pad_sleep_regwen_19_qs; + logic dio_pad_sleep_regwen_19_wd; + logic dio_pad_sleep_regwen_20_we; + logic dio_pad_sleep_regwen_20_qs; + logic dio_pad_sleep_regwen_20_wd; + logic dio_pad_sleep_regwen_21_we; + logic dio_pad_sleep_regwen_21_qs; + logic dio_pad_sleep_regwen_21_wd; + logic dio_pad_sleep_regwen_22_we; + logic dio_pad_sleep_regwen_22_qs; + logic dio_pad_sleep_regwen_22_wd; + logic dio_pad_sleep_regwen_23_we; + logic dio_pad_sleep_regwen_23_qs; + logic dio_pad_sleep_regwen_23_wd; + logic dio_pad_sleep_regwen_24_we; + logic dio_pad_sleep_regwen_24_qs; + logic dio_pad_sleep_regwen_24_wd; + logic dio_pad_sleep_regwen_25_we; + logic dio_pad_sleep_regwen_25_qs; + logic dio_pad_sleep_regwen_25_wd; + logic dio_pad_sleep_regwen_26_we; + logic dio_pad_sleep_regwen_26_qs; + logic dio_pad_sleep_regwen_26_wd; + logic dio_pad_sleep_regwen_27_we; + logic dio_pad_sleep_regwen_27_qs; + logic dio_pad_sleep_regwen_27_wd; + logic dio_pad_sleep_regwen_28_we; + logic dio_pad_sleep_regwen_28_qs; + logic dio_pad_sleep_regwen_28_wd; + logic dio_pad_sleep_regwen_29_we; + logic dio_pad_sleep_regwen_29_qs; + logic dio_pad_sleep_regwen_29_wd; + logic dio_pad_sleep_regwen_30_we; + logic dio_pad_sleep_regwen_30_qs; + logic dio_pad_sleep_regwen_30_wd; + logic dio_pad_sleep_regwen_31_we; + logic dio_pad_sleep_regwen_31_qs; + logic dio_pad_sleep_regwen_31_wd; + logic dio_pad_sleep_regwen_32_we; + logic dio_pad_sleep_regwen_32_qs; + logic dio_pad_sleep_regwen_32_wd; + logic dio_pad_sleep_regwen_33_we; + logic dio_pad_sleep_regwen_33_qs; + logic dio_pad_sleep_regwen_33_wd; + logic dio_pad_sleep_regwen_34_we; + logic dio_pad_sleep_regwen_34_qs; + logic dio_pad_sleep_regwen_34_wd; + logic dio_pad_sleep_regwen_35_we; + logic dio_pad_sleep_regwen_35_qs; + logic dio_pad_sleep_regwen_35_wd; + logic dio_pad_sleep_regwen_36_we; + logic dio_pad_sleep_regwen_36_qs; + logic dio_pad_sleep_regwen_36_wd; + logic dio_pad_sleep_regwen_37_we; + logic dio_pad_sleep_regwen_37_qs; + logic dio_pad_sleep_regwen_37_wd; + logic dio_pad_sleep_regwen_38_we; + logic dio_pad_sleep_regwen_38_qs; + logic dio_pad_sleep_regwen_38_wd; + logic dio_pad_sleep_regwen_39_we; + logic dio_pad_sleep_regwen_39_qs; + logic dio_pad_sleep_regwen_39_wd; + logic dio_pad_sleep_regwen_40_we; + logic dio_pad_sleep_regwen_40_qs; + logic dio_pad_sleep_regwen_40_wd; + logic dio_pad_sleep_regwen_41_we; + logic dio_pad_sleep_regwen_41_qs; + logic dio_pad_sleep_regwen_41_wd; + logic dio_pad_sleep_regwen_42_we; + logic dio_pad_sleep_regwen_42_qs; + logic dio_pad_sleep_regwen_42_wd; + logic dio_pad_sleep_regwen_43_we; + logic dio_pad_sleep_regwen_43_qs; + logic dio_pad_sleep_regwen_43_wd; + logic dio_pad_sleep_regwen_44_we; + logic dio_pad_sleep_regwen_44_qs; + logic dio_pad_sleep_regwen_44_wd; + logic dio_pad_sleep_regwen_45_we; + logic dio_pad_sleep_regwen_45_qs; + logic dio_pad_sleep_regwen_45_wd; + logic dio_pad_sleep_regwen_46_we; + logic dio_pad_sleep_regwen_46_qs; + logic dio_pad_sleep_regwen_46_wd; + logic dio_pad_sleep_regwen_47_we; + logic dio_pad_sleep_regwen_47_qs; + logic dio_pad_sleep_regwen_47_wd; + logic dio_pad_sleep_regwen_48_we; + logic dio_pad_sleep_regwen_48_qs; + logic dio_pad_sleep_regwen_48_wd; + logic dio_pad_sleep_regwen_49_we; + logic dio_pad_sleep_regwen_49_qs; + logic dio_pad_sleep_regwen_49_wd; + logic dio_pad_sleep_regwen_50_we; + logic dio_pad_sleep_regwen_50_qs; + logic dio_pad_sleep_regwen_50_wd; + logic dio_pad_sleep_regwen_51_we; + logic dio_pad_sleep_regwen_51_qs; + logic dio_pad_sleep_regwen_51_wd; + logic dio_pad_sleep_regwen_52_we; + logic dio_pad_sleep_regwen_52_qs; + logic dio_pad_sleep_regwen_52_wd; + logic dio_pad_sleep_regwen_53_we; + logic dio_pad_sleep_regwen_53_qs; + logic dio_pad_sleep_regwen_53_wd; + logic dio_pad_sleep_regwen_54_we; + logic dio_pad_sleep_regwen_54_qs; + logic dio_pad_sleep_regwen_54_wd; + logic dio_pad_sleep_regwen_55_we; + logic dio_pad_sleep_regwen_55_qs; + logic dio_pad_sleep_regwen_55_wd; + logic dio_pad_sleep_regwen_56_we; + logic dio_pad_sleep_regwen_56_qs; + logic dio_pad_sleep_regwen_56_wd; + logic dio_pad_sleep_regwen_57_we; + logic dio_pad_sleep_regwen_57_qs; + logic dio_pad_sleep_regwen_57_wd; + logic dio_pad_sleep_regwen_58_we; + logic dio_pad_sleep_regwen_58_qs; + logic dio_pad_sleep_regwen_58_wd; + logic dio_pad_sleep_regwen_59_we; + logic dio_pad_sleep_regwen_59_qs; + logic dio_pad_sleep_regwen_59_wd; + logic dio_pad_sleep_regwen_60_we; + logic dio_pad_sleep_regwen_60_qs; + logic dio_pad_sleep_regwen_60_wd; + logic dio_pad_sleep_regwen_61_we; + logic dio_pad_sleep_regwen_61_qs; + logic dio_pad_sleep_regwen_61_wd; + logic dio_pad_sleep_regwen_62_we; + logic dio_pad_sleep_regwen_62_qs; + logic dio_pad_sleep_regwen_62_wd; + logic dio_pad_sleep_regwen_63_we; + logic dio_pad_sleep_regwen_63_qs; + logic dio_pad_sleep_regwen_63_wd; + logic dio_pad_sleep_regwen_64_we; + logic dio_pad_sleep_regwen_64_qs; + logic dio_pad_sleep_regwen_64_wd; + logic dio_pad_sleep_regwen_65_we; + logic dio_pad_sleep_regwen_65_qs; + logic dio_pad_sleep_regwen_65_wd; + logic dio_pad_sleep_regwen_66_we; + logic dio_pad_sleep_regwen_66_qs; + logic dio_pad_sleep_regwen_66_wd; + logic dio_pad_sleep_regwen_67_we; + logic dio_pad_sleep_regwen_67_qs; + logic dio_pad_sleep_regwen_67_wd; + logic dio_pad_sleep_regwen_68_we; + logic dio_pad_sleep_regwen_68_qs; + logic dio_pad_sleep_regwen_68_wd; + logic dio_pad_sleep_regwen_69_we; + logic dio_pad_sleep_regwen_69_qs; + logic dio_pad_sleep_regwen_69_wd; + logic dio_pad_sleep_regwen_70_we; + logic dio_pad_sleep_regwen_70_qs; + logic dio_pad_sleep_regwen_70_wd; + logic dio_pad_sleep_regwen_71_we; + logic dio_pad_sleep_regwen_71_qs; + logic dio_pad_sleep_regwen_71_wd; + logic dio_pad_sleep_regwen_72_we; + logic dio_pad_sleep_regwen_72_qs; + logic dio_pad_sleep_regwen_72_wd; + logic dio_pad_sleep_en_0_we; + logic dio_pad_sleep_en_0_qs; + logic dio_pad_sleep_en_0_wd; + logic dio_pad_sleep_en_1_we; + logic dio_pad_sleep_en_1_qs; + logic dio_pad_sleep_en_1_wd; + logic dio_pad_sleep_en_2_we; + logic dio_pad_sleep_en_2_qs; + logic dio_pad_sleep_en_2_wd; + logic dio_pad_sleep_en_3_we; + logic dio_pad_sleep_en_3_qs; + logic dio_pad_sleep_en_3_wd; + logic dio_pad_sleep_en_4_we; + logic dio_pad_sleep_en_4_qs; + logic dio_pad_sleep_en_4_wd; + logic dio_pad_sleep_en_5_we; + logic dio_pad_sleep_en_5_qs; + logic dio_pad_sleep_en_5_wd; + logic dio_pad_sleep_en_6_we; + logic dio_pad_sleep_en_6_qs; + logic dio_pad_sleep_en_6_wd; + logic dio_pad_sleep_en_7_we; + logic dio_pad_sleep_en_7_qs; + logic dio_pad_sleep_en_7_wd; + logic dio_pad_sleep_en_8_we; + logic dio_pad_sleep_en_8_qs; + logic dio_pad_sleep_en_8_wd; + logic dio_pad_sleep_en_9_we; + logic dio_pad_sleep_en_9_qs; + logic dio_pad_sleep_en_9_wd; + logic dio_pad_sleep_en_10_we; + logic dio_pad_sleep_en_10_qs; + logic dio_pad_sleep_en_10_wd; + logic dio_pad_sleep_en_11_we; + logic dio_pad_sleep_en_11_qs; + logic dio_pad_sleep_en_11_wd; + logic dio_pad_sleep_en_12_we; + logic dio_pad_sleep_en_12_qs; + logic dio_pad_sleep_en_12_wd; + logic dio_pad_sleep_en_13_we; + logic dio_pad_sleep_en_13_qs; + logic dio_pad_sleep_en_13_wd; + logic dio_pad_sleep_en_14_we; + logic dio_pad_sleep_en_14_qs; + logic dio_pad_sleep_en_14_wd; + logic dio_pad_sleep_en_15_we; + logic dio_pad_sleep_en_15_qs; + logic dio_pad_sleep_en_15_wd; + logic dio_pad_sleep_en_16_we; + logic dio_pad_sleep_en_16_qs; + logic dio_pad_sleep_en_16_wd; + logic dio_pad_sleep_en_17_we; + logic dio_pad_sleep_en_17_qs; + logic dio_pad_sleep_en_17_wd; + logic dio_pad_sleep_en_18_we; + logic dio_pad_sleep_en_18_qs; + logic dio_pad_sleep_en_18_wd; + logic dio_pad_sleep_en_19_we; + logic dio_pad_sleep_en_19_qs; + logic dio_pad_sleep_en_19_wd; + logic dio_pad_sleep_en_20_we; + logic dio_pad_sleep_en_20_qs; + logic dio_pad_sleep_en_20_wd; + logic dio_pad_sleep_en_21_we; + logic dio_pad_sleep_en_21_qs; + logic dio_pad_sleep_en_21_wd; + logic dio_pad_sleep_en_22_we; + logic dio_pad_sleep_en_22_qs; + logic dio_pad_sleep_en_22_wd; + logic dio_pad_sleep_en_23_we; + logic dio_pad_sleep_en_23_qs; + logic dio_pad_sleep_en_23_wd; + logic dio_pad_sleep_en_24_we; + logic dio_pad_sleep_en_24_qs; + logic dio_pad_sleep_en_24_wd; + logic dio_pad_sleep_en_25_we; + logic dio_pad_sleep_en_25_qs; + logic dio_pad_sleep_en_25_wd; + logic dio_pad_sleep_en_26_we; + logic dio_pad_sleep_en_26_qs; + logic dio_pad_sleep_en_26_wd; + logic dio_pad_sleep_en_27_we; + logic dio_pad_sleep_en_27_qs; + logic dio_pad_sleep_en_27_wd; + logic dio_pad_sleep_en_28_we; + logic dio_pad_sleep_en_28_qs; + logic dio_pad_sleep_en_28_wd; + logic dio_pad_sleep_en_29_we; + logic dio_pad_sleep_en_29_qs; + logic dio_pad_sleep_en_29_wd; + logic dio_pad_sleep_en_30_we; + logic dio_pad_sleep_en_30_qs; + logic dio_pad_sleep_en_30_wd; + logic dio_pad_sleep_en_31_we; + logic dio_pad_sleep_en_31_qs; + logic dio_pad_sleep_en_31_wd; + logic dio_pad_sleep_en_32_we; + logic dio_pad_sleep_en_32_qs; + logic dio_pad_sleep_en_32_wd; + logic dio_pad_sleep_en_33_we; + logic dio_pad_sleep_en_33_qs; + logic dio_pad_sleep_en_33_wd; + logic dio_pad_sleep_en_34_we; + logic dio_pad_sleep_en_34_qs; + logic dio_pad_sleep_en_34_wd; + logic dio_pad_sleep_en_35_we; + logic dio_pad_sleep_en_35_qs; + logic dio_pad_sleep_en_35_wd; + logic dio_pad_sleep_en_36_we; + logic dio_pad_sleep_en_36_qs; + logic dio_pad_sleep_en_36_wd; + logic dio_pad_sleep_en_37_we; + logic dio_pad_sleep_en_37_qs; + logic dio_pad_sleep_en_37_wd; + logic dio_pad_sleep_en_38_we; + logic dio_pad_sleep_en_38_qs; + logic dio_pad_sleep_en_38_wd; + logic dio_pad_sleep_en_39_we; + logic dio_pad_sleep_en_39_qs; + logic dio_pad_sleep_en_39_wd; + logic dio_pad_sleep_en_40_we; + logic dio_pad_sleep_en_40_qs; + logic dio_pad_sleep_en_40_wd; + logic dio_pad_sleep_en_41_we; + logic dio_pad_sleep_en_41_qs; + logic dio_pad_sleep_en_41_wd; + logic dio_pad_sleep_en_42_we; + logic dio_pad_sleep_en_42_qs; + logic dio_pad_sleep_en_42_wd; + logic dio_pad_sleep_en_43_we; + logic dio_pad_sleep_en_43_qs; + logic dio_pad_sleep_en_43_wd; + logic dio_pad_sleep_en_44_we; + logic dio_pad_sleep_en_44_qs; + logic dio_pad_sleep_en_44_wd; + logic dio_pad_sleep_en_45_we; + logic dio_pad_sleep_en_45_qs; + logic dio_pad_sleep_en_45_wd; + logic dio_pad_sleep_en_46_we; + logic dio_pad_sleep_en_46_qs; + logic dio_pad_sleep_en_46_wd; + logic dio_pad_sleep_en_47_we; + logic dio_pad_sleep_en_47_qs; + logic dio_pad_sleep_en_47_wd; + logic dio_pad_sleep_en_48_we; + logic dio_pad_sleep_en_48_qs; + logic dio_pad_sleep_en_48_wd; + logic dio_pad_sleep_en_49_we; + logic dio_pad_sleep_en_49_qs; + logic dio_pad_sleep_en_49_wd; + logic dio_pad_sleep_en_50_we; + logic dio_pad_sleep_en_50_qs; + logic dio_pad_sleep_en_50_wd; + logic dio_pad_sleep_en_51_we; + logic dio_pad_sleep_en_51_qs; + logic dio_pad_sleep_en_51_wd; + logic dio_pad_sleep_en_52_we; + logic dio_pad_sleep_en_52_qs; + logic dio_pad_sleep_en_52_wd; + logic dio_pad_sleep_en_53_we; + logic dio_pad_sleep_en_53_qs; + logic dio_pad_sleep_en_53_wd; + logic dio_pad_sleep_en_54_we; + logic dio_pad_sleep_en_54_qs; + logic dio_pad_sleep_en_54_wd; + logic dio_pad_sleep_en_55_we; + logic dio_pad_sleep_en_55_qs; + logic dio_pad_sleep_en_55_wd; + logic dio_pad_sleep_en_56_we; + logic dio_pad_sleep_en_56_qs; + logic dio_pad_sleep_en_56_wd; + logic dio_pad_sleep_en_57_we; + logic dio_pad_sleep_en_57_qs; + logic dio_pad_sleep_en_57_wd; + logic dio_pad_sleep_en_58_we; + logic dio_pad_sleep_en_58_qs; + logic dio_pad_sleep_en_58_wd; + logic dio_pad_sleep_en_59_we; + logic dio_pad_sleep_en_59_qs; + logic dio_pad_sleep_en_59_wd; + logic dio_pad_sleep_en_60_we; + logic dio_pad_sleep_en_60_qs; + logic dio_pad_sleep_en_60_wd; + logic dio_pad_sleep_en_61_we; + logic dio_pad_sleep_en_61_qs; + logic dio_pad_sleep_en_61_wd; + logic dio_pad_sleep_en_62_we; + logic dio_pad_sleep_en_62_qs; + logic dio_pad_sleep_en_62_wd; + logic dio_pad_sleep_en_63_we; + logic dio_pad_sleep_en_63_qs; + logic dio_pad_sleep_en_63_wd; + logic dio_pad_sleep_en_64_we; + logic dio_pad_sleep_en_64_qs; + logic dio_pad_sleep_en_64_wd; + logic dio_pad_sleep_en_65_we; + logic dio_pad_sleep_en_65_qs; + logic dio_pad_sleep_en_65_wd; + logic dio_pad_sleep_en_66_we; + logic dio_pad_sleep_en_66_qs; + logic dio_pad_sleep_en_66_wd; + logic dio_pad_sleep_en_67_we; + logic dio_pad_sleep_en_67_qs; + logic dio_pad_sleep_en_67_wd; + logic dio_pad_sleep_en_68_we; + logic dio_pad_sleep_en_68_qs; + logic dio_pad_sleep_en_68_wd; + logic dio_pad_sleep_en_69_we; + logic dio_pad_sleep_en_69_qs; + logic dio_pad_sleep_en_69_wd; + logic dio_pad_sleep_en_70_we; + logic dio_pad_sleep_en_70_qs; + logic dio_pad_sleep_en_70_wd; + logic dio_pad_sleep_en_71_we; + logic dio_pad_sleep_en_71_qs; + logic dio_pad_sleep_en_71_wd; + logic dio_pad_sleep_en_72_we; + logic dio_pad_sleep_en_72_qs; + logic dio_pad_sleep_en_72_wd; + logic dio_pad_sleep_mode_0_we; + logic [1:0] dio_pad_sleep_mode_0_qs; + logic [1:0] dio_pad_sleep_mode_0_wd; + logic dio_pad_sleep_mode_1_we; + logic [1:0] dio_pad_sleep_mode_1_qs; + logic [1:0] dio_pad_sleep_mode_1_wd; + logic dio_pad_sleep_mode_2_we; + logic [1:0] dio_pad_sleep_mode_2_qs; + logic [1:0] dio_pad_sleep_mode_2_wd; + logic dio_pad_sleep_mode_3_we; + logic [1:0] dio_pad_sleep_mode_3_qs; + logic [1:0] dio_pad_sleep_mode_3_wd; + logic dio_pad_sleep_mode_4_we; + logic [1:0] dio_pad_sleep_mode_4_qs; + logic [1:0] dio_pad_sleep_mode_4_wd; + logic dio_pad_sleep_mode_5_we; + logic [1:0] dio_pad_sleep_mode_5_qs; + logic [1:0] dio_pad_sleep_mode_5_wd; + logic dio_pad_sleep_mode_6_we; + logic [1:0] dio_pad_sleep_mode_6_qs; + logic [1:0] dio_pad_sleep_mode_6_wd; + logic dio_pad_sleep_mode_7_we; + logic [1:0] dio_pad_sleep_mode_7_qs; + logic [1:0] dio_pad_sleep_mode_7_wd; + logic dio_pad_sleep_mode_8_we; + logic [1:0] dio_pad_sleep_mode_8_qs; + logic [1:0] dio_pad_sleep_mode_8_wd; + logic dio_pad_sleep_mode_9_we; + logic [1:0] dio_pad_sleep_mode_9_qs; + logic [1:0] dio_pad_sleep_mode_9_wd; + logic dio_pad_sleep_mode_10_we; + logic [1:0] dio_pad_sleep_mode_10_qs; + logic [1:0] dio_pad_sleep_mode_10_wd; + logic dio_pad_sleep_mode_11_we; + logic [1:0] dio_pad_sleep_mode_11_qs; + logic [1:0] dio_pad_sleep_mode_11_wd; + logic dio_pad_sleep_mode_12_we; + logic [1:0] dio_pad_sleep_mode_12_qs; + logic [1:0] dio_pad_sleep_mode_12_wd; + logic dio_pad_sleep_mode_13_we; + logic [1:0] dio_pad_sleep_mode_13_qs; + logic [1:0] dio_pad_sleep_mode_13_wd; + logic dio_pad_sleep_mode_14_we; + logic [1:0] dio_pad_sleep_mode_14_qs; + logic [1:0] dio_pad_sleep_mode_14_wd; + logic dio_pad_sleep_mode_15_we; + logic [1:0] dio_pad_sleep_mode_15_qs; + logic [1:0] dio_pad_sleep_mode_15_wd; + logic dio_pad_sleep_mode_16_we; + logic [1:0] dio_pad_sleep_mode_16_qs; + logic [1:0] dio_pad_sleep_mode_16_wd; + logic dio_pad_sleep_mode_17_we; + logic [1:0] dio_pad_sleep_mode_17_qs; + logic [1:0] dio_pad_sleep_mode_17_wd; + logic dio_pad_sleep_mode_18_we; + logic [1:0] dio_pad_sleep_mode_18_qs; + logic [1:0] dio_pad_sleep_mode_18_wd; + logic dio_pad_sleep_mode_19_we; + logic [1:0] dio_pad_sleep_mode_19_qs; + logic [1:0] dio_pad_sleep_mode_19_wd; + logic dio_pad_sleep_mode_20_we; + logic [1:0] dio_pad_sleep_mode_20_qs; + logic [1:0] dio_pad_sleep_mode_20_wd; + logic dio_pad_sleep_mode_21_we; + logic [1:0] dio_pad_sleep_mode_21_qs; + logic [1:0] dio_pad_sleep_mode_21_wd; + logic dio_pad_sleep_mode_22_we; + logic [1:0] dio_pad_sleep_mode_22_qs; + logic [1:0] dio_pad_sleep_mode_22_wd; + logic dio_pad_sleep_mode_23_we; + logic [1:0] dio_pad_sleep_mode_23_qs; + logic [1:0] dio_pad_sleep_mode_23_wd; + logic dio_pad_sleep_mode_24_we; + logic [1:0] dio_pad_sleep_mode_24_qs; + logic [1:0] dio_pad_sleep_mode_24_wd; + logic dio_pad_sleep_mode_25_we; + logic [1:0] dio_pad_sleep_mode_25_qs; + logic [1:0] dio_pad_sleep_mode_25_wd; + logic dio_pad_sleep_mode_26_we; + logic [1:0] dio_pad_sleep_mode_26_qs; + logic [1:0] dio_pad_sleep_mode_26_wd; + logic dio_pad_sleep_mode_27_we; + logic [1:0] dio_pad_sleep_mode_27_qs; + logic [1:0] dio_pad_sleep_mode_27_wd; + logic dio_pad_sleep_mode_28_we; + logic [1:0] dio_pad_sleep_mode_28_qs; + logic [1:0] dio_pad_sleep_mode_28_wd; + logic dio_pad_sleep_mode_29_we; + logic [1:0] dio_pad_sleep_mode_29_qs; + logic [1:0] dio_pad_sleep_mode_29_wd; + logic dio_pad_sleep_mode_30_we; + logic [1:0] dio_pad_sleep_mode_30_qs; + logic [1:0] dio_pad_sleep_mode_30_wd; + logic dio_pad_sleep_mode_31_we; + logic [1:0] dio_pad_sleep_mode_31_qs; + logic [1:0] dio_pad_sleep_mode_31_wd; + logic dio_pad_sleep_mode_32_we; + logic [1:0] dio_pad_sleep_mode_32_qs; + logic [1:0] dio_pad_sleep_mode_32_wd; + logic dio_pad_sleep_mode_33_we; + logic [1:0] dio_pad_sleep_mode_33_qs; + logic [1:0] dio_pad_sleep_mode_33_wd; + logic dio_pad_sleep_mode_34_we; + logic [1:0] dio_pad_sleep_mode_34_qs; + logic [1:0] dio_pad_sleep_mode_34_wd; + logic dio_pad_sleep_mode_35_we; + logic [1:0] dio_pad_sleep_mode_35_qs; + logic [1:0] dio_pad_sleep_mode_35_wd; + logic dio_pad_sleep_mode_36_we; + logic [1:0] dio_pad_sleep_mode_36_qs; + logic [1:0] dio_pad_sleep_mode_36_wd; + logic dio_pad_sleep_mode_37_we; + logic [1:0] dio_pad_sleep_mode_37_qs; + logic [1:0] dio_pad_sleep_mode_37_wd; + logic dio_pad_sleep_mode_38_we; + logic [1:0] dio_pad_sleep_mode_38_qs; + logic [1:0] dio_pad_sleep_mode_38_wd; + logic dio_pad_sleep_mode_39_we; + logic [1:0] dio_pad_sleep_mode_39_qs; + logic [1:0] dio_pad_sleep_mode_39_wd; + logic dio_pad_sleep_mode_40_we; + logic [1:0] dio_pad_sleep_mode_40_qs; + logic [1:0] dio_pad_sleep_mode_40_wd; + logic dio_pad_sleep_mode_41_we; + logic [1:0] dio_pad_sleep_mode_41_qs; + logic [1:0] dio_pad_sleep_mode_41_wd; + logic dio_pad_sleep_mode_42_we; + logic [1:0] dio_pad_sleep_mode_42_qs; + logic [1:0] dio_pad_sleep_mode_42_wd; + logic dio_pad_sleep_mode_43_we; + logic [1:0] dio_pad_sleep_mode_43_qs; + logic [1:0] dio_pad_sleep_mode_43_wd; + logic dio_pad_sleep_mode_44_we; + logic [1:0] dio_pad_sleep_mode_44_qs; + logic [1:0] dio_pad_sleep_mode_44_wd; + logic dio_pad_sleep_mode_45_we; + logic [1:0] dio_pad_sleep_mode_45_qs; + logic [1:0] dio_pad_sleep_mode_45_wd; + logic dio_pad_sleep_mode_46_we; + logic [1:0] dio_pad_sleep_mode_46_qs; + logic [1:0] dio_pad_sleep_mode_46_wd; + logic dio_pad_sleep_mode_47_we; + logic [1:0] dio_pad_sleep_mode_47_qs; + logic [1:0] dio_pad_sleep_mode_47_wd; + logic dio_pad_sleep_mode_48_we; + logic [1:0] dio_pad_sleep_mode_48_qs; + logic [1:0] dio_pad_sleep_mode_48_wd; + logic dio_pad_sleep_mode_49_we; + logic [1:0] dio_pad_sleep_mode_49_qs; + logic [1:0] dio_pad_sleep_mode_49_wd; + logic dio_pad_sleep_mode_50_we; + logic [1:0] dio_pad_sleep_mode_50_qs; + logic [1:0] dio_pad_sleep_mode_50_wd; + logic dio_pad_sleep_mode_51_we; + logic [1:0] dio_pad_sleep_mode_51_qs; + logic [1:0] dio_pad_sleep_mode_51_wd; + logic dio_pad_sleep_mode_52_we; + logic [1:0] dio_pad_sleep_mode_52_qs; + logic [1:0] dio_pad_sleep_mode_52_wd; + logic dio_pad_sleep_mode_53_we; + logic [1:0] dio_pad_sleep_mode_53_qs; + logic [1:0] dio_pad_sleep_mode_53_wd; + logic dio_pad_sleep_mode_54_we; + logic [1:0] dio_pad_sleep_mode_54_qs; + logic [1:0] dio_pad_sleep_mode_54_wd; + logic dio_pad_sleep_mode_55_we; + logic [1:0] dio_pad_sleep_mode_55_qs; + logic [1:0] dio_pad_sleep_mode_55_wd; + logic dio_pad_sleep_mode_56_we; + logic [1:0] dio_pad_sleep_mode_56_qs; + logic [1:0] dio_pad_sleep_mode_56_wd; + logic dio_pad_sleep_mode_57_we; + logic [1:0] dio_pad_sleep_mode_57_qs; + logic [1:0] dio_pad_sleep_mode_57_wd; + logic dio_pad_sleep_mode_58_we; + logic [1:0] dio_pad_sleep_mode_58_qs; + logic [1:0] dio_pad_sleep_mode_58_wd; + logic dio_pad_sleep_mode_59_we; + logic [1:0] dio_pad_sleep_mode_59_qs; + logic [1:0] dio_pad_sleep_mode_59_wd; + logic dio_pad_sleep_mode_60_we; + logic [1:0] dio_pad_sleep_mode_60_qs; + logic [1:0] dio_pad_sleep_mode_60_wd; + logic dio_pad_sleep_mode_61_we; + logic [1:0] dio_pad_sleep_mode_61_qs; + logic [1:0] dio_pad_sleep_mode_61_wd; + logic dio_pad_sleep_mode_62_we; + logic [1:0] dio_pad_sleep_mode_62_qs; + logic [1:0] dio_pad_sleep_mode_62_wd; + logic dio_pad_sleep_mode_63_we; + logic [1:0] dio_pad_sleep_mode_63_qs; + logic [1:0] dio_pad_sleep_mode_63_wd; + logic dio_pad_sleep_mode_64_we; + logic [1:0] dio_pad_sleep_mode_64_qs; + logic [1:0] dio_pad_sleep_mode_64_wd; + logic dio_pad_sleep_mode_65_we; + logic [1:0] dio_pad_sleep_mode_65_qs; + logic [1:0] dio_pad_sleep_mode_65_wd; + logic dio_pad_sleep_mode_66_we; + logic [1:0] dio_pad_sleep_mode_66_qs; + logic [1:0] dio_pad_sleep_mode_66_wd; + logic dio_pad_sleep_mode_67_we; + logic [1:0] dio_pad_sleep_mode_67_qs; + logic [1:0] dio_pad_sleep_mode_67_wd; + logic dio_pad_sleep_mode_68_we; + logic [1:0] dio_pad_sleep_mode_68_qs; + logic [1:0] dio_pad_sleep_mode_68_wd; + logic dio_pad_sleep_mode_69_we; + logic [1:0] dio_pad_sleep_mode_69_qs; + logic [1:0] dio_pad_sleep_mode_69_wd; + logic dio_pad_sleep_mode_70_we; + logic [1:0] dio_pad_sleep_mode_70_qs; + logic [1:0] dio_pad_sleep_mode_70_wd; + logic dio_pad_sleep_mode_71_we; + logic [1:0] dio_pad_sleep_mode_71_qs; + logic [1:0] dio_pad_sleep_mode_71_wd; + logic dio_pad_sleep_mode_72_we; + logic [1:0] dio_pad_sleep_mode_72_qs; + logic [1:0] dio_pad_sleep_mode_72_wd; + logic wkup_detector_regwen_0_we; + logic wkup_detector_regwen_0_qs; + logic wkup_detector_regwen_0_wd; + logic wkup_detector_regwen_1_we; + logic wkup_detector_regwen_1_qs; + logic wkup_detector_regwen_1_wd; + logic wkup_detector_regwen_2_we; + logic wkup_detector_regwen_2_qs; + logic wkup_detector_regwen_2_wd; + logic wkup_detector_regwen_3_we; + logic wkup_detector_regwen_3_qs; + logic wkup_detector_regwen_3_wd; + logic wkup_detector_regwen_4_we; + logic wkup_detector_regwen_4_qs; + logic wkup_detector_regwen_4_wd; + logic wkup_detector_regwen_5_we; + logic wkup_detector_regwen_5_qs; + logic wkup_detector_regwen_5_wd; + logic wkup_detector_regwen_6_we; + logic wkup_detector_regwen_6_qs; + logic wkup_detector_regwen_6_wd; + logic wkup_detector_regwen_7_we; + logic wkup_detector_regwen_7_qs; + logic wkup_detector_regwen_7_wd; + logic wkup_detector_en_0_we; + logic [0:0] wkup_detector_en_0_qs; + logic wkup_detector_en_0_busy; + logic wkup_detector_en_1_we; + logic [0:0] wkup_detector_en_1_qs; + logic wkup_detector_en_1_busy; + logic wkup_detector_en_2_we; + logic [0:0] wkup_detector_en_2_qs; + logic wkup_detector_en_2_busy; + logic wkup_detector_en_3_we; + logic [0:0] wkup_detector_en_3_qs; + logic wkup_detector_en_3_busy; + logic wkup_detector_en_4_we; + logic [0:0] wkup_detector_en_4_qs; + logic wkup_detector_en_4_busy; + logic wkup_detector_en_5_we; + logic [0:0] wkup_detector_en_5_qs; + logic wkup_detector_en_5_busy; + logic wkup_detector_en_6_we; + logic [0:0] wkup_detector_en_6_qs; + logic wkup_detector_en_6_busy; + logic wkup_detector_en_7_we; + logic [0:0] wkup_detector_en_7_qs; + logic wkup_detector_en_7_busy; + logic wkup_detector_0_we; + logic [4:0] wkup_detector_0_qs; + logic wkup_detector_0_busy; + logic wkup_detector_1_we; + logic [4:0] wkup_detector_1_qs; + logic wkup_detector_1_busy; + logic wkup_detector_2_we; + logic [4:0] wkup_detector_2_qs; + logic wkup_detector_2_busy; + logic wkup_detector_3_we; + logic [4:0] wkup_detector_3_qs; + logic wkup_detector_3_busy; + logic wkup_detector_4_we; + logic [4:0] wkup_detector_4_qs; + logic wkup_detector_4_busy; + logic wkup_detector_5_we; + logic [4:0] wkup_detector_5_qs; + logic wkup_detector_5_busy; + logic wkup_detector_6_we; + logic [4:0] wkup_detector_6_qs; + logic wkup_detector_6_busy; + logic wkup_detector_7_we; + logic [4:0] wkup_detector_7_qs; + logic wkup_detector_7_busy; + logic wkup_detector_cnt_th_0_we; + logic [7:0] wkup_detector_cnt_th_0_qs; + logic wkup_detector_cnt_th_0_busy; + logic wkup_detector_cnt_th_1_we; + logic [7:0] wkup_detector_cnt_th_1_qs; + logic wkup_detector_cnt_th_1_busy; + logic wkup_detector_cnt_th_2_we; + logic [7:0] wkup_detector_cnt_th_2_qs; + logic wkup_detector_cnt_th_2_busy; + logic wkup_detector_cnt_th_3_we; + logic [7:0] wkup_detector_cnt_th_3_qs; + logic wkup_detector_cnt_th_3_busy; + logic wkup_detector_cnt_th_4_we; + logic [7:0] wkup_detector_cnt_th_4_qs; + logic wkup_detector_cnt_th_4_busy; + logic wkup_detector_cnt_th_5_we; + logic [7:0] wkup_detector_cnt_th_5_qs; + logic wkup_detector_cnt_th_5_busy; + logic wkup_detector_cnt_th_6_we; + logic [7:0] wkup_detector_cnt_th_6_qs; + logic wkup_detector_cnt_th_6_busy; + logic wkup_detector_cnt_th_7_we; + logic [7:0] wkup_detector_cnt_th_7_qs; + logic wkup_detector_cnt_th_7_busy; + logic wkup_detector_padsel_0_we; + logic [6:0] wkup_detector_padsel_0_qs; + logic [6:0] wkup_detector_padsel_0_wd; + logic wkup_detector_padsel_1_we; + logic [6:0] wkup_detector_padsel_1_qs; + logic [6:0] wkup_detector_padsel_1_wd; + logic wkup_detector_padsel_2_we; + logic [6:0] wkup_detector_padsel_2_qs; + logic [6:0] wkup_detector_padsel_2_wd; + logic wkup_detector_padsel_3_we; + logic [6:0] wkup_detector_padsel_3_qs; + logic [6:0] wkup_detector_padsel_3_wd; + logic wkup_detector_padsel_4_we; + logic [6:0] wkup_detector_padsel_4_qs; + logic [6:0] wkup_detector_padsel_4_wd; + logic wkup_detector_padsel_5_we; + logic [6:0] wkup_detector_padsel_5_qs; + logic [6:0] wkup_detector_padsel_5_wd; + logic wkup_detector_padsel_6_we; + logic [6:0] wkup_detector_padsel_6_qs; + logic [6:0] wkup_detector_padsel_6_wd; + logic wkup_detector_padsel_7_we; + logic [6:0] wkup_detector_padsel_7_qs; + logic [6:0] wkup_detector_padsel_7_wd; + logic wkup_cause_we; + logic [7:0] wkup_cause_qs; + logic wkup_cause_busy; + // Define register CDC handling. + // CDC handling is done on a per-reg instead of per-field boundary. + + logic aon_wkup_detector_en_0_qs_int; + logic [0:0] aon_wkup_detector_en_0_qs; + logic [0:0] aon_wkup_detector_en_0_wdata; + logic aon_wkup_detector_en_0_we; + logic unused_aon_wkup_detector_en_0_wdata; + logic aon_wkup_detector_en_0_regwen; + + always_comb begin + aon_wkup_detector_en_0_qs = 1'h0; + aon_wkup_detector_en_0_qs = aon_wkup_detector_en_0_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_0_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_0_qs), + .src_we_i (wkup_detector_en_0_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_0_busy), + .src_qs_o (wkup_detector_en_0_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_0_qs), + .dst_we_o (aon_wkup_detector_en_0_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_0_regwen), + .dst_wd_o (aon_wkup_detector_en_0_wdata) + ); + assign unused_aon_wkup_detector_en_0_wdata = + ^aon_wkup_detector_en_0_wdata; + + logic aon_wkup_detector_en_1_qs_int; + logic [0:0] aon_wkup_detector_en_1_qs; + logic [0:0] aon_wkup_detector_en_1_wdata; + logic aon_wkup_detector_en_1_we; + logic unused_aon_wkup_detector_en_1_wdata; + logic aon_wkup_detector_en_1_regwen; + + always_comb begin + aon_wkup_detector_en_1_qs = 1'h0; + aon_wkup_detector_en_1_qs = aon_wkup_detector_en_1_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_1_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_1_qs), + .src_we_i (wkup_detector_en_1_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_1_busy), + .src_qs_o (wkup_detector_en_1_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_1_qs), + .dst_we_o (aon_wkup_detector_en_1_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_1_regwen), + .dst_wd_o (aon_wkup_detector_en_1_wdata) + ); + assign unused_aon_wkup_detector_en_1_wdata = + ^aon_wkup_detector_en_1_wdata; + + logic aon_wkup_detector_en_2_qs_int; + logic [0:0] aon_wkup_detector_en_2_qs; + logic [0:0] aon_wkup_detector_en_2_wdata; + logic aon_wkup_detector_en_2_we; + logic unused_aon_wkup_detector_en_2_wdata; + logic aon_wkup_detector_en_2_regwen; + + always_comb begin + aon_wkup_detector_en_2_qs = 1'h0; + aon_wkup_detector_en_2_qs = aon_wkup_detector_en_2_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_2_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_2_qs), + .src_we_i (wkup_detector_en_2_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_2_busy), + .src_qs_o (wkup_detector_en_2_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_2_qs), + .dst_we_o (aon_wkup_detector_en_2_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_2_regwen), + .dst_wd_o (aon_wkup_detector_en_2_wdata) + ); + assign unused_aon_wkup_detector_en_2_wdata = + ^aon_wkup_detector_en_2_wdata; + + logic aon_wkup_detector_en_3_qs_int; + logic [0:0] aon_wkup_detector_en_3_qs; + logic [0:0] aon_wkup_detector_en_3_wdata; + logic aon_wkup_detector_en_3_we; + logic unused_aon_wkup_detector_en_3_wdata; + logic aon_wkup_detector_en_3_regwen; + + always_comb begin + aon_wkup_detector_en_3_qs = 1'h0; + aon_wkup_detector_en_3_qs = aon_wkup_detector_en_3_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_3_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_3_qs), + .src_we_i (wkup_detector_en_3_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_3_busy), + .src_qs_o (wkup_detector_en_3_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_3_qs), + .dst_we_o (aon_wkup_detector_en_3_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_3_regwen), + .dst_wd_o (aon_wkup_detector_en_3_wdata) + ); + assign unused_aon_wkup_detector_en_3_wdata = + ^aon_wkup_detector_en_3_wdata; + + logic aon_wkup_detector_en_4_qs_int; + logic [0:0] aon_wkup_detector_en_4_qs; + logic [0:0] aon_wkup_detector_en_4_wdata; + logic aon_wkup_detector_en_4_we; + logic unused_aon_wkup_detector_en_4_wdata; + logic aon_wkup_detector_en_4_regwen; + + always_comb begin + aon_wkup_detector_en_4_qs = 1'h0; + aon_wkup_detector_en_4_qs = aon_wkup_detector_en_4_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_4_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_4_qs), + .src_we_i (wkup_detector_en_4_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_4_busy), + .src_qs_o (wkup_detector_en_4_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_4_qs), + .dst_we_o (aon_wkup_detector_en_4_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_4_regwen), + .dst_wd_o (aon_wkup_detector_en_4_wdata) + ); + assign unused_aon_wkup_detector_en_4_wdata = + ^aon_wkup_detector_en_4_wdata; + + logic aon_wkup_detector_en_5_qs_int; + logic [0:0] aon_wkup_detector_en_5_qs; + logic [0:0] aon_wkup_detector_en_5_wdata; + logic aon_wkup_detector_en_5_we; + logic unused_aon_wkup_detector_en_5_wdata; + logic aon_wkup_detector_en_5_regwen; + + always_comb begin + aon_wkup_detector_en_5_qs = 1'h0; + aon_wkup_detector_en_5_qs = aon_wkup_detector_en_5_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_5_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_5_qs), + .src_we_i (wkup_detector_en_5_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_5_busy), + .src_qs_o (wkup_detector_en_5_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_5_qs), + .dst_we_o (aon_wkup_detector_en_5_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_5_regwen), + .dst_wd_o (aon_wkup_detector_en_5_wdata) + ); + assign unused_aon_wkup_detector_en_5_wdata = + ^aon_wkup_detector_en_5_wdata; + + logic aon_wkup_detector_en_6_qs_int; + logic [0:0] aon_wkup_detector_en_6_qs; + logic [0:0] aon_wkup_detector_en_6_wdata; + logic aon_wkup_detector_en_6_we; + logic unused_aon_wkup_detector_en_6_wdata; + logic aon_wkup_detector_en_6_regwen; + + always_comb begin + aon_wkup_detector_en_6_qs = 1'h0; + aon_wkup_detector_en_6_qs = aon_wkup_detector_en_6_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_6_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_6_qs), + .src_we_i (wkup_detector_en_6_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_6_busy), + .src_qs_o (wkup_detector_en_6_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_6_qs), + .dst_we_o (aon_wkup_detector_en_6_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_6_regwen), + .dst_wd_o (aon_wkup_detector_en_6_wdata) + ); + assign unused_aon_wkup_detector_en_6_wdata = + ^aon_wkup_detector_en_6_wdata; + + logic aon_wkup_detector_en_7_qs_int; + logic [0:0] aon_wkup_detector_en_7_qs; + logic [0:0] aon_wkup_detector_en_7_wdata; + logic aon_wkup_detector_en_7_we; + logic unused_aon_wkup_detector_en_7_wdata; + logic aon_wkup_detector_en_7_regwen; + + always_comb begin + aon_wkup_detector_en_7_qs = 1'h0; + aon_wkup_detector_en_7_qs = aon_wkup_detector_en_7_qs_int; + end + + prim_reg_cdc #( + .DataWidth(1), + .ResetVal(1'h0), + .BitMask(1'h1), + .DstWrReq(0) + ) u_wkup_detector_en_7_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_7_qs), + .src_we_i (wkup_detector_en_7_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[0:0]), + .src_busy_o (wkup_detector_en_7_busy), + .src_qs_o (wkup_detector_en_7_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_en_7_qs), + .dst_we_o (aon_wkup_detector_en_7_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_en_7_regwen), + .dst_wd_o (aon_wkup_detector_en_7_wdata) + ); + assign unused_aon_wkup_detector_en_7_wdata = + ^aon_wkup_detector_en_7_wdata; + + logic [2:0] aon_wkup_detector_0_mode_0_qs_int; + logic aon_wkup_detector_0_filter_0_qs_int; + logic aon_wkup_detector_0_miodio_0_qs_int; + logic [4:0] aon_wkup_detector_0_qs; + logic [4:0] aon_wkup_detector_0_wdata; + logic aon_wkup_detector_0_we; + logic unused_aon_wkup_detector_0_wdata; + logic aon_wkup_detector_0_regwen; + + always_comb begin + aon_wkup_detector_0_qs = 5'h0; + aon_wkup_detector_0_qs[2:0] = aon_wkup_detector_0_mode_0_qs_int; + aon_wkup_detector_0_qs[3] = aon_wkup_detector_0_filter_0_qs_int; + aon_wkup_detector_0_qs[4] = aon_wkup_detector_0_miodio_0_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_0_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_0_qs), + .src_we_i (wkup_detector_0_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_0_busy), + .src_qs_o (wkup_detector_0_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_0_qs), + .dst_we_o (aon_wkup_detector_0_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_0_regwen), + .dst_wd_o (aon_wkup_detector_0_wdata) + ); + assign unused_aon_wkup_detector_0_wdata = + ^aon_wkup_detector_0_wdata; + + logic [2:0] aon_wkup_detector_1_mode_1_qs_int; + logic aon_wkup_detector_1_filter_1_qs_int; + logic aon_wkup_detector_1_miodio_1_qs_int; + logic [4:0] aon_wkup_detector_1_qs; + logic [4:0] aon_wkup_detector_1_wdata; + logic aon_wkup_detector_1_we; + logic unused_aon_wkup_detector_1_wdata; + logic aon_wkup_detector_1_regwen; + + always_comb begin + aon_wkup_detector_1_qs = 5'h0; + aon_wkup_detector_1_qs[2:0] = aon_wkup_detector_1_mode_1_qs_int; + aon_wkup_detector_1_qs[3] = aon_wkup_detector_1_filter_1_qs_int; + aon_wkup_detector_1_qs[4] = aon_wkup_detector_1_miodio_1_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_1_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_1_qs), + .src_we_i (wkup_detector_1_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_1_busy), + .src_qs_o (wkup_detector_1_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_1_qs), + .dst_we_o (aon_wkup_detector_1_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_1_regwen), + .dst_wd_o (aon_wkup_detector_1_wdata) + ); + assign unused_aon_wkup_detector_1_wdata = + ^aon_wkup_detector_1_wdata; + + logic [2:0] aon_wkup_detector_2_mode_2_qs_int; + logic aon_wkup_detector_2_filter_2_qs_int; + logic aon_wkup_detector_2_miodio_2_qs_int; + logic [4:0] aon_wkup_detector_2_qs; + logic [4:0] aon_wkup_detector_2_wdata; + logic aon_wkup_detector_2_we; + logic unused_aon_wkup_detector_2_wdata; + logic aon_wkup_detector_2_regwen; + + always_comb begin + aon_wkup_detector_2_qs = 5'h0; + aon_wkup_detector_2_qs[2:0] = aon_wkup_detector_2_mode_2_qs_int; + aon_wkup_detector_2_qs[3] = aon_wkup_detector_2_filter_2_qs_int; + aon_wkup_detector_2_qs[4] = aon_wkup_detector_2_miodio_2_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_2_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_2_qs), + .src_we_i (wkup_detector_2_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_2_busy), + .src_qs_o (wkup_detector_2_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_2_qs), + .dst_we_o (aon_wkup_detector_2_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_2_regwen), + .dst_wd_o (aon_wkup_detector_2_wdata) + ); + assign unused_aon_wkup_detector_2_wdata = + ^aon_wkup_detector_2_wdata; + + logic [2:0] aon_wkup_detector_3_mode_3_qs_int; + logic aon_wkup_detector_3_filter_3_qs_int; + logic aon_wkup_detector_3_miodio_3_qs_int; + logic [4:0] aon_wkup_detector_3_qs; + logic [4:0] aon_wkup_detector_3_wdata; + logic aon_wkup_detector_3_we; + logic unused_aon_wkup_detector_3_wdata; + logic aon_wkup_detector_3_regwen; + + always_comb begin + aon_wkup_detector_3_qs = 5'h0; + aon_wkup_detector_3_qs[2:0] = aon_wkup_detector_3_mode_3_qs_int; + aon_wkup_detector_3_qs[3] = aon_wkup_detector_3_filter_3_qs_int; + aon_wkup_detector_3_qs[4] = aon_wkup_detector_3_miodio_3_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_3_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_3_qs), + .src_we_i (wkup_detector_3_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_3_busy), + .src_qs_o (wkup_detector_3_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_3_qs), + .dst_we_o (aon_wkup_detector_3_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_3_regwen), + .dst_wd_o (aon_wkup_detector_3_wdata) + ); + assign unused_aon_wkup_detector_3_wdata = + ^aon_wkup_detector_3_wdata; + + logic [2:0] aon_wkup_detector_4_mode_4_qs_int; + logic aon_wkup_detector_4_filter_4_qs_int; + logic aon_wkup_detector_4_miodio_4_qs_int; + logic [4:0] aon_wkup_detector_4_qs; + logic [4:0] aon_wkup_detector_4_wdata; + logic aon_wkup_detector_4_we; + logic unused_aon_wkup_detector_4_wdata; + logic aon_wkup_detector_4_regwen; + + always_comb begin + aon_wkup_detector_4_qs = 5'h0; + aon_wkup_detector_4_qs[2:0] = aon_wkup_detector_4_mode_4_qs_int; + aon_wkup_detector_4_qs[3] = aon_wkup_detector_4_filter_4_qs_int; + aon_wkup_detector_4_qs[4] = aon_wkup_detector_4_miodio_4_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_4_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_4_qs), + .src_we_i (wkup_detector_4_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_4_busy), + .src_qs_o (wkup_detector_4_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_4_qs), + .dst_we_o (aon_wkup_detector_4_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_4_regwen), + .dst_wd_o (aon_wkup_detector_4_wdata) + ); + assign unused_aon_wkup_detector_4_wdata = + ^aon_wkup_detector_4_wdata; + + logic [2:0] aon_wkup_detector_5_mode_5_qs_int; + logic aon_wkup_detector_5_filter_5_qs_int; + logic aon_wkup_detector_5_miodio_5_qs_int; + logic [4:0] aon_wkup_detector_5_qs; + logic [4:0] aon_wkup_detector_5_wdata; + logic aon_wkup_detector_5_we; + logic unused_aon_wkup_detector_5_wdata; + logic aon_wkup_detector_5_regwen; + + always_comb begin + aon_wkup_detector_5_qs = 5'h0; + aon_wkup_detector_5_qs[2:0] = aon_wkup_detector_5_mode_5_qs_int; + aon_wkup_detector_5_qs[3] = aon_wkup_detector_5_filter_5_qs_int; + aon_wkup_detector_5_qs[4] = aon_wkup_detector_5_miodio_5_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_5_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_5_qs), + .src_we_i (wkup_detector_5_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_5_busy), + .src_qs_o (wkup_detector_5_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_5_qs), + .dst_we_o (aon_wkup_detector_5_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_5_regwen), + .dst_wd_o (aon_wkup_detector_5_wdata) + ); + assign unused_aon_wkup_detector_5_wdata = + ^aon_wkup_detector_5_wdata; + + logic [2:0] aon_wkup_detector_6_mode_6_qs_int; + logic aon_wkup_detector_6_filter_6_qs_int; + logic aon_wkup_detector_6_miodio_6_qs_int; + logic [4:0] aon_wkup_detector_6_qs; + logic [4:0] aon_wkup_detector_6_wdata; + logic aon_wkup_detector_6_we; + logic unused_aon_wkup_detector_6_wdata; + logic aon_wkup_detector_6_regwen; + + always_comb begin + aon_wkup_detector_6_qs = 5'h0; + aon_wkup_detector_6_qs[2:0] = aon_wkup_detector_6_mode_6_qs_int; + aon_wkup_detector_6_qs[3] = aon_wkup_detector_6_filter_6_qs_int; + aon_wkup_detector_6_qs[4] = aon_wkup_detector_6_miodio_6_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_6_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_6_qs), + .src_we_i (wkup_detector_6_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_6_busy), + .src_qs_o (wkup_detector_6_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_6_qs), + .dst_we_o (aon_wkup_detector_6_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_6_regwen), + .dst_wd_o (aon_wkup_detector_6_wdata) + ); + assign unused_aon_wkup_detector_6_wdata = + ^aon_wkup_detector_6_wdata; + + logic [2:0] aon_wkup_detector_7_mode_7_qs_int; + logic aon_wkup_detector_7_filter_7_qs_int; + logic aon_wkup_detector_7_miodio_7_qs_int; + logic [4:0] aon_wkup_detector_7_qs; + logic [4:0] aon_wkup_detector_7_wdata; + logic aon_wkup_detector_7_we; + logic unused_aon_wkup_detector_7_wdata; + logic aon_wkup_detector_7_regwen; + + always_comb begin + aon_wkup_detector_7_qs = 5'h0; + aon_wkup_detector_7_qs[2:0] = aon_wkup_detector_7_mode_7_qs_int; + aon_wkup_detector_7_qs[3] = aon_wkup_detector_7_filter_7_qs_int; + aon_wkup_detector_7_qs[4] = aon_wkup_detector_7_miodio_7_qs_int; + end + + prim_reg_cdc #( + .DataWidth(5), + .ResetVal(5'h0), + .BitMask(5'h1f), + .DstWrReq(0) + ) u_wkup_detector_7_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_7_qs), + .src_we_i (wkup_detector_7_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[4:0]), + .src_busy_o (wkup_detector_7_busy), + .src_qs_o (wkup_detector_7_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_7_qs), + .dst_we_o (aon_wkup_detector_7_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_7_regwen), + .dst_wd_o (aon_wkup_detector_7_wdata) + ); + assign unused_aon_wkup_detector_7_wdata = + ^aon_wkup_detector_7_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_0_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_0_qs; + logic [7:0] aon_wkup_detector_cnt_th_0_wdata; + logic aon_wkup_detector_cnt_th_0_we; + logic unused_aon_wkup_detector_cnt_th_0_wdata; + logic aon_wkup_detector_cnt_th_0_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_0_qs = 8'h0; + aon_wkup_detector_cnt_th_0_qs = aon_wkup_detector_cnt_th_0_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_0_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_0_qs), + .src_we_i (wkup_detector_cnt_th_0_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_0_busy), + .src_qs_o (wkup_detector_cnt_th_0_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_0_qs), + .dst_we_o (aon_wkup_detector_cnt_th_0_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_0_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_0_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_0_wdata = + ^aon_wkup_detector_cnt_th_0_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_1_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_1_qs; + logic [7:0] aon_wkup_detector_cnt_th_1_wdata; + logic aon_wkup_detector_cnt_th_1_we; + logic unused_aon_wkup_detector_cnt_th_1_wdata; + logic aon_wkup_detector_cnt_th_1_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_1_qs = 8'h0; + aon_wkup_detector_cnt_th_1_qs = aon_wkup_detector_cnt_th_1_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_1_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_1_qs), + .src_we_i (wkup_detector_cnt_th_1_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_1_busy), + .src_qs_o (wkup_detector_cnt_th_1_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_1_qs), + .dst_we_o (aon_wkup_detector_cnt_th_1_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_1_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_1_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_1_wdata = + ^aon_wkup_detector_cnt_th_1_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_2_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_2_qs; + logic [7:0] aon_wkup_detector_cnt_th_2_wdata; + logic aon_wkup_detector_cnt_th_2_we; + logic unused_aon_wkup_detector_cnt_th_2_wdata; + logic aon_wkup_detector_cnt_th_2_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_2_qs = 8'h0; + aon_wkup_detector_cnt_th_2_qs = aon_wkup_detector_cnt_th_2_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_2_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_2_qs), + .src_we_i (wkup_detector_cnt_th_2_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_2_busy), + .src_qs_o (wkup_detector_cnt_th_2_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_2_qs), + .dst_we_o (aon_wkup_detector_cnt_th_2_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_2_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_2_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_2_wdata = + ^aon_wkup_detector_cnt_th_2_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_3_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_3_qs; + logic [7:0] aon_wkup_detector_cnt_th_3_wdata; + logic aon_wkup_detector_cnt_th_3_we; + logic unused_aon_wkup_detector_cnt_th_3_wdata; + logic aon_wkup_detector_cnt_th_3_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_3_qs = 8'h0; + aon_wkup_detector_cnt_th_3_qs = aon_wkup_detector_cnt_th_3_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_3_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_3_qs), + .src_we_i (wkup_detector_cnt_th_3_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_3_busy), + .src_qs_o (wkup_detector_cnt_th_3_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_3_qs), + .dst_we_o (aon_wkup_detector_cnt_th_3_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_3_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_3_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_3_wdata = + ^aon_wkup_detector_cnt_th_3_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_4_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_4_qs; + logic [7:0] aon_wkup_detector_cnt_th_4_wdata; + logic aon_wkup_detector_cnt_th_4_we; + logic unused_aon_wkup_detector_cnt_th_4_wdata; + logic aon_wkup_detector_cnt_th_4_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_4_qs = 8'h0; + aon_wkup_detector_cnt_th_4_qs = aon_wkup_detector_cnt_th_4_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_4_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_4_qs), + .src_we_i (wkup_detector_cnt_th_4_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_4_busy), + .src_qs_o (wkup_detector_cnt_th_4_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_4_qs), + .dst_we_o (aon_wkup_detector_cnt_th_4_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_4_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_4_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_4_wdata = + ^aon_wkup_detector_cnt_th_4_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_5_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_5_qs; + logic [7:0] aon_wkup_detector_cnt_th_5_wdata; + logic aon_wkup_detector_cnt_th_5_we; + logic unused_aon_wkup_detector_cnt_th_5_wdata; + logic aon_wkup_detector_cnt_th_5_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_5_qs = 8'h0; + aon_wkup_detector_cnt_th_5_qs = aon_wkup_detector_cnt_th_5_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_5_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_5_qs), + .src_we_i (wkup_detector_cnt_th_5_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_5_busy), + .src_qs_o (wkup_detector_cnt_th_5_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_5_qs), + .dst_we_o (aon_wkup_detector_cnt_th_5_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_5_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_5_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_5_wdata = + ^aon_wkup_detector_cnt_th_5_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_6_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_6_qs; + logic [7:0] aon_wkup_detector_cnt_th_6_wdata; + logic aon_wkup_detector_cnt_th_6_we; + logic unused_aon_wkup_detector_cnt_th_6_wdata; + logic aon_wkup_detector_cnt_th_6_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_6_qs = 8'h0; + aon_wkup_detector_cnt_th_6_qs = aon_wkup_detector_cnt_th_6_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_6_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_6_qs), + .src_we_i (wkup_detector_cnt_th_6_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_6_busy), + .src_qs_o (wkup_detector_cnt_th_6_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_6_qs), + .dst_we_o (aon_wkup_detector_cnt_th_6_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_6_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_6_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_6_wdata = + ^aon_wkup_detector_cnt_th_6_wdata; + + logic [7:0] aon_wkup_detector_cnt_th_7_qs_int; + logic [7:0] aon_wkup_detector_cnt_th_7_qs; + logic [7:0] aon_wkup_detector_cnt_th_7_wdata; + logic aon_wkup_detector_cnt_th_7_we; + logic unused_aon_wkup_detector_cnt_th_7_wdata; + logic aon_wkup_detector_cnt_th_7_regwen; + + always_comb begin + aon_wkup_detector_cnt_th_7_qs = 8'h0; + aon_wkup_detector_cnt_th_7_qs = aon_wkup_detector_cnt_th_7_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(0) + ) u_wkup_detector_cnt_th_7_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i (wkup_detector_regwen_7_qs), + .src_we_i (wkup_detector_cnt_th_7_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_detector_cnt_th_7_busy), + .src_qs_o (wkup_detector_cnt_th_7_qs), // for software read back + .dst_update_i ('0), + .dst_ds_i ('0), + .dst_qs_i (aon_wkup_detector_cnt_th_7_qs), + .dst_we_o (aon_wkup_detector_cnt_th_7_we), + .dst_re_o (), + .dst_regwen_o (aon_wkup_detector_cnt_th_7_regwen), + .dst_wd_o (aon_wkup_detector_cnt_th_7_wdata) + ); + assign unused_aon_wkup_detector_cnt_th_7_wdata = + ^aon_wkup_detector_cnt_th_7_wdata; + + logic aon_wkup_cause_cause_0_ds_int; + logic aon_wkup_cause_cause_0_qs_int; + logic aon_wkup_cause_cause_1_ds_int; + logic aon_wkup_cause_cause_1_qs_int; + logic aon_wkup_cause_cause_2_ds_int; + logic aon_wkup_cause_cause_2_qs_int; + logic aon_wkup_cause_cause_3_ds_int; + logic aon_wkup_cause_cause_3_qs_int; + logic aon_wkup_cause_cause_4_ds_int; + logic aon_wkup_cause_cause_4_qs_int; + logic aon_wkup_cause_cause_5_ds_int; + logic aon_wkup_cause_cause_5_qs_int; + logic aon_wkup_cause_cause_6_ds_int; + logic aon_wkup_cause_cause_6_qs_int; + logic aon_wkup_cause_cause_7_ds_int; + logic aon_wkup_cause_cause_7_qs_int; + logic [7:0] aon_wkup_cause_ds; + logic aon_wkup_cause_qe; + logic [7:0] aon_wkup_cause_qs; + logic [7:0] aon_wkup_cause_wdata; + logic aon_wkup_cause_we; + logic unused_aon_wkup_cause_wdata; + + always_comb begin + aon_wkup_cause_qs = 8'h0; + aon_wkup_cause_ds = 8'h0; + aon_wkup_cause_ds[0] = aon_wkup_cause_cause_0_ds_int; + aon_wkup_cause_qs[0] = aon_wkup_cause_cause_0_qs_int; + aon_wkup_cause_ds[1] = aon_wkup_cause_cause_1_ds_int; + aon_wkup_cause_qs[1] = aon_wkup_cause_cause_1_qs_int; + aon_wkup_cause_ds[2] = aon_wkup_cause_cause_2_ds_int; + aon_wkup_cause_qs[2] = aon_wkup_cause_cause_2_qs_int; + aon_wkup_cause_ds[3] = aon_wkup_cause_cause_3_ds_int; + aon_wkup_cause_qs[3] = aon_wkup_cause_cause_3_qs_int; + aon_wkup_cause_ds[4] = aon_wkup_cause_cause_4_ds_int; + aon_wkup_cause_qs[4] = aon_wkup_cause_cause_4_qs_int; + aon_wkup_cause_ds[5] = aon_wkup_cause_cause_5_ds_int; + aon_wkup_cause_qs[5] = aon_wkup_cause_cause_5_qs_int; + aon_wkup_cause_ds[6] = aon_wkup_cause_cause_6_ds_int; + aon_wkup_cause_qs[6] = aon_wkup_cause_cause_6_qs_int; + aon_wkup_cause_ds[7] = aon_wkup_cause_cause_7_ds_int; + aon_wkup_cause_qs[7] = aon_wkup_cause_cause_7_qs_int; + end + + prim_reg_cdc #( + .DataWidth(8), + .ResetVal(8'h0), + .BitMask(8'hff), + .DstWrReq(1) + ) u_wkup_cause_cdc ( + .clk_src_i (clk_i), + .rst_src_ni (rst_ni), + .clk_dst_i (clk_aon_i), + .rst_dst_ni (rst_aon_ni), + .src_regwen_i ('0), + .src_we_i (wkup_cause_we), + .src_re_i ('0), + .src_wd_i (reg_wdata[7:0]), + .src_busy_o (wkup_cause_busy), + .src_qs_o (wkup_cause_qs), // for software read back + .dst_update_i (aon_wkup_cause_qe), + .dst_ds_i (aon_wkup_cause_ds), + .dst_qs_i (aon_wkup_cause_qs), + .dst_we_o (aon_wkup_cause_we), + .dst_re_o (), + .dst_regwen_o (), + .dst_wd_o (aon_wkup_cause_wdata) + ); + assign unused_aon_wkup_cause_wdata = + ^aon_wkup_cause_wdata; + + // Register instances + // R[alert_test]: V(True) + logic alert_test_qe; + logic [0:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.qe = alert_test_qe; + + + // Subregister 0 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_0_we), + .wd (mio_periph_insel_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_0_qs) + ); + + + // Subregister 1 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_1_we), + .wd (mio_periph_insel_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_1_qs) + ); + + + // Subregister 2 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_2_we), + .wd (mio_periph_insel_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_2_qs) + ); + + + // Subregister 3 of Multireg mio_periph_insel_regwen + // R[mio_periph_insel_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_periph_insel_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_regwen_3_we), + .wd (mio_periph_insel_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_regwen_3_qs) + ); + + + // Subregister 0 of Multireg mio_periph_insel + // R[mio_periph_insel_0]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_0_gated_we; + assign mio_periph_insel_0_gated_we = mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_0_gated_we), + .wd (mio_periph_insel_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[0].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_0_qs) + ); + + + // Subregister 1 of Multireg mio_periph_insel + // R[mio_periph_insel_1]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_1_gated_we; + assign mio_periph_insel_1_gated_we = mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_1_gated_we), + .wd (mio_periph_insel_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[1].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_1_qs) + ); + + + // Subregister 2 of Multireg mio_periph_insel + // R[mio_periph_insel_2]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_2_gated_we; + assign mio_periph_insel_2_gated_we = mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_2_gated_we), + .wd (mio_periph_insel_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[2].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_2_qs) + ); + + + // Subregister 3 of Multireg mio_periph_insel + // R[mio_periph_insel_3]: V(False) + // Create REGWEN-gated WE signal + logic mio_periph_insel_3_gated_we; + assign mio_periph_insel_3_gated_we = mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs; + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_mio_periph_insel_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_periph_insel_3_gated_we), + .wd (mio_periph_insel_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_periph_insel[3].q), + .ds (), + + // to register interface (read) + .qs (mio_periph_insel_3_qs) + ); + + + // Subregister 0 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_0_we), + .wd (mio_outsel_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_0_qs) + ); + + + // Subregister 1 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_1_we), + .wd (mio_outsel_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_1_qs) + ); + + + // Subregister 2 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_2_we), + .wd (mio_outsel_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_2_qs) + ); + + + // Subregister 3 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_3_we), + .wd (mio_outsel_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_3_qs) + ); + + + // Subregister 4 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_4_we), + .wd (mio_outsel_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_4_qs) + ); + + + // Subregister 5 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_5_we), + .wd (mio_outsel_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_5_qs) + ); + + + // Subregister 6 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_6_we), + .wd (mio_outsel_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_6_qs) + ); + + + // Subregister 7 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_7_we), + .wd (mio_outsel_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_7_qs) + ); + + + // Subregister 8 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_8_we), + .wd (mio_outsel_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_8_qs) + ); + + + // Subregister 9 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_9_we), + .wd (mio_outsel_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_9_qs) + ); + + + // Subregister 10 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_10_we), + .wd (mio_outsel_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_10_qs) + ); + + + // Subregister 11 of Multireg mio_outsel_regwen + // R[mio_outsel_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_outsel_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_regwen_11_we), + .wd (mio_outsel_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_outsel_regwen_11_qs) + ); + + + // Subregister 0 of Multireg mio_outsel + // R[mio_outsel_0]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_0_gated_we; + assign mio_outsel_0_gated_we = mio_outsel_0_we & mio_outsel_regwen_0_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_0_gated_we), + .wd (mio_outsel_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[0].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_0_qs) + ); + + + // Subregister 1 of Multireg mio_outsel + // R[mio_outsel_1]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_1_gated_we; + assign mio_outsel_1_gated_we = mio_outsel_1_we & mio_outsel_regwen_1_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_1_gated_we), + .wd (mio_outsel_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[1].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_1_qs) + ); + + + // Subregister 2 of Multireg mio_outsel + // R[mio_outsel_2]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_2_gated_we; + assign mio_outsel_2_gated_we = mio_outsel_2_we & mio_outsel_regwen_2_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_2_gated_we), + .wd (mio_outsel_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[2].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_2_qs) + ); + + + // Subregister 3 of Multireg mio_outsel + // R[mio_outsel_3]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_3_gated_we; + assign mio_outsel_3_gated_we = mio_outsel_3_we & mio_outsel_regwen_3_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_3_gated_we), + .wd (mio_outsel_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[3].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_3_qs) + ); + + + // Subregister 4 of Multireg mio_outsel + // R[mio_outsel_4]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_4_gated_we; + assign mio_outsel_4_gated_we = mio_outsel_4_we & mio_outsel_regwen_4_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_4_gated_we), + .wd (mio_outsel_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[4].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_4_qs) + ); + + + // Subregister 5 of Multireg mio_outsel + // R[mio_outsel_5]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_5_gated_we; + assign mio_outsel_5_gated_we = mio_outsel_5_we & mio_outsel_regwen_5_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_5_gated_we), + .wd (mio_outsel_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[5].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_5_qs) + ); + + + // Subregister 6 of Multireg mio_outsel + // R[mio_outsel_6]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_6_gated_we; + assign mio_outsel_6_gated_we = mio_outsel_6_we & mio_outsel_regwen_6_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_6_gated_we), + .wd (mio_outsel_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[6].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_6_qs) + ); + + + // Subregister 7 of Multireg mio_outsel + // R[mio_outsel_7]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_7_gated_we; + assign mio_outsel_7_gated_we = mio_outsel_7_we & mio_outsel_regwen_7_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_7_gated_we), + .wd (mio_outsel_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[7].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_7_qs) + ); + + + // Subregister 8 of Multireg mio_outsel + // R[mio_outsel_8]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_8_gated_we; + assign mio_outsel_8_gated_we = mio_outsel_8_we & mio_outsel_regwen_8_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_8_gated_we), + .wd (mio_outsel_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[8].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_8_qs) + ); + + + // Subregister 9 of Multireg mio_outsel + // R[mio_outsel_9]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_9_gated_we; + assign mio_outsel_9_gated_we = mio_outsel_9_we & mio_outsel_regwen_9_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_9_gated_we), + .wd (mio_outsel_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[9].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_9_qs) + ); + + + // Subregister 10 of Multireg mio_outsel + // R[mio_outsel_10]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_10_gated_we; + assign mio_outsel_10_gated_we = mio_outsel_10_we & mio_outsel_regwen_10_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_10_gated_we), + .wd (mio_outsel_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[10].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_10_qs) + ); + + + // Subregister 11 of Multireg mio_outsel + // R[mio_outsel_11]: V(False) + // Create REGWEN-gated WE signal + logic mio_outsel_11_gated_we; + assign mio_outsel_11_gated_we = mio_outsel_11_we & mio_outsel_regwen_11_qs; + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h2), + .Mubi (1'b0) + ) u_mio_outsel_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_outsel_11_gated_we), + .wd (mio_outsel_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_outsel[11].q), + .ds (), + + // to register interface (read) + .qs (mio_outsel_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_0_we), + .wd (mio_pad_attr_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_0_qs) + ); + + + // Subregister 1 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_1_we), + .wd (mio_pad_attr_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_1_qs) + ); + + + // Subregister 2 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_2_we), + .wd (mio_pad_attr_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_2_qs) + ); + + + // Subregister 3 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_3_we), + .wd (mio_pad_attr_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_3_qs) + ); + + + // Subregister 4 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_4_we), + .wd (mio_pad_attr_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_4_qs) + ); + + + // Subregister 5 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_5_we), + .wd (mio_pad_attr_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_5_qs) + ); + + + // Subregister 6 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_6_we), + .wd (mio_pad_attr_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_6_qs) + ); + + + // Subregister 7 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_7_we), + .wd (mio_pad_attr_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_7_qs) + ); + + + // Subregister 8 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_8_we), + .wd (mio_pad_attr_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_8_qs) + ); + + + // Subregister 9 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_9_we), + .wd (mio_pad_attr_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_9_qs) + ); + + + // Subregister 10 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_10_we), + .wd (mio_pad_attr_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_10_qs) + ); + + + // Subregister 11 of Multireg mio_pad_attr_regwen + // R[mio_pad_attr_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_attr_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_attr_regwen_11_we), + .wd (mio_pad_attr_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_attr_regwen_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_attr + // R[mio_pad_attr_0]: V(True) + logic mio_pad_attr_0_qe; + logic [9:0] mio_pad_attr_0_flds_we; + assign mio_pad_attr_0_qe = &mio_pad_attr_0_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_0_gated_we; + assign mio_pad_attr_0_gated_we = mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs; + // F[invert_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_invert_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_invert_0_wd), + .d (hw2reg.mio_pad_attr[0].invert.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[0]), + .q (reg2hw.mio_pad_attr[0].invert.q), + .ds (), + .qs (mio_pad_attr_0_invert_0_qs) + ); + assign reg2hw.mio_pad_attr[0].invert.qe = mio_pad_attr_0_qe; + + // F[virtual_od_en_0]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_virtual_od_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_virtual_od_en_0_wd), + .d (hw2reg.mio_pad_attr[0].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[1]), + .q (reg2hw.mio_pad_attr[0].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_0_virtual_od_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].virtual_od_en.qe = mio_pad_attr_0_qe; + + // F[pull_en_0]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_pull_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_pull_en_0_wd), + .d (hw2reg.mio_pad_attr[0].pull_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[2]), + .q (reg2hw.mio_pad_attr[0].pull_en.q), + .ds (), + .qs (mio_pad_attr_0_pull_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].pull_en.qe = mio_pad_attr_0_qe; + + // F[pull_select_0]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_pull_select_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_pull_select_0_wd), + .d (hw2reg.mio_pad_attr[0].pull_select.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[3]), + .q (reg2hw.mio_pad_attr[0].pull_select.q), + .ds (), + .qs (mio_pad_attr_0_pull_select_0_qs) + ); + assign reg2hw.mio_pad_attr[0].pull_select.qe = mio_pad_attr_0_qe; + + // F[keeper_en_0]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_keeper_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_keeper_en_0_wd), + .d (hw2reg.mio_pad_attr[0].keeper_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[4]), + .q (reg2hw.mio_pad_attr[0].keeper_en.q), + .ds (), + .qs (mio_pad_attr_0_keeper_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].keeper_en.qe = mio_pad_attr_0_qe; + + // F[schmitt_en_0]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_schmitt_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_schmitt_en_0_wd), + .d (hw2reg.mio_pad_attr[0].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[5]), + .q (reg2hw.mio_pad_attr[0].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_0_schmitt_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].schmitt_en.qe = mio_pad_attr_0_qe; + + // F[od_en_0]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_od_en_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_od_en_0_wd), + .d (hw2reg.mio_pad_attr[0].od_en.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[6]), + .q (reg2hw.mio_pad_attr[0].od_en.q), + .ds (), + .qs (mio_pad_attr_0_od_en_0_qs) + ); + assign reg2hw.mio_pad_attr[0].od_en.qe = mio_pad_attr_0_qe; + + // F[input_disable_0]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_0_input_disable_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_input_disable_0_wd), + .d (hw2reg.mio_pad_attr[0].input_disable.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[7]), + .q (reg2hw.mio_pad_attr[0].input_disable.q), + .ds (), + .qs (mio_pad_attr_0_input_disable_0_qs) + ); + assign reg2hw.mio_pad_attr[0].input_disable.qe = mio_pad_attr_0_qe; + + // F[slew_rate_0]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_0_slew_rate_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_slew_rate_0_wd), + .d (hw2reg.mio_pad_attr[0].slew_rate.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[8]), + .q (reg2hw.mio_pad_attr[0].slew_rate.q), + .ds (), + .qs (mio_pad_attr_0_slew_rate_0_qs) + ); + assign reg2hw.mio_pad_attr[0].slew_rate.qe = mio_pad_attr_0_qe; + + // F[drive_strength_0]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_0_drive_strength_0 ( + .re (mio_pad_attr_0_re), + .we (mio_pad_attr_0_gated_we), + .wd (mio_pad_attr_0_drive_strength_0_wd), + .d (hw2reg.mio_pad_attr[0].drive_strength.d), + .qre (), + .qe (mio_pad_attr_0_flds_we[9]), + .q (reg2hw.mio_pad_attr[0].drive_strength.q), + .ds (), + .qs (mio_pad_attr_0_drive_strength_0_qs) + ); + assign reg2hw.mio_pad_attr[0].drive_strength.qe = mio_pad_attr_0_qe; + + + // Subregister 1 of Multireg mio_pad_attr + // R[mio_pad_attr_1]: V(True) + logic mio_pad_attr_1_qe; + logic [9:0] mio_pad_attr_1_flds_we; + assign mio_pad_attr_1_qe = &mio_pad_attr_1_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_1_gated_we; + assign mio_pad_attr_1_gated_we = mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs; + // F[invert_1]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_invert_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_invert_1_wd), + .d (hw2reg.mio_pad_attr[1].invert.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[0]), + .q (reg2hw.mio_pad_attr[1].invert.q), + .ds (), + .qs (mio_pad_attr_1_invert_1_qs) + ); + assign reg2hw.mio_pad_attr[1].invert.qe = mio_pad_attr_1_qe; + + // F[virtual_od_en_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_virtual_od_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_virtual_od_en_1_wd), + .d (hw2reg.mio_pad_attr[1].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[1]), + .q (reg2hw.mio_pad_attr[1].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_1_virtual_od_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].virtual_od_en.qe = mio_pad_attr_1_qe; + + // F[pull_en_1]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_pull_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_pull_en_1_wd), + .d (hw2reg.mio_pad_attr[1].pull_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[2]), + .q (reg2hw.mio_pad_attr[1].pull_en.q), + .ds (), + .qs (mio_pad_attr_1_pull_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].pull_en.qe = mio_pad_attr_1_qe; + + // F[pull_select_1]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_pull_select_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_pull_select_1_wd), + .d (hw2reg.mio_pad_attr[1].pull_select.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[3]), + .q (reg2hw.mio_pad_attr[1].pull_select.q), + .ds (), + .qs (mio_pad_attr_1_pull_select_1_qs) + ); + assign reg2hw.mio_pad_attr[1].pull_select.qe = mio_pad_attr_1_qe; + + // F[keeper_en_1]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_keeper_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_keeper_en_1_wd), + .d (hw2reg.mio_pad_attr[1].keeper_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[4]), + .q (reg2hw.mio_pad_attr[1].keeper_en.q), + .ds (), + .qs (mio_pad_attr_1_keeper_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].keeper_en.qe = mio_pad_attr_1_qe; + + // F[schmitt_en_1]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_schmitt_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_schmitt_en_1_wd), + .d (hw2reg.mio_pad_attr[1].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[5]), + .q (reg2hw.mio_pad_attr[1].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_1_schmitt_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].schmitt_en.qe = mio_pad_attr_1_qe; + + // F[od_en_1]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_od_en_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_od_en_1_wd), + .d (hw2reg.mio_pad_attr[1].od_en.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[6]), + .q (reg2hw.mio_pad_attr[1].od_en.q), + .ds (), + .qs (mio_pad_attr_1_od_en_1_qs) + ); + assign reg2hw.mio_pad_attr[1].od_en.qe = mio_pad_attr_1_qe; + + // F[input_disable_1]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_1_input_disable_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_input_disable_1_wd), + .d (hw2reg.mio_pad_attr[1].input_disable.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[7]), + .q (reg2hw.mio_pad_attr[1].input_disable.q), + .ds (), + .qs (mio_pad_attr_1_input_disable_1_qs) + ); + assign reg2hw.mio_pad_attr[1].input_disable.qe = mio_pad_attr_1_qe; + + // F[slew_rate_1]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_1_slew_rate_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_slew_rate_1_wd), + .d (hw2reg.mio_pad_attr[1].slew_rate.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[8]), + .q (reg2hw.mio_pad_attr[1].slew_rate.q), + .ds (), + .qs (mio_pad_attr_1_slew_rate_1_qs) + ); + assign reg2hw.mio_pad_attr[1].slew_rate.qe = mio_pad_attr_1_qe; + + // F[drive_strength_1]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_1_drive_strength_1 ( + .re (mio_pad_attr_1_re), + .we (mio_pad_attr_1_gated_we), + .wd (mio_pad_attr_1_drive_strength_1_wd), + .d (hw2reg.mio_pad_attr[1].drive_strength.d), + .qre (), + .qe (mio_pad_attr_1_flds_we[9]), + .q (reg2hw.mio_pad_attr[1].drive_strength.q), + .ds (), + .qs (mio_pad_attr_1_drive_strength_1_qs) + ); + assign reg2hw.mio_pad_attr[1].drive_strength.qe = mio_pad_attr_1_qe; + + + // Subregister 2 of Multireg mio_pad_attr + // R[mio_pad_attr_2]: V(True) + logic mio_pad_attr_2_qe; + logic [9:0] mio_pad_attr_2_flds_we; + assign mio_pad_attr_2_qe = &mio_pad_attr_2_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_2_gated_we; + assign mio_pad_attr_2_gated_we = mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs; + // F[invert_2]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_invert_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_invert_2_wd), + .d (hw2reg.mio_pad_attr[2].invert.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[0]), + .q (reg2hw.mio_pad_attr[2].invert.q), + .ds (), + .qs (mio_pad_attr_2_invert_2_qs) + ); + assign reg2hw.mio_pad_attr[2].invert.qe = mio_pad_attr_2_qe; + + // F[virtual_od_en_2]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_virtual_od_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_virtual_od_en_2_wd), + .d (hw2reg.mio_pad_attr[2].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[1]), + .q (reg2hw.mio_pad_attr[2].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_2_virtual_od_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].virtual_od_en.qe = mio_pad_attr_2_qe; + + // F[pull_en_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_pull_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_pull_en_2_wd), + .d (hw2reg.mio_pad_attr[2].pull_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[2]), + .q (reg2hw.mio_pad_attr[2].pull_en.q), + .ds (), + .qs (mio_pad_attr_2_pull_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].pull_en.qe = mio_pad_attr_2_qe; + + // F[pull_select_2]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_pull_select_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_pull_select_2_wd), + .d (hw2reg.mio_pad_attr[2].pull_select.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[3]), + .q (reg2hw.mio_pad_attr[2].pull_select.q), + .ds (), + .qs (mio_pad_attr_2_pull_select_2_qs) + ); + assign reg2hw.mio_pad_attr[2].pull_select.qe = mio_pad_attr_2_qe; + + // F[keeper_en_2]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_keeper_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_keeper_en_2_wd), + .d (hw2reg.mio_pad_attr[2].keeper_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[4]), + .q (reg2hw.mio_pad_attr[2].keeper_en.q), + .ds (), + .qs (mio_pad_attr_2_keeper_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].keeper_en.qe = mio_pad_attr_2_qe; + + // F[schmitt_en_2]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_schmitt_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_schmitt_en_2_wd), + .d (hw2reg.mio_pad_attr[2].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[5]), + .q (reg2hw.mio_pad_attr[2].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_2_schmitt_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].schmitt_en.qe = mio_pad_attr_2_qe; + + // F[od_en_2]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_od_en_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_od_en_2_wd), + .d (hw2reg.mio_pad_attr[2].od_en.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[6]), + .q (reg2hw.mio_pad_attr[2].od_en.q), + .ds (), + .qs (mio_pad_attr_2_od_en_2_qs) + ); + assign reg2hw.mio_pad_attr[2].od_en.qe = mio_pad_attr_2_qe; + + // F[input_disable_2]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_2_input_disable_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_input_disable_2_wd), + .d (hw2reg.mio_pad_attr[2].input_disable.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[7]), + .q (reg2hw.mio_pad_attr[2].input_disable.q), + .ds (), + .qs (mio_pad_attr_2_input_disable_2_qs) + ); + assign reg2hw.mio_pad_attr[2].input_disable.qe = mio_pad_attr_2_qe; + + // F[slew_rate_2]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_2_slew_rate_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_slew_rate_2_wd), + .d (hw2reg.mio_pad_attr[2].slew_rate.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[8]), + .q (reg2hw.mio_pad_attr[2].slew_rate.q), + .ds (), + .qs (mio_pad_attr_2_slew_rate_2_qs) + ); + assign reg2hw.mio_pad_attr[2].slew_rate.qe = mio_pad_attr_2_qe; + + // F[drive_strength_2]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_2_drive_strength_2 ( + .re (mio_pad_attr_2_re), + .we (mio_pad_attr_2_gated_we), + .wd (mio_pad_attr_2_drive_strength_2_wd), + .d (hw2reg.mio_pad_attr[2].drive_strength.d), + .qre (), + .qe (mio_pad_attr_2_flds_we[9]), + .q (reg2hw.mio_pad_attr[2].drive_strength.q), + .ds (), + .qs (mio_pad_attr_2_drive_strength_2_qs) + ); + assign reg2hw.mio_pad_attr[2].drive_strength.qe = mio_pad_attr_2_qe; + + + // Subregister 3 of Multireg mio_pad_attr + // R[mio_pad_attr_3]: V(True) + logic mio_pad_attr_3_qe; + logic [9:0] mio_pad_attr_3_flds_we; + assign mio_pad_attr_3_qe = &mio_pad_attr_3_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_3_gated_we; + assign mio_pad_attr_3_gated_we = mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs; + // F[invert_3]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_invert_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_invert_3_wd), + .d (hw2reg.mio_pad_attr[3].invert.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[0]), + .q (reg2hw.mio_pad_attr[3].invert.q), + .ds (), + .qs (mio_pad_attr_3_invert_3_qs) + ); + assign reg2hw.mio_pad_attr[3].invert.qe = mio_pad_attr_3_qe; + + // F[virtual_od_en_3]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_virtual_od_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_virtual_od_en_3_wd), + .d (hw2reg.mio_pad_attr[3].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[1]), + .q (reg2hw.mio_pad_attr[3].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_3_virtual_od_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].virtual_od_en.qe = mio_pad_attr_3_qe; + + // F[pull_en_3]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_pull_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_pull_en_3_wd), + .d (hw2reg.mio_pad_attr[3].pull_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[2]), + .q (reg2hw.mio_pad_attr[3].pull_en.q), + .ds (), + .qs (mio_pad_attr_3_pull_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].pull_en.qe = mio_pad_attr_3_qe; + + // F[pull_select_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_pull_select_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_pull_select_3_wd), + .d (hw2reg.mio_pad_attr[3].pull_select.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[3]), + .q (reg2hw.mio_pad_attr[3].pull_select.q), + .ds (), + .qs (mio_pad_attr_3_pull_select_3_qs) + ); + assign reg2hw.mio_pad_attr[3].pull_select.qe = mio_pad_attr_3_qe; + + // F[keeper_en_3]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_keeper_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_keeper_en_3_wd), + .d (hw2reg.mio_pad_attr[3].keeper_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[4]), + .q (reg2hw.mio_pad_attr[3].keeper_en.q), + .ds (), + .qs (mio_pad_attr_3_keeper_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].keeper_en.qe = mio_pad_attr_3_qe; + + // F[schmitt_en_3]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_schmitt_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_schmitt_en_3_wd), + .d (hw2reg.mio_pad_attr[3].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[5]), + .q (reg2hw.mio_pad_attr[3].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_3_schmitt_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].schmitt_en.qe = mio_pad_attr_3_qe; + + // F[od_en_3]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_od_en_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_od_en_3_wd), + .d (hw2reg.mio_pad_attr[3].od_en.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[6]), + .q (reg2hw.mio_pad_attr[3].od_en.q), + .ds (), + .qs (mio_pad_attr_3_od_en_3_qs) + ); + assign reg2hw.mio_pad_attr[3].od_en.qe = mio_pad_attr_3_qe; + + // F[input_disable_3]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_3_input_disable_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_input_disable_3_wd), + .d (hw2reg.mio_pad_attr[3].input_disable.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[7]), + .q (reg2hw.mio_pad_attr[3].input_disable.q), + .ds (), + .qs (mio_pad_attr_3_input_disable_3_qs) + ); + assign reg2hw.mio_pad_attr[3].input_disable.qe = mio_pad_attr_3_qe; + + // F[slew_rate_3]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_3_slew_rate_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_slew_rate_3_wd), + .d (hw2reg.mio_pad_attr[3].slew_rate.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[8]), + .q (reg2hw.mio_pad_attr[3].slew_rate.q), + .ds (), + .qs (mio_pad_attr_3_slew_rate_3_qs) + ); + assign reg2hw.mio_pad_attr[3].slew_rate.qe = mio_pad_attr_3_qe; + + // F[drive_strength_3]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_3_drive_strength_3 ( + .re (mio_pad_attr_3_re), + .we (mio_pad_attr_3_gated_we), + .wd (mio_pad_attr_3_drive_strength_3_wd), + .d (hw2reg.mio_pad_attr[3].drive_strength.d), + .qre (), + .qe (mio_pad_attr_3_flds_we[9]), + .q (reg2hw.mio_pad_attr[3].drive_strength.q), + .ds (), + .qs (mio_pad_attr_3_drive_strength_3_qs) + ); + assign reg2hw.mio_pad_attr[3].drive_strength.qe = mio_pad_attr_3_qe; + + + // Subregister 4 of Multireg mio_pad_attr + // R[mio_pad_attr_4]: V(True) + logic mio_pad_attr_4_qe; + logic [9:0] mio_pad_attr_4_flds_we; + assign mio_pad_attr_4_qe = &mio_pad_attr_4_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_4_gated_we; + assign mio_pad_attr_4_gated_we = mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs; + // F[invert_4]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_invert_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_invert_4_wd), + .d (hw2reg.mio_pad_attr[4].invert.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[0]), + .q (reg2hw.mio_pad_attr[4].invert.q), + .ds (), + .qs (mio_pad_attr_4_invert_4_qs) + ); + assign reg2hw.mio_pad_attr[4].invert.qe = mio_pad_attr_4_qe; + + // F[virtual_od_en_4]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_virtual_od_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_virtual_od_en_4_wd), + .d (hw2reg.mio_pad_attr[4].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[1]), + .q (reg2hw.mio_pad_attr[4].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_4_virtual_od_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].virtual_od_en.qe = mio_pad_attr_4_qe; + + // F[pull_en_4]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_pull_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_pull_en_4_wd), + .d (hw2reg.mio_pad_attr[4].pull_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[2]), + .q (reg2hw.mio_pad_attr[4].pull_en.q), + .ds (), + .qs (mio_pad_attr_4_pull_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].pull_en.qe = mio_pad_attr_4_qe; + + // F[pull_select_4]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_pull_select_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_pull_select_4_wd), + .d (hw2reg.mio_pad_attr[4].pull_select.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[3]), + .q (reg2hw.mio_pad_attr[4].pull_select.q), + .ds (), + .qs (mio_pad_attr_4_pull_select_4_qs) + ); + assign reg2hw.mio_pad_attr[4].pull_select.qe = mio_pad_attr_4_qe; + + // F[keeper_en_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_keeper_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_keeper_en_4_wd), + .d (hw2reg.mio_pad_attr[4].keeper_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[4]), + .q (reg2hw.mio_pad_attr[4].keeper_en.q), + .ds (), + .qs (mio_pad_attr_4_keeper_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].keeper_en.qe = mio_pad_attr_4_qe; + + // F[schmitt_en_4]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_schmitt_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_schmitt_en_4_wd), + .d (hw2reg.mio_pad_attr[4].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[5]), + .q (reg2hw.mio_pad_attr[4].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_4_schmitt_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].schmitt_en.qe = mio_pad_attr_4_qe; + + // F[od_en_4]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_od_en_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_od_en_4_wd), + .d (hw2reg.mio_pad_attr[4].od_en.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[6]), + .q (reg2hw.mio_pad_attr[4].od_en.q), + .ds (), + .qs (mio_pad_attr_4_od_en_4_qs) + ); + assign reg2hw.mio_pad_attr[4].od_en.qe = mio_pad_attr_4_qe; + + // F[input_disable_4]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_4_input_disable_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_input_disable_4_wd), + .d (hw2reg.mio_pad_attr[4].input_disable.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[7]), + .q (reg2hw.mio_pad_attr[4].input_disable.q), + .ds (), + .qs (mio_pad_attr_4_input_disable_4_qs) + ); + assign reg2hw.mio_pad_attr[4].input_disable.qe = mio_pad_attr_4_qe; + + // F[slew_rate_4]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_4_slew_rate_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_slew_rate_4_wd), + .d (hw2reg.mio_pad_attr[4].slew_rate.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[8]), + .q (reg2hw.mio_pad_attr[4].slew_rate.q), + .ds (), + .qs (mio_pad_attr_4_slew_rate_4_qs) + ); + assign reg2hw.mio_pad_attr[4].slew_rate.qe = mio_pad_attr_4_qe; + + // F[drive_strength_4]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_4_drive_strength_4 ( + .re (mio_pad_attr_4_re), + .we (mio_pad_attr_4_gated_we), + .wd (mio_pad_attr_4_drive_strength_4_wd), + .d (hw2reg.mio_pad_attr[4].drive_strength.d), + .qre (), + .qe (mio_pad_attr_4_flds_we[9]), + .q (reg2hw.mio_pad_attr[4].drive_strength.q), + .ds (), + .qs (mio_pad_attr_4_drive_strength_4_qs) + ); + assign reg2hw.mio_pad_attr[4].drive_strength.qe = mio_pad_attr_4_qe; + + + // Subregister 5 of Multireg mio_pad_attr + // R[mio_pad_attr_5]: V(True) + logic mio_pad_attr_5_qe; + logic [9:0] mio_pad_attr_5_flds_we; + assign mio_pad_attr_5_qe = &mio_pad_attr_5_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_5_gated_we; + assign mio_pad_attr_5_gated_we = mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs; + // F[invert_5]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_invert_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_invert_5_wd), + .d (hw2reg.mio_pad_attr[5].invert.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[0]), + .q (reg2hw.mio_pad_attr[5].invert.q), + .ds (), + .qs (mio_pad_attr_5_invert_5_qs) + ); + assign reg2hw.mio_pad_attr[5].invert.qe = mio_pad_attr_5_qe; + + // F[virtual_od_en_5]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_virtual_od_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_virtual_od_en_5_wd), + .d (hw2reg.mio_pad_attr[5].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[1]), + .q (reg2hw.mio_pad_attr[5].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_5_virtual_od_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].virtual_od_en.qe = mio_pad_attr_5_qe; + + // F[pull_en_5]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_pull_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_pull_en_5_wd), + .d (hw2reg.mio_pad_attr[5].pull_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[2]), + .q (reg2hw.mio_pad_attr[5].pull_en.q), + .ds (), + .qs (mio_pad_attr_5_pull_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].pull_en.qe = mio_pad_attr_5_qe; + + // F[pull_select_5]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_pull_select_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_pull_select_5_wd), + .d (hw2reg.mio_pad_attr[5].pull_select.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[3]), + .q (reg2hw.mio_pad_attr[5].pull_select.q), + .ds (), + .qs (mio_pad_attr_5_pull_select_5_qs) + ); + assign reg2hw.mio_pad_attr[5].pull_select.qe = mio_pad_attr_5_qe; + + // F[keeper_en_5]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_keeper_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_keeper_en_5_wd), + .d (hw2reg.mio_pad_attr[5].keeper_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[4]), + .q (reg2hw.mio_pad_attr[5].keeper_en.q), + .ds (), + .qs (mio_pad_attr_5_keeper_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].keeper_en.qe = mio_pad_attr_5_qe; + + // F[schmitt_en_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_schmitt_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_schmitt_en_5_wd), + .d (hw2reg.mio_pad_attr[5].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[5]), + .q (reg2hw.mio_pad_attr[5].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_5_schmitt_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].schmitt_en.qe = mio_pad_attr_5_qe; + + // F[od_en_5]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_od_en_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_od_en_5_wd), + .d (hw2reg.mio_pad_attr[5].od_en.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[6]), + .q (reg2hw.mio_pad_attr[5].od_en.q), + .ds (), + .qs (mio_pad_attr_5_od_en_5_qs) + ); + assign reg2hw.mio_pad_attr[5].od_en.qe = mio_pad_attr_5_qe; + + // F[input_disable_5]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_5_input_disable_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_input_disable_5_wd), + .d (hw2reg.mio_pad_attr[5].input_disable.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[7]), + .q (reg2hw.mio_pad_attr[5].input_disable.q), + .ds (), + .qs (mio_pad_attr_5_input_disable_5_qs) + ); + assign reg2hw.mio_pad_attr[5].input_disable.qe = mio_pad_attr_5_qe; + + // F[slew_rate_5]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_5_slew_rate_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_slew_rate_5_wd), + .d (hw2reg.mio_pad_attr[5].slew_rate.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[8]), + .q (reg2hw.mio_pad_attr[5].slew_rate.q), + .ds (), + .qs (mio_pad_attr_5_slew_rate_5_qs) + ); + assign reg2hw.mio_pad_attr[5].slew_rate.qe = mio_pad_attr_5_qe; + + // F[drive_strength_5]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_5_drive_strength_5 ( + .re (mio_pad_attr_5_re), + .we (mio_pad_attr_5_gated_we), + .wd (mio_pad_attr_5_drive_strength_5_wd), + .d (hw2reg.mio_pad_attr[5].drive_strength.d), + .qre (), + .qe (mio_pad_attr_5_flds_we[9]), + .q (reg2hw.mio_pad_attr[5].drive_strength.q), + .ds (), + .qs (mio_pad_attr_5_drive_strength_5_qs) + ); + assign reg2hw.mio_pad_attr[5].drive_strength.qe = mio_pad_attr_5_qe; + + + // Subregister 6 of Multireg mio_pad_attr + // R[mio_pad_attr_6]: V(True) + logic mio_pad_attr_6_qe; + logic [9:0] mio_pad_attr_6_flds_we; + assign mio_pad_attr_6_qe = &mio_pad_attr_6_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_6_gated_we; + assign mio_pad_attr_6_gated_we = mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs; + // F[invert_6]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_invert_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_invert_6_wd), + .d (hw2reg.mio_pad_attr[6].invert.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[0]), + .q (reg2hw.mio_pad_attr[6].invert.q), + .ds (), + .qs (mio_pad_attr_6_invert_6_qs) + ); + assign reg2hw.mio_pad_attr[6].invert.qe = mio_pad_attr_6_qe; + + // F[virtual_od_en_6]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_virtual_od_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_virtual_od_en_6_wd), + .d (hw2reg.mio_pad_attr[6].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[1]), + .q (reg2hw.mio_pad_attr[6].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_6_virtual_od_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].virtual_od_en.qe = mio_pad_attr_6_qe; + + // F[pull_en_6]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_pull_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_pull_en_6_wd), + .d (hw2reg.mio_pad_attr[6].pull_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[2]), + .q (reg2hw.mio_pad_attr[6].pull_en.q), + .ds (), + .qs (mio_pad_attr_6_pull_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].pull_en.qe = mio_pad_attr_6_qe; + + // F[pull_select_6]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_pull_select_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_pull_select_6_wd), + .d (hw2reg.mio_pad_attr[6].pull_select.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[3]), + .q (reg2hw.mio_pad_attr[6].pull_select.q), + .ds (), + .qs (mio_pad_attr_6_pull_select_6_qs) + ); + assign reg2hw.mio_pad_attr[6].pull_select.qe = mio_pad_attr_6_qe; + + // F[keeper_en_6]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_keeper_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_keeper_en_6_wd), + .d (hw2reg.mio_pad_attr[6].keeper_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[4]), + .q (reg2hw.mio_pad_attr[6].keeper_en.q), + .ds (), + .qs (mio_pad_attr_6_keeper_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].keeper_en.qe = mio_pad_attr_6_qe; + + // F[schmitt_en_6]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_schmitt_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_schmitt_en_6_wd), + .d (hw2reg.mio_pad_attr[6].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[5]), + .q (reg2hw.mio_pad_attr[6].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_6_schmitt_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].schmitt_en.qe = mio_pad_attr_6_qe; + + // F[od_en_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_od_en_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_od_en_6_wd), + .d (hw2reg.mio_pad_attr[6].od_en.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[6]), + .q (reg2hw.mio_pad_attr[6].od_en.q), + .ds (), + .qs (mio_pad_attr_6_od_en_6_qs) + ); + assign reg2hw.mio_pad_attr[6].od_en.qe = mio_pad_attr_6_qe; + + // F[input_disable_6]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_6_input_disable_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_input_disable_6_wd), + .d (hw2reg.mio_pad_attr[6].input_disable.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[7]), + .q (reg2hw.mio_pad_attr[6].input_disable.q), + .ds (), + .qs (mio_pad_attr_6_input_disable_6_qs) + ); + assign reg2hw.mio_pad_attr[6].input_disable.qe = mio_pad_attr_6_qe; + + // F[slew_rate_6]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_6_slew_rate_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_slew_rate_6_wd), + .d (hw2reg.mio_pad_attr[6].slew_rate.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[8]), + .q (reg2hw.mio_pad_attr[6].slew_rate.q), + .ds (), + .qs (mio_pad_attr_6_slew_rate_6_qs) + ); + assign reg2hw.mio_pad_attr[6].slew_rate.qe = mio_pad_attr_6_qe; + + // F[drive_strength_6]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_6_drive_strength_6 ( + .re (mio_pad_attr_6_re), + .we (mio_pad_attr_6_gated_we), + .wd (mio_pad_attr_6_drive_strength_6_wd), + .d (hw2reg.mio_pad_attr[6].drive_strength.d), + .qre (), + .qe (mio_pad_attr_6_flds_we[9]), + .q (reg2hw.mio_pad_attr[6].drive_strength.q), + .ds (), + .qs (mio_pad_attr_6_drive_strength_6_qs) + ); + assign reg2hw.mio_pad_attr[6].drive_strength.qe = mio_pad_attr_6_qe; + + + // Subregister 7 of Multireg mio_pad_attr + // R[mio_pad_attr_7]: V(True) + logic mio_pad_attr_7_qe; + logic [9:0] mio_pad_attr_7_flds_we; + assign mio_pad_attr_7_qe = &mio_pad_attr_7_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_7_gated_we; + assign mio_pad_attr_7_gated_we = mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs; + // F[invert_7]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_invert_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_invert_7_wd), + .d (hw2reg.mio_pad_attr[7].invert.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[0]), + .q (reg2hw.mio_pad_attr[7].invert.q), + .ds (), + .qs (mio_pad_attr_7_invert_7_qs) + ); + assign reg2hw.mio_pad_attr[7].invert.qe = mio_pad_attr_7_qe; + + // F[virtual_od_en_7]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_virtual_od_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_virtual_od_en_7_wd), + .d (hw2reg.mio_pad_attr[7].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[1]), + .q (reg2hw.mio_pad_attr[7].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_7_virtual_od_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].virtual_od_en.qe = mio_pad_attr_7_qe; + + // F[pull_en_7]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_pull_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_pull_en_7_wd), + .d (hw2reg.mio_pad_attr[7].pull_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[2]), + .q (reg2hw.mio_pad_attr[7].pull_en.q), + .ds (), + .qs (mio_pad_attr_7_pull_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].pull_en.qe = mio_pad_attr_7_qe; + + // F[pull_select_7]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_pull_select_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_pull_select_7_wd), + .d (hw2reg.mio_pad_attr[7].pull_select.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[3]), + .q (reg2hw.mio_pad_attr[7].pull_select.q), + .ds (), + .qs (mio_pad_attr_7_pull_select_7_qs) + ); + assign reg2hw.mio_pad_attr[7].pull_select.qe = mio_pad_attr_7_qe; + + // F[keeper_en_7]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_keeper_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_keeper_en_7_wd), + .d (hw2reg.mio_pad_attr[7].keeper_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[4]), + .q (reg2hw.mio_pad_attr[7].keeper_en.q), + .ds (), + .qs (mio_pad_attr_7_keeper_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].keeper_en.qe = mio_pad_attr_7_qe; + + // F[schmitt_en_7]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_schmitt_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_schmitt_en_7_wd), + .d (hw2reg.mio_pad_attr[7].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[5]), + .q (reg2hw.mio_pad_attr[7].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_7_schmitt_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].schmitt_en.qe = mio_pad_attr_7_qe; + + // F[od_en_7]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_od_en_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_od_en_7_wd), + .d (hw2reg.mio_pad_attr[7].od_en.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[6]), + .q (reg2hw.mio_pad_attr[7].od_en.q), + .ds (), + .qs (mio_pad_attr_7_od_en_7_qs) + ); + assign reg2hw.mio_pad_attr[7].od_en.qe = mio_pad_attr_7_qe; + + // F[input_disable_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_7_input_disable_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_input_disable_7_wd), + .d (hw2reg.mio_pad_attr[7].input_disable.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[7]), + .q (reg2hw.mio_pad_attr[7].input_disable.q), + .ds (), + .qs (mio_pad_attr_7_input_disable_7_qs) + ); + assign reg2hw.mio_pad_attr[7].input_disable.qe = mio_pad_attr_7_qe; + + // F[slew_rate_7]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_7_slew_rate_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_slew_rate_7_wd), + .d (hw2reg.mio_pad_attr[7].slew_rate.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[8]), + .q (reg2hw.mio_pad_attr[7].slew_rate.q), + .ds (), + .qs (mio_pad_attr_7_slew_rate_7_qs) + ); + assign reg2hw.mio_pad_attr[7].slew_rate.qe = mio_pad_attr_7_qe; + + // F[drive_strength_7]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_7_drive_strength_7 ( + .re (mio_pad_attr_7_re), + .we (mio_pad_attr_7_gated_we), + .wd (mio_pad_attr_7_drive_strength_7_wd), + .d (hw2reg.mio_pad_attr[7].drive_strength.d), + .qre (), + .qe (mio_pad_attr_7_flds_we[9]), + .q (reg2hw.mio_pad_attr[7].drive_strength.q), + .ds (), + .qs (mio_pad_attr_7_drive_strength_7_qs) + ); + assign reg2hw.mio_pad_attr[7].drive_strength.qe = mio_pad_attr_7_qe; + + + // Subregister 8 of Multireg mio_pad_attr + // R[mio_pad_attr_8]: V(True) + logic mio_pad_attr_8_qe; + logic [9:0] mio_pad_attr_8_flds_we; + assign mio_pad_attr_8_qe = &mio_pad_attr_8_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_8_gated_we; + assign mio_pad_attr_8_gated_we = mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs; + // F[invert_8]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_invert_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_invert_8_wd), + .d (hw2reg.mio_pad_attr[8].invert.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[0]), + .q (reg2hw.mio_pad_attr[8].invert.q), + .ds (), + .qs (mio_pad_attr_8_invert_8_qs) + ); + assign reg2hw.mio_pad_attr[8].invert.qe = mio_pad_attr_8_qe; + + // F[virtual_od_en_8]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_virtual_od_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_virtual_od_en_8_wd), + .d (hw2reg.mio_pad_attr[8].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[1]), + .q (reg2hw.mio_pad_attr[8].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_8_virtual_od_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].virtual_od_en.qe = mio_pad_attr_8_qe; + + // F[pull_en_8]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_pull_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_pull_en_8_wd), + .d (hw2reg.mio_pad_attr[8].pull_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[2]), + .q (reg2hw.mio_pad_attr[8].pull_en.q), + .ds (), + .qs (mio_pad_attr_8_pull_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].pull_en.qe = mio_pad_attr_8_qe; + + // F[pull_select_8]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_pull_select_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_pull_select_8_wd), + .d (hw2reg.mio_pad_attr[8].pull_select.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[3]), + .q (reg2hw.mio_pad_attr[8].pull_select.q), + .ds (), + .qs (mio_pad_attr_8_pull_select_8_qs) + ); + assign reg2hw.mio_pad_attr[8].pull_select.qe = mio_pad_attr_8_qe; + + // F[keeper_en_8]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_keeper_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_keeper_en_8_wd), + .d (hw2reg.mio_pad_attr[8].keeper_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[4]), + .q (reg2hw.mio_pad_attr[8].keeper_en.q), + .ds (), + .qs (mio_pad_attr_8_keeper_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].keeper_en.qe = mio_pad_attr_8_qe; + + // F[schmitt_en_8]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_schmitt_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_schmitt_en_8_wd), + .d (hw2reg.mio_pad_attr[8].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[5]), + .q (reg2hw.mio_pad_attr[8].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_8_schmitt_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].schmitt_en.qe = mio_pad_attr_8_qe; + + // F[od_en_8]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_od_en_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_od_en_8_wd), + .d (hw2reg.mio_pad_attr[8].od_en.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[6]), + .q (reg2hw.mio_pad_attr[8].od_en.q), + .ds (), + .qs (mio_pad_attr_8_od_en_8_qs) + ); + assign reg2hw.mio_pad_attr[8].od_en.qe = mio_pad_attr_8_qe; + + // F[input_disable_8]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_8_input_disable_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_input_disable_8_wd), + .d (hw2reg.mio_pad_attr[8].input_disable.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[7]), + .q (reg2hw.mio_pad_attr[8].input_disable.q), + .ds (), + .qs (mio_pad_attr_8_input_disable_8_qs) + ); + assign reg2hw.mio_pad_attr[8].input_disable.qe = mio_pad_attr_8_qe; + + // F[slew_rate_8]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_8_slew_rate_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_slew_rate_8_wd), + .d (hw2reg.mio_pad_attr[8].slew_rate.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[8]), + .q (reg2hw.mio_pad_attr[8].slew_rate.q), + .ds (), + .qs (mio_pad_attr_8_slew_rate_8_qs) + ); + assign reg2hw.mio_pad_attr[8].slew_rate.qe = mio_pad_attr_8_qe; + + // F[drive_strength_8]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_8_drive_strength_8 ( + .re (mio_pad_attr_8_re), + .we (mio_pad_attr_8_gated_we), + .wd (mio_pad_attr_8_drive_strength_8_wd), + .d (hw2reg.mio_pad_attr[8].drive_strength.d), + .qre (), + .qe (mio_pad_attr_8_flds_we[9]), + .q (reg2hw.mio_pad_attr[8].drive_strength.q), + .ds (), + .qs (mio_pad_attr_8_drive_strength_8_qs) + ); + assign reg2hw.mio_pad_attr[8].drive_strength.qe = mio_pad_attr_8_qe; + + + // Subregister 9 of Multireg mio_pad_attr + // R[mio_pad_attr_9]: V(True) + logic mio_pad_attr_9_qe; + logic [9:0] mio_pad_attr_9_flds_we; + assign mio_pad_attr_9_qe = &mio_pad_attr_9_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_9_gated_we; + assign mio_pad_attr_9_gated_we = mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs; + // F[invert_9]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_invert_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_invert_9_wd), + .d (hw2reg.mio_pad_attr[9].invert.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[0]), + .q (reg2hw.mio_pad_attr[9].invert.q), + .ds (), + .qs (mio_pad_attr_9_invert_9_qs) + ); + assign reg2hw.mio_pad_attr[9].invert.qe = mio_pad_attr_9_qe; + + // F[virtual_od_en_9]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_virtual_od_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_virtual_od_en_9_wd), + .d (hw2reg.mio_pad_attr[9].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[1]), + .q (reg2hw.mio_pad_attr[9].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_9_virtual_od_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].virtual_od_en.qe = mio_pad_attr_9_qe; + + // F[pull_en_9]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_pull_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_pull_en_9_wd), + .d (hw2reg.mio_pad_attr[9].pull_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[2]), + .q (reg2hw.mio_pad_attr[9].pull_en.q), + .ds (), + .qs (mio_pad_attr_9_pull_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].pull_en.qe = mio_pad_attr_9_qe; + + // F[pull_select_9]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_pull_select_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_pull_select_9_wd), + .d (hw2reg.mio_pad_attr[9].pull_select.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[3]), + .q (reg2hw.mio_pad_attr[9].pull_select.q), + .ds (), + .qs (mio_pad_attr_9_pull_select_9_qs) + ); + assign reg2hw.mio_pad_attr[9].pull_select.qe = mio_pad_attr_9_qe; + + // F[keeper_en_9]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_keeper_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_keeper_en_9_wd), + .d (hw2reg.mio_pad_attr[9].keeper_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[4]), + .q (reg2hw.mio_pad_attr[9].keeper_en.q), + .ds (), + .qs (mio_pad_attr_9_keeper_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].keeper_en.qe = mio_pad_attr_9_qe; + + // F[schmitt_en_9]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_schmitt_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_schmitt_en_9_wd), + .d (hw2reg.mio_pad_attr[9].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[5]), + .q (reg2hw.mio_pad_attr[9].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_9_schmitt_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].schmitt_en.qe = mio_pad_attr_9_qe; + + // F[od_en_9]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_od_en_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_od_en_9_wd), + .d (hw2reg.mio_pad_attr[9].od_en.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[6]), + .q (reg2hw.mio_pad_attr[9].od_en.q), + .ds (), + .qs (mio_pad_attr_9_od_en_9_qs) + ); + assign reg2hw.mio_pad_attr[9].od_en.qe = mio_pad_attr_9_qe; + + // F[input_disable_9]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_9_input_disable_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_input_disable_9_wd), + .d (hw2reg.mio_pad_attr[9].input_disable.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[7]), + .q (reg2hw.mio_pad_attr[9].input_disable.q), + .ds (), + .qs (mio_pad_attr_9_input_disable_9_qs) + ); + assign reg2hw.mio_pad_attr[9].input_disable.qe = mio_pad_attr_9_qe; + + // F[slew_rate_9]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_9_slew_rate_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_slew_rate_9_wd), + .d (hw2reg.mio_pad_attr[9].slew_rate.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[8]), + .q (reg2hw.mio_pad_attr[9].slew_rate.q), + .ds (), + .qs (mio_pad_attr_9_slew_rate_9_qs) + ); + assign reg2hw.mio_pad_attr[9].slew_rate.qe = mio_pad_attr_9_qe; + + // F[drive_strength_9]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_9_drive_strength_9 ( + .re (mio_pad_attr_9_re), + .we (mio_pad_attr_9_gated_we), + .wd (mio_pad_attr_9_drive_strength_9_wd), + .d (hw2reg.mio_pad_attr[9].drive_strength.d), + .qre (), + .qe (mio_pad_attr_9_flds_we[9]), + .q (reg2hw.mio_pad_attr[9].drive_strength.q), + .ds (), + .qs (mio_pad_attr_9_drive_strength_9_qs) + ); + assign reg2hw.mio_pad_attr[9].drive_strength.qe = mio_pad_attr_9_qe; + + + // Subregister 10 of Multireg mio_pad_attr + // R[mio_pad_attr_10]: V(True) + logic mio_pad_attr_10_qe; + logic [9:0] mio_pad_attr_10_flds_we; + assign mio_pad_attr_10_qe = &mio_pad_attr_10_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_10_gated_we; + assign mio_pad_attr_10_gated_we = mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs; + // F[invert_10]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_invert_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_invert_10_wd), + .d (hw2reg.mio_pad_attr[10].invert.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[0]), + .q (reg2hw.mio_pad_attr[10].invert.q), + .ds (), + .qs (mio_pad_attr_10_invert_10_qs) + ); + assign reg2hw.mio_pad_attr[10].invert.qe = mio_pad_attr_10_qe; + + // F[virtual_od_en_10]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_virtual_od_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_virtual_od_en_10_wd), + .d (hw2reg.mio_pad_attr[10].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[1]), + .q (reg2hw.mio_pad_attr[10].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_10_virtual_od_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].virtual_od_en.qe = mio_pad_attr_10_qe; + + // F[pull_en_10]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_pull_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_pull_en_10_wd), + .d (hw2reg.mio_pad_attr[10].pull_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[2]), + .q (reg2hw.mio_pad_attr[10].pull_en.q), + .ds (), + .qs (mio_pad_attr_10_pull_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].pull_en.qe = mio_pad_attr_10_qe; + + // F[pull_select_10]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_pull_select_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_pull_select_10_wd), + .d (hw2reg.mio_pad_attr[10].pull_select.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[3]), + .q (reg2hw.mio_pad_attr[10].pull_select.q), + .ds (), + .qs (mio_pad_attr_10_pull_select_10_qs) + ); + assign reg2hw.mio_pad_attr[10].pull_select.qe = mio_pad_attr_10_qe; + + // F[keeper_en_10]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_keeper_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_keeper_en_10_wd), + .d (hw2reg.mio_pad_attr[10].keeper_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[4]), + .q (reg2hw.mio_pad_attr[10].keeper_en.q), + .ds (), + .qs (mio_pad_attr_10_keeper_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].keeper_en.qe = mio_pad_attr_10_qe; + + // F[schmitt_en_10]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_schmitt_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_schmitt_en_10_wd), + .d (hw2reg.mio_pad_attr[10].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[5]), + .q (reg2hw.mio_pad_attr[10].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_10_schmitt_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].schmitt_en.qe = mio_pad_attr_10_qe; + + // F[od_en_10]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_od_en_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_od_en_10_wd), + .d (hw2reg.mio_pad_attr[10].od_en.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[6]), + .q (reg2hw.mio_pad_attr[10].od_en.q), + .ds (), + .qs (mio_pad_attr_10_od_en_10_qs) + ); + assign reg2hw.mio_pad_attr[10].od_en.qe = mio_pad_attr_10_qe; + + // F[input_disable_10]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_10_input_disable_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_input_disable_10_wd), + .d (hw2reg.mio_pad_attr[10].input_disable.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[7]), + .q (reg2hw.mio_pad_attr[10].input_disable.q), + .ds (), + .qs (mio_pad_attr_10_input_disable_10_qs) + ); + assign reg2hw.mio_pad_attr[10].input_disable.qe = mio_pad_attr_10_qe; + + // F[slew_rate_10]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_10_slew_rate_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_slew_rate_10_wd), + .d (hw2reg.mio_pad_attr[10].slew_rate.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[8]), + .q (reg2hw.mio_pad_attr[10].slew_rate.q), + .ds (), + .qs (mio_pad_attr_10_slew_rate_10_qs) + ); + assign reg2hw.mio_pad_attr[10].slew_rate.qe = mio_pad_attr_10_qe; + + // F[drive_strength_10]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_10_drive_strength_10 ( + .re (mio_pad_attr_10_re), + .we (mio_pad_attr_10_gated_we), + .wd (mio_pad_attr_10_drive_strength_10_wd), + .d (hw2reg.mio_pad_attr[10].drive_strength.d), + .qre (), + .qe (mio_pad_attr_10_flds_we[9]), + .q (reg2hw.mio_pad_attr[10].drive_strength.q), + .ds (), + .qs (mio_pad_attr_10_drive_strength_10_qs) + ); + assign reg2hw.mio_pad_attr[10].drive_strength.qe = mio_pad_attr_10_qe; + + + // Subregister 11 of Multireg mio_pad_attr + // R[mio_pad_attr_11]: V(True) + logic mio_pad_attr_11_qe; + logic [9:0] mio_pad_attr_11_flds_we; + assign mio_pad_attr_11_qe = &mio_pad_attr_11_flds_we; + // Create REGWEN-gated WE signal + logic mio_pad_attr_11_gated_we; + assign mio_pad_attr_11_gated_we = mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs; + // F[invert_11]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_invert_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_invert_11_wd), + .d (hw2reg.mio_pad_attr[11].invert.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[0]), + .q (reg2hw.mio_pad_attr[11].invert.q), + .ds (), + .qs (mio_pad_attr_11_invert_11_qs) + ); + assign reg2hw.mio_pad_attr[11].invert.qe = mio_pad_attr_11_qe; + + // F[virtual_od_en_11]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_virtual_od_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_virtual_od_en_11_wd), + .d (hw2reg.mio_pad_attr[11].virtual_od_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[1]), + .q (reg2hw.mio_pad_attr[11].virtual_od_en.q), + .ds (), + .qs (mio_pad_attr_11_virtual_od_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].virtual_od_en.qe = mio_pad_attr_11_qe; + + // F[pull_en_11]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_pull_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_pull_en_11_wd), + .d (hw2reg.mio_pad_attr[11].pull_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[2]), + .q (reg2hw.mio_pad_attr[11].pull_en.q), + .ds (), + .qs (mio_pad_attr_11_pull_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].pull_en.qe = mio_pad_attr_11_qe; + + // F[pull_select_11]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_pull_select_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_pull_select_11_wd), + .d (hw2reg.mio_pad_attr[11].pull_select.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[3]), + .q (reg2hw.mio_pad_attr[11].pull_select.q), + .ds (), + .qs (mio_pad_attr_11_pull_select_11_qs) + ); + assign reg2hw.mio_pad_attr[11].pull_select.qe = mio_pad_attr_11_qe; + + // F[keeper_en_11]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_keeper_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_keeper_en_11_wd), + .d (hw2reg.mio_pad_attr[11].keeper_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[4]), + .q (reg2hw.mio_pad_attr[11].keeper_en.q), + .ds (), + .qs (mio_pad_attr_11_keeper_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].keeper_en.qe = mio_pad_attr_11_qe; + + // F[schmitt_en_11]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_schmitt_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_schmitt_en_11_wd), + .d (hw2reg.mio_pad_attr[11].schmitt_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[5]), + .q (reg2hw.mio_pad_attr[11].schmitt_en.q), + .ds (), + .qs (mio_pad_attr_11_schmitt_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].schmitt_en.qe = mio_pad_attr_11_qe; + + // F[od_en_11]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_od_en_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_od_en_11_wd), + .d (hw2reg.mio_pad_attr[11].od_en.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[6]), + .q (reg2hw.mio_pad_attr[11].od_en.q), + .ds (), + .qs (mio_pad_attr_11_od_en_11_qs) + ); + assign reg2hw.mio_pad_attr[11].od_en.qe = mio_pad_attr_11_qe; + + // F[input_disable_11]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_mio_pad_attr_11_input_disable_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_input_disable_11_wd), + .d (hw2reg.mio_pad_attr[11].input_disable.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[7]), + .q (reg2hw.mio_pad_attr[11].input_disable.q), + .ds (), + .qs (mio_pad_attr_11_input_disable_11_qs) + ); + assign reg2hw.mio_pad_attr[11].input_disable.qe = mio_pad_attr_11_qe; + + // F[slew_rate_11]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_mio_pad_attr_11_slew_rate_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_slew_rate_11_wd), + .d (hw2reg.mio_pad_attr[11].slew_rate.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[8]), + .q (reg2hw.mio_pad_attr[11].slew_rate.q), + .ds (), + .qs (mio_pad_attr_11_slew_rate_11_qs) + ); + assign reg2hw.mio_pad_attr[11].slew_rate.qe = mio_pad_attr_11_qe; + + // F[drive_strength_11]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_mio_pad_attr_11_drive_strength_11 ( + .re (mio_pad_attr_11_re), + .we (mio_pad_attr_11_gated_we), + .wd (mio_pad_attr_11_drive_strength_11_wd), + .d (hw2reg.mio_pad_attr[11].drive_strength.d), + .qre (), + .qe (mio_pad_attr_11_flds_we[9]), + .q (reg2hw.mio_pad_attr[11].drive_strength.q), + .ds (), + .qs (mio_pad_attr_11_drive_strength_11_qs) + ); + assign reg2hw.mio_pad_attr[11].drive_strength.qe = mio_pad_attr_11_qe; + + + // Subregister 0 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_0_we), + .wd (dio_pad_attr_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_0_qs) + ); + + + // Subregister 1 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_1_we), + .wd (dio_pad_attr_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_1_qs) + ); + + + // Subregister 2 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_2_we), + .wd (dio_pad_attr_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_2_qs) + ); + + + // Subregister 3 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_3_we), + .wd (dio_pad_attr_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_3_qs) + ); + + + // Subregister 4 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_4_we), + .wd (dio_pad_attr_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_4_qs) + ); + + + // Subregister 5 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_5_we), + .wd (dio_pad_attr_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_5_qs) + ); + + + // Subregister 6 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_6_we), + .wd (dio_pad_attr_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_6_qs) + ); + + + // Subregister 7 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_7_we), + .wd (dio_pad_attr_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_7_qs) + ); + + + // Subregister 8 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_8_we), + .wd (dio_pad_attr_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_8_qs) + ); + + + // Subregister 9 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_9_we), + .wd (dio_pad_attr_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_9_qs) + ); + + + // Subregister 10 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_10_we), + .wd (dio_pad_attr_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_10_qs) + ); + + + // Subregister 11 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_11_we), + .wd (dio_pad_attr_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_11_qs) + ); + + + // Subregister 12 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_12]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_12_we), + .wd (dio_pad_attr_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_12_qs) + ); + + + // Subregister 13 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_13]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_13_we), + .wd (dio_pad_attr_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_13_qs) + ); + + + // Subregister 14 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_14]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_14_we), + .wd (dio_pad_attr_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_14_qs) + ); + + + // Subregister 15 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_15]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_15_we), + .wd (dio_pad_attr_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_15_qs) + ); + + + // Subregister 16 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_16]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_16_we), + .wd (dio_pad_attr_regwen_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_16_qs) + ); + + + // Subregister 17 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_17]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_17_we), + .wd (dio_pad_attr_regwen_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_17_qs) + ); + + + // Subregister 18 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_18]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_18_we), + .wd (dio_pad_attr_regwen_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_18_qs) + ); + + + // Subregister 19 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_19]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_19_we), + .wd (dio_pad_attr_regwen_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_19_qs) + ); + + + // Subregister 20 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_20]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_20_we), + .wd (dio_pad_attr_regwen_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_20_qs) + ); + + + // Subregister 21 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_21]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_21_we), + .wd (dio_pad_attr_regwen_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_21_qs) + ); + + + // Subregister 22 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_22]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_22_we), + .wd (dio_pad_attr_regwen_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_22_qs) + ); + + + // Subregister 23 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_23]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_23_we), + .wd (dio_pad_attr_regwen_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_23_qs) + ); + + + // Subregister 24 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_24]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_24_we), + .wd (dio_pad_attr_regwen_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_24_qs) + ); + + + // Subregister 25 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_25]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_25_we), + .wd (dio_pad_attr_regwen_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_25_qs) + ); + + + // Subregister 26 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_26]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_26_we), + .wd (dio_pad_attr_regwen_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_26_qs) + ); + + + // Subregister 27 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_27]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_27_we), + .wd (dio_pad_attr_regwen_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_27_qs) + ); + + + // Subregister 28 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_28]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_28_we), + .wd (dio_pad_attr_regwen_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_28_qs) + ); + + + // Subregister 29 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_29]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_29_we), + .wd (dio_pad_attr_regwen_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_29_qs) + ); + + + // Subregister 30 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_30]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_30_we), + .wd (dio_pad_attr_regwen_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_30_qs) + ); + + + // Subregister 31 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_31]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_31_we), + .wd (dio_pad_attr_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_31_qs) + ); + + + // Subregister 32 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_32]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_32_we), + .wd (dio_pad_attr_regwen_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_32_qs) + ); + + + // Subregister 33 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_33]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_33_we), + .wd (dio_pad_attr_regwen_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_33_qs) + ); + + + // Subregister 34 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_34]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_34_we), + .wd (dio_pad_attr_regwen_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_34_qs) + ); + + + // Subregister 35 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_35]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_35_we), + .wd (dio_pad_attr_regwen_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_35_qs) + ); + + + // Subregister 36 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_36]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_36_we), + .wd (dio_pad_attr_regwen_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_36_qs) + ); + + + // Subregister 37 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_37_we), + .wd (dio_pad_attr_regwen_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_38_we), + .wd (dio_pad_attr_regwen_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_39_we), + .wd (dio_pad_attr_regwen_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_40_we), + .wd (dio_pad_attr_regwen_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_41_we), + .wd (dio_pad_attr_regwen_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_42_we), + .wd (dio_pad_attr_regwen_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_42_qs) + ); + + + // Subregister 43 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_43]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_43_we), + .wd (dio_pad_attr_regwen_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_43_qs) + ); + + + // Subregister 44 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_44]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_44_we), + .wd (dio_pad_attr_regwen_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_44_qs) + ); + + + // Subregister 45 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_45]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_45_we), + .wd (dio_pad_attr_regwen_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_45_qs) + ); + + + // Subregister 46 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_46]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_46_we), + .wd (dio_pad_attr_regwen_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_46_qs) + ); + + + // Subregister 47 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_47]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_47_we), + .wd (dio_pad_attr_regwen_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_47_qs) + ); + + + // Subregister 48 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_48]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_48_we), + .wd (dio_pad_attr_regwen_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_48_qs) + ); + + + // Subregister 49 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_49]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_49_we), + .wd (dio_pad_attr_regwen_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_49_qs) + ); + + + // Subregister 50 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_50]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_50_we), + .wd (dio_pad_attr_regwen_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_50_qs) + ); + + + // Subregister 51 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_51]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_51_we), + .wd (dio_pad_attr_regwen_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_51_qs) + ); + + + // Subregister 52 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_52]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_52_we), + .wd (dio_pad_attr_regwen_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_52_qs) + ); + + + // Subregister 53 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_53]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_53_we), + .wd (dio_pad_attr_regwen_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_53_qs) + ); + + + // Subregister 54 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_54]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_54_we), + .wd (dio_pad_attr_regwen_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_54_qs) + ); + + + // Subregister 55 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_55]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_55_we), + .wd (dio_pad_attr_regwen_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_55_qs) + ); + + + // Subregister 56 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_56]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_56_we), + .wd (dio_pad_attr_regwen_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_56_qs) + ); + + + // Subregister 57 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_57_we), + .wd (dio_pad_attr_regwen_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_57_qs) + ); + + + // Subregister 58 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_58_we), + .wd (dio_pad_attr_regwen_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_58_qs) + ); + + + // Subregister 59 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_59]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_59_we), + .wd (dio_pad_attr_regwen_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_59_qs) + ); + + + // Subregister 60 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_60]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_60_we), + .wd (dio_pad_attr_regwen_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_60_qs) + ); + + + // Subregister 61 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_61]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_61_we), + .wd (dio_pad_attr_regwen_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_61_qs) + ); + + + // Subregister 62 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_62]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_62_we), + .wd (dio_pad_attr_regwen_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_62_qs) + ); + + + // Subregister 63 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_63_we), + .wd (dio_pad_attr_regwen_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_63_qs) + ); + + + // Subregister 64 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_64_we), + .wd (dio_pad_attr_regwen_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_64_qs) + ); + + + // Subregister 65 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_65_we), + .wd (dio_pad_attr_regwen_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_65_qs) + ); + + + // Subregister 66 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_66_we), + .wd (dio_pad_attr_regwen_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_66_qs) + ); + + + // Subregister 67 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_67_we), + .wd (dio_pad_attr_regwen_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_67_qs) + ); + + + // Subregister 68 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_68_we), + .wd (dio_pad_attr_regwen_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_68_qs) + ); + + + // Subregister 69 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_69]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_69_we), + .wd (dio_pad_attr_regwen_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_69_qs) + ); + + + // Subregister 70 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_70]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_70_we), + .wd (dio_pad_attr_regwen_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_70_qs) + ); + + + // Subregister 71 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_71]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_71_we), + .wd (dio_pad_attr_regwen_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_71_qs) + ); + + + // Subregister 72 of Multireg dio_pad_attr_regwen + // R[dio_pad_attr_regwen_72]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_attr_regwen_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_attr_regwen_72_we), + .wd (dio_pad_attr_regwen_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_attr_regwen_72_qs) + ); + + + // Subregister 0 of Multireg dio_pad_attr + // R[dio_pad_attr_0]: V(True) + logic dio_pad_attr_0_qe; + logic [9:0] dio_pad_attr_0_flds_we; + assign dio_pad_attr_0_qe = &dio_pad_attr_0_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_0_gated_we; + assign dio_pad_attr_0_gated_we = dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs; + // F[invert_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_invert_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_invert_0_wd), + .d (hw2reg.dio_pad_attr[0].invert.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[0]), + .q (reg2hw.dio_pad_attr[0].invert.q), + .ds (), + .qs (dio_pad_attr_0_invert_0_qs) + ); + assign reg2hw.dio_pad_attr[0].invert.qe = dio_pad_attr_0_qe; + + // F[virtual_od_en_0]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_virtual_od_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_virtual_od_en_0_wd), + .d (hw2reg.dio_pad_attr[0].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[1]), + .q (reg2hw.dio_pad_attr[0].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_0_virtual_od_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].virtual_od_en.qe = dio_pad_attr_0_qe; + + // F[pull_en_0]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_pull_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_pull_en_0_wd), + .d (hw2reg.dio_pad_attr[0].pull_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[2]), + .q (reg2hw.dio_pad_attr[0].pull_en.q), + .ds (), + .qs (dio_pad_attr_0_pull_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].pull_en.qe = dio_pad_attr_0_qe; + + // F[pull_select_0]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_pull_select_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_pull_select_0_wd), + .d (hw2reg.dio_pad_attr[0].pull_select.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[3]), + .q (reg2hw.dio_pad_attr[0].pull_select.q), + .ds (), + .qs (dio_pad_attr_0_pull_select_0_qs) + ); + assign reg2hw.dio_pad_attr[0].pull_select.qe = dio_pad_attr_0_qe; + + // F[keeper_en_0]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_keeper_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_keeper_en_0_wd), + .d (hw2reg.dio_pad_attr[0].keeper_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[4]), + .q (reg2hw.dio_pad_attr[0].keeper_en.q), + .ds (), + .qs (dio_pad_attr_0_keeper_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].keeper_en.qe = dio_pad_attr_0_qe; + + // F[schmitt_en_0]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_schmitt_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_schmitt_en_0_wd), + .d (hw2reg.dio_pad_attr[0].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[5]), + .q (reg2hw.dio_pad_attr[0].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_0_schmitt_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].schmitt_en.qe = dio_pad_attr_0_qe; + + // F[od_en_0]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_od_en_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_od_en_0_wd), + .d (hw2reg.dio_pad_attr[0].od_en.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[6]), + .q (reg2hw.dio_pad_attr[0].od_en.q), + .ds (), + .qs (dio_pad_attr_0_od_en_0_qs) + ); + assign reg2hw.dio_pad_attr[0].od_en.qe = dio_pad_attr_0_qe; + + // F[input_disable_0]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_0_input_disable_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_input_disable_0_wd), + .d (hw2reg.dio_pad_attr[0].input_disable.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[7]), + .q (reg2hw.dio_pad_attr[0].input_disable.q), + .ds (), + .qs (dio_pad_attr_0_input_disable_0_qs) + ); + assign reg2hw.dio_pad_attr[0].input_disable.qe = dio_pad_attr_0_qe; + + // F[slew_rate_0]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_0_slew_rate_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_slew_rate_0_wd), + .d (hw2reg.dio_pad_attr[0].slew_rate.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[8]), + .q (reg2hw.dio_pad_attr[0].slew_rate.q), + .ds (), + .qs (dio_pad_attr_0_slew_rate_0_qs) + ); + assign reg2hw.dio_pad_attr[0].slew_rate.qe = dio_pad_attr_0_qe; + + // F[drive_strength_0]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_0_drive_strength_0 ( + .re (dio_pad_attr_0_re), + .we (dio_pad_attr_0_gated_we), + .wd (dio_pad_attr_0_drive_strength_0_wd), + .d (hw2reg.dio_pad_attr[0].drive_strength.d), + .qre (), + .qe (dio_pad_attr_0_flds_we[9]), + .q (reg2hw.dio_pad_attr[0].drive_strength.q), + .ds (), + .qs (dio_pad_attr_0_drive_strength_0_qs) + ); + assign reg2hw.dio_pad_attr[0].drive_strength.qe = dio_pad_attr_0_qe; + + + // Subregister 1 of Multireg dio_pad_attr + // R[dio_pad_attr_1]: V(True) + logic dio_pad_attr_1_qe; + logic [9:0] dio_pad_attr_1_flds_we; + assign dio_pad_attr_1_qe = &dio_pad_attr_1_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_1_gated_we; + assign dio_pad_attr_1_gated_we = dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs; + // F[invert_1]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_invert_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_invert_1_wd), + .d (hw2reg.dio_pad_attr[1].invert.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[0]), + .q (reg2hw.dio_pad_attr[1].invert.q), + .ds (), + .qs (dio_pad_attr_1_invert_1_qs) + ); + assign reg2hw.dio_pad_attr[1].invert.qe = dio_pad_attr_1_qe; + + // F[virtual_od_en_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_virtual_od_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_virtual_od_en_1_wd), + .d (hw2reg.dio_pad_attr[1].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[1]), + .q (reg2hw.dio_pad_attr[1].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_1_virtual_od_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].virtual_od_en.qe = dio_pad_attr_1_qe; + + // F[pull_en_1]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_pull_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_pull_en_1_wd), + .d (hw2reg.dio_pad_attr[1].pull_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[2]), + .q (reg2hw.dio_pad_attr[1].pull_en.q), + .ds (), + .qs (dio_pad_attr_1_pull_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].pull_en.qe = dio_pad_attr_1_qe; + + // F[pull_select_1]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_pull_select_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_pull_select_1_wd), + .d (hw2reg.dio_pad_attr[1].pull_select.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[3]), + .q (reg2hw.dio_pad_attr[1].pull_select.q), + .ds (), + .qs (dio_pad_attr_1_pull_select_1_qs) + ); + assign reg2hw.dio_pad_attr[1].pull_select.qe = dio_pad_attr_1_qe; + + // F[keeper_en_1]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_keeper_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_keeper_en_1_wd), + .d (hw2reg.dio_pad_attr[1].keeper_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[4]), + .q (reg2hw.dio_pad_attr[1].keeper_en.q), + .ds (), + .qs (dio_pad_attr_1_keeper_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].keeper_en.qe = dio_pad_attr_1_qe; + + // F[schmitt_en_1]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_schmitt_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_schmitt_en_1_wd), + .d (hw2reg.dio_pad_attr[1].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[5]), + .q (reg2hw.dio_pad_attr[1].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_1_schmitt_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].schmitt_en.qe = dio_pad_attr_1_qe; + + // F[od_en_1]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_od_en_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_od_en_1_wd), + .d (hw2reg.dio_pad_attr[1].od_en.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[6]), + .q (reg2hw.dio_pad_attr[1].od_en.q), + .ds (), + .qs (dio_pad_attr_1_od_en_1_qs) + ); + assign reg2hw.dio_pad_attr[1].od_en.qe = dio_pad_attr_1_qe; + + // F[input_disable_1]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_1_input_disable_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_input_disable_1_wd), + .d (hw2reg.dio_pad_attr[1].input_disable.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[7]), + .q (reg2hw.dio_pad_attr[1].input_disable.q), + .ds (), + .qs (dio_pad_attr_1_input_disable_1_qs) + ); + assign reg2hw.dio_pad_attr[1].input_disable.qe = dio_pad_attr_1_qe; + + // F[slew_rate_1]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_1_slew_rate_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_slew_rate_1_wd), + .d (hw2reg.dio_pad_attr[1].slew_rate.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[8]), + .q (reg2hw.dio_pad_attr[1].slew_rate.q), + .ds (), + .qs (dio_pad_attr_1_slew_rate_1_qs) + ); + assign reg2hw.dio_pad_attr[1].slew_rate.qe = dio_pad_attr_1_qe; + + // F[drive_strength_1]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_1_drive_strength_1 ( + .re (dio_pad_attr_1_re), + .we (dio_pad_attr_1_gated_we), + .wd (dio_pad_attr_1_drive_strength_1_wd), + .d (hw2reg.dio_pad_attr[1].drive_strength.d), + .qre (), + .qe (dio_pad_attr_1_flds_we[9]), + .q (reg2hw.dio_pad_attr[1].drive_strength.q), + .ds (), + .qs (dio_pad_attr_1_drive_strength_1_qs) + ); + assign reg2hw.dio_pad_attr[1].drive_strength.qe = dio_pad_attr_1_qe; + + + // Subregister 2 of Multireg dio_pad_attr + // R[dio_pad_attr_2]: V(True) + logic dio_pad_attr_2_qe; + logic [9:0] dio_pad_attr_2_flds_we; + assign dio_pad_attr_2_qe = &dio_pad_attr_2_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_2_gated_we; + assign dio_pad_attr_2_gated_we = dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs; + // F[invert_2]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_invert_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_invert_2_wd), + .d (hw2reg.dio_pad_attr[2].invert.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[0]), + .q (reg2hw.dio_pad_attr[2].invert.q), + .ds (), + .qs (dio_pad_attr_2_invert_2_qs) + ); + assign reg2hw.dio_pad_attr[2].invert.qe = dio_pad_attr_2_qe; + + // F[virtual_od_en_2]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_virtual_od_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_virtual_od_en_2_wd), + .d (hw2reg.dio_pad_attr[2].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[1]), + .q (reg2hw.dio_pad_attr[2].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_2_virtual_od_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].virtual_od_en.qe = dio_pad_attr_2_qe; + + // F[pull_en_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_pull_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_pull_en_2_wd), + .d (hw2reg.dio_pad_attr[2].pull_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[2]), + .q (reg2hw.dio_pad_attr[2].pull_en.q), + .ds (), + .qs (dio_pad_attr_2_pull_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].pull_en.qe = dio_pad_attr_2_qe; + + // F[pull_select_2]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_pull_select_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_pull_select_2_wd), + .d (hw2reg.dio_pad_attr[2].pull_select.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[3]), + .q (reg2hw.dio_pad_attr[2].pull_select.q), + .ds (), + .qs (dio_pad_attr_2_pull_select_2_qs) + ); + assign reg2hw.dio_pad_attr[2].pull_select.qe = dio_pad_attr_2_qe; + + // F[keeper_en_2]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_keeper_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_keeper_en_2_wd), + .d (hw2reg.dio_pad_attr[2].keeper_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[4]), + .q (reg2hw.dio_pad_attr[2].keeper_en.q), + .ds (), + .qs (dio_pad_attr_2_keeper_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].keeper_en.qe = dio_pad_attr_2_qe; + + // F[schmitt_en_2]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_schmitt_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_schmitt_en_2_wd), + .d (hw2reg.dio_pad_attr[2].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[5]), + .q (reg2hw.dio_pad_attr[2].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_2_schmitt_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].schmitt_en.qe = dio_pad_attr_2_qe; + + // F[od_en_2]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_od_en_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_od_en_2_wd), + .d (hw2reg.dio_pad_attr[2].od_en.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[6]), + .q (reg2hw.dio_pad_attr[2].od_en.q), + .ds (), + .qs (dio_pad_attr_2_od_en_2_qs) + ); + assign reg2hw.dio_pad_attr[2].od_en.qe = dio_pad_attr_2_qe; + + // F[input_disable_2]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_2_input_disable_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_input_disable_2_wd), + .d (hw2reg.dio_pad_attr[2].input_disable.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[7]), + .q (reg2hw.dio_pad_attr[2].input_disable.q), + .ds (), + .qs (dio_pad_attr_2_input_disable_2_qs) + ); + assign reg2hw.dio_pad_attr[2].input_disable.qe = dio_pad_attr_2_qe; + + // F[slew_rate_2]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_2_slew_rate_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_slew_rate_2_wd), + .d (hw2reg.dio_pad_attr[2].slew_rate.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[8]), + .q (reg2hw.dio_pad_attr[2].slew_rate.q), + .ds (), + .qs (dio_pad_attr_2_slew_rate_2_qs) + ); + assign reg2hw.dio_pad_attr[2].slew_rate.qe = dio_pad_attr_2_qe; + + // F[drive_strength_2]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_2_drive_strength_2 ( + .re (dio_pad_attr_2_re), + .we (dio_pad_attr_2_gated_we), + .wd (dio_pad_attr_2_drive_strength_2_wd), + .d (hw2reg.dio_pad_attr[2].drive_strength.d), + .qre (), + .qe (dio_pad_attr_2_flds_we[9]), + .q (reg2hw.dio_pad_attr[2].drive_strength.q), + .ds (), + .qs (dio_pad_attr_2_drive_strength_2_qs) + ); + assign reg2hw.dio_pad_attr[2].drive_strength.qe = dio_pad_attr_2_qe; + + + // Subregister 3 of Multireg dio_pad_attr + // R[dio_pad_attr_3]: V(True) + logic dio_pad_attr_3_qe; + logic [9:0] dio_pad_attr_3_flds_we; + assign dio_pad_attr_3_qe = &dio_pad_attr_3_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_3_gated_we; + assign dio_pad_attr_3_gated_we = dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs; + // F[invert_3]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_invert_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_invert_3_wd), + .d (hw2reg.dio_pad_attr[3].invert.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[0]), + .q (reg2hw.dio_pad_attr[3].invert.q), + .ds (), + .qs (dio_pad_attr_3_invert_3_qs) + ); + assign reg2hw.dio_pad_attr[3].invert.qe = dio_pad_attr_3_qe; + + // F[virtual_od_en_3]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_virtual_od_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_virtual_od_en_3_wd), + .d (hw2reg.dio_pad_attr[3].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[1]), + .q (reg2hw.dio_pad_attr[3].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_3_virtual_od_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].virtual_od_en.qe = dio_pad_attr_3_qe; + + // F[pull_en_3]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_pull_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_pull_en_3_wd), + .d (hw2reg.dio_pad_attr[3].pull_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[2]), + .q (reg2hw.dio_pad_attr[3].pull_en.q), + .ds (), + .qs (dio_pad_attr_3_pull_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].pull_en.qe = dio_pad_attr_3_qe; + + // F[pull_select_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_pull_select_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_pull_select_3_wd), + .d (hw2reg.dio_pad_attr[3].pull_select.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[3]), + .q (reg2hw.dio_pad_attr[3].pull_select.q), + .ds (), + .qs (dio_pad_attr_3_pull_select_3_qs) + ); + assign reg2hw.dio_pad_attr[3].pull_select.qe = dio_pad_attr_3_qe; + + // F[keeper_en_3]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_keeper_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_keeper_en_3_wd), + .d (hw2reg.dio_pad_attr[3].keeper_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[4]), + .q (reg2hw.dio_pad_attr[3].keeper_en.q), + .ds (), + .qs (dio_pad_attr_3_keeper_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].keeper_en.qe = dio_pad_attr_3_qe; + + // F[schmitt_en_3]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_schmitt_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_schmitt_en_3_wd), + .d (hw2reg.dio_pad_attr[3].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[5]), + .q (reg2hw.dio_pad_attr[3].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_3_schmitt_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].schmitt_en.qe = dio_pad_attr_3_qe; + + // F[od_en_3]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_od_en_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_od_en_3_wd), + .d (hw2reg.dio_pad_attr[3].od_en.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[6]), + .q (reg2hw.dio_pad_attr[3].od_en.q), + .ds (), + .qs (dio_pad_attr_3_od_en_3_qs) + ); + assign reg2hw.dio_pad_attr[3].od_en.qe = dio_pad_attr_3_qe; + + // F[input_disable_3]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_3_input_disable_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_input_disable_3_wd), + .d (hw2reg.dio_pad_attr[3].input_disable.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[7]), + .q (reg2hw.dio_pad_attr[3].input_disable.q), + .ds (), + .qs (dio_pad_attr_3_input_disable_3_qs) + ); + assign reg2hw.dio_pad_attr[3].input_disable.qe = dio_pad_attr_3_qe; + + // F[slew_rate_3]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_3_slew_rate_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_slew_rate_3_wd), + .d (hw2reg.dio_pad_attr[3].slew_rate.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[8]), + .q (reg2hw.dio_pad_attr[3].slew_rate.q), + .ds (), + .qs (dio_pad_attr_3_slew_rate_3_qs) + ); + assign reg2hw.dio_pad_attr[3].slew_rate.qe = dio_pad_attr_3_qe; + + // F[drive_strength_3]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_3_drive_strength_3 ( + .re (dio_pad_attr_3_re), + .we (dio_pad_attr_3_gated_we), + .wd (dio_pad_attr_3_drive_strength_3_wd), + .d (hw2reg.dio_pad_attr[3].drive_strength.d), + .qre (), + .qe (dio_pad_attr_3_flds_we[9]), + .q (reg2hw.dio_pad_attr[3].drive_strength.q), + .ds (), + .qs (dio_pad_attr_3_drive_strength_3_qs) + ); + assign reg2hw.dio_pad_attr[3].drive_strength.qe = dio_pad_attr_3_qe; + + + // Subregister 4 of Multireg dio_pad_attr + // R[dio_pad_attr_4]: V(True) + logic dio_pad_attr_4_qe; + logic [9:0] dio_pad_attr_4_flds_we; + assign dio_pad_attr_4_qe = &dio_pad_attr_4_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_4_gated_we; + assign dio_pad_attr_4_gated_we = dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs; + // F[invert_4]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_invert_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_invert_4_wd), + .d (hw2reg.dio_pad_attr[4].invert.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[0]), + .q (reg2hw.dio_pad_attr[4].invert.q), + .ds (), + .qs (dio_pad_attr_4_invert_4_qs) + ); + assign reg2hw.dio_pad_attr[4].invert.qe = dio_pad_attr_4_qe; + + // F[virtual_od_en_4]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_virtual_od_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_virtual_od_en_4_wd), + .d (hw2reg.dio_pad_attr[4].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[1]), + .q (reg2hw.dio_pad_attr[4].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_4_virtual_od_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].virtual_od_en.qe = dio_pad_attr_4_qe; + + // F[pull_en_4]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_pull_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_pull_en_4_wd), + .d (hw2reg.dio_pad_attr[4].pull_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[2]), + .q (reg2hw.dio_pad_attr[4].pull_en.q), + .ds (), + .qs (dio_pad_attr_4_pull_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].pull_en.qe = dio_pad_attr_4_qe; + + // F[pull_select_4]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_pull_select_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_pull_select_4_wd), + .d (hw2reg.dio_pad_attr[4].pull_select.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[3]), + .q (reg2hw.dio_pad_attr[4].pull_select.q), + .ds (), + .qs (dio_pad_attr_4_pull_select_4_qs) + ); + assign reg2hw.dio_pad_attr[4].pull_select.qe = dio_pad_attr_4_qe; + + // F[keeper_en_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_keeper_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_keeper_en_4_wd), + .d (hw2reg.dio_pad_attr[4].keeper_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[4]), + .q (reg2hw.dio_pad_attr[4].keeper_en.q), + .ds (), + .qs (dio_pad_attr_4_keeper_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].keeper_en.qe = dio_pad_attr_4_qe; + + // F[schmitt_en_4]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_schmitt_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_schmitt_en_4_wd), + .d (hw2reg.dio_pad_attr[4].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[5]), + .q (reg2hw.dio_pad_attr[4].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_4_schmitt_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].schmitt_en.qe = dio_pad_attr_4_qe; + + // F[od_en_4]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_od_en_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_od_en_4_wd), + .d (hw2reg.dio_pad_attr[4].od_en.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[6]), + .q (reg2hw.dio_pad_attr[4].od_en.q), + .ds (), + .qs (dio_pad_attr_4_od_en_4_qs) + ); + assign reg2hw.dio_pad_attr[4].od_en.qe = dio_pad_attr_4_qe; + + // F[input_disable_4]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_4_input_disable_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_input_disable_4_wd), + .d (hw2reg.dio_pad_attr[4].input_disable.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[7]), + .q (reg2hw.dio_pad_attr[4].input_disable.q), + .ds (), + .qs (dio_pad_attr_4_input_disable_4_qs) + ); + assign reg2hw.dio_pad_attr[4].input_disable.qe = dio_pad_attr_4_qe; + + // F[slew_rate_4]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_4_slew_rate_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_slew_rate_4_wd), + .d (hw2reg.dio_pad_attr[4].slew_rate.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[8]), + .q (reg2hw.dio_pad_attr[4].slew_rate.q), + .ds (), + .qs (dio_pad_attr_4_slew_rate_4_qs) + ); + assign reg2hw.dio_pad_attr[4].slew_rate.qe = dio_pad_attr_4_qe; + + // F[drive_strength_4]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_4_drive_strength_4 ( + .re (dio_pad_attr_4_re), + .we (dio_pad_attr_4_gated_we), + .wd (dio_pad_attr_4_drive_strength_4_wd), + .d (hw2reg.dio_pad_attr[4].drive_strength.d), + .qre (), + .qe (dio_pad_attr_4_flds_we[9]), + .q (reg2hw.dio_pad_attr[4].drive_strength.q), + .ds (), + .qs (dio_pad_attr_4_drive_strength_4_qs) + ); + assign reg2hw.dio_pad_attr[4].drive_strength.qe = dio_pad_attr_4_qe; + + + // Subregister 5 of Multireg dio_pad_attr + // R[dio_pad_attr_5]: V(True) + logic dio_pad_attr_5_qe; + logic [9:0] dio_pad_attr_5_flds_we; + assign dio_pad_attr_5_qe = &dio_pad_attr_5_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_5_gated_we; + assign dio_pad_attr_5_gated_we = dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs; + // F[invert_5]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_invert_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_invert_5_wd), + .d (hw2reg.dio_pad_attr[5].invert.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[0]), + .q (reg2hw.dio_pad_attr[5].invert.q), + .ds (), + .qs (dio_pad_attr_5_invert_5_qs) + ); + assign reg2hw.dio_pad_attr[5].invert.qe = dio_pad_attr_5_qe; + + // F[virtual_od_en_5]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_virtual_od_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_virtual_od_en_5_wd), + .d (hw2reg.dio_pad_attr[5].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[1]), + .q (reg2hw.dio_pad_attr[5].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_5_virtual_od_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].virtual_od_en.qe = dio_pad_attr_5_qe; + + // F[pull_en_5]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_pull_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_pull_en_5_wd), + .d (hw2reg.dio_pad_attr[5].pull_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[2]), + .q (reg2hw.dio_pad_attr[5].pull_en.q), + .ds (), + .qs (dio_pad_attr_5_pull_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].pull_en.qe = dio_pad_attr_5_qe; + + // F[pull_select_5]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_pull_select_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_pull_select_5_wd), + .d (hw2reg.dio_pad_attr[5].pull_select.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[3]), + .q (reg2hw.dio_pad_attr[5].pull_select.q), + .ds (), + .qs (dio_pad_attr_5_pull_select_5_qs) + ); + assign reg2hw.dio_pad_attr[5].pull_select.qe = dio_pad_attr_5_qe; + + // F[keeper_en_5]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_keeper_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_keeper_en_5_wd), + .d (hw2reg.dio_pad_attr[5].keeper_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[4]), + .q (reg2hw.dio_pad_attr[5].keeper_en.q), + .ds (), + .qs (dio_pad_attr_5_keeper_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].keeper_en.qe = dio_pad_attr_5_qe; + + // F[schmitt_en_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_schmitt_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_schmitt_en_5_wd), + .d (hw2reg.dio_pad_attr[5].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[5]), + .q (reg2hw.dio_pad_attr[5].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_5_schmitt_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].schmitt_en.qe = dio_pad_attr_5_qe; + + // F[od_en_5]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_od_en_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_od_en_5_wd), + .d (hw2reg.dio_pad_attr[5].od_en.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[6]), + .q (reg2hw.dio_pad_attr[5].od_en.q), + .ds (), + .qs (dio_pad_attr_5_od_en_5_qs) + ); + assign reg2hw.dio_pad_attr[5].od_en.qe = dio_pad_attr_5_qe; + + // F[input_disable_5]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_5_input_disable_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_input_disable_5_wd), + .d (hw2reg.dio_pad_attr[5].input_disable.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[7]), + .q (reg2hw.dio_pad_attr[5].input_disable.q), + .ds (), + .qs (dio_pad_attr_5_input_disable_5_qs) + ); + assign reg2hw.dio_pad_attr[5].input_disable.qe = dio_pad_attr_5_qe; + + // F[slew_rate_5]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_5_slew_rate_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_slew_rate_5_wd), + .d (hw2reg.dio_pad_attr[5].slew_rate.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[8]), + .q (reg2hw.dio_pad_attr[5].slew_rate.q), + .ds (), + .qs (dio_pad_attr_5_slew_rate_5_qs) + ); + assign reg2hw.dio_pad_attr[5].slew_rate.qe = dio_pad_attr_5_qe; + + // F[drive_strength_5]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_5_drive_strength_5 ( + .re (dio_pad_attr_5_re), + .we (dio_pad_attr_5_gated_we), + .wd (dio_pad_attr_5_drive_strength_5_wd), + .d (hw2reg.dio_pad_attr[5].drive_strength.d), + .qre (), + .qe (dio_pad_attr_5_flds_we[9]), + .q (reg2hw.dio_pad_attr[5].drive_strength.q), + .ds (), + .qs (dio_pad_attr_5_drive_strength_5_qs) + ); + assign reg2hw.dio_pad_attr[5].drive_strength.qe = dio_pad_attr_5_qe; + + + // Subregister 6 of Multireg dio_pad_attr + // R[dio_pad_attr_6]: V(True) + logic dio_pad_attr_6_qe; + logic [9:0] dio_pad_attr_6_flds_we; + assign dio_pad_attr_6_qe = &dio_pad_attr_6_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_6_gated_we; + assign dio_pad_attr_6_gated_we = dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs; + // F[invert_6]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_invert_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_invert_6_wd), + .d (hw2reg.dio_pad_attr[6].invert.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[0]), + .q (reg2hw.dio_pad_attr[6].invert.q), + .ds (), + .qs (dio_pad_attr_6_invert_6_qs) + ); + assign reg2hw.dio_pad_attr[6].invert.qe = dio_pad_attr_6_qe; + + // F[virtual_od_en_6]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_virtual_od_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_virtual_od_en_6_wd), + .d (hw2reg.dio_pad_attr[6].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[1]), + .q (reg2hw.dio_pad_attr[6].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_6_virtual_od_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].virtual_od_en.qe = dio_pad_attr_6_qe; + + // F[pull_en_6]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_pull_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_pull_en_6_wd), + .d (hw2reg.dio_pad_attr[6].pull_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[2]), + .q (reg2hw.dio_pad_attr[6].pull_en.q), + .ds (), + .qs (dio_pad_attr_6_pull_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].pull_en.qe = dio_pad_attr_6_qe; + + // F[pull_select_6]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_pull_select_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_pull_select_6_wd), + .d (hw2reg.dio_pad_attr[6].pull_select.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[3]), + .q (reg2hw.dio_pad_attr[6].pull_select.q), + .ds (), + .qs (dio_pad_attr_6_pull_select_6_qs) + ); + assign reg2hw.dio_pad_attr[6].pull_select.qe = dio_pad_attr_6_qe; + + // F[keeper_en_6]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_keeper_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_keeper_en_6_wd), + .d (hw2reg.dio_pad_attr[6].keeper_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[4]), + .q (reg2hw.dio_pad_attr[6].keeper_en.q), + .ds (), + .qs (dio_pad_attr_6_keeper_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].keeper_en.qe = dio_pad_attr_6_qe; + + // F[schmitt_en_6]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_schmitt_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_schmitt_en_6_wd), + .d (hw2reg.dio_pad_attr[6].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[5]), + .q (reg2hw.dio_pad_attr[6].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_6_schmitt_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].schmitt_en.qe = dio_pad_attr_6_qe; + + // F[od_en_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_od_en_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_od_en_6_wd), + .d (hw2reg.dio_pad_attr[6].od_en.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[6]), + .q (reg2hw.dio_pad_attr[6].od_en.q), + .ds (), + .qs (dio_pad_attr_6_od_en_6_qs) + ); + assign reg2hw.dio_pad_attr[6].od_en.qe = dio_pad_attr_6_qe; + + // F[input_disable_6]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_6_input_disable_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_input_disable_6_wd), + .d (hw2reg.dio_pad_attr[6].input_disable.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[7]), + .q (reg2hw.dio_pad_attr[6].input_disable.q), + .ds (), + .qs (dio_pad_attr_6_input_disable_6_qs) + ); + assign reg2hw.dio_pad_attr[6].input_disable.qe = dio_pad_attr_6_qe; + + // F[slew_rate_6]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_6_slew_rate_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_slew_rate_6_wd), + .d (hw2reg.dio_pad_attr[6].slew_rate.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[8]), + .q (reg2hw.dio_pad_attr[6].slew_rate.q), + .ds (), + .qs (dio_pad_attr_6_slew_rate_6_qs) + ); + assign reg2hw.dio_pad_attr[6].slew_rate.qe = dio_pad_attr_6_qe; + + // F[drive_strength_6]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_6_drive_strength_6 ( + .re (dio_pad_attr_6_re), + .we (dio_pad_attr_6_gated_we), + .wd (dio_pad_attr_6_drive_strength_6_wd), + .d (hw2reg.dio_pad_attr[6].drive_strength.d), + .qre (), + .qe (dio_pad_attr_6_flds_we[9]), + .q (reg2hw.dio_pad_attr[6].drive_strength.q), + .ds (), + .qs (dio_pad_attr_6_drive_strength_6_qs) + ); + assign reg2hw.dio_pad_attr[6].drive_strength.qe = dio_pad_attr_6_qe; + + + // Subregister 7 of Multireg dio_pad_attr + // R[dio_pad_attr_7]: V(True) + logic dio_pad_attr_7_qe; + logic [9:0] dio_pad_attr_7_flds_we; + assign dio_pad_attr_7_qe = &dio_pad_attr_7_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_7_gated_we; + assign dio_pad_attr_7_gated_we = dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs; + // F[invert_7]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_invert_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_invert_7_wd), + .d (hw2reg.dio_pad_attr[7].invert.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[0]), + .q (reg2hw.dio_pad_attr[7].invert.q), + .ds (), + .qs (dio_pad_attr_7_invert_7_qs) + ); + assign reg2hw.dio_pad_attr[7].invert.qe = dio_pad_attr_7_qe; + + // F[virtual_od_en_7]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_virtual_od_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_virtual_od_en_7_wd), + .d (hw2reg.dio_pad_attr[7].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[1]), + .q (reg2hw.dio_pad_attr[7].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_7_virtual_od_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].virtual_od_en.qe = dio_pad_attr_7_qe; + + // F[pull_en_7]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_pull_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_pull_en_7_wd), + .d (hw2reg.dio_pad_attr[7].pull_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[2]), + .q (reg2hw.dio_pad_attr[7].pull_en.q), + .ds (), + .qs (dio_pad_attr_7_pull_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].pull_en.qe = dio_pad_attr_7_qe; + + // F[pull_select_7]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_pull_select_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_pull_select_7_wd), + .d (hw2reg.dio_pad_attr[7].pull_select.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[3]), + .q (reg2hw.dio_pad_attr[7].pull_select.q), + .ds (), + .qs (dio_pad_attr_7_pull_select_7_qs) + ); + assign reg2hw.dio_pad_attr[7].pull_select.qe = dio_pad_attr_7_qe; + + // F[keeper_en_7]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_keeper_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_keeper_en_7_wd), + .d (hw2reg.dio_pad_attr[7].keeper_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[4]), + .q (reg2hw.dio_pad_attr[7].keeper_en.q), + .ds (), + .qs (dio_pad_attr_7_keeper_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].keeper_en.qe = dio_pad_attr_7_qe; + + // F[schmitt_en_7]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_schmitt_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_schmitt_en_7_wd), + .d (hw2reg.dio_pad_attr[7].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[5]), + .q (reg2hw.dio_pad_attr[7].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_7_schmitt_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].schmitt_en.qe = dio_pad_attr_7_qe; + + // F[od_en_7]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_od_en_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_od_en_7_wd), + .d (hw2reg.dio_pad_attr[7].od_en.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[6]), + .q (reg2hw.dio_pad_attr[7].od_en.q), + .ds (), + .qs (dio_pad_attr_7_od_en_7_qs) + ); + assign reg2hw.dio_pad_attr[7].od_en.qe = dio_pad_attr_7_qe; + + // F[input_disable_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_7_input_disable_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_input_disable_7_wd), + .d (hw2reg.dio_pad_attr[7].input_disable.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[7]), + .q (reg2hw.dio_pad_attr[7].input_disable.q), + .ds (), + .qs (dio_pad_attr_7_input_disable_7_qs) + ); + assign reg2hw.dio_pad_attr[7].input_disable.qe = dio_pad_attr_7_qe; + + // F[slew_rate_7]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_7_slew_rate_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_slew_rate_7_wd), + .d (hw2reg.dio_pad_attr[7].slew_rate.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[8]), + .q (reg2hw.dio_pad_attr[7].slew_rate.q), + .ds (), + .qs (dio_pad_attr_7_slew_rate_7_qs) + ); + assign reg2hw.dio_pad_attr[7].slew_rate.qe = dio_pad_attr_7_qe; + + // F[drive_strength_7]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_7_drive_strength_7 ( + .re (dio_pad_attr_7_re), + .we (dio_pad_attr_7_gated_we), + .wd (dio_pad_attr_7_drive_strength_7_wd), + .d (hw2reg.dio_pad_attr[7].drive_strength.d), + .qre (), + .qe (dio_pad_attr_7_flds_we[9]), + .q (reg2hw.dio_pad_attr[7].drive_strength.q), + .ds (), + .qs (dio_pad_attr_7_drive_strength_7_qs) + ); + assign reg2hw.dio_pad_attr[7].drive_strength.qe = dio_pad_attr_7_qe; + + + // Subregister 8 of Multireg dio_pad_attr + // R[dio_pad_attr_8]: V(True) + logic dio_pad_attr_8_qe; + logic [9:0] dio_pad_attr_8_flds_we; + assign dio_pad_attr_8_qe = &dio_pad_attr_8_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_8_gated_we; + assign dio_pad_attr_8_gated_we = dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs; + // F[invert_8]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_invert_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_invert_8_wd), + .d (hw2reg.dio_pad_attr[8].invert.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[0]), + .q (reg2hw.dio_pad_attr[8].invert.q), + .ds (), + .qs (dio_pad_attr_8_invert_8_qs) + ); + assign reg2hw.dio_pad_attr[8].invert.qe = dio_pad_attr_8_qe; + + // F[virtual_od_en_8]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_virtual_od_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_virtual_od_en_8_wd), + .d (hw2reg.dio_pad_attr[8].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[1]), + .q (reg2hw.dio_pad_attr[8].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_8_virtual_od_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].virtual_od_en.qe = dio_pad_attr_8_qe; + + // F[pull_en_8]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_pull_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_pull_en_8_wd), + .d (hw2reg.dio_pad_attr[8].pull_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[2]), + .q (reg2hw.dio_pad_attr[8].pull_en.q), + .ds (), + .qs (dio_pad_attr_8_pull_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].pull_en.qe = dio_pad_attr_8_qe; + + // F[pull_select_8]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_pull_select_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_pull_select_8_wd), + .d (hw2reg.dio_pad_attr[8].pull_select.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[3]), + .q (reg2hw.dio_pad_attr[8].pull_select.q), + .ds (), + .qs (dio_pad_attr_8_pull_select_8_qs) + ); + assign reg2hw.dio_pad_attr[8].pull_select.qe = dio_pad_attr_8_qe; + + // F[keeper_en_8]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_keeper_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_keeper_en_8_wd), + .d (hw2reg.dio_pad_attr[8].keeper_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[4]), + .q (reg2hw.dio_pad_attr[8].keeper_en.q), + .ds (), + .qs (dio_pad_attr_8_keeper_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].keeper_en.qe = dio_pad_attr_8_qe; + + // F[schmitt_en_8]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_schmitt_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_schmitt_en_8_wd), + .d (hw2reg.dio_pad_attr[8].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[5]), + .q (reg2hw.dio_pad_attr[8].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_8_schmitt_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].schmitt_en.qe = dio_pad_attr_8_qe; + + // F[od_en_8]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_od_en_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_od_en_8_wd), + .d (hw2reg.dio_pad_attr[8].od_en.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[6]), + .q (reg2hw.dio_pad_attr[8].od_en.q), + .ds (), + .qs (dio_pad_attr_8_od_en_8_qs) + ); + assign reg2hw.dio_pad_attr[8].od_en.qe = dio_pad_attr_8_qe; + + // F[input_disable_8]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_8_input_disable_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_input_disable_8_wd), + .d (hw2reg.dio_pad_attr[8].input_disable.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[7]), + .q (reg2hw.dio_pad_attr[8].input_disable.q), + .ds (), + .qs (dio_pad_attr_8_input_disable_8_qs) + ); + assign reg2hw.dio_pad_attr[8].input_disable.qe = dio_pad_attr_8_qe; + + // F[slew_rate_8]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_8_slew_rate_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_slew_rate_8_wd), + .d (hw2reg.dio_pad_attr[8].slew_rate.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[8]), + .q (reg2hw.dio_pad_attr[8].slew_rate.q), + .ds (), + .qs (dio_pad_attr_8_slew_rate_8_qs) + ); + assign reg2hw.dio_pad_attr[8].slew_rate.qe = dio_pad_attr_8_qe; + + // F[drive_strength_8]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_8_drive_strength_8 ( + .re (dio_pad_attr_8_re), + .we (dio_pad_attr_8_gated_we), + .wd (dio_pad_attr_8_drive_strength_8_wd), + .d (hw2reg.dio_pad_attr[8].drive_strength.d), + .qre (), + .qe (dio_pad_attr_8_flds_we[9]), + .q (reg2hw.dio_pad_attr[8].drive_strength.q), + .ds (), + .qs (dio_pad_attr_8_drive_strength_8_qs) + ); + assign reg2hw.dio_pad_attr[8].drive_strength.qe = dio_pad_attr_8_qe; + + + // Subregister 9 of Multireg dio_pad_attr + // R[dio_pad_attr_9]: V(True) + logic dio_pad_attr_9_qe; + logic [9:0] dio_pad_attr_9_flds_we; + assign dio_pad_attr_9_qe = &dio_pad_attr_9_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_9_gated_we; + assign dio_pad_attr_9_gated_we = dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs; + // F[invert_9]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_invert_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_invert_9_wd), + .d (hw2reg.dio_pad_attr[9].invert.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[0]), + .q (reg2hw.dio_pad_attr[9].invert.q), + .ds (), + .qs (dio_pad_attr_9_invert_9_qs) + ); + assign reg2hw.dio_pad_attr[9].invert.qe = dio_pad_attr_9_qe; + + // F[virtual_od_en_9]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_virtual_od_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_virtual_od_en_9_wd), + .d (hw2reg.dio_pad_attr[9].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[1]), + .q (reg2hw.dio_pad_attr[9].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_9_virtual_od_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].virtual_od_en.qe = dio_pad_attr_9_qe; + + // F[pull_en_9]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_pull_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_pull_en_9_wd), + .d (hw2reg.dio_pad_attr[9].pull_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[2]), + .q (reg2hw.dio_pad_attr[9].pull_en.q), + .ds (), + .qs (dio_pad_attr_9_pull_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].pull_en.qe = dio_pad_attr_9_qe; + + // F[pull_select_9]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_pull_select_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_pull_select_9_wd), + .d (hw2reg.dio_pad_attr[9].pull_select.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[3]), + .q (reg2hw.dio_pad_attr[9].pull_select.q), + .ds (), + .qs (dio_pad_attr_9_pull_select_9_qs) + ); + assign reg2hw.dio_pad_attr[9].pull_select.qe = dio_pad_attr_9_qe; + + // F[keeper_en_9]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_keeper_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_keeper_en_9_wd), + .d (hw2reg.dio_pad_attr[9].keeper_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[4]), + .q (reg2hw.dio_pad_attr[9].keeper_en.q), + .ds (), + .qs (dio_pad_attr_9_keeper_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].keeper_en.qe = dio_pad_attr_9_qe; + + // F[schmitt_en_9]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_schmitt_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_schmitt_en_9_wd), + .d (hw2reg.dio_pad_attr[9].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[5]), + .q (reg2hw.dio_pad_attr[9].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_9_schmitt_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].schmitt_en.qe = dio_pad_attr_9_qe; + + // F[od_en_9]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_od_en_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_od_en_9_wd), + .d (hw2reg.dio_pad_attr[9].od_en.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[6]), + .q (reg2hw.dio_pad_attr[9].od_en.q), + .ds (), + .qs (dio_pad_attr_9_od_en_9_qs) + ); + assign reg2hw.dio_pad_attr[9].od_en.qe = dio_pad_attr_9_qe; + + // F[input_disable_9]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_9_input_disable_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_input_disable_9_wd), + .d (hw2reg.dio_pad_attr[9].input_disable.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[7]), + .q (reg2hw.dio_pad_attr[9].input_disable.q), + .ds (), + .qs (dio_pad_attr_9_input_disable_9_qs) + ); + assign reg2hw.dio_pad_attr[9].input_disable.qe = dio_pad_attr_9_qe; + + // F[slew_rate_9]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_9_slew_rate_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_slew_rate_9_wd), + .d (hw2reg.dio_pad_attr[9].slew_rate.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[8]), + .q (reg2hw.dio_pad_attr[9].slew_rate.q), + .ds (), + .qs (dio_pad_attr_9_slew_rate_9_qs) + ); + assign reg2hw.dio_pad_attr[9].slew_rate.qe = dio_pad_attr_9_qe; + + // F[drive_strength_9]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_9_drive_strength_9 ( + .re (dio_pad_attr_9_re), + .we (dio_pad_attr_9_gated_we), + .wd (dio_pad_attr_9_drive_strength_9_wd), + .d (hw2reg.dio_pad_attr[9].drive_strength.d), + .qre (), + .qe (dio_pad_attr_9_flds_we[9]), + .q (reg2hw.dio_pad_attr[9].drive_strength.q), + .ds (), + .qs (dio_pad_attr_9_drive_strength_9_qs) + ); + assign reg2hw.dio_pad_attr[9].drive_strength.qe = dio_pad_attr_9_qe; + + + // Subregister 10 of Multireg dio_pad_attr + // R[dio_pad_attr_10]: V(True) + logic dio_pad_attr_10_qe; + logic [9:0] dio_pad_attr_10_flds_we; + assign dio_pad_attr_10_qe = &dio_pad_attr_10_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_10_gated_we; + assign dio_pad_attr_10_gated_we = dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs; + // F[invert_10]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_invert_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_invert_10_wd), + .d (hw2reg.dio_pad_attr[10].invert.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[0]), + .q (reg2hw.dio_pad_attr[10].invert.q), + .ds (), + .qs (dio_pad_attr_10_invert_10_qs) + ); + assign reg2hw.dio_pad_attr[10].invert.qe = dio_pad_attr_10_qe; + + // F[virtual_od_en_10]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_virtual_od_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_virtual_od_en_10_wd), + .d (hw2reg.dio_pad_attr[10].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[1]), + .q (reg2hw.dio_pad_attr[10].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_10_virtual_od_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].virtual_od_en.qe = dio_pad_attr_10_qe; + + // F[pull_en_10]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_pull_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_pull_en_10_wd), + .d (hw2reg.dio_pad_attr[10].pull_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[2]), + .q (reg2hw.dio_pad_attr[10].pull_en.q), + .ds (), + .qs (dio_pad_attr_10_pull_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].pull_en.qe = dio_pad_attr_10_qe; + + // F[pull_select_10]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_pull_select_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_pull_select_10_wd), + .d (hw2reg.dio_pad_attr[10].pull_select.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[3]), + .q (reg2hw.dio_pad_attr[10].pull_select.q), + .ds (), + .qs (dio_pad_attr_10_pull_select_10_qs) + ); + assign reg2hw.dio_pad_attr[10].pull_select.qe = dio_pad_attr_10_qe; + + // F[keeper_en_10]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_keeper_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_keeper_en_10_wd), + .d (hw2reg.dio_pad_attr[10].keeper_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[4]), + .q (reg2hw.dio_pad_attr[10].keeper_en.q), + .ds (), + .qs (dio_pad_attr_10_keeper_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].keeper_en.qe = dio_pad_attr_10_qe; + + // F[schmitt_en_10]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_schmitt_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_schmitt_en_10_wd), + .d (hw2reg.dio_pad_attr[10].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[5]), + .q (reg2hw.dio_pad_attr[10].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_10_schmitt_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].schmitt_en.qe = dio_pad_attr_10_qe; + + // F[od_en_10]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_od_en_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_od_en_10_wd), + .d (hw2reg.dio_pad_attr[10].od_en.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[6]), + .q (reg2hw.dio_pad_attr[10].od_en.q), + .ds (), + .qs (dio_pad_attr_10_od_en_10_qs) + ); + assign reg2hw.dio_pad_attr[10].od_en.qe = dio_pad_attr_10_qe; + + // F[input_disable_10]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_10_input_disable_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_input_disable_10_wd), + .d (hw2reg.dio_pad_attr[10].input_disable.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[7]), + .q (reg2hw.dio_pad_attr[10].input_disable.q), + .ds (), + .qs (dio_pad_attr_10_input_disable_10_qs) + ); + assign reg2hw.dio_pad_attr[10].input_disable.qe = dio_pad_attr_10_qe; + + // F[slew_rate_10]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_10_slew_rate_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_slew_rate_10_wd), + .d (hw2reg.dio_pad_attr[10].slew_rate.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[8]), + .q (reg2hw.dio_pad_attr[10].slew_rate.q), + .ds (), + .qs (dio_pad_attr_10_slew_rate_10_qs) + ); + assign reg2hw.dio_pad_attr[10].slew_rate.qe = dio_pad_attr_10_qe; + + // F[drive_strength_10]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_10_drive_strength_10 ( + .re (dio_pad_attr_10_re), + .we (dio_pad_attr_10_gated_we), + .wd (dio_pad_attr_10_drive_strength_10_wd), + .d (hw2reg.dio_pad_attr[10].drive_strength.d), + .qre (), + .qe (dio_pad_attr_10_flds_we[9]), + .q (reg2hw.dio_pad_attr[10].drive_strength.q), + .ds (), + .qs (dio_pad_attr_10_drive_strength_10_qs) + ); + assign reg2hw.dio_pad_attr[10].drive_strength.qe = dio_pad_attr_10_qe; + + + // Subregister 11 of Multireg dio_pad_attr + // R[dio_pad_attr_11]: V(True) + logic dio_pad_attr_11_qe; + logic [9:0] dio_pad_attr_11_flds_we; + assign dio_pad_attr_11_qe = &dio_pad_attr_11_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_11_gated_we; + assign dio_pad_attr_11_gated_we = dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs; + // F[invert_11]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_invert_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_invert_11_wd), + .d (hw2reg.dio_pad_attr[11].invert.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[0]), + .q (reg2hw.dio_pad_attr[11].invert.q), + .ds (), + .qs (dio_pad_attr_11_invert_11_qs) + ); + assign reg2hw.dio_pad_attr[11].invert.qe = dio_pad_attr_11_qe; + + // F[virtual_od_en_11]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_virtual_od_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_virtual_od_en_11_wd), + .d (hw2reg.dio_pad_attr[11].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[1]), + .q (reg2hw.dio_pad_attr[11].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_11_virtual_od_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].virtual_od_en.qe = dio_pad_attr_11_qe; + + // F[pull_en_11]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_pull_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_pull_en_11_wd), + .d (hw2reg.dio_pad_attr[11].pull_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[2]), + .q (reg2hw.dio_pad_attr[11].pull_en.q), + .ds (), + .qs (dio_pad_attr_11_pull_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].pull_en.qe = dio_pad_attr_11_qe; + + // F[pull_select_11]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_pull_select_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_pull_select_11_wd), + .d (hw2reg.dio_pad_attr[11].pull_select.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[3]), + .q (reg2hw.dio_pad_attr[11].pull_select.q), + .ds (), + .qs (dio_pad_attr_11_pull_select_11_qs) + ); + assign reg2hw.dio_pad_attr[11].pull_select.qe = dio_pad_attr_11_qe; + + // F[keeper_en_11]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_keeper_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_keeper_en_11_wd), + .d (hw2reg.dio_pad_attr[11].keeper_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[4]), + .q (reg2hw.dio_pad_attr[11].keeper_en.q), + .ds (), + .qs (dio_pad_attr_11_keeper_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].keeper_en.qe = dio_pad_attr_11_qe; + + // F[schmitt_en_11]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_schmitt_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_schmitt_en_11_wd), + .d (hw2reg.dio_pad_attr[11].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[5]), + .q (reg2hw.dio_pad_attr[11].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_11_schmitt_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].schmitt_en.qe = dio_pad_attr_11_qe; + + // F[od_en_11]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_od_en_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_od_en_11_wd), + .d (hw2reg.dio_pad_attr[11].od_en.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[6]), + .q (reg2hw.dio_pad_attr[11].od_en.q), + .ds (), + .qs (dio_pad_attr_11_od_en_11_qs) + ); + assign reg2hw.dio_pad_attr[11].od_en.qe = dio_pad_attr_11_qe; + + // F[input_disable_11]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_11_input_disable_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_input_disable_11_wd), + .d (hw2reg.dio_pad_attr[11].input_disable.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[7]), + .q (reg2hw.dio_pad_attr[11].input_disable.q), + .ds (), + .qs (dio_pad_attr_11_input_disable_11_qs) + ); + assign reg2hw.dio_pad_attr[11].input_disable.qe = dio_pad_attr_11_qe; + + // F[slew_rate_11]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_11_slew_rate_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_slew_rate_11_wd), + .d (hw2reg.dio_pad_attr[11].slew_rate.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[8]), + .q (reg2hw.dio_pad_attr[11].slew_rate.q), + .ds (), + .qs (dio_pad_attr_11_slew_rate_11_qs) + ); + assign reg2hw.dio_pad_attr[11].slew_rate.qe = dio_pad_attr_11_qe; + + // F[drive_strength_11]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_11_drive_strength_11 ( + .re (dio_pad_attr_11_re), + .we (dio_pad_attr_11_gated_we), + .wd (dio_pad_attr_11_drive_strength_11_wd), + .d (hw2reg.dio_pad_attr[11].drive_strength.d), + .qre (), + .qe (dio_pad_attr_11_flds_we[9]), + .q (reg2hw.dio_pad_attr[11].drive_strength.q), + .ds (), + .qs (dio_pad_attr_11_drive_strength_11_qs) + ); + assign reg2hw.dio_pad_attr[11].drive_strength.qe = dio_pad_attr_11_qe; + + + // Subregister 12 of Multireg dio_pad_attr + // R[dio_pad_attr_12]: V(True) + logic dio_pad_attr_12_qe; + logic [9:0] dio_pad_attr_12_flds_we; + assign dio_pad_attr_12_qe = &dio_pad_attr_12_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_12_gated_we; + assign dio_pad_attr_12_gated_we = dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs; + // F[invert_12]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_invert_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_invert_12_wd), + .d (hw2reg.dio_pad_attr[12].invert.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[0]), + .q (reg2hw.dio_pad_attr[12].invert.q), + .ds (), + .qs (dio_pad_attr_12_invert_12_qs) + ); + assign reg2hw.dio_pad_attr[12].invert.qe = dio_pad_attr_12_qe; + + // F[virtual_od_en_12]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_virtual_od_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_virtual_od_en_12_wd), + .d (hw2reg.dio_pad_attr[12].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[1]), + .q (reg2hw.dio_pad_attr[12].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_12_virtual_od_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].virtual_od_en.qe = dio_pad_attr_12_qe; + + // F[pull_en_12]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_pull_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_pull_en_12_wd), + .d (hw2reg.dio_pad_attr[12].pull_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[2]), + .q (reg2hw.dio_pad_attr[12].pull_en.q), + .ds (), + .qs (dio_pad_attr_12_pull_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].pull_en.qe = dio_pad_attr_12_qe; + + // F[pull_select_12]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_pull_select_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_pull_select_12_wd), + .d (hw2reg.dio_pad_attr[12].pull_select.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[3]), + .q (reg2hw.dio_pad_attr[12].pull_select.q), + .ds (), + .qs (dio_pad_attr_12_pull_select_12_qs) + ); + assign reg2hw.dio_pad_attr[12].pull_select.qe = dio_pad_attr_12_qe; + + // F[keeper_en_12]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_keeper_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_keeper_en_12_wd), + .d (hw2reg.dio_pad_attr[12].keeper_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[4]), + .q (reg2hw.dio_pad_attr[12].keeper_en.q), + .ds (), + .qs (dio_pad_attr_12_keeper_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].keeper_en.qe = dio_pad_attr_12_qe; + + // F[schmitt_en_12]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_schmitt_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_schmitt_en_12_wd), + .d (hw2reg.dio_pad_attr[12].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[5]), + .q (reg2hw.dio_pad_attr[12].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_12_schmitt_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].schmitt_en.qe = dio_pad_attr_12_qe; + + // F[od_en_12]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_od_en_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_od_en_12_wd), + .d (hw2reg.dio_pad_attr[12].od_en.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[6]), + .q (reg2hw.dio_pad_attr[12].od_en.q), + .ds (), + .qs (dio_pad_attr_12_od_en_12_qs) + ); + assign reg2hw.dio_pad_attr[12].od_en.qe = dio_pad_attr_12_qe; + + // F[input_disable_12]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_12_input_disable_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_input_disable_12_wd), + .d (hw2reg.dio_pad_attr[12].input_disable.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[7]), + .q (reg2hw.dio_pad_attr[12].input_disable.q), + .ds (), + .qs (dio_pad_attr_12_input_disable_12_qs) + ); + assign reg2hw.dio_pad_attr[12].input_disable.qe = dio_pad_attr_12_qe; + + // F[slew_rate_12]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_12_slew_rate_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_slew_rate_12_wd), + .d (hw2reg.dio_pad_attr[12].slew_rate.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[8]), + .q (reg2hw.dio_pad_attr[12].slew_rate.q), + .ds (), + .qs (dio_pad_attr_12_slew_rate_12_qs) + ); + assign reg2hw.dio_pad_attr[12].slew_rate.qe = dio_pad_attr_12_qe; + + // F[drive_strength_12]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_12_drive_strength_12 ( + .re (dio_pad_attr_12_re), + .we (dio_pad_attr_12_gated_we), + .wd (dio_pad_attr_12_drive_strength_12_wd), + .d (hw2reg.dio_pad_attr[12].drive_strength.d), + .qre (), + .qe (dio_pad_attr_12_flds_we[9]), + .q (reg2hw.dio_pad_attr[12].drive_strength.q), + .ds (), + .qs (dio_pad_attr_12_drive_strength_12_qs) + ); + assign reg2hw.dio_pad_attr[12].drive_strength.qe = dio_pad_attr_12_qe; + + + // Subregister 13 of Multireg dio_pad_attr + // R[dio_pad_attr_13]: V(True) + logic dio_pad_attr_13_qe; + logic [9:0] dio_pad_attr_13_flds_we; + assign dio_pad_attr_13_qe = &dio_pad_attr_13_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_13_gated_we; + assign dio_pad_attr_13_gated_we = dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs; + // F[invert_13]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_invert_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_invert_13_wd), + .d (hw2reg.dio_pad_attr[13].invert.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[0]), + .q (reg2hw.dio_pad_attr[13].invert.q), + .ds (), + .qs (dio_pad_attr_13_invert_13_qs) + ); + assign reg2hw.dio_pad_attr[13].invert.qe = dio_pad_attr_13_qe; + + // F[virtual_od_en_13]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_virtual_od_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_virtual_od_en_13_wd), + .d (hw2reg.dio_pad_attr[13].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[1]), + .q (reg2hw.dio_pad_attr[13].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_13_virtual_od_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].virtual_od_en.qe = dio_pad_attr_13_qe; + + // F[pull_en_13]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_pull_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_pull_en_13_wd), + .d (hw2reg.dio_pad_attr[13].pull_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[2]), + .q (reg2hw.dio_pad_attr[13].pull_en.q), + .ds (), + .qs (dio_pad_attr_13_pull_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].pull_en.qe = dio_pad_attr_13_qe; + + // F[pull_select_13]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_pull_select_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_pull_select_13_wd), + .d (hw2reg.dio_pad_attr[13].pull_select.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[3]), + .q (reg2hw.dio_pad_attr[13].pull_select.q), + .ds (), + .qs (dio_pad_attr_13_pull_select_13_qs) + ); + assign reg2hw.dio_pad_attr[13].pull_select.qe = dio_pad_attr_13_qe; + + // F[keeper_en_13]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_keeper_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_keeper_en_13_wd), + .d (hw2reg.dio_pad_attr[13].keeper_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[4]), + .q (reg2hw.dio_pad_attr[13].keeper_en.q), + .ds (), + .qs (dio_pad_attr_13_keeper_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].keeper_en.qe = dio_pad_attr_13_qe; + + // F[schmitt_en_13]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_schmitt_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_schmitt_en_13_wd), + .d (hw2reg.dio_pad_attr[13].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[5]), + .q (reg2hw.dio_pad_attr[13].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_13_schmitt_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].schmitt_en.qe = dio_pad_attr_13_qe; + + // F[od_en_13]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_od_en_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_od_en_13_wd), + .d (hw2reg.dio_pad_attr[13].od_en.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[6]), + .q (reg2hw.dio_pad_attr[13].od_en.q), + .ds (), + .qs (dio_pad_attr_13_od_en_13_qs) + ); + assign reg2hw.dio_pad_attr[13].od_en.qe = dio_pad_attr_13_qe; + + // F[input_disable_13]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_13_input_disable_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_input_disable_13_wd), + .d (hw2reg.dio_pad_attr[13].input_disable.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[7]), + .q (reg2hw.dio_pad_attr[13].input_disable.q), + .ds (), + .qs (dio_pad_attr_13_input_disable_13_qs) + ); + assign reg2hw.dio_pad_attr[13].input_disable.qe = dio_pad_attr_13_qe; + + // F[slew_rate_13]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_13_slew_rate_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_slew_rate_13_wd), + .d (hw2reg.dio_pad_attr[13].slew_rate.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[8]), + .q (reg2hw.dio_pad_attr[13].slew_rate.q), + .ds (), + .qs (dio_pad_attr_13_slew_rate_13_qs) + ); + assign reg2hw.dio_pad_attr[13].slew_rate.qe = dio_pad_attr_13_qe; + + // F[drive_strength_13]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_13_drive_strength_13 ( + .re (dio_pad_attr_13_re), + .we (dio_pad_attr_13_gated_we), + .wd (dio_pad_attr_13_drive_strength_13_wd), + .d (hw2reg.dio_pad_attr[13].drive_strength.d), + .qre (), + .qe (dio_pad_attr_13_flds_we[9]), + .q (reg2hw.dio_pad_attr[13].drive_strength.q), + .ds (), + .qs (dio_pad_attr_13_drive_strength_13_qs) + ); + assign reg2hw.dio_pad_attr[13].drive_strength.qe = dio_pad_attr_13_qe; + + + // Subregister 14 of Multireg dio_pad_attr + // R[dio_pad_attr_14]: V(True) + logic dio_pad_attr_14_qe; + logic [9:0] dio_pad_attr_14_flds_we; + assign dio_pad_attr_14_qe = &dio_pad_attr_14_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_14_gated_we; + assign dio_pad_attr_14_gated_we = dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs; + // F[invert_14]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_invert_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_invert_14_wd), + .d (hw2reg.dio_pad_attr[14].invert.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[0]), + .q (reg2hw.dio_pad_attr[14].invert.q), + .ds (), + .qs (dio_pad_attr_14_invert_14_qs) + ); + assign reg2hw.dio_pad_attr[14].invert.qe = dio_pad_attr_14_qe; + + // F[virtual_od_en_14]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_virtual_od_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_virtual_od_en_14_wd), + .d (hw2reg.dio_pad_attr[14].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[1]), + .q (reg2hw.dio_pad_attr[14].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_14_virtual_od_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].virtual_od_en.qe = dio_pad_attr_14_qe; + + // F[pull_en_14]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_pull_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_pull_en_14_wd), + .d (hw2reg.dio_pad_attr[14].pull_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[2]), + .q (reg2hw.dio_pad_attr[14].pull_en.q), + .ds (), + .qs (dio_pad_attr_14_pull_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].pull_en.qe = dio_pad_attr_14_qe; + + // F[pull_select_14]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_pull_select_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_pull_select_14_wd), + .d (hw2reg.dio_pad_attr[14].pull_select.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[3]), + .q (reg2hw.dio_pad_attr[14].pull_select.q), + .ds (), + .qs (dio_pad_attr_14_pull_select_14_qs) + ); + assign reg2hw.dio_pad_attr[14].pull_select.qe = dio_pad_attr_14_qe; + + // F[keeper_en_14]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_keeper_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_keeper_en_14_wd), + .d (hw2reg.dio_pad_attr[14].keeper_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[4]), + .q (reg2hw.dio_pad_attr[14].keeper_en.q), + .ds (), + .qs (dio_pad_attr_14_keeper_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].keeper_en.qe = dio_pad_attr_14_qe; + + // F[schmitt_en_14]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_schmitt_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_schmitt_en_14_wd), + .d (hw2reg.dio_pad_attr[14].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[5]), + .q (reg2hw.dio_pad_attr[14].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_14_schmitt_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].schmitt_en.qe = dio_pad_attr_14_qe; + + // F[od_en_14]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_od_en_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_od_en_14_wd), + .d (hw2reg.dio_pad_attr[14].od_en.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[6]), + .q (reg2hw.dio_pad_attr[14].od_en.q), + .ds (), + .qs (dio_pad_attr_14_od_en_14_qs) + ); + assign reg2hw.dio_pad_attr[14].od_en.qe = dio_pad_attr_14_qe; + + // F[input_disable_14]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_14_input_disable_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_input_disable_14_wd), + .d (hw2reg.dio_pad_attr[14].input_disable.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[7]), + .q (reg2hw.dio_pad_attr[14].input_disable.q), + .ds (), + .qs (dio_pad_attr_14_input_disable_14_qs) + ); + assign reg2hw.dio_pad_attr[14].input_disable.qe = dio_pad_attr_14_qe; + + // F[slew_rate_14]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_14_slew_rate_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_slew_rate_14_wd), + .d (hw2reg.dio_pad_attr[14].slew_rate.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[8]), + .q (reg2hw.dio_pad_attr[14].slew_rate.q), + .ds (), + .qs (dio_pad_attr_14_slew_rate_14_qs) + ); + assign reg2hw.dio_pad_attr[14].slew_rate.qe = dio_pad_attr_14_qe; + + // F[drive_strength_14]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_14_drive_strength_14 ( + .re (dio_pad_attr_14_re), + .we (dio_pad_attr_14_gated_we), + .wd (dio_pad_attr_14_drive_strength_14_wd), + .d (hw2reg.dio_pad_attr[14].drive_strength.d), + .qre (), + .qe (dio_pad_attr_14_flds_we[9]), + .q (reg2hw.dio_pad_attr[14].drive_strength.q), + .ds (), + .qs (dio_pad_attr_14_drive_strength_14_qs) + ); + assign reg2hw.dio_pad_attr[14].drive_strength.qe = dio_pad_attr_14_qe; + + + // Subregister 15 of Multireg dio_pad_attr + // R[dio_pad_attr_15]: V(True) + logic dio_pad_attr_15_qe; + logic [9:0] dio_pad_attr_15_flds_we; + assign dio_pad_attr_15_qe = &dio_pad_attr_15_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_15_gated_we; + assign dio_pad_attr_15_gated_we = dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs; + // F[invert_15]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_invert_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_invert_15_wd), + .d (hw2reg.dio_pad_attr[15].invert.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[0]), + .q (reg2hw.dio_pad_attr[15].invert.q), + .ds (), + .qs (dio_pad_attr_15_invert_15_qs) + ); + assign reg2hw.dio_pad_attr[15].invert.qe = dio_pad_attr_15_qe; + + // F[virtual_od_en_15]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_virtual_od_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_virtual_od_en_15_wd), + .d (hw2reg.dio_pad_attr[15].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[1]), + .q (reg2hw.dio_pad_attr[15].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_15_virtual_od_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].virtual_od_en.qe = dio_pad_attr_15_qe; + + // F[pull_en_15]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_pull_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_pull_en_15_wd), + .d (hw2reg.dio_pad_attr[15].pull_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[2]), + .q (reg2hw.dio_pad_attr[15].pull_en.q), + .ds (), + .qs (dio_pad_attr_15_pull_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].pull_en.qe = dio_pad_attr_15_qe; + + // F[pull_select_15]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_pull_select_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_pull_select_15_wd), + .d (hw2reg.dio_pad_attr[15].pull_select.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[3]), + .q (reg2hw.dio_pad_attr[15].pull_select.q), + .ds (), + .qs (dio_pad_attr_15_pull_select_15_qs) + ); + assign reg2hw.dio_pad_attr[15].pull_select.qe = dio_pad_attr_15_qe; + + // F[keeper_en_15]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_keeper_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_keeper_en_15_wd), + .d (hw2reg.dio_pad_attr[15].keeper_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[4]), + .q (reg2hw.dio_pad_attr[15].keeper_en.q), + .ds (), + .qs (dio_pad_attr_15_keeper_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].keeper_en.qe = dio_pad_attr_15_qe; + + // F[schmitt_en_15]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_schmitt_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_schmitt_en_15_wd), + .d (hw2reg.dio_pad_attr[15].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[5]), + .q (reg2hw.dio_pad_attr[15].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_15_schmitt_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].schmitt_en.qe = dio_pad_attr_15_qe; + + // F[od_en_15]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_od_en_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_od_en_15_wd), + .d (hw2reg.dio_pad_attr[15].od_en.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[6]), + .q (reg2hw.dio_pad_attr[15].od_en.q), + .ds (), + .qs (dio_pad_attr_15_od_en_15_qs) + ); + assign reg2hw.dio_pad_attr[15].od_en.qe = dio_pad_attr_15_qe; + + // F[input_disable_15]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_15_input_disable_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_input_disable_15_wd), + .d (hw2reg.dio_pad_attr[15].input_disable.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[7]), + .q (reg2hw.dio_pad_attr[15].input_disable.q), + .ds (), + .qs (dio_pad_attr_15_input_disable_15_qs) + ); + assign reg2hw.dio_pad_attr[15].input_disable.qe = dio_pad_attr_15_qe; + + // F[slew_rate_15]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_15_slew_rate_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_slew_rate_15_wd), + .d (hw2reg.dio_pad_attr[15].slew_rate.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[8]), + .q (reg2hw.dio_pad_attr[15].slew_rate.q), + .ds (), + .qs (dio_pad_attr_15_slew_rate_15_qs) + ); + assign reg2hw.dio_pad_attr[15].slew_rate.qe = dio_pad_attr_15_qe; + + // F[drive_strength_15]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_15_drive_strength_15 ( + .re (dio_pad_attr_15_re), + .we (dio_pad_attr_15_gated_we), + .wd (dio_pad_attr_15_drive_strength_15_wd), + .d (hw2reg.dio_pad_attr[15].drive_strength.d), + .qre (), + .qe (dio_pad_attr_15_flds_we[9]), + .q (reg2hw.dio_pad_attr[15].drive_strength.q), + .ds (), + .qs (dio_pad_attr_15_drive_strength_15_qs) + ); + assign reg2hw.dio_pad_attr[15].drive_strength.qe = dio_pad_attr_15_qe; + + + // Subregister 16 of Multireg dio_pad_attr + // R[dio_pad_attr_16]: V(True) + logic dio_pad_attr_16_qe; + logic [9:0] dio_pad_attr_16_flds_we; + assign dio_pad_attr_16_qe = &dio_pad_attr_16_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_16_gated_we; + assign dio_pad_attr_16_gated_we = dio_pad_attr_16_we & dio_pad_attr_regwen_16_qs; + // F[invert_16]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_invert_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_invert_16_wd), + .d (hw2reg.dio_pad_attr[16].invert.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[0]), + .q (reg2hw.dio_pad_attr[16].invert.q), + .ds (), + .qs (dio_pad_attr_16_invert_16_qs) + ); + assign reg2hw.dio_pad_attr[16].invert.qe = dio_pad_attr_16_qe; + + // F[virtual_od_en_16]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_virtual_od_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_virtual_od_en_16_wd), + .d (hw2reg.dio_pad_attr[16].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[1]), + .q (reg2hw.dio_pad_attr[16].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_16_virtual_od_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].virtual_od_en.qe = dio_pad_attr_16_qe; + + // F[pull_en_16]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_pull_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_pull_en_16_wd), + .d (hw2reg.dio_pad_attr[16].pull_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[2]), + .q (reg2hw.dio_pad_attr[16].pull_en.q), + .ds (), + .qs (dio_pad_attr_16_pull_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].pull_en.qe = dio_pad_attr_16_qe; + + // F[pull_select_16]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_pull_select_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_pull_select_16_wd), + .d (hw2reg.dio_pad_attr[16].pull_select.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[3]), + .q (reg2hw.dio_pad_attr[16].pull_select.q), + .ds (), + .qs (dio_pad_attr_16_pull_select_16_qs) + ); + assign reg2hw.dio_pad_attr[16].pull_select.qe = dio_pad_attr_16_qe; + + // F[keeper_en_16]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_keeper_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_keeper_en_16_wd), + .d (hw2reg.dio_pad_attr[16].keeper_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[4]), + .q (reg2hw.dio_pad_attr[16].keeper_en.q), + .ds (), + .qs (dio_pad_attr_16_keeper_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].keeper_en.qe = dio_pad_attr_16_qe; + + // F[schmitt_en_16]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_schmitt_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_schmitt_en_16_wd), + .d (hw2reg.dio_pad_attr[16].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[5]), + .q (reg2hw.dio_pad_attr[16].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_16_schmitt_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].schmitt_en.qe = dio_pad_attr_16_qe; + + // F[od_en_16]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_od_en_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_od_en_16_wd), + .d (hw2reg.dio_pad_attr[16].od_en.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[6]), + .q (reg2hw.dio_pad_attr[16].od_en.q), + .ds (), + .qs (dio_pad_attr_16_od_en_16_qs) + ); + assign reg2hw.dio_pad_attr[16].od_en.qe = dio_pad_attr_16_qe; + + // F[input_disable_16]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_16_input_disable_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_input_disable_16_wd), + .d (hw2reg.dio_pad_attr[16].input_disable.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[7]), + .q (reg2hw.dio_pad_attr[16].input_disable.q), + .ds (), + .qs (dio_pad_attr_16_input_disable_16_qs) + ); + assign reg2hw.dio_pad_attr[16].input_disable.qe = dio_pad_attr_16_qe; + + // F[slew_rate_16]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_16_slew_rate_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_slew_rate_16_wd), + .d (hw2reg.dio_pad_attr[16].slew_rate.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[8]), + .q (reg2hw.dio_pad_attr[16].slew_rate.q), + .ds (), + .qs (dio_pad_attr_16_slew_rate_16_qs) + ); + assign reg2hw.dio_pad_attr[16].slew_rate.qe = dio_pad_attr_16_qe; + + // F[drive_strength_16]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_16_drive_strength_16 ( + .re (dio_pad_attr_16_re), + .we (dio_pad_attr_16_gated_we), + .wd (dio_pad_attr_16_drive_strength_16_wd), + .d (hw2reg.dio_pad_attr[16].drive_strength.d), + .qre (), + .qe (dio_pad_attr_16_flds_we[9]), + .q (reg2hw.dio_pad_attr[16].drive_strength.q), + .ds (), + .qs (dio_pad_attr_16_drive_strength_16_qs) + ); + assign reg2hw.dio_pad_attr[16].drive_strength.qe = dio_pad_attr_16_qe; + + + // Subregister 17 of Multireg dio_pad_attr + // R[dio_pad_attr_17]: V(True) + logic dio_pad_attr_17_qe; + logic [9:0] dio_pad_attr_17_flds_we; + assign dio_pad_attr_17_qe = &dio_pad_attr_17_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_17_gated_we; + assign dio_pad_attr_17_gated_we = dio_pad_attr_17_we & dio_pad_attr_regwen_17_qs; + // F[invert_17]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_invert_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_invert_17_wd), + .d (hw2reg.dio_pad_attr[17].invert.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[0]), + .q (reg2hw.dio_pad_attr[17].invert.q), + .ds (), + .qs (dio_pad_attr_17_invert_17_qs) + ); + assign reg2hw.dio_pad_attr[17].invert.qe = dio_pad_attr_17_qe; + + // F[virtual_od_en_17]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_virtual_od_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_virtual_od_en_17_wd), + .d (hw2reg.dio_pad_attr[17].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[1]), + .q (reg2hw.dio_pad_attr[17].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_17_virtual_od_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].virtual_od_en.qe = dio_pad_attr_17_qe; + + // F[pull_en_17]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_pull_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_pull_en_17_wd), + .d (hw2reg.dio_pad_attr[17].pull_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[2]), + .q (reg2hw.dio_pad_attr[17].pull_en.q), + .ds (), + .qs (dio_pad_attr_17_pull_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].pull_en.qe = dio_pad_attr_17_qe; + + // F[pull_select_17]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_pull_select_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_pull_select_17_wd), + .d (hw2reg.dio_pad_attr[17].pull_select.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[3]), + .q (reg2hw.dio_pad_attr[17].pull_select.q), + .ds (), + .qs (dio_pad_attr_17_pull_select_17_qs) + ); + assign reg2hw.dio_pad_attr[17].pull_select.qe = dio_pad_attr_17_qe; + + // F[keeper_en_17]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_keeper_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_keeper_en_17_wd), + .d (hw2reg.dio_pad_attr[17].keeper_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[4]), + .q (reg2hw.dio_pad_attr[17].keeper_en.q), + .ds (), + .qs (dio_pad_attr_17_keeper_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].keeper_en.qe = dio_pad_attr_17_qe; + + // F[schmitt_en_17]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_schmitt_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_schmitt_en_17_wd), + .d (hw2reg.dio_pad_attr[17].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[5]), + .q (reg2hw.dio_pad_attr[17].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_17_schmitt_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].schmitt_en.qe = dio_pad_attr_17_qe; + + // F[od_en_17]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_od_en_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_od_en_17_wd), + .d (hw2reg.dio_pad_attr[17].od_en.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[6]), + .q (reg2hw.dio_pad_attr[17].od_en.q), + .ds (), + .qs (dio_pad_attr_17_od_en_17_qs) + ); + assign reg2hw.dio_pad_attr[17].od_en.qe = dio_pad_attr_17_qe; + + // F[input_disable_17]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_17_input_disable_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_input_disable_17_wd), + .d (hw2reg.dio_pad_attr[17].input_disable.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[7]), + .q (reg2hw.dio_pad_attr[17].input_disable.q), + .ds (), + .qs (dio_pad_attr_17_input_disable_17_qs) + ); + assign reg2hw.dio_pad_attr[17].input_disable.qe = dio_pad_attr_17_qe; + + // F[slew_rate_17]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_17_slew_rate_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_slew_rate_17_wd), + .d (hw2reg.dio_pad_attr[17].slew_rate.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[8]), + .q (reg2hw.dio_pad_attr[17].slew_rate.q), + .ds (), + .qs (dio_pad_attr_17_slew_rate_17_qs) + ); + assign reg2hw.dio_pad_attr[17].slew_rate.qe = dio_pad_attr_17_qe; + + // F[drive_strength_17]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_17_drive_strength_17 ( + .re (dio_pad_attr_17_re), + .we (dio_pad_attr_17_gated_we), + .wd (dio_pad_attr_17_drive_strength_17_wd), + .d (hw2reg.dio_pad_attr[17].drive_strength.d), + .qre (), + .qe (dio_pad_attr_17_flds_we[9]), + .q (reg2hw.dio_pad_attr[17].drive_strength.q), + .ds (), + .qs (dio_pad_attr_17_drive_strength_17_qs) + ); + assign reg2hw.dio_pad_attr[17].drive_strength.qe = dio_pad_attr_17_qe; + + + // Subregister 18 of Multireg dio_pad_attr + // R[dio_pad_attr_18]: V(True) + logic dio_pad_attr_18_qe; + logic [9:0] dio_pad_attr_18_flds_we; + assign dio_pad_attr_18_qe = &dio_pad_attr_18_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_18_gated_we; + assign dio_pad_attr_18_gated_we = dio_pad_attr_18_we & dio_pad_attr_regwen_18_qs; + // F[invert_18]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_invert_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_invert_18_wd), + .d (hw2reg.dio_pad_attr[18].invert.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[0]), + .q (reg2hw.dio_pad_attr[18].invert.q), + .ds (), + .qs (dio_pad_attr_18_invert_18_qs) + ); + assign reg2hw.dio_pad_attr[18].invert.qe = dio_pad_attr_18_qe; + + // F[virtual_od_en_18]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_virtual_od_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_virtual_od_en_18_wd), + .d (hw2reg.dio_pad_attr[18].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[1]), + .q (reg2hw.dio_pad_attr[18].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_18_virtual_od_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].virtual_od_en.qe = dio_pad_attr_18_qe; + + // F[pull_en_18]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_pull_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_pull_en_18_wd), + .d (hw2reg.dio_pad_attr[18].pull_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[2]), + .q (reg2hw.dio_pad_attr[18].pull_en.q), + .ds (), + .qs (dio_pad_attr_18_pull_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].pull_en.qe = dio_pad_attr_18_qe; + + // F[pull_select_18]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_pull_select_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_pull_select_18_wd), + .d (hw2reg.dio_pad_attr[18].pull_select.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[3]), + .q (reg2hw.dio_pad_attr[18].pull_select.q), + .ds (), + .qs (dio_pad_attr_18_pull_select_18_qs) + ); + assign reg2hw.dio_pad_attr[18].pull_select.qe = dio_pad_attr_18_qe; + + // F[keeper_en_18]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_keeper_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_keeper_en_18_wd), + .d (hw2reg.dio_pad_attr[18].keeper_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[4]), + .q (reg2hw.dio_pad_attr[18].keeper_en.q), + .ds (), + .qs (dio_pad_attr_18_keeper_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].keeper_en.qe = dio_pad_attr_18_qe; + + // F[schmitt_en_18]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_schmitt_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_schmitt_en_18_wd), + .d (hw2reg.dio_pad_attr[18].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[5]), + .q (reg2hw.dio_pad_attr[18].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_18_schmitt_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].schmitt_en.qe = dio_pad_attr_18_qe; + + // F[od_en_18]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_od_en_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_od_en_18_wd), + .d (hw2reg.dio_pad_attr[18].od_en.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[6]), + .q (reg2hw.dio_pad_attr[18].od_en.q), + .ds (), + .qs (dio_pad_attr_18_od_en_18_qs) + ); + assign reg2hw.dio_pad_attr[18].od_en.qe = dio_pad_attr_18_qe; + + // F[input_disable_18]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_18_input_disable_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_input_disable_18_wd), + .d (hw2reg.dio_pad_attr[18].input_disable.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[7]), + .q (reg2hw.dio_pad_attr[18].input_disable.q), + .ds (), + .qs (dio_pad_attr_18_input_disable_18_qs) + ); + assign reg2hw.dio_pad_attr[18].input_disable.qe = dio_pad_attr_18_qe; + + // F[slew_rate_18]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_18_slew_rate_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_slew_rate_18_wd), + .d (hw2reg.dio_pad_attr[18].slew_rate.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[8]), + .q (reg2hw.dio_pad_attr[18].slew_rate.q), + .ds (), + .qs (dio_pad_attr_18_slew_rate_18_qs) + ); + assign reg2hw.dio_pad_attr[18].slew_rate.qe = dio_pad_attr_18_qe; + + // F[drive_strength_18]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_18_drive_strength_18 ( + .re (dio_pad_attr_18_re), + .we (dio_pad_attr_18_gated_we), + .wd (dio_pad_attr_18_drive_strength_18_wd), + .d (hw2reg.dio_pad_attr[18].drive_strength.d), + .qre (), + .qe (dio_pad_attr_18_flds_we[9]), + .q (reg2hw.dio_pad_attr[18].drive_strength.q), + .ds (), + .qs (dio_pad_attr_18_drive_strength_18_qs) + ); + assign reg2hw.dio_pad_attr[18].drive_strength.qe = dio_pad_attr_18_qe; + + + // Subregister 19 of Multireg dio_pad_attr + // R[dio_pad_attr_19]: V(True) + logic dio_pad_attr_19_qe; + logic [9:0] dio_pad_attr_19_flds_we; + assign dio_pad_attr_19_qe = &dio_pad_attr_19_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_19_gated_we; + assign dio_pad_attr_19_gated_we = dio_pad_attr_19_we & dio_pad_attr_regwen_19_qs; + // F[invert_19]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_invert_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_invert_19_wd), + .d (hw2reg.dio_pad_attr[19].invert.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[0]), + .q (reg2hw.dio_pad_attr[19].invert.q), + .ds (), + .qs (dio_pad_attr_19_invert_19_qs) + ); + assign reg2hw.dio_pad_attr[19].invert.qe = dio_pad_attr_19_qe; + + // F[virtual_od_en_19]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_virtual_od_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_virtual_od_en_19_wd), + .d (hw2reg.dio_pad_attr[19].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[1]), + .q (reg2hw.dio_pad_attr[19].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_19_virtual_od_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].virtual_od_en.qe = dio_pad_attr_19_qe; + + // F[pull_en_19]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_pull_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_pull_en_19_wd), + .d (hw2reg.dio_pad_attr[19].pull_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[2]), + .q (reg2hw.dio_pad_attr[19].pull_en.q), + .ds (), + .qs (dio_pad_attr_19_pull_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].pull_en.qe = dio_pad_attr_19_qe; + + // F[pull_select_19]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_pull_select_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_pull_select_19_wd), + .d (hw2reg.dio_pad_attr[19].pull_select.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[3]), + .q (reg2hw.dio_pad_attr[19].pull_select.q), + .ds (), + .qs (dio_pad_attr_19_pull_select_19_qs) + ); + assign reg2hw.dio_pad_attr[19].pull_select.qe = dio_pad_attr_19_qe; + + // F[keeper_en_19]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_keeper_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_keeper_en_19_wd), + .d (hw2reg.dio_pad_attr[19].keeper_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[4]), + .q (reg2hw.dio_pad_attr[19].keeper_en.q), + .ds (), + .qs (dio_pad_attr_19_keeper_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].keeper_en.qe = dio_pad_attr_19_qe; + + // F[schmitt_en_19]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_schmitt_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_schmitt_en_19_wd), + .d (hw2reg.dio_pad_attr[19].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[5]), + .q (reg2hw.dio_pad_attr[19].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_19_schmitt_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].schmitt_en.qe = dio_pad_attr_19_qe; + + // F[od_en_19]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_od_en_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_od_en_19_wd), + .d (hw2reg.dio_pad_attr[19].od_en.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[6]), + .q (reg2hw.dio_pad_attr[19].od_en.q), + .ds (), + .qs (dio_pad_attr_19_od_en_19_qs) + ); + assign reg2hw.dio_pad_attr[19].od_en.qe = dio_pad_attr_19_qe; + + // F[input_disable_19]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_19_input_disable_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_input_disable_19_wd), + .d (hw2reg.dio_pad_attr[19].input_disable.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[7]), + .q (reg2hw.dio_pad_attr[19].input_disable.q), + .ds (), + .qs (dio_pad_attr_19_input_disable_19_qs) + ); + assign reg2hw.dio_pad_attr[19].input_disable.qe = dio_pad_attr_19_qe; + + // F[slew_rate_19]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_19_slew_rate_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_slew_rate_19_wd), + .d (hw2reg.dio_pad_attr[19].slew_rate.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[8]), + .q (reg2hw.dio_pad_attr[19].slew_rate.q), + .ds (), + .qs (dio_pad_attr_19_slew_rate_19_qs) + ); + assign reg2hw.dio_pad_attr[19].slew_rate.qe = dio_pad_attr_19_qe; + + // F[drive_strength_19]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_19_drive_strength_19 ( + .re (dio_pad_attr_19_re), + .we (dio_pad_attr_19_gated_we), + .wd (dio_pad_attr_19_drive_strength_19_wd), + .d (hw2reg.dio_pad_attr[19].drive_strength.d), + .qre (), + .qe (dio_pad_attr_19_flds_we[9]), + .q (reg2hw.dio_pad_attr[19].drive_strength.q), + .ds (), + .qs (dio_pad_attr_19_drive_strength_19_qs) + ); + assign reg2hw.dio_pad_attr[19].drive_strength.qe = dio_pad_attr_19_qe; + + + // Subregister 20 of Multireg dio_pad_attr + // R[dio_pad_attr_20]: V(True) + logic dio_pad_attr_20_qe; + logic [9:0] dio_pad_attr_20_flds_we; + assign dio_pad_attr_20_qe = &dio_pad_attr_20_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_20_gated_we; + assign dio_pad_attr_20_gated_we = dio_pad_attr_20_we & dio_pad_attr_regwen_20_qs; + // F[invert_20]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_invert_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_invert_20_wd), + .d (hw2reg.dio_pad_attr[20].invert.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[0]), + .q (reg2hw.dio_pad_attr[20].invert.q), + .ds (), + .qs (dio_pad_attr_20_invert_20_qs) + ); + assign reg2hw.dio_pad_attr[20].invert.qe = dio_pad_attr_20_qe; + + // F[virtual_od_en_20]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_virtual_od_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_virtual_od_en_20_wd), + .d (hw2reg.dio_pad_attr[20].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[1]), + .q (reg2hw.dio_pad_attr[20].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_20_virtual_od_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].virtual_od_en.qe = dio_pad_attr_20_qe; + + // F[pull_en_20]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_pull_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_pull_en_20_wd), + .d (hw2reg.dio_pad_attr[20].pull_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[2]), + .q (reg2hw.dio_pad_attr[20].pull_en.q), + .ds (), + .qs (dio_pad_attr_20_pull_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].pull_en.qe = dio_pad_attr_20_qe; + + // F[pull_select_20]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_pull_select_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_pull_select_20_wd), + .d (hw2reg.dio_pad_attr[20].pull_select.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[3]), + .q (reg2hw.dio_pad_attr[20].pull_select.q), + .ds (), + .qs (dio_pad_attr_20_pull_select_20_qs) + ); + assign reg2hw.dio_pad_attr[20].pull_select.qe = dio_pad_attr_20_qe; + + // F[keeper_en_20]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_keeper_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_keeper_en_20_wd), + .d (hw2reg.dio_pad_attr[20].keeper_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[4]), + .q (reg2hw.dio_pad_attr[20].keeper_en.q), + .ds (), + .qs (dio_pad_attr_20_keeper_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].keeper_en.qe = dio_pad_attr_20_qe; + + // F[schmitt_en_20]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_schmitt_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_schmitt_en_20_wd), + .d (hw2reg.dio_pad_attr[20].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[5]), + .q (reg2hw.dio_pad_attr[20].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_20_schmitt_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].schmitt_en.qe = dio_pad_attr_20_qe; + + // F[od_en_20]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_od_en_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_od_en_20_wd), + .d (hw2reg.dio_pad_attr[20].od_en.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[6]), + .q (reg2hw.dio_pad_attr[20].od_en.q), + .ds (), + .qs (dio_pad_attr_20_od_en_20_qs) + ); + assign reg2hw.dio_pad_attr[20].od_en.qe = dio_pad_attr_20_qe; + + // F[input_disable_20]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_20_input_disable_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_input_disable_20_wd), + .d (hw2reg.dio_pad_attr[20].input_disable.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[7]), + .q (reg2hw.dio_pad_attr[20].input_disable.q), + .ds (), + .qs (dio_pad_attr_20_input_disable_20_qs) + ); + assign reg2hw.dio_pad_attr[20].input_disable.qe = dio_pad_attr_20_qe; + + // F[slew_rate_20]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_20_slew_rate_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_slew_rate_20_wd), + .d (hw2reg.dio_pad_attr[20].slew_rate.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[8]), + .q (reg2hw.dio_pad_attr[20].slew_rate.q), + .ds (), + .qs (dio_pad_attr_20_slew_rate_20_qs) + ); + assign reg2hw.dio_pad_attr[20].slew_rate.qe = dio_pad_attr_20_qe; + + // F[drive_strength_20]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_20_drive_strength_20 ( + .re (dio_pad_attr_20_re), + .we (dio_pad_attr_20_gated_we), + .wd (dio_pad_attr_20_drive_strength_20_wd), + .d (hw2reg.dio_pad_attr[20].drive_strength.d), + .qre (), + .qe (dio_pad_attr_20_flds_we[9]), + .q (reg2hw.dio_pad_attr[20].drive_strength.q), + .ds (), + .qs (dio_pad_attr_20_drive_strength_20_qs) + ); + assign reg2hw.dio_pad_attr[20].drive_strength.qe = dio_pad_attr_20_qe; + + + // Subregister 21 of Multireg dio_pad_attr + // R[dio_pad_attr_21]: V(True) + logic dio_pad_attr_21_qe; + logic [9:0] dio_pad_attr_21_flds_we; + assign dio_pad_attr_21_qe = &dio_pad_attr_21_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_21_gated_we; + assign dio_pad_attr_21_gated_we = dio_pad_attr_21_we & dio_pad_attr_regwen_21_qs; + // F[invert_21]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_invert_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_invert_21_wd), + .d (hw2reg.dio_pad_attr[21].invert.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[0]), + .q (reg2hw.dio_pad_attr[21].invert.q), + .ds (), + .qs (dio_pad_attr_21_invert_21_qs) + ); + assign reg2hw.dio_pad_attr[21].invert.qe = dio_pad_attr_21_qe; + + // F[virtual_od_en_21]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_virtual_od_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_virtual_od_en_21_wd), + .d (hw2reg.dio_pad_attr[21].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[1]), + .q (reg2hw.dio_pad_attr[21].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_21_virtual_od_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].virtual_od_en.qe = dio_pad_attr_21_qe; + + // F[pull_en_21]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_pull_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_pull_en_21_wd), + .d (hw2reg.dio_pad_attr[21].pull_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[2]), + .q (reg2hw.dio_pad_attr[21].pull_en.q), + .ds (), + .qs (dio_pad_attr_21_pull_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].pull_en.qe = dio_pad_attr_21_qe; + + // F[pull_select_21]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_pull_select_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_pull_select_21_wd), + .d (hw2reg.dio_pad_attr[21].pull_select.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[3]), + .q (reg2hw.dio_pad_attr[21].pull_select.q), + .ds (), + .qs (dio_pad_attr_21_pull_select_21_qs) + ); + assign reg2hw.dio_pad_attr[21].pull_select.qe = dio_pad_attr_21_qe; + + // F[keeper_en_21]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_keeper_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_keeper_en_21_wd), + .d (hw2reg.dio_pad_attr[21].keeper_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[4]), + .q (reg2hw.dio_pad_attr[21].keeper_en.q), + .ds (), + .qs (dio_pad_attr_21_keeper_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].keeper_en.qe = dio_pad_attr_21_qe; + + // F[schmitt_en_21]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_schmitt_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_schmitt_en_21_wd), + .d (hw2reg.dio_pad_attr[21].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[5]), + .q (reg2hw.dio_pad_attr[21].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_21_schmitt_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].schmitt_en.qe = dio_pad_attr_21_qe; + + // F[od_en_21]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_od_en_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_od_en_21_wd), + .d (hw2reg.dio_pad_attr[21].od_en.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[6]), + .q (reg2hw.dio_pad_attr[21].od_en.q), + .ds (), + .qs (dio_pad_attr_21_od_en_21_qs) + ); + assign reg2hw.dio_pad_attr[21].od_en.qe = dio_pad_attr_21_qe; + + // F[input_disable_21]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_21_input_disable_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_input_disable_21_wd), + .d (hw2reg.dio_pad_attr[21].input_disable.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[7]), + .q (reg2hw.dio_pad_attr[21].input_disable.q), + .ds (), + .qs (dio_pad_attr_21_input_disable_21_qs) + ); + assign reg2hw.dio_pad_attr[21].input_disable.qe = dio_pad_attr_21_qe; + + // F[slew_rate_21]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_21_slew_rate_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_slew_rate_21_wd), + .d (hw2reg.dio_pad_attr[21].slew_rate.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[8]), + .q (reg2hw.dio_pad_attr[21].slew_rate.q), + .ds (), + .qs (dio_pad_attr_21_slew_rate_21_qs) + ); + assign reg2hw.dio_pad_attr[21].slew_rate.qe = dio_pad_attr_21_qe; + + // F[drive_strength_21]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_21_drive_strength_21 ( + .re (dio_pad_attr_21_re), + .we (dio_pad_attr_21_gated_we), + .wd (dio_pad_attr_21_drive_strength_21_wd), + .d (hw2reg.dio_pad_attr[21].drive_strength.d), + .qre (), + .qe (dio_pad_attr_21_flds_we[9]), + .q (reg2hw.dio_pad_attr[21].drive_strength.q), + .ds (), + .qs (dio_pad_attr_21_drive_strength_21_qs) + ); + assign reg2hw.dio_pad_attr[21].drive_strength.qe = dio_pad_attr_21_qe; + + + // Subregister 22 of Multireg dio_pad_attr + // R[dio_pad_attr_22]: V(True) + logic dio_pad_attr_22_qe; + logic [9:0] dio_pad_attr_22_flds_we; + assign dio_pad_attr_22_qe = &dio_pad_attr_22_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_22_gated_we; + assign dio_pad_attr_22_gated_we = dio_pad_attr_22_we & dio_pad_attr_regwen_22_qs; + // F[invert_22]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_invert_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_invert_22_wd), + .d (hw2reg.dio_pad_attr[22].invert.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[0]), + .q (reg2hw.dio_pad_attr[22].invert.q), + .ds (), + .qs (dio_pad_attr_22_invert_22_qs) + ); + assign reg2hw.dio_pad_attr[22].invert.qe = dio_pad_attr_22_qe; + + // F[virtual_od_en_22]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_virtual_od_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_virtual_od_en_22_wd), + .d (hw2reg.dio_pad_attr[22].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[1]), + .q (reg2hw.dio_pad_attr[22].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_22_virtual_od_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].virtual_od_en.qe = dio_pad_attr_22_qe; + + // F[pull_en_22]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_pull_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_pull_en_22_wd), + .d (hw2reg.dio_pad_attr[22].pull_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[2]), + .q (reg2hw.dio_pad_attr[22].pull_en.q), + .ds (), + .qs (dio_pad_attr_22_pull_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].pull_en.qe = dio_pad_attr_22_qe; + + // F[pull_select_22]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_pull_select_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_pull_select_22_wd), + .d (hw2reg.dio_pad_attr[22].pull_select.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[3]), + .q (reg2hw.dio_pad_attr[22].pull_select.q), + .ds (), + .qs (dio_pad_attr_22_pull_select_22_qs) + ); + assign reg2hw.dio_pad_attr[22].pull_select.qe = dio_pad_attr_22_qe; + + // F[keeper_en_22]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_keeper_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_keeper_en_22_wd), + .d (hw2reg.dio_pad_attr[22].keeper_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[4]), + .q (reg2hw.dio_pad_attr[22].keeper_en.q), + .ds (), + .qs (dio_pad_attr_22_keeper_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].keeper_en.qe = dio_pad_attr_22_qe; + + // F[schmitt_en_22]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_schmitt_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_schmitt_en_22_wd), + .d (hw2reg.dio_pad_attr[22].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[5]), + .q (reg2hw.dio_pad_attr[22].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_22_schmitt_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].schmitt_en.qe = dio_pad_attr_22_qe; + + // F[od_en_22]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_od_en_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_od_en_22_wd), + .d (hw2reg.dio_pad_attr[22].od_en.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[6]), + .q (reg2hw.dio_pad_attr[22].od_en.q), + .ds (), + .qs (dio_pad_attr_22_od_en_22_qs) + ); + assign reg2hw.dio_pad_attr[22].od_en.qe = dio_pad_attr_22_qe; + + // F[input_disable_22]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_22_input_disable_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_input_disable_22_wd), + .d (hw2reg.dio_pad_attr[22].input_disable.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[7]), + .q (reg2hw.dio_pad_attr[22].input_disable.q), + .ds (), + .qs (dio_pad_attr_22_input_disable_22_qs) + ); + assign reg2hw.dio_pad_attr[22].input_disable.qe = dio_pad_attr_22_qe; + + // F[slew_rate_22]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_22_slew_rate_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_slew_rate_22_wd), + .d (hw2reg.dio_pad_attr[22].slew_rate.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[8]), + .q (reg2hw.dio_pad_attr[22].slew_rate.q), + .ds (), + .qs (dio_pad_attr_22_slew_rate_22_qs) + ); + assign reg2hw.dio_pad_attr[22].slew_rate.qe = dio_pad_attr_22_qe; + + // F[drive_strength_22]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_22_drive_strength_22 ( + .re (dio_pad_attr_22_re), + .we (dio_pad_attr_22_gated_we), + .wd (dio_pad_attr_22_drive_strength_22_wd), + .d (hw2reg.dio_pad_attr[22].drive_strength.d), + .qre (), + .qe (dio_pad_attr_22_flds_we[9]), + .q (reg2hw.dio_pad_attr[22].drive_strength.q), + .ds (), + .qs (dio_pad_attr_22_drive_strength_22_qs) + ); + assign reg2hw.dio_pad_attr[22].drive_strength.qe = dio_pad_attr_22_qe; + + + // Subregister 23 of Multireg dio_pad_attr + // R[dio_pad_attr_23]: V(True) + logic dio_pad_attr_23_qe; + logic [9:0] dio_pad_attr_23_flds_we; + assign dio_pad_attr_23_qe = &dio_pad_attr_23_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_23_gated_we; + assign dio_pad_attr_23_gated_we = dio_pad_attr_23_we & dio_pad_attr_regwen_23_qs; + // F[invert_23]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_invert_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_invert_23_wd), + .d (hw2reg.dio_pad_attr[23].invert.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[0]), + .q (reg2hw.dio_pad_attr[23].invert.q), + .ds (), + .qs (dio_pad_attr_23_invert_23_qs) + ); + assign reg2hw.dio_pad_attr[23].invert.qe = dio_pad_attr_23_qe; + + // F[virtual_od_en_23]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_virtual_od_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_virtual_od_en_23_wd), + .d (hw2reg.dio_pad_attr[23].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[1]), + .q (reg2hw.dio_pad_attr[23].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_23_virtual_od_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].virtual_od_en.qe = dio_pad_attr_23_qe; + + // F[pull_en_23]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_pull_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_pull_en_23_wd), + .d (hw2reg.dio_pad_attr[23].pull_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[2]), + .q (reg2hw.dio_pad_attr[23].pull_en.q), + .ds (), + .qs (dio_pad_attr_23_pull_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].pull_en.qe = dio_pad_attr_23_qe; + + // F[pull_select_23]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_pull_select_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_pull_select_23_wd), + .d (hw2reg.dio_pad_attr[23].pull_select.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[3]), + .q (reg2hw.dio_pad_attr[23].pull_select.q), + .ds (), + .qs (dio_pad_attr_23_pull_select_23_qs) + ); + assign reg2hw.dio_pad_attr[23].pull_select.qe = dio_pad_attr_23_qe; + + // F[keeper_en_23]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_keeper_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_keeper_en_23_wd), + .d (hw2reg.dio_pad_attr[23].keeper_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[4]), + .q (reg2hw.dio_pad_attr[23].keeper_en.q), + .ds (), + .qs (dio_pad_attr_23_keeper_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].keeper_en.qe = dio_pad_attr_23_qe; + + // F[schmitt_en_23]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_schmitt_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_schmitt_en_23_wd), + .d (hw2reg.dio_pad_attr[23].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[5]), + .q (reg2hw.dio_pad_attr[23].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_23_schmitt_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].schmitt_en.qe = dio_pad_attr_23_qe; + + // F[od_en_23]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_od_en_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_od_en_23_wd), + .d (hw2reg.dio_pad_attr[23].od_en.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[6]), + .q (reg2hw.dio_pad_attr[23].od_en.q), + .ds (), + .qs (dio_pad_attr_23_od_en_23_qs) + ); + assign reg2hw.dio_pad_attr[23].od_en.qe = dio_pad_attr_23_qe; + + // F[input_disable_23]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_23_input_disable_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_input_disable_23_wd), + .d (hw2reg.dio_pad_attr[23].input_disable.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[7]), + .q (reg2hw.dio_pad_attr[23].input_disable.q), + .ds (), + .qs (dio_pad_attr_23_input_disable_23_qs) + ); + assign reg2hw.dio_pad_attr[23].input_disable.qe = dio_pad_attr_23_qe; + + // F[slew_rate_23]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_23_slew_rate_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_slew_rate_23_wd), + .d (hw2reg.dio_pad_attr[23].slew_rate.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[8]), + .q (reg2hw.dio_pad_attr[23].slew_rate.q), + .ds (), + .qs (dio_pad_attr_23_slew_rate_23_qs) + ); + assign reg2hw.dio_pad_attr[23].slew_rate.qe = dio_pad_attr_23_qe; + + // F[drive_strength_23]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_23_drive_strength_23 ( + .re (dio_pad_attr_23_re), + .we (dio_pad_attr_23_gated_we), + .wd (dio_pad_attr_23_drive_strength_23_wd), + .d (hw2reg.dio_pad_attr[23].drive_strength.d), + .qre (), + .qe (dio_pad_attr_23_flds_we[9]), + .q (reg2hw.dio_pad_attr[23].drive_strength.q), + .ds (), + .qs (dio_pad_attr_23_drive_strength_23_qs) + ); + assign reg2hw.dio_pad_attr[23].drive_strength.qe = dio_pad_attr_23_qe; + + + // Subregister 24 of Multireg dio_pad_attr + // R[dio_pad_attr_24]: V(True) + logic dio_pad_attr_24_qe; + logic [9:0] dio_pad_attr_24_flds_we; + assign dio_pad_attr_24_qe = &dio_pad_attr_24_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_24_gated_we; + assign dio_pad_attr_24_gated_we = dio_pad_attr_24_we & dio_pad_attr_regwen_24_qs; + // F[invert_24]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_invert_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_invert_24_wd), + .d (hw2reg.dio_pad_attr[24].invert.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[0]), + .q (reg2hw.dio_pad_attr[24].invert.q), + .ds (), + .qs (dio_pad_attr_24_invert_24_qs) + ); + assign reg2hw.dio_pad_attr[24].invert.qe = dio_pad_attr_24_qe; + + // F[virtual_od_en_24]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_virtual_od_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_virtual_od_en_24_wd), + .d (hw2reg.dio_pad_attr[24].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[1]), + .q (reg2hw.dio_pad_attr[24].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_24_virtual_od_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].virtual_od_en.qe = dio_pad_attr_24_qe; + + // F[pull_en_24]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_pull_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_pull_en_24_wd), + .d (hw2reg.dio_pad_attr[24].pull_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[2]), + .q (reg2hw.dio_pad_attr[24].pull_en.q), + .ds (), + .qs (dio_pad_attr_24_pull_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].pull_en.qe = dio_pad_attr_24_qe; + + // F[pull_select_24]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_pull_select_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_pull_select_24_wd), + .d (hw2reg.dio_pad_attr[24].pull_select.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[3]), + .q (reg2hw.dio_pad_attr[24].pull_select.q), + .ds (), + .qs (dio_pad_attr_24_pull_select_24_qs) + ); + assign reg2hw.dio_pad_attr[24].pull_select.qe = dio_pad_attr_24_qe; + + // F[keeper_en_24]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_keeper_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_keeper_en_24_wd), + .d (hw2reg.dio_pad_attr[24].keeper_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[4]), + .q (reg2hw.dio_pad_attr[24].keeper_en.q), + .ds (), + .qs (dio_pad_attr_24_keeper_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].keeper_en.qe = dio_pad_attr_24_qe; + + // F[schmitt_en_24]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_schmitt_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_schmitt_en_24_wd), + .d (hw2reg.dio_pad_attr[24].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[5]), + .q (reg2hw.dio_pad_attr[24].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_24_schmitt_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].schmitt_en.qe = dio_pad_attr_24_qe; + + // F[od_en_24]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_od_en_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_od_en_24_wd), + .d (hw2reg.dio_pad_attr[24].od_en.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[6]), + .q (reg2hw.dio_pad_attr[24].od_en.q), + .ds (), + .qs (dio_pad_attr_24_od_en_24_qs) + ); + assign reg2hw.dio_pad_attr[24].od_en.qe = dio_pad_attr_24_qe; + + // F[input_disable_24]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_24_input_disable_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_input_disable_24_wd), + .d (hw2reg.dio_pad_attr[24].input_disable.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[7]), + .q (reg2hw.dio_pad_attr[24].input_disable.q), + .ds (), + .qs (dio_pad_attr_24_input_disable_24_qs) + ); + assign reg2hw.dio_pad_attr[24].input_disable.qe = dio_pad_attr_24_qe; + + // F[slew_rate_24]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_24_slew_rate_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_slew_rate_24_wd), + .d (hw2reg.dio_pad_attr[24].slew_rate.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[8]), + .q (reg2hw.dio_pad_attr[24].slew_rate.q), + .ds (), + .qs (dio_pad_attr_24_slew_rate_24_qs) + ); + assign reg2hw.dio_pad_attr[24].slew_rate.qe = dio_pad_attr_24_qe; + + // F[drive_strength_24]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_24_drive_strength_24 ( + .re (dio_pad_attr_24_re), + .we (dio_pad_attr_24_gated_we), + .wd (dio_pad_attr_24_drive_strength_24_wd), + .d (hw2reg.dio_pad_attr[24].drive_strength.d), + .qre (), + .qe (dio_pad_attr_24_flds_we[9]), + .q (reg2hw.dio_pad_attr[24].drive_strength.q), + .ds (), + .qs (dio_pad_attr_24_drive_strength_24_qs) + ); + assign reg2hw.dio_pad_attr[24].drive_strength.qe = dio_pad_attr_24_qe; + + + // Subregister 25 of Multireg dio_pad_attr + // R[dio_pad_attr_25]: V(True) + logic dio_pad_attr_25_qe; + logic [9:0] dio_pad_attr_25_flds_we; + assign dio_pad_attr_25_qe = &dio_pad_attr_25_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_25_gated_we; + assign dio_pad_attr_25_gated_we = dio_pad_attr_25_we & dio_pad_attr_regwen_25_qs; + // F[invert_25]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_invert_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_invert_25_wd), + .d (hw2reg.dio_pad_attr[25].invert.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[0]), + .q (reg2hw.dio_pad_attr[25].invert.q), + .ds (), + .qs (dio_pad_attr_25_invert_25_qs) + ); + assign reg2hw.dio_pad_attr[25].invert.qe = dio_pad_attr_25_qe; + + // F[virtual_od_en_25]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_virtual_od_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_virtual_od_en_25_wd), + .d (hw2reg.dio_pad_attr[25].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[1]), + .q (reg2hw.dio_pad_attr[25].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_25_virtual_od_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].virtual_od_en.qe = dio_pad_attr_25_qe; + + // F[pull_en_25]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_pull_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_pull_en_25_wd), + .d (hw2reg.dio_pad_attr[25].pull_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[2]), + .q (reg2hw.dio_pad_attr[25].pull_en.q), + .ds (), + .qs (dio_pad_attr_25_pull_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].pull_en.qe = dio_pad_attr_25_qe; + + // F[pull_select_25]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_pull_select_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_pull_select_25_wd), + .d (hw2reg.dio_pad_attr[25].pull_select.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[3]), + .q (reg2hw.dio_pad_attr[25].pull_select.q), + .ds (), + .qs (dio_pad_attr_25_pull_select_25_qs) + ); + assign reg2hw.dio_pad_attr[25].pull_select.qe = dio_pad_attr_25_qe; + + // F[keeper_en_25]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_keeper_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_keeper_en_25_wd), + .d (hw2reg.dio_pad_attr[25].keeper_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[4]), + .q (reg2hw.dio_pad_attr[25].keeper_en.q), + .ds (), + .qs (dio_pad_attr_25_keeper_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].keeper_en.qe = dio_pad_attr_25_qe; + + // F[schmitt_en_25]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_schmitt_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_schmitt_en_25_wd), + .d (hw2reg.dio_pad_attr[25].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[5]), + .q (reg2hw.dio_pad_attr[25].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_25_schmitt_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].schmitt_en.qe = dio_pad_attr_25_qe; + + // F[od_en_25]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_od_en_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_od_en_25_wd), + .d (hw2reg.dio_pad_attr[25].od_en.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[6]), + .q (reg2hw.dio_pad_attr[25].od_en.q), + .ds (), + .qs (dio_pad_attr_25_od_en_25_qs) + ); + assign reg2hw.dio_pad_attr[25].od_en.qe = dio_pad_attr_25_qe; + + // F[input_disable_25]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_25_input_disable_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_input_disable_25_wd), + .d (hw2reg.dio_pad_attr[25].input_disable.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[7]), + .q (reg2hw.dio_pad_attr[25].input_disable.q), + .ds (), + .qs (dio_pad_attr_25_input_disable_25_qs) + ); + assign reg2hw.dio_pad_attr[25].input_disable.qe = dio_pad_attr_25_qe; + + // F[slew_rate_25]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_25_slew_rate_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_slew_rate_25_wd), + .d (hw2reg.dio_pad_attr[25].slew_rate.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[8]), + .q (reg2hw.dio_pad_attr[25].slew_rate.q), + .ds (), + .qs (dio_pad_attr_25_slew_rate_25_qs) + ); + assign reg2hw.dio_pad_attr[25].slew_rate.qe = dio_pad_attr_25_qe; + + // F[drive_strength_25]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_25_drive_strength_25 ( + .re (dio_pad_attr_25_re), + .we (dio_pad_attr_25_gated_we), + .wd (dio_pad_attr_25_drive_strength_25_wd), + .d (hw2reg.dio_pad_attr[25].drive_strength.d), + .qre (), + .qe (dio_pad_attr_25_flds_we[9]), + .q (reg2hw.dio_pad_attr[25].drive_strength.q), + .ds (), + .qs (dio_pad_attr_25_drive_strength_25_qs) + ); + assign reg2hw.dio_pad_attr[25].drive_strength.qe = dio_pad_attr_25_qe; + + + // Subregister 26 of Multireg dio_pad_attr + // R[dio_pad_attr_26]: V(True) + logic dio_pad_attr_26_qe; + logic [9:0] dio_pad_attr_26_flds_we; + assign dio_pad_attr_26_qe = &dio_pad_attr_26_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_26_gated_we; + assign dio_pad_attr_26_gated_we = dio_pad_attr_26_we & dio_pad_attr_regwen_26_qs; + // F[invert_26]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_invert_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_invert_26_wd), + .d (hw2reg.dio_pad_attr[26].invert.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[0]), + .q (reg2hw.dio_pad_attr[26].invert.q), + .ds (), + .qs (dio_pad_attr_26_invert_26_qs) + ); + assign reg2hw.dio_pad_attr[26].invert.qe = dio_pad_attr_26_qe; + + // F[virtual_od_en_26]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_virtual_od_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_virtual_od_en_26_wd), + .d (hw2reg.dio_pad_attr[26].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[1]), + .q (reg2hw.dio_pad_attr[26].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_26_virtual_od_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].virtual_od_en.qe = dio_pad_attr_26_qe; + + // F[pull_en_26]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_pull_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_pull_en_26_wd), + .d (hw2reg.dio_pad_attr[26].pull_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[2]), + .q (reg2hw.dio_pad_attr[26].pull_en.q), + .ds (), + .qs (dio_pad_attr_26_pull_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].pull_en.qe = dio_pad_attr_26_qe; + + // F[pull_select_26]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_pull_select_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_pull_select_26_wd), + .d (hw2reg.dio_pad_attr[26].pull_select.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[3]), + .q (reg2hw.dio_pad_attr[26].pull_select.q), + .ds (), + .qs (dio_pad_attr_26_pull_select_26_qs) + ); + assign reg2hw.dio_pad_attr[26].pull_select.qe = dio_pad_attr_26_qe; + + // F[keeper_en_26]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_keeper_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_keeper_en_26_wd), + .d (hw2reg.dio_pad_attr[26].keeper_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[4]), + .q (reg2hw.dio_pad_attr[26].keeper_en.q), + .ds (), + .qs (dio_pad_attr_26_keeper_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].keeper_en.qe = dio_pad_attr_26_qe; + + // F[schmitt_en_26]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_schmitt_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_schmitt_en_26_wd), + .d (hw2reg.dio_pad_attr[26].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[5]), + .q (reg2hw.dio_pad_attr[26].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_26_schmitt_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].schmitt_en.qe = dio_pad_attr_26_qe; + + // F[od_en_26]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_od_en_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_od_en_26_wd), + .d (hw2reg.dio_pad_attr[26].od_en.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[6]), + .q (reg2hw.dio_pad_attr[26].od_en.q), + .ds (), + .qs (dio_pad_attr_26_od_en_26_qs) + ); + assign reg2hw.dio_pad_attr[26].od_en.qe = dio_pad_attr_26_qe; + + // F[input_disable_26]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_26_input_disable_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_input_disable_26_wd), + .d (hw2reg.dio_pad_attr[26].input_disable.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[7]), + .q (reg2hw.dio_pad_attr[26].input_disable.q), + .ds (), + .qs (dio_pad_attr_26_input_disable_26_qs) + ); + assign reg2hw.dio_pad_attr[26].input_disable.qe = dio_pad_attr_26_qe; + + // F[slew_rate_26]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_26_slew_rate_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_slew_rate_26_wd), + .d (hw2reg.dio_pad_attr[26].slew_rate.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[8]), + .q (reg2hw.dio_pad_attr[26].slew_rate.q), + .ds (), + .qs (dio_pad_attr_26_slew_rate_26_qs) + ); + assign reg2hw.dio_pad_attr[26].slew_rate.qe = dio_pad_attr_26_qe; + + // F[drive_strength_26]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_26_drive_strength_26 ( + .re (dio_pad_attr_26_re), + .we (dio_pad_attr_26_gated_we), + .wd (dio_pad_attr_26_drive_strength_26_wd), + .d (hw2reg.dio_pad_attr[26].drive_strength.d), + .qre (), + .qe (dio_pad_attr_26_flds_we[9]), + .q (reg2hw.dio_pad_attr[26].drive_strength.q), + .ds (), + .qs (dio_pad_attr_26_drive_strength_26_qs) + ); + assign reg2hw.dio_pad_attr[26].drive_strength.qe = dio_pad_attr_26_qe; + + + // Subregister 27 of Multireg dio_pad_attr + // R[dio_pad_attr_27]: V(True) + logic dio_pad_attr_27_qe; + logic [9:0] dio_pad_attr_27_flds_we; + assign dio_pad_attr_27_qe = &dio_pad_attr_27_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_27_gated_we; + assign dio_pad_attr_27_gated_we = dio_pad_attr_27_we & dio_pad_attr_regwen_27_qs; + // F[invert_27]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_invert_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_invert_27_wd), + .d (hw2reg.dio_pad_attr[27].invert.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[0]), + .q (reg2hw.dio_pad_attr[27].invert.q), + .ds (), + .qs (dio_pad_attr_27_invert_27_qs) + ); + assign reg2hw.dio_pad_attr[27].invert.qe = dio_pad_attr_27_qe; + + // F[virtual_od_en_27]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_virtual_od_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_virtual_od_en_27_wd), + .d (hw2reg.dio_pad_attr[27].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[1]), + .q (reg2hw.dio_pad_attr[27].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_27_virtual_od_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].virtual_od_en.qe = dio_pad_attr_27_qe; + + // F[pull_en_27]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_pull_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_pull_en_27_wd), + .d (hw2reg.dio_pad_attr[27].pull_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[2]), + .q (reg2hw.dio_pad_attr[27].pull_en.q), + .ds (), + .qs (dio_pad_attr_27_pull_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].pull_en.qe = dio_pad_attr_27_qe; + + // F[pull_select_27]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_pull_select_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_pull_select_27_wd), + .d (hw2reg.dio_pad_attr[27].pull_select.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[3]), + .q (reg2hw.dio_pad_attr[27].pull_select.q), + .ds (), + .qs (dio_pad_attr_27_pull_select_27_qs) + ); + assign reg2hw.dio_pad_attr[27].pull_select.qe = dio_pad_attr_27_qe; + + // F[keeper_en_27]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_keeper_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_keeper_en_27_wd), + .d (hw2reg.dio_pad_attr[27].keeper_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[4]), + .q (reg2hw.dio_pad_attr[27].keeper_en.q), + .ds (), + .qs (dio_pad_attr_27_keeper_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].keeper_en.qe = dio_pad_attr_27_qe; + + // F[schmitt_en_27]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_schmitt_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_schmitt_en_27_wd), + .d (hw2reg.dio_pad_attr[27].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[5]), + .q (reg2hw.dio_pad_attr[27].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_27_schmitt_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].schmitt_en.qe = dio_pad_attr_27_qe; + + // F[od_en_27]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_od_en_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_od_en_27_wd), + .d (hw2reg.dio_pad_attr[27].od_en.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[6]), + .q (reg2hw.dio_pad_attr[27].od_en.q), + .ds (), + .qs (dio_pad_attr_27_od_en_27_qs) + ); + assign reg2hw.dio_pad_attr[27].od_en.qe = dio_pad_attr_27_qe; + + // F[input_disable_27]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_27_input_disable_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_input_disable_27_wd), + .d (hw2reg.dio_pad_attr[27].input_disable.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[7]), + .q (reg2hw.dio_pad_attr[27].input_disable.q), + .ds (), + .qs (dio_pad_attr_27_input_disable_27_qs) + ); + assign reg2hw.dio_pad_attr[27].input_disable.qe = dio_pad_attr_27_qe; + + // F[slew_rate_27]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_27_slew_rate_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_slew_rate_27_wd), + .d (hw2reg.dio_pad_attr[27].slew_rate.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[8]), + .q (reg2hw.dio_pad_attr[27].slew_rate.q), + .ds (), + .qs (dio_pad_attr_27_slew_rate_27_qs) + ); + assign reg2hw.dio_pad_attr[27].slew_rate.qe = dio_pad_attr_27_qe; + + // F[drive_strength_27]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_27_drive_strength_27 ( + .re (dio_pad_attr_27_re), + .we (dio_pad_attr_27_gated_we), + .wd (dio_pad_attr_27_drive_strength_27_wd), + .d (hw2reg.dio_pad_attr[27].drive_strength.d), + .qre (), + .qe (dio_pad_attr_27_flds_we[9]), + .q (reg2hw.dio_pad_attr[27].drive_strength.q), + .ds (), + .qs (dio_pad_attr_27_drive_strength_27_qs) + ); + assign reg2hw.dio_pad_attr[27].drive_strength.qe = dio_pad_attr_27_qe; + + + // Subregister 28 of Multireg dio_pad_attr + // R[dio_pad_attr_28]: V(True) + logic dio_pad_attr_28_qe; + logic [9:0] dio_pad_attr_28_flds_we; + assign dio_pad_attr_28_qe = &dio_pad_attr_28_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_28_gated_we; + assign dio_pad_attr_28_gated_we = dio_pad_attr_28_we & dio_pad_attr_regwen_28_qs; + // F[invert_28]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_invert_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_invert_28_wd), + .d (hw2reg.dio_pad_attr[28].invert.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[0]), + .q (reg2hw.dio_pad_attr[28].invert.q), + .ds (), + .qs (dio_pad_attr_28_invert_28_qs) + ); + assign reg2hw.dio_pad_attr[28].invert.qe = dio_pad_attr_28_qe; + + // F[virtual_od_en_28]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_virtual_od_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_virtual_od_en_28_wd), + .d (hw2reg.dio_pad_attr[28].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[1]), + .q (reg2hw.dio_pad_attr[28].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_28_virtual_od_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].virtual_od_en.qe = dio_pad_attr_28_qe; + + // F[pull_en_28]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_pull_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_pull_en_28_wd), + .d (hw2reg.dio_pad_attr[28].pull_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[2]), + .q (reg2hw.dio_pad_attr[28].pull_en.q), + .ds (), + .qs (dio_pad_attr_28_pull_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].pull_en.qe = dio_pad_attr_28_qe; + + // F[pull_select_28]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_pull_select_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_pull_select_28_wd), + .d (hw2reg.dio_pad_attr[28].pull_select.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[3]), + .q (reg2hw.dio_pad_attr[28].pull_select.q), + .ds (), + .qs (dio_pad_attr_28_pull_select_28_qs) + ); + assign reg2hw.dio_pad_attr[28].pull_select.qe = dio_pad_attr_28_qe; + + // F[keeper_en_28]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_keeper_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_keeper_en_28_wd), + .d (hw2reg.dio_pad_attr[28].keeper_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[4]), + .q (reg2hw.dio_pad_attr[28].keeper_en.q), + .ds (), + .qs (dio_pad_attr_28_keeper_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].keeper_en.qe = dio_pad_attr_28_qe; + + // F[schmitt_en_28]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_schmitt_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_schmitt_en_28_wd), + .d (hw2reg.dio_pad_attr[28].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[5]), + .q (reg2hw.dio_pad_attr[28].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_28_schmitt_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].schmitt_en.qe = dio_pad_attr_28_qe; + + // F[od_en_28]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_od_en_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_od_en_28_wd), + .d (hw2reg.dio_pad_attr[28].od_en.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[6]), + .q (reg2hw.dio_pad_attr[28].od_en.q), + .ds (), + .qs (dio_pad_attr_28_od_en_28_qs) + ); + assign reg2hw.dio_pad_attr[28].od_en.qe = dio_pad_attr_28_qe; + + // F[input_disable_28]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_28_input_disable_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_input_disable_28_wd), + .d (hw2reg.dio_pad_attr[28].input_disable.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[7]), + .q (reg2hw.dio_pad_attr[28].input_disable.q), + .ds (), + .qs (dio_pad_attr_28_input_disable_28_qs) + ); + assign reg2hw.dio_pad_attr[28].input_disable.qe = dio_pad_attr_28_qe; + + // F[slew_rate_28]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_28_slew_rate_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_slew_rate_28_wd), + .d (hw2reg.dio_pad_attr[28].slew_rate.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[8]), + .q (reg2hw.dio_pad_attr[28].slew_rate.q), + .ds (), + .qs (dio_pad_attr_28_slew_rate_28_qs) + ); + assign reg2hw.dio_pad_attr[28].slew_rate.qe = dio_pad_attr_28_qe; + + // F[drive_strength_28]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_28_drive_strength_28 ( + .re (dio_pad_attr_28_re), + .we (dio_pad_attr_28_gated_we), + .wd (dio_pad_attr_28_drive_strength_28_wd), + .d (hw2reg.dio_pad_attr[28].drive_strength.d), + .qre (), + .qe (dio_pad_attr_28_flds_we[9]), + .q (reg2hw.dio_pad_attr[28].drive_strength.q), + .ds (), + .qs (dio_pad_attr_28_drive_strength_28_qs) + ); + assign reg2hw.dio_pad_attr[28].drive_strength.qe = dio_pad_attr_28_qe; + + + // Subregister 29 of Multireg dio_pad_attr + // R[dio_pad_attr_29]: V(True) + logic dio_pad_attr_29_qe; + logic [9:0] dio_pad_attr_29_flds_we; + assign dio_pad_attr_29_qe = &dio_pad_attr_29_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_29_gated_we; + assign dio_pad_attr_29_gated_we = dio_pad_attr_29_we & dio_pad_attr_regwen_29_qs; + // F[invert_29]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_invert_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_invert_29_wd), + .d (hw2reg.dio_pad_attr[29].invert.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[0]), + .q (reg2hw.dio_pad_attr[29].invert.q), + .ds (), + .qs (dio_pad_attr_29_invert_29_qs) + ); + assign reg2hw.dio_pad_attr[29].invert.qe = dio_pad_attr_29_qe; + + // F[virtual_od_en_29]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_virtual_od_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_virtual_od_en_29_wd), + .d (hw2reg.dio_pad_attr[29].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[1]), + .q (reg2hw.dio_pad_attr[29].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_29_virtual_od_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].virtual_od_en.qe = dio_pad_attr_29_qe; + + // F[pull_en_29]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_pull_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_pull_en_29_wd), + .d (hw2reg.dio_pad_attr[29].pull_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[2]), + .q (reg2hw.dio_pad_attr[29].pull_en.q), + .ds (), + .qs (dio_pad_attr_29_pull_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].pull_en.qe = dio_pad_attr_29_qe; + + // F[pull_select_29]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_pull_select_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_pull_select_29_wd), + .d (hw2reg.dio_pad_attr[29].pull_select.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[3]), + .q (reg2hw.dio_pad_attr[29].pull_select.q), + .ds (), + .qs (dio_pad_attr_29_pull_select_29_qs) + ); + assign reg2hw.dio_pad_attr[29].pull_select.qe = dio_pad_attr_29_qe; + + // F[keeper_en_29]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_keeper_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_keeper_en_29_wd), + .d (hw2reg.dio_pad_attr[29].keeper_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[4]), + .q (reg2hw.dio_pad_attr[29].keeper_en.q), + .ds (), + .qs (dio_pad_attr_29_keeper_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].keeper_en.qe = dio_pad_attr_29_qe; + + // F[schmitt_en_29]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_schmitt_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_schmitt_en_29_wd), + .d (hw2reg.dio_pad_attr[29].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[5]), + .q (reg2hw.dio_pad_attr[29].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_29_schmitt_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].schmitt_en.qe = dio_pad_attr_29_qe; + + // F[od_en_29]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_od_en_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_od_en_29_wd), + .d (hw2reg.dio_pad_attr[29].od_en.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[6]), + .q (reg2hw.dio_pad_attr[29].od_en.q), + .ds (), + .qs (dio_pad_attr_29_od_en_29_qs) + ); + assign reg2hw.dio_pad_attr[29].od_en.qe = dio_pad_attr_29_qe; + + // F[input_disable_29]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_29_input_disable_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_input_disable_29_wd), + .d (hw2reg.dio_pad_attr[29].input_disable.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[7]), + .q (reg2hw.dio_pad_attr[29].input_disable.q), + .ds (), + .qs (dio_pad_attr_29_input_disable_29_qs) + ); + assign reg2hw.dio_pad_attr[29].input_disable.qe = dio_pad_attr_29_qe; + + // F[slew_rate_29]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_29_slew_rate_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_slew_rate_29_wd), + .d (hw2reg.dio_pad_attr[29].slew_rate.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[8]), + .q (reg2hw.dio_pad_attr[29].slew_rate.q), + .ds (), + .qs (dio_pad_attr_29_slew_rate_29_qs) + ); + assign reg2hw.dio_pad_attr[29].slew_rate.qe = dio_pad_attr_29_qe; + + // F[drive_strength_29]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_29_drive_strength_29 ( + .re (dio_pad_attr_29_re), + .we (dio_pad_attr_29_gated_we), + .wd (dio_pad_attr_29_drive_strength_29_wd), + .d (hw2reg.dio_pad_attr[29].drive_strength.d), + .qre (), + .qe (dio_pad_attr_29_flds_we[9]), + .q (reg2hw.dio_pad_attr[29].drive_strength.q), + .ds (), + .qs (dio_pad_attr_29_drive_strength_29_qs) + ); + assign reg2hw.dio_pad_attr[29].drive_strength.qe = dio_pad_attr_29_qe; + + + // Subregister 30 of Multireg dio_pad_attr + // R[dio_pad_attr_30]: V(True) + logic dio_pad_attr_30_qe; + logic [9:0] dio_pad_attr_30_flds_we; + assign dio_pad_attr_30_qe = &dio_pad_attr_30_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_30_gated_we; + assign dio_pad_attr_30_gated_we = dio_pad_attr_30_we & dio_pad_attr_regwen_30_qs; + // F[invert_30]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_invert_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_invert_30_wd), + .d (hw2reg.dio_pad_attr[30].invert.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[0]), + .q (reg2hw.dio_pad_attr[30].invert.q), + .ds (), + .qs (dio_pad_attr_30_invert_30_qs) + ); + assign reg2hw.dio_pad_attr[30].invert.qe = dio_pad_attr_30_qe; + + // F[virtual_od_en_30]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_virtual_od_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_virtual_od_en_30_wd), + .d (hw2reg.dio_pad_attr[30].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[1]), + .q (reg2hw.dio_pad_attr[30].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_30_virtual_od_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].virtual_od_en.qe = dio_pad_attr_30_qe; + + // F[pull_en_30]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_pull_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_pull_en_30_wd), + .d (hw2reg.dio_pad_attr[30].pull_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[2]), + .q (reg2hw.dio_pad_attr[30].pull_en.q), + .ds (), + .qs (dio_pad_attr_30_pull_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].pull_en.qe = dio_pad_attr_30_qe; + + // F[pull_select_30]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_pull_select_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_pull_select_30_wd), + .d (hw2reg.dio_pad_attr[30].pull_select.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[3]), + .q (reg2hw.dio_pad_attr[30].pull_select.q), + .ds (), + .qs (dio_pad_attr_30_pull_select_30_qs) + ); + assign reg2hw.dio_pad_attr[30].pull_select.qe = dio_pad_attr_30_qe; + + // F[keeper_en_30]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_keeper_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_keeper_en_30_wd), + .d (hw2reg.dio_pad_attr[30].keeper_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[4]), + .q (reg2hw.dio_pad_attr[30].keeper_en.q), + .ds (), + .qs (dio_pad_attr_30_keeper_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].keeper_en.qe = dio_pad_attr_30_qe; + + // F[schmitt_en_30]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_schmitt_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_schmitt_en_30_wd), + .d (hw2reg.dio_pad_attr[30].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[5]), + .q (reg2hw.dio_pad_attr[30].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_30_schmitt_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].schmitt_en.qe = dio_pad_attr_30_qe; + + // F[od_en_30]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_od_en_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_od_en_30_wd), + .d (hw2reg.dio_pad_attr[30].od_en.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[6]), + .q (reg2hw.dio_pad_attr[30].od_en.q), + .ds (), + .qs (dio_pad_attr_30_od_en_30_qs) + ); + assign reg2hw.dio_pad_attr[30].od_en.qe = dio_pad_attr_30_qe; + + // F[input_disable_30]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_30_input_disable_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_input_disable_30_wd), + .d (hw2reg.dio_pad_attr[30].input_disable.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[7]), + .q (reg2hw.dio_pad_attr[30].input_disable.q), + .ds (), + .qs (dio_pad_attr_30_input_disable_30_qs) + ); + assign reg2hw.dio_pad_attr[30].input_disable.qe = dio_pad_attr_30_qe; + + // F[slew_rate_30]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_30_slew_rate_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_slew_rate_30_wd), + .d (hw2reg.dio_pad_attr[30].slew_rate.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[8]), + .q (reg2hw.dio_pad_attr[30].slew_rate.q), + .ds (), + .qs (dio_pad_attr_30_slew_rate_30_qs) + ); + assign reg2hw.dio_pad_attr[30].slew_rate.qe = dio_pad_attr_30_qe; + + // F[drive_strength_30]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_30_drive_strength_30 ( + .re (dio_pad_attr_30_re), + .we (dio_pad_attr_30_gated_we), + .wd (dio_pad_attr_30_drive_strength_30_wd), + .d (hw2reg.dio_pad_attr[30].drive_strength.d), + .qre (), + .qe (dio_pad_attr_30_flds_we[9]), + .q (reg2hw.dio_pad_attr[30].drive_strength.q), + .ds (), + .qs (dio_pad_attr_30_drive_strength_30_qs) + ); + assign reg2hw.dio_pad_attr[30].drive_strength.qe = dio_pad_attr_30_qe; + + + // Subregister 31 of Multireg dio_pad_attr + // R[dio_pad_attr_31]: V(True) + logic dio_pad_attr_31_qe; + logic [9:0] dio_pad_attr_31_flds_we; + assign dio_pad_attr_31_qe = &dio_pad_attr_31_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_31_gated_we; + assign dio_pad_attr_31_gated_we = dio_pad_attr_31_we & dio_pad_attr_regwen_31_qs; + // F[invert_31]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_invert_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_invert_31_wd), + .d (hw2reg.dio_pad_attr[31].invert.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[0]), + .q (reg2hw.dio_pad_attr[31].invert.q), + .ds (), + .qs (dio_pad_attr_31_invert_31_qs) + ); + assign reg2hw.dio_pad_attr[31].invert.qe = dio_pad_attr_31_qe; + + // F[virtual_od_en_31]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_virtual_od_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_virtual_od_en_31_wd), + .d (hw2reg.dio_pad_attr[31].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[1]), + .q (reg2hw.dio_pad_attr[31].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_31_virtual_od_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].virtual_od_en.qe = dio_pad_attr_31_qe; + + // F[pull_en_31]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_pull_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_pull_en_31_wd), + .d (hw2reg.dio_pad_attr[31].pull_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[2]), + .q (reg2hw.dio_pad_attr[31].pull_en.q), + .ds (), + .qs (dio_pad_attr_31_pull_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].pull_en.qe = dio_pad_attr_31_qe; + + // F[pull_select_31]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_pull_select_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_pull_select_31_wd), + .d (hw2reg.dio_pad_attr[31].pull_select.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[3]), + .q (reg2hw.dio_pad_attr[31].pull_select.q), + .ds (), + .qs (dio_pad_attr_31_pull_select_31_qs) + ); + assign reg2hw.dio_pad_attr[31].pull_select.qe = dio_pad_attr_31_qe; + + // F[keeper_en_31]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_keeper_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_keeper_en_31_wd), + .d (hw2reg.dio_pad_attr[31].keeper_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[4]), + .q (reg2hw.dio_pad_attr[31].keeper_en.q), + .ds (), + .qs (dio_pad_attr_31_keeper_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].keeper_en.qe = dio_pad_attr_31_qe; + + // F[schmitt_en_31]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_schmitt_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_schmitt_en_31_wd), + .d (hw2reg.dio_pad_attr[31].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[5]), + .q (reg2hw.dio_pad_attr[31].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_31_schmitt_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].schmitt_en.qe = dio_pad_attr_31_qe; + + // F[od_en_31]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_od_en_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_od_en_31_wd), + .d (hw2reg.dio_pad_attr[31].od_en.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[6]), + .q (reg2hw.dio_pad_attr[31].od_en.q), + .ds (), + .qs (dio_pad_attr_31_od_en_31_qs) + ); + assign reg2hw.dio_pad_attr[31].od_en.qe = dio_pad_attr_31_qe; + + // F[input_disable_31]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_31_input_disable_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_input_disable_31_wd), + .d (hw2reg.dio_pad_attr[31].input_disable.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[7]), + .q (reg2hw.dio_pad_attr[31].input_disable.q), + .ds (), + .qs (dio_pad_attr_31_input_disable_31_qs) + ); + assign reg2hw.dio_pad_attr[31].input_disable.qe = dio_pad_attr_31_qe; + + // F[slew_rate_31]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_31_slew_rate_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_slew_rate_31_wd), + .d (hw2reg.dio_pad_attr[31].slew_rate.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[8]), + .q (reg2hw.dio_pad_attr[31].slew_rate.q), + .ds (), + .qs (dio_pad_attr_31_slew_rate_31_qs) + ); + assign reg2hw.dio_pad_attr[31].slew_rate.qe = dio_pad_attr_31_qe; + + // F[drive_strength_31]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_31_drive_strength_31 ( + .re (dio_pad_attr_31_re), + .we (dio_pad_attr_31_gated_we), + .wd (dio_pad_attr_31_drive_strength_31_wd), + .d (hw2reg.dio_pad_attr[31].drive_strength.d), + .qre (), + .qe (dio_pad_attr_31_flds_we[9]), + .q (reg2hw.dio_pad_attr[31].drive_strength.q), + .ds (), + .qs (dio_pad_attr_31_drive_strength_31_qs) + ); + assign reg2hw.dio_pad_attr[31].drive_strength.qe = dio_pad_attr_31_qe; + + + // Subregister 32 of Multireg dio_pad_attr + // R[dio_pad_attr_32]: V(True) + logic dio_pad_attr_32_qe; + logic [9:0] dio_pad_attr_32_flds_we; + assign dio_pad_attr_32_qe = &dio_pad_attr_32_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_32_gated_we; + assign dio_pad_attr_32_gated_we = dio_pad_attr_32_we & dio_pad_attr_regwen_32_qs; + // F[invert_32]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_invert_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_invert_32_wd), + .d (hw2reg.dio_pad_attr[32].invert.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[0]), + .q (reg2hw.dio_pad_attr[32].invert.q), + .ds (), + .qs (dio_pad_attr_32_invert_32_qs) + ); + assign reg2hw.dio_pad_attr[32].invert.qe = dio_pad_attr_32_qe; + + // F[virtual_od_en_32]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_virtual_od_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_virtual_od_en_32_wd), + .d (hw2reg.dio_pad_attr[32].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[1]), + .q (reg2hw.dio_pad_attr[32].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_32_virtual_od_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].virtual_od_en.qe = dio_pad_attr_32_qe; + + // F[pull_en_32]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_pull_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_pull_en_32_wd), + .d (hw2reg.dio_pad_attr[32].pull_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[2]), + .q (reg2hw.dio_pad_attr[32].pull_en.q), + .ds (), + .qs (dio_pad_attr_32_pull_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].pull_en.qe = dio_pad_attr_32_qe; + + // F[pull_select_32]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_pull_select_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_pull_select_32_wd), + .d (hw2reg.dio_pad_attr[32].pull_select.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[3]), + .q (reg2hw.dio_pad_attr[32].pull_select.q), + .ds (), + .qs (dio_pad_attr_32_pull_select_32_qs) + ); + assign reg2hw.dio_pad_attr[32].pull_select.qe = dio_pad_attr_32_qe; + + // F[keeper_en_32]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_keeper_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_keeper_en_32_wd), + .d (hw2reg.dio_pad_attr[32].keeper_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[4]), + .q (reg2hw.dio_pad_attr[32].keeper_en.q), + .ds (), + .qs (dio_pad_attr_32_keeper_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].keeper_en.qe = dio_pad_attr_32_qe; + + // F[schmitt_en_32]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_schmitt_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_schmitt_en_32_wd), + .d (hw2reg.dio_pad_attr[32].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[5]), + .q (reg2hw.dio_pad_attr[32].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_32_schmitt_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].schmitt_en.qe = dio_pad_attr_32_qe; + + // F[od_en_32]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_od_en_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_od_en_32_wd), + .d (hw2reg.dio_pad_attr[32].od_en.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[6]), + .q (reg2hw.dio_pad_attr[32].od_en.q), + .ds (), + .qs (dio_pad_attr_32_od_en_32_qs) + ); + assign reg2hw.dio_pad_attr[32].od_en.qe = dio_pad_attr_32_qe; + + // F[input_disable_32]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_32_input_disable_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_input_disable_32_wd), + .d (hw2reg.dio_pad_attr[32].input_disable.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[7]), + .q (reg2hw.dio_pad_attr[32].input_disable.q), + .ds (), + .qs (dio_pad_attr_32_input_disable_32_qs) + ); + assign reg2hw.dio_pad_attr[32].input_disable.qe = dio_pad_attr_32_qe; + + // F[slew_rate_32]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_32_slew_rate_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_slew_rate_32_wd), + .d (hw2reg.dio_pad_attr[32].slew_rate.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[8]), + .q (reg2hw.dio_pad_attr[32].slew_rate.q), + .ds (), + .qs (dio_pad_attr_32_slew_rate_32_qs) + ); + assign reg2hw.dio_pad_attr[32].slew_rate.qe = dio_pad_attr_32_qe; + + // F[drive_strength_32]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_32_drive_strength_32 ( + .re (dio_pad_attr_32_re), + .we (dio_pad_attr_32_gated_we), + .wd (dio_pad_attr_32_drive_strength_32_wd), + .d (hw2reg.dio_pad_attr[32].drive_strength.d), + .qre (), + .qe (dio_pad_attr_32_flds_we[9]), + .q (reg2hw.dio_pad_attr[32].drive_strength.q), + .ds (), + .qs (dio_pad_attr_32_drive_strength_32_qs) + ); + assign reg2hw.dio_pad_attr[32].drive_strength.qe = dio_pad_attr_32_qe; + + + // Subregister 33 of Multireg dio_pad_attr + // R[dio_pad_attr_33]: V(True) + logic dio_pad_attr_33_qe; + logic [9:0] dio_pad_attr_33_flds_we; + assign dio_pad_attr_33_qe = &dio_pad_attr_33_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_33_gated_we; + assign dio_pad_attr_33_gated_we = dio_pad_attr_33_we & dio_pad_attr_regwen_33_qs; + // F[invert_33]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_invert_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_invert_33_wd), + .d (hw2reg.dio_pad_attr[33].invert.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[0]), + .q (reg2hw.dio_pad_attr[33].invert.q), + .ds (), + .qs (dio_pad_attr_33_invert_33_qs) + ); + assign reg2hw.dio_pad_attr[33].invert.qe = dio_pad_attr_33_qe; + + // F[virtual_od_en_33]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_virtual_od_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_virtual_od_en_33_wd), + .d (hw2reg.dio_pad_attr[33].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[1]), + .q (reg2hw.dio_pad_attr[33].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_33_virtual_od_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].virtual_od_en.qe = dio_pad_attr_33_qe; + + // F[pull_en_33]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_pull_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_pull_en_33_wd), + .d (hw2reg.dio_pad_attr[33].pull_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[2]), + .q (reg2hw.dio_pad_attr[33].pull_en.q), + .ds (), + .qs (dio_pad_attr_33_pull_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].pull_en.qe = dio_pad_attr_33_qe; + + // F[pull_select_33]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_pull_select_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_pull_select_33_wd), + .d (hw2reg.dio_pad_attr[33].pull_select.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[3]), + .q (reg2hw.dio_pad_attr[33].pull_select.q), + .ds (), + .qs (dio_pad_attr_33_pull_select_33_qs) + ); + assign reg2hw.dio_pad_attr[33].pull_select.qe = dio_pad_attr_33_qe; + + // F[keeper_en_33]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_keeper_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_keeper_en_33_wd), + .d (hw2reg.dio_pad_attr[33].keeper_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[4]), + .q (reg2hw.dio_pad_attr[33].keeper_en.q), + .ds (), + .qs (dio_pad_attr_33_keeper_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].keeper_en.qe = dio_pad_attr_33_qe; + + // F[schmitt_en_33]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_schmitt_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_schmitt_en_33_wd), + .d (hw2reg.dio_pad_attr[33].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[5]), + .q (reg2hw.dio_pad_attr[33].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_33_schmitt_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].schmitt_en.qe = dio_pad_attr_33_qe; + + // F[od_en_33]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_od_en_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_od_en_33_wd), + .d (hw2reg.dio_pad_attr[33].od_en.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[6]), + .q (reg2hw.dio_pad_attr[33].od_en.q), + .ds (), + .qs (dio_pad_attr_33_od_en_33_qs) + ); + assign reg2hw.dio_pad_attr[33].od_en.qe = dio_pad_attr_33_qe; + + // F[input_disable_33]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_33_input_disable_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_input_disable_33_wd), + .d (hw2reg.dio_pad_attr[33].input_disable.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[7]), + .q (reg2hw.dio_pad_attr[33].input_disable.q), + .ds (), + .qs (dio_pad_attr_33_input_disable_33_qs) + ); + assign reg2hw.dio_pad_attr[33].input_disable.qe = dio_pad_attr_33_qe; + + // F[slew_rate_33]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_33_slew_rate_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_slew_rate_33_wd), + .d (hw2reg.dio_pad_attr[33].slew_rate.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[8]), + .q (reg2hw.dio_pad_attr[33].slew_rate.q), + .ds (), + .qs (dio_pad_attr_33_slew_rate_33_qs) + ); + assign reg2hw.dio_pad_attr[33].slew_rate.qe = dio_pad_attr_33_qe; + + // F[drive_strength_33]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_33_drive_strength_33 ( + .re (dio_pad_attr_33_re), + .we (dio_pad_attr_33_gated_we), + .wd (dio_pad_attr_33_drive_strength_33_wd), + .d (hw2reg.dio_pad_attr[33].drive_strength.d), + .qre (), + .qe (dio_pad_attr_33_flds_we[9]), + .q (reg2hw.dio_pad_attr[33].drive_strength.q), + .ds (), + .qs (dio_pad_attr_33_drive_strength_33_qs) + ); + assign reg2hw.dio_pad_attr[33].drive_strength.qe = dio_pad_attr_33_qe; + + + // Subregister 34 of Multireg dio_pad_attr + // R[dio_pad_attr_34]: V(True) + logic dio_pad_attr_34_qe; + logic [9:0] dio_pad_attr_34_flds_we; + assign dio_pad_attr_34_qe = &dio_pad_attr_34_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_34_gated_we; + assign dio_pad_attr_34_gated_we = dio_pad_attr_34_we & dio_pad_attr_regwen_34_qs; + // F[invert_34]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_invert_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_invert_34_wd), + .d (hw2reg.dio_pad_attr[34].invert.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[0]), + .q (reg2hw.dio_pad_attr[34].invert.q), + .ds (), + .qs (dio_pad_attr_34_invert_34_qs) + ); + assign reg2hw.dio_pad_attr[34].invert.qe = dio_pad_attr_34_qe; + + // F[virtual_od_en_34]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_virtual_od_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_virtual_od_en_34_wd), + .d (hw2reg.dio_pad_attr[34].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[1]), + .q (reg2hw.dio_pad_attr[34].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_34_virtual_od_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].virtual_od_en.qe = dio_pad_attr_34_qe; + + // F[pull_en_34]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_pull_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_pull_en_34_wd), + .d (hw2reg.dio_pad_attr[34].pull_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[2]), + .q (reg2hw.dio_pad_attr[34].pull_en.q), + .ds (), + .qs (dio_pad_attr_34_pull_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].pull_en.qe = dio_pad_attr_34_qe; + + // F[pull_select_34]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_pull_select_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_pull_select_34_wd), + .d (hw2reg.dio_pad_attr[34].pull_select.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[3]), + .q (reg2hw.dio_pad_attr[34].pull_select.q), + .ds (), + .qs (dio_pad_attr_34_pull_select_34_qs) + ); + assign reg2hw.dio_pad_attr[34].pull_select.qe = dio_pad_attr_34_qe; + + // F[keeper_en_34]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_keeper_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_keeper_en_34_wd), + .d (hw2reg.dio_pad_attr[34].keeper_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[4]), + .q (reg2hw.dio_pad_attr[34].keeper_en.q), + .ds (), + .qs (dio_pad_attr_34_keeper_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].keeper_en.qe = dio_pad_attr_34_qe; + + // F[schmitt_en_34]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_schmitt_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_schmitt_en_34_wd), + .d (hw2reg.dio_pad_attr[34].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[5]), + .q (reg2hw.dio_pad_attr[34].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_34_schmitt_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].schmitt_en.qe = dio_pad_attr_34_qe; + + // F[od_en_34]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_od_en_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_od_en_34_wd), + .d (hw2reg.dio_pad_attr[34].od_en.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[6]), + .q (reg2hw.dio_pad_attr[34].od_en.q), + .ds (), + .qs (dio_pad_attr_34_od_en_34_qs) + ); + assign reg2hw.dio_pad_attr[34].od_en.qe = dio_pad_attr_34_qe; + + // F[input_disable_34]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_34_input_disable_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_input_disable_34_wd), + .d (hw2reg.dio_pad_attr[34].input_disable.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[7]), + .q (reg2hw.dio_pad_attr[34].input_disable.q), + .ds (), + .qs (dio_pad_attr_34_input_disable_34_qs) + ); + assign reg2hw.dio_pad_attr[34].input_disable.qe = dio_pad_attr_34_qe; + + // F[slew_rate_34]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_34_slew_rate_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_slew_rate_34_wd), + .d (hw2reg.dio_pad_attr[34].slew_rate.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[8]), + .q (reg2hw.dio_pad_attr[34].slew_rate.q), + .ds (), + .qs (dio_pad_attr_34_slew_rate_34_qs) + ); + assign reg2hw.dio_pad_attr[34].slew_rate.qe = dio_pad_attr_34_qe; + + // F[drive_strength_34]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_34_drive_strength_34 ( + .re (dio_pad_attr_34_re), + .we (dio_pad_attr_34_gated_we), + .wd (dio_pad_attr_34_drive_strength_34_wd), + .d (hw2reg.dio_pad_attr[34].drive_strength.d), + .qre (), + .qe (dio_pad_attr_34_flds_we[9]), + .q (reg2hw.dio_pad_attr[34].drive_strength.q), + .ds (), + .qs (dio_pad_attr_34_drive_strength_34_qs) + ); + assign reg2hw.dio_pad_attr[34].drive_strength.qe = dio_pad_attr_34_qe; + + + // Subregister 35 of Multireg dio_pad_attr + // R[dio_pad_attr_35]: V(True) + logic dio_pad_attr_35_qe; + logic [9:0] dio_pad_attr_35_flds_we; + assign dio_pad_attr_35_qe = &dio_pad_attr_35_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_35_gated_we; + assign dio_pad_attr_35_gated_we = dio_pad_attr_35_we & dio_pad_attr_regwen_35_qs; + // F[invert_35]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_invert_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_invert_35_wd), + .d (hw2reg.dio_pad_attr[35].invert.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[0]), + .q (reg2hw.dio_pad_attr[35].invert.q), + .ds (), + .qs (dio_pad_attr_35_invert_35_qs) + ); + assign reg2hw.dio_pad_attr[35].invert.qe = dio_pad_attr_35_qe; + + // F[virtual_od_en_35]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_virtual_od_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_virtual_od_en_35_wd), + .d (hw2reg.dio_pad_attr[35].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[1]), + .q (reg2hw.dio_pad_attr[35].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_35_virtual_od_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].virtual_od_en.qe = dio_pad_attr_35_qe; + + // F[pull_en_35]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_pull_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_pull_en_35_wd), + .d (hw2reg.dio_pad_attr[35].pull_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[2]), + .q (reg2hw.dio_pad_attr[35].pull_en.q), + .ds (), + .qs (dio_pad_attr_35_pull_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].pull_en.qe = dio_pad_attr_35_qe; + + // F[pull_select_35]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_pull_select_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_pull_select_35_wd), + .d (hw2reg.dio_pad_attr[35].pull_select.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[3]), + .q (reg2hw.dio_pad_attr[35].pull_select.q), + .ds (), + .qs (dio_pad_attr_35_pull_select_35_qs) + ); + assign reg2hw.dio_pad_attr[35].pull_select.qe = dio_pad_attr_35_qe; + + // F[keeper_en_35]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_keeper_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_keeper_en_35_wd), + .d (hw2reg.dio_pad_attr[35].keeper_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[4]), + .q (reg2hw.dio_pad_attr[35].keeper_en.q), + .ds (), + .qs (dio_pad_attr_35_keeper_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].keeper_en.qe = dio_pad_attr_35_qe; + + // F[schmitt_en_35]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_schmitt_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_schmitt_en_35_wd), + .d (hw2reg.dio_pad_attr[35].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[5]), + .q (reg2hw.dio_pad_attr[35].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_35_schmitt_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].schmitt_en.qe = dio_pad_attr_35_qe; + + // F[od_en_35]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_od_en_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_od_en_35_wd), + .d (hw2reg.dio_pad_attr[35].od_en.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[6]), + .q (reg2hw.dio_pad_attr[35].od_en.q), + .ds (), + .qs (dio_pad_attr_35_od_en_35_qs) + ); + assign reg2hw.dio_pad_attr[35].od_en.qe = dio_pad_attr_35_qe; + + // F[input_disable_35]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_35_input_disable_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_input_disable_35_wd), + .d (hw2reg.dio_pad_attr[35].input_disable.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[7]), + .q (reg2hw.dio_pad_attr[35].input_disable.q), + .ds (), + .qs (dio_pad_attr_35_input_disable_35_qs) + ); + assign reg2hw.dio_pad_attr[35].input_disable.qe = dio_pad_attr_35_qe; + + // F[slew_rate_35]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_35_slew_rate_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_slew_rate_35_wd), + .d (hw2reg.dio_pad_attr[35].slew_rate.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[8]), + .q (reg2hw.dio_pad_attr[35].slew_rate.q), + .ds (), + .qs (dio_pad_attr_35_slew_rate_35_qs) + ); + assign reg2hw.dio_pad_attr[35].slew_rate.qe = dio_pad_attr_35_qe; + + // F[drive_strength_35]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_35_drive_strength_35 ( + .re (dio_pad_attr_35_re), + .we (dio_pad_attr_35_gated_we), + .wd (dio_pad_attr_35_drive_strength_35_wd), + .d (hw2reg.dio_pad_attr[35].drive_strength.d), + .qre (), + .qe (dio_pad_attr_35_flds_we[9]), + .q (reg2hw.dio_pad_attr[35].drive_strength.q), + .ds (), + .qs (dio_pad_attr_35_drive_strength_35_qs) + ); + assign reg2hw.dio_pad_attr[35].drive_strength.qe = dio_pad_attr_35_qe; + + + // Subregister 36 of Multireg dio_pad_attr + // R[dio_pad_attr_36]: V(True) + logic dio_pad_attr_36_qe; + logic [9:0] dio_pad_attr_36_flds_we; + assign dio_pad_attr_36_qe = &dio_pad_attr_36_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_36_gated_we; + assign dio_pad_attr_36_gated_we = dio_pad_attr_36_we & dio_pad_attr_regwen_36_qs; + // F[invert_36]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_invert_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_invert_36_wd), + .d (hw2reg.dio_pad_attr[36].invert.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[0]), + .q (reg2hw.dio_pad_attr[36].invert.q), + .ds (), + .qs (dio_pad_attr_36_invert_36_qs) + ); + assign reg2hw.dio_pad_attr[36].invert.qe = dio_pad_attr_36_qe; + + // F[virtual_od_en_36]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_virtual_od_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_virtual_od_en_36_wd), + .d (hw2reg.dio_pad_attr[36].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[1]), + .q (reg2hw.dio_pad_attr[36].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_36_virtual_od_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].virtual_od_en.qe = dio_pad_attr_36_qe; + + // F[pull_en_36]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_pull_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_pull_en_36_wd), + .d (hw2reg.dio_pad_attr[36].pull_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[2]), + .q (reg2hw.dio_pad_attr[36].pull_en.q), + .ds (), + .qs (dio_pad_attr_36_pull_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].pull_en.qe = dio_pad_attr_36_qe; + + // F[pull_select_36]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_pull_select_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_pull_select_36_wd), + .d (hw2reg.dio_pad_attr[36].pull_select.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[3]), + .q (reg2hw.dio_pad_attr[36].pull_select.q), + .ds (), + .qs (dio_pad_attr_36_pull_select_36_qs) + ); + assign reg2hw.dio_pad_attr[36].pull_select.qe = dio_pad_attr_36_qe; + + // F[keeper_en_36]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_keeper_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_keeper_en_36_wd), + .d (hw2reg.dio_pad_attr[36].keeper_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[4]), + .q (reg2hw.dio_pad_attr[36].keeper_en.q), + .ds (), + .qs (dio_pad_attr_36_keeper_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].keeper_en.qe = dio_pad_attr_36_qe; + + // F[schmitt_en_36]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_schmitt_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_schmitt_en_36_wd), + .d (hw2reg.dio_pad_attr[36].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[5]), + .q (reg2hw.dio_pad_attr[36].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_36_schmitt_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].schmitt_en.qe = dio_pad_attr_36_qe; + + // F[od_en_36]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_od_en_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_od_en_36_wd), + .d (hw2reg.dio_pad_attr[36].od_en.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[6]), + .q (reg2hw.dio_pad_attr[36].od_en.q), + .ds (), + .qs (dio_pad_attr_36_od_en_36_qs) + ); + assign reg2hw.dio_pad_attr[36].od_en.qe = dio_pad_attr_36_qe; + + // F[input_disable_36]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_36_input_disable_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_input_disable_36_wd), + .d (hw2reg.dio_pad_attr[36].input_disable.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[7]), + .q (reg2hw.dio_pad_attr[36].input_disable.q), + .ds (), + .qs (dio_pad_attr_36_input_disable_36_qs) + ); + assign reg2hw.dio_pad_attr[36].input_disable.qe = dio_pad_attr_36_qe; + + // F[slew_rate_36]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_36_slew_rate_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_slew_rate_36_wd), + .d (hw2reg.dio_pad_attr[36].slew_rate.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[8]), + .q (reg2hw.dio_pad_attr[36].slew_rate.q), + .ds (), + .qs (dio_pad_attr_36_slew_rate_36_qs) + ); + assign reg2hw.dio_pad_attr[36].slew_rate.qe = dio_pad_attr_36_qe; + + // F[drive_strength_36]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_36_drive_strength_36 ( + .re (dio_pad_attr_36_re), + .we (dio_pad_attr_36_gated_we), + .wd (dio_pad_attr_36_drive_strength_36_wd), + .d (hw2reg.dio_pad_attr[36].drive_strength.d), + .qre (), + .qe (dio_pad_attr_36_flds_we[9]), + .q (reg2hw.dio_pad_attr[36].drive_strength.q), + .ds (), + .qs (dio_pad_attr_36_drive_strength_36_qs) + ); + assign reg2hw.dio_pad_attr[36].drive_strength.qe = dio_pad_attr_36_qe; + + + // Subregister 37 of Multireg dio_pad_attr + // R[dio_pad_attr_37]: V(True) + logic dio_pad_attr_37_qe; + logic [9:0] dio_pad_attr_37_flds_we; + assign dio_pad_attr_37_qe = &dio_pad_attr_37_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_37_gated_we; + assign dio_pad_attr_37_gated_we = dio_pad_attr_37_we & dio_pad_attr_regwen_37_qs; + // F[invert_37]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_invert_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_invert_37_wd), + .d (hw2reg.dio_pad_attr[37].invert.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[0]), + .q (reg2hw.dio_pad_attr[37].invert.q), + .ds (), + .qs (dio_pad_attr_37_invert_37_qs) + ); + assign reg2hw.dio_pad_attr[37].invert.qe = dio_pad_attr_37_qe; + + // F[virtual_od_en_37]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_virtual_od_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_virtual_od_en_37_wd), + .d (hw2reg.dio_pad_attr[37].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[1]), + .q (reg2hw.dio_pad_attr[37].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_37_virtual_od_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].virtual_od_en.qe = dio_pad_attr_37_qe; + + // F[pull_en_37]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_pull_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_pull_en_37_wd), + .d (hw2reg.dio_pad_attr[37].pull_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[2]), + .q (reg2hw.dio_pad_attr[37].pull_en.q), + .ds (), + .qs (dio_pad_attr_37_pull_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].pull_en.qe = dio_pad_attr_37_qe; + + // F[pull_select_37]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_pull_select_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_pull_select_37_wd), + .d (hw2reg.dio_pad_attr[37].pull_select.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[3]), + .q (reg2hw.dio_pad_attr[37].pull_select.q), + .ds (), + .qs (dio_pad_attr_37_pull_select_37_qs) + ); + assign reg2hw.dio_pad_attr[37].pull_select.qe = dio_pad_attr_37_qe; + + // F[keeper_en_37]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_keeper_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_keeper_en_37_wd), + .d (hw2reg.dio_pad_attr[37].keeper_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[4]), + .q (reg2hw.dio_pad_attr[37].keeper_en.q), + .ds (), + .qs (dio_pad_attr_37_keeper_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].keeper_en.qe = dio_pad_attr_37_qe; + + // F[schmitt_en_37]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_schmitt_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_schmitt_en_37_wd), + .d (hw2reg.dio_pad_attr[37].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[5]), + .q (reg2hw.dio_pad_attr[37].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_37_schmitt_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].schmitt_en.qe = dio_pad_attr_37_qe; + + // F[od_en_37]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_od_en_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_od_en_37_wd), + .d (hw2reg.dio_pad_attr[37].od_en.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[6]), + .q (reg2hw.dio_pad_attr[37].od_en.q), + .ds (), + .qs (dio_pad_attr_37_od_en_37_qs) + ); + assign reg2hw.dio_pad_attr[37].od_en.qe = dio_pad_attr_37_qe; + + // F[input_disable_37]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_37_input_disable_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_input_disable_37_wd), + .d (hw2reg.dio_pad_attr[37].input_disable.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[7]), + .q (reg2hw.dio_pad_attr[37].input_disable.q), + .ds (), + .qs (dio_pad_attr_37_input_disable_37_qs) + ); + assign reg2hw.dio_pad_attr[37].input_disable.qe = dio_pad_attr_37_qe; + + // F[slew_rate_37]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_37_slew_rate_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_slew_rate_37_wd), + .d (hw2reg.dio_pad_attr[37].slew_rate.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[8]), + .q (reg2hw.dio_pad_attr[37].slew_rate.q), + .ds (), + .qs (dio_pad_attr_37_slew_rate_37_qs) + ); + assign reg2hw.dio_pad_attr[37].slew_rate.qe = dio_pad_attr_37_qe; + + // F[drive_strength_37]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_37_drive_strength_37 ( + .re (dio_pad_attr_37_re), + .we (dio_pad_attr_37_gated_we), + .wd (dio_pad_attr_37_drive_strength_37_wd), + .d (hw2reg.dio_pad_attr[37].drive_strength.d), + .qre (), + .qe (dio_pad_attr_37_flds_we[9]), + .q (reg2hw.dio_pad_attr[37].drive_strength.q), + .ds (), + .qs (dio_pad_attr_37_drive_strength_37_qs) + ); + assign reg2hw.dio_pad_attr[37].drive_strength.qe = dio_pad_attr_37_qe; + + + // Subregister 38 of Multireg dio_pad_attr + // R[dio_pad_attr_38]: V(True) + logic dio_pad_attr_38_qe; + logic [9:0] dio_pad_attr_38_flds_we; + assign dio_pad_attr_38_qe = &dio_pad_attr_38_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_38_gated_we; + assign dio_pad_attr_38_gated_we = dio_pad_attr_38_we & dio_pad_attr_regwen_38_qs; + // F[invert_38]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_invert_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_invert_38_wd), + .d (hw2reg.dio_pad_attr[38].invert.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[0]), + .q (reg2hw.dio_pad_attr[38].invert.q), + .ds (), + .qs (dio_pad_attr_38_invert_38_qs) + ); + assign reg2hw.dio_pad_attr[38].invert.qe = dio_pad_attr_38_qe; + + // F[virtual_od_en_38]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_virtual_od_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_virtual_od_en_38_wd), + .d (hw2reg.dio_pad_attr[38].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[1]), + .q (reg2hw.dio_pad_attr[38].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_38_virtual_od_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].virtual_od_en.qe = dio_pad_attr_38_qe; + + // F[pull_en_38]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_pull_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_pull_en_38_wd), + .d (hw2reg.dio_pad_attr[38].pull_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[2]), + .q (reg2hw.dio_pad_attr[38].pull_en.q), + .ds (), + .qs (dio_pad_attr_38_pull_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].pull_en.qe = dio_pad_attr_38_qe; + + // F[pull_select_38]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_pull_select_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_pull_select_38_wd), + .d (hw2reg.dio_pad_attr[38].pull_select.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[3]), + .q (reg2hw.dio_pad_attr[38].pull_select.q), + .ds (), + .qs (dio_pad_attr_38_pull_select_38_qs) + ); + assign reg2hw.dio_pad_attr[38].pull_select.qe = dio_pad_attr_38_qe; + + // F[keeper_en_38]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_keeper_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_keeper_en_38_wd), + .d (hw2reg.dio_pad_attr[38].keeper_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[4]), + .q (reg2hw.dio_pad_attr[38].keeper_en.q), + .ds (), + .qs (dio_pad_attr_38_keeper_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].keeper_en.qe = dio_pad_attr_38_qe; + + // F[schmitt_en_38]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_schmitt_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_schmitt_en_38_wd), + .d (hw2reg.dio_pad_attr[38].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[5]), + .q (reg2hw.dio_pad_attr[38].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_38_schmitt_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].schmitt_en.qe = dio_pad_attr_38_qe; + + // F[od_en_38]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_od_en_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_od_en_38_wd), + .d (hw2reg.dio_pad_attr[38].od_en.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[6]), + .q (reg2hw.dio_pad_attr[38].od_en.q), + .ds (), + .qs (dio_pad_attr_38_od_en_38_qs) + ); + assign reg2hw.dio_pad_attr[38].od_en.qe = dio_pad_attr_38_qe; + + // F[input_disable_38]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_38_input_disable_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_input_disable_38_wd), + .d (hw2reg.dio_pad_attr[38].input_disable.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[7]), + .q (reg2hw.dio_pad_attr[38].input_disable.q), + .ds (), + .qs (dio_pad_attr_38_input_disable_38_qs) + ); + assign reg2hw.dio_pad_attr[38].input_disable.qe = dio_pad_attr_38_qe; + + // F[slew_rate_38]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_38_slew_rate_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_slew_rate_38_wd), + .d (hw2reg.dio_pad_attr[38].slew_rate.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[8]), + .q (reg2hw.dio_pad_attr[38].slew_rate.q), + .ds (), + .qs (dio_pad_attr_38_slew_rate_38_qs) + ); + assign reg2hw.dio_pad_attr[38].slew_rate.qe = dio_pad_attr_38_qe; + + // F[drive_strength_38]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_38_drive_strength_38 ( + .re (dio_pad_attr_38_re), + .we (dio_pad_attr_38_gated_we), + .wd (dio_pad_attr_38_drive_strength_38_wd), + .d (hw2reg.dio_pad_attr[38].drive_strength.d), + .qre (), + .qe (dio_pad_attr_38_flds_we[9]), + .q (reg2hw.dio_pad_attr[38].drive_strength.q), + .ds (), + .qs (dio_pad_attr_38_drive_strength_38_qs) + ); + assign reg2hw.dio_pad_attr[38].drive_strength.qe = dio_pad_attr_38_qe; + + + // Subregister 39 of Multireg dio_pad_attr + // R[dio_pad_attr_39]: V(True) + logic dio_pad_attr_39_qe; + logic [9:0] dio_pad_attr_39_flds_we; + assign dio_pad_attr_39_qe = &dio_pad_attr_39_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_39_gated_we; + assign dio_pad_attr_39_gated_we = dio_pad_attr_39_we & dio_pad_attr_regwen_39_qs; + // F[invert_39]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_invert_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_invert_39_wd), + .d (hw2reg.dio_pad_attr[39].invert.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[0]), + .q (reg2hw.dio_pad_attr[39].invert.q), + .ds (), + .qs (dio_pad_attr_39_invert_39_qs) + ); + assign reg2hw.dio_pad_attr[39].invert.qe = dio_pad_attr_39_qe; + + // F[virtual_od_en_39]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_virtual_od_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_virtual_od_en_39_wd), + .d (hw2reg.dio_pad_attr[39].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[1]), + .q (reg2hw.dio_pad_attr[39].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_39_virtual_od_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].virtual_od_en.qe = dio_pad_attr_39_qe; + + // F[pull_en_39]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_pull_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_pull_en_39_wd), + .d (hw2reg.dio_pad_attr[39].pull_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[2]), + .q (reg2hw.dio_pad_attr[39].pull_en.q), + .ds (), + .qs (dio_pad_attr_39_pull_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].pull_en.qe = dio_pad_attr_39_qe; + + // F[pull_select_39]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_pull_select_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_pull_select_39_wd), + .d (hw2reg.dio_pad_attr[39].pull_select.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[3]), + .q (reg2hw.dio_pad_attr[39].pull_select.q), + .ds (), + .qs (dio_pad_attr_39_pull_select_39_qs) + ); + assign reg2hw.dio_pad_attr[39].pull_select.qe = dio_pad_attr_39_qe; + + // F[keeper_en_39]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_keeper_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_keeper_en_39_wd), + .d (hw2reg.dio_pad_attr[39].keeper_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[4]), + .q (reg2hw.dio_pad_attr[39].keeper_en.q), + .ds (), + .qs (dio_pad_attr_39_keeper_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].keeper_en.qe = dio_pad_attr_39_qe; + + // F[schmitt_en_39]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_schmitt_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_schmitt_en_39_wd), + .d (hw2reg.dio_pad_attr[39].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[5]), + .q (reg2hw.dio_pad_attr[39].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_39_schmitt_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].schmitt_en.qe = dio_pad_attr_39_qe; + + // F[od_en_39]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_od_en_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_od_en_39_wd), + .d (hw2reg.dio_pad_attr[39].od_en.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[6]), + .q (reg2hw.dio_pad_attr[39].od_en.q), + .ds (), + .qs (dio_pad_attr_39_od_en_39_qs) + ); + assign reg2hw.dio_pad_attr[39].od_en.qe = dio_pad_attr_39_qe; + + // F[input_disable_39]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_39_input_disable_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_input_disable_39_wd), + .d (hw2reg.dio_pad_attr[39].input_disable.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[7]), + .q (reg2hw.dio_pad_attr[39].input_disable.q), + .ds (), + .qs (dio_pad_attr_39_input_disable_39_qs) + ); + assign reg2hw.dio_pad_attr[39].input_disable.qe = dio_pad_attr_39_qe; + + // F[slew_rate_39]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_39_slew_rate_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_slew_rate_39_wd), + .d (hw2reg.dio_pad_attr[39].slew_rate.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[8]), + .q (reg2hw.dio_pad_attr[39].slew_rate.q), + .ds (), + .qs (dio_pad_attr_39_slew_rate_39_qs) + ); + assign reg2hw.dio_pad_attr[39].slew_rate.qe = dio_pad_attr_39_qe; + + // F[drive_strength_39]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_39_drive_strength_39 ( + .re (dio_pad_attr_39_re), + .we (dio_pad_attr_39_gated_we), + .wd (dio_pad_attr_39_drive_strength_39_wd), + .d (hw2reg.dio_pad_attr[39].drive_strength.d), + .qre (), + .qe (dio_pad_attr_39_flds_we[9]), + .q (reg2hw.dio_pad_attr[39].drive_strength.q), + .ds (), + .qs (dio_pad_attr_39_drive_strength_39_qs) + ); + assign reg2hw.dio_pad_attr[39].drive_strength.qe = dio_pad_attr_39_qe; + + + // Subregister 40 of Multireg dio_pad_attr + // R[dio_pad_attr_40]: V(True) + logic dio_pad_attr_40_qe; + logic [9:0] dio_pad_attr_40_flds_we; + assign dio_pad_attr_40_qe = &dio_pad_attr_40_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_40_gated_we; + assign dio_pad_attr_40_gated_we = dio_pad_attr_40_we & dio_pad_attr_regwen_40_qs; + // F[invert_40]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_invert_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_invert_40_wd), + .d (hw2reg.dio_pad_attr[40].invert.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[0]), + .q (reg2hw.dio_pad_attr[40].invert.q), + .ds (), + .qs (dio_pad_attr_40_invert_40_qs) + ); + assign reg2hw.dio_pad_attr[40].invert.qe = dio_pad_attr_40_qe; + + // F[virtual_od_en_40]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_virtual_od_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_virtual_od_en_40_wd), + .d (hw2reg.dio_pad_attr[40].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[1]), + .q (reg2hw.dio_pad_attr[40].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_40_virtual_od_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].virtual_od_en.qe = dio_pad_attr_40_qe; + + // F[pull_en_40]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_pull_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_pull_en_40_wd), + .d (hw2reg.dio_pad_attr[40].pull_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[2]), + .q (reg2hw.dio_pad_attr[40].pull_en.q), + .ds (), + .qs (dio_pad_attr_40_pull_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].pull_en.qe = dio_pad_attr_40_qe; + + // F[pull_select_40]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_pull_select_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_pull_select_40_wd), + .d (hw2reg.dio_pad_attr[40].pull_select.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[3]), + .q (reg2hw.dio_pad_attr[40].pull_select.q), + .ds (), + .qs (dio_pad_attr_40_pull_select_40_qs) + ); + assign reg2hw.dio_pad_attr[40].pull_select.qe = dio_pad_attr_40_qe; + + // F[keeper_en_40]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_keeper_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_keeper_en_40_wd), + .d (hw2reg.dio_pad_attr[40].keeper_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[4]), + .q (reg2hw.dio_pad_attr[40].keeper_en.q), + .ds (), + .qs (dio_pad_attr_40_keeper_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].keeper_en.qe = dio_pad_attr_40_qe; + + // F[schmitt_en_40]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_schmitt_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_schmitt_en_40_wd), + .d (hw2reg.dio_pad_attr[40].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[5]), + .q (reg2hw.dio_pad_attr[40].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_40_schmitt_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].schmitt_en.qe = dio_pad_attr_40_qe; + + // F[od_en_40]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_od_en_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_od_en_40_wd), + .d (hw2reg.dio_pad_attr[40].od_en.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[6]), + .q (reg2hw.dio_pad_attr[40].od_en.q), + .ds (), + .qs (dio_pad_attr_40_od_en_40_qs) + ); + assign reg2hw.dio_pad_attr[40].od_en.qe = dio_pad_attr_40_qe; + + // F[input_disable_40]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_40_input_disable_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_input_disable_40_wd), + .d (hw2reg.dio_pad_attr[40].input_disable.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[7]), + .q (reg2hw.dio_pad_attr[40].input_disable.q), + .ds (), + .qs (dio_pad_attr_40_input_disable_40_qs) + ); + assign reg2hw.dio_pad_attr[40].input_disable.qe = dio_pad_attr_40_qe; + + // F[slew_rate_40]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_40_slew_rate_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_slew_rate_40_wd), + .d (hw2reg.dio_pad_attr[40].slew_rate.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[8]), + .q (reg2hw.dio_pad_attr[40].slew_rate.q), + .ds (), + .qs (dio_pad_attr_40_slew_rate_40_qs) + ); + assign reg2hw.dio_pad_attr[40].slew_rate.qe = dio_pad_attr_40_qe; + + // F[drive_strength_40]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_40_drive_strength_40 ( + .re (dio_pad_attr_40_re), + .we (dio_pad_attr_40_gated_we), + .wd (dio_pad_attr_40_drive_strength_40_wd), + .d (hw2reg.dio_pad_attr[40].drive_strength.d), + .qre (), + .qe (dio_pad_attr_40_flds_we[9]), + .q (reg2hw.dio_pad_attr[40].drive_strength.q), + .ds (), + .qs (dio_pad_attr_40_drive_strength_40_qs) + ); + assign reg2hw.dio_pad_attr[40].drive_strength.qe = dio_pad_attr_40_qe; + + + // Subregister 41 of Multireg dio_pad_attr + // R[dio_pad_attr_41]: V(True) + logic dio_pad_attr_41_qe; + logic [9:0] dio_pad_attr_41_flds_we; + assign dio_pad_attr_41_qe = &dio_pad_attr_41_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_41_gated_we; + assign dio_pad_attr_41_gated_we = dio_pad_attr_41_we & dio_pad_attr_regwen_41_qs; + // F[invert_41]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_invert_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_invert_41_wd), + .d (hw2reg.dio_pad_attr[41].invert.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[0]), + .q (reg2hw.dio_pad_attr[41].invert.q), + .ds (), + .qs (dio_pad_attr_41_invert_41_qs) + ); + assign reg2hw.dio_pad_attr[41].invert.qe = dio_pad_attr_41_qe; + + // F[virtual_od_en_41]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_virtual_od_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_virtual_od_en_41_wd), + .d (hw2reg.dio_pad_attr[41].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[1]), + .q (reg2hw.dio_pad_attr[41].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_41_virtual_od_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].virtual_od_en.qe = dio_pad_attr_41_qe; + + // F[pull_en_41]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_pull_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_pull_en_41_wd), + .d (hw2reg.dio_pad_attr[41].pull_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[2]), + .q (reg2hw.dio_pad_attr[41].pull_en.q), + .ds (), + .qs (dio_pad_attr_41_pull_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].pull_en.qe = dio_pad_attr_41_qe; + + // F[pull_select_41]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_pull_select_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_pull_select_41_wd), + .d (hw2reg.dio_pad_attr[41].pull_select.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[3]), + .q (reg2hw.dio_pad_attr[41].pull_select.q), + .ds (), + .qs (dio_pad_attr_41_pull_select_41_qs) + ); + assign reg2hw.dio_pad_attr[41].pull_select.qe = dio_pad_attr_41_qe; + + // F[keeper_en_41]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_keeper_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_keeper_en_41_wd), + .d (hw2reg.dio_pad_attr[41].keeper_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[4]), + .q (reg2hw.dio_pad_attr[41].keeper_en.q), + .ds (), + .qs (dio_pad_attr_41_keeper_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].keeper_en.qe = dio_pad_attr_41_qe; + + // F[schmitt_en_41]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_schmitt_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_schmitt_en_41_wd), + .d (hw2reg.dio_pad_attr[41].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[5]), + .q (reg2hw.dio_pad_attr[41].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_41_schmitt_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].schmitt_en.qe = dio_pad_attr_41_qe; + + // F[od_en_41]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_od_en_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_od_en_41_wd), + .d (hw2reg.dio_pad_attr[41].od_en.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[6]), + .q (reg2hw.dio_pad_attr[41].od_en.q), + .ds (), + .qs (dio_pad_attr_41_od_en_41_qs) + ); + assign reg2hw.dio_pad_attr[41].od_en.qe = dio_pad_attr_41_qe; + + // F[input_disable_41]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_41_input_disable_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_input_disable_41_wd), + .d (hw2reg.dio_pad_attr[41].input_disable.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[7]), + .q (reg2hw.dio_pad_attr[41].input_disable.q), + .ds (), + .qs (dio_pad_attr_41_input_disable_41_qs) + ); + assign reg2hw.dio_pad_attr[41].input_disable.qe = dio_pad_attr_41_qe; + + // F[slew_rate_41]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_41_slew_rate_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_slew_rate_41_wd), + .d (hw2reg.dio_pad_attr[41].slew_rate.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[8]), + .q (reg2hw.dio_pad_attr[41].slew_rate.q), + .ds (), + .qs (dio_pad_attr_41_slew_rate_41_qs) + ); + assign reg2hw.dio_pad_attr[41].slew_rate.qe = dio_pad_attr_41_qe; + + // F[drive_strength_41]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_41_drive_strength_41 ( + .re (dio_pad_attr_41_re), + .we (dio_pad_attr_41_gated_we), + .wd (dio_pad_attr_41_drive_strength_41_wd), + .d (hw2reg.dio_pad_attr[41].drive_strength.d), + .qre (), + .qe (dio_pad_attr_41_flds_we[9]), + .q (reg2hw.dio_pad_attr[41].drive_strength.q), + .ds (), + .qs (dio_pad_attr_41_drive_strength_41_qs) + ); + assign reg2hw.dio_pad_attr[41].drive_strength.qe = dio_pad_attr_41_qe; + + + // Subregister 42 of Multireg dio_pad_attr + // R[dio_pad_attr_42]: V(True) + logic dio_pad_attr_42_qe; + logic [9:0] dio_pad_attr_42_flds_we; + assign dio_pad_attr_42_qe = &dio_pad_attr_42_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_42_gated_we; + assign dio_pad_attr_42_gated_we = dio_pad_attr_42_we & dio_pad_attr_regwen_42_qs; + // F[invert_42]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_invert_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_invert_42_wd), + .d (hw2reg.dio_pad_attr[42].invert.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[0]), + .q (reg2hw.dio_pad_attr[42].invert.q), + .ds (), + .qs (dio_pad_attr_42_invert_42_qs) + ); + assign reg2hw.dio_pad_attr[42].invert.qe = dio_pad_attr_42_qe; + + // F[virtual_od_en_42]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_virtual_od_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_virtual_od_en_42_wd), + .d (hw2reg.dio_pad_attr[42].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[1]), + .q (reg2hw.dio_pad_attr[42].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_42_virtual_od_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].virtual_od_en.qe = dio_pad_attr_42_qe; + + // F[pull_en_42]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_pull_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_pull_en_42_wd), + .d (hw2reg.dio_pad_attr[42].pull_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[2]), + .q (reg2hw.dio_pad_attr[42].pull_en.q), + .ds (), + .qs (dio_pad_attr_42_pull_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].pull_en.qe = dio_pad_attr_42_qe; + + // F[pull_select_42]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_pull_select_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_pull_select_42_wd), + .d (hw2reg.dio_pad_attr[42].pull_select.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[3]), + .q (reg2hw.dio_pad_attr[42].pull_select.q), + .ds (), + .qs (dio_pad_attr_42_pull_select_42_qs) + ); + assign reg2hw.dio_pad_attr[42].pull_select.qe = dio_pad_attr_42_qe; + + // F[keeper_en_42]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_keeper_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_keeper_en_42_wd), + .d (hw2reg.dio_pad_attr[42].keeper_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[4]), + .q (reg2hw.dio_pad_attr[42].keeper_en.q), + .ds (), + .qs (dio_pad_attr_42_keeper_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].keeper_en.qe = dio_pad_attr_42_qe; + + // F[schmitt_en_42]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_schmitt_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_schmitt_en_42_wd), + .d (hw2reg.dio_pad_attr[42].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[5]), + .q (reg2hw.dio_pad_attr[42].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_42_schmitt_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].schmitt_en.qe = dio_pad_attr_42_qe; + + // F[od_en_42]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_od_en_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_od_en_42_wd), + .d (hw2reg.dio_pad_attr[42].od_en.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[6]), + .q (reg2hw.dio_pad_attr[42].od_en.q), + .ds (), + .qs (dio_pad_attr_42_od_en_42_qs) + ); + assign reg2hw.dio_pad_attr[42].od_en.qe = dio_pad_attr_42_qe; + + // F[input_disable_42]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_42_input_disable_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_input_disable_42_wd), + .d (hw2reg.dio_pad_attr[42].input_disable.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[7]), + .q (reg2hw.dio_pad_attr[42].input_disable.q), + .ds (), + .qs (dio_pad_attr_42_input_disable_42_qs) + ); + assign reg2hw.dio_pad_attr[42].input_disable.qe = dio_pad_attr_42_qe; + + // F[slew_rate_42]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_42_slew_rate_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_slew_rate_42_wd), + .d (hw2reg.dio_pad_attr[42].slew_rate.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[8]), + .q (reg2hw.dio_pad_attr[42].slew_rate.q), + .ds (), + .qs (dio_pad_attr_42_slew_rate_42_qs) + ); + assign reg2hw.dio_pad_attr[42].slew_rate.qe = dio_pad_attr_42_qe; + + // F[drive_strength_42]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_42_drive_strength_42 ( + .re (dio_pad_attr_42_re), + .we (dio_pad_attr_42_gated_we), + .wd (dio_pad_attr_42_drive_strength_42_wd), + .d (hw2reg.dio_pad_attr[42].drive_strength.d), + .qre (), + .qe (dio_pad_attr_42_flds_we[9]), + .q (reg2hw.dio_pad_attr[42].drive_strength.q), + .ds (), + .qs (dio_pad_attr_42_drive_strength_42_qs) + ); + assign reg2hw.dio_pad_attr[42].drive_strength.qe = dio_pad_attr_42_qe; + + + // Subregister 43 of Multireg dio_pad_attr + // R[dio_pad_attr_43]: V(True) + logic dio_pad_attr_43_qe; + logic [9:0] dio_pad_attr_43_flds_we; + assign dio_pad_attr_43_qe = &dio_pad_attr_43_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_43_gated_we; + assign dio_pad_attr_43_gated_we = dio_pad_attr_43_we & dio_pad_attr_regwen_43_qs; + // F[invert_43]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_invert_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_invert_43_wd), + .d (hw2reg.dio_pad_attr[43].invert.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[0]), + .q (reg2hw.dio_pad_attr[43].invert.q), + .ds (), + .qs (dio_pad_attr_43_invert_43_qs) + ); + assign reg2hw.dio_pad_attr[43].invert.qe = dio_pad_attr_43_qe; + + // F[virtual_od_en_43]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_virtual_od_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_virtual_od_en_43_wd), + .d (hw2reg.dio_pad_attr[43].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[1]), + .q (reg2hw.dio_pad_attr[43].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_43_virtual_od_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].virtual_od_en.qe = dio_pad_attr_43_qe; + + // F[pull_en_43]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_pull_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_pull_en_43_wd), + .d (hw2reg.dio_pad_attr[43].pull_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[2]), + .q (reg2hw.dio_pad_attr[43].pull_en.q), + .ds (), + .qs (dio_pad_attr_43_pull_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].pull_en.qe = dio_pad_attr_43_qe; + + // F[pull_select_43]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_pull_select_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_pull_select_43_wd), + .d (hw2reg.dio_pad_attr[43].pull_select.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[3]), + .q (reg2hw.dio_pad_attr[43].pull_select.q), + .ds (), + .qs (dio_pad_attr_43_pull_select_43_qs) + ); + assign reg2hw.dio_pad_attr[43].pull_select.qe = dio_pad_attr_43_qe; + + // F[keeper_en_43]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_keeper_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_keeper_en_43_wd), + .d (hw2reg.dio_pad_attr[43].keeper_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[4]), + .q (reg2hw.dio_pad_attr[43].keeper_en.q), + .ds (), + .qs (dio_pad_attr_43_keeper_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].keeper_en.qe = dio_pad_attr_43_qe; + + // F[schmitt_en_43]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_schmitt_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_schmitt_en_43_wd), + .d (hw2reg.dio_pad_attr[43].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[5]), + .q (reg2hw.dio_pad_attr[43].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_43_schmitt_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].schmitt_en.qe = dio_pad_attr_43_qe; + + // F[od_en_43]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_od_en_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_od_en_43_wd), + .d (hw2reg.dio_pad_attr[43].od_en.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[6]), + .q (reg2hw.dio_pad_attr[43].od_en.q), + .ds (), + .qs (dio_pad_attr_43_od_en_43_qs) + ); + assign reg2hw.dio_pad_attr[43].od_en.qe = dio_pad_attr_43_qe; + + // F[input_disable_43]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_43_input_disable_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_input_disable_43_wd), + .d (hw2reg.dio_pad_attr[43].input_disable.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[7]), + .q (reg2hw.dio_pad_attr[43].input_disable.q), + .ds (), + .qs (dio_pad_attr_43_input_disable_43_qs) + ); + assign reg2hw.dio_pad_attr[43].input_disable.qe = dio_pad_attr_43_qe; + + // F[slew_rate_43]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_43_slew_rate_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_slew_rate_43_wd), + .d (hw2reg.dio_pad_attr[43].slew_rate.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[8]), + .q (reg2hw.dio_pad_attr[43].slew_rate.q), + .ds (), + .qs (dio_pad_attr_43_slew_rate_43_qs) + ); + assign reg2hw.dio_pad_attr[43].slew_rate.qe = dio_pad_attr_43_qe; + + // F[drive_strength_43]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_43_drive_strength_43 ( + .re (dio_pad_attr_43_re), + .we (dio_pad_attr_43_gated_we), + .wd (dio_pad_attr_43_drive_strength_43_wd), + .d (hw2reg.dio_pad_attr[43].drive_strength.d), + .qre (), + .qe (dio_pad_attr_43_flds_we[9]), + .q (reg2hw.dio_pad_attr[43].drive_strength.q), + .ds (), + .qs (dio_pad_attr_43_drive_strength_43_qs) + ); + assign reg2hw.dio_pad_attr[43].drive_strength.qe = dio_pad_attr_43_qe; + + + // Subregister 44 of Multireg dio_pad_attr + // R[dio_pad_attr_44]: V(True) + logic dio_pad_attr_44_qe; + logic [9:0] dio_pad_attr_44_flds_we; + assign dio_pad_attr_44_qe = &dio_pad_attr_44_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_44_gated_we; + assign dio_pad_attr_44_gated_we = dio_pad_attr_44_we & dio_pad_attr_regwen_44_qs; + // F[invert_44]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_invert_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_invert_44_wd), + .d (hw2reg.dio_pad_attr[44].invert.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[0]), + .q (reg2hw.dio_pad_attr[44].invert.q), + .ds (), + .qs (dio_pad_attr_44_invert_44_qs) + ); + assign reg2hw.dio_pad_attr[44].invert.qe = dio_pad_attr_44_qe; + + // F[virtual_od_en_44]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_virtual_od_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_virtual_od_en_44_wd), + .d (hw2reg.dio_pad_attr[44].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[1]), + .q (reg2hw.dio_pad_attr[44].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_44_virtual_od_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].virtual_od_en.qe = dio_pad_attr_44_qe; + + // F[pull_en_44]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_pull_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_pull_en_44_wd), + .d (hw2reg.dio_pad_attr[44].pull_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[2]), + .q (reg2hw.dio_pad_attr[44].pull_en.q), + .ds (), + .qs (dio_pad_attr_44_pull_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].pull_en.qe = dio_pad_attr_44_qe; + + // F[pull_select_44]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_pull_select_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_pull_select_44_wd), + .d (hw2reg.dio_pad_attr[44].pull_select.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[3]), + .q (reg2hw.dio_pad_attr[44].pull_select.q), + .ds (), + .qs (dio_pad_attr_44_pull_select_44_qs) + ); + assign reg2hw.dio_pad_attr[44].pull_select.qe = dio_pad_attr_44_qe; + + // F[keeper_en_44]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_keeper_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_keeper_en_44_wd), + .d (hw2reg.dio_pad_attr[44].keeper_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[4]), + .q (reg2hw.dio_pad_attr[44].keeper_en.q), + .ds (), + .qs (dio_pad_attr_44_keeper_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].keeper_en.qe = dio_pad_attr_44_qe; + + // F[schmitt_en_44]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_schmitt_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_schmitt_en_44_wd), + .d (hw2reg.dio_pad_attr[44].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[5]), + .q (reg2hw.dio_pad_attr[44].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_44_schmitt_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].schmitt_en.qe = dio_pad_attr_44_qe; + + // F[od_en_44]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_od_en_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_od_en_44_wd), + .d (hw2reg.dio_pad_attr[44].od_en.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[6]), + .q (reg2hw.dio_pad_attr[44].od_en.q), + .ds (), + .qs (dio_pad_attr_44_od_en_44_qs) + ); + assign reg2hw.dio_pad_attr[44].od_en.qe = dio_pad_attr_44_qe; + + // F[input_disable_44]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_44_input_disable_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_input_disable_44_wd), + .d (hw2reg.dio_pad_attr[44].input_disable.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[7]), + .q (reg2hw.dio_pad_attr[44].input_disable.q), + .ds (), + .qs (dio_pad_attr_44_input_disable_44_qs) + ); + assign reg2hw.dio_pad_attr[44].input_disable.qe = dio_pad_attr_44_qe; + + // F[slew_rate_44]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_44_slew_rate_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_slew_rate_44_wd), + .d (hw2reg.dio_pad_attr[44].slew_rate.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[8]), + .q (reg2hw.dio_pad_attr[44].slew_rate.q), + .ds (), + .qs (dio_pad_attr_44_slew_rate_44_qs) + ); + assign reg2hw.dio_pad_attr[44].slew_rate.qe = dio_pad_attr_44_qe; + + // F[drive_strength_44]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_44_drive_strength_44 ( + .re (dio_pad_attr_44_re), + .we (dio_pad_attr_44_gated_we), + .wd (dio_pad_attr_44_drive_strength_44_wd), + .d (hw2reg.dio_pad_attr[44].drive_strength.d), + .qre (), + .qe (dio_pad_attr_44_flds_we[9]), + .q (reg2hw.dio_pad_attr[44].drive_strength.q), + .ds (), + .qs (dio_pad_attr_44_drive_strength_44_qs) + ); + assign reg2hw.dio_pad_attr[44].drive_strength.qe = dio_pad_attr_44_qe; + + + // Subregister 45 of Multireg dio_pad_attr + // R[dio_pad_attr_45]: V(True) + logic dio_pad_attr_45_qe; + logic [9:0] dio_pad_attr_45_flds_we; + assign dio_pad_attr_45_qe = &dio_pad_attr_45_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_45_gated_we; + assign dio_pad_attr_45_gated_we = dio_pad_attr_45_we & dio_pad_attr_regwen_45_qs; + // F[invert_45]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_invert_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_invert_45_wd), + .d (hw2reg.dio_pad_attr[45].invert.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[0]), + .q (reg2hw.dio_pad_attr[45].invert.q), + .ds (), + .qs (dio_pad_attr_45_invert_45_qs) + ); + assign reg2hw.dio_pad_attr[45].invert.qe = dio_pad_attr_45_qe; + + // F[virtual_od_en_45]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_virtual_od_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_virtual_od_en_45_wd), + .d (hw2reg.dio_pad_attr[45].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[1]), + .q (reg2hw.dio_pad_attr[45].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_45_virtual_od_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].virtual_od_en.qe = dio_pad_attr_45_qe; + + // F[pull_en_45]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_pull_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_pull_en_45_wd), + .d (hw2reg.dio_pad_attr[45].pull_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[2]), + .q (reg2hw.dio_pad_attr[45].pull_en.q), + .ds (), + .qs (dio_pad_attr_45_pull_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].pull_en.qe = dio_pad_attr_45_qe; + + // F[pull_select_45]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_pull_select_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_pull_select_45_wd), + .d (hw2reg.dio_pad_attr[45].pull_select.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[3]), + .q (reg2hw.dio_pad_attr[45].pull_select.q), + .ds (), + .qs (dio_pad_attr_45_pull_select_45_qs) + ); + assign reg2hw.dio_pad_attr[45].pull_select.qe = dio_pad_attr_45_qe; + + // F[keeper_en_45]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_keeper_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_keeper_en_45_wd), + .d (hw2reg.dio_pad_attr[45].keeper_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[4]), + .q (reg2hw.dio_pad_attr[45].keeper_en.q), + .ds (), + .qs (dio_pad_attr_45_keeper_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].keeper_en.qe = dio_pad_attr_45_qe; + + // F[schmitt_en_45]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_schmitt_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_schmitt_en_45_wd), + .d (hw2reg.dio_pad_attr[45].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[5]), + .q (reg2hw.dio_pad_attr[45].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_45_schmitt_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].schmitt_en.qe = dio_pad_attr_45_qe; + + // F[od_en_45]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_od_en_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_od_en_45_wd), + .d (hw2reg.dio_pad_attr[45].od_en.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[6]), + .q (reg2hw.dio_pad_attr[45].od_en.q), + .ds (), + .qs (dio_pad_attr_45_od_en_45_qs) + ); + assign reg2hw.dio_pad_attr[45].od_en.qe = dio_pad_attr_45_qe; + + // F[input_disable_45]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_45_input_disable_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_input_disable_45_wd), + .d (hw2reg.dio_pad_attr[45].input_disable.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[7]), + .q (reg2hw.dio_pad_attr[45].input_disable.q), + .ds (), + .qs (dio_pad_attr_45_input_disable_45_qs) + ); + assign reg2hw.dio_pad_attr[45].input_disable.qe = dio_pad_attr_45_qe; + + // F[slew_rate_45]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_45_slew_rate_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_slew_rate_45_wd), + .d (hw2reg.dio_pad_attr[45].slew_rate.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[8]), + .q (reg2hw.dio_pad_attr[45].slew_rate.q), + .ds (), + .qs (dio_pad_attr_45_slew_rate_45_qs) + ); + assign reg2hw.dio_pad_attr[45].slew_rate.qe = dio_pad_attr_45_qe; + + // F[drive_strength_45]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_45_drive_strength_45 ( + .re (dio_pad_attr_45_re), + .we (dio_pad_attr_45_gated_we), + .wd (dio_pad_attr_45_drive_strength_45_wd), + .d (hw2reg.dio_pad_attr[45].drive_strength.d), + .qre (), + .qe (dio_pad_attr_45_flds_we[9]), + .q (reg2hw.dio_pad_attr[45].drive_strength.q), + .ds (), + .qs (dio_pad_attr_45_drive_strength_45_qs) + ); + assign reg2hw.dio_pad_attr[45].drive_strength.qe = dio_pad_attr_45_qe; + + + // Subregister 46 of Multireg dio_pad_attr + // R[dio_pad_attr_46]: V(True) + logic dio_pad_attr_46_qe; + logic [9:0] dio_pad_attr_46_flds_we; + assign dio_pad_attr_46_qe = &dio_pad_attr_46_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_46_gated_we; + assign dio_pad_attr_46_gated_we = dio_pad_attr_46_we & dio_pad_attr_regwen_46_qs; + // F[invert_46]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_invert_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_invert_46_wd), + .d (hw2reg.dio_pad_attr[46].invert.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[0]), + .q (reg2hw.dio_pad_attr[46].invert.q), + .ds (), + .qs (dio_pad_attr_46_invert_46_qs) + ); + assign reg2hw.dio_pad_attr[46].invert.qe = dio_pad_attr_46_qe; + + // F[virtual_od_en_46]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_virtual_od_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_virtual_od_en_46_wd), + .d (hw2reg.dio_pad_attr[46].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[1]), + .q (reg2hw.dio_pad_attr[46].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_46_virtual_od_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].virtual_od_en.qe = dio_pad_attr_46_qe; + + // F[pull_en_46]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_pull_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_pull_en_46_wd), + .d (hw2reg.dio_pad_attr[46].pull_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[2]), + .q (reg2hw.dio_pad_attr[46].pull_en.q), + .ds (), + .qs (dio_pad_attr_46_pull_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].pull_en.qe = dio_pad_attr_46_qe; + + // F[pull_select_46]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_pull_select_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_pull_select_46_wd), + .d (hw2reg.dio_pad_attr[46].pull_select.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[3]), + .q (reg2hw.dio_pad_attr[46].pull_select.q), + .ds (), + .qs (dio_pad_attr_46_pull_select_46_qs) + ); + assign reg2hw.dio_pad_attr[46].pull_select.qe = dio_pad_attr_46_qe; + + // F[keeper_en_46]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_keeper_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_keeper_en_46_wd), + .d (hw2reg.dio_pad_attr[46].keeper_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[4]), + .q (reg2hw.dio_pad_attr[46].keeper_en.q), + .ds (), + .qs (dio_pad_attr_46_keeper_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].keeper_en.qe = dio_pad_attr_46_qe; + + // F[schmitt_en_46]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_schmitt_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_schmitt_en_46_wd), + .d (hw2reg.dio_pad_attr[46].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[5]), + .q (reg2hw.dio_pad_attr[46].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_46_schmitt_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].schmitt_en.qe = dio_pad_attr_46_qe; + + // F[od_en_46]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_od_en_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_od_en_46_wd), + .d (hw2reg.dio_pad_attr[46].od_en.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[6]), + .q (reg2hw.dio_pad_attr[46].od_en.q), + .ds (), + .qs (dio_pad_attr_46_od_en_46_qs) + ); + assign reg2hw.dio_pad_attr[46].od_en.qe = dio_pad_attr_46_qe; + + // F[input_disable_46]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_46_input_disable_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_input_disable_46_wd), + .d (hw2reg.dio_pad_attr[46].input_disable.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[7]), + .q (reg2hw.dio_pad_attr[46].input_disable.q), + .ds (), + .qs (dio_pad_attr_46_input_disable_46_qs) + ); + assign reg2hw.dio_pad_attr[46].input_disable.qe = dio_pad_attr_46_qe; + + // F[slew_rate_46]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_46_slew_rate_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_slew_rate_46_wd), + .d (hw2reg.dio_pad_attr[46].slew_rate.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[8]), + .q (reg2hw.dio_pad_attr[46].slew_rate.q), + .ds (), + .qs (dio_pad_attr_46_slew_rate_46_qs) + ); + assign reg2hw.dio_pad_attr[46].slew_rate.qe = dio_pad_attr_46_qe; + + // F[drive_strength_46]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_46_drive_strength_46 ( + .re (dio_pad_attr_46_re), + .we (dio_pad_attr_46_gated_we), + .wd (dio_pad_attr_46_drive_strength_46_wd), + .d (hw2reg.dio_pad_attr[46].drive_strength.d), + .qre (), + .qe (dio_pad_attr_46_flds_we[9]), + .q (reg2hw.dio_pad_attr[46].drive_strength.q), + .ds (), + .qs (dio_pad_attr_46_drive_strength_46_qs) + ); + assign reg2hw.dio_pad_attr[46].drive_strength.qe = dio_pad_attr_46_qe; + + + // Subregister 47 of Multireg dio_pad_attr + // R[dio_pad_attr_47]: V(True) + logic dio_pad_attr_47_qe; + logic [9:0] dio_pad_attr_47_flds_we; + assign dio_pad_attr_47_qe = &dio_pad_attr_47_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_47_gated_we; + assign dio_pad_attr_47_gated_we = dio_pad_attr_47_we & dio_pad_attr_regwen_47_qs; + // F[invert_47]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_invert_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_invert_47_wd), + .d (hw2reg.dio_pad_attr[47].invert.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[0]), + .q (reg2hw.dio_pad_attr[47].invert.q), + .ds (), + .qs (dio_pad_attr_47_invert_47_qs) + ); + assign reg2hw.dio_pad_attr[47].invert.qe = dio_pad_attr_47_qe; + + // F[virtual_od_en_47]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_virtual_od_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_virtual_od_en_47_wd), + .d (hw2reg.dio_pad_attr[47].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[1]), + .q (reg2hw.dio_pad_attr[47].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_47_virtual_od_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].virtual_od_en.qe = dio_pad_attr_47_qe; + + // F[pull_en_47]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_pull_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_pull_en_47_wd), + .d (hw2reg.dio_pad_attr[47].pull_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[2]), + .q (reg2hw.dio_pad_attr[47].pull_en.q), + .ds (), + .qs (dio_pad_attr_47_pull_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].pull_en.qe = dio_pad_attr_47_qe; + + // F[pull_select_47]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_pull_select_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_pull_select_47_wd), + .d (hw2reg.dio_pad_attr[47].pull_select.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[3]), + .q (reg2hw.dio_pad_attr[47].pull_select.q), + .ds (), + .qs (dio_pad_attr_47_pull_select_47_qs) + ); + assign reg2hw.dio_pad_attr[47].pull_select.qe = dio_pad_attr_47_qe; + + // F[keeper_en_47]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_keeper_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_keeper_en_47_wd), + .d (hw2reg.dio_pad_attr[47].keeper_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[4]), + .q (reg2hw.dio_pad_attr[47].keeper_en.q), + .ds (), + .qs (dio_pad_attr_47_keeper_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].keeper_en.qe = dio_pad_attr_47_qe; + + // F[schmitt_en_47]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_schmitt_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_schmitt_en_47_wd), + .d (hw2reg.dio_pad_attr[47].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[5]), + .q (reg2hw.dio_pad_attr[47].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_47_schmitt_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].schmitt_en.qe = dio_pad_attr_47_qe; + + // F[od_en_47]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_od_en_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_od_en_47_wd), + .d (hw2reg.dio_pad_attr[47].od_en.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[6]), + .q (reg2hw.dio_pad_attr[47].od_en.q), + .ds (), + .qs (dio_pad_attr_47_od_en_47_qs) + ); + assign reg2hw.dio_pad_attr[47].od_en.qe = dio_pad_attr_47_qe; + + // F[input_disable_47]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_47_input_disable_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_input_disable_47_wd), + .d (hw2reg.dio_pad_attr[47].input_disable.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[7]), + .q (reg2hw.dio_pad_attr[47].input_disable.q), + .ds (), + .qs (dio_pad_attr_47_input_disable_47_qs) + ); + assign reg2hw.dio_pad_attr[47].input_disable.qe = dio_pad_attr_47_qe; + + // F[slew_rate_47]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_47_slew_rate_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_slew_rate_47_wd), + .d (hw2reg.dio_pad_attr[47].slew_rate.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[8]), + .q (reg2hw.dio_pad_attr[47].slew_rate.q), + .ds (), + .qs (dio_pad_attr_47_slew_rate_47_qs) + ); + assign reg2hw.dio_pad_attr[47].slew_rate.qe = dio_pad_attr_47_qe; + + // F[drive_strength_47]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_47_drive_strength_47 ( + .re (dio_pad_attr_47_re), + .we (dio_pad_attr_47_gated_we), + .wd (dio_pad_attr_47_drive_strength_47_wd), + .d (hw2reg.dio_pad_attr[47].drive_strength.d), + .qre (), + .qe (dio_pad_attr_47_flds_we[9]), + .q (reg2hw.dio_pad_attr[47].drive_strength.q), + .ds (), + .qs (dio_pad_attr_47_drive_strength_47_qs) + ); + assign reg2hw.dio_pad_attr[47].drive_strength.qe = dio_pad_attr_47_qe; + + + // Subregister 48 of Multireg dio_pad_attr + // R[dio_pad_attr_48]: V(True) + logic dio_pad_attr_48_qe; + logic [9:0] dio_pad_attr_48_flds_we; + assign dio_pad_attr_48_qe = &dio_pad_attr_48_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_48_gated_we; + assign dio_pad_attr_48_gated_we = dio_pad_attr_48_we & dio_pad_attr_regwen_48_qs; + // F[invert_48]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_invert_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_invert_48_wd), + .d (hw2reg.dio_pad_attr[48].invert.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[0]), + .q (reg2hw.dio_pad_attr[48].invert.q), + .ds (), + .qs (dio_pad_attr_48_invert_48_qs) + ); + assign reg2hw.dio_pad_attr[48].invert.qe = dio_pad_attr_48_qe; + + // F[virtual_od_en_48]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_virtual_od_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_virtual_od_en_48_wd), + .d (hw2reg.dio_pad_attr[48].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[1]), + .q (reg2hw.dio_pad_attr[48].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_48_virtual_od_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].virtual_od_en.qe = dio_pad_attr_48_qe; + + // F[pull_en_48]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_pull_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_pull_en_48_wd), + .d (hw2reg.dio_pad_attr[48].pull_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[2]), + .q (reg2hw.dio_pad_attr[48].pull_en.q), + .ds (), + .qs (dio_pad_attr_48_pull_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].pull_en.qe = dio_pad_attr_48_qe; + + // F[pull_select_48]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_pull_select_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_pull_select_48_wd), + .d (hw2reg.dio_pad_attr[48].pull_select.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[3]), + .q (reg2hw.dio_pad_attr[48].pull_select.q), + .ds (), + .qs (dio_pad_attr_48_pull_select_48_qs) + ); + assign reg2hw.dio_pad_attr[48].pull_select.qe = dio_pad_attr_48_qe; + + // F[keeper_en_48]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_keeper_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_keeper_en_48_wd), + .d (hw2reg.dio_pad_attr[48].keeper_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[4]), + .q (reg2hw.dio_pad_attr[48].keeper_en.q), + .ds (), + .qs (dio_pad_attr_48_keeper_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].keeper_en.qe = dio_pad_attr_48_qe; + + // F[schmitt_en_48]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_schmitt_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_schmitt_en_48_wd), + .d (hw2reg.dio_pad_attr[48].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[5]), + .q (reg2hw.dio_pad_attr[48].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_48_schmitt_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].schmitt_en.qe = dio_pad_attr_48_qe; + + // F[od_en_48]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_od_en_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_od_en_48_wd), + .d (hw2reg.dio_pad_attr[48].od_en.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[6]), + .q (reg2hw.dio_pad_attr[48].od_en.q), + .ds (), + .qs (dio_pad_attr_48_od_en_48_qs) + ); + assign reg2hw.dio_pad_attr[48].od_en.qe = dio_pad_attr_48_qe; + + // F[input_disable_48]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_48_input_disable_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_input_disable_48_wd), + .d (hw2reg.dio_pad_attr[48].input_disable.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[7]), + .q (reg2hw.dio_pad_attr[48].input_disable.q), + .ds (), + .qs (dio_pad_attr_48_input_disable_48_qs) + ); + assign reg2hw.dio_pad_attr[48].input_disable.qe = dio_pad_attr_48_qe; + + // F[slew_rate_48]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_48_slew_rate_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_slew_rate_48_wd), + .d (hw2reg.dio_pad_attr[48].slew_rate.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[8]), + .q (reg2hw.dio_pad_attr[48].slew_rate.q), + .ds (), + .qs (dio_pad_attr_48_slew_rate_48_qs) + ); + assign reg2hw.dio_pad_attr[48].slew_rate.qe = dio_pad_attr_48_qe; + + // F[drive_strength_48]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_48_drive_strength_48 ( + .re (dio_pad_attr_48_re), + .we (dio_pad_attr_48_gated_we), + .wd (dio_pad_attr_48_drive_strength_48_wd), + .d (hw2reg.dio_pad_attr[48].drive_strength.d), + .qre (), + .qe (dio_pad_attr_48_flds_we[9]), + .q (reg2hw.dio_pad_attr[48].drive_strength.q), + .ds (), + .qs (dio_pad_attr_48_drive_strength_48_qs) + ); + assign reg2hw.dio_pad_attr[48].drive_strength.qe = dio_pad_attr_48_qe; + + + // Subregister 49 of Multireg dio_pad_attr + // R[dio_pad_attr_49]: V(True) + logic dio_pad_attr_49_qe; + logic [9:0] dio_pad_attr_49_flds_we; + assign dio_pad_attr_49_qe = &dio_pad_attr_49_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_49_gated_we; + assign dio_pad_attr_49_gated_we = dio_pad_attr_49_we & dio_pad_attr_regwen_49_qs; + // F[invert_49]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_invert_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_invert_49_wd), + .d (hw2reg.dio_pad_attr[49].invert.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[0]), + .q (reg2hw.dio_pad_attr[49].invert.q), + .ds (), + .qs (dio_pad_attr_49_invert_49_qs) + ); + assign reg2hw.dio_pad_attr[49].invert.qe = dio_pad_attr_49_qe; + + // F[virtual_od_en_49]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_virtual_od_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_virtual_od_en_49_wd), + .d (hw2reg.dio_pad_attr[49].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[1]), + .q (reg2hw.dio_pad_attr[49].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_49_virtual_od_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].virtual_od_en.qe = dio_pad_attr_49_qe; + + // F[pull_en_49]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_pull_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_pull_en_49_wd), + .d (hw2reg.dio_pad_attr[49].pull_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[2]), + .q (reg2hw.dio_pad_attr[49].pull_en.q), + .ds (), + .qs (dio_pad_attr_49_pull_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].pull_en.qe = dio_pad_attr_49_qe; + + // F[pull_select_49]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_pull_select_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_pull_select_49_wd), + .d (hw2reg.dio_pad_attr[49].pull_select.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[3]), + .q (reg2hw.dio_pad_attr[49].pull_select.q), + .ds (), + .qs (dio_pad_attr_49_pull_select_49_qs) + ); + assign reg2hw.dio_pad_attr[49].pull_select.qe = dio_pad_attr_49_qe; + + // F[keeper_en_49]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_keeper_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_keeper_en_49_wd), + .d (hw2reg.dio_pad_attr[49].keeper_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[4]), + .q (reg2hw.dio_pad_attr[49].keeper_en.q), + .ds (), + .qs (dio_pad_attr_49_keeper_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].keeper_en.qe = dio_pad_attr_49_qe; + + // F[schmitt_en_49]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_schmitt_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_schmitt_en_49_wd), + .d (hw2reg.dio_pad_attr[49].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[5]), + .q (reg2hw.dio_pad_attr[49].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_49_schmitt_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].schmitt_en.qe = dio_pad_attr_49_qe; + + // F[od_en_49]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_od_en_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_od_en_49_wd), + .d (hw2reg.dio_pad_attr[49].od_en.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[6]), + .q (reg2hw.dio_pad_attr[49].od_en.q), + .ds (), + .qs (dio_pad_attr_49_od_en_49_qs) + ); + assign reg2hw.dio_pad_attr[49].od_en.qe = dio_pad_attr_49_qe; + + // F[input_disable_49]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_49_input_disable_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_input_disable_49_wd), + .d (hw2reg.dio_pad_attr[49].input_disable.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[7]), + .q (reg2hw.dio_pad_attr[49].input_disable.q), + .ds (), + .qs (dio_pad_attr_49_input_disable_49_qs) + ); + assign reg2hw.dio_pad_attr[49].input_disable.qe = dio_pad_attr_49_qe; + + // F[slew_rate_49]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_49_slew_rate_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_slew_rate_49_wd), + .d (hw2reg.dio_pad_attr[49].slew_rate.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[8]), + .q (reg2hw.dio_pad_attr[49].slew_rate.q), + .ds (), + .qs (dio_pad_attr_49_slew_rate_49_qs) + ); + assign reg2hw.dio_pad_attr[49].slew_rate.qe = dio_pad_attr_49_qe; + + // F[drive_strength_49]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_49_drive_strength_49 ( + .re (dio_pad_attr_49_re), + .we (dio_pad_attr_49_gated_we), + .wd (dio_pad_attr_49_drive_strength_49_wd), + .d (hw2reg.dio_pad_attr[49].drive_strength.d), + .qre (), + .qe (dio_pad_attr_49_flds_we[9]), + .q (reg2hw.dio_pad_attr[49].drive_strength.q), + .ds (), + .qs (dio_pad_attr_49_drive_strength_49_qs) + ); + assign reg2hw.dio_pad_attr[49].drive_strength.qe = dio_pad_attr_49_qe; + + + // Subregister 50 of Multireg dio_pad_attr + // R[dio_pad_attr_50]: V(True) + logic dio_pad_attr_50_qe; + logic [9:0] dio_pad_attr_50_flds_we; + assign dio_pad_attr_50_qe = &dio_pad_attr_50_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_50_gated_we; + assign dio_pad_attr_50_gated_we = dio_pad_attr_50_we & dio_pad_attr_regwen_50_qs; + // F[invert_50]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_invert_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_invert_50_wd), + .d (hw2reg.dio_pad_attr[50].invert.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[0]), + .q (reg2hw.dio_pad_attr[50].invert.q), + .ds (), + .qs (dio_pad_attr_50_invert_50_qs) + ); + assign reg2hw.dio_pad_attr[50].invert.qe = dio_pad_attr_50_qe; + + // F[virtual_od_en_50]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_virtual_od_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_virtual_od_en_50_wd), + .d (hw2reg.dio_pad_attr[50].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[1]), + .q (reg2hw.dio_pad_attr[50].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_50_virtual_od_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].virtual_od_en.qe = dio_pad_attr_50_qe; + + // F[pull_en_50]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_pull_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_pull_en_50_wd), + .d (hw2reg.dio_pad_attr[50].pull_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[2]), + .q (reg2hw.dio_pad_attr[50].pull_en.q), + .ds (), + .qs (dio_pad_attr_50_pull_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].pull_en.qe = dio_pad_attr_50_qe; + + // F[pull_select_50]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_pull_select_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_pull_select_50_wd), + .d (hw2reg.dio_pad_attr[50].pull_select.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[3]), + .q (reg2hw.dio_pad_attr[50].pull_select.q), + .ds (), + .qs (dio_pad_attr_50_pull_select_50_qs) + ); + assign reg2hw.dio_pad_attr[50].pull_select.qe = dio_pad_attr_50_qe; + + // F[keeper_en_50]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_keeper_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_keeper_en_50_wd), + .d (hw2reg.dio_pad_attr[50].keeper_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[4]), + .q (reg2hw.dio_pad_attr[50].keeper_en.q), + .ds (), + .qs (dio_pad_attr_50_keeper_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].keeper_en.qe = dio_pad_attr_50_qe; + + // F[schmitt_en_50]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_schmitt_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_schmitt_en_50_wd), + .d (hw2reg.dio_pad_attr[50].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[5]), + .q (reg2hw.dio_pad_attr[50].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_50_schmitt_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].schmitt_en.qe = dio_pad_attr_50_qe; + + // F[od_en_50]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_od_en_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_od_en_50_wd), + .d (hw2reg.dio_pad_attr[50].od_en.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[6]), + .q (reg2hw.dio_pad_attr[50].od_en.q), + .ds (), + .qs (dio_pad_attr_50_od_en_50_qs) + ); + assign reg2hw.dio_pad_attr[50].od_en.qe = dio_pad_attr_50_qe; + + // F[input_disable_50]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_50_input_disable_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_input_disable_50_wd), + .d (hw2reg.dio_pad_attr[50].input_disable.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[7]), + .q (reg2hw.dio_pad_attr[50].input_disable.q), + .ds (), + .qs (dio_pad_attr_50_input_disable_50_qs) + ); + assign reg2hw.dio_pad_attr[50].input_disable.qe = dio_pad_attr_50_qe; + + // F[slew_rate_50]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_50_slew_rate_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_slew_rate_50_wd), + .d (hw2reg.dio_pad_attr[50].slew_rate.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[8]), + .q (reg2hw.dio_pad_attr[50].slew_rate.q), + .ds (), + .qs (dio_pad_attr_50_slew_rate_50_qs) + ); + assign reg2hw.dio_pad_attr[50].slew_rate.qe = dio_pad_attr_50_qe; + + // F[drive_strength_50]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_50_drive_strength_50 ( + .re (dio_pad_attr_50_re), + .we (dio_pad_attr_50_gated_we), + .wd (dio_pad_attr_50_drive_strength_50_wd), + .d (hw2reg.dio_pad_attr[50].drive_strength.d), + .qre (), + .qe (dio_pad_attr_50_flds_we[9]), + .q (reg2hw.dio_pad_attr[50].drive_strength.q), + .ds (), + .qs (dio_pad_attr_50_drive_strength_50_qs) + ); + assign reg2hw.dio_pad_attr[50].drive_strength.qe = dio_pad_attr_50_qe; + + + // Subregister 51 of Multireg dio_pad_attr + // R[dio_pad_attr_51]: V(True) + logic dio_pad_attr_51_qe; + logic [9:0] dio_pad_attr_51_flds_we; + assign dio_pad_attr_51_qe = &dio_pad_attr_51_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_51_gated_we; + assign dio_pad_attr_51_gated_we = dio_pad_attr_51_we & dio_pad_attr_regwen_51_qs; + // F[invert_51]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_invert_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_invert_51_wd), + .d (hw2reg.dio_pad_attr[51].invert.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[0]), + .q (reg2hw.dio_pad_attr[51].invert.q), + .ds (), + .qs (dio_pad_attr_51_invert_51_qs) + ); + assign reg2hw.dio_pad_attr[51].invert.qe = dio_pad_attr_51_qe; + + // F[virtual_od_en_51]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_virtual_od_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_virtual_od_en_51_wd), + .d (hw2reg.dio_pad_attr[51].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[1]), + .q (reg2hw.dio_pad_attr[51].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_51_virtual_od_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].virtual_od_en.qe = dio_pad_attr_51_qe; + + // F[pull_en_51]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_pull_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_pull_en_51_wd), + .d (hw2reg.dio_pad_attr[51].pull_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[2]), + .q (reg2hw.dio_pad_attr[51].pull_en.q), + .ds (), + .qs (dio_pad_attr_51_pull_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].pull_en.qe = dio_pad_attr_51_qe; + + // F[pull_select_51]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_pull_select_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_pull_select_51_wd), + .d (hw2reg.dio_pad_attr[51].pull_select.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[3]), + .q (reg2hw.dio_pad_attr[51].pull_select.q), + .ds (), + .qs (dio_pad_attr_51_pull_select_51_qs) + ); + assign reg2hw.dio_pad_attr[51].pull_select.qe = dio_pad_attr_51_qe; + + // F[keeper_en_51]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_keeper_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_keeper_en_51_wd), + .d (hw2reg.dio_pad_attr[51].keeper_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[4]), + .q (reg2hw.dio_pad_attr[51].keeper_en.q), + .ds (), + .qs (dio_pad_attr_51_keeper_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].keeper_en.qe = dio_pad_attr_51_qe; + + // F[schmitt_en_51]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_schmitt_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_schmitt_en_51_wd), + .d (hw2reg.dio_pad_attr[51].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[5]), + .q (reg2hw.dio_pad_attr[51].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_51_schmitt_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].schmitt_en.qe = dio_pad_attr_51_qe; + + // F[od_en_51]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_od_en_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_od_en_51_wd), + .d (hw2reg.dio_pad_attr[51].od_en.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[6]), + .q (reg2hw.dio_pad_attr[51].od_en.q), + .ds (), + .qs (dio_pad_attr_51_od_en_51_qs) + ); + assign reg2hw.dio_pad_attr[51].od_en.qe = dio_pad_attr_51_qe; + + // F[input_disable_51]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_51_input_disable_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_input_disable_51_wd), + .d (hw2reg.dio_pad_attr[51].input_disable.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[7]), + .q (reg2hw.dio_pad_attr[51].input_disable.q), + .ds (), + .qs (dio_pad_attr_51_input_disable_51_qs) + ); + assign reg2hw.dio_pad_attr[51].input_disable.qe = dio_pad_attr_51_qe; + + // F[slew_rate_51]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_51_slew_rate_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_slew_rate_51_wd), + .d (hw2reg.dio_pad_attr[51].slew_rate.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[8]), + .q (reg2hw.dio_pad_attr[51].slew_rate.q), + .ds (), + .qs (dio_pad_attr_51_slew_rate_51_qs) + ); + assign reg2hw.dio_pad_attr[51].slew_rate.qe = dio_pad_attr_51_qe; + + // F[drive_strength_51]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_51_drive_strength_51 ( + .re (dio_pad_attr_51_re), + .we (dio_pad_attr_51_gated_we), + .wd (dio_pad_attr_51_drive_strength_51_wd), + .d (hw2reg.dio_pad_attr[51].drive_strength.d), + .qre (), + .qe (dio_pad_attr_51_flds_we[9]), + .q (reg2hw.dio_pad_attr[51].drive_strength.q), + .ds (), + .qs (dio_pad_attr_51_drive_strength_51_qs) + ); + assign reg2hw.dio_pad_attr[51].drive_strength.qe = dio_pad_attr_51_qe; + + + // Subregister 52 of Multireg dio_pad_attr + // R[dio_pad_attr_52]: V(True) + logic dio_pad_attr_52_qe; + logic [9:0] dio_pad_attr_52_flds_we; + assign dio_pad_attr_52_qe = &dio_pad_attr_52_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_52_gated_we; + assign dio_pad_attr_52_gated_we = dio_pad_attr_52_we & dio_pad_attr_regwen_52_qs; + // F[invert_52]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_invert_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_invert_52_wd), + .d (hw2reg.dio_pad_attr[52].invert.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[0]), + .q (reg2hw.dio_pad_attr[52].invert.q), + .ds (), + .qs (dio_pad_attr_52_invert_52_qs) + ); + assign reg2hw.dio_pad_attr[52].invert.qe = dio_pad_attr_52_qe; + + // F[virtual_od_en_52]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_virtual_od_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_virtual_od_en_52_wd), + .d (hw2reg.dio_pad_attr[52].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[1]), + .q (reg2hw.dio_pad_attr[52].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_52_virtual_od_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].virtual_od_en.qe = dio_pad_attr_52_qe; + + // F[pull_en_52]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_pull_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_pull_en_52_wd), + .d (hw2reg.dio_pad_attr[52].pull_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[2]), + .q (reg2hw.dio_pad_attr[52].pull_en.q), + .ds (), + .qs (dio_pad_attr_52_pull_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].pull_en.qe = dio_pad_attr_52_qe; + + // F[pull_select_52]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_pull_select_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_pull_select_52_wd), + .d (hw2reg.dio_pad_attr[52].pull_select.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[3]), + .q (reg2hw.dio_pad_attr[52].pull_select.q), + .ds (), + .qs (dio_pad_attr_52_pull_select_52_qs) + ); + assign reg2hw.dio_pad_attr[52].pull_select.qe = dio_pad_attr_52_qe; + + // F[keeper_en_52]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_keeper_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_keeper_en_52_wd), + .d (hw2reg.dio_pad_attr[52].keeper_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[4]), + .q (reg2hw.dio_pad_attr[52].keeper_en.q), + .ds (), + .qs (dio_pad_attr_52_keeper_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].keeper_en.qe = dio_pad_attr_52_qe; + + // F[schmitt_en_52]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_schmitt_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_schmitt_en_52_wd), + .d (hw2reg.dio_pad_attr[52].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[5]), + .q (reg2hw.dio_pad_attr[52].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_52_schmitt_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].schmitt_en.qe = dio_pad_attr_52_qe; + + // F[od_en_52]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_od_en_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_od_en_52_wd), + .d (hw2reg.dio_pad_attr[52].od_en.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[6]), + .q (reg2hw.dio_pad_attr[52].od_en.q), + .ds (), + .qs (dio_pad_attr_52_od_en_52_qs) + ); + assign reg2hw.dio_pad_attr[52].od_en.qe = dio_pad_attr_52_qe; + + // F[input_disable_52]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_52_input_disable_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_input_disable_52_wd), + .d (hw2reg.dio_pad_attr[52].input_disable.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[7]), + .q (reg2hw.dio_pad_attr[52].input_disable.q), + .ds (), + .qs (dio_pad_attr_52_input_disable_52_qs) + ); + assign reg2hw.dio_pad_attr[52].input_disable.qe = dio_pad_attr_52_qe; + + // F[slew_rate_52]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_52_slew_rate_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_slew_rate_52_wd), + .d (hw2reg.dio_pad_attr[52].slew_rate.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[8]), + .q (reg2hw.dio_pad_attr[52].slew_rate.q), + .ds (), + .qs (dio_pad_attr_52_slew_rate_52_qs) + ); + assign reg2hw.dio_pad_attr[52].slew_rate.qe = dio_pad_attr_52_qe; + + // F[drive_strength_52]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_52_drive_strength_52 ( + .re (dio_pad_attr_52_re), + .we (dio_pad_attr_52_gated_we), + .wd (dio_pad_attr_52_drive_strength_52_wd), + .d (hw2reg.dio_pad_attr[52].drive_strength.d), + .qre (), + .qe (dio_pad_attr_52_flds_we[9]), + .q (reg2hw.dio_pad_attr[52].drive_strength.q), + .ds (), + .qs (dio_pad_attr_52_drive_strength_52_qs) + ); + assign reg2hw.dio_pad_attr[52].drive_strength.qe = dio_pad_attr_52_qe; + + + // Subregister 53 of Multireg dio_pad_attr + // R[dio_pad_attr_53]: V(True) + logic dio_pad_attr_53_qe; + logic [9:0] dio_pad_attr_53_flds_we; + assign dio_pad_attr_53_qe = &dio_pad_attr_53_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_53_gated_we; + assign dio_pad_attr_53_gated_we = dio_pad_attr_53_we & dio_pad_attr_regwen_53_qs; + // F[invert_53]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_invert_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_invert_53_wd), + .d (hw2reg.dio_pad_attr[53].invert.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[0]), + .q (reg2hw.dio_pad_attr[53].invert.q), + .ds (), + .qs (dio_pad_attr_53_invert_53_qs) + ); + assign reg2hw.dio_pad_attr[53].invert.qe = dio_pad_attr_53_qe; + + // F[virtual_od_en_53]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_virtual_od_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_virtual_od_en_53_wd), + .d (hw2reg.dio_pad_attr[53].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[1]), + .q (reg2hw.dio_pad_attr[53].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_53_virtual_od_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].virtual_od_en.qe = dio_pad_attr_53_qe; + + // F[pull_en_53]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_pull_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_pull_en_53_wd), + .d (hw2reg.dio_pad_attr[53].pull_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[2]), + .q (reg2hw.dio_pad_attr[53].pull_en.q), + .ds (), + .qs (dio_pad_attr_53_pull_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].pull_en.qe = dio_pad_attr_53_qe; + + // F[pull_select_53]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_pull_select_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_pull_select_53_wd), + .d (hw2reg.dio_pad_attr[53].pull_select.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[3]), + .q (reg2hw.dio_pad_attr[53].pull_select.q), + .ds (), + .qs (dio_pad_attr_53_pull_select_53_qs) + ); + assign reg2hw.dio_pad_attr[53].pull_select.qe = dio_pad_attr_53_qe; + + // F[keeper_en_53]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_keeper_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_keeper_en_53_wd), + .d (hw2reg.dio_pad_attr[53].keeper_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[4]), + .q (reg2hw.dio_pad_attr[53].keeper_en.q), + .ds (), + .qs (dio_pad_attr_53_keeper_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].keeper_en.qe = dio_pad_attr_53_qe; + + // F[schmitt_en_53]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_schmitt_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_schmitt_en_53_wd), + .d (hw2reg.dio_pad_attr[53].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[5]), + .q (reg2hw.dio_pad_attr[53].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_53_schmitt_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].schmitt_en.qe = dio_pad_attr_53_qe; + + // F[od_en_53]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_od_en_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_od_en_53_wd), + .d (hw2reg.dio_pad_attr[53].od_en.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[6]), + .q (reg2hw.dio_pad_attr[53].od_en.q), + .ds (), + .qs (dio_pad_attr_53_od_en_53_qs) + ); + assign reg2hw.dio_pad_attr[53].od_en.qe = dio_pad_attr_53_qe; + + // F[input_disable_53]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_53_input_disable_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_input_disable_53_wd), + .d (hw2reg.dio_pad_attr[53].input_disable.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[7]), + .q (reg2hw.dio_pad_attr[53].input_disable.q), + .ds (), + .qs (dio_pad_attr_53_input_disable_53_qs) + ); + assign reg2hw.dio_pad_attr[53].input_disable.qe = dio_pad_attr_53_qe; + + // F[slew_rate_53]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_53_slew_rate_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_slew_rate_53_wd), + .d (hw2reg.dio_pad_attr[53].slew_rate.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[8]), + .q (reg2hw.dio_pad_attr[53].slew_rate.q), + .ds (), + .qs (dio_pad_attr_53_slew_rate_53_qs) + ); + assign reg2hw.dio_pad_attr[53].slew_rate.qe = dio_pad_attr_53_qe; + + // F[drive_strength_53]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_53_drive_strength_53 ( + .re (dio_pad_attr_53_re), + .we (dio_pad_attr_53_gated_we), + .wd (dio_pad_attr_53_drive_strength_53_wd), + .d (hw2reg.dio_pad_attr[53].drive_strength.d), + .qre (), + .qe (dio_pad_attr_53_flds_we[9]), + .q (reg2hw.dio_pad_attr[53].drive_strength.q), + .ds (), + .qs (dio_pad_attr_53_drive_strength_53_qs) + ); + assign reg2hw.dio_pad_attr[53].drive_strength.qe = dio_pad_attr_53_qe; + + + // Subregister 54 of Multireg dio_pad_attr + // R[dio_pad_attr_54]: V(True) + logic dio_pad_attr_54_qe; + logic [9:0] dio_pad_attr_54_flds_we; + assign dio_pad_attr_54_qe = &dio_pad_attr_54_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_54_gated_we; + assign dio_pad_attr_54_gated_we = dio_pad_attr_54_we & dio_pad_attr_regwen_54_qs; + // F[invert_54]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_invert_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_invert_54_wd), + .d (hw2reg.dio_pad_attr[54].invert.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[0]), + .q (reg2hw.dio_pad_attr[54].invert.q), + .ds (), + .qs (dio_pad_attr_54_invert_54_qs) + ); + assign reg2hw.dio_pad_attr[54].invert.qe = dio_pad_attr_54_qe; + + // F[virtual_od_en_54]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_virtual_od_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_virtual_od_en_54_wd), + .d (hw2reg.dio_pad_attr[54].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[1]), + .q (reg2hw.dio_pad_attr[54].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_54_virtual_od_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].virtual_od_en.qe = dio_pad_attr_54_qe; + + // F[pull_en_54]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_pull_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_pull_en_54_wd), + .d (hw2reg.dio_pad_attr[54].pull_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[2]), + .q (reg2hw.dio_pad_attr[54].pull_en.q), + .ds (), + .qs (dio_pad_attr_54_pull_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].pull_en.qe = dio_pad_attr_54_qe; + + // F[pull_select_54]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_pull_select_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_pull_select_54_wd), + .d (hw2reg.dio_pad_attr[54].pull_select.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[3]), + .q (reg2hw.dio_pad_attr[54].pull_select.q), + .ds (), + .qs (dio_pad_attr_54_pull_select_54_qs) + ); + assign reg2hw.dio_pad_attr[54].pull_select.qe = dio_pad_attr_54_qe; + + // F[keeper_en_54]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_keeper_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_keeper_en_54_wd), + .d (hw2reg.dio_pad_attr[54].keeper_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[4]), + .q (reg2hw.dio_pad_attr[54].keeper_en.q), + .ds (), + .qs (dio_pad_attr_54_keeper_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].keeper_en.qe = dio_pad_attr_54_qe; + + // F[schmitt_en_54]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_schmitt_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_schmitt_en_54_wd), + .d (hw2reg.dio_pad_attr[54].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[5]), + .q (reg2hw.dio_pad_attr[54].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_54_schmitt_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].schmitt_en.qe = dio_pad_attr_54_qe; + + // F[od_en_54]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_od_en_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_od_en_54_wd), + .d (hw2reg.dio_pad_attr[54].od_en.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[6]), + .q (reg2hw.dio_pad_attr[54].od_en.q), + .ds (), + .qs (dio_pad_attr_54_od_en_54_qs) + ); + assign reg2hw.dio_pad_attr[54].od_en.qe = dio_pad_attr_54_qe; + + // F[input_disable_54]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_54_input_disable_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_input_disable_54_wd), + .d (hw2reg.dio_pad_attr[54].input_disable.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[7]), + .q (reg2hw.dio_pad_attr[54].input_disable.q), + .ds (), + .qs (dio_pad_attr_54_input_disable_54_qs) + ); + assign reg2hw.dio_pad_attr[54].input_disable.qe = dio_pad_attr_54_qe; + + // F[slew_rate_54]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_54_slew_rate_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_slew_rate_54_wd), + .d (hw2reg.dio_pad_attr[54].slew_rate.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[8]), + .q (reg2hw.dio_pad_attr[54].slew_rate.q), + .ds (), + .qs (dio_pad_attr_54_slew_rate_54_qs) + ); + assign reg2hw.dio_pad_attr[54].slew_rate.qe = dio_pad_attr_54_qe; + + // F[drive_strength_54]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_54_drive_strength_54 ( + .re (dio_pad_attr_54_re), + .we (dio_pad_attr_54_gated_we), + .wd (dio_pad_attr_54_drive_strength_54_wd), + .d (hw2reg.dio_pad_attr[54].drive_strength.d), + .qre (), + .qe (dio_pad_attr_54_flds_we[9]), + .q (reg2hw.dio_pad_attr[54].drive_strength.q), + .ds (), + .qs (dio_pad_attr_54_drive_strength_54_qs) + ); + assign reg2hw.dio_pad_attr[54].drive_strength.qe = dio_pad_attr_54_qe; + + + // Subregister 55 of Multireg dio_pad_attr + // R[dio_pad_attr_55]: V(True) + logic dio_pad_attr_55_qe; + logic [9:0] dio_pad_attr_55_flds_we; + assign dio_pad_attr_55_qe = &dio_pad_attr_55_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_55_gated_we; + assign dio_pad_attr_55_gated_we = dio_pad_attr_55_we & dio_pad_attr_regwen_55_qs; + // F[invert_55]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_invert_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_invert_55_wd), + .d (hw2reg.dio_pad_attr[55].invert.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[0]), + .q (reg2hw.dio_pad_attr[55].invert.q), + .ds (), + .qs (dio_pad_attr_55_invert_55_qs) + ); + assign reg2hw.dio_pad_attr[55].invert.qe = dio_pad_attr_55_qe; + + // F[virtual_od_en_55]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_virtual_od_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_virtual_od_en_55_wd), + .d (hw2reg.dio_pad_attr[55].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[1]), + .q (reg2hw.dio_pad_attr[55].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_55_virtual_od_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].virtual_od_en.qe = dio_pad_attr_55_qe; + + // F[pull_en_55]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_pull_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_pull_en_55_wd), + .d (hw2reg.dio_pad_attr[55].pull_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[2]), + .q (reg2hw.dio_pad_attr[55].pull_en.q), + .ds (), + .qs (dio_pad_attr_55_pull_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].pull_en.qe = dio_pad_attr_55_qe; + + // F[pull_select_55]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_pull_select_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_pull_select_55_wd), + .d (hw2reg.dio_pad_attr[55].pull_select.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[3]), + .q (reg2hw.dio_pad_attr[55].pull_select.q), + .ds (), + .qs (dio_pad_attr_55_pull_select_55_qs) + ); + assign reg2hw.dio_pad_attr[55].pull_select.qe = dio_pad_attr_55_qe; + + // F[keeper_en_55]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_keeper_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_keeper_en_55_wd), + .d (hw2reg.dio_pad_attr[55].keeper_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[4]), + .q (reg2hw.dio_pad_attr[55].keeper_en.q), + .ds (), + .qs (dio_pad_attr_55_keeper_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].keeper_en.qe = dio_pad_attr_55_qe; + + // F[schmitt_en_55]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_schmitt_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_schmitt_en_55_wd), + .d (hw2reg.dio_pad_attr[55].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[5]), + .q (reg2hw.dio_pad_attr[55].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_55_schmitt_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].schmitt_en.qe = dio_pad_attr_55_qe; + + // F[od_en_55]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_od_en_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_od_en_55_wd), + .d (hw2reg.dio_pad_attr[55].od_en.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[6]), + .q (reg2hw.dio_pad_attr[55].od_en.q), + .ds (), + .qs (dio_pad_attr_55_od_en_55_qs) + ); + assign reg2hw.dio_pad_attr[55].od_en.qe = dio_pad_attr_55_qe; + + // F[input_disable_55]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_55_input_disable_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_input_disable_55_wd), + .d (hw2reg.dio_pad_attr[55].input_disable.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[7]), + .q (reg2hw.dio_pad_attr[55].input_disable.q), + .ds (), + .qs (dio_pad_attr_55_input_disable_55_qs) + ); + assign reg2hw.dio_pad_attr[55].input_disable.qe = dio_pad_attr_55_qe; + + // F[slew_rate_55]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_55_slew_rate_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_slew_rate_55_wd), + .d (hw2reg.dio_pad_attr[55].slew_rate.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[8]), + .q (reg2hw.dio_pad_attr[55].slew_rate.q), + .ds (), + .qs (dio_pad_attr_55_slew_rate_55_qs) + ); + assign reg2hw.dio_pad_attr[55].slew_rate.qe = dio_pad_attr_55_qe; + + // F[drive_strength_55]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_55_drive_strength_55 ( + .re (dio_pad_attr_55_re), + .we (dio_pad_attr_55_gated_we), + .wd (dio_pad_attr_55_drive_strength_55_wd), + .d (hw2reg.dio_pad_attr[55].drive_strength.d), + .qre (), + .qe (dio_pad_attr_55_flds_we[9]), + .q (reg2hw.dio_pad_attr[55].drive_strength.q), + .ds (), + .qs (dio_pad_attr_55_drive_strength_55_qs) + ); + assign reg2hw.dio_pad_attr[55].drive_strength.qe = dio_pad_attr_55_qe; + + + // Subregister 56 of Multireg dio_pad_attr + // R[dio_pad_attr_56]: V(True) + logic dio_pad_attr_56_qe; + logic [9:0] dio_pad_attr_56_flds_we; + assign dio_pad_attr_56_qe = &dio_pad_attr_56_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_56_gated_we; + assign dio_pad_attr_56_gated_we = dio_pad_attr_56_we & dio_pad_attr_regwen_56_qs; + // F[invert_56]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_invert_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_invert_56_wd), + .d (hw2reg.dio_pad_attr[56].invert.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[0]), + .q (reg2hw.dio_pad_attr[56].invert.q), + .ds (), + .qs (dio_pad_attr_56_invert_56_qs) + ); + assign reg2hw.dio_pad_attr[56].invert.qe = dio_pad_attr_56_qe; + + // F[virtual_od_en_56]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_virtual_od_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_virtual_od_en_56_wd), + .d (hw2reg.dio_pad_attr[56].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[1]), + .q (reg2hw.dio_pad_attr[56].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_56_virtual_od_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].virtual_od_en.qe = dio_pad_attr_56_qe; + + // F[pull_en_56]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_pull_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_pull_en_56_wd), + .d (hw2reg.dio_pad_attr[56].pull_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[2]), + .q (reg2hw.dio_pad_attr[56].pull_en.q), + .ds (), + .qs (dio_pad_attr_56_pull_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].pull_en.qe = dio_pad_attr_56_qe; + + // F[pull_select_56]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_pull_select_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_pull_select_56_wd), + .d (hw2reg.dio_pad_attr[56].pull_select.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[3]), + .q (reg2hw.dio_pad_attr[56].pull_select.q), + .ds (), + .qs (dio_pad_attr_56_pull_select_56_qs) + ); + assign reg2hw.dio_pad_attr[56].pull_select.qe = dio_pad_attr_56_qe; + + // F[keeper_en_56]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_keeper_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_keeper_en_56_wd), + .d (hw2reg.dio_pad_attr[56].keeper_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[4]), + .q (reg2hw.dio_pad_attr[56].keeper_en.q), + .ds (), + .qs (dio_pad_attr_56_keeper_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].keeper_en.qe = dio_pad_attr_56_qe; + + // F[schmitt_en_56]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_schmitt_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_schmitt_en_56_wd), + .d (hw2reg.dio_pad_attr[56].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[5]), + .q (reg2hw.dio_pad_attr[56].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_56_schmitt_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].schmitt_en.qe = dio_pad_attr_56_qe; + + // F[od_en_56]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_od_en_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_od_en_56_wd), + .d (hw2reg.dio_pad_attr[56].od_en.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[6]), + .q (reg2hw.dio_pad_attr[56].od_en.q), + .ds (), + .qs (dio_pad_attr_56_od_en_56_qs) + ); + assign reg2hw.dio_pad_attr[56].od_en.qe = dio_pad_attr_56_qe; + + // F[input_disable_56]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_56_input_disable_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_input_disable_56_wd), + .d (hw2reg.dio_pad_attr[56].input_disable.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[7]), + .q (reg2hw.dio_pad_attr[56].input_disable.q), + .ds (), + .qs (dio_pad_attr_56_input_disable_56_qs) + ); + assign reg2hw.dio_pad_attr[56].input_disable.qe = dio_pad_attr_56_qe; + + // F[slew_rate_56]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_56_slew_rate_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_slew_rate_56_wd), + .d (hw2reg.dio_pad_attr[56].slew_rate.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[8]), + .q (reg2hw.dio_pad_attr[56].slew_rate.q), + .ds (), + .qs (dio_pad_attr_56_slew_rate_56_qs) + ); + assign reg2hw.dio_pad_attr[56].slew_rate.qe = dio_pad_attr_56_qe; + + // F[drive_strength_56]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_56_drive_strength_56 ( + .re (dio_pad_attr_56_re), + .we (dio_pad_attr_56_gated_we), + .wd (dio_pad_attr_56_drive_strength_56_wd), + .d (hw2reg.dio_pad_attr[56].drive_strength.d), + .qre (), + .qe (dio_pad_attr_56_flds_we[9]), + .q (reg2hw.dio_pad_attr[56].drive_strength.q), + .ds (), + .qs (dio_pad_attr_56_drive_strength_56_qs) + ); + assign reg2hw.dio_pad_attr[56].drive_strength.qe = dio_pad_attr_56_qe; + + + // Subregister 57 of Multireg dio_pad_attr + // R[dio_pad_attr_57]: V(True) + logic dio_pad_attr_57_qe; + logic [9:0] dio_pad_attr_57_flds_we; + assign dio_pad_attr_57_qe = &dio_pad_attr_57_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_57_gated_we; + assign dio_pad_attr_57_gated_we = dio_pad_attr_57_we & dio_pad_attr_regwen_57_qs; + // F[invert_57]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_invert_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_invert_57_wd), + .d (hw2reg.dio_pad_attr[57].invert.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[0]), + .q (reg2hw.dio_pad_attr[57].invert.q), + .ds (), + .qs (dio_pad_attr_57_invert_57_qs) + ); + assign reg2hw.dio_pad_attr[57].invert.qe = dio_pad_attr_57_qe; + + // F[virtual_od_en_57]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_virtual_od_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_virtual_od_en_57_wd), + .d (hw2reg.dio_pad_attr[57].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[1]), + .q (reg2hw.dio_pad_attr[57].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_57_virtual_od_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].virtual_od_en.qe = dio_pad_attr_57_qe; + + // F[pull_en_57]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_pull_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_pull_en_57_wd), + .d (hw2reg.dio_pad_attr[57].pull_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[2]), + .q (reg2hw.dio_pad_attr[57].pull_en.q), + .ds (), + .qs (dio_pad_attr_57_pull_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].pull_en.qe = dio_pad_attr_57_qe; + + // F[pull_select_57]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_pull_select_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_pull_select_57_wd), + .d (hw2reg.dio_pad_attr[57].pull_select.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[3]), + .q (reg2hw.dio_pad_attr[57].pull_select.q), + .ds (), + .qs (dio_pad_attr_57_pull_select_57_qs) + ); + assign reg2hw.dio_pad_attr[57].pull_select.qe = dio_pad_attr_57_qe; + + // F[keeper_en_57]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_keeper_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_keeper_en_57_wd), + .d (hw2reg.dio_pad_attr[57].keeper_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[4]), + .q (reg2hw.dio_pad_attr[57].keeper_en.q), + .ds (), + .qs (dio_pad_attr_57_keeper_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].keeper_en.qe = dio_pad_attr_57_qe; + + // F[schmitt_en_57]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_schmitt_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_schmitt_en_57_wd), + .d (hw2reg.dio_pad_attr[57].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[5]), + .q (reg2hw.dio_pad_attr[57].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_57_schmitt_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].schmitt_en.qe = dio_pad_attr_57_qe; + + // F[od_en_57]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_od_en_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_od_en_57_wd), + .d (hw2reg.dio_pad_attr[57].od_en.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[6]), + .q (reg2hw.dio_pad_attr[57].od_en.q), + .ds (), + .qs (dio_pad_attr_57_od_en_57_qs) + ); + assign reg2hw.dio_pad_attr[57].od_en.qe = dio_pad_attr_57_qe; + + // F[input_disable_57]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_57_input_disable_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_input_disable_57_wd), + .d (hw2reg.dio_pad_attr[57].input_disable.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[7]), + .q (reg2hw.dio_pad_attr[57].input_disable.q), + .ds (), + .qs (dio_pad_attr_57_input_disable_57_qs) + ); + assign reg2hw.dio_pad_attr[57].input_disable.qe = dio_pad_attr_57_qe; + + // F[slew_rate_57]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_57_slew_rate_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_slew_rate_57_wd), + .d (hw2reg.dio_pad_attr[57].slew_rate.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[8]), + .q (reg2hw.dio_pad_attr[57].slew_rate.q), + .ds (), + .qs (dio_pad_attr_57_slew_rate_57_qs) + ); + assign reg2hw.dio_pad_attr[57].slew_rate.qe = dio_pad_attr_57_qe; + + // F[drive_strength_57]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_57_drive_strength_57 ( + .re (dio_pad_attr_57_re), + .we (dio_pad_attr_57_gated_we), + .wd (dio_pad_attr_57_drive_strength_57_wd), + .d (hw2reg.dio_pad_attr[57].drive_strength.d), + .qre (), + .qe (dio_pad_attr_57_flds_we[9]), + .q (reg2hw.dio_pad_attr[57].drive_strength.q), + .ds (), + .qs (dio_pad_attr_57_drive_strength_57_qs) + ); + assign reg2hw.dio_pad_attr[57].drive_strength.qe = dio_pad_attr_57_qe; + + + // Subregister 58 of Multireg dio_pad_attr + // R[dio_pad_attr_58]: V(True) + logic dio_pad_attr_58_qe; + logic [9:0] dio_pad_attr_58_flds_we; + assign dio_pad_attr_58_qe = &dio_pad_attr_58_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_58_gated_we; + assign dio_pad_attr_58_gated_we = dio_pad_attr_58_we & dio_pad_attr_regwen_58_qs; + // F[invert_58]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_invert_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_invert_58_wd), + .d (hw2reg.dio_pad_attr[58].invert.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[0]), + .q (reg2hw.dio_pad_attr[58].invert.q), + .ds (), + .qs (dio_pad_attr_58_invert_58_qs) + ); + assign reg2hw.dio_pad_attr[58].invert.qe = dio_pad_attr_58_qe; + + // F[virtual_od_en_58]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_virtual_od_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_virtual_od_en_58_wd), + .d (hw2reg.dio_pad_attr[58].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[1]), + .q (reg2hw.dio_pad_attr[58].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_58_virtual_od_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].virtual_od_en.qe = dio_pad_attr_58_qe; + + // F[pull_en_58]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_pull_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_pull_en_58_wd), + .d (hw2reg.dio_pad_attr[58].pull_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[2]), + .q (reg2hw.dio_pad_attr[58].pull_en.q), + .ds (), + .qs (dio_pad_attr_58_pull_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].pull_en.qe = dio_pad_attr_58_qe; + + // F[pull_select_58]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_pull_select_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_pull_select_58_wd), + .d (hw2reg.dio_pad_attr[58].pull_select.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[3]), + .q (reg2hw.dio_pad_attr[58].pull_select.q), + .ds (), + .qs (dio_pad_attr_58_pull_select_58_qs) + ); + assign reg2hw.dio_pad_attr[58].pull_select.qe = dio_pad_attr_58_qe; + + // F[keeper_en_58]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_keeper_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_keeper_en_58_wd), + .d (hw2reg.dio_pad_attr[58].keeper_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[4]), + .q (reg2hw.dio_pad_attr[58].keeper_en.q), + .ds (), + .qs (dio_pad_attr_58_keeper_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].keeper_en.qe = dio_pad_attr_58_qe; + + // F[schmitt_en_58]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_schmitt_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_schmitt_en_58_wd), + .d (hw2reg.dio_pad_attr[58].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[5]), + .q (reg2hw.dio_pad_attr[58].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_58_schmitt_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].schmitt_en.qe = dio_pad_attr_58_qe; + + // F[od_en_58]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_od_en_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_od_en_58_wd), + .d (hw2reg.dio_pad_attr[58].od_en.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[6]), + .q (reg2hw.dio_pad_attr[58].od_en.q), + .ds (), + .qs (dio_pad_attr_58_od_en_58_qs) + ); + assign reg2hw.dio_pad_attr[58].od_en.qe = dio_pad_attr_58_qe; + + // F[input_disable_58]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_58_input_disable_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_input_disable_58_wd), + .d (hw2reg.dio_pad_attr[58].input_disable.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[7]), + .q (reg2hw.dio_pad_attr[58].input_disable.q), + .ds (), + .qs (dio_pad_attr_58_input_disable_58_qs) + ); + assign reg2hw.dio_pad_attr[58].input_disable.qe = dio_pad_attr_58_qe; + + // F[slew_rate_58]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_58_slew_rate_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_slew_rate_58_wd), + .d (hw2reg.dio_pad_attr[58].slew_rate.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[8]), + .q (reg2hw.dio_pad_attr[58].slew_rate.q), + .ds (), + .qs (dio_pad_attr_58_slew_rate_58_qs) + ); + assign reg2hw.dio_pad_attr[58].slew_rate.qe = dio_pad_attr_58_qe; + + // F[drive_strength_58]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_58_drive_strength_58 ( + .re (dio_pad_attr_58_re), + .we (dio_pad_attr_58_gated_we), + .wd (dio_pad_attr_58_drive_strength_58_wd), + .d (hw2reg.dio_pad_attr[58].drive_strength.d), + .qre (), + .qe (dio_pad_attr_58_flds_we[9]), + .q (reg2hw.dio_pad_attr[58].drive_strength.q), + .ds (), + .qs (dio_pad_attr_58_drive_strength_58_qs) + ); + assign reg2hw.dio_pad_attr[58].drive_strength.qe = dio_pad_attr_58_qe; + + + // Subregister 59 of Multireg dio_pad_attr + // R[dio_pad_attr_59]: V(True) + logic dio_pad_attr_59_qe; + logic [9:0] dio_pad_attr_59_flds_we; + assign dio_pad_attr_59_qe = &dio_pad_attr_59_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_59_gated_we; + assign dio_pad_attr_59_gated_we = dio_pad_attr_59_we & dio_pad_attr_regwen_59_qs; + // F[invert_59]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_invert_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_invert_59_wd), + .d (hw2reg.dio_pad_attr[59].invert.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[0]), + .q (reg2hw.dio_pad_attr[59].invert.q), + .ds (), + .qs (dio_pad_attr_59_invert_59_qs) + ); + assign reg2hw.dio_pad_attr[59].invert.qe = dio_pad_attr_59_qe; + + // F[virtual_od_en_59]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_virtual_od_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_virtual_od_en_59_wd), + .d (hw2reg.dio_pad_attr[59].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[1]), + .q (reg2hw.dio_pad_attr[59].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_59_virtual_od_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].virtual_od_en.qe = dio_pad_attr_59_qe; + + // F[pull_en_59]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_pull_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_pull_en_59_wd), + .d (hw2reg.dio_pad_attr[59].pull_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[2]), + .q (reg2hw.dio_pad_attr[59].pull_en.q), + .ds (), + .qs (dio_pad_attr_59_pull_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].pull_en.qe = dio_pad_attr_59_qe; + + // F[pull_select_59]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_pull_select_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_pull_select_59_wd), + .d (hw2reg.dio_pad_attr[59].pull_select.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[3]), + .q (reg2hw.dio_pad_attr[59].pull_select.q), + .ds (), + .qs (dio_pad_attr_59_pull_select_59_qs) + ); + assign reg2hw.dio_pad_attr[59].pull_select.qe = dio_pad_attr_59_qe; + + // F[keeper_en_59]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_keeper_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_keeper_en_59_wd), + .d (hw2reg.dio_pad_attr[59].keeper_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[4]), + .q (reg2hw.dio_pad_attr[59].keeper_en.q), + .ds (), + .qs (dio_pad_attr_59_keeper_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].keeper_en.qe = dio_pad_attr_59_qe; + + // F[schmitt_en_59]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_schmitt_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_schmitt_en_59_wd), + .d (hw2reg.dio_pad_attr[59].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[5]), + .q (reg2hw.dio_pad_attr[59].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_59_schmitt_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].schmitt_en.qe = dio_pad_attr_59_qe; + + // F[od_en_59]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_od_en_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_od_en_59_wd), + .d (hw2reg.dio_pad_attr[59].od_en.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[6]), + .q (reg2hw.dio_pad_attr[59].od_en.q), + .ds (), + .qs (dio_pad_attr_59_od_en_59_qs) + ); + assign reg2hw.dio_pad_attr[59].od_en.qe = dio_pad_attr_59_qe; + + // F[input_disable_59]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_59_input_disable_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_input_disable_59_wd), + .d (hw2reg.dio_pad_attr[59].input_disable.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[7]), + .q (reg2hw.dio_pad_attr[59].input_disable.q), + .ds (), + .qs (dio_pad_attr_59_input_disable_59_qs) + ); + assign reg2hw.dio_pad_attr[59].input_disable.qe = dio_pad_attr_59_qe; + + // F[slew_rate_59]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_59_slew_rate_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_slew_rate_59_wd), + .d (hw2reg.dio_pad_attr[59].slew_rate.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[8]), + .q (reg2hw.dio_pad_attr[59].slew_rate.q), + .ds (), + .qs (dio_pad_attr_59_slew_rate_59_qs) + ); + assign reg2hw.dio_pad_attr[59].slew_rate.qe = dio_pad_attr_59_qe; + + // F[drive_strength_59]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_59_drive_strength_59 ( + .re (dio_pad_attr_59_re), + .we (dio_pad_attr_59_gated_we), + .wd (dio_pad_attr_59_drive_strength_59_wd), + .d (hw2reg.dio_pad_attr[59].drive_strength.d), + .qre (), + .qe (dio_pad_attr_59_flds_we[9]), + .q (reg2hw.dio_pad_attr[59].drive_strength.q), + .ds (), + .qs (dio_pad_attr_59_drive_strength_59_qs) + ); + assign reg2hw.dio_pad_attr[59].drive_strength.qe = dio_pad_attr_59_qe; + + + // Subregister 60 of Multireg dio_pad_attr + // R[dio_pad_attr_60]: V(True) + logic dio_pad_attr_60_qe; + logic [9:0] dio_pad_attr_60_flds_we; + assign dio_pad_attr_60_qe = &dio_pad_attr_60_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_60_gated_we; + assign dio_pad_attr_60_gated_we = dio_pad_attr_60_we & dio_pad_attr_regwen_60_qs; + // F[invert_60]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_invert_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_invert_60_wd), + .d (hw2reg.dio_pad_attr[60].invert.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[0]), + .q (reg2hw.dio_pad_attr[60].invert.q), + .ds (), + .qs (dio_pad_attr_60_invert_60_qs) + ); + assign reg2hw.dio_pad_attr[60].invert.qe = dio_pad_attr_60_qe; + + // F[virtual_od_en_60]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_virtual_od_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_virtual_od_en_60_wd), + .d (hw2reg.dio_pad_attr[60].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[1]), + .q (reg2hw.dio_pad_attr[60].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_60_virtual_od_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].virtual_od_en.qe = dio_pad_attr_60_qe; + + // F[pull_en_60]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_pull_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_pull_en_60_wd), + .d (hw2reg.dio_pad_attr[60].pull_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[2]), + .q (reg2hw.dio_pad_attr[60].pull_en.q), + .ds (), + .qs (dio_pad_attr_60_pull_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].pull_en.qe = dio_pad_attr_60_qe; + + // F[pull_select_60]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_pull_select_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_pull_select_60_wd), + .d (hw2reg.dio_pad_attr[60].pull_select.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[3]), + .q (reg2hw.dio_pad_attr[60].pull_select.q), + .ds (), + .qs (dio_pad_attr_60_pull_select_60_qs) + ); + assign reg2hw.dio_pad_attr[60].pull_select.qe = dio_pad_attr_60_qe; + + // F[keeper_en_60]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_keeper_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_keeper_en_60_wd), + .d (hw2reg.dio_pad_attr[60].keeper_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[4]), + .q (reg2hw.dio_pad_attr[60].keeper_en.q), + .ds (), + .qs (dio_pad_attr_60_keeper_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].keeper_en.qe = dio_pad_attr_60_qe; + + // F[schmitt_en_60]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_schmitt_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_schmitt_en_60_wd), + .d (hw2reg.dio_pad_attr[60].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[5]), + .q (reg2hw.dio_pad_attr[60].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_60_schmitt_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].schmitt_en.qe = dio_pad_attr_60_qe; + + // F[od_en_60]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_od_en_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_od_en_60_wd), + .d (hw2reg.dio_pad_attr[60].od_en.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[6]), + .q (reg2hw.dio_pad_attr[60].od_en.q), + .ds (), + .qs (dio_pad_attr_60_od_en_60_qs) + ); + assign reg2hw.dio_pad_attr[60].od_en.qe = dio_pad_attr_60_qe; + + // F[input_disable_60]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_60_input_disable_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_input_disable_60_wd), + .d (hw2reg.dio_pad_attr[60].input_disable.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[7]), + .q (reg2hw.dio_pad_attr[60].input_disable.q), + .ds (), + .qs (dio_pad_attr_60_input_disable_60_qs) + ); + assign reg2hw.dio_pad_attr[60].input_disable.qe = dio_pad_attr_60_qe; + + // F[slew_rate_60]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_60_slew_rate_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_slew_rate_60_wd), + .d (hw2reg.dio_pad_attr[60].slew_rate.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[8]), + .q (reg2hw.dio_pad_attr[60].slew_rate.q), + .ds (), + .qs (dio_pad_attr_60_slew_rate_60_qs) + ); + assign reg2hw.dio_pad_attr[60].slew_rate.qe = dio_pad_attr_60_qe; + + // F[drive_strength_60]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_60_drive_strength_60 ( + .re (dio_pad_attr_60_re), + .we (dio_pad_attr_60_gated_we), + .wd (dio_pad_attr_60_drive_strength_60_wd), + .d (hw2reg.dio_pad_attr[60].drive_strength.d), + .qre (), + .qe (dio_pad_attr_60_flds_we[9]), + .q (reg2hw.dio_pad_attr[60].drive_strength.q), + .ds (), + .qs (dio_pad_attr_60_drive_strength_60_qs) + ); + assign reg2hw.dio_pad_attr[60].drive_strength.qe = dio_pad_attr_60_qe; + + + // Subregister 61 of Multireg dio_pad_attr + // R[dio_pad_attr_61]: V(True) + logic dio_pad_attr_61_qe; + logic [9:0] dio_pad_attr_61_flds_we; + assign dio_pad_attr_61_qe = &dio_pad_attr_61_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_61_gated_we; + assign dio_pad_attr_61_gated_we = dio_pad_attr_61_we & dio_pad_attr_regwen_61_qs; + // F[invert_61]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_invert_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_invert_61_wd), + .d (hw2reg.dio_pad_attr[61].invert.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[0]), + .q (reg2hw.dio_pad_attr[61].invert.q), + .ds (), + .qs (dio_pad_attr_61_invert_61_qs) + ); + assign reg2hw.dio_pad_attr[61].invert.qe = dio_pad_attr_61_qe; + + // F[virtual_od_en_61]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_virtual_od_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_virtual_od_en_61_wd), + .d (hw2reg.dio_pad_attr[61].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[1]), + .q (reg2hw.dio_pad_attr[61].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_61_virtual_od_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].virtual_od_en.qe = dio_pad_attr_61_qe; + + // F[pull_en_61]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_pull_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_pull_en_61_wd), + .d (hw2reg.dio_pad_attr[61].pull_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[2]), + .q (reg2hw.dio_pad_attr[61].pull_en.q), + .ds (), + .qs (dio_pad_attr_61_pull_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].pull_en.qe = dio_pad_attr_61_qe; + + // F[pull_select_61]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_pull_select_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_pull_select_61_wd), + .d (hw2reg.dio_pad_attr[61].pull_select.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[3]), + .q (reg2hw.dio_pad_attr[61].pull_select.q), + .ds (), + .qs (dio_pad_attr_61_pull_select_61_qs) + ); + assign reg2hw.dio_pad_attr[61].pull_select.qe = dio_pad_attr_61_qe; + + // F[keeper_en_61]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_keeper_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_keeper_en_61_wd), + .d (hw2reg.dio_pad_attr[61].keeper_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[4]), + .q (reg2hw.dio_pad_attr[61].keeper_en.q), + .ds (), + .qs (dio_pad_attr_61_keeper_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].keeper_en.qe = dio_pad_attr_61_qe; + + // F[schmitt_en_61]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_schmitt_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_schmitt_en_61_wd), + .d (hw2reg.dio_pad_attr[61].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[5]), + .q (reg2hw.dio_pad_attr[61].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_61_schmitt_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].schmitt_en.qe = dio_pad_attr_61_qe; + + // F[od_en_61]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_od_en_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_od_en_61_wd), + .d (hw2reg.dio_pad_attr[61].od_en.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[6]), + .q (reg2hw.dio_pad_attr[61].od_en.q), + .ds (), + .qs (dio_pad_attr_61_od_en_61_qs) + ); + assign reg2hw.dio_pad_attr[61].od_en.qe = dio_pad_attr_61_qe; + + // F[input_disable_61]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_61_input_disable_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_input_disable_61_wd), + .d (hw2reg.dio_pad_attr[61].input_disable.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[7]), + .q (reg2hw.dio_pad_attr[61].input_disable.q), + .ds (), + .qs (dio_pad_attr_61_input_disable_61_qs) + ); + assign reg2hw.dio_pad_attr[61].input_disable.qe = dio_pad_attr_61_qe; + + // F[slew_rate_61]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_61_slew_rate_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_slew_rate_61_wd), + .d (hw2reg.dio_pad_attr[61].slew_rate.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[8]), + .q (reg2hw.dio_pad_attr[61].slew_rate.q), + .ds (), + .qs (dio_pad_attr_61_slew_rate_61_qs) + ); + assign reg2hw.dio_pad_attr[61].slew_rate.qe = dio_pad_attr_61_qe; + + // F[drive_strength_61]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_61_drive_strength_61 ( + .re (dio_pad_attr_61_re), + .we (dio_pad_attr_61_gated_we), + .wd (dio_pad_attr_61_drive_strength_61_wd), + .d (hw2reg.dio_pad_attr[61].drive_strength.d), + .qre (), + .qe (dio_pad_attr_61_flds_we[9]), + .q (reg2hw.dio_pad_attr[61].drive_strength.q), + .ds (), + .qs (dio_pad_attr_61_drive_strength_61_qs) + ); + assign reg2hw.dio_pad_attr[61].drive_strength.qe = dio_pad_attr_61_qe; + + + // Subregister 62 of Multireg dio_pad_attr + // R[dio_pad_attr_62]: V(True) + logic dio_pad_attr_62_qe; + logic [9:0] dio_pad_attr_62_flds_we; + assign dio_pad_attr_62_qe = &dio_pad_attr_62_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_62_gated_we; + assign dio_pad_attr_62_gated_we = dio_pad_attr_62_we & dio_pad_attr_regwen_62_qs; + // F[invert_62]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_invert_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_invert_62_wd), + .d (hw2reg.dio_pad_attr[62].invert.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[0]), + .q (reg2hw.dio_pad_attr[62].invert.q), + .ds (), + .qs (dio_pad_attr_62_invert_62_qs) + ); + assign reg2hw.dio_pad_attr[62].invert.qe = dio_pad_attr_62_qe; + + // F[virtual_od_en_62]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_virtual_od_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_virtual_od_en_62_wd), + .d (hw2reg.dio_pad_attr[62].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[1]), + .q (reg2hw.dio_pad_attr[62].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_62_virtual_od_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].virtual_od_en.qe = dio_pad_attr_62_qe; + + // F[pull_en_62]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_pull_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_pull_en_62_wd), + .d (hw2reg.dio_pad_attr[62].pull_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[2]), + .q (reg2hw.dio_pad_attr[62].pull_en.q), + .ds (), + .qs (dio_pad_attr_62_pull_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].pull_en.qe = dio_pad_attr_62_qe; + + // F[pull_select_62]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_pull_select_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_pull_select_62_wd), + .d (hw2reg.dio_pad_attr[62].pull_select.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[3]), + .q (reg2hw.dio_pad_attr[62].pull_select.q), + .ds (), + .qs (dio_pad_attr_62_pull_select_62_qs) + ); + assign reg2hw.dio_pad_attr[62].pull_select.qe = dio_pad_attr_62_qe; + + // F[keeper_en_62]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_keeper_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_keeper_en_62_wd), + .d (hw2reg.dio_pad_attr[62].keeper_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[4]), + .q (reg2hw.dio_pad_attr[62].keeper_en.q), + .ds (), + .qs (dio_pad_attr_62_keeper_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].keeper_en.qe = dio_pad_attr_62_qe; + + // F[schmitt_en_62]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_schmitt_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_schmitt_en_62_wd), + .d (hw2reg.dio_pad_attr[62].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[5]), + .q (reg2hw.dio_pad_attr[62].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_62_schmitt_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].schmitt_en.qe = dio_pad_attr_62_qe; + + // F[od_en_62]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_od_en_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_od_en_62_wd), + .d (hw2reg.dio_pad_attr[62].od_en.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[6]), + .q (reg2hw.dio_pad_attr[62].od_en.q), + .ds (), + .qs (dio_pad_attr_62_od_en_62_qs) + ); + assign reg2hw.dio_pad_attr[62].od_en.qe = dio_pad_attr_62_qe; + + // F[input_disable_62]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_62_input_disable_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_input_disable_62_wd), + .d (hw2reg.dio_pad_attr[62].input_disable.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[7]), + .q (reg2hw.dio_pad_attr[62].input_disable.q), + .ds (), + .qs (dio_pad_attr_62_input_disable_62_qs) + ); + assign reg2hw.dio_pad_attr[62].input_disable.qe = dio_pad_attr_62_qe; + + // F[slew_rate_62]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_62_slew_rate_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_slew_rate_62_wd), + .d (hw2reg.dio_pad_attr[62].slew_rate.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[8]), + .q (reg2hw.dio_pad_attr[62].slew_rate.q), + .ds (), + .qs (dio_pad_attr_62_slew_rate_62_qs) + ); + assign reg2hw.dio_pad_attr[62].slew_rate.qe = dio_pad_attr_62_qe; + + // F[drive_strength_62]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_62_drive_strength_62 ( + .re (dio_pad_attr_62_re), + .we (dio_pad_attr_62_gated_we), + .wd (dio_pad_attr_62_drive_strength_62_wd), + .d (hw2reg.dio_pad_attr[62].drive_strength.d), + .qre (), + .qe (dio_pad_attr_62_flds_we[9]), + .q (reg2hw.dio_pad_attr[62].drive_strength.q), + .ds (), + .qs (dio_pad_attr_62_drive_strength_62_qs) + ); + assign reg2hw.dio_pad_attr[62].drive_strength.qe = dio_pad_attr_62_qe; + + + // Subregister 63 of Multireg dio_pad_attr + // R[dio_pad_attr_63]: V(True) + logic dio_pad_attr_63_qe; + logic [9:0] dio_pad_attr_63_flds_we; + assign dio_pad_attr_63_qe = &dio_pad_attr_63_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_63_gated_we; + assign dio_pad_attr_63_gated_we = dio_pad_attr_63_we & dio_pad_attr_regwen_63_qs; + // F[invert_63]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_invert_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_invert_63_wd), + .d (hw2reg.dio_pad_attr[63].invert.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[0]), + .q (reg2hw.dio_pad_attr[63].invert.q), + .ds (), + .qs (dio_pad_attr_63_invert_63_qs) + ); + assign reg2hw.dio_pad_attr[63].invert.qe = dio_pad_attr_63_qe; + + // F[virtual_od_en_63]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_virtual_od_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_virtual_od_en_63_wd), + .d (hw2reg.dio_pad_attr[63].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[1]), + .q (reg2hw.dio_pad_attr[63].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_63_virtual_od_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].virtual_od_en.qe = dio_pad_attr_63_qe; + + // F[pull_en_63]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_pull_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_pull_en_63_wd), + .d (hw2reg.dio_pad_attr[63].pull_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[2]), + .q (reg2hw.dio_pad_attr[63].pull_en.q), + .ds (), + .qs (dio_pad_attr_63_pull_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].pull_en.qe = dio_pad_attr_63_qe; + + // F[pull_select_63]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_pull_select_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_pull_select_63_wd), + .d (hw2reg.dio_pad_attr[63].pull_select.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[3]), + .q (reg2hw.dio_pad_attr[63].pull_select.q), + .ds (), + .qs (dio_pad_attr_63_pull_select_63_qs) + ); + assign reg2hw.dio_pad_attr[63].pull_select.qe = dio_pad_attr_63_qe; + + // F[keeper_en_63]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_keeper_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_keeper_en_63_wd), + .d (hw2reg.dio_pad_attr[63].keeper_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[4]), + .q (reg2hw.dio_pad_attr[63].keeper_en.q), + .ds (), + .qs (dio_pad_attr_63_keeper_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].keeper_en.qe = dio_pad_attr_63_qe; + + // F[schmitt_en_63]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_schmitt_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_schmitt_en_63_wd), + .d (hw2reg.dio_pad_attr[63].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[5]), + .q (reg2hw.dio_pad_attr[63].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_63_schmitt_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].schmitt_en.qe = dio_pad_attr_63_qe; + + // F[od_en_63]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_od_en_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_od_en_63_wd), + .d (hw2reg.dio_pad_attr[63].od_en.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[6]), + .q (reg2hw.dio_pad_attr[63].od_en.q), + .ds (), + .qs (dio_pad_attr_63_od_en_63_qs) + ); + assign reg2hw.dio_pad_attr[63].od_en.qe = dio_pad_attr_63_qe; + + // F[input_disable_63]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_63_input_disable_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_input_disable_63_wd), + .d (hw2reg.dio_pad_attr[63].input_disable.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[7]), + .q (reg2hw.dio_pad_attr[63].input_disable.q), + .ds (), + .qs (dio_pad_attr_63_input_disable_63_qs) + ); + assign reg2hw.dio_pad_attr[63].input_disable.qe = dio_pad_attr_63_qe; + + // F[slew_rate_63]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_63_slew_rate_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_slew_rate_63_wd), + .d (hw2reg.dio_pad_attr[63].slew_rate.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[8]), + .q (reg2hw.dio_pad_attr[63].slew_rate.q), + .ds (), + .qs (dio_pad_attr_63_slew_rate_63_qs) + ); + assign reg2hw.dio_pad_attr[63].slew_rate.qe = dio_pad_attr_63_qe; + + // F[drive_strength_63]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_63_drive_strength_63 ( + .re (dio_pad_attr_63_re), + .we (dio_pad_attr_63_gated_we), + .wd (dio_pad_attr_63_drive_strength_63_wd), + .d (hw2reg.dio_pad_attr[63].drive_strength.d), + .qre (), + .qe (dio_pad_attr_63_flds_we[9]), + .q (reg2hw.dio_pad_attr[63].drive_strength.q), + .ds (), + .qs (dio_pad_attr_63_drive_strength_63_qs) + ); + assign reg2hw.dio_pad_attr[63].drive_strength.qe = dio_pad_attr_63_qe; + + + // Subregister 64 of Multireg dio_pad_attr + // R[dio_pad_attr_64]: V(True) + logic dio_pad_attr_64_qe; + logic [9:0] dio_pad_attr_64_flds_we; + assign dio_pad_attr_64_qe = &dio_pad_attr_64_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_64_gated_we; + assign dio_pad_attr_64_gated_we = dio_pad_attr_64_we & dio_pad_attr_regwen_64_qs; + // F[invert_64]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_invert_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_invert_64_wd), + .d (hw2reg.dio_pad_attr[64].invert.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[0]), + .q (reg2hw.dio_pad_attr[64].invert.q), + .ds (), + .qs (dio_pad_attr_64_invert_64_qs) + ); + assign reg2hw.dio_pad_attr[64].invert.qe = dio_pad_attr_64_qe; + + // F[virtual_od_en_64]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_virtual_od_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_virtual_od_en_64_wd), + .d (hw2reg.dio_pad_attr[64].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[1]), + .q (reg2hw.dio_pad_attr[64].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_64_virtual_od_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].virtual_od_en.qe = dio_pad_attr_64_qe; + + // F[pull_en_64]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_pull_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_pull_en_64_wd), + .d (hw2reg.dio_pad_attr[64].pull_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[2]), + .q (reg2hw.dio_pad_attr[64].pull_en.q), + .ds (), + .qs (dio_pad_attr_64_pull_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].pull_en.qe = dio_pad_attr_64_qe; + + // F[pull_select_64]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_pull_select_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_pull_select_64_wd), + .d (hw2reg.dio_pad_attr[64].pull_select.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[3]), + .q (reg2hw.dio_pad_attr[64].pull_select.q), + .ds (), + .qs (dio_pad_attr_64_pull_select_64_qs) + ); + assign reg2hw.dio_pad_attr[64].pull_select.qe = dio_pad_attr_64_qe; + + // F[keeper_en_64]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_keeper_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_keeper_en_64_wd), + .d (hw2reg.dio_pad_attr[64].keeper_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[4]), + .q (reg2hw.dio_pad_attr[64].keeper_en.q), + .ds (), + .qs (dio_pad_attr_64_keeper_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].keeper_en.qe = dio_pad_attr_64_qe; + + // F[schmitt_en_64]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_schmitt_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_schmitt_en_64_wd), + .d (hw2reg.dio_pad_attr[64].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[5]), + .q (reg2hw.dio_pad_attr[64].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_64_schmitt_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].schmitt_en.qe = dio_pad_attr_64_qe; + + // F[od_en_64]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_od_en_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_od_en_64_wd), + .d (hw2reg.dio_pad_attr[64].od_en.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[6]), + .q (reg2hw.dio_pad_attr[64].od_en.q), + .ds (), + .qs (dio_pad_attr_64_od_en_64_qs) + ); + assign reg2hw.dio_pad_attr[64].od_en.qe = dio_pad_attr_64_qe; + + // F[input_disable_64]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_64_input_disable_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_input_disable_64_wd), + .d (hw2reg.dio_pad_attr[64].input_disable.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[7]), + .q (reg2hw.dio_pad_attr[64].input_disable.q), + .ds (), + .qs (dio_pad_attr_64_input_disable_64_qs) + ); + assign reg2hw.dio_pad_attr[64].input_disable.qe = dio_pad_attr_64_qe; + + // F[slew_rate_64]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_64_slew_rate_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_slew_rate_64_wd), + .d (hw2reg.dio_pad_attr[64].slew_rate.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[8]), + .q (reg2hw.dio_pad_attr[64].slew_rate.q), + .ds (), + .qs (dio_pad_attr_64_slew_rate_64_qs) + ); + assign reg2hw.dio_pad_attr[64].slew_rate.qe = dio_pad_attr_64_qe; + + // F[drive_strength_64]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_64_drive_strength_64 ( + .re (dio_pad_attr_64_re), + .we (dio_pad_attr_64_gated_we), + .wd (dio_pad_attr_64_drive_strength_64_wd), + .d (hw2reg.dio_pad_attr[64].drive_strength.d), + .qre (), + .qe (dio_pad_attr_64_flds_we[9]), + .q (reg2hw.dio_pad_attr[64].drive_strength.q), + .ds (), + .qs (dio_pad_attr_64_drive_strength_64_qs) + ); + assign reg2hw.dio_pad_attr[64].drive_strength.qe = dio_pad_attr_64_qe; + + + // Subregister 65 of Multireg dio_pad_attr + // R[dio_pad_attr_65]: V(True) + logic dio_pad_attr_65_qe; + logic [9:0] dio_pad_attr_65_flds_we; + assign dio_pad_attr_65_qe = &dio_pad_attr_65_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_65_gated_we; + assign dio_pad_attr_65_gated_we = dio_pad_attr_65_we & dio_pad_attr_regwen_65_qs; + // F[invert_65]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_invert_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_invert_65_wd), + .d (hw2reg.dio_pad_attr[65].invert.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[0]), + .q (reg2hw.dio_pad_attr[65].invert.q), + .ds (), + .qs (dio_pad_attr_65_invert_65_qs) + ); + assign reg2hw.dio_pad_attr[65].invert.qe = dio_pad_attr_65_qe; + + // F[virtual_od_en_65]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_virtual_od_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_virtual_od_en_65_wd), + .d (hw2reg.dio_pad_attr[65].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[1]), + .q (reg2hw.dio_pad_attr[65].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_65_virtual_od_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].virtual_od_en.qe = dio_pad_attr_65_qe; + + // F[pull_en_65]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_pull_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_pull_en_65_wd), + .d (hw2reg.dio_pad_attr[65].pull_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[2]), + .q (reg2hw.dio_pad_attr[65].pull_en.q), + .ds (), + .qs (dio_pad_attr_65_pull_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].pull_en.qe = dio_pad_attr_65_qe; + + // F[pull_select_65]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_pull_select_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_pull_select_65_wd), + .d (hw2reg.dio_pad_attr[65].pull_select.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[3]), + .q (reg2hw.dio_pad_attr[65].pull_select.q), + .ds (), + .qs (dio_pad_attr_65_pull_select_65_qs) + ); + assign reg2hw.dio_pad_attr[65].pull_select.qe = dio_pad_attr_65_qe; + + // F[keeper_en_65]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_keeper_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_keeper_en_65_wd), + .d (hw2reg.dio_pad_attr[65].keeper_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[4]), + .q (reg2hw.dio_pad_attr[65].keeper_en.q), + .ds (), + .qs (dio_pad_attr_65_keeper_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].keeper_en.qe = dio_pad_attr_65_qe; + + // F[schmitt_en_65]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_schmitt_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_schmitt_en_65_wd), + .d (hw2reg.dio_pad_attr[65].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[5]), + .q (reg2hw.dio_pad_attr[65].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_65_schmitt_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].schmitt_en.qe = dio_pad_attr_65_qe; + + // F[od_en_65]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_od_en_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_od_en_65_wd), + .d (hw2reg.dio_pad_attr[65].od_en.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[6]), + .q (reg2hw.dio_pad_attr[65].od_en.q), + .ds (), + .qs (dio_pad_attr_65_od_en_65_qs) + ); + assign reg2hw.dio_pad_attr[65].od_en.qe = dio_pad_attr_65_qe; + + // F[input_disable_65]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_65_input_disable_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_input_disable_65_wd), + .d (hw2reg.dio_pad_attr[65].input_disable.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[7]), + .q (reg2hw.dio_pad_attr[65].input_disable.q), + .ds (), + .qs (dio_pad_attr_65_input_disable_65_qs) + ); + assign reg2hw.dio_pad_attr[65].input_disable.qe = dio_pad_attr_65_qe; + + // F[slew_rate_65]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_65_slew_rate_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_slew_rate_65_wd), + .d (hw2reg.dio_pad_attr[65].slew_rate.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[8]), + .q (reg2hw.dio_pad_attr[65].slew_rate.q), + .ds (), + .qs (dio_pad_attr_65_slew_rate_65_qs) + ); + assign reg2hw.dio_pad_attr[65].slew_rate.qe = dio_pad_attr_65_qe; + + // F[drive_strength_65]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_65_drive_strength_65 ( + .re (dio_pad_attr_65_re), + .we (dio_pad_attr_65_gated_we), + .wd (dio_pad_attr_65_drive_strength_65_wd), + .d (hw2reg.dio_pad_attr[65].drive_strength.d), + .qre (), + .qe (dio_pad_attr_65_flds_we[9]), + .q (reg2hw.dio_pad_attr[65].drive_strength.q), + .ds (), + .qs (dio_pad_attr_65_drive_strength_65_qs) + ); + assign reg2hw.dio_pad_attr[65].drive_strength.qe = dio_pad_attr_65_qe; + + + // Subregister 66 of Multireg dio_pad_attr + // R[dio_pad_attr_66]: V(True) + logic dio_pad_attr_66_qe; + logic [9:0] dio_pad_attr_66_flds_we; + assign dio_pad_attr_66_qe = &dio_pad_attr_66_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_66_gated_we; + assign dio_pad_attr_66_gated_we = dio_pad_attr_66_we & dio_pad_attr_regwen_66_qs; + // F[invert_66]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_invert_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_invert_66_wd), + .d (hw2reg.dio_pad_attr[66].invert.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[0]), + .q (reg2hw.dio_pad_attr[66].invert.q), + .ds (), + .qs (dio_pad_attr_66_invert_66_qs) + ); + assign reg2hw.dio_pad_attr[66].invert.qe = dio_pad_attr_66_qe; + + // F[virtual_od_en_66]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_virtual_od_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_virtual_od_en_66_wd), + .d (hw2reg.dio_pad_attr[66].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[1]), + .q (reg2hw.dio_pad_attr[66].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_66_virtual_od_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].virtual_od_en.qe = dio_pad_attr_66_qe; + + // F[pull_en_66]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_pull_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_pull_en_66_wd), + .d (hw2reg.dio_pad_attr[66].pull_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[2]), + .q (reg2hw.dio_pad_attr[66].pull_en.q), + .ds (), + .qs (dio_pad_attr_66_pull_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].pull_en.qe = dio_pad_attr_66_qe; + + // F[pull_select_66]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_pull_select_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_pull_select_66_wd), + .d (hw2reg.dio_pad_attr[66].pull_select.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[3]), + .q (reg2hw.dio_pad_attr[66].pull_select.q), + .ds (), + .qs (dio_pad_attr_66_pull_select_66_qs) + ); + assign reg2hw.dio_pad_attr[66].pull_select.qe = dio_pad_attr_66_qe; + + // F[keeper_en_66]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_keeper_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_keeper_en_66_wd), + .d (hw2reg.dio_pad_attr[66].keeper_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[4]), + .q (reg2hw.dio_pad_attr[66].keeper_en.q), + .ds (), + .qs (dio_pad_attr_66_keeper_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].keeper_en.qe = dio_pad_attr_66_qe; + + // F[schmitt_en_66]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_schmitt_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_schmitt_en_66_wd), + .d (hw2reg.dio_pad_attr[66].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[5]), + .q (reg2hw.dio_pad_attr[66].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_66_schmitt_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].schmitt_en.qe = dio_pad_attr_66_qe; + + // F[od_en_66]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_od_en_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_od_en_66_wd), + .d (hw2reg.dio_pad_attr[66].od_en.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[6]), + .q (reg2hw.dio_pad_attr[66].od_en.q), + .ds (), + .qs (dio_pad_attr_66_od_en_66_qs) + ); + assign reg2hw.dio_pad_attr[66].od_en.qe = dio_pad_attr_66_qe; + + // F[input_disable_66]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_66_input_disable_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_input_disable_66_wd), + .d (hw2reg.dio_pad_attr[66].input_disable.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[7]), + .q (reg2hw.dio_pad_attr[66].input_disable.q), + .ds (), + .qs (dio_pad_attr_66_input_disable_66_qs) + ); + assign reg2hw.dio_pad_attr[66].input_disable.qe = dio_pad_attr_66_qe; + + // F[slew_rate_66]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_66_slew_rate_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_slew_rate_66_wd), + .d (hw2reg.dio_pad_attr[66].slew_rate.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[8]), + .q (reg2hw.dio_pad_attr[66].slew_rate.q), + .ds (), + .qs (dio_pad_attr_66_slew_rate_66_qs) + ); + assign reg2hw.dio_pad_attr[66].slew_rate.qe = dio_pad_attr_66_qe; + + // F[drive_strength_66]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_66_drive_strength_66 ( + .re (dio_pad_attr_66_re), + .we (dio_pad_attr_66_gated_we), + .wd (dio_pad_attr_66_drive_strength_66_wd), + .d (hw2reg.dio_pad_attr[66].drive_strength.d), + .qre (), + .qe (dio_pad_attr_66_flds_we[9]), + .q (reg2hw.dio_pad_attr[66].drive_strength.q), + .ds (), + .qs (dio_pad_attr_66_drive_strength_66_qs) + ); + assign reg2hw.dio_pad_attr[66].drive_strength.qe = dio_pad_attr_66_qe; + + + // Subregister 67 of Multireg dio_pad_attr + // R[dio_pad_attr_67]: V(True) + logic dio_pad_attr_67_qe; + logic [9:0] dio_pad_attr_67_flds_we; + assign dio_pad_attr_67_qe = &dio_pad_attr_67_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_67_gated_we; + assign dio_pad_attr_67_gated_we = dio_pad_attr_67_we & dio_pad_attr_regwen_67_qs; + // F[invert_67]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_invert_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_invert_67_wd), + .d (hw2reg.dio_pad_attr[67].invert.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[0]), + .q (reg2hw.dio_pad_attr[67].invert.q), + .ds (), + .qs (dio_pad_attr_67_invert_67_qs) + ); + assign reg2hw.dio_pad_attr[67].invert.qe = dio_pad_attr_67_qe; + + // F[virtual_od_en_67]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_virtual_od_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_virtual_od_en_67_wd), + .d (hw2reg.dio_pad_attr[67].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[1]), + .q (reg2hw.dio_pad_attr[67].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_67_virtual_od_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].virtual_od_en.qe = dio_pad_attr_67_qe; + + // F[pull_en_67]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_pull_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_pull_en_67_wd), + .d (hw2reg.dio_pad_attr[67].pull_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[2]), + .q (reg2hw.dio_pad_attr[67].pull_en.q), + .ds (), + .qs (dio_pad_attr_67_pull_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].pull_en.qe = dio_pad_attr_67_qe; + + // F[pull_select_67]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_pull_select_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_pull_select_67_wd), + .d (hw2reg.dio_pad_attr[67].pull_select.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[3]), + .q (reg2hw.dio_pad_attr[67].pull_select.q), + .ds (), + .qs (dio_pad_attr_67_pull_select_67_qs) + ); + assign reg2hw.dio_pad_attr[67].pull_select.qe = dio_pad_attr_67_qe; + + // F[keeper_en_67]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_keeper_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_keeper_en_67_wd), + .d (hw2reg.dio_pad_attr[67].keeper_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[4]), + .q (reg2hw.dio_pad_attr[67].keeper_en.q), + .ds (), + .qs (dio_pad_attr_67_keeper_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].keeper_en.qe = dio_pad_attr_67_qe; + + // F[schmitt_en_67]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_schmitt_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_schmitt_en_67_wd), + .d (hw2reg.dio_pad_attr[67].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[5]), + .q (reg2hw.dio_pad_attr[67].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_67_schmitt_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].schmitt_en.qe = dio_pad_attr_67_qe; + + // F[od_en_67]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_od_en_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_od_en_67_wd), + .d (hw2reg.dio_pad_attr[67].od_en.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[6]), + .q (reg2hw.dio_pad_attr[67].od_en.q), + .ds (), + .qs (dio_pad_attr_67_od_en_67_qs) + ); + assign reg2hw.dio_pad_attr[67].od_en.qe = dio_pad_attr_67_qe; + + // F[input_disable_67]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_67_input_disable_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_input_disable_67_wd), + .d (hw2reg.dio_pad_attr[67].input_disable.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[7]), + .q (reg2hw.dio_pad_attr[67].input_disable.q), + .ds (), + .qs (dio_pad_attr_67_input_disable_67_qs) + ); + assign reg2hw.dio_pad_attr[67].input_disable.qe = dio_pad_attr_67_qe; + + // F[slew_rate_67]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_67_slew_rate_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_slew_rate_67_wd), + .d (hw2reg.dio_pad_attr[67].slew_rate.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[8]), + .q (reg2hw.dio_pad_attr[67].slew_rate.q), + .ds (), + .qs (dio_pad_attr_67_slew_rate_67_qs) + ); + assign reg2hw.dio_pad_attr[67].slew_rate.qe = dio_pad_attr_67_qe; + + // F[drive_strength_67]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_67_drive_strength_67 ( + .re (dio_pad_attr_67_re), + .we (dio_pad_attr_67_gated_we), + .wd (dio_pad_attr_67_drive_strength_67_wd), + .d (hw2reg.dio_pad_attr[67].drive_strength.d), + .qre (), + .qe (dio_pad_attr_67_flds_we[9]), + .q (reg2hw.dio_pad_attr[67].drive_strength.q), + .ds (), + .qs (dio_pad_attr_67_drive_strength_67_qs) + ); + assign reg2hw.dio_pad_attr[67].drive_strength.qe = dio_pad_attr_67_qe; + + + // Subregister 68 of Multireg dio_pad_attr + // R[dio_pad_attr_68]: V(True) + logic dio_pad_attr_68_qe; + logic [9:0] dio_pad_attr_68_flds_we; + assign dio_pad_attr_68_qe = &dio_pad_attr_68_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_68_gated_we; + assign dio_pad_attr_68_gated_we = dio_pad_attr_68_we & dio_pad_attr_regwen_68_qs; + // F[invert_68]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_invert_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_invert_68_wd), + .d (hw2reg.dio_pad_attr[68].invert.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[0]), + .q (reg2hw.dio_pad_attr[68].invert.q), + .ds (), + .qs (dio_pad_attr_68_invert_68_qs) + ); + assign reg2hw.dio_pad_attr[68].invert.qe = dio_pad_attr_68_qe; + + // F[virtual_od_en_68]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_virtual_od_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_virtual_od_en_68_wd), + .d (hw2reg.dio_pad_attr[68].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[1]), + .q (reg2hw.dio_pad_attr[68].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_68_virtual_od_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].virtual_od_en.qe = dio_pad_attr_68_qe; + + // F[pull_en_68]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_pull_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_pull_en_68_wd), + .d (hw2reg.dio_pad_attr[68].pull_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[2]), + .q (reg2hw.dio_pad_attr[68].pull_en.q), + .ds (), + .qs (dio_pad_attr_68_pull_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].pull_en.qe = dio_pad_attr_68_qe; + + // F[pull_select_68]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_pull_select_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_pull_select_68_wd), + .d (hw2reg.dio_pad_attr[68].pull_select.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[3]), + .q (reg2hw.dio_pad_attr[68].pull_select.q), + .ds (), + .qs (dio_pad_attr_68_pull_select_68_qs) + ); + assign reg2hw.dio_pad_attr[68].pull_select.qe = dio_pad_attr_68_qe; + + // F[keeper_en_68]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_keeper_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_keeper_en_68_wd), + .d (hw2reg.dio_pad_attr[68].keeper_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[4]), + .q (reg2hw.dio_pad_attr[68].keeper_en.q), + .ds (), + .qs (dio_pad_attr_68_keeper_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].keeper_en.qe = dio_pad_attr_68_qe; + + // F[schmitt_en_68]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_schmitt_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_schmitt_en_68_wd), + .d (hw2reg.dio_pad_attr[68].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[5]), + .q (reg2hw.dio_pad_attr[68].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_68_schmitt_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].schmitt_en.qe = dio_pad_attr_68_qe; + + // F[od_en_68]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_od_en_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_od_en_68_wd), + .d (hw2reg.dio_pad_attr[68].od_en.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[6]), + .q (reg2hw.dio_pad_attr[68].od_en.q), + .ds (), + .qs (dio_pad_attr_68_od_en_68_qs) + ); + assign reg2hw.dio_pad_attr[68].od_en.qe = dio_pad_attr_68_qe; + + // F[input_disable_68]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_68_input_disable_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_input_disable_68_wd), + .d (hw2reg.dio_pad_attr[68].input_disable.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[7]), + .q (reg2hw.dio_pad_attr[68].input_disable.q), + .ds (), + .qs (dio_pad_attr_68_input_disable_68_qs) + ); + assign reg2hw.dio_pad_attr[68].input_disable.qe = dio_pad_attr_68_qe; + + // F[slew_rate_68]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_68_slew_rate_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_slew_rate_68_wd), + .d (hw2reg.dio_pad_attr[68].slew_rate.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[8]), + .q (reg2hw.dio_pad_attr[68].slew_rate.q), + .ds (), + .qs (dio_pad_attr_68_slew_rate_68_qs) + ); + assign reg2hw.dio_pad_attr[68].slew_rate.qe = dio_pad_attr_68_qe; + + // F[drive_strength_68]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_68_drive_strength_68 ( + .re (dio_pad_attr_68_re), + .we (dio_pad_attr_68_gated_we), + .wd (dio_pad_attr_68_drive_strength_68_wd), + .d (hw2reg.dio_pad_attr[68].drive_strength.d), + .qre (), + .qe (dio_pad_attr_68_flds_we[9]), + .q (reg2hw.dio_pad_attr[68].drive_strength.q), + .ds (), + .qs (dio_pad_attr_68_drive_strength_68_qs) + ); + assign reg2hw.dio_pad_attr[68].drive_strength.qe = dio_pad_attr_68_qe; + + + // Subregister 69 of Multireg dio_pad_attr + // R[dio_pad_attr_69]: V(True) + logic dio_pad_attr_69_qe; + logic [9:0] dio_pad_attr_69_flds_we; + assign dio_pad_attr_69_qe = &dio_pad_attr_69_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_69_gated_we; + assign dio_pad_attr_69_gated_we = dio_pad_attr_69_we & dio_pad_attr_regwen_69_qs; + // F[invert_69]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_invert_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_invert_69_wd), + .d (hw2reg.dio_pad_attr[69].invert.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[0]), + .q (reg2hw.dio_pad_attr[69].invert.q), + .ds (), + .qs (dio_pad_attr_69_invert_69_qs) + ); + assign reg2hw.dio_pad_attr[69].invert.qe = dio_pad_attr_69_qe; + + // F[virtual_od_en_69]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_virtual_od_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_virtual_od_en_69_wd), + .d (hw2reg.dio_pad_attr[69].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[1]), + .q (reg2hw.dio_pad_attr[69].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_69_virtual_od_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].virtual_od_en.qe = dio_pad_attr_69_qe; + + // F[pull_en_69]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_pull_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_pull_en_69_wd), + .d (hw2reg.dio_pad_attr[69].pull_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[2]), + .q (reg2hw.dio_pad_attr[69].pull_en.q), + .ds (), + .qs (dio_pad_attr_69_pull_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].pull_en.qe = dio_pad_attr_69_qe; + + // F[pull_select_69]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_pull_select_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_pull_select_69_wd), + .d (hw2reg.dio_pad_attr[69].pull_select.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[3]), + .q (reg2hw.dio_pad_attr[69].pull_select.q), + .ds (), + .qs (dio_pad_attr_69_pull_select_69_qs) + ); + assign reg2hw.dio_pad_attr[69].pull_select.qe = dio_pad_attr_69_qe; + + // F[keeper_en_69]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_keeper_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_keeper_en_69_wd), + .d (hw2reg.dio_pad_attr[69].keeper_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[4]), + .q (reg2hw.dio_pad_attr[69].keeper_en.q), + .ds (), + .qs (dio_pad_attr_69_keeper_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].keeper_en.qe = dio_pad_attr_69_qe; + + // F[schmitt_en_69]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_schmitt_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_schmitt_en_69_wd), + .d (hw2reg.dio_pad_attr[69].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[5]), + .q (reg2hw.dio_pad_attr[69].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_69_schmitt_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].schmitt_en.qe = dio_pad_attr_69_qe; + + // F[od_en_69]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_od_en_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_od_en_69_wd), + .d (hw2reg.dio_pad_attr[69].od_en.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[6]), + .q (reg2hw.dio_pad_attr[69].od_en.q), + .ds (), + .qs (dio_pad_attr_69_od_en_69_qs) + ); + assign reg2hw.dio_pad_attr[69].od_en.qe = dio_pad_attr_69_qe; + + // F[input_disable_69]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_69_input_disable_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_input_disable_69_wd), + .d (hw2reg.dio_pad_attr[69].input_disable.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[7]), + .q (reg2hw.dio_pad_attr[69].input_disable.q), + .ds (), + .qs (dio_pad_attr_69_input_disable_69_qs) + ); + assign reg2hw.dio_pad_attr[69].input_disable.qe = dio_pad_attr_69_qe; + + // F[slew_rate_69]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_69_slew_rate_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_slew_rate_69_wd), + .d (hw2reg.dio_pad_attr[69].slew_rate.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[8]), + .q (reg2hw.dio_pad_attr[69].slew_rate.q), + .ds (), + .qs (dio_pad_attr_69_slew_rate_69_qs) + ); + assign reg2hw.dio_pad_attr[69].slew_rate.qe = dio_pad_attr_69_qe; + + // F[drive_strength_69]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_69_drive_strength_69 ( + .re (dio_pad_attr_69_re), + .we (dio_pad_attr_69_gated_we), + .wd (dio_pad_attr_69_drive_strength_69_wd), + .d (hw2reg.dio_pad_attr[69].drive_strength.d), + .qre (), + .qe (dio_pad_attr_69_flds_we[9]), + .q (reg2hw.dio_pad_attr[69].drive_strength.q), + .ds (), + .qs (dio_pad_attr_69_drive_strength_69_qs) + ); + assign reg2hw.dio_pad_attr[69].drive_strength.qe = dio_pad_attr_69_qe; + + + // Subregister 70 of Multireg dio_pad_attr + // R[dio_pad_attr_70]: V(True) + logic dio_pad_attr_70_qe; + logic [9:0] dio_pad_attr_70_flds_we; + assign dio_pad_attr_70_qe = &dio_pad_attr_70_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_70_gated_we; + assign dio_pad_attr_70_gated_we = dio_pad_attr_70_we & dio_pad_attr_regwen_70_qs; + // F[invert_70]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_invert_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_invert_70_wd), + .d (hw2reg.dio_pad_attr[70].invert.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[0]), + .q (reg2hw.dio_pad_attr[70].invert.q), + .ds (), + .qs (dio_pad_attr_70_invert_70_qs) + ); + assign reg2hw.dio_pad_attr[70].invert.qe = dio_pad_attr_70_qe; + + // F[virtual_od_en_70]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_virtual_od_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_virtual_od_en_70_wd), + .d (hw2reg.dio_pad_attr[70].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[1]), + .q (reg2hw.dio_pad_attr[70].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_70_virtual_od_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].virtual_od_en.qe = dio_pad_attr_70_qe; + + // F[pull_en_70]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_pull_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_pull_en_70_wd), + .d (hw2reg.dio_pad_attr[70].pull_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[2]), + .q (reg2hw.dio_pad_attr[70].pull_en.q), + .ds (), + .qs (dio_pad_attr_70_pull_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].pull_en.qe = dio_pad_attr_70_qe; + + // F[pull_select_70]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_pull_select_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_pull_select_70_wd), + .d (hw2reg.dio_pad_attr[70].pull_select.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[3]), + .q (reg2hw.dio_pad_attr[70].pull_select.q), + .ds (), + .qs (dio_pad_attr_70_pull_select_70_qs) + ); + assign reg2hw.dio_pad_attr[70].pull_select.qe = dio_pad_attr_70_qe; + + // F[keeper_en_70]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_keeper_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_keeper_en_70_wd), + .d (hw2reg.dio_pad_attr[70].keeper_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[4]), + .q (reg2hw.dio_pad_attr[70].keeper_en.q), + .ds (), + .qs (dio_pad_attr_70_keeper_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].keeper_en.qe = dio_pad_attr_70_qe; + + // F[schmitt_en_70]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_schmitt_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_schmitt_en_70_wd), + .d (hw2reg.dio_pad_attr[70].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[5]), + .q (reg2hw.dio_pad_attr[70].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_70_schmitt_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].schmitt_en.qe = dio_pad_attr_70_qe; + + // F[od_en_70]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_od_en_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_od_en_70_wd), + .d (hw2reg.dio_pad_attr[70].od_en.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[6]), + .q (reg2hw.dio_pad_attr[70].od_en.q), + .ds (), + .qs (dio_pad_attr_70_od_en_70_qs) + ); + assign reg2hw.dio_pad_attr[70].od_en.qe = dio_pad_attr_70_qe; + + // F[input_disable_70]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_70_input_disable_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_input_disable_70_wd), + .d (hw2reg.dio_pad_attr[70].input_disable.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[7]), + .q (reg2hw.dio_pad_attr[70].input_disable.q), + .ds (), + .qs (dio_pad_attr_70_input_disable_70_qs) + ); + assign reg2hw.dio_pad_attr[70].input_disable.qe = dio_pad_attr_70_qe; + + // F[slew_rate_70]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_70_slew_rate_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_slew_rate_70_wd), + .d (hw2reg.dio_pad_attr[70].slew_rate.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[8]), + .q (reg2hw.dio_pad_attr[70].slew_rate.q), + .ds (), + .qs (dio_pad_attr_70_slew_rate_70_qs) + ); + assign reg2hw.dio_pad_attr[70].slew_rate.qe = dio_pad_attr_70_qe; + + // F[drive_strength_70]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_70_drive_strength_70 ( + .re (dio_pad_attr_70_re), + .we (dio_pad_attr_70_gated_we), + .wd (dio_pad_attr_70_drive_strength_70_wd), + .d (hw2reg.dio_pad_attr[70].drive_strength.d), + .qre (), + .qe (dio_pad_attr_70_flds_we[9]), + .q (reg2hw.dio_pad_attr[70].drive_strength.q), + .ds (), + .qs (dio_pad_attr_70_drive_strength_70_qs) + ); + assign reg2hw.dio_pad_attr[70].drive_strength.qe = dio_pad_attr_70_qe; + + + // Subregister 71 of Multireg dio_pad_attr + // R[dio_pad_attr_71]: V(True) + logic dio_pad_attr_71_qe; + logic [9:0] dio_pad_attr_71_flds_we; + assign dio_pad_attr_71_qe = &dio_pad_attr_71_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_71_gated_we; + assign dio_pad_attr_71_gated_we = dio_pad_attr_71_we & dio_pad_attr_regwen_71_qs; + // F[invert_71]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_invert_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_invert_71_wd), + .d (hw2reg.dio_pad_attr[71].invert.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[0]), + .q (reg2hw.dio_pad_attr[71].invert.q), + .ds (), + .qs (dio_pad_attr_71_invert_71_qs) + ); + assign reg2hw.dio_pad_attr[71].invert.qe = dio_pad_attr_71_qe; + + // F[virtual_od_en_71]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_virtual_od_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_virtual_od_en_71_wd), + .d (hw2reg.dio_pad_attr[71].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[1]), + .q (reg2hw.dio_pad_attr[71].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_71_virtual_od_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].virtual_od_en.qe = dio_pad_attr_71_qe; + + // F[pull_en_71]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_pull_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_pull_en_71_wd), + .d (hw2reg.dio_pad_attr[71].pull_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[2]), + .q (reg2hw.dio_pad_attr[71].pull_en.q), + .ds (), + .qs (dio_pad_attr_71_pull_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].pull_en.qe = dio_pad_attr_71_qe; + + // F[pull_select_71]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_pull_select_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_pull_select_71_wd), + .d (hw2reg.dio_pad_attr[71].pull_select.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[3]), + .q (reg2hw.dio_pad_attr[71].pull_select.q), + .ds (), + .qs (dio_pad_attr_71_pull_select_71_qs) + ); + assign reg2hw.dio_pad_attr[71].pull_select.qe = dio_pad_attr_71_qe; + + // F[keeper_en_71]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_keeper_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_keeper_en_71_wd), + .d (hw2reg.dio_pad_attr[71].keeper_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[4]), + .q (reg2hw.dio_pad_attr[71].keeper_en.q), + .ds (), + .qs (dio_pad_attr_71_keeper_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].keeper_en.qe = dio_pad_attr_71_qe; + + // F[schmitt_en_71]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_schmitt_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_schmitt_en_71_wd), + .d (hw2reg.dio_pad_attr[71].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[5]), + .q (reg2hw.dio_pad_attr[71].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_71_schmitt_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].schmitt_en.qe = dio_pad_attr_71_qe; + + // F[od_en_71]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_od_en_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_od_en_71_wd), + .d (hw2reg.dio_pad_attr[71].od_en.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[6]), + .q (reg2hw.dio_pad_attr[71].od_en.q), + .ds (), + .qs (dio_pad_attr_71_od_en_71_qs) + ); + assign reg2hw.dio_pad_attr[71].od_en.qe = dio_pad_attr_71_qe; + + // F[input_disable_71]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_71_input_disable_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_input_disable_71_wd), + .d (hw2reg.dio_pad_attr[71].input_disable.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[7]), + .q (reg2hw.dio_pad_attr[71].input_disable.q), + .ds (), + .qs (dio_pad_attr_71_input_disable_71_qs) + ); + assign reg2hw.dio_pad_attr[71].input_disable.qe = dio_pad_attr_71_qe; + + // F[slew_rate_71]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_71_slew_rate_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_slew_rate_71_wd), + .d (hw2reg.dio_pad_attr[71].slew_rate.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[8]), + .q (reg2hw.dio_pad_attr[71].slew_rate.q), + .ds (), + .qs (dio_pad_attr_71_slew_rate_71_qs) + ); + assign reg2hw.dio_pad_attr[71].slew_rate.qe = dio_pad_attr_71_qe; + + // F[drive_strength_71]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_71_drive_strength_71 ( + .re (dio_pad_attr_71_re), + .we (dio_pad_attr_71_gated_we), + .wd (dio_pad_attr_71_drive_strength_71_wd), + .d (hw2reg.dio_pad_attr[71].drive_strength.d), + .qre (), + .qe (dio_pad_attr_71_flds_we[9]), + .q (reg2hw.dio_pad_attr[71].drive_strength.q), + .ds (), + .qs (dio_pad_attr_71_drive_strength_71_qs) + ); + assign reg2hw.dio_pad_attr[71].drive_strength.qe = dio_pad_attr_71_qe; + + + // Subregister 72 of Multireg dio_pad_attr + // R[dio_pad_attr_72]: V(True) + logic dio_pad_attr_72_qe; + logic [9:0] dio_pad_attr_72_flds_we; + assign dio_pad_attr_72_qe = &dio_pad_attr_72_flds_we; + // Create REGWEN-gated WE signal + logic dio_pad_attr_72_gated_we; + assign dio_pad_attr_72_gated_we = dio_pad_attr_72_we & dio_pad_attr_regwen_72_qs; + // F[invert_72]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_invert_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_invert_72_wd), + .d (hw2reg.dio_pad_attr[72].invert.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[0]), + .q (reg2hw.dio_pad_attr[72].invert.q), + .ds (), + .qs (dio_pad_attr_72_invert_72_qs) + ); + assign reg2hw.dio_pad_attr[72].invert.qe = dio_pad_attr_72_qe; + + // F[virtual_od_en_72]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_virtual_od_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_virtual_od_en_72_wd), + .d (hw2reg.dio_pad_attr[72].virtual_od_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[1]), + .q (reg2hw.dio_pad_attr[72].virtual_od_en.q), + .ds (), + .qs (dio_pad_attr_72_virtual_od_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].virtual_od_en.qe = dio_pad_attr_72_qe; + + // F[pull_en_72]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_pull_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_pull_en_72_wd), + .d (hw2reg.dio_pad_attr[72].pull_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[2]), + .q (reg2hw.dio_pad_attr[72].pull_en.q), + .ds (), + .qs (dio_pad_attr_72_pull_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].pull_en.qe = dio_pad_attr_72_qe; + + // F[pull_select_72]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_pull_select_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_pull_select_72_wd), + .d (hw2reg.dio_pad_attr[72].pull_select.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[3]), + .q (reg2hw.dio_pad_attr[72].pull_select.q), + .ds (), + .qs (dio_pad_attr_72_pull_select_72_qs) + ); + assign reg2hw.dio_pad_attr[72].pull_select.qe = dio_pad_attr_72_qe; + + // F[keeper_en_72]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_keeper_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_keeper_en_72_wd), + .d (hw2reg.dio_pad_attr[72].keeper_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[4]), + .q (reg2hw.dio_pad_attr[72].keeper_en.q), + .ds (), + .qs (dio_pad_attr_72_keeper_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].keeper_en.qe = dio_pad_attr_72_qe; + + // F[schmitt_en_72]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_schmitt_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_schmitt_en_72_wd), + .d (hw2reg.dio_pad_attr[72].schmitt_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[5]), + .q (reg2hw.dio_pad_attr[72].schmitt_en.q), + .ds (), + .qs (dio_pad_attr_72_schmitt_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].schmitt_en.qe = dio_pad_attr_72_qe; + + // F[od_en_72]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_od_en_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_od_en_72_wd), + .d (hw2reg.dio_pad_attr[72].od_en.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[6]), + .q (reg2hw.dio_pad_attr[72].od_en.q), + .ds (), + .qs (dio_pad_attr_72_od_en_72_qs) + ); + assign reg2hw.dio_pad_attr[72].od_en.qe = dio_pad_attr_72_qe; + + // F[input_disable_72]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_dio_pad_attr_72_input_disable_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_input_disable_72_wd), + .d (hw2reg.dio_pad_attr[72].input_disable.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[7]), + .q (reg2hw.dio_pad_attr[72].input_disable.q), + .ds (), + .qs (dio_pad_attr_72_input_disable_72_qs) + ); + assign reg2hw.dio_pad_attr[72].input_disable.qe = dio_pad_attr_72_qe; + + // F[slew_rate_72]: 17:16 + prim_subreg_ext #( + .DW (2) + ) u_dio_pad_attr_72_slew_rate_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_slew_rate_72_wd), + .d (hw2reg.dio_pad_attr[72].slew_rate.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[8]), + .q (reg2hw.dio_pad_attr[72].slew_rate.q), + .ds (), + .qs (dio_pad_attr_72_slew_rate_72_qs) + ); + assign reg2hw.dio_pad_attr[72].slew_rate.qe = dio_pad_attr_72_qe; + + // F[drive_strength_72]: 23:20 + prim_subreg_ext #( + .DW (4) + ) u_dio_pad_attr_72_drive_strength_72 ( + .re (dio_pad_attr_72_re), + .we (dio_pad_attr_72_gated_we), + .wd (dio_pad_attr_72_drive_strength_72_wd), + .d (hw2reg.dio_pad_attr[72].drive_strength.d), + .qre (), + .qe (dio_pad_attr_72_flds_we[9]), + .q (reg2hw.dio_pad_attr[72].drive_strength.q), + .ds (), + .qs (dio_pad_attr_72_drive_strength_72_qs) + ); + assign reg2hw.dio_pad_attr[72].drive_strength.qe = dio_pad_attr_72_qe; + + + // Subregister 0 of Multireg mio_pad_sleep_status + // R[mio_pad_sleep_status]: V(False) + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_0_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[0].de), + .d (hw2reg.mio_pad_sleep_status[0].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[0].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_0_qs) + ); + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_1_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[1].de), + .d (hw2reg.mio_pad_sleep_status[1].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[1].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_1_qs) + ); + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_2_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[2].de), + .d (hw2reg.mio_pad_sleep_status[2].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[2].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_2_qs) + ); + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_3_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[3].de), + .d (hw2reg.mio_pad_sleep_status[3].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[3].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_3_qs) + ); + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_4_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[4].de), + .d (hw2reg.mio_pad_sleep_status[4].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[4].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_4_qs) + ); + + // F[en_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_5_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[5].de), + .d (hw2reg.mio_pad_sleep_status[5].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[5].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_5_qs) + ); + + // F[en_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_6_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[6].de), + .d (hw2reg.mio_pad_sleep_status[6].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[6].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_6_qs) + ); + + // F[en_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_7_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[7].de), + .d (hw2reg.mio_pad_sleep_status[7].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[7].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_7_qs) + ); + + // F[en_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_8_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[8].de), + .d (hw2reg.mio_pad_sleep_status[8].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[8].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_8_qs) + ); + + // F[en_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_9_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[9].de), + .d (hw2reg.mio_pad_sleep_status[9].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[9].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_9_qs) + ); + + // F[en_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_10_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[10].de), + .d (hw2reg.mio_pad_sleep_status[10].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[10].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_10_qs) + ); + + // F[en_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_status_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_status_we), + .wd (mio_pad_sleep_status_en_11_wd), + + // from internal hardware + .de (hw2reg.mio_pad_sleep_status[11].de), + .d (hw2reg.mio_pad_sleep_status[11].d), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_status[11].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_status_en_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_0_we), + .wd (mio_pad_sleep_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_0_qs) + ); + + + // Subregister 1 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_1_we), + .wd (mio_pad_sleep_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_1_qs) + ); + + + // Subregister 2 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_2_we), + .wd (mio_pad_sleep_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_2_qs) + ); + + + // Subregister 3 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_3_we), + .wd (mio_pad_sleep_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_3_qs) + ); + + + // Subregister 4 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_4_we), + .wd (mio_pad_sleep_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_4_qs) + ); + + + // Subregister 5 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_5_we), + .wd (mio_pad_sleep_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_5_qs) + ); + + + // Subregister 6 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_6_we), + .wd (mio_pad_sleep_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_6_qs) + ); + + + // Subregister 7 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_7_we), + .wd (mio_pad_sleep_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_7_qs) + ); + + + // Subregister 8 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_8_we), + .wd (mio_pad_sleep_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_8_qs) + ); + + + // Subregister 9 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_9_we), + .wd (mio_pad_sleep_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_9_qs) + ); + + + // Subregister 10 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_10_we), + .wd (mio_pad_sleep_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_10_qs) + ); + + + // Subregister 11 of Multireg mio_pad_sleep_regwen + // R[mio_pad_sleep_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_mio_pad_sleep_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_regwen_11_we), + .wd (mio_pad_sleep_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_regwen_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_0]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_0_gated_we; + assign mio_pad_sleep_en_0_gated_we = mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_0_gated_we), + .wd (mio_pad_sleep_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[0].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_0_qs) + ); + + + // Subregister 1 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_1]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_1_gated_we; + assign mio_pad_sleep_en_1_gated_we = mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_1_gated_we), + .wd (mio_pad_sleep_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[1].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_1_qs) + ); + + + // Subregister 2 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_2]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_2_gated_we; + assign mio_pad_sleep_en_2_gated_we = mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_2_gated_we), + .wd (mio_pad_sleep_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[2].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_2_qs) + ); + + + // Subregister 3 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_3]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_3_gated_we; + assign mio_pad_sleep_en_3_gated_we = mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_3_gated_we), + .wd (mio_pad_sleep_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[3].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_3_qs) + ); + + + // Subregister 4 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_4]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_4_gated_we; + assign mio_pad_sleep_en_4_gated_we = mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_4_gated_we), + .wd (mio_pad_sleep_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[4].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_4_qs) + ); + + + // Subregister 5 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_5]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_5_gated_we; + assign mio_pad_sleep_en_5_gated_we = mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_5_gated_we), + .wd (mio_pad_sleep_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[5].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_5_qs) + ); + + + // Subregister 6 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_6]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_6_gated_we; + assign mio_pad_sleep_en_6_gated_we = mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_6_gated_we), + .wd (mio_pad_sleep_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[6].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_6_qs) + ); + + + // Subregister 7 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_7]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_7_gated_we; + assign mio_pad_sleep_en_7_gated_we = mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_7_gated_we), + .wd (mio_pad_sleep_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[7].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_7_qs) + ); + + + // Subregister 8 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_8]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_8_gated_we; + assign mio_pad_sleep_en_8_gated_we = mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_8_gated_we), + .wd (mio_pad_sleep_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[8].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_8_qs) + ); + + + // Subregister 9 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_9]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_9_gated_we; + assign mio_pad_sleep_en_9_gated_we = mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_9_gated_we), + .wd (mio_pad_sleep_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[9].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_9_qs) + ); + + + // Subregister 10 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_10]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_10_gated_we; + assign mio_pad_sleep_en_10_gated_we = mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_10_gated_we), + .wd (mio_pad_sleep_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[10].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_10_qs) + ); + + + // Subregister 11 of Multireg mio_pad_sleep_en + // R[mio_pad_sleep_en_11]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_en_11_gated_we; + assign mio_pad_sleep_en_11_gated_we = mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_mio_pad_sleep_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_en_11_gated_we), + .wd (mio_pad_sleep_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_en[11].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_en_11_qs) + ); + + + // Subregister 0 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_0]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_0_gated_we; + assign mio_pad_sleep_mode_0_gated_we = mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_0_gated_we), + .wd (mio_pad_sleep_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[0].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_0_qs) + ); + + + // Subregister 1 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_1]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_1_gated_we; + assign mio_pad_sleep_mode_1_gated_we = mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_1_gated_we), + .wd (mio_pad_sleep_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[1].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_1_qs) + ); + + + // Subregister 2 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_2]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_2_gated_we; + assign mio_pad_sleep_mode_2_gated_we = mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_2_gated_we), + .wd (mio_pad_sleep_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[2].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_2_qs) + ); + + + // Subregister 3 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_3]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_3_gated_we; + assign mio_pad_sleep_mode_3_gated_we = mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_3_gated_we), + .wd (mio_pad_sleep_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[3].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_3_qs) + ); + + + // Subregister 4 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_4]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_4_gated_we; + assign mio_pad_sleep_mode_4_gated_we = mio_pad_sleep_mode_4_we & mio_pad_sleep_regwen_4_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_4_gated_we), + .wd (mio_pad_sleep_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[4].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_4_qs) + ); + + + // Subregister 5 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_5]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_5_gated_we; + assign mio_pad_sleep_mode_5_gated_we = mio_pad_sleep_mode_5_we & mio_pad_sleep_regwen_5_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_5_gated_we), + .wd (mio_pad_sleep_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[5].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_5_qs) + ); + + + // Subregister 6 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_6]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_6_gated_we; + assign mio_pad_sleep_mode_6_gated_we = mio_pad_sleep_mode_6_we & mio_pad_sleep_regwen_6_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_6_gated_we), + .wd (mio_pad_sleep_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[6].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_6_qs) + ); + + + // Subregister 7 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_7]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_7_gated_we; + assign mio_pad_sleep_mode_7_gated_we = mio_pad_sleep_mode_7_we & mio_pad_sleep_regwen_7_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_7_gated_we), + .wd (mio_pad_sleep_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[7].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_7_qs) + ); + + + // Subregister 8 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_8]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_8_gated_we; + assign mio_pad_sleep_mode_8_gated_we = mio_pad_sleep_mode_8_we & mio_pad_sleep_regwen_8_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_8_gated_we), + .wd (mio_pad_sleep_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[8].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_8_qs) + ); + + + // Subregister 9 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_9]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_9_gated_we; + assign mio_pad_sleep_mode_9_gated_we = mio_pad_sleep_mode_9_we & mio_pad_sleep_regwen_9_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_9_gated_we), + .wd (mio_pad_sleep_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[9].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_9_qs) + ); + + + // Subregister 10 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_10]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_10_gated_we; + assign mio_pad_sleep_mode_10_gated_we = mio_pad_sleep_mode_10_we & mio_pad_sleep_regwen_10_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_10_gated_we), + .wd (mio_pad_sleep_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[10].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_10_qs) + ); + + + // Subregister 11 of Multireg mio_pad_sleep_mode + // R[mio_pad_sleep_mode_11]: V(False) + // Create REGWEN-gated WE signal + logic mio_pad_sleep_mode_11_gated_we; + assign mio_pad_sleep_mode_11_gated_we = mio_pad_sleep_mode_11_we & mio_pad_sleep_regwen_11_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_mio_pad_sleep_mode_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (mio_pad_sleep_mode_11_gated_we), + .wd (mio_pad_sleep_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.mio_pad_sleep_mode[11].q), + .ds (), + + // to register interface (read) + .qs (mio_pad_sleep_mode_11_qs) + ); + + + // Subregister 0 of Multireg dio_pad_sleep_status + // R[dio_pad_sleep_status_0]: V(False) + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_0_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[0].de), + .d (hw2reg.dio_pad_sleep_status[0].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[0].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_0_qs) + ); + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_1_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[1].de), + .d (hw2reg.dio_pad_sleep_status[1].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[1].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_1_qs) + ); + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_2_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[2].de), + .d (hw2reg.dio_pad_sleep_status[2].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[2].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_2_qs) + ); + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_3_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[3].de), + .d (hw2reg.dio_pad_sleep_status[3].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[3].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_3_qs) + ); + + // F[en_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_4_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[4].de), + .d (hw2reg.dio_pad_sleep_status[4].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[4].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_4_qs) + ); + + // F[en_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_5_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[5].de), + .d (hw2reg.dio_pad_sleep_status[5].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[5].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_5_qs) + ); + + // F[en_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_6_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[6].de), + .d (hw2reg.dio_pad_sleep_status[6].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[6].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_6_qs) + ); + + // F[en_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_7_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[7].de), + .d (hw2reg.dio_pad_sleep_status[7].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[7].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_7_qs) + ); + + // F[en_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_8_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[8].de), + .d (hw2reg.dio_pad_sleep_status[8].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[8].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_8_qs) + ); + + // F[en_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_9_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[9].de), + .d (hw2reg.dio_pad_sleep_status[9].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[9].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_9_qs) + ); + + // F[en_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_10_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[10].de), + .d (hw2reg.dio_pad_sleep_status[10].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[10].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_10_qs) + ); + + // F[en_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_11_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[11].de), + .d (hw2reg.dio_pad_sleep_status[11].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[11].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_11_qs) + ); + + // F[en_12]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_12_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[12].de), + .d (hw2reg.dio_pad_sleep_status[12].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[12].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_12_qs) + ); + + // F[en_13]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_13_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[13].de), + .d (hw2reg.dio_pad_sleep_status[13].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[13].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_13_qs) + ); + + // F[en_14]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_14_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[14].de), + .d (hw2reg.dio_pad_sleep_status[14].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[14].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_14_qs) + ); + + // F[en_15]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_15_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[15].de), + .d (hw2reg.dio_pad_sleep_status[15].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[15].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_15_qs) + ); + + // F[en_16]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_16_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[16].de), + .d (hw2reg.dio_pad_sleep_status[16].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[16].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_16_qs) + ); + + // F[en_17]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_17_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[17].de), + .d (hw2reg.dio_pad_sleep_status[17].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[17].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_17_qs) + ); + + // F[en_18]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_18_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[18].de), + .d (hw2reg.dio_pad_sleep_status[18].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[18].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_18_qs) + ); + + // F[en_19]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_19_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[19].de), + .d (hw2reg.dio_pad_sleep_status[19].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[19].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_19_qs) + ); + + // F[en_20]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_20_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[20].de), + .d (hw2reg.dio_pad_sleep_status[20].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[20].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_20_qs) + ); + + // F[en_21]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_21_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[21].de), + .d (hw2reg.dio_pad_sleep_status[21].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[21].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_21_qs) + ); + + // F[en_22]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_22_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[22].de), + .d (hw2reg.dio_pad_sleep_status[22].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[22].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_22_qs) + ); + + // F[en_23]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_23_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[23].de), + .d (hw2reg.dio_pad_sleep_status[23].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[23].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_23_qs) + ); + + // F[en_24]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_24_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[24].de), + .d (hw2reg.dio_pad_sleep_status[24].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[24].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_24_qs) + ); + + // F[en_25]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_25_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[25].de), + .d (hw2reg.dio_pad_sleep_status[25].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[25].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_25_qs) + ); + + // F[en_26]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_26_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[26].de), + .d (hw2reg.dio_pad_sleep_status[26].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[26].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_26_qs) + ); + + // F[en_27]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_27_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[27].de), + .d (hw2reg.dio_pad_sleep_status[27].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[27].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_27_qs) + ); + + // F[en_28]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_28_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[28].de), + .d (hw2reg.dio_pad_sleep_status[28].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[28].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_28_qs) + ); + + // F[en_29]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_29_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[29].de), + .d (hw2reg.dio_pad_sleep_status[29].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[29].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_29_qs) + ); + + // F[en_30]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_30_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[30].de), + .d (hw2reg.dio_pad_sleep_status[30].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[30].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_30_qs) + ); + + // F[en_31]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_0_en_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_0_we), + .wd (dio_pad_sleep_status_0_en_31_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[31].de), + .d (hw2reg.dio_pad_sleep_status[31].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[31].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_0_en_31_qs) + ); + + + // Subregister 1 of Multireg dio_pad_sleep_status + // R[dio_pad_sleep_status_1]: V(False) + // F[en_32]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_32_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[32].de), + .d (hw2reg.dio_pad_sleep_status[32].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[32].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_32_qs) + ); + + // F[en_33]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_33_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[33].de), + .d (hw2reg.dio_pad_sleep_status[33].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[33].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_33_qs) + ); + + // F[en_34]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_34_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[34].de), + .d (hw2reg.dio_pad_sleep_status[34].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[34].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_34_qs) + ); + + // F[en_35]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_35_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[35].de), + .d (hw2reg.dio_pad_sleep_status[35].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[35].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_35_qs) + ); + + // F[en_36]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_36_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[36].de), + .d (hw2reg.dio_pad_sleep_status[36].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[36].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_36_qs) + ); + + // F[en_37]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_37_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[37].de), + .d (hw2reg.dio_pad_sleep_status[37].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[37].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_37_qs) + ); + + // F[en_38]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_38_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[38].de), + .d (hw2reg.dio_pad_sleep_status[38].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[38].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_38_qs) + ); + + // F[en_39]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_39_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[39].de), + .d (hw2reg.dio_pad_sleep_status[39].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[39].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_39_qs) + ); + + // F[en_40]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_40_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[40].de), + .d (hw2reg.dio_pad_sleep_status[40].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[40].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_40_qs) + ); + + // F[en_41]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_41_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[41].de), + .d (hw2reg.dio_pad_sleep_status[41].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[41].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_41_qs) + ); + + // F[en_42]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_42_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[42].de), + .d (hw2reg.dio_pad_sleep_status[42].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[42].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_42_qs) + ); + + // F[en_43]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_43_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[43].de), + .d (hw2reg.dio_pad_sleep_status[43].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[43].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_43_qs) + ); + + // F[en_44]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_44_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[44].de), + .d (hw2reg.dio_pad_sleep_status[44].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[44].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_44_qs) + ); + + // F[en_45]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_45_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[45].de), + .d (hw2reg.dio_pad_sleep_status[45].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[45].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_45_qs) + ); + + // F[en_46]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_46_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[46].de), + .d (hw2reg.dio_pad_sleep_status[46].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[46].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_46_qs) + ); + + // F[en_47]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_47_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[47].de), + .d (hw2reg.dio_pad_sleep_status[47].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[47].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_47_qs) + ); + + // F[en_48]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_48_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[48].de), + .d (hw2reg.dio_pad_sleep_status[48].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[48].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_48_qs) + ); + + // F[en_49]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_49_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[49].de), + .d (hw2reg.dio_pad_sleep_status[49].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[49].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_49_qs) + ); + + // F[en_50]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_50_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[50].de), + .d (hw2reg.dio_pad_sleep_status[50].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[50].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_50_qs) + ); + + // F[en_51]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_51_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[51].de), + .d (hw2reg.dio_pad_sleep_status[51].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[51].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_51_qs) + ); + + // F[en_52]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_52_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[52].de), + .d (hw2reg.dio_pad_sleep_status[52].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[52].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_52_qs) + ); + + // F[en_53]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_53_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[53].de), + .d (hw2reg.dio_pad_sleep_status[53].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[53].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_53_qs) + ); + + // F[en_54]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_54_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[54].de), + .d (hw2reg.dio_pad_sleep_status[54].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[54].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_54_qs) + ); + + // F[en_55]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_55_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[55].de), + .d (hw2reg.dio_pad_sleep_status[55].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[55].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_55_qs) + ); + + // F[en_56]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_56_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[56].de), + .d (hw2reg.dio_pad_sleep_status[56].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[56].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_56_qs) + ); + + // F[en_57]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_57_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[57].de), + .d (hw2reg.dio_pad_sleep_status[57].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[57].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_57_qs) + ); + + // F[en_58]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_58_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[58].de), + .d (hw2reg.dio_pad_sleep_status[58].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[58].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_58_qs) + ); + + // F[en_59]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_59_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[59].de), + .d (hw2reg.dio_pad_sleep_status[59].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[59].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_59_qs) + ); + + // F[en_60]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_60_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[60].de), + .d (hw2reg.dio_pad_sleep_status[60].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[60].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_60_qs) + ); + + // F[en_61]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_61_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[61].de), + .d (hw2reg.dio_pad_sleep_status[61].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[61].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_61_qs) + ); + + // F[en_62]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_62_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[62].de), + .d (hw2reg.dio_pad_sleep_status[62].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[62].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_62_qs) + ); + + // F[en_63]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_1_en_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_1_we), + .wd (dio_pad_sleep_status_1_en_63_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[63].de), + .d (hw2reg.dio_pad_sleep_status[63].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[63].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_1_en_63_qs) + ); + + + // Subregister 2 of Multireg dio_pad_sleep_status + // R[dio_pad_sleep_status_2]: V(False) + // F[en_64]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_64_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[64].de), + .d (hw2reg.dio_pad_sleep_status[64].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[64].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_64_qs) + ); + + // F[en_65]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_65_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[65].de), + .d (hw2reg.dio_pad_sleep_status[65].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[65].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_65_qs) + ); + + // F[en_66]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_66_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[66].de), + .d (hw2reg.dio_pad_sleep_status[66].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[66].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_66_qs) + ); + + // F[en_67]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_67_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[67].de), + .d (hw2reg.dio_pad_sleep_status[67].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[67].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_67_qs) + ); + + // F[en_68]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_68_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[68].de), + .d (hw2reg.dio_pad_sleep_status[68].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[68].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_68_qs) + ); + + // F[en_69]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_69_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[69].de), + .d (hw2reg.dio_pad_sleep_status[69].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[69].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_69_qs) + ); + + // F[en_70]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_70_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[70].de), + .d (hw2reg.dio_pad_sleep_status[70].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[70].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_70_qs) + ); + + // F[en_71]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_71_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[71].de), + .d (hw2reg.dio_pad_sleep_status[71].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[71].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_71_qs) + ); + + // F[en_72]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_status_2_en_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_status_2_we), + .wd (dio_pad_sleep_status_2_en_72_wd), + + // from internal hardware + .de (hw2reg.dio_pad_sleep_status[72].de), + .d (hw2reg.dio_pad_sleep_status[72].d), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_status[72].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_status_2_en_72_qs) + ); + + + // Subregister 0 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_0_we), + .wd (dio_pad_sleep_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_0_qs) + ); + + + // Subregister 1 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_1_we), + .wd (dio_pad_sleep_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_1_qs) + ); + + + // Subregister 2 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_2_we), + .wd (dio_pad_sleep_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_2_qs) + ); + + + // Subregister 3 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_3_we), + .wd (dio_pad_sleep_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_3_qs) + ); + + + // Subregister 4 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_4_we), + .wd (dio_pad_sleep_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_4_qs) + ); + + + // Subregister 5 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_5_we), + .wd (dio_pad_sleep_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_5_qs) + ); + + + // Subregister 6 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_6_we), + .wd (dio_pad_sleep_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_6_qs) + ); + + + // Subregister 7 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_7_we), + .wd (dio_pad_sleep_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_7_qs) + ); + + + // Subregister 8 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_8]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_8_we), + .wd (dio_pad_sleep_regwen_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_8_qs) + ); + + + // Subregister 9 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_9]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_9_we), + .wd (dio_pad_sleep_regwen_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_9_qs) + ); + + + // Subregister 10 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_10]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_10_we), + .wd (dio_pad_sleep_regwen_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_10_qs) + ); + + + // Subregister 11 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_11]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_11_we), + .wd (dio_pad_sleep_regwen_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_11_qs) + ); + + + // Subregister 12 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_12]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_12_we), + .wd (dio_pad_sleep_regwen_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_12_qs) + ); + + + // Subregister 13 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_13]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_13_we), + .wd (dio_pad_sleep_regwen_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_13_qs) + ); + + + // Subregister 14 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_14]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_14_we), + .wd (dio_pad_sleep_regwen_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_14_qs) + ); + + + // Subregister 15 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_15]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_15_we), + .wd (dio_pad_sleep_regwen_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_15_qs) + ); + + + // Subregister 16 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_16]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_16_we), + .wd (dio_pad_sleep_regwen_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_16_qs) + ); + + + // Subregister 17 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_17]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_17_we), + .wd (dio_pad_sleep_regwen_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_17_qs) + ); + + + // Subregister 18 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_18]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_18_we), + .wd (dio_pad_sleep_regwen_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_18_qs) + ); + + + // Subregister 19 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_19]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_19_we), + .wd (dio_pad_sleep_regwen_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_19_qs) + ); + + + // Subregister 20 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_20]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_20_we), + .wd (dio_pad_sleep_regwen_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_20_qs) + ); + + + // Subregister 21 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_21]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_21_we), + .wd (dio_pad_sleep_regwen_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_21_qs) + ); + + + // Subregister 22 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_22]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_22_we), + .wd (dio_pad_sleep_regwen_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_22_qs) + ); + + + // Subregister 23 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_23]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_23_we), + .wd (dio_pad_sleep_regwen_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_23_qs) + ); + + + // Subregister 24 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_24]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_24_we), + .wd (dio_pad_sleep_regwen_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_24_qs) + ); + + + // Subregister 25 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_25]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_25_we), + .wd (dio_pad_sleep_regwen_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_25_qs) + ); + + + // Subregister 26 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_26]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_26_we), + .wd (dio_pad_sleep_regwen_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_26_qs) + ); + + + // Subregister 27 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_27]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_27_we), + .wd (dio_pad_sleep_regwen_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_27_qs) + ); + + + // Subregister 28 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_28]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_28_we), + .wd (dio_pad_sleep_regwen_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_28_qs) + ); + + + // Subregister 29 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_29]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_29_we), + .wd (dio_pad_sleep_regwen_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_29_qs) + ); + + + // Subregister 30 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_30]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_30_we), + .wd (dio_pad_sleep_regwen_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_30_qs) + ); + + + // Subregister 31 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_31]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_31_we), + .wd (dio_pad_sleep_regwen_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_31_qs) + ); + + + // Subregister 32 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_32]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_32_we), + .wd (dio_pad_sleep_regwen_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_32_qs) + ); + + + // Subregister 33 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_33]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_33_we), + .wd (dio_pad_sleep_regwen_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_33_qs) + ); + + + // Subregister 34 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_34]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_34_we), + .wd (dio_pad_sleep_regwen_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_34_qs) + ); + + + // Subregister 35 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_35]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_35_we), + .wd (dio_pad_sleep_regwen_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_35_qs) + ); + + + // Subregister 36 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_36]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_36_we), + .wd (dio_pad_sleep_regwen_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_36_qs) + ); + + + // Subregister 37 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_37]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_37_we), + .wd (dio_pad_sleep_regwen_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_38]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_38_we), + .wd (dio_pad_sleep_regwen_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_39]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_39_we), + .wd (dio_pad_sleep_regwen_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_40]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_40_we), + .wd (dio_pad_sleep_regwen_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_41]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_41_we), + .wd (dio_pad_sleep_regwen_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_42]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_42_we), + .wd (dio_pad_sleep_regwen_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_42_qs) + ); + + + // Subregister 43 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_43]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_43_we), + .wd (dio_pad_sleep_regwen_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_43_qs) + ); + + + // Subregister 44 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_44]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_44_we), + .wd (dio_pad_sleep_regwen_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_44_qs) + ); + + + // Subregister 45 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_45]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_45_we), + .wd (dio_pad_sleep_regwen_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_45_qs) + ); + + + // Subregister 46 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_46]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_46_we), + .wd (dio_pad_sleep_regwen_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_46_qs) + ); + + + // Subregister 47 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_47]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_47_we), + .wd (dio_pad_sleep_regwen_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_47_qs) + ); + + + // Subregister 48 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_48]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_48_we), + .wd (dio_pad_sleep_regwen_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_48_qs) + ); + + + // Subregister 49 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_49]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_49_we), + .wd (dio_pad_sleep_regwen_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_49_qs) + ); + + + // Subregister 50 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_50]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_50_we), + .wd (dio_pad_sleep_regwen_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_50_qs) + ); + + + // Subregister 51 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_51]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_51_we), + .wd (dio_pad_sleep_regwen_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_51_qs) + ); + + + // Subregister 52 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_52]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_52_we), + .wd (dio_pad_sleep_regwen_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_52_qs) + ); + + + // Subregister 53 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_53]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_53_we), + .wd (dio_pad_sleep_regwen_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_53_qs) + ); + + + // Subregister 54 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_54]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_54_we), + .wd (dio_pad_sleep_regwen_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_54_qs) + ); + + + // Subregister 55 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_55]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_55_we), + .wd (dio_pad_sleep_regwen_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_55_qs) + ); + + + // Subregister 56 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_56]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_56_we), + .wd (dio_pad_sleep_regwen_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_56_qs) + ); + + + // Subregister 57 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_57]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_57_we), + .wd (dio_pad_sleep_regwen_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_57_qs) + ); + + + // Subregister 58 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_58]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_58_we), + .wd (dio_pad_sleep_regwen_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_58_qs) + ); + + + // Subregister 59 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_59]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_59_we), + .wd (dio_pad_sleep_regwen_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_59_qs) + ); + + + // Subregister 60 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_60]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_60_we), + .wd (dio_pad_sleep_regwen_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_60_qs) + ); + + + // Subregister 61 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_61]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_61_we), + .wd (dio_pad_sleep_regwen_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_61_qs) + ); + + + // Subregister 62 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_62]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_62_we), + .wd (dio_pad_sleep_regwen_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_62_qs) + ); + + + // Subregister 63 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_63]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_63_we), + .wd (dio_pad_sleep_regwen_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_63_qs) + ); + + + // Subregister 64 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_64]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_64_we), + .wd (dio_pad_sleep_regwen_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_64_qs) + ); + + + // Subregister 65 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_65]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_65_we), + .wd (dio_pad_sleep_regwen_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_65_qs) + ); + + + // Subregister 66 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_66]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_66_we), + .wd (dio_pad_sleep_regwen_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_66_qs) + ); + + + // Subregister 67 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_67]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_67_we), + .wd (dio_pad_sleep_regwen_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_67_qs) + ); + + + // Subregister 68 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_68]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_68_we), + .wd (dio_pad_sleep_regwen_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_68_qs) + ); + + + // Subregister 69 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_69]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_69_we), + .wd (dio_pad_sleep_regwen_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_69_qs) + ); + + + // Subregister 70 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_70]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_70_we), + .wd (dio_pad_sleep_regwen_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_70_qs) + ); + + + // Subregister 71 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_71]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_71_we), + .wd (dio_pad_sleep_regwen_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_71_qs) + ); + + + // Subregister 72 of Multireg dio_pad_sleep_regwen + // R[dio_pad_sleep_regwen_72]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_dio_pad_sleep_regwen_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_regwen_72_we), + .wd (dio_pad_sleep_regwen_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_regwen_72_qs) + ); + + + // Subregister 0 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_0]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_0_gated_we; + assign dio_pad_sleep_en_0_gated_we = dio_pad_sleep_en_0_we & dio_pad_sleep_regwen_0_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_0_gated_we), + .wd (dio_pad_sleep_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[0].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_0_qs) + ); + + + // Subregister 1 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_1]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_1_gated_we; + assign dio_pad_sleep_en_1_gated_we = dio_pad_sleep_en_1_we & dio_pad_sleep_regwen_1_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_1_gated_we), + .wd (dio_pad_sleep_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[1].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_1_qs) + ); + + + // Subregister 2 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_2]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_2_gated_we; + assign dio_pad_sleep_en_2_gated_we = dio_pad_sleep_en_2_we & dio_pad_sleep_regwen_2_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_2_gated_we), + .wd (dio_pad_sleep_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[2].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_2_qs) + ); + + + // Subregister 3 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_3]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_3_gated_we; + assign dio_pad_sleep_en_3_gated_we = dio_pad_sleep_en_3_we & dio_pad_sleep_regwen_3_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_3_gated_we), + .wd (dio_pad_sleep_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[3].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_3_qs) + ); + + + // Subregister 4 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_4]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_4_gated_we; + assign dio_pad_sleep_en_4_gated_we = dio_pad_sleep_en_4_we & dio_pad_sleep_regwen_4_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_4_gated_we), + .wd (dio_pad_sleep_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[4].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_4_qs) + ); + + + // Subregister 5 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_5]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_5_gated_we; + assign dio_pad_sleep_en_5_gated_we = dio_pad_sleep_en_5_we & dio_pad_sleep_regwen_5_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_5_gated_we), + .wd (dio_pad_sleep_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[5].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_5_qs) + ); + + + // Subregister 6 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_6]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_6_gated_we; + assign dio_pad_sleep_en_6_gated_we = dio_pad_sleep_en_6_we & dio_pad_sleep_regwen_6_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_6_gated_we), + .wd (dio_pad_sleep_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[6].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_6_qs) + ); + + + // Subregister 7 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_7]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_7_gated_we; + assign dio_pad_sleep_en_7_gated_we = dio_pad_sleep_en_7_we & dio_pad_sleep_regwen_7_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_7_gated_we), + .wd (dio_pad_sleep_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[7].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_7_qs) + ); + + + // Subregister 8 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_8]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_8_gated_we; + assign dio_pad_sleep_en_8_gated_we = dio_pad_sleep_en_8_we & dio_pad_sleep_regwen_8_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_8_gated_we), + .wd (dio_pad_sleep_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[8].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_8_qs) + ); + + + // Subregister 9 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_9]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_9_gated_we; + assign dio_pad_sleep_en_9_gated_we = dio_pad_sleep_en_9_we & dio_pad_sleep_regwen_9_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_9_gated_we), + .wd (dio_pad_sleep_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[9].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_9_qs) + ); + + + // Subregister 10 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_10]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_10_gated_we; + assign dio_pad_sleep_en_10_gated_we = dio_pad_sleep_en_10_we & dio_pad_sleep_regwen_10_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_10_gated_we), + .wd (dio_pad_sleep_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[10].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_10_qs) + ); + + + // Subregister 11 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_11]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_11_gated_we; + assign dio_pad_sleep_en_11_gated_we = dio_pad_sleep_en_11_we & dio_pad_sleep_regwen_11_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_11_gated_we), + .wd (dio_pad_sleep_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[11].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_11_qs) + ); + + + // Subregister 12 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_12]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_12_gated_we; + assign dio_pad_sleep_en_12_gated_we = dio_pad_sleep_en_12_we & dio_pad_sleep_regwen_12_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_12_gated_we), + .wd (dio_pad_sleep_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[12].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_12_qs) + ); + + + // Subregister 13 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_13]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_13_gated_we; + assign dio_pad_sleep_en_13_gated_we = dio_pad_sleep_en_13_we & dio_pad_sleep_regwen_13_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_13_gated_we), + .wd (dio_pad_sleep_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[13].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_13_qs) + ); + + + // Subregister 14 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_14]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_14_gated_we; + assign dio_pad_sleep_en_14_gated_we = dio_pad_sleep_en_14_we & dio_pad_sleep_regwen_14_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_14_gated_we), + .wd (dio_pad_sleep_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[14].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_14_qs) + ); + + + // Subregister 15 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_15]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_15_gated_we; + assign dio_pad_sleep_en_15_gated_we = dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_15_gated_we), + .wd (dio_pad_sleep_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[15].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_15_qs) + ); + + + // Subregister 16 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_16]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_16_gated_we; + assign dio_pad_sleep_en_16_gated_we = dio_pad_sleep_en_16_we & dio_pad_sleep_regwen_16_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_16_gated_we), + .wd (dio_pad_sleep_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[16].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_16_qs) + ); + + + // Subregister 17 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_17]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_17_gated_we; + assign dio_pad_sleep_en_17_gated_we = dio_pad_sleep_en_17_we & dio_pad_sleep_regwen_17_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_17_gated_we), + .wd (dio_pad_sleep_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[17].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_17_qs) + ); + + + // Subregister 18 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_18]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_18_gated_we; + assign dio_pad_sleep_en_18_gated_we = dio_pad_sleep_en_18_we & dio_pad_sleep_regwen_18_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_18_gated_we), + .wd (dio_pad_sleep_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[18].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_18_qs) + ); + + + // Subregister 19 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_19]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_19_gated_we; + assign dio_pad_sleep_en_19_gated_we = dio_pad_sleep_en_19_we & dio_pad_sleep_regwen_19_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_19_gated_we), + .wd (dio_pad_sleep_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[19].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_19_qs) + ); + + + // Subregister 20 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_20]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_20_gated_we; + assign dio_pad_sleep_en_20_gated_we = dio_pad_sleep_en_20_we & dio_pad_sleep_regwen_20_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_20_gated_we), + .wd (dio_pad_sleep_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[20].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_20_qs) + ); + + + // Subregister 21 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_21]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_21_gated_we; + assign dio_pad_sleep_en_21_gated_we = dio_pad_sleep_en_21_we & dio_pad_sleep_regwen_21_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_21_gated_we), + .wd (dio_pad_sleep_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[21].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_21_qs) + ); + + + // Subregister 22 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_22]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_22_gated_we; + assign dio_pad_sleep_en_22_gated_we = dio_pad_sleep_en_22_we & dio_pad_sleep_regwen_22_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_22_gated_we), + .wd (dio_pad_sleep_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[22].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_22_qs) + ); + + + // Subregister 23 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_23]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_23_gated_we; + assign dio_pad_sleep_en_23_gated_we = dio_pad_sleep_en_23_we & dio_pad_sleep_regwen_23_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_23_gated_we), + .wd (dio_pad_sleep_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[23].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_23_qs) + ); + + + // Subregister 24 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_24]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_24_gated_we; + assign dio_pad_sleep_en_24_gated_we = dio_pad_sleep_en_24_we & dio_pad_sleep_regwen_24_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_24_gated_we), + .wd (dio_pad_sleep_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[24].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_24_qs) + ); + + + // Subregister 25 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_25]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_25_gated_we; + assign dio_pad_sleep_en_25_gated_we = dio_pad_sleep_en_25_we & dio_pad_sleep_regwen_25_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_25_gated_we), + .wd (dio_pad_sleep_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[25].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_25_qs) + ); + + + // Subregister 26 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_26]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_26_gated_we; + assign dio_pad_sleep_en_26_gated_we = dio_pad_sleep_en_26_we & dio_pad_sleep_regwen_26_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_26_gated_we), + .wd (dio_pad_sleep_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[26].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_26_qs) + ); + + + // Subregister 27 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_27]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_27_gated_we; + assign dio_pad_sleep_en_27_gated_we = dio_pad_sleep_en_27_we & dio_pad_sleep_regwen_27_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_27_gated_we), + .wd (dio_pad_sleep_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[27].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_27_qs) + ); + + + // Subregister 28 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_28]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_28_gated_we; + assign dio_pad_sleep_en_28_gated_we = dio_pad_sleep_en_28_we & dio_pad_sleep_regwen_28_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_28_gated_we), + .wd (dio_pad_sleep_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[28].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_28_qs) + ); + + + // Subregister 29 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_29]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_29_gated_we; + assign dio_pad_sleep_en_29_gated_we = dio_pad_sleep_en_29_we & dio_pad_sleep_regwen_29_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_29_gated_we), + .wd (dio_pad_sleep_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[29].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_29_qs) + ); + + + // Subregister 30 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_30]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_30_gated_we; + assign dio_pad_sleep_en_30_gated_we = dio_pad_sleep_en_30_we & dio_pad_sleep_regwen_30_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_30_gated_we), + .wd (dio_pad_sleep_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[30].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_30_qs) + ); + + + // Subregister 31 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_31]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_31_gated_we; + assign dio_pad_sleep_en_31_gated_we = dio_pad_sleep_en_31_we & dio_pad_sleep_regwen_31_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_31_gated_we), + .wd (dio_pad_sleep_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[31].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_31_qs) + ); + + + // Subregister 32 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_32]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_32_gated_we; + assign dio_pad_sleep_en_32_gated_we = dio_pad_sleep_en_32_we & dio_pad_sleep_regwen_32_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_32_gated_we), + .wd (dio_pad_sleep_en_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[32].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_32_qs) + ); + + + // Subregister 33 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_33]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_33_gated_we; + assign dio_pad_sleep_en_33_gated_we = dio_pad_sleep_en_33_we & dio_pad_sleep_regwen_33_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_33_gated_we), + .wd (dio_pad_sleep_en_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[33].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_33_qs) + ); + + + // Subregister 34 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_34]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_34_gated_we; + assign dio_pad_sleep_en_34_gated_we = dio_pad_sleep_en_34_we & dio_pad_sleep_regwen_34_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_34_gated_we), + .wd (dio_pad_sleep_en_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[34].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_34_qs) + ); + + + // Subregister 35 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_35]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_35_gated_we; + assign dio_pad_sleep_en_35_gated_we = dio_pad_sleep_en_35_we & dio_pad_sleep_regwen_35_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_35_gated_we), + .wd (dio_pad_sleep_en_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[35].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_35_qs) + ); + + + // Subregister 36 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_36]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_36_gated_we; + assign dio_pad_sleep_en_36_gated_we = dio_pad_sleep_en_36_we & dio_pad_sleep_regwen_36_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_36_gated_we), + .wd (dio_pad_sleep_en_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[36].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_36_qs) + ); + + + // Subregister 37 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_37]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_37_gated_we; + assign dio_pad_sleep_en_37_gated_we = dio_pad_sleep_en_37_we & dio_pad_sleep_regwen_37_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_37_gated_we), + .wd (dio_pad_sleep_en_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[37].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_38]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_38_gated_we; + assign dio_pad_sleep_en_38_gated_we = dio_pad_sleep_en_38_we & dio_pad_sleep_regwen_38_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_38_gated_we), + .wd (dio_pad_sleep_en_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[38].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_39]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_39_gated_we; + assign dio_pad_sleep_en_39_gated_we = dio_pad_sleep_en_39_we & dio_pad_sleep_regwen_39_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_39_gated_we), + .wd (dio_pad_sleep_en_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[39].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_40]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_40_gated_we; + assign dio_pad_sleep_en_40_gated_we = dio_pad_sleep_en_40_we & dio_pad_sleep_regwen_40_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_40_gated_we), + .wd (dio_pad_sleep_en_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[40].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_41]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_41_gated_we; + assign dio_pad_sleep_en_41_gated_we = dio_pad_sleep_en_41_we & dio_pad_sleep_regwen_41_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_41_gated_we), + .wd (dio_pad_sleep_en_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[41].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_42]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_42_gated_we; + assign dio_pad_sleep_en_42_gated_we = dio_pad_sleep_en_42_we & dio_pad_sleep_regwen_42_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_42_gated_we), + .wd (dio_pad_sleep_en_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[42].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_42_qs) + ); + + + // Subregister 43 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_43]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_43_gated_we; + assign dio_pad_sleep_en_43_gated_we = dio_pad_sleep_en_43_we & dio_pad_sleep_regwen_43_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_43_gated_we), + .wd (dio_pad_sleep_en_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[43].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_43_qs) + ); + + + // Subregister 44 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_44]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_44_gated_we; + assign dio_pad_sleep_en_44_gated_we = dio_pad_sleep_en_44_we & dio_pad_sleep_regwen_44_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_44_gated_we), + .wd (dio_pad_sleep_en_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[44].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_44_qs) + ); + + + // Subregister 45 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_45]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_45_gated_we; + assign dio_pad_sleep_en_45_gated_we = dio_pad_sleep_en_45_we & dio_pad_sleep_regwen_45_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_45_gated_we), + .wd (dio_pad_sleep_en_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[45].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_45_qs) + ); + + + // Subregister 46 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_46]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_46_gated_we; + assign dio_pad_sleep_en_46_gated_we = dio_pad_sleep_en_46_we & dio_pad_sleep_regwen_46_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_46_gated_we), + .wd (dio_pad_sleep_en_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[46].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_46_qs) + ); + + + // Subregister 47 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_47]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_47_gated_we; + assign dio_pad_sleep_en_47_gated_we = dio_pad_sleep_en_47_we & dio_pad_sleep_regwen_47_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_47_gated_we), + .wd (dio_pad_sleep_en_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[47].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_47_qs) + ); + + + // Subregister 48 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_48]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_48_gated_we; + assign dio_pad_sleep_en_48_gated_we = dio_pad_sleep_en_48_we & dio_pad_sleep_regwen_48_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_48_gated_we), + .wd (dio_pad_sleep_en_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[48].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_48_qs) + ); + + + // Subregister 49 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_49]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_49_gated_we; + assign dio_pad_sleep_en_49_gated_we = dio_pad_sleep_en_49_we & dio_pad_sleep_regwen_49_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_49_gated_we), + .wd (dio_pad_sleep_en_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[49].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_49_qs) + ); + + + // Subregister 50 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_50]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_50_gated_we; + assign dio_pad_sleep_en_50_gated_we = dio_pad_sleep_en_50_we & dio_pad_sleep_regwen_50_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_50_gated_we), + .wd (dio_pad_sleep_en_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[50].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_50_qs) + ); + + + // Subregister 51 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_51]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_51_gated_we; + assign dio_pad_sleep_en_51_gated_we = dio_pad_sleep_en_51_we & dio_pad_sleep_regwen_51_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_51_gated_we), + .wd (dio_pad_sleep_en_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[51].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_51_qs) + ); + + + // Subregister 52 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_52]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_52_gated_we; + assign dio_pad_sleep_en_52_gated_we = dio_pad_sleep_en_52_we & dio_pad_sleep_regwen_52_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_52_gated_we), + .wd (dio_pad_sleep_en_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[52].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_52_qs) + ); + + + // Subregister 53 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_53]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_53_gated_we; + assign dio_pad_sleep_en_53_gated_we = dio_pad_sleep_en_53_we & dio_pad_sleep_regwen_53_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_53_gated_we), + .wd (dio_pad_sleep_en_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[53].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_53_qs) + ); + + + // Subregister 54 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_54]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_54_gated_we; + assign dio_pad_sleep_en_54_gated_we = dio_pad_sleep_en_54_we & dio_pad_sleep_regwen_54_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_54_gated_we), + .wd (dio_pad_sleep_en_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[54].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_54_qs) + ); + + + // Subregister 55 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_55]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_55_gated_we; + assign dio_pad_sleep_en_55_gated_we = dio_pad_sleep_en_55_we & dio_pad_sleep_regwen_55_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_55_gated_we), + .wd (dio_pad_sleep_en_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[55].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_55_qs) + ); + + + // Subregister 56 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_56]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_56_gated_we; + assign dio_pad_sleep_en_56_gated_we = dio_pad_sleep_en_56_we & dio_pad_sleep_regwen_56_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_56_gated_we), + .wd (dio_pad_sleep_en_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[56].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_56_qs) + ); + + + // Subregister 57 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_57]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_57_gated_we; + assign dio_pad_sleep_en_57_gated_we = dio_pad_sleep_en_57_we & dio_pad_sleep_regwen_57_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_57_gated_we), + .wd (dio_pad_sleep_en_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[57].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_57_qs) + ); + + + // Subregister 58 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_58]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_58_gated_we; + assign dio_pad_sleep_en_58_gated_we = dio_pad_sleep_en_58_we & dio_pad_sleep_regwen_58_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_58_gated_we), + .wd (dio_pad_sleep_en_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[58].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_58_qs) + ); + + + // Subregister 59 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_59]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_59_gated_we; + assign dio_pad_sleep_en_59_gated_we = dio_pad_sleep_en_59_we & dio_pad_sleep_regwen_59_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_59_gated_we), + .wd (dio_pad_sleep_en_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[59].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_59_qs) + ); + + + // Subregister 60 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_60]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_60_gated_we; + assign dio_pad_sleep_en_60_gated_we = dio_pad_sleep_en_60_we & dio_pad_sleep_regwen_60_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_60_gated_we), + .wd (dio_pad_sleep_en_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[60].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_60_qs) + ); + + + // Subregister 61 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_61]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_61_gated_we; + assign dio_pad_sleep_en_61_gated_we = dio_pad_sleep_en_61_we & dio_pad_sleep_regwen_61_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_61_gated_we), + .wd (dio_pad_sleep_en_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[61].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_61_qs) + ); + + + // Subregister 62 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_62]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_62_gated_we; + assign dio_pad_sleep_en_62_gated_we = dio_pad_sleep_en_62_we & dio_pad_sleep_regwen_62_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_62_gated_we), + .wd (dio_pad_sleep_en_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[62].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_62_qs) + ); + + + // Subregister 63 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_63]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_63_gated_we; + assign dio_pad_sleep_en_63_gated_we = dio_pad_sleep_en_63_we & dio_pad_sleep_regwen_63_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_63_gated_we), + .wd (dio_pad_sleep_en_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[63].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_63_qs) + ); + + + // Subregister 64 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_64]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_64_gated_we; + assign dio_pad_sleep_en_64_gated_we = dio_pad_sleep_en_64_we & dio_pad_sleep_regwen_64_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_64_gated_we), + .wd (dio_pad_sleep_en_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[64].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_64_qs) + ); + + + // Subregister 65 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_65]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_65_gated_we; + assign dio_pad_sleep_en_65_gated_we = dio_pad_sleep_en_65_we & dio_pad_sleep_regwen_65_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_65_gated_we), + .wd (dio_pad_sleep_en_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[65].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_65_qs) + ); + + + // Subregister 66 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_66]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_66_gated_we; + assign dio_pad_sleep_en_66_gated_we = dio_pad_sleep_en_66_we & dio_pad_sleep_regwen_66_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_66_gated_we), + .wd (dio_pad_sleep_en_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[66].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_66_qs) + ); + + + // Subregister 67 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_67]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_67_gated_we; + assign dio_pad_sleep_en_67_gated_we = dio_pad_sleep_en_67_we & dio_pad_sleep_regwen_67_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_67_gated_we), + .wd (dio_pad_sleep_en_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[67].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_67_qs) + ); + + + // Subregister 68 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_68]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_68_gated_we; + assign dio_pad_sleep_en_68_gated_we = dio_pad_sleep_en_68_we & dio_pad_sleep_regwen_68_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_68_gated_we), + .wd (dio_pad_sleep_en_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[68].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_68_qs) + ); + + + // Subregister 69 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_69]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_69_gated_we; + assign dio_pad_sleep_en_69_gated_we = dio_pad_sleep_en_69_we & dio_pad_sleep_regwen_69_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_69_gated_we), + .wd (dio_pad_sleep_en_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[69].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_69_qs) + ); + + + // Subregister 70 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_70]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_70_gated_we; + assign dio_pad_sleep_en_70_gated_we = dio_pad_sleep_en_70_we & dio_pad_sleep_regwen_70_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_70_gated_we), + .wd (dio_pad_sleep_en_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[70].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_70_qs) + ); + + + // Subregister 71 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_71]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_71_gated_we; + assign dio_pad_sleep_en_71_gated_we = dio_pad_sleep_en_71_we & dio_pad_sleep_regwen_71_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_71_gated_we), + .wd (dio_pad_sleep_en_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[71].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_71_qs) + ); + + + // Subregister 72 of Multireg dio_pad_sleep_en + // R[dio_pad_sleep_en_72]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_en_72_gated_we; + assign dio_pad_sleep_en_72_gated_we = dio_pad_sleep_en_72_we & dio_pad_sleep_regwen_72_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_dio_pad_sleep_en_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_en_72_gated_we), + .wd (dio_pad_sleep_en_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_en[72].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_en_72_qs) + ); + + + // Subregister 0 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_0]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_0_gated_we; + assign dio_pad_sleep_mode_0_gated_we = dio_pad_sleep_mode_0_we & dio_pad_sleep_regwen_0_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_0_gated_we), + .wd (dio_pad_sleep_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[0].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_0_qs) + ); + + + // Subregister 1 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_1]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_1_gated_we; + assign dio_pad_sleep_mode_1_gated_we = dio_pad_sleep_mode_1_we & dio_pad_sleep_regwen_1_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_1_gated_we), + .wd (dio_pad_sleep_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[1].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_1_qs) + ); + + + // Subregister 2 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_2]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_2_gated_we; + assign dio_pad_sleep_mode_2_gated_we = dio_pad_sleep_mode_2_we & dio_pad_sleep_regwen_2_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_2_gated_we), + .wd (dio_pad_sleep_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[2].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_2_qs) + ); + + + // Subregister 3 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_3]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_3_gated_we; + assign dio_pad_sleep_mode_3_gated_we = dio_pad_sleep_mode_3_we & dio_pad_sleep_regwen_3_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_3_gated_we), + .wd (dio_pad_sleep_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[3].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_3_qs) + ); + + + // Subregister 4 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_4]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_4_gated_we; + assign dio_pad_sleep_mode_4_gated_we = dio_pad_sleep_mode_4_we & dio_pad_sleep_regwen_4_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_4_gated_we), + .wd (dio_pad_sleep_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[4].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_4_qs) + ); + + + // Subregister 5 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_5]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_5_gated_we; + assign dio_pad_sleep_mode_5_gated_we = dio_pad_sleep_mode_5_we & dio_pad_sleep_regwen_5_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_5_gated_we), + .wd (dio_pad_sleep_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[5].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_5_qs) + ); + + + // Subregister 6 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_6]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_6_gated_we; + assign dio_pad_sleep_mode_6_gated_we = dio_pad_sleep_mode_6_we & dio_pad_sleep_regwen_6_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_6_gated_we), + .wd (dio_pad_sleep_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[6].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_6_qs) + ); + + + // Subregister 7 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_7]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_7_gated_we; + assign dio_pad_sleep_mode_7_gated_we = dio_pad_sleep_mode_7_we & dio_pad_sleep_regwen_7_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_7_gated_we), + .wd (dio_pad_sleep_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[7].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_7_qs) + ); + + + // Subregister 8 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_8]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_8_gated_we; + assign dio_pad_sleep_mode_8_gated_we = dio_pad_sleep_mode_8_we & dio_pad_sleep_regwen_8_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_8_gated_we), + .wd (dio_pad_sleep_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[8].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_8_qs) + ); + + + // Subregister 9 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_9]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_9_gated_we; + assign dio_pad_sleep_mode_9_gated_we = dio_pad_sleep_mode_9_we & dio_pad_sleep_regwen_9_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_9_gated_we), + .wd (dio_pad_sleep_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[9].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_9_qs) + ); + + + // Subregister 10 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_10]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_10_gated_we; + assign dio_pad_sleep_mode_10_gated_we = dio_pad_sleep_mode_10_we & dio_pad_sleep_regwen_10_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_10_gated_we), + .wd (dio_pad_sleep_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[10].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_10_qs) + ); + + + // Subregister 11 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_11]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_11_gated_we; + assign dio_pad_sleep_mode_11_gated_we = dio_pad_sleep_mode_11_we & dio_pad_sleep_regwen_11_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_11_gated_we), + .wd (dio_pad_sleep_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[11].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_11_qs) + ); + + + // Subregister 12 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_12]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_12_gated_we; + assign dio_pad_sleep_mode_12_gated_we = dio_pad_sleep_mode_12_we & dio_pad_sleep_regwen_12_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_12_gated_we), + .wd (dio_pad_sleep_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[12].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_12_qs) + ); + + + // Subregister 13 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_13]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_13_gated_we; + assign dio_pad_sleep_mode_13_gated_we = dio_pad_sleep_mode_13_we & dio_pad_sleep_regwen_13_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_13_gated_we), + .wd (dio_pad_sleep_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[13].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_13_qs) + ); + + + // Subregister 14 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_14]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_14_gated_we; + assign dio_pad_sleep_mode_14_gated_we = dio_pad_sleep_mode_14_we & dio_pad_sleep_regwen_14_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_14_gated_we), + .wd (dio_pad_sleep_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[14].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_14_qs) + ); + + + // Subregister 15 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_15]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_15_gated_we; + assign dio_pad_sleep_mode_15_gated_we = dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_15_gated_we), + .wd (dio_pad_sleep_mode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[15].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_15_qs) + ); + + + // Subregister 16 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_16]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_16_gated_we; + assign dio_pad_sleep_mode_16_gated_we = dio_pad_sleep_mode_16_we & dio_pad_sleep_regwen_16_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_16_gated_we), + .wd (dio_pad_sleep_mode_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[16].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_16_qs) + ); + + + // Subregister 17 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_17]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_17_gated_we; + assign dio_pad_sleep_mode_17_gated_we = dio_pad_sleep_mode_17_we & dio_pad_sleep_regwen_17_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_17_gated_we), + .wd (dio_pad_sleep_mode_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[17].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_17_qs) + ); + + + // Subregister 18 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_18]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_18_gated_we; + assign dio_pad_sleep_mode_18_gated_we = dio_pad_sleep_mode_18_we & dio_pad_sleep_regwen_18_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_18_gated_we), + .wd (dio_pad_sleep_mode_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[18].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_18_qs) + ); + + + // Subregister 19 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_19]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_19_gated_we; + assign dio_pad_sleep_mode_19_gated_we = dio_pad_sleep_mode_19_we & dio_pad_sleep_regwen_19_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_19_gated_we), + .wd (dio_pad_sleep_mode_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[19].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_19_qs) + ); + + + // Subregister 20 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_20]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_20_gated_we; + assign dio_pad_sleep_mode_20_gated_we = dio_pad_sleep_mode_20_we & dio_pad_sleep_regwen_20_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_20_gated_we), + .wd (dio_pad_sleep_mode_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[20].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_20_qs) + ); + + + // Subregister 21 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_21]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_21_gated_we; + assign dio_pad_sleep_mode_21_gated_we = dio_pad_sleep_mode_21_we & dio_pad_sleep_regwen_21_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_21_gated_we), + .wd (dio_pad_sleep_mode_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[21].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_21_qs) + ); + + + // Subregister 22 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_22]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_22_gated_we; + assign dio_pad_sleep_mode_22_gated_we = dio_pad_sleep_mode_22_we & dio_pad_sleep_regwen_22_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_22_gated_we), + .wd (dio_pad_sleep_mode_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[22].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_22_qs) + ); + + + // Subregister 23 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_23]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_23_gated_we; + assign dio_pad_sleep_mode_23_gated_we = dio_pad_sleep_mode_23_we & dio_pad_sleep_regwen_23_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_23_gated_we), + .wd (dio_pad_sleep_mode_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[23].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_23_qs) + ); + + + // Subregister 24 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_24]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_24_gated_we; + assign dio_pad_sleep_mode_24_gated_we = dio_pad_sleep_mode_24_we & dio_pad_sleep_regwen_24_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_24_gated_we), + .wd (dio_pad_sleep_mode_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[24].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_24_qs) + ); + + + // Subregister 25 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_25]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_25_gated_we; + assign dio_pad_sleep_mode_25_gated_we = dio_pad_sleep_mode_25_we & dio_pad_sleep_regwen_25_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_25_gated_we), + .wd (dio_pad_sleep_mode_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[25].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_25_qs) + ); + + + // Subregister 26 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_26]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_26_gated_we; + assign dio_pad_sleep_mode_26_gated_we = dio_pad_sleep_mode_26_we & dio_pad_sleep_regwen_26_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_26_gated_we), + .wd (dio_pad_sleep_mode_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[26].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_26_qs) + ); + + + // Subregister 27 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_27]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_27_gated_we; + assign dio_pad_sleep_mode_27_gated_we = dio_pad_sleep_mode_27_we & dio_pad_sleep_regwen_27_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_27_gated_we), + .wd (dio_pad_sleep_mode_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[27].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_27_qs) + ); + + + // Subregister 28 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_28]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_28_gated_we; + assign dio_pad_sleep_mode_28_gated_we = dio_pad_sleep_mode_28_we & dio_pad_sleep_regwen_28_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_28_gated_we), + .wd (dio_pad_sleep_mode_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[28].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_28_qs) + ); + + + // Subregister 29 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_29]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_29_gated_we; + assign dio_pad_sleep_mode_29_gated_we = dio_pad_sleep_mode_29_we & dio_pad_sleep_regwen_29_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_29_gated_we), + .wd (dio_pad_sleep_mode_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[29].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_29_qs) + ); + + + // Subregister 30 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_30]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_30_gated_we; + assign dio_pad_sleep_mode_30_gated_we = dio_pad_sleep_mode_30_we & dio_pad_sleep_regwen_30_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_30_gated_we), + .wd (dio_pad_sleep_mode_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[30].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_30_qs) + ); + + + // Subregister 31 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_31]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_31_gated_we; + assign dio_pad_sleep_mode_31_gated_we = dio_pad_sleep_mode_31_we & dio_pad_sleep_regwen_31_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_31_gated_we), + .wd (dio_pad_sleep_mode_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[31].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_31_qs) + ); + + + // Subregister 32 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_32]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_32_gated_we; + assign dio_pad_sleep_mode_32_gated_we = dio_pad_sleep_mode_32_we & dio_pad_sleep_regwen_32_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_32_gated_we), + .wd (dio_pad_sleep_mode_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[32].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_32_qs) + ); + + + // Subregister 33 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_33]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_33_gated_we; + assign dio_pad_sleep_mode_33_gated_we = dio_pad_sleep_mode_33_we & dio_pad_sleep_regwen_33_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_33_gated_we), + .wd (dio_pad_sleep_mode_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[33].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_33_qs) + ); + + + // Subregister 34 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_34]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_34_gated_we; + assign dio_pad_sleep_mode_34_gated_we = dio_pad_sleep_mode_34_we & dio_pad_sleep_regwen_34_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_34_gated_we), + .wd (dio_pad_sleep_mode_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[34].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_34_qs) + ); + + + // Subregister 35 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_35]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_35_gated_we; + assign dio_pad_sleep_mode_35_gated_we = dio_pad_sleep_mode_35_we & dio_pad_sleep_regwen_35_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_35_gated_we), + .wd (dio_pad_sleep_mode_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[35].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_35_qs) + ); + + + // Subregister 36 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_36]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_36_gated_we; + assign dio_pad_sleep_mode_36_gated_we = dio_pad_sleep_mode_36_we & dio_pad_sleep_regwen_36_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_36_gated_we), + .wd (dio_pad_sleep_mode_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[36].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_36_qs) + ); + + + // Subregister 37 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_37]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_37_gated_we; + assign dio_pad_sleep_mode_37_gated_we = dio_pad_sleep_mode_37_we & dio_pad_sleep_regwen_37_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_37_gated_we), + .wd (dio_pad_sleep_mode_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[37].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_37_qs) + ); + + + // Subregister 38 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_38]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_38_gated_we; + assign dio_pad_sleep_mode_38_gated_we = dio_pad_sleep_mode_38_we & dio_pad_sleep_regwen_38_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_38_gated_we), + .wd (dio_pad_sleep_mode_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[38].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_38_qs) + ); + + + // Subregister 39 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_39]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_39_gated_we; + assign dio_pad_sleep_mode_39_gated_we = dio_pad_sleep_mode_39_we & dio_pad_sleep_regwen_39_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_39_gated_we), + .wd (dio_pad_sleep_mode_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[39].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_39_qs) + ); + + + // Subregister 40 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_40]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_40_gated_we; + assign dio_pad_sleep_mode_40_gated_we = dio_pad_sleep_mode_40_we & dio_pad_sleep_regwen_40_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_40_gated_we), + .wd (dio_pad_sleep_mode_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[40].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_40_qs) + ); + + + // Subregister 41 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_41]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_41_gated_we; + assign dio_pad_sleep_mode_41_gated_we = dio_pad_sleep_mode_41_we & dio_pad_sleep_regwen_41_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_41_gated_we), + .wd (dio_pad_sleep_mode_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[41].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_41_qs) + ); + + + // Subregister 42 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_42]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_42_gated_we; + assign dio_pad_sleep_mode_42_gated_we = dio_pad_sleep_mode_42_we & dio_pad_sleep_regwen_42_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_42_gated_we), + .wd (dio_pad_sleep_mode_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[42].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_42_qs) + ); + + + // Subregister 43 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_43]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_43_gated_we; + assign dio_pad_sleep_mode_43_gated_we = dio_pad_sleep_mode_43_we & dio_pad_sleep_regwen_43_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_43_gated_we), + .wd (dio_pad_sleep_mode_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[43].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_43_qs) + ); + + + // Subregister 44 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_44]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_44_gated_we; + assign dio_pad_sleep_mode_44_gated_we = dio_pad_sleep_mode_44_we & dio_pad_sleep_regwen_44_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_44_gated_we), + .wd (dio_pad_sleep_mode_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[44].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_44_qs) + ); + + + // Subregister 45 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_45]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_45_gated_we; + assign dio_pad_sleep_mode_45_gated_we = dio_pad_sleep_mode_45_we & dio_pad_sleep_regwen_45_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_45_gated_we), + .wd (dio_pad_sleep_mode_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[45].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_45_qs) + ); + + + // Subregister 46 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_46]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_46_gated_we; + assign dio_pad_sleep_mode_46_gated_we = dio_pad_sleep_mode_46_we & dio_pad_sleep_regwen_46_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_46_gated_we), + .wd (dio_pad_sleep_mode_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[46].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_46_qs) + ); + + + // Subregister 47 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_47]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_47_gated_we; + assign dio_pad_sleep_mode_47_gated_we = dio_pad_sleep_mode_47_we & dio_pad_sleep_regwen_47_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_47_gated_we), + .wd (dio_pad_sleep_mode_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[47].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_47_qs) + ); + + + // Subregister 48 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_48]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_48_gated_we; + assign dio_pad_sleep_mode_48_gated_we = dio_pad_sleep_mode_48_we & dio_pad_sleep_regwen_48_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_48_gated_we), + .wd (dio_pad_sleep_mode_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[48].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_48_qs) + ); + + + // Subregister 49 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_49]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_49_gated_we; + assign dio_pad_sleep_mode_49_gated_we = dio_pad_sleep_mode_49_we & dio_pad_sleep_regwen_49_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_49_gated_we), + .wd (dio_pad_sleep_mode_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[49].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_49_qs) + ); + + + // Subregister 50 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_50]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_50_gated_we; + assign dio_pad_sleep_mode_50_gated_we = dio_pad_sleep_mode_50_we & dio_pad_sleep_regwen_50_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_50_gated_we), + .wd (dio_pad_sleep_mode_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[50].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_50_qs) + ); + + + // Subregister 51 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_51]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_51_gated_we; + assign dio_pad_sleep_mode_51_gated_we = dio_pad_sleep_mode_51_we & dio_pad_sleep_regwen_51_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_51_gated_we), + .wd (dio_pad_sleep_mode_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[51].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_51_qs) + ); + + + // Subregister 52 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_52]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_52_gated_we; + assign dio_pad_sleep_mode_52_gated_we = dio_pad_sleep_mode_52_we & dio_pad_sleep_regwen_52_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_52_gated_we), + .wd (dio_pad_sleep_mode_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[52].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_52_qs) + ); + + + // Subregister 53 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_53]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_53_gated_we; + assign dio_pad_sleep_mode_53_gated_we = dio_pad_sleep_mode_53_we & dio_pad_sleep_regwen_53_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_53_gated_we), + .wd (dio_pad_sleep_mode_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[53].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_53_qs) + ); + + + // Subregister 54 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_54]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_54_gated_we; + assign dio_pad_sleep_mode_54_gated_we = dio_pad_sleep_mode_54_we & dio_pad_sleep_regwen_54_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_54_gated_we), + .wd (dio_pad_sleep_mode_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[54].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_54_qs) + ); + + + // Subregister 55 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_55]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_55_gated_we; + assign dio_pad_sleep_mode_55_gated_we = dio_pad_sleep_mode_55_we & dio_pad_sleep_regwen_55_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_55_gated_we), + .wd (dio_pad_sleep_mode_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[55].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_55_qs) + ); + + + // Subregister 56 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_56]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_56_gated_we; + assign dio_pad_sleep_mode_56_gated_we = dio_pad_sleep_mode_56_we & dio_pad_sleep_regwen_56_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_56_gated_we), + .wd (dio_pad_sleep_mode_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[56].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_56_qs) + ); + + + // Subregister 57 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_57]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_57_gated_we; + assign dio_pad_sleep_mode_57_gated_we = dio_pad_sleep_mode_57_we & dio_pad_sleep_regwen_57_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_57_gated_we), + .wd (dio_pad_sleep_mode_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[57].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_57_qs) + ); + + + // Subregister 58 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_58]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_58_gated_we; + assign dio_pad_sleep_mode_58_gated_we = dio_pad_sleep_mode_58_we & dio_pad_sleep_regwen_58_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_58_gated_we), + .wd (dio_pad_sleep_mode_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[58].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_58_qs) + ); + + + // Subregister 59 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_59]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_59_gated_we; + assign dio_pad_sleep_mode_59_gated_we = dio_pad_sleep_mode_59_we & dio_pad_sleep_regwen_59_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_59_gated_we), + .wd (dio_pad_sleep_mode_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[59].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_59_qs) + ); + + + // Subregister 60 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_60]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_60_gated_we; + assign dio_pad_sleep_mode_60_gated_we = dio_pad_sleep_mode_60_we & dio_pad_sleep_regwen_60_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_60_gated_we), + .wd (dio_pad_sleep_mode_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[60].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_60_qs) + ); + + + // Subregister 61 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_61]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_61_gated_we; + assign dio_pad_sleep_mode_61_gated_we = dio_pad_sleep_mode_61_we & dio_pad_sleep_regwen_61_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_61_gated_we), + .wd (dio_pad_sleep_mode_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[61].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_61_qs) + ); + + + // Subregister 62 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_62]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_62_gated_we; + assign dio_pad_sleep_mode_62_gated_we = dio_pad_sleep_mode_62_we & dio_pad_sleep_regwen_62_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_62_gated_we), + .wd (dio_pad_sleep_mode_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[62].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_62_qs) + ); + + + // Subregister 63 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_63]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_63_gated_we; + assign dio_pad_sleep_mode_63_gated_we = dio_pad_sleep_mode_63_we & dio_pad_sleep_regwen_63_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_63_gated_we), + .wd (dio_pad_sleep_mode_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[63].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_63_qs) + ); + + + // Subregister 64 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_64]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_64_gated_we; + assign dio_pad_sleep_mode_64_gated_we = dio_pad_sleep_mode_64_we & dio_pad_sleep_regwen_64_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_64_gated_we), + .wd (dio_pad_sleep_mode_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[64].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_64_qs) + ); + + + // Subregister 65 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_65]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_65_gated_we; + assign dio_pad_sleep_mode_65_gated_we = dio_pad_sleep_mode_65_we & dio_pad_sleep_regwen_65_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_65_gated_we), + .wd (dio_pad_sleep_mode_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[65].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_65_qs) + ); + + + // Subregister 66 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_66]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_66_gated_we; + assign dio_pad_sleep_mode_66_gated_we = dio_pad_sleep_mode_66_we & dio_pad_sleep_regwen_66_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_66_gated_we), + .wd (dio_pad_sleep_mode_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[66].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_66_qs) + ); + + + // Subregister 67 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_67]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_67_gated_we; + assign dio_pad_sleep_mode_67_gated_we = dio_pad_sleep_mode_67_we & dio_pad_sleep_regwen_67_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_67_gated_we), + .wd (dio_pad_sleep_mode_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[67].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_67_qs) + ); + + + // Subregister 68 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_68]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_68_gated_we; + assign dio_pad_sleep_mode_68_gated_we = dio_pad_sleep_mode_68_we & dio_pad_sleep_regwen_68_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_68_gated_we), + .wd (dio_pad_sleep_mode_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[68].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_68_qs) + ); + + + // Subregister 69 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_69]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_69_gated_we; + assign dio_pad_sleep_mode_69_gated_we = dio_pad_sleep_mode_69_we & dio_pad_sleep_regwen_69_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_69_gated_we), + .wd (dio_pad_sleep_mode_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[69].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_69_qs) + ); + + + // Subregister 70 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_70]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_70_gated_we; + assign dio_pad_sleep_mode_70_gated_we = dio_pad_sleep_mode_70_we & dio_pad_sleep_regwen_70_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_70_gated_we), + .wd (dio_pad_sleep_mode_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[70].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_70_qs) + ); + + + // Subregister 71 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_71]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_71_gated_we; + assign dio_pad_sleep_mode_71_gated_we = dio_pad_sleep_mode_71_we & dio_pad_sleep_regwen_71_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_71_gated_we), + .wd (dio_pad_sleep_mode_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[71].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_71_qs) + ); + + + // Subregister 72 of Multireg dio_pad_sleep_mode + // R[dio_pad_sleep_mode_72]: V(False) + // Create REGWEN-gated WE signal + logic dio_pad_sleep_mode_72_gated_we; + assign dio_pad_sleep_mode_72_gated_we = dio_pad_sleep_mode_72_we & dio_pad_sleep_regwen_72_qs; + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h2), + .Mubi (1'b0) + ) u_dio_pad_sleep_mode_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (dio_pad_sleep_mode_72_gated_we), + .wd (dio_pad_sleep_mode_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.dio_pad_sleep_mode[72].q), + .ds (), + + // to register interface (read) + .qs (dio_pad_sleep_mode_72_qs) + ); + + + // Subregister 0 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_0_we), + .wd (wkup_detector_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_0_qs) + ); + + + // Subregister 1 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_1_we), + .wd (wkup_detector_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_1_qs) + ); + + + // Subregister 2 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_2_we), + .wd (wkup_detector_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_2_qs) + ); + + + // Subregister 3 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_3]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_3_we), + .wd (wkup_detector_regwen_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_3_qs) + ); + + + // Subregister 4 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_4]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_4_we), + .wd (wkup_detector_regwen_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_4_qs) + ); + + + // Subregister 5 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_5]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_5_we), + .wd (wkup_detector_regwen_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_5_qs) + ); + + + // Subregister 6 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_6]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_6_we), + .wd (wkup_detector_regwen_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_6_qs) + ); + + + // Subregister 7 of Multireg wkup_detector_regwen + // R[wkup_detector_regwen_7]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wkup_detector_regwen_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_regwen_7_we), + .wd (wkup_detector_regwen_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wkup_detector_regwen_7_qs) + ); + + + // Subregister 0 of Multireg wkup_detector_en + // R[wkup_detector_en_0]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_0_gated_we; + assign aon_wkup_detector_en_0_gated_we = + aon_wkup_detector_en_0_we & aon_wkup_detector_en_0_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_0_gated_we), + .wd (aon_wkup_detector_en_0_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[0].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_0_qs_int) + ); + + + // Subregister 1 of Multireg wkup_detector_en + // R[wkup_detector_en_1]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_1_gated_we; + assign aon_wkup_detector_en_1_gated_we = + aon_wkup_detector_en_1_we & aon_wkup_detector_en_1_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_1_gated_we), + .wd (aon_wkup_detector_en_1_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[1].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_1_qs_int) + ); + + + // Subregister 2 of Multireg wkup_detector_en + // R[wkup_detector_en_2]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_2_gated_we; + assign aon_wkup_detector_en_2_gated_we = + aon_wkup_detector_en_2_we & aon_wkup_detector_en_2_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_2_gated_we), + .wd (aon_wkup_detector_en_2_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[2].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_2_qs_int) + ); + + + // Subregister 3 of Multireg wkup_detector_en + // R[wkup_detector_en_3]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_3_gated_we; + assign aon_wkup_detector_en_3_gated_we = + aon_wkup_detector_en_3_we & aon_wkup_detector_en_3_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_3_gated_we), + .wd (aon_wkup_detector_en_3_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[3].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_3_qs_int) + ); + + + // Subregister 4 of Multireg wkup_detector_en + // R[wkup_detector_en_4]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_4_gated_we; + assign aon_wkup_detector_en_4_gated_we = + aon_wkup_detector_en_4_we & aon_wkup_detector_en_4_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_4_gated_we), + .wd (aon_wkup_detector_en_4_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[4].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_4_qs_int) + ); + + + // Subregister 5 of Multireg wkup_detector_en + // R[wkup_detector_en_5]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_5_gated_we; + assign aon_wkup_detector_en_5_gated_we = + aon_wkup_detector_en_5_we & aon_wkup_detector_en_5_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_5_gated_we), + .wd (aon_wkup_detector_en_5_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[5].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_5_qs_int) + ); + + + // Subregister 6 of Multireg wkup_detector_en + // R[wkup_detector_en_6]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_6_gated_we; + assign aon_wkup_detector_en_6_gated_we = + aon_wkup_detector_en_6_we & aon_wkup_detector_en_6_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_6_gated_we), + .wd (aon_wkup_detector_en_6_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[6].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_6_qs_int) + ); + + + // Subregister 7 of Multireg wkup_detector_en + // R[wkup_detector_en_7]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_en_7_gated_we; + assign aon_wkup_detector_en_7_gated_we = + aon_wkup_detector_en_7_we & aon_wkup_detector_en_7_regwen; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_en_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_en_7_gated_we), + .wd (aon_wkup_detector_en_7_wdata[0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_en[7].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_en_7_qs_int) + ); + + + // Subregister 0 of Multireg wkup_detector + // R[wkup_detector_0]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_0_gated_we; + assign aon_wkup_detector_0_gated_we = aon_wkup_detector_0_we & aon_wkup_detector_0_regwen; + // F[mode_0]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_0_mode_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_0_gated_we), + .wd (aon_wkup_detector_0_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[0].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_0_mode_0_qs_int) + ); + + // F[filter_0]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_0_filter_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_0_gated_we), + .wd (aon_wkup_detector_0_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[0].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_0_filter_0_qs_int) + ); + + // F[miodio_0]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_0_miodio_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_0_gated_we), + .wd (aon_wkup_detector_0_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[0].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_0_miodio_0_qs_int) + ); + + + // Subregister 1 of Multireg wkup_detector + // R[wkup_detector_1]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_1_gated_we; + assign aon_wkup_detector_1_gated_we = aon_wkup_detector_1_we & aon_wkup_detector_1_regwen; + // F[mode_1]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_1_mode_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_1_gated_we), + .wd (aon_wkup_detector_1_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[1].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_1_mode_1_qs_int) + ); + + // F[filter_1]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_1_filter_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_1_gated_we), + .wd (aon_wkup_detector_1_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[1].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_1_filter_1_qs_int) + ); + + // F[miodio_1]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_1_miodio_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_1_gated_we), + .wd (aon_wkup_detector_1_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[1].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_1_miodio_1_qs_int) + ); + + + // Subregister 2 of Multireg wkup_detector + // R[wkup_detector_2]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_2_gated_we; + assign aon_wkup_detector_2_gated_we = aon_wkup_detector_2_we & aon_wkup_detector_2_regwen; + // F[mode_2]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_2_mode_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_2_gated_we), + .wd (aon_wkup_detector_2_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[2].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_2_mode_2_qs_int) + ); + + // F[filter_2]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_2_filter_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_2_gated_we), + .wd (aon_wkup_detector_2_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[2].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_2_filter_2_qs_int) + ); + + // F[miodio_2]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_2_miodio_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_2_gated_we), + .wd (aon_wkup_detector_2_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[2].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_2_miodio_2_qs_int) + ); + + + // Subregister 3 of Multireg wkup_detector + // R[wkup_detector_3]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_3_gated_we; + assign aon_wkup_detector_3_gated_we = aon_wkup_detector_3_we & aon_wkup_detector_3_regwen; + // F[mode_3]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_3_mode_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_3_gated_we), + .wd (aon_wkup_detector_3_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[3].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_3_mode_3_qs_int) + ); + + // F[filter_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_3_filter_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_3_gated_we), + .wd (aon_wkup_detector_3_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[3].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_3_filter_3_qs_int) + ); + + // F[miodio_3]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_3_miodio_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_3_gated_we), + .wd (aon_wkup_detector_3_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[3].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_3_miodio_3_qs_int) + ); + + + // Subregister 4 of Multireg wkup_detector + // R[wkup_detector_4]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_4_gated_we; + assign aon_wkup_detector_4_gated_we = aon_wkup_detector_4_we & aon_wkup_detector_4_regwen; + // F[mode_4]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_4_mode_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_4_gated_we), + .wd (aon_wkup_detector_4_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[4].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_4_mode_4_qs_int) + ); + + // F[filter_4]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_4_filter_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_4_gated_we), + .wd (aon_wkup_detector_4_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[4].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_4_filter_4_qs_int) + ); + + // F[miodio_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_4_miodio_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_4_gated_we), + .wd (aon_wkup_detector_4_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[4].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_4_miodio_4_qs_int) + ); + + + // Subregister 5 of Multireg wkup_detector + // R[wkup_detector_5]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_5_gated_we; + assign aon_wkup_detector_5_gated_we = aon_wkup_detector_5_we & aon_wkup_detector_5_regwen; + // F[mode_5]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_5_mode_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_5_gated_we), + .wd (aon_wkup_detector_5_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[5].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_5_mode_5_qs_int) + ); + + // F[filter_5]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_5_filter_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_5_gated_we), + .wd (aon_wkup_detector_5_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[5].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_5_filter_5_qs_int) + ); + + // F[miodio_5]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_5_miodio_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_5_gated_we), + .wd (aon_wkup_detector_5_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[5].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_5_miodio_5_qs_int) + ); + + + // Subregister 6 of Multireg wkup_detector + // R[wkup_detector_6]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_6_gated_we; + assign aon_wkup_detector_6_gated_we = aon_wkup_detector_6_we & aon_wkup_detector_6_regwen; + // F[mode_6]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_6_mode_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_6_gated_we), + .wd (aon_wkup_detector_6_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[6].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_6_mode_6_qs_int) + ); + + // F[filter_6]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_6_filter_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_6_gated_we), + .wd (aon_wkup_detector_6_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[6].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_6_filter_6_qs_int) + ); + + // F[miodio_6]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_6_miodio_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_6_gated_we), + .wd (aon_wkup_detector_6_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[6].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_6_miodio_6_qs_int) + ); + + + // Subregister 7 of Multireg wkup_detector + // R[wkup_detector_7]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_7_gated_we; + assign aon_wkup_detector_7_gated_we = aon_wkup_detector_7_we & aon_wkup_detector_7_regwen; + // F[mode_7]: 2:0 + prim_subreg #( + .DW (3), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (3'h0), + .Mubi (1'b0) + ) u_wkup_detector_7_mode_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_7_gated_we), + .wd (aon_wkup_detector_7_wdata[2:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[7].mode.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_7_mode_7_qs_int) + ); + + // F[filter_7]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_7_filter_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_7_gated_we), + .wd (aon_wkup_detector_7_wdata[3]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[7].filter.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_7_filter_7_qs_int) + ); + + // F[miodio_7]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_detector_7_miodio_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_7_gated_we), + .wd (aon_wkup_detector_7_wdata[4]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector[7].miodio.q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_7_miodio_7_qs_int) + ); + + + // Subregister 0 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_0]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_0_gated_we; + assign aon_wkup_detector_cnt_th_0_gated_we = + aon_wkup_detector_cnt_th_0_we & aon_wkup_detector_cnt_th_0_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_0_gated_we), + .wd (aon_wkup_detector_cnt_th_0_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[0].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_0_qs_int) + ); + + + // Subregister 1 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_1]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_1_gated_we; + assign aon_wkup_detector_cnt_th_1_gated_we = + aon_wkup_detector_cnt_th_1_we & aon_wkup_detector_cnt_th_1_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_1_gated_we), + .wd (aon_wkup_detector_cnt_th_1_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[1].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_1_qs_int) + ); + + + // Subregister 2 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_2]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_2_gated_we; + assign aon_wkup_detector_cnt_th_2_gated_we = + aon_wkup_detector_cnt_th_2_we & aon_wkup_detector_cnt_th_2_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_2_gated_we), + .wd (aon_wkup_detector_cnt_th_2_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[2].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_2_qs_int) + ); + + + // Subregister 3 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_3]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_3_gated_we; + assign aon_wkup_detector_cnt_th_3_gated_we = + aon_wkup_detector_cnt_th_3_we & aon_wkup_detector_cnt_th_3_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_3_gated_we), + .wd (aon_wkup_detector_cnt_th_3_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[3].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_3_qs_int) + ); + + + // Subregister 4 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_4]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_4_gated_we; + assign aon_wkup_detector_cnt_th_4_gated_we = + aon_wkup_detector_cnt_th_4_we & aon_wkup_detector_cnt_th_4_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_4_gated_we), + .wd (aon_wkup_detector_cnt_th_4_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[4].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_4_qs_int) + ); + + + // Subregister 5 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_5]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_5_gated_we; + assign aon_wkup_detector_cnt_th_5_gated_we = + aon_wkup_detector_cnt_th_5_we & aon_wkup_detector_cnt_th_5_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_5_gated_we), + .wd (aon_wkup_detector_cnt_th_5_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[5].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_5_qs_int) + ); + + + // Subregister 6 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_6]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_6_gated_we; + assign aon_wkup_detector_cnt_th_6_gated_we = + aon_wkup_detector_cnt_th_6_we & aon_wkup_detector_cnt_th_6_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_6_gated_we), + .wd (aon_wkup_detector_cnt_th_6_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[6].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_6_qs_int) + ); + + + // Subregister 7 of Multireg wkup_detector_cnt_th + // R[wkup_detector_cnt_th_7]: V(False) + // Create REGWEN-gated WE signal + logic aon_wkup_detector_cnt_th_7_gated_we; + assign aon_wkup_detector_cnt_th_7_gated_we = + aon_wkup_detector_cnt_th_7_we & aon_wkup_detector_cnt_th_7_regwen; + prim_subreg #( + .DW (8), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (8'h0), + .Mubi (1'b0) + ) u_wkup_detector_cnt_th_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_detector_cnt_th_7_gated_we), + .wd (aon_wkup_detector_cnt_th_7_wdata[7:0]), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_cnt_th[7].q), + .ds (), + + // to register interface (read) + .qs (aon_wkup_detector_cnt_th_7_qs_int) + ); + + + // Subregister 0 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_0]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_0_gated_we; + assign wkup_detector_padsel_0_gated_we = wkup_detector_padsel_0_we & wkup_detector_regwen_0_qs; + prim_subreg #( + .DW (7), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_0_gated_we), + .wd (wkup_detector_padsel_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[0].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_0_qs) + ); + + + // Subregister 1 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_1]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_1_gated_we; + assign wkup_detector_padsel_1_gated_we = wkup_detector_padsel_1_we & wkup_detector_regwen_1_qs; + prim_subreg #( + .DW (7), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_1_gated_we), + .wd (wkup_detector_padsel_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[1].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_1_qs) + ); + + + // Subregister 2 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_2]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_2_gated_we; + assign wkup_detector_padsel_2_gated_we = wkup_detector_padsel_2_we & wkup_detector_regwen_2_qs; + prim_subreg #( + .DW (7), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_2_gated_we), + .wd (wkup_detector_padsel_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[2].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_2_qs) + ); + + + // Subregister 3 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_3]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_3_gated_we; + assign wkup_detector_padsel_3_gated_we = wkup_detector_padsel_3_we & wkup_detector_regwen_3_qs; + prim_subreg #( + .DW (7), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_3_gated_we), + .wd (wkup_detector_padsel_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[3].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_3_qs) + ); + + + // Subregister 4 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_4]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_4_gated_we; + assign wkup_detector_padsel_4_gated_we = wkup_detector_padsel_4_we & wkup_detector_regwen_4_qs; + prim_subreg #( + .DW (7), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_4_gated_we), + .wd (wkup_detector_padsel_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[4].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_4_qs) + ); + + + // Subregister 5 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_5]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_5_gated_we; + assign wkup_detector_padsel_5_gated_we = wkup_detector_padsel_5_we & wkup_detector_regwen_5_qs; + prim_subreg #( + .DW (7), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_5_gated_we), + .wd (wkup_detector_padsel_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[5].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_5_qs) + ); + + + // Subregister 6 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_6]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_6_gated_we; + assign wkup_detector_padsel_6_gated_we = wkup_detector_padsel_6_we & wkup_detector_regwen_6_qs; + prim_subreg #( + .DW (7), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_6_gated_we), + .wd (wkup_detector_padsel_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[6].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_6_qs) + ); + + + // Subregister 7 of Multireg wkup_detector_padsel + // R[wkup_detector_padsel_7]: V(False) + // Create REGWEN-gated WE signal + logic wkup_detector_padsel_7_gated_we; + assign wkup_detector_padsel_7_gated_we = wkup_detector_padsel_7_we & wkup_detector_regwen_7_qs; + prim_subreg #( + .DW (7), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (7'h0), + .Mubi (1'b0) + ) u_wkup_detector_padsel_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wkup_detector_padsel_7_gated_we), + .wd (wkup_detector_padsel_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wkup_detector_padsel[7].q), + .ds (), + + // to register interface (read) + .qs (wkup_detector_padsel_7_qs) + ); + + + // Subregister 0 of Multireg wkup_cause + // R[wkup_cause]: V(False) + logic [7:0] wkup_cause_flds_we; + assign aon_wkup_cause_qe = |wkup_cause_flds_we; + // F[cause_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_0 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[0]), + + // from internal hardware + .de (hw2reg.wkup_cause[0].de), + .d (hw2reg.wkup_cause[0].d), + + // to internal hardware + .qe (wkup_cause_flds_we[0]), + .q (reg2hw.wkup_cause[0].q), + .ds (aon_wkup_cause_cause_0_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_0_qs_int) + ); + + // F[cause_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_1 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[1]), + + // from internal hardware + .de (hw2reg.wkup_cause[1].de), + .d (hw2reg.wkup_cause[1].d), + + // to internal hardware + .qe (wkup_cause_flds_we[1]), + .q (reg2hw.wkup_cause[1].q), + .ds (aon_wkup_cause_cause_1_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_1_qs_int) + ); + + // F[cause_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_2 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[2]), + + // from internal hardware + .de (hw2reg.wkup_cause[2].de), + .d (hw2reg.wkup_cause[2].d), + + // to internal hardware + .qe (wkup_cause_flds_we[2]), + .q (reg2hw.wkup_cause[2].q), + .ds (aon_wkup_cause_cause_2_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_2_qs_int) + ); + + // F[cause_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_3 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[3]), + + // from internal hardware + .de (hw2reg.wkup_cause[3].de), + .d (hw2reg.wkup_cause[3].d), + + // to internal hardware + .qe (wkup_cause_flds_we[3]), + .q (reg2hw.wkup_cause[3].q), + .ds (aon_wkup_cause_cause_3_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_3_qs_int) + ); + + // F[cause_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_4 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[4]), + + // from internal hardware + .de (hw2reg.wkup_cause[4].de), + .d (hw2reg.wkup_cause[4].d), + + // to internal hardware + .qe (wkup_cause_flds_we[4]), + .q (reg2hw.wkup_cause[4].q), + .ds (aon_wkup_cause_cause_4_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_4_qs_int) + ); + + // F[cause_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_5 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[5]), + + // from internal hardware + .de (hw2reg.wkup_cause[5].de), + .d (hw2reg.wkup_cause[5].d), + + // to internal hardware + .qe (wkup_cause_flds_we[5]), + .q (reg2hw.wkup_cause[5].q), + .ds (aon_wkup_cause_cause_5_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_5_qs_int) + ); + + // F[cause_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_6 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[6]), + + // from internal hardware + .de (hw2reg.wkup_cause[6].de), + .d (hw2reg.wkup_cause[6].d), + + // to internal hardware + .qe (wkup_cause_flds_we[6]), + .q (reg2hw.wkup_cause[6].q), + .ds (aon_wkup_cause_cause_6_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_6_qs_int) + ); + + // F[cause_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wkup_cause_cause_7 ( + .clk_i (clk_aon_i), + .rst_ni (rst_aon_ni), + + // from register interface + .we (aon_wkup_cause_we), + .wd (aon_wkup_cause_wdata[7]), + + // from internal hardware + .de (hw2reg.wkup_cause[7].de), + .d (hw2reg.wkup_cause[7].d), + + // to internal hardware + .qe (wkup_cause_flds_we[7]), + .q (reg2hw.wkup_cause[7].q), + .ds (aon_wkup_cause_cause_7_ds_int), + + // to register interface (read) + .qs (aon_wkup_cause_cause_7_qs_int) + ); + + + + logic [502:0] addr_hit; + always_comb begin + addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET); + addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET); + addr_hit[ 2] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_1_OFFSET); + addr_hit[ 3] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_2_OFFSET); + addr_hit[ 4] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_3_OFFSET); + addr_hit[ 5] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); + addr_hit[ 6] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); + addr_hit[ 7] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); + addr_hit[ 8] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); + addr_hit[ 9] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); + addr_hit[ 10] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); + addr_hit[ 11] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); + addr_hit[ 12] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); + addr_hit[ 13] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); + addr_hit[ 14] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); + addr_hit[ 15] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); + addr_hit[ 16] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); + addr_hit[ 17] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); + addr_hit[ 18] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); + addr_hit[ 19] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); + addr_hit[ 20] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); + addr_hit[ 21] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); + addr_hit[ 22] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); + addr_hit[ 23] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); + addr_hit[ 24] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); + addr_hit[ 25] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); + addr_hit[ 26] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); + addr_hit[ 27] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); + addr_hit[ 28] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); + addr_hit[ 29] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); + addr_hit[ 30] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); + addr_hit[ 31] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); + addr_hit[ 32] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); + addr_hit[ 33] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[ 34] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[ 35] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[ 36] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[ 37] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[ 38] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[ 39] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[ 40] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[ 41] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[ 42] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[ 43] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[ 44] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[ 45] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); + addr_hit[ 46] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); + addr_hit[ 47] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); + addr_hit[ 48] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); + addr_hit[ 49] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); + addr_hit[ 50] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); + addr_hit[ 51] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); + addr_hit[ 52] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); + addr_hit[ 53] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); + addr_hit[ 54] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); + addr_hit[ 55] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); + addr_hit[ 56] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); + addr_hit[ 57] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[ 58] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[ 59] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[ 60] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[ 61] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[ 62] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[ 63] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[ 64] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[ 65] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[ 66] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[ 67] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[ 68] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[ 69] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[ 70] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[ 71] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[ 72] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[ 73] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[ 74] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[ 75] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[ 76] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[ 77] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[ 78] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[ 79] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[ 80] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[ 81] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[ 82] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[ 83] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[ 84] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[ 85] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[ 86] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[ 87] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[ 88] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[ 89] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_32_OFFSET); + addr_hit[ 90] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_33_OFFSET); + addr_hit[ 91] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_34_OFFSET); + addr_hit[ 92] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_35_OFFSET); + addr_hit[ 93] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_36_OFFSET); + addr_hit[ 94] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_37_OFFSET); + addr_hit[ 95] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_38_OFFSET); + addr_hit[ 96] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_39_OFFSET); + addr_hit[ 97] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_40_OFFSET); + addr_hit[ 98] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_41_OFFSET); + addr_hit[ 99] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_42_OFFSET); + addr_hit[100] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_43_OFFSET); + addr_hit[101] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_44_OFFSET); + addr_hit[102] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_45_OFFSET); + addr_hit[103] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_46_OFFSET); + addr_hit[104] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_47_OFFSET); + addr_hit[105] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_48_OFFSET); + addr_hit[106] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_49_OFFSET); + addr_hit[107] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_50_OFFSET); + addr_hit[108] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_51_OFFSET); + addr_hit[109] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_52_OFFSET); + addr_hit[110] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_53_OFFSET); + addr_hit[111] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_54_OFFSET); + addr_hit[112] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_55_OFFSET); + addr_hit[113] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_56_OFFSET); + addr_hit[114] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_57_OFFSET); + addr_hit[115] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_58_OFFSET); + addr_hit[116] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_59_OFFSET); + addr_hit[117] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_60_OFFSET); + addr_hit[118] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_61_OFFSET); + addr_hit[119] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_62_OFFSET); + addr_hit[120] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_63_OFFSET); + addr_hit[121] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_64_OFFSET); + addr_hit[122] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_65_OFFSET); + addr_hit[123] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_66_OFFSET); + addr_hit[124] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_67_OFFSET); + addr_hit[125] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_68_OFFSET); + addr_hit[126] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_69_OFFSET); + addr_hit[127] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_70_OFFSET); + addr_hit[128] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_71_OFFSET); + addr_hit[129] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_72_OFFSET); + addr_hit[130] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); + addr_hit[131] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); + addr_hit[132] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); + addr_hit[133] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); + addr_hit[134] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); + addr_hit[135] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); + addr_hit[136] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); + addr_hit[137] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); + addr_hit[138] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); + addr_hit[139] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); + addr_hit[140] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); + addr_hit[141] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); + addr_hit[142] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); + addr_hit[143] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); + addr_hit[144] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET); + addr_hit[145] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET); + addr_hit[146] = (reg_addr == PINMUX_DIO_PAD_ATTR_16_OFFSET); + addr_hit[147] = (reg_addr == PINMUX_DIO_PAD_ATTR_17_OFFSET); + addr_hit[148] = (reg_addr == PINMUX_DIO_PAD_ATTR_18_OFFSET); + addr_hit[149] = (reg_addr == PINMUX_DIO_PAD_ATTR_19_OFFSET); + addr_hit[150] = (reg_addr == PINMUX_DIO_PAD_ATTR_20_OFFSET); + addr_hit[151] = (reg_addr == PINMUX_DIO_PAD_ATTR_21_OFFSET); + addr_hit[152] = (reg_addr == PINMUX_DIO_PAD_ATTR_22_OFFSET); + addr_hit[153] = (reg_addr == PINMUX_DIO_PAD_ATTR_23_OFFSET); + addr_hit[154] = (reg_addr == PINMUX_DIO_PAD_ATTR_24_OFFSET); + addr_hit[155] = (reg_addr == PINMUX_DIO_PAD_ATTR_25_OFFSET); + addr_hit[156] = (reg_addr == PINMUX_DIO_PAD_ATTR_26_OFFSET); + addr_hit[157] = (reg_addr == PINMUX_DIO_PAD_ATTR_27_OFFSET); + addr_hit[158] = (reg_addr == PINMUX_DIO_PAD_ATTR_28_OFFSET); + addr_hit[159] = (reg_addr == PINMUX_DIO_PAD_ATTR_29_OFFSET); + addr_hit[160] = (reg_addr == PINMUX_DIO_PAD_ATTR_30_OFFSET); + addr_hit[161] = (reg_addr == PINMUX_DIO_PAD_ATTR_31_OFFSET); + addr_hit[162] = (reg_addr == PINMUX_DIO_PAD_ATTR_32_OFFSET); + addr_hit[163] = (reg_addr == PINMUX_DIO_PAD_ATTR_33_OFFSET); + addr_hit[164] = (reg_addr == PINMUX_DIO_PAD_ATTR_34_OFFSET); + addr_hit[165] = (reg_addr == PINMUX_DIO_PAD_ATTR_35_OFFSET); + addr_hit[166] = (reg_addr == PINMUX_DIO_PAD_ATTR_36_OFFSET); + addr_hit[167] = (reg_addr == PINMUX_DIO_PAD_ATTR_37_OFFSET); + addr_hit[168] = (reg_addr == PINMUX_DIO_PAD_ATTR_38_OFFSET); + addr_hit[169] = (reg_addr == PINMUX_DIO_PAD_ATTR_39_OFFSET); + addr_hit[170] = (reg_addr == PINMUX_DIO_PAD_ATTR_40_OFFSET); + addr_hit[171] = (reg_addr == PINMUX_DIO_PAD_ATTR_41_OFFSET); + addr_hit[172] = (reg_addr == PINMUX_DIO_PAD_ATTR_42_OFFSET); + addr_hit[173] = (reg_addr == PINMUX_DIO_PAD_ATTR_43_OFFSET); + addr_hit[174] = (reg_addr == PINMUX_DIO_PAD_ATTR_44_OFFSET); + addr_hit[175] = (reg_addr == PINMUX_DIO_PAD_ATTR_45_OFFSET); + addr_hit[176] = (reg_addr == PINMUX_DIO_PAD_ATTR_46_OFFSET); + addr_hit[177] = (reg_addr == PINMUX_DIO_PAD_ATTR_47_OFFSET); + addr_hit[178] = (reg_addr == PINMUX_DIO_PAD_ATTR_48_OFFSET); + addr_hit[179] = (reg_addr == PINMUX_DIO_PAD_ATTR_49_OFFSET); + addr_hit[180] = (reg_addr == PINMUX_DIO_PAD_ATTR_50_OFFSET); + addr_hit[181] = (reg_addr == PINMUX_DIO_PAD_ATTR_51_OFFSET); + addr_hit[182] = (reg_addr == PINMUX_DIO_PAD_ATTR_52_OFFSET); + addr_hit[183] = (reg_addr == PINMUX_DIO_PAD_ATTR_53_OFFSET); + addr_hit[184] = (reg_addr == PINMUX_DIO_PAD_ATTR_54_OFFSET); + addr_hit[185] = (reg_addr == PINMUX_DIO_PAD_ATTR_55_OFFSET); + addr_hit[186] = (reg_addr == PINMUX_DIO_PAD_ATTR_56_OFFSET); + addr_hit[187] = (reg_addr == PINMUX_DIO_PAD_ATTR_57_OFFSET); + addr_hit[188] = (reg_addr == PINMUX_DIO_PAD_ATTR_58_OFFSET); + addr_hit[189] = (reg_addr == PINMUX_DIO_PAD_ATTR_59_OFFSET); + addr_hit[190] = (reg_addr == PINMUX_DIO_PAD_ATTR_60_OFFSET); + addr_hit[191] = (reg_addr == PINMUX_DIO_PAD_ATTR_61_OFFSET); + addr_hit[192] = (reg_addr == PINMUX_DIO_PAD_ATTR_62_OFFSET); + addr_hit[193] = (reg_addr == PINMUX_DIO_PAD_ATTR_63_OFFSET); + addr_hit[194] = (reg_addr == PINMUX_DIO_PAD_ATTR_64_OFFSET); + addr_hit[195] = (reg_addr == PINMUX_DIO_PAD_ATTR_65_OFFSET); + addr_hit[196] = (reg_addr == PINMUX_DIO_PAD_ATTR_66_OFFSET); + addr_hit[197] = (reg_addr == PINMUX_DIO_PAD_ATTR_67_OFFSET); + addr_hit[198] = (reg_addr == PINMUX_DIO_PAD_ATTR_68_OFFSET); + addr_hit[199] = (reg_addr == PINMUX_DIO_PAD_ATTR_69_OFFSET); + addr_hit[200] = (reg_addr == PINMUX_DIO_PAD_ATTR_70_OFFSET); + addr_hit[201] = (reg_addr == PINMUX_DIO_PAD_ATTR_71_OFFSET); + addr_hit[202] = (reg_addr == PINMUX_DIO_PAD_ATTR_72_OFFSET); + addr_hit[203] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[204] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[205] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[206] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[207] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[208] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[240] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_0_OFFSET); + addr_hit[241] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_1_OFFSET); + addr_hit[242] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_2_OFFSET); + addr_hit[243] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[244] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[245] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[246] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[247] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[248] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[249] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[250] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[251] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[252] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[253] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[254] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[255] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[256] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[257] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[258] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[259] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[260] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[261] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[262] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[263] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[264] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[265] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[266] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[267] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[268] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[269] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[270] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[271] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[272] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[273] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[274] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[275] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_32_OFFSET); + addr_hit[276] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_33_OFFSET); + addr_hit[277] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_34_OFFSET); + addr_hit[278] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_35_OFFSET); + addr_hit[279] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_36_OFFSET); + addr_hit[280] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_37_OFFSET); + addr_hit[281] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_38_OFFSET); + addr_hit[282] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_39_OFFSET); + addr_hit[283] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_40_OFFSET); + addr_hit[284] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_41_OFFSET); + addr_hit[285] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_42_OFFSET); + addr_hit[286] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_43_OFFSET); + addr_hit[287] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_44_OFFSET); + addr_hit[288] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_45_OFFSET); + addr_hit[289] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_46_OFFSET); + addr_hit[290] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_47_OFFSET); + addr_hit[291] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_48_OFFSET); + addr_hit[292] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_49_OFFSET); + addr_hit[293] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_50_OFFSET); + addr_hit[294] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_51_OFFSET); + addr_hit[295] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_52_OFFSET); + addr_hit[296] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_53_OFFSET); + addr_hit[297] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_54_OFFSET); + addr_hit[298] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_55_OFFSET); + addr_hit[299] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_56_OFFSET); + addr_hit[300] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_57_OFFSET); + addr_hit[301] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_58_OFFSET); + addr_hit[302] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_59_OFFSET); + addr_hit[303] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_60_OFFSET); + addr_hit[304] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_61_OFFSET); + addr_hit[305] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_62_OFFSET); + addr_hit[306] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_63_OFFSET); + addr_hit[307] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_64_OFFSET); + addr_hit[308] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_65_OFFSET); + addr_hit[309] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_66_OFFSET); + addr_hit[310] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_67_OFFSET); + addr_hit[311] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_68_OFFSET); + addr_hit[312] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_69_OFFSET); + addr_hit[313] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_70_OFFSET); + addr_hit[314] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_71_OFFSET); + addr_hit[315] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_72_OFFSET); + addr_hit[316] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[317] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[318] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[319] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[320] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[321] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[322] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[323] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[324] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[325] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[326] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[327] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[328] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[329] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[330] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[331] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[332] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[333] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[334] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[335] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[336] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_32_OFFSET); + addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_33_OFFSET); + addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_34_OFFSET); + addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_35_OFFSET); + addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_36_OFFSET); + addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_37_OFFSET); + addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_38_OFFSET); + addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_39_OFFSET); + addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_40_OFFSET); + addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_41_OFFSET); + addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_42_OFFSET); + addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_43_OFFSET); + addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_44_OFFSET); + addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_45_OFFSET); + addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_46_OFFSET); + addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_47_OFFSET); + addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_48_OFFSET); + addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_49_OFFSET); + addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_50_OFFSET); + addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_51_OFFSET); + addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_52_OFFSET); + addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_53_OFFSET); + addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_54_OFFSET); + addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_55_OFFSET); + addr_hit[372] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_56_OFFSET); + addr_hit[373] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_57_OFFSET); + addr_hit[374] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_58_OFFSET); + addr_hit[375] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_59_OFFSET); + addr_hit[376] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_60_OFFSET); + addr_hit[377] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_61_OFFSET); + addr_hit[378] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_62_OFFSET); + addr_hit[379] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_63_OFFSET); + addr_hit[380] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_64_OFFSET); + addr_hit[381] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_65_OFFSET); + addr_hit[382] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_66_OFFSET); + addr_hit[383] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_67_OFFSET); + addr_hit[384] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_68_OFFSET); + addr_hit[385] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_69_OFFSET); + addr_hit[386] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_70_OFFSET); + addr_hit[387] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_71_OFFSET); + addr_hit[388] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_72_OFFSET); + addr_hit[389] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[390] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[391] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[392] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[393] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[394] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[395] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[396] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[397] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[398] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[399] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[400] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[401] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[402] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[403] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[404] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[405] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[406] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[407] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[408] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[409] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[410] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[411] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[412] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[413] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[414] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[415] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[416] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[417] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[418] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[419] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[420] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[421] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_32_OFFSET); + addr_hit[422] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_33_OFFSET); + addr_hit[423] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_34_OFFSET); + addr_hit[424] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_35_OFFSET); + addr_hit[425] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_36_OFFSET); + addr_hit[426] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_37_OFFSET); + addr_hit[427] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_38_OFFSET); + addr_hit[428] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_39_OFFSET); + addr_hit[429] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_40_OFFSET); + addr_hit[430] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_41_OFFSET); + addr_hit[431] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_42_OFFSET); + addr_hit[432] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_43_OFFSET); + addr_hit[433] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_44_OFFSET); + addr_hit[434] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_45_OFFSET); + addr_hit[435] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_46_OFFSET); + addr_hit[436] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_47_OFFSET); + addr_hit[437] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_48_OFFSET); + addr_hit[438] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_49_OFFSET); + addr_hit[439] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_50_OFFSET); + addr_hit[440] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_51_OFFSET); + addr_hit[441] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_52_OFFSET); + addr_hit[442] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_53_OFFSET); + addr_hit[443] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_54_OFFSET); + addr_hit[444] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_55_OFFSET); + addr_hit[445] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_56_OFFSET); + addr_hit[446] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_57_OFFSET); + addr_hit[447] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_58_OFFSET); + addr_hit[448] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_59_OFFSET); + addr_hit[449] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_60_OFFSET); + addr_hit[450] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_61_OFFSET); + addr_hit[451] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_62_OFFSET); + addr_hit[452] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_63_OFFSET); + addr_hit[453] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_64_OFFSET); + addr_hit[454] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_65_OFFSET); + addr_hit[455] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_66_OFFSET); + addr_hit[456] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_67_OFFSET); + addr_hit[457] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_68_OFFSET); + addr_hit[458] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_69_OFFSET); + addr_hit[459] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_70_OFFSET); + addr_hit[460] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_71_OFFSET); + addr_hit[461] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_72_OFFSET); + addr_hit[462] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); + addr_hit[463] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); + addr_hit[464] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); + addr_hit[465] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); + addr_hit[466] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); + addr_hit[467] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); + addr_hit[468] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); + addr_hit[469] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); + addr_hit[470] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); + addr_hit[471] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); + addr_hit[472] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); + addr_hit[473] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); + addr_hit[474] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); + addr_hit[475] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); + addr_hit[476] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); + addr_hit[477] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); + addr_hit[478] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[479] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[480] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[481] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[482] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[483] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[484] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[485] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[486] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[487] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[488] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); + addr_hit[489] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); + addr_hit[490] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); + addr_hit[491] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); + addr_hit[492] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); + addr_hit[493] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); + addr_hit[494] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[495] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[496] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); + addr_hit[497] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); + addr_hit[498] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); + addr_hit[499] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); + addr_hit[500] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); + addr_hit[501] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); + addr_hit[502] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(PINMUX_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(PINMUX_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(PINMUX_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(PINMUX_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(PINMUX_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(PINMUX_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(PINMUX_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(PINMUX_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(PINMUX_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(PINMUX_PERMIT[ 9] & ~reg_be))) | + (addr_hit[ 10] & (|(PINMUX_PERMIT[ 10] & ~reg_be))) | + (addr_hit[ 11] & (|(PINMUX_PERMIT[ 11] & ~reg_be))) | + (addr_hit[ 12] & (|(PINMUX_PERMIT[ 12] & ~reg_be))) | + (addr_hit[ 13] & (|(PINMUX_PERMIT[ 13] & ~reg_be))) | + (addr_hit[ 14] & (|(PINMUX_PERMIT[ 14] & ~reg_be))) | + (addr_hit[ 15] & (|(PINMUX_PERMIT[ 15] & ~reg_be))) | + (addr_hit[ 16] & (|(PINMUX_PERMIT[ 16] & ~reg_be))) | + (addr_hit[ 17] & (|(PINMUX_PERMIT[ 17] & ~reg_be))) | + (addr_hit[ 18] & (|(PINMUX_PERMIT[ 18] & ~reg_be))) | + (addr_hit[ 19] & (|(PINMUX_PERMIT[ 19] & ~reg_be))) | + (addr_hit[ 20] & (|(PINMUX_PERMIT[ 20] & ~reg_be))) | + (addr_hit[ 21] & (|(PINMUX_PERMIT[ 21] & ~reg_be))) | + (addr_hit[ 22] & (|(PINMUX_PERMIT[ 22] & ~reg_be))) | + (addr_hit[ 23] & (|(PINMUX_PERMIT[ 23] & ~reg_be))) | + (addr_hit[ 24] & (|(PINMUX_PERMIT[ 24] & ~reg_be))) | + (addr_hit[ 25] & (|(PINMUX_PERMIT[ 25] & ~reg_be))) | + (addr_hit[ 26] & (|(PINMUX_PERMIT[ 26] & ~reg_be))) | + (addr_hit[ 27] & (|(PINMUX_PERMIT[ 27] & ~reg_be))) | + (addr_hit[ 28] & (|(PINMUX_PERMIT[ 28] & ~reg_be))) | + (addr_hit[ 29] & (|(PINMUX_PERMIT[ 29] & ~reg_be))) | + (addr_hit[ 30] & (|(PINMUX_PERMIT[ 30] & ~reg_be))) | + (addr_hit[ 31] & (|(PINMUX_PERMIT[ 31] & ~reg_be))) | + (addr_hit[ 32] & (|(PINMUX_PERMIT[ 32] & ~reg_be))) | + (addr_hit[ 33] & (|(PINMUX_PERMIT[ 33] & ~reg_be))) | + (addr_hit[ 34] & (|(PINMUX_PERMIT[ 34] & ~reg_be))) | + (addr_hit[ 35] & (|(PINMUX_PERMIT[ 35] & ~reg_be))) | + (addr_hit[ 36] & (|(PINMUX_PERMIT[ 36] & ~reg_be))) | + (addr_hit[ 37] & (|(PINMUX_PERMIT[ 37] & ~reg_be))) | + (addr_hit[ 38] & (|(PINMUX_PERMIT[ 38] & ~reg_be))) | + (addr_hit[ 39] & (|(PINMUX_PERMIT[ 39] & ~reg_be))) | + (addr_hit[ 40] & (|(PINMUX_PERMIT[ 40] & ~reg_be))) | + (addr_hit[ 41] & (|(PINMUX_PERMIT[ 41] & ~reg_be))) | + (addr_hit[ 42] & (|(PINMUX_PERMIT[ 42] & ~reg_be))) | + (addr_hit[ 43] & (|(PINMUX_PERMIT[ 43] & ~reg_be))) | + (addr_hit[ 44] & (|(PINMUX_PERMIT[ 44] & ~reg_be))) | + (addr_hit[ 45] & (|(PINMUX_PERMIT[ 45] & ~reg_be))) | + (addr_hit[ 46] & (|(PINMUX_PERMIT[ 46] & ~reg_be))) | + (addr_hit[ 47] & (|(PINMUX_PERMIT[ 47] & ~reg_be))) | + (addr_hit[ 48] & (|(PINMUX_PERMIT[ 48] & ~reg_be))) | + (addr_hit[ 49] & (|(PINMUX_PERMIT[ 49] & ~reg_be))) | + (addr_hit[ 50] & (|(PINMUX_PERMIT[ 50] & ~reg_be))) | + (addr_hit[ 51] & (|(PINMUX_PERMIT[ 51] & ~reg_be))) | + (addr_hit[ 52] & (|(PINMUX_PERMIT[ 52] & ~reg_be))) | + (addr_hit[ 53] & (|(PINMUX_PERMIT[ 53] & ~reg_be))) | + (addr_hit[ 54] & (|(PINMUX_PERMIT[ 54] & ~reg_be))) | + (addr_hit[ 55] & (|(PINMUX_PERMIT[ 55] & ~reg_be))) | + (addr_hit[ 56] & (|(PINMUX_PERMIT[ 56] & ~reg_be))) | + (addr_hit[ 57] & (|(PINMUX_PERMIT[ 57] & ~reg_be))) | + (addr_hit[ 58] & (|(PINMUX_PERMIT[ 58] & ~reg_be))) | + (addr_hit[ 59] & (|(PINMUX_PERMIT[ 59] & ~reg_be))) | + (addr_hit[ 60] & (|(PINMUX_PERMIT[ 60] & ~reg_be))) | + (addr_hit[ 61] & (|(PINMUX_PERMIT[ 61] & ~reg_be))) | + (addr_hit[ 62] & (|(PINMUX_PERMIT[ 62] & ~reg_be))) | + (addr_hit[ 63] & (|(PINMUX_PERMIT[ 63] & ~reg_be))) | + (addr_hit[ 64] & (|(PINMUX_PERMIT[ 64] & ~reg_be))) | + (addr_hit[ 65] & (|(PINMUX_PERMIT[ 65] & ~reg_be))) | + (addr_hit[ 66] & (|(PINMUX_PERMIT[ 66] & ~reg_be))) | + (addr_hit[ 67] & (|(PINMUX_PERMIT[ 67] & ~reg_be))) | + (addr_hit[ 68] & (|(PINMUX_PERMIT[ 68] & ~reg_be))) | + (addr_hit[ 69] & (|(PINMUX_PERMIT[ 69] & ~reg_be))) | + (addr_hit[ 70] & (|(PINMUX_PERMIT[ 70] & ~reg_be))) | + (addr_hit[ 71] & (|(PINMUX_PERMIT[ 71] & ~reg_be))) | + (addr_hit[ 72] & (|(PINMUX_PERMIT[ 72] & ~reg_be))) | + (addr_hit[ 73] & (|(PINMUX_PERMIT[ 73] & ~reg_be))) | + (addr_hit[ 74] & (|(PINMUX_PERMIT[ 74] & ~reg_be))) | + (addr_hit[ 75] & (|(PINMUX_PERMIT[ 75] & ~reg_be))) | + (addr_hit[ 76] & (|(PINMUX_PERMIT[ 76] & ~reg_be))) | + (addr_hit[ 77] & (|(PINMUX_PERMIT[ 77] & ~reg_be))) | + (addr_hit[ 78] & (|(PINMUX_PERMIT[ 78] & ~reg_be))) | + (addr_hit[ 79] & (|(PINMUX_PERMIT[ 79] & ~reg_be))) | + (addr_hit[ 80] & (|(PINMUX_PERMIT[ 80] & ~reg_be))) | + (addr_hit[ 81] & (|(PINMUX_PERMIT[ 81] & ~reg_be))) | + (addr_hit[ 82] & (|(PINMUX_PERMIT[ 82] & ~reg_be))) | + (addr_hit[ 83] & (|(PINMUX_PERMIT[ 83] & ~reg_be))) | + (addr_hit[ 84] & (|(PINMUX_PERMIT[ 84] & ~reg_be))) | + (addr_hit[ 85] & (|(PINMUX_PERMIT[ 85] & ~reg_be))) | + (addr_hit[ 86] & (|(PINMUX_PERMIT[ 86] & ~reg_be))) | + (addr_hit[ 87] & (|(PINMUX_PERMIT[ 87] & ~reg_be))) | + (addr_hit[ 88] & (|(PINMUX_PERMIT[ 88] & ~reg_be))) | + (addr_hit[ 89] & (|(PINMUX_PERMIT[ 89] & ~reg_be))) | + (addr_hit[ 90] & (|(PINMUX_PERMIT[ 90] & ~reg_be))) | + (addr_hit[ 91] & (|(PINMUX_PERMIT[ 91] & ~reg_be))) | + (addr_hit[ 92] & (|(PINMUX_PERMIT[ 92] & ~reg_be))) | + (addr_hit[ 93] & (|(PINMUX_PERMIT[ 93] & ~reg_be))) | + (addr_hit[ 94] & (|(PINMUX_PERMIT[ 94] & ~reg_be))) | + (addr_hit[ 95] & (|(PINMUX_PERMIT[ 95] & ~reg_be))) | + (addr_hit[ 96] & (|(PINMUX_PERMIT[ 96] & ~reg_be))) | + (addr_hit[ 97] & (|(PINMUX_PERMIT[ 97] & ~reg_be))) | + (addr_hit[ 98] & (|(PINMUX_PERMIT[ 98] & ~reg_be))) | + (addr_hit[ 99] & (|(PINMUX_PERMIT[ 99] & ~reg_be))) | + (addr_hit[100] & (|(PINMUX_PERMIT[100] & ~reg_be))) | + (addr_hit[101] & (|(PINMUX_PERMIT[101] & ~reg_be))) | + (addr_hit[102] & (|(PINMUX_PERMIT[102] & ~reg_be))) | + (addr_hit[103] & (|(PINMUX_PERMIT[103] & ~reg_be))) | + (addr_hit[104] & (|(PINMUX_PERMIT[104] & ~reg_be))) | + (addr_hit[105] & (|(PINMUX_PERMIT[105] & ~reg_be))) | + (addr_hit[106] & (|(PINMUX_PERMIT[106] & ~reg_be))) | + (addr_hit[107] & (|(PINMUX_PERMIT[107] & ~reg_be))) | + (addr_hit[108] & (|(PINMUX_PERMIT[108] & ~reg_be))) | + (addr_hit[109] & (|(PINMUX_PERMIT[109] & ~reg_be))) | + (addr_hit[110] & (|(PINMUX_PERMIT[110] & ~reg_be))) | + (addr_hit[111] & (|(PINMUX_PERMIT[111] & ~reg_be))) | + (addr_hit[112] & (|(PINMUX_PERMIT[112] & ~reg_be))) | + (addr_hit[113] & (|(PINMUX_PERMIT[113] & ~reg_be))) | + (addr_hit[114] & (|(PINMUX_PERMIT[114] & ~reg_be))) | + (addr_hit[115] & (|(PINMUX_PERMIT[115] & ~reg_be))) | + (addr_hit[116] & (|(PINMUX_PERMIT[116] & ~reg_be))) | + (addr_hit[117] & (|(PINMUX_PERMIT[117] & ~reg_be))) | + (addr_hit[118] & (|(PINMUX_PERMIT[118] & ~reg_be))) | + (addr_hit[119] & (|(PINMUX_PERMIT[119] & ~reg_be))) | + (addr_hit[120] & (|(PINMUX_PERMIT[120] & ~reg_be))) | + (addr_hit[121] & (|(PINMUX_PERMIT[121] & ~reg_be))) | + (addr_hit[122] & (|(PINMUX_PERMIT[122] & ~reg_be))) | + (addr_hit[123] & (|(PINMUX_PERMIT[123] & ~reg_be))) | + (addr_hit[124] & (|(PINMUX_PERMIT[124] & ~reg_be))) | + (addr_hit[125] & (|(PINMUX_PERMIT[125] & ~reg_be))) | + (addr_hit[126] & (|(PINMUX_PERMIT[126] & ~reg_be))) | + (addr_hit[127] & (|(PINMUX_PERMIT[127] & ~reg_be))) | + (addr_hit[128] & (|(PINMUX_PERMIT[128] & ~reg_be))) | + (addr_hit[129] & (|(PINMUX_PERMIT[129] & ~reg_be))) | + (addr_hit[130] & (|(PINMUX_PERMIT[130] & ~reg_be))) | + (addr_hit[131] & (|(PINMUX_PERMIT[131] & ~reg_be))) | + (addr_hit[132] & (|(PINMUX_PERMIT[132] & ~reg_be))) | + (addr_hit[133] & (|(PINMUX_PERMIT[133] & ~reg_be))) | + (addr_hit[134] & (|(PINMUX_PERMIT[134] & ~reg_be))) | + (addr_hit[135] & (|(PINMUX_PERMIT[135] & ~reg_be))) | + (addr_hit[136] & (|(PINMUX_PERMIT[136] & ~reg_be))) | + (addr_hit[137] & (|(PINMUX_PERMIT[137] & ~reg_be))) | + (addr_hit[138] & (|(PINMUX_PERMIT[138] & ~reg_be))) | + (addr_hit[139] & (|(PINMUX_PERMIT[139] & ~reg_be))) | + (addr_hit[140] & (|(PINMUX_PERMIT[140] & ~reg_be))) | + (addr_hit[141] & (|(PINMUX_PERMIT[141] & ~reg_be))) | + (addr_hit[142] & (|(PINMUX_PERMIT[142] & ~reg_be))) | + (addr_hit[143] & (|(PINMUX_PERMIT[143] & ~reg_be))) | + (addr_hit[144] & (|(PINMUX_PERMIT[144] & ~reg_be))) | + (addr_hit[145] & (|(PINMUX_PERMIT[145] & ~reg_be))) | + (addr_hit[146] & (|(PINMUX_PERMIT[146] & ~reg_be))) | + (addr_hit[147] & (|(PINMUX_PERMIT[147] & ~reg_be))) | + (addr_hit[148] & (|(PINMUX_PERMIT[148] & ~reg_be))) | + (addr_hit[149] & (|(PINMUX_PERMIT[149] & ~reg_be))) | + (addr_hit[150] & (|(PINMUX_PERMIT[150] & ~reg_be))) | + (addr_hit[151] & (|(PINMUX_PERMIT[151] & ~reg_be))) | + (addr_hit[152] & (|(PINMUX_PERMIT[152] & ~reg_be))) | + (addr_hit[153] & (|(PINMUX_PERMIT[153] & ~reg_be))) | + (addr_hit[154] & (|(PINMUX_PERMIT[154] & ~reg_be))) | + (addr_hit[155] & (|(PINMUX_PERMIT[155] & ~reg_be))) | + (addr_hit[156] & (|(PINMUX_PERMIT[156] & ~reg_be))) | + (addr_hit[157] & (|(PINMUX_PERMIT[157] & ~reg_be))) | + (addr_hit[158] & (|(PINMUX_PERMIT[158] & ~reg_be))) | + (addr_hit[159] & (|(PINMUX_PERMIT[159] & ~reg_be))) | + (addr_hit[160] & (|(PINMUX_PERMIT[160] & ~reg_be))) | + (addr_hit[161] & (|(PINMUX_PERMIT[161] & ~reg_be))) | + (addr_hit[162] & (|(PINMUX_PERMIT[162] & ~reg_be))) | + (addr_hit[163] & (|(PINMUX_PERMIT[163] & ~reg_be))) | + (addr_hit[164] & (|(PINMUX_PERMIT[164] & ~reg_be))) | + (addr_hit[165] & (|(PINMUX_PERMIT[165] & ~reg_be))) | + (addr_hit[166] & (|(PINMUX_PERMIT[166] & ~reg_be))) | + (addr_hit[167] & (|(PINMUX_PERMIT[167] & ~reg_be))) | + (addr_hit[168] & (|(PINMUX_PERMIT[168] & ~reg_be))) | + (addr_hit[169] & (|(PINMUX_PERMIT[169] & ~reg_be))) | + (addr_hit[170] & (|(PINMUX_PERMIT[170] & ~reg_be))) | + (addr_hit[171] & (|(PINMUX_PERMIT[171] & ~reg_be))) | + (addr_hit[172] & (|(PINMUX_PERMIT[172] & ~reg_be))) | + (addr_hit[173] & (|(PINMUX_PERMIT[173] & ~reg_be))) | + (addr_hit[174] & (|(PINMUX_PERMIT[174] & ~reg_be))) | + (addr_hit[175] & (|(PINMUX_PERMIT[175] & ~reg_be))) | + (addr_hit[176] & (|(PINMUX_PERMIT[176] & ~reg_be))) | + (addr_hit[177] & (|(PINMUX_PERMIT[177] & ~reg_be))) | + (addr_hit[178] & (|(PINMUX_PERMIT[178] & ~reg_be))) | + (addr_hit[179] & (|(PINMUX_PERMIT[179] & ~reg_be))) | + (addr_hit[180] & (|(PINMUX_PERMIT[180] & ~reg_be))) | + (addr_hit[181] & (|(PINMUX_PERMIT[181] & ~reg_be))) | + (addr_hit[182] & (|(PINMUX_PERMIT[182] & ~reg_be))) | + (addr_hit[183] & (|(PINMUX_PERMIT[183] & ~reg_be))) | + (addr_hit[184] & (|(PINMUX_PERMIT[184] & ~reg_be))) | + (addr_hit[185] & (|(PINMUX_PERMIT[185] & ~reg_be))) | + (addr_hit[186] & (|(PINMUX_PERMIT[186] & ~reg_be))) | + (addr_hit[187] & (|(PINMUX_PERMIT[187] & ~reg_be))) | + (addr_hit[188] & (|(PINMUX_PERMIT[188] & ~reg_be))) | + (addr_hit[189] & (|(PINMUX_PERMIT[189] & ~reg_be))) | + (addr_hit[190] & (|(PINMUX_PERMIT[190] & ~reg_be))) | + (addr_hit[191] & (|(PINMUX_PERMIT[191] & ~reg_be))) | + (addr_hit[192] & (|(PINMUX_PERMIT[192] & ~reg_be))) | + (addr_hit[193] & (|(PINMUX_PERMIT[193] & ~reg_be))) | + (addr_hit[194] & (|(PINMUX_PERMIT[194] & ~reg_be))) | + (addr_hit[195] & (|(PINMUX_PERMIT[195] & ~reg_be))) | + (addr_hit[196] & (|(PINMUX_PERMIT[196] & ~reg_be))) | + (addr_hit[197] & (|(PINMUX_PERMIT[197] & ~reg_be))) | + (addr_hit[198] & (|(PINMUX_PERMIT[198] & ~reg_be))) | + (addr_hit[199] & (|(PINMUX_PERMIT[199] & ~reg_be))) | + (addr_hit[200] & (|(PINMUX_PERMIT[200] & ~reg_be))) | + (addr_hit[201] & (|(PINMUX_PERMIT[201] & ~reg_be))) | + (addr_hit[202] & (|(PINMUX_PERMIT[202] & ~reg_be))) | + (addr_hit[203] & (|(PINMUX_PERMIT[203] & ~reg_be))) | + (addr_hit[204] & (|(PINMUX_PERMIT[204] & ~reg_be))) | + (addr_hit[205] & (|(PINMUX_PERMIT[205] & ~reg_be))) | + (addr_hit[206] & (|(PINMUX_PERMIT[206] & ~reg_be))) | + (addr_hit[207] & (|(PINMUX_PERMIT[207] & ~reg_be))) | + (addr_hit[208] & (|(PINMUX_PERMIT[208] & ~reg_be))) | + (addr_hit[209] & (|(PINMUX_PERMIT[209] & ~reg_be))) | + (addr_hit[210] & (|(PINMUX_PERMIT[210] & ~reg_be))) | + (addr_hit[211] & (|(PINMUX_PERMIT[211] & ~reg_be))) | + (addr_hit[212] & (|(PINMUX_PERMIT[212] & ~reg_be))) | + (addr_hit[213] & (|(PINMUX_PERMIT[213] & ~reg_be))) | + (addr_hit[214] & (|(PINMUX_PERMIT[214] & ~reg_be))) | + (addr_hit[215] & (|(PINMUX_PERMIT[215] & ~reg_be))) | + (addr_hit[216] & (|(PINMUX_PERMIT[216] & ~reg_be))) | + (addr_hit[217] & (|(PINMUX_PERMIT[217] & ~reg_be))) | + (addr_hit[218] & (|(PINMUX_PERMIT[218] & ~reg_be))) | + (addr_hit[219] & (|(PINMUX_PERMIT[219] & ~reg_be))) | + (addr_hit[220] & (|(PINMUX_PERMIT[220] & ~reg_be))) | + (addr_hit[221] & (|(PINMUX_PERMIT[221] & ~reg_be))) | + (addr_hit[222] & (|(PINMUX_PERMIT[222] & ~reg_be))) | + (addr_hit[223] & (|(PINMUX_PERMIT[223] & ~reg_be))) | + (addr_hit[224] & (|(PINMUX_PERMIT[224] & ~reg_be))) | + (addr_hit[225] & (|(PINMUX_PERMIT[225] & ~reg_be))) | + (addr_hit[226] & (|(PINMUX_PERMIT[226] & ~reg_be))) | + (addr_hit[227] & (|(PINMUX_PERMIT[227] & ~reg_be))) | + (addr_hit[228] & (|(PINMUX_PERMIT[228] & ~reg_be))) | + (addr_hit[229] & (|(PINMUX_PERMIT[229] & ~reg_be))) | + (addr_hit[230] & (|(PINMUX_PERMIT[230] & ~reg_be))) | + (addr_hit[231] & (|(PINMUX_PERMIT[231] & ~reg_be))) | + (addr_hit[232] & (|(PINMUX_PERMIT[232] & ~reg_be))) | + (addr_hit[233] & (|(PINMUX_PERMIT[233] & ~reg_be))) | + (addr_hit[234] & (|(PINMUX_PERMIT[234] & ~reg_be))) | + (addr_hit[235] & (|(PINMUX_PERMIT[235] & ~reg_be))) | + (addr_hit[236] & (|(PINMUX_PERMIT[236] & ~reg_be))) | + (addr_hit[237] & (|(PINMUX_PERMIT[237] & ~reg_be))) | + (addr_hit[238] & (|(PINMUX_PERMIT[238] & ~reg_be))) | + (addr_hit[239] & (|(PINMUX_PERMIT[239] & ~reg_be))) | + (addr_hit[240] & (|(PINMUX_PERMIT[240] & ~reg_be))) | + (addr_hit[241] & (|(PINMUX_PERMIT[241] & ~reg_be))) | + (addr_hit[242] & (|(PINMUX_PERMIT[242] & ~reg_be))) | + (addr_hit[243] & (|(PINMUX_PERMIT[243] & ~reg_be))) | + (addr_hit[244] & (|(PINMUX_PERMIT[244] & ~reg_be))) | + (addr_hit[245] & (|(PINMUX_PERMIT[245] & ~reg_be))) | + (addr_hit[246] & (|(PINMUX_PERMIT[246] & ~reg_be))) | + (addr_hit[247] & (|(PINMUX_PERMIT[247] & ~reg_be))) | + (addr_hit[248] & (|(PINMUX_PERMIT[248] & ~reg_be))) | + (addr_hit[249] & (|(PINMUX_PERMIT[249] & ~reg_be))) | + (addr_hit[250] & (|(PINMUX_PERMIT[250] & ~reg_be))) | + (addr_hit[251] & (|(PINMUX_PERMIT[251] & ~reg_be))) | + (addr_hit[252] & (|(PINMUX_PERMIT[252] & ~reg_be))) | + (addr_hit[253] & (|(PINMUX_PERMIT[253] & ~reg_be))) | + (addr_hit[254] & (|(PINMUX_PERMIT[254] & ~reg_be))) | + (addr_hit[255] & (|(PINMUX_PERMIT[255] & ~reg_be))) | + (addr_hit[256] & (|(PINMUX_PERMIT[256] & ~reg_be))) | + (addr_hit[257] & (|(PINMUX_PERMIT[257] & ~reg_be))) | + (addr_hit[258] & (|(PINMUX_PERMIT[258] & ~reg_be))) | + (addr_hit[259] & (|(PINMUX_PERMIT[259] & ~reg_be))) | + (addr_hit[260] & (|(PINMUX_PERMIT[260] & ~reg_be))) | + (addr_hit[261] & (|(PINMUX_PERMIT[261] & ~reg_be))) | + (addr_hit[262] & (|(PINMUX_PERMIT[262] & ~reg_be))) | + (addr_hit[263] & (|(PINMUX_PERMIT[263] & ~reg_be))) | + (addr_hit[264] & (|(PINMUX_PERMIT[264] & ~reg_be))) | + (addr_hit[265] & (|(PINMUX_PERMIT[265] & ~reg_be))) | + (addr_hit[266] & (|(PINMUX_PERMIT[266] & ~reg_be))) | + (addr_hit[267] & (|(PINMUX_PERMIT[267] & ~reg_be))) | + (addr_hit[268] & (|(PINMUX_PERMIT[268] & ~reg_be))) | + (addr_hit[269] & (|(PINMUX_PERMIT[269] & ~reg_be))) | + (addr_hit[270] & (|(PINMUX_PERMIT[270] & ~reg_be))) | + (addr_hit[271] & (|(PINMUX_PERMIT[271] & ~reg_be))) | + (addr_hit[272] & (|(PINMUX_PERMIT[272] & ~reg_be))) | + (addr_hit[273] & (|(PINMUX_PERMIT[273] & ~reg_be))) | + (addr_hit[274] & (|(PINMUX_PERMIT[274] & ~reg_be))) | + (addr_hit[275] & (|(PINMUX_PERMIT[275] & ~reg_be))) | + (addr_hit[276] & (|(PINMUX_PERMIT[276] & ~reg_be))) | + (addr_hit[277] & (|(PINMUX_PERMIT[277] & ~reg_be))) | + (addr_hit[278] & (|(PINMUX_PERMIT[278] & ~reg_be))) | + (addr_hit[279] & (|(PINMUX_PERMIT[279] & ~reg_be))) | + (addr_hit[280] & (|(PINMUX_PERMIT[280] & ~reg_be))) | + (addr_hit[281] & (|(PINMUX_PERMIT[281] & ~reg_be))) | + (addr_hit[282] & (|(PINMUX_PERMIT[282] & ~reg_be))) | + (addr_hit[283] & (|(PINMUX_PERMIT[283] & ~reg_be))) | + (addr_hit[284] & (|(PINMUX_PERMIT[284] & ~reg_be))) | + (addr_hit[285] & (|(PINMUX_PERMIT[285] & ~reg_be))) | + (addr_hit[286] & (|(PINMUX_PERMIT[286] & ~reg_be))) | + (addr_hit[287] & (|(PINMUX_PERMIT[287] & ~reg_be))) | + (addr_hit[288] & (|(PINMUX_PERMIT[288] & ~reg_be))) | + (addr_hit[289] & (|(PINMUX_PERMIT[289] & ~reg_be))) | + (addr_hit[290] & (|(PINMUX_PERMIT[290] & ~reg_be))) | + (addr_hit[291] & (|(PINMUX_PERMIT[291] & ~reg_be))) | + (addr_hit[292] & (|(PINMUX_PERMIT[292] & ~reg_be))) | + (addr_hit[293] & (|(PINMUX_PERMIT[293] & ~reg_be))) | + (addr_hit[294] & (|(PINMUX_PERMIT[294] & ~reg_be))) | + (addr_hit[295] & (|(PINMUX_PERMIT[295] & ~reg_be))) | + (addr_hit[296] & (|(PINMUX_PERMIT[296] & ~reg_be))) | + (addr_hit[297] & (|(PINMUX_PERMIT[297] & ~reg_be))) | + (addr_hit[298] & (|(PINMUX_PERMIT[298] & ~reg_be))) | + (addr_hit[299] & (|(PINMUX_PERMIT[299] & ~reg_be))) | + (addr_hit[300] & (|(PINMUX_PERMIT[300] & ~reg_be))) | + (addr_hit[301] & (|(PINMUX_PERMIT[301] & ~reg_be))) | + (addr_hit[302] & (|(PINMUX_PERMIT[302] & ~reg_be))) | + (addr_hit[303] & (|(PINMUX_PERMIT[303] & ~reg_be))) | + (addr_hit[304] & (|(PINMUX_PERMIT[304] & ~reg_be))) | + (addr_hit[305] & (|(PINMUX_PERMIT[305] & ~reg_be))) | + (addr_hit[306] & (|(PINMUX_PERMIT[306] & ~reg_be))) | + (addr_hit[307] & (|(PINMUX_PERMIT[307] & ~reg_be))) | + (addr_hit[308] & (|(PINMUX_PERMIT[308] & ~reg_be))) | + (addr_hit[309] & (|(PINMUX_PERMIT[309] & ~reg_be))) | + (addr_hit[310] & (|(PINMUX_PERMIT[310] & ~reg_be))) | + (addr_hit[311] & (|(PINMUX_PERMIT[311] & ~reg_be))) | + (addr_hit[312] & (|(PINMUX_PERMIT[312] & ~reg_be))) | + (addr_hit[313] & (|(PINMUX_PERMIT[313] & ~reg_be))) | + (addr_hit[314] & (|(PINMUX_PERMIT[314] & ~reg_be))) | + (addr_hit[315] & (|(PINMUX_PERMIT[315] & ~reg_be))) | + (addr_hit[316] & (|(PINMUX_PERMIT[316] & ~reg_be))) | + (addr_hit[317] & (|(PINMUX_PERMIT[317] & ~reg_be))) | + (addr_hit[318] & (|(PINMUX_PERMIT[318] & ~reg_be))) | + (addr_hit[319] & (|(PINMUX_PERMIT[319] & ~reg_be))) | + (addr_hit[320] & (|(PINMUX_PERMIT[320] & ~reg_be))) | + (addr_hit[321] & (|(PINMUX_PERMIT[321] & ~reg_be))) | + (addr_hit[322] & (|(PINMUX_PERMIT[322] & ~reg_be))) | + (addr_hit[323] & (|(PINMUX_PERMIT[323] & ~reg_be))) | + (addr_hit[324] & (|(PINMUX_PERMIT[324] & ~reg_be))) | + (addr_hit[325] & (|(PINMUX_PERMIT[325] & ~reg_be))) | + (addr_hit[326] & (|(PINMUX_PERMIT[326] & ~reg_be))) | + (addr_hit[327] & (|(PINMUX_PERMIT[327] & ~reg_be))) | + (addr_hit[328] & (|(PINMUX_PERMIT[328] & ~reg_be))) | + (addr_hit[329] & (|(PINMUX_PERMIT[329] & ~reg_be))) | + (addr_hit[330] & (|(PINMUX_PERMIT[330] & ~reg_be))) | + (addr_hit[331] & (|(PINMUX_PERMIT[331] & ~reg_be))) | + (addr_hit[332] & (|(PINMUX_PERMIT[332] & ~reg_be))) | + (addr_hit[333] & (|(PINMUX_PERMIT[333] & ~reg_be))) | + (addr_hit[334] & (|(PINMUX_PERMIT[334] & ~reg_be))) | + (addr_hit[335] & (|(PINMUX_PERMIT[335] & ~reg_be))) | + (addr_hit[336] & (|(PINMUX_PERMIT[336] & ~reg_be))) | + (addr_hit[337] & (|(PINMUX_PERMIT[337] & ~reg_be))) | + (addr_hit[338] & (|(PINMUX_PERMIT[338] & ~reg_be))) | + (addr_hit[339] & (|(PINMUX_PERMIT[339] & ~reg_be))) | + (addr_hit[340] & (|(PINMUX_PERMIT[340] & ~reg_be))) | + (addr_hit[341] & (|(PINMUX_PERMIT[341] & ~reg_be))) | + (addr_hit[342] & (|(PINMUX_PERMIT[342] & ~reg_be))) | + (addr_hit[343] & (|(PINMUX_PERMIT[343] & ~reg_be))) | + (addr_hit[344] & (|(PINMUX_PERMIT[344] & ~reg_be))) | + (addr_hit[345] & (|(PINMUX_PERMIT[345] & ~reg_be))) | + (addr_hit[346] & (|(PINMUX_PERMIT[346] & ~reg_be))) | + (addr_hit[347] & (|(PINMUX_PERMIT[347] & ~reg_be))) | + (addr_hit[348] & (|(PINMUX_PERMIT[348] & ~reg_be))) | + (addr_hit[349] & (|(PINMUX_PERMIT[349] & ~reg_be))) | + (addr_hit[350] & (|(PINMUX_PERMIT[350] & ~reg_be))) | + (addr_hit[351] & (|(PINMUX_PERMIT[351] & ~reg_be))) | + (addr_hit[352] & (|(PINMUX_PERMIT[352] & ~reg_be))) | + (addr_hit[353] & (|(PINMUX_PERMIT[353] & ~reg_be))) | + (addr_hit[354] & (|(PINMUX_PERMIT[354] & ~reg_be))) | + (addr_hit[355] & (|(PINMUX_PERMIT[355] & ~reg_be))) | + (addr_hit[356] & (|(PINMUX_PERMIT[356] & ~reg_be))) | + (addr_hit[357] & (|(PINMUX_PERMIT[357] & ~reg_be))) | + (addr_hit[358] & (|(PINMUX_PERMIT[358] & ~reg_be))) | + (addr_hit[359] & (|(PINMUX_PERMIT[359] & ~reg_be))) | + (addr_hit[360] & (|(PINMUX_PERMIT[360] & ~reg_be))) | + (addr_hit[361] & (|(PINMUX_PERMIT[361] & ~reg_be))) | + (addr_hit[362] & (|(PINMUX_PERMIT[362] & ~reg_be))) | + (addr_hit[363] & (|(PINMUX_PERMIT[363] & ~reg_be))) | + (addr_hit[364] & (|(PINMUX_PERMIT[364] & ~reg_be))) | + (addr_hit[365] & (|(PINMUX_PERMIT[365] & ~reg_be))) | + (addr_hit[366] & (|(PINMUX_PERMIT[366] & ~reg_be))) | + (addr_hit[367] & (|(PINMUX_PERMIT[367] & ~reg_be))) | + (addr_hit[368] & (|(PINMUX_PERMIT[368] & ~reg_be))) | + (addr_hit[369] & (|(PINMUX_PERMIT[369] & ~reg_be))) | + (addr_hit[370] & (|(PINMUX_PERMIT[370] & ~reg_be))) | + (addr_hit[371] & (|(PINMUX_PERMIT[371] & ~reg_be))) | + (addr_hit[372] & (|(PINMUX_PERMIT[372] & ~reg_be))) | + (addr_hit[373] & (|(PINMUX_PERMIT[373] & ~reg_be))) | + (addr_hit[374] & (|(PINMUX_PERMIT[374] & ~reg_be))) | + (addr_hit[375] & (|(PINMUX_PERMIT[375] & ~reg_be))) | + (addr_hit[376] & (|(PINMUX_PERMIT[376] & ~reg_be))) | + (addr_hit[377] & (|(PINMUX_PERMIT[377] & ~reg_be))) | + (addr_hit[378] & (|(PINMUX_PERMIT[378] & ~reg_be))) | + (addr_hit[379] & (|(PINMUX_PERMIT[379] & ~reg_be))) | + (addr_hit[380] & (|(PINMUX_PERMIT[380] & ~reg_be))) | + (addr_hit[381] & (|(PINMUX_PERMIT[381] & ~reg_be))) | + (addr_hit[382] & (|(PINMUX_PERMIT[382] & ~reg_be))) | + (addr_hit[383] & (|(PINMUX_PERMIT[383] & ~reg_be))) | + (addr_hit[384] & (|(PINMUX_PERMIT[384] & ~reg_be))) | + (addr_hit[385] & (|(PINMUX_PERMIT[385] & ~reg_be))) | + (addr_hit[386] & (|(PINMUX_PERMIT[386] & ~reg_be))) | + (addr_hit[387] & (|(PINMUX_PERMIT[387] & ~reg_be))) | + (addr_hit[388] & (|(PINMUX_PERMIT[388] & ~reg_be))) | + (addr_hit[389] & (|(PINMUX_PERMIT[389] & ~reg_be))) | + (addr_hit[390] & (|(PINMUX_PERMIT[390] & ~reg_be))) | + (addr_hit[391] & (|(PINMUX_PERMIT[391] & ~reg_be))) | + (addr_hit[392] & (|(PINMUX_PERMIT[392] & ~reg_be))) | + (addr_hit[393] & (|(PINMUX_PERMIT[393] & ~reg_be))) | + (addr_hit[394] & (|(PINMUX_PERMIT[394] & ~reg_be))) | + (addr_hit[395] & (|(PINMUX_PERMIT[395] & ~reg_be))) | + (addr_hit[396] & (|(PINMUX_PERMIT[396] & ~reg_be))) | + (addr_hit[397] & (|(PINMUX_PERMIT[397] & ~reg_be))) | + (addr_hit[398] & (|(PINMUX_PERMIT[398] & ~reg_be))) | + (addr_hit[399] & (|(PINMUX_PERMIT[399] & ~reg_be))) | + (addr_hit[400] & (|(PINMUX_PERMIT[400] & ~reg_be))) | + (addr_hit[401] & (|(PINMUX_PERMIT[401] & ~reg_be))) | + (addr_hit[402] & (|(PINMUX_PERMIT[402] & ~reg_be))) | + (addr_hit[403] & (|(PINMUX_PERMIT[403] & ~reg_be))) | + (addr_hit[404] & (|(PINMUX_PERMIT[404] & ~reg_be))) | + (addr_hit[405] & (|(PINMUX_PERMIT[405] & ~reg_be))) | + (addr_hit[406] & (|(PINMUX_PERMIT[406] & ~reg_be))) | + (addr_hit[407] & (|(PINMUX_PERMIT[407] & ~reg_be))) | + (addr_hit[408] & (|(PINMUX_PERMIT[408] & ~reg_be))) | + (addr_hit[409] & (|(PINMUX_PERMIT[409] & ~reg_be))) | + (addr_hit[410] & (|(PINMUX_PERMIT[410] & ~reg_be))) | + (addr_hit[411] & (|(PINMUX_PERMIT[411] & ~reg_be))) | + (addr_hit[412] & (|(PINMUX_PERMIT[412] & ~reg_be))) | + (addr_hit[413] & (|(PINMUX_PERMIT[413] & ~reg_be))) | + (addr_hit[414] & (|(PINMUX_PERMIT[414] & ~reg_be))) | + (addr_hit[415] & (|(PINMUX_PERMIT[415] & ~reg_be))) | + (addr_hit[416] & (|(PINMUX_PERMIT[416] & ~reg_be))) | + (addr_hit[417] & (|(PINMUX_PERMIT[417] & ~reg_be))) | + (addr_hit[418] & (|(PINMUX_PERMIT[418] & ~reg_be))) | + (addr_hit[419] & (|(PINMUX_PERMIT[419] & ~reg_be))) | + (addr_hit[420] & (|(PINMUX_PERMIT[420] & ~reg_be))) | + (addr_hit[421] & (|(PINMUX_PERMIT[421] & ~reg_be))) | + (addr_hit[422] & (|(PINMUX_PERMIT[422] & ~reg_be))) | + (addr_hit[423] & (|(PINMUX_PERMIT[423] & ~reg_be))) | + (addr_hit[424] & (|(PINMUX_PERMIT[424] & ~reg_be))) | + (addr_hit[425] & (|(PINMUX_PERMIT[425] & ~reg_be))) | + (addr_hit[426] & (|(PINMUX_PERMIT[426] & ~reg_be))) | + (addr_hit[427] & (|(PINMUX_PERMIT[427] & ~reg_be))) | + (addr_hit[428] & (|(PINMUX_PERMIT[428] & ~reg_be))) | + (addr_hit[429] & (|(PINMUX_PERMIT[429] & ~reg_be))) | + (addr_hit[430] & (|(PINMUX_PERMIT[430] & ~reg_be))) | + (addr_hit[431] & (|(PINMUX_PERMIT[431] & ~reg_be))) | + (addr_hit[432] & (|(PINMUX_PERMIT[432] & ~reg_be))) | + (addr_hit[433] & (|(PINMUX_PERMIT[433] & ~reg_be))) | + (addr_hit[434] & (|(PINMUX_PERMIT[434] & ~reg_be))) | + (addr_hit[435] & (|(PINMUX_PERMIT[435] & ~reg_be))) | + (addr_hit[436] & (|(PINMUX_PERMIT[436] & ~reg_be))) | + (addr_hit[437] & (|(PINMUX_PERMIT[437] & ~reg_be))) | + (addr_hit[438] & (|(PINMUX_PERMIT[438] & ~reg_be))) | + (addr_hit[439] & (|(PINMUX_PERMIT[439] & ~reg_be))) | + (addr_hit[440] & (|(PINMUX_PERMIT[440] & ~reg_be))) | + (addr_hit[441] & (|(PINMUX_PERMIT[441] & ~reg_be))) | + (addr_hit[442] & (|(PINMUX_PERMIT[442] & ~reg_be))) | + (addr_hit[443] & (|(PINMUX_PERMIT[443] & ~reg_be))) | + (addr_hit[444] & (|(PINMUX_PERMIT[444] & ~reg_be))) | + (addr_hit[445] & (|(PINMUX_PERMIT[445] & ~reg_be))) | + (addr_hit[446] & (|(PINMUX_PERMIT[446] & ~reg_be))) | + (addr_hit[447] & (|(PINMUX_PERMIT[447] & ~reg_be))) | + (addr_hit[448] & (|(PINMUX_PERMIT[448] & ~reg_be))) | + (addr_hit[449] & (|(PINMUX_PERMIT[449] & ~reg_be))) | + (addr_hit[450] & (|(PINMUX_PERMIT[450] & ~reg_be))) | + (addr_hit[451] & (|(PINMUX_PERMIT[451] & ~reg_be))) | + (addr_hit[452] & (|(PINMUX_PERMIT[452] & ~reg_be))) | + (addr_hit[453] & (|(PINMUX_PERMIT[453] & ~reg_be))) | + (addr_hit[454] & (|(PINMUX_PERMIT[454] & ~reg_be))) | + (addr_hit[455] & (|(PINMUX_PERMIT[455] & ~reg_be))) | + (addr_hit[456] & (|(PINMUX_PERMIT[456] & ~reg_be))) | + (addr_hit[457] & (|(PINMUX_PERMIT[457] & ~reg_be))) | + (addr_hit[458] & (|(PINMUX_PERMIT[458] & ~reg_be))) | + (addr_hit[459] & (|(PINMUX_PERMIT[459] & ~reg_be))) | + (addr_hit[460] & (|(PINMUX_PERMIT[460] & ~reg_be))) | + (addr_hit[461] & (|(PINMUX_PERMIT[461] & ~reg_be))) | + (addr_hit[462] & (|(PINMUX_PERMIT[462] & ~reg_be))) | + (addr_hit[463] & (|(PINMUX_PERMIT[463] & ~reg_be))) | + (addr_hit[464] & (|(PINMUX_PERMIT[464] & ~reg_be))) | + (addr_hit[465] & (|(PINMUX_PERMIT[465] & ~reg_be))) | + (addr_hit[466] & (|(PINMUX_PERMIT[466] & ~reg_be))) | + (addr_hit[467] & (|(PINMUX_PERMIT[467] & ~reg_be))) | + (addr_hit[468] & (|(PINMUX_PERMIT[468] & ~reg_be))) | + (addr_hit[469] & (|(PINMUX_PERMIT[469] & ~reg_be))) | + (addr_hit[470] & (|(PINMUX_PERMIT[470] & ~reg_be))) | + (addr_hit[471] & (|(PINMUX_PERMIT[471] & ~reg_be))) | + (addr_hit[472] & (|(PINMUX_PERMIT[472] & ~reg_be))) | + (addr_hit[473] & (|(PINMUX_PERMIT[473] & ~reg_be))) | + (addr_hit[474] & (|(PINMUX_PERMIT[474] & ~reg_be))) | + (addr_hit[475] & (|(PINMUX_PERMIT[475] & ~reg_be))) | + (addr_hit[476] & (|(PINMUX_PERMIT[476] & ~reg_be))) | + (addr_hit[477] & (|(PINMUX_PERMIT[477] & ~reg_be))) | + (addr_hit[478] & (|(PINMUX_PERMIT[478] & ~reg_be))) | + (addr_hit[479] & (|(PINMUX_PERMIT[479] & ~reg_be))) | + (addr_hit[480] & (|(PINMUX_PERMIT[480] & ~reg_be))) | + (addr_hit[481] & (|(PINMUX_PERMIT[481] & ~reg_be))) | + (addr_hit[482] & (|(PINMUX_PERMIT[482] & ~reg_be))) | + (addr_hit[483] & (|(PINMUX_PERMIT[483] & ~reg_be))) | + (addr_hit[484] & (|(PINMUX_PERMIT[484] & ~reg_be))) | + (addr_hit[485] & (|(PINMUX_PERMIT[485] & ~reg_be))) | + (addr_hit[486] & (|(PINMUX_PERMIT[486] & ~reg_be))) | + (addr_hit[487] & (|(PINMUX_PERMIT[487] & ~reg_be))) | + (addr_hit[488] & (|(PINMUX_PERMIT[488] & ~reg_be))) | + (addr_hit[489] & (|(PINMUX_PERMIT[489] & ~reg_be))) | + (addr_hit[490] & (|(PINMUX_PERMIT[490] & ~reg_be))) | + (addr_hit[491] & (|(PINMUX_PERMIT[491] & ~reg_be))) | + (addr_hit[492] & (|(PINMUX_PERMIT[492] & ~reg_be))) | + (addr_hit[493] & (|(PINMUX_PERMIT[493] & ~reg_be))) | + (addr_hit[494] & (|(PINMUX_PERMIT[494] & ~reg_be))) | + (addr_hit[495] & (|(PINMUX_PERMIT[495] & ~reg_be))) | + (addr_hit[496] & (|(PINMUX_PERMIT[496] & ~reg_be))) | + (addr_hit[497] & (|(PINMUX_PERMIT[497] & ~reg_be))) | + (addr_hit[498] & (|(PINMUX_PERMIT[498] & ~reg_be))) | + (addr_hit[499] & (|(PINMUX_PERMIT[499] & ~reg_be))) | + (addr_hit[500] & (|(PINMUX_PERMIT[500] & ~reg_be))) | + (addr_hit[501] & (|(PINMUX_PERMIT[501] & ~reg_be))) | + (addr_hit[502] & (|(PINMUX_PERMIT[502] & ~reg_be))))); + end + + // Generate write-enables + assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_0_we = addr_hit[1] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_0_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_1_we = addr_hit[2] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_1_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_2_we = addr_hit[3] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_2_wd = reg_wdata[0]; + assign mio_periph_insel_regwen_3_we = addr_hit[4] & reg_we & !reg_error; + + assign mio_periph_insel_regwen_3_wd = reg_wdata[0]; + assign mio_periph_insel_0_we = addr_hit[5] & reg_we & !reg_error; + + assign mio_periph_insel_0_wd = reg_wdata[3:0]; + assign mio_periph_insel_1_we = addr_hit[6] & reg_we & !reg_error; + + assign mio_periph_insel_1_wd = reg_wdata[3:0]; + assign mio_periph_insel_2_we = addr_hit[7] & reg_we & !reg_error; + + assign mio_periph_insel_2_wd = reg_wdata[3:0]; + assign mio_periph_insel_3_we = addr_hit[8] & reg_we & !reg_error; + + assign mio_periph_insel_3_wd = reg_wdata[3:0]; + assign mio_outsel_regwen_0_we = addr_hit[9] & reg_we & !reg_error; + + assign mio_outsel_regwen_0_wd = reg_wdata[0]; + assign mio_outsel_regwen_1_we = addr_hit[10] & reg_we & !reg_error; + + assign mio_outsel_regwen_1_wd = reg_wdata[0]; + assign mio_outsel_regwen_2_we = addr_hit[11] & reg_we & !reg_error; + + assign mio_outsel_regwen_2_wd = reg_wdata[0]; + assign mio_outsel_regwen_3_we = addr_hit[12] & reg_we & !reg_error; + + assign mio_outsel_regwen_3_wd = reg_wdata[0]; + assign mio_outsel_regwen_4_we = addr_hit[13] & reg_we & !reg_error; + + assign mio_outsel_regwen_4_wd = reg_wdata[0]; + assign mio_outsel_regwen_5_we = addr_hit[14] & reg_we & !reg_error; + + assign mio_outsel_regwen_5_wd = reg_wdata[0]; + assign mio_outsel_regwen_6_we = addr_hit[15] & reg_we & !reg_error; + + assign mio_outsel_regwen_6_wd = reg_wdata[0]; + assign mio_outsel_regwen_7_we = addr_hit[16] & reg_we & !reg_error; + + assign mio_outsel_regwen_7_wd = reg_wdata[0]; + assign mio_outsel_regwen_8_we = addr_hit[17] & reg_we & !reg_error; + + assign mio_outsel_regwen_8_wd = reg_wdata[0]; + assign mio_outsel_regwen_9_we = addr_hit[18] & reg_we & !reg_error; + + assign mio_outsel_regwen_9_wd = reg_wdata[0]; + assign mio_outsel_regwen_10_we = addr_hit[19] & reg_we & !reg_error; + + assign mio_outsel_regwen_10_wd = reg_wdata[0]; + assign mio_outsel_regwen_11_we = addr_hit[20] & reg_we & !reg_error; + + assign mio_outsel_regwen_11_wd = reg_wdata[0]; + assign mio_outsel_0_we = addr_hit[21] & reg_we & !reg_error; + + assign mio_outsel_0_wd = reg_wdata[2:0]; + assign mio_outsel_1_we = addr_hit[22] & reg_we & !reg_error; + + assign mio_outsel_1_wd = reg_wdata[2:0]; + assign mio_outsel_2_we = addr_hit[23] & reg_we & !reg_error; + + assign mio_outsel_2_wd = reg_wdata[2:0]; + assign mio_outsel_3_we = addr_hit[24] & reg_we & !reg_error; + + assign mio_outsel_3_wd = reg_wdata[2:0]; + assign mio_outsel_4_we = addr_hit[25] & reg_we & !reg_error; + + assign mio_outsel_4_wd = reg_wdata[2:0]; + assign mio_outsel_5_we = addr_hit[26] & reg_we & !reg_error; + + assign mio_outsel_5_wd = reg_wdata[2:0]; + assign mio_outsel_6_we = addr_hit[27] & reg_we & !reg_error; + + assign mio_outsel_6_wd = reg_wdata[2:0]; + assign mio_outsel_7_we = addr_hit[28] & reg_we & !reg_error; + + assign mio_outsel_7_wd = reg_wdata[2:0]; + assign mio_outsel_8_we = addr_hit[29] & reg_we & !reg_error; + + assign mio_outsel_8_wd = reg_wdata[2:0]; + assign mio_outsel_9_we = addr_hit[30] & reg_we & !reg_error; + + assign mio_outsel_9_wd = reg_wdata[2:0]; + assign mio_outsel_10_we = addr_hit[31] & reg_we & !reg_error; + + assign mio_outsel_10_wd = reg_wdata[2:0]; + assign mio_outsel_11_we = addr_hit[32] & reg_we & !reg_error; + + assign mio_outsel_11_wd = reg_wdata[2:0]; + assign mio_pad_attr_regwen_0_we = addr_hit[33] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_0_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_1_we = addr_hit[34] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_1_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_2_we = addr_hit[35] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_2_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_3_we = addr_hit[36] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_3_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_4_we = addr_hit[37] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_4_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_5_we = addr_hit[38] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_5_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_6_we = addr_hit[39] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_6_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_7_we = addr_hit[40] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_7_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_8_we = addr_hit[41] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_8_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_9_we = addr_hit[42] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_9_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_10_we = addr_hit[43] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_10_wd = reg_wdata[0]; + assign mio_pad_attr_regwen_11_we = addr_hit[44] & reg_we & !reg_error; + + assign mio_pad_attr_regwen_11_wd = reg_wdata[0]; + assign mio_pad_attr_0_re = addr_hit[45] & reg_re & !reg_error; + assign mio_pad_attr_0_we = addr_hit[45] & reg_we & !reg_error; + + assign mio_pad_attr_0_invert_0_wd = reg_wdata[0]; + + assign mio_pad_attr_0_virtual_od_en_0_wd = reg_wdata[1]; + + assign mio_pad_attr_0_pull_en_0_wd = reg_wdata[2]; + + assign mio_pad_attr_0_pull_select_0_wd = reg_wdata[3]; + + assign mio_pad_attr_0_keeper_en_0_wd = reg_wdata[4]; + + assign mio_pad_attr_0_schmitt_en_0_wd = reg_wdata[5]; + + assign mio_pad_attr_0_od_en_0_wd = reg_wdata[6]; + + assign mio_pad_attr_0_input_disable_0_wd = reg_wdata[7]; + + assign mio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; + + assign mio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; + assign mio_pad_attr_1_re = addr_hit[46] & reg_re & !reg_error; + assign mio_pad_attr_1_we = addr_hit[46] & reg_we & !reg_error; + + assign mio_pad_attr_1_invert_1_wd = reg_wdata[0]; + + assign mio_pad_attr_1_virtual_od_en_1_wd = reg_wdata[1]; + + assign mio_pad_attr_1_pull_en_1_wd = reg_wdata[2]; + + assign mio_pad_attr_1_pull_select_1_wd = reg_wdata[3]; + + assign mio_pad_attr_1_keeper_en_1_wd = reg_wdata[4]; + + assign mio_pad_attr_1_schmitt_en_1_wd = reg_wdata[5]; + + assign mio_pad_attr_1_od_en_1_wd = reg_wdata[6]; + + assign mio_pad_attr_1_input_disable_1_wd = reg_wdata[7]; + + assign mio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; + + assign mio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; + assign mio_pad_attr_2_re = addr_hit[47] & reg_re & !reg_error; + assign mio_pad_attr_2_we = addr_hit[47] & reg_we & !reg_error; + + assign mio_pad_attr_2_invert_2_wd = reg_wdata[0]; + + assign mio_pad_attr_2_virtual_od_en_2_wd = reg_wdata[1]; + + assign mio_pad_attr_2_pull_en_2_wd = reg_wdata[2]; + + assign mio_pad_attr_2_pull_select_2_wd = reg_wdata[3]; + + assign mio_pad_attr_2_keeper_en_2_wd = reg_wdata[4]; + + assign mio_pad_attr_2_schmitt_en_2_wd = reg_wdata[5]; + + assign mio_pad_attr_2_od_en_2_wd = reg_wdata[6]; + + assign mio_pad_attr_2_input_disable_2_wd = reg_wdata[7]; + + assign mio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; + + assign mio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; + assign mio_pad_attr_3_re = addr_hit[48] & reg_re & !reg_error; + assign mio_pad_attr_3_we = addr_hit[48] & reg_we & !reg_error; + + assign mio_pad_attr_3_invert_3_wd = reg_wdata[0]; + + assign mio_pad_attr_3_virtual_od_en_3_wd = reg_wdata[1]; + + assign mio_pad_attr_3_pull_en_3_wd = reg_wdata[2]; + + assign mio_pad_attr_3_pull_select_3_wd = reg_wdata[3]; + + assign mio_pad_attr_3_keeper_en_3_wd = reg_wdata[4]; + + assign mio_pad_attr_3_schmitt_en_3_wd = reg_wdata[5]; + + assign mio_pad_attr_3_od_en_3_wd = reg_wdata[6]; + + assign mio_pad_attr_3_input_disable_3_wd = reg_wdata[7]; + + assign mio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; + + assign mio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; + assign mio_pad_attr_4_re = addr_hit[49] & reg_re & !reg_error; + assign mio_pad_attr_4_we = addr_hit[49] & reg_we & !reg_error; + + assign mio_pad_attr_4_invert_4_wd = reg_wdata[0]; + + assign mio_pad_attr_4_virtual_od_en_4_wd = reg_wdata[1]; + + assign mio_pad_attr_4_pull_en_4_wd = reg_wdata[2]; + + assign mio_pad_attr_4_pull_select_4_wd = reg_wdata[3]; + + assign mio_pad_attr_4_keeper_en_4_wd = reg_wdata[4]; + + assign mio_pad_attr_4_schmitt_en_4_wd = reg_wdata[5]; + + assign mio_pad_attr_4_od_en_4_wd = reg_wdata[6]; + + assign mio_pad_attr_4_input_disable_4_wd = reg_wdata[7]; + + assign mio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; + + assign mio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; + assign mio_pad_attr_5_re = addr_hit[50] & reg_re & !reg_error; + assign mio_pad_attr_5_we = addr_hit[50] & reg_we & !reg_error; + + assign mio_pad_attr_5_invert_5_wd = reg_wdata[0]; + + assign mio_pad_attr_5_virtual_od_en_5_wd = reg_wdata[1]; + + assign mio_pad_attr_5_pull_en_5_wd = reg_wdata[2]; + + assign mio_pad_attr_5_pull_select_5_wd = reg_wdata[3]; + + assign mio_pad_attr_5_keeper_en_5_wd = reg_wdata[4]; + + assign mio_pad_attr_5_schmitt_en_5_wd = reg_wdata[5]; + + assign mio_pad_attr_5_od_en_5_wd = reg_wdata[6]; + + assign mio_pad_attr_5_input_disable_5_wd = reg_wdata[7]; + + assign mio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; + + assign mio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; + assign mio_pad_attr_6_re = addr_hit[51] & reg_re & !reg_error; + assign mio_pad_attr_6_we = addr_hit[51] & reg_we & !reg_error; + + assign mio_pad_attr_6_invert_6_wd = reg_wdata[0]; + + assign mio_pad_attr_6_virtual_od_en_6_wd = reg_wdata[1]; + + assign mio_pad_attr_6_pull_en_6_wd = reg_wdata[2]; + + assign mio_pad_attr_6_pull_select_6_wd = reg_wdata[3]; + + assign mio_pad_attr_6_keeper_en_6_wd = reg_wdata[4]; + + assign mio_pad_attr_6_schmitt_en_6_wd = reg_wdata[5]; + + assign mio_pad_attr_6_od_en_6_wd = reg_wdata[6]; + + assign mio_pad_attr_6_input_disable_6_wd = reg_wdata[7]; + + assign mio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; + + assign mio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; + assign mio_pad_attr_7_re = addr_hit[52] & reg_re & !reg_error; + assign mio_pad_attr_7_we = addr_hit[52] & reg_we & !reg_error; + + assign mio_pad_attr_7_invert_7_wd = reg_wdata[0]; + + assign mio_pad_attr_7_virtual_od_en_7_wd = reg_wdata[1]; + + assign mio_pad_attr_7_pull_en_7_wd = reg_wdata[2]; + + assign mio_pad_attr_7_pull_select_7_wd = reg_wdata[3]; + + assign mio_pad_attr_7_keeper_en_7_wd = reg_wdata[4]; + + assign mio_pad_attr_7_schmitt_en_7_wd = reg_wdata[5]; + + assign mio_pad_attr_7_od_en_7_wd = reg_wdata[6]; + + assign mio_pad_attr_7_input_disable_7_wd = reg_wdata[7]; + + assign mio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; + + assign mio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; + assign mio_pad_attr_8_re = addr_hit[53] & reg_re & !reg_error; + assign mio_pad_attr_8_we = addr_hit[53] & reg_we & !reg_error; + + assign mio_pad_attr_8_invert_8_wd = reg_wdata[0]; + + assign mio_pad_attr_8_virtual_od_en_8_wd = reg_wdata[1]; + + assign mio_pad_attr_8_pull_en_8_wd = reg_wdata[2]; + + assign mio_pad_attr_8_pull_select_8_wd = reg_wdata[3]; + + assign mio_pad_attr_8_keeper_en_8_wd = reg_wdata[4]; + + assign mio_pad_attr_8_schmitt_en_8_wd = reg_wdata[5]; + + assign mio_pad_attr_8_od_en_8_wd = reg_wdata[6]; + + assign mio_pad_attr_8_input_disable_8_wd = reg_wdata[7]; + + assign mio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; + + assign mio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; + assign mio_pad_attr_9_re = addr_hit[54] & reg_re & !reg_error; + assign mio_pad_attr_9_we = addr_hit[54] & reg_we & !reg_error; + + assign mio_pad_attr_9_invert_9_wd = reg_wdata[0]; + + assign mio_pad_attr_9_virtual_od_en_9_wd = reg_wdata[1]; + + assign mio_pad_attr_9_pull_en_9_wd = reg_wdata[2]; + + assign mio_pad_attr_9_pull_select_9_wd = reg_wdata[3]; + + assign mio_pad_attr_9_keeper_en_9_wd = reg_wdata[4]; + + assign mio_pad_attr_9_schmitt_en_9_wd = reg_wdata[5]; + + assign mio_pad_attr_9_od_en_9_wd = reg_wdata[6]; + + assign mio_pad_attr_9_input_disable_9_wd = reg_wdata[7]; + + assign mio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; + + assign mio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; + assign mio_pad_attr_10_re = addr_hit[55] & reg_re & !reg_error; + assign mio_pad_attr_10_we = addr_hit[55] & reg_we & !reg_error; + + assign mio_pad_attr_10_invert_10_wd = reg_wdata[0]; + + assign mio_pad_attr_10_virtual_od_en_10_wd = reg_wdata[1]; + + assign mio_pad_attr_10_pull_en_10_wd = reg_wdata[2]; + + assign mio_pad_attr_10_pull_select_10_wd = reg_wdata[3]; + + assign mio_pad_attr_10_keeper_en_10_wd = reg_wdata[4]; + + assign mio_pad_attr_10_schmitt_en_10_wd = reg_wdata[5]; + + assign mio_pad_attr_10_od_en_10_wd = reg_wdata[6]; + + assign mio_pad_attr_10_input_disable_10_wd = reg_wdata[7]; + + assign mio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; + + assign mio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; + assign mio_pad_attr_11_re = addr_hit[56] & reg_re & !reg_error; + assign mio_pad_attr_11_we = addr_hit[56] & reg_we & !reg_error; + + assign mio_pad_attr_11_invert_11_wd = reg_wdata[0]; + + assign mio_pad_attr_11_virtual_od_en_11_wd = reg_wdata[1]; + + assign mio_pad_attr_11_pull_en_11_wd = reg_wdata[2]; + + assign mio_pad_attr_11_pull_select_11_wd = reg_wdata[3]; + + assign mio_pad_attr_11_keeper_en_11_wd = reg_wdata[4]; + + assign mio_pad_attr_11_schmitt_en_11_wd = reg_wdata[5]; + + assign mio_pad_attr_11_od_en_11_wd = reg_wdata[6]; + + assign mio_pad_attr_11_input_disable_11_wd = reg_wdata[7]; + + assign mio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; + + assign mio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; + assign dio_pad_attr_regwen_0_we = addr_hit[57] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_0_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_1_we = addr_hit[58] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_1_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_2_we = addr_hit[59] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_2_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_3_we = addr_hit[60] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_3_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_4_we = addr_hit[61] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_4_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_5_we = addr_hit[62] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_5_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_6_we = addr_hit[63] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_6_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_7_we = addr_hit[64] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_7_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_8_we = addr_hit[65] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_8_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_9_we = addr_hit[66] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_9_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_10_we = addr_hit[67] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_10_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_11_we = addr_hit[68] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_11_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_12_we = addr_hit[69] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_12_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_13_we = addr_hit[70] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_13_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_14_we = addr_hit[71] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_14_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_15_we = addr_hit[72] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_15_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_16_we = addr_hit[73] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_16_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_17_we = addr_hit[74] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_17_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_18_we = addr_hit[75] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_18_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_19_we = addr_hit[76] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_19_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_20_we = addr_hit[77] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_20_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_21_we = addr_hit[78] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_21_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_22_we = addr_hit[79] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_22_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_23_we = addr_hit[80] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_23_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_24_we = addr_hit[81] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_24_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_25_we = addr_hit[82] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_25_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_26_we = addr_hit[83] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_26_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_27_we = addr_hit[84] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_27_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_28_we = addr_hit[85] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_28_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_29_we = addr_hit[86] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_29_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_30_we = addr_hit[87] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_30_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_31_we = addr_hit[88] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_31_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_32_we = addr_hit[89] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_32_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_33_we = addr_hit[90] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_33_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_34_we = addr_hit[91] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_34_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_35_we = addr_hit[92] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_35_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_36_we = addr_hit[93] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_36_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_37_we = addr_hit[94] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_37_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_38_we = addr_hit[95] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_38_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_39_we = addr_hit[96] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_39_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_40_we = addr_hit[97] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_40_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_41_we = addr_hit[98] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_41_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_42_we = addr_hit[99] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_42_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_43_we = addr_hit[100] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_43_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_44_we = addr_hit[101] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_44_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_45_we = addr_hit[102] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_45_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_46_we = addr_hit[103] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_46_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_47_we = addr_hit[104] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_47_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_48_we = addr_hit[105] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_48_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_49_we = addr_hit[106] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_49_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_50_we = addr_hit[107] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_50_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_51_we = addr_hit[108] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_51_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_52_we = addr_hit[109] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_52_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_53_we = addr_hit[110] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_53_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_54_we = addr_hit[111] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_54_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_55_we = addr_hit[112] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_55_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_56_we = addr_hit[113] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_56_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_57_we = addr_hit[114] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_57_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_58_we = addr_hit[115] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_58_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_59_we = addr_hit[116] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_59_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_60_we = addr_hit[117] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_60_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_61_we = addr_hit[118] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_61_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_62_we = addr_hit[119] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_62_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_63_we = addr_hit[120] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_63_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_64_we = addr_hit[121] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_64_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_65_we = addr_hit[122] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_65_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_66_we = addr_hit[123] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_66_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_67_we = addr_hit[124] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_67_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_68_we = addr_hit[125] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_68_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_69_we = addr_hit[126] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_69_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_70_we = addr_hit[127] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_70_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_71_we = addr_hit[128] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_71_wd = reg_wdata[0]; + assign dio_pad_attr_regwen_72_we = addr_hit[129] & reg_we & !reg_error; + + assign dio_pad_attr_regwen_72_wd = reg_wdata[0]; + assign dio_pad_attr_0_re = addr_hit[130] & reg_re & !reg_error; + assign dio_pad_attr_0_we = addr_hit[130] & reg_we & !reg_error; + + assign dio_pad_attr_0_invert_0_wd = reg_wdata[0]; + + assign dio_pad_attr_0_virtual_od_en_0_wd = reg_wdata[1]; + + assign dio_pad_attr_0_pull_en_0_wd = reg_wdata[2]; + + assign dio_pad_attr_0_pull_select_0_wd = reg_wdata[3]; + + assign dio_pad_attr_0_keeper_en_0_wd = reg_wdata[4]; + + assign dio_pad_attr_0_schmitt_en_0_wd = reg_wdata[5]; + + assign dio_pad_attr_0_od_en_0_wd = reg_wdata[6]; + + assign dio_pad_attr_0_input_disable_0_wd = reg_wdata[7]; + + assign dio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; + + assign dio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; + assign dio_pad_attr_1_re = addr_hit[131] & reg_re & !reg_error; + assign dio_pad_attr_1_we = addr_hit[131] & reg_we & !reg_error; + + assign dio_pad_attr_1_invert_1_wd = reg_wdata[0]; + + assign dio_pad_attr_1_virtual_od_en_1_wd = reg_wdata[1]; + + assign dio_pad_attr_1_pull_en_1_wd = reg_wdata[2]; + + assign dio_pad_attr_1_pull_select_1_wd = reg_wdata[3]; + + assign dio_pad_attr_1_keeper_en_1_wd = reg_wdata[4]; + + assign dio_pad_attr_1_schmitt_en_1_wd = reg_wdata[5]; + + assign dio_pad_attr_1_od_en_1_wd = reg_wdata[6]; + + assign dio_pad_attr_1_input_disable_1_wd = reg_wdata[7]; + + assign dio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; + + assign dio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; + assign dio_pad_attr_2_re = addr_hit[132] & reg_re & !reg_error; + assign dio_pad_attr_2_we = addr_hit[132] & reg_we & !reg_error; + + assign dio_pad_attr_2_invert_2_wd = reg_wdata[0]; + + assign dio_pad_attr_2_virtual_od_en_2_wd = reg_wdata[1]; + + assign dio_pad_attr_2_pull_en_2_wd = reg_wdata[2]; + + assign dio_pad_attr_2_pull_select_2_wd = reg_wdata[3]; + + assign dio_pad_attr_2_keeper_en_2_wd = reg_wdata[4]; + + assign dio_pad_attr_2_schmitt_en_2_wd = reg_wdata[5]; + + assign dio_pad_attr_2_od_en_2_wd = reg_wdata[6]; + + assign dio_pad_attr_2_input_disable_2_wd = reg_wdata[7]; + + assign dio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; + + assign dio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; + assign dio_pad_attr_3_re = addr_hit[133] & reg_re & !reg_error; + assign dio_pad_attr_3_we = addr_hit[133] & reg_we & !reg_error; + + assign dio_pad_attr_3_invert_3_wd = reg_wdata[0]; + + assign dio_pad_attr_3_virtual_od_en_3_wd = reg_wdata[1]; + + assign dio_pad_attr_3_pull_en_3_wd = reg_wdata[2]; + + assign dio_pad_attr_3_pull_select_3_wd = reg_wdata[3]; + + assign dio_pad_attr_3_keeper_en_3_wd = reg_wdata[4]; + + assign dio_pad_attr_3_schmitt_en_3_wd = reg_wdata[5]; + + assign dio_pad_attr_3_od_en_3_wd = reg_wdata[6]; + + assign dio_pad_attr_3_input_disable_3_wd = reg_wdata[7]; + + assign dio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; + + assign dio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; + assign dio_pad_attr_4_re = addr_hit[134] & reg_re & !reg_error; + assign dio_pad_attr_4_we = addr_hit[134] & reg_we & !reg_error; + + assign dio_pad_attr_4_invert_4_wd = reg_wdata[0]; + + assign dio_pad_attr_4_virtual_od_en_4_wd = reg_wdata[1]; + + assign dio_pad_attr_4_pull_en_4_wd = reg_wdata[2]; + + assign dio_pad_attr_4_pull_select_4_wd = reg_wdata[3]; + + assign dio_pad_attr_4_keeper_en_4_wd = reg_wdata[4]; + + assign dio_pad_attr_4_schmitt_en_4_wd = reg_wdata[5]; + + assign dio_pad_attr_4_od_en_4_wd = reg_wdata[6]; + + assign dio_pad_attr_4_input_disable_4_wd = reg_wdata[7]; + + assign dio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; + + assign dio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; + assign dio_pad_attr_5_re = addr_hit[135] & reg_re & !reg_error; + assign dio_pad_attr_5_we = addr_hit[135] & reg_we & !reg_error; + + assign dio_pad_attr_5_invert_5_wd = reg_wdata[0]; + + assign dio_pad_attr_5_virtual_od_en_5_wd = reg_wdata[1]; + + assign dio_pad_attr_5_pull_en_5_wd = reg_wdata[2]; + + assign dio_pad_attr_5_pull_select_5_wd = reg_wdata[3]; + + assign dio_pad_attr_5_keeper_en_5_wd = reg_wdata[4]; + + assign dio_pad_attr_5_schmitt_en_5_wd = reg_wdata[5]; + + assign dio_pad_attr_5_od_en_5_wd = reg_wdata[6]; + + assign dio_pad_attr_5_input_disable_5_wd = reg_wdata[7]; + + assign dio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; + + assign dio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; + assign dio_pad_attr_6_re = addr_hit[136] & reg_re & !reg_error; + assign dio_pad_attr_6_we = addr_hit[136] & reg_we & !reg_error; + + assign dio_pad_attr_6_invert_6_wd = reg_wdata[0]; + + assign dio_pad_attr_6_virtual_od_en_6_wd = reg_wdata[1]; + + assign dio_pad_attr_6_pull_en_6_wd = reg_wdata[2]; + + assign dio_pad_attr_6_pull_select_6_wd = reg_wdata[3]; + + assign dio_pad_attr_6_keeper_en_6_wd = reg_wdata[4]; + + assign dio_pad_attr_6_schmitt_en_6_wd = reg_wdata[5]; + + assign dio_pad_attr_6_od_en_6_wd = reg_wdata[6]; + + assign dio_pad_attr_6_input_disable_6_wd = reg_wdata[7]; + + assign dio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; + + assign dio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; + assign dio_pad_attr_7_re = addr_hit[137] & reg_re & !reg_error; + assign dio_pad_attr_7_we = addr_hit[137] & reg_we & !reg_error; + + assign dio_pad_attr_7_invert_7_wd = reg_wdata[0]; + + assign dio_pad_attr_7_virtual_od_en_7_wd = reg_wdata[1]; + + assign dio_pad_attr_7_pull_en_7_wd = reg_wdata[2]; + + assign dio_pad_attr_7_pull_select_7_wd = reg_wdata[3]; + + assign dio_pad_attr_7_keeper_en_7_wd = reg_wdata[4]; + + assign dio_pad_attr_7_schmitt_en_7_wd = reg_wdata[5]; + + assign dio_pad_attr_7_od_en_7_wd = reg_wdata[6]; + + assign dio_pad_attr_7_input_disable_7_wd = reg_wdata[7]; + + assign dio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; + + assign dio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; + assign dio_pad_attr_8_re = addr_hit[138] & reg_re & !reg_error; + assign dio_pad_attr_8_we = addr_hit[138] & reg_we & !reg_error; + + assign dio_pad_attr_8_invert_8_wd = reg_wdata[0]; + + assign dio_pad_attr_8_virtual_od_en_8_wd = reg_wdata[1]; + + assign dio_pad_attr_8_pull_en_8_wd = reg_wdata[2]; + + assign dio_pad_attr_8_pull_select_8_wd = reg_wdata[3]; + + assign dio_pad_attr_8_keeper_en_8_wd = reg_wdata[4]; + + assign dio_pad_attr_8_schmitt_en_8_wd = reg_wdata[5]; + + assign dio_pad_attr_8_od_en_8_wd = reg_wdata[6]; + + assign dio_pad_attr_8_input_disable_8_wd = reg_wdata[7]; + + assign dio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; + + assign dio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; + assign dio_pad_attr_9_re = addr_hit[139] & reg_re & !reg_error; + assign dio_pad_attr_9_we = addr_hit[139] & reg_we & !reg_error; + + assign dio_pad_attr_9_invert_9_wd = reg_wdata[0]; + + assign dio_pad_attr_9_virtual_od_en_9_wd = reg_wdata[1]; + + assign dio_pad_attr_9_pull_en_9_wd = reg_wdata[2]; + + assign dio_pad_attr_9_pull_select_9_wd = reg_wdata[3]; + + assign dio_pad_attr_9_keeper_en_9_wd = reg_wdata[4]; + + assign dio_pad_attr_9_schmitt_en_9_wd = reg_wdata[5]; + + assign dio_pad_attr_9_od_en_9_wd = reg_wdata[6]; + + assign dio_pad_attr_9_input_disable_9_wd = reg_wdata[7]; + + assign dio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; + + assign dio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; + assign dio_pad_attr_10_re = addr_hit[140] & reg_re & !reg_error; + assign dio_pad_attr_10_we = addr_hit[140] & reg_we & !reg_error; + + assign dio_pad_attr_10_invert_10_wd = reg_wdata[0]; + + assign dio_pad_attr_10_virtual_od_en_10_wd = reg_wdata[1]; + + assign dio_pad_attr_10_pull_en_10_wd = reg_wdata[2]; + + assign dio_pad_attr_10_pull_select_10_wd = reg_wdata[3]; + + assign dio_pad_attr_10_keeper_en_10_wd = reg_wdata[4]; + + assign dio_pad_attr_10_schmitt_en_10_wd = reg_wdata[5]; + + assign dio_pad_attr_10_od_en_10_wd = reg_wdata[6]; + + assign dio_pad_attr_10_input_disable_10_wd = reg_wdata[7]; + + assign dio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; + + assign dio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; + assign dio_pad_attr_11_re = addr_hit[141] & reg_re & !reg_error; + assign dio_pad_attr_11_we = addr_hit[141] & reg_we & !reg_error; + + assign dio_pad_attr_11_invert_11_wd = reg_wdata[0]; + + assign dio_pad_attr_11_virtual_od_en_11_wd = reg_wdata[1]; + + assign dio_pad_attr_11_pull_en_11_wd = reg_wdata[2]; + + assign dio_pad_attr_11_pull_select_11_wd = reg_wdata[3]; + + assign dio_pad_attr_11_keeper_en_11_wd = reg_wdata[4]; + + assign dio_pad_attr_11_schmitt_en_11_wd = reg_wdata[5]; + + assign dio_pad_attr_11_od_en_11_wd = reg_wdata[6]; + + assign dio_pad_attr_11_input_disable_11_wd = reg_wdata[7]; + + assign dio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; + + assign dio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; + assign dio_pad_attr_12_re = addr_hit[142] & reg_re & !reg_error; + assign dio_pad_attr_12_we = addr_hit[142] & reg_we & !reg_error; + + assign dio_pad_attr_12_invert_12_wd = reg_wdata[0]; + + assign dio_pad_attr_12_virtual_od_en_12_wd = reg_wdata[1]; + + assign dio_pad_attr_12_pull_en_12_wd = reg_wdata[2]; + + assign dio_pad_attr_12_pull_select_12_wd = reg_wdata[3]; + + assign dio_pad_attr_12_keeper_en_12_wd = reg_wdata[4]; + + assign dio_pad_attr_12_schmitt_en_12_wd = reg_wdata[5]; + + assign dio_pad_attr_12_od_en_12_wd = reg_wdata[6]; + + assign dio_pad_attr_12_input_disable_12_wd = reg_wdata[7]; + + assign dio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; + + assign dio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; + assign dio_pad_attr_13_re = addr_hit[143] & reg_re & !reg_error; + assign dio_pad_attr_13_we = addr_hit[143] & reg_we & !reg_error; + + assign dio_pad_attr_13_invert_13_wd = reg_wdata[0]; + + assign dio_pad_attr_13_virtual_od_en_13_wd = reg_wdata[1]; + + assign dio_pad_attr_13_pull_en_13_wd = reg_wdata[2]; + + assign dio_pad_attr_13_pull_select_13_wd = reg_wdata[3]; + + assign dio_pad_attr_13_keeper_en_13_wd = reg_wdata[4]; + + assign dio_pad_attr_13_schmitt_en_13_wd = reg_wdata[5]; + + assign dio_pad_attr_13_od_en_13_wd = reg_wdata[6]; + + assign dio_pad_attr_13_input_disable_13_wd = reg_wdata[7]; + + assign dio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; + + assign dio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; + assign dio_pad_attr_14_re = addr_hit[144] & reg_re & !reg_error; + assign dio_pad_attr_14_we = addr_hit[144] & reg_we & !reg_error; + + assign dio_pad_attr_14_invert_14_wd = reg_wdata[0]; + + assign dio_pad_attr_14_virtual_od_en_14_wd = reg_wdata[1]; + + assign dio_pad_attr_14_pull_en_14_wd = reg_wdata[2]; + + assign dio_pad_attr_14_pull_select_14_wd = reg_wdata[3]; + + assign dio_pad_attr_14_keeper_en_14_wd = reg_wdata[4]; + + assign dio_pad_attr_14_schmitt_en_14_wd = reg_wdata[5]; + + assign dio_pad_attr_14_od_en_14_wd = reg_wdata[6]; + + assign dio_pad_attr_14_input_disable_14_wd = reg_wdata[7]; + + assign dio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; + + assign dio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; + assign dio_pad_attr_15_re = addr_hit[145] & reg_re & !reg_error; + assign dio_pad_attr_15_we = addr_hit[145] & reg_we & !reg_error; + + assign dio_pad_attr_15_invert_15_wd = reg_wdata[0]; + + assign dio_pad_attr_15_virtual_od_en_15_wd = reg_wdata[1]; + + assign dio_pad_attr_15_pull_en_15_wd = reg_wdata[2]; + + assign dio_pad_attr_15_pull_select_15_wd = reg_wdata[3]; + + assign dio_pad_attr_15_keeper_en_15_wd = reg_wdata[4]; + + assign dio_pad_attr_15_schmitt_en_15_wd = reg_wdata[5]; + + assign dio_pad_attr_15_od_en_15_wd = reg_wdata[6]; + + assign dio_pad_attr_15_input_disable_15_wd = reg_wdata[7]; + + assign dio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; + + assign dio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; + assign dio_pad_attr_16_re = addr_hit[146] & reg_re & !reg_error; + assign dio_pad_attr_16_we = addr_hit[146] & reg_we & !reg_error; + + assign dio_pad_attr_16_invert_16_wd = reg_wdata[0]; + + assign dio_pad_attr_16_virtual_od_en_16_wd = reg_wdata[1]; + + assign dio_pad_attr_16_pull_en_16_wd = reg_wdata[2]; + + assign dio_pad_attr_16_pull_select_16_wd = reg_wdata[3]; + + assign dio_pad_attr_16_keeper_en_16_wd = reg_wdata[4]; + + assign dio_pad_attr_16_schmitt_en_16_wd = reg_wdata[5]; + + assign dio_pad_attr_16_od_en_16_wd = reg_wdata[6]; + + assign dio_pad_attr_16_input_disable_16_wd = reg_wdata[7]; + + assign dio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16]; + + assign dio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20]; + assign dio_pad_attr_17_re = addr_hit[147] & reg_re & !reg_error; + assign dio_pad_attr_17_we = addr_hit[147] & reg_we & !reg_error; + + assign dio_pad_attr_17_invert_17_wd = reg_wdata[0]; + + assign dio_pad_attr_17_virtual_od_en_17_wd = reg_wdata[1]; + + assign dio_pad_attr_17_pull_en_17_wd = reg_wdata[2]; + + assign dio_pad_attr_17_pull_select_17_wd = reg_wdata[3]; + + assign dio_pad_attr_17_keeper_en_17_wd = reg_wdata[4]; + + assign dio_pad_attr_17_schmitt_en_17_wd = reg_wdata[5]; + + assign dio_pad_attr_17_od_en_17_wd = reg_wdata[6]; + + assign dio_pad_attr_17_input_disable_17_wd = reg_wdata[7]; + + assign dio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16]; + + assign dio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20]; + assign dio_pad_attr_18_re = addr_hit[148] & reg_re & !reg_error; + assign dio_pad_attr_18_we = addr_hit[148] & reg_we & !reg_error; + + assign dio_pad_attr_18_invert_18_wd = reg_wdata[0]; + + assign dio_pad_attr_18_virtual_od_en_18_wd = reg_wdata[1]; + + assign dio_pad_attr_18_pull_en_18_wd = reg_wdata[2]; + + assign dio_pad_attr_18_pull_select_18_wd = reg_wdata[3]; + + assign dio_pad_attr_18_keeper_en_18_wd = reg_wdata[4]; + + assign dio_pad_attr_18_schmitt_en_18_wd = reg_wdata[5]; + + assign dio_pad_attr_18_od_en_18_wd = reg_wdata[6]; + + assign dio_pad_attr_18_input_disable_18_wd = reg_wdata[7]; + + assign dio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16]; + + assign dio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20]; + assign dio_pad_attr_19_re = addr_hit[149] & reg_re & !reg_error; + assign dio_pad_attr_19_we = addr_hit[149] & reg_we & !reg_error; + + assign dio_pad_attr_19_invert_19_wd = reg_wdata[0]; + + assign dio_pad_attr_19_virtual_od_en_19_wd = reg_wdata[1]; + + assign dio_pad_attr_19_pull_en_19_wd = reg_wdata[2]; + + assign dio_pad_attr_19_pull_select_19_wd = reg_wdata[3]; + + assign dio_pad_attr_19_keeper_en_19_wd = reg_wdata[4]; + + assign dio_pad_attr_19_schmitt_en_19_wd = reg_wdata[5]; + + assign dio_pad_attr_19_od_en_19_wd = reg_wdata[6]; + + assign dio_pad_attr_19_input_disable_19_wd = reg_wdata[7]; + + assign dio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16]; + + assign dio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20]; + assign dio_pad_attr_20_re = addr_hit[150] & reg_re & !reg_error; + assign dio_pad_attr_20_we = addr_hit[150] & reg_we & !reg_error; + + assign dio_pad_attr_20_invert_20_wd = reg_wdata[0]; + + assign dio_pad_attr_20_virtual_od_en_20_wd = reg_wdata[1]; + + assign dio_pad_attr_20_pull_en_20_wd = reg_wdata[2]; + + assign dio_pad_attr_20_pull_select_20_wd = reg_wdata[3]; + + assign dio_pad_attr_20_keeper_en_20_wd = reg_wdata[4]; + + assign dio_pad_attr_20_schmitt_en_20_wd = reg_wdata[5]; + + assign dio_pad_attr_20_od_en_20_wd = reg_wdata[6]; + + assign dio_pad_attr_20_input_disable_20_wd = reg_wdata[7]; + + assign dio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16]; + + assign dio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20]; + assign dio_pad_attr_21_re = addr_hit[151] & reg_re & !reg_error; + assign dio_pad_attr_21_we = addr_hit[151] & reg_we & !reg_error; + + assign dio_pad_attr_21_invert_21_wd = reg_wdata[0]; + + assign dio_pad_attr_21_virtual_od_en_21_wd = reg_wdata[1]; + + assign dio_pad_attr_21_pull_en_21_wd = reg_wdata[2]; + + assign dio_pad_attr_21_pull_select_21_wd = reg_wdata[3]; + + assign dio_pad_attr_21_keeper_en_21_wd = reg_wdata[4]; + + assign dio_pad_attr_21_schmitt_en_21_wd = reg_wdata[5]; + + assign dio_pad_attr_21_od_en_21_wd = reg_wdata[6]; + + assign dio_pad_attr_21_input_disable_21_wd = reg_wdata[7]; + + assign dio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16]; + + assign dio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20]; + assign dio_pad_attr_22_re = addr_hit[152] & reg_re & !reg_error; + assign dio_pad_attr_22_we = addr_hit[152] & reg_we & !reg_error; + + assign dio_pad_attr_22_invert_22_wd = reg_wdata[0]; + + assign dio_pad_attr_22_virtual_od_en_22_wd = reg_wdata[1]; + + assign dio_pad_attr_22_pull_en_22_wd = reg_wdata[2]; + + assign dio_pad_attr_22_pull_select_22_wd = reg_wdata[3]; + + assign dio_pad_attr_22_keeper_en_22_wd = reg_wdata[4]; + + assign dio_pad_attr_22_schmitt_en_22_wd = reg_wdata[5]; + + assign dio_pad_attr_22_od_en_22_wd = reg_wdata[6]; + + assign dio_pad_attr_22_input_disable_22_wd = reg_wdata[7]; + + assign dio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16]; + + assign dio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20]; + assign dio_pad_attr_23_re = addr_hit[153] & reg_re & !reg_error; + assign dio_pad_attr_23_we = addr_hit[153] & reg_we & !reg_error; + + assign dio_pad_attr_23_invert_23_wd = reg_wdata[0]; + + assign dio_pad_attr_23_virtual_od_en_23_wd = reg_wdata[1]; + + assign dio_pad_attr_23_pull_en_23_wd = reg_wdata[2]; + + assign dio_pad_attr_23_pull_select_23_wd = reg_wdata[3]; + + assign dio_pad_attr_23_keeper_en_23_wd = reg_wdata[4]; + + assign dio_pad_attr_23_schmitt_en_23_wd = reg_wdata[5]; + + assign dio_pad_attr_23_od_en_23_wd = reg_wdata[6]; + + assign dio_pad_attr_23_input_disable_23_wd = reg_wdata[7]; + + assign dio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16]; + + assign dio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20]; + assign dio_pad_attr_24_re = addr_hit[154] & reg_re & !reg_error; + assign dio_pad_attr_24_we = addr_hit[154] & reg_we & !reg_error; + + assign dio_pad_attr_24_invert_24_wd = reg_wdata[0]; + + assign dio_pad_attr_24_virtual_od_en_24_wd = reg_wdata[1]; + + assign dio_pad_attr_24_pull_en_24_wd = reg_wdata[2]; + + assign dio_pad_attr_24_pull_select_24_wd = reg_wdata[3]; + + assign dio_pad_attr_24_keeper_en_24_wd = reg_wdata[4]; + + assign dio_pad_attr_24_schmitt_en_24_wd = reg_wdata[5]; + + assign dio_pad_attr_24_od_en_24_wd = reg_wdata[6]; + + assign dio_pad_attr_24_input_disable_24_wd = reg_wdata[7]; + + assign dio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16]; + + assign dio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20]; + assign dio_pad_attr_25_re = addr_hit[155] & reg_re & !reg_error; + assign dio_pad_attr_25_we = addr_hit[155] & reg_we & !reg_error; + + assign dio_pad_attr_25_invert_25_wd = reg_wdata[0]; + + assign dio_pad_attr_25_virtual_od_en_25_wd = reg_wdata[1]; + + assign dio_pad_attr_25_pull_en_25_wd = reg_wdata[2]; + + assign dio_pad_attr_25_pull_select_25_wd = reg_wdata[3]; + + assign dio_pad_attr_25_keeper_en_25_wd = reg_wdata[4]; + + assign dio_pad_attr_25_schmitt_en_25_wd = reg_wdata[5]; + + assign dio_pad_attr_25_od_en_25_wd = reg_wdata[6]; + + assign dio_pad_attr_25_input_disable_25_wd = reg_wdata[7]; + + assign dio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16]; + + assign dio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20]; + assign dio_pad_attr_26_re = addr_hit[156] & reg_re & !reg_error; + assign dio_pad_attr_26_we = addr_hit[156] & reg_we & !reg_error; + + assign dio_pad_attr_26_invert_26_wd = reg_wdata[0]; + + assign dio_pad_attr_26_virtual_od_en_26_wd = reg_wdata[1]; + + assign dio_pad_attr_26_pull_en_26_wd = reg_wdata[2]; + + assign dio_pad_attr_26_pull_select_26_wd = reg_wdata[3]; + + assign dio_pad_attr_26_keeper_en_26_wd = reg_wdata[4]; + + assign dio_pad_attr_26_schmitt_en_26_wd = reg_wdata[5]; + + assign dio_pad_attr_26_od_en_26_wd = reg_wdata[6]; + + assign dio_pad_attr_26_input_disable_26_wd = reg_wdata[7]; + + assign dio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16]; + + assign dio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20]; + assign dio_pad_attr_27_re = addr_hit[157] & reg_re & !reg_error; + assign dio_pad_attr_27_we = addr_hit[157] & reg_we & !reg_error; + + assign dio_pad_attr_27_invert_27_wd = reg_wdata[0]; + + assign dio_pad_attr_27_virtual_od_en_27_wd = reg_wdata[1]; + + assign dio_pad_attr_27_pull_en_27_wd = reg_wdata[2]; + + assign dio_pad_attr_27_pull_select_27_wd = reg_wdata[3]; + + assign dio_pad_attr_27_keeper_en_27_wd = reg_wdata[4]; + + assign dio_pad_attr_27_schmitt_en_27_wd = reg_wdata[5]; + + assign dio_pad_attr_27_od_en_27_wd = reg_wdata[6]; + + assign dio_pad_attr_27_input_disable_27_wd = reg_wdata[7]; + + assign dio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16]; + + assign dio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20]; + assign dio_pad_attr_28_re = addr_hit[158] & reg_re & !reg_error; + assign dio_pad_attr_28_we = addr_hit[158] & reg_we & !reg_error; + + assign dio_pad_attr_28_invert_28_wd = reg_wdata[0]; + + assign dio_pad_attr_28_virtual_od_en_28_wd = reg_wdata[1]; + + assign dio_pad_attr_28_pull_en_28_wd = reg_wdata[2]; + + assign dio_pad_attr_28_pull_select_28_wd = reg_wdata[3]; + + assign dio_pad_attr_28_keeper_en_28_wd = reg_wdata[4]; + + assign dio_pad_attr_28_schmitt_en_28_wd = reg_wdata[5]; + + assign dio_pad_attr_28_od_en_28_wd = reg_wdata[6]; + + assign dio_pad_attr_28_input_disable_28_wd = reg_wdata[7]; + + assign dio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16]; + + assign dio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20]; + assign dio_pad_attr_29_re = addr_hit[159] & reg_re & !reg_error; + assign dio_pad_attr_29_we = addr_hit[159] & reg_we & !reg_error; + + assign dio_pad_attr_29_invert_29_wd = reg_wdata[0]; + + assign dio_pad_attr_29_virtual_od_en_29_wd = reg_wdata[1]; + + assign dio_pad_attr_29_pull_en_29_wd = reg_wdata[2]; + + assign dio_pad_attr_29_pull_select_29_wd = reg_wdata[3]; + + assign dio_pad_attr_29_keeper_en_29_wd = reg_wdata[4]; + + assign dio_pad_attr_29_schmitt_en_29_wd = reg_wdata[5]; + + assign dio_pad_attr_29_od_en_29_wd = reg_wdata[6]; + + assign dio_pad_attr_29_input_disable_29_wd = reg_wdata[7]; + + assign dio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16]; + + assign dio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20]; + assign dio_pad_attr_30_re = addr_hit[160] & reg_re & !reg_error; + assign dio_pad_attr_30_we = addr_hit[160] & reg_we & !reg_error; + + assign dio_pad_attr_30_invert_30_wd = reg_wdata[0]; + + assign dio_pad_attr_30_virtual_od_en_30_wd = reg_wdata[1]; + + assign dio_pad_attr_30_pull_en_30_wd = reg_wdata[2]; + + assign dio_pad_attr_30_pull_select_30_wd = reg_wdata[3]; + + assign dio_pad_attr_30_keeper_en_30_wd = reg_wdata[4]; + + assign dio_pad_attr_30_schmitt_en_30_wd = reg_wdata[5]; + + assign dio_pad_attr_30_od_en_30_wd = reg_wdata[6]; + + assign dio_pad_attr_30_input_disable_30_wd = reg_wdata[7]; + + assign dio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16]; + + assign dio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20]; + assign dio_pad_attr_31_re = addr_hit[161] & reg_re & !reg_error; + assign dio_pad_attr_31_we = addr_hit[161] & reg_we & !reg_error; + + assign dio_pad_attr_31_invert_31_wd = reg_wdata[0]; + + assign dio_pad_attr_31_virtual_od_en_31_wd = reg_wdata[1]; + + assign dio_pad_attr_31_pull_en_31_wd = reg_wdata[2]; + + assign dio_pad_attr_31_pull_select_31_wd = reg_wdata[3]; + + assign dio_pad_attr_31_keeper_en_31_wd = reg_wdata[4]; + + assign dio_pad_attr_31_schmitt_en_31_wd = reg_wdata[5]; + + assign dio_pad_attr_31_od_en_31_wd = reg_wdata[6]; + + assign dio_pad_attr_31_input_disable_31_wd = reg_wdata[7]; + + assign dio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16]; + + assign dio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20]; + assign dio_pad_attr_32_re = addr_hit[162] & reg_re & !reg_error; + assign dio_pad_attr_32_we = addr_hit[162] & reg_we & !reg_error; + + assign dio_pad_attr_32_invert_32_wd = reg_wdata[0]; + + assign dio_pad_attr_32_virtual_od_en_32_wd = reg_wdata[1]; + + assign dio_pad_attr_32_pull_en_32_wd = reg_wdata[2]; + + assign dio_pad_attr_32_pull_select_32_wd = reg_wdata[3]; + + assign dio_pad_attr_32_keeper_en_32_wd = reg_wdata[4]; + + assign dio_pad_attr_32_schmitt_en_32_wd = reg_wdata[5]; + + assign dio_pad_attr_32_od_en_32_wd = reg_wdata[6]; + + assign dio_pad_attr_32_input_disable_32_wd = reg_wdata[7]; + + assign dio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16]; + + assign dio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20]; + assign dio_pad_attr_33_re = addr_hit[163] & reg_re & !reg_error; + assign dio_pad_attr_33_we = addr_hit[163] & reg_we & !reg_error; + + assign dio_pad_attr_33_invert_33_wd = reg_wdata[0]; + + assign dio_pad_attr_33_virtual_od_en_33_wd = reg_wdata[1]; + + assign dio_pad_attr_33_pull_en_33_wd = reg_wdata[2]; + + assign dio_pad_attr_33_pull_select_33_wd = reg_wdata[3]; + + assign dio_pad_attr_33_keeper_en_33_wd = reg_wdata[4]; + + assign dio_pad_attr_33_schmitt_en_33_wd = reg_wdata[5]; + + assign dio_pad_attr_33_od_en_33_wd = reg_wdata[6]; + + assign dio_pad_attr_33_input_disable_33_wd = reg_wdata[7]; + + assign dio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16]; + + assign dio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20]; + assign dio_pad_attr_34_re = addr_hit[164] & reg_re & !reg_error; + assign dio_pad_attr_34_we = addr_hit[164] & reg_we & !reg_error; + + assign dio_pad_attr_34_invert_34_wd = reg_wdata[0]; + + assign dio_pad_attr_34_virtual_od_en_34_wd = reg_wdata[1]; + + assign dio_pad_attr_34_pull_en_34_wd = reg_wdata[2]; + + assign dio_pad_attr_34_pull_select_34_wd = reg_wdata[3]; + + assign dio_pad_attr_34_keeper_en_34_wd = reg_wdata[4]; + + assign dio_pad_attr_34_schmitt_en_34_wd = reg_wdata[5]; + + assign dio_pad_attr_34_od_en_34_wd = reg_wdata[6]; + + assign dio_pad_attr_34_input_disable_34_wd = reg_wdata[7]; + + assign dio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16]; + + assign dio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20]; + assign dio_pad_attr_35_re = addr_hit[165] & reg_re & !reg_error; + assign dio_pad_attr_35_we = addr_hit[165] & reg_we & !reg_error; + + assign dio_pad_attr_35_invert_35_wd = reg_wdata[0]; + + assign dio_pad_attr_35_virtual_od_en_35_wd = reg_wdata[1]; + + assign dio_pad_attr_35_pull_en_35_wd = reg_wdata[2]; + + assign dio_pad_attr_35_pull_select_35_wd = reg_wdata[3]; + + assign dio_pad_attr_35_keeper_en_35_wd = reg_wdata[4]; + + assign dio_pad_attr_35_schmitt_en_35_wd = reg_wdata[5]; + + assign dio_pad_attr_35_od_en_35_wd = reg_wdata[6]; + + assign dio_pad_attr_35_input_disable_35_wd = reg_wdata[7]; + + assign dio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16]; + + assign dio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20]; + assign dio_pad_attr_36_re = addr_hit[166] & reg_re & !reg_error; + assign dio_pad_attr_36_we = addr_hit[166] & reg_we & !reg_error; + + assign dio_pad_attr_36_invert_36_wd = reg_wdata[0]; + + assign dio_pad_attr_36_virtual_od_en_36_wd = reg_wdata[1]; + + assign dio_pad_attr_36_pull_en_36_wd = reg_wdata[2]; + + assign dio_pad_attr_36_pull_select_36_wd = reg_wdata[3]; + + assign dio_pad_attr_36_keeper_en_36_wd = reg_wdata[4]; + + assign dio_pad_attr_36_schmitt_en_36_wd = reg_wdata[5]; + + assign dio_pad_attr_36_od_en_36_wd = reg_wdata[6]; + + assign dio_pad_attr_36_input_disable_36_wd = reg_wdata[7]; + + assign dio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16]; + + assign dio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20]; + assign dio_pad_attr_37_re = addr_hit[167] & reg_re & !reg_error; + assign dio_pad_attr_37_we = addr_hit[167] & reg_we & !reg_error; + + assign dio_pad_attr_37_invert_37_wd = reg_wdata[0]; + + assign dio_pad_attr_37_virtual_od_en_37_wd = reg_wdata[1]; + + assign dio_pad_attr_37_pull_en_37_wd = reg_wdata[2]; + + assign dio_pad_attr_37_pull_select_37_wd = reg_wdata[3]; + + assign dio_pad_attr_37_keeper_en_37_wd = reg_wdata[4]; + + assign dio_pad_attr_37_schmitt_en_37_wd = reg_wdata[5]; + + assign dio_pad_attr_37_od_en_37_wd = reg_wdata[6]; + + assign dio_pad_attr_37_input_disable_37_wd = reg_wdata[7]; + + assign dio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16]; + + assign dio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20]; + assign dio_pad_attr_38_re = addr_hit[168] & reg_re & !reg_error; + assign dio_pad_attr_38_we = addr_hit[168] & reg_we & !reg_error; + + assign dio_pad_attr_38_invert_38_wd = reg_wdata[0]; + + assign dio_pad_attr_38_virtual_od_en_38_wd = reg_wdata[1]; + + assign dio_pad_attr_38_pull_en_38_wd = reg_wdata[2]; + + assign dio_pad_attr_38_pull_select_38_wd = reg_wdata[3]; + + assign dio_pad_attr_38_keeper_en_38_wd = reg_wdata[4]; + + assign dio_pad_attr_38_schmitt_en_38_wd = reg_wdata[5]; + + assign dio_pad_attr_38_od_en_38_wd = reg_wdata[6]; + + assign dio_pad_attr_38_input_disable_38_wd = reg_wdata[7]; + + assign dio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16]; + + assign dio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20]; + assign dio_pad_attr_39_re = addr_hit[169] & reg_re & !reg_error; + assign dio_pad_attr_39_we = addr_hit[169] & reg_we & !reg_error; + + assign dio_pad_attr_39_invert_39_wd = reg_wdata[0]; + + assign dio_pad_attr_39_virtual_od_en_39_wd = reg_wdata[1]; + + assign dio_pad_attr_39_pull_en_39_wd = reg_wdata[2]; + + assign dio_pad_attr_39_pull_select_39_wd = reg_wdata[3]; + + assign dio_pad_attr_39_keeper_en_39_wd = reg_wdata[4]; + + assign dio_pad_attr_39_schmitt_en_39_wd = reg_wdata[5]; + + assign dio_pad_attr_39_od_en_39_wd = reg_wdata[6]; + + assign dio_pad_attr_39_input_disable_39_wd = reg_wdata[7]; + + assign dio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16]; + + assign dio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20]; + assign dio_pad_attr_40_re = addr_hit[170] & reg_re & !reg_error; + assign dio_pad_attr_40_we = addr_hit[170] & reg_we & !reg_error; + + assign dio_pad_attr_40_invert_40_wd = reg_wdata[0]; + + assign dio_pad_attr_40_virtual_od_en_40_wd = reg_wdata[1]; + + assign dio_pad_attr_40_pull_en_40_wd = reg_wdata[2]; + + assign dio_pad_attr_40_pull_select_40_wd = reg_wdata[3]; + + assign dio_pad_attr_40_keeper_en_40_wd = reg_wdata[4]; + + assign dio_pad_attr_40_schmitt_en_40_wd = reg_wdata[5]; + + assign dio_pad_attr_40_od_en_40_wd = reg_wdata[6]; + + assign dio_pad_attr_40_input_disable_40_wd = reg_wdata[7]; + + assign dio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16]; + + assign dio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20]; + assign dio_pad_attr_41_re = addr_hit[171] & reg_re & !reg_error; + assign dio_pad_attr_41_we = addr_hit[171] & reg_we & !reg_error; + + assign dio_pad_attr_41_invert_41_wd = reg_wdata[0]; + + assign dio_pad_attr_41_virtual_od_en_41_wd = reg_wdata[1]; + + assign dio_pad_attr_41_pull_en_41_wd = reg_wdata[2]; + + assign dio_pad_attr_41_pull_select_41_wd = reg_wdata[3]; + + assign dio_pad_attr_41_keeper_en_41_wd = reg_wdata[4]; + + assign dio_pad_attr_41_schmitt_en_41_wd = reg_wdata[5]; + + assign dio_pad_attr_41_od_en_41_wd = reg_wdata[6]; + + assign dio_pad_attr_41_input_disable_41_wd = reg_wdata[7]; + + assign dio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16]; + + assign dio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20]; + assign dio_pad_attr_42_re = addr_hit[172] & reg_re & !reg_error; + assign dio_pad_attr_42_we = addr_hit[172] & reg_we & !reg_error; + + assign dio_pad_attr_42_invert_42_wd = reg_wdata[0]; + + assign dio_pad_attr_42_virtual_od_en_42_wd = reg_wdata[1]; + + assign dio_pad_attr_42_pull_en_42_wd = reg_wdata[2]; + + assign dio_pad_attr_42_pull_select_42_wd = reg_wdata[3]; + + assign dio_pad_attr_42_keeper_en_42_wd = reg_wdata[4]; + + assign dio_pad_attr_42_schmitt_en_42_wd = reg_wdata[5]; + + assign dio_pad_attr_42_od_en_42_wd = reg_wdata[6]; + + assign dio_pad_attr_42_input_disable_42_wd = reg_wdata[7]; + + assign dio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16]; + + assign dio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20]; + assign dio_pad_attr_43_re = addr_hit[173] & reg_re & !reg_error; + assign dio_pad_attr_43_we = addr_hit[173] & reg_we & !reg_error; + + assign dio_pad_attr_43_invert_43_wd = reg_wdata[0]; + + assign dio_pad_attr_43_virtual_od_en_43_wd = reg_wdata[1]; + + assign dio_pad_attr_43_pull_en_43_wd = reg_wdata[2]; + + assign dio_pad_attr_43_pull_select_43_wd = reg_wdata[3]; + + assign dio_pad_attr_43_keeper_en_43_wd = reg_wdata[4]; + + assign dio_pad_attr_43_schmitt_en_43_wd = reg_wdata[5]; + + assign dio_pad_attr_43_od_en_43_wd = reg_wdata[6]; + + assign dio_pad_attr_43_input_disable_43_wd = reg_wdata[7]; + + assign dio_pad_attr_43_slew_rate_43_wd = reg_wdata[17:16]; + + assign dio_pad_attr_43_drive_strength_43_wd = reg_wdata[23:20]; + assign dio_pad_attr_44_re = addr_hit[174] & reg_re & !reg_error; + assign dio_pad_attr_44_we = addr_hit[174] & reg_we & !reg_error; + + assign dio_pad_attr_44_invert_44_wd = reg_wdata[0]; + + assign dio_pad_attr_44_virtual_od_en_44_wd = reg_wdata[1]; + + assign dio_pad_attr_44_pull_en_44_wd = reg_wdata[2]; + + assign dio_pad_attr_44_pull_select_44_wd = reg_wdata[3]; + + assign dio_pad_attr_44_keeper_en_44_wd = reg_wdata[4]; + + assign dio_pad_attr_44_schmitt_en_44_wd = reg_wdata[5]; + + assign dio_pad_attr_44_od_en_44_wd = reg_wdata[6]; + + assign dio_pad_attr_44_input_disable_44_wd = reg_wdata[7]; + + assign dio_pad_attr_44_slew_rate_44_wd = reg_wdata[17:16]; + + assign dio_pad_attr_44_drive_strength_44_wd = reg_wdata[23:20]; + assign dio_pad_attr_45_re = addr_hit[175] & reg_re & !reg_error; + assign dio_pad_attr_45_we = addr_hit[175] & reg_we & !reg_error; + + assign dio_pad_attr_45_invert_45_wd = reg_wdata[0]; + + assign dio_pad_attr_45_virtual_od_en_45_wd = reg_wdata[1]; + + assign dio_pad_attr_45_pull_en_45_wd = reg_wdata[2]; + + assign dio_pad_attr_45_pull_select_45_wd = reg_wdata[3]; + + assign dio_pad_attr_45_keeper_en_45_wd = reg_wdata[4]; + + assign dio_pad_attr_45_schmitt_en_45_wd = reg_wdata[5]; + + assign dio_pad_attr_45_od_en_45_wd = reg_wdata[6]; + + assign dio_pad_attr_45_input_disable_45_wd = reg_wdata[7]; + + assign dio_pad_attr_45_slew_rate_45_wd = reg_wdata[17:16]; + + assign dio_pad_attr_45_drive_strength_45_wd = reg_wdata[23:20]; + assign dio_pad_attr_46_re = addr_hit[176] & reg_re & !reg_error; + assign dio_pad_attr_46_we = addr_hit[176] & reg_we & !reg_error; + + assign dio_pad_attr_46_invert_46_wd = reg_wdata[0]; + + assign dio_pad_attr_46_virtual_od_en_46_wd = reg_wdata[1]; + + assign dio_pad_attr_46_pull_en_46_wd = reg_wdata[2]; + + assign dio_pad_attr_46_pull_select_46_wd = reg_wdata[3]; + + assign dio_pad_attr_46_keeper_en_46_wd = reg_wdata[4]; + + assign dio_pad_attr_46_schmitt_en_46_wd = reg_wdata[5]; + + assign dio_pad_attr_46_od_en_46_wd = reg_wdata[6]; + + assign dio_pad_attr_46_input_disable_46_wd = reg_wdata[7]; + + assign dio_pad_attr_46_slew_rate_46_wd = reg_wdata[17:16]; + + assign dio_pad_attr_46_drive_strength_46_wd = reg_wdata[23:20]; + assign dio_pad_attr_47_re = addr_hit[177] & reg_re & !reg_error; + assign dio_pad_attr_47_we = addr_hit[177] & reg_we & !reg_error; + + assign dio_pad_attr_47_invert_47_wd = reg_wdata[0]; + + assign dio_pad_attr_47_virtual_od_en_47_wd = reg_wdata[1]; + + assign dio_pad_attr_47_pull_en_47_wd = reg_wdata[2]; + + assign dio_pad_attr_47_pull_select_47_wd = reg_wdata[3]; + + assign dio_pad_attr_47_keeper_en_47_wd = reg_wdata[4]; + + assign dio_pad_attr_47_schmitt_en_47_wd = reg_wdata[5]; + + assign dio_pad_attr_47_od_en_47_wd = reg_wdata[6]; + + assign dio_pad_attr_47_input_disable_47_wd = reg_wdata[7]; + + assign dio_pad_attr_47_slew_rate_47_wd = reg_wdata[17:16]; + + assign dio_pad_attr_47_drive_strength_47_wd = reg_wdata[23:20]; + assign dio_pad_attr_48_re = addr_hit[178] & reg_re & !reg_error; + assign dio_pad_attr_48_we = addr_hit[178] & reg_we & !reg_error; + + assign dio_pad_attr_48_invert_48_wd = reg_wdata[0]; + + assign dio_pad_attr_48_virtual_od_en_48_wd = reg_wdata[1]; + + assign dio_pad_attr_48_pull_en_48_wd = reg_wdata[2]; + + assign dio_pad_attr_48_pull_select_48_wd = reg_wdata[3]; + + assign dio_pad_attr_48_keeper_en_48_wd = reg_wdata[4]; + + assign dio_pad_attr_48_schmitt_en_48_wd = reg_wdata[5]; + + assign dio_pad_attr_48_od_en_48_wd = reg_wdata[6]; + + assign dio_pad_attr_48_input_disable_48_wd = reg_wdata[7]; + + assign dio_pad_attr_48_slew_rate_48_wd = reg_wdata[17:16]; + + assign dio_pad_attr_48_drive_strength_48_wd = reg_wdata[23:20]; + assign dio_pad_attr_49_re = addr_hit[179] & reg_re & !reg_error; + assign dio_pad_attr_49_we = addr_hit[179] & reg_we & !reg_error; + + assign dio_pad_attr_49_invert_49_wd = reg_wdata[0]; + + assign dio_pad_attr_49_virtual_od_en_49_wd = reg_wdata[1]; + + assign dio_pad_attr_49_pull_en_49_wd = reg_wdata[2]; + + assign dio_pad_attr_49_pull_select_49_wd = reg_wdata[3]; + + assign dio_pad_attr_49_keeper_en_49_wd = reg_wdata[4]; + + assign dio_pad_attr_49_schmitt_en_49_wd = reg_wdata[5]; + + assign dio_pad_attr_49_od_en_49_wd = reg_wdata[6]; + + assign dio_pad_attr_49_input_disable_49_wd = reg_wdata[7]; + + assign dio_pad_attr_49_slew_rate_49_wd = reg_wdata[17:16]; + + assign dio_pad_attr_49_drive_strength_49_wd = reg_wdata[23:20]; + assign dio_pad_attr_50_re = addr_hit[180] & reg_re & !reg_error; + assign dio_pad_attr_50_we = addr_hit[180] & reg_we & !reg_error; + + assign dio_pad_attr_50_invert_50_wd = reg_wdata[0]; + + assign dio_pad_attr_50_virtual_od_en_50_wd = reg_wdata[1]; + + assign dio_pad_attr_50_pull_en_50_wd = reg_wdata[2]; + + assign dio_pad_attr_50_pull_select_50_wd = reg_wdata[3]; + + assign dio_pad_attr_50_keeper_en_50_wd = reg_wdata[4]; + + assign dio_pad_attr_50_schmitt_en_50_wd = reg_wdata[5]; + + assign dio_pad_attr_50_od_en_50_wd = reg_wdata[6]; + + assign dio_pad_attr_50_input_disable_50_wd = reg_wdata[7]; + + assign dio_pad_attr_50_slew_rate_50_wd = reg_wdata[17:16]; + + assign dio_pad_attr_50_drive_strength_50_wd = reg_wdata[23:20]; + assign dio_pad_attr_51_re = addr_hit[181] & reg_re & !reg_error; + assign dio_pad_attr_51_we = addr_hit[181] & reg_we & !reg_error; + + assign dio_pad_attr_51_invert_51_wd = reg_wdata[0]; + + assign dio_pad_attr_51_virtual_od_en_51_wd = reg_wdata[1]; + + assign dio_pad_attr_51_pull_en_51_wd = reg_wdata[2]; + + assign dio_pad_attr_51_pull_select_51_wd = reg_wdata[3]; + + assign dio_pad_attr_51_keeper_en_51_wd = reg_wdata[4]; + + assign dio_pad_attr_51_schmitt_en_51_wd = reg_wdata[5]; + + assign dio_pad_attr_51_od_en_51_wd = reg_wdata[6]; + + assign dio_pad_attr_51_input_disable_51_wd = reg_wdata[7]; + + assign dio_pad_attr_51_slew_rate_51_wd = reg_wdata[17:16]; + + assign dio_pad_attr_51_drive_strength_51_wd = reg_wdata[23:20]; + assign dio_pad_attr_52_re = addr_hit[182] & reg_re & !reg_error; + assign dio_pad_attr_52_we = addr_hit[182] & reg_we & !reg_error; + + assign dio_pad_attr_52_invert_52_wd = reg_wdata[0]; + + assign dio_pad_attr_52_virtual_od_en_52_wd = reg_wdata[1]; + + assign dio_pad_attr_52_pull_en_52_wd = reg_wdata[2]; + + assign dio_pad_attr_52_pull_select_52_wd = reg_wdata[3]; + + assign dio_pad_attr_52_keeper_en_52_wd = reg_wdata[4]; + + assign dio_pad_attr_52_schmitt_en_52_wd = reg_wdata[5]; + + assign dio_pad_attr_52_od_en_52_wd = reg_wdata[6]; + + assign dio_pad_attr_52_input_disable_52_wd = reg_wdata[7]; + + assign dio_pad_attr_52_slew_rate_52_wd = reg_wdata[17:16]; + + assign dio_pad_attr_52_drive_strength_52_wd = reg_wdata[23:20]; + assign dio_pad_attr_53_re = addr_hit[183] & reg_re & !reg_error; + assign dio_pad_attr_53_we = addr_hit[183] & reg_we & !reg_error; + + assign dio_pad_attr_53_invert_53_wd = reg_wdata[0]; + + assign dio_pad_attr_53_virtual_od_en_53_wd = reg_wdata[1]; + + assign dio_pad_attr_53_pull_en_53_wd = reg_wdata[2]; + + assign dio_pad_attr_53_pull_select_53_wd = reg_wdata[3]; + + assign dio_pad_attr_53_keeper_en_53_wd = reg_wdata[4]; + + assign dio_pad_attr_53_schmitt_en_53_wd = reg_wdata[5]; + + assign dio_pad_attr_53_od_en_53_wd = reg_wdata[6]; + + assign dio_pad_attr_53_input_disable_53_wd = reg_wdata[7]; + + assign dio_pad_attr_53_slew_rate_53_wd = reg_wdata[17:16]; + + assign dio_pad_attr_53_drive_strength_53_wd = reg_wdata[23:20]; + assign dio_pad_attr_54_re = addr_hit[184] & reg_re & !reg_error; + assign dio_pad_attr_54_we = addr_hit[184] & reg_we & !reg_error; + + assign dio_pad_attr_54_invert_54_wd = reg_wdata[0]; + + assign dio_pad_attr_54_virtual_od_en_54_wd = reg_wdata[1]; + + assign dio_pad_attr_54_pull_en_54_wd = reg_wdata[2]; + + assign dio_pad_attr_54_pull_select_54_wd = reg_wdata[3]; + + assign dio_pad_attr_54_keeper_en_54_wd = reg_wdata[4]; + + assign dio_pad_attr_54_schmitt_en_54_wd = reg_wdata[5]; + + assign dio_pad_attr_54_od_en_54_wd = reg_wdata[6]; + + assign dio_pad_attr_54_input_disable_54_wd = reg_wdata[7]; + + assign dio_pad_attr_54_slew_rate_54_wd = reg_wdata[17:16]; + + assign dio_pad_attr_54_drive_strength_54_wd = reg_wdata[23:20]; + assign dio_pad_attr_55_re = addr_hit[185] & reg_re & !reg_error; + assign dio_pad_attr_55_we = addr_hit[185] & reg_we & !reg_error; + + assign dio_pad_attr_55_invert_55_wd = reg_wdata[0]; + + assign dio_pad_attr_55_virtual_od_en_55_wd = reg_wdata[1]; + + assign dio_pad_attr_55_pull_en_55_wd = reg_wdata[2]; + + assign dio_pad_attr_55_pull_select_55_wd = reg_wdata[3]; + + assign dio_pad_attr_55_keeper_en_55_wd = reg_wdata[4]; + + assign dio_pad_attr_55_schmitt_en_55_wd = reg_wdata[5]; + + assign dio_pad_attr_55_od_en_55_wd = reg_wdata[6]; + + assign dio_pad_attr_55_input_disable_55_wd = reg_wdata[7]; + + assign dio_pad_attr_55_slew_rate_55_wd = reg_wdata[17:16]; + + assign dio_pad_attr_55_drive_strength_55_wd = reg_wdata[23:20]; + assign dio_pad_attr_56_re = addr_hit[186] & reg_re & !reg_error; + assign dio_pad_attr_56_we = addr_hit[186] & reg_we & !reg_error; + + assign dio_pad_attr_56_invert_56_wd = reg_wdata[0]; + + assign dio_pad_attr_56_virtual_od_en_56_wd = reg_wdata[1]; + + assign dio_pad_attr_56_pull_en_56_wd = reg_wdata[2]; + + assign dio_pad_attr_56_pull_select_56_wd = reg_wdata[3]; + + assign dio_pad_attr_56_keeper_en_56_wd = reg_wdata[4]; + + assign dio_pad_attr_56_schmitt_en_56_wd = reg_wdata[5]; + + assign dio_pad_attr_56_od_en_56_wd = reg_wdata[6]; + + assign dio_pad_attr_56_input_disable_56_wd = reg_wdata[7]; + + assign dio_pad_attr_56_slew_rate_56_wd = reg_wdata[17:16]; + + assign dio_pad_attr_56_drive_strength_56_wd = reg_wdata[23:20]; + assign dio_pad_attr_57_re = addr_hit[187] & reg_re & !reg_error; + assign dio_pad_attr_57_we = addr_hit[187] & reg_we & !reg_error; + + assign dio_pad_attr_57_invert_57_wd = reg_wdata[0]; + + assign dio_pad_attr_57_virtual_od_en_57_wd = reg_wdata[1]; + + assign dio_pad_attr_57_pull_en_57_wd = reg_wdata[2]; + + assign dio_pad_attr_57_pull_select_57_wd = reg_wdata[3]; + + assign dio_pad_attr_57_keeper_en_57_wd = reg_wdata[4]; + + assign dio_pad_attr_57_schmitt_en_57_wd = reg_wdata[5]; + + assign dio_pad_attr_57_od_en_57_wd = reg_wdata[6]; + + assign dio_pad_attr_57_input_disable_57_wd = reg_wdata[7]; + + assign dio_pad_attr_57_slew_rate_57_wd = reg_wdata[17:16]; + + assign dio_pad_attr_57_drive_strength_57_wd = reg_wdata[23:20]; + assign dio_pad_attr_58_re = addr_hit[188] & reg_re & !reg_error; + assign dio_pad_attr_58_we = addr_hit[188] & reg_we & !reg_error; + + assign dio_pad_attr_58_invert_58_wd = reg_wdata[0]; + + assign dio_pad_attr_58_virtual_od_en_58_wd = reg_wdata[1]; + + assign dio_pad_attr_58_pull_en_58_wd = reg_wdata[2]; + + assign dio_pad_attr_58_pull_select_58_wd = reg_wdata[3]; + + assign dio_pad_attr_58_keeper_en_58_wd = reg_wdata[4]; + + assign dio_pad_attr_58_schmitt_en_58_wd = reg_wdata[5]; + + assign dio_pad_attr_58_od_en_58_wd = reg_wdata[6]; + + assign dio_pad_attr_58_input_disable_58_wd = reg_wdata[7]; + + assign dio_pad_attr_58_slew_rate_58_wd = reg_wdata[17:16]; + + assign dio_pad_attr_58_drive_strength_58_wd = reg_wdata[23:20]; + assign dio_pad_attr_59_re = addr_hit[189] & reg_re & !reg_error; + assign dio_pad_attr_59_we = addr_hit[189] & reg_we & !reg_error; + + assign dio_pad_attr_59_invert_59_wd = reg_wdata[0]; + + assign dio_pad_attr_59_virtual_od_en_59_wd = reg_wdata[1]; + + assign dio_pad_attr_59_pull_en_59_wd = reg_wdata[2]; + + assign dio_pad_attr_59_pull_select_59_wd = reg_wdata[3]; + + assign dio_pad_attr_59_keeper_en_59_wd = reg_wdata[4]; + + assign dio_pad_attr_59_schmitt_en_59_wd = reg_wdata[5]; + + assign dio_pad_attr_59_od_en_59_wd = reg_wdata[6]; + + assign dio_pad_attr_59_input_disable_59_wd = reg_wdata[7]; + + assign dio_pad_attr_59_slew_rate_59_wd = reg_wdata[17:16]; + + assign dio_pad_attr_59_drive_strength_59_wd = reg_wdata[23:20]; + assign dio_pad_attr_60_re = addr_hit[190] & reg_re & !reg_error; + assign dio_pad_attr_60_we = addr_hit[190] & reg_we & !reg_error; + + assign dio_pad_attr_60_invert_60_wd = reg_wdata[0]; + + assign dio_pad_attr_60_virtual_od_en_60_wd = reg_wdata[1]; + + assign dio_pad_attr_60_pull_en_60_wd = reg_wdata[2]; + + assign dio_pad_attr_60_pull_select_60_wd = reg_wdata[3]; + + assign dio_pad_attr_60_keeper_en_60_wd = reg_wdata[4]; + + assign dio_pad_attr_60_schmitt_en_60_wd = reg_wdata[5]; + + assign dio_pad_attr_60_od_en_60_wd = reg_wdata[6]; + + assign dio_pad_attr_60_input_disable_60_wd = reg_wdata[7]; + + assign dio_pad_attr_60_slew_rate_60_wd = reg_wdata[17:16]; + + assign dio_pad_attr_60_drive_strength_60_wd = reg_wdata[23:20]; + assign dio_pad_attr_61_re = addr_hit[191] & reg_re & !reg_error; + assign dio_pad_attr_61_we = addr_hit[191] & reg_we & !reg_error; + + assign dio_pad_attr_61_invert_61_wd = reg_wdata[0]; + + assign dio_pad_attr_61_virtual_od_en_61_wd = reg_wdata[1]; + + assign dio_pad_attr_61_pull_en_61_wd = reg_wdata[2]; + + assign dio_pad_attr_61_pull_select_61_wd = reg_wdata[3]; + + assign dio_pad_attr_61_keeper_en_61_wd = reg_wdata[4]; + + assign dio_pad_attr_61_schmitt_en_61_wd = reg_wdata[5]; + + assign dio_pad_attr_61_od_en_61_wd = reg_wdata[6]; + + assign dio_pad_attr_61_input_disable_61_wd = reg_wdata[7]; + + assign dio_pad_attr_61_slew_rate_61_wd = reg_wdata[17:16]; + + assign dio_pad_attr_61_drive_strength_61_wd = reg_wdata[23:20]; + assign dio_pad_attr_62_re = addr_hit[192] & reg_re & !reg_error; + assign dio_pad_attr_62_we = addr_hit[192] & reg_we & !reg_error; + + assign dio_pad_attr_62_invert_62_wd = reg_wdata[0]; + + assign dio_pad_attr_62_virtual_od_en_62_wd = reg_wdata[1]; + + assign dio_pad_attr_62_pull_en_62_wd = reg_wdata[2]; + + assign dio_pad_attr_62_pull_select_62_wd = reg_wdata[3]; + + assign dio_pad_attr_62_keeper_en_62_wd = reg_wdata[4]; + + assign dio_pad_attr_62_schmitt_en_62_wd = reg_wdata[5]; + + assign dio_pad_attr_62_od_en_62_wd = reg_wdata[6]; + + assign dio_pad_attr_62_input_disable_62_wd = reg_wdata[7]; + + assign dio_pad_attr_62_slew_rate_62_wd = reg_wdata[17:16]; + + assign dio_pad_attr_62_drive_strength_62_wd = reg_wdata[23:20]; + assign dio_pad_attr_63_re = addr_hit[193] & reg_re & !reg_error; + assign dio_pad_attr_63_we = addr_hit[193] & reg_we & !reg_error; + + assign dio_pad_attr_63_invert_63_wd = reg_wdata[0]; + + assign dio_pad_attr_63_virtual_od_en_63_wd = reg_wdata[1]; + + assign dio_pad_attr_63_pull_en_63_wd = reg_wdata[2]; + + assign dio_pad_attr_63_pull_select_63_wd = reg_wdata[3]; + + assign dio_pad_attr_63_keeper_en_63_wd = reg_wdata[4]; + + assign dio_pad_attr_63_schmitt_en_63_wd = reg_wdata[5]; + + assign dio_pad_attr_63_od_en_63_wd = reg_wdata[6]; + + assign dio_pad_attr_63_input_disable_63_wd = reg_wdata[7]; + + assign dio_pad_attr_63_slew_rate_63_wd = reg_wdata[17:16]; + + assign dio_pad_attr_63_drive_strength_63_wd = reg_wdata[23:20]; + assign dio_pad_attr_64_re = addr_hit[194] & reg_re & !reg_error; + assign dio_pad_attr_64_we = addr_hit[194] & reg_we & !reg_error; + + assign dio_pad_attr_64_invert_64_wd = reg_wdata[0]; + + assign dio_pad_attr_64_virtual_od_en_64_wd = reg_wdata[1]; + + assign dio_pad_attr_64_pull_en_64_wd = reg_wdata[2]; + + assign dio_pad_attr_64_pull_select_64_wd = reg_wdata[3]; + + assign dio_pad_attr_64_keeper_en_64_wd = reg_wdata[4]; + + assign dio_pad_attr_64_schmitt_en_64_wd = reg_wdata[5]; + + assign dio_pad_attr_64_od_en_64_wd = reg_wdata[6]; + + assign dio_pad_attr_64_input_disable_64_wd = reg_wdata[7]; + + assign dio_pad_attr_64_slew_rate_64_wd = reg_wdata[17:16]; + + assign dio_pad_attr_64_drive_strength_64_wd = reg_wdata[23:20]; + assign dio_pad_attr_65_re = addr_hit[195] & reg_re & !reg_error; + assign dio_pad_attr_65_we = addr_hit[195] & reg_we & !reg_error; + + assign dio_pad_attr_65_invert_65_wd = reg_wdata[0]; + + assign dio_pad_attr_65_virtual_od_en_65_wd = reg_wdata[1]; + + assign dio_pad_attr_65_pull_en_65_wd = reg_wdata[2]; + + assign dio_pad_attr_65_pull_select_65_wd = reg_wdata[3]; + + assign dio_pad_attr_65_keeper_en_65_wd = reg_wdata[4]; + + assign dio_pad_attr_65_schmitt_en_65_wd = reg_wdata[5]; + + assign dio_pad_attr_65_od_en_65_wd = reg_wdata[6]; + + assign dio_pad_attr_65_input_disable_65_wd = reg_wdata[7]; + + assign dio_pad_attr_65_slew_rate_65_wd = reg_wdata[17:16]; + + assign dio_pad_attr_65_drive_strength_65_wd = reg_wdata[23:20]; + assign dio_pad_attr_66_re = addr_hit[196] & reg_re & !reg_error; + assign dio_pad_attr_66_we = addr_hit[196] & reg_we & !reg_error; + + assign dio_pad_attr_66_invert_66_wd = reg_wdata[0]; + + assign dio_pad_attr_66_virtual_od_en_66_wd = reg_wdata[1]; + + assign dio_pad_attr_66_pull_en_66_wd = reg_wdata[2]; + + assign dio_pad_attr_66_pull_select_66_wd = reg_wdata[3]; + + assign dio_pad_attr_66_keeper_en_66_wd = reg_wdata[4]; + + assign dio_pad_attr_66_schmitt_en_66_wd = reg_wdata[5]; + + assign dio_pad_attr_66_od_en_66_wd = reg_wdata[6]; + + assign dio_pad_attr_66_input_disable_66_wd = reg_wdata[7]; + + assign dio_pad_attr_66_slew_rate_66_wd = reg_wdata[17:16]; + + assign dio_pad_attr_66_drive_strength_66_wd = reg_wdata[23:20]; + assign dio_pad_attr_67_re = addr_hit[197] & reg_re & !reg_error; + assign dio_pad_attr_67_we = addr_hit[197] & reg_we & !reg_error; + + assign dio_pad_attr_67_invert_67_wd = reg_wdata[0]; + + assign dio_pad_attr_67_virtual_od_en_67_wd = reg_wdata[1]; + + assign dio_pad_attr_67_pull_en_67_wd = reg_wdata[2]; + + assign dio_pad_attr_67_pull_select_67_wd = reg_wdata[3]; + + assign dio_pad_attr_67_keeper_en_67_wd = reg_wdata[4]; + + assign dio_pad_attr_67_schmitt_en_67_wd = reg_wdata[5]; + + assign dio_pad_attr_67_od_en_67_wd = reg_wdata[6]; + + assign dio_pad_attr_67_input_disable_67_wd = reg_wdata[7]; + + assign dio_pad_attr_67_slew_rate_67_wd = reg_wdata[17:16]; + + assign dio_pad_attr_67_drive_strength_67_wd = reg_wdata[23:20]; + assign dio_pad_attr_68_re = addr_hit[198] & reg_re & !reg_error; + assign dio_pad_attr_68_we = addr_hit[198] & reg_we & !reg_error; + + assign dio_pad_attr_68_invert_68_wd = reg_wdata[0]; + + assign dio_pad_attr_68_virtual_od_en_68_wd = reg_wdata[1]; + + assign dio_pad_attr_68_pull_en_68_wd = reg_wdata[2]; + + assign dio_pad_attr_68_pull_select_68_wd = reg_wdata[3]; + + assign dio_pad_attr_68_keeper_en_68_wd = reg_wdata[4]; + + assign dio_pad_attr_68_schmitt_en_68_wd = reg_wdata[5]; + + assign dio_pad_attr_68_od_en_68_wd = reg_wdata[6]; + + assign dio_pad_attr_68_input_disable_68_wd = reg_wdata[7]; + + assign dio_pad_attr_68_slew_rate_68_wd = reg_wdata[17:16]; + + assign dio_pad_attr_68_drive_strength_68_wd = reg_wdata[23:20]; + assign dio_pad_attr_69_re = addr_hit[199] & reg_re & !reg_error; + assign dio_pad_attr_69_we = addr_hit[199] & reg_we & !reg_error; + + assign dio_pad_attr_69_invert_69_wd = reg_wdata[0]; + + assign dio_pad_attr_69_virtual_od_en_69_wd = reg_wdata[1]; + + assign dio_pad_attr_69_pull_en_69_wd = reg_wdata[2]; + + assign dio_pad_attr_69_pull_select_69_wd = reg_wdata[3]; + + assign dio_pad_attr_69_keeper_en_69_wd = reg_wdata[4]; + + assign dio_pad_attr_69_schmitt_en_69_wd = reg_wdata[5]; + + assign dio_pad_attr_69_od_en_69_wd = reg_wdata[6]; + + assign dio_pad_attr_69_input_disable_69_wd = reg_wdata[7]; + + assign dio_pad_attr_69_slew_rate_69_wd = reg_wdata[17:16]; + + assign dio_pad_attr_69_drive_strength_69_wd = reg_wdata[23:20]; + assign dio_pad_attr_70_re = addr_hit[200] & reg_re & !reg_error; + assign dio_pad_attr_70_we = addr_hit[200] & reg_we & !reg_error; + + assign dio_pad_attr_70_invert_70_wd = reg_wdata[0]; + + assign dio_pad_attr_70_virtual_od_en_70_wd = reg_wdata[1]; + + assign dio_pad_attr_70_pull_en_70_wd = reg_wdata[2]; + + assign dio_pad_attr_70_pull_select_70_wd = reg_wdata[3]; + + assign dio_pad_attr_70_keeper_en_70_wd = reg_wdata[4]; + + assign dio_pad_attr_70_schmitt_en_70_wd = reg_wdata[5]; + + assign dio_pad_attr_70_od_en_70_wd = reg_wdata[6]; + + assign dio_pad_attr_70_input_disable_70_wd = reg_wdata[7]; + + assign dio_pad_attr_70_slew_rate_70_wd = reg_wdata[17:16]; + + assign dio_pad_attr_70_drive_strength_70_wd = reg_wdata[23:20]; + assign dio_pad_attr_71_re = addr_hit[201] & reg_re & !reg_error; + assign dio_pad_attr_71_we = addr_hit[201] & reg_we & !reg_error; + + assign dio_pad_attr_71_invert_71_wd = reg_wdata[0]; + + assign dio_pad_attr_71_virtual_od_en_71_wd = reg_wdata[1]; + + assign dio_pad_attr_71_pull_en_71_wd = reg_wdata[2]; + + assign dio_pad_attr_71_pull_select_71_wd = reg_wdata[3]; + + assign dio_pad_attr_71_keeper_en_71_wd = reg_wdata[4]; + + assign dio_pad_attr_71_schmitt_en_71_wd = reg_wdata[5]; + + assign dio_pad_attr_71_od_en_71_wd = reg_wdata[6]; + + assign dio_pad_attr_71_input_disable_71_wd = reg_wdata[7]; + + assign dio_pad_attr_71_slew_rate_71_wd = reg_wdata[17:16]; + + assign dio_pad_attr_71_drive_strength_71_wd = reg_wdata[23:20]; + assign dio_pad_attr_72_re = addr_hit[202] & reg_re & !reg_error; + assign dio_pad_attr_72_we = addr_hit[202] & reg_we & !reg_error; + + assign dio_pad_attr_72_invert_72_wd = reg_wdata[0]; + + assign dio_pad_attr_72_virtual_od_en_72_wd = reg_wdata[1]; + + assign dio_pad_attr_72_pull_en_72_wd = reg_wdata[2]; + + assign dio_pad_attr_72_pull_select_72_wd = reg_wdata[3]; + + assign dio_pad_attr_72_keeper_en_72_wd = reg_wdata[4]; + + assign dio_pad_attr_72_schmitt_en_72_wd = reg_wdata[5]; + + assign dio_pad_attr_72_od_en_72_wd = reg_wdata[6]; + + assign dio_pad_attr_72_input_disable_72_wd = reg_wdata[7]; + + assign dio_pad_attr_72_slew_rate_72_wd = reg_wdata[17:16]; + + assign dio_pad_attr_72_drive_strength_72_wd = reg_wdata[23:20]; + assign mio_pad_sleep_status_we = addr_hit[203] & reg_we & !reg_error; + + assign mio_pad_sleep_status_en_0_wd = reg_wdata[0]; + + assign mio_pad_sleep_status_en_1_wd = reg_wdata[1]; + + assign mio_pad_sleep_status_en_2_wd = reg_wdata[2]; + + assign mio_pad_sleep_status_en_3_wd = reg_wdata[3]; + + assign mio_pad_sleep_status_en_4_wd = reg_wdata[4]; + + assign mio_pad_sleep_status_en_5_wd = reg_wdata[5]; + + assign mio_pad_sleep_status_en_6_wd = reg_wdata[6]; + + assign mio_pad_sleep_status_en_7_wd = reg_wdata[7]; + + assign mio_pad_sleep_status_en_8_wd = reg_wdata[8]; + + assign mio_pad_sleep_status_en_9_wd = reg_wdata[9]; + + assign mio_pad_sleep_status_en_10_wd = reg_wdata[10]; + + assign mio_pad_sleep_status_en_11_wd = reg_wdata[11]; + assign mio_pad_sleep_regwen_0_we = addr_hit[204] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_0_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_1_we = addr_hit[205] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_1_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_2_we = addr_hit[206] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_2_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_3_we = addr_hit[207] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_3_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_4_we = addr_hit[208] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_4_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_5_we = addr_hit[209] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_5_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_6_we = addr_hit[210] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_6_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_7_we = addr_hit[211] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_7_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_8_we = addr_hit[212] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_8_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_9_we = addr_hit[213] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_9_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_10_we = addr_hit[214] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_10_wd = reg_wdata[0]; + assign mio_pad_sleep_regwen_11_we = addr_hit[215] & reg_we & !reg_error; + + assign mio_pad_sleep_regwen_11_wd = reg_wdata[0]; + assign mio_pad_sleep_en_0_we = addr_hit[216] & reg_we & !reg_error; + + assign mio_pad_sleep_en_0_wd = reg_wdata[0]; + assign mio_pad_sleep_en_1_we = addr_hit[217] & reg_we & !reg_error; + + assign mio_pad_sleep_en_1_wd = reg_wdata[0]; + assign mio_pad_sleep_en_2_we = addr_hit[218] & reg_we & !reg_error; + + assign mio_pad_sleep_en_2_wd = reg_wdata[0]; + assign mio_pad_sleep_en_3_we = addr_hit[219] & reg_we & !reg_error; + + assign mio_pad_sleep_en_3_wd = reg_wdata[0]; + assign mio_pad_sleep_en_4_we = addr_hit[220] & reg_we & !reg_error; + + assign mio_pad_sleep_en_4_wd = reg_wdata[0]; + assign mio_pad_sleep_en_5_we = addr_hit[221] & reg_we & !reg_error; + + assign mio_pad_sleep_en_5_wd = reg_wdata[0]; + assign mio_pad_sleep_en_6_we = addr_hit[222] & reg_we & !reg_error; + + assign mio_pad_sleep_en_6_wd = reg_wdata[0]; + assign mio_pad_sleep_en_7_we = addr_hit[223] & reg_we & !reg_error; + + assign mio_pad_sleep_en_7_wd = reg_wdata[0]; + assign mio_pad_sleep_en_8_we = addr_hit[224] & reg_we & !reg_error; + + assign mio_pad_sleep_en_8_wd = reg_wdata[0]; + assign mio_pad_sleep_en_9_we = addr_hit[225] & reg_we & !reg_error; + + assign mio_pad_sleep_en_9_wd = reg_wdata[0]; + assign mio_pad_sleep_en_10_we = addr_hit[226] & reg_we & !reg_error; + + assign mio_pad_sleep_en_10_wd = reg_wdata[0]; + assign mio_pad_sleep_en_11_we = addr_hit[227] & reg_we & !reg_error; + + assign mio_pad_sleep_en_11_wd = reg_wdata[0]; + assign mio_pad_sleep_mode_0_we = addr_hit[228] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_1_we = addr_hit[229] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_2_we = addr_hit[230] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_3_we = addr_hit[231] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_4_we = addr_hit[232] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_5_we = addr_hit[233] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_6_we = addr_hit[234] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_7_we = addr_hit[235] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_8_we = addr_hit[236] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_9_we = addr_hit[237] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_10_we = addr_hit[238] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0]; + assign mio_pad_sleep_mode_11_we = addr_hit[239] & reg_we & !reg_error; + + assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0]; + assign dio_pad_sleep_status_0_we = addr_hit[240] & reg_we & !reg_error; + + assign dio_pad_sleep_status_0_en_0_wd = reg_wdata[0]; + + assign dio_pad_sleep_status_0_en_1_wd = reg_wdata[1]; + + assign dio_pad_sleep_status_0_en_2_wd = reg_wdata[2]; + + assign dio_pad_sleep_status_0_en_3_wd = reg_wdata[3]; + + assign dio_pad_sleep_status_0_en_4_wd = reg_wdata[4]; + + assign dio_pad_sleep_status_0_en_5_wd = reg_wdata[5]; + + assign dio_pad_sleep_status_0_en_6_wd = reg_wdata[6]; + + assign dio_pad_sleep_status_0_en_7_wd = reg_wdata[7]; + + assign dio_pad_sleep_status_0_en_8_wd = reg_wdata[8]; + + assign dio_pad_sleep_status_0_en_9_wd = reg_wdata[9]; + + assign dio_pad_sleep_status_0_en_10_wd = reg_wdata[10]; + + assign dio_pad_sleep_status_0_en_11_wd = reg_wdata[11]; + + assign dio_pad_sleep_status_0_en_12_wd = reg_wdata[12]; + + assign dio_pad_sleep_status_0_en_13_wd = reg_wdata[13]; + + assign dio_pad_sleep_status_0_en_14_wd = reg_wdata[14]; + + assign dio_pad_sleep_status_0_en_15_wd = reg_wdata[15]; + + assign dio_pad_sleep_status_0_en_16_wd = reg_wdata[16]; + + assign dio_pad_sleep_status_0_en_17_wd = reg_wdata[17]; + + assign dio_pad_sleep_status_0_en_18_wd = reg_wdata[18]; + + assign dio_pad_sleep_status_0_en_19_wd = reg_wdata[19]; + + assign dio_pad_sleep_status_0_en_20_wd = reg_wdata[20]; + + assign dio_pad_sleep_status_0_en_21_wd = reg_wdata[21]; + + assign dio_pad_sleep_status_0_en_22_wd = reg_wdata[22]; + + assign dio_pad_sleep_status_0_en_23_wd = reg_wdata[23]; + + assign dio_pad_sleep_status_0_en_24_wd = reg_wdata[24]; + + assign dio_pad_sleep_status_0_en_25_wd = reg_wdata[25]; + + assign dio_pad_sleep_status_0_en_26_wd = reg_wdata[26]; + + assign dio_pad_sleep_status_0_en_27_wd = reg_wdata[27]; + + assign dio_pad_sleep_status_0_en_28_wd = reg_wdata[28]; + + assign dio_pad_sleep_status_0_en_29_wd = reg_wdata[29]; + + assign dio_pad_sleep_status_0_en_30_wd = reg_wdata[30]; + + assign dio_pad_sleep_status_0_en_31_wd = reg_wdata[31]; + assign dio_pad_sleep_status_1_we = addr_hit[241] & reg_we & !reg_error; + + assign dio_pad_sleep_status_1_en_32_wd = reg_wdata[0]; + + assign dio_pad_sleep_status_1_en_33_wd = reg_wdata[1]; + + assign dio_pad_sleep_status_1_en_34_wd = reg_wdata[2]; + + assign dio_pad_sleep_status_1_en_35_wd = reg_wdata[3]; + + assign dio_pad_sleep_status_1_en_36_wd = reg_wdata[4]; + + assign dio_pad_sleep_status_1_en_37_wd = reg_wdata[5]; + + assign dio_pad_sleep_status_1_en_38_wd = reg_wdata[6]; + + assign dio_pad_sleep_status_1_en_39_wd = reg_wdata[7]; + + assign dio_pad_sleep_status_1_en_40_wd = reg_wdata[8]; + + assign dio_pad_sleep_status_1_en_41_wd = reg_wdata[9]; + + assign dio_pad_sleep_status_1_en_42_wd = reg_wdata[10]; + + assign dio_pad_sleep_status_1_en_43_wd = reg_wdata[11]; + + assign dio_pad_sleep_status_1_en_44_wd = reg_wdata[12]; + + assign dio_pad_sleep_status_1_en_45_wd = reg_wdata[13]; + + assign dio_pad_sleep_status_1_en_46_wd = reg_wdata[14]; + + assign dio_pad_sleep_status_1_en_47_wd = reg_wdata[15]; + + assign dio_pad_sleep_status_1_en_48_wd = reg_wdata[16]; + + assign dio_pad_sleep_status_1_en_49_wd = reg_wdata[17]; + + assign dio_pad_sleep_status_1_en_50_wd = reg_wdata[18]; + + assign dio_pad_sleep_status_1_en_51_wd = reg_wdata[19]; + + assign dio_pad_sleep_status_1_en_52_wd = reg_wdata[20]; + + assign dio_pad_sleep_status_1_en_53_wd = reg_wdata[21]; + + assign dio_pad_sleep_status_1_en_54_wd = reg_wdata[22]; + + assign dio_pad_sleep_status_1_en_55_wd = reg_wdata[23]; + + assign dio_pad_sleep_status_1_en_56_wd = reg_wdata[24]; + + assign dio_pad_sleep_status_1_en_57_wd = reg_wdata[25]; + + assign dio_pad_sleep_status_1_en_58_wd = reg_wdata[26]; + + assign dio_pad_sleep_status_1_en_59_wd = reg_wdata[27]; + + assign dio_pad_sleep_status_1_en_60_wd = reg_wdata[28]; + + assign dio_pad_sleep_status_1_en_61_wd = reg_wdata[29]; + + assign dio_pad_sleep_status_1_en_62_wd = reg_wdata[30]; + + assign dio_pad_sleep_status_1_en_63_wd = reg_wdata[31]; + assign dio_pad_sleep_status_2_we = addr_hit[242] & reg_we & !reg_error; + + assign dio_pad_sleep_status_2_en_64_wd = reg_wdata[0]; + + assign dio_pad_sleep_status_2_en_65_wd = reg_wdata[1]; + + assign dio_pad_sleep_status_2_en_66_wd = reg_wdata[2]; + + assign dio_pad_sleep_status_2_en_67_wd = reg_wdata[3]; + + assign dio_pad_sleep_status_2_en_68_wd = reg_wdata[4]; + + assign dio_pad_sleep_status_2_en_69_wd = reg_wdata[5]; + + assign dio_pad_sleep_status_2_en_70_wd = reg_wdata[6]; + + assign dio_pad_sleep_status_2_en_71_wd = reg_wdata[7]; + + assign dio_pad_sleep_status_2_en_72_wd = reg_wdata[8]; + assign dio_pad_sleep_regwen_0_we = addr_hit[243] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_0_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_1_we = addr_hit[244] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_1_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_2_we = addr_hit[245] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_2_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_3_we = addr_hit[246] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_3_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_4_we = addr_hit[247] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_4_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_5_we = addr_hit[248] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_5_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_6_we = addr_hit[249] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_6_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_7_we = addr_hit[250] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_7_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_8_we = addr_hit[251] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_8_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_9_we = addr_hit[252] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_9_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_10_we = addr_hit[253] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_10_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_11_we = addr_hit[254] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_11_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_12_we = addr_hit[255] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_12_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_13_we = addr_hit[256] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_13_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_14_we = addr_hit[257] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_14_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_15_we = addr_hit[258] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_15_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_16_we = addr_hit[259] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_16_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_17_we = addr_hit[260] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_17_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_18_we = addr_hit[261] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_18_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_19_we = addr_hit[262] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_19_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_20_we = addr_hit[263] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_20_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_21_we = addr_hit[264] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_21_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_22_we = addr_hit[265] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_22_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_23_we = addr_hit[266] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_23_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_24_we = addr_hit[267] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_24_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_25_we = addr_hit[268] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_25_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_26_we = addr_hit[269] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_26_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_27_we = addr_hit[270] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_27_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_28_we = addr_hit[271] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_28_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_29_we = addr_hit[272] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_29_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_30_we = addr_hit[273] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_30_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_31_we = addr_hit[274] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_31_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_32_we = addr_hit[275] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_32_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_33_we = addr_hit[276] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_33_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_34_we = addr_hit[277] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_34_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_35_we = addr_hit[278] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_35_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_36_we = addr_hit[279] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_36_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_37_we = addr_hit[280] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_37_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_38_we = addr_hit[281] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_38_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_39_we = addr_hit[282] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_39_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_40_we = addr_hit[283] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_40_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_41_we = addr_hit[284] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_41_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_42_we = addr_hit[285] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_42_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_43_we = addr_hit[286] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_43_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_44_we = addr_hit[287] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_44_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_45_we = addr_hit[288] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_45_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_46_we = addr_hit[289] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_46_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_47_we = addr_hit[290] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_47_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_48_we = addr_hit[291] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_48_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_49_we = addr_hit[292] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_49_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_50_we = addr_hit[293] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_50_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_51_we = addr_hit[294] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_51_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_52_we = addr_hit[295] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_52_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_53_we = addr_hit[296] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_53_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_54_we = addr_hit[297] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_54_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_55_we = addr_hit[298] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_55_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_56_we = addr_hit[299] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_56_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_57_we = addr_hit[300] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_57_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_58_we = addr_hit[301] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_58_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_59_we = addr_hit[302] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_59_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_60_we = addr_hit[303] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_60_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_61_we = addr_hit[304] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_61_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_62_we = addr_hit[305] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_62_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_63_we = addr_hit[306] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_63_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_64_we = addr_hit[307] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_64_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_65_we = addr_hit[308] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_65_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_66_we = addr_hit[309] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_66_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_67_we = addr_hit[310] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_67_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_68_we = addr_hit[311] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_68_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_69_we = addr_hit[312] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_69_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_70_we = addr_hit[313] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_70_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_71_we = addr_hit[314] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_71_wd = reg_wdata[0]; + assign dio_pad_sleep_regwen_72_we = addr_hit[315] & reg_we & !reg_error; + + assign dio_pad_sleep_regwen_72_wd = reg_wdata[0]; + assign dio_pad_sleep_en_0_we = addr_hit[316] & reg_we & !reg_error; + + assign dio_pad_sleep_en_0_wd = reg_wdata[0]; + assign dio_pad_sleep_en_1_we = addr_hit[317] & reg_we & !reg_error; + + assign dio_pad_sleep_en_1_wd = reg_wdata[0]; + assign dio_pad_sleep_en_2_we = addr_hit[318] & reg_we & !reg_error; + + assign dio_pad_sleep_en_2_wd = reg_wdata[0]; + assign dio_pad_sleep_en_3_we = addr_hit[319] & reg_we & !reg_error; + + assign dio_pad_sleep_en_3_wd = reg_wdata[0]; + assign dio_pad_sleep_en_4_we = addr_hit[320] & reg_we & !reg_error; + + assign dio_pad_sleep_en_4_wd = reg_wdata[0]; + assign dio_pad_sleep_en_5_we = addr_hit[321] & reg_we & !reg_error; + + assign dio_pad_sleep_en_5_wd = reg_wdata[0]; + assign dio_pad_sleep_en_6_we = addr_hit[322] & reg_we & !reg_error; + + assign dio_pad_sleep_en_6_wd = reg_wdata[0]; + assign dio_pad_sleep_en_7_we = addr_hit[323] & reg_we & !reg_error; + + assign dio_pad_sleep_en_7_wd = reg_wdata[0]; + assign dio_pad_sleep_en_8_we = addr_hit[324] & reg_we & !reg_error; + + assign dio_pad_sleep_en_8_wd = reg_wdata[0]; + assign dio_pad_sleep_en_9_we = addr_hit[325] & reg_we & !reg_error; + + assign dio_pad_sleep_en_9_wd = reg_wdata[0]; + assign dio_pad_sleep_en_10_we = addr_hit[326] & reg_we & !reg_error; + + assign dio_pad_sleep_en_10_wd = reg_wdata[0]; + assign dio_pad_sleep_en_11_we = addr_hit[327] & reg_we & !reg_error; + + assign dio_pad_sleep_en_11_wd = reg_wdata[0]; + assign dio_pad_sleep_en_12_we = addr_hit[328] & reg_we & !reg_error; + + assign dio_pad_sleep_en_12_wd = reg_wdata[0]; + assign dio_pad_sleep_en_13_we = addr_hit[329] & reg_we & !reg_error; + + assign dio_pad_sleep_en_13_wd = reg_wdata[0]; + assign dio_pad_sleep_en_14_we = addr_hit[330] & reg_we & !reg_error; + + assign dio_pad_sleep_en_14_wd = reg_wdata[0]; + assign dio_pad_sleep_en_15_we = addr_hit[331] & reg_we & !reg_error; + + assign dio_pad_sleep_en_15_wd = reg_wdata[0]; + assign dio_pad_sleep_en_16_we = addr_hit[332] & reg_we & !reg_error; + + assign dio_pad_sleep_en_16_wd = reg_wdata[0]; + assign dio_pad_sleep_en_17_we = addr_hit[333] & reg_we & !reg_error; + + assign dio_pad_sleep_en_17_wd = reg_wdata[0]; + assign dio_pad_sleep_en_18_we = addr_hit[334] & reg_we & !reg_error; + + assign dio_pad_sleep_en_18_wd = reg_wdata[0]; + assign dio_pad_sleep_en_19_we = addr_hit[335] & reg_we & !reg_error; + + assign dio_pad_sleep_en_19_wd = reg_wdata[0]; + assign dio_pad_sleep_en_20_we = addr_hit[336] & reg_we & !reg_error; + + assign dio_pad_sleep_en_20_wd = reg_wdata[0]; + assign dio_pad_sleep_en_21_we = addr_hit[337] & reg_we & !reg_error; + + assign dio_pad_sleep_en_21_wd = reg_wdata[0]; + assign dio_pad_sleep_en_22_we = addr_hit[338] & reg_we & !reg_error; + + assign dio_pad_sleep_en_22_wd = reg_wdata[0]; + assign dio_pad_sleep_en_23_we = addr_hit[339] & reg_we & !reg_error; + + assign dio_pad_sleep_en_23_wd = reg_wdata[0]; + assign dio_pad_sleep_en_24_we = addr_hit[340] & reg_we & !reg_error; + + assign dio_pad_sleep_en_24_wd = reg_wdata[0]; + assign dio_pad_sleep_en_25_we = addr_hit[341] & reg_we & !reg_error; + + assign dio_pad_sleep_en_25_wd = reg_wdata[0]; + assign dio_pad_sleep_en_26_we = addr_hit[342] & reg_we & !reg_error; + + assign dio_pad_sleep_en_26_wd = reg_wdata[0]; + assign dio_pad_sleep_en_27_we = addr_hit[343] & reg_we & !reg_error; + + assign dio_pad_sleep_en_27_wd = reg_wdata[0]; + assign dio_pad_sleep_en_28_we = addr_hit[344] & reg_we & !reg_error; + + assign dio_pad_sleep_en_28_wd = reg_wdata[0]; + assign dio_pad_sleep_en_29_we = addr_hit[345] & reg_we & !reg_error; + + assign dio_pad_sleep_en_29_wd = reg_wdata[0]; + assign dio_pad_sleep_en_30_we = addr_hit[346] & reg_we & !reg_error; + + assign dio_pad_sleep_en_30_wd = reg_wdata[0]; + assign dio_pad_sleep_en_31_we = addr_hit[347] & reg_we & !reg_error; + + assign dio_pad_sleep_en_31_wd = reg_wdata[0]; + assign dio_pad_sleep_en_32_we = addr_hit[348] & reg_we & !reg_error; + + assign dio_pad_sleep_en_32_wd = reg_wdata[0]; + assign dio_pad_sleep_en_33_we = addr_hit[349] & reg_we & !reg_error; + + assign dio_pad_sleep_en_33_wd = reg_wdata[0]; + assign dio_pad_sleep_en_34_we = addr_hit[350] & reg_we & !reg_error; + + assign dio_pad_sleep_en_34_wd = reg_wdata[0]; + assign dio_pad_sleep_en_35_we = addr_hit[351] & reg_we & !reg_error; + + assign dio_pad_sleep_en_35_wd = reg_wdata[0]; + assign dio_pad_sleep_en_36_we = addr_hit[352] & reg_we & !reg_error; + + assign dio_pad_sleep_en_36_wd = reg_wdata[0]; + assign dio_pad_sleep_en_37_we = addr_hit[353] & reg_we & !reg_error; + + assign dio_pad_sleep_en_37_wd = reg_wdata[0]; + assign dio_pad_sleep_en_38_we = addr_hit[354] & reg_we & !reg_error; + + assign dio_pad_sleep_en_38_wd = reg_wdata[0]; + assign dio_pad_sleep_en_39_we = addr_hit[355] & reg_we & !reg_error; + + assign dio_pad_sleep_en_39_wd = reg_wdata[0]; + assign dio_pad_sleep_en_40_we = addr_hit[356] & reg_we & !reg_error; + + assign dio_pad_sleep_en_40_wd = reg_wdata[0]; + assign dio_pad_sleep_en_41_we = addr_hit[357] & reg_we & !reg_error; + + assign dio_pad_sleep_en_41_wd = reg_wdata[0]; + assign dio_pad_sleep_en_42_we = addr_hit[358] & reg_we & !reg_error; + + assign dio_pad_sleep_en_42_wd = reg_wdata[0]; + assign dio_pad_sleep_en_43_we = addr_hit[359] & reg_we & !reg_error; + + assign dio_pad_sleep_en_43_wd = reg_wdata[0]; + assign dio_pad_sleep_en_44_we = addr_hit[360] & reg_we & !reg_error; + + assign dio_pad_sleep_en_44_wd = reg_wdata[0]; + assign dio_pad_sleep_en_45_we = addr_hit[361] & reg_we & !reg_error; + + assign dio_pad_sleep_en_45_wd = reg_wdata[0]; + assign dio_pad_sleep_en_46_we = addr_hit[362] & reg_we & !reg_error; + + assign dio_pad_sleep_en_46_wd = reg_wdata[0]; + assign dio_pad_sleep_en_47_we = addr_hit[363] & reg_we & !reg_error; + + assign dio_pad_sleep_en_47_wd = reg_wdata[0]; + assign dio_pad_sleep_en_48_we = addr_hit[364] & reg_we & !reg_error; + + assign dio_pad_sleep_en_48_wd = reg_wdata[0]; + assign dio_pad_sleep_en_49_we = addr_hit[365] & reg_we & !reg_error; + + assign dio_pad_sleep_en_49_wd = reg_wdata[0]; + assign dio_pad_sleep_en_50_we = addr_hit[366] & reg_we & !reg_error; + + assign dio_pad_sleep_en_50_wd = reg_wdata[0]; + assign dio_pad_sleep_en_51_we = addr_hit[367] & reg_we & !reg_error; + + assign dio_pad_sleep_en_51_wd = reg_wdata[0]; + assign dio_pad_sleep_en_52_we = addr_hit[368] & reg_we & !reg_error; + + assign dio_pad_sleep_en_52_wd = reg_wdata[0]; + assign dio_pad_sleep_en_53_we = addr_hit[369] & reg_we & !reg_error; + + assign dio_pad_sleep_en_53_wd = reg_wdata[0]; + assign dio_pad_sleep_en_54_we = addr_hit[370] & reg_we & !reg_error; + + assign dio_pad_sleep_en_54_wd = reg_wdata[0]; + assign dio_pad_sleep_en_55_we = addr_hit[371] & reg_we & !reg_error; + + assign dio_pad_sleep_en_55_wd = reg_wdata[0]; + assign dio_pad_sleep_en_56_we = addr_hit[372] & reg_we & !reg_error; + + assign dio_pad_sleep_en_56_wd = reg_wdata[0]; + assign dio_pad_sleep_en_57_we = addr_hit[373] & reg_we & !reg_error; + + assign dio_pad_sleep_en_57_wd = reg_wdata[0]; + assign dio_pad_sleep_en_58_we = addr_hit[374] & reg_we & !reg_error; + + assign dio_pad_sleep_en_58_wd = reg_wdata[0]; + assign dio_pad_sleep_en_59_we = addr_hit[375] & reg_we & !reg_error; + + assign dio_pad_sleep_en_59_wd = reg_wdata[0]; + assign dio_pad_sleep_en_60_we = addr_hit[376] & reg_we & !reg_error; + + assign dio_pad_sleep_en_60_wd = reg_wdata[0]; + assign dio_pad_sleep_en_61_we = addr_hit[377] & reg_we & !reg_error; + + assign dio_pad_sleep_en_61_wd = reg_wdata[0]; + assign dio_pad_sleep_en_62_we = addr_hit[378] & reg_we & !reg_error; + + assign dio_pad_sleep_en_62_wd = reg_wdata[0]; + assign dio_pad_sleep_en_63_we = addr_hit[379] & reg_we & !reg_error; + + assign dio_pad_sleep_en_63_wd = reg_wdata[0]; + assign dio_pad_sleep_en_64_we = addr_hit[380] & reg_we & !reg_error; + + assign dio_pad_sleep_en_64_wd = reg_wdata[0]; + assign dio_pad_sleep_en_65_we = addr_hit[381] & reg_we & !reg_error; + + assign dio_pad_sleep_en_65_wd = reg_wdata[0]; + assign dio_pad_sleep_en_66_we = addr_hit[382] & reg_we & !reg_error; + + assign dio_pad_sleep_en_66_wd = reg_wdata[0]; + assign dio_pad_sleep_en_67_we = addr_hit[383] & reg_we & !reg_error; + + assign dio_pad_sleep_en_67_wd = reg_wdata[0]; + assign dio_pad_sleep_en_68_we = addr_hit[384] & reg_we & !reg_error; + + assign dio_pad_sleep_en_68_wd = reg_wdata[0]; + assign dio_pad_sleep_en_69_we = addr_hit[385] & reg_we & !reg_error; + + assign dio_pad_sleep_en_69_wd = reg_wdata[0]; + assign dio_pad_sleep_en_70_we = addr_hit[386] & reg_we & !reg_error; + + assign dio_pad_sleep_en_70_wd = reg_wdata[0]; + assign dio_pad_sleep_en_71_we = addr_hit[387] & reg_we & !reg_error; + + assign dio_pad_sleep_en_71_wd = reg_wdata[0]; + assign dio_pad_sleep_en_72_we = addr_hit[388] & reg_we & !reg_error; + + assign dio_pad_sleep_en_72_wd = reg_wdata[0]; + assign dio_pad_sleep_mode_0_we = addr_hit[389] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_1_we = addr_hit[390] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_2_we = addr_hit[391] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_3_we = addr_hit[392] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_4_we = addr_hit[393] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_5_we = addr_hit[394] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_6_we = addr_hit[395] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_7_we = addr_hit[396] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_8_we = addr_hit[397] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_9_we = addr_hit[398] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_10_we = addr_hit[399] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_11_we = addr_hit[400] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_12_we = addr_hit[401] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_13_we = addr_hit[402] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_14_we = addr_hit[403] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_15_we = addr_hit[404] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_16_we = addr_hit[405] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_16_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_17_we = addr_hit[406] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_17_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_18_we = addr_hit[407] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_18_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_19_we = addr_hit[408] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_19_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_20_we = addr_hit[409] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_20_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_21_we = addr_hit[410] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_21_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_22_we = addr_hit[411] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_22_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_23_we = addr_hit[412] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_23_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_24_we = addr_hit[413] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_24_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_25_we = addr_hit[414] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_25_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_26_we = addr_hit[415] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_26_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_27_we = addr_hit[416] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_27_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_28_we = addr_hit[417] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_28_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_29_we = addr_hit[418] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_29_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_30_we = addr_hit[419] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_30_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_31_we = addr_hit[420] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_31_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_32_we = addr_hit[421] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_32_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_33_we = addr_hit[422] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_33_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_34_we = addr_hit[423] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_34_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_35_we = addr_hit[424] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_35_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_36_we = addr_hit[425] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_36_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_37_we = addr_hit[426] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_37_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_38_we = addr_hit[427] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_38_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_39_we = addr_hit[428] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_39_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_40_we = addr_hit[429] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_40_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_41_we = addr_hit[430] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_41_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_42_we = addr_hit[431] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_42_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_43_we = addr_hit[432] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_43_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_44_we = addr_hit[433] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_44_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_45_we = addr_hit[434] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_45_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_46_we = addr_hit[435] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_46_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_47_we = addr_hit[436] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_47_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_48_we = addr_hit[437] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_48_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_49_we = addr_hit[438] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_49_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_50_we = addr_hit[439] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_50_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_51_we = addr_hit[440] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_51_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_52_we = addr_hit[441] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_52_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_53_we = addr_hit[442] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_53_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_54_we = addr_hit[443] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_54_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_55_we = addr_hit[444] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_55_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_56_we = addr_hit[445] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_56_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_57_we = addr_hit[446] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_57_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_58_we = addr_hit[447] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_58_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_59_we = addr_hit[448] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_59_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_60_we = addr_hit[449] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_60_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_61_we = addr_hit[450] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_61_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_62_we = addr_hit[451] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_62_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_63_we = addr_hit[452] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_63_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_64_we = addr_hit[453] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_64_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_65_we = addr_hit[454] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_65_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_66_we = addr_hit[455] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_66_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_67_we = addr_hit[456] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_67_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_68_we = addr_hit[457] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_68_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_69_we = addr_hit[458] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_69_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_70_we = addr_hit[459] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_70_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_71_we = addr_hit[460] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_71_wd = reg_wdata[1:0]; + assign dio_pad_sleep_mode_72_we = addr_hit[461] & reg_we & !reg_error; + + assign dio_pad_sleep_mode_72_wd = reg_wdata[1:0]; + assign wkup_detector_regwen_0_we = addr_hit[462] & reg_we & !reg_error; + + assign wkup_detector_regwen_0_wd = reg_wdata[0]; + assign wkup_detector_regwen_1_we = addr_hit[463] & reg_we & !reg_error; + + assign wkup_detector_regwen_1_wd = reg_wdata[0]; + assign wkup_detector_regwen_2_we = addr_hit[464] & reg_we & !reg_error; + + assign wkup_detector_regwen_2_wd = reg_wdata[0]; + assign wkup_detector_regwen_3_we = addr_hit[465] & reg_we & !reg_error; + + assign wkup_detector_regwen_3_wd = reg_wdata[0]; + assign wkup_detector_regwen_4_we = addr_hit[466] & reg_we & !reg_error; + + assign wkup_detector_regwen_4_wd = reg_wdata[0]; + assign wkup_detector_regwen_5_we = addr_hit[467] & reg_we & !reg_error; + + assign wkup_detector_regwen_5_wd = reg_wdata[0]; + assign wkup_detector_regwen_6_we = addr_hit[468] & reg_we & !reg_error; + + assign wkup_detector_regwen_6_wd = reg_wdata[0]; + assign wkup_detector_regwen_7_we = addr_hit[469] & reg_we & !reg_error; + + assign wkup_detector_regwen_7_wd = reg_wdata[0]; + assign wkup_detector_en_0_we = addr_hit[470] & reg_we & !reg_error; + + assign wkup_detector_en_1_we = addr_hit[471] & reg_we & !reg_error; + + assign wkup_detector_en_2_we = addr_hit[472] & reg_we & !reg_error; + + assign wkup_detector_en_3_we = addr_hit[473] & reg_we & !reg_error; + + assign wkup_detector_en_4_we = addr_hit[474] & reg_we & !reg_error; + + assign wkup_detector_en_5_we = addr_hit[475] & reg_we & !reg_error; + + assign wkup_detector_en_6_we = addr_hit[476] & reg_we & !reg_error; + + assign wkup_detector_en_7_we = addr_hit[477] & reg_we & !reg_error; + + assign wkup_detector_0_we = addr_hit[478] & reg_we & !reg_error; + + + + assign wkup_detector_1_we = addr_hit[479] & reg_we & !reg_error; + + + + assign wkup_detector_2_we = addr_hit[480] & reg_we & !reg_error; + + + + assign wkup_detector_3_we = addr_hit[481] & reg_we & !reg_error; + + + + assign wkup_detector_4_we = addr_hit[482] & reg_we & !reg_error; + + + + assign wkup_detector_5_we = addr_hit[483] & reg_we & !reg_error; + + + + assign wkup_detector_6_we = addr_hit[484] & reg_we & !reg_error; + + + + assign wkup_detector_7_we = addr_hit[485] & reg_we & !reg_error; + + + + assign wkup_detector_cnt_th_0_we = addr_hit[486] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_1_we = addr_hit[487] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_2_we = addr_hit[488] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_3_we = addr_hit[489] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_4_we = addr_hit[490] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_5_we = addr_hit[491] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_6_we = addr_hit[492] & reg_we & !reg_error; + + assign wkup_detector_cnt_th_7_we = addr_hit[493] & reg_we & !reg_error; + + assign wkup_detector_padsel_0_we = addr_hit[494] & reg_we & !reg_error; + + assign wkup_detector_padsel_0_wd = reg_wdata[6:0]; + assign wkup_detector_padsel_1_we = addr_hit[495] & reg_we & !reg_error; + + assign wkup_detector_padsel_1_wd = reg_wdata[6:0]; + assign wkup_detector_padsel_2_we = addr_hit[496] & reg_we & !reg_error; + + assign wkup_detector_padsel_2_wd = reg_wdata[6:0]; + assign wkup_detector_padsel_3_we = addr_hit[497] & reg_we & !reg_error; + + assign wkup_detector_padsel_3_wd = reg_wdata[6:0]; + assign wkup_detector_padsel_4_we = addr_hit[498] & reg_we & !reg_error; + + assign wkup_detector_padsel_4_wd = reg_wdata[6:0]; + assign wkup_detector_padsel_5_we = addr_hit[499] & reg_we & !reg_error; + + assign wkup_detector_padsel_5_wd = reg_wdata[6:0]; + assign wkup_detector_padsel_6_we = addr_hit[500] & reg_we & !reg_error; + + assign wkup_detector_padsel_6_wd = reg_wdata[6:0]; + assign wkup_detector_padsel_7_we = addr_hit[501] & reg_we & !reg_error; + + assign wkup_detector_padsel_7_wd = reg_wdata[6:0]; + assign wkup_cause_we = addr_hit[502] & reg_we & !reg_error; + + + + + + + + + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = alert_test_we; + reg_we_check[1] = mio_periph_insel_regwen_0_we; + reg_we_check[2] = mio_periph_insel_regwen_1_we; + reg_we_check[3] = mio_periph_insel_regwen_2_we; + reg_we_check[4] = mio_periph_insel_regwen_3_we; + reg_we_check[5] = mio_periph_insel_0_gated_we; + reg_we_check[6] = mio_periph_insel_1_gated_we; + reg_we_check[7] = mio_periph_insel_2_gated_we; + reg_we_check[8] = mio_periph_insel_3_gated_we; + reg_we_check[9] = mio_outsel_regwen_0_we; + reg_we_check[10] = mio_outsel_regwen_1_we; + reg_we_check[11] = mio_outsel_regwen_2_we; + reg_we_check[12] = mio_outsel_regwen_3_we; + reg_we_check[13] = mio_outsel_regwen_4_we; + reg_we_check[14] = mio_outsel_regwen_5_we; + reg_we_check[15] = mio_outsel_regwen_6_we; + reg_we_check[16] = mio_outsel_regwen_7_we; + reg_we_check[17] = mio_outsel_regwen_8_we; + reg_we_check[18] = mio_outsel_regwen_9_we; + reg_we_check[19] = mio_outsel_regwen_10_we; + reg_we_check[20] = mio_outsel_regwen_11_we; + reg_we_check[21] = mio_outsel_0_gated_we; + reg_we_check[22] = mio_outsel_1_gated_we; + reg_we_check[23] = mio_outsel_2_gated_we; + reg_we_check[24] = mio_outsel_3_gated_we; + reg_we_check[25] = mio_outsel_4_gated_we; + reg_we_check[26] = mio_outsel_5_gated_we; + reg_we_check[27] = mio_outsel_6_gated_we; + reg_we_check[28] = mio_outsel_7_gated_we; + reg_we_check[29] = mio_outsel_8_gated_we; + reg_we_check[30] = mio_outsel_9_gated_we; + reg_we_check[31] = mio_outsel_10_gated_we; + reg_we_check[32] = mio_outsel_11_gated_we; + reg_we_check[33] = mio_pad_attr_regwen_0_we; + reg_we_check[34] = mio_pad_attr_regwen_1_we; + reg_we_check[35] = mio_pad_attr_regwen_2_we; + reg_we_check[36] = mio_pad_attr_regwen_3_we; + reg_we_check[37] = mio_pad_attr_regwen_4_we; + reg_we_check[38] = mio_pad_attr_regwen_5_we; + reg_we_check[39] = mio_pad_attr_regwen_6_we; + reg_we_check[40] = mio_pad_attr_regwen_7_we; + reg_we_check[41] = mio_pad_attr_regwen_8_we; + reg_we_check[42] = mio_pad_attr_regwen_9_we; + reg_we_check[43] = mio_pad_attr_regwen_10_we; + reg_we_check[44] = mio_pad_attr_regwen_11_we; + reg_we_check[45] = mio_pad_attr_0_gated_we; + reg_we_check[46] = mio_pad_attr_1_gated_we; + reg_we_check[47] = mio_pad_attr_2_gated_we; + reg_we_check[48] = mio_pad_attr_3_gated_we; + reg_we_check[49] = mio_pad_attr_4_gated_we; + reg_we_check[50] = mio_pad_attr_5_gated_we; + reg_we_check[51] = mio_pad_attr_6_gated_we; + reg_we_check[52] = mio_pad_attr_7_gated_we; + reg_we_check[53] = mio_pad_attr_8_gated_we; + reg_we_check[54] = mio_pad_attr_9_gated_we; + reg_we_check[55] = mio_pad_attr_10_gated_we; + reg_we_check[56] = mio_pad_attr_11_gated_we; + reg_we_check[57] = dio_pad_attr_regwen_0_we; + reg_we_check[58] = dio_pad_attr_regwen_1_we; + reg_we_check[59] = dio_pad_attr_regwen_2_we; + reg_we_check[60] = dio_pad_attr_regwen_3_we; + reg_we_check[61] = dio_pad_attr_regwen_4_we; + reg_we_check[62] = dio_pad_attr_regwen_5_we; + reg_we_check[63] = dio_pad_attr_regwen_6_we; + reg_we_check[64] = dio_pad_attr_regwen_7_we; + reg_we_check[65] = dio_pad_attr_regwen_8_we; + reg_we_check[66] = dio_pad_attr_regwen_9_we; + reg_we_check[67] = dio_pad_attr_regwen_10_we; + reg_we_check[68] = dio_pad_attr_regwen_11_we; + reg_we_check[69] = dio_pad_attr_regwen_12_we; + reg_we_check[70] = dio_pad_attr_regwen_13_we; + reg_we_check[71] = dio_pad_attr_regwen_14_we; + reg_we_check[72] = dio_pad_attr_regwen_15_we; + reg_we_check[73] = dio_pad_attr_regwen_16_we; + reg_we_check[74] = dio_pad_attr_regwen_17_we; + reg_we_check[75] = dio_pad_attr_regwen_18_we; + reg_we_check[76] = dio_pad_attr_regwen_19_we; + reg_we_check[77] = dio_pad_attr_regwen_20_we; + reg_we_check[78] = dio_pad_attr_regwen_21_we; + reg_we_check[79] = dio_pad_attr_regwen_22_we; + reg_we_check[80] = dio_pad_attr_regwen_23_we; + reg_we_check[81] = dio_pad_attr_regwen_24_we; + reg_we_check[82] = dio_pad_attr_regwen_25_we; + reg_we_check[83] = dio_pad_attr_regwen_26_we; + reg_we_check[84] = dio_pad_attr_regwen_27_we; + reg_we_check[85] = dio_pad_attr_regwen_28_we; + reg_we_check[86] = dio_pad_attr_regwen_29_we; + reg_we_check[87] = dio_pad_attr_regwen_30_we; + reg_we_check[88] = dio_pad_attr_regwen_31_we; + reg_we_check[89] = dio_pad_attr_regwen_32_we; + reg_we_check[90] = dio_pad_attr_regwen_33_we; + reg_we_check[91] = dio_pad_attr_regwen_34_we; + reg_we_check[92] = dio_pad_attr_regwen_35_we; + reg_we_check[93] = dio_pad_attr_regwen_36_we; + reg_we_check[94] = dio_pad_attr_regwen_37_we; + reg_we_check[95] = dio_pad_attr_regwen_38_we; + reg_we_check[96] = dio_pad_attr_regwen_39_we; + reg_we_check[97] = dio_pad_attr_regwen_40_we; + reg_we_check[98] = dio_pad_attr_regwen_41_we; + reg_we_check[99] = dio_pad_attr_regwen_42_we; + reg_we_check[100] = dio_pad_attr_regwen_43_we; + reg_we_check[101] = dio_pad_attr_regwen_44_we; + reg_we_check[102] = dio_pad_attr_regwen_45_we; + reg_we_check[103] = dio_pad_attr_regwen_46_we; + reg_we_check[104] = dio_pad_attr_regwen_47_we; + reg_we_check[105] = dio_pad_attr_regwen_48_we; + reg_we_check[106] = dio_pad_attr_regwen_49_we; + reg_we_check[107] = dio_pad_attr_regwen_50_we; + reg_we_check[108] = dio_pad_attr_regwen_51_we; + reg_we_check[109] = dio_pad_attr_regwen_52_we; + reg_we_check[110] = dio_pad_attr_regwen_53_we; + reg_we_check[111] = dio_pad_attr_regwen_54_we; + reg_we_check[112] = dio_pad_attr_regwen_55_we; + reg_we_check[113] = dio_pad_attr_regwen_56_we; + reg_we_check[114] = dio_pad_attr_regwen_57_we; + reg_we_check[115] = dio_pad_attr_regwen_58_we; + reg_we_check[116] = dio_pad_attr_regwen_59_we; + reg_we_check[117] = dio_pad_attr_regwen_60_we; + reg_we_check[118] = dio_pad_attr_regwen_61_we; + reg_we_check[119] = dio_pad_attr_regwen_62_we; + reg_we_check[120] = dio_pad_attr_regwen_63_we; + reg_we_check[121] = dio_pad_attr_regwen_64_we; + reg_we_check[122] = dio_pad_attr_regwen_65_we; + reg_we_check[123] = dio_pad_attr_regwen_66_we; + reg_we_check[124] = dio_pad_attr_regwen_67_we; + reg_we_check[125] = dio_pad_attr_regwen_68_we; + reg_we_check[126] = dio_pad_attr_regwen_69_we; + reg_we_check[127] = dio_pad_attr_regwen_70_we; + reg_we_check[128] = dio_pad_attr_regwen_71_we; + reg_we_check[129] = dio_pad_attr_regwen_72_we; + reg_we_check[130] = dio_pad_attr_0_gated_we; + reg_we_check[131] = dio_pad_attr_1_gated_we; + reg_we_check[132] = dio_pad_attr_2_gated_we; + reg_we_check[133] = dio_pad_attr_3_gated_we; + reg_we_check[134] = dio_pad_attr_4_gated_we; + reg_we_check[135] = dio_pad_attr_5_gated_we; + reg_we_check[136] = dio_pad_attr_6_gated_we; + reg_we_check[137] = dio_pad_attr_7_gated_we; + reg_we_check[138] = dio_pad_attr_8_gated_we; + reg_we_check[139] = dio_pad_attr_9_gated_we; + reg_we_check[140] = dio_pad_attr_10_gated_we; + reg_we_check[141] = dio_pad_attr_11_gated_we; + reg_we_check[142] = dio_pad_attr_12_gated_we; + reg_we_check[143] = dio_pad_attr_13_gated_we; + reg_we_check[144] = dio_pad_attr_14_gated_we; + reg_we_check[145] = dio_pad_attr_15_gated_we; + reg_we_check[146] = dio_pad_attr_16_gated_we; + reg_we_check[147] = dio_pad_attr_17_gated_we; + reg_we_check[148] = dio_pad_attr_18_gated_we; + reg_we_check[149] = dio_pad_attr_19_gated_we; + reg_we_check[150] = dio_pad_attr_20_gated_we; + reg_we_check[151] = dio_pad_attr_21_gated_we; + reg_we_check[152] = dio_pad_attr_22_gated_we; + reg_we_check[153] = dio_pad_attr_23_gated_we; + reg_we_check[154] = dio_pad_attr_24_gated_we; + reg_we_check[155] = dio_pad_attr_25_gated_we; + reg_we_check[156] = dio_pad_attr_26_gated_we; + reg_we_check[157] = dio_pad_attr_27_gated_we; + reg_we_check[158] = dio_pad_attr_28_gated_we; + reg_we_check[159] = dio_pad_attr_29_gated_we; + reg_we_check[160] = dio_pad_attr_30_gated_we; + reg_we_check[161] = dio_pad_attr_31_gated_we; + reg_we_check[162] = dio_pad_attr_32_gated_we; + reg_we_check[163] = dio_pad_attr_33_gated_we; + reg_we_check[164] = dio_pad_attr_34_gated_we; + reg_we_check[165] = dio_pad_attr_35_gated_we; + reg_we_check[166] = dio_pad_attr_36_gated_we; + reg_we_check[167] = dio_pad_attr_37_gated_we; + reg_we_check[168] = dio_pad_attr_38_gated_we; + reg_we_check[169] = dio_pad_attr_39_gated_we; + reg_we_check[170] = dio_pad_attr_40_gated_we; + reg_we_check[171] = dio_pad_attr_41_gated_we; + reg_we_check[172] = dio_pad_attr_42_gated_we; + reg_we_check[173] = dio_pad_attr_43_gated_we; + reg_we_check[174] = dio_pad_attr_44_gated_we; + reg_we_check[175] = dio_pad_attr_45_gated_we; + reg_we_check[176] = dio_pad_attr_46_gated_we; + reg_we_check[177] = dio_pad_attr_47_gated_we; + reg_we_check[178] = dio_pad_attr_48_gated_we; + reg_we_check[179] = dio_pad_attr_49_gated_we; + reg_we_check[180] = dio_pad_attr_50_gated_we; + reg_we_check[181] = dio_pad_attr_51_gated_we; + reg_we_check[182] = dio_pad_attr_52_gated_we; + reg_we_check[183] = dio_pad_attr_53_gated_we; + reg_we_check[184] = dio_pad_attr_54_gated_we; + reg_we_check[185] = dio_pad_attr_55_gated_we; + reg_we_check[186] = dio_pad_attr_56_gated_we; + reg_we_check[187] = dio_pad_attr_57_gated_we; + reg_we_check[188] = dio_pad_attr_58_gated_we; + reg_we_check[189] = dio_pad_attr_59_gated_we; + reg_we_check[190] = dio_pad_attr_60_gated_we; + reg_we_check[191] = dio_pad_attr_61_gated_we; + reg_we_check[192] = dio_pad_attr_62_gated_we; + reg_we_check[193] = dio_pad_attr_63_gated_we; + reg_we_check[194] = dio_pad_attr_64_gated_we; + reg_we_check[195] = dio_pad_attr_65_gated_we; + reg_we_check[196] = dio_pad_attr_66_gated_we; + reg_we_check[197] = dio_pad_attr_67_gated_we; + reg_we_check[198] = dio_pad_attr_68_gated_we; + reg_we_check[199] = dio_pad_attr_69_gated_we; + reg_we_check[200] = dio_pad_attr_70_gated_we; + reg_we_check[201] = dio_pad_attr_71_gated_we; + reg_we_check[202] = dio_pad_attr_72_gated_we; + reg_we_check[203] = mio_pad_sleep_status_we; + reg_we_check[204] = mio_pad_sleep_regwen_0_we; + reg_we_check[205] = mio_pad_sleep_regwen_1_we; + reg_we_check[206] = mio_pad_sleep_regwen_2_we; + reg_we_check[207] = mio_pad_sleep_regwen_3_we; + reg_we_check[208] = mio_pad_sleep_regwen_4_we; + reg_we_check[209] = mio_pad_sleep_regwen_5_we; + reg_we_check[210] = mio_pad_sleep_regwen_6_we; + reg_we_check[211] = mio_pad_sleep_regwen_7_we; + reg_we_check[212] = mio_pad_sleep_regwen_8_we; + reg_we_check[213] = mio_pad_sleep_regwen_9_we; + reg_we_check[214] = mio_pad_sleep_regwen_10_we; + reg_we_check[215] = mio_pad_sleep_regwen_11_we; + reg_we_check[216] = mio_pad_sleep_en_0_gated_we; + reg_we_check[217] = mio_pad_sleep_en_1_gated_we; + reg_we_check[218] = mio_pad_sleep_en_2_gated_we; + reg_we_check[219] = mio_pad_sleep_en_3_gated_we; + reg_we_check[220] = mio_pad_sleep_en_4_gated_we; + reg_we_check[221] = mio_pad_sleep_en_5_gated_we; + reg_we_check[222] = mio_pad_sleep_en_6_gated_we; + reg_we_check[223] = mio_pad_sleep_en_7_gated_we; + reg_we_check[224] = mio_pad_sleep_en_8_gated_we; + reg_we_check[225] = mio_pad_sleep_en_9_gated_we; + reg_we_check[226] = mio_pad_sleep_en_10_gated_we; + reg_we_check[227] = mio_pad_sleep_en_11_gated_we; + reg_we_check[228] = mio_pad_sleep_mode_0_gated_we; + reg_we_check[229] = mio_pad_sleep_mode_1_gated_we; + reg_we_check[230] = mio_pad_sleep_mode_2_gated_we; + reg_we_check[231] = mio_pad_sleep_mode_3_gated_we; + reg_we_check[232] = mio_pad_sleep_mode_4_gated_we; + reg_we_check[233] = mio_pad_sleep_mode_5_gated_we; + reg_we_check[234] = mio_pad_sleep_mode_6_gated_we; + reg_we_check[235] = mio_pad_sleep_mode_7_gated_we; + reg_we_check[236] = mio_pad_sleep_mode_8_gated_we; + reg_we_check[237] = mio_pad_sleep_mode_9_gated_we; + reg_we_check[238] = mio_pad_sleep_mode_10_gated_we; + reg_we_check[239] = mio_pad_sleep_mode_11_gated_we; + reg_we_check[240] = dio_pad_sleep_status_0_we; + reg_we_check[241] = dio_pad_sleep_status_1_we; + reg_we_check[242] = dio_pad_sleep_status_2_we; + reg_we_check[243] = dio_pad_sleep_regwen_0_we; + reg_we_check[244] = dio_pad_sleep_regwen_1_we; + reg_we_check[245] = dio_pad_sleep_regwen_2_we; + reg_we_check[246] = dio_pad_sleep_regwen_3_we; + reg_we_check[247] = dio_pad_sleep_regwen_4_we; + reg_we_check[248] = dio_pad_sleep_regwen_5_we; + reg_we_check[249] = dio_pad_sleep_regwen_6_we; + reg_we_check[250] = dio_pad_sleep_regwen_7_we; + reg_we_check[251] = dio_pad_sleep_regwen_8_we; + reg_we_check[252] = dio_pad_sleep_regwen_9_we; + reg_we_check[253] = dio_pad_sleep_regwen_10_we; + reg_we_check[254] = dio_pad_sleep_regwen_11_we; + reg_we_check[255] = dio_pad_sleep_regwen_12_we; + reg_we_check[256] = dio_pad_sleep_regwen_13_we; + reg_we_check[257] = dio_pad_sleep_regwen_14_we; + reg_we_check[258] = dio_pad_sleep_regwen_15_we; + reg_we_check[259] = dio_pad_sleep_regwen_16_we; + reg_we_check[260] = dio_pad_sleep_regwen_17_we; + reg_we_check[261] = dio_pad_sleep_regwen_18_we; + reg_we_check[262] = dio_pad_sleep_regwen_19_we; + reg_we_check[263] = dio_pad_sleep_regwen_20_we; + reg_we_check[264] = dio_pad_sleep_regwen_21_we; + reg_we_check[265] = dio_pad_sleep_regwen_22_we; + reg_we_check[266] = dio_pad_sleep_regwen_23_we; + reg_we_check[267] = dio_pad_sleep_regwen_24_we; + reg_we_check[268] = dio_pad_sleep_regwen_25_we; + reg_we_check[269] = dio_pad_sleep_regwen_26_we; + reg_we_check[270] = dio_pad_sleep_regwen_27_we; + reg_we_check[271] = dio_pad_sleep_regwen_28_we; + reg_we_check[272] = dio_pad_sleep_regwen_29_we; + reg_we_check[273] = dio_pad_sleep_regwen_30_we; + reg_we_check[274] = dio_pad_sleep_regwen_31_we; + reg_we_check[275] = dio_pad_sleep_regwen_32_we; + reg_we_check[276] = dio_pad_sleep_regwen_33_we; + reg_we_check[277] = dio_pad_sleep_regwen_34_we; + reg_we_check[278] = dio_pad_sleep_regwen_35_we; + reg_we_check[279] = dio_pad_sleep_regwen_36_we; + reg_we_check[280] = dio_pad_sleep_regwen_37_we; + reg_we_check[281] = dio_pad_sleep_regwen_38_we; + reg_we_check[282] = dio_pad_sleep_regwen_39_we; + reg_we_check[283] = dio_pad_sleep_regwen_40_we; + reg_we_check[284] = dio_pad_sleep_regwen_41_we; + reg_we_check[285] = dio_pad_sleep_regwen_42_we; + reg_we_check[286] = dio_pad_sleep_regwen_43_we; + reg_we_check[287] = dio_pad_sleep_regwen_44_we; + reg_we_check[288] = dio_pad_sleep_regwen_45_we; + reg_we_check[289] = dio_pad_sleep_regwen_46_we; + reg_we_check[290] = dio_pad_sleep_regwen_47_we; + reg_we_check[291] = dio_pad_sleep_regwen_48_we; + reg_we_check[292] = dio_pad_sleep_regwen_49_we; + reg_we_check[293] = dio_pad_sleep_regwen_50_we; + reg_we_check[294] = dio_pad_sleep_regwen_51_we; + reg_we_check[295] = dio_pad_sleep_regwen_52_we; + reg_we_check[296] = dio_pad_sleep_regwen_53_we; + reg_we_check[297] = dio_pad_sleep_regwen_54_we; + reg_we_check[298] = dio_pad_sleep_regwen_55_we; + reg_we_check[299] = dio_pad_sleep_regwen_56_we; + reg_we_check[300] = dio_pad_sleep_regwen_57_we; + reg_we_check[301] = dio_pad_sleep_regwen_58_we; + reg_we_check[302] = dio_pad_sleep_regwen_59_we; + reg_we_check[303] = dio_pad_sleep_regwen_60_we; + reg_we_check[304] = dio_pad_sleep_regwen_61_we; + reg_we_check[305] = dio_pad_sleep_regwen_62_we; + reg_we_check[306] = dio_pad_sleep_regwen_63_we; + reg_we_check[307] = dio_pad_sleep_regwen_64_we; + reg_we_check[308] = dio_pad_sleep_regwen_65_we; + reg_we_check[309] = dio_pad_sleep_regwen_66_we; + reg_we_check[310] = dio_pad_sleep_regwen_67_we; + reg_we_check[311] = dio_pad_sleep_regwen_68_we; + reg_we_check[312] = dio_pad_sleep_regwen_69_we; + reg_we_check[313] = dio_pad_sleep_regwen_70_we; + reg_we_check[314] = dio_pad_sleep_regwen_71_we; + reg_we_check[315] = dio_pad_sleep_regwen_72_we; + reg_we_check[316] = dio_pad_sleep_en_0_gated_we; + reg_we_check[317] = dio_pad_sleep_en_1_gated_we; + reg_we_check[318] = dio_pad_sleep_en_2_gated_we; + reg_we_check[319] = dio_pad_sleep_en_3_gated_we; + reg_we_check[320] = dio_pad_sleep_en_4_gated_we; + reg_we_check[321] = dio_pad_sleep_en_5_gated_we; + reg_we_check[322] = dio_pad_sleep_en_6_gated_we; + reg_we_check[323] = dio_pad_sleep_en_7_gated_we; + reg_we_check[324] = dio_pad_sleep_en_8_gated_we; + reg_we_check[325] = dio_pad_sleep_en_9_gated_we; + reg_we_check[326] = dio_pad_sleep_en_10_gated_we; + reg_we_check[327] = dio_pad_sleep_en_11_gated_we; + reg_we_check[328] = dio_pad_sleep_en_12_gated_we; + reg_we_check[329] = dio_pad_sleep_en_13_gated_we; + reg_we_check[330] = dio_pad_sleep_en_14_gated_we; + reg_we_check[331] = dio_pad_sleep_en_15_gated_we; + reg_we_check[332] = dio_pad_sleep_en_16_gated_we; + reg_we_check[333] = dio_pad_sleep_en_17_gated_we; + reg_we_check[334] = dio_pad_sleep_en_18_gated_we; + reg_we_check[335] = dio_pad_sleep_en_19_gated_we; + reg_we_check[336] = dio_pad_sleep_en_20_gated_we; + reg_we_check[337] = dio_pad_sleep_en_21_gated_we; + reg_we_check[338] = dio_pad_sleep_en_22_gated_we; + reg_we_check[339] = dio_pad_sleep_en_23_gated_we; + reg_we_check[340] = dio_pad_sleep_en_24_gated_we; + reg_we_check[341] = dio_pad_sleep_en_25_gated_we; + reg_we_check[342] = dio_pad_sleep_en_26_gated_we; + reg_we_check[343] = dio_pad_sleep_en_27_gated_we; + reg_we_check[344] = dio_pad_sleep_en_28_gated_we; + reg_we_check[345] = dio_pad_sleep_en_29_gated_we; + reg_we_check[346] = dio_pad_sleep_en_30_gated_we; + reg_we_check[347] = dio_pad_sleep_en_31_gated_we; + reg_we_check[348] = dio_pad_sleep_en_32_gated_we; + reg_we_check[349] = dio_pad_sleep_en_33_gated_we; + reg_we_check[350] = dio_pad_sleep_en_34_gated_we; + reg_we_check[351] = dio_pad_sleep_en_35_gated_we; + reg_we_check[352] = dio_pad_sleep_en_36_gated_we; + reg_we_check[353] = dio_pad_sleep_en_37_gated_we; + reg_we_check[354] = dio_pad_sleep_en_38_gated_we; + reg_we_check[355] = dio_pad_sleep_en_39_gated_we; + reg_we_check[356] = dio_pad_sleep_en_40_gated_we; + reg_we_check[357] = dio_pad_sleep_en_41_gated_we; + reg_we_check[358] = dio_pad_sleep_en_42_gated_we; + reg_we_check[359] = dio_pad_sleep_en_43_gated_we; + reg_we_check[360] = dio_pad_sleep_en_44_gated_we; + reg_we_check[361] = dio_pad_sleep_en_45_gated_we; + reg_we_check[362] = dio_pad_sleep_en_46_gated_we; + reg_we_check[363] = dio_pad_sleep_en_47_gated_we; + reg_we_check[364] = dio_pad_sleep_en_48_gated_we; + reg_we_check[365] = dio_pad_sleep_en_49_gated_we; + reg_we_check[366] = dio_pad_sleep_en_50_gated_we; + reg_we_check[367] = dio_pad_sleep_en_51_gated_we; + reg_we_check[368] = dio_pad_sleep_en_52_gated_we; + reg_we_check[369] = dio_pad_sleep_en_53_gated_we; + reg_we_check[370] = dio_pad_sleep_en_54_gated_we; + reg_we_check[371] = dio_pad_sleep_en_55_gated_we; + reg_we_check[372] = dio_pad_sleep_en_56_gated_we; + reg_we_check[373] = dio_pad_sleep_en_57_gated_we; + reg_we_check[374] = dio_pad_sleep_en_58_gated_we; + reg_we_check[375] = dio_pad_sleep_en_59_gated_we; + reg_we_check[376] = dio_pad_sleep_en_60_gated_we; + reg_we_check[377] = dio_pad_sleep_en_61_gated_we; + reg_we_check[378] = dio_pad_sleep_en_62_gated_we; + reg_we_check[379] = dio_pad_sleep_en_63_gated_we; + reg_we_check[380] = dio_pad_sleep_en_64_gated_we; + reg_we_check[381] = dio_pad_sleep_en_65_gated_we; + reg_we_check[382] = dio_pad_sleep_en_66_gated_we; + reg_we_check[383] = dio_pad_sleep_en_67_gated_we; + reg_we_check[384] = dio_pad_sleep_en_68_gated_we; + reg_we_check[385] = dio_pad_sleep_en_69_gated_we; + reg_we_check[386] = dio_pad_sleep_en_70_gated_we; + reg_we_check[387] = dio_pad_sleep_en_71_gated_we; + reg_we_check[388] = dio_pad_sleep_en_72_gated_we; + reg_we_check[389] = dio_pad_sleep_mode_0_gated_we; + reg_we_check[390] = dio_pad_sleep_mode_1_gated_we; + reg_we_check[391] = dio_pad_sleep_mode_2_gated_we; + reg_we_check[392] = dio_pad_sleep_mode_3_gated_we; + reg_we_check[393] = dio_pad_sleep_mode_4_gated_we; + reg_we_check[394] = dio_pad_sleep_mode_5_gated_we; + reg_we_check[395] = dio_pad_sleep_mode_6_gated_we; + reg_we_check[396] = dio_pad_sleep_mode_7_gated_we; + reg_we_check[397] = dio_pad_sleep_mode_8_gated_we; + reg_we_check[398] = dio_pad_sleep_mode_9_gated_we; + reg_we_check[399] = dio_pad_sleep_mode_10_gated_we; + reg_we_check[400] = dio_pad_sleep_mode_11_gated_we; + reg_we_check[401] = dio_pad_sleep_mode_12_gated_we; + reg_we_check[402] = dio_pad_sleep_mode_13_gated_we; + reg_we_check[403] = dio_pad_sleep_mode_14_gated_we; + reg_we_check[404] = dio_pad_sleep_mode_15_gated_we; + reg_we_check[405] = dio_pad_sleep_mode_16_gated_we; + reg_we_check[406] = dio_pad_sleep_mode_17_gated_we; + reg_we_check[407] = dio_pad_sleep_mode_18_gated_we; + reg_we_check[408] = dio_pad_sleep_mode_19_gated_we; + reg_we_check[409] = dio_pad_sleep_mode_20_gated_we; + reg_we_check[410] = dio_pad_sleep_mode_21_gated_we; + reg_we_check[411] = dio_pad_sleep_mode_22_gated_we; + reg_we_check[412] = dio_pad_sleep_mode_23_gated_we; + reg_we_check[413] = dio_pad_sleep_mode_24_gated_we; + reg_we_check[414] = dio_pad_sleep_mode_25_gated_we; + reg_we_check[415] = dio_pad_sleep_mode_26_gated_we; + reg_we_check[416] = dio_pad_sleep_mode_27_gated_we; + reg_we_check[417] = dio_pad_sleep_mode_28_gated_we; + reg_we_check[418] = dio_pad_sleep_mode_29_gated_we; + reg_we_check[419] = dio_pad_sleep_mode_30_gated_we; + reg_we_check[420] = dio_pad_sleep_mode_31_gated_we; + reg_we_check[421] = dio_pad_sleep_mode_32_gated_we; + reg_we_check[422] = dio_pad_sleep_mode_33_gated_we; + reg_we_check[423] = dio_pad_sleep_mode_34_gated_we; + reg_we_check[424] = dio_pad_sleep_mode_35_gated_we; + reg_we_check[425] = dio_pad_sleep_mode_36_gated_we; + reg_we_check[426] = dio_pad_sleep_mode_37_gated_we; + reg_we_check[427] = dio_pad_sleep_mode_38_gated_we; + reg_we_check[428] = dio_pad_sleep_mode_39_gated_we; + reg_we_check[429] = dio_pad_sleep_mode_40_gated_we; + reg_we_check[430] = dio_pad_sleep_mode_41_gated_we; + reg_we_check[431] = dio_pad_sleep_mode_42_gated_we; + reg_we_check[432] = dio_pad_sleep_mode_43_gated_we; + reg_we_check[433] = dio_pad_sleep_mode_44_gated_we; + reg_we_check[434] = dio_pad_sleep_mode_45_gated_we; + reg_we_check[435] = dio_pad_sleep_mode_46_gated_we; + reg_we_check[436] = dio_pad_sleep_mode_47_gated_we; + reg_we_check[437] = dio_pad_sleep_mode_48_gated_we; + reg_we_check[438] = dio_pad_sleep_mode_49_gated_we; + reg_we_check[439] = dio_pad_sleep_mode_50_gated_we; + reg_we_check[440] = dio_pad_sleep_mode_51_gated_we; + reg_we_check[441] = dio_pad_sleep_mode_52_gated_we; + reg_we_check[442] = dio_pad_sleep_mode_53_gated_we; + reg_we_check[443] = dio_pad_sleep_mode_54_gated_we; + reg_we_check[444] = dio_pad_sleep_mode_55_gated_we; + reg_we_check[445] = dio_pad_sleep_mode_56_gated_we; + reg_we_check[446] = dio_pad_sleep_mode_57_gated_we; + reg_we_check[447] = dio_pad_sleep_mode_58_gated_we; + reg_we_check[448] = dio_pad_sleep_mode_59_gated_we; + reg_we_check[449] = dio_pad_sleep_mode_60_gated_we; + reg_we_check[450] = dio_pad_sleep_mode_61_gated_we; + reg_we_check[451] = dio_pad_sleep_mode_62_gated_we; + reg_we_check[452] = dio_pad_sleep_mode_63_gated_we; + reg_we_check[453] = dio_pad_sleep_mode_64_gated_we; + reg_we_check[454] = dio_pad_sleep_mode_65_gated_we; + reg_we_check[455] = dio_pad_sleep_mode_66_gated_we; + reg_we_check[456] = dio_pad_sleep_mode_67_gated_we; + reg_we_check[457] = dio_pad_sleep_mode_68_gated_we; + reg_we_check[458] = dio_pad_sleep_mode_69_gated_we; + reg_we_check[459] = dio_pad_sleep_mode_70_gated_we; + reg_we_check[460] = dio_pad_sleep_mode_71_gated_we; + reg_we_check[461] = dio_pad_sleep_mode_72_gated_we; + reg_we_check[462] = wkup_detector_regwen_0_we; + reg_we_check[463] = wkup_detector_regwen_1_we; + reg_we_check[464] = wkup_detector_regwen_2_we; + reg_we_check[465] = wkup_detector_regwen_3_we; + reg_we_check[466] = wkup_detector_regwen_4_we; + reg_we_check[467] = wkup_detector_regwen_5_we; + reg_we_check[468] = wkup_detector_regwen_6_we; + reg_we_check[469] = wkup_detector_regwen_7_we; + reg_we_check[470] = wkup_detector_en_0_we; + reg_we_check[471] = wkup_detector_en_1_we; + reg_we_check[472] = wkup_detector_en_2_we; + reg_we_check[473] = wkup_detector_en_3_we; + reg_we_check[474] = wkup_detector_en_4_we; + reg_we_check[475] = wkup_detector_en_5_we; + reg_we_check[476] = wkup_detector_en_6_we; + reg_we_check[477] = wkup_detector_en_7_we; + reg_we_check[478] = wkup_detector_0_we; + reg_we_check[479] = wkup_detector_1_we; + reg_we_check[480] = wkup_detector_2_we; + reg_we_check[481] = wkup_detector_3_we; + reg_we_check[482] = wkup_detector_4_we; + reg_we_check[483] = wkup_detector_5_we; + reg_we_check[484] = wkup_detector_6_we; + reg_we_check[485] = wkup_detector_7_we; + reg_we_check[486] = wkup_detector_cnt_th_0_we; + reg_we_check[487] = wkup_detector_cnt_th_1_we; + reg_we_check[488] = wkup_detector_cnt_th_2_we; + reg_we_check[489] = wkup_detector_cnt_th_3_we; + reg_we_check[490] = wkup_detector_cnt_th_4_we; + reg_we_check[491] = wkup_detector_cnt_th_5_we; + reg_we_check[492] = wkup_detector_cnt_th_6_we; + reg_we_check[493] = wkup_detector_cnt_th_7_we; + reg_we_check[494] = wkup_detector_padsel_0_gated_we; + reg_we_check[495] = wkup_detector_padsel_1_gated_we; + reg_we_check[496] = wkup_detector_padsel_2_gated_we; + reg_we_check[497] = wkup_detector_padsel_3_gated_we; + reg_we_check[498] = wkup_detector_padsel_4_gated_we; + reg_we_check[499] = wkup_detector_padsel_5_gated_we; + reg_we_check[500] = wkup_detector_padsel_6_gated_we; + reg_we_check[501] = wkup_detector_padsel_7_gated_we; + reg_we_check[502] = wkup_cause_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[1]: begin + reg_rdata_next[0] = mio_periph_insel_regwen_0_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = mio_periph_insel_regwen_1_qs; + end + + addr_hit[3]: begin + reg_rdata_next[0] = mio_periph_insel_regwen_2_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = mio_periph_insel_regwen_3_qs; + end + + addr_hit[5]: begin + reg_rdata_next[3:0] = mio_periph_insel_0_qs; + end + + addr_hit[6]: begin + reg_rdata_next[3:0] = mio_periph_insel_1_qs; + end + + addr_hit[7]: begin + reg_rdata_next[3:0] = mio_periph_insel_2_qs; + end + + addr_hit[8]: begin + reg_rdata_next[3:0] = mio_periph_insel_3_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = mio_outsel_regwen_0_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = mio_outsel_regwen_1_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = mio_outsel_regwen_2_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = mio_outsel_regwen_3_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = mio_outsel_regwen_4_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = mio_outsel_regwen_5_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = mio_outsel_regwen_6_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = mio_outsel_regwen_7_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = mio_outsel_regwen_8_qs; + end + + addr_hit[18]: begin + reg_rdata_next[0] = mio_outsel_regwen_9_qs; + end + + addr_hit[19]: begin + reg_rdata_next[0] = mio_outsel_regwen_10_qs; + end + + addr_hit[20]: begin + reg_rdata_next[0] = mio_outsel_regwen_11_qs; + end + + addr_hit[21]: begin + reg_rdata_next[2:0] = mio_outsel_0_qs; + end + + addr_hit[22]: begin + reg_rdata_next[2:0] = mio_outsel_1_qs; + end + + addr_hit[23]: begin + reg_rdata_next[2:0] = mio_outsel_2_qs; + end + + addr_hit[24]: begin + reg_rdata_next[2:0] = mio_outsel_3_qs; + end + + addr_hit[25]: begin + reg_rdata_next[2:0] = mio_outsel_4_qs; + end + + addr_hit[26]: begin + reg_rdata_next[2:0] = mio_outsel_5_qs; + end + + addr_hit[27]: begin + reg_rdata_next[2:0] = mio_outsel_6_qs; + end + + addr_hit[28]: begin + reg_rdata_next[2:0] = mio_outsel_7_qs; + end + + addr_hit[29]: begin + reg_rdata_next[2:0] = mio_outsel_8_qs; + end + + addr_hit[30]: begin + reg_rdata_next[2:0] = mio_outsel_9_qs; + end + + addr_hit[31]: begin + reg_rdata_next[2:0] = mio_outsel_10_qs; + end + + addr_hit[32]: begin + reg_rdata_next[2:0] = mio_outsel_11_qs; + end + + addr_hit[33]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; + end + + addr_hit[34]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; + end + + addr_hit[35]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; + end + + addr_hit[36]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; + end + + addr_hit[37]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; + end + + addr_hit[38]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; + end + + addr_hit[39]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; + end + + addr_hit[40]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; + end + + addr_hit[41]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; + end + + addr_hit[42]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; + end + + addr_hit[43]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; + end + + addr_hit[44]: begin + reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; + end + + addr_hit[45]: begin + reg_rdata_next[0] = mio_pad_attr_0_invert_0_qs; + reg_rdata_next[1] = mio_pad_attr_0_virtual_od_en_0_qs; + reg_rdata_next[2] = mio_pad_attr_0_pull_en_0_qs; + reg_rdata_next[3] = mio_pad_attr_0_pull_select_0_qs; + reg_rdata_next[4] = mio_pad_attr_0_keeper_en_0_qs; + reg_rdata_next[5] = mio_pad_attr_0_schmitt_en_0_qs; + reg_rdata_next[6] = mio_pad_attr_0_od_en_0_qs; + reg_rdata_next[7] = mio_pad_attr_0_input_disable_0_qs; + reg_rdata_next[17:16] = mio_pad_attr_0_slew_rate_0_qs; + reg_rdata_next[23:20] = mio_pad_attr_0_drive_strength_0_qs; + end + + addr_hit[46]: begin + reg_rdata_next[0] = mio_pad_attr_1_invert_1_qs; + reg_rdata_next[1] = mio_pad_attr_1_virtual_od_en_1_qs; + reg_rdata_next[2] = mio_pad_attr_1_pull_en_1_qs; + reg_rdata_next[3] = mio_pad_attr_1_pull_select_1_qs; + reg_rdata_next[4] = mio_pad_attr_1_keeper_en_1_qs; + reg_rdata_next[5] = mio_pad_attr_1_schmitt_en_1_qs; + reg_rdata_next[6] = mio_pad_attr_1_od_en_1_qs; + reg_rdata_next[7] = mio_pad_attr_1_input_disable_1_qs; + reg_rdata_next[17:16] = mio_pad_attr_1_slew_rate_1_qs; + reg_rdata_next[23:20] = mio_pad_attr_1_drive_strength_1_qs; + end + + addr_hit[47]: begin + reg_rdata_next[0] = mio_pad_attr_2_invert_2_qs; + reg_rdata_next[1] = mio_pad_attr_2_virtual_od_en_2_qs; + reg_rdata_next[2] = mio_pad_attr_2_pull_en_2_qs; + reg_rdata_next[3] = mio_pad_attr_2_pull_select_2_qs; + reg_rdata_next[4] = mio_pad_attr_2_keeper_en_2_qs; + reg_rdata_next[5] = mio_pad_attr_2_schmitt_en_2_qs; + reg_rdata_next[6] = mio_pad_attr_2_od_en_2_qs; + reg_rdata_next[7] = mio_pad_attr_2_input_disable_2_qs; + reg_rdata_next[17:16] = mio_pad_attr_2_slew_rate_2_qs; + reg_rdata_next[23:20] = mio_pad_attr_2_drive_strength_2_qs; + end + + addr_hit[48]: begin + reg_rdata_next[0] = mio_pad_attr_3_invert_3_qs; + reg_rdata_next[1] = mio_pad_attr_3_virtual_od_en_3_qs; + reg_rdata_next[2] = mio_pad_attr_3_pull_en_3_qs; + reg_rdata_next[3] = mio_pad_attr_3_pull_select_3_qs; + reg_rdata_next[4] = mio_pad_attr_3_keeper_en_3_qs; + reg_rdata_next[5] = mio_pad_attr_3_schmitt_en_3_qs; + reg_rdata_next[6] = mio_pad_attr_3_od_en_3_qs; + reg_rdata_next[7] = mio_pad_attr_3_input_disable_3_qs; + reg_rdata_next[17:16] = mio_pad_attr_3_slew_rate_3_qs; + reg_rdata_next[23:20] = mio_pad_attr_3_drive_strength_3_qs; + end + + addr_hit[49]: begin + reg_rdata_next[0] = mio_pad_attr_4_invert_4_qs; + reg_rdata_next[1] = mio_pad_attr_4_virtual_od_en_4_qs; + reg_rdata_next[2] = mio_pad_attr_4_pull_en_4_qs; + reg_rdata_next[3] = mio_pad_attr_4_pull_select_4_qs; + reg_rdata_next[4] = mio_pad_attr_4_keeper_en_4_qs; + reg_rdata_next[5] = mio_pad_attr_4_schmitt_en_4_qs; + reg_rdata_next[6] = mio_pad_attr_4_od_en_4_qs; + reg_rdata_next[7] = mio_pad_attr_4_input_disable_4_qs; + reg_rdata_next[17:16] = mio_pad_attr_4_slew_rate_4_qs; + reg_rdata_next[23:20] = mio_pad_attr_4_drive_strength_4_qs; + end + + addr_hit[50]: begin + reg_rdata_next[0] = mio_pad_attr_5_invert_5_qs; + reg_rdata_next[1] = mio_pad_attr_5_virtual_od_en_5_qs; + reg_rdata_next[2] = mio_pad_attr_5_pull_en_5_qs; + reg_rdata_next[3] = mio_pad_attr_5_pull_select_5_qs; + reg_rdata_next[4] = mio_pad_attr_5_keeper_en_5_qs; + reg_rdata_next[5] = mio_pad_attr_5_schmitt_en_5_qs; + reg_rdata_next[6] = mio_pad_attr_5_od_en_5_qs; + reg_rdata_next[7] = mio_pad_attr_5_input_disable_5_qs; + reg_rdata_next[17:16] = mio_pad_attr_5_slew_rate_5_qs; + reg_rdata_next[23:20] = mio_pad_attr_5_drive_strength_5_qs; + end + + addr_hit[51]: begin + reg_rdata_next[0] = mio_pad_attr_6_invert_6_qs; + reg_rdata_next[1] = mio_pad_attr_6_virtual_od_en_6_qs; + reg_rdata_next[2] = mio_pad_attr_6_pull_en_6_qs; + reg_rdata_next[3] = mio_pad_attr_6_pull_select_6_qs; + reg_rdata_next[4] = mio_pad_attr_6_keeper_en_6_qs; + reg_rdata_next[5] = mio_pad_attr_6_schmitt_en_6_qs; + reg_rdata_next[6] = mio_pad_attr_6_od_en_6_qs; + reg_rdata_next[7] = mio_pad_attr_6_input_disable_6_qs; + reg_rdata_next[17:16] = mio_pad_attr_6_slew_rate_6_qs; + reg_rdata_next[23:20] = mio_pad_attr_6_drive_strength_6_qs; + end + + addr_hit[52]: begin + reg_rdata_next[0] = mio_pad_attr_7_invert_7_qs; + reg_rdata_next[1] = mio_pad_attr_7_virtual_od_en_7_qs; + reg_rdata_next[2] = mio_pad_attr_7_pull_en_7_qs; + reg_rdata_next[3] = mio_pad_attr_7_pull_select_7_qs; + reg_rdata_next[4] = mio_pad_attr_7_keeper_en_7_qs; + reg_rdata_next[5] = mio_pad_attr_7_schmitt_en_7_qs; + reg_rdata_next[6] = mio_pad_attr_7_od_en_7_qs; + reg_rdata_next[7] = mio_pad_attr_7_input_disable_7_qs; + reg_rdata_next[17:16] = mio_pad_attr_7_slew_rate_7_qs; + reg_rdata_next[23:20] = mio_pad_attr_7_drive_strength_7_qs; + end + + addr_hit[53]: begin + reg_rdata_next[0] = mio_pad_attr_8_invert_8_qs; + reg_rdata_next[1] = mio_pad_attr_8_virtual_od_en_8_qs; + reg_rdata_next[2] = mio_pad_attr_8_pull_en_8_qs; + reg_rdata_next[3] = mio_pad_attr_8_pull_select_8_qs; + reg_rdata_next[4] = mio_pad_attr_8_keeper_en_8_qs; + reg_rdata_next[5] = mio_pad_attr_8_schmitt_en_8_qs; + reg_rdata_next[6] = mio_pad_attr_8_od_en_8_qs; + reg_rdata_next[7] = mio_pad_attr_8_input_disable_8_qs; + reg_rdata_next[17:16] = mio_pad_attr_8_slew_rate_8_qs; + reg_rdata_next[23:20] = mio_pad_attr_8_drive_strength_8_qs; + end + + addr_hit[54]: begin + reg_rdata_next[0] = mio_pad_attr_9_invert_9_qs; + reg_rdata_next[1] = mio_pad_attr_9_virtual_od_en_9_qs; + reg_rdata_next[2] = mio_pad_attr_9_pull_en_9_qs; + reg_rdata_next[3] = mio_pad_attr_9_pull_select_9_qs; + reg_rdata_next[4] = mio_pad_attr_9_keeper_en_9_qs; + reg_rdata_next[5] = mio_pad_attr_9_schmitt_en_9_qs; + reg_rdata_next[6] = mio_pad_attr_9_od_en_9_qs; + reg_rdata_next[7] = mio_pad_attr_9_input_disable_9_qs; + reg_rdata_next[17:16] = mio_pad_attr_9_slew_rate_9_qs; + reg_rdata_next[23:20] = mio_pad_attr_9_drive_strength_9_qs; + end + + addr_hit[55]: begin + reg_rdata_next[0] = mio_pad_attr_10_invert_10_qs; + reg_rdata_next[1] = mio_pad_attr_10_virtual_od_en_10_qs; + reg_rdata_next[2] = mio_pad_attr_10_pull_en_10_qs; + reg_rdata_next[3] = mio_pad_attr_10_pull_select_10_qs; + reg_rdata_next[4] = mio_pad_attr_10_keeper_en_10_qs; + reg_rdata_next[5] = mio_pad_attr_10_schmitt_en_10_qs; + reg_rdata_next[6] = mio_pad_attr_10_od_en_10_qs; + reg_rdata_next[7] = mio_pad_attr_10_input_disable_10_qs; + reg_rdata_next[17:16] = mio_pad_attr_10_slew_rate_10_qs; + reg_rdata_next[23:20] = mio_pad_attr_10_drive_strength_10_qs; + end + + addr_hit[56]: begin + reg_rdata_next[0] = mio_pad_attr_11_invert_11_qs; + reg_rdata_next[1] = mio_pad_attr_11_virtual_od_en_11_qs; + reg_rdata_next[2] = mio_pad_attr_11_pull_en_11_qs; + reg_rdata_next[3] = mio_pad_attr_11_pull_select_11_qs; + reg_rdata_next[4] = mio_pad_attr_11_keeper_en_11_qs; + reg_rdata_next[5] = mio_pad_attr_11_schmitt_en_11_qs; + reg_rdata_next[6] = mio_pad_attr_11_od_en_11_qs; + reg_rdata_next[7] = mio_pad_attr_11_input_disable_11_qs; + reg_rdata_next[17:16] = mio_pad_attr_11_slew_rate_11_qs; + reg_rdata_next[23:20] = mio_pad_attr_11_drive_strength_11_qs; + end + + addr_hit[57]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_0_qs; + end + + addr_hit[58]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_1_qs; + end + + addr_hit[59]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_2_qs; + end + + addr_hit[60]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_3_qs; + end + + addr_hit[61]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_4_qs; + end + + addr_hit[62]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_5_qs; + end + + addr_hit[63]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_6_qs; + end + + addr_hit[64]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_7_qs; + end + + addr_hit[65]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_8_qs; + end + + addr_hit[66]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_9_qs; + end + + addr_hit[67]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_10_qs; + end + + addr_hit[68]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_11_qs; + end + + addr_hit[69]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_12_qs; + end + + addr_hit[70]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_13_qs; + end + + addr_hit[71]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_14_qs; + end + + addr_hit[72]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_15_qs; + end + + addr_hit[73]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_16_qs; + end + + addr_hit[74]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_17_qs; + end + + addr_hit[75]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_18_qs; + end + + addr_hit[76]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_19_qs; + end + + addr_hit[77]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_20_qs; + end + + addr_hit[78]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_21_qs; + end + + addr_hit[79]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_22_qs; + end + + addr_hit[80]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_23_qs; + end + + addr_hit[81]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_24_qs; + end + + addr_hit[82]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_25_qs; + end + + addr_hit[83]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_26_qs; + end + + addr_hit[84]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_27_qs; + end + + addr_hit[85]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_28_qs; + end + + addr_hit[86]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_29_qs; + end + + addr_hit[87]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_30_qs; + end + + addr_hit[88]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_31_qs; + end + + addr_hit[89]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_32_qs; + end + + addr_hit[90]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_33_qs; + end + + addr_hit[91]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_34_qs; + end + + addr_hit[92]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_35_qs; + end + + addr_hit[93]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_36_qs; + end + + addr_hit[94]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_37_qs; + end + + addr_hit[95]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_38_qs; + end + + addr_hit[96]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_39_qs; + end + + addr_hit[97]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_40_qs; + end + + addr_hit[98]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_41_qs; + end + + addr_hit[99]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_42_qs; + end + + addr_hit[100]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_43_qs; + end + + addr_hit[101]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_44_qs; + end + + addr_hit[102]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_45_qs; + end + + addr_hit[103]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_46_qs; + end + + addr_hit[104]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_47_qs; + end + + addr_hit[105]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_48_qs; + end + + addr_hit[106]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_49_qs; + end + + addr_hit[107]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_50_qs; + end + + addr_hit[108]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_51_qs; + end + + addr_hit[109]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_52_qs; + end + + addr_hit[110]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_53_qs; + end + + addr_hit[111]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_54_qs; + end + + addr_hit[112]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_55_qs; + end + + addr_hit[113]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_56_qs; + end + + addr_hit[114]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_57_qs; + end + + addr_hit[115]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_58_qs; + end + + addr_hit[116]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_59_qs; + end + + addr_hit[117]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_60_qs; + end + + addr_hit[118]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_61_qs; + end + + addr_hit[119]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_62_qs; + end + + addr_hit[120]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_63_qs; + end + + addr_hit[121]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_64_qs; + end + + addr_hit[122]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_65_qs; + end + + addr_hit[123]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_66_qs; + end + + addr_hit[124]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_67_qs; + end + + addr_hit[125]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_68_qs; + end + + addr_hit[126]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_69_qs; + end + + addr_hit[127]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_70_qs; + end + + addr_hit[128]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_71_qs; + end + + addr_hit[129]: begin + reg_rdata_next[0] = dio_pad_attr_regwen_72_qs; + end + + addr_hit[130]: begin + reg_rdata_next[0] = dio_pad_attr_0_invert_0_qs; + reg_rdata_next[1] = dio_pad_attr_0_virtual_od_en_0_qs; + reg_rdata_next[2] = dio_pad_attr_0_pull_en_0_qs; + reg_rdata_next[3] = dio_pad_attr_0_pull_select_0_qs; + reg_rdata_next[4] = dio_pad_attr_0_keeper_en_0_qs; + reg_rdata_next[5] = dio_pad_attr_0_schmitt_en_0_qs; + reg_rdata_next[6] = dio_pad_attr_0_od_en_0_qs; + reg_rdata_next[7] = dio_pad_attr_0_input_disable_0_qs; + reg_rdata_next[17:16] = dio_pad_attr_0_slew_rate_0_qs; + reg_rdata_next[23:20] = dio_pad_attr_0_drive_strength_0_qs; + end + + addr_hit[131]: begin + reg_rdata_next[0] = dio_pad_attr_1_invert_1_qs; + reg_rdata_next[1] = dio_pad_attr_1_virtual_od_en_1_qs; + reg_rdata_next[2] = dio_pad_attr_1_pull_en_1_qs; + reg_rdata_next[3] = dio_pad_attr_1_pull_select_1_qs; + reg_rdata_next[4] = dio_pad_attr_1_keeper_en_1_qs; + reg_rdata_next[5] = dio_pad_attr_1_schmitt_en_1_qs; + reg_rdata_next[6] = dio_pad_attr_1_od_en_1_qs; + reg_rdata_next[7] = dio_pad_attr_1_input_disable_1_qs; + reg_rdata_next[17:16] = dio_pad_attr_1_slew_rate_1_qs; + reg_rdata_next[23:20] = dio_pad_attr_1_drive_strength_1_qs; + end + + addr_hit[132]: begin + reg_rdata_next[0] = dio_pad_attr_2_invert_2_qs; + reg_rdata_next[1] = dio_pad_attr_2_virtual_od_en_2_qs; + reg_rdata_next[2] = dio_pad_attr_2_pull_en_2_qs; + reg_rdata_next[3] = dio_pad_attr_2_pull_select_2_qs; + reg_rdata_next[4] = dio_pad_attr_2_keeper_en_2_qs; + reg_rdata_next[5] = dio_pad_attr_2_schmitt_en_2_qs; + reg_rdata_next[6] = dio_pad_attr_2_od_en_2_qs; + reg_rdata_next[7] = dio_pad_attr_2_input_disable_2_qs; + reg_rdata_next[17:16] = dio_pad_attr_2_slew_rate_2_qs; + reg_rdata_next[23:20] = dio_pad_attr_2_drive_strength_2_qs; + end + + addr_hit[133]: begin + reg_rdata_next[0] = dio_pad_attr_3_invert_3_qs; + reg_rdata_next[1] = dio_pad_attr_3_virtual_od_en_3_qs; + reg_rdata_next[2] = dio_pad_attr_3_pull_en_3_qs; + reg_rdata_next[3] = dio_pad_attr_3_pull_select_3_qs; + reg_rdata_next[4] = dio_pad_attr_3_keeper_en_3_qs; + reg_rdata_next[5] = dio_pad_attr_3_schmitt_en_3_qs; + reg_rdata_next[6] = dio_pad_attr_3_od_en_3_qs; + reg_rdata_next[7] = dio_pad_attr_3_input_disable_3_qs; + reg_rdata_next[17:16] = dio_pad_attr_3_slew_rate_3_qs; + reg_rdata_next[23:20] = dio_pad_attr_3_drive_strength_3_qs; + end + + addr_hit[134]: begin + reg_rdata_next[0] = dio_pad_attr_4_invert_4_qs; + reg_rdata_next[1] = dio_pad_attr_4_virtual_od_en_4_qs; + reg_rdata_next[2] = dio_pad_attr_4_pull_en_4_qs; + reg_rdata_next[3] = dio_pad_attr_4_pull_select_4_qs; + reg_rdata_next[4] = dio_pad_attr_4_keeper_en_4_qs; + reg_rdata_next[5] = dio_pad_attr_4_schmitt_en_4_qs; + reg_rdata_next[6] = dio_pad_attr_4_od_en_4_qs; + reg_rdata_next[7] = dio_pad_attr_4_input_disable_4_qs; + reg_rdata_next[17:16] = dio_pad_attr_4_slew_rate_4_qs; + reg_rdata_next[23:20] = dio_pad_attr_4_drive_strength_4_qs; + end + + addr_hit[135]: begin + reg_rdata_next[0] = dio_pad_attr_5_invert_5_qs; + reg_rdata_next[1] = dio_pad_attr_5_virtual_od_en_5_qs; + reg_rdata_next[2] = dio_pad_attr_5_pull_en_5_qs; + reg_rdata_next[3] = dio_pad_attr_5_pull_select_5_qs; + reg_rdata_next[4] = dio_pad_attr_5_keeper_en_5_qs; + reg_rdata_next[5] = dio_pad_attr_5_schmitt_en_5_qs; + reg_rdata_next[6] = dio_pad_attr_5_od_en_5_qs; + reg_rdata_next[7] = dio_pad_attr_5_input_disable_5_qs; + reg_rdata_next[17:16] = dio_pad_attr_5_slew_rate_5_qs; + reg_rdata_next[23:20] = dio_pad_attr_5_drive_strength_5_qs; + end + + addr_hit[136]: begin + reg_rdata_next[0] = dio_pad_attr_6_invert_6_qs; + reg_rdata_next[1] = dio_pad_attr_6_virtual_od_en_6_qs; + reg_rdata_next[2] = dio_pad_attr_6_pull_en_6_qs; + reg_rdata_next[3] = dio_pad_attr_6_pull_select_6_qs; + reg_rdata_next[4] = dio_pad_attr_6_keeper_en_6_qs; + reg_rdata_next[5] = dio_pad_attr_6_schmitt_en_6_qs; + reg_rdata_next[6] = dio_pad_attr_6_od_en_6_qs; + reg_rdata_next[7] = dio_pad_attr_6_input_disable_6_qs; + reg_rdata_next[17:16] = dio_pad_attr_6_slew_rate_6_qs; + reg_rdata_next[23:20] = dio_pad_attr_6_drive_strength_6_qs; + end + + addr_hit[137]: begin + reg_rdata_next[0] = dio_pad_attr_7_invert_7_qs; + reg_rdata_next[1] = dio_pad_attr_7_virtual_od_en_7_qs; + reg_rdata_next[2] = dio_pad_attr_7_pull_en_7_qs; + reg_rdata_next[3] = dio_pad_attr_7_pull_select_7_qs; + reg_rdata_next[4] = dio_pad_attr_7_keeper_en_7_qs; + reg_rdata_next[5] = dio_pad_attr_7_schmitt_en_7_qs; + reg_rdata_next[6] = dio_pad_attr_7_od_en_7_qs; + reg_rdata_next[7] = dio_pad_attr_7_input_disable_7_qs; + reg_rdata_next[17:16] = dio_pad_attr_7_slew_rate_7_qs; + reg_rdata_next[23:20] = dio_pad_attr_7_drive_strength_7_qs; + end + + addr_hit[138]: begin + reg_rdata_next[0] = dio_pad_attr_8_invert_8_qs; + reg_rdata_next[1] = dio_pad_attr_8_virtual_od_en_8_qs; + reg_rdata_next[2] = dio_pad_attr_8_pull_en_8_qs; + reg_rdata_next[3] = dio_pad_attr_8_pull_select_8_qs; + reg_rdata_next[4] = dio_pad_attr_8_keeper_en_8_qs; + reg_rdata_next[5] = dio_pad_attr_8_schmitt_en_8_qs; + reg_rdata_next[6] = dio_pad_attr_8_od_en_8_qs; + reg_rdata_next[7] = dio_pad_attr_8_input_disable_8_qs; + reg_rdata_next[17:16] = dio_pad_attr_8_slew_rate_8_qs; + reg_rdata_next[23:20] = dio_pad_attr_8_drive_strength_8_qs; + end + + addr_hit[139]: begin + reg_rdata_next[0] = dio_pad_attr_9_invert_9_qs; + reg_rdata_next[1] = dio_pad_attr_9_virtual_od_en_9_qs; + reg_rdata_next[2] = dio_pad_attr_9_pull_en_9_qs; + reg_rdata_next[3] = dio_pad_attr_9_pull_select_9_qs; + reg_rdata_next[4] = dio_pad_attr_9_keeper_en_9_qs; + reg_rdata_next[5] = dio_pad_attr_9_schmitt_en_9_qs; + reg_rdata_next[6] = dio_pad_attr_9_od_en_9_qs; + reg_rdata_next[7] = dio_pad_attr_9_input_disable_9_qs; + reg_rdata_next[17:16] = dio_pad_attr_9_slew_rate_9_qs; + reg_rdata_next[23:20] = dio_pad_attr_9_drive_strength_9_qs; + end + + addr_hit[140]: begin + reg_rdata_next[0] = dio_pad_attr_10_invert_10_qs; + reg_rdata_next[1] = dio_pad_attr_10_virtual_od_en_10_qs; + reg_rdata_next[2] = dio_pad_attr_10_pull_en_10_qs; + reg_rdata_next[3] = dio_pad_attr_10_pull_select_10_qs; + reg_rdata_next[4] = dio_pad_attr_10_keeper_en_10_qs; + reg_rdata_next[5] = dio_pad_attr_10_schmitt_en_10_qs; + reg_rdata_next[6] = dio_pad_attr_10_od_en_10_qs; + reg_rdata_next[7] = dio_pad_attr_10_input_disable_10_qs; + reg_rdata_next[17:16] = dio_pad_attr_10_slew_rate_10_qs; + reg_rdata_next[23:20] = dio_pad_attr_10_drive_strength_10_qs; + end + + addr_hit[141]: begin + reg_rdata_next[0] = dio_pad_attr_11_invert_11_qs; + reg_rdata_next[1] = dio_pad_attr_11_virtual_od_en_11_qs; + reg_rdata_next[2] = dio_pad_attr_11_pull_en_11_qs; + reg_rdata_next[3] = dio_pad_attr_11_pull_select_11_qs; + reg_rdata_next[4] = dio_pad_attr_11_keeper_en_11_qs; + reg_rdata_next[5] = dio_pad_attr_11_schmitt_en_11_qs; + reg_rdata_next[6] = dio_pad_attr_11_od_en_11_qs; + reg_rdata_next[7] = dio_pad_attr_11_input_disable_11_qs; + reg_rdata_next[17:16] = dio_pad_attr_11_slew_rate_11_qs; + reg_rdata_next[23:20] = dio_pad_attr_11_drive_strength_11_qs; + end + + addr_hit[142]: begin + reg_rdata_next[0] = dio_pad_attr_12_invert_12_qs; + reg_rdata_next[1] = dio_pad_attr_12_virtual_od_en_12_qs; + reg_rdata_next[2] = dio_pad_attr_12_pull_en_12_qs; + reg_rdata_next[3] = dio_pad_attr_12_pull_select_12_qs; + reg_rdata_next[4] = dio_pad_attr_12_keeper_en_12_qs; + reg_rdata_next[5] = dio_pad_attr_12_schmitt_en_12_qs; + reg_rdata_next[6] = dio_pad_attr_12_od_en_12_qs; + reg_rdata_next[7] = dio_pad_attr_12_input_disable_12_qs; + reg_rdata_next[17:16] = dio_pad_attr_12_slew_rate_12_qs; + reg_rdata_next[23:20] = dio_pad_attr_12_drive_strength_12_qs; + end + + addr_hit[143]: begin + reg_rdata_next[0] = dio_pad_attr_13_invert_13_qs; + reg_rdata_next[1] = dio_pad_attr_13_virtual_od_en_13_qs; + reg_rdata_next[2] = dio_pad_attr_13_pull_en_13_qs; + reg_rdata_next[3] = dio_pad_attr_13_pull_select_13_qs; + reg_rdata_next[4] = dio_pad_attr_13_keeper_en_13_qs; + reg_rdata_next[5] = dio_pad_attr_13_schmitt_en_13_qs; + reg_rdata_next[6] = dio_pad_attr_13_od_en_13_qs; + reg_rdata_next[7] = dio_pad_attr_13_input_disable_13_qs; + reg_rdata_next[17:16] = dio_pad_attr_13_slew_rate_13_qs; + reg_rdata_next[23:20] = dio_pad_attr_13_drive_strength_13_qs; + end + + addr_hit[144]: begin + reg_rdata_next[0] = dio_pad_attr_14_invert_14_qs; + reg_rdata_next[1] = dio_pad_attr_14_virtual_od_en_14_qs; + reg_rdata_next[2] = dio_pad_attr_14_pull_en_14_qs; + reg_rdata_next[3] = dio_pad_attr_14_pull_select_14_qs; + reg_rdata_next[4] = dio_pad_attr_14_keeper_en_14_qs; + reg_rdata_next[5] = dio_pad_attr_14_schmitt_en_14_qs; + reg_rdata_next[6] = dio_pad_attr_14_od_en_14_qs; + reg_rdata_next[7] = dio_pad_attr_14_input_disable_14_qs; + reg_rdata_next[17:16] = dio_pad_attr_14_slew_rate_14_qs; + reg_rdata_next[23:20] = dio_pad_attr_14_drive_strength_14_qs; + end + + addr_hit[145]: begin + reg_rdata_next[0] = dio_pad_attr_15_invert_15_qs; + reg_rdata_next[1] = dio_pad_attr_15_virtual_od_en_15_qs; + reg_rdata_next[2] = dio_pad_attr_15_pull_en_15_qs; + reg_rdata_next[3] = dio_pad_attr_15_pull_select_15_qs; + reg_rdata_next[4] = dio_pad_attr_15_keeper_en_15_qs; + reg_rdata_next[5] = dio_pad_attr_15_schmitt_en_15_qs; + reg_rdata_next[6] = dio_pad_attr_15_od_en_15_qs; + reg_rdata_next[7] = dio_pad_attr_15_input_disable_15_qs; + reg_rdata_next[17:16] = dio_pad_attr_15_slew_rate_15_qs; + reg_rdata_next[23:20] = dio_pad_attr_15_drive_strength_15_qs; + end + + addr_hit[146]: begin + reg_rdata_next[0] = dio_pad_attr_16_invert_16_qs; + reg_rdata_next[1] = dio_pad_attr_16_virtual_od_en_16_qs; + reg_rdata_next[2] = dio_pad_attr_16_pull_en_16_qs; + reg_rdata_next[3] = dio_pad_attr_16_pull_select_16_qs; + reg_rdata_next[4] = dio_pad_attr_16_keeper_en_16_qs; + reg_rdata_next[5] = dio_pad_attr_16_schmitt_en_16_qs; + reg_rdata_next[6] = dio_pad_attr_16_od_en_16_qs; + reg_rdata_next[7] = dio_pad_attr_16_input_disable_16_qs; + reg_rdata_next[17:16] = dio_pad_attr_16_slew_rate_16_qs; + reg_rdata_next[23:20] = dio_pad_attr_16_drive_strength_16_qs; + end + + addr_hit[147]: begin + reg_rdata_next[0] = dio_pad_attr_17_invert_17_qs; + reg_rdata_next[1] = dio_pad_attr_17_virtual_od_en_17_qs; + reg_rdata_next[2] = dio_pad_attr_17_pull_en_17_qs; + reg_rdata_next[3] = dio_pad_attr_17_pull_select_17_qs; + reg_rdata_next[4] = dio_pad_attr_17_keeper_en_17_qs; + reg_rdata_next[5] = dio_pad_attr_17_schmitt_en_17_qs; + reg_rdata_next[6] = dio_pad_attr_17_od_en_17_qs; + reg_rdata_next[7] = dio_pad_attr_17_input_disable_17_qs; + reg_rdata_next[17:16] = dio_pad_attr_17_slew_rate_17_qs; + reg_rdata_next[23:20] = dio_pad_attr_17_drive_strength_17_qs; + end + + addr_hit[148]: begin + reg_rdata_next[0] = dio_pad_attr_18_invert_18_qs; + reg_rdata_next[1] = dio_pad_attr_18_virtual_od_en_18_qs; + reg_rdata_next[2] = dio_pad_attr_18_pull_en_18_qs; + reg_rdata_next[3] = dio_pad_attr_18_pull_select_18_qs; + reg_rdata_next[4] = dio_pad_attr_18_keeper_en_18_qs; + reg_rdata_next[5] = dio_pad_attr_18_schmitt_en_18_qs; + reg_rdata_next[6] = dio_pad_attr_18_od_en_18_qs; + reg_rdata_next[7] = dio_pad_attr_18_input_disable_18_qs; + reg_rdata_next[17:16] = dio_pad_attr_18_slew_rate_18_qs; + reg_rdata_next[23:20] = dio_pad_attr_18_drive_strength_18_qs; + end + + addr_hit[149]: begin + reg_rdata_next[0] = dio_pad_attr_19_invert_19_qs; + reg_rdata_next[1] = dio_pad_attr_19_virtual_od_en_19_qs; + reg_rdata_next[2] = dio_pad_attr_19_pull_en_19_qs; + reg_rdata_next[3] = dio_pad_attr_19_pull_select_19_qs; + reg_rdata_next[4] = dio_pad_attr_19_keeper_en_19_qs; + reg_rdata_next[5] = dio_pad_attr_19_schmitt_en_19_qs; + reg_rdata_next[6] = dio_pad_attr_19_od_en_19_qs; + reg_rdata_next[7] = dio_pad_attr_19_input_disable_19_qs; + reg_rdata_next[17:16] = dio_pad_attr_19_slew_rate_19_qs; + reg_rdata_next[23:20] = dio_pad_attr_19_drive_strength_19_qs; + end + + addr_hit[150]: begin + reg_rdata_next[0] = dio_pad_attr_20_invert_20_qs; + reg_rdata_next[1] = dio_pad_attr_20_virtual_od_en_20_qs; + reg_rdata_next[2] = dio_pad_attr_20_pull_en_20_qs; + reg_rdata_next[3] = dio_pad_attr_20_pull_select_20_qs; + reg_rdata_next[4] = dio_pad_attr_20_keeper_en_20_qs; + reg_rdata_next[5] = dio_pad_attr_20_schmitt_en_20_qs; + reg_rdata_next[6] = dio_pad_attr_20_od_en_20_qs; + reg_rdata_next[7] = dio_pad_attr_20_input_disable_20_qs; + reg_rdata_next[17:16] = dio_pad_attr_20_slew_rate_20_qs; + reg_rdata_next[23:20] = dio_pad_attr_20_drive_strength_20_qs; + end + + addr_hit[151]: begin + reg_rdata_next[0] = dio_pad_attr_21_invert_21_qs; + reg_rdata_next[1] = dio_pad_attr_21_virtual_od_en_21_qs; + reg_rdata_next[2] = dio_pad_attr_21_pull_en_21_qs; + reg_rdata_next[3] = dio_pad_attr_21_pull_select_21_qs; + reg_rdata_next[4] = dio_pad_attr_21_keeper_en_21_qs; + reg_rdata_next[5] = dio_pad_attr_21_schmitt_en_21_qs; + reg_rdata_next[6] = dio_pad_attr_21_od_en_21_qs; + reg_rdata_next[7] = dio_pad_attr_21_input_disable_21_qs; + reg_rdata_next[17:16] = dio_pad_attr_21_slew_rate_21_qs; + reg_rdata_next[23:20] = dio_pad_attr_21_drive_strength_21_qs; + end + + addr_hit[152]: begin + reg_rdata_next[0] = dio_pad_attr_22_invert_22_qs; + reg_rdata_next[1] = dio_pad_attr_22_virtual_od_en_22_qs; + reg_rdata_next[2] = dio_pad_attr_22_pull_en_22_qs; + reg_rdata_next[3] = dio_pad_attr_22_pull_select_22_qs; + reg_rdata_next[4] = dio_pad_attr_22_keeper_en_22_qs; + reg_rdata_next[5] = dio_pad_attr_22_schmitt_en_22_qs; + reg_rdata_next[6] = dio_pad_attr_22_od_en_22_qs; + reg_rdata_next[7] = dio_pad_attr_22_input_disable_22_qs; + reg_rdata_next[17:16] = dio_pad_attr_22_slew_rate_22_qs; + reg_rdata_next[23:20] = dio_pad_attr_22_drive_strength_22_qs; + end + + addr_hit[153]: begin + reg_rdata_next[0] = dio_pad_attr_23_invert_23_qs; + reg_rdata_next[1] = dio_pad_attr_23_virtual_od_en_23_qs; + reg_rdata_next[2] = dio_pad_attr_23_pull_en_23_qs; + reg_rdata_next[3] = dio_pad_attr_23_pull_select_23_qs; + reg_rdata_next[4] = dio_pad_attr_23_keeper_en_23_qs; + reg_rdata_next[5] = dio_pad_attr_23_schmitt_en_23_qs; + reg_rdata_next[6] = dio_pad_attr_23_od_en_23_qs; + reg_rdata_next[7] = dio_pad_attr_23_input_disable_23_qs; + reg_rdata_next[17:16] = dio_pad_attr_23_slew_rate_23_qs; + reg_rdata_next[23:20] = dio_pad_attr_23_drive_strength_23_qs; + end + + addr_hit[154]: begin + reg_rdata_next[0] = dio_pad_attr_24_invert_24_qs; + reg_rdata_next[1] = dio_pad_attr_24_virtual_od_en_24_qs; + reg_rdata_next[2] = dio_pad_attr_24_pull_en_24_qs; + reg_rdata_next[3] = dio_pad_attr_24_pull_select_24_qs; + reg_rdata_next[4] = dio_pad_attr_24_keeper_en_24_qs; + reg_rdata_next[5] = dio_pad_attr_24_schmitt_en_24_qs; + reg_rdata_next[6] = dio_pad_attr_24_od_en_24_qs; + reg_rdata_next[7] = dio_pad_attr_24_input_disable_24_qs; + reg_rdata_next[17:16] = dio_pad_attr_24_slew_rate_24_qs; + reg_rdata_next[23:20] = dio_pad_attr_24_drive_strength_24_qs; + end + + addr_hit[155]: begin + reg_rdata_next[0] = dio_pad_attr_25_invert_25_qs; + reg_rdata_next[1] = dio_pad_attr_25_virtual_od_en_25_qs; + reg_rdata_next[2] = dio_pad_attr_25_pull_en_25_qs; + reg_rdata_next[3] = dio_pad_attr_25_pull_select_25_qs; + reg_rdata_next[4] = dio_pad_attr_25_keeper_en_25_qs; + reg_rdata_next[5] = dio_pad_attr_25_schmitt_en_25_qs; + reg_rdata_next[6] = dio_pad_attr_25_od_en_25_qs; + reg_rdata_next[7] = dio_pad_attr_25_input_disable_25_qs; + reg_rdata_next[17:16] = dio_pad_attr_25_slew_rate_25_qs; + reg_rdata_next[23:20] = dio_pad_attr_25_drive_strength_25_qs; + end + + addr_hit[156]: begin + reg_rdata_next[0] = dio_pad_attr_26_invert_26_qs; + reg_rdata_next[1] = dio_pad_attr_26_virtual_od_en_26_qs; + reg_rdata_next[2] = dio_pad_attr_26_pull_en_26_qs; + reg_rdata_next[3] = dio_pad_attr_26_pull_select_26_qs; + reg_rdata_next[4] = dio_pad_attr_26_keeper_en_26_qs; + reg_rdata_next[5] = dio_pad_attr_26_schmitt_en_26_qs; + reg_rdata_next[6] = dio_pad_attr_26_od_en_26_qs; + reg_rdata_next[7] = dio_pad_attr_26_input_disable_26_qs; + reg_rdata_next[17:16] = dio_pad_attr_26_slew_rate_26_qs; + reg_rdata_next[23:20] = dio_pad_attr_26_drive_strength_26_qs; + end + + addr_hit[157]: begin + reg_rdata_next[0] = dio_pad_attr_27_invert_27_qs; + reg_rdata_next[1] = dio_pad_attr_27_virtual_od_en_27_qs; + reg_rdata_next[2] = dio_pad_attr_27_pull_en_27_qs; + reg_rdata_next[3] = dio_pad_attr_27_pull_select_27_qs; + reg_rdata_next[4] = dio_pad_attr_27_keeper_en_27_qs; + reg_rdata_next[5] = dio_pad_attr_27_schmitt_en_27_qs; + reg_rdata_next[6] = dio_pad_attr_27_od_en_27_qs; + reg_rdata_next[7] = dio_pad_attr_27_input_disable_27_qs; + reg_rdata_next[17:16] = dio_pad_attr_27_slew_rate_27_qs; + reg_rdata_next[23:20] = dio_pad_attr_27_drive_strength_27_qs; + end + + addr_hit[158]: begin + reg_rdata_next[0] = dio_pad_attr_28_invert_28_qs; + reg_rdata_next[1] = dio_pad_attr_28_virtual_od_en_28_qs; + reg_rdata_next[2] = dio_pad_attr_28_pull_en_28_qs; + reg_rdata_next[3] = dio_pad_attr_28_pull_select_28_qs; + reg_rdata_next[4] = dio_pad_attr_28_keeper_en_28_qs; + reg_rdata_next[5] = dio_pad_attr_28_schmitt_en_28_qs; + reg_rdata_next[6] = dio_pad_attr_28_od_en_28_qs; + reg_rdata_next[7] = dio_pad_attr_28_input_disable_28_qs; + reg_rdata_next[17:16] = dio_pad_attr_28_slew_rate_28_qs; + reg_rdata_next[23:20] = dio_pad_attr_28_drive_strength_28_qs; + end + + addr_hit[159]: begin + reg_rdata_next[0] = dio_pad_attr_29_invert_29_qs; + reg_rdata_next[1] = dio_pad_attr_29_virtual_od_en_29_qs; + reg_rdata_next[2] = dio_pad_attr_29_pull_en_29_qs; + reg_rdata_next[3] = dio_pad_attr_29_pull_select_29_qs; + reg_rdata_next[4] = dio_pad_attr_29_keeper_en_29_qs; + reg_rdata_next[5] = dio_pad_attr_29_schmitt_en_29_qs; + reg_rdata_next[6] = dio_pad_attr_29_od_en_29_qs; + reg_rdata_next[7] = dio_pad_attr_29_input_disable_29_qs; + reg_rdata_next[17:16] = dio_pad_attr_29_slew_rate_29_qs; + reg_rdata_next[23:20] = dio_pad_attr_29_drive_strength_29_qs; + end + + addr_hit[160]: begin + reg_rdata_next[0] = dio_pad_attr_30_invert_30_qs; + reg_rdata_next[1] = dio_pad_attr_30_virtual_od_en_30_qs; + reg_rdata_next[2] = dio_pad_attr_30_pull_en_30_qs; + reg_rdata_next[3] = dio_pad_attr_30_pull_select_30_qs; + reg_rdata_next[4] = dio_pad_attr_30_keeper_en_30_qs; + reg_rdata_next[5] = dio_pad_attr_30_schmitt_en_30_qs; + reg_rdata_next[6] = dio_pad_attr_30_od_en_30_qs; + reg_rdata_next[7] = dio_pad_attr_30_input_disable_30_qs; + reg_rdata_next[17:16] = dio_pad_attr_30_slew_rate_30_qs; + reg_rdata_next[23:20] = dio_pad_attr_30_drive_strength_30_qs; + end + + addr_hit[161]: begin + reg_rdata_next[0] = dio_pad_attr_31_invert_31_qs; + reg_rdata_next[1] = dio_pad_attr_31_virtual_od_en_31_qs; + reg_rdata_next[2] = dio_pad_attr_31_pull_en_31_qs; + reg_rdata_next[3] = dio_pad_attr_31_pull_select_31_qs; + reg_rdata_next[4] = dio_pad_attr_31_keeper_en_31_qs; + reg_rdata_next[5] = dio_pad_attr_31_schmitt_en_31_qs; + reg_rdata_next[6] = dio_pad_attr_31_od_en_31_qs; + reg_rdata_next[7] = dio_pad_attr_31_input_disable_31_qs; + reg_rdata_next[17:16] = dio_pad_attr_31_slew_rate_31_qs; + reg_rdata_next[23:20] = dio_pad_attr_31_drive_strength_31_qs; + end + + addr_hit[162]: begin + reg_rdata_next[0] = dio_pad_attr_32_invert_32_qs; + reg_rdata_next[1] = dio_pad_attr_32_virtual_od_en_32_qs; + reg_rdata_next[2] = dio_pad_attr_32_pull_en_32_qs; + reg_rdata_next[3] = dio_pad_attr_32_pull_select_32_qs; + reg_rdata_next[4] = dio_pad_attr_32_keeper_en_32_qs; + reg_rdata_next[5] = dio_pad_attr_32_schmitt_en_32_qs; + reg_rdata_next[6] = dio_pad_attr_32_od_en_32_qs; + reg_rdata_next[7] = dio_pad_attr_32_input_disable_32_qs; + reg_rdata_next[17:16] = dio_pad_attr_32_slew_rate_32_qs; + reg_rdata_next[23:20] = dio_pad_attr_32_drive_strength_32_qs; + end + + addr_hit[163]: begin + reg_rdata_next[0] = dio_pad_attr_33_invert_33_qs; + reg_rdata_next[1] = dio_pad_attr_33_virtual_od_en_33_qs; + reg_rdata_next[2] = dio_pad_attr_33_pull_en_33_qs; + reg_rdata_next[3] = dio_pad_attr_33_pull_select_33_qs; + reg_rdata_next[4] = dio_pad_attr_33_keeper_en_33_qs; + reg_rdata_next[5] = dio_pad_attr_33_schmitt_en_33_qs; + reg_rdata_next[6] = dio_pad_attr_33_od_en_33_qs; + reg_rdata_next[7] = dio_pad_attr_33_input_disable_33_qs; + reg_rdata_next[17:16] = dio_pad_attr_33_slew_rate_33_qs; + reg_rdata_next[23:20] = dio_pad_attr_33_drive_strength_33_qs; + end + + addr_hit[164]: begin + reg_rdata_next[0] = dio_pad_attr_34_invert_34_qs; + reg_rdata_next[1] = dio_pad_attr_34_virtual_od_en_34_qs; + reg_rdata_next[2] = dio_pad_attr_34_pull_en_34_qs; + reg_rdata_next[3] = dio_pad_attr_34_pull_select_34_qs; + reg_rdata_next[4] = dio_pad_attr_34_keeper_en_34_qs; + reg_rdata_next[5] = dio_pad_attr_34_schmitt_en_34_qs; + reg_rdata_next[6] = dio_pad_attr_34_od_en_34_qs; + reg_rdata_next[7] = dio_pad_attr_34_input_disable_34_qs; + reg_rdata_next[17:16] = dio_pad_attr_34_slew_rate_34_qs; + reg_rdata_next[23:20] = dio_pad_attr_34_drive_strength_34_qs; + end + + addr_hit[165]: begin + reg_rdata_next[0] = dio_pad_attr_35_invert_35_qs; + reg_rdata_next[1] = dio_pad_attr_35_virtual_od_en_35_qs; + reg_rdata_next[2] = dio_pad_attr_35_pull_en_35_qs; + reg_rdata_next[3] = dio_pad_attr_35_pull_select_35_qs; + reg_rdata_next[4] = dio_pad_attr_35_keeper_en_35_qs; + reg_rdata_next[5] = dio_pad_attr_35_schmitt_en_35_qs; + reg_rdata_next[6] = dio_pad_attr_35_od_en_35_qs; + reg_rdata_next[7] = dio_pad_attr_35_input_disable_35_qs; + reg_rdata_next[17:16] = dio_pad_attr_35_slew_rate_35_qs; + reg_rdata_next[23:20] = dio_pad_attr_35_drive_strength_35_qs; + end + + addr_hit[166]: begin + reg_rdata_next[0] = dio_pad_attr_36_invert_36_qs; + reg_rdata_next[1] = dio_pad_attr_36_virtual_od_en_36_qs; + reg_rdata_next[2] = dio_pad_attr_36_pull_en_36_qs; + reg_rdata_next[3] = dio_pad_attr_36_pull_select_36_qs; + reg_rdata_next[4] = dio_pad_attr_36_keeper_en_36_qs; + reg_rdata_next[5] = dio_pad_attr_36_schmitt_en_36_qs; + reg_rdata_next[6] = dio_pad_attr_36_od_en_36_qs; + reg_rdata_next[7] = dio_pad_attr_36_input_disable_36_qs; + reg_rdata_next[17:16] = dio_pad_attr_36_slew_rate_36_qs; + reg_rdata_next[23:20] = dio_pad_attr_36_drive_strength_36_qs; + end + + addr_hit[167]: begin + reg_rdata_next[0] = dio_pad_attr_37_invert_37_qs; + reg_rdata_next[1] = dio_pad_attr_37_virtual_od_en_37_qs; + reg_rdata_next[2] = dio_pad_attr_37_pull_en_37_qs; + reg_rdata_next[3] = dio_pad_attr_37_pull_select_37_qs; + reg_rdata_next[4] = dio_pad_attr_37_keeper_en_37_qs; + reg_rdata_next[5] = dio_pad_attr_37_schmitt_en_37_qs; + reg_rdata_next[6] = dio_pad_attr_37_od_en_37_qs; + reg_rdata_next[7] = dio_pad_attr_37_input_disable_37_qs; + reg_rdata_next[17:16] = dio_pad_attr_37_slew_rate_37_qs; + reg_rdata_next[23:20] = dio_pad_attr_37_drive_strength_37_qs; + end + + addr_hit[168]: begin + reg_rdata_next[0] = dio_pad_attr_38_invert_38_qs; + reg_rdata_next[1] = dio_pad_attr_38_virtual_od_en_38_qs; + reg_rdata_next[2] = dio_pad_attr_38_pull_en_38_qs; + reg_rdata_next[3] = dio_pad_attr_38_pull_select_38_qs; + reg_rdata_next[4] = dio_pad_attr_38_keeper_en_38_qs; + reg_rdata_next[5] = dio_pad_attr_38_schmitt_en_38_qs; + reg_rdata_next[6] = dio_pad_attr_38_od_en_38_qs; + reg_rdata_next[7] = dio_pad_attr_38_input_disable_38_qs; + reg_rdata_next[17:16] = dio_pad_attr_38_slew_rate_38_qs; + reg_rdata_next[23:20] = dio_pad_attr_38_drive_strength_38_qs; + end + + addr_hit[169]: begin + reg_rdata_next[0] = dio_pad_attr_39_invert_39_qs; + reg_rdata_next[1] = dio_pad_attr_39_virtual_od_en_39_qs; + reg_rdata_next[2] = dio_pad_attr_39_pull_en_39_qs; + reg_rdata_next[3] = dio_pad_attr_39_pull_select_39_qs; + reg_rdata_next[4] = dio_pad_attr_39_keeper_en_39_qs; + reg_rdata_next[5] = dio_pad_attr_39_schmitt_en_39_qs; + reg_rdata_next[6] = dio_pad_attr_39_od_en_39_qs; + reg_rdata_next[7] = dio_pad_attr_39_input_disable_39_qs; + reg_rdata_next[17:16] = dio_pad_attr_39_slew_rate_39_qs; + reg_rdata_next[23:20] = dio_pad_attr_39_drive_strength_39_qs; + end + + addr_hit[170]: begin + reg_rdata_next[0] = dio_pad_attr_40_invert_40_qs; + reg_rdata_next[1] = dio_pad_attr_40_virtual_od_en_40_qs; + reg_rdata_next[2] = dio_pad_attr_40_pull_en_40_qs; + reg_rdata_next[3] = dio_pad_attr_40_pull_select_40_qs; + reg_rdata_next[4] = dio_pad_attr_40_keeper_en_40_qs; + reg_rdata_next[5] = dio_pad_attr_40_schmitt_en_40_qs; + reg_rdata_next[6] = dio_pad_attr_40_od_en_40_qs; + reg_rdata_next[7] = dio_pad_attr_40_input_disable_40_qs; + reg_rdata_next[17:16] = dio_pad_attr_40_slew_rate_40_qs; + reg_rdata_next[23:20] = dio_pad_attr_40_drive_strength_40_qs; + end + + addr_hit[171]: begin + reg_rdata_next[0] = dio_pad_attr_41_invert_41_qs; + reg_rdata_next[1] = dio_pad_attr_41_virtual_od_en_41_qs; + reg_rdata_next[2] = dio_pad_attr_41_pull_en_41_qs; + reg_rdata_next[3] = dio_pad_attr_41_pull_select_41_qs; + reg_rdata_next[4] = dio_pad_attr_41_keeper_en_41_qs; + reg_rdata_next[5] = dio_pad_attr_41_schmitt_en_41_qs; + reg_rdata_next[6] = dio_pad_attr_41_od_en_41_qs; + reg_rdata_next[7] = dio_pad_attr_41_input_disable_41_qs; + reg_rdata_next[17:16] = dio_pad_attr_41_slew_rate_41_qs; + reg_rdata_next[23:20] = dio_pad_attr_41_drive_strength_41_qs; + end + + addr_hit[172]: begin + reg_rdata_next[0] = dio_pad_attr_42_invert_42_qs; + reg_rdata_next[1] = dio_pad_attr_42_virtual_od_en_42_qs; + reg_rdata_next[2] = dio_pad_attr_42_pull_en_42_qs; + reg_rdata_next[3] = dio_pad_attr_42_pull_select_42_qs; + reg_rdata_next[4] = dio_pad_attr_42_keeper_en_42_qs; + reg_rdata_next[5] = dio_pad_attr_42_schmitt_en_42_qs; + reg_rdata_next[6] = dio_pad_attr_42_od_en_42_qs; + reg_rdata_next[7] = dio_pad_attr_42_input_disable_42_qs; + reg_rdata_next[17:16] = dio_pad_attr_42_slew_rate_42_qs; + reg_rdata_next[23:20] = dio_pad_attr_42_drive_strength_42_qs; + end + + addr_hit[173]: begin + reg_rdata_next[0] = dio_pad_attr_43_invert_43_qs; + reg_rdata_next[1] = dio_pad_attr_43_virtual_od_en_43_qs; + reg_rdata_next[2] = dio_pad_attr_43_pull_en_43_qs; + reg_rdata_next[3] = dio_pad_attr_43_pull_select_43_qs; + reg_rdata_next[4] = dio_pad_attr_43_keeper_en_43_qs; + reg_rdata_next[5] = dio_pad_attr_43_schmitt_en_43_qs; + reg_rdata_next[6] = dio_pad_attr_43_od_en_43_qs; + reg_rdata_next[7] = dio_pad_attr_43_input_disable_43_qs; + reg_rdata_next[17:16] = dio_pad_attr_43_slew_rate_43_qs; + reg_rdata_next[23:20] = dio_pad_attr_43_drive_strength_43_qs; + end + + addr_hit[174]: begin + reg_rdata_next[0] = dio_pad_attr_44_invert_44_qs; + reg_rdata_next[1] = dio_pad_attr_44_virtual_od_en_44_qs; + reg_rdata_next[2] = dio_pad_attr_44_pull_en_44_qs; + reg_rdata_next[3] = dio_pad_attr_44_pull_select_44_qs; + reg_rdata_next[4] = dio_pad_attr_44_keeper_en_44_qs; + reg_rdata_next[5] = dio_pad_attr_44_schmitt_en_44_qs; + reg_rdata_next[6] = dio_pad_attr_44_od_en_44_qs; + reg_rdata_next[7] = dio_pad_attr_44_input_disable_44_qs; + reg_rdata_next[17:16] = dio_pad_attr_44_slew_rate_44_qs; + reg_rdata_next[23:20] = dio_pad_attr_44_drive_strength_44_qs; + end + + addr_hit[175]: begin + reg_rdata_next[0] = dio_pad_attr_45_invert_45_qs; + reg_rdata_next[1] = dio_pad_attr_45_virtual_od_en_45_qs; + reg_rdata_next[2] = dio_pad_attr_45_pull_en_45_qs; + reg_rdata_next[3] = dio_pad_attr_45_pull_select_45_qs; + reg_rdata_next[4] = dio_pad_attr_45_keeper_en_45_qs; + reg_rdata_next[5] = dio_pad_attr_45_schmitt_en_45_qs; + reg_rdata_next[6] = dio_pad_attr_45_od_en_45_qs; + reg_rdata_next[7] = dio_pad_attr_45_input_disable_45_qs; + reg_rdata_next[17:16] = dio_pad_attr_45_slew_rate_45_qs; + reg_rdata_next[23:20] = dio_pad_attr_45_drive_strength_45_qs; + end + + addr_hit[176]: begin + reg_rdata_next[0] = dio_pad_attr_46_invert_46_qs; + reg_rdata_next[1] = dio_pad_attr_46_virtual_od_en_46_qs; + reg_rdata_next[2] = dio_pad_attr_46_pull_en_46_qs; + reg_rdata_next[3] = dio_pad_attr_46_pull_select_46_qs; + reg_rdata_next[4] = dio_pad_attr_46_keeper_en_46_qs; + reg_rdata_next[5] = dio_pad_attr_46_schmitt_en_46_qs; + reg_rdata_next[6] = dio_pad_attr_46_od_en_46_qs; + reg_rdata_next[7] = dio_pad_attr_46_input_disable_46_qs; + reg_rdata_next[17:16] = dio_pad_attr_46_slew_rate_46_qs; + reg_rdata_next[23:20] = dio_pad_attr_46_drive_strength_46_qs; + end + + addr_hit[177]: begin + reg_rdata_next[0] = dio_pad_attr_47_invert_47_qs; + reg_rdata_next[1] = dio_pad_attr_47_virtual_od_en_47_qs; + reg_rdata_next[2] = dio_pad_attr_47_pull_en_47_qs; + reg_rdata_next[3] = dio_pad_attr_47_pull_select_47_qs; + reg_rdata_next[4] = dio_pad_attr_47_keeper_en_47_qs; + reg_rdata_next[5] = dio_pad_attr_47_schmitt_en_47_qs; + reg_rdata_next[6] = dio_pad_attr_47_od_en_47_qs; + reg_rdata_next[7] = dio_pad_attr_47_input_disable_47_qs; + reg_rdata_next[17:16] = dio_pad_attr_47_slew_rate_47_qs; + reg_rdata_next[23:20] = dio_pad_attr_47_drive_strength_47_qs; + end + + addr_hit[178]: begin + reg_rdata_next[0] = dio_pad_attr_48_invert_48_qs; + reg_rdata_next[1] = dio_pad_attr_48_virtual_od_en_48_qs; + reg_rdata_next[2] = dio_pad_attr_48_pull_en_48_qs; + reg_rdata_next[3] = dio_pad_attr_48_pull_select_48_qs; + reg_rdata_next[4] = dio_pad_attr_48_keeper_en_48_qs; + reg_rdata_next[5] = dio_pad_attr_48_schmitt_en_48_qs; + reg_rdata_next[6] = dio_pad_attr_48_od_en_48_qs; + reg_rdata_next[7] = dio_pad_attr_48_input_disable_48_qs; + reg_rdata_next[17:16] = dio_pad_attr_48_slew_rate_48_qs; + reg_rdata_next[23:20] = dio_pad_attr_48_drive_strength_48_qs; + end + + addr_hit[179]: begin + reg_rdata_next[0] = dio_pad_attr_49_invert_49_qs; + reg_rdata_next[1] = dio_pad_attr_49_virtual_od_en_49_qs; + reg_rdata_next[2] = dio_pad_attr_49_pull_en_49_qs; + reg_rdata_next[3] = dio_pad_attr_49_pull_select_49_qs; + reg_rdata_next[4] = dio_pad_attr_49_keeper_en_49_qs; + reg_rdata_next[5] = dio_pad_attr_49_schmitt_en_49_qs; + reg_rdata_next[6] = dio_pad_attr_49_od_en_49_qs; + reg_rdata_next[7] = dio_pad_attr_49_input_disable_49_qs; + reg_rdata_next[17:16] = dio_pad_attr_49_slew_rate_49_qs; + reg_rdata_next[23:20] = dio_pad_attr_49_drive_strength_49_qs; + end + + addr_hit[180]: begin + reg_rdata_next[0] = dio_pad_attr_50_invert_50_qs; + reg_rdata_next[1] = dio_pad_attr_50_virtual_od_en_50_qs; + reg_rdata_next[2] = dio_pad_attr_50_pull_en_50_qs; + reg_rdata_next[3] = dio_pad_attr_50_pull_select_50_qs; + reg_rdata_next[4] = dio_pad_attr_50_keeper_en_50_qs; + reg_rdata_next[5] = dio_pad_attr_50_schmitt_en_50_qs; + reg_rdata_next[6] = dio_pad_attr_50_od_en_50_qs; + reg_rdata_next[7] = dio_pad_attr_50_input_disable_50_qs; + reg_rdata_next[17:16] = dio_pad_attr_50_slew_rate_50_qs; + reg_rdata_next[23:20] = dio_pad_attr_50_drive_strength_50_qs; + end + + addr_hit[181]: begin + reg_rdata_next[0] = dio_pad_attr_51_invert_51_qs; + reg_rdata_next[1] = dio_pad_attr_51_virtual_od_en_51_qs; + reg_rdata_next[2] = dio_pad_attr_51_pull_en_51_qs; + reg_rdata_next[3] = dio_pad_attr_51_pull_select_51_qs; + reg_rdata_next[4] = dio_pad_attr_51_keeper_en_51_qs; + reg_rdata_next[5] = dio_pad_attr_51_schmitt_en_51_qs; + reg_rdata_next[6] = dio_pad_attr_51_od_en_51_qs; + reg_rdata_next[7] = dio_pad_attr_51_input_disable_51_qs; + reg_rdata_next[17:16] = dio_pad_attr_51_slew_rate_51_qs; + reg_rdata_next[23:20] = dio_pad_attr_51_drive_strength_51_qs; + end + + addr_hit[182]: begin + reg_rdata_next[0] = dio_pad_attr_52_invert_52_qs; + reg_rdata_next[1] = dio_pad_attr_52_virtual_od_en_52_qs; + reg_rdata_next[2] = dio_pad_attr_52_pull_en_52_qs; + reg_rdata_next[3] = dio_pad_attr_52_pull_select_52_qs; + reg_rdata_next[4] = dio_pad_attr_52_keeper_en_52_qs; + reg_rdata_next[5] = dio_pad_attr_52_schmitt_en_52_qs; + reg_rdata_next[6] = dio_pad_attr_52_od_en_52_qs; + reg_rdata_next[7] = dio_pad_attr_52_input_disable_52_qs; + reg_rdata_next[17:16] = dio_pad_attr_52_slew_rate_52_qs; + reg_rdata_next[23:20] = dio_pad_attr_52_drive_strength_52_qs; + end + + addr_hit[183]: begin + reg_rdata_next[0] = dio_pad_attr_53_invert_53_qs; + reg_rdata_next[1] = dio_pad_attr_53_virtual_od_en_53_qs; + reg_rdata_next[2] = dio_pad_attr_53_pull_en_53_qs; + reg_rdata_next[3] = dio_pad_attr_53_pull_select_53_qs; + reg_rdata_next[4] = dio_pad_attr_53_keeper_en_53_qs; + reg_rdata_next[5] = dio_pad_attr_53_schmitt_en_53_qs; + reg_rdata_next[6] = dio_pad_attr_53_od_en_53_qs; + reg_rdata_next[7] = dio_pad_attr_53_input_disable_53_qs; + reg_rdata_next[17:16] = dio_pad_attr_53_slew_rate_53_qs; + reg_rdata_next[23:20] = dio_pad_attr_53_drive_strength_53_qs; + end + + addr_hit[184]: begin + reg_rdata_next[0] = dio_pad_attr_54_invert_54_qs; + reg_rdata_next[1] = dio_pad_attr_54_virtual_od_en_54_qs; + reg_rdata_next[2] = dio_pad_attr_54_pull_en_54_qs; + reg_rdata_next[3] = dio_pad_attr_54_pull_select_54_qs; + reg_rdata_next[4] = dio_pad_attr_54_keeper_en_54_qs; + reg_rdata_next[5] = dio_pad_attr_54_schmitt_en_54_qs; + reg_rdata_next[6] = dio_pad_attr_54_od_en_54_qs; + reg_rdata_next[7] = dio_pad_attr_54_input_disable_54_qs; + reg_rdata_next[17:16] = dio_pad_attr_54_slew_rate_54_qs; + reg_rdata_next[23:20] = dio_pad_attr_54_drive_strength_54_qs; + end + + addr_hit[185]: begin + reg_rdata_next[0] = dio_pad_attr_55_invert_55_qs; + reg_rdata_next[1] = dio_pad_attr_55_virtual_od_en_55_qs; + reg_rdata_next[2] = dio_pad_attr_55_pull_en_55_qs; + reg_rdata_next[3] = dio_pad_attr_55_pull_select_55_qs; + reg_rdata_next[4] = dio_pad_attr_55_keeper_en_55_qs; + reg_rdata_next[5] = dio_pad_attr_55_schmitt_en_55_qs; + reg_rdata_next[6] = dio_pad_attr_55_od_en_55_qs; + reg_rdata_next[7] = dio_pad_attr_55_input_disable_55_qs; + reg_rdata_next[17:16] = dio_pad_attr_55_slew_rate_55_qs; + reg_rdata_next[23:20] = dio_pad_attr_55_drive_strength_55_qs; + end + + addr_hit[186]: begin + reg_rdata_next[0] = dio_pad_attr_56_invert_56_qs; + reg_rdata_next[1] = dio_pad_attr_56_virtual_od_en_56_qs; + reg_rdata_next[2] = dio_pad_attr_56_pull_en_56_qs; + reg_rdata_next[3] = dio_pad_attr_56_pull_select_56_qs; + reg_rdata_next[4] = dio_pad_attr_56_keeper_en_56_qs; + reg_rdata_next[5] = dio_pad_attr_56_schmitt_en_56_qs; + reg_rdata_next[6] = dio_pad_attr_56_od_en_56_qs; + reg_rdata_next[7] = dio_pad_attr_56_input_disable_56_qs; + reg_rdata_next[17:16] = dio_pad_attr_56_slew_rate_56_qs; + reg_rdata_next[23:20] = dio_pad_attr_56_drive_strength_56_qs; + end + + addr_hit[187]: begin + reg_rdata_next[0] = dio_pad_attr_57_invert_57_qs; + reg_rdata_next[1] = dio_pad_attr_57_virtual_od_en_57_qs; + reg_rdata_next[2] = dio_pad_attr_57_pull_en_57_qs; + reg_rdata_next[3] = dio_pad_attr_57_pull_select_57_qs; + reg_rdata_next[4] = dio_pad_attr_57_keeper_en_57_qs; + reg_rdata_next[5] = dio_pad_attr_57_schmitt_en_57_qs; + reg_rdata_next[6] = dio_pad_attr_57_od_en_57_qs; + reg_rdata_next[7] = dio_pad_attr_57_input_disable_57_qs; + reg_rdata_next[17:16] = dio_pad_attr_57_slew_rate_57_qs; + reg_rdata_next[23:20] = dio_pad_attr_57_drive_strength_57_qs; + end + + addr_hit[188]: begin + reg_rdata_next[0] = dio_pad_attr_58_invert_58_qs; + reg_rdata_next[1] = dio_pad_attr_58_virtual_od_en_58_qs; + reg_rdata_next[2] = dio_pad_attr_58_pull_en_58_qs; + reg_rdata_next[3] = dio_pad_attr_58_pull_select_58_qs; + reg_rdata_next[4] = dio_pad_attr_58_keeper_en_58_qs; + reg_rdata_next[5] = dio_pad_attr_58_schmitt_en_58_qs; + reg_rdata_next[6] = dio_pad_attr_58_od_en_58_qs; + reg_rdata_next[7] = dio_pad_attr_58_input_disable_58_qs; + reg_rdata_next[17:16] = dio_pad_attr_58_slew_rate_58_qs; + reg_rdata_next[23:20] = dio_pad_attr_58_drive_strength_58_qs; + end + + addr_hit[189]: begin + reg_rdata_next[0] = dio_pad_attr_59_invert_59_qs; + reg_rdata_next[1] = dio_pad_attr_59_virtual_od_en_59_qs; + reg_rdata_next[2] = dio_pad_attr_59_pull_en_59_qs; + reg_rdata_next[3] = dio_pad_attr_59_pull_select_59_qs; + reg_rdata_next[4] = dio_pad_attr_59_keeper_en_59_qs; + reg_rdata_next[5] = dio_pad_attr_59_schmitt_en_59_qs; + reg_rdata_next[6] = dio_pad_attr_59_od_en_59_qs; + reg_rdata_next[7] = dio_pad_attr_59_input_disable_59_qs; + reg_rdata_next[17:16] = dio_pad_attr_59_slew_rate_59_qs; + reg_rdata_next[23:20] = dio_pad_attr_59_drive_strength_59_qs; + end + + addr_hit[190]: begin + reg_rdata_next[0] = dio_pad_attr_60_invert_60_qs; + reg_rdata_next[1] = dio_pad_attr_60_virtual_od_en_60_qs; + reg_rdata_next[2] = dio_pad_attr_60_pull_en_60_qs; + reg_rdata_next[3] = dio_pad_attr_60_pull_select_60_qs; + reg_rdata_next[4] = dio_pad_attr_60_keeper_en_60_qs; + reg_rdata_next[5] = dio_pad_attr_60_schmitt_en_60_qs; + reg_rdata_next[6] = dio_pad_attr_60_od_en_60_qs; + reg_rdata_next[7] = dio_pad_attr_60_input_disable_60_qs; + reg_rdata_next[17:16] = dio_pad_attr_60_slew_rate_60_qs; + reg_rdata_next[23:20] = dio_pad_attr_60_drive_strength_60_qs; + end + + addr_hit[191]: begin + reg_rdata_next[0] = dio_pad_attr_61_invert_61_qs; + reg_rdata_next[1] = dio_pad_attr_61_virtual_od_en_61_qs; + reg_rdata_next[2] = dio_pad_attr_61_pull_en_61_qs; + reg_rdata_next[3] = dio_pad_attr_61_pull_select_61_qs; + reg_rdata_next[4] = dio_pad_attr_61_keeper_en_61_qs; + reg_rdata_next[5] = dio_pad_attr_61_schmitt_en_61_qs; + reg_rdata_next[6] = dio_pad_attr_61_od_en_61_qs; + reg_rdata_next[7] = dio_pad_attr_61_input_disable_61_qs; + reg_rdata_next[17:16] = dio_pad_attr_61_slew_rate_61_qs; + reg_rdata_next[23:20] = dio_pad_attr_61_drive_strength_61_qs; + end + + addr_hit[192]: begin + reg_rdata_next[0] = dio_pad_attr_62_invert_62_qs; + reg_rdata_next[1] = dio_pad_attr_62_virtual_od_en_62_qs; + reg_rdata_next[2] = dio_pad_attr_62_pull_en_62_qs; + reg_rdata_next[3] = dio_pad_attr_62_pull_select_62_qs; + reg_rdata_next[4] = dio_pad_attr_62_keeper_en_62_qs; + reg_rdata_next[5] = dio_pad_attr_62_schmitt_en_62_qs; + reg_rdata_next[6] = dio_pad_attr_62_od_en_62_qs; + reg_rdata_next[7] = dio_pad_attr_62_input_disable_62_qs; + reg_rdata_next[17:16] = dio_pad_attr_62_slew_rate_62_qs; + reg_rdata_next[23:20] = dio_pad_attr_62_drive_strength_62_qs; + end + + addr_hit[193]: begin + reg_rdata_next[0] = dio_pad_attr_63_invert_63_qs; + reg_rdata_next[1] = dio_pad_attr_63_virtual_od_en_63_qs; + reg_rdata_next[2] = dio_pad_attr_63_pull_en_63_qs; + reg_rdata_next[3] = dio_pad_attr_63_pull_select_63_qs; + reg_rdata_next[4] = dio_pad_attr_63_keeper_en_63_qs; + reg_rdata_next[5] = dio_pad_attr_63_schmitt_en_63_qs; + reg_rdata_next[6] = dio_pad_attr_63_od_en_63_qs; + reg_rdata_next[7] = dio_pad_attr_63_input_disable_63_qs; + reg_rdata_next[17:16] = dio_pad_attr_63_slew_rate_63_qs; + reg_rdata_next[23:20] = dio_pad_attr_63_drive_strength_63_qs; + end + + addr_hit[194]: begin + reg_rdata_next[0] = dio_pad_attr_64_invert_64_qs; + reg_rdata_next[1] = dio_pad_attr_64_virtual_od_en_64_qs; + reg_rdata_next[2] = dio_pad_attr_64_pull_en_64_qs; + reg_rdata_next[3] = dio_pad_attr_64_pull_select_64_qs; + reg_rdata_next[4] = dio_pad_attr_64_keeper_en_64_qs; + reg_rdata_next[5] = dio_pad_attr_64_schmitt_en_64_qs; + reg_rdata_next[6] = dio_pad_attr_64_od_en_64_qs; + reg_rdata_next[7] = dio_pad_attr_64_input_disable_64_qs; + reg_rdata_next[17:16] = dio_pad_attr_64_slew_rate_64_qs; + reg_rdata_next[23:20] = dio_pad_attr_64_drive_strength_64_qs; + end + + addr_hit[195]: begin + reg_rdata_next[0] = dio_pad_attr_65_invert_65_qs; + reg_rdata_next[1] = dio_pad_attr_65_virtual_od_en_65_qs; + reg_rdata_next[2] = dio_pad_attr_65_pull_en_65_qs; + reg_rdata_next[3] = dio_pad_attr_65_pull_select_65_qs; + reg_rdata_next[4] = dio_pad_attr_65_keeper_en_65_qs; + reg_rdata_next[5] = dio_pad_attr_65_schmitt_en_65_qs; + reg_rdata_next[6] = dio_pad_attr_65_od_en_65_qs; + reg_rdata_next[7] = dio_pad_attr_65_input_disable_65_qs; + reg_rdata_next[17:16] = dio_pad_attr_65_slew_rate_65_qs; + reg_rdata_next[23:20] = dio_pad_attr_65_drive_strength_65_qs; + end + + addr_hit[196]: begin + reg_rdata_next[0] = dio_pad_attr_66_invert_66_qs; + reg_rdata_next[1] = dio_pad_attr_66_virtual_od_en_66_qs; + reg_rdata_next[2] = dio_pad_attr_66_pull_en_66_qs; + reg_rdata_next[3] = dio_pad_attr_66_pull_select_66_qs; + reg_rdata_next[4] = dio_pad_attr_66_keeper_en_66_qs; + reg_rdata_next[5] = dio_pad_attr_66_schmitt_en_66_qs; + reg_rdata_next[6] = dio_pad_attr_66_od_en_66_qs; + reg_rdata_next[7] = dio_pad_attr_66_input_disable_66_qs; + reg_rdata_next[17:16] = dio_pad_attr_66_slew_rate_66_qs; + reg_rdata_next[23:20] = dio_pad_attr_66_drive_strength_66_qs; + end + + addr_hit[197]: begin + reg_rdata_next[0] = dio_pad_attr_67_invert_67_qs; + reg_rdata_next[1] = dio_pad_attr_67_virtual_od_en_67_qs; + reg_rdata_next[2] = dio_pad_attr_67_pull_en_67_qs; + reg_rdata_next[3] = dio_pad_attr_67_pull_select_67_qs; + reg_rdata_next[4] = dio_pad_attr_67_keeper_en_67_qs; + reg_rdata_next[5] = dio_pad_attr_67_schmitt_en_67_qs; + reg_rdata_next[6] = dio_pad_attr_67_od_en_67_qs; + reg_rdata_next[7] = dio_pad_attr_67_input_disable_67_qs; + reg_rdata_next[17:16] = dio_pad_attr_67_slew_rate_67_qs; + reg_rdata_next[23:20] = dio_pad_attr_67_drive_strength_67_qs; + end + + addr_hit[198]: begin + reg_rdata_next[0] = dio_pad_attr_68_invert_68_qs; + reg_rdata_next[1] = dio_pad_attr_68_virtual_od_en_68_qs; + reg_rdata_next[2] = dio_pad_attr_68_pull_en_68_qs; + reg_rdata_next[3] = dio_pad_attr_68_pull_select_68_qs; + reg_rdata_next[4] = dio_pad_attr_68_keeper_en_68_qs; + reg_rdata_next[5] = dio_pad_attr_68_schmitt_en_68_qs; + reg_rdata_next[6] = dio_pad_attr_68_od_en_68_qs; + reg_rdata_next[7] = dio_pad_attr_68_input_disable_68_qs; + reg_rdata_next[17:16] = dio_pad_attr_68_slew_rate_68_qs; + reg_rdata_next[23:20] = dio_pad_attr_68_drive_strength_68_qs; + end + + addr_hit[199]: begin + reg_rdata_next[0] = dio_pad_attr_69_invert_69_qs; + reg_rdata_next[1] = dio_pad_attr_69_virtual_od_en_69_qs; + reg_rdata_next[2] = dio_pad_attr_69_pull_en_69_qs; + reg_rdata_next[3] = dio_pad_attr_69_pull_select_69_qs; + reg_rdata_next[4] = dio_pad_attr_69_keeper_en_69_qs; + reg_rdata_next[5] = dio_pad_attr_69_schmitt_en_69_qs; + reg_rdata_next[6] = dio_pad_attr_69_od_en_69_qs; + reg_rdata_next[7] = dio_pad_attr_69_input_disable_69_qs; + reg_rdata_next[17:16] = dio_pad_attr_69_slew_rate_69_qs; + reg_rdata_next[23:20] = dio_pad_attr_69_drive_strength_69_qs; + end + + addr_hit[200]: begin + reg_rdata_next[0] = dio_pad_attr_70_invert_70_qs; + reg_rdata_next[1] = dio_pad_attr_70_virtual_od_en_70_qs; + reg_rdata_next[2] = dio_pad_attr_70_pull_en_70_qs; + reg_rdata_next[3] = dio_pad_attr_70_pull_select_70_qs; + reg_rdata_next[4] = dio_pad_attr_70_keeper_en_70_qs; + reg_rdata_next[5] = dio_pad_attr_70_schmitt_en_70_qs; + reg_rdata_next[6] = dio_pad_attr_70_od_en_70_qs; + reg_rdata_next[7] = dio_pad_attr_70_input_disable_70_qs; + reg_rdata_next[17:16] = dio_pad_attr_70_slew_rate_70_qs; + reg_rdata_next[23:20] = dio_pad_attr_70_drive_strength_70_qs; + end + + addr_hit[201]: begin + reg_rdata_next[0] = dio_pad_attr_71_invert_71_qs; + reg_rdata_next[1] = dio_pad_attr_71_virtual_od_en_71_qs; + reg_rdata_next[2] = dio_pad_attr_71_pull_en_71_qs; + reg_rdata_next[3] = dio_pad_attr_71_pull_select_71_qs; + reg_rdata_next[4] = dio_pad_attr_71_keeper_en_71_qs; + reg_rdata_next[5] = dio_pad_attr_71_schmitt_en_71_qs; + reg_rdata_next[6] = dio_pad_attr_71_od_en_71_qs; + reg_rdata_next[7] = dio_pad_attr_71_input_disable_71_qs; + reg_rdata_next[17:16] = dio_pad_attr_71_slew_rate_71_qs; + reg_rdata_next[23:20] = dio_pad_attr_71_drive_strength_71_qs; + end + + addr_hit[202]: begin + reg_rdata_next[0] = dio_pad_attr_72_invert_72_qs; + reg_rdata_next[1] = dio_pad_attr_72_virtual_od_en_72_qs; + reg_rdata_next[2] = dio_pad_attr_72_pull_en_72_qs; + reg_rdata_next[3] = dio_pad_attr_72_pull_select_72_qs; + reg_rdata_next[4] = dio_pad_attr_72_keeper_en_72_qs; + reg_rdata_next[5] = dio_pad_attr_72_schmitt_en_72_qs; + reg_rdata_next[6] = dio_pad_attr_72_od_en_72_qs; + reg_rdata_next[7] = dio_pad_attr_72_input_disable_72_qs; + reg_rdata_next[17:16] = dio_pad_attr_72_slew_rate_72_qs; + reg_rdata_next[23:20] = dio_pad_attr_72_drive_strength_72_qs; + end + + addr_hit[203]: begin + reg_rdata_next[0] = mio_pad_sleep_status_en_0_qs; + reg_rdata_next[1] = mio_pad_sleep_status_en_1_qs; + reg_rdata_next[2] = mio_pad_sleep_status_en_2_qs; + reg_rdata_next[3] = mio_pad_sleep_status_en_3_qs; + reg_rdata_next[4] = mio_pad_sleep_status_en_4_qs; + reg_rdata_next[5] = mio_pad_sleep_status_en_5_qs; + reg_rdata_next[6] = mio_pad_sleep_status_en_6_qs; + reg_rdata_next[7] = mio_pad_sleep_status_en_7_qs; + reg_rdata_next[8] = mio_pad_sleep_status_en_8_qs; + reg_rdata_next[9] = mio_pad_sleep_status_en_9_qs; + reg_rdata_next[10] = mio_pad_sleep_status_en_10_qs; + reg_rdata_next[11] = mio_pad_sleep_status_en_11_qs; + end + + addr_hit[204]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs; + end + + addr_hit[205]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs; + end + + addr_hit[206]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs; + end + + addr_hit[207]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs; + end + + addr_hit[208]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs; + end + + addr_hit[209]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs; + end + + addr_hit[210]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs; + end + + addr_hit[211]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs; + end + + addr_hit[212]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs; + end + + addr_hit[213]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs; + end + + addr_hit[214]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs; + end + + addr_hit[215]: begin + reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs; + end + + addr_hit[216]: begin + reg_rdata_next[0] = mio_pad_sleep_en_0_qs; + end + + addr_hit[217]: begin + reg_rdata_next[0] = mio_pad_sleep_en_1_qs; + end + + addr_hit[218]: begin + reg_rdata_next[0] = mio_pad_sleep_en_2_qs; + end + + addr_hit[219]: begin + reg_rdata_next[0] = mio_pad_sleep_en_3_qs; + end + + addr_hit[220]: begin + reg_rdata_next[0] = mio_pad_sleep_en_4_qs; + end + + addr_hit[221]: begin + reg_rdata_next[0] = mio_pad_sleep_en_5_qs; + end + + addr_hit[222]: begin + reg_rdata_next[0] = mio_pad_sleep_en_6_qs; + end + + addr_hit[223]: begin + reg_rdata_next[0] = mio_pad_sleep_en_7_qs; + end + + addr_hit[224]: begin + reg_rdata_next[0] = mio_pad_sleep_en_8_qs; + end + + addr_hit[225]: begin + reg_rdata_next[0] = mio_pad_sleep_en_9_qs; + end + + addr_hit[226]: begin + reg_rdata_next[0] = mio_pad_sleep_en_10_qs; + end + + addr_hit[227]: begin + reg_rdata_next[0] = mio_pad_sleep_en_11_qs; + end + + addr_hit[228]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs; + end + + addr_hit[229]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs; + end + + addr_hit[230]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs; + end + + addr_hit[231]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs; + end + + addr_hit[232]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs; + end + + addr_hit[233]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs; + end + + addr_hit[234]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs; + end + + addr_hit[235]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs; + end + + addr_hit[236]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs; + end + + addr_hit[237]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs; + end + + addr_hit[238]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs; + end + + addr_hit[239]: begin + reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs; + end + + addr_hit[240]: begin + reg_rdata_next[0] = dio_pad_sleep_status_0_en_0_qs; + reg_rdata_next[1] = dio_pad_sleep_status_0_en_1_qs; + reg_rdata_next[2] = dio_pad_sleep_status_0_en_2_qs; + reg_rdata_next[3] = dio_pad_sleep_status_0_en_3_qs; + reg_rdata_next[4] = dio_pad_sleep_status_0_en_4_qs; + reg_rdata_next[5] = dio_pad_sleep_status_0_en_5_qs; + reg_rdata_next[6] = dio_pad_sleep_status_0_en_6_qs; + reg_rdata_next[7] = dio_pad_sleep_status_0_en_7_qs; + reg_rdata_next[8] = dio_pad_sleep_status_0_en_8_qs; + reg_rdata_next[9] = dio_pad_sleep_status_0_en_9_qs; + reg_rdata_next[10] = dio_pad_sleep_status_0_en_10_qs; + reg_rdata_next[11] = dio_pad_sleep_status_0_en_11_qs; + reg_rdata_next[12] = dio_pad_sleep_status_0_en_12_qs; + reg_rdata_next[13] = dio_pad_sleep_status_0_en_13_qs; + reg_rdata_next[14] = dio_pad_sleep_status_0_en_14_qs; + reg_rdata_next[15] = dio_pad_sleep_status_0_en_15_qs; + reg_rdata_next[16] = dio_pad_sleep_status_0_en_16_qs; + reg_rdata_next[17] = dio_pad_sleep_status_0_en_17_qs; + reg_rdata_next[18] = dio_pad_sleep_status_0_en_18_qs; + reg_rdata_next[19] = dio_pad_sleep_status_0_en_19_qs; + reg_rdata_next[20] = dio_pad_sleep_status_0_en_20_qs; + reg_rdata_next[21] = dio_pad_sleep_status_0_en_21_qs; + reg_rdata_next[22] = dio_pad_sleep_status_0_en_22_qs; + reg_rdata_next[23] = dio_pad_sleep_status_0_en_23_qs; + reg_rdata_next[24] = dio_pad_sleep_status_0_en_24_qs; + reg_rdata_next[25] = dio_pad_sleep_status_0_en_25_qs; + reg_rdata_next[26] = dio_pad_sleep_status_0_en_26_qs; + reg_rdata_next[27] = dio_pad_sleep_status_0_en_27_qs; + reg_rdata_next[28] = dio_pad_sleep_status_0_en_28_qs; + reg_rdata_next[29] = dio_pad_sleep_status_0_en_29_qs; + reg_rdata_next[30] = dio_pad_sleep_status_0_en_30_qs; + reg_rdata_next[31] = dio_pad_sleep_status_0_en_31_qs; + end + + addr_hit[241]: begin + reg_rdata_next[0] = dio_pad_sleep_status_1_en_32_qs; + reg_rdata_next[1] = dio_pad_sleep_status_1_en_33_qs; + reg_rdata_next[2] = dio_pad_sleep_status_1_en_34_qs; + reg_rdata_next[3] = dio_pad_sleep_status_1_en_35_qs; + reg_rdata_next[4] = dio_pad_sleep_status_1_en_36_qs; + reg_rdata_next[5] = dio_pad_sleep_status_1_en_37_qs; + reg_rdata_next[6] = dio_pad_sleep_status_1_en_38_qs; + reg_rdata_next[7] = dio_pad_sleep_status_1_en_39_qs; + reg_rdata_next[8] = dio_pad_sleep_status_1_en_40_qs; + reg_rdata_next[9] = dio_pad_sleep_status_1_en_41_qs; + reg_rdata_next[10] = dio_pad_sleep_status_1_en_42_qs; + reg_rdata_next[11] = dio_pad_sleep_status_1_en_43_qs; + reg_rdata_next[12] = dio_pad_sleep_status_1_en_44_qs; + reg_rdata_next[13] = dio_pad_sleep_status_1_en_45_qs; + reg_rdata_next[14] = dio_pad_sleep_status_1_en_46_qs; + reg_rdata_next[15] = dio_pad_sleep_status_1_en_47_qs; + reg_rdata_next[16] = dio_pad_sleep_status_1_en_48_qs; + reg_rdata_next[17] = dio_pad_sleep_status_1_en_49_qs; + reg_rdata_next[18] = dio_pad_sleep_status_1_en_50_qs; + reg_rdata_next[19] = dio_pad_sleep_status_1_en_51_qs; + reg_rdata_next[20] = dio_pad_sleep_status_1_en_52_qs; + reg_rdata_next[21] = dio_pad_sleep_status_1_en_53_qs; + reg_rdata_next[22] = dio_pad_sleep_status_1_en_54_qs; + reg_rdata_next[23] = dio_pad_sleep_status_1_en_55_qs; + reg_rdata_next[24] = dio_pad_sleep_status_1_en_56_qs; + reg_rdata_next[25] = dio_pad_sleep_status_1_en_57_qs; + reg_rdata_next[26] = dio_pad_sleep_status_1_en_58_qs; + reg_rdata_next[27] = dio_pad_sleep_status_1_en_59_qs; + reg_rdata_next[28] = dio_pad_sleep_status_1_en_60_qs; + reg_rdata_next[29] = dio_pad_sleep_status_1_en_61_qs; + reg_rdata_next[30] = dio_pad_sleep_status_1_en_62_qs; + reg_rdata_next[31] = dio_pad_sleep_status_1_en_63_qs; + end + + addr_hit[242]: begin + reg_rdata_next[0] = dio_pad_sleep_status_2_en_64_qs; + reg_rdata_next[1] = dio_pad_sleep_status_2_en_65_qs; + reg_rdata_next[2] = dio_pad_sleep_status_2_en_66_qs; + reg_rdata_next[3] = dio_pad_sleep_status_2_en_67_qs; + reg_rdata_next[4] = dio_pad_sleep_status_2_en_68_qs; + reg_rdata_next[5] = dio_pad_sleep_status_2_en_69_qs; + reg_rdata_next[6] = dio_pad_sleep_status_2_en_70_qs; + reg_rdata_next[7] = dio_pad_sleep_status_2_en_71_qs; + reg_rdata_next[8] = dio_pad_sleep_status_2_en_72_qs; + end + + addr_hit[243]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs; + end + + addr_hit[244]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs; + end + + addr_hit[245]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs; + end + + addr_hit[246]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs; + end + + addr_hit[247]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs; + end + + addr_hit[248]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs; + end + + addr_hit[249]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs; + end + + addr_hit[250]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs; + end + + addr_hit[251]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs; + end + + addr_hit[252]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs; + end + + addr_hit[253]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs; + end + + addr_hit[254]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs; + end + + addr_hit[255]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs; + end + + addr_hit[256]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs; + end + + addr_hit[257]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs; + end + + addr_hit[258]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs; + end + + addr_hit[259]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_16_qs; + end + + addr_hit[260]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_17_qs; + end + + addr_hit[261]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_18_qs; + end + + addr_hit[262]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_19_qs; + end + + addr_hit[263]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_20_qs; + end + + addr_hit[264]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_21_qs; + end + + addr_hit[265]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_22_qs; + end + + addr_hit[266]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_23_qs; + end + + addr_hit[267]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_24_qs; + end + + addr_hit[268]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_25_qs; + end + + addr_hit[269]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_26_qs; + end + + addr_hit[270]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_27_qs; + end + + addr_hit[271]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_28_qs; + end + + addr_hit[272]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_29_qs; + end + + addr_hit[273]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_30_qs; + end + + addr_hit[274]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_31_qs; + end + + addr_hit[275]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_32_qs; + end + + addr_hit[276]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_33_qs; + end + + addr_hit[277]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_34_qs; + end + + addr_hit[278]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_35_qs; + end + + addr_hit[279]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_36_qs; + end + + addr_hit[280]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_37_qs; + end + + addr_hit[281]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_38_qs; + end + + addr_hit[282]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_39_qs; + end + + addr_hit[283]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_40_qs; + end + + addr_hit[284]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_41_qs; + end + + addr_hit[285]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_42_qs; + end + + addr_hit[286]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_43_qs; + end + + addr_hit[287]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_44_qs; + end + + addr_hit[288]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_45_qs; + end + + addr_hit[289]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_46_qs; + end + + addr_hit[290]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_47_qs; + end + + addr_hit[291]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_48_qs; + end + + addr_hit[292]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_49_qs; + end + + addr_hit[293]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_50_qs; + end + + addr_hit[294]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_51_qs; + end + + addr_hit[295]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_52_qs; + end + + addr_hit[296]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_53_qs; + end + + addr_hit[297]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_54_qs; + end + + addr_hit[298]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_55_qs; + end + + addr_hit[299]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_56_qs; + end + + addr_hit[300]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_57_qs; + end + + addr_hit[301]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_58_qs; + end + + addr_hit[302]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_59_qs; + end + + addr_hit[303]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_60_qs; + end + + addr_hit[304]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_61_qs; + end + + addr_hit[305]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_62_qs; + end + + addr_hit[306]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_63_qs; + end + + addr_hit[307]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_64_qs; + end + + addr_hit[308]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_65_qs; + end + + addr_hit[309]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_66_qs; + end + + addr_hit[310]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_67_qs; + end + + addr_hit[311]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_68_qs; + end + + addr_hit[312]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_69_qs; + end + + addr_hit[313]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_70_qs; + end + + addr_hit[314]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_71_qs; + end + + addr_hit[315]: begin + reg_rdata_next[0] = dio_pad_sleep_regwen_72_qs; + end + + addr_hit[316]: begin + reg_rdata_next[0] = dio_pad_sleep_en_0_qs; + end + + addr_hit[317]: begin + reg_rdata_next[0] = dio_pad_sleep_en_1_qs; + end + + addr_hit[318]: begin + reg_rdata_next[0] = dio_pad_sleep_en_2_qs; + end + + addr_hit[319]: begin + reg_rdata_next[0] = dio_pad_sleep_en_3_qs; + end + + addr_hit[320]: begin + reg_rdata_next[0] = dio_pad_sleep_en_4_qs; + end + + addr_hit[321]: begin + reg_rdata_next[0] = dio_pad_sleep_en_5_qs; + end + + addr_hit[322]: begin + reg_rdata_next[0] = dio_pad_sleep_en_6_qs; + end + + addr_hit[323]: begin + reg_rdata_next[0] = dio_pad_sleep_en_7_qs; + end + + addr_hit[324]: begin + reg_rdata_next[0] = dio_pad_sleep_en_8_qs; + end + + addr_hit[325]: begin + reg_rdata_next[0] = dio_pad_sleep_en_9_qs; + end + + addr_hit[326]: begin + reg_rdata_next[0] = dio_pad_sleep_en_10_qs; + end + + addr_hit[327]: begin + reg_rdata_next[0] = dio_pad_sleep_en_11_qs; + end + + addr_hit[328]: begin + reg_rdata_next[0] = dio_pad_sleep_en_12_qs; + end + + addr_hit[329]: begin + reg_rdata_next[0] = dio_pad_sleep_en_13_qs; + end + + addr_hit[330]: begin + reg_rdata_next[0] = dio_pad_sleep_en_14_qs; + end + + addr_hit[331]: begin + reg_rdata_next[0] = dio_pad_sleep_en_15_qs; + end + + addr_hit[332]: begin + reg_rdata_next[0] = dio_pad_sleep_en_16_qs; + end + + addr_hit[333]: begin + reg_rdata_next[0] = dio_pad_sleep_en_17_qs; + end + + addr_hit[334]: begin + reg_rdata_next[0] = dio_pad_sleep_en_18_qs; + end + + addr_hit[335]: begin + reg_rdata_next[0] = dio_pad_sleep_en_19_qs; + end + + addr_hit[336]: begin + reg_rdata_next[0] = dio_pad_sleep_en_20_qs; + end + + addr_hit[337]: begin + reg_rdata_next[0] = dio_pad_sleep_en_21_qs; + end + + addr_hit[338]: begin + reg_rdata_next[0] = dio_pad_sleep_en_22_qs; + end + + addr_hit[339]: begin + reg_rdata_next[0] = dio_pad_sleep_en_23_qs; + end + + addr_hit[340]: begin + reg_rdata_next[0] = dio_pad_sleep_en_24_qs; + end + + addr_hit[341]: begin + reg_rdata_next[0] = dio_pad_sleep_en_25_qs; + end + + addr_hit[342]: begin + reg_rdata_next[0] = dio_pad_sleep_en_26_qs; + end + + addr_hit[343]: begin + reg_rdata_next[0] = dio_pad_sleep_en_27_qs; + end + + addr_hit[344]: begin + reg_rdata_next[0] = dio_pad_sleep_en_28_qs; + end + + addr_hit[345]: begin + reg_rdata_next[0] = dio_pad_sleep_en_29_qs; + end + + addr_hit[346]: begin + reg_rdata_next[0] = dio_pad_sleep_en_30_qs; + end + + addr_hit[347]: begin + reg_rdata_next[0] = dio_pad_sleep_en_31_qs; + end + + addr_hit[348]: begin + reg_rdata_next[0] = dio_pad_sleep_en_32_qs; + end + + addr_hit[349]: begin + reg_rdata_next[0] = dio_pad_sleep_en_33_qs; + end + + addr_hit[350]: begin + reg_rdata_next[0] = dio_pad_sleep_en_34_qs; + end + + addr_hit[351]: begin + reg_rdata_next[0] = dio_pad_sleep_en_35_qs; + end + + addr_hit[352]: begin + reg_rdata_next[0] = dio_pad_sleep_en_36_qs; + end + + addr_hit[353]: begin + reg_rdata_next[0] = dio_pad_sleep_en_37_qs; + end + + addr_hit[354]: begin + reg_rdata_next[0] = dio_pad_sleep_en_38_qs; + end + + addr_hit[355]: begin + reg_rdata_next[0] = dio_pad_sleep_en_39_qs; + end + + addr_hit[356]: begin + reg_rdata_next[0] = dio_pad_sleep_en_40_qs; + end + + addr_hit[357]: begin + reg_rdata_next[0] = dio_pad_sleep_en_41_qs; + end + + addr_hit[358]: begin + reg_rdata_next[0] = dio_pad_sleep_en_42_qs; + end + + addr_hit[359]: begin + reg_rdata_next[0] = dio_pad_sleep_en_43_qs; + end + + addr_hit[360]: begin + reg_rdata_next[0] = dio_pad_sleep_en_44_qs; + end + + addr_hit[361]: begin + reg_rdata_next[0] = dio_pad_sleep_en_45_qs; + end + + addr_hit[362]: begin + reg_rdata_next[0] = dio_pad_sleep_en_46_qs; + end + + addr_hit[363]: begin + reg_rdata_next[0] = dio_pad_sleep_en_47_qs; + end + + addr_hit[364]: begin + reg_rdata_next[0] = dio_pad_sleep_en_48_qs; + end + + addr_hit[365]: begin + reg_rdata_next[0] = dio_pad_sleep_en_49_qs; + end + + addr_hit[366]: begin + reg_rdata_next[0] = dio_pad_sleep_en_50_qs; + end + + addr_hit[367]: begin + reg_rdata_next[0] = dio_pad_sleep_en_51_qs; + end + + addr_hit[368]: begin + reg_rdata_next[0] = dio_pad_sleep_en_52_qs; + end + + addr_hit[369]: begin + reg_rdata_next[0] = dio_pad_sleep_en_53_qs; + end + + addr_hit[370]: begin + reg_rdata_next[0] = dio_pad_sleep_en_54_qs; + end + + addr_hit[371]: begin + reg_rdata_next[0] = dio_pad_sleep_en_55_qs; + end + + addr_hit[372]: begin + reg_rdata_next[0] = dio_pad_sleep_en_56_qs; + end + + addr_hit[373]: begin + reg_rdata_next[0] = dio_pad_sleep_en_57_qs; + end + + addr_hit[374]: begin + reg_rdata_next[0] = dio_pad_sleep_en_58_qs; + end + + addr_hit[375]: begin + reg_rdata_next[0] = dio_pad_sleep_en_59_qs; + end + + addr_hit[376]: begin + reg_rdata_next[0] = dio_pad_sleep_en_60_qs; + end + + addr_hit[377]: begin + reg_rdata_next[0] = dio_pad_sleep_en_61_qs; + end + + addr_hit[378]: begin + reg_rdata_next[0] = dio_pad_sleep_en_62_qs; + end + + addr_hit[379]: begin + reg_rdata_next[0] = dio_pad_sleep_en_63_qs; + end + + addr_hit[380]: begin + reg_rdata_next[0] = dio_pad_sleep_en_64_qs; + end + + addr_hit[381]: begin + reg_rdata_next[0] = dio_pad_sleep_en_65_qs; + end + + addr_hit[382]: begin + reg_rdata_next[0] = dio_pad_sleep_en_66_qs; + end + + addr_hit[383]: begin + reg_rdata_next[0] = dio_pad_sleep_en_67_qs; + end + + addr_hit[384]: begin + reg_rdata_next[0] = dio_pad_sleep_en_68_qs; + end + + addr_hit[385]: begin + reg_rdata_next[0] = dio_pad_sleep_en_69_qs; + end + + addr_hit[386]: begin + reg_rdata_next[0] = dio_pad_sleep_en_70_qs; + end + + addr_hit[387]: begin + reg_rdata_next[0] = dio_pad_sleep_en_71_qs; + end + + addr_hit[388]: begin + reg_rdata_next[0] = dio_pad_sleep_en_72_qs; + end + + addr_hit[389]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs; + end + + addr_hit[390]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs; + end + + addr_hit[391]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs; + end + + addr_hit[392]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs; + end + + addr_hit[393]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs; + end + + addr_hit[394]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs; + end + + addr_hit[395]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs; + end + + addr_hit[396]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs; + end + + addr_hit[397]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs; + end + + addr_hit[398]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs; + end + + addr_hit[399]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs; + end + + addr_hit[400]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs; + end + + addr_hit[401]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs; + end + + addr_hit[402]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs; + end + + addr_hit[403]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs; + end + + addr_hit[404]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs; + end + + addr_hit[405]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_16_qs; + end + + addr_hit[406]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_17_qs; + end + + addr_hit[407]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_18_qs; + end + + addr_hit[408]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_19_qs; + end + + addr_hit[409]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_20_qs; + end + + addr_hit[410]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_21_qs; + end + + addr_hit[411]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_22_qs; + end + + addr_hit[412]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_23_qs; + end + + addr_hit[413]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_24_qs; + end + + addr_hit[414]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_25_qs; + end + + addr_hit[415]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_26_qs; + end + + addr_hit[416]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_27_qs; + end + + addr_hit[417]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_28_qs; + end + + addr_hit[418]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_29_qs; + end + + addr_hit[419]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_30_qs; + end + + addr_hit[420]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_31_qs; + end + + addr_hit[421]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_32_qs; + end + + addr_hit[422]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_33_qs; + end + + addr_hit[423]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_34_qs; + end + + addr_hit[424]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_35_qs; + end + + addr_hit[425]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_36_qs; + end + + addr_hit[426]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_37_qs; + end + + addr_hit[427]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_38_qs; + end + + addr_hit[428]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_39_qs; + end + + addr_hit[429]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_40_qs; + end + + addr_hit[430]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_41_qs; + end + + addr_hit[431]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_42_qs; + end + + addr_hit[432]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_43_qs; + end + + addr_hit[433]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_44_qs; + end + + addr_hit[434]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_45_qs; + end + + addr_hit[435]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_46_qs; + end + + addr_hit[436]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_47_qs; + end + + addr_hit[437]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_48_qs; + end + + addr_hit[438]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_49_qs; + end + + addr_hit[439]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_50_qs; + end + + addr_hit[440]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_51_qs; + end + + addr_hit[441]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_52_qs; + end + + addr_hit[442]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_53_qs; + end + + addr_hit[443]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_54_qs; + end + + addr_hit[444]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_55_qs; + end + + addr_hit[445]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_56_qs; + end + + addr_hit[446]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_57_qs; + end + + addr_hit[447]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_58_qs; + end + + addr_hit[448]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_59_qs; + end + + addr_hit[449]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_60_qs; + end + + addr_hit[450]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_61_qs; + end + + addr_hit[451]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_62_qs; + end + + addr_hit[452]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_63_qs; + end + + addr_hit[453]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_64_qs; + end + + addr_hit[454]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_65_qs; + end + + addr_hit[455]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_66_qs; + end + + addr_hit[456]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_67_qs; + end + + addr_hit[457]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_68_qs; + end + + addr_hit[458]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_69_qs; + end + + addr_hit[459]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_70_qs; + end + + addr_hit[460]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_71_qs; + end + + addr_hit[461]: begin + reg_rdata_next[1:0] = dio_pad_sleep_mode_72_qs; + end + + addr_hit[462]: begin + reg_rdata_next[0] = wkup_detector_regwen_0_qs; + end + + addr_hit[463]: begin + reg_rdata_next[0] = wkup_detector_regwen_1_qs; + end + + addr_hit[464]: begin + reg_rdata_next[0] = wkup_detector_regwen_2_qs; + end + + addr_hit[465]: begin + reg_rdata_next[0] = wkup_detector_regwen_3_qs; + end + + addr_hit[466]: begin + reg_rdata_next[0] = wkup_detector_regwen_4_qs; + end + + addr_hit[467]: begin + reg_rdata_next[0] = wkup_detector_regwen_5_qs; + end + + addr_hit[468]: begin + reg_rdata_next[0] = wkup_detector_regwen_6_qs; + end + + addr_hit[469]: begin + reg_rdata_next[0] = wkup_detector_regwen_7_qs; + end + + addr_hit[470]: begin + reg_rdata_next = DW'(wkup_detector_en_0_qs); + end + addr_hit[471]: begin + reg_rdata_next = DW'(wkup_detector_en_1_qs); + end + addr_hit[472]: begin + reg_rdata_next = DW'(wkup_detector_en_2_qs); + end + addr_hit[473]: begin + reg_rdata_next = DW'(wkup_detector_en_3_qs); + end + addr_hit[474]: begin + reg_rdata_next = DW'(wkup_detector_en_4_qs); + end + addr_hit[475]: begin + reg_rdata_next = DW'(wkup_detector_en_5_qs); + end + addr_hit[476]: begin + reg_rdata_next = DW'(wkup_detector_en_6_qs); + end + addr_hit[477]: begin + reg_rdata_next = DW'(wkup_detector_en_7_qs); + end + addr_hit[478]: begin + reg_rdata_next = DW'(wkup_detector_0_qs); + end + addr_hit[479]: begin + reg_rdata_next = DW'(wkup_detector_1_qs); + end + addr_hit[480]: begin + reg_rdata_next = DW'(wkup_detector_2_qs); + end + addr_hit[481]: begin + reg_rdata_next = DW'(wkup_detector_3_qs); + end + addr_hit[482]: begin + reg_rdata_next = DW'(wkup_detector_4_qs); + end + addr_hit[483]: begin + reg_rdata_next = DW'(wkup_detector_5_qs); + end + addr_hit[484]: begin + reg_rdata_next = DW'(wkup_detector_6_qs); + end + addr_hit[485]: begin + reg_rdata_next = DW'(wkup_detector_7_qs); + end + addr_hit[486]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_0_qs); + end + addr_hit[487]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_1_qs); + end + addr_hit[488]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_2_qs); + end + addr_hit[489]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_3_qs); + end + addr_hit[490]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_4_qs); + end + addr_hit[491]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_5_qs); + end + addr_hit[492]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_6_qs); + end + addr_hit[493]: begin + reg_rdata_next = DW'(wkup_detector_cnt_th_7_qs); + end + addr_hit[494]: begin + reg_rdata_next[6:0] = wkup_detector_padsel_0_qs; + end + + addr_hit[495]: begin + reg_rdata_next[6:0] = wkup_detector_padsel_1_qs; + end + + addr_hit[496]: begin + reg_rdata_next[6:0] = wkup_detector_padsel_2_qs; + end + + addr_hit[497]: begin + reg_rdata_next[6:0] = wkup_detector_padsel_3_qs; + end + + addr_hit[498]: begin + reg_rdata_next[6:0] = wkup_detector_padsel_4_qs; + end + + addr_hit[499]: begin + reg_rdata_next[6:0] = wkup_detector_padsel_5_qs; + end + + addr_hit[500]: begin + reg_rdata_next[6:0] = wkup_detector_padsel_6_qs; + end + + addr_hit[501]: begin + reg_rdata_next[6:0] = wkup_detector_padsel_7_qs; + end + + addr_hit[502]: begin + reg_rdata_next = DW'(wkup_cause_qs); + end + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + logic reg_busy_sel; + assign reg_busy = (reg_busy_sel | shadow_busy) & tl_i.a_valid; + always_comb begin + reg_busy_sel = '0; + unique case (1'b1) + addr_hit[470]: begin + reg_busy_sel = wkup_detector_en_0_busy; + end + addr_hit[471]: begin + reg_busy_sel = wkup_detector_en_1_busy; + end + addr_hit[472]: begin + reg_busy_sel = wkup_detector_en_2_busy; + end + addr_hit[473]: begin + reg_busy_sel = wkup_detector_en_3_busy; + end + addr_hit[474]: begin + reg_busy_sel = wkup_detector_en_4_busy; + end + addr_hit[475]: begin + reg_busy_sel = wkup_detector_en_5_busy; + end + addr_hit[476]: begin + reg_busy_sel = wkup_detector_en_6_busy; + end + addr_hit[477]: begin + reg_busy_sel = wkup_detector_en_7_busy; + end + addr_hit[478]: begin + reg_busy_sel = wkup_detector_0_busy; + end + addr_hit[479]: begin + reg_busy_sel = wkup_detector_1_busy; + end + addr_hit[480]: begin + reg_busy_sel = wkup_detector_2_busy; + end + addr_hit[481]: begin + reg_busy_sel = wkup_detector_3_busy; + end + addr_hit[482]: begin + reg_busy_sel = wkup_detector_4_busy; + end + addr_hit[483]: begin + reg_busy_sel = wkup_detector_5_busy; + end + addr_hit[484]: begin + reg_busy_sel = wkup_detector_6_busy; + end + addr_hit[485]: begin + reg_busy_sel = wkup_detector_7_busy; + end + addr_hit[486]: begin + reg_busy_sel = wkup_detector_cnt_th_0_busy; + end + addr_hit[487]: begin + reg_busy_sel = wkup_detector_cnt_th_1_busy; + end + addr_hit[488]: begin + reg_busy_sel = wkup_detector_cnt_th_2_busy; + end + addr_hit[489]: begin + reg_busy_sel = wkup_detector_cnt_th_3_busy; + end + addr_hit[490]: begin + reg_busy_sel = wkup_detector_cnt_th_4_busy; + end + addr_hit[491]: begin + reg_busy_sel = wkup_detector_cnt_th_5_busy; + end + addr_hit[492]: begin + reg_busy_sel = wkup_detector_cnt_th_6_busy; + end + addr_hit[493]: begin + reg_busy_sel = wkup_detector_cnt_th_7_busy; + end + addr_hit[502]: begin + reg_busy_sel = wkup_cause_busy; + end + default: begin + reg_busy_sel = '0; + end + endcase + end + + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_strap_sampling.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_strap_sampling.sv new file mode 100644 index 00000000000..6204dce9de4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_strap_sampling.sv @@ -0,0 +1,471 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module pinmux_strap_sampling + import pinmux_pkg::*; + import pinmux_reg_pkg::*; + import prim_pad_wrapper_pkg::*; + import lc_ctrl_pkg::*; +#( + // Taget-specific pinmux configuration passed down from the + // target-specific top-level. + parameter target_cfg_t TargetCfg = DefaultTargetCfg +) ( + input clk_i, + input rst_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + // To padring side + output pad_attr_t [NumIOs-1:0] attr_padring_o, + output logic [NumIOs-1:0] out_padring_o, + output logic [NumIOs-1:0] oe_padring_o, + input logic [NumIOs-1:0] in_padring_i, + // To core side + input pad_attr_t [NumIOs-1:0] attr_core_i, + input logic [NumIOs-1:0] out_core_i, + input logic [NumIOs-1:0] oe_core_i, + output logic [NumIOs-1:0] in_core_o, + // Used for TAP qualification + input logic strap_en_i, + input lc_tx_t lc_dft_en_i, + input lc_tx_t lc_hw_debug_clr_i, + input lc_tx_t lc_hw_debug_en_i, + input lc_tx_t lc_check_byp_en_i, + input lc_tx_t lc_escalate_en_i, + output lc_tx_t pinmux_hw_debug_en_o, + // Sampled values for DFT straps + output dft_strap_test_req_t dft_strap_test_o, + // Hold tap strap select + input dft_hold_tap_sel_i, + // Qualified JTAG signals for TAPs + output jtag_pkg::jtag_req_t lc_jtag_o, + input jtag_pkg::jtag_rsp_t lc_jtag_i, + output jtag_pkg::jtag_req_t rv_jtag_o, + input jtag_pkg::jtag_rsp_t rv_jtag_i, + output jtag_pkg::jtag_req_t dft_jtag_o, + input jtag_pkg::jtag_rsp_t dft_jtag_i +); + + + ///////////////////////////////////// + // Life cycle signal synchronizers // + ///////////////////////////////////// + + prim_mubi_pkg::mubi4_t [0:0] scanmode; + + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) // clock/reset below is only used for SVAs. + ) u_por_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(scanmode) + ); + + typedef enum logic [1:0] { + DftEnSample, + DftEnTapSel, + DftEnLast + } lc_dft_en_e; + + lc_tx_t [DftEnLast-1:0] lc_dft_en; + prim_lc_sync #( + .NumCopies(int'(DftEnLast)) + ) u_prim_lc_sync_lc_dft_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_dft_en_i), + .lc_en_o(lc_dft_en) + ); + lc_tx_t [0:0] lc_hw_debug_clr; + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_lc_hw_debug_clr ( + .clk_i, + .rst_ni, + .lc_en_i(lc_hw_debug_clr_i), + .lc_en_o(lc_hw_debug_clr) + ); + lc_tx_t [0:0] lc_hw_debug_en; + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_lc_hw_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_hw_debug_en_i), + .lc_en_o(lc_hw_debug_en) + ); + lc_tx_t [0:0] lc_check_byp_en; + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_lc_check_byp_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_check_byp_en_i), + .lc_en_o(lc_check_byp_en) + ); + lc_tx_t [0:0] lc_escalate_en; + prim_lc_sync #( + .NumCopies(1) + ) u_prim_lc_sync_lc_escalate_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_escalate_en_i), + .lc_en_o(lc_escalate_en) + ); + + + ///////////////////////////// + // LC_HW_DEBUG_EN Latching // + ///////////////////////////// + + // In order to keep a RV_DM JTAG debug session alive during NDM reset, we need to memorize the + // state of lc_hw_debug_en, since OTP/LC will be reset as part of NDM reset (the only parts not + // reset are in the pwr/rst/clkmgrs, RV_DM and this strap sampling module). We sample the life + // cycle signal state when the strap sampling pulse is asserted bu the PWRMGR. This pulse is + // asserted once during boot (and not after an NDM reset). + // + // Note that DFT TAP selection is not affected by this since we always consume the life value for + // lc_dft_en. We also make sure to invalidate the sampled lc_hw_debug_en whenever lc_check_byp_en + // or lc_escalate_en are not OFF. lc_escalate_en is asserted as part of an escalation, and + // lc_check_byp_en is asserted whenever a life cycle transition is initiated (it causes the OTP + // controller to skip background checks on the life cycle partition as it undergoes + // modification). This makes sure that the sampled value here does not survive a life cycle + // transition. + // + // Finally, note that there is secondary gating on the RV_DM and DFT TAPs that is always consuming + // live lc_hw_debug_en and lc_dft_en signals for added protection. + + // Convert the strap enable pulse to a mubi signal and mask lc_hw_debug_en with it. + lc_tx_t lc_strap_en, lc_hw_debug_en_masked; + assign lc_strap_en = lc_tx_bool_to_lc_tx(strap_en_i); + assign lc_hw_debug_en_masked = lc_tx_and_hi(lc_strap_en, lc_hw_debug_en[0]); + + // Output ON if + // - If the strap sampling pulse is asserted and lc_hw_debug_en is ON + // - If the pinmux_hw_debug_en_q is already set to ON (this is the latching feedback loop) + // Note: make sure we use a hardened, rectifying OR function since otherwise two non-strict + // values may produce a strict ON value. + lc_tx_t hw_debug_en_set, pinmux_hw_debug_en_q; + prim_lc_or_hardened #( + .ActVal(On) + ) u_prim_lc_or_hardened ( + .clk_i, + .rst_ni, + .lc_en_a_i(lc_hw_debug_en_masked), + .lc_en_b_i(pinmux_hw_debug_en_q), + .lc_en_o (hw_debug_en_set) + ); + + // Output ON if both lc_check_byp_en and lc_escalate_en are set to OFF. + lc_tx_t neither_check_byp_nor_escalate; + assign neither_check_byp_nor_escalate = lc_tx_inv(lc_tx_and_lo(lc_check_byp_en[0], + lc_escalate_en[0])); + + // Output ON if the signal above is strictly ON and lc_hw_debug_clr is strictly OFF; otherwise + // output a non-ON value (which may be different from OFF). + lc_tx_t hw_debug_en_gating; + assign hw_debug_en_gating = lc_tx_and_hi(neither_check_byp_nor_escalate, + lc_tx_inv(lc_hw_debug_clr[0])); + + // Gate the hw_debug_en_set signal and feed it into the latching flop. + lc_tx_t pinmux_hw_debug_en_d; + assign pinmux_hw_debug_en_d = lc_tx_and_hi(hw_debug_en_set, hw_debug_en_gating); + + prim_lc_sender u_prim_lc_sender_pinmux_hw_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(pinmux_hw_debug_en_d), + .lc_en_o(pinmux_hw_debug_en_q) + ); + + typedef enum logic [1:0] { + HwDebugEnSample, + HwDebugEnTapSel, + HwDebugEnRvDmOut, + HwDebugEnLast + } pinmux_hw_debug_en_e; + + lc_tx_t [HwDebugEnLast-1:0] pinmux_hw_debug_en; + prim_lc_sync #( + .NumCopies(int'(HwDebugEnLast)), + .AsyncOn(0) // no sync needed + ) u_prim_lc_sync_pinmux_hw_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(pinmux_hw_debug_en_q), + .lc_en_o(pinmux_hw_debug_en) + ); + + // We send this latched version over to the RV_DM in order to gate the JTAG signals and TAP side. + // Note that the bus side will remain gated with the live lc_hw_debug_en value inside RV_DM. + assign pinmux_hw_debug_en_o = pinmux_hw_debug_en[HwDebugEnRvDmOut]; + + // Check that we can correctly latch upon strap_en_i + `ASSERT(LcHwDebugEnSet_A, + (lc_tx_test_true_strict(lc_hw_debug_en[0]) || + lc_tx_test_true_strict(pinmux_hw_debug_en_q)) && + lc_tx_test_false_strict(lc_hw_debug_clr[0]) && + lc_tx_test_false_strict(lc_check_byp_en[0]) && + lc_tx_test_false_strict(lc_escalate_en[0]) && + strap_en_i + |=> + lc_tx_test_true_strict(pinmux_hw_debug_en_q)) + // Check that latching ON can only occur if lc_hw_debug_en_i is set. + `ASSERT(LcHwDebugEnSetRev0_A, + lc_tx_test_false_loose(pinmux_hw_debug_en_q) ##1 + lc_tx_test_true_strict(pinmux_hw_debug_en_q) + |-> + $past(lc_tx_test_true_strict(lc_hw_debug_en[0]))) + // Check that latching ON can only occur if strap_en_i is set. + `ASSERT(LcHwDebugEnSetRev1_A, + lc_tx_test_false_loose(pinmux_hw_debug_en_q) ##1 + lc_tx_test_true_strict(pinmux_hw_debug_en_q) + |-> + $past(strap_en_i)) + // Check that any non-OFF value on lc_check_byp_en_i or lc_escalate_en_i or lc_hw_debug_clr_i + // clears the latched value. + `ASSERT(LcHwDebugEnClear_A, + lc_tx_test_true_loose(lc_check_byp_en[0]) || + lc_tx_test_true_loose(lc_escalate_en[0]) || + lc_tx_test_true_loose(lc_hw_debug_clr[0]) + |=> + lc_tx_test_false_loose(pinmux_hw_debug_en_q)) + + ////////////////////////// + // Strap Sampling Logic // + ////////////////////////// + + logic dft_strap_valid_d, dft_strap_valid_q; + logic lc_strap_sample_en, rv_strap_sample_en, dft_strap_sample_en; + logic [NTapStraps-1:0] tap_strap_d, tap_strap_q; + logic [NDFTStraps-1:0] dft_strap_d, dft_strap_q; + + // The LC strap at index 0 has a slightly different + // enable condition than the DFT strap at index 1. + assign tap_strap_d[0] = (lc_strap_sample_en) ? in_padring_i[TargetCfg.tap_strap0_idx] : + tap_strap_q[0]; + assign tap_strap_d[1] = (rv_strap_sample_en) ? in_padring_i[TargetCfg.tap_strap1_idx] : + tap_strap_q[1]; + + // We're always using the DFT strap sample enable for the DFT straps. + assign dft_strap_d = (dft_strap_sample_en) ? {in_padring_i[TargetCfg.dft_strap1_idx], + in_padring_i[TargetCfg.dft_strap0_idx]} : + dft_strap_q; + + assign dft_strap_valid_d = dft_strap_sample_en | dft_strap_valid_q; + assign dft_strap_test_o.valid = dft_strap_valid_q; + assign dft_strap_test_o.straps = dft_strap_q; + + + // During dft enabled states, we continously sample all straps unless + // told not to do so by external dft logic + logic tap_sampling_en; + logic dft_hold_tap_sel; + // Delay the strap sampling pulse by one cycle so that the pinmux_hw_debug_en above can + // propagate through the pinmux_hw_debug_en_q flop. + logic strap_en_q; + + prim_buf #( + .Width(1) + ) u_buf_hold_tap ( + .in_i(dft_hold_tap_sel_i), + .out_o(dft_hold_tap_sel) + ); + assign tap_sampling_en = lc_tx_test_true_strict(lc_dft_en[DftEnSample]) & ~dft_hold_tap_sel; + + always_comb begin : p_strap_sampling + lc_strap_sample_en = 1'b0; + rv_strap_sample_en = 1'b0; + dft_strap_sample_en = 1'b0; + // Initial strap sampling pulse from pwrmgr, + // qualified by life cycle signals. + // The DFT-mode straps are always sampled only once. + if (strap_en_q && tap_sampling_en) begin + dft_strap_sample_en = 1'b1; + end + // In DFT-enabled life cycle states we continously + // sample the TAP straps to be able to switch back and + // forth between different TAPs. + if (strap_en_q || tap_sampling_en) begin + lc_strap_sample_en = 1'b1; + if (lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnSample])) begin + rv_strap_sample_en = 1'b1; + end + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_strap_sample + if (!rst_ni) begin + tap_strap_q <= '0; + dft_strap_q <= '0; + dft_strap_valid_q <= 1'b0; + strap_en_q <= 1'b0; + end else begin + tap_strap_q <= tap_strap_d; + dft_strap_q <= dft_strap_d; + dft_strap_valid_q <= dft_strap_valid_d; + strap_en_q <= strap_en_i; + end + end + + /////////////////////// + // TAP Selection Mux // + /////////////////////// + + logic jtag_en; + tap_strap_t tap_strap; + jtag_pkg::jtag_req_t jtag_req, lc_jtag_req, rv_jtag_req, dft_jtag_req; + jtag_pkg::jtag_rsp_t jtag_rsp, lc_jtag_rsp, rv_jtag_rsp, dft_jtag_rsp; + + // This muxes the JTAG signals to the correct TAP, based on the + // sampled straps. Further, the individual JTAG signals are gated + // using the corresponding life cycle signal. + assign tap_strap = tap_strap_t'(tap_strap_q); + `ASSERT_KNOWN(TapStrapKnown_A, tap_strap) + + always_comb begin : p_tap_mux + jtag_rsp = '0; + // Note that this holds the JTAGs in reset + // when they are not selected. + lc_jtag_req = '0; + rv_jtag_req = '0; + dft_jtag_req = '0; + // This activates the TDO override further below. + jtag_en = 1'b0; + + unique case (tap_strap) + LcTapSel: begin + lc_jtag_req = jtag_req; + jtag_rsp = lc_jtag_rsp; + jtag_en = 1'b1; + end + RvTapSel: begin + if (lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnTapSel])) begin + rv_jtag_req = jtag_req; + jtag_rsp = rv_jtag_rsp; + jtag_en = 1'b1; + end + end + DftTapSel: begin + if (lc_tx_test_true_strict(lc_dft_en[DftEnTapSel])) begin + dft_jtag_req = jtag_req; + jtag_rsp = dft_jtag_rsp; + jtag_en = 1'b1; + end + end + default: ; + endcase // tap_strap_t'(tap_strap_q) + end + + // Insert hand instantiated buffers for + // these signals to prevent further optimization. + pinmux_jtag_buf u_pinmux_jtag_buf_lc ( + .req_i(lc_jtag_req), + .req_o(lc_jtag_o), + .rsp_i(lc_jtag_i), + .rsp_o(lc_jtag_rsp) + ); + pinmux_jtag_buf u_pinmux_jtag_buf_rv ( + .req_i(rv_jtag_req), + .req_o(rv_jtag_o), + .rsp_i(rv_jtag_i), + .rsp_o(rv_jtag_rsp) + ); + pinmux_jtag_buf u_pinmux_jtag_buf_dft ( + .req_i(dft_jtag_req), + .req_o(dft_jtag_o), + .rsp_i(dft_jtag_i), + .rsp_o(dft_jtag_rsp) + ); + + ////////////////////// + // TAP Input Muxes // + ////////////////////// + + // Inputs connections + assign jtag_req.tck = in_padring_i[TargetCfg.tck_idx]; + assign jtag_req.tms = in_padring_i[TargetCfg.tms_idx]; + assign jtag_req.tdi = in_padring_i[TargetCfg.tdi_idx]; + + // Note that this resets the selected TAP controller in + // scanmode. If the TAP controller needs to be active during + // reset, this reset bypass needs to be adapted accordingly. + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_por_aon_n_mux ( + .clk0_i(in_padring_i[TargetCfg.trst_idx]), + .clk1_i(rst_ni), + .sel_i(prim_mubi_pkg::mubi4_test_true_strict(scanmode[0])), + .clk_o(jtag_req.trst_n) + ); + + // Input tie-off muxes and output overrides + for (genvar k = 0; k < NumIOs; k++) begin : gen_input_tie_off + if (k == TargetCfg.tck_idx || + k == TargetCfg.tms_idx || + k == TargetCfg.trst_idx || + k == TargetCfg.tdi_idx || + k == TargetCfg.tdo_idx) begin : gen_jtag_signal + + // Tie off inputs. + assign in_core_o[k] = (jtag_en) ? 1'b0 : in_padring_i[k]; + + if (k == TargetCfg.tdo_idx) begin : gen_output_mux + // Override TDO output. + assign out_padring_o[k] = (jtag_en) ? jtag_rsp.tdo : out_core_i[k]; + assign oe_padring_o[k] = (jtag_en) ? jtag_rsp.tdo_oe : oe_core_i[k]; + end else begin : gen_output_tie_off + // Make sure these pads are set to high-z. + assign out_padring_o[k] = (jtag_en) ? 1'b0 : out_core_i[k]; + assign oe_padring_o[k] = (jtag_en) ? 1'b0 : oe_core_i[k]; + end + + // Also reset all corresponding pad attributes to the default ('0) when JTAG is enabled. + // This disables functional pad features that may have been set, e.g., pull-up/pull-down. + // Do enable schmitt trigger on JTAG clock and JTAG reset for better signal integrity. + if (k == TargetCfg.tck_idx || k == TargetCfg.trst_idx) begin : gen_schmitt_en + assign attr_padring_o[k] = (jtag_en) ? '{schmitt_en: 1'b1, default: '0} : attr_core_i[k]; + end else begin : gen_no_schmitt + assign attr_padring_o[k] = (jtag_en) ? '0 : attr_core_i[k]; + end + end else begin : gen_other_inputs + assign attr_padring_o[k] = attr_core_i[k]; + assign in_core_o[k] = in_padring_i[k]; + assign out_padring_o[k] = out_core_i[k]; + assign oe_padring_o[k] = oe_core_i[k]; + end + end + + //////////////// + // Assertions // + //////////////// + + `ASSERT_INIT(tck_idxRange_A, TargetCfg.tck_idx >= 0 && TargetCfg.tck_idx < NumIOs) + `ASSERT_INIT(tms_idxRange_A, TargetCfg.tms_idx >= 0 && TargetCfg.tms_idx < NumIOs) + `ASSERT_INIT(trst_idxRange_A, TargetCfg.trst_idx >= 0 && TargetCfg.trst_idx < NumIOs) + `ASSERT_INIT(tdi_idxRange_A, TargetCfg.tdi_idx >= 0 && TargetCfg.tdi_idx < NumIOs) + `ASSERT_INIT(tdo_idxRange_A, TargetCfg.tdo_idx >= 0 && TargetCfg.tdo_idx < NumIOs) + + `ASSERT_INIT(tap_strap0_idxRange_A, TargetCfg.tap_strap0_idx >= 0 && + TargetCfg.tap_strap0_idx < NumIOs) + `ASSERT_INIT(tap_strap1_idxRange_A, TargetCfg.tap_strap1_idx >= 0 && + TargetCfg.tap_strap1_idx < NumIOs) + `ASSERT_INIT(dft_strap0_idxRange_A, TargetCfg.dft_strap0_idx >= 0 && + TargetCfg.dft_strap0_idx < NumIOs) + `ASSERT_INIT(dft_strap1_idxRange_A, TargetCfg.dft_strap1_idx >= 0 && + TargetCfg.dft_strap1_idx < NumIOs) + + `ASSERT(RvTapOff0_A, lc_hw_debug_en_i == Off ##2 strap_en_i && pinmux_hw_debug_en_q == Off + |=> rv_jtag_o == '0) + `ASSERT(RvTapOff1_A, pinmux_hw_debug_en[0] == Off |-> rv_jtag_o == '0) + `ASSERT(DftTapOff0_A, lc_dft_en_i == Off |-> ##2 dft_jtag_o == '0) + + // These assumptions are only used in FPV. They will cause failures in simulations. + `ASSUME_FPV(RvTapOff2_A, lc_hw_debug_en_i == Off ##2 strap_en_i && pinmux_hw_debug_en_q == Off + |=> rv_jtag_i == '0) + `ASSUME_FPV(RvTapOff3_A, pinmux_hw_debug_en[0] == Off |-> rv_jtag_i == '0) + `ASSUME_FPV(DftTapOff1_A, lc_dft_en_i == Off |-> ##2 dft_jtag_i == '0) + +endmodule : pinmux_strap_sampling diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_wkup.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_wkup.sv new file mode 100644 index 00000000000..b8b9a04b71e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/rtl/pinmux_wkup.sv @@ -0,0 +1,91 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module pinmux_wkup + import pinmux_pkg::*; + import pinmux_reg_pkg::*; +#( + parameter int Cycles = 4 +) ( + input clk_i, + input rst_ni, + input wkup_en_i, + input filter_en_i, + input wkup_mode_e wkup_mode_i, + input [WkupCntWidth-1:0] wkup_cnt_th_i, + input pin_value_i, + // Wakeup request pulse signal + output logic aon_wkup_pulse_o +); + + //////////////////////////// + // Optional Signal Filter // + //////////////////////////// + + // This uses a lower value for filtering than GPIO since the always-on clock is slower. If the + // filter is disabled, this reduces to a plain 2-stage flop synchronizer. + logic filter_out_d, filter_out_q; + prim_filter #( + .AsyncOn(1), // Instantiate 2-stage synchronizer + .Cycles(Cycles) + ) u_prim_filter ( + .clk_i, + .rst_ni, + .enable_i(filter_en_i), + .filter_i(pin_value_i), + .filter_o(filter_out_d) + ); + + ////////////////////// + // Pattern Matching // + ////////////////////// + + logic rising, falling; + assign falling = ~filter_out_d & filter_out_q; + assign rising = filter_out_d & ~filter_out_q; + + logic cnt_en, cnt_eq_th; + logic [WkupCntWidth-1:0] cnt_d, cnt_q; + assign cnt_d = (cnt_eq_th) ? '0 : (cnt_en) ? cnt_q + 1'b1 : '0; + + assign cnt_eq_th = (cnt_q >= wkup_cnt_th_i); + + always_comb begin : p_mode + aon_wkup_pulse_o = 1'b0; + cnt_en = 1'b0; + if (wkup_en_i) begin + unique case (wkup_mode_i) + Negedge: begin + aon_wkup_pulse_o = falling; + end + Edge: begin + aon_wkup_pulse_o = rising | falling; + end + HighTimed: begin + cnt_en = filter_out_d; + aon_wkup_pulse_o = cnt_eq_th; + end + LowTimed: begin + cnt_en = ~filter_out_d; + aon_wkup_pulse_o = cnt_eq_th; + end + // Default to rising + default: begin + aon_wkup_pulse_o = rising; + end + endcase + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_aon_pattern + if (!rst_ni) begin + filter_out_q <= 1'b0; + cnt_q <= '0; + end else begin + filter_out_q <= filter_out_d; + cnt_q <= cnt_d; + end + end + +endmodule : pinmux_wkup diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/syn/constraints.sdc b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/syn/constraints.sdc new file mode 100644 index 00000000000..4ca2bfef15c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/syn/constraints.sdc @@ -0,0 +1,58 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Generic constraints file for simple testsynthesis flow + +# note that we do not fix hold timing in this flow +set SETUP_CLOCK_UNCERTAINTY 0.5 + +##################### +# main clock # +##################### +set MAIN_CLK_PIN clk_i +set MAIN_RST_PIN rst_ni +set AON_CLK_PIN clk_aon_i + + +# set main clock to 125 MHz +set MAIN_TCK 8.0 +set_ideal_network ${MAIN_CLK_PIN} +set_ideal_network ${MAIN_RST_PIN} +set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${MAIN_CLK_PIN} + +# other timing constraint in ns +set IN_DEL 1.0 +set OUT_DEL 1.0 +set DELAY ${MAIN_TCK} + +create_clock ${MAIN_CLK_PIN} -period ${MAIN_TCK} +create_clock ${AON_CLK_PIN} -period ${MAIN_TCK} + +# in to out +set_max_delay ${DELAY} -from [all_inputs] -to [all_outputs] +# in to reg / reg to out +set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] [get_ports -of_objects [get_clocks]]] -clock ${MAIN_CLK_PIN} +set_output_delay ${OUT_DEL} [all_outputs] -clock ${MAIN_CLK_PIN} + +set_clock_groups -name group1 -async \ + -group [get_clocks ${MAIN_CLK_PIN} ] \ + -group [get_clocks ${AON_CLK_PIN} ] \ + +##################### +# I/O drive/load # +##################### + +# attach load and drivers to IOs to get a more realistic estimate +set_driving_cell -no_design_rule -lib_cell ${DRIVING_CELL} -pin ${DRIVING_CELL_PIN} [all_inputs] +set_load [load_of ${LOAD_CELL_LIB}/${LOAD_CELL}/${LOAD_CELL_PIN}] [all_outputs] + +# set a nonzero critical range to be able to spot the violating paths better +# in the report +set_critical_range 0.5 ${DUT} + +##################### +# Size Only Cells # +##################### + +set_size_only -all_instances [get_cells -h *u_size_only*] true diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/syn/pinmux_syn_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/syn/pinmux_syn_cfg.hjson new file mode 100644 index 00000000000..ad35b76a61d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/syn/pinmux_syn_cfg.hjson @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Top level dut name (sv module). + name: pinmux + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_ip:pinmux:0.1 + + import_cfgs: [// Project wide common synthesis config file + "{proj_root}/hw/syn/tools/dvsim/common_syn_cfg.hjson"], + + // Timing constraints for this module + sdc_file: "{proj_root}/hw/top_darjeeling_no_ibex/ip_autogen/pinmux/syn/constraints.sdc" + + // Technology specific timing constraints for this module + foundry_sdc_file: "{foundry_root}/top_darjeeling_no_ibex/syn/foundry.constraints.sdc" +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/BUILD new file mode 100644 index 00000000000..72e54623e7c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/BUILD @@ -0,0 +1,25 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.svg", + ]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/README.md new file mode 100644 index 00000000000..7a3d4698fa7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/README.md @@ -0,0 +1,36 @@ +# Power Manager HWIP Technical Specification +[`pwrmgr`](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/pwrmgr/code.svg) + +# Overview + +This document specifies the functionality of the OpenTitan power manager. + +## Features + +- Cold boot, low power entry / exit and reset support. +- 2 different low power modes. +- Software initiated low power entry and hardware requested low power exit. +- Peripheral reset requests +- Low power abort and low power fall-through support. +- ROM integrity check at power-up. +- Local checks for escalator and power stability. + +## Description + +The power manager sequences power, clocks, and reset resources of the design through cold boot, low power entry/exit and reset scenarios. + +Cold boot, also known as POR (power on reset) is the first reset state of the design. +The power manager sequences the design from a freshly reset state to an active state where software can be initialized. + +- Low power entry is the process in which the device enters one of two low power modes (sleep or deep sleep). +- Low power exit is the process in which the device exits low power mode and returns to active state. +- Low power entry is always initiated by software, while low power exit is always initiated by a previously setup hardware event such as pins or internal timers. +- The power manager processes the software and hardware requests to perform the appropriate actions. + +Reset scenarios refer to non-POR events that cause the device to reboot. +There are various stimuli that can cause such a reset, ranging from external user input to watchdog timeout. +The power manager processes the reset request and brings the device to an appropriate state. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/BUILD new file mode 100644 index 00000000000..7608dc3c817 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/BUILD @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_pwrmgr.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = glob([ + "pwrmgr.hjson", + "*_testplan.hjson", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/pwrmgr.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/pwrmgr.hjson new file mode 100644 index 00000000000..fdee9e067a3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/pwrmgr.hjson @@ -0,0 +1,821 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "pwrmgr", + human_name: "Power Manager", + one_line_desc: "Sequences on-chip power, clocks, and resets through different reset and power states", + one_paragraph_desc: ''' + Power Manager sequences on-chip power, clocks, and reset signals on power-on reset (aka cold boot), low power entry and exit, and non-power-on resets. + To this end, it can turn power domains on and off, control root resets with Reset Manager, and control root clock enables with AST and Clock Manager. + During power up, Power Manager is responsible for triggering OTP sensing, initiating Life Cycle Controller, coordinating with ROM Controller for the startup ROM check, and eventually releasing software to execute. + It features several countermeasures to deter fault injection (FI) attacks. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "20", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_pwrmgr", + revisions: [ + { + version: "0.1.0", + life_stage: "L1", + design_stage: "D1", + verification_stage: "V0", // this module is not verified at the block level + dif_stage: "S0", + commit_id: "b2abc989498f072d9a5530f8aab9b58c1f92c9fb" + } + { + version: "1.0.1", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {reset: "rst_main_ni"}, + {clock: "clk_slow_i", reset: "rst_slow_ni"}, + {clock: "clk_lc_i", reset: "rst_lc_ni"}, + {clock: "clk_esc_i", reset: "rst_esc_ni"} + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + interrupt_list: [ + { name: "wakeup", desc: "Wake from low power state. See wake info for more details" }, + ], + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + features: [ + { name: "PWRMGR.STARTUP.LIFE_CYCLE_INITIALIZATION", + desc: "Wait completion of Life Cycle initialization." + } + { name: "PWRMGR.CLOCK_CONTROL.IO_IN_LOW_POWER", + desc: '''Controls whether the IO clock remains active in + low power mode. + ''' + } + { name: "PWRMGR.CLOCK_CONTROL.MAIN_IN_LOW_POWER", + desc: '''Controls whether the MAIN clock remains active in + low power mode. + ''' + } + { name: "PWRMGR.CLOCK_CONTROL.USB_IN_LOW_POWER", + desc: '''Controls whether the USB clock remains active in + low power mode. + ''' + } + { name: "PWRMGR.CLOCK_CONTROL.USB_WHEN_ACTIVE", + desc: "Controls whether the USB clock is enabled in active state." + } + { name: "PWRMGR.LOW_POWER.ENTRY", + desc: '''Controls of low power entry, and cases when low power is + not entered due to interrupts or specific units getting busy. + ''' + } + { name: "PWRMGR.LOW_POWER.DISABLE_POWER" + desc: '''Controls whether power is turned off for non-AON domains when + in low power. + ''' + } + { name: "PWRMGR.LOW_POWER.PINMUX_AON_PIN_WKUP_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request pin_wkup_req from pinmux_aon." + } + { name: "PWRMGR.LOW_POWER.PINMUX_AON_PIN_WKUP_REQ_WAKEUP_REQUEST" + desc: "Wakeup request pin_wkup_req from pinmux_aon." + } + { name: "PWRMGR.LOW_POWER.AON_TIMER_AON_WKUP_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request wkup_req from aon_timer_aon." + } + { name: "PWRMGR.LOW_POWER.AON_TIMER_AON_WKUP_REQ_WAKEUP_REQUEST" + desc: "Wakeup request wkup_req from aon_timer_aon." + } + { name: "PWRMGR.LOW_POWER.SOC_PROXY_WKUP_INTERNAL_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request wkup_internal_req from soc_proxy." + } + { name: "PWRMGR.LOW_POWER.SOC_PROXY_WKUP_INTERNAL_REQ_WAKEUP_REQUEST" + desc: "Wakeup request wkup_internal_req from soc_proxy." + } + { name: "PWRMGR.LOW_POWER.SOC_PROXY_WKUP_EXTERNAL_REQ_WAKEUP_ENABLE" + desc: "Enable wakeup request wkup_external_req from soc_proxy." + } + { name: "PWRMGR.LOW_POWER.SOC_PROXY_WKUP_EXTERNAL_REQ_WAKEUP_REQUEST" + desc: "Wakeup request wkup_external_req from soc_proxy." + } + { name: "PWRMGR.LOW_POWER.WAKE_INFO" + desc: "Record what caused the chip to wakeup from low power." + } + { name: "PWRMGR.RESET.CHECK_ROM_INTEGRITY", + desc: "Wait for successful completion of ROM integrity checks." + } + { name: "PWRMGR.RESET.AON_TIMER_AON_AON_TIMER_RST_REQ_ENABLE", + desc: "Enable reset request from aon_timer_aon." + } + { name: "PWRMGR.RESET.AON_TIMER_AON_AON_TIMER_RST_REQ_REQUEST", + desc: "Reset request from aon_timer_aon." + } + { name: "PWRMGR.RESET.SOC_PROXY_RST_REQ_EXTERNAL_ENABLE", + desc: "Enable reset request from soc_proxy." + } + { name: "PWRMGR.RESET.SOC_PROXY_RST_REQ_EXTERNAL_REQUEST", + desc: "Reset request from soc_proxy." + } + { name: "PWRMGR.RESET.ESCALATION_REQUEST", + desc: "Trigger reset in response to incoming escalation requests." + } + { name: "PWRMGR.RESET.ESCALATION_TIMEOUT", + desc: "Trigger reset in response to non-responsive escalation network." + } + { name: "PWRMGR.RESET.SW_RST_REQUEST", + desc: "Trigger reset in response to rstmgr's sw reset request." + } + { name: "PWRMGR.RESET.MAIN_POWER_GLITCH_RESET", + desc: "Trigger reset in response to glitch in main power." + } + { name: "PWRMGR.RESET.NDM_RESET_REQUEST", + desc: "Trigger reset in response to RV_DM ndm reset." + } + { name: "PWRMGR.RESET.POR_REQUEST", + desc: "Trigger reset in response to POR_N pin." + } + ] + + inter_signal_list: [ + { struct: "pwr_boot_status", + type: "uni", + name: "boot_status", + act: "req", + package: "pwrmgr_pkg", + }, + { struct: "pwr_ast", + type: "req_rsp", + name: "pwr_ast", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_rst", + type: "req_rsp", + name: "pwr_rst", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_clk", + type: "req_rsp", + name: "pwr_clk", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_otp", + type: "req_rsp", + name: "pwr_otp", + act: "req", + package: "pwrmgr_pkg", + }, + + { struct: "pwr_lc", + type: "req_rsp", + name: "pwr_lc", + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "pwr_flash", + type: "uni", + name: "pwr_flash", + act: "rcv", + package: "pwrmgr_pkg", + }, + + { struct: "esc_tx", + type: "uni", + name: "esc_rst_tx", + act: "rcv", + package: "prim_esc_pkg", + }, + + { struct: "esc_rx", + type: "uni", + name: "esc_rst_rx", + act: "req", + package: "prim_esc_pkg", + }, + + { struct: "cpu_pwrmgr", + type: "uni", + name: "pwr_cpu", + act: "rcv", + package: "rv_core_ibex_pkg", + }, + + { struct: "logic", + width: 4, + type: "uni", + name: "wakeups", + act: "rcv", + package: "", + }, + + { struct: "logic", + width: 2, + type: "uni", + name: "rstreqs", + act: "rcv", + package: "", + }, + + { struct: "logic", + type: "uni", + name: "ndmreset_req", + act: "rcv", + }, + + { struct: "logic", + type: "uni", + name: "strap", + act: "req", + package: "", + }, + + { struct: "logic", + type: "uni", + name: "low_power", + act: "req", + package: "", + }, + + { struct: "pwrmgr_data", + type: "uni", + name: "rom_ctrl", + act: "rcv", + width: "3" + package: "rom_ctrl_pkg", + default: "rom_ctrl_pkg::PWRMGR_DATA_DEFAULT" + }, + + { struct: "lc_tx", + type: "uni", + name: "fetch_en", + act: "req", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_dft_en", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "lc_tx", + type: "uni", + name: "lc_hw_debug_en", + act: "rcv", + package: "lc_ctrl_pkg", + }, + + { struct: "mubi4", + type: "uni", + name: "sw_rst_req", + act: "rcv", + package: "prim_mubi_pkg", + }, + ], + + param_list: [ + { name: "NumWkups", + desc: "Number of wakeups", + type: "int", + default: "4", + local: "true" + }, + + { name: "PINMUX_AON_PIN_WKUP_REQ_IDX", + desc: "Vector index for pinmux_aon pin_wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "0", + local: "true" + }, + + { name: "AON_TIMER_AON_WKUP_REQ_IDX", + desc: "Vector index for aon_timer_aon wkup_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "1", + local: "true" + }, + + { name: "SOC_PROXY_WKUP_INTERNAL_REQ_IDX", + desc: "Vector index for soc_proxy wkup_internal_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "2", + local: "true" + }, + + { name: "SOC_PROXY_WKUP_EXTERNAL_REQ_IDX", + desc: "Vector index for soc_proxy wkup_external_req, applies for WAKEUP_EN, WAKE_STATUS and WAKE_INFO", + type: "int", + default: "3", + local: "true" + }, + + + { name: "NumRstReqs", + desc: "Number of peripheral reset requets", + type: "int", + default: "2", + local: "true" + }, + + { name: "NumIntRstReqs", + desc: "Number of pwrmgr internal reset requets", + type: "int", + default: "2", + local: "true" + }, + + { name: "NumDebugRstReqs", + desc: "Number of debug reset requets", + type: "int", + default: "0", + local: "true" + }, + + { name: "NumRomInputs", + desc: "Number of inputs from ROM_CTRL", + type: "int", + default: "3", + local: "true" + }, + { + name: "EscNumSeverities" + desc: "Number of escalation severities" + type: "int" + default: "4" + local: "false" + }, + { + name: "EscPingCountWidth" + desc: "Width of ping count for the escalation receiver" + type: "int" + default: "16" + local: "false" + }, + + { name: "ResetMainPwrIdx", + desc: "Reset req idx for MainPwr", + type: "int", + default: "2", + local: "true" + }, + { name: "ResetEscIdx", + desc: "Reset req idx for Esc", + type: "int", + default: "3", + local: "true" + }, + + ], + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "LC_CTRL.INTERSIG.MUBI", + desc: "life cycle control / debug signals are multibit." + } + { name: "ROM_CTRL.INTERSIG.MUBI", + desc: "rom control done/good signals are multibit." + } + { name: "RSTMGR.INTERSIG.MUBI", + desc: "reset manager software request is multibit." + } + { name: "ESC_RX.CLK.BKGN_CHK", + desc: "Escalation receiver has a background timeout check" + } + { name: "ESC_RX.CLK.LOCAL_ESC", + desc: "Escalation receiver clock timeout has a local reset escalation" + } + { name: "FSM.SPARSE", + desc: "Sparse encoding for slow and fast state machines." + } + { name: "FSM.TERMINAL", + desc: ''' + When FSMs reach a bad state, go into a terminate state that does not + recover without user or external host intervention. + ''' + } + { name: "CTRL_FLOW.GLOBAL_ESC", + desc: "When global escalation is received, proceed directly to reset." + } + { name: "MAIN_PD.RST.LOCAL_ESC", + desc: "When main power domain reset glitches, proceed directly to reset." + } + { name: "CTRL.CONFIG.REGWEN", + desc: "Main control protected by regwen." + } + { name: "WAKEUP.CONFIG.REGWEN", + desc: "Wakeup configuration protected by regwen." + } + { name: "RESET.CONFIG.REGWEN", + desc: "Reset configuration protected by regwen." + } + + ] + + regwidth: "32", + registers: [ + + { name: "CTRL_CFG_REGWEN", + swaccess: "ro", + hwaccess: "hwo", + hwext: "true", + desc: ''' + Controls the configurability of the !!CONTROL register. + + This register ensures the contents do not change once a low power hint and + WFI has occurred. + + It unlocks whenever a low power transition has completed (transition back to the + ACTIVE state) for any reason. + ''', + + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Configuration enable. + + This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. + When the device transitions back from low power state to active state, this bit is set + back to 1 to allow software configuration of !!CONTROL + ''', + resval: "1", + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + + { name: "CONTROL", + desc: "Control register", + swaccess: "rw", + hwaccess: "hro", + regwen: "CTRL_CFG_REGWEN", + tags: [// Turning off USB clock in active state impacts other CSRs + // at the chip level (in other blocks, such as clkmgr), + // so we exclude writing from this register. + "excl:CsrAllTests:CsrExclWrite"] + fields: [ + { bits: "0", + hwaccess: "hrw", + name: "LOW_POWER_HINT", + desc: ''' + The low power hint to power manager. + The hint is an indication for how the manager should treat the next WFI. + Once the power manager begins a low power transition, or if a valid reset request is registered, + this bit is automatically cleared by HW. + ''' + resval: "0" + enum: [ + { value: "0", + name: "None", + desc: ''' + No low power intent + ''' + }, + { value: "1", + name: "Low Power", + desc: ''' + Next WFI should trigger low power entry + ''' + }, + ] + tags: [// The regwen for this reg is RO. CSR seq can't support to check this reg + "excl:CsrAllTests:CsrExclAll"] + }, + + { bits: "4", + name: "CORE_CLK_EN", + desc: "Core clock enable during low power state", + resval: "0", + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + Core clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + Core clock enabled during low power state + ''' + }, + ] + }, + + { bits: "5", + name: "IO_CLK_EN", + desc: "IO clock enable during low power state", + resval: "0", + enum: [ + { value: "0", + name: "Disabled", + desc: ''' + IO clock disabled during low power state + ''' + }, + { value: "1", + name: "Enabled", + desc: ''' + IO clock enabled during low power state + ''' + }, + ] + }, + + { bits: "6", + name: "MAIN_PD_N", + desc: "Active low, main power domain power down", + resval: "1" + enum: [ + { value: "0", + name: "Power down", + desc: ''' + Main power domain is powered down during low power state. + ''' + }, + { value: "1", + name: "Power up", + desc: ''' + Main power domain is kept powered during low power state + ''' + }, + ] + }, + ], + }, + + { name: "CFG_CDC_SYNC", + swaccess: "rw", + hwaccess: "hrw", + hwqe: "true", + desc: ''' + The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the + fast clock domain but used in the slow clock domain. + + The configuration are not propagated across the clock boundary until this + register is triggered and read. See fields below for more details + ''', + + fields: [ + { bits: "0", + name: "SYNC", + desc: ''' + Configuration sync. When this bit is written to 1, a sync pulse is generated. When + the sync completes, this bit then self clears. + + Software should write this bit to 1, wait for it to clear, before assuming the slow clock + domain has accepted the programmed values. + ''', + resval: "0", + }, + ] + tags: [// This bit triggers a payload synchronization and self clears when complete. + // Do not write this bit as there will be side effects and the value will not persist + "excl:CsrNonInitTests:CsrExclWrite"] + }, + + { name: "WAKEUP_EN_REGWEN", + desc: "Configuration enable for wakeup_en register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, WAKEUP_EN register can be configured. + When 0, WAKEUP_EN register cannot be configured. + ''', + }, + ] + }, + + { multireg: + { name: "WAKEUP_EN", + desc: "Bit mask for enabled wakeups", + swaccess: "rw", + hwaccess: "hro", + regwen: "WAKEUP_EN_REGWEN", + resval: "0" + cname: "wakeup_en", + count: "NumWkups" + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that wakeup is also enabled. + Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. + ''', + }, + ] + }, + }, + + { multireg: + { name: "WAKE_STATUS", + desc: "A read only register of all current wake requests post enable mask", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + cname: "wake_status", + count: "NumWkups", + tags: [// Cannot auto-predict current wake request status + "excl:CsrNonInitTests:CsrExclWriteCheck"], + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + Current value of wake requests + ''', + }, + ] + }, + }, + + { name: "RESET_EN_REGWEN", + desc: "Configuration enable for reset_en register", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + resval: "1" + name: "EN", + desc: ''' + When 1, RESET_EN register can be configured. + When 0, RESET_EN register cannot be configured. + ''', + }, + ] + }, + + { multireg: + { name: "RESET_EN", + desc: "Bit mask for enabled reset requests", + swaccess: "rw", + hwaccess: "hro", + regwen: "RESET_EN_REGWEN", + resval: "0" + cname: "rstreq_en", + count: "NumRstReqs" + fields: [ + { bits: "0", + name: "EN", + desc: ''' + Whenever a particular bit is set to 1, that reset request is enabled. + Whenever a particular bit is set to 0, that reset request cannot reset the device. + ''', + }, + ] + tags: [// Self resets should never be triggered by automated tests + "excl:CsrAllTests:CsrExclWrite"] + }, + }, + + { multireg: + { name: "RESET_STATUS", + desc: "A read only register of all current reset requests post enable mask", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + cname: "reset_status", + count: "NumRstReqs", + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + Current value of reset request + ''', + }, + ] + }, + }, + + { name: "ESCALATE_RESET_STATUS", + desc: "A read only register of escalation reset request", + swaccess: "ro", + hwaccess: "hwo", + resval: "0" + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + When 1, an escalation reset has been seen. + When 0, there is no escalation reset. + ''', + }, + ] + }, + + { name: "WAKE_INFO_CAPTURE_DIS", + desc: "Indicates which functions caused the chip to wakeup", + swaccess: "rw", + hwaccess: "hro", + resval: "0" + fields: [ + { bits: "0", + name: "VAL", + desc: ''' + When written to 1, this actively suppresses the wakeup info capture. + When written to 0, wakeup info capture timing is controlled by HW. + ''', + }, + ] + }, + + { name: "WAKE_INFO", + desc: ''' + Indicates which functions caused the chip to wakeup. + The wake info recording begins whenever the device begins a valid low power entry. + + This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. + This means it is possible to capture multiple wakeup reasons. + ''', + swaccess: "rw1c", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + resval: "0" + fields: [ + { bits: "3:0", + name: "REASONS", + desc: "Various peripheral wake reasons" + }, + { bits: "4", + name: "FALL_THROUGH", + desc: ''' + The fall through wakeup reason indicates that despite setting a WFI and providing a low power + hint, an interrupt arrived at just the right time to break the executing core out of WFI. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + { bits: "5", + name: "ABORT", + desc: ''' + The abort wakeup reason indicates that despite setting a WFI and providing a low power + hint, an active flash / lifecycle / otp transaction was ongoing when the power controller + attempted to initiate low power entry. + + The power manager detects this condition, halts low power entry and reports as a wakeup reason + ''', + }, + ] + tags: [// This regwen is completely under HW management and thus cannot be manipulated + // by software. + "excl:CsrNonInitTests:CsrExclCheck"] + }, + + { name: "FAULT_STATUS", + desc: "A read only register that shows the existing faults", + swaccess: "ro", + hwaccess: "hrw", + sync: "clk_lc_i", + resval: "0" + fields: [ + { bits: "0", + name: "REG_INTG_ERR", + desc: ''' + When 1, an integrity error has occurred. + ''', + }, + + { bits: "1", + name: "ESC_TIMEOUT", + desc: ''' + When 1, an escalation clock / reset timeout has occurred. + ''', + }, + + { bits: "2", + name: "MAIN_PD_GLITCH", + desc: ''' + When 1, unexpected power glitch was observed on main PD. + ''', + }, + ] + }, + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson new file mode 100644 index 00000000000..6857dede1b3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/pwrmgr_sec_cm_testplan.hjson @@ -0,0 +1,219 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../pwrmgr/data/pwrmgr.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../pwrmgr/data/pwrmgr_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: '''Verify the countermeasure(s) BUS.INTEGRITY. + This entry is covered by tl_access_test + (hw/dv/tools/dvsim/tests/tl_access_tests.hjson) + ''' + stage: V2S + tests: ["pwrmgr_tl_intg_err"] + } + { + name: sec_cm_lc_ctrl_intersig_mubi + desc: '''Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI. + + **Stimulus**: + - Use comprehensive stimulus - reset and wakeup - + as background traffic to ensure this counter measure + is valid for various states of fast and slow state. + - Drive lc_hw_debug_en_i and lc_dft_en_i with + mixed valid and invalid values. + + **Check**: + - Collect coverage by binding cip_mubi_cov_if to + tb.dut.lc_hw_debug_en_i and tb.dut.lc_dft_en_i + - Add assertion to check whether rom_intg_chk_dis + is set to '1' only when lc_dft_en_i or lc_hw_debug_en_i + is high. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_lc_ctrl_intersig_mubi"] + } + { + name: sec_cm_rom_ctrl_intersig_mubi + desc: '''Verify the countermeasure(s) ROM_CTRL.INTERSIG.MUBI. + + **Stimulus**: + - Use comprehensive stimulus - reset and wakeup - + as background traffic to ensure this counter measure + is valid for various states of fast and slow fsm. + - Drive rom_ctrl_i with mixed valid and invalid values. + + **Check**: + - Collect coverage by binding cip_mubi_cov_if to + tb.dut.rom_ctrl_i + ''' + stage: V2S + tests: ["pwrmgr_wakeup_reset", "pwrmgr_repeat_wakeup_reset"] + } + { + name: sec_cm_rstmgr_intersig_mubi + desc: '''Verify the countermeasure(s) RSTMGR.INTERSIG.MUBI. + + **Stimulus**: + - Drive tb.dut.sw_rst_req_i with mixed valid and invalid values + + **Check**: + - See sw rst only happens when dut gets valid value by + probing fast fsm state. The state has to move low power state. + - Collect coverage by binding cip_mubi_cov_if to + tb.dut.sw_rst_req_i + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_rstmgr_intersig_mubi"] + } + { + name: sec_cm_esc_rx_clk_bkgn_chk + desc: '''Verify the countermeasure(s) ESC_RX.CLK.BKGN_CHK. + + **Stimulus**: + - At FastPwrStateActive state, create escalation clock + or reset failure by stopping clock or asserting reset. + + **Check**: + - Expecting fatal alert event and rstreqs[ResetEscIdx]. + - Add assertion to see if u_esc_timeout happens, then + rstreqs[ResetEscIdx] should be asserted. + - After the alert agent processese the alert + by asserting escalation reset, + see if dut is back to normal operation state. + ''' + stage: V2S + tests: ["pwrmgr_esc_clk_rst_malfunc"] + } + { + name: sec_cm_esc_rx_clk_local_esc + desc: '''Verify the countermeasure(s) ESC_RX.CLK.LOCAL_ESC. + + This is triggered by common cm primitives (SecCmPrimCount). + (https://github.com/lowRISC/opentitan/blob/master + /hw/dv/sv/cip_lib/doc/index.md#security-verification + -for-common-countermeasure-primitives) + + **Check**: + - Detect fast state transition to FastPwrStateResetPrep. + - Add assertion to check if u_sec_timeout happens, then + rstreqs[ResetEscIdx] should be asserted. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm"] + } + { + name: sec_cm_fsm_sparse + desc: '''Verify the countermeasure(s) FSM.SPARSE. + This is triggered by common cm primitives (SecCmPrimSparseFsmFlop). + (https://github.com/lowRISC/opentitan/blob/master + /hw/dv/sv/cip_lib/doc/index.md#security-verification + -for-common-countermeasure-primitives) + ''' + stage: V2S + tests: ["pwrmgr_sec_cm"] + } + { + name: sec_cm_fsm_terminal + desc: '''Verify the countermeasure(s) FSM.TERMINAL. + + This is caused by any invalid (slow|fast) state. + + **Check**: + - If slow state is invalid, fast state becomes FastPwrStateInvalid, + pwr_ast_o.pwr_clamp =1 and pwr_ast_o.main_pd_n = 0. + - If fast state is invalid, pwr_rst_o.rst_lc_req is all one, + pwr_rst_o.rst_sys_req is all one and pwr_clk_o = 0. + Dut should be recovered by asserting rst_n = 0. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm"] + } + { + name: sec_cm_ctrl_flow_global_esc + desc: '''Verify the countermeasure(s) CTRL_FLOW.GLOBAL_ESC. + + **Stimulus**: + - Send escalation request to esc_rst_tx_i + + **Check**: + - Check fast state transition to FastPwrStateResetPrep + - Add assertion to see if we get pwr_rst_o.rstreqs[ResetEscIdx] + set when dut receives esc_rst_tx_i + ''' + stage: V2S + tests: ["pwrmgr_global_esc"] + } + { + name: sec_cm_main_pd_rst_local_esc + desc: '''Verify the countermeasure(s) MAIN_PD.RST.LOCAL_ESC. + + **Stimulus**: + - Create power reset glitch by setting tb.dut.rst_main_ni + and tb.dut.pwr_ast_i.main_pok to 0 + + **Check**: + - Check fast state transition to FastPwrStateResetPrep + - Add assertion to see if we get pwr_rst_o.rstreqs[ResetMainPwrIdx] + ''' + stage: V2S + tests: ["pwrmgr_glitch"] + } + { + name: sec_cm_ctrl_config_regwen + desc: '''Verify the countermeasure(s) CTRL.CONFIG.REGWEN. + + **Stimulus**: + - Initiate low power transition by setting + PWRMGR.CONTROL.LOW_POWER_HINT to 1. Wait for a few cycle + to ensure the csr value propagates to slow clock domain. + Then issue csr write to PWRMGR.CONTROL + + **Check**: + - After the csr update under PWRMGR.CTRL_CFG_REGWEN = 0, + read back and check the value is not updated by + the csr update attempt. + ''' + stage: V2S + tests: ["pwrmgr_sec_cm_ctrl_config_regwen"] + } + { + name: sec_cm_wakeup_config_regwen + desc: '''Verify the countermeasure(s) WAKEUP.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["pwrmgr_csr_rw"] + } + { + name: sec_cm_reset_config_regwen + desc: '''Verify the countermeasure(s) RESET.CONFIG.REGWEN. + + This is covered by auto csr test. + ''' + stage: V2S + tests: ["pwrmgr_csr_rw"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson new file mode 100644 index 00000000000..aad3a73fc56 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/pwrmgr_testplan.hjson @@ -0,0 +1,369 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "pwrmgr" + import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson", + "pwrmgr_sec_cm_testplan.hjson"] + testpoints: [ + { + name: smoke + desc: ''' + Smoke test exercising the pwrmgr state transitions. + + - Brings pwrmgr out of POR. + - Enables wakeup. + - Triggers SW initiated low power transition with reset settings + in `control` CSR. + - Triggers wakeup. + - Enables and triggers a reset. + - Waits for pwrmgr to be out of reset. + + **Stimulus**: + - CSR writes to `wakeup_en`, `reset_en`, and `low_power_hint`. + - Needs many input pins to line up correctly in order to prevent the + pwrmgr from waiting forever. Most of these are set in response + to outputs, and are checked by SVA. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - The wakeup and reset causes are as expected reading CSRs + `wake_status` and `reset_status`. + - The output `pwr_rst_req.reset_cause` matches a low power or + reset cause. + - The output `pwr_rst_req.rstreqs` matches the enabled resets. + ''' + stage: V1 + tests: ["pwrmgr_smoke"] + } + { + name: wakeup + desc: ''' + Test random wakeup, wakeup_en, wake_info_capture_dis, and + interrupt. + + The different wakeup inputs can be disabled via bits in the + `wakeup_en` CSR. Update of `wakeup_info` can be disabled + via the `wake_info_capture_dis` CSR. Any wakeup causes an + interrupt unless interrupts are disabled. + + **Stimulus**: + - Sets `wakeup_en` randomly but don't set it to zero, or the + test will timeout. + - Set `wake_info_capture_dis` randomly on and off. + - Bring pwrmgr to low power. + - Set `wakeups_i` inputs randomly. + - Set `intr_enable` randomly. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - Depending on `wakeups_i`: + - If all wakeups are disabled, wait some time checking the + state remains inactive. + - Set `wakeups_i` so at least one is enabled. + - Checks `wakeup_status` CSR during transition to active state + since the reset involved will clear the wakeups_i input. + - Checks the `wake_info` CSR. + - Checks the output `pwr_rst_req.reset_cause` is `LowPwrEntry`. + - Check that `intr_wakeup_o` is set according to `intr_enable` CSR. + - Coverage collected by `wakeup_cg` and `wakeup_intr_cg`. + ''' + stage: V2 + tests: ["pwrmgr_wakeup"] + } + { + name: control_clks + desc: ''' + Test CSR control of peripheral clocks during low power. + + The peripheral clocks can be configured to remain on or be turned + off during low power with bits in the `control` CSR register. The + usb clock can also be configured off in active mode. + + **Stimulus**: + - Sets these control bits at random. + - Cause a low power transition and wakeup. + + **Checks**: + - The clock enable outputs to the AST clocks during a low + power transition match the control bits. + - The usb clock enable is also checked during active mode against + the control register. + ''' + stage: V2 + tests: ["pwrmgr_wakeup"] + } + { + name: aborted_low_power + desc: ''' + Test aborted low power transitions. + + Low power transitions can be aborted in two cases: + - The processor gets an interrupt soon after a low power entry is + triggered. + - OTP, LC, or FLASH are not idle. + This test aborts low power transitions, and disables any wakeups, + so the test would timeout if low power was entered. + + **Stimulus**: + - Bring pwrmgr to low power. + - Either disable `pwr_cpu.core_sleeping` or keep some of `lc_idle`, + `otp_idle`, or `flash_idle` inputs off. + - Disable all wakeup enables. + - Randomly set `wakeup_info_capture_dis` CSR. + + **Checks**: + - The `ctrl_cfg_regwen` CSR reads as 1 on the first attempt. + - Checks the output `pwr_rst_req.reset_cause` doesn't change for + a bounded amount of time. + - Check that the `wakeup_info` CSR flags either `fall_through` or + `abort` events when capture is enabled. + ''' + stage: V2 + tests: ["pwrmgr_aborted_low_power", "pwrmgr_lowpower_invalid"] + } + { + name: reset + desc: ''' + Test random reset and reset_en. + + Conditional reset inputs can be disabled via bits in the `reset_en` + CSR, while escalation and main power are unconditional. Resets can + be triggered either in active or low power state. + + **Stimulus**: + - Sets `reset_en` randomly. + - Randomly choose whether to put the unit in low power mode. + - Generate resets randomly in value and time: + - Conditionals via rstreqs_i, + - Main power glitch via rst_main_ni. + - Escalation via `esc_rst_tx_i`. + - Sw reset from rstmgr via `sw_rst_req_i`. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - Checks the `reset_status` CSRs. + - Checks `ip_clk_en` output has a low transition. + - SVA that when `pwr_rst_req.reset_cause` is HwReq, and the output + `pwr_rst_req.rstreqs` matches the unconditional and enabled + conditional resets inputs. + ''' + stage: V2 + tests: ["pwrmgr_reset", "pwrmgr_reset_invalid"] + } + { + name: main_power_glitch_reset + desc: ''' + Test reset due to a glitch in main power. + + A power glitch causes an unconditional reset. + + **Stimulus**: + - Set the rst_main_ni input low indicating a main power glitch. + + **Checks**: + - The fast fsm becomes active when `fetch_en_o` output rises. + - Checks the `reset_status` CSRs. + - Checks `ip_clk_en` output has a low transition. + - Checks the output `pwr_rst_req.reset_cause` matches HwReq. + - Checks the output `pwr_rst_req.rstreqs` matches power glitch. + ''' + stage: V2 + tests: ["pwrmgr_reset"] + } + { + name: reset_wakeup_race + desc: ''' + Test wakeup from low power and reset request almost coinciding. + + If a wakeup from low power and a reset occur at nearly the same time + the system handles them one at a time. + + **Stimulus**: + - Trigger reset and wakeup from low power as described for other + testpoints. + - Issue reset and wakeup a random number of cycles after the slow + state machine is in LowPower state. + - This also checks them coinciding. + + **Check**: + - Similar tests as for the wakeup and reset testpoints, except + making sure they happen per the triggering order. + ''' + stage: V2 + tests: ["pwrmgr_wakeup_reset"] + } + { + name: lowpower_wakeup_race + desc: ''' + Test wakeups coming close to lowpower entry. + + If low power entry and a wakeup are closely aligned the hardware + could get confused. Notice this is very unlikely, since wakeup is + only sensed when the slow fsm is in LowPower state. + + **Stimulus**: + - Trigger low power entry as described for other testpoints. + - Have all wakeups enabled. + - Assert wakeups_i in the temporal neighborhood of low power + entry. + + **Check**: + - No timeout occurs. + - Either pwrmgr remains active or a full low power cycle occurs. + ''' + stage: V2 + tests: ["pwrmgr_lowpower_wakeup_race"] + } + { + name: disable_rom_integrity_check + desc: ''' + Test rom integrity check is disabled under life cycle test states. + + While running a series of reset event, at FastPwrStateRomCheck + state, + - Drive lc_hw_debug_en_i and lc_dft_en_i to random value + excluding {lc_ctrl_pkg::On, lc_ctrl_pkg::On} for both ports. + - Set rom_ctrl_i.good = Mubi4False. + - Wait for a while to make sure fsm state check is not FastPwrStateActive. + + Then, + - Drive lc_hw_debug_en_i and lc_dft_en_i to {lc_ctrl_pkg::On, lc_ctrl_pkg::On} + - Check test finish gracefully. + + Try these steps with different lc_ctrl inputs. + ''' + stage: V2 + tests: ["pwrmgr_disable_rom_integrity_check"] + } + { + name: escalation_timeout + desc: '''This tests the escalation timeout feature. + + If the escalation network doesn't respond to an outgoing "health" + requests within 128 cycles pwrmgr should issue an escalation reset + request. + + **Stimulus**: + - Cause the external escalation network to stop responding, either + disabling the clock or jamming the differential pairs. + + **Check**: + - After 128 cycles of inactivity an escalation reset should be + triggered. + ''' + stage: V3 + tests: ["pwrmgr_escalation_timeout"] + } + { + name: stress_all + desc: '''This runs random sequences in succession. + + Randomly chooses from the following sequences: + - pwrmgr_aborted_low_power_vseq + - pwrmgr_lowpower_wakeup_race_vseq + - pwrmgr_reset_vseq + - pwrmgr_smoke_vseq + - pwrmgr_wakeup_reset_vseq + - pwrmgr_wakeup_vseq + ''' + stage: V2 + tests: ["pwrmgr_stress_all"] + } + ] + + covergroups: [ + { + name: wakeup_ctrl_cg + desc: ''' + Collects coverage on wakeup enable and capture functionality. + + This is collected per individual wakeup bit. Covergroup contains + coverpoints for the `wakeup_en` CSR bit, `wakeup_info_capture_dis` + CSR, `wakeups_i` input bit, and `wakeup_status` CSR bit, and their + cross. + ''' + } + { + name: wakeup_intr_cg + desc: ''' + Collects coverage on interrupts for wakeup functionality. + + This is collected per individual wakeup bit. Covergroup contains + coverpoints for the `intr_en` CSR, the `wakeup_status` CSR bit, + the `intr_status` CSR, the output `intr_wakeup` port, and their + cross. + ''' + } + { + name: control_cg + desc: ''' + Collects coverage on clock and power bits from `control` CSR during + a lowpower transition and active state. + ''' + } + { + name: hw_reset_0_cg + desc: ''' + Collects coverage related to external reset `0`. + + Covergroup contains coverpoints for the `rstreqs_i[0]` external + reset input, its corresponding bit in `reset_en` CSR, and whether + this reset is asserted during low power state, and suitable crosses. + ''' + } + { + name: hw_reset_1_cg + desc: ''' + Collects coverage related to external reset `1`. + + Covergroup contains coverpoints for the `rstreqs_i[1]` external + reset input, its corresponding bit in `reset_en` CSR, and whether + this reset is asserted during low power state, and suitable crosses. + ''' + } + { + name: rstmgr_sw_reset_cg + desc: ''' + Collects coverage on the software reset from rstmgr. + + Covergroup contains a coverpoint for the input `sw_rst_req_i` from + rstmgr. + ''' + } + { + name: main_power_reset_cg + desc: ''' + Collects coverage on resets due to a main power glitch. + + Covergroup contains a coverpoint for the input `rst_main_i` that + triggers a power glitch reset, and whether this reset is asserted + during low power state. + ''' + } + { + name: esc_reset_cg + desc: ''' + Collects coverage on resets due to escalation. + + Covergroup contains a coverpoint for the input `esc_rst_tx_i` that + triggers an escalation reset, and whether this reset is asserted + during low power state. + ''' + } + { + name: reset_wakeup_distance_cg + desc: ''' + Covergroup contains a coverpoint for the difference between the + cycles when the reset and the wakeup were received in the inputs. + The difference is positive when reset happened after wakeup, and + zero when the two happened at the same clock cycle. + ''' + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/top_darjeeling_no_ibex_pwrmgr.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/top_darjeeling_no_ibex_pwrmgr.ipconfig.hjson new file mode 100644 index 00000000000..1c075309b3d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/top_darjeeling_no_ibex_pwrmgr.ipconfig.hjson @@ -0,0 +1,76 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_pwrmgr + param_values: + { + NumWkups: 4 + Wkups: + [ + { + name: pin_wkup_req + width: "1" + module: pinmux_aon + } + { + name: wkup_req + width: "1" + module: aon_timer_aon + } + { + name: wkup_internal_req + width: "1" + module: soc_proxy + } + { + name: wkup_external_req + width: "1" + module: soc_proxy + } + ] + NumRstReqs: 2 + rst_reqs: + { + int: + [ + { + name: MainPwr + desc: main power glitch reset request + module: pwrmgr_aon + } + { + name: Esc + desc: escalation reset request + module: alert_handler + } + ] + peripheral: + [ + { + name: aon_timer_rst_req + width: "1" + module: aon_timer_aon + desc: Watchdog reset request. + } + { + name: rst_req_external + width: "1" + module: soc_proxy + desc: External reset request + } + ] + } + wait_for_external_reset: true + NumRomInputs: 3 + has_aon_clk: true + src_clks: + [ + main + io + ] + topname: darjeeling_no_ibex + uniquified_modules: {} + module_instance_name: pwrmgr + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/defs.bzl new file mode 100644 index 00000000000..23906f532d8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/defs.bzl @@ -0,0 +1,11 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +PWRMGR = opentitan_ip( + name = "pwrmgr", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data:pwrmgr.hjson", + ipconfig = "//hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data:top_darjeeling_no_ibex_pwrmgr.ipconfig.hjson", + extension = "//hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util:dt", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/checklist.md b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/checklist.md new file mode 100644 index 00000000000..2cb33d32f77 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/checklist.md @@ -0,0 +1,266 @@ +# PWRMGR Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [PWRMGR peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done |[PWRMGR Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | N/A | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | N/A | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Done | +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | @matutem, @vogelpi, @adk +Review | Signoff date | Done | 2024-08-06 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [PWRMGR DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | [PWRMGR testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | Block has no mem +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exceptions: debug, power, performance +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | NA | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | NA | +Tests | [SIM_FW_SIMULATED][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | NA | +Coverage | [FPV_COI_COVERAGE_V2][] | NA | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Done | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_VERIFIED][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | UNR will be added after intra structure issue is resolved. +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Done | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | NA | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | NA | +Coverage | [FPV_COI_COVERAGE_AT_100][] | NA | +Code Quality | [ALL_TODOS_RESOLVED][] | Done | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/interfaces.md b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/interfaces.md new file mode 100644 index 00000000000..4363a5bf127 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/interfaces.md @@ -0,0 +1,68 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`pwrmgr`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_slow_i`**, **`clk_lc_i`**, **`clk_esc_i`** +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:---------------|:-----------------------------|:--------|:------|--------:|:--------------| +| boot_status | pwrmgr_pkg::pwr_boot_status | uni | req | 1 | | +| pwr_ast | pwrmgr_pkg::pwr_ast | req_rsp | req | 1 | | +| pwr_rst | pwrmgr_pkg::pwr_rst | req_rsp | req | 1 | | +| pwr_clk | pwrmgr_pkg::pwr_clk | req_rsp | req | 1 | | +| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | req | 1 | | +| pwr_lc | lc_ctrl_pkg::pwr_lc | req_rsp | req | 1 | | +| pwr_flash | pwrmgr_pkg::pwr_flash | uni | rcv | 1 | | +| esc_rst_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | | +| esc_rst_rx | prim_esc_pkg::esc_rx | uni | req | 1 | | +| pwr_cpu | rv_core_ibex_pkg::cpu_pwrmgr | uni | rcv | 1 | | +| wakeups | logic | uni | rcv | 4 | | +| rstreqs | logic | uni | rcv | 2 | | +| ndmreset_req | logic | uni | rcv | 1 | | +| strap | logic | uni | req | 1 | | +| low_power | logic | uni | req | 1 | | +| rom_ctrl | rom_ctrl_pkg::pwrmgr_data | uni | rcv | 3 | | +| fetch_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | | +| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| sw_rst_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Interrupts + +| Interrupt Name | Type | Description | +|:-----------------|:-------|:----------------------------------------------------------| +| wakeup | Event | Wake from low power state. See wake info for more details | + +## Security Alerts + +| Alert Name | Description | +|:-------------|:----------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:------------------------------|:-------------------------------------------------------------------------------------------------------------------------| +| PWRMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| PWRMGR.LC_CTRL.INTERSIG.MUBI | life cycle control / debug signals are multibit. | +| PWRMGR.ROM_CTRL.INTERSIG.MUBI | rom control done/good signals are multibit. | +| PWRMGR.RSTMGR.INTERSIG.MUBI | reset manager software request is multibit. | +| PWRMGR.ESC_RX.CLK.BKGN_CHK | Escalation receiver has a background timeout check | +| PWRMGR.ESC_RX.CLK.LOCAL_ESC | Escalation receiver clock timeout has a local reset escalation | +| PWRMGR.FSM.SPARSE | Sparse encoding for slow and fast state machines. | +| PWRMGR.FSM.TERMINAL | When FSMs reach a bad state, go into a terminate state that does not recover without user or external host intervention. | +| PWRMGR.CTRL_FLOW.GLOBAL_ESC | When global escalation is received, proceed directly to reset. | +| PWRMGR.MAIN_PD.RST.LOCAL_ESC | When main power domain reset glitches, proceed directly to reset. | +| PWRMGR.CTRL.CONFIG.REGWEN | Main control protected by regwen. | +| PWRMGR.WAKEUP.CONFIG.REGWEN | Wakeup configuration protected by regwen. | +| PWRMGR.RESET.CONFIG.REGWEN | Reset configuration protected by regwen. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/programmers_guide.md b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/programmers_guide.md new file mode 100644 index 00000000000..4fb6b768d97 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/programmers_guide.md @@ -0,0 +1,81 @@ +# Programmer's Guide + +The process in which the power manager is used is highly dependent on the system's topology. +The following proposes one method for how this can be done. + +Assume first the system has the power states described [above](theory_of_operation.md#supported-low-power-modes). + +## Programmer Sequence for Entering Low Power + +1. Disable interrupt handling. +2. Mask all interrupt sources that should not prevent low power entry. + - Note that merely *disabling* interrupt handling with the `mie` global interrupt-enable bit on the processing host is insufficient. + - Interrupt sources that are not masked can cause the [fall through exit](theory_of_operation.md#fall-through-handling). +3. Enable desired wakeup and reset sources in [`WAKEUP_EN`](registers.md#wakeup_en) and [`RESET_EN`](registers.md#reset_en). +4. Perform any system-specific low power entry steps, e.g. + - Interrupt checks (if something became pending prior to disable) +5. Configure low power mode configuration in [`CONTROL`](registers.md#control). + - [`LOW_POWER_HINT`](registers.md#control--low_power_hint) must be set to trigger low power entry when the CPU sleeps. +7. Set and poll [`CFG_CDC_SYNC`](registers.md#cfg_cdc_sync) to ensure above settings propagate across clock domains. +8. Execute wait-for-interrupt instruction on the processing host. + +Note that entering low power mode requires that pwrmgr's `pwr_cpu_i.core_sleeping` input be at logic high long enough to be sampled. +A wait-for-interrupt instruction does not guarantee entry into low power, since the CPU could immediately resume execution in some cases. + +### Possible Exits + +Once low power is initiated, the system may exit due to several reasons. +1. Graceful low power exit - This exit occurs when some source in the system gracefully wakes up the power manager. +2. System reset request - This exit occurs when either software or a peripheral requests the pwrmgr to reset the system. +3. [Fall through exit](theory_of_operation.md#fall-through-handling) - This exit occurs when an interrupt manages to break the wait-for-interrupt loop. +4. [Aborted entry](theory_of_operation.md#abort-handling) - This exit occurs when low power entry is attempted with an ongoing non-volatile transaction. + +In both fall through exit and aborted entry, the power manager does not actually enter low power. +Instead the low power entry is interrupted and the system restored to active state. + +In addition, a CPU's sleeping signal that is too short for the power manager to sample will not trigger even an attempt to go to low power. +In such cases, there will be no bits set in [`WAKE_INFO`](registers.md#wake_info), and no side effects of pwrmgr entering low power mode will trigger. + +To check the exit condition, software can follow these steps: +1. Clear low power hint in [`CONTROL`](registers.md#control) and poll until it becomes cleared. + + - Until the hint clears, the values in [`WAKE_INFO`](registers.md#wake_info) may not reflect the true exit condition. +2. Check [`WAKE_INFO`](registers.md#wake_info) to get the condition. + - If no bits are set, then this was a fast fall through, where low power entry was not attempted. + +## Programmer Sequence for Exiting Low Power + +There are two separate cases for low power exit. +One is exiting from deep sleep, and the other is exiting from normal sleep. + +### Exiting from Deep Sleep + +When exiting from deep sleep, the system begins execution in ROM. + +1. Complete normal preparation steps. +2. Check reset cause in [rstmgr](../../rstmgr/README.md) +3. Re-enable modules that have powered down. +4. Disable wakeup recording through [`WAKE_INFO_CAPTURE_DIS`](registers.md#wake_info_capture_dis). +5. Check which source woke up the system through [`WAKE_INFO`](registers.md#wake_info). +6. Take appropriate steps to handle the wake and resume normal operation. +7. Once wake is handled, clear the wake indication in [`WAKE_INFO`](registers.md#wake_info). + +### Exiting from Normal Sleep + +The handling for fall-through and abort are similar to normal sleep exit. +Since in these scenarios the system was not reset, software continues executing the instruction after the wait-for-interrupt invocation. + +1. Check exit condition to determine appropriate steps. +2. Clear low power hints and configuration in [`CONTROL`](registers.md#control). +3. Set and poll [`CFG_CDC_SYNC`](registers.md#cfg_cdc_sync) to ensure setting changes have propagated across clock boundaries. +4. Disable wakeup sources and stop recording. +5. Re-enable interrupts for normal operation and wakeup handling. +6. Once wake is handled, clear the wake indication in [`WAKE_INFO`](registers.md#wake_info). + +For an in-depth discussion, please see [power management programmers model](https://docs.google.com/document/d/1w86rmvylJgZVmmQ6Q1YBcCp2VFctkQT3zJ408SJMLPE/edit?usp=sharing) for additional details. + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_pwrmgr.h) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/pwrmgr_connectivity.svg b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/pwrmgr_connectivity.svg new file mode 100644 index 00000000000..b525330ca14 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/pwrmgr_connectivity.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/pwrmgr_fsms.svg b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/pwrmgr_fsms.svg new file mode 100644 index 00000000000..962794cd0ab --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/pwrmgr_fsms.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/registers.md b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/registers.md new file mode 100644 index 00000000000..24029a45e83 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/registers.md @@ -0,0 +1,411 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------------------| +| pwrmgr.[`INTR_STATE`](#intr_state) | 0x0 | 4 | Interrupt State Register | +| pwrmgr.[`INTR_ENABLE`](#intr_enable) | 0x4 | 4 | Interrupt Enable Register | +| pwrmgr.[`INTR_TEST`](#intr_test) | 0x8 | 4 | Interrupt Test Register | +| pwrmgr.[`ALERT_TEST`](#alert_test) | 0xc | 4 | Alert Test Register | +| pwrmgr.[`CTRL_CFG_REGWEN`](#ctrl_cfg_regwen) | 0x10 | 4 | Controls the configurability of the [`CONTROL`](#control) register. | +| pwrmgr.[`CONTROL`](#control) | 0x14 | 4 | Control register | +| pwrmgr.[`CFG_CDC_SYNC`](#cfg_cdc_sync) | 0x18 | 4 | The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the | +| pwrmgr.[`WAKEUP_EN_REGWEN`](#wakeup_en_regwen) | 0x1c | 4 | Configuration enable for wakeup_en register | +| pwrmgr.[`WAKEUP_EN`](#wakeup_en) | 0x20 | 4 | Bit mask for enabled wakeups | +| pwrmgr.[`WAKE_STATUS`](#wake_status) | 0x24 | 4 | A read only register of all current wake requests post enable mask | +| pwrmgr.[`RESET_EN_REGWEN`](#reset_en_regwen) | 0x28 | 4 | Configuration enable for reset_en register | +| pwrmgr.[`RESET_EN`](#reset_en) | 0x2c | 4 | Bit mask for enabled reset requests | +| pwrmgr.[`RESET_STATUS`](#reset_status) | 0x30 | 4 | A read only register of all current reset requests post enable mask | +| pwrmgr.[`ESCALATE_RESET_STATUS`](#escalate_reset_status) | 0x34 | 4 | A read only register of escalation reset request | +| pwrmgr.[`WAKE_INFO_CAPTURE_DIS`](#wake_info_capture_dis) | 0x38 | 4 | Indicates which functions caused the chip to wakeup | +| pwrmgr.[`WAKE_INFO`](#wake_info) | 0x3c | 4 | Indicates which functions caused the chip to wakeup. | +| pwrmgr.[`FAULT_STATUS`](#fault_status) | 0x40 | 4 | A read only register that shows the existing faults | + +## INTR_STATE +Interrupt State Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw1c | 0x0 | wakeup | Wake from low power state. See wake info for more details | + +## INTR_ENABLE +Interrupt Enable Register +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "wakeup", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | wakeup | Enable interrupt when [`INTR_STATE.wakeup`](#intr_state) is set. | + +## INTR_TEST +Interrupt Test Register +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "wakeup", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | wakeup | Write 1 to force [`INTR_STATE.wakeup`](#intr_state) to 1. | + +## ALERT_TEST +Alert Test Register +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:-------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | + +## CTRL_CFG_REGWEN +Controls the configurability of the [`CONTROL`](#control) register. + +This register ensures the contents do not change once a low power hint and +WFI has occurred. + +It unlocks whenever a low power transition has completed (transition back to the +ACTIVE state) for any reason. +- Offset: `0x10` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | ro | 0x1 | EN | Configuration enable. This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. When the device transitions back from low power state to active state, this bit is set back to 1 to allow software configuration of [`CONTROL`](#control) | + +## CONTROL +Control register +- Offset: `0x14` +- Reset default: `0x40` +- Reset mask: `0x71` +- Register enable: [`CTRL_CFG_REGWEN`](#ctrl_cfg_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "LOW_POWER_HINT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "CORE_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IO_CLK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MAIN_PD_N", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-------------------------------------------| +| 31:7 | | | Reserved | +| 6 | rw | 0x1 | [MAIN_PD_N](#control--main_pd_n) | +| 5 | rw | 0x0 | [IO_CLK_EN](#control--io_clk_en) | +| 4 | rw | 0x0 | [CORE_CLK_EN](#control--core_clk_en) | +| 3:1 | | | Reserved | +| 0 | rw | 0x0 | [LOW_POWER_HINT](#control--low_power_hint) | + +### CONTROL . MAIN_PD_N +Active low, main power domain power down + +| Value | Name | Description | +|:--------|:-----------|:----------------------------------------------------------| +| 0x0 | Power down | Main power domain is powered down during low power state. | +| 0x1 | Power up | Main power domain is kept powered during low power state | + + +### CONTROL . IO_CLK_EN +IO clock enable during low power state + +| Value | Name | Description | +|:--------|:---------|:-----------------------------------------| +| 0x0 | Disabled | IO clock disabled during low power state | +| 0x1 | Enabled | IO clock enabled during low power state | + + +### CONTROL . CORE_CLK_EN +Core clock enable during low power state + +| Value | Name | Description | +|:--------|:---------|:-------------------------------------------| +| 0x0 | Disabled | Core clock disabled during low power state | +| 0x1 | Enabled | Core clock enabled during low power state | + + +### CONTROL . LOW_POWER_HINT +The low power hint to power manager. +The hint is an indication for how the manager should treat the next WFI. +Once the power manager begins a low power transition, or if a valid reset request is registered, +this bit is automatically cleared by HW. + +| Value | Name | Description | +|:--------|:----------|:----------------------------------------| +| 0x0 | None | No low power intent | +| 0x1 | Low Power | Next WFI should trigger low power entry | + + +## CFG_CDC_SYNC +The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the +fast clock domain but used in the slow clock domain. + +The configuration are not propagated across the clock boundary until this +register is triggered and read. See fields below for more details +- Offset: `0x18` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "SYNC", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------| +| 31:1 | | | Reserved | +| 0 | rw | 0x0 | [SYNC](#cfg_cdc_sync--sync) | + +### CFG_CDC_SYNC . SYNC +Configuration sync. When this bit is written to 1, a sync pulse is generated. When +the sync completes, this bit then self clears. + +Software should write this bit to 1, wait for it to clear, before assuming the slow clock +domain has accepted the programmed values. + +## WAKEUP_EN_REGWEN +Configuration enable for wakeup_en register +- Offset: `0x1c` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, WAKEUP_EN register can be configured. When 0, WAKEUP_EN register cannot be configured. | + +## WAKEUP_EN +Bit mask for enabled wakeups +- Offset: `0x20` +- Reset default: `0x0` +- Reset mask: `0xf` +- Register enable: [`WAKEUP_EN_REGWEN`](#wakeup_en_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3 | rw | 0x0 | EN_3 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 2 | rw | 0x0 | EN_2 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | +| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. | + +## WAKE_STATUS +A read only register of all current wake requests post enable mask +- Offset: `0x24` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_3", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------| +| 31:4 | | | | Reserved | +| 3 | ro | 0x0 | VAL_3 | Current value of wake requests | +| 2 | ro | 0x0 | VAL_2 | Current value of wake requests | +| 1 | ro | 0x0 | VAL_1 | Current value of wake requests | +| 0 | ro | 0x0 | VAL_0 | Current value of wake requests | + +## RESET_EN_REGWEN +Configuration enable for reset_en register +- Offset: `0x28` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, RESET_EN register can be configured. When 0, RESET_EN register cannot be configured. | + +## RESET_EN +Bit mask for enabled reset requests +- Offset: `0x2c` +- Reset default: `0x0` +- Reset mask: `0x3` +- Register enable: [`RESET_EN_REGWEN`](#reset_en_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. | +| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. | + +## RESET_STATUS +A read only register of all current reset requests post enable mask +- Offset: `0x30` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "VAL_0", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VAL_1", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------| +| 31:2 | | | | Reserved | +| 1 | ro | 0x0 | VAL_1 | Current value of reset request | +| 0 | ro | 0x0 | VAL_0 | Current value of reset request | + +## ESCALATE_RESET_STATUS +A read only register of escalation reset request +- Offset: `0x34` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | ro | 0x0 | VAL | When 1, an escalation reset has been seen. When 0, there is no escalation reset. | + +## WAKE_INFO_CAPTURE_DIS +Indicates which functions caused the chip to wakeup +- Offset: `0x38` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | VAL | When written to 1, this actively suppresses the wakeup info capture. When written to 0, wakeup info capture timing is controlled by HW. | + +## WAKE_INFO +Indicates which functions caused the chip to wakeup. +The wake info recording begins whenever the device begins a valid low power entry. + +This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. +This means it is possible to capture multiple wakeup reasons. +- Offset: `0x3c` +- Reset default: `0x0` +- Reset mask: `0x3f` + +### Fields + +```wavejson +{"reg": [{"name": "REASONS", "bits": 4, "attr": ["rw1c"], "rotate": -90}, {"name": "FALL_THROUGH", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ABORT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 140}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:-----------------------------------------| +| 31:6 | | | Reserved | +| 5 | rw1c | 0x0 | [ABORT](#wake_info--abort) | +| 4 | rw1c | 0x0 | [FALL_THROUGH](#wake_info--fall_through) | +| 3:0 | rw1c | 0x0 | [REASONS](#wake_info--reasons) | + +### WAKE_INFO . ABORT +The abort wakeup reason indicates that despite setting a WFI and providing a low power +hint, an active flash / lifecycle / otp transaction was ongoing when the power controller +attempted to initiate low power entry. + +The power manager detects this condition, halts low power entry and reports as a wakeup reason + +### WAKE_INFO . FALL_THROUGH +The fall through wakeup reason indicates that despite setting a WFI and providing a low power +hint, an interrupt arrived at just the right time to break the executing core out of WFI. + +The power manager detects this condition, halts low power entry and reports as a wakeup reason + +### WAKE_INFO . REASONS +Various peripheral wake reasons + +## FAULT_STATUS +A read only register that shows the existing faults +- Offset: `0x40` +- Reset default: `0x0` +- Reset mask: `0x7` + +### Fields + +```wavejson +{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ESC_TIMEOUT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_PD_GLITCH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------------|:----------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2 | ro | 0x0 | MAIN_PD_GLITCH | When 1, unexpected power glitch was observed on main PD. | +| 1 | ro | 0x0 | ESC_TIMEOUT | When 1, an escalation clock / reset timeout has occurred. | +| 0 | ro | 0x0 | REG_INTG_ERR | When 1, an integrity error has occurred. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/theory_of_operation.md b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/theory_of_operation.md new file mode 100644 index 00000000000..d3cf4d67558 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/doc/theory_of_operation.md @@ -0,0 +1,306 @@ +# Theory of Operation + +The power manager performs the following functions: +- Turn on/off power domain(s). +- Control root resets with the reset manager. +- Control root clock enables with AST and clock manager. +- Sequence various power up activities such as OTP sensing, life cycle initiation and releasing software to execute. + + +## Block Diagram + +See the below high level block diagram that illustrates the connections between the power manager and various system components. +Blocks outlined with a solid magenta line are always on; while blocks outlined with a dashed magenta line are a mix of components that are and those that are not. + +![Power Manager Connectivity Diagram](../doc/pwrmgr_connectivity.svg) + +## Overall Sequencing + +The power manager contains two state machines. +One operates on the always-on slow clock (this clock is always running and usually measured in KHz) and is responsible for turning faster clocks on and off and managing the power domains. +The other operates on a normal fixed clock (usually measured in MHz) and is responsible for everything else in the power sequence. + +The following diagram breaks down the general functionality of both. +The state machines are colored based on their clock domains. +The green state machine is clocked by the normal fixed domain, while the orange state machine is clocked by the slow domain. +Specific request / acknowledge signals are also highlighted in this color scheme to show where the two state machines communicate. + +![Power Manager FSMs](../doc/pwrmgr_fsms.svg) + + +Note, most of the states are transitional states, and only the following state combinations are resting states. + + +* Slow FSM `Idle` and fast FSM `Active` +* Slow FSM `Low Power` and fast FSM `Low Power` + +The slow FSM `Low Power` and fast FSM `Active` states specifically are concepts useful when examining [reset handling](#reset-request-handling). + + +## Slow Clock Domain FSM + +The slow clock domain FSM (referred to as the slow FSM from here on) resets to the Reset state. +This state is released by `por_rst_n`, which is supplied from the reset controller. +The `por_rst_n` signal is released when the reset controller detects the root power domains (`vcaon_pok` from AST) of the system are ready. +Please see the [ast](../../../ip/ast/README.md) for more details. + +The slow FSM requests the AST to power up the main domain and high speed clocks. +Once those steps are done, it requests the [fast FSM](#fast-clock-domain-fsm) to begin operation. +The slow FSM also handles power isolation controls as part of this process. + +Once the fast FSM acknowledges the power-up completion, the slow FSM transitions to `Idle` and waits for a power down request. +When a power down request is received, the slow FSM turns off AST clocks and power as directed by software configuration. +This means the clocks and power are not always turned off, but are rather controlled by software configurations in [`CONTROL`](registers.md#control) prior to low power entry . +Once these steps are complete, the slow FSM transitions to a low power state and awaits a wake request, which can come either as an actual wakeup, or a reset event (for example always on watchdog expiration). + +#### Sparse FSM + +Since the slow FSM is sparsely encoded, it is possible for the FSM to end up in an undefined state if attacked. +When this occurs, the slow FSM sends an `invalid` indication to the fast FSM and forcibly powers off and clamps everything. + +The clocks are kept on however to allow the fast FSM to operate if it is able to receive the `invalid` indication. +The slow FSM does not recover from this state until the system is reset by POR. + +Unlike [escalation resets](#escalation-reset-request), the system does not self reset. +Instead the system goes into a terminal non-responsive state where a user or host must directly intervene by toggling the power or asserting an external reset input. + +## Fast Clock Domain FSM + +The fast clock domain FSM (referred to as fast FSM from here on) resets to `Low Power` state and waits for a power-up request from the slow FSM. + +Once received, the fast FSM sequences the initialization of various units before the system is put in active state. +Depending on the system configuration some units may not be present and the sequence skips over. +This describes the default sequence assuming all the units are present. + +The fast FSM notifies the clock manager to enable all second level clock gating. +The fast FSM notifies the reset manager to release the life cycle reset stage, which allows the otp controller (OTP) to begin sensing. +Once OTP sensing completes, the life cycle controller is initialized. +The initialization of the life cycle controller puts the device into its allowed operating state. + +Once life cycle initialization is done, the fast FSM acknowledges the slow FSM rquest and initiates strap sampling. +Once strap sampling is complete, the sequence continues once the rom controller finishes its checks. +Note that `flash_ctrl` initialization is explicitly not done here, please see [sections below](#flash-handling) for more details. +The processor is allowed to start executing, the fast FSM transitions to `Active` state and waits for a software low power entry request. + +A low power request is initiated by software through a combination of WFI and software low power hint in [`CONTROL`](registers.md#control). +Specifically, this means if software issues only WFI, the power manager does not treat it as a power down request. +The notion of WFI is exported from the processor. +For Ibex, this is currently in the form of `core_sleeping_o`. + +In response to the low power entry request, the fast FSM disables all second level clock gating. +Before proceeding, the fast FSM explicitly separates the handling between a normal low power entry and a [reset request](#reset-request-handling). + +For low power entry, there are two cases, [fall through handling](#fall-through-handling) and [abort handling](#abort-handling). +If none of these exception cases are matched for low power entry, the fast FSM then asserts appropriate resets as necessary and requests the slow FSM to take over. + +For reset requests, fall through and aborts are not checked and the system simply resets directly. +Note in this scenario the slow FSM is not requested to take over. + +#### Sparse FSM + +Since the fast FSM is sparsely encoded, it is possible for the FSM to end up in an undefined state if attacked. +When this occurs, the fast FSM forcibly disables all clocks and holds the system in reset. + +The fast FSM does not recover from this state until the system is reset by POR. + + +### ROM Integrity Checks + +The power manager coordinates the [start up ROM check](../../../../ip/rom_ctrl/README.md#the-startup-rom-check) with `rom_ctrl`. + +After every reset, the power manager sends an indication to the `rom_ctrl` to begin performing integrity checks. +When the `rom_ctrl` checks are finished, a `done` and `good` indication are sent back to the power manager. + +If the device is in life cycle test states (`TEST_UNLOCKED` or `RMA`), the `good` signal is ignored and the ROM contents are always allowed to execute. + +If the device is not in one of the test states, the `good` signal is used to determine ROM execution. +If `good` is true, ROM execution is allowed. +If `good` is false, ROM execution is disallowed. + +### Fall Through Handling + +A low power entry fall through occurs when some condition occurs that immediately de-assert the entry conditions right after the software requests it. + +This can happen if right after software asserts WFI, an interrupt is shown to the processor, thus breaking it out of its currently stopped state. +Whether this type of fall through happens is highly dependent on how the system handles interrupts during low power entry - some systems may choose to completely silence any interrupt not related to wakeup, others may choose to leave them all enabled. +The fall through handle is specifically catered to the latter category. + +For a normal low power entry, the fast FSM first checks that the low power entry conditions are still true. +If the entry conditions are no longer true, the fast FSM "falls through" the entry handling and returns the system to active state, thus terminating the entry process. + +### Abort Handling + +If the entry conditions are still true, the fast FSM then checks there are no ongoing non-volatile activities from `otp_ctrl`, `lc_ctrl` and `flash_ctrl` (if they re part of the system). +If any module is active, the fast FSM "aborts" entry handling and returns the system to active state, thus terminating the entry process. + +## Reset Request Handling + +There are 4 reset requests in the system +- peripheral requested reset such as watchdog. +- reset manager's software requested reset, which is functionally very similar to a peripheral requested reset. +- power manager's internal reset request. +- Non-debug module reset. + +Flash brownout is handled separately and described in [flash handling section](#flash-handling) below. + +Note that the non-debug module reset is handled similarly to a peripheral requested reset, except that the non-debug module reset won't affect the debug module state and associated TAP muxing logic inside the pinmux. + +The power controller only observes reset requests in two states - the slow FSM `Low Power` state and the fast FSM `Active` state. +When a reset request is received during slow FSM `Low Power` state, the system begins its usual power up sequence even if a wakeup has not been received. + +When a reset request is received during fast FSM `Active` state, the fast FSM asserts resets and transitions back to its `Low Power` state. +The normal power-up process described [above](#fast-clock-domain-fsm) is then followed to release the resets. +Note in this case, the slow FSM is "not activated" and remains in its `Idle` state. + +### Power Manager Internal Reset Requests + +In additional to external requests, the power manager maintains 2 internal reset requests: +* Escalation reset request +* Main power domain unstable reset request + +#### Escalation Reset Request + +Alert escalation resets in general behave similarly to peripheral requested resets. +However, peripheral resets are always handled gracefully and follow the normal FSM transition. + +Alert escalations can happen at any time and do not always obey normal rules. +As a result, upon alert escalation, the power manager makes a best case effort to transition directly into reset handling. + +This may not always be possible if the escalation happens while the FSM is in an invalid state. +In this scenario, the pwrmgr keeps everything powered off and silenced and requests escalation handling if the system ever wakes up. + +#### Escalation Clock Timeout + +Under normal behavior, the power manager can receive escalation requests from the system and handle them [appropriately](#escalation-reset-request). +However, if the escalation clock or reset are non-functional for any reason, the escalation request would not be serviced. + +To mitigate this, the power manager actively checks for escalation interface clock/reset timeout. +This is done by a continuous request / acknowledge interface between the power manager's local clock/reset and the escalate network's clock/reset. + +If the request / acknowledge interface does not respond within 128 power manager clock cycles, the escalate domain is assumed to be off. +When this happens, the power manager creates a local escalation request that behaves identically to the global escalation request. + + +#### Main Power Unstable Reset Requests +If the main power ever becomes unstable (the power okay indication is low even though it is powered on), the power manager requests an internal reset. +This reset behaves similarly to the escalation reset and transitions directly into reset handling. + +Note that under normal low power conditions, the main power may be turned off. +As a result of this, the main power unstable checks are valid only during states that power should be on and stable. +This includes any state where power manager has requested the power to be turned on. + + +### Reset Requests Received During Other States + +All other states in the slow / fast FSM are considered transitional states. +Resets are not observed in other states because the system will always be transitioning towards one of the steady states (the system is in the process of powering down or powering up). +Once a steady state is reached, reset requests are then observed and processed. + +### Reset Recording + +There are two ways in which the device is reset: +- The reset requests mentioned in [reset handling](#reset-request-handling) +- Low power entry (`sleep_req` in the state diagram) + +The power manager handles only one of these at a time (see state diagrams). +This means if reset request and low power entry collide, the power manager will handle them on a first come first served basis. +When the handling of the first is completed, the power manager handles the second pending request if it is still present. + +This is done because low power resets and peripheral requested resets lead to different behaviors. +When the power manager commits to handling a specific request, it informs the reset manager why it has reset the processor. + +For example, assume a low power entry request arrives slightly ahead of reset requests. +The power manager will: +- Transition the system into low power state. +- Inform the reset manager to record "low power exit" as the reset reason. +- Once in low state, transition the system to `Active` state by using the reset request as a wakeup indicator. +- Inform the reset manager to also record the peripheral that requested reset. +- Once in `Active` state, reset the system and begin normal power-up routines again. + +If reset requests arrive slightly ahead of a low power entry request, then power manager will: +- Reset the system and begin normal power-up routines. +- Inform the reset manager to record the peripheral that requested reset. +- Once in `Active` state, if the low power entry request is still present, transition to low power state. + - Inform the reset manager to also record "low power exit" as the reset reason. +- If the low power entry request was wiped out by reset, the system then stays in `Active` state and awaits software instructions. + +Ultimately when control is returned to software, it may see two reset reasons and must handle them accordingly. + + +## Wakeup Recording + +Similar to [reset handling](#reset-request-handling), wakeup signals are only observed during slow FSM `Low Power`; however their recording is continuous until explicitly disabled by software. + +Wakeup recording begins when the fast FSM transitions out of `Active` state and continues until explicitly disabled by software. +This ensures wakeup events are not missed until software has set up the appropriate peripherals. +Recording needs clocks to be active, and during low power they are usually not. +For this reason, it is important for wakeups to be level and remain active until software clears them. + +The software is also able to enable recording during `Active` state if it chooses to do so. The recording enables are OR’d together for hardware purposes. + + +## Flash Handling +For the section below, flash macro refers to the proprietary flash storage supplied by a vendor. +`flash_ctrl`, on the other hand, refers to the open source controller that manages access to the flash macro. + +### Power-Up Handling + +The [AST](../../../ip/ast/README.md) automatically takes the flash macro out of power down state as part of the power manager's power up request. + +Once flash macro is powered up and ready, an indication is sent to the `flash_ctrl`. + +Once the boot ROM is allowed to execute, it is expected to further initialize the `flash_ctrl` and flash macro prior to using it. +This involves the following steps: + +* Poll `flash_ctrl` register to ensure flash macro has powered up and completed internal initialization. +* Initialize `flash_ctrl` seed reading and scrambling. + +### Power-Down Handling + +Before the device enters low power, the pwrmgr first checks to ensure there are no ongoing transactions to the flash macro. +When the device enters deep sleep, the flash macro is automatically put into power down mode by the AST. +The AST places the flash macro into power down through direct signaling between AST and flash macro, the pwrmgr is not directly involved. + +When the device exits low power state, it is the responsibility of the boot ROM to poll for flash macro and `flash_ctrl` power-up complete similar to the above section. + +### Flash Brownout Handling + +When the external supply of the device dips below a certain threshold during a non-volatile flash macro operation (program or erase), the flash macro requires the operation to terminate in a pre-defined manner. +This sequence will be exclusively handled by the AST. + +The power manager is unaware of the difference between POR and flash brownout. +Because of this, the software also cannot distinguish between these two reset causes. + + +## Supported Low Power Modes + +This section details the various low power modes supported by OpenTitan. + + +### Deep Sleep or Standby + +This is the lowest power mode of the device (outside of full power down or device held in reset). +During this state: + +* All clocks other than the always-on slow clock are turned off at the source. +* All non-always-on digital domains are powered off. +* I/O power domains may or may not be off. + * The state of the IO power domain has no impact on the digital core’s power budget, e.g. the IO power being off does not cause the accompanying digital logic in pads or elsewhere to leak more. + + +### Normal Sleep + +This is a fast low power mode of the device that trades-off power consumption for resume latency. +During this state: + +* All clocks other than the KHz slow clock are turned off at the source. +* All power domains are kept on for fast resume. +* Sensor countermeasures can be opportunistically on. +* I/O power domains may or may not be off. + * The state of the IO power domain has no impact on the digital core’s power budget, e.g. the IO power being off does not cause the accompanying digital logic in pads or elsewhere to leak more. + +## Debug + +When performing TAP debug, it is important for the debugging software to prevent the system from going to low power. +If the system enters low power during live debug, the debug session will be broken. +There is currently no standardized way to do this, so it is up to the debugging agent to perform the correct steps. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/README.md new file mode 100644 index 00000000000..75036164de8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/README.md @@ -0,0 +1,253 @@ +# PWRMGR DV document + +## Goals +* **DV** + * Verify all PWRMGR IP features by running dynamic simulations with a SV/UVM based testbench. + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules. +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench. + +## Current status +* [Design & verification stage](../doc/checklist.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/latest/report.html) + +## Design features +For detailed information on PWRMGR design features, please see the [PWRMGR HWIP technical specification](../README.md). + +## Testbench architecture +PWRMGR testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +### Block diagram +![Block diagram](./doc/tb.svg) + +### Top level testbench +Top level testbench is located at [`hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tb.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tb.sv). +It instantiates the PWRMGR DUT module [`hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr.sv). +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* PWRMGR interface [`hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv). +* Interrupts ([`pins_if`](../../../../dv/sv/common_ifs/README.md)) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + +### Common DV utility components +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +### Global types & methods +All common types and methods defined at the package level can be found in +[`pwrmgr_env_pkg`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv). +Some of them in use are: +```systemverilog + typedef enum int { + WakeupSysrst, + WakeupDbgCable, + WakeupPin, + WakeupUsb, + WakeupAonTimer, + WakeupSensorCtrl + } wakeup_e; + + typedef struct packed { + logic main_pd_n; + logic io_clk_en; + logic main_clk_en; + } control_enables_t; + + typedef bit [pwrmgr_reg_pkg::NumWkups-1:0] wakeups_t; + typedef bit [pwrmgr_reg_pkg::NumRstReqs-1:0] resets_t; + + // This is used to send all resets to rstmgr. + typedef bit [pwrmgr_pkg::HwResetWidth-1:0] resets_out_t; +``` +### TL_agent +PWRMGR testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md) which provides the ability to drive and independently monitor random traffic via TL host interface into PWRMGR device. + +### UVM RAL Model +The PWRMGR RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md). + +### Stimulus strategy +The sequences are closely related to the testplan's testpoints. +Testpoints and coverage are described in more detail in the [testplan](#testplan). +All test sequences reside in [`hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib), and extend `pwrmgr_base_vseq`. +The `pwrmgr_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point. +It provides commonly used handles, variables, functions and tasks used by the test sequences. +Some of the most commonly used tasks and functions are as follows: +* task `wait_for_rom_and_active`: + Randomize rom_ctrls and waits for the fast fsm to be active or inactive, indicated by whether the `fetch_en_o` output become On or Off respectively. + We mostly call this expecting it to be active before the tests can start, since any CSR accesses require the CPU to be running. + The rom_ctrl inputs are randomized repeatedly, but in such a way that they end up allowing transitions to active. +* task `wait_for_csr_to_propagate_to_slow_domain`: + Waits for `cfg_cdc_sync` CSR to be clear, indicating the CDC to the slow clock has completed. +* task `wait_for_reset_cause`: + Waits for the `pwr_rst_req.reset_cause` output to match an expected cause. +* task `check_wait_info`: + Checks the wake_info CSR matches expectations. +* task `check_reset_status`: + Checks the reset_status CSR matches expectations. +* task `check_and_clear_interrupt`: + Checks the interrupt enable, status, and output pin. + +In addition, the base sequence provides two tasks that provide expected inputs based on the pwrmgr outputs. +In the absence of these inputs the pwrmgr will be stuck waiting forever. +Being based on outputs means the inputs are in accordance to the implicit protocol. +The tasks in question are: +* task `slow_responder`: + Handles required input changes from AST for the slow state machine. + For the various `_en` outputs it changes the `_val` as required, for the non-aon clocks from the ast. +* task `fast_responder`: + Handles input changes for the fast state machine. + * Completes the handshake with rstmgr for lc and sys resets: some random cycles after an output reset is requested the corresponding reset src input must go low. + * Completes the handshake with clkmgr: the various `_status` inputs need to match the corresponding `_ip_clk_en` output after some cycles, for the non-aon clocks from the ast. + * Completes the handshake with lc and otp: both *_done inputs must match the corresponding *_init outputs after some cycles. + +These tasks are started by the parent sequence's `pre_start` task, and terminated gracefully in the parent sequence's `post_start` task. +### Test sequences +The test sequences besides the base are as follows: +* `pwrmgr_smoke_vseq` tests the pwrmgr through POR, entry and exit from software initiated low power and reset. +* `pwrmgr_wakeup_vseq` checks the transitions to low power and the wakeup settings. + It randomizes wakeup inputs, wakeup enables, the wakeup info capture enable, and the interrupt enable. +* `pwrmgr_aborted_low_power_vseq` creates scenarios that lead to aborting a low power transition. + The abort can be due to the processor waking up very soon, or otp, lc, or flash being busy. +* `pwrmgr_reset_vseq` checks the pwrmgr response to conditional resets and reset enables, and unconditional escalation and main power glitch resets. +* `pwrmgr_wakeup_reset_vseq` aligns reset and wakeup from low power. +* `pwrmgr_lowpower_wakeup_race_vseq` aligns a wakeup event coming in proximity to low power entry. + Notice the wakeup is not expected to impact low power entry, since it is not sampled at this time. + +### Functional coverage +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* `wakeup_ctrl_cg` covers wakeup and capture control. +* `wakeup_intr_cg` covers control of the interrupt due to a wakeup. +* `control_cg` covers clock controls. +* `hw_reset_0_cg` covers external reset via `rstreqs_i[0]`. +* `hw_reset_1_cg` covers external reset via `rstreqs_i[1]`. +* `rstmgr_sw_reset_cg` covers software initiated resets via rstmgr CSR. +* `main_power_reset_cg` covers resets due to a main power glitch. +* `esc_reset_cg` covers resets due to an incoming escalation. +* `reset_wakeup_distance_cg` covers the distance in clock cycles between a wakeup and a reset request. + +More details about these sequences and covergroups can be found at [testplan](#testplan). + +### Self-checking strategy +Many of the checks are performed via SVA, and are enabled for all test sequences. +Refer to the [assertions](#assertions) section below for details. + +#### Scoreboard +The `pwrmgr_scoreboard` is primarily used for end to end checking. + +Many inputs must have specific transitions to prevent the pwrmgr fsms from wait forever. +When possible the transitions are triggered by pwrmgr output changes. +These are described according to the unit that originates or is the recipient of the ports. +See also the test plan for specific ways these are driven to trigger different testpoints. + +##### AST +- Output `slow_clk_en` is always on. +- Input `slow_clk_val` is unused. +- Outputs `core_clk_en`, `io_clk_en`, and `usb_clk_en` reset low, and go high prior to the slow fsm requesting the fast fsm to wakeup. + Notice the usb clock can be programmed to stay low on wakeup via the `control` CSR. + These clock enables are cleared on reset, and should match their corresponding enables in the `control` CSR on low power transitions. + These clock enables are checked via SVAs in [`hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv). + When slow fsm transitions to `SlowPwrStateReqPwrUp` the clock enables should be on (except usb should match `control.usb_clk_en_active`). + When slow fsm transitions to `SlowPwrStatePwrClampOn` the clock enables should match their bits in the `control` CSR. +- Inputs `core_clk_val`, `io_clk_val`, and `usb_clk_val` track the corresponding enables. + They are driven by `slow_responder`, which turn them off when their enables go off, and turn them back on a few random slow clock cycles after their enables go on. + Slow fsm waits for them to go high prior to requesting fast fsm wakeup. + Lack of a high transition when needed is detected via timeout. + Such timeout would be due to the corresponding enables being set incorrectly. + These inputs are checked via SVAs in [`hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv). +- Output `main_pd_n` should go high when slow fsm transitions to `SlowPwrStateMainPowerOn`, and should match `control.main_pd_n` CSR when slow fsm transitions to `SlowPwrStateMainPowerOff`. +- Input `main_pok` should turn on for the slow fsm to start power up sequence. + This is also driven by `slow_responder`, which turn this off in response to `main_pd_n` going low, and turn it back on after a few random slow clock cycles from `main_pd_n` going high. + Lack of a high transition causes a timeout, and would point to `main_pd_n` being set incorrectly. +- Output transitions of `pwr_clamp_env` must always precede transitions of + `pwr_clamp` output. + Output transitions of `pwr_clamp` to active must always precede transitions + of `main_pd_n` output to active. + Output transitions of `pwr_clamp` to inactive must always follow transitions + of `main_pd_n` output to inactive. + +##### RSTMGR +- Output `rst_lc_req` resets to 1, also set on reset transition, and on low power transitions that turn off main clock. + Cleared early on during the steps to fast fsm active. +- Input `rst_lc_src_n` go low in response to `rst_lc_req` high, go high when `rst_lc_req` clears (and lc is reset). + Driven by `fast_responder` in response to `rst_lc_req`, waiting a few random cycles prior to transitions. + Fast fsm waits for it to go low before deactivating, and for it to go high before activating. + Checked implicitly by lack of timeout: a timeout would be due to `rst_lc_req` being set incorrectly, and by SVA as described below. +- Output `rst_sys_req` resets to 1, also set to on reset, and on low power transitions that turn off main clock. + Cleared right before the fast fsm goes active. +- Input `rst_sys_src_n` go low in response to `rst_sys_req` high. + Transitions go high when `rst_sysd_req` clears (and lc is reset). + Fast fsm waits for it to go low before deactivating. + Also driver by `fast_responder`. + Checked implicitly by lack of timeout, and by SVA. +- Output `rstreqs` correspond to the enabled pwrmgr rstreqs inputs plus main power glitch, escalation reset, and software reset request from RSTMGR. + Checked in scoreboard and SVA. +- Output `reset_cause` indicates a reset is due to low power entry or a reset request. + Checked in scoreboard. + +##### CLKMGR +- Outputs `pwr_clk_o._ip_clk_en` reset low, are driven high by fast fsm when going active, and driven low when going inactive. + The `` correspond to `io`, `main`, and `usb`. +- Inputs `pwr_clk_i._status` are expected to track `pwr_clk_o._ip_clk_en`. + Fast fsm waits for them going high prior to going active, and going low prior to deactivating. + These are controlled by the `control` CSR. + Driven by `fast_responder`, which turns them off when `_ip_clk_en` goes low, and turns them back on a few random cycles after `_ip_clk_en` goes high. + Checked by lack of a timeout: such timeout would be due to `ip_clk_en` being set incorrectly. + Also checked by SVA. + +##### OTP +- Output `otp_init` resets low, goes high when the fast fsm is going active, and low after the `otp_done` input goes high. +- Input `otp_done` is driven by `fast_responder`. + It is initialized low, and goes high some random cycles after `otp_init` goes high. + The sequencer will timeout if `otp_init` is not driven high. +- Input `otp_idle` normally set high, but is set low by the `pwrmgr_aborted_low_power_vseq` sequence. + +##### LC +The pins connecting to LC behave pretty much the same way as those to OTP. + +##### FLASH +- Input `flash_idle` is handled much like `lc_idle` and `otp_idle`. + +##### CPU +- Input `core_sleeping` is driven by sequences. + It is driven low to enable a transition to low power. + After the transition is under way it is a don't care. + The `pwrmgr_aborted_low_power_vseq` sequence sets it carefully to abort a low power entry soon after the attempt because the processor wakes up. + +##### Wakeups and Resets +There are a number of wakeup and reset requests. +They are driven by sequences as they need to. + +#### Assertions +The [`hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv) module binds a few modules containing assertions to the IP as follows: +* TLUL assertions: the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) ensures TileLink interface protocol compliance. +* Clock enables assertions: + The `pwrmgr_clock_enables_sva_if` module contains assertions checking that the various clk_en outputs correspond to the settings in the `control` CSR. +* CLKMGR clk_en to status handshake assertions: + The `clkmgr_pwrmgr_sva_if` contains assertions checking the various `_status` inputs track the corresponding `_ip_clk_en` outputs. +* AST input/output handshake assertions: + The `pwrmgr_ast_sva_if` module contains assertions checking that the inputs from the AST respond to the pwrmgr outputs. +* RSTMGR input/output handshake assertions: + The `pwrmgr_rstmgr_sva_if` module contains assertions checking the following: + * The `rst_lc_src_n` input from RSTMGR respond to the `rst_lc_req` pwrmgr output. + * The `rst_sys_src_n` input from RSTMGR respond to the `rst_sys_req` pwrmgr output. + * The different `pwr_rst_o.rstreqs` output bits track the corresponding reset causes. + These include hardware, power glitch, escalation, and software resets. + +In addition, the RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. + +## Building and running tests +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_smoke +``` + +## Testplan +[Testplan](../data/pwrmgr_testplan.hjson) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_bind.sv new file mode 100644 index 00000000000..2df5f893d62 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_bind.sv @@ -0,0 +1,53 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// Power manager coverage bindings for multi bus input +module pwrmgr_cov_bind; + + bind pwrmgr cip_lc_tx_cov_if u_lc_dft_en_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_dft_en_i) + ); + + bind pwrmgr cip_lc_tx_cov_if u_lc_hw_debug_en_mubi_cov_if ( + .rst_ni (rst_ni), + .val (lc_hw_debug_en_i) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl0_good_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i[0].done) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl0_done_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i[0].good) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl1_good_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i[1].done) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl1_done_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i[1].good) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl2_good_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i[2].done) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_rom_ctrl2_done_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (rom_ctrl_i[2].good) + ); + + bind pwrmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_sw_rst_req_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (sw_rst_req_i) + ); +endmodule // pwrmgr_cov_bind diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el new file mode 100644 index 00000000000..6e3e974019c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/cov/pwrmgr_cov_manual_excl.el @@ -0,0 +1,34 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//================================================== +// This file contains the Excluded objects +// Generated By User: jdonjdon +// Format Version: 2 +// Date: Sun Sep 25 22:09:48 2022 +// ExclMode: default +//================================================== +CHECKSUM: "2301929872 963630968" +INSTANCE: tb.dut.u_esc_rx.u_prim_count +ANNOTATION: "[UNSUPPORTED] Ports are assigned constant by RTL." +Toggle step_i "net step_i[21:0]" +Toggle set_cnt_i "net set_cnt_i[21:0]" +CHECKSUM: "3681358461" +INSTANCE: tb.dut.u_esc_timeout.u_ref_timeout +ANNOTATION: "[UNR] Input req_chk_i is tied to constant 0 and src_req_i to constant 1" +Assert SyncReqAckHoldReq "assertion" +CHECKSUM: "2699797328" +INSTANCE: tb.dut.pwrmgr_ast_sva_if +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert CoreClkGlitchToEnOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert UsbClkGlitchToValOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert UsbClkGlitchToEnOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert IoClkGlitchToValOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert IoClkGlitchToEnOff_A "assertion" +ANNOTATION: "[UNR] por_d0_ni input is tied to constant 1" +Assert CoreClkGlitchToValOff_A "assertion" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/cov/pwrmgr_tgl_excl.cfg b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/cov/pwrmgr_tgl_excl.cfg new file mode 100644 index 00000000000..9d1f7fd2c62 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/cov/pwrmgr_tgl_excl.cfg @@ -0,0 +1,9 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//====================================================================== +// This file contains outputs of pwrmgr tied to constants. +//====================================================================== + +-module_node pwrmgr pwr_ast_o.slow_clk_en diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/doc/tb.svg b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/doc/tb.svg new file mode 100644 index 00000000000..285ef6948e4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core new file mode 100644 index 00000000000..27ac92042c4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env.core @@ -0,0 +1,58 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:pwrmgr_env:0.1 +description: "PWRMGR DV UVM environment" +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:ip:rv_core_ibex_pkg + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg + - lowrisc:darjeeling_no_ibex_constants:top_pkg + files: + - pwrmgr_env_pkg.sv + - pwrmgr_env_cfg.sv: {is_include_file: true} + - pwrmgr_env_cov.sv: {is_include_file: true} + - pwrmgr_if.sv + - pwrmgr_virtual_sequencer.sv: {is_include_file: true} + - pwrmgr_scoreboard.sv: {is_include_file: true} + - pwrmgr_env.sv: {is_include_file: true} + - seq_lib/pwrmgr_vseq_list.sv: {is_include_file: true} + - seq_lib/pwrmgr_base_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_aborted_low_power_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_common_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_smoke_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_wakeup_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_wakeup_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_sw_reset_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_global_esc_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_escalation_timeout_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_glitch_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_reset_invalid_vseq.sv: {is_include_file: true} + - seq_lib/pwrmgr_lowpower_invalid_vseq.sv: {is_include_file: true} + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: pwrmgr + ip_hjson: ../../data/pwrmgr.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env.sv new file mode 100644 index 00000000000..96646b5f2a9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env.sv @@ -0,0 +1,57 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_env extends cip_base_env #( + .CFG_T (pwrmgr_env_cfg), + .COV_T (pwrmgr_env_cov), + .VIRTUAL_SEQUENCER_T(pwrmgr_virtual_sequencer), + .SCOREBOARD_T (pwrmgr_scoreboard) +); + `uvm_component_utils(pwrmgr_env) + + alert_esc_agent m_esc_agent; + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "slow_clk_rst_vif", cfg.slow_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get slow_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "esc_clk_rst_vif", cfg.esc_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get esc_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "lc_clk_rst_vif", cfg.lc_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get lc_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_if)::get(this, "", "pwrmgr_vif", cfg.pwrmgr_vif)) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_clock_enables_sva_if)::get( + this, "", "pwrmgr_clock_enables_sva_vif", cfg.pwrmgr_clock_enables_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_clock_enables_sva_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::get( + this, "", "pwrmgr_rstmgr_sva_vif", cfg.pwrmgr_rstmgr_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_rstmgr_sva_vif from uvm_config_db") + end + + m_esc_agent = alert_esc_agent::type_id::create("m_esc_agent", this); + uvm_config_db#(alert_esc_agent_cfg)::set(this, "m_esc_agent", "cfg", cfg.m_esc_agent_cfg); + cfg.m_esc_agent_cfg.en_cov = cfg.en_cov; + + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cfg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cfg.sv new file mode 100644 index 00000000000..113b8b6ea03 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cfg.sv @@ -0,0 +1,52 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_env_cfg extends cip_base_env_cfg #( + .RAL_T(pwrmgr_reg_block) +); + + // disable fault csr read check from scoreboard + bit disable_csr_rd_chk = 0; + + // Invalid state test. Used to disable interrupt check. + bit invalid_st_test = 0; + + // ext component cfgs + alert_esc_agent_cfg m_esc_agent_cfg; + + `uvm_object_utils_begin(pwrmgr_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + // ext interfaces + virtual clk_rst_if esc_clk_rst_vif; + virtual clk_rst_if lc_clk_rst_vif; + virtual clk_rst_if slow_clk_rst_vif; + virtual pwrmgr_if pwrmgr_vif; + virtual pwrmgr_clock_enables_sva_if pwrmgr_clock_enables_sva_vif; + virtual pwrmgr_rstmgr_sva_if #(.PowerDomains(pwrmgr_pkg::PowerDomains)) pwrmgr_rstmgr_sva_vif; + + // The run_phase object, to deal with objections. + uvm_phase run_phase; + + virtual function void initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = pwrmgr_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + num_interrupts = ral.intr_state.get_n_used_bits(); + `ASSERT_I(NumInstrMatch_A, num_interrupts == NUM_INTERRUPTS) + `uvm_info(`gfn, $sformatf("num_interrupts = %0d", num_interrupts), UVM_MEDIUM) + + // pwrmgr_tl_intg_err test uses default alert name "fata_fault" + // and it requires following field to be '1' + tl_intg_alert_fields[ral.fault_status.reg_intg_err] = 1; + m_tl_agent_cfg.max_outstanding_req = 1; + m_esc_agent_cfg = alert_esc_agent_cfg::type_id::create("m_esc_agent_cfg"); + `DV_CHECK_RANDOMIZE_FATAL(m_esc_agent_cfg) + m_esc_agent_cfg.is_alert = 0; + // Disable escalation ping coverage. + m_esc_agent_cfg.en_ping_cov = 0; + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cov.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cov.sv new file mode 100644 index 00000000000..63ab9f40282 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cov.sv @@ -0,0 +1,213 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergroups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here. + * Covergroups may also be wrapped inside helper classes if needed. + */ + +`include "cip_macros.svh" + +// Wrapper class for wakeup control covergroup. +class pwrmgr_wakeup_ctrl_cg_wrap; + // This covers enable, capture, and status of wakeups. + covergroup wakeup_ctrl_cg(string name) with function sample (bit enable, bit capture, bit wakeup); + option.name = name; + option.per_instance = 1; + + enable_cp: coverpoint enable; + capture_cp: coverpoint capture; + wakeup_cp: coverpoint wakeup; + + wakeup_cross: cross enable_cp, capture_cp, wakeup_cp; + endgroup + + function new(string name); + wakeup_ctrl_cg = new(name); + endfunction + + function void sample (bit enable, bit capture, bit wakeup); + wakeup_ctrl_cg.sample(enable, capture, wakeup); + endfunction +endclass + +// Wrapper class for wakeup interrupt covergroup. +class pwrmgr_wakeup_intr_cg_wrap; + // This covers interrupts generated by wakeups. + covergroup wakeup_intr_cg( + string name + ) with function sample ( + bit wakeup, bit enable, bit status, bit interrupt + ); + option.name = name; + option.per_instance = 1; + + enable_cp: coverpoint enable; + status_cp: coverpoint status; + wakeup_cp: coverpoint wakeup; + interrupt_cp: coverpoint interrupt; + + interrupt_cross: cross enable_cp, status_cp, wakeup_cp, interrupt_cp{ + // An interrupt cannot happen unless wake_status is on. + ignore_bins no_wakeup = interrupt_cross with (!wakeup_cp && interrupt_cp); + // An interrupt cannot happen unless it is enabled. + ignore_bins disable_pin = interrupt_cross with (!enable_cp && interrupt_cp); + // An interrupt cannot happen if intr_status is off. + ignore_bins no_status_pin = interrupt_cross with (!status_cp && interrupt_cp); + // If all preconditions are satisfied there must be an interrupt. + ignore_bins missing_int = interrupt_cross with (enable_cp && status_cp && wakeup_cp && + !interrupt_cp); + } + endgroup + + function new(string name); + wakeup_intr_cg = new(name); + endfunction + + function void sample (bit enable, bit status, bit wakeup, bit interrupt); + wakeup_intr_cg.sample(wakeup, enable, status, interrupt); + endfunction +endclass + +class pwrmgr_env_cov extends cip_base_env_cov #( + .CFG_T(pwrmgr_env_cfg) +); + `uvm_component_utils(pwrmgr_env_cov) + + // the base class provides the following handles for use: + // pwrmgr_env_cfg: cfg + + // covergroups + pwrmgr_wakeup_ctrl_cg_wrap wakeup_ctrl_cg_wrap[pwrmgr_reg_pkg::NumWkups]; + pwrmgr_wakeup_intr_cg_wrap wakeup_intr_cg_wrap[pwrmgr_reg_pkg::NumWkups]; + + // This collects coverage on the clock and power control functionality. + covergroup control_cg with function sample (control_enables_t control_enables, bit sleep); + main_cp: coverpoint control_enables.main_clk_en; + io_cp: coverpoint control_enables.io_clk_en; + main_pd_n_cp: coverpoint control_enables.main_pd_n; + sleep_cp: coverpoint sleep; + + control_cross: cross + main_cp, + io_cp, + main_pd_n_cp, sleep_cp; + endgroup + + covergroup hw_reset_0_cg with function sample (logic reset, logic enable, bit sleep); + reset_cp: coverpoint reset; + enable_cp: coverpoint enable; + sleep_cp: coverpoint sleep; + reset_cross: cross reset_cp, enable_cp, sleep_cp { + // Reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (reset_cp && sleep_cp); + } + endgroup + + covergroup hw_reset_1_cg with function sample (logic reset, logic enable, bit sleep); + reset_cp: coverpoint reset; + enable_cp: coverpoint enable; + sleep_cp: coverpoint sleep; + reset_cross: cross reset_cp, enable_cp, sleep_cp { + // Reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (reset_cp && sleep_cp); + } + endgroup + + // This reset cannot be generated in low power state since it is triggered by software. + covergroup rstmgr_sw_reset_cg with function sample (logic sw_reset); + sw_reset_cp: coverpoint sw_reset; + endgroup + + covergroup main_power_reset_cg with function sample (logic main_power_reset, bit sleep); + main_power_reset_cp: coverpoint main_power_reset; + sleep_cp: coverpoint sleep; + reset_cross: cross main_power_reset_cp, sleep_cp { + // Any reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (main_power_reset_cp && sleep_cp); + } + endgroup + + covergroup esc_reset_cg with function sample (logic esc_reset, bit sleep); + esc_reset_cp: coverpoint esc_reset; + sleep_cp: coverpoint sleep; + reset_cross: cross esc_reset_cp, sleep_cp { + // Any reset and sleep are mutually exclusive. + illegal_bins illegal = reset_cross with (esc_reset_cp && sleep_cp); + } + endgroup + + // This measures the number of cycles between the reset and wakeup. + // It is positive when reset happened after wakeup, and zero when they coincided in time. + covergroup reset_wakeup_distance_cg with function sample (int cycles); + cycles_cp: coverpoint cycles { + bins close[] = {[-4 : 4]}; + bins far = default; + } + endgroup + + // This covers the rom inputs that should prevent entering the active state. + covergroup rom_active_blockers_cg with function sample ( + logic [3:0] done_0, logic [3:0] good_0, + logic [3:0] done_1, logic [3:0] good_1, + logic [3:0] done_2, logic [3:0] good_2, + logic [3:0] dft, logic [3:0] debug + ); + done_0_cp: coverpoint done_0 { + `DV_MUBI4_CP_BINS + } + good_0_cp: coverpoint good_0 { + `DV_MUBI4_CP_BINS + } + done_1_cp: coverpoint done_1 { + `DV_MUBI4_CP_BINS + } + good_1_cp: coverpoint good_1 { + `DV_MUBI4_CP_BINS + } + done_2_cp: coverpoint done_2 { + `DV_MUBI4_CP_BINS + } + good_2_cp: coverpoint good_2 { + `DV_MUBI4_CP_BINS + } + dft_cp: coverpoint dft { + `DV_LC_TX_T_CP_BINS + } + debug_cp: coverpoint debug { + `DV_LC_TX_T_CP_BINS + } + blockers_cross: cross + done_0_cp, good_0_cp, + done_1_cp, good_1_cp, + done_2_cp, good_2_cp, + dft_cp, debug_cp; + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + foreach (wakeup_ctrl_cg_wrap[i]) begin + pwrmgr_env_pkg::wakeup_e wakeup = pwrmgr_env_pkg::wakeup_e'(i); + wakeup_ctrl_cg_wrap[i] = new({wakeup.name, "_ctrl_cg"}); + wakeup_intr_cg_wrap[i] = new({wakeup.name, "_intr_cg"}); + end + control_cg = new(); + hw_reset_0_cg = new(); + hw_reset_1_cg = new(); + rstmgr_sw_reset_cg = new(); + main_power_reset_cg = new(); + esc_reset_cg = new(); + reset_wakeup_distance_cg = new(); + rom_active_blockers_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv new file mode 100644 index 00000000000..04597c348c8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_env_pkg.sv @@ -0,0 +1,87 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package pwrmgr_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import pwrmgr_ral_pkg::*; + import alert_esc_agent_pkg::*; + import pwrmgr_pkg::PowerDomains; + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + import prim_mubi_pkg::MuBi4Width; + import sec_cm_pkg::*; + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter int NUM_INTERRUPTS = 1; + + // clk enable disable delay + parameter uint MAIN_CLK_DELAY_MIN = 15; + parameter uint MAIN_CLK_DELAY_MAX = 258; + parameter uint ESC_CLK_DELAY_MIN = 1; + parameter uint ESC_CLK_DELAY_MAX = 10; + + // alerts + parameter uint NUM_ALERTS = 1; + parameter string LIST_OF_ALERTS[NUM_ALERTS] = {"fatal_fault"}; + + // types + typedef enum int { + WakeupSysrst, + WakeupDbgCable, + WakeupPin, + WakeupUsb, + WakeupAonTimer, + WakeupSensorCtrl + } wakeup_e; + + typedef enum int { + PwrmgrMubiNone = 0, + PwrmgrMubiLcCtrl = 1, + PwrmgrMubiRomCtrl = 2 + } pwrmgr_mubi_e; + + typedef struct packed { + logic main_pd_n; + logic io_clk_en; + logic main_clk_en; + } control_enables_t; + + typedef bit [pwrmgr_reg_pkg::NumWkups-1:0] wakeups_t; + typedef bit [pwrmgr_reg_pkg::NumRstReqs-1:0] resets_t; + + // This is used to send all resets to rstmgr. + typedef bit [pwrmgr_pkg::HwResetWidth-1:0] resets_out_t; + + // need a short name to avoid 100 line cut off + parameter int MUBI4W = prim_mubi_pkg::MuBi4Width; + + // functions + + // variables + bit [NUM_INTERRUPTS-1:0] exp_intr; + wakeups_t exp_wakeup_reasons; + control_enables_t control_enables; + logic low_power_hint; + + // package sources + `include "pwrmgr_env_cfg.sv" + `include "pwrmgr_env_cov.sv" + `include "pwrmgr_virtual_sequencer.sv" + `include "pwrmgr_scoreboard.sv" + `include "pwrmgr_env.sv" + `include "pwrmgr_vseq_list.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv new file mode 100644 index 00000000000..2da8a98a233 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_if.sv @@ -0,0 +1,230 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// pwrmgr interface. +// +// Samples some internal signals to help coverage collection: +interface pwrmgr_if ( + input logic clk, + input logic rst_n, + input logic clk_slow, + input logic rst_slow_n +); + import uvm_pkg::*; + import pwrmgr_reg_pkg::NumWkups; + import pwrmgr_reg_pkg::NumRstReqs; + import pwrmgr_reg_pkg::NumRomInputs; + import pwrmgr_env_pkg::*; + + // Ports to the dut side. + + logic rst_main_n; + + pwrmgr_pkg::pwr_ast_req_t pwr_ast_req; + pwrmgr_pkg::pwr_ast_rsp_t pwr_ast_rsp; + + pwrmgr_pkg::pwr_rst_req_t pwr_rst_req; + pwrmgr_pkg::pwr_rst_rsp_t pwr_rst_rsp; + + pwrmgr_pkg::pwr_clk_req_t pwr_clk_req; + pwrmgr_pkg::pwr_clk_rsp_t pwr_clk_rsp; + + pwrmgr_pkg::pwr_otp_req_t pwr_otp_req; + pwrmgr_pkg::pwr_otp_rsp_t pwr_otp_rsp; + + lc_ctrl_pkg::pwr_lc_req_t pwr_lc_req; + lc_ctrl_pkg::pwr_lc_rsp_t pwr_lc_rsp; + + pwrmgr_pkg::pwr_flash_t pwr_flash; + + pwrmgr_pkg::pwrmgr_cpu_t cpu_i; + rv_core_ibex_pkg::cpu_pwrmgr_t pwr_cpu; + + lc_ctrl_pkg::lc_tx_t fetch_en; + lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; + lc_ctrl_pkg::lc_tx_t lc_dft_en; + + logic [ NumWkups-1:0] wakeups_i; + logic [ NumRstReqs-1:0] rstreqs_i; + + logic strap; + logic low_power; + + rom_ctrl_pkg::pwrmgr_data_t [NumRomInputs-1:0] rom_ctrl_i; + + prim_mubi_pkg::mubi4_t sw_rst_req_i; + + logic intr_wakeup; + + // Relevant CSR values. + logic wakeup_en_regwen; + logic [ NumWkups-1:0] wakeup_en; + logic [ NumWkups-1:0] wakeup_status; + logic wakeup_capture_en; + + logic [ NumRstReqs-1:0] reset_en; + logic [ NumRstReqs-1:0] reset_en_q; + logic [ NumRstReqs-1:0] reset_status; + + logic lowpwr_cfg_wen; + pwrmgr_reg_pkg::pwrmgr_hw2reg_wake_info_reg_t wake_info; + + // Internal DUT signals. +`ifndef PATH_TO_DUT + `define PATH_TO_DUT tb.dut +`endif + + // Slow fsm state. + pwrmgr_pkg::slow_pwr_state_e slow_state; + always_comb slow_state = `PATH_TO_DUT.u_slow_fsm.state_q; + + // Fast fsm state. + pwrmgr_pkg::fast_pwr_state_e fast_state; + always_comb fast_state = `PATH_TO_DUT.u_fsm.state_q; + + // cfg regwen + always_comb lowpwr_cfg_wen = `PATH_TO_DUT.lowpwr_cfg_wen; + + // reset status + always_comb + reset_status = { + `PATH_TO_DUT.u_reg.reset_status_val_1_qs, `PATH_TO_DUT.u_reg.reset_status_val_0_qs + }; + always_comb + reset_en_q = {`PATH_TO_DUT.u_reg.reset_en_en_1_qs, `PATH_TO_DUT.u_reg.reset_en_en_0_qs}; + always_comb + wakeup_en = { + `PATH_TO_DUT.reg2hw.wakeup_en[5].q, + `PATH_TO_DUT.reg2hw.wakeup_en[4].q, + `PATH_TO_DUT.reg2hw.wakeup_en[3].q, + `PATH_TO_DUT.reg2hw.wakeup_en[2].q, + `PATH_TO_DUT.reg2hw.wakeup_en[1].q, + `PATH_TO_DUT.reg2hw.wakeup_en[0].q + }; + + // Wakeup_status ro CSR. + always_comb + wakeup_status = { + `PATH_TO_DUT.hw2reg.wake_status[5].d, + `PATH_TO_DUT.hw2reg.wake_status[4].d, + `PATH_TO_DUT.hw2reg.wake_status[3].d, + `PATH_TO_DUT.hw2reg.wake_status[2].d, + `PATH_TO_DUT.hw2reg.wake_status[1].d, + `PATH_TO_DUT.hw2reg.wake_status[0].d + }; + + always_comb wakeup_capture_en = !`PATH_TO_DUT.u_reg.wake_info_capture_dis_qs; + always_comb wake_info = `PATH_TO_DUT.i_wake_info.info_o; + + logic intr_enable; + always_comb intr_enable = `PATH_TO_DUT.reg2hw.intr_enable.q; + + logic intr_status; + always_comb intr_status = `PATH_TO_DUT.reg2hw.intr_state.q; + + // This is only used to determine if an interrupt will be set in case of a reset while in + // low power. tryIt is very hard to perdict if the reset or a wakeup happen first, so this + // signal is used to help instead. + pwrmgr_pkg::pwrup_cause_e pwrup_cause; + always_comb pwrup_cause = `PATH_TO_DUT.slow_pwrup_cause; + + // Used to disable assertions once with the first power glitch. + bit internal_assertion_disabled; + + function automatic void update_ast_main_pok(logic value); + pwr_ast_rsp.main_pok = value; + endfunction + + function automatic void update_otp_done(logic value); + pwr_otp_rsp.otp_done = value; + endfunction + + function automatic void update_otp_idle(logic value); + pwr_otp_rsp.otp_idle = value; + endfunction + + function automatic void update_lc_done(logic value); + pwr_lc_rsp.lc_done = value; + endfunction + + function automatic void update_lc_idle(logic value); + pwr_lc_rsp.lc_idle = value; + endfunction + + function automatic void update_flash_idle(logic value); + pwr_flash.flash_idle = value; + endfunction + + function automatic void update_cpu_sleeping(logic value); + pwr_cpu.core_sleeping = value; + endfunction + + function automatic void update_wakeups(logic [NumWkups-1:0] wakeups); + wakeups_i = wakeups; + endfunction + + function automatic void update_resets(logic [NumRstReqs-1:0] resets); + rstreqs_i = resets; + endfunction + + function automatic void update_reset_en(logic [NumRstReqs-1:0] reset_en_value); + reset_en = reset_en_value; + endfunction + + function automatic void update_sw_rst_req(prim_mubi_pkg::mubi4_t value); + sw_rst_req_i = value; + endfunction + + // This could be in a hypothetical rom_ctrl driver. + function automatic void update_rom_ctrl(rom_ctrl_pkg::pwrmgr_data_t ctrl, bit unsigned index); + `DV_CHECK(index < NumRomInputs, , , "pwrmgr_if") + rom_ctrl_i[index] = ctrl; + endfunction + + // Sends a main power glitch and disables a design assertion that trips for power glitches. + task automatic glitch_power_reset(); + rst_main_n = 1'b0; + if (!internal_assertion_disabled) begin + internal_assertion_disabled = 1'b1; + `uvm_info("pwrmgr_if", "disabling power glitch related SVA", UVM_MEDIUM) + $assertoff(1, tb.dut.u_slow_fsm.IntRstReq_A); + end + repeat (2) @(posedge clk_slow); + rst_main_n = 1'b1; + endtask + + // FIXME Move all these initializations to sequences. + initial begin + // From AST. + pwr_ast_rsp = '{default: '0}; + pwr_rst_rsp = '{default: '0}; + pwr_clk_rsp = '{default: '0}; + pwr_otp_rsp = '{default: '0}; + pwr_lc_rsp = '{default: '0}; + pwr_flash = '{default: '0}; + pwr_cpu = rv_core_ibex_pkg::CPU_PWRMGR_DEFAULT; + wakeups_i = pwrmgr_pkg::WAKEUPS_DEFAULT; + rstreqs_i = pwrmgr_pkg::RSTREQS_DEFAULT; + sw_rst_req_i = prim_mubi_pkg::MuBi4False; + rom_ctrl_i = '{default: rom_ctrl_pkg::PWRMGR_DATA_DEFAULT}; + end + + clocking slow_cb @(posedge clk_slow); + input slow_state; + input pwr_ast_req; + output pwr_ast_rsp; + endclocking + + clocking fast_cb @(posedge clk); + input fast_state; + input pwr_rst_req; + output pwr_rst_rsp; + input pwr_clk_req; + output pwr_clk_rsp; + input pwr_lc_req; + output pwr_lc_rsp; + input pwr_otp_req; + output pwr_otp_rsp; + endclocking +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_scoreboard.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_scoreboard.sv new file mode 100644 index 00000000000..a5a714833c1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_scoreboard.sv @@ -0,0 +1,373 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_scoreboard extends cip_base_scoreboard #( + .CFG_T(pwrmgr_env_cfg), + .RAL_T(pwrmgr_reg_block), + .COV_T(pwrmgr_env_cov) +); + `uvm_component_utils(pwrmgr_scoreboard) + + // local variables + + // TLM agent fifos + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void build_phase(uvm_phase phase); + string common_seq_type; + super.build_phase(phase); + + void'($value$plusargs("run_%0s", common_seq_type)); + if (common_seq_type == "stress_all_with_rand_reset") do_alert_check = 0; + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + cfg.run_phase = phase; + fork + monitor_power_glitch(); + monitor_escalation_timeout(); + reset_cip_helper(); + wakeup_ctrl_coverage_collector(); + wakeup_intr_coverage_collector(); + low_power_coverage_collector(); + reset_coverage_collector(); + rom_coverage_collector(); + join_none + endtask + + task monitor_power_glitch(); + fork + forever + @cfg.pwrmgr_vif.rst_main_n begin + if (cfg.pwrmgr_vif.rst_main_n == 1'b0 && `gmv(ral.control.main_pd_n)) begin + set_exp_alert("fatal_fault", 1, 500); + end + end + join + endtask + + // An escalation timeout is triggered in test sequences by stopping clk_esc_i when the clock is + // meant to be enabled, or by driving rst_esc_ni active when the dut is not expecting it. + task monitor_escalation_timeout(); + fork + forever + @(posedge cfg.esc_clk_rst_vif.clk_gate) begin + if (cfg.pwrmgr_vif.pwr_clk_req.io_ip_clk_en) begin + // A timeout could be triggered if the escalation clock is stopped for too many clk_i + // cycles. The precise threshold is somewhat unpredictable for reasons explained in + // the pwrmgr_escalation_timeout sequence, and the sequence is such that 121 cycles + // works as a threshold to avoid unpredictable stoppages. + `uvm_info(`gfn, "Detected unexpected clk_esc_i stop", UVM_MEDIUM) + fork + begin : isolation_fork + // This fork is so we can wait for a number of cycles with the clock inactive, + // and stop waiting if the escalation clock gate is re-opened. + fork + begin + cfg.clk_rst_vif.wait_clks(121); + if (cfg.esc_clk_rst_vif.clk_gate && cfg.pwrmgr_vif.pwr_ast_req.io_clk_en && + cfg.pwrmgr_vif.pwr_clk_req.io_ip_clk_en) begin + `uvm_info(`gfn, "clk_esc_i has been inactive enough to trigger an alert", + UVM_MEDIUM) + `uvm_info(`gfn, "set_exp_alert from monitor_escalation_timeout clock gated", + UVM_MEDIUM) + set_exp_alert("fatal_fault", 1, 500); + end + end + // This stops the wait if the gate is re-opened. + @(negedge cfg.esc_clk_rst_vif.clk_gate); + join_any + disable fork; + end + join + end + end + forever + @(negedge cfg.esc_clk_rst_vif.o_rst_n) begin + if (cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On) begin + `uvm_info(`gfn, "Detected unexpected rst_esc_ni active", UVM_MEDIUM) + set_exp_alert("fatal_fault", 1, 500); + end + end + join + endtask + + // We need to reset the cip scoreboard, since the alert handler responds + // to lc domain0 resets, yet the pwrmgr's clk_rst_vif is aon. So when a + // reset happens the cip scoreboard needs to be informed, both when reset + // starts and when it ends. + task reset_cip_helper(); + fork + forever + @cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req begin + if (|cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req) begin + // Start of d0 reset request. + `uvm_info(`gfn, "pwrmgr start reset in reset_cip_helper", UVM_MEDIUM) + cfg.reset_asserted(); + end + end + forever + @cfg.pwrmgr_vif.fetch_en begin + if (cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On) begin + // End of d0 reset request. + `uvm_info(`gfn, "pwrmgr end reset in reset_cip_helper", UVM_MEDIUM) + reset_alert_state(); + end + end + join + endtask + + task wakeup_ctrl_coverage_collector(); + forever + @(posedge (|cfg.pwrmgr_vif.wakeups_i)) begin + if (cfg.en_cov) begin + // Allow for synchronization delay. + cfg.slow_clk_rst_vif.wait_clks(2); + foreach (cov.wakeup_ctrl_cg_wrap[i]) begin + cov.wakeup_ctrl_cg_wrap[i].sample(cfg.pwrmgr_vif.wakeup_en[i], + cfg.pwrmgr_vif.wakeup_capture_en, + cfg.pwrmgr_vif.wakeups_i[i]); + end + end + end + endtask + + task wakeup_intr_coverage_collector(); + forever + @(posedge (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone)) begin + if (cfg.en_cov) begin + foreach (cov.wakeup_intr_cg_wrap[i]) begin + cov.wakeup_intr_cg_wrap[i].sample( + cfg.pwrmgr_vif.wakeup_status[i], cfg.pwrmgr_vif.intr_enable, + cfg.pwrmgr_vif.intr_status, cfg.pwrmgr_vif.intr_wakeup); + end + end + end + endtask + + task low_power_coverage_collector(); + forever + @(posedge cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::LowPwrEntry) begin + if (cfg.en_cov) begin + // At this point pwrmgr is asleep. + cov.control_cg.sample(control_enables, 1'b1); + end + end + endtask + + local task sample_reset_coverage(bit sleep); + cov.hw_reset_0_cg.sample(cfg.pwrmgr_vif.rstreqs_i[0], cfg.pwrmgr_vif.reset_en[0], sleep); + cov.hw_reset_1_cg.sample(cfg.pwrmgr_vif.rstreqs_i[1], cfg.pwrmgr_vif.reset_en[1], sleep); + cov.rstmgr_sw_reset_cg.sample(cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True); + cov.main_power_reset_cg.sample( + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx], sleep); + cov.esc_reset_cg.sample(cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx], sleep); + `uvm_info(`gfn, $sformatf( + { + "reset_cg sample with hw_resets=%b, hw_resets_en=%b, ", + "esc_rst=%b, main_pwr_rst=%b, sw_rst=%b, sleep=%b" + }, + cfg.pwrmgr_vif.rstreqs_i, + cfg.pwrmgr_vif.reset_en, + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx], + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx], + cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True, + sleep + ), UVM_MEDIUM) + endtask + + task reset_coverage_collector(); + fork + forever + @(posedge cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::HwReq) begin + if (cfg.en_cov) begin + sample_reset_coverage(.sleep(1'b0)); + end + end + forever + @(posedge cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateLowPower) begin + if (cfg.en_cov) begin + sample_reset_coverage(.sleep(1'b1)); + end + end + join_none + endtask + + task rom_coverage_collector(); + forever + @( + cfg.pwrmgr_vif.rom_ctrl_i[0] or + cfg.pwrmgr_vif.rom_ctrl_i[1] or + cfg.pwrmgr_vif.rom_ctrl_i[2] or + cfg.pwrmgr_vif.lc_hw_debug_en or + cfg.pwrmgr_vif.lc_dft_en) begin + if (cfg.en_cov) begin + cov.rom_active_blockers_cg.sample( + cfg.pwrmgr_vif.rom_ctrl_i[0].done, + cfg.pwrmgr_vif.rom_ctrl_i[0].good, + cfg.pwrmgr_vif.rom_ctrl_i[1].done, + cfg.pwrmgr_vif.rom_ctrl_i[1].good, + cfg.pwrmgr_vif.rom_ctrl_i[2].done, + cfg.pwrmgr_vif.rom_ctrl_i[2].good, + cfg.pwrmgr_vif.lc_dft_en, + cfg.pwrmgr_vif.lc_hw_debug_en); + end + end + endtask + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + bit do_read_check = ~(cfg.disable_csr_rd_chk); + bit skip_intr_chk = cfg.invalid_st_test; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // if incoming access is a write to a valid csr, then make updates right away + if (addr_phase_write) begin + `uvm_info(`gfn, $sformatf("Writing 0x%x to %s", item.a_data, csr.get_full_name()), UVM_MEDIUM) + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // process the csr req + // for write, update local variable and fifo at address phase + // for read, update prediction at address phase and compare at data phase + case (csr.get_name()) + // add individual case item for each csr + "intr_state": begin + if (skip_intr_chk) return; + if (data_phase_write) begin + exp_intr &= ~item.a_data; + end else if (data_phase_read) begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + foreach (exp_intr[i]) begin + if (cfg.en_cov) begin + cov.intr_cg.sample(i, intr_en[i], exp_intr[i]); + cov.intr_pins_cg.sample(i, cfg.intr_vif.pins[i]); + end + `DV_CHECK_EQ(item.d_data[i], exp_intr[i], $sformatf("Interrupt bit %0d", i)); + `DV_CHECK_CASE_EQ(cfg.intr_vif.pins[i], (intr_en[i] & exp_intr[i]), $sformatf( + "Interrupt_pin bit %0d", i)); + end + end + // rw1c: write 1 clears, write 0 is no-op. + do_read_check = 1'b0; + end + "intr_enable", "alert_test": begin + // Do nothing + end + "intr_test": begin + if (data_phase_write) begin + bit [TL_DW-1:0] intr_en = ral.intr_enable.get_mirrored_value(); + exp_intr |= item.a_data; + if (cfg.en_cov) begin + foreach (exp_intr[i]) begin + cov.intr_test_cg.sample(i, item.a_data[i], intr_en[i], exp_intr[i]); + end + end + end + // Write-only, so it can't be read. + do_read_check = 1'b0; + end + "ctrl_cfg_regwen": begin + // Read-only. Hardware clears this bit when going to low power mode, + // and sets it in active mode. + do_read_check = 1'b0; + end + "control": begin + // Only some bits can be checked on reads. Bit 0 is cleared by hardware + // on low power transition or when registering a valid reset. + if (data_phase_write) begin + low_power_hint = get_field_val(ral.control.low_power_hint, item.a_data); + control_enables = '{ + main_clk_en: get_field_val(ral.control.core_clk_en, item.a_data), + io_clk_en: get_field_val(ral.control.io_clk_en, item.a_data), + main_pd_n: get_field_val(ral.control.main_pd_n, item.a_data) + }; + `uvm_info(`gfn, $sformatf("Writing low power hint=%b", low_power_hint), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("Writing control_enables=%p", control_enables), UVM_MEDIUM) + if (cfg.en_cov) begin + // At this point the processor is not asleep. + cov.control_cg.sample(control_enables, 1'b0); + end + end + end + "cfg_cdc_sync": begin + // rw1c: When written to 1 this bit self-clears when the slow clock domain + // syncs. + do_read_check = 1'b0; + end + "wakeup_en_regwen": begin + end + "wakeup_en": begin + end + "wake_status": begin + // Read-only. + do_read_check = 1'b0; + end + "reset_en_regwen": begin + // rw0c, so writing a 1 is a no-op. + end + "reset_en": begin + if (data_phase_write) begin + cfg.pwrmgr_vif.update_reset_en(item.a_data); + end + end + "reset_status": begin + // Read-only. + do_read_check = 1'b0; + end + "escalate_reset_status": begin + // Read-only. + do_read_check = 1'b0; + end + "wake_info_capture_dis": begin + end + "wake_info": begin + // rw1c: write 1 clears, write 0 is no-op. + do_read_check = 1'b0; + end + default: begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + `uvm_info(`gfn, $sformatf("Reading 0x%x from %s", item.d_data, csr.get_full_name()), UVM_LOW) + if (do_read_check) begin + `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data, $sformatf( + "reg name: %0s", csr.get_full_name())) + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endtask + + virtual function void reset(string kind = "HARD"); + super.reset(kind); + // reset local fifos queues and variables + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv new file mode 100644 index 00000000000..ec7f602fbcb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/pwrmgr_virtual_sequencer.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(pwrmgr_env_cfg), + .COV_T(pwrmgr_env_cov) +); + `uvm_component_utils(pwrmgr_virtual_sequencer) + + + `uvm_component_new + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv new file mode 100644 index 00000000000..41222fe2ad1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_aborted_low_power_vseq.sv @@ -0,0 +1,124 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The aborted low power test causes low power transitions to abort for CPU interrupts and nvms not +// idle. It randomly enables wakeups, info capture, and interrupts, and sends wakeups at random +// times, and causes a test failure if they are not aborted. +class pwrmgr_aborted_low_power_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_aborted_low_power_vseq) + + `uvm_object_new + + // If set causes an abort because the CPU gets an interrupt, which shows up as + // pwr_cpu.core_sleeping being low when the fast FSM is in FastPwrStateFallThrough. + rand bit cpu_interrupt; + + constraint cpu_interrupt_c { + cpu_interrupt dist { + 1 := 2, + 0 := 6 + }; + } + + rand bit flash_idle; + rand bit lc_idle; + rand bit otp_idle; + + constraint idle_c { + solve cpu_interrupt before flash_idle, lc_idle, otp_idle; + if (!cpu_interrupt) {(flash_idle && lc_idle && otp_idle) == 1'b0;} + } + + constraint wakeups_c {wakeups != 0;} + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + // Make sure wakeup capture is enabled to check the abort happened. + constraint enable_wakeup_capture_c {disable_wakeup_capture == 1'b0;} + + task body(); + logic [TL_DW-1:0] value; + wakeups_t enabled_wakeups; + check_wake_status('0); + set_nvms_idle(); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + // Enable wakeups. + enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf( + "Enabled wakeups=0x%x (wkups=%x wkup_en=%x)", enabled_wakeups, wakeups, wakeups_en + ), UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + low_power_hint = 1'b1; + + // Put CPU to sleep even before the control registers are fully written to avoid + // unexpected failures to abort due to delicate timing. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + + fork + begin + update_control_csr(); + `uvm_info(`gfn, $sformatf("After update_control_csr exp_intr=%b", exp_intr), UVM_MEDIUM) + end + begin + // Prepare for an abort ahead of time. + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + // Wait one more cycle for update_control_csr called above to predict the interrupt + // based on the value of cpu_sleeping right after the transition out of active state. + // There is enough time for this since it takes time to disable the clocks. + cfg.clk_rst_vif.wait_clks(1); + if (cpu_interrupt) begin + `uvm_info(`gfn, "Expecting a fall through (0x40)", UVM_MEDIUM) + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + end else begin + `uvm_info(`gfn, $sformatf( + "Expecting an abort (0x80): fi=%b, li=%b, oi=%b", + flash_idle, + lc_idle, + otp_idle + ), UVM_MEDIUM) + set_nvms_idle(flash_idle, lc_idle, otp_idle); + end + end + join + wait_for_rom_and_active(); + + `uvm_info(`gfn, "Back from sleep attempt", UVM_MEDIUM) + @cfg.clk_rst_vif.cb; + + // No wakeups, but check abort and fall_through. + fork + begin + fast_check_reset_status(0); + end + begin + fast_check_wake_info(.reasons('0), .fall_through(cpu_interrupt), .abort(~cpu_interrupt)); + end + join + + clear_wake_info(); + + // And check interrupt is set. + check_and_clear_interrupt(.expected(1'b1)); + + // Get ready for another round. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + set_nvms_idle(); + cfg.slow_clk_rst_vif.wait_clks(4); + end + `uvm_info(`gfn, "Test done", UVM_MEDIUM) + endtask + +endclass : pwrmgr_aborted_low_power_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv new file mode 100644 index 00000000000..7ac377973c2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_base_vseq.sv @@ -0,0 +1,831 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_base_vseq extends cip_base_vseq #( + .RAL_T (pwrmgr_reg_block), + .CFG_T (pwrmgr_env_cfg), + .COV_T (pwrmgr_env_cov), + .VIRTUAL_SEQUENCER_T(pwrmgr_virtual_sequencer) +); + `uvm_object_utils(pwrmgr_base_vseq) + + `uvm_object_new + + localparam int ActiveTimeoutInNanoSeconds = 10_000; + localparam int PropagationToSlowTimeoutInNanoSeconds = 15_000; + localparam int FetchEnTimeoutNs = 40_000; + + localparam int MaxCyclesBeforeEnable = 12; + + import pwrmgr_reg_pkg::NumRomInputs; + + typedef enum int { + FastFsmActive, + FastFsmInactive + } fast_fsm_activity_e; + + // Random wakeups and resets. + rand wakeups_t wakeups; + rand wakeups_t wakeups_en; + rand resets_t resets; + rand resets_t resets_en; + rand bit power_glitch_reset; + rand bit escalation_reset; + rand bit ndm_reset; + + rand bit en_intr; + + constraint resets_en_c { + solve resets, power_glitch_reset, escalation_reset, ndm_reset before resets_en; + |{resets_en & resets, power_glitch_reset, escalation_reset, ndm_reset} == 1'b1; + } + + rand bit disable_wakeup_capture; + + // Random control enables. + rand control_enables_t control_enables; + + // Random delays. + rand int cycles_before_clks_ok; + rand int cycles_between_clks_ok; + rand int cycles_before_main_status; + rand int cycles_before_io_status; + rand int cycles_before_rst_lc_src; + rand int cycles_before_rst_sys_src; + rand int cycles_before_otp_done; + rand int cycles_before_lc_done; + rand int cycles_before_wakeup; + rand int cycles_before_reset; + + // Slow responder delays. + rand int cycles_before_main_clk_en; + rand int cycles_before_io_clk_en; + rand int cycles_before_main_pok; + + // This tracks the local objection count from these responders. We do not use UVM + // objections because uvm_objection::wait_for(UVM_ALL_DROPPED, this) seems to wait + // for all objections to be dropped, not just those raised by this. + local int fast_objection_count = 0; + local int slow_objection_count = 0; + + constraint cycles_before_clks_ok_c {cycles_before_clks_ok inside {[3 : 10]};} + constraint cycles_between_clks_ok_c {cycles_between_clks_ok inside {[3 : 10]};} + constraint cycles_before_main_status_c {cycles_before_main_status inside {[0 : 4]};} + constraint cycles_before_io_status_c {cycles_before_io_status inside {[0 : 4]};} + constraint cycles_before_rst_lc_src_base_c {cycles_before_rst_lc_src inside {[0 : 4]};} + constraint cycles_before_rst_sys_src_base_c {cycles_before_rst_sys_src inside {[0 : 4]};} + constraint cycles_before_otp_done_base_c {cycles_before_otp_done inside {[0 : 4]};} + constraint cycles_before_lc_done_base_c {cycles_before_lc_done inside {[0 : 4]};} + constraint cycles_before_wakeup_c {cycles_before_wakeup inside {[2 : 6]};} + constraint cycles_before_reset_c {cycles_before_reset inside {[2 : 6]};} + constraint cycles_before_main_clk_en_c { + cycles_before_main_clk_en inside {[1 : MaxCyclesBeforeEnable]}; + } + constraint cycles_before_io_clk_en_c { + cycles_before_io_clk_en inside {[1 : MaxCyclesBeforeEnable - 2]}; + } + constraint cycles_before_main_pok_c {cycles_before_main_pok inside {[2 : MaxCyclesBeforeEnable]};} + + // This is used to trigger a software reset, as per rstmgr's `reset_req` CSR. + mubi4_t sw_rst_from_rstmgr = MuBi4False; + + bit do_pwrmgr_init = 1'b1; + // This static variable is incremented in each pre_start and decremented in each post_start. + // It is used to start and stop the responders when the parent sequence starts and ends. + local static int sequence_depth = 0; + pwrmgr_mubi_e mubi_mode; + + // This stops randomizing cycles counts that select from a pipeline, since + // changes can lead to missing or unexpected transitions. + task stop_randomizing_cycles(); + cycles_before_main_clk_en.rand_mode(0); + cycles_before_io_clk_en.rand_mode(0); + cycles_before_main_pok.rand_mode(0); + endtask + + // Disable exclusions for CONTROL.USB_CLK_EN_ACTIVE and RESET_EN: they are meant for full-chip only. + function void disable_unnecessary_exclusions(); + csr_excl_item csr_excl = ral.get_excl_item(); + `uvm_info(`gfn, "Dealing with exclusions", UVM_MEDIUM) + csr_excl.enable_excl(.obj("pwrmgr_reg_block.control"), .enable(1'b0)); + csr_excl.enable_excl(.obj("pwrmgr_reg_block.reset_en"), .enable(1'b0)); + csr_excl.print_exclusions(UVM_MEDIUM); + endfunction + + virtual task pre_start(); + cfg.pwrmgr_vif.lc_hw_debug_en = lc_ctrl_pkg::Off; + cfg.pwrmgr_vif.lc_dft_en = lc_ctrl_pkg::Off; + mubi_mode = PwrmgrMubiNone; + `DV_GET_ENUM_PLUSARG(pwrmgr_mubi_e, mubi_mode, pwrmgr_mubi_mode) + `uvm_info(`gfn, $sformatf("pwrmgr mubi mode : %s", mubi_mode.name()), UVM_MEDIUM) + + if (do_pwrmgr_init) pwrmgr_init(); + disable_unnecessary_exclusions(); + cfg.slow_clk_rst_vif.wait_for_reset(.wait_negedge(0)); + stop_randomizing_cycles(); + fork + // Deactivate rst_main_n to make sure the slow fsm won't be confused into thinking + // a power glitch occurred, and wait some cycles so testing doesn't start until any + // side-effects are cleared. This confusion can arise if a sequence with random resets + // gets reset while sending a power glitch. + begin + cfg.pwrmgr_vif.rst_main_n = 1'b1; + cfg.slow_clk_rst_vif.wait_clks(7); + end + begin + if (sequence_depth == 0) begin + `uvm_info(`gfn, "Starting responders", UVM_MEDIUM) + slow_responder(); + fast_responder(); + end + ++sequence_depth; + super.pre_start(); + end + join + endtask : pre_start + + task post_apply_reset(string reset_kind = "HARD"); + super.post_apply_reset(reset_kind); + if (reset_kind == "HARD") begin + // Undo any pending resets. + cfg.pwrmgr_vif.rst_main_n = 1'b1; + cfg.pwrmgr_vif.update_resets(0); + end + + `uvm_info(`gfn, "waiting for fast active after applying reset", UVM_MEDIUM) + update_roms_response(.done(MuBi4True), .good(MuBi4True)); + wait_for_fast_fsm(FastFsmActive); + // And drive the cpu not sleeping. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + endtask + + task post_start(); + super.post_start(); + --sequence_depth; + if (sequence_depth == 0) begin + `uvm_info(`gfn, $sformatf( + "Waiting for all objections done with fast=%0d, slow=%0d", + fast_objection_count, + slow_objection_count + ), UVM_MEDIUM) + `DV_WAIT(fast_objection_count == 0 && slow_objection_count == 0) + `uvm_info(`gfn, "all local objections are done", UVM_LOW) + control_assertions(0); + `uvm_info(`gfn, "Stopping responders", UVM_MEDIUM) + disable slow_responder; + disable fast_responder; + end + endtask + + virtual task dut_init(string reset_kind = "HARD"); + super.dut_init(); + endtask + + virtual task dut_shutdown(); + // There are no known checks to perform here. + endtask + + virtual task apply_reset(string kind = "HARD"); + `uvm_info(`gfn, $sformatf("At apply_reset kind='%0s'", kind), UVM_MEDIUM) + fork + super.apply_reset(kind); + if (kind == "HARD") begin + // A short slow clock reset should suffice. + cfg.slow_clk_rst_vif.apply_reset(.reset_width_clks(5)); + end + cfg.esc_clk_rst_vif.apply_reset(); + cfg.lc_clk_rst_vif.apply_reset(); + // Escalation resets are cleared when reset goes active. + clear_escalation_reset(); + clear_ndm_reset(); + join + // And wait until the responders settle with all okay from the AST. + `DV_WAIT( + cfg.pwrmgr_vif.pwr_ast_rsp.main_pok && + cfg.pwrmgr_vif.pwr_ast_rsp.core_clk_val && + cfg.pwrmgr_vif.pwr_ast_rsp.io_clk_val) + `uvm_info(`gfn, $sformatf("Out of apply_reset kind='%0s'", kind), UVM_MEDIUM) + endtask + + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + cfg.slow_clk_rst_vif.drive_rst_pin(0); + cfg.esc_clk_rst_vif.drive_rst_pin(0); + cfg.lc_clk_rst_vif.drive_rst_pin(0); + super.apply_resets_concurrently(cfg.slow_clk_rst_vif.clk_period_ps); + cfg.esc_clk_rst_vif.drive_rst_pin(1); + cfg.lc_clk_rst_vif.drive_rst_pin(1); + cfg.slow_clk_rst_vif.drive_rst_pin(1); + endtask + + // setup basic pwrmgr features + virtual task pwrmgr_init(); + // The fast clock frequency is set by ral. + // The real slow clock rate is 200kHz, but that slows testing down. + // Increasing its frequency improves DV efficiency without compromising quality. + cfg.slow_clk_rst_vif.set_freq_mhz(7); + `uvm_info(`gfn, $sformatf( + "slow clock freq=%fMHz, period=%0dns", + cfg.slow_clk_rst_vif.clk_freq_mhz, + cfg.slow_clk_rst_vif.clk_period_ps + ), UVM_MEDIUM) + cfg.esc_clk_rst_vif.set_freq_mhz(cfg.clk_rst_vif.clk_freq_mhz); + cfg.lc_clk_rst_vif.set_freq_mhz(cfg.clk_rst_vif.clk_freq_mhz); + set_ndmreset_req('0); + control_assertions(0); + endtask + + virtual task setup_interrupt(bit enable); + csr_wr(.ptr(ral.intr_enable.wakeup), .value(enable)); + `uvm_info(`gfn, $sformatf("Wakeup interrupt is %0sabled", enable ? "en" : "dis"), UVM_MEDIUM) + endtask + + // May check intr_state.wakeup CSR against expected, and regardless, it checks that the + // interrupt output matches intr_state && intr_enable. The first check is disabled if + // check_expected is off, which is used when a reset and an interrupt come in close + // temporal proximity. + virtual task check_and_clear_interrupt(bit expected, bit check_expected = 1'b1); + bit enable; + `uvm_info(`gfn, "Checking and clearing interrupt", UVM_MEDIUM) + if (check_expected) begin + csr_rd_check(.ptr(ral.intr_state.wakeup), .compare_value(expected), + .err_msg("interrupt mismatch")); + end else begin + csr_rd(.ptr(ral.intr_state.wakeup), .value(expected)); + end + csr_rd(.ptr(ral.intr_enable.wakeup), .value(enable)); + `DV_CHECK_EQ(cfg.pwrmgr_vif.intr_wakeup, expected && enable) + csr_wr(.ptr(ral.intr_state.wakeup), .value(1'b1)); + endtask + + local function void raise_fast_objection(string label); + ++fast_objection_count; + `uvm_info(`gfn, $sformatf("Raising fast objection to %0d for %0s", fast_objection_count, label), + UVM_HIGH) + endfunction + + local function void drop_fast_objection(string label); + --fast_objection_count; + `uvm_info(`gfn, $sformatf("Dropping fast objection to %0d for %0s", fast_objection_count, label + ), UVM_HIGH) + endfunction + + local function void raise_slow_objection(string label); + ++slow_objection_count; + `uvm_info(`gfn, $sformatf("Raising slow objection to %0d for %0s", slow_objection_count, label), + UVM_MEDIUM) + endfunction + + local function void drop_slow_objection(string label); + --slow_objection_count; + `uvm_info(`gfn, $sformatf("Dropping slow objection to %0d for %0s", slow_objection_count, label + ), UVM_MEDIUM) + endfunction + + virtual function void set_ndmreset_req(logic value); + cfg.pwrmgr_vif.cpu_i.ndmreset_req = value; + endfunction + + // Generates expected responses for the slow fsm. + // - Completes the clock handshake with the ast: when a clk_en output changes, after a few + // cycles the ast is expected to set the corresponding clk_val input to the same value. + // - It is possible changes occur in fast succession, so the side-effect is pipelined. + // Uses macros because VCS flags an error for assignments to automatic variables, + // even if the variable is a ref to an interface variable. + + `define SLOW_DETECT(rsp_name_, req_) \ + forever \ + @req_ begin \ + raise_slow_objection(rsp_name_); \ + `uvm_info(`gfn, $sformatf( \ + "slow_responder: Will drive %0s to %b", rsp_name_, req_), UVM_MEDIUM) \ + end + + `define SLOW_SHIFT_SR(req_, rsp_sr_) \ + forever \ + @cfg.slow_clk_rst_vif.cb begin \ + rsp_sr_ = {rsp_sr_[MaxCyclesBeforeEnable-1:0], req_}; \ + end + + `define SLOW_ASSIGN(rsp_name_, cycles_, rsp_sr_, rsp_) \ + forever \ + @(rsp_sr_[cycles_]) begin \ + `uvm_info(`gfn, $sformatf( \ + "slow_responder: Driving %0s to %b after %0d AON cycles.", \ + rsp_name_, \ + rsp_sr_[cycles_], \ + cycles_ \ + ), UVM_MEDIUM) \ + rsp_ <= rsp_sr_[cycles_]; \ + drop_slow_objection(rsp_name_); \ + end + + task slow_responder(); + logic [MaxCyclesBeforeEnable:0] main_clk_val_sr; + logic [MaxCyclesBeforeEnable:0] io_clk_val_sr; + logic [MaxCyclesBeforeEnable:0] main_pd_val_sr; + fork + `SLOW_DETECT("main_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.core_clk_en) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.core_clk_en, main_clk_val_sr) + `SLOW_ASSIGN("main_clk_val", cycles_before_main_clk_en, main_clk_val_sr, + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.core_clk_val) + + `SLOW_DETECT("io_clk_val", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.io_clk_en) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.io_clk_en, io_clk_val_sr) + // Notice this splits updates due to io_clk_en in two processes: with a single process + // and a wait inside a quick sequence of changes would cause skipping some update, per + // SV scheduling semantics. + forever + @(io_clk_val_sr[cycles_before_io_clk_en]) begin + logic new_value = io_clk_val_sr[cycles_before_io_clk_en]; + `uvm_info(`gfn, $sformatf( + "slow_responder: Driving %0s to %b after %0d AON cycles.", + "io_clk_val", + new_value, + cycles_before_io_clk_en + ), UVM_MEDIUM) + if (new_value == 1) begin + cfg.clk_rst_vif.start_clk(); + cfg.lc_clk_rst_vif.start_clk(); + cfg.esc_clk_rst_vif.start_clk(); + end else begin + cfg.clk_rst_vif.stop_clk(); + cfg.lc_clk_rst_vif.stop_clk(); + cfg.esc_clk_rst_vif.stop_clk(); + end + end + forever + @(io_clk_val_sr[cycles_before_io_clk_en+2]) begin + logic new_value = io_clk_val_sr[cycles_before_io_clk_en+2]; + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.io_clk_val <= new_value; + drop_slow_objection("io_clk_val"); + end + + `SLOW_DETECT("main_pok", cfg.pwrmgr_vif.slow_cb.pwr_ast_req.main_pd_n) + `SLOW_SHIFT_SR(cfg.pwrmgr_vif.slow_cb.pwr_ast_req.main_pd_n, main_pd_val_sr) + `SLOW_ASSIGN("main_pok", cycles_before_main_pok, main_pd_val_sr, + cfg.pwrmgr_vif.slow_cb.pwr_ast_rsp.main_pok) + join_none + endtask : slow_responder + `undef SLOW_DETECT + `undef SLOW_SHIFT_SR + `undef SLOW_ASSIGN + + // Generates expected responses for the fast fsm. + // - Completes the reset handshake with the rstmgr for lc and sys resets: soon after a + // reset is requested the corresponding active low reset src must go low. + // - Completes the handshake with the clkmgr for io, main, and usb clocks: + // each status input needs to track the corresponding ip_clk_en output. + // - Completes handshake with lc and otp: *_done needs to track *_init. + // Macros for the same reason as the slow responder. + + `define FAST_RESPONSE_ACTION(rsp_name, rsp, req, cycles) \ + `uvm_info(`gfn, $sformatf( \ + "fast_responder %s: Will drive %0s to %b in %0d fast clock cycles", \ + rsp_name, rsp_name, req, cycles), UVM_HIGH) \ + cfg.clk_rst_vif.wait_clks(cycles); \ + rsp <= req; \ + `uvm_info(`gfn, $sformatf("fast_responder %s: Driving %0s to %b", rsp_name, rsp_name, req), UVM_HIGH) \ + + + task fast_responder(); + fork + forever + @cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req begin + `uvm_info(`gfn, $sformatf( + "fast responder got rst_lc_req change to 0x%x", + cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req + ), UVM_HIGH) + raise_fast_objection("rst_lc_src_n"); + `FAST_RESPONSE_ACTION("rst_lc_src_n", cfg.pwrmgr_vif.fast_cb.pwr_rst_rsp.rst_lc_src_n, + ~cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req, + cycles_before_rst_lc_src) + if (cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_lc_req[1] == 1'b0) begin + // Wait for the rst_lc_src_n[1] input to go inactive. + if (cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1] != 1'b1) + @(posedge cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1]); + cfg.esc_clk_rst_vif.drive_rst_pin(1); + cfg.lc_clk_rst_vif.drive_rst_pin(1); + end else begin + // And clear all reset requests when rst_lc_src_n[1] goes active, because when + // peripherals are reset they should drop their reset requests. + if (cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1] != 1'b0) + @(negedge cfg.pwrmgr_vif.pwr_rst_rsp.rst_lc_src_n[1]); + cfg.esc_clk_rst_vif.drive_rst_pin(0); + cfg.lc_clk_rst_vif.drive_rst_pin(0); + clear_escalation_reset(); + clear_ndm_reset(); + cfg.pwrmgr_vif.update_resets('0); + cfg.pwrmgr_vif.update_sw_rst_req(MuBi4False); + `uvm_info(`gfn, "Clearing resets", UVM_MEDIUM) + end + drop_fast_objection("rst_lc_src_n"); + `uvm_info(`gfn, "fast responder done with rst_lc_req change", UVM_HIGH) + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_sys_req begin + raise_fast_objection("rst_sys_src_n"); + `FAST_RESPONSE_ACTION("rst_sys_src_n", cfg.pwrmgr_vif.fast_cb.pwr_rst_rsp.rst_sys_src_n, + ~cfg.pwrmgr_vif.fast_cb.pwr_rst_req.rst_sys_req, + cycles_before_rst_sys_src) + drop_fast_objection("rst_sys_src_n"); + end + + forever + @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.main_ip_clk_en begin + raise_fast_objection("main_status"); + `FAST_RESPONSE_ACTION("main_status", cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.main_status, + cfg.pwrmgr_vif.fast_cb.pwr_clk_req.main_ip_clk_en, + cycles_before_main_status) + drop_fast_objection("main_status"); + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en begin + logic new_value = cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en; + raise_fast_objection("io_status"); + `uvm_info(`gfn, $sformatf( + "fast_responder: Will drive %0s to %b in %0d fast clock cycles", + "io_status", + new_value, + cycles_before_io_status + ), UVM_HIGH) + cfg.clk_rst_vif.wait_clks(cycles_before_io_status); + if (new_value) cfg.esc_clk_rst_vif.start_clk(); + else cfg.esc_clk_rst_vif.stop_clk(); + cfg.clk_rst_vif.wait_clks(2); + cfg.pwrmgr_vif.fast_cb.pwr_clk_rsp.io_status <= new_value; + `uvm_info(`gfn, $sformatf( + "fast_responder: Driving %0s to %b", + "io_status", + cfg.pwrmgr_vif.fast_cb.pwr_clk_req.io_ip_clk_en + ), UVM_HIGH) + drop_fast_objection("io_status"); + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_lc_req.lc_init begin + raise_fast_objection("lc_done"); + `FAST_RESPONSE_ACTION("lc_done", cfg.pwrmgr_vif.fast_cb.pwr_lc_rsp.lc_done, + cfg.pwrmgr_vif.fast_cb.pwr_lc_req.lc_init, cycles_before_lc_done) + drop_fast_objection("lc_done"); + end + forever + @cfg.pwrmgr_vif.fast_cb.pwr_otp_req.otp_init begin + raise_fast_objection("otp_done"); + `FAST_RESPONSE_ACTION("otp_done", cfg.pwrmgr_vif.fast_cb.pwr_otp_rsp.otp_done, + cfg.pwrmgr_vif.fast_cb.pwr_otp_req.otp_init, cycles_before_otp_done) + drop_fast_objection("otp_done"); + end + join_none + endtask : fast_responder + `undef FAST_RESPONSE_ACTION + + function void control_assertions(bit enable); + `uvm_info(`gfn, $sformatf("%0sabling assertions", enable ? "En" : "Dis"), UVM_MEDIUM) + cfg.pwrmgr_clock_enables_sva_vif.disable_sva = !enable; + cfg.pwrmgr_rstmgr_sva_vif.disable_sva = !enable; + endfunction + + local task wait_for_fall_through(); + `DV_WAIT(!cfg.pwrmgr_vif.pwr_cpu.core_sleeping) + exp_intr = 1'b1; + `uvm_info(`gfn, "wait_for_fall_through succeeds", UVM_MEDIUM) + endtask + + local task wait_for_abort(); + `DV_WAIT( + !cfg.pwrmgr_vif.pwr_flash.flash_idle || !cfg.pwrmgr_vif.pwr_otp_rsp.otp_idle || + !cfg.pwrmgr_vif.pwr_lc_rsp.lc_idle) + exp_intr = 1'b1; + `uvm_info(`gfn, "wait_for_abort succeeds", UVM_MEDIUM) + endtask + + local task wait_for_low_power_transition(); + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + exp_wakeup_reasons = wakeups & wakeups_en; + exp_intr = 1'b1; + `uvm_info(`gfn, "Setting expected interrupt", UVM_MEDIUM) + endtask + + task process_low_power_hint(); + `uvm_info(`gfn, "Entering process_low_power_hint", UVM_MEDIUM) + // Timeout if the low power transition waits too long for WFI. + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + `uvm_info(`gfn, "In process_low_power_hint pre forks", UVM_MEDIUM) + // Clear expectations. + exp_wakeup_reasons = 1'b0; + fork + begin : isolation_fork + fork + wait_for_fall_through(); + wait_for_abort(); + wait_for_low_power_transition(); + join_any + disable fork; + end + join + // At this point we know the low power transition went through or was aborted. + // If it went through, determine if the transition to active state is for a reset, and + // cancel the expected interrupt. + if (exp_wakeup_reasons) begin + `DV_WAIT(cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateMainPowerOn) + if (cfg.pwrmgr_vif.pwrup_cause == pwrmgr_pkg::Reset) begin + `uvm_info(`gfn, "Cancelling expected interrupt", UVM_MEDIUM) + exp_intr = 1'b0; + end + end + endtask + + // Updates control CSR. + task update_control_csr(); + fork + begin + ral.control.core_clk_en.set(control_enables.main_clk_en); + ral.control.io_clk_en.set(control_enables.io_clk_en); + ral.control.main_pd_n.set(control_enables.main_pd_n); + ral.control.low_power_hint.set(low_power_hint); + // Disable assertions when main power is down. + control_assertions(control_enables.main_pd_n); + `uvm_info(`gfn, $sformatf( + "Setting control CSR to 0x%x, enables=%p, low_power_hint=%b", + ral.control.get(), + control_enables, + low_power_hint + ), UVM_MEDIUM) + csr_update(.csr(ral.control)); + wait_for_csr_to_propagate_to_slow_domain(); + end + // Predict the effect of the potential low power transition. + if (low_power_hint) process_low_power_hint(); + join_any + endtask : update_control_csr + + // This enables the fast fsm to transition to low power when all nvms are idle after the + // transition is enabled by software and cpu WFI. When not all are idle the transition is + // aborted. + virtual task set_nvms_idle(logic flash_idle = 1'b1, logic lc_idle = 1'b1, logic otp_idle = 1'b1); + `uvm_info(`gfn, $sformatf( + "Setting nvms idle: flash=%b, lc=%b, otp=%b", flash_idle, lc_idle, otp_idle), + UVM_MEDIUM) + cfg.pwrmgr_vif.update_flash_idle(flash_idle); + cfg.pwrmgr_vif.update_lc_idle(lc_idle); + cfg.pwrmgr_vif.update_otp_idle(otp_idle); + endtask + + // This checks the CPU is enabled, use it to start CSR activity. + function bit cpu_is_enabled(); + return cfg.pwrmgr_vif.fetch_en == lc_ctrl_pkg::On; + endfunction + + // Waits for the fast fsm becoming active or inactive, indicated by the + // fetch_en output going On or Off respectively. + task wait_for_fast_fsm(fast_fsm_activity_e activity = FastFsmActive); + lc_ctrl_pkg::lc_tx_t fetch_en = activity == FastFsmActive ? lc_ctrl_pkg::On : lc_ctrl_pkg::Off; + `uvm_info(`gfn, $sformatf("starting wait for pwrmgr %s", activity.name), UVM_MEDIUM) + `DV_SPINWAIT(wait (cfg.pwrmgr_vif.fetch_en == fetch_en);, + "timeout waiting for pwrmgr fast fsm target activity", FetchEnTimeoutNs) + `uvm_info(`gfn, $sformatf("pwrmgr reached %s", activity.name), UVM_MEDIUM) + endtask + + // Waits for the lc_rst output going inactive, which would complete a device reset. + // This should not be called for shallow sleep, since there is no lc_rst request. + task wait_for_lc_rst_release(); + `uvm_info(`gfn, "starting wait for release of lc_rst for non-aon domain", UVM_MEDIUM) + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req[1] == 1'b1, + "timeout waiting for lc_rst[1] to be active", FetchEnTimeoutNs) + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req[1] == 1'b0, + "timeout waiting for lc_rst[1] to be inactive", FetchEnTimeoutNs) + `uvm_info(`gfn, "pwrmgr fast released lc_req[1]", UVM_MEDIUM) + endtask + + task wait_for_reset_cause(pwrmgr_pkg::reset_cause_e cause); + `DV_WAIT(cfg.pwrmgr_vif.pwr_rst_req.reset_cause == cause) + `uvm_info(`gfn, $sformatf("Observed reset cause_match %s (0x%x)", cause.name, cause), + UVM_MEDIUM) + endtask + + virtual task wait_for_csr_to_propagate_to_slow_domain(); + csr_wr(.ptr(ral.cfg_cdc_sync), .value(1'b1)); + csr_spinwait(.ptr(ral.cfg_cdc_sync), .exp_data(1'b0), + .timeout_ns(PropagationToSlowTimeoutInNanoSeconds)); + `uvm_info(`gfn, "CSR updates made it to the slow domain", UVM_MEDIUM) + endtask + + // Checks the reset_status CSR matches expectations. + task check_reset_status(resets_t expected_resets); + csr_rd_check(.ptr(ral.reset_status[0]), .compare_value(expected_resets), + .err_msg("reset_status")); + endtask + + task fast_check_reset_status(resets_t expected_resets); + logic [pwrmgr_reg_pkg::NumRstReqs-1:0] init_reset_status; + `uvm_info(`gfn, "init reset status", UVM_MEDIUM); + // Wait to get out of low power state, since all reset status should have settled. + if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateLowPower) begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateLowPower);, + "fast state out of low power for reset timeout", 15_000) + end + + init_reset_status = cfg.pwrmgr_vif.reset_status; + if (expected_resets == init_reset_status) begin + // This is a success, so nothing more to do. + return; + end else begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.reset_status != init_reset_status);, $sformatf( + "reset_status wait timeout exp:%x init:%x", expected_resets, init_reset_status), + 15_000) + // The various bits of reset_status could have different sync delays, wait some more. + cfg.clk_rst_vif.wait_clks(2); + `DV_CHECK_EQ(cfg.pwrmgr_vif.reset_status, expected_resets) + end + endtask + + // Checks the wake_status CSR matches expectations. + task check_wake_status(wakeups_t expected_wakeups); + csr_rd_check(.ptr(ral.wake_status[0]), .compare_value(expected_wakeups), + .err_msg("wake_status")); + endtask + + // Checks that wake_status meets expectations. Notice different bits of wake_status can + // be updated at different times, according to their arrival order. Also, whenever reset + // goes active this comparison stops. + task fast_check_wake_status(wakeups_t expected_wakeups); + logic [pwrmgr_reg_pkg::NumWkups-1:0] init_wakeup_status; + `uvm_info(`gfn, "init wakeup", UVM_MEDIUM); + init_wakeup_status = cfg.pwrmgr_vif.wakeup_status; + + // Wait to get out of low power state, since all wake status should have settled + if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateLowPower) begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateLowPower);, + "fast state out of low power for wakeup timeout", 15_000) + end + + if (expected_wakeups == init_wakeup_status) begin + // This is a success, so nothing more to do. + return; + end else begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.wakeup_status != init_wakeup_status);, $sformatf( + "wakeup_status wait timeout exp:%x init:%x", expected_wakeups, init_wakeup_status + ), 15_000) + // The various bits of wakeup_status could have arrived at different time because they are + // triggered outside pwrmgr, so wait a couple more cycles until there is a match or there + // is a reset. + repeat (2) begin + if (cfg.pwrmgr_vif.wakeup_status == expected_wakeups || !cfg.clk_rst_vif.rst_n) return; + cfg.clk_rst_vif.wait_clks(1); + end + `DV_CHECK_EQ(cfg.pwrmgr_vif.wakeup_status, expected_wakeups) + end + endtask + + task fast_check_wake_info(wakeups_t reasons, wakeups_t prior_reasons = '0, bit fall_through, + bit prior_fall_through = '0, bit abort, bit prior_abort = '0); + pwrmgr_reg_pkg::pwrmgr_hw2reg_wake_info_reg_t initial_value, exp_value; + initial_value = cfg.pwrmgr_vif.wake_info; + + if (disable_wakeup_capture) begin + exp_value.reasons = prior_reasons; + exp_value.fall_through = prior_fall_through; + exp_value.abort = prior_abort; + end else begin + exp_value.reasons = (reasons | prior_reasons); + exp_value.fall_through = (fall_through | prior_fall_through); + exp_value.abort = (abort | prior_abort); + end + if (exp_value != initial_value) begin + // The various bits of wake_info could have different sync delays, so wait some more. + cfg.clk_rst_vif.wait_clks(1); + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.wake_info == exp_value);, + $sformatf("wake info wait timeout exp:%p actual:%p", exp_value, + cfg.pwrmgr_vif.wake_info), + 15_000) + end + endtask : fast_check_wake_info + + // Checks the wake_info CSR matches expectations depending on capture disable. + // The per-field "prior_" arguments support cases where the wake_info register was not + // cleared and may contain residual values. + task check_wake_info(wakeups_t reasons, wakeups_t prior_reasons = '0, bit fall_through, + bit prior_fall_through = '0, bit abort, bit prior_abort = '0); + if (disable_wakeup_capture) begin + csr_rd_check(.ptr(ral.wake_info.reasons), .compare_value(prior_reasons), + .err_msg("With capture disabled")); + csr_rd_check(.ptr(ral.wake_info.fall_through), .compare_value(prior_fall_through), + .err_msg("With capture disabled")); + csr_rd_check(.ptr(ral.wake_info.abort), .compare_value(prior_abort), + .err_msg("With capture disabled")); + end else begin + csr_rd_check(.ptr(ral.wake_info.reasons), .compare_value(reasons | prior_reasons), + .err_msg("With capture enabled")); + csr_rd_check(.ptr(ral.wake_info.fall_through), + .compare_value(fall_through | prior_fall_through), + .err_msg("With capture enabled")); + csr_rd_check(.ptr(ral.wake_info.abort), .compare_value(abort | prior_abort), + .err_msg("With capture enabled")); + end + endtask : check_wake_info + + task clear_wake_info(); + // To clear wake_info, capture must be disabled. + csr_wr(.ptr(ral.wake_info_capture_dis), .value(1'b1)); + csr_wr(.ptr(ral.wake_info), .value('1)); + endtask + + function void send_escalation_reset(); + `uvm_info(`gfn, "Sending escalation reset", UVM_MEDIUM) + cfg.m_esc_agent_cfg.vif.sender_cb.esc_tx_int <= 2'b10; + endfunction + + function void clear_escalation_reset(); + `uvm_info(`gfn, "Clearing escalation reset", UVM_MEDIUM) + cfg.m_esc_agent_cfg.vif.sender_cb.esc_tx_int <= 2'b01; + endfunction + + function void send_ndm_reset(); + `uvm_info(`gfn, "Sending ndm reset", UVM_MEDIUM) + cfg.pwrmgr_vif.cpu_i.ndmreset_req = 1'b1; + endfunction + + function void clear_ndm_reset(); + `uvm_info(`gfn, "Clearing ndm reset", UVM_MEDIUM) + cfg.pwrmgr_vif.cpu_i.ndmreset_req = 1'b0; + endfunction + + task send_power_glitch(); + // Create glitch by 'glitch_power_reset'. An outgoing alert is only possible + // when main power is up. + if (control_enables.main_pd_n) expect_fatal_alerts = 1; + else expect_fatal_alerts = 0; + `uvm_info(`gfn, $sformatf( + "Sending power glitch, expecting %0s alert", expect_fatal_alerts ? "an" : "no"), + UVM_MEDIUM) + cfg.pwrmgr_vif.glitch_power_reset(); + endtask + + // This sets rom_ctrl responses. + function void update_roms_response(mubi4_t done = MuBi4True, mubi4_t good = MuBi4True); + // Set all to true. + for (int r = 0; r < NumRomInputs; ++r) begin + cfg.pwrmgr_vif.update_rom_ctrl('{done: done, good: good}, r); + end + endfunction + + // Randomize roms response. + // This can be called after a reset before the fast fsm is active to check the + // rom response handling. + task randomize_roms_response(); + mubi4_t done; + mubi4_t good; + int rom_index; + // Randomize all without setting done to True. + repeat (5) begin + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(rom_index, rom_index inside {[0:NumRomInputs-1]};) + done = get_rand_mubi4_val(.t_weight(0), .f_weight(1), .other_weight(1)); + good = get_rand_mubi4_val(.t_weight(1), .f_weight(1), .other_weight(1)); + cfg.pwrmgr_vif.update_rom_ctrl('{done: done, good: good}, rom_index); + cfg.clk_rst_vif.wait_clks(5); + end + // Set done to true and randomize good without setting it to True. + // Notice this can lead to a transition to active state depending on some lc inputs. + update_roms_response(.done(MuBi4True), .good(MuBi4False)); + `DV_WAIT(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone) + repeat (5) begin + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(rom_index, rom_index inside {[0:NumRomInputs-1]};) + done = get_rand_mubi4_val(.t_weight(1), .f_weight(1), .other_weight(1)); + good = get_rand_mubi4_val(.t_weight(1), .f_weight(1), .other_weight(1)); + cfg.pwrmgr_vif.update_rom_ctrl('{done: done, good: good}, rom_index); + cfg.clk_rst_vif.wait_clks(5); + end + // Set all to true. + update_roms_response(.done(MuBi4True), .good(MuBi4True)); + `uvm_info(`gfn, "Set rom response to MuBi4True", UVM_MEDIUM) + endtask : randomize_roms_response + + // Drive rom_ctrl during a reset to randomly check rom responses. + virtual task wait_for_rom_and_active(); + // Do nothing if the fast fsm is active and cpu is enabled. + if (cpu_is_enabled()) return; + // First make sure the rom will block transition to active. + `uvm_info(`gfn, "Started wait_for_rom_and_active", UVM_MEDIUM) + cfg.pwrmgr_vif.update_rom_ctrl('{default: MuBi4False}, 0); + fork + randomize_roms_response(); + wait_for_fast_fsm(FastFsmActive); + join + `uvm_info(`gfn, "Finished wait_for_rom_and_active", UVM_MEDIUM) + endtask + + // Control assertions in rom_ctrl synchronizers since they check for stability and the rom_ctrl + // randomization can trip them. + task control_rom_ctrl_sync_assertions(bit enable); + if (enable) begin + $asserton(0, "tb.dut.u_cdc.gen_rom_inputs[0].u_sync_rom_ctrl"); + $asserton(0, "tb.dut.u_cdc.gen_rom_inputs[1].u_sync_rom_ctrl"); + $asserton(0, "tb.dut.u_cdc.gen_rom_inputs[2].u_sync_rom_ctrl"); + end else begin + $assertoff(0, "tb.dut.u_cdc.gen_rom_inputs[0].u_sync_rom_ctrl"); + $assertoff(0, "tb.dut.u_cdc.gen_rom_inputs[1].u_sync_rom_ctrl"); + $assertoff(0, "tb.dut.u_cdc.gen_rom_inputs[2].u_sync_rom_ctrl"); + end + endtask + +endclass : pwrmgr_base_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv new file mode 100644 index 00000000000..c0812ba7aca --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_common_vseq.sv @@ -0,0 +1,121 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_common_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_common_vseq) + + constraint num_trans_c {num_trans inside {[1 : 2]};} + `uvm_object_new + + parameter int STATE_TRANSITION_NS = 50000; + + virtual task pre_start(); + csr_excl_item csr_excl = ral.get_excl_item(); + super.pre_start(); + // In pwrmgr, random reset event can be regarded as power glitch in tb. + // Since glitch is marked as fatal and creates alert after PR#12072, + // exclude pwrmgr_reg_block.fault_status from the random reset tests + // to avoid spurious test failure. + if (common_seq_type inside {"csr_mem_rw_with_rand_reset", "stress_all_with_rand_reset"}) begin + csr_excl.add_excl("pwrmgr_reg_block.fault_status", CsrExclCheck); + expect_fatal_alerts = 1; + end + endtask + + virtual task body(); + run_common_vseq_wrapper(num_trans); + `uvm_info(`gfn, "Done with body", UVM_HIGH) + endtask : body + + task rand_reset_eor_clean_up(); + // clear wakeup at the beginning + cfg.pwrmgr_vif.update_wakeups('0); + cfg.clk_rst_vif.wait_clks(2); + + // clear interrupt + csr_wr(.ptr(ral.intr_state), .value(1)); + endtask : rand_reset_eor_clean_up + + // SVA control to handle side-effects of fault injections. + virtual function void sec_cm_fi_ctrl_svas(sec_cm_base_if_proxy if_proxy, bit enable); + if (!uvm_re_match("*.u_fsm.u_state_regs*", if_proxy.path)) begin + if (!enable) $assertoff(0, "tb.dut.pwrmgr_sec_cm_checker_assert.RomBlockActiveState_A"); + else $asserton(0, "tb.dut.pwrmgr_sec_cm_checker_assert.RomBlockActiveState_A"); + end + endfunction + + // pwrmgr has three alert events + // REG_INTG_ERR, ESC_TIMEOUT and MAIN_PD_GLITCH + // all others will trigger only reset. + // So disable wait_alert by skipping super.check_sec_cm_fi_resp() + virtual task check_sec_cm_fi_resp(sec_cm_base_if_proxy if_proxy); + string slow_st_to, fast_st_to, msg; + // to avoid 100 column cut off + slow_st_to = { + "slow state local esc chk timeout:", + "fast_state %s, pwr_ast_req.pwr_clamp %0d, pwr_ast_req.main_pd_n %0d" + }; + fast_st_to = { + "fast state local esc chk timeout:", + "pwr_rst_req.rst_lc_req %0d, pwr_rst_req.rst_sys_req %0d, pwr_clk_req %0d" + }; + + `uvm_info(`gfn, $sformatf("sec_cm_type %s", if_proxy.sec_cm_type.name), UVM_MEDIUM) + + case (if_proxy.sec_cm_type) + SecCmPrimSparseFsmFlop: begin + // if slow state is unknown, + // wait for + // fast_state == FastPwrStateInvalid + // tb.dut.pwr_ast_o.pwr_clamp == 1 + // tb.dut.pwr_ast_o.main_pd_n == 0 + // + // if fast state is unknown, + // wait for + // tb.dut.pwr_rst_o.rst_lc_req == 2'b11 + // tb.dut.pwr_rst_o.rst_sys_req == 2'b11 + // tb.dut.pwr_clk_o == 3'b0 + if (!uvm_re_match("*.u_slow_fsm.*", if_proxy.path)) begin + `uvm_info(`gfn, "detect unknown slow state", UVM_MEDIUM) + msg = $sformatf( + slow_st_to, + cfg.pwrmgr_vif.fast_state.name, + cfg.pwrmgr_vif.pwr_ast_req.pwr_clamp, + cfg.pwrmgr_vif.pwr_ast_req.main_pd_n + ); + + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateInvalid && + cfg.pwrmgr_vif.pwr_ast_req.pwr_clamp == 1 && + cfg.pwrmgr_vif.pwr_ast_rsp.main_pok == 0);, msg, STATE_TRANSITION_NS) + end + if (!uvm_re_match("*.u_fsm.*", if_proxy.path)) begin + `uvm_info(`gfn, "detect unknown fast state", UVM_MEDIUM) + msg = $sformatf( + fast_st_to, + cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req, + cfg.pwrmgr_vif.pwr_rst_req.rst_sys_req, + cfg.pwrmgr_vif.pwr_clk_req + ); + + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.pwr_rst_req.rst_lc_req == 2'b11 && + cfg.pwrmgr_vif.pwr_rst_req.rst_sys_req == 2'b11 && + cfg.pwrmgr_vif.pwr_clk_req == 3'h0);, msg, 5000) + end + end + SecCmPrimCount: begin + // wait for fast state to be FastPwrStateResetPrep + // before assert reset + `uvm_info(`gfn, "check rx_clk local esc", UVM_MEDIUM) + msg = $sformatf( + "rx clk loc esc chk timeout : fast_state %s", cfg.pwrmgr_vif.fast_state.name + ); + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep);, msg, + STATE_TRANSITION_NS) + end + default: `uvm_fatal(`gfn, $sformatf("unexpected sec_cm_type %s", if_proxy.sec_cm_type.name)) + endcase // case (if_proxy.sec_cm_type) + // This makes sure errors are not injected too close together to avoid confusion. + cfg.slow_clk_rst_vif.wait_clks(10); + endtask : check_sec_cm_fi_resp +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv new file mode 100644 index 00000000000..736bcfbb5b3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_disable_rom_integrity_check_vseq.sv @@ -0,0 +1,138 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Test multiple resets with setting lc_* inputs with random value. +class pwrmgr_disable_rom_integrity_check_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_disable_rom_integrity_check_vseq) + `uvm_object_new + + rand bit release_by_good; + rand int rom_index; + constraint rom_index_c {rom_index inside {[0:pwrmgr_reg_pkg::NumRomInputs-1]};} + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + function void post_randomize(); + sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4)); + super.post_randomize(); + endfunction + + local task detect_block(output bit blocked); + blocked = 1; + repeat (20) begin + @cfg.slow_clk_rst_vif.cb; + if (cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateActive) begin + blocked = 0; + break; + end + end + endtask + + task body(); + resets_t enabled_resets; + wait_for_rom_and_active(); + check_reset_status('0); + + for (int i = 0; i < num_trans; ++i) begin + prim_mubi_pkg::mubi4_t done; + prim_mubi_pkg::mubi4_t good; + `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + // set lc ctrl input to random value + cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val( + .t_weight(1), .f_weight(3), .other_weight(1) + ); + // Have all rom response other than rom_index okay. + for (int r = 0; r < pwrmgr_reg_pkg::NumRomInputs; ++r) begin + if (r != rom_index) + cfg.pwrmgr_vif.update_rom_ctrl('{default: prim_mubi_pkg::MuBi4True}, r); + end + cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(3), .other_weight(1)); + done = get_rand_mubi4_val(.t_weight(1), .f_weight(3), .other_weight(1)); + good = get_rand_mubi4_val(.t_weight(1), .f_weight(3), .other_weight(1)); + cfg.pwrmgr_vif.update_rom_ctrl('{done: done, good: good}, rom_index); + + `uvm_info(`gfn, $sformatf("Set done 0x%x, good 0x%x", done, good), UVM_MEDIUM) + + enabled_resets = resets_en & resets; + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b", + enabled_resets, + power_glitch_reset, + escalation_reset, + sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True, + ndm_reset + ), UVM_MEDIUM) + + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + // This is necessary to propagate reset_en. + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger resets. The glitch is sent prior to the externals since if it is delayed + // it will cause a separate reset after the externals, which complicates the checks. + if (power_glitch_reset) send_power_glitch(); + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM) + cfg.pwrmgr_vif.update_resets(resets); + `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM) + if (escalation_reset) send_escalation_reset(); + cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr); + if (ndm_reset) send_ndm_reset(); + + `uvm_info(`gfn, "Wait for Fast State NE FastPwrStateActive", UVM_MEDIUM) + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + + if (cfg.pwrmgr_vif.rom_ctrl_i[rom_index].done != prim_mubi_pkg::MuBi4True) begin + // Check fast state is not FastPwrStateActive for a while + repeat (20) begin + @cfg.slow_clk_rst_vif.cb; + `DV_CHECK_NE(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateActive) + end + + // Set done to True. + `uvm_info(`gfn, "Set rom_ctrl.done input True", UVM_MEDIUM) + cfg.pwrmgr_vif.update_rom_ctrl('{ + done: prim_mubi_pkg::MuBi4True, good: cfg.pwrmgr_vif.rom_ctrl_i[rom_index].good + }, rom_index); + cfg.slow_clk_rst_vif.wait_clks(2); + end + + if (cfg.pwrmgr_vif.rom_ctrl_i[rom_index].good != prim_mubi_pkg::MuBi4True) begin + bit blocked = 0; + detect_block(blocked); + if (blocked) begin + if (release_by_good) begin + // Set to good. + cfg.pwrmgr_vif.update_rom_ctrl('{ + done: prim_mubi_pkg::MuBi4True, good: prim_mubi_pkg::MuBi4True + }, rom_index); + end else begin + // Disable rom checks. + `uvm_info(`gfn, "Set lc ctrl inputs On", UVM_MEDIUM) + cfg.pwrmgr_vif.lc_hw_debug_en = lc_ctrl_pkg::On; + cfg.pwrmgr_vif.lc_dft_en = lc_ctrl_pkg::On; + end + end // if (blocked) + cfg.slow_clk_rst_vif.wait_clks(2); + end + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, "Back from reset", UVM_MEDIUM) + + check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0)); + + cfg.slow_clk_rst_vif.wait_clks(4); + check_reset_status('0); + + // And check interrupt is not set. + check_and_clear_interrupt(.expected(1'b0)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_disable_rom_integrity_check_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv new file mode 100644 index 00000000000..cd650a7052d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_esc_clk_rst_malfunc_vseq.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Description: +// This sequence creates escalation clock and reset malfunction at FastPwrStateActive state. +// This event will trigger timeout counter and assert timeout signal +// when timeout counter reaches EscTimeOutCnt value. +// Once the timeout occurs, it will create fatal alert and alert agent(tb) will set esc rst. +// The pass or failure status is determined in the cip scoreboard. +class pwrmgr_esc_clk_rst_malfunc_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_esc_clk_rst_malfunc_vseq) + + `uvm_object_new + constraint num_trans_c {num_trans inside {[1 : 3]};} + + virtual task body(); + wait_for_rom_and_active(); + // Wait some time so the stimulus is sent after the fast fsm becoming active. + cfg.clk_rst_vif.wait_clks(4); + expect_fatal_alerts = 1; + trigger_escalation_timeout(); + wait_for_rom_and_active(); + endtask : body + + // Trigers an escalation timeout fault, either stopping clk_esc_i or driving rst_esc_ni. + // + // Randomly set a bit to 0 or 1: if 0 stop clk_esc_i, if 1 make rst_esc_ni active. + task trigger_escalation_timeout(); + int which = $urandom_range(0, 1); + `uvm_info(`gfn, $sformatf("Triggering escalation via %0s", which ? "rst" : "clk"), UVM_MEDIUM) + if (which == 0) cfg.esc_clk_rst_vif.stop_clk(); + else cfg.esc_clk_rst_vif.drive_rst_pin(1'b0); + + // Wait for cpu fetch to be disabled, as an indication a reset is triggered. + `DV_SPINWAIT(wait (cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On);, + "timeout waiting for the CPU to be inactive", FetchEnTimeoutNs) + `uvm_info(`gfn, "Releasing trigger", UVM_MEDIUM) + if (which == 0) cfg.esc_clk_rst_vif.start_clk(); + else cfg.esc_clk_rst_vif.drive_rst_pin(1'b1); + endtask : trigger_escalation_timeout +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv new file mode 100644 index 00000000000..2c3fc6d121f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_escalation_timeout_vseq.sv @@ -0,0 +1,88 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Description: +// This test checks that an escalation reset is generated when the escalation clock stops for +// enough cycles. +class pwrmgr_escalation_timeout_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_escalation_timeout_vseq) + + `uvm_object_new + + // The following two parameters are used to determine when to perform checks. + + // The number of clock cycles with a stopped escalation clock before raising escalation is 128. + // But the logic can wait for up to 7 more cycles before it starts the counter, and there is + // some additional fast clock cycles of delay in the logic that triggers the escalation to + // be signalled. This adds 12 extra cycles to be conservative. + localparam int EscTimeoutMainClkThreshold = 128 + 7 + 12; + + // In addition, there is a clock domain crossing to the slow clock, which can add a couple slow + // clocks cycles plus an extra cycle for the input to meet the next clock cycle. + localparam int EscTimeoutSlowClkThreshold = 2 + 1; + + int trans_cnt = 0; + constraint num_trans_c {num_trans inside {[1 : 5]};} + + // This stops the escalation clock for a certain number of cycles, and + // checks a reset occurs or not, depending on expect_reset. + task check_stopped_esc_clk(int stop_cycles, bit expect_reset); + fork + begin + `uvm_info(`gfn, $sformatf( + "Stopping escalation clock for %0d cycles %s expecting reset", + stop_cycles, expect_reset ? "" : "not "), + UVM_MEDIUM) + cfg.esc_clk_rst_vif.stop_clk(); + // The clock will be restarted while handling a reset, so no need to restart it here. + if (!expect_reset) begin + cfg.clk_rst_vif.wait_clks(stop_cycles); + `uvm_info(`gfn, "Restarting escalation clock", UVM_MEDIUM) + cfg.esc_clk_rst_vif.start_clk(); + cfg.esc_clk_rst_vif.wait_clks(4000); + end + end + begin + if (expect_reset) begin + // The expectation is to create an outgoing reset request, disable cpu fetching, and the + // reset cause to indicate a hardware request. + // Turn the cycle counts into a number of nanoseconds for waiting with timeout. + // The clk_rst_vifs give the period in pico seconds so divide by 1000. + int wait_ns = (EscTimeoutMainClkThreshold * cfg.clk_rst_vif.clk_period_ps + + EscTimeoutSlowClkThreshold * cfg.slow_clk_rst_vif.clk_period_ps) / 1000; + `DV_SPINWAIT( + wait(cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On && + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[pwrmgr_reg_pkg::ResetEscIdx] == 1'b1 && + cfg.pwrmgr_vif.pwr_rst_req.reset_cause == pwrmgr_pkg::HwReq); + `uvm_info(`gfn, "escalation reset completed", UVM_LOW), + "escalation reset was not completed as expected", wait_ns) + end else begin + repeat (8000) begin + cfg.clk_rst_vif.wait_clks(1); + if (cfg.pwrmgr_vif.fetch_en != lc_ctrl_pkg::On) begin + `uvm_error(`gfn, "Unexpected cpu fetch disable, indicating a reset") + end + end + end + end + join + endtask + + virtual task body(); + wait_for_rom_and_active(); + cfg.slow_clk_rst_vif.set_freq_mhz(1); + cfg.esc_clk_rst_vif.wait_clks(200); + // The timeout is not accurately predictable for two reasons: + // - The initial count for the timeout can be from 0 to 7, which means the timeout could + // happen between 121 and 128 cycles after the clock. + // - The timeout has a req-ack synchronizer which has some randomness due to the phase. + // This adds a few more cycles of uncertainty. + // Keep the clock stopped for less than 118 cycles should be safe to avoid an alert. + check_stopped_esc_clk(118, 1'b0); + check_stopped_esc_clk(2000, 1'b1); + wait_for_rom_and_active(); + check_stopped_esc_clk(136, 1'b1); + endtask : body + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv new file mode 100644 index 00000000000..b7369f188ab --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_glitch_vseq.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// This test asserts glitch to power_reset and see +// dut can recover gracefully. +class pwrmgr_glitch_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_glitch_vseq) + + `uvm_object_new + + int trans_cnt = 0; + constraint num_trans_c {num_trans inside {[1 : 5]};} + + virtual task body(); + expect_fatal_alerts = 1; + for (int i = 0; i < num_trans; ++i) begin + wait_for_rom_and_active(); + cfg.clk_rst_vif.wait_clks(4); + + fork + send_power_glitch(); + begin + cfg.pwrmgr_vif.update_ast_main_pok(0); + cfg.slow_clk_rst_vif.wait_clks(2); + cfg.pwrmgr_vif.update_ast_main_pok(1); + end + join + + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == pwrmgr_pkg::FastPwrStateResetPrep && + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[2] == 1);, $sformatf( + "checker timeout : fast_state %s, pwr_rst_req 0x%x", + cfg.pwrmgr_vif.fast_state.name, + cfg.pwrmgr_vif.pwr_rst_req.rstreqs + ), 10000) + + dut_init(); + end + endtask : body +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv new file mode 100644 index 00000000000..1209fa591b8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_global_esc_vseq.sv @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// This test asserts global escalation reset to dut +// and check global escalation request is handled by +// dut properly. +class pwrmgr_global_esc_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_global_esc_vseq) + + `uvm_object_new + + int trans_cnt = 0; + constraint num_trans_c {num_trans inside {[1 : 5]};} + + virtual task body(); + fork + send_esc(); + check_rst_req(); + join + endtask : body + + task send_esc(); + int cycle; + for (int i = 0; i < num_trans; ++i) begin + wait_for_fast_fsm(FastFsmActive); + cycle = $urandom_range(50, 300); + send_escalation_reset(); + repeat (cycle) @(cfg.clk_rst_vif.cb); + clear_escalation_reset(); + end + endtask : send_esc + + task check_rst_req(); + bit dut_init_done = -1; + + while (trans_cnt < num_trans) begin + @(cfg.clk_rst_vif.cb); + wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive && + cfg.pwrmgr_vif.pwr_rst_req.rstreqs[3] == 1'b1); + trans_cnt++; + + // Make sure previous dut_init is done + if (dut_init_done > -1) begin + wait(dut_init_done == 1); + end + // Spawning dut_init thread then go to + // wait reset state + fork + begin + dut_init_done = 0; + dut_init(); + dut_init_done = 1; + end + begin + cfg.clk_rst_vif.wait_clks(10); + end + join_any + end + wait(dut_init_done == 1); + endtask : check_rst_req + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv new file mode 100644 index 00000000000..37142e26832 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_invalid_vseq.sv @@ -0,0 +1,141 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The test to create transition to invalid state from any lowpower transitions. +class pwrmgr_lowpower_invalid_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_lowpower_invalid_vseq) + `uvm_object_new + + // Create enum to map rtl local sparse state + // to continuous dv state. + typedef enum bit [3:0] { + DVWaitDisClks = 0, + DVWaitFallThrough = 1, + DVWaitNvmIdleChk = 2, + DVWaitLowPowerPrep = 3, + DVWaitReqPwrDn = 4, + DVWaitLowPower = 5, + DVWaitEnableClocks = 6, + DVWaitReleaseLcRst = 7, + DVWaitOtpInit = 8, + DVWaitLcInit = 9, + DVWaitAckPwrUp = 10, + DVWaitRomCheck = 11, + DVWaitStrap = 12, + DVWaitActive = 13, + DVWaitInvalid = 14 + } reset_index_e; + + constraint wakeups_c {wakeups != 0;} + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + task body(); + reset_index_e reset_index; + resets_t enabled_resets; + string path = "tb.dut.u_fsm.fsm_invalid_i"; + int num_of_target_states = 4; + + // Spurious interrupt check can be executed by + // residue of lowpower task. Since we cannot kill csr op + // by disable fork, we have to disable spurious interrup check. + cfg.invalid_st_test = 1; + + wait_for_rom_and_active(); + `uvm_info(`gfn, "At body start", UVM_MEDIUM) + check_wake_status('0); + reset_index = DVWaitFallThrough; + + for (int i = 0; i < num_of_target_states; ++i) begin + `uvm_info(`gfn, $sformatf("Starting new round %0d %s", i, reset_index.name), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + fork + start_lowpower_transition(); + begin + int wait_time_ns = 10000; + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == dv2rtl_st(reset_index));, $sformatf( + "Timed out waiting for state %s", reset_index.name), wait_time_ns) + + @cfg.clk_rst_vif.cbn; + `DV_CHECK(uvm_hdl_force(path, 1)) + `uvm_info(`gfn, "Injected invalid slow state", UVM_MEDIUM) + @cfg.clk_rst_vif.cb; + end + join_any + @cfg.clk_rst_vif.cb; + `DV_CHECK(uvm_hdl_release(path)) + `DV_CHECK(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateInvalid) + + repeat (10) @cfg.clk_rst_vif.cb; + + apply_reset(); + reset_index = reset_index.next(); + wait_for_fast_fsm(FastFsmActive); + `uvm_info(`gfn, $sformatf("Done with round %0d", i), UVM_MEDIUM) + end // for (int i = 0; i < 4; ++i) + endtask + + task start_lowpower_transition(); + wakeups_t enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + low_power_hint = 1; + update_control_csr(); + + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM) + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + set_nvms_idle(); + + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + + if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + end + + // Now bring it back. + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + // wakeups should be registered. + cfg.pwrmgr_vif.update_wakeups('1); + + wait_for_rom_and_active(); + `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM) + endtask : start_lowpower_transition + + function pwrmgr_pkg::fast_pwr_state_e dv2rtl_st(reset_index_e idx); + case (idx) + DVWaitDisClks: return pwrmgr_pkg::FastPwrStateDisClks; + DVWaitFallThrough: return pwrmgr_pkg::FastPwrStateFallThrough; + DVWaitNvmIdleChk: return pwrmgr_pkg::FastPwrStateNvmIdleChk; + DVWaitLowPowerPrep: return pwrmgr_pkg::FastPwrStateLowPowerPrep; + DVWaitReqPwrDn: return pwrmgr_pkg::FastPwrStateReqPwrDn; + DVWaitLowPower: return pwrmgr_pkg::FastPwrStateLowPower; + DVWaitEnableClocks: return pwrmgr_pkg::FastPwrStateEnableClocks; + DVWaitReleaseLcRst: return pwrmgr_pkg::FastPwrStateReleaseLcRst; + DVWaitOtpInit: return pwrmgr_pkg::FastPwrStateOtpInit; + DVWaitLcInit: return pwrmgr_pkg::FastPwrStateLcInit; + DVWaitAckPwrUp: return pwrmgr_pkg::FastPwrStateAckPwrUp; + DVWaitRomCheck: return pwrmgr_pkg::FastPwrStateRomCheckDone; + DVWaitStrap: return pwrmgr_pkg::FastPwrStateStrap; + DVWaitActive: return pwrmgr_pkg::FastPwrStateActive; + DVWaitInvalid: return pwrmgr_pkg::FastPwrStateInvalid; + default: begin + `uvm_error("dv2rma_st", $sformatf("unknown index:%0d", idx)) + end + endcase + endfunction : dv2rtl_st + +endclass : pwrmgr_lowpower_invalid_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv new file mode 100644 index 00000000000..d4ad00db0dd --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_lowpower_wakeup_race_vseq.sv @@ -0,0 +1,143 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The lowpower_wakeup race test randomly enables wakeups, info capture, and interrupts, +// and sends wakeups in the temporal vecinity of low power entry. It also sends wakeups +// after wakeup processing starts. +class pwrmgr_lowpower_wakeup_race_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_lowpower_wakeup_race_vseq) + + `uvm_object_new + + constraint wakeups_c {wakeups != 0;} + + rand bit keep_prior_wake_info; + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + rand int cycles_before_early_wakeup; + rand int cycles_before_transition; + constraint cycles_racing_c { + cycles_before_early_wakeup inside {[2 : 8]}; + cycles_before_transition inside {[2 : 8]}; + } + + task body(); + logic [TL_DW-1:0] value; + wakeups_t prior_reasons = '0; + bit prior_fall_through = '0; + bit prior_abort = '0; + wait_for_rom_and_active(); + + check_wake_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", wakeups_en & wakeups), UVM_MEDIUM) + + if (keep_prior_wake_info) begin + csr_rd(.ptr(ral.wake_info.reasons), .value(prior_reasons)); + csr_rd(.ptr(ral.wake_info.fall_through), .value(prior_fall_through)); + csr_rd(.ptr(ral.wake_info.abort), .value(prior_abort)); + end else begin + clear_wake_info(); + prior_reasons = '0; + prior_fall_through = '0; + prior_abort = '0; + end + `uvm_info(`gfn, $sformatf( + "Prior wake_info: reasons=0x%x, fall_through=%b, abort=%b", + prior_reasons, + prior_fall_through, + prior_abort + ), UVM_MEDIUM) + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + + low_power_hint = 1'b1; + update_control_csr(); + + set_nvms_idle(); + + // This will send the wakeup and trigger low power entry so they almost coincide. + fork + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_transition); + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + end + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_early_wakeup); + // Send the wakeups. + cfg.pwrmgr_vif.update_wakeups(wakeups); + end + join + + wait_for_fast_fsm(FastFsmInactive); + + fork + wait_for_rom_and_active(); + begin + // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset. + // This read will not work in the chip, since the processor will be asleep. + // We wait until the cycle following the fast fsm lc_rst release. + if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin + wait_for_lc_rst_release(); + check_wake_status(wakeups & wakeups_en); + `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", wakeups & wakeups_en), UVM_MEDIUM) + end + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + // Send more wakeups to make sure they are reported in CSRs. With this all enabled + // wakeups should be registered. + cfg.pwrmgr_vif.update_wakeups('1); + end + join + `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM) + + // make this check parallel. + // to avoid csr rd blocking later status read request and + // miss status update window. + @cfg.clk_rst_vif.cb; + fork + begin + fast_check_reset_status(0); + end + begin + fast_check_wake_info(.reasons(wakeups_en), .prior_reasons(prior_reasons), + .fall_through(1'b0), .abort(1'b0), + .prior_fall_through(prior_fall_through), .prior_abort(prior_abort)); + end + join + `uvm_info(`gfn, "done with checks for reset and wakeup", UVM_MEDIUM) + // This is the expected side-effect of the low power entry reset, since the source of the + // non-aon wakeup sources will deassert it as a consequence of their reset. + // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups + // will remain active, preventing the device from going to sleep. + cfg.pwrmgr_vif.update_wakeups('0); + cfg.slow_clk_rst_vif.wait_clks(10); + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + + // wait for clock is on + cfg.clk_rst_vif.wait_clks(10); + + check_wake_status('0); + + // Wait for interrupt to be generated whether or not it is enabled. + cfg.slow_clk_rst_vif.wait_clks(10); + `uvm_info(`gfn, "in check_and_clear_interrupt", UVM_MEDIUM) + check_and_clear_interrupt(.expected(1'b1)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_lowpower_wakeup_race_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv new file mode 100644 index 00000000000..89457487947 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_repeat_wakeup_reset_vseq.sv @@ -0,0 +1,64 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// The wakeup_reset test randomly enables wakeups and resets, info capture, and interrupts, +// and sends wakeups and resets in close temporal proximity at random times. +class pwrmgr_repeat_wakeup_reset_vseq extends pwrmgr_wakeup_reset_vseq; + `uvm_object_utils(pwrmgr_repeat_wakeup_reset_vseq) + + `uvm_object_new + + bit [lc_ctrl_pkg::TxWidth-1:0] bad_lc_tx; + + int cycles_from_reset; + int micros_to_release; + + bit super_sequence_done; + + task body(); + num_trans_c.constraint_mode(0); + num_trans = 50; + super_sequence_done = 0; + + control_rom_ctrl_sync_assertions(.enable(1'b0)); + fork + begin + super.body(); + super_sequence_done = 1; + end + drv_stim(mubi_mode); + join + endtask : body + + task drv_stim(pwrmgr_mubi_e mubi_mode); + if (mubi_mode == PwrmgrMubiLcCtrl) drv_lc_ctrl(); + endtask : drv_stim + + task drv_lc_ctrl(); + int delay; + + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(cycles_from_reset, cycles_from_reset inside {[2 : 8]};) + `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(micros_to_release, micros_to_release inside {[2 : 4]};) + + repeat (50) begin : repeat_50 + wait(cfg.esc_clk_rst_vif.rst_n); + cfg.clk_rst_vif.wait_clks(cycles_from_reset); + if (super_sequence_done) begin + `uvm_info(`gfn, "Break from drv_lc_ctrl", UVM_MEDIUM) + break; + end + `uvm_info(`gfn, "Injection to lc_hw_debug_en", UVM_MEDIUM) + cfg.pwrmgr_vif.lc_hw_debug_en = get_rand_lc_tx_val( + .t_weight(1), .f_weight(1), .other_weight(2) + ); + #(micros_to_release * 1us); + `uvm_info(`gfn, "Injection to lc_dft_en", UVM_MEDIUM) + if (super_sequence_done) break; + cfg.pwrmgr_vif.lc_dft_en = get_rand_lc_tx_val(.t_weight(1), .f_weight(1), .other_weight(2)); + #(micros_to_release * 1us); + end : repeat_50 + `uvm_info(`gfn, "ended drv_lc_ctrl", UVM_MEDIUM) + endtask : drv_lc_ctrl + +endclass : pwrmgr_repeat_wakeup_reset_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv new file mode 100644 index 00000000000..f95576d3564 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv @@ -0,0 +1,129 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The test to create transition to invalid state from any reset transitions. +class pwrmgr_reset_invalid_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_reset_invalid_vseq) + `uvm_object_new + + // Create enum to map rtl local sparse state + // to continuous dv state. + typedef enum bit [3:0] { + DVWaitDisClks = 0, + DVWaitNvmShutDown = 1, + DVWaitResetPrep = 2, + DVWaitLowPower = 3, + DVWaitEnableClocks = 4, + DVWaitReleaseLcRst = 5, + DVWaitOtpInit = 6, + DVWaitLcInit = 7, + DVWaitAckPwrUp = 8, + DVWaitRomCheck = 9, + DVWaitStrap = 10, + DVWaitActive = 11, + DVWaitInvalid = 12 + } reset_index_e; + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + function void post_randomize(); + sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4)); + super.post_randomize(); + endfunction + + task body(); + reset_index_e reset_index; + resets_t enabled_resets; + string path = "tb.dut.u_fsm.fsm_invalid_i"; + int num_of_target_states = 11; + + wait_for_rom_and_active(); + check_reset_status('0); + $assertoff(0, "tb.dut.u_cdc.u_clr_reqack.SyncReqAckHoldReq"); + + for (int i = 0; i < num_of_target_states; ++i) begin + `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + fork + create_any_reset_event(); + begin + int wait_time_ns = 20000; + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state == dv2rtl_st(reset_index));, $sformatf( + "Timed out waiting for state %s", reset_index.name), wait_time_ns) + + @cfg.clk_rst_vif.cbn; + `uvm_info(`gfn, $sformatf("Will cause invalid state forcing %s = 1", path), UVM_MEDIUM) + `DV_CHECK(uvm_hdl_force(path, 1)) + @cfg.clk_rst_vif.cb; + end + join + @cfg.clk_rst_vif.cb; + `DV_CHECK(uvm_hdl_release(path)) + `DV_CHECK(cfg.pwrmgr_vif.fast_state, pwrmgr_pkg::FastPwrStateInvalid) + `uvm_info(`gfn, "All good, resetting for next round", UVM_MEDIUM) + repeat (10) @cfg.clk_rst_vif.cb; + apply_reset(); + reset_index = reset_index.next(); + wait_for_fast_fsm(FastFsmActive); + end + endtask + + task create_any_reset_event(); + resets_t enabled_resets = resets_t'(resets_en & resets); + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b", + enabled_resets, + power_glitch_reset, + escalation_reset, + sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True, + ndm_reset + ), UVM_MEDIUM) + + `uvm_info(`gfn, "Trying to write to reset_en CSR", UVM_MEDIUM) + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + // This is necessary to propagate reset_en. + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger resets. The glitch is sent prior to the externals since if it is delayed + // it will cause a separate reset after the externals, which complicates the checks. + if (power_glitch_reset) send_power_glitch(); + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + if (cycles_before_reset == 0) enabled_resets = 0; + + `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM) + cfg.pwrmgr_vif.update_resets(resets); + `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM) + if (escalation_reset) send_escalation_reset(); + if (ndm_reset) send_ndm_reset(); + cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr); + + endtask : create_any_reset_event + + function pwrmgr_pkg::fast_pwr_state_e dv2rtl_st(reset_index_e idx); + case (idx) + DVWaitDisClks: return pwrmgr_pkg::FastPwrStateDisClks; + DVWaitNvmShutDown: return pwrmgr_pkg::FastPwrStateNvmShutDown; + DVWaitResetPrep: return pwrmgr_pkg::FastPwrStateResetPrep; + DVWaitLowPower: return pwrmgr_pkg::FastPwrStateLowPower; + DVWaitEnableClocks: return pwrmgr_pkg::FastPwrStateEnableClocks; + DVWaitReleaseLcRst: return pwrmgr_pkg::FastPwrStateReleaseLcRst; + DVWaitOtpInit: return pwrmgr_pkg::FastPwrStateOtpInit; + DVWaitLcInit: return pwrmgr_pkg::FastPwrStateLcInit; + DVWaitAckPwrUp: return pwrmgr_pkg::FastPwrStateAckPwrUp; + DVWaitRomCheck: return pwrmgr_pkg::FastPwrStateRomCheckDone; + DVWaitStrap: return pwrmgr_pkg::FastPwrStateStrap; + DVWaitActive: return pwrmgr_pkg::FastPwrStateActive; + DVWaitInvalid: return pwrmgr_pkg::FastPwrStateInvalid; + default: begin + `uvm_error("dv2rma_st", $sformatf("unknown index:%0d", idx)) + end + endcase + endfunction : dv2rtl_st + +endclass : pwrmgr_reset_invalid_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv new file mode 100644 index 00000000000..0b61cb797ee --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_vseq.sv @@ -0,0 +1,79 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The reset test randomly introduces external resets, ndm resets, power glitches, and escalation +// resets. +class pwrmgr_reset_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_reset_vseq) + `uvm_object_new + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + function void post_randomize(); + sw_rst_from_rstmgr = get_rand_mubi4_val(.t_weight(8), .f_weight(4), .other_weight(4)); + super.post_randomize(); + endfunction + + task body(); + logic [TL_DW-1:0] value; + resets_t enabled_resets; + wait_for_rom_and_active(); + + check_reset_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + enabled_resets = resets_en & resets; + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, escalation=%b, sw_reset=%b, ndm_reset=%b", + enabled_resets, + power_glitch_reset, + escalation_reset, + sw_rst_from_rstmgr == prim_mubi_pkg::MuBi4True, + ndm_reset + ), UVM_MEDIUM) + + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + // This is necessary to propagate reset_en, and it needs a couple additional slow + // clock cycles for a synchronizer to be ready to mask incoming resets. + wait_for_csr_to_propagate_to_slow_domain(); + cfg.slow_clk_rst_vif.wait_clks(2); + + // Trigger resets. The glitch is sent prior to the externals since if it is delayed + // it will cause a separate reset after the externals, which complicates the checks. + if (power_glitch_reset) send_power_glitch(); + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + + `uvm_info(`gfn, $sformatf("Sending resets=0x%x", resets), UVM_MEDIUM) + cfg.pwrmgr_vif.update_resets(resets); + `uvm_info(`gfn, $sformatf("Sending sw reset from rstmgr=%b", sw_rst_from_rstmgr), UVM_MEDIUM) + if (escalation_reset) begin + send_escalation_reset(); + // Wait for the alert to propagate to fault_status? + end + cfg.pwrmgr_vif.update_sw_rst_req(sw_rst_from_rstmgr); + if (ndm_reset) send_ndm_reset(); + + // Expect to start reset. + `DV_WAIT(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive) + `uvm_info(`gfn, "Started to process reset", UVM_MEDIUM) + + wait_for_rom_and_active(); + `uvm_info(`gfn, "Back from reset", UVM_MEDIUM) + + check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0)); + + cfg.slow_clk_rst_vif.wait_clks(4); + check_reset_status('0); + + // And check interrupt is not set. + check_and_clear_interrupt(.expected(1'b0)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_reset_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv new file mode 100644 index 00000000000..b8682b1b3c6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Decription: +// Create low power transition and wakeup a few times. +// When PWRMGR.CONTROL.LOW_POWER_HINT is set and core_sleep is high, +// issue random write to PWRMGR.CONTROL and check +// PWRMGR.CONTROL value is not changed, except for LOW_POWER_HINT. +class pwrmgr_sec_cm_ctrl_config_regwen_vseq extends pwrmgr_wakeup_vseq; + `uvm_object_utils(pwrmgr_sec_cm_ctrl_config_regwen_vseq) + + `uvm_object_new + + virtual task pre_start(); + super.pre_start(); + cfg.disable_csr_rd_chk = 1; + endtask : pre_start + + task proc_illegal_ctrl_access(); + uvm_reg_data_t wdata, expdata, compare_mask; + // CONTROL.LOW_POWER_HINT is hardware-writeable, so mask it from checking. + // It gets cleared very quickly. + compare_mask = '1; + compare_mask = compare_mask - ral.control.low_power_hint.get_field_mask(); + + cfg.clk_rst_vif.wait_clks(1); + wait(cfg.pwrmgr_vif.lowpwr_cfg_wen == 0); + + repeat ($urandom_range(1, 5)) begin + `DV_CHECK_STD_RANDOMIZE_FATAL(wdata) + expdata = ral.control.get(); + `uvm_info(`gfn, $sformatf("csr start %x", ral.control.get()), UVM_HIGH) + csr_wr(.ptr(ral.control), .value(wdata)); + csr_rd_check(.ptr(ral.control), .compare_value(expdata), .compare_mask(compare_mask)); + `uvm_info(`gfn, "csr done", UVM_HIGH) + end + endtask : proc_illegal_ctrl_access + + virtual task initiate_low_power_transition(); + super.initiate_low_power_transition(); + // The access checks can only happen if the bus is powered and the clock + // is active. + if ((ral.control.main_pd_n.get_mirrored_value() == 1'b1) && + (ral.control.io_clk_en.get_mirrored_value() == 1'b1)) begin + proc_illegal_ctrl_access(); + end + endtask +endclass : pwrmgr_sec_cm_ctrl_config_regwen_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv new file mode 100644 index 00000000000..090b7ff42cc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_smoke_vseq.sv @@ -0,0 +1,88 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The smoke test brings the pwrmgr through a POR reset, followed by a low +// power sequence, followed by reset. + +// smoke test vseq +class pwrmgr_smoke_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_smoke_vseq) + + `uvm_object_new + constraint cycles_before_rst_lc_src_c {cycles_before_rst_lc_src inside {[1 : 2]};} + constraint cycles_before_otp_done_c {cycles_before_otp_done inside {[1 : 2]};} + constraint cycles_before_lc_done_c {cycles_before_lc_done inside {[1 : 2]};} + + constraint wakeups_c {wakeups != 0;} + constraint resets_c {resets != 0;} + + constraint control_enables_c { + control_enables.main_clk_en == ral.control.core_clk_en.get_reset(); + control_enables.io_clk_en == ral.control.io_clk_en.get_reset(); + control_enables.main_pd_n == ral.control.main_pd_n.get_reset(); + } + + task body(); + logic [TL_DW-1:0] value; + wakeups_t wakeup_en; + resets_t reset_en; + wait_for_rom_and_active(); + set_nvms_idle(); + setup_interrupt(.enable(1'b1)); + + check_wake_status('0); + check_reset_status('0); + + // Enable all wakeups so any peripheral can cause a wakeup. + wakeup_en = '1; + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeup_en)); + + low_power_hint = 1'b1; + update_control_csr(); + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + + // Now bring it back. + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + + wait_for_rom_and_active(); + `uvm_info(`gfn, "smoke back from wakeup", UVM_MEDIUM) + + check_wake_status(wakeups & wakeup_en); + check_reset_status('0); + // And make the cpu active. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + + cfg.pwrmgr_vif.update_wakeups('0); + check_and_clear_interrupt(.expected(1'b1)); + + // Enable resets. + reset_en = '1; + csr_wr(.ptr(ral.reset_en[0]), .value(reset_en)); + wait_for_csr_to_propagate_to_slow_domain(); + + // Trigger a reset. + cfg.pwrmgr_vif.update_resets(resets); + cfg.slow_clk_rst_vif.wait_clks(2); + wait_for_reset_cause(pwrmgr_pkg::HwReq); + + // Now bring it back: the slow fsm doesn't participate on this, so we cannot + // rely on the ctrl_cfg_regwen CSR. Wait for the reset status to clear. + wait_for_rom_and_active(); + + // The reset_status CSR should be clear since the unit requesting reset + // should have been reset, so the incoming reset should have cleared. + check_reset_status('0); + check_wake_status('0); + clear_wake_info(); + + // Wait for interrupt to be generated whether or not it is enabled. + cfg.slow_clk_rst_vif.wait_clks(10); + check_and_clear_interrupt(.expected(1'b0)); + endtask + +endclass : pwrmgr_smoke_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv new file mode 100644 index 00000000000..a088b2975b2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_stress_all_vseq.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all pwrmgr seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +class pwrmgr_stress_all_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_stress_all_vseq) + + `uvm_object_new + + task body(); + string seq_names[] = { + "pwrmgr_aborted_low_power_vseq", + "pwrmgr_lowpower_wakeup_race_vseq", + "pwrmgr_reset_vseq", + "pwrmgr_smoke_vseq", + "pwrmgr_wakeup_reset_vseq", + "pwrmgr_wakeup_vseq" + }; + + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + pwrmgr_base_vseq pwrmgr_vseq; + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(pwrmgr_vseq, seq) + + pwrmgr_vseq.do_apply_reset = 1; + pwrmgr_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(pwrmgr_vseq) + `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, pwrmgr_vseq.get_name()), + UVM_MEDIUM) + + pwrmgr_vseq.start(p_sequencer); + `uvm_info(`gfn, $sformatf( + "End of sequence %0s with seq_idx = %0d", pwrmgr_vseq.get_name(), seq_idx), + UVM_MEDIUM) + end + endtask : body +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv new file mode 100644 index 00000000000..1a7411f9254 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_sw_reset_vseq.sv @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// The reset test randomly introduces external resets. +class pwrmgr_sw_reset_vseq extends pwrmgr_base_vseq; + + `uvm_object_utils(pwrmgr_sw_reset_vseq) + `uvm_object_new + + constraint wakeups_c {wakeups == 0;} + constraint wakeups_en_c {wakeups_en == 0;} + + task body(); + int exp_rst; + wait_for_rom_and_active(); + + check_reset_status('0); + num_trans_c.constraint_mode(0); + num_trans = 30; + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + cfg.pwrmgr_vif.sw_rst_req_i = prim_mubi_pkg::mubi4_t'($urandom_range(0, 15)); + exp_rst = (cfg.pwrmgr_vif.sw_rst_req_i == prim_mubi_pkg::MuBi4True); + cfg.slow_clk_rst_vif.wait_clks(4); + + // sw reset causes fast state machine transition to lowpower state + if (exp_rst == 1) begin + `DV_SPINWAIT(wait(cfg.pwrmgr_vif.fast_state != pwrmgr_pkg::FastPwrStateActive);, + "timeout waiting for non fast-active state", 1000) + end + + // This read is not always possible since the CPU may be off. + + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + wait_for_rom_and_active(); + `uvm_info(`gfn, "Back from reset", UVM_MEDIUM) + + check_wake_info(.reasons('0), .fall_through(1'b0), .abort(1'b0)); + + cfg.slow_clk_rst_vif.wait_clks(4); + check_reset_status('0); + + // And check interrupt is not set. + check_and_clear_interrupt(.expected(1'b0)); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_sw_reset_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv new file mode 100644 index 00000000000..bc09a19a037 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_vseq_list.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "pwrmgr_base_vseq.sv" +`include "pwrmgr_aborted_low_power_vseq.sv" +`include "pwrmgr_lowpower_wakeup_race_vseq.sv" +`include "pwrmgr_reset_vseq.sv" +`include "pwrmgr_smoke_vseq.sv" +`include "pwrmgr_stress_all_vseq.sv" +`include "pwrmgr_wakeup_reset_vseq.sv" +`include "pwrmgr_wakeup_vseq.sv" +`include "pwrmgr_common_vseq.sv" +`include "pwrmgr_repeat_wakeup_reset_vseq.sv" +`include "pwrmgr_sw_reset_vseq.sv" +`include "pwrmgr_esc_clk_rst_malfunc_vseq.sv" +`include "pwrmgr_sec_cm_ctrl_config_regwen_vseq.sv" +`include "pwrmgr_global_esc_vseq.sv" +`include "pwrmgr_escalation_timeout_vseq.sv" +`include "pwrmgr_glitch_vseq.sv" +`include "pwrmgr_disable_rom_integrity_check_vseq.sv" +`include "pwrmgr_reset_invalid_vseq.sv" +`include "pwrmgr_lowpower_invalid_vseq.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv new file mode 100644 index 00000000000..069e7592bb5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_reset_vseq.sv @@ -0,0 +1,138 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The wakeup_reset test randomly enables wakeups and resets, info capture, and interrupts, +// and sends wakeups and resets in close temporal proximity at random times. +// Notice it makes no sense to send escalation reset requests while in low +// power, when the clocks are stopped, or while the system is already in reset +// since escalation should not be triggered with reset active. +class pwrmgr_wakeup_reset_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_wakeup_reset_vseq) + + `uvm_object_new + + constraint wakeups_c {wakeups != 0;} + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + (wakeups_en & wakeups) != 0; + } + constraint disable_wakeup_capture_c {disable_wakeup_capture == 1'b0;} + + // Disabling escalation resets per comment above. + constraint escalation_reset_c {escalation_reset == 0;} + + task body(); + logic [TL_DW-1:0] value; + resets_t enabled_resets; + wakeups_t enabled_wakeups; + + wait_for_rom_and_active(); + + check_reset_status('0); + check_wake_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + setup_interrupt(.enable(en_intr)); + + // Enable resets. + enabled_resets = resets_en & resets; + `uvm_info(`gfn, $sformatf( + "Enabled resets=0x%x, power_reset=%b, sw_reset=%b", + enabled_resets, + power_glitch_reset, + sw_rst_from_rstmgr + ), UVM_MEDIUM) + csr_wr(.ptr(ral.reset_en[0]), .value(resets_en)); + + // Enable wakeups. + enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf("Enabled wakeups=0x%x", enabled_wakeups), UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + clear_wake_info(); + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + + low_power_hint = 1'b1; + update_control_csr(); + + // Initiate low power transition. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + set_nvms_idle(); + // Wait for the slow state machine to be in low power. + wait(cfg.pwrmgr_vif.slow_state == pwrmgr_pkg::SlowPwrStateLowPower); + // This will send the wakeup and reset so they almost coincide. + // at low power state, do not use clk_rst_vif, cause it is off. + fork + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_reset); + cfg.pwrmgr_vif.update_resets(resets); + + if (power_glitch_reset) begin + send_power_glitch(); + enabled_resets = 0; + end + `uvm_info(`gfn, $sformatf("Sending reset=%b, power_glitch=%b", resets, power_glitch_reset + ), UVM_MEDIUM) + end + + begin + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + `uvm_info(`gfn, $sformatf("Sending wakeup=%b", wakeups), UVM_MEDIUM) + end + join + + if (cfg.en_cov) begin + cov.reset_wakeup_distance_cg.sample(cycles_before_reset - cycles_before_wakeup); + end + // randomize_roms_response has some waits, and so does the code to check wake_status, + // so we fork them to avoid conflicts. + fork + begin + // At lowpower state, wait for clock comes back before check any csr + @cfg.clk_rst_vif.cb; + // Check wake_status prior to actual wakeup, since the wakeup request will be reset. + fast_check_wake_status(enabled_wakeups); + `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", enabled_wakeups), UVM_MEDIUM) + end + randomize_roms_response(); + join + wait_for_fast_fsm(FastFsmActive); + + check_reset_status('0); + + check_wake_info(.reasons(enabled_wakeups), .prior_reasons(1'b0), .fall_through(1'b0), + .prior_fall_through(1'b0), .abort(1'b0), .prior_abort(1'b0)); + // This is the expected side-effect of the low power entry reset, since the source of the + // non-aon wakeup sources will deassert it as a consequence of their reset. + // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups + // will remain active, preventing the device from going to sleep. + cfg.pwrmgr_vif.update_wakeups('0); + cfg.slow_clk_rst_vif.wait_clks(10); + check_reset_status('0); + check_wake_status('0); + + cfg.slow_clk_rst_vif.wait_clks(10); + // An interrupt will be generated depending on the exact timing of the slow fsm getting + // the reset and wakeup. We choose not to predict it here (it is checked on other tests). + // Instead, we just check if the interrupt status is asserted and it is enabled the + // output interrupt is active. + check_and_clear_interrupt(.expected(1'b1), .check_expected('0)); + // Clear hardware resets: if they are enabled they are cleared when rst_lc_req[1] goes active, + // but this makes sure they are cleared even if none is enabled for the next round. + cfg.pwrmgr_vif.update_resets('0); + // And make the cpu active. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + end + clear_wake_info(); + endtask + +endclass : pwrmgr_wakeup_reset_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv new file mode 100644 index 00000000000..921d17c44b2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_wakeup_vseq.sv @@ -0,0 +1,130 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// The wakeup test randomly enables wakeups, info capture, and interrupts, +// and sends wakeups at random times. +class pwrmgr_wakeup_vseq extends pwrmgr_base_vseq; + `uvm_object_utils(pwrmgr_wakeup_vseq) + + `uvm_object_new + + constraint wakeups_c {wakeups != 0;} + + rand bit keep_prior_wake_info; + + constraint wakeup_en_c { + solve wakeups before wakeups_en; + |(wakeups_en & wakeups) == 1'b1; + } + + task body(); + logic [TL_DW-1:0] value; + wakeups_t enabled_wakeups; + wakeups_t prior_reasons = '0; + bit prior_fall_through = '0; + bit prior_abort = '0; + + wait_for_rom_and_active(); + check_wake_status('0); + for (int i = 0; i < num_trans; ++i) begin + `uvm_info(`gfn, "Starting new round", UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + + // Instrument interrupts. + setup_interrupt(en_intr); + + // Enable wakeups. + enabled_wakeups = wakeups_en & wakeups; + `DV_CHECK(enabled_wakeups, $sformatf( + "Some wakeup must be enabled: wkups=%b, wkup_en=%b", wakeups, wakeups_en)) + `uvm_info(`gfn, $sformatf( + "Enabled wakeups=0x%x, wakeups=0x%x, enables=0x%x", + enabled_wakeups, wakeups, wakeups_en), + UVM_MEDIUM) + csr_wr(.ptr(ral.wakeup_en[0]), .value(wakeups_en)); + + if (keep_prior_wake_info) begin + csr_rd(.ptr(ral.wake_info.reasons), .value(prior_reasons)); + csr_rd(.ptr(ral.wake_info.fall_through), .value(prior_fall_through)); + csr_rd(.ptr(ral.wake_info.abort), .value(prior_abort)); + end else begin + clear_wake_info(); + prior_reasons = '0; + prior_fall_through = '0; + prior_abort = '0; + end + `uvm_info(`gfn, $sformatf( + "Prior wake_info: reasons=0x%x, fall_through=%b, abort=%b", + prior_reasons, + prior_fall_through, + prior_abort + ), UVM_MEDIUM) + + `uvm_info(`gfn, $sformatf("%0sabling wakeup capture", disable_wakeup_capture ? "Dis" : "En"), + UVM_MEDIUM) + csr_wr(.ptr(ral.wake_info_capture_dis), .value(disable_wakeup_capture)); + + low_power_hint = 1'b1; + update_control_csr(); + + // Initiate low power transition. + initiate_low_power_transition(); + + if (ral.control.main_pd_n.get_mirrored_value() == 1'b0) begin + wait_for_reset_cause(pwrmgr_pkg::LowPwrEntry); + end + + // Now bring it back. + cfg.slow_clk_rst_vif.wait_clks(cycles_before_wakeup); + cfg.pwrmgr_vif.update_wakeups(wakeups); + // Check wake_status prior to wakeup, or the unit requesting wakeup will have been reset. + // This read will not work in the chip, since the processor will be asleep. + cfg.slow_clk_rst_vif.wait_clks(4); + // wait for clock is on + cfg.clk_rst_vif.wait_clks(10); + + check_wake_status(enabled_wakeups); + `uvm_info(`gfn, $sformatf("Got wake_status=0x%x", enabled_wakeups), UVM_MEDIUM) + wait(cfg.pwrmgr_vif.pwr_clk_req.main_ip_clk_en == 1'b1); + + wait_for_rom_and_active(); + `uvm_info(`gfn, "Back from wakeup", UVM_MEDIUM) + + @cfg.clk_rst_vif.cb; + fork + begin + fast_check_reset_status(0); + end + begin + fast_check_wake_info(.reasons(enabled_wakeups), .prior_reasons(prior_reasons), + .fall_through(1'b0), .abort(1'b0), + .prior_fall_through(prior_fall_through), .prior_abort(prior_abort)); + end + join + // This is the expected side-effect of the low power entry reset, since the source of the + // non-aon wakeup sources will deassert it as a consequence of their reset. + // Some aon wakeups may remain active until software clears them. If they didn't, such wakeups + // will remain active, preventing the device from going to sleep. + cfg.pwrmgr_vif.update_wakeups('0); + cfg.slow_clk_rst_vif.wait_clks(10); + + // if clock is off, we need to wait until it is resumed. + cfg.clk_rst_vif.wait_clks(5); + check_wake_status('0); + + // And make the cpu active. + cfg.pwrmgr_vif.update_cpu_sleeping(1'b0); + + // Wait for interrupt to be generated whether or not it is enabled. + cfg.slow_clk_rst_vif.wait_clks(10); + check_and_clear_interrupt(.expected(1'b1)); + end + clear_wake_info(); + endtask + + virtual task initiate_low_power_transition(); + cfg.pwrmgr_vif.update_cpu_sleeping(1'b1); + set_nvms_idle(); + endtask +endclass : pwrmgr_wakeup_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/pwrmgr_sim.core b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/pwrmgr_sim.core new file mode 100644 index 00000000000..596577030bf --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/pwrmgr_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:pwrmgr_sim:0.1 +description: "PWRMGR DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:pwrmgr:0.1 + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:pwrmgr_test:0.1 + - lowrisc:darjeeling_no_ibex_dv:pwrmgr_sva:0.1 + - lowrisc:darjeeling_no_ibex_dv:pwrmgr_unit_only_sva:0.1 + files: + - tb.sv + - cov/pwrmgr_cov_bind.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson new file mode 100644 index 00000000000..c1982fbff93 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson @@ -0,0 +1,152 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: pwrmgr + + // Top level dut name (sv module). + dut: pwrmgr + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_dv:pwrmgr_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/pwrmgr_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"] + + // Exclusion files + vcs_cov_excl_files: ["{self_dir}/cov/pwrmgr_cov_manual_excl.el"] + + // Overrides + overrides: [ + // Handle generated coverage exclusion. + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {dv_root}/tools/vcs/cover.cfg+{dv_root}/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/pwrmgr_tgl_excl.cfg" + } + ] + + // Add additional tops for simulation. + sim_tops: ["pwrmgr_bind", + "pwrmgr_cov_bind", + "pwrmgr_unit_only_bind", + "sec_cm_prim_count_bind", + "sec_cm_prim_sparse_fsm_flop_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: pwrmgr_base_test + uvm_test_seq: pwrmgr_base_vseq + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: pwrmgr_smoke + uvm_test_seq: pwrmgr_smoke_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_reset + uvm_test_seq: pwrmgr_reset_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_lowpower_wakeup_race + uvm_test_seq: pwrmgr_lowpower_wakeup_race_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_wakeup + uvm_test_seq: pwrmgr_wakeup_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_wakeup_reset + uvm_test_seq: pwrmgr_wakeup_reset_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_aborted_low_power + uvm_test_seq: pwrmgr_aborted_low_power_vseq + } + { + name: pwrmgr_sec_cm_lc_ctrl_intersig_mubi + uvm_test_seq: pwrmgr_repeat_wakeup_reset_vseq + run_opts: ["+test_timeout_ns=3000000", "+pwrmgr_mubi_mode=PwrmgrMubiLcCtrl"] + } + { + name: pwrmgr_sec_cm_rstmgr_intersig_mubi + uvm_test_seq: pwrmgr_sw_reset_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_esc_clk_rst_malfunc + uvm_test_seq: pwrmgr_esc_clk_rst_malfunc_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_sec_cm_ctrl_config_regwen + uvm_test_seq: pwrmgr_sec_cm_ctrl_config_regwen_vseq + run_opts: ["+test_timeout_ns=50000000"] + } + { + name: pwrmgr_global_esc + uvm_test_seq: pwrmgr_global_esc_vseq + run_opts: ["+test_timeout_ns=1000000000"] + } + { + name: pwrmgr_escalation_timeout + uvm_test_seq: pwrmgr_escalation_timeout_vseq + } + { + name: pwrmgr_glitch + uvm_test_seq: pwrmgr_glitch_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_disable_rom_integrity_check + uvm_test_seq: pwrmgr_disable_rom_integrity_check_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_reset_invalid + uvm_test_seq: pwrmgr_reset_invalid_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + { + name: pwrmgr_lowpower_invalid + uvm_test_seq: pwrmgr_lowpower_invalid_vseq + run_opts: ["+test_timeout_ns=1000000"] + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["pwrmgr_smoke"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv new file mode 100644 index 00000000000..4950a2cf8fa --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_ast_sva_if.sv @@ -0,0 +1,115 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check the inputs from ast react according to +// the pwrmgr outputs. The ast inputs are generated by the base sequences, but +// these assertions will also be useful at full chip level. +interface pwrmgr_ast_sva_if #( + parameter bit CheckClocks = 1'b0 +) ( + input logic clk_slow_i, + input logic rst_slow_ni, + input logic clk_main_i, + input logic clk_io_i, + input logic por_d0_ni, + // The pwrmgr outputs. + input pwrmgr_pkg::pwr_ast_req_t pwr_ast_o, + // The pwrmgr inputs. + input pwrmgr_pkg::pwr_ast_rsp_t pwr_ast_i +); + + // These numbers of cycles are meant to match both the randomization in + // pwrmgr_base_vseq, and the actual cycle counts from full chip. + // Notice the expectation for full chip is that deassertion of *clk_val + // takes 0 cycles, and assertion takes a 2 cycle synchronizer delay on + // the slow clock; deassertion of main_pok takes one cycle, and assertion + // not more than 2 cycles. + localparam int MinClkWaitCycles = 0; + localparam int MinPdnWaitCycles = 0; + localparam int MaxClkWaitCycles = 60; + localparam int MaxPdnWaitCycles = 110; + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_slow_ni || disable_sva; + + `define CLK_WAIT_BOUNDS ##[MinClkWaitCycles:MaxClkWaitCycles] + `define PDN_WAIT_BOUNDS ##[MinPdnWaitCycles:MaxPdnWaitCycles] + + // Clock enable-valid. + + // Changes triggered by por_d0_ni only affect clk_val. + `ASSERT(MainClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:1] !pwr_ast_i.core_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(MainClkGlitchToValOn_A, + $rose(por_d0_ni) && pwr_ast_o.core_clk_en |-> ##[0:2] pwr_ast_i.core_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(IoClkGlitchToValOff_A, $fell(por_d0_ni) |-> ##[0:1] !pwr_ast_i.io_clk_val, clk_slow_i, + reset_or_disable) + `ASSERT(IoClkGlitchToValOn_A, + $rose(por_d0_ni) && pwr_ast_o.io_clk_en |-> ##[0:2] pwr_ast_i.io_clk_val, clk_slow_i, + reset_or_disable) + // Changes not triggered by por_d0_ni + `ASSERT(MainClkHandshakeOn_A, + $rose(pwr_ast_o.core_clk_en) && por_d0_ni |-> `CLK_WAIT_BOUNDS + pwr_ast_i.core_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable) + `ASSERT(MainClkHandshakeOff_A, + $fell(pwr_ast_o.core_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.core_clk_val, clk_slow_i, + reset_or_disable) + + `ASSERT(IoClkHandshakeOn_A, + $rose(pwr_ast_o.io_clk_en) && por_d0_ni |-> `CLK_WAIT_BOUNDS + pwr_ast_i.io_clk_val || !por_d0_ni, clk_slow_i, reset_or_disable) + `ASSERT(IoClkHandshakeOff_A, + $fell(pwr_ast_o.io_clk_en) |-> `CLK_WAIT_BOUNDS !pwr_ast_i.io_clk_val, clk_slow_i, + reset_or_disable) + + if (CheckClocks) begin : gen_check_clock + int main_clk_cycles; + always_ff @(posedge clk_main_i) main_clk_cyces++; + int io_clk_cycles; + always_ff @(posedge clk_io_i) io_clk_cyces++; + + `ASSERT(MainClkStopped_A, + $fell( + pwr_ast_i.core_clk_val + ) |=> ($stable( + main_clk_cycles + ) || pwr_ast_i.core_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + `ASSERT(MainClkRun_A, + $rose( + pwr_ast_i.core_clk_val + ) |=> (!$stable( + main_clk_cycles + ) || !pwr_ast_i.core_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + + `ASSERT(IOClkStopped_A, + $fell( + pwr_ast_i.io_clk_val + ) |=> ($stable( + io_clk_cycles + ) || pwr_ast_i.io_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + `ASSERT(IoClkRun_A, + $rose( + pwr_ast_i.io_clk_val + ) |=> (!$stable( + io_clk_cycles + ) || !pwr_ast_i.io_clk_val) [* 1 : $], + clk_slow_i, reset_or_disable) + + end + + // Main pd-pok + `ASSERT(MainPdHandshakeOn_A, pwr_ast_o.main_pd_n |-> `PDN_WAIT_BOUNDS pwr_ast_i.main_pok, + clk_slow_i, reset_or_disable) + `ASSERT(MainPdHandshakeOff_A, !pwr_ast_o.main_pd_n |-> `PDN_WAIT_BOUNDS !pwr_ast_i.main_pok, + clk_slow_i, reset_or_disable) + + `undef CLK_WAIT_BOUNDS + `undef PDN_WAIT_BOUNDS +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv new file mode 100644 index 00000000000..1a7db8387e9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_bind.sv @@ -0,0 +1,75 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module pwrmgr_bind; +`ifndef GATE_LEVEL + bind pwrmgr tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); + + // In top-level testbench, do not bind the csr_assert_fpv to reduce simulation time. +`ifndef TOP_LEVEL_DV + bind pwrmgr pwrmgr_csr_assert_fpv pwrmgr_csr_assert (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); +`endif + + // Clock control assertions. + bind pwrmgr pwrmgr_clock_enables_sva_if pwrmgr_clock_enables_sva_if ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .fast_state(u_fsm.state_q), + .slow_state(u_slow_fsm.state_q), + // The synchronized control CSR bits. + .main_pd_ni(slow_main_pd_n), + .main_clk_en_i(slow_main_clk_en), + .io_clk_en_i(slow_io_clk_en), + // The main power control. + .main_pd_n(pwr_ast_o.main_pd_n), + // The output enables. + .main_clk_en(pwr_ast_o.core_clk_en), + .io_clk_en(pwr_ast_o.io_clk_en) + ); + + bind pwrmgr clkmgr_pwrmgr_sva_if #(.IS_USB(0)) clkmgr_pwrmgr_main_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_clk_o.main_ip_clk_en), + .status(pwr_clk_i.main_status) + ); + + bind pwrmgr clkmgr_pwrmgr_sva_if #(.IS_USB(0)) clkmgr_pwrmgr_io_sva_if ( + .clk_i, + .rst_ni, + .clk_en(pwr_clk_o.io_ip_clk_en), + .status(pwr_clk_i.io_status) + ); + + bind pwrmgr pwrmgr_sec_cm_checker_assert pwrmgr_sec_cm_checker_assert ( + .clk_i, + .rst_ni, + .clk_lc_i, + .rst_lc_ni, + .clk_esc_i, + .rst_esc_ni, + .clk_slow_i, + .rst_slow_ni, + .rst_main_ni, + .io_clk_en(pwr_clk_o.io_ip_clk_en), + .pwr_rst_o, + .esc_timeout(esc_timeout_lc_q), + .slow_esc_rst_req(slow_peri_reqs.rstreqs[3]), + .slow_mp_rst_req(slow_peri_reqs.rstreqs[2]), + .slow_fsm_invalid, + .fast_fsm_invalid(u_fsm.u_state_regs.unused_err_o), + .rom_intg_chk_dis(u_fsm.rom_intg_chk_dis), + .rom_intg_chk_done(u_fsm.rom_intg_chk_done), + .rom_intg_chk_good(u_fsm.rom_intg_chk_good), + .fast_state(u_fsm.state_q), + .lc_dft_en_i(u_fsm.lc_dft_en_i), + .lc_hw_debug_en_i(u_fsm.lc_hw_debug_en_i), + .main_pd_ni(u_slow_fsm.main_pd_ni), + .rom_ctrl_done_i(u_fsm.rom_ctrl_done_i), + .rom_ctrl_good_i(u_fsm.rom_ctrl_good_i) + ); +`endif +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv new file mode 100644 index 00000000000..cba43afe451 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_clock_enables_sva_if.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check that the output clock enables correspond +// to the control CSR when transitioning into or out of the active state. In +// addition, the usb clock can change anytime when in the active state. +interface pwrmgr_clock_enables_sva_if ( + input logic clk_i, + input logic rst_ni, + input pwrmgr_pkg::fast_pwr_state_e fast_state, + input pwrmgr_pkg::slow_pwr_state_e slow_state, + // The synchronized control CSR bits. + input logic main_pd_ni, + input logic main_clk_en_i, + input logic io_clk_en_i, + // The output enables. + input logic main_pd_n, + input logic main_clk_en, + input logic io_clk_en +); + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_ni || disable_sva; + + sequence transitionUp_S; slow_state == pwrmgr_pkg::SlowPwrStateReqPwrUp; endsequence + + sequence transitionDown_S; slow_state == pwrmgr_pkg::SlowPwrStatePwrClampOn; endsequence + + bit fast_is_active; + always_comb fast_is_active = fast_state == pwrmgr_pkg::FastPwrStateActive; + + `ASSERT(MainClkPwrUp_A, transitionUp_S |=> main_clk_en == 1'b1, clk_i, reset_or_disable) + `ASSERT(IoClkPwrUp_A, transitionUp_S |=> io_clk_en == 1'b1, clk_i, reset_or_disable) + + `ASSERT(MainClkPwrDown_A, transitionDown_S |=> main_clk_en == (main_clk_en_i && main_pd_ni), + clk_i, reset_or_disable) + `ASSERT(IoClkPwrDown_A, transitionDown_S |=> io_clk_en == (io_clk_en_i && main_pd_ni), + clk_i, reset_or_disable) +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv new file mode 100644 index 00000000000..47d32756ee5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstreqs_sva_if.sv @@ -0,0 +1,102 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has some assertions that check the pwrmgr rstreqs and reset_cause output is set per the +// reset requests the pwrmgr receives or generates. +interface pwrmgr_rstreqs_sva_if + import pwrmgr_pkg::*, pwrmgr_reg_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input logic clk_slow_i, + input logic rst_slow_ni, + + // Input causes resets. + input logic [ NumRstReqs-1:0] rstreqs_i, + input logic [ NumRstReqs-1:0] reset_en, + input logic sw_rst_req_i, + input logic main_rst_req_i, + input logic esc_rst_req_i, + input logic ndm_rst_req_i, + // outputs + input logic main_pd_n, + input reset_cause_e reset_cause, + input logic [HwResetWidth-1:0] rstreqs +); + + // output reset cycle with a clk enable disable + localparam int MinMainRstCycles = 0; + localparam int MaxMainRstCycles = 400; + `define MAIN_RST_CYCLES ##[MinMainRstCycles:MaxMainRstCycles] + + // The timing of the escalation reset is determined by the slow clock, but will not propagate if + // the non-slow clock is off. We use the regular clock and multiply the clock cycles times the + // clock ratio. + localparam int FastToSlowFreqRatio = 120; + + localparam int MinEscRstCycles = 0; + localparam int MaxEscRstCycles = 4 * FastToSlowFreqRatio; + `define ESC_RST_CYCLES ##[MinEscRstCycles:MaxEscRstCycles] + + bit disable_sva; + bit reset_or_disable; + + always_comb reset_or_disable = !rst_ni || !rst_slow_ni || disable_sva; + + // Reset ins to outs. + for (genvar rst = 0; rst < NumRstReqs; ++rst) begin : gen_hw_resets + `ASSERT(HwResetOn_A, + $rose( + rstreqs_i[rst] && reset_en[rst] + ) |-> `MAIN_RST_CYCLES rstreqs[rst] && reset_cause == HwReq, clk_slow_i, + reset_or_disable) + `ASSERT(HwResetOff_A, + $fell( + rstreqs_i[rst] && reset_en[rst] + ) |-> `MAIN_RST_CYCLES !rstreqs[rst] && reset_cause != HwReq, clk_slow_i, + reset_or_disable) + end + + // This is used to ignore main_rst_req_i (wired to rst_main_n) if it happens during low power, + // since as part of deep sleep rst_main_n will trigger and not because of a power glitch. + logic rst_main_n_ignored_for_main_pwr_rst; + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + rst_main_n_ignored_for_main_pwr_rst <= 0; + end else if (!main_pd_n && reset_cause == LowPwrEntry) begin + rst_main_n_ignored_for_main_pwr_rst <= 1; + end else if (reset_cause != LowPwrEntry) begin + rst_main_n_ignored_for_main_pwr_rst <= 0; + end + end + + `ASSERT(MainPwrRstOn_A, + $rose( + main_rst_req_i && !rst_main_n_ignored_for_main_pwr_rst + ) |-> `MAIN_RST_CYCLES rstreqs[ResetMainPwrIdx], clk_slow_i, + reset_or_disable) + `ASSERT(MainPwrRstOff_A, + $fell( + main_rst_req_i + ) |-> `MAIN_RST_CYCLES !rstreqs[ResetMainPwrIdx], clk_slow_i, + reset_or_disable) + + // Signals in EscRstOn_A and EscRstOff_A are sampled with slow and fast clock. + // Since fast clock can be gated, use fast clock to evaluate cycle delay + // to avoid spurious failure. + `ASSERT(EscRstOn_A, + $rose( + esc_rst_req_i + ) |-> `ESC_RST_CYCLES rstreqs[ResetEscIdx], clk_i, reset_or_disable) + `ASSERT(EscRstOff_A, + $fell( + esc_rst_req_i + ) |-> `ESC_RST_CYCLES !rstreqs[ResetEscIdx], clk_i, reset_or_disable) + + // Software initiated resets do not affect rstreqs since rstmgr generates them. + `ASSERT(SwResetSetCause_A, + $rose(sw_rst_req_i) |-> MAIN_RST_CYCLES (reset_cause == HwReq), clk_i, + reset_or_disable) + +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv new file mode 100644 index 00000000000..4f56024bb1f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_sec_cm_checker_assert.sv @@ -0,0 +1,171 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has a number of assertions to check security countermeasures. They are +// individually described in their comments. +module pwrmgr_sec_cm_checker_assert + import pwrmgr_reg_pkg::*; +( + input clk_i, + input rst_ni, + input clk_lc_i, + input rst_lc_ni, + input clk_esc_i, + input rst_esc_ni, + input rst_main_ni, + input clk_slow_i, + input rst_slow_ni, + input logic io_clk_en, + input pwrmgr_pkg::pwr_rst_req_t pwr_rst_o, + input slow_fsm_invalid, + input fast_fsm_invalid, + input prim_mubi_pkg::mubi4_t rom_intg_chk_dis, + input prim_mubi_pkg::mubi4_t rom_intg_chk_done, + input prim_mubi_pkg::mubi4_t rom_intg_chk_good, + input pwrmgr_pkg::fast_pwr_state_e fast_state, + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input esc_timeout, + input slow_esc_rst_req, + input slow_mp_rst_req, + input main_pd_ni, + input prim_mubi_pkg::mubi4_t rom_ctrl_done_i, + input prim_mubi_pkg::mubi4_t rom_ctrl_good_i +); + + bit disable_sva; + bit reset_or_disable; + bit esc_reset_or_disable; + bit slow_reset_or_disable; + + always_comb reset_or_disable = !rst_ni || disable_sva; + always_comb esc_reset_or_disable = !rst_esc_ni || disable_sva; + always_comb slow_reset_or_disable = !rst_slow_ni || disable_sva; + + // rom_intg_chk_dis only allows two states. + // Note that lc_dft_en_i and lc_hw_debug_en_i are already synchronized to clk_i at this + // hierarchy level. + // Check that rom integrity checks are disabled when lc_dft_en_i and lc_hw_debug_en_i are active. + `ASSERT(RomIntgChkDisTrue_A, + rom_intg_chk_dis == prim_mubi_pkg::MuBi4True |-> + (lc_dft_en_i == lc_ctrl_pkg::On && + lc_hw_debug_en_i == lc_ctrl_pkg::On), + clk_i, + reset_or_disable) + + // Check that rom integrity checks are enabled when either lc_dft_en_i or lc_hw_debug_en_i are + // inactive. + `ASSERT(RomIntgChkDisFalse_A, + rom_intg_chk_dis == prim_mubi_pkg::MuBi4False |-> + (lc_dft_en_i !== lc_ctrl_pkg::On || + lc_hw_debug_en_i !== lc_ctrl_pkg::On), + clk_i, + reset_or_disable) + + // For any assertions involving state transitions, also allow cases where the fsm + // transitions to an invalid state, since we inject invalid encodings at random. + // For slow fsm invalid states the fast fsm explicitly transitions to FastPwrStateInvalid + // For fast fsm invalid states we use the fast_fsm_invalid input. + + // Check that unless rom_intg_chk_done is mubi true the fast state machine will + // stay in FastPwrStateRomCheckDone or transition to Invalid. + `ASSERT(RomBlockCheckGoodState_A, + rom_intg_chk_done != prim_mubi_pkg::MuBi4True && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone |=> + fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone || + fast_state == pwrmgr_pkg::FastPwrStateInvalid || + fast_fsm_invalid, + clk_i, + reset_or_disable) + + // Check that when rom_intg_chk_done is mubi true the fast state machine will transition + // from FastPwrStateRomCheckDone to either FastPwrStateRomCheckGood or Invalid. + `ASSERT(RomAllowCheckGoodState_A, + rom_intg_chk_done == prim_mubi_pkg::MuBi4True && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckDone |=> + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood || + fast_state == pwrmgr_pkg::FastPwrStateInvalid || + fast_fsm_invalid, + clk_i, + reset_or_disable) + + // Check that unless rom_intg_chk_good is mubi true or rom_intg_chk_dis is mubi true + // the fast state machine will stay in FastPwrStateRomCheckGood. + `ASSERT(RomBlockActiveState_A, + rom_intg_chk_good != prim_mubi_pkg::MuBi4True && + rom_intg_chk_dis != prim_mubi_pkg::MuBi4True && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood |=> + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood || + fast_state == pwrmgr_pkg::FastPwrStateInvalid || + fast_fsm_invalid, + clk_i, + reset_or_disable) + + // Check that when one of rom_intg_chk_good or rom_intg_chk_dis is mubi true the fast + // state machine will transition from FastPwrStateRomCheckGood to FastPwrStateActive + // or Invalid. + `ASSERT(RomAllowActiveState_A, + (rom_intg_chk_good == prim_mubi_pkg::MuBi4True || + rom_intg_chk_dis == prim_mubi_pkg::MuBi4True) && + fast_state == pwrmgr_pkg::FastPwrStateRomCheckGood |=> + fast_state == pwrmgr_pkg::FastPwrStateActive || + fast_state == pwrmgr_pkg::FastPwrStateInvalid || + fast_fsm_invalid, + clk_i, + reset_or_disable) + + // For testpoints sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc. + // If the escalation clock (clk_esc_i) stops for too many cycles and is not + // disabled, an escalation timeout should be requested until rst_lc_ni goes + // active. + // The bound of cycles is 128 cycles for the counter, 8 cycles maximum for the + // counter to engage, and 2 cycles for a synchronizer. Use negedge of clk_i + // to sample clk_esc_i as 1 when active, and 0 when inactive. + `ASSERT(EscClkStopEscTimeout_A, !clk_esc_i && io_clk_en [* (128 + 8 + 2)] |=> + esc_timeout || !rst_lc_ni, !clk_i, reset_or_disable) + + // For testpoints sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc. + // Escalation timeout should not be requested when rst_nc_ni is active. + `ASSERT(EscTimeoutStoppedByClReset_A, + !rst_lc_ni |-> !esc_timeout, clk_i, reset_or_disable) + + // For testpoints sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc. + // If escalation timeout is detected a reset request will be generated. + `ASSERT(EscTimeoutTriggersReset_A, esc_timeout |=> ##[1:3] slow_esc_rst_req, + clk_slow_i, !rst_slow_ni || disable_sva) + + // pwr_rst_o.rstreqs checker + // For testpoints sec_cm_esc_rx_clk_bkgn_chk, sec_cm_esc_rx_clk_local_esc. + // If a slow clock domain escalation reset is requested, rstreqs[ResetEscIdx] + // should be asserted after some cycles unless rst_lc_n becomes active. + `ASSERT(RstreqChkEsctimeout_A, + $rose( + slow_esc_rst_req + ) ##1 slow_esc_rst_req |-> ##[0:10] pwr_rst_o.rstreqs[ResetEscIdx] || !rst_lc_ni, + clk_i, reset_or_disable) + + // For testpoint sec_cm_fsm_terminal. + // If slow_fsm or fast_fsm is invalid, both pwr_rst_o.rst_lc_req and + // pwr_rst_o.rst_sys_req should be set. + `ASSERT(RstreqChkFsmterm_A, + $rose(slow_fsm_invalid) || $rose(fast_fsm_invalid) + |-> ##[0:10] $rose(pwr_rst_o.rst_lc_req & pwr_rst_o.rst_sys_req), + clk_i, reset_or_disable) + + // For testpoint sec_cm_ctrl_flow_global_esc. + // If a slow clock domain escalation reset request is set, the output escalation + // reset pwr_rst_o.rstreqs[ResetEscIdx] should be asserted after some cycles. + `ASSERT(RstreqChkGlbesc_A, + $rose(slow_esc_rst_req) ##1 slow_esc_rst_req |-> + ##[0:10] (pwr_rst_o.rstreqs[ResetEscIdx] | !rst_esc_ni), + clk_i, reset_or_disable) + + // For testpoint sec_cm_main_pd_rst_local_esc. + // If power is up and rst_main_ni goes low, pwr_rst_o.rstreqs[ResetMainPwrIdx] + // should be asserted. + `ASSERT(RstreqChkMainpd_A, + slow_mp_rst_req |-> ##[0:5] pwr_rst_o.rstreqs[ResetMainPwrIdx], clk_i, + reset_or_disable) + +endmodule : pwrmgr_sec_cm_checker_assert diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core new file mode 100644 index 00000000000..7bceb825122 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_sva.core @@ -0,0 +1,43 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:pwrmgr_sva:0.1 +description: "PWRMGR assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + - lowrisc:dv:clkmgr_pwrmgr_sva_if + - lowrisc:dv:pwrmgr_rstmgr_sva_if:0.1 + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg + files: + - pwrmgr_bind.sv + - pwrmgr_clock_enables_sva_if.sv + - pwrmgr_rstreqs_sva_if.sv + - pwrmgr_sec_cm_checker_assert.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:darjeeling_no_ibex_ip:pwrmgr:0.1 + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/pwrmgr.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: pwrmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_bind.sv new file mode 100644 index 00000000000..511af2f854d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This binds assertions that should not be bound at chip level. +module pwrmgr_unit_only_bind; + + bind pwrmgr pwrmgr_rstmgr_sva_if #( + .PowerDomains(pwrmgr_pkg::PowerDomains) + ) pwrmgr_rstmgr_sva_if ( + .clk_i, + .rst_ni, + .clk_slow_i, + .rst_slow_ni, + // The outputs from pwrmgr. + .rst_lc_req(pwr_rst_o.rst_lc_req), + .rst_sys_req(pwr_rst_o.rst_sys_req), + // The inputs from rstmgr. + .rst_lc_src_n(pwr_rst_i.rst_lc_src_n), + .rst_sys_src_n(pwr_rst_i.rst_sys_src_n) + ); + +endmodule : pwrmgr_unit_only_bind diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_sva.core b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_sva.core new file mode 100644 index 00000000000..35c73da79a5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_unit_only_sva.core @@ -0,0 +1,36 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:pwrmgr_unit_only_sva:0.1 +description: "PWRMGR assertion interfaces not suitable for chip level bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + - lowrisc:dv:pwrmgr_rstmgr_sva_if + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg:0.1 + - lowrisc:darjeeling_no_ibex_ip:pwrmgr:0.1 + + files: + - pwrmgr_unit_only_bind.sv + file_type: systemVerilogSource + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/pwrmgr.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + formal: + <<: *default_target + filesets: + - files_dv + toplevel: pwrmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tb.sv new file mode 100644 index 00000000000..8d3f1493974 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tb.sv @@ -0,0 +1,143 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import pwrmgr_env_pkg::*; + import pwrmgr_test_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n; + wire clk_esc, rst_esc_n; + wire clk_lc, rst_lc_n; + wire clk_slow, rst_slow_n; + wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + wire int_reset_req; + + // interfaces + clk_rst_if clk_rst_if ( + .clk (clk), + .rst_n(rst_n) + ); + clk_rst_if lc_clk_rst_if ( + .clk (clk_lc), + .rst_n(rst_lc_n) + ); + clk_rst_if esc_clk_rst_if ( + .clk (clk_esc), + .rst_n(rst_esc_n) + ); + clk_rst_if slow_clk_rst_if ( + .clk (clk_slow), + .rst_n(rst_slow_n) + ); + pins_if #(NUM_MAX_INTERRUPTS) intr_if (interrupts); + alert_esc_if esc_if ( + .clk (clk), + .rst_n(rst_n) + ); + tl_if tl_if ( + .clk (clk), + .rst_n(rst_n) + ); + + assign interrupts[0] = pwrmgr_if.intr_wakeup; + assign int_reset_req = tb.dut.internal_reset_req; + + pwrmgr_if pwrmgr_if ( + .clk, + .rst_n, + .clk_slow, + .rst_slow_n + ); + + `DV_ALERT_IF_CONNECT(clk_lc, rst_lc_n) + + // dut + pwrmgr dut ( + .clk_i (clk), + .rst_ni (rst_n), + .clk_slow_i (clk_slow), + .rst_slow_ni(rst_slow_n), + .rst_main_ni(pwrmgr_if.rst_main_n), + .clk_lc_i (clk_lc), + .rst_lc_ni (rst_lc_n), + .clk_esc_i (clk_esc), + .rst_esc_ni (rst_esc_n), + + .tl_i(tl_if.h2d), + .tl_o(tl_if.d2h), + + .alert_rx_i(alert_rx), + .alert_tx_o(alert_tx), + + .pwr_ast_i(pwrmgr_if.pwr_ast_rsp), + .pwr_ast_o(pwrmgr_if.pwr_ast_req), + + .pwr_rst_i(pwrmgr_if.pwr_rst_rsp), + .pwr_rst_o(pwrmgr_if.pwr_rst_req), + + .pwr_clk_i(pwrmgr_if.pwr_clk_rsp), + .pwr_clk_o(pwrmgr_if.pwr_clk_req), + + .pwr_otp_i(pwrmgr_if.pwr_otp_rsp), + .pwr_otp_o(pwrmgr_if.pwr_otp_req), + + .pwr_lc_i(pwrmgr_if.pwr_lc_rsp), + .pwr_lc_o(pwrmgr_if.pwr_lc_req), + + .pwr_flash_i(pwrmgr_if.pwr_flash), + .pwr_cpu_i (pwrmgr_if.pwr_cpu), + + .fetch_en_o(pwrmgr_if.fetch_en), + .wakeups_i (pwrmgr_if.wakeups_i), + // TODO(#22710): properly cooperate with `pwrmgr_if.rstreqs_i[1]` + .rstreqs_i ({int_reset_req, pwrmgr_if.rstreqs_i[0]}), + .ndmreset_req_i(pwrmgr_if.cpu_i.ndmreset_req), + + .lc_dft_en_i (pwrmgr_if.lc_dft_en), + .lc_hw_debug_en_i(pwrmgr_if.lc_hw_debug_en), + + .strap_o (pwrmgr_if.strap), + .low_power_o(pwrmgr_if.low_power), + + .rom_ctrl_i(pwrmgr_if.rom_ctrl_i), + + .sw_rst_req_i(pwrmgr_if.sw_rst_req_i), + + .esc_rst_tx_i(esc_if.esc_tx), + .esc_rst_rx_o(esc_if.esc_rx), + + .intr_wakeup_o(pwrmgr_if.intr_wakeup) + ); + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + esc_clk_rst_if.set_active(); + lc_clk_rst_if.set_active(); + slow_clk_rst_if.set_active(); + + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "esc_clk_rst_vif", esc_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "lc_clk_rst_vif", lc_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "slow_clk_rst_vif", slow_clk_rst_if); + uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if); + uvm_config_db#(virtual alert_esc_if)::set(null, "*.env.m_esc_agent*", "vif", esc_if); + uvm_config_db#(virtual pwrmgr_if)::set(null, "*.env", "pwrmgr_vif", pwrmgr_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + uvm_config_db#(virtual pwrmgr_clock_enables_sva_if)::set( + null, "*.env", "pwrmgr_clock_enables_sva_vif", dut.pwrmgr_clock_enables_sva_if); + uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::set(null, "*.env", "pwrmgr_rstmgr_sva_vif", + dut.pwrmgr_rstmgr_sva_if); + $timeformat(-12, 0, " ps", 12); + run_test(); + end // initial begin + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tests/pwrmgr_base_test.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tests/pwrmgr_base_test.sv new file mode 100644 index 00000000000..0432cfc12b3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tests/pwrmgr_base_test.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class pwrmgr_base_test extends cip_base_test #( + .CFG_T(pwrmgr_env_cfg), + .ENV_T(pwrmgr_env) +); + + `uvm_component_utils(pwrmgr_base_test) + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // pwrmgr_env_cfg: cfg + // pwrmgr_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : pwrmgr_base_test diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tests/pwrmgr_test.core b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tests/pwrmgr_test.core new file mode 100644 index 00000000000..c3cf4d1ab00 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tests/pwrmgr_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:pwrmgr_test:0.1 +description: "PWRMGR DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:pwrmgr_env:0.1 + files: + - pwrmgr_test_pkg.sv + - pwrmgr_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tests/pwrmgr_test_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tests/pwrmgr_test_pkg.sv new file mode 100644 index 00000000000..afbd1941556 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/tests/pwrmgr_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package pwrmgr_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import pwrmgr_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "pwrmgr_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/lint/pwrmgr.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/lint/pwrmgr.vlt new file mode 100644 index 00000000000..a38de163cf1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/lint/pwrmgr.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for Power Manager diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/lint/pwrmgr.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/lint/pwrmgr.waiver new file mode 100644 index 00000000000..75aee6c3c11 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/lint/pwrmgr.waiver @@ -0,0 +1,5 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for Power Manager diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/lint/pwrmgr_pkg.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/lint/pwrmgr_pkg.vlt new file mode 100644 index 00000000000..a5949a211be --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/lint/pwrmgr_pkg.vlt @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for the pwrmgr_pkg + +`verilator_config + +// Waive the SYMRSVDWORD warning in pwrmgr_reg_pkg: we have a field in +// the WAKE_INFO register called "abort", which means pwrmgr_reg_pkg +// defines a struct with that name, clashing with a C++ reserved word. +lint_off -rule SYMRSVDWORD -file "*/pwrmgr_reg_pkg.sv" -match "*common word: 'abort'" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/pwrmgr.core b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/pwrmgr.core new file mode 100644 index 00000000000..47f0a02331f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/pwrmgr.core @@ -0,0 +1,81 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:pwrmgr:0.1 +description: "Power manager RTL" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:esc + - lowrisc:prim:lc_sync + - lowrisc:prim:lc_sender + - lowrisc:prim:all + - lowrisc:ip:rom_ctrl_pkg + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:ip:rv_core_ibex_pkg + - lowrisc:prim:sparse_fsm + - lowrisc:prim:mubi + - lowrisc:prim:clock_buf + - lowrisc:prim:measure + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg:0.1 + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_reg:0.1 + files: + - rtl/pwrmgr_cdc.sv + - rtl/pwrmgr_slow_fsm.sv + - rtl/pwrmgr_fsm.sv + - rtl/pwrmgr_wake_info.sv + - rtl/pwrmgr.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: pwrmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/pwrmgr_pkg.core b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/pwrmgr_pkg.core new file mode 100644 index 00000000000..d4084cd53b6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/pwrmgr_pkg.core @@ -0,0 +1,32 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg:0.1 +description: "Power manager package" + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:ip:rom_ctrl_pkg + files: + - rtl/pwrmgr_reg_pkg.sv + - rtl/pwrmgr_pkg.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/pwrmgr_pkg.vlt + file_type: vlt + +targets: + default: + filesets: + - tool_verilator ? (files_verilator_waiver) + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/pwrmgr_reg.core b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/pwrmgr_reg.core new file mode 100644 index 00000000000..1732547cbd2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/pwrmgr_reg.core @@ -0,0 +1,21 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:pwrmgr_reg:0.1 +description: "Power manager registers" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:subreg + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg + files: + - rtl/pwrmgr_reg_top.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr.sv new file mode 100644 index 00000000000..bd631678b20 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr.sv @@ -0,0 +1,767 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager +// + +`include "prim_assert.sv" + +module pwrmgr + import pwrmgr_pkg::*; + import pwrmgr_reg_pkg::*; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert and escalation signal + parameter int unsigned AlertSkewCycles = 1, + parameter int unsigned EscNumSeverities = 4, + parameter int unsigned EscPingCountWidth = 16 +) ( + // Clocks and resets + input clk_slow_i, + input clk_i, + input rst_slow_ni, + input rst_ni, + input rst_main_ni, + input clk_lc_i, + input rst_lc_ni, + input clk_esc_i, + input rst_esc_ni, + + // Bus Interface + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // AST interface + input pwr_ast_rsp_t pwr_ast_i, + output pwr_ast_req_t pwr_ast_o, + + // rstmgr interface + input pwr_rst_rsp_t pwr_rst_i, + output pwr_rst_req_t pwr_rst_o, + + // clkmgr interface + output pwr_clk_req_t pwr_clk_o, + input pwr_clk_rsp_t pwr_clk_i, + + // otp interface + input pwr_otp_rsp_t pwr_otp_i, + output pwr_otp_req_t pwr_otp_o, + + // life cycle interface + input lc_ctrl_pkg::pwr_lc_rsp_t pwr_lc_i, + output lc_ctrl_pkg::pwr_lc_req_t pwr_lc_o, + + // flash interface + input pwr_flash_t pwr_flash_i, + + // processor interface + input rv_core_ibex_pkg::cpu_pwrmgr_t pwr_cpu_i, + // SEC_CM: LC_CTRL.INTERSIG.MUBI + output lc_ctrl_pkg::lc_tx_t fetch_en_o, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + output pwr_boot_status_t boot_status_o, + // peripherals wakeup and reset requests + input [NumWkups-1:0] wakeups_i, + input [NumRstReqs-1:0] rstreqs_i, + + // cpu related inputs + input ndmreset_req_i, + + // pinmux and other peripherals + output logic strap_o, + output logic low_power_o, + + // rom_ctrl interface + // SEC_CM: ROM_CTRL.INTERSIG.MUBI + input rom_ctrl_pkg::pwrmgr_data_t [NumRomInputs-1:0] rom_ctrl_i, + + // software issued reset request + // SEC_CM: RSTMGR.INTERSIG.MUBI + input prim_mubi_pkg::mubi4_t sw_rst_req_i, + + // escalation interface + input prim_esc_pkg::esc_tx_t esc_rst_tx_i, + output prim_esc_pkg::esc_rx_t esc_rst_rx_o, + + output intr_wakeup_o + +); + //////////////////////////////////////////////////// + // Input handling // + //////////////////////////////////////////////////// + + logic ndmreset_req_q; + logic ndm_req_valid; + + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_ndm_sync ( + .clk_i, + .rst_ni, + .d_i(ndmreset_req_i), + .q_o(ndmreset_req_q) + ); + + assign ndm_req_valid = ndmreset_req_q; + + //////////////////////////// + /// escalation detections + //////////////////////////// + + logic clk_lc; + logic rst_lc_n; + assign clk_lc = clk_lc_i; + assign rst_lc_n = rst_lc_ni; + + logic clk_esc; + logic rst_esc_n; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_esc_clk_buf ( + .clk_i(clk_esc_i), + .clk_o(clk_esc) + ); + + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_esc_rst_buf ( + .clk_i(rst_esc_ni), + .clk_o(rst_esc_n) + ); + + logic esc_rst_req_d, esc_rst_req_q; + prim_esc_receiver #( + .N_ESC_SEV (EscNumSeverities), + .PING_CNT_DW (EscPingCountWidth), + .SkewCycles (AlertSkewCycles) + ) u_esc_rx ( + .clk_i(clk_esc), + .rst_ni(rst_esc_n), + .esc_req_o(esc_rst_req_d), + .esc_rx_o(esc_rst_rx_o), + .esc_tx_i(esc_rst_tx_i) + ); + + // These assertions use formal or simulation to prove that once esc_rst_req is latched, we expect + // to see the lc reset requests in pwr_rst_o. The one exception is when escalation requests are + // cancelled while the CPU fetch is disabled, meaning the fast fsm is inactive. +`ifdef SIMULATION + // In simulation mode, the prim_cdc_rand_delay module inserts a random one cycle delay to the + // two flop synchronizers. There are two CDCs in the path from escalation reset to the fast fsm + // receiving it, one to the slow clock, and one back to the fast one. And there are additional + // cycles in the fast fsm to generate outputs. However, esc_rst_req_q can be dropped due to + // rst_lc_n, which will cause slow_peri_reqs_masked.rstreqs[ResetEscIdx] to drop. + `ASSERT(PwrmgrSecCmEscToSlowResetReq_A, + esc_rst_req_q |-> ##[1:5] !esc_rst_req_q || slow_peri_reqs_masked.rstreqs[ResetEscIdx], + clk_slow_i, !rst_slow_ni) + `ASSERT(PwrmgrSecCmFsmEscToResetReq_A, + slow_peri_reqs_masked.rstreqs[ResetEscIdx] |-> + ##[1:4] !slow_peri_reqs_masked.rstreqs[ResetEscIdx] || u_fsm.reset_reqs_i[ResetEscIdx], + clk_i, !rst_ni) +`else + `ASSERT(PwrmgrSecCmEscToSlowResetReq_A, + esc_rst_req_d |-> ##[2:3] ( + (!esc_rst_req_d && lc_ctrl_pkg::lc_tx_test_false_loose(fetch_en_o)) || + slow_peri_reqs_masked.rstreqs[ResetEscIdx] + ), clk_slow_i, !rst_slow_ni) + `ASSERT(PwrmgrSlowResetReqToFsmResetReq_A, + slow_peri_reqs_masked.rstreqs[ResetEscIdx] |-> ##1 u_fsm.reset_reqs_i[ResetEscIdx], + clk_i, !rst_ni) +`endif + + `ASSERT(PwrmgrSecCmEscToLCReset_A, u_fsm.reset_reqs_i[ResetEscIdx] && + u_fsm.state_q == FastPwrStateActive |-> ##4 pwr_rst_o.rst_lc_req == 2'b11, + clk_i, !rst_ni) + + always_ff @(posedge clk_lc or negedge rst_lc_n) begin + if (!rst_lc_n) begin + esc_rst_req_q <= '0; + end else if (esc_rst_req_d) begin + // once latched, do not clear until reset + esc_rst_req_q <= 1'b1; + end + end + + localparam int EscTimeOutCnt = 128; + logic esc_timeout, esc_timeout_lc_d, esc_timeout_lc_q; + // SEC_CM: ESC_RX.CLK.BKGN_CHK, ESC_RX.CLK.LOCAL_ESC + prim_clock_timeout #( + .TimeOutCnt(EscTimeOutCnt) + ) u_esc_timeout ( + .clk_chk_i(clk_esc), + .rst_chk_ni(rst_esc_n), + .clk_i, + .rst_ni, + // if any ip clock enable is turned on, then the escalation + // clocks are also enabled. + .en_i(|pwr_clk_o), + .timeout_o(esc_timeout) + ); + + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_esc_timeout_sync ( + .clk_i(clk_lc), + .rst_ni(rst_lc_n), + .d_i(esc_timeout), + .q_o(esc_timeout_lc_d) + ); + + always_ff @(posedge clk_lc or negedge rst_lc_n) begin + if (!rst_lc_n) begin + esc_timeout_lc_q <= '0; + end else if (esc_timeout_lc_d) begin + // once latched, do not clear until reset + esc_timeout_lc_q <= 1'b1; + end + end + + + //////////////////////////// + /// async declarations + //////////////////////////// + pwr_peri_t peri_reqs_raw; + logic slow_rst_req; + + assign peri_reqs_raw.wakeups = wakeups_i; + assign peri_reqs_raw.rstreqs[NumRstReqs-1:0] = rstreqs_i; + assign peri_reqs_raw.rstreqs[ResetMainPwrIdx] = slow_rst_req; + // SEC_CM: ESC_RX.CLK.LOCAL_ESC, CTRL_FLOW.GLOBAL_ESC + assign peri_reqs_raw.rstreqs[ResetEscIdx] = esc_rst_req_q | esc_timeout_lc_q; + assign peri_reqs_raw.rstreqs[ResetNdmIdx] = ndm_req_valid; + + //////////////////////////// + /// Software reset request + //////////////////////////// + logic sw_rst_req; + prim_buf #( + .Width(1) + ) u_sw_req_buf ( + .in_i(prim_mubi_pkg::mubi4_test_true_strict(sw_rst_req_i)), + .out_o(sw_rst_req) + ); + + assign peri_reqs_raw.rstreqs[ResetSwReqIdx] = sw_rst_req; + + //////////////////////////// + /// clk_i domain declarations + //////////////////////////// + + pwrmgr_reg2hw_t reg2hw; + pwrmgr_hw2reg_t hw2reg; + pwr_peri_t peri_reqs_masked; + + logic req_pwrup; + logic ack_pwrup; + logic req_pwrdn; + logic ack_pwrdn; + logic fsm_invalid; + logic clr_slow_req; + pwrup_cause_e pwrup_cause; + + logic low_power_fall_through; + logic low_power_abort; + + pwr_flash_t flash_rsp; + pwr_otp_rsp_t otp_rsp; + + prim_mubi_pkg::mubi4_t [NumRomInputs-1:0] rom_ctrl_done_async; + prim_mubi_pkg::mubi4_t [NumRomInputs-1:0] rom_ctrl_done; + prim_mubi_pkg::mubi4_t rom_ctrl_done_combined; + prim_mubi_pkg::mubi4_t rom_ctrl_good_combined; + + logic core_sleeping; + logic low_power_entry; + + //////////////////////////// + /// clk_slow_i domain declarations + //////////////////////////// + + // Captured signals + // These signals, though on clk_i domain, are safe for clk_slow_i to use + logic [NumWkups-1:0] slow_wakeup_en; + logic [NumRstReqs-1:0] slow_reset_en; + + pwr_ast_rsp_t slow_ast; + pwr_peri_t slow_peri_reqs, slow_peri_reqs_masked; + + pwrup_cause_e slow_pwrup_cause; + logic slow_pwrup_cause_toggle; + logic slow_req_pwrup; + logic slow_ack_pwrup; + logic slow_req_pwrdn; + logic slow_ack_pwrdn; + logic slow_fsm_invalid; + logic slow_main_pd_n; + logic slow_main_clk_en; + logic slow_io_clk_en; + logic slow_clr_req; + + + + //////////////////////////// + /// Register module + //////////////////////////// + logic [NumAlerts-1:0] alert_test, alerts; + logic low_power_hint; + logic lowpwr_cfg_wen; + logic clr_hint; + logic wkup; + logic clr_cfg_lock; + logic reg_intg_err; + + // SEC_CM: BUS.INTEGRITY + // SEC_CM: CTRL.CONFIG.REGWEN, WAKEUP.CONFIG.REGWEN, RESET.CONFIG.REGWEN + pwrmgr_reg_top u_reg ( + .clk_i, + .rst_ni, + .clk_lc_i (clk_lc ), + .rst_lc_ni (rst_lc_n), + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + .intg_err_o (reg_intg_err) + ); + + // whenever low power entry begins, wipe the hint + assign hw2reg.control.low_power_hint.d = 1'b0; + assign hw2reg.control.low_power_hint.de = clr_hint; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + lowpwr_cfg_wen <= 1'b1; + end else if (!lowpwr_cfg_wen && (clr_cfg_lock || wkup)) begin + lowpwr_cfg_wen <= 1'b1; + end else if (low_power_entry) begin + lowpwr_cfg_wen <= 1'b0; + end + end + + assign hw2reg.ctrl_cfg_regwen.d = lowpwr_cfg_wen; + + assign hw2reg.fault_status.reg_intg_err.de = reg_intg_err; + assign hw2reg.fault_status.reg_intg_err.d = 1'b1; + assign hw2reg.fault_status.esc_timeout.de = esc_timeout_lc_q; + assign hw2reg.fault_status.esc_timeout.d = 1'b1; + + // The main power domain glitch automatically causes a reset, so regsitering + // an alert is functionally pointless. However, if an attacker somehow manages/ + // to silence the reset, this gives us one potential back-up path through alert_handler. + // Allow capture of main_pd fault status whenever the system is live. + assign hw2reg.fault_status.main_pd_glitch.de = pwr_clk_o.main_ip_clk_en; + assign hw2reg.fault_status.main_pd_glitch.d = peri_reqs_masked.rstreqs[ResetMainPwrIdx] | + reg2hw.fault_status.main_pd_glitch.q; + + `ASSERT(GlitchStatusPersist_A, $rose(reg2hw.fault_status.main_pd_glitch.q) |-> + reg2hw.fault_status.main_pd_glitch.q until !rst_lc_ni) + + //////////////////////////// + /// alerts + //////////////////////////// + + // the logic below assumes there is only one alert, so make an + // explicit assertion check for it. + `ASSERT_INIT(AlertNumCheck_A, NumAlerts == 1) + + assign alert_test = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; + + assign alerts[0] = reg2hw.fault_status.reg_intg_err.q | + reg2hw.fault_status.esc_timeout.q | + reg2hw.fault_status.main_pd_glitch.q; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .SkewCycles(AlertSkewCycles), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i ( clk_lc ), + .rst_ni ( rst_lc_n ), + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + //////////////////////////// + /// cdc handling + //////////////////////////// + + // Assign to array for convenience in CDC block below. + for (genvar k = 0; k < NumRomInputs; k ++) begin : gen_done_assign + assign rom_ctrl_done_async[k] = rom_ctrl_i[k].done; + end + + pwrmgr_cdc u_cdc ( + .clk_i, + .rst_ni, + .clk_slow_i, + .rst_slow_ni, + + // slow domain signals + .slow_req_pwrup_i(slow_req_pwrup), + .slow_ack_pwrdn_i(slow_ack_pwrdn), + .slow_fsm_invalid_i(slow_fsm_invalid), + .slow_pwrup_cause_toggle_i(slow_pwrup_cause_toggle), + .slow_pwrup_cause_i(slow_pwrup_cause), + .slow_wakeup_en_o(slow_wakeup_en), + .slow_reset_en_o(slow_reset_en), + .slow_main_pd_no(slow_main_pd_n), + .slow_main_clk_en_o(slow_main_clk_en), + .slow_io_clk_en_o(slow_io_clk_en), + .slow_req_pwrdn_o(slow_req_pwrdn), + .slow_ack_pwrup_o(slow_ack_pwrup), + .slow_ast_o(slow_ast), + .slow_peri_reqs_o(slow_peri_reqs), + .slow_peri_reqs_masked_i(slow_peri_reqs_masked), + .slow_clr_req_o(slow_clr_req), + + // fast domain signals + .req_pwrdn_i(req_pwrdn), + .ack_pwrup_i(ack_pwrup), + .cfg_cdc_sync_i(reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q), + .cdc_sync_done_o(hw2reg.cfg_cdc_sync.de), + .wakeup_en_i(reg2hw.wakeup_en), + .reset_en_i(reg2hw.reset_en), + .main_pd_ni(reg2hw.control.main_pd_n.q), + .main_clk_en_i(reg2hw.control.core_clk_en.q), + .io_clk_en_i(reg2hw.control.io_clk_en.q), + .ack_pwrdn_o(ack_pwrdn), + .fsm_invalid_o(fsm_invalid), + .req_pwrup_o(req_pwrup), + .pwrup_cause_o(pwrup_cause), + .peri_reqs_o(peri_reqs_masked), + .clr_slow_req_i(clr_slow_req), + + // AST signals + .ast_i(pwr_ast_i), + + // peripheral signals + .peri_i(peri_reqs_raw), + + // flash handshake + .flash_i(pwr_flash_i), + .flash_o(flash_rsp), + + // OTP signals + .otp_i(pwr_otp_i), + .otp_o(otp_rsp), + + // rom_ctrl signals + .rom_ctrl_done_i(rom_ctrl_done_async), + .rom_ctrl_done_o(rom_ctrl_done), + + // core sleeping + .core_sleeping_i(pwr_cpu_i.core_sleeping), + .core_sleeping_o(core_sleeping) + + ); + + always_comb begin + rom_ctrl_done_combined = prim_mubi_pkg::MuBi4True; + rom_ctrl_good_combined = prim_mubi_pkg::MuBi4True; + for (int k = 0; k < NumRomInputs; k++) begin + rom_ctrl_done_combined = + prim_mubi_pkg::mubi4_and_hi(rom_ctrl_done_combined, rom_ctrl_done[k]); + // rom_ctrl_i.good is not synchronized as it acts as a "payload" signal + // to "done". Good is only observed if "done" is high. + rom_ctrl_good_combined = + prim_mubi_pkg::mubi4_and_hi(rom_ctrl_good_combined, rom_ctrl_i[k].good); + end + end + + assign hw2reg.cfg_cdc_sync.d = 1'b0; + + //////////////////////////// + /// Wakup and reset capture + //////////////////////////// + + // reset and wakeup requests are captured into the slow clock domain and then + // fanned out to other domains as necessary. This ensures there is not a huge + // time gap between when the slow clk domain sees the signal vs when the fast + // clock domains see it. This creates redundant syncing but keeps the time + // scale approximately the same across all domains. + // + // This also implies that these signals must be at least 1 clk_slow pulse long + // + // Since resets are not latched inside pwrmgr, there exists a corner case where + // non-always-on reset requests may get wiped out by a graceful low power entry + // It's not clear if this is really an issue at the moment, but something to keep + // in mind if future changes are needed. + // + // Latching the reset requests is not difficult, but the bigger question is who + // should clear it and when that should happen. If the clearing does not work + // correctly, it is possible for the device to end up in a permanent reset loop, + // and that would be very undesirable. + + assign slow_peri_reqs_masked.wakeups = slow_peri_reqs.wakeups & slow_wakeup_en; + // msb is software request + // the internal requests include escalation and internal requests + // the lsbs are the software enabled peripheral requests. + assign slow_peri_reqs_masked.rstreqs = slow_peri_reqs.rstreqs & + {{NumSwRstReq{1'b1}}, + {NumDebugRstReqs{1'b1}}, + {NumIntRstReqs{1'b1}}, + slow_reset_en}; + logic strap_sampled; + logic internal_reset_req; + logic ext_reset_req; + + // Make the SoC see what the slow FSM sees to to generate the light_reset to the SoC + assign internal_reset_req = |slow_peri_reqs_masked.rstreqs; + + // The MSB of `slow_peri_reqs.rstreqs` is the external reset request. We want it to always + // propagate, in order to continue from the Reset Wait state in the fast FSM. + assign ext_reset_req = slow_peri_reqs.rstreqs[NumRstReqs-1]; + + for (genvar i = 0; i < NumWkups; i++) begin : gen_wakeup_status + assign hw2reg.wake_status[i].de = 1'b1; + assign hw2reg.wake_status[i].d = peri_reqs_masked.wakeups[i]; + end + + for (genvar i = 0; i < NumRstReqs; i++) begin : gen_reset_status + assign hw2reg.reset_status[i].de = 1'b1; + assign hw2reg.reset_status[i].d = peri_reqs_masked.rstreqs[i]; + end + + assign hw2reg.escalate_reset_status.de = 1'b1; + assign hw2reg.escalate_reset_status.d = peri_reqs_masked.rstreqs[NumRstReqs]; + + + //////////////////////////// + /// clk_slow FSM + //////////////////////////// + + pwrmgr_slow_fsm u_slow_fsm ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .rst_main_ni (rst_main_ni), + .wakeup_i (|slow_peri_reqs_masked.wakeups), + .reset_req_i (|slow_peri_reqs_masked.rstreqs), + .ast_i (slow_ast), + .req_pwrup_o (slow_req_pwrup), + .pwrup_cause_o (slow_pwrup_cause), + .pwrup_cause_toggle_o (slow_pwrup_cause_toggle), + .ack_pwrup_i (slow_ack_pwrup), + .req_pwrdn_i (slow_req_pwrdn), + .ack_pwrdn_o (slow_ack_pwrdn), + .rst_req_o (slow_rst_req), + .fsm_invalid_o (slow_fsm_invalid), + .clr_req_i (slow_clr_req), + + .main_pd_ni (slow_main_pd_n), + .main_clk_en_i (slow_main_clk_en), + .io_clk_en_i (slow_io_clk_en), + + // outputs to AST - These are on the slow clock domain + // TBD - need to check this with partners + .ast_o (pwr_ast_o) + ); + + lc_ctrl_pkg::lc_tx_t lc_dft_en; + prim_lc_sync u_prim_lc_sync_dft_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_dft_en_i), + .lc_en_o({lc_dft_en}) + ); + + lc_ctrl_pkg::lc_tx_t lc_hw_debug_en; + prim_lc_sync u_prim_lc_sync_hw_debug_en ( + .clk_i, + .rst_ni, + .lc_en_i(lc_hw_debug_en_i), + .lc_en_o({lc_hw_debug_en}) + ); + + //////////////////////////// + /// clk FSM + //////////////////////////// + + assign low_power_hint = reg2hw.control.low_power_hint.q == LowPower; + assign low_power_entry = core_sleeping & low_power_hint; + + pwrmgr_fsm u_fsm ( + .clk_i, + .rst_ni, + .clk_slow_i, + .rst_slow_ni, + + // interface with slow_fsm + .req_pwrup_i (req_pwrup), + .pwrup_cause_i (pwrup_cause), // por, wake or reset request + .ack_pwrup_o (ack_pwrup), + .req_pwrdn_o (req_pwrdn), + .ack_pwrdn_i (ack_pwrdn), + .low_power_entry_i (low_power_entry), + .reset_reqs_i (peri_reqs_masked.rstreqs), + .fsm_invalid_i (fsm_invalid), + .clr_slow_req_o (clr_slow_req), + + // cfg + .main_pd_ni (reg2hw.control.main_pd_n.q), + + // consumed in pwrmgr + .wkup_o (wkup), + .clr_cfg_lock_o (clr_cfg_lock), + .fall_through_o (low_power_fall_through), + .abort_o (low_power_abort), + .clr_hint_o (clr_hint), + .int_reset_req_i (internal_reset_req), + .ext_reset_req_i (ext_reset_req), + + // rstmgr + .pwr_rst_o (pwr_rst_o), + .pwr_rst_i (pwr_rst_i), + + // clkmgr + .ips_clk_en_o (pwr_clk_o), + .clk_en_status_i (pwr_clk_i), + + // otp + .otp_init_o (pwr_otp_o.otp_init), + .otp_done_i (otp_rsp.otp_done), + .otp_idle_i (otp_rsp.otp_idle), + + // lc + .lc_init_o (pwr_lc_o.lc_init), + .lc_done_i (pwr_lc_i.lc_done), + .lc_idle_i (pwr_lc_i.lc_idle), + .lc_dft_en_i (lc_dft_en), + .lc_hw_debug_en_i (lc_hw_debug_en), + + // flash + .flash_idle_i (flash_rsp.flash_idle), + + // rom_ctrl + .rom_ctrl_done_i (rom_ctrl_done_combined), + .rom_ctrl_good_i (rom_ctrl_good_combined), + + // processing element + .fetch_en_o, + + // pinmux and other peripherals + .strap_o, + .strap_sampled_o (strap_sampled), // to debug monitoring logic + .low_power_o + ); + + //////////////////////////// + /// Wakeup Info Capture + //////////////////////////// + + logic wake_info_wen; + logic [TotalWakeWidth-1:0] wake_info_data; + + assign wake_info_wen = reg2hw.wake_info.abort.qe | + reg2hw.wake_info.fall_through.qe | + reg2hw.wake_info.reasons.qe; + + assign wake_info_data = {reg2hw.wake_info.abort.q, + reg2hw.wake_info.fall_through.q, + reg2hw.wake_info.reasons.q}; + + pwrmgr_wake_info i_wake_info ( + .clk_i, + .rst_ni, + .wr_i (wake_info_wen), + .data_i (wake_info_data), + .start_capture_i (low_power_o), + .record_dis_i (reg2hw.wake_info_capture_dis.q), + .wakeups_i (peri_reqs_masked.wakeups), + .fall_through_i (low_power_fall_through), + .abort_i (low_power_abort), + .info_o (hw2reg.wake_info) + ); + + //////////////////////////// + /// Interrupts + //////////////////////////// + + // This interrupt is asserted whenever the fast FSM transitions + // into active state. However, it does not assert during POR + prim_intr_hw #(.Width(1)) intr_wakeup ( + .clk_i, + .rst_ni, + .event_intr_i (wkup), + .reg2hw_intr_enable_q_i (reg2hw.intr_enable.q), + .reg2hw_intr_test_q_i (reg2hw.intr_test.q), + .reg2hw_intr_test_qe_i (reg2hw.intr_test.qe), + .reg2hw_intr_state_q_i (reg2hw.intr_state.q), + .hw2reg_intr_state_de_o (hw2reg.intr_state.de), + .hw2reg_intr_state_d_o (hw2reg.intr_state.d), + .intr_o (intr_wakeup_o) + ); + + //////////////////////////////////////////////////// + // Routing status signal outputs for monitoring + //////////////////////////////////////////////////// + assign boot_status_o.cpu_fetch_en = fetch_en_o; + assign boot_status_o.rom_ctrl_status = rom_ctrl_i; + assign boot_status_o.lc_done = pwr_lc_i.lc_done; + assign boot_status_o.otp_done = otp_rsp.otp_done; + assign boot_status_o.clk_status = pwr_clk_i; + assign boot_status_o.light_reset_req = internal_reset_req; + assign boot_status_o.strap_sampled = strap_sampled; + + //////////////////////////// + /// Assertions + //////////////////////////// + + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid ) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready ) + `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o ) + `ASSERT_KNOWN(AstKnownO_A, pwr_ast_o ) + `ASSERT_KNOWN(RstKnownO_A, pwr_rst_o ) + `ASSERT_KNOWN(ClkKnownO_A, pwr_clk_o ) + `ASSERT_KNOWN(OtpKnownO_A, pwr_otp_o ) + `ASSERT_KNOWN(LcKnownO_A, pwr_lc_o ) + `ASSERT_KNOWN(IntrKnownO_A, intr_wakeup_o ) + + // EscTimeOutCnt also sets the required clock ratios between escalator and local clock + // Ie, clk_lc cannot be so slow that the timeout count is reached + `ifdef INC_ASSERT + //VCS coverage off + // pragma coverage off + logic effective_rst_n; + assign effective_rst_n = clk_lc_i && rst_ni; + + logic [31:0] cnt; + always_ff @(posedge clk_i or negedge effective_rst_n) begin + if (!effective_rst_n) begin + cnt <= '0; + end else begin + cnt <= cnt + 1'b1; + end + end + //VCS coverage on + // pragma coverage on + + `ASSERT(ClkRatio_A, cnt < EscTimeOutCnt) + + `endif + + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(FsmCheck_A, u_fsm.u_state_regs, + pwr_rst_o.rst_lc_req && pwr_rst_o.rst_sys_req) + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ERR(SlowFsmCheck_A, u_slow_fsm.u_state_regs, + pwr_ast_o.pwr_clamp && !pwr_ast_o.main_pd_n, 0, 2, + clk_slow_i, !rst_slow_ni) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) +endmodule // pwrmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_cdc.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_cdc.sv new file mode 100644 index 00000000000..8c8939d97d2 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_cdc.sv @@ -0,0 +1,307 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager CDC handling +// + +`include "prim_assert.sv" + +module pwrmgr_cdc import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*; +( + // Clocks and resets + input clk_slow_i, + input clk_i, + input rst_slow_ni, + input rst_ni, + + // slow domain signals, + input slow_req_pwrup_i, + input slow_ack_pwrdn_i, + input slow_fsm_invalid_i, + input slow_pwrup_cause_toggle_i, + input pwrup_cause_e slow_pwrup_cause_i, + output logic [NumWkups-1:0] slow_wakeup_en_o, + output logic [NumRstReqs-1:0] slow_reset_en_o, + output logic slow_main_pd_no, + output logic slow_main_clk_en_o, + output logic slow_io_clk_en_o, + output logic slow_req_pwrdn_o, + output logic slow_ack_pwrup_o, + output pwr_ast_rsp_t slow_ast_o, + output pwr_peri_t slow_peri_reqs_o, + input pwr_peri_t slow_peri_reqs_masked_i, + output logic slow_clr_req_o, + + // fast domain signals + input req_pwrdn_i, + input ack_pwrup_i, + input cfg_cdc_sync_i, + input [NumWkups-1:0] wakeup_en_i, + input logic [NumRstReqs-1:0] reset_en_i, + input main_pd_ni, + input main_clk_en_i, + input io_clk_en_i, + output logic ack_pwrdn_o, + output logic fsm_invalid_o, + output logic req_pwrup_o, + output pwrup_cause_e pwrup_cause_o, + output pwr_peri_t peri_reqs_o, + output logic cdc_sync_done_o, + input clr_slow_req_i, + + // peripheral inputs, mixed domains + input pwr_peri_t peri_i, + input pwr_flash_t flash_i, + output pwr_flash_t flash_o, + + // otp interface + input pwr_otp_rsp_t otp_i, + output pwr_otp_rsp_t otp_o, + + // AST inputs, unknown domain + input pwr_ast_rsp_t ast_i, + + // rom_ctrl signals + input prim_mubi_pkg::mubi4_t [NumRomInputs-1:0] rom_ctrl_done_i, + output prim_mubi_pkg::mubi4_t [NumRomInputs-1:0] rom_ctrl_done_o, + + // core sleeping + input core_sleeping_i, + output logic core_sleeping_o + +); + + //////////////////////////////// + // Sync from clk_i to clk_slow_i + //////////////////////////////// + + logic slow_cdc_sync; + pwr_ast_rsp_t slow_ast_q, slow_ast_q2; + + prim_flop_2sync # ( + .Width(1) + ) u_req_pwrdn_sync ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(req_pwrdn_i), + .q_o(slow_req_pwrdn_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ack_pwrup_sync ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(ack_pwrup_i), + .q_o(slow_ack_pwrup_o) + ); + + prim_pulse_sync u_slow_cdc_sync ( + .clk_src_i(clk_i), + .rst_src_ni(rst_ni), + .src_pulse_i(cfg_cdc_sync_i), + .clk_dst_i(clk_slow_i), + .rst_dst_ni(rst_slow_ni), + .dst_pulse_o(slow_cdc_sync) + ); + + // Even though this is multi-bit, the bits are individual request lines. + // So there is no general concern about recombining as there is + // no intent to use them in a related manner. + prim_flop_2sync # ( + .Width($bits(pwr_peri_t)) + ) u_slow_ext_req_sync ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .d_i (peri_i), + .q_o (slow_peri_reqs_o) + ); + + + // Some of the AST signals are multi-bits themselves (such as clk_val) + // thus they need to be delayed one more stage to check for stability + prim_flop_2sync # ( + .Width($bits(pwr_ast_rsp_t)), + .ResetValue(PWR_AST_RSP_SYNC_DEFAULT) + ) u_ast_sync ( + .clk_i (clk_slow_i), + .rst_ni (rst_slow_ni), + .d_i (ast_i), + .q_o (slow_ast_q) + ); + + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_ast_q2 <= PWR_AST_RSP_SYNC_DEFAULT; + end else begin + slow_ast_q2 <= slow_ast_q; + end + end + + // if possible, we should simulate below with random delays through + // flop_2sync + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_ast_o <= PWR_AST_RSP_SYNC_DEFAULT; + end else if (slow_ast_q2 == slow_ast_q) begin + // Output only updates whenever sync and delayed outputs both agree. + // If there are delays in sync, this will result in a 1 cycle difference + // and the output will hold the previous value + slow_ast_o <= slow_ast_q2; + end + end + + // only register configurations can be sync'd using slow_cdc_sync + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_wakeup_en_o <= '0; + slow_reset_en_o <= '0; + slow_main_pd_no <= '1; + slow_main_clk_en_o <= '0; + slow_io_clk_en_o <= '0; + end else if (slow_cdc_sync) begin + slow_wakeup_en_o <= wakeup_en_i; + slow_reset_en_o <= reset_en_i; + slow_main_pd_no <= main_pd_ni; + slow_main_clk_en_o <= main_clk_en_i; + slow_io_clk_en_o <= io_clk_en_i; + end + end + + //////////////////////////////// + // Sync from clk_slow_i to clk_i + //////////////////////////////// + + logic pwrup_cause_toggle_q, pwrup_cause_toggle_q2; + logic pwrup_cause_chg; + + prim_flop_2sync # ( + .Width(1) + ) u_req_pwrup_sync ( + .clk_i, + .rst_ni, + .d_i(slow_req_pwrup_i), + .q_o(req_pwrup_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_ack_pwrdn_sync ( + .clk_i, + .rst_ni, + .d_i(slow_ack_pwrdn_i), + .q_o(ack_pwrdn_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_int_fsm_invalid_sync ( + .clk_i, + .rst_ni, + .d_i(slow_fsm_invalid_i), + .q_o(fsm_invalid_o) + ); + + prim_flop_2sync # ( + .Width(1) + ) u_pwrup_chg_sync ( + .clk_i, + .rst_ni, + .d_i(slow_pwrup_cause_toggle_i), + .q_o(pwrup_cause_toggle_q) + ); + + + prim_flop_2sync # ( + .Width(1) + ) u_sleeping_sync ( + .clk_i, + .rst_ni, + .d_i(core_sleeping_i), + .q_o(core_sleeping_o) + ); + + prim_pulse_sync u_scdc_sync ( + .clk_src_i(clk_slow_i), + .rst_src_ni(rst_slow_ni), + .src_pulse_i(slow_cdc_sync), + .clk_dst_i(clk_i), + .rst_dst_ni(rst_ni), + .dst_pulse_o(cdc_sync_done_o) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pwrup_cause_toggle_q2 <= 1'b0; + end else begin + pwrup_cause_toggle_q2 <= pwrup_cause_toggle_q; + end + end + + assign pwrup_cause_chg = pwrup_cause_toggle_q2 ^ pwrup_cause_toggle_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + pwrup_cause_o <= Por; + end else if (pwrup_cause_chg) begin + pwrup_cause_o <= slow_pwrup_cause_i; + end + end + + prim_flop_2sync #( + .Width($bits(pwr_peri_t)) + ) u_ext_req_sync ( + .clk_i, + .rst_ni, + .d_i(slow_peri_reqs_masked_i), + .q_o(peri_reqs_o) + ); + + prim_flop_2sync #( + .Width(1), + .ResetValue(1'b1) + ) u_sync_flash_idle ( + .clk_i, + .rst_ni, + .d_i(flash_i.flash_idle), + .q_o(flash_o.flash_idle) + ); + + prim_flop_2sync #( + .Width($bits(pwr_otp_rsp_t)), + .ResetValue('0) + ) u_sync_otp ( + .clk_i, + .rst_ni, + .d_i(otp_i), + .q_o(otp_o) + ); + + for (genvar k = 0; k < NumRomInputs; k++) begin : gen_rom_inputs + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(1), + .StabilityCheck(1) + ) u_sync_rom_ctrl ( + .clk_i, + .rst_ni, + .mubi_i(rom_ctrl_done_i[k]), + .mubi_o({rom_ctrl_done_o[k]}) + ); + end + + //////////////////////////////// + // Handshake + //////////////////////////////// + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_clr_req_sync ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(clr_slow_req_i), + .q_o(slow_clr_req_o) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_cdc_pulse.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_cdc_pulse.sv new file mode 100644 index 00000000000..ad7c501439e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_cdc_pulse.sv @@ -0,0 +1,91 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager module to find slow clock edges +// The clock is not used directly to avoid STA issues, instead a toggle +// pulse is used. + +`include "prim_assert.sv" + +module pwrmgr_cdc_pulse ( + input clk_slow_i, + input clk_i, + input rst_ni, + input rst_slow_ni, + input start_i, + input stop_i, + output logic pulse_o +); + + logic slow_toggle_pq, slow_toggle_nq; + logic clk_slow_pq, clk_slow_nq; + logic clk_slow_pq2, clk_slow_nq2; + logic toggle; + logic valid; + + // toggle pulse generated on positive edge + always_ff @(posedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_toggle_pq <= 1'b0; + end else begin + slow_toggle_pq <= ~slow_toggle_pq; + end + end + + // toggle pulse generated on negative edge + always_ff @(negedge clk_slow_i or negedge rst_slow_ni) begin + if (!rst_slow_ni) begin + slow_toggle_nq <= 1'b0; + end else begin + slow_toggle_nq <= ~slow_toggle_nq; + end + end + + + prim_flop_2sync # ( + .Width(1) + ) i_pos_sync ( + .clk_i, + .rst_ni, + .d_i(slow_toggle_pq), + .q_o(clk_slow_pq) + ); + + prim_flop_2sync # ( + .Width(1) + ) i_neg_sync ( + .clk_i, + .rst_ni, + .d_i(slow_toggle_nq), + .q_o(clk_slow_nq) + ); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + clk_slow_pq2 <= 1'b0; + clk_slow_nq2 <= 1'b0; + end else begin + clk_slow_pq2 <= clk_slow_pq; + clk_slow_nq2 <= clk_slow_nq; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + valid <= 1'b0; + end else if (valid && stop_i) begin + valid <= 1'b0; + end else if (!valid && toggle && start_i) begin + valid <= 1'b1; + end + end + + // toggle is found on either positive and negative edges of clk_slow_i + assign toggle = clk_slow_pq2 ^ clk_slow_pq | clk_slow_nq2 ^ clk_slow_nq; + assign pulse_o = valid & toggle; + + + + +endmodule // pwrmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_fsm.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_fsm.sv new file mode 100644 index 00000000000..beff4fb9bb4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_fsm.sv @@ -0,0 +1,563 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Fast FSM +// + +`include "prim_assert.sv" + +module pwrmgr_fsm import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*;( + input clk_i, + input rst_ni, + input clk_slow_i, + input rst_slow_ni, + + // interface with slow_fsm + input req_pwrup_i, + input pwrup_cause_e pwrup_cause_i, + output logic ack_pwrup_o, + output logic req_pwrdn_o, + input ack_pwrdn_i, + input low_power_entry_i, + input main_pd_ni, + input [TotalResetWidth-1:0] reset_reqs_i, + input fsm_invalid_i, + output logic clr_slow_req_o, + + // consumed in pwrmgr + output logic wkup_o, // generate wake interrupt + output logic fall_through_o, + output logic abort_o, + output logic clr_hint_o, + output logic clr_cfg_lock_o, + input logic int_reset_req_i, // internally generated reset request. + // Send to platform to assert reset + input logic ext_reset_req_i, // Internal Req held until ext reset deasserts + + // rstmgr + output pwr_rst_req_t pwr_rst_o, + input pwr_rst_rsp_t pwr_rst_i, + + // clkmgr + output pwr_clk_req_t ips_clk_en_o, + input pwr_clk_rsp_t clk_en_status_i, + + // otp + output logic otp_init_o, + input otp_done_i, + input otp_idle_i, + + // lc + output logic lc_init_o, + input lc_done_i, + input lc_idle_i, + input lc_ctrl_pkg::lc_tx_t lc_dft_en_i, + input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, + + // flash + input flash_idle_i, + + // rom_ctrl + input prim_mubi_pkg::mubi4_t rom_ctrl_done_i, + input prim_mubi_pkg::mubi4_t rom_ctrl_good_i, + + // pinmux + output logic strap_o, + output logic strap_sampled_o, + output logic low_power_o, + + // processing elements + output lc_ctrl_pkg::lc_tx_t fetch_en_o +); + + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::mubi4_test_true_strict; + import prim_mubi_pkg::mubi4_or_hi; + import prim_mubi_pkg::mubi4_and_hi; + import lc_ctrl_pkg::lc_tx_and_hi; + import lc_ctrl_pkg::lc_tx_test_true_strict; + + // The code below always assumes the always on domain is index 0 + `ASSERT_INIT(AlwaysOnIndex_A, ALWAYS_ON_DOMAIN == 0) + + // when there are multiple on domains, the latter 1 should become another parameter + localparam int OffDomainSelStart = ALWAYS_ON_DOMAIN + 1; + + // all powered down domains have resets asserted + logic pd_n_rsts_asserted; + + // all domains have resets asserted + logic all_rsts_asserted; + + // resets are valid + logic reset_valid; + + // reset hint to rstmgr + reset_cause_e reset_cause_q, reset_cause_d; + + // reset request + logic reset_req; + logic direct_rst_req; + logic ndmreset_req; + logic hw_rst_req; + logic sw_rst_req; + + // strap sample should only happen on cold boot or when the + // the system goes through a reset cycle + + // disable processing element fetching + lc_ctrl_pkg::lc_tx_t fetch_en_q, fetch_en_d; + + fast_pwr_state_e state_d, state_q; + logic reset_ongoing_q, reset_ongoing_d; + logic req_pwrdn_q, req_pwrdn_d; + logic ack_pwrup_q, ack_pwrup_d; + logic ip_clk_en_q, ip_clk_en_d; + logic [PowerDomains-1:0] rst_lc_req_q, rst_sys_req_q; + logic [PowerDomains-1:0] rst_lc_req_d, rst_sys_req_d; + logic otp_init; + logic lc_init; + logic low_power_q, low_power_d; + + assign pd_n_rsts_asserted = pwr_rst_i.rst_lc_src_n[PowerDomains-1:OffDomainSelStart] == '0 & + pwr_rst_i.rst_sys_src_n[PowerDomains-1:OffDomainSelStart] == '0; + + logic lc_rsts_valid; + assign lc_rsts_valid = ((rst_lc_req_q & ~pwr_rst_i.rst_lc_src_n) | + (~rst_lc_req_q & pwr_rst_i.rst_lc_src_n)) == {PowerDomains{1'b1}}; + logic sys_rsts_valid; + assign sys_rsts_valid = ((rst_sys_req_q & ~pwr_rst_i.rst_sys_src_n) | + (~rst_sys_req_q & pwr_rst_i.rst_sys_src_n)) == {PowerDomains{1'b1}}; + + assign all_rsts_asserted = lc_rsts_valid & sys_rsts_valid; + + // Any reset request was asserted. + assign reset_req = |reset_reqs_i; + + // Any peripheral triggererd hardware reset request. + assign hw_rst_req = |reset_reqs_i[NumRstReqs-1:0]; + + // Direct reset request that bypass checks. + assign direct_rst_req = reset_reqs_i[ResetEscIdx] | + reset_reqs_i[ResetMainPwrIdx]; + + // Ndm reset request. + assign ndmreset_req = reset_reqs_i[ResetNdmIdx]; + + // Software triggered reset request. + assign sw_rst_req = reset_reqs_i[ResetSwReqIdx]; + + // when in low power path, resets are controlled by domain power down + // when in reset path, all resets must be asserted + // when the reset cause is something else, it is invalid + assign reset_valid = reset_cause_q == LowPwrEntry ? main_pd_ni | pd_n_rsts_asserted : + reset_cause_q == HwReq ? all_rsts_asserted : 1'b0; + + // Provide the ability to control the reset to OpenTitan RoT from an external source. The logic + // below makes sure that when an internal reset request is generated, it is held high until the + // external SoC reset logic asserts and then deasserts deasserts the external reset signal. The + // pwrmgr fast FSM is held in FastPwrStateResetWait state until the external reset deasserts. + // This ensure that the OT reset exit is synchronized with the rest of the SoC & platform. + logic ext_rst_req_d, ext_rst_req_q; + logic ext_rst_pending_d, ext_rst_pending_q; + + always_comb begin + ext_rst_req_d = ext_reset_req_i; + ext_rst_pending_d = ext_rst_pending_q; + + if (ext_rst_pending_q && !ext_rst_req_d && ext_rst_req_q) begin + ext_rst_pending_d = 1'b0; + end else if (int_reset_req_i) begin + ext_rst_pending_d = 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ext_rst_req_q <= 1'b0; + ext_rst_pending_q <= 1'b0; + end else begin + ext_rst_req_q <= ext_rst_req_d; + ext_rst_pending_q <= ext_rst_pending_d; + end + end + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ack_pwrup_q <= 1'b0; + req_pwrdn_q <= 1'b0; + reset_ongoing_q <= 1'b0; + ip_clk_en_q <= 1'b0; + rst_lc_req_q <= {PowerDomains{1'b1}}; + rst_sys_req_q <= {PowerDomains{1'b1}}; + reset_cause_q <= ResetUndefined; + low_power_q <= 1'b1; + end else begin + ack_pwrup_q <= ack_pwrup_d; + req_pwrdn_q <= req_pwrdn_d; + reset_ongoing_q <= reset_ongoing_d; + ip_clk_en_q <= ip_clk_en_d; + rst_lc_req_q <= rst_lc_req_d; + rst_sys_req_q <= rst_sys_req_d; + reset_cause_q <= reset_cause_d; + low_power_q <= low_power_d; + end + end + + // SEC_CM: FSM.SPARSE + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, fast_pwr_state_e, FastPwrStateLowPower) + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + strap_sampled_o <= 1'b0; + end else if (&rst_sys_req_q) begin + strap_sampled_o <= 1'b0; + end else if (strap_o) begin + strap_sampled_o <= 1'b1; + end + end + + prim_lc_sender u_fetch_en ( + .clk_i, + .rst_ni, + .lc_en_i(fetch_en_d), + .lc_en_o(fetch_en_q) + ); + assign fetch_en_o = fetch_en_q; + + // Life cycle broadcast may take time to propagate through the system. + // The sync below simulates that behavior using the slowest clock in the + // system. + logic slow_lc_done; + logic lc_done; + + prim_flop_2sync #( + .Width(1) + ) u_slow_sync_lc_done ( + .clk_i(clk_slow_i), + .rst_ni(rst_slow_ni), + .d_i(lc_done_i), + .q_o(slow_lc_done) + ); + + prim_flop_2sync #( + .Width(1) + ) u_sync_lc_done ( + .clk_i, + .rst_ni, + .d_i(slow_lc_done), + .q_o(lc_done) + ); + + + logic clks_enabled; + logic clks_disabled; + + // clocks all enabled computed as follows: + // if enable is high, meaning clock is requested to turn on, the status must + // also be 1. + // if enable is low, meaning clock is not requested to turn on, the status is + // don't care. + // the bit-wise OR of both conditions must be all true. + assign clks_enabled = ip_clk_en_q && + &((ips_clk_en_o & clk_en_status_i) | ~ips_clk_en_o); + + // clocks all disabled is the opposite: + // if enable is low the status must also be low. + // if enable is high, the status is don't care. + // the bit-wise OR of both conditions must be all true. + assign clks_disabled = ~ip_clk_en_q && + &((~ips_clk_en_o & ~clk_en_status_i) | ips_clk_en_o); + + + // rom integrity checks are disabled during TEST / RMA states + // During TEST / RMA states, both dft_en and hw_debug_en are On. + // During DEV / PROD states, either both signals are Off, or only + // hw_debug_en is On + + mubi4_t rom_intg_chk_dis; + assign rom_intg_chk_dis = lc_tx_test_true_strict(lc_tx_and_hi(lc_dft_en_i, lc_hw_debug_en_i)) ? + prim_mubi_pkg::MuBi4True : + prim_mubi_pkg::MuBi4False; + + mubi4_t rom_intg_chk_done; + mubi4_t rom_intg_chk_good; + assign rom_intg_chk_done = mubi4_or_hi(mubi4_and_hi(rom_intg_chk_dis, rom_ctrl_done_i), + rom_ctrl_done_i); + assign rom_intg_chk_good = mubi4_or_hi(rom_intg_chk_dis, rom_ctrl_good_i); + + always_comb begin + otp_init = 1'b0; + lc_init = 1'b0; + wkup_o = 1'b0; + fall_through_o = 1'b0; + abort_o = 1'b0; + clr_hint_o = 1'b0; + clr_cfg_lock_o = 1'b0; + strap_o = 1'b0; + clr_slow_req_o = 1'b0; + + state_d = state_q; + ack_pwrup_d = ack_pwrup_q; + req_pwrdn_d = req_pwrdn_q; + reset_ongoing_d = reset_ongoing_q; + ip_clk_en_d = ip_clk_en_q; + rst_lc_req_d = rst_lc_req_q; + rst_sys_req_d = rst_sys_req_q; + reset_cause_d = reset_cause_q; + low_power_d = low_power_q; + fetch_en_d = fetch_en_q; + + unique case(state_q) + + FastPwrStateLowPower: begin + if (req_pwrup_i || reset_ongoing_q) begin + state_d = FastPwrStateEnableClocks; + end + end + + FastPwrStateEnableClocks: begin + ip_clk_en_d = 1'b1; + if (clks_enabled) begin + state_d = FastPwrStateReleaseLcRst; + end + end + + FastPwrStateReleaseLcRst: begin + rst_lc_req_d = '0; // release rst_lc_n for all power domains + rst_sys_req_d = '0; // release rst_sys_n for all power domains + // once all resets are released continue to otp initialization + if (&pwr_rst_i.rst_lc_src_n) begin + state_d = FastPwrStateOtpInit; + end + end + + FastPwrStateOtpInit: begin + otp_init = 1'b1; + + if (otp_done_i) begin + state_d = FastPwrStateLcInit; + end + end + + FastPwrStateLcInit: begin + lc_init = 1'b1; + + if (lc_done) begin + state_d = FastPwrStateAckPwrUp; + + end + end + + FastPwrStateAckPwrUp: begin + // only ack the slow_fsm if we actually transitioned through it + ack_pwrup_d = !reset_ongoing_q; + + // wait for request power up to drop relative to ack + if (!req_pwrup_i || reset_ongoing_q) begin + ack_pwrup_d = 1'b0; + clr_cfg_lock_o = 1'b1; + // generate a wakeup interrupt if we intended to go to low power + // and we were woken from low power with a wakeup and not reset + wkup_o = (pwrup_cause_i == Wake) & (reset_cause_q == LowPwrEntry); + // This constitutes the end of a reset cycle + reset_ongoing_d = 1'b0; + state_d = FastPwrStateStrap; + end + end + + FastPwrStateStrap: begin + strap_o = ~strap_sampled_o; + state_d = FastPwrStateRomCheckDone; + end + + FastPwrStateRomCheckDone: begin + // zero outgoing low power indication + low_power_d = '0; + reset_cause_d = ResetNone; + + // When done is observed, advance to good check + if (mubi4_test_true_strict(rom_intg_chk_done)) begin + state_d = FastPwrStateRomCheckGood; + end + end + + FastPwrStateRomCheckGood: begin + if (mubi4_test_true_strict(rom_intg_chk_good)) begin + state_d = FastPwrStateActive; + end + end + + FastPwrStateActive: begin + // only in active state, allow processor to execute + fetch_en_d = lc_ctrl_pkg::On; + + // when handling reset request or low power entry of any + // kind, stop processor from fetching + if (reset_req || low_power_entry_i) begin + fetch_en_d = lc_ctrl_pkg::Off; + reset_cause_d = ResetUndefined; + state_d = FastPwrStateDisClks; + end + end + + FastPwrStateDisClks: begin + ip_clk_en_d = 1'b0; + + if (clks_disabled) begin + state_d = reset_req ? FastPwrStateNvmShutDown : FastPwrStateFallThrough; + low_power_d = ~reset_req; + end else begin + // escalation was received, skip all handshaking and directly reset + state_d = direct_rst_req ? FastPwrStateNvmShutDown : state_q; + low_power_d = ~reset_req; + end + end + + // Low Power Path + FastPwrStateFallThrough: begin + clr_hint_o = 1'b1; + + // The processor was interrupted after it asserted WFI and is executing again + if (!low_power_entry_i) begin + ip_clk_en_d = 1'b1; + wkup_o = 1'b1; + fall_through_o = 1'b1; + state_d = FastPwrStateRomCheckDone; + end else begin + state_d = FastPwrStateNvmIdleChk; + end + end + + FastPwrStateNvmIdleChk: begin + + if (otp_idle_i && lc_idle_i && flash_idle_i) begin + state_d = FastPwrStateLowPowerPrep; + end else begin + ip_clk_en_d = 1'b1; + wkup_o = 1'b1; + abort_o = 1'b1; + state_d = FastPwrStateRomCheckDone; + end + end + + FastPwrStateLowPowerPrep: begin + // reset cause is set only if main power domain will be turned off + reset_cause_d = LowPwrEntry; + + // reset non-always-on domains if requested + // this includes the clock manager, which implies pwr/rst managers must + // be fed directly from the source + for (int i = OffDomainSelStart; i < PowerDomains; i++) begin + rst_lc_req_d[i] = ~main_pd_ni; + rst_sys_req_d[i] = ~main_pd_ni; + end + + if (reset_valid) begin + state_d = FastPwrStateReqPwrDn; + end + end + + FastPwrStateReqPwrDn: begin + req_pwrdn_d = 1'b1; + + if (ack_pwrdn_i) begin + req_pwrdn_d = 1'b0; + state_d = FastPwrStateLowPower; + end + end + + // Reset Path + FastPwrStateNvmShutDown: begin + clr_hint_o = 1'b1; + reset_ongoing_d = 1'b1; + state_d = FastPwrStateResetPrep; + end + + FastPwrStateResetPrep: begin + reset_cause_d = HwReq; + rst_lc_req_d = {PowerDomains{1'b1}}; + rst_sys_req_d = {PowerDomains{(hw_rst_req | + direct_rst_req | + sw_rst_req) | + (ndmreset_req & + lc_ctrl_pkg::lc_tx_test_false_loose(lc_hw_debug_en_i))}}; + + + state_d = FastPwrStateResetWait; + end + + FastPwrStateResetWait: begin + rst_lc_req_d = {PowerDomains{1'b1}}; + clr_slow_req_o = reset_reqs_i[ResetMainPwrIdx]; + // The main power reset request is checked here specifically because it is + // the only reset request in the system that operates on the POR domain. + // This has to be the case since it would otherwise not be able to monitor + // the non-always-on domains. + // + // As a result of this, the normal reset process does not automatically + // wipe out the reset request, so we specifically clear it and wait for it to be + // cleared before proceeding. This also implies if the system is under a persistent + // glitch, or if someone just turned off the power before pwrmgr turns it off itself, + // we will stay stuck here and perpetually hold the system in reset. + // Need to hold in reset until external reset deasserts (i.e. ext_rst_pending_q goes low) + if (reset_valid && !reset_reqs_i[ResetMainPwrIdx] && !ext_rst_pending_q) begin + state_d = FastPwrStateLowPower; + end + end + + + // Terminal state, kill everything + // SEC_CM: FSM.TERMINAL + default: begin + rst_lc_req_d = {PowerDomains{1'b1}}; + rst_sys_req_d = {PowerDomains{1'b1}}; + ip_clk_en_d = 1'b0; + end + endcase // unique case (state_q) + + if (fsm_invalid_i) begin + // the slow fsm is completely out of sync, transition to terminal state + state_d = FastPwrStateInvalid; + end + + + end // always_comb + + assign ack_pwrup_o = ack_pwrup_q; + assign req_pwrdn_o = req_pwrdn_q; + assign low_power_o = low_power_q; + + assign pwr_rst_o.rst_lc_req = rst_lc_req_q; + assign pwr_rst_o.rst_sys_req = rst_sys_req_q; + assign pwr_rst_o.reset_cause = reset_cause_q; + assign pwr_rst_o.rstreqs = reset_reqs_i[HwResetWidth-1:0]; + + // main and io clocks are only turned on/off as part of normal + // power sequence + assign ips_clk_en_o.main_ip_clk_en = ip_clk_en_q; + assign ips_clk_en_o.io_ip_clk_en = ip_clk_en_q; + + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_reg_otp_init ( + .clk_i, + .rst_ni, + .d_i(otp_init), + .q_o(otp_init_o) + ); + + prim_flop #( + .Width(1), + .ResetValue(1'b0) + ) u_reg_lc_init ( + .clk_i, + .rst_ni, + .d_i(lc_init), + .q_o(lc_init_o) + ); + + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv new file mode 100644 index 00000000000..ba471af83a5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_pkg.sv @@ -0,0 +1,259 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Package +// + +package pwrmgr_pkg; + + // global constant + parameter int ALWAYS_ON_DOMAIN = 0; + + // variables referenced by other modules / packages + parameter int PowerDomains = 2; // this needs to be a topgen populated number, or from topcfg? + + // variables referenced only by pwrmgr + localparam int TotalWakeWidth = pwrmgr_reg_pkg::NumWkups + 2; // Abort and fall through are added + + parameter int NumSwRstReq = 1; + + // position of escalation request + parameter int HwResetWidth = pwrmgr_reg_pkg::NumRstReqs + + pwrmgr_reg_pkg::NumIntRstReqs + + pwrmgr_reg_pkg::NumDebugRstReqs; + parameter int TotalResetWidth = HwResetWidth + NumSwRstReq; + parameter int ResetSwReqIdx = TotalResetWidth - 1; + + // pwrmgr to ast + typedef struct packed { + logic main_pd_n; + logic pwr_clamp_env; + logic pwr_clamp; + logic slow_clk_en; + logic core_clk_en; + logic io_clk_en; + } pwr_ast_req_t; + + typedef struct packed { + logic slow_clk_val; + logic core_clk_val; + logic io_clk_val; + logic main_pok; + } pwr_ast_rsp_t; + + // default value of pwr_ast_rsp (for dangling ports) + parameter pwr_ast_rsp_t PWR_AST_RSP_DEFAULT = '{ + slow_clk_val: 1'b1, + core_clk_val: 1'b1, + io_clk_val: 1'b1, + main_pok: 1'b1 + }; + + parameter pwr_ast_rsp_t PWR_AST_RSP_SYNC_DEFAULT = '{ + slow_clk_val: 1'b0, + core_clk_val: 1'b0, + io_clk_val: 1'b0, + main_pok: 1'b0 + }; + + // reasons for pwrmgr reset + typedef enum logic [1:0] { + ResetNone = 0, // there is no reset + LowPwrEntry = 1, // reset is caused by low power entry + HwReq = 2, // reset is caused by peripheral reset requests + ResetUndefined = 3 // this should never happen outside of POR + } reset_cause_e; + + // pwrmgr to rstmgr + typedef struct packed { + logic [PowerDomains-1:0] rst_lc_req; + logic [PowerDomains-1:0] rst_sys_req; + logic [HwResetWidth-1:0] rstreqs; + reset_cause_e reset_cause; + } pwr_rst_req_t; + + // rstmgr to pwrmgr + typedef struct packed { + logic [PowerDomains-1:0] rst_lc_src_n; + logic [PowerDomains-1:0] rst_sys_src_n; + } pwr_rst_rsp_t; + + // default value (for dangling ports) + parameter pwr_rst_rsp_t PWR_RST_RSP_DEFAULT = '{ + rst_lc_src_n: {PowerDomains{1'b1}}, + rst_sys_src_n: {PowerDomains{1'b1}} + }; + + // pwrmgr to clkmgr + typedef struct packed { + logic main_ip_clk_en; + logic io_ip_clk_en; + } pwr_clk_req_t; + + // clkmgr to pwrmgr + typedef struct packed { + logic main_status; + logic io_status; + } pwr_clk_rsp_t; + + // pwrmgr to otp + typedef struct packed { + logic otp_init; + } pwr_otp_req_t; + + // otp to pwrmgr + typedef struct packed { + logic otp_done; + logic otp_idle; + } pwr_otp_rsp_t; + + // default value (for dangling ports) + parameter pwr_otp_rsp_t PWR_OTP_RSP_DEFAULT = '{ + otp_done: 1'b1, + otp_idle: 1'b1 + }; + + typedef struct packed { + logic flash_idle; + } pwr_flash_t; + + parameter pwr_flash_t PWR_FLASH_DEFAULT = '{ + flash_idle: 1'b1 + }; + + // cpu reset requests and status + typedef struct packed { + logic ndmreset_req; + } pwrmgr_cpu_t; + + typedef struct packed { + lc_ctrl_pkg::lc_tx_t cpu_fetch_en; + rom_ctrl_pkg::pwrmgr_data_t [pwrmgr_reg_pkg::NumRomInputs-1:0] rom_ctrl_status; + logic lc_done; + logic otp_done; + logic strap_sampled; + logic light_reset_req; + pwr_clk_rsp_t clk_status; + } pwr_boot_status_t; + + // exported resets + + // default value for pwrmgr_ast_rsp_t (for dangling ports) + parameter pwrmgr_cpu_t PWRMGR_CPU_DEFAULT = '{ + ndmreset_req: '0 + }; + + // default value (for dangling ports) + parameter int WAKEUPS_DEFAULT = '0; + parameter int RSTREQS_DEFAULT = '0; + + // peripherals to pwrmgr + typedef struct packed { + logic [pwrmgr_reg_pkg::NumWkups-1:0] wakeups; + // reset requests include external requests + escalation reset + logic [TotalResetWidth-1:0] rstreqs; + } pwr_peri_t; + + // power-up causes + typedef enum logic [1:0] { + Por = 2'h0, + Wake = 2'h1, + Reset = 2'h2 + } pwrup_cause_e; + + // low power hints + typedef enum logic { + None = 1'b0, + LowPower = 1'b1 + } low_power_hint_e; + + // fast fsm state enum + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 19 -n 12 \ + // -s 3096160381 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: ||||||||||||||||| (30.99%) + // 6: |||||||||||||||||||| (35.09%) + // 7: ||||||||| (15.79%) + // 8: |||||| (10.53%) + // 9: ||| (5.85%) + // 10: | (1.75%) + // 11: -- + // 12: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 10 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 10 + // + localparam int FastPwrStateWidth = 12; + typedef enum logic [FastPwrStateWidth-1:0] { + FastPwrStateLowPower = 12'b000000110111, + FastPwrStateEnableClocks = 12'b101011001110, + FastPwrStateReleaseLcRst = 12'b100111000000, + FastPwrStateOtpInit = 12'b111110100010, + FastPwrStateLcInit = 12'b101001010011, + FastPwrStateStrap = 12'b110000111010, + FastPwrStateAckPwrUp = 12'b000010101000, + FastPwrStateRomCheckDone = 12'b010111110011, + FastPwrStateRomCheckGood = 12'b010000000100, + FastPwrStateActive = 12'b001101100100, + FastPwrStateDisClks = 12'b001110010101, + FastPwrStateFallThrough = 12'b011011010000, + FastPwrStateNvmIdleChk = 12'b100101111001, + FastPwrStateLowPowerPrep = 12'b010110001111, + FastPwrStateNvmShutDown = 12'b001100001010, + FastPwrStateResetPrep = 12'b011001101111, + FastPwrStateResetWait = 12'b111111111100, + FastPwrStateReqPwrDn = 12'b111010001001, + FastPwrStateInvalid = 12'b110101010110 + } fast_pwr_state_e; + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 5 -m 12 -n 10 \ + // -s 1726685338 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: -- + // 4: -- + // 5: |||||||||||||||||||| (54.55%) + // 6: |||||||||||||||| (45.45%) + // 7: -- + // 8: -- + // 9: -- + // 10: -- + // + // Minimum Hamming distance: 5 + // Maximum Hamming distance: 6 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 8 + // + localparam int SlowPwrStateWidth = 10; + typedef enum logic [SlowPwrStateWidth-1:0] { + SlowPwrStateReset = 10'b0000100010, + SlowPwrStateLowPower = 10'b1011000111, + SlowPwrStateMainPowerOn = 10'b0110101111, + SlowPwrStatePwrClampOff = 10'b0110010001, + SlowPwrStateClocksOn = 10'b1010111100, + SlowPwrStateReqPwrUp = 10'b0011011010, + SlowPwrStateIdle = 10'b1111100000, + SlowPwrStateAckPwrDn = 10'b0001110101, + SlowPwrStateClocksOff = 10'b1101111011, + SlowPwrStatePwrClampOn = 10'b0101001100, + SlowPwrStateMainPowerOff = 10'b1000001001, + SlowPwrStateInvalid = 10'b1100010110 + } slow_pwr_state_e; + +endpackage // pwrmgr_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_reg_pkg.sv new file mode 100644 index 00000000000..b8c22b9fe37 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_reg_pkg.sv @@ -0,0 +1,279 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package pwrmgr_reg_pkg; + + // Param list + parameter int NumWkups = 4; + parameter int PINMUX_AON_PIN_WKUP_REQ_IDX = 0; + parameter int AON_TIMER_AON_WKUP_REQ_IDX = 1; + parameter int SOC_PROXY_WKUP_INTERNAL_REQ_IDX = 2; + parameter int SOC_PROXY_WKUP_EXTERNAL_REQ_IDX = 3; + parameter int NumRstReqs = 2; + parameter int NumIntRstReqs = 2; + parameter int NumDebugRstReqs = 0; + parameter int NumRomInputs = 3; + parameter int ResetMainPwrIdx = 2; + parameter int ResetEscIdx = 3; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int BlockAw = 7; + + // Number of registers for every interface + parameter int NumRegs = 17; + + // Alert indices + typedef enum int { + AlertFatalFaultIdx = 0 + } pwrmgr_alert_idx_t; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_intr_state_reg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_intr_enable_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_intr_test_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + } main_pd_n; + struct packed { + logic q; + } io_clk_en; + struct packed { + logic q; + } core_clk_en; + struct packed { + logic q; + } low_power_hint; + } pwrmgr_reg2hw_control_reg_t; + + typedef struct packed { + logic q; + logic qe; + } pwrmgr_reg2hw_cfg_cdc_sync_reg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_wakeup_en_mreg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_reset_en_mreg_t; + + typedef struct packed { + logic q; + } pwrmgr_reg2hw_wake_info_capture_dis_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } abort; + struct packed { + logic q; + logic qe; + } fall_through; + struct packed { + logic [3:0] q; + logic qe; + } reasons; + } pwrmgr_reg2hw_wake_info_reg_t; + + typedef struct packed { + struct packed { + logic q; + } main_pd_glitch; + struct packed { + logic q; + } esc_timeout; + struct packed { + logic q; + } reg_intg_err; + } pwrmgr_reg2hw_fault_status_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_intr_state_reg_t; + + typedef struct packed { + logic d; + } pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } low_power_hint; + } pwrmgr_hw2reg_control_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_cfg_cdc_sync_reg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_wake_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_reset_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } pwrmgr_hw2reg_escalate_reset_status_reg_t; + + typedef struct packed { + struct packed { + logic d; + } abort; + struct packed { + logic d; + } fall_through; + struct packed { + logic [3:0] d; + } reasons; + } pwrmgr_hw2reg_wake_info_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } main_pd_glitch; + struct packed { + logic d; + logic de; + } esc_timeout; + struct packed { + logic d; + logic de; + } reg_intg_err; + } pwrmgr_hw2reg_fault_status_reg_t; + + // Register -> HW type + typedef struct packed { + pwrmgr_reg2hw_intr_state_reg_t intr_state; // [30:30] + pwrmgr_reg2hw_intr_enable_reg_t intr_enable; // [29:29] + pwrmgr_reg2hw_intr_test_reg_t intr_test; // [28:27] + pwrmgr_reg2hw_alert_test_reg_t alert_test; // [26:25] + pwrmgr_reg2hw_control_reg_t control; // [24:21] + pwrmgr_reg2hw_cfg_cdc_sync_reg_t cfg_cdc_sync; // [20:19] + pwrmgr_reg2hw_wakeup_en_mreg_t [3:0] wakeup_en; // [18:15] + pwrmgr_reg2hw_reset_en_mreg_t [1:0] reset_en; // [14:13] + pwrmgr_reg2hw_wake_info_capture_dis_reg_t wake_info_capture_dis; // [12:12] + pwrmgr_reg2hw_wake_info_reg_t wake_info; // [11:3] + pwrmgr_reg2hw_fault_status_reg_t fault_status; // [2:0] + } pwrmgr_reg2hw_t; + + // HW -> register type + typedef struct packed { + pwrmgr_hw2reg_intr_state_reg_t intr_state; // [32:31] + pwrmgr_hw2reg_ctrl_cfg_regwen_reg_t ctrl_cfg_regwen; // [30:30] + pwrmgr_hw2reg_control_reg_t control; // [29:28] + pwrmgr_hw2reg_cfg_cdc_sync_reg_t cfg_cdc_sync; // [27:26] + pwrmgr_hw2reg_wake_status_mreg_t [3:0] wake_status; // [25:18] + pwrmgr_hw2reg_reset_status_mreg_t [1:0] reset_status; // [17:14] + pwrmgr_hw2reg_escalate_reset_status_reg_t escalate_reset_status; // [13:12] + pwrmgr_hw2reg_wake_info_reg_t wake_info; // [11:6] + pwrmgr_hw2reg_fault_status_reg_t fault_status; // [5:0] + } pwrmgr_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] PWRMGR_INTR_STATE_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] PWRMGR_INTR_ENABLE_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] PWRMGR_INTR_TEST_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] PWRMGR_ALERT_TEST_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] PWRMGR_CTRL_CFG_REGWEN_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] PWRMGR_CONTROL_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] PWRMGR_CFG_CDC_SYNC_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_REGWEN_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] PWRMGR_WAKEUP_EN_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] PWRMGR_WAKE_STATUS_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_REGWEN_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] PWRMGR_RESET_EN_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] PWRMGR_RESET_STATUS_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] PWRMGR_ESCALATE_RESET_STATUS_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] PWRMGR_WAKE_INFO_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] PWRMGR_FAULT_STATUS_OFFSET = 7'h 40; + + // Reset values for hwext registers and their fields + parameter logic [0:0] PWRMGR_INTR_TEST_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_INTR_TEST_WAKEUP_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_ALERT_TEST_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_RESVAL = 1'h 1; + parameter logic [0:0] PWRMGR_CTRL_CFG_REGWEN_EN_RESVAL = 1'h 1; + parameter logic [5:0] PWRMGR_WAKE_INFO_RESVAL = 6'h 0; + parameter logic [3:0] PWRMGR_WAKE_INFO_REASONS_RESVAL = 4'h 0; + parameter logic [0:0] PWRMGR_WAKE_INFO_FALL_THROUGH_RESVAL = 1'h 0; + parameter logic [0:0] PWRMGR_WAKE_INFO_ABORT_RESVAL = 1'h 0; + + // Register index + typedef enum int { + PWRMGR_INTR_STATE, + PWRMGR_INTR_ENABLE, + PWRMGR_INTR_TEST, + PWRMGR_ALERT_TEST, + PWRMGR_CTRL_CFG_REGWEN, + PWRMGR_CONTROL, + PWRMGR_CFG_CDC_SYNC, + PWRMGR_WAKEUP_EN_REGWEN, + PWRMGR_WAKEUP_EN, + PWRMGR_WAKE_STATUS, + PWRMGR_RESET_EN_REGWEN, + PWRMGR_RESET_EN, + PWRMGR_RESET_STATUS, + PWRMGR_ESCALATE_RESET_STATUS, + PWRMGR_WAKE_INFO_CAPTURE_DIS, + PWRMGR_WAKE_INFO, + PWRMGR_FAULT_STATUS + } pwrmgr_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] PWRMGR_PERMIT [17] = '{ + 4'b 0001, // index[ 0] PWRMGR_INTR_STATE + 4'b 0001, // index[ 1] PWRMGR_INTR_ENABLE + 4'b 0001, // index[ 2] PWRMGR_INTR_TEST + 4'b 0001, // index[ 3] PWRMGR_ALERT_TEST + 4'b 0001, // index[ 4] PWRMGR_CTRL_CFG_REGWEN + 4'b 0001, // index[ 5] PWRMGR_CONTROL + 4'b 0001, // index[ 6] PWRMGR_CFG_CDC_SYNC + 4'b 0001, // index[ 7] PWRMGR_WAKEUP_EN_REGWEN + 4'b 0001, // index[ 8] PWRMGR_WAKEUP_EN + 4'b 0001, // index[ 9] PWRMGR_WAKE_STATUS + 4'b 0001, // index[10] PWRMGR_RESET_EN_REGWEN + 4'b 0001, // index[11] PWRMGR_RESET_EN + 4'b 0001, // index[12] PWRMGR_RESET_STATUS + 4'b 0001, // index[13] PWRMGR_ESCALATE_RESET_STATUS + 4'b 0001, // index[14] PWRMGR_WAKE_INFO_CAPTURE_DIS + 4'b 0001, // index[15] PWRMGR_WAKE_INFO + 4'b 0001 // index[16] PWRMGR_FAULT_STATUS + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_reg_top.sv new file mode 100644 index 00000000000..13a18e9b9bb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_reg_top.sv @@ -0,0 +1,1299 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module pwrmgr_reg_top ( + input clk_i, + input rst_ni, + input clk_lc_i, + input rst_lc_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write + input pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import pwrmgr_reg_pkg::* ; + + localparam int AW = 7; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [16:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(17) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_lc_i or negedge rst_lc_ni) begin + if (!rst_lc_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic intr_state_we; + logic intr_state_qs; + logic intr_state_wd; + logic intr_enable_we; + logic intr_enable_qs; + logic intr_enable_wd; + logic intr_test_we; + logic intr_test_wd; + logic alert_test_we; + logic alert_test_wd; + logic ctrl_cfg_regwen_re; + logic ctrl_cfg_regwen_qs; + logic control_we; + logic control_low_power_hint_qs; + logic control_low_power_hint_wd; + logic control_core_clk_en_qs; + logic control_core_clk_en_wd; + logic control_io_clk_en_qs; + logic control_io_clk_en_wd; + logic control_main_pd_n_qs; + logic control_main_pd_n_wd; + logic cfg_cdc_sync_we; + logic cfg_cdc_sync_qs; + logic cfg_cdc_sync_wd; + logic wakeup_en_regwen_we; + logic wakeup_en_regwen_qs; + logic wakeup_en_regwen_wd; + logic wakeup_en_we; + logic wakeup_en_en_0_qs; + logic wakeup_en_en_0_wd; + logic wakeup_en_en_1_qs; + logic wakeup_en_en_1_wd; + logic wakeup_en_en_2_qs; + logic wakeup_en_en_2_wd; + logic wakeup_en_en_3_qs; + logic wakeup_en_en_3_wd; + logic wake_status_val_0_qs; + logic wake_status_val_1_qs; + logic wake_status_val_2_qs; + logic wake_status_val_3_qs; + logic reset_en_regwen_we; + logic reset_en_regwen_qs; + logic reset_en_regwen_wd; + logic reset_en_we; + logic reset_en_en_0_qs; + logic reset_en_en_0_wd; + logic reset_en_en_1_qs; + logic reset_en_en_1_wd; + logic reset_status_val_0_qs; + logic reset_status_val_1_qs; + logic escalate_reset_status_qs; + logic wake_info_capture_dis_we; + logic wake_info_capture_dis_qs; + logic wake_info_capture_dis_wd; + logic wake_info_re; + logic wake_info_we; + logic [3:0] wake_info_reasons_qs; + logic [3:0] wake_info_reasons_wd; + logic wake_info_fall_through_qs; + logic wake_info_fall_through_wd; + logic wake_info_abort_qs; + logic wake_info_abort_wd; + logic fault_status_reg_intg_err_qs; + logic fault_status_esc_timeout_qs; + logic fault_status_main_pd_glitch_qs; + // Define register CDC handling. + // CDC handling is done on a per-reg instead of per-field boundary. + + // Register instances + // R[intr_state]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_state_we), + .wd (intr_state_wd), + + // from internal hardware + .de (hw2reg.intr_state.de), + .d (hw2reg.intr_state.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.q), + .ds (), + + // to register interface (read) + .qs (intr_state_qs) + ); + + + // R[intr_enable]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [0:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_intr_test ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [0:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.qe = alert_test_qe; + + + // R[ctrl_cfg_regwen]: V(True) + prim_subreg_ext #( + .DW (1) + ) u_ctrl_cfg_regwen ( + .re (ctrl_cfg_regwen_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.ctrl_cfg_regwen.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (ctrl_cfg_regwen_qs) + ); + + + // R[control]: V(False) + // Create REGWEN-gated WE signal + logic control_gated_we; + assign control_gated_we = control_we & ctrl_cfg_regwen_qs; + // F[low_power_hint]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_control_low_power_hint ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_low_power_hint_wd), + + // from internal hardware + .de (hw2reg.control.low_power_hint.de), + .d (hw2reg.control.low_power_hint.d), + + // to internal hardware + .qe (), + .q (reg2hw.control.low_power_hint.q), + .ds (), + + // to register interface (read) + .qs (control_low_power_hint_qs) + ); + + // F[core_clk_en]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_control_core_clk_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_core_clk_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.control.core_clk_en.q), + .ds (), + + // to register interface (read) + .qs (control_core_clk_en_qs) + ); + + // F[io_clk_en]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_control_io_clk_en ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_io_clk_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.control.io_clk_en.q), + .ds (), + + // to register interface (read) + .qs (control_io_clk_en_qs) + ); + + // F[main_pd_n]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_control_main_pd_n ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (control_gated_we), + .wd (control_main_pd_n_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.control.main_pd_n.q), + .ds (), + + // to register interface (read) + .qs (control_main_pd_n_qs) + ); + + + // R[cfg_cdc_sync]: V(False) + logic cfg_cdc_sync_qe; + logic [0:0] cfg_cdc_sync_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_cfg_cdc_sync0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&cfg_cdc_sync_flds_we), + .q_o(cfg_cdc_sync_qe) + ); + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cfg_cdc_sync ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cfg_cdc_sync_we), + .wd (cfg_cdc_sync_wd), + + // from internal hardware + .de (hw2reg.cfg_cdc_sync.de), + .d (hw2reg.cfg_cdc_sync.d), + + // to internal hardware + .qe (cfg_cdc_sync_flds_we[0]), + .q (reg2hw.cfg_cdc_sync.q), + .ds (), + + // to register interface (read) + .qs (cfg_cdc_sync_qs) + ); + assign reg2hw.cfg_cdc_sync.qe = cfg_cdc_sync_qe; + + + // R[wakeup_en_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_wakeup_en_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_regwen_we), + .wd (wakeup_en_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wakeup_en_regwen_qs) + ); + + + // Subregister 0 of Multireg wakeup_en + // R[wakeup_en]: V(False) + // Create REGWEN-gated WE signal + logic wakeup_en_gated_we; + assign wakeup_en_gated_we = wakeup_en_we & wakeup_en_regwen_qs; + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[0].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_0_qs) + ); + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[1].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_1_qs) + ); + + // F[en_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[2].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_2_qs) + ); + + // F[en_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wakeup_en_en_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wakeup_en_gated_we), + .wd (wakeup_en_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wakeup_en[3].q), + .ds (), + + // to register interface (read) + .qs (wakeup_en_en_3_qs) + ); + + + // Subregister 0 of Multireg wake_status + // R[wake_status]: V(False) + // F[val_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[0].de), + .d (hw2reg.wake_status[0].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_0_qs) + ); + + // F[val_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[1].de), + .d (hw2reg.wake_status[1].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_1_qs) + ); + + // F[val_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[2].de), + .d (hw2reg.wake_status[2].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_2_qs) + ); + + // F[val_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_status_val_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.wake_status[3].de), + .d (hw2reg.wake_status[3].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (wake_status_val_3_qs) + ); + + + // R[reset_en_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_reset_en_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (reset_en_regwen_we), + .wd (reset_en_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_en_regwen_qs) + ); + + + // Subregister 0 of Multireg reset_en + // R[reset_en]: V(False) + // Create REGWEN-gated WE signal + logic reset_en_gated_we; + assign reset_en_gated_we = reset_en_we & reset_en_regwen_qs; + // F[en_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_en_en_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (reset_en_gated_we), + .wd (reset_en_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.reset_en[0].q), + .ds (), + + // to register interface (read) + .qs (reset_en_en_0_qs) + ); + + // F[en_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_en_en_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (reset_en_gated_we), + .wd (reset_en_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.reset_en[1].q), + .ds (), + + // to register interface (read) + .qs (reset_en_en_1_qs) + ); + + + // Subregister 0 of Multireg reset_status + // R[reset_status]: V(False) + // F[val_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_status_val_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.reset_status[0].de), + .d (hw2reg.reset_status[0].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_status_val_0_qs) + ); + + // F[val_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_status_val_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.reset_status[1].de), + .d (hw2reg.reset_status[1].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_status_val_1_qs) + ); + + + // R[escalate_reset_status]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_escalate_reset_status ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.escalate_reset_status.de), + .d (hw2reg.escalate_reset_status.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (escalate_reset_status_qs) + ); + + + // R[wake_info_capture_dis]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_wake_info_capture_dis ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (wake_info_capture_dis_we), + .wd (wake_info_capture_dis_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.wake_info_capture_dis.q), + .ds (), + + // to register interface (read) + .qs (wake_info_capture_dis_qs) + ); + + + // R[wake_info]: V(True) + logic wake_info_qe; + logic [2:0] wake_info_flds_we; + assign wake_info_qe = &wake_info_flds_we; + // F[reasons]: 3:0 + prim_subreg_ext #( + .DW (4) + ) u_wake_info_reasons ( + .re (wake_info_re), + .we (wake_info_we), + .wd (wake_info_reasons_wd), + .d (hw2reg.wake_info.reasons.d), + .qre (), + .qe (wake_info_flds_we[0]), + .q (reg2hw.wake_info.reasons.q), + .ds (), + .qs (wake_info_reasons_qs) + ); + assign reg2hw.wake_info.reasons.qe = wake_info_qe; + + // F[fall_through]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_wake_info_fall_through ( + .re (wake_info_re), + .we (wake_info_we), + .wd (wake_info_fall_through_wd), + .d (hw2reg.wake_info.fall_through.d), + .qre (), + .qe (wake_info_flds_we[1]), + .q (reg2hw.wake_info.fall_through.q), + .ds (), + .qs (wake_info_fall_through_qs) + ); + assign reg2hw.wake_info.fall_through.qe = wake_info_qe; + + // F[abort]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_wake_info_abort ( + .re (wake_info_re), + .we (wake_info_we), + .wd (wake_info_abort_wd), + .d (hw2reg.wake_info.abort.d), + .qre (), + .qe (wake_info_flds_we[2]), + .q (reg2hw.wake_info.abort.q), + .ds (), + .qs (wake_info_abort_qs) + ); + assign reg2hw.wake_info.abort.qe = wake_info_qe; + + + // R[fault_status]: V(False) + // F[reg_intg_err]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fault_status_reg_intg_err ( + // sync clock and reset required for this register + .clk_i (clk_lc_i), + .rst_ni (rst_lc_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fault_status.reg_intg_err.de), + .d (hw2reg.fault_status.reg_intg_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.fault_status.reg_intg_err.q), + .ds (), + + // to register interface (read) + .qs (fault_status_reg_intg_err_qs) + ); + + // F[esc_timeout]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fault_status_esc_timeout ( + // sync clock and reset required for this register + .clk_i (clk_lc_i), + .rst_ni (rst_lc_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fault_status.esc_timeout.de), + .d (hw2reg.fault_status.esc_timeout.d), + + // to internal hardware + .qe (), + .q (reg2hw.fault_status.esc_timeout.q), + .ds (), + + // to register interface (read) + .qs (fault_status_esc_timeout_qs) + ); + + // F[main_pd_glitch]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_fault_status_main_pd_glitch ( + // sync clock and reset required for this register + .clk_i (clk_lc_i), + .rst_ni (rst_lc_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.fault_status.main_pd_glitch.de), + .d (hw2reg.fault_status.main_pd_glitch.d), + + // to internal hardware + .qe (), + .q (reg2hw.fault_status.main_pd_glitch.q), + .ds (), + + // to register interface (read) + .qs (fault_status_main_pd_glitch_qs) + ); + + + + logic [16:0] addr_hit; + always_comb begin + addr_hit[ 0] = (reg_addr == PWRMGR_INTR_STATE_OFFSET); + addr_hit[ 1] = (reg_addr == PWRMGR_INTR_ENABLE_OFFSET); + addr_hit[ 2] = (reg_addr == PWRMGR_INTR_TEST_OFFSET); + addr_hit[ 3] = (reg_addr == PWRMGR_ALERT_TEST_OFFSET); + addr_hit[ 4] = (reg_addr == PWRMGR_CTRL_CFG_REGWEN_OFFSET); + addr_hit[ 5] = (reg_addr == PWRMGR_CONTROL_OFFSET); + addr_hit[ 6] = (reg_addr == PWRMGR_CFG_CDC_SYNC_OFFSET); + addr_hit[ 7] = (reg_addr == PWRMGR_WAKEUP_EN_REGWEN_OFFSET); + addr_hit[ 8] = (reg_addr == PWRMGR_WAKEUP_EN_OFFSET); + addr_hit[ 9] = (reg_addr == PWRMGR_WAKE_STATUS_OFFSET); + addr_hit[10] = (reg_addr == PWRMGR_RESET_EN_REGWEN_OFFSET); + addr_hit[11] = (reg_addr == PWRMGR_RESET_EN_OFFSET); + addr_hit[12] = (reg_addr == PWRMGR_RESET_STATUS_OFFSET); + addr_hit[13] = (reg_addr == PWRMGR_ESCALATE_RESET_STATUS_OFFSET); + addr_hit[14] = (reg_addr == PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET); + addr_hit[15] = (reg_addr == PWRMGR_WAKE_INFO_OFFSET); + addr_hit[16] = (reg_addr == PWRMGR_FAULT_STATUS_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(PWRMGR_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(PWRMGR_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(PWRMGR_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(PWRMGR_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(PWRMGR_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(PWRMGR_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(PWRMGR_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(PWRMGR_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(PWRMGR_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(PWRMGR_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(PWRMGR_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(PWRMGR_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(PWRMGR_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(PWRMGR_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(PWRMGR_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(PWRMGR_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(PWRMGR_PERMIT[16] & ~reg_be))))); + end + + // Generate write-enables + assign intr_state_we = addr_hit[0] & reg_we & !reg_error; + + assign intr_state_wd = reg_wdata[0]; + assign intr_enable_we = addr_hit[1] & reg_we & !reg_error; + + assign intr_enable_wd = reg_wdata[0]; + assign intr_test_we = addr_hit[2] & reg_we & !reg_error; + + assign intr_test_wd = reg_wdata[0]; + assign alert_test_we = addr_hit[3] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + assign ctrl_cfg_regwen_re = addr_hit[4] & reg_re & !reg_error; + assign control_we = addr_hit[5] & reg_we & !reg_error; + + assign control_low_power_hint_wd = reg_wdata[0]; + + assign control_core_clk_en_wd = reg_wdata[4]; + + assign control_io_clk_en_wd = reg_wdata[5]; + + assign control_main_pd_n_wd = reg_wdata[6]; + assign cfg_cdc_sync_we = addr_hit[6] & reg_we & !reg_error; + + assign cfg_cdc_sync_wd = reg_wdata[0]; + assign wakeup_en_regwen_we = addr_hit[7] & reg_we & !reg_error; + + assign wakeup_en_regwen_wd = reg_wdata[0]; + assign wakeup_en_we = addr_hit[8] & reg_we & !reg_error; + + assign wakeup_en_en_0_wd = reg_wdata[0]; + + assign wakeup_en_en_1_wd = reg_wdata[1]; + + assign wakeup_en_en_2_wd = reg_wdata[2]; + + assign wakeup_en_en_3_wd = reg_wdata[3]; + assign reset_en_regwen_we = addr_hit[10] & reg_we & !reg_error; + + assign reset_en_regwen_wd = reg_wdata[0]; + assign reset_en_we = addr_hit[11] & reg_we & !reg_error; + + assign reset_en_en_0_wd = reg_wdata[0]; + + assign reset_en_en_1_wd = reg_wdata[1]; + assign wake_info_capture_dis_we = addr_hit[14] & reg_we & !reg_error; + + assign wake_info_capture_dis_wd = reg_wdata[0]; + assign wake_info_re = addr_hit[15] & reg_re & !reg_error; + assign wake_info_we = addr_hit[15] & reg_we & !reg_error; + + assign wake_info_reasons_wd = reg_wdata[3:0]; + + assign wake_info_fall_through_wd = reg_wdata[4]; + + assign wake_info_abort_wd = reg_wdata[5]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = intr_state_we; + reg_we_check[1] = intr_enable_we; + reg_we_check[2] = intr_test_we; + reg_we_check[3] = alert_test_we; + reg_we_check[4] = 1'b0; + reg_we_check[5] = control_gated_we; + reg_we_check[6] = cfg_cdc_sync_we; + reg_we_check[7] = wakeup_en_regwen_we; + reg_we_check[8] = wakeup_en_gated_we; + reg_we_check[9] = 1'b0; + reg_we_check[10] = reset_en_regwen_we; + reg_we_check[11] = reset_en_gated_we; + reg_we_check[12] = 1'b0; + reg_we_check[13] = 1'b0; + reg_we_check[14] = wake_info_capture_dis_we; + reg_we_check[15] = wake_info_we; + reg_we_check[16] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = intr_state_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[3]: begin + reg_rdata_next[0] = '0; + end + + addr_hit[4]: begin + reg_rdata_next[0] = ctrl_cfg_regwen_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = control_low_power_hint_qs; + reg_rdata_next[4] = control_core_clk_en_qs; + reg_rdata_next[5] = control_io_clk_en_qs; + reg_rdata_next[6] = control_main_pd_n_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = cfg_cdc_sync_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = wakeup_en_regwen_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = wakeup_en_en_0_qs; + reg_rdata_next[1] = wakeup_en_en_1_qs; + reg_rdata_next[2] = wakeup_en_en_2_qs; + reg_rdata_next[3] = wakeup_en_en_3_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = wake_status_val_0_qs; + reg_rdata_next[1] = wake_status_val_1_qs; + reg_rdata_next[2] = wake_status_val_2_qs; + reg_rdata_next[3] = wake_status_val_3_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = reset_en_regwen_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = reset_en_en_0_qs; + reg_rdata_next[1] = reset_en_en_1_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = reset_status_val_0_qs; + reg_rdata_next[1] = reset_status_val_1_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = escalate_reset_status_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = wake_info_capture_dis_qs; + end + + addr_hit[15]: begin + reg_rdata_next[3:0] = wake_info_reasons_qs; + reg_rdata_next[4] = wake_info_fall_through_qs; + reg_rdata_next[5] = wake_info_abort_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = fault_status_reg_intg_err_qs; + reg_rdata_next[1] = fault_status_esc_timeout_qs; + reg_rdata_next[2] = fault_status_main_pd_glitch_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_slow_fsm.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_slow_fsm.sv new file mode 100644 index 00000000000..104d5f8517d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_slow_fsm.sv @@ -0,0 +1,337 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Slow FSM +// + +`include "prim_assert.sv" + +module pwrmgr_slow_fsm import pwrmgr_pkg::*; ( + input clk_i, + input rst_ni, + input rst_main_ni, + + // sync'ed requests from peripherals + input wakeup_i, + input reset_req_i, + + // interface with fast fsm + output logic req_pwrup_o, + output logic pwrup_cause_toggle_o, + output pwrup_cause_e pwrup_cause_o, + input ack_pwrup_i, + input req_pwrdn_i, + output logic ack_pwrdn_o, + output logic rst_req_o, + output logic fsm_invalid_o, + input clr_req_i, + + // low power entry configuration + input main_pd_ni, + input main_clk_en_i, + input io_clk_en_i, + + // AST interface + input pwr_ast_rsp_t ast_i, + output pwr_ast_req_t ast_o +); + + slow_pwr_state_e state_q, state_d; + + // All signals crossing over to other domain must be flopped + pwrup_cause_e cause_q, cause_d; + logic cause_toggle_q, cause_toggle_d; + logic req_pwrup_q, req_pwrup_d; + logic ack_pwrdn_q, ack_pwrdn_d; + + logic clk_active; + + // All power signals and signals going to analog logic are flopped to avoid transitional glitches + logic pd_nq, pd_nd; + logic pwr_clamp_q, pwr_clamp_d; + logic pwr_clamp_env_q, pwr_clamp_env_d; + logic main_clk_en_q, main_clk_en_d; + logic io_clk_en_q, io_clk_en_d; + logic fsm_invalid_q, fsm_invalid_d; + + logic all_clks_valid; + logic all_clks_invalid; + + // when to monitor pok for instability + // These are monitored only in active and low power states + logic mon_main_pok; + logic set_main_pok; + logic async_main_pok_st; + logic main_pok_st; + + // all clocks sources are valid + // if clocks (usb) not configured to be active, then just bypass check + assign all_clks_valid = ( + ast_i.core_clk_val & + ast_i.io_clk_val + ); + + // usb clock state during low power is not completely controlled by + // input. + // if main_pd_ni is 0, (ie power will be turned off), then the low power + // state of usb is also off. If main_pd_ni is 1 (power will be kept on), + // then the low power state of usb is directly controlled. + // Non-usb clocks are disabled when power is turned off. + + logic main_clk_en; + assign main_clk_en = main_pd_ni & main_clk_en_i; + + logic io_clk_en; + assign io_clk_en = main_pd_ni & io_clk_en_i; + + // if clocks were configured to turn off, make sure val is invalid + // if clocks were not configured to turn off, just bypass the check + assign all_clks_invalid = ( + (main_clk_en | ~ast_i.core_clk_val) & + (io_clk_en | ~ast_i.io_clk_val) + ); + + // ensure that clock controls are constantly re-evaluated and not just + // in one specific state + // When fsm is invalid, force the clocks to be on such that the fast fsm + // can forcibly reset the system. + // In the event the clocks cannot be turned on even when forced, the fsm + // invalid signal forces power to turn off. + assign main_clk_en_d = fsm_invalid_q | (clk_active | main_clk_en); + assign io_clk_en_d = fsm_invalid_q | (clk_active | io_clk_en); + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cause_q <= Por; + cause_toggle_q <= 1'b0; + pd_nq <= 1'b1; + pwr_clamp_q <= 1'b1; + pwr_clamp_env_q <= 1'b1; + main_clk_en_q <= 1'b0; + io_clk_en_q <= 1'b0; + req_pwrup_q <= 1'b0; + ack_pwrdn_q <= 1'b0; + fsm_invalid_q <= 1'b0; + end else begin + cause_q <= cause_d; + cause_toggle_q <= cause_toggle_d; + pd_nq <= pd_nd; + pwr_clamp_q <= pwr_clamp_d; + pwr_clamp_env_q <= pwr_clamp_env_d; + main_clk_en_q <= main_clk_en_d; + io_clk_en_q <= io_clk_en_d; + req_pwrup_q <= req_pwrup_d; + ack_pwrdn_q <= ack_pwrdn_d; + fsm_invalid_q <= fsm_invalid_d; + end + end + + // SEC_CM: FSM.SPARSE + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, slow_pwr_state_e, SlowPwrStateReset) + + always_comb begin + state_d = state_q; + cause_d = cause_q; + pd_nd = pd_nq; + cause_toggle_d = cause_toggle_q; + pwr_clamp_d = pwr_clamp_q; + pwr_clamp_env_d = pwr_clamp_env_q; + + req_pwrup_d = req_pwrup_q; + ack_pwrdn_d = ack_pwrdn_q; + fsm_invalid_d = fsm_invalid_q; + + set_main_pok = '0; + + clk_active = '0; + + unique case(state_q) + + SlowPwrStateReset: begin + state_d = SlowPwrStateMainPowerOn; + cause_d = Por; + end + + SlowPwrStateLowPower: begin + // reset request behaves identically to a wakeup, other than the power-up cause being + // different + if (wakeup_i || reset_req_i) begin + state_d = SlowPwrStateMainPowerOn; + cause_toggle_d = ~cause_toggle_q; + cause_d = reset_req_i ? Reset : Wake; + end + end + + SlowPwrStateMainPowerOn: begin + pd_nd = 1'b1; + + if (main_pok_st) begin + set_main_pok = 1'b1; + pwr_clamp_env_d = 1'b0; + state_d = SlowPwrStatePwrClampOff; + end + end + + SlowPwrStatePwrClampOff: begin + pwr_clamp_d = 1'b0; + state_d = SlowPwrStateClocksOn; + end + + SlowPwrStateClocksOn: begin + clk_active = 1'b1; + + if (all_clks_valid) begin + state_d = SlowPwrStateReqPwrUp; + end + end + + SlowPwrStateReqPwrUp: begin + clk_active = 1'b1; + req_pwrup_d = 1'b1; + + // req_pwrdn_i should be 0 here to indicate + // the request from the previous round has definitely completed + if (ack_pwrup_i && !req_pwrdn_i) begin + req_pwrup_d = 1'b0; + state_d = SlowPwrStateIdle; + end + end + + SlowPwrStateIdle: begin + // ack_pwrup_i should be 0 here to indicate + // the ack from the previous round has definitively completed + clk_active = 1'b1; + + if (req_pwrdn_i && !ack_pwrup_i) begin + state_d = SlowPwrStateAckPwrDn; + end + end + + SlowPwrStateAckPwrDn: begin + clk_active = 1'b1; + ack_pwrdn_d = 1'b1; + + if (!req_pwrdn_i) begin + ack_pwrdn_d = 1'b0; + state_d = SlowPwrStateClocksOff; + end + end + + SlowPwrStateClocksOff: begin + if (all_clks_invalid) begin + // if main power is turned off, assert early clamp ahead + pwr_clamp_env_d = ~main_pd_ni; + state_d = SlowPwrStatePwrClampOn; + end + end + + SlowPwrStatePwrClampOn: begin + // if main power is turned off, assert clamp ahead + pwr_clamp_d = pwr_clamp_env_q; + state_d = SlowPwrStateMainPowerOff; + end + + SlowPwrStateMainPowerOff: begin + pd_nd = main_pd_ni; + + // Proceed if power is already off, or if there was no intent to + // turn off the power. + if (!main_pok_st | main_pd_ni) begin + state_d = SlowPwrStateLowPower; + end + end + + // Very terminal state, kill everything + // Signal the fast FSM if it somehow is still running. + // Both FSMs are now permanently out of sync and the device + // must be rebooted. + // SEC_CM: FSM.TERMINAL + default: begin + fsm_invalid_d = 1'b1; + pd_nd = 1'b0; + pwr_clamp_d = 1'b1; + end + endcase // unique case (state_q) + end // always_comb + + // If the main_pok ever drops, capture that glitch + // and hold onto it for reset escalation + always_ff @(posedge clk_i or negedge rst_main_ni) begin + if (!rst_main_ni) begin + async_main_pok_st <= '0; + end else begin + async_main_pok_st <= ast_i.main_pok; + end + end + + // We need to synchronize the above because the reset + // may cause the signal to change at any time. + prim_flop_2sync # ( + .Width(1) + ) u_main_pok_sync ( + .clk_i, + .rst_ni, + .d_i(async_main_pok_st), + .q_o(main_pok_st) + ); + + // Determine when pok should be monitored + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mon_main_pok <= '0; + end else if (!pd_nd && mon_main_pok) begin + mon_main_pok <= 1'b0; + end else if (set_main_pok) begin + mon_main_pok <= 1'b1; + end + end + + // power stability reset request + // If the main power becomes unstable for whatever reason, + // request reset + // SEC_CM: MAIN_PD.RST.LOCAL_ESC + logic pwr_rst_req; + assign pwr_rst_req = mon_main_pok & ~main_pok_st; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_req_o <= '0; + end else if (clr_req_i) begin + rst_req_o <= '0; + end else begin + rst_req_o <= rst_req_o | pwr_rst_req; + end + end + + assign pwrup_cause_o = cause_q; + assign pwrup_cause_toggle_o = cause_toggle_q; + assign req_pwrup_o = req_pwrup_q; + assign ack_pwrdn_o = ack_pwrdn_q; + assign fsm_invalid_o = fsm_invalid_q; + + assign ast_o.core_clk_en = main_clk_en_q; + assign ast_o.io_clk_en = io_clk_en_q; + + assign ast_o.main_pd_n = pd_nq; + assign ast_o.pwr_clamp_env = pwr_clamp_env_q; + assign ast_o.pwr_clamp = pwr_clamp_q; + // This is hardwired to 1 all the time + assign ast_o.slow_clk_en = 1'b1; + + + //////////////////////////// + /// Unused + //////////////////////////// + + logic unused_slow_clk_val; + assign unused_slow_clk_val = ast_i.slow_clk_val; + + //////////////////////////// + /// Assertion + //////////////////////////// + // Under normal circumstances, this should NEVER fire + // May need to add a signal to disable this check for simulation + `ASSERT(IntRstReq_A, pwr_rst_req == '0) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_wake_info.sv b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_wake_info.sv new file mode 100644 index 00000000000..68f4e8f1c09 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/rtl/pwrmgr_wake_info.sv @@ -0,0 +1,74 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Power Manager Wake Information +// + +`include "prim_assert.sv" + +module pwrmgr_wake_info import pwrmgr_pkg::*; import pwrmgr_reg_pkg::*; +( + input clk_i, + input rst_ni, + input wr_i, + input [TotalWakeWidth-1:0] data_i, + input start_capture_i, + input record_dis_i, + input [NumWkups-1:0] wakeups_i, + input fall_through_i, + input abort_i, + output pwrmgr_hw2reg_wake_info_reg_t info_o +); + + logic record_en; + + // detect rising edge of start_capture_i + logic start_capture_q1, start_capture; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + start_capture_q1 <= 1'b1; + end else begin + start_capture_q1 <= start_capture_i; + end + end + + assign start_capture = start_capture_i & ~start_capture_q1; + + // generate the record enable signal + // HW enables the recording + // Software can suppress the recording or disable it + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + record_en <= 1'b0; + end else if (start_capture && !record_dis_i) begin + // if not disabled by software + // a recording enable pulse by HW starts recording + record_en <= 1'b1; + end else if (record_dis_i && record_en) begin + // if recording is already ongoing + // a disable command by software shuts things down + record_en <= 1'b0; + end + end + + logic [TotalWakeWidth-1:0] info; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + info <= '0; + end else if (wr_i) begin + info <= info & ~data_i; // W1C + end else if (record_en) begin // If set once, hold until clear + info[0 +: NumWkups] <= info[0 +: NumWkups] | wakeups_i; + info[NumWkups +: 2] <= info[NumWkups +: 2] | {abort_i, fall_through_i}; + end + end + + // assign outputs + assign info_o.abort.d = info[NumWkups + 1]; + assign info_o.fall_through.d = info[NumWkups]; + assign info_o.reasons = info[NumWkups-1:0]; + + + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/BUILD.bazel b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/BUILD.bazel new file mode 100644 index 00000000000..153a7c07877 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/BUILD.bazel @@ -0,0 +1,20 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +py_library( + name = "ipconfig", + srcs = ["ipconfig.py"], +) + +py_library( + name = "dt", + srcs = ["dt.py"], + deps = [ + ":ipconfig", + "//util/dtgen:helper", + "//util/topgen", + ], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/dt.py b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/dt.py new file mode 100644 index 00000000000..c613a461dfe --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/dt.py @@ -0,0 +1,233 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +"""This contains a class which is used to help generate the device tables (DT) +files. +""" +from dtgen.helper import IpHelper, Extension, StructType, ScalarType, ArrayMapType +from topgen.lib import Name +from typing import Optional +from collections import OrderedDict +import os +import sys + +sys.path.insert(0, os.path.dirname(os.path.realpath(__file__))) +from ipconfig import PwrmgrIpConfig # noqa: E402 + +HEADER_EXT_TEMPLATE = """ +/** + * Description of a wakeup source. + * + * A wakeup source is always identified by the instance ID of the module where it comes from. + * Some instances can have several wakeup signals, e.g. the pinmux has two (`pin` and `usb`). + * For such IPs, it is not sufficient to know the instance, we also need to know which + * signal triggered the wakeup. The `wakeup` index can be used to distinguish between those. + * This value should be casted to the `dt__wakeup_t` type of the corresponding IP. + * For example, if the `pwrmgr` has two `pinmux` wakeup sources as described above, it's + * two wakeup sources will be described as follows: + * ```c + * {.inst_id = kDtInstanceIdPinmux, .wakeup = kDtPinmuxWakeupPinWkupReq}, // for `pin` + * {.inst_id = kDtInstanceIdPinmux, .wakeup = kDtPinmuxWakeupUsbWkupReq}, // for `usb` + * ``` + */ +%(wakeup_src_struct)s + +/** + * Get the number of wakeup sources. + * + * @param dt Instance of pwrmgr. + * @return Number of wakeup sources. + */ +size_t dt_pwrmgr_wakeup_src_count(dt_pwrmgr_t dt); + +/** + * Get the description of a wakeup source. + * + * The wakeup sources are ordered as they appear in the registers. + * + * @param dt Instance of pwrmgr. + * @param idx Index of the wakeup source, between 0 and `dt_pwrmgr_wakeup_src_count(dt)-1`. + * @return Description of the source. + */ +dt_pwrmgr_wakeup_src_t dt_pwrmgr_wakeup_src(dt_pwrmgr_t dt, size_t idx); + +/** + * Description of a reset request source. + * + * A reset request source is always identified by the instance ID of the module where it comes + * from. In principle, some instances could have several reset requests. If this is the case, + * the `rst_req` can be used to distinguish between those. It should be cast to the + * `dt__reset_req_t` type of the corresponding IP. + */ +%(reset_req_src_struct)s + +/** + * Get the number of peripheral reset requests. + * + * @param dt Instance of pwrmgr. + * @return Number of reset requests. + */ +size_t dt_pwrmgr_reset_request_src_count(dt_pwrmgr_t dt); + +/** + * Get the description of a reset request. + * + * The reset requests are ordered as they appear in the registers. + * + * @param dt Instance of pwrmgr. + * @param idx Index of the reset request source, between 0 and + * `dt_pwrmgr_reset_request_src_count(dt)-1`. + * @return Description of the reset. + */ +dt_pwrmgr_reset_req_src_t dt_pwrmgr_reset_request_src(dt_pwrmgr_t dt, size_t idx); +""" + +SOURCE_EXT_TEMPLATE = """ +size_t dt_pwrmgr_wakeup_src_count(dt_pwrmgr_t dt) { + return %(wakeup_src_count)d; +} + +dt_pwrmgr_wakeup_src_t dt_pwrmgr_wakeup_src(dt_pwrmgr_t dt, size_t idx) { + dt_pwrmgr_wakeup_src_t invalid = {.inst_id = kDtInstanceIdUnknown, .wakeup = 0}; + return TRY_GET_DT(dt, invalid)->pwrmgr_ext.wakeup_src[idx]; +} + +size_t dt_pwrmgr_reset_request_src_count(dt_pwrmgr_t dt) { + return %(reset_reqs_count)d; +} + +dt_pwrmgr_reset_req_src_t dt_pwrmgr_reset_request_src(dt_pwrmgr_t dt, size_t idx) { + dt_pwrmgr_reset_req_src_t invalid = {.inst_id = kDtInstanceIdUnknown, .reset_req = 0}; + return TRY_GET_DT(dt, invalid)->pwrmgr_ext.rst_reqs[idx]; +} +""" + + +class PwrmgrExt(Extension): + WAKEUP_SOURCE_STRUCT_NAME = Name.from_snake_case("dt_pwrmgr_wakeup_src") + WAKEUP_SOURCE_INST_FIELD_NAME = Name(["inst", "id"]) + WAKEUP_SOURCE_WAKEUP_FIELD_NAME = Name(["wakeup"]) + RSTREQ_SOURCE_STRUCT_NAME = Name.from_snake_case("dt_pwrmgr_reset_req_src") + RSTREQ_SOURCE_INST_FIELD_NAME = Name(["inst", "id"]) + RSTREQ_SOURCE_REQ_FIELD_NAME = Name(["reset", "req"]) + EXT_WAKEUP_SOURCES_FIELD_NAME = Name(["wakeup", "src"]) + EXT_RESET_REQS_FIELD_NAME = Name(["rst", "reqs"]) + + def __init__(self, ip_helper: IpHelper): + self.ip_helper = ip_helper + if self.ip_helper.ipconfig is None: + raise RuntimeError("the pwrmgr extension requires the ipconfig to be provided") + self.ipconfig = PwrmgrIpConfig(self.ip_helper.ipconfig) + + # Create a type to represent a wakeup. + self.wakeup_src_struct = StructType(self.WAKEUP_SOURCE_STRUCT_NAME) + self.wakeup_src_struct.add_field( + name = self.WAKEUP_SOURCE_INST_FIELD_NAME, + field_type = ScalarType(self.ip_helper.top_helper.DT_INSTANCE_ID_NAME), + docstring = "Instance ID of the source of this wakeup.", + ) + self.wakeup_src_struct.add_field( + name = self.WAKEUP_SOURCE_WAKEUP_FIELD_NAME, + field_type = ScalarType("size_t"), + docstring = "Index of the wakeup signal for that instance.", + ) + # Create a type to represent a reset request. + self.reset_req_src_struct = StructType(self.RSTREQ_SOURCE_STRUCT_NAME) + self.reset_req_src_struct.add_field( + name = self.RSTREQ_SOURCE_INST_FIELD_NAME, + field_type = ScalarType(self.ip_helper.top_helper.DT_INSTANCE_ID_NAME), + docstring = "Instance ID of the source of this reset request.", + ) + self.reset_req_src_struct.add_field( + name = self.RSTREQ_SOURCE_REQ_FIELD_NAME, + field_type = ScalarType("size_t"), + docstring = "Index of the reset request signal for that instance.", + ) + + @staticmethod + def create_ext(ip_helper: IpHelper): + if ip_helper.ip.name == "pwrmgr": + return PwrmgrExt(ip_helper) + + def extend_dt_ip(self) -> tuple[Name, StructType]: + wakeup_count = len(self.ipconfig.wakeup_list()) + rstreq_count = len(self.ipconfig.peripheral_reset_req_list()) + + st = StructType() + # Add field to list wakeup sources. + st.add_field( + name = self.EXT_WAKEUP_SOURCES_FIELD_NAME, + field_type = ArrayMapType( + elem_type = self.wakeup_src_struct, + index_type = ScalarType("size_t"), + length = str(wakeup_count), + ), + docstring = "List of wakeup sources, in the order of the register fields", + ) + # Add field to list reset requests. + st.add_field( + name = self.EXT_RESET_REQS_FIELD_NAME, + field_type = ArrayMapType( + elem_type = self.reset_req_src_struct, + index_type = ScalarType("size_t"), + length = str(rstreq_count), + ), + docstring = "List of reset requests, in the order of the register fields", + ) + return Name(["pwrmgr_ext"]), st + + def fill_dt_ip(self, m) -> Optional[dict]: + wakeup_srcs = {} + self._extra_includes = OrderedDict() + for (idx, wakeup) in enumerate(self.ipconfig.wakeup_list()): + # We need to create the wakeup name from another module. + module_type = self.ip_helper.top_helper.get_module_type(wakeup["module"]) + self._extra_includes[module_type] = None + wkup_name = Name(["dt"]) + wkup_name += Name.from_snake_case(module_type) + wkup_name += Name(["wakeup"]) + wkup_name += Name.from_snake_case(wakeup["name"]) + wakeup_srcs[str(idx)] = { + self.WAKEUP_SOURCE_INST_FIELD_NAME: Name.from_snake_case(wakeup["module"]), + self.WAKEUP_SOURCE_WAKEUP_FIELD_NAME: wkup_name.as_c_enum() + } + rst_reqs = {} + for (idx, reset) in enumerate(self.ipconfig.peripheral_reset_req_list()): + # We need to create the reset name from another module. + module_type = self.ip_helper.top_helper.get_module_type(reset["module"]) + self._extra_includes[module_type] = None + rstreq = Name(["dt"]) + rstreq += Name.from_snake_case(module_type) + rstreq += Name(["reset", "req"]) + rstreq += Name.from_snake_case( + self.ip_helper.simplify_reset_request_name(reset["name"])) + rst_reqs[str(idx)] = { + self.RSTREQ_SOURCE_INST_FIELD_NAME: Name.from_snake_case(reset["module"]), + self.RSTREQ_SOURCE_REQ_FIELD_NAME: rstreq.as_c_enum() + } + + return { + self.EXT_WAKEUP_SOURCES_FIELD_NAME: wakeup_srcs, + self.EXT_RESET_REQS_FIELD_NAME: rst_reqs, + } + + def render_dt_ip(self, pos: Extension.DtIpPos) -> str: + if pos == Extension.DtIpPos.HeaderEnd: + subs = { + 'wakeup_src_struct': self.wakeup_src_struct.render_type_def(), + 'reset_req_src_struct': self.reset_req_src_struct.render_type_def(), + } + return HEADER_EXT_TEMPLATE % subs + elif pos == Extension.DtIpPos.SourceIncludes: + includes = "" + for ip in self._extra_includes: + includes += f"#include \"dt_{ip}.h\"\n" + return includes + elif pos == Extension.DtIpPos.SourceEnd: + subs = { + 'wakeup_src_count': len(self.ipconfig.wakeup_list()), + 'reset_reqs_count': len(self.ipconfig.peripheral_reset_req_list()), + } + return SOURCE_EXT_TEMPLATE % subs + else: + return "" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/ipconfig.py b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/ipconfig.py new file mode 100644 index 00000000000..dd4adba56a7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/ipconfig.py @@ -0,0 +1,53 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +""" +This contains a class to access the pwrmgr's configuration from its ipconfig +files. +""" +from typing import List, Dict + + +class PwrmgrIpConfig: + def __init__(self, ipconfig: object): + """ + Initialize an `IpConfig` from an already loaded and parsed `ipconfig.hjson` + files. + """ + self.param_values = ipconfig["param_values"] + + def wakeup_list(self) -> List[Dict]: + """ + Return the list of wakeups: each wakeup is described by a dictionary + with the following fields: + - `name`: name of the wakeup . + - `module`: the module where the wakeup comes from. + + The list is ordered as in the description. + """ + assert self.param_values["NumWkups"] == len(self.param_values["Wkups"]) + return [ + { + "name": wkup["name"], + "module": wkup["module"], + } + for wkup in self.param_values["Wkups"] + ] + + def peripheral_reset_req_list(self) -> List[Dict]: + """ + Return the list of peripheral reset requests: each reset is described by + a dictionary with the following fields: + - `name`: name of the reset request. + - `module`: the module where the reset comes from. + + The list is ordered as in the description. + """ + assert self.param_values["NumRstReqs"] == len(self.param_values["rst_reqs"]["peripheral"]) + return [ + { + "name": rst["name"], + "module": rst["module"], + } + for rst in self.param_values["rst_reqs"]["peripheral"] + ] diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/reg_pwrmgr.py b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/reg_pwrmgr.py new file mode 100755 index 00000000000..736fbb81f89 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/util/reg_pwrmgr.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python3 +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +r"""Convert mako template to Hjson register description +""" +import argparse +import sys +from io import StringIO + +from mako.template import Template + + +def main(): + parser = argparse.ArgumentParser(prog="reg_pwrmgr") + parser.add_argument('input', + nargs='?', + metavar='file', + type=argparse.FileType('r'), + default=sys.stdin, + help='input template file') + parser.add_argument('--n_wkups', + type=int, + default=16, + help='Number of Wakeup sources') + + args = parser.parse_args() + + # Determine output: if stdin then stdout if not then ?? + out = StringIO() + + reg_tpl = Template(args.input.read()) + out.write( + reg_tpl.render(NumWkups=args.n_wkups)) + + print(out.getvalue()) + + out.close() + + +if __name__ == "__main__": + main() diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/BUILD new file mode 100644 index 00000000000..e48a9057646 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/BUILD @@ -0,0 +1,22 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob(["**/*.md"]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/README.md new file mode 100644 index 00000000000..aaf75d51a94 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/README.md @@ -0,0 +1,36 @@ +# RACL Control Technical specification + +# Overview + +This document specifies the functionality of the RACL control permission IP. +`racl_ctrl` is an interface between the TileLink bus and RACL policy distribution and error logs. +As a peripheral on the chip interconnect bus, it follows the [Comportability Specification](../../../../doc/contributing/hw/comportability/README.md). + +RACL itself is specified at [RACL: Register Access Control Architecture](../../../../doc/contributing/hw/racl/README.md). + +# Distribution of policies + +RACL policies on the system can be configured through [registers](doc/registers.md) in `racl_ctrl`. +Each policy is specified in a register named after that policy. +The set of policies is then distributed by `racl_ctrl` through as a single vector called `racl_policies_o`. + +# Error logs + +A subscribing IP can log an error with `racl_ctrl` using the IP's item in the `racl_error_i` port. +Similarly, a RACL error from outside of OpenTitan can be reported through a particular index of the `racl_error_external_i` port. +If multiple errors are logged at the same cycle, arbitration will record the one with the lowest index in this list: +- Items from `racl_error_i` (internal errors) +- Items from `racl_error_external_i` (errors from outside of OpenTitan) +- An error reported by `racl_ctrl` itself. + +If there is more than one error reported (concurrently or over several cycles), the `error_log.overflow` field will be set. +The log can be cleared by writing `1` to the `error_log.overflow` field. + +# Alerts and security + +A TileLink transaction with incorrect integrity bits will cause a TL integrity error. +This generates a `fatal_fault` alert. + +This instantiation of `racl_ctrl` uses shadowed policy registers. +A storage error (meaning that the shadowed copy is not an inverse) causes the `fatal_fault` alert. +An update error causes the `recov_ctrl_update_err` alert, which is not fatal. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data/BUILD new file mode 100644 index 00000000000..46eb9e3de67 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data/BUILD @@ -0,0 +1,12 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_racl_ctrl.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = ["racl_ctrl.hjson"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data/racl_ctrl.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data/racl_ctrl.hjson new file mode 100644 index 00000000000..789433c3fd1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data/racl_ctrl.hjson @@ -0,0 +1,319 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +# RACL Control register template +# +{ + name: "racl_ctrl", + human_name: "RACL Control", + one_line_desc: "Implements the RACL policy registers to distribute to subscribing IPs.", + one_paragraph_desc: ''' + Implements the RACL policy registers to distribute to subscribing IPs. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "43", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_racl_ctrl", + revisions: [ + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D0", + verification_stage: "V0", + dif_stage: "S0", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni"}, + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device", static_racl_support: true } + ], + // In order to not disturb the racl_ctrl address map, we place the alert test and interrupt + // registers manually at a safe offset after the main CSRs. + // TODO(#26748) Add tooling support to avoid manual placement of alert/interrupt registers + no_auto_intr_regs: "True", + no_auto_alert_regs: "True", + interrupt_list: [ + { name: "racl_error", + desc: "RACL error has occurred.", + type: "status" + } + ] + alert_list: [ + { name: "fatal_fault" + desc: "This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected." + } + { name: "recov_ctrl_update_err", + desc: "This recoverable alert is triggered upon detecting an update error in the shadowed Control Register." + } + ], + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "RACL_POLICY.CONFIG.SHADOW", + desc: "RACL policy registers are shadowed." + } + ] + regwidth: "32", + param_list: [ + { name: "NumSubscribingIps", + desc: "Number of subscribing RACL IPs", + type: "int", + default: "11", + expose: "true" + local: "true" + }, + { name: "NumExternalSubscribingIps", + desc: "Number of external subscribing RACL IPs", + type: "int", + default: "1", + expose: "true" + local: "false" + }, + ], + inter_signal_list: [ + { struct: "racl_policy_vec", + type: "uni", + name: "racl_policies", + act: "req", + package: "top_racl_pkg", + desc: ''' + Policy vector distributed to the subscribing RACL IPs. + ''' + } + { struct: "racl_error_log", + type: "uni", + name: "racl_error", + act: "rcv", + width: "NumSubscribingIps" + package: "top_racl_pkg", + desc: ''' + Error log information from all IPs. + Only one IP can raise an error at a time. + ''' + } + { struct: "racl_error_log", + type: "uni", + name: "racl_error_external", + act: "rcv", + width: "NumExternalSubscribingIps" + package: "top_racl_pkg", + desc: ''' + Error log information from all external IPs. + Only one IP can raise an error at a time. + ''' + } + ], + + registers: [ + { name: "POLICY_ALL_RD_WR_SHADOWED" + desc: ''' + Read and write policy for ALL_RD_WR + ''' + swaccess: "rw" + hwaccess: "hro" + shadowed: "true" + update_err_alert: "recov_ctrl_update_err" + storage_err_alert: "fatal_fault" + fields: [ + { bits: "31:16" + name: "write_perm" + resval: 7 + desc: ''' + Write permission for policy ALL_RD_WR + ''' + } + { bits: "15:0" + name: "read_perm" + resval: 7 + desc: ''' + Read permission for policy ALL_RD_WR + ''' + } + ] + } + { reserved: "1" } + { name: "POLICY_ROT_PRIVATE_SHADOWED" + desc: ''' + Read and write policy for ROT_PRIVATE + ''' + swaccess: "rw" + hwaccess: "hro" + shadowed: "true" + update_err_alert: "recov_ctrl_update_err" + storage_err_alert: "fatal_fault" + fields: [ + { bits: "31:16" + name: "write_perm" + resval: 1 + desc: ''' + Write permission for policy ROT_PRIVATE + ''' + } + { bits: "15:0" + name: "read_perm" + resval: 1 + desc: ''' + Read permission for policy ROT_PRIVATE + ''' + } + ] + } + { reserved: "1" } + { name: "POLICY_SOC_ROT_SHADOWED" + desc: ''' + Read and write policy for SOC_ROT + ''' + swaccess: "rw" + hwaccess: "hro" + shadowed: "true" + update_err_alert: "recov_ctrl_update_err" + storage_err_alert: "fatal_fault" + fields: [ + { bits: "31:16" + name: "write_perm" + resval: 5 + desc: ''' + Write permission for policy SOC_ROT + ''' + } + { bits: "15:0" + name: "read_perm" + resval: 5 + desc: ''' + Read permission for policy SOC_ROT + ''' + } + ] + } + { reserved: "1" } + { skipto: "0xE8" } + { name: "INTR_STATE", + desc: "Interrupt State Register", + swaccess: "ro", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "racl_error", + desc: ''' + Interrupt status. The interrupt is raised when a RACL error occurs and cleared + when error_log is cleared by writing 1 to error_log.valid." + ''' + } + ] + tags: [// interrupt could be updated by HW + "excl:CsrNonInitTests:CsrExclWriteCheck"], + }, + { name: "INTR_ENABLE", + desc: "Interrupt Enable Register", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", + name: "IE", + desc: "Interrupt Enable" + } + ] + }, + { name: "INTR_TEST", + desc: "Interrupt Test Register", + swaccess: "wo", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { bits: "0", + name: "racl_error", + desc: "Write 1 to force racl_error interrupt", + } + ] + }, + { name: "ALERT_TEST", + desc: '''Alert Test Register.''', + swaccess: "wo", + hwaccess: "hro", + hwqe: "True", + hwext: "True", + fields: [ + { bits: "0", + name: "fatal_fault", + desc: "'Write 1 to trigger one alert event of this kind.'", + } + { bits: "1", + name: "recov_ctrl_update_err", + desc: "'Write 1 to trigger one alert event of this kind.'", + } + ], + } + { name: "ERROR_LOG" + desc: "Error logging registers" + swaccess: "ro" + hwaccess: "hwo" + hwqe: "true" + fields: [ + { bits: "0" + name: "valid" + resval: 0x0 + swaccess: "rw1c" + hwaccess: "hrw" + desc: ''' + Indicates a RACL error and the log register contains valid data. + Writing a one clears this register and the !!ERROR_LOG_ADDRESS register. + ''' + } + { bits: "1" + name: "overflow" + resval: 0x0 + desc: ''' + Indicates a RACL error overflow when a RACL error occurred while the log register was set. + ''' + } + { bits: "2" + name: "read_access" + resval: 0x0 + desc: ''' + 0: Write transfer was denied. + 1: Read transfer was denied. + ''' + } + { bits: "6:3" + name: "role" + resval: 0x0 + desc: ''' + RACL role causing the error. + ''' + } + { bits: "11:7" + name: "ctn_uid" + resval: 0x0 + desc: ''' + CTN UID causing the error. + ''' + } + ] + } + { name: "ERROR_LOG_ADDRESS" + desc: '''Contains the address on which a RACL violation occurred. + This register is valid if and only if the `valid` field of !!ERROR_LOG is true. + Once valid, the address doesn't change (even if there are subsequent RACL violations) until the register gets cleared. + This register gets cleared when SW writes `1` to the `valid` field of the !!ERROR_LOG register. + ''' + swaccess: "ro" + hwaccess: "hwo" + fields: [ + { bits: "31:0" + name: "address" + resval: 0x0 + desc: ''' + Address on which a RACL violation occurred. + ''' + } + ] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data/top_darjeeling_no_ibex_racl_ctrl.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data/top_darjeeling_no_ibex_racl_ctrl.ipconfig.hjson new file mode 100644 index 00000000000..82d35ffb1c8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data/top_darjeeling_no_ibex_racl_ctrl.ipconfig.hjson @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_racl_ctrl + param_values: + { + module_instance_name: racl_ctrl + nr_role_bits: 4 + nr_ctn_uid_bits: 5 + nr_policies: 3 + nr_subscribing_ips: 11 + policies: + [ + { + name: ALL_RD_WR + desc: Standard policies allowing all roles to access a register + allowed_rd: + [ + ROT + ROLE1 + SOC + ] + allowed_wr: + [ + ROT + ROLE1 + SOC + ] + rd_default: 7 + wr_default: 7 + } + { + name: ROT_PRIVATE + rot_private: true + desc: Standard policies allowing only the ROT role to access a register + allowed_rd: + [ + ROT + ] + allowed_wr: + [ + ROT + ] + rd_default: 1 + wr_default: 1 + } + { + name: SOC_ROT + desc: Custom policy + allowed_rd: + [ + ROT + SOC + ] + allowed_wr: + [ + ROT + SOC + ] + rd_default: 5 + wr_default: 5 + } + ] + topname: darjeeling_no_ibex + uniquified_modules: {} + enable_shadow_reg: true + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/defs.bzl new file mode 100644 index 00000000000..7587265cf0b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/defs.bzl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +RACL_CTRL = opentitan_ip( + name = "racl_ctrl", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/data:racl_ctrl.hjson", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/doc/interfaces.md b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/doc/interfaces.md new file mode 100644 index 00000000000..aaed0fc14ae --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/doc/interfaces.md @@ -0,0 +1,41 @@ +# Hardware Interfaces + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`racl_ctrl`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: *none* +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:--------------------|:------------------------------|:--------|:------|:--------------------------|:---------------------------------------------------------------------------------------| +| racl_policies | top_racl_pkg::racl_policy_vec | uni | req | 1 | Policy vector distributed to the subscribing RACL IPs. | +| racl_error | top_racl_pkg::racl_error_log | uni | rcv | NumSubscribingIps | Error log information from all IPs. Only one IP can raise an error at a time. | +| racl_error_external | top_racl_pkg::racl_error_log | uni | rcv | NumExternalSubscribingIps | Error log information from all external IPs. Only one IP can raise an error at a time. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Interrupts + +| Interrupt Name | Type | Description | +|:-----------------|:-------|:-------------------------| +| racl_error | Status | RACL error has occurred. | + +## Security Alerts + +| Alert Name | Description | +|:----------------------|:-----------------------------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. | +| recov_ctrl_update_err | This recoverable alert is triggered upon detecting an update error in the shadowed Control Register. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:------------------------------------|:------------------------------------| +| RACL_CTRL.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| RACL_CTRL.RACL_POLICY.CONFIG.SHADOW | RACL policy registers are shadowed. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/doc/racl_configuration.md b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/doc/racl_configuration.md new file mode 100644 index 00000000000..3ee709cc2d5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/doc/racl_configuration.md @@ -0,0 +1,356 @@ +# RACL Configuration + + +## RACL groups + +### RACL group: Null + +| Policy Name | Index | Description | +|:--------------|--------:|:------------------------------------------------------------------| +| ALL_RD_WR | 0 | Standard policies allowing all roles to access a register | +| ROT_PRIVATE | 1 | Standard policies allowing only the ROT role to access a register | +| SOC_ROT | 2 | Custom policy | + + +## RACL configuration + +### RACL configuration for `mbx0` and interface `soc` + +- IP: mbx +- Instance base address: 0x1465000 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:---------------------------------|:---------|:----------|:--------|:--------------|:------|:--------|:------| +| mbx0.soc.`SOC_CONTROL` | 0x8 | 0x1465008 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx0.soc.`SOC_STATUS` | 0xc | 0x146500c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx0.soc.`WDATA` | 0x10 | 0x1465010 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx0.soc.`RDATA` | 0x14 | 0x1465014 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx0.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x1465018 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx0.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x146501c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | + +### RACL configuration for `mbx1` and interface `soc` + +- IP: mbx +- Instance base address: 0x1465100 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:---------------------------------|:---------|:----------|:--------|:--------------|:------|:--------|:------| +| mbx1.soc.`SOC_CONTROL` | 0x8 | 0x1465108 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx1.soc.`SOC_STATUS` | 0xc | 0x146510c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx1.soc.`WDATA` | 0x10 | 0x1465110 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx1.soc.`RDATA` | 0x14 | 0x1465114 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx1.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x1465118 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx1.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x146511c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | + +### RACL configuration for `mbx2` and interface `soc` + +- IP: mbx +- Instance base address: 0x1465200 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:---------------------------------|:---------|:----------|:--------|:--------------|:------|:--------|:------| +| mbx2.soc.`SOC_CONTROL` | 0x8 | 0x1465208 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx2.soc.`SOC_STATUS` | 0xc | 0x146520c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx2.soc.`WDATA` | 0x10 | 0x1465210 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx2.soc.`RDATA` | 0x14 | 0x1465214 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx2.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x1465218 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx2.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x146521c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | + +### RACL configuration for `mbx3` and interface `soc` + +- IP: mbx +- Instance base address: 0x1465300 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:---------------------------------|:---------|:----------|:--------|:--------------|:------|:--------|:------| +| mbx3.soc.`SOC_CONTROL` | 0x8 | 0x1465308 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx3.soc.`SOC_STATUS` | 0xc | 0x146530c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx3.soc.`WDATA` | 0x10 | 0x1465310 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx3.soc.`RDATA` | 0x14 | 0x1465314 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx3.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x1465318 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx3.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x146531c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | + +### RACL configuration for `mbx4` and interface `soc` + +- IP: mbx +- Instance base address: 0x1465400 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:---------------------------------|:---------|:----------|:--------|:--------------|:------|:--------|:------| +| mbx4.soc.`SOC_CONTROL` | 0x8 | 0x1465408 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx4.soc.`SOC_STATUS` | 0xc | 0x146540c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx4.soc.`WDATA` | 0x10 | 0x1465410 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx4.soc.`RDATA` | 0x14 | 0x1465414 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx4.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x1465418 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx4.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x146541c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | + +### RACL configuration for `mbx5` and interface `soc` + +- IP: mbx +- Instance base address: 0x1465500 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:---------------------------------|:---------|:----------|:--------|:--------------|:------|:--------|:------| +| mbx5.soc.`SOC_CONTROL` | 0x8 | 0x1465508 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx5.soc.`SOC_STATUS` | 0xc | 0x146550c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx5.soc.`WDATA` | 0x10 | 0x1465510 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx5.soc.`RDATA` | 0x14 | 0x1465514 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx5.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x1465518 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx5.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x146551c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | + +### RACL configuration for `mbx6` and interface `soc` + +- IP: mbx +- Instance base address: 0x1496000 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:---------------------------------|:---------|:----------|:--------|:--------------|:------|:--------|:------| +| mbx6.soc.`SOC_CONTROL` | 0x8 | 0x1496008 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx6.soc.`SOC_STATUS` | 0xc | 0x149600c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx6.soc.`WDATA` | 0x10 | 0x1496010 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx6.soc.`RDATA` | 0x14 | 0x1496014 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx6.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x1496018 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx6.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x149601c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | + +### RACL configuration for `mbx_jtag` and interface `soc` + +- IP: mbx +- Instance base address: 0x2200 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:-------------------------------------|:---------|:----------|:--------|:--------------|:------|:--------|:------| +| mbx_jtag.soc.`SOC_CONTROL` | 0x8 | 0x2208 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx_jtag.soc.`SOC_STATUS` | 0xc | 0x220c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx_jtag.soc.`WDATA` | 0x10 | 0x2210 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx_jtag.soc.`RDATA` | 0x14 | 0x2214 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx_jtag.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x2218 | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | +| mbx_jtag.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x221c | 0x4 | 0 (ALL_RD_WR) | R / W | R / W | R / W | + +### RACL configuration for `mbx_pcie0` and interface `soc` + +- IP: mbx +- Instance base address: 0x1460100 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:--------------------------------------|:---------|:----------|:--------|:------------|:------|:--------|:------| +| mbx_pcie0.soc.`SOC_CONTROL` | 0x8 | 0x1460108 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie0.soc.`SOC_STATUS` | 0xc | 0x146010c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie0.soc.`WDATA` | 0x10 | 0x1460110 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie0.soc.`RDATA` | 0x14 | 0x1460114 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie0.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x1460118 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie0.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x146011c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | + +### RACL configuration for `mbx_pcie1` and interface `soc` + +- IP: mbx +- Instance base address: 0x1460200 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:--------------------------------------|:---------|:----------|:--------|:------------|:------|:--------|:------| +| mbx_pcie1.soc.`SOC_CONTROL` | 0x8 | 0x1460208 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie1.soc.`SOC_STATUS` | 0xc | 0x146020c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie1.soc.`WDATA` | 0x10 | 0x1460210 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie1.soc.`RDATA` | 0x14 | 0x1460214 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie1.soc.`SOC_DOE_INTR_MSG_ADDR` | 0x18 | 0x1460218 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| mbx_pcie1.soc.`SOC_DOE_INTR_MSG_DATA` | 0x1c | 0x146021c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | + +### RACL configuration for `ac_range_check` and interface `null` + +- IP: ac_range_check +- Instance base address: 0x1464000 +- RACL group: Null + + +| Name | Offset | Address | Width | Policy | ROT | ROLE1 | SOC | +|:-----------------------------------------------|:---------|:----------|:--------|:------------|:------|:--------|:------| +| ac_range_check.`INTR_STATE` | 0x0 | 0x1464000 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`INTR_ENABLE` | 0x4 | 0x1464004 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`INTR_TEST` | 0x8 | 0x1464008 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`ALERT_TEST` | 0xc | 0x146400c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`ALERT_STATUS` | 0x10 | 0x1464010 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`LOG_CONFIG` | 0x14 | 0x1464014 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`LOG_STATUS` | 0x18 | 0x1464018 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`LOG_ADDRESS` | 0x1c | 0x146401c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_0` | 0x20 | 0x1464020 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_1` | 0x24 | 0x1464024 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_2` | 0x28 | 0x1464028 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_3` | 0x2c | 0x146402c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_4` | 0x30 | 0x1464030 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_5` | 0x34 | 0x1464034 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_6` | 0x38 | 0x1464038 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_7` | 0x3c | 0x146403c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_8` | 0x40 | 0x1464040 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_9` | 0x44 | 0x1464044 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_10` | 0x48 | 0x1464048 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_11` | 0x4c | 0x146404c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_12` | 0x50 | 0x1464050 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_13` | 0x54 | 0x1464054 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_14` | 0x58 | 0x1464058 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_15` | 0x5c | 0x146405c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_16` | 0x60 | 0x1464060 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_17` | 0x64 | 0x1464064 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_18` | 0x68 | 0x1464068 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_19` | 0x6c | 0x146406c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_20` | 0x70 | 0x1464070 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_21` | 0x74 | 0x1464074 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_22` | 0x78 | 0x1464078 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_23` | 0x7c | 0x146407c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_24` | 0x80 | 0x1464080 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_25` | 0x84 | 0x1464084 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_26` | 0x88 | 0x1464088 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_27` | 0x8c | 0x146408c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_28` | 0x90 | 0x1464090 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_29` | 0x94 | 0x1464094 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_30` | 0x98 | 0x1464098 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_REGWEN_31` | 0x9c | 0x146409c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_0` | 0xa0 | 0x14640a0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_1` | 0xa4 | 0x14640a4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_2` | 0xa8 | 0x14640a8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_3` | 0xac | 0x14640ac | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_4` | 0xb0 | 0x14640b0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_5` | 0xb4 | 0x14640b4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_6` | 0xb8 | 0x14640b8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_7` | 0xbc | 0x14640bc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_8` | 0xc0 | 0x14640c0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_9` | 0xc4 | 0x14640c4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_10` | 0xc8 | 0x14640c8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_11` | 0xcc | 0x14640cc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_12` | 0xd0 | 0x14640d0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_13` | 0xd4 | 0x14640d4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_14` | 0xd8 | 0x14640d8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_15` | 0xdc | 0x14640dc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_16` | 0xe0 | 0x14640e0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_17` | 0xe4 | 0x14640e4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_18` | 0xe8 | 0x14640e8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_19` | 0xec | 0x14640ec | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_20` | 0xf0 | 0x14640f0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_21` | 0xf4 | 0x14640f4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_22` | 0xf8 | 0x14640f8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_23` | 0xfc | 0x14640fc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_24` | 0x100 | 0x1464100 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_25` | 0x104 | 0x1464104 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_26` | 0x108 | 0x1464108 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_27` | 0x10c | 0x146410c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_28` | 0x110 | 0x1464110 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_29` | 0x114 | 0x1464114 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_30` | 0x118 | 0x1464118 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_BASE_31` | 0x11c | 0x146411c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_0` | 0x120 | 0x1464120 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_1` | 0x124 | 0x1464124 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_2` | 0x128 | 0x1464128 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_3` | 0x12c | 0x146412c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_4` | 0x130 | 0x1464130 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_5` | 0x134 | 0x1464134 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_6` | 0x138 | 0x1464138 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_7` | 0x13c | 0x146413c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_8` | 0x140 | 0x1464140 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_9` | 0x144 | 0x1464144 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_10` | 0x148 | 0x1464148 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_11` | 0x14c | 0x146414c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_12` | 0x150 | 0x1464150 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_13` | 0x154 | 0x1464154 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_14` | 0x158 | 0x1464158 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_15` | 0x15c | 0x146415c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_16` | 0x160 | 0x1464160 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_17` | 0x164 | 0x1464164 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_18` | 0x168 | 0x1464168 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_19` | 0x16c | 0x146416c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_20` | 0x170 | 0x1464170 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_21` | 0x174 | 0x1464174 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_22` | 0x178 | 0x1464178 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_23` | 0x17c | 0x146417c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_24` | 0x180 | 0x1464180 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_25` | 0x184 | 0x1464184 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_26` | 0x188 | 0x1464188 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_27` | 0x18c | 0x146418c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_28` | 0x190 | 0x1464190 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_29` | 0x194 | 0x1464194 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_30` | 0x198 | 0x1464198 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_LIMIT_31` | 0x19c | 0x146419c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_0` | 0x1a0 | 0x14641a0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_1` | 0x1a4 | 0x14641a4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_2` | 0x1a8 | 0x14641a8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_3` | 0x1ac | 0x14641ac | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_4` | 0x1b0 | 0x14641b0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_5` | 0x1b4 | 0x14641b4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_6` | 0x1b8 | 0x14641b8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_7` | 0x1bc | 0x14641bc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_8` | 0x1c0 | 0x14641c0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_9` | 0x1c4 | 0x14641c4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_10` | 0x1c8 | 0x14641c8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_11` | 0x1cc | 0x14641cc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_12` | 0x1d0 | 0x14641d0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_13` | 0x1d4 | 0x14641d4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_14` | 0x1d8 | 0x14641d8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_15` | 0x1dc | 0x14641dc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_16` | 0x1e0 | 0x14641e0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_17` | 0x1e4 | 0x14641e4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_18` | 0x1e8 | 0x14641e8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_19` | 0x1ec | 0x14641ec | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_20` | 0x1f0 | 0x14641f0 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_21` | 0x1f4 | 0x14641f4 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_22` | 0x1f8 | 0x14641f8 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_23` | 0x1fc | 0x14641fc | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_24` | 0x200 | 0x1464200 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_25` | 0x204 | 0x1464204 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_26` | 0x208 | 0x1464208 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_27` | 0x20c | 0x146420c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_28` | 0x210 | 0x1464210 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_29` | 0x214 | 0x1464214 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_30` | 0x218 | 0x1464218 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_ATTR_31` | 0x21c | 0x146421c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_0` | 0x220 | 0x1464220 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_1` | 0x224 | 0x1464224 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_2` | 0x228 | 0x1464228 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_3` | 0x22c | 0x146422c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_4` | 0x230 | 0x1464230 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_5` | 0x234 | 0x1464234 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_6` | 0x238 | 0x1464238 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_7` | 0x23c | 0x146423c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_8` | 0x240 | 0x1464240 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_9` | 0x244 | 0x1464244 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_10` | 0x248 | 0x1464248 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_11` | 0x24c | 0x146424c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_12` | 0x250 | 0x1464250 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_13` | 0x254 | 0x1464254 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_14` | 0x258 | 0x1464258 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_15` | 0x25c | 0x146425c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_16` | 0x260 | 0x1464260 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_17` | 0x264 | 0x1464264 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_18` | 0x268 | 0x1464268 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_19` | 0x26c | 0x146426c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_20` | 0x270 | 0x1464270 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_21` | 0x274 | 0x1464274 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_22` | 0x278 | 0x1464278 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_23` | 0x27c | 0x146427c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_24` | 0x280 | 0x1464280 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_25` | 0x284 | 0x1464284 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_26` | 0x288 | 0x1464288 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_27` | 0x28c | 0x146428c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_28` | 0x290 | 0x1464290 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_29` | 0x294 | 0x1464294 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_30` | 0x298 | 0x1464298 | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | +| ac_range_check.`RANGE_RACL_POLICY_SHADOWED_31` | 0x29c | 0x146429c | 0x4 | 2 (SOC_ROT) | R / W | - / - | R / W | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/doc/registers.md b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/doc/registers.md new file mode 100644 index 00000000000..3debaf05f86 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/doc/registers.md @@ -0,0 +1,179 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:------------------------------------------------------------------------|:---------|---------:|:---------------------------------------------------------| +| racl_ctrl.[`POLICY_ALL_RD_WR_SHADOWED`](#policy_all_rd_wr_shadowed) | 0x0 | 4 | Read and write policy for ALL_RD_WR | +| racl_ctrl.[`POLICY_ROT_PRIVATE_SHADOWED`](#policy_rot_private_shadowed) | 0x8 | 4 | Read and write policy for ROT_PRIVATE | +| racl_ctrl.[`POLICY_SOC_ROT_SHADOWED`](#policy_soc_rot_shadowed) | 0x10 | 4 | Read and write policy for SOC_ROT | +| racl_ctrl.[`INTR_STATE`](#intr_state) | 0xe8 | 4 | Interrupt State Register | +| racl_ctrl.[`INTR_ENABLE`](#intr_enable) | 0xec | 4 | Interrupt Enable Register | +| racl_ctrl.[`INTR_TEST`](#intr_test) | 0xf0 | 4 | Interrupt Test Register | +| racl_ctrl.[`ALERT_TEST`](#alert_test) | 0xf4 | 4 | Alert Test Register. | +| racl_ctrl.[`ERROR_LOG`](#error_log) | 0xf8 | 4 | Error logging registers | +| racl_ctrl.[`ERROR_LOG_ADDRESS`](#error_log_address) | 0xfc | 4 | Contains the address on which a RACL violation occurred. | + +## POLICY_ALL_RD_WR_SHADOWED +Read and write policy for ALL_RD_WR +- Offset: `0x0` +- Reset default: `0x70007` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "read_perm", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "write_perm", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------|:--------------------------------------| +| 31:16 | rw | 0x7 | write_perm | Write permission for policy ALL_RD_WR | +| 15:0 | rw | 0x7 | read_perm | Read permission for policy ALL_RD_WR | + +## POLICY_ROT_PRIVATE_SHADOWED +Read and write policy for ROT_PRIVATE +- Offset: `0x8` +- Reset default: `0x10001` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "read_perm", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "write_perm", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------|:----------------------------------------| +| 31:16 | rw | 0x1 | write_perm | Write permission for policy ROT_PRIVATE | +| 15:0 | rw | 0x1 | read_perm | Read permission for policy ROT_PRIVATE | + +## POLICY_SOC_ROT_SHADOWED +Read and write policy for SOC_ROT +- Offset: `0x10` +- Reset default: `0x50005` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "read_perm", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "write_perm", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------|:------------------------------------| +| 31:16 | rw | 0x5 | write_perm | Write permission for policy SOC_ROT | +| 15:0 | rw | 0x5 | read_perm | Read permission for policy SOC_ROT | + +## INTR_STATE +Interrupt State Register +- Offset: `0xe8` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "racl_error", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------|:-------------------------------------------------------------------------------------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | ro | 0x0 | racl_error | Interrupt status. The interrupt is raised when a RACL error occurs and cleared when error_log is cleared by writing 1 to error_log.valid." | + +## INTR_ENABLE +Interrupt Enable Register +- Offset: `0xec` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "IE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | IE | Interrupt Enable | + +## INTR_TEST +Interrupt Test Register +- Offset: `0xf0` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "racl_error", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-----------|:--------------------------------------| +| 31:1 | | | | Reserved | +| 0 | wo | x | racl_error | Write 1 to force racl_error interrupt | + +## ALERT_TEST +Alert Test Register. +- Offset: `0xf4` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "recov_ctrl_update_err", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------|:---------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | wo | x | recov_ctrl_update_err | 'Write 1 to trigger one alert event of this kind.' | +| 0 | wo | x | fatal_fault | 'Write 1 to trigger one alert event of this kind.' | + +## ERROR_LOG +Error logging registers +- Offset: `0xf8` +- Reset default: `0x0` +- Reset mask: `0xfff` + +### Fields + +```wavejson +{"reg": [{"name": "valid", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "overflow", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "read_access", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "role", "bits": 4, "attr": ["ro"], "rotate": 0}, {"name": "ctn_uid", "bits": 5, "attr": ["ro"], "rotate": 0}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:12 | | | | Reserved | +| 11:7 | ro | 0x0 | ctn_uid | CTN UID causing the error. | +| 6:3 | ro | 0x0 | role | RACL role causing the error. | +| 2 | ro | 0x0 | read_access | 0: Write transfer was denied. 1: Read transfer was denied. | +| 1 | ro | 0x0 | overflow | Indicates a RACL error overflow when a RACL error occurred while the log register was set. | +| 0 | rw1c | 0x0 | valid | Indicates a RACL error and the log register contains valid data. Writing a one clears this register and the [`ERROR_LOG_ADDRESS`](#error_log_address) register. | + +## ERROR_LOG_ADDRESS +Contains the address on which a RACL violation occurred. + This register is valid if and only if the `valid` field of [`ERROR_LOG`](#error_log) is true. + Once valid, the address doesn't change (even if there are subsequent RACL violations) until the register gets cleared. + This register gets cleared when SW writes `1` to the `valid` field of the [`ERROR_LOG`](#error_log) register. +- Offset: `0xfc` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "address", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------------------------------------| +| 31:0 | ro | 0x0 | address | Address on which a RACL violation occurred. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/racl_ctrl_ral.core b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/racl_ctrl_ral.core new file mode 100644 index 00000000000..3db441b9143 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/racl_ctrl_ral.core @@ -0,0 +1,27 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:racl_ctrl_ral:0.1 +description: "RACL_CTRL register model" +virtual: + - "lowrisc:dv:racl_ctrl_ral" +filesets: + ral_dep: + depend: + - lowrisc:dv:ralgen + +generate: + ral: + generator: ralgen + parameters: + name: racl_ctrl + ip_hjson: ../data/racl_ctrl.hjson + position: prepend + +targets: + default: + filesets: + - ral_dep + generate: + - ral diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/racl_ctrl_sim.core b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/racl_ctrl_sim.core new file mode 100644 index 00000000000..107dff4213c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/racl_ctrl_sim.core @@ -0,0 +1,31 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:racl_ctrl_sim:0.1 +description: "A racl_ctrl simulation" +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_constants:top_racl_pkg + - lowrisc:darjeeling_no_ibex_ip:racl_ctrl + + files_dv: + depend: + - lowrisc:dv:racl_ctrl_test + - lowrisc:darjeeling_no_ibex_dv:racl_ctrl_sva + files: + - tb.sv + file_type: systemVerilogSource + + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/racl_ctrl_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/racl_ctrl_sim_cfg.hjson new file mode 100644 index 00000000000..154d077a1d7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/racl_ctrl_sim_cfg.hjson @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_dv:racl_ctrl_sim:0.1 + + // RAL spec - used to generate the RAL model. + ral_spec: "{self_dir}/../data/racl_ctrl.hjson" + + // Top level dut module name + dut: racl_ctrl + + // Tell the tool to include the bind module as a top-level. Since the name of the bind module is + // templated, this needs to be done here. + sim_tops: ["racl_ctrl_bind"] + + // Import the underlying sim_cfg (not templated) + import_cfgs: ["{proj_root}/hw/ip/racl_ctrl/dv/racl_ctrl_tests.hjson"] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/sva/racl_ctrl_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/sva/racl_ctrl_bind.sv new file mode 100644 index 00000000000..e3f2cb61da0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/sva/racl_ctrl_bind.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module racl_ctrl_bind; + + bind racl_ctrl tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind racl_ctrl racl_ctrl_csr_assert_fpv racl_ctrl_csr_assert ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/sva/racl_ctrl_sva.core b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/sva/racl_ctrl_sva.core new file mode 100644 index 00000000000..7561790f3cf --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/sva/racl_ctrl_sva.core @@ -0,0 +1,41 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Register assertions and bind file. This needs to be templated because it +# needs the register layout (from racl_ctrl.hjson) to know what registers exist. + +name: lowrisc:darjeeling_no_ibex_dv:racl_ctrl_sva:0.1 +description: "RACL_CTRL assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:tlul:headers + - lowrisc:fpv:csr_assert_gen + files: + - racl_ctrl_bind.sv + file_type: systemVerilogSource + + files_formal: + depend: + - lowrisc:darjeeling_no_ibex_ip:racl_ctrl + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/racl_ctrl.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + formal: + <<: *default_target + filesets: + - files_formal + - files_dv + toplevel: racl_ctrl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/tb.sv new file mode 100644 index 00000000000..eadec2bd9c7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/dv/tb.sv @@ -0,0 +1,61 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + import uvm_pkg::*; + import dv_utils_pkg::*; + + // Note that the tb itself doesn't really need to import the test package. But we *do* need to + // make sure that the EDA tool doesn't throw away the package at elaboration time, because we want + // the classes inside it to exist so that their static variables cause them to be registered with + // the UVM factory. + import racl_ctrl_test_pkg::racl_ctrl_base_test; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n, rst_shadowed_n; + + clk_rst_if clk_rst_if (.clk(clk), .rst_n(rst_n)); + rst_shadowed_if rst_shad_if (.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n)); + tl_if tl_if (.clk(clk), .rst_n(rst_n)); + racl_ctrl_policies_if policies_if (); + + // Information about the names of alerts and their indices (used by DV_ALERT_IF_CONNECT to attach + // interfaces to the ports and register them with the config db) + localparam int unsigned NUM_ALERTS = 2; + localparam string LIST_OF_ALERTS[NUM_ALERTS] = {"fatal_fault", "recov_ctrl_update_err"}; + + `DV_ALERT_IF_CONNECT() + + racl_ctrl dut ( + .clk_i (clk ), + .rst_ni (rst_n ), + .rst_shadowed_ni (rst_shadowed_n ), + + .tl_i (tl_if.h2d ), + .tl_o (tl_if.d2h ), + + .alert_rx_i (alert_rx ), + .alert_tx_o (alert_tx ), + + .racl_policies_o (policies_if.policies ), + .racl_error_i ( /* TODO: Not yet connecting error input */ '0 ), + .racl_error_external_i ( /* TODO: Not yet connecting external error input */ '0 ) + ); + + initial begin + // drive clk and rst_n from clk_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shad_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + uvm_config_db#(virtual racl_ctrl_policies_if)::set(null, "*.env", "policies_if", policies_if); + + $timeformat(-12, 0, " ps", 12); + run_test(); + end + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/lint/racl_ctrl.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/lint/racl_ctrl.waiver new file mode 100644 index 00000000000..615fc14a6f4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/lint/racl_ctrl.waiver @@ -0,0 +1,10 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for racl_ctrl + +waive -rules {HIER_NET_NOT_READ} -location {racl_ctrl_reg_top.sv} -regexp {error_log_flds_we\[4:1\]' is not read from in module} \ + -comment "Internal register is accepted to not be read. Tracked in #25663." + +waive -rules {LINE_LENGTH} -location {racl_ctrl_reg_pkg.sv} -comment "Auto generated lines may be too long" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/racl_ctrl.core b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/racl_ctrl.core new file mode 100644 index 00000000000..506248502d5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/racl_ctrl.core @@ -0,0 +1,68 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:racl_ctrl:0.1 +description: "RACL Control permission IP" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:mubi + - lowrisc:prim:all + - lowrisc:prim:racl_error_arb + # TODO: This is used by the register top and shouldn't be pulled explicitly here. + - lowrisc:prim:onehot + - lowrisc:darjeeling_no_ibex_constants:top_racl_pkg + files: + - rtl/racl_ctrl_reg_pkg.sv + - rtl/racl_ctrl_reg_top.sv + - rtl/racl_ctrl.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/racl_ctrl.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl + toplevel: racl_ctrl + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/rtl/racl_ctrl.sv b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/rtl/racl_ctrl.sv new file mode 100644 index 00000000000..273998e1bfc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/rtl/racl_ctrl.sv @@ -0,0 +1,219 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module racl_ctrl import racl_ctrl_reg_pkg::*; #( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert signal + parameter int unsigned AlertSkewCycles = 1, + parameter int unsigned NumSubscribingIps = 1, + parameter int unsigned NumExternalSubscribingIps = 1, + parameter bit RaclErrorRsp = 1'b1 +) ( + input logic clk_i, + input logic rst_ni, + input logic rst_shadowed_ni, + // Bus Interface (device) + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + // Interrupt + output logic intr_racl_error_o, + // Output policy vector for distribution + output top_racl_pkg::racl_policy_vec_t racl_policies_o, + // RACL violation information. + input top_racl_pkg::racl_error_log_t [NumSubscribingIps-1:0] racl_error_i, + // External RACL violation information (from top-level) + input top_racl_pkg::racl_error_log_t [NumExternalSubscribingIps-1:0] racl_error_external_i +); + import top_racl_pkg::*; + + racl_ctrl_reg2hw_t reg2hw; + racl_ctrl_hw2reg_t hw2reg; + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Register Interface + ////////////////////////////////////////////////////////////////////////////////////////////////// + logic reg_intg_error; + logic shadowed_storage_err, shadowed_update_err; + racl_error_log_t racl_ctrl_racl_error; + + // SEC_CM: BUS.INTEGRITY + // SEC_CM: RACL_POLICY.CONFIG.SHADOW + racl_ctrl_reg_top #( + .EnableRacl ( 1'b1 ), + .RaclErrorRsp ( RaclErrorRsp ) + ) u_reg ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .rst_shadowed_ni ( rst_shadowed_ni ), + .tl_i ( tl_i ), + .tl_o ( tl_o ), + .reg2hw ( reg2hw ), + .hw2reg ( hw2reg ), + .shadowed_storage_err_o ( shadowed_storage_err ), + .shadowed_update_err_o ( shadowed_update_err ), + .racl_error_o ( racl_ctrl_racl_error ), + .intg_err_o ( reg_intg_error ) + ); + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Alert Management + ////////////////////////////////////////////////////////////////////////////////////////////////// + logic [NumAlerts-1:0] alert_test, alert; + + assign alert[AlertFatalFaultIdx] = reg_intg_error | shadowed_storage_err; + assign alert[AlertRecovCtrlUpdateErrIdx] = shadowed_update_err; + + assign alert_test[AlertFatalFaultIdx] = reg2hw.alert_test.fatal_fault.q & + reg2hw.alert_test.fatal_fault.qe; + assign alert_test[AlertRecovCtrlUpdateErrIdx] = reg2hw.alert_test.recov_ctrl_update_err.q & + reg2hw.alert_test.recov_ctrl_update_err.qe; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn ( AlertAsyncOn[i] ), + .SkewCycles ( AlertSkewCycles ), + .IsFatal ( i == AlertFatalFaultIdx ) + ) u_prim_alert_sender ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alert[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Policy broadcasting + ////////////////////////////////////////////////////////////////////////////////////////////////// + + racl_policy_t policy_all_rd_wr; + racl_policy_t policy_rot_private; + racl_policy_t policy_soc_rot; + + // Assign register policy values to policy structs + assign policy_all_rd_wr.read_perm = reg2hw.policy_all_rd_wr_shadowed.read_perm.q; + assign policy_all_rd_wr.write_perm = reg2hw.policy_all_rd_wr_shadowed.write_perm.q; + + assign policy_rot_private.read_perm = reg2hw.policy_rot_private_shadowed.read_perm.q; + assign policy_rot_private.write_perm = reg2hw.policy_rot_private_shadowed.write_perm.q; + + assign policy_soc_rot.read_perm = reg2hw.policy_soc_rot_shadowed.read_perm.q; + assign policy_soc_rot.write_perm = reg2hw.policy_soc_rot_shadowed.write_perm.q; + + // Broadcast all policies via policy vector + assign racl_policies_o = { + policy_soc_rot, + policy_rot_private, + policy_all_rd_wr + }; + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Error handling + ////////////////////////////////////////////////////////////////////////////////////////////////// + + // The total number of RACL error sources + localparam int unsigned NumAllIps = NumSubscribingIps + NumExternalSubscribingIps + 1; + + // Concatenate the two incoming RACL error vectors for common handling + racl_error_log_t combined_racl_error[NumAllIps]; + + // Combine the internal and external RACL log to a single valid vector (for assertion) and a + // combined error vector for common handling in the logging logic. + always_comb begin + for (int unsigned i = 0; i < NumSubscribingIps; i++) begin + combined_racl_error[i] = racl_error_i[i]; + end + + for (int unsigned i = NumSubscribingIps; + i < NumSubscribingIps + NumExternalSubscribingIps; i++) begin + combined_racl_error[i] = racl_error_external_i[i - NumSubscribingIps]; + end + + // Last element is the internal RACL error of the own reg_top + combined_racl_error[NumAllIps-1] = racl_ctrl_racl_error; + end + + // Arbitrate between all simultaneously valid error log requests. + racl_error_log_t racl_error_arb; + prim_racl_error_arb #( + .N ( NumAllIps ) + ) u_prim_err_arb ( + .clk_i, + .rst_ni, + .error_log_i ( combined_racl_error ), + .error_log_o ( racl_error_arb ) + ); + + // On the first error, we log the address and other information + logic first_error; + assign first_error = ~reg2hw.error_log.valid.q & racl_error_arb.valid; + + // Writing 1 to the error valid bit clears the log and log address again + logic clear_log; + assign clear_log = reg2hw.error_log.valid.q & reg2hw.error_log.valid.qe; + + assign hw2reg.error_log.valid.d = ~clear_log; + assign hw2reg.error_log.valid.de = racl_error_arb.valid | clear_log; + + // Overflow is raised when error is valid and a new error is coming in or more than one + // error is coming in at the same time + assign hw2reg.error_log.overflow.d = ~clear_log; + assign hw2reg.error_log.overflow.de = (reg2hw.error_log.valid.q & racl_error_arb.valid) | + racl_error_arb.overflow | + clear_log; + + assign hw2reg.error_log.read_access.d = clear_log ? '0 : racl_error_arb.read_access; + assign hw2reg.error_log.read_access.de = first_error | clear_log; + + assign hw2reg.error_log.role.d = clear_log ? '0 : racl_error_arb.racl_role; + assign hw2reg.error_log.role.de = first_error | clear_log; + + assign hw2reg.error_log.ctn_uid.d = clear_log ? '0 : racl_error_arb.ctn_uid; + assign hw2reg.error_log.ctn_uid.de = first_error | clear_log; + + assign hw2reg.error_log_address.d = clear_log ? '0 : racl_error_arb.request_address; + assign hw2reg.error_log_address.de = first_error | clear_log; + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Interrupt handling + ////////////////////////////////////////////////////////////////////////////////////////////////// + + prim_intr_hw #( + .Width ( 1 ), + .IntrT ( "Status" ) + ) u_intr_racl_error ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .event_intr_i ( reg2hw.error_log.valid.q ), + .reg2hw_intr_enable_q_i ( reg2hw.intr_enable.q ), + .reg2hw_intr_test_q_i ( reg2hw.intr_test.q ), + .reg2hw_intr_test_qe_i ( reg2hw.intr_test.qe ), + .reg2hw_intr_state_q_i ( reg2hw.intr_state.q ), + .hw2reg_intr_state_de_o ( hw2reg.intr_state.de ), + .hw2reg_intr_state_d_o ( hw2reg.intr_state.d ), + .intr_o ( intr_racl_error_o ) + ); + + ////////////////////////////////////////////////////////////////////////////////////////////////// + // Assertions + ////////////////////////////////////////////////////////////////////////////////////////////////// + + // All outputs should be known value after reset + `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o) + `ASSERT_KNOWN(RaclErrorIrqKnown_A, intr_racl_error_o) + + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + + `ASSERT_KNOWN(RaclErrorKnown_A, racl_policies_o) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/rtl/racl_ctrl_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/rtl/racl_ctrl_reg_pkg.sv new file mode 100644 index 00000000000..a73f9a96a06 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/rtl/racl_ctrl_reg_pkg.sv @@ -0,0 +1,179 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package racl_ctrl_reg_pkg; + + // Param list + parameter int NumAlerts = 2; + + // Address widths within the block + parameter int BlockAw = 8; + + // Number of registers for every interface + parameter int NumRegs = 9; + + // Alert indices + typedef enum int { + AlertFatalFaultIdx = 0, + AlertRecovCtrlUpdateErrIdx = 1 + } racl_ctrl_alert_idx_t; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic [15:0] q; + } write_perm; + struct packed { + logic [15:0] q; + } read_perm; + } racl_ctrl_reg2hw_policy_all_rd_wr_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + } write_perm; + struct packed { + logic [15:0] q; + } read_perm; + } racl_ctrl_reg2hw_policy_rot_private_shadowed_reg_t; + + typedef struct packed { + struct packed { + logic [15:0] q; + } write_perm; + struct packed { + logic [15:0] q; + } read_perm; + } racl_ctrl_reg2hw_policy_soc_rot_shadowed_reg_t; + + typedef struct packed { + logic q; + } racl_ctrl_reg2hw_intr_state_reg_t; + + typedef struct packed { + logic q; + } racl_ctrl_reg2hw_intr_enable_reg_t; + + typedef struct packed { + logic q; + logic qe; + } racl_ctrl_reg2hw_intr_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } recov_ctrl_update_err; + struct packed { + logic q; + logic qe; + } fatal_fault; + } racl_ctrl_reg2hw_alert_test_reg_t; + + typedef struct packed { + struct packed { + logic q; + logic qe; + } valid; + } racl_ctrl_reg2hw_error_log_reg_t; + + typedef struct packed { + logic d; + logic de; + } racl_ctrl_hw2reg_intr_state_reg_t; + + typedef struct packed { + struct packed { + logic [4:0] d; + logic de; + } ctn_uid; + struct packed { + logic [3:0] d; + logic de; + } role; + struct packed { + logic d; + logic de; + } read_access; + struct packed { + logic d; + logic de; + } overflow; + struct packed { + logic d; + logic de; + } valid; + } racl_ctrl_hw2reg_error_log_reg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } racl_ctrl_hw2reg_error_log_address_reg_t; + + // Register -> HW type + typedef struct packed { + racl_ctrl_reg2hw_policy_all_rd_wr_shadowed_reg_t policy_all_rd_wr_shadowed; // [105:74] + racl_ctrl_reg2hw_policy_rot_private_shadowed_reg_t policy_rot_private_shadowed; // [73:42] + racl_ctrl_reg2hw_policy_soc_rot_shadowed_reg_t policy_soc_rot_shadowed; // [41:10] + racl_ctrl_reg2hw_intr_state_reg_t intr_state; // [9:9] + racl_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [8:8] + racl_ctrl_reg2hw_intr_test_reg_t intr_test; // [7:6] + racl_ctrl_reg2hw_alert_test_reg_t alert_test; // [5:2] + racl_ctrl_reg2hw_error_log_reg_t error_log; // [1:0] + } racl_ctrl_reg2hw_t; + + // HW -> register type + typedef struct packed { + racl_ctrl_hw2reg_intr_state_reg_t intr_state; // [51:50] + racl_ctrl_hw2reg_error_log_reg_t error_log; // [49:33] + racl_ctrl_hw2reg_error_log_address_reg_t error_log_address; // [32:0] + } racl_ctrl_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_OFFSET = 8'h 0; + parameter logic [BlockAw-1:0] RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_OFFSET = 8'h 8; + parameter logic [BlockAw-1:0] RACL_CTRL_POLICY_SOC_ROT_SHADOWED_OFFSET = 8'h 10; + parameter logic [BlockAw-1:0] RACL_CTRL_INTR_STATE_OFFSET = 8'h e8; + parameter logic [BlockAw-1:0] RACL_CTRL_INTR_ENABLE_OFFSET = 8'h ec; + parameter logic [BlockAw-1:0] RACL_CTRL_INTR_TEST_OFFSET = 8'h f0; + parameter logic [BlockAw-1:0] RACL_CTRL_ALERT_TEST_OFFSET = 8'h f4; + parameter logic [BlockAw-1:0] RACL_CTRL_ERROR_LOG_OFFSET = 8'h f8; + parameter logic [BlockAw-1:0] RACL_CTRL_ERROR_LOG_ADDRESS_OFFSET = 8'h fc; + + // Reset values for hwext registers and their fields + parameter logic [0:0] RACL_CTRL_INTR_TEST_RESVAL = 1'h 0; + parameter logic [1:0] RACL_CTRL_ALERT_TEST_RESVAL = 2'h 0; + + // Register index + typedef enum int { + RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED, + RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED, + RACL_CTRL_POLICY_SOC_ROT_SHADOWED, + RACL_CTRL_INTR_STATE, + RACL_CTRL_INTR_ENABLE, + RACL_CTRL_INTR_TEST, + RACL_CTRL_ALERT_TEST, + RACL_CTRL_ERROR_LOG, + RACL_CTRL_ERROR_LOG_ADDRESS + } racl_ctrl_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] RACL_CTRL_PERMIT [9] = '{ + 4'b 1111, // index[0] RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED + 4'b 1111, // index[1] RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED + 4'b 1111, // index[2] RACL_CTRL_POLICY_SOC_ROT_SHADOWED + 4'b 0001, // index[3] RACL_CTRL_INTR_STATE + 4'b 0001, // index[4] RACL_CTRL_INTR_ENABLE + 4'b 0001, // index[5] RACL_CTRL_INTR_TEST + 4'b 0001, // index[6] RACL_CTRL_ALERT_TEST + 4'b 0011, // index[7] RACL_CTRL_ERROR_LOG + 4'b 1111 // index[8] RACL_CTRL_ERROR_LOG_ADDRESS + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/rtl/racl_ctrl_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/rtl/racl_ctrl_reg_top.sv new file mode 100644 index 00000000000..59e17fcb92b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/racl_ctrl/rtl/racl_ctrl_reg_top.sv @@ -0,0 +1,948 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module racl_ctrl_reg_top + # ( + parameter bit EnableRacl = 1'b0, + parameter bit RaclErrorRsp = 1'b1 + ) ( + input clk_i, + input rst_ni, + input rst_shadowed_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output racl_ctrl_reg_pkg::racl_ctrl_reg2hw_t reg2hw, // Write + input racl_ctrl_reg_pkg::racl_ctrl_hw2reg_t hw2reg, // Read + + output logic shadowed_storage_err_o, + output logic shadowed_update_err_o, + + // RACL interface + output top_racl_pkg::racl_error_log_t racl_error_o, + + // Integrity check errors + output logic intg_err_o +); + + import racl_ctrl_reg_pkg::* ; + + localparam int AW = 8; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [8:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(9) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + // Translate RACL error to TLUL error if enabled + .error_i (reg_error | (RaclErrorRsp & racl_error_o.valid)) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic policy_all_rd_wr_shadowed_re; + logic policy_all_rd_wr_shadowed_we; + logic [15:0] policy_all_rd_wr_shadowed_read_perm_qs; + logic [15:0] policy_all_rd_wr_shadowed_read_perm_wd; + logic policy_all_rd_wr_shadowed_read_perm_storage_err; + logic policy_all_rd_wr_shadowed_read_perm_update_err; + logic [15:0] policy_all_rd_wr_shadowed_write_perm_qs; + logic [15:0] policy_all_rd_wr_shadowed_write_perm_wd; + logic policy_all_rd_wr_shadowed_write_perm_storage_err; + logic policy_all_rd_wr_shadowed_write_perm_update_err; + logic policy_rot_private_shadowed_re; + logic policy_rot_private_shadowed_we; + logic [15:0] policy_rot_private_shadowed_read_perm_qs; + logic [15:0] policy_rot_private_shadowed_read_perm_wd; + logic policy_rot_private_shadowed_read_perm_storage_err; + logic policy_rot_private_shadowed_read_perm_update_err; + logic [15:0] policy_rot_private_shadowed_write_perm_qs; + logic [15:0] policy_rot_private_shadowed_write_perm_wd; + logic policy_rot_private_shadowed_write_perm_storage_err; + logic policy_rot_private_shadowed_write_perm_update_err; + logic policy_soc_rot_shadowed_re; + logic policy_soc_rot_shadowed_we; + logic [15:0] policy_soc_rot_shadowed_read_perm_qs; + logic [15:0] policy_soc_rot_shadowed_read_perm_wd; + logic policy_soc_rot_shadowed_read_perm_storage_err; + logic policy_soc_rot_shadowed_read_perm_update_err; + logic [15:0] policy_soc_rot_shadowed_write_perm_qs; + logic [15:0] policy_soc_rot_shadowed_write_perm_wd; + logic policy_soc_rot_shadowed_write_perm_storage_err; + logic policy_soc_rot_shadowed_write_perm_update_err; + logic intr_state_qs; + logic intr_enable_we; + logic intr_enable_qs; + logic intr_enable_wd; + logic intr_test_we; + logic intr_test_wd; + logic alert_test_we; + logic alert_test_fatal_fault_wd; + logic alert_test_recov_ctrl_update_err_wd; + logic error_log_we; + logic error_log_valid_qs; + logic error_log_valid_wd; + logic error_log_overflow_qs; + logic error_log_read_access_qs; + logic [3:0] error_log_role_qs; + logic [4:0] error_log_ctn_uid_qs; + logic [31:0] error_log_address_qs; + + // Register instances + // R[policy_all_rd_wr_shadowed]: V(False) + // F[read_perm]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h7), + .Mubi (1'b0) + ) u_policy_all_rd_wr_shadowed_read_perm ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (policy_all_rd_wr_shadowed_re), + .we (policy_all_rd_wr_shadowed_we), + .wd (policy_all_rd_wr_shadowed_read_perm_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.policy_all_rd_wr_shadowed.read_perm.q), + .ds (), + + // to register interface (read) + .qs (policy_all_rd_wr_shadowed_read_perm_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (policy_all_rd_wr_shadowed_read_perm_update_err), + .err_storage (policy_all_rd_wr_shadowed_read_perm_storage_err) + ); + + // F[write_perm]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h7), + .Mubi (1'b0) + ) u_policy_all_rd_wr_shadowed_write_perm ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (policy_all_rd_wr_shadowed_re), + .we (policy_all_rd_wr_shadowed_we), + .wd (policy_all_rd_wr_shadowed_write_perm_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.policy_all_rd_wr_shadowed.write_perm.q), + .ds (), + + // to register interface (read) + .qs (policy_all_rd_wr_shadowed_write_perm_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (policy_all_rd_wr_shadowed_write_perm_update_err), + .err_storage (policy_all_rd_wr_shadowed_write_perm_storage_err) + ); + + + // R[policy_rot_private_shadowed]: V(False) + // F[read_perm]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h1), + .Mubi (1'b0) + ) u_policy_rot_private_shadowed_read_perm ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (policy_rot_private_shadowed_re), + .we (policy_rot_private_shadowed_we), + .wd (policy_rot_private_shadowed_read_perm_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.policy_rot_private_shadowed.read_perm.q), + .ds (), + + // to register interface (read) + .qs (policy_rot_private_shadowed_read_perm_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (policy_rot_private_shadowed_read_perm_update_err), + .err_storage (policy_rot_private_shadowed_read_perm_storage_err) + ); + + // F[write_perm]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h1), + .Mubi (1'b0) + ) u_policy_rot_private_shadowed_write_perm ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (policy_rot_private_shadowed_re), + .we (policy_rot_private_shadowed_we), + .wd (policy_rot_private_shadowed_write_perm_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.policy_rot_private_shadowed.write_perm.q), + .ds (), + + // to register interface (read) + .qs (policy_rot_private_shadowed_write_perm_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (policy_rot_private_shadowed_write_perm_update_err), + .err_storage (policy_rot_private_shadowed_write_perm_storage_err) + ); + + + // R[policy_soc_rot_shadowed]: V(False) + // F[read_perm]: 15:0 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h5), + .Mubi (1'b0) + ) u_policy_soc_rot_shadowed_read_perm ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (policy_soc_rot_shadowed_re), + .we (policy_soc_rot_shadowed_we), + .wd (policy_soc_rot_shadowed_read_perm_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.policy_soc_rot_shadowed.read_perm.q), + .ds (), + + // to register interface (read) + .qs (policy_soc_rot_shadowed_read_perm_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (policy_soc_rot_shadowed_read_perm_update_err), + .err_storage (policy_soc_rot_shadowed_read_perm_storage_err) + ); + + // F[write_perm]: 31:16 + prim_subreg_shadow #( + .DW (16), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (16'h5), + .Mubi (1'b0) + ) u_policy_soc_rot_shadowed_write_perm ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .rst_shadowed_ni (rst_shadowed_ni), + + // from register interface + .re (policy_soc_rot_shadowed_re), + .we (policy_soc_rot_shadowed_we), + .wd (policy_soc_rot_shadowed_write_perm_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.policy_soc_rot_shadowed.write_perm.q), + .ds (), + + // to register interface (read) + .qs (policy_soc_rot_shadowed_write_perm_qs), + + // Shadow register phase. Relevant for hwext only. + .phase (), + + // Shadow register error conditions + .err_update (policy_soc_rot_shadowed_write_perm_update_err), + .err_storage (policy_soc_rot_shadowed_write_perm_storage_err) + ); + + + // R[intr_state]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_state ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.intr_state.de), + .d (hw2reg.intr_state.d), + + // to internal hardware + .qe (), + .q (reg2hw.intr_state.q), + .ds (), + + // to register interface (read) + .qs (intr_state_qs) + ); + + + // R[intr_enable]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_intr_enable ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (intr_enable_we), + .wd (intr_enable_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.intr_enable.q), + .ds (), + + // to register interface (read) + .qs (intr_enable_qs) + ); + + + // R[intr_test]: V(True) + logic intr_test_qe; + logic [0:0] intr_test_flds_we; + assign intr_test_qe = &intr_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_intr_test ( + .re (1'b0), + .we (intr_test_we), + .wd (intr_test_wd), + .d ('0), + .qre (), + .qe (intr_test_flds_we[0]), + .q (reg2hw.intr_test.q), + .ds (), + .qs () + ); + assign reg2hw.intr_test.qe = intr_test_qe; + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [1:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[fatal_fault]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.fatal_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe; + + // F[recov_ctrl_update_err]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_recov_ctrl_update_err ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_recov_ctrl_update_err_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.recov_ctrl_update_err.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.recov_ctrl_update_err.qe = alert_test_qe; + + + // R[error_log]: V(False) + logic error_log_qe; + logic [4:0] error_log_flds_we; + prim_flop #( + .Width(1), + .ResetValue(0) + ) u_error_log0_qe ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(&(error_log_flds_we | 5'h1e)), + .q_o(error_log_qe) + ); + // F[valid]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_error_log_valid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (error_log_we), + .wd (error_log_valid_wd), + + // from internal hardware + .de (hw2reg.error_log.valid.de), + .d (hw2reg.error_log.valid.d), + + // to internal hardware + .qe (error_log_flds_we[0]), + .q (reg2hw.error_log.valid.q), + .ds (), + + // to register interface (read) + .qs (error_log_valid_qs) + ); + assign reg2hw.error_log.valid.qe = error_log_qe; + + // F[overflow]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_error_log_overflow ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.error_log.overflow.de), + .d (hw2reg.error_log.overflow.d), + + // to internal hardware + .qe (error_log_flds_we[1]), + .q (), + .ds (), + + // to register interface (read) + .qs (error_log_overflow_qs) + ); + + // F[read_access]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_error_log_read_access ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.error_log.read_access.de), + .d (hw2reg.error_log.read_access.d), + + // to internal hardware + .qe (error_log_flds_we[2]), + .q (), + .ds (), + + // to register interface (read) + .qs (error_log_read_access_qs) + ); + + // F[role]: 6:3 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_error_log_role ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.error_log.role.de), + .d (hw2reg.error_log.role.d), + + // to internal hardware + .qe (error_log_flds_we[3]), + .q (), + .ds (), + + // to register interface (read) + .qs (error_log_role_qs) + ); + + // F[ctn_uid]: 11:7 + prim_subreg #( + .DW (5), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (5'h0), + .Mubi (1'b0) + ) u_error_log_ctn_uid ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.error_log.ctn_uid.de), + .d (hw2reg.error_log.ctn_uid.d), + + // to internal hardware + .qe (error_log_flds_we[4]), + .q (), + .ds (), + + // to register interface (read) + .qs (error_log_ctn_uid_qs) + ); + + + // R[error_log_address]: V(False) + prim_subreg #( + .DW (32), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (32'h0), + .Mubi (1'b0) + ) u_error_log_address ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.error_log_address.de), + .d (hw2reg.error_log_address.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (error_log_address_qs) + ); + + + + logic [8:0] addr_hit; + top_racl_pkg::racl_role_vec_t racl_role_vec; + top_racl_pkg::racl_role_t racl_role; + + logic [8:0] racl_addr_hit_read; + logic [8:0] racl_addr_hit_write; + + if (EnableRacl) begin : gen_racl_role_logic + // Retrieve RACL role from user bits and one-hot encode that for the comparison bitmap + assign racl_role = top_racl_pkg::tlul_extract_racl_role_bits(tl_i.a_user.rsvd); + + prim_onehot_enc #( + .OneHotWidth( $bits(top_racl_pkg::racl_role_vec_t) ) + ) u_racl_role_encode ( + .in_i ( racl_role ), + .en_i ( 1'b1 ), + .out_o( racl_role_vec ) + ); + // For the static RACL assignment for racl_ctrl only one role (ROT_PRIVATE) is used, + // leaving others unread. Intentionally read them to avoid linting errors. + logic unused_role_vec; + assign unused_role_vec = ^racl_role_vec; + end else begin : gen_no_racl_role_logic + assign racl_role = '0; + assign racl_role_vec = '0; + end + + always_comb begin + racl_addr_hit_read = '0; + racl_addr_hit_write = '0; + addr_hit[0] = (reg_addr == RACL_CTRL_POLICY_ALL_RD_WR_SHADOWED_OFFSET); + addr_hit[1] = (reg_addr == RACL_CTRL_POLICY_ROT_PRIVATE_SHADOWED_OFFSET); + addr_hit[2] = (reg_addr == RACL_CTRL_POLICY_SOC_ROT_SHADOWED_OFFSET); + addr_hit[3] = (reg_addr == RACL_CTRL_INTR_STATE_OFFSET); + addr_hit[4] = (reg_addr == RACL_CTRL_INTR_ENABLE_OFFSET); + addr_hit[5] = (reg_addr == RACL_CTRL_INTR_TEST_OFFSET); + addr_hit[6] = (reg_addr == RACL_CTRL_ALERT_TEST_OFFSET); + addr_hit[7] = (reg_addr == RACL_CTRL_ERROR_LOG_OFFSET); + addr_hit[8] = (reg_addr == RACL_CTRL_ERROR_LOG_ADDRESS_OFFSET); + + if (EnableRacl) begin : gen_racl_hit + for (int unsigned slice_idx = 0; slice_idx < 9; slice_idx++) begin + // Static RACL protection with ROT_PRIVATE policy + racl_addr_hit_read[slice_idx] = + addr_hit[slice_idx] & (|(top_racl_pkg::RACL_POLICY_ROT_PRIVATE_RD & racl_role_vec)); + racl_addr_hit_write[slice_idx] = + addr_hit[slice_idx] & (|(top_racl_pkg::RACL_POLICY_ROT_PRIVATE_WR & racl_role_vec)); + end + end else begin : gen_no_racl + racl_addr_hit_read = addr_hit; + racl_addr_hit_write = addr_hit; + end + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + // A valid address hit, access, but failed the RACL check + assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) | + (reg_we & ~|racl_addr_hit_write)); + assign racl_error_o.request_address = top_pkg::TL_AW'(reg_addr); + assign racl_error_o.racl_role = racl_role; + assign racl_error_o.overflow = 1'b0; + + if (EnableRacl) begin : gen_racl_log + assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd); + assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get; + end else begin : gen_no_racl_log + assign racl_error_o.ctn_uid = '0; + assign racl_error_o.read_access = 1'b0; + end + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((racl_addr_hit_write[0] & (|(RACL_CTRL_PERMIT[0] & ~reg_be))) | + (racl_addr_hit_write[1] & (|(RACL_CTRL_PERMIT[1] & ~reg_be))) | + (racl_addr_hit_write[2] & (|(RACL_CTRL_PERMIT[2] & ~reg_be))) | + (racl_addr_hit_write[3] & (|(RACL_CTRL_PERMIT[3] & ~reg_be))) | + (racl_addr_hit_write[4] & (|(RACL_CTRL_PERMIT[4] & ~reg_be))) | + (racl_addr_hit_write[5] & (|(RACL_CTRL_PERMIT[5] & ~reg_be))) | + (racl_addr_hit_write[6] & (|(RACL_CTRL_PERMIT[6] & ~reg_be))) | + (racl_addr_hit_write[7] & (|(RACL_CTRL_PERMIT[7] & ~reg_be))) | + (racl_addr_hit_write[8] & (|(RACL_CTRL_PERMIT[8] & ~reg_be))))); + end + + // Generate write-enables + assign policy_all_rd_wr_shadowed_re = racl_addr_hit_read[0] & reg_re & !reg_error; + assign policy_all_rd_wr_shadowed_we = racl_addr_hit_write[0] & reg_we & !reg_error; + + assign policy_all_rd_wr_shadowed_read_perm_wd = reg_wdata[15:0]; + + assign policy_all_rd_wr_shadowed_write_perm_wd = reg_wdata[31:16]; + assign policy_rot_private_shadowed_re = racl_addr_hit_read[1] & reg_re & !reg_error; + assign policy_rot_private_shadowed_we = racl_addr_hit_write[1] & reg_we & !reg_error; + + assign policy_rot_private_shadowed_read_perm_wd = reg_wdata[15:0]; + + assign policy_rot_private_shadowed_write_perm_wd = reg_wdata[31:16]; + assign policy_soc_rot_shadowed_re = racl_addr_hit_read[2] & reg_re & !reg_error; + assign policy_soc_rot_shadowed_we = racl_addr_hit_write[2] & reg_we & !reg_error; + + assign policy_soc_rot_shadowed_read_perm_wd = reg_wdata[15:0]; + + assign policy_soc_rot_shadowed_write_perm_wd = reg_wdata[31:16]; + assign intr_enable_we = racl_addr_hit_write[4] & reg_we & !reg_error; + + assign intr_enable_wd = reg_wdata[0]; + assign intr_test_we = racl_addr_hit_write[5] & reg_we & !reg_error; + + assign intr_test_wd = reg_wdata[0]; + assign alert_test_we = racl_addr_hit_write[6] & reg_we & !reg_error; + + assign alert_test_fatal_fault_wd = reg_wdata[0]; + + assign alert_test_recov_ctrl_update_err_wd = reg_wdata[1]; + assign error_log_we = racl_addr_hit_write[7] & reg_we & !reg_error; + + assign error_log_valid_wd = reg_wdata[0]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = policy_all_rd_wr_shadowed_we; + reg_we_check[1] = policy_rot_private_shadowed_we; + reg_we_check[2] = policy_soc_rot_shadowed_we; + reg_we_check[3] = 1'b0; + reg_we_check[4] = intr_enable_we; + reg_we_check[5] = intr_test_we; + reg_we_check[6] = alert_test_we; + reg_we_check[7] = error_log_we; + reg_we_check[8] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + racl_addr_hit_read[0]: begin + reg_rdata_next[15:0] = policy_all_rd_wr_shadowed_read_perm_qs; + reg_rdata_next[31:16] = policy_all_rd_wr_shadowed_write_perm_qs; + end + + racl_addr_hit_read[1]: begin + reg_rdata_next[15:0] = policy_rot_private_shadowed_read_perm_qs; + reg_rdata_next[31:16] = policy_rot_private_shadowed_write_perm_qs; + end + + racl_addr_hit_read[2]: begin + reg_rdata_next[15:0] = policy_soc_rot_shadowed_read_perm_qs; + reg_rdata_next[31:16] = policy_soc_rot_shadowed_write_perm_qs; + end + + racl_addr_hit_read[3]: begin + reg_rdata_next[0] = intr_state_qs; + end + + racl_addr_hit_read[4]: begin + reg_rdata_next[0] = intr_enable_qs; + end + + racl_addr_hit_read[5]: begin + reg_rdata_next[0] = '0; + end + + racl_addr_hit_read[6]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + racl_addr_hit_read[7]: begin + reg_rdata_next[0] = error_log_valid_qs; + reg_rdata_next[1] = error_log_overflow_qs; + reg_rdata_next[2] = error_log_read_access_qs; + reg_rdata_next[6:3] = error_log_role_qs; + reg_rdata_next[11:7] = error_log_ctn_uid_qs; + end + + racl_addr_hit_read[8]: begin + reg_rdata_next[31:0] = error_log_address_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + logic rst_done; + logic shadow_rst_done; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + rst_done <= '0; + end else begin + rst_done <= 1'b1; + end + end + + always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin + if (!rst_shadowed_ni) begin + shadow_rst_done <= '0; + end else begin + shadow_rst_done <= 1'b1; + end + end + + // both shadow and normal resets have been released + assign shadow_busy = ~(rst_done & shadow_rst_done); + + // Collect up storage and update errors + assign shadowed_storage_err_o = |{ + policy_all_rd_wr_shadowed_read_perm_storage_err, + policy_all_rd_wr_shadowed_write_perm_storage_err, + policy_rot_private_shadowed_read_perm_storage_err, + policy_rot_private_shadowed_write_perm_storage_err, + policy_soc_rot_shadowed_read_perm_storage_err, + policy_soc_rot_shadowed_write_perm_storage_err + }; + assign shadowed_update_err_o = |{ + policy_all_rd_wr_shadowed_read_perm_update_err, + policy_all_rd_wr_shadowed_write_perm_update_err, + policy_rot_private_shadowed_read_perm_update_err, + policy_rot_private_shadowed_write_perm_update_err, + policy_soc_rot_shadowed_read_perm_update_err, + policy_soc_rot_shadowed_write_perm_update_err + }; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/BUILD new file mode 100644 index 00000000000..d5c7e48c2c4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/BUILD @@ -0,0 +1,25 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.svg", + ]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/README.md new file mode 100644 index 00000000000..8c7f150fd35 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/README.md @@ -0,0 +1,29 @@ +# Reset Manager HWIP Technical Specification + +[`rstmgr`](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/rstmgr/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr/code.svg) + +[`rstmgr_cnsty_chk`](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/latest/report.html): +![](https://dashboards.lowrisc.org/badges/dv/rstmgr_cnsty_chk/test.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr_cnsty_chk/passing.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr_cnsty_chk/functional.svg) +![](https://dashboards.lowrisc.org/badges/dv/rstmgr_cnsty_chk/code.svg) + +# Overview + +This document describes the functionality of the reset controller and its interaction with the rest of the OpenTitan system. + +## Features + +* Stretch incoming POR. +* Cascaded system resets. +* Peripheral system reset requests. +* RISC-V non-debug-module reset support. +* Limited and selective software controlled module reset. +* Always-on reset information register. +* Always-on alert crash dump register. +* Always-on CPU crash dump register. +* Reset consistency checks. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/BUILD new file mode 100644 index 00000000000..2a30e314ade --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/BUILD @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_rstmgr.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = glob([ + "rstmgr.hjson", + "*_testplan.hjson", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr.cfg.example.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr.cfg.example.hjson new file mode 100644 index 00000000000..028899301a0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr.cfg.example.hjson @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Example configuration +{ + // Reset attributes + // name: name of reset. + // + // gen: whether the reset is generated + // 1: it is a generated reset inside rstmgr + // 0: it is a hardwired design reset inside rstmgr (roots and por) + // + // type: the reset type [ext, top] + // ext: the reset is coming in from the ports, external to earlgrey + // int: the reset is only used inside rstmgr + // top: the reset is output from rstmgr to top level struct + // + // root: The parent reset + // If type is "ext", there is no root, since it is external + // + // domain: The power domain + // If no domain, it means there is no choice, just inherits from root. + // Otherwise, selects the domain to which it is related + // 0 is defaulted for always on. + // TBD: This should eventually be changed to a name->index project wide lookup + // + // clk: related clock domain for synchronous release + // If type is "por", there is not related clock, since it is + // likely external or generated from a voltage comparator + // + resets: [ + { name: "rst_ni", gen: 0, type: "ext" } + { name: "por_aon", gen: 0, type: "top", root: "rst_ni", clk: "aon" } + { name: "lc_src", gen: 0, type: "int", root: "por", clk: "io_div2" } + { name: "sys_src", gen: 0, type: "int", root: "por", clk: "io_div2" } + { name: "por", gen: 1, type: "top", root: "por_aon", clk: "main" } + { name: "por_io", gen: 1, type: "top", root: "por_aon", clk: "io" } + { name: "por_io_div2", gen: 1, type: "top", root: "por_aon", clk: "io_div2" } + { name: "por_usb", gen: 1, type: "top", root: "por_aon", clk: "usb" } + { name: "lc", gen: 1, type: "top", domain: "0", root: "lc_src", clk: "io_div2" } + { name: "sys", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "main" } + { name: "sys_io", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2" } + { name: "sys_aon", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "aon" } + { name: "spi_device", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "io_div2", sw: 1 } + { name: "usb", gen: 1, type: "top", domain: "0", root: "sys_src", clk: "usb", sw: 1 } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr.hjson new file mode 100644 index 00000000000..e952fc19072 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr.hjson @@ -0,0 +1,604 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + + +# RSTMGR register template +# +{ + name: "rstmgr", + human_name: "Reset Manager", + one_line_desc: "Controls the on-chip reset signals, records reset cause and CPU crash dump for software", + one_paragraph_desc: ''' + Reset Manager controls the on-chip reset. + It receives one root power-on reset signal for each power domain from AST and feeds one reset signal for each on-chip reset domain to the OpenTitan hardware blocks. + Resets can be requested by Power Manager, which internally arbitrates peripheral resets, e.g., from AON Timer and Alert Handler, RISC-V Debug Module, and to a limited extent by software. + Through always-on registers, software can get information on the reset cause, as well as alert and CPU status prior to a triggered reset (crash dump). + To deter fault injection (FI) attacks, several countermeasures are implemented, including consistency checks of leaf resets and support for shadow resets. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "22", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_rstmgr", + revisions: [ + { + version: "1.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2S", + dif_stage: "S2", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + {clock: "clk_aon_i"}, + {clock: "clk_io_div4_i"}, + {clock: "clk_main_i"}, + {clock: "clk_io_i"}, + {clock: "clk_io_div2_i"}, + {clock: "clk_por_i", reset: "rst_por_ni"}, + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal structural fault is detected. + Structural faults include errors such as sparse fsm errors and tlul integrity errors. + ''' + } + { name: "fatal_cnsty_fault", + desc: ''' + This fatal alert is triggered when a reset consistency fault is detected. + It is separated from the category above for clearer error collection and debug. + ''' + } + ], + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + { name: "SCAN.INTERSIG.MUBI", + desc: "scan control signals are multibit" + } + { name: "LEAF.RST.BKGN_CHK", + desc: "Background consistency checks for each leaf reset." + } + { name: "LEAF.RST.SHADOW", + desc: "Leaf resets to blocks containing shadow registers are shadowed" + } + { name: "LEAF.FSM.SPARSE", + desc: "Sparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets" + } + { name: "SW_RST.CONFIG.REGWEN", + desc: "Software reset controls are protected by regwen" + } + { name: "DUMP_CTRL.CONFIG.REGWEN", + desc: "Crash dump controls are protected by regwen" + } + ] + regwidth: "32", + scan: "true", + scan_reset: "true", + param_list: [ + { name: "RdWidth", + desc: "Read width for crash info", + type: "int", + default: "32", + local: "true" + }, + + { name: "IdxWidth", + desc: "Index width for crash info", + type: "int", + default: "4", + local: "true" + }, + + { name: "NumHwResets", + desc: "Number of hardware reset requests, inclusive of debug resets and pwrmgr's internal resets ", + type: "int", + default: "4", + local: "true" + }, + + { name: "NumSwResets", + desc: "Number of software resets", + type: "int", + default: "3", + local: "true" + }, + + { name: "NumTotalResets", + desc: "Number of total reset requests, inclusive of hw/sw, por and low power exit", + type: "int", + default: "7", + local: "true" + }, + + { name: "SecCheck", + type: "bit", + default: "1'b1", + desc: ''' + When 1, enable rstmgr reset consistency checks. + When 0, there are no consistency checks. + ''' + local: "false", + expose: "true" + }, + + { name: "SecMaxSyncDelay", + type: "int", + default: "2", + desc: ''' + The maximum synchronization delay for parent / child reset checks. + ''' + local: "false", + expose: "true" + }, + ], + features: [ + { name: "RSTMGR.SW_RST.CHIP_RESET", + desc: "Cause a reset of all but some AON and system debug blocks via CSR." + } + { name: "RSTMGR.SW_RST.SPI_DEVICE_REQUEST", + desc: "Trigger reset of SPI_DEVICE peripheral via CSR." + } + { name: "RSTMGR.SW_RST.SPI_DEVICE_ENABLE", + desc: "Enable reset of SPI_DEVICE peripheral via CSR." + } + { name: "RSTMGR.SW_RST.SPI_HOST0_REQUEST", + desc: "Trigger reset of SPI_HOST0 peripheral via CSR." + } + { name: "RSTMGR.SW_RST.SPI_HOST0_ENABLE", + desc: "Enable reset of SPI_HOST0 peripheral via CSR." + } + { name: "RSTMGR.SW_RST.I2C0_REQUEST", + desc: "Trigger reset of I2C0 peripheral via CSR." + } + { name: "RSTMGR.SW_RST.I2C0_ENABLE", + desc: "Enable reset of I2C0 peripheral via CSR." + } + { name: "RSTMGR.RESET_INFO.CAPTURE", + desc: "Capture information about the causes of a reset." + } + { name: "RSTMGR.RESET_INFO.CLEAR", + desc: "Clear information about the causes of a reset." + } + { name: "RSTMGR.ALERT_INFO.CAPTURE", + desc: "Capture alert crash dump information upon reset." + } + { name: "RSTMGR.ALERT_INFO.ENABLE", + desc: "Enable capture of alert crash dump information." + } + { name: "RSTMGR.CPU_INFO.CAPTURE", + desc: "Capture cpu crash dump information upon reset." + } + { name: "RSTMGR.CPU_INFO.ENABLE", + desc: "Enable capture of cpu crash dump information." + } + { name: "RSTMGR.ALERT_HANDLER.RESET_STATUS", + desc: "Inform alert handler about reset enable status for each reset." + } + ] + // Define rstmgr struct package + inter_signal_list: [ + { struct: "logic", + type: "uni", + name: "por_n", + act: "rcv", + width: "2" + desc: ''' + Root power on reset signals from ast. + There is one root reset signal for each core power domain. + ''' + }, + + { struct: "pwr_rst", // pwr_rst_req_t, pwr_rst_rsp_t + type: "req_rsp", + name: "pwr", // resets_o (req), resets_i (rsp) + act: "rsp", + desc: ''' + Reset request signals from power manager. + Power manager can request for specific domains of the lc/sys reset tree to assert. + ''' + }, + + { struct: "rstmgr_out", + type: "uni", + name: "resets", + act: "req", + package: "rstmgr_pkg", // Origin package (only needs for the req) + desc: ''' + Leaf resets fed to the system. + ''' + }, + + { struct: "rstmgr_rst_en", + type: "uni", + name: "rst_en", + act: "req", + package: "rstmgr_pkg", // Origin package (only needs for the req) + desc: ''' + Low-power-group outputs used by alert handler. + ''' + }, + + { struct: "alert_crashdump", + type: "uni", + name: "alert_dump", + act: "rcv", + package: "alert_handler_pkg", + desc: ''' + Alert handler crash dump information. + ''' + }, + + { struct: "cpu_crash_dump", + type: "uni", + name: "cpu_dump", + act: "rcv", + package: "rv_core_ibex_pkg", + desc: ''' + Main processing element crash dump information. + ''' + }, + + { struct: "mubi4", + type: "uni", + name: "sw_rst_req", + act: "req", + package: "prim_mubi_pkg", + desc: ''' + Software requested system reset to pwrmgr. + ''' + }, + + // Exported resets + ], + + registers: [ + + { name: "RESET_REQ", + desc: ''' + Software requested system reset. + ''', + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { bits: "3:0", + mubi: true + name: "VAL", + desc: ''' + When set to kMultiBitBool4True, a reset to power manager is requested. + Upon completion of reset, this bit is automatically cleared by hardware. + ''' + resval: false + }, + ], + tags: [// This register will cause a system reset, directed test only + "excl:CsrAllTests:CsrExclWrite"] + }, + + { name: "RESET_INFO", + desc: ''' + Device reset reason. + ''', + swaccess: "rw1c", + hwaccess: "hwo", + sync: "clk_por_i", + fields: [ + { bits: "0", + hwaccess: "none", + name: "POR", + desc: ''' + Indicates when a device has reset due to power up. + ''' + resval: "1" + }, + + { bits: "1", + name: "LOW_POWER_EXIT", + desc: ''' + Indicates when a device has reset due low power exit. + ''' + resval: "0" + }, + + { bits: "2", + hwaccess: "hrw", + name: "SW_RESET", + desc: ''' + Indicates when a device has reset due to !!RESET_REQ. + ''' + resval: "0" + }, + + // reset requests include escalation reset, main power glitch, + // ndm reset request + other peripheral requests + { bits: "6:3", + hwaccess: "hrw", + name: "HW_REQ", + desc: ''' + Indicates when a device has reset due to a hardware requested reset. + The bit mapping is as follows: + b3: aon_timer_aon: Watchdog reset request. + b4: soc_proxy: External reset request + b5: pwrmgr_aon: main power glitch reset request + b6: alert_handler: escalation reset request + ''' + resval: "0" + }, + ] + }, + + { name: "ALERT_REGWEN", + desc: "Alert write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, !!ALERT_INFO_CTRL can be modified. + ''' + }, + ] + } + + { name: "ALERT_INFO_CTRL", + desc: ''' + Alert info dump controls. + ''', + swaccess: "rw", + hwaccess: "hro", + sync: "clk_por_i", + regwen: "ALERT_REGWEN", + fields: [ + { bits: "0", + name: "EN", + hwaccess: "hrw", + desc: ''' + Enable alert dump to capture new information. + This field is automatically set to 0 upon system reset (even if rstmgr is not reset). + ''' + resval: "0" + }, + + { bits: "4+IdxWidth-1:4", + name: "INDEX", + desc: ''' + Controls which 32-bit value to read. + ''' + resval: "0" + }, + ] + }, + + { name: "ALERT_INFO_ATTR", + desc: ''' + Alert info dump attributes. + ''', + swaccess: "ro", + hwaccess: "hwo", + sync: "clk_por_i", + hwext: "true", + fields: [ + { bits: "IdxWidth-1:0", + name: "CNT_AVAIL", + swaccess: "ro", + hwaccess: "hwo", + desc: ''' + The number of 32-bit values contained in the alert info dump. + ''' + resval: "0", + tags: [// This field is tied to a design constant, thus the + // default value is never 0. Since there is not a way + // to express this behavior at the moment, exclude from automated checks. + "excl:CsrAllTests:CsrExclCheck"] + }, + ] + }, + + { name: "ALERT_INFO", + desc: ''' + Alert dump information prior to last reset. + Which value read is controlled by the !!ALERT_INFO_CTRL register. + ''', + swaccess: "ro", + hwaccess: "hwo", + sync: "clk_por_i", + hwext: "true", + fields: [ + { bits: "31:0", + name: "VALUE", + desc: ''' + The current 32-bit value of crash dump. + ''' + resval: "0", + }, + ] + }, + { name: "CPU_REGWEN", + desc: "Cpu write enable", + swaccess: "rw0c", + hwaccess: "none", + fields: [ + { bits: "0", + name: "EN", + resval: "1" + desc: ''' + When 1, !!CPU_INFO_CTRL can be modified. + ''' + }, + ] + } + + { name: "CPU_INFO_CTRL", + desc: ''' + Cpu info dump controls. + ''', + swaccess: "rw", + hwaccess: "hro", + sync: "clk_por_i", + regwen: "CPU_REGWEN", + fields: [ + { bits: "0", + name: "EN", + hwaccess: "hrw", + desc: ''' + Enable cpu dump to capture new information. + This field is automatically set to 0 upon system reset (even if rstmgr is not reset). + ''' + resval: "0" + }, + + { bits: "4+IdxWidth-1:4", + name: "INDEX", + desc: ''' + Controls which 32-bit value to read. + ''' + resval: "0" + }, + ] + }, + + { name: "CPU_INFO_ATTR", + desc: ''' + Cpu info dump attributes. + ''', + swaccess: "ro", + hwaccess: "hwo", + sync: "clk_por_i", + hwext: "true", + fields: [ + { bits: "IdxWidth-1:0", + name: "CNT_AVAIL", + swaccess: "ro", + hwaccess: "hwo", + desc: ''' + The number of 32-bit values contained in the cpu info dump. + ''' + resval: "0", + tags: [// This field is tied to a design constant, thus the + // default value is never 0. Since there is not a way + // to express this behavior at the moment, exclude from automated checks. + "excl:CsrAllTests:CsrExclCheck"] + }, + ] + }, + + { name: "CPU_INFO", + desc: ''' + Cpu dump information prior to last reset. + Which value read is controlled by the !!CPU_INFO_CTRL register. + ''', + swaccess: "ro", + hwaccess: "hwo", + sync: "clk_por_i", + hwext: "true", + fields: [ + { bits: "31:0", + name: "VALUE", + desc: ''' + The current 32-bit value of crash dump. + ''' + resval: "0", + }, + ] + }, + + + # Templated registers for software control + + { multireg: { + cname: "RSTMGR_SW_RST", + name: "SW_RST_REGWEN", + desc: ''' + Register write enable for software controllable resets. + When a particular bit value is 0, the corresponding value in !!SW_RST_CTRL_N can no longer be changed. + When a particular bit value is 1, the corresponding value in !!SW_RST_CTRL_N can be changed. + ''', + count: "NumSwResets", + swaccess: "rw0c", + hwaccess: "none", + compact: false, + fields: [ + { + bits: "0", + name: "EN", + desc: "Register write enable for software controllable resets", + resval: "1", + }, + ], + } + } + + { multireg: { + cname: "RSTMGR_SW_RST", + name: "SW_RST_CTRL_N", + desc: ''' + Software controllable resets. + When a particular bit value is 0, the corresponding module is held in reset. + When a particular bit value is 1, the corresponding module is not held in reset. + ''', + count: "NumSwResets", + swaccess: "rw", + hwaccess: "hro", + regwen: "SW_RST_REGWEN", + regwen_multi: true, + fields: [ + { + bits: "0", + name: "VAL", + desc: "Software reset value", + resval: "1", + }, + ], + tags: [// Don't reset other IPs as it will affect CSR access on these IPs. + // In addition, rapid flips of these bits can occasionally cause the reset + // consistency checkers to trigger alerts, which also update err_code bits. + "excl:CsrAllTests:CsrExclWrite"] + } + } + + { name: "ERR_CODE", + desc: ''' + A bit vector of all the errors that have occurred in reset manager + ''', + swaccess: "ro", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "REG_INTG_ERR", + desc: ''' + The register file has experienced an integrity error. + ''' + resval: "0" + }, + + { bits: "1", + name: "RESET_CONSISTENCY_ERR", + desc: ''' + A inconsistent parent / child reset was observed. + ''' + resval: "0" + }, + + { bits: "2", + name: "FSM_ERR", + desc: ''' + Sparsely encoded fsm error. + ''' + resval: "0" + }, + + ] + }, + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr_sec_cm_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr_sec_cm_testplan.hjson new file mode 100644 index 00000000000..096bd7f5777 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr_sec_cm_testplan.hjson @@ -0,0 +1,108 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../rstmgr/data/rstmgr.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../rstmgr/data/rstmgr_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: '''Verify the countermeasure(s) BUS.INTEGRITY. + This entry is covered by tl_access_test. + ''' + stage: V2S + tests: ["rstmgr_tl_intg_err"] + } + { + name: sec_cm_scan_intersig_mubi + desc: '''Verify the countermeasure(s) SCAN.INTERSIG.MUBI. + + **Stimulus**: + Same as smoke test but drive scanmode_i with a constant invalid + value during the test. + + **Check**: + If dut accepts any of invalid values, test will fail by turning dut to scanmode. + ''' + stage: V2S + tests: ["rstmgr_sec_cm_scan_intersig_mubi"] + } + { + name: sec_cm_leaf_rst_bkgn_chk + desc: '''Verify the countermeasure(s) LEAF.RST.BKGN_CHK. + + ** Stimulus**: + Execute a series of reset event - lowpower, hwreq, and + sw reset -. And at the beginning of these events, create + reset consistency error to one of 25 leaf modules. + (exclude u_daon_por_io_div4 and u_daon_por_io_div4_shadowed, + see #11858, #12729 for details) + Do the same test for all 25 modules. + + **Check**: + Upon asserting each reset consistency error, + check alert_fatal_cnsty_fault is asserted. + ''' + stage: V2S + tests: ["rstmgr_leaf_rst_cnsty"] + } + { + name: sec_cm_leaf_rst_shadow + desc: '''Verify the countermeasure(s) LEAF.RST.SHADOW. + After power up, create glitch to a shadow leaf reset module. + Check if normal leaf reset module is not triggerred. + Do over all {shadow, normal} leaf reset module pairs + ''' + stage: V2S + tests: ["rstmgr_leaf_rst_shadow_attack"] + } + { + name: sec_cm_leaf_fsm_sparse + desc: '''Verify the countermeasure(s) LEAF.FSM.SPARSE. + + Force leaf rst check state to illegal value. + This is triggered by common cm primitives + ''' + stage: V2S + tests: ["rstmgr_sec_cm"] + } + { + name: sec_cm_sw_rst_config_regwen + desc: '''Verify the countermeasure(s) SW_RST.CONFIG.REGWEN. + + RSTMGR.SW_RST_CTRL_N. + This is covered by auto csr test. + ''' + stage: V2S + tests: ["rstmgr_csr_rw"] + } + { + name: sec_cm_dump_ctrl_config_regwen + desc: '''Verify the countermeasure(s) DUMP_CTRL.CONFIG.REGWEN. + + RSTMGR.ALERT_INFO_CTRL and RSTMGR.CPU_INFO_CTRL + This is covered by auto csr test. + ''' + stage: V2S + tests: ["rstmgr_csr_rw"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr_testplan.hjson new file mode 100644 index 00000000000..be44e83d038 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/rstmgr_testplan.hjson @@ -0,0 +1,247 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "rstmgr" + import_testplans: ["hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson", + "hw/dv/tools/dvsim/testplans/csr_testplan.hjson", + "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson", + "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson", + "hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson", + "rstmgr_sec_cm_testplan.hjson"] + + testpoints: [ + { + name: smoke + desc: ''' + Smoke test accessing a major datapath within the rstmgr. + + Checks the behavior of rstmgr when receiving various reset requests. + + **Stimulus**: + - Send a scan reset. + - Send a low power entry reset. + - Send a peripheral reset request. + - Send a debug reset. + - Configure a software request for peripheral reset. + - Set alert and cpu dump inputs to random values. + + **Checks**: + - Checks the reset_info matches expected values. + - Checks the `alert_info` CSR correctly captures the input info. + - Checks the `cpu_info` CSR correctly captures the input info. + - Checks the output reset pins corresponding to sw resettable + units match `sw_rst_ctrl_n` CSR. + ''' + stage: V1 + tests: ["rstmgr_smoke"] + } + { + name: reset_stretcher + desc: '''Test the POR reset signal must be stable for multiple cycles. + + The POR reset signal must remain active for at least 32 consecutive + cycles before going inactive for the rest of the reset tree to go + inactive. + + **Stimulus**: + - Activate POR, and de-activate it at a random width less than 32 + cycles between de-activations for N de-activations. + + **Checks**: + - With SVA check the output reset is only set if the input reset + has had at least 32 cycles of steady input reset active. + ''' + stage: V2 + tests: ["rstmgr_por_stretcher"] + } + { + name: sw_rst + desc: '''Test the sw_rst functionality. + + The `sw_rst_regwen` and `sw_rst_ctrl_n` CSRs control the specific + reset outputs to peripherals in the following sequence: + - Test all `sw_rst_ctrl_n` bits when `sw_rst_regwen` is all 1's. + - Clear each `sw_rst_regwen` bit to verify the corresponding resets + are masked. + + **Stimulus**: + - Write `sw_rst_ctrl_n` CSR with random values when regwen is all 1's. + - Clear each `sw_rst_regwen` bit and write `sw_rst_ctrl_n` CSR with + all 0's. + - After each regwen bit check set `sw_rst_ctrl_n` to all 1's. + + **Checks**: + - Check that the zero bits in `sw_rst_ctrl_n` enabled by + `sw_rst_regwen` cause the respective resets to become active. + - Check that the zero bits in `sw_rst_ctrl_n` disabled by + `sw_rst_regwen` have no effect on resets. + - Check the `reset_info`, `cpu_info`, and `alert_info` CSRs are not modified. + ''' + stage: V2 + tests: ["rstmgr_sw_rst"] + } + { + name: sw_rst_reset_race + desc: '''Test sw_rst and reset close in time. + + Sends sw_rst and regular resets in close temporal proximity. + + **Stimulus**: + - Write `sw_rst_ctrl_n` CSR with random values when regwen is all 1's. + - Send a hardware reset. + - Release resets. + + **Checks**: + - Check the `reset_info` CSR. + - Reset behavior is checked by SVA. + ''' + stage: V2 + tests: ["rstmgr_sw_rst_reset_race"] + } + { + name: reset_info + desc: '''Test the reporting of reset reason. + + **Stimulus**: + - Generate the different resets recorded in `reset_info` CSR. + - Randomly clear `reset_info` (it is rw1c). + + **Checks**: + - The resulting setting of `reset_info` is as expected. + - Each bit was set at least once. + - Each bit was cleared at least once. + ''' + stage: V2 + tests: ["rstmgr_reset"] + } + { + name: cpu_info + desc: '''Test the cpu_info recording. + + The `cpu_info` CSR register(s) can capture the contents of the + `cpu_dump_i` input when resets happen and it is enabled. + + **Stimulus**: + - Regularly modify the `cpu_dump_i` input. + - With `cpu_regwen` on, randomly set `cpu_info_ctrl.en` to control + whether the dump should be captured. + - Generate reset(s) as in `smoke` testpoint. + + **Checks**: + - Verify the `cpu_info` is only captured when enabled. + - Verify the `cpu_info` contents at each `cpu_info_ctrl.index` + matches the expected value. + ''' + stage: V2 + tests: ["rstmgr_reset"] + } + { + name: alert_info + desc: '''Test the alert_info recording. + + The `alert_info` CSR register(s) can capture the contents of the + `alert_dump_i` input when resets happen and it is enabled. + + **Stimulus**: + - Regularly modify the `alert_dump_i` input. + - With `alert_regwen` on, randomly set `alert_info_ctrl.en` to + control whether the dump should be captured. + - Generate reset(s) as in `smoke` testpoint. + + **Checks**: + - Verify the `alert_info` is only captured when enabled. + - Verify the `alert_info` contents at each `alert_info_ctrl.index` + matches the expected value. + ''' + stage: V2 + tests: ["rstmgr_reset"] + } + { + name: reset_info_capture + desc: '''Test the capture blocking effect of rst_cpu_n input. + + After an AON reset reset capture is blocked until the input + rst_cpu_n goes inactive. + + **Stimulus**: + - Wait for a random number of resets before setting rst_cpu_n + inactive. + + **Checks**: + - Non-AON resets prior to this event don't capture. + ''' + stage: V2 + tests: ["rstmgr_reset"] + } + { + name: stress_all + desc: '''This runs random tests sequentially. + + Stress with the following sequences: + - rstmgr_reset_vseq + - rstmgr_smoke_vseq + - rstmgr_sw_rst_vseq + ''' + stage: V2 + tests: ["rstmgr_stress_all"] + } + ] + + covergroups: [ + { + name: reset_stretcher_cg + desc: '''Collects coverage on the reset_stretcher functionality. + + The stretcher counter is reset when por_n_i is not stable. + Collect both the count at the point of instability, and the + number of times the counter was reset. + ''' + } + { + name: alert_info_capture_cg + desc: '''Collects coverage on reset type and enable when reset occurs. + + Uses `reset_cp` that records the reset encoded as in `reset_info` + CSR, and `ctrl_en_cp` capturing `alert_info_ctrl.en` CSR, and + creates the per-reset_cp bit cross. + ''' + } + { + name: alert_info_access_cg + desc: '''Collects coverage on the reads of alert_info. + + This captures `alert_info_ctrl.index` CSR to verify all fields + of alert_info have been read. + ''' + } + { + name: cpu_info_capture_cg + desc: '''Collects coverage on the reset and enable when reset occurs. + + Uses `reset_cp` that records the reset encoded as in `reset_info` + CSR, and `ctrl_en_cp` capturing `cpu_info_ctrl.en` CSR, and creates + the per-reset_cp bit cross. + ''' + } + { + name: cpu_info_access_cg + desc: '''Collects coverage on the reads of cpu_info. + + This captures `cpu_info_ctrl.index` CSR to verify all fields + of cpu_info have been read. + ''' + } + { + name: sw_rst_cg + desc: '''Collects coverage on the software reset functionality. + + Each bit of the pair `sw_rst_regwen` and `sw_rst_ctrl_n` CSRs + independently control if the corresponding output reset is + activated. + This collects one coverpoint for each, and their cross. + ''' + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/top_darjeeling_no_ibex_rstmgr.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/top_darjeeling_no_ibex_rstmgr.ipconfig.hjson new file mode 100644 index 00000000000..2e841238aed --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data/top_darjeeling_no_ibex_rstmgr.ipconfig.hjson @@ -0,0 +1,476 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_rstmgr + param_values: + { + clk_freqs: + { + aon: 62500000 + io_div4: 250000000 + main: 1000000000 + io: 1000000000 + io_div2: 500000000 + } + reqs: + { + int: + [ + { + name: MainPwr + desc: main power glitch reset request + module: pwrmgr_aon + } + { + name: Esc + desc: escalation reset request + module: alert_handler + } + ] + peripheral: + [ + { + name: aon_timer_rst_req + width: "1" + module: aon_timer_aon + desc: Watchdog reset request. + } + { + name: rst_req_external + width: "1" + module: soc_proxy + desc: External reset request + } + ] + } + power_domains: + [ + Aon + "0" + ] + num_rstreqs: 2 + sw_rsts: + { + spi_device: io_div4 + spi_host0: io_div4 + i2c0: io_div4 + } + output_rsts: + [ + { + name: por_aon + gen: false + type: top + domains: + [ + "0" + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_aon_n + clock: aon + } + { + name: por + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_n + parent: por_aon + clock: main + } + { + name: por_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_n + parent: por_aon + clock: io + } + { + name: por_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div2_n + parent: por_aon + clock: io_div2 + } + { + name: por_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div4_n + parent: por_aon + clock: io_div4 + } + { + name: lc + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_n + parent: lc_src + clock: main + } + { + name: lc_aon + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_aon_n + parent: lc_src + clock: aon + } + { + name: lc_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_n + parent: lc_src + clock: io + } + { + name: lc_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_div2_n + parent: lc_src + clock: io_div2 + } + { + name: lc_io_div4 + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_io_div4_n + parent: lc_src + clock: io_div4 + } + { + name: sys + gen: true + type: top + domains: [] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_n + parent: sys_src + clock: main + } + { + name: sys_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_io_div4_n + parent: sys_src + clock: io_div4 + } + { + name: spi_device + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_device_n + parent: lc_src + clock: io_div4 + } + { + name: spi_host0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_host0_n + parent: lc_src + clock: io_div4 + } + { + name: i2c0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_i2c0_n + parent: lc_src + clock: io_div4 + } + ] + leaf_rsts: + [ + { + name: por + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_n + parent: por_aon + clock: main + } + { + name: por_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_n + parent: por_aon + clock: io + } + { + name: por_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div2_n + parent: por_aon + clock: io_div2 + } + { + name: por_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_por_io_div4_n + parent: por_aon + clock: io_div4 + } + { + name: lc + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_n + parent: lc_src + clock: main + } + { + name: lc_aon + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_aon_n + parent: lc_src + clock: aon + } + { + name: lc_io + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_n + parent: lc_src + clock: io + } + { + name: lc_io_div2 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_lc_io_div2_n + parent: lc_src + clock: io_div2 + } + { + name: lc_io_div4 + gen: true + type: top + domains: + [ + "0" + Aon + ] + shadowed: true + sw: false + path: rstmgr_aon_resets.rst_lc_io_div4_n + parent: lc_src + clock: io_div4 + } + { + name: sys + gen: true + type: top + domains: [] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_n + parent: sys_src + clock: main + } + { + name: sys_io_div4 + gen: true + type: top + domains: + [ + Aon + ] + shadowed: false + sw: false + path: rstmgr_aon_resets.rst_sys_io_div4_n + parent: sys_src + clock: io_div4 + } + { + name: spi_device + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_device_n + parent: lc_src + clock: io_div4 + } + { + name: spi_host0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_spi_host0_n + parent: lc_src + clock: io_div4 + } + { + name: i2c0 + gen: true + type: top + domains: + [ + "0" + ] + shadowed: false + sw: true + path: rstmgr_aon_resets.rst_i2c0_n + parent: lc_src + clock: io_div4 + } + ] + rst_ni: lc_io_div4 + export_rsts: {} + with_alert_handler: true + topname: darjeeling_no_ibex + uniquified_modules: {} + module_instance_name: rstmgr + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/defs.bzl new file mode 100644 index 00000000000..371813a14ec --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/defs.bzl @@ -0,0 +1,11 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +RSTMGR = opentitan_ip( + name = "rstmgr", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data:rstmgr.hjson", + ipconfig = "//hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/data:top_darjeeling_no_ibex_rstmgr.ipconfig.hjson", + extension = "//hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util:dt", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/checklist.md b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/checklist.md new file mode 100644 index 00000000000..1e01155675d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/checklist.md @@ -0,0 +1,266 @@ +# RSTMGR Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [RSTMGR peripheral.](../README.md) +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [RSTMGR Design Spec](../README.md) +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | NA | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|---------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | Done | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [DOC_INTEGRATION_GUIDE][] | Waived | This checklist item has been added retrospectively. +Documentation | [MISSING_FUNC][] | Done | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | +RTL | [STYLE_X][] | Done | +RTL | [CDC_SYNCMACRO][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_SETUP][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [AREA_CHECK][] | Done | +Code Quality | [TIMING_CHECK][] | Done | +Security | [SEC_CM_DOCUMENTED][] | Done | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[DOC_INTEGRATION_GUIDE]: ../../../../../doc/project_governance/checklist/README.md#doc_integration_guide +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[RDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#rdc_setup +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | Done | +Security | [SEC_CM_SHADOW_REGS][] | Done | +Security | [SEC_CM_RTL_REVIEWED][] | Done | +Security | [SEC_CM_COUNCIL_REVIEWED][] | Done | + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | With waivers approved by TC on 2024-08-08 +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Done | +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | matutem@, vogelpi@, adk@ +Review | Signoff date | Done | 2024-08-08 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [RSTMGR DV document](../dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | [RSTMGR Testplan](../dv/README.md#testplan) +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | Done | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | Done | +Tests | [SIM_SMOKE_TEST_PASSING][] | Done | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done | Block has no mem +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done | +Regression | [FPV_REGRESSION_SETUP][] | N/A | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Done | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception: power, performance +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Done | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | Done | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | Done | +Tests | [SIM_ALL_TESTS_PASSING][] | Done | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | N/A | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | N/A | +Tests | [SIM_FW_SIMULATED][] | Done | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Done | +Coverage | [SIM_CODE_COVERAGE_V2][] | Done | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Done | +Coverage | [FPV_CODE_COVERAGE_V2][] | N/A | +Coverage | [FPV_COI_COVERAGE_V2][] | N/A | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Done | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Done | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Done | +Tests | [FPV_SEC_CM_VERIFIED][] | Done | +Tests | [SIM_SEC_CM_VERIFIED][] | Done | +Coverage | [SIM_COVERAGE_REVIEWED][] | Done | +Review | [SEC_CM_DV_REVIEWED][] | Done | + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_verified +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]:../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/interfaces.md b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/interfaces.md new file mode 100644 index 00000000000..3b4ac080210 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/interfaces.md @@ -0,0 +1,55 @@ +# Hardware Interfaces + + +The following table lists the instantiation parameters of `rstmgr`. + +Parameter | Default | Description +----------------------------|---------------|--------------- +`SecCheck` | 1 | Enables reset consistency checks on the leaf reset. Each check contains a small FSM. +`SecMaxSyncDelay` | 2 | The default synchronization delay assumptions used in reset consistency checks. If a design uses a sync cell with more stages of delay, that value should be supplied. + + + + +Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`rstmgr`** has the following hardware interfaces defined +- Primary Clock: **`clk_i`** +- Other Clocks: **`clk_aon_i`**, **`clk_io_div4_i`**, **`clk_main_i`**, **`clk_io_i`**, **`clk_io_div2_i`**, **`clk_por_i`** +- Bus Device Interfaces (TL-UL): **`tl`** +- Bus Host Interfaces (TL-UL): *none* +- Peripheral Pins for Chip IO: *none* +- Interrupts: *none* + +## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) + +| Port Name | Package::Struct | Type | Act | Width | Description | +|:------------|:-----------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------| +| por_n | logic | uni | rcv | 2 | Root power on reset signals from ast. There is one root reset signal for each core power domain. | +| pwr | pwr_rst | req_rsp | rsp | 1 | Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert. | +| resets | rstmgr_pkg::rstmgr_out | uni | req | 1 | Leaf resets fed to the system. | +| rst_en | rstmgr_pkg::rstmgr_rst_en | uni | req | 1 | Low-power-group outputs used by alert handler. | +| alert_dump | alert_handler_pkg::alert_crashdump | uni | rcv | 1 | Alert handler crash dump information. | +| cpu_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | rcv | 1 | Main processing element crash dump information. | +| sw_rst_req | prim_mubi_pkg::mubi4 | uni | req | 1 | Software requested system reset to pwrmgr. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | + +## Security Alerts + +| Alert Name | Description | +|:------------------|:---------------------------------------------------------------------------------------------------------------------------------------------------------------| +| fatal_fault | This fatal alert is triggered when a fatal structural fault is detected. Structural faults include errors such as sparse fsm errors and tlul integrity errors. | +| fatal_cnsty_fault | This fatal alert is triggered when a reset consistency fault is detected. It is separated from the category above for clearer error collection and debug. | + +## Security Countermeasures + +| Countermeasure ID | Description | +|:-------------------------------|:---------------------------------------------------------------------------------------------------------------------------| +| RSTMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. | +| RSTMGR.SCAN.INTERSIG.MUBI | scan control signals are multibit | +| RSTMGR.LEAF.RST.BKGN_CHK | Background consistency checks for each leaf reset. | +| RSTMGR.LEAF.RST.SHADOW | Leaf resets to blocks containing shadow registers are shadowed | +| RSTMGR.LEAF.FSM.SPARSE | Sparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets | +| RSTMGR.SW_RST.CONFIG.REGWEN | Software reset controls are protected by regwen | +| RSTMGR.DUMP_CTRL.CONFIG.REGWEN | Crash dump controls are protected by regwen | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/programmers_guide.md b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/programmers_guide.md new file mode 100644 index 00000000000..8f46814c81c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/programmers_guide.md @@ -0,0 +1,5 @@ +# Programmer's Guide + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_rstmgr.h) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/registers.md b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/registers.md new file mode 100644 index 00000000000..021a1a13745 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/registers.md @@ -0,0 +1,316 @@ +# Registers + + +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------|:---------|---------:|:-------------------------------------------------------------------| +| rstmgr.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| rstmgr.[`RESET_REQ`](#reset_req) | 0x4 | 4 | Software requested system reset. | +| rstmgr.[`RESET_INFO`](#reset_info) | 0x8 | 4 | Device reset reason. | +| rstmgr.[`ALERT_REGWEN`](#alert_regwen) | 0xc | 4 | Alert write enable | +| rstmgr.[`ALERT_INFO_CTRL`](#alert_info_ctrl) | 0x10 | 4 | Alert info dump controls. | +| rstmgr.[`ALERT_INFO_ATTR`](#alert_info_attr) | 0x14 | 4 | Alert info dump attributes. | +| rstmgr.[`ALERT_INFO`](#alert_info) | 0x18 | 4 | Alert dump information prior to last reset. | +| rstmgr.[`CPU_REGWEN`](#cpu_regwen) | 0x1c | 4 | Cpu write enable | +| rstmgr.[`CPU_INFO_CTRL`](#cpu_info_ctrl) | 0x20 | 4 | Cpu info dump controls. | +| rstmgr.[`CPU_INFO_ATTR`](#cpu_info_attr) | 0x24 | 4 | Cpu info dump attributes. | +| rstmgr.[`CPU_INFO`](#cpu_info) | 0x28 | 4 | Cpu dump information prior to last reset. | +| rstmgr.[`SW_RST_REGWEN_0`](#sw_rst_regwen) | 0x2c | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_REGWEN_1`](#sw_rst_regwen) | 0x30 | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_REGWEN_2`](#sw_rst_regwen) | 0x34 | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_0`](#sw_rst_ctrl_n) | 0x38 | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_1`](#sw_rst_ctrl_n) | 0x3c | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_2`](#sw_rst_ctrl_n) | 0x40 | 4 | Software controllable resets. | +| rstmgr.[`ERR_CODE`](#err_code) | 0x44 | 4 | A bit vector of all the errors that have occurred in reset manager | + +## ALERT_TEST +Alert Test Register +- Offset: `0x0` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "fatal_cnsty_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------------|:-------------------------------------------------| +| 31:2 | | | | Reserved | +| 1 | wo | 0x0 | fatal_cnsty_fault | Write 1 to trigger one alert event of this kind. | +| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | + +## RESET_REQ +Software requested system reset. +- Offset: `0x4` +- Reset default: `0x9` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | rw | 0x9 | VAL | When set to kMultiBitBool4True, a reset to power manager is requested. Upon completion of reset, this bit is automatically cleared by hardware. | + +## RESET_INFO +Device reset reason. +- Offset: `0x8` +- Reset default: `0x1` +- Reset mask: `0x7f` + +### Fields + +```wavejson +{"reg": [{"name": "POR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "LOW_POWER_EXIT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "SW_RESET", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "HW_REQ", "bits": 4, "attr": ["rw1c"], "rotate": 0}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}} +``` + +| Bits | Type | Reset | Name | +|:------:|:------:|:-------:|:----------------------------------------------| +| 31:7 | | | Reserved | +| 6:3 | rw1c | 0x0 | [HW_REQ](#reset_info--hw_req) | +| 2 | rw1c | 0x0 | [SW_RESET](#reset_info--sw_reset) | +| 1 | rw1c | 0x0 | [LOW_POWER_EXIT](#reset_info--low_power_exit) | +| 0 | rw1c | 0x1 | [POR](#reset_info--por) | + +### RESET_INFO . HW_REQ +Indicates when a device has reset due to a hardware requested reset. +The bit mapping is as follows: +b3: aon_timer_aon: Watchdog reset request. +b4: soc_proxy: External reset request +b5: pwrmgr_aon: main power glitch reset request +b6: alert_handler: escalation reset request + +### RESET_INFO . SW_RESET +Indicates when a device has reset due to [`RESET_REQ.`](#reset_req) + +### RESET_INFO . LOW_POWER_EXIT +Indicates when a device has reset due low power exit. + +### RESET_INFO . POR +Indicates when a device has reset due to power up. + +## ALERT_REGWEN +Alert write enable +- Offset: `0xc` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, [`ALERT_INFO_CTRL`](#alert_info_ctrl) can be modified. | + +## ALERT_INFO_CTRL +Alert info dump controls. +- Offset: `0x10` +- Reset default: `0x0` +- Reset mask: `0xf1` +- Register enable: [`ALERT_REGWEN`](#alert_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "INDEX", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------| +| 31:8 | | | | Reserved | +| 7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. | +| 3:1 | | | | Reserved | +| 0 | rw | 0x0 | EN | Enable alert dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). | + +## ALERT_INFO_ATTR +Alert info dump attributes. +- Offset: `0x14` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "CNT_AVAIL", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the alert info dump. | + +## ALERT_INFO + Alert dump information prior to last reset. + Which value read is controlled by the [`ALERT_INFO_CTRL`](#alert_info_ctrl) register. +- Offset: `0x18` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "VALUE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------| +| 31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. | + +## CPU_REGWEN +Cpu write enable +- Offset: `0x1c` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-----------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | When 1, [`CPU_INFO_CTRL`](#cpu_info_ctrl) can be modified. | + +## CPU_INFO_CTRL +Cpu info dump controls. +- Offset: `0x20` +- Reset default: `0x0` +- Reset mask: `0xf1` +- Register enable: [`CPU_REGWEN`](#cpu_regwen) + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "INDEX", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------------------------------------------------------------------------------------------------| +| 31:8 | | | | Reserved | +| 7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. | +| 3:1 | | | | Reserved | +| 0 | rw | 0x0 | EN | Enable cpu dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). | + +## CPU_INFO_ATTR +Cpu info dump attributes. +- Offset: `0x24` +- Reset default: `0x0` +- Reset mask: `0xf` + +### Fields + +```wavejson +{"reg": [{"name": "CNT_AVAIL", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:------------------------------------------------------------| +| 31:4 | | | | Reserved | +| 3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the cpu info dump. | + +## CPU_INFO + Cpu dump information prior to last reset. + Which value read is controlled by the [`CPU_INFO_CTRL`](#cpu_info_ctrl) register. +- Offset: `0x28` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "VALUE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:----------------------------------------| +| 31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. | + +## SW_RST_REGWEN +Register write enable for software controllable resets. +When a particular bit value is 0, the corresponding value in [`SW_RST_CTRL_N`](#sw_rst_ctrl_n) can no longer be changed. +When a particular bit value is 1, the corresponding value in [`SW_RST_CTRL_N`](#sw_rst_ctrl_n) can be changed. +- Reset default: `0x1` +- Reset mask: `0x1` + +### Instances + +| Name | Offset | +|:----------------|:---------| +| SW_RST_REGWEN_0 | 0x2c | +| SW_RST_REGWEN_1 | 0x30 | +| SW_RST_REGWEN_2 | 0x34 | + + +### Fields + +```wavejson +{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:-------------------------------------------------------| +| 31:1 | | | | Reserved | +| 0 | rw0c | 0x1 | EN | Register write enable for software controllable resets | + +## SW_RST_CTRL_N +Software controllable resets. +When a particular bit value is 0, the corresponding module is held in reset. +When a particular bit value is 1, the corresponding module is not held in reset. +- Reset default: `0x1` +- Reset mask: `0x1` +- Register enable: [`SW_RST_REGWEN`](#sw_rst_regwen) + +### Instances + +| Name | Offset | +|:----------------|:---------| +| SW_RST_CTRL_N_0 | 0x38 | +| SW_RST_CTRL_N_1 | 0x3c | +| SW_RST_CTRL_N_2 | 0x40 | + + +### Fields + +```wavejson +{"reg": [{"name": "VAL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:---------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x1 | VAL | Software reset value | + +## ERR_CODE +A bit vector of all the errors that have occurred in reset manager +- Offset: `0x44` +- Reset default: `0x0` +- Reset mask: `0x7` + +### Fields + +```wavejson +{"reg": [{"name": "REG_INTG_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RESET_CONSISTENCY_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FSM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------------|:------------------------------------------------------| +| 31:3 | | | | Reserved | +| 2 | ro | 0x0 | FSM_ERR | Sparsely encoded fsm error. | +| 1 | ro | 0x0 | RESET_CONSISTENCY_ERR | A inconsistent parent / child reset was observed. | +| 0 | ro | 0x0 | REG_INTG_ERR | The register file has experienced an integrity error. | + + + diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/reset_topology.svg b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/reset_topology.svg new file mode 100644 index 00000000000..81510a29643 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/reset_topology.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/theory_of_operation.md b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/theory_of_operation.md new file mode 100644 index 00000000000..cdacd78b7b1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/doc/theory_of_operation.md @@ -0,0 +1,310 @@ +# Theory of Operation + +The OpenTitan reset topology and reset controller block diagram are shown in the diagram below. +The reset controller is closely related to the [power controller](../../pwrmgr/README.md), please refer to that spec for details on how reset controller inputs are controlled. + +![Reset Topology](../doc/reset_topology.svg) + +## Reset Topology + +The topology can be summarized as follows: + +* There are two reset domains + * Test Domain - Driven by `TRSTn` + * Core Domain - Driven by internal [POR circuitry](../../../ip/ast/README.md). +* Test domain is comprised of the following components + * SOC TAP and related DFT circuits + * RISC-V TAP (part of the `rv_dm` module) + +The test domain does not have sub reset trees. +`TRSTn` is used directly by all components in the domain. + +The Core domain consists of all remaining logic and contains 4 sub reset trees, see table below. + + + + + + + + + + + + + + + + + + + + + + +
+Reset Tree + Description +
rst_por_n + POR reset tree. +

+This reset is driven by ast, stretched inside the reset manager and resets all core domain logic in the design. +

rst_lc_n + Life Cycle reset tree. +

+This reset is derived from rst_por_n and resets all logic in the design except:

    + +
  • rv_dm +
  • A small portion of pinmux
+
rst_sys_n + Debug reset tree. +

+This reset is derived from rst_por_n and resets debug domain logic excluded in the life cycle reset tree

    +
rst_{module}_n + Module specific reset. +

+This reset is derived from rst_lc_n and sets only the targeted module and nothing else. +

+For OpenTitan, the only current targets are spi_device, all instances of spi_host, all instances of i2c and usbdev +

+ +The reset trees are cascaded upon one another in this order: +- `rst_por_n` -> `rst_lc_n` -> `rst_module_n` +- `rst_por_n` -> `rst_sys_n` -> `rst_module_n` +This means when a particular reset asserts, all downstream resets also assert. + +The primary difference between `rst_lc_n` and `rst_sys_n` is that the former controls the reset state of most logic in the system, while the latter controls the reset state only of the debug domain. +This separation is required because the debug domain may request the system to reset while retaining debug info and control. +This is particularly useful if one wanted to debug something early during the boot flow, and thus needed to set a break point after requesting a debug reset. + +The reset topology also contains additional properties: +* Selective processor HART resets, such as `hartreset` in `dmcontrol`, are not implemented, as it causes a security policy inconsistency with the remaining system. + * Specifically, these selective resets can cause the cascaded property shown above to not be obeyed. +* Modules do not implement local resets that wipe configuration registers, especially if there are configuration locks. + * Modules are allowed to implement local soft resets that clear datapaths; but these are examined on a case by case basis for possible security side channels. +* In a production system, the Test Reset Input (`TRSTn`) should be explicitly asserted through system integration. + * In a production system, `TRSTn` only needs to be released for RMA transitions and nothing else. +. + +## Reset Manager + +The reset manager handles the reset of the core domain, and also holds relevant reset information in CSR registers, such as: + +* [`RESET_INFO`](registers.md#reset_info) indicates why the system was reset. +* [`ALERT_INFO`](registers.md#alert_info) contains the recorded alert status prior to system reset. + * This is useful in case the reset was triggered by an alert escalation. +* [`CPU_INFO`](registers.md#cpu_info) contains recorded CPU state prior to system reset. + * This is useful in case the reset was triggered by a watchdog where the host hung on a particular bus transaction. + +Additionally, the reset manager, along with the power manager, accepts requests from the system and asserts resets for the appropriate clock trees. +These requests primarily come from the following sources: +* Peripherals capable of reset requests: such as [sysrst_ctrl](../../../../ip/sysrst_ctrl/README.md) and [always on timers ](../../../../ip/aon_timer/README.md). +* Debug modules such as `rv_dm`. +* Power manager request for low power entry and exit. +* Escalation reset requests such as those from `alert_handler` or `pwrmgr` itself. +* Direct software request for reset. + +### Shadow Resets + +OpenTitan supports the shadow configuration registers. +These are registers stored in two constantly checking copies to ensure the values are not maliciously or accidentally disturbed. +For these components, the reset manager outputs a shadow reset dedicated to resetting only the shadow storage. +This reset separation ensures that a targetted attack on the reset line cannot easily defeat shadow registers. + +### Reset Consistency Checks + +The reset manager implements reset consistency checks to ensure that triggered resets are supposed to happen and not due to some fault in the system. +Every leaf reset in the system has an associated consistency checker. + +The consistency check ensures that when a leaf reset asserts, either its parent reset must have asserted, or the software request, if available, has asserted. +While this sounds simple in principle, the check itself crosses up to 3 clock domains and must be carefully managed. + +First, the parent and leaf resets are used to asynchronously assert a flag indication. +This flag indication is then synchronized into the reset manager's local clock domain. + +The reset manager then checks as follows: +- If a leaf reset has asserted, check to see either its parent or software request (synchronous to the local domain) has asserted. + +- If the condition is not true, it is possible the parent reset indication is still being synchronized, thus we wait for the parent indication. + +- It is also possible the parent indication was seen first, but the leaf condition was not, in this case, we wait for the leaf indication. + +- A timeout period corresponding to the maximum synchronization delay is used to cover both waits. + - If the appropriate pairing is not seen in the given amount of time, signal an error, as the leaf reset asserted without cause. + +- If all reset conditions are satisfied, wait for the reset release to gracefully complete the cycle. + +### Reset Indications for Alert Handler + +The alert handler needs to know the status of the various reset domains in the system to avoid false alert indications due to the ping mechanism. +To that end, the reset manager outputs a 4bit MuBi signal for each reset domain that indicates whether its reset is active. +For more information on this mechanism, see [alert handler documentation](../../alert_handler/doc/theory_of_operation.md#low-power-management-of-alert-channels). + +## Design Details + +The reset manager generates the resets required by the system by synchronizing reset tree components to appropriate output clocks. +As a result, a particular reset tree (for example `rst_lc_n`) may have multiple outputs depending on the clock domains of its consumers. + +Each reset tree is discussed in detail below. + +## POR Reset Tree + +The POR reset tree, `rst_por_n`, is the root reset of the entire device. +If this reset ever asserts, everything in the design is reset. + +The `ast` input `aon_pok` is used as the root reset indication. +It is filtered and stretched to cover any slow voltage ramp scenarios. +The stretch parameters are design time configurations. + +* The filter acts as a synchronizer and is by default 3 stages. +* The count by default is 32. + * The counter increments only when all stages of the filter are 1. + * If any stage at any point becomes '0', the reset counter returns to 0 and downstream logic is driven to reset again. +* Both functions are expected to operate on slow, always available KHz clocks. + + +## Life Cycle Reset Tree + +Life cycle reset, `rst_lc_n` asserts under the following conditions: +* Whenever `rst_por_n` asserts. +* Whenever a peripheral reset request (always on timer watchdog, rbox reset request, alert handler escalation, direct software request) is received. + +The `rst_lc_n` tree contains both always-on and non-always-on versions. +How many non-always-on versions is dependent on how many power domains are supported by the system. + +## System Reset Tree + +System reset, `rst_sys_n` , assertion depends on life cycle state. + +When in PROD and PROD_END states, `rst_sys_n` is identical to `rst_lc_n`. + +When in TEST, RMA and DEV states, `rst_sys_n` is identical to `rst_lc_n` unless the reset request is `ndmreset_req`. +`ndmreset_req` is issued by the debug module of the system, it requests for all logic, except those needed to maintain debug state to reset. + +Since `ndmreset_req` is valid only during TEST, RMA and DEV states, it is the only place where the reset is differentiated. +During these states, when `ndmreset_req` is issued, all logic except the debug module and associated glue logic are reset. + +The `rst_sys_n` tree contains both always-on and non-always-on versions. +How many non-always-on versions is dependent on how many power domains are supported by the system. + +## Output Leaf Resets + +The reset trees discussed above are not directly output to the system for consumption. +Instead, the output leaf resets are synchronized versions of the various root resets. +How many leaf resets there are and to which clock is decided by the system and templated through the reset manager module. + +Assuming a leaf output has N power domains and M clock domains, it potentially means one reset tree may output NxM outputs to satisfy all the reset scenario combinations. + +## Power Domains and Reset Trees + +It is alluded above that reset trees may contain both always-on and non-always-on versions. +This distinction is required to support power manager's various low power states. +When a power domain goes offline, all of its components must reset, regardless of the reset tree to which it belongs. + +For example, assume a system with two power domains - `Domain A` is always-on, and `Domain B` is non-always-on. +When `Domain B` is powered off, all of `Domain B`'s resets, from `rst_lc_n`, `rst_sys_n` to `rst_module_n` are asserted. +However, the corresponding resets for `Domain A` are left untouched because it has not been powered off. + +## Software Controlled Resets + +Certain leaf resets can be directly controlled by software. +Due to security considerations, most leaf resets cannot be controlled, only a few blocks are given exceptions. +The only blocks currently allowed to software reset are `spi_device`, `usbdev`, `spi_host` and `i2c`. + +The criteria for selecting which block is software reset controllable is meant to be overly restrictive. +Unless there is a clear need, the default option is to not provide reset control. + +In general, the following rules apply: +* If a module has configuration register lockdown, it cannot be software resettable. +* If a module operates on secret data (keys), it cannot be software resettable. + * Or a software reset should render the secret data unusable until some initialization routine is run to reduce the Hamming leakage of secret data. +* If a module can alter the software's perception of time or general control flow (timer or interrupt aggregator), it cannot be software resettable. +* If a module contains sensor functions for security, it cannot be software resettable. +* If a module controls life cycle or related function, it cannot be software resettable. + +## Summary + +The following table summarizes the different reset requests and which part of each reset tree, along with what power domain is affected. + +Reset Request Type | Example | POR Reset Tree | LC Reset Tree | SYS Reset Tree | Module Specific Reset +----------------------------------| --------------------------------------------------------------| ---------------| ------------- | --------------- | ---------------------- +POR | VCC toggle, POR_N pad toggle | all domains | all domains | all domains | all domains +HW reset Request | `aon_timer` reset request, `alert_handler` escalation request | | all domains | all domains | all domains +Directed SW system reset request | `rstmgr` SW_RESET | | all domains | all domains | all domains +Ndm reset request (PROD/PROD_END) | `rv_dm` non-debug-module reset request in PROD | | all domains | all domains | all domains +Ndm reset request (Other states) | `rv_dm` non-debug-module reset request in DEV | | all domains | | all domains +SW low power entry | wait-for-interrupt deep sleep entry | | non-aon domains | non-aon domains | non-aon domains +SW controlled reset request | `rstmgr` SW_RST_CTRL_N | | | | all domains + + +## Reset Information + +The reset information register is a reflection of the reset state from the perspective of the system. +In OpenTitan, since there is only 1 host, it is thus from the perspective of the processor. +This also suggests that if the design had multiple processors, there would need to be multiple such registers. + +If a reset does not cause the processor to reset, there is no reason for the reset information to change (this is also why there is a strong security link between the reset of the processor and the rest of the system). +The following are the currently defined reset reasons and their meaning: + +Reset Cause | Description +------------------------|--------------- +`POR` | Cold boot, the system was reset through POR circuitry. +`LOW_POWER_EXIT` | Warm boot, the system was reset through low power exit. +`NDM RESET` | Warm boot, the system was reset through `rv_dm` non-debug-module request. +`SW_REQ` | Warm boot, the system was reset through [`RESET_REQ`](registers.md#reset_req). +`HW_REQ` | Warm boot, the system was reset through peripheral requests. There may be multiple such requests. + + +The reset info register is write 1 clear. +It is software responsibility to clear old reset reasons; the reset manager simply records based on the rules below. + +Excluding power on reset, which is always recorded when the device POR circuitry is triggered, the other resets are recorded when authorized by the reset manager. +Reset manager authorization is based on reset categories as indicated by the power manager. +The power manager has three reset categories that are mutually exclusive: +* No reset has been triggered by pwrmgr. +* Low power entry reset has been triggered by pwrmgr. +* Software or peripheral reset request has been triggered by pwrmgr. + +The reset categories are sent to the reset manager so that it can decide which reason to record when the processor reset is observed. +Non-debug-module resets are allowed only when no resets have been triggered by pwrmgr. + +Since a reset could be motivated by multiple reasons (a security escalation during low power transition for example), the reset information registers constantly record all reset causes in which it is allowed. +The only case where this is not done is `POR`, where active recording is silenced until the first processor reset release. + +Even though four reset causes are labeled as warm boot, their effects on the system are not identical. + +* When the reset cause is `LOW_POWER_EXIT`, it means only the non-always-on domains have been reset. + * Always-on domains retain their pre-low power values. +* When the reset cause is `NDM_RESET`, it means only the `rst_sys_n` tree has asserted for all power domains. +* When the reset cause is `HW_REQ` or `SW_REQ`, it means everything other than power / clock / reset managers have reset. + +This behavioral difference may be important to software, as it implies the configuration of the system may need to be different. + +## Crash Dump Information + +The reset manager manages crash dump information for software debugging across unexpected resets and watchdogs. +When enabled, the latest alert information and latest CPU information are captured in always-on registers. + +When the software resumes after the reset, it is then able to examine the last CPU state or the last set of alert information to understand why the system has reset. + +The enable for such debug capture can be locked such that it never captures. + +### Alert Information + +The alert information register contains the value of the alert crash dump prior to a triggered reset. +Since this information differs in length between system implementation, the alert information register only displays 32-bits at a time. +The [`ALERT_INFO_ATTR`](registers.md#alert_info_attr) register indicates how many 32-bit data segments must be read. + +To enable alert crash dump capture, set [`ALERT_INFO_CTRL.EN`](registers.md#alert_info_ctrl) to 1. +Once the system has reset, check [`ALERT_INFO_ATTR.CNT_AVAIL`](registers.md#alert_info_attr) for how many reads need to be done. +Set [`ALERT_INFO_CTRL.INDEX`](registers.md#alert_info_ctrl) to the desired segment, and then read the output from [`ALERT_INFO`](registers.md#alert_info). + +### CPU Information + +The CPU information register contains the value of the CPU state prior to a triggered reset. +Since this information differs in length between system implementation, the information register only displays 32-bits at a time. + +For more details on the CPU dump details, please see [crash dump](../../rv_core_ibex/README.md#crash-dump-collection). + +The [`CPU_INFO_ATTR`](registers.md#cpu_info_attr) register indicates how many 32-bit data segments must be read. +Software then simply needs to write in [`CPU_INFO_CTRL.INDEX`](registers.md#cpu_info_ctrl) which segment it wishes and then read out the [`CPU_INFO`](registers.md#cpu_info) register. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/README.md new file mode 100644 index 00000000000..5d7248d9497 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/README.md @@ -0,0 +1,121 @@ +# RSTMGR DV document + +* **DV** + * Verify all RSTMGR IP features by running dynamic simulations with a SV/UVM based testbench + * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules +* **FPV** + * Verify TileLink device protocol compliance with an SVA based testbench + +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../doc/project_governance/development_stages.md) +* [Simulation results](https://reports.opentitan.org/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/latest/report.html) + +For detailed information on RSTMGR design features, please see the [RSTMGR HWIP technical specification](../README.md). + +RSTMGR testbench has been constructed based on the [CIP testbench architecture](../../../../dv/sv/cip_lib/README.md). + +![Block diagram](./doc/tb.svg) + +The top level testbench is located at [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tb.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tb.sv). +It instantiates the RSTMGR DUT module [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr.sv). +In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`: +* [Clock and reset interface](../../../../dv/sv/common_ifs/README.md) +* [TileLink host interface](../../../../dv/sv/tl_agent/README.md) +* RSTMGR interface [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_if.sv) +* Alerts ([`alert_esc_if`](../../../../dv/sv/alert_esc_agent/README.md)) + +The following utilities provide generic helper tasks and functions to perform activities that are common across the project: +* [dv_utils_pkg](../../../../dv/sv/dv_utils/README.md) +* [csr_utils_pkg](../../../../dv/sv/csr_utils/README.md) + +All common types and methods defined at the package level can be found in +`rstmgr_env_pkg`. Some of them in use are: +```systemverilog + typedef logic [NumSwResets-1:0] sw_rst_t; + typedef logic [$bits(alert_handler_pkg::alert_crashdump_t)-1:0] linearized_alert_dump_t; + typedef virtual pwrmgr_rstmgr_sva_if #(.CHECK_RSTREQS(0)) parameterized_pwrmgr_rstmgr_sva_vif; +``` +The RSTMGR testbench instantiates (already handled in CIP base env) [tl_agent](../../../../dv/sv/tl_agent/README.md). +This provides the ability to drive and independently monitor random traffic via the TL host interface into the RSTMGR device. + +RSTMGR testbench instantiates (already handled in CIP base env) [alert_agents](../../../../dv/sv/alert_esc_agent/README.md): +[list alert names]. +The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in RSTMGR device. + +The RSTMGR RAL model is created with the [`ralgen`](../../../../dv/tools/ralgen/README.md) FuseSoC generator script automatically when the simulation is at the build stage. + +It can be created manually by invoking [`regtool`](../../../../../util/reggen/doc/setup_and_use.md). + +The following test sequences and covergroups are described in more detail in the testplan at `hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/data/rstmgr_testplan.hjson`, and also included [below](#testplan). + +This IP is only reset via the `por_n_i` input, and by `scan_rst_ni` qualified by `scanmode_i` being active. +The regular `rst_ni` input is connected to its own `resets_o.rst_por_io_div4_n[0]` output, so the reset output from `clk_rst_if` is not connected. +Similarly, all reset outputs from other `clk_rst_if` instances are ignored, and only their clock output is used. +This is consistent with this IP being in charge of all derived resets in the chip. + +Besides the POR resets above, the test sequences mostly assert various reset requests from pwrmgr and trigger resets vir RESET_REQ CSR. +Alert and CPU dump info is randomized and checked on resets. + +The test sequences reside in [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib). +All test sequences are extended from `rstmgr_base_vseq`, which is extended from `cip_base_vseq` and serves as a starting point. +It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call. +Some of the most commonly used tasks / functions are as follows: +* task `wait_for_cpu_out_of_reset`: + Waits for the `resets_o.rst_sys_n[1]` output to go high, indicating the CPU is out of reset and CSRs can be accessed. +* task `check_cpu_dump_info`: + Reads and compares each field in the `cpu_info` CSR against the given cpu dump. +* task `check_software_reset_csr_and_pins`: + Reads and compares the `sw_rst_ctrl_n` CSR and the output reset ports against the given value. + +Other sequences follow: +* `rstmgr_smoke_vseq` tests the rstmgr through software initiated low power, peripheral reset, ndm reset, and software initiated resets. +* `rstmgr_reset_stretcher_vseq` tests the `resets_o.rst_por_aon_n[0]` output is asserted after 32 stable cycles of `ast_i.aon_pok`. +* `rstmgr_sw_rst_vseq` tests the functionality provided by the `sw_rst_regwen` and `sw_rst_ctrl_n`. +* `rstmgr_reset_info_vseq` tests the `reset_info` CSR contents correspond to the different resets. +* `rstmgr_cpu_info_vseq` tests the `cpu_info` CSR contents capture to the `cpu_dump_i` present at the time of a reset. +* `rstmgr_alert_info_vseq` tests the `alert_info` CSR contents capture to the `alert_dump_i` present at the time of a reset. + +To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. +The following covergroups have been developed to prove that the test intent has been adequately met: +* `reset_stretcher_cg` +* `alert_info_cg` +* `cpu_info_cg` +* `alert_info_capture_cg` +* `cpu_info_capture_cg` +* `sw_rst_cg` + +Most self checking is done using SVA, and via explicit CSR reads. +The latter are described in the testplan. + +* TLUL assertions: The `tb/rstmgr_bind.sv` file binds the `tlul_assert` [assertions](../../../../ip/tlul/doc/TlulProtocolChecker.md) to the IP to ensure TileLink interface protocol compliance. +* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset. +* Response to pwrmgr's `rst_lc_req` and `rst_sys_req` inputs: these trigger transitions in `rst_lc_src_n` and `rst_sys_rst_n` outputs. + Checked via SVAs in [`hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv). +* Response to `cpu_i.ndmreset_req` input: after it is asserted, rstmgr's `rst_sys_src_n` should go active. + Checked via SVA in [`hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/pwrmgr/dv/sva/pwrmgr_rstmgr_sva_if.sv). +* Resets cascade hierarchically per [Reset Topology](../doc/theory_of_operation.md#reset-topology). + Checked via SVA in [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv). +* POR must be active for at least 32 consecutive cycles before going inactive before output resets go inactive. + Checked via SVA in [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv). +* The scan reset `scan_rst_ni` qualified by `scanmode_i` triggers all cascaded resets that `por_n_i` does. + Checked via SVA in [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv). +* Software resets to peripherals also cascade hierarchically. + Checked via SVA in [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv). +* The output `rst_en_o` for alert_handler tracks their corresponding resets. + Checked via SVA in both [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv) and [`hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv`](https://github.com/lowRISC/opentitan/blob/master/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv). +* The `alert` and `cpu_info_attr` indicate the number of 32-bit words needed to capture their inputs. + Checked via SVA in `hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv`. + +The rstmgr_cnsty_chk module is a D2S component. +It depends on very specific timing, and requires tampering stimulus to verify its functionality. +It has its own separate dv environment and tests at `hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk`. +It is excluded from coverage for the rstmgr dv tests. + +We are using our in-house developed [regression tool](../../../../../util/dvsim/README.md) for building and running our tests and regressions. +Please take a look at the link for detailed information on the usage, capabilities, features and known issues. +Here's how to run a smoke test: +```console +$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson -i rstmgr_smoke +``` + +[Testplan](../data/rstmgr_testplan.hjson) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_cov_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_cov_bind.sv new file mode 100644 index 00000000000..03781409cc6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_cov_bind.sv @@ -0,0 +1,13 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// Reset manager coverage bindings for multi bus input +module rstmgr_cov_bind; + // sec cm coverage bind + bind rstmgr cip_mubi_cov_if #(.Width(prim_mubi_pkg::MuBi4Width)) u_scanmode_mubi_cov_if ( + .rst_ni (rst_ni), + .mubi (scanmode_i) + ); +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_cover.cfg b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_cover.cfg new file mode 100644 index 00000000000..7dc7cd2f1dc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_cover.cfg @@ -0,0 +1,9 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Remove rstmgr_cnsty_chk module tree since it is a pre-verified sub-module. +-moduletree rstmgr_cnsty_chk +begin tgl + +module rstmgr_cnsty_chk +end diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_tgl_excl.cfg b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_tgl_excl.cfg new file mode 100644 index 00000000000..fa52799c295 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_tgl_excl.cfg @@ -0,0 +1,34 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +//====================================================================== +// This file contains outputs of rstmgr tied to constants. +//====================================================================== + +-module_node rstmgr resets_o.rst_por_n[Domain0Sel] +-module_node rstmgr rst_en_o.por[Domain0Sel] +-module_node rstmgr resets_o.rst_por_io_n[Domain0Sel] +-module_node rstmgr rst_en_o.por_io[Domain0Sel] +-module_node rstmgr resets_o.rst_por_io_div2_n[Domain0Sel] +-module_node rstmgr rst_en_o.por_io_div2[Domain0Sel] +-module_node rstmgr resets_o.rst_por_io_div4_n[Domain0Sel] +-module_node rstmgr rst_en_o.por_io_div4[Domain0Sel] +-module_node rstmgr resets_o.rst_lc_aon_n[Domain0Sel] +-module_node rstmgr rst_en_o.lc_aon[Domain0Sel] +-module_node rstmgr resets_o.rst_lc_io_n[Domain0Sel] +-module_node rstmgr rst_en_o.lc_io[Domain0Sel] +-module_node rstmgr resets_o.rst_lc_io_div2_n[Domain0Sel] +-module_node rstmgr rst_en_o.lc_io_div2[Domain0Sel] +-module_node rstmgr resets_o.rst_sys_n[DomainAonSel] +-module_node rstmgr rst_en_o.sys[DomainAonSel] +-module_node rstmgr resets_o.rst_sys_n[Domain0Sel] +-module_node rstmgr rst_en_o.sys[Domain0Sel] +-module_node rstmgr resets_o.rst_sys_io_div4_n[Domain0Sel] +-module_node rstmgr rst_en_o.sys_io_div4[Domain0Sel] +-module_node rstmgr resets_o.rst_spi_device_n[DomainAonSel] +-module_node rstmgr rst_en_o.spi_device[DomainAonSel] +-module_node rstmgr resets_o.rst_spi_host0_n[DomainAonSel] +-module_node rstmgr rst_en_o.spi_host0[DomainAonSel] +-module_node rstmgr resets_o.rst_i2c0_n[DomainAonSel] +-module_node rstmgr rst_en_o.i2c0[DomainAonSel] diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el new file mode 100644 index 00000000000..2426c55284a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/cov/rstmgr_unr_excl.el @@ -0,0 +1,88 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Generated UNR file from Synopsys UNR tool with D2S rstmgr_cnsty_chk module +// excluded. +// +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Tue Jan 17 12:16:09 2023 +// ExclMode: default +//================================================== +CHECKSUM: "258095983 1288805244" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_i2c2_n [0] "logic resets_o.rst_i2c2_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_i2c1_n [0] "logic resets_o.rst_i2c1_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_i2c1_n [0] "logic resets_o.rst_i2c1_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_i2c0_n [0] "logic resets_o.rst_i2c0_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_i2c0_n [0] "logic resets_o.rst_i2c0_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_usb_aon_n [0] "logic resets_o.rst_usb_aon_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_usb_aon_n [0] "logic resets_o.rst_usb_aon_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_usb_n [0] "logic resets_o.rst_usb_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_usb_n [0] "logic resets_o.rst_usb_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_spi_host1_n [0] "logic resets_o.rst_spi_host1_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_spi_host1_n [0] "logic resets_o.rst_spi_host1_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_spi_host0_n [0] "logic resets_o.rst_spi_host0_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_spi_host0_n [0] "logic resets_o.rst_spi_host0_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_spi_device_n [0] "logic resets_o.rst_spi_device_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_spi_device_n [0] "logic resets_o.rst_spi_device_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_sys_io_div4_n [1] "logic resets_o.rst_sys_io_div4_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_sys_io_div4_n [1] "logic resets_o.rst_sys_io_div4_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_sys_n [0] "logic resets_o.rst_sys_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_sys_n [0] "logic resets_o.rst_sys_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_lc_aon_n [1] "logic resets_o.rst_lc_aon_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_lc_aon_n [1] "logic resets_o.rst_lc_aon_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_usb_n [1] "logic resets_o.rst_por_usb_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_usb_n [1] "logic resets_o.rst_por_usb_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_io_div4_n [1] "logic resets_o.rst_por_io_div4_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_io_div4_n [1] "logic resets_o.rst_por_io_div4_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_io_div2_n [1] "logic resets_o.rst_por_io_div2_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_io_div2_n [1] "logic resets_o.rst_por_io_div2_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_io_n [1] "logic resets_o.rst_por_io_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_io_n [1] "logic resets_o.rst_por_io_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 0to1 resets_o.rst_por_n [1] "logic resets_o.rst_por_n[1:0]" +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 resets_o.rst_por_n [1] "logic resets_o.rst_por_n[1:0]" +CHECKSUM: "7550215 3610141655" +INSTANCE: tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_rst_chk +ANNOTATION: "VC_COV_UNR" +Toggle 1to0 err_o "logic err_o" +CHECKSUM: "74367784 3785313510" +INSTANCE: tb.dut.u_reg.u_reg_if +ANNOTATION: "VC_COV_UNR" +Condition 18 "3340270436" "(addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error) 1 -1" (5 "01000") diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/doc/tb.svg b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/doc/tb.svg new file mode 100644 index 00000000000..8a1940ac4dc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/doc/tb.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env.core new file mode 100644 index 00000000000..c41f2c9a307 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env.core @@ -0,0 +1,55 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:rstmgr_env:0.1 +description: "RSTMGR DV UVM environment" +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:rstmgr + + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + - lowrisc:darjeeling_no_ibex_ip:rstmgr_pkg + - lowrisc:darjeeling_no_ibex_constants:top_pkg + + files: + - rstmgr_env_pkg.sv + - rstmgr_env_cfg.sv: {is_include_file: true} + - rstmgr_env_cov.sv: {is_include_file: true} + - rstmgr_virtual_sequencer.sv: {is_include_file: true} + - rstmgr_scoreboard.sv: {is_include_file: true} + - rstmgr_env.sv: {is_include_file: true} + - seq_lib/rstmgr_vseq_list.sv: {is_include_file: true} + - seq_lib/rstmgr_base_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_common_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_por_stretcher_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_reset_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_smoke_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_stress_all_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_sw_rst_reset_race_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_sw_rst_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_sec_cm_scan_intersig_mubi_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv: {is_include_file: true} + - seq_lib/rstmgr_leaf_rst_shadow_attack_vseq.sv: {is_include_file: true} + - rstmgr_if.sv + file_type: systemVerilogSource + +generate: + ral: + generator: ralgen + parameters: + name: rstmgr + ip_hjson: ../../data/rstmgr.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + - files_rtl + generate: + - ral diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env.sv new file mode 100644 index 00000000000..733841c6303 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env.sv @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_env extends cip_base_env #( + .CFG_T (rstmgr_env_cfg), + .COV_T (rstmgr_env_cov), + .VIRTUAL_SEQUENCER_T(rstmgr_virtual_sequencer), + .SCOREBOARD_T (rstmgr_scoreboard) +); + `uvm_component_utils(rstmgr_env) + + `uvm_component_new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "aon_clk_rst_vif", cfg.aon_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get aon_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_clk_rst_vif", cfg.io_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_div2_clk_rst_vif", cfg.io_div2_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_div2_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "io_div4_clk_rst_vif", cfg.io_div4_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get io_div4_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual clk_rst_if)::get( + this, "", "main_clk_rst_vif", cfg.main_clk_rst_vif + )) begin + `uvm_fatal(`gfn, "failed to get main_clk_rst_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::get( + this, "", "pwrmgr_rstmgr_sva_vif", cfg.pwrmgr_rstmgr_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get pwrmgr_rstmgr_sva_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual rstmgr_cascading_sva_if)::get( + this, "", "rstmgr_cascading_sva_vif", cfg.rstmgr_cascading_sva_vif + )) begin + `uvm_fatal(`gfn, "failed to get rstmgr_cascading_sva_vif from uvm_config_db") + end + if (!uvm_config_db#(virtual rstmgr_if)::get(this, "", "rstmgr_vif", cfg.rstmgr_vif)) begin + `uvm_fatal(`gfn, "failed to get rstmgr_vif from uvm_config_db") + end + endfunction + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env_cfg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env_cfg.sv new file mode 100644 index 00000000000..92168644602 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env_cfg.sv @@ -0,0 +1,36 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_env_cfg extends cip_base_env_cfg #( + .RAL_T(rstmgr_reg_block) +); + + // This scoreboard handle is used to flag expected errors. + rstmgr_scoreboard scoreboard; + + // ext component cfgs + + `uvm_object_utils_begin(rstmgr_env_cfg) + `uvm_object_utils_end + + `uvm_object_new + + virtual clk_rst_if aon_clk_rst_vif; + virtual clk_rst_if io_clk_rst_vif; + virtual clk_rst_if io_div2_clk_rst_vif; + virtual clk_rst_if io_div4_clk_rst_vif; + virtual clk_rst_if main_clk_rst_vif; + virtual pwrmgr_rstmgr_sva_if #(.PowerDomains(rstmgr_pkg::PowerDomains)) pwrmgr_rstmgr_sva_vif; + virtual rstmgr_cascading_sva_if rstmgr_cascading_sva_vif; + virtual rstmgr_if rstmgr_vif; + + virtual function void initialize(bit [31:0] csr_base_addr = '1); + list_of_alerts = rstmgr_env_pkg::LIST_OF_ALERTS; + super.initialize(csr_base_addr); + + tl_intg_alert_fields[ral.err_code.reg_intg_err] = 1; + m_tl_agent_cfg.max_outstanding_req = 1; + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env_cov.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env_cov.sv new file mode 100644 index 00000000000..15656b8ef5b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env_cov.sv @@ -0,0 +1,104 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +/** + * Covergroups that are dependent on run-time parameters that may be available + * only in build_phase can be defined here + * Covergroups may also be wrapped inside helper classes if needed. + */ + +class rstmgr_sw_rst_cg_wrap; + covergroup sw_rst_cg(string name) with function sample (bit enable, bit rst_n); + option.name = name; + option.per_instance = 1; + + enable_cp: coverpoint enable; + rst_n_cp: coverpoint rst_n; + + sw_rst_cross: cross enable, rst_n; + endgroup + + function new(string name); + sw_rst_cg = new(name); + endfunction + + function void sample (bit enable, bit rst_n); + sw_rst_cg.sample(enable, rst_n); + endfunction +endclass + +class rstmgr_env_cov extends cip_base_env_cov #( + .CFG_T(rstmgr_env_cfg) +); + `uvm_component_utils(rstmgr_env_cov) + + // the base class provides the following handles for use: + // rstmgr_env_cfg: cfg + + rstmgr_sw_rst_cg_wrap sw_rst_cg_wrap[NumSwResets]; + + covergroup alert_info_capture_cg with function sample (logic [7:0] reset_info, logic enable); + reset_info_cp: coverpoint reset_info { + bins reset_info_cp[] = {1, 2, 4, 8, 16, 32, 64, 128}; + bins others = default; + } + enable_cp: coverpoint enable; + capture_cross: cross reset_info_cp, enable_cp; + endgroup + + covergroup alert_info_access_cg with function sample (logic [3:0] index); + index_cp: coverpoint index { + bins valid[] = {[0 : ($bits(alert_crashdump_t) + 31) / 32 - 1]}; + bins others = default; + } + endgroup + + covergroup cpu_info_capture_cg with function sample (logic [7:0] reset_info, logic enable); + reset_info_cp: coverpoint reset_info { + bins reset_info_cp[] = {1, 2, 4, 8, 16, 32, 64, 128}; + bins others = default; + } + enable_cp: coverpoint enable; + capture_cross: cross reset_info_cp, enable_cp; + endgroup + + covergroup cpu_info_access_cg with function sample (logic [3:0] index); + index_cp: coverpoint index { + bins valid[] = {[0 : ($bits(rv_core_ibex_pkg::cpu_crash_dump_t) + 31) / 32 - 1]}; + bins others = default; + } + endgroup + + covergroup reset_stretcher_cg with function sample (byte length, byte count); + length_cp: coverpoint length { + bins lb[8] = {[1 : 40]}; + bins others = default; + } + count_cp: coverpoint count { + bins cb[4] = {[0 : 15]}; + bins others = default; + } + endgroup + + function new(string name, uvm_component parent); + super.new(name, parent); + foreach (sw_rst_cg_wrap[i]) begin + string cg_name = $sformatf("sw_rst_ctrl_n[%0d]", i); + sw_rst_cg_wrap[i] = new(cg_name); + end + alert_info_capture_cg = new(); + alert_info_access_cg = new(); + cpu_info_capture_cg = new(); + cpu_info_access_cg = new(); + reset_stretcher_cg = new(); + endfunction : new + + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + // [or instantiate covergroups here] + // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky + // See cip_base_env_cov for details + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv new file mode 100644 index 00000000000..bbb312c83d9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_env_pkg.sv @@ -0,0 +1,89 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package rstmgr_env_pkg; + // dep packages + import uvm_pkg::*; + import top_pkg::*; + import dv_utils_pkg::*; + import dv_lib_pkg::*; + import tl_agent_pkg::*; + import cip_base_pkg::*; + import dv_base_reg_pkg::*; + import csr_utils_pkg::*; + import rstmgr_ral_pkg::*; + + import prim_mubi_pkg::mubi4_t; + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + + import rstmgr_reg_pkg::NumHwResets; + import rstmgr_reg_pkg::NumSwResets; + + import alert_handler_pkg::alert_crashdump_t; + import rv_core_ibex_pkg::cpu_crash_dump_t; + + import sec_cm_pkg::*; + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // parameters + parameter uint NUM_ALERTS = 2; + parameter string LIST_OF_ALERTS[NUM_ALERTS] = {"fatal_fault", "fatal_cnsty_fault"}; + + // Sorted instances of rstmgr_leaf_rst instances with security checks enabled. + parameter string LIST_OF_LEAFS[] = { + "u_d0_i2c0", + "u_d0_lc", + "u_d0_lc_shadowed", + "u_d0_spi_device", + "u_d0_spi_host0", + "u_daon_lc", + "u_daon_lc_aon", + "u_daon_lc_io", + "u_daon_lc_io_div2", + "u_daon_lc_shadowed", + "u_daon_por", + "u_daon_por_io", + "u_daon_por_io_div2", + "u_daon_por_io_div4", + "u_daon_sys_io_div4" + }; + + // Instances of rstmgr_leaf_rst modules which have a shadow pair. + parameter string LIST_OF_SHADOW_LEAFS[] = { + "u_d0_lc", + "u_d0_lc_io_div4", + "u_daon_lc", + "u_daon_lc_io_div4" + }; + + // types + typedef logic [NumSwResets-1:0] sw_rst_t; + typedef class rstmgr_scoreboard; + + typedef logic [$bits(alert_crashdump_t)-1:0] linearized_alert_dump_t; + + // This is used to capture the values of CSR fields are reset by POR only, so these CSR + // values can be restored to their pre-reset value right after a reset is done and undo + // the dv_base reset clearing them. + typedef struct packed { + logic alert_info_ctrl_en; + logic [3:0] alert_info_ctrl_index; + logic cpu_info_ctrl_en; + logic [3:0] cpu_info_ctrl_index; + } rstmgr_values_of_por_csr_fields_t; + + // functions + + // package sources + `include "rstmgr_env_cfg.sv" + `include "rstmgr_env_cov.sv" + `include "rstmgr_virtual_sequencer.sv" + `include "rstmgr_scoreboard.sv" + `include "rstmgr_env.sv" + `include "rstmgr_vseq_list.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_if.sv new file mode 100644 index 00000000000..07f9cd57b07 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_if.sv @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// clkmgr interface. + +interface rstmgr_if ( + input logic clk_aon, + input logic clk, + input logic rst_n +); + + import rstmgr_env_pkg::*; + import rstmgr_pkg::PowerDomains; + + logic [PowerDomains-1:0] por_n; + + pwrmgr_pkg::pwr_rst_req_t pwr_i; + pwrmgr_pkg::pwr_rst_rsp_t pwr_o; + + prim_mubi_pkg::mubi4_t sw_rst_req_o; + + // cpu related inputs + rstmgr_pkg::rstmgr_cpu_t cpu_i; + + // Interface to alert handler + alert_handler_pkg::alert_crashdump_t alert_dump_i; + + // Interface to cpu crash dump + rv_core_ibex_pkg::cpu_crash_dump_t cpu_dump_i; + + // dft bypass + logic scan_rst_ni; + prim_mubi_pkg::mubi4_t scanmode_i; + + // Reset status for alert handler. + rstmgr_pkg::rstmgr_rst_en_t rst_en_o; + + // reset outputs + rstmgr_pkg::rstmgr_out_t resets_o; + + // Supporting code. + int aon_cycles; + always @(posedge clk_aon) aon_cycles += 1; + + // Internal DUT signals. +`ifndef PATH_TO_DUT + `define PATH_TO_DUT tb.dut +`endif + + logic [7:0] reset_info; + always_comb begin + reset_info = { + `PATH_TO_DUT.u_reg.reset_info_hw_req_qs, + `PATH_TO_DUT.u_reg.reset_info_sw_reset_qs, + `PATH_TO_DUT.u_reg.reset_info_low_power_exit_qs, + `PATH_TO_DUT.u_reg.reset_info_por_qs + }; + end + + logic alert_info_en; + always_comb alert_info_en = `PATH_TO_DUT.reg2hw.alert_info_ctrl.en.q; + + logic cpu_info_en; + always_comb cpu_info_en = `PATH_TO_DUT.reg2hw.cpu_info_ctrl.en.q; + + bit rst_ni_inactive; + always_comb rst_ni_inactive = resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]; +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv new file mode 100644 index 00000000000..ff3e4518d6d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_scoreboard.sv @@ -0,0 +1,312 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_scoreboard extends cip_base_scoreboard #( + .CFG_T(rstmgr_env_cfg), + .RAL_T(rstmgr_reg_block), + .COV_T(rstmgr_env_cov) +); + `uvm_component_utils(rstmgr_scoreboard) + + // local variables + static const string sw_rst_ctrl_n_preffix = "sw_rst_ctrl_n_"; + + // This is used to capture and restore upon a regular reset the CSR values that are reset + // by POR only, since the CIP and lower layers will reset all CSRs. + rstmgr_values_of_por_csr_fields_t por_fields; + + // TLM agent fifos + + // local queues to hold incoming packets pending comparison + + `uvm_component_new + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + cfg.scoreboard = this; + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + // Initial capture to be able to restore after POR. + capture_por_csr_fields(); + fork + monitor_por(); + monitor_capture(); + monitor_tlul_rst(); + join_none + endtask + + // Start coverage collection after the very first POR negedge, since that transition is not + // useful for coverage. + local task monitor_por(); + int stretch_start; + int reset_count; + if (!cfg.en_cov) return; + @(negedge cfg.rstmgr_vif.por_n); + forever + @cfg.rstmgr_vif.por_n begin + if (cfg.rstmgr_vif.por_n == 1'b1) stretch_start = cfg.rstmgr_vif.aon_cycles; + else begin + int stretch_cycles = cfg.rstmgr_vif.aon_cycles - stretch_start; + ++reset_count; + `DV_CHECK_GT(stretch_cycles, 0) + cov.reset_stretcher_cg.sample(stretch_cycles, reset_count); + end + end + endtask + + local task monitor_capture(); + if (!cfg.en_cov) return; + forever + @cfg.rstmgr_vif.reset_info begin + if (cfg.rstmgr_vif.reset_info != '0) begin + cov.alert_info_capture_cg.sample(cfg.rstmgr_vif.reset_info, cfg.rstmgr_vif.alert_info_en); + cov.cpu_info_capture_cg.sample(cfg.rstmgr_vif.reset_info, cfg.rstmgr_vif.cpu_info_en); + end + end + endtask + + // Monitor tlul reset to update csr_utils_pkg::under_reset variable. This is needed + // because the tlul reset in rstmgr is generated internally, unlike any other modules + // where it is controlled by clk_rst_vif. + local task monitor_tlul_rst(); + forever + @cfg.m_tl_agent_cfg.vif.rst_n begin + if (!cfg.m_tl_agent_cfg.vif.rst_n) begin + `uvm_info(`gfn, "tl got reset", UVM_MEDIUM) + under_reset = 1; + end else begin + `uvm_info(`gfn, "tl got out of reset", UVM_MEDIUM) + under_reset = 0; + clear_outstanding_access(); + cfg.clk_rst_vif.wait_clks(1); + restore_por_csr_fields(); + end + end + endtask + + // This converts the trailing digits in a name to a number. + // It is fatal if there are no trailing digits. + local function int get_index_from_multibit_name(string name); + string suffix; + int last_char_index = name.len() - 1; + int i; + for (i = 0; i <= last_char_index; ++i) begin + byte character = name[last_char_index - i]; + if (character < "0" || character > "9") break; + end + `DV_CHECK(i > 0) + suffix = name.substr(last_char_index - i, last_char_index); + return suffix.atoi(); + endfunction + + local function bit blocked_by_regwen(string ral_name); + bit blocked = 0; + + if (ral_name == "alert_info_ctrl") + blocked = `gmv(ral.alert_regwen) == 0; + if (ral_name == "cpu_info_ctrl") + blocked = `gmv(ral.cpu_regwen) == 0; + // And only the various "sw_rst_ctrl_n may be blocked, so ignore all others. + if (uvm_re_match({sw_rst_ctrl_n_preffix, "*"}, ral_name)) + return 0; + case (ral_name[sw_rst_ctrl_n_preffix.len()]) + "0": blocked = `gmv(ral.sw_rst_regwen[0]) == 0; + "1": blocked = `gmv(ral.sw_rst_regwen[1]) == 0; + "2": blocked = `gmv(ral.sw_rst_regwen[2]) == 0; + "3": blocked = `gmv(ral.sw_rst_regwen[3]) == 0; + "4": blocked = `gmv(ral.sw_rst_regwen[4]) == 0; + "5": blocked = `gmv(ral.sw_rst_regwen[5]) == 0; + "6": blocked = `gmv(ral.sw_rst_regwen[6]) == 0; + "7": blocked = `gmv(ral.sw_rst_regwen[7]) == 0; + default: + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", ral_name)) + endcase + `uvm_info(`gfn, $sformatf( + "blocked_by_regwen: csr = %0s is %0sblocked", ral_name, blocked ? "" : "not "), + UVM_MEDIUM) + return blocked; + endfunction + + virtual task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name); + uvm_reg csr; + bit do_read_check = 1'b1; + bit write = item.is_write(); + uvm_reg_addr_t csr_addr = cfg.ral_models[ral_name].get_word_aligned_addr(item.a_addr); + + bit addr_phase_read = (!write && channel == AddrChannel); + bit addr_phase_write = (write && channel == AddrChannel); + bit data_phase_read = (!write && channel == DataChannel); + bit data_phase_write = (write && channel == DataChannel); + + // if access was to a valid csr, get the csr handle + if (csr_addr inside {cfg.ral_models[ral_name].csr_addrs}) begin + csr = cfg.ral_models[ral_name].default_map.get_reg_by_offset(csr_addr); + `DV_CHECK_NE_FATAL(csr, null) + end else begin + `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr)) + end + + // If incoming access is a write to a valid csr and is not blocked by a regwen, make + // updates right away. + if (addr_phase_write) begin + if (!blocked_by_regwen(csr.get_name())) + void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask))); + end + + // process the csr req: + // for write, update local variable and fifo at address phase, + // for read, update prediction at address phase and compare at data phase. + case (csr.get_name()) + // add individual case item for each csr + "alert_test": begin + // Write only. + do_read_check = 1'b0; + end + "reset_req": begin + end + "reset_info": begin + // RW1C. + do_read_check = 1'b0; + end + "alert_regwen": begin + // RW0C. + end + "alert_info_ctrl": begin + // The en bit is cleared by any hardware reset, but other bits are only cleared by POR. + end + "alert_info_attr": begin + // Read only. + do_read_check = 1'b0; + end + "alert_info": begin + // Read only. + do_read_check = 1'b0; + if (cfg.en_cov) begin + cov.alert_info_access_cg.sample(ral.alert_info_ctrl.index.get()); + end + end + "cpu_regwen": begin + // RW0C. + end + "cpu_info_ctrl": begin + // The en bit is cleared by any hardware reset, but other bits are only cleared by POR. + end + "cpu_info_attr": begin + // Read only. + do_read_check = 1'b0; + end + "cpu_info": begin + // Read only. + do_read_check = 1'b0; + if (cfg.en_cov) begin + cov.cpu_info_access_cg.sample(ral.cpu_info_ctrl.index.get()); + end + end + "err_code": begin + // Set by hardware. + do_read_check = 1'b0; + end + default: begin + if (!uvm_re_match({sw_rst_ctrl_n_preffix, "*"}, csr.get_name())) begin + `uvm_info(`gfn, $sformatf("write to %0s with 0x%x", csr.get_name(), item.a_data), + UVM_MEDIUM) + if (cfg.en_cov && addr_phase_write) begin + int i = get_index_from_multibit_name(csr.get_name()); + logic enable = ral.sw_rst_regwen[i].get(); + cov.sw_rst_cg_wrap[i].sample(enable, item.a_data); + end + end else if (!uvm_re_match("sw_rst_regwen_*", csr.get_name())) begin + // RW0C, so check. + end else begin + `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name())) + end + end + endcase + + // On reads, if do_read_check, is set, then check mirrored_value against item.d_data + if (data_phase_read) begin + if (do_read_check) begin + uvm_reg_data_t mirrored_value = csr.get_mirrored_value(); + case (csr.get_name()) + "alert_info_ctrl", + "cpu_info_ctrl": begin + // Override bit 0 since it can be cleared by hardware. + `DV_CHECK_EQ((mirrored_value | 1), (item.d_data | 1), $sformatf( + "reg name: %0s, before masking: mirrored value 0x%x, data read 0x%x", + csr.get_full_name(), mirrored_value, item.d_data)) + end + default: + `DV_CHECK_EQ(mirrored_value, item.d_data, $sformatf( + "reg name: %0s", csr.get_full_name())) + endcase + end + void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ))); + end + endtask + + local function void capture_por_csr_fields(); + por_fields.alert_info_ctrl_en = `gmv(ral.alert_info_ctrl.en); + `uvm_info(`gfn, $sformatf("captured alert_info_ctrl.en 0x%x", por_fields.alert_info_ctrl_en), + UVM_MEDIUM) + por_fields.alert_info_ctrl_index = `gmv(ral.alert_info_ctrl.index); + `uvm_info(`gfn, $sformatf( + "captured alert_info_ctrl.index 0x%x", por_fields.alert_info_ctrl_index), UVM_MEDIUM) + por_fields.cpu_info_ctrl_en = `gmv(ral.cpu_info_ctrl.en); + `uvm_info(`gfn, $sformatf( + "captured cpu_info_ctrl.en 0x%x", por_fields.cpu_info_ctrl_en), UVM_MEDIUM) + por_fields.cpu_info_ctrl_index = `gmv(ral.cpu_info_ctrl.index); + `uvm_info(`gfn, $sformatf( + "captured cpu_info_ctrl.index 0x%x", por_fields.cpu_info_ctrl_index), UVM_MEDIUM) + endfunction + + // Restore the alert and cpu_info_ctrl index values, and the enable bits only on low power reset + // since all other resets clear them. + local task restore_por_csr_fields(); + if (cfg.rstmgr_vif.reset_info[ral.reset_info.low_power_exit.get_lsb_pos()]) begin + `uvm_info(`gfn, $sformatf( + "Restoring alert_info_ctrl.en to 0x%x", por_fields.alert_info_ctrl_en), UVM_MEDIUM) + csr_wr(.ptr(ral.alert_info_ctrl.en), .value(por_fields.alert_info_ctrl_en), .backdoor(1), + .predict(1)); + `uvm_info(`gfn, $sformatf("Restoring cpu_info_ctrl.en to 0x%x", por_fields.cpu_info_ctrl_en), + UVM_MEDIUM) + csr_wr(.ptr(ral.cpu_info_ctrl.en), .value(por_fields.cpu_info_ctrl_en), .backdoor(1), + .predict(1)); + end + `uvm_info(`gfn, $sformatf( + "Restoring alert_info_ctrl.index to 0x%x", por_fields.alert_info_ctrl_index), + UVM_MEDIUM) + csr_wr(.ptr(ral.alert_info_ctrl.index), .value(por_fields.alert_info_ctrl_index), .backdoor(1), + .predict(1)); + `uvm_info(`gfn, $sformatf( + "After restoring alert_info_ctrl mirrored value 0x%x", `gmv(ral.alert_info_ctrl)), + UVM_MEDIUM) + `uvm_info(`gfn, $sformatf( + "Restoring cpu_info_ctrl.index to 0x%x", por_fields.cpu_info_ctrl_index), UVM_MEDIUM) + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(por_fields.cpu_info_ctrl_index), .backdoor(1), + .predict(1)); + `uvm_info(`gfn, $sformatf( + "After restoring cpu_info_ctrl mirrored value 0x%x", `gmv(ral.cpu_info_ctrl)), + UVM_MEDIUM) + endtask + + // There are a handful of registers that are reset on POR only, but the dv_base classes + // will clear all mirrored values on reset. Rather than changing all that code to handle + // resets more accurately here we just capture the mirrored values of all such CSRs + // before reset, and apply them back once reset is handled. It would be really clean if + // they could be restored here right after reset, but restore is a task so it cannot be + // called within a function. + virtual function void reset(string kind = "HARD"); + capture_por_csr_fields(); + super.reset(kind); + // reset local fifos queues and variables + endfunction + + function void check_phase(uvm_phase phase); + super.check_phase(phase); + // post test checks - ensure that all local fifos and queues are empty + endfunction + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_virtual_sequencer.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_virtual_sequencer.sv new file mode 100644 index 00000000000..f81afdab42b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/rstmgr_virtual_sequencer.sv @@ -0,0 +1,14 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_virtual_sequencer extends cip_base_virtual_sequencer #( + .CFG_T(rstmgr_env_cfg), + .COV_T(rstmgr_env_cov) +); + `uvm_component_utils(rstmgr_virtual_sequencer) + + + `uvm_component_new + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv new file mode 100644 index 00000000000..b3b6256e202 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv @@ -0,0 +1,550 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_base_vseq extends cip_base_vseq #( + .RAL_T (rstmgr_reg_block), + .CFG_T (rstmgr_env_cfg), + .COV_T (rstmgr_env_cov), + .VIRTUAL_SEQUENCER_T(rstmgr_virtual_sequencer) +); + + `uvm_object_utils(rstmgr_base_vseq) + + `uvm_object_new + + // Set clock frequencies per spec, except the aon is 200kHZ, which is + // too slow and could slow testing down for no good reason. + localparam int AON_FREQ_MHZ = 3; + localparam int IO_FREQ_MHZ = 1000; + localparam int IO_DIV2_FREQ_MHZ = 500; + localparam int IO_DIV4_FREQ_MHZ = 250; + localparam int MAIN_FREQ_MHZ = 1000; + + // POR needs to be stable not less than 32 clock cycles, plus some extra, before it + // propagates to the rest of the logic. + localparam int POR_CLK_CYCLES = 40; + + // This is only used for the various clocks to start ticking, so can be any small number. + localparam int BOGUS_RESET_CLK_CYCLES = 2; + + // Some extra cycles from reset going inactive before the CPU's reset goes inactive. + localparam int CPU_RESET_CLK_CYCLES = 10; + + // The different types of reset. + typedef enum int { + ResetPOR, + ResetScan, + ResetLowPower, + ResetSw, + ResetHw, + ResetLast + } reset_e; + + // The reset_info adds POR and low power to TotalResetWidth. + typedef logic [pwrmgr_pkg::TotalResetWidth+2-1:0] reset_info_t; + typedef logic [pwrmgr_pkg::HwResetWidth-1:0] rstreqs_t; + + rand sw_rst_t sw_rst_regwen; + rand sw_rst_t sw_rst_ctrl_n; + + bit reset_once; + + rand cpu_crash_dump_t cpu_dump; + rand alert_crashdump_t alert_dump; + + rand rstreqs_t rstreqs; + + rand logic scan_rst_ni; + constraint scan_rst_ni_c {scan_rst_ni == 1;} + + // Various cycles for delaying stimulus. + rand int rst_to_req_cycles; + constraint rst_to_req_cycles_c {rst_to_req_cycles inside {[1 : 6]};} + + rand int release_lc_to_release_sys_cycles; + constraint release_lc_to_release_sys_cycles_c { + release_lc_to_release_sys_cycles inside {[1 : 10]}; + } + + rand int scan_rst_cycles; + constraint scan_rst_cycles_c {scan_rst_cycles inside {[0 : 4]};} + + rand int scanmode_cycles; + constraint scanmode_cycles_c {scanmode_cycles inside {[0 : 4]};} + + rand int lowpower_rst_cycles; + constraint lowpower_rst_cycles_c {lowpower_rst_cycles inside {[0 : 20]};} + + rand int sw_rst_cycles; + constraint sw_rst_cycles_c {sw_rst_cycles inside {[0 : 20]};} + + rand int hw_rst_cycles; + constraint hw_rst_cycles_c {hw_rst_cycles inside {[0 : 20]};} + + rand int reset_us; + constraint reset_us_c {reset_us inside {[1 : 4]};} + + bit do_rstmgr_init = 1'b1; + + mubi4_t scanmode; + int scanmode_on_weight = 8; + + // This is used to randomize the delays for the clocks to start and stop. + typedef struct { + bit [5:0] io_delay; + bit [5:0] io_div2_delay; + bit [5:0] io_div4_delay; + bit [5:0] main_delay; + } clock_delays_in_ns_t; + + // What to expect when testing resets. + string reset_name[reset_e] = '{ + ResetPOR: "POR", + ResetScan: "scan", + ResetLowPower: "low power", + ResetSw: "software", + ResetHw: "hardware" + }; + + function int get_reset_code(reset_e reset, rstreqs_t rstreqs); + case (reset) + ResetPOR, ResetScan: return 1 << ral.reset_info.por.get_lsb_pos(); + ResetLowPower: return 1 << ral.reset_info.low_power_exit.get_lsb_pos(); + ResetSw: return 1 << ral.reset_info.sw_reset.get_lsb_pos(); + ResetHw: return rstreqs << ral.reset_info.hw_req.get_lsb_pos(); + default: `uvm_error(`gfn, $sformatf("Unexpected reset code %0d", reset)) + endcase + endfunction + + function void post_randomize(); + scanmode = get_rand_mubi4_val(scanmode_on_weight, 4, 4); + endfunction + + local function void update_scanmode(prim_mubi_pkg::mubi4_t value); + cfg.rstmgr_vif.scanmode_i = value; + endfunction + + local function void update_scan_rst_n(logic value); + cfg.rstmgr_vif.scan_rst_ni = value; + endfunction + + local function void set_pwrmgr_rst_reqs(logic rst_lc_req, logic rst_sys_req); + `uvm_info(`gfn, $sformatf("Setting pwr_i lc_req=%x sys_req=%x", rst_lc_req, rst_sys_req), + UVM_MEDIUM) + cfg.rstmgr_vif.pwr_i.rst_lc_req = {rstmgr_pkg::PowerDomains{rst_lc_req}}; + cfg.rstmgr_vif.pwr_i.rst_sys_req = {rstmgr_pkg::PowerDomains{rst_sys_req}}; + endfunction + + local function void set_rstreqs(rstreqs_t rstreqs); + cfg.rstmgr_vif.pwr_i.rstreqs = rstreqs; + endfunction + + local function void add_rstreqs(rstreqs_t rstreqs); + cfg.rstmgr_vif.pwr_i.rstreqs |= rstreqs; + `uvm_info(`gfn, $sformatf("Updating rstreqs to 0x%x", cfg.rstmgr_vif.pwr_i.rstreqs), UVM_MEDIUM) + endfunction + + local function void set_reset_cause(pwrmgr_pkg::reset_cause_e reset_cause); + cfg.rstmgr_vif.pwr_i.reset_cause = reset_cause; + endfunction + + static function logic is_running_sequence(string seq_name); + string actual_sequence = "none"; + // Okay to ignore return value since the default won't match. + void'($value$plusargs("UVM_TEST_SEQ=%0s", actual_sequence)); + return actual_sequence.compare(seq_name) == 0; + endfunction + + virtual protected task check_reset_info(logic [TL_DW-1:0] expected_value, + string msg = "reset_info mismatch"); + csr_rd_check(.ptr(ral.reset_info), .compare_value(expected_value), .err_msg(msg)); + endtask + + local function void set_cpu_dump_info(cpu_crash_dump_t cpu_dump); + `uvm_info(`gfn, $sformatf("Setting cpu_dump_i to %p", cpu_dump), UVM_MEDIUM) + cfg.rstmgr_vif.cpu_dump_i = cpu_dump; + endfunction + + local task check_cpu_dump_info(cpu_crash_dump_t cpu_dump); + `uvm_info(`gfn, "Checking cpu_info", UVM_MEDIUM) + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(7)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.prev_valid), + .err_msg("checking previous_valid")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(6)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.prev_exception_pc), + .err_msg("checking previous exception_pc")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(5)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.prev_exception_addr), + .err_msg("checking previous exception_addr")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(4)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.current_pc), + .err_msg("checking current current_pc")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(3)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.next_pc), + .err_msg("checking current next_pc")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(2)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.last_data_addr), + .err_msg("checking current last_data_addr")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(1)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.exception_pc), + .err_msg("checking current exception_pc")); + csr_wr(.ptr(ral.cpu_info_ctrl.index), .value(0)); + csr_rd_check(.ptr(ral.cpu_info), .compare_value(cpu_dump.current.exception_addr), + .err_msg("checking current exception_addr")); + + endtask + + local function void set_alert_dump_info(alert_crashdump_t alert_dump); + `uvm_info(`gfn, $sformatf( + "Setting alert_dump_i to 0x%x", linearized_alert_dump_t'({>>{alert_dump}})), + UVM_MEDIUM) + cfg.rstmgr_vif.alert_dump_i = alert_dump; + endfunction + + local task check_alert_dump_info(alert_crashdump_t alert_dump); + localparam int DumpWidth = $bits(alert_dump); + localparam int WordWidth = 32; + logic [DumpWidth-1:0] linear_dump = {>>{alert_dump}}; + int i; + `uvm_info(`gfn, "Checking alert_info", UVM_MEDIUM) + for (i = 0; i + WordWidth <= DumpWidth; i += WordWidth) begin + csr_wr(.ptr(ral.alert_info_ctrl.index), .value(i / WordWidth)); + csr_rd_check(.ptr(ral.alert_info), .compare_value(linear_dump[i+:WordWidth]), + .err_msg($sformatf("checking alert_info bits %0d:%0d", i + 31, i))); + end + if (i < DumpWidth) begin + logic [(DumpWidth % 32) - 1:0] word = linear_dump >> i; + csr_wr(.ptr(ral.alert_info_ctrl.index), .value(i / WordWidth)); + csr_rd_check(.ptr(ral.alert_info), .compare_value(word), + .err_msg($sformatf("checking alert_info bits %0d:%0d", DumpWidth - 1, i))); + end + endtask + + virtual protected task set_alert_info_for_capture(alert_crashdump_t alert_dump, logic enable); + set_alert_dump_info(alert_dump); + `uvm_info(`gfn, $sformatf("%0sabling alert_info capture", (enable ? "En" : "Dis")), UVM_MEDIUM) + csr_wr(.ptr(ral.alert_info_ctrl.en), .value(enable)); + endtask + + virtual protected task set_cpu_info_for_capture(cpu_crash_dump_t cpu_dump, logic enable); + set_cpu_dump_info(cpu_dump); + `uvm_info(`gfn, $sformatf("%0sabling cpu_info capture", (enable ? "En" : "Dis")), UVM_MEDIUM) + csr_wr(.ptr(ral.cpu_info_ctrl.en), .value(enable)); + endtask + + virtual protected task set_alert_and_cpu_info_for_capture(alert_crashdump_t alert_dump, + cpu_crash_dump_t cpu_dump); + set_alert_info_for_capture(alert_dump, 1'b1); + set_cpu_info_for_capture(cpu_dump, 1'b1); + endtask + + virtual protected task check_alert_info_after_reset(alert_crashdump_t alert_dump, logic enable); + csr_rd_check(.ptr(ral.alert_info_ctrl.en), .compare_value(enable), + .err_msg($sformatf("Expected alert info capture enable %b", enable))); + csr_wr(.ptr(ral.alert_info_ctrl.en), .value(enable)); + check_alert_dump_info(alert_dump); + endtask + + virtual protected task check_cpu_info_after_reset(cpu_crash_dump_t cpu_dump, logic enable); + csr_rd_check(.ptr(ral.cpu_info_ctrl.en), .compare_value(enable), + .err_msg($sformatf("Expected cpu info capture enable %b", enable))); + csr_wr(.ptr(ral.cpu_info_ctrl.en), .value(enable)); + check_cpu_dump_info(cpu_dump); + endtask + + // Checks both alert and cpu_info_ctrl.en, and their _info contents. + // This is tricky: both ctrl.en fields don't necessarily match the mirrored value since the + // hardware may update them on most resets. This can cause the subsequent writes to the .index + // field to overwrite the .en field. To make things simpler, after checking .en's expected + // value we write it to update the mirrored value. + virtual protected task check_alert_and_cpu_info_after_reset( + alert_crashdump_t alert_dump, cpu_crash_dump_t cpu_dump, logic enable); + check_alert_info_after_reset(alert_dump, enable); + check_cpu_info_after_reset(cpu_dump, enable); + endtask + + virtual protected task clear_alert_and_cpu_info(); + set_alert_and_cpu_info_for_capture('0, '0); + send_sw_reset(); + cfg.io_div4_clk_rst_vif.wait_clks(20); // # of lc reset cycles measured from waveform + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(0)); + endtask + + virtual protected task clear_sw_rst_ctrl_n(); + const sw_rst_t sw_rst_all_ones = '1; + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value(sw_rst_all_ones)); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(sw_rst_all_ones), + .err_msg("Expected sw_rst_ctrl_n to be set")); + endtask + + virtual protected task clear_sw_rst_ctrl_n_per_entry(int entry); + csr_wr(.ptr(ral.sw_rst_ctrl_n[entry]), .value(1'b1)); + csr_rd_check(.ptr(ral.sw_rst_ctrl_n[entry]), .compare_value(1'b1), + .err_msg($sformatf("Expected sw_rst_ctrl_n[%0d] to be set", entry))); + endtask + + virtual protected task check_sw_rst_regwen(sw_rst_t expected_regwen); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_regwen), .compare_value(expected_regwen), + .err_msg("Mismatching sw_rst_regwen")); + endtask + + // Stimulate and check sw_rst_ctrl_n with a given sw_rst_regwen setting. + // Exit when a reset is detected or the sequence would be invalid and may get stuck. + virtual protected task check_sw_rst_ctrl_n(sw_rst_t sw_rst_ctrl_n, sw_rst_t sw_rst_regwen, + bit erase_ctrl_n); + sw_rst_t exp_ctrl_n = ~sw_rst_regwen | sw_rst_ctrl_n; + + `uvm_info(`gfn, $sformatf( + "Setting sw_rst_ctrl_n to 0x%0x with regwen 0x%x, expect 0x%x", + sw_rst_ctrl_n, + sw_rst_regwen, + exp_ctrl_n + ), UVM_MEDIUM) + foreach (ral.sw_rst_ctrl_n[i]) begin + if (under_reset) return; + csr_wr(.ptr(ral.sw_rst_ctrl_n[i]), .value(sw_rst_ctrl_n[i])); + if (under_reset) return; + csr_rd_check(.ptr(ral.sw_rst_ctrl_n[i]), .compare_value(exp_ctrl_n[i]), + .err_msg($sformatf("Mismatch for bit %0d", i))); + end + if (erase_ctrl_n && !under_reset) clear_sw_rst_ctrl_n(); + endtask + + virtual protected task check_sw_rst_ctrl_n_per_entry( + sw_rst_t sw_rst_ctrl_n, sw_rst_t sw_rst_regwen, bit erase_ctrl_n, int entry); + sw_rst_t exp_ctrl_n; + + `uvm_info(`gfn, $sformatf("Set sw_rst_ctrl_n[%0d] to 0x%0x", entry, sw_rst_ctrl_n), UVM_MEDIUM) + csr_wr(.ptr(ral.sw_rst_ctrl_n[entry]), .value(sw_rst_ctrl_n[entry])); + // And check that the reset outputs match the actual ctrl_n settings. + // Allow for domain crossing delay. + cfg.io_div2_clk_rst_vif.wait_clks(3); + exp_ctrl_n = ~sw_rst_regwen | sw_rst_ctrl_n; + `uvm_info(`gfn, $sformatf( + "regwen=%b, ctrl_n=%b, expected=%b", sw_rst_regwen, sw_rst_ctrl_n, exp_ctrl_n), + UVM_MEDIUM) + csr_rd_check(.ptr(ral.sw_rst_ctrl_n[entry]), .compare_value(exp_ctrl_n[entry]), + .err_msg($sformatf("Expected enabled updates in sw_rst_ctrl_n[%0d]", entry))); + if (erase_ctrl_n) clear_sw_rst_ctrl_n_per_entry(entry); + endtask + + local task control_all_clocks(bit enable); + // Randomize the delays for each clock turning on or off. + clock_delays_in_ns_t delays; + `DV_CHECK_STD_RANDOMIZE_FATAL(delays) + if (enable) fork + #(delays.io_delay * 1ns) cfg.io_clk_rst_vif.start_clk(); + #(delays.io_div2_delay * 1ns) cfg.io_div2_clk_rst_vif.start_clk(); + #(delays.io_div4_delay * 1ns) cfg.io_div4_clk_rst_vif.start_clk(); + #(delays.main_delay * 1ns) cfg.main_clk_rst_vif.start_clk(); + join else fork + #(delays.io_delay * 1ns) cfg.io_clk_rst_vif.stop_clk(); + #(delays.io_div2_delay * 1ns) cfg.io_div2_clk_rst_vif.stop_clk(); + #(delays.io_div4_delay * 1ns) cfg.io_div4_clk_rst_vif.stop_clk(); + #(delays.main_delay * 1ns) cfg.main_clk_rst_vif.stop_clk(); + join + endtask + + // Happens with hardware resets. + local task reset_start(pwrmgr_pkg::reset_cause_e reset_cause); + `uvm_info(`gfn, $sformatf("Starting pwrmgr inputs for %0s request", reset_cause.name()), + UVM_MEDIUM) + set_reset_cause(reset_cause); + // These lag the reset requests since they are set after the pwrmgr fast fsm has made some + // state transitions. + cfg.io_div4_clk_rst_vif.wait_clks(rst_to_req_cycles); + set_pwrmgr_rst_reqs(.rst_lc_req('1), .rst_sys_req('1)); + cfg.clk_rst_vif.stop_clk(); + if (reset_cause == pwrmgr_pkg::LowPwrEntry) begin + control_all_clocks(.enable(0)); + end + endtask + + protected task wait_till_active(); + // And wait for the main reset to be done. + `DV_WAIT(cfg.rstmgr_vif.rst_ni_inactive, "Time-out waiting for rst_ni becoming inactive"); + // And wait a few cycles for settling before allowing the sequences to start. + cfg.io_div4_clk_rst_vif.wait_clks(8); + endtask + + protected task reset_done(); + `uvm_info(`gfn, "Releasing reset", UVM_LOW) + update_scanmode(prim_mubi_pkg::MuBi4False); + update_scan_rst_n(1'b1); + if (cfg.rstmgr_vif.pwr_i.reset_cause == pwrmgr_pkg::LowPwrEntry) begin + control_all_clocks(.enable(1)); + end + cfg.clk_rst_vif.start_clk(); + cfg.io_div4_clk_rst_vif.wait_clks(10); + set_reset_cause(pwrmgr_pkg::ResetNone); + set_pwrmgr_rst_reqs(.rst_lc_req('0), .rst_sys_req('1)); + cfg.io_div4_clk_rst_vif.wait_clks(release_lc_to_release_sys_cycles); + set_pwrmgr_rst_reqs(.rst_lc_req('0), .rst_sys_req('0)); + set_rstreqs(0); + wait_till_active(); + `uvm_info(`gfn, "Reset done", UVM_MEDIUM) + endtask + + // Sends either an external hardware reset request, setting the possibly different + // rstreqs bits at different times. It optionally completes the reset. + virtual protected task send_hw_reset(rstreqs_t rstreqs, logic complete_it = 1); + `uvm_info(`gfn, $sformatf("Sending hw reset with 0b%0b", rstreqs), UVM_LOW) + reset_start(pwrmgr_pkg::HwReq); + fork + begin : isolation_fork + foreach (rstreqs[i]) begin : loop + if (rstreqs[i]) begin + fork + automatic int index = i; + automatic bit [2:0] cycles; + `DV_CHECK_STD_RANDOMIZE_FATAL(cycles) + cfg.io_div4_clk_rst_vif.wait_clks(cycles); + add_rstreqs(rstreqs & (1 << index)); + join_none + end + end : loop + wait fork; + end : isolation_fork + join + if (complete_it) reset_done(); + endtask + + virtual protected task send_lowpower_reset(bit complete_it = 1); + `uvm_info(`gfn, "Sending low power reset", UVM_LOW) + reset_start(pwrmgr_pkg::LowPwrEntry); + if (complete_it) reset_done(); + endtask + + + // Lead with scan_rst active to avoid some derived sequence changing scanmode_i in such + // a way it defeats this reset. + virtual protected task send_scan_reset(bit complete_it = 1); + `uvm_info(`gfn, "Sending scan reset", UVM_MEDIUM) + fork + begin + cfg.io_div4_clk_rst_vif.wait_clks(scan_rst_cycles); + update_scan_rst_n(1'b0); + end + begin + cfg.io_div4_clk_rst_vif.wait_clks(scanmode_cycles); + update_scanmode(prim_mubi_pkg::MuBi4True); + end + join + reset_start(pwrmgr_pkg::HwReq); + + // The clocks are turned off, so wait in time units. + #(reset_us * 1us); + if (complete_it) reset_done(); + endtask + + // Requests a sw reset. It is cleared by hardware once the reset is taken. + virtual protected task send_sw_reset(bit complete_it = 1); + `uvm_info(`gfn, "Sending sw reset", UVM_LOW) + reset_start(pwrmgr_pkg::HwReq); + #(reset_us * 1us); + if (complete_it) reset_done(); + endtask + + virtual task dut_init(string reset_kind = "HARD"); + if (do_rstmgr_init) rstmgr_init(); + super.dut_init(); + endtask + + virtual task dut_shutdown(); + // No checks seem needed. + endtask + + local task start_clocks(); + control_all_clocks(.enable(1)); + fork + cfg.aon_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + cfg.io_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + cfg.io_div2_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + cfg.io_div4_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + cfg.main_clk_rst_vif.apply_reset(.reset_width_clks(BOGUS_RESET_CLK_CYCLES)); + join + endtask + + protected task por_reset_done(bit complete_it); + cfg.rstmgr_vif.por_n = '1; + reset_start(pwrmgr_pkg::ResetUndefined); + #(reset_us * 1us); + if (complete_it) reset_done(); + endtask + + virtual protected task por_reset(bit complete_it = 1); + `uvm_info(`gfn, "Starting POR", UVM_MEDIUM) + cfg.rstmgr_vif.por_n = '0; + control_all_clocks(.enable(0)); + #(100 * 1ns); + start_clocks(); + cfg.aon_clk_rst_vif.wait_clks(POR_CLK_CYCLES); + por_reset_done(complete_it); + endtask + + virtual task apply_reset(string kind = "HARD"); + fork + por_reset(); + super.apply_reset(kind); + join + endtask + + virtual task apply_resets_concurrently(int reset_duration_ps = 0); + fork + por_reset(); + start_clocks(); + super.apply_resets_concurrently(reset_duration_ps); + join + `uvm_info(`gfn, "Done with apply_resets_concurrently", UVM_MEDIUM) + endtask + + // Disable exclusions for RESET_REQ since they cause trouble for full-chip only. + function void disable_unnecessary_exclusions(); + csr_excl_item csr_excl = ral.get_excl_item(); + `uvm_info(`gfn, "Dealing with exclusions", UVM_MEDIUM) + csr_excl.enable_excl(.obj("rstmgr_reg_block.reset_req"), .enable(1'b0)); + csr_excl.print_exclusions(UVM_MEDIUM); + endfunction + + task pre_start(); + if (do_rstmgr_init) rstmgr_init(); + disable_unnecessary_exclusions(); + super.pre_start(); + endtask + + // setup basic rstmgr features + virtual task rstmgr_init(); + // Must set clk_rst_vif frequency to IO_DIV4_FREQ_MHZ since they are gated + // versions of each other and have no clock domain crossings. + // Notice they may still end up out of phase due to the way they get started. + cfg.clk_rst_vif.set_freq_mhz(IO_DIV4_FREQ_MHZ); + cfg.aon_clk_rst_vif.set_freq_mhz(AON_FREQ_MHZ); + cfg.io_clk_rst_vif.set_freq_mhz(IO_FREQ_MHZ); + cfg.io_div2_clk_rst_vif.set_freq_mhz(IO_DIV2_FREQ_MHZ); + cfg.io_div4_clk_rst_vif.set_freq_mhz(IO_DIV4_FREQ_MHZ); + cfg.main_clk_rst_vif.set_freq_mhz(MAIN_FREQ_MHZ); + // Initial values for some input pins. + cfg.rstmgr_vif.scanmode_i = prim_mubi_pkg::MuBi4False; + cfg.rstmgr_vif.scan_rst_ni = scan_rst_ni; + set_pwrmgr_rst_reqs(1'b0, 1'b0); + set_rstreqs('0); + set_reset_cause(pwrmgr_pkg::ResetNone); + endtask + + // csr method wrapper for unpacked array registers + virtual task rstmgr_csr_rd_check_unpack( + input uvm_object ptr[], input uvm_reg_data_t compare_value = 0, input string err_msg = ""); + foreach (ptr[i]) begin + if (cfg.under_reset) return; + csr_rd_check(.ptr(ptr[i]), .compare_value(compare_value[i]), .err_msg(err_msg)); + end + endtask : rstmgr_csr_rd_check_unpack + + virtual task rstmgr_csr_wr_unpack(input uvm_object ptr[], input uvm_reg_data_t value); + foreach (ptr[i]) begin + if (cfg.under_reset) return; + csr_wr(.ptr(ptr[i]), .value(value[i])); + end + endtask +endclass : rstmgr_base_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_common_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_common_vseq.sv new file mode 100644 index 00000000000..3f87231dfd3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_common_vseq.sv @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_common_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_common_vseq) + + constraint num_trans_c {num_trans inside {[1 : 2]};} + `uvm_object_new + + virtual task body(); + run_common_vseq_wrapper(num_trans); + endtask : body + +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv new file mode 100644 index 00000000000..fdc180ea41f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv @@ -0,0 +1,228 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This tests each leaf reset consistency checkers. +// +// For resets out of +// 1 - low power entry reset +// 2 - hw req reset +// 3 - sw reset +// Create reset consistency errors in the current leaf, and check that a +// fatal_cnsty_fault alert is generated. +class rstmgr_leaf_rst_cnsty_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_leaf_rst_cnsty_vseq) + + `uvm_object_new + + int cycles_to_check = 7; + int error_pos; + int my_pos; + rand int cycles_reset_width; + rand int cycles_child_reset_width; + rand int cycles_in_apply_resets; + rand int cycles_to_child_reset; + rand int cycles_to_child_release; + rand int cycles_to_parent_reset; + rand int cycles_to_parent_release; + rand int cycles_to_sw_reset; + rand int cycles_to_sw_release; + + constraint rstreqs_non_zero_c {rstreqs != '0;} + constraint sw_rst_regwen_non_trivial_c {sw_rst_regwen != '0 && sw_rst_regwen != '1;} + constraint sw_rst_some_reset_n_c {sw_rst_regwen & ~sw_rst_ctrl_n != '0;} + + constraint cycles_reset_width_c {cycles_reset_width inside {[2 : 10]};} + constraint cycles_child_reset_width_c {cycles_child_reset_width inside {[2 : 10]};} + constraint cycles_in_apply_resets_c {cycles_in_apply_resets inside {[5 : 25]};} + constraint cycles_to_child_reset_c {cycles_to_child_reset inside {[3 : 8]};} + constraint cycles_to_child_release_c {cycles_to_child_release inside {[3 : 6]};} + constraint cycles_to_parent_reset_c {cycles_to_parent_reset inside {[2 : 8]};} + constraint cycles_to_parent_release_c {cycles_to_parent_release inside {[3 : 6]};} + constraint cycles_to_sw_reset_c {cycles_to_sw_reset inside {[2 : 8]};} + constraint cycles_to_sw_release_c {cycles_to_sw_release inside {[3 : 6]};} + + // There is an extra POR reset when the consistency failure is triggered due to apply_reset. + int maybe_por_reset; + + task body(); + for (int i = 0; i < LIST_OF_LEAFS.size(); ++i) begin + string leaf_path = {"tb.dut.", LIST_OF_LEAFS[i], ".gen_rst_chk.u_rst_chk"}; + error_pos = $urandom_range(1, 3); + my_pos = 0; + `uvm_info(`gfn, $sformatf("Round %0d %s pos:%0d", i, leaf_path, error_pos), UVM_MEDIUM) + // Get a clean slate for reset_info. + csr_wr(.ptr(ral.reset_info), .value('1)); + + fork + unexpected_child_activity(leaf_path); + begin + int expected; + set_pos_and_wait(); + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + // Send low power entry reset. + send_lowpower_reset(); + expected = 1 << ral.reset_info.low_power_exit.get_lsb_pos(); + + check_reset_info(maybe_por_reset | expected, "expected reset_info to indicate low power"); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b1); + + csr_wr(.ptr(ral.reset_info), .value('1)); + cfg.io_div4_clk_rst_vif.wait_clks(10); + + // Send HwReq. + // Enable alert_info and cpu_info capture. + set_pos_and_wait(); + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + expected = rstreqs << ral.reset_info.hw_req.get_lsb_pos(); + send_hw_reset(rstreqs); + check_reset_info(maybe_por_reset | expected, $sformatf( + "expected reset_info to match hw_req 0x%x", expected)); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b0); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + set_pos_and_wait(); + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + // Send sw reset. + csr_wr(.ptr(ral.reset_req), .value(MuBi4True)); + send_sw_reset(); + expected = 1 << ral.reset_info.sw_reset.get_lsb_pos(); + check_reset_info(maybe_por_reset | expected, "Expected reset_info to indicate sw reset"); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 0); + csr_wr(.ptr(ral.reset_info), .value('1)); + end + join + end + endtask : body + + task post_start(); + expect_fatal_alerts = 1; + super.post_start(); + endtask + + task send_unexpected_child_reset(string path); + `uvm_info(`gfn, "unexpected child reset start", UVM_MEDIUM) + // clear all + set_leaf_reset(.path({path, ".parent_rst_ni"}), .value(1), .cycles(0)); + set_leaf_reset(.path({path, ".sw_rst_req_i"}), .value(0), .cycles(0)); + set_leaf_reset(.path({path, ".child_rst_ni"}), .value(1), .cycles(0)); + + cfg.scoreboard.set_exp_alert("fatal_cnsty_fault", 1, 20); + + // assert child reset + set_leaf_reset(.path({path, ".child_rst_ni"}), .value(0), .cycles(cycles_to_child_reset)); + endtask : send_unexpected_child_reset + + task send_unexpected_child_release(string path); + `uvm_info(`gfn, "unexpected child release start", UVM_MEDIUM) + fork + set_leaf_reset(.path({path, ".parent_rst_ni"}), .value(0), .cycles(cycles_to_parent_reset)); + set_leaf_reset(.path({path, ".sw_rst_req_i"}), .value(1), .cycles(cycles_to_sw_reset)); + set_leaf_reset(.path({path, ".child_rst_ni"}), .value(0), .cycles(cycles_to_child_reset)); + join + + cfg.scoreboard.set_exp_alert("fatal_cnsty_fault", 1, 20); + + set_leaf_reset(.path({path, ".child_rst_ni"}), .value(1), .cycles(cycles_to_child_release)); + endtask : send_unexpected_child_release + + local task set_leaf_reset(string path, logic value, int cycles); + cfg.clk_rst_vif.wait_clks(cycles); + `uvm_info(`gfn, $sformatf("Force %s = %b", path, value), UVM_MEDIUM) + `DV_CHECK(uvm_hdl_force(path, value)) + endtask : set_leaf_reset + + // Create some unexpected child activity when my_pos is error_pos. The unexpected activity + // should trigger alerts, so this fails if no alert is generated. + task unexpected_child_activity(string path); + int err_value; + string lpath; + `DV_SPINWAIT(while (my_pos < error_pos) @cfg.clk_rst_vif.cb;, + "Timeout waiting for my_pos < error_pos", 1000_000) + + `DV_SPINWAIT(wait_for_cnsty_idle(path);, "Timeout waiting for cnsty_idle", 1000_000) + + `DV_SPINWAIT(wait_for_alert_sender_ready();, "Timeout waiting for alert_sender ready", 1000_000) + `DV_CHECK_RANDOMIZE_FATAL(this); + `uvm_info(`gfn, "Triggering inconsistency", UVM_MEDIUM) + randcase + 1: send_unexpected_child_reset(path); + 1: send_unexpected_child_release(path); + endcase + + cfg.clk_rst_vif.wait_clks(cycles_to_check); + `DV_SPINWAIT(wait(cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.alert_tx_final.alert_p);, + "Timeout waiting for alert fatal_cnsty_fault", 10_000) + + lpath = {path, ".child_rst_ni"}; + `DV_CHECK(uvm_hdl_release(lpath)) + lpath = {path, ".parent_rst_ni"}; + `DV_CHECK(uvm_hdl_release(lpath)) + lpath = {path, ".sw_rst_req_i"}; + `DV_CHECK(uvm_hdl_release(lpath)) + // And expect POR bit to be set. + maybe_por_reset = 1; + apply_reset(); + + // set error_pos to large value + // after error injection. + error_pos = 100; + endtask : unexpected_child_activity + + // wait for parent and child reset deassert. + // to make sure rstmgr_cnsty_chk state is not Reset state. + task wait_for_cnsty_idle(string path); + int value = 1; + string lpath; + + while (value == 1) begin + @cfg.clk_rst_vif.cb; + lpath = {path, ".sync_parent_rst"}; + `DV_CHECK(uvm_hdl_read(lpath, value)) + end + value = 1; + while (value == 1) begin + @cfg.clk_rst_vif.cb; + lpath = {path, ".sync_child_rst"}; + `DV_CHECK(uvm_hdl_read(lpath, value)) + end + endtask : wait_for_cnsty_idle + + // This waits until the alert_rx differential pairs are complementary, indicating the + // end of their initialization phase. This is necessary so the fault injection doesn't + // happen during initialization, which would end up delaying the outgoing alert. + task wait_for_alert_sender_ready(); + `uvm_info(`gfn, "Waiting for alert sender ready", UVM_MEDIUM) + forever @cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb begin + if (cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb.alert_rx.ping_p != + cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb.alert_rx.ping_n && + cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb.alert_rx.ack_p != + cfg.m_alert_agent_cfgs["fatal_cnsty_fault"].vif.sender_cb.alert_rx.ack_n) begin + `uvm_info(`gfn, "Alert sender is ready", UVM_MEDIUM) + return; + end + end + endtask : wait_for_alert_sender_ready + + task check_alert_and_cpu_info_after_reset(alert_crashdump_t alert_dump, cpu_crash_dump_t cpu_dump, + logic enable); + + if (error_pos != my_pos) begin + super.check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, enable); + end + endtask : check_alert_and_cpu_info_after_reset + + // Increments my_pos and if it equals error_pos this just waits to give time for the consistency + // error to be injected and side-effects to be created. Clear the expectation of a por reset + // since this is a new reset. + task set_pos_and_wait(); + maybe_por_reset = 0; + my_pos++; + `DV_SPINWAIT(while (my_pos == error_pos) @cfg.clk_rst_vif.cb;, $sformatf( + "Timeout waiting for my_pos == error_pos ends my_pos:%0d", my_pos), 1000_000) + endtask : set_pos_and_wait +endclass : rstmgr_leaf_rst_cnsty_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_shadow_attack_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_shadow_attack_vseq.sv new file mode 100644 index 00000000000..4b88e03748f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_shadow_attack_vseq.sv @@ -0,0 +1,84 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Description: +// Test assert glitch to shadow leaf reset module and +// check if nomal reset module got affected or vice versa +class rstmgr_leaf_rst_shadow_attack_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_leaf_rst_shadow_attack_vseq) + + `uvm_object_new + + string leaf_path; + + task body(); + for (int i = 0; i < LIST_OF_SHADOW_LEAFS.size(); ++i) begin + leaf_path = {"tb.dut.", LIST_OF_SHADOW_LEAFS[i]}; + `uvm_info(`gfn, $sformatf("Round %0d %s ", i, leaf_path), UVM_MEDIUM) + + leaf_rst_attack(leaf_path, {leaf_path, "_shadowed"}); + leaf_rst_attack({leaf_path, "_shadowed"}, leaf_path); + end + endtask : body + + task leaf_rst_attack(string npath, string gpath); + // Wait for any bit in rst_sys_io_div4_n to become inactive. + wait(|cfg.rstmgr_vif.resets_o.rst_sys_io_div4_n); + // Disable cascading reset assertions, since forcing related signals causes failures. + cfg.rstmgr_cascading_sva_vif.disable_sva = 1'b1; + `uvm_info(`gfn, $sformatf("Starting leaf attack between %s and %s", npath, gpath), UVM_MEDIUM) + cfg.scoreboard.set_exp_alert("fatal_cnsty_fault", 1, 20); + add_glitch(gpath); + wait_and_check(npath); + remove_glitch(gpath); + cfg.rstmgr_cascading_sva_vif.disable_sva = 1'b0; + `uvm_info(`gfn, "Ending leaf attack", UVM_MEDIUM) + + cfg.clk_rst_vif.wait_clks(10); + apply_reset(); + endtask : leaf_rst_attack + + + function void add_glitch(string path); + string epath = {path, ".rst_en_o"}; + string opath = {path, ".leaf_rst_o"}; + + `DV_CHECK(uvm_hdl_force(epath, prim_mubi_pkg::MuBi4True), $sformatf( + "Path %0s has problem", epath)) + `DV_CHECK(uvm_hdl_force(opath, 0), $sformatf("Path %0s has problem", opath)) + endfunction + + task wait_and_check(string path); + logic [3:0] rst_en; + logic leaf_rst; + string epath = {path, ".rst_en_o"}; + string opath = {path, ".leaf_rst_o"}; + + // Wait enough cycles to allow the uvm_hdl_force to take effect, since it is not instantaneous, + // and for side-effects to propagate. + cfg.io_div4_clk_rst_vif.wait_clks(10); + + `uvm_info(`gfn, $sformatf("Checking rst and en for %s", path), UVM_MEDIUM) + `DV_CHECK(uvm_hdl_read(epath, rst_en), $sformatf("Path %0s has problem", epath)) + `DV_CHECK(uvm_hdl_read(opath, leaf_rst), $sformatf("Path %0s has problem", opath)) + + `DV_CHECK_EQ(prim_mubi_pkg::mubi4_t'(rst_en), prim_mubi_pkg::MuBi4False, + $sformatf("%s value mismatch", epath)) + `DV_CHECK_EQ(leaf_rst, 1, $sformatf("%s value mismatch", opath)) + endtask : wait_and_check + + function void remove_glitch(string path); + string epath = {path, ".rst_en_o"}; + string opath = {path, ".leaf_rst_o"}; + `DV_CHECK(uvm_hdl_release(epath), $sformatf("Path %0s has problem", epath)) + `DV_CHECK(uvm_hdl_release(opath), $sformatf("Path %0s has problem", opath)) + endfunction + + // clean up glitch will create reset consistency error + // in shadow leaf reset module + task post_start(); + expect_fatal_alerts = 1; + super.post_start(); + endtask + +endclass : rstmgr_leaf_rst_shadow_attack_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_por_stretcher_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_por_stretcher_vseq.sv new file mode 100644 index 00000000000..5a68b713453 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_por_stretcher_vseq.sv @@ -0,0 +1,43 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the POR stretching functionality: it directly controls the por_n_i input at the start of +// the test, and randomly glitches it for a few cycles at intervals less than the stretch cycle +// count, which is at least 32 cycles, to make sure the internal and output resets won't be +// released until the input is held steady for a sufficient number of cycles. +class rstmgr_por_stretcher_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_por_stretcher_vseq) + + `uvm_object_new + + // Wait a few cycles for resets to propagate before we start flipping por_n_i, to avoid + // spurious SVA failures dut to missing rise transitions of leaf resets. + localparam int AON_CYCLES_BEFORE_START = 4; + + // Wait this many cycles before checking for side effects of a complete reset. + localparam int AON_CYCLES_BEFORE_RESET_CHECK = 45; + + rand int glitch_separation_cycles; + rand int glitch_duration_cycles; + + // The separation between glitches that will cause a reset to fail to propagate. + constraint glitch_separation_cycles_c {glitch_separation_cycles inside {[1 : 35]};} + // The duration cycle is not very interesting. + constraint glitch_duration_cycles_c {glitch_duration_cycles inside {[1 : 8]};} + + task body(); + cfg.aon_clk_rst_vif.wait_clks(AON_CYCLES_BEFORE_START); + for (int i = 0; i < num_trans; ++i) begin + `DV_CHECK_RANDOMIZE_FATAL(this) + cfg.rstmgr_vif.por_n = 1'b1; + cfg.aon_clk_rst_vif.wait_clks(glitch_separation_cycles); + cfg.rstmgr_vif.por_n = 1'b0; + cfg.aon_clk_rst_vif.wait_clks(glitch_duration_cycles); + `DV_CHECK_EQ(cfg.rstmgr_vif.resets_o.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel], 1'b0) + end + por_reset_done(.complete_it(1)); + csr_rd_check(.ptr(ral.reset_info.por), .compare_value(1'b1), + .err_msg("Unexpected reset_info.por low")); + endtask +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv new file mode 100644 index 00000000000..1a5071c521c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv @@ -0,0 +1,189 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the reset_info CSR settings, and alert and cpu dump capture for random +// resets. +// +// Notice that for rstmgr both POR and scan reset have identical side-effects. +class rstmgr_reset_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_reset_vseq) + + `uvm_object_new + + typedef bit [ResetLast-1:0] which_resets_t; + + rand bit por_rst; + rand bit scan_rst; + rand bit low_power_rst; + rand bit sw_rst; + rand bit hw_rst; + + constraint which_resets_c { + $onehot( + {por_rst, scan_rst, low_power_rst, sw_rst || hw_rst} + ); + } + + constraint num_trans_c {num_trans inside {[40 : 60]};} + + // VCS seems to have non-uniform distributions for this variable. + rand logic alert_enable; + + rand logic cpu_enable; + + rand reset_e start_reset; + constraint start_reset_c {start_reset inside {ResetPOR, ResetScan};} + + which_resets_t which_resets; + mubi4_t sw_reset_csr; + + function which_resets_t create_which_resets(); + which_resets_t which_resets; + if (por_rst) which_resets[ResetPOR] = 1; + if (scan_rst) which_resets[ResetScan] = 1; + if (low_power_rst) which_resets[ResetLowPower] = 1; + if (sw_rst) which_resets[ResetSw] = 1; + if (hw_rst) which_resets[ResetHw] = 1; + return which_resets; + endfunction + + function bit has_aon_reset(which_resets_t which_resets); + return which_resets[ResetPOR] || which_resets[ResetScan]; + endfunction + + function bit clear_capture_enable(which_resets_t which_resets); + return (which_resets & ~(1 << ResetLowPower)) ? 1 : 0; + endfunction + + function void post_randomize(); + sw_reset_csr = get_rand_mubi4_val(0, 2, 4); + endfunction + + function string resets_description(which_resets_t which_resets, rstreqs_t rstreqs); + string msg = "Resets to be sent:"; + bit some; + for (reset_e r = r.first(); r != r.last(); r = r.next()) begin + if (which_resets[r]) begin + if (some) msg = {msg, ", "}; + msg = {msg, " ", reset_name[r]}; + if (r == ResetHw) msg = {msg, $sformatf(" with 0x%x", rstreqs)}; + some = 1; + end + end + return msg; + endfunction + + function reset_info_t get_expected_reset_info(which_resets_t which_resets, rstreqs_t rstreqs); + reset_info_t reset_info; + for (reset_e r = r.first(); r != r.last(); r = r.next()) begin + if (which_resets[r]) reset_info |= get_reset_code(r, rstreqs); + end + return reset_info; + endfunction + + task body(); + reset_info_t expected_reset_info_code; + logic expected_alert_enable; + logic expected_cpu_enable; + alert_crashdump_t expected_alert_dump = '0; + cpu_crash_dump_t expected_cpu_dump = '0; + alert_crashdump_t prev_alert_dump = '0; + cpu_crash_dump_t prev_cpu_dump = '0; + + // Expect reset info to be POR when running the sequence standalone. + if (is_running_sequence("rstmgr_reset_vseq")) begin + check_reset_info(1, "expected reset_info to be POR"); + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(1'b0)); + end + + `DV_CHECK_RANDOMIZE_FATAL(this) + + // Clear reset_info register, and enable cpu and alert info capture. + set_alert_info_for_capture(alert_dump, alert_enable); + set_cpu_info_for_capture(cpu_dump, cpu_enable); + csr_wr(.ptr(ral.reset_info), .value('1)); + + // We need to start with an AON reset to process non-capturing resets. + if (start_reset == ResetPOR) por_reset(); + else if (start_reset == ResetScan) send_scan_reset(); + + // On either of these resets we expect captures to be all zero and enables to be off. + expected_alert_dump = '0; + expected_cpu_dump = '0; + expected_alert_enable = 0; + expected_cpu_enable = 0; + + cfg.clk_rst_vif.wait_clks(8); + // Wait till rst_lc_n is inactive for non-aon. + `DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1]) + + check_reset_info(get_reset_code(start_reset, 0), {reset_name[start_reset], " reset"}); + check_alert_info_after_reset(expected_alert_dump, expected_alert_enable); + check_cpu_info_after_reset(expected_cpu_dump, expected_cpu_enable); + prev_alert_dump = expected_alert_dump; + prev_cpu_dump = expected_cpu_dump; + + for (int i = 0; i < num_trans; ++i) begin : trans_loop + logic clear_enables; + logic has_aon; + + `uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM) + `DV_CHECK_RANDOMIZE_FATAL(this) + which_resets = create_which_resets(); + set_alert_info_for_capture(alert_dump, alert_enable); + set_cpu_info_for_capture(cpu_dump, cpu_enable); + csr_wr(.ptr(ral.reset_info), .value('1)); + if (which_resets[ResetSw]) begin + sw_reset_csr = MuBi4True; + csr_wr(.ptr(ral.reset_req), .value(sw_reset_csr)); + end + has_aon = has_aon_reset(which_resets); + clear_enables = clear_capture_enable(which_resets); + + `uvm_info(`gfn, $sformatf("Expected to %0s capture enables", clear_enables ? "clear" : "hold" + ), UVM_MEDIUM) + expected_reset_info_code = get_expected_reset_info(which_resets, rstreqs); + expected_alert_enable = alert_enable && !clear_enables; + expected_cpu_enable = cpu_enable && !clear_enables; + expected_alert_dump = has_aon ? '0 : (alert_enable ? alert_dump : prev_alert_dump); + expected_cpu_dump = has_aon ? '0 : (cpu_enable ? cpu_dump : prev_cpu_dump); + `uvm_info(`gfn, resets_description(which_resets, rstreqs), UVM_MEDIUM) + `uvm_info(`gfn, $sformatf("resets with alert_en %b, cpu_en %b", alert_enable, cpu_enable), + UVM_MEDIUM) + + fork + if (which_resets[ResetPOR]) por_reset(.complete_it(0)); + if (which_resets[ResetScan]) send_scan_reset(.complete_it(0)); + if (which_resets[ResetLowPower]) begin + cfg.io_div4_clk_rst_vif.wait_clks(lowpower_rst_cycles); + send_lowpower_reset(.complete_it(0)); + end + if (which_resets[ResetSw]) begin + cfg.io_div4_clk_rst_vif.wait_clks(sw_rst_cycles); + send_sw_reset(.complete_it(0)); + end + if (which_resets[ResetHw]) begin + cfg.io_div4_clk_rst_vif.wait_clks(hw_rst_cycles); + send_hw_reset(rstreqs, .complete_it(0)); + end + join + #(reset_us * 1us); + reset_done(); + + cfg.io_div4_clk_rst_vif.wait_clks(8); + wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]); + check_reset_info(expected_reset_info_code); + check_alert_info_after_reset(.alert_dump(expected_alert_dump), + .enable(expected_alert_enable)); + check_cpu_info_after_reset(.cpu_dump(expected_cpu_dump), .enable(expected_cpu_enable)); + if (has_aon) read_and_check_all_csrs_after_reset(); + prev_alert_dump = expected_alert_dump; + prev_cpu_dump = expected_cpu_dump; + end : trans_loop + csr_wr(.ptr(ral.reset_info), .value('1)); + // This clears the info registers to cancel side-effects into other sequences with stress tests. + clear_alert_and_cpu_info(); + endtask : body + +endclass : rstmgr_reset_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sec_cm_scan_intersig_mubi_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sec_cm_scan_intersig_mubi_vseq.sv new file mode 100644 index 00000000000..cb4369acbb4 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sec_cm_scan_intersig_mubi_vseq.sv @@ -0,0 +1,52 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Description: +// While running smoke test, assert illegal scanmode input +class rstmgr_sec_cm_scan_intersig_mubi_vseq extends rstmgr_smoke_vseq; + + `uvm_object_utils(rstmgr_sec_cm_scan_intersig_mubi_vseq) + + `uvm_object_new + + task body(); + fork + begin : isolation_fork + fork + super.body(); + add_noise(); + join_any + disable fork; + end + join + endtask : body + + task add_noise(); + int delay; + + forever begin + // If scan_rst_ni is active we assume super is doing a scan reset, so keep scanmode_i True. + if (cfg.rstmgr_vif.scan_rst_ni == 1'b1) begin + cfg.rstmgr_vif.scanmode_i = get_rand_mubi4_val(0, 1, 4); + end else begin + cfg.rstmgr_vif.scanmode_i = prim_mubi_pkg::MuBi4True; + end + delay = $urandom_range(5, 30); + fork + // This waits for a certain number of cycles or for a change in scan_rst_ni, + // whichever is sooner, or it could end up skipping a full scan reset. + begin : isolation_fork + fork + // @(edge) is not supported by xcelium, workaround with posedge+negedge + @(posedge cfg.rstmgr_vif.scan_rst_ni or negedge cfg.rstmgr_vif.scan_rst_ni); + cfg.clk_rst_vif.wait_clks(delay); + join_any + disable fork; + end + join + // Somehow without this VCS will scan_rst_ni transitions to 0. + #0; + end + endtask : add_noise +endclass : rstmgr_sec_cm_scan_intersig_mubi_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv new file mode 100644 index 00000000000..9d8a05495c6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv @@ -0,0 +1,116 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the different kinds of reset: POR, low power wakeup, hardware reset, debug_mode reset, +// and software initiated peripheral resets. +class rstmgr_smoke_vseq extends rstmgr_base_vseq; + + `uvm_object_utils(rstmgr_smoke_vseq) + + `uvm_object_new + + constraint rstreqs_non_zero_c {rstreqs != '0;} + constraint sw_rst_regwen_non_trivial_c {sw_rst_regwen != '0 && sw_rst_regwen != '1;} + constraint sw_rst_some_reset_c {sw_rst_regwen & ~sw_rst_ctrl_n != '0;} + + local task wait_between_resets(); + cfg.io_div4_clk_rst_vif.wait_clks(10); + endtask + + task body(); + uvm_reg_data_t exp_reg; + bit is_standalone = is_running_sequence("rstmgr_smoke_vseq"); + // Expect reset info to be POR when running the sequence standalone. + if (is_standalone) begin + check_reset_info(1, "expected reset_info to be POR"); + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(1'b0)); + end + csr_wr(.ptr(ral.reset_info), .value('1)); + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + send_scan_reset(); + // Scan reset triggers an AON reset (and all others). + wait(&cfg.rstmgr_vif.resets_o.rst_por_aon_n); + + check_reset_info(1, "expected reset_info to be POR for scan reset"); + // Alert and cpu info settings were reset. Check and re-enable them. + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(1'b0)); + wait_between_resets(); + + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + // Send low power entry reset. + send_lowpower_reset(); + exp_reg = csr_utils_pkg::get_csr_val_with_updated_field(ral.reset_info.low_power_exit, '0, 1); + check_reset_info(exp_reg, "expected reset_info to indicate low power"); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b1); + wait_between_resets(); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + // Send HwReq. + // Enable alert_info and cpu_info capture. + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + send_hw_reset(rstreqs); + exp_reg = csr_utils_pkg::get_csr_val_with_updated_field(ral.reset_info.hw_req, '0, rstreqs); + check_reset_info(exp_reg, $sformatf("expected reset_info to match 0x%x", exp_reg)); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b0); + wait_between_resets(); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + `DV_CHECK_RANDOMIZE_FATAL(this) + set_alert_and_cpu_info_for_capture(alert_dump, cpu_dump); + + // Send sw reset. + csr_wr(.ptr(ral.reset_req), .value(MuBi4True)); + send_sw_reset(); + exp_reg = csr_utils_pkg::get_csr_val_with_updated_field(ral.reset_info.sw_reset, '0, 1); + check_reset_info(exp_reg, "Expected reset_info to indicate sw reset"); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 0); + wait_between_resets(); + + csr_wr(.ptr(ral.reset_info), .value('1)); + + // Testing software resets: only run this when the sequence is run standalone, since + // setting sw_rst_regwen is irreversible. + if (is_standalone) begin : sw_rst + logic [NumSwResets-1:0] exp_ctrl_n; + const logic [NumSwResets-1:0] sw_rst_all_ones = '1; + alert_crashdump_t bogus_alert_dump = '1; + cpu_crash_dump_t bogus_cpu_dump = '1; + + set_alert_and_cpu_info_for_capture(bogus_alert_dump, bogus_cpu_dump); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(sw_rst_all_ones), + .err_msg("expected no reset on")); + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_regwen), .value(sw_rst_regwen)); + `uvm_info(`gfn, $sformatf("sw_rst_regwen set to 0x%0h", sw_rst_regwen), UVM_LOW) + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_regwen), .compare_value(sw_rst_regwen)); + + // This is probably also tested by common CSR tests. + // Check sw_rst_regwen can not be set to all ones again because it is rw0c. + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_regwen), .value({NumSwResets{1'b1}})); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_regwen), .compare_value(sw_rst_regwen), + .err_msg("Expected sw_rst_regwen block raising individual bits because rw0c")); + + // Check that the regwen disabled bits block corresponding updated to ctrl_n. + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value(sw_rst_regwen)); + rstmgr_csr_rd_check_unpack(.ptr(ral.sw_rst_ctrl_n), .compare_value(sw_rst_all_ones), + .err_msg("Expected sw_rst_ctrl_n not to change")); + + check_sw_rst_ctrl_n(sw_rst_ctrl_n, sw_rst_regwen, 1); + check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b1); + end : sw_rst + // This clears the info registers to cancel side-effects into other sequences with stress tests. + clear_alert_and_cpu_info(); + endtask : body + +endclass : rstmgr_smoke_vseq diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_stress_all_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_stress_all_vseq.sv new file mode 100644 index 00000000000..0ab994ac1c8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_stress_all_vseq.sv @@ -0,0 +1,37 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// combine all rstmgr seqs (except below seqs) in one seq to run sequentially +// 1. csr seq, which requires scb to be disabled +class rstmgr_stress_all_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_stress_all_vseq) + + `uvm_object_new + + task body(); + string seq_names[] = {"rstmgr_reset_vseq", "rstmgr_smoke_vseq", "rstmgr_sw_rst_vseq"}; + for (int i = 1; i <= num_trans; i++) begin + uvm_sequence seq; + rstmgr_base_vseq rstmgr_vseq; + uint seq_idx = $urandom_range(0, seq_names.size - 1); + + seq = create_seq_by_name(seq_names[seq_idx]); + `downcast(rstmgr_vseq, seq) + + // if upper seq disables do_apply_reset for this seq, then can't issue reset + // as upper seq may drive reset + if (do_apply_reset) rstmgr_vseq.do_apply_reset = $urandom_range(0, 1); + else rstmgr_vseq.do_apply_reset = 0; + rstmgr_vseq.set_sequencer(p_sequencer); + `DV_CHECK_RANDOMIZE_FATAL(rstmgr_vseq) + `uvm_info(`gfn, $sformatf("seq_idx = %0d, sequence is %0s", seq_idx, rstmgr_vseq.get_name()), + UVM_MEDIUM) + + rstmgr_vseq.start(p_sequencer); + `uvm_info(`gfn, $sformatf( + "End of sequence %0s with seq_idx = %0d", rstmgr_vseq.get_name(), seq_idx), + UVM_MEDIUM) + end + endtask : body +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_reset_race_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_reset_race_vseq.sv new file mode 100644 index 00000000000..87c394266d5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_reset_race_vseq.sv @@ -0,0 +1,59 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the software reset functionality: using `sw_rst_regen` and `sw_rst_ctrl_n` CSRs it causes +// resets for each of the bits randomly. It also triggers lc or sys resets to verify the reset +// transitions that cause rising upper resets but non-rising leafs. +// +// Then it clears specific `sw_rst_regwen` bits and attempts to cause resets to determine +// the bits with `sw_rst_regwen` cleared cannot cause a reset. +class rstmgr_sw_rst_reset_race_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_sw_rst_reset_race_vseq) + + `uvm_object_new + rand int cycles_before_sw_rst; + rand int cycles_before_reset; + + // When reset is issued the clocks will be stopped, so the sw_rst_ctrl_n writes must + // start before reset to be safe, or this could wait forever since the clock will stop. + constraint cycles_racing_c { + solve cycles_before_reset before cycles_before_sw_rst; + cycles_before_reset inside {[2 : 8]}; + cycles_before_sw_rst inside {[1 : cycles_before_reset - 1]}; + } + + constraint rstreqs_non_zero_c {rstreqs != '0;} + + task body(); + bit [NumSwResets-1:0] exp_ctrl_n; + bit [NumSwResets-1:0] sw_rst_regwen = '1; + int expected; + alert_handler_pkg::alert_crashdump_t bogus_alert_dump = '1; + rv_core_ibex_pkg::cpu_crash_dump_t bogus_cpu_dump = '1; + set_alert_and_cpu_info_for_capture(bogus_alert_dump, bogus_cpu_dump); + + for (int i = 0; i < num_trans; ++i) begin + csr_wr(.ptr(ral.reset_info), .value('1)); + + `DV_CHECK_RANDOMIZE_FATAL(this) + fork + begin + cfg.clk_rst_vif.wait_clks(cycles_before_sw_rst); + check_sw_rst_ctrl_n(sw_rst_ctrl_n, sw_rst_regwen, 0); + `uvm_info(`gfn, "Done with sw_rst", UVM_MEDIUM) + end + begin + cfg.clk_rst_vif.wait_clks(cycles_before_reset); + send_hw_reset(rstreqs, .complete_it(0)); + `uvm_info(`gfn, "Done with send_reset", UVM_MEDIUM) + end + join + #(reset_us * 1us); + reset_done(); + clear_sw_rst_ctrl_n(); + expected = rstreqs << ral.reset_info.hw_req.get_lsb_pos(); + check_reset_info(expected, $sformatf("expected reset_info to match 0x%x", expected)); + end + endtask +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv new file mode 100644 index 00000000000..edb0ba7d24d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_sw_rst_vseq.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Tests the software reset functionality: using `sw_rst_regen` and `sw_rst_ctrl_n` CSRs it causes +// resets for each of the bits randomly. It also triggers lc or sys resets to verify the reset +// transitions that cause rising upper resets but non-rising leafs. +// +// Then it clears each `sw_rst_regwen` bits and attempts to cause resets to determine +// the bits with `sw_rst_regwen` cleared cannot cause a reset. +class rstmgr_sw_rst_vseq extends rstmgr_base_vseq; + `uvm_object_utils(rstmgr_sw_rst_vseq) + + `uvm_object_new + + task body(); + bit [NumSwResets-1:0] exp_ctrl_n; + bit [NumSwResets-1:0] sw_rst_regwen = '1; + alert_crashdump_t bogus_alert_dump = '1; + cpu_crash_dump_t bogus_cpu_dump = '1; + set_alert_and_cpu_info_for_capture(bogus_alert_dump, bogus_cpu_dump); + + for (int i = 0; i < num_trans; ++i) begin + `DV_CHECK_RANDOMIZE_FATAL(this) + check_sw_rst_ctrl_n(sw_rst_ctrl_n, sw_rst_regwen, i % 2); + end + // Only run this part of the test if running standalone. Doing this in a stress test + // messes things up since setting the sw_rst_regwen CSR is irreversible. + if (is_running_sequence("rstmgr_sw_rst_vseq")) begin + // In preparation for the per-bit enable test, set sw_rst_ctrl_n to all 1. + rstmgr_csr_wr_unpack(.ptr(ral.sw_rst_ctrl_n), .value({NumSwResets{1'b1}})); + for (int i = 0; i < NumSwResets; ++i) begin + // Clear the regwen. + bit [NumSwResets-1:0] val_regwen = ~(1 << i); + bit [NumSwResets-1:0] exp_regwen = (~0) << (i + 1); + `uvm_info(`gfn, $sformatf("clearing sw_rst_regwen[%0d]", i), UVM_LOW) + csr_wr(.ptr(ral.sw_rst_regwen[i]), .value(val_regwen[i])); + check_sw_rst_regwen(exp_regwen); + check_sw_rst_ctrl_n(.sw_rst_ctrl_n('0), .sw_rst_regwen(exp_regwen), .erase_ctrl_n(1'b1)); + check_sw_rst_ctrl_n(.sw_rst_ctrl_n('1), .sw_rst_regwen(exp_regwen), .erase_ctrl_n(1'b1)); + // Check we cannot set it back. + csr_wr(.ptr(ral.sw_rst_regwen[i]), .value(1)); + csr_rd_check(.ptr(ral.sw_rst_regwen[i]), .compare_value(0), + .err_msg($sformatf("sw_rst_regwen[%0d] cannot be set back to 1", i))); + end + check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(1'b1)); + end + endtask +endclass diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv new file mode 100644 index 00000000000..10d98cad9bf --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_vseq_list.sv @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "rstmgr_base_vseq.sv" +`include "rstmgr_por_stretcher_vseq.sv" +`include "rstmgr_reset_vseq.sv" +`include "rstmgr_smoke_vseq.sv" +`include "rstmgr_stress_all_vseq.sv" +`include "rstmgr_sw_rst_reset_race_vseq.sv" +`include "rstmgr_sw_rst_vseq.sv" +`include "rstmgr_common_vseq.sv" +`include "rstmgr_sec_cm_scan_intersig_mubi_vseq.sv" +`include "rstmgr_leaf_rst_cnsty_vseq.sv" +`include "rstmgr_leaf_rst_shadow_attack_vseq.sv" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_manual_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_manual_excl.el new file mode 100644 index 00000000000..f152dfdd346 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_manual_excl.el @@ -0,0 +1,15 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Wed Nov 16 12:45:49 2022 +// ExclMode: default +//================================================== +CHECKSUM: "3681358461" +INSTANCE: tb.dut.u_child_handshake +ANNOTATION: "[UNR] src_req_i and req_chk_i are tied to constants" +Assert SyncReqAckHoldReq "assertion" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_unr_excl.el b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_unr_excl.el new file mode 100644 index 00000000000..75fe8118bd0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/cov_unr_excl.el @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +//================================================== +// This file contains the Excluded objects +// Generated By User: maturana +// Format Version: 2 +// Date: Wed Nov 16 20:32:58 2022 +// ExclMode: default +//================================================== +CHECKSUM: "1154881809 722956608" +INSTANCE: tb.dut +ANNOTATION: "VC_COV_UNR" +Condition 4 "1172916134" "(sync_child_rst && ((!sync_parent_rst))) 1 -1" (2 "10") +ANNOTATION: "VC_COV_UNR" +Condition 5 "1866172979" "(sync_parent_rst && ((!sync_child_rst))) 1 -1" (2 "10") diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/data/rstmgr_cnsty_chk_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/data/rstmgr_cnsty_chk_testplan.hjson new file mode 100644 index 00000000000..8c1d365bb0a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/data/rstmgr_cnsty_chk_testplan.hjson @@ -0,0 +1,43 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "rstmgr_cnsty_chk" + testpoints: [ + { + name: unexpected_child_reset_activity + desc: '''Verify unexpected child_reset activity flags an error. + ''' + stage: V2S + tests: ["rstmgr_cnsty_chk_smoke"] + } + { + name: child_reset_asserts_late + desc: '''Verify error triggered if child reset asserts late. + ''' + stage: V2S + tests: [] + } + { + name: child_reset_releases_late + desc: '''Verify error triggered if child reset releases late. + ''' + stage: V2S + tests: [] + } + { + name: parent_reset_asserts_late + desc: '''Verify error triggered if parent reset asserts late. + ''' + stage: V2S + tests: [] + } + { + name: parent_reset_releases_late + desc: '''Verify error triggered if parent reset releases late. + ''' + stage: V2S + tests: [] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core new file mode 100644 index 00000000000..58662611e38 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim.core @@ -0,0 +1,32 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:rstmgr_cnsty_chk_sim:0.1 +description: "Rstmgr_cnsty_chk DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:rstmgr_cnsty_chk:0.1 + - lowrisc:dv:sec_cm + file_type: systemVerilogSource + + files_dv: + depend: + - lowrisc:dv:dv_utils + - lowrisc:dv:dv_test_status + - lowrisc:dv:common_ifs + files: + - tb.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson new file mode 100644 index 00000000000..a7e5ebcd33b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson @@ -0,0 +1,50 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: rstmgr_cnsty_chk + + // Top level dut name (sv module). + dut: rstmgr_cnsty_chk + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_dv:rstmgr_cnsty_chk_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/data/rstmgr_cnsty_chk_testplan.hjson" + + // Import additional common sim cfg files. + import_cfgs: ["{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson"] + + + // Specific exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov_manual_excl.el", + "{self_dir}/cov_unr_excl.el"] + + // Default iterations for all tests - each test entry can override this. + reseed: 10 + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: rstmgr_cnsty_chk_test + } + ] + // List of regressions. + regressions: [ + { + name: smoke + tests: ["rstmgr_cnsty_chk_test"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/tb.sv new file mode 100644 index 00000000000..61028f24561 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/tb.sv @@ -0,0 +1,486 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for rstmgr_cnsty_chk. +// +// The test runs pairs of events separated by a variable number of cycles in order to determine +// when errors are triggered. +// +// Consider events E1 and E2: it can send E1 from N cycles before E2 up to M cycles after it and +// any number of cycles in between. +// +// The event pairs considered are: +// - Parent reset active, child reset active +// - Sw reset active, child reset active +// - Parent reset inactive, child reset inactive +// - Sw reset inactive, child reset inactive +// +// There are two clocks involved, and it tests either one running faster then the other. +// +// In order to improve coverage it also injects sparse fsm errors. + +// Interface driving the dut. +interface rstmgr_cnsty_chk_if; + logic child_rst_ni; + logic parent_rst_ni; + logic sw_rst_req_i; + logic sw_rst_req_clr_o; + logic err_o; + logic fsm_err_o; +endinterface + +// Class generating stimulus. +class reset_class; + parameter time ClkPeriod = 10_000; + parameter time ChildFastClkPeriod = 6_543; + parameter time ChildSlowClkPeriod = 25_678; + + parameter int ScanSweepBeforeCycles = 50; + parameter int ScanSweepAfterCycles = 10; + parameter int ScanSweepCycles = ScanSweepBeforeCycles + ScanSweepAfterCycles; + + parameter int IterationsPerDelta = 16; + + typedef enum int { + OrderChildLags, + OrderChildLeads + } order_e; + + typedef enum int { + TimingOkay, + TimingSlow + } timing_e; + + typedef enum int { + ChildClkFaster, + ChildClkSlower + } child_clk_e; + + typedef struct packed { + order_e order; + timing_e timing; + } reset_op_t; + + virtual clk_rst_if clk_rst_vif; + virtual clk_rst_if child_clk_rst_vif; + virtual rstmgr_cnsty_chk_if reset_vif; + + logic error = 0; + int cycles_to_check = 8; + + bit parent_rst_n; + bit sw_reset; + + int cycles_to_child_reset; + int cycles_to_child_release; + int cycles_to_parent_reset; + int cycles_to_parent_release; + int cycles_to_sw_reset; + int cycles_to_sw_release; + + rand int cycles_reset_width; + rand int cycles_child_reset_width; + rand int cycles_in_apply_resets; + + constraint cycles_reset_width_c {cycles_reset_width inside {[2 : 10]};} + constraint cycles_child_reset_width_c {cycles_child_reset_width inside {[2 : 10]};} + constraint cycles_in_apply_resets_c {cycles_in_apply_resets inside {[5 : 25]};} + + function new(virtual clk_rst_if clk_vif, virtual clk_rst_if child_clk_vif, + virtual rstmgr_cnsty_chk_if rst_vif); + clk_rst_vif = clk_vif; + child_clk_rst_vif = child_clk_vif; + reset_vif = rst_vif; + endfunction + + function string get_full_name(); + return "reset_class"; + endfunction + + task set_child_period(child_clk_e child_clk); + import uvm_pkg::*; + if (child_clk == ChildClkFaster) begin + `uvm_info(`gfn, $sformatf( + "Setting child clk (%0d ps) faster than reference (%0d ps)", + ChildFastClkPeriod, + ClkPeriod + ), UVM_LOW) + child_clk_rst_vif.set_period_ps(ChildFastClkPeriod); + end else begin + `uvm_info(`gfn, $sformatf( + "Setting child clk (%0d ps) slower than reference (%0d ps)", + ChildSlowClkPeriod, + ClkPeriod + ), UVM_LOW) + child_clk_rst_vif.set_period_ps(ChildSlowClkPeriod); + end + endtask + + task apply_resets(); + import uvm_pkg::*; + `uvm_info(`gfn, "Start apply_resets", UVM_MEDIUM) + fork + clk_rst_vif.apply_reset(.reset_width_clks(cycles_reset_width)); + child_clk_rst_vif.apply_reset(.reset_width_clks(cycles_child_reset_width)); + begin + reset_vif.parent_rst_ni = 1'b0; + clk_rst_vif.wait_clks(cycles_in_apply_resets); + reset_vif.parent_rst_ni = 1'b1; + end + begin + reset_vif.child_rst_ni = 1'b0; + child_clk_rst_vif.wait_clks(cycles_in_apply_resets); + reset_vif.child_rst_ni = 1'b1; + end + join + clk_rst_vif.wait_clks(20); + `uvm_info(`gfn, "End apply_resets", UVM_MEDIUM) + endtask + + task set_quiescent(); + import uvm_pkg::*; + `uvm_info(`gfn, "Setting quiescent inputs", UVM_MEDIUM) + reset_vif.parent_rst_ni = 1'b1; + reset_vif.sw_rst_req_i = 1'b0; + reset_vif.child_rst_ni = 1'b1; + endtask + + task set_parent_reset(logic value, int cycles); + import uvm_pkg::*; + if (reset_vif.parent_rst_ni == value) return; + `uvm_info(`gfn, $sformatf("Setting parent_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH) + clk_rst_vif.wait_clks(cycles); + reset_vif.parent_rst_ni = value; + endtask + + task set_sw_reset(logic value, int cycles); + import uvm_pkg::*; + if (reset_vif.sw_rst_req_i == value) return; + `uvm_info(`gfn, $sformatf("Setting sw_rst_req_i=%b after %0d cycles", value, cycles), UVM_HIGH) + clk_rst_vif.wait_clks(cycles); + reset_vif.sw_rst_req_i = value; + endtask + + task set_child_reset(logic value, int cycles); + import uvm_pkg::*; + if (reset_vif.child_rst_ni == value) return; + `uvm_info(`gfn, $sformatf("Setting child_rst_ni=%b after %0d cycles", value, cycles), UVM_HIGH) + clk_rst_vif.wait_clks(cycles); + reset_vif.child_rst_ni = value; + endtask + + task reset_start(); + fork + set_parent_reset(.value(parent_rst_n), .cycles(cycles_to_parent_reset)); + set_sw_reset(.value(sw_reset), .cycles(cycles_to_sw_reset)); + set_child_reset(.value(0), .cycles(cycles_to_child_reset)); + join + endtask + + task reset_end(); + fork + set_parent_reset(.value(1), .cycles(cycles_to_parent_release)); + set_sw_reset(.value(0), .cycles(cycles_to_sw_release)); + set_child_reset(.value(1), .cycles(cycles_to_child_release)); + join + endtask + + // Run a number of reset scenarios with some given cycle delays to allow CDC cycle fluctuations. + task run_iterations(input string description, input int delta_cycles, output int error_count); + import uvm_pkg::*; + + error_count = 0; + for (int i = 0; i < IterationsPerDelta; ++i) begin + set_quiescent(); + reset_start(); + clk_rst_vif.wait_clks(20); + reset_end(); + clk_rst_vif.wait_clks(cycles_to_check); + if (reset_vif.err_o) begin + ++error_count; + end + `uvm_info(`gfn, $sformatf( + "Scan %0s with cycles delta %0d error %b", + description, + delta_cycles, + reset_vif.err_o + ), UVM_HIGH) + // May get error, so reset. + set_quiescent(); + apply_resets(); + end + endtask + + // Run a parent reset to child reset. + task scan_parent_rst(); + import uvm_pkg::*; + + `uvm_info(`gfn, "scanning parent resets", UVM_LOW) + sw_reset = 0; + parent_rst_n = 0; + cycles_to_parent_release = 4; + cycles_to_child_release = 5; + cycles_to_child_reset = ScanSweepBeforeCycles; + for ( + cycles_to_parent_reset = 0; + cycles_to_parent_reset < ScanSweepCycles; + ++cycles_to_parent_reset + ) begin + int error_count = 0; + int delta_cycles = cycles_to_parent_reset - cycles_to_child_reset; + `uvm_info(`gfn, $sformatf("Sending parent reset %0d cycles from child", delta_cycles), + UVM_MEDIUM) + run_iterations("parent reset", delta_cycles, error_count); + `uvm_info(`gfn, $sformatf( + "Scan parent reset with cycles delta %0d total errors %0d / %0d", + delta_cycles, + error_count, + IterationsPerDelta + ), UVM_LOW) + `DV_CHECK(((delta_cycles <= -4) || (delta_cycles >= 4)) || (error_count == 0)) + `DV_CHECK(((delta_cycles >= -5) && (delta_cycles <= 5)) || + (error_count == IterationsPerDelta)) + end + endtask + + task scan_parent_release(); + import uvm_pkg::*; + + `uvm_info(`gfn, "scanning parent release", UVM_LOW) + sw_reset = 0; + parent_rst_n = 0; + cycles_to_parent_reset = 5; + cycles_to_child_reset = 5; + cycles_to_child_release = ScanSweepBeforeCycles; + for ( + cycles_to_parent_release = 0; + cycles_to_parent_release < ScanSweepCycles; + ++cycles_to_parent_release + ) begin + int error_count = 0; + int delta_cycles = cycles_to_parent_release - cycles_to_child_release; + `uvm_info(`gfn, $sformatf("Sending parent release %0d cycles from child", delta_cycles), + UVM_MEDIUM) + run_iterations("parent release", delta_cycles, error_count); + `uvm_info(`gfn, $sformatf( + "Scan parent release with cycles delta %0d total errors %0d / %0d", + delta_cycles, + error_count, + IterationsPerDelta + ), UVM_LOW) + `DV_CHECK((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0)) + `DV_CHECK(((delta_cycles > -42) && (delta_cycles < 2)) || (error_count == IterationsPerDelta)) + end + endtask + + task scan_sw_rst(); + import uvm_pkg::*; + + `uvm_info(`gfn, "scanning sw resets", UVM_LOW) + sw_reset = 1; + parent_rst_n = 1; + cycles_to_sw_release = 4; + cycles_to_child_release = 5; + cycles_to_child_reset = ScanSweepBeforeCycles; + for (cycles_to_sw_reset = 0; cycles_to_sw_reset < ScanSweepCycles; ++cycles_to_sw_reset) begin + int error_count = 0; + int delta_cycles = cycles_to_sw_reset - cycles_to_child_reset; + `uvm_info(`gfn, $sformatf("Sending sw reset %0d cycles from child", delta_cycles), UVM_HIGH) + run_iterations("sw reset", delta_cycles, error_count); + `uvm_info(`gfn, $sformatf( + "Scan sw reset with cycles delta %0d total errors %0d / %0d", + delta_cycles, + error_count, + IterationsPerDelta + ), UVM_LOW) + `DV_CHECK((delta_cycles >= 3) || (error_count == 0)) + `DV_CHECK((delta_cycles <= 3) || (error_count == IterationsPerDelta)) + end + endtask + + task scan_sw_release(); + import uvm_pkg::*; + + `uvm_info(`gfn, "scanning sw releases", UVM_LOW) + sw_reset = 1; + parent_rst_n = 1; + cycles_to_sw_reset = 4; + cycles_to_child_reset = 5; + cycles_to_child_release = ScanSweepBeforeCycles; + for ( + cycles_to_sw_release = 0; cycles_to_sw_release < ScanSweepCycles; ++cycles_to_sw_release + ) begin + int error_count = 0; + int delta_cycles = cycles_to_sw_release - cycles_to_child_release; + `uvm_info(`gfn, $sformatf("Sending sw release %0d cycles from child", delta_cycles), UVM_HIGH) + run_iterations("sw release", delta_cycles, error_count); + `uvm_info(`gfn, $sformatf( + "Scan sw release with cycles delta %0d total errors %0d / %0d", + delta_cycles, + error_count, + IterationsPerDelta + ), UVM_LOW) + `DV_CHECK((delta_cycles < -8) || (delta_cycles > 3) || (error_count == 0)) + `DV_CHECK(((delta_cycles > -38) && (delta_cycles < 5)) || (error_count == IterationsPerDelta)) + end + endtask + + task inject_fsm_errors(); + sec_cm_pkg::sec_cm_base_if_proxy if_proxy = sec_cm_pkg::find_sec_cm_if_proxy( + "tb.dut.u_state_regs", 0 + ); + `DV_CHECK(!reset_vif.fsm_err_o) + repeat (10) begin + clk_rst_vif.wait_clks(5); + if_proxy.inject_fault(); + clk_rst_vif.wait_clks(5); + if_proxy.restore_fault(); + `DV_CHECK(reset_vif.fsm_err_o) + apply_resets(); + `DV_CHECK(!reset_vif.fsm_err_o) + end + clk_rst_vif.wait_clks(5); + endtask + + task body(); + import uvm_pkg::*; + + foreach (sec_cm_pkg::sec_cm_if_proxy_q[i]) begin + `uvm_info(`gfn, $sformatf("Path of proxy: %0s", sec_cm_pkg::sec_cm_if_proxy_q[i].path), + UVM_MEDIUM) + end + clk_rst_vif.set_period_ps(ClkPeriod); + clk_rst_vif.set_active(); + child_clk_rst_vif.set_period_ps(ChildFastClkPeriod); + child_clk_rst_vif.set_active(); + `DV_CHECK_RANDOMIZE_FATAL(this); + + `uvm_info(`gfn, "Past set active", UVM_MEDIUM) + set_quiescent(); + apply_resets(); + + // Run with child clock faster than reference. + set_child_period(ChildClkFaster); + clk_rst_vif.wait_clks(20); + + set_quiescent(); + apply_resets(); + scan_parent_rst(); + + set_quiescent(); + apply_resets(); + scan_parent_release(); + + set_quiescent(); + apply_resets(); + scan_sw_rst(); + + set_quiescent(); + apply_resets(); + scan_sw_release(); + + set_quiescent(); + apply_resets(); + + // Run with child clock slower than reference. + set_child_period(ChildClkSlower); + clk_rst_vif.wait_clks(20); + + set_quiescent(); + apply_resets(); + scan_parent_rst(); + + set_quiescent(); + apply_resets(); + scan_parent_release(); + + set_quiescent(); + apply_resets(); + scan_sw_rst(); + + set_quiescent(); + apply_resets(); + scan_sw_release(); + + // And inject sparse fsm errors. + set_quiescent(); + apply_resets(); + inject_fsm_errors(); + endtask +endclass + +module tb; + import uvm_pkg::*; + + reset_class reset_cl; + + wire clk_i; + wire rst_ni; + wire child_clk_i; + wire unused_child_rst_ni; + + bind prim_sparse_fsm_flop prim_sparse_fsm_flop_if #( + .Width(Width), + .CustomForceName(CustomForceName) + ) prim_sparse_fsm_flop_if (.*); + + clk_rst_if clk_rst_if ( + .clk (clk_i), + .rst_n(rst_ni) + ); + clk_rst_if child_clk_rst_if ( + .clk (child_clk_i), + .rst_n(child_rst_ni) + ); + rstmgr_cnsty_chk_if rstmgr_cnsty_chk_if (); + + logic sw_rst_req_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + sw_rst_req_q <= '0; + end else if (sw_rst_req_q && rstmgr_cnsty_chk_if.sw_rst_req_clr_o) begin + sw_rst_req_q <= '0; + end else if (!sw_rst_req_q && rstmgr_cnsty_chk_if.sw_rst_req_i && + !rstmgr_cnsty_chk_if.sw_rst_req_clr_o) begin + sw_rst_req_q <= 1'b1; + end + end + + logic leaf_chk_rst_n; + prim_rst_sync u_prim_rst_sync ( + .clk_i (child_clk_i), + .d_i (rst_ni), + .q_o (leaf_chk_rst_n), + .scan_rst_ni(1'b1), + .scanmode_i(prim_mubi_pkg::MuBi4False) + ); + + rstmgr_cnsty_chk dut ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .child_clk_i(child_clk_i), + .child_rst_ni(rstmgr_cnsty_chk_if.child_rst_ni), + .child_chk_rst_ni(leaf_chk_rst_n), + .parent_rst_ni(rstmgr_cnsty_chk_if.parent_rst_ni), + .sw_rst_req_i(rstmgr_cnsty_chk_if.sw_rst_req_i | sw_rst_req_q), + .sw_rst_req_clr_o(rstmgr_cnsty_chk_if.sw_rst_req_clr_o), + .err_o(rstmgr_cnsty_chk_if.err_o), + .fsm_err_o(rstmgr_cnsty_chk_if.fsm_err_o) + ); + + // set this to one to avoid a SVA error + // This SVA is to ensure we have a fatal alert check attached to the FSM error, but this is unit + // level testbench, no alert will occur. + assign dut.u_state_regs.unused_assert_connected = 1; + initial begin + automatic dv_utils_pkg::dv_report_server dv_report_server = new(); + $timeformat(-12, 0, " ps", 12); + uvm_report_server::set_server(dv_report_server); + reset_cl = new(clk_rst_if, child_clk_rst_if, rstmgr_cnsty_chk_if); + reset_cl.body(); + dv_report_server.report_summarize(); + $finish(); + end + +endmodule : tb diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_sim.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_sim.core new file mode 100644 index 00000000000..4bc88f07a80 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_sim.core @@ -0,0 +1,30 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:rstmgr_sim:0.1 +description: "RSTMGR DV sim target" +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:rstmgr + + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:rstmgr_test:0.1 + - lowrisc:darjeeling_no_ibex_dv:rstmgr_sva:0.1 + files: + - tb.sv + - cov/rstmgr_cov_bind.sv + file_type: systemVerilogSource + +targets: + sim: &sim_target + toplevel: tb + filesets: + - files_rtl + - files_dv + default_tool: vcs + + lint: + <<: *sim_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson new file mode 100644 index 00000000000..83937eb940b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson @@ -0,0 +1,109 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + // Name of the sim cfg - typically same as the name of the DUT. + name: rstmgr + + // Top level dut name (sv module). + dut: rstmgr + + // Top level testbench name (sv module). + tb: tb + + // Simulator used to sign off this block + tool: vcs + + // Fusesoc core file used for building the file list. + fusesoc_core: lowrisc:darjeeling_no_ibex_dv:rstmgr_sim:0.1 + + // Testplan hjson file. + testplan: "{self_dir}/../data/rstmgr_testplan.hjson" + + // RAL spec - used to generate the RAL model. + ral_spec: "{self_dir}/../data/rstmgr.hjson" + + // Import additional common sim cfg files. + import_cfgs: [// Project wide common sim cfg file + "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson", + // Common CIP test lists + "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson", + "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson", + // Just run the stress_all sequence, and don't inject random + // resets since we may get overlapping resets due to sequences + // that inject them. + "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson" + ] + + // Specific exclusion files. + vcs_cov_excl_files: ["{self_dir}/cov/rstmgr_unr_excl.el"] + + // Overrides + overrides: [ + { + name: default_vcs_cov_cfg_file + value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{self_dir}/cov/rstmgr_cover.cfg+{self_dir}/cov/rstmgr_tgl_excl.cfg" + } + ] + + // Add additional tops for simulation. + sim_tops: ["rstmgr_bind", "rstmgr_cov_bind", + "sec_cm_prim_sparse_fsm_flop_bind", + "sec_cm_prim_onehot_check_bind"] + + // Default iterations for all tests - each test entry can override this. + reseed: 50 + + // Default UVM test and seq class name. + uvm_test: rstmgr_base_test + uvm_test_seq: rstmgr_base_vseq + + // Enable cdc instrumentation. + run_opts: ["+cdc_instrumentation_enabled=1"] + + // List of test specifications. + tests: [ + { + name: rstmgr_smoke + uvm_test_seq: rstmgr_smoke_vseq + } + { + name: rstmgr_por_stretcher + uvm_test_seq: rstmgr_por_stretcher_vseq + } + { + name: rstmgr_reset + uvm_test_seq: rstmgr_reset_vseq + } + { + name: rstmgr_sw_rst_reset_race + uvm_test_seq: rstmgr_sw_rst_reset_race_vseq + } + { + name: rstmgr_sw_rst + uvm_test_seq: rstmgr_sw_rst_vseq + } + { + name: rstmgr_sec_cm_scan_intersig_mubi + uvm_test_seq: rstmgr_sec_cm_scan_intersig_mubi_vseq + } + { + name: rstmgr_leaf_rst_cnsty + uvm_test_seq: rstmgr_leaf_rst_cnsty_vseq + } + { + name: rstmgr_leaf_rst_shadow_attack + uvm_test_seq: rstmgr_leaf_rst_shadow_attack_vseq + } + ] + + // List of regressions. + regressions: [ + { + name: smoke + tests: ["rstmgr_smoke"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv new file mode 100644 index 00000000000..e3467c7d728 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_attrs_sva_if.sv @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has assertions that check the read-only value of the alert and cpu_info_attr. +interface rstmgr_attrs_sva_if ( + input logic rst_ni, + input int actual_alert_info_attr, + input int actual_cpu_info_attr, + input int expected_alert_info_attr, + input int expected_cpu_info_attr +); + + initial + @(posedge rst_ni) begin + `ASSERT_I(AlertInfoAttr_A, actual_alert_info_attr == expected_alert_info_attr) + `ASSERT_I(CpuInfoAttr_A, actual_cpu_info_attr == expected_cpu_info_attr) + end +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv new file mode 100644 index 00000000000..5a420f006fb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_bind.sv @@ -0,0 +1,89 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module rstmgr_bind; +`ifndef GATE_LEVEL + bind rstmgr tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); + + // In top-level testbench, do not bind the csr_assert_fpv to reduce simulation time. +`ifndef TOP_LEVEL_DV + bind rstmgr rstmgr_csr_assert_fpv rstmgr_csr_assert (.clk_i, .rst_ni, .h2d(tl_i), .d2h(tl_o)); +`endif + + bind rstmgr rstmgr_cascading_sva_if rstmgr_cascading_sva_if ( + .clk_i, + .clk_aon_i, + .clk_io_i, + .clk_io_div2_i, + .clk_io_div4_i, + .clk_main_i, + .por_n_i, + .scan_rst_ni, + .scanmode_i, + .resets_o, + .rst_lc_req(pwr_i.rst_lc_req), + .rst_sys_req(pwr_i.rst_sys_req), + .rst_lc_src_n(pwr_o.rst_lc_src_n), + .rst_sys_src_n(pwr_o.rst_sys_src_n) + ); + + bind rstmgr rstmgr_attrs_sva_if rstmgr_attrs_sva_if ( + .rst_ni, + .actual_alert_info_attr(int'(hw2reg.alert_info_attr)), + .actual_cpu_info_attr(int'(hw2reg.cpu_info_attr)), + .expected_alert_info_attr(($bits(alert_dump_i) + 31) / 32), + .expected_cpu_info_attr(($bits(cpu_dump_i) + 31) / 32) + ); + + bind rstmgr pwrmgr_rstmgr_sva_if #( + .PowerDomains(rstmgr_pkg::PowerDomains) + ) pwrmgr_rstmgr_sva_if ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clk_slow_i(clk_aon_i), + .rst_slow_ni(&rst_por_aon_n), + // These are actually used for checks. + .rst_lc_req(pwr_i.rst_lc_req), + .rst_sys_req(pwr_i.rst_sys_req), + // The inputs from rstmgr. + .rst_lc_src_n(pwr_o.rst_lc_src_n), + .rst_sys_src_n(pwr_o.rst_sys_src_n) + ); + + bind rstmgr rstmgr_sw_rst_sva_if rstmgr_sw_rst_sva_if ( + .clk_i({ + clk_io_div4_i, + clk_io_div4_i, + clk_io_div4_i + }), + .rst_ni, + .parent_rst_n(rst_sys_src_n[1]), + .ctrl_ns(reg2hw.sw_rst_ctrl_n), + .rst_ens({ + rst_en_o.i2c0[1] == prim_mubi_pkg::MuBi4True, + rst_en_o.spi_host0[1] == prim_mubi_pkg::MuBi4True, + rst_en_o.spi_device[1] == prim_mubi_pkg::MuBi4True + }), + .rst_ns({ + resets_o.rst_i2c0_n[1], + resets_o.rst_spi_host0_n[1], + resets_o.rst_spi_device_n[1] + }) + ); + + bind rstmgr rstmgr_rst_en_track_sva_if rstmgr_rst_en_track_sva_if ( + .resets_i(resets_o), + .reset_en_i(rst_en_o), + .clk_aon_i, + .clk_io_i, + .clk_io_div2_i, + .clk_io_div4_i, + .clk_main_i, + .rst_por_ni(rst_por_ni) + ); + +`endif +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv new file mode 100644 index 00000000000..aea637a3670 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv @@ -0,0 +1,186 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has assertions that check the reset outputs of rstmgr cascade properly. +// This means higher level resets always cause the lower level ones to assert. +// The hierarchy is +// por > lc > sys > specific peripherals +// In addition, a scan reset is at the same level as por. +// +// Local terminology: A cascading relationship is between an "above" and a "below" reset. +// +// Some individual reset outputs will always be off. Allowing for this in general would +// weaken the property that some resets MUST rise following other rise. +// +// Peripheral resets cascade from sys, and are checked in rstmgr_sw_rst_sva_if since they +// require additional inputs. +interface rstmgr_cascading_sva_if ( + input logic clk_i, + input logic clk_aon_i, + input logic clk_io_i, + input logic clk_io_div2_i, + input logic clk_io_div4_i, + input logic clk_main_i, + input [rstmgr_pkg::PowerDomains-1:0] por_n_i, + input rstmgr_pkg::rstmgr_out_t resets_o, + input [rstmgr_pkg::PowerDomains-1:0] rst_lc_req, + input [rstmgr_pkg::PowerDomains-1:0] rst_sys_req, + input [rstmgr_pkg::PowerDomains-1:0] rst_lc_src_n, + input [rstmgr_pkg::PowerDomains-1:0] rst_sys_src_n, + input logic scan_rst_ni, + input prim_mubi_pkg::mubi4_t scanmode_i +); + + // The min and max bounds on the number of cycles for an edge to occur. + typedef struct { + int min; + int max; + } bounds_t; + + // The bounds for a fall and rise edge to occur. + typedef struct { + bounds_t fall; + bounds_t rise; + } edge_bounds_t; + + // This is used to check por_n_i active high leads to a rising edge of rst_por_aon_n[0]. + // The number of cycles with por_n_i stable is 32 plus synchronizers and some filter stages. + localparam edge_bounds_t PorCycles = '{fall: '{min: 0, max: 4}, rise: '{min: 35, max: 40}}; + + // This is used to check for regular synchronizing delay. Reset falls asynchronously so the + // fall min cycles is zero. + localparam edge_bounds_t SyncCycles = '{fall: '{min: 0, max: 3}, rise: '{min: 1, max: 3}}; + + // Cycles are counted from the output rst_por_aon_n or scan reset edges. The rise times can be + // higher since in the chip the aon reset goes through the pwrmgr slow fsm where it causes an + // lc rise request and there may be multiple synchronizers in the path. + localparam edge_bounds_t LcCycles = '{fall: '{min: 0, max: 4}, rise: '{min: 1, max: 4}}; + + // In the real system the rise of rst_lc_src_n is triggered by the pwr_i.rst_lc_req input, + // which can take a few cycles since it comes from the pwrmgr after it gets reset, + // is generated with the aon clock, and gets synchronized before it triggers + // a rise in rst_lc_src_n. There is an SVA for the rise in pwrmgr_rstmgr_sva_if. + + // The cycles are counted from Lc edges. + localparam edge_bounds_t SysCycles = '{fall: '{min: 0, max: 3}, rise: '{min: 1, max: 5}}; + + // The different peripheral edges are synchronized to their respective clocks, + // so these counts assume synchronization and are triggered on the correct clock. + localparam edge_bounds_t PeriCycles = '{fall: '{min: 0, max: 4}, rise: '{min: 2, max: 8}}; + + bit disable_sva; + + // Macros to avoid excessive boiler-plate code below. + `define FALL_ASSERT(_name, _from, _to, _cycles, _clk) \ + `ASSERT(_name``AboveFall_A, \ + $fell(_from) |-> ##[_cycles.fall.min:_cycles.fall.max] _from || !_to, _clk, \ + disable_sva) + + `define RISE_ASSERTS(_name, _from, _to, _cycles, _clk) \ + `ASSERT(_name``AboveRise_A, \ + $rose(_from) ##1 _from [* _cycles.rise.min] |=> ##[0:_cycles.rise.max-_cycles.rise.min] (!_from || _to), _clk, \ + disable_sva) + + `define CASCADED_ASSERTS(_name, _from, _to, _cycles, _clk) \ + `FALL_ASSERT(_name, _from, _to, _cycles, _clk) \ + `RISE_ASSERTS(_name, _from, _to, _cycles, _clk) + + // A fall in por_n_i leads to a fall in rst_por_aon_n[0]. + `FALL_ASSERT(CascadePorToAon, por_n_i[rstmgr_pkg::DomainAonSel], + resets_o.rst_por_aon_n[rstmgr_pkg::DomainAonSel], PorCycles, clk_aon_i) + + // A number of consecutive cycles with por_n_i inactive (high) should cause the aon resets to + // become inactive. This checks POR stretching. + + // The antecedent: por_n_i rising and being active for enough cycles. + + logic scanmode; + always_comb scanmode = prim_mubi_pkg::mubi4_test_true_strict(scanmode_i); + + logic scan_reset_n; + always_comb scan_reset_n = !scanmode || scan_rst_ni; + + // In scanmode only scan_rst_ni controls reset, so por_n_i is ignored. + logic aon_por_n_i; + always_comb aon_por_n_i = por_n_i[rstmgr_pkg::DomainAonSel] && !scanmode; + + sequence PorStable_S; + $rose( + aon_por_n_i + ) ##1 aon_por_n_i [* PorCycles.rise.min]; + endsequence + + // The reset stretching assertion. + `ASSERT(StablePorToAonRise_A, + PorStable_S |-> ##[0:(PorCycles.rise.max-PorCycles.rise.min)] + !aon_por_n_i || resets_o.rst_por_aon_n[0], + clk_aon_i, disable_sva) + + // The scan reset to Por. + `ASSERT(ScanRstToAonRise_A, scan_reset_n && scanmode |-> resets_o.rst_por_aon_n[0], clk_aon_i, + disable_sva) + + logic [rstmgr_pkg::PowerDomains-1:0] effective_aon_rst_n; + always_comb + effective_aon_rst_n = resets_o.rst_por_aon_n & {rstmgr_pkg::PowerDomains{scan_reset_n}}; + + // The AON reset triggers the various POR reset for the different clock domains through + // synchronizers. + // The current system doesn't have any consumers of domain 1 por_io_div4, and thus only domain 0 + // cascading is checked here. + `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0], + resets_o.rst_por_io_div4_n[0], SyncCycles, clk_io_div4_i) + + // The internal reset is triggered by one of synchronized por. + logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n; + always_comb por_rst_n = resets_o.rst_por_aon_n; + + logic [rstmgr_pkg::PowerDomains-1:0] local_rst_or_lc_req_n; + always_comb local_rst_or_lc_req_n = por_rst_n & ~rst_lc_req; + + logic [rstmgr_pkg::PowerDomains-1:0] lc_rst_or_sys_req_n; + always_comb lc_rst_or_sys_req_n = por_rst_n & ~rst_sys_req; + + for (genvar pd = 0; pd < rstmgr_pkg::PowerDomains; ++pd) begin : g_power_domains + // The root lc reset is triggered either by the internal reset, or by the pwr_i.rst_lc_req + // input. The latter is checked independently in pwrmgr_rstmgr_sva_if. + `CASCADED_ASSERTS(CascadeLocalRstToLc, local_rst_or_lc_req_n[pd], rst_lc_src_n[pd], LcCycles, + clk_i) + + // The root sys reset is triggered by the lc reset, or independently by external requests. + // The latter is checked independently in pwrmgr_rstmgr_sva_if. + `CASCADED_ASSERTS(CascadeLcToSys, lc_rst_or_sys_req_n[pd], rst_sys_src_n[pd], SysCycles, clk_i) + + // Controlled by rst_sys_src_n. + if (pd == rstmgr_pkg::DomainAonSel) begin : gen_sys_io_div4_chk + `CASCADED_ASSERTS(CascadeSysToSysIoDiv4, rst_sys_src_n[pd], resets_o.rst_sys_io_div4_n[pd], + SysCycles, clk_io_div4_i) + end + end + + // Aon to POR + `CASCADED_ASSERTS(CascadeEffAonToRstPor, effective_aon_rst_n[rstmgr_pkg::DomainAonSel], + resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i) + `CASCADED_ASSERTS(CascadeEffAonToRstPorIo, effective_aon_rst_n[rstmgr_pkg::DomainAonSel], + resets_o.rst_por_io_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_i) + `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv2, effective_aon_rst_n[rstmgr_pkg::DomainAonSel], + resets_o.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_io_div2_i) + + + // Controlled by rst_lc_src_n. + `CASCADED_ASSERTS(CascadeLcToLcAon, rst_lc_src_n[rstmgr_pkg::DomainAonSel], + resets_o.rst_lc_aon_n[rstmgr_pkg::DomainAonSel], SysCycles, clk_aon_i) + `CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::Domain0Sel], + resets_o.rst_lc_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i) + + // Controlled by rst_sys_src_n. + `CASCADED_ASSERTS(CascadeSysToSys, rst_sys_src_n[rstmgr_pkg::Domain0Sel], + resets_o.rst_sys_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_main_i) + `CASCADED_ASSERTS(CascadeLcToLcShadowed, rst_lc_src_n[rstmgr_pkg::Domain0Sel], + resets_o.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i) + + `undef FALL_ASSERT + `undef RISE_ASSERTS + `undef CASCADED_ASSERTS +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv new file mode 100644 index 00000000000..916aa9996f1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_rst_en_track_sva_if.sv @@ -0,0 +1,242 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This checks that the outgoing resets and the corresponding reset enable going to alert handler +// are shifted by a single clock cycle. +interface rstmgr_rst_en_track_sva_if ( + input rstmgr_pkg::rstmgr_out_t resets_i, + input rstmgr_pkg::rstmgr_rst_en_t reset_en_i, + input logic clk_aon_i, + input logic clk_io_div4_i, + input logic clk_main_i, + input logic clk_io_i, + input logic clk_io_div2_i, + input logic rst_por_ni +); + import rstmgr_pkg::DomainAonSel; + import rstmgr_pkg::Domain0Sel; + localparam int DELAY = 1; + + `ASSERT(D0RstPorAonEnTracksRstPorAonActive_A, + $fell(resets_i.rst_por_aon_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.por_aon[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_aon_i, + !rst_por_ni) + + `ASSERT(D0RstPorAonEnTracksRstPorAonInactive_A, + $rose(resets_i.rst_por_aon_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_por_aon_n[Domain0Sel] || + reset_en_i.por_aon[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstPorAonEnTracksRstPorAonActive_A, + $fell(resets_i.rst_por_aon_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por_aon[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstPorAonEnTracksRstPorAonInactive_A, + $rose(resets_i.rst_por_aon_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_aon_n[DomainAonSel] || + reset_en_i.por_aon[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstPorEnTracksRstPorActive_A, + $fell(resets_i.rst_por_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstPorEnTracksRstPorInactive_A, + $rose(resets_i.rst_por_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_n[DomainAonSel] || + reset_en_i.por[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoEnTracksRstPorIoActive_A, + $fell(resets_i.rst_por_io_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por_io[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoEnTracksRstPorIoInactive_A, + $rose(resets_i.rst_por_io_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_io_n[DomainAonSel] || + reset_en_i.por_io[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A, + $fell(resets_i.rst_por_io_div2_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por_io_div2[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div2_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A, + $rose(resets_i.rst_por_io_div2_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_io_div2_n[DomainAonSel] || + reset_en_i.por_io_div2[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div2_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A, + $fell(resets_i.rst_por_io_div4_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.por_io_div4[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A, + $rose(resets_i.rst_por_io_div4_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_por_io_div4_n[DomainAonSel] || + reset_en_i.por_io_div4[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstLcShadowedEnTracksRstLcShadowedActive_A, + $fell(resets_i.rst_lc_shadowed_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.lc_shadowed[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_main_i, + !rst_por_ni) + + `ASSERT(D0RstLcShadowedEnTracksRstLcShadowedInactive_A, + $rose(resets_i.rst_lc_shadowed_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_lc_shadowed_n[Domain0Sel] || + reset_en_i.lc_shadowed[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstLcShadowedEnTracksRstLcShadowedActive_A, + $fell(resets_i.rst_lc_shadowed_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_shadowed[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstLcShadowedEnTracksRstLcShadowedInactive_A, + $rose(resets_i.rst_lc_shadowed_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_shadowed_n[DomainAonSel] || + reset_en_i.lc_shadowed[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_main_i, + !rst_por_ni) + + `ASSERT(DAonRstLcAonEnTracksRstLcAonActive_A, + $fell(resets_i.rst_lc_aon_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_aon[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstLcAonEnTracksRstLcAonInactive_A, + $rose(resets_i.rst_lc_aon_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_aon_n[DomainAonSel] || + reset_en_i.lc_aon[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_aon_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoEnTracksRstLcIoActive_A, + $fell(resets_i.rst_lc_io_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_io[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoEnTracksRstLcIoInactive_A, + $rose(resets_i.rst_lc_io_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_io_n[DomainAonSel] || + reset_en_i.lc_io[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A, + $fell(resets_i.rst_lc_io_div2_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_io_div2[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div2_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A, + $rose(resets_i.rst_lc_io_div2_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_io_div2_n[DomainAonSel] || + reset_en_i.lc_io_div2[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div2_i, + !rst_por_ni) + + `ASSERT(D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A, + $fell(resets_i.rst_lc_io_div4_shadowed_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.lc_io_div4_shadowed[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A, + $rose(resets_i.rst_lc_io_div4_shadowed_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_lc_io_div4_shadowed_n[Domain0Sel] || + reset_en_i.lc_io_div4_shadowed[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A, + $fell(resets_i.rst_lc_io_div4_shadowed_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.lc_io_div4_shadowed[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A, + $rose(resets_i.rst_lc_io_div4_shadowed_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_lc_io_div4_shadowed_n[DomainAonSel] || + reset_en_i.lc_io_div4_shadowed[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A, + $fell(resets_i.rst_sys_io_div4_n[DomainAonSel]) |-> ##[0:DELAY] + reset_en_i.sys_io_div4[DomainAonSel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A, + $rose(resets_i.rst_sys_io_div4_n[DomainAonSel]) |-> ##DELAY + !resets_i.rst_sys_io_div4_n[DomainAonSel] || + reset_en_i.sys_io_div4[DomainAonSel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstSpiDeviceEnTracksRstSpiDeviceActive_A, + $fell(resets_i.rst_spi_device_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.spi_device[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A, + $rose(resets_i.rst_spi_device_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_spi_device_n[Domain0Sel] || + reset_en_i.spi_device[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstSpiHost0EnTracksRstSpiHost0Active_A, + $fell(resets_i.rst_spi_host0_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.spi_host0[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstSpiHost0EnTracksRstSpiHost0Inactive_A, + $rose(resets_i.rst_spi_host0_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_spi_host0_n[Domain0Sel] || + reset_en_i.spi_host0[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstI2c0EnTracksRstI2c0Active_A, + $fell(resets_i.rst_i2c0_n[Domain0Sel]) |-> ##[0:DELAY] + reset_en_i.i2c0[Domain0Sel] == prim_mubi_pkg::MuBi4True, + clk_io_div4_i, + !rst_por_ni) + + `ASSERT(D0RstI2c0EnTracksRstI2c0Inactive_A, + $rose(resets_i.rst_i2c0_n[Domain0Sel]) |-> ##DELAY + !resets_i.rst_i2c0_n[Domain0Sel] || + reset_en_i.i2c0[Domain0Sel] == prim_mubi_pkg::MuBi4False, + clk_io_div4_i, + !rst_por_ni) + +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sva.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sva.core new file mode 100644 index 00000000000..8d859a1f357 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sva.core @@ -0,0 +1,35 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:rstmgr_sva:0.1 +description: "RSTMGR assertion modules and bind file." +filesets: + files_dv: + depend: + - lowrisc:prim:mubi + - lowrisc:darjeeling_no_ibex_ip:rstmgr_pkg:0.1 + - lowrisc:fpv:csr_assert_gen + - lowrisc:darjeeling_no_ibex_dv:rstmgr_sva_ifs:0.1 + + files: + - rstmgr_bind.sv + file_type: systemVerilogSource + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../../data/rstmgr.hjson + +targets: + default: &default_target + filesets: + - files_dv + generate: + - csr_assert_gen + formal: + <<: *default_target + filesets: + - files_dv + toplevel: rstmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sva_ifs.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sva_ifs.core new file mode 100644 index 00000000000..9b45f9a0e0b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sva_ifs.core @@ -0,0 +1,25 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:rstmgr_sva_ifs:0.1 +description: "RSTMGR cascading resets assertion interface." +filesets: + files_dv: + depend: + - lowrisc:ip:lc_ctrl_pkg + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg + - lowrisc:dv:pwrmgr_rstmgr_sva_if + - lowrisc:darjeeling_no_ibex_ip:rstmgr + + files: + - rstmgr_attrs_sva_if.sv + - rstmgr_cascading_sva_if.sv + - rstmgr_rst_en_track_sva_if.sv + - rstmgr_sw_rst_sva_if.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv new file mode 100644 index 00000000000..7be1e059407 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/sva/rstmgr_sw_rst_sva_if.sv @@ -0,0 +1,44 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This has assertions that check the output resets read-only value of the alert and cpu_info_attr. +interface rstmgr_sw_rst_sva_if ( + input logic [rstmgr_reg_pkg::NumSwResets-1:0] clk_i, + input logic rst_ni, + input logic parent_rst_n, + input logic [rstmgr_reg_pkg::NumSwResets-1:0] ctrl_ns, + input logic [rstmgr_reg_pkg::NumSwResets-1:0] rst_ens, + input logic [rstmgr_reg_pkg::NumSwResets-1:0] rst_ns +); + parameter int RiseMin = 2; + parameter int RiseMax = 12; + + bit disable_sva; + + for (genvar i = 0; i < rstmgr_reg_pkg::NumSwResets; ++i) begin : gen_assertions + logic rst_cause; + always_comb rst_cause = !parent_rst_n || !ctrl_ns[i]; + + sequence CauseReadyOn_S; + $rose( + rst_cause + ) ##1 rst_cause [* RiseMin]; + endsequence + + sequence CauseReadyOff_S; + $fell( + rst_cause + ) ##1 !rst_cause [* RiseMin]; + endsequence + + `ASSERT(RstNOn_A, CauseReadyOn_S |=> ##[0:RiseMax-RiseMin] !rst_cause || !rst_ns[i], clk_i[i], + !rst_ni || disable_sva) + `ASSERT(RstNOff_A, CauseReadyOff_S |=> ##[0:RiseMax-RiseMin] rst_cause || rst_ns[i], clk_i[i], + !rst_ni || disable_sva) + `ASSERT(RstEnOn_A, CauseReadyOn_S |=> ##[0:RiseMax-RiseMin] !rst_cause || rst_ens[i], clk_i[i], + !rst_ni || disable_sva) + `ASSERT(RstEnOff_A, CauseReadyOff_S |=> ##[0:RiseMax-RiseMin] rst_cause || !rst_ens[i], + clk_i[i], !rst_ni || disable_sva) + end +endinterface diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tb.sv new file mode 100644 index 00000000000..126335d3950 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tb.sv @@ -0,0 +1,144 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +module tb; + // dep packages + import uvm_pkg::*; + import dv_utils_pkg::*; + import rstmgr_env_pkg::*; + import rstmgr_test_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + wire clk, rst_n; + clk_rst_if clk_rst_if ( + .clk, + .rst_n + ); + + wire clk_aon; + clk_rst_if aon_clk_rst_if ( + .clk (clk_aon), + .rst_n() + ); + + wire clk_io_div4; + clk_rst_if io_div4_clk_rst_if ( + .clk (clk_io_div4), + .rst_n() + ); + + wire clk_main; + clk_rst_if main_clk_rst_if ( + .clk (clk_main), + .rst_n() + ); + + wire clk_io; + clk_rst_if io_clk_rst_if ( + .clk (clk_io), + .rst_n() + ); + + wire clk_io_div2; + clk_rst_if io_div2_clk_rst_if ( + .clk (clk_io_div2), + .rst_n() + ); + + + tl_if tl_if ( + .clk, + .rst_n(rstmgr_if.resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + + rstmgr_if rstmgr_if ( + .clk_aon, + .clk, + .rst_n + ); + + initial begin + clk_rst_if.set_active(); + aon_clk_rst_if.set_active(); + io_clk_rst_if.set_active(); + io_div2_clk_rst_if.set_active(); + io_div4_clk_rst_if.set_active(); + main_clk_rst_if.set_active(); + end + + `DV_ALERT_IF_CONNECT() + + // dut + // IMPORTANT: Notice the rst_ni input is connected to one of dut's outputs. + // This is consistent with rstmgr being the only source of resets. + rstmgr dut ( + .clk_i (clk), + .rst_ni (rstmgr_if.resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .clk_aon_i (clk_aon), + .clk_io_i (clk_io), + .clk_io_div2_i(clk_io_div2), + .clk_io_div4_i(clk_io_div4), + .clk_main_i (clk_main), + .clk_por_i (clk_io_div4), + .rst_por_ni (rstmgr_if.resets_o.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), + + .tl_i (tl_if.h2d), + .tl_o (tl_if.d2h), + .alert_rx_i(alert_rx), + .alert_tx_o(alert_tx), + + .por_n_i(rstmgr_if.por_n), + + .pwr_i(rstmgr_if.pwr_i), + .pwr_o(rstmgr_if.pwr_o), + + .sw_rst_req_o (rstmgr_if.sw_rst_req_o), + + .alert_dump_i(rstmgr_if.alert_dump_i), + .cpu_dump_i (rstmgr_if.cpu_dump_i), + + .scan_rst_ni(rstmgr_if.scan_rst_ni), + .scanmode_i (rstmgr_if.scanmode_i), + + .rst_en_o(rstmgr_if.rst_en_o), + .resets_o(rstmgr_if.resets_o) + ); + + initial begin + // drive clk and rst_n from clk_rst_if + clk_rst_if.set_active(); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "aon_clk_rst_vif", + aon_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_clk_rst_vif", + io_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_div2_clk_rst_vif", + io_div2_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "io_div4_clk_rst_vif", + io_div4_clk_rst_if); + uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "main_clk_rst_vif", + main_clk_rst_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if); + + uvm_config_db#(virtual pwrmgr_rstmgr_sva_if)::set(null, "*.env", "pwrmgr_rstmgr_sva_vif", + dut.pwrmgr_rstmgr_sva_if); + uvm_config_db#(virtual rstmgr_cascading_sva_if)::set(null, "*.env", "rstmgr_cascading_sva_vif", + dut.rstmgr_cascading_sva_if); + uvm_config_db#(virtual rstmgr_if)::set(null, "*.env", "rstmgr_vif", rstmgr_if); + + $timeformat(-12, 0, " ps", 12); + run_test(); + end + + initial begin + // This may help any code that depends on clk_rst_vif.rst_n in the infrastructure: they won't + // be able to change but at least the reset value will be true to the environment. + clk_rst_if.drive_rst_n = 1'b0; + force clk_rst_if.rst_n = rstmgr_if.resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]; + end + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tests/rstmgr_base_test.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tests/rstmgr_base_test.sv new file mode 100644 index 00000000000..a3eaf46e04f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tests/rstmgr_base_test.sv @@ -0,0 +1,20 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +class rstmgr_base_test extends cip_base_test #( + .CFG_T(rstmgr_env_cfg), + .ENV_T(rstmgr_env) +); + + `uvm_component_utils(rstmgr_base_test) + `uvm_component_new + + // the base class dv_base_test creates the following instances: + // rstmgr_env_cfg: cfg + // rstmgr_env: env + + // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in + // the run_phase; as such, nothing more needs to be done + +endclass : rstmgr_base_test diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tests/rstmgr_test.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tests/rstmgr_test.core new file mode 100644 index 00000000000..94e6b578677 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tests/rstmgr_test.core @@ -0,0 +1,19 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_dv:rstmgr_test:0.1 +description: "RSTMGR DV UVM test" +filesets: + files_dv: + depend: + - lowrisc:darjeeling_no_ibex_dv:rstmgr_env:0.1 + files: + - rstmgr_test_pkg.sv + - rstmgr_base_test.sv: {is_include_file: true} + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tests/rstmgr_test_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tests/rstmgr_test_pkg.sv new file mode 100644 index 00000000000..6bc66f09e85 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/dv/tests/rstmgr_test_pkg.sv @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package rstmgr_test_pkg; + // dep packages + import uvm_pkg::*; + import cip_base_pkg::*; + import rstmgr_env_pkg::*; + + // macro includes + `include "uvm_macros.svh" + `include "dv_macros.svh" + + // local types + + // functions + + // package sources + `include "rstmgr_base_test.sv" + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/lint/rstmgr.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/lint/rstmgr.vlt new file mode 100644 index 00000000000..a345f0dcdf9 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/lint/rstmgr.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for rstmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/lint/rstmgr.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/lint/rstmgr.waiver new file mode 100644 index 00000000000..4958290fba5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/lint/rstmgr.waiver @@ -0,0 +1,37 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for rstmgr + +# dedicated reset drivers / muxes +set_reset_drivers prim_clock_mux2 prim_flop_2sync prim_flop +set_clock_drivers prim_clock_buf + +waive -rules TERMINAL_STATE -location {rstmgr_cnsty_chk.sv} -regexp {Terminal state 'Error' is detected} \ + -comment "Intentional terminal state" + +# All leaf resets have a reset multiplexer for scan reset +waive -rules RESET_MUX -location {rstmgr.sv rstmgr_por.sv rstmgr_ctrl.sv} -regexp {Asynchronous reset '(resets_o\.)?rst_[A-Za-z_0-9]+_n(\[[0-9:]+\])?' is driven by a multiplexer} \ + -comment "This is dedicated reset infrastructure, and hence permissible" + +waive -rules RESET_MUX -location {rstmgr_leaf_rst.sv} -regexp {Asynchronous reset 'leaf_rst_o' is driven by a multiplexer} \ + -comment "This is dedicated reset infrastructure, and hence permissible" + +waive -rules RESET_MUX -location {rstmgr_leaf_rst.sv} -regexp {Asynchronous reset 'gen_rst_chk.leaf_chk_rst_n' is driven by a multiplexer here, used as a reset 'rst_dst_ni' at} \ + -comment "This is dedicated reset infrastructure, and hence permissible" + +waive -rules RESET_USE -location {rstmgr.sv} -regexp {'rst_(por_aon_)?n\[1\]' is connected to 'rstmgr_ctrl' port 'rst_.*ni*} \ + -comment "Parent Non always on resets are combined with the always on reset first before being used as resets" + +waive -rules RESET_USE -location {rstmgr.sv} -regexp {rst_lc_src_n.* is connected to 'rstmgr_ctrl' port 'rst_parent_ni.*} \ + -comment "Parent resets are used synchronously instead of directly as async resets" + +waive -rules CONST_FF -location {rstmgr_crash_info.sv} -regexp {Flip-flop \'slots_q\[.*\]\[.*\]\' is driven by constant zeros in module \'rstmgr_crash_info\'} \ + -comment "Some bits int the last slot are tied off to zero." + +waive -rules CONST_FF -location {rstmgr_cnsty_chk.sv} -regexp {Flip-flop '(parent|child)_rst_asserted' is driven by constant zero} \ + -comment "These flipflop inputs are driven by zero." + +waive -rules CONST_FF -location {rstmgr_por.sv} -msg {Flip-flop 'rst_filter_n[0]' is driven by constant one} \ + -comment "This flipflops is a reset filter, and the first index is driven by a constant one." diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr.core new file mode 100644 index 00000000000..a5cded15701 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr.core @@ -0,0 +1,69 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:rstmgr:0.1 +description: "Reset manager RTL" + +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:alert_handler_pkg + - lowrisc:ip:rv_core_ibex_pkg + - lowrisc:ip:tlul + - lowrisc:prim:clock_mux2 + - lowrisc:prim:esc + - lowrisc:prim:lc_sync + - lowrisc:prim:mubi + - lowrisc:prim:clock_buf + - lowrisc:prim:sparse_fsm + - lowrisc:darjeeling_no_ibex_ip:rstmgr_pkg:0.1 + - lowrisc:darjeeling_no_ibex_ip:rstmgr_reg:0.1 + - lowrisc:darjeeling_no_ibex_ip:rstmgr_cnsty_chk:0.1 + files: + - rtl/rstmgr_ctrl.sv + - rtl/rstmgr_por.sv + - rtl/rstmgr_crash_info.sv + - rtl/rstmgr_leaf_rst.sv + - rtl/rstmgr.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/rstmgr.waiver + file_type: waiver + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - files_rtl + toplevel: rstmgr + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr_cnsty_chk.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr_cnsty_chk.core new file mode 100644 index 00000000000..e55ba93572f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr_cnsty_chk.core @@ -0,0 +1,40 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: lowrisc:darjeeling_no_ibex_ip:rstmgr_cnsty_chk:0.1 +description: "Rstmgr consistency checker" +filesets: + files_rtl: + depend: + - lowrisc:prim:all + - lowrisc:prim:sparse_fsm + - lowrisc:ip:rv_core_ibex_pkg + - lowrisc:darjeeling_no_ibex_ip:rstmgr_pkg + files: + - rtl/rstmgr_cnsty_chk.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + +targets: + default: + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr_pkg.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr_pkg.core new file mode 100644 index 00000000000..9aa881d7455 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr_pkg.core @@ -0,0 +1,20 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:rstmgr_pkg:0.1 +description: "Reset manager package" + +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:pwrmgr_pkg + files: + - rtl/rstmgr_reg_pkg.sv + - rtl/rstmgr_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr_reg.core b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr_reg.core new file mode 100644 index 00000000000..95b7d86e117 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rstmgr_reg.core @@ -0,0 +1,21 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:rstmgr_reg:0.1 +description: "Reset manager registers" + +filesets: + files_rtl: + depend: + - lowrisc:tlul:headers + - lowrisc:prim:subreg + - lowrisc:darjeeling_no_ibex_ip:rstmgr_pkg + files: + - rtl/rstmgr_reg_top.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr.sv new file mode 100644 index 00000000000..24c60f189db --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr.sv @@ -0,0 +1,967 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module is the overall reset manager wrapper + +`include "prim_assert.sv" + + +// This top level controller is fairly hardcoded right now, but will be switched to a template +module rstmgr + import rstmgr_pkg::*; + import rstmgr_reg_pkg::*; + import prim_mubi_pkg::mubi4_t; +#( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert signal + parameter int unsigned AlertSkewCycles = 1, + parameter bit SecCheck = 1, + parameter int SecMaxSyncDelay = 2 +) ( + // Primary module clocks + input clk_i, + input rst_ni, + input clk_aon_i, + input clk_io_div4_i, + input clk_main_i, + input clk_io_i, + input clk_io_div2_i, + input clk_por_i, + input rst_por_ni, + + // POR input + input [PowerDomains-1:0] por_n_i, + + // Bus Interface + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // pwrmgr interface + input pwrmgr_pkg::pwr_rst_req_t pwr_i, + output pwrmgr_pkg::pwr_rst_rsp_t pwr_o, + + // software initiated reset request + output mubi4_t sw_rst_req_o, + + // Interface to alert handler + input alert_handler_pkg::alert_crashdump_t alert_dump_i, + + // Interface to cpu crash dump + input rv_core_ibex_pkg::cpu_crash_dump_t cpu_dump_i, + + // dft bypass + input scan_rst_ni, + // SEC_CM: SCAN.INTERSIG.MUBI + input prim_mubi_pkg::mubi4_t scanmode_i, + + // Reset asserted indications going to alert handler + output rstmgr_rst_en_t rst_en_o, + + // reset outputs + output rstmgr_out_t resets_o + +); + + import prim_mubi_pkg::MuBi4False; + import prim_mubi_pkg::MuBi4True; + + // receive POR and stretch + // The por is at first stretched and synced on clk_aon + // The rst_ni and pok_i input will be changed once AST is integrated + logic [PowerDomains-1:0] rst_por_aon_n; + + for (genvar i = 0; i < PowerDomains; i++) begin : gen_rst_por_aon + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] por_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_por_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o(por_scanmode) + ); + + if (i == DomainAonSel) begin : gen_rst_por_aon_normal + rstmgr_por u_rst_por_aon ( + .clk_i(clk_aon_i), + .rst_ni(por_n_i[i]), + .scan_rst_ni, + .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(por_scanmode[0])), + .rst_no(rst_por_aon_n[i]) + ); + + // reset asserted indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender ( + .clk_i(clk_aon_i), + .rst_ni(rst_por_aon_n[i]), + .mubi_i(MuBi4False), + .mubi_o(rst_en_o.por_aon[i]) + ); + end else begin : gen_rst_por_domain + logic rst_por_aon_premux; + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_por_domain_sync ( + .clk_i(clk_aon_i), + // do not release from reset if aon has not + .rst_ni(rst_por_aon_n[DomainAonSel] & por_n_i[i]), + .d_i(1'b1), + .q_o(rst_por_aon_premux) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_por_domain_mux ( + .clk0_i(rst_por_aon_premux), + .clk1_i(scan_rst_ni), + .sel_i(prim_mubi_pkg::mubi4_test_true_strict(por_scanmode[0])), + .clk_o(rst_por_aon_n[i]) + ); + + // reset asserted indication for alert handler + prim_mubi4_sender #( + .ResetValue(MuBi4True) + ) u_prim_mubi4_sender ( + .clk_i(clk_aon_i), + .rst_ni(rst_por_aon_n[i]), + .mubi_i(MuBi4False), + .mubi_o(rst_en_o.por_aon[i]) + ); + end + end + assign resets_o.rst_por_aon_n = rst_por_aon_n; + + logic clk_por; + logic rst_por_n; + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_por_clk_buf ( + .clk_i(clk_por_i), + .clk_o(clk_por) + ); + + prim_clock_buf #( + .NoFpgaBuf(1'b1) + ) u_por_rst_buf ( + .clk_i(rst_por_ni), + .clk_o(rst_por_n) + ); + + //////////////////////////////////////////////////// + // Register Interface // + //////////////////////////////////////////////////// + + rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw; + rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg; + + logic reg_intg_err; + // SEC_CM: BUS.INTEGRITY + // SEC_CM: SW_RST.CONFIG.REGWEN, DUMP_CTRL.CONFIG.REGWEN + rstmgr_reg_top u_reg ( + .clk_i, + .rst_ni, + .clk_por_i (clk_por), + .rst_por_ni (rst_por_n), + .tl_i, + .tl_o, + .reg2hw, + .hw2reg, + .intg_err_o(reg_intg_err) + ); + + + //////////////////////////////////////////////////// + // Errors // + //////////////////////////////////////////////////// + + // consistency check errors + logic [13:0][PowerDomains-1:0] cnsty_chk_errs; + logic [13:0][PowerDomains-1:0] shadow_cnsty_chk_errs; + + // consistency sparse fsm errors + logic [13:0][PowerDomains-1:0] fsm_errs; + logic [13:0][PowerDomains-1:0] shadow_fsm_errs; + + assign hw2reg.err_code.reg_intg_err.d = 1'b1; + assign hw2reg.err_code.reg_intg_err.de = reg_intg_err; + assign hw2reg.err_code.reset_consistency_err.d = 1'b1; + assign hw2reg.err_code.reset_consistency_err.de = |cnsty_chk_errs || + |shadow_cnsty_chk_errs; + assign hw2reg.err_code.fsm_err.d = 1'b1; + assign hw2reg.err_code.fsm_err.de = |fsm_errs || |shadow_fsm_errs; + //////////////////////////////////////////////////// + // Alerts // + //////////////////////////////////////////////////// + logic [NumAlerts-1:0] alert_test, alerts; + + // All of these are fatal alerts + assign alerts[0] = reg2hw.err_code.reg_intg_err.q | + (|reg2hw.err_code.fsm_err.q); + + assign alerts[1] = reg2hw.err_code.reset_consistency_err.q; + + assign alert_test = { + reg2hw.alert_test.fatal_cnsty_fault.q & reg2hw.alert_test.fatal_cnsty_fault.qe, + reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe + }; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .SkewCycles(AlertSkewCycles), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + //////////////////////////////////////////////////// + // Source resets in the system // + // These are hardcoded and not directly used. // + // Instead they act as async reset roots. // + //////////////////////////////////////////////////// + + // The two source reset modules are chained together. The output of one is fed into the + // the second. This ensures that if upstream resets for any reason, the associated downstream + // reset will also reset. + + logic [PowerDomains-1:0] rst_lc_src_n; + logic [PowerDomains-1:0] rst_sys_src_n; + + // Declared as size 1 packed array to avoid FPV warning. + prim_mubi_pkg::mubi4_t [0:0] rst_ctrl_scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_ctrl_scanmode_sync ( + .clk_i (clk_por), + .rst_ni (rst_por_n), + .mubi_i(scanmode_i), + .mubi_o(rst_ctrl_scanmode) + ); + + // lc reset sources + rstmgr_ctrl u_lc_src ( + .clk_i (clk_por), + .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(rst_ctrl_scanmode[0])), + .scan_rst_ni, + .rst_req_i(pwr_i.rst_lc_req), + .rst_parent_ni(rst_por_aon_n), + .rst_no(rst_lc_src_n) + ); + + // sys reset sources + rstmgr_ctrl u_sys_src ( + .clk_i (clk_por), + .scanmode_i(prim_mubi_pkg::mubi4_test_true_strict(rst_ctrl_scanmode[0])), + .scan_rst_ni, + .rst_req_i(pwr_i.rst_sys_req), + .rst_parent_ni(rst_por_aon_n), + .rst_no(rst_sys_src_n) + ); + + assign pwr_o.rst_lc_src_n = rst_lc_src_n; + assign pwr_o.rst_sys_src_n = rst_sys_src_n; + + + //////////////////////////////////////////////////// + // leaf reset in the system // + // These should all be generated // + //////////////////////////////////////////////////// + // To simplify generation, each reset generates all associated power domain outputs. + // If a reset does not support a particular power domain, that reset is always hard-wired to 0. + + // Generating resets for por + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_por ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_por_aon_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por[DomainAonSel]), + .leaf_rst_o(resets_o.rst_por_n[DomainAonSel]), + .err_o(cnsty_chk_errs[0][DomainAonSel]), + .fsm_err_o(fsm_errs[0][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_por_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonPorFsmCheck_A, + u_daon_por.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_por_n[Domain0Sel] = '0; + assign cnsty_chk_errs[0][Domain0Sel] = '0; + assign fsm_errs[0][Domain0Sel] = '0; + assign rst_en_o.por[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[0] = '0; + assign shadow_fsm_errs[0] = '0; + + // Generating resets for por_io + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_por_io ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_i), + .parent_rst_ni(rst_por_aon_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_io[DomainAonSel]), + .leaf_rst_o(resets_o.rst_por_io_n[DomainAonSel]), + .err_o(cnsty_chk_errs[1][DomainAonSel]), + .fsm_err_o(fsm_errs[1][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_por_io_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonPorIoFsmCheck_A, + u_daon_por_io.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_por_io_n[Domain0Sel] = '0; + assign cnsty_chk_errs[1][Domain0Sel] = '0; + assign fsm_errs[1][Domain0Sel] = '0; + assign rst_en_o.por_io[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[1] = '0; + assign shadow_fsm_errs[1] = '0; + + // Generating resets for por_io_div2 + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_por_io_div2 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div2_i), + .parent_rst_ni(rst_por_aon_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_io_div2[DomainAonSel]), + .leaf_rst_o(resets_o.rst_por_io_div2_n[DomainAonSel]), + .err_o(cnsty_chk_errs[2][DomainAonSel]), + .fsm_err_o(fsm_errs[2][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_por_io_div2_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonPorIoDiv2FsmCheck_A, + u_daon_por_io_div2.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_por_io_div2_n[Domain0Sel] = '0; + assign cnsty_chk_errs[2][Domain0Sel] = '0; + assign fsm_errs[2][Domain0Sel] = '0; + assign rst_en_o.por_io_div2[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[2] = '0; + assign shadow_fsm_errs[2] = '0; + + // Generating resets for por_io_div4 + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_por_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_por_aon_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.por_io_div4[DomainAonSel]), + .leaf_rst_o(resets_o.rst_por_io_div4_n[DomainAonSel]), + .err_o(cnsty_chk_errs[3][DomainAonSel]), + .fsm_err_o(fsm_errs[3][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_por_io_div4_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonPorIoDiv4FsmCheck_A, + u_daon_por_io_div4.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_por_io_div4_n[Domain0Sel] = '0; + assign cnsty_chk_errs[3][Domain0Sel] = '0; + assign fsm_errs[3][Domain0Sel] = '0; + assign rst_en_o.por_io_div4[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[3] = '0; + assign shadow_fsm_errs[3] = '0; + + // Generating resets for lc + // Power Domains: ['0', 'Aon'] + // Shadowed: True + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_n[DomainAonSel]), + .err_o(cnsty_chk_errs[4][DomainAonSel]), + .fsm_err_o(fsm_errs[4][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcFsmCheck_A, + u_daon_lc.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_lc ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc[Domain0Sel]), + .leaf_rst_o(resets_o.rst_lc_n[Domain0Sel]), + .err_o(cnsty_chk_errs[4][Domain0Sel]), + .fsm_err_o(fsm_errs[4][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_lc_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0LcFsmCheck_A, + u_d0_lc.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_shadowed ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_shadowed[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_shadowed_n[DomainAonSel]), + .err_o(shadow_cnsty_chk_errs[4][DomainAonSel]), + .fsm_err_o(shadow_fsm_errs[4][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_shadowed_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcShadowedFsmCheck_A, + u_daon_lc_shadowed.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_lc_shadowed ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_main_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_shadowed[Domain0Sel]), + .leaf_rst_o(resets_o.rst_lc_shadowed_n[Domain0Sel]), + .err_o(shadow_cnsty_chk_errs[4][Domain0Sel]), + .fsm_err_o(shadow_fsm_errs[4][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_lc_shadowed_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0LcShadowedFsmCheck_A, + u_d0_lc_shadowed.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + + // Generating resets for lc_aon + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_aon ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_aon_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_aon[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_aon_n[DomainAonSel]), + .err_o(cnsty_chk_errs[5][DomainAonSel]), + .fsm_err_o(fsm_errs[5][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_aon_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcAonFsmCheck_A, + u_daon_lc_aon.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_lc_aon_n[Domain0Sel] = '0; + assign cnsty_chk_errs[5][Domain0Sel] = '0; + assign fsm_errs[5][Domain0Sel] = '0; + assign rst_en_o.lc_aon[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[5] = '0; + assign shadow_fsm_errs[5] = '0; + + // Generating resets for lc_io + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_io ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_io_n[DomainAonSel]), + .err_o(cnsty_chk_errs[6][DomainAonSel]), + .fsm_err_o(fsm_errs[6][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_io_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcIoFsmCheck_A, + u_daon_lc_io.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_lc_io_n[Domain0Sel] = '0; + assign cnsty_chk_errs[6][Domain0Sel] = '0; + assign fsm_errs[6][Domain0Sel] = '0; + assign rst_en_o.lc_io[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[6] = '0; + assign shadow_fsm_errs[6] = '0; + + // Generating resets for lc_io_div2 + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_io_div2 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div2_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div2[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_io_div2_n[DomainAonSel]), + .err_o(cnsty_chk_errs[7][DomainAonSel]), + .fsm_err_o(fsm_errs[7][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_lc_io_div2_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonLcIoDiv2FsmCheck_A, + u_daon_lc_io_div2.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_lc_io_div2_n[Domain0Sel] = '0; + assign cnsty_chk_errs[7][Domain0Sel] = '0; + assign fsm_errs[7][Domain0Sel] = '0; + assign rst_en_o.lc_io_div2[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[7] = '0; + assign shadow_fsm_errs[7] = '0; + + // Generating resets for lc_io_div4 + // Power Domains: ['0', 'Aon'] + // Shadowed: True + rstmgr_leaf_rst #( + .SecCheck(0), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div4[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_io_div4_n[DomainAonSel]), + .err_o(cnsty_chk_errs[8][DomainAonSel]), + .fsm_err_o(fsm_errs[8][DomainAonSel]) + ); + + rstmgr_leaf_rst #( + .SecCheck(0), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_lc_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div4[Domain0Sel]), + .leaf_rst_o(resets_o.rst_lc_io_div4_n[Domain0Sel]), + .err_o(cnsty_chk_errs[8][Domain0Sel]), + .fsm_err_o(fsm_errs[8][Domain0Sel]) + ); + + rstmgr_leaf_rst #( + .SecCheck(0), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_lc_io_div4_shadowed ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div4_shadowed[DomainAonSel]), + .leaf_rst_o(resets_o.rst_lc_io_div4_shadowed_n[DomainAonSel]), + .err_o(shadow_cnsty_chk_errs[8][DomainAonSel]), + .fsm_err_o(shadow_fsm_errs[8][DomainAonSel]) + ); + + rstmgr_leaf_rst #( + .SecCheck(0), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_d0_lc_io_div4_shadowed ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.lc_io_div4_shadowed[Domain0Sel]), + .leaf_rst_o(resets_o.rst_lc_io_div4_shadowed_n[Domain0Sel]), + .err_o(shadow_cnsty_chk_errs[8][Domain0Sel]), + .fsm_err_o(shadow_fsm_errs[8][Domain0Sel]) + ); + + + // Generating resets for sys + // Power Domains: [] + // Shadowed: False + assign resets_o.rst_sys_n[DomainAonSel] = '0; + assign cnsty_chk_errs[9][DomainAonSel] = '0; + assign fsm_errs[9][DomainAonSel] = '0; + assign rst_en_o.sys[DomainAonSel] = MuBi4True; + assign resets_o.rst_sys_n[Domain0Sel] = '0; + assign cnsty_chk_errs[9][Domain0Sel] = '0; + assign fsm_errs[9][Domain0Sel] = '0; + assign rst_en_o.sys[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[9] = '0; + assign shadow_fsm_errs[9] = '0; + + // Generating resets for sys_io_div4 + // Power Domains: ['Aon'] + // Shadowed: False + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b0) + ) u_daon_sys_io_div4 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_sys_src_n[DomainAonSel]), + .sw_rst_req_ni(1'b1), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.sys_io_div4[DomainAonSel]), + .leaf_rst_o(resets_o.rst_sys_io_div4_n[DomainAonSel]), + .err_o(cnsty_chk_errs[10][DomainAonSel]), + .fsm_err_o(fsm_errs[10][DomainAonSel]) + ); + + if (SecCheck) begin : gen_daon_sys_io_div4_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + DAonSysIoDiv4FsmCheck_A, + u_daon_sys_io_div4.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign resets_o.rst_sys_io_div4_n[Domain0Sel] = '0; + assign cnsty_chk_errs[10][Domain0Sel] = '0; + assign fsm_errs[10][Domain0Sel] = '0; + assign rst_en_o.sys_io_div4[Domain0Sel] = MuBi4True; + assign shadow_cnsty_chk_errs[10] = '0; + assign shadow_fsm_errs[10] = '0; + + // Generating resets for spi_device + // Power Domains: ['0'] + // Shadowed: False + assign resets_o.rst_spi_device_n[DomainAonSel] = '0; + assign cnsty_chk_errs[11][DomainAonSel] = '0; + assign fsm_errs[11][DomainAonSel] = '0; + assign rst_en_o.spi_device[DomainAonSel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b1) + ) u_d0_spi_device ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_DEVICE].q), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.spi_device[Domain0Sel]), + .leaf_rst_o(resets_o.rst_spi_device_n[Domain0Sel]), + .err_o(cnsty_chk_errs[11][Domain0Sel]), + .fsm_err_o(fsm_errs[11][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_spi_device_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0SpiDeviceFsmCheck_A, + u_d0_spi_device.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[11] = '0; + assign shadow_fsm_errs[11] = '0; + + // Generating resets for spi_host0 + // Power Domains: ['0'] + // Shadowed: False + assign resets_o.rst_spi_host0_n[DomainAonSel] = '0; + assign cnsty_chk_errs[12][DomainAonSel] = '0; + assign fsm_errs[12][DomainAonSel] = '0; + assign rst_en_o.spi_host0[DomainAonSel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b1) + ) u_d0_spi_host0 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[SPI_HOST0].q), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.spi_host0[Domain0Sel]), + .leaf_rst_o(resets_o.rst_spi_host0_n[Domain0Sel]), + .err_o(cnsty_chk_errs[12][Domain0Sel]), + .fsm_err_o(fsm_errs[12][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_spi_host0_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0SpiHost0FsmCheck_A, + u_d0_spi_host0.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[12] = '0; + assign shadow_fsm_errs[12] = '0; + + // Generating resets for i2c0 + // Power Domains: ['0'] + // Shadowed: False + assign resets_o.rst_i2c0_n[DomainAonSel] = '0; + assign cnsty_chk_errs[13][DomainAonSel] = '0; + assign fsm_errs[13][DomainAonSel] = '0; + assign rst_en_o.i2c0[DomainAonSel] = MuBi4True; + rstmgr_leaf_rst #( + .SecCheck(SecCheck), + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(1'b1) + ) u_d0_i2c0 ( + .clk_i, + .rst_ni, + .leaf_clk_i(clk_io_div4_i), + .parent_rst_ni(rst_lc_src_n[Domain0Sel]), + .sw_rst_req_ni(reg2hw.sw_rst_ctrl_n[I2C0].q), + .scan_rst_ni, + .scanmode_i, + .rst_en_o(rst_en_o.i2c0[Domain0Sel]), + .leaf_rst_o(resets_o.rst_i2c0_n[Domain0Sel]), + .err_o(cnsty_chk_errs[13][Domain0Sel]), + .fsm_err_o(fsm_errs[13][Domain0Sel]) + ); + + if (SecCheck) begin : gen_d0_i2c0_assert + `ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT( + D0I2c0FsmCheck_A, + u_d0_i2c0.gen_rst_chk.u_rst_chk.u_state_regs, + alert_tx_o[0]) + end + assign shadow_cnsty_chk_errs[13] = '0; + assign shadow_fsm_errs[13] = '0; + + + //////////////////////////////////////////////////// + // Reset info construction // + //////////////////////////////////////////////////// + + logic rst_hw_req; + logic rst_low_power; + logic pwrmgr_rst_req; + + // there is a valid reset request from pwrmgr + assign pwrmgr_rst_req = |pwr_i.rst_lc_req || |pwr_i.rst_sys_req; + + // a reset reason is only valid if the related processing element is also reset. + // In the future, if ever there are multiple processing elements, this code here + // must be updated to account for each individual core. + assign rst_hw_req = pwrmgr_rst_req & + (pwr_i.reset_cause == pwrmgr_pkg::HwReq); + assign rst_low_power = pwrmgr_rst_req & + (pwr_i.reset_cause == pwrmgr_pkg::LowPwrEntry); + + // software initiated reset request + assign sw_rst_req_o = prim_mubi_pkg::mubi4_t'(reg2hw.reset_req.q); + + // when pwrmgr reset request is received (reset is imminent), clear software + // request so we are not in an infinite reset loop. + assign hw2reg.reset_req.de = pwrmgr_rst_req; + assign hw2reg.reset_req.d = prim_mubi_pkg::MuBi4False; + + // Only sw is allowed to clear a reset reason, hw is only allowed to set it. + assign hw2reg.reset_info.low_power_exit.d = 1'b1; + assign hw2reg.reset_info.low_power_exit.de = rst_low_power; + + // software issued request triggers the same response as hardware, although it is + // accounted for differently. + assign hw2reg.reset_info.sw_reset.d = prim_mubi_pkg::mubi4_test_true_strict(sw_rst_req_o) | + reg2hw.reset_info.sw_reset.q; + assign hw2reg.reset_info.sw_reset.de = rst_hw_req; + + // HW reset requests most likely will be multi-bit, so OR in whatever reasons + // that are already set. + assign hw2reg.reset_info.hw_req.d = pwr_i.rstreqs | + reg2hw.reset_info.hw_req.q; + assign hw2reg.reset_info.hw_req.de = rst_hw_req; + + //////////////////////////////////////////////////// + // Crash info capture // + //////////////////////////////////////////////////// + + logic dump_capture; + assign dump_capture = rst_hw_req | rst_low_power; + + // halt dump capture once we hit particular conditions + logic dump_capture_halt; + assign dump_capture_halt = rst_hw_req; + + rstmgr_crash_info #( + .CrashDumpWidth($bits(alert_handler_pkg::alert_crashdump_t)) + ) u_alert_info ( + .clk_i(clk_por_i), + .rst_ni(rst_por_ni), + .dump_i(alert_dump_i), + .dump_capture_i(dump_capture & reg2hw.alert_info_ctrl.en.q), + .slot_sel_i(reg2hw.alert_info_ctrl.index.q), + .slots_cnt_o(hw2reg.alert_info_attr.d), + .slot_o(hw2reg.alert_info.d) + ); + + rstmgr_crash_info #( + .CrashDumpWidth($bits(rv_core_ibex_pkg::cpu_crash_dump_t)) + ) u_cpu_info ( + .clk_i(clk_por_i), + .rst_ni(rst_por_ni), + .dump_i(cpu_dump_i), + .dump_capture_i(dump_capture & reg2hw.cpu_info_ctrl.en.q), + .slot_sel_i(reg2hw.cpu_info_ctrl.index.q), + .slots_cnt_o(hw2reg.cpu_info_attr.d), + .slot_o(hw2reg.cpu_info.d) + ); + + // once dump is captured, no more information is captured until + // re-enabled by software. + assign hw2reg.alert_info_ctrl.en.d = 1'b0; + assign hw2reg.alert_info_ctrl.en.de = dump_capture_halt; + assign hw2reg.cpu_info_ctrl.en.d = 1'b0; + assign hw2reg.cpu_info_ctrl.en.de = dump_capture_halt; + + //////////////////////////////////////////////////// + // Exported resets // + //////////////////////////////////////////////////// + + + + + //////////////////////////////////////////////////// + // Assertions // + //////////////////////////////////////////////////// + + `ASSERT_INIT(ParameterMatch_A, NumHwResets == pwrmgr_pkg::HwResetWidth) + + // when upstream resets, downstream must also reset + + // output known asserts + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid ) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready ) + `ASSERT_KNOWN(AlertsKnownO_A, alert_tx_o ) + `ASSERT_KNOWN(PwrKnownO_A, pwr_o ) + `ASSERT_KNOWN(ResetsKnownO_A, resets_o ) + `ASSERT_KNOWN(RstEnKnownO_A, rst_en_o ) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0]) +endmodule // rstmgr diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_cnsty_chk.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_cnsty_chk.sv new file mode 100644 index 00000000000..d70ab3be41c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_cnsty_chk.sv @@ -0,0 +1,273 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements reset consistency checks +// The main goal is to check whether conditions allow for a reset to be asserted +// For example, if a child reset asserts, it must be the case that its parent +// reset or software controls (if available) have asserted. +// If a child reset asserts and neither of the above case is true, it is considered +// a fatal error. + +`include "prim_assert.sv" + +module rstmgr_cnsty_chk + import rstmgr_pkg::*; + import rstmgr_reg_pkg::*; +#( + parameter int SecMaxSyncDelay = 2, + parameter bit SwRstReq = 1 +) ( + input clk_i, + input rst_ni, + input child_clk_i, + input child_rst_ni, + input child_chk_rst_ni, // rst_ni synchronized to child_clk_i domain. + input parent_rst_ni, + input sw_rst_req_i, + output logic sw_rst_req_clr_o, + output logic err_o, + output logic fsm_err_o +); + + // The "+ 2" here is because the cnt counter that uses this width needs to be able to count up to + // SecMaxSyncDelay + 1. + localparam int CntWidth = $clog2(SecMaxSyncDelay + 2); + + // These two flops below are completely async. + // The value from these flops are always fed through synchronizers before use. + logic parent_rst_asserted; + always_ff @(posedge clk_i or negedge parent_rst_ni) begin + if (!parent_rst_ni) begin + parent_rst_asserted <= 1'b1; + end else begin + parent_rst_asserted <= '0; + end + end + + logic child_rst_asserted; + always_ff @(posedge clk_i or negedge child_rst_ni) begin + if (!child_rst_ni) begin + child_rst_asserted <= 1'b1; + end else begin + child_rst_asserted <= '0; + end + end + + logic sync_parent_rst; + prim_flop_2sync #( + .Width(1), + .ResetValue(1) + ) u_parent_sync ( + .clk_i, + .rst_ni, + .d_i(parent_rst_asserted), + .q_o(sync_parent_rst) + ); + + logic sync_child_rst; + prim_flop_2sync #( + .Width(1), + .ResetValue(1) + ) u_child_sync ( + .clk_i, + .rst_ni, + .d_i(child_rst_asserted), + .q_o(sync_child_rst) + ); + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 7 -n 6 \ + // -s 90402488 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (57.14%) + // 4: ||||||||||||||| (42.86%) + // 5: -- + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 4 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 5 + // + localparam int StateWidth = 6; + typedef enum logic [StateWidth-1:0] { + Reset = 6'b010001, + Idle = 6'b100011, + WaitForParent = 6'b111101, + WaitForChild = 6'b001111, + WaitForSrcRelease = 6'b100100, + WaitForChildRelease = 6'b111010, + Error = 6'b010110, + FsmError = 6'b001000 + } state_e; + + state_e state_q, state_d; + + // SEC_CM: LEAF.FSM.SPARSE + `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Reset, clk_i, rst_ni) + + logic timeout; + logic cnt_inc; + logic cnt_clr; + logic [CntWidth-1:0] cnt; + + // the timeout count is on clk_i because the synchronizers are + // also operating on clk_i. We are mainly trying to wait out the reset assertion delays. + // parent resets are asynchronous assertion so there is at most a one cycle separation. + // if needed we can make this timeout bigger. + assign timeout = int'(cnt) > SecMaxSyncDelay; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cnt <= '0; + end else if (cnt_clr) begin + cnt <= '0; + end else if (cnt_inc && !timeout) begin + cnt <= cnt + 1'b1; + end + end + + logic src_valid; + // The following code makes it easier for tools such as UNR, + // it is not functionally required. + if (SwRstReq) begin : gen_sw_rst_req + assign src_valid = sync_parent_rst || sw_rst_req_i; + end else begin : gen_no_sw_rst_req + assign src_valid = sync_parent_rst; + + logic unused_sw_rst_req; + assign unused_sw_rst_req = sw_rst_req_i; + end + + logic sync_child_ack; + + always_comb begin + state_d = state_q; + err_o = '0; + fsm_err_o = '0; + cnt_inc = '0; + cnt_clr = '0; + sw_rst_req_clr_o = '0; + + unique case (state_q) + Reset: begin + // when the checker itself comes out of reset, conditions + // may be ambiguous, wait for things to stabilize + if (!sync_child_rst && !sync_parent_rst) begin + state_d = Idle; + end + end + + Idle: begin + // If a child reset asserts, one of the conditions must be true. + // It is possible for the child to assert but parent to remain de-asserted + // due to CDC latency (or vice versa), wait for the other corresponding reset + // when this occurs. + if (sync_child_rst && src_valid) begin + state_d = WaitForSrcRelease; + end else if (sync_child_rst && !sync_parent_rst) begin + state_d = WaitForParent; + end else if (sync_parent_rst && !sync_child_rst) begin + state_d = WaitForChild; + end + end + + // parent reset must show up within timeout region + WaitForParent: begin + cnt_inc = 1'b1; + + if (timeout && !sync_parent_rst) begin + state_d = Error; + end else if (sync_parent_rst) begin + state_d = WaitForSrcRelease; + cnt_clr = 1'b1; + end + end + + // child reset must show up within timeout region + WaitForChild: begin + cnt_inc = 1'b1; + + if (timeout && !sync_child_rst) begin + state_d = Error; + end else if (sync_child_rst) begin + state_d = WaitForSrcRelease; + cnt_clr = 1'b1; + end + end + + // waiting for parent reset to release + WaitForSrcRelease: begin + // if arrived here due to software requested reset, it is now + // okay to clear the original request. + sw_rst_req_clr_o = 1'b1; + + // it is not possible for the child reset to release + // ahead of the parent reset + if (!sync_child_rst && src_valid) begin + state_d = Error; + end else if (!src_valid) begin + cnt_clr = 1'b1; + state_d = WaitForChildRelease; + end + end + + // waiting for child reset to release + WaitForChildRelease: begin + // operate only on child ack to keep things in sync + // This is needed because the reset releases are synchronous to the child clock. + // So if we have a situation where the child clock is way slower than the local + // clock used to increment the count, we may timeout incorrectly. + // By using sync_child_ack, we ensure that the count is advanced only when a + // child clock edge is seen. This usage is conservative, because by the time + // sync_child_ack is seen, there may have been more than one child clock, yet the + // count is only incremented by 1. + cnt_inc = sync_child_ack; + if (sync_child_rst && src_valid) begin + // This condition covers the case if for whatever reason the parent reset re-asserts + // in a valid way. + state_d = WaitForSrcRelease; + cnt_clr = 1'b1; + end else if (sync_child_rst && timeout) begin + state_d = Error; + end else if (!sync_child_rst) begin + state_d = Idle; + cnt_clr = 1'b1; + end + end + + Error: begin + err_o = 1'b1; + end + + FsmError: begin + fsm_err_o = 1'b1; + end + + default: begin + state_d = FsmError; + fsm_err_o = 1'b1; + end + endcase // unique case (state_q) + end // always_comb + + logic child_ack; + prim_sync_reqack u_child_handshake ( + .clk_src_i(clk_i), + .rst_src_ni(rst_ni), + .clk_dst_i(child_clk_i), + .rst_dst_ni(child_chk_rst_ni), + .req_chk_i('0), + .src_req_i(1'b1), + .src_ack_o(sync_child_ack), + .dst_req_o(child_ack), + .dst_ack_i(child_ack) + ); + +endmodule // rstmgr_cnsty_chk diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_crash_info.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_crash_info.sv new file mode 100644 index 00000000000..e252c43fd6d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_crash_info.sv @@ -0,0 +1,60 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// This module implements the crash dump functionality + +`include "prim_assert.sv" + +module rstmgr_crash_info + import rstmgr_pkg::*; + import rstmgr_reg_pkg::IdxWidth; + import rstmgr_reg_pkg::RdWidth; +#( + parameter int CrashDumpWidth = 32, + localparam int CrashRemainder = CrashDumpWidth % RdWidth > 0 ? 1 : 0, + localparam int unsigned CrashStoreSlot = CrashDumpWidth / RdWidth + CrashRemainder, + localparam int SlotCntWidth = $clog2(CrashStoreSlot) +) ( + input clk_i, + input rst_ni, + input [CrashDumpWidth-1:0] dump_i, + input dump_capture_i, + input [IdxWidth-1:0] slot_sel_i, + output logic [IdxWidth-1:0] slots_cnt_o, + output logic [RdWidth-1:0] slot_o +); + + localparam int TotalWidth = CrashStoreSlot * RdWidth; + logic [2**SlotCntWidth-1:0][RdWidth-1:0] slots; + logic [ CrashStoreSlot-1:0][RdWidth-1:0] slots_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + slots_q <= '0; + end else if (dump_capture_i) begin + slots_q <= TotalWidth'(dump_i); + end + end + + always_comb begin + slots = '0; + slots[CrashStoreSlot-1:0] = slots_q; + end + + assign slots_cnt_o = CrashStoreSlot[IdxWidth-1:0]; + assign slot_o = slots[slot_sel_i[SlotCntWidth-1:0]]; + + if (SlotCntWidth < IdxWidth) begin : gen_tieoffs + //VCS coverage off + // pragma coverage off + logic [IdxWidth-SlotCntWidth-1:0] unused_idx; + assign unused_idx = slot_sel_i[IdxWidth-1:SlotCntWidth]; + //VCS coverage on + // pragma coverage on + end + + // Make sure the crash dump isn't excessively large + `ASSERT_INIT(CntStoreSlot_A, CrashStoreSlot < (1 << IdxWidth)) + `ASSERT_INIT(CntWidth_A, SlotCntWidth <= IdxWidth) + +endmodule // rstmgr_crash_info diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_ctrl.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_ctrl.sv new file mode 100644 index 00000000000..a762ec8281b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_ctrl.sv @@ -0,0 +1,77 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements generic reset controls +// + +`include "prim_assert.sv" + +module rstmgr_ctrl + import rstmgr_pkg::*; + import rstmgr_reg_pkg::*; +( + input clk_i, + input [PowerDomains-1:0] rst_req_i, + input [PowerDomains-1:0] rst_parent_ni, // parent reset + output logic [PowerDomains-1:0] rst_no, + input scanmode_i, + input scan_rst_ni +); + + // the always on root reset + logic rst_aon_n_premux, rst_aon_n; + + // the remaining resets + logic [OffDomains-1:0] rst_pd_nd, rst_pd_nq; + + // always on handling + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_aon_rst ( + .clk_i, + .rst_ni(rst_parent_ni[DomainAonSel]), + .d_i(~rst_req_i[DomainAonSel]), + .q_o(rst_aon_n_premux) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_aon_mux ( + .clk0_i(rst_aon_n_premux), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_aon_n) + ); + assign rst_no[DomainAonSel] = rst_aon_n; + + // the non-always-on domains + // These reset whenever the always on domain reset, to ensure power definition consistency. + // By extension, they also reset whenever the root (rst_ni) resets + assign rst_pd_nd = ~rst_req_i[Domain0Sel +: OffDomains]; + + localparam int DomainPdStartIdx = DomainAonSel + 1; + for(genvar i = 0; i < OffDomains; i++) begin : gen_rst_pd_n + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_pd_rst ( + .clk_i, + // when the always on portion resets, always reset the non-always-on portion as well. + .rst_ni(rst_aon_n & rst_parent_ni[DomainPdStartIdx + i]), + .d_i(rst_pd_nd[i]), + .q_o(rst_pd_nq[i]) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_pd_mux ( + .clk0_i(rst_pd_nq[i]), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_no[DomainPdStartIdx + i]) + ); + end + +endmodule // rstmgr_ctrl diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_leaf_rst.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_leaf_rst.sv new file mode 100644 index 00000000000..ca1ab02a1c7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_leaf_rst.sv @@ -0,0 +1,134 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module generates the leaf resets and instantiates the associated reset +// checks. + +`include "prim_assert.sv" + +module rstmgr_leaf_rst + import rstmgr_pkg::*; + import rstmgr_reg_pkg::*; + import prim_mubi_pkg::mubi4_t; #( + parameter bit SecCheck = 1, + parameter int SecMaxSyncDelay = 2, + parameter bit SwRstReq = 1 +) ( + input clk_i, + input rst_ni, + input leaf_clk_i, + input parent_rst_ni, + input sw_rst_req_ni, + input prim_mubi_pkg::mubi4_t scanmode_i, + input scan_rst_ni, + output mubi4_t rst_en_o, + output logic leaf_rst_o, + output logic err_o, + output logic fsm_err_o +); + + prim_mubi_pkg::mubi4_t scanmode; + prim_mubi4_sync #( + .NumCopies(1), + .AsyncOn(0) + ) u_scanmode_sync ( + .clk_i, + .rst_ni, + .mubi_i(scanmode_i), + .mubi_o({scanmode}) + ); + + logic leaf_rst_sync; + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_rst_sync ( + .clk_i(leaf_clk_i), + .rst_ni(parent_rst_ni), + .d_i(sw_rst_req_ni), + .q_o(leaf_rst_sync) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_mux ( + .clk0_i(leaf_rst_sync), + .clk1_i(scan_rst_ni), + .sel_i(prim_mubi_pkg::mubi4_test_true_strict(scanmode)), + .clk_o(leaf_rst_o) + ); + + logic sw_rst_req_q; + logic clr_sw_rst_req; + if (SwRstReq && SecCheck) begin : gen_sw_rst_req + // once software requests a reset, hold on to the request until the consistency + // checker passes the assertion check point + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + sw_rst_req_q <= '0; + end else if (sw_rst_req_q && clr_sw_rst_req) begin + sw_rst_req_q <= '0; + end else if (!sw_rst_req_q && !sw_rst_req_ni && !clr_sw_rst_req) begin + sw_rst_req_q <= 1'b1; + end + end + end else begin : gen_no_sw_rst_req + //VCS coverage off + // pragma coverage off + logic unused_sig; + assign unused_sig = clr_sw_rst_req; + //VCS coverage on + // pragma coverage on + assign sw_rst_req_q = '0; + end + + if (SecCheck) begin : gen_rst_chk + + // We have to create a separately synced reset for the child handshakes below, since keeping the + // child side of the prim_sync_reqack synchronizer under reset would defeat the reset checker's + // purpose, as it would never count any clock ticks in the WaitForChildRelease state above. + logic leaf_chk_rst_n; + prim_rst_sync u_prim_rst_sync ( + .clk_i (leaf_clk_i), + .d_i (rst_ni), + .q_o (leaf_chk_rst_n), + .scan_rst_ni, + .scanmode_i + ); + + // SEC_CM: LEAF.RST.BKGN_CHK + rstmgr_cnsty_chk #( + .SecMaxSyncDelay(SecMaxSyncDelay), + .SwRstReq(SwRstReq) + ) u_rst_chk ( + .clk_i, + .rst_ni, + .child_clk_i(leaf_clk_i), + .child_rst_ni(leaf_rst_o), + .child_chk_rst_ni(leaf_chk_rst_n), + .parent_rst_ni, + .sw_rst_req_i(sw_rst_req_q | ~sw_rst_req_ni), + .sw_rst_req_clr_o(clr_sw_rst_req), + .err_o, + .fsm_err_o + ); + end else begin : gen_no_rst_chk + logic unused_sig; + assign unused_sig = sw_rst_req_q; + assign clr_sw_rst_req = '0; + assign err_o = '0; + assign fsm_err_o = '0; + end + + // reset asserted indication for alert handler + prim_mubi4_sender #( + .ResetValue(prim_mubi_pkg::MuBi4True) + ) u_prim_mubi4_sender ( + .clk_i(leaf_clk_i), + .rst_ni(leaf_rst_o), + .mubi_i(prim_mubi_pkg::MuBi4False), + .mubi_o(rst_en_o) + ); + +endmodule // rstmgr_leaf_rst diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv new file mode 100644 index 00000000000..fd05f66371d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_pkg.sv @@ -0,0 +1,97 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// + +package rstmgr_pkg; + + // Power domain parameters + parameter int PowerDomains = 2; + parameter int DomainAonSel = 0; + parameter int Domain0Sel = 1; + + // Number of non-always-on domains + parameter int OffDomains = PowerDomains-1; + + // positions of software controllable reset bits + parameter int SPI_DEVICE = 0; + parameter int SPI_HOST0 = 1; + parameter int I2C0 = 2; + + // resets generated and broadcast + // SEC_CM: LEAF.RST.SHADOW + typedef struct packed { + logic [PowerDomains-1:0] rst_por_aon_n; + logic [PowerDomains-1:0] rst_por_n; + logic [PowerDomains-1:0] rst_por_io_n; + logic [PowerDomains-1:0] rst_por_io_div2_n; + logic [PowerDomains-1:0] rst_por_io_div4_n; + logic [PowerDomains-1:0] rst_lc_shadowed_n; + logic [PowerDomains-1:0] rst_lc_n; + logic [PowerDomains-1:0] rst_lc_aon_n; + logic [PowerDomains-1:0] rst_lc_io_n; + logic [PowerDomains-1:0] rst_lc_io_div2_n; + logic [PowerDomains-1:0] rst_lc_io_div4_shadowed_n; + logic [PowerDomains-1:0] rst_lc_io_div4_n; + logic [PowerDomains-1:0] rst_sys_n; + logic [PowerDomains-1:0] rst_sys_io_div4_n; + logic [PowerDomains-1:0] rst_spi_device_n; + logic [PowerDomains-1:0] rst_spi_host0_n; + logic [PowerDomains-1:0] rst_i2c0_n; + } rstmgr_out_t; + + // reset indication for alert handler + typedef struct packed { + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_aon; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_io; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_io_div2; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] por_io_div4; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_shadowed; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_aon; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io_div2; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io_div4_shadowed; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] lc_io_div4; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] sys; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] sys_io_div4; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] spi_device; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] spi_host0; + prim_mubi_pkg::mubi4_t [PowerDomains-1:0] i2c0; + } rstmgr_rst_en_t; + + parameter int NumOutputRst = 17 * PowerDomains; + + // cpu reset requests and status + typedef struct packed { + logic ndmreset_req; + } rstmgr_cpu_t; + + // exported resets + + // default value for rstmgr_ast_rsp_t (for dangling ports) + parameter rstmgr_cpu_t RSTMGR_CPU_DEFAULT = '{ + ndmreset_req: '0 + }; + + // Enumeration for pwrmgr hw reset inputs + localparam int ResetWidths = $clog2(rstmgr_reg_pkg::NumTotalResets); + typedef enum logic [ResetWidths-1:0] { + ReqPeriResetIdx[0:1], + ReqMainPwrResetIdx, + ReqEscResetIdx + } reset_req_idx_e; + + // Enumeration for reset info bit idx + typedef enum logic [ResetWidths-1:0] { + InfoPorIdx, + InfoLowPowerExitIdx, + InfoSwResetIdx, + InfoPeriResetIdx[0:1], + InfoMainPwrResetIdx, + InfoEscResetIdx + } reset_info_idx_e; + + +endpackage // rstmgr_pkg diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_por.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_por.sv new file mode 100644 index 00000000000..0ac7e14becb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_por.sv @@ -0,0 +1,106 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module stretches the POR +// + +module rstmgr_por #( + parameter int FilterStages = 3, + parameter int unsigned StretchCount = 32 +) ( + input clk_i, + input rst_ni, + input scan_rst_ni, + input scanmode_i, + output logic rst_no +); + localparam int CtrWidth = $clog2(StretchCount+1); + + logic rst_root_n_pre_mux, rst_root_n; + logic [FilterStages-1:0] rst_filter_n; + logic rst_stable; + logic rst_clean_n; + logic [CtrWidth-1:0] cnt; + logic cnt_en; + + // sync the POR + prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) u_rst_sync ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(1'b1), + .q_o(rst_root_n_pre_mux) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_root_mux ( + .clk0_i(rst_root_n_pre_mux), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_root_n) + ); + + // filter the POR + always_ff @(posedge clk_i or negedge rst_root_n) begin + if (!rst_root_n) begin + rst_filter_n <= '0; + end else begin + rst_filter_n <= {rst_filter_n[0 +: FilterStages-1], 1'b1}; + end + end + + // The stable is a vote of all filter stages. + // Only when all the stages agree is the reset considered stable and count allowed. + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_clean_mux ( + .clk0_i(rst_filter_n[FilterStages-1]), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_clean_n) + ); + + assign rst_stable = &rst_filter_n; + assign cnt_en = rst_stable & !rst_no; + + // stretch the POR + logic rst_nd, rst_nq; + + assign rst_nd = ~rst_stable ? 1'b0 : + cnt_en & (cnt == StretchCount[CtrWidth-1:0]) ? 1'b1 : rst_nq; + + always_ff @(posedge clk_i or negedge rst_clean_n) begin + if (!rst_clean_n) begin + cnt <= '0; + end else if (!rst_stable) begin + cnt <= '0; + end else if (cnt_en) begin + cnt <= cnt + 1'b1; + end + end + + prim_flop #( + .Width(1), + .ResetValue('0) + ) u_rst_flop ( + .clk_i, + .rst_ni(rst_clean_n), + .d_i(rst_nd), + .q_o(rst_nq) + ); + + prim_clock_mux2 #( + .NoFpgaBufG(1'b1) + ) u_rst_out_mux ( + .clk0_i(rst_nq), + .clk1_i(scan_rst_ni), + .sel_i(scanmode_i), + .clk_o(rst_no) + ); + +endmodule // rstmgr_por diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv new file mode 100644 index 00000000000..d92a33628dc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv @@ -0,0 +1,257 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package rstmgr_reg_pkg; + + // Param list + parameter int RdWidth = 32; + parameter int IdxWidth = 4; + parameter int NumHwResets = 4; + parameter int NumSwResets = 3; + parameter int NumTotalResets = 7; + parameter int NumAlerts = 2; + + // Address widths within the block + parameter int BlockAw = 7; + + // Number of registers for every interface + parameter int NumRegs = 18; + + // Alert indices + typedef enum int { + AlertFatalFaultIdx = 0, + AlertFatalCnstyFaultIdx = 1 + } rstmgr_alert_idx_t; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + logic qe; + } fatal_cnsty_fault; + struct packed { + logic q; + logic qe; + } fatal_fault; + } rstmgr_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic [3:0] q; + } rstmgr_reg2hw_reset_req_reg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + } hw_req; + struct packed { + logic q; + } sw_reset; + } rstmgr_reg2hw_reset_info_reg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + } index; + struct packed { + logic q; + } en; + } rstmgr_reg2hw_alert_info_ctrl_reg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + } index; + struct packed { + logic q; + } en; + } rstmgr_reg2hw_cpu_info_ctrl_reg_t; + + typedef struct packed { + logic q; + } rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t; + + typedef struct packed { + struct packed { + logic q; + } fsm_err; + struct packed { + logic q; + } reset_consistency_err; + struct packed { + logic q; + } reg_intg_err; + } rstmgr_reg2hw_err_code_reg_t; + + typedef struct packed { + logic [3:0] d; + logic de; + } rstmgr_hw2reg_reset_req_reg_t; + + typedef struct packed { + struct packed { + logic [3:0] d; + logic de; + } hw_req; + struct packed { + logic d; + logic de; + } sw_reset; + struct packed { + logic d; + logic de; + } low_power_exit; + } rstmgr_hw2reg_reset_info_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } en; + } rstmgr_hw2reg_alert_info_ctrl_reg_t; + + typedef struct packed { + logic [3:0] d; + } rstmgr_hw2reg_alert_info_attr_reg_t; + + typedef struct packed { + logic [31:0] d; + } rstmgr_hw2reg_alert_info_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } en; + } rstmgr_hw2reg_cpu_info_ctrl_reg_t; + + typedef struct packed { + logic [3:0] d; + } rstmgr_hw2reg_cpu_info_attr_reg_t; + + typedef struct packed { + logic [31:0] d; + } rstmgr_hw2reg_cpu_info_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } fsm_err; + struct packed { + logic d; + logic de; + } reset_consistency_err; + struct packed { + logic d; + logic de; + } reg_intg_err; + } rstmgr_hw2reg_err_code_reg_t; + + // Register -> HW type + typedef struct packed { + rstmgr_reg2hw_alert_test_reg_t alert_test; // [28:25] + rstmgr_reg2hw_reset_req_reg_t reset_req; // [24:21] + rstmgr_reg2hw_reset_info_reg_t reset_info; // [20:16] + rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [15:11] + rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [10:6] + rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [2:0] sw_rst_ctrl_n; // [5:3] + rstmgr_reg2hw_err_code_reg_t err_code; // [2:0] + } rstmgr_reg2hw_t; + + // HW -> register type + typedef struct packed { + rstmgr_hw2reg_reset_req_reg_t reset_req; // [95:91] + rstmgr_hw2reg_reset_info_reg_t reset_info; // [90:82] + rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [81:80] + rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [79:76] + rstmgr_hw2reg_alert_info_reg_t alert_info; // [75:44] + rstmgr_hw2reg_cpu_info_ctrl_reg_t cpu_info_ctrl; // [43:42] + rstmgr_hw2reg_cpu_info_attr_reg_t cpu_info_attr; // [41:38] + rstmgr_hw2reg_cpu_info_reg_t cpu_info; // [37:6] + rstmgr_hw2reg_err_code_reg_t err_code; // [5:0] + } rstmgr_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] RSTMGR_ALERT_TEST_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] RSTMGR_RESET_REQ_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] RSTMGR_RESET_INFO_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] RSTMGR_ALERT_REGWEN_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_CTRL_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_ATTR_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] RSTMGR_CPU_REGWEN_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_CTRL_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_ATTR_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_0_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_1_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_2_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_0_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_1_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_2_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] RSTMGR_ERR_CODE_OFFSET = 7'h 44; + + // Reset values for hwext registers and their fields + parameter logic [1:0] RSTMGR_ALERT_TEST_RESVAL = 2'h 0; + parameter logic [0:0] RSTMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; + parameter logic [0:0] RSTMGR_ALERT_TEST_FATAL_CNSTY_FAULT_RESVAL = 1'h 0; + parameter logic [3:0] RSTMGR_ALERT_INFO_ATTR_RESVAL = 4'h 0; + parameter logic [3:0] RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_RESVAL = 4'h 0; + parameter logic [31:0] RSTMGR_ALERT_INFO_RESVAL = 32'h 0; + parameter logic [31:0] RSTMGR_ALERT_INFO_VALUE_RESVAL = 32'h 0; + parameter logic [3:0] RSTMGR_CPU_INFO_ATTR_RESVAL = 4'h 0; + parameter logic [3:0] RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_RESVAL = 4'h 0; + parameter logic [31:0] RSTMGR_CPU_INFO_RESVAL = 32'h 0; + parameter logic [31:0] RSTMGR_CPU_INFO_VALUE_RESVAL = 32'h 0; + + // Register index + typedef enum int { + RSTMGR_ALERT_TEST, + RSTMGR_RESET_REQ, + RSTMGR_RESET_INFO, + RSTMGR_ALERT_REGWEN, + RSTMGR_ALERT_INFO_CTRL, + RSTMGR_ALERT_INFO_ATTR, + RSTMGR_ALERT_INFO, + RSTMGR_CPU_REGWEN, + RSTMGR_CPU_INFO_CTRL, + RSTMGR_CPU_INFO_ATTR, + RSTMGR_CPU_INFO, + RSTMGR_SW_RST_REGWEN_0, + RSTMGR_SW_RST_REGWEN_1, + RSTMGR_SW_RST_REGWEN_2, + RSTMGR_SW_RST_CTRL_N_0, + RSTMGR_SW_RST_CTRL_N_1, + RSTMGR_SW_RST_CTRL_N_2, + RSTMGR_ERR_CODE + } rstmgr_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] RSTMGR_PERMIT [18] = '{ + 4'b 0001, // index[ 0] RSTMGR_ALERT_TEST + 4'b 0001, // index[ 1] RSTMGR_RESET_REQ + 4'b 0001, // index[ 2] RSTMGR_RESET_INFO + 4'b 0001, // index[ 3] RSTMGR_ALERT_REGWEN + 4'b 0001, // index[ 4] RSTMGR_ALERT_INFO_CTRL + 4'b 0001, // index[ 5] RSTMGR_ALERT_INFO_ATTR + 4'b 1111, // index[ 6] RSTMGR_ALERT_INFO + 4'b 0001, // index[ 7] RSTMGR_CPU_REGWEN + 4'b 0001, // index[ 8] RSTMGR_CPU_INFO_CTRL + 4'b 0001, // index[ 9] RSTMGR_CPU_INFO_ATTR + 4'b 1111, // index[10] RSTMGR_CPU_INFO + 4'b 0001, // index[11] RSTMGR_SW_RST_REGWEN_0 + 4'b 0001, // index[12] RSTMGR_SW_RST_REGWEN_1 + 4'b 0001, // index[13] RSTMGR_SW_RST_REGWEN_2 + 4'b 0001, // index[14] RSTMGR_SW_RST_CTRL_N_0 + 4'b 0001, // index[15] RSTMGR_SW_RST_CTRL_N_1 + 4'b 0001, // index[16] RSTMGR_SW_RST_CTRL_N_2 + 4'b 0001 // index[17] RSTMGR_ERR_CODE + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv new file mode 100644 index 00000000000..e59e44575d0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv @@ -0,0 +1,1122 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module rstmgr_reg_top ( + input clk_i, + input rst_ni, + input clk_por_i, + input rst_por_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output rstmgr_reg_pkg::rstmgr_reg2hw_t reg2hw, // Write + input rstmgr_reg_pkg::rstmgr_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import rstmgr_reg_pkg::* ; + + localparam int AW = 7; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [17:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(18) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic alert_test_we; + logic alert_test_fatal_fault_wd; + logic alert_test_fatal_cnsty_fault_wd; + logic reset_req_we; + logic [3:0] reset_req_qs; + logic [3:0] reset_req_wd; + logic reset_info_we; + logic reset_info_por_qs; + logic reset_info_por_wd; + logic reset_info_low_power_exit_qs; + logic reset_info_low_power_exit_wd; + logic reset_info_sw_reset_qs; + logic reset_info_sw_reset_wd; + logic [3:0] reset_info_hw_req_qs; + logic [3:0] reset_info_hw_req_wd; + logic alert_regwen_we; + logic alert_regwen_qs; + logic alert_regwen_wd; + logic alert_info_ctrl_we; + logic alert_info_ctrl_en_qs; + logic alert_info_ctrl_en_wd; + logic [3:0] alert_info_ctrl_index_qs; + logic [3:0] alert_info_ctrl_index_wd; + logic alert_info_attr_re; + logic [3:0] alert_info_attr_qs; + logic alert_info_re; + logic [31:0] alert_info_qs; + logic cpu_regwen_we; + logic cpu_regwen_qs; + logic cpu_regwen_wd; + logic cpu_info_ctrl_we; + logic cpu_info_ctrl_en_qs; + logic cpu_info_ctrl_en_wd; + logic [3:0] cpu_info_ctrl_index_qs; + logic [3:0] cpu_info_ctrl_index_wd; + logic cpu_info_attr_re; + logic [3:0] cpu_info_attr_qs; + logic cpu_info_re; + logic [31:0] cpu_info_qs; + logic sw_rst_regwen_0_we; + logic sw_rst_regwen_0_qs; + logic sw_rst_regwen_0_wd; + logic sw_rst_regwen_1_we; + logic sw_rst_regwen_1_qs; + logic sw_rst_regwen_1_wd; + logic sw_rst_regwen_2_we; + logic sw_rst_regwen_2_qs; + logic sw_rst_regwen_2_wd; + logic sw_rst_ctrl_n_0_we; + logic sw_rst_ctrl_n_0_qs; + logic sw_rst_ctrl_n_0_wd; + logic sw_rst_ctrl_n_1_we; + logic sw_rst_ctrl_n_1_qs; + logic sw_rst_ctrl_n_1_wd; + logic sw_rst_ctrl_n_2_we; + logic sw_rst_ctrl_n_2_qs; + logic sw_rst_ctrl_n_2_wd; + logic err_code_reg_intg_err_qs; + logic err_code_reset_consistency_err_qs; + logic err_code_fsm_err_qs; + // Define register CDC handling. + // CDC handling is done on a per-reg instead of per-field boundary. + + // Register instances + // R[alert_test]: V(True) + logic alert_test_qe; + logic [1:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + // F[fatal_fault]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.fatal_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe; + + // F[fatal_cnsty_fault]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_alert_test_fatal_cnsty_fault ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_fatal_cnsty_fault_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[1]), + .q (reg2hw.alert_test.fatal_cnsty_fault.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.fatal_cnsty_fault.qe = alert_test_qe; + + + // R[reset_req]: V(False) + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h9), + .Mubi (1'b1) + ) u_reset_req ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (reset_req_we), + .wd (reset_req_wd), + + // from internal hardware + .de (hw2reg.reset_req.de), + .d (hw2reg.reset_req.d), + + // to internal hardware + .qe (), + .q (reg2hw.reset_req.q), + .ds (), + + // to register interface (read) + .qs (reset_req_qs) + ); + + + // R[reset_info]: V(False) + // F[por]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_reset_info_por ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (reset_info_we), + .wd (reset_info_por_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_info_por_qs) + ); + + // F[low_power_exit]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_info_low_power_exit ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (reset_info_we), + .wd (reset_info_low_power_exit_wd), + + // from internal hardware + .de (hw2reg.reset_info.low_power_exit.de), + .d (hw2reg.reset_info.low_power_exit.d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (reset_info_low_power_exit_qs) + ); + + // F[sw_reset]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_reset_info_sw_reset ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (reset_info_we), + .wd (reset_info_sw_reset_wd), + + // from internal hardware + .de (hw2reg.reset_info.sw_reset.de), + .d (hw2reg.reset_info.sw_reset.d), + + // to internal hardware + .qe (), + .q (reg2hw.reset_info.sw_reset.q), + .ds (), + + // to register interface (read) + .qs (reset_info_sw_reset_qs) + ); + + // F[hw_req]: 6:3 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessW1C), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_reset_info_hw_req ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (reset_info_we), + .wd (reset_info_hw_req_wd), + + // from internal hardware + .de (hw2reg.reset_info.hw_req.de), + .d (hw2reg.reset_info.hw_req.d), + + // to internal hardware + .qe (), + .q (reg2hw.reset_info.hw_req.q), + .ds (), + + // to register interface (read) + .qs (reset_info_hw_req_qs) + ); + + + // R[alert_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_alert_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (alert_regwen_we), + .wd (alert_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (alert_regwen_qs) + ); + + + // R[alert_info_ctrl]: V(False) + // Create REGWEN-gated WE signal + logic alert_info_ctrl_gated_we; + assign alert_info_ctrl_gated_we = alert_info_ctrl_we & alert_regwen_qs; + // F[en]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_alert_info_ctrl_en ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (alert_info_ctrl_gated_we), + .wd (alert_info_ctrl_en_wd), + + // from internal hardware + .de (hw2reg.alert_info_ctrl.en.de), + .d (hw2reg.alert_info_ctrl.en.d), + + // to internal hardware + .qe (), + .q (reg2hw.alert_info_ctrl.en.q), + .ds (), + + // to register interface (read) + .qs (alert_info_ctrl_en_qs) + ); + + // F[index]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_alert_info_ctrl_index ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (alert_info_ctrl_gated_we), + .wd (alert_info_ctrl_index_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.alert_info_ctrl.index.q), + .ds (), + + // to register interface (read) + .qs (alert_info_ctrl_index_qs) + ); + + + // R[alert_info_attr]: V(True) + prim_subreg_ext #( + .DW (4) + ) u_alert_info_attr ( + .re (alert_info_attr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.alert_info_attr.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (alert_info_attr_qs) + ); + + + // R[alert_info]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_alert_info ( + .re (alert_info_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.alert_info.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (alert_info_qs) + ); + + + // R[cpu_regwen]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_cpu_regwen ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (cpu_regwen_we), + .wd (cpu_regwen_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (cpu_regwen_qs) + ); + + + // R[cpu_info_ctrl]: V(False) + // Create REGWEN-gated WE signal + logic cpu_info_ctrl_gated_we; + assign cpu_info_ctrl_gated_we = cpu_info_ctrl_we & cpu_regwen_qs; + // F[en]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_cpu_info_ctrl_en ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (cpu_info_ctrl_gated_we), + .wd (cpu_info_ctrl_en_wd), + + // from internal hardware + .de (hw2reg.cpu_info_ctrl.en.de), + .d (hw2reg.cpu_info_ctrl.en.d), + + // to internal hardware + .qe (), + .q (reg2hw.cpu_info_ctrl.en.q), + .ds (), + + // to register interface (read) + .qs (cpu_info_ctrl_en_qs) + ); + + // F[index]: 7:4 + prim_subreg #( + .DW (4), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (4'h0), + .Mubi (1'b0) + ) u_cpu_info_ctrl_index ( + // sync clock and reset required for this register + .clk_i (clk_por_i), + .rst_ni (rst_por_ni), + + // from register interface + .we (cpu_info_ctrl_gated_we), + .wd (cpu_info_ctrl_index_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.cpu_info_ctrl.index.q), + .ds (), + + // to register interface (read) + .qs (cpu_info_ctrl_index_qs) + ); + + + // R[cpu_info_attr]: V(True) + prim_subreg_ext #( + .DW (4) + ) u_cpu_info_attr ( + .re (cpu_info_attr_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.cpu_info_attr.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (cpu_info_attr_qs) + ); + + + // R[cpu_info]: V(True) + prim_subreg_ext #( + .DW (32) + ) u_cpu_info ( + .re (cpu_info_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.cpu_info.d), + .qre (), + .qe (), + .q (), + .ds (), + .qs (cpu_info_qs) + ); + + + // Subregister 0 of Multireg sw_rst_regwen + // R[sw_rst_regwen_0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_regwen_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_regwen_0_we), + .wd (sw_rst_regwen_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (sw_rst_regwen_0_qs) + ); + + + // Subregister 1 of Multireg sw_rst_regwen + // R[sw_rst_regwen_1]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_regwen_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_regwen_1_we), + .wd (sw_rst_regwen_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (sw_rst_regwen_1_qs) + ); + + + // Subregister 2 of Multireg sw_rst_regwen + // R[sw_rst_regwen_2]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessW0C), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_regwen_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_regwen_2_we), + .wd (sw_rst_regwen_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (sw_rst_regwen_2_qs) + ); + + + // Subregister 0 of Multireg sw_rst_ctrl_n + // R[sw_rst_ctrl_n_0]: V(False) + // Create REGWEN-gated WE signal + logic sw_rst_ctrl_n_0_gated_we; + assign sw_rst_ctrl_n_0_gated_we = sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_ctrl_n_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_ctrl_n_0_gated_we), + .wd (sw_rst_ctrl_n_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_ctrl_n[0].q), + .ds (), + + // to register interface (read) + .qs (sw_rst_ctrl_n_0_qs) + ); + + + // Subregister 1 of Multireg sw_rst_ctrl_n + // R[sw_rst_ctrl_n_1]: V(False) + // Create REGWEN-gated WE signal + logic sw_rst_ctrl_n_1_gated_we; + assign sw_rst_ctrl_n_1_gated_we = sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_ctrl_n_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_ctrl_n_1_gated_we), + .wd (sw_rst_ctrl_n_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_ctrl_n[1].q), + .ds (), + + // to register interface (read) + .qs (sw_rst_ctrl_n_1_qs) + ); + + + // Subregister 2 of Multireg sw_rst_ctrl_n + // R[sw_rst_ctrl_n_2]: V(False) + // Create REGWEN-gated WE signal + logic sw_rst_ctrl_n_2_gated_we; + assign sw_rst_ctrl_n_2_gated_we = sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs; + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h1), + .Mubi (1'b0) + ) u_sw_rst_ctrl_n_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (sw_rst_ctrl_n_2_gated_we), + .wd (sw_rst_ctrl_n_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.sw_rst_ctrl_n[2].q), + .ds (), + + // to register interface (read) + .qs (sw_rst_ctrl_n_2_qs) + ); + + + // R[err_code]: V(False) + // F[reg_intg_err]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_err_code_reg_intg_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.err_code.reg_intg_err.de), + .d (hw2reg.err_code.reg_intg_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.err_code.reg_intg_err.q), + .ds (), + + // to register interface (read) + .qs (err_code_reg_intg_err_qs) + ); + + // F[reset_consistency_err]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_err_code_reset_consistency_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.err_code.reset_consistency_err.de), + .d (hw2reg.err_code.reset_consistency_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.err_code.reset_consistency_err.q), + .ds (), + + // to register interface (read) + .qs (err_code_reset_consistency_err_qs) + ); + + // F[fsm_err]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_err_code_fsm_err ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.err_code.fsm_err.de), + .d (hw2reg.err_code.fsm_err.d), + + // to internal hardware + .qe (), + .q (reg2hw.err_code.fsm_err.q), + .ds (), + + // to register interface (read) + .qs (err_code_fsm_err_qs) + ); + + + + logic [17:0] addr_hit; + always_comb begin + addr_hit[ 0] = (reg_addr == RSTMGR_ALERT_TEST_OFFSET); + addr_hit[ 1] = (reg_addr == RSTMGR_RESET_REQ_OFFSET); + addr_hit[ 2] = (reg_addr == RSTMGR_RESET_INFO_OFFSET); + addr_hit[ 3] = (reg_addr == RSTMGR_ALERT_REGWEN_OFFSET); + addr_hit[ 4] = (reg_addr == RSTMGR_ALERT_INFO_CTRL_OFFSET); + addr_hit[ 5] = (reg_addr == RSTMGR_ALERT_INFO_ATTR_OFFSET); + addr_hit[ 6] = (reg_addr == RSTMGR_ALERT_INFO_OFFSET); + addr_hit[ 7] = (reg_addr == RSTMGR_CPU_REGWEN_OFFSET); + addr_hit[ 8] = (reg_addr == RSTMGR_CPU_INFO_CTRL_OFFSET); + addr_hit[ 9] = (reg_addr == RSTMGR_CPU_INFO_ATTR_OFFSET); + addr_hit[10] = (reg_addr == RSTMGR_CPU_INFO_OFFSET); + addr_hit[11] = (reg_addr == RSTMGR_SW_RST_REGWEN_0_OFFSET); + addr_hit[12] = (reg_addr == RSTMGR_SW_RST_REGWEN_1_OFFSET); + addr_hit[13] = (reg_addr == RSTMGR_SW_RST_REGWEN_2_OFFSET); + addr_hit[14] = (reg_addr == RSTMGR_SW_RST_CTRL_N_0_OFFSET); + addr_hit[15] = (reg_addr == RSTMGR_SW_RST_CTRL_N_1_OFFSET); + addr_hit[16] = (reg_addr == RSTMGR_SW_RST_CTRL_N_2_OFFSET); + addr_hit[17] = (reg_addr == RSTMGR_ERR_CODE_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(RSTMGR_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(RSTMGR_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(RSTMGR_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(RSTMGR_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(RSTMGR_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(RSTMGR_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(RSTMGR_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(RSTMGR_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(RSTMGR_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(RSTMGR_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(RSTMGR_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(RSTMGR_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(RSTMGR_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(RSTMGR_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(RSTMGR_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(RSTMGR_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(RSTMGR_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(RSTMGR_PERMIT[17] & ~reg_be))))); + end + + // Generate write-enables + assign alert_test_we = addr_hit[0] & reg_we & !reg_error; + + assign alert_test_fatal_fault_wd = reg_wdata[0]; + + assign alert_test_fatal_cnsty_fault_wd = reg_wdata[1]; + assign reset_req_we = addr_hit[1] & reg_we & !reg_error; + + assign reset_req_wd = reg_wdata[3:0]; + assign reset_info_we = addr_hit[2] & reg_we & !reg_error; + + assign reset_info_por_wd = reg_wdata[0]; + + assign reset_info_low_power_exit_wd = reg_wdata[1]; + + assign reset_info_sw_reset_wd = reg_wdata[2]; + + assign reset_info_hw_req_wd = reg_wdata[6:3]; + assign alert_regwen_we = addr_hit[3] & reg_we & !reg_error; + + assign alert_regwen_wd = reg_wdata[0]; + assign alert_info_ctrl_we = addr_hit[4] & reg_we & !reg_error; + + assign alert_info_ctrl_en_wd = reg_wdata[0]; + + assign alert_info_ctrl_index_wd = reg_wdata[7:4]; + assign alert_info_attr_re = addr_hit[5] & reg_re & !reg_error; + assign alert_info_re = addr_hit[6] & reg_re & !reg_error; + assign cpu_regwen_we = addr_hit[7] & reg_we & !reg_error; + + assign cpu_regwen_wd = reg_wdata[0]; + assign cpu_info_ctrl_we = addr_hit[8] & reg_we & !reg_error; + + assign cpu_info_ctrl_en_wd = reg_wdata[0]; + + assign cpu_info_ctrl_index_wd = reg_wdata[7:4]; + assign cpu_info_attr_re = addr_hit[9] & reg_re & !reg_error; + assign cpu_info_re = addr_hit[10] & reg_re & !reg_error; + assign sw_rst_regwen_0_we = addr_hit[11] & reg_we & !reg_error; + + assign sw_rst_regwen_0_wd = reg_wdata[0]; + assign sw_rst_regwen_1_we = addr_hit[12] & reg_we & !reg_error; + + assign sw_rst_regwen_1_wd = reg_wdata[0]; + assign sw_rst_regwen_2_we = addr_hit[13] & reg_we & !reg_error; + + assign sw_rst_regwen_2_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_0_we = addr_hit[14] & reg_we & !reg_error; + + assign sw_rst_ctrl_n_0_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_1_we = addr_hit[15] & reg_we & !reg_error; + + assign sw_rst_ctrl_n_1_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_2_we = addr_hit[16] & reg_we & !reg_error; + + assign sw_rst_ctrl_n_2_wd = reg_wdata[0]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = alert_test_we; + reg_we_check[1] = reset_req_we; + reg_we_check[2] = reset_info_we; + reg_we_check[3] = alert_regwen_we; + reg_we_check[4] = alert_info_ctrl_gated_we; + reg_we_check[5] = 1'b0; + reg_we_check[6] = 1'b0; + reg_we_check[7] = cpu_regwen_we; + reg_we_check[8] = cpu_info_ctrl_gated_we; + reg_we_check[9] = 1'b0; + reg_we_check[10] = 1'b0; + reg_we_check[11] = sw_rst_regwen_0_we; + reg_we_check[12] = sw_rst_regwen_1_we; + reg_we_check[13] = sw_rst_regwen_2_we; + reg_we_check[14] = sw_rst_ctrl_n_0_gated_we; + reg_we_check[15] = sw_rst_ctrl_n_1_gated_we; + reg_we_check[16] = sw_rst_ctrl_n_2_gated_we; + reg_we_check[17] = 1'b0; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + end + + addr_hit[1]: begin + reg_rdata_next[3:0] = reset_req_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = reset_info_por_qs; + reg_rdata_next[1] = reset_info_low_power_exit_qs; + reg_rdata_next[2] = reset_info_sw_reset_qs; + reg_rdata_next[6:3] = reset_info_hw_req_qs; + end + + addr_hit[3]: begin + reg_rdata_next[0] = alert_regwen_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = alert_info_ctrl_en_qs; + reg_rdata_next[7:4] = alert_info_ctrl_index_qs; + end + + addr_hit[5]: begin + reg_rdata_next[3:0] = alert_info_attr_qs; + end + + addr_hit[6]: begin + reg_rdata_next[31:0] = alert_info_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = cpu_regwen_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = cpu_info_ctrl_en_qs; + reg_rdata_next[7:4] = cpu_info_ctrl_index_qs; + end + + addr_hit[9]: begin + reg_rdata_next[3:0] = cpu_info_attr_qs; + end + + addr_hit[10]: begin + reg_rdata_next[31:0] = cpu_info_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = sw_rst_regwen_0_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = sw_rst_regwen_1_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = sw_rst_regwen_2_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = sw_rst_ctrl_n_0_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = sw_rst_ctrl_n_1_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = sw_rst_ctrl_n_2_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = err_code_reg_intg_err_qs; + reg_rdata_next[1] = err_code_reset_consistency_err_qs; + reg_rdata_next[2] = err_code_fsm_err_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util/BUILD.bazel b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util/BUILD.bazel new file mode 100644 index 00000000000..153a7c07877 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util/BUILD.bazel @@ -0,0 +1,20 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +py_library( + name = "ipconfig", + srcs = ["ipconfig.py"], +) + +py_library( + name = "dt", + srcs = ["dt.py"], + deps = [ + ":ipconfig", + "//util/dtgen:helper", + "//util/topgen", + ], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util/dt.py b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util/dt.py new file mode 100644 index 00000000000..a425a422232 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util/dt.py @@ -0,0 +1,202 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +"""This contains a class which is used to help generate the device tables (DT) +files. +""" +from dtgen.helper import IpHelper, Extension, StructType, ScalarType, ArrayMapType +from topgen.lib import Name +from collections import OrderedDict +import os +import sys + +sys.path.insert(0, os.path.dirname(os.path.realpath(__file__))) +from ipconfig import IpConfig # noqa: E402 + +HEADER_EXT_TEMPLATE = """ +/** + * Get the number of software resets. + * + * @param dt Instance of rstmgr. + * @return Number of software resets. + */ +size_t dt_rstmgr_sw_reset_count(dt_rstmgr_t dt); + +/** + * Get the reset ID of a software reset. + * + * The resets are ordered in the same way as they appear in the registers. + * + * @param dt Instance of rstmgr. + * @param idx Index of the software reset, between 0 and `dt_rstmgr_sw_reset_count(dt)-1`. + * @return Reset ID, or `kDtResetUnknown` for invalid parameters. + */ +dt_reset_t dt_rstmgr_sw_reset(dt_rstmgr_t dt, size_t idx); + +/** + * Description of a reset request source. + * + * A reset request source is always identified by the instance ID of the module where it comes + * from. In principle, some instances could have several reset requests. If this is the case, + * the `rst_req` can be used to distinguish between those. It should be cast to the + * `dt__reset_req_t` type of the corresponding IP. + * + * WARNING At the moment, three hardcoded reset requests are treated specially and have their + * `rst_req` field set to `0` because there is no corresponding reset request declared by those IPs: + * - the main power glitch reset request, coming from the `pwrmgr`, + * - the escalation reset request, coming from the `alert_handler`, + * - the non-debug-module reset request, coming from the `rv_dm`. + */ +%(reset_req_src_struct)s + +/** + * Get the number of hardware reset requests. + * + * @param dt Instance of rstmgr. + * @return Number of reset requests. + */ +size_t dt_rstmgr_hw_reset_req_src_count(dt_rstmgr_t dt); + +/** + * Get the description of a reset request. + * + * The reset requests are ordered as they appear in the registers. + * + * @param dt Instance of rstmgr. + * @param idx Index of the reset request source, between 0 and + * `dt_pwrmgr_hw_reset_req_src_count(dt)-1`. + * @return Description of the reset. + */ +dt_rstmgr_reset_req_src_t dt_rstmgr_hw_reset_req_src(dt_rstmgr_t dt, size_t idx); +""" + +SOURCE_EXT_TEMPLATE = """ +size_t dt_rstmgr_sw_reset_count(dt_rstmgr_t dt) { + return %(sw_reset_count)d; +} + +dt_reset_t dt_rstmgr_sw_reset(dt_rstmgr_t dt, size_t idx) { + if (idx >= %(sw_reset_count)d) { + return kDtResetUnknown; + } + return TRY_GET_DT(dt, kDtResetUnknown)->rstmgr_ext.sw_rst[idx]; +} +""" + + +class RstmgrExt(Extension): + RSTREQ_SOURCE_STRUCT_NAME = Name.from_snake_case("dt_rstmgr_reset_req_src") + RSTREQ_SOURCE_INST_FIELD_NAME = Name(["inst", "id"]) + RSTREQ_SOURCE_REQ_FIELD_NAME = Name(["reset", "req"]) + + SW_RESETS_FIELD_NAME = Name(["sw", "rst"]) + HW_REQS_FIELD_NAME = Name(["hw", "req"]) + + def __init__(self, ip_helper: IpHelper): + self.ip_helper = ip_helper + if self.ip_helper.ipconfig is None: + raise RuntimeError("the rstmgr extension requires the ipconfig to be provided") + self.ipconfig = IpConfig(self.ip_helper.ipconfig) + + # Create a type to represent a reset request. + self.reset_req_src_struct = StructType(self.RSTREQ_SOURCE_STRUCT_NAME) + self.reset_req_src_struct.add_field( + name = self.RSTREQ_SOURCE_INST_FIELD_NAME, + field_type = ScalarType(self.ip_helper.top_helper.DT_INSTANCE_ID_NAME), + docstring = "Instance ID of the source of this reset request.", + ) + self.reset_req_src_struct.add_field( + name = self.RSTREQ_SOURCE_REQ_FIELD_NAME, + field_type = ScalarType("size_t"), + docstring = "Index of the reset request signal for that instance.", + ) + + def create_ext(ip_helper: IpHelper): + if ip_helper.ip.name == "rstmgr": + return RstmgrExt(ip_helper) + + def extend_dt_ip(self) -> tuple[Name, StructType]: + sw_rsts_count = len(self.ipconfig.sw_rsts_list()) + hw_reqs_count = len(self.ipconfig.hw_reset_req_list()) + + st = StructType() + # Add field to list SW resets. + st.add_field( + name = self.SW_RESETS_FIELD_NAME, + field_type = ArrayMapType( + elem_type = ScalarType(self.ip_helper.top_helper.DT_RESET_ENUM_NAME), + index_type = ScalarType("size_t"), + length = str(sw_rsts_count), + ), + docstring = "List of software resets, in the order of the register fields", + ) + # Add field to list HW reset requests. + st.add_field( + name = self.HW_REQS_FIELD_NAME, + field_type = ArrayMapType( + elem_type = self.reset_req_src_struct, + index_type = ScalarType("size_t"), + length = str(hw_reqs_count), + ), + docstring = "List of hardware reset requests, in the order of the register fields", + ) + return Name(["rstmgr_ext"]), st + + def fill_dt_ip(self, m) -> dict: + sw_rsts = {} + self._extra_includes = OrderedDict() + for (idx, rst) in enumerate(self.ipconfig.sw_rsts_list()): + sw_rsts[str(idx)] = Name.from_snake_case(rst) + hw_reqs = {} + for (idx, reset) in enumerate(self.ipconfig.hw_reset_req_list()): + # NOTE Englishbreakfast pretends to have an escalation signal but + # in fact does not have an alert_handler so we need to special case + # that. Similarly there is no rv_dm. + if self.ip_helper.top_helper.top["name"] == "englishbreakfast" and \ + reset["module"] in ["alert_handler", "rv_dm"]: + inst_id = Name(["unknown"]) + else: + inst_id = Name.from_snake_case(reset["module"]) + # Even though the ipconfig currently models internal and debug reset + # requests like peripherals, they are in reality hardcoded signals and + # therefore there is not correspondingly named reset requests coming from + # those blocks. For now, simply hardwire those to 0 to workaround the issue. + if reset["name"] not in ["Ndm", "MainPwr", "Esc"] and inst_id != Name(["unknown"]): + module_type = self.ip_helper.top_helper.get_module_type(reset["module"]) + self._extra_includes[module_type] = None + rstreq = Name(["dt"]) + rstreq += Name.from_snake_case(module_type) + rstreq += Name(["reset", "req"]) + rstreq += Name.from_snake_case( + self.ip_helper.simplify_reset_request_name(reset["name"])) + rstreq = rstreq.as_c_enum() + else: + rstreq = "0" + hw_reqs[str(idx)] = { + self.RSTREQ_SOURCE_INST_FIELD_NAME: inst_id, + self.RSTREQ_SOURCE_REQ_FIELD_NAME: rstreq, + } + + return { + self.SW_RESETS_FIELD_NAME: sw_rsts, + self.HW_REQS_FIELD_NAME: hw_reqs, + } + + def render_dt_ip(self, pos: Extension.DtIpPos) -> str: + if pos == Extension.DtIpPos.HeaderEnd: + subs = { + 'reset_req_src_struct': self.reset_req_src_struct.render_type_def(), + } + return HEADER_EXT_TEMPLATE % subs + elif pos == Extension.DtIpPos.SourceIncludes: + includes = "" + for ip in self._extra_includes: + includes += f"#include \"dt_{ip}.h\"\n" + return includes + elif pos == Extension.DtIpPos.SourceEnd: + subs = { + 'sw_reset_count': len(self.ipconfig.sw_rsts_list()), + } + return SOURCE_EXT_TEMPLATE % subs + else: + return "" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util/ipconfig.py b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util/ipconfig.py new file mode 100644 index 00000000000..54a79362924 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rstmgr/util/ipconfig.py @@ -0,0 +1,45 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +""" +This contains a class to access the rstmgr's configuration from its ipconfig +files. +""" +from typing import List, Dict + + +class IpConfig: + def __init__(self, ipconfig: object): + """ + Initialize an `IpConfig` from an already loaded and parsed `ipconfig.hjson` + file, as well as a top configuration. + """ + self.param_values = ipconfig["param_values"] + + def sw_rsts_list(self) -> List[str]: + """ + Return the list of SW resets: each reset is described by the name of its + signal. + + The list is ordered in the same order as in the description. + """ + return self.param_values["sw_rsts"] + + def hw_reset_req_list(self) -> List[Dict]: + """ + Return the list of all reset requests: each reset is described by + a dictionary with the following fields: + - `name`: name of the reset request. + - `module`: the module where the reset comes from. + + The list is ordered as in the `HW_REQ` register. + """ + reqs = self.param_values["reqs"] + return [ + { + "name": rst["name"], + "module": rst["module"], + } + # Watch out for the order: this matches what is used in `pwrmgr.hjson.tpl`. + for rst in reqs["peripheral"] + reqs["int"] + reqs["debug"] + ] diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/BUILD new file mode 100644 index 00000000000..da05a31b199 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/BUILD @@ -0,0 +1,25 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ), +) + +filegroup( + name = "doc_files", + srcs = glob([ + "**/*.md", + "**/*.svg", + ]) + ["//hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data:doc_files"], +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/README.md new file mode 100644 index 00000000000..1436784f7a3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/README.md @@ -0,0 +1,26 @@ +# Interrupt Controller Technical Specification + +# Overview + +This document specifies the Interrupt Controller (RV_PLIC) functionality. This +module conforms to the +[Comportable guideline for peripheral functionality](../../../../doc/contributing/hw/comportability/README.md). +See that document for integration overview within the broader top level system. + + +## Features + +- RISC-V Platform-Level Interrupt Controller (PLIC) compliant interrupt controller +- Support arbitrary number of interrupt vectors (up to 255) and targets +- Support interrupt enable, interrupt status registers +- Memory-mapped MSIP register per HART for software interrupt control. + +## Description + +The RV_PLIC module is designed to manage various interrupt sources from the +peripherals. It receives interrupt events as either edge or level of the +incoming interrupt signals (``intr_src_i``) and can notify multiple targets. + +## Compatibility + +The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/BUILD b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/BUILD new file mode 100644 index 00000000000..3a07c386a27 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/BUILD @@ -0,0 +1,15 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +exports_files(["top_darjeeling_no_ibex_rv_plic.ipconfig.hjson"]) + +filegroup( + name = "doc_files", + srcs = glob([ + "rv_plic.hjson", + "*_testplan.hjson", + ]), +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/rv_plic.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/rv_plic.hjson new file mode 100644 index 00000000000..1451479c1e7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/rv_plic.hjson @@ -0,0 +1,210 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +# RV_PLIC register template +# +# Parameter (given by Python tool) +# - src: Number of Interrupt Sources +# - target: Number of Targets that handle interrupt requests +# - prio: Max value of interrupt priorities +# - module_instance_name: Module instance name. +{ + name: "rv_plic", + human_name: "RISC-V platform level interrupt controller", + one_line_desc: "Interrupt controller, adhering to RISC-V PLIC specification", + one_paragraph_desc: ''' + rv_plic is an interrupt controller which handles multiple interrupt sources. Each interrupt + source can be enabled or disabled, and can be given a priority. rv_plic generates an output + that identifies the source with the highest priority amongst those that are currently asserted. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "33", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: "../doc/checklist", + sw_checklist: "/sw/device/lib/dif/dif_rv_plic", + revisions: [ + { + version: "2.0.0", + life_stage: "L1", + design_stage: "D3", + verification_stage: "V2", + dif_stage: "S2", + commit_id: "", + notes: "Use FPV to perform block level verification.", + } + ], + clocking: [{clock: "clk_i", reset: "rst_ni"}], + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + + param_list: [ + { name: "NumSrc", + desc: "Number of interrupt sources", + type: "int", + default: "163", + local: "true" + }, + { name: "NumTarget", + desc: "Number of Targets (Harts)", + type: "int", + default: "1", + local: "true", + }, + { name: "PrioWidth", + desc: "Width of priority signals", + type: "int", + default: "2", + local: "true", + }, + ], + + // In order to not disturb the PLIC address map, we place the alert test + // register manually at a safe offset after the main CSRs. + no_auto_alert_regs: "True", + alert_list: [ + { name: "fatal_fault", + desc: ''' + This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. + ''' + } + ], + + inter_signal_list: [ + { struct: "logic", + type: "uni", + name: "irq", + act: "req", + package: "", + width: "1" + }, + + { struct: "logic", + type: "uni", + name: "irq_id", + act: "req", + package: "", + }, + + { struct: "logic", + type: "uni", + name: "msip", + act: "req", + package: "", + width: "1" + }, + ] + + countermeasures: [ + { name: "BUS.INTEGRITY", + desc: "End-to-end bus integrity scheme." + } + ] + + features: [ + { name: "RV_PLIC.PRIORITY", + desc: '''Each interrupt source can be given a configurable priority.''' + } + { name: "RV_PLIC.ENABLE", + desc: '''Each target has an associated set of interrupt enable bits. Configuring these + controls whether a target will be notified when the interrupt is triggered. + ''' + } + ] + + regwidth: "32", + registers: [ + { multireg: + { name: "PRIO", + desc: "Interrupt Source Priority", + count: "NumSrc", + cname: "RV_PLIC", + swaccess: "rw", + hwaccess: "hro", + compact: false, + fields: [ + { bits: "1:0" } + ], + } + } + { skipto: "0x00001000" } + { multireg: { + name: "IP", + desc: "Interrupt Pending", + count: "NumSrc", + cname: "RV_PLIC", + swaccess: "ro", + hwaccess: "hwo", + fields: [ + { bits: "0", name: "P", desc: "Interrupt Pending of Source" } + ], + tags: [// IP is driven by intr_src, cannot auto-predict + "excl:CsrNonInitTests:CsrExclCheck"], + } + }, + { skipto: "0x2000" } + { multireg: { + name: "IE0", + desc: "Interrupt Enable for Target 0", + count: "NumSrc", + cname: "RV_PLIC", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", name: "E", desc: "Interrupt Enable of Source" } + ], + } + } + { skipto: "0x200000" } + { name: "THRESHOLD0", + desc: "Threshold of priority for Target 0", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "1:0" } + ], + } + { name: "CC0", + desc: '''Claim interrupt by read, complete interrupt by write for Target 0. + Value read/written is interrupt ID. Reading a value of 0 means no pending interrupts.''', + swaccess: "rw", + hwaccess: "hrw", + hwext: "true", + hwqe: "true", + hwre: "true", + fields: [ + { bits: "7:0" } + ], + tags: [// CC register value is related to IP + "excl:CsrNonInitTests:CsrExclCheck"], + } + { skipto: "0x4000000" } + { name: "MSIP0", + desc: '''msip for Hart 0. + Write 1 to here asserts software interrupt for Hart msip_o[0], write 0 to clear.''', + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", + desc: "Software Interrupt Pending register", + } + ], + } + { skipto: "0x4004000" } + { name: "ALERT_TEST", + desc: '''Alert Test Register.''', + swaccess: "wo", + hwaccess: "hro", + hwqe: "True", + hwext: "True", + fields: [ + { bits: "0", + name: "fatal_fault", + desc: "'Write 1 to trigger one alert event of this kind.'", + } + ], + } + ], +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/rv_plic_fpv_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/rv_plic_fpv_testplan.hjson new file mode 100644 index 00000000000..ea0956eff73 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/rv_plic_fpv_testplan.hjson @@ -0,0 +1,73 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "rv_plic" + import_testplans: ["hw/dv/tools/dvsim/testplans/fpv_csr_testplan.hjson"] + testpoints: [ + { + name: LevelTriggeredIp_A + desc: '''If interrupt pending (`ip`) is triggered, and the level indicator is set to + level triggered (`le=0`), then in the prvious clock cycle, the interrupt source + (`intr_src_i) should be set to 1.''' + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: LevelTriggeredIpWithClaim_A + desc: '''If `intr_src_i` is set to 1, level indicator is set to level triggered, and claim + signal is not set, then at the next clock cycle `ip` will be triggered.''' + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: IpStableAfterTriggered_A + desc: "Once `ip` is set, it stays stable until is being claimed." + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: IpClearAfterClaim_A + desc: "Once `ip` is set and being claimed, its value is cleared to 0." + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: IpStableAfterClaimed_A + desc: '''Once `ip` is cleared to 0, it stays stable until completed and being triggered + again.''' + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: TriggerIrqForwardCheck_A + desc: '''If interrupt is enabled (`ie=1`), interrupt pending is set (`ip=1`), interrupt + input has the highest priority among the rest of the inputs, and its priority is + above the threshold. Then in the next clock clcye, the `irq_o` should be triggered, + and the `irq_id_o` will reflect the input ID.''' + stage: V2 + tests: ["rv_plic_assert"] + } + { + name: TriggerIrqBackwardCheck_A + desc: '''If `irq_o` is set to 1, then in the previous clock cycle, the corresponding + `ip` should be set, `ie` should be enabled, and the interrupt source should above the + threshold and have the highest priority.''' + stage: V2 + tests: ["rv_plic_assert"] + + } + { + name: IdChangeWithIrq_A + desc: '''If `irq_id_o` signal is changed and the signal does not change to 0 (value 0 does + not represent any interrupt source ID). Then either of the two condition should have + happened: + - `irq_o` is triggered + - No interrupt triggered, `ip` is set and `ie` is enabled, interrupt source priority is the + largest among the rest of the interrupt, but the interrupt source + priority is smaller than the threshold''' + stage: V2 + tests: ["rv_plic_assert"] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/rv_plic_sec_cm_testplan.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/rv_plic_sec_cm_testplan.hjson new file mode 100644 index 00000000000..d7aac02a08d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/rv_plic_sec_cm_testplan.hjson @@ -0,0 +1,33 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../rv_plic/data/rv_plic.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../rv_plic/data/rv_plic_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_bus_integrity + desc: "Verify the countermeasure(s) BUS.INTEGRITY." + stage: V2S + tests: [] + } + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/top_darjeeling_no_ibex_rv_plic.ipconfig.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/top_darjeeling_no_ibex_rv_plic.ipconfig.hjson new file mode 100644 index 00000000000..b7011116047 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data/top_darjeeling_no_ibex_rv_plic.ipconfig.hjson @@ -0,0 +1,25 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + instance_name: top_darjeeling_no_ibex_rv_plic + param_values: + { + module_instance_name: rv_plic + src: 163 + target: 1 + prio: 3 + topname: darjeeling_no_ibex + uniquified_modules: {} + racl_support: false + } + dtgen: + { + src: + { + type: uint8 + name: num_irq_sources + doc: Number of interrupt sources + } + } +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/defs.bzl b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/defs.bzl new file mode 100644 index 00000000000..3f0452eb56c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/defs.bzl @@ -0,0 +1,9 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +RV_PLIC = opentitan_ip( + name = "rv_plic", + hjson = "//hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/data:rv_plic.hjson", +) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/block_diagram.svg b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/block_diagram.svg new file mode 100644 index 00000000000..ac02b678fa6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/block_diagram.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/checklist.md b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/checklist.md new file mode 100644 index 00000000000..9177f98cdee --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/checklist.md @@ -0,0 +1,264 @@ +# RV_PLIC Checklist + +This checklist is for [Hardware Stage](../../../../../doc/project_governance/development_stages.md) transitions for the [RV_PLIC peripheral](../README.md). +All checklist items refer to the content in the [Checklist.](../../../../../doc/project_governance/checklist/README.md) + +## Design Checklist + +### D1 + +Type | Item | Resolution | Note/Collaterals +--------------|--------------------------------|-------------|------------------ +Documentation | [SPEC_COMPLETE][] | Done | [RV_PLIC Spec][] +Documentation | [CSR_DEFINED][] | Done | +RTL | [CLKRST_CONNECTED][] | Done | +RTL | [IP_TOP][] | Done | +RTL | [IP_INSTANTIABLE][] | Done | +RTL | [PHYSICAL_MACROS_DEFINED_80][] | Done | +RTL | [FUNC_IMPLEMENTED][] | Done | +RTL | [ASSERT_KNOWN_ADDED][] | Done | +Code Quality | [LINT_SETUP][] | Done | + +[RV_PLIC Spec]: ../README.md + +[SPEC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#spec_complete +[CSR_DEFINED]: ../../../../../doc/project_governance/checklist/README.md#csr_defined +[CLKRST_CONNECTED]: ../../../../../doc/project_governance/checklist/README.md#clkrst_connected +[IP_TOP]: ../../../../../doc/project_governance/checklist/README.md#ip_top +[IP_INSTANTIABLE]: ../../../../../doc/project_governance/checklist/README.md#ip_instantiable +[PHYSICAL_MACROS_DEFINED_80]: ../../../../../doc/project_governance/checklist/README.md#physical_macros_defined_80 +[FUNC_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#func_implemented +[ASSERT_KNOWN_ADDED]: ../../../../../doc/project_governance/checklist/README.md#assert_known_added +[LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#lint_setup + +### D2 + +Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES][] | N/A | +Documentation | [BLOCK_DIAGRAM][] | Done | +Documentation | [DOC_INTERFACE][] | Done | +Documentation | [MISSING_FUNC][] | N/A | +Documentation | [FEATURE_FROZEN][] | Done | +RTL | [FEATURE_COMPLETE][] | Done | +RTL | [AREA_CHECK][] | Done | +RTL | [PORT_FROZEN][] | Done | +RTL | [ARCHITECTURE_FROZEN][] | Done | +RTL | [REVIEW_TODO][] | Done | One TODO about Vivado Issue +RTL | [STYLE_X][] | Done | +Code Quality | [LINT_PASS][] | Done | +Code Quality | [CDC_SETUP][] | N/A | +Code Quality | [TIMING_CHECK][] | Done | Fmax @ 50MHz on NexysVideo +Code Quality | [CDC_SYNCMACRO][] | N/A | +Security | [SEC_CM_DOCUMENTED][] | N/A | + +[NEW_FEATURES]: ../../../../../doc/project_governance/checklist/README.md#new_features +[BLOCK_DIAGRAM]: ../../../../../doc/project_governance/checklist/README.md#block_diagram +[DOC_INTERFACE]: ../../../../../doc/project_governance/checklist/README.md#doc_interface +[MISSING_FUNC]: ../../../../../doc/project_governance/checklist/README.md#missing_func +[FEATURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#feature_frozen +[FEATURE_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#feature_complete +[AREA_CHECK]: ../../../../../doc/project_governance/checklist/README.md#area_check +[PORT_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#port_frozen +[ARCHITECTURE_FROZEN]: ../../../../../doc/project_governance/checklist/README.md#architecture_frozen +[REVIEW_TODO]: ../../../../../doc/project_governance/checklist/README.md#review_todo +[STYLE_X]: ../../../../../doc/project_governance/checklist/README.md#style_x +[LINT_PASS]: ../../../../../doc/project_governance/checklist/README.md#lint_pass +[CDC_SETUP]: ../../../../../doc/project_governance/checklist/README.md#cdc_setup +[TIMING_CHECK]: ../../../../../doc/project_governance/checklist/README.md#timing_check +[CDC_SYNCMACRO]: ../../../../../doc/project_governance/checklist/README.md#cdc_syncmacro +[SEC_CM_DOCUMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_documented + +### D2S + + Type | Item | Resolution | Note/Collaterals +--------------|------------------------------|-------------|------------------ +Security | [SEC_CM_ASSETS_LISTED][] | Done | +Security | [SEC_CM_IMPLEMENTED][] | Done | +Security | [SEC_CM_RND_CNST][] | N/A | +Security | [SEC_CM_NON_RESET_FLOPS][] | N/A | +Security | [SEC_CM_SHADOW_REGS][] | N/A | +Security | [SEC_CM_RTL_REVIEWED][] | N/A | +Security | [SEC_CM_COUNCIL_REVIEWED][] | N/A | This block only contains the bus-integrity CM. + +[SEC_CM_ASSETS_LISTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_assets_listed +[SEC_CM_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_implemented +[SEC_CM_RND_CNST]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rnd_cnst +[SEC_CM_NON_RESET_FLOPS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_non_reset_flops +[SEC_CM_SHADOW_REGS]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_shadow_regs +[SEC_CM_RTL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_rtl_reviewed +[SEC_CM_COUNCIL_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_council_reviewed + +### D3 + + Type | Item | Resolution | Note/Collaterals +--------------|-------------------------|-------------|------------------ +Documentation | [NEW_FEATURES_D3][] | Done | +RTL | [TODO_COMPLETE][] | Done | +Code Quality | [LINT_COMPLETE][] | Done | +Code Quality | [CDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Code Quality | [RDC_COMPLETE][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_RTL][] | Done | +Review | [REVIEW_DELETED_FF][] | Waived | No block-level flow available - waived to top-level signoff. +Review | [REVIEW_SW_CHANGE][] | Done | +Review | [REVIEW_SW_ERRATA][] | Done | +Review | Reviewer(s) | Done | eunchan@ gac@ chencindy@ ttrippel@ +Review | Signoff date | Done | 2022-07-25 + +[NEW_FEATURES_D3]: ../../../../../doc/project_governance/checklist/README.md#new_features_d3 +[TODO_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#todo_complete +[LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#lint_complete +[CDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#cdc_complete +[RDC_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#rdc_complete +[REVIEW_RTL]: ../../../../../doc/project_governance/checklist/README.md#review_rtl +[REVIEW_DELETED_FF]: ../../../../../doc/project_governance/checklist/README.md#review_deleted_ff +[REVIEW_SW_CHANGE]: ../../../../../doc/project_governance/checklist/README.md#review_sw_change +[REVIEW_SW_ERRATA]: ../../../../../doc/project_governance/checklist/README.md#review_sw_errata + +## Verification Checklist + +### V1 + + Type | Item | Resolution | Note/Collaterals +--------------|---------------------------------------|-------------|------------------ +Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [rv_plic_fpv_plan](./dv/README.md) +Documentation | [TESTPLAN_COMPLETED][] | Done | +Testbench | [TB_TOP_CREATED][] | Done | +Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done | +Testbench | [SIM_TB_ENV_CREATED][] | N/A | +Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | N/A | +Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done | +Testbench | [TB_GEN_AUTOMATED][] | N/A | +Tests | [SIM_SMOKE_TEST_PASSING][] | N/A | +Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | N/A | +Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Done | +Tool Setup | [SIM_ALT_TOOL_SETUP][] | N/A | +Regression | [SIM_SMOKE_REGRESSION_SETUP][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | N/A | +Regression | [FPV_REGRESSION_SETUP][] | Done | +Coverage | [SIM_COVERAGE_MODEL_ADDED][] | N/A | +Code Quality | [TB_LINT_SETUP][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A | +Review | [DESIGN_SPEC_REVIEWED][] | Done | +Review | [TESTPLAN_REVIEWED][] | Done | +Review | [STD_TEST_CATEGORIES_PLANNED][] | N/A | +Review | [V2_CHECKLIST_SCOPED][] | Done | + +[DV_DOC_DRAFT_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_draft_completed +[TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#testplan_completed +[TB_TOP_CREATED]: ../../../../../doc/project_governance/checklist/README.md#tb_top_created +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#preliminary_assertion_checks_added +[SIM_TB_ENV_CREATED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_created +[SIM_RAL_MODEL_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#sim_ral_model_gen_automated +[CSR_CHECK_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#csr_check_gen_automated +[TB_GEN_AUTOMATED]: ../../../../../doc/project_governance/checklist/README.md#tb_gen_automated +[SIM_SMOKE_TEST_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_test_passing +[SIM_CSR_MEM_TEST_SUITE_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_csr_mem_test_suite_passing +[FPV_MAIN_ASSERTIONS_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_main_assertions_proven +[SIM_ALT_TOOL_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_alt_tool_setup +[SIM_SMOKE_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_smoke_regression_setup +[SIM_NIGHTLY_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_setup +[FPV_REGRESSION_SETUP]: ../../../../../doc/project_governance/checklist/README.md#fpv_regression_setup +[SIM_COVERAGE_MODEL_ADDED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_model_added +[TB_LINT_SETUP]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_setup +[PRE_VERIFIED_SUB_MODULES_V1]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v1 +[DESIGN_SPEC_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#design_spec_reviewed +[TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#testplan_reviewed +[STD_TEST_CATEGORIES_PLANNED]: ../../../../../doc/project_governance/checklist/README.md#std_test_categories_planned +[V2_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v2_checklist_scoped + +### V2 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | N/A | +Documentation | [DV_DOC_COMPLETED][] | Done | +Testbench | [FUNCTIONAL_COVERAGE_IMPLEMENTED][] | N/A | +Testbench | [ALL_INTERFACES_EXERCISED][] | Done | +Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Done | +Testbench | [SIM_TB_ENV_COMPLETED][] | N/A | +Tests | [SIM_ALL_TESTS_PASSING][] | N/A | +Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Done | +Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Done | +Tests | [SIM_FW_SIMULATED][] | N/A | +Regression | [SIM_NIGHTLY_REGRESSION_V2][] | N/A | +Coverage | [SIM_CODE_COVERAGE_V2][] | N/A | +Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | N/A | +Coverage | [FPV_CODE_COVERAGE_V2][] | Done | +Coverage | [FPV_COI_COVERAGE_V2][] | Done | +Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | N/A | +Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Done | +Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Done | +Review | [DV_DOC_TESTPLAN_REVIEWED][] | Not Started | +Review | [V3_CHECKLIST_SCOPED][] | Done | + +[DESIGN_DELTAS_CAPTURED_V2]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v2 +[DV_DOC_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_completed +[FUNCTIONAL_COVERAGE_IMPLEMENTED]: ../../../../../doc/project_governance/checklist/README.md#functional_coverage_implemented +[ALL_INTERFACES_EXERCISED]: ../../../../../doc/project_governance/checklist/README.md#all_interfaces_exercised +[ALL_ASSERTION_CHECKS_ADDED]: ../../../../../doc/project_governance/checklist/README.md#all_assertion_checks_added +[SIM_TB_ENV_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sim_tb_env_completed +[SIM_ALL_TESTS_PASSING]: ../../../../../doc/project_governance/checklist/README.md#sim_all_tests_passing +[FPV_ALL_ASSERTIONS_WRITTEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assertions_written +[FPV_ALL_ASSUMPTIONS_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#fpv_all_assumptions_reviewed +[SIM_FW_SIMULATED]: ../../../../../doc/project_governance/checklist/README.md#sim_fw_simulated +[SIM_NIGHTLY_REGRESSION_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_v2 +[SIM_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_v2 +[SIM_FUNCTIONAL_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_v2 +[FPV_CODE_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_v2 +[FPV_COI_COVERAGE_V2]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_v2 +[PRE_VERIFIED_SUB_MODULES_V2]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v2 +[NO_HIGH_PRIORITY_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_high_priority_issues_pending +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]: ../../../../../doc/project_governance/checklist/README.md#all_low_priority_issues_root_caused +[DV_DOC_TESTPLAN_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#dv_doc_testplan_reviewed +[V3_CHECKLIST_SCOPED]: ../../../../../doc/project_governance/checklist/README.md#v3_checklist_scoped + +### V2S + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------------|-------------|------------------ +Documentation | [SEC_CM_TESTPLAN_COMPLETED][] | Waived | Waived since only 1 standard sec_cm - bus integrity. +Tests | [FPV_SEC_CM_PROVEN][] | Done | The bus integrity cm has been proven formally. +Tests | [SIM_SEC_CM_VERIFIED][] | N/A | This module only has an FPV testbench. +Coverage | [SIM_COVERAGE_REVIEWED][] | N/A | This module only has an FPV testbench. +Review | [SEC_CM_DV_REVIEWED][] | Waived | Waived since only 1 standard sec_cm - bus integrity. + +[SEC_CM_TESTPLAN_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_testplan_completed +[FPV_SEC_CM_PROVEN]: ../../../../../doc/project_governance/checklist/README.md#fpv_sec_cm_proven +[SIM_SEC_CM_VERIFIED]: ../../../../../doc/project_governance/checklist/README.md#sim_sec_cm_verified +[SIM_COVERAGE_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sim_coverage_reviewed +[SEC_CM_DV_REVIEWED]: ../../../../../doc/project_governance/checklist/README.md#sec_cm_dv_reviewed + +### V3 + + Type | Item | Resolution | Note/Collaterals +--------------|-----------------------------------|-------------|------------------ +Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | +Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started | +Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started | +Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started | +Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started | +Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started | +Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started | +Code Quality | [ALL_TODOS_RESOLVED][] | Not Started | +Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started | +Code Quality | [TB_LINT_COMPLETE][] | Not Started | +Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | +Issues | [NO_ISSUES_PENDING][] | Not Started | +Review | Reviewer(s) | Not Started | +Review | Signoff date | Not Started | + +[DESIGN_DELTAS_CAPTURED_V3]: ../../../../../doc/project_governance/checklist/README.md#design_deltas_captured_v3 +[X_PROP_ANALYSIS_COMPLETED]: ../../../../../doc/project_governance/checklist/README.md#x_prop_analysis_completed +[FPV_ASSERTIONS_PROVEN_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#fpv_assertions_proven_at_v3 +[SIM_NIGHTLY_REGRESSION_AT_V3]: ../../../../../doc/project_governance/checklist/README.md#sim_nightly_regression_at_v3 +[SIM_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_code_coverage_at_100 +[SIM_FUNCTIONAL_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#sim_functional_coverage_at_100 +[FPV_CODE_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_code_coverage_at_100 +[FPV_COI_COVERAGE_AT_100]: ../../../../../doc/project_governance/checklist/README.md#fpv_coi_coverage_at_100 +[ALL_TODOS_RESOLVED]: ../../../../../doc/project_governance/checklist/README.md#all_todos_resolved +[NO_TOOL_WARNINGS_THROWN]: ../../../../../doc/project_governance/checklist/README.md#no_tool_warnings_thrown +[TB_LINT_COMPLETE]: ../../../../../doc/project_governance/checklist/README.md#tb_lint_complete +[PRE_VERIFIED_SUB_MODULES_V3]: ../../../../../doc/project_governance/checklist/README.md#pre_verified_sub_modules_v3 +[NO_ISSUES_PENDING]: ../../../../../doc/project_governance/checklist/README.md#no_issues_pending diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/dv/README.md b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/dv/README.md new file mode 100644 index 00000000000..18130a9ce6c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/dv/README.md @@ -0,0 +1,48 @@ +# RV_PLIC DV document + +## Goals +* DV: + * RV_PLIC is decided to verify in FPV only + +* FPV: + * Verify all the RV_PLIC outputs by writing assumptions and assertions with a + FPV based testbench + * Verify TileLink device protocol compliance with a FPV based testbench + +## Current status +* [Design & verification stage](../../../../README.md) + * [HW development stages](../../../../../../doc/project_governance/development_stages.md) +* FPV dashboard (link TBD) + +## Design features +For detailed information on RV_PLIC design features, please see the +[RV_PLIC design specification](../../README.md). + +## Testbench architecture +RV_PLIC FPV testbench has been constructed based on the [formal +architecture](../../../../../formal/README.md). + +### Block diagram +![Block diagram](fpv.svg) + +#### TLUL assertions +* The file `rv_plic_bind.sv` binds the `tlul_assert` [assertions](../../../../../ip/tlul/doc/TlulProtocolChecker.md) + to rv_plic to ensure TileLink interface protocol compliance. +* The `hw/rv_plic/fpv/tb/rv_plic_bind.sv` also binds the `rv_plic_csr_assert_fpv` + under `fpv/vip/` to check if TileLink writes and reads correct + CSRs. + +#### RV_PLIC assertions +The file `rv_plic_bind.sv` binds the `rv_plic_assert` under `rv_plic_assert.sv`. +The assertion file ensures RV_PLIC's outputs (`irq_o` and `irq_id_o`) and important signals (`ip`) are being asserted. + +##### Symbolic variables +Due to there are large number of input interrupt sources, the symbolic variable +is used to reduce the number of repeated assertions code. In RV_PLIC, we +declared two symbolic variables `src_sel` and `tgt_sel` to represent the index for +interrupt source and interrupt target. +Detailed explanation is listed in the +[Symbolic Variables](../../../../../formal/README.md#symbolic-variables) section. + +## Testplan +[Testplan](../../data/rv_plic_fpv_testplan.hjson) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/dv/fpv.svg b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/dv/fpv.svg new file mode 100644 index 00000000000..2f4cfe07985 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/dv/fpv.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/programmers_guide.md b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/programmers_guide.md new file mode 100644 index 00000000000..72fb0979c06 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/programmers_guide.md @@ -0,0 +1,100 @@ +# Programmer's Guide + +## Initialization + +After reset, RV_PLIC doesn't generate any interrupts to any targets even if +interrupt sources are set, as all priorities and thresholds are 0 by default and +all ``IE`` values are 0. Software should configure the above three registers. + +[`PRIO0`](../data/rv_plic.hjson#prio_0) .. [`PRIO31`](../data/rv_plic.hjson#prio_1) registers are unique. So, only one of the targets +shall configure them. + +```c +// Pseudo-code below +void plic_init() { + // Configure priority + // Note that PRIO0 register doesn't affect as intr_src_i[0] is tied to 0. + for (int i = 0; i < N_SOURCE; ++i) { + *(PRIO + i) = value(i); + } +} + +void plic_threshold(tid, threshold) { + *(THRESHOLD + tid) = threshold; +} + +void plic_enable(tid, iid) { + // iid: 0-based ID + int offset = ceil(N_SOURCE / 32) * tid + (iid >> 5); + + *(IE + offset) = *(IE + offset) | (1 << (iid % 32)); +} +``` + +## Handling Interrupt Request Events + +If software receives an interrupt request, it is recommended to follow the steps +shown below (assuming target 0 which uses [`CC0`](../data/rv_plic.hjson#cc0) for claim/complete). + +1. Claim the interrupts right after entering to the interrupt service routine + by reading the [`CC0`](../data/rv_plic.hjson#cc0) register. +2. Determine which interrupt should be serviced based on the values read from + the [`CC0`](../data/rv_plic.hjson#cc0) register. +3. Execute ISR, clearing the originating peripheral interrupt. +4. Write Interrupt ID to [`CC0`](../data/rv_plic.hjson#cc0) +5. Repeat as necessary for other pending interrupts. + +It is possible to have multiple interrupt events claimed. If software claims one +interrupt request, then the process module advertises any pending interrupts +with lower priority unless new higher priority interrupt events occur. If a +higher interrupt event occurs after previous interrupt is claimed, the RV_PLIC +IP advertises the higher priority interrupt. Software may utilize an event +manager inside a loop so that interrupt claiming and completion can be +separated. + +~~~~c +void interrupt_service() { + uint32_t tid = /* ... */; + uint32_t iid = *(CC + tid); + if (iid == 0) { + // Interrupt is claimed by one of other targets. + return; + } + + do { + // Process interrupts... + // ... + + // Finish. + *(CC + tid) = iid; + iid = *(CC + tid); + } while (iid != 0); +} +~~~~ + +As a reference, default interrupt service routines are auto-generated for each +IP, and are documented [here](/sw/apis/isr__testutils_8h.html). + +## Device Interface Functions (DIFs) + +- [Device Interface Functions](../../../../../sw/device/lib/dif/dif_rv_plic.h) + +## Registers + +The RV_PLIC in the top level is generated by topgen tool so that the number of +interrupt sources may be different. + +- IE: CEILING(N_SOURCE / DW) X N_TARGET + Each bit enables corresponding interrupt source. Each target has IE set. +- PRIO: N_SOURCE + Universal set across all targets. Lower n bits are valid. n is determined by + MAX_PRIO parameter +- THRESHOLD: N_TARGET + Priority threshold per target. Only priority of the interrupt greater than + threshold can raise interrupt notification to the target. +- IP: CEILING(N_SOURCE / DW) + Pending bits right after the gateways. Read-only +- CC: N_TARGET + Claim by read, complete by write + +* [Register Table](../data/rv_plic.hjson#interfaces) diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/theory_of_operation.md b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/theory_of_operation.md new file mode 100644 index 00000000000..161a7979787 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/doc/theory_of_operation.md @@ -0,0 +1,118 @@ +# Theory of Operation + +## Block Diagram + +![RV_PLIC Block Diagram](block_diagram.svg) + +## Hardware Interfaces + +* [Interface Tables](../data/rv_plic.hjson#interfaces) + +## Design Details + +### Identifier + +Each interrupt source has a unique ID assigned based upon its bit position +within the input `intr_src_i`. ID ranges from 0 to N, the number of interrupt +sources. ID 0 is reserved and represents no interrupt. The bit 0 of +`intr_src_i` shall be tied to 0 from the outside of RV_PLIC. The +`intr_src_i[i]` bit has an ID of `i`. This ID is used when targets "claim" the +interrupt and to "complete" the interrupt event. + +### Priority and Threshold + +Interrupt sources have configurable priority values. The maximum value of the +priority is configurable through the localparam `MAX_PRIO` in the rv_plic +top-level module. For each target there is a threshold value ([`THRESHOLD0`](../data/rv_plic.hjson#threshold0) for +target 0). RV_PLIC notifies a target of an interrupt only if it's priority is +strictly greater than the target's threshold. Note this means an interrupt with +a priority is 0 is effectively prevented from causing an interrupt at any target +and a target can suppress all interrupts by setting it's threshold to the max +priority value. + +`MAX_PRIO` parameter is most area contributing option in RV_PLIC. If `MAX_PRIO` +is big, then finding the highest priority in Process module may consume a lot of +logic gates. + +### Interrupt Gateways + +The Gateway observes incoming interrupt sources and converts them to a common +interrupt format used internally by RV_PLIC. It can be parameterized to detect +interrupts events on an edge (when the signal changes from **0** to **1**) or +level basis (where the signal remains at **1**). +The choice is a system-integration decision and can be configured via the design parameter `LevelEdgeTrig` for each interrupt request. + +When the gateway detects an interrupt event it raises the interrupt pending bit +([`IP`](../data/rv_plic.hjson#ip)) for that interrupt source. When an interrupt is claimed by a target the +relevant bit of [`IP`](../data/rv_plic.hjson#ip) is cleared. A bit in [`IP`](../data/rv_plic.hjson#ip) will not be reasserted until the +target signals completion of the interrupt. Any new interrupt event between a +bit in [`IP`](../data/rv_plic.hjson#ip) asserting and completing that interrupt is ignored. In particular +this means that for edge triggered interrupts if a new edge is seen after the +source's [`IP`](../data/rv_plic.hjson#ip) bit is asserted but before completion, that edge will be ignored +(counting missed edges as discussed in the RISC-V PLIC specification is not +supported). + +Note that there is no ability for a level triggered interrupt to be cancelled. +If the interrupt drops after the gateway has set a bit in [`IP`](../data/rv_plic.hjson#ip), the bit will +remain set until the interrupt is completed. The SW handler should be conscious +of this and check the interrupt still requires handling in the handler if this +behaviour is possible. + +### Interrupt Enables + +Each target has a set of Interrupt Enable ([`IE0`](../data/rv_plic.hjson#ie0) for target 0) registers. Each +bit in the [`IE0`](../data/rv_plic.hjson#ie0) registers controls the corresponding interrupt source. If an +interrupt source is disabled for a target, then interrupt events from that +source won't trigger an interrupt at the target. RV_PLIC doesn't have a global +interrupt disable feature. + +### Interrupt Claims + +"Claiming" an interrupt is done by a target reading the associated +Claim/Completion register for the target ([`CC0`](../data/rv_plic.hjson#cc0) for target 0). The return value +of the [`CC0`](../data/rv_plic.hjson#cc0) read represents the ID of the pending interrupt that has the +highest priority. If two or more pending interrupts have the same priority, +RV_PLIC chooses the one with lowest ID. Only interrupts that are enabled +for the target can be claimed. The target priority threshold doesn't matter +(this only factors into whether an interrupt is signalled to the target) so +lower priority interrupt IDs can be returned on a read from [`CC0`](../data/rv_plic.hjson#cc0). If no +interrupt is pending (or all pending interrupts are disabled for the target) a +read of [`CC0`](../data/rv_plic.hjson#cc0) returns an ID of 0. + +### Interrupt Completion + +After an interrupt is claimed, the relevant bit of interrupt pending ([`IP`](../data/rv_plic.hjson#ip)) is +cleared, regardless of the status of the `intr_src_i` input value. Until a +target "completes" the interrupt, it won't be re-asserted if a new event for the +interrupt occurs. A target completes the interrupt by writing the ID of the +interrupt to the Claim/Complete register ([`CC0`](../data/rv_plic.hjson#cc0) for target 0). The write event +is forwarded to the Gateway logic, which resets the interrupt status to accept a +new interrupt event. The assumption is that the processor has cleaned up the +originating interrupt event during the time between claim and complete such that +`intr_src_i[ID]` will have de-asserted (unless a new interrupt has occurred). + +```wavejson +{ signal: [ + { name: 'clk', wave: 'p...........' }, + { name: 'intr_src_i[i]', wave: '01....0.1...', node:'.a....e.f...'}, + { name: 'irq_o', wave: '0.1.0......1', node:'..b.d......h'}, + { name: 'irq_id_o', wave: '=.=.=......=', + data: ["0","i","0","i"] }, + { name: 'claim', wave: '0..10.......', node:'...c........'}, + { name: 'complete', wave: '0.........10', node:'..........g.'}, + ], + head:{ + text: 'Interrupt Flow', + tick: 0, + }, +} +``` + +In the example above an interrupt for source ID `i` is configured as a level +interrupt and is raised at a, this results in the target being notified of the +interrupt at b. The target claims the interrupt at c (reading `i` from it's +Claim/Complete register) so `irq_o` deasserts though `intr_src_i[i]` remains +raised. The SW handles the interrupt and it drops at e. However a new interrupt +quickly occurs at f. As complete hasn't been signaled yet `irq_o` isn't +asserted. At g the interrupt is completed (by writing `i` to it's +Claim/Complete register) so at h `irq_o` is asserted due to the new interrupt. diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson new file mode 100644 index 00000000000..e77d6989e7b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/rv_plic_expected_failure.hjson @@ -0,0 +1,12 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +{ + unreachable: + [ + rv_plic_tb.dut.FpvSecCmRegWeOnehotCheck_A:precondition1 + rv_plic_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.Onehot0Check_A:precondition1 + rv_plic_tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.gen_enable_check.gen_not_strict.EnableCheck_A:precondition1 + ] +} diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/rv_plic_fpv.core b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/rv_plic_fpv.core new file mode 100644 index 00000000000..ee6185ebc13 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/rv_plic_fpv.core @@ -0,0 +1,44 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:rv_plic_fpv:0.1 +description: "FPV for RISC-V PLIC" + +filesets: + files_formal: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:all + - lowrisc:darjeeling_no_ibex_ip:rv_plic + - lowrisc:fpv:csr_assert_gen + files: + - tb/rv_plic_bind_fpv.sv + - tb/rv_plic_tb.sv + - vip/rv_plic_assert_fpv.sv + file_type: systemVerilogSource + + +generate: + csr_assert_gen: + generator: csr_assert_gen + parameters: + spec: ../data/rv_plic.hjson + depend: lowrisc:darjeeling_no_ibex_ip:rv_plic + +targets: + default: &default_target + # note, this setting is just used + # to generate a file list for jg + default_tool: icarus + filesets: + - files_formal + generate: + - csr_assert_gen + toplevel: rv_plic_tb + + formal: + <<: *default_target + + lint: + <<: *default_target diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/tb/coverage.tcl b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/tb/coverage.tcl new file mode 100644 index 00000000000..6e89eb5f01c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/tb/coverage.tcl @@ -0,0 +1,88 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# The port data_o in u_data_chk is untied and used nowhere. +check_cov -waiver -add -start_line 25 -end_line 56 -type {statement} -instance\ + {dut.u_reg.u_chk.u_tlul_data_integ_dec.u_data_chk} -comment {data_o is untied} + +# The port data_o in u_data_chk is untied and used nowhere. +check_cov -waiver -add -start_line 25 -end_line 81 -type {statement} -instance\ + {dut.u_reg.u_chk.u_chk} -comment {data_o is untied} + +# Since the interrupts are level triggered, we don't use scr_q register in rv_plic_gateway. So, +# even if this logic is broken, nobody (in the assertions world) cares. +check_cov -waiver -add -start_line 33 -end_line 33 -instance {dut.u_gateway} -comment\ + {Interrupts are level triggered and this assignment would not affect any assertions} + +# To support the waivers above, this assertion is added. So, if interrupts are no longer level +# triggered, this will fail. +assert -name InterruptsLevelTriggered_A {!$rose(dut.u_gateway.le_i)} + +# The ds output port is not connected for any instantiation of prim_subreg or prim_subreg_ext in +# rv_plic. This would only be connected for a writeable register that has an asynchronous clock +# (see reg_top.sv.tpl), and rv_plic doesn't have any of these. As such, the code that is waived +# here (which drives the port) is undetectable. +check_cov -waiver -add -source_file {src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv}\ + -start_line 64 -end_line 64 -type {branch} -comment {Checker coverage is undetectable as ds is\ + unconnected} + +# For all the ip registers, de is true and hence wr_en is true. The branch misses the else part and +# appeared dead. +check_cov -waiver -add -source_file {src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv} -start_line\ + 58 -end_line 58 -type {branch} -comment {wr_en is true and the branch doesn't contain the else\ + part} + +# These two blocking assignment appear as undetectable and making an assertion for them looks +# unreasonable as for this particular instance, they will always be generated as zero. +check_cov -waiver -add -start_line 67 -end_line 68 -type {statement} -instance\ + {dut.u_reg.u_reg_if.u_rsp_intg_gen} -comment {Rsp and Data Intg will always be zero} + +# Waiving all the alert instances for coverage. +foreach alert_sender_inst [get_design_info -list instance -filter "prim_alert_sender$" -regexp] { + check_cov -waiver -add -instance "$alert_sender_inst"\ + -comment {FPV for Alerts has already been done elsewhere} +} + +proc clog2 {NumSrc} { + return [expr {ceil(log($NumSrc)/log(2))}] +} + +# These are all the dead nodes in a binary tree. They are dead because the rightmost nodes at the +# bottom of the tree are tied with 1'b0. Hence, their parents on levels below them also assigned +# with 1'b0. +proc tree {NumSrc} { + set NumLevels [clog2 $NumSrc] + for {set level 1} {$level < $NumLevels} {incr level} { + set h [expr {$NumLevels - $level}] + set node_int [expr {int(1 + floor(($NumSrc-1-2**($h-1))/(2**$h)))}] + set exp1 "dut.gen_target\[0].u_target.u_prim_max_tree" + for {set node $node_int} {$node < 2**$level} {incr node} { + set exp2 ".gen_tree\[$level].gen_level\[$node].gen_nodes.sel" + check_cov -waiver -add -expression "$exp1$exp2" -type {branch} -comment {Dead node} + } + } +} + +tree {186} + +# Preconditions of OnehotCheck_A and Enable_A cannot happen without applying stopat. +# +# Below, we disable the assertions inside the embedded task and enable them inside the task where +# the stopat on reg_we_check lives. +proc move_to_task {task_name assert_list} { + foreach assert_name $assert_list { + task -edit ${task_name} -copy "${assert_name}.*" -regexp + assert -disable -regexp "\\::${assert_name}" + } +} + +task -create notOnehotInpt + +move_to_task notOnehotInpt {\ + .*\.u_prim_reg_we_check.u_prim_onehot_check.Onehot0Check_A\ + .*\.u_prim_reg_we_check.u_prim_onehot_check\..*\.EnableCheck_A\ + .*\.FpvSecCmRegWeOnehotCheck_A\ +} + +stopat -task notOnehotInpt dut.u_reg.reg_we_check diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/tb/rv_plic_bind_fpv.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/tb/rv_plic_bind_fpv.sv new file mode 100644 index 00000000000..f344a014cd1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/tb/rv_plic_bind_fpv.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module rv_plic_bind_fpv; + + import rv_plic_reg_pkg::*; + + bind rv_plic rv_plic_assert_fpv #( + .NumSrc(rv_plic_reg_pkg::NumSrc), + .NumTarget(rv_plic_reg_pkg::NumTarget), + .NumAlerts(rv_plic_reg_pkg::NumAlerts), + .PRIOW(rv_plic_reg_pkg::PrioWidth) + ) rv_plic_assert_fpv( + .clk_i, + .rst_ni, + .intr_src_i, + .alert_rx_i, + .alert_tx_o, + .irq_o, + .irq_id_o, + .msip_o, + .ip, + .ie, + .claim, + .complete, + .prio, + .threshold, + .fatal_alert_i (alerts[0]), + .tl_o + ); + + bind rv_plic tlul_assert #( + .EndpointType("Device") + ) tlul_assert_device ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + + bind rv_plic rv_plic_csr_assert_fpv rv_plic_csr_assert_fpv ( + .clk_i, + .rst_ni, + .h2d (tl_i), + .d2h (tl_o) + ); + +endmodule : rv_plic_bind_fpv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv new file mode 100644 index 00000000000..8a64257766d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv @@ -0,0 +1,40 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Testbench module for rv_plic. Intended to use with a formal tool. + +module rv_plic_tb import rv_plic_reg_pkg::*; #( + // test all implementations + localparam int unsigned NumInstances = 1 +) ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t [NumInstances-1:0] tl_i, + output tlul_pkg::tl_d2h_t [NumInstances-1:0] tl_o, + input [NumInstances-1:0][NumSrc-1:0] intr_src_i, + input prim_alert_pkg::alert_rx_t [NumInstances-1:0][NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumInstances-1:0][NumAlerts-1:0] alert_tx_o, + output [NumInstances-1:0][NumTarget-1:0] irq_o, + output [$clog2(NumSrc)-1:0] irq_id_o [NumInstances][NumTarget], + output logic [NumInstances-1:0][NumTarget-1:0] msip_o +); + + // TODO: once the PLIC is fully parameterizable in RTL, generate + // several instances with different NumSrc and NumTarget configs here + // (in a similar way as this has been done in prim_lfsr_fpv) + // for (genvar k = 0; k < NumInstances; k++) begin : geNumInstances + rv_plic dut ( + .clk_i , + .rst_ni , + .tl_i (tl_i[0]), + .tl_o (tl_o[0]), + .intr_src_i (intr_src_i[0]), + .alert_rx_i (alert_rx_i[0]), + .alert_tx_o (alert_tx_o[0]), + .irq_o (irq_o[0]), + .irq_id_o (irq_id_o[0]), + .msip_o (msip_o[0]) + ); + +endmodule : rv_plic_tb diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv new file mode 100644 index 00000000000..febfb4d8e6f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/fpv/vip/rv_plic_assert_fpv.sv @@ -0,0 +1,122 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// Testbench module for rv_plic. Intended to use with a formal tool. + +`include "prim_assert.sv" + +module rv_plic_assert_fpv #(parameter int NumSrc = 1, + parameter int NumTarget = 1, + parameter int NumAlerts = 1, + parameter int PRIOW = $clog2(7+1) +) ( + input clk_i, + input rst_ni, + input [NumSrc-1:0] intr_src_i, + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + input prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + input [NumTarget-1:0] irq_o, + input [$clog2(NumSrc)-1:0] irq_id_o [NumTarget], + input [NumTarget-1:0] msip_o, + // probe design signals + input [NumSrc-1:0] ip, + input [NumSrc-1:0] ie [NumTarget], + input [NumSrc-1:0] claim, + input [NumSrc-1:0] complete, + input [NumSrc-1:0][PRIOW-1:0] prio, + input [PRIOW-1:0] threshold [NumTarget], + input logic fatal_alert_i, + input tlul_pkg::tl_d2h_t tl_o +); + + localparam int SrcIdxWidth = NumSrc > 1 ? $clog2(NumSrc - 1) : 1; + localparam int TgtIdxWidth = NumTarget > 1 ? $clog2(NumTarget - 1) : 1; + + logic claim_reg, claimed; + logic max_priority; + logic irq; + logic [$clog2(NumSrc)-1:0] i_high_prio; + + // symbolic variables + bit [SrcIdxWidth-1:0] src_sel; + bit [TgtIdxWidth-1:0] tgt_sel; + + `ASSUME_FPV(IsrcRange_M, src_sel > 0 && src_sel < NumSrc, clk_i, !rst_ni) + `ASSUME_FPV(ItgtRange_M, tgt_sel >= 0 && tgt_sel < NumTarget, clk_i, !rst_ni) + `ASSUME_FPV(IsrcStable_M, ##1 $stable(src_sel), clk_i, !rst_ni) + `ASSUME_FPV(ItgtStable_M, ##1 $stable(tgt_sel), clk_i, !rst_ni) + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + claim_reg <= 1'b0; + end else if (claim[src_sel]) begin + claim_reg <= 1'b1; + end else if (complete[src_sel]) begin + claim_reg <= 1'b0; + end + end + + assign claimed = claim_reg || claim[src_sel]; + + always_comb begin + max_priority = 1'b1; + for (int i = 0; i < NumSrc; i++) begin + // conditions that if src_sel has the highest priority with the lowest ID + if (i != src_sel && ip[i] && ie[tgt_sel][i] && + (prio[i] > prio[src_sel] || (prio[i] == prio[src_sel] && i < src_sel))) begin + max_priority = 1'b0; + break; + end + end + end + + always_comb begin + automatic logic [31:0] max_prio = 0; + for (int i = NumSrc-1; i >= 0; i--) begin + if (ip[i] && ie[tgt_sel][i] && prio[i] >= max_prio) begin + max_prio = prio[i]; + i_high_prio = i; // i is the smallest id if have IPs with the same priority + end + end + if (max_prio > threshold[tgt_sel]) irq = 1'b1; + else irq = 1'b0; + end + + // when IP is set, previous cycle should follow edge or level triggered criteria + `ASSERT(LevelTriggeredIp_A, ##3 $rose(ip[src_sel]) |-> $past(intr_src_i[src_sel], 3)) + + // when interrupt is trigger, and nothing claimed yet, then next cycle should assert IP. + `ASSERT(LevelTriggeredIpWithClaim_A, ##2 $past(intr_src_i[src_sel], 2) && + !claimed |=> ip[src_sel]) + + // ip stays stable until claimed, reset to 0 after claimed, and stays 0 until complete + `ASSERT(IpStableAfterTriggered_A, ip[src_sel] && !claimed |=> ip[src_sel]) + `ASSERT(IpClearAfterClaim_A, ip[src_sel] && claim[src_sel] |=> !ip[src_sel]) + `ASSERT(IpStableAfterClaimed_A, claimed |=> !ip[src_sel]) + + // when ip is set and priority is the largest and above threshold, and interrupt enable is set, + // assertion irq_o at next cycle + `ASSERT(TriggerIrqForwardCheck_A, ip[src_sel] && prio[src_sel] > threshold[tgt_sel] && + max_priority && ie[tgt_sel][src_sel] |=> irq_o[tgt_sel]) + + `ASSERT(TriggerIrqBackwardCheck_A, $rose(irq_o[tgt_sel]) |-> + $past(irq) && (irq_id_o[tgt_sel] == $past(i_high_prio))) + + // when irq ID changed, but not to ID=0, irq_o should be high, or irq represents the largest prio + // but smaller than the threshold + `ASSERT(IdChangeWithIrq_A, !$stable(irq_id_o[tgt_sel]) && irq_id_o[tgt_sel] != 0 |-> + irq_o[tgt_sel] || ((irq_id_o[tgt_sel]) == $past(i_high_prio) && !$past(irq))) + + // If a response is coming back from the device, then check if it contains the correct integrity + // bits. + `ASSERT(DataIntg_A, + tl_o.d_valid -> (tlul_pkg::get_data_intg(tl_o.d_data) == tl_o.d_user.data_intg)) + + `ASSERT(RspIntg_A, + tl_o.d_valid -> + (prim_secded_pkg::prim_secded_inv_64_57_enc({51'b0, tlul_pkg::extract_d2h_rsp_intg(tl_o)}) + >> (64-tlul_pkg::D2HRspIntgWidth)) == tl_o.d_user.rsp_intg) + + // When fatal alert happens then only reset can clear it. + `ASSERT(FatalAlertNeverdrops_A, ##1 !$fell(fatal_alert_i)) +endmodule : rv_plic_assert_fpv diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/lint/rv_plic.vlt b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/lint/rv_plic.vlt new file mode 100644 index 00000000000..f9318e609c6 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/lint/rv_plic.vlt @@ -0,0 +1,7 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for rv_plic + +`verilator_config diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/lint/rv_plic.waiver b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/lint/rv_plic.waiver new file mode 100644 index 00000000000..9e84bd90212 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/lint/rv_plic.waiver @@ -0,0 +1,22 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for Platform-Level Interrupt Controller + +waive -rules ONE_BIT_MEM_WIDTH -location {rv_plic.sv} -regexp {Memory '(claim_re|complete_we)' has} \ + -comment "N_TARGET can be 1." + +waive -rules VAR_INDEX_RANGE -location {rv_plic.sv} -regexp {(claim_id|complete_id).* (maximum|minimum) value} \ + -comment "Claim ID is guarded inside target module, complete ID has undeterministic behavior if FW writes OOR value" + +waive -rules HIER_NET_NOT_READ -location {rv_plic.sv} -regexp {[Nn]et 'tl_[io]\.[ad]_(address|param|user)} \ + -comment "Register interface doesn't use upper address and param, user filed" + +waive -rules EXPLICIT_BITLEN -location {rv_plic_target.sv} -regexp {Bit length .* '1'} \ + -comment "i + 1 is assumed as constant and guarded by SRCW" +waive -rules INTEGER -location {rv_plic_target.sv} -regexp {'i' of type int used as} \ + -comment "int i is static and only assigned to irq_id_next when it hits condition" + +waive -rules TWOS_COMP -location {rv_plic_target.sv} -regexp {Explicit two's complement with terms} \ + -comment "This is permissible in this context" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic.sv new file mode 100644 index 00000000000..d974f5d37bc --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic.sv @@ -0,0 +1,442 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// RISC-V Platform-Level Interrupt Controller compliant INTC +// +// Current version doesn't support MSI interrupt but it is easy to add +// the feature. Create one external register and connect qe signal to the +// gateway module (as edge-triggered) +// +// Consider to set MAX_PRIO as small number as possible. It is main factor +// of area increase if edge-triggered counter isn't implemented. +// +// Verilog parameter +// MAX_PRIO: Maximum value of interrupt priority + +`include "prim_assert.sv" + +module rv_plic import rv_plic_reg_pkg::*; #( + parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, + // Number of cycles a differential skew is tolerated on the alert signal + parameter int unsigned AlertSkewCycles = 1, + // OpenTitan IP standardizes on level triggered interrupts, + // hence LevelEdgeTrig is set to all-zeroes by default. + // Note that in case of edge-triggered interrupts, CDC handling is not + // fully implemented yet (this would require instantiating pulse syncs + // and routing the source clocks / resets to the PLIC). + parameter logic [NumSrc-1:0] LevelEdgeTrig = '0, // 0: level, 1: edge + // derived parameter + localparam int SRCW = $clog2(NumSrc) +) ( + input clk_i, + input rst_ni, + + // Bus Interface (device) + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + + // Interrupt Sources + input [NumSrc-1:0] intr_src_i, + + // Alerts + input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i, + output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o, + + // Interrupt notification to targets + output [NumTarget-1:0] irq_o, + output [SRCW-1:0] irq_id_o [NumTarget], + + output logic [NumTarget-1:0] msip_o +); + + rv_plic_reg2hw_t reg2hw; + rv_plic_hw2reg_t hw2reg; + + localparam int MAX_PRIO = 3; + localparam int PRIOW = $clog2(MAX_PRIO+1); + + logic [NumSrc-1:0] ip; + + logic [NumSrc-1:0] ie [NumTarget]; + + logic [NumTarget-1:0] claim_re; // Target read indicator + logic [SRCW-1:0] claim_id [NumTarget]; + logic [NumSrc-1:0] claim; // Converted from claim_re/claim_id + + logic [NumTarget-1:0] complete_we; // Target write indicator + logic [SRCW-1:0] complete_id [NumTarget]; + logic [NumSrc-1:0] complete; // Converted from complete_re/complete_id + + logic [SRCW-1:0] cc_id [NumTarget]; // Write ID + + logic [NumSrc-1:0][PRIOW-1:0] prio; + + logic [PRIOW-1:0] threshold [NumTarget]; + + // Glue logic between rv_plic_reg_top and others + assign cc_id = irq_id_o; + + always_comb begin + claim = '0; + for (int i = 0 ; i < NumTarget ; i++) begin + if (claim_re[i]) claim[claim_id[i]] = 1'b1; + end + end + always_comb begin + complete = '0; + for (int i = 0 ; i < NumTarget ; i++) begin + if (complete_we[i]) complete[complete_id[i]] = 1'b1; + end + end + + //`ASSERT_PULSE(claimPulse, claim_re[i]) + //`ASSERT_PULSE(completePulse, complete_we[i]) + + `ASSERT(onehot0Claim, $onehot0(claim_re)) + + `ASSERT(onehot0Complete, $onehot0(complete_we)) + + ////////////// + // Priority // + ////////////// + assign prio[0] = reg2hw.prio[0].q; + assign prio[1] = reg2hw.prio[1].q; + assign prio[2] = reg2hw.prio[2].q; + assign prio[3] = reg2hw.prio[3].q; + assign prio[4] = reg2hw.prio[4].q; + assign prio[5] = reg2hw.prio[5].q; + assign prio[6] = reg2hw.prio[6].q; + assign prio[7] = reg2hw.prio[7].q; + assign prio[8] = reg2hw.prio[8].q; + assign prio[9] = reg2hw.prio[9].q; + assign prio[10] = reg2hw.prio[10].q; + assign prio[11] = reg2hw.prio[11].q; + assign prio[12] = reg2hw.prio[12].q; + assign prio[13] = reg2hw.prio[13].q; + assign prio[14] = reg2hw.prio[14].q; + assign prio[15] = reg2hw.prio[15].q; + assign prio[16] = reg2hw.prio[16].q; + assign prio[17] = reg2hw.prio[17].q; + assign prio[18] = reg2hw.prio[18].q; + assign prio[19] = reg2hw.prio[19].q; + assign prio[20] = reg2hw.prio[20].q; + assign prio[21] = reg2hw.prio[21].q; + assign prio[22] = reg2hw.prio[22].q; + assign prio[23] = reg2hw.prio[23].q; + assign prio[24] = reg2hw.prio[24].q; + assign prio[25] = reg2hw.prio[25].q; + assign prio[26] = reg2hw.prio[26].q; + assign prio[27] = reg2hw.prio[27].q; + assign prio[28] = reg2hw.prio[28].q; + assign prio[29] = reg2hw.prio[29].q; + assign prio[30] = reg2hw.prio[30].q; + assign prio[31] = reg2hw.prio[31].q; + assign prio[32] = reg2hw.prio[32].q; + assign prio[33] = reg2hw.prio[33].q; + assign prio[34] = reg2hw.prio[34].q; + assign prio[35] = reg2hw.prio[35].q; + assign prio[36] = reg2hw.prio[36].q; + assign prio[37] = reg2hw.prio[37].q; + assign prio[38] = reg2hw.prio[38].q; + assign prio[39] = reg2hw.prio[39].q; + assign prio[40] = reg2hw.prio[40].q; + assign prio[41] = reg2hw.prio[41].q; + assign prio[42] = reg2hw.prio[42].q; + assign prio[43] = reg2hw.prio[43].q; + assign prio[44] = reg2hw.prio[44].q; + assign prio[45] = reg2hw.prio[45].q; + assign prio[46] = reg2hw.prio[46].q; + assign prio[47] = reg2hw.prio[47].q; + assign prio[48] = reg2hw.prio[48].q; + assign prio[49] = reg2hw.prio[49].q; + assign prio[50] = reg2hw.prio[50].q; + assign prio[51] = reg2hw.prio[51].q; + assign prio[52] = reg2hw.prio[52].q; + assign prio[53] = reg2hw.prio[53].q; + assign prio[54] = reg2hw.prio[54].q; + assign prio[55] = reg2hw.prio[55].q; + assign prio[56] = reg2hw.prio[56].q; + assign prio[57] = reg2hw.prio[57].q; + assign prio[58] = reg2hw.prio[58].q; + assign prio[59] = reg2hw.prio[59].q; + assign prio[60] = reg2hw.prio[60].q; + assign prio[61] = reg2hw.prio[61].q; + assign prio[62] = reg2hw.prio[62].q; + assign prio[63] = reg2hw.prio[63].q; + assign prio[64] = reg2hw.prio[64].q; + assign prio[65] = reg2hw.prio[65].q; + assign prio[66] = reg2hw.prio[66].q; + assign prio[67] = reg2hw.prio[67].q; + assign prio[68] = reg2hw.prio[68].q; + assign prio[69] = reg2hw.prio[69].q; + assign prio[70] = reg2hw.prio[70].q; + assign prio[71] = reg2hw.prio[71].q; + assign prio[72] = reg2hw.prio[72].q; + assign prio[73] = reg2hw.prio[73].q; + assign prio[74] = reg2hw.prio[74].q; + assign prio[75] = reg2hw.prio[75].q; + assign prio[76] = reg2hw.prio[76].q; + assign prio[77] = reg2hw.prio[77].q; + assign prio[78] = reg2hw.prio[78].q; + assign prio[79] = reg2hw.prio[79].q; + assign prio[80] = reg2hw.prio[80].q; + assign prio[81] = reg2hw.prio[81].q; + assign prio[82] = reg2hw.prio[82].q; + assign prio[83] = reg2hw.prio[83].q; + assign prio[84] = reg2hw.prio[84].q; + assign prio[85] = reg2hw.prio[85].q; + assign prio[86] = reg2hw.prio[86].q; + assign prio[87] = reg2hw.prio[87].q; + assign prio[88] = reg2hw.prio[88].q; + assign prio[89] = reg2hw.prio[89].q; + assign prio[90] = reg2hw.prio[90].q; + assign prio[91] = reg2hw.prio[91].q; + assign prio[92] = reg2hw.prio[92].q; + assign prio[93] = reg2hw.prio[93].q; + assign prio[94] = reg2hw.prio[94].q; + assign prio[95] = reg2hw.prio[95].q; + assign prio[96] = reg2hw.prio[96].q; + assign prio[97] = reg2hw.prio[97].q; + assign prio[98] = reg2hw.prio[98].q; + assign prio[99] = reg2hw.prio[99].q; + assign prio[100] = reg2hw.prio[100].q; + assign prio[101] = reg2hw.prio[101].q; + assign prio[102] = reg2hw.prio[102].q; + assign prio[103] = reg2hw.prio[103].q; + assign prio[104] = reg2hw.prio[104].q; + assign prio[105] = reg2hw.prio[105].q; + assign prio[106] = reg2hw.prio[106].q; + assign prio[107] = reg2hw.prio[107].q; + assign prio[108] = reg2hw.prio[108].q; + assign prio[109] = reg2hw.prio[109].q; + assign prio[110] = reg2hw.prio[110].q; + assign prio[111] = reg2hw.prio[111].q; + assign prio[112] = reg2hw.prio[112].q; + assign prio[113] = reg2hw.prio[113].q; + assign prio[114] = reg2hw.prio[114].q; + assign prio[115] = reg2hw.prio[115].q; + assign prio[116] = reg2hw.prio[116].q; + assign prio[117] = reg2hw.prio[117].q; + assign prio[118] = reg2hw.prio[118].q; + assign prio[119] = reg2hw.prio[119].q; + assign prio[120] = reg2hw.prio[120].q; + assign prio[121] = reg2hw.prio[121].q; + assign prio[122] = reg2hw.prio[122].q; + assign prio[123] = reg2hw.prio[123].q; + assign prio[124] = reg2hw.prio[124].q; + assign prio[125] = reg2hw.prio[125].q; + assign prio[126] = reg2hw.prio[126].q; + assign prio[127] = reg2hw.prio[127].q; + assign prio[128] = reg2hw.prio[128].q; + assign prio[129] = reg2hw.prio[129].q; + assign prio[130] = reg2hw.prio[130].q; + assign prio[131] = reg2hw.prio[131].q; + assign prio[132] = reg2hw.prio[132].q; + assign prio[133] = reg2hw.prio[133].q; + assign prio[134] = reg2hw.prio[134].q; + assign prio[135] = reg2hw.prio[135].q; + assign prio[136] = reg2hw.prio[136].q; + assign prio[137] = reg2hw.prio[137].q; + assign prio[138] = reg2hw.prio[138].q; + assign prio[139] = reg2hw.prio[139].q; + assign prio[140] = reg2hw.prio[140].q; + assign prio[141] = reg2hw.prio[141].q; + assign prio[142] = reg2hw.prio[142].q; + assign prio[143] = reg2hw.prio[143].q; + assign prio[144] = reg2hw.prio[144].q; + assign prio[145] = reg2hw.prio[145].q; + assign prio[146] = reg2hw.prio[146].q; + assign prio[147] = reg2hw.prio[147].q; + assign prio[148] = reg2hw.prio[148].q; + assign prio[149] = reg2hw.prio[149].q; + assign prio[150] = reg2hw.prio[150].q; + assign prio[151] = reg2hw.prio[151].q; + assign prio[152] = reg2hw.prio[152].q; + assign prio[153] = reg2hw.prio[153].q; + assign prio[154] = reg2hw.prio[154].q; + assign prio[155] = reg2hw.prio[155].q; + assign prio[156] = reg2hw.prio[156].q; + assign prio[157] = reg2hw.prio[157].q; + assign prio[158] = reg2hw.prio[158].q; + assign prio[159] = reg2hw.prio[159].q; + assign prio[160] = reg2hw.prio[160].q; + assign prio[161] = reg2hw.prio[161].q; + assign prio[162] = reg2hw.prio[162].q; + + ////////////////////// + // Interrupt Enable // + ////////////////////// + for (genvar s = 0; s < 163; s++) begin : gen_ie0 + assign ie[0][s] = reg2hw.ie0[s].q; + end + + //////////////////////// + // THRESHOLD register // + //////////////////////// + assign threshold[0] = reg2hw.threshold0.q; + + ///////////////// + // CC register // + ///////////////// + assign claim_re[0] = reg2hw.cc0.re; + assign claim_id[0] = irq_id_o[0]; + assign complete_we[0] = reg2hw.cc0.qe; + assign complete_id[0] = reg2hw.cc0.q; + assign hw2reg.cc0.d = cc_id[0]; + + /////////////////// + // MSIP register // + /////////////////// + assign msip_o[0] = reg2hw.msip0.q; + + //////// + // IP // + //////// + for (genvar s = 0; s < 163; s++) begin : gen_ip + assign hw2reg.ip[s].de = 1'b1; // Always write + assign hw2reg.ip[s].d = ip[s]; + end + + ////////////// + // Gateways // + ////////////// + + // Synchronize all incoming interrupt requests. + logic [NumSrc-1:0] intr_src_synced; + prim_flop_2sync #( + .Width(NumSrc) + ) u_prim_flop_2sync ( + .clk_i, + .rst_ni, + .d_i(intr_src_i), + .q_o(intr_src_synced) + ); + + rv_plic_gateway #( + .N_SOURCE (NumSrc) + ) u_gateway ( + .clk_i, + .rst_ni, + + .src_i (intr_src_synced), + .le_i (LevelEdgeTrig), + + .claim_i (claim), + .complete_i (complete), + + .ip_o (ip) + ); + + /////////////////////////////////// + // Target interrupt notification // + /////////////////////////////////// + for (genvar i = 0 ; i < NumTarget ; i++) begin : gen_target + rv_plic_target #( + .N_SOURCE (NumSrc), + .MAX_PRIO (MAX_PRIO) + ) u_target ( + .clk_i, + .rst_ni, + + .ip_i (ip), + .ie_i (ie[i]), + + .prio_i (prio), + .threshold_i (threshold[i]), + + .irq_o (irq_o[i]), + .irq_id_o (irq_id_o[i]) + + ); + end + + //////////// + // Alerts // + //////////// + + logic [NumAlerts-1:0] alert_test, alerts; + + assign alert_test = { + reg2hw.alert_test.q & + reg2hw.alert_test.qe + }; + + for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx + prim_alert_sender #( + .AsyncOn(AlertAsyncOn[i]), + .SkewCycles(AlertSkewCycles), + .IsFatal(1'b1) + ) u_prim_alert_sender ( + .clk_i, + .rst_ni, + .alert_test_i ( alert_test[i] ), + .alert_req_i ( alerts[i] ), + .alert_ack_o ( ), + .alert_state_o ( ), + .alert_rx_i ( alert_rx_i[i] ), + .alert_tx_o ( alert_tx_o[i] ) + ); + end + + //////////////////////// + // Register interface // + //////////////////////// + // Limitation of register tool prevents the module from having flexibility to parameters + // So, signals are manually tied at the top. + rv_plic_reg_top u_reg ( + .clk_i, + .rst_ni, + + .tl_i, + .tl_o, + + .reg2hw, + .hw2reg, + + // SEC_CM: BUS.INTEGRITY + .intg_err_o(alerts[0]) + ); + + // Assertions + `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid) + `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready) + `ASSERT_KNOWN(IrqKnownO_A, irq_o) + `ASSERT_KNOWN(MsipKnownO_A, msip_o) + for (genvar k = 0; k < NumTarget; k++) begin : gen_irq_id_known + `ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o[k]) + end + + // Assume + `ASSUME(Irq0Tied_A, intr_src_i[0] == 1'b0) + + // This assertion should be provable in FPV because we don't have a block-level DV environment. It + // is trying to say that any integrity error detected inside the register block (u_reg) will cause + // an alert to be asserted within at most _SEC_CM_ALERT_MAX_CYC cycles. + // + // This isn't *quite* true because there are two extra requirements for prim_alert_sender to send + // an alert with alert_p high: + // + // - The multi-phase alert handshake might not be in the expected phase. Rather than adding an + // assumption that says alert_rx_i acks a signal when it is raised, we cheat and add a + // precondition about the initial state of the prim_alert_sender FSM, guaranteeing that we're + // not waiting for an ack. + // + // - The prim_alert_sender musn't detect a signal integrity issue on the alert signal coming in + // (alert_rx_i). Normally FpvSecCm tests get analysed with an FPV_ALERT_NO_SIGINT_ERR define, + // but we don't have that defined here. To avoid this happening, we want an assertion of the + // form "If no integrity error is detected for _SEC_CM_ALERT_MAX_CYC cycles, the alert_p signal + // must go high". To encode this cleanly in SVA, we actually say "We can't have neither an + // integrity error nor an alert signal for too many cycles". + `ASSERT(FpvSecCmBusIntegrity_A, + ($rose(u_reg.intg_err) && + gen_alert_tx[0].u_prim_alert_sender.state_q == gen_alert_tx[0].u_prim_alert_sender.Idle) + |-> + not ((!gen_alert_tx[0].u_prim_alert_sender.sigint_detected && !alert_tx_o[0].alert_p) + [*`_SEC_CM_ALERT_MAX_CYC])) + + // Alert assertions for reg_we onehot check + `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT_IN(RegWeOnehotCheck_A, + u_reg, + gen_alert_tx[0].u_prim_alert_sender.alert_req_i) +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_gateway.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_gateway.sv new file mode 100644 index 00000000000..b6e158004c3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_gateway.sv @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// RISC-V Platform-Level Interrupt Gateways module + +module rv_plic_gateway #( + parameter int N_SOURCE = 32 +) ( + input clk_i, + input rst_ni, + + input [N_SOURCE-1:0] src_i, + input [N_SOURCE-1:0] le_i, // Level0 Edge1 + + input [N_SOURCE-1:0] claim_i, // $onehot0(claim_i) + input [N_SOURCE-1:0] complete_i, // $onehot0(complete_i) + + output logic [N_SOURCE-1:0] ip_o +); + + logic [N_SOURCE-1:0] ia; // Interrupt Active + + // The set[i] signal says that interrupt i is being requested. If the interrupt is level triggered + // (because le_i[i]=0) then this just asks that src_i[i] is true. If the interrupt is edge + // triggered (because le_i[i]=1) then we also ask that src_i[i] was false on the previous cycle + // (which is registered with src_q). + logic [N_SOURCE-1:0] set; + logic [N_SOURCE-1:0] src_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) src_q <= '0; + else src_q <= src_i; + end + + assign set = src_i & ~(src_q & le_i); + + // Interrupt pending is set by source (depends on le_i), cleared by claim_i. + // Until interrupt is claimed, set doesn't affect ip_o. + // RISC-V PLIC spec mentioned it can have counter for edge triggered + // But skipped the feature as counter consumes substantial logic size. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ip_o <= '0; + end else begin + ip_o <= (ip_o | (set & ~ia & ~ip_o)) & (~(ip_o & claim_i)); + end + end + + // Interrupt active is to control ip_o. If ip_o is set then until completed + // by target, ip_o shouldn't be set by source even claim_i can clear ip_o. + // ia can be cleared only when ia was set. If `set` and `complete_i` happen + // at the same time, always `set` wins. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + ia <= '0; + end else begin + ia <= (ia | (set & ~ia)) & (~(ia & complete_i & ~ip_o)); + end + end + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv new file mode 100644 index 00000000000..e56ec61eb0e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_reg_pkg.sv @@ -0,0 +1,633 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package rv_plic_reg_pkg; + + // Param list + parameter int NumSrc = 163; + parameter int NumTarget = 1; + parameter int PrioWidth = 2; + parameter int NumAlerts = 1; + + // Address widths within the block + parameter int BlockAw = 27; + + // Number of registers for every interface + parameter int NumRegs = 179; + + // Alert indices + typedef enum int { + AlertFatalFaultIdx = 0 + } rv_plic_alert_idx_t; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_prio_mreg_t; + + typedef struct packed { + logic q; + } rv_plic_reg2hw_ie0_mreg_t; + + typedef struct packed { + logic [1:0] q; + } rv_plic_reg2hw_threshold0_reg_t; + + typedef struct packed { + logic [7:0] q; + logic qe; + logic re; + } rv_plic_reg2hw_cc0_reg_t; + + typedef struct packed { + logic q; + } rv_plic_reg2hw_msip0_reg_t; + + typedef struct packed { + logic q; + logic qe; + } rv_plic_reg2hw_alert_test_reg_t; + + typedef struct packed { + logic d; + logic de; + } rv_plic_hw2reg_ip_mreg_t; + + typedef struct packed { + logic [7:0] d; + } rv_plic_hw2reg_cc0_reg_t; + + // Register -> HW type + typedef struct packed { + rv_plic_reg2hw_prio_mreg_t [162:0] prio; // [503:178] + rv_plic_reg2hw_ie0_mreg_t [162:0] ie0; // [177:15] + rv_plic_reg2hw_threshold0_reg_t threshold0; // [14:13] + rv_plic_reg2hw_cc0_reg_t cc0; // [12:3] + rv_plic_reg2hw_msip0_reg_t msip0; // [2:2] + rv_plic_reg2hw_alert_test_reg_t alert_test; // [1:0] + } rv_plic_reg2hw_t; + + // HW -> register type + typedef struct packed { + rv_plic_hw2reg_ip_mreg_t [162:0] ip; // [333:8] + rv_plic_hw2reg_cc0_reg_t cc0; // [7:0] + } rv_plic_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_0_OFFSET = 27'h 0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_1_OFFSET = 27'h 4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_2_OFFSET = 27'h 8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_3_OFFSET = 27'h c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_4_OFFSET = 27'h 10; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_5_OFFSET = 27'h 14; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_6_OFFSET = 27'h 18; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_7_OFFSET = 27'h 1c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_8_OFFSET = 27'h 20; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_9_OFFSET = 27'h 24; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_10_OFFSET = 27'h 28; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_11_OFFSET = 27'h 2c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_12_OFFSET = 27'h 30; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_13_OFFSET = 27'h 34; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_14_OFFSET = 27'h 38; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_15_OFFSET = 27'h 3c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_16_OFFSET = 27'h 40; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_17_OFFSET = 27'h 44; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_18_OFFSET = 27'h 48; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_19_OFFSET = 27'h 4c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_20_OFFSET = 27'h 50; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_21_OFFSET = 27'h 54; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_22_OFFSET = 27'h 58; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_23_OFFSET = 27'h 5c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_24_OFFSET = 27'h 60; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_25_OFFSET = 27'h 64; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_26_OFFSET = 27'h 68; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_27_OFFSET = 27'h 6c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_28_OFFSET = 27'h 70; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_29_OFFSET = 27'h 74; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_30_OFFSET = 27'h 78; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_31_OFFSET = 27'h 7c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_32_OFFSET = 27'h 80; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_33_OFFSET = 27'h 84; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_34_OFFSET = 27'h 88; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_35_OFFSET = 27'h 8c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_36_OFFSET = 27'h 90; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_37_OFFSET = 27'h 94; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_38_OFFSET = 27'h 98; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_39_OFFSET = 27'h 9c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_40_OFFSET = 27'h a0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_41_OFFSET = 27'h a4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_42_OFFSET = 27'h a8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_43_OFFSET = 27'h ac; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_44_OFFSET = 27'h b0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_45_OFFSET = 27'h b4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_46_OFFSET = 27'h b8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_47_OFFSET = 27'h bc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_48_OFFSET = 27'h c0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_49_OFFSET = 27'h c4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_50_OFFSET = 27'h c8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_51_OFFSET = 27'h cc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_52_OFFSET = 27'h d0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_53_OFFSET = 27'h d4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_54_OFFSET = 27'h d8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_55_OFFSET = 27'h dc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_56_OFFSET = 27'h e0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_57_OFFSET = 27'h e4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_58_OFFSET = 27'h e8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_59_OFFSET = 27'h ec; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_60_OFFSET = 27'h f0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_61_OFFSET = 27'h f4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_62_OFFSET = 27'h f8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_63_OFFSET = 27'h fc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_64_OFFSET = 27'h 100; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_65_OFFSET = 27'h 104; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_66_OFFSET = 27'h 108; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_67_OFFSET = 27'h 10c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_68_OFFSET = 27'h 110; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_69_OFFSET = 27'h 114; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_70_OFFSET = 27'h 118; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_71_OFFSET = 27'h 11c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_72_OFFSET = 27'h 120; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_73_OFFSET = 27'h 124; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_74_OFFSET = 27'h 128; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_75_OFFSET = 27'h 12c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_76_OFFSET = 27'h 130; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_77_OFFSET = 27'h 134; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_78_OFFSET = 27'h 138; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_79_OFFSET = 27'h 13c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_80_OFFSET = 27'h 140; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_81_OFFSET = 27'h 144; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_82_OFFSET = 27'h 148; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_83_OFFSET = 27'h 14c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_84_OFFSET = 27'h 150; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_85_OFFSET = 27'h 154; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_86_OFFSET = 27'h 158; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_87_OFFSET = 27'h 15c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_88_OFFSET = 27'h 160; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_89_OFFSET = 27'h 164; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_90_OFFSET = 27'h 168; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_91_OFFSET = 27'h 16c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_92_OFFSET = 27'h 170; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_93_OFFSET = 27'h 174; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_94_OFFSET = 27'h 178; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_95_OFFSET = 27'h 17c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_96_OFFSET = 27'h 180; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_97_OFFSET = 27'h 184; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_98_OFFSET = 27'h 188; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_99_OFFSET = 27'h 18c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_100_OFFSET = 27'h 190; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_101_OFFSET = 27'h 194; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_102_OFFSET = 27'h 198; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_103_OFFSET = 27'h 19c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_104_OFFSET = 27'h 1a0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_105_OFFSET = 27'h 1a4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_106_OFFSET = 27'h 1a8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_107_OFFSET = 27'h 1ac; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_108_OFFSET = 27'h 1b0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_109_OFFSET = 27'h 1b4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_110_OFFSET = 27'h 1b8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_111_OFFSET = 27'h 1bc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_112_OFFSET = 27'h 1c0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_113_OFFSET = 27'h 1c4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_114_OFFSET = 27'h 1c8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_115_OFFSET = 27'h 1cc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_116_OFFSET = 27'h 1d0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_117_OFFSET = 27'h 1d4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_118_OFFSET = 27'h 1d8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_119_OFFSET = 27'h 1dc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_120_OFFSET = 27'h 1e0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_121_OFFSET = 27'h 1e4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_122_OFFSET = 27'h 1e8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_123_OFFSET = 27'h 1ec; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_124_OFFSET = 27'h 1f0; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_125_OFFSET = 27'h 1f4; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_126_OFFSET = 27'h 1f8; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_127_OFFSET = 27'h 1fc; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_128_OFFSET = 27'h 200; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_129_OFFSET = 27'h 204; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_130_OFFSET = 27'h 208; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_131_OFFSET = 27'h 20c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_132_OFFSET = 27'h 210; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_133_OFFSET = 27'h 214; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_134_OFFSET = 27'h 218; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_135_OFFSET = 27'h 21c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_136_OFFSET = 27'h 220; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_137_OFFSET = 27'h 224; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_138_OFFSET = 27'h 228; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_139_OFFSET = 27'h 22c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_140_OFFSET = 27'h 230; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_141_OFFSET = 27'h 234; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_142_OFFSET = 27'h 238; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_143_OFFSET = 27'h 23c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_144_OFFSET = 27'h 240; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_145_OFFSET = 27'h 244; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_146_OFFSET = 27'h 248; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_147_OFFSET = 27'h 24c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_148_OFFSET = 27'h 250; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_149_OFFSET = 27'h 254; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_150_OFFSET = 27'h 258; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_151_OFFSET = 27'h 25c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_152_OFFSET = 27'h 260; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_153_OFFSET = 27'h 264; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_154_OFFSET = 27'h 268; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_155_OFFSET = 27'h 26c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_156_OFFSET = 27'h 270; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_157_OFFSET = 27'h 274; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_158_OFFSET = 27'h 278; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_159_OFFSET = 27'h 27c; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_160_OFFSET = 27'h 280; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_161_OFFSET = 27'h 284; + parameter logic [BlockAw-1:0] RV_PLIC_PRIO_162_OFFSET = 27'h 288; + parameter logic [BlockAw-1:0] RV_PLIC_IP_0_OFFSET = 27'h 1000; + parameter logic [BlockAw-1:0] RV_PLIC_IP_1_OFFSET = 27'h 1004; + parameter logic [BlockAw-1:0] RV_PLIC_IP_2_OFFSET = 27'h 1008; + parameter logic [BlockAw-1:0] RV_PLIC_IP_3_OFFSET = 27'h 100c; + parameter logic [BlockAw-1:0] RV_PLIC_IP_4_OFFSET = 27'h 1010; + parameter logic [BlockAw-1:0] RV_PLIC_IP_5_OFFSET = 27'h 1014; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_0_OFFSET = 27'h 2000; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_1_OFFSET = 27'h 2004; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_2_OFFSET = 27'h 2008; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_3_OFFSET = 27'h 200c; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_4_OFFSET = 27'h 2010; + parameter logic [BlockAw-1:0] RV_PLIC_IE0_5_OFFSET = 27'h 2014; + parameter logic [BlockAw-1:0] RV_PLIC_THRESHOLD0_OFFSET = 27'h 200000; + parameter logic [BlockAw-1:0] RV_PLIC_CC0_OFFSET = 27'h 200004; + parameter logic [BlockAw-1:0] RV_PLIC_MSIP0_OFFSET = 27'h 4000000; + parameter logic [BlockAw-1:0] RV_PLIC_ALERT_TEST_OFFSET = 27'h 4004000; + + // Reset values for hwext registers and their fields + parameter logic [7:0] RV_PLIC_CC0_RESVAL = 8'h 0; + parameter logic [0:0] RV_PLIC_ALERT_TEST_RESVAL = 1'h 0; + + // Register index + typedef enum int { + RV_PLIC_PRIO_0, + RV_PLIC_PRIO_1, + RV_PLIC_PRIO_2, + RV_PLIC_PRIO_3, + RV_PLIC_PRIO_4, + RV_PLIC_PRIO_5, + RV_PLIC_PRIO_6, + RV_PLIC_PRIO_7, + RV_PLIC_PRIO_8, + RV_PLIC_PRIO_9, + RV_PLIC_PRIO_10, + RV_PLIC_PRIO_11, + RV_PLIC_PRIO_12, + RV_PLIC_PRIO_13, + RV_PLIC_PRIO_14, + RV_PLIC_PRIO_15, + RV_PLIC_PRIO_16, + RV_PLIC_PRIO_17, + RV_PLIC_PRIO_18, + RV_PLIC_PRIO_19, + RV_PLIC_PRIO_20, + RV_PLIC_PRIO_21, + RV_PLIC_PRIO_22, + RV_PLIC_PRIO_23, + RV_PLIC_PRIO_24, + RV_PLIC_PRIO_25, + RV_PLIC_PRIO_26, + RV_PLIC_PRIO_27, + RV_PLIC_PRIO_28, + RV_PLIC_PRIO_29, + RV_PLIC_PRIO_30, + RV_PLIC_PRIO_31, + RV_PLIC_PRIO_32, + RV_PLIC_PRIO_33, + RV_PLIC_PRIO_34, + RV_PLIC_PRIO_35, + RV_PLIC_PRIO_36, + RV_PLIC_PRIO_37, + RV_PLIC_PRIO_38, + RV_PLIC_PRIO_39, + RV_PLIC_PRIO_40, + RV_PLIC_PRIO_41, + RV_PLIC_PRIO_42, + RV_PLIC_PRIO_43, + RV_PLIC_PRIO_44, + RV_PLIC_PRIO_45, + RV_PLIC_PRIO_46, + RV_PLIC_PRIO_47, + RV_PLIC_PRIO_48, + RV_PLIC_PRIO_49, + RV_PLIC_PRIO_50, + RV_PLIC_PRIO_51, + RV_PLIC_PRIO_52, + RV_PLIC_PRIO_53, + RV_PLIC_PRIO_54, + RV_PLIC_PRIO_55, + RV_PLIC_PRIO_56, + RV_PLIC_PRIO_57, + RV_PLIC_PRIO_58, + RV_PLIC_PRIO_59, + RV_PLIC_PRIO_60, + RV_PLIC_PRIO_61, + RV_PLIC_PRIO_62, + RV_PLIC_PRIO_63, + RV_PLIC_PRIO_64, + RV_PLIC_PRIO_65, + RV_PLIC_PRIO_66, + RV_PLIC_PRIO_67, + RV_PLIC_PRIO_68, + RV_PLIC_PRIO_69, + RV_PLIC_PRIO_70, + RV_PLIC_PRIO_71, + RV_PLIC_PRIO_72, + RV_PLIC_PRIO_73, + RV_PLIC_PRIO_74, + RV_PLIC_PRIO_75, + RV_PLIC_PRIO_76, + RV_PLIC_PRIO_77, + RV_PLIC_PRIO_78, + RV_PLIC_PRIO_79, + RV_PLIC_PRIO_80, + RV_PLIC_PRIO_81, + RV_PLIC_PRIO_82, + RV_PLIC_PRIO_83, + RV_PLIC_PRIO_84, + RV_PLIC_PRIO_85, + RV_PLIC_PRIO_86, + RV_PLIC_PRIO_87, + RV_PLIC_PRIO_88, + RV_PLIC_PRIO_89, + RV_PLIC_PRIO_90, + RV_PLIC_PRIO_91, + RV_PLIC_PRIO_92, + RV_PLIC_PRIO_93, + RV_PLIC_PRIO_94, + RV_PLIC_PRIO_95, + RV_PLIC_PRIO_96, + RV_PLIC_PRIO_97, + RV_PLIC_PRIO_98, + RV_PLIC_PRIO_99, + RV_PLIC_PRIO_100, + RV_PLIC_PRIO_101, + RV_PLIC_PRIO_102, + RV_PLIC_PRIO_103, + RV_PLIC_PRIO_104, + RV_PLIC_PRIO_105, + RV_PLIC_PRIO_106, + RV_PLIC_PRIO_107, + RV_PLIC_PRIO_108, + RV_PLIC_PRIO_109, + RV_PLIC_PRIO_110, + RV_PLIC_PRIO_111, + RV_PLIC_PRIO_112, + RV_PLIC_PRIO_113, + RV_PLIC_PRIO_114, + RV_PLIC_PRIO_115, + RV_PLIC_PRIO_116, + RV_PLIC_PRIO_117, + RV_PLIC_PRIO_118, + RV_PLIC_PRIO_119, + RV_PLIC_PRIO_120, + RV_PLIC_PRIO_121, + RV_PLIC_PRIO_122, + RV_PLIC_PRIO_123, + RV_PLIC_PRIO_124, + RV_PLIC_PRIO_125, + RV_PLIC_PRIO_126, + RV_PLIC_PRIO_127, + RV_PLIC_PRIO_128, + RV_PLIC_PRIO_129, + RV_PLIC_PRIO_130, + RV_PLIC_PRIO_131, + RV_PLIC_PRIO_132, + RV_PLIC_PRIO_133, + RV_PLIC_PRIO_134, + RV_PLIC_PRIO_135, + RV_PLIC_PRIO_136, + RV_PLIC_PRIO_137, + RV_PLIC_PRIO_138, + RV_PLIC_PRIO_139, + RV_PLIC_PRIO_140, + RV_PLIC_PRIO_141, + RV_PLIC_PRIO_142, + RV_PLIC_PRIO_143, + RV_PLIC_PRIO_144, + RV_PLIC_PRIO_145, + RV_PLIC_PRIO_146, + RV_PLIC_PRIO_147, + RV_PLIC_PRIO_148, + RV_PLIC_PRIO_149, + RV_PLIC_PRIO_150, + RV_PLIC_PRIO_151, + RV_PLIC_PRIO_152, + RV_PLIC_PRIO_153, + RV_PLIC_PRIO_154, + RV_PLIC_PRIO_155, + RV_PLIC_PRIO_156, + RV_PLIC_PRIO_157, + RV_PLIC_PRIO_158, + RV_PLIC_PRIO_159, + RV_PLIC_PRIO_160, + RV_PLIC_PRIO_161, + RV_PLIC_PRIO_162, + RV_PLIC_IP_0, + RV_PLIC_IP_1, + RV_PLIC_IP_2, + RV_PLIC_IP_3, + RV_PLIC_IP_4, + RV_PLIC_IP_5, + RV_PLIC_IE0_0, + RV_PLIC_IE0_1, + RV_PLIC_IE0_2, + RV_PLIC_IE0_3, + RV_PLIC_IE0_4, + RV_PLIC_IE0_5, + RV_PLIC_THRESHOLD0, + RV_PLIC_CC0, + RV_PLIC_MSIP0, + RV_PLIC_ALERT_TEST + } rv_plic_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] RV_PLIC_PERMIT [179] = '{ + 4'b 0001, // index[ 0] RV_PLIC_PRIO_0 + 4'b 0001, // index[ 1] RV_PLIC_PRIO_1 + 4'b 0001, // index[ 2] RV_PLIC_PRIO_2 + 4'b 0001, // index[ 3] RV_PLIC_PRIO_3 + 4'b 0001, // index[ 4] RV_PLIC_PRIO_4 + 4'b 0001, // index[ 5] RV_PLIC_PRIO_5 + 4'b 0001, // index[ 6] RV_PLIC_PRIO_6 + 4'b 0001, // index[ 7] RV_PLIC_PRIO_7 + 4'b 0001, // index[ 8] RV_PLIC_PRIO_8 + 4'b 0001, // index[ 9] RV_PLIC_PRIO_9 + 4'b 0001, // index[ 10] RV_PLIC_PRIO_10 + 4'b 0001, // index[ 11] RV_PLIC_PRIO_11 + 4'b 0001, // index[ 12] RV_PLIC_PRIO_12 + 4'b 0001, // index[ 13] RV_PLIC_PRIO_13 + 4'b 0001, // index[ 14] RV_PLIC_PRIO_14 + 4'b 0001, // index[ 15] RV_PLIC_PRIO_15 + 4'b 0001, // index[ 16] RV_PLIC_PRIO_16 + 4'b 0001, // index[ 17] RV_PLIC_PRIO_17 + 4'b 0001, // index[ 18] RV_PLIC_PRIO_18 + 4'b 0001, // index[ 19] RV_PLIC_PRIO_19 + 4'b 0001, // index[ 20] RV_PLIC_PRIO_20 + 4'b 0001, // index[ 21] RV_PLIC_PRIO_21 + 4'b 0001, // index[ 22] RV_PLIC_PRIO_22 + 4'b 0001, // index[ 23] RV_PLIC_PRIO_23 + 4'b 0001, // index[ 24] RV_PLIC_PRIO_24 + 4'b 0001, // index[ 25] RV_PLIC_PRIO_25 + 4'b 0001, // index[ 26] RV_PLIC_PRIO_26 + 4'b 0001, // index[ 27] RV_PLIC_PRIO_27 + 4'b 0001, // index[ 28] RV_PLIC_PRIO_28 + 4'b 0001, // index[ 29] RV_PLIC_PRIO_29 + 4'b 0001, // index[ 30] RV_PLIC_PRIO_30 + 4'b 0001, // index[ 31] RV_PLIC_PRIO_31 + 4'b 0001, // index[ 32] RV_PLIC_PRIO_32 + 4'b 0001, // index[ 33] RV_PLIC_PRIO_33 + 4'b 0001, // index[ 34] RV_PLIC_PRIO_34 + 4'b 0001, // index[ 35] RV_PLIC_PRIO_35 + 4'b 0001, // index[ 36] RV_PLIC_PRIO_36 + 4'b 0001, // index[ 37] RV_PLIC_PRIO_37 + 4'b 0001, // index[ 38] RV_PLIC_PRIO_38 + 4'b 0001, // index[ 39] RV_PLIC_PRIO_39 + 4'b 0001, // index[ 40] RV_PLIC_PRIO_40 + 4'b 0001, // index[ 41] RV_PLIC_PRIO_41 + 4'b 0001, // index[ 42] RV_PLIC_PRIO_42 + 4'b 0001, // index[ 43] RV_PLIC_PRIO_43 + 4'b 0001, // index[ 44] RV_PLIC_PRIO_44 + 4'b 0001, // index[ 45] RV_PLIC_PRIO_45 + 4'b 0001, // index[ 46] RV_PLIC_PRIO_46 + 4'b 0001, // index[ 47] RV_PLIC_PRIO_47 + 4'b 0001, // index[ 48] RV_PLIC_PRIO_48 + 4'b 0001, // index[ 49] RV_PLIC_PRIO_49 + 4'b 0001, // index[ 50] RV_PLIC_PRIO_50 + 4'b 0001, // index[ 51] RV_PLIC_PRIO_51 + 4'b 0001, // index[ 52] RV_PLIC_PRIO_52 + 4'b 0001, // index[ 53] RV_PLIC_PRIO_53 + 4'b 0001, // index[ 54] RV_PLIC_PRIO_54 + 4'b 0001, // index[ 55] RV_PLIC_PRIO_55 + 4'b 0001, // index[ 56] RV_PLIC_PRIO_56 + 4'b 0001, // index[ 57] RV_PLIC_PRIO_57 + 4'b 0001, // index[ 58] RV_PLIC_PRIO_58 + 4'b 0001, // index[ 59] RV_PLIC_PRIO_59 + 4'b 0001, // index[ 60] RV_PLIC_PRIO_60 + 4'b 0001, // index[ 61] RV_PLIC_PRIO_61 + 4'b 0001, // index[ 62] RV_PLIC_PRIO_62 + 4'b 0001, // index[ 63] RV_PLIC_PRIO_63 + 4'b 0001, // index[ 64] RV_PLIC_PRIO_64 + 4'b 0001, // index[ 65] RV_PLIC_PRIO_65 + 4'b 0001, // index[ 66] RV_PLIC_PRIO_66 + 4'b 0001, // index[ 67] RV_PLIC_PRIO_67 + 4'b 0001, // index[ 68] RV_PLIC_PRIO_68 + 4'b 0001, // index[ 69] RV_PLIC_PRIO_69 + 4'b 0001, // index[ 70] RV_PLIC_PRIO_70 + 4'b 0001, // index[ 71] RV_PLIC_PRIO_71 + 4'b 0001, // index[ 72] RV_PLIC_PRIO_72 + 4'b 0001, // index[ 73] RV_PLIC_PRIO_73 + 4'b 0001, // index[ 74] RV_PLIC_PRIO_74 + 4'b 0001, // index[ 75] RV_PLIC_PRIO_75 + 4'b 0001, // index[ 76] RV_PLIC_PRIO_76 + 4'b 0001, // index[ 77] RV_PLIC_PRIO_77 + 4'b 0001, // index[ 78] RV_PLIC_PRIO_78 + 4'b 0001, // index[ 79] RV_PLIC_PRIO_79 + 4'b 0001, // index[ 80] RV_PLIC_PRIO_80 + 4'b 0001, // index[ 81] RV_PLIC_PRIO_81 + 4'b 0001, // index[ 82] RV_PLIC_PRIO_82 + 4'b 0001, // index[ 83] RV_PLIC_PRIO_83 + 4'b 0001, // index[ 84] RV_PLIC_PRIO_84 + 4'b 0001, // index[ 85] RV_PLIC_PRIO_85 + 4'b 0001, // index[ 86] RV_PLIC_PRIO_86 + 4'b 0001, // index[ 87] RV_PLIC_PRIO_87 + 4'b 0001, // index[ 88] RV_PLIC_PRIO_88 + 4'b 0001, // index[ 89] RV_PLIC_PRIO_89 + 4'b 0001, // index[ 90] RV_PLIC_PRIO_90 + 4'b 0001, // index[ 91] RV_PLIC_PRIO_91 + 4'b 0001, // index[ 92] RV_PLIC_PRIO_92 + 4'b 0001, // index[ 93] RV_PLIC_PRIO_93 + 4'b 0001, // index[ 94] RV_PLIC_PRIO_94 + 4'b 0001, // index[ 95] RV_PLIC_PRIO_95 + 4'b 0001, // index[ 96] RV_PLIC_PRIO_96 + 4'b 0001, // index[ 97] RV_PLIC_PRIO_97 + 4'b 0001, // index[ 98] RV_PLIC_PRIO_98 + 4'b 0001, // index[ 99] RV_PLIC_PRIO_99 + 4'b 0001, // index[100] RV_PLIC_PRIO_100 + 4'b 0001, // index[101] RV_PLIC_PRIO_101 + 4'b 0001, // index[102] RV_PLIC_PRIO_102 + 4'b 0001, // index[103] RV_PLIC_PRIO_103 + 4'b 0001, // index[104] RV_PLIC_PRIO_104 + 4'b 0001, // index[105] RV_PLIC_PRIO_105 + 4'b 0001, // index[106] RV_PLIC_PRIO_106 + 4'b 0001, // index[107] RV_PLIC_PRIO_107 + 4'b 0001, // index[108] RV_PLIC_PRIO_108 + 4'b 0001, // index[109] RV_PLIC_PRIO_109 + 4'b 0001, // index[110] RV_PLIC_PRIO_110 + 4'b 0001, // index[111] RV_PLIC_PRIO_111 + 4'b 0001, // index[112] RV_PLIC_PRIO_112 + 4'b 0001, // index[113] RV_PLIC_PRIO_113 + 4'b 0001, // index[114] RV_PLIC_PRIO_114 + 4'b 0001, // index[115] RV_PLIC_PRIO_115 + 4'b 0001, // index[116] RV_PLIC_PRIO_116 + 4'b 0001, // index[117] RV_PLIC_PRIO_117 + 4'b 0001, // index[118] RV_PLIC_PRIO_118 + 4'b 0001, // index[119] RV_PLIC_PRIO_119 + 4'b 0001, // index[120] RV_PLIC_PRIO_120 + 4'b 0001, // index[121] RV_PLIC_PRIO_121 + 4'b 0001, // index[122] RV_PLIC_PRIO_122 + 4'b 0001, // index[123] RV_PLIC_PRIO_123 + 4'b 0001, // index[124] RV_PLIC_PRIO_124 + 4'b 0001, // index[125] RV_PLIC_PRIO_125 + 4'b 0001, // index[126] RV_PLIC_PRIO_126 + 4'b 0001, // index[127] RV_PLIC_PRIO_127 + 4'b 0001, // index[128] RV_PLIC_PRIO_128 + 4'b 0001, // index[129] RV_PLIC_PRIO_129 + 4'b 0001, // index[130] RV_PLIC_PRIO_130 + 4'b 0001, // index[131] RV_PLIC_PRIO_131 + 4'b 0001, // index[132] RV_PLIC_PRIO_132 + 4'b 0001, // index[133] RV_PLIC_PRIO_133 + 4'b 0001, // index[134] RV_PLIC_PRIO_134 + 4'b 0001, // index[135] RV_PLIC_PRIO_135 + 4'b 0001, // index[136] RV_PLIC_PRIO_136 + 4'b 0001, // index[137] RV_PLIC_PRIO_137 + 4'b 0001, // index[138] RV_PLIC_PRIO_138 + 4'b 0001, // index[139] RV_PLIC_PRIO_139 + 4'b 0001, // index[140] RV_PLIC_PRIO_140 + 4'b 0001, // index[141] RV_PLIC_PRIO_141 + 4'b 0001, // index[142] RV_PLIC_PRIO_142 + 4'b 0001, // index[143] RV_PLIC_PRIO_143 + 4'b 0001, // index[144] RV_PLIC_PRIO_144 + 4'b 0001, // index[145] RV_PLIC_PRIO_145 + 4'b 0001, // index[146] RV_PLIC_PRIO_146 + 4'b 0001, // index[147] RV_PLIC_PRIO_147 + 4'b 0001, // index[148] RV_PLIC_PRIO_148 + 4'b 0001, // index[149] RV_PLIC_PRIO_149 + 4'b 0001, // index[150] RV_PLIC_PRIO_150 + 4'b 0001, // index[151] RV_PLIC_PRIO_151 + 4'b 0001, // index[152] RV_PLIC_PRIO_152 + 4'b 0001, // index[153] RV_PLIC_PRIO_153 + 4'b 0001, // index[154] RV_PLIC_PRIO_154 + 4'b 0001, // index[155] RV_PLIC_PRIO_155 + 4'b 0001, // index[156] RV_PLIC_PRIO_156 + 4'b 0001, // index[157] RV_PLIC_PRIO_157 + 4'b 0001, // index[158] RV_PLIC_PRIO_158 + 4'b 0001, // index[159] RV_PLIC_PRIO_159 + 4'b 0001, // index[160] RV_PLIC_PRIO_160 + 4'b 0001, // index[161] RV_PLIC_PRIO_161 + 4'b 0001, // index[162] RV_PLIC_PRIO_162 + 4'b 1111, // index[163] RV_PLIC_IP_0 + 4'b 1111, // index[164] RV_PLIC_IP_1 + 4'b 1111, // index[165] RV_PLIC_IP_2 + 4'b 1111, // index[166] RV_PLIC_IP_3 + 4'b 1111, // index[167] RV_PLIC_IP_4 + 4'b 0001, // index[168] RV_PLIC_IP_5 + 4'b 1111, // index[169] RV_PLIC_IE0_0 + 4'b 1111, // index[170] RV_PLIC_IE0_1 + 4'b 1111, // index[171] RV_PLIC_IE0_2 + 4'b 1111, // index[172] RV_PLIC_IE0_3 + 4'b 1111, // index[173] RV_PLIC_IE0_4 + 4'b 0001, // index[174] RV_PLIC_IE0_5 + 4'b 0001, // index[175] RV_PLIC_THRESHOLD0 + 4'b 0001, // index[176] RV_PLIC_CC0 + 4'b 0001, // index[177] RV_PLIC_MSIP0 + 4'b 0001 // index[178] RV_PLIC_ALERT_TEST + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv new file mode 100644 index 00000000000..055df8a5981 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_reg_top.sv @@ -0,0 +1,17240 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + +`include "prim_assert.sv" + +module rv_plic_reg_top ( + input clk_i, + input rst_ni, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // To HW + output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write + input rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg, // Read + + // Integrity check errors + output logic intg_err_o +); + + import rv_plic_reg_pkg::* ; + + localparam int AW = 27; + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + logic reg_busy; + + tlul_pkg::tl_h2d_t tl_reg_h2d; + tlul_pkg::tl_d2h_t tl_reg_d2h; + + + // incoming payload check + logic intg_err; + tlul_cmd_intg_chk u_chk ( + .tl_i(tl_i), + .err_o(intg_err) + ); + + // also check for spurious write enables + logic reg_we_err; + logic [178:0] reg_we_check; + prim_reg_we_check #( + .OneHotWidth(179) + ) u_prim_reg_we_check ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .oh_i (reg_we_check), + .en_i (reg_we && !addrmiss), + .err_o (reg_we_err) + ); + + logic err_q; + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + err_q <= '0; + end else if (intg_err || reg_we_err) begin + err_q <= 1'b1; + end + end + + // integrity error output is permanent and should be used for alert generation + // register errors are transactional + assign intg_err_o = err_q | intg_err | reg_we_err; + + // outgoing integrity generation + tlul_pkg::tl_d2h_t tl_o_pre; + tlul_rsp_intg_gen #( + .EnableRspIntgGen(1), + .EnableDataIntgGen(1) + ) u_rsp_intg_gen ( + .tl_i(tl_o_pre), + .tl_o(tl_o) + ); + + assign tl_reg_h2d = tl_i; + assign tl_o_pre = tl_reg_d2h; + + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW), + .EnableDataIntgGen(0) + ) u_reg_if ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + .tl_i (tl_reg_h2d), + .tl_o (tl_reg_d2h), + + .en_ifetch_i(prim_mubi_pkg::MuBi4False), + .intg_error_o(), + + .we_o (reg_we), + .re_o (reg_re), + .addr_o (reg_addr), + .wdata_o (reg_wdata), + .be_o (reg_be), + .busy_i (reg_busy), + .rdata_i (reg_rdata), + .error_i (reg_error) + ); + + // cdc oversampling signals + + assign reg_rdata = reg_rdata_next ; + assign reg_error = addrmiss | wr_err | intg_err; + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic prio_0_we; + logic [1:0] prio_0_qs; + logic [1:0] prio_0_wd; + logic prio_1_we; + logic [1:0] prio_1_qs; + logic [1:0] prio_1_wd; + logic prio_2_we; + logic [1:0] prio_2_qs; + logic [1:0] prio_2_wd; + logic prio_3_we; + logic [1:0] prio_3_qs; + logic [1:0] prio_3_wd; + logic prio_4_we; + logic [1:0] prio_4_qs; + logic [1:0] prio_4_wd; + logic prio_5_we; + logic [1:0] prio_5_qs; + logic [1:0] prio_5_wd; + logic prio_6_we; + logic [1:0] prio_6_qs; + logic [1:0] prio_6_wd; + logic prio_7_we; + logic [1:0] prio_7_qs; + logic [1:0] prio_7_wd; + logic prio_8_we; + logic [1:0] prio_8_qs; + logic [1:0] prio_8_wd; + logic prio_9_we; + logic [1:0] prio_9_qs; + logic [1:0] prio_9_wd; + logic prio_10_we; + logic [1:0] prio_10_qs; + logic [1:0] prio_10_wd; + logic prio_11_we; + logic [1:0] prio_11_qs; + logic [1:0] prio_11_wd; + logic prio_12_we; + logic [1:0] prio_12_qs; + logic [1:0] prio_12_wd; + logic prio_13_we; + logic [1:0] prio_13_qs; + logic [1:0] prio_13_wd; + logic prio_14_we; + logic [1:0] prio_14_qs; + logic [1:0] prio_14_wd; + logic prio_15_we; + logic [1:0] prio_15_qs; + logic [1:0] prio_15_wd; + logic prio_16_we; + logic [1:0] prio_16_qs; + logic [1:0] prio_16_wd; + logic prio_17_we; + logic [1:0] prio_17_qs; + logic [1:0] prio_17_wd; + logic prio_18_we; + logic [1:0] prio_18_qs; + logic [1:0] prio_18_wd; + logic prio_19_we; + logic [1:0] prio_19_qs; + logic [1:0] prio_19_wd; + logic prio_20_we; + logic [1:0] prio_20_qs; + logic [1:0] prio_20_wd; + logic prio_21_we; + logic [1:0] prio_21_qs; + logic [1:0] prio_21_wd; + logic prio_22_we; + logic [1:0] prio_22_qs; + logic [1:0] prio_22_wd; + logic prio_23_we; + logic [1:0] prio_23_qs; + logic [1:0] prio_23_wd; + logic prio_24_we; + logic [1:0] prio_24_qs; + logic [1:0] prio_24_wd; + logic prio_25_we; + logic [1:0] prio_25_qs; + logic [1:0] prio_25_wd; + logic prio_26_we; + logic [1:0] prio_26_qs; + logic [1:0] prio_26_wd; + logic prio_27_we; + logic [1:0] prio_27_qs; + logic [1:0] prio_27_wd; + logic prio_28_we; + logic [1:0] prio_28_qs; + logic [1:0] prio_28_wd; + logic prio_29_we; + logic [1:0] prio_29_qs; + logic [1:0] prio_29_wd; + logic prio_30_we; + logic [1:0] prio_30_qs; + logic [1:0] prio_30_wd; + logic prio_31_we; + logic [1:0] prio_31_qs; + logic [1:0] prio_31_wd; + logic prio_32_we; + logic [1:0] prio_32_qs; + logic [1:0] prio_32_wd; + logic prio_33_we; + logic [1:0] prio_33_qs; + logic [1:0] prio_33_wd; + logic prio_34_we; + logic [1:0] prio_34_qs; + logic [1:0] prio_34_wd; + logic prio_35_we; + logic [1:0] prio_35_qs; + logic [1:0] prio_35_wd; + logic prio_36_we; + logic [1:0] prio_36_qs; + logic [1:0] prio_36_wd; + logic prio_37_we; + logic [1:0] prio_37_qs; + logic [1:0] prio_37_wd; + logic prio_38_we; + logic [1:0] prio_38_qs; + logic [1:0] prio_38_wd; + logic prio_39_we; + logic [1:0] prio_39_qs; + logic [1:0] prio_39_wd; + logic prio_40_we; + logic [1:0] prio_40_qs; + logic [1:0] prio_40_wd; + logic prio_41_we; + logic [1:0] prio_41_qs; + logic [1:0] prio_41_wd; + logic prio_42_we; + logic [1:0] prio_42_qs; + logic [1:0] prio_42_wd; + logic prio_43_we; + logic [1:0] prio_43_qs; + logic [1:0] prio_43_wd; + logic prio_44_we; + logic [1:0] prio_44_qs; + logic [1:0] prio_44_wd; + logic prio_45_we; + logic [1:0] prio_45_qs; + logic [1:0] prio_45_wd; + logic prio_46_we; + logic [1:0] prio_46_qs; + logic [1:0] prio_46_wd; + logic prio_47_we; + logic [1:0] prio_47_qs; + logic [1:0] prio_47_wd; + logic prio_48_we; + logic [1:0] prio_48_qs; + logic [1:0] prio_48_wd; + logic prio_49_we; + logic [1:0] prio_49_qs; + logic [1:0] prio_49_wd; + logic prio_50_we; + logic [1:0] prio_50_qs; + logic [1:0] prio_50_wd; + logic prio_51_we; + logic [1:0] prio_51_qs; + logic [1:0] prio_51_wd; + logic prio_52_we; + logic [1:0] prio_52_qs; + logic [1:0] prio_52_wd; + logic prio_53_we; + logic [1:0] prio_53_qs; + logic [1:0] prio_53_wd; + logic prio_54_we; + logic [1:0] prio_54_qs; + logic [1:0] prio_54_wd; + logic prio_55_we; + logic [1:0] prio_55_qs; + logic [1:0] prio_55_wd; + logic prio_56_we; + logic [1:0] prio_56_qs; + logic [1:0] prio_56_wd; + logic prio_57_we; + logic [1:0] prio_57_qs; + logic [1:0] prio_57_wd; + logic prio_58_we; + logic [1:0] prio_58_qs; + logic [1:0] prio_58_wd; + logic prio_59_we; + logic [1:0] prio_59_qs; + logic [1:0] prio_59_wd; + logic prio_60_we; + logic [1:0] prio_60_qs; + logic [1:0] prio_60_wd; + logic prio_61_we; + logic [1:0] prio_61_qs; + logic [1:0] prio_61_wd; + logic prio_62_we; + logic [1:0] prio_62_qs; + logic [1:0] prio_62_wd; + logic prio_63_we; + logic [1:0] prio_63_qs; + logic [1:0] prio_63_wd; + logic prio_64_we; + logic [1:0] prio_64_qs; + logic [1:0] prio_64_wd; + logic prio_65_we; + logic [1:0] prio_65_qs; + logic [1:0] prio_65_wd; + logic prio_66_we; + logic [1:0] prio_66_qs; + logic [1:0] prio_66_wd; + logic prio_67_we; + logic [1:0] prio_67_qs; + logic [1:0] prio_67_wd; + logic prio_68_we; + logic [1:0] prio_68_qs; + logic [1:0] prio_68_wd; + logic prio_69_we; + logic [1:0] prio_69_qs; + logic [1:0] prio_69_wd; + logic prio_70_we; + logic [1:0] prio_70_qs; + logic [1:0] prio_70_wd; + logic prio_71_we; + logic [1:0] prio_71_qs; + logic [1:0] prio_71_wd; + logic prio_72_we; + logic [1:0] prio_72_qs; + logic [1:0] prio_72_wd; + logic prio_73_we; + logic [1:0] prio_73_qs; + logic [1:0] prio_73_wd; + logic prio_74_we; + logic [1:0] prio_74_qs; + logic [1:0] prio_74_wd; + logic prio_75_we; + logic [1:0] prio_75_qs; + logic [1:0] prio_75_wd; + logic prio_76_we; + logic [1:0] prio_76_qs; + logic [1:0] prio_76_wd; + logic prio_77_we; + logic [1:0] prio_77_qs; + logic [1:0] prio_77_wd; + logic prio_78_we; + logic [1:0] prio_78_qs; + logic [1:0] prio_78_wd; + logic prio_79_we; + logic [1:0] prio_79_qs; + logic [1:0] prio_79_wd; + logic prio_80_we; + logic [1:0] prio_80_qs; + logic [1:0] prio_80_wd; + logic prio_81_we; + logic [1:0] prio_81_qs; + logic [1:0] prio_81_wd; + logic prio_82_we; + logic [1:0] prio_82_qs; + logic [1:0] prio_82_wd; + logic prio_83_we; + logic [1:0] prio_83_qs; + logic [1:0] prio_83_wd; + logic prio_84_we; + logic [1:0] prio_84_qs; + logic [1:0] prio_84_wd; + logic prio_85_we; + logic [1:0] prio_85_qs; + logic [1:0] prio_85_wd; + logic prio_86_we; + logic [1:0] prio_86_qs; + logic [1:0] prio_86_wd; + logic prio_87_we; + logic [1:0] prio_87_qs; + logic [1:0] prio_87_wd; + logic prio_88_we; + logic [1:0] prio_88_qs; + logic [1:0] prio_88_wd; + logic prio_89_we; + logic [1:0] prio_89_qs; + logic [1:0] prio_89_wd; + logic prio_90_we; + logic [1:0] prio_90_qs; + logic [1:0] prio_90_wd; + logic prio_91_we; + logic [1:0] prio_91_qs; + logic [1:0] prio_91_wd; + logic prio_92_we; + logic [1:0] prio_92_qs; + logic [1:0] prio_92_wd; + logic prio_93_we; + logic [1:0] prio_93_qs; + logic [1:0] prio_93_wd; + logic prio_94_we; + logic [1:0] prio_94_qs; + logic [1:0] prio_94_wd; + logic prio_95_we; + logic [1:0] prio_95_qs; + logic [1:0] prio_95_wd; + logic prio_96_we; + logic [1:0] prio_96_qs; + logic [1:0] prio_96_wd; + logic prio_97_we; + logic [1:0] prio_97_qs; + logic [1:0] prio_97_wd; + logic prio_98_we; + logic [1:0] prio_98_qs; + logic [1:0] prio_98_wd; + logic prio_99_we; + logic [1:0] prio_99_qs; + logic [1:0] prio_99_wd; + logic prio_100_we; + logic [1:0] prio_100_qs; + logic [1:0] prio_100_wd; + logic prio_101_we; + logic [1:0] prio_101_qs; + logic [1:0] prio_101_wd; + logic prio_102_we; + logic [1:0] prio_102_qs; + logic [1:0] prio_102_wd; + logic prio_103_we; + logic [1:0] prio_103_qs; + logic [1:0] prio_103_wd; + logic prio_104_we; + logic [1:0] prio_104_qs; + logic [1:0] prio_104_wd; + logic prio_105_we; + logic [1:0] prio_105_qs; + logic [1:0] prio_105_wd; + logic prio_106_we; + logic [1:0] prio_106_qs; + logic [1:0] prio_106_wd; + logic prio_107_we; + logic [1:0] prio_107_qs; + logic [1:0] prio_107_wd; + logic prio_108_we; + logic [1:0] prio_108_qs; + logic [1:0] prio_108_wd; + logic prio_109_we; + logic [1:0] prio_109_qs; + logic [1:0] prio_109_wd; + logic prio_110_we; + logic [1:0] prio_110_qs; + logic [1:0] prio_110_wd; + logic prio_111_we; + logic [1:0] prio_111_qs; + logic [1:0] prio_111_wd; + logic prio_112_we; + logic [1:0] prio_112_qs; + logic [1:0] prio_112_wd; + logic prio_113_we; + logic [1:0] prio_113_qs; + logic [1:0] prio_113_wd; + logic prio_114_we; + logic [1:0] prio_114_qs; + logic [1:0] prio_114_wd; + logic prio_115_we; + logic [1:0] prio_115_qs; + logic [1:0] prio_115_wd; + logic prio_116_we; + logic [1:0] prio_116_qs; + logic [1:0] prio_116_wd; + logic prio_117_we; + logic [1:0] prio_117_qs; + logic [1:0] prio_117_wd; + logic prio_118_we; + logic [1:0] prio_118_qs; + logic [1:0] prio_118_wd; + logic prio_119_we; + logic [1:0] prio_119_qs; + logic [1:0] prio_119_wd; + logic prio_120_we; + logic [1:0] prio_120_qs; + logic [1:0] prio_120_wd; + logic prio_121_we; + logic [1:0] prio_121_qs; + logic [1:0] prio_121_wd; + logic prio_122_we; + logic [1:0] prio_122_qs; + logic [1:0] prio_122_wd; + logic prio_123_we; + logic [1:0] prio_123_qs; + logic [1:0] prio_123_wd; + logic prio_124_we; + logic [1:0] prio_124_qs; + logic [1:0] prio_124_wd; + logic prio_125_we; + logic [1:0] prio_125_qs; + logic [1:0] prio_125_wd; + logic prio_126_we; + logic [1:0] prio_126_qs; + logic [1:0] prio_126_wd; + logic prio_127_we; + logic [1:0] prio_127_qs; + logic [1:0] prio_127_wd; + logic prio_128_we; + logic [1:0] prio_128_qs; + logic [1:0] prio_128_wd; + logic prio_129_we; + logic [1:0] prio_129_qs; + logic [1:0] prio_129_wd; + logic prio_130_we; + logic [1:0] prio_130_qs; + logic [1:0] prio_130_wd; + logic prio_131_we; + logic [1:0] prio_131_qs; + logic [1:0] prio_131_wd; + logic prio_132_we; + logic [1:0] prio_132_qs; + logic [1:0] prio_132_wd; + logic prio_133_we; + logic [1:0] prio_133_qs; + logic [1:0] prio_133_wd; + logic prio_134_we; + logic [1:0] prio_134_qs; + logic [1:0] prio_134_wd; + logic prio_135_we; + logic [1:0] prio_135_qs; + logic [1:0] prio_135_wd; + logic prio_136_we; + logic [1:0] prio_136_qs; + logic [1:0] prio_136_wd; + logic prio_137_we; + logic [1:0] prio_137_qs; + logic [1:0] prio_137_wd; + logic prio_138_we; + logic [1:0] prio_138_qs; + logic [1:0] prio_138_wd; + logic prio_139_we; + logic [1:0] prio_139_qs; + logic [1:0] prio_139_wd; + logic prio_140_we; + logic [1:0] prio_140_qs; + logic [1:0] prio_140_wd; + logic prio_141_we; + logic [1:0] prio_141_qs; + logic [1:0] prio_141_wd; + logic prio_142_we; + logic [1:0] prio_142_qs; + logic [1:0] prio_142_wd; + logic prio_143_we; + logic [1:0] prio_143_qs; + logic [1:0] prio_143_wd; + logic prio_144_we; + logic [1:0] prio_144_qs; + logic [1:0] prio_144_wd; + logic prio_145_we; + logic [1:0] prio_145_qs; + logic [1:0] prio_145_wd; + logic prio_146_we; + logic [1:0] prio_146_qs; + logic [1:0] prio_146_wd; + logic prio_147_we; + logic [1:0] prio_147_qs; + logic [1:0] prio_147_wd; + logic prio_148_we; + logic [1:0] prio_148_qs; + logic [1:0] prio_148_wd; + logic prio_149_we; + logic [1:0] prio_149_qs; + logic [1:0] prio_149_wd; + logic prio_150_we; + logic [1:0] prio_150_qs; + logic [1:0] prio_150_wd; + logic prio_151_we; + logic [1:0] prio_151_qs; + logic [1:0] prio_151_wd; + logic prio_152_we; + logic [1:0] prio_152_qs; + logic [1:0] prio_152_wd; + logic prio_153_we; + logic [1:0] prio_153_qs; + logic [1:0] prio_153_wd; + logic prio_154_we; + logic [1:0] prio_154_qs; + logic [1:0] prio_154_wd; + logic prio_155_we; + logic [1:0] prio_155_qs; + logic [1:0] prio_155_wd; + logic prio_156_we; + logic [1:0] prio_156_qs; + logic [1:0] prio_156_wd; + logic prio_157_we; + logic [1:0] prio_157_qs; + logic [1:0] prio_157_wd; + logic prio_158_we; + logic [1:0] prio_158_qs; + logic [1:0] prio_158_wd; + logic prio_159_we; + logic [1:0] prio_159_qs; + logic [1:0] prio_159_wd; + logic prio_160_we; + logic [1:0] prio_160_qs; + logic [1:0] prio_160_wd; + logic prio_161_we; + logic [1:0] prio_161_qs; + logic [1:0] prio_161_wd; + logic prio_162_we; + logic [1:0] prio_162_qs; + logic [1:0] prio_162_wd; + logic ip_0_p_0_qs; + logic ip_0_p_1_qs; + logic ip_0_p_2_qs; + logic ip_0_p_3_qs; + logic ip_0_p_4_qs; + logic ip_0_p_5_qs; + logic ip_0_p_6_qs; + logic ip_0_p_7_qs; + logic ip_0_p_8_qs; + logic ip_0_p_9_qs; + logic ip_0_p_10_qs; + logic ip_0_p_11_qs; + logic ip_0_p_12_qs; + logic ip_0_p_13_qs; + logic ip_0_p_14_qs; + logic ip_0_p_15_qs; + logic ip_0_p_16_qs; + logic ip_0_p_17_qs; + logic ip_0_p_18_qs; + logic ip_0_p_19_qs; + logic ip_0_p_20_qs; + logic ip_0_p_21_qs; + logic ip_0_p_22_qs; + logic ip_0_p_23_qs; + logic ip_0_p_24_qs; + logic ip_0_p_25_qs; + logic ip_0_p_26_qs; + logic ip_0_p_27_qs; + logic ip_0_p_28_qs; + logic ip_0_p_29_qs; + logic ip_0_p_30_qs; + logic ip_0_p_31_qs; + logic ip_1_p_32_qs; + logic ip_1_p_33_qs; + logic ip_1_p_34_qs; + logic ip_1_p_35_qs; + logic ip_1_p_36_qs; + logic ip_1_p_37_qs; + logic ip_1_p_38_qs; + logic ip_1_p_39_qs; + logic ip_1_p_40_qs; + logic ip_1_p_41_qs; + logic ip_1_p_42_qs; + logic ip_1_p_43_qs; + logic ip_1_p_44_qs; + logic ip_1_p_45_qs; + logic ip_1_p_46_qs; + logic ip_1_p_47_qs; + logic ip_1_p_48_qs; + logic ip_1_p_49_qs; + logic ip_1_p_50_qs; + logic ip_1_p_51_qs; + logic ip_1_p_52_qs; + logic ip_1_p_53_qs; + logic ip_1_p_54_qs; + logic ip_1_p_55_qs; + logic ip_1_p_56_qs; + logic ip_1_p_57_qs; + logic ip_1_p_58_qs; + logic ip_1_p_59_qs; + logic ip_1_p_60_qs; + logic ip_1_p_61_qs; + logic ip_1_p_62_qs; + logic ip_1_p_63_qs; + logic ip_2_p_64_qs; + logic ip_2_p_65_qs; + logic ip_2_p_66_qs; + logic ip_2_p_67_qs; + logic ip_2_p_68_qs; + logic ip_2_p_69_qs; + logic ip_2_p_70_qs; + logic ip_2_p_71_qs; + logic ip_2_p_72_qs; + logic ip_2_p_73_qs; + logic ip_2_p_74_qs; + logic ip_2_p_75_qs; + logic ip_2_p_76_qs; + logic ip_2_p_77_qs; + logic ip_2_p_78_qs; + logic ip_2_p_79_qs; + logic ip_2_p_80_qs; + logic ip_2_p_81_qs; + logic ip_2_p_82_qs; + logic ip_2_p_83_qs; + logic ip_2_p_84_qs; + logic ip_2_p_85_qs; + logic ip_2_p_86_qs; + logic ip_2_p_87_qs; + logic ip_2_p_88_qs; + logic ip_2_p_89_qs; + logic ip_2_p_90_qs; + logic ip_2_p_91_qs; + logic ip_2_p_92_qs; + logic ip_2_p_93_qs; + logic ip_2_p_94_qs; + logic ip_2_p_95_qs; + logic ip_3_p_96_qs; + logic ip_3_p_97_qs; + logic ip_3_p_98_qs; + logic ip_3_p_99_qs; + logic ip_3_p_100_qs; + logic ip_3_p_101_qs; + logic ip_3_p_102_qs; + logic ip_3_p_103_qs; + logic ip_3_p_104_qs; + logic ip_3_p_105_qs; + logic ip_3_p_106_qs; + logic ip_3_p_107_qs; + logic ip_3_p_108_qs; + logic ip_3_p_109_qs; + logic ip_3_p_110_qs; + logic ip_3_p_111_qs; + logic ip_3_p_112_qs; + logic ip_3_p_113_qs; + logic ip_3_p_114_qs; + logic ip_3_p_115_qs; + logic ip_3_p_116_qs; + logic ip_3_p_117_qs; + logic ip_3_p_118_qs; + logic ip_3_p_119_qs; + logic ip_3_p_120_qs; + logic ip_3_p_121_qs; + logic ip_3_p_122_qs; + logic ip_3_p_123_qs; + logic ip_3_p_124_qs; + logic ip_3_p_125_qs; + logic ip_3_p_126_qs; + logic ip_3_p_127_qs; + logic ip_4_p_128_qs; + logic ip_4_p_129_qs; + logic ip_4_p_130_qs; + logic ip_4_p_131_qs; + logic ip_4_p_132_qs; + logic ip_4_p_133_qs; + logic ip_4_p_134_qs; + logic ip_4_p_135_qs; + logic ip_4_p_136_qs; + logic ip_4_p_137_qs; + logic ip_4_p_138_qs; + logic ip_4_p_139_qs; + logic ip_4_p_140_qs; + logic ip_4_p_141_qs; + logic ip_4_p_142_qs; + logic ip_4_p_143_qs; + logic ip_4_p_144_qs; + logic ip_4_p_145_qs; + logic ip_4_p_146_qs; + logic ip_4_p_147_qs; + logic ip_4_p_148_qs; + logic ip_4_p_149_qs; + logic ip_4_p_150_qs; + logic ip_4_p_151_qs; + logic ip_4_p_152_qs; + logic ip_4_p_153_qs; + logic ip_4_p_154_qs; + logic ip_4_p_155_qs; + logic ip_4_p_156_qs; + logic ip_4_p_157_qs; + logic ip_4_p_158_qs; + logic ip_4_p_159_qs; + logic ip_5_p_160_qs; + logic ip_5_p_161_qs; + logic ip_5_p_162_qs; + logic ie0_0_we; + logic ie0_0_e_0_qs; + logic ie0_0_e_0_wd; + logic ie0_0_e_1_qs; + logic ie0_0_e_1_wd; + logic ie0_0_e_2_qs; + logic ie0_0_e_2_wd; + logic ie0_0_e_3_qs; + logic ie0_0_e_3_wd; + logic ie0_0_e_4_qs; + logic ie0_0_e_4_wd; + logic ie0_0_e_5_qs; + logic ie0_0_e_5_wd; + logic ie0_0_e_6_qs; + logic ie0_0_e_6_wd; + logic ie0_0_e_7_qs; + logic ie0_0_e_7_wd; + logic ie0_0_e_8_qs; + logic ie0_0_e_8_wd; + logic ie0_0_e_9_qs; + logic ie0_0_e_9_wd; + logic ie0_0_e_10_qs; + logic ie0_0_e_10_wd; + logic ie0_0_e_11_qs; + logic ie0_0_e_11_wd; + logic ie0_0_e_12_qs; + logic ie0_0_e_12_wd; + logic ie0_0_e_13_qs; + logic ie0_0_e_13_wd; + logic ie0_0_e_14_qs; + logic ie0_0_e_14_wd; + logic ie0_0_e_15_qs; + logic ie0_0_e_15_wd; + logic ie0_0_e_16_qs; + logic ie0_0_e_16_wd; + logic ie0_0_e_17_qs; + logic ie0_0_e_17_wd; + logic ie0_0_e_18_qs; + logic ie0_0_e_18_wd; + logic ie0_0_e_19_qs; + logic ie0_0_e_19_wd; + logic ie0_0_e_20_qs; + logic ie0_0_e_20_wd; + logic ie0_0_e_21_qs; + logic ie0_0_e_21_wd; + logic ie0_0_e_22_qs; + logic ie0_0_e_22_wd; + logic ie0_0_e_23_qs; + logic ie0_0_e_23_wd; + logic ie0_0_e_24_qs; + logic ie0_0_e_24_wd; + logic ie0_0_e_25_qs; + logic ie0_0_e_25_wd; + logic ie0_0_e_26_qs; + logic ie0_0_e_26_wd; + logic ie0_0_e_27_qs; + logic ie0_0_e_27_wd; + logic ie0_0_e_28_qs; + logic ie0_0_e_28_wd; + logic ie0_0_e_29_qs; + logic ie0_0_e_29_wd; + logic ie0_0_e_30_qs; + logic ie0_0_e_30_wd; + logic ie0_0_e_31_qs; + logic ie0_0_e_31_wd; + logic ie0_1_we; + logic ie0_1_e_32_qs; + logic ie0_1_e_32_wd; + logic ie0_1_e_33_qs; + logic ie0_1_e_33_wd; + logic ie0_1_e_34_qs; + logic ie0_1_e_34_wd; + logic ie0_1_e_35_qs; + logic ie0_1_e_35_wd; + logic ie0_1_e_36_qs; + logic ie0_1_e_36_wd; + logic ie0_1_e_37_qs; + logic ie0_1_e_37_wd; + logic ie0_1_e_38_qs; + logic ie0_1_e_38_wd; + logic ie0_1_e_39_qs; + logic ie0_1_e_39_wd; + logic ie0_1_e_40_qs; + logic ie0_1_e_40_wd; + logic ie0_1_e_41_qs; + logic ie0_1_e_41_wd; + logic ie0_1_e_42_qs; + logic ie0_1_e_42_wd; + logic ie0_1_e_43_qs; + logic ie0_1_e_43_wd; + logic ie0_1_e_44_qs; + logic ie0_1_e_44_wd; + logic ie0_1_e_45_qs; + logic ie0_1_e_45_wd; + logic ie0_1_e_46_qs; + logic ie0_1_e_46_wd; + logic ie0_1_e_47_qs; + logic ie0_1_e_47_wd; + logic ie0_1_e_48_qs; + logic ie0_1_e_48_wd; + logic ie0_1_e_49_qs; + logic ie0_1_e_49_wd; + logic ie0_1_e_50_qs; + logic ie0_1_e_50_wd; + logic ie0_1_e_51_qs; + logic ie0_1_e_51_wd; + logic ie0_1_e_52_qs; + logic ie0_1_e_52_wd; + logic ie0_1_e_53_qs; + logic ie0_1_e_53_wd; + logic ie0_1_e_54_qs; + logic ie0_1_e_54_wd; + logic ie0_1_e_55_qs; + logic ie0_1_e_55_wd; + logic ie0_1_e_56_qs; + logic ie0_1_e_56_wd; + logic ie0_1_e_57_qs; + logic ie0_1_e_57_wd; + logic ie0_1_e_58_qs; + logic ie0_1_e_58_wd; + logic ie0_1_e_59_qs; + logic ie0_1_e_59_wd; + logic ie0_1_e_60_qs; + logic ie0_1_e_60_wd; + logic ie0_1_e_61_qs; + logic ie0_1_e_61_wd; + logic ie0_1_e_62_qs; + logic ie0_1_e_62_wd; + logic ie0_1_e_63_qs; + logic ie0_1_e_63_wd; + logic ie0_2_we; + logic ie0_2_e_64_qs; + logic ie0_2_e_64_wd; + logic ie0_2_e_65_qs; + logic ie0_2_e_65_wd; + logic ie0_2_e_66_qs; + logic ie0_2_e_66_wd; + logic ie0_2_e_67_qs; + logic ie0_2_e_67_wd; + logic ie0_2_e_68_qs; + logic ie0_2_e_68_wd; + logic ie0_2_e_69_qs; + logic ie0_2_e_69_wd; + logic ie0_2_e_70_qs; + logic ie0_2_e_70_wd; + logic ie0_2_e_71_qs; + logic ie0_2_e_71_wd; + logic ie0_2_e_72_qs; + logic ie0_2_e_72_wd; + logic ie0_2_e_73_qs; + logic ie0_2_e_73_wd; + logic ie0_2_e_74_qs; + logic ie0_2_e_74_wd; + logic ie0_2_e_75_qs; + logic ie0_2_e_75_wd; + logic ie0_2_e_76_qs; + logic ie0_2_e_76_wd; + logic ie0_2_e_77_qs; + logic ie0_2_e_77_wd; + logic ie0_2_e_78_qs; + logic ie0_2_e_78_wd; + logic ie0_2_e_79_qs; + logic ie0_2_e_79_wd; + logic ie0_2_e_80_qs; + logic ie0_2_e_80_wd; + logic ie0_2_e_81_qs; + logic ie0_2_e_81_wd; + logic ie0_2_e_82_qs; + logic ie0_2_e_82_wd; + logic ie0_2_e_83_qs; + logic ie0_2_e_83_wd; + logic ie0_2_e_84_qs; + logic ie0_2_e_84_wd; + logic ie0_2_e_85_qs; + logic ie0_2_e_85_wd; + logic ie0_2_e_86_qs; + logic ie0_2_e_86_wd; + logic ie0_2_e_87_qs; + logic ie0_2_e_87_wd; + logic ie0_2_e_88_qs; + logic ie0_2_e_88_wd; + logic ie0_2_e_89_qs; + logic ie0_2_e_89_wd; + logic ie0_2_e_90_qs; + logic ie0_2_e_90_wd; + logic ie0_2_e_91_qs; + logic ie0_2_e_91_wd; + logic ie0_2_e_92_qs; + logic ie0_2_e_92_wd; + logic ie0_2_e_93_qs; + logic ie0_2_e_93_wd; + logic ie0_2_e_94_qs; + logic ie0_2_e_94_wd; + logic ie0_2_e_95_qs; + logic ie0_2_e_95_wd; + logic ie0_3_we; + logic ie0_3_e_96_qs; + logic ie0_3_e_96_wd; + logic ie0_3_e_97_qs; + logic ie0_3_e_97_wd; + logic ie0_3_e_98_qs; + logic ie0_3_e_98_wd; + logic ie0_3_e_99_qs; + logic ie0_3_e_99_wd; + logic ie0_3_e_100_qs; + logic ie0_3_e_100_wd; + logic ie0_3_e_101_qs; + logic ie0_3_e_101_wd; + logic ie0_3_e_102_qs; + logic ie0_3_e_102_wd; + logic ie0_3_e_103_qs; + logic ie0_3_e_103_wd; + logic ie0_3_e_104_qs; + logic ie0_3_e_104_wd; + logic ie0_3_e_105_qs; + logic ie0_3_e_105_wd; + logic ie0_3_e_106_qs; + logic ie0_3_e_106_wd; + logic ie0_3_e_107_qs; + logic ie0_3_e_107_wd; + logic ie0_3_e_108_qs; + logic ie0_3_e_108_wd; + logic ie0_3_e_109_qs; + logic ie0_3_e_109_wd; + logic ie0_3_e_110_qs; + logic ie0_3_e_110_wd; + logic ie0_3_e_111_qs; + logic ie0_3_e_111_wd; + logic ie0_3_e_112_qs; + logic ie0_3_e_112_wd; + logic ie0_3_e_113_qs; + logic ie0_3_e_113_wd; + logic ie0_3_e_114_qs; + logic ie0_3_e_114_wd; + logic ie0_3_e_115_qs; + logic ie0_3_e_115_wd; + logic ie0_3_e_116_qs; + logic ie0_3_e_116_wd; + logic ie0_3_e_117_qs; + logic ie0_3_e_117_wd; + logic ie0_3_e_118_qs; + logic ie0_3_e_118_wd; + logic ie0_3_e_119_qs; + logic ie0_3_e_119_wd; + logic ie0_3_e_120_qs; + logic ie0_3_e_120_wd; + logic ie0_3_e_121_qs; + logic ie0_3_e_121_wd; + logic ie0_3_e_122_qs; + logic ie0_3_e_122_wd; + logic ie0_3_e_123_qs; + logic ie0_3_e_123_wd; + logic ie0_3_e_124_qs; + logic ie0_3_e_124_wd; + logic ie0_3_e_125_qs; + logic ie0_3_e_125_wd; + logic ie0_3_e_126_qs; + logic ie0_3_e_126_wd; + logic ie0_3_e_127_qs; + logic ie0_3_e_127_wd; + logic ie0_4_we; + logic ie0_4_e_128_qs; + logic ie0_4_e_128_wd; + logic ie0_4_e_129_qs; + logic ie0_4_e_129_wd; + logic ie0_4_e_130_qs; + logic ie0_4_e_130_wd; + logic ie0_4_e_131_qs; + logic ie0_4_e_131_wd; + logic ie0_4_e_132_qs; + logic ie0_4_e_132_wd; + logic ie0_4_e_133_qs; + logic ie0_4_e_133_wd; + logic ie0_4_e_134_qs; + logic ie0_4_e_134_wd; + logic ie0_4_e_135_qs; + logic ie0_4_e_135_wd; + logic ie0_4_e_136_qs; + logic ie0_4_e_136_wd; + logic ie0_4_e_137_qs; + logic ie0_4_e_137_wd; + logic ie0_4_e_138_qs; + logic ie0_4_e_138_wd; + logic ie0_4_e_139_qs; + logic ie0_4_e_139_wd; + logic ie0_4_e_140_qs; + logic ie0_4_e_140_wd; + logic ie0_4_e_141_qs; + logic ie0_4_e_141_wd; + logic ie0_4_e_142_qs; + logic ie0_4_e_142_wd; + logic ie0_4_e_143_qs; + logic ie0_4_e_143_wd; + logic ie0_4_e_144_qs; + logic ie0_4_e_144_wd; + logic ie0_4_e_145_qs; + logic ie0_4_e_145_wd; + logic ie0_4_e_146_qs; + logic ie0_4_e_146_wd; + logic ie0_4_e_147_qs; + logic ie0_4_e_147_wd; + logic ie0_4_e_148_qs; + logic ie0_4_e_148_wd; + logic ie0_4_e_149_qs; + logic ie0_4_e_149_wd; + logic ie0_4_e_150_qs; + logic ie0_4_e_150_wd; + logic ie0_4_e_151_qs; + logic ie0_4_e_151_wd; + logic ie0_4_e_152_qs; + logic ie0_4_e_152_wd; + logic ie0_4_e_153_qs; + logic ie0_4_e_153_wd; + logic ie0_4_e_154_qs; + logic ie0_4_e_154_wd; + logic ie0_4_e_155_qs; + logic ie0_4_e_155_wd; + logic ie0_4_e_156_qs; + logic ie0_4_e_156_wd; + logic ie0_4_e_157_qs; + logic ie0_4_e_157_wd; + logic ie0_4_e_158_qs; + logic ie0_4_e_158_wd; + logic ie0_4_e_159_qs; + logic ie0_4_e_159_wd; + logic ie0_5_we; + logic ie0_5_e_160_qs; + logic ie0_5_e_160_wd; + logic ie0_5_e_161_qs; + logic ie0_5_e_161_wd; + logic ie0_5_e_162_qs; + logic ie0_5_e_162_wd; + logic threshold0_we; + logic [1:0] threshold0_qs; + logic [1:0] threshold0_wd; + logic cc0_re; + logic cc0_we; + logic [7:0] cc0_qs; + logic [7:0] cc0_wd; + logic msip0_we; + logic msip0_qs; + logic msip0_wd; + logic alert_test_we; + logic alert_test_wd; + + // Register instances + // Subregister 0 of Multireg prio + // R[prio_0]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_0_we), + .wd (prio_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[0].q), + .ds (), + + // to register interface (read) + .qs (prio_0_qs) + ); + + + // Subregister 1 of Multireg prio + // R[prio_1]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_1_we), + .wd (prio_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[1].q), + .ds (), + + // to register interface (read) + .qs (prio_1_qs) + ); + + + // Subregister 2 of Multireg prio + // R[prio_2]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_2_we), + .wd (prio_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[2].q), + .ds (), + + // to register interface (read) + .qs (prio_2_qs) + ); + + + // Subregister 3 of Multireg prio + // R[prio_3]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_3_we), + .wd (prio_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[3].q), + .ds (), + + // to register interface (read) + .qs (prio_3_qs) + ); + + + // Subregister 4 of Multireg prio + // R[prio_4]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_4_we), + .wd (prio_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[4].q), + .ds (), + + // to register interface (read) + .qs (prio_4_qs) + ); + + + // Subregister 5 of Multireg prio + // R[prio_5]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_5_we), + .wd (prio_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[5].q), + .ds (), + + // to register interface (read) + .qs (prio_5_qs) + ); + + + // Subregister 6 of Multireg prio + // R[prio_6]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_6_we), + .wd (prio_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[6].q), + .ds (), + + // to register interface (read) + .qs (prio_6_qs) + ); + + + // Subregister 7 of Multireg prio + // R[prio_7]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_7_we), + .wd (prio_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[7].q), + .ds (), + + // to register interface (read) + .qs (prio_7_qs) + ); + + + // Subregister 8 of Multireg prio + // R[prio_8]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_8_we), + .wd (prio_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[8].q), + .ds (), + + // to register interface (read) + .qs (prio_8_qs) + ); + + + // Subregister 9 of Multireg prio + // R[prio_9]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_9_we), + .wd (prio_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[9].q), + .ds (), + + // to register interface (read) + .qs (prio_9_qs) + ); + + + // Subregister 10 of Multireg prio + // R[prio_10]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_10_we), + .wd (prio_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[10].q), + .ds (), + + // to register interface (read) + .qs (prio_10_qs) + ); + + + // Subregister 11 of Multireg prio + // R[prio_11]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_11_we), + .wd (prio_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[11].q), + .ds (), + + // to register interface (read) + .qs (prio_11_qs) + ); + + + // Subregister 12 of Multireg prio + // R[prio_12]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_12_we), + .wd (prio_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[12].q), + .ds (), + + // to register interface (read) + .qs (prio_12_qs) + ); + + + // Subregister 13 of Multireg prio + // R[prio_13]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_13_we), + .wd (prio_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[13].q), + .ds (), + + // to register interface (read) + .qs (prio_13_qs) + ); + + + // Subregister 14 of Multireg prio + // R[prio_14]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_14_we), + .wd (prio_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[14].q), + .ds (), + + // to register interface (read) + .qs (prio_14_qs) + ); + + + // Subregister 15 of Multireg prio + // R[prio_15]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_15_we), + .wd (prio_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[15].q), + .ds (), + + // to register interface (read) + .qs (prio_15_qs) + ); + + + // Subregister 16 of Multireg prio + // R[prio_16]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_16_we), + .wd (prio_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[16].q), + .ds (), + + // to register interface (read) + .qs (prio_16_qs) + ); + + + // Subregister 17 of Multireg prio + // R[prio_17]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_17_we), + .wd (prio_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[17].q), + .ds (), + + // to register interface (read) + .qs (prio_17_qs) + ); + + + // Subregister 18 of Multireg prio + // R[prio_18]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_18_we), + .wd (prio_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[18].q), + .ds (), + + // to register interface (read) + .qs (prio_18_qs) + ); + + + // Subregister 19 of Multireg prio + // R[prio_19]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_19_we), + .wd (prio_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[19].q), + .ds (), + + // to register interface (read) + .qs (prio_19_qs) + ); + + + // Subregister 20 of Multireg prio + // R[prio_20]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_20_we), + .wd (prio_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[20].q), + .ds (), + + // to register interface (read) + .qs (prio_20_qs) + ); + + + // Subregister 21 of Multireg prio + // R[prio_21]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_21_we), + .wd (prio_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[21].q), + .ds (), + + // to register interface (read) + .qs (prio_21_qs) + ); + + + // Subregister 22 of Multireg prio + // R[prio_22]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_22_we), + .wd (prio_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[22].q), + .ds (), + + // to register interface (read) + .qs (prio_22_qs) + ); + + + // Subregister 23 of Multireg prio + // R[prio_23]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_23_we), + .wd (prio_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[23].q), + .ds (), + + // to register interface (read) + .qs (prio_23_qs) + ); + + + // Subregister 24 of Multireg prio + // R[prio_24]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_24_we), + .wd (prio_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[24].q), + .ds (), + + // to register interface (read) + .qs (prio_24_qs) + ); + + + // Subregister 25 of Multireg prio + // R[prio_25]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_25_we), + .wd (prio_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[25].q), + .ds (), + + // to register interface (read) + .qs (prio_25_qs) + ); + + + // Subregister 26 of Multireg prio + // R[prio_26]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_26_we), + .wd (prio_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[26].q), + .ds (), + + // to register interface (read) + .qs (prio_26_qs) + ); + + + // Subregister 27 of Multireg prio + // R[prio_27]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_27_we), + .wd (prio_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[27].q), + .ds (), + + // to register interface (read) + .qs (prio_27_qs) + ); + + + // Subregister 28 of Multireg prio + // R[prio_28]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_28_we), + .wd (prio_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[28].q), + .ds (), + + // to register interface (read) + .qs (prio_28_qs) + ); + + + // Subregister 29 of Multireg prio + // R[prio_29]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_29_we), + .wd (prio_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[29].q), + .ds (), + + // to register interface (read) + .qs (prio_29_qs) + ); + + + // Subregister 30 of Multireg prio + // R[prio_30]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_30_we), + .wd (prio_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[30].q), + .ds (), + + // to register interface (read) + .qs (prio_30_qs) + ); + + + // Subregister 31 of Multireg prio + // R[prio_31]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_31_we), + .wd (prio_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[31].q), + .ds (), + + // to register interface (read) + .qs (prio_31_qs) + ); + + + // Subregister 32 of Multireg prio + // R[prio_32]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_32_we), + .wd (prio_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[32].q), + .ds (), + + // to register interface (read) + .qs (prio_32_qs) + ); + + + // Subregister 33 of Multireg prio + // R[prio_33]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_33_we), + .wd (prio_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[33].q), + .ds (), + + // to register interface (read) + .qs (prio_33_qs) + ); + + + // Subregister 34 of Multireg prio + // R[prio_34]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_34_we), + .wd (prio_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[34].q), + .ds (), + + // to register interface (read) + .qs (prio_34_qs) + ); + + + // Subregister 35 of Multireg prio + // R[prio_35]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_35_we), + .wd (prio_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[35].q), + .ds (), + + // to register interface (read) + .qs (prio_35_qs) + ); + + + // Subregister 36 of Multireg prio + // R[prio_36]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_36_we), + .wd (prio_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[36].q), + .ds (), + + // to register interface (read) + .qs (prio_36_qs) + ); + + + // Subregister 37 of Multireg prio + // R[prio_37]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_37_we), + .wd (prio_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[37].q), + .ds (), + + // to register interface (read) + .qs (prio_37_qs) + ); + + + // Subregister 38 of Multireg prio + // R[prio_38]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_38_we), + .wd (prio_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[38].q), + .ds (), + + // to register interface (read) + .qs (prio_38_qs) + ); + + + // Subregister 39 of Multireg prio + // R[prio_39]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_39_we), + .wd (prio_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[39].q), + .ds (), + + // to register interface (read) + .qs (prio_39_qs) + ); + + + // Subregister 40 of Multireg prio + // R[prio_40]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_40_we), + .wd (prio_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[40].q), + .ds (), + + // to register interface (read) + .qs (prio_40_qs) + ); + + + // Subregister 41 of Multireg prio + // R[prio_41]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_41_we), + .wd (prio_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[41].q), + .ds (), + + // to register interface (read) + .qs (prio_41_qs) + ); + + + // Subregister 42 of Multireg prio + // R[prio_42]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_42_we), + .wd (prio_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[42].q), + .ds (), + + // to register interface (read) + .qs (prio_42_qs) + ); + + + // Subregister 43 of Multireg prio + // R[prio_43]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_43_we), + .wd (prio_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[43].q), + .ds (), + + // to register interface (read) + .qs (prio_43_qs) + ); + + + // Subregister 44 of Multireg prio + // R[prio_44]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_44_we), + .wd (prio_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[44].q), + .ds (), + + // to register interface (read) + .qs (prio_44_qs) + ); + + + // Subregister 45 of Multireg prio + // R[prio_45]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_45_we), + .wd (prio_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[45].q), + .ds (), + + // to register interface (read) + .qs (prio_45_qs) + ); + + + // Subregister 46 of Multireg prio + // R[prio_46]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_46_we), + .wd (prio_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[46].q), + .ds (), + + // to register interface (read) + .qs (prio_46_qs) + ); + + + // Subregister 47 of Multireg prio + // R[prio_47]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_47_we), + .wd (prio_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[47].q), + .ds (), + + // to register interface (read) + .qs (prio_47_qs) + ); + + + // Subregister 48 of Multireg prio + // R[prio_48]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_48_we), + .wd (prio_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[48].q), + .ds (), + + // to register interface (read) + .qs (prio_48_qs) + ); + + + // Subregister 49 of Multireg prio + // R[prio_49]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_49_we), + .wd (prio_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[49].q), + .ds (), + + // to register interface (read) + .qs (prio_49_qs) + ); + + + // Subregister 50 of Multireg prio + // R[prio_50]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_50_we), + .wd (prio_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[50].q), + .ds (), + + // to register interface (read) + .qs (prio_50_qs) + ); + + + // Subregister 51 of Multireg prio + // R[prio_51]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_51_we), + .wd (prio_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[51].q), + .ds (), + + // to register interface (read) + .qs (prio_51_qs) + ); + + + // Subregister 52 of Multireg prio + // R[prio_52]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_52_we), + .wd (prio_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[52].q), + .ds (), + + // to register interface (read) + .qs (prio_52_qs) + ); + + + // Subregister 53 of Multireg prio + // R[prio_53]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_53_we), + .wd (prio_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[53].q), + .ds (), + + // to register interface (read) + .qs (prio_53_qs) + ); + + + // Subregister 54 of Multireg prio + // R[prio_54]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_54_we), + .wd (prio_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[54].q), + .ds (), + + // to register interface (read) + .qs (prio_54_qs) + ); + + + // Subregister 55 of Multireg prio + // R[prio_55]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_55_we), + .wd (prio_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[55].q), + .ds (), + + // to register interface (read) + .qs (prio_55_qs) + ); + + + // Subregister 56 of Multireg prio + // R[prio_56]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_56_we), + .wd (prio_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[56].q), + .ds (), + + // to register interface (read) + .qs (prio_56_qs) + ); + + + // Subregister 57 of Multireg prio + // R[prio_57]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_57_we), + .wd (prio_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[57].q), + .ds (), + + // to register interface (read) + .qs (prio_57_qs) + ); + + + // Subregister 58 of Multireg prio + // R[prio_58]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_58_we), + .wd (prio_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[58].q), + .ds (), + + // to register interface (read) + .qs (prio_58_qs) + ); + + + // Subregister 59 of Multireg prio + // R[prio_59]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_59_we), + .wd (prio_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[59].q), + .ds (), + + // to register interface (read) + .qs (prio_59_qs) + ); + + + // Subregister 60 of Multireg prio + // R[prio_60]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_60_we), + .wd (prio_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[60].q), + .ds (), + + // to register interface (read) + .qs (prio_60_qs) + ); + + + // Subregister 61 of Multireg prio + // R[prio_61]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_61_we), + .wd (prio_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[61].q), + .ds (), + + // to register interface (read) + .qs (prio_61_qs) + ); + + + // Subregister 62 of Multireg prio + // R[prio_62]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_62_we), + .wd (prio_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[62].q), + .ds (), + + // to register interface (read) + .qs (prio_62_qs) + ); + + + // Subregister 63 of Multireg prio + // R[prio_63]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_63_we), + .wd (prio_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[63].q), + .ds (), + + // to register interface (read) + .qs (prio_63_qs) + ); + + + // Subregister 64 of Multireg prio + // R[prio_64]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_64_we), + .wd (prio_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[64].q), + .ds (), + + // to register interface (read) + .qs (prio_64_qs) + ); + + + // Subregister 65 of Multireg prio + // R[prio_65]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_65_we), + .wd (prio_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[65].q), + .ds (), + + // to register interface (read) + .qs (prio_65_qs) + ); + + + // Subregister 66 of Multireg prio + // R[prio_66]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_66_we), + .wd (prio_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[66].q), + .ds (), + + // to register interface (read) + .qs (prio_66_qs) + ); + + + // Subregister 67 of Multireg prio + // R[prio_67]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_67_we), + .wd (prio_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[67].q), + .ds (), + + // to register interface (read) + .qs (prio_67_qs) + ); + + + // Subregister 68 of Multireg prio + // R[prio_68]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_68_we), + .wd (prio_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[68].q), + .ds (), + + // to register interface (read) + .qs (prio_68_qs) + ); + + + // Subregister 69 of Multireg prio + // R[prio_69]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_69_we), + .wd (prio_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[69].q), + .ds (), + + // to register interface (read) + .qs (prio_69_qs) + ); + + + // Subregister 70 of Multireg prio + // R[prio_70]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_70_we), + .wd (prio_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[70].q), + .ds (), + + // to register interface (read) + .qs (prio_70_qs) + ); + + + // Subregister 71 of Multireg prio + // R[prio_71]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_71_we), + .wd (prio_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[71].q), + .ds (), + + // to register interface (read) + .qs (prio_71_qs) + ); + + + // Subregister 72 of Multireg prio + // R[prio_72]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_72_we), + .wd (prio_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[72].q), + .ds (), + + // to register interface (read) + .qs (prio_72_qs) + ); + + + // Subregister 73 of Multireg prio + // R[prio_73]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_73_we), + .wd (prio_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[73].q), + .ds (), + + // to register interface (read) + .qs (prio_73_qs) + ); + + + // Subregister 74 of Multireg prio + // R[prio_74]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_74_we), + .wd (prio_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[74].q), + .ds (), + + // to register interface (read) + .qs (prio_74_qs) + ); + + + // Subregister 75 of Multireg prio + // R[prio_75]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_75_we), + .wd (prio_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[75].q), + .ds (), + + // to register interface (read) + .qs (prio_75_qs) + ); + + + // Subregister 76 of Multireg prio + // R[prio_76]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_76_we), + .wd (prio_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[76].q), + .ds (), + + // to register interface (read) + .qs (prio_76_qs) + ); + + + // Subregister 77 of Multireg prio + // R[prio_77]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_77_we), + .wd (prio_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[77].q), + .ds (), + + // to register interface (read) + .qs (prio_77_qs) + ); + + + // Subregister 78 of Multireg prio + // R[prio_78]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_78_we), + .wd (prio_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[78].q), + .ds (), + + // to register interface (read) + .qs (prio_78_qs) + ); + + + // Subregister 79 of Multireg prio + // R[prio_79]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_79_we), + .wd (prio_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[79].q), + .ds (), + + // to register interface (read) + .qs (prio_79_qs) + ); + + + // Subregister 80 of Multireg prio + // R[prio_80]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_80_we), + .wd (prio_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[80].q), + .ds (), + + // to register interface (read) + .qs (prio_80_qs) + ); + + + // Subregister 81 of Multireg prio + // R[prio_81]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_81_we), + .wd (prio_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[81].q), + .ds (), + + // to register interface (read) + .qs (prio_81_qs) + ); + + + // Subregister 82 of Multireg prio + // R[prio_82]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_82_we), + .wd (prio_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[82].q), + .ds (), + + // to register interface (read) + .qs (prio_82_qs) + ); + + + // Subregister 83 of Multireg prio + // R[prio_83]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_83_we), + .wd (prio_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[83].q), + .ds (), + + // to register interface (read) + .qs (prio_83_qs) + ); + + + // Subregister 84 of Multireg prio + // R[prio_84]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_84_we), + .wd (prio_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[84].q), + .ds (), + + // to register interface (read) + .qs (prio_84_qs) + ); + + + // Subregister 85 of Multireg prio + // R[prio_85]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_85_we), + .wd (prio_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[85].q), + .ds (), + + // to register interface (read) + .qs (prio_85_qs) + ); + + + // Subregister 86 of Multireg prio + // R[prio_86]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_86_we), + .wd (prio_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[86].q), + .ds (), + + // to register interface (read) + .qs (prio_86_qs) + ); + + + // Subregister 87 of Multireg prio + // R[prio_87]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_87_we), + .wd (prio_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[87].q), + .ds (), + + // to register interface (read) + .qs (prio_87_qs) + ); + + + // Subregister 88 of Multireg prio + // R[prio_88]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_88_we), + .wd (prio_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[88].q), + .ds (), + + // to register interface (read) + .qs (prio_88_qs) + ); + + + // Subregister 89 of Multireg prio + // R[prio_89]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_89_we), + .wd (prio_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[89].q), + .ds (), + + // to register interface (read) + .qs (prio_89_qs) + ); + + + // Subregister 90 of Multireg prio + // R[prio_90]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_90_we), + .wd (prio_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[90].q), + .ds (), + + // to register interface (read) + .qs (prio_90_qs) + ); + + + // Subregister 91 of Multireg prio + // R[prio_91]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_91_we), + .wd (prio_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[91].q), + .ds (), + + // to register interface (read) + .qs (prio_91_qs) + ); + + + // Subregister 92 of Multireg prio + // R[prio_92]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_92_we), + .wd (prio_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[92].q), + .ds (), + + // to register interface (read) + .qs (prio_92_qs) + ); + + + // Subregister 93 of Multireg prio + // R[prio_93]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_93_we), + .wd (prio_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[93].q), + .ds (), + + // to register interface (read) + .qs (prio_93_qs) + ); + + + // Subregister 94 of Multireg prio + // R[prio_94]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_94_we), + .wd (prio_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[94].q), + .ds (), + + // to register interface (read) + .qs (prio_94_qs) + ); + + + // Subregister 95 of Multireg prio + // R[prio_95]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_95_we), + .wd (prio_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[95].q), + .ds (), + + // to register interface (read) + .qs (prio_95_qs) + ); + + + // Subregister 96 of Multireg prio + // R[prio_96]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_96_we), + .wd (prio_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[96].q), + .ds (), + + // to register interface (read) + .qs (prio_96_qs) + ); + + + // Subregister 97 of Multireg prio + // R[prio_97]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_97_we), + .wd (prio_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[97].q), + .ds (), + + // to register interface (read) + .qs (prio_97_qs) + ); + + + // Subregister 98 of Multireg prio + // R[prio_98]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_98_we), + .wd (prio_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[98].q), + .ds (), + + // to register interface (read) + .qs (prio_98_qs) + ); + + + // Subregister 99 of Multireg prio + // R[prio_99]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_99 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_99_we), + .wd (prio_99_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[99].q), + .ds (), + + // to register interface (read) + .qs (prio_99_qs) + ); + + + // Subregister 100 of Multireg prio + // R[prio_100]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_100 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_100_we), + .wd (prio_100_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[100].q), + .ds (), + + // to register interface (read) + .qs (prio_100_qs) + ); + + + // Subregister 101 of Multireg prio + // R[prio_101]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_101 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_101_we), + .wd (prio_101_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[101].q), + .ds (), + + // to register interface (read) + .qs (prio_101_qs) + ); + + + // Subregister 102 of Multireg prio + // R[prio_102]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_102 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_102_we), + .wd (prio_102_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[102].q), + .ds (), + + // to register interface (read) + .qs (prio_102_qs) + ); + + + // Subregister 103 of Multireg prio + // R[prio_103]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_103 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_103_we), + .wd (prio_103_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[103].q), + .ds (), + + // to register interface (read) + .qs (prio_103_qs) + ); + + + // Subregister 104 of Multireg prio + // R[prio_104]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_104 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_104_we), + .wd (prio_104_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[104].q), + .ds (), + + // to register interface (read) + .qs (prio_104_qs) + ); + + + // Subregister 105 of Multireg prio + // R[prio_105]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_105 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_105_we), + .wd (prio_105_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[105].q), + .ds (), + + // to register interface (read) + .qs (prio_105_qs) + ); + + + // Subregister 106 of Multireg prio + // R[prio_106]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_106 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_106_we), + .wd (prio_106_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[106].q), + .ds (), + + // to register interface (read) + .qs (prio_106_qs) + ); + + + // Subregister 107 of Multireg prio + // R[prio_107]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_107 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_107_we), + .wd (prio_107_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[107].q), + .ds (), + + // to register interface (read) + .qs (prio_107_qs) + ); + + + // Subregister 108 of Multireg prio + // R[prio_108]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_108 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_108_we), + .wd (prio_108_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[108].q), + .ds (), + + // to register interface (read) + .qs (prio_108_qs) + ); + + + // Subregister 109 of Multireg prio + // R[prio_109]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_109 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_109_we), + .wd (prio_109_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[109].q), + .ds (), + + // to register interface (read) + .qs (prio_109_qs) + ); + + + // Subregister 110 of Multireg prio + // R[prio_110]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_110 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_110_we), + .wd (prio_110_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[110].q), + .ds (), + + // to register interface (read) + .qs (prio_110_qs) + ); + + + // Subregister 111 of Multireg prio + // R[prio_111]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_111 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_111_we), + .wd (prio_111_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[111].q), + .ds (), + + // to register interface (read) + .qs (prio_111_qs) + ); + + + // Subregister 112 of Multireg prio + // R[prio_112]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_112 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_112_we), + .wd (prio_112_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[112].q), + .ds (), + + // to register interface (read) + .qs (prio_112_qs) + ); + + + // Subregister 113 of Multireg prio + // R[prio_113]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_113 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_113_we), + .wd (prio_113_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[113].q), + .ds (), + + // to register interface (read) + .qs (prio_113_qs) + ); + + + // Subregister 114 of Multireg prio + // R[prio_114]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_114 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_114_we), + .wd (prio_114_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[114].q), + .ds (), + + // to register interface (read) + .qs (prio_114_qs) + ); + + + // Subregister 115 of Multireg prio + // R[prio_115]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_115 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_115_we), + .wd (prio_115_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[115].q), + .ds (), + + // to register interface (read) + .qs (prio_115_qs) + ); + + + // Subregister 116 of Multireg prio + // R[prio_116]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_116 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_116_we), + .wd (prio_116_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[116].q), + .ds (), + + // to register interface (read) + .qs (prio_116_qs) + ); + + + // Subregister 117 of Multireg prio + // R[prio_117]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_117 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_117_we), + .wd (prio_117_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[117].q), + .ds (), + + // to register interface (read) + .qs (prio_117_qs) + ); + + + // Subregister 118 of Multireg prio + // R[prio_118]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_118 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_118_we), + .wd (prio_118_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[118].q), + .ds (), + + // to register interface (read) + .qs (prio_118_qs) + ); + + + // Subregister 119 of Multireg prio + // R[prio_119]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_119 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_119_we), + .wd (prio_119_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[119].q), + .ds (), + + // to register interface (read) + .qs (prio_119_qs) + ); + + + // Subregister 120 of Multireg prio + // R[prio_120]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_120 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_120_we), + .wd (prio_120_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[120].q), + .ds (), + + // to register interface (read) + .qs (prio_120_qs) + ); + + + // Subregister 121 of Multireg prio + // R[prio_121]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_121 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_121_we), + .wd (prio_121_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[121].q), + .ds (), + + // to register interface (read) + .qs (prio_121_qs) + ); + + + // Subregister 122 of Multireg prio + // R[prio_122]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_122 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_122_we), + .wd (prio_122_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[122].q), + .ds (), + + // to register interface (read) + .qs (prio_122_qs) + ); + + + // Subregister 123 of Multireg prio + // R[prio_123]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_123 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_123_we), + .wd (prio_123_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[123].q), + .ds (), + + // to register interface (read) + .qs (prio_123_qs) + ); + + + // Subregister 124 of Multireg prio + // R[prio_124]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_124 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_124_we), + .wd (prio_124_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[124].q), + .ds (), + + // to register interface (read) + .qs (prio_124_qs) + ); + + + // Subregister 125 of Multireg prio + // R[prio_125]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_125 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_125_we), + .wd (prio_125_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[125].q), + .ds (), + + // to register interface (read) + .qs (prio_125_qs) + ); + + + // Subregister 126 of Multireg prio + // R[prio_126]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_126 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_126_we), + .wd (prio_126_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[126].q), + .ds (), + + // to register interface (read) + .qs (prio_126_qs) + ); + + + // Subregister 127 of Multireg prio + // R[prio_127]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_127 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_127_we), + .wd (prio_127_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[127].q), + .ds (), + + // to register interface (read) + .qs (prio_127_qs) + ); + + + // Subregister 128 of Multireg prio + // R[prio_128]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_128 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_128_we), + .wd (prio_128_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[128].q), + .ds (), + + // to register interface (read) + .qs (prio_128_qs) + ); + + + // Subregister 129 of Multireg prio + // R[prio_129]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_129 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_129_we), + .wd (prio_129_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[129].q), + .ds (), + + // to register interface (read) + .qs (prio_129_qs) + ); + + + // Subregister 130 of Multireg prio + // R[prio_130]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_130 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_130_we), + .wd (prio_130_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[130].q), + .ds (), + + // to register interface (read) + .qs (prio_130_qs) + ); + + + // Subregister 131 of Multireg prio + // R[prio_131]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_131 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_131_we), + .wd (prio_131_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[131].q), + .ds (), + + // to register interface (read) + .qs (prio_131_qs) + ); + + + // Subregister 132 of Multireg prio + // R[prio_132]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_132 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_132_we), + .wd (prio_132_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[132].q), + .ds (), + + // to register interface (read) + .qs (prio_132_qs) + ); + + + // Subregister 133 of Multireg prio + // R[prio_133]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_133 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_133_we), + .wd (prio_133_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[133].q), + .ds (), + + // to register interface (read) + .qs (prio_133_qs) + ); + + + // Subregister 134 of Multireg prio + // R[prio_134]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_134 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_134_we), + .wd (prio_134_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[134].q), + .ds (), + + // to register interface (read) + .qs (prio_134_qs) + ); + + + // Subregister 135 of Multireg prio + // R[prio_135]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_135 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_135_we), + .wd (prio_135_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[135].q), + .ds (), + + // to register interface (read) + .qs (prio_135_qs) + ); + + + // Subregister 136 of Multireg prio + // R[prio_136]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_136 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_136_we), + .wd (prio_136_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[136].q), + .ds (), + + // to register interface (read) + .qs (prio_136_qs) + ); + + + // Subregister 137 of Multireg prio + // R[prio_137]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_137 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_137_we), + .wd (prio_137_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[137].q), + .ds (), + + // to register interface (read) + .qs (prio_137_qs) + ); + + + // Subregister 138 of Multireg prio + // R[prio_138]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_138 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_138_we), + .wd (prio_138_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[138].q), + .ds (), + + // to register interface (read) + .qs (prio_138_qs) + ); + + + // Subregister 139 of Multireg prio + // R[prio_139]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_139 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_139_we), + .wd (prio_139_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[139].q), + .ds (), + + // to register interface (read) + .qs (prio_139_qs) + ); + + + // Subregister 140 of Multireg prio + // R[prio_140]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_140 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_140_we), + .wd (prio_140_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[140].q), + .ds (), + + // to register interface (read) + .qs (prio_140_qs) + ); + + + // Subregister 141 of Multireg prio + // R[prio_141]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_141 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_141_we), + .wd (prio_141_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[141].q), + .ds (), + + // to register interface (read) + .qs (prio_141_qs) + ); + + + // Subregister 142 of Multireg prio + // R[prio_142]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_142 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_142_we), + .wd (prio_142_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[142].q), + .ds (), + + // to register interface (read) + .qs (prio_142_qs) + ); + + + // Subregister 143 of Multireg prio + // R[prio_143]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_143 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_143_we), + .wd (prio_143_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[143].q), + .ds (), + + // to register interface (read) + .qs (prio_143_qs) + ); + + + // Subregister 144 of Multireg prio + // R[prio_144]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_144 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_144_we), + .wd (prio_144_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[144].q), + .ds (), + + // to register interface (read) + .qs (prio_144_qs) + ); + + + // Subregister 145 of Multireg prio + // R[prio_145]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_145 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_145_we), + .wd (prio_145_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[145].q), + .ds (), + + // to register interface (read) + .qs (prio_145_qs) + ); + + + // Subregister 146 of Multireg prio + // R[prio_146]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_146 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_146_we), + .wd (prio_146_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[146].q), + .ds (), + + // to register interface (read) + .qs (prio_146_qs) + ); + + + // Subregister 147 of Multireg prio + // R[prio_147]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_147 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_147_we), + .wd (prio_147_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[147].q), + .ds (), + + // to register interface (read) + .qs (prio_147_qs) + ); + + + // Subregister 148 of Multireg prio + // R[prio_148]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_148 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_148_we), + .wd (prio_148_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[148].q), + .ds (), + + // to register interface (read) + .qs (prio_148_qs) + ); + + + // Subregister 149 of Multireg prio + // R[prio_149]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_149 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_149_we), + .wd (prio_149_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[149].q), + .ds (), + + // to register interface (read) + .qs (prio_149_qs) + ); + + + // Subregister 150 of Multireg prio + // R[prio_150]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_150 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_150_we), + .wd (prio_150_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[150].q), + .ds (), + + // to register interface (read) + .qs (prio_150_qs) + ); + + + // Subregister 151 of Multireg prio + // R[prio_151]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_151 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_151_we), + .wd (prio_151_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[151].q), + .ds (), + + // to register interface (read) + .qs (prio_151_qs) + ); + + + // Subregister 152 of Multireg prio + // R[prio_152]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_152 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_152_we), + .wd (prio_152_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[152].q), + .ds (), + + // to register interface (read) + .qs (prio_152_qs) + ); + + + // Subregister 153 of Multireg prio + // R[prio_153]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_153 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_153_we), + .wd (prio_153_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[153].q), + .ds (), + + // to register interface (read) + .qs (prio_153_qs) + ); + + + // Subregister 154 of Multireg prio + // R[prio_154]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_154 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_154_we), + .wd (prio_154_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[154].q), + .ds (), + + // to register interface (read) + .qs (prio_154_qs) + ); + + + // Subregister 155 of Multireg prio + // R[prio_155]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_155 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_155_we), + .wd (prio_155_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[155].q), + .ds (), + + // to register interface (read) + .qs (prio_155_qs) + ); + + + // Subregister 156 of Multireg prio + // R[prio_156]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_156 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_156_we), + .wd (prio_156_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[156].q), + .ds (), + + // to register interface (read) + .qs (prio_156_qs) + ); + + + // Subregister 157 of Multireg prio + // R[prio_157]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_157 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_157_we), + .wd (prio_157_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[157].q), + .ds (), + + // to register interface (read) + .qs (prio_157_qs) + ); + + + // Subregister 158 of Multireg prio + // R[prio_158]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_158 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_158_we), + .wd (prio_158_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[158].q), + .ds (), + + // to register interface (read) + .qs (prio_158_qs) + ); + + + // Subregister 159 of Multireg prio + // R[prio_159]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_159 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_159_we), + .wd (prio_159_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[159].q), + .ds (), + + // to register interface (read) + .qs (prio_159_qs) + ); + + + // Subregister 160 of Multireg prio + // R[prio_160]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_160 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_160_we), + .wd (prio_160_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[160].q), + .ds (), + + // to register interface (read) + .qs (prio_160_qs) + ); + + + // Subregister 161 of Multireg prio + // R[prio_161]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_161 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_161_we), + .wd (prio_161_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[161].q), + .ds (), + + // to register interface (read) + .qs (prio_161_qs) + ); + + + // Subregister 162 of Multireg prio + // R[prio_162]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_prio_162 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (prio_162_we), + .wd (prio_162_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.prio[162].q), + .ds (), + + // to register interface (read) + .qs (prio_162_qs) + ); + + + // Subregister 0 of Multireg ip + // R[ip_0]: V(False) + // F[p_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[0].de), + .d (hw2reg.ip[0].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_0_qs) + ); + + // F[p_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[1].de), + .d (hw2reg.ip[1].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_1_qs) + ); + + // F[p_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[2].de), + .d (hw2reg.ip[2].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_2_qs) + ); + + // F[p_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[3].de), + .d (hw2reg.ip[3].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_3_qs) + ); + + // F[p_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[4].de), + .d (hw2reg.ip[4].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_4_qs) + ); + + // F[p_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[5].de), + .d (hw2reg.ip[5].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_5_qs) + ); + + // F[p_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[6].de), + .d (hw2reg.ip[6].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_6_qs) + ); + + // F[p_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[7].de), + .d (hw2reg.ip[7].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_7_qs) + ); + + // F[p_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[8].de), + .d (hw2reg.ip[8].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_8_qs) + ); + + // F[p_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[9].de), + .d (hw2reg.ip[9].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_9_qs) + ); + + // F[p_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[10].de), + .d (hw2reg.ip[10].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_10_qs) + ); + + // F[p_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[11].de), + .d (hw2reg.ip[11].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_11_qs) + ); + + // F[p_12]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[12].de), + .d (hw2reg.ip[12].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_12_qs) + ); + + // F[p_13]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[13].de), + .d (hw2reg.ip[13].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_13_qs) + ); + + // F[p_14]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[14].de), + .d (hw2reg.ip[14].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_14_qs) + ); + + // F[p_15]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[15].de), + .d (hw2reg.ip[15].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_15_qs) + ); + + // F[p_16]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[16].de), + .d (hw2reg.ip[16].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_16_qs) + ); + + // F[p_17]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[17].de), + .d (hw2reg.ip[17].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_17_qs) + ); + + // F[p_18]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[18].de), + .d (hw2reg.ip[18].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_18_qs) + ); + + // F[p_19]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[19].de), + .d (hw2reg.ip[19].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_19_qs) + ); + + // F[p_20]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[20].de), + .d (hw2reg.ip[20].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_20_qs) + ); + + // F[p_21]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[21].de), + .d (hw2reg.ip[21].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_21_qs) + ); + + // F[p_22]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[22].de), + .d (hw2reg.ip[22].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_22_qs) + ); + + // F[p_23]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[23].de), + .d (hw2reg.ip[23].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_23_qs) + ); + + // F[p_24]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[24].de), + .d (hw2reg.ip[24].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_24_qs) + ); + + // F[p_25]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[25].de), + .d (hw2reg.ip[25].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_25_qs) + ); + + // F[p_26]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[26].de), + .d (hw2reg.ip[26].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_26_qs) + ); + + // F[p_27]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[27].de), + .d (hw2reg.ip[27].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_27_qs) + ); + + // F[p_28]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[28].de), + .d (hw2reg.ip[28].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_28_qs) + ); + + // F[p_29]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[29].de), + .d (hw2reg.ip[29].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_29_qs) + ); + + // F[p_30]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[30].de), + .d (hw2reg.ip[30].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_30_qs) + ); + + // F[p_31]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_0_p_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[31].de), + .d (hw2reg.ip[31].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_0_p_31_qs) + ); + + + // Subregister 1 of Multireg ip + // R[ip_1]: V(False) + // F[p_32]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[32].de), + .d (hw2reg.ip[32].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_32_qs) + ); + + // F[p_33]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[33].de), + .d (hw2reg.ip[33].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_33_qs) + ); + + // F[p_34]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[34].de), + .d (hw2reg.ip[34].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_34_qs) + ); + + // F[p_35]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[35].de), + .d (hw2reg.ip[35].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_35_qs) + ); + + // F[p_36]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[36].de), + .d (hw2reg.ip[36].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_36_qs) + ); + + // F[p_37]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[37].de), + .d (hw2reg.ip[37].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_37_qs) + ); + + // F[p_38]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[38].de), + .d (hw2reg.ip[38].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_38_qs) + ); + + // F[p_39]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[39].de), + .d (hw2reg.ip[39].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_39_qs) + ); + + // F[p_40]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[40].de), + .d (hw2reg.ip[40].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_40_qs) + ); + + // F[p_41]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[41].de), + .d (hw2reg.ip[41].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_41_qs) + ); + + // F[p_42]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[42].de), + .d (hw2reg.ip[42].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_42_qs) + ); + + // F[p_43]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[43].de), + .d (hw2reg.ip[43].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_43_qs) + ); + + // F[p_44]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[44].de), + .d (hw2reg.ip[44].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_44_qs) + ); + + // F[p_45]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[45].de), + .d (hw2reg.ip[45].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_45_qs) + ); + + // F[p_46]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[46].de), + .d (hw2reg.ip[46].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_46_qs) + ); + + // F[p_47]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[47].de), + .d (hw2reg.ip[47].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_47_qs) + ); + + // F[p_48]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[48].de), + .d (hw2reg.ip[48].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_48_qs) + ); + + // F[p_49]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[49].de), + .d (hw2reg.ip[49].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_49_qs) + ); + + // F[p_50]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[50].de), + .d (hw2reg.ip[50].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_50_qs) + ); + + // F[p_51]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[51].de), + .d (hw2reg.ip[51].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_51_qs) + ); + + // F[p_52]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[52].de), + .d (hw2reg.ip[52].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_52_qs) + ); + + // F[p_53]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[53].de), + .d (hw2reg.ip[53].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_53_qs) + ); + + // F[p_54]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[54].de), + .d (hw2reg.ip[54].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_54_qs) + ); + + // F[p_55]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[55].de), + .d (hw2reg.ip[55].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_55_qs) + ); + + // F[p_56]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[56].de), + .d (hw2reg.ip[56].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_56_qs) + ); + + // F[p_57]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[57].de), + .d (hw2reg.ip[57].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_57_qs) + ); + + // F[p_58]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[58].de), + .d (hw2reg.ip[58].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_58_qs) + ); + + // F[p_59]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[59].de), + .d (hw2reg.ip[59].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_59_qs) + ); + + // F[p_60]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[60].de), + .d (hw2reg.ip[60].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_60_qs) + ); + + // F[p_61]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[61].de), + .d (hw2reg.ip[61].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_61_qs) + ); + + // F[p_62]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[62].de), + .d (hw2reg.ip[62].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_62_qs) + ); + + // F[p_63]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_1_p_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[63].de), + .d (hw2reg.ip[63].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_1_p_63_qs) + ); + + + // Subregister 2 of Multireg ip + // R[ip_2]: V(False) + // F[p_64]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[64].de), + .d (hw2reg.ip[64].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_64_qs) + ); + + // F[p_65]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[65].de), + .d (hw2reg.ip[65].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_65_qs) + ); + + // F[p_66]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[66].de), + .d (hw2reg.ip[66].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_66_qs) + ); + + // F[p_67]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[67].de), + .d (hw2reg.ip[67].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_67_qs) + ); + + // F[p_68]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[68].de), + .d (hw2reg.ip[68].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_68_qs) + ); + + // F[p_69]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[69].de), + .d (hw2reg.ip[69].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_69_qs) + ); + + // F[p_70]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[70].de), + .d (hw2reg.ip[70].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_70_qs) + ); + + // F[p_71]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[71].de), + .d (hw2reg.ip[71].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_71_qs) + ); + + // F[p_72]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[72].de), + .d (hw2reg.ip[72].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_72_qs) + ); + + // F[p_73]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[73].de), + .d (hw2reg.ip[73].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_73_qs) + ); + + // F[p_74]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[74].de), + .d (hw2reg.ip[74].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_74_qs) + ); + + // F[p_75]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[75].de), + .d (hw2reg.ip[75].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_75_qs) + ); + + // F[p_76]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[76].de), + .d (hw2reg.ip[76].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_76_qs) + ); + + // F[p_77]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[77].de), + .d (hw2reg.ip[77].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_77_qs) + ); + + // F[p_78]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[78].de), + .d (hw2reg.ip[78].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_78_qs) + ); + + // F[p_79]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[79].de), + .d (hw2reg.ip[79].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_79_qs) + ); + + // F[p_80]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[80].de), + .d (hw2reg.ip[80].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_80_qs) + ); + + // F[p_81]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[81].de), + .d (hw2reg.ip[81].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_81_qs) + ); + + // F[p_82]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[82].de), + .d (hw2reg.ip[82].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_82_qs) + ); + + // F[p_83]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[83].de), + .d (hw2reg.ip[83].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_83_qs) + ); + + // F[p_84]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[84].de), + .d (hw2reg.ip[84].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_84_qs) + ); + + // F[p_85]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[85].de), + .d (hw2reg.ip[85].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_85_qs) + ); + + // F[p_86]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[86].de), + .d (hw2reg.ip[86].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_86_qs) + ); + + // F[p_87]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[87].de), + .d (hw2reg.ip[87].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_87_qs) + ); + + // F[p_88]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[88].de), + .d (hw2reg.ip[88].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_88_qs) + ); + + // F[p_89]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[89].de), + .d (hw2reg.ip[89].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_89_qs) + ); + + // F[p_90]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[90].de), + .d (hw2reg.ip[90].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_90_qs) + ); + + // F[p_91]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[91].de), + .d (hw2reg.ip[91].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_91_qs) + ); + + // F[p_92]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[92].de), + .d (hw2reg.ip[92].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_92_qs) + ); + + // F[p_93]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[93].de), + .d (hw2reg.ip[93].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_93_qs) + ); + + // F[p_94]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[94].de), + .d (hw2reg.ip[94].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_94_qs) + ); + + // F[p_95]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_2_p_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[95].de), + .d (hw2reg.ip[95].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_2_p_95_qs) + ); + + + // Subregister 3 of Multireg ip + // R[ip_3]: V(False) + // F[p_96]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[96].de), + .d (hw2reg.ip[96].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_96_qs) + ); + + // F[p_97]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[97].de), + .d (hw2reg.ip[97].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_97_qs) + ); + + // F[p_98]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[98].de), + .d (hw2reg.ip[98].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_98_qs) + ); + + // F[p_99]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_99 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[99].de), + .d (hw2reg.ip[99].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_99_qs) + ); + + // F[p_100]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_100 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[100].de), + .d (hw2reg.ip[100].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_100_qs) + ); + + // F[p_101]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_101 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[101].de), + .d (hw2reg.ip[101].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_101_qs) + ); + + // F[p_102]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_102 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[102].de), + .d (hw2reg.ip[102].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_102_qs) + ); + + // F[p_103]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_103 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[103].de), + .d (hw2reg.ip[103].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_103_qs) + ); + + // F[p_104]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_104 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[104].de), + .d (hw2reg.ip[104].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_104_qs) + ); + + // F[p_105]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_105 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[105].de), + .d (hw2reg.ip[105].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_105_qs) + ); + + // F[p_106]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_106 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[106].de), + .d (hw2reg.ip[106].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_106_qs) + ); + + // F[p_107]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_107 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[107].de), + .d (hw2reg.ip[107].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_107_qs) + ); + + // F[p_108]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_108 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[108].de), + .d (hw2reg.ip[108].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_108_qs) + ); + + // F[p_109]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_109 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[109].de), + .d (hw2reg.ip[109].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_109_qs) + ); + + // F[p_110]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_110 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[110].de), + .d (hw2reg.ip[110].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_110_qs) + ); + + // F[p_111]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_111 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[111].de), + .d (hw2reg.ip[111].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_111_qs) + ); + + // F[p_112]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_112 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[112].de), + .d (hw2reg.ip[112].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_112_qs) + ); + + // F[p_113]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_113 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[113].de), + .d (hw2reg.ip[113].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_113_qs) + ); + + // F[p_114]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_114 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[114].de), + .d (hw2reg.ip[114].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_114_qs) + ); + + // F[p_115]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_115 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[115].de), + .d (hw2reg.ip[115].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_115_qs) + ); + + // F[p_116]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_116 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[116].de), + .d (hw2reg.ip[116].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_116_qs) + ); + + // F[p_117]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_117 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[117].de), + .d (hw2reg.ip[117].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_117_qs) + ); + + // F[p_118]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_118 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[118].de), + .d (hw2reg.ip[118].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_118_qs) + ); + + // F[p_119]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_119 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[119].de), + .d (hw2reg.ip[119].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_119_qs) + ); + + // F[p_120]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_120 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[120].de), + .d (hw2reg.ip[120].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_120_qs) + ); + + // F[p_121]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_121 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[121].de), + .d (hw2reg.ip[121].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_121_qs) + ); + + // F[p_122]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_122 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[122].de), + .d (hw2reg.ip[122].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_122_qs) + ); + + // F[p_123]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_123 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[123].de), + .d (hw2reg.ip[123].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_123_qs) + ); + + // F[p_124]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_124 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[124].de), + .d (hw2reg.ip[124].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_124_qs) + ); + + // F[p_125]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_125 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[125].de), + .d (hw2reg.ip[125].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_125_qs) + ); + + // F[p_126]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_126 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[126].de), + .d (hw2reg.ip[126].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_126_qs) + ); + + // F[p_127]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_3_p_127 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[127].de), + .d (hw2reg.ip[127].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_3_p_127_qs) + ); + + + // Subregister 4 of Multireg ip + // R[ip_4]: V(False) + // F[p_128]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_128 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[128].de), + .d (hw2reg.ip[128].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_128_qs) + ); + + // F[p_129]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_129 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[129].de), + .d (hw2reg.ip[129].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_129_qs) + ); + + // F[p_130]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_130 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[130].de), + .d (hw2reg.ip[130].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_130_qs) + ); + + // F[p_131]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_131 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[131].de), + .d (hw2reg.ip[131].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_131_qs) + ); + + // F[p_132]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_132 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[132].de), + .d (hw2reg.ip[132].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_132_qs) + ); + + // F[p_133]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_133 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[133].de), + .d (hw2reg.ip[133].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_133_qs) + ); + + // F[p_134]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_134 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[134].de), + .d (hw2reg.ip[134].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_134_qs) + ); + + // F[p_135]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_135 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[135].de), + .d (hw2reg.ip[135].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_135_qs) + ); + + // F[p_136]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_136 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[136].de), + .d (hw2reg.ip[136].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_136_qs) + ); + + // F[p_137]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_137 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[137].de), + .d (hw2reg.ip[137].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_137_qs) + ); + + // F[p_138]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_138 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[138].de), + .d (hw2reg.ip[138].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_138_qs) + ); + + // F[p_139]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_139 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[139].de), + .d (hw2reg.ip[139].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_139_qs) + ); + + // F[p_140]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_140 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[140].de), + .d (hw2reg.ip[140].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_140_qs) + ); + + // F[p_141]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_141 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[141].de), + .d (hw2reg.ip[141].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_141_qs) + ); + + // F[p_142]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_142 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[142].de), + .d (hw2reg.ip[142].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_142_qs) + ); + + // F[p_143]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_143 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[143].de), + .d (hw2reg.ip[143].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_143_qs) + ); + + // F[p_144]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_144 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[144].de), + .d (hw2reg.ip[144].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_144_qs) + ); + + // F[p_145]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_145 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[145].de), + .d (hw2reg.ip[145].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_145_qs) + ); + + // F[p_146]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_146 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[146].de), + .d (hw2reg.ip[146].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_146_qs) + ); + + // F[p_147]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_147 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[147].de), + .d (hw2reg.ip[147].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_147_qs) + ); + + // F[p_148]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_148 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[148].de), + .d (hw2reg.ip[148].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_148_qs) + ); + + // F[p_149]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_149 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[149].de), + .d (hw2reg.ip[149].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_149_qs) + ); + + // F[p_150]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_150 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[150].de), + .d (hw2reg.ip[150].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_150_qs) + ); + + // F[p_151]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_151 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[151].de), + .d (hw2reg.ip[151].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_151_qs) + ); + + // F[p_152]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_152 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[152].de), + .d (hw2reg.ip[152].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_152_qs) + ); + + // F[p_153]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_153 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[153].de), + .d (hw2reg.ip[153].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_153_qs) + ); + + // F[p_154]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_154 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[154].de), + .d (hw2reg.ip[154].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_154_qs) + ); + + // F[p_155]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_155 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[155].de), + .d (hw2reg.ip[155].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_155_qs) + ); + + // F[p_156]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_156 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[156].de), + .d (hw2reg.ip[156].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_156_qs) + ); + + // F[p_157]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_157 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[157].de), + .d (hw2reg.ip[157].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_157_qs) + ); + + // F[p_158]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_158 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[158].de), + .d (hw2reg.ip[158].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_158_qs) + ); + + // F[p_159]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_4_p_159 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[159].de), + .d (hw2reg.ip[159].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_4_p_159_qs) + ); + + + // Subregister 5 of Multireg ip + // R[ip_5]: V(False) + // F[p_160]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_5_p_160 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[160].de), + .d (hw2reg.ip[160].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_5_p_160_qs) + ); + + // F[p_161]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_5_p_161 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[161].de), + .d (hw2reg.ip[161].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_5_p_161_qs) + ); + + // F[p_162]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRO), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ip_5_p_162 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (1'b0), + .wd ('0), + + // from internal hardware + .de (hw2reg.ip[162].de), + .d (hw2reg.ip[162].d), + + // to internal hardware + .qe (), + .q (), + .ds (), + + // to register interface (read) + .qs (ip_5_p_162_qs) + ); + + + // Subregister 0 of Multireg ie0 + // R[ie0_0]: V(False) + // F[e_0]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[0].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_0_qs) + ); + + // F[e_1]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_1 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[1].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_1_qs) + ); + + // F[e_2]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_2 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[2].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_2_qs) + ); + + // F[e_3]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_3 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[3].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_3_qs) + ); + + // F[e_4]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_4 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[4].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_4_qs) + ); + + // F[e_5]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_5 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[5].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_5_qs) + ); + + // F[e_6]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_6 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[6].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_6_qs) + ); + + // F[e_7]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_7 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[7].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_7_qs) + ); + + // F[e_8]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_8 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[8].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_8_qs) + ); + + // F[e_9]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_9 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[9].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_9_qs) + ); + + // F[e_10]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_10 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[10].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_10_qs) + ); + + // F[e_11]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_11 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[11].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_11_qs) + ); + + // F[e_12]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_12 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[12].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_12_qs) + ); + + // F[e_13]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_13 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[13].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_13_qs) + ); + + // F[e_14]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_14 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[14].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_14_qs) + ); + + // F[e_15]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_15 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[15].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_15_qs) + ); + + // F[e_16]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_16 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[16].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_16_qs) + ); + + // F[e_17]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_17 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[17].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_17_qs) + ); + + // F[e_18]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_18 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[18].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_18_qs) + ); + + // F[e_19]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_19 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[19].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_19_qs) + ); + + // F[e_20]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_20 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[20].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_20_qs) + ); + + // F[e_21]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_21 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[21].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_21_qs) + ); + + // F[e_22]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_22 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[22].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_22_qs) + ); + + // F[e_23]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_23 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[23].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_23_qs) + ); + + // F[e_24]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_24 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[24].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_24_qs) + ); + + // F[e_25]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_25 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[25].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_25_qs) + ); + + // F[e_26]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_26 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[26].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_26_qs) + ); + + // F[e_27]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_27 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[27].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_27_qs) + ); + + // F[e_28]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_28 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[28].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_28_qs) + ); + + // F[e_29]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_29 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[29].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_29_qs) + ); + + // F[e_30]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_30 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[30].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_30_qs) + ); + + // F[e_31]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_0_e_31 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_0_we), + .wd (ie0_0_e_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[31].q), + .ds (), + + // to register interface (read) + .qs (ie0_0_e_31_qs) + ); + + + // Subregister 1 of Multireg ie0 + // R[ie0_1]: V(False) + // F[e_32]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_32 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_32_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[32].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_32_qs) + ); + + // F[e_33]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_33 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_33_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[33].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_33_qs) + ); + + // F[e_34]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_34 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_34_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[34].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_34_qs) + ); + + // F[e_35]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_35 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_35_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[35].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_35_qs) + ); + + // F[e_36]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_36 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_36_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[36].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_36_qs) + ); + + // F[e_37]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_37 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_37_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[37].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_37_qs) + ); + + // F[e_38]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_38 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_38_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[38].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_38_qs) + ); + + // F[e_39]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_39 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_39_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[39].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_39_qs) + ); + + // F[e_40]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_40 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_40_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[40].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_40_qs) + ); + + // F[e_41]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_41 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_41_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[41].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_41_qs) + ); + + // F[e_42]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_42 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_42_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[42].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_42_qs) + ); + + // F[e_43]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_43 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_43_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[43].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_43_qs) + ); + + // F[e_44]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_44 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_44_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[44].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_44_qs) + ); + + // F[e_45]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_45 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_45_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[45].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_45_qs) + ); + + // F[e_46]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_46 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_46_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[46].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_46_qs) + ); + + // F[e_47]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_47 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_47_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[47].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_47_qs) + ); + + // F[e_48]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_48 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_48_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[48].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_48_qs) + ); + + // F[e_49]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_49 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_49_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[49].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_49_qs) + ); + + // F[e_50]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_50 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_50_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[50].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_50_qs) + ); + + // F[e_51]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_51 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_51_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[51].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_51_qs) + ); + + // F[e_52]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_52 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_52_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[52].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_52_qs) + ); + + // F[e_53]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_53 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_53_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[53].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_53_qs) + ); + + // F[e_54]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_54 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_54_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[54].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_54_qs) + ); + + // F[e_55]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_55 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_55_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[55].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_55_qs) + ); + + // F[e_56]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_56 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_56_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[56].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_56_qs) + ); + + // F[e_57]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_57 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_57_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[57].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_57_qs) + ); + + // F[e_58]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_58 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_58_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[58].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_58_qs) + ); + + // F[e_59]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_59 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_59_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[59].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_59_qs) + ); + + // F[e_60]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_60 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_60_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[60].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_60_qs) + ); + + // F[e_61]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_61 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_61_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[61].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_61_qs) + ); + + // F[e_62]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_62 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_62_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[62].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_62_qs) + ); + + // F[e_63]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_1_e_63 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_1_we), + .wd (ie0_1_e_63_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[63].q), + .ds (), + + // to register interface (read) + .qs (ie0_1_e_63_qs) + ); + + + // Subregister 2 of Multireg ie0 + // R[ie0_2]: V(False) + // F[e_64]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_64 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_64_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[64].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_64_qs) + ); + + // F[e_65]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_65 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_65_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[65].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_65_qs) + ); + + // F[e_66]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_66 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_66_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[66].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_66_qs) + ); + + // F[e_67]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_67 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_67_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[67].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_67_qs) + ); + + // F[e_68]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_68 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_68_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[68].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_68_qs) + ); + + // F[e_69]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_69 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_69_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[69].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_69_qs) + ); + + // F[e_70]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_70 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_70_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[70].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_70_qs) + ); + + // F[e_71]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_71 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_71_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[71].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_71_qs) + ); + + // F[e_72]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_72 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_72_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[72].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_72_qs) + ); + + // F[e_73]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_73 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_73_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[73].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_73_qs) + ); + + // F[e_74]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_74 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_74_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[74].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_74_qs) + ); + + // F[e_75]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_75 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_75_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[75].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_75_qs) + ); + + // F[e_76]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_76 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_76_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[76].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_76_qs) + ); + + // F[e_77]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_77 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_77_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[77].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_77_qs) + ); + + // F[e_78]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_78 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_78_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[78].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_78_qs) + ); + + // F[e_79]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_79 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_79_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[79].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_79_qs) + ); + + // F[e_80]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_80 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_80_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[80].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_80_qs) + ); + + // F[e_81]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_81 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_81_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[81].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_81_qs) + ); + + // F[e_82]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_82 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_82_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[82].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_82_qs) + ); + + // F[e_83]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_83 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_83_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[83].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_83_qs) + ); + + // F[e_84]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_84 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_84_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[84].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_84_qs) + ); + + // F[e_85]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_85 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_85_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[85].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_85_qs) + ); + + // F[e_86]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_86 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_86_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[86].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_86_qs) + ); + + // F[e_87]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_87 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_87_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[87].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_87_qs) + ); + + // F[e_88]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_88 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_88_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[88].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_88_qs) + ); + + // F[e_89]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_89 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_89_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[89].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_89_qs) + ); + + // F[e_90]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_90 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_90_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[90].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_90_qs) + ); + + // F[e_91]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_91 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_91_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[91].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_91_qs) + ); + + // F[e_92]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_92 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_92_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[92].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_92_qs) + ); + + // F[e_93]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_93 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_93_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[93].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_93_qs) + ); + + // F[e_94]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_94 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_94_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[94].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_94_qs) + ); + + // F[e_95]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_2_e_95 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_2_we), + .wd (ie0_2_e_95_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[95].q), + .ds (), + + // to register interface (read) + .qs (ie0_2_e_95_qs) + ); + + + // Subregister 3 of Multireg ie0 + // R[ie0_3]: V(False) + // F[e_96]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_96 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_96_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[96].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_96_qs) + ); + + // F[e_97]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_97 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_97_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[97].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_97_qs) + ); + + // F[e_98]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_98 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_98_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[98].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_98_qs) + ); + + // F[e_99]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_99 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_99_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[99].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_99_qs) + ); + + // F[e_100]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_100 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_100_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[100].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_100_qs) + ); + + // F[e_101]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_101 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_101_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[101].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_101_qs) + ); + + // F[e_102]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_102 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_102_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[102].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_102_qs) + ); + + // F[e_103]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_103 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_103_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[103].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_103_qs) + ); + + // F[e_104]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_104 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_104_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[104].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_104_qs) + ); + + // F[e_105]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_105 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_105_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[105].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_105_qs) + ); + + // F[e_106]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_106 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_106_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[106].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_106_qs) + ); + + // F[e_107]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_107 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_107_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[107].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_107_qs) + ); + + // F[e_108]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_108 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_108_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[108].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_108_qs) + ); + + // F[e_109]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_109 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_109_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[109].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_109_qs) + ); + + // F[e_110]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_110 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_110_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[110].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_110_qs) + ); + + // F[e_111]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_111 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_111_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[111].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_111_qs) + ); + + // F[e_112]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_112 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_112_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[112].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_112_qs) + ); + + // F[e_113]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_113 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_113_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[113].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_113_qs) + ); + + // F[e_114]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_114 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_114_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[114].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_114_qs) + ); + + // F[e_115]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_115 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_115_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[115].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_115_qs) + ); + + // F[e_116]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_116 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_116_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[116].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_116_qs) + ); + + // F[e_117]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_117 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_117_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[117].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_117_qs) + ); + + // F[e_118]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_118 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_118_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[118].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_118_qs) + ); + + // F[e_119]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_119 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_119_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[119].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_119_qs) + ); + + // F[e_120]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_120 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_120_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[120].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_120_qs) + ); + + // F[e_121]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_121 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_121_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[121].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_121_qs) + ); + + // F[e_122]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_122 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_122_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[122].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_122_qs) + ); + + // F[e_123]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_123 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_123_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[123].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_123_qs) + ); + + // F[e_124]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_124 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_124_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[124].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_124_qs) + ); + + // F[e_125]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_125 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_125_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[125].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_125_qs) + ); + + // F[e_126]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_126 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_126_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[126].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_126_qs) + ); + + // F[e_127]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_3_e_127 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_3_we), + .wd (ie0_3_e_127_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[127].q), + .ds (), + + // to register interface (read) + .qs (ie0_3_e_127_qs) + ); + + + // Subregister 4 of Multireg ie0 + // R[ie0_4]: V(False) + // F[e_128]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_128 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_128_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[128].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_128_qs) + ); + + // F[e_129]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_129 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_129_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[129].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_129_qs) + ); + + // F[e_130]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_130 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_130_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[130].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_130_qs) + ); + + // F[e_131]: 3:3 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_131 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_131_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[131].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_131_qs) + ); + + // F[e_132]: 4:4 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_132 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_132_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[132].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_132_qs) + ); + + // F[e_133]: 5:5 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_133 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_133_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[133].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_133_qs) + ); + + // F[e_134]: 6:6 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_134 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_134_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[134].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_134_qs) + ); + + // F[e_135]: 7:7 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_135 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_135_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[135].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_135_qs) + ); + + // F[e_136]: 8:8 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_136 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_136_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[136].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_136_qs) + ); + + // F[e_137]: 9:9 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_137 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_137_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[137].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_137_qs) + ); + + // F[e_138]: 10:10 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_138 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_138_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[138].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_138_qs) + ); + + // F[e_139]: 11:11 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_139 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_139_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[139].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_139_qs) + ); + + // F[e_140]: 12:12 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_140 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_140_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[140].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_140_qs) + ); + + // F[e_141]: 13:13 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_141 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_141_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[141].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_141_qs) + ); + + // F[e_142]: 14:14 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_142 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_142_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[142].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_142_qs) + ); + + // F[e_143]: 15:15 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_143 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_143_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[143].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_143_qs) + ); + + // F[e_144]: 16:16 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_144 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_144_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[144].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_144_qs) + ); + + // F[e_145]: 17:17 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_145 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_145_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[145].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_145_qs) + ); + + // F[e_146]: 18:18 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_146 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_146_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[146].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_146_qs) + ); + + // F[e_147]: 19:19 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_147 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_147_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[147].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_147_qs) + ); + + // F[e_148]: 20:20 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_148 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_148_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[148].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_148_qs) + ); + + // F[e_149]: 21:21 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_149 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_149_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[149].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_149_qs) + ); + + // F[e_150]: 22:22 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_150 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_150_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[150].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_150_qs) + ); + + // F[e_151]: 23:23 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_151 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_151_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[151].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_151_qs) + ); + + // F[e_152]: 24:24 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_152 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_152_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[152].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_152_qs) + ); + + // F[e_153]: 25:25 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_153 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_153_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[153].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_153_qs) + ); + + // F[e_154]: 26:26 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_154 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_154_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[154].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_154_qs) + ); + + // F[e_155]: 27:27 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_155 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_155_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[155].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_155_qs) + ); + + // F[e_156]: 28:28 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_156 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_156_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[156].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_156_qs) + ); + + // F[e_157]: 29:29 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_157 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_157_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[157].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_157_qs) + ); + + // F[e_158]: 30:30 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_158 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_158_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[158].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_158_qs) + ); + + // F[e_159]: 31:31 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_4_e_159 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_4_we), + .wd (ie0_4_e_159_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[159].q), + .ds (), + + // to register interface (read) + .qs (ie0_4_e_159_qs) + ); + + + // Subregister 5 of Multireg ie0 + // R[ie0_5]: V(False) + // F[e_160]: 0:0 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_5_e_160 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_5_we), + .wd (ie0_5_e_160_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[160].q), + .ds (), + + // to register interface (read) + .qs (ie0_5_e_160_qs) + ); + + // F[e_161]: 1:1 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_5_e_161 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_5_we), + .wd (ie0_5_e_161_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[161].q), + .ds (), + + // to register interface (read) + .qs (ie0_5_e_161_qs) + ); + + // F[e_162]: 2:2 + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_ie0_5_e_162 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (ie0_5_we), + .wd (ie0_5_e_162_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.ie0[162].q), + .ds (), + + // to register interface (read) + .qs (ie0_5_e_162_qs) + ); + + + // R[threshold0]: V(False) + prim_subreg #( + .DW (2), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (2'h0), + .Mubi (1'b0) + ) u_threshold0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (threshold0_we), + .wd (threshold0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.threshold0.q), + .ds (), + + // to register interface (read) + .qs (threshold0_qs) + ); + + + // R[cc0]: V(True) + logic cc0_qe; + logic [0:0] cc0_flds_we; + assign cc0_qe = &cc0_flds_we; + prim_subreg_ext #( + .DW (8) + ) u_cc0 ( + .re (cc0_re), + .we (cc0_we), + .wd (cc0_wd), + .d (hw2reg.cc0.d), + .qre (reg2hw.cc0.re), + .qe (cc0_flds_we[0]), + .q (reg2hw.cc0.q), + .ds (), + .qs (cc0_qs) + ); + assign reg2hw.cc0.qe = cc0_qe; + + + // R[msip0]: V(False) + prim_subreg #( + .DW (1), + .SwAccess(prim_subreg_pkg::SwAccessRW), + .RESVAL (1'h0), + .Mubi (1'b0) + ) u_msip0 ( + .clk_i (clk_i), + .rst_ni (rst_ni), + + // from register interface + .we (msip0_we), + .wd (msip0_wd), + + // from internal hardware + .de (1'b0), + .d ('0), + + // to internal hardware + .qe (), + .q (reg2hw.msip0.q), + .ds (), + + // to register interface (read) + .qs (msip0_qs) + ); + + + // R[alert_test]: V(True) + logic alert_test_qe; + logic [0:0] alert_test_flds_we; + assign alert_test_qe = &alert_test_flds_we; + prim_subreg_ext #( + .DW (1) + ) u_alert_test ( + .re (1'b0), + .we (alert_test_we), + .wd (alert_test_wd), + .d ('0), + .qre (), + .qe (alert_test_flds_we[0]), + .q (reg2hw.alert_test.q), + .ds (), + .qs () + ); + assign reg2hw.alert_test.qe = alert_test_qe; + + + + logic [178:0] addr_hit; + always_comb begin + addr_hit[ 0] = (reg_addr == RV_PLIC_PRIO_0_OFFSET); + addr_hit[ 1] = (reg_addr == RV_PLIC_PRIO_1_OFFSET); + addr_hit[ 2] = (reg_addr == RV_PLIC_PRIO_2_OFFSET); + addr_hit[ 3] = (reg_addr == RV_PLIC_PRIO_3_OFFSET); + addr_hit[ 4] = (reg_addr == RV_PLIC_PRIO_4_OFFSET); + addr_hit[ 5] = (reg_addr == RV_PLIC_PRIO_5_OFFSET); + addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO_6_OFFSET); + addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO_7_OFFSET); + addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO_8_OFFSET); + addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO_9_OFFSET); + addr_hit[ 10] = (reg_addr == RV_PLIC_PRIO_10_OFFSET); + addr_hit[ 11] = (reg_addr == RV_PLIC_PRIO_11_OFFSET); + addr_hit[ 12] = (reg_addr == RV_PLIC_PRIO_12_OFFSET); + addr_hit[ 13] = (reg_addr == RV_PLIC_PRIO_13_OFFSET); + addr_hit[ 14] = (reg_addr == RV_PLIC_PRIO_14_OFFSET); + addr_hit[ 15] = (reg_addr == RV_PLIC_PRIO_15_OFFSET); + addr_hit[ 16] = (reg_addr == RV_PLIC_PRIO_16_OFFSET); + addr_hit[ 17] = (reg_addr == RV_PLIC_PRIO_17_OFFSET); + addr_hit[ 18] = (reg_addr == RV_PLIC_PRIO_18_OFFSET); + addr_hit[ 19] = (reg_addr == RV_PLIC_PRIO_19_OFFSET); + addr_hit[ 20] = (reg_addr == RV_PLIC_PRIO_20_OFFSET); + addr_hit[ 21] = (reg_addr == RV_PLIC_PRIO_21_OFFSET); + addr_hit[ 22] = (reg_addr == RV_PLIC_PRIO_22_OFFSET); + addr_hit[ 23] = (reg_addr == RV_PLIC_PRIO_23_OFFSET); + addr_hit[ 24] = (reg_addr == RV_PLIC_PRIO_24_OFFSET); + addr_hit[ 25] = (reg_addr == RV_PLIC_PRIO_25_OFFSET); + addr_hit[ 26] = (reg_addr == RV_PLIC_PRIO_26_OFFSET); + addr_hit[ 27] = (reg_addr == RV_PLIC_PRIO_27_OFFSET); + addr_hit[ 28] = (reg_addr == RV_PLIC_PRIO_28_OFFSET); + addr_hit[ 29] = (reg_addr == RV_PLIC_PRIO_29_OFFSET); + addr_hit[ 30] = (reg_addr == RV_PLIC_PRIO_30_OFFSET); + addr_hit[ 31] = (reg_addr == RV_PLIC_PRIO_31_OFFSET); + addr_hit[ 32] = (reg_addr == RV_PLIC_PRIO_32_OFFSET); + addr_hit[ 33] = (reg_addr == RV_PLIC_PRIO_33_OFFSET); + addr_hit[ 34] = (reg_addr == RV_PLIC_PRIO_34_OFFSET); + addr_hit[ 35] = (reg_addr == RV_PLIC_PRIO_35_OFFSET); + addr_hit[ 36] = (reg_addr == RV_PLIC_PRIO_36_OFFSET); + addr_hit[ 37] = (reg_addr == RV_PLIC_PRIO_37_OFFSET); + addr_hit[ 38] = (reg_addr == RV_PLIC_PRIO_38_OFFSET); + addr_hit[ 39] = (reg_addr == RV_PLIC_PRIO_39_OFFSET); + addr_hit[ 40] = (reg_addr == RV_PLIC_PRIO_40_OFFSET); + addr_hit[ 41] = (reg_addr == RV_PLIC_PRIO_41_OFFSET); + addr_hit[ 42] = (reg_addr == RV_PLIC_PRIO_42_OFFSET); + addr_hit[ 43] = (reg_addr == RV_PLIC_PRIO_43_OFFSET); + addr_hit[ 44] = (reg_addr == RV_PLIC_PRIO_44_OFFSET); + addr_hit[ 45] = (reg_addr == RV_PLIC_PRIO_45_OFFSET); + addr_hit[ 46] = (reg_addr == RV_PLIC_PRIO_46_OFFSET); + addr_hit[ 47] = (reg_addr == RV_PLIC_PRIO_47_OFFSET); + addr_hit[ 48] = (reg_addr == RV_PLIC_PRIO_48_OFFSET); + addr_hit[ 49] = (reg_addr == RV_PLIC_PRIO_49_OFFSET); + addr_hit[ 50] = (reg_addr == RV_PLIC_PRIO_50_OFFSET); + addr_hit[ 51] = (reg_addr == RV_PLIC_PRIO_51_OFFSET); + addr_hit[ 52] = (reg_addr == RV_PLIC_PRIO_52_OFFSET); + addr_hit[ 53] = (reg_addr == RV_PLIC_PRIO_53_OFFSET); + addr_hit[ 54] = (reg_addr == RV_PLIC_PRIO_54_OFFSET); + addr_hit[ 55] = (reg_addr == RV_PLIC_PRIO_55_OFFSET); + addr_hit[ 56] = (reg_addr == RV_PLIC_PRIO_56_OFFSET); + addr_hit[ 57] = (reg_addr == RV_PLIC_PRIO_57_OFFSET); + addr_hit[ 58] = (reg_addr == RV_PLIC_PRIO_58_OFFSET); + addr_hit[ 59] = (reg_addr == RV_PLIC_PRIO_59_OFFSET); + addr_hit[ 60] = (reg_addr == RV_PLIC_PRIO_60_OFFSET); + addr_hit[ 61] = (reg_addr == RV_PLIC_PRIO_61_OFFSET); + addr_hit[ 62] = (reg_addr == RV_PLIC_PRIO_62_OFFSET); + addr_hit[ 63] = (reg_addr == RV_PLIC_PRIO_63_OFFSET); + addr_hit[ 64] = (reg_addr == RV_PLIC_PRIO_64_OFFSET); + addr_hit[ 65] = (reg_addr == RV_PLIC_PRIO_65_OFFSET); + addr_hit[ 66] = (reg_addr == RV_PLIC_PRIO_66_OFFSET); + addr_hit[ 67] = (reg_addr == RV_PLIC_PRIO_67_OFFSET); + addr_hit[ 68] = (reg_addr == RV_PLIC_PRIO_68_OFFSET); + addr_hit[ 69] = (reg_addr == RV_PLIC_PRIO_69_OFFSET); + addr_hit[ 70] = (reg_addr == RV_PLIC_PRIO_70_OFFSET); + addr_hit[ 71] = (reg_addr == RV_PLIC_PRIO_71_OFFSET); + addr_hit[ 72] = (reg_addr == RV_PLIC_PRIO_72_OFFSET); + addr_hit[ 73] = (reg_addr == RV_PLIC_PRIO_73_OFFSET); + addr_hit[ 74] = (reg_addr == RV_PLIC_PRIO_74_OFFSET); + addr_hit[ 75] = (reg_addr == RV_PLIC_PRIO_75_OFFSET); + addr_hit[ 76] = (reg_addr == RV_PLIC_PRIO_76_OFFSET); + addr_hit[ 77] = (reg_addr == RV_PLIC_PRIO_77_OFFSET); + addr_hit[ 78] = (reg_addr == RV_PLIC_PRIO_78_OFFSET); + addr_hit[ 79] = (reg_addr == RV_PLIC_PRIO_79_OFFSET); + addr_hit[ 80] = (reg_addr == RV_PLIC_PRIO_80_OFFSET); + addr_hit[ 81] = (reg_addr == RV_PLIC_PRIO_81_OFFSET); + addr_hit[ 82] = (reg_addr == RV_PLIC_PRIO_82_OFFSET); + addr_hit[ 83] = (reg_addr == RV_PLIC_PRIO_83_OFFSET); + addr_hit[ 84] = (reg_addr == RV_PLIC_PRIO_84_OFFSET); + addr_hit[ 85] = (reg_addr == RV_PLIC_PRIO_85_OFFSET); + addr_hit[ 86] = (reg_addr == RV_PLIC_PRIO_86_OFFSET); + addr_hit[ 87] = (reg_addr == RV_PLIC_PRIO_87_OFFSET); + addr_hit[ 88] = (reg_addr == RV_PLIC_PRIO_88_OFFSET); + addr_hit[ 89] = (reg_addr == RV_PLIC_PRIO_89_OFFSET); + addr_hit[ 90] = (reg_addr == RV_PLIC_PRIO_90_OFFSET); + addr_hit[ 91] = (reg_addr == RV_PLIC_PRIO_91_OFFSET); + addr_hit[ 92] = (reg_addr == RV_PLIC_PRIO_92_OFFSET); + addr_hit[ 93] = (reg_addr == RV_PLIC_PRIO_93_OFFSET); + addr_hit[ 94] = (reg_addr == RV_PLIC_PRIO_94_OFFSET); + addr_hit[ 95] = (reg_addr == RV_PLIC_PRIO_95_OFFSET); + addr_hit[ 96] = (reg_addr == RV_PLIC_PRIO_96_OFFSET); + addr_hit[ 97] = (reg_addr == RV_PLIC_PRIO_97_OFFSET); + addr_hit[ 98] = (reg_addr == RV_PLIC_PRIO_98_OFFSET); + addr_hit[ 99] = (reg_addr == RV_PLIC_PRIO_99_OFFSET); + addr_hit[100] = (reg_addr == RV_PLIC_PRIO_100_OFFSET); + addr_hit[101] = (reg_addr == RV_PLIC_PRIO_101_OFFSET); + addr_hit[102] = (reg_addr == RV_PLIC_PRIO_102_OFFSET); + addr_hit[103] = (reg_addr == RV_PLIC_PRIO_103_OFFSET); + addr_hit[104] = (reg_addr == RV_PLIC_PRIO_104_OFFSET); + addr_hit[105] = (reg_addr == RV_PLIC_PRIO_105_OFFSET); + addr_hit[106] = (reg_addr == RV_PLIC_PRIO_106_OFFSET); + addr_hit[107] = (reg_addr == RV_PLIC_PRIO_107_OFFSET); + addr_hit[108] = (reg_addr == RV_PLIC_PRIO_108_OFFSET); + addr_hit[109] = (reg_addr == RV_PLIC_PRIO_109_OFFSET); + addr_hit[110] = (reg_addr == RV_PLIC_PRIO_110_OFFSET); + addr_hit[111] = (reg_addr == RV_PLIC_PRIO_111_OFFSET); + addr_hit[112] = (reg_addr == RV_PLIC_PRIO_112_OFFSET); + addr_hit[113] = (reg_addr == RV_PLIC_PRIO_113_OFFSET); + addr_hit[114] = (reg_addr == RV_PLIC_PRIO_114_OFFSET); + addr_hit[115] = (reg_addr == RV_PLIC_PRIO_115_OFFSET); + addr_hit[116] = (reg_addr == RV_PLIC_PRIO_116_OFFSET); + addr_hit[117] = (reg_addr == RV_PLIC_PRIO_117_OFFSET); + addr_hit[118] = (reg_addr == RV_PLIC_PRIO_118_OFFSET); + addr_hit[119] = (reg_addr == RV_PLIC_PRIO_119_OFFSET); + addr_hit[120] = (reg_addr == RV_PLIC_PRIO_120_OFFSET); + addr_hit[121] = (reg_addr == RV_PLIC_PRIO_121_OFFSET); + addr_hit[122] = (reg_addr == RV_PLIC_PRIO_122_OFFSET); + addr_hit[123] = (reg_addr == RV_PLIC_PRIO_123_OFFSET); + addr_hit[124] = (reg_addr == RV_PLIC_PRIO_124_OFFSET); + addr_hit[125] = (reg_addr == RV_PLIC_PRIO_125_OFFSET); + addr_hit[126] = (reg_addr == RV_PLIC_PRIO_126_OFFSET); + addr_hit[127] = (reg_addr == RV_PLIC_PRIO_127_OFFSET); + addr_hit[128] = (reg_addr == RV_PLIC_PRIO_128_OFFSET); + addr_hit[129] = (reg_addr == RV_PLIC_PRIO_129_OFFSET); + addr_hit[130] = (reg_addr == RV_PLIC_PRIO_130_OFFSET); + addr_hit[131] = (reg_addr == RV_PLIC_PRIO_131_OFFSET); + addr_hit[132] = (reg_addr == RV_PLIC_PRIO_132_OFFSET); + addr_hit[133] = (reg_addr == RV_PLIC_PRIO_133_OFFSET); + addr_hit[134] = (reg_addr == RV_PLIC_PRIO_134_OFFSET); + addr_hit[135] = (reg_addr == RV_PLIC_PRIO_135_OFFSET); + addr_hit[136] = (reg_addr == RV_PLIC_PRIO_136_OFFSET); + addr_hit[137] = (reg_addr == RV_PLIC_PRIO_137_OFFSET); + addr_hit[138] = (reg_addr == RV_PLIC_PRIO_138_OFFSET); + addr_hit[139] = (reg_addr == RV_PLIC_PRIO_139_OFFSET); + addr_hit[140] = (reg_addr == RV_PLIC_PRIO_140_OFFSET); + addr_hit[141] = (reg_addr == RV_PLIC_PRIO_141_OFFSET); + addr_hit[142] = (reg_addr == RV_PLIC_PRIO_142_OFFSET); + addr_hit[143] = (reg_addr == RV_PLIC_PRIO_143_OFFSET); + addr_hit[144] = (reg_addr == RV_PLIC_PRIO_144_OFFSET); + addr_hit[145] = (reg_addr == RV_PLIC_PRIO_145_OFFSET); + addr_hit[146] = (reg_addr == RV_PLIC_PRIO_146_OFFSET); + addr_hit[147] = (reg_addr == RV_PLIC_PRIO_147_OFFSET); + addr_hit[148] = (reg_addr == RV_PLIC_PRIO_148_OFFSET); + addr_hit[149] = (reg_addr == RV_PLIC_PRIO_149_OFFSET); + addr_hit[150] = (reg_addr == RV_PLIC_PRIO_150_OFFSET); + addr_hit[151] = (reg_addr == RV_PLIC_PRIO_151_OFFSET); + addr_hit[152] = (reg_addr == RV_PLIC_PRIO_152_OFFSET); + addr_hit[153] = (reg_addr == RV_PLIC_PRIO_153_OFFSET); + addr_hit[154] = (reg_addr == RV_PLIC_PRIO_154_OFFSET); + addr_hit[155] = (reg_addr == RV_PLIC_PRIO_155_OFFSET); + addr_hit[156] = (reg_addr == RV_PLIC_PRIO_156_OFFSET); + addr_hit[157] = (reg_addr == RV_PLIC_PRIO_157_OFFSET); + addr_hit[158] = (reg_addr == RV_PLIC_PRIO_158_OFFSET); + addr_hit[159] = (reg_addr == RV_PLIC_PRIO_159_OFFSET); + addr_hit[160] = (reg_addr == RV_PLIC_PRIO_160_OFFSET); + addr_hit[161] = (reg_addr == RV_PLIC_PRIO_161_OFFSET); + addr_hit[162] = (reg_addr == RV_PLIC_PRIO_162_OFFSET); + addr_hit[163] = (reg_addr == RV_PLIC_IP_0_OFFSET); + addr_hit[164] = (reg_addr == RV_PLIC_IP_1_OFFSET); + addr_hit[165] = (reg_addr == RV_PLIC_IP_2_OFFSET); + addr_hit[166] = (reg_addr == RV_PLIC_IP_3_OFFSET); + addr_hit[167] = (reg_addr == RV_PLIC_IP_4_OFFSET); + addr_hit[168] = (reg_addr == RV_PLIC_IP_5_OFFSET); + addr_hit[169] = (reg_addr == RV_PLIC_IE0_0_OFFSET); + addr_hit[170] = (reg_addr == RV_PLIC_IE0_1_OFFSET); + addr_hit[171] = (reg_addr == RV_PLIC_IE0_2_OFFSET); + addr_hit[172] = (reg_addr == RV_PLIC_IE0_3_OFFSET); + addr_hit[173] = (reg_addr == RV_PLIC_IE0_4_OFFSET); + addr_hit[174] = (reg_addr == RV_PLIC_IE0_5_OFFSET); + addr_hit[175] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET); + addr_hit[176] = (reg_addr == RV_PLIC_CC0_OFFSET); + addr_hit[177] = (reg_addr == RV_PLIC_MSIP0_OFFSET); + addr_hit[178] = (reg_addr == RV_PLIC_ALERT_TEST_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(RV_PLIC_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(RV_PLIC_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(RV_PLIC_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(RV_PLIC_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(RV_PLIC_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(RV_PLIC_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(RV_PLIC_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(RV_PLIC_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(RV_PLIC_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(RV_PLIC_PERMIT[ 9] & ~reg_be))) | + (addr_hit[ 10] & (|(RV_PLIC_PERMIT[ 10] & ~reg_be))) | + (addr_hit[ 11] & (|(RV_PLIC_PERMIT[ 11] & ~reg_be))) | + (addr_hit[ 12] & (|(RV_PLIC_PERMIT[ 12] & ~reg_be))) | + (addr_hit[ 13] & (|(RV_PLIC_PERMIT[ 13] & ~reg_be))) | + (addr_hit[ 14] & (|(RV_PLIC_PERMIT[ 14] & ~reg_be))) | + (addr_hit[ 15] & (|(RV_PLIC_PERMIT[ 15] & ~reg_be))) | + (addr_hit[ 16] & (|(RV_PLIC_PERMIT[ 16] & ~reg_be))) | + (addr_hit[ 17] & (|(RV_PLIC_PERMIT[ 17] & ~reg_be))) | + (addr_hit[ 18] & (|(RV_PLIC_PERMIT[ 18] & ~reg_be))) | + (addr_hit[ 19] & (|(RV_PLIC_PERMIT[ 19] & ~reg_be))) | + (addr_hit[ 20] & (|(RV_PLIC_PERMIT[ 20] & ~reg_be))) | + (addr_hit[ 21] & (|(RV_PLIC_PERMIT[ 21] & ~reg_be))) | + (addr_hit[ 22] & (|(RV_PLIC_PERMIT[ 22] & ~reg_be))) | + (addr_hit[ 23] & (|(RV_PLIC_PERMIT[ 23] & ~reg_be))) | + (addr_hit[ 24] & (|(RV_PLIC_PERMIT[ 24] & ~reg_be))) | + (addr_hit[ 25] & (|(RV_PLIC_PERMIT[ 25] & ~reg_be))) | + (addr_hit[ 26] & (|(RV_PLIC_PERMIT[ 26] & ~reg_be))) | + (addr_hit[ 27] & (|(RV_PLIC_PERMIT[ 27] & ~reg_be))) | + (addr_hit[ 28] & (|(RV_PLIC_PERMIT[ 28] & ~reg_be))) | + (addr_hit[ 29] & (|(RV_PLIC_PERMIT[ 29] & ~reg_be))) | + (addr_hit[ 30] & (|(RV_PLIC_PERMIT[ 30] & ~reg_be))) | + (addr_hit[ 31] & (|(RV_PLIC_PERMIT[ 31] & ~reg_be))) | + (addr_hit[ 32] & (|(RV_PLIC_PERMIT[ 32] & ~reg_be))) | + (addr_hit[ 33] & (|(RV_PLIC_PERMIT[ 33] & ~reg_be))) | + (addr_hit[ 34] & (|(RV_PLIC_PERMIT[ 34] & ~reg_be))) | + (addr_hit[ 35] & (|(RV_PLIC_PERMIT[ 35] & ~reg_be))) | + (addr_hit[ 36] & (|(RV_PLIC_PERMIT[ 36] & ~reg_be))) | + (addr_hit[ 37] & (|(RV_PLIC_PERMIT[ 37] & ~reg_be))) | + (addr_hit[ 38] & (|(RV_PLIC_PERMIT[ 38] & ~reg_be))) | + (addr_hit[ 39] & (|(RV_PLIC_PERMIT[ 39] & ~reg_be))) | + (addr_hit[ 40] & (|(RV_PLIC_PERMIT[ 40] & ~reg_be))) | + (addr_hit[ 41] & (|(RV_PLIC_PERMIT[ 41] & ~reg_be))) | + (addr_hit[ 42] & (|(RV_PLIC_PERMIT[ 42] & ~reg_be))) | + (addr_hit[ 43] & (|(RV_PLIC_PERMIT[ 43] & ~reg_be))) | + (addr_hit[ 44] & (|(RV_PLIC_PERMIT[ 44] & ~reg_be))) | + (addr_hit[ 45] & (|(RV_PLIC_PERMIT[ 45] & ~reg_be))) | + (addr_hit[ 46] & (|(RV_PLIC_PERMIT[ 46] & ~reg_be))) | + (addr_hit[ 47] & (|(RV_PLIC_PERMIT[ 47] & ~reg_be))) | + (addr_hit[ 48] & (|(RV_PLIC_PERMIT[ 48] & ~reg_be))) | + (addr_hit[ 49] & (|(RV_PLIC_PERMIT[ 49] & ~reg_be))) | + (addr_hit[ 50] & (|(RV_PLIC_PERMIT[ 50] & ~reg_be))) | + (addr_hit[ 51] & (|(RV_PLIC_PERMIT[ 51] & ~reg_be))) | + (addr_hit[ 52] & (|(RV_PLIC_PERMIT[ 52] & ~reg_be))) | + (addr_hit[ 53] & (|(RV_PLIC_PERMIT[ 53] & ~reg_be))) | + (addr_hit[ 54] & (|(RV_PLIC_PERMIT[ 54] & ~reg_be))) | + (addr_hit[ 55] & (|(RV_PLIC_PERMIT[ 55] & ~reg_be))) | + (addr_hit[ 56] & (|(RV_PLIC_PERMIT[ 56] & ~reg_be))) | + (addr_hit[ 57] & (|(RV_PLIC_PERMIT[ 57] & ~reg_be))) | + (addr_hit[ 58] & (|(RV_PLIC_PERMIT[ 58] & ~reg_be))) | + (addr_hit[ 59] & (|(RV_PLIC_PERMIT[ 59] & ~reg_be))) | + (addr_hit[ 60] & (|(RV_PLIC_PERMIT[ 60] & ~reg_be))) | + (addr_hit[ 61] & (|(RV_PLIC_PERMIT[ 61] & ~reg_be))) | + (addr_hit[ 62] & (|(RV_PLIC_PERMIT[ 62] & ~reg_be))) | + (addr_hit[ 63] & (|(RV_PLIC_PERMIT[ 63] & ~reg_be))) | + (addr_hit[ 64] & (|(RV_PLIC_PERMIT[ 64] & ~reg_be))) | + (addr_hit[ 65] & (|(RV_PLIC_PERMIT[ 65] & ~reg_be))) | + (addr_hit[ 66] & (|(RV_PLIC_PERMIT[ 66] & ~reg_be))) | + (addr_hit[ 67] & (|(RV_PLIC_PERMIT[ 67] & ~reg_be))) | + (addr_hit[ 68] & (|(RV_PLIC_PERMIT[ 68] & ~reg_be))) | + (addr_hit[ 69] & (|(RV_PLIC_PERMIT[ 69] & ~reg_be))) | + (addr_hit[ 70] & (|(RV_PLIC_PERMIT[ 70] & ~reg_be))) | + (addr_hit[ 71] & (|(RV_PLIC_PERMIT[ 71] & ~reg_be))) | + (addr_hit[ 72] & (|(RV_PLIC_PERMIT[ 72] & ~reg_be))) | + (addr_hit[ 73] & (|(RV_PLIC_PERMIT[ 73] & ~reg_be))) | + (addr_hit[ 74] & (|(RV_PLIC_PERMIT[ 74] & ~reg_be))) | + (addr_hit[ 75] & (|(RV_PLIC_PERMIT[ 75] & ~reg_be))) | + (addr_hit[ 76] & (|(RV_PLIC_PERMIT[ 76] & ~reg_be))) | + (addr_hit[ 77] & (|(RV_PLIC_PERMIT[ 77] & ~reg_be))) | + (addr_hit[ 78] & (|(RV_PLIC_PERMIT[ 78] & ~reg_be))) | + (addr_hit[ 79] & (|(RV_PLIC_PERMIT[ 79] & ~reg_be))) | + (addr_hit[ 80] & (|(RV_PLIC_PERMIT[ 80] & ~reg_be))) | + (addr_hit[ 81] & (|(RV_PLIC_PERMIT[ 81] & ~reg_be))) | + (addr_hit[ 82] & (|(RV_PLIC_PERMIT[ 82] & ~reg_be))) | + (addr_hit[ 83] & (|(RV_PLIC_PERMIT[ 83] & ~reg_be))) | + (addr_hit[ 84] & (|(RV_PLIC_PERMIT[ 84] & ~reg_be))) | + (addr_hit[ 85] & (|(RV_PLIC_PERMIT[ 85] & ~reg_be))) | + (addr_hit[ 86] & (|(RV_PLIC_PERMIT[ 86] & ~reg_be))) | + (addr_hit[ 87] & (|(RV_PLIC_PERMIT[ 87] & ~reg_be))) | + (addr_hit[ 88] & (|(RV_PLIC_PERMIT[ 88] & ~reg_be))) | + (addr_hit[ 89] & (|(RV_PLIC_PERMIT[ 89] & ~reg_be))) | + (addr_hit[ 90] & (|(RV_PLIC_PERMIT[ 90] & ~reg_be))) | + (addr_hit[ 91] & (|(RV_PLIC_PERMIT[ 91] & ~reg_be))) | + (addr_hit[ 92] & (|(RV_PLIC_PERMIT[ 92] & ~reg_be))) | + (addr_hit[ 93] & (|(RV_PLIC_PERMIT[ 93] & ~reg_be))) | + (addr_hit[ 94] & (|(RV_PLIC_PERMIT[ 94] & ~reg_be))) | + (addr_hit[ 95] & (|(RV_PLIC_PERMIT[ 95] & ~reg_be))) | + (addr_hit[ 96] & (|(RV_PLIC_PERMIT[ 96] & ~reg_be))) | + (addr_hit[ 97] & (|(RV_PLIC_PERMIT[ 97] & ~reg_be))) | + (addr_hit[ 98] & (|(RV_PLIC_PERMIT[ 98] & ~reg_be))) | + (addr_hit[ 99] & (|(RV_PLIC_PERMIT[ 99] & ~reg_be))) | + (addr_hit[100] & (|(RV_PLIC_PERMIT[100] & ~reg_be))) | + (addr_hit[101] & (|(RV_PLIC_PERMIT[101] & ~reg_be))) | + (addr_hit[102] & (|(RV_PLIC_PERMIT[102] & ~reg_be))) | + (addr_hit[103] & (|(RV_PLIC_PERMIT[103] & ~reg_be))) | + (addr_hit[104] & (|(RV_PLIC_PERMIT[104] & ~reg_be))) | + (addr_hit[105] & (|(RV_PLIC_PERMIT[105] & ~reg_be))) | + (addr_hit[106] & (|(RV_PLIC_PERMIT[106] & ~reg_be))) | + (addr_hit[107] & (|(RV_PLIC_PERMIT[107] & ~reg_be))) | + (addr_hit[108] & (|(RV_PLIC_PERMIT[108] & ~reg_be))) | + (addr_hit[109] & (|(RV_PLIC_PERMIT[109] & ~reg_be))) | + (addr_hit[110] & (|(RV_PLIC_PERMIT[110] & ~reg_be))) | + (addr_hit[111] & (|(RV_PLIC_PERMIT[111] & ~reg_be))) | + (addr_hit[112] & (|(RV_PLIC_PERMIT[112] & ~reg_be))) | + (addr_hit[113] & (|(RV_PLIC_PERMIT[113] & ~reg_be))) | + (addr_hit[114] & (|(RV_PLIC_PERMIT[114] & ~reg_be))) | + (addr_hit[115] & (|(RV_PLIC_PERMIT[115] & ~reg_be))) | + (addr_hit[116] & (|(RV_PLIC_PERMIT[116] & ~reg_be))) | + (addr_hit[117] & (|(RV_PLIC_PERMIT[117] & ~reg_be))) | + (addr_hit[118] & (|(RV_PLIC_PERMIT[118] & ~reg_be))) | + (addr_hit[119] & (|(RV_PLIC_PERMIT[119] & ~reg_be))) | + (addr_hit[120] & (|(RV_PLIC_PERMIT[120] & ~reg_be))) | + (addr_hit[121] & (|(RV_PLIC_PERMIT[121] & ~reg_be))) | + (addr_hit[122] & (|(RV_PLIC_PERMIT[122] & ~reg_be))) | + (addr_hit[123] & (|(RV_PLIC_PERMIT[123] & ~reg_be))) | + (addr_hit[124] & (|(RV_PLIC_PERMIT[124] & ~reg_be))) | + (addr_hit[125] & (|(RV_PLIC_PERMIT[125] & ~reg_be))) | + (addr_hit[126] & (|(RV_PLIC_PERMIT[126] & ~reg_be))) | + (addr_hit[127] & (|(RV_PLIC_PERMIT[127] & ~reg_be))) | + (addr_hit[128] & (|(RV_PLIC_PERMIT[128] & ~reg_be))) | + (addr_hit[129] & (|(RV_PLIC_PERMIT[129] & ~reg_be))) | + (addr_hit[130] & (|(RV_PLIC_PERMIT[130] & ~reg_be))) | + (addr_hit[131] & (|(RV_PLIC_PERMIT[131] & ~reg_be))) | + (addr_hit[132] & (|(RV_PLIC_PERMIT[132] & ~reg_be))) | + (addr_hit[133] & (|(RV_PLIC_PERMIT[133] & ~reg_be))) | + (addr_hit[134] & (|(RV_PLIC_PERMIT[134] & ~reg_be))) | + (addr_hit[135] & (|(RV_PLIC_PERMIT[135] & ~reg_be))) | + (addr_hit[136] & (|(RV_PLIC_PERMIT[136] & ~reg_be))) | + (addr_hit[137] & (|(RV_PLIC_PERMIT[137] & ~reg_be))) | + (addr_hit[138] & (|(RV_PLIC_PERMIT[138] & ~reg_be))) | + (addr_hit[139] & (|(RV_PLIC_PERMIT[139] & ~reg_be))) | + (addr_hit[140] & (|(RV_PLIC_PERMIT[140] & ~reg_be))) | + (addr_hit[141] & (|(RV_PLIC_PERMIT[141] & ~reg_be))) | + (addr_hit[142] & (|(RV_PLIC_PERMIT[142] & ~reg_be))) | + (addr_hit[143] & (|(RV_PLIC_PERMIT[143] & ~reg_be))) | + (addr_hit[144] & (|(RV_PLIC_PERMIT[144] & ~reg_be))) | + (addr_hit[145] & (|(RV_PLIC_PERMIT[145] & ~reg_be))) | + (addr_hit[146] & (|(RV_PLIC_PERMIT[146] & ~reg_be))) | + (addr_hit[147] & (|(RV_PLIC_PERMIT[147] & ~reg_be))) | + (addr_hit[148] & (|(RV_PLIC_PERMIT[148] & ~reg_be))) | + (addr_hit[149] & (|(RV_PLIC_PERMIT[149] & ~reg_be))) | + (addr_hit[150] & (|(RV_PLIC_PERMIT[150] & ~reg_be))) | + (addr_hit[151] & (|(RV_PLIC_PERMIT[151] & ~reg_be))) | + (addr_hit[152] & (|(RV_PLIC_PERMIT[152] & ~reg_be))) | + (addr_hit[153] & (|(RV_PLIC_PERMIT[153] & ~reg_be))) | + (addr_hit[154] & (|(RV_PLIC_PERMIT[154] & ~reg_be))) | + (addr_hit[155] & (|(RV_PLIC_PERMIT[155] & ~reg_be))) | + (addr_hit[156] & (|(RV_PLIC_PERMIT[156] & ~reg_be))) | + (addr_hit[157] & (|(RV_PLIC_PERMIT[157] & ~reg_be))) | + (addr_hit[158] & (|(RV_PLIC_PERMIT[158] & ~reg_be))) | + (addr_hit[159] & (|(RV_PLIC_PERMIT[159] & ~reg_be))) | + (addr_hit[160] & (|(RV_PLIC_PERMIT[160] & ~reg_be))) | + (addr_hit[161] & (|(RV_PLIC_PERMIT[161] & ~reg_be))) | + (addr_hit[162] & (|(RV_PLIC_PERMIT[162] & ~reg_be))) | + (addr_hit[163] & (|(RV_PLIC_PERMIT[163] & ~reg_be))) | + (addr_hit[164] & (|(RV_PLIC_PERMIT[164] & ~reg_be))) | + (addr_hit[165] & (|(RV_PLIC_PERMIT[165] & ~reg_be))) | + (addr_hit[166] & (|(RV_PLIC_PERMIT[166] & ~reg_be))) | + (addr_hit[167] & (|(RV_PLIC_PERMIT[167] & ~reg_be))) | + (addr_hit[168] & (|(RV_PLIC_PERMIT[168] & ~reg_be))) | + (addr_hit[169] & (|(RV_PLIC_PERMIT[169] & ~reg_be))) | + (addr_hit[170] & (|(RV_PLIC_PERMIT[170] & ~reg_be))) | + (addr_hit[171] & (|(RV_PLIC_PERMIT[171] & ~reg_be))) | + (addr_hit[172] & (|(RV_PLIC_PERMIT[172] & ~reg_be))) | + (addr_hit[173] & (|(RV_PLIC_PERMIT[173] & ~reg_be))) | + (addr_hit[174] & (|(RV_PLIC_PERMIT[174] & ~reg_be))) | + (addr_hit[175] & (|(RV_PLIC_PERMIT[175] & ~reg_be))) | + (addr_hit[176] & (|(RV_PLIC_PERMIT[176] & ~reg_be))) | + (addr_hit[177] & (|(RV_PLIC_PERMIT[177] & ~reg_be))) | + (addr_hit[178] & (|(RV_PLIC_PERMIT[178] & ~reg_be))))); + end + + // Generate write-enables + assign prio_0_we = addr_hit[0] & reg_we & !reg_error; + + assign prio_0_wd = reg_wdata[1:0]; + assign prio_1_we = addr_hit[1] & reg_we & !reg_error; + + assign prio_1_wd = reg_wdata[1:0]; + assign prio_2_we = addr_hit[2] & reg_we & !reg_error; + + assign prio_2_wd = reg_wdata[1:0]; + assign prio_3_we = addr_hit[3] & reg_we & !reg_error; + + assign prio_3_wd = reg_wdata[1:0]; + assign prio_4_we = addr_hit[4] & reg_we & !reg_error; + + assign prio_4_wd = reg_wdata[1:0]; + assign prio_5_we = addr_hit[5] & reg_we & !reg_error; + + assign prio_5_wd = reg_wdata[1:0]; + assign prio_6_we = addr_hit[6] & reg_we & !reg_error; + + assign prio_6_wd = reg_wdata[1:0]; + assign prio_7_we = addr_hit[7] & reg_we & !reg_error; + + assign prio_7_wd = reg_wdata[1:0]; + assign prio_8_we = addr_hit[8] & reg_we & !reg_error; + + assign prio_8_wd = reg_wdata[1:0]; + assign prio_9_we = addr_hit[9] & reg_we & !reg_error; + + assign prio_9_wd = reg_wdata[1:0]; + assign prio_10_we = addr_hit[10] & reg_we & !reg_error; + + assign prio_10_wd = reg_wdata[1:0]; + assign prio_11_we = addr_hit[11] & reg_we & !reg_error; + + assign prio_11_wd = reg_wdata[1:0]; + assign prio_12_we = addr_hit[12] & reg_we & !reg_error; + + assign prio_12_wd = reg_wdata[1:0]; + assign prio_13_we = addr_hit[13] & reg_we & !reg_error; + + assign prio_13_wd = reg_wdata[1:0]; + assign prio_14_we = addr_hit[14] & reg_we & !reg_error; + + assign prio_14_wd = reg_wdata[1:0]; + assign prio_15_we = addr_hit[15] & reg_we & !reg_error; + + assign prio_15_wd = reg_wdata[1:0]; + assign prio_16_we = addr_hit[16] & reg_we & !reg_error; + + assign prio_16_wd = reg_wdata[1:0]; + assign prio_17_we = addr_hit[17] & reg_we & !reg_error; + + assign prio_17_wd = reg_wdata[1:0]; + assign prio_18_we = addr_hit[18] & reg_we & !reg_error; + + assign prio_18_wd = reg_wdata[1:0]; + assign prio_19_we = addr_hit[19] & reg_we & !reg_error; + + assign prio_19_wd = reg_wdata[1:0]; + assign prio_20_we = addr_hit[20] & reg_we & !reg_error; + + assign prio_20_wd = reg_wdata[1:0]; + assign prio_21_we = addr_hit[21] & reg_we & !reg_error; + + assign prio_21_wd = reg_wdata[1:0]; + assign prio_22_we = addr_hit[22] & reg_we & !reg_error; + + assign prio_22_wd = reg_wdata[1:0]; + assign prio_23_we = addr_hit[23] & reg_we & !reg_error; + + assign prio_23_wd = reg_wdata[1:0]; + assign prio_24_we = addr_hit[24] & reg_we & !reg_error; + + assign prio_24_wd = reg_wdata[1:0]; + assign prio_25_we = addr_hit[25] & reg_we & !reg_error; + + assign prio_25_wd = reg_wdata[1:0]; + assign prio_26_we = addr_hit[26] & reg_we & !reg_error; + + assign prio_26_wd = reg_wdata[1:0]; + assign prio_27_we = addr_hit[27] & reg_we & !reg_error; + + assign prio_27_wd = reg_wdata[1:0]; + assign prio_28_we = addr_hit[28] & reg_we & !reg_error; + + assign prio_28_wd = reg_wdata[1:0]; + assign prio_29_we = addr_hit[29] & reg_we & !reg_error; + + assign prio_29_wd = reg_wdata[1:0]; + assign prio_30_we = addr_hit[30] & reg_we & !reg_error; + + assign prio_30_wd = reg_wdata[1:0]; + assign prio_31_we = addr_hit[31] & reg_we & !reg_error; + + assign prio_31_wd = reg_wdata[1:0]; + assign prio_32_we = addr_hit[32] & reg_we & !reg_error; + + assign prio_32_wd = reg_wdata[1:0]; + assign prio_33_we = addr_hit[33] & reg_we & !reg_error; + + assign prio_33_wd = reg_wdata[1:0]; + assign prio_34_we = addr_hit[34] & reg_we & !reg_error; + + assign prio_34_wd = reg_wdata[1:0]; + assign prio_35_we = addr_hit[35] & reg_we & !reg_error; + + assign prio_35_wd = reg_wdata[1:0]; + assign prio_36_we = addr_hit[36] & reg_we & !reg_error; + + assign prio_36_wd = reg_wdata[1:0]; + assign prio_37_we = addr_hit[37] & reg_we & !reg_error; + + assign prio_37_wd = reg_wdata[1:0]; + assign prio_38_we = addr_hit[38] & reg_we & !reg_error; + + assign prio_38_wd = reg_wdata[1:0]; + assign prio_39_we = addr_hit[39] & reg_we & !reg_error; + + assign prio_39_wd = reg_wdata[1:0]; + assign prio_40_we = addr_hit[40] & reg_we & !reg_error; + + assign prio_40_wd = reg_wdata[1:0]; + assign prio_41_we = addr_hit[41] & reg_we & !reg_error; + + assign prio_41_wd = reg_wdata[1:0]; + assign prio_42_we = addr_hit[42] & reg_we & !reg_error; + + assign prio_42_wd = reg_wdata[1:0]; + assign prio_43_we = addr_hit[43] & reg_we & !reg_error; + + assign prio_43_wd = reg_wdata[1:0]; + assign prio_44_we = addr_hit[44] & reg_we & !reg_error; + + assign prio_44_wd = reg_wdata[1:0]; + assign prio_45_we = addr_hit[45] & reg_we & !reg_error; + + assign prio_45_wd = reg_wdata[1:0]; + assign prio_46_we = addr_hit[46] & reg_we & !reg_error; + + assign prio_46_wd = reg_wdata[1:0]; + assign prio_47_we = addr_hit[47] & reg_we & !reg_error; + + assign prio_47_wd = reg_wdata[1:0]; + assign prio_48_we = addr_hit[48] & reg_we & !reg_error; + + assign prio_48_wd = reg_wdata[1:0]; + assign prio_49_we = addr_hit[49] & reg_we & !reg_error; + + assign prio_49_wd = reg_wdata[1:0]; + assign prio_50_we = addr_hit[50] & reg_we & !reg_error; + + assign prio_50_wd = reg_wdata[1:0]; + assign prio_51_we = addr_hit[51] & reg_we & !reg_error; + + assign prio_51_wd = reg_wdata[1:0]; + assign prio_52_we = addr_hit[52] & reg_we & !reg_error; + + assign prio_52_wd = reg_wdata[1:0]; + assign prio_53_we = addr_hit[53] & reg_we & !reg_error; + + assign prio_53_wd = reg_wdata[1:0]; + assign prio_54_we = addr_hit[54] & reg_we & !reg_error; + + assign prio_54_wd = reg_wdata[1:0]; + assign prio_55_we = addr_hit[55] & reg_we & !reg_error; + + assign prio_55_wd = reg_wdata[1:0]; + assign prio_56_we = addr_hit[56] & reg_we & !reg_error; + + assign prio_56_wd = reg_wdata[1:0]; + assign prio_57_we = addr_hit[57] & reg_we & !reg_error; + + assign prio_57_wd = reg_wdata[1:0]; + assign prio_58_we = addr_hit[58] & reg_we & !reg_error; + + assign prio_58_wd = reg_wdata[1:0]; + assign prio_59_we = addr_hit[59] & reg_we & !reg_error; + + assign prio_59_wd = reg_wdata[1:0]; + assign prio_60_we = addr_hit[60] & reg_we & !reg_error; + + assign prio_60_wd = reg_wdata[1:0]; + assign prio_61_we = addr_hit[61] & reg_we & !reg_error; + + assign prio_61_wd = reg_wdata[1:0]; + assign prio_62_we = addr_hit[62] & reg_we & !reg_error; + + assign prio_62_wd = reg_wdata[1:0]; + assign prio_63_we = addr_hit[63] & reg_we & !reg_error; + + assign prio_63_wd = reg_wdata[1:0]; + assign prio_64_we = addr_hit[64] & reg_we & !reg_error; + + assign prio_64_wd = reg_wdata[1:0]; + assign prio_65_we = addr_hit[65] & reg_we & !reg_error; + + assign prio_65_wd = reg_wdata[1:0]; + assign prio_66_we = addr_hit[66] & reg_we & !reg_error; + + assign prio_66_wd = reg_wdata[1:0]; + assign prio_67_we = addr_hit[67] & reg_we & !reg_error; + + assign prio_67_wd = reg_wdata[1:0]; + assign prio_68_we = addr_hit[68] & reg_we & !reg_error; + + assign prio_68_wd = reg_wdata[1:0]; + assign prio_69_we = addr_hit[69] & reg_we & !reg_error; + + assign prio_69_wd = reg_wdata[1:0]; + assign prio_70_we = addr_hit[70] & reg_we & !reg_error; + + assign prio_70_wd = reg_wdata[1:0]; + assign prio_71_we = addr_hit[71] & reg_we & !reg_error; + + assign prio_71_wd = reg_wdata[1:0]; + assign prio_72_we = addr_hit[72] & reg_we & !reg_error; + + assign prio_72_wd = reg_wdata[1:0]; + assign prio_73_we = addr_hit[73] & reg_we & !reg_error; + + assign prio_73_wd = reg_wdata[1:0]; + assign prio_74_we = addr_hit[74] & reg_we & !reg_error; + + assign prio_74_wd = reg_wdata[1:0]; + assign prio_75_we = addr_hit[75] & reg_we & !reg_error; + + assign prio_75_wd = reg_wdata[1:0]; + assign prio_76_we = addr_hit[76] & reg_we & !reg_error; + + assign prio_76_wd = reg_wdata[1:0]; + assign prio_77_we = addr_hit[77] & reg_we & !reg_error; + + assign prio_77_wd = reg_wdata[1:0]; + assign prio_78_we = addr_hit[78] & reg_we & !reg_error; + + assign prio_78_wd = reg_wdata[1:0]; + assign prio_79_we = addr_hit[79] & reg_we & !reg_error; + + assign prio_79_wd = reg_wdata[1:0]; + assign prio_80_we = addr_hit[80] & reg_we & !reg_error; + + assign prio_80_wd = reg_wdata[1:0]; + assign prio_81_we = addr_hit[81] & reg_we & !reg_error; + + assign prio_81_wd = reg_wdata[1:0]; + assign prio_82_we = addr_hit[82] & reg_we & !reg_error; + + assign prio_82_wd = reg_wdata[1:0]; + assign prio_83_we = addr_hit[83] & reg_we & !reg_error; + + assign prio_83_wd = reg_wdata[1:0]; + assign prio_84_we = addr_hit[84] & reg_we & !reg_error; + + assign prio_84_wd = reg_wdata[1:0]; + assign prio_85_we = addr_hit[85] & reg_we & !reg_error; + + assign prio_85_wd = reg_wdata[1:0]; + assign prio_86_we = addr_hit[86] & reg_we & !reg_error; + + assign prio_86_wd = reg_wdata[1:0]; + assign prio_87_we = addr_hit[87] & reg_we & !reg_error; + + assign prio_87_wd = reg_wdata[1:0]; + assign prio_88_we = addr_hit[88] & reg_we & !reg_error; + + assign prio_88_wd = reg_wdata[1:0]; + assign prio_89_we = addr_hit[89] & reg_we & !reg_error; + + assign prio_89_wd = reg_wdata[1:0]; + assign prio_90_we = addr_hit[90] & reg_we & !reg_error; + + assign prio_90_wd = reg_wdata[1:0]; + assign prio_91_we = addr_hit[91] & reg_we & !reg_error; + + assign prio_91_wd = reg_wdata[1:0]; + assign prio_92_we = addr_hit[92] & reg_we & !reg_error; + + assign prio_92_wd = reg_wdata[1:0]; + assign prio_93_we = addr_hit[93] & reg_we & !reg_error; + + assign prio_93_wd = reg_wdata[1:0]; + assign prio_94_we = addr_hit[94] & reg_we & !reg_error; + + assign prio_94_wd = reg_wdata[1:0]; + assign prio_95_we = addr_hit[95] & reg_we & !reg_error; + + assign prio_95_wd = reg_wdata[1:0]; + assign prio_96_we = addr_hit[96] & reg_we & !reg_error; + + assign prio_96_wd = reg_wdata[1:0]; + assign prio_97_we = addr_hit[97] & reg_we & !reg_error; + + assign prio_97_wd = reg_wdata[1:0]; + assign prio_98_we = addr_hit[98] & reg_we & !reg_error; + + assign prio_98_wd = reg_wdata[1:0]; + assign prio_99_we = addr_hit[99] & reg_we & !reg_error; + + assign prio_99_wd = reg_wdata[1:0]; + assign prio_100_we = addr_hit[100] & reg_we & !reg_error; + + assign prio_100_wd = reg_wdata[1:0]; + assign prio_101_we = addr_hit[101] & reg_we & !reg_error; + + assign prio_101_wd = reg_wdata[1:0]; + assign prio_102_we = addr_hit[102] & reg_we & !reg_error; + + assign prio_102_wd = reg_wdata[1:0]; + assign prio_103_we = addr_hit[103] & reg_we & !reg_error; + + assign prio_103_wd = reg_wdata[1:0]; + assign prio_104_we = addr_hit[104] & reg_we & !reg_error; + + assign prio_104_wd = reg_wdata[1:0]; + assign prio_105_we = addr_hit[105] & reg_we & !reg_error; + + assign prio_105_wd = reg_wdata[1:0]; + assign prio_106_we = addr_hit[106] & reg_we & !reg_error; + + assign prio_106_wd = reg_wdata[1:0]; + assign prio_107_we = addr_hit[107] & reg_we & !reg_error; + + assign prio_107_wd = reg_wdata[1:0]; + assign prio_108_we = addr_hit[108] & reg_we & !reg_error; + + assign prio_108_wd = reg_wdata[1:0]; + assign prio_109_we = addr_hit[109] & reg_we & !reg_error; + + assign prio_109_wd = reg_wdata[1:0]; + assign prio_110_we = addr_hit[110] & reg_we & !reg_error; + + assign prio_110_wd = reg_wdata[1:0]; + assign prio_111_we = addr_hit[111] & reg_we & !reg_error; + + assign prio_111_wd = reg_wdata[1:0]; + assign prio_112_we = addr_hit[112] & reg_we & !reg_error; + + assign prio_112_wd = reg_wdata[1:0]; + assign prio_113_we = addr_hit[113] & reg_we & !reg_error; + + assign prio_113_wd = reg_wdata[1:0]; + assign prio_114_we = addr_hit[114] & reg_we & !reg_error; + + assign prio_114_wd = reg_wdata[1:0]; + assign prio_115_we = addr_hit[115] & reg_we & !reg_error; + + assign prio_115_wd = reg_wdata[1:0]; + assign prio_116_we = addr_hit[116] & reg_we & !reg_error; + + assign prio_116_wd = reg_wdata[1:0]; + assign prio_117_we = addr_hit[117] & reg_we & !reg_error; + + assign prio_117_wd = reg_wdata[1:0]; + assign prio_118_we = addr_hit[118] & reg_we & !reg_error; + + assign prio_118_wd = reg_wdata[1:0]; + assign prio_119_we = addr_hit[119] & reg_we & !reg_error; + + assign prio_119_wd = reg_wdata[1:0]; + assign prio_120_we = addr_hit[120] & reg_we & !reg_error; + + assign prio_120_wd = reg_wdata[1:0]; + assign prio_121_we = addr_hit[121] & reg_we & !reg_error; + + assign prio_121_wd = reg_wdata[1:0]; + assign prio_122_we = addr_hit[122] & reg_we & !reg_error; + + assign prio_122_wd = reg_wdata[1:0]; + assign prio_123_we = addr_hit[123] & reg_we & !reg_error; + + assign prio_123_wd = reg_wdata[1:0]; + assign prio_124_we = addr_hit[124] & reg_we & !reg_error; + + assign prio_124_wd = reg_wdata[1:0]; + assign prio_125_we = addr_hit[125] & reg_we & !reg_error; + + assign prio_125_wd = reg_wdata[1:0]; + assign prio_126_we = addr_hit[126] & reg_we & !reg_error; + + assign prio_126_wd = reg_wdata[1:0]; + assign prio_127_we = addr_hit[127] & reg_we & !reg_error; + + assign prio_127_wd = reg_wdata[1:0]; + assign prio_128_we = addr_hit[128] & reg_we & !reg_error; + + assign prio_128_wd = reg_wdata[1:0]; + assign prio_129_we = addr_hit[129] & reg_we & !reg_error; + + assign prio_129_wd = reg_wdata[1:0]; + assign prio_130_we = addr_hit[130] & reg_we & !reg_error; + + assign prio_130_wd = reg_wdata[1:0]; + assign prio_131_we = addr_hit[131] & reg_we & !reg_error; + + assign prio_131_wd = reg_wdata[1:0]; + assign prio_132_we = addr_hit[132] & reg_we & !reg_error; + + assign prio_132_wd = reg_wdata[1:0]; + assign prio_133_we = addr_hit[133] & reg_we & !reg_error; + + assign prio_133_wd = reg_wdata[1:0]; + assign prio_134_we = addr_hit[134] & reg_we & !reg_error; + + assign prio_134_wd = reg_wdata[1:0]; + assign prio_135_we = addr_hit[135] & reg_we & !reg_error; + + assign prio_135_wd = reg_wdata[1:0]; + assign prio_136_we = addr_hit[136] & reg_we & !reg_error; + + assign prio_136_wd = reg_wdata[1:0]; + assign prio_137_we = addr_hit[137] & reg_we & !reg_error; + + assign prio_137_wd = reg_wdata[1:0]; + assign prio_138_we = addr_hit[138] & reg_we & !reg_error; + + assign prio_138_wd = reg_wdata[1:0]; + assign prio_139_we = addr_hit[139] & reg_we & !reg_error; + + assign prio_139_wd = reg_wdata[1:0]; + assign prio_140_we = addr_hit[140] & reg_we & !reg_error; + + assign prio_140_wd = reg_wdata[1:0]; + assign prio_141_we = addr_hit[141] & reg_we & !reg_error; + + assign prio_141_wd = reg_wdata[1:0]; + assign prio_142_we = addr_hit[142] & reg_we & !reg_error; + + assign prio_142_wd = reg_wdata[1:0]; + assign prio_143_we = addr_hit[143] & reg_we & !reg_error; + + assign prio_143_wd = reg_wdata[1:0]; + assign prio_144_we = addr_hit[144] & reg_we & !reg_error; + + assign prio_144_wd = reg_wdata[1:0]; + assign prio_145_we = addr_hit[145] & reg_we & !reg_error; + + assign prio_145_wd = reg_wdata[1:0]; + assign prio_146_we = addr_hit[146] & reg_we & !reg_error; + + assign prio_146_wd = reg_wdata[1:0]; + assign prio_147_we = addr_hit[147] & reg_we & !reg_error; + + assign prio_147_wd = reg_wdata[1:0]; + assign prio_148_we = addr_hit[148] & reg_we & !reg_error; + + assign prio_148_wd = reg_wdata[1:0]; + assign prio_149_we = addr_hit[149] & reg_we & !reg_error; + + assign prio_149_wd = reg_wdata[1:0]; + assign prio_150_we = addr_hit[150] & reg_we & !reg_error; + + assign prio_150_wd = reg_wdata[1:0]; + assign prio_151_we = addr_hit[151] & reg_we & !reg_error; + + assign prio_151_wd = reg_wdata[1:0]; + assign prio_152_we = addr_hit[152] & reg_we & !reg_error; + + assign prio_152_wd = reg_wdata[1:0]; + assign prio_153_we = addr_hit[153] & reg_we & !reg_error; + + assign prio_153_wd = reg_wdata[1:0]; + assign prio_154_we = addr_hit[154] & reg_we & !reg_error; + + assign prio_154_wd = reg_wdata[1:0]; + assign prio_155_we = addr_hit[155] & reg_we & !reg_error; + + assign prio_155_wd = reg_wdata[1:0]; + assign prio_156_we = addr_hit[156] & reg_we & !reg_error; + + assign prio_156_wd = reg_wdata[1:0]; + assign prio_157_we = addr_hit[157] & reg_we & !reg_error; + + assign prio_157_wd = reg_wdata[1:0]; + assign prio_158_we = addr_hit[158] & reg_we & !reg_error; + + assign prio_158_wd = reg_wdata[1:0]; + assign prio_159_we = addr_hit[159] & reg_we & !reg_error; + + assign prio_159_wd = reg_wdata[1:0]; + assign prio_160_we = addr_hit[160] & reg_we & !reg_error; + + assign prio_160_wd = reg_wdata[1:0]; + assign prio_161_we = addr_hit[161] & reg_we & !reg_error; + + assign prio_161_wd = reg_wdata[1:0]; + assign prio_162_we = addr_hit[162] & reg_we & !reg_error; + + assign prio_162_wd = reg_wdata[1:0]; + assign ie0_0_we = addr_hit[169] & reg_we & !reg_error; + + assign ie0_0_e_0_wd = reg_wdata[0]; + + assign ie0_0_e_1_wd = reg_wdata[1]; + + assign ie0_0_e_2_wd = reg_wdata[2]; + + assign ie0_0_e_3_wd = reg_wdata[3]; + + assign ie0_0_e_4_wd = reg_wdata[4]; + + assign ie0_0_e_5_wd = reg_wdata[5]; + + assign ie0_0_e_6_wd = reg_wdata[6]; + + assign ie0_0_e_7_wd = reg_wdata[7]; + + assign ie0_0_e_8_wd = reg_wdata[8]; + + assign ie0_0_e_9_wd = reg_wdata[9]; + + assign ie0_0_e_10_wd = reg_wdata[10]; + + assign ie0_0_e_11_wd = reg_wdata[11]; + + assign ie0_0_e_12_wd = reg_wdata[12]; + + assign ie0_0_e_13_wd = reg_wdata[13]; + + assign ie0_0_e_14_wd = reg_wdata[14]; + + assign ie0_0_e_15_wd = reg_wdata[15]; + + assign ie0_0_e_16_wd = reg_wdata[16]; + + assign ie0_0_e_17_wd = reg_wdata[17]; + + assign ie0_0_e_18_wd = reg_wdata[18]; + + assign ie0_0_e_19_wd = reg_wdata[19]; + + assign ie0_0_e_20_wd = reg_wdata[20]; + + assign ie0_0_e_21_wd = reg_wdata[21]; + + assign ie0_0_e_22_wd = reg_wdata[22]; + + assign ie0_0_e_23_wd = reg_wdata[23]; + + assign ie0_0_e_24_wd = reg_wdata[24]; + + assign ie0_0_e_25_wd = reg_wdata[25]; + + assign ie0_0_e_26_wd = reg_wdata[26]; + + assign ie0_0_e_27_wd = reg_wdata[27]; + + assign ie0_0_e_28_wd = reg_wdata[28]; + + assign ie0_0_e_29_wd = reg_wdata[29]; + + assign ie0_0_e_30_wd = reg_wdata[30]; + + assign ie0_0_e_31_wd = reg_wdata[31]; + assign ie0_1_we = addr_hit[170] & reg_we & !reg_error; + + assign ie0_1_e_32_wd = reg_wdata[0]; + + assign ie0_1_e_33_wd = reg_wdata[1]; + + assign ie0_1_e_34_wd = reg_wdata[2]; + + assign ie0_1_e_35_wd = reg_wdata[3]; + + assign ie0_1_e_36_wd = reg_wdata[4]; + + assign ie0_1_e_37_wd = reg_wdata[5]; + + assign ie0_1_e_38_wd = reg_wdata[6]; + + assign ie0_1_e_39_wd = reg_wdata[7]; + + assign ie0_1_e_40_wd = reg_wdata[8]; + + assign ie0_1_e_41_wd = reg_wdata[9]; + + assign ie0_1_e_42_wd = reg_wdata[10]; + + assign ie0_1_e_43_wd = reg_wdata[11]; + + assign ie0_1_e_44_wd = reg_wdata[12]; + + assign ie0_1_e_45_wd = reg_wdata[13]; + + assign ie0_1_e_46_wd = reg_wdata[14]; + + assign ie0_1_e_47_wd = reg_wdata[15]; + + assign ie0_1_e_48_wd = reg_wdata[16]; + + assign ie0_1_e_49_wd = reg_wdata[17]; + + assign ie0_1_e_50_wd = reg_wdata[18]; + + assign ie0_1_e_51_wd = reg_wdata[19]; + + assign ie0_1_e_52_wd = reg_wdata[20]; + + assign ie0_1_e_53_wd = reg_wdata[21]; + + assign ie0_1_e_54_wd = reg_wdata[22]; + + assign ie0_1_e_55_wd = reg_wdata[23]; + + assign ie0_1_e_56_wd = reg_wdata[24]; + + assign ie0_1_e_57_wd = reg_wdata[25]; + + assign ie0_1_e_58_wd = reg_wdata[26]; + + assign ie0_1_e_59_wd = reg_wdata[27]; + + assign ie0_1_e_60_wd = reg_wdata[28]; + + assign ie0_1_e_61_wd = reg_wdata[29]; + + assign ie0_1_e_62_wd = reg_wdata[30]; + + assign ie0_1_e_63_wd = reg_wdata[31]; + assign ie0_2_we = addr_hit[171] & reg_we & !reg_error; + + assign ie0_2_e_64_wd = reg_wdata[0]; + + assign ie0_2_e_65_wd = reg_wdata[1]; + + assign ie0_2_e_66_wd = reg_wdata[2]; + + assign ie0_2_e_67_wd = reg_wdata[3]; + + assign ie0_2_e_68_wd = reg_wdata[4]; + + assign ie0_2_e_69_wd = reg_wdata[5]; + + assign ie0_2_e_70_wd = reg_wdata[6]; + + assign ie0_2_e_71_wd = reg_wdata[7]; + + assign ie0_2_e_72_wd = reg_wdata[8]; + + assign ie0_2_e_73_wd = reg_wdata[9]; + + assign ie0_2_e_74_wd = reg_wdata[10]; + + assign ie0_2_e_75_wd = reg_wdata[11]; + + assign ie0_2_e_76_wd = reg_wdata[12]; + + assign ie0_2_e_77_wd = reg_wdata[13]; + + assign ie0_2_e_78_wd = reg_wdata[14]; + + assign ie0_2_e_79_wd = reg_wdata[15]; + + assign ie0_2_e_80_wd = reg_wdata[16]; + + assign ie0_2_e_81_wd = reg_wdata[17]; + + assign ie0_2_e_82_wd = reg_wdata[18]; + + assign ie0_2_e_83_wd = reg_wdata[19]; + + assign ie0_2_e_84_wd = reg_wdata[20]; + + assign ie0_2_e_85_wd = reg_wdata[21]; + + assign ie0_2_e_86_wd = reg_wdata[22]; + + assign ie0_2_e_87_wd = reg_wdata[23]; + + assign ie0_2_e_88_wd = reg_wdata[24]; + + assign ie0_2_e_89_wd = reg_wdata[25]; + + assign ie0_2_e_90_wd = reg_wdata[26]; + + assign ie0_2_e_91_wd = reg_wdata[27]; + + assign ie0_2_e_92_wd = reg_wdata[28]; + + assign ie0_2_e_93_wd = reg_wdata[29]; + + assign ie0_2_e_94_wd = reg_wdata[30]; + + assign ie0_2_e_95_wd = reg_wdata[31]; + assign ie0_3_we = addr_hit[172] & reg_we & !reg_error; + + assign ie0_3_e_96_wd = reg_wdata[0]; + + assign ie0_3_e_97_wd = reg_wdata[1]; + + assign ie0_3_e_98_wd = reg_wdata[2]; + + assign ie0_3_e_99_wd = reg_wdata[3]; + + assign ie0_3_e_100_wd = reg_wdata[4]; + + assign ie0_3_e_101_wd = reg_wdata[5]; + + assign ie0_3_e_102_wd = reg_wdata[6]; + + assign ie0_3_e_103_wd = reg_wdata[7]; + + assign ie0_3_e_104_wd = reg_wdata[8]; + + assign ie0_3_e_105_wd = reg_wdata[9]; + + assign ie0_3_e_106_wd = reg_wdata[10]; + + assign ie0_3_e_107_wd = reg_wdata[11]; + + assign ie0_3_e_108_wd = reg_wdata[12]; + + assign ie0_3_e_109_wd = reg_wdata[13]; + + assign ie0_3_e_110_wd = reg_wdata[14]; + + assign ie0_3_e_111_wd = reg_wdata[15]; + + assign ie0_3_e_112_wd = reg_wdata[16]; + + assign ie0_3_e_113_wd = reg_wdata[17]; + + assign ie0_3_e_114_wd = reg_wdata[18]; + + assign ie0_3_e_115_wd = reg_wdata[19]; + + assign ie0_3_e_116_wd = reg_wdata[20]; + + assign ie0_3_e_117_wd = reg_wdata[21]; + + assign ie0_3_e_118_wd = reg_wdata[22]; + + assign ie0_3_e_119_wd = reg_wdata[23]; + + assign ie0_3_e_120_wd = reg_wdata[24]; + + assign ie0_3_e_121_wd = reg_wdata[25]; + + assign ie0_3_e_122_wd = reg_wdata[26]; + + assign ie0_3_e_123_wd = reg_wdata[27]; + + assign ie0_3_e_124_wd = reg_wdata[28]; + + assign ie0_3_e_125_wd = reg_wdata[29]; + + assign ie0_3_e_126_wd = reg_wdata[30]; + + assign ie0_3_e_127_wd = reg_wdata[31]; + assign ie0_4_we = addr_hit[173] & reg_we & !reg_error; + + assign ie0_4_e_128_wd = reg_wdata[0]; + + assign ie0_4_e_129_wd = reg_wdata[1]; + + assign ie0_4_e_130_wd = reg_wdata[2]; + + assign ie0_4_e_131_wd = reg_wdata[3]; + + assign ie0_4_e_132_wd = reg_wdata[4]; + + assign ie0_4_e_133_wd = reg_wdata[5]; + + assign ie0_4_e_134_wd = reg_wdata[6]; + + assign ie0_4_e_135_wd = reg_wdata[7]; + + assign ie0_4_e_136_wd = reg_wdata[8]; + + assign ie0_4_e_137_wd = reg_wdata[9]; + + assign ie0_4_e_138_wd = reg_wdata[10]; + + assign ie0_4_e_139_wd = reg_wdata[11]; + + assign ie0_4_e_140_wd = reg_wdata[12]; + + assign ie0_4_e_141_wd = reg_wdata[13]; + + assign ie0_4_e_142_wd = reg_wdata[14]; + + assign ie0_4_e_143_wd = reg_wdata[15]; + + assign ie0_4_e_144_wd = reg_wdata[16]; + + assign ie0_4_e_145_wd = reg_wdata[17]; + + assign ie0_4_e_146_wd = reg_wdata[18]; + + assign ie0_4_e_147_wd = reg_wdata[19]; + + assign ie0_4_e_148_wd = reg_wdata[20]; + + assign ie0_4_e_149_wd = reg_wdata[21]; + + assign ie0_4_e_150_wd = reg_wdata[22]; + + assign ie0_4_e_151_wd = reg_wdata[23]; + + assign ie0_4_e_152_wd = reg_wdata[24]; + + assign ie0_4_e_153_wd = reg_wdata[25]; + + assign ie0_4_e_154_wd = reg_wdata[26]; + + assign ie0_4_e_155_wd = reg_wdata[27]; + + assign ie0_4_e_156_wd = reg_wdata[28]; + + assign ie0_4_e_157_wd = reg_wdata[29]; + + assign ie0_4_e_158_wd = reg_wdata[30]; + + assign ie0_4_e_159_wd = reg_wdata[31]; + assign ie0_5_we = addr_hit[174] & reg_we & !reg_error; + + assign ie0_5_e_160_wd = reg_wdata[0]; + + assign ie0_5_e_161_wd = reg_wdata[1]; + + assign ie0_5_e_162_wd = reg_wdata[2]; + assign threshold0_we = addr_hit[175] & reg_we & !reg_error; + + assign threshold0_wd = reg_wdata[1:0]; + assign cc0_re = addr_hit[176] & reg_re & !reg_error; + assign cc0_we = addr_hit[176] & reg_we & !reg_error; + + assign cc0_wd = reg_wdata[7:0]; + assign msip0_we = addr_hit[177] & reg_we & !reg_error; + + assign msip0_wd = reg_wdata[0]; + assign alert_test_we = addr_hit[178] & reg_we & !reg_error; + + assign alert_test_wd = reg_wdata[0]; + + // Assign write-enables to checker logic vector. + always_comb begin + reg_we_check[0] = prio_0_we; + reg_we_check[1] = prio_1_we; + reg_we_check[2] = prio_2_we; + reg_we_check[3] = prio_3_we; + reg_we_check[4] = prio_4_we; + reg_we_check[5] = prio_5_we; + reg_we_check[6] = prio_6_we; + reg_we_check[7] = prio_7_we; + reg_we_check[8] = prio_8_we; + reg_we_check[9] = prio_9_we; + reg_we_check[10] = prio_10_we; + reg_we_check[11] = prio_11_we; + reg_we_check[12] = prio_12_we; + reg_we_check[13] = prio_13_we; + reg_we_check[14] = prio_14_we; + reg_we_check[15] = prio_15_we; + reg_we_check[16] = prio_16_we; + reg_we_check[17] = prio_17_we; + reg_we_check[18] = prio_18_we; + reg_we_check[19] = prio_19_we; + reg_we_check[20] = prio_20_we; + reg_we_check[21] = prio_21_we; + reg_we_check[22] = prio_22_we; + reg_we_check[23] = prio_23_we; + reg_we_check[24] = prio_24_we; + reg_we_check[25] = prio_25_we; + reg_we_check[26] = prio_26_we; + reg_we_check[27] = prio_27_we; + reg_we_check[28] = prio_28_we; + reg_we_check[29] = prio_29_we; + reg_we_check[30] = prio_30_we; + reg_we_check[31] = prio_31_we; + reg_we_check[32] = prio_32_we; + reg_we_check[33] = prio_33_we; + reg_we_check[34] = prio_34_we; + reg_we_check[35] = prio_35_we; + reg_we_check[36] = prio_36_we; + reg_we_check[37] = prio_37_we; + reg_we_check[38] = prio_38_we; + reg_we_check[39] = prio_39_we; + reg_we_check[40] = prio_40_we; + reg_we_check[41] = prio_41_we; + reg_we_check[42] = prio_42_we; + reg_we_check[43] = prio_43_we; + reg_we_check[44] = prio_44_we; + reg_we_check[45] = prio_45_we; + reg_we_check[46] = prio_46_we; + reg_we_check[47] = prio_47_we; + reg_we_check[48] = prio_48_we; + reg_we_check[49] = prio_49_we; + reg_we_check[50] = prio_50_we; + reg_we_check[51] = prio_51_we; + reg_we_check[52] = prio_52_we; + reg_we_check[53] = prio_53_we; + reg_we_check[54] = prio_54_we; + reg_we_check[55] = prio_55_we; + reg_we_check[56] = prio_56_we; + reg_we_check[57] = prio_57_we; + reg_we_check[58] = prio_58_we; + reg_we_check[59] = prio_59_we; + reg_we_check[60] = prio_60_we; + reg_we_check[61] = prio_61_we; + reg_we_check[62] = prio_62_we; + reg_we_check[63] = prio_63_we; + reg_we_check[64] = prio_64_we; + reg_we_check[65] = prio_65_we; + reg_we_check[66] = prio_66_we; + reg_we_check[67] = prio_67_we; + reg_we_check[68] = prio_68_we; + reg_we_check[69] = prio_69_we; + reg_we_check[70] = prio_70_we; + reg_we_check[71] = prio_71_we; + reg_we_check[72] = prio_72_we; + reg_we_check[73] = prio_73_we; + reg_we_check[74] = prio_74_we; + reg_we_check[75] = prio_75_we; + reg_we_check[76] = prio_76_we; + reg_we_check[77] = prio_77_we; + reg_we_check[78] = prio_78_we; + reg_we_check[79] = prio_79_we; + reg_we_check[80] = prio_80_we; + reg_we_check[81] = prio_81_we; + reg_we_check[82] = prio_82_we; + reg_we_check[83] = prio_83_we; + reg_we_check[84] = prio_84_we; + reg_we_check[85] = prio_85_we; + reg_we_check[86] = prio_86_we; + reg_we_check[87] = prio_87_we; + reg_we_check[88] = prio_88_we; + reg_we_check[89] = prio_89_we; + reg_we_check[90] = prio_90_we; + reg_we_check[91] = prio_91_we; + reg_we_check[92] = prio_92_we; + reg_we_check[93] = prio_93_we; + reg_we_check[94] = prio_94_we; + reg_we_check[95] = prio_95_we; + reg_we_check[96] = prio_96_we; + reg_we_check[97] = prio_97_we; + reg_we_check[98] = prio_98_we; + reg_we_check[99] = prio_99_we; + reg_we_check[100] = prio_100_we; + reg_we_check[101] = prio_101_we; + reg_we_check[102] = prio_102_we; + reg_we_check[103] = prio_103_we; + reg_we_check[104] = prio_104_we; + reg_we_check[105] = prio_105_we; + reg_we_check[106] = prio_106_we; + reg_we_check[107] = prio_107_we; + reg_we_check[108] = prio_108_we; + reg_we_check[109] = prio_109_we; + reg_we_check[110] = prio_110_we; + reg_we_check[111] = prio_111_we; + reg_we_check[112] = prio_112_we; + reg_we_check[113] = prio_113_we; + reg_we_check[114] = prio_114_we; + reg_we_check[115] = prio_115_we; + reg_we_check[116] = prio_116_we; + reg_we_check[117] = prio_117_we; + reg_we_check[118] = prio_118_we; + reg_we_check[119] = prio_119_we; + reg_we_check[120] = prio_120_we; + reg_we_check[121] = prio_121_we; + reg_we_check[122] = prio_122_we; + reg_we_check[123] = prio_123_we; + reg_we_check[124] = prio_124_we; + reg_we_check[125] = prio_125_we; + reg_we_check[126] = prio_126_we; + reg_we_check[127] = prio_127_we; + reg_we_check[128] = prio_128_we; + reg_we_check[129] = prio_129_we; + reg_we_check[130] = prio_130_we; + reg_we_check[131] = prio_131_we; + reg_we_check[132] = prio_132_we; + reg_we_check[133] = prio_133_we; + reg_we_check[134] = prio_134_we; + reg_we_check[135] = prio_135_we; + reg_we_check[136] = prio_136_we; + reg_we_check[137] = prio_137_we; + reg_we_check[138] = prio_138_we; + reg_we_check[139] = prio_139_we; + reg_we_check[140] = prio_140_we; + reg_we_check[141] = prio_141_we; + reg_we_check[142] = prio_142_we; + reg_we_check[143] = prio_143_we; + reg_we_check[144] = prio_144_we; + reg_we_check[145] = prio_145_we; + reg_we_check[146] = prio_146_we; + reg_we_check[147] = prio_147_we; + reg_we_check[148] = prio_148_we; + reg_we_check[149] = prio_149_we; + reg_we_check[150] = prio_150_we; + reg_we_check[151] = prio_151_we; + reg_we_check[152] = prio_152_we; + reg_we_check[153] = prio_153_we; + reg_we_check[154] = prio_154_we; + reg_we_check[155] = prio_155_we; + reg_we_check[156] = prio_156_we; + reg_we_check[157] = prio_157_we; + reg_we_check[158] = prio_158_we; + reg_we_check[159] = prio_159_we; + reg_we_check[160] = prio_160_we; + reg_we_check[161] = prio_161_we; + reg_we_check[162] = prio_162_we; + reg_we_check[163] = 1'b0; + reg_we_check[164] = 1'b0; + reg_we_check[165] = 1'b0; + reg_we_check[166] = 1'b0; + reg_we_check[167] = 1'b0; + reg_we_check[168] = 1'b0; + reg_we_check[169] = ie0_0_we; + reg_we_check[170] = ie0_1_we; + reg_we_check[171] = ie0_2_we; + reg_we_check[172] = ie0_3_we; + reg_we_check[173] = ie0_4_we; + reg_we_check[174] = ie0_5_we; + reg_we_check[175] = threshold0_we; + reg_we_check[176] = cc0_we; + reg_we_check[177] = msip0_we; + reg_we_check[178] = alert_test_we; + end + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[1:0] = prio_0_qs; + end + + addr_hit[1]: begin + reg_rdata_next[1:0] = prio_1_qs; + end + + addr_hit[2]: begin + reg_rdata_next[1:0] = prio_2_qs; + end + + addr_hit[3]: begin + reg_rdata_next[1:0] = prio_3_qs; + end + + addr_hit[4]: begin + reg_rdata_next[1:0] = prio_4_qs; + end + + addr_hit[5]: begin + reg_rdata_next[1:0] = prio_5_qs; + end + + addr_hit[6]: begin + reg_rdata_next[1:0] = prio_6_qs; + end + + addr_hit[7]: begin + reg_rdata_next[1:0] = prio_7_qs; + end + + addr_hit[8]: begin + reg_rdata_next[1:0] = prio_8_qs; + end + + addr_hit[9]: begin + reg_rdata_next[1:0] = prio_9_qs; + end + + addr_hit[10]: begin + reg_rdata_next[1:0] = prio_10_qs; + end + + addr_hit[11]: begin + reg_rdata_next[1:0] = prio_11_qs; + end + + addr_hit[12]: begin + reg_rdata_next[1:0] = prio_12_qs; + end + + addr_hit[13]: begin + reg_rdata_next[1:0] = prio_13_qs; + end + + addr_hit[14]: begin + reg_rdata_next[1:0] = prio_14_qs; + end + + addr_hit[15]: begin + reg_rdata_next[1:0] = prio_15_qs; + end + + addr_hit[16]: begin + reg_rdata_next[1:0] = prio_16_qs; + end + + addr_hit[17]: begin + reg_rdata_next[1:0] = prio_17_qs; + end + + addr_hit[18]: begin + reg_rdata_next[1:0] = prio_18_qs; + end + + addr_hit[19]: begin + reg_rdata_next[1:0] = prio_19_qs; + end + + addr_hit[20]: begin + reg_rdata_next[1:0] = prio_20_qs; + end + + addr_hit[21]: begin + reg_rdata_next[1:0] = prio_21_qs; + end + + addr_hit[22]: begin + reg_rdata_next[1:0] = prio_22_qs; + end + + addr_hit[23]: begin + reg_rdata_next[1:0] = prio_23_qs; + end + + addr_hit[24]: begin + reg_rdata_next[1:0] = prio_24_qs; + end + + addr_hit[25]: begin + reg_rdata_next[1:0] = prio_25_qs; + end + + addr_hit[26]: begin + reg_rdata_next[1:0] = prio_26_qs; + end + + addr_hit[27]: begin + reg_rdata_next[1:0] = prio_27_qs; + end + + addr_hit[28]: begin + reg_rdata_next[1:0] = prio_28_qs; + end + + addr_hit[29]: begin + reg_rdata_next[1:0] = prio_29_qs; + end + + addr_hit[30]: begin + reg_rdata_next[1:0] = prio_30_qs; + end + + addr_hit[31]: begin + reg_rdata_next[1:0] = prio_31_qs; + end + + addr_hit[32]: begin + reg_rdata_next[1:0] = prio_32_qs; + end + + addr_hit[33]: begin + reg_rdata_next[1:0] = prio_33_qs; + end + + addr_hit[34]: begin + reg_rdata_next[1:0] = prio_34_qs; + end + + addr_hit[35]: begin + reg_rdata_next[1:0] = prio_35_qs; + end + + addr_hit[36]: begin + reg_rdata_next[1:0] = prio_36_qs; + end + + addr_hit[37]: begin + reg_rdata_next[1:0] = prio_37_qs; + end + + addr_hit[38]: begin + reg_rdata_next[1:0] = prio_38_qs; + end + + addr_hit[39]: begin + reg_rdata_next[1:0] = prio_39_qs; + end + + addr_hit[40]: begin + reg_rdata_next[1:0] = prio_40_qs; + end + + addr_hit[41]: begin + reg_rdata_next[1:0] = prio_41_qs; + end + + addr_hit[42]: begin + reg_rdata_next[1:0] = prio_42_qs; + end + + addr_hit[43]: begin + reg_rdata_next[1:0] = prio_43_qs; + end + + addr_hit[44]: begin + reg_rdata_next[1:0] = prio_44_qs; + end + + addr_hit[45]: begin + reg_rdata_next[1:0] = prio_45_qs; + end + + addr_hit[46]: begin + reg_rdata_next[1:0] = prio_46_qs; + end + + addr_hit[47]: begin + reg_rdata_next[1:0] = prio_47_qs; + end + + addr_hit[48]: begin + reg_rdata_next[1:0] = prio_48_qs; + end + + addr_hit[49]: begin + reg_rdata_next[1:0] = prio_49_qs; + end + + addr_hit[50]: begin + reg_rdata_next[1:0] = prio_50_qs; + end + + addr_hit[51]: begin + reg_rdata_next[1:0] = prio_51_qs; + end + + addr_hit[52]: begin + reg_rdata_next[1:0] = prio_52_qs; + end + + addr_hit[53]: begin + reg_rdata_next[1:0] = prio_53_qs; + end + + addr_hit[54]: begin + reg_rdata_next[1:0] = prio_54_qs; + end + + addr_hit[55]: begin + reg_rdata_next[1:0] = prio_55_qs; + end + + addr_hit[56]: begin + reg_rdata_next[1:0] = prio_56_qs; + end + + addr_hit[57]: begin + reg_rdata_next[1:0] = prio_57_qs; + end + + addr_hit[58]: begin + reg_rdata_next[1:0] = prio_58_qs; + end + + addr_hit[59]: begin + reg_rdata_next[1:0] = prio_59_qs; + end + + addr_hit[60]: begin + reg_rdata_next[1:0] = prio_60_qs; + end + + addr_hit[61]: begin + reg_rdata_next[1:0] = prio_61_qs; + end + + addr_hit[62]: begin + reg_rdata_next[1:0] = prio_62_qs; + end + + addr_hit[63]: begin + reg_rdata_next[1:0] = prio_63_qs; + end + + addr_hit[64]: begin + reg_rdata_next[1:0] = prio_64_qs; + end + + addr_hit[65]: begin + reg_rdata_next[1:0] = prio_65_qs; + end + + addr_hit[66]: begin + reg_rdata_next[1:0] = prio_66_qs; + end + + addr_hit[67]: begin + reg_rdata_next[1:0] = prio_67_qs; + end + + addr_hit[68]: begin + reg_rdata_next[1:0] = prio_68_qs; + end + + addr_hit[69]: begin + reg_rdata_next[1:0] = prio_69_qs; + end + + addr_hit[70]: begin + reg_rdata_next[1:0] = prio_70_qs; + end + + addr_hit[71]: begin + reg_rdata_next[1:0] = prio_71_qs; + end + + addr_hit[72]: begin + reg_rdata_next[1:0] = prio_72_qs; + end + + addr_hit[73]: begin + reg_rdata_next[1:0] = prio_73_qs; + end + + addr_hit[74]: begin + reg_rdata_next[1:0] = prio_74_qs; + end + + addr_hit[75]: begin + reg_rdata_next[1:0] = prio_75_qs; + end + + addr_hit[76]: begin + reg_rdata_next[1:0] = prio_76_qs; + end + + addr_hit[77]: begin + reg_rdata_next[1:0] = prio_77_qs; + end + + addr_hit[78]: begin + reg_rdata_next[1:0] = prio_78_qs; + end + + addr_hit[79]: begin + reg_rdata_next[1:0] = prio_79_qs; + end + + addr_hit[80]: begin + reg_rdata_next[1:0] = prio_80_qs; + end + + addr_hit[81]: begin + reg_rdata_next[1:0] = prio_81_qs; + end + + addr_hit[82]: begin + reg_rdata_next[1:0] = prio_82_qs; + end + + addr_hit[83]: begin + reg_rdata_next[1:0] = prio_83_qs; + end + + addr_hit[84]: begin + reg_rdata_next[1:0] = prio_84_qs; + end + + addr_hit[85]: begin + reg_rdata_next[1:0] = prio_85_qs; + end + + addr_hit[86]: begin + reg_rdata_next[1:0] = prio_86_qs; + end + + addr_hit[87]: begin + reg_rdata_next[1:0] = prio_87_qs; + end + + addr_hit[88]: begin + reg_rdata_next[1:0] = prio_88_qs; + end + + addr_hit[89]: begin + reg_rdata_next[1:0] = prio_89_qs; + end + + addr_hit[90]: begin + reg_rdata_next[1:0] = prio_90_qs; + end + + addr_hit[91]: begin + reg_rdata_next[1:0] = prio_91_qs; + end + + addr_hit[92]: begin + reg_rdata_next[1:0] = prio_92_qs; + end + + addr_hit[93]: begin + reg_rdata_next[1:0] = prio_93_qs; + end + + addr_hit[94]: begin + reg_rdata_next[1:0] = prio_94_qs; + end + + addr_hit[95]: begin + reg_rdata_next[1:0] = prio_95_qs; + end + + addr_hit[96]: begin + reg_rdata_next[1:0] = prio_96_qs; + end + + addr_hit[97]: begin + reg_rdata_next[1:0] = prio_97_qs; + end + + addr_hit[98]: begin + reg_rdata_next[1:0] = prio_98_qs; + end + + addr_hit[99]: begin + reg_rdata_next[1:0] = prio_99_qs; + end + + addr_hit[100]: begin + reg_rdata_next[1:0] = prio_100_qs; + end + + addr_hit[101]: begin + reg_rdata_next[1:0] = prio_101_qs; + end + + addr_hit[102]: begin + reg_rdata_next[1:0] = prio_102_qs; + end + + addr_hit[103]: begin + reg_rdata_next[1:0] = prio_103_qs; + end + + addr_hit[104]: begin + reg_rdata_next[1:0] = prio_104_qs; + end + + addr_hit[105]: begin + reg_rdata_next[1:0] = prio_105_qs; + end + + addr_hit[106]: begin + reg_rdata_next[1:0] = prio_106_qs; + end + + addr_hit[107]: begin + reg_rdata_next[1:0] = prio_107_qs; + end + + addr_hit[108]: begin + reg_rdata_next[1:0] = prio_108_qs; + end + + addr_hit[109]: begin + reg_rdata_next[1:0] = prio_109_qs; + end + + addr_hit[110]: begin + reg_rdata_next[1:0] = prio_110_qs; + end + + addr_hit[111]: begin + reg_rdata_next[1:0] = prio_111_qs; + end + + addr_hit[112]: begin + reg_rdata_next[1:0] = prio_112_qs; + end + + addr_hit[113]: begin + reg_rdata_next[1:0] = prio_113_qs; + end + + addr_hit[114]: begin + reg_rdata_next[1:0] = prio_114_qs; + end + + addr_hit[115]: begin + reg_rdata_next[1:0] = prio_115_qs; + end + + addr_hit[116]: begin + reg_rdata_next[1:0] = prio_116_qs; + end + + addr_hit[117]: begin + reg_rdata_next[1:0] = prio_117_qs; + end + + addr_hit[118]: begin + reg_rdata_next[1:0] = prio_118_qs; + end + + addr_hit[119]: begin + reg_rdata_next[1:0] = prio_119_qs; + end + + addr_hit[120]: begin + reg_rdata_next[1:0] = prio_120_qs; + end + + addr_hit[121]: begin + reg_rdata_next[1:0] = prio_121_qs; + end + + addr_hit[122]: begin + reg_rdata_next[1:0] = prio_122_qs; + end + + addr_hit[123]: begin + reg_rdata_next[1:0] = prio_123_qs; + end + + addr_hit[124]: begin + reg_rdata_next[1:0] = prio_124_qs; + end + + addr_hit[125]: begin + reg_rdata_next[1:0] = prio_125_qs; + end + + addr_hit[126]: begin + reg_rdata_next[1:0] = prio_126_qs; + end + + addr_hit[127]: begin + reg_rdata_next[1:0] = prio_127_qs; + end + + addr_hit[128]: begin + reg_rdata_next[1:0] = prio_128_qs; + end + + addr_hit[129]: begin + reg_rdata_next[1:0] = prio_129_qs; + end + + addr_hit[130]: begin + reg_rdata_next[1:0] = prio_130_qs; + end + + addr_hit[131]: begin + reg_rdata_next[1:0] = prio_131_qs; + end + + addr_hit[132]: begin + reg_rdata_next[1:0] = prio_132_qs; + end + + addr_hit[133]: begin + reg_rdata_next[1:0] = prio_133_qs; + end + + addr_hit[134]: begin + reg_rdata_next[1:0] = prio_134_qs; + end + + addr_hit[135]: begin + reg_rdata_next[1:0] = prio_135_qs; + end + + addr_hit[136]: begin + reg_rdata_next[1:0] = prio_136_qs; + end + + addr_hit[137]: begin + reg_rdata_next[1:0] = prio_137_qs; + end + + addr_hit[138]: begin + reg_rdata_next[1:0] = prio_138_qs; + end + + addr_hit[139]: begin + reg_rdata_next[1:0] = prio_139_qs; + end + + addr_hit[140]: begin + reg_rdata_next[1:0] = prio_140_qs; + end + + addr_hit[141]: begin + reg_rdata_next[1:0] = prio_141_qs; + end + + addr_hit[142]: begin + reg_rdata_next[1:0] = prio_142_qs; + end + + addr_hit[143]: begin + reg_rdata_next[1:0] = prio_143_qs; + end + + addr_hit[144]: begin + reg_rdata_next[1:0] = prio_144_qs; + end + + addr_hit[145]: begin + reg_rdata_next[1:0] = prio_145_qs; + end + + addr_hit[146]: begin + reg_rdata_next[1:0] = prio_146_qs; + end + + addr_hit[147]: begin + reg_rdata_next[1:0] = prio_147_qs; + end + + addr_hit[148]: begin + reg_rdata_next[1:0] = prio_148_qs; + end + + addr_hit[149]: begin + reg_rdata_next[1:0] = prio_149_qs; + end + + addr_hit[150]: begin + reg_rdata_next[1:0] = prio_150_qs; + end + + addr_hit[151]: begin + reg_rdata_next[1:0] = prio_151_qs; + end + + addr_hit[152]: begin + reg_rdata_next[1:0] = prio_152_qs; + end + + addr_hit[153]: begin + reg_rdata_next[1:0] = prio_153_qs; + end + + addr_hit[154]: begin + reg_rdata_next[1:0] = prio_154_qs; + end + + addr_hit[155]: begin + reg_rdata_next[1:0] = prio_155_qs; + end + + addr_hit[156]: begin + reg_rdata_next[1:0] = prio_156_qs; + end + + addr_hit[157]: begin + reg_rdata_next[1:0] = prio_157_qs; + end + + addr_hit[158]: begin + reg_rdata_next[1:0] = prio_158_qs; + end + + addr_hit[159]: begin + reg_rdata_next[1:0] = prio_159_qs; + end + + addr_hit[160]: begin + reg_rdata_next[1:0] = prio_160_qs; + end + + addr_hit[161]: begin + reg_rdata_next[1:0] = prio_161_qs; + end + + addr_hit[162]: begin + reg_rdata_next[1:0] = prio_162_qs; + end + + addr_hit[163]: begin + reg_rdata_next[0] = ip_0_p_0_qs; + reg_rdata_next[1] = ip_0_p_1_qs; + reg_rdata_next[2] = ip_0_p_2_qs; + reg_rdata_next[3] = ip_0_p_3_qs; + reg_rdata_next[4] = ip_0_p_4_qs; + reg_rdata_next[5] = ip_0_p_5_qs; + reg_rdata_next[6] = ip_0_p_6_qs; + reg_rdata_next[7] = ip_0_p_7_qs; + reg_rdata_next[8] = ip_0_p_8_qs; + reg_rdata_next[9] = ip_0_p_9_qs; + reg_rdata_next[10] = ip_0_p_10_qs; + reg_rdata_next[11] = ip_0_p_11_qs; + reg_rdata_next[12] = ip_0_p_12_qs; + reg_rdata_next[13] = ip_0_p_13_qs; + reg_rdata_next[14] = ip_0_p_14_qs; + reg_rdata_next[15] = ip_0_p_15_qs; + reg_rdata_next[16] = ip_0_p_16_qs; + reg_rdata_next[17] = ip_0_p_17_qs; + reg_rdata_next[18] = ip_0_p_18_qs; + reg_rdata_next[19] = ip_0_p_19_qs; + reg_rdata_next[20] = ip_0_p_20_qs; + reg_rdata_next[21] = ip_0_p_21_qs; + reg_rdata_next[22] = ip_0_p_22_qs; + reg_rdata_next[23] = ip_0_p_23_qs; + reg_rdata_next[24] = ip_0_p_24_qs; + reg_rdata_next[25] = ip_0_p_25_qs; + reg_rdata_next[26] = ip_0_p_26_qs; + reg_rdata_next[27] = ip_0_p_27_qs; + reg_rdata_next[28] = ip_0_p_28_qs; + reg_rdata_next[29] = ip_0_p_29_qs; + reg_rdata_next[30] = ip_0_p_30_qs; + reg_rdata_next[31] = ip_0_p_31_qs; + end + + addr_hit[164]: begin + reg_rdata_next[0] = ip_1_p_32_qs; + reg_rdata_next[1] = ip_1_p_33_qs; + reg_rdata_next[2] = ip_1_p_34_qs; + reg_rdata_next[3] = ip_1_p_35_qs; + reg_rdata_next[4] = ip_1_p_36_qs; + reg_rdata_next[5] = ip_1_p_37_qs; + reg_rdata_next[6] = ip_1_p_38_qs; + reg_rdata_next[7] = ip_1_p_39_qs; + reg_rdata_next[8] = ip_1_p_40_qs; + reg_rdata_next[9] = ip_1_p_41_qs; + reg_rdata_next[10] = ip_1_p_42_qs; + reg_rdata_next[11] = ip_1_p_43_qs; + reg_rdata_next[12] = ip_1_p_44_qs; + reg_rdata_next[13] = ip_1_p_45_qs; + reg_rdata_next[14] = ip_1_p_46_qs; + reg_rdata_next[15] = ip_1_p_47_qs; + reg_rdata_next[16] = ip_1_p_48_qs; + reg_rdata_next[17] = ip_1_p_49_qs; + reg_rdata_next[18] = ip_1_p_50_qs; + reg_rdata_next[19] = ip_1_p_51_qs; + reg_rdata_next[20] = ip_1_p_52_qs; + reg_rdata_next[21] = ip_1_p_53_qs; + reg_rdata_next[22] = ip_1_p_54_qs; + reg_rdata_next[23] = ip_1_p_55_qs; + reg_rdata_next[24] = ip_1_p_56_qs; + reg_rdata_next[25] = ip_1_p_57_qs; + reg_rdata_next[26] = ip_1_p_58_qs; + reg_rdata_next[27] = ip_1_p_59_qs; + reg_rdata_next[28] = ip_1_p_60_qs; + reg_rdata_next[29] = ip_1_p_61_qs; + reg_rdata_next[30] = ip_1_p_62_qs; + reg_rdata_next[31] = ip_1_p_63_qs; + end + + addr_hit[165]: begin + reg_rdata_next[0] = ip_2_p_64_qs; + reg_rdata_next[1] = ip_2_p_65_qs; + reg_rdata_next[2] = ip_2_p_66_qs; + reg_rdata_next[3] = ip_2_p_67_qs; + reg_rdata_next[4] = ip_2_p_68_qs; + reg_rdata_next[5] = ip_2_p_69_qs; + reg_rdata_next[6] = ip_2_p_70_qs; + reg_rdata_next[7] = ip_2_p_71_qs; + reg_rdata_next[8] = ip_2_p_72_qs; + reg_rdata_next[9] = ip_2_p_73_qs; + reg_rdata_next[10] = ip_2_p_74_qs; + reg_rdata_next[11] = ip_2_p_75_qs; + reg_rdata_next[12] = ip_2_p_76_qs; + reg_rdata_next[13] = ip_2_p_77_qs; + reg_rdata_next[14] = ip_2_p_78_qs; + reg_rdata_next[15] = ip_2_p_79_qs; + reg_rdata_next[16] = ip_2_p_80_qs; + reg_rdata_next[17] = ip_2_p_81_qs; + reg_rdata_next[18] = ip_2_p_82_qs; + reg_rdata_next[19] = ip_2_p_83_qs; + reg_rdata_next[20] = ip_2_p_84_qs; + reg_rdata_next[21] = ip_2_p_85_qs; + reg_rdata_next[22] = ip_2_p_86_qs; + reg_rdata_next[23] = ip_2_p_87_qs; + reg_rdata_next[24] = ip_2_p_88_qs; + reg_rdata_next[25] = ip_2_p_89_qs; + reg_rdata_next[26] = ip_2_p_90_qs; + reg_rdata_next[27] = ip_2_p_91_qs; + reg_rdata_next[28] = ip_2_p_92_qs; + reg_rdata_next[29] = ip_2_p_93_qs; + reg_rdata_next[30] = ip_2_p_94_qs; + reg_rdata_next[31] = ip_2_p_95_qs; + end + + addr_hit[166]: begin + reg_rdata_next[0] = ip_3_p_96_qs; + reg_rdata_next[1] = ip_3_p_97_qs; + reg_rdata_next[2] = ip_3_p_98_qs; + reg_rdata_next[3] = ip_3_p_99_qs; + reg_rdata_next[4] = ip_3_p_100_qs; + reg_rdata_next[5] = ip_3_p_101_qs; + reg_rdata_next[6] = ip_3_p_102_qs; + reg_rdata_next[7] = ip_3_p_103_qs; + reg_rdata_next[8] = ip_3_p_104_qs; + reg_rdata_next[9] = ip_3_p_105_qs; + reg_rdata_next[10] = ip_3_p_106_qs; + reg_rdata_next[11] = ip_3_p_107_qs; + reg_rdata_next[12] = ip_3_p_108_qs; + reg_rdata_next[13] = ip_3_p_109_qs; + reg_rdata_next[14] = ip_3_p_110_qs; + reg_rdata_next[15] = ip_3_p_111_qs; + reg_rdata_next[16] = ip_3_p_112_qs; + reg_rdata_next[17] = ip_3_p_113_qs; + reg_rdata_next[18] = ip_3_p_114_qs; + reg_rdata_next[19] = ip_3_p_115_qs; + reg_rdata_next[20] = ip_3_p_116_qs; + reg_rdata_next[21] = ip_3_p_117_qs; + reg_rdata_next[22] = ip_3_p_118_qs; + reg_rdata_next[23] = ip_3_p_119_qs; + reg_rdata_next[24] = ip_3_p_120_qs; + reg_rdata_next[25] = ip_3_p_121_qs; + reg_rdata_next[26] = ip_3_p_122_qs; + reg_rdata_next[27] = ip_3_p_123_qs; + reg_rdata_next[28] = ip_3_p_124_qs; + reg_rdata_next[29] = ip_3_p_125_qs; + reg_rdata_next[30] = ip_3_p_126_qs; + reg_rdata_next[31] = ip_3_p_127_qs; + end + + addr_hit[167]: begin + reg_rdata_next[0] = ip_4_p_128_qs; + reg_rdata_next[1] = ip_4_p_129_qs; + reg_rdata_next[2] = ip_4_p_130_qs; + reg_rdata_next[3] = ip_4_p_131_qs; + reg_rdata_next[4] = ip_4_p_132_qs; + reg_rdata_next[5] = ip_4_p_133_qs; + reg_rdata_next[6] = ip_4_p_134_qs; + reg_rdata_next[7] = ip_4_p_135_qs; + reg_rdata_next[8] = ip_4_p_136_qs; + reg_rdata_next[9] = ip_4_p_137_qs; + reg_rdata_next[10] = ip_4_p_138_qs; + reg_rdata_next[11] = ip_4_p_139_qs; + reg_rdata_next[12] = ip_4_p_140_qs; + reg_rdata_next[13] = ip_4_p_141_qs; + reg_rdata_next[14] = ip_4_p_142_qs; + reg_rdata_next[15] = ip_4_p_143_qs; + reg_rdata_next[16] = ip_4_p_144_qs; + reg_rdata_next[17] = ip_4_p_145_qs; + reg_rdata_next[18] = ip_4_p_146_qs; + reg_rdata_next[19] = ip_4_p_147_qs; + reg_rdata_next[20] = ip_4_p_148_qs; + reg_rdata_next[21] = ip_4_p_149_qs; + reg_rdata_next[22] = ip_4_p_150_qs; + reg_rdata_next[23] = ip_4_p_151_qs; + reg_rdata_next[24] = ip_4_p_152_qs; + reg_rdata_next[25] = ip_4_p_153_qs; + reg_rdata_next[26] = ip_4_p_154_qs; + reg_rdata_next[27] = ip_4_p_155_qs; + reg_rdata_next[28] = ip_4_p_156_qs; + reg_rdata_next[29] = ip_4_p_157_qs; + reg_rdata_next[30] = ip_4_p_158_qs; + reg_rdata_next[31] = ip_4_p_159_qs; + end + + addr_hit[168]: begin + reg_rdata_next[0] = ip_5_p_160_qs; + reg_rdata_next[1] = ip_5_p_161_qs; + reg_rdata_next[2] = ip_5_p_162_qs; + end + + addr_hit[169]: begin + reg_rdata_next[0] = ie0_0_e_0_qs; + reg_rdata_next[1] = ie0_0_e_1_qs; + reg_rdata_next[2] = ie0_0_e_2_qs; + reg_rdata_next[3] = ie0_0_e_3_qs; + reg_rdata_next[4] = ie0_0_e_4_qs; + reg_rdata_next[5] = ie0_0_e_5_qs; + reg_rdata_next[6] = ie0_0_e_6_qs; + reg_rdata_next[7] = ie0_0_e_7_qs; + reg_rdata_next[8] = ie0_0_e_8_qs; + reg_rdata_next[9] = ie0_0_e_9_qs; + reg_rdata_next[10] = ie0_0_e_10_qs; + reg_rdata_next[11] = ie0_0_e_11_qs; + reg_rdata_next[12] = ie0_0_e_12_qs; + reg_rdata_next[13] = ie0_0_e_13_qs; + reg_rdata_next[14] = ie0_0_e_14_qs; + reg_rdata_next[15] = ie0_0_e_15_qs; + reg_rdata_next[16] = ie0_0_e_16_qs; + reg_rdata_next[17] = ie0_0_e_17_qs; + reg_rdata_next[18] = ie0_0_e_18_qs; + reg_rdata_next[19] = ie0_0_e_19_qs; + reg_rdata_next[20] = ie0_0_e_20_qs; + reg_rdata_next[21] = ie0_0_e_21_qs; + reg_rdata_next[22] = ie0_0_e_22_qs; + reg_rdata_next[23] = ie0_0_e_23_qs; + reg_rdata_next[24] = ie0_0_e_24_qs; + reg_rdata_next[25] = ie0_0_e_25_qs; + reg_rdata_next[26] = ie0_0_e_26_qs; + reg_rdata_next[27] = ie0_0_e_27_qs; + reg_rdata_next[28] = ie0_0_e_28_qs; + reg_rdata_next[29] = ie0_0_e_29_qs; + reg_rdata_next[30] = ie0_0_e_30_qs; + reg_rdata_next[31] = ie0_0_e_31_qs; + end + + addr_hit[170]: begin + reg_rdata_next[0] = ie0_1_e_32_qs; + reg_rdata_next[1] = ie0_1_e_33_qs; + reg_rdata_next[2] = ie0_1_e_34_qs; + reg_rdata_next[3] = ie0_1_e_35_qs; + reg_rdata_next[4] = ie0_1_e_36_qs; + reg_rdata_next[5] = ie0_1_e_37_qs; + reg_rdata_next[6] = ie0_1_e_38_qs; + reg_rdata_next[7] = ie0_1_e_39_qs; + reg_rdata_next[8] = ie0_1_e_40_qs; + reg_rdata_next[9] = ie0_1_e_41_qs; + reg_rdata_next[10] = ie0_1_e_42_qs; + reg_rdata_next[11] = ie0_1_e_43_qs; + reg_rdata_next[12] = ie0_1_e_44_qs; + reg_rdata_next[13] = ie0_1_e_45_qs; + reg_rdata_next[14] = ie0_1_e_46_qs; + reg_rdata_next[15] = ie0_1_e_47_qs; + reg_rdata_next[16] = ie0_1_e_48_qs; + reg_rdata_next[17] = ie0_1_e_49_qs; + reg_rdata_next[18] = ie0_1_e_50_qs; + reg_rdata_next[19] = ie0_1_e_51_qs; + reg_rdata_next[20] = ie0_1_e_52_qs; + reg_rdata_next[21] = ie0_1_e_53_qs; + reg_rdata_next[22] = ie0_1_e_54_qs; + reg_rdata_next[23] = ie0_1_e_55_qs; + reg_rdata_next[24] = ie0_1_e_56_qs; + reg_rdata_next[25] = ie0_1_e_57_qs; + reg_rdata_next[26] = ie0_1_e_58_qs; + reg_rdata_next[27] = ie0_1_e_59_qs; + reg_rdata_next[28] = ie0_1_e_60_qs; + reg_rdata_next[29] = ie0_1_e_61_qs; + reg_rdata_next[30] = ie0_1_e_62_qs; + reg_rdata_next[31] = ie0_1_e_63_qs; + end + + addr_hit[171]: begin + reg_rdata_next[0] = ie0_2_e_64_qs; + reg_rdata_next[1] = ie0_2_e_65_qs; + reg_rdata_next[2] = ie0_2_e_66_qs; + reg_rdata_next[3] = ie0_2_e_67_qs; + reg_rdata_next[4] = ie0_2_e_68_qs; + reg_rdata_next[5] = ie0_2_e_69_qs; + reg_rdata_next[6] = ie0_2_e_70_qs; + reg_rdata_next[7] = ie0_2_e_71_qs; + reg_rdata_next[8] = ie0_2_e_72_qs; + reg_rdata_next[9] = ie0_2_e_73_qs; + reg_rdata_next[10] = ie0_2_e_74_qs; + reg_rdata_next[11] = ie0_2_e_75_qs; + reg_rdata_next[12] = ie0_2_e_76_qs; + reg_rdata_next[13] = ie0_2_e_77_qs; + reg_rdata_next[14] = ie0_2_e_78_qs; + reg_rdata_next[15] = ie0_2_e_79_qs; + reg_rdata_next[16] = ie0_2_e_80_qs; + reg_rdata_next[17] = ie0_2_e_81_qs; + reg_rdata_next[18] = ie0_2_e_82_qs; + reg_rdata_next[19] = ie0_2_e_83_qs; + reg_rdata_next[20] = ie0_2_e_84_qs; + reg_rdata_next[21] = ie0_2_e_85_qs; + reg_rdata_next[22] = ie0_2_e_86_qs; + reg_rdata_next[23] = ie0_2_e_87_qs; + reg_rdata_next[24] = ie0_2_e_88_qs; + reg_rdata_next[25] = ie0_2_e_89_qs; + reg_rdata_next[26] = ie0_2_e_90_qs; + reg_rdata_next[27] = ie0_2_e_91_qs; + reg_rdata_next[28] = ie0_2_e_92_qs; + reg_rdata_next[29] = ie0_2_e_93_qs; + reg_rdata_next[30] = ie0_2_e_94_qs; + reg_rdata_next[31] = ie0_2_e_95_qs; + end + + addr_hit[172]: begin + reg_rdata_next[0] = ie0_3_e_96_qs; + reg_rdata_next[1] = ie0_3_e_97_qs; + reg_rdata_next[2] = ie0_3_e_98_qs; + reg_rdata_next[3] = ie0_3_e_99_qs; + reg_rdata_next[4] = ie0_3_e_100_qs; + reg_rdata_next[5] = ie0_3_e_101_qs; + reg_rdata_next[6] = ie0_3_e_102_qs; + reg_rdata_next[7] = ie0_3_e_103_qs; + reg_rdata_next[8] = ie0_3_e_104_qs; + reg_rdata_next[9] = ie0_3_e_105_qs; + reg_rdata_next[10] = ie0_3_e_106_qs; + reg_rdata_next[11] = ie0_3_e_107_qs; + reg_rdata_next[12] = ie0_3_e_108_qs; + reg_rdata_next[13] = ie0_3_e_109_qs; + reg_rdata_next[14] = ie0_3_e_110_qs; + reg_rdata_next[15] = ie0_3_e_111_qs; + reg_rdata_next[16] = ie0_3_e_112_qs; + reg_rdata_next[17] = ie0_3_e_113_qs; + reg_rdata_next[18] = ie0_3_e_114_qs; + reg_rdata_next[19] = ie0_3_e_115_qs; + reg_rdata_next[20] = ie0_3_e_116_qs; + reg_rdata_next[21] = ie0_3_e_117_qs; + reg_rdata_next[22] = ie0_3_e_118_qs; + reg_rdata_next[23] = ie0_3_e_119_qs; + reg_rdata_next[24] = ie0_3_e_120_qs; + reg_rdata_next[25] = ie0_3_e_121_qs; + reg_rdata_next[26] = ie0_3_e_122_qs; + reg_rdata_next[27] = ie0_3_e_123_qs; + reg_rdata_next[28] = ie0_3_e_124_qs; + reg_rdata_next[29] = ie0_3_e_125_qs; + reg_rdata_next[30] = ie0_3_e_126_qs; + reg_rdata_next[31] = ie0_3_e_127_qs; + end + + addr_hit[173]: begin + reg_rdata_next[0] = ie0_4_e_128_qs; + reg_rdata_next[1] = ie0_4_e_129_qs; + reg_rdata_next[2] = ie0_4_e_130_qs; + reg_rdata_next[3] = ie0_4_e_131_qs; + reg_rdata_next[4] = ie0_4_e_132_qs; + reg_rdata_next[5] = ie0_4_e_133_qs; + reg_rdata_next[6] = ie0_4_e_134_qs; + reg_rdata_next[7] = ie0_4_e_135_qs; + reg_rdata_next[8] = ie0_4_e_136_qs; + reg_rdata_next[9] = ie0_4_e_137_qs; + reg_rdata_next[10] = ie0_4_e_138_qs; + reg_rdata_next[11] = ie0_4_e_139_qs; + reg_rdata_next[12] = ie0_4_e_140_qs; + reg_rdata_next[13] = ie0_4_e_141_qs; + reg_rdata_next[14] = ie0_4_e_142_qs; + reg_rdata_next[15] = ie0_4_e_143_qs; + reg_rdata_next[16] = ie0_4_e_144_qs; + reg_rdata_next[17] = ie0_4_e_145_qs; + reg_rdata_next[18] = ie0_4_e_146_qs; + reg_rdata_next[19] = ie0_4_e_147_qs; + reg_rdata_next[20] = ie0_4_e_148_qs; + reg_rdata_next[21] = ie0_4_e_149_qs; + reg_rdata_next[22] = ie0_4_e_150_qs; + reg_rdata_next[23] = ie0_4_e_151_qs; + reg_rdata_next[24] = ie0_4_e_152_qs; + reg_rdata_next[25] = ie0_4_e_153_qs; + reg_rdata_next[26] = ie0_4_e_154_qs; + reg_rdata_next[27] = ie0_4_e_155_qs; + reg_rdata_next[28] = ie0_4_e_156_qs; + reg_rdata_next[29] = ie0_4_e_157_qs; + reg_rdata_next[30] = ie0_4_e_158_qs; + reg_rdata_next[31] = ie0_4_e_159_qs; + end + + addr_hit[174]: begin + reg_rdata_next[0] = ie0_5_e_160_qs; + reg_rdata_next[1] = ie0_5_e_161_qs; + reg_rdata_next[2] = ie0_5_e_162_qs; + end + + addr_hit[175]: begin + reg_rdata_next[1:0] = threshold0_qs; + end + + addr_hit[176]: begin + reg_rdata_next[7:0] = cc0_qs; + end + + addr_hit[177]: begin + reg_rdata_next[0] = msip0_qs; + end + + addr_hit[178]: begin + reg_rdata_next[0] = '0; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // shadow busy + logic shadow_busy; + assign shadow_busy = 1'b0; + + // register busy + assign reg_busy = shadow_busy; + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) + `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) + + `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) + + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) + + // this is formulated as an assumption such that the FPV testbenches do disprove this + // property by mistake + //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_target.sv b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_target.sv new file mode 100644 index 00000000000..301dff3e99f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rtl/rv_plic_target.sv @@ -0,0 +1,74 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// RISC-V Platform-Level Interrupt Generator for Target +// +// This module basically doing IE & IP based on priority and threshold_i. +// Keep in mind that increasing MAX_PRIO affects logic size a lot. +// +// The module implements a binary tree to find the maximal entry. the solution +// has O(N) area and O(log(N)) delay complexity, and thus scales well with +// many input sources. +// + +`include "prim_assert.sv" + +module rv_plic_target #( + parameter int N_SOURCE = 32, + parameter int MAX_PRIO = 7, + + // Local param (Do not change this through parameter + localparam int SrcWidth = $clog2(N_SOURCE), // derived parameter + localparam int PrioWidth = $clog2(MAX_PRIO+1) // derived parameter +) ( + input clk_i, + input rst_ni, + + input [N_SOURCE-1:0] ip_i, + input [N_SOURCE-1:0] ie_i, + + input [N_SOURCE-1:0][PrioWidth-1:0] prio_i, + input [PrioWidth-1:0] threshold_i, + + output logic irq_o, + output logic [SrcWidth-1:0] irq_id_o +); + + // Find maximum value and index using a binary tree implementation. + logic max_valid; + logic [PrioWidth-1:0] max_value; + logic [SrcWidth-1:0] max_idx; + prim_max_tree #( + .NumSrc(N_SOURCE), + .Width(PrioWidth) + ) u_prim_max_tree ( + .clk_i, + .rst_ni, + .values_i(prio_i), + .valid_i(ip_i & ie_i), + .max_value_o(max_value), + .max_idx_o(max_idx), + .max_valid_o(max_valid) + ); + + logic irq_d, irq_q; + logic [SrcWidth-1:0] irq_id_d, irq_id_q; + + assign irq_d = (max_value > threshold_i) ? max_valid : 1'b0; + assign irq_id_d = (max_valid) ? max_idx : '0; + + always_ff @(posedge clk_i or negedge rst_ni) begin : gen_regs + if (!rst_ni) begin + irq_q <= 1'b0; + irq_id_q <= '0; + end else begin + irq_q <= irq_d; + irq_id_q <= irq_id_d; + end + end + + assign irq_o = irq_q; + assign irq_id_o = irq_id_q; + +endmodule diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rv_plic.core b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rv_plic.core new file mode 100644 index 00000000000..9e71371ad01 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rv_plic.core @@ -0,0 +1,40 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:rv_plic:0.1 +description: "RISC-V Platform Interrupt Controller (PLIC)" + +filesets: + files_rtl: + depend: + - lowrisc:darjeeling_no_ibex_ip:rv_plic_component:0.1 + - lowrisc:ip:tlul + - lowrisc:prim:subreg + files: + - rtl/rv_plic_reg_pkg.sv + - rtl/rv_plic_reg_top.sv + - rtl/rv_plic.sv + file_type: systemVerilogSource + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - files_rtl + toplevel: rv_plic + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rv_plic_component.core b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rv_plic_component.core new file mode 100644 index 00000000000..48bcdc3f156 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/ip_autogen/rv_plic/rv_plic_component.core @@ -0,0 +1,51 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:darjeeling_no_ibex_ip:rv_plic_component:0.1 +description: "RISC-V Platform Interrupt Controller (PLIC)" + +filesets: + files_rtl: + depend: + - lowrisc:prim:assert + - lowrisc:prim:alert + - lowrisc:prim:max_tree + - lowrisc:prim:flop_2sync + - lowrisc:prim:reg_we_check + files: + - rtl/rv_plic_gateway.sv + - rtl/rv_plic_target.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/rv_plic.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/rv_plic.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + +targets: + default: + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl diff --git a/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex.vbl b/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex.vbl new file mode 100644 index 00000000000..eecf2a87e6f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex.vbl @@ -0,0 +1,6 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# These lines are too long due to templating +waive --rule=line-length --location=".*top_darjeeling_no_ibex.*" diff --git a/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex.vlt b/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex.vlt new file mode 100644 index 00000000000..795a6e0568c --- /dev/null +++ b/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex.vlt @@ -0,0 +1,5 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// waiver file for top_darjeeling_no_ibex diff --git a/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex.waiver b/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex.waiver new file mode 100644 index 00000000000..e419dcdea34 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex.waiver @@ -0,0 +1,77 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for top_darjeeling_no_ibex + +# dedicated reset drivers / muxes +set_reset_drivers prim_clock_mux2 prim_flop_2sync prim_flop +set_clock_drivers prim_clock_buf prim_clock_mux2 + +# TODO #25411: remove these waivers later when the USB clock was removed from the integrated system +# in a clean way. Right now there are some dangling signals that we have to keep in order +# to not disrupt the RTL structure and associated DV. +waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {xbar_main.sv} \ + -regexp {'(clk_usb_i|rst_usb_ni)' is not read from in module 'xbar_main'} \ + -comment "Temporary waiver for dangling USB clocks and resets." + +# All leaf resets have a reset multiplex +waive -rules RESET_MUX -location {top_darjeeling_no_ibex.sv} -regexp {Asynchronous reset .*rstmgr_aon_resets\.rst.* is driven by a multiplexer} \ + -comment "This is dedicated reset infrastructure, and hence permissible" + +# scan reset is a legal asynchronous reset +waive -rules RESET_USE -location {top_darjeeling_no_ibex.sv} -regexp {'scan_rst_ni' is connected to .* port 'scan_rst_ni', and used as an asynchronous reset or set 'rst_.*ni' at} \ + -comment "Scan reset is a legal asynchronous reset" + +# TODO: Remove waiver when #25410 is resolved +waive -rules {HIER_BRANCH_NOT_READ} -location {pinmux.sv} \ + -msg {Net 'rst_sys_ni' is not read from in module 'pinmux'} \ + -comment "This signal is unused but cannot yet be gated in ipgen" + +# TODO: Remove waiver when #25410 is resolved +waive -rules {HIER_BRANCH_NOT_READ} -location {pinmux.sv} \ + -msg {Net 'scanmode_i' is not read from in module 'pinmux'} \ + -comment "This signal is unused but cannot yet be gated in ipgen" + +waive -rules INPUT_NOT_READ -location {pinmux.sv} -regexp {Input port '(rst_sys_ni|scanmode_i)' is not read from} \ + -comment "This signal is unused but cannot yet be gated in ipgen." + +waive -rules {HIER_NET_NOT_READ NOT_READ} -location {clkmgr.sv} \ + -regexp {(Net|Signal) 'clk_io_root' is not read from in module 'clkmgr'} \ + -comment "This clock is unused in Darjeeling - should not be generated" + +waive -rules {HIER_NET_NOT_READ NOT_READ} -location {clkmgr.sv} \ + -regexp {(Net|Signal) 'clk_io_div2_root' is not read from in module 'clkmgr'} \ + -comment "This clock is unused in Darjeeling - should not be generated" + +waive -rules CLOCK_MUX -location {clkmgr.sv top_darjeeling_no_ibex.sv} -regexp {.*clk_io_div.* is driven by a multiplexer here} \ + -comment "Divided clocks go through prim_clock_div, which use muxes for scan bypass and clock step down" + +waive -rules CLOCK_MUX -location {top_darjeeling_no_ibex.sv} -regexp {Clock 'spi_device_passthrough_req.sck' reaches a multiplexer here, used as a clock} \ + -comment "In passthrough mode, spi_host muxes 'spi_device_passthrough_req.sck' to the `cio_sck_o` output." + +waive -rules {CLOCK_USE} -location {pinmux.sv} -regexp {'dio_wkup_mux\[(42|43)\]' is used for some other purpose, and as clock} \ + -comment "DioSpiDeviceSck and DioSpiDeviceCsb at indices 42 and 43 both can act as clocks" + +# Most SAME_NAME_TYPE issues have been fixed. There are however some that overlap due to similar terminology. +# Since these functions / parameters / signals live in different scopes, this is acceptable, and we can waive them. +waive -rules SAME_NAME_TYPE -location {aes_sbox_canright_pkg.sv keccak_2share.sv} -regexp {'theta' is used as a (reg|function) here, and as a (function|reg) at} \ + -comment {This is acceptable, since these are used in different hierarchies.} +waive -rules SAME_NAME_TYPE -location {keccak_round.sv otbn_pkg.sv} -regexp {'L' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ + -comment {This is acceptable, since these are used in different hierarchies.} +waive -rules SAME_NAME_TYPE -location {spi_device.sv rstmgr_pkg.sv} -regexp {'spi_device' is used as a (module|reg) here, and as a (reg|module) at } \ + -comment {This is acceptable, since these are used in different hierarchies.} +waive -rules SAME_NAME_TYPE -location {tlul_socket_m1.sv otbn_pkg.sv} -regexp {'M' is used as a (parameter|reg) here, and as a (reg|parameter) at} \ + -comment {This is acceptable, since these are used in different hierarchies.} +waive -rules SAME_NAME_TYPE -location {prim_trivium.sv prim_xoshiro256pp.sv} -regexp {'state_update' is used as a (reg|function) here, and as a (function|reg) at} \ + -comment {This is acceptable, since these are used in different hierarchies.} +waive -rules SAME_NAME_TYPE -location {spi_device.sv mbx.sv} -regexp {'mbx' is used as a (reg|module) here, and as a (module|reg) at} \ + -comment {This is acceptable, since these are used in different hierarchies.} + +# intentionally unused +waive -rules {NOT_READ HIER_NET_NOT_READ} -location {top_darjeeling_no_ibex.sv} -regexp {.*cio_otp_macro_test_(en_)?d2p\[7:1\].* is not read} \ + -comment "otp test bus made deliberately larger on purpose" + +waive -rules {LINE_LENGTH} -location {top_darjeeling_no_ibex.sv} -regexp {Line length of [0-9]+ exceeds 100 character limit} \ + -comment "top_darjeeling_no_ibex is auto-generated and adhering to the line length limit is not always feasible for auto-generated code" + diff --git a/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex_lint_cfgs.hjson b/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex_lint_cfgs.hjson new file mode 100644 index 00000000000..c0f366ef75d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/lint/top_darjeeling_no_ibex_lint_cfgs.hjson @@ -0,0 +1,284 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + + // This is the primary cfg hjson for RTL linting. It imports ALL individual lint + // cfgs of the IPs and the full chip used in top_darjeeling. This enables to run + // them all as a regression in one shot. + name: top_darjeeling_batch + + flow: lint + + import_cfgs: [// common server configuration for results upload + "{proj_root}/hw/data/common_project_cfg.hjson" + // tool-specific configuration + "{proj_root}/hw/lint/tools/dvsim/{tool}.hjson"] + + // Different dashboard output path for each tool + rel_path: "hw/top_darjeeling_no_ibex/lint/{tool}/summary" + + // Severities to be printed in the summary report + report_severities: ["warning", "error"] + + use_cfgs: [{ name: mbx + fusesoc_core: lowrisc:ip:mbx + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/mbx/lint/{tool}" + }, + { name: dma + fusesoc_core: lowrisc:ip:dma + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/dma/lint/{tool}" + }, + { name: aes + fusesoc_core: lowrisc:ip:aes + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/aes/lint/{tool}" + }, + { + name: ac_range_check + fusesoc_core: lowrisc:darjeeling_ip:ac_range_check + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/top_darjeeling/ip_autogen/ac_range_check/lint/{tool}" + }, + { name: alert_handler + fusesoc_core: lowrisc:darjeeling_ip:alert_handler + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/top_darjeeling/ip_autogen/alert_handler/lint/{tool}" + }, + { name: aon_timer + fusesoc_core: lowrisc:ip:aon_timer + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/aon_timer/lint/{tool}" + }, + { name: ast + fusesoc_core: lowrisc:systems:top_darjeeling_ast + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/top_darjeeling/ip/ast/lint/{tool}" + }, + //{ name: clkmgr + // fusesoc_core: lowrisc:darjeeling_ip:clkmgr + // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], + // rel_path: "hw/top_darjeeling/ip_autogen/clkmgr/lint/{tool}", + //}, + { name: csrng + fusesoc_core: lowrisc:ip:csrng + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/csrng/lint/{tool}" + }, + { name: entropy_src + fusesoc_core: lowrisc:ip:entropy_src + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/entropy_src/lint/{tool}" + }, + { name: edn + fusesoc_core: lowrisc:ip:edn + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/edn/lint/{tool}" + }, + { name: hmac + fusesoc_core: lowrisc:ip:hmac + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/hmac/lint/{tool}" + }, + { name: kmac + fusesoc_core: lowrisc:ip:kmac + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/kmac/lint/{tool}" + }, + { name: i2c + fusesoc_core: lowrisc:ip:i2c + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/i2c/lint/{tool}" + }, + { name: lc_ctrl + fusesoc_core: lowrisc:ip:lc_ctrl + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/lc_ctrl/lint/{tool}" + }, + { name: keymgr + fusesoc_core: lowrisc:ip:keymgr + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/keymgr/lint/{tool}" + }, + { name: keymgr_dpe + fusesoc_core: lowrisc:ip:keymgr_dpe + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/keymgr_dpe/lint/{tool}" + }, + { name: otbn + fusesoc_core: lowrisc:ip:otbn + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/otbn/lint/{tool}" + }, + { name: otp_ctrl + fusesoc_core: lowrisc:darjeeling_ip:otp_ctrl + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/top_darjeeling/ip_autogen/otp_ctrl/lint/{tool}" + }, + //{ name: pinmux + // fusesoc_core: lowrisc:darjeeling_ip:pinmux + // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + // rel_path: "hw/top_darjeeling/ip_autogen/pinmux/lint/{tool}" + //}, + { name: pwrmgr + fusesoc_core: lowrisc:darjeeling_ip:pwrmgr + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/top_darjeeling/ip_autogen/pwrmgr/lint/{tool}", + }, + { name: rom_ctrl + fusesoc_core: lowrisc:ip:rom_ctrl + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/rom_ctrl/lint/{tool}" + }, + { name: rstmgr + fusesoc_core: lowrisc:darjeeling_ip:rstmgr + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/top_darjeeling/ip_autogen/rstmgr/lint/{tool}", + }, + { name: gpio + fusesoc_core: lowrisc:darjeeling_ip:gpio + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/top_darjeeling/ip_autogen/gpio/lint/{tool}" + }, + { name: rv_core_ibex + fusesoc_core: lowrisc:darjeeling_ip:rv_core_ibex + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"], + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/top_darjeeling/ip_autogen/rv_core_ibex/lint/{tool}", + }, + { name: rv_dm + fusesoc_core: lowrisc:ip:rv_dm + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/rv_dm/lint/{tool}" + }, + { name: soc_dbg_ctrl + fusesoc_core: lowrisc:ip:soc_dbg_ctrl + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/soc_dbg_ctrl/lint/{tool}" + }, + { name: soc_dbg_ctrl_decode + fusesoc_core: lowrisc:ip:soc_dbg_ctrl_decode + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/ip/socdbg_ctrl/lint/{tool}" + }, + { name: top_darjeeling_rv_plic + fusesoc_core: lowrisc:darjeeling_ip:rv_plic + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/top_darjeeling/ip_autogen/rv_plic/lint/{tool}" + }, + { name: rv_timer + fusesoc_core: lowrisc:ip:rv_timer + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/rv_timer/lint/{tool}" + }, + { name: soc_proxy + fusesoc_core: lowrisc:systems:soc_proxy + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + rel_path: "hw/top_darjeeling/ip/soc_proxy/lint/{tool}" + }, + { name: spi_device + fusesoc_core: lowrisc:ip:spi_device + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/spi_device/lint/{tool}" + }, + { name: spi_host + fusesoc_core: lowrisc:ip:spi_host + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/spi_host/lint/{tool}" + }, + { name: sram_ctrl + fusesoc_core: lowrisc:ip:sram_ctrl + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/sram_ctrl/lint/{tool}" + }, + { name: uart + fusesoc_core: lowrisc:ip:uart + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/uart/lint/{tool}" + }, + { name: socket_1n + fusesoc_core: lowrisc:tlul:socket_1n + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/tlul/socket_1n/lint/{tool}" + }, + { name: socket_m1 + fusesoc_core: lowrisc:tlul:socket_m1 + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/tlul/socket_m1/lint/{tool}" + }, + { name: adapter_reg + fusesoc_core: lowrisc:tlul:adapter_reg + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/tlul/adapter_reg/lint/{tool}" + }, + //{ name: adapter_dmi + // fusesoc_core: lowrisc:tlul:adapter_dmi + // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + // rel_path: "hw/ip/tlul/adapter_dmi/lint/{tool}" + //}, + //{ name: jtag_dtm + // fusesoc_core: lowrisc:tlul:jtag_dtm + // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + // rel_path: "hw/ip/tlul/jtag_dtm/lint/{tool}" + //}, + { name: adapter_sram + fusesoc_core: lowrisc:tlul:adapter_sram + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/tlul/adapter_sram/lint/{tool}" + }, + { name: sram2tlul + fusesoc_core: lowrisc:tlul:sram2tlul + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling:0.1" + rel_path: "hw/ip/tlul/sram2tlul/lint/{tool}" + }, + { name: top_darjeeling_no_ibex + fusesoc_core: lowrisc:systems:top_darjeeling_no_ibex + import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + additional_fusesoc_argument: "--mapping=lowrisc:systems:top_darjeeling_no_ibex:0.1" + rel_path: "hw/top_darjeeling_no_ibex/lint/{tool}" + }, + //{ name: chip_darjeeling_asic + // fusesoc_core: lowrisc:systems:chip_darjeeling_asic + // import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + // rel_path: "hw/top_darjeeling/lint/{tool}" + //}, + ] + +} + diff --git a/hw/top_darjeeling_no_ibex/rtl/autogen/chip_darjeeling_no_ibex_asic.sv b/hw/top_darjeeling_no_ibex/rtl/autogen/chip_darjeeling_no_ibex_asic.sv new file mode 100644 index 00000000000..d5198b715b0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/rtl/autogen/chip_darjeeling_no_ibex_asic.sv @@ -0,0 +1,1815 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + + +module chip_darjeeling_no_ibex_asic #( + parameter bit SecRomCtrl0DisableScrambling = 1'b0, + parameter bit SecRomCtrl1DisableScrambling = 1'b0 +) ( + // Dedicated Pads + inout POR_N, // Manual Pad + inout JTAG_TCK, // Manual Pad + inout JTAG_TMS, // Manual Pad + inout JTAG_TDI, // Manual Pad + inout JTAG_TDO, // Manual Pad + inout JTAG_TRST_N, // Manual Pad + inout OTP_EXT_VOLT, // Manual Pad + inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D2, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D3, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_CLK, // Dedicated Pad for spi_host0_sck + inout SPI_HOST_CS_L, // Dedicated Pad for spi_host0_csb + inout SPI_DEV_D0, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D1, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D2, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D3, // Dedicated Pad for spi_device_sd + inout SPI_DEV_CLK, // Dedicated Pad for spi_device_sck + inout SPI_DEV_CS_L, // Dedicated Pad for spi_device_csb + inout SPI_DEV_TPM_CS_L, // Dedicated Pad for spi_device_tpm_csb + inout UART_RX, // Dedicated Pad for uart0_rx + inout UART_TX, // Dedicated Pad for uart0_tx + inout I2C_SCL, // Dedicated Pad for i2c0_scl + inout I2C_SDA, // Dedicated Pad for i2c0_sda + inout GPIO0, // Dedicated Pad for gpio_gpio + inout GPIO1, // Dedicated Pad for gpio_gpio + inout GPIO2, // Dedicated Pad for gpio_gpio + inout GPIO3, // Dedicated Pad for gpio_gpio + inout GPIO4, // Dedicated Pad for gpio_gpio + inout GPIO5, // Dedicated Pad for gpio_gpio + inout GPIO6, // Dedicated Pad for gpio_gpio + inout GPIO7, // Dedicated Pad for gpio_gpio + inout GPIO8, // Dedicated Pad for gpio_gpio + inout GPIO9, // Dedicated Pad for gpio_gpio + inout GPIO10, // Dedicated Pad for gpio_gpio + inout GPIO11, // Dedicated Pad for gpio_gpio + inout GPIO12, // Dedicated Pad for gpio_gpio + inout GPIO13, // Dedicated Pad for gpio_gpio + inout GPIO14, // Dedicated Pad for gpio_gpio + inout GPIO15, // Dedicated Pad for gpio_gpio + inout GPIO16, // Dedicated Pad for gpio_gpio + inout GPIO17, // Dedicated Pad for gpio_gpio + inout GPIO18, // Dedicated Pad for gpio_gpio + inout GPIO19, // Dedicated Pad for gpio_gpio + inout GPIO20, // Dedicated Pad for gpio_gpio + inout GPIO21, // Dedicated Pad for gpio_gpio + inout GPIO22, // Dedicated Pad for gpio_gpio + inout GPIO23, // Dedicated Pad for gpio_gpio + inout GPIO24, // Dedicated Pad for gpio_gpio + inout GPIO25, // Dedicated Pad for gpio_gpio + inout GPIO26, // Dedicated Pad for gpio_gpio + inout GPIO27, // Dedicated Pad for gpio_gpio + inout GPIO28, // Dedicated Pad for gpio_gpio + inout GPIO29, // Dedicated Pad for gpio_gpio + inout GPIO30, // Dedicated Pad for gpio_gpio + inout GPIO31, // Dedicated Pad for gpio_gpio + inout SOC_GPI0, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI1, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI2, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI3, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI4, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI5, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI6, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI7, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI8, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI9, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI10, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI11, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPO0, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO1, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO2, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO3, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO4, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO5, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO6, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO7, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO8, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO9, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO10, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO11, // Dedicated Pad for soc_proxy_soc_gpo + + // Muxed Pads + inout MIO0, // MIO Pad 0 + inout MIO1, // MIO Pad 1 + inout MIO2, // MIO Pad 2 + inout MIO3, // MIO Pad 3 + inout MIO4, // MIO Pad 4 + inout MIO5, // MIO Pad 5 + inout MIO6, // MIO Pad 6 + inout MIO7, // MIO Pad 7 + inout MIO8, // MIO Pad 8 + inout MIO9, // MIO Pad 9 + inout MIO10, // MIO Pad 10 + inout MIO11 // MIO Pad 11 +); + + import top_darjeeling_no_ibex_pkg::*; + import prim_pad_wrapper_pkg::*; + + //////////////////////////// + // Special Signal Indices // + //////////////////////////// + + localparam int Tap0PadIdx = 0; + localparam int Tap1PadIdx = 1; + localparam int Dft0PadIdx = 2; + localparam int Dft1PadIdx = 3; + localparam int TckPadIdx = 4; + localparam int TmsPadIdx = 5; + localparam int TrstNPadIdx = 6; + localparam int TdiPadIdx = 7; + localparam int TdoPadIdx = 8; + + // DFT and Debug signal positions in the pinout. + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + // TODO: check whether there is a better way to pass these USB-specific params + // The use of these indexes is gated behind a parameter, but to synthesize they + // need to exist even if the code-path is never used (pinmux.sv:UsbWkupModuleEn). + // Hence, set to zero. + usb_dp_idx: 0, + usb_dn_idx: 0, + usb_sense_idx: 0, + // Pad types for attribute WARL behavior + dio_pad_type: { + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO uart0_tx + BidirStd, // DIO spi_host0_csb + BidirStd, // DIO spi_host0_sck + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO uart0_rx + InputStd, // DIO spi_device_tpm_csb + InputStd, // DIO spi_device_csb + InputStd, // DIO spi_device_sck + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO i2c0_sda + BidirStd, // DIO i2c0_scl + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd // DIO spi_host0_sd + }, + mio_pad_type: { + BidirStd, // MIO Pad 11 + BidirStd, // MIO Pad 10 + BidirStd, // MIO Pad 9 + BidirStd, // MIO Pad 8 + BidirStd, // MIO Pad 7 + BidirStd, // MIO Pad 6 + BidirStd, // MIO Pad 5 + BidirStd, // MIO Pad 4 + BidirStd, // MIO Pad 3 + BidirStd, // MIO Pad 2 + BidirStd, // MIO Pad 1 + BidirStd // MIO Pad 0 + }, + // Pad scan roles + dio_scan_role: { + scan_role_pkg::DioPadSocGpo11ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo10ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo9ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo8ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo7ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo6ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo5ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo4ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo3ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo2ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo1ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo0ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadUartTxScanRole, // DIO uart0_tx + scan_role_pkg::DioPadSpiHostCsLScanRole, // DIO spi_host0_csb + scan_role_pkg::DioPadSpiHostClkScanRole, // DIO spi_host0_sck + scan_role_pkg::DioPadSocGpi11ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi10ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi9ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi8ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi7ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi6ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi5ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi4ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi3ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi2ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi1ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi0ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadUartRxScanRole, // DIO uart0_rx + scan_role_pkg::DioPadSpiDevTpmCsLScanRole, // DIO spi_device_tpm_csb + scan_role_pkg::DioPadSpiDevCsLScanRole, // DIO spi_device_csb + scan_role_pkg::DioPadSpiDevClkScanRole, // DIO spi_device_sck + scan_role_pkg::DioPadGpio31ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio30ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio29ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio28ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio27ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio26ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio25ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio24ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio23ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio22ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio21ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio20ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio19ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio18ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio17ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio16ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio15ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio14ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio13ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio12ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio11ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio10ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio9ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio8ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio7ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio6ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio5ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio4ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio3ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio2ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio1ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio0ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadI2cSdaScanRole, // DIO i2c0_sda + scan_role_pkg::DioPadI2cSclScanRole, // DIO i2c0_scl + scan_role_pkg::DioPadSpiDevD3ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD2ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD1ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD0ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiHostD3ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD2ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD1ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD0ScanRole // DIO spi_host0_sd + }, + mio_scan_role: { + scan_role_pkg::MioPadMio11ScanRole, + scan_role_pkg::MioPadMio10ScanRole, + scan_role_pkg::MioPadMio9ScanRole, + scan_role_pkg::MioPadMio8ScanRole, + scan_role_pkg::MioPadMio7ScanRole, + scan_role_pkg::MioPadMio6ScanRole, + scan_role_pkg::MioPadMio5ScanRole, + scan_role_pkg::MioPadMio4ScanRole, + scan_role_pkg::MioPadMio3ScanRole, + scan_role_pkg::MioPadMio2ScanRole, + scan_role_pkg::MioPadMio1ScanRole, + scan_role_pkg::MioPadMio0ScanRole + } + }; + + //////////////////////// + // Signal definitions // + //////////////////////// + + + pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr; + pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw; + logic [80-1:0] dio_in_raw; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in; + + logic unused_mio_in_raw; + logic unused_dio_in_raw; + assign unused_mio_in_raw = ^mio_in_raw; + assign unused_dio_in_raw = ^dio_in_raw; + + // Manual pads + logic manual_in_por_n, manual_out_por_n, manual_oe_por_n; + logic manual_in_jtag_tck, manual_out_jtag_tck, manual_oe_jtag_tck; + logic manual_in_jtag_tms, manual_out_jtag_tms, manual_oe_jtag_tms; + logic manual_in_jtag_tdi, manual_out_jtag_tdi, manual_oe_jtag_tdi; + logic manual_in_jtag_tdo, manual_out_jtag_tdo, manual_oe_jtag_tdo; + logic manual_in_jtag_trst_n, manual_out_jtag_trst_n, manual_oe_jtag_trst_n; + logic manual_in_otp_ext_volt, manual_out_otp_ext_volt, manual_oe_otp_ext_volt; + + pad_attr_t manual_attr_por_n; + pad_attr_t manual_attr_jtag_tck; + pad_attr_t manual_attr_jtag_tms; + pad_attr_t manual_attr_jtag_tdi; + pad_attr_t manual_attr_jtag_tdo; + pad_attr_t manual_attr_jtag_trst_n; + pad_attr_t manual_attr_otp_ext_volt; + + + ////////////////////// + // Padring Instance // + ////////////////////// + + ast_pkg::ast_clks_t ast_base_clks; + + // AST signals needed in padring + logic scan_rst_n; + prim_mubi_pkg::mubi4_t scanmode; + + padring #( + // Padring specific counts may differ from pinmux config due + // to custom, stubbed or added pads. + .NDioPads(80), + .NMioPads(12), + .PhysicalPads(1), + .NIoBanks(int'(IoBankCount)), + .DioScanRole ({ + scan_role_pkg::DioPadSocGpo11ScanRole, + scan_role_pkg::DioPadSocGpo10ScanRole, + scan_role_pkg::DioPadSocGpo9ScanRole, + scan_role_pkg::DioPadSocGpo8ScanRole, + scan_role_pkg::DioPadSocGpo7ScanRole, + scan_role_pkg::DioPadSocGpo6ScanRole, + scan_role_pkg::DioPadSocGpo5ScanRole, + scan_role_pkg::DioPadSocGpo4ScanRole, + scan_role_pkg::DioPadSocGpo3ScanRole, + scan_role_pkg::DioPadSocGpo2ScanRole, + scan_role_pkg::DioPadSocGpo1ScanRole, + scan_role_pkg::DioPadSocGpo0ScanRole, + scan_role_pkg::DioPadSocGpi11ScanRole, + scan_role_pkg::DioPadSocGpi10ScanRole, + scan_role_pkg::DioPadSocGpi9ScanRole, + scan_role_pkg::DioPadSocGpi8ScanRole, + scan_role_pkg::DioPadSocGpi7ScanRole, + scan_role_pkg::DioPadSocGpi6ScanRole, + scan_role_pkg::DioPadSocGpi5ScanRole, + scan_role_pkg::DioPadSocGpi4ScanRole, + scan_role_pkg::DioPadSocGpi3ScanRole, + scan_role_pkg::DioPadSocGpi2ScanRole, + scan_role_pkg::DioPadSocGpi1ScanRole, + scan_role_pkg::DioPadSocGpi0ScanRole, + scan_role_pkg::DioPadGpio31ScanRole, + scan_role_pkg::DioPadGpio30ScanRole, + scan_role_pkg::DioPadGpio29ScanRole, + scan_role_pkg::DioPadGpio28ScanRole, + scan_role_pkg::DioPadGpio27ScanRole, + scan_role_pkg::DioPadGpio26ScanRole, + scan_role_pkg::DioPadGpio25ScanRole, + scan_role_pkg::DioPadGpio24ScanRole, + scan_role_pkg::DioPadGpio23ScanRole, + scan_role_pkg::DioPadGpio22ScanRole, + scan_role_pkg::DioPadGpio21ScanRole, + scan_role_pkg::DioPadGpio20ScanRole, + scan_role_pkg::DioPadGpio19ScanRole, + scan_role_pkg::DioPadGpio18ScanRole, + scan_role_pkg::DioPadGpio17ScanRole, + scan_role_pkg::DioPadGpio16ScanRole, + scan_role_pkg::DioPadGpio15ScanRole, + scan_role_pkg::DioPadGpio14ScanRole, + scan_role_pkg::DioPadGpio13ScanRole, + scan_role_pkg::DioPadGpio12ScanRole, + scan_role_pkg::DioPadGpio11ScanRole, + scan_role_pkg::DioPadGpio10ScanRole, + scan_role_pkg::DioPadGpio9ScanRole, + scan_role_pkg::DioPadGpio8ScanRole, + scan_role_pkg::DioPadGpio7ScanRole, + scan_role_pkg::DioPadGpio6ScanRole, + scan_role_pkg::DioPadGpio5ScanRole, + scan_role_pkg::DioPadGpio4ScanRole, + scan_role_pkg::DioPadGpio3ScanRole, + scan_role_pkg::DioPadGpio2ScanRole, + scan_role_pkg::DioPadGpio1ScanRole, + scan_role_pkg::DioPadGpio0ScanRole, + scan_role_pkg::DioPadI2cSdaScanRole, + scan_role_pkg::DioPadI2cSclScanRole, + scan_role_pkg::DioPadUartTxScanRole, + scan_role_pkg::DioPadUartRxScanRole, + scan_role_pkg::DioPadSpiDevTpmCsLScanRole, + scan_role_pkg::DioPadSpiDevCsLScanRole, + scan_role_pkg::DioPadSpiDevClkScanRole, + scan_role_pkg::DioPadSpiDevD3ScanRole, + scan_role_pkg::DioPadSpiDevD2ScanRole, + scan_role_pkg::DioPadSpiDevD1ScanRole, + scan_role_pkg::DioPadSpiDevD0ScanRole, + scan_role_pkg::DioPadSpiHostCsLScanRole, + scan_role_pkg::DioPadSpiHostClkScanRole, + scan_role_pkg::DioPadSpiHostD3ScanRole, + scan_role_pkg::DioPadSpiHostD2ScanRole, + scan_role_pkg::DioPadSpiHostD1ScanRole, + scan_role_pkg::DioPadSpiHostD0ScanRole, + scan_role_pkg::DioPadOtpExtVoltScanRole, + scan_role_pkg::DioPadJtagTrstNScanRole, + scan_role_pkg::DioPadJtagTdoScanRole, + scan_role_pkg::DioPadJtagTdiScanRole, + scan_role_pkg::DioPadJtagTmsScanRole, + scan_role_pkg::DioPadJtagTckScanRole, + scan_role_pkg::DioPadPorNScanRole + }), + .MioScanRole ({ + scan_role_pkg::MioPadMio11ScanRole, + scan_role_pkg::MioPadMio10ScanRole, + scan_role_pkg::MioPadMio9ScanRole, + scan_role_pkg::MioPadMio8ScanRole, + scan_role_pkg::MioPadMio7ScanRole, + scan_role_pkg::MioPadMio6ScanRole, + scan_role_pkg::MioPadMio5ScanRole, + scan_role_pkg::MioPadMio4ScanRole, + scan_role_pkg::MioPadMio3ScanRole, + scan_role_pkg::MioPadMio2ScanRole, + scan_role_pkg::MioPadMio1ScanRole, + scan_role_pkg::MioPadMio0ScanRole + }), + .DioPadBank ({ + IoBankVio, // SOC_GPO11 + IoBankVio, // SOC_GPO10 + IoBankVio, // SOC_GPO9 + IoBankVio, // SOC_GPO8 + IoBankVio, // SOC_GPO7 + IoBankVio, // SOC_GPO6 + IoBankVio, // SOC_GPO5 + IoBankVio, // SOC_GPO4 + IoBankVio, // SOC_GPO3 + IoBankVio, // SOC_GPO2 + IoBankVio, // SOC_GPO1 + IoBankVio, // SOC_GPO0 + IoBankVio, // SOC_GPI11 + IoBankVio, // SOC_GPI10 + IoBankVio, // SOC_GPI9 + IoBankVio, // SOC_GPI8 + IoBankVio, // SOC_GPI7 + IoBankVio, // SOC_GPI6 + IoBankVio, // SOC_GPI5 + IoBankVio, // SOC_GPI4 + IoBankVio, // SOC_GPI3 + IoBankVio, // SOC_GPI2 + IoBankVio, // SOC_GPI1 + IoBankVio, // SOC_GPI0 + IoBankVio, // GPIO31 + IoBankVio, // GPIO30 + IoBankVio, // GPIO29 + IoBankVio, // GPIO28 + IoBankVio, // GPIO27 + IoBankVio, // GPIO26 + IoBankVio, // GPIO25 + IoBankVio, // GPIO24 + IoBankVio, // GPIO23 + IoBankVio, // GPIO22 + IoBankVio, // GPIO21 + IoBankVio, // GPIO20 + IoBankVio, // GPIO19 + IoBankVio, // GPIO18 + IoBankVio, // GPIO17 + IoBankVio, // GPIO16 + IoBankVio, // GPIO15 + IoBankVio, // GPIO14 + IoBankVio, // GPIO13 + IoBankVio, // GPIO12 + IoBankVio, // GPIO11 + IoBankVio, // GPIO10 + IoBankVio, // GPIO9 + IoBankVio, // GPIO8 + IoBankVio, // GPIO7 + IoBankVio, // GPIO6 + IoBankVio, // GPIO5 + IoBankVio, // GPIO4 + IoBankVio, // GPIO3 + IoBankVio, // GPIO2 + IoBankVio, // GPIO1 + IoBankVio, // GPIO0 + IoBankVio, // I2C_SDA + IoBankVio, // I2C_SCL + IoBankVio, // UART_TX + IoBankVio, // UART_RX + IoBankVio, // SPI_DEV_TPM_CS_L + IoBankVio, // SPI_DEV_CS_L + IoBankVio, // SPI_DEV_CLK + IoBankVio, // SPI_DEV_D3 + IoBankVio, // SPI_DEV_D2 + IoBankVio, // SPI_DEV_D1 + IoBankVio, // SPI_DEV_D0 + IoBankVio, // SPI_HOST_CS_L + IoBankVio, // SPI_HOST_CLK + IoBankVio, // SPI_HOST_D3 + IoBankVio, // SPI_HOST_D2 + IoBankVio, // SPI_HOST_D1 + IoBankVio, // SPI_HOST_D0 + IoBankVio, // OTP_EXT_VOLT + IoBankVio, // JTAG_TRST_N + IoBankVio, // JTAG_TDO + IoBankVio, // JTAG_TDI + IoBankVio, // JTAG_TMS + IoBankVio, // JTAG_TCK + IoBankVio // POR_N + }), + .MioPadBank ({ + IoBankVio, // MIO11 + IoBankVio, // MIO10 + IoBankVio, // MIO9 + IoBankVio, // MIO8 + IoBankVio, // MIO7 + IoBankVio, // MIO6 + IoBankVio, // MIO5 + IoBankVio, // MIO4 + IoBankVio, // MIO3 + IoBankVio, // MIO2 + IoBankVio, // MIO1 + IoBankVio // MIO0 + }), + .DioPadType ({ + BidirStd, // SOC_GPO11 + BidirStd, // SOC_GPO10 + BidirStd, // SOC_GPO9 + BidirStd, // SOC_GPO8 + BidirStd, // SOC_GPO7 + BidirStd, // SOC_GPO6 + BidirStd, // SOC_GPO5 + BidirStd, // SOC_GPO4 + BidirStd, // SOC_GPO3 + BidirStd, // SOC_GPO2 + BidirStd, // SOC_GPO1 + BidirStd, // SOC_GPO0 + InputStd, // SOC_GPI11 + InputStd, // SOC_GPI10 + InputStd, // SOC_GPI9 + InputStd, // SOC_GPI8 + InputStd, // SOC_GPI7 + InputStd, // SOC_GPI6 + InputStd, // SOC_GPI5 + InputStd, // SOC_GPI4 + InputStd, // SOC_GPI3 + InputStd, // SOC_GPI2 + InputStd, // SOC_GPI1 + InputStd, // SOC_GPI0 + BidirStd, // GPIO31 + BidirStd, // GPIO30 + BidirStd, // GPIO29 + BidirStd, // GPIO28 + BidirStd, // GPIO27 + BidirStd, // GPIO26 + BidirStd, // GPIO25 + BidirStd, // GPIO24 + BidirStd, // GPIO23 + BidirStd, // GPIO22 + BidirStd, // GPIO21 + BidirStd, // GPIO20 + BidirStd, // GPIO19 + BidirStd, // GPIO18 + BidirStd, // GPIO17 + BidirStd, // GPIO16 + BidirStd, // GPIO15 + BidirStd, // GPIO14 + BidirStd, // GPIO13 + BidirStd, // GPIO12 + BidirStd, // GPIO11 + BidirStd, // GPIO10 + BidirStd, // GPIO9 + BidirStd, // GPIO8 + BidirStd, // GPIO7 + BidirStd, // GPIO6 + BidirStd, // GPIO5 + BidirStd, // GPIO4 + BidirStd, // GPIO3 + BidirStd, // GPIO2 + BidirStd, // GPIO1 + BidirStd, // GPIO0 + BidirStd, // I2C_SDA + BidirStd, // I2C_SCL + BidirStd, // UART_TX + InputStd, // UART_RX + InputStd, // SPI_DEV_TPM_CS_L + InputStd, // SPI_DEV_CS_L + InputStd, // SPI_DEV_CLK + BidirStd, // SPI_DEV_D3 + BidirStd, // SPI_DEV_D2 + BidirStd, // SPI_DEV_D1 + BidirStd, // SPI_DEV_D0 + BidirStd, // SPI_HOST_CS_L + BidirStd, // SPI_HOST_CLK + BidirStd, // SPI_HOST_D3 + BidirStd, // SPI_HOST_D2 + BidirStd, // SPI_HOST_D1 + BidirStd, // SPI_HOST_D0 + AnalogIn1, // OTP_EXT_VOLT + InputStd, // JTAG_TRST_N + BidirStd, // JTAG_TDO + InputStd, // JTAG_TDI + InputStd, // JTAG_TMS + InputStd, // JTAG_TCK + InputStd // POR_N + }), + .MioPadType ({ + BidirStd, // MIO11 + BidirStd, // MIO10 + BidirStd, // MIO9 + BidirStd, // MIO8 + BidirStd, // MIO7 + BidirStd, // MIO6 + BidirStd, // MIO5 + BidirStd, // MIO4 + BidirStd, // MIO3 + BidirStd, // MIO2 + BidirStd, // MIO1 + BidirStd // MIO0 + }) + ) u_padring ( + // This is only used for scan and DFT purposes + .clk_scan_i ( ast_base_clks.clk_sys ), + .scanmode_i ( scanmode ), + .dio_in_raw_o ( dio_in_raw ), + // Chip IOs + .dio_pad_io ({ + SOC_GPO11, + SOC_GPO10, + SOC_GPO9, + SOC_GPO8, + SOC_GPO7, + SOC_GPO6, + SOC_GPO5, + SOC_GPO4, + SOC_GPO3, + SOC_GPO2, + SOC_GPO1, + SOC_GPO0, + SOC_GPI11, + SOC_GPI10, + SOC_GPI9, + SOC_GPI8, + SOC_GPI7, + SOC_GPI6, + SOC_GPI5, + SOC_GPI4, + SOC_GPI3, + SOC_GPI2, + SOC_GPI1, + SOC_GPI0, + GPIO31, + GPIO30, + GPIO29, + GPIO28, + GPIO27, + GPIO26, + GPIO25, + GPIO24, + GPIO23, + GPIO22, + GPIO21, + GPIO20, + GPIO19, + GPIO18, + GPIO17, + GPIO16, + GPIO15, + GPIO14, + GPIO13, + GPIO12, + GPIO11, + GPIO10, + GPIO9, + GPIO8, + GPIO7, + GPIO6, + GPIO5, + GPIO4, + GPIO3, + GPIO2, + GPIO1, + GPIO0, + I2C_SDA, + I2C_SCL, + UART_TX, + UART_RX, + SPI_DEV_TPM_CS_L, + SPI_DEV_CS_L, + SPI_DEV_CLK, + SPI_DEV_D3, + SPI_DEV_D2, + SPI_DEV_D1, + SPI_DEV_D0, + SPI_HOST_CS_L, + SPI_HOST_CLK, + SPI_HOST_D3, + SPI_HOST_D2, + SPI_HOST_D1, + SPI_HOST_D0, + OTP_EXT_VOLT, + JTAG_TRST_N, + JTAG_TDO, + JTAG_TDI, + JTAG_TMS, + JTAG_TCK, + POR_N + }), + + .mio_pad_io ({ + MIO11, + MIO10, + MIO9, + MIO8, + MIO7, + MIO6, + MIO5, + MIO4, + MIO3, + MIO2, + MIO1, + MIO0 + }), + + // Core-facing + .dio_in_o ({ + dio_in[DioSocProxySocGpo11], + dio_in[DioSocProxySocGpo10], + dio_in[DioSocProxySocGpo9], + dio_in[DioSocProxySocGpo8], + dio_in[DioSocProxySocGpo7], + dio_in[DioSocProxySocGpo6], + dio_in[DioSocProxySocGpo5], + dio_in[DioSocProxySocGpo4], + dio_in[DioSocProxySocGpo3], + dio_in[DioSocProxySocGpo2], + dio_in[DioSocProxySocGpo1], + dio_in[DioSocProxySocGpo0], + dio_in[DioSocProxySocGpi11], + dio_in[DioSocProxySocGpi10], + dio_in[DioSocProxySocGpi9], + dio_in[DioSocProxySocGpi8], + dio_in[DioSocProxySocGpi7], + dio_in[DioSocProxySocGpi6], + dio_in[DioSocProxySocGpi5], + dio_in[DioSocProxySocGpi4], + dio_in[DioSocProxySocGpi3], + dio_in[DioSocProxySocGpi2], + dio_in[DioSocProxySocGpi1], + dio_in[DioSocProxySocGpi0], + dio_in[DioGpioGpio31], + dio_in[DioGpioGpio30], + dio_in[DioGpioGpio29], + dio_in[DioGpioGpio28], + dio_in[DioGpioGpio27], + dio_in[DioGpioGpio26], + dio_in[DioGpioGpio25], + dio_in[DioGpioGpio24], + dio_in[DioGpioGpio23], + dio_in[DioGpioGpio22], + dio_in[DioGpioGpio21], + dio_in[DioGpioGpio20], + dio_in[DioGpioGpio19], + dio_in[DioGpioGpio18], + dio_in[DioGpioGpio17], + dio_in[DioGpioGpio16], + dio_in[DioGpioGpio15], + dio_in[DioGpioGpio14], + dio_in[DioGpioGpio13], + dio_in[DioGpioGpio12], + dio_in[DioGpioGpio11], + dio_in[DioGpioGpio10], + dio_in[DioGpioGpio9], + dio_in[DioGpioGpio8], + dio_in[DioGpioGpio7], + dio_in[DioGpioGpio6], + dio_in[DioGpioGpio5], + dio_in[DioGpioGpio4], + dio_in[DioGpioGpio3], + dio_in[DioGpioGpio2], + dio_in[DioGpioGpio1], + dio_in[DioGpioGpio0], + dio_in[DioI2c0Sda], + dio_in[DioI2c0Scl], + dio_in[DioUart0Tx], + dio_in[DioUart0Rx], + dio_in[DioSpiDeviceTpmCsb], + dio_in[DioSpiDeviceCsb], + dio_in[DioSpiDeviceSck], + dio_in[DioSpiDeviceSd3], + dio_in[DioSpiDeviceSd2], + dio_in[DioSpiDeviceSd1], + dio_in[DioSpiDeviceSd0], + dio_in[DioSpiHost0Csb], + dio_in[DioSpiHost0Sck], + dio_in[DioSpiHost0Sd3], + dio_in[DioSpiHost0Sd2], + dio_in[DioSpiHost0Sd1], + dio_in[DioSpiHost0Sd0], + manual_in_otp_ext_volt, + manual_in_jtag_trst_n, + manual_in_jtag_tdo, + manual_in_jtag_tdi, + manual_in_jtag_tms, + manual_in_jtag_tck, + manual_in_por_n + }), + .dio_out_i ({ + dio_out[DioSocProxySocGpo11], + dio_out[DioSocProxySocGpo10], + dio_out[DioSocProxySocGpo9], + dio_out[DioSocProxySocGpo8], + dio_out[DioSocProxySocGpo7], + dio_out[DioSocProxySocGpo6], + dio_out[DioSocProxySocGpo5], + dio_out[DioSocProxySocGpo4], + dio_out[DioSocProxySocGpo3], + dio_out[DioSocProxySocGpo2], + dio_out[DioSocProxySocGpo1], + dio_out[DioSocProxySocGpo0], + dio_out[DioSocProxySocGpi11], + dio_out[DioSocProxySocGpi10], + dio_out[DioSocProxySocGpi9], + dio_out[DioSocProxySocGpi8], + dio_out[DioSocProxySocGpi7], + dio_out[DioSocProxySocGpi6], + dio_out[DioSocProxySocGpi5], + dio_out[DioSocProxySocGpi4], + dio_out[DioSocProxySocGpi3], + dio_out[DioSocProxySocGpi2], + dio_out[DioSocProxySocGpi1], + dio_out[DioSocProxySocGpi0], + dio_out[DioGpioGpio31], + dio_out[DioGpioGpio30], + dio_out[DioGpioGpio29], + dio_out[DioGpioGpio28], + dio_out[DioGpioGpio27], + dio_out[DioGpioGpio26], + dio_out[DioGpioGpio25], + dio_out[DioGpioGpio24], + dio_out[DioGpioGpio23], + dio_out[DioGpioGpio22], + dio_out[DioGpioGpio21], + dio_out[DioGpioGpio20], + dio_out[DioGpioGpio19], + dio_out[DioGpioGpio18], + dio_out[DioGpioGpio17], + dio_out[DioGpioGpio16], + dio_out[DioGpioGpio15], + dio_out[DioGpioGpio14], + dio_out[DioGpioGpio13], + dio_out[DioGpioGpio12], + dio_out[DioGpioGpio11], + dio_out[DioGpioGpio10], + dio_out[DioGpioGpio9], + dio_out[DioGpioGpio8], + dio_out[DioGpioGpio7], + dio_out[DioGpioGpio6], + dio_out[DioGpioGpio5], + dio_out[DioGpioGpio4], + dio_out[DioGpioGpio3], + dio_out[DioGpioGpio2], + dio_out[DioGpioGpio1], + dio_out[DioGpioGpio0], + dio_out[DioI2c0Sda], + dio_out[DioI2c0Scl], + dio_out[DioUart0Tx], + dio_out[DioUart0Rx], + dio_out[DioSpiDeviceTpmCsb], + dio_out[DioSpiDeviceCsb], + dio_out[DioSpiDeviceSck], + dio_out[DioSpiDeviceSd3], + dio_out[DioSpiDeviceSd2], + dio_out[DioSpiDeviceSd1], + dio_out[DioSpiDeviceSd0], + dio_out[DioSpiHost0Csb], + dio_out[DioSpiHost0Sck], + dio_out[DioSpiHost0Sd3], + dio_out[DioSpiHost0Sd2], + dio_out[DioSpiHost0Sd1], + dio_out[DioSpiHost0Sd0], + manual_out_otp_ext_volt, + manual_out_jtag_trst_n, + manual_out_jtag_tdo, + manual_out_jtag_tdi, + manual_out_jtag_tms, + manual_out_jtag_tck, + manual_out_por_n + }), + .dio_oe_i ({ + dio_oe[DioSocProxySocGpo11], + dio_oe[DioSocProxySocGpo10], + dio_oe[DioSocProxySocGpo9], + dio_oe[DioSocProxySocGpo8], + dio_oe[DioSocProxySocGpo7], + dio_oe[DioSocProxySocGpo6], + dio_oe[DioSocProxySocGpo5], + dio_oe[DioSocProxySocGpo4], + dio_oe[DioSocProxySocGpo3], + dio_oe[DioSocProxySocGpo2], + dio_oe[DioSocProxySocGpo1], + dio_oe[DioSocProxySocGpo0], + dio_oe[DioSocProxySocGpi11], + dio_oe[DioSocProxySocGpi10], + dio_oe[DioSocProxySocGpi9], + dio_oe[DioSocProxySocGpi8], + dio_oe[DioSocProxySocGpi7], + dio_oe[DioSocProxySocGpi6], + dio_oe[DioSocProxySocGpi5], + dio_oe[DioSocProxySocGpi4], + dio_oe[DioSocProxySocGpi3], + dio_oe[DioSocProxySocGpi2], + dio_oe[DioSocProxySocGpi1], + dio_oe[DioSocProxySocGpi0], + dio_oe[DioGpioGpio31], + dio_oe[DioGpioGpio30], + dio_oe[DioGpioGpio29], + dio_oe[DioGpioGpio28], + dio_oe[DioGpioGpio27], + dio_oe[DioGpioGpio26], + dio_oe[DioGpioGpio25], + dio_oe[DioGpioGpio24], + dio_oe[DioGpioGpio23], + dio_oe[DioGpioGpio22], + dio_oe[DioGpioGpio21], + dio_oe[DioGpioGpio20], + dio_oe[DioGpioGpio19], + dio_oe[DioGpioGpio18], + dio_oe[DioGpioGpio17], + dio_oe[DioGpioGpio16], + dio_oe[DioGpioGpio15], + dio_oe[DioGpioGpio14], + dio_oe[DioGpioGpio13], + dio_oe[DioGpioGpio12], + dio_oe[DioGpioGpio11], + dio_oe[DioGpioGpio10], + dio_oe[DioGpioGpio9], + dio_oe[DioGpioGpio8], + dio_oe[DioGpioGpio7], + dio_oe[DioGpioGpio6], + dio_oe[DioGpioGpio5], + dio_oe[DioGpioGpio4], + dio_oe[DioGpioGpio3], + dio_oe[DioGpioGpio2], + dio_oe[DioGpioGpio1], + dio_oe[DioGpioGpio0], + dio_oe[DioI2c0Sda], + dio_oe[DioI2c0Scl], + dio_oe[DioUart0Tx], + dio_oe[DioUart0Rx], + dio_oe[DioSpiDeviceTpmCsb], + dio_oe[DioSpiDeviceCsb], + dio_oe[DioSpiDeviceSck], + dio_oe[DioSpiDeviceSd3], + dio_oe[DioSpiDeviceSd2], + dio_oe[DioSpiDeviceSd1], + dio_oe[DioSpiDeviceSd0], + dio_oe[DioSpiHost0Csb], + dio_oe[DioSpiHost0Sck], + dio_oe[DioSpiHost0Sd3], + dio_oe[DioSpiHost0Sd2], + dio_oe[DioSpiHost0Sd1], + dio_oe[DioSpiHost0Sd0], + manual_oe_otp_ext_volt, + manual_oe_jtag_trst_n, + manual_oe_jtag_tdo, + manual_oe_jtag_tdi, + manual_oe_jtag_tms, + manual_oe_jtag_tck, + manual_oe_por_n + }), + .dio_attr_i ({ + dio_attr[DioSocProxySocGpo11], + dio_attr[DioSocProxySocGpo10], + dio_attr[DioSocProxySocGpo9], + dio_attr[DioSocProxySocGpo8], + dio_attr[DioSocProxySocGpo7], + dio_attr[DioSocProxySocGpo6], + dio_attr[DioSocProxySocGpo5], + dio_attr[DioSocProxySocGpo4], + dio_attr[DioSocProxySocGpo3], + dio_attr[DioSocProxySocGpo2], + dio_attr[DioSocProxySocGpo1], + dio_attr[DioSocProxySocGpo0], + dio_attr[DioSocProxySocGpi11], + dio_attr[DioSocProxySocGpi10], + dio_attr[DioSocProxySocGpi9], + dio_attr[DioSocProxySocGpi8], + dio_attr[DioSocProxySocGpi7], + dio_attr[DioSocProxySocGpi6], + dio_attr[DioSocProxySocGpi5], + dio_attr[DioSocProxySocGpi4], + dio_attr[DioSocProxySocGpi3], + dio_attr[DioSocProxySocGpi2], + dio_attr[DioSocProxySocGpi1], + dio_attr[DioSocProxySocGpi0], + dio_attr[DioGpioGpio31], + dio_attr[DioGpioGpio30], + dio_attr[DioGpioGpio29], + dio_attr[DioGpioGpio28], + dio_attr[DioGpioGpio27], + dio_attr[DioGpioGpio26], + dio_attr[DioGpioGpio25], + dio_attr[DioGpioGpio24], + dio_attr[DioGpioGpio23], + dio_attr[DioGpioGpio22], + dio_attr[DioGpioGpio21], + dio_attr[DioGpioGpio20], + dio_attr[DioGpioGpio19], + dio_attr[DioGpioGpio18], + dio_attr[DioGpioGpio17], + dio_attr[DioGpioGpio16], + dio_attr[DioGpioGpio15], + dio_attr[DioGpioGpio14], + dio_attr[DioGpioGpio13], + dio_attr[DioGpioGpio12], + dio_attr[DioGpioGpio11], + dio_attr[DioGpioGpio10], + dio_attr[DioGpioGpio9], + dio_attr[DioGpioGpio8], + dio_attr[DioGpioGpio7], + dio_attr[DioGpioGpio6], + dio_attr[DioGpioGpio5], + dio_attr[DioGpioGpio4], + dio_attr[DioGpioGpio3], + dio_attr[DioGpioGpio2], + dio_attr[DioGpioGpio1], + dio_attr[DioGpioGpio0], + dio_attr[DioI2c0Sda], + dio_attr[DioI2c0Scl], + dio_attr[DioUart0Tx], + dio_attr[DioUart0Rx], + dio_attr[DioSpiDeviceTpmCsb], + dio_attr[DioSpiDeviceCsb], + dio_attr[DioSpiDeviceSck], + dio_attr[DioSpiDeviceSd3], + dio_attr[DioSpiDeviceSd2], + dio_attr[DioSpiDeviceSd1], + dio_attr[DioSpiDeviceSd0], + dio_attr[DioSpiHost0Csb], + dio_attr[DioSpiHost0Sck], + dio_attr[DioSpiHost0Sd3], + dio_attr[DioSpiHost0Sd2], + dio_attr[DioSpiHost0Sd1], + dio_attr[DioSpiHost0Sd0], + manual_attr_otp_ext_volt, + manual_attr_jtag_trst_n, + manual_attr_jtag_tdo, + manual_attr_jtag_tdi, + manual_attr_jtag_tms, + manual_attr_jtag_tck, + manual_attr_por_n + }), + + .mio_in_o (mio_in[11:0]), + .mio_out_i (mio_out[11:0]), + .mio_oe_i (mio_oe[11:0]), + .mio_attr_i (mio_attr[11:0]), + .mio_in_raw_o (mio_in_raw[11:0]) + ); + + + + + ////////////////////////////////// + // AST - Common for all targets // + ////////////////////////////////// + + // pwrmgr interface + pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; + pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; + + // assorted ast status + ast_pkg::ast_pwst_t ast_pwst; + + // TLUL interface + tlul_pkg::tl_h2d_t base_ast_bus; + tlul_pkg::tl_d2h_t ast_base_bus; + + // synchronization clocks / rests + clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; + rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets; + + // external clock + logic ext_clk; + + // monitored clock + logic sck_monitor; + + // debug policy bus + soc_dbg_ctrl_pkg::soc_dbg_policy_t soc_dbg_policy_bus; + + // observe interface + logic [7:0] otp_obs; + ast_pkg::ast_obs_ctrl_t obs_ctrl; + + // otp power sequence + otp_macro_pkg::otp_ast_req_t otp_macro_pwr_seq; + otp_macro_pkg::otp_ast_rsp_t otp_macro_pwr_seq_h; + + // OTP DFT configuration + otp_macro_pkg::otp_cfg_t otp_cfg; + assign otp_cfg = otp_macro_pkg::OTP_CFG_DEFAULT; + + // entropy source interface + logic es_rng_enable, es_rng_valid; + logic [ast_pkg::EntropyStreams-1:0] es_rng_bit; + + // alerts interface + ast_pkg::ast_alert_rsp_t ast_alert_rsp; + ast_pkg::ast_alert_req_t ast_alert_req; + assign ast_alert_rsp = '0; + + // clock bypass req/ack + prim_mubi_pkg::mubi4_t io_clk_byp_req; + prim_mubi_pkg::mubi4_t io_clk_byp_ack; + prim_mubi_pkg::mubi4_t all_clk_byp_req; + prim_mubi_pkg::mubi4_t all_clk_byp_ack; + prim_mubi_pkg::mubi4_t hi_speed_sel; + prim_mubi_pkg::mubi4_t div_step_down_req; + + // DFT connections + logic scan_en; + lc_ctrl_pkg::lc_tx_t lc_dft_en; + + // Jitter enable + prim_mubi_pkg::mubi4_t jen; + + // reset domain connections + import rstmgr_pkg::PowerDomains; + import rstmgr_pkg::DomainAonSel; + import rstmgr_pkg::Domain0Sel; + + // Memory configuration connections + ast_pkg::spm_rm_t ast_ram_1p_cfg; + ast_pkg::spm_rm_t ast_rf_cfg; + ast_pkg::spm_rm_t ast_rom_cfg; + ast_pkg::dpm_rm_t ast_ram_2p_fcfg; + ast_pkg::dpm_rm_t ast_ram_2p_lcfg; + + // conversion from ast structure to memory centric structures + prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg; + assign ram_1p_cfg = '{ + ram_cfg: '{ + test: ast_ram_1p_cfg.test, + cfg_en: ast_ram_1p_cfg.marg_en, + cfg: ast_ram_1p_cfg.marg + }, + rf_cfg: '{ + test: ast_rf_cfg.test, + cfg_en: ast_rf_cfg.marg_en, + cfg: ast_rf_cfg.marg + } + }; + + logic unused_usb_ram_2p_cfg; + assign unused_usb_ram_2p_cfg = ^{ast_ram_2p_fcfg.marg_en_a, + ast_ram_2p_fcfg.marg_a, + ast_ram_2p_fcfg.test_a, + ast_ram_2p_fcfg.marg_en_b, + ast_ram_2p_fcfg.marg_b, + ast_ram_2p_fcfg.test_b}; + + // this maps as follows: + // assign spi_ram_2p_cfg = {10'h000, ram_2p_cfg_i.a_ram_lcfg, ram_2p_cfg_i.b_ram_lcfg}; + prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg; + assign spi_ram_2p_cfg = '{ + a_ram_lcfg: '{ + test: ast_ram_2p_lcfg.test_a, + cfg_en: ast_ram_2p_lcfg.marg_en_a, + cfg: ast_ram_2p_lcfg.marg_a + }, + b_ram_lcfg: '{ + test: ast_ram_2p_lcfg.test_b, + cfg_en: ast_ram_2p_lcfg.marg_en_b, + cfg: ast_ram_2p_lcfg.marg_b + }, + default: '0 + }; + + prim_rom_pkg::rom_cfg_t rom_ctrl0_cfg; + prim_rom_pkg::rom_cfg_t rom_ctrl1_cfg; + + assign rom_ctrl0_cfg = '{ + test: ast_rom_cfg.test, + cfg_en: ast_rom_cfg.marg_en, + cfg: ast_rom_cfg.marg + }; + assign rom_ctrl1_cfg = '{ + test: ast_rom_cfg.test, + cfg_en: ast_rom_cfg.marg_en, + cfg: ast_rom_cfg.marg + }; + + ////////////////////////////////// + // AST - Custom for targets // + ////////////////////////////////// + + + assign ast_base_pwr.main_pok = ast_pwst.main_pok; + + logic [rstmgr_pkg::PowerDomains-1:0] por_n; + assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok}; + + + // external clock comes in at a fixed position + assign ext_clk = mio_in_raw[MioPadMio11]; + + wire unused_t0, unused_t1; + assign unused_t0 = 1'b0; + assign unused_t1 = 1'b0; + + // AST does not use all clocks / resets forwarded to it + logic unused_slow_clk_en; + assign unused_slow_clk_en = base_ast_pwr.slow_clk_en; + + logic unused_pwr_clamp; + assign unused_pwr_clamp = base_ast_pwr.pwr_clamp; + + + prim_mubi_pkg::mubi4_t ast_init_done; + + ast #( + .AdcChannels(ast_pkg::AdcChannels), + .AdcDataWidth(ast_pkg::AdcDataWidth), + .UsbCalibWidth(ast_pkg::UsbCalibWidth), + .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth), + .Pad2AstInWidth(ast_pkg::Pad2AstInWidth) + ) u_ast ( + // external POR + .por_ni ( manual_in_por_n ), + + // USB IO Pull-up Calibration Setting + .usb_io_pu_cal_o ( ), + + // adc + .adc_a0_ai ( '0 ), + .adc_a1_ai ( '0 ), + + // Direct short to PAD + .ast2pad_t0_ao ( unused_t0 ), + .ast2pad_t1_ao ( unused_t1 ), + // clocks and resets supplied for detection + .sns_clks_i ( clkmgr_aon_clocks ), + .sns_rsts_i ( rstmgr_aon_resets ), + .sns_spi_ext_clk_i ( sck_monitor ), + // tlul + .tl_i ( base_ast_bus ), + .tl_o ( ast_base_bus ), + // init done indication + .ast_init_done_o ( ast_init_done ), + // buffered clocks & resets + .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_infra), + .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_peri), + .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_adc_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), + .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_rng_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .clk_ast_ext_i ( ext_clk ), + + // pok test for FPGA + .vcc_supp_i ( 1'b1 ), + .vcaon_supp_i ( 1'b1 ), + .vcmain_supp_i ( 1'b1 ), + .vioa_supp_i ( 1'b1 ), + .viob_supp_i ( 1'b1 ), + // pok + .ast_pwst_o ( ast_pwst ), + .ast_pwst_h_o ( ), + // main regulator + .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ), + .main_pd_ni ( base_ast_pwr.main_pd_n ), + // pdm control (flash)/otp + .flash_power_down_h_o ( ), + .flash_power_ready_h_o ( ), + .otp_power_seq_i ( otp_macro_pwr_seq ), + .otp_power_seq_h_o ( otp_macro_pwr_seq_h ), + // system source clock + .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ), + // need to add function in clkmgr + .clk_src_sys_jen_i ( jen ), + .clk_src_sys_o ( ast_base_clks.clk_sys ), + .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ), + // aon source clock + .clk_src_aon_o ( ast_base_clks.clk_aon ), + .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ), + // io source clock + .clk_src_io_en_i ( base_ast_pwr.io_clk_en ), + .clk_src_io_o ( ast_base_clks.clk_io ), + .clk_src_io_val_o ( ast_base_pwr.io_clk_val ), + .clk_src_io_48m_o ( div_step_down_req ), + // usb source clock + .usb_ref_pulse_i ( '0 ), + .usb_ref_val_i ( '0 ), + .clk_src_usb_en_i ( '0 ), + .clk_src_usb_o ( ), + .clk_src_usb_val_o ( ), + // adc + .adc_pd_i ( '0 ), + .adc_chnsel_i ( '0 ), + .adc_d_o ( ), + .adc_d_val_o ( ), + // rng + .rng_en_i ( es_rng_enable ), + .rng_fips_i ( es_rng_fips ), + .rng_val_o ( es_rng_valid ), + .rng_b_o ( es_rng_bit ), + // alerts + .alert_rsp_i ( ast_alert_rsp ), + .alert_req_o ( ast_alert_req ), + // dft + .lc_dft_en_i ( lc_dft_en ), + .fla_obs_i ( '0 ), + .usb_obs_i ( '0 ), + .otp_obs_i ( otp_obs ), + .otm_obs_i ( '0 ), + .obs_ctrl_o ( obs_ctrl ), + // pinmux related + .padmux2ast_i ( '0 ), + .ast2padmux_o ( ), + .ext_freq_is_96m_i ( hi_speed_sel ), + .all_clk_byp_req_i ( all_clk_byp_req ), + .all_clk_byp_ack_o ( all_clk_byp_ack ), + .io_clk_byp_req_i ( io_clk_byp_req ), + .io_clk_byp_ack_o ( io_clk_byp_ack ), + .flash_bist_en_o ( ), + // Memory configuration connections + .dpram_rmf_o ( ast_ram_2p_fcfg ), + .dpram_rml_o ( ast_ram_2p_lcfg ), + .spram_rm_o ( ast_ram_1p_cfg ), + .sprgf_rm_o ( ast_rf_cfg ), + .sprom_rm_o ( ast_rom_cfg ), + // scan + .dft_scan_md_o ( scanmode ), + .scan_shift_en_o ( scan_en ), + .scan_reset_no ( scan_rst_n ) + ); + + ////////////////// + // TAP Instance // + ////////////////// + + tlul_pkg::tl_h2d_t dmi_h2d; + tlul_pkg::tl_d2h_t dmi_d2h; + jtag_pkg::jtag_req_t jtag_req; + jtag_pkg::jtag_rsp_t jtag_rsp; + + assign jtag_req.tck = manual_in_jtag_tck; + assign jtag_req.tms = manual_in_jtag_tms; + assign jtag_req.trst_n = manual_in_jtag_trst_n; + assign jtag_req.tdi = manual_in_jtag_tdi; + + assign manual_out_jtag_tck = '0; + assign manual_out_jtag_tms = '0; + assign manual_out_jtag_trst_n = '0; + assign manual_out_jtag_tdi = '0; + assign manual_oe_jtag_tck = '0; + assign manual_oe_jtag_tms = '0; + assign manual_oe_jtag_trst_n = '0; + assign manual_oe_jtag_tdi = '0; + assign manual_attr_jtag_tck = '0; + assign manual_attr_jtag_tms = '0; + assign manual_attr_jtag_trst_n = '0; + assign manual_attr_jtag_tdi = '0; + + assign manual_out_jtag_tdo = jtag_rsp.tdo; + assign manual_oe_jtag_tdo = jtag_rsp.tdo_oe; + assign manual_attr_jtag_tdo = '0; + + logic unused_manual_jtag_sigs; + assign unused_manual_jtag_sigs = ^{ + manual_in_jtag_tdo + }; + + tlul_jtag_dtm #( + .IdcodeValue(jtag_id_pkg::LC_DM_COMBINED_JTAG_IDCODE), + // Notes: + // - one RV_DM instance uses 9bits + // - our crossbar tooling expects individual IPs to be spaced apart by 12bits at the moment + // - the DMI address shifted through jtag is a word address and hence 2bits smaller than this + // - setting this to 18bits effectively gives us 2^6 = 64 addressable 12bit ranges + .NumDmiByteAbits(18) + ) u_tlul_jtag_dtm ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), + .jtag_i (jtag_req), + .jtag_o (jtag_rsp), + .scan_rst_ni(scan_rst_n), + .scanmode_i (scanmode), + .tl_h2d_o (dmi_h2d), + .tl_d2h_i (dmi_d2h) + ); + + // TODO: Resolve this and wire it up. + tlul_pkg::tl_h2d_t ctn_misc_tl_h2d_i; + assign ctn_misc_tl_h2d_i = tlul_pkg::TL_H2D_DEFAULT; + tlul_pkg::tl_d2h_t ctn_misc_tl_d2h_o; + + // TODO: Over/ride/ all access range checks for now. + prim_mubi_pkg::mubi8_t ac_range_check_overwrite_i; + assign ac_range_check_overwrite_i = prim_mubi_pkg::MuBi8True; + + // TODO: External RACL error input. + top_racl_pkg::racl_error_log_t ext_racl_error; + assign ext_racl_error = '0; + + //////////////// + // CTN M-to-1 // + //////////////// + + tlul_pkg::tl_h2d_t ctn_tl_h2d[2]; + tlul_pkg::tl_d2h_t ctn_tl_d2h[2]; + //TODO: Resolve this and wire it up. + assign ctn_tl_h2d[1] = tlul_pkg::TL_H2D_DEFAULT; + + tlul_pkg::tl_h2d_t ctn_sm1_to_s1n_tl_h2d; + tlul_pkg::tl_d2h_t ctn_sm1_to_s1n_tl_d2h; + + tlul_socket_m1 #( + .M (2), + .HReqPass ({2{1'b1}}), + .HRspPass ({2{1'b1}}), + .HReqDepth ({2{4'd0}}), + .HRspDepth ({2{4'd0}}), + .DReqPass (1'b1), + .DRspPass (1'b1), + .DReqDepth (4'd0), + .DRspDepth (4'd0) + ) u_ctn_sm1 ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_tl_h2d), + .tl_h_o (ctn_tl_d2h), + .tl_d_o (ctn_sm1_to_s1n_tl_h2d), + .tl_d_i (ctn_sm1_to_s1n_tl_d2h) + ); + + //////////////////////////////////////////// + // CTN Address decoding and SRAM Instance // + //////////////////////////////////////////// + + localparam int CtnSramDw = top_pkg::TL_DW + tlul_pkg::DataIntgWidth; + + tlul_pkg::tl_h2d_t ctn_s1n_tl_h2d[1]; + tlul_pkg::tl_d2h_t ctn_s1n_tl_d2h[1]; + + // Steering signal for address decoding. + logic [0:0] ctn_dev_sel_s1n; + + logic sram_req, sram_we, sram_rvalid; + logic [top_pkg::CtnSramAw-1:0] sram_addr; + logic [CtnSramDw-1:0] sram_wdata, sram_wmask, sram_rdata; + + // Steering of requests. + // Addresses leaving the RoT through the CTN port are mapped to an internal 1G address space of + // 0x4000_0000 - 0x8000_0000. However, the CTN RAM only covers a 1MB region inside that space, + // and hence additional decoding and steering logic is needed here. + // TODO: this should in the future be replaced by an automatically generated crossbar. + always_comb begin + // Default steering to generate error response if address is not within the range + ctn_dev_sel_s1n = 1'b1; + // Steering to CTN SRAM. + if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_RAM_CTN_SIZE_BYTES-1)) == + (TOP_DARJEELING_RAM_CTN_BASE_ADDR - TOP_DARJEELING_CTN_BASE_ADDR)) begin + ctn_dev_sel_s1n = 1'd0; + end + end + + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (8'h0), + .DRspDepth (8'h0), + .N (1) + ) u_ctn_s1n ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_sm1_to_s1n_tl_h2d), + .tl_h_o (ctn_sm1_to_s1n_tl_d2h), + .tl_d_o (ctn_s1n_tl_h2d), + .tl_d_i (ctn_s1n_tl_d2h), + .dev_select_i (ctn_dev_sel_s1n) + ); + + tlul_adapter_sram #( + .SramAw(top_pkg::CtnSramAw), + .SramDw(CtnSramDw - tlul_pkg::DataIntgWidth), + .Outstanding(2), + .ByteAccess(1), + .CmdIntgCheck(1), + .EnableRspIntgGen(1), + .EnableDataIntgGen(0), + .EnableDataIntgPt(1), + .SecFifoPtr (0) + ) u_tlul_adapter_sram_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_i (ctn_s1n_tl_h2d[0]), + .tl_o (ctn_s1n_tl_d2h[0]), + // Ifetch is explicitly allowed + .en_ifetch_i (prim_mubi_pkg::MuBi4True), + .req_o (sram_req), + .req_type_o (), + // SRAM can always accept a request. + .gnt_i (1'b1), + .we_o (sram_we), + .addr_o (sram_addr), + .wdata_o (sram_wdata), + .wmask_o (sram_wmask), + .intg_error_o(), + .user_rsvd_o (), + .rdata_i (sram_rdata), + .rvalid_i (sram_rvalid), + .rerror_i ('0), + .compound_txn_in_progress_o(), + .readback_en_i(prim_mubi_pkg::MuBi4False), + .readback_error_o(), + .wr_collision_i(1'b0), + .write_pending_i(1'b0) + ); + + prim_ram_1p_adv #( + .Depth(top_pkg::CtnSramDepth), + .Width(CtnSramDw), + .DataBitsPerMask(CtnSramDw), + .EnableECC(0), + .EnableParity(0), + .EnableInputPipeline(1), + .EnableOutputPipeline(1) + ) u_prim_ram_1p_adv_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .req_i (sram_req), + .write_i (sram_we), + .addr_i (sram_addr), + .wdata_i (sram_wdata), + .wmask_i (sram_wmask), + .rdata_o (sram_rdata), + .rvalid_o (sram_rvalid), + // No error detection is enabled inside SRAM. + // Bus ECC is checked at the consumer side. + .rerror_o (), + .cfg_i (ram_1p_cfg), + .cfg_rsp_o(), + .alert_o() + ); + + + + ////////////////////////////////// + // Manual Pad / Signal Tie-offs // + ////////////////////////////////// + + assign manual_out_por_n = 1'b0; + assign manual_oe_por_n = 1'b0; + + assign manual_out_otp_ext_volt = 1'b0; + assign manual_oe_otp_ext_volt = 1'b0; + + // These pad attributes currently tied off permanently (these are all input-only pads). + assign manual_attr_por_n = '0; + assign manual_attr_otp_ext_volt = '0; + + logic unused_manual_sigs; + assign unused_manual_sigs = ^{ + manual_in_otp_ext_volt + }; + + soc_proxy_pkg::soc_alert_req_t [soc_proxy_pkg::NumFatalExternalAlerts-1:0] soc_fatal_alert_req; + soc_proxy_pkg::soc_alert_req_t [soc_proxy_pkg::NumRecovExternalAlerts-1:0] soc_recov_alert_req; + assign soc_fatal_alert_req = + {soc_proxy_pkg::NumFatalExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}}; + assign soc_recov_alert_req = + {soc_proxy_pkg::NumRecovExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}}; + + // The power manager waits until the external reset request is removed by the SoC before + // proceeding to boot after an internal reset request. DV may also drive this signal briefly and + // asynchronously to request a reset on behalf of the simulated SoC. + // + // Note that since the signal is filtered inside the SoC proxy it must be of at least 5 + // AON clock periods in duration. + logic soc_rst_req_async; + assign soc_rst_req_async = 1'b0; + + ////////////////////// + // Top-level design // + ////////////////////// + top_darjeeling_no_ibex #( + .PinmuxAonTargetCfg(PinmuxTargetCfg), + .SecAesAllowForcingMasks(1'b1), + .SecRomCtrl0DisableScrambling(SecRomCtrl0DisableScrambling), + .SecRomCtrl1DisableScrambling(SecRomCtrl1DisableScrambling) + ) top_darjeeling_no_ibex ( + // ast connections + .por_n_i ( por_n ), + .clk_main_i ( ast_base_clks.clk_sys ), + .clk_io_i ( ast_base_clks.clk_io ), + .clk_aon_i ( ast_base_clks.clk_aon ), + .clks_ast_o ( clkmgr_aon_clocks ), + .clk_main_jitter_en_o ( jen ), + .rsts_ast_o ( rstmgr_aon_resets ), + .integrator_id_i ( '0 ), + .sck_monitor_o ( sck_monitor ), + .pwrmgr_ast_req_o ( base_ast_pwr ), + .pwrmgr_ast_rsp_i ( ast_base_pwr ), + .ast_tl_req_o ( base_ast_bus ), + .ast_tl_rsp_i ( ast_base_bus ), + .obs_ctrl_i ( obs_ctrl ), + .otp_macro_pwr_seq_o ( otp_macro_pwr_seq ), + .otp_macro_pwr_seq_h_i ( otp_macro_pwr_seq_h ), + .otp_obs_o ( otp_obs ), + .otp_cfg_i ( otp_cfg ), + .otp_cfg_rsp_o ( otp_cfg_rsp ), + .ctn_tl_h2d_o ( ctn_tl_h2d[0] ), + .ctn_tl_d2h_i ( ctn_tl_d2h[0] ), + .ac_range_check_overwrite_i ( ac_range_check_overwrite_i ), + .racl_error_i ( ext_racl_error ), + .soc_gpi_async_o ( ), + .soc_gpo_async_i ( '0 ), + .soc_dbg_policy_bus_o ( soc_dbg_policy_bus ), + .debug_halt_cpu_boot_i ( '0 ), + .dma_sys_req_o ( ), + .dma_sys_rsp_i ( '0 ), + .mbx_tl_req_i ( tlul_pkg::TL_H2D_DEFAULT ), + .mbx_tl_rsp_o ( ), + .pwrmgr_boot_status_o ( pwrmgr_boot_status ), + .ctn_misc_tl_h2d_i ( ctn_misc_tl_h2d_i ), + .ctn_misc_tl_d2h_o ( ctn_misc_tl_d2h_o ), + .soc_fatal_alert_req_i ( soc_fatal_alert_req ), + .soc_fatal_alert_rsp_o ( ), + .soc_recov_alert_req_i ( soc_recov_alert_req ), + .soc_recov_alert_rsp_o ( ), + .soc_intr_async_i ( '0 ), + .soc_wkup_async_i ( 1'b0 ), + .soc_rst_req_async_i ( soc_rst_req_async ), + .soc_lsio_trigger_i ( '0 ), + .mbx0_doe_intr_en_o ( ), + .mbx0_doe_intr_o ( ), + .mbx0_doe_intr_support_o ( ), + .mbx0_doe_async_msg_support_o ( ), + .mbx1_doe_intr_en_o ( ), + .mbx1_doe_intr_o ( ), + .mbx1_doe_intr_support_o ( ), + .mbx1_doe_async_msg_support_o ( ), + .mbx2_doe_intr_en_o ( ), + .mbx2_doe_intr_o ( ), + .mbx2_doe_intr_support_o ( ), + .mbx2_doe_async_msg_support_o ( ), + .mbx3_doe_intr_en_o ( ), + .mbx3_doe_intr_o ( ), + .mbx3_doe_intr_support_o ( ), + .mbx3_doe_async_msg_support_o ( ), + .mbx4_doe_intr_en_o ( ), + .mbx4_doe_intr_o ( ), + .mbx4_doe_intr_support_o ( ), + .mbx4_doe_async_msg_support_o ( ), + .mbx5_doe_intr_en_o ( ), + .mbx5_doe_intr_o ( ), + .mbx5_doe_intr_support_o ( ), + .mbx5_doe_async_msg_support_o ( ), + .mbx6_doe_intr_en_o ( ), + .mbx6_doe_intr_o ( ), + .mbx6_doe_intr_support_o ( ), + .mbx6_doe_async_msg_support_o ( ), + .mbx_jtag_doe_intr_en_o ( ), + .mbx_jtag_doe_intr_o ( ), + .mbx_jtag_doe_intr_support_o ( ), + .mbx_jtag_doe_async_msg_support_o ( ), + .mbx_pcie0_doe_intr_en_o ( ), + .mbx_pcie0_doe_intr_o ( ), + .mbx_pcie0_doe_intr_support_o ( ), + .mbx_pcie0_doe_async_msg_support_o ( ), + .mbx_pcie1_doe_intr_en_o ( ), + .mbx_pcie1_doe_intr_o ( ), + .mbx_pcie1_doe_intr_support_o ( ), + .mbx_pcie1_doe_async_msg_support_o ( ), + .es_rng_enable_o ( es_rng_enable ), + .es_rng_valid_i ( es_rng_valid ), + .es_rng_bit_i ( es_rng_bit ), + .es_rng_fips_o ( es_rng_fips ), + .io_clk_byp_req_o ( io_clk_byp_req ), + .io_clk_byp_ack_i ( io_clk_byp_ack ), + .all_clk_byp_req_o ( all_clk_byp_req ), + .all_clk_byp_ack_i ( all_clk_byp_ack ), + .hi_speed_sel_o ( hi_speed_sel ), + .div_step_down_req_i ( div_step_down_req ), + .calib_rdy_i ( ast_init_done ), + + // OTP external voltage + .otp_ext_voltage_h_io ( OTP_EXT_VOLT ), + + // DMI TL-UL + .dbg_tl_req_i ( dmi_h2d ), + .dbg_tl_rsp_o ( dmi_d2h ), + // Quasi-static word address for next_dm register value. + .rv_dm_next_dm_addr_i ( '0 ), + // Multiplexed I/O + .mio_in_i ( mio_in ), + .mio_out_o ( mio_out ), + .mio_oe_o ( mio_oe ), + + // Dedicated I/O + .dio_in_i ( dio_in ), + .dio_out_o ( dio_out ), + .dio_oe_o ( dio_oe ), + + // Pad attributes + .mio_attr_o ( mio_attr ), + .dio_attr_o ( dio_attr ), + + // Memory attributes + .rom_ctrl0_cfg_i ( rom_ctrl0_cfg ), + .rom_ctrl1_cfg_i ( rom_ctrl1_cfg ), + .i2c_ram_1p_cfg_i ( ram_1p_cfg ), + .i2c_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_ret_aon_ram_1p_cfg_i ( ram_1p_cfg ), + .sram_ctrl_ret_aon_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_main_ram_1p_cfg_i ( ram_1p_cfg ), + .sram_ctrl_main_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_mbox_ram_1p_cfg_i ( ram_1p_cfg ), + .sram_ctrl_mbox_ram_1p_cfg_rsp_o ( ), + .otbn_imem_ram_1p_cfg_i ( ram_1p_cfg ), + .otbn_imem_ram_1p_cfg_rsp_o ( ), + .otbn_dmem_ram_1p_cfg_i ( ram_1p_cfg ), + .otbn_dmem_ram_1p_cfg_rsp_o ( ), + .rv_core_ibex_icache_tag_ram_1p_cfg_i ( ram_1p_cfg ), + .rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o ( ), + .rv_core_ibex_icache_data_ram_1p_cfg_i ( ram_1p_cfg ), + .rv_core_ibex_icache_data_ram_1p_cfg_rsp_o ( ), + .spi_device_ram_2p_cfg_sys2spi_i ( spi_ram_2p_cfg ), + .spi_device_ram_2p_cfg_spi2sys_i ( spi_ram_2p_cfg ), + .spi_device_ram_2p_cfg_rsp_sys2spi_o ( ), + .spi_device_ram_2p_cfg_rsp_spi2sys_o ( ), + + // DFT signals + .ast_lc_dft_en_o ( lc_dft_en ), + .ast_lc_hw_debug_en_o ( ), + .scan_rst_ni ( scan_rst_n ), + .scan_en_i ( scan_en ), + .scanmode_i ( scanmode ), + + // FPGA build info + .fpga_info_i ( '0 ) + ); + +logic unused_signals; +assign unused_signals = ^{pwrmgr_boot_status.clk_status, + pwrmgr_boot_status.cpu_fetch_en, + pwrmgr_boot_status.lc_done, + pwrmgr_boot_status.otp_done, + pwrmgr_boot_status.rom_ctrl_status, + pwrmgr_boot_status.strap_sampled}; + + + +endmodule : chip_darjeeling_no_ibex_asic diff --git a/hw/top_darjeeling_no_ibex/rtl/autogen/chip_darjeeling_no_ibex_cw310.sv b/hw/top_darjeeling_no_ibex/rtl/autogen/chip_darjeeling_no_ibex_cw310.sv new file mode 100644 index 00000000000..e7d0e42a038 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/rtl/autogen/chip_darjeeling_no_ibex_cw310.sv @@ -0,0 +1,1741 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + + +module chip_darjeeling_no_ibex_cw310 #( + // Path to a VMEM file containing the contents of the boot ROM, which will be + // baked into the FPGA bitstream. + parameter BootRomInitFile = "test_rom_fpga_cw310.32.vmem", + // Path to a VMEM file containing the contents of the emulated OTP, which will be + // baked into the FPGA bitstream. + parameter OtpMacroMemInitFile = "otp_img_fpga_cw310.vmem" +) ( + // Dedicated Pads + inout POR_N, // Manual Pad + inout JTAG_TCK, // Manual Pad + inout JTAG_TMS, // Manual Pad + inout JTAG_TDI, // Manual Pad + inout JTAG_TDO, // Manual Pad + inout JTAG_TRST_N, // Manual Pad + inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D1, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D2, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_D3, // Dedicated Pad for spi_host0_sd + inout SPI_HOST_CLK, // Dedicated Pad for spi_host0_sck + inout SPI_HOST_CS_L, // Dedicated Pad for spi_host0_csb + inout SPI_DEV_D0, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D1, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D2, // Dedicated Pad for spi_device_sd + inout SPI_DEV_D3, // Dedicated Pad for spi_device_sd + inout SPI_DEV_CLK, // Dedicated Pad for spi_device_sck + inout SPI_DEV_CS_L, // Dedicated Pad for spi_device_csb + inout SPI_DEV_TPM_CS_L, // Dedicated Pad for spi_device_tpm_csb + inout UART_RX, // Dedicated Pad for uart0_rx + inout UART_TX, // Dedicated Pad for uart0_tx + inout I2C_SCL, // Dedicated Pad for i2c0_scl + inout I2C_SDA, // Dedicated Pad for i2c0_sda + inout GPIO0, // Dedicated Pad for gpio_gpio + inout GPIO1, // Dedicated Pad for gpio_gpio + inout GPIO2, // Dedicated Pad for gpio_gpio + inout GPIO3, // Dedicated Pad for gpio_gpio + inout GPIO4, // Dedicated Pad for gpio_gpio + inout GPIO5, // Dedicated Pad for gpio_gpio + inout GPIO6, // Dedicated Pad for gpio_gpio + inout GPIO7, // Dedicated Pad for gpio_gpio + inout GPIO8, // Dedicated Pad for gpio_gpio + inout GPIO9, // Dedicated Pad for gpio_gpio + inout GPIO10, // Dedicated Pad for gpio_gpio + inout GPIO11, // Dedicated Pad for gpio_gpio + inout GPIO12, // Dedicated Pad for gpio_gpio + inout GPIO13, // Dedicated Pad for gpio_gpio + inout GPIO14, // Dedicated Pad for gpio_gpio + inout GPIO15, // Dedicated Pad for gpio_gpio + inout GPIO16, // Dedicated Pad for gpio_gpio + inout GPIO17, // Dedicated Pad for gpio_gpio + inout GPIO18, // Dedicated Pad for gpio_gpio + inout GPIO19, // Dedicated Pad for gpio_gpio + inout GPIO20, // Dedicated Pad for gpio_gpio + inout GPIO21, // Dedicated Pad for gpio_gpio + inout GPIO22, // Dedicated Pad for gpio_gpio + inout GPIO23, // Dedicated Pad for gpio_gpio + inout GPIO24, // Dedicated Pad for gpio_gpio + inout GPIO25, // Dedicated Pad for gpio_gpio + inout GPIO26, // Dedicated Pad for gpio_gpio + inout GPIO27, // Dedicated Pad for gpio_gpio + inout GPIO28, // Dedicated Pad for gpio_gpio + inout GPIO29, // Dedicated Pad for gpio_gpio + inout GPIO30, // Dedicated Pad for gpio_gpio + inout GPIO31, // Dedicated Pad for gpio_gpio + inout SOC_GPI0, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI1, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI2, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI3, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI4, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI5, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI6, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI7, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI8, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI9, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI10, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPI11, // Dedicated Pad for soc_proxy_soc_gpi + inout SOC_GPO0, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO1, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO2, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO3, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO4, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO5, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO6, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO7, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO8, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO9, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO10, // Dedicated Pad for soc_proxy_soc_gpo + inout SOC_GPO11, // Dedicated Pad for soc_proxy_soc_gpo + inout IO_CLK, // Manual Pad + inout POR_BUTTON_N, // Manual Pad + inout IO_CLKOUT, // Manual Pad + inout IO_TRIGGER, // Manual Pad + + // Muxed Pads + inout MIO0, // MIO Pad 0 + inout MIO1, // MIO Pad 1 + inout MIO2, // MIO Pad 2 + inout MIO3, // MIO Pad 3 + inout MIO4, // MIO Pad 4 + inout MIO5, // MIO Pad 5 + inout MIO6, // MIO Pad 6 + inout MIO7, // MIO Pad 7 + inout MIO8, // MIO Pad 8 + inout MIO9, // MIO Pad 9 + inout MIO10, // MIO Pad 10 + inout MIO11 // MIO Pad 11 +); + + import top_darjeeling_no_ibex_pkg::*; + import prim_pad_wrapper_pkg::*; + + //////////////////////////// + // Special Signal Indices // + //////////////////////////// + + localparam int Tap0PadIdx = 0; + localparam int Tap1PadIdx = 1; + localparam int Dft0PadIdx = 2; + localparam int Dft1PadIdx = 3; + localparam int TckPadIdx = 4; + localparam int TmsPadIdx = 5; + localparam int TrstNPadIdx = 6; + localparam int TdiPadIdx = 7; + localparam int TdoPadIdx = 8; + + // DFT and Debug signal positions in the pinout. + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + // TODO: check whether there is a better way to pass these USB-specific params + // The use of these indexes is gated behind a parameter, but to synthesize they + // need to exist even if the code-path is never used (pinmux.sv:UsbWkupModuleEn). + // Hence, set to zero. + usb_dp_idx: 0, + usb_dn_idx: 0, + usb_sense_idx: 0, + // Pad types for attribute WARL behavior + dio_pad_type: { + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO soc_proxy_soc_gpo + BidirStd, // DIO uart0_tx + BidirStd, // DIO spi_host0_csb + BidirStd, // DIO spi_host0_sck + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO soc_proxy_soc_gpi + InputStd, // DIO uart0_rx + InputStd, // DIO spi_device_tpm_csb + InputStd, // DIO spi_device_csb + InputStd, // DIO spi_device_sck + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO gpio_gpio + BidirStd, // DIO i2c0_sda + BidirStd, // DIO i2c0_scl + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_device_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd, // DIO spi_host0_sd + BidirStd // DIO spi_host0_sd + }, + mio_pad_type: { + BidirStd, // MIO Pad 11 + BidirStd, // MIO Pad 10 + BidirStd, // MIO Pad 9 + BidirStd, // MIO Pad 8 + BidirStd, // MIO Pad 7 + BidirStd, // MIO Pad 6 + BidirStd, // MIO Pad 5 + BidirStd, // MIO Pad 4 + BidirStd, // MIO Pad 3 + BidirStd, // MIO Pad 2 + BidirStd, // MIO Pad 1 + BidirStd // MIO Pad 0 + }, + // Pad scan roles + dio_scan_role: { + scan_role_pkg::DioPadSocGpo11ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo10ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo9ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo8ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo7ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo6ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo5ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo4ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo3ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo2ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo1ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadSocGpo0ScanRole, // DIO soc_proxy_soc_gpo + scan_role_pkg::DioPadUartTxScanRole, // DIO uart0_tx + scan_role_pkg::DioPadSpiHostCsLScanRole, // DIO spi_host0_csb + scan_role_pkg::DioPadSpiHostClkScanRole, // DIO spi_host0_sck + scan_role_pkg::DioPadSocGpi11ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi10ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi9ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi8ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi7ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi6ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi5ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi4ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi3ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi2ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi1ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadSocGpi0ScanRole, // DIO soc_proxy_soc_gpi + scan_role_pkg::DioPadUartRxScanRole, // DIO uart0_rx + scan_role_pkg::DioPadSpiDevTpmCsLScanRole, // DIO spi_device_tpm_csb + scan_role_pkg::DioPadSpiDevCsLScanRole, // DIO spi_device_csb + scan_role_pkg::DioPadSpiDevClkScanRole, // DIO spi_device_sck + scan_role_pkg::DioPadGpio31ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio30ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio29ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio28ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio27ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio26ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio25ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio24ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio23ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio22ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio21ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio20ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio19ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio18ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio17ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio16ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio15ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio14ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio13ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio12ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio11ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio10ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio9ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio8ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio7ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio6ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio5ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio4ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio3ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio2ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio1ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadGpio0ScanRole, // DIO gpio_gpio + scan_role_pkg::DioPadI2cSdaScanRole, // DIO i2c0_sda + scan_role_pkg::DioPadI2cSclScanRole, // DIO i2c0_scl + scan_role_pkg::DioPadSpiDevD3ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD2ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD1ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiDevD0ScanRole, // DIO spi_device_sd + scan_role_pkg::DioPadSpiHostD3ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD2ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD1ScanRole, // DIO spi_host0_sd + scan_role_pkg::DioPadSpiHostD0ScanRole // DIO spi_host0_sd + }, + mio_scan_role: { + scan_role_pkg::MioPadMio11ScanRole, + scan_role_pkg::MioPadMio10ScanRole, + scan_role_pkg::MioPadMio9ScanRole, + scan_role_pkg::MioPadMio8ScanRole, + scan_role_pkg::MioPadMio7ScanRole, + scan_role_pkg::MioPadMio6ScanRole, + scan_role_pkg::MioPadMio5ScanRole, + scan_role_pkg::MioPadMio4ScanRole, + scan_role_pkg::MioPadMio3ScanRole, + scan_role_pkg::MioPadMio2ScanRole, + scan_role_pkg::MioPadMio1ScanRole, + scan_role_pkg::MioPadMio0ScanRole + } + }; + + //////////////////////// + // Signal definitions // + //////////////////////// + + + pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr; + pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw; + logic [83-1:0] dio_in_raw; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in; + + logic unused_mio_in_raw; + logic unused_dio_in_raw; + assign unused_mio_in_raw = ^mio_in_raw; + assign unused_dio_in_raw = ^dio_in_raw; + + // Manual pads + logic manual_in_por_n, manual_out_por_n, manual_oe_por_n; + logic manual_in_jtag_tck, manual_out_jtag_tck, manual_oe_jtag_tck; + logic manual_in_jtag_tms, manual_out_jtag_tms, manual_oe_jtag_tms; + logic manual_in_jtag_tdi, manual_out_jtag_tdi, manual_oe_jtag_tdi; + logic manual_in_jtag_tdo, manual_out_jtag_tdo, manual_oe_jtag_tdo; + logic manual_in_jtag_trst_n, manual_out_jtag_trst_n, manual_oe_jtag_trst_n; + logic manual_in_io_clk, manual_out_io_clk, manual_oe_io_clk; + logic manual_in_por_button_n, manual_out_por_button_n, manual_oe_por_button_n; + logic manual_in_io_clkout, manual_out_io_clkout, manual_oe_io_clkout; + logic manual_in_io_trigger, manual_out_io_trigger, manual_oe_io_trigger; + + pad_attr_t manual_attr_por_n; + pad_attr_t manual_attr_jtag_tck; + pad_attr_t manual_attr_jtag_tms; + pad_attr_t manual_attr_jtag_tdi; + pad_attr_t manual_attr_jtag_tdo; + pad_attr_t manual_attr_jtag_trst_n; + pad_attr_t manual_attr_io_clk; + pad_attr_t manual_attr_por_button_n; + pad_attr_t manual_attr_io_clkout; + pad_attr_t manual_attr_io_trigger; + + ///////////////////////// + // Stubbed pad tie-off // + ///////////////////////// + + // Only signals going to non-custom pads need to be tied off. + logic [91:0] unused_sig; + + ////////////////////// + // Padring Instance // + ////////////////////// + + ast_pkg::ast_clks_t ast_base_clks; + + + padring #( + // Padring specific counts may differ from pinmux config due + // to custom, stubbed or added pads. + .NDioPads(83), + .NMioPads(12), + .DioPadType ({ + BidirStd, // IO_TRIGGER + BidirStd, // IO_CLKOUT + InputStd, // POR_BUTTON_N + InputStd, // IO_CLK + BidirStd, // SOC_GPO11 + BidirStd, // SOC_GPO10 + BidirStd, // SOC_GPO9 + BidirStd, // SOC_GPO8 + BidirStd, // SOC_GPO7 + BidirStd, // SOC_GPO6 + BidirStd, // SOC_GPO5 + BidirStd, // SOC_GPO4 + BidirStd, // SOC_GPO3 + BidirStd, // SOC_GPO2 + BidirStd, // SOC_GPO1 + BidirStd, // SOC_GPO0 + InputStd, // SOC_GPI11 + InputStd, // SOC_GPI10 + InputStd, // SOC_GPI9 + InputStd, // SOC_GPI8 + InputStd, // SOC_GPI7 + InputStd, // SOC_GPI6 + InputStd, // SOC_GPI5 + InputStd, // SOC_GPI4 + InputStd, // SOC_GPI3 + InputStd, // SOC_GPI2 + InputStd, // SOC_GPI1 + InputStd, // SOC_GPI0 + BidirStd, // GPIO31 + BidirStd, // GPIO30 + BidirStd, // GPIO29 + BidirStd, // GPIO28 + BidirStd, // GPIO27 + BidirStd, // GPIO26 + BidirStd, // GPIO25 + BidirStd, // GPIO24 + BidirStd, // GPIO23 + BidirStd, // GPIO22 + BidirStd, // GPIO21 + BidirStd, // GPIO20 + BidirStd, // GPIO19 + BidirStd, // GPIO18 + BidirStd, // GPIO17 + BidirStd, // GPIO16 + BidirStd, // GPIO15 + BidirStd, // GPIO14 + BidirStd, // GPIO13 + BidirStd, // GPIO12 + BidirStd, // GPIO11 + BidirStd, // GPIO10 + BidirStd, // GPIO9 + BidirStd, // GPIO8 + BidirStd, // GPIO7 + BidirStd, // GPIO6 + BidirStd, // GPIO5 + BidirStd, // GPIO4 + BidirStd, // GPIO3 + BidirStd, // GPIO2 + BidirStd, // GPIO1 + BidirStd, // GPIO0 + BidirStd, // I2C_SDA + BidirStd, // I2C_SCL + BidirStd, // UART_TX + InputStd, // UART_RX + InputStd, // SPI_DEV_TPM_CS_L + InputStd, // SPI_DEV_CS_L + InputStd, // SPI_DEV_CLK + BidirStd, // SPI_DEV_D3 + BidirStd, // SPI_DEV_D2 + BidirStd, // SPI_DEV_D1 + BidirStd, // SPI_DEV_D0 + BidirStd, // SPI_HOST_CS_L + BidirStd, // SPI_HOST_CLK + BidirStd, // SPI_HOST_D3 + BidirStd, // SPI_HOST_D2 + BidirStd, // SPI_HOST_D1 + BidirStd, // SPI_HOST_D0 + InputStd, // JTAG_TRST_N + BidirStd, // JTAG_TDO + InputStd, // JTAG_TDI + InputStd, // JTAG_TMS + InputStd, // JTAG_TCK + InputStd // POR_N + }), + .MioPadType ({ + BidirStd, // MIO11 + BidirStd, // MIO10 + BidirStd, // MIO9 + BidirStd, // MIO8 + BidirStd, // MIO7 + BidirStd, // MIO6 + BidirStd, // MIO5 + BidirStd, // MIO4 + BidirStd, // MIO3 + BidirStd, // MIO2 + BidirStd, // MIO1 + BidirStd // MIO0 + }) + ) u_padring ( + // This is only used for scan and DFT purposes + .clk_scan_i ( 1'b0 ), + .scanmode_i ( prim_mubi_pkg::MuBi4False ), + .dio_in_raw_o ( dio_in_raw ), + // Chip IOs + .dio_pad_io ({ + IO_TRIGGER, + IO_CLKOUT, + POR_BUTTON_N, + IO_CLK, + SOC_GPO11, + SOC_GPO10, + SOC_GPO9, + SOC_GPO8, + SOC_GPO7, + SOC_GPO6, + SOC_GPO5, + SOC_GPO4, + SOC_GPO3, + SOC_GPO2, + SOC_GPO1, + SOC_GPO0, + SOC_GPI11, + SOC_GPI10, + SOC_GPI9, + SOC_GPI8, + SOC_GPI7, + SOC_GPI6, + SOC_GPI5, + SOC_GPI4, + SOC_GPI3, + SOC_GPI2, + SOC_GPI1, + SOC_GPI0, + GPIO31, + GPIO30, + GPIO29, + GPIO28, + GPIO27, + GPIO26, + GPIO25, + GPIO24, + GPIO23, + GPIO22, + GPIO21, + GPIO20, + GPIO19, + GPIO18, + GPIO17, + GPIO16, + GPIO15, + GPIO14, + GPIO13, + GPIO12, + GPIO11, + GPIO10, + GPIO9, + GPIO8, + GPIO7, + GPIO6, + GPIO5, + GPIO4, + GPIO3, + GPIO2, + GPIO1, + GPIO0, + I2C_SDA, + I2C_SCL, + UART_TX, + UART_RX, + SPI_DEV_TPM_CS_L, + SPI_DEV_CS_L, + SPI_DEV_CLK, + SPI_DEV_D3, + SPI_DEV_D2, + SPI_DEV_D1, + SPI_DEV_D0, + SPI_HOST_CS_L, + SPI_HOST_CLK, + SPI_HOST_D3, + SPI_HOST_D2, + SPI_HOST_D1, + SPI_HOST_D0, + JTAG_TRST_N, + JTAG_TDO, + JTAG_TDI, + JTAG_TMS, + JTAG_TCK, + POR_N + }), + + .mio_pad_io ({ + MIO11, + MIO10, + MIO9, + MIO8, + MIO7, + MIO6, + MIO5, + MIO4, + MIO3, + MIO2, + MIO1, + MIO0 + }), + + // Core-facing + .dio_in_o ({ + manual_in_io_trigger, + manual_in_io_clkout, + manual_in_por_button_n, + manual_in_io_clk, + dio_in[DioSocProxySocGpo11], + dio_in[DioSocProxySocGpo10], + dio_in[DioSocProxySocGpo9], + dio_in[DioSocProxySocGpo8], + dio_in[DioSocProxySocGpo7], + dio_in[DioSocProxySocGpo6], + dio_in[DioSocProxySocGpo5], + dio_in[DioSocProxySocGpo4], + dio_in[DioSocProxySocGpo3], + dio_in[DioSocProxySocGpo2], + dio_in[DioSocProxySocGpo1], + dio_in[DioSocProxySocGpo0], + dio_in[DioSocProxySocGpi11], + dio_in[DioSocProxySocGpi10], + dio_in[DioSocProxySocGpi9], + dio_in[DioSocProxySocGpi8], + dio_in[DioSocProxySocGpi7], + dio_in[DioSocProxySocGpi6], + dio_in[DioSocProxySocGpi5], + dio_in[DioSocProxySocGpi4], + dio_in[DioSocProxySocGpi3], + dio_in[DioSocProxySocGpi2], + dio_in[DioSocProxySocGpi1], + dio_in[DioSocProxySocGpi0], + dio_in[DioGpioGpio31], + dio_in[DioGpioGpio30], + dio_in[DioGpioGpio29], + dio_in[DioGpioGpio28], + dio_in[DioGpioGpio27], + dio_in[DioGpioGpio26], + dio_in[DioGpioGpio25], + dio_in[DioGpioGpio24], + dio_in[DioGpioGpio23], + dio_in[DioGpioGpio22], + dio_in[DioGpioGpio21], + dio_in[DioGpioGpio20], + dio_in[DioGpioGpio19], + dio_in[DioGpioGpio18], + dio_in[DioGpioGpio17], + dio_in[DioGpioGpio16], + dio_in[DioGpioGpio15], + dio_in[DioGpioGpio14], + dio_in[DioGpioGpio13], + dio_in[DioGpioGpio12], + dio_in[DioGpioGpio11], + dio_in[DioGpioGpio10], + dio_in[DioGpioGpio9], + dio_in[DioGpioGpio8], + dio_in[DioGpioGpio7], + dio_in[DioGpioGpio6], + dio_in[DioGpioGpio5], + dio_in[DioGpioGpio4], + dio_in[DioGpioGpio3], + dio_in[DioGpioGpio2], + dio_in[DioGpioGpio1], + dio_in[DioGpioGpio0], + dio_in[DioI2c0Sda], + dio_in[DioI2c0Scl], + dio_in[DioUart0Tx], + dio_in[DioUart0Rx], + dio_in[DioSpiDeviceTpmCsb], + dio_in[DioSpiDeviceCsb], + dio_in[DioSpiDeviceSck], + dio_in[DioSpiDeviceSd3], + dio_in[DioSpiDeviceSd2], + dio_in[DioSpiDeviceSd1], + dio_in[DioSpiDeviceSd0], + dio_in[DioSpiHost0Csb], + dio_in[DioSpiHost0Sck], + dio_in[DioSpiHost0Sd3], + dio_in[DioSpiHost0Sd2], + dio_in[DioSpiHost0Sd1], + dio_in[DioSpiHost0Sd0], + manual_in_jtag_trst_n, + manual_in_jtag_tdo, + manual_in_jtag_tdi, + manual_in_jtag_tms, + manual_in_jtag_tck, + manual_in_por_n + }), + .dio_out_i ({ + manual_out_io_trigger, + manual_out_io_clkout, + manual_out_por_button_n, + manual_out_io_clk, + dio_out[DioSocProxySocGpo11], + dio_out[DioSocProxySocGpo10], + dio_out[DioSocProxySocGpo9], + dio_out[DioSocProxySocGpo8], + dio_out[DioSocProxySocGpo7], + dio_out[DioSocProxySocGpo6], + dio_out[DioSocProxySocGpo5], + dio_out[DioSocProxySocGpo4], + dio_out[DioSocProxySocGpo3], + dio_out[DioSocProxySocGpo2], + dio_out[DioSocProxySocGpo1], + dio_out[DioSocProxySocGpo0], + dio_out[DioSocProxySocGpi11], + dio_out[DioSocProxySocGpi10], + dio_out[DioSocProxySocGpi9], + dio_out[DioSocProxySocGpi8], + dio_out[DioSocProxySocGpi7], + dio_out[DioSocProxySocGpi6], + dio_out[DioSocProxySocGpi5], + dio_out[DioSocProxySocGpi4], + dio_out[DioSocProxySocGpi3], + dio_out[DioSocProxySocGpi2], + dio_out[DioSocProxySocGpi1], + dio_out[DioSocProxySocGpi0], + dio_out[DioGpioGpio31], + dio_out[DioGpioGpio30], + dio_out[DioGpioGpio29], + dio_out[DioGpioGpio28], + dio_out[DioGpioGpio27], + dio_out[DioGpioGpio26], + dio_out[DioGpioGpio25], + dio_out[DioGpioGpio24], + dio_out[DioGpioGpio23], + dio_out[DioGpioGpio22], + dio_out[DioGpioGpio21], + dio_out[DioGpioGpio20], + dio_out[DioGpioGpio19], + dio_out[DioGpioGpio18], + dio_out[DioGpioGpio17], + dio_out[DioGpioGpio16], + dio_out[DioGpioGpio15], + dio_out[DioGpioGpio14], + dio_out[DioGpioGpio13], + dio_out[DioGpioGpio12], + dio_out[DioGpioGpio11], + dio_out[DioGpioGpio10], + dio_out[DioGpioGpio9], + dio_out[DioGpioGpio8], + dio_out[DioGpioGpio7], + dio_out[DioGpioGpio6], + dio_out[DioGpioGpio5], + dio_out[DioGpioGpio4], + dio_out[DioGpioGpio3], + dio_out[DioGpioGpio2], + dio_out[DioGpioGpio1], + dio_out[DioGpioGpio0], + dio_out[DioI2c0Sda], + dio_out[DioI2c0Scl], + dio_out[DioUart0Tx], + dio_out[DioUart0Rx], + dio_out[DioSpiDeviceTpmCsb], + dio_out[DioSpiDeviceCsb], + dio_out[DioSpiDeviceSck], + dio_out[DioSpiDeviceSd3], + dio_out[DioSpiDeviceSd2], + dio_out[DioSpiDeviceSd1], + dio_out[DioSpiDeviceSd0], + dio_out[DioSpiHost0Csb], + dio_out[DioSpiHost0Sck], + dio_out[DioSpiHost0Sd3], + dio_out[DioSpiHost0Sd2], + dio_out[DioSpiHost0Sd1], + dio_out[DioSpiHost0Sd0], + manual_out_jtag_trst_n, + manual_out_jtag_tdo, + manual_out_jtag_tdi, + manual_out_jtag_tms, + manual_out_jtag_tck, + manual_out_por_n + }), + .dio_oe_i ({ + manual_oe_io_trigger, + manual_oe_io_clkout, + manual_oe_por_button_n, + manual_oe_io_clk, + dio_oe[DioSocProxySocGpo11], + dio_oe[DioSocProxySocGpo10], + dio_oe[DioSocProxySocGpo9], + dio_oe[DioSocProxySocGpo8], + dio_oe[DioSocProxySocGpo7], + dio_oe[DioSocProxySocGpo6], + dio_oe[DioSocProxySocGpo5], + dio_oe[DioSocProxySocGpo4], + dio_oe[DioSocProxySocGpo3], + dio_oe[DioSocProxySocGpo2], + dio_oe[DioSocProxySocGpo1], + dio_oe[DioSocProxySocGpo0], + dio_oe[DioSocProxySocGpi11], + dio_oe[DioSocProxySocGpi10], + dio_oe[DioSocProxySocGpi9], + dio_oe[DioSocProxySocGpi8], + dio_oe[DioSocProxySocGpi7], + dio_oe[DioSocProxySocGpi6], + dio_oe[DioSocProxySocGpi5], + dio_oe[DioSocProxySocGpi4], + dio_oe[DioSocProxySocGpi3], + dio_oe[DioSocProxySocGpi2], + dio_oe[DioSocProxySocGpi1], + dio_oe[DioSocProxySocGpi0], + dio_oe[DioGpioGpio31], + dio_oe[DioGpioGpio30], + dio_oe[DioGpioGpio29], + dio_oe[DioGpioGpio28], + dio_oe[DioGpioGpio27], + dio_oe[DioGpioGpio26], + dio_oe[DioGpioGpio25], + dio_oe[DioGpioGpio24], + dio_oe[DioGpioGpio23], + dio_oe[DioGpioGpio22], + dio_oe[DioGpioGpio21], + dio_oe[DioGpioGpio20], + dio_oe[DioGpioGpio19], + dio_oe[DioGpioGpio18], + dio_oe[DioGpioGpio17], + dio_oe[DioGpioGpio16], + dio_oe[DioGpioGpio15], + dio_oe[DioGpioGpio14], + dio_oe[DioGpioGpio13], + dio_oe[DioGpioGpio12], + dio_oe[DioGpioGpio11], + dio_oe[DioGpioGpio10], + dio_oe[DioGpioGpio9], + dio_oe[DioGpioGpio8], + dio_oe[DioGpioGpio7], + dio_oe[DioGpioGpio6], + dio_oe[DioGpioGpio5], + dio_oe[DioGpioGpio4], + dio_oe[DioGpioGpio3], + dio_oe[DioGpioGpio2], + dio_oe[DioGpioGpio1], + dio_oe[DioGpioGpio0], + dio_oe[DioI2c0Sda], + dio_oe[DioI2c0Scl], + dio_oe[DioUart0Tx], + dio_oe[DioUart0Rx], + dio_oe[DioSpiDeviceTpmCsb], + dio_oe[DioSpiDeviceCsb], + dio_oe[DioSpiDeviceSck], + dio_oe[DioSpiDeviceSd3], + dio_oe[DioSpiDeviceSd2], + dio_oe[DioSpiDeviceSd1], + dio_oe[DioSpiDeviceSd0], + dio_oe[DioSpiHost0Csb], + dio_oe[DioSpiHost0Sck], + dio_oe[DioSpiHost0Sd3], + dio_oe[DioSpiHost0Sd2], + dio_oe[DioSpiHost0Sd1], + dio_oe[DioSpiHost0Sd0], + manual_oe_jtag_trst_n, + manual_oe_jtag_tdo, + manual_oe_jtag_tdi, + manual_oe_jtag_tms, + manual_oe_jtag_tck, + manual_oe_por_n + }), + .dio_attr_i ({ + manual_attr_io_trigger, + manual_attr_io_clkout, + manual_attr_por_button_n, + manual_attr_io_clk, + dio_attr[DioSocProxySocGpo11], + dio_attr[DioSocProxySocGpo10], + dio_attr[DioSocProxySocGpo9], + dio_attr[DioSocProxySocGpo8], + dio_attr[DioSocProxySocGpo7], + dio_attr[DioSocProxySocGpo6], + dio_attr[DioSocProxySocGpo5], + dio_attr[DioSocProxySocGpo4], + dio_attr[DioSocProxySocGpo3], + dio_attr[DioSocProxySocGpo2], + dio_attr[DioSocProxySocGpo1], + dio_attr[DioSocProxySocGpo0], + dio_attr[DioSocProxySocGpi11], + dio_attr[DioSocProxySocGpi10], + dio_attr[DioSocProxySocGpi9], + dio_attr[DioSocProxySocGpi8], + dio_attr[DioSocProxySocGpi7], + dio_attr[DioSocProxySocGpi6], + dio_attr[DioSocProxySocGpi5], + dio_attr[DioSocProxySocGpi4], + dio_attr[DioSocProxySocGpi3], + dio_attr[DioSocProxySocGpi2], + dio_attr[DioSocProxySocGpi1], + dio_attr[DioSocProxySocGpi0], + dio_attr[DioGpioGpio31], + dio_attr[DioGpioGpio30], + dio_attr[DioGpioGpio29], + dio_attr[DioGpioGpio28], + dio_attr[DioGpioGpio27], + dio_attr[DioGpioGpio26], + dio_attr[DioGpioGpio25], + dio_attr[DioGpioGpio24], + dio_attr[DioGpioGpio23], + dio_attr[DioGpioGpio22], + dio_attr[DioGpioGpio21], + dio_attr[DioGpioGpio20], + dio_attr[DioGpioGpio19], + dio_attr[DioGpioGpio18], + dio_attr[DioGpioGpio17], + dio_attr[DioGpioGpio16], + dio_attr[DioGpioGpio15], + dio_attr[DioGpioGpio14], + dio_attr[DioGpioGpio13], + dio_attr[DioGpioGpio12], + dio_attr[DioGpioGpio11], + dio_attr[DioGpioGpio10], + dio_attr[DioGpioGpio9], + dio_attr[DioGpioGpio8], + dio_attr[DioGpioGpio7], + dio_attr[DioGpioGpio6], + dio_attr[DioGpioGpio5], + dio_attr[DioGpioGpio4], + dio_attr[DioGpioGpio3], + dio_attr[DioGpioGpio2], + dio_attr[DioGpioGpio1], + dio_attr[DioGpioGpio0], + dio_attr[DioI2c0Sda], + dio_attr[DioI2c0Scl], + dio_attr[DioUart0Tx], + dio_attr[DioUart0Rx], + dio_attr[DioSpiDeviceTpmCsb], + dio_attr[DioSpiDeviceCsb], + dio_attr[DioSpiDeviceSck], + dio_attr[DioSpiDeviceSd3], + dio_attr[DioSpiDeviceSd2], + dio_attr[DioSpiDeviceSd1], + dio_attr[DioSpiDeviceSd0], + dio_attr[DioSpiHost0Csb], + dio_attr[DioSpiHost0Sck], + dio_attr[DioSpiHost0Sd3], + dio_attr[DioSpiHost0Sd2], + dio_attr[DioSpiHost0Sd1], + dio_attr[DioSpiHost0Sd0], + manual_attr_jtag_trst_n, + manual_attr_jtag_tdo, + manual_attr_jtag_tdi, + manual_attr_jtag_tms, + manual_attr_jtag_tck, + manual_attr_por_n + }), + + .mio_in_o (mio_in[11:0]), + .mio_out_i (mio_out[11:0]), + .mio_oe_i (mio_oe[11:0]), + .mio_attr_i (mio_attr[11:0]), + .mio_in_raw_o (mio_in_raw[11:0]) + ); + + + + + ////////////////////////////////// + // AST - Common for all targets // + ////////////////////////////////// + + // pwrmgr interface + pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; + pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; + + // assorted ast status + ast_pkg::ast_pwst_t ast_pwst; + + // TLUL interface + tlul_pkg::tl_h2d_t base_ast_bus; + tlul_pkg::tl_d2h_t ast_base_bus; + + // synchronization clocks / rests + clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; + rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets; + + // external clock + logic ext_clk; + + // monitored clock + logic sck_monitor; + + // debug policy bus + soc_dbg_ctrl_pkg::soc_dbg_policy_t soc_dbg_policy_bus; + + // observe interface + logic [7:0] otp_obs; + ast_pkg::ast_obs_ctrl_t obs_ctrl; + + // otp power sequence + otp_macro_pkg::otp_ast_req_t otp_macro_pwr_seq; + otp_macro_pkg::otp_ast_rsp_t otp_macro_pwr_seq_h; + + // OTP DFT configuration + otp_macro_pkg::otp_cfg_t otp_cfg; + assign otp_cfg = otp_macro_pkg::OTP_CFG_DEFAULT; + + // entropy source interface + logic es_rng_enable, es_rng_valid; + logic [ast_pkg::EntropyStreams-1:0] es_rng_bit; + + // alerts interface + ast_pkg::ast_alert_rsp_t ast_alert_rsp; + ast_pkg::ast_alert_req_t ast_alert_req; + assign ast_alert_rsp = '0; + + // clock bypass req/ack + prim_mubi_pkg::mubi4_t io_clk_byp_req; + prim_mubi_pkg::mubi4_t io_clk_byp_ack; + prim_mubi_pkg::mubi4_t all_clk_byp_req; + prim_mubi_pkg::mubi4_t all_clk_byp_ack; + prim_mubi_pkg::mubi4_t hi_speed_sel; + prim_mubi_pkg::mubi4_t div_step_down_req; + + // DFT connections + logic scan_en; + lc_ctrl_pkg::lc_tx_t lc_dft_en; + + // Jitter enable + prim_mubi_pkg::mubi4_t jen; + + // reset domain connections + import rstmgr_pkg::PowerDomains; + import rstmgr_pkg::DomainAonSel; + import rstmgr_pkg::Domain0Sel; + + // Memory configuration connections + ast_pkg::spm_rm_t ast_ram_1p_cfg; + ast_pkg::spm_rm_t ast_rf_cfg; + ast_pkg::spm_rm_t ast_rom_cfg; + ast_pkg::dpm_rm_t ast_ram_2p_fcfg; + ast_pkg::dpm_rm_t ast_ram_2p_lcfg; + + // conversion from ast structure to memory centric structures + prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg; + assign ram_1p_cfg = '{ + ram_cfg: '{ + test: ast_ram_1p_cfg.test, + cfg_en: ast_ram_1p_cfg.marg_en, + cfg: ast_ram_1p_cfg.marg + }, + rf_cfg: '{ + test: ast_rf_cfg.test, + cfg_en: ast_rf_cfg.marg_en, + cfg: ast_rf_cfg.marg + } + }; + + logic unused_usb_ram_2p_cfg; + assign unused_usb_ram_2p_cfg = ^{ast_ram_2p_fcfg.marg_en_a, + ast_ram_2p_fcfg.marg_a, + ast_ram_2p_fcfg.test_a, + ast_ram_2p_fcfg.marg_en_b, + ast_ram_2p_fcfg.marg_b, + ast_ram_2p_fcfg.test_b}; + + // this maps as follows: + // assign spi_ram_2p_cfg = {10'h000, ram_2p_cfg_i.a_ram_lcfg, ram_2p_cfg_i.b_ram_lcfg}; + prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg; + assign spi_ram_2p_cfg = '{ + a_ram_lcfg: '{ + test: ast_ram_2p_lcfg.test_a, + cfg_en: ast_ram_2p_lcfg.marg_en_a, + cfg: ast_ram_2p_lcfg.marg_a + }, + b_ram_lcfg: '{ + test: ast_ram_2p_lcfg.test_b, + cfg_en: ast_ram_2p_lcfg.marg_en_b, + cfg: ast_ram_2p_lcfg.marg_b + }, + default: '0 + }; + + prim_rom_pkg::rom_cfg_t rom_ctrl0_cfg; + prim_rom_pkg::rom_cfg_t rom_ctrl1_cfg; + + assign rom_ctrl0_cfg = '{ + test: ast_rom_cfg.test, + cfg_en: ast_rom_cfg.marg_en, + cfg: ast_rom_cfg.marg + }; + assign rom_ctrl1_cfg = '{ + test: ast_rom_cfg.test, + cfg_en: ast_rom_cfg.marg_en, + cfg: ast_rom_cfg.marg + }; + + ////////////////////////////////// + // AST - Custom for targets // + ////////////////////////////////// + + + assign ast_base_pwr.main_pok = ast_pwst.main_pok; + + logic [rstmgr_pkg::PowerDomains-1:0] por_n; + assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok}; + + // TODO: Hook this up when FPGA pads are updated + assign ext_clk = '0; + assign pad2ast = '0; + + logic clk_main, clk_usb_48mhz, clk_aon, rst_n, srst_n; + clkgen_xil7series # ( + .AddClkBuf(0) + ) clkgen ( + .clk_i(manual_in_io_clk), + .rst_ni(manual_in_por_n), + .srst_ni(srst_n), + .clk_main_o(clk_main), + .clk_48MHz_o(clk_usb_48mhz), + .clk_aon_o(clk_aon), + .rst_no(rst_n) + ); + + logic [31:0] fpga_info; + usr_access_xil7series u_info ( + .info_o(fpga_info) + ); + + ast_pkg::clks_osc_byp_t clks_osc_byp; + assign clks_osc_byp = '{ + usb: clk_usb_48mhz, + sys: clk_main, + io: clk_main, + aon: clk_aon + }; + + + prim_mubi_pkg::mubi4_t ast_init_done; + + ast #( + .AdcChannels(ast_pkg::AdcChannels), + .AdcDataWidth(ast_pkg::AdcDataWidth), + .UsbCalibWidth(ast_pkg::UsbCalibWidth), + .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth), + .Pad2AstInWidth(ast_pkg::Pad2AstInWidth) + ) u_ast ( + // external POR + .por_ni ( rst_n ), + + // USB IO Pull-up Calibration Setting + .usb_io_pu_cal_o ( ), + + // clocks' oschillator bypass for FPGA + .clk_osc_byp_i ( clks_osc_byp ), + + // adc + .adc_a0_ai ( '0 ), + .adc_a1_ai ( '0 ), + + // Direct short to PAD + .ast2pad_t0_ao ( ), + .ast2pad_t1_ao ( ), + + // clocks and resets supplied for detection + .sns_clks_i ( clkmgr_aon_clocks ), + .sns_rsts_i ( rstmgr_aon_resets ), + .sns_spi_ext_clk_i ( sck_monitor ), + // tlul + .tl_i ( base_ast_bus ), + .tl_o ( ast_base_bus ), + // init done indication + .ast_init_done_o ( ast_init_done ), + // buffered clocks & resets + .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_infra), + .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_peri), + .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_adc_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), + .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_ast_rng_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .clk_ast_ext_i ( ext_clk ), + + // pok test for FPGA + .vcc_supp_i ( 1'b1 ), + .vcaon_supp_i ( 1'b1 ), + .vcmain_supp_i ( 1'b1 ), + .vioa_supp_i ( 1'b1 ), + .viob_supp_i ( 1'b1 ), + // pok + .ast_pwst_o ( ast_pwst ), + .ast_pwst_h_o ( ), + // main regulator + .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ), + .main_pd_ni ( base_ast_pwr.main_pd_n ), + // pdm control (flash)/otp + .flash_power_down_h_o ( ), + .flash_power_ready_h_o ( ), + .otp_power_seq_i ( otp_macro_pwr_seq ), + .otp_power_seq_h_o ( otp_macro_pwr_seq_h ), + // system source clock + .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ), + // need to add function in clkmgr + .clk_src_sys_jen_i ( jen ), + .clk_src_sys_o ( ast_base_clks.clk_sys ), + .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ), + // aon source clock + .clk_src_aon_o ( ast_base_clks.clk_aon ), + .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ), + // io source clock + .clk_src_io_en_i ( base_ast_pwr.io_clk_en ), + .clk_src_io_o ( ast_base_clks.clk_io ), + .clk_src_io_val_o ( ast_base_pwr.io_clk_val ), + .clk_src_io_48m_o ( div_step_down_req ), + // usb source clock + .usb_ref_pulse_i ( '0 ), + .usb_ref_val_i ( '0 ), + .clk_src_usb_en_i ( '0 ), + .clk_src_usb_o ( ), + .clk_src_usb_val_o ( ), + // adc + .adc_pd_i ( '0 ), + .adc_chnsel_i ( '0 ), + .adc_d_o ( ), + .adc_d_val_o ( ), + // rng + .rng_en_i ( es_rng_enable ), + .rng_fips_i ( es_rng_fips ), + .rng_val_o ( es_rng_valid ), + .rng_b_o ( es_rng_bit ), + // alerts + .alert_rsp_i ( ast_alert_rsp ), + .alert_req_o ( ast_alert_req ), + // dft + .lc_dft_en_i ( lc_dft_en ), + .fla_obs_i ( '0 ), + .usb_obs_i ( '0 ), + .otp_obs_i ( otp_obs ), + .otm_obs_i ( '0 ), + .obs_ctrl_o ( obs_ctrl ), + // pinmux related + .padmux2ast_i ( '0 ), + .ast2padmux_o ( ), + .ext_freq_is_96m_i ( hi_speed_sel ), + .all_clk_byp_req_i ( all_clk_byp_req ), + .all_clk_byp_ack_o ( all_clk_byp_ack ), + .io_clk_byp_req_i ( io_clk_byp_req ), + .io_clk_byp_ack_o ( io_clk_byp_ack ), + .flash_bist_en_o ( ), + // Memory configuration connections + .dpram_rmf_o ( ast_ram_2p_fcfg ), + .dpram_rml_o ( ast_ram_2p_lcfg ), + .spram_rm_o ( ast_ram_1p_cfg ), + .sprgf_rm_o ( ast_rf_cfg ), + .sprom_rm_o ( ast_rom_cfg ), + // scan + .dft_scan_md_o ( scanmode ), + .scan_shift_en_o ( scan_en ), + .scan_reset_no ( scan_rst_n ) + ); + + ////////////////// + // TAP Instance // + ////////////////// + + tlul_pkg::tl_h2d_t dmi_h2d; + tlul_pkg::tl_d2h_t dmi_d2h; + jtag_pkg::jtag_req_t jtag_req; + jtag_pkg::jtag_rsp_t jtag_rsp; + + assign jtag_req.tck = manual_in_jtag_tck; + assign jtag_req.tms = manual_in_jtag_tms; + assign jtag_req.trst_n = manual_in_jtag_trst_n; + assign jtag_req.tdi = manual_in_jtag_tdi; + + assign manual_out_jtag_tck = '0; + assign manual_out_jtag_tms = '0; + assign manual_out_jtag_trst_n = '0; + assign manual_out_jtag_tdi = '0; + assign manual_oe_jtag_tck = '0; + assign manual_oe_jtag_tms = '0; + assign manual_oe_jtag_trst_n = '0; + assign manual_oe_jtag_tdi = '0; + assign manual_attr_jtag_tck = '0; + assign manual_attr_jtag_tms = '0; + assign manual_attr_jtag_trst_n = '0; + assign manual_attr_jtag_tdi = '0; + + assign manual_out_jtag_tdo = jtag_rsp.tdo; + assign manual_oe_jtag_tdo = jtag_rsp.tdo_oe; + assign manual_attr_jtag_tdo = '0; + + logic unused_manual_jtag_sigs; + assign unused_manual_jtag_sigs = ^{ + manual_in_jtag_tdo + }; + + tlul_jtag_dtm #( + .IdcodeValue(jtag_id_pkg::LC_DM_COMBINED_JTAG_IDCODE), + // Notes: + // - one RV_DM instance uses 9bits + // - our crossbar tooling expects individual IPs to be spaced apart by 12bits at the moment + // - the DMI address shifted through jtag is a word address and hence 2bits smaller than this + // - setting this to 18bits effectively gives us 2^6 = 64 addressable 12bit ranges + .NumDmiByteAbits(18) + ) u_tlul_jtag_dtm ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), + .jtag_i (jtag_req), + .jtag_o (jtag_rsp), + .scan_rst_ni(scan_rst_n), + .scanmode_i (scanmode), + .tl_h2d_o (dmi_h2d), + .tl_d2h_i (dmi_d2h) + ); + + // TODO: Resolve this and wire it up. + tlul_pkg::tl_h2d_t ctn_misc_tl_h2d_i; + assign ctn_misc_tl_h2d_i = tlul_pkg::TL_H2D_DEFAULT; + tlul_pkg::tl_d2h_t ctn_misc_tl_d2h_o; + + // TODO: Over/ride/ all access range checks for now. + prim_mubi_pkg::mubi8_t ac_range_check_overwrite_i; + assign ac_range_check_overwrite_i = prim_mubi_pkg::MuBi8True; + + // TODO: External RACL error input. + top_racl_pkg::racl_error_log_t ext_racl_error; + assign ext_racl_error = '0; + + //////////////// + // CTN M-to-1 // + //////////////// + + tlul_pkg::tl_h2d_t ctn_tl_h2d[2]; + tlul_pkg::tl_d2h_t ctn_tl_d2h[2]; + //TODO: Resolve this and wire it up. + assign ctn_tl_h2d[1] = tlul_pkg::TL_H2D_DEFAULT; + + tlul_pkg::tl_h2d_t ctn_sm1_to_s1n_tl_h2d; + tlul_pkg::tl_d2h_t ctn_sm1_to_s1n_tl_d2h; + + tlul_socket_m1 #( + .M (2), + .HReqPass ({2{1'b1}}), + .HRspPass ({2{1'b1}}), + .HReqDepth ({2{4'd0}}), + .HRspDepth ({2{4'd0}}), + .DReqPass (1'b1), + .DRspPass (1'b1), + .DReqDepth (4'd0), + .DRspDepth (4'd0) + ) u_ctn_sm1 ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_tl_h2d), + .tl_h_o (ctn_tl_d2h), + .tl_d_o (ctn_sm1_to_s1n_tl_h2d), + .tl_d_i (ctn_sm1_to_s1n_tl_d2h) + ); + + //////////////////////////////////////////// + // CTN Address decoding and SRAM Instance // + //////////////////////////////////////////// + + localparam int CtnSramDw = top_pkg::TL_DW + tlul_pkg::DataIntgWidth; + + tlul_pkg::tl_h2d_t ctn_s1n_tl_h2d[1]; + tlul_pkg::tl_d2h_t ctn_s1n_tl_d2h[1]; + + // Steering signal for address decoding. + logic [0:0] ctn_dev_sel_s1n; + + logic sram_req, sram_we, sram_rvalid; + logic [top_pkg::CtnSramAw-1:0] sram_addr; + logic [CtnSramDw-1:0] sram_wdata, sram_wmask, sram_rdata; + + // Steering of requests. + // Addresses leaving the RoT through the CTN port are mapped to an internal 1G address space of + // 0x4000_0000 - 0x8000_0000. However, the CTN RAM only covers a 1MB region inside that space, + // and hence additional decoding and steering logic is needed here. + // TODO: this should in the future be replaced by an automatically generated crossbar. + always_comb begin + // Default steering to generate error response if address is not within the range + ctn_dev_sel_s1n = 1'b1; + // Steering to CTN SRAM. + if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_RAM_CTN_SIZE_BYTES-1)) == + (TOP_DARJEELING_RAM_CTN_BASE_ADDR - TOP_DARJEELING_CTN_BASE_ADDR)) begin + ctn_dev_sel_s1n = 1'd0; + end + end + + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (8'h0), + .DRspDepth (8'h0), + .N (1) + ) u_ctn_s1n ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_sm1_to_s1n_tl_h2d), + .tl_h_o (ctn_sm1_to_s1n_tl_d2h), + .tl_d_o (ctn_s1n_tl_h2d), + .tl_d_i (ctn_s1n_tl_d2h), + .dev_select_i (ctn_dev_sel_s1n) + ); + + tlul_adapter_sram #( + .SramAw(top_pkg::CtnSramAw), + .SramDw(CtnSramDw - tlul_pkg::DataIntgWidth), + .Outstanding(2), + .ByteAccess(1), + .CmdIntgCheck(1), + .EnableRspIntgGen(1), + .EnableDataIntgGen(0), + .EnableDataIntgPt(1), + .SecFifoPtr (0) + ) u_tlul_adapter_sram_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_i (ctn_s1n_tl_h2d[0]), + .tl_o (ctn_s1n_tl_d2h[0]), + // Ifetch is explicitly allowed + .en_ifetch_i (prim_mubi_pkg::MuBi4True), + .req_o (sram_req), + .req_type_o (), + // SRAM can always accept a request. + .gnt_i (1'b1), + .we_o (sram_we), + .addr_o (sram_addr), + .wdata_o (sram_wdata), + .wmask_o (sram_wmask), + .intg_error_o(), + .user_rsvd_o (), + .rdata_i (sram_rdata), + .rvalid_i (sram_rvalid), + .rerror_i ('0), + .compound_txn_in_progress_o(), + .readback_en_i(prim_mubi_pkg::MuBi4False), + .readback_error_o(), + .wr_collision_i(1'b0), + .write_pending_i(1'b0) + ); + + prim_ram_1p_adv #( + .Depth(top_pkg::CtnSramDepth), + .Width(CtnSramDw), + .DataBitsPerMask(CtnSramDw), + .EnableECC(0), + .EnableParity(0), + .EnableInputPipeline(1), + .EnableOutputPipeline(1) + ) u_prim_ram_1p_adv_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .req_i (sram_req), + .write_i (sram_we), + .addr_i (sram_addr), + .wdata_i (sram_wdata), + .wmask_i (sram_wmask), + .rdata_o (sram_rdata), + .rvalid_o (sram_rvalid), + // No error detection is enabled inside SRAM. + // Bus ECC is checked at the consumer side. + .rerror_o (), + .cfg_i (ram_1p_cfg), + .cfg_rsp_o(), + .alert_o() + ); + + + +logic unused_signals; +assign unused_signals = ^{pwrmgr_boot_status.clk_status, + pwrmgr_boot_status.cpu_fetch_en, + pwrmgr_boot_status.lc_done, + pwrmgr_boot_status.otp_done, + pwrmgr_boot_status.rom_ctrl_status, + pwrmgr_boot_status.strap_sampled}; + + ////////////////// + // PLL for FPGA // + ////////////////// + + assign manual_attr_io_clk = '0; + assign manual_out_io_clk = 1'b0; + assign manual_oe_io_clk = 1'b0; + assign manual_attr_por_n = '0; + assign manual_out_por_n = 1'b0; + assign manual_oe_por_n = 1'b0; + assign manual_attr_por_button_n = '0; + assign manual_out_por_button_n = 1'b0; + assign manual_oe_por_button_n = 1'b0; + + assign srst_n = manual_in_por_button_n; + + // Extend the internal reset request from the power manager. + // + // TODO: To model the SoC within FPGA this logic is insufficient; its presence here + // is to avoid a design that locks up awaiting the deassertion of the signal + // `soc_rst_req_async_i` in response to an internal reset request. + logic internal_request_d, internal_request_q; + logic external_reset, count_up; + logic [3:0] count; + always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin + if (!por_n[0]) begin + external_reset <= 1'b0; + internal_request_q <= 1'b0; + count_up <= '0; + count <= '0; + end else begin + internal_request_q <= internal_request_d; + if (!internal_request_q && internal_request_d) begin + count_up <= 1'b1; + external_reset <= 1; + end else if (count == 'd8) begin + count_up <= 0; + external_reset <= 0; + count <= '0; + end else if (count_up) begin + count <= count + 1; + end + end + end + + ////////////////////// + // Top-level design // + ////////////////////// + + // the rst_ni pin only goes to AST + // the rest of the logic generates reset based on the 'pok' signal. + // for verilator purposes, make these two the same. + prim_mubi_pkg::mubi4_t lc_clk_bypass; // TODO Tim + +// TODO: align this with ASIC version to minimize the duplication. +// Also need to add AST simulation and FPGA emulation models for things like entropy source - +// otherwise Verilator / FPGA will hang. + top_darjeeling_no_ibex #( + .SecAesMasking(1'b1), + .SecAesSBoxImpl(aes_pkg::SBoxImplDom), + .SecAesStartTriggerDelay(320), + .SecAesAllowForcingMasks(1'b1), + .KmacEnMasking(0), + .KmacSwKeyMasked(1), + .SecKmacCmdDelay(320), + .SecKmacIdleAcceptSwMsg(1'b1), + .KeymgrDpeKmacEnMasking(0), + .CsrngSBoxImpl(aes_pkg::SBoxImplLut), + .OtbnRegFile(otbn_pkg::RegFileFPGA), + .SecOtbnMuteUrnd(1'b1), + .SecOtbnSkipUrndReseedAtStart(1'b1), + .OtpMacroMemInitFile(OtpMacroMemInitFile), + .RvCoreIbexPipeLine(1), + .SramCtrlRetAonInstrExec(0), + // TODO(opentitan-integrated/issues/251): + // Enable hashing below once the build infrastructure can + // load scrambled images on FPGA platforms. The DV can + // already partially handle it by initializing the 2nd ROM + // with random data via the backdoor loading interface - it + // can't load "real" SW images yet since that requires + // additional build infrastructure. + .SecRomCtrl1DisableScrambling(1), + .RomCtrl0BootRomInitFile(BootRomInitFile), + .RvCoreIbexRegFile(ibex_pkg::RegFileFPGA), + .RvCoreIbexSecureIbex(0), + .SramCtrlMainInstrExec(1), + .PinmuxAonTargetCfg(PinmuxTargetCfg) + ) top_darjeeling_no_ibex ( + .por_n_i ( por_n ), + .clk_main_i ( ast_base_clks.clk_sys ), + .clk_io_i ( ast_base_clks.clk_io ), + .clk_aon_i ( ast_base_clks.clk_aon ), + .clks_ast_o ( clkmgr_aon_clocks ), + .clk_main_jitter_en_o ( jen ), + .rsts_ast_o ( rstmgr_aon_resets ), + .integrator_id_i ( '0 ), + .sck_monitor_o ( sck_monitor ), + .pwrmgr_ast_req_o ( base_ast_pwr ), + .pwrmgr_ast_rsp_i ( ast_base_pwr ), + .obs_ctrl_i ( obs_ctrl ), + .io_clk_byp_req_o ( io_clk_byp_req ), + .io_clk_byp_ack_i ( io_clk_byp_ack ), + .all_clk_byp_req_o ( all_clk_byp_req ), + .all_clk_byp_ack_i ( all_clk_byp_ack ), + .hi_speed_sel_o ( hi_speed_sel ), + .div_step_down_req_i ( div_step_down_req ), + .fpga_info_i ( fpga_info ), + .ast_tl_req_o ( base_ast_bus ), + .ast_tl_rsp_i ( ast_base_bus ), + .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), + .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), + .otp_obs_o ( otp_obs ), + .otp_cfg_i ( otp_cfg ), + .otp_cfg_rsp_o ( otp_cfg_rsp ), + .ctn_tl_h2d_o ( ctn_tl_h2d[0] ), + .ctn_tl_d2h_i ( ctn_tl_d2h[0] ), + .ac_range_check_overwrite_i ( ac_range_check_overwrite_i ), + .racl_error_i ( ext_racl_error ), + .soc_gpi_async_o ( ), + .soc_gpo_async_i ( '0 ), + .soc_dbg_policy_bus_o ( soc_dbg_policy_bus ), + .debug_halt_cpu_boot_i ( '0 ), + .dma_sys_req_o ( ), + .dma_sys_rsp_i ( '0 ), + .soc_rst_req_async_i ( external_reset ), + .soc_lsio_trigger_i ( '0 ), + .es_rng_enable_o ( es_rng_enable ), + .es_rng_valid_i ( es_rng_valid ), + .es_rng_bit_i ( es_rng_bit ), + .calib_rdy_i ( ast_init_done ), + + // DMI TL-UL + .dbg_tl_req_i ( dmi_h2d ), + .dbg_tl_rsp_o ( dmi_d2h ), + // Quasi-static word address for next_dm register value. + .rv_dm_next_dm_addr_i ( '0 ), + // Multiplexed I/O + .mio_in_i ( mio_in ), + .mio_out_o ( mio_out ), + .mio_oe_o ( mio_oe ), + + // Dedicated I/O + .dio_in_i ( dio_in ), + .dio_out_o ( dio_out ), + .dio_oe_o ( dio_oe ), + + // Pad attributes + .mio_attr_o ( mio_attr ), + .dio_attr_o ( dio_attr ), + + // Memory attributes + .rom_ctrl0_cfg_i ( '0 ), + .rom_ctrl1_cfg_i ( '0 ), + .i2c_ram_1p_cfg_i ( '0 ), + .i2c_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_ret_aon_ram_1p_cfg_i ( '0 ), + .sram_ctrl_ret_aon_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_main_ram_1p_cfg_i ( '0 ), + .sram_ctrl_main_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_mbox_ram_1p_cfg_i ( '0 ), + .sram_ctrl_mbox_ram_1p_cfg_rsp_o ( ), + .otbn_imem_ram_1p_cfg_i ( '0 ), + .otbn_imem_ram_1p_cfg_rsp_o ( ), + .otbn_dmem_ram_1p_cfg_i ( '0 ), + .otbn_dmem_ram_1p_cfg_rsp_o ( ), + .rv_core_ibex_icache_tag_ram_1p_cfg_i ( '0 ), + .rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o ( ), + .rv_core_ibex_icache_data_ram_1p_cfg_i ( '0 ), + .rv_core_ibex_icache_data_ram_1p_cfg_rsp_o ( ), + .spi_device_ram_2p_cfg_sys2spi_i ( '0 ), + .spi_device_ram_2p_cfg_spi2sys_i ( '0 ), + .spi_device_ram_2p_cfg_rsp_sys2spi_o ( ), + .spi_device_ram_2p_cfg_rsp_spi2sys_o ( ), + + // DFT signals + .ast_lc_dft_en_o ( lc_dft_en ), + .ast_lc_hw_debug_en_o ( ), + // DFT signals + .dft_hold_tap_sel_i ( '0 ), + .scan_rst_ni ( 1'b1 ), + .scan_en_i ( 1'b0 ), + .scanmode_i ( prim_mubi_pkg::MuBi4False ) + ); + + + ///////////////////////////////////////////////////// + // ChipWhisperer CW310/305 Capture Board Interface // + ///////////////////////////////////////////////////// + // This is used to interface OpenTitan as a target with a capture board trough the ChipWhisperer + // 20-pin connector. This is used for SCA/FI experiments only. + + logic unused_inputs; + assign unused_inputs = manual_in_io_clkout ^ manual_in_io_trigger; + + // Synchronous clock output to capture board. + assign manual_out_io_clkout = manual_in_io_clk; + assign manual_oe_io_clkout = 1'b1; + + // Capture trigger. + // We use the clkmgr_aon_idle signal of the IP of interest to form a precise capture trigger. + // GPIO[11:10] is used for selecting the IP of interest. The encoding is as follows (see + // hint_names_e enum in clkmgr_pkg.sv for details). + // + // IP - GPIO[11:10] - Index for clkmgr_aon_idle + // ------------------------------------------------------------- + // AES - 00 - 0 + // HMAC - 01 - 1 - not implemented on CW305 + // KMAC - 10 - 2 - not implemented on CW305 + // OTBN - 11 - 3 - not implemented on CW305 + // + // GPIO9 is used for gating the selected capture trigger in software. Alternatively, GPIO8 + // can be used to implement a less precise but fully software-controlled capture trigger + // similar to what can be done on ASIC. + // + // Note that on the CW305, GPIO[9,8] are connected to LED[5(Green),7(Red)]. + + prim_mubi_pkg::mubi4_t clk_trans_idle, manual_in_io_clk_idle; + + clkmgr_pkg::hint_names_e trigger_sel; + always_comb begin : trigger_sel_mux + unique case ({mio_out[MioOutGpioGpio11], mio_out[MioOutGpioGpio10]}) + 2'b00: trigger_sel = clkmgr_pkg::HintMainAes; + 2'b01: trigger_sel = clkmgr_pkg::HintMainHmac; + 2'b10: trigger_sel = clkmgr_pkg::HintMainKmac; + 2'b11: trigger_sel = clkmgr_pkg::HintMainOtbn; + default: trigger_sel = clkmgr_pkg::HintMainAes; + endcase; + end + assign clk_trans_idle = top_darjeeling_no_ibex.clkmgr_aon_idle[trigger_sel]; + + logic clk_io_div4_trigger_hw_en, manual_in_io_clk_trigger_hw_en; + logic clk_io_div4_trigger_hw_oe, manual_in_io_clk_trigger_hw_oe; + logic clk_io_div4_trigger_sw_en, manual_in_io_clk_trigger_sw_en; + logic clk_io_div4_trigger_sw_oe, manual_in_io_clk_trigger_sw_oe; + assign clk_io_div4_trigger_hw_en = mio_out[MioOutGpioGpio9]; + assign clk_io_div4_trigger_hw_oe = mio_oe[MioOutGpioGpio9]; + assign clk_io_div4_trigger_sw_en = mio_out[MioOutGpioGpio8]; + assign clk_io_div4_trigger_sw_oe = mio_oe[MioOutGpioGpio8]; + + // Synchronize signals to manual_in_io_clk. + prim_flop_2sync #( + .Width ($bits(clk_trans_idle) + 4) + ) u_sync_trigger ( + .clk_i (manual_in_io_clk), + .rst_ni(manual_in_por_n), + .d_i ({clk_trans_idle, + clk_io_div4_trigger_hw_en, + clk_io_div4_trigger_hw_oe, + clk_io_div4_trigger_sw_en, + clk_io_div4_trigger_sw_oe}), + .q_o ({manual_in_io_clk_idle, + manual_in_io_clk_trigger_hw_en, + manual_in_io_clk_trigger_hw_oe, + manual_in_io_clk_trigger_sw_en, + manual_in_io_clk_trigger_sw_oe}) + ); + + // Generate the actual trigger signal as trigger_sw OR trigger_hw. + assign manual_attr_io_trigger = '0; + assign manual_oe_io_trigger = + manual_in_io_clk_trigger_sw_oe | manual_in_io_clk_trigger_hw_oe; + assign manual_out_io_trigger = + manual_in_io_clk_trigger_sw_en | (manual_in_io_clk_trigger_hw_en & + prim_mubi_pkg::mubi4_test_false_strict(manual_in_io_clk_idle)); + +endmodule : chip_darjeeling_no_ibex_cw310 diff --git a/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex.sv b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex.sv new file mode 100644 index 00000000000..efae43591b1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex.sv @@ -0,0 +1,3208 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +`include "prim_assert.sv" + +module top_darjeeling_no_ibex #( + // Manually defined parameters + + // Auto-inferred parameters + // parameters for uart0 + // parameters for gpio + parameter bit GpioGpioAsyncOn = 1, + parameter bit GpioGpioAsHwStrapsEn = 1, + // parameters for spi_device + parameter spi_device_pkg::sram_type_e SpiDeviceSramType = spi_device_pkg::SramType1r1w, + // parameters for i2c0 + parameter int I2c0InputDelayCycles = 0, + // parameters for otp_ctrl + // parameters for otp_macro + parameter OtpMacroMemInitFile = "", + // parameters for lc_ctrl + parameter bit SecLcCtrlVolatileRawUnlockEn = top_pkg::SecVolatileRawUnlockEn, + parameter bit LcCtrlUseDmiInterface = 1, + parameter logic [15:0] LcCtrlSiliconCreatorId = 16'h 4002, + parameter logic [15:0] LcCtrlProductId = 16'h 4000, + parameter logic [7:0] LcCtrlRevisionId = 8'h 01, + parameter logic [31:0] LcCtrlIdcodeValue = 32'h00000001, + // parameters for alert_handler + parameter int AlertHandlerEscNumSeverities = 4, + parameter int AlertHandlerEscPingCountWidth = 16, + // parameters for spi_host0 + // parameters for pwrmgr_aon + // parameters for rstmgr_aon + parameter bit SecRstmgrAonCheck = 1'b1, + parameter int SecRstmgrAonMaxSyncDelay = 2, + // parameters for clkmgr_aon + // parameters for pinmux_aon + parameter pinmux_pkg::target_cfg_t PinmuxAonTargetCfg = pinmux_pkg::DefaultTargetCfg, + // parameters for aon_timer_aon + // parameters for soc_proxy + // parameters for sram_ctrl_ret_aon + parameter int SramCtrlRetAonInstSize = 4096, + parameter int SramCtrlRetAonNumRamInst = 1, + parameter bit SramCtrlRetAonInstrExec = 0, + parameter int SramCtrlRetAonNumPrinceRoundsHalf = 3, + parameter bit SramCtrlRetAonEccCorrection = 0, + // parameters for rv_plic + // parameters for aes + parameter bit SecAesMasking = 1, + parameter aes_pkg::sbox_impl_e SecAesSBoxImpl = aes_pkg::SBoxImplDom, + parameter int unsigned SecAesStartTriggerDelay = 0, + parameter bit SecAesAllowForcingMasks = 1'b0, + parameter bit SecAesSkipPRNGReseeding = 1'b0, + // parameters for hmac + // parameters for kmac + parameter bit KmacEnMasking = 1, + parameter bit KmacSwKeyMasked = 0, + parameter int SecKmacCmdDelay = 0, + parameter bit SecKmacIdleAcceptSwMsg = 0, + parameter int KmacNumAppIntf = 4, + parameter kmac_pkg::app_config_t KmacAppCfg[KmacNumAppIntf] = + '{kmac_pkg::AppCfgKeyMgr, + kmac_pkg::AppCfgLcCtrl, + kmac_pkg::AppCfgRomCtrl, + kmac_pkg::AppCfgRomCtrl}, + // parameters for otbn + parameter bit OtbnStub = 0, + parameter otbn_pkg::regfile_e OtbnRegFile = otbn_pkg::RegFileFF, + parameter bit SecOtbnMuteUrnd = 0, + parameter bit SecOtbnSkipUrndReseedAtStart = 0, + // parameters for keymgr_dpe + parameter bit KeymgrDpeKmacEnMasking = 1, + // parameters for csrng + parameter aes_pkg::sbox_impl_e CsrngSBoxImpl = aes_pkg::SBoxImplCanright, + // parameters for entropy_src + parameter int EntropySrcRngBusWidth = 16, + parameter int EntropySrcRngBusBitSelWidth = 4, + parameter int EntropySrcHealthTestWindowWidth = 20, + parameter bit EntropySrcStub = 0, + // parameters for edn0 + // parameters for edn1 + // parameters for sram_ctrl_main + parameter int SramCtrlMainInstSize = 65536, + parameter int SramCtrlMainNumRamInst = 1, + parameter bit SramCtrlMainInstrExec = 1, + parameter int SramCtrlMainNumPrinceRoundsHalf = 3, + parameter bit SramCtrlMainEccCorrection = 0, + // parameters for sram_ctrl_mbox + parameter int SramCtrlMboxInstSize = 4096, + parameter int SramCtrlMboxNumRamInst = 1, + parameter bit SramCtrlMboxInstrExec = 0, + parameter int SramCtrlMboxNumPrinceRoundsHalf = 3, + parameter bit SramCtrlMboxEccCorrection = 0, + // parameters for rom_ctrl0 + parameter RomCtrl0BootRomInitFile = "", + parameter bit SecRomCtrl0DisableScrambling = 1'b0, + // parameters for rom_ctrl1 + parameter RomCtrl1BootRomInitFile = "", + parameter bit SecRomCtrl1DisableScrambling = 1'b0, + // parameters for dma + parameter bit DmaEnableDataIntgGen = 1'b1, + parameter bit DmaEnableRspDataIntgCheck = 1'b1, + parameter logic [tlul_pkg::RsvdWidth-1:0] DmaTlUserRsvd = '0, + parameter logic [dma_pkg::SYS_RACL_WIDTH-1:0] DmaSysRacl = '0, + parameter int unsigned DmaOtAgentId = 0, + // parameters for mbx0 + // parameters for mbx1 + // parameters for mbx2 + // parameters for mbx3 + // parameters for mbx4 + // parameters for mbx5 + // parameters for mbx6 + // parameters for mbx_jtag + // parameters for mbx_pcie0 + // parameters for mbx_pcie1 + // parameters for soc_dbg_ctrl + // parameters for racl_ctrl + parameter int RaclCtrlNumExternalSubscribingIps = 1, + // parameters for ac_range_check + parameter bit AcRangeCheckRangeCheckErrorRsp = 1 +) ( + // Multiplexed I/O + input [11:0] mio_in_i, + output logic [11:0] mio_out_o, + output logic [11:0] mio_oe_o, + // Dedicated I/O + input [72:0] dio_in_i, + output logic [72:0] dio_out_o, + output logic [72:0] dio_oe_o, + + // pad attributes to padring + output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr_o, + output prim_pad_wrapper_pkg::pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr_o, + + + // Inter-module Signal External type + output lc_ctrl_pkg::lc_tx_t ast_lc_dft_en_o, + output lc_ctrl_pkg::lc_tx_t ast_lc_hw_debug_en_o, + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + input prim_rom_pkg::rom_cfg_t rom_ctrl0_cfg_i, + input prim_rom_pkg::rom_cfg_t rom_ctrl1_cfg_i, + input prim_ram_1p_pkg::ram_1p_cfg_t i2c_ram_1p_cfg_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t i2c_ram_1p_cfg_rsp_o, + input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlRetAonNumRamInst-1:0] sram_ctrl_ret_aon_ram_1p_cfg_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlRetAonNumRamInst-1:0] sram_ctrl_ret_aon_ram_1p_cfg_rsp_o, + input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlMainNumRamInst-1:0] sram_ctrl_main_ram_1p_cfg_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlMainNumRamInst-1:0] sram_ctrl_main_ram_1p_cfg_rsp_o, + input prim_ram_1p_pkg::ram_1p_cfg_t [SramCtrlMboxNumRamInst-1:0] sram_ctrl_mbox_ram_1p_cfg_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t [SramCtrlMboxNumRamInst-1:0] sram_ctrl_mbox_ram_1p_cfg_rsp_o, + input prim_ram_1p_pkg::ram_1p_cfg_t otbn_imem_ram_1p_cfg_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t otbn_imem_ram_1p_cfg_rsp_o, + input prim_ram_1p_pkg::ram_1p_cfg_t otbn_dmem_ram_1p_cfg_i, + output prim_ram_1p_pkg::ram_1p_cfg_rsp_t otbn_dmem_ram_1p_cfg_rsp_o, + output logic no_ibex_msip_o, + output logic no_ibex_irq_o, + input prim_ram_2p_pkg::ram_2p_cfg_t spi_device_ram_2p_cfg_sys2spi_i, + output prim_ram_2p_pkg::ram_2p_cfg_rsp_t spi_device_ram_2p_cfg_rsp_sys2spi_o, + output prim_ram_2p_pkg::ram_2p_cfg_rsp_t spi_device_ram_2p_cfg_rsp_spi2sys_o, + input prim_ram_2p_pkg::ram_2p_cfg_t spi_device_ram_2p_cfg_spi2sys_i, + output pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status_o, + output prim_mubi_pkg::mubi4_t clk_main_jitter_en_o, + output prim_mubi_pkg::mubi4_t io_clk_byp_req_o, + input prim_mubi_pkg::mubi4_t io_clk_byp_ack_i, + output prim_mubi_pkg::mubi4_t all_clk_byp_req_o, + input prim_mubi_pkg::mubi4_t all_clk_byp_ack_i, + output prim_mubi_pkg::mubi4_t hi_speed_sel_o, + input prim_mubi_pkg::mubi4_t div_step_down_req_i, + input prim_mubi_pkg::mubi4_t calib_rdy_i, + output dma_pkg::sys_req_t dma_sys_req_o, + input dma_pkg::sys_rsp_t dma_sys_rsp_i, + output logic es_rng_enable_o, + input logic es_rng_valid_i, + input logic [EntropySrcRngBusWidth-1:0] es_rng_bit_i, + output logic es_rng_fips_o, + input tlul_pkg::tl_h2d_t mbx_tl_req_i, + output tlul_pkg::tl_d2h_t mbx_tl_rsp_o, + output logic mbx0_doe_intr_o, + output logic mbx0_doe_intr_en_o, + output logic mbx0_doe_intr_support_o, + output logic mbx0_doe_async_msg_support_o, + output logic mbx1_doe_intr_o, + output logic mbx1_doe_intr_en_o, + output logic mbx1_doe_intr_support_o, + output logic mbx1_doe_async_msg_support_o, + output logic mbx2_doe_intr_o, + output logic mbx2_doe_intr_en_o, + output logic mbx2_doe_intr_support_o, + output logic mbx2_doe_async_msg_support_o, + output logic mbx3_doe_intr_o, + output logic mbx3_doe_intr_en_o, + output logic mbx3_doe_intr_support_o, + output logic mbx3_doe_async_msg_support_o, + output logic mbx4_doe_intr_o, + output logic mbx4_doe_intr_en_o, + output logic mbx4_doe_intr_support_o, + output logic mbx4_doe_async_msg_support_o, + output logic mbx5_doe_intr_o, + output logic mbx5_doe_intr_en_o, + output logic mbx5_doe_intr_support_o, + output logic mbx5_doe_async_msg_support_o, + output logic mbx6_doe_intr_o, + output logic mbx6_doe_intr_en_o, + output logic mbx6_doe_intr_support_o, + output logic mbx6_doe_async_msg_support_o, + output logic mbx_jtag_doe_intr_o, + output logic mbx_jtag_doe_intr_en_o, + output logic mbx_jtag_doe_intr_support_o, + output logic mbx_jtag_doe_async_msg_support_o, + output logic mbx_pcie0_doe_intr_o, + output logic mbx_pcie0_doe_intr_en_o, + output logic mbx_pcie0_doe_intr_support_o, + output logic mbx_pcie0_doe_async_msg_support_o, + output logic mbx_pcie1_doe_intr_o, + output logic mbx_pcie1_doe_intr_en_o, + output logic mbx_pcie1_doe_intr_support_o, + output logic mbx_pcie1_doe_async_msg_support_o, + input tlul_pkg::tl_h2d_t dbg_tl_req_i, + output tlul_pkg::tl_d2h_t dbg_tl_rsp_o, + output tlul_pkg::tl_h2d_t ast_tl_req_o, + input tlul_pkg::tl_d2h_t ast_tl_rsp_i, + output pwrmgr_pkg::pwr_ast_req_t pwrmgr_ast_req_o, + input pwrmgr_pkg::pwr_ast_rsp_t pwrmgr_ast_rsp_i, + output otp_macro_pkg::pwr_seq_t otp_macro_pwr_seq_o, + input otp_macro_pkg::pwr_seq_t otp_macro_pwr_seq_h_i, + inout otp_ext_voltage_h_io, + output logic [7:0] otp_obs_o, + input otp_macro_pkg::otp_cfg_t otp_cfg_i, + output otp_macro_pkg::otp_cfg_rsp_t otp_cfg_rsp_o, + input logic [1:0] por_n_i, + input tlul_pkg::tl_h2d_t ctn_misc_tl_h2d_i, + output tlul_pkg::tl_d2h_t ctn_misc_tl_d2h_o, + input soc_proxy_pkg::soc_alert_req_t [23:0] soc_fatal_alert_req_i, + output soc_proxy_pkg::soc_alert_rsp_t [23:0] soc_fatal_alert_rsp_o, + input soc_proxy_pkg::soc_alert_req_t [3:0] soc_recov_alert_req_i, + output soc_proxy_pkg::soc_alert_rsp_t [3:0] soc_recov_alert_rsp_o, + input logic soc_wkup_async_i, + input logic soc_rst_req_async_i, + input logic [31:0] soc_intr_async_i, + input logic [7:0] soc_lsio_trigger_i, + output logic [15:0] soc_gpi_async_o, + input logic [15:0] soc_gpo_async_i, + input logic [3:0] integrator_id_i, + output logic sck_monitor_o, + output soc_dbg_ctrl_pkg::soc_dbg_policy_t soc_dbg_policy_bus_o, + input logic debug_halt_cpu_boot_i, + output top_racl_pkg::racl_policy_vec_t racl_policies_o, + input top_racl_pkg::racl_error_log_t [RaclCtrlNumExternalSubscribingIps-1:0] racl_error_i, + input prim_mubi_pkg::mubi8_t ac_range_check_overwrite_i, + output tlul_pkg::tl_h2d_t ctn_tl_h2d_o, + input tlul_pkg::tl_d2h_t ctn_tl_d2h_i, + + + // All externally supplied clocks + input clk_main_i, + input clk_io_i, + input clk_aon_i, + + // All clocks forwarded to ast + output clkmgr_pkg::clkmgr_out_t clks_ast_o, + output rstmgr_pkg::rstmgr_out_t rsts_ast_o, + + input scan_rst_ni, // reset used for test mode + input scan_en_i, + input prim_mubi_pkg::mubi4_t scanmode_i // lc_ctrl_pkg::On for Scan +); + + import tlul_pkg::*; + import top_pkg::*; + import tl_main_pkg::*; + import top_darjeeling_no_ibex_pkg::*; + // Compile-time random constants + import top_darjeeling_no_ibex_rnd_cnst_pkg::*; + import top_darjeeling_no_ibex_racl_pkg::*; + + // Local Parameters + // local parameters for lc_ctrl + localparam int LcCtrlNumRmaAckSigs = 1; + // local parameters for spi_host0 + localparam int SpiHost0NumCS = 1; + // local parameters for sram_ctrl_ret_aon + localparam int SramCtrlRetAonOutstanding = 2; + // local parameters for entropy_src + localparam int EntropySrcEsFifoDepth = 3; + localparam int unsigned EntropySrcDistrFifoDepth = 26; + // local parameters for sram_ctrl_main + localparam int SramCtrlMainOutstanding = 2; + // local parameters for sram_ctrl_mbox + localparam int SramCtrlMboxOutstanding = 2; + // local parameters for racl_ctrl + localparam int RaclCtrlNumSubscribingIps = 11; + + // Signals + logic [3:0] mio_p2d; + logic [4:0] mio_d2p; + logic [4:0] mio_en_d2p; + logic [72:0] dio_p2d; + logic [72:0] dio_d2p; + logic [72:0] dio_en_d2p; + // uart0 + logic cio_uart0_rx_p2d; + logic cio_uart0_tx_d2p; + logic cio_uart0_tx_en_d2p; + // gpio + logic [31:0] cio_gpio_gpio_p2d; + logic [31:0] cio_gpio_gpio_d2p; + logic [31:0] cio_gpio_gpio_en_d2p; + // spi_device + logic cio_spi_device_sck_p2d; + logic cio_spi_device_csb_p2d; + logic cio_spi_device_tpm_csb_p2d; + logic [3:0] cio_spi_device_sd_p2d; + logic [3:0] cio_spi_device_sd_d2p; + logic [3:0] cio_spi_device_sd_en_d2p; + // i2c0 + logic cio_i2c0_sda_p2d; + logic cio_i2c0_scl_p2d; + logic cio_i2c0_sda_d2p; + logic cio_i2c0_sda_en_d2p; + logic cio_i2c0_scl_d2p; + logic cio_i2c0_scl_en_d2p; + // otp_ctrl + // otp_macro + logic [7:0] cio_otp_macro_test_d2p; + logic [7:0] cio_otp_macro_test_en_d2p; + // lc_ctrl + // alert_handler + // spi_host0 + logic [3:0] cio_spi_host0_sd_p2d; + logic cio_spi_host0_sck_d2p; + logic cio_spi_host0_sck_en_d2p; + logic cio_spi_host0_csb_d2p; + logic cio_spi_host0_csb_en_d2p; + logic [3:0] cio_spi_host0_sd_d2p; + logic [3:0] cio_spi_host0_sd_en_d2p; + // pwrmgr_aon + // rstmgr_aon + // clkmgr_aon + // pinmux_aon + // aon_timer_aon + // soc_proxy + logic [15:0] cio_soc_proxy_soc_gpi_p2d; + logic [15:0] cio_soc_proxy_soc_gpo_d2p; + logic [15:0] cio_soc_proxy_soc_gpo_en_d2p; + // sram_ctrl_ret_aon + // rv_plic + // aes + // hmac + // kmac + // otbn + // keymgr_dpe + // csrng + // entropy_src + // edn0 + // edn1 + // sram_ctrl_main + // sram_ctrl_mbox + // rom_ctrl0 + // rom_ctrl1 + // dma + // mbx0 + // mbx1 + // mbx2 + // mbx3 + // mbx4 + // mbx5 + // mbx6 + // mbx_jtag + // mbx_pcie0 + // mbx_pcie1 + // soc_dbg_ctrl + // racl_ctrl + // ac_range_check + + + logic [162:0] intr_vector; + // Interrupt source list + logic intr_uart0_tx_watermark; + logic intr_uart0_rx_watermark; + logic intr_uart0_tx_done; + logic intr_uart0_rx_overflow; + logic intr_uart0_rx_frame_err; + logic intr_uart0_rx_break_err; + logic intr_uart0_rx_timeout; + logic intr_uart0_rx_parity_err; + logic intr_uart0_tx_empty; + logic [31:0] intr_gpio_gpio; + logic intr_spi_device_upload_cmdfifo_not_empty; + logic intr_spi_device_upload_payload_not_empty; + logic intr_spi_device_upload_payload_overflow; + logic intr_spi_device_readbuf_watermark; + logic intr_spi_device_readbuf_flip; + logic intr_spi_device_tpm_header_not_empty; + logic intr_spi_device_tpm_rdfifo_cmd_end; + logic intr_spi_device_tpm_rdfifo_drop; + logic intr_i2c0_fmt_threshold; + logic intr_i2c0_rx_threshold; + logic intr_i2c0_acq_threshold; + logic intr_i2c0_rx_overflow; + logic intr_i2c0_controller_halt; + logic intr_i2c0_scl_interference; + logic intr_i2c0_sda_interference; + logic intr_i2c0_stretch_timeout; + logic intr_i2c0_sda_unstable; + logic intr_i2c0_cmd_complete; + logic intr_i2c0_tx_stretch; + logic intr_i2c0_tx_threshold; + logic intr_i2c0_acq_stretch; + logic intr_i2c0_unexp_stop; + logic intr_i2c0_host_timeout; + logic intr_otp_ctrl_otp_operation_done; + logic intr_otp_ctrl_otp_error; + logic intr_alert_handler_classa; + logic intr_alert_handler_classb; + logic intr_alert_handler_classc; + logic intr_alert_handler_classd; + logic intr_spi_host0_error; + logic intr_spi_host0_spi_event; + logic intr_pwrmgr_aon_wakeup; + logic intr_aon_timer_aon_wkup_timer_expired; + logic intr_aon_timer_aon_wdog_timer_bark; + logic [31:0] intr_soc_proxy_external; + logic intr_hmac_hmac_done; + logic intr_hmac_fifo_empty; + logic intr_hmac_hmac_err; + logic intr_kmac_kmac_done; + logic intr_kmac_fifo_empty; + logic intr_kmac_kmac_err; + logic intr_otbn_done; + logic intr_keymgr_dpe_op_done; + logic intr_csrng_cs_cmd_req_done; + logic intr_csrng_cs_entropy_req; + logic intr_csrng_cs_hw_inst_exc; + logic intr_csrng_cs_fatal_err; + logic intr_entropy_src_es_entropy_valid; + logic intr_entropy_src_es_health_test_failed; + logic intr_entropy_src_es_observe_fifo_ready; + logic intr_entropy_src_es_fatal_err; + logic intr_edn0_edn_cmd_req_done; + logic intr_edn0_edn_fatal_err; + logic intr_edn1_edn_cmd_req_done; + logic intr_edn1_edn_fatal_err; + logic intr_dma_dma_done; + logic intr_dma_dma_chunk_done; + logic intr_dma_dma_error; + logic intr_mbx0_mbx_ready; + logic intr_mbx0_mbx_abort; + logic intr_mbx0_mbx_error; + logic intr_mbx1_mbx_ready; + logic intr_mbx1_mbx_abort; + logic intr_mbx1_mbx_error; + logic intr_mbx2_mbx_ready; + logic intr_mbx2_mbx_abort; + logic intr_mbx2_mbx_error; + logic intr_mbx3_mbx_ready; + logic intr_mbx3_mbx_abort; + logic intr_mbx3_mbx_error; + logic intr_mbx4_mbx_ready; + logic intr_mbx4_mbx_abort; + logic intr_mbx4_mbx_error; + logic intr_mbx5_mbx_ready; + logic intr_mbx5_mbx_abort; + logic intr_mbx5_mbx_error; + logic intr_mbx6_mbx_ready; + logic intr_mbx6_mbx_abort; + logic intr_mbx6_mbx_error; + logic intr_mbx_jtag_mbx_ready; + logic intr_mbx_jtag_mbx_abort; + logic intr_mbx_jtag_mbx_error; + logic intr_mbx_pcie0_mbx_ready; + logic intr_mbx_pcie0_mbx_abort; + logic intr_mbx_pcie0_mbx_error; + logic intr_mbx_pcie1_mbx_ready; + logic intr_mbx_pcie1_mbx_abort; + logic intr_mbx_pcie1_mbx_error; + logic intr_racl_ctrl_racl_error; + logic intr_ac_range_check_deny_cnt_reached; + + // Alert list + prim_alert_pkg::alert_tx_t [alert_handler_pkg::NAlerts-1:0] alert_tx; + prim_alert_pkg::alert_rx_t [alert_handler_pkg::NAlerts-1:0] alert_rx; + + + // define inter-module signals + ast_pkg::ast_obs_ctrl_t ast_obs_ctrl; + alert_handler_pkg::alert_crashdump_t alert_handler_crashdump; + prim_esc_pkg::esc_rx_t [3:0] alert_handler_esc_rx; + prim_esc_pkg::esc_tx_t [3:0] alert_handler_esc_tx; + csrng_pkg::csrng_req_t [1:0] csrng_csrng_cmd_req; + csrng_pkg::csrng_rsp_t [1:0] csrng_csrng_cmd_rsp; + entropy_src_pkg::entropy_src_hw_if_req_t csrng_entropy_src_hw_if_req; + entropy_src_pkg::entropy_src_hw_if_rsp_t csrng_entropy_src_hw_if_rsp; + entropy_src_pkg::cs_aes_halt_req_t csrng_cs_aes_halt_req; + entropy_src_pkg::cs_aes_halt_rsp_t csrng_cs_aes_halt_rsp; + otp_ctrl_pkg::sram_otp_key_req_t [3:0] otp_ctrl_sram_otp_key_req; + otp_ctrl_pkg::sram_otp_key_rsp_t [3:0] otp_ctrl_sram_otp_key_rsp; + pwrmgr_pkg::pwr_rst_req_t pwrmgr_aon_pwr_rst_req; + pwrmgr_pkg::pwr_rst_rsp_t pwrmgr_aon_pwr_rst_rsp; + pwrmgr_pkg::pwr_clk_req_t pwrmgr_aon_pwr_clk_req; + pwrmgr_pkg::pwr_clk_rsp_t pwrmgr_aon_pwr_clk_rsp; + pwrmgr_pkg::pwr_otp_req_t pwrmgr_aon_pwr_otp_req; + pwrmgr_pkg::pwr_otp_rsp_t pwrmgr_aon_pwr_otp_rsp; + lc_ctrl_pkg::pwr_lc_req_t pwrmgr_aon_pwr_lc_req; + lc_ctrl_pkg::pwr_lc_rsp_t pwrmgr_aon_pwr_lc_rsp; + logic pwrmgr_aon_strap; + logic pwrmgr_aon_low_power; + rom_ctrl_pkg::pwrmgr_data_t [2:0] pwrmgr_aon_rom_ctrl; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_aon_boot_status; + rom_ctrl_pkg::keymgr_data_t [1:0] keymgr_dpe_rom_digest; + dma_pkg::lsio_trigger_t dma_lsio_trigger; + logic i2c0_lsio_trigger; + logic spi_host0_lsio_trigger; + logic uart0_lsio_trigger; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_flash_rma_req; + lc_ctrl_pkg::lc_tx_t otbn_lc_rma_ack; + edn_pkg::edn_req_t [7:0] edn0_edn_req; + edn_pkg::edn_rsp_t [7:0] edn0_edn_rsp; + edn_pkg::edn_req_t [7:0] edn1_edn_req; + edn_pkg::edn_rsp_t [7:0] edn1_edn_rsp; + otp_ctrl_pkg::otbn_otp_key_req_t otp_ctrl_otbn_otp_key_req; + otp_ctrl_pkg::otbn_otp_key_rsp_t otp_ctrl_otbn_otp_key_rsp; + otp_ctrl_pkg::otp_keymgr_key_t otp_ctrl_otp_keymgr_key; + keymgr_pkg::hw_key_req_t keymgr_dpe_aes_key; + keymgr_pkg::hw_key_req_t keymgr_dpe_kmac_key; + keymgr_pkg::otbn_key_req_t keymgr_dpe_otbn_key; + kmac_pkg::app_req_t [KmacNumAppIntf-1:0] kmac_app_req; + kmac_pkg::app_rsp_t [KmacNumAppIntf-1:0] kmac_app_rsp; + logic kmac_en_masking; + prim_mubi_pkg::mubi4_t [3:0] clkmgr_aon_idle; + otp_ctrl_pkg::otp_lc_data_t otp_ctrl_otp_lc_data; + otp_ctrl_pkg::lc_otp_program_req_t lc_ctrl_lc_otp_program_req; + otp_ctrl_pkg::lc_otp_program_rsp_t lc_ctrl_lc_otp_program_rsp; + otp_macro_pkg::otp_test_req_t lc_ctrl_lc_otp_vendor_test_req; + otp_macro_pkg::otp_test_rsp_t lc_ctrl_lc_otp_vendor_test_rsp; + lc_ctrl_pkg::lc_keymgr_div_t lc_ctrl_lc_keymgr_div; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_raw_test_rma; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_dft_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_hw_debug_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_keymgr_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_escalate_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_check_byp_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_req; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_clk_byp_ack; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_creator_seed_sw_rw_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_owner_seed_sw_rw_en; + lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_seed_hw_rd_en; + otp_ctrl_macro_pkg::otp_ctrl_macro_req_t otp_ctrl_otp_macro_req; + otp_ctrl_macro_pkg::otp_ctrl_macro_rsp_t otp_ctrl_otp_macro_rsp; + spi_device_pkg::passthrough_req_t spi_device_passthrough_req; + spi_device_pkg::passthrough_rsp_t spi_device_passthrough_rsp; + prim_mubi_pkg::mubi4_t rstmgr_aon_sw_rst_req; + tlul_pkg::tl_h2d_t soc_proxy_dma_tl_h2d; + tlul_pkg::tl_d2h_t soc_proxy_dma_tl_d2h; + tlul_pkg::tl_h2d_t soc_proxy_ctn_tl_h2d; + tlul_pkg::tl_d2h_t soc_proxy_ctn_tl_d2h; + logic [3:0] pwrmgr_aon_wakeups; + logic [1:0] pwrmgr_aon_rstreqs; + tlul_pkg::tl_h2d_t main_tl_peri_req; + tlul_pkg::tl_d2h_t main_tl_peri_rsp; + tlul_pkg::tl_h2d_t soc_proxy_ctn_tl_req; + tlul_pkg::tl_d2h_t soc_proxy_ctn_tl_rsp; + tlul_pkg::tl_h2d_t hmac_tl_req; + tlul_pkg::tl_d2h_t hmac_tl_rsp; + tlul_pkg::tl_h2d_t kmac_tl_req; + tlul_pkg::tl_d2h_t kmac_tl_rsp; + tlul_pkg::tl_h2d_t aes_tl_req; + tlul_pkg::tl_d2h_t aes_tl_rsp; + tlul_pkg::tl_h2d_t otbn_tl_req; + tlul_pkg::tl_d2h_t otbn_tl_rsp; + tlul_pkg::tl_h2d_t keymgr_dpe_tl_req; + tlul_pkg::tl_d2h_t keymgr_dpe_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_main_ram_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_main_ram_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_mbox_ram_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_mbox_ram_tl_rsp; + tlul_pkg::tl_h2d_t main_tl_dma__host_req; + tlul_pkg::tl_d2h_t main_tl_dma__host_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx0__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx0__sram_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx1__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx1__sram_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx2__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx2__sram_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx3__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx3__sram_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx4__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx4__sram_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx5__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx5__sram_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx6__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx6__sram_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx_jtag__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx_jtag__sram_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx_pcie0__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx_pcie0__sram_rsp; + tlul_pkg::tl_h2d_t main_tl_mbx_pcie1__sram_req; + tlul_pkg::tl_d2h_t main_tl_mbx_pcie1__sram_rsp; + tlul_pkg::tl_h2d_t uart0_tl_req; + tlul_pkg::tl_d2h_t uart0_tl_rsp; + tlul_pkg::tl_h2d_t i2c0_tl_req; + tlul_pkg::tl_d2h_t i2c0_tl_rsp; + tlul_pkg::tl_h2d_t gpio_tl_req; + tlul_pkg::tl_d2h_t gpio_tl_rsp; + tlul_pkg::tl_h2d_t spi_host0_tl_req; + tlul_pkg::tl_d2h_t spi_host0_tl_rsp; + tlul_pkg::tl_h2d_t spi_device_tl_req; + tlul_pkg::tl_d2h_t spi_device_tl_rsp; + tlul_pkg::tl_h2d_t pwrmgr_aon_tl_req; + tlul_pkg::tl_d2h_t pwrmgr_aon_tl_rsp; + tlul_pkg::tl_h2d_t rstmgr_aon_tl_req; + tlul_pkg::tl_d2h_t rstmgr_aon_tl_rsp; + tlul_pkg::tl_h2d_t clkmgr_aon_tl_req; + tlul_pkg::tl_d2h_t clkmgr_aon_tl_rsp; + tlul_pkg::tl_h2d_t pinmux_aon_tl_req; + tlul_pkg::tl_d2h_t pinmux_aon_tl_rsp; + tlul_pkg::tl_h2d_t otp_ctrl_core_tl_req; + tlul_pkg::tl_d2h_t otp_ctrl_core_tl_rsp; + tlul_pkg::tl_h2d_t otp_macro_prim_tl_req; + tlul_pkg::tl_d2h_t otp_macro_prim_tl_rsp; + tlul_pkg::tl_h2d_t lc_ctrl_regs_tl_req; + tlul_pkg::tl_d2h_t lc_ctrl_regs_tl_rsp; + tlul_pkg::tl_h2d_t alert_handler_tl_req; + tlul_pkg::tl_d2h_t alert_handler_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_ret_aon_regs_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_ret_aon_regs_tl_rsp; + tlul_pkg::tl_h2d_t sram_ctrl_ret_aon_ram_tl_req; + tlul_pkg::tl_d2h_t sram_ctrl_ret_aon_ram_tl_rsp; + tlul_pkg::tl_h2d_t aon_timer_aon_tl_req; + tlul_pkg::tl_d2h_t aon_timer_aon_tl_rsp; + tlul_pkg::tl_h2d_t soc_dbg_ctrl_core_tl_req; + tlul_pkg::tl_d2h_t soc_dbg_ctrl_core_tl_rsp; + tlul_pkg::tl_h2d_t mbx0_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx0_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx1_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx1_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx2_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx2_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx3_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx3_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx4_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx4_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx5_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx5_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx6_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx6_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx_pcie0_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx_pcie0_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t mbx_pcie1_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx_pcie1_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t racl_ctrl_tl_req; + tlul_pkg::tl_d2h_t racl_ctrl_tl_rsp; + tlul_pkg::tl_h2d_t ac_range_check_tl_req; + tlul_pkg::tl_d2h_t ac_range_check_tl_rsp; + tlul_pkg::tl_h2d_t mbx_jtag_soc_tl_d_req; + tlul_pkg::tl_d2h_t mbx_jtag_soc_tl_d_rsp; + tlul_pkg::tl_h2d_t lc_ctrl_dmi_tl_req; + tlul_pkg::tl_d2h_t lc_ctrl_dmi_tl_rsp; + tlul_pkg::tl_h2d_t soc_dbg_ctrl_jtag_tl_req; + tlul_pkg::tl_d2h_t soc_dbg_ctrl_jtag_tl_rsp; + top_racl_pkg::racl_policy_vec_t racl_ctrl_racl_policies; + top_racl_pkg::racl_error_log_t [RaclCtrlNumSubscribingIps-1:0] racl_ctrl_racl_error; + clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; + clkmgr_pkg::clkmgr_cg_en_t clkmgr_aon_cg_en; + rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets; + rstmgr_pkg::rstmgr_rst_en_t rstmgr_aon_rst_en; + otp_ctrl_part_pkg::otp_broadcast_t otp_ctrl_otp_broadcast; + prim_mubi_pkg::mubi8_t csrng_otp_en_csrng_sw_app_read; + lc_ctrl_state_pkg::soc_dbg_state_t soc_dbg_ctrl_soc_dbg_state; + otp_ctrl_pkg::otp_device_id_t lc_ctrl_otp_device_id; + otp_ctrl_pkg::otp_manuf_state_t lc_ctrl_otp_manuf_state; + otp_ctrl_pkg::otp_device_id_t keymgr_dpe_otp_device_id; + prim_mubi_pkg::mubi8_t sram_ctrl_main_otp_en_sram_ifetch; + + // define mixed connection to port + assign ast_lc_dft_en_o = lc_ctrl_lc_dft_en; + assign ast_lc_hw_debug_en_o = lc_ctrl_lc_hw_debug_en; + assign ast_obs_ctrl = obs_ctrl_i; + assign pwrmgr_boot_status_o = pwrmgr_aon_boot_status; + assign racl_policies_o = racl_ctrl_racl_policies; + + // define partial inter-module tie-off + otp_ctrl_pkg::sram_otp_key_rsp_t unused_otp_ctrl_sram_otp_key_rsp3; + edn_pkg::edn_rsp_t unused_edn0_edn_rsp6; + edn_pkg::edn_rsp_t unused_edn0_edn_rsp7; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp1; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp2; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp3; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp4; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp5; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp6; + edn_pkg::edn_rsp_t unused_edn1_edn_rsp7; + + // assign partial inter-module tie-off + assign unused_otp_ctrl_sram_otp_key_rsp3 = otp_ctrl_sram_otp_key_rsp[3]; + assign unused_edn0_edn_rsp6 = edn0_edn_rsp[6]; + assign unused_edn0_edn_rsp7 = edn0_edn_rsp[7]; + assign unused_edn1_edn_rsp1 = edn1_edn_rsp[1]; + assign unused_edn1_edn_rsp2 = edn1_edn_rsp[2]; + assign unused_edn1_edn_rsp3 = edn1_edn_rsp[3]; + assign unused_edn1_edn_rsp4 = edn1_edn_rsp[4]; + assign unused_edn1_edn_rsp5 = edn1_edn_rsp[5]; + assign unused_edn1_edn_rsp6 = edn1_edn_rsp[6]; + assign unused_edn1_edn_rsp7 = edn1_edn_rsp[7]; + assign alert_handler_esc_rx[3] = prim_esc_pkg::ESC_RX_DEFAULT; + assign otp_ctrl_sram_otp_key_req[3] = '0; + assign edn0_edn_req[6] = '0; + assign edn0_edn_req[7] = '0; + assign edn1_edn_req[1] = '0; + assign edn1_edn_req[2] = '0; + assign edn1_edn_req[3] = '0; + assign edn1_edn_req[4] = '0; + assign edn1_edn_req[5] = '0; + assign edn1_edn_req[6] = '0; + assign edn1_edn_req[7] = '0; + + + // OTP HW_CFG Broadcast signals. + // TODO(#6713): The actual struct breakout and mapping currently needs to + // be performed by hand. + assign csrng_otp_en_csrng_sw_app_read = + otp_ctrl_otp_broadcast.hw_cfg1_data.en_csrng_sw_app_read; + assign sram_ctrl_main_otp_en_sram_ifetch = + otp_ctrl_otp_broadcast.hw_cfg1_data.en_sram_ifetch; + assign lc_ctrl_otp_device_id = + otp_ctrl_otp_broadcast.hw_cfg0_data.device_id; + assign soc_dbg_ctrl_soc_dbg_state = + otp_ctrl_otp_broadcast.hw_cfg1_data.soc_dbg_state; + assign lc_ctrl_otp_manuf_state = + otp_ctrl_otp_broadcast.hw_cfg0_data.manuf_state; + assign keymgr_dpe_otp_device_id = + otp_ctrl_otp_broadcast.hw_cfg0_data.device_id; + + logic unused_otp_broadcast_bits; + assign unused_otp_broadcast_bits = ^{ + otp_ctrl_otp_broadcast.valid, + otp_ctrl_otp_broadcast.hw_cfg0_data.hw_cfg0_digest, + otp_ctrl_otp_broadcast.hw_cfg1_data.hw_cfg1_digest, + otp_ctrl_otp_broadcast.hw_cfg1_data.unallocated + }; + + // See #7978 This below is a hack. + // This is because ast is a comportable-like module that sits outside + // of top_darjeeling_no_ibex's boundary. + assign clks_ast_o = clkmgr_aon_clocks; + assign rsts_ast_o = rstmgr_aon_resets; + + + // Wire up alert handler LPGs + prim_mubi_pkg::mubi4_t [alert_handler_pkg::NLpg-1:0] lpg_cg_en; + prim_mubi_pkg::mubi4_t [alert_handler_pkg::NLpg-1:0] lpg_rst_en; + + + // peri_lc_io_div4_0 + assign lpg_cg_en[0] = clkmgr_aon_cg_en.io_div4_peri; + assign lpg_rst_en[0] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // peri_spi_device_0 + assign lpg_cg_en[1] = clkmgr_aon_cg_en.io_div4_peri; + assign lpg_rst_en[1] = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::Domain0Sel]; + // peri_i2c0_0 + assign lpg_cg_en[2] = clkmgr_aon_cg_en.io_div4_peri; + assign lpg_rst_en[2] = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::Domain0Sel]; + // secure_lc_io_div4_0 + assign lpg_cg_en[3] = clkmgr_aon_cg_en.io_div4_secure; + assign lpg_rst_en[3] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // peri_spi_host0_0 + assign lpg_cg_en[4] = clkmgr_aon_cg_en.io_div4_peri; + assign lpg_rst_en[4] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel]; + // powerup_por_io_div4_Aon + assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_powerup; + assign lpg_rst_en[5] = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::DomainAonSel]; + // powerup_lc_io_div4_Aon + assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_powerup; + assign lpg_rst_en[6] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; + // timers_lc_io_div4_Aon + assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_div4_timers; + assign lpg_rst_en[7] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; + // infra_lc_io_div4_0 + assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_div4_infra; + assign lpg_rst_en[8] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // infra_lc_0 + assign lpg_cg_en[9] = clkmgr_aon_cg_en.main_infra; + assign lpg_rst_en[9] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // infra_lc_io_div4_Aon + assign lpg_cg_en[10] = clkmgr_aon_cg_en.io_div4_infra; + assign lpg_rst_en[10] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel]; + // secure_lc_0 + assign lpg_cg_en[11] = clkmgr_aon_cg_en.main_secure; + assign lpg_rst_en[11] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // aes_trans_lc_0 + assign lpg_cg_en[12] = clkmgr_aon_cg_en.main_aes; + assign lpg_rst_en[12] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // hmac_trans_lc_0 + assign lpg_cg_en[13] = clkmgr_aon_cg_en.main_hmac; + assign lpg_rst_en[13] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // kmac_trans_lc_0 + assign lpg_cg_en[14] = clkmgr_aon_cg_en.main_kmac; + assign lpg_rst_en[14] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + // otbn_trans_lc_0 + assign lpg_cg_en[15] = clkmgr_aon_cg_en.main_otbn; + assign lpg_rst_en[15] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; + + +// tie-off unused connections +//VCS coverage off +// pragma coverage off + prim_mubi_pkg::mubi4_t unused_cg_en_0; + assign unused_cg_en_0 = clkmgr_aon_cg_en.aon_powerup; + prim_mubi_pkg::mubi4_t unused_cg_en_1; + assign unused_cg_en_1 = clkmgr_aon_cg_en.main_powerup; + prim_mubi_pkg::mubi4_t unused_cg_en_2; + assign unused_cg_en_2 = clkmgr_aon_cg_en.io_powerup; + prim_mubi_pkg::mubi4_t unused_cg_en_3; + assign unused_cg_en_3 = clkmgr_aon_cg_en.io_div2_powerup; + prim_mubi_pkg::mubi4_t unused_cg_en_4; + assign unused_cg_en_4 = clkmgr_aon_cg_en.aon_infra; + prim_mubi_pkg::mubi4_t unused_cg_en_5; + assign unused_cg_en_5 = clkmgr_aon_cg_en.aon_peri; + prim_mubi_pkg::mubi4_t unused_cg_en_6; + assign unused_cg_en_6 = clkmgr_aon_cg_en.aon_timers; + prim_mubi_pkg::mubi4_t unused_cg_en_7; + assign unused_cg_en_7 = clkmgr_aon_cg_en.io_div2_peri; + prim_mubi_pkg::mubi4_t unused_rst_en_0; + assign unused_rst_en_0 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_1; + assign unused_rst_en_1 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_2; + assign unused_rst_en_2 = rstmgr_aon_rst_en.por[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_3; + assign unused_rst_en_3 = rstmgr_aon_rst_en.por[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_4; + assign unused_rst_en_4 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_5; + assign unused_rst_en_5 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_6; + assign unused_rst_en_6 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_7; + assign unused_rst_en_7 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_8; + assign unused_rst_en_8 = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_9; + assign unused_rst_en_9 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_10; + assign unused_rst_en_10 = rstmgr_aon_rst_en.lc[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_11; + assign unused_rst_en_11 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_12; + assign unused_rst_en_12 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_13; + assign unused_rst_en_13 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_14; + assign unused_rst_en_14 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_15; + assign unused_rst_en_15 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_16; + assign unused_rst_en_16 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_17; + assign unused_rst_en_17 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_18; + assign unused_rst_en_18 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_19; + assign unused_rst_en_19 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_20; + assign unused_rst_en_20 = rstmgr_aon_rst_en.sys[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_21; + assign unused_rst_en_21 = rstmgr_aon_rst_en.sys[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_22; + assign unused_rst_en_22 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_23; + assign unused_rst_en_23 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel]; + prim_mubi_pkg::mubi4_t unused_rst_en_24; + assign unused_rst_en_24 = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_25; + assign unused_rst_en_25 = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::DomainAonSel]; + prim_mubi_pkg::mubi4_t unused_rst_en_26; + assign unused_rst_en_26 = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::DomainAonSel]; +//VCS coverage on +// pragma coverage on + + // Peripheral Instantiation + + + uart #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[0:0]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_uart0 ( + + // Input + .cio_rx_i (cio_uart0_rx_p2d), + + // Output + .cio_tx_o (cio_uart0_tx_d2p), + .cio_tx_en_o (cio_uart0_tx_en_d2p), + + // Interrupt + .intr_tx_watermark_o (intr_uart0_tx_watermark), + .intr_rx_watermark_o (intr_uart0_rx_watermark), + .intr_tx_done_o (intr_uart0_tx_done), + .intr_rx_overflow_o (intr_uart0_rx_overflow), + .intr_rx_frame_err_o (intr_uart0_rx_frame_err), + .intr_rx_break_err_o (intr_uart0_rx_break_err), + .intr_rx_timeout_o (intr_uart0_rx_timeout), + .intr_rx_parity_err_o (intr_uart0_rx_parity_err), + .intr_tx_empty_o (intr_uart0_tx_empty), + // [0]: fatal_fault + .alert_tx_o ( alert_tx[0:0] ), + .alert_rx_i ( alert_rx[0:0] ), + + // Inter-module signals + .lsio_trigger_o(uart0_lsio_trigger), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .tl_i(uart0_tl_req), + .tl_o(uart0_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + gpio #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:1]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .GpioAsyncOn(GpioGpioAsyncOn), + .GpioAsHwStrapsEn(GpioGpioAsHwStrapsEn) + ) u_gpio ( + + // Input + .cio_gpio_i (cio_gpio_gpio_p2d), + + // Output + .cio_gpio_o (cio_gpio_gpio_d2p), + .cio_gpio_en_o (cio_gpio_gpio_en_d2p), + + // Interrupt + .intr_gpio_o (intr_gpio_gpio), + // [1]: fatal_fault + .alert_tx_o ( alert_tx[1:1] ), + .alert_rx_i ( alert_rx[1:1] ), + + // Inter-module signals + .strap_en_i(pwrmgr_aon_strap), + .sampled_straps_o(), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .tl_i(gpio_tl_req), + .tl_o(gpio_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + spi_device #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[2:2]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .SramType(SpiDeviceSramType) + ) u_spi_device ( + + // Input + .cio_sck_i (cio_spi_device_sck_p2d), + .cio_csb_i (cio_spi_device_csb_p2d), + .cio_tpm_csb_i (cio_spi_device_tpm_csb_p2d), + .cio_sd_i (cio_spi_device_sd_p2d), + + // Output + .cio_sd_o (cio_spi_device_sd_d2p), + .cio_sd_en_o (cio_spi_device_sd_en_d2p), + + // Interrupt + .intr_upload_cmdfifo_not_empty_o (intr_spi_device_upload_cmdfifo_not_empty), + .intr_upload_payload_not_empty_o (intr_spi_device_upload_payload_not_empty), + .intr_upload_payload_overflow_o (intr_spi_device_upload_payload_overflow), + .intr_readbuf_watermark_o (intr_spi_device_readbuf_watermark), + .intr_readbuf_flip_o (intr_spi_device_readbuf_flip), + .intr_tpm_header_not_empty_o (intr_spi_device_tpm_header_not_empty), + .intr_tpm_rdfifo_cmd_end_o (intr_spi_device_tpm_rdfifo_cmd_end), + .intr_tpm_rdfifo_drop_o (intr_spi_device_tpm_rdfifo_drop), + // [2]: fatal_fault + .alert_tx_o ( alert_tx[2:2] ), + .alert_rx_i ( alert_rx[2:2] ), + + // Inter-module signals + .ram_cfg_sys2spi_i(spi_device_ram_2p_cfg_sys2spi_i), + .ram_cfg_rsp_sys2spi_o(spi_device_ram_2p_cfg_rsp_sys2spi_o), + .ram_cfg_spi2sys_i(spi_device_ram_2p_cfg_spi2sys_i), + .ram_cfg_rsp_spi2sys_o(spi_device_ram_2p_cfg_rsp_spi2sys_o), + .passthrough_o(spi_device_passthrough_req), + .passthrough_i(spi_device_passthrough_rsp), + .mbist_en_i('0), + .sck_monitor_o(sck_monitor_o), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .tl_i(spi_device_tl_req), + .tl_o(spi_device_tl_rsp), + .scanmode_i, + .scan_rst_ni, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .scan_clk_i (clkmgr_aon_clocks.clk_io_div2_peri), + .rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel]) + ); + i2c #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:3]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .InputDelayCycles(I2c0InputDelayCycles) + ) u_i2c0 ( + + // Input + .cio_sda_i (cio_i2c0_sda_p2d), + .cio_scl_i (cio_i2c0_scl_p2d), + + // Output + .cio_sda_o (cio_i2c0_sda_d2p), + .cio_sda_en_o (cio_i2c0_sda_en_d2p), + .cio_scl_o (cio_i2c0_scl_d2p), + .cio_scl_en_o (cio_i2c0_scl_en_d2p), + + // Interrupt + .intr_fmt_threshold_o (intr_i2c0_fmt_threshold), + .intr_rx_threshold_o (intr_i2c0_rx_threshold), + .intr_acq_threshold_o (intr_i2c0_acq_threshold), + .intr_rx_overflow_o (intr_i2c0_rx_overflow), + .intr_controller_halt_o (intr_i2c0_controller_halt), + .intr_scl_interference_o (intr_i2c0_scl_interference), + .intr_sda_interference_o (intr_i2c0_sda_interference), + .intr_stretch_timeout_o (intr_i2c0_stretch_timeout), + .intr_sda_unstable_o (intr_i2c0_sda_unstable), + .intr_cmd_complete_o (intr_i2c0_cmd_complete), + .intr_tx_stretch_o (intr_i2c0_tx_stretch), + .intr_tx_threshold_o (intr_i2c0_tx_threshold), + .intr_acq_stretch_o (intr_i2c0_acq_stretch), + .intr_unexp_stop_o (intr_i2c0_unexp_stop), + .intr_host_timeout_o (intr_i2c0_host_timeout), + // [3]: fatal_fault + .alert_tx_o ( alert_tx[3:3] ), + .alert_rx_i ( alert_rx[3:3] ), + + // Inter-module signals + .ram_cfg_i(i2c_ram_1p_cfg_i), + .ram_cfg_rsp_o(i2c_ram_1p_cfg_rsp_o), + .lsio_trigger_o(i2c0_lsio_trigger), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .tl_i(i2c0_tl_req), + .tl_o(i2c0_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel]) + ); + otp_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:4]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed), + .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm), + .RndCnstScrmblKeyInit(RndCnstOtpCtrlScrmblKeyInit) + ) u_otp_ctrl ( + + // Interrupt + .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done), + .intr_otp_error_o (intr_otp_ctrl_otp_error), + // [4]: fatal_macro_error + // [5]: fatal_check_error + // [6]: fatal_bus_integ_error + // [7]: fatal_prim_otp_alert + // [8]: recov_prim_otp_alert + .alert_tx_o ( alert_tx[8:4] ), + .alert_rx_i ( alert_rx[8:4] ), + + // Inter-module signals + .edn_o(edn0_edn_req[1]), + .edn_i(edn0_edn_rsp[1]), + .pwr_otp_i(pwrmgr_aon_pwr_otp_req), + .pwr_otp_o(pwrmgr_aon_pwr_otp_rsp), + .lc_otp_program_i(lc_ctrl_lc_otp_program_req), + .lc_otp_program_o(lc_ctrl_lc_otp_program_rsp), + .otp_lc_data_o(otp_ctrl_otp_lc_data), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en), + .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en), + .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en), + .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en), + .otp_keymgr_key_o(otp_ctrl_otp_keymgr_key), + .sram_otp_key_i(otp_ctrl_sram_otp_key_req), + .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp), + .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req), + .otbn_otp_key_o(otp_ctrl_otbn_otp_key_rsp), + .otp_broadcast_o(otp_ctrl_otp_broadcast), + .otp_macro_o(otp_ctrl_otp_macro_req), + .otp_macro_i(otp_ctrl_otp_macro_rsp), + .core_tl_i(otp_ctrl_core_tl_req), + .core_tl_o(otp_ctrl_core_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + otp_macro #( + .Width(otp_ctrl_macro_pkg::OtpWidth), + .Depth(otp_ctrl_macro_pkg::OtpDepth), + .SizeWidth(otp_ctrl_macro_pkg::OtpSizeWidth), + .MemInitFile(OtpMacroMemInitFile), + .VendorTestOffset(otp_ctrl_reg_pkg::VendorTestOffset), + .VendorTestSize(otp_ctrl_reg_pkg::VendorTestSize) + ) u_otp_macro ( + + // Output + .cio_test_o (cio_otp_macro_test_d2p), + .cio_test_en_o (cio_otp_macro_test_en_d2p), + + // Inter-module signals + .obs_ctrl_i(ast_obs_ctrl), + .otp_obs_o(otp_obs_o), + .pwr_seq_o(otp_macro_pwr_seq_o), + .pwr_seq_h_i(otp_macro_pwr_seq_h_i), + .ext_voltage_h_io(otp_ext_voltage_h_io), + .lc_dft_en_i(lc_ctrl_lc_dft_en), + .test_i(lc_ctrl_lc_otp_vendor_test_req), + .test_o(lc_ctrl_lc_otp_vendor_test_rsp), + .otp_i(otp_ctrl_otp_macro_req), + .otp_o(otp_ctrl_otp_macro_rsp), + .cfg_i(otp_cfg_i), + .cfg_rsp_o(otp_cfg_rsp_o), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .prim_tl_i(otp_macro_prim_tl_req), + .prim_tl_o(otp_macro_prim_tl_rsp), + .scanmode_i, + .scan_rst_ni, + .scan_en_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + lc_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[11:9]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .SecVolatileRawUnlockEn(SecLcCtrlVolatileRawUnlockEn), + .UseDmiInterface(LcCtrlUseDmiInterface), + .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid), + .RndCnstLcKeymgrDivTestUnlocked(RndCnstLcCtrlLcKeymgrDivTestUnlocked), + .RndCnstLcKeymgrDivDev(RndCnstLcCtrlLcKeymgrDivDev), + .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction), + .RndCnstLcKeymgrDivRma(RndCnstLcCtrlLcKeymgrDivRma), + .RndCnstInvalidTokens(RndCnstLcCtrlInvalidTokens), + .SiliconCreatorId(LcCtrlSiliconCreatorId), + .ProductId(LcCtrlProductId), + .RevisionId(LcCtrlRevisionId), + .IdcodeValue(LcCtrlIdcodeValue), + .NumRmaAckSigs(LcCtrlNumRmaAckSigs), + .EscNumSeverities(AlertHandlerEscNumSeverities), + .EscPingCountWidth(AlertHandlerEscPingCountWidth) + ) u_lc_ctrl ( + // [9]: fatal_prog_error + // [10]: fatal_state_error + // [11]: fatal_bus_integ_error + .alert_tx_o ( alert_tx[11:9] ), + .alert_rx_i ( alert_rx[11:9] ), + + // Inter-module signals + .jtag_i(jtag_pkg::JTAG_REQ_DEFAULT), + .jtag_o(), + .esc_scrap_state0_tx_i(alert_handler_esc_tx[0]), + .esc_scrap_state0_rx_o(alert_handler_esc_rx[0]), + .esc_scrap_state1_tx_i(alert_handler_esc_tx[1]), + .esc_scrap_state1_rx_o(alert_handler_esc_rx[1]), + .pwr_lc_i(pwrmgr_aon_pwr_lc_req), + .pwr_lc_o(pwrmgr_aon_pwr_lc_rsp), + .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_req), + .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_rsp), + .otp_lc_data_i(otp_ctrl_otp_lc_data), + .lc_otp_program_o(lc_ctrl_lc_otp_program_req), + .lc_otp_program_i(lc_ctrl_lc_otp_program_rsp), + .kmac_data_o(kmac_app_req[1]), + .kmac_data_i(kmac_app_rsp[1]), + .lc_raw_test_rma_o(lc_ctrl_lc_raw_test_rma), + .lc_dft_en_o(lc_ctrl_lc_dft_en), + .lc_nvm_debug_en_o(), + .lc_hw_debug_clr_o(), + .lc_hw_debug_en_o(lc_ctrl_lc_hw_debug_en), + .lc_cpu_en_o(), + .lc_keymgr_en_o(lc_ctrl_lc_keymgr_en), + .lc_escalate_en_o(lc_ctrl_lc_escalate_en), + .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_req), + .lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack), + .lc_flash_rma_req_o(lc_ctrl_lc_flash_rma_req), + .lc_flash_rma_ack_i(otbn_lc_rma_ack), + .lc_flash_rma_seed_o(), + .lc_check_byp_en_o(lc_ctrl_lc_check_byp_en), + .lc_creator_seed_sw_rw_en_o(lc_ctrl_lc_creator_seed_sw_rw_en), + .lc_owner_seed_sw_rw_en_o(lc_ctrl_lc_owner_seed_sw_rw_en), + .lc_iso_part_sw_rd_en_o(), + .lc_iso_part_sw_wr_en_o(), + .lc_seed_hw_rd_en_o(lc_ctrl_lc_seed_hw_rd_en), + .lc_keymgr_div_o(lc_ctrl_lc_keymgr_div), + .otp_device_id_i(lc_ctrl_otp_device_id), + .otp_manuf_state_i(lc_ctrl_otp_manuf_state), + .hw_rev_o(), + .strap_en_override_o(), + .regs_tl_i(lc_ctrl_regs_tl_req), + .regs_tl_o(lc_ctrl_regs_tl_rsp), + .dmi_tl_i(lc_ctrl_dmi_tl_req), + .dmi_tl_o(lc_ctrl_dmi_tl_rsp), + .scanmode_i, + .scan_rst_ni, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_kmac_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_kmac_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + alert_handler #( + .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed), + .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm), + .EscNumSeverities(AlertHandlerEscNumSeverities), + .EscPingCountWidth(AlertHandlerEscPingCountWidth) + ) u_alert_handler ( + + // Interrupt + .intr_classa_o (intr_alert_handler_classa), + .intr_classb_o (intr_alert_handler_classb), + .intr_classc_o (intr_alert_handler_classc), + .intr_classd_o (intr_alert_handler_classd), + + // Inter-module signals + .crashdump_o(alert_handler_crashdump), + .edn_o(edn0_edn_req[3]), + .edn_i(edn0_edn_rsp[3]), + .esc_rx_i(alert_handler_esc_rx), + .esc_tx_o(alert_handler_esc_tx), + .tl_i(alert_handler_tl_req), + .tl_o(alert_handler_tl_rsp), + // alert signals + .alert_rx_o ( alert_rx ), + .alert_tx_i ( alert_tx ), + // synchronized clock gated / reset asserted + // indications for each alert + .lpg_cg_en_i ( lpg_cg_en ), + .lpg_rst_en_i ( lpg_rst_en ), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + spi_host #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[12:12]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .NumCS(SpiHost0NumCS) + ) u_spi_host0 ( + + // Input + .cio_sd_i (cio_spi_host0_sd_p2d), + + // Output + .cio_sck_o (cio_spi_host0_sck_d2p), + .cio_sck_en_o (cio_spi_host0_sck_en_d2p), + .cio_csb_o (cio_spi_host0_csb_d2p), + .cio_csb_en_o (cio_spi_host0_csb_en_d2p), + .cio_sd_o (cio_spi_host0_sd_d2p), + .cio_sd_en_o (cio_spi_host0_sd_en_d2p), + + // Interrupt + .intr_error_o (intr_spi_host0_error), + .intr_spi_event_o (intr_spi_host0_spi_event), + // [12]: fatal_fault + .alert_tx_o ( alert_tx[12:12] ), + .alert_rx_i ( alert_rx[12:12] ), + + // Inter-module signals + .passthrough_i(spi_device_passthrough_req), + .passthrough_o(spi_device_passthrough_rsp), + .lsio_trigger_o(spi_host0_lsio_trigger), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .tl_i(spi_host0_tl_req), + .tl_o(spi_host0_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_peri), + .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]) + ); + pwrmgr #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[13:13]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .EscNumSeverities(AlertHandlerEscNumSeverities), + .EscPingCountWidth(AlertHandlerEscPingCountWidth) + ) u_pwrmgr_aon ( + + // Interrupt + .intr_wakeup_o (intr_pwrmgr_aon_wakeup), + // [13]: fatal_fault + .alert_tx_o ( alert_tx[13:13] ), + .alert_rx_i ( alert_rx[13:13] ), + + // Inter-module signals + .boot_status_o(pwrmgr_aon_boot_status), + .pwr_ast_o(pwrmgr_ast_req_o), + .pwr_ast_i(pwrmgr_ast_rsp_i), + .pwr_rst_o(pwrmgr_aon_pwr_rst_req), + .pwr_rst_i(pwrmgr_aon_pwr_rst_rsp), + .pwr_clk_o(pwrmgr_aon_pwr_clk_req), + .pwr_clk_i(pwrmgr_aon_pwr_clk_rsp), + .pwr_otp_o(pwrmgr_aon_pwr_otp_req), + .pwr_otp_i(pwrmgr_aon_pwr_otp_rsp), + .pwr_lc_o(pwrmgr_aon_pwr_lc_req), + .pwr_lc_i(pwrmgr_aon_pwr_lc_rsp), + .pwr_flash_i(pwrmgr_pkg::PWR_FLASH_DEFAULT), + .esc_rst_tx_i(alert_handler_esc_tx[2]), + .esc_rst_rx_o(alert_handler_esc_rx[2]), + .pwr_cpu_i(rv_core_ibex_pkg::CPU_PWRMGR_DEFAULT), + .wakeups_i(pwrmgr_aon_wakeups), + .rstreqs_i(pwrmgr_aon_rstreqs), + .ndmreset_req_i('0), + .strap_o(pwrmgr_aon_strap), + .low_power_o(pwrmgr_aon_low_power), + .rom_ctrl_i(pwrmgr_aon_rom_ctrl), + .fetch_en_o(), + .lc_dft_en_i(lc_ctrl_lc_dft_en), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .sw_rst_req_i(rstmgr_aon_sw_rst_req), + .tl_i(pwrmgr_aon_tl_req), + .tl_o(pwrmgr_aon_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_slow_i (clkmgr_aon_clocks.clk_aon_powerup), + .clk_lc_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure), + .rst_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_main_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::Domain0Sel]), + .rst_lc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_slow_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel]) + ); + rstmgr #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[15:14]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .SecCheck(SecRstmgrAonCheck), + .SecMaxSyncDelay(SecRstmgrAonMaxSyncDelay) + ) u_rstmgr_aon ( + // [14]: fatal_fault + // [15]: fatal_cnsty_fault + .alert_tx_o ( alert_tx[15:14] ), + .alert_rx_i ( alert_rx[15:14] ), + + // Inter-module signals + .por_n_i(por_n_i), + .pwr_i(pwrmgr_aon_pwr_rst_req), + .pwr_o(pwrmgr_aon_pwr_rst_rsp), + .resets_o(rstmgr_aon_resets), + .rst_en_o(rstmgr_aon_rst_en), + .alert_dump_i(alert_handler_crashdump), + .cpu_dump_i(rv_core_ibex_pkg::CPU_CRASH_DUMP_DEFAULT), + .sw_rst_req_o(rstmgr_aon_sw_rst_req), + .tl_i(rstmgr_aon_tl_req), + .tl_o(rstmgr_aon_tl_rsp), + .scanmode_i, + .scan_rst_ni, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_por_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup), + .clk_main_i (clkmgr_aon_clocks.clk_main_powerup), + .clk_io_i (clkmgr_aon_clocks.clk_io_powerup), + .clk_io_div2_i (clkmgr_aon_clocks.clk_io_div2_powerup), + .clk_io_div4_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]) + ); + clkmgr #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[17:16]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_clkmgr_aon ( + // [16]: recov_fault + // [17]: fatal_fault + .alert_tx_o ( alert_tx[17:16] ), + .alert_rx_i ( alert_rx[17:16] ), + + // Inter-module signals + .clocks_o(clkmgr_aon_clocks), + .cg_en_o(clkmgr_aon_cg_en), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .io_clk_byp_req_o(io_clk_byp_req_o), + .io_clk_byp_ack_i(io_clk_byp_ack_i), + .all_clk_byp_req_o(all_clk_byp_req_o), + .all_clk_byp_ack_i(all_clk_byp_ack_i), + .hi_speed_sel_o(hi_speed_sel_o), + .div_step_down_req_i(div_step_down_req_i), + .lc_clk_byp_req_i(lc_ctrl_lc_clk_byp_req), + .lc_clk_byp_ack_o(lc_ctrl_lc_clk_byp_ack), + .jitter_en_o(clk_main_jitter_en_o), + .pwr_i(pwrmgr_aon_pwr_clk_req), + .pwr_o(pwrmgr_aon_pwr_clk_rsp), + .idle_i(clkmgr_aon_idle), + .calib_rdy_i(calib_rdy_i), + .tl_i(clkmgr_aon_tl_req), + .tl_o(clkmgr_aon_tl_rsp), + .scanmode_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_main_i (clk_main_i), + .clk_io_i (clk_io_i), + .clk_aon_i (clk_aon_i), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::DomainAonSel]), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), + .rst_io_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::DomainAonSel]), + .rst_io_div2_ni (rstmgr_aon_resets.rst_lc_io_div2_n[rstmgr_pkg::DomainAonSel]), + .rst_io_div4_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::DomainAonSel]), + .rst_root_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_root_io_ni (rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]), + .rst_root_io_div2_ni (rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]), + .rst_root_io_div4_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_root_main_ni (rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]) + ); + pinmux #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:18]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .TargetCfg(PinmuxAonTargetCfg) + ) u_pinmux_aon ( + // [18]: fatal_fault + .alert_tx_o ( alert_tx[18:18] ), + .alert_rx_i ( alert_rx[18:18] ), + + // Inter-module signals + .sleep_en_i(pwrmgr_aon_low_power), + .pin_wkup_req_o(pwrmgr_aon_wakeups[0]), + .tl_i(pinmux_aon_tl_req), + .tl_o(pinmux_aon_tl_rsp), + + .periph_to_mio_i (mio_d2p ), + .periph_to_mio_oe_i (mio_en_d2p ), + .mio_to_periph_o (mio_p2d ), + + .mio_attr_o, + .mio_out_o, + .mio_oe_o, + .mio_in_i, + + .periph_to_dio_i (dio_d2p ), + .periph_to_dio_oe_i (dio_en_d2p ), + .dio_to_periph_o (dio_p2d ), + + .dio_attr_o, + .dio_out_o, + .dio_oe_o, + .dio_in_i, + + .scanmode_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup), + .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]), + .rst_sys_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]) + ); + aon_timer #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_aon_timer_aon ( + + // Interrupt + .intr_wkup_timer_expired_o (intr_aon_timer_aon_wkup_timer_expired), + .intr_wdog_timer_bark_o (intr_aon_timer_aon_wdog_timer_bark), + // [19]: fatal_fault + .alert_tx_o ( alert_tx[19:19] ), + .alert_rx_i ( alert_rx[19:19] ), + + // Inter-module signals + .nmi_wdog_timer_bark_o(), + .wkup_req_o(pwrmgr_aon_wakeups[1]), + .aon_timer_rst_req_o(pwrmgr_aon_rstreqs[0]), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .sleep_mode_i(pwrmgr_aon_low_power), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .tl_i(aon_timer_aon_tl_req), + .tl_o(aon_timer_aon_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_timers), + .clk_aon_i (clkmgr_aon_clocks.clk_aon_timers), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]) + ); + soc_proxy #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:20]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_soc_proxy ( + + // Input + .cio_soc_gpi_i (cio_soc_proxy_soc_gpi_p2d), + + // Output + .cio_soc_gpo_o (cio_soc_proxy_soc_gpo_d2p), + .cio_soc_gpo_en_o (cio_soc_proxy_soc_gpo_en_d2p), + + // Interrupt + .intr_external_o (intr_soc_proxy_external), + // [20]: fatal_alert_intg + // [21]: fatal_alert_external_0 + // [22]: fatal_alert_external_1 + // [23]: fatal_alert_external_2 + // [24]: fatal_alert_external_3 + // [25]: fatal_alert_external_4 + // [26]: fatal_alert_external_5 + // [27]: fatal_alert_external_6 + // [28]: fatal_alert_external_7 + // [29]: fatal_alert_external_8 + // [30]: fatal_alert_external_9 + // [31]: fatal_alert_external_10 + // [32]: fatal_alert_external_11 + // [33]: fatal_alert_external_12 + // [34]: fatal_alert_external_13 + // [35]: fatal_alert_external_14 + // [36]: fatal_alert_external_15 + // [37]: fatal_alert_external_16 + // [38]: fatal_alert_external_17 + // [39]: fatal_alert_external_18 + // [40]: fatal_alert_external_19 + // [41]: fatal_alert_external_20 + // [42]: fatal_alert_external_21 + // [43]: fatal_alert_external_22 + // [44]: fatal_alert_external_23 + // [45]: recov_alert_external_0 + // [46]: recov_alert_external_1 + // [47]: recov_alert_external_2 + // [48]: recov_alert_external_3 + .alert_tx_o ( alert_tx[48:20] ), + .alert_rx_i ( alert_rx[48:20] ), + + // Inter-module signals + .dma_tl_h2d_i(soc_proxy_dma_tl_h2d), + .dma_tl_d2h_o(soc_proxy_dma_tl_d2h), + .misc_tl_h2d_i(ctn_misc_tl_h2d_i), + .misc_tl_d2h_o(ctn_misc_tl_d2h_o), + .wkup_internal_req_o(pwrmgr_aon_wakeups[2]), + .wkup_external_req_o(pwrmgr_aon_wakeups[3]), + .rst_req_external_o(pwrmgr_aon_rstreqs[1]), + .ctn_tl_h2d_o(soc_proxy_ctn_tl_h2d), + .ctn_tl_d2h_i(soc_proxy_ctn_tl_d2h), + .i2c_lsio_trigger_i(i2c0_lsio_trigger), + .spi_host_lsio_trigger_i(spi_host0_lsio_trigger), + .uart_lsio_trigger_i(uart0_lsio_trigger), + .soc_lsio_trigger_i(soc_lsio_trigger_i), + .dma_lsio_trigger_o(dma_lsio_trigger), + .soc_fatal_alert_i(soc_fatal_alert_req_i), + .soc_fatal_alert_o(soc_fatal_alert_rsp_o), + .soc_recov_alert_i(soc_recov_alert_req_i), + .soc_recov_alert_o(soc_recov_alert_rsp_o), + .soc_wkup_async_i(soc_wkup_async_i), + .soc_rst_req_async_i(soc_rst_req_async_i), + .soc_intr_async_i(soc_intr_async_i), + .soc_gpi_async_o(soc_gpi_async_o), + .soc_gpo_async_i(soc_gpo_async_i), + .integrator_id_i(integrator_id_i), + .core_tl_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_o(), + .ctn_tl_i(soc_proxy_ctn_tl_req), + .ctn_tl_o(soc_proxy_ctn_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .clk_aon_i (clkmgr_aon_clocks.clk_aon_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]) + ); + sram_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[49:49]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey), + .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce), + .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed), + .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm), + .MemSizeRam(4096), + .InstSize(SramCtrlRetAonInstSize), + .NumRamInst(SramCtrlRetAonNumRamInst), + .InstrExec(SramCtrlRetAonInstrExec), + .NumPrinceRoundsHalf(SramCtrlRetAonNumPrinceRoundsHalf), + .Outstanding(SramCtrlRetAonOutstanding), + .EccCorrection(SramCtrlRetAonEccCorrection) + ) u_sram_ctrl_ret_aon ( + // [49]: fatal_error + .alert_tx_o ( alert_tx[49:49] ), + .alert_rx_i ( alert_rx[49:49] ), + .racl_policy_sel_ranges_ram_i('{top_racl_pkg::RACL_RANGE_T_DEFAULT}), + + // Inter-module signals + .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]), + .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[1]), + .cfg_i(sram_ctrl_ret_aon_ram_1p_cfg_i), + .cfg_rsp_o(sram_ctrl_ret_aon_ram_1p_cfg_rsp_o), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_hw_debug_en_i(lc_ctrl_pkg::Off), + .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .sram_rerror_o(), + .regs_tl_i(sram_ctrl_ret_aon_regs_tl_req), + .regs_tl_o(sram_ctrl_ret_aon_regs_tl_rsp), + .ram_tl_i(sram_ctrl_ret_aon_ram_tl_req), + .ram_tl_o(sram_ctrl_ret_aon_ram_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_infra), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]) + ); + rv_plic #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:50]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_rv_plic ( + // [50]: fatal_fault + .alert_tx_o ( alert_tx[50:50] ), + .alert_rx_i ( alert_rx[50:50] ), + + // Inter-module signals + .irq_o(no_ibex_irq_o), + .irq_id_o(), + .msip_o(no_ibex_msip_o), + .tl_i(tlul_pkg::TL_H2D_DEFAULT), + .tl_o(), + .intr_src_i (intr_vector), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + aes #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .AES192Enable(1'b1), + .SecMasking(SecAesMasking), + .SecSBoxImpl(SecAesSBoxImpl), + .SecStartTriggerDelay(SecAesStartTriggerDelay), + .SecAllowForcingMasks(SecAesAllowForcingMasks), + .SecSkipPRNGReseeding(SecAesSkipPRNGReseeding), + .RndCnstClearingLfsrSeed(RndCnstAesClearingLfsrSeed), + .RndCnstClearingLfsrPerm(RndCnstAesClearingLfsrPerm), + .RndCnstClearingSharePerm(RndCnstAesClearingSharePerm), + .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed), + .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm) + ) u_aes ( + // [51]: recov_ctrl_update_err + // [52]: fatal_fault + .alert_tx_o ( alert_tx[52:51] ), + .alert_rx_i ( alert_rx[52:51] ), + + // Inter-module signals + .idle_o(clkmgr_aon_idle[0]), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .edn_o(edn0_edn_req[4]), + .edn_i(edn0_edn_rsp[4]), + .keymgr_key_i(keymgr_dpe_aes_key), + .tl_i(aes_tl_req), + .tl_o(aes_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_aes), + .clk_edn_i (clkmgr_aon_clocks.clk_main_aes), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + hmac #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[53:53]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_hmac ( + + // Interrupt + .intr_hmac_done_o (intr_hmac_hmac_done), + .intr_fifo_empty_o (intr_hmac_fifo_empty), + .intr_hmac_err_o (intr_hmac_hmac_err), + // [53]: fatal_fault + .alert_tx_o ( alert_tx[53:53] ), + .alert_rx_i ( alert_rx[53:53] ), + + // Inter-module signals + .idle_o(clkmgr_aon_idle[1]), + .tl_i(hmac_tl_req), + .tl_o(hmac_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_hmac), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + kmac #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[55:54]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .EnMasking(KmacEnMasking), + .SwKeyMasked(KmacSwKeyMasked), + .SecCmdDelay(SecKmacCmdDelay), + .SecIdleAcceptSwMsg(SecKmacIdleAcceptSwMsg), + .NumAppIntf(KmacNumAppIntf), + .AppCfg(KmacAppCfg), + .RndCnstLfsrSeed(RndCnstKmacLfsrSeed), + .RndCnstLfsrPerm(RndCnstKmacLfsrPerm), + .RndCnstBufferLfsrSeed(RndCnstKmacBufferLfsrSeed), + .RndCnstMsgPerm(RndCnstKmacMsgPerm) + ) u_kmac ( + + // Interrupt + .intr_kmac_done_o (intr_kmac_kmac_done), + .intr_fifo_empty_o (intr_kmac_fifo_empty), + .intr_kmac_err_o (intr_kmac_kmac_err), + // [54]: recov_operation_err + // [55]: fatal_fault_err + .alert_tx_o ( alert_tx[55:54] ), + .alert_rx_i ( alert_rx[55:54] ), + + // Inter-module signals + .keymgr_key_i(keymgr_dpe_kmac_key), + .app_i(kmac_app_req), + .app_o(kmac_app_rsp), + .entropy_o(edn0_edn_req[2]), + .entropy_i(edn0_edn_rsp[2]), + .idle_o(clkmgr_aon_idle[2]), + .en_masking_o(kmac_en_masking), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .tl_i(kmac_tl_req), + .tl_o(kmac_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_kmac), + .clk_edn_i (clkmgr_aon_clocks.clk_main_kmac), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + otbn #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[57:56]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .Stub(OtbnStub), + .RegFile(OtbnRegFile), + .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed), + .SecMuteUrnd(SecOtbnMuteUrnd), + .SecSkipUrndReseedAtStart(SecOtbnSkipUrndReseedAtStart), + .RndCnstOtbnKey(RndCnstOtbnOtbnKey), + .RndCnstOtbnNonce(RndCnstOtbnOtbnNonce) + ) u_otbn ( + + // Interrupt + .intr_done_o (intr_otbn_done), + // [56]: fatal + // [57]: recov + .alert_tx_o ( alert_tx[57:56] ), + .alert_rx_i ( alert_rx[57:56] ), + + // Inter-module signals + .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req), + .otbn_otp_key_i(otp_ctrl_otbn_otp_key_rsp), + .edn_rnd_o(edn1_edn_req[0]), + .edn_rnd_i(edn1_edn_rsp[0]), + .edn_urnd_o(edn0_edn_req[5]), + .edn_urnd_i(edn0_edn_rsp[5]), + .idle_o(clkmgr_aon_idle[3]), + .ram_cfg_imem_i(otbn_imem_ram_1p_cfg_i), + .ram_cfg_dmem_i(otbn_dmem_ram_1p_cfg_i), + .ram_cfg_rsp_imem_o(otbn_imem_ram_1p_cfg_rsp_o), + .ram_cfg_rsp_dmem_o(otbn_dmem_ram_1p_cfg_rsp_o), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_rma_req_i(lc_ctrl_lc_flash_rma_req), + .lc_rma_ack_o(otbn_lc_rma_ack), + .keymgr_key_i(keymgr_dpe_otbn_key), + .tl_i(otbn_tl_req), + .tl_o(otbn_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_otbn), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + keymgr_dpe #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:58]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .KmacEnMasking(KeymgrDpeKmacEnMasking), + .RndCnstLfsrSeed(RndCnstKeymgrDpeLfsrSeed), + .RndCnstLfsrPerm(RndCnstKeymgrDpeLfsrPerm), + .RndCnstRandPerm(RndCnstKeymgrDpeRandPerm), + .RndCnstRevisionSeed(RndCnstKeymgrDpeRevisionSeed), + .RndCnstSoftOutputSeed(RndCnstKeymgrDpeSoftOutputSeed), + .RndCnstHardOutputSeed(RndCnstKeymgrDpeHardOutputSeed), + .RndCnstAesSeed(RndCnstKeymgrDpeAesSeed), + .RndCnstKmacSeed(RndCnstKeymgrDpeKmacSeed), + .RndCnstOtbnSeed(RndCnstKeymgrDpeOtbnSeed), + .RndCnstNoneSeed(RndCnstKeymgrDpeNoneSeed) + ) u_keymgr_dpe ( + + // Interrupt + .intr_op_done_o (intr_keymgr_dpe_op_done), + // [58]: recov_operation_err + // [59]: fatal_fault_err + .alert_tx_o ( alert_tx[59:58] ), + .alert_rx_i ( alert_rx[59:58] ), + + // Inter-module signals + .edn_o(edn0_edn_req[0]), + .edn_i(edn0_edn_rsp[0]), + .aes_key_o(keymgr_dpe_aes_key), + .kmac_key_o(keymgr_dpe_kmac_key), + .otbn_key_o(keymgr_dpe_otbn_key), + .kmac_data_o(kmac_app_req[0]), + .kmac_data_i(kmac_app_rsp[0]), + .otp_key_i(otp_ctrl_otp_keymgr_key), + .otp_device_id_i(keymgr_dpe_otp_device_id), + .lc_keymgr_en_i(lc_ctrl_lc_keymgr_en), + .lc_keymgr_div_i(lc_ctrl_lc_keymgr_div), + .rom_digest_i(keymgr_dpe_rom_digest), + .kmac_en_masking_i(kmac_en_masking), + .tl_i(keymgr_dpe_tl_req), + .tl_o(keymgr_dpe_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .clk_edn_i (clkmgr_aon_clocks.clk_main_secure), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + csrng #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[61:60]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction), + .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction), + .SBoxImpl(CsrngSBoxImpl) + ) u_csrng ( + + // Interrupt + .intr_cs_cmd_req_done_o (intr_csrng_cs_cmd_req_done), + .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req), + .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc), + .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err), + // [60]: recov_alert + // [61]: fatal_alert + .alert_tx_o ( alert_tx[61:60] ), + .alert_rx_i ( alert_rx[61:60] ), + + // Inter-module signals + .csrng_cmd_i(csrng_csrng_cmd_req), + .csrng_cmd_o(csrng_csrng_cmd_rsp), + .entropy_src_hw_if_o(csrng_entropy_src_hw_if_req), + .entropy_src_hw_if_i(csrng_entropy_src_hw_if_rsp), + .cs_aes_halt_i(csrng_cs_aes_halt_req), + .cs_aes_halt_o(csrng_cs_aes_halt_rsp), + .otp_en_csrng_sw_app_read_i(csrng_otp_en_csrng_sw_app_read), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .tl_i(tlul_pkg::TL_H2D_DEFAULT), + .tl_o(), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + entropy_src #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[63:62]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .RngBusWidth(EntropySrcRngBusWidth), + .RngBusBitSelWidth(EntropySrcRngBusBitSelWidth), + .HealthTestWindowWidth(EntropySrcHealthTestWindowWidth), + .EsFifoDepth(EntropySrcEsFifoDepth), + .DistrFifoDepth(EntropySrcDistrFifoDepth), + .Stub(EntropySrcStub) + ) u_entropy_src ( + + // Interrupt + .intr_es_entropy_valid_o (intr_entropy_src_es_entropy_valid), + .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed), + .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready), + .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err), + // [62]: recov_alert + // [63]: fatal_alert + .alert_tx_o ( alert_tx[63:62] ), + .alert_rx_i ( alert_rx[63:62] ), + + // Inter-module signals + .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req), + .entropy_src_hw_if_o(csrng_entropy_src_hw_if_rsp), + .cs_aes_halt_o(csrng_cs_aes_halt_req), + .cs_aes_halt_i(csrng_cs_aes_halt_rsp), + .entropy_src_rng_enable_o(es_rng_enable_o), + .entropy_src_rng_valid_i(es_rng_valid_i), + .entropy_src_rng_bits_i(es_rng_bit_i), + .entropy_src_xht_valid_o(), + .entropy_src_xht_bits_o(), + .entropy_src_xht_bit_sel_o(), + .entropy_src_xht_health_test_window_o(), + .entropy_src_xht_meta_o(), + .entropy_src_xht_meta_i(entropy_src_pkg::ENTROPY_SRC_XHT_META_RSP_DEFAULT), + .otp_en_entropy_src_fw_read_i(prim_mubi_pkg::MuBi8True), + .otp_en_entropy_src_fw_over_i(prim_mubi_pkg::MuBi8True), + .rng_fips_o(es_rng_fips_o), + .tl_i(tlul_pkg::TL_H2D_DEFAULT), + .tl_o(), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + edn #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[65:64]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_edn0 ( + + // Interrupt + .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done), + .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err), + // [64]: recov_alert + // [65]: fatal_alert + .alert_tx_o ( alert_tx[65:64] ), + .alert_rx_i ( alert_rx[65:64] ), + + // Inter-module signals + .csrng_cmd_o(csrng_csrng_cmd_req[0]), + .csrng_cmd_i(csrng_csrng_cmd_rsp[0]), + .edn_i(edn0_edn_req), + .edn_o(edn0_edn_rsp), + .tl_i(tlul_pkg::TL_H2D_DEFAULT), + .tl_o(), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + edn #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[67:66]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_edn1 ( + + // Interrupt + .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done), + .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err), + // [66]: recov_alert + // [67]: fatal_alert + .alert_tx_o ( alert_tx[67:66] ), + .alert_rx_i ( alert_rx[67:66] ), + + // Inter-module signals + .csrng_cmd_o(csrng_csrng_cmd_req[1]), + .csrng_cmd_i(csrng_csrng_cmd_rsp[1]), + .edn_i(edn1_edn_req), + .edn_o(edn1_edn_rsp), + .tl_i(tlul_pkg::TL_H2D_DEFAULT), + .tl_o(), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + sram_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[68:68]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .RndCnstSramKey(RndCnstSramCtrlMainSramKey), + .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce), + .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed), + .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm), + .MemSizeRam(65536), + .InstSize(SramCtrlMainInstSize), + .NumRamInst(SramCtrlMainNumRamInst), + .InstrExec(SramCtrlMainInstrExec), + .NumPrinceRoundsHalf(SramCtrlMainNumPrinceRoundsHalf), + .Outstanding(SramCtrlMainOutstanding), + .EccCorrection(SramCtrlMainEccCorrection) + ) u_sram_ctrl_main ( + // [68]: fatal_error + .alert_tx_o ( alert_tx[68:68] ), + .alert_rx_i ( alert_rx[68:68] ), + .racl_policy_sel_ranges_ram_i('{top_racl_pkg::RACL_RANGE_T_DEFAULT}), + + // Inter-module signals + .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]), + .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[0]), + .cfg_i(sram_ctrl_main_ram_1p_cfg_i), + .cfg_rsp_o(sram_ctrl_main_ram_1p_cfg_rsp_o), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .otp_en_sram_ifetch_i(sram_ctrl_main_otp_en_sram_ifetch), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .sram_rerror_o(), + .regs_tl_i(tlul_pkg::TL_H2D_DEFAULT), + .regs_tl_o(), + .ram_tl_i(sram_ctrl_main_ram_tl_req), + .ram_tl_o(sram_ctrl_main_ram_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + sram_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[69:69]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .RndCnstSramKey(RndCnstSramCtrlMboxSramKey), + .RndCnstSramNonce(RndCnstSramCtrlMboxSramNonce), + .RndCnstLfsrSeed(RndCnstSramCtrlMboxLfsrSeed), + .RndCnstLfsrPerm(RndCnstSramCtrlMboxLfsrPerm), + .MemSizeRam(4096), + .InstSize(SramCtrlMboxInstSize), + .NumRamInst(SramCtrlMboxNumRamInst), + .InstrExec(SramCtrlMboxInstrExec), + .NumPrinceRoundsHalf(SramCtrlMboxNumPrinceRoundsHalf), + .Outstanding(SramCtrlMboxOutstanding), + .EccCorrection(SramCtrlMboxEccCorrection) + ) u_sram_ctrl_mbox ( + // [69]: fatal_error + .alert_tx_o ( alert_tx[69:69] ), + .alert_rx_i ( alert_rx[69:69] ), + .racl_policy_sel_ranges_ram_i('{top_racl_pkg::RACL_RANGE_T_DEFAULT}), + + // Inter-module signals + .sram_otp_key_o(otp_ctrl_sram_otp_key_req[2]), + .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[2]), + .cfg_i(sram_ctrl_mbox_ram_1p_cfg_i), + .cfg_rsp_o(sram_ctrl_mbox_ram_1p_cfg_rsp_o), + .lc_escalate_en_i(lc_ctrl_lc_escalate_en), + .lc_hw_debug_en_i(lc_ctrl_pkg::Off), + .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .sram_rerror_o(), + .regs_tl_i(tlul_pkg::TL_H2D_DEFAULT), + .regs_tl_o(), + .ram_tl_i(sram_ctrl_mbox_ram_tl_req), + .ram_tl_o(sram_ctrl_mbox_ram_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + rom_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[70:70]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .BootRomInitFile(RomCtrl0BootRomInitFile), + .RndCnstScrNonce(RndCnstRomCtrl0ScrNonce), + .RndCnstScrKey(RndCnstRomCtrl0ScrKey), + .SecDisableScrambling(SecRomCtrl0DisableScrambling), + .MemSizeRom(32768) + ) u_rom_ctrl0 ( + // [70]: fatal + .alert_tx_o ( alert_tx[70:70] ), + .alert_rx_i ( alert_rx[70:70] ), + + // Inter-module signals + .rom_cfg_i(rom_ctrl0_cfg_i), + .pwrmgr_data_o(pwrmgr_aon_rom_ctrl[0]), + .keymgr_data_o(keymgr_dpe_rom_digest[0]), + .kmac_data_o(kmac_app_req[2]), + .kmac_data_i(kmac_app_rsp[2]), + .regs_tl_i(tlul_pkg::TL_H2D_DEFAULT), + .regs_tl_o(), + .rom_tl_i(tlul_pkg::TL_H2D_DEFAULT), + .rom_tl_o(), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + rom_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[71:71]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .BootRomInitFile(RomCtrl1BootRomInitFile), + .RndCnstScrNonce(RndCnstRomCtrl1ScrNonce), + .RndCnstScrKey(RndCnstRomCtrl1ScrKey), + .SecDisableScrambling(SecRomCtrl1DisableScrambling), + .MemSizeRom(65536) + ) u_rom_ctrl1 ( + // [71]: fatal + .alert_tx_o ( alert_tx[71:71] ), + .alert_rx_i ( alert_rx[71:71] ), + + // Inter-module signals + .rom_cfg_i(rom_ctrl1_cfg_i), + .pwrmgr_data_o(pwrmgr_aon_rom_ctrl[1]), + .keymgr_data_o(keymgr_dpe_rom_digest[1]), + .kmac_data_o(kmac_app_req[3]), + .kmac_data_i(kmac_app_rsp[3]), + .regs_tl_i(tlul_pkg::TL_H2D_DEFAULT), + .regs_tl_o(), + .rom_tl_i(tlul_pkg::TL_H2D_DEFAULT), + .rom_tl_o(), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + dma #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[72:72]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .EnableDataIntgGen(DmaEnableDataIntgGen), + .EnableRspDataIntgCheck(DmaEnableRspDataIntgCheck), + .TlUserRsvd(DmaTlUserRsvd), + .SysRacl(DmaSysRacl), + .OtAgentId(DmaOtAgentId) + ) u_dma ( + + // Interrupt + .intr_dma_done_o (intr_dma_dma_done), + .intr_dma_chunk_done_o (intr_dma_dma_chunk_done), + .intr_dma_error_o (intr_dma_dma_error), + // [72]: fatal_fault + .alert_tx_o ( alert_tx[72:72] ), + .alert_rx_i ( alert_rx[72:72] ), + + // Inter-module signals + .lsio_trigger_i(dma_lsio_trigger), + .sys_o(dma_sys_req_o), + .sys_i(dma_sys_rsp_i), + .ctn_tl_h2d_o(soc_proxy_dma_tl_h2d), + .ctn_tl_d2h_i(soc_proxy_dma_tl_d2h), + .racl_policies_i(top_racl_pkg::RACL_POLICY_VEC_DEFAULT), + .racl_error_o(), + .host_tl_h_o(main_tl_dma__host_req), + .host_tl_h_i(main_tl_dma__host_rsp), + .tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .tl_d_o(), + .scanmode_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX0_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX0_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX0_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[74:73]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx0 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx0_mbx_ready), + .intr_mbx_abort_o (intr_mbx0_mbx_abort), + .intr_mbx_error_o (intr_mbx0_mbx_error), + // [73]: fatal_fault + // [74]: recov_fault + .alert_tx_o ( alert_tx[74:73] ), + .alert_rx_i ( alert_rx[74:73] ), + + // Inter-module signals + .doe_intr_support_o(mbx0_doe_intr_support_o), + .doe_intr_en_o(mbx0_doe_intr_en_o), + .doe_intr_o(mbx0_doe_intr_o), + .doe_async_msg_support_o(mbx0_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[0]), + .sram_tl_h_o(main_tl_mbx0__sram_req), + .sram_tl_h_i(main_tl_mbx0__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx0_soc_tl_d_req), + .soc_tl_d_o(mbx0_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX1_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX1_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX1_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[76:75]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx1 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx1_mbx_ready), + .intr_mbx_abort_o (intr_mbx1_mbx_abort), + .intr_mbx_error_o (intr_mbx1_mbx_error), + // [75]: fatal_fault + // [76]: recov_fault + .alert_tx_o ( alert_tx[76:75] ), + .alert_rx_i ( alert_rx[76:75] ), + + // Inter-module signals + .doe_intr_support_o(mbx1_doe_intr_support_o), + .doe_intr_en_o(mbx1_doe_intr_en_o), + .doe_intr_o(mbx1_doe_intr_o), + .doe_async_msg_support_o(mbx1_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[1]), + .sram_tl_h_o(main_tl_mbx1__sram_req), + .sram_tl_h_i(main_tl_mbx1__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx1_soc_tl_d_req), + .soc_tl_d_o(mbx1_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX2_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX2_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX2_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[78:77]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx2 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx2_mbx_ready), + .intr_mbx_abort_o (intr_mbx2_mbx_abort), + .intr_mbx_error_o (intr_mbx2_mbx_error), + // [77]: fatal_fault + // [78]: recov_fault + .alert_tx_o ( alert_tx[78:77] ), + .alert_rx_i ( alert_rx[78:77] ), + + // Inter-module signals + .doe_intr_support_o(mbx2_doe_intr_support_o), + .doe_intr_en_o(mbx2_doe_intr_en_o), + .doe_intr_o(mbx2_doe_intr_o), + .doe_async_msg_support_o(mbx2_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[2]), + .sram_tl_h_o(main_tl_mbx2__sram_req), + .sram_tl_h_i(main_tl_mbx2__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx2_soc_tl_d_req), + .soc_tl_d_o(mbx2_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX3_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX3_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX3_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[80:79]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx3 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx3_mbx_ready), + .intr_mbx_abort_o (intr_mbx3_mbx_abort), + .intr_mbx_error_o (intr_mbx3_mbx_error), + // [79]: fatal_fault + // [80]: recov_fault + .alert_tx_o ( alert_tx[80:79] ), + .alert_rx_i ( alert_rx[80:79] ), + + // Inter-module signals + .doe_intr_support_o(mbx3_doe_intr_support_o), + .doe_intr_en_o(mbx3_doe_intr_en_o), + .doe_intr_o(mbx3_doe_intr_o), + .doe_async_msg_support_o(mbx3_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[3]), + .sram_tl_h_o(main_tl_mbx3__sram_req), + .sram_tl_h_i(main_tl_mbx3__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx3_soc_tl_d_req), + .soc_tl_d_o(mbx3_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX4_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX4_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX4_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[82:81]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx4 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx4_mbx_ready), + .intr_mbx_abort_o (intr_mbx4_mbx_abort), + .intr_mbx_error_o (intr_mbx4_mbx_error), + // [81]: fatal_fault + // [82]: recov_fault + .alert_tx_o ( alert_tx[82:81] ), + .alert_rx_i ( alert_rx[82:81] ), + + // Inter-module signals + .doe_intr_support_o(mbx4_doe_intr_support_o), + .doe_intr_en_o(mbx4_doe_intr_en_o), + .doe_intr_o(mbx4_doe_intr_o), + .doe_async_msg_support_o(mbx4_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[4]), + .sram_tl_h_o(main_tl_mbx4__sram_req), + .sram_tl_h_i(main_tl_mbx4__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx4_soc_tl_d_req), + .soc_tl_d_o(mbx4_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX5_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX5_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX5_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[84:83]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx5 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx5_mbx_ready), + .intr_mbx_abort_o (intr_mbx5_mbx_abort), + .intr_mbx_error_o (intr_mbx5_mbx_error), + // [83]: fatal_fault + // [84]: recov_fault + .alert_tx_o ( alert_tx[84:83] ), + .alert_rx_i ( alert_rx[84:83] ), + + // Inter-module signals + .doe_intr_support_o(mbx5_doe_intr_support_o), + .doe_intr_en_o(mbx5_doe_intr_en_o), + .doe_intr_o(mbx5_doe_intr_o), + .doe_async_msg_support_o(mbx5_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[5]), + .sram_tl_h_o(main_tl_mbx5__sram_req), + .sram_tl_h_i(main_tl_mbx5__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx5_soc_tl_d_req), + .soc_tl_d_o(mbx5_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX6_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX6_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX6_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[86:85]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx6 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx6_mbx_ready), + .intr_mbx_abort_o (intr_mbx6_mbx_abort), + .intr_mbx_error_o (intr_mbx6_mbx_error), + // [85]: fatal_fault + // [86]: recov_fault + .alert_tx_o ( alert_tx[86:85] ), + .alert_rx_i ( alert_rx[86:85] ), + + // Inter-module signals + .doe_intr_support_o(mbx6_doe_intr_support_o), + .doe_intr_en_o(mbx6_doe_intr_en_o), + .doe_intr_o(mbx6_doe_intr_o), + .doe_async_msg_support_o(mbx6_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[6]), + .sram_tl_h_o(main_tl_mbx6__sram_req), + .sram_tl_h_i(main_tl_mbx6__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx6_soc_tl_d_req), + .soc_tl_d_o(mbx6_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX_JTAG_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX_JTAG_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX_JTAG_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[88:87]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx_jtag ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx_jtag_mbx_ready), + .intr_mbx_abort_o (intr_mbx_jtag_mbx_abort), + .intr_mbx_error_o (intr_mbx_jtag_mbx_error), + // [87]: fatal_fault + // [88]: recov_fault + .alert_tx_o ( alert_tx[88:87] ), + .alert_rx_i ( alert_rx[88:87] ), + + // Inter-module signals + .doe_intr_support_o(mbx_jtag_doe_intr_support_o), + .doe_intr_en_o(mbx_jtag_doe_intr_en_o), + .doe_intr_o(mbx_jtag_doe_intr_o), + .doe_async_msg_support_o(mbx_jtag_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[7]), + .sram_tl_h_o(main_tl_mbx_jtag__sram_req), + .sram_tl_h_i(main_tl_mbx_jtag__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx_jtag_soc_tl_d_req), + .soc_tl_d_o(mbx_jtag_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX_PCIE0_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX_PCIE0_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX_PCIE0_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[90:89]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx_pcie0 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx_pcie0_mbx_ready), + .intr_mbx_abort_o (intr_mbx_pcie0_mbx_abort), + .intr_mbx_error_o (intr_mbx_pcie0_mbx_error), + // [89]: fatal_fault + // [90]: recov_fault + .alert_tx_o ( alert_tx[90:89] ), + .alert_rx_i ( alert_rx[90:89] ), + + // Inter-module signals + .doe_intr_support_o(mbx_pcie0_doe_intr_support_o), + .doe_intr_en_o(mbx_pcie0_doe_intr_en_o), + .doe_intr_o(mbx_pcie0_doe_intr_o), + .doe_async_msg_support_o(mbx_pcie0_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[8]), + .sram_tl_h_o(main_tl_mbx_pcie0__sram_req), + .sram_tl_h_i(main_tl_mbx_pcie0__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx_pcie0_soc_tl_d_req), + .soc_tl_d_o(mbx_pcie0_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + mbx #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVecSoc(RACL_POLICY_SEL_VEC_MBX_PCIE1_SOC), + .RaclPolicySelWinSocWdata(RACL_POLICY_SEL_WIN_MBX_PCIE1_SOC_WDATA), + .RaclPolicySelWinSocRdata(RACL_POLICY_SEL_WIN_MBX_PCIE1_SOC_RDATA), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[92:91]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_mbx_pcie1 ( + + // Interrupt + .intr_mbx_ready_o (intr_mbx_pcie1_mbx_ready), + .intr_mbx_abort_o (intr_mbx_pcie1_mbx_abort), + .intr_mbx_error_o (intr_mbx_pcie1_mbx_error), + // [91]: fatal_fault + // [92]: recov_fault + .alert_tx_o ( alert_tx[92:91] ), + .alert_rx_i ( alert_rx[92:91] ), + + // Inter-module signals + .doe_intr_support_o(mbx_pcie1_doe_intr_support_o), + .doe_intr_en_o(mbx_pcie1_doe_intr_en_o), + .doe_intr_o(mbx_pcie1_doe_intr_o), + .doe_async_msg_support_o(mbx_pcie1_doe_async_msg_support_o), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[9]), + .sram_tl_h_o(main_tl_mbx_pcie1__sram_req), + .sram_tl_h_i(main_tl_mbx_pcie1__sram_rsp), + .core_tl_d_i(tlul_pkg::TL_H2D_DEFAULT), + .core_tl_d_o(), + .soc_tl_d_i(mbx_pcie1_soc_tl_d_req), + .soc_tl_d_o(mbx_pcie1_soc_tl_d_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + soc_dbg_ctrl #( + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[94:93]), + .AlertSkewCycles(top_pkg::AlertSkewCycles) + ) u_soc_dbg_ctrl ( + // [93]: fatal_fault + // [94]: recov_ctrl_update_err + .alert_tx_o ( alert_tx[94:93] ), + .alert_rx_i ( alert_rx[94:93] ), + + // Inter-module signals + .boot_status_i(pwrmgr_aon_boot_status), + .soc_dbg_state_i(soc_dbg_ctrl_soc_dbg_state), + .soc_dbg_policy_bus_o(soc_dbg_policy_bus_o), + .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en), + .lc_dft_en_i(lc_ctrl_lc_dft_en), + .lc_raw_test_rma_i(lc_ctrl_lc_raw_test_rma), + .halt_cpu_boot_i(debug_halt_cpu_boot_i), + .continue_cpu_boot_o(pwrmgr_aon_rom_ctrl[2]), + .core_tl_i(soc_dbg_ctrl_core_tl_req), + .core_tl_o(soc_dbg_ctrl_core_tl_rsp), + .jtag_tl_i(soc_dbg_ctrl_jtag_tl_req), + .jtag_tl_o(soc_dbg_ctrl_jtag_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_io_div4_secure), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) + ); + racl_ctrl #( + .RaclErrorRsp(1'b1), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[96:95]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .NumSubscribingIps(RaclCtrlNumSubscribingIps), + .NumExternalSubscribingIps(RaclCtrlNumExternalSubscribingIps) + ) u_racl_ctrl ( + + // Interrupt + .intr_racl_error_o (intr_racl_ctrl_racl_error), + // [95]: fatal_fault + // [96]: recov_ctrl_update_err + .alert_tx_o ( alert_tx[96:95] ), + .alert_rx_i ( alert_rx[96:95] ), + + // Inter-module signals + .racl_policies_o(racl_ctrl_racl_policies), + .racl_error_i(racl_ctrl_racl_error), + .racl_error_external_i(racl_error_i), + .tl_i(racl_ctrl_tl_req), + .tl_o(racl_ctrl_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + ac_range_check #( + .EnableRacl(1'b1), + .RaclErrorRsp(top_racl_pkg::ErrorRsp), + .RaclPolicySelVec(RACL_POLICY_SEL_VEC_AC_RANGE_CHECK), + .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[98:97]), + .AlertSkewCycles(top_pkg::AlertSkewCycles), + .RangeCheckErrorRsp(AcRangeCheckRangeCheckErrorRsp) + ) u_ac_range_check ( + + // Interrupt + .intr_deny_cnt_reached_o (intr_ac_range_check_deny_cnt_reached), + // [97]: recov_ctrl_update_err + // [98]: fatal_fault + .alert_tx_o ( alert_tx[98:97] ), + .alert_rx_i ( alert_rx[98:97] ), + + // Inter-module signals + .range_check_overwrite_i(ac_range_check_overwrite_i), + .ctn_tl_h2d_i(soc_proxy_ctn_tl_h2d), + .ctn_tl_d2h_o(soc_proxy_ctn_tl_d2h), + .ctn_filtered_tl_h2d_o(ctn_tl_h2d_o), + .ctn_filtered_tl_d2h_i(ctn_tl_d2h_i), + .racl_policies_i(racl_ctrl_racl_policies), + .racl_error_o(racl_ctrl_racl_error[10]), + .tl_i(ac_range_check_tl_req), + .tl_o(ac_range_check_tl_rsp), + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_secure), + .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); + + + // interrupt assignments + assign intr_vector = { + intr_ac_range_check_deny_cnt_reached, // IDs [162 +: 1] + intr_racl_ctrl_racl_error, // IDs [161 +: 1] + intr_mbx_pcie1_mbx_error, // IDs [160 +: 1] + intr_mbx_pcie1_mbx_abort, // IDs [159 +: 1] + intr_mbx_pcie1_mbx_ready, // IDs [158 +: 1] + intr_mbx_pcie0_mbx_error, // IDs [157 +: 1] + intr_mbx_pcie0_mbx_abort, // IDs [156 +: 1] + intr_mbx_pcie0_mbx_ready, // IDs [155 +: 1] + intr_mbx_jtag_mbx_error, // IDs [154 +: 1] + intr_mbx_jtag_mbx_abort, // IDs [153 +: 1] + intr_mbx_jtag_mbx_ready, // IDs [152 +: 1] + intr_mbx6_mbx_error, // IDs [151 +: 1] + intr_mbx6_mbx_abort, // IDs [150 +: 1] + intr_mbx6_mbx_ready, // IDs [149 +: 1] + intr_mbx5_mbx_error, // IDs [148 +: 1] + intr_mbx5_mbx_abort, // IDs [147 +: 1] + intr_mbx5_mbx_ready, // IDs [146 +: 1] + intr_mbx4_mbx_error, // IDs [145 +: 1] + intr_mbx4_mbx_abort, // IDs [144 +: 1] + intr_mbx4_mbx_ready, // IDs [143 +: 1] + intr_mbx3_mbx_error, // IDs [142 +: 1] + intr_mbx3_mbx_abort, // IDs [141 +: 1] + intr_mbx3_mbx_ready, // IDs [140 +: 1] + intr_mbx2_mbx_error, // IDs [139 +: 1] + intr_mbx2_mbx_abort, // IDs [138 +: 1] + intr_mbx2_mbx_ready, // IDs [137 +: 1] + intr_mbx1_mbx_error, // IDs [136 +: 1] + intr_mbx1_mbx_abort, // IDs [135 +: 1] + intr_mbx1_mbx_ready, // IDs [134 +: 1] + intr_mbx0_mbx_error, // IDs [133 +: 1] + intr_mbx0_mbx_abort, // IDs [132 +: 1] + intr_mbx0_mbx_ready, // IDs [131 +: 1] + intr_dma_dma_error, // IDs [130 +: 1] + intr_dma_dma_chunk_done, // IDs [129 +: 1] + intr_dma_dma_done, // IDs [128 +: 1] + intr_edn1_edn_fatal_err, // IDs [127 +: 1] + intr_edn1_edn_cmd_req_done, // IDs [126 +: 1] + intr_edn0_edn_fatal_err, // IDs [125 +: 1] + intr_edn0_edn_cmd_req_done, // IDs [124 +: 1] + intr_entropy_src_es_fatal_err, // IDs [123 +: 1] + intr_entropy_src_es_observe_fifo_ready, // IDs [122 +: 1] + intr_entropy_src_es_health_test_failed, // IDs [121 +: 1] + intr_entropy_src_es_entropy_valid, // IDs [120 +: 1] + intr_csrng_cs_fatal_err, // IDs [119 +: 1] + intr_csrng_cs_hw_inst_exc, // IDs [118 +: 1] + intr_csrng_cs_entropy_req, // IDs [117 +: 1] + intr_csrng_cs_cmd_req_done, // IDs [116 +: 1] + intr_keymgr_dpe_op_done, // IDs [115 +: 1] + intr_otbn_done, // IDs [114 +: 1] + intr_kmac_kmac_err, // IDs [113 +: 1] + intr_kmac_fifo_empty, // IDs [112 +: 1] + intr_kmac_kmac_done, // IDs [111 +: 1] + intr_hmac_hmac_err, // IDs [110 +: 1] + intr_hmac_fifo_empty, // IDs [109 +: 1] + intr_hmac_hmac_done, // IDs [108 +: 1] + intr_soc_proxy_external, // IDs [76 +: 32] + intr_aon_timer_aon_wdog_timer_bark, // IDs [75 +: 1] + intr_aon_timer_aon_wkup_timer_expired, // IDs [74 +: 1] + intr_pwrmgr_aon_wakeup, // IDs [73 +: 1] + intr_spi_host0_spi_event, // IDs [72 +: 1] + intr_spi_host0_error, // IDs [71 +: 1] + intr_alert_handler_classd, // IDs [70 +: 1] + intr_alert_handler_classc, // IDs [69 +: 1] + intr_alert_handler_classb, // IDs [68 +: 1] + intr_alert_handler_classa, // IDs [67 +: 1] + intr_otp_ctrl_otp_error, // IDs [66 +: 1] + intr_otp_ctrl_otp_operation_done, // IDs [65 +: 1] + intr_i2c0_host_timeout, // IDs [64 +: 1] + intr_i2c0_unexp_stop, // IDs [63 +: 1] + intr_i2c0_acq_stretch, // IDs [62 +: 1] + intr_i2c0_tx_threshold, // IDs [61 +: 1] + intr_i2c0_tx_stretch, // IDs [60 +: 1] + intr_i2c0_cmd_complete, // IDs [59 +: 1] + intr_i2c0_sda_unstable, // IDs [58 +: 1] + intr_i2c0_stretch_timeout, // IDs [57 +: 1] + intr_i2c0_sda_interference, // IDs [56 +: 1] + intr_i2c0_scl_interference, // IDs [55 +: 1] + intr_i2c0_controller_halt, // IDs [54 +: 1] + intr_i2c0_rx_overflow, // IDs [53 +: 1] + intr_i2c0_acq_threshold, // IDs [52 +: 1] + intr_i2c0_rx_threshold, // IDs [51 +: 1] + intr_i2c0_fmt_threshold, // IDs [50 +: 1] + intr_spi_device_tpm_rdfifo_drop, // IDs [49 +: 1] + intr_spi_device_tpm_rdfifo_cmd_end, // IDs [48 +: 1] + intr_spi_device_tpm_header_not_empty, // IDs [47 +: 1] + intr_spi_device_readbuf_flip, // IDs [46 +: 1] + intr_spi_device_readbuf_watermark, // IDs [45 +: 1] + intr_spi_device_upload_payload_overflow, // IDs [44 +: 1] + intr_spi_device_upload_payload_not_empty, // IDs [43 +: 1] + intr_spi_device_upload_cmdfifo_not_empty, // IDs [42 +: 1] + intr_gpio_gpio, // IDs [10 +: 32] + intr_uart0_tx_empty, // IDs [9 +: 1] + intr_uart0_rx_parity_err, // IDs [8 +: 1] + intr_uart0_rx_timeout, // IDs [7 +: 1] + intr_uart0_rx_break_err, // IDs [6 +: 1] + intr_uart0_rx_frame_err, // IDs [5 +: 1] + intr_uart0_rx_overflow, // IDs [4 +: 1] + intr_uart0_tx_done, // IDs [3 +: 1] + intr_uart0_rx_watermark, // IDs [2 +: 1] + intr_uart0_tx_watermark, // IDs [1 +: 1] + 1'b 0 // ID [0 +: 1] is a special case and tied to zero. + }; + + // TL-UL Crossbar + xbar_main u_xbar_main ( + .clk_main_i (clkmgr_aon_clocks.clk_main_infra), + .clk_fixed_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_fixed_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + + // port: tl_dma__host + .tl_dma__host_i(main_tl_dma__host_req), + .tl_dma__host_o(main_tl_dma__host_rsp), + + // port: tl_mbx0__sram + .tl_mbx0__sram_i(main_tl_mbx0__sram_req), + .tl_mbx0__sram_o(main_tl_mbx0__sram_rsp), + + // port: tl_mbx1__sram + .tl_mbx1__sram_i(main_tl_mbx1__sram_req), + .tl_mbx1__sram_o(main_tl_mbx1__sram_rsp), + + // port: tl_mbx2__sram + .tl_mbx2__sram_i(main_tl_mbx2__sram_req), + .tl_mbx2__sram_o(main_tl_mbx2__sram_rsp), + + // port: tl_mbx3__sram + .tl_mbx3__sram_i(main_tl_mbx3__sram_req), + .tl_mbx3__sram_o(main_tl_mbx3__sram_rsp), + + // port: tl_mbx4__sram + .tl_mbx4__sram_i(main_tl_mbx4__sram_req), + .tl_mbx4__sram_o(main_tl_mbx4__sram_rsp), + + // port: tl_mbx5__sram + .tl_mbx5__sram_i(main_tl_mbx5__sram_req), + .tl_mbx5__sram_o(main_tl_mbx5__sram_rsp), + + // port: tl_mbx6__sram + .tl_mbx6__sram_i(main_tl_mbx6__sram_req), + .tl_mbx6__sram_o(main_tl_mbx6__sram_rsp), + + // port: tl_mbx_jtag__sram + .tl_mbx_jtag__sram_i(main_tl_mbx_jtag__sram_req), + .tl_mbx_jtag__sram_o(main_tl_mbx_jtag__sram_rsp), + + // port: tl_mbx_pcie0__sram + .tl_mbx_pcie0__sram_i(main_tl_mbx_pcie0__sram_req), + .tl_mbx_pcie0__sram_o(main_tl_mbx_pcie0__sram_rsp), + + // port: tl_mbx_pcie1__sram + .tl_mbx_pcie1__sram_i(main_tl_mbx_pcie1__sram_req), + .tl_mbx_pcie1__sram_o(main_tl_mbx_pcie1__sram_rsp), + + // port: tl_peri + .tl_peri_o(main_tl_peri_req), + .tl_peri_i(main_tl_peri_rsp), + + // port: tl_soc_proxy__ctn + .tl_soc_proxy__ctn_o(soc_proxy_ctn_tl_req), + .tl_soc_proxy__ctn_i(soc_proxy_ctn_tl_rsp), + + // port: tl_hmac + .tl_hmac_o(hmac_tl_req), + .tl_hmac_i(hmac_tl_rsp), + + // port: tl_kmac + .tl_kmac_o(kmac_tl_req), + .tl_kmac_i(kmac_tl_rsp), + + // port: tl_aes + .tl_aes_o(aes_tl_req), + .tl_aes_i(aes_tl_rsp), + + // port: tl_otbn + .tl_otbn_o(otbn_tl_req), + .tl_otbn_i(otbn_tl_rsp), + + // port: tl_keymgr_dpe + .tl_keymgr_dpe_o(keymgr_dpe_tl_req), + .tl_keymgr_dpe_i(keymgr_dpe_tl_rsp), + + // port: tl_sram_ctrl_main__ram + .tl_sram_ctrl_main__ram_o(sram_ctrl_main_ram_tl_req), + .tl_sram_ctrl_main__ram_i(sram_ctrl_main_ram_tl_rsp), + + // port: tl_sram_ctrl_mbox__ram + .tl_sram_ctrl_mbox__ram_o(sram_ctrl_mbox_ram_tl_req), + .tl_sram_ctrl_mbox__ram_i(sram_ctrl_mbox_ram_tl_rsp), + + + .scanmode_i + ); + xbar_peri u_xbar_peri ( + .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + + // port: tl_main + .tl_main_i(main_tl_peri_req), + .tl_main_o(main_tl_peri_rsp), + + // port: tl_uart0 + .tl_uart0_o(uart0_tl_req), + .tl_uart0_i(uart0_tl_rsp), + + // port: tl_i2c0 + .tl_i2c0_o(i2c0_tl_req), + .tl_i2c0_i(i2c0_tl_rsp), + + // port: tl_gpio + .tl_gpio_o(gpio_tl_req), + .tl_gpio_i(gpio_tl_rsp), + + // port: tl_spi_host0 + .tl_spi_host0_o(spi_host0_tl_req), + .tl_spi_host0_i(spi_host0_tl_rsp), + + // port: tl_spi_device + .tl_spi_device_o(spi_device_tl_req), + .tl_spi_device_i(spi_device_tl_rsp), + + // port: tl_pwrmgr_aon + .tl_pwrmgr_aon_o(pwrmgr_aon_tl_req), + .tl_pwrmgr_aon_i(pwrmgr_aon_tl_rsp), + + // port: tl_rstmgr_aon + .tl_rstmgr_aon_o(rstmgr_aon_tl_req), + .tl_rstmgr_aon_i(rstmgr_aon_tl_rsp), + + // port: tl_clkmgr_aon + .tl_clkmgr_aon_o(clkmgr_aon_tl_req), + .tl_clkmgr_aon_i(clkmgr_aon_tl_rsp), + + // port: tl_pinmux_aon + .tl_pinmux_aon_o(pinmux_aon_tl_req), + .tl_pinmux_aon_i(pinmux_aon_tl_rsp), + + // port: tl_otp_ctrl__core + .tl_otp_ctrl__core_o(otp_ctrl_core_tl_req), + .tl_otp_ctrl__core_i(otp_ctrl_core_tl_rsp), + + // port: tl_otp_macro__prim + .tl_otp_macro__prim_o(otp_macro_prim_tl_req), + .tl_otp_macro__prim_i(otp_macro_prim_tl_rsp), + + // port: tl_lc_ctrl__regs + .tl_lc_ctrl__regs_o(lc_ctrl_regs_tl_req), + .tl_lc_ctrl__regs_i(lc_ctrl_regs_tl_rsp), + + // port: tl_alert_handler + .tl_alert_handler_o(alert_handler_tl_req), + .tl_alert_handler_i(alert_handler_tl_rsp), + + // port: tl_sram_ctrl_ret_aon__regs + .tl_sram_ctrl_ret_aon__regs_o(sram_ctrl_ret_aon_regs_tl_req), + .tl_sram_ctrl_ret_aon__regs_i(sram_ctrl_ret_aon_regs_tl_rsp), + + // port: tl_sram_ctrl_ret_aon__ram + .tl_sram_ctrl_ret_aon__ram_o(sram_ctrl_ret_aon_ram_tl_req), + .tl_sram_ctrl_ret_aon__ram_i(sram_ctrl_ret_aon_ram_tl_rsp), + + // port: tl_aon_timer_aon + .tl_aon_timer_aon_o(aon_timer_aon_tl_req), + .tl_aon_timer_aon_i(aon_timer_aon_tl_rsp), + + // port: tl_ast + .tl_ast_o(ast_tl_req_o), + .tl_ast_i(ast_tl_rsp_i), + + // port: tl_soc_dbg_ctrl__core + .tl_soc_dbg_ctrl__core_o(soc_dbg_ctrl_core_tl_req), + .tl_soc_dbg_ctrl__core_i(soc_dbg_ctrl_core_tl_rsp), + + + .scanmode_i + ); + xbar_mbx u_xbar_mbx ( + .clk_mbx_i (clkmgr_aon_clocks.clk_main_infra), + .rst_mbx_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + + // port: tl_mbx + .tl_mbx_i(mbx_tl_req_i), + .tl_mbx_o(mbx_tl_rsp_o), + + // port: tl_mbx0__soc + .tl_mbx0__soc_o(mbx0_soc_tl_d_req), + .tl_mbx0__soc_i(mbx0_soc_tl_d_rsp), + + // port: tl_mbx1__soc + .tl_mbx1__soc_o(mbx1_soc_tl_d_req), + .tl_mbx1__soc_i(mbx1_soc_tl_d_rsp), + + // port: tl_mbx2__soc + .tl_mbx2__soc_o(mbx2_soc_tl_d_req), + .tl_mbx2__soc_i(mbx2_soc_tl_d_rsp), + + // port: tl_mbx3__soc + .tl_mbx3__soc_o(mbx3_soc_tl_d_req), + .tl_mbx3__soc_i(mbx3_soc_tl_d_rsp), + + // port: tl_mbx4__soc + .tl_mbx4__soc_o(mbx4_soc_tl_d_req), + .tl_mbx4__soc_i(mbx4_soc_tl_d_rsp), + + // port: tl_mbx5__soc + .tl_mbx5__soc_o(mbx5_soc_tl_d_req), + .tl_mbx5__soc_i(mbx5_soc_tl_d_rsp), + + // port: tl_mbx6__soc + .tl_mbx6__soc_o(mbx6_soc_tl_d_req), + .tl_mbx6__soc_i(mbx6_soc_tl_d_rsp), + + // port: tl_mbx_pcie0__soc + .tl_mbx_pcie0__soc_o(mbx_pcie0_soc_tl_d_req), + .tl_mbx_pcie0__soc_i(mbx_pcie0_soc_tl_d_rsp), + + // port: tl_mbx_pcie1__soc + .tl_mbx_pcie1__soc_o(mbx_pcie1_soc_tl_d_req), + .tl_mbx_pcie1__soc_i(mbx_pcie1_soc_tl_d_rsp), + + // port: tl_racl_ctrl + .tl_racl_ctrl_o(racl_ctrl_tl_req), + .tl_racl_ctrl_i(racl_ctrl_tl_rsp), + + // port: tl_ac_range_check + .tl_ac_range_check_o(ac_range_check_tl_req), + .tl_ac_range_check_i(ac_range_check_tl_rsp), + + + .scanmode_i + ); + xbar_dbg u_xbar_dbg ( + .clk_dbg_i (clkmgr_aon_clocks.clk_main_infra), + .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra), + .rst_dbg_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]), + + // port: tl_dbg + .tl_dbg_i(dbg_tl_req_i), + .tl_dbg_o(dbg_tl_rsp_o), + + // port: tl_mbx_jtag__soc + .tl_mbx_jtag__soc_o(mbx_jtag_soc_tl_d_req), + .tl_mbx_jtag__soc_i(mbx_jtag_soc_tl_d_rsp), + + // port: tl_lc_ctrl__dmi + .tl_lc_ctrl__dmi_o(lc_ctrl_dmi_tl_req), + .tl_lc_ctrl__dmi_i(lc_ctrl_dmi_tl_rsp), + + // port: tl_soc_dbg_ctrl__jtag + .tl_soc_dbg_ctrl__jtag_o(soc_dbg_ctrl_jtag_tl_req), + .tl_soc_dbg_ctrl__jtag_i(soc_dbg_ctrl_jtag_tl_rsp), + + + .scanmode_i + ); + + // Pinmux connections + // All muxed inputs + assign cio_soc_proxy_soc_gpi_p2d[12] = mio_p2d[MioInSocProxySocGpi12]; + assign cio_soc_proxy_soc_gpi_p2d[13] = mio_p2d[MioInSocProxySocGpi13]; + assign cio_soc_proxy_soc_gpi_p2d[14] = mio_p2d[MioInSocProxySocGpi14]; + assign cio_soc_proxy_soc_gpi_p2d[15] = mio_p2d[MioInSocProxySocGpi15]; + + // All muxed outputs + assign mio_d2p[MioOutSocProxySocGpo12] = cio_soc_proxy_soc_gpo_d2p[12]; + assign mio_d2p[MioOutSocProxySocGpo13] = cio_soc_proxy_soc_gpo_d2p[13]; + assign mio_d2p[MioOutSocProxySocGpo14] = cio_soc_proxy_soc_gpo_d2p[14]; + assign mio_d2p[MioOutSocProxySocGpo15] = cio_soc_proxy_soc_gpo_d2p[15]; + assign mio_d2p[MioOutOtpMacroTest0] = cio_otp_macro_test_d2p[0]; + + // All muxed output enables + assign mio_en_d2p[MioOutSocProxySocGpo12] = cio_soc_proxy_soc_gpo_en_d2p[12]; + assign mio_en_d2p[MioOutSocProxySocGpo13] = cio_soc_proxy_soc_gpo_en_d2p[13]; + assign mio_en_d2p[MioOutSocProxySocGpo14] = cio_soc_proxy_soc_gpo_en_d2p[14]; + assign mio_en_d2p[MioOutSocProxySocGpo15] = cio_soc_proxy_soc_gpo_en_d2p[15]; + assign mio_en_d2p[MioOutOtpMacroTest0] = cio_otp_macro_test_en_d2p[0]; + + // All dedicated inputs + logic [72:0] unused_dio_p2d; + assign unused_dio_p2d = dio_p2d; + assign cio_spi_host0_sd_p2d[0] = dio_p2d[DioSpiHost0Sd0]; + assign cio_spi_host0_sd_p2d[1] = dio_p2d[DioSpiHost0Sd1]; + assign cio_spi_host0_sd_p2d[2] = dio_p2d[DioSpiHost0Sd2]; + assign cio_spi_host0_sd_p2d[3] = dio_p2d[DioSpiHost0Sd3]; + assign cio_spi_device_sd_p2d[0] = dio_p2d[DioSpiDeviceSd0]; + assign cio_spi_device_sd_p2d[1] = dio_p2d[DioSpiDeviceSd1]; + assign cio_spi_device_sd_p2d[2] = dio_p2d[DioSpiDeviceSd2]; + assign cio_spi_device_sd_p2d[3] = dio_p2d[DioSpiDeviceSd3]; + assign cio_i2c0_scl_p2d = dio_p2d[DioI2c0Scl]; + assign cio_i2c0_sda_p2d = dio_p2d[DioI2c0Sda]; + assign cio_gpio_gpio_p2d[0] = dio_p2d[DioGpioGpio0]; + assign cio_gpio_gpio_p2d[1] = dio_p2d[DioGpioGpio1]; + assign cio_gpio_gpio_p2d[2] = dio_p2d[DioGpioGpio2]; + assign cio_gpio_gpio_p2d[3] = dio_p2d[DioGpioGpio3]; + assign cio_gpio_gpio_p2d[4] = dio_p2d[DioGpioGpio4]; + assign cio_gpio_gpio_p2d[5] = dio_p2d[DioGpioGpio5]; + assign cio_gpio_gpio_p2d[6] = dio_p2d[DioGpioGpio6]; + assign cio_gpio_gpio_p2d[7] = dio_p2d[DioGpioGpio7]; + assign cio_gpio_gpio_p2d[8] = dio_p2d[DioGpioGpio8]; + assign cio_gpio_gpio_p2d[9] = dio_p2d[DioGpioGpio9]; + assign cio_gpio_gpio_p2d[10] = dio_p2d[DioGpioGpio10]; + assign cio_gpio_gpio_p2d[11] = dio_p2d[DioGpioGpio11]; + assign cio_gpio_gpio_p2d[12] = dio_p2d[DioGpioGpio12]; + assign cio_gpio_gpio_p2d[13] = dio_p2d[DioGpioGpio13]; + assign cio_gpio_gpio_p2d[14] = dio_p2d[DioGpioGpio14]; + assign cio_gpio_gpio_p2d[15] = dio_p2d[DioGpioGpio15]; + assign cio_gpio_gpio_p2d[16] = dio_p2d[DioGpioGpio16]; + assign cio_gpio_gpio_p2d[17] = dio_p2d[DioGpioGpio17]; + assign cio_gpio_gpio_p2d[18] = dio_p2d[DioGpioGpio18]; + assign cio_gpio_gpio_p2d[19] = dio_p2d[DioGpioGpio19]; + assign cio_gpio_gpio_p2d[20] = dio_p2d[DioGpioGpio20]; + assign cio_gpio_gpio_p2d[21] = dio_p2d[DioGpioGpio21]; + assign cio_gpio_gpio_p2d[22] = dio_p2d[DioGpioGpio22]; + assign cio_gpio_gpio_p2d[23] = dio_p2d[DioGpioGpio23]; + assign cio_gpio_gpio_p2d[24] = dio_p2d[DioGpioGpio24]; + assign cio_gpio_gpio_p2d[25] = dio_p2d[DioGpioGpio25]; + assign cio_gpio_gpio_p2d[26] = dio_p2d[DioGpioGpio26]; + assign cio_gpio_gpio_p2d[27] = dio_p2d[DioGpioGpio27]; + assign cio_gpio_gpio_p2d[28] = dio_p2d[DioGpioGpio28]; + assign cio_gpio_gpio_p2d[29] = dio_p2d[DioGpioGpio29]; + assign cio_gpio_gpio_p2d[30] = dio_p2d[DioGpioGpio30]; + assign cio_gpio_gpio_p2d[31] = dio_p2d[DioGpioGpio31]; + assign cio_spi_device_sck_p2d = dio_p2d[DioSpiDeviceSck]; + assign cio_spi_device_csb_p2d = dio_p2d[DioSpiDeviceCsb]; + assign cio_spi_device_tpm_csb_p2d = dio_p2d[DioSpiDeviceTpmCsb]; + assign cio_uart0_rx_p2d = dio_p2d[DioUart0Rx]; + assign cio_soc_proxy_soc_gpi_p2d[0] = dio_p2d[DioSocProxySocGpi0]; + assign cio_soc_proxy_soc_gpi_p2d[1] = dio_p2d[DioSocProxySocGpi1]; + assign cio_soc_proxy_soc_gpi_p2d[2] = dio_p2d[DioSocProxySocGpi2]; + assign cio_soc_proxy_soc_gpi_p2d[3] = dio_p2d[DioSocProxySocGpi3]; + assign cio_soc_proxy_soc_gpi_p2d[4] = dio_p2d[DioSocProxySocGpi4]; + assign cio_soc_proxy_soc_gpi_p2d[5] = dio_p2d[DioSocProxySocGpi5]; + assign cio_soc_proxy_soc_gpi_p2d[6] = dio_p2d[DioSocProxySocGpi6]; + assign cio_soc_proxy_soc_gpi_p2d[7] = dio_p2d[DioSocProxySocGpi7]; + assign cio_soc_proxy_soc_gpi_p2d[8] = dio_p2d[DioSocProxySocGpi8]; + assign cio_soc_proxy_soc_gpi_p2d[9] = dio_p2d[DioSocProxySocGpi9]; + assign cio_soc_proxy_soc_gpi_p2d[10] = dio_p2d[DioSocProxySocGpi10]; + assign cio_soc_proxy_soc_gpi_p2d[11] = dio_p2d[DioSocProxySocGpi11]; + + // All dedicated outputs + assign dio_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_d2p[0]; + assign dio_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_d2p[1]; + assign dio_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_d2p[2]; + assign dio_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_d2p[3]; + assign dio_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_d2p[0]; + assign dio_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_d2p[1]; + assign dio_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_d2p[2]; + assign dio_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_d2p[3]; + assign dio_d2p[DioI2c0Scl] = cio_i2c0_scl_d2p; + assign dio_d2p[DioI2c0Sda] = cio_i2c0_sda_d2p; + assign dio_d2p[DioGpioGpio0] = cio_gpio_gpio_d2p[0]; + assign dio_d2p[DioGpioGpio1] = cio_gpio_gpio_d2p[1]; + assign dio_d2p[DioGpioGpio2] = cio_gpio_gpio_d2p[2]; + assign dio_d2p[DioGpioGpio3] = cio_gpio_gpio_d2p[3]; + assign dio_d2p[DioGpioGpio4] = cio_gpio_gpio_d2p[4]; + assign dio_d2p[DioGpioGpio5] = cio_gpio_gpio_d2p[5]; + assign dio_d2p[DioGpioGpio6] = cio_gpio_gpio_d2p[6]; + assign dio_d2p[DioGpioGpio7] = cio_gpio_gpio_d2p[7]; + assign dio_d2p[DioGpioGpio8] = cio_gpio_gpio_d2p[8]; + assign dio_d2p[DioGpioGpio9] = cio_gpio_gpio_d2p[9]; + assign dio_d2p[DioGpioGpio10] = cio_gpio_gpio_d2p[10]; + assign dio_d2p[DioGpioGpio11] = cio_gpio_gpio_d2p[11]; + assign dio_d2p[DioGpioGpio12] = cio_gpio_gpio_d2p[12]; + assign dio_d2p[DioGpioGpio13] = cio_gpio_gpio_d2p[13]; + assign dio_d2p[DioGpioGpio14] = cio_gpio_gpio_d2p[14]; + assign dio_d2p[DioGpioGpio15] = cio_gpio_gpio_d2p[15]; + assign dio_d2p[DioGpioGpio16] = cio_gpio_gpio_d2p[16]; + assign dio_d2p[DioGpioGpio17] = cio_gpio_gpio_d2p[17]; + assign dio_d2p[DioGpioGpio18] = cio_gpio_gpio_d2p[18]; + assign dio_d2p[DioGpioGpio19] = cio_gpio_gpio_d2p[19]; + assign dio_d2p[DioGpioGpio20] = cio_gpio_gpio_d2p[20]; + assign dio_d2p[DioGpioGpio21] = cio_gpio_gpio_d2p[21]; + assign dio_d2p[DioGpioGpio22] = cio_gpio_gpio_d2p[22]; + assign dio_d2p[DioGpioGpio23] = cio_gpio_gpio_d2p[23]; + assign dio_d2p[DioGpioGpio24] = cio_gpio_gpio_d2p[24]; + assign dio_d2p[DioGpioGpio25] = cio_gpio_gpio_d2p[25]; + assign dio_d2p[DioGpioGpio26] = cio_gpio_gpio_d2p[26]; + assign dio_d2p[DioGpioGpio27] = cio_gpio_gpio_d2p[27]; + assign dio_d2p[DioGpioGpio28] = cio_gpio_gpio_d2p[28]; + assign dio_d2p[DioGpioGpio29] = cio_gpio_gpio_d2p[29]; + assign dio_d2p[DioGpioGpio30] = cio_gpio_gpio_d2p[30]; + assign dio_d2p[DioGpioGpio31] = cio_gpio_gpio_d2p[31]; + assign dio_d2p[DioSpiDeviceSck] = 1'b0; + assign dio_d2p[DioSpiDeviceCsb] = 1'b0; + assign dio_d2p[DioSpiDeviceTpmCsb] = 1'b0; + assign dio_d2p[DioUart0Rx] = 1'b0; + assign dio_d2p[DioSocProxySocGpi0] = 1'b0; + assign dio_d2p[DioSocProxySocGpi1] = 1'b0; + assign dio_d2p[DioSocProxySocGpi2] = 1'b0; + assign dio_d2p[DioSocProxySocGpi3] = 1'b0; + assign dio_d2p[DioSocProxySocGpi4] = 1'b0; + assign dio_d2p[DioSocProxySocGpi5] = 1'b0; + assign dio_d2p[DioSocProxySocGpi6] = 1'b0; + assign dio_d2p[DioSocProxySocGpi7] = 1'b0; + assign dio_d2p[DioSocProxySocGpi8] = 1'b0; + assign dio_d2p[DioSocProxySocGpi9] = 1'b0; + assign dio_d2p[DioSocProxySocGpi10] = 1'b0; + assign dio_d2p[DioSocProxySocGpi11] = 1'b0; + assign dio_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_d2p; + assign dio_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_d2p; + assign dio_d2p[DioUart0Tx] = cio_uart0_tx_d2p; + assign dio_d2p[DioSocProxySocGpo0] = cio_soc_proxy_soc_gpo_d2p[0]; + assign dio_d2p[DioSocProxySocGpo1] = cio_soc_proxy_soc_gpo_d2p[1]; + assign dio_d2p[DioSocProxySocGpo2] = cio_soc_proxy_soc_gpo_d2p[2]; + assign dio_d2p[DioSocProxySocGpo3] = cio_soc_proxy_soc_gpo_d2p[3]; + assign dio_d2p[DioSocProxySocGpo4] = cio_soc_proxy_soc_gpo_d2p[4]; + assign dio_d2p[DioSocProxySocGpo5] = cio_soc_proxy_soc_gpo_d2p[5]; + assign dio_d2p[DioSocProxySocGpo6] = cio_soc_proxy_soc_gpo_d2p[6]; + assign dio_d2p[DioSocProxySocGpo7] = cio_soc_proxy_soc_gpo_d2p[7]; + assign dio_d2p[DioSocProxySocGpo8] = cio_soc_proxy_soc_gpo_d2p[8]; + assign dio_d2p[DioSocProxySocGpo9] = cio_soc_proxy_soc_gpo_d2p[9]; + assign dio_d2p[DioSocProxySocGpo10] = cio_soc_proxy_soc_gpo_d2p[10]; + assign dio_d2p[DioSocProxySocGpo11] = cio_soc_proxy_soc_gpo_d2p[11]; + + // All dedicated output enables + assign dio_en_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_en_d2p[0]; + assign dio_en_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_en_d2p[1]; + assign dio_en_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_en_d2p[2]; + assign dio_en_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_en_d2p[3]; + assign dio_en_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_en_d2p[0]; + assign dio_en_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_en_d2p[1]; + assign dio_en_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_en_d2p[2]; + assign dio_en_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_en_d2p[3]; + assign dio_en_d2p[DioI2c0Scl] = cio_i2c0_scl_en_d2p; + assign dio_en_d2p[DioI2c0Sda] = cio_i2c0_sda_en_d2p; + assign dio_en_d2p[DioGpioGpio0] = cio_gpio_gpio_en_d2p[0]; + assign dio_en_d2p[DioGpioGpio1] = cio_gpio_gpio_en_d2p[1]; + assign dio_en_d2p[DioGpioGpio2] = cio_gpio_gpio_en_d2p[2]; + assign dio_en_d2p[DioGpioGpio3] = cio_gpio_gpio_en_d2p[3]; + assign dio_en_d2p[DioGpioGpio4] = cio_gpio_gpio_en_d2p[4]; + assign dio_en_d2p[DioGpioGpio5] = cio_gpio_gpio_en_d2p[5]; + assign dio_en_d2p[DioGpioGpio6] = cio_gpio_gpio_en_d2p[6]; + assign dio_en_d2p[DioGpioGpio7] = cio_gpio_gpio_en_d2p[7]; + assign dio_en_d2p[DioGpioGpio8] = cio_gpio_gpio_en_d2p[8]; + assign dio_en_d2p[DioGpioGpio9] = cio_gpio_gpio_en_d2p[9]; + assign dio_en_d2p[DioGpioGpio10] = cio_gpio_gpio_en_d2p[10]; + assign dio_en_d2p[DioGpioGpio11] = cio_gpio_gpio_en_d2p[11]; + assign dio_en_d2p[DioGpioGpio12] = cio_gpio_gpio_en_d2p[12]; + assign dio_en_d2p[DioGpioGpio13] = cio_gpio_gpio_en_d2p[13]; + assign dio_en_d2p[DioGpioGpio14] = cio_gpio_gpio_en_d2p[14]; + assign dio_en_d2p[DioGpioGpio15] = cio_gpio_gpio_en_d2p[15]; + assign dio_en_d2p[DioGpioGpio16] = cio_gpio_gpio_en_d2p[16]; + assign dio_en_d2p[DioGpioGpio17] = cio_gpio_gpio_en_d2p[17]; + assign dio_en_d2p[DioGpioGpio18] = cio_gpio_gpio_en_d2p[18]; + assign dio_en_d2p[DioGpioGpio19] = cio_gpio_gpio_en_d2p[19]; + assign dio_en_d2p[DioGpioGpio20] = cio_gpio_gpio_en_d2p[20]; + assign dio_en_d2p[DioGpioGpio21] = cio_gpio_gpio_en_d2p[21]; + assign dio_en_d2p[DioGpioGpio22] = cio_gpio_gpio_en_d2p[22]; + assign dio_en_d2p[DioGpioGpio23] = cio_gpio_gpio_en_d2p[23]; + assign dio_en_d2p[DioGpioGpio24] = cio_gpio_gpio_en_d2p[24]; + assign dio_en_d2p[DioGpioGpio25] = cio_gpio_gpio_en_d2p[25]; + assign dio_en_d2p[DioGpioGpio26] = cio_gpio_gpio_en_d2p[26]; + assign dio_en_d2p[DioGpioGpio27] = cio_gpio_gpio_en_d2p[27]; + assign dio_en_d2p[DioGpioGpio28] = cio_gpio_gpio_en_d2p[28]; + assign dio_en_d2p[DioGpioGpio29] = cio_gpio_gpio_en_d2p[29]; + assign dio_en_d2p[DioGpioGpio30] = cio_gpio_gpio_en_d2p[30]; + assign dio_en_d2p[DioGpioGpio31] = cio_gpio_gpio_en_d2p[31]; + assign dio_en_d2p[DioSpiDeviceSck] = 1'b0; + assign dio_en_d2p[DioSpiDeviceCsb] = 1'b0; + assign dio_en_d2p[DioSpiDeviceTpmCsb] = 1'b0; + assign dio_en_d2p[DioUart0Rx] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi0] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi1] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi2] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi3] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi4] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi5] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi6] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi7] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi8] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi9] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi10] = 1'b0; + assign dio_en_d2p[DioSocProxySocGpi11] = 1'b0; + assign dio_en_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_en_d2p; + assign dio_en_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_en_d2p; + assign dio_en_d2p[DioUart0Tx] = cio_uart0_tx_en_d2p; + assign dio_en_d2p[DioSocProxySocGpo0] = cio_soc_proxy_soc_gpo_en_d2p[0]; + assign dio_en_d2p[DioSocProxySocGpo1] = cio_soc_proxy_soc_gpo_en_d2p[1]; + assign dio_en_d2p[DioSocProxySocGpo2] = cio_soc_proxy_soc_gpo_en_d2p[2]; + assign dio_en_d2p[DioSocProxySocGpo3] = cio_soc_proxy_soc_gpo_en_d2p[3]; + assign dio_en_d2p[DioSocProxySocGpo4] = cio_soc_proxy_soc_gpo_en_d2p[4]; + assign dio_en_d2p[DioSocProxySocGpo5] = cio_soc_proxy_soc_gpo_en_d2p[5]; + assign dio_en_d2p[DioSocProxySocGpo6] = cio_soc_proxy_soc_gpo_en_d2p[6]; + assign dio_en_d2p[DioSocProxySocGpo7] = cio_soc_proxy_soc_gpo_en_d2p[7]; + assign dio_en_d2p[DioSocProxySocGpo8] = cio_soc_proxy_soc_gpo_en_d2p[8]; + assign dio_en_d2p[DioSocProxySocGpo9] = cio_soc_proxy_soc_gpo_en_d2p[9]; + assign dio_en_d2p[DioSocProxySocGpo10] = cio_soc_proxy_soc_gpo_en_d2p[10]; + assign dio_en_d2p[DioSocProxySocGpo11] = cio_soc_proxy_soc_gpo_en_d2p[11]; + + + // make sure scanmode_i is never X (including during reset) + `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_main_i, 0) + + // TODO(#26288) : EnCsrngSwAppReadSize should not be present in Darjeeling; presently, this signal + // must be used to avoid a lint error. + logic unused_en_csrng; + assign unused_en_csrng = ^otp_ctrl_otp_broadcast.hw_cfg1_data.en_csrng_sw_app_read; + +endmodule diff --git a/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_pkg.sv b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_pkg.sv new file mode 100644 index 00000000000..ec7327f448b --- /dev/null +++ b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_pkg.sv @@ -0,0 +1,1164 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +package top_darjeeling_no_ibex_pkg; + /** + * Peripheral base address for uart0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_UART0_BASE_ADDR = 32'h30010000; + + /** + * Peripheral size in bytes for uart0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_UART0_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for gpio in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_GPIO_BASE_ADDR = 32'h30000000; + + /** + * Peripheral size in bytes for gpio in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_GPIO_SIZE_BYTES = 32'h100; + + /** + * Peripheral base address for spi_device in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SPI_DEVICE_BASE_ADDR = 32'h30310000; + + /** + * Peripheral size in bytes for spi_device in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SPI_DEVICE_SIZE_BYTES = 32'h2000; + + /** + * Peripheral base address for i2c0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_I2C0_BASE_ADDR = 32'h30080000; + + /** + * Peripheral size in bytes for i2c0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_I2C0_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on otp_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_BASE_ADDR = 32'h30130000; + + /** + * Peripheral size in bytes for core device on otp_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_SIZE_BYTES = 32'h8000; + + /** + * Peripheral base address for prim device on otp_macro in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_BASE_ADDR = 32'h30140000; + + /** + * Peripheral size in bytes for prim device on otp_macro in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for regs device on lc_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_BASE_ADDR = 32'h30150000; + + /** + * Peripheral size in bytes for regs device on lc_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_SIZE_BYTES = 32'h100; + + /** + * Peripheral base address for alert_handler in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_BASE_ADDR = 32'h30160000; + + /** + * Peripheral size in bytes for alert_handler in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_SIZE_BYTES = 32'h800; + + /** + * Peripheral base address for spi_host0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SPI_HOST0_BASE_ADDR = 32'h30300000; + + /** + * Peripheral size in bytes for spi_host0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SPI_HOST0_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for pwrmgr_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_PWRMGR_AON_BASE_ADDR = 32'h30400000; + + /** + * Peripheral size in bytes for pwrmgr_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_PWRMGR_AON_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for rstmgr_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RSTMGR_AON_BASE_ADDR = 32'h30410000; + + /** + * Peripheral size in bytes for rstmgr_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RSTMGR_AON_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for clkmgr_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_CLKMGR_AON_BASE_ADDR = 32'h30420000; + + /** + * Peripheral size in bytes for clkmgr_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_CLKMGR_AON_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for pinmux_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_PINMUX_AON_BASE_ADDR = 32'h30460000; + + /** + * Peripheral size in bytes for pinmux_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_PINMUX_AON_SIZE_BYTES = 32'h800; + + /** + * Peripheral base address for aon_timer_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_BASE_ADDR = 32'h30470000; + + /** + * Peripheral size in bytes for aon_timer_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for ast in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_AST_BASE_ADDR = 32'h30480000; + + /** + * Peripheral size in bytes for ast in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_AST_SIZE_BYTES = 32'h400; + + /** + * Peripheral base address for core device on soc_proxy in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_BASE_ADDR = 32'h22030000; + + /** + * Peripheral size in bytes for core device on soc_proxy in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_SIZE_BYTES = 32'h10; + + /** + * Peripheral base address for ctn device on soc_proxy in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_BASE_ADDR = 32'h40000000; + + /** + * Peripheral size in bytes for ctn device on soc_proxy in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_SIZE_BYTES = 32'h40000000; + + /** + * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_BASE_ADDR = 32'h30500000; + + /** + * Peripheral size in bytes for regs device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_BASE_ADDR = 32'h30600000; + + /** + * Peripheral size in bytes for ram device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for rv_plic in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RV_PLIC_BASE_ADDR = 32'h28000000; + + /** + * Peripheral size in bytes for rv_plic in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RV_PLIC_SIZE_BYTES = 32'h8000000; + + /** + * Peripheral base address for aes in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_AES_BASE_ADDR = 32'h21100000; + + /** + * Peripheral size in bytes for aes in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_AES_SIZE_BYTES = 32'h100; + + /** + * Peripheral base address for hmac in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_HMAC_BASE_ADDR = 32'h21110000; + + /** + * Peripheral size in bytes for hmac in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_HMAC_SIZE_BYTES = 32'h2000; + + /** + * Peripheral base address for kmac in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_KMAC_BASE_ADDR = 32'h21120000; + + /** + * Peripheral size in bytes for kmac in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_KMAC_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for otbn in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_OTBN_BASE_ADDR = 32'h21130000; + + /** + * Peripheral size in bytes for otbn in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_OTBN_SIZE_BYTES = 32'h10000; + + /** + * Peripheral base address for keymgr_dpe in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_BASE_ADDR = 32'h21140000; + + /** + * Peripheral size in bytes for keymgr_dpe in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_SIZE_BYTES = 32'h100; + + /** + * Peripheral base address for csrng in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_CSRNG_BASE_ADDR = 32'h21150000; + + /** + * Peripheral size in bytes for csrng in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_CSRNG_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for entropy_src in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_BASE_ADDR = 32'h21160000; + + /** + * Peripheral size in bytes for entropy_src in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_SIZE_BYTES = 32'h100; + + /** + * Peripheral base address for edn0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_EDN0_BASE_ADDR = 32'h21170000; + + /** + * Peripheral size in bytes for edn0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_EDN0_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for edn1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_EDN1_BASE_ADDR = 32'h21180000; + + /** + * Peripheral size in bytes for edn1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_EDN1_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for regs device on sram_ctrl_main in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_BASE_ADDR = 32'h211C0000; + + /** + * Peripheral size in bytes for regs device on sram_ctrl_main in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for ram device on sram_ctrl_main in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_BASE_ADDR = 32'h10000000; + + /** + * Peripheral size in bytes for ram device on sram_ctrl_main in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_SIZE_BYTES = 32'h10000; + + /** + * Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_BASE_ADDR = 32'h211D0000; + + /** + * Peripheral size in bytes for regs device on sram_ctrl_mbox in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_SIZE_BYTES = 32'h40; + + /** + * Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_BASE_ADDR = 32'h11000000; + + /** + * Peripheral size in bytes for ram device on sram_ctrl_mbox in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for regs device on rom_ctrl0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_BASE_ADDR = 32'h211E0000; + + /** + * Peripheral size in bytes for regs device on rom_ctrl0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for rom device on rom_ctrl0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_BASE_ADDR = 32'h8000; + + /** + * Peripheral size in bytes for rom device on rom_ctrl0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_SIZE_BYTES = 32'h8000; + + /** + * Peripheral base address for regs device on rom_ctrl1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_BASE_ADDR = 32'h211E1000; + + /** + * Peripheral size in bytes for regs device on rom_ctrl1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for rom device on rom_ctrl1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_BASE_ADDR = 32'h20000; + + /** + * Peripheral size in bytes for rom device on rom_ctrl1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_SIZE_BYTES = 32'h10000; + + /** + * Peripheral base address for dma in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_DMA_BASE_ADDR = 32'h22010000; + + /** + * Peripheral size in bytes for dma in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_DMA_SIZE_BYTES = 32'h200; + + /** + * Peripheral base address for core device on mbx0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX0_CORE_BASE_ADDR = 32'h22000000; + + /** + * Peripheral size in bytes for core device on mbx0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX0_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX1_CORE_BASE_ADDR = 32'h22000100; + + /** + * Peripheral size in bytes for core device on mbx1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX1_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx2 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX2_CORE_BASE_ADDR = 32'h22000200; + + /** + * Peripheral size in bytes for core device on mbx2 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX2_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx3 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX3_CORE_BASE_ADDR = 32'h22000300; + + /** + * Peripheral size in bytes for core device on mbx3 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX3_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx4 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX4_CORE_BASE_ADDR = 32'h22000400; + + /** + * Peripheral size in bytes for core device on mbx4 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX4_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx5 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX5_CORE_BASE_ADDR = 32'h22000500; + + /** + * Peripheral size in bytes for core device on mbx5 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX5_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx6 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX6_CORE_BASE_ADDR = 32'h22000600; + + /** + * Peripheral size in bytes for core device on mbx6 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX6_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx_jtag in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_BASE_ADDR = 32'h22000800; + + /** + * Peripheral size in bytes for core device on mbx_jtag in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx_pcie0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_BASE_ADDR = 32'h22040000; + + /** + * Peripheral size in bytes for core device on mbx_pcie0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on mbx_pcie1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_BASE_ADDR = 32'h22040100; + + /** + * Peripheral size in bytes for core device on mbx_pcie1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_SIZE_BYTES = 32'h80; + + /** + * Peripheral base address for core device on soc_dbg_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_BASE_ADDR = 32'h30170000; + + /** + * Peripheral size in bytes for core device on soc_dbg_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_SIZE_BYTES = 32'h20; + + /** + * Memory base address for ctn in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_CTN_BASE_ADDR = 32'h40000000; + + /** + * Memory size for ctn in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_CTN_SIZE_BYTES = 32'h40000000; + + /** + * Memory base address for ram_ctn in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RAM_CTN_BASE_ADDR = 32'h41000000; + + /** + * Memory size for ram_ctn in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RAM_CTN_SIZE_BYTES = 32'h100000; + + /** + * Memory base address for ram_ret_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RAM_RET_AON_BASE_ADDR = 32'h30600000; + + /** + * Memory size for ram_ret_aon in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RAM_RET_AON_SIZE_BYTES = 32'h1000; + + /** + * Memory base address for ram_main in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RAM_MAIN_BASE_ADDR = 32'h10000000; + + /** + * Memory size for ram_main in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RAM_MAIN_SIZE_BYTES = 32'h10000; + + /** + * Memory base address for ram_mbox in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RAM_MBOX_BASE_ADDR = 32'h11000000; + + /** + * Memory size for ram_mbox in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_RAM_MBOX_SIZE_BYTES = 32'h1000; + + /** + * Memory base address for rom0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM0_BASE_ADDR = 32'h8000; + + /** + * Memory size for rom0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM0_SIZE_BYTES = 32'h8000; + + /** + * Memory base address for rom1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM1_BASE_ADDR = 32'h20000; + + /** + * Memory size for rom1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_ROM1_SIZE_BYTES = 32'h10000; + + + // Enumeration of alert modules + typedef enum int unsigned { + TopDarjeelingNoIbexAlertPeripheralUart0 = 0, + TopDarjeelingNoIbexAlertPeripheralGpio = 1, + TopDarjeelingNoIbexAlertPeripheralSpiDevice = 2, + TopDarjeelingNoIbexAlertPeripheralI2c0 = 3, + TopDarjeelingNoIbexAlertPeripheralOtpCtrl = 4, + TopDarjeelingNoIbexAlertPeripheralLcCtrl = 5, + TopDarjeelingNoIbexAlertPeripheralSpiHost0 = 6, + TopDarjeelingNoIbexAlertPeripheralPwrmgrAon = 7, + TopDarjeelingNoIbexAlertPeripheralRstmgrAon = 8, + TopDarjeelingNoIbexAlertPeripheralClkmgrAon = 9, + TopDarjeelingNoIbexAlertPeripheralPinmuxAon = 10, + TopDarjeelingNoIbexAlertPeripheralAonTimerAon = 11, + TopDarjeelingNoIbexAlertPeripheralSocProxy = 12, + TopDarjeelingNoIbexAlertPeripheralSramCtrlRetAon = 13, + TopDarjeelingNoIbexAlertPeripheralRvPlic = 14, + TopDarjeelingNoIbexAlertPeripheralAes = 15, + TopDarjeelingNoIbexAlertPeripheralHmac = 16, + TopDarjeelingNoIbexAlertPeripheralKmac = 17, + TopDarjeelingNoIbexAlertPeripheralOtbn = 18, + TopDarjeelingNoIbexAlertPeripheralKeymgrDpe = 19, + TopDarjeelingNoIbexAlertPeripheralCsrng = 20, + TopDarjeelingNoIbexAlertPeripheralEntropySrc = 21, + TopDarjeelingNoIbexAlertPeripheralEdn0 = 22, + TopDarjeelingNoIbexAlertPeripheralEdn1 = 23, + TopDarjeelingNoIbexAlertPeripheralSramCtrlMain = 24, + TopDarjeelingNoIbexAlertPeripheralSramCtrlMbox = 25, + TopDarjeelingNoIbexAlertPeripheralRomCtrl0 = 26, + TopDarjeelingNoIbexAlertPeripheralRomCtrl1 = 27, + TopDarjeelingNoIbexAlertPeripheralDma = 28, + TopDarjeelingNoIbexAlertPeripheralMbx0 = 29, + TopDarjeelingNoIbexAlertPeripheralMbx1 = 30, + TopDarjeelingNoIbexAlertPeripheralMbx2 = 31, + TopDarjeelingNoIbexAlertPeripheralMbx3 = 32, + TopDarjeelingNoIbexAlertPeripheralMbx4 = 33, + TopDarjeelingNoIbexAlertPeripheralMbx5 = 34, + TopDarjeelingNoIbexAlertPeripheralMbx6 = 35, + TopDarjeelingNoIbexAlertPeripheralMbxJtag = 36, + TopDarjeelingNoIbexAlertPeripheralMbxPcie0 = 37, + TopDarjeelingNoIbexAlertPeripheralMbxPcie1 = 38, + TopDarjeelingNoIbexAlertPeripheralSocDbgCtrl = 39, + TopDarjeelingNoIbexAlertPeripheralRaclCtrl = 40, + TopDarjeelingNoIbexAlertPeripheralAcRangeCheck = 41, + TopDarjeelingNoIbexAlertPeripheralCount + } alert_peripheral_e; + + // Enumeration of alerts + typedef enum int unsigned { + TopDarjeelingNoIbexAlertIdUart0FatalFault = 0, + TopDarjeelingNoIbexAlertIdGpioFatalFault = 1, + TopDarjeelingNoIbexAlertIdSpiDeviceFatalFault = 2, + TopDarjeelingNoIbexAlertIdI2c0FatalFault = 3, + TopDarjeelingNoIbexAlertIdOtpCtrlFatalMacroError = 4, + TopDarjeelingNoIbexAlertIdOtpCtrlFatalCheckError = 5, + TopDarjeelingNoIbexAlertIdOtpCtrlFatalBusIntegError = 6, + TopDarjeelingNoIbexAlertIdOtpCtrlFatalPrimOtpAlert = 7, + TopDarjeelingNoIbexAlertIdOtpCtrlRecovPrimOtpAlert = 8, + TopDarjeelingNoIbexAlertIdLcCtrlFatalProgError = 9, + TopDarjeelingNoIbexAlertIdLcCtrlFatalStateError = 10, + TopDarjeelingNoIbexAlertIdLcCtrlFatalBusIntegError = 11, + TopDarjeelingNoIbexAlertIdSpiHost0FatalFault = 12, + TopDarjeelingNoIbexAlertIdPwrmgrAonFatalFault = 13, + TopDarjeelingNoIbexAlertIdRstmgrAonFatalFault = 14, + TopDarjeelingNoIbexAlertIdRstmgrAonFatalCnstyFault = 15, + TopDarjeelingNoIbexAlertIdClkmgrAonRecovFault = 16, + TopDarjeelingNoIbexAlertIdClkmgrAonFatalFault = 17, + TopDarjeelingNoIbexAlertIdPinmuxAonFatalFault = 18, + TopDarjeelingNoIbexAlertIdAonTimerAonFatalFault = 19, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertIntg = 20, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal0 = 21, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal1 = 22, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal2 = 23, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal3 = 24, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal4 = 25, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal5 = 26, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal6 = 27, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal7 = 28, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal8 = 29, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal9 = 30, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal10 = 31, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal11 = 32, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal12 = 33, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal13 = 34, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal14 = 35, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal15 = 36, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal16 = 37, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal17 = 38, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal18 = 39, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal19 = 40, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal20 = 41, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal21 = 42, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal22 = 43, + TopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal23 = 44, + TopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal0 = 45, + TopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal1 = 46, + TopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal2 = 47, + TopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal3 = 48, + TopDarjeelingNoIbexAlertIdSramCtrlRetAonFatalError = 49, + TopDarjeelingNoIbexAlertIdRvPlicFatalFault = 50, + TopDarjeelingNoIbexAlertIdAesRecovCtrlUpdateErr = 51, + TopDarjeelingNoIbexAlertIdAesFatalFault = 52, + TopDarjeelingNoIbexAlertIdHmacFatalFault = 53, + TopDarjeelingNoIbexAlertIdKmacRecovOperationErr = 54, + TopDarjeelingNoIbexAlertIdKmacFatalFaultErr = 55, + TopDarjeelingNoIbexAlertIdOtbnFatal = 56, + TopDarjeelingNoIbexAlertIdOtbnRecov = 57, + TopDarjeelingNoIbexAlertIdKeymgrDpeRecovOperationErr = 58, + TopDarjeelingNoIbexAlertIdKeymgrDpeFatalFaultErr = 59, + TopDarjeelingNoIbexAlertIdCsrngRecovAlert = 60, + TopDarjeelingNoIbexAlertIdCsrngFatalAlert = 61, + TopDarjeelingNoIbexAlertIdEntropySrcRecovAlert = 62, + TopDarjeelingNoIbexAlertIdEntropySrcFatalAlert = 63, + TopDarjeelingNoIbexAlertIdEdn0RecovAlert = 64, + TopDarjeelingNoIbexAlertIdEdn0FatalAlert = 65, + TopDarjeelingNoIbexAlertIdEdn1RecovAlert = 66, + TopDarjeelingNoIbexAlertIdEdn1FatalAlert = 67, + TopDarjeelingNoIbexAlertIdSramCtrlMainFatalError = 68, + TopDarjeelingNoIbexAlertIdSramCtrlMboxFatalError = 69, + TopDarjeelingNoIbexAlertIdRomCtrl0Fatal = 70, + TopDarjeelingNoIbexAlertIdRomCtrl1Fatal = 71, + TopDarjeelingNoIbexAlertIdDmaFatalFault = 72, + TopDarjeelingNoIbexAlertIdMbx0FatalFault = 73, + TopDarjeelingNoIbexAlertIdMbx0RecovFault = 74, + TopDarjeelingNoIbexAlertIdMbx1FatalFault = 75, + TopDarjeelingNoIbexAlertIdMbx1RecovFault = 76, + TopDarjeelingNoIbexAlertIdMbx2FatalFault = 77, + TopDarjeelingNoIbexAlertIdMbx2RecovFault = 78, + TopDarjeelingNoIbexAlertIdMbx3FatalFault = 79, + TopDarjeelingNoIbexAlertIdMbx3RecovFault = 80, + TopDarjeelingNoIbexAlertIdMbx4FatalFault = 81, + TopDarjeelingNoIbexAlertIdMbx4RecovFault = 82, + TopDarjeelingNoIbexAlertIdMbx5FatalFault = 83, + TopDarjeelingNoIbexAlertIdMbx5RecovFault = 84, + TopDarjeelingNoIbexAlertIdMbx6FatalFault = 85, + TopDarjeelingNoIbexAlertIdMbx6RecovFault = 86, + TopDarjeelingNoIbexAlertIdMbxJtagFatalFault = 87, + TopDarjeelingNoIbexAlertIdMbxJtagRecovFault = 88, + TopDarjeelingNoIbexAlertIdMbxPcie0FatalFault = 89, + TopDarjeelingNoIbexAlertIdMbxPcie0RecovFault = 90, + TopDarjeelingNoIbexAlertIdMbxPcie1FatalFault = 91, + TopDarjeelingNoIbexAlertIdMbxPcie1RecovFault = 92, + TopDarjeelingNoIbexAlertIdSocDbgCtrlFatalFault = 93, + TopDarjeelingNoIbexAlertIdSocDbgCtrlRecovCtrlUpdateErr = 94, + TopDarjeelingNoIbexAlertIdRaclCtrlFatalFault = 95, + TopDarjeelingNoIbexAlertIdRaclCtrlRecovCtrlUpdateErr = 96, + TopDarjeelingNoIbexAlertIdAcRangeCheckRecovCtrlUpdateErr = 97, + TopDarjeelingNoIbexAlertIdAcRangeCheckFatalFault = 98, + TopDarjeelingNoIbexAlertIdCount + } alert_id_e; + + // Enumeration of interrupts + typedef enum int unsigned { + TopDarjeelingNoIbexIrqIdUart0TxWatermark = 1, + TopDarjeelingNoIbexIrqIdUart0RxWatermark = 2, + TopDarjeelingNoIbexIrqIdUart0TxDone = 3, + TopDarjeelingNoIbexIrqIdUart0RxOverflow = 4, + TopDarjeelingNoIbexIrqIdUart0RxFrameErr = 5, + TopDarjeelingNoIbexIrqIdUart0RxBreakErr = 6, + TopDarjeelingNoIbexIrqIdUart0RxTimeout = 7, + TopDarjeelingNoIbexIrqIdUart0RxParityErr = 8, + TopDarjeelingNoIbexIrqIdUart0TxEmpty = 9, + TopDarjeelingNoIbexIrqIdGpioGpio0 = 10, + TopDarjeelingNoIbexIrqIdGpioGpio1 = 11, + TopDarjeelingNoIbexIrqIdGpioGpio2 = 12, + TopDarjeelingNoIbexIrqIdGpioGpio3 = 13, + TopDarjeelingNoIbexIrqIdGpioGpio4 = 14, + TopDarjeelingNoIbexIrqIdGpioGpio5 = 15, + TopDarjeelingNoIbexIrqIdGpioGpio6 = 16, + TopDarjeelingNoIbexIrqIdGpioGpio7 = 17, + TopDarjeelingNoIbexIrqIdGpioGpio8 = 18, + TopDarjeelingNoIbexIrqIdGpioGpio9 = 19, + TopDarjeelingNoIbexIrqIdGpioGpio10 = 20, + TopDarjeelingNoIbexIrqIdGpioGpio11 = 21, + TopDarjeelingNoIbexIrqIdGpioGpio12 = 22, + TopDarjeelingNoIbexIrqIdGpioGpio13 = 23, + TopDarjeelingNoIbexIrqIdGpioGpio14 = 24, + TopDarjeelingNoIbexIrqIdGpioGpio15 = 25, + TopDarjeelingNoIbexIrqIdGpioGpio16 = 26, + TopDarjeelingNoIbexIrqIdGpioGpio17 = 27, + TopDarjeelingNoIbexIrqIdGpioGpio18 = 28, + TopDarjeelingNoIbexIrqIdGpioGpio19 = 29, + TopDarjeelingNoIbexIrqIdGpioGpio20 = 30, + TopDarjeelingNoIbexIrqIdGpioGpio21 = 31, + TopDarjeelingNoIbexIrqIdGpioGpio22 = 32, + TopDarjeelingNoIbexIrqIdGpioGpio23 = 33, + TopDarjeelingNoIbexIrqIdGpioGpio24 = 34, + TopDarjeelingNoIbexIrqIdGpioGpio25 = 35, + TopDarjeelingNoIbexIrqIdGpioGpio26 = 36, + TopDarjeelingNoIbexIrqIdGpioGpio27 = 37, + TopDarjeelingNoIbexIrqIdGpioGpio28 = 38, + TopDarjeelingNoIbexIrqIdGpioGpio29 = 39, + TopDarjeelingNoIbexIrqIdGpioGpio30 = 40, + TopDarjeelingNoIbexIrqIdGpioGpio31 = 41, + TopDarjeelingNoIbexIrqIdSpiDeviceUploadCmdfifoNotEmpty = 42, + TopDarjeelingNoIbexIrqIdSpiDeviceUploadPayloadNotEmpty = 43, + TopDarjeelingNoIbexIrqIdSpiDeviceUploadPayloadOverflow = 44, + TopDarjeelingNoIbexIrqIdSpiDeviceReadbufWatermark = 45, + TopDarjeelingNoIbexIrqIdSpiDeviceReadbufFlip = 46, + TopDarjeelingNoIbexIrqIdSpiDeviceTpmHeaderNotEmpty = 47, + TopDarjeelingNoIbexIrqIdSpiDeviceTpmRdfifoCmdEnd = 48, + TopDarjeelingNoIbexIrqIdSpiDeviceTpmRdfifoDrop = 49, + TopDarjeelingNoIbexIrqIdI2c0FmtThreshold = 50, + TopDarjeelingNoIbexIrqIdI2c0RxThreshold = 51, + TopDarjeelingNoIbexIrqIdI2c0AcqThreshold = 52, + TopDarjeelingNoIbexIrqIdI2c0RxOverflow = 53, + TopDarjeelingNoIbexIrqIdI2c0ControllerHalt = 54, + TopDarjeelingNoIbexIrqIdI2c0SclInterference = 55, + TopDarjeelingNoIbexIrqIdI2c0SdaInterference = 56, + TopDarjeelingNoIbexIrqIdI2c0StretchTimeout = 57, + TopDarjeelingNoIbexIrqIdI2c0SdaUnstable = 58, + TopDarjeelingNoIbexIrqIdI2c0CmdComplete = 59, + TopDarjeelingNoIbexIrqIdI2c0TxStretch = 60, + TopDarjeelingNoIbexIrqIdI2c0TxThreshold = 61, + TopDarjeelingNoIbexIrqIdI2c0AcqStretch = 62, + TopDarjeelingNoIbexIrqIdI2c0UnexpStop = 63, + TopDarjeelingNoIbexIrqIdI2c0HostTimeout = 64, + TopDarjeelingNoIbexIrqIdOtpCtrlOtpOperationDone = 65, + TopDarjeelingNoIbexIrqIdOtpCtrlOtpError = 66, + TopDarjeelingNoIbexIrqIdAlertHandlerClassa = 67, + TopDarjeelingNoIbexIrqIdAlertHandlerClassb = 68, + TopDarjeelingNoIbexIrqIdAlertHandlerClassc = 69, + TopDarjeelingNoIbexIrqIdAlertHandlerClassd = 70, + TopDarjeelingNoIbexIrqIdSpiHost0Error = 71, + TopDarjeelingNoIbexIrqIdSpiHost0SpiEvent = 72, + TopDarjeelingNoIbexIrqIdPwrmgrAonWakeup = 73, + TopDarjeelingNoIbexIrqIdAonTimerAonWkupTimerExpired = 74, + TopDarjeelingNoIbexIrqIdAonTimerAonWdogTimerBark = 75, + TopDarjeelingNoIbexIrqIdSocProxyExternal0 = 76, + TopDarjeelingNoIbexIrqIdSocProxyExternal1 = 77, + TopDarjeelingNoIbexIrqIdSocProxyExternal2 = 78, + TopDarjeelingNoIbexIrqIdSocProxyExternal3 = 79, + TopDarjeelingNoIbexIrqIdSocProxyExternal4 = 80, + TopDarjeelingNoIbexIrqIdSocProxyExternal5 = 81, + TopDarjeelingNoIbexIrqIdSocProxyExternal6 = 82, + TopDarjeelingNoIbexIrqIdSocProxyExternal7 = 83, + TopDarjeelingNoIbexIrqIdSocProxyExternal8 = 84, + TopDarjeelingNoIbexIrqIdSocProxyExternal9 = 85, + TopDarjeelingNoIbexIrqIdSocProxyExternal10 = 86, + TopDarjeelingNoIbexIrqIdSocProxyExternal11 = 87, + TopDarjeelingNoIbexIrqIdSocProxyExternal12 = 88, + TopDarjeelingNoIbexIrqIdSocProxyExternal13 = 89, + TopDarjeelingNoIbexIrqIdSocProxyExternal14 = 90, + TopDarjeelingNoIbexIrqIdSocProxyExternal15 = 91, + TopDarjeelingNoIbexIrqIdSocProxyExternal16 = 92, + TopDarjeelingNoIbexIrqIdSocProxyExternal17 = 93, + TopDarjeelingNoIbexIrqIdSocProxyExternal18 = 94, + TopDarjeelingNoIbexIrqIdSocProxyExternal19 = 95, + TopDarjeelingNoIbexIrqIdSocProxyExternal20 = 96, + TopDarjeelingNoIbexIrqIdSocProxyExternal21 = 97, + TopDarjeelingNoIbexIrqIdSocProxyExternal22 = 98, + TopDarjeelingNoIbexIrqIdSocProxyExternal23 = 99, + TopDarjeelingNoIbexIrqIdSocProxyExternal24 = 100, + TopDarjeelingNoIbexIrqIdSocProxyExternal25 = 101, + TopDarjeelingNoIbexIrqIdSocProxyExternal26 = 102, + TopDarjeelingNoIbexIrqIdSocProxyExternal27 = 103, + TopDarjeelingNoIbexIrqIdSocProxyExternal28 = 104, + TopDarjeelingNoIbexIrqIdSocProxyExternal29 = 105, + TopDarjeelingNoIbexIrqIdSocProxyExternal30 = 106, + TopDarjeelingNoIbexIrqIdSocProxyExternal31 = 107, + TopDarjeelingNoIbexIrqIdHmacHmacDone = 108, + TopDarjeelingNoIbexIrqIdHmacFifoEmpty = 109, + TopDarjeelingNoIbexIrqIdHmacHmacErr = 110, + TopDarjeelingNoIbexIrqIdKmacKmacDone = 111, + TopDarjeelingNoIbexIrqIdKmacFifoEmpty = 112, + TopDarjeelingNoIbexIrqIdKmacKmacErr = 113, + TopDarjeelingNoIbexIrqIdOtbnDone = 114, + TopDarjeelingNoIbexIrqIdKeymgrDpeOpDone = 115, + TopDarjeelingNoIbexIrqIdCsrngCsCmdReqDone = 116, + TopDarjeelingNoIbexIrqIdCsrngCsEntropyReq = 117, + TopDarjeelingNoIbexIrqIdCsrngCsHwInstExc = 118, + TopDarjeelingNoIbexIrqIdCsrngCsFatalErr = 119, + TopDarjeelingNoIbexIrqIdEntropySrcEsEntropyValid = 120, + TopDarjeelingNoIbexIrqIdEntropySrcEsHealthTestFailed = 121, + TopDarjeelingNoIbexIrqIdEntropySrcEsObserveFifoReady = 122, + TopDarjeelingNoIbexIrqIdEntropySrcEsFatalErr = 123, + TopDarjeelingNoIbexIrqIdEdn0EdnCmdReqDone = 124, + TopDarjeelingNoIbexIrqIdEdn0EdnFatalErr = 125, + TopDarjeelingNoIbexIrqIdEdn1EdnCmdReqDone = 126, + TopDarjeelingNoIbexIrqIdEdn1EdnFatalErr = 127, + TopDarjeelingNoIbexIrqIdDmaDmaDone = 128, + TopDarjeelingNoIbexIrqIdDmaDmaChunkDone = 129, + TopDarjeelingNoIbexIrqIdDmaDmaError = 130, + TopDarjeelingNoIbexIrqIdMbx0MbxReady = 131, + TopDarjeelingNoIbexIrqIdMbx0MbxAbort = 132, + TopDarjeelingNoIbexIrqIdMbx0MbxError = 133, + TopDarjeelingNoIbexIrqIdMbx1MbxReady = 134, + TopDarjeelingNoIbexIrqIdMbx1MbxAbort = 135, + TopDarjeelingNoIbexIrqIdMbx1MbxError = 136, + TopDarjeelingNoIbexIrqIdMbx2MbxReady = 137, + TopDarjeelingNoIbexIrqIdMbx2MbxAbort = 138, + TopDarjeelingNoIbexIrqIdMbx2MbxError = 139, + TopDarjeelingNoIbexIrqIdMbx3MbxReady = 140, + TopDarjeelingNoIbexIrqIdMbx3MbxAbort = 141, + TopDarjeelingNoIbexIrqIdMbx3MbxError = 142, + TopDarjeelingNoIbexIrqIdMbx4MbxReady = 143, + TopDarjeelingNoIbexIrqIdMbx4MbxAbort = 144, + TopDarjeelingNoIbexIrqIdMbx4MbxError = 145, + TopDarjeelingNoIbexIrqIdMbx5MbxReady = 146, + TopDarjeelingNoIbexIrqIdMbx5MbxAbort = 147, + TopDarjeelingNoIbexIrqIdMbx5MbxError = 148, + TopDarjeelingNoIbexIrqIdMbx6MbxReady = 149, + TopDarjeelingNoIbexIrqIdMbx6MbxAbort = 150, + TopDarjeelingNoIbexIrqIdMbx6MbxError = 151, + TopDarjeelingNoIbexIrqIdMbxJtagMbxReady = 152, + TopDarjeelingNoIbexIrqIdMbxJtagMbxAbort = 153, + TopDarjeelingNoIbexIrqIdMbxJtagMbxError = 154, + TopDarjeelingNoIbexIrqIdMbxPcie0MbxReady = 155, + TopDarjeelingNoIbexIrqIdMbxPcie0MbxAbort = 156, + TopDarjeelingNoIbexIrqIdMbxPcie0MbxError = 157, + TopDarjeelingNoIbexIrqIdMbxPcie1MbxReady = 158, + TopDarjeelingNoIbexIrqIdMbxPcie1MbxAbort = 159, + TopDarjeelingNoIbexIrqIdMbxPcie1MbxError = 160, + TopDarjeelingNoIbexIrqIdRaclCtrlRaclError = 161, + TopDarjeelingNoIbexIrqIdAcRangeCheckDenyCntReached = 162, + TopDarjeelingNoIbexIrqIdCount + } interrupt_id_e; + + // Enumeration of IO power domains. + // Only used in ASIC target. + typedef enum logic [0:0] { + IoBankVio = 0, + IoBankCount = 1 + } pwr_dom_e; + + // Enumeration for MIO signals on the top-level. + typedef enum int unsigned { + MioInSocProxySocGpi12 = 0, + MioInSocProxySocGpi13 = 1, + MioInSocProxySocGpi14 = 2, + MioInSocProxySocGpi15 = 3, + MioInCount = 4 + } mio_in_e; + + typedef enum { + MioOutSocProxySocGpo12 = 0, + MioOutSocProxySocGpo13 = 1, + MioOutSocProxySocGpo14 = 2, + MioOutSocProxySocGpo15 = 3, + MioOutOtpMacroTest0 = 4, + MioOutCount = 5 + } mio_out_e; + + // Enumeration for DIO signals, used on both the top and chip-levels. + typedef enum int unsigned { + DioSpiHost0Sd0 = 0, + DioSpiHost0Sd1 = 1, + DioSpiHost0Sd2 = 2, + DioSpiHost0Sd3 = 3, + DioSpiDeviceSd0 = 4, + DioSpiDeviceSd1 = 5, + DioSpiDeviceSd2 = 6, + DioSpiDeviceSd3 = 7, + DioI2c0Scl = 8, + DioI2c0Sda = 9, + DioGpioGpio0 = 10, + DioGpioGpio1 = 11, + DioGpioGpio2 = 12, + DioGpioGpio3 = 13, + DioGpioGpio4 = 14, + DioGpioGpio5 = 15, + DioGpioGpio6 = 16, + DioGpioGpio7 = 17, + DioGpioGpio8 = 18, + DioGpioGpio9 = 19, + DioGpioGpio10 = 20, + DioGpioGpio11 = 21, + DioGpioGpio12 = 22, + DioGpioGpio13 = 23, + DioGpioGpio14 = 24, + DioGpioGpio15 = 25, + DioGpioGpio16 = 26, + DioGpioGpio17 = 27, + DioGpioGpio18 = 28, + DioGpioGpio19 = 29, + DioGpioGpio20 = 30, + DioGpioGpio21 = 31, + DioGpioGpio22 = 32, + DioGpioGpio23 = 33, + DioGpioGpio24 = 34, + DioGpioGpio25 = 35, + DioGpioGpio26 = 36, + DioGpioGpio27 = 37, + DioGpioGpio28 = 38, + DioGpioGpio29 = 39, + DioGpioGpio30 = 40, + DioGpioGpio31 = 41, + DioSpiDeviceSck = 42, + DioSpiDeviceCsb = 43, + DioSpiDeviceTpmCsb = 44, + DioUart0Rx = 45, + DioSocProxySocGpi0 = 46, + DioSocProxySocGpi1 = 47, + DioSocProxySocGpi2 = 48, + DioSocProxySocGpi3 = 49, + DioSocProxySocGpi4 = 50, + DioSocProxySocGpi5 = 51, + DioSocProxySocGpi6 = 52, + DioSocProxySocGpi7 = 53, + DioSocProxySocGpi8 = 54, + DioSocProxySocGpi9 = 55, + DioSocProxySocGpi10 = 56, + DioSocProxySocGpi11 = 57, + DioSpiHost0Sck = 58, + DioSpiHost0Csb = 59, + DioUart0Tx = 60, + DioSocProxySocGpo0 = 61, + DioSocProxySocGpo1 = 62, + DioSocProxySocGpo2 = 63, + DioSocProxySocGpo3 = 64, + DioSocProxySocGpo4 = 65, + DioSocProxySocGpo5 = 66, + DioSocProxySocGpo6 = 67, + DioSocProxySocGpo7 = 68, + DioSocProxySocGpo8 = 69, + DioSocProxySocGpo9 = 70, + DioSocProxySocGpo10 = 71, + DioSocProxySocGpo11 = 72, + DioCount = 73 + } dio_e; + + // Enumeration for the types of pads. + typedef enum { + MioPad, + DioPad + } pad_type_e; + + // Raw MIO/DIO input array indices on chip-level. + // TODO: Does not account for target specific stubbed/added pads. + // Need to make a target-specific package for those. + typedef enum int unsigned { + MioPadMio0 = 0, + MioPadMio1 = 1, + MioPadMio2 = 2, + MioPadMio3 = 3, + MioPadMio4 = 4, + MioPadMio5 = 5, + MioPadMio6 = 6, + MioPadMio7 = 7, + MioPadMio8 = 8, + MioPadMio9 = 9, + MioPadMio10 = 10, + MioPadMio11 = 11, + MioPadCount + } mio_pad_e; + + typedef enum int unsigned { + DioPadPorN = 0, + DioPadJtagTck = 1, + DioPadJtagTms = 2, + DioPadJtagTdi = 3, + DioPadJtagTdo = 4, + DioPadJtagTrstN = 5, + DioPadOtpExtVolt = 6, + DioPadSpiHostD0 = 7, + DioPadSpiHostD1 = 8, + DioPadSpiHostD2 = 9, + DioPadSpiHostD3 = 10, + DioPadSpiHostClk = 11, + DioPadSpiHostCsL = 12, + DioPadSpiDevD0 = 13, + DioPadSpiDevD1 = 14, + DioPadSpiDevD2 = 15, + DioPadSpiDevD3 = 16, + DioPadSpiDevClk = 17, + DioPadSpiDevCsL = 18, + DioPadSpiDevTpmCsL = 19, + DioPadUartRx = 20, + DioPadUartTx = 21, + DioPadI2cScl = 22, + DioPadI2cSda = 23, + DioPadGpio0 = 24, + DioPadGpio1 = 25, + DioPadGpio2 = 26, + DioPadGpio3 = 27, + DioPadGpio4 = 28, + DioPadGpio5 = 29, + DioPadGpio6 = 30, + DioPadGpio7 = 31, + DioPadGpio8 = 32, + DioPadGpio9 = 33, + DioPadGpio10 = 34, + DioPadGpio11 = 35, + DioPadGpio12 = 36, + DioPadGpio13 = 37, + DioPadGpio14 = 38, + DioPadGpio15 = 39, + DioPadGpio16 = 40, + DioPadGpio17 = 41, + DioPadGpio18 = 42, + DioPadGpio19 = 43, + DioPadGpio20 = 44, + DioPadGpio21 = 45, + DioPadGpio22 = 46, + DioPadGpio23 = 47, + DioPadGpio24 = 48, + DioPadGpio25 = 49, + DioPadGpio26 = 50, + DioPadGpio27 = 51, + DioPadGpio28 = 52, + DioPadGpio29 = 53, + DioPadGpio30 = 54, + DioPadGpio31 = 55, + DioPadSocGpi0 = 56, + DioPadSocGpi1 = 57, + DioPadSocGpi2 = 58, + DioPadSocGpi3 = 59, + DioPadSocGpi4 = 60, + DioPadSocGpi5 = 61, + DioPadSocGpi6 = 62, + DioPadSocGpi7 = 63, + DioPadSocGpi8 = 64, + DioPadSocGpi9 = 65, + DioPadSocGpi10 = 66, + DioPadSocGpi11 = 67, + DioPadSocGpo0 = 68, + DioPadSocGpo1 = 69, + DioPadSocGpo2 = 70, + DioPadSocGpo3 = 71, + DioPadSocGpo4 = 72, + DioPadSocGpo5 = 73, + DioPadSocGpo6 = 74, + DioPadSocGpo7 = 75, + DioPadSocGpo8 = 76, + DioPadSocGpo9 = 77, + DioPadSocGpo10 = 78, + DioPadSocGpo11 = 79, + DioPadCount + } dio_pad_e; + + // List of peripheral instantiated in this chip. + typedef enum { + PeripheralAes, + PeripheralAlertHandler, + PeripheralAonTimerAon, + PeripheralAst, + PeripheralClkmgrAon, + PeripheralCsrng, + PeripheralDma, + PeripheralEdn0, + PeripheralEdn1, + PeripheralEntropySrc, + PeripheralGpio, + PeripheralHmac, + PeripheralI2c0, + PeripheralKeymgrDpe, + PeripheralKmac, + PeripheralLcCtrl, + PeripheralMbx0, + PeripheralMbx1, + PeripheralMbx2, + PeripheralMbx3, + PeripheralMbx4, + PeripheralMbx5, + PeripheralMbx6, + PeripheralMbxJtag, + PeripheralMbxPcie0, + PeripheralMbxPcie1, + PeripheralOtbn, + PeripheralOtpCtrl, + PeripheralOtpMacro, + PeripheralPinmuxAon, + PeripheralPwrmgrAon, + PeripheralRomCtrl0, + PeripheralRomCtrl1, + PeripheralRstmgrAon, + PeripheralRvPlic, + PeripheralSocDbgCtrl, + PeripheralSocProxy, + PeripheralSpiDevice, + PeripheralSpiHost0, + PeripheralSramCtrlMain, + PeripheralSramCtrlMbox, + PeripheralSramCtrlRetAon, + PeripheralUart0, + PeripheralCount + } peripheral_e; + + // TODO: Enumeration for PLIC Interrupt source peripheral. + +// MACROs for AST analog simulation support +`ifdef ANALOGSIM + `define INOUT_AI input ast_pkg::awire_t + `define INOUT_AO output ast_pkg::awire_t +`else + `define INOUT_AI inout + `define INOUT_AO inout +`endif + +endpackage diff --git a/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_racl_pkg.sv b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_racl_pkg.sv new file mode 100644 index 00000000000..db5895445e5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_racl_pkg.sv @@ -0,0 +1,361 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + + +package top_darjeeling_no_ibex_racl_pkg; + import top_racl_pkg::*; + + /** + * RACL groups and policies: + * Null + * 0: ALL_RD_WR + * 1: ROT_PRIVATE + * 2: SOC_ROT + */ + + /** + * Policy selection vector for mbx0 + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX0_SOC [4] = '{ + RACL_POLICY_SEL_ALL_RD_WR, // 0 SOC_CONTROL : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 1 SOC_STATUS : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 0 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX0_SOC_WDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX0_SOC_RDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + + /** + * Policy selection vector for mbx1 + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX1_SOC [4] = '{ + RACL_POLICY_SEL_ALL_RD_WR, // 0 SOC_CONTROL : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 1 SOC_STATUS : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 0 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX1_SOC_WDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX1_SOC_RDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + + /** + * Policy selection vector for mbx2 + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX2_SOC [4] = '{ + RACL_POLICY_SEL_ALL_RD_WR, // 0 SOC_CONTROL : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 1 SOC_STATUS : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 0 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX2_SOC_WDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX2_SOC_RDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + + /** + * Policy selection vector for mbx3 + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX3_SOC [4] = '{ + RACL_POLICY_SEL_ALL_RD_WR, // 0 SOC_CONTROL : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 1 SOC_STATUS : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 0 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX3_SOC_WDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX3_SOC_RDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + + /** + * Policy selection vector for mbx4 + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX4_SOC [4] = '{ + RACL_POLICY_SEL_ALL_RD_WR, // 0 SOC_CONTROL : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 1 SOC_STATUS : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 0 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX4_SOC_WDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX4_SOC_RDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + + /** + * Policy selection vector for mbx5 + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX5_SOC [4] = '{ + RACL_POLICY_SEL_ALL_RD_WR, // 0 SOC_CONTROL : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 1 SOC_STATUS : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 0 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX5_SOC_WDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX5_SOC_RDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + + /** + * Policy selection vector for mbx6 + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX6_SOC [4] = '{ + RACL_POLICY_SEL_ALL_RD_WR, // 0 SOC_CONTROL : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 1 SOC_STATUS : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 0 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX6_SOC_WDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX6_SOC_RDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + + /** + * Policy selection vector for mbx_jtag + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX_JTAG_SOC [4] = '{ + RACL_POLICY_SEL_ALL_RD_WR, // 0 SOC_CONTROL : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 1 SOC_STATUS : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 0 + RACL_POLICY_SEL_ALL_RD_WR // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 0 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX_JTAG_SOC_WDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX_JTAG_SOC_RDATA = + RACL_POLICY_SEL_ALL_RD_WR; // Policy Idx 0 + + /** + * Policy selection vector for mbx_pcie0 + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX_PCIE0_SOC [4] = '{ + RACL_POLICY_SEL_SOC_ROT, // 0 SOC_CONTROL : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 1 SOC_STATUS : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 2 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX_PCIE0_SOC_WDATA = + RACL_POLICY_SEL_SOC_ROT; // Policy Idx 2 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX_PCIE0_SOC_RDATA = + RACL_POLICY_SEL_SOC_ROT; // Policy Idx 2 + + /** + * Policy selection vector for mbx_pcie1 + * TLUL interface name: soc + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_MBX_PCIE1_SOC [4] = '{ + RACL_POLICY_SEL_SOC_ROT, // 0 SOC_CONTROL : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 1 SOC_STATUS : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 2 SOC_DOE_INTR_MSG_ADDR : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT // 3 SOC_DOE_INTR_MSG_DATA : Policy Idx 2 + }; + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX_PCIE1_SOC_WDATA = + RACL_POLICY_SEL_SOC_ROT; // Policy Idx 2 + parameter racl_policy_sel_t RACL_POLICY_SEL_WIN_MBX_PCIE1_SOC_RDATA = + RACL_POLICY_SEL_SOC_ROT; // Policy Idx 2 + + /** + * Policy selection vector for ac_range_check + * TLUL interface name: None + * RACL group: Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_VEC_AC_RANGE_CHECK [168] = '{ + RACL_POLICY_SEL_SOC_ROT, // 0 INTR_STATE : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 1 INTR_ENABLE : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 2 INTR_TEST : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 3 ALERT_TEST : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 4 ALERT_STATUS : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 5 LOG_CONFIG : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 6 LOG_STATUS : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 7 LOG_ADDRESS : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 8 RANGE_REGWEN_0 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 9 RANGE_REGWEN_1 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 10 RANGE_REGWEN_2 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 11 RANGE_REGWEN_3 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 12 RANGE_REGWEN_4 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 13 RANGE_REGWEN_5 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 14 RANGE_REGWEN_6 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 15 RANGE_REGWEN_7 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 16 RANGE_REGWEN_8 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 17 RANGE_REGWEN_9 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 18 RANGE_REGWEN_10 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 19 RANGE_REGWEN_11 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 20 RANGE_REGWEN_12 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 21 RANGE_REGWEN_13 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 22 RANGE_REGWEN_14 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 23 RANGE_REGWEN_15 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 24 RANGE_REGWEN_16 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 25 RANGE_REGWEN_17 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 26 RANGE_REGWEN_18 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 27 RANGE_REGWEN_19 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 28 RANGE_REGWEN_20 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 29 RANGE_REGWEN_21 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 30 RANGE_REGWEN_22 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 31 RANGE_REGWEN_23 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 32 RANGE_REGWEN_24 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 33 RANGE_REGWEN_25 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 34 RANGE_REGWEN_26 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 35 RANGE_REGWEN_27 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 36 RANGE_REGWEN_28 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 37 RANGE_REGWEN_29 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 38 RANGE_REGWEN_30 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 39 RANGE_REGWEN_31 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 40 RANGE_BASE_0 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 41 RANGE_BASE_1 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 42 RANGE_BASE_2 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 43 RANGE_BASE_3 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 44 RANGE_BASE_4 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 45 RANGE_BASE_5 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 46 RANGE_BASE_6 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 47 RANGE_BASE_7 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 48 RANGE_BASE_8 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 49 RANGE_BASE_9 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 50 RANGE_BASE_10 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 51 RANGE_BASE_11 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 52 RANGE_BASE_12 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 53 RANGE_BASE_13 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 54 RANGE_BASE_14 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 55 RANGE_BASE_15 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 56 RANGE_BASE_16 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 57 RANGE_BASE_17 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 58 RANGE_BASE_18 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 59 RANGE_BASE_19 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 60 RANGE_BASE_20 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 61 RANGE_BASE_21 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 62 RANGE_BASE_22 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 63 RANGE_BASE_23 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 64 RANGE_BASE_24 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 65 RANGE_BASE_25 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 66 RANGE_BASE_26 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 67 RANGE_BASE_27 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 68 RANGE_BASE_28 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 69 RANGE_BASE_29 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 70 RANGE_BASE_30 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 71 RANGE_BASE_31 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 72 RANGE_LIMIT_0 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 73 RANGE_LIMIT_1 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 74 RANGE_LIMIT_2 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 75 RANGE_LIMIT_3 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 76 RANGE_LIMIT_4 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 77 RANGE_LIMIT_5 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 78 RANGE_LIMIT_6 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 79 RANGE_LIMIT_7 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 80 RANGE_LIMIT_8 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 81 RANGE_LIMIT_9 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 82 RANGE_LIMIT_10 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 83 RANGE_LIMIT_11 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 84 RANGE_LIMIT_12 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 85 RANGE_LIMIT_13 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 86 RANGE_LIMIT_14 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 87 RANGE_LIMIT_15 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 88 RANGE_LIMIT_16 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 89 RANGE_LIMIT_17 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 90 RANGE_LIMIT_18 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 91 RANGE_LIMIT_19 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 92 RANGE_LIMIT_20 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 93 RANGE_LIMIT_21 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 94 RANGE_LIMIT_22 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 95 RANGE_LIMIT_23 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 96 RANGE_LIMIT_24 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 97 RANGE_LIMIT_25 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 98 RANGE_LIMIT_26 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 99 RANGE_LIMIT_27 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 100 RANGE_LIMIT_28 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 101 RANGE_LIMIT_29 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 102 RANGE_LIMIT_30 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 103 RANGE_LIMIT_31 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 104 RANGE_ATTR_0 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 105 RANGE_ATTR_1 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 106 RANGE_ATTR_2 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 107 RANGE_ATTR_3 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 108 RANGE_ATTR_4 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 109 RANGE_ATTR_5 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 110 RANGE_ATTR_6 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 111 RANGE_ATTR_7 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 112 RANGE_ATTR_8 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 113 RANGE_ATTR_9 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 114 RANGE_ATTR_10 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 115 RANGE_ATTR_11 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 116 RANGE_ATTR_12 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 117 RANGE_ATTR_13 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 118 RANGE_ATTR_14 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 119 RANGE_ATTR_15 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 120 RANGE_ATTR_16 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 121 RANGE_ATTR_17 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 122 RANGE_ATTR_18 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 123 RANGE_ATTR_19 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 124 RANGE_ATTR_20 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 125 RANGE_ATTR_21 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 126 RANGE_ATTR_22 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 127 RANGE_ATTR_23 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 128 RANGE_ATTR_24 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 129 RANGE_ATTR_25 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 130 RANGE_ATTR_26 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 131 RANGE_ATTR_27 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 132 RANGE_ATTR_28 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 133 RANGE_ATTR_29 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 134 RANGE_ATTR_30 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 135 RANGE_ATTR_31 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 136 RANGE_RACL_POLICY_SHADOWED_0 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 137 RANGE_RACL_POLICY_SHADOWED_1 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 138 RANGE_RACL_POLICY_SHADOWED_2 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 139 RANGE_RACL_POLICY_SHADOWED_3 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 140 RANGE_RACL_POLICY_SHADOWED_4 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 141 RANGE_RACL_POLICY_SHADOWED_5 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 142 RANGE_RACL_POLICY_SHADOWED_6 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 143 RANGE_RACL_POLICY_SHADOWED_7 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 144 RANGE_RACL_POLICY_SHADOWED_8 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 145 RANGE_RACL_POLICY_SHADOWED_9 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 146 RANGE_RACL_POLICY_SHADOWED_10 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 147 RANGE_RACL_POLICY_SHADOWED_11 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 148 RANGE_RACL_POLICY_SHADOWED_12 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 149 RANGE_RACL_POLICY_SHADOWED_13 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 150 RANGE_RACL_POLICY_SHADOWED_14 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 151 RANGE_RACL_POLICY_SHADOWED_15 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 152 RANGE_RACL_POLICY_SHADOWED_16 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 153 RANGE_RACL_POLICY_SHADOWED_17 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 154 RANGE_RACL_POLICY_SHADOWED_18 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 155 RANGE_RACL_POLICY_SHADOWED_19 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 156 RANGE_RACL_POLICY_SHADOWED_20 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 157 RANGE_RACL_POLICY_SHADOWED_21 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 158 RANGE_RACL_POLICY_SHADOWED_22 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 159 RANGE_RACL_POLICY_SHADOWED_23 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 160 RANGE_RACL_POLICY_SHADOWED_24 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 161 RANGE_RACL_POLICY_SHADOWED_25 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 162 RANGE_RACL_POLICY_SHADOWED_26 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 163 RANGE_RACL_POLICY_SHADOWED_27 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 164 RANGE_RACL_POLICY_SHADOWED_28 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 165 RANGE_RACL_POLICY_SHADOWED_29 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT, // 166 RANGE_RACL_POLICY_SHADOWED_30 : Policy Idx 2 + RACL_POLICY_SEL_SOC_ROT // 167 RANGE_RACL_POLICY_SHADOWED_31 : Policy Idx 2 + }; + +endpackage diff --git a/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_rnd_cnst_pkg.sv b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_rnd_cnst_pkg.sv new file mode 100644 index 00000000000..0aeaaad9e86 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_rnd_cnst_pkg.sv @@ -0,0 +1,362 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + + +package top_darjeeling_no_ibex_rnd_cnst_pkg; + + //////////////////////////////////////////// + // otp_ctrl + //////////////////////////////////////////// + // Compile-time random bits for initial LFSR seed + parameter otp_ctrl_top_specific_pkg::lfsr_seed_t RndCnstOtpCtrlLfsrSeed = { + 40'hCD_A9A5FCEB + }; + + // Compile-time random permutation for LFSR output + parameter otp_ctrl_top_specific_pkg::lfsr_perm_t RndCnstOtpCtrlLfsrPerm = { + 240'h5CA7_514DF488_95654290_C14125E0_1884E99C_12364F2D_40C719B8_903676A0 + }; + + // Compile-time random permutation for scrambling key/nonce register reset value + parameter otp_ctrl_top_specific_pkg::scrmbl_key_init_t RndCnstOtpCtrlScrmblKeyInit = { + 256'h58FA9063_CE216C0B_412615D7_3F476529_A96A1A8A_CA4B0BDC_BE6B240C_31095162 + }; + + //////////////////////////////////////////// + // lc_ctrl + //////////////////////////////////////////// + // Diversification value used for all invalid life cycle states. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivInvalid = { + 128'hE41BF99B_2BC41E9E_DBB4685F_7EB27EB3 + }; + + // Diversification value used for the TEST_UNLOCKED* life cycle states. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivTestUnlocked = { + 128'hB35F3527_52E34F64_CE978305_BFC3481A + }; + + // Diversification value used for the DEV life cycle state. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivDev = { + 128'h2162EA27_92B7508F_1EAB067A_F954DDA5 + }; + + // Diversification value used for the PROD/PROD_END life cycle states. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivProduction = { + 128'h491439A9_DDE63208_01FDCF25_A4FBA528 + }; + + // Diversification value used for the RMA life cycle state. + parameter lc_ctrl_pkg::lc_keymgr_div_t RndCnstLcCtrlLcKeymgrDivRma = { + 128'h39911706_9E77C887_F53DDA6F_B4EF8758 + }; + + // Compile-time random bits used for invalid tokens in the token mux + parameter lc_ctrl_pkg::lc_token_mux_t RndCnstLcCtrlInvalidTokens = { + 256'hB99027B6_AA7468BC_0BD8D703_68E7CFB1_1A99675B_14624061_9335A9E2_D123834D, + 256'h18744778_BE5E63C0_87E36838_B56B1A45_F6FD312F_5353FA7B_2CE9FC83_DDAF1DD8, + 256'hC5A42E2A_D24FA022_21B6FF5A_AD7A9C09_D5D9FDD1_CFCF5128_35C0CFAE_2ED0C69F, + 256'hA488685C_EA9BC1C8_9BFB7399_AEF5C6EB_5D6E4E23_416A0AA6_D7AC7EC9_C3304470 + }; + + //////////////////////////////////////////// + // alert_handler + //////////////////////////////////////////// + // Compile-time random bits for initial LFSR seed + parameter alert_handler_pkg::lfsr_seed_t RndCnstAlertHandlerLfsrSeed = { + 32'hFBE505F9 + }; + + // Compile-time random permutation for LFSR output + parameter alert_handler_pkg::lfsr_perm_t RndCnstAlertHandlerLfsrPerm = { + 160'h7EA97F41_618DB861_9EAAEE1C_8209A5DA_7F3C824C + }; + + //////////////////////////////////////////// + // sram_ctrl_ret_aon + //////////////////////////////////////////// + // Compile-time random reset value for SRAM scrambling key. + parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetAonSramKey = { + 128'h246C4264_F37EC198_201794AD_DA1B1692 + }; + + // Compile-time random reset value for SRAM scrambling nonce. + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetAonSramNonce = { + 128'h9DF5E06A_56AADED4_43259FFB_5736DD68 + }; + + // Compile-time random bits for initial LFSR seed + parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlRetAonLfsrSeed = { + 64'h01215B98_E162DCC0 + }; + + // Compile-time random permutation for LFSR output + parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlRetAonLfsrPerm = { + 128'hE2AC3B98_3855BD0B_2D0A5663_6D210A1C, + 256'h08895B16_1FD1EFFD_93CF8170_63CDCAE5_1382B5E8_6B7D45A5_D236CF94_4B3BA327 + }; + + //////////////////////////////////////////// + // aes + //////////////////////////////////////////// + // Default seed of the PRNG used for register clearing. + parameter aes_pkg::clearing_lfsr_seed_t RndCnstAesClearingLfsrSeed = { + 64'hDF6A55F0_D23BB7DC + }; + + // Permutation applied to the LFSR of the PRNG used for clearing. + parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingLfsrPerm = { + 128'h3875E861_96A6B9D9_D3A5B3FB_E042DE8F, + 256'hE1764300_A1AF2B41_19C93936_0CD4AAFF_3F496D4C_7CA97DDE_223A0115_6CD09C43 + }; + + // Permutation applied to the clearing PRNG output for clearing the second share of registers. + parameter aes_pkg::clearing_lfsr_perm_t RndCnstAesClearingSharePerm = { + 128'h76B2231D_488F580D_C16307CD_C7E56ED3, + 256'hAA939AF3_3F29BB49_F0E9255C_52DA0D9F_42D767B2_E3946CED_01334A0A_069DC869 + }; + + // Default seed of the PRNG used for masking. + parameter aes_pkg::masking_lfsr_seed_t RndCnstAesMaskingLfsrSeed = { + 32'h4FB06B9E, + 256'hA47DBF44_1AA625F5_DDF2DCB0_3C2B8670_24D54654_C6E64E7A_AC13CB5D_D2F3DDBB + }; + + // Permutation applied to the output of the PRNG used for masking. + parameter aes_pkg::masking_lfsr_perm_t RndCnstAesMaskingLfsrPerm = { + 256'h503D6861_08074C74_3356290C_6D163234_91532B2F_181F4879_172D990D_3A0F609E, + 256'h202E8B5F_6B808E41_4F058909_397C1B0E_73464A4B_92025587_43456996_8A124E9F, + 256'h253F867B_6C19574D_5993902C_6E679813_88651D72_479D8C23_3E22703B_8438421C, + 256'h515B7F01_780A8376_855C249B_522A5811_5E213700_267D1E40_04449C82_149A1A77, + 256'h7A6A8D94_8F35816F_757E0B62_3031063C_49546366_10150327_365A955D_64719728 + }; + + //////////////////////////////////////////// + // kmac + //////////////////////////////////////////// + // Compile-time random data for PRNG default seed + parameter kmac_pkg::lfsr_seed_t RndCnstKmacLfsrSeed = { + 32'h452480A6, + 256'h1092E8A8_0CDF2678_89E06A8A_1AB5F6DB_8158AA7C_98DDEC28_34FDD682_25AC00E6 + }; + + // Compile-time random permutation for PRNG output + parameter kmac_pkg::lfsr_perm_t RndCnstKmacLfsrPerm = { + 64'hA2269242_199B14C0, + 256'hD6F316E1_A9005719_0D034D1F_02E4676D_8A4B70B3_F9946A07_68E15649_D5D14423, + 256'hA9E5A0BD_47472D05_DB04226E_1C487FBE_8498D833_9BD879AC_9FBF2679_FB1D1357, + 256'hB9B47194_86705EB2_5797F6C8_75101508_38A47E6D_1B728B4E_23D25182_B9545BC5, + 256'h0C760419_281A2B4D_B68981BA_EA93E1BA_84CB2166_684771CB_BC385344_BB68B981, + 256'h4EC48939_32ABCC7C_55C605EA_D2FB5CC6_0B5A2493_47279F13_83E65668_636A4F48, + 256'hC6F6AA92_08A8CE68_06D61666_2A535171_666D6EC7_F1DCA55B_F560F927_6B671D34, + 256'h7F52A68C_70296B13_68BF3F01_97FC5408_8E34CDB6_74B11140_471E9899_09623A06, + 256'h2BD3199C_DCC991E1_85025C18_8E736BD2_6C3F86D5_2A66DEAD_47956516_052B7895, + 256'hC6A682A0_AE8DA29E_624D3C91_CEE72C1E_BAA2D9F4_7BC34842_DDDE43E2_2ABF020D, + 256'h90A90649_87DFBBA2_977A4301_BACDB0F0_85519209_2C2086A0_80CCCB02_854C5CF6, + 256'hBD0B39A4_378C9E00_ACA1B2BA_7895C21A_D28C8D81_99C47BCA_B9886FAC_E5F01C37, + 256'h664FABFD_2689E093_B43C1DDC_32085A04_820AECFD_17E266B9_06422E07_223FA455, + 256'hB03E3E72_9658A183_4DA3A9B9_741325E5_5557A52C_EAFDB883_7145924C_738F27D8, + 256'h3A5F6828_2E484926_ABDEE78A_650014E4_11A90751_095E03D1_A9AD6721_EC6C524B, + 256'h31770A11_69103B74_7C5A5A59_C9772282_6886A33C_D5A6A8A1_580A25BD_3F9E4535, + 256'h0B15638B_47AA9B2A_14E7E9E5_46123C00_D44540A4_F48C518A_F5F869B0_6D7112A8, + 256'h52D86114_4313EF28_32D5018C_2401D570_0D73187E_07D37BF9_67822A63_AADB96CA, + 256'hA9856849_56B1770F_2669F6EE_F80EC329_ECEFAAEE_DC591293_A06AFAE4_B1465BE5, + 256'h2E53D512_201175A7_11D1A1A1_80367993_22C4E389_4109E9C0_62340A60_43357265, + 256'hC98055ED_5C5B1255_9D1870C3_C58D2BA7_72C27C84_12B7ACB5_801D9642_4BBF4CB7, + 256'hD47D77D8_84A16AAC_104485F3_9D623B50_FB3828C2_98D5465D_30700C31_6E27A283, + 256'h64698C04_E18F10D9_71BDB7E8_7004F6A7_85670487_259D7010_A04A41BA_101D20D5, + 256'hFB3292B1_C80A86B9_0231A80A_814BE5D9_C1530D29_3025BE46_930520BE_450D2ABA, + 256'h18B4DE03_66898C16_E950E73D_DEE85A7F_478DC394_FF5B6566_2C8D9E14_4C24A712, + 256'h8CF21458_791F1848_C385DF0A_B43E4425_39109152_5BC00215_5E5AB876_E97431E9, + 256'h3CF06D03_9344EB91_660B2E55_3D563311_073022B7_B0BA8709_AC2AD88B_0782C5AC, + 256'h04105038_D6B3D989_8D0E7265_9A942CC3_8E9B1AE3_4ED3A829_F405A516_DCC7B663, + 256'h32D8C17F_9A7775F8_B9980324_BD880DF4_5E742B2E_E5D6F540_48FA3A39_5E9115B2, + 256'h2E8EE766_7DF24C9B_3120132E_C4227081_2F02EAB0_737691B4_F9F7375A_66C20765, + 256'h89232237_3786828E_B8502C47_14B863CB_350C2DC0_D02C1EC9_66E96C15_615C258A, + 256'h3E9D8BC2_8B203174_57C80497_A02F0A88_0D44D95A_91846323_59EB101A_DB995D4A + }; + + // Compile-time random data for PRNG buffer default seed + parameter kmac_pkg::buffer_lfsr_seed_t RndCnstKmacBufferLfsrSeed = { + 32'h2246562D, + 256'hCCEDA3A4_23366A80_96B121FA_42246B6C_385A5AA3_B4FE9C0A_8D1F2128_E03E0B01, + 256'h632E027E_34C81340_BCFD0FD5_3473B544_0B76763B_45BCA816_6865FDAF_59F386D5, + 256'h174CC7F5_FD1F544B_3A82C54E_1481730F_66854723_D0056094_5B6C126F_FEC03BF1 + }; + + // Compile-time random permutation for LFSR Message output + parameter kmac_pkg::msg_perm_t RndCnstKmacMsgPerm = { + 128'hB9C2273F_03A025FF_456FAB7C_566BF4E4, + 256'h74544FB5_98D73902_34BDDAC6_888C0DE1_B6499401_13E969FE_CE0A7725_EB8C086A + }; + + //////////////////////////////////////////// + // otbn + //////////////////////////////////////////// + // Default seed of the PRNG used for URND. + parameter otbn_pkg::urnd_prng_seed_t RndCnstOtbnUrndPrngSeed = { + 256'hF8A394A0_94C63C8A_F070919C_D8B168CA_B6A734A2_A92B34BA_17C53191_1E20C1A4 + }; + + // Compile-time random reset value for IMem/DMem scrambling key. + parameter otp_ctrl_pkg::otbn_key_t RndCnstOtbnOtbnKey = { + 128'h96592784_AC089E72_877BDAF9_F7954486 + }; + + // Compile-time random reset value for IMem/DMem scrambling nonce. + parameter otp_ctrl_pkg::otbn_nonce_t RndCnstOtbnOtbnNonce = { + 64'h164B58EA_68F9B7F6 + }; + + //////////////////////////////////////////// + // keymgr_dpe + //////////////////////////////////////////// + // Compile-time random bits for initial LFSR seed + parameter keymgr_pkg::lfsr_seed_t RndCnstKeymgrDpeLfsrSeed = { + 64'h47CDAFC1_C9A905A7 + }; + + // Compile-time random permutation for LFSR output + parameter keymgr_pkg::lfsr_perm_t RndCnstKeymgrDpeLfsrPerm = { + 128'hDFC0E31D_C106C730_1A9ECE4C_BD726063, + 256'h858DBA46_554F47F2_7928A122_D3BAD9B0_6B99DA7F_091D7028_BF9094FA_05F7B52A + }; + + // Compile-time random permutation for entropy used in share overriding + parameter keymgr_pkg::rand_perm_t RndCnstKeymgrDpeRandPerm = { + 160'h3F4D14A9_62F03037_66EC0934_5B538DDC_A7F43E15 + }; + + // Compile-time random bits for revision seed + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeRevisionSeed = { + 256'h6E77B99B_F0A1BCD6_7FB8941C_331A4427_7BC08F71_1D2D33E7_2BC40A36_399D8364 + }; + + // Compile-time random bits for software generation seed + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeSoftOutputSeed = { + 256'hDCD59508_D525078E_802F91D8_583804FD_E71271F1_738C1CAC_987A6B8A_7758B762 + }; + + // Compile-time random bits for hardware generation seed + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeHardOutputSeed = { + 256'h216EDD63_070949C7_834AB6EE_6E7AD485_FF3CA72C_2242223C_E6D70F17_B4F4B328 + }; + + // Compile-time random bits for generation seed when aes destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeAesSeed = { + 256'h18AA49D1_25B4DEFB_1F3C0BE8_A29BE065_C26D2355_0BBC139F_F6461763_D7E966A8 + }; + + // Compile-time random bits for generation seed when kmac destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeKmacSeed = { + 256'hA7219EB2_E8EF9F11_A152E6C7_1AA23B88_64416E75_0C01A333_9C6C7AA1_1244ECD2 + }; + + // Compile-time random bits for generation seed when otbn destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeOtbnSeed = { + 256'h8A62CB1B_851078C2_A5F18EEE_28D0B562_043B7312_EFAD871F_92E7527D_A865D661 + }; + + // Compile-time random bits for generation seed when no destination selected + parameter keymgr_pkg::seed_t RndCnstKeymgrDpeNoneSeed = { + 256'h281FE98D_FCD72E3C_6D150A85_D6300959_6F7966C5_C68CAEDD_E4AB7C65_FB8D5961 + }; + + //////////////////////////////////////////// + // csrng + //////////////////////////////////////////// + // Compile-time random bits for csrng state group diversification value + parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivNonProduction = { + 128'h8284064D_7194E470_7ADA81F8_A6DB14CA, + 256'h845BEEE6_0798289A_D4FB0DF1_76829639_0152700E_078EC5A9_51B627CF_2CCD155D + }; + + // Compile-time random bits for csrng state group diversification value + parameter csrng_pkg::cs_keymgr_div_t RndCnstCsrngCsKeymgrDivProduction = { + 128'h84FDACED_736E9336_2C8DA83C_5F4DD209, + 256'h3E4D2A70_DD99DCF4_CCAC341A_2F1A2704_F5E21287_FA168AF2_51B370D0_34CDA605 + }; + + //////////////////////////////////////////// + // sram_ctrl_main + //////////////////////////////////////////// + // Compile-time random reset value for SRAM scrambling key. + parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMainSramKey = { + 128'h152662F4_D11B3245_D5943EA5_FD2E4BEA + }; + + // Compile-time random reset value for SRAM scrambling nonce. + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMainSramNonce = { + 128'h016B7911_DEAF01DF_74254737_1445D6E3 + }; + + // Compile-time random bits for initial LFSR seed + parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMainLfsrSeed = { + 64'h955145E3_074D9CA9 + }; + + // Compile-time random permutation for LFSR output + parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMainLfsrPerm = { + 128'h839F7F3C_512A2A1A_F31ADD8C_8B867C90, + 256'hB5687252_6C013503_99F59137_41DEBAF4_317489C2_DDA61B3B_5C328D74_BE07BA7A + }; + + //////////////////////////////////////////// + // sram_ctrl_mbox + //////////////////////////////////////////// + // Compile-time random reset value for SRAM scrambling key. + parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlMboxSramKey = { + 128'h29BD781E_FE2B4B06_F4B349E0_372B7394 + }; + + // Compile-time random reset value for SRAM scrambling nonce. + parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlMboxSramNonce = { + 128'hD415D937_F3578CC1_200DD1FB_1D0ECF94 + }; + + // Compile-time random bits for initial LFSR seed + parameter sram_ctrl_pkg::lfsr_seed_t RndCnstSramCtrlMboxLfsrSeed = { + 64'h8594BC83_1C3E0E1F + }; + + // Compile-time random permutation for LFSR output + parameter sram_ctrl_pkg::lfsr_perm_t RndCnstSramCtrlMboxLfsrPerm = { + 128'h392500F4_625987FC_175BB8F4_AE86EC56, + 256'h58103487_53A6215A_E4405F3D_1DDC9EA7_B8BB31FC_90B2BAD4_3B42C766_2FFA6C8C + }; + + //////////////////////////////////////////// + // rom_ctrl0 + //////////////////////////////////////////// + // Fixed nonce used for address / data scrambling + parameter bit [63:0] RndCnstRomCtrl0ScrNonce = { + 64'h435205EF_40D4B50C + }; + + // Randomised constant used as a scrambling key for ROM data + parameter bit [127:0] RndCnstRomCtrl0ScrKey = { + 128'hBD86B493_2D75CEBE_7060738E_FA203541 + }; + + //////////////////////////////////////////// + // rom_ctrl1 + //////////////////////////////////////////// + // Fixed nonce used for address / data scrambling + parameter bit [63:0] RndCnstRomCtrl1ScrNonce = { + 64'h8082CFE9_6E5CC128 + }; + + // Randomised constant used as a scrambling key for ROM data + parameter bit [127:0] RndCnstRomCtrl1ScrKey = { + 128'h0FBE2F2E_323688BC_C7ECBB1A_7DB7BE4C + }; + +endpackage : top_darjeeling_no_ibex_rnd_cnst_pkg diff --git a/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_soc_dbg_pkg.sv b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_soc_dbg_pkg.sv new file mode 100644 index 00000000000..07eb0f5c1a8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_soc_dbg_pkg.sv @@ -0,0 +1,45 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +package top_darjeeling_no_ibex_soc_dbg_pkg; + /** + * Peripheral base address for dmi device on lc_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_BASE_ADDR = 32'h3000; + + /** + * Peripheral size in bytes for dmi device on lc_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_SIZE_BYTES = 32'h1000; + + /** + * Peripheral base address for soc device on mbx_jtag in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_BASE_ADDR = 32'h2200; + + /** + * Peripheral size in bytes for soc device on mbx_jtag in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for jtag device on soc_dbg_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_BASE_ADDR = 32'h2300; + + /** + * Peripheral size in bytes for jtag device on soc_dbg_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_SIZE_BYTES = 32'h20; + + +endpackage diff --git a/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_soc_mbx_pkg.sv b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_soc_mbx_pkg.sv new file mode 100644 index 00000000000..27b0165cc23 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/rtl/autogen/top_darjeeling_no_ibex_soc_mbx_pkg.sv @@ -0,0 +1,125 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + +package top_darjeeling_no_ibex_soc_mbx_pkg; + /** + * Peripheral base address for soc device on mbx0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_BASE_ADDR = 32'h1465000; + + /** + * Peripheral size in bytes for soc device on mbx0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_BASE_ADDR = 32'h1465100; + + /** + * Peripheral size in bytes for soc device on mbx1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx2 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_BASE_ADDR = 32'h1465200; + + /** + * Peripheral size in bytes for soc device on mbx2 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx3 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_BASE_ADDR = 32'h1465300; + + /** + * Peripheral size in bytes for soc device on mbx3 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx4 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_BASE_ADDR = 32'h1465400; + + /** + * Peripheral size in bytes for soc device on mbx4 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx5 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_BASE_ADDR = 32'h1465500; + + /** + * Peripheral size in bytes for soc device on mbx5 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx6 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_BASE_ADDR = 32'h1496000; + + /** + * Peripheral size in bytes for soc device on mbx6 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx_pcie0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_BASE_ADDR = 32'h1460100; + + /** + * Peripheral size in bytes for soc device on mbx_pcie0 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for soc device on mbx_pcie1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_BASE_ADDR = 32'h1460200; + + /** + * Peripheral size in bytes for soc device on mbx_pcie1 in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_SIZE_BYTES = 32'h20; + + /** + * Peripheral base address for racl_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_BASE_ADDR = 32'h1461F00; + + /** + * Peripheral size in bytes for racl_ctrl in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_SIZE_BYTES = 32'h100; + + /** + * Peripheral base address for ac_range_check in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_BASE_ADDR = 32'h1464000; + + /** + * Peripheral size in bytes for ac_range_check in top darjeeling_no_ibex. + */ + parameter int unsigned TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_SIZE_BYTES = 32'h400; + + +endpackage diff --git a/hw/top_darjeeling_no_ibex/rtl/autogen/top_racl_pkg.sv b/hw/top_darjeeling_no_ibex/rtl/autogen/top_racl_pkg.sv new file mode 100644 index 00000000000..c714d7ebab3 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/rtl/autogen/top_racl_pkg.sv @@ -0,0 +1,124 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson \ +// -o hw/top_darjeeling_no_ibex/ \ +// --rnd_cnst_seed \ +// 1017106219537032642877583828875051302543807092889754935647094601236425074047 + + +package top_racl_pkg; + // Number of RACL policies used + parameter int unsigned NrRaclPolicies = 3; + + // RACL Policy selector bits + parameter int unsigned RaclPolicySelLen = prim_util_pkg::vbits(NrRaclPolicies); + + // RACL Policy selector type + typedef logic [RaclPolicySelLen-1:0] racl_policy_sel_t; + + // Enable TLUL error response on RACL denied accesses + parameter bit ErrorRsp = 1; + + // Number of RACL bits transferred + parameter int unsigned NrRaclBits = 4; + + // Number of CTN UID bits transferred + parameter int unsigned NrCtnUidBits = 5; + + // RACL role type binary encoded + typedef logic [NrRaclBits-1:0] racl_role_t; + + // CTN UID assigned the bus originator + typedef logic [NrCtnUidBits-1:0] ctn_uid_t; + + // RACL permission: A one-hot encoded role vector + typedef logic [(2**NrRaclBits)-1:0] racl_role_vec_t; + + // RACL policy containing a read and write permission + typedef struct packed { + racl_role_vec_t write_perm; // Write permission (upper bits) + racl_role_vec_t read_perm; // Read permission (lower bits) + } racl_policy_t; + + // RACL range used to protect a range of addresses with a RACL policy (e.g., for sram). + typedef struct packed { + logic [top_pkg::TL_AW-1:0] base; // Start address of range + logic [top_pkg::TL_AW-1:0] limit; // End address of range (inclusive) + racl_policy_sel_t policy_sel; // Policy selector + logic enable; // 0: Range is disabled, 1: Range is enabled + } racl_range_t; + + // RACL policy vector for distributing RACL policies from the RACL widget to the subscribing IP + typedef racl_policy_t [NrRaclPolicies-1:0] racl_policy_vec_t; + + // Default policy vector for unconnected RACL IPs + parameter racl_policy_vec_t RACL_POLICY_VEC_DEFAULT = '0; + + // Default policy selection range for unconnected RACL IPs + parameter racl_range_t RACL_RANGE_T_DEFAULT = '0; + + // Default ROT Private read policy value + parameter racl_role_vec_t RACL_POLICY_ROT_PRIVATE_RD = 16'h1; + + // Default ROT Private write policy value + parameter racl_role_vec_t RACL_POLICY_ROT_PRIVATE_WR = 16'h1; + + // RACL information logged in case of a denial + typedef struct packed { + logic valid; // Error information is valid + logic overflow; // Error overflow, More than 1 RACL error at a time + racl_role_t racl_role; + ctn_uid_t ctn_uid; + logic read_access; // 0: Write access, 1: Read access + logic [top_pkg::TL_AW-1:0] request_address; + } racl_error_log_t; + + // Extract RACL role bits from the TLUL reserved user bits + function automatic racl_role_t tlul_extract_racl_role_bits(logic [tlul_pkg::RsvdWidth-1:0] rsvd); + // Waive unused bits + logic unused_rsvd_bits; + unused_rsvd_bits = ^{rsvd}; + + return racl_role_t'(rsvd[8:5]); + endfunction + + // Extract CTN UID bits from the TLUL reserved user bits + function automatic ctn_uid_t tlul_extract_ctn_uid_bits(logic [tlul_pkg::RsvdWidth-1:0] rsvd); + // Waive unused bits + logic unused_rsvd_bits; + unused_rsvd_bits = ^{rsvd}; + + return ctn_uid_t'(rsvd[4:0]); + endfunction + + // Build a TLUL reserved user bit vector based on RACL role and CTN UID + function automatic logic [tlul_pkg::RsvdWidth-1:0] tlul_build_user_rsvd_vec(racl_role_t racl_role, + ctn_uid_t ctn_uid); + logic [tlul_pkg::RsvdWidth-1:0] rsvd; + rsvd = '0; + rsvd[8:5] = racl_role; + rsvd[4:0] = ctn_uid; + return rsvd; + endfunction + + /** + * RACL Roles + */ + parameter racl_role_t RACL_ROLE_ROT = 4'h0; + parameter racl_role_t RACL_ROLE_ROLE1 = 4'h1; + parameter racl_role_t RACL_ROLE_SOC = 4'h2; + + /** + * RACL Policy Selectors for group Null + */ + parameter racl_policy_sel_t RACL_POLICY_SEL_ALL_RD_WR = 0; + parameter racl_policy_sel_t RACL_POLICY_SEL_ROT_PRIVATE = 1; + parameter racl_policy_sel_t RACL_POLICY_SEL_SOC_ROT = 2; + + +endpackage diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/.clang-format b/hw/top_darjeeling_no_ibex/sw/autogen/.clang-format new file mode 100644 index 00000000000..7cb47a7a72e --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/.clang-format @@ -0,0 +1,4 @@ +# This disables clang-format on all files in the sw/autogen directory. +# This is needed so that git-clang-format and similar scripts work. +DisableFormat: true +SortIncludes: false diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/BUILD b/hw/top_darjeeling_no_ibex/sw/autogen/BUILD new file mode 100644 index 00000000000..2e61cbe83d7 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/BUILD @@ -0,0 +1,36 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------# +# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +# util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +# -o hw/top_darjeeling_no_ibex + +load("//rules:linker.bzl", "ld_library") +load("//hw/top:defs.bzl", "opentitan_require_top") + +package(default_visibility = ["//visibility:public"]) + +cc_library( + name = "top_darjeeling_no_ibex", + srcs = [ + "top_darjeeling_no_ibex.c", + ], + hdrs = [ + "top_darjeeling_no_ibex.h", + "top_darjeeling_no_ibex_memory.h", + ], + defines = ["OPENTITAN_IS_DARJEELING_NO_IBEX"], + target_compatible_with = opentitan_require_top("darjeeling_no_ibex"), +) + +ld_library( + name = "top_darjeeling_no_ibex_memory", + defines = [ + "OPENTITAN_TOP_MEMORY_LD=top_darjeeling_no_ibex_memory.ld", + "OPENTITAN_IS_DARJEELING_NO_IBEX", + ], + includes = ["top_darjeeling_no_ibex_memory.ld"], + target_compatible_with = opentitan_require_top("darjeeling_no_ibex"), +) diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/chip/mod.rs b/hw/top_darjeeling_no_ibex/sw/autogen/chip/mod.rs new file mode 100644 index 00000000000..aa30a9e0f83 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/chip/mod.rs @@ -0,0 +1,7 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +pub mod top_darjeeling_no_ibex; +pub mod top_darjeeling_no_ibex_soc_dbg; +pub mod top_darjeeling_no_ibex_soc_mbx; diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/chip/top_darjeeling_no_ibex.rs b/hw/top_darjeeling_no_ibex/sw/autogen/chip/top_darjeeling_no_ibex.rs new file mode 100644 index 00000000000..690a0a13c1a --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/chip/top_darjeeling_no_ibex.rs @@ -0,0 +1,2770 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +//! This file contains enums and consts for use within the Rust codebase. +//! +//! These definitions are for information that depends on the top-specific chip +//! configuration, which includes: +//! - Device Memory Information (for Peripherals and Memory) +//! - PLIC Interrupt ID Names and Source Mappings +//! - Alert ID Names and Source Mappings +//! - Pinmux Pin/Select Names +//! - Power Manager Wakeups + +use core::convert::TryFrom; + +/// Peripheral base address for uart0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const UART0_BASE_ADDR: usize = 0x30010000; + +/// Peripheral size for uart0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #UART0_BASE_ADDR and +/// `UART0_BASE_ADDR + UART0_SIZE_BYTES`. +pub const UART0_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for gpio in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const GPIO_BASE_ADDR: usize = 0x30000000; + +/// Peripheral size for gpio in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #GPIO_BASE_ADDR and +/// `GPIO_BASE_ADDR + GPIO_SIZE_BYTES`. +pub const GPIO_SIZE_BYTES: usize = 0x100; + +/// Peripheral base address for spi_device in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SPI_DEVICE_BASE_ADDR: usize = 0x30310000; + +/// Peripheral size for spi_device in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SPI_DEVICE_BASE_ADDR and +/// `SPI_DEVICE_BASE_ADDR + SPI_DEVICE_SIZE_BYTES`. +pub const SPI_DEVICE_SIZE_BYTES: usize = 0x2000; + +/// Peripheral base address for i2c0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const I2C0_BASE_ADDR: usize = 0x30080000; + +/// Peripheral size for i2c0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #I2C0_BASE_ADDR and +/// `I2C0_BASE_ADDR + I2C0_SIZE_BYTES`. +pub const I2C0_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on otp_ctrl in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const OTP_CTRL_CORE_BASE_ADDR: usize = 0x30130000; + +/// Peripheral size for core device on otp_ctrl in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #OTP_CTRL_CORE_BASE_ADDR and +/// `OTP_CTRL_CORE_BASE_ADDR + OTP_CTRL_CORE_SIZE_BYTES`. +pub const OTP_CTRL_CORE_SIZE_BYTES: usize = 0x8000; + +/// Peripheral base address for prim device on otp_macro in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const OTP_MACRO_PRIM_BASE_ADDR: usize = 0x30140000; + +/// Peripheral size for prim device on otp_macro in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #OTP_MACRO_PRIM_BASE_ADDR and +/// `OTP_MACRO_PRIM_BASE_ADDR + OTP_MACRO_PRIM_SIZE_BYTES`. +pub const OTP_MACRO_PRIM_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for regs device on lc_ctrl in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const LC_CTRL_REGS_BASE_ADDR: usize = 0x30150000; + +/// Peripheral size for regs device on lc_ctrl in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #LC_CTRL_REGS_BASE_ADDR and +/// `LC_CTRL_REGS_BASE_ADDR + LC_CTRL_REGS_SIZE_BYTES`. +pub const LC_CTRL_REGS_SIZE_BYTES: usize = 0x100; + +/// Peripheral base address for alert_handler in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ALERT_HANDLER_BASE_ADDR: usize = 0x30160000; + +/// Peripheral size for alert_handler in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ALERT_HANDLER_BASE_ADDR and +/// `ALERT_HANDLER_BASE_ADDR + ALERT_HANDLER_SIZE_BYTES`. +pub const ALERT_HANDLER_SIZE_BYTES: usize = 0x800; + +/// Peripheral base address for spi_host0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SPI_HOST0_BASE_ADDR: usize = 0x30300000; + +/// Peripheral size for spi_host0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SPI_HOST0_BASE_ADDR and +/// `SPI_HOST0_BASE_ADDR + SPI_HOST0_SIZE_BYTES`. +pub const SPI_HOST0_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for pwrmgr_aon in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const PWRMGR_AON_BASE_ADDR: usize = 0x30400000; + +/// Peripheral size for pwrmgr_aon in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #PWRMGR_AON_BASE_ADDR and +/// `PWRMGR_AON_BASE_ADDR + PWRMGR_AON_SIZE_BYTES`. +pub const PWRMGR_AON_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for rstmgr_aon in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RSTMGR_AON_BASE_ADDR: usize = 0x30410000; + +/// Peripheral size for rstmgr_aon in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RSTMGR_AON_BASE_ADDR and +/// `RSTMGR_AON_BASE_ADDR + RSTMGR_AON_SIZE_BYTES`. +pub const RSTMGR_AON_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for clkmgr_aon in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const CLKMGR_AON_BASE_ADDR: usize = 0x30420000; + +/// Peripheral size for clkmgr_aon in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #CLKMGR_AON_BASE_ADDR and +/// `CLKMGR_AON_BASE_ADDR + CLKMGR_AON_SIZE_BYTES`. +pub const CLKMGR_AON_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for pinmux_aon in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const PINMUX_AON_BASE_ADDR: usize = 0x30460000; + +/// Peripheral size for pinmux_aon in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #PINMUX_AON_BASE_ADDR and +/// `PINMUX_AON_BASE_ADDR + PINMUX_AON_SIZE_BYTES`. +pub const PINMUX_AON_SIZE_BYTES: usize = 0x800; + +/// Peripheral base address for aon_timer_aon in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const AON_TIMER_AON_BASE_ADDR: usize = 0x30470000; + +/// Peripheral size for aon_timer_aon in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #AON_TIMER_AON_BASE_ADDR and +/// `AON_TIMER_AON_BASE_ADDR + AON_TIMER_AON_SIZE_BYTES`. +pub const AON_TIMER_AON_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for ast in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const AST_BASE_ADDR: usize = 0x30480000; + +/// Peripheral size for ast in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #AST_BASE_ADDR and +/// `AST_BASE_ADDR + AST_SIZE_BYTES`. +pub const AST_SIZE_BYTES: usize = 0x400; + +/// Peripheral base address for core device on soc_proxy in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SOC_PROXY_CORE_BASE_ADDR: usize = 0x22030000; + +/// Peripheral size for core device on soc_proxy in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SOC_PROXY_CORE_BASE_ADDR and +/// `SOC_PROXY_CORE_BASE_ADDR + SOC_PROXY_CORE_SIZE_BYTES`. +pub const SOC_PROXY_CORE_SIZE_BYTES: usize = 0x10; + +/// Peripheral base address for ctn device on soc_proxy in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SOC_PROXY_CTN_BASE_ADDR: usize = 0x40000000; + +/// Peripheral size for ctn device on soc_proxy in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SOC_PROXY_CTN_BASE_ADDR and +/// `SOC_PROXY_CTN_BASE_ADDR + SOC_PROXY_CTN_SIZE_BYTES`. +pub const SOC_PROXY_CTN_SIZE_BYTES: usize = 0x40000000; + +/// Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_RET_AON_REGS_BASE_ADDR: usize = 0x30500000; + +/// Peripheral size for regs device on sram_ctrl_ret_aon in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_RET_AON_REGS_BASE_ADDR and +/// `SRAM_CTRL_RET_AON_REGS_BASE_ADDR + SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`. +pub const SRAM_CTRL_RET_AON_REGS_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_RET_AON_RAM_BASE_ADDR: usize = 0x30600000; + +/// Peripheral size for ram device on sram_ctrl_ret_aon in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_RET_AON_RAM_BASE_ADDR and +/// `SRAM_CTRL_RET_AON_RAM_BASE_ADDR + SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`. +pub const SRAM_CTRL_RET_AON_RAM_SIZE_BYTES: usize = 0x1000; + +/// Peripheral base address for rv_plic in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RV_PLIC_BASE_ADDR: usize = 0x28000000; + +/// Peripheral size for rv_plic in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RV_PLIC_BASE_ADDR and +/// `RV_PLIC_BASE_ADDR + RV_PLIC_SIZE_BYTES`. +pub const RV_PLIC_SIZE_BYTES: usize = 0x8000000; + +/// Peripheral base address for aes in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const AES_BASE_ADDR: usize = 0x21100000; + +/// Peripheral size for aes in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #AES_BASE_ADDR and +/// `AES_BASE_ADDR + AES_SIZE_BYTES`. +pub const AES_SIZE_BYTES: usize = 0x100; + +/// Peripheral base address for hmac in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const HMAC_BASE_ADDR: usize = 0x21110000; + +/// Peripheral size for hmac in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #HMAC_BASE_ADDR and +/// `HMAC_BASE_ADDR + HMAC_SIZE_BYTES`. +pub const HMAC_SIZE_BYTES: usize = 0x2000; + +/// Peripheral base address for kmac in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const KMAC_BASE_ADDR: usize = 0x21120000; + +/// Peripheral size for kmac in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #KMAC_BASE_ADDR and +/// `KMAC_BASE_ADDR + KMAC_SIZE_BYTES`. +pub const KMAC_SIZE_BYTES: usize = 0x1000; + +/// Peripheral base address for otbn in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const OTBN_BASE_ADDR: usize = 0x21130000; + +/// Peripheral size for otbn in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #OTBN_BASE_ADDR and +/// `OTBN_BASE_ADDR + OTBN_SIZE_BYTES`. +pub const OTBN_SIZE_BYTES: usize = 0x10000; + +/// Peripheral base address for keymgr_dpe in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const KEYMGR_DPE_BASE_ADDR: usize = 0x21140000; + +/// Peripheral size for keymgr_dpe in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #KEYMGR_DPE_BASE_ADDR and +/// `KEYMGR_DPE_BASE_ADDR + KEYMGR_DPE_SIZE_BYTES`. +pub const KEYMGR_DPE_SIZE_BYTES: usize = 0x100; + +/// Peripheral base address for csrng in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const CSRNG_BASE_ADDR: usize = 0x21150000; + +/// Peripheral size for csrng in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #CSRNG_BASE_ADDR and +/// `CSRNG_BASE_ADDR + CSRNG_SIZE_BYTES`. +pub const CSRNG_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for entropy_src in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ENTROPY_SRC_BASE_ADDR: usize = 0x21160000; + +/// Peripheral size for entropy_src in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ENTROPY_SRC_BASE_ADDR and +/// `ENTROPY_SRC_BASE_ADDR + ENTROPY_SRC_SIZE_BYTES`. +pub const ENTROPY_SRC_SIZE_BYTES: usize = 0x100; + +/// Peripheral base address for edn0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const EDN0_BASE_ADDR: usize = 0x21170000; + +/// Peripheral size for edn0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #EDN0_BASE_ADDR and +/// `EDN0_BASE_ADDR + EDN0_SIZE_BYTES`. +pub const EDN0_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for edn1 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const EDN1_BASE_ADDR: usize = 0x21180000; + +/// Peripheral size for edn1 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #EDN1_BASE_ADDR and +/// `EDN1_BASE_ADDR + EDN1_SIZE_BYTES`. +pub const EDN1_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for regs device on sram_ctrl_main in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_MAIN_REGS_BASE_ADDR: usize = 0x211C0000; + +/// Peripheral size for regs device on sram_ctrl_main in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_MAIN_REGS_BASE_ADDR and +/// `SRAM_CTRL_MAIN_REGS_BASE_ADDR + SRAM_CTRL_MAIN_REGS_SIZE_BYTES`. +pub const SRAM_CTRL_MAIN_REGS_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for ram device on sram_ctrl_main in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_MAIN_RAM_BASE_ADDR: usize = 0x10000000; + +/// Peripheral size for ram device on sram_ctrl_main in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_MAIN_RAM_BASE_ADDR and +/// `SRAM_CTRL_MAIN_RAM_BASE_ADDR + SRAM_CTRL_MAIN_RAM_SIZE_BYTES`. +pub const SRAM_CTRL_MAIN_RAM_SIZE_BYTES: usize = 0x10000; + +/// Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_MBOX_REGS_BASE_ADDR: usize = 0x211D0000; + +/// Peripheral size for regs device on sram_ctrl_mbox in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_MBOX_REGS_BASE_ADDR and +/// `SRAM_CTRL_MBOX_REGS_BASE_ADDR + SRAM_CTRL_MBOX_REGS_SIZE_BYTES`. +pub const SRAM_CTRL_MBOX_REGS_SIZE_BYTES: usize = 0x40; + +/// Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SRAM_CTRL_MBOX_RAM_BASE_ADDR: usize = 0x11000000; + +/// Peripheral size for ram device on sram_ctrl_mbox in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SRAM_CTRL_MBOX_RAM_BASE_ADDR and +/// `SRAM_CTRL_MBOX_RAM_BASE_ADDR + SRAM_CTRL_MBOX_RAM_SIZE_BYTES`. +pub const SRAM_CTRL_MBOX_RAM_SIZE_BYTES: usize = 0x1000; + +/// Peripheral base address for regs device on rom_ctrl0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ROM_CTRL0_REGS_BASE_ADDR: usize = 0x211E0000; + +/// Peripheral size for regs device on rom_ctrl0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ROM_CTRL0_REGS_BASE_ADDR and +/// `ROM_CTRL0_REGS_BASE_ADDR + ROM_CTRL0_REGS_SIZE_BYTES`. +pub const ROM_CTRL0_REGS_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for rom device on rom_ctrl0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ROM_CTRL0_ROM_BASE_ADDR: usize = 0x8000; + +/// Peripheral size for rom device on rom_ctrl0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ROM_CTRL0_ROM_BASE_ADDR and +/// `ROM_CTRL0_ROM_BASE_ADDR + ROM_CTRL0_ROM_SIZE_BYTES`. +pub const ROM_CTRL0_ROM_SIZE_BYTES: usize = 0x8000; + +/// Peripheral base address for regs device on rom_ctrl1 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ROM_CTRL1_REGS_BASE_ADDR: usize = 0x211E1000; + +/// Peripheral size for regs device on rom_ctrl1 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ROM_CTRL1_REGS_BASE_ADDR and +/// `ROM_CTRL1_REGS_BASE_ADDR + ROM_CTRL1_REGS_SIZE_BYTES`. +pub const ROM_CTRL1_REGS_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for rom device on rom_ctrl1 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const ROM_CTRL1_ROM_BASE_ADDR: usize = 0x20000; + +/// Peripheral size for rom device on rom_ctrl1 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #ROM_CTRL1_ROM_BASE_ADDR and +/// `ROM_CTRL1_ROM_BASE_ADDR + ROM_CTRL1_ROM_SIZE_BYTES`. +pub const ROM_CTRL1_ROM_SIZE_BYTES: usize = 0x10000; + +/// Peripheral base address for dma in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const DMA_BASE_ADDR: usize = 0x22010000; + +/// Peripheral size for dma in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #DMA_BASE_ADDR and +/// `DMA_BASE_ADDR + DMA_SIZE_BYTES`. +pub const DMA_SIZE_BYTES: usize = 0x200; + +/// Peripheral base address for core device on mbx0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX0_CORE_BASE_ADDR: usize = 0x22000000; + +/// Peripheral size for core device on mbx0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX0_CORE_BASE_ADDR and +/// `MBX0_CORE_BASE_ADDR + MBX0_CORE_SIZE_BYTES`. +pub const MBX0_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx1 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX1_CORE_BASE_ADDR: usize = 0x22000100; + +/// Peripheral size for core device on mbx1 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX1_CORE_BASE_ADDR and +/// `MBX1_CORE_BASE_ADDR + MBX1_CORE_SIZE_BYTES`. +pub const MBX1_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx2 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX2_CORE_BASE_ADDR: usize = 0x22000200; + +/// Peripheral size for core device on mbx2 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX2_CORE_BASE_ADDR and +/// `MBX2_CORE_BASE_ADDR + MBX2_CORE_SIZE_BYTES`. +pub const MBX2_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx3 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX3_CORE_BASE_ADDR: usize = 0x22000300; + +/// Peripheral size for core device on mbx3 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX3_CORE_BASE_ADDR and +/// `MBX3_CORE_BASE_ADDR + MBX3_CORE_SIZE_BYTES`. +pub const MBX3_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx4 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX4_CORE_BASE_ADDR: usize = 0x22000400; + +/// Peripheral size for core device on mbx4 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX4_CORE_BASE_ADDR and +/// `MBX4_CORE_BASE_ADDR + MBX4_CORE_SIZE_BYTES`. +pub const MBX4_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx5 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX5_CORE_BASE_ADDR: usize = 0x22000500; + +/// Peripheral size for core device on mbx5 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX5_CORE_BASE_ADDR and +/// `MBX5_CORE_BASE_ADDR + MBX5_CORE_SIZE_BYTES`. +pub const MBX5_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx6 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX6_CORE_BASE_ADDR: usize = 0x22000600; + +/// Peripheral size for core device on mbx6 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX6_CORE_BASE_ADDR and +/// `MBX6_CORE_BASE_ADDR + MBX6_CORE_SIZE_BYTES`. +pub const MBX6_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx_jtag in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX_JTAG_CORE_BASE_ADDR: usize = 0x22000800; + +/// Peripheral size for core device on mbx_jtag in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX_JTAG_CORE_BASE_ADDR and +/// `MBX_JTAG_CORE_BASE_ADDR + MBX_JTAG_CORE_SIZE_BYTES`. +pub const MBX_JTAG_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx_pcie0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX_PCIE0_CORE_BASE_ADDR: usize = 0x22040000; + +/// Peripheral size for core device on mbx_pcie0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX_PCIE0_CORE_BASE_ADDR and +/// `MBX_PCIE0_CORE_BASE_ADDR + MBX_PCIE0_CORE_SIZE_BYTES`. +pub const MBX_PCIE0_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on mbx_pcie1 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX_PCIE1_CORE_BASE_ADDR: usize = 0x22040100; + +/// Peripheral size for core device on mbx_pcie1 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX_PCIE1_CORE_BASE_ADDR and +/// `MBX_PCIE1_CORE_BASE_ADDR + MBX_PCIE1_CORE_SIZE_BYTES`. +pub const MBX_PCIE1_CORE_SIZE_BYTES: usize = 0x80; + +/// Peripheral base address for core device on soc_dbg_ctrl in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SOC_DBG_CTRL_CORE_BASE_ADDR: usize = 0x30170000; + +/// Peripheral size for core device on soc_dbg_ctrl in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SOC_DBG_CTRL_CORE_BASE_ADDR and +/// `SOC_DBG_CTRL_CORE_BASE_ADDR + SOC_DBG_CTRL_CORE_SIZE_BYTES`. +pub const SOC_DBG_CTRL_CORE_SIZE_BYTES: usize = 0x20; + +/// Memory base address for ctn in top darjeeling_no_ibex. +pub const CTN_BASE_ADDR: usize = 0x40000000; + +/// Memory size for ctn in top darjeeling_no_ibex. +pub const CTN_SIZE_BYTES: usize = 0x40000000; + +/// Memory base address for ram_ret_aon in top darjeeling_no_ibex. +pub const RAM_RET_AON_BASE_ADDR: usize = 0x30600000; + +/// Memory size for ram_ret_aon in top darjeeling_no_ibex. +pub const RAM_RET_AON_SIZE_BYTES: usize = 0x1000; + +/// Memory base address for ram_main in top darjeeling_no_ibex. +pub const RAM_MAIN_BASE_ADDR: usize = 0x10000000; + +/// Memory size for ram_main in top darjeeling_no_ibex. +pub const RAM_MAIN_SIZE_BYTES: usize = 0x10000; + +/// Memory base address for ram_mbox in top darjeeling_no_ibex. +pub const RAM_MBOX_BASE_ADDR: usize = 0x11000000; + +/// Memory size for ram_mbox in top darjeeling_no_ibex. +pub const RAM_MBOX_SIZE_BYTES: usize = 0x1000; + +/// Memory base address for rom0 in top darjeeling_no_ibex. +pub const ROM0_BASE_ADDR: usize = 0x8000; + +/// Memory size for rom0 in top darjeeling_no_ibex. +pub const ROM0_SIZE_BYTES: usize = 0x8000; + +/// Memory base address for rom1 in top darjeeling_no_ibex. +pub const ROM1_BASE_ADDR: usize = 0x20000; + +/// Memory size for rom1 in top darjeeling_no_ibex. +pub const ROM1_SIZE_BYTES: usize = 0x10000; + +/// PLIC Interrupt Source Peripheral. +/// +/// Enumeration used to determine which peripheral asserted the corresponding +/// interrupt. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PlicPeripheral { + /// Unknown Peripheral + Unknown = 0, + /// uart0 + Uart0 = 1, + /// gpio + Gpio = 2, + /// spi_device + SpiDevice = 3, + /// i2c0 + I2c0 = 4, + /// otp_ctrl + OtpCtrl = 5, + /// alert_handler + AlertHandler = 6, + /// spi_host0 + SpiHost0 = 7, + /// pwrmgr_aon + PwrmgrAon = 8, + /// aon_timer_aon + AonTimerAon = 9, + /// soc_proxy + SocProxy = 10, + /// hmac + Hmac = 11, + /// kmac + Kmac = 12, + /// otbn + Otbn = 13, + /// keymgr_dpe + KeymgrDpe = 14, + /// csrng + Csrng = 15, + /// entropy_src + EntropySrc = 16, + /// edn0 + Edn0 = 17, + /// edn1 + Edn1 = 18, + /// dma + Dma = 19, + /// mbx0 + Mbx0 = 20, + /// mbx1 + Mbx1 = 21, + /// mbx2 + Mbx2 = 22, + /// mbx3 + Mbx3 = 23, + /// mbx4 + Mbx4 = 24, + /// mbx5 + Mbx5 = 25, + /// mbx6 + Mbx6 = 26, + /// mbx_jtag + MbxJtag = 27, + /// mbx_pcie0 + MbxPcie0 = 28, + /// mbx_pcie1 + MbxPcie1 = 29, + /// racl_ctrl + RaclCtrl = 30, + /// ac_range_check + AcRangeCheck = 31, +} + +impl TryFrom for PlicPeripheral { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::Unknown), + 1 => Ok(Self::Uart0), + 2 => Ok(Self::Gpio), + 3 => Ok(Self::SpiDevice), + 4 => Ok(Self::I2c0), + 5 => Ok(Self::OtpCtrl), + 6 => Ok(Self::AlertHandler), + 7 => Ok(Self::SpiHost0), + 8 => Ok(Self::PwrmgrAon), + 9 => Ok(Self::AonTimerAon), + 10 => Ok(Self::SocProxy), + 11 => Ok(Self::Hmac), + 12 => Ok(Self::Kmac), + 13 => Ok(Self::Otbn), + 14 => Ok(Self::KeymgrDpe), + 15 => Ok(Self::Csrng), + 16 => Ok(Self::EntropySrc), + 17 => Ok(Self::Edn0), + 18 => Ok(Self::Edn1), + 19 => Ok(Self::Dma), + 20 => Ok(Self::Mbx0), + 21 => Ok(Self::Mbx1), + 22 => Ok(Self::Mbx2), + 23 => Ok(Self::Mbx3), + 24 => Ok(Self::Mbx4), + 25 => Ok(Self::Mbx5), + 26 => Ok(Self::Mbx6), + 27 => Ok(Self::MbxJtag), + 28 => Ok(Self::MbxPcie0), + 29 => Ok(Self::MbxPcie1), + 30 => Ok(Self::RaclCtrl), + 31 => Ok(Self::AcRangeCheck), + _ => Err(val), + } + } +} + +/// PLIC Interrupt Source. +/// +/// Enumeration of all PLIC interrupt sources. The interrupt sources belonging to +/// the same peripheral are guaranteed to be consecutive. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PlicIrqId { + /// No Interrupt + None = 0, + /// uart0_tx_watermark + Uart0TxWatermark = 1, + /// uart0_rx_watermark + Uart0RxWatermark = 2, + /// uart0_tx_done + Uart0TxDone = 3, + /// uart0_rx_overflow + Uart0RxOverflow = 4, + /// uart0_rx_frame_err + Uart0RxFrameErr = 5, + /// uart0_rx_break_err + Uart0RxBreakErr = 6, + /// uart0_rx_timeout + Uart0RxTimeout = 7, + /// uart0_rx_parity_err + Uart0RxParityErr = 8, + /// uart0_tx_empty + Uart0TxEmpty = 9, + /// gpio_gpio 0 + GpioGpio0 = 10, + /// gpio_gpio 1 + GpioGpio1 = 11, + /// gpio_gpio 2 + GpioGpio2 = 12, + /// gpio_gpio 3 + GpioGpio3 = 13, + /// gpio_gpio 4 + GpioGpio4 = 14, + /// gpio_gpio 5 + GpioGpio5 = 15, + /// gpio_gpio 6 + GpioGpio6 = 16, + /// gpio_gpio 7 + GpioGpio7 = 17, + /// gpio_gpio 8 + GpioGpio8 = 18, + /// gpio_gpio 9 + GpioGpio9 = 19, + /// gpio_gpio 10 + GpioGpio10 = 20, + /// gpio_gpio 11 + GpioGpio11 = 21, + /// gpio_gpio 12 + GpioGpio12 = 22, + /// gpio_gpio 13 + GpioGpio13 = 23, + /// gpio_gpio 14 + GpioGpio14 = 24, + /// gpio_gpio 15 + GpioGpio15 = 25, + /// gpio_gpio 16 + GpioGpio16 = 26, + /// gpio_gpio 17 + GpioGpio17 = 27, + /// gpio_gpio 18 + GpioGpio18 = 28, + /// gpio_gpio 19 + GpioGpio19 = 29, + /// gpio_gpio 20 + GpioGpio20 = 30, + /// gpio_gpio 21 + GpioGpio21 = 31, + /// gpio_gpio 22 + GpioGpio22 = 32, + /// gpio_gpio 23 + GpioGpio23 = 33, + /// gpio_gpio 24 + GpioGpio24 = 34, + /// gpio_gpio 25 + GpioGpio25 = 35, + /// gpio_gpio 26 + GpioGpio26 = 36, + /// gpio_gpio 27 + GpioGpio27 = 37, + /// gpio_gpio 28 + GpioGpio28 = 38, + /// gpio_gpio 29 + GpioGpio29 = 39, + /// gpio_gpio 30 + GpioGpio30 = 40, + /// gpio_gpio 31 + GpioGpio31 = 41, + /// spi_device_upload_cmdfifo_not_empty + SpiDeviceUploadCmdfifoNotEmpty = 42, + /// spi_device_upload_payload_not_empty + SpiDeviceUploadPayloadNotEmpty = 43, + /// spi_device_upload_payload_overflow + SpiDeviceUploadPayloadOverflow = 44, + /// spi_device_readbuf_watermark + SpiDeviceReadbufWatermark = 45, + /// spi_device_readbuf_flip + SpiDeviceReadbufFlip = 46, + /// spi_device_tpm_header_not_empty + SpiDeviceTpmHeaderNotEmpty = 47, + /// spi_device_tpm_rdfifo_cmd_end + SpiDeviceTpmRdfifoCmdEnd = 48, + /// spi_device_tpm_rdfifo_drop + SpiDeviceTpmRdfifoDrop = 49, + /// i2c0_fmt_threshold + I2c0FmtThreshold = 50, + /// i2c0_rx_threshold + I2c0RxThreshold = 51, + /// i2c0_acq_threshold + I2c0AcqThreshold = 52, + /// i2c0_rx_overflow + I2c0RxOverflow = 53, + /// i2c0_controller_halt + I2c0ControllerHalt = 54, + /// i2c0_scl_interference + I2c0SclInterference = 55, + /// i2c0_sda_interference + I2c0SdaInterference = 56, + /// i2c0_stretch_timeout + I2c0StretchTimeout = 57, + /// i2c0_sda_unstable + I2c0SdaUnstable = 58, + /// i2c0_cmd_complete + I2c0CmdComplete = 59, + /// i2c0_tx_stretch + I2c0TxStretch = 60, + /// i2c0_tx_threshold + I2c0TxThreshold = 61, + /// i2c0_acq_stretch + I2c0AcqStretch = 62, + /// i2c0_unexp_stop + I2c0UnexpStop = 63, + /// i2c0_host_timeout + I2c0HostTimeout = 64, + /// otp_ctrl_otp_operation_done + OtpCtrlOtpOperationDone = 65, + /// otp_ctrl_otp_error + OtpCtrlOtpError = 66, + /// alert_handler_classa + AlertHandlerClassa = 67, + /// alert_handler_classb + AlertHandlerClassb = 68, + /// alert_handler_classc + AlertHandlerClassc = 69, + /// alert_handler_classd + AlertHandlerClassd = 70, + /// spi_host0_error + SpiHost0Error = 71, + /// spi_host0_spi_event + SpiHost0SpiEvent = 72, + /// pwrmgr_aon_wakeup + PwrmgrAonWakeup = 73, + /// aon_timer_aon_wkup_timer_expired + AonTimerAonWkupTimerExpired = 74, + /// aon_timer_aon_wdog_timer_bark + AonTimerAonWdogTimerBark = 75, + /// soc_proxy_external 0 + SocProxyExternal0 = 76, + /// soc_proxy_external 1 + SocProxyExternal1 = 77, + /// soc_proxy_external 2 + SocProxyExternal2 = 78, + /// soc_proxy_external 3 + SocProxyExternal3 = 79, + /// soc_proxy_external 4 + SocProxyExternal4 = 80, + /// soc_proxy_external 5 + SocProxyExternal5 = 81, + /// soc_proxy_external 6 + SocProxyExternal6 = 82, + /// soc_proxy_external 7 + SocProxyExternal7 = 83, + /// soc_proxy_external 8 + SocProxyExternal8 = 84, + /// soc_proxy_external 9 + SocProxyExternal9 = 85, + /// soc_proxy_external 10 + SocProxyExternal10 = 86, + /// soc_proxy_external 11 + SocProxyExternal11 = 87, + /// soc_proxy_external 12 + SocProxyExternal12 = 88, + /// soc_proxy_external 13 + SocProxyExternal13 = 89, + /// soc_proxy_external 14 + SocProxyExternal14 = 90, + /// soc_proxy_external 15 + SocProxyExternal15 = 91, + /// soc_proxy_external 16 + SocProxyExternal16 = 92, + /// soc_proxy_external 17 + SocProxyExternal17 = 93, + /// soc_proxy_external 18 + SocProxyExternal18 = 94, + /// soc_proxy_external 19 + SocProxyExternal19 = 95, + /// soc_proxy_external 20 + SocProxyExternal20 = 96, + /// soc_proxy_external 21 + SocProxyExternal21 = 97, + /// soc_proxy_external 22 + SocProxyExternal22 = 98, + /// soc_proxy_external 23 + SocProxyExternal23 = 99, + /// soc_proxy_external 24 + SocProxyExternal24 = 100, + /// soc_proxy_external 25 + SocProxyExternal25 = 101, + /// soc_proxy_external 26 + SocProxyExternal26 = 102, + /// soc_proxy_external 27 + SocProxyExternal27 = 103, + /// soc_proxy_external 28 + SocProxyExternal28 = 104, + /// soc_proxy_external 29 + SocProxyExternal29 = 105, + /// soc_proxy_external 30 + SocProxyExternal30 = 106, + /// soc_proxy_external 31 + SocProxyExternal31 = 107, + /// hmac_hmac_done + HmacHmacDone = 108, + /// hmac_fifo_empty + HmacFifoEmpty = 109, + /// hmac_hmac_err + HmacHmacErr = 110, + /// kmac_kmac_done + KmacKmacDone = 111, + /// kmac_fifo_empty + KmacFifoEmpty = 112, + /// kmac_kmac_err + KmacKmacErr = 113, + /// otbn_done + OtbnDone = 114, + /// keymgr_dpe_op_done + KeymgrDpeOpDone = 115, + /// csrng_cs_cmd_req_done + CsrngCsCmdReqDone = 116, + /// csrng_cs_entropy_req + CsrngCsEntropyReq = 117, + /// csrng_cs_hw_inst_exc + CsrngCsHwInstExc = 118, + /// csrng_cs_fatal_err + CsrngCsFatalErr = 119, + /// entropy_src_es_entropy_valid + EntropySrcEsEntropyValid = 120, + /// entropy_src_es_health_test_failed + EntropySrcEsHealthTestFailed = 121, + /// entropy_src_es_observe_fifo_ready + EntropySrcEsObserveFifoReady = 122, + /// entropy_src_es_fatal_err + EntropySrcEsFatalErr = 123, + /// edn0_edn_cmd_req_done + Edn0EdnCmdReqDone = 124, + /// edn0_edn_fatal_err + Edn0EdnFatalErr = 125, + /// edn1_edn_cmd_req_done + Edn1EdnCmdReqDone = 126, + /// edn1_edn_fatal_err + Edn1EdnFatalErr = 127, + /// dma_dma_done + DmaDmaDone = 128, + /// dma_dma_chunk_done + DmaDmaChunkDone = 129, + /// dma_dma_error + DmaDmaError = 130, + /// mbx0_mbx_ready + Mbx0MbxReady = 131, + /// mbx0_mbx_abort + Mbx0MbxAbort = 132, + /// mbx0_mbx_error + Mbx0MbxError = 133, + /// mbx1_mbx_ready + Mbx1MbxReady = 134, + /// mbx1_mbx_abort + Mbx1MbxAbort = 135, + /// mbx1_mbx_error + Mbx1MbxError = 136, + /// mbx2_mbx_ready + Mbx2MbxReady = 137, + /// mbx2_mbx_abort + Mbx2MbxAbort = 138, + /// mbx2_mbx_error + Mbx2MbxError = 139, + /// mbx3_mbx_ready + Mbx3MbxReady = 140, + /// mbx3_mbx_abort + Mbx3MbxAbort = 141, + /// mbx3_mbx_error + Mbx3MbxError = 142, + /// mbx4_mbx_ready + Mbx4MbxReady = 143, + /// mbx4_mbx_abort + Mbx4MbxAbort = 144, + /// mbx4_mbx_error + Mbx4MbxError = 145, + /// mbx5_mbx_ready + Mbx5MbxReady = 146, + /// mbx5_mbx_abort + Mbx5MbxAbort = 147, + /// mbx5_mbx_error + Mbx5MbxError = 148, + /// mbx6_mbx_ready + Mbx6MbxReady = 149, + /// mbx6_mbx_abort + Mbx6MbxAbort = 150, + /// mbx6_mbx_error + Mbx6MbxError = 151, + /// mbx_jtag_mbx_ready + MbxJtagMbxReady = 152, + /// mbx_jtag_mbx_abort + MbxJtagMbxAbort = 153, + /// mbx_jtag_mbx_error + MbxJtagMbxError = 154, + /// mbx_pcie0_mbx_ready + MbxPcie0MbxReady = 155, + /// mbx_pcie0_mbx_abort + MbxPcie0MbxAbort = 156, + /// mbx_pcie0_mbx_error + MbxPcie0MbxError = 157, + /// mbx_pcie1_mbx_ready + MbxPcie1MbxReady = 158, + /// mbx_pcie1_mbx_abort + MbxPcie1MbxAbort = 159, + /// mbx_pcie1_mbx_error + MbxPcie1MbxError = 160, + /// racl_ctrl_racl_error + RaclCtrlRaclError = 161, + /// ac_range_check_deny_cnt_reached + AcRangeCheckDenyCntReached = 162, +} + +impl TryFrom for PlicIrqId { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::None), + 1 => Ok(Self::Uart0TxWatermark), + 2 => Ok(Self::Uart0RxWatermark), + 3 => Ok(Self::Uart0TxDone), + 4 => Ok(Self::Uart0RxOverflow), + 5 => Ok(Self::Uart0RxFrameErr), + 6 => Ok(Self::Uart0RxBreakErr), + 7 => Ok(Self::Uart0RxTimeout), + 8 => Ok(Self::Uart0RxParityErr), + 9 => Ok(Self::Uart0TxEmpty), + 10 => Ok(Self::GpioGpio0), + 11 => Ok(Self::GpioGpio1), + 12 => Ok(Self::GpioGpio2), + 13 => Ok(Self::GpioGpio3), + 14 => Ok(Self::GpioGpio4), + 15 => Ok(Self::GpioGpio5), + 16 => Ok(Self::GpioGpio6), + 17 => Ok(Self::GpioGpio7), + 18 => Ok(Self::GpioGpio8), + 19 => Ok(Self::GpioGpio9), + 20 => Ok(Self::GpioGpio10), + 21 => Ok(Self::GpioGpio11), + 22 => Ok(Self::GpioGpio12), + 23 => Ok(Self::GpioGpio13), + 24 => Ok(Self::GpioGpio14), + 25 => Ok(Self::GpioGpio15), + 26 => Ok(Self::GpioGpio16), + 27 => Ok(Self::GpioGpio17), + 28 => Ok(Self::GpioGpio18), + 29 => Ok(Self::GpioGpio19), + 30 => Ok(Self::GpioGpio20), + 31 => Ok(Self::GpioGpio21), + 32 => Ok(Self::GpioGpio22), + 33 => Ok(Self::GpioGpio23), + 34 => Ok(Self::GpioGpio24), + 35 => Ok(Self::GpioGpio25), + 36 => Ok(Self::GpioGpio26), + 37 => Ok(Self::GpioGpio27), + 38 => Ok(Self::GpioGpio28), + 39 => Ok(Self::GpioGpio29), + 40 => Ok(Self::GpioGpio30), + 41 => Ok(Self::GpioGpio31), + 42 => Ok(Self::SpiDeviceUploadCmdfifoNotEmpty), + 43 => Ok(Self::SpiDeviceUploadPayloadNotEmpty), + 44 => Ok(Self::SpiDeviceUploadPayloadOverflow), + 45 => Ok(Self::SpiDeviceReadbufWatermark), + 46 => Ok(Self::SpiDeviceReadbufFlip), + 47 => Ok(Self::SpiDeviceTpmHeaderNotEmpty), + 48 => Ok(Self::SpiDeviceTpmRdfifoCmdEnd), + 49 => Ok(Self::SpiDeviceTpmRdfifoDrop), + 50 => Ok(Self::I2c0FmtThreshold), + 51 => Ok(Self::I2c0RxThreshold), + 52 => Ok(Self::I2c0AcqThreshold), + 53 => Ok(Self::I2c0RxOverflow), + 54 => Ok(Self::I2c0ControllerHalt), + 55 => Ok(Self::I2c0SclInterference), + 56 => Ok(Self::I2c0SdaInterference), + 57 => Ok(Self::I2c0StretchTimeout), + 58 => Ok(Self::I2c0SdaUnstable), + 59 => Ok(Self::I2c0CmdComplete), + 60 => Ok(Self::I2c0TxStretch), + 61 => Ok(Self::I2c0TxThreshold), + 62 => Ok(Self::I2c0AcqStretch), + 63 => Ok(Self::I2c0UnexpStop), + 64 => Ok(Self::I2c0HostTimeout), + 65 => Ok(Self::OtpCtrlOtpOperationDone), + 66 => Ok(Self::OtpCtrlOtpError), + 67 => Ok(Self::AlertHandlerClassa), + 68 => Ok(Self::AlertHandlerClassb), + 69 => Ok(Self::AlertHandlerClassc), + 70 => Ok(Self::AlertHandlerClassd), + 71 => Ok(Self::SpiHost0Error), + 72 => Ok(Self::SpiHost0SpiEvent), + 73 => Ok(Self::PwrmgrAonWakeup), + 74 => Ok(Self::AonTimerAonWkupTimerExpired), + 75 => Ok(Self::AonTimerAonWdogTimerBark), + 76 => Ok(Self::SocProxyExternal0), + 77 => Ok(Self::SocProxyExternal1), + 78 => Ok(Self::SocProxyExternal2), + 79 => Ok(Self::SocProxyExternal3), + 80 => Ok(Self::SocProxyExternal4), + 81 => Ok(Self::SocProxyExternal5), + 82 => Ok(Self::SocProxyExternal6), + 83 => Ok(Self::SocProxyExternal7), + 84 => Ok(Self::SocProxyExternal8), + 85 => Ok(Self::SocProxyExternal9), + 86 => Ok(Self::SocProxyExternal10), + 87 => Ok(Self::SocProxyExternal11), + 88 => Ok(Self::SocProxyExternal12), + 89 => Ok(Self::SocProxyExternal13), + 90 => Ok(Self::SocProxyExternal14), + 91 => Ok(Self::SocProxyExternal15), + 92 => Ok(Self::SocProxyExternal16), + 93 => Ok(Self::SocProxyExternal17), + 94 => Ok(Self::SocProxyExternal18), + 95 => Ok(Self::SocProxyExternal19), + 96 => Ok(Self::SocProxyExternal20), + 97 => Ok(Self::SocProxyExternal21), + 98 => Ok(Self::SocProxyExternal22), + 99 => Ok(Self::SocProxyExternal23), + 100 => Ok(Self::SocProxyExternal24), + 101 => Ok(Self::SocProxyExternal25), + 102 => Ok(Self::SocProxyExternal26), + 103 => Ok(Self::SocProxyExternal27), + 104 => Ok(Self::SocProxyExternal28), + 105 => Ok(Self::SocProxyExternal29), + 106 => Ok(Self::SocProxyExternal30), + 107 => Ok(Self::SocProxyExternal31), + 108 => Ok(Self::HmacHmacDone), + 109 => Ok(Self::HmacFifoEmpty), + 110 => Ok(Self::HmacHmacErr), + 111 => Ok(Self::KmacKmacDone), + 112 => Ok(Self::KmacFifoEmpty), + 113 => Ok(Self::KmacKmacErr), + 114 => Ok(Self::OtbnDone), + 115 => Ok(Self::KeymgrDpeOpDone), + 116 => Ok(Self::CsrngCsCmdReqDone), + 117 => Ok(Self::CsrngCsEntropyReq), + 118 => Ok(Self::CsrngCsHwInstExc), + 119 => Ok(Self::CsrngCsFatalErr), + 120 => Ok(Self::EntropySrcEsEntropyValid), + 121 => Ok(Self::EntropySrcEsHealthTestFailed), + 122 => Ok(Self::EntropySrcEsObserveFifoReady), + 123 => Ok(Self::EntropySrcEsFatalErr), + 124 => Ok(Self::Edn0EdnCmdReqDone), + 125 => Ok(Self::Edn0EdnFatalErr), + 126 => Ok(Self::Edn1EdnCmdReqDone), + 127 => Ok(Self::Edn1EdnFatalErr), + 128 => Ok(Self::DmaDmaDone), + 129 => Ok(Self::DmaDmaChunkDone), + 130 => Ok(Self::DmaDmaError), + 131 => Ok(Self::Mbx0MbxReady), + 132 => Ok(Self::Mbx0MbxAbort), + 133 => Ok(Self::Mbx0MbxError), + 134 => Ok(Self::Mbx1MbxReady), + 135 => Ok(Self::Mbx1MbxAbort), + 136 => Ok(Self::Mbx1MbxError), + 137 => Ok(Self::Mbx2MbxReady), + 138 => Ok(Self::Mbx2MbxAbort), + 139 => Ok(Self::Mbx2MbxError), + 140 => Ok(Self::Mbx3MbxReady), + 141 => Ok(Self::Mbx3MbxAbort), + 142 => Ok(Self::Mbx3MbxError), + 143 => Ok(Self::Mbx4MbxReady), + 144 => Ok(Self::Mbx4MbxAbort), + 145 => Ok(Self::Mbx4MbxError), + 146 => Ok(Self::Mbx5MbxReady), + 147 => Ok(Self::Mbx5MbxAbort), + 148 => Ok(Self::Mbx5MbxError), + 149 => Ok(Self::Mbx6MbxReady), + 150 => Ok(Self::Mbx6MbxAbort), + 151 => Ok(Self::Mbx6MbxError), + 152 => Ok(Self::MbxJtagMbxReady), + 153 => Ok(Self::MbxJtagMbxAbort), + 154 => Ok(Self::MbxJtagMbxError), + 155 => Ok(Self::MbxPcie0MbxReady), + 156 => Ok(Self::MbxPcie0MbxAbort), + 157 => Ok(Self::MbxPcie0MbxError), + 158 => Ok(Self::MbxPcie1MbxReady), + 159 => Ok(Self::MbxPcie1MbxAbort), + 160 => Ok(Self::MbxPcie1MbxError), + 161 => Ok(Self::RaclCtrlRaclError), + 162 => Ok(Self::AcRangeCheckDenyCntReached), + _ => Err(val), + } + } +} + +/// PLIC Interrupt Target. +/// +/// Enumeration used to determine which set of IE, CC, threshold registers to +/// access for a given interrupt target. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PlicTarget { + /// Ibex Core 0 + Ibex0 = 0, +} + +/// PLIC Interrupt Source to Peripheral Map +/// +/// This array is a mapping from `PlicIrqId` to +/// `PlicPeripheral`. +pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 163] = [ + // None -> PlicPeripheral::Unknown + PlicPeripheral::Unknown, + // Uart0TxWatermark -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxWatermark -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0TxDone -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxOverflow -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxFrameErr -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxBreakErr -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxTimeout -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0RxParityErr -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // Uart0TxEmpty -> PlicPeripheral::Uart0 + PlicPeripheral::Uart0, + // GpioGpio0 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio1 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio2 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio3 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio4 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio5 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio6 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio7 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio8 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio9 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio10 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio11 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio12 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio13 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio14 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio15 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio16 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio17 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio18 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio19 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio20 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio21 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio22 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio23 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio24 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio25 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio26 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio27 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio28 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio29 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio30 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // GpioGpio31 -> PlicPeripheral::Gpio + PlicPeripheral::Gpio, + // SpiDeviceUploadCmdfifoNotEmpty -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceUploadPayloadNotEmpty -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceUploadPayloadOverflow -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceReadbufWatermark -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceReadbufFlip -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceTpmHeaderNotEmpty -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceTpmRdfifoCmdEnd -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // SpiDeviceTpmRdfifoDrop -> PlicPeripheral::SpiDevice + PlicPeripheral::SpiDevice, + // I2c0FmtThreshold -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0RxThreshold -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0AcqThreshold -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0RxOverflow -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0ControllerHalt -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0SclInterference -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0SdaInterference -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0StretchTimeout -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0SdaUnstable -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0CmdComplete -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0TxStretch -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0TxThreshold -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0AcqStretch -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0UnexpStop -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // I2c0HostTimeout -> PlicPeripheral::I2c0 + PlicPeripheral::I2c0, + // OtpCtrlOtpOperationDone -> PlicPeripheral::OtpCtrl + PlicPeripheral::OtpCtrl, + // OtpCtrlOtpError -> PlicPeripheral::OtpCtrl + PlicPeripheral::OtpCtrl, + // AlertHandlerClassa -> PlicPeripheral::AlertHandler + PlicPeripheral::AlertHandler, + // AlertHandlerClassb -> PlicPeripheral::AlertHandler + PlicPeripheral::AlertHandler, + // AlertHandlerClassc -> PlicPeripheral::AlertHandler + PlicPeripheral::AlertHandler, + // AlertHandlerClassd -> PlicPeripheral::AlertHandler + PlicPeripheral::AlertHandler, + // SpiHost0Error -> PlicPeripheral::SpiHost0 + PlicPeripheral::SpiHost0, + // SpiHost0SpiEvent -> PlicPeripheral::SpiHost0 + PlicPeripheral::SpiHost0, + // PwrmgrAonWakeup -> PlicPeripheral::PwrmgrAon + PlicPeripheral::PwrmgrAon, + // AonTimerAonWkupTimerExpired -> PlicPeripheral::AonTimerAon + PlicPeripheral::AonTimerAon, + // AonTimerAonWdogTimerBark -> PlicPeripheral::AonTimerAon + PlicPeripheral::AonTimerAon, + // SocProxyExternal0 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal1 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal2 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal3 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal4 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal5 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal6 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal7 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal8 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal9 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal10 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal11 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal12 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal13 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal14 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal15 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal16 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal17 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal18 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal19 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal20 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal21 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal22 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal23 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal24 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal25 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal26 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal27 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal28 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal29 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal30 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // SocProxyExternal31 -> PlicPeripheral::SocProxy + PlicPeripheral::SocProxy, + // HmacHmacDone -> PlicPeripheral::Hmac + PlicPeripheral::Hmac, + // HmacFifoEmpty -> PlicPeripheral::Hmac + PlicPeripheral::Hmac, + // HmacHmacErr -> PlicPeripheral::Hmac + PlicPeripheral::Hmac, + // KmacKmacDone -> PlicPeripheral::Kmac + PlicPeripheral::Kmac, + // KmacFifoEmpty -> PlicPeripheral::Kmac + PlicPeripheral::Kmac, + // KmacKmacErr -> PlicPeripheral::Kmac + PlicPeripheral::Kmac, + // OtbnDone -> PlicPeripheral::Otbn + PlicPeripheral::Otbn, + // KeymgrDpeOpDone -> PlicPeripheral::KeymgrDpe + PlicPeripheral::KeymgrDpe, + // CsrngCsCmdReqDone -> PlicPeripheral::Csrng + PlicPeripheral::Csrng, + // CsrngCsEntropyReq -> PlicPeripheral::Csrng + PlicPeripheral::Csrng, + // CsrngCsHwInstExc -> PlicPeripheral::Csrng + PlicPeripheral::Csrng, + // CsrngCsFatalErr -> PlicPeripheral::Csrng + PlicPeripheral::Csrng, + // EntropySrcEsEntropyValid -> PlicPeripheral::EntropySrc + PlicPeripheral::EntropySrc, + // EntropySrcEsHealthTestFailed -> PlicPeripheral::EntropySrc + PlicPeripheral::EntropySrc, + // EntropySrcEsObserveFifoReady -> PlicPeripheral::EntropySrc + PlicPeripheral::EntropySrc, + // EntropySrcEsFatalErr -> PlicPeripheral::EntropySrc + PlicPeripheral::EntropySrc, + // Edn0EdnCmdReqDone -> PlicPeripheral::Edn0 + PlicPeripheral::Edn0, + // Edn0EdnFatalErr -> PlicPeripheral::Edn0 + PlicPeripheral::Edn0, + // Edn1EdnCmdReqDone -> PlicPeripheral::Edn1 + PlicPeripheral::Edn1, + // Edn1EdnFatalErr -> PlicPeripheral::Edn1 + PlicPeripheral::Edn1, + // DmaDmaDone -> PlicPeripheral::Dma + PlicPeripheral::Dma, + // DmaDmaChunkDone -> PlicPeripheral::Dma + PlicPeripheral::Dma, + // DmaDmaError -> PlicPeripheral::Dma + PlicPeripheral::Dma, + // Mbx0MbxReady -> PlicPeripheral::Mbx0 + PlicPeripheral::Mbx0, + // Mbx0MbxAbort -> PlicPeripheral::Mbx0 + PlicPeripheral::Mbx0, + // Mbx0MbxError -> PlicPeripheral::Mbx0 + PlicPeripheral::Mbx0, + // Mbx1MbxReady -> PlicPeripheral::Mbx1 + PlicPeripheral::Mbx1, + // Mbx1MbxAbort -> PlicPeripheral::Mbx1 + PlicPeripheral::Mbx1, + // Mbx1MbxError -> PlicPeripheral::Mbx1 + PlicPeripheral::Mbx1, + // Mbx2MbxReady -> PlicPeripheral::Mbx2 + PlicPeripheral::Mbx2, + // Mbx2MbxAbort -> PlicPeripheral::Mbx2 + PlicPeripheral::Mbx2, + // Mbx2MbxError -> PlicPeripheral::Mbx2 + PlicPeripheral::Mbx2, + // Mbx3MbxReady -> PlicPeripheral::Mbx3 + PlicPeripheral::Mbx3, + // Mbx3MbxAbort -> PlicPeripheral::Mbx3 + PlicPeripheral::Mbx3, + // Mbx3MbxError -> PlicPeripheral::Mbx3 + PlicPeripheral::Mbx3, + // Mbx4MbxReady -> PlicPeripheral::Mbx4 + PlicPeripheral::Mbx4, + // Mbx4MbxAbort -> PlicPeripheral::Mbx4 + PlicPeripheral::Mbx4, + // Mbx4MbxError -> PlicPeripheral::Mbx4 + PlicPeripheral::Mbx4, + // Mbx5MbxReady -> PlicPeripheral::Mbx5 + PlicPeripheral::Mbx5, + // Mbx5MbxAbort -> PlicPeripheral::Mbx5 + PlicPeripheral::Mbx5, + // Mbx5MbxError -> PlicPeripheral::Mbx5 + PlicPeripheral::Mbx5, + // Mbx6MbxReady -> PlicPeripheral::Mbx6 + PlicPeripheral::Mbx6, + // Mbx6MbxAbort -> PlicPeripheral::Mbx6 + PlicPeripheral::Mbx6, + // Mbx6MbxError -> PlicPeripheral::Mbx6 + PlicPeripheral::Mbx6, + // MbxJtagMbxReady -> PlicPeripheral::MbxJtag + PlicPeripheral::MbxJtag, + // MbxJtagMbxAbort -> PlicPeripheral::MbxJtag + PlicPeripheral::MbxJtag, + // MbxJtagMbxError -> PlicPeripheral::MbxJtag + PlicPeripheral::MbxJtag, + // MbxPcie0MbxReady -> PlicPeripheral::MbxPcie0 + PlicPeripheral::MbxPcie0, + // MbxPcie0MbxAbort -> PlicPeripheral::MbxPcie0 + PlicPeripheral::MbxPcie0, + // MbxPcie0MbxError -> PlicPeripheral::MbxPcie0 + PlicPeripheral::MbxPcie0, + // MbxPcie1MbxReady -> PlicPeripheral::MbxPcie1 + PlicPeripheral::MbxPcie1, + // MbxPcie1MbxAbort -> PlicPeripheral::MbxPcie1 + PlicPeripheral::MbxPcie1, + // MbxPcie1MbxError -> PlicPeripheral::MbxPcie1 + PlicPeripheral::MbxPcie1, + // RaclCtrlRaclError -> PlicPeripheral::RaclCtrl + PlicPeripheral::RaclCtrl, + // AcRangeCheckDenyCntReached -> PlicPeripheral::AcRangeCheck + PlicPeripheral::AcRangeCheck, +]; + +/// Alert Handler Source Peripheral. +/// +/// Enumeration used to determine which peripheral asserted the corresponding +/// alert. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum AlertPeripheral { + /// External Peripheral + External = 0, + /// uart0 + Uart0 = 1, + /// gpio + Gpio = 2, + /// spi_device + SpiDevice = 3, + /// i2c0 + I2c0 = 4, + /// otp_ctrl + OtpCtrl = 5, + /// lc_ctrl + LcCtrl = 6, + /// spi_host0 + SpiHost0 = 7, + /// pwrmgr_aon + PwrmgrAon = 8, + /// rstmgr_aon + RstmgrAon = 9, + /// clkmgr_aon + ClkmgrAon = 10, + /// pinmux_aon + PinmuxAon = 11, + /// aon_timer_aon + AonTimerAon = 12, + /// soc_proxy + SocProxy = 13, + /// sram_ctrl_ret_aon + SramCtrlRetAon = 14, + /// rv_plic + RvPlic = 15, + /// aes + Aes = 16, + /// hmac + Hmac = 17, + /// kmac + Kmac = 18, + /// otbn + Otbn = 19, + /// keymgr_dpe + KeymgrDpe = 20, + /// csrng + Csrng = 21, + /// entropy_src + EntropySrc = 22, + /// edn0 + Edn0 = 23, + /// edn1 + Edn1 = 24, + /// sram_ctrl_main + SramCtrlMain = 25, + /// sram_ctrl_mbox + SramCtrlMbox = 26, + /// rom_ctrl0 + RomCtrl0 = 27, + /// rom_ctrl1 + RomCtrl1 = 28, + /// dma + Dma = 29, + /// mbx0 + Mbx0 = 30, + /// mbx1 + Mbx1 = 31, + /// mbx2 + Mbx2 = 32, + /// mbx3 + Mbx3 = 33, + /// mbx4 + Mbx4 = 34, + /// mbx5 + Mbx5 = 35, + /// mbx6 + Mbx6 = 36, + /// mbx_jtag + MbxJtag = 37, + /// mbx_pcie0 + MbxPcie0 = 38, + /// mbx_pcie1 + MbxPcie1 = 39, + /// soc_dbg_ctrl + SocDbgCtrl = 40, + /// racl_ctrl + RaclCtrl = 41, + /// ac_range_check + AcRangeCheck = 42, +} + +/// Alert Handler Alert Source. +/// +/// Enumeration of all Alert Handler Alert Sources. The alert sources belonging to +/// the same peripheral are guaranteed to be consecutive. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum AlertId { + /// uart0_fatal_fault + Uart0FatalFault = 0, + /// gpio_fatal_fault + GpioFatalFault = 1, + /// spi_device_fatal_fault + SpiDeviceFatalFault = 2, + /// i2c0_fatal_fault + I2c0FatalFault = 3, + /// otp_ctrl_fatal_macro_error + OtpCtrlFatalMacroError = 4, + /// otp_ctrl_fatal_check_error + OtpCtrlFatalCheckError = 5, + /// otp_ctrl_fatal_bus_integ_error + OtpCtrlFatalBusIntegError = 6, + /// otp_ctrl_fatal_prim_otp_alert + OtpCtrlFatalPrimOtpAlert = 7, + /// otp_ctrl_recov_prim_otp_alert + OtpCtrlRecovPrimOtpAlert = 8, + /// lc_ctrl_fatal_prog_error + LcCtrlFatalProgError = 9, + /// lc_ctrl_fatal_state_error + LcCtrlFatalStateError = 10, + /// lc_ctrl_fatal_bus_integ_error + LcCtrlFatalBusIntegError = 11, + /// spi_host0_fatal_fault + SpiHost0FatalFault = 12, + /// pwrmgr_aon_fatal_fault + PwrmgrAonFatalFault = 13, + /// rstmgr_aon_fatal_fault + RstmgrAonFatalFault = 14, + /// rstmgr_aon_fatal_cnsty_fault + RstmgrAonFatalCnstyFault = 15, + /// clkmgr_aon_recov_fault + ClkmgrAonRecovFault = 16, + /// clkmgr_aon_fatal_fault + ClkmgrAonFatalFault = 17, + /// pinmux_aon_fatal_fault + PinmuxAonFatalFault = 18, + /// aon_timer_aon_fatal_fault + AonTimerAonFatalFault = 19, + /// soc_proxy_fatal_alert_intg + SocProxyFatalAlertIntg = 20, + /// soc_proxy_fatal_alert_external_0 + SocProxyFatalAlertExternal0 = 21, + /// soc_proxy_fatal_alert_external_1 + SocProxyFatalAlertExternal1 = 22, + /// soc_proxy_fatal_alert_external_2 + SocProxyFatalAlertExternal2 = 23, + /// soc_proxy_fatal_alert_external_3 + SocProxyFatalAlertExternal3 = 24, + /// soc_proxy_fatal_alert_external_4 + SocProxyFatalAlertExternal4 = 25, + /// soc_proxy_fatal_alert_external_5 + SocProxyFatalAlertExternal5 = 26, + /// soc_proxy_fatal_alert_external_6 + SocProxyFatalAlertExternal6 = 27, + /// soc_proxy_fatal_alert_external_7 + SocProxyFatalAlertExternal7 = 28, + /// soc_proxy_fatal_alert_external_8 + SocProxyFatalAlertExternal8 = 29, + /// soc_proxy_fatal_alert_external_9 + SocProxyFatalAlertExternal9 = 30, + /// soc_proxy_fatal_alert_external_10 + SocProxyFatalAlertExternal10 = 31, + /// soc_proxy_fatal_alert_external_11 + SocProxyFatalAlertExternal11 = 32, + /// soc_proxy_fatal_alert_external_12 + SocProxyFatalAlertExternal12 = 33, + /// soc_proxy_fatal_alert_external_13 + SocProxyFatalAlertExternal13 = 34, + /// soc_proxy_fatal_alert_external_14 + SocProxyFatalAlertExternal14 = 35, + /// soc_proxy_fatal_alert_external_15 + SocProxyFatalAlertExternal15 = 36, + /// soc_proxy_fatal_alert_external_16 + SocProxyFatalAlertExternal16 = 37, + /// soc_proxy_fatal_alert_external_17 + SocProxyFatalAlertExternal17 = 38, + /// soc_proxy_fatal_alert_external_18 + SocProxyFatalAlertExternal18 = 39, + /// soc_proxy_fatal_alert_external_19 + SocProxyFatalAlertExternal19 = 40, + /// soc_proxy_fatal_alert_external_20 + SocProxyFatalAlertExternal20 = 41, + /// soc_proxy_fatal_alert_external_21 + SocProxyFatalAlertExternal21 = 42, + /// soc_proxy_fatal_alert_external_22 + SocProxyFatalAlertExternal22 = 43, + /// soc_proxy_fatal_alert_external_23 + SocProxyFatalAlertExternal23 = 44, + /// soc_proxy_recov_alert_external_0 + SocProxyRecovAlertExternal0 = 45, + /// soc_proxy_recov_alert_external_1 + SocProxyRecovAlertExternal1 = 46, + /// soc_proxy_recov_alert_external_2 + SocProxyRecovAlertExternal2 = 47, + /// soc_proxy_recov_alert_external_3 + SocProxyRecovAlertExternal3 = 48, + /// sram_ctrl_ret_aon_fatal_error + SramCtrlRetAonFatalError = 49, + /// rv_plic_fatal_fault + RvPlicFatalFault = 50, + /// aes_recov_ctrl_update_err + AesRecovCtrlUpdateErr = 51, + /// aes_fatal_fault + AesFatalFault = 52, + /// hmac_fatal_fault + HmacFatalFault = 53, + /// kmac_recov_operation_err + KmacRecovOperationErr = 54, + /// kmac_fatal_fault_err + KmacFatalFaultErr = 55, + /// otbn_fatal + OtbnFatal = 56, + /// otbn_recov + OtbnRecov = 57, + /// keymgr_dpe_recov_operation_err + KeymgrDpeRecovOperationErr = 58, + /// keymgr_dpe_fatal_fault_err + KeymgrDpeFatalFaultErr = 59, + /// csrng_recov_alert + CsrngRecovAlert = 60, + /// csrng_fatal_alert + CsrngFatalAlert = 61, + /// entropy_src_recov_alert + EntropySrcRecovAlert = 62, + /// entropy_src_fatal_alert + EntropySrcFatalAlert = 63, + /// edn0_recov_alert + Edn0RecovAlert = 64, + /// edn0_fatal_alert + Edn0FatalAlert = 65, + /// edn1_recov_alert + Edn1RecovAlert = 66, + /// edn1_fatal_alert + Edn1FatalAlert = 67, + /// sram_ctrl_main_fatal_error + SramCtrlMainFatalError = 68, + /// sram_ctrl_mbox_fatal_error + SramCtrlMboxFatalError = 69, + /// rom_ctrl0_fatal + RomCtrl0Fatal = 70, + /// rom_ctrl1_fatal + RomCtrl1Fatal = 71, + /// dma_fatal_fault + DmaFatalFault = 72, + /// mbx0_fatal_fault + Mbx0FatalFault = 73, + /// mbx0_recov_fault + Mbx0RecovFault = 74, + /// mbx1_fatal_fault + Mbx1FatalFault = 75, + /// mbx1_recov_fault + Mbx1RecovFault = 76, + /// mbx2_fatal_fault + Mbx2FatalFault = 77, + /// mbx2_recov_fault + Mbx2RecovFault = 78, + /// mbx3_fatal_fault + Mbx3FatalFault = 79, + /// mbx3_recov_fault + Mbx3RecovFault = 80, + /// mbx4_fatal_fault + Mbx4FatalFault = 81, + /// mbx4_recov_fault + Mbx4RecovFault = 82, + /// mbx5_fatal_fault + Mbx5FatalFault = 83, + /// mbx5_recov_fault + Mbx5RecovFault = 84, + /// mbx6_fatal_fault + Mbx6FatalFault = 85, + /// mbx6_recov_fault + Mbx6RecovFault = 86, + /// mbx_jtag_fatal_fault + MbxJtagFatalFault = 87, + /// mbx_jtag_recov_fault + MbxJtagRecovFault = 88, + /// mbx_pcie0_fatal_fault + MbxPcie0FatalFault = 89, + /// mbx_pcie0_recov_fault + MbxPcie0RecovFault = 90, + /// mbx_pcie1_fatal_fault + MbxPcie1FatalFault = 91, + /// mbx_pcie1_recov_fault + MbxPcie1RecovFault = 92, + /// soc_dbg_ctrl_fatal_fault + SocDbgCtrlFatalFault = 93, + /// soc_dbg_ctrl_recov_ctrl_update_err + SocDbgCtrlRecovCtrlUpdateErr = 94, + /// racl_ctrl_fatal_fault + RaclCtrlFatalFault = 95, + /// racl_ctrl_recov_ctrl_update_err + RaclCtrlRecovCtrlUpdateErr = 96, + /// ac_range_check_recov_ctrl_update_err + AcRangeCheckRecovCtrlUpdateErr = 97, + /// ac_range_check_fatal_fault + AcRangeCheckFatalFault = 98, +} + +impl TryFrom for AlertId { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::Uart0FatalFault), + 1 => Ok(Self::GpioFatalFault), + 2 => Ok(Self::SpiDeviceFatalFault), + 3 => Ok(Self::I2c0FatalFault), + 4 => Ok(Self::OtpCtrlFatalMacroError), + 5 => Ok(Self::OtpCtrlFatalCheckError), + 6 => Ok(Self::OtpCtrlFatalBusIntegError), + 7 => Ok(Self::OtpCtrlFatalPrimOtpAlert), + 8 => Ok(Self::OtpCtrlRecovPrimOtpAlert), + 9 => Ok(Self::LcCtrlFatalProgError), + 10 => Ok(Self::LcCtrlFatalStateError), + 11 => Ok(Self::LcCtrlFatalBusIntegError), + 12 => Ok(Self::SpiHost0FatalFault), + 13 => Ok(Self::PwrmgrAonFatalFault), + 14 => Ok(Self::RstmgrAonFatalFault), + 15 => Ok(Self::RstmgrAonFatalCnstyFault), + 16 => Ok(Self::ClkmgrAonRecovFault), + 17 => Ok(Self::ClkmgrAonFatalFault), + 18 => Ok(Self::PinmuxAonFatalFault), + 19 => Ok(Self::AonTimerAonFatalFault), + 20 => Ok(Self::SocProxyFatalAlertIntg), + 21 => Ok(Self::SocProxyFatalAlertExternal0), + 22 => Ok(Self::SocProxyFatalAlertExternal1), + 23 => Ok(Self::SocProxyFatalAlertExternal2), + 24 => Ok(Self::SocProxyFatalAlertExternal3), + 25 => Ok(Self::SocProxyFatalAlertExternal4), + 26 => Ok(Self::SocProxyFatalAlertExternal5), + 27 => Ok(Self::SocProxyFatalAlertExternal6), + 28 => Ok(Self::SocProxyFatalAlertExternal7), + 29 => Ok(Self::SocProxyFatalAlertExternal8), + 30 => Ok(Self::SocProxyFatalAlertExternal9), + 31 => Ok(Self::SocProxyFatalAlertExternal10), + 32 => Ok(Self::SocProxyFatalAlertExternal11), + 33 => Ok(Self::SocProxyFatalAlertExternal12), + 34 => Ok(Self::SocProxyFatalAlertExternal13), + 35 => Ok(Self::SocProxyFatalAlertExternal14), + 36 => Ok(Self::SocProxyFatalAlertExternal15), + 37 => Ok(Self::SocProxyFatalAlertExternal16), + 38 => Ok(Self::SocProxyFatalAlertExternal17), + 39 => Ok(Self::SocProxyFatalAlertExternal18), + 40 => Ok(Self::SocProxyFatalAlertExternal19), + 41 => Ok(Self::SocProxyFatalAlertExternal20), + 42 => Ok(Self::SocProxyFatalAlertExternal21), + 43 => Ok(Self::SocProxyFatalAlertExternal22), + 44 => Ok(Self::SocProxyFatalAlertExternal23), + 45 => Ok(Self::SocProxyRecovAlertExternal0), + 46 => Ok(Self::SocProxyRecovAlertExternal1), + 47 => Ok(Self::SocProxyRecovAlertExternal2), + 48 => Ok(Self::SocProxyRecovAlertExternal3), + 49 => Ok(Self::SramCtrlRetAonFatalError), + 50 => Ok(Self::RvPlicFatalFault), + 51 => Ok(Self::AesRecovCtrlUpdateErr), + 52 => Ok(Self::AesFatalFault), + 53 => Ok(Self::HmacFatalFault), + 54 => Ok(Self::KmacRecovOperationErr), + 55 => Ok(Self::KmacFatalFaultErr), + 56 => Ok(Self::OtbnFatal), + 57 => Ok(Self::OtbnRecov), + 58 => Ok(Self::KeymgrDpeRecovOperationErr), + 59 => Ok(Self::KeymgrDpeFatalFaultErr), + 60 => Ok(Self::CsrngRecovAlert), + 61 => Ok(Self::CsrngFatalAlert), + 62 => Ok(Self::EntropySrcRecovAlert), + 63 => Ok(Self::EntropySrcFatalAlert), + 64 => Ok(Self::Edn0RecovAlert), + 65 => Ok(Self::Edn0FatalAlert), + 66 => Ok(Self::Edn1RecovAlert), + 67 => Ok(Self::Edn1FatalAlert), + 68 => Ok(Self::SramCtrlMainFatalError), + 69 => Ok(Self::SramCtrlMboxFatalError), + 70 => Ok(Self::RomCtrl0Fatal), + 71 => Ok(Self::RomCtrl1Fatal), + 72 => Ok(Self::DmaFatalFault), + 73 => Ok(Self::Mbx0FatalFault), + 74 => Ok(Self::Mbx0RecovFault), + 75 => Ok(Self::Mbx1FatalFault), + 76 => Ok(Self::Mbx1RecovFault), + 77 => Ok(Self::Mbx2FatalFault), + 78 => Ok(Self::Mbx2RecovFault), + 79 => Ok(Self::Mbx3FatalFault), + 80 => Ok(Self::Mbx3RecovFault), + 81 => Ok(Self::Mbx4FatalFault), + 82 => Ok(Self::Mbx4RecovFault), + 83 => Ok(Self::Mbx5FatalFault), + 84 => Ok(Self::Mbx5RecovFault), + 85 => Ok(Self::Mbx6FatalFault), + 86 => Ok(Self::Mbx6RecovFault), + 87 => Ok(Self::MbxJtagFatalFault), + 88 => Ok(Self::MbxJtagRecovFault), + 89 => Ok(Self::MbxPcie0FatalFault), + 90 => Ok(Self::MbxPcie0RecovFault), + 91 => Ok(Self::MbxPcie1FatalFault), + 92 => Ok(Self::MbxPcie1RecovFault), + 93 => Ok(Self::SocDbgCtrlFatalFault), + 94 => Ok(Self::SocDbgCtrlRecovCtrlUpdateErr), + 95 => Ok(Self::RaclCtrlFatalFault), + 96 => Ok(Self::RaclCtrlRecovCtrlUpdateErr), + 97 => Ok(Self::AcRangeCheckRecovCtrlUpdateErr), + 98 => Ok(Self::AcRangeCheckFatalFault), + _ => Err(val), + } + } +} + +/// Alert Handler Alert Source to Peripheral Map +/// +/// This array is a mapping from `AlertId` to +/// `AlertPeripheral`. +pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 99] = [ + // Uart0FatalFault -> AlertPeripheral::Uart0 + AlertPeripheral::Uart0, + // GpioFatalFault -> AlertPeripheral::Gpio + AlertPeripheral::Gpio, + // SpiDeviceFatalFault -> AlertPeripheral::SpiDevice + AlertPeripheral::SpiDevice, + // I2c0FatalFault -> AlertPeripheral::I2c0 + AlertPeripheral::I2c0, + // OtpCtrlFatalMacroError -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // OtpCtrlFatalCheckError -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // OtpCtrlFatalBusIntegError -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // OtpCtrlFatalPrimOtpAlert -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // OtpCtrlRecovPrimOtpAlert -> AlertPeripheral::OtpCtrl + AlertPeripheral::OtpCtrl, + // LcCtrlFatalProgError -> AlertPeripheral::LcCtrl + AlertPeripheral::LcCtrl, + // LcCtrlFatalStateError -> AlertPeripheral::LcCtrl + AlertPeripheral::LcCtrl, + // LcCtrlFatalBusIntegError -> AlertPeripheral::LcCtrl + AlertPeripheral::LcCtrl, + // SpiHost0FatalFault -> AlertPeripheral::SpiHost0 + AlertPeripheral::SpiHost0, + // PwrmgrAonFatalFault -> AlertPeripheral::PwrmgrAon + AlertPeripheral::PwrmgrAon, + // RstmgrAonFatalFault -> AlertPeripheral::RstmgrAon + AlertPeripheral::RstmgrAon, + // RstmgrAonFatalCnstyFault -> AlertPeripheral::RstmgrAon + AlertPeripheral::RstmgrAon, + // ClkmgrAonRecovFault -> AlertPeripheral::ClkmgrAon + AlertPeripheral::ClkmgrAon, + // ClkmgrAonFatalFault -> AlertPeripheral::ClkmgrAon + AlertPeripheral::ClkmgrAon, + // PinmuxAonFatalFault -> AlertPeripheral::PinmuxAon + AlertPeripheral::PinmuxAon, + // AonTimerAonFatalFault -> AlertPeripheral::AonTimerAon + AlertPeripheral::AonTimerAon, + // SocProxyFatalAlertIntg -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal0 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal1 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal2 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal3 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal4 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal5 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal6 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal7 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal8 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal9 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal10 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal11 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal12 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal13 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal14 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal15 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal16 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal17 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal18 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal19 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal20 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal21 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal22 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyFatalAlertExternal23 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyRecovAlertExternal0 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyRecovAlertExternal1 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyRecovAlertExternal2 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SocProxyRecovAlertExternal3 -> AlertPeripheral::SocProxy + AlertPeripheral::SocProxy, + // SramCtrlRetAonFatalError -> AlertPeripheral::SramCtrlRetAon + AlertPeripheral::SramCtrlRetAon, + // RvPlicFatalFault -> AlertPeripheral::RvPlic + AlertPeripheral::RvPlic, + // AesRecovCtrlUpdateErr -> AlertPeripheral::Aes + AlertPeripheral::Aes, + // AesFatalFault -> AlertPeripheral::Aes + AlertPeripheral::Aes, + // HmacFatalFault -> AlertPeripheral::Hmac + AlertPeripheral::Hmac, + // KmacRecovOperationErr -> AlertPeripheral::Kmac + AlertPeripheral::Kmac, + // KmacFatalFaultErr -> AlertPeripheral::Kmac + AlertPeripheral::Kmac, + // OtbnFatal -> AlertPeripheral::Otbn + AlertPeripheral::Otbn, + // OtbnRecov -> AlertPeripheral::Otbn + AlertPeripheral::Otbn, + // KeymgrDpeRecovOperationErr -> AlertPeripheral::KeymgrDpe + AlertPeripheral::KeymgrDpe, + // KeymgrDpeFatalFaultErr -> AlertPeripheral::KeymgrDpe + AlertPeripheral::KeymgrDpe, + // CsrngRecovAlert -> AlertPeripheral::Csrng + AlertPeripheral::Csrng, + // CsrngFatalAlert -> AlertPeripheral::Csrng + AlertPeripheral::Csrng, + // EntropySrcRecovAlert -> AlertPeripheral::EntropySrc + AlertPeripheral::EntropySrc, + // EntropySrcFatalAlert -> AlertPeripheral::EntropySrc + AlertPeripheral::EntropySrc, + // Edn0RecovAlert -> AlertPeripheral::Edn0 + AlertPeripheral::Edn0, + // Edn0FatalAlert -> AlertPeripheral::Edn0 + AlertPeripheral::Edn0, + // Edn1RecovAlert -> AlertPeripheral::Edn1 + AlertPeripheral::Edn1, + // Edn1FatalAlert -> AlertPeripheral::Edn1 + AlertPeripheral::Edn1, + // SramCtrlMainFatalError -> AlertPeripheral::SramCtrlMain + AlertPeripheral::SramCtrlMain, + // SramCtrlMboxFatalError -> AlertPeripheral::SramCtrlMbox + AlertPeripheral::SramCtrlMbox, + // RomCtrl0Fatal -> AlertPeripheral::RomCtrl0 + AlertPeripheral::RomCtrl0, + // RomCtrl1Fatal -> AlertPeripheral::RomCtrl1 + AlertPeripheral::RomCtrl1, + // DmaFatalFault -> AlertPeripheral::Dma + AlertPeripheral::Dma, + // Mbx0FatalFault -> AlertPeripheral::Mbx0 + AlertPeripheral::Mbx0, + // Mbx0RecovFault -> AlertPeripheral::Mbx0 + AlertPeripheral::Mbx0, + // Mbx1FatalFault -> AlertPeripheral::Mbx1 + AlertPeripheral::Mbx1, + // Mbx1RecovFault -> AlertPeripheral::Mbx1 + AlertPeripheral::Mbx1, + // Mbx2FatalFault -> AlertPeripheral::Mbx2 + AlertPeripheral::Mbx2, + // Mbx2RecovFault -> AlertPeripheral::Mbx2 + AlertPeripheral::Mbx2, + // Mbx3FatalFault -> AlertPeripheral::Mbx3 + AlertPeripheral::Mbx3, + // Mbx3RecovFault -> AlertPeripheral::Mbx3 + AlertPeripheral::Mbx3, + // Mbx4FatalFault -> AlertPeripheral::Mbx4 + AlertPeripheral::Mbx4, + // Mbx4RecovFault -> AlertPeripheral::Mbx4 + AlertPeripheral::Mbx4, + // Mbx5FatalFault -> AlertPeripheral::Mbx5 + AlertPeripheral::Mbx5, + // Mbx5RecovFault -> AlertPeripheral::Mbx5 + AlertPeripheral::Mbx5, + // Mbx6FatalFault -> AlertPeripheral::Mbx6 + AlertPeripheral::Mbx6, + // Mbx6RecovFault -> AlertPeripheral::Mbx6 + AlertPeripheral::Mbx6, + // MbxJtagFatalFault -> AlertPeripheral::MbxJtag + AlertPeripheral::MbxJtag, + // MbxJtagRecovFault -> AlertPeripheral::MbxJtag + AlertPeripheral::MbxJtag, + // MbxPcie0FatalFault -> AlertPeripheral::MbxPcie0 + AlertPeripheral::MbxPcie0, + // MbxPcie0RecovFault -> AlertPeripheral::MbxPcie0 + AlertPeripheral::MbxPcie0, + // MbxPcie1FatalFault -> AlertPeripheral::MbxPcie1 + AlertPeripheral::MbxPcie1, + // MbxPcie1RecovFault -> AlertPeripheral::MbxPcie1 + AlertPeripheral::MbxPcie1, + // SocDbgCtrlFatalFault -> AlertPeripheral::SocDbgCtrl + AlertPeripheral::SocDbgCtrl, + // SocDbgCtrlRecovCtrlUpdateErr -> AlertPeripheral::SocDbgCtrl + AlertPeripheral::SocDbgCtrl, + // RaclCtrlFatalFault -> AlertPeripheral::RaclCtrl + AlertPeripheral::RaclCtrl, + // RaclCtrlRecovCtrlUpdateErr -> AlertPeripheral::RaclCtrl + AlertPeripheral::RaclCtrl, + // AcRangeCheckRecovCtrlUpdateErr -> AlertPeripheral::AcRangeCheck + AlertPeripheral::AcRangeCheck, + // AcRangeCheckFatalFault -> AlertPeripheral::AcRangeCheck + AlertPeripheral::AcRangeCheck, +]; + +// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1} +// 0 and 1 are tied to value 0 and 1 +pub const NUM_MIO_PADS: usize = 12; +pub const NUM_DIO_PADS: usize = 73; + +pub const PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET: usize = 2; +pub const PINMUX_PERIPH_OUTSEL_IDX_OFFSET: usize = 3; + +/// Pinmux Peripheral Input. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PinmuxPeripheralIn { + /// Peripheral Input 0 + SocProxySocGpi12 = 0, + /// Peripheral Input 1 + SocProxySocGpi13 = 1, + /// Peripheral Input 2 + SocProxySocGpi14 = 2, + /// Peripheral Input 3 + SocProxySocGpi15 = 3, +} + +impl TryFrom for PinmuxPeripheralIn { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::SocProxySocGpi12), + 1 => Ok(Self::SocProxySocGpi13), + 2 => Ok(Self::SocProxySocGpi14), + 3 => Ok(Self::SocProxySocGpi15), + _ => Err(val), + } + } +} + +/// Pinmux MIO Input Selector. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PinmuxInsel { + /// Tie constantly to zero + ConstantZero = 0, + /// Tie constantly to one + ConstantOne = 1, + /// MIO Pad 0 + Mio0 = 2, + /// MIO Pad 1 + Mio1 = 3, + /// MIO Pad 2 + Mio2 = 4, + /// MIO Pad 3 + Mio3 = 5, + /// MIO Pad 4 + Mio4 = 6, + /// MIO Pad 5 + Mio5 = 7, + /// MIO Pad 6 + Mio6 = 8, + /// MIO Pad 7 + Mio7 = 9, + /// MIO Pad 8 + Mio8 = 10, + /// MIO Pad 9 + Mio9 = 11, + /// MIO Pad 10 + Mio10 = 12, + /// MIO Pad 11 + Mio11 = 13, +} + +impl TryFrom for PinmuxInsel { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::ConstantZero), + 1 => Ok(Self::ConstantOne), + 2 => Ok(Self::Mio0), + 3 => Ok(Self::Mio1), + 4 => Ok(Self::Mio2), + 5 => Ok(Self::Mio3), + 6 => Ok(Self::Mio4), + 7 => Ok(Self::Mio5), + 8 => Ok(Self::Mio6), + 9 => Ok(Self::Mio7), + 10 => Ok(Self::Mio8), + 11 => Ok(Self::Mio9), + 12 => Ok(Self::Mio10), + 13 => Ok(Self::Mio11), + _ => Err(val), + } + } +} + +/// Pinmux MIO Output. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PinmuxMioOut { + /// MIO Pad 0 + Mio0 = 0, + /// MIO Pad 1 + Mio1 = 1, + /// MIO Pad 2 + Mio2 = 2, + /// MIO Pad 3 + Mio3 = 3, + /// MIO Pad 4 + Mio4 = 4, + /// MIO Pad 5 + Mio5 = 5, + /// MIO Pad 6 + Mio6 = 6, + /// MIO Pad 7 + Mio7 = 7, + /// MIO Pad 8 + Mio8 = 8, + /// MIO Pad 9 + Mio9 = 9, + /// MIO Pad 10 + Mio10 = 10, + /// MIO Pad 11 + Mio11 = 11, +} + +impl TryFrom for PinmuxMioOut { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::Mio0), + 1 => Ok(Self::Mio1), + 2 => Ok(Self::Mio2), + 3 => Ok(Self::Mio3), + 4 => Ok(Self::Mio4), + 5 => Ok(Self::Mio5), + 6 => Ok(Self::Mio6), + 7 => Ok(Self::Mio7), + 8 => Ok(Self::Mio8), + 9 => Ok(Self::Mio9), + 10 => Ok(Self::Mio10), + 11 => Ok(Self::Mio11), + _ => Err(val), + } + } +} + +/// Pinmux Peripheral Output Selector. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PinmuxOutsel { + /// Tie constantly to zero + ConstantZero = 0, + /// Tie constantly to one + ConstantOne = 1, + /// Tie constantly to high-Z + ConstantHighZ = 2, + /// Peripheral Output 0 + SocProxySocGpo12 = 3, + /// Peripheral Output 1 + SocProxySocGpo13 = 4, + /// Peripheral Output 2 + SocProxySocGpo14 = 5, + /// Peripheral Output 3 + SocProxySocGpo15 = 6, + /// Peripheral Output 4 + OtpMacroTest0 = 7, +} + +impl TryFrom for PinmuxOutsel { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::ConstantZero), + 1 => Ok(Self::ConstantOne), + 2 => Ok(Self::ConstantHighZ), + 3 => Ok(Self::SocProxySocGpo12), + 4 => Ok(Self::SocProxySocGpo13), + 5 => Ok(Self::SocProxySocGpo14), + 6 => Ok(Self::SocProxySocGpo15), + 7 => Ok(Self::OtpMacroTest0), + _ => Err(val), + } + } +} + +/// Dedicated Pad Selects +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum DirectPads { + SpiHost0Sd0 = 0, + SpiHost0Sd1 = 1, + SpiHost0Sd2 = 2, + SpiHost0Sd3 = 3, + SpiDeviceSd0 = 4, + SpiDeviceSd1 = 5, + SpiDeviceSd2 = 6, + SpiDeviceSd3 = 7, + I2c0Scl = 8, + I2c0Sda = 9, + GpioGpio0 = 10, + GpioGpio1 = 11, + GpioGpio2 = 12, + GpioGpio3 = 13, + GpioGpio4 = 14, + GpioGpio5 = 15, + GpioGpio6 = 16, + GpioGpio7 = 17, + GpioGpio8 = 18, + GpioGpio9 = 19, + GpioGpio10 = 20, + GpioGpio11 = 21, + GpioGpio12 = 22, + GpioGpio13 = 23, + GpioGpio14 = 24, + GpioGpio15 = 25, + GpioGpio16 = 26, + GpioGpio17 = 27, + GpioGpio18 = 28, + GpioGpio19 = 29, + GpioGpio20 = 30, + GpioGpio21 = 31, + GpioGpio22 = 32, + GpioGpio23 = 33, + GpioGpio24 = 34, + GpioGpio25 = 35, + GpioGpio26 = 36, + GpioGpio27 = 37, + GpioGpio28 = 38, + GpioGpio29 = 39, + GpioGpio30 = 40, + GpioGpio31 = 41, + SpiDeviceSck = 42, + SpiDeviceCsb = 43, + SpiDeviceTpmCsb = 44, + Uart0Rx = 45, + SocProxySocGpi0 = 46, + SocProxySocGpi1 = 47, + SocProxySocGpi2 = 48, + SocProxySocGpi3 = 49, + SocProxySocGpi4 = 50, + SocProxySocGpi5 = 51, + SocProxySocGpi6 = 52, + SocProxySocGpi7 = 53, + SocProxySocGpi8 = 54, + SocProxySocGpi9 = 55, + SocProxySocGpi10 = 56, + SocProxySocGpi11 = 57, + SpiHost0Sck = 58, + SpiHost0Csb = 59, + Uart0Tx = 60, + SocProxySocGpo0 = 61, + SocProxySocGpo1 = 62, + SocProxySocGpo2 = 63, + SocProxySocGpo3 = 64, + SocProxySocGpo4 = 65, + SocProxySocGpo5 = 66, + SocProxySocGpo6 = 67, + SocProxySocGpo7 = 68, + SocProxySocGpo8 = 69, + SocProxySocGpo9 = 70, + SocProxySocGpo10 = 71, + SocProxySocGpo11 = 72, +} + +impl TryFrom for DirectPads { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::SpiHost0Sd0), + 1 => Ok(Self::SpiHost0Sd1), + 2 => Ok(Self::SpiHost0Sd2), + 3 => Ok(Self::SpiHost0Sd3), + 4 => Ok(Self::SpiDeviceSd0), + 5 => Ok(Self::SpiDeviceSd1), + 6 => Ok(Self::SpiDeviceSd2), + 7 => Ok(Self::SpiDeviceSd3), + 8 => Ok(Self::I2c0Scl), + 9 => Ok(Self::I2c0Sda), + 10 => Ok(Self::GpioGpio0), + 11 => Ok(Self::GpioGpio1), + 12 => Ok(Self::GpioGpio2), + 13 => Ok(Self::GpioGpio3), + 14 => Ok(Self::GpioGpio4), + 15 => Ok(Self::GpioGpio5), + 16 => Ok(Self::GpioGpio6), + 17 => Ok(Self::GpioGpio7), + 18 => Ok(Self::GpioGpio8), + 19 => Ok(Self::GpioGpio9), + 20 => Ok(Self::GpioGpio10), + 21 => Ok(Self::GpioGpio11), + 22 => Ok(Self::GpioGpio12), + 23 => Ok(Self::GpioGpio13), + 24 => Ok(Self::GpioGpio14), + 25 => Ok(Self::GpioGpio15), + 26 => Ok(Self::GpioGpio16), + 27 => Ok(Self::GpioGpio17), + 28 => Ok(Self::GpioGpio18), + 29 => Ok(Self::GpioGpio19), + 30 => Ok(Self::GpioGpio20), + 31 => Ok(Self::GpioGpio21), + 32 => Ok(Self::GpioGpio22), + 33 => Ok(Self::GpioGpio23), + 34 => Ok(Self::GpioGpio24), + 35 => Ok(Self::GpioGpio25), + 36 => Ok(Self::GpioGpio26), + 37 => Ok(Self::GpioGpio27), + 38 => Ok(Self::GpioGpio28), + 39 => Ok(Self::GpioGpio29), + 40 => Ok(Self::GpioGpio30), + 41 => Ok(Self::GpioGpio31), + 42 => Ok(Self::SpiDeviceSck), + 43 => Ok(Self::SpiDeviceCsb), + 44 => Ok(Self::SpiDeviceTpmCsb), + 45 => Ok(Self::Uart0Rx), + 46 => Ok(Self::SocProxySocGpi0), + 47 => Ok(Self::SocProxySocGpi1), + 48 => Ok(Self::SocProxySocGpi2), + 49 => Ok(Self::SocProxySocGpi3), + 50 => Ok(Self::SocProxySocGpi4), + 51 => Ok(Self::SocProxySocGpi5), + 52 => Ok(Self::SocProxySocGpi6), + 53 => Ok(Self::SocProxySocGpi7), + 54 => Ok(Self::SocProxySocGpi8), + 55 => Ok(Self::SocProxySocGpi9), + 56 => Ok(Self::SocProxySocGpi10), + 57 => Ok(Self::SocProxySocGpi11), + 58 => Ok(Self::SpiHost0Sck), + 59 => Ok(Self::SpiHost0Csb), + 60 => Ok(Self::Uart0Tx), + 61 => Ok(Self::SocProxySocGpo0), + 62 => Ok(Self::SocProxySocGpo1), + 63 => Ok(Self::SocProxySocGpo2), + 64 => Ok(Self::SocProxySocGpo3), + 65 => Ok(Self::SocProxySocGpo4), + 66 => Ok(Self::SocProxySocGpo5), + 67 => Ok(Self::SocProxySocGpo6), + 68 => Ok(Self::SocProxySocGpo7), + 69 => Ok(Self::SocProxySocGpo8), + 70 => Ok(Self::SocProxySocGpo9), + 71 => Ok(Self::SocProxySocGpo10), + 72 => Ok(Self::SocProxySocGpo11), + _ => Err(val), + } + } +} + +/// Muxed Pad Selects +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum MuxedPads { + Mio0 = 0, + Mio1 = 1, + Mio2 = 2, + Mio3 = 3, + Mio4 = 4, + Mio5 = 5, + Mio6 = 6, + Mio7 = 7, + Mio8 = 8, + Mio9 = 9, + Mio10 = 10, + Mio11 = 11, +} + +impl TryFrom for MuxedPads { + type Error = u32; + fn try_from(val: u32) -> Result { + match val { + 0 => Ok(Self::Mio0), + 1 => Ok(Self::Mio1), + 2 => Ok(Self::Mio2), + 3 => Ok(Self::Mio3), + 4 => Ok(Self::Mio4), + 5 => Ok(Self::Mio5), + 6 => Ok(Self::Mio6), + 7 => Ok(Self::Mio7), + 8 => Ok(Self::Mio8), + 9 => Ok(Self::Mio9), + 10 => Ok(Self::Mio10), + 11 => Ok(Self::Mio11), + _ => Err(val), + } + } +} + +/// Power Manager Wakeup Signals +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PowerManagerWakeUps { + PinmuxAonPinWkupReq = 0, + AonTimerAonWkupReq = 1, + SocProxyWkupInternalReq = 2, + SocProxyWkupExternalReq = 3, +} + +/// Reset Manager Software Controlled Resets +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum ResetManagerSwResets { + SpiDevice = 0, + SpiHost0 = 1, + I2c0 = 2, +} + +/// Power Manager Reset Request Signals +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum PowerManagerResetRequests { + AonTimerAonAonTimerRstReq = 0, + SocProxyRstReqExternal = 1, +} + +/// Clock Manager Software-Controlled ("Gated") Clocks. +/// +/// The Software has full control over these clocks. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum GateableClocks { + /// Clock clk_io_div4_peri in group peri + IoDiv4Peri = 0, + /// Clock clk_io_div2_peri in group peri + IoDiv2Peri = 1, +} + +/// Clock Manager Software-Hinted Clocks. +/// +/// The Software has partial control over these clocks. It can ask them to stop, +/// but the clock manager is in control of whether the clock actually is stopped. +#[derive(Copy, Clone, PartialEq, Eq)] +#[repr(u32)] +pub enum HintableClocks { + /// Clock clk_main_aes in group trans + MainAes = 0, + /// Clock clk_main_hmac in group trans + MainHmac = 1, + /// Clock clk_main_kmac in group trans + MainKmac = 2, + /// Clock clk_main_otbn in group trans + MainOtbn = 3, +} + +/// MMIO Region +/// +/// MMIO region excludes any memory that is separate from the module +/// configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but +/// retention SRAM or spi_device are included. +pub const TOP_DARJEELING_NO_IBEX_MMIO_BASE_ADDR: usize = 0x21100000; +pub const TOP_DARJEELING_NO_IBEX_MMIO_SIZE_BYTES: usize = 0xF501000; diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/chip/top_darjeeling_no_ibex_soc_dbg.rs b/hw/top_darjeeling_no_ibex/sw/autogen/chip/top_darjeeling_no_ibex_soc_dbg.rs new file mode 100644 index 00000000000..33fadafbd98 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/chip/top_darjeeling_no_ibex_soc_dbg.rs @@ -0,0 +1,62 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +//! This file contains enums and consts for use within the Rust codebase. +//! +//! These definitions are for information that depends on the top-specific chip +//! configuration, which includes: +//! - Device Memory Information (for Peripherals and Memory) +//! - PLIC Interrupt ID Names and Source Mappings +//! - Alert ID Names and Source Mappings + +use core::convert::TryFrom; + +/// Peripheral base address for dmi device on lc_ctrl in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const LC_CTRL_DMI_BASE_ADDR: usize = 0x3000; + +/// Peripheral size for dmi device on lc_ctrl in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #LC_CTRL_DMI_BASE_ADDR and +/// `LC_CTRL_DMI_BASE_ADDR + LC_CTRL_DMI_SIZE_BYTES`. +pub const LC_CTRL_DMI_SIZE_BYTES: usize = 0x1000; + +/// Peripheral base address for soc device on mbx_jtag in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX_JTAG_SOC_BASE_ADDR: usize = 0x2200; + +/// Peripheral size for soc device on mbx_jtag in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX_JTAG_SOC_BASE_ADDR and +/// `MBX_JTAG_SOC_BASE_ADDR + MBX_JTAG_SOC_SIZE_BYTES`. +pub const MBX_JTAG_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for jtag device on soc_dbg_ctrl in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const SOC_DBG_CTRL_JTAG_BASE_ADDR: usize = 0x2300; + +/// Peripheral size for jtag device on soc_dbg_ctrl in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #SOC_DBG_CTRL_JTAG_BASE_ADDR and +/// `SOC_DBG_CTRL_JTAG_BASE_ADDR + SOC_DBG_CTRL_JTAG_SIZE_BYTES`. +pub const SOC_DBG_CTRL_JTAG_SIZE_BYTES: usize = 0x20; diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/chip/top_darjeeling_no_ibex_soc_mbx.rs b/hw/top_darjeeling_no_ibex/sw/autogen/chip/top_darjeeling_no_ibex_soc_mbx.rs new file mode 100644 index 00000000000..98a6e7c1c0d --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/chip/top_darjeeling_no_ibex_soc_mbx.rs @@ -0,0 +1,174 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +//! This file contains enums and consts for use within the Rust codebase. +//! +//! These definitions are for information that depends on the top-specific chip +//! configuration, which includes: +//! - Device Memory Information (for Peripherals and Memory) +//! - PLIC Interrupt ID Names and Source Mappings +//! - Alert ID Names and Source Mappings + +use core::convert::TryFrom; + +/// Peripheral base address for soc device on mbx0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX0_SOC_BASE_ADDR: usize = 0x1465000; + +/// Peripheral size for soc device on mbx0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX0_SOC_BASE_ADDR and +/// `MBX0_SOC_BASE_ADDR + MBX0_SOC_SIZE_BYTES`. +pub const MBX0_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for soc device on mbx1 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX1_SOC_BASE_ADDR: usize = 0x1465100; + +/// Peripheral size for soc device on mbx1 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX1_SOC_BASE_ADDR and +/// `MBX1_SOC_BASE_ADDR + MBX1_SOC_SIZE_BYTES`. +pub const MBX1_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for soc device on mbx2 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX2_SOC_BASE_ADDR: usize = 0x1465200; + +/// Peripheral size for soc device on mbx2 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX2_SOC_BASE_ADDR and +/// `MBX2_SOC_BASE_ADDR + MBX2_SOC_SIZE_BYTES`. +pub const MBX2_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for soc device on mbx3 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX3_SOC_BASE_ADDR: usize = 0x1465300; + +/// Peripheral size for soc device on mbx3 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX3_SOC_BASE_ADDR and +/// `MBX3_SOC_BASE_ADDR + MBX3_SOC_SIZE_BYTES`. +pub const MBX3_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for soc device on mbx4 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX4_SOC_BASE_ADDR: usize = 0x1465400; + +/// Peripheral size for soc device on mbx4 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX4_SOC_BASE_ADDR and +/// `MBX4_SOC_BASE_ADDR + MBX4_SOC_SIZE_BYTES`. +pub const MBX4_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for soc device on mbx5 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX5_SOC_BASE_ADDR: usize = 0x1465500; + +/// Peripheral size for soc device on mbx5 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX5_SOC_BASE_ADDR and +/// `MBX5_SOC_BASE_ADDR + MBX5_SOC_SIZE_BYTES`. +pub const MBX5_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for soc device on mbx6 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX6_SOC_BASE_ADDR: usize = 0x1496000; + +/// Peripheral size for soc device on mbx6 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX6_SOC_BASE_ADDR and +/// `MBX6_SOC_BASE_ADDR + MBX6_SOC_SIZE_BYTES`. +pub const MBX6_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for soc device on mbx_pcie0 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX_PCIE0_SOC_BASE_ADDR: usize = 0x1460100; + +/// Peripheral size for soc device on mbx_pcie0 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX_PCIE0_SOC_BASE_ADDR and +/// `MBX_PCIE0_SOC_BASE_ADDR + MBX_PCIE0_SOC_SIZE_BYTES`. +pub const MBX_PCIE0_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for soc device on mbx_pcie1 in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const MBX_PCIE1_SOC_BASE_ADDR: usize = 0x1460200; + +/// Peripheral size for soc device on mbx_pcie1 in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #MBX_PCIE1_SOC_BASE_ADDR and +/// `MBX_PCIE1_SOC_BASE_ADDR + MBX_PCIE1_SOC_SIZE_BYTES`. +pub const MBX_PCIE1_SOC_SIZE_BYTES: usize = 0x20; + +/// Peripheral base address for racl_ctrl in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const RACL_CTRL_BASE_ADDR: usize = 0x1461F00; + +/// Peripheral size for racl_ctrl in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #RACL_CTRL_BASE_ADDR and +/// `RACL_CTRL_BASE_ADDR + RACL_CTRL_SIZE_BYTES`. +pub const RACL_CTRL_SIZE_BYTES: usize = 0x100; + +/// Peripheral base address for ac_range_check in top darjeeling_no_ibex. +/// +/// This should be used with #mmio_region_from_addr to access the memory-mapped +/// registers associated with the peripheral (usually via a DIF). +pub const AC_RANGE_CHECK_BASE_ADDR: usize = 0x1464000; + +/// Peripheral size for ac_range_check in top darjeeling_no_ibex. +/// +/// This is the size (in bytes) of the peripheral's reserved memory area. All +/// memory-mapped registers associated with this peripheral should have an +/// address between #AC_RANGE_CHECK_BASE_ADDR and +/// `AC_RANGE_CHECK_BASE_ADDR + AC_RANGE_CHECK_SIZE_BYTES`. +pub const AC_RANGE_CHECK_SIZE_BYTES: usize = 0x400; diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/tests/BUILD b/hw/top_darjeeling_no_ibex/sw/autogen/tests/BUILD new file mode 100644 index 00000000000..f58dd242fab --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/tests/BUILD @@ -0,0 +1,138 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------# +# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +# util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +# -o hw/top_darjeeling_no_ibex + +load( + "//rules/opentitan:defs.bzl", + "cw310_params", + "fpga_params", + "opentitan_test", + "silicon_params", + "verilator_params", +) +load("@bazel_skylib//lib:dicts.bzl", "dicts") + +package(default_visibility = ["//visibility:public"]) + +# Number of peripherals per test +NR_IRQ_PERIPH_PER_TEST = 10 + +# Total numbers of tests (the last will contain only remaining IRQs) +NR_IRQ_PERIPH_TESTS = 3 + +[ + opentitan_test( + name = "plic_all_irqs_test_{}".format(idx * NR_IRQ_PERIPH_PER_TEST), + srcs = ["plic_all_irqs_test.c"], + # For the last test, do not specify TEST_MAX_IRQ_PERIPHERAL to be sure + # that we are capturing all peripherals. + copts = [ + "-DTEST_MIN_IRQ_PERIPHERAL={}".format(idx * NR_IRQ_PERIPH_PER_TEST), + ] + ([ + "-DTEST_MAX_IRQ_PERIPHERAL={}".format((idx + 1) * NR_IRQ_PERIPH_PER_TEST), + ] if idx < NR_IRQ_PERIPH_PER_TEST - 1 else []), + exec_env = dicts.add( + ), + verilator = verilator_params( + timeout = "eternal", + tags = [ + "flaky", + "manual", + ], + # This test can take > 60 minutes, so mark it manual as it + # shouldn't run in CI/nightlies. + # often times out in 3600s on 4 cores + ), + deps = [ + "//hw/top_darjeeling_no_ibex/sw/autogen:top_darjeeling_no_ibex", + "//sw/device/lib/arch:boot_stage", + "//sw/device/lib/base:mmio", + "//sw/device/lib/dif/autogen:ac_range_check", + "//sw/device/lib/dif/autogen:alert_handler", + "//sw/device/lib/dif/autogen:aon_timer", + "//sw/device/lib/dif/autogen:csrng", + "//sw/device/lib/dif/autogen:dma", + "//sw/device/lib/dif/autogen:edn", + "//sw/device/lib/dif/autogen:entropy_src", + "//sw/device/lib/dif/autogen:gpio", + "//sw/device/lib/dif/autogen:hmac", + "//sw/device/lib/dif/autogen:i2c", + "//sw/device/lib/dif/autogen:keymgr_dpe", + "//sw/device/lib/dif/autogen:kmac", + "//sw/device/lib/dif/autogen:mbx", + "//sw/device/lib/dif/autogen:otbn", + "//sw/device/lib/dif/autogen:otp_ctrl", + "//sw/device/lib/dif/autogen:pwrmgr", + "//sw/device/lib/dif/autogen:racl_ctrl", + "//sw/device/lib/dif/autogen:rv_plic", + "//sw/device/lib/dif/autogen:soc_proxy", + "//sw/device/lib/dif/autogen:spi_device", + "//sw/device/lib/dif/autogen:spi_host", + "//sw/device/lib/dif/autogen:uart", + "//sw/device/lib/runtime:irq", + "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:rv_plic_testutils", + "//sw/device/lib/testing/test_framework:ottf_main", + ], + ) + for idx in range(NR_IRQ_PERIPH_TESTS) +] + +test_suite( + name = "plic_all_irqs_test", + tests = [ + "plic_all_irqs_test_{}".format(idx * NR_IRQ_PERIPH_PER_TEST) + for idx in range(NR_IRQ_PERIPH_TESTS) + ], +) + +opentitan_test( + name = "alert_test", + srcs = ["alert_test.c"], + exec_env = dicts.add( + ), + deps = [ + "//hw/top_darjeeling_no_ibex/sw/autogen:top_darjeeling_no_ibex", + "//sw/device/lib/arch:boot_stage", + "//sw/device/lib/base:memory", + "//sw/device/lib/base:mmio", + "//sw/device/lib/dif/autogen:ac_range_check", + "//sw/device/lib/dif/autogen:aes", + "//sw/device/lib/dif/autogen:alert_handler", + "//sw/device/lib/dif/autogen:aon_timer", + "//sw/device/lib/dif/autogen:clkmgr", + "//sw/device/lib/dif/autogen:csrng", + "//sw/device/lib/dif/autogen:dma", + "//sw/device/lib/dif/autogen:edn", + "//sw/device/lib/dif/autogen:entropy_src", + "//sw/device/lib/dif/autogen:gpio", + "//sw/device/lib/dif/autogen:hmac", + "//sw/device/lib/dif/autogen:i2c", + "//sw/device/lib/dif/autogen:keymgr_dpe", + "//sw/device/lib/dif/autogen:kmac", + "//sw/device/lib/dif/autogen:lc_ctrl", + "//sw/device/lib/dif/autogen:mbx", + "//sw/device/lib/dif/autogen:otbn", + "//sw/device/lib/dif/autogen:otp_ctrl", + "//sw/device/lib/dif/autogen:pinmux", + "//sw/device/lib/dif/autogen:pwrmgr", + "//sw/device/lib/dif/autogen:racl_ctrl", + "//sw/device/lib/dif/autogen:rom_ctrl", + "//sw/device/lib/dif/autogen:rstmgr", + "//sw/device/lib/dif/autogen:rv_plic", + "//sw/device/lib/dif/autogen:soc_dbg_ctrl", + "//sw/device/lib/dif/autogen:soc_proxy", + "//sw/device/lib/dif/autogen:spi_device", + "//sw/device/lib/dif/autogen:spi_host", + "//sw/device/lib/dif/autogen:sram_ctrl", + "//sw/device/lib/dif/autogen:uart", + "//sw/device/lib/runtime:log", + "//sw/device/lib/testing:alert_handler_testutils", + "//sw/device/lib/testing/test_framework:ottf_main", + ], +) diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/tests/alert_test.c b/hw/top_darjeeling_no_ibex/sw/autogen/tests/alert_test.c new file mode 100644 index 00000000000..5c4272d1685 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/tests/alert_test.c @@ -0,0 +1,928 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// clang-format off + +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex +#include "sw/device/lib/arch/boot_stage.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/autogen/dif_ac_range_check_autogen.h" +#include "sw/device/lib/dif/autogen/dif_aes_autogen.h" +#include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h" +#include "sw/device/lib/dif/autogen/dif_aon_timer_autogen.h" +#include "sw/device/lib/dif/autogen/dif_clkmgr_autogen.h" +#include "sw/device/lib/dif/autogen/dif_csrng_autogen.h" +#include "sw/device/lib/dif/autogen/dif_dma_autogen.h" +#include "sw/device/lib/dif/autogen/dif_edn_autogen.h" +#include "sw/device/lib/dif/autogen/dif_entropy_src_autogen.h" +#include "sw/device/lib/dif/autogen/dif_gpio_autogen.h" +#include "sw/device/lib/dif/autogen/dif_hmac_autogen.h" +#include "sw/device/lib/dif/autogen/dif_i2c_autogen.h" +#include "sw/device/lib/dif/autogen/dif_keymgr_dpe_autogen.h" +#include "sw/device/lib/dif/autogen/dif_kmac_autogen.h" +#include "sw/device/lib/dif/autogen/dif_lc_ctrl_autogen.h" +#include "sw/device/lib/dif/autogen/dif_mbx_autogen.h" +#include "sw/device/lib/dif/autogen/dif_otbn_autogen.h" +#include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h" +#include "sw/device/lib/dif/autogen/dif_pinmux_autogen.h" +#include "sw/device/lib/dif/autogen/dif_pwrmgr_autogen.h" +#include "sw/device/lib/dif/autogen/dif_racl_ctrl_autogen.h" +#include "sw/device/lib/dif/autogen/dif_rom_ctrl_autogen.h" +#include "sw/device/lib/dif/autogen/dif_rstmgr_autogen.h" +#include "sw/device/lib/dif/autogen/dif_rv_plic_autogen.h" +#include "sw/device/lib/dif/autogen/dif_soc_dbg_ctrl_autogen.h" +#include "sw/device/lib/dif/autogen/dif_soc_proxy_autogen.h" +#include "sw/device/lib/dif/autogen/dif_spi_device_autogen.h" +#include "sw/device/lib/dif/autogen/dif_spi_host_autogen.h" +#include "sw/device/lib/dif/autogen/dif_sram_ctrl_autogen.h" +#include "sw/device/lib/dif/autogen/dif_uart_autogen.h" +#include "sw/device/lib/testing/alert_handler_testutils.h" +#include "sw/device/lib/testing/test_framework/FreeRTOSConfig.h" +#include "sw/device/lib/testing/test_framework/check.h" +#include "sw/device/lib/testing/test_framework/ottf_test_config.h" + +#include "alert_handler_regs.h" // Generated. +#include "hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex.h" + +OTTF_DEFINE_TEST_CONFIG(); + +static dif_alert_handler_t alert_handler; +static dif_ac_range_check_t ac_range_check; +static dif_aes_t aes; +static dif_aon_timer_t aon_timer_aon; +static dif_clkmgr_t clkmgr_aon; +static dif_csrng_t csrng; +static dif_dma_t dma; +static dif_edn_t edn0; +static dif_edn_t edn1; +static dif_entropy_src_t entropy_src; +static dif_gpio_t gpio; +static dif_hmac_t hmac; +static dif_i2c_t i2c0; +static dif_keymgr_dpe_t keymgr_dpe; +static dif_kmac_t kmac; +static dif_lc_ctrl_t lc_ctrl; +static dif_mbx_t mbx0; +static dif_mbx_t mbx1; +static dif_mbx_t mbx2; +static dif_mbx_t mbx3; +static dif_mbx_t mbx4; +static dif_mbx_t mbx5; +static dif_mbx_t mbx6; +static dif_mbx_t mbx_jtag; +static dif_mbx_t mbx_pcie0; +static dif_mbx_t mbx_pcie1; +static dif_otbn_t otbn; +static dif_otp_ctrl_t otp_ctrl; +static dif_pinmux_t pinmux_aon; +static dif_pwrmgr_t pwrmgr_aon; +static dif_racl_ctrl_t racl_ctrl; +static dif_rom_ctrl_t rom_ctrl0; +static dif_rom_ctrl_t rom_ctrl1; +static dif_rstmgr_t rstmgr_aon; +static dif_rv_plic_t rv_plic; +static dif_soc_dbg_ctrl_t soc_dbg_ctrl; +static dif_soc_proxy_t soc_proxy; +static dif_spi_device_t spi_device; +static dif_spi_host_t spi_host0; +static dif_sram_ctrl_t sram_ctrl_main; +static dif_sram_ctrl_t sram_ctrl_mbox; +static dif_sram_ctrl_t sram_ctrl_ret_aon; +static dif_uart_t uart0; + +/** + * Initialize the peripherals used in this test. + */ +static void init_peripherals(void) { + mmio_region_t base_addr; + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_BASE_ADDR); + CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_BASE_ADDR); + CHECK_DIF_OK(dif_ac_range_check_init(base_addr, &ac_range_check)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_AES_BASE_ADDR); + CHECK_DIF_OK(dif_aes_init(base_addr, &aes)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_BASE_ADDR); + CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_CLKMGR_AON_BASE_ADDR); + CHECK_DIF_OK(dif_clkmgr_init(base_addr, &clkmgr_aon)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_CSRNG_BASE_ADDR); + CHECK_DIF_OK(dif_csrng_init(base_addr, &csrng)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_DMA_BASE_ADDR); + CHECK_DIF_OK(dif_dma_init(base_addr, &dma)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_EDN0_BASE_ADDR); + CHECK_DIF_OK(dif_edn_init(base_addr, &edn0)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_EDN1_BASE_ADDR); + CHECK_DIF_OK(dif_edn_init(base_addr, &edn1)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_BASE_ADDR); + CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_GPIO_BASE_ADDR); + CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_HMAC_BASE_ADDR); + CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_I2C0_BASE_ADDR); + CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_BASE_ADDR); + CHECK_DIF_OK(dif_keymgr_dpe_init(base_addr, &keymgr_dpe)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_KMAC_BASE_ADDR); + CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_BASE_ADDR); + CHECK_DIF_OK(dif_lc_ctrl_init(base_addr, &lc_ctrl)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX0_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx0)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX1_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx1)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX2_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx2)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX3_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx3)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX4_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx4)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX5_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx5)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX6_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx6)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_jtag)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_pcie0)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_pcie1)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_OTBN_BASE_ADDR); + CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_PINMUX_AON_BASE_ADDR); + CHECK_DIF_OK(dif_pinmux_init(base_addr, &pinmux_aon)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_PWRMGR_AON_BASE_ADDR); + CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr_aon)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_BASE_ADDR); + CHECK_DIF_OK(dif_racl_ctrl_init(base_addr, &racl_ctrl)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_BASE_ADDR); + CHECK_DIF_OK(dif_rom_ctrl_init(base_addr, &rom_ctrl0)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_BASE_ADDR); + CHECK_DIF_OK(dif_rom_ctrl_init(base_addr, &rom_ctrl1)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_RSTMGR_AON_BASE_ADDR); + CHECK_DIF_OK(dif_rstmgr_init(base_addr, &rstmgr_aon)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_RV_PLIC_BASE_ADDR); + CHECK_DIF_OK(dif_rv_plic_init(base_addr, &rv_plic)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_soc_dbg_ctrl_init(base_addr, &soc_dbg_ctrl)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_soc_proxy_init(base_addr, &soc_proxy)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SPI_DEVICE_BASE_ADDR); + CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SPI_HOST0_BASE_ADDR); + CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_BASE_ADDR); + CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_main)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_BASE_ADDR); + CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_mbox)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_BASE_ADDR); + CHECK_DIF_OK(dif_sram_ctrl_init(base_addr, &sram_ctrl_ret_aon)); + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_UART0_BASE_ADDR); + CHECK_DIF_OK(dif_uart_init(base_addr, &uart0)); + +} + +/** + * Configure the alert handler to escalate on alerts upto phase 1 (i.e. wipe + * secret) but not trigger reset. Then CPU can check if alert_handler triggers the correct + * alert_cause register. + */ +static void alert_handler_config(void) { + dif_alert_handler_alert_t alerts[ALERT_HANDLER_PARAM_N_ALERTS]; + dif_alert_handler_class_t alert_classes[ALERT_HANDLER_PARAM_N_ALERTS]; + + // Enable all incoming alerts and configure them to classa. + // This alert should never fire because we do not expect any incoming alerts. + for (dif_alert_handler_alert_t i = 0; i < ALERT_HANDLER_PARAM_N_ALERTS; ++i) { + alerts[i] = i; + alert_classes[i] = kDifAlertHandlerClassA; + } + + dif_alert_handler_escalation_phase_t esc_phases[] = { + {.phase = kDifAlertHandlerClassStatePhase0, + .signal = 0, + .duration_cycles = 2000}}; + + dif_alert_handler_class_config_t class_config = { + .auto_lock_accumulation_counter = kDifToggleDisabled, + .accumulator_threshold = 0, + .irq_deadline_cycles = 10000, + .escalation_phases = esc_phases, + .escalation_phases_len = ARRAYSIZE(esc_phases), + .crashdump_escalation_phase = kDifAlertHandlerClassStatePhase1, + }; + + dif_alert_handler_class_config_t class_configs[] = {class_config, + class_config}; + + dif_alert_handler_class_t classes[] = {kDifAlertHandlerClassA, + kDifAlertHandlerClassB}; + dif_alert_handler_config_t config = { + .alerts = alerts, + .alert_classes = alert_classes, + .alerts_len = ARRAYSIZE(alerts), + .classes = classes, + .class_configs = class_configs, + .classes_len = ARRAYSIZE(class_configs), + .ping_timeout = 1000, + }; + + CHECK_STATUS_OK(alert_handler_testutils_configure_all(&alert_handler, config, + kDifToggleEnabled)); +} + +// Trigger alert for each module by writing one to `alert_test` register. +// Then check alert_handler's alert_cause register to make sure the correct alert reaches +// alert_handler. +static void trigger_alert_test(void) { + bool is_cause; + dif_alert_handler_alert_t exp_alert; + + // Write ac_range_check's alert_test reg and check alert_cause. + for (dif_ac_range_check_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_ac_range_check_alert_force(&ac_range_check, kDifAcRangeCheckAlertRecovCtrlUpdateErr + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdAcRangeCheckRecovCtrlUpdateErr + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write aes's alert_test reg and check alert_cause. + for (dif_aes_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_aes_alert_force(&aes, kDifAesAlertRecovCtrlUpdateErr + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdAesRecovCtrlUpdateErr + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write aon_timer's alert_test reg and check alert_cause. + for (dif_aon_timer_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_aon_timer_alert_force(&aon_timer_aon, kDifAonTimerAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdAonTimerAonFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write clkmgr's alert_test reg and check alert_cause. + for (dif_clkmgr_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_clkmgr_alert_force(&clkmgr_aon, kDifClkmgrAlertRecovFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdClkmgrAonRecovFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write csrng's alert_test reg and check alert_cause. + for (dif_csrng_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_csrng_alert_force(&csrng, kDifCsrngAlertRecovAlert + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdCsrngRecovAlert + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write dma's alert_test reg and check alert_cause. + for (dif_dma_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_dma_alert_force(&dma, kDifDmaAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdDmaFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write edn's alert_test reg and check alert_cause. + for (dif_edn_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_edn_alert_force(&edn0, kDifEdnAlertRecovAlert + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdEdn0RecovAlert + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write edn's alert_test reg and check alert_cause. + for (dif_edn_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_edn_alert_force(&edn1, kDifEdnAlertRecovAlert + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdEdn1RecovAlert + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write entropy_src's alert_test reg and check alert_cause. + for (dif_entropy_src_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_entropy_src_alert_force(&entropy_src, kDifEntropySrcAlertRecovAlert + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdEntropySrcRecovAlert + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write gpio's alert_test reg and check alert_cause. + for (dif_gpio_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_gpio_alert_force(&gpio, kDifGpioAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdGpioFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write hmac's alert_test reg and check alert_cause. + for (dif_hmac_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_hmac_alert_force(&hmac, kDifHmacAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdHmacFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write i2c's alert_test reg and check alert_cause. + for (dif_i2c_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_i2c_alert_force(&i2c0, kDifI2cAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdI2c0FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write keymgr_dpe's alert_test reg and check alert_cause. + for (dif_keymgr_dpe_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_keymgr_dpe_alert_force(&keymgr_dpe, kDifKeymgrDpeAlertRecovOperationErr + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdKeymgrDpeRecovOperationErr + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write kmac's alert_test reg and check alert_cause. + for (dif_kmac_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_kmac_alert_force(&kmac, kDifKmacAlertRecovOperationErr + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdKmacRecovOperationErr + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write lc_ctrl's alert_test reg and check alert_cause. + for (dif_lc_ctrl_alert_t i = 0; i < 3; ++i) { + CHECK_DIF_OK(dif_lc_ctrl_alert_force(&lc_ctrl, kDifLcCtrlAlertFatalProgError + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdLcCtrlFatalProgError + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx0, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbx0FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx1, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbx1FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx2, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbx2FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx3, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbx3FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx4, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbx4FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx5, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbx5FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx6, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbx6FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx_jtag, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbxJtagFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx_pcie0, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbxPcie0FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write mbx's alert_test reg and check alert_cause. + for (dif_mbx_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_mbx_alert_force(&mbx_pcie1, kDifMbxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdMbxPcie1FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write otbn's alert_test reg and check alert_cause. + for (dif_otbn_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_otbn_alert_force(&otbn, kDifOtbnAlertFatal + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdOtbnFatal + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // TODO(lowrisc/opentitan#20348): Enable otp_ctrl when this is fixed. + if (kBootStage != kBootStageOwner) { + // Write otp_ctrl's alert_test reg and check alert_cause. + for (dif_otp_ctrl_alert_t i = 0; i < 5; ++i) { + CHECK_DIF_OK(dif_otp_ctrl_alert_force(&otp_ctrl, kDifOtpCtrlAlertFatalMacroError + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdOtpCtrlFatalMacroError + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + } + + // Write pinmux's alert_test reg and check alert_cause. + for (dif_pinmux_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_pinmux_alert_force(&pinmux_aon, kDifPinmuxAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdPinmuxAonFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write pwrmgr's alert_test reg and check alert_cause. + for (dif_pwrmgr_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_pwrmgr_alert_force(&pwrmgr_aon, kDifPwrmgrAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdPwrmgrAonFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write racl_ctrl's alert_test reg and check alert_cause. + for (dif_racl_ctrl_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_racl_ctrl_alert_force(&racl_ctrl, kDifRaclCtrlAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdRaclCtrlFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write rom_ctrl's alert_test reg and check alert_cause. + for (dif_rom_ctrl_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_rom_ctrl_alert_force(&rom_ctrl0, kDifRomCtrlAlertFatal + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdRomCtrl0Fatal + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write rom_ctrl's alert_test reg and check alert_cause. + for (dif_rom_ctrl_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_rom_ctrl_alert_force(&rom_ctrl1, kDifRomCtrlAlertFatal + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdRomCtrl1Fatal + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write rstmgr's alert_test reg and check alert_cause. + for (dif_rstmgr_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_rstmgr_alert_force(&rstmgr_aon, kDifRstmgrAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdRstmgrAonFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write rv_plic's alert_test reg and check alert_cause. + for (dif_rv_plic_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_rv_plic_alert_force(&rv_plic, kDifRvPlicAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdRvPlicFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write soc_dbg_ctrl's alert_test reg and check alert_cause. + for (dif_soc_dbg_ctrl_alert_t i = 0; i < 2; ++i) { + CHECK_DIF_OK(dif_soc_dbg_ctrl_alert_force(&soc_dbg_ctrl, kDifSocDbgCtrlAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdSocDbgCtrlFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write soc_proxy's alert_test reg and check alert_cause. + for (dif_soc_proxy_alert_t i = 0; i < 29; ++i) { + CHECK_DIF_OK(dif_soc_proxy_alert_force(&soc_proxy, kDifSocProxyAlertFatalAlertIntg + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertIntg + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write spi_device's alert_test reg and check alert_cause. + for (dif_spi_device_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_spi_device_alert_force(&spi_device, kDifSpiDeviceAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdSpiDeviceFatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write spi_host's alert_test reg and check alert_cause. + for (dif_spi_host_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_spi_host_alert_force(&spi_host0, kDifSpiHostAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdSpiHost0FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write sram_ctrl's alert_test reg and check alert_cause. + for (dif_sram_ctrl_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_main, kDifSramCtrlAlertFatalError + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdSramCtrlMainFatalError + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write sram_ctrl's alert_test reg and check alert_cause. + for (dif_sram_ctrl_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_mbox, kDifSramCtrlAlertFatalError + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdSramCtrlMboxFatalError + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write sram_ctrl's alert_test reg and check alert_cause. + for (dif_sram_ctrl_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_sram_ctrl_alert_force(&sram_ctrl_ret_aon, kDifSramCtrlAlertFatalError + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdSramCtrlRetAonFatalError + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } + + // Write uart's alert_test reg and check alert_cause. + for (dif_uart_alert_t i = 0; i < 1; ++i) { + CHECK_DIF_OK(dif_uart_alert_force(&uart0, kDifUartAlertFatalFault + i)); + + // Verify that alert handler received it. + exp_alert = kTopDarjeelingNoIbexAlertIdUart0FatalFault + i; + CHECK_DIF_OK(dif_alert_handler_alert_is_cause( + &alert_handler, exp_alert, &is_cause)); + CHECK(is_cause, "Expect alert %d!", exp_alert); + + // Clear alert cause register + CHECK_DIF_OK(dif_alert_handler_alert_acknowledge( + &alert_handler, exp_alert)); + } +} + +bool test_main(void) { + init_peripherals(); + alert_handler_config(); + trigger_alert_test(); + return true; +} diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/tests/plic_all_irqs_test.c b/hw/top_darjeeling_no_ibex/sw/autogen/tests/plic_all_irqs_test.c new file mode 100644 index 00000000000..e506ef7a12f --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/tests/plic_all_irqs_test.c @@ -0,0 +1,2310 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// clang-format off +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex +#include + +// This test should avoid otp_ctrl interrupts in rom_ext, since the rom +// extension configures CSR accesses to OTP and AST to become illegal. +// +// This test is getting too big so we need to split it up. To do so, +// each peripheral is given an ID (according to their alphabetical order) +// and we define TEST_MIN_IRQ_PERIPHERAL and TEST_MAX_IRQ_PERIPHERAL to +// choose which ones are being tested. + +#ifndef TEST_MIN_IRQ_PERIPHERAL +#define TEST_MIN_IRQ_PERIPHERAL 0 +#endif + +#ifndef TEST_MAX_IRQ_PERIPHERAL +#define TEST_MAX_IRQ_PERIPHERAL 21 +#endif + +#include "sw/device/lib/arch/boot_stage.h" +#include "sw/device/lib/base/csr.h" +#include "sw/device/lib/base/mmio.h" +#include "sw/device/lib/dif/autogen/dif_ac_range_check_autogen.h" +#include "sw/device/lib/dif/autogen/dif_alert_handler_autogen.h" +#include "sw/device/lib/dif/autogen/dif_aon_timer_autogen.h" +#include "sw/device/lib/dif/autogen/dif_csrng_autogen.h" +#include "sw/device/lib/dif/autogen/dif_dma_autogen.h" +#include "sw/device/lib/dif/autogen/dif_edn_autogen.h" +#include "sw/device/lib/dif/autogen/dif_entropy_src_autogen.h" +#include "sw/device/lib/dif/autogen/dif_gpio_autogen.h" +#include "sw/device/lib/dif/autogen/dif_hmac_autogen.h" +#include "sw/device/lib/dif/autogen/dif_i2c_autogen.h" +#include "sw/device/lib/dif/autogen/dif_keymgr_dpe_autogen.h" +#include "sw/device/lib/dif/autogen/dif_kmac_autogen.h" +#include "sw/device/lib/dif/autogen/dif_mbx_autogen.h" +#include "sw/device/lib/dif/autogen/dif_otbn_autogen.h" +#include "sw/device/lib/dif/autogen/dif_otp_ctrl_autogen.h" +#include "sw/device/lib/dif/autogen/dif_pwrmgr_autogen.h" +#include "sw/device/lib/dif/autogen/dif_racl_ctrl_autogen.h" +#include "sw/device/lib/dif/autogen/dif_rv_plic_autogen.h" +#include "sw/device/lib/dif/autogen/dif_soc_proxy_autogen.h" +#include "sw/device/lib/dif/autogen/dif_spi_device_autogen.h" +#include "sw/device/lib/dif/autogen/dif_spi_host_autogen.h" +#include "sw/device/lib/dif/autogen/dif_uart_autogen.h" +#include "sw/device/lib/runtime/ibex.h" +#include "sw/device/lib/runtime/irq.h" +#include "sw/device/lib/runtime/log.h" +#include "sw/device/lib/testing/rv_plic_testutils.h" +#include "sw/device/lib/testing/test_framework/check.h" +#include "sw/device/lib/testing/test_framework/ottf_main.h" +#include "sw/device/lib/testing/test_framework/status.h" + +#include "hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex.h" + +#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL +static dif_ac_range_check_t ac_range_check; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +static dif_alert_handler_t alert_handler; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +static dif_aon_timer_t aon_timer_aon; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +static dif_csrng_t csrng; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +static dif_dma_t dma; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +static dif_edn_t edn0; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +static dif_edn_t edn1; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +static dif_entropy_src_t entropy_src; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +static dif_gpio_t gpio; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +static dif_hmac_t hmac; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +static dif_i2c_t i2c0; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +static dif_keymgr_dpe_t keymgr_dpe; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +static dif_kmac_t kmac; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx0; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx1; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx2; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx3; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx4; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx5; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx6; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx_jtag; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx_pcie0; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static dif_mbx_t mbx_pcie1; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +static dif_otbn_t otbn; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +static dif_otp_ctrl_t otp_ctrl; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +static dif_pwrmgr_t pwrmgr_aon; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +static dif_racl_ctrl_t racl_ctrl; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +static dif_soc_proxy_t soc_proxy; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +static dif_spi_device_t spi_device; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +static dif_spi_host_t spi_host0; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +static dif_uart_t uart0; +#endif + +static dif_rv_plic_t plic; +static const top_darjeeling_no_ibex_plic_target_t kHart = kTopDarjeeling_no_ibexPlicTargetIbex0; + +/** + * Flag indicating which peripheral is under test. + * + * Declared volatile because it is referenced in the main program flow as well + * as the ISR. + */ +static volatile top_darjeeling_no_ibex_plic_peripheral_t peripheral_expected; + +/** + * Flags indicating the IRQ expected to have triggered and serviced within the + * peripheral. + * + * Declared volatile because it is referenced in the main program flow as well + * as the ISR. + */ + +#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_ac_range_check_irq_t ac_range_check_irq_expected; +static volatile dif_ac_range_check_irq_t ac_range_check_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_alert_handler_irq_t alert_handler_irq_expected; +static volatile dif_alert_handler_irq_t alert_handler_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_aon_timer_irq_t aon_timer_irq_expected; +static volatile dif_aon_timer_irq_t aon_timer_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_csrng_irq_t csrng_irq_expected; +static volatile dif_csrng_irq_t csrng_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_dma_irq_t dma_irq_expected; +static volatile dif_dma_irq_t dma_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_edn_irq_t edn_irq_expected; +static volatile dif_edn_irq_t edn_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_entropy_src_irq_t entropy_src_irq_expected; +static volatile dif_entropy_src_irq_t entropy_src_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_gpio_irq_t gpio_irq_expected; +static volatile dif_gpio_irq_t gpio_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_hmac_irq_t hmac_irq_expected; +static volatile dif_hmac_irq_t hmac_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_i2c_irq_t i2c_irq_expected; +static volatile dif_i2c_irq_t i2c_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_keymgr_dpe_irq_t keymgr_dpe_irq_expected; +static volatile dif_keymgr_dpe_irq_t keymgr_dpe_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_kmac_irq_t kmac_irq_expected; +static volatile dif_kmac_irq_t kmac_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_mbx_irq_t mbx_irq_expected; +static volatile dif_mbx_irq_t mbx_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_otbn_irq_t otbn_irq_expected; +static volatile dif_otbn_irq_t otbn_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_expected; +static volatile dif_otp_ctrl_irq_t otp_ctrl_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_pwrmgr_irq_t pwrmgr_irq_expected; +static volatile dif_pwrmgr_irq_t pwrmgr_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_racl_ctrl_irq_t racl_ctrl_irq_expected; +static volatile dif_racl_ctrl_irq_t racl_ctrl_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_soc_proxy_irq_t soc_proxy_irq_expected; +static volatile dif_soc_proxy_irq_t soc_proxy_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_spi_device_irq_t spi_device_irq_expected; +static volatile dif_spi_device_irq_t spi_device_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_spi_host_irq_t spi_host_irq_expected; +static volatile dif_spi_host_irq_t spi_host_irq_serviced; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL +static volatile dif_uart_irq_t uart_irq_expected; +static volatile dif_uart_irq_t uart_irq_serviced; +#endif + +/** + * Provides external IRQ handling for this test. + * + * This function overrides the default OTTF external ISR. + * + * For each IRQ, it performs the following: + * 1. Claims the IRQ fired (finds PLIC IRQ index). + * 2. Checks that the index belongs to the expected peripheral. + * 3. Checks that the correct and the only IRQ from the expected peripheral + * triggered. + * 4. Clears the IRQ at the peripheral. + * 5. Completes the IRQ service at PLIC. + */ +void ottf_external_isr(uint32_t *exc_info) { + dif_rv_plic_irq_id_t plic_irq_id; + CHECK_DIF_OK(dif_rv_plic_irq_claim(&plic, kHart, &plic_irq_id)); + + top_darjeeling_no_ibex_plic_peripheral_t peripheral = (top_darjeeling_no_ibex_plic_peripheral_t) + top_darjeeling_no_ibex_plic_interrupt_for_peripheral[plic_irq_id]; + CHECK(peripheral == peripheral_expected, + "Interrupt from incorrect peripheral: exp = %d, obs = %d", + peripheral_expected, peripheral); + + switch (peripheral) { +#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralAcRangeCheck: { + dif_ac_range_check_irq_t irq = + (dif_ac_range_check_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdAcRangeCheckDenyCntReached); + CHECK(irq == ac_range_check_irq_expected, + "Incorrect ac_range_check IRQ triggered: exp = %d, obs = %d", + ac_range_check_irq_expected, irq); + ac_range_check_irq_serviced = irq; + + dif_ac_range_check_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_ac_range_check_irq_get_state(&ac_range_check, &snapshot)); + CHECK(snapshot == (dif_ac_range_check_irq_state_snapshot_t)(1 << irq), + "Only ac_range_check IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + if (0x1 & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_ac_range_check_irq_force(&ac_range_check, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x0 & (1 << irq))) { + CHECK_DIF_OK(dif_ac_range_check_irq_set_enabled(&ac_range_check, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_ac_range_check_irq_acknowledge(&ac_range_check, irq)); + } + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralAlertHandler: { + dif_alert_handler_irq_t irq = + (dif_alert_handler_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdAlertHandlerClassa); + CHECK(irq == alert_handler_irq_expected, + "Incorrect alert_handler IRQ triggered: exp = %d, obs = %d", + alert_handler_irq_expected, irq); + alert_handler_irq_serviced = irq; + + dif_alert_handler_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_alert_handler_irq_get_state(&alert_handler, &snapshot)); + CHECK(snapshot == (dif_alert_handler_irq_state_snapshot_t)(1 << irq), + "Only alert_handler IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_alert_handler_irq_acknowledge(&alert_handler, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralAonTimerAon: { + dif_aon_timer_irq_t irq = + (dif_aon_timer_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdAonTimerAonWkupTimerExpired); + CHECK(irq == aon_timer_irq_expected, + "Incorrect aon_timer_aon IRQ triggered: exp = %d, obs = %d", + aon_timer_irq_expected, irq); + aon_timer_irq_serviced = irq; + + dif_aon_timer_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_aon_timer_irq_get_state(&aon_timer_aon, &snapshot)); + CHECK(snapshot == (dif_aon_timer_irq_state_snapshot_t)(1 << irq), + "Only aon_timer_aon IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_aon_timer_irq_acknowledge(&aon_timer_aon, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralCsrng: { + dif_csrng_irq_t irq = + (dif_csrng_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdCsrngCsCmdReqDone); + CHECK(irq == csrng_irq_expected, + "Incorrect csrng IRQ triggered: exp = %d, obs = %d", + csrng_irq_expected, irq); + csrng_irq_serviced = irq; + + dif_csrng_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_csrng_irq_get_state(&csrng, &snapshot)); + CHECK(snapshot == (dif_csrng_irq_state_snapshot_t)(1 << irq), + "Only csrng IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_csrng_irq_acknowledge(&csrng, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralDma: { + dif_dma_irq_t irq = + (dif_dma_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdDmaDmaDone); + CHECK(irq == dma_irq_expected, + "Incorrect dma IRQ triggered: exp = %d, obs = %d", + dma_irq_expected, irq); + dma_irq_serviced = irq; + + dif_dma_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_dma_irq_get_state(&dma, &snapshot)); + CHECK(snapshot == (dif_dma_irq_state_snapshot_t)(1 << irq), + "Only dma IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + if (0x7 & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_dma_irq_force(&dma, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x0 & (1 << irq))) { + CHECK_DIF_OK(dif_dma_irq_set_enabled(&dma, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_dma_irq_acknowledge(&dma, irq)); + } + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralEdn0: { + dif_edn_irq_t irq = + (dif_edn_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdEdn0EdnCmdReqDone); + CHECK(irq == edn_irq_expected, + "Incorrect edn0 IRQ triggered: exp = %d, obs = %d", + edn_irq_expected, irq); + edn_irq_serviced = irq; + + dif_edn_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_edn_irq_get_state(&edn0, &snapshot)); + CHECK(snapshot == (dif_edn_irq_state_snapshot_t)(1 << irq), + "Only edn0 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_edn_irq_acknowledge(&edn0, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralEdn1: { + dif_edn_irq_t irq = + (dif_edn_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdEdn1EdnCmdReqDone); + CHECK(irq == edn_irq_expected, + "Incorrect edn1 IRQ triggered: exp = %d, obs = %d", + edn_irq_expected, irq); + edn_irq_serviced = irq; + + dif_edn_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_edn_irq_get_state(&edn1, &snapshot)); + CHECK(snapshot == (dif_edn_irq_state_snapshot_t)(1 << irq), + "Only edn1 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_edn_irq_acknowledge(&edn1, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralEntropySrc: { + dif_entropy_src_irq_t irq = + (dif_entropy_src_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdEntropySrcEsEntropyValid); + CHECK(irq == entropy_src_irq_expected, + "Incorrect entropy_src IRQ triggered: exp = %d, obs = %d", + entropy_src_irq_expected, irq); + entropy_src_irq_serviced = irq; + + dif_entropy_src_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_entropy_src_irq_get_state(&entropy_src, &snapshot)); + CHECK(snapshot == (dif_entropy_src_irq_state_snapshot_t)(1 << irq), + "Only entropy_src IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_entropy_src_irq_acknowledge(&entropy_src, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralGpio: { + dif_gpio_irq_t irq = + (dif_gpio_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdGpioGpio0); + CHECK(irq == gpio_irq_expected, + "Incorrect gpio IRQ triggered: exp = %d, obs = %d", + gpio_irq_expected, irq); + gpio_irq_serviced = irq; + + dif_gpio_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_gpio_irq_get_state(&gpio, &snapshot)); + CHECK(snapshot == (dif_gpio_irq_state_snapshot_t)(1 << irq), + "Only gpio IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_gpio_irq_acknowledge(&gpio, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralHmac: { + dif_hmac_irq_t irq = + (dif_hmac_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdHmacHmacDone); + CHECK(irq == hmac_irq_expected, + "Incorrect hmac IRQ triggered: exp = %d, obs = %d", + hmac_irq_expected, irq); + hmac_irq_serviced = irq; + + dif_hmac_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_hmac_irq_get_state(&hmac, &snapshot)); + CHECK(snapshot == (dif_hmac_irq_state_snapshot_t)(1 << irq), + "Only hmac IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + if (0x2 & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_hmac_irq_force(&hmac, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x0 & (1 << irq))) { + CHECK_DIF_OK(dif_hmac_irq_set_enabled(&hmac, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_hmac_irq_acknowledge(&hmac, irq)); + } + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralI2c0: { + dif_i2c_irq_t irq = + (dif_i2c_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdI2c0FmtThreshold); + CHECK(irq == i2c_irq_expected, + "Incorrect i2c0 IRQ triggered: exp = %d, obs = %d", + i2c_irq_expected, irq); + i2c_irq_serviced = irq; + + dif_i2c_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_i2c_irq_get_state(&i2c0, &snapshot)); + CHECK(snapshot == (dif_i2c_irq_state_snapshot_t)(1 << irq), + "Only i2c0 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + if (0x1c17 & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_i2c_irq_force(&i2c0, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x0 & (1 << irq))) { + CHECK_DIF_OK(dif_i2c_irq_set_enabled(&i2c0, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_i2c_irq_acknowledge(&i2c0, irq)); + } + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralKeymgrDpe: { + dif_keymgr_dpe_irq_t irq = + (dif_keymgr_dpe_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdKeymgrDpeOpDone); + CHECK(irq == keymgr_dpe_irq_expected, + "Incorrect keymgr_dpe IRQ triggered: exp = %d, obs = %d", + keymgr_dpe_irq_expected, irq); + keymgr_dpe_irq_serviced = irq; + + dif_keymgr_dpe_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_keymgr_dpe_irq_get_state(&keymgr_dpe, &snapshot)); + CHECK(snapshot == (dif_keymgr_dpe_irq_state_snapshot_t)(1 << irq), + "Only keymgr_dpe IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_keymgr_dpe_irq_acknowledge(&keymgr_dpe, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralKmac: { + dif_kmac_irq_t irq = + (dif_kmac_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdKmacKmacDone); + CHECK(irq == kmac_irq_expected, + "Incorrect kmac IRQ triggered: exp = %d, obs = %d", + kmac_irq_expected, irq); + kmac_irq_serviced = irq; + + dif_kmac_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_kmac_irq_get_state(&kmac, &snapshot)); + CHECK(snapshot == (dif_kmac_irq_state_snapshot_t)(1 << irq), + "Only kmac IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + if (0x2 & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_kmac_irq_force(&kmac, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x0 & (1 << irq))) { + CHECK_DIF_OK(dif_kmac_irq_set_enabled(&kmac, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_kmac_irq_acknowledge(&kmac, irq)); + } + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbx0: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbx0MbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx0 IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx0, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx0 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx0, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbx1: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbx1MbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx1 IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx1, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx1 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx1, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbx2: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbx2MbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx2 IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx2, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx2 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx2, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbx3: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbx3MbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx3 IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx3, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx3 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx3, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbx4: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbx4MbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx4 IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx4, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx4 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx4, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbx5: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbx5MbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx5 IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx5, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx5 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx5, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbx6: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbx6MbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx6 IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx6, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx6 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx6, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbxJtag: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbxJtagMbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx_jtag IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx_jtag, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx_jtag IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx_jtag, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbxPcie0: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbxPcie0MbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx_pcie0 IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx_pcie0, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx_pcie0 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx_pcie0, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralMbxPcie1: { + dif_mbx_irq_t irq = + (dif_mbx_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdMbxPcie1MbxReady); + CHECK(irq == mbx_irq_expected, + "Incorrect mbx_pcie1 IRQ triggered: exp = %d, obs = %d", + mbx_irq_expected, irq); + mbx_irq_serviced = irq; + + dif_mbx_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_mbx_irq_get_state(&mbx_pcie1, &snapshot)); + CHECK(snapshot == (dif_mbx_irq_state_snapshot_t)(1 << irq), + "Only mbx_pcie1 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_mbx_irq_acknowledge(&mbx_pcie1, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralOtbn: { + dif_otbn_irq_t irq = + (dif_otbn_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdOtbnDone); + CHECK(irq == otbn_irq_expected, + "Incorrect otbn IRQ triggered: exp = %d, obs = %d", + otbn_irq_expected, irq); + otbn_irq_serviced = irq; + + dif_otbn_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_otbn_irq_get_state(&otbn, &snapshot)); + CHECK(snapshot == (dif_otbn_irq_state_snapshot_t)(1 << irq), + "Only otbn IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_otbn_irq_acknowledge(&otbn, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralOtpCtrl: { + dif_otp_ctrl_irq_t irq = + (dif_otp_ctrl_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdOtpCtrlOtpOperationDone); + CHECK(irq == otp_ctrl_irq_expected, + "Incorrect otp_ctrl IRQ triggered: exp = %d, obs = %d", + otp_ctrl_irq_expected, irq); + otp_ctrl_irq_serviced = irq; + + dif_otp_ctrl_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_otp_ctrl_irq_get_state(&otp_ctrl, &snapshot)); + CHECK(snapshot == (dif_otp_ctrl_irq_state_snapshot_t)(1 << irq), + "Only otp_ctrl IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge(&otp_ctrl, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralPwrmgrAon: { + dif_pwrmgr_irq_t irq = + (dif_pwrmgr_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdPwrmgrAonWakeup); + CHECK(irq == pwrmgr_irq_expected, + "Incorrect pwrmgr_aon IRQ triggered: exp = %d, obs = %d", + pwrmgr_irq_expected, irq); + pwrmgr_irq_serviced = irq; + + dif_pwrmgr_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_pwrmgr_irq_get_state(&pwrmgr_aon, &snapshot)); + CHECK(snapshot == (dif_pwrmgr_irq_state_snapshot_t)(1 << irq), + "Only pwrmgr_aon IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge(&pwrmgr_aon, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralRaclCtrl: { + dif_racl_ctrl_irq_t irq = + (dif_racl_ctrl_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdRaclCtrlRaclError); + CHECK(irq == racl_ctrl_irq_expected, + "Incorrect racl_ctrl IRQ triggered: exp = %d, obs = %d", + racl_ctrl_irq_expected, irq); + racl_ctrl_irq_serviced = irq; + + dif_racl_ctrl_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_racl_ctrl_irq_get_state(&racl_ctrl, &snapshot)); + CHECK(snapshot == (dif_racl_ctrl_irq_state_snapshot_t)(1 << irq), + "Only racl_ctrl IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + if (0x1 & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_racl_ctrl_irq_force(&racl_ctrl, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x0 & (1 << irq))) { + CHECK_DIF_OK(dif_racl_ctrl_irq_set_enabled(&racl_ctrl, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_racl_ctrl_irq_acknowledge(&racl_ctrl, irq)); + } + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralSocProxy: { + dif_soc_proxy_irq_t irq = + (dif_soc_proxy_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal0); + CHECK(irq == soc_proxy_irq_expected, + "Incorrect soc_proxy IRQ triggered: exp = %d, obs = %d", + soc_proxy_irq_expected, irq); + soc_proxy_irq_serviced = irq; + + dif_soc_proxy_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_soc_proxy_irq_get_state(&soc_proxy, &snapshot)); + CHECK(snapshot == (dif_soc_proxy_irq_state_snapshot_t)(1 << irq), + "Only soc_proxy IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + CHECK_DIF_OK(dif_soc_proxy_irq_acknowledge(&soc_proxy, irq)); + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralSpiDevice: { + dif_spi_device_irq_t irq = + (dif_spi_device_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty); + CHECK(irq == spi_device_irq_expected, + "Incorrect spi_device IRQ triggered: exp = %d, obs = %d", + spi_device_irq_expected, irq); + spi_device_irq_serviced = irq; + + dif_spi_device_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_spi_device_irq_get_state(&spi_device, &snapshot)); + CHECK(snapshot == (dif_spi_device_irq_state_snapshot_t)(1 << irq), + "Only spi_device IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + if (0x20 & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_spi_device_irq_force(&spi_device, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x0 & (1 << irq))) { + CHECK_DIF_OK(dif_spi_device_irq_set_enabled(&spi_device, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_spi_device_irq_acknowledge(&spi_device, irq)); + } + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralSpiHost0: { + dif_spi_host_irq_t irq = + (dif_spi_host_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdSpiHost0Error); + CHECK(irq == spi_host_irq_expected, + "Incorrect spi_host0 IRQ triggered: exp = %d, obs = %d", + spi_host_irq_expected, irq); + spi_host_irq_serviced = irq; + + dif_spi_host_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_spi_host_irq_get_state(&spi_host0, &snapshot)); + CHECK(snapshot == (dif_spi_host_irq_state_snapshot_t)(1 << irq), + "Only spi_host0 IRQ %d expected to fire. Actual interrupt " + "status = %x", + irq, snapshot); + + if (0x2 & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host0, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x0 & (1 << irq))) { + CHECK_DIF_OK(dif_spi_host_irq_set_enabled(&spi_host0, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_spi_host_irq_acknowledge(&spi_host0, irq)); + } + break; + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL + case kTopDarjeelingNoIbexPlicPeripheralUart0: { + dif_uart_irq_t irq = + (dif_uart_irq_t)(plic_irq_id - + (dif_rv_plic_irq_id_t) + kTopDarjeelingNoIbexPlicIrqIdUart0TxWatermark); + CHECK(irq == uart_irq_expected, + "Incorrect uart0 IRQ triggered: exp = %d, obs = %d", + uart_irq_expected, irq); + uart_irq_serviced = irq; + + dif_uart_irq_state_snapshot_t snapshot; + CHECK_DIF_OK(dif_uart_irq_get_state(&uart0, &snapshot)); + CHECK(snapshot == (dif_uart_irq_state_snapshot_t)((1 << irq) | 0x101), + "Expected uart0 interrupt status %x. Actual interrupt " + "status = %x", + (1 << irq) | 0x101, snapshot); + + if (0x103 & (1 << irq)) { + // We do not acknowledge status type interrupt at the IP side, but we + // need to clear the test force register. + CHECK_DIF_OK(dif_uart_irq_force(&uart0, irq, false)); + // In case this status interrupt is asserted by default, we also + // disable it at this point so that it does not interfere with the + // rest of the test. + if ((0x101 & (1 << irq))) { + CHECK_DIF_OK(dif_uart_irq_set_enabled(&uart0, irq, false)); + } + } else { + // We acknowledge event type interrupt. + CHECK_DIF_OK(dif_uart_irq_acknowledge(&uart0, irq)); + } + break; + } +#endif + + default: + LOG_FATAL("ISR is not implemented!"); + test_status_set(kTestStatusFailed); + } + // Complete the IRQ at PLIC. + CHECK_DIF_OK(dif_rv_plic_irq_complete(&plic, kHart, plic_irq_id)); +} + +/** + * Initializes the handles to all peripherals. + */ +static void peripherals_init(void) { + mmio_region_t base_addr; + +#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_BASE_ADDR); + CHECK_DIF_OK(dif_ac_range_check_init(base_addr, &ac_range_check)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_BASE_ADDR); + CHECK_DIF_OK(dif_alert_handler_init(base_addr, &alert_handler)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_BASE_ADDR); + CHECK_DIF_OK(dif_aon_timer_init(base_addr, &aon_timer_aon)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_CSRNG_BASE_ADDR); + CHECK_DIF_OK(dif_csrng_init(base_addr, &csrng)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_DMA_BASE_ADDR); + CHECK_DIF_OK(dif_dma_init(base_addr, &dma)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_EDN0_BASE_ADDR); + CHECK_DIF_OK(dif_edn_init(base_addr, &edn0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_EDN1_BASE_ADDR); + CHECK_DIF_OK(dif_edn_init(base_addr, &edn1)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_BASE_ADDR); + CHECK_DIF_OK(dif_entropy_src_init(base_addr, &entropy_src)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_GPIO_BASE_ADDR); + CHECK_DIF_OK(dif_gpio_init(base_addr, &gpio)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_HMAC_BASE_ADDR); + CHECK_DIF_OK(dif_hmac_init(base_addr, &hmac)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_I2C0_BASE_ADDR); + CHECK_DIF_OK(dif_i2c_init(base_addr, &i2c0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_BASE_ADDR); + CHECK_DIF_OK(dif_keymgr_dpe_init(base_addr, &keymgr_dpe)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_KMAC_BASE_ADDR); + CHECK_DIF_OK(dif_kmac_init(base_addr, &kmac)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX0_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX1_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx1)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX2_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx2)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX3_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx3)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX4_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx4)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX5_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx5)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX6_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx6)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_jtag)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_pcie0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_mbx_init(base_addr, &mbx_pcie1)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_OTBN_BASE_ADDR); + CHECK_DIF_OK(dif_otbn_init(base_addr, &otbn)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_otp_ctrl_init(base_addr, &otp_ctrl)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_PWRMGR_AON_BASE_ADDR); + CHECK_DIF_OK(dif_pwrmgr_init(base_addr, &pwrmgr_aon)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_BASE_ADDR); + CHECK_DIF_OK(dif_racl_ctrl_init(base_addr, &racl_ctrl)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_BASE_ADDR); + CHECK_DIF_OK(dif_soc_proxy_init(base_addr, &soc_proxy)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SPI_DEVICE_BASE_ADDR); + CHECK_DIF_OK(dif_spi_device_init(base_addr, &spi_device)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_SPI_HOST0_BASE_ADDR); + CHECK_DIF_OK(dif_spi_host_init(base_addr, &spi_host0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_UART0_BASE_ADDR); + CHECK_DIF_OK(dif_uart_init(base_addr, &uart0)); +#endif + + base_addr = mmio_region_from_addr(TOP_DARJEELING_NO_IBEX_RV_PLIC_BASE_ADDR); + CHECK_DIF_OK(dif_rv_plic_init(base_addr, &plic)); +} + +/** + * Clears pending IRQs in all peripherals. + */ +static void peripheral_irqs_clear(void) { +#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_ac_range_check_irq_acknowledge_all(&ac_range_check)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_alert_handler_irq_acknowledge_all(&alert_handler)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_aon_timer_irq_acknowledge_all(&aon_timer_aon)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_csrng_irq_acknowledge_all(&csrng)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_dma_irq_acknowledge_all(&dma)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_edn_irq_acknowledge_all(&edn1)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_entropy_src_irq_acknowledge_all(&entropy_src)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_gpio_irq_acknowledge_all(&gpio)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_hmac_irq_acknowledge_all(&hmac)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_keymgr_dpe_irq_acknowledge_all(&keymgr_dpe)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_kmac_irq_acknowledge_all(&kmac)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx1)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx2)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx3)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx4)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx5)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx6)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx_jtag)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx_pcie0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_acknowledge_all(&mbx_pcie1)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_otbn_irq_acknowledge_all(&otbn)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL + if (kBootStage != kBootStageOwner) { + CHECK_DIF_OK(dif_otp_ctrl_irq_acknowledge_all(&otp_ctrl)); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_pwrmgr_irq_acknowledge_all(&pwrmgr_aon)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_racl_ctrl_irq_acknowledge_all(&racl_ctrl)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_soc_proxy_irq_acknowledge_all(&soc_proxy)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_spi_device_irq_acknowledge_all(&spi_device)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host0)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_uart_irq_acknowledge_all(&uart0)); +#endif +} + +/** + * Enables all IRQs in all peripherals. + */ +static void peripheral_irqs_enable(void) { +#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + dif_ac_range_check_irq_state_snapshot_t ac_range_check_irqs = + (dif_ac_range_check_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + dif_alert_handler_irq_state_snapshot_t alert_handler_irqs = + (dif_alert_handler_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + dif_csrng_irq_state_snapshot_t csrng_irqs = + (dif_csrng_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + dif_dma_irq_state_snapshot_t dma_irqs = + (dif_dma_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + dif_edn_irq_state_snapshot_t edn_irqs = + (dif_edn_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL + dif_entropy_src_irq_state_snapshot_t entropy_src_irqs = + (dif_entropy_src_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + dif_gpio_irq_state_snapshot_t gpio_irqs = + (dif_gpio_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL + dif_hmac_irq_state_snapshot_t hmac_irqs = + (dif_hmac_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + dif_i2c_irq_state_snapshot_t i2c_irqs = + (dif_i2c_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL + dif_keymgr_dpe_irq_state_snapshot_t keymgr_dpe_irqs = + (dif_keymgr_dpe_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL + dif_kmac_irq_state_snapshot_t kmac_irqs = + (dif_kmac_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + dif_mbx_irq_state_snapshot_t mbx_irqs = + (dif_mbx_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL + dif_otbn_irq_state_snapshot_t otbn_irqs = + (dif_otbn_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL + dif_otp_ctrl_irq_state_snapshot_t otp_ctrl_irqs = + (dif_otp_ctrl_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + dif_pwrmgr_irq_state_snapshot_t pwrmgr_irqs = + (dif_pwrmgr_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL + dif_racl_ctrl_irq_state_snapshot_t racl_ctrl_irqs = + (dif_racl_ctrl_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL + dif_soc_proxy_irq_state_snapshot_t soc_proxy_irqs = + (dif_soc_proxy_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL + dif_spi_device_irq_state_snapshot_t spi_device_irqs = + (dif_spi_device_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL + dif_spi_host_irq_state_snapshot_t spi_host_irqs = + (dif_spi_host_irq_state_snapshot_t)0xffffffff; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL + // Note: this peripheral contains status interrupts that are asserted by + // default. Therefore, not all interrupts are enabled here, since that + // would interfere with this test. Instead, these interrupts are enabled on + // demand once they are being tested. + dif_uart_irq_state_snapshot_t uart_irqs = + (dif_uart_irq_state_snapshot_t)0xfffffefe; +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_ac_range_check_irq_restore_all(&ac_range_check, &ac_range_check_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_alert_handler_irq_restore_all(&alert_handler, &alert_handler_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_csrng_irq_restore_all(&csrng, &csrng_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_dma_irq_restore_all(&dma, &dma_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_edn_irq_restore_all(&edn0, &edn_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_edn_irq_restore_all(&edn1, &edn_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_entropy_src_irq_restore_all(&entropy_src, &entropy_src_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_gpio_irq_restore_all(&gpio, &gpio_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_hmac_irq_restore_all(&hmac, &hmac_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_i2c_irq_restore_all(&i2c0, &i2c_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_keymgr_dpe_irq_restore_all(&keymgr_dpe, &keymgr_dpe_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_kmac_irq_restore_all(&kmac, &kmac_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx0, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx1, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx2, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx3, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx4, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx5, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx6, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx_jtag, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx_pcie0, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_mbx_irq_restore_all(&mbx_pcie1, &mbx_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_otbn_irq_restore_all(&otbn, &otbn_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL + if (kBootStage != kBootStageOwner) { + CHECK_DIF_OK(dif_otp_ctrl_irq_restore_all(&otp_ctrl, &otp_ctrl_irqs)); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_pwrmgr_irq_restore_all(&pwrmgr_aon, &pwrmgr_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_racl_ctrl_irq_restore_all(&racl_ctrl, &racl_ctrl_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_soc_proxy_irq_restore_all(&soc_proxy, &soc_proxy_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_spi_device_irq_restore_all(&spi_device, &spi_device_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL + CHECK_DIF_OK(dif_spi_host_irq_restore_all(&spi_host0, &spi_host_irqs)); +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL + // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference + // from the logging facility. + if (kDeviceType == kDeviceSimDV) { + CHECK_DIF_OK(dif_uart_irq_restore_all(&uart0, &uart_irqs)); + } +#endif +} + +/** + * Triggers all IRQs in all peripherals one by one. + * + * Walks through all instances of all peripherals and triggers an interrupt one + * by one, by forcing with the `intr_test` CSR. On trigger, the CPU instantly + * jumps into the ISR. The main flow of execution thus proceeds to check that + * the correct IRQ was serviced immediately. The ISR, in turn checks if the + * expected IRQ from the expected peripheral triggered. + */ +static void peripheral_irqs_trigger(void) { + unsigned int status_default_mask; + // Depending on the build configuration, this variable may show up as unused + // in the clang linter. This statement waives that error. + (void)status_default_mask; + +#if TEST_MIN_IRQ_PERIPHERAL <= 0 && 0 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralAcRangeCheck; + status_default_mask = 0x0; + for (dif_ac_range_check_irq_t irq = kDifAcRangeCheckIrqDenyCntReached; irq <= kDifAcRangeCheckIrqDenyCntReached; + ++irq) { + ac_range_check_irq_expected = irq; + LOG_INFO("Triggering ac_range_check IRQ %d.", irq); + CHECK_DIF_OK(dif_ac_range_check_irq_force(&ac_range_check, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_ac_range_check_irq_set_enabled(&ac_range_check, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(ac_range_check_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from ac_range_check is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 1 && 1 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralAlertHandler; + for (dif_alert_handler_irq_t irq = kDifAlertHandlerIrqClassa; irq <= kDifAlertHandlerIrqClassd; + ++irq) { + alert_handler_irq_expected = irq; + LOG_INFO("Triggering alert_handler IRQ %d.", irq); + CHECK_DIF_OK(dif_alert_handler_irq_force(&alert_handler, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(alert_handler_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from alert_handler is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 2 && 2 < TEST_MAX_IRQ_PERIPHERAL + // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference + // from the logging facility. + // aon_timer may generate a NMI instead of a PLIC IRQ depending on the ROM. + // Since there are other tests covering this already, we just skip this for + // non-DV setups. + if (kDeviceType == kDeviceSimDV) { + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralAonTimerAon; + for (dif_aon_timer_irq_t irq = kDifAonTimerIrqWkupTimerExpired; irq <= kDifAonTimerIrqWdogTimerBark; + ++irq) { + aon_timer_irq_expected = irq; + LOG_INFO("Triggering aon_timer_aon IRQ %d.", irq); + CHECK_DIF_OK(dif_aon_timer_irq_force(&aon_timer_aon, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(aon_timer_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from aon_timer_aon is serviced.", irq); + } + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 3 && 3 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralCsrng; + for (dif_csrng_irq_t irq = kDifCsrngIrqCsCmdReqDone; irq <= kDifCsrngIrqCsFatalErr; + ++irq) { + csrng_irq_expected = irq; + LOG_INFO("Triggering csrng IRQ %d.", irq); + CHECK_DIF_OK(dif_csrng_irq_force(&csrng, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(csrng_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from csrng is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 4 && 4 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralDma; + status_default_mask = 0x0; + for (dif_dma_irq_t irq = kDifDmaIrqDmaDone; irq <= kDifDmaIrqDmaError; + ++irq) { + dma_irq_expected = irq; + LOG_INFO("Triggering dma IRQ %d.", irq); + CHECK_DIF_OK(dif_dma_irq_force(&dma, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_dma_irq_set_enabled(&dma, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(dma_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from dma is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralEdn0; + for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone; irq <= kDifEdnIrqEdnFatalErr; + ++irq) { + edn_irq_expected = irq; + LOG_INFO("Triggering edn0 IRQ %d.", irq); + CHECK_DIF_OK(dif_edn_irq_force(&edn0, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(edn_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from edn0 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 5 && 5 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralEdn1; + for (dif_edn_irq_t irq = kDifEdnIrqEdnCmdReqDone; irq <= kDifEdnIrqEdnFatalErr; + ++irq) { + edn_irq_expected = irq; + LOG_INFO("Triggering edn1 IRQ %d.", irq); + CHECK_DIF_OK(dif_edn_irq_force(&edn1, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(edn_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from edn1 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 6 && 6 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralEntropySrc; + for (dif_entropy_src_irq_t irq = kDifEntropySrcIrqEsEntropyValid; irq <= kDifEntropySrcIrqEsFatalErr; + ++irq) { + entropy_src_irq_expected = irq; + LOG_INFO("Triggering entropy_src IRQ %d.", irq); + CHECK_DIF_OK(dif_entropy_src_irq_force(&entropy_src, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(entropy_src_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from entropy_src is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 7 && 7 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralGpio; + for (dif_gpio_irq_t irq = kDifGpioIrqGpio0; irq <= kDifGpioIrqGpio31; + ++irq) { + gpio_irq_expected = irq; + LOG_INFO("Triggering gpio IRQ %d.", irq); + CHECK_DIF_OK(dif_gpio_irq_force(&gpio, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(gpio_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from gpio is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 8 && 8 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralHmac; + status_default_mask = 0x0; + for (dif_hmac_irq_t irq = kDifHmacIrqHmacDone; irq <= kDifHmacIrqHmacErr; + ++irq) { + hmac_irq_expected = irq; + LOG_INFO("Triggering hmac IRQ %d.", irq); + CHECK_DIF_OK(dif_hmac_irq_force(&hmac, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_hmac_irq_set_enabled(&hmac, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(hmac_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from hmac is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 9 && 9 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralI2c0; + status_default_mask = 0x0; + for (dif_i2c_irq_t irq = kDifI2cIrqFmtThreshold; irq <= kDifI2cIrqHostTimeout; + ++irq) { + i2c_irq_expected = irq; + LOG_INFO("Triggering i2c0 IRQ %d.", irq); + CHECK_DIF_OK(dif_i2c_irq_force(&i2c0, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_i2c_irq_set_enabled(&i2c0, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(i2c_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from i2c0 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 10 && 10 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralKeymgrDpe; + for (dif_keymgr_dpe_irq_t irq = kDifKeymgrDpeIrqOpDone; irq <= kDifKeymgrDpeIrqOpDone; + ++irq) { + keymgr_dpe_irq_expected = irq; + LOG_INFO("Triggering keymgr_dpe IRQ %d.", irq); + CHECK_DIF_OK(dif_keymgr_dpe_irq_force(&keymgr_dpe, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(keymgr_dpe_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from keymgr_dpe is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 11 && 11 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralKmac; + status_default_mask = 0x0; + for (dif_kmac_irq_t irq = kDifKmacIrqKmacDone; irq <= kDifKmacIrqKmacErr; + ++irq) { + kmac_irq_expected = irq; + LOG_INFO("Triggering kmac IRQ %d.", irq); + CHECK_DIF_OK(dif_kmac_irq_force(&kmac, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_kmac_irq_set_enabled(&kmac, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(kmac_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from kmac is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbx0; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx0 IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx0, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx0 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbx1; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx1 IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx1, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx1 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbx2; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx2 IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx2, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx2 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbx3; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx3 IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx3, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx3 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbx4; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx4 IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx4, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx4 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbx5; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx5 IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx5, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx5 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbx6; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx6 IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx6, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx6 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbxJtag; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx_jtag IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx_jtag, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx_jtag is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbxPcie0; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx_pcie0 IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx_pcie0, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx_pcie0 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 12 && 12 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralMbxPcie1; + for (dif_mbx_irq_t irq = kDifMbxIrqMbxReady; irq <= kDifMbxIrqMbxError; + ++irq) { + mbx_irq_expected = irq; + LOG_INFO("Triggering mbx_pcie1 IRQ %d.", irq); + CHECK_DIF_OK(dif_mbx_irq_force(&mbx_pcie1, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(mbx_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from mbx_pcie1 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 13 && 13 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralOtbn; + for (dif_otbn_irq_t irq = kDifOtbnIrqDone; irq <= kDifOtbnIrqDone; + ++irq) { + otbn_irq_expected = irq; + LOG_INFO("Triggering otbn IRQ %d.", irq); + CHECK_DIF_OK(dif_otbn_irq_force(&otbn, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(otbn_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from otbn is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 14 && 14 < TEST_MAX_IRQ_PERIPHERAL + // Skip OTP_CTRL in boot stage owner since ROM_EXT configures all accesses + // to OTP_CTRL and AST to be illegal. + if (kBootStage != kBootStageOwner) { + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralOtpCtrl; + for (dif_otp_ctrl_irq_t irq = kDifOtpCtrlIrqOtpOperationDone; irq <= kDifOtpCtrlIrqOtpError; + ++irq) { + otp_ctrl_irq_expected = irq; + LOG_INFO("Triggering otp_ctrl IRQ %d.", irq); + CHECK_DIF_OK(dif_otp_ctrl_irq_force(&otp_ctrl, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(otp_ctrl_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from otp_ctrl is serviced.", irq); + } + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 15 && 15 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralPwrmgrAon; + for (dif_pwrmgr_irq_t irq = kDifPwrmgrIrqWakeup; irq <= kDifPwrmgrIrqWakeup; + ++irq) { + pwrmgr_irq_expected = irq; + LOG_INFO("Triggering pwrmgr_aon IRQ %d.", irq); + CHECK_DIF_OK(dif_pwrmgr_irq_force(&pwrmgr_aon, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(pwrmgr_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from pwrmgr_aon is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 16 && 16 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralRaclCtrl; + status_default_mask = 0x0; + for (dif_racl_ctrl_irq_t irq = kDifRaclCtrlIrqRaclError; irq <= kDifRaclCtrlIrqRaclError; + ++irq) { + racl_ctrl_irq_expected = irq; + LOG_INFO("Triggering racl_ctrl IRQ %d.", irq); + CHECK_DIF_OK(dif_racl_ctrl_irq_force(&racl_ctrl, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_racl_ctrl_irq_set_enabled(&racl_ctrl, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(racl_ctrl_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from racl_ctrl is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 17 && 17 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralSocProxy; + for (dif_soc_proxy_irq_t irq = kDifSocProxyIrqExternal0; irq <= kDifSocProxyIrqExternal31; + ++irq) { + soc_proxy_irq_expected = irq; + LOG_INFO("Triggering soc_proxy IRQ %d.", irq); + CHECK_DIF_OK(dif_soc_proxy_irq_force(&soc_proxy, irq, true)); + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(soc_proxy_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from soc_proxy is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 18 && 18 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralSpiDevice; + status_default_mask = 0x0; + for (dif_spi_device_irq_t irq = kDifSpiDeviceIrqUploadCmdfifoNotEmpty; irq <= kDifSpiDeviceIrqTpmRdfifoDrop; + ++irq) { + spi_device_irq_expected = irq; + LOG_INFO("Triggering spi_device IRQ %d.", irq); + CHECK_DIF_OK(dif_spi_device_irq_force(&spi_device, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_spi_device_irq_set_enabled(&spi_device, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(spi_device_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from spi_device is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 19 && 19 < TEST_MAX_IRQ_PERIPHERAL + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralSpiHost0; + status_default_mask = 0x0; + for (dif_spi_host_irq_t irq = kDifSpiHostIrqError; irq <= kDifSpiHostIrqSpiEvent; + ++irq) { + spi_host_irq_expected = irq; + LOG_INFO("Triggering spi_host0 IRQ %d.", irq); + CHECK_DIF_OK(dif_spi_host_irq_force(&spi_host0, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_spi_host_irq_set_enabled(&spi_host0, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(spi_host_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from spi_host0 is serviced.", irq); + } +#endif + +#if TEST_MIN_IRQ_PERIPHERAL <= 20 && 20 < TEST_MAX_IRQ_PERIPHERAL + // lowrisc/opentitan#8656: Skip UART0 in non-DV setups due to interference + // from the logging facility. + // aon_timer may generate a NMI instead of a PLIC IRQ depending on the ROM. + // Since there are other tests covering this already, we just skip this for + // non-DV setups. + if (kDeviceType == kDeviceSimDV) { + peripheral_expected = kTopDarjeelingNoIbexPlicPeripheralUart0; + status_default_mask = 0x101; + for (dif_uart_irq_t irq = kDifUartIrqTxWatermark; irq <= kDifUartIrqTxEmpty; + ++irq) { + uart_irq_expected = irq; + LOG_INFO("Triggering uart0 IRQ %d.", irq); + CHECK_DIF_OK(dif_uart_irq_force(&uart0, irq, true)); + + // In this case, the interrupt has not been enabled yet because that would + // interfere with testing other interrupts. We enable it here and let the + // interrupt handler disable it again. + if ((status_default_mask & 0x1)) { + CHECK_DIF_OK(dif_uart_irq_set_enabled(&uart0, irq, true)); + } + status_default_mask >>= 1; + + // This avoids a race where *irq_serviced is read before + // entering the ISR. + IBEX_SPIN_FOR(uart_irq_serviced == irq, 1); + LOG_INFO("IRQ %d from uart0 is serviced.", irq); + } + } +#endif +} + +/** + * Checks that the target ID corresponds to the ID of the hart on which + * this test is executed on. This check is meant to be used in a + * single-hart system only. + */ +static void check_hart_id(uint32_t exp_hart_id) { + uint32_t act_hart_id; + CSR_READ(CSR_REG_MHARTID, &act_hart_id); + CHECK(act_hart_id == exp_hart_id, "Processor has unexpected HART ID."); +} + +OTTF_DEFINE_TEST_CONFIG(); + +bool test_main(void) { + irq_global_ctrl(true); + irq_external_ctrl(true); + peripherals_init(); + check_hart_id((uint32_t)kHart); + rv_plic_testutils_irq_range_enable( + &plic, kHart, kTopDarjeeling_no_ibexPlicIrqIdNone + 1, kTopDarjeeling_no_ibexPlicIrqIdLast); + peripheral_irqs_clear(); + peripheral_irqs_enable(); + peripheral_irqs_trigger(); + return true; +} + +// clang-format on diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex.c b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex.c new file mode 100644 index 00000000000..071de34c1d0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex.c @@ -0,0 +1,292 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex + +#include "hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex.h" + +/** + * Alert Handler Alert Source to Peripheral Map + * + * This array is a mapping from `top_darjeeling_no_ibex_alert_id_t` to + * `top_darjeeling_no_ibex_alert_peripheral_t`. + */ +const top_darjeeling_no_ibex_alert_peripheral_t + top_darjeeling_no_ibex_alert_for_peripheral[99] = { + [kTopDarjeelingNoIbexAlertIdUart0FatalFault] = kTopDarjeelingNoIbexAlertPeripheralUart0, + [kTopDarjeelingNoIbexAlertIdGpioFatalFault] = kTopDarjeelingNoIbexAlertPeripheralGpio, + [kTopDarjeelingNoIbexAlertIdSpiDeviceFatalFault] = kTopDarjeelingNoIbexAlertPeripheralSpiDevice, + [kTopDarjeelingNoIbexAlertIdI2c0FatalFault] = kTopDarjeelingNoIbexAlertPeripheralI2c0, + [kTopDarjeelingNoIbexAlertIdOtpCtrlFatalMacroError] = kTopDarjeelingNoIbexAlertPeripheralOtpCtrl, + [kTopDarjeelingNoIbexAlertIdOtpCtrlFatalCheckError] = kTopDarjeelingNoIbexAlertPeripheralOtpCtrl, + [kTopDarjeelingNoIbexAlertIdOtpCtrlFatalBusIntegError] = kTopDarjeelingNoIbexAlertPeripheralOtpCtrl, + [kTopDarjeelingNoIbexAlertIdOtpCtrlFatalPrimOtpAlert] = kTopDarjeelingNoIbexAlertPeripheralOtpCtrl, + [kTopDarjeelingNoIbexAlertIdOtpCtrlRecovPrimOtpAlert] = kTopDarjeelingNoIbexAlertPeripheralOtpCtrl, + [kTopDarjeelingNoIbexAlertIdLcCtrlFatalProgError] = kTopDarjeelingNoIbexAlertPeripheralLcCtrl, + [kTopDarjeelingNoIbexAlertIdLcCtrlFatalStateError] = kTopDarjeelingNoIbexAlertPeripheralLcCtrl, + [kTopDarjeelingNoIbexAlertIdLcCtrlFatalBusIntegError] = kTopDarjeelingNoIbexAlertPeripheralLcCtrl, + [kTopDarjeelingNoIbexAlertIdSpiHost0FatalFault] = kTopDarjeelingNoIbexAlertPeripheralSpiHost0, + [kTopDarjeelingNoIbexAlertIdPwrmgrAonFatalFault] = kTopDarjeelingNoIbexAlertPeripheralPwrmgrAon, + [kTopDarjeelingNoIbexAlertIdRstmgrAonFatalFault] = kTopDarjeelingNoIbexAlertPeripheralRstmgrAon, + [kTopDarjeelingNoIbexAlertIdRstmgrAonFatalCnstyFault] = kTopDarjeelingNoIbexAlertPeripheralRstmgrAon, + [kTopDarjeelingNoIbexAlertIdClkmgrAonRecovFault] = kTopDarjeelingNoIbexAlertPeripheralClkmgrAon, + [kTopDarjeelingNoIbexAlertIdClkmgrAonFatalFault] = kTopDarjeelingNoIbexAlertPeripheralClkmgrAon, + [kTopDarjeelingNoIbexAlertIdPinmuxAonFatalFault] = kTopDarjeelingNoIbexAlertPeripheralPinmuxAon, + [kTopDarjeelingNoIbexAlertIdAonTimerAonFatalFault] = kTopDarjeelingNoIbexAlertPeripheralAonTimerAon, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertIntg] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal0] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal1] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal2] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal3] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal4] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal5] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal6] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal7] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal8] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal9] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal10] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal11] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal12] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal13] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal14] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal15] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal16] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal17] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal18] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal19] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal20] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal21] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal22] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal23] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal0] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal1] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal2] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal3] = kTopDarjeelingNoIbexAlertPeripheralSocProxy, + [kTopDarjeelingNoIbexAlertIdSramCtrlRetAonFatalError] = kTopDarjeelingNoIbexAlertPeripheralSramCtrlRetAon, + [kTopDarjeelingNoIbexAlertIdRvPlicFatalFault] = kTopDarjeelingNoIbexAlertPeripheralRvPlic, + [kTopDarjeelingNoIbexAlertIdAesRecovCtrlUpdateErr] = kTopDarjeelingNoIbexAlertPeripheralAes, + [kTopDarjeelingNoIbexAlertIdAesFatalFault] = kTopDarjeelingNoIbexAlertPeripheralAes, + [kTopDarjeelingNoIbexAlertIdHmacFatalFault] = kTopDarjeelingNoIbexAlertPeripheralHmac, + [kTopDarjeelingNoIbexAlertIdKmacRecovOperationErr] = kTopDarjeelingNoIbexAlertPeripheralKmac, + [kTopDarjeelingNoIbexAlertIdKmacFatalFaultErr] = kTopDarjeelingNoIbexAlertPeripheralKmac, + [kTopDarjeelingNoIbexAlertIdOtbnFatal] = kTopDarjeelingNoIbexAlertPeripheralOtbn, + [kTopDarjeelingNoIbexAlertIdOtbnRecov] = kTopDarjeelingNoIbexAlertPeripheralOtbn, + [kTopDarjeelingNoIbexAlertIdKeymgrDpeRecovOperationErr] = kTopDarjeelingNoIbexAlertPeripheralKeymgrDpe, + [kTopDarjeelingNoIbexAlertIdKeymgrDpeFatalFaultErr] = kTopDarjeelingNoIbexAlertPeripheralKeymgrDpe, + [kTopDarjeelingNoIbexAlertIdCsrngRecovAlert] = kTopDarjeelingNoIbexAlertPeripheralCsrng, + [kTopDarjeelingNoIbexAlertIdCsrngFatalAlert] = kTopDarjeelingNoIbexAlertPeripheralCsrng, + [kTopDarjeelingNoIbexAlertIdEntropySrcRecovAlert] = kTopDarjeelingNoIbexAlertPeripheralEntropySrc, + [kTopDarjeelingNoIbexAlertIdEntropySrcFatalAlert] = kTopDarjeelingNoIbexAlertPeripheralEntropySrc, + [kTopDarjeelingNoIbexAlertIdEdn0RecovAlert] = kTopDarjeelingNoIbexAlertPeripheralEdn0, + [kTopDarjeelingNoIbexAlertIdEdn0FatalAlert] = kTopDarjeelingNoIbexAlertPeripheralEdn0, + [kTopDarjeelingNoIbexAlertIdEdn1RecovAlert] = kTopDarjeelingNoIbexAlertPeripheralEdn1, + [kTopDarjeelingNoIbexAlertIdEdn1FatalAlert] = kTopDarjeelingNoIbexAlertPeripheralEdn1, + [kTopDarjeelingNoIbexAlertIdSramCtrlMainFatalError] = kTopDarjeelingNoIbexAlertPeripheralSramCtrlMain, + [kTopDarjeelingNoIbexAlertIdSramCtrlMboxFatalError] = kTopDarjeelingNoIbexAlertPeripheralSramCtrlMbox, + [kTopDarjeelingNoIbexAlertIdRomCtrl0Fatal] = kTopDarjeelingNoIbexAlertPeripheralRomCtrl0, + [kTopDarjeelingNoIbexAlertIdRomCtrl1Fatal] = kTopDarjeelingNoIbexAlertPeripheralRomCtrl1, + [kTopDarjeelingNoIbexAlertIdDmaFatalFault] = kTopDarjeelingNoIbexAlertPeripheralDma, + [kTopDarjeelingNoIbexAlertIdMbx0FatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbx0, + [kTopDarjeelingNoIbexAlertIdMbx0RecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbx0, + [kTopDarjeelingNoIbexAlertIdMbx1FatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbx1, + [kTopDarjeelingNoIbexAlertIdMbx1RecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbx1, + [kTopDarjeelingNoIbexAlertIdMbx2FatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbx2, + [kTopDarjeelingNoIbexAlertIdMbx2RecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbx2, + [kTopDarjeelingNoIbexAlertIdMbx3FatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbx3, + [kTopDarjeelingNoIbexAlertIdMbx3RecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbx3, + [kTopDarjeelingNoIbexAlertIdMbx4FatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbx4, + [kTopDarjeelingNoIbexAlertIdMbx4RecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbx4, + [kTopDarjeelingNoIbexAlertIdMbx5FatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbx5, + [kTopDarjeelingNoIbexAlertIdMbx5RecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbx5, + [kTopDarjeelingNoIbexAlertIdMbx6FatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbx6, + [kTopDarjeelingNoIbexAlertIdMbx6RecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbx6, + [kTopDarjeelingNoIbexAlertIdMbxJtagFatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbxJtag, + [kTopDarjeelingNoIbexAlertIdMbxJtagRecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbxJtag, + [kTopDarjeelingNoIbexAlertIdMbxPcie0FatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbxPcie0, + [kTopDarjeelingNoIbexAlertIdMbxPcie0RecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbxPcie0, + [kTopDarjeelingNoIbexAlertIdMbxPcie1FatalFault] = kTopDarjeelingNoIbexAlertPeripheralMbxPcie1, + [kTopDarjeelingNoIbexAlertIdMbxPcie1RecovFault] = kTopDarjeelingNoIbexAlertPeripheralMbxPcie1, + [kTopDarjeelingNoIbexAlertIdSocDbgCtrlFatalFault] = kTopDarjeelingNoIbexAlertPeripheralSocDbgCtrl, + [kTopDarjeelingNoIbexAlertIdSocDbgCtrlRecovCtrlUpdateErr] = kTopDarjeelingNoIbexAlertPeripheralSocDbgCtrl, + [kTopDarjeelingNoIbexAlertIdRaclCtrlFatalFault] = kTopDarjeelingNoIbexAlertPeripheralRaclCtrl, + [kTopDarjeelingNoIbexAlertIdRaclCtrlRecovCtrlUpdateErr] = kTopDarjeelingNoIbexAlertPeripheralRaclCtrl, + [kTopDarjeelingNoIbexAlertIdAcRangeCheckRecovCtrlUpdateErr] = kTopDarjeelingNoIbexAlertPeripheralAcRangeCheck, + [kTopDarjeelingNoIbexAlertIdAcRangeCheckFatalFault] = kTopDarjeelingNoIbexAlertPeripheralAcRangeCheck, +}; + +/** + * PLIC Interrupt Source to Peripheral Map + * + * This array is a mapping from `top_darjeeling_no_ibex_plic_irq_id_t` to + * `top_darjeeling_no_ibex_plic_peripheral_t`. + */ +const top_darjeeling_no_ibex_plic_peripheral_t + top_darjeeling_no_ibex_plic_interrupt_for_peripheral[163] = { + [kTopDarjeelingNoIbexPlicIrqIdNone] = kTopDarjeelingNoIbexPlicPeripheralUnknown, + [kTopDarjeelingNoIbexPlicIrqIdUart0TxWatermark] = kTopDarjeelingNoIbexPlicPeripheralUart0, + [kTopDarjeelingNoIbexPlicIrqIdUart0RxWatermark] = kTopDarjeelingNoIbexPlicPeripheralUart0, + [kTopDarjeelingNoIbexPlicIrqIdUart0TxDone] = kTopDarjeelingNoIbexPlicPeripheralUart0, + [kTopDarjeelingNoIbexPlicIrqIdUart0RxOverflow] = kTopDarjeelingNoIbexPlicPeripheralUart0, + [kTopDarjeelingNoIbexPlicIrqIdUart0RxFrameErr] = kTopDarjeelingNoIbexPlicPeripheralUart0, + [kTopDarjeelingNoIbexPlicIrqIdUart0RxBreakErr] = kTopDarjeelingNoIbexPlicPeripheralUart0, + [kTopDarjeelingNoIbexPlicIrqIdUart0RxTimeout] = kTopDarjeelingNoIbexPlicPeripheralUart0, + [kTopDarjeelingNoIbexPlicIrqIdUart0RxParityErr] = kTopDarjeelingNoIbexPlicPeripheralUart0, + [kTopDarjeelingNoIbexPlicIrqIdUart0TxEmpty] = kTopDarjeelingNoIbexPlicPeripheralUart0, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio0] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio1] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio2] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio3] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio4] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio5] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio6] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio7] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio8] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio9] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio10] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio11] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio12] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio13] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio14] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio15] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio16] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio17] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio18] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio19] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio20] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio21] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio22] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio23] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio24] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio25] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio26] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio27] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio28] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio29] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio30] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdGpioGpio31] = kTopDarjeelingNoIbexPlicPeripheralGpio, + [kTopDarjeelingNoIbexPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty] = kTopDarjeelingNoIbexPlicPeripheralSpiDevice, + [kTopDarjeelingNoIbexPlicIrqIdSpiDeviceUploadPayloadNotEmpty] = kTopDarjeelingNoIbexPlicPeripheralSpiDevice, + [kTopDarjeelingNoIbexPlicIrqIdSpiDeviceUploadPayloadOverflow] = kTopDarjeelingNoIbexPlicPeripheralSpiDevice, + [kTopDarjeelingNoIbexPlicIrqIdSpiDeviceReadbufWatermark] = kTopDarjeelingNoIbexPlicPeripheralSpiDevice, + [kTopDarjeelingNoIbexPlicIrqIdSpiDeviceReadbufFlip] = kTopDarjeelingNoIbexPlicPeripheralSpiDevice, + [kTopDarjeelingNoIbexPlicIrqIdSpiDeviceTpmHeaderNotEmpty] = kTopDarjeelingNoIbexPlicPeripheralSpiDevice, + [kTopDarjeelingNoIbexPlicIrqIdSpiDeviceTpmRdfifoCmdEnd] = kTopDarjeelingNoIbexPlicPeripheralSpiDevice, + [kTopDarjeelingNoIbexPlicIrqIdSpiDeviceTpmRdfifoDrop] = kTopDarjeelingNoIbexPlicPeripheralSpiDevice, + [kTopDarjeelingNoIbexPlicIrqIdI2c0FmtThreshold] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0RxThreshold] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0AcqThreshold] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0RxOverflow] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0ControllerHalt] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0SclInterference] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0SdaInterference] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0StretchTimeout] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0SdaUnstable] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0CmdComplete] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0TxStretch] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0TxThreshold] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0AcqStretch] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0UnexpStop] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdI2c0HostTimeout] = kTopDarjeelingNoIbexPlicPeripheralI2c0, + [kTopDarjeelingNoIbexPlicIrqIdOtpCtrlOtpOperationDone] = kTopDarjeelingNoIbexPlicPeripheralOtpCtrl, + [kTopDarjeelingNoIbexPlicIrqIdOtpCtrlOtpError] = kTopDarjeelingNoIbexPlicPeripheralOtpCtrl, + [kTopDarjeelingNoIbexPlicIrqIdAlertHandlerClassa] = kTopDarjeelingNoIbexPlicPeripheralAlertHandler, + [kTopDarjeelingNoIbexPlicIrqIdAlertHandlerClassb] = kTopDarjeelingNoIbexPlicPeripheralAlertHandler, + [kTopDarjeelingNoIbexPlicIrqIdAlertHandlerClassc] = kTopDarjeelingNoIbexPlicPeripheralAlertHandler, + [kTopDarjeelingNoIbexPlicIrqIdAlertHandlerClassd] = kTopDarjeelingNoIbexPlicPeripheralAlertHandler, + [kTopDarjeelingNoIbexPlicIrqIdSpiHost0Error] = kTopDarjeelingNoIbexPlicPeripheralSpiHost0, + [kTopDarjeelingNoIbexPlicIrqIdSpiHost0SpiEvent] = kTopDarjeelingNoIbexPlicPeripheralSpiHost0, + [kTopDarjeelingNoIbexPlicIrqIdPwrmgrAonWakeup] = kTopDarjeelingNoIbexPlicPeripheralPwrmgrAon, + [kTopDarjeelingNoIbexPlicIrqIdAonTimerAonWkupTimerExpired] = kTopDarjeelingNoIbexPlicPeripheralAonTimerAon, + [kTopDarjeelingNoIbexPlicIrqIdAonTimerAonWdogTimerBark] = kTopDarjeelingNoIbexPlicPeripheralAonTimerAon, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal0] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal1] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal2] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal3] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal4] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal5] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal6] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal7] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal8] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal9] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal10] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal11] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal12] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal13] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal14] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal15] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal16] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal17] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal18] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal19] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal20] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal21] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal22] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal23] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal24] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal25] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal26] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal27] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal28] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal29] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal30] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal31] = kTopDarjeelingNoIbexPlicPeripheralSocProxy, + [kTopDarjeelingNoIbexPlicIrqIdHmacHmacDone] = kTopDarjeelingNoIbexPlicPeripheralHmac, + [kTopDarjeelingNoIbexPlicIrqIdHmacFifoEmpty] = kTopDarjeelingNoIbexPlicPeripheralHmac, + [kTopDarjeelingNoIbexPlicIrqIdHmacHmacErr] = kTopDarjeelingNoIbexPlicPeripheralHmac, + [kTopDarjeelingNoIbexPlicIrqIdKmacKmacDone] = kTopDarjeelingNoIbexPlicPeripheralKmac, + [kTopDarjeelingNoIbexPlicIrqIdKmacFifoEmpty] = kTopDarjeelingNoIbexPlicPeripheralKmac, + [kTopDarjeelingNoIbexPlicIrqIdKmacKmacErr] = kTopDarjeelingNoIbexPlicPeripheralKmac, + [kTopDarjeelingNoIbexPlicIrqIdOtbnDone] = kTopDarjeelingNoIbexPlicPeripheralOtbn, + [kTopDarjeelingNoIbexPlicIrqIdKeymgrDpeOpDone] = kTopDarjeelingNoIbexPlicPeripheralKeymgrDpe, + [kTopDarjeelingNoIbexPlicIrqIdCsrngCsCmdReqDone] = kTopDarjeelingNoIbexPlicPeripheralCsrng, + [kTopDarjeelingNoIbexPlicIrqIdCsrngCsEntropyReq] = kTopDarjeelingNoIbexPlicPeripheralCsrng, + [kTopDarjeelingNoIbexPlicIrqIdCsrngCsHwInstExc] = kTopDarjeelingNoIbexPlicPeripheralCsrng, + [kTopDarjeelingNoIbexPlicIrqIdCsrngCsFatalErr] = kTopDarjeelingNoIbexPlicPeripheralCsrng, + [kTopDarjeelingNoIbexPlicIrqIdEntropySrcEsEntropyValid] = kTopDarjeelingNoIbexPlicPeripheralEntropySrc, + [kTopDarjeelingNoIbexPlicIrqIdEntropySrcEsHealthTestFailed] = kTopDarjeelingNoIbexPlicPeripheralEntropySrc, + [kTopDarjeelingNoIbexPlicIrqIdEntropySrcEsObserveFifoReady] = kTopDarjeelingNoIbexPlicPeripheralEntropySrc, + [kTopDarjeelingNoIbexPlicIrqIdEntropySrcEsFatalErr] = kTopDarjeelingNoIbexPlicPeripheralEntropySrc, + [kTopDarjeelingNoIbexPlicIrqIdEdn0EdnCmdReqDone] = kTopDarjeelingNoIbexPlicPeripheralEdn0, + [kTopDarjeelingNoIbexPlicIrqIdEdn0EdnFatalErr] = kTopDarjeelingNoIbexPlicPeripheralEdn0, + [kTopDarjeelingNoIbexPlicIrqIdEdn1EdnCmdReqDone] = kTopDarjeelingNoIbexPlicPeripheralEdn1, + [kTopDarjeelingNoIbexPlicIrqIdEdn1EdnFatalErr] = kTopDarjeelingNoIbexPlicPeripheralEdn1, + [kTopDarjeelingNoIbexPlicIrqIdDmaDmaDone] = kTopDarjeelingNoIbexPlicPeripheralDma, + [kTopDarjeelingNoIbexPlicIrqIdDmaDmaChunkDone] = kTopDarjeelingNoIbexPlicPeripheralDma, + [kTopDarjeelingNoIbexPlicIrqIdDmaDmaError] = kTopDarjeelingNoIbexPlicPeripheralDma, + [kTopDarjeelingNoIbexPlicIrqIdMbx0MbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbx0, + [kTopDarjeelingNoIbexPlicIrqIdMbx0MbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbx0, + [kTopDarjeelingNoIbexPlicIrqIdMbx0MbxError] = kTopDarjeelingNoIbexPlicPeripheralMbx0, + [kTopDarjeelingNoIbexPlicIrqIdMbx1MbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbx1, + [kTopDarjeelingNoIbexPlicIrqIdMbx1MbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbx1, + [kTopDarjeelingNoIbexPlicIrqIdMbx1MbxError] = kTopDarjeelingNoIbexPlicPeripheralMbx1, + [kTopDarjeelingNoIbexPlicIrqIdMbx2MbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbx2, + [kTopDarjeelingNoIbexPlicIrqIdMbx2MbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbx2, + [kTopDarjeelingNoIbexPlicIrqIdMbx2MbxError] = kTopDarjeelingNoIbexPlicPeripheralMbx2, + [kTopDarjeelingNoIbexPlicIrqIdMbx3MbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbx3, + [kTopDarjeelingNoIbexPlicIrqIdMbx3MbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbx3, + [kTopDarjeelingNoIbexPlicIrqIdMbx3MbxError] = kTopDarjeelingNoIbexPlicPeripheralMbx3, + [kTopDarjeelingNoIbexPlicIrqIdMbx4MbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbx4, + [kTopDarjeelingNoIbexPlicIrqIdMbx4MbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbx4, + [kTopDarjeelingNoIbexPlicIrqIdMbx4MbxError] = kTopDarjeelingNoIbexPlicPeripheralMbx4, + [kTopDarjeelingNoIbexPlicIrqIdMbx5MbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbx5, + [kTopDarjeelingNoIbexPlicIrqIdMbx5MbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbx5, + [kTopDarjeelingNoIbexPlicIrqIdMbx5MbxError] = kTopDarjeelingNoIbexPlicPeripheralMbx5, + [kTopDarjeelingNoIbexPlicIrqIdMbx6MbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbx6, + [kTopDarjeelingNoIbexPlicIrqIdMbx6MbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbx6, + [kTopDarjeelingNoIbexPlicIrqIdMbx6MbxError] = kTopDarjeelingNoIbexPlicPeripheralMbx6, + [kTopDarjeelingNoIbexPlicIrqIdMbxJtagMbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbxJtag, + [kTopDarjeelingNoIbexPlicIrqIdMbxJtagMbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbxJtag, + [kTopDarjeelingNoIbexPlicIrqIdMbxJtagMbxError] = kTopDarjeelingNoIbexPlicPeripheralMbxJtag, + [kTopDarjeelingNoIbexPlicIrqIdMbxPcie0MbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbxPcie0, + [kTopDarjeelingNoIbexPlicIrqIdMbxPcie0MbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbxPcie0, + [kTopDarjeelingNoIbexPlicIrqIdMbxPcie0MbxError] = kTopDarjeelingNoIbexPlicPeripheralMbxPcie0, + [kTopDarjeelingNoIbexPlicIrqIdMbxPcie1MbxReady] = kTopDarjeelingNoIbexPlicPeripheralMbxPcie1, + [kTopDarjeelingNoIbexPlicIrqIdMbxPcie1MbxAbort] = kTopDarjeelingNoIbexPlicPeripheralMbxPcie1, + [kTopDarjeelingNoIbexPlicIrqIdMbxPcie1MbxError] = kTopDarjeelingNoIbexPlicPeripheralMbxPcie1, + [kTopDarjeelingNoIbexPlicIrqIdRaclCtrlRaclError] = kTopDarjeelingNoIbexPlicPeripheralRaclCtrl, + [kTopDarjeelingNoIbexPlicIrqIdAcRangeCheckDenyCntReached] = kTopDarjeelingNoIbexPlicPeripheralAcRangeCheck, +}; diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex.h b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex.h new file mode 100644 index 00000000000..d682640e4fb --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex.h @@ -0,0 +1,1628 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex + +#ifndef OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_H_ +#define OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_H_ + +/** + * @file + * @brief Top-specific Definitions + * + * This file contains preprocessor and type definitions for use within the + * device C/C++ codebase. + * + * These definitions are for information that depends on the top-specific chip + * configuration, which includes: + * - Device Memory Information (for Peripherals and Memory) + * - PLIC Interrupt ID Names and Source Mappings + * - Alert ID Names and Source Mappings + * - Pinmux Pin/Select Names + * - Power Manager Wakeups + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Peripheral base address for uart0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_UART0_BASE_ADDR 0x30010000u + +/** + * Peripheral size for uart0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_UART0_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_UART0_BASE_ADDR + TOP_DARJEELING_NO_IBEX_UART0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_UART0_SIZE_BYTES 0x40u + +/** + * Peripheral base address for gpio in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_GPIO_BASE_ADDR 0x30000000u + +/** + * Peripheral size for gpio in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_GPIO_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_GPIO_BASE_ADDR + TOP_DARJEELING_NO_IBEX_GPIO_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_GPIO_SIZE_BYTES 0x100u + +/** + * Peripheral base address for spi_device in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SPI_DEVICE_BASE_ADDR 0x30310000u + +/** + * Peripheral size for spi_device in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SPI_DEVICE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SPI_DEVICE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SPI_DEVICE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SPI_DEVICE_SIZE_BYTES 0x2000u + +/** + * Peripheral base address for i2c0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_I2C0_BASE_ADDR 0x30080000u + +/** + * Peripheral size for i2c0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_I2C0_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_I2C0_BASE_ADDR + TOP_DARJEELING_NO_IBEX_I2C0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_I2C0_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on otp_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_BASE_ADDR 0x30130000u + +/** + * Peripheral size for core device on otp_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_SIZE_BYTES 0x8000u + +/** + * Peripheral base address for prim device on otp_macro in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_BASE_ADDR 0x30140000u + +/** + * Peripheral size for prim device on otp_macro in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_SIZE_BYTES 0x20u + +/** + * Peripheral base address for regs device on lc_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_BASE_ADDR 0x30150000u + +/** + * Peripheral size for regs device on lc_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_SIZE_BYTES 0x100u + +/** + * Peripheral base address for alert_handler in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_BASE_ADDR 0x30160000u + +/** + * Peripheral size for alert_handler in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_SIZE_BYTES 0x800u + +/** + * Peripheral base address for spi_host0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SPI_HOST0_BASE_ADDR 0x30300000u + +/** + * Peripheral size for spi_host0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SPI_HOST0_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SPI_HOST0_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SPI_HOST0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SPI_HOST0_SIZE_BYTES 0x40u + +/** + * Peripheral base address for pwrmgr_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_PWRMGR_AON_BASE_ADDR 0x30400000u + +/** + * Peripheral size for pwrmgr_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_PWRMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_PWRMGR_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_PWRMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_PWRMGR_AON_SIZE_BYTES 0x80u + +/** + * Peripheral base address for rstmgr_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_RSTMGR_AON_BASE_ADDR 0x30410000u + +/** + * Peripheral size for rstmgr_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_RSTMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_RSTMGR_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_RSTMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_RSTMGR_AON_SIZE_BYTES 0x80u + +/** + * Peripheral base address for clkmgr_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_CLKMGR_AON_BASE_ADDR 0x30420000u + +/** + * Peripheral size for clkmgr_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_CLKMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_CLKMGR_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_CLKMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_CLKMGR_AON_SIZE_BYTES 0x40u + +/** + * Peripheral base address for pinmux_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_PINMUX_AON_BASE_ADDR 0x30460000u + +/** + * Peripheral size for pinmux_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_PINMUX_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_PINMUX_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_PINMUX_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_PINMUX_AON_SIZE_BYTES 0x800u + +/** + * Peripheral base address for aon_timer_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_BASE_ADDR 0x30470000u + +/** + * Peripheral size for aon_timer_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_SIZE_BYTES 0x40u + +/** + * Peripheral base address for ast in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_AST_BASE_ADDR 0x30480000u + +/** + * Peripheral size for ast in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_AST_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_AST_BASE_ADDR + TOP_DARJEELING_NO_IBEX_AST_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_AST_SIZE_BYTES 0x400u + +/** + * Peripheral base address for core device on soc_proxy in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_BASE_ADDR 0x22030000u + +/** + * Peripheral size for core device on soc_proxy in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_SIZE_BYTES 0x10u + +/** + * Peripheral base address for ctn device on soc_proxy in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_BASE_ADDR 0x40000000u + +/** + * Peripheral size for ctn device on soc_proxy in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_SIZE_BYTES 0x40000000u + +/** + * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x30500000u + +/** + * Peripheral size for regs device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40u + +/** + * Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x30600000u + +/** + * Peripheral size for ram device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for rv_plic in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_RV_PLIC_BASE_ADDR 0x28000000u + +/** + * Peripheral size for rv_plic in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_RV_PLIC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_RV_PLIC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_RV_PLIC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_RV_PLIC_SIZE_BYTES 0x8000000u + +/** + * Peripheral base address for aes in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_AES_BASE_ADDR 0x21100000u + +/** + * Peripheral size for aes in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_AES_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_AES_BASE_ADDR + TOP_DARJEELING_NO_IBEX_AES_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_AES_SIZE_BYTES 0x100u + +/** + * Peripheral base address for hmac in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_HMAC_BASE_ADDR 0x21110000u + +/** + * Peripheral size for hmac in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_HMAC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_HMAC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_HMAC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_HMAC_SIZE_BYTES 0x2000u + +/** + * Peripheral base address for kmac in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_KMAC_BASE_ADDR 0x21120000u + +/** + * Peripheral size for kmac in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_KMAC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_KMAC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_KMAC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_KMAC_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for otbn in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_OTBN_BASE_ADDR 0x21130000u + +/** + * Peripheral size for otbn in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_OTBN_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_OTBN_BASE_ADDR + TOP_DARJEELING_NO_IBEX_OTBN_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_OTBN_SIZE_BYTES 0x10000u + +/** + * Peripheral base address for keymgr_dpe in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_BASE_ADDR 0x21140000u + +/** + * Peripheral size for keymgr_dpe in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_SIZE_BYTES 0x100u + +/** + * Peripheral base address for csrng in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_CSRNG_BASE_ADDR 0x21150000u + +/** + * Peripheral size for csrng in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_CSRNG_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_CSRNG_BASE_ADDR + TOP_DARJEELING_NO_IBEX_CSRNG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_CSRNG_SIZE_BYTES 0x80u + +/** + * Peripheral base address for entropy_src in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_BASE_ADDR 0x21160000u + +/** + * Peripheral size for entropy_src in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_SIZE_BYTES 0x100u + +/** + * Peripheral base address for edn0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_EDN0_BASE_ADDR 0x21170000u + +/** + * Peripheral size for edn0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_EDN0_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_EDN0_BASE_ADDR + TOP_DARJEELING_NO_IBEX_EDN0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_EDN0_SIZE_BYTES 0x80u + +/** + * Peripheral base address for edn1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_EDN1_BASE_ADDR 0x21180000u + +/** + * Peripheral size for edn1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_EDN1_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_EDN1_BASE_ADDR + TOP_DARJEELING_NO_IBEX_EDN1_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_EDN1_SIZE_BYTES 0x80u + +/** + * Peripheral base address for regs device on sram_ctrl_main in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x211C0000u + +/** + * Peripheral size for regs device on sram_ctrl_main in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40u + +/** + * Peripheral base address for ram device on sram_ctrl_main in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000u + +/** + * Peripheral size for ram device on sram_ctrl_main in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x10000u + +/** + * Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_BASE_ADDR 0x211D0000u + +/** + * Peripheral size for regs device on sram_ctrl_mbox in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_SIZE_BYTES 0x40u + +/** + * Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_BASE_ADDR 0x11000000u + +/** + * Peripheral size for ram device on sram_ctrl_mbox in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for regs device on rom_ctrl0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_BASE_ADDR 0x211E0000u + +/** + * Peripheral size for regs device on rom_ctrl0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_SIZE_BYTES 0x80u + +/** + * Peripheral base address for rom device on rom_ctrl0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_BASE_ADDR 0x8000u + +/** + * Peripheral size for rom device on rom_ctrl0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_SIZE_BYTES 0x8000u + +/** + * Peripheral base address for regs device on rom_ctrl1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_BASE_ADDR 0x211E1000u + +/** + * Peripheral size for regs device on rom_ctrl1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_SIZE_BYTES 0x80u + +/** + * Peripheral base address for rom device on rom_ctrl1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_BASE_ADDR 0x20000u + +/** + * Peripheral size for rom device on rom_ctrl1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_SIZE_BYTES 0x10000u + +/** + * Peripheral base address for dma in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_DMA_BASE_ADDR 0x22010000u + +/** + * Peripheral size for dma in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_DMA_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_DMA_BASE_ADDR + TOP_DARJEELING_NO_IBEX_DMA_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_DMA_SIZE_BYTES 0x200u + +/** + * Peripheral base address for core device on mbx0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX0_CORE_BASE_ADDR 0x22000000u + +/** + * Peripheral size for core device on mbx0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX0_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX0_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX0_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX0_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX1_CORE_BASE_ADDR 0x22000100u + +/** + * Peripheral size for core device on mbx1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX1_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX1_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX1_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX1_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx2 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX2_CORE_BASE_ADDR 0x22000200u + +/** + * Peripheral size for core device on mbx2 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX2_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX2_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX2_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX2_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx3 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX3_CORE_BASE_ADDR 0x22000300u + +/** + * Peripheral size for core device on mbx3 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX3_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX3_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX3_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX3_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx4 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX4_CORE_BASE_ADDR 0x22000400u + +/** + * Peripheral size for core device on mbx4 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX4_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX4_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX4_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX4_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx5 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX5_CORE_BASE_ADDR 0x22000500u + +/** + * Peripheral size for core device on mbx5 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX5_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX5_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX5_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX5_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx6 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX6_CORE_BASE_ADDR 0x22000600u + +/** + * Peripheral size for core device on mbx6 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX6_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX6_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX6_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX6_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx_jtag in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_BASE_ADDR 0x22000800u + +/** + * Peripheral size for core device on mbx_jtag in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx_pcie0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_BASE_ADDR 0x22040000u + +/** + * Peripheral size for core device on mbx_pcie0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on mbx_pcie1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_BASE_ADDR 0x22040100u + +/** + * Peripheral size for core device on mbx_pcie1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_SIZE_BYTES 0x80u + +/** + * Peripheral base address for core device on soc_dbg_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_BASE_ADDR 0x30170000u + +/** + * Peripheral size for core device on soc_dbg_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_SIZE_BYTES 0x20u + + +/** + * Memory base address for ctn in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_CTN_BASE_ADDR 0x40000000u + +/** + * Memory size for ctn in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_CTN_SIZE_BYTES 0x40000000u + +/** + * Memory base address for ram_ret_aon in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_RET_AON_BASE_ADDR 0x30600000u + +/** + * Memory size for ram_ret_aon in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_RET_AON_SIZE_BYTES 0x1000u + +/** + * Memory base address for ram_main in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_MAIN_BASE_ADDR 0x10000000u + +/** + * Memory size for ram_main in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_MAIN_SIZE_BYTES 0x10000u + +/** + * Memory base address for ram_mbox in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_MBOX_BASE_ADDR 0x11000000u + +/** + * Memory size for ram_mbox in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_MBOX_SIZE_BYTES 0x1000u + +/** + * Memory base address for rom0 in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_ROM0_BASE_ADDR 0x8000u + +/** + * Memory size for rom0 in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_ROM0_SIZE_BYTES 0x8000u + +/** + * Memory base address for rom1 in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_ROM1_BASE_ADDR 0x20000u + +/** + * Memory size for rom1 in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_ROM1_SIZE_BYTES 0x10000u + + +/** + * PLIC Interrupt Source Peripheral. + * + * Enumeration used to determine which peripheral asserted the corresponding + * interrupt. + */ +typedef enum top_darjeeling_no_ibex_plic_peripheral { + kTopDarjeelingNoIbexPlicPeripheralUnknown = 0, /**< Unknown Peripheral */ + kTopDarjeelingNoIbexPlicPeripheralUart0 = 1, /**< uart0 */ + kTopDarjeelingNoIbexPlicPeripheralGpio = 2, /**< gpio */ + kTopDarjeelingNoIbexPlicPeripheralSpiDevice = 3, /**< spi_device */ + kTopDarjeelingNoIbexPlicPeripheralI2c0 = 4, /**< i2c0 */ + kTopDarjeelingNoIbexPlicPeripheralOtpCtrl = 5, /**< otp_ctrl */ + kTopDarjeelingNoIbexPlicPeripheralAlertHandler = 6, /**< alert_handler */ + kTopDarjeelingNoIbexPlicPeripheralSpiHost0 = 7, /**< spi_host0 */ + kTopDarjeelingNoIbexPlicPeripheralPwrmgrAon = 8, /**< pwrmgr_aon */ + kTopDarjeelingNoIbexPlicPeripheralAonTimerAon = 9, /**< aon_timer_aon */ + kTopDarjeelingNoIbexPlicPeripheralSocProxy = 10, /**< soc_proxy */ + kTopDarjeelingNoIbexPlicPeripheralHmac = 11, /**< hmac */ + kTopDarjeelingNoIbexPlicPeripheralKmac = 12, /**< kmac */ + kTopDarjeelingNoIbexPlicPeripheralOtbn = 13, /**< otbn */ + kTopDarjeelingNoIbexPlicPeripheralKeymgrDpe = 14, /**< keymgr_dpe */ + kTopDarjeelingNoIbexPlicPeripheralCsrng = 15, /**< csrng */ + kTopDarjeelingNoIbexPlicPeripheralEntropySrc = 16, /**< entropy_src */ + kTopDarjeelingNoIbexPlicPeripheralEdn0 = 17, /**< edn0 */ + kTopDarjeelingNoIbexPlicPeripheralEdn1 = 18, /**< edn1 */ + kTopDarjeelingNoIbexPlicPeripheralDma = 19, /**< dma */ + kTopDarjeelingNoIbexPlicPeripheralMbx0 = 20, /**< mbx0 */ + kTopDarjeelingNoIbexPlicPeripheralMbx1 = 21, /**< mbx1 */ + kTopDarjeelingNoIbexPlicPeripheralMbx2 = 22, /**< mbx2 */ + kTopDarjeelingNoIbexPlicPeripheralMbx3 = 23, /**< mbx3 */ + kTopDarjeelingNoIbexPlicPeripheralMbx4 = 24, /**< mbx4 */ + kTopDarjeelingNoIbexPlicPeripheralMbx5 = 25, /**< mbx5 */ + kTopDarjeelingNoIbexPlicPeripheralMbx6 = 26, /**< mbx6 */ + kTopDarjeelingNoIbexPlicPeripheralMbxJtag = 27, /**< mbx_jtag */ + kTopDarjeelingNoIbexPlicPeripheralMbxPcie0 = 28, /**< mbx_pcie0 */ + kTopDarjeelingNoIbexPlicPeripheralMbxPcie1 = 29, /**< mbx_pcie1 */ + kTopDarjeelingNoIbexPlicPeripheralRaclCtrl = 30, /**< racl_ctrl */ + kTopDarjeelingNoIbexPlicPeripheralAcRangeCheck = 31, /**< ac_range_check */ + kTopDarjeelingNoIbexPlicPeripheralLast = 31, /**< \internal Final PLIC peripheral */ +} top_darjeeling_no_ibex_plic_peripheral_t; + +/** + * PLIC Interrupt Source. + * + * Enumeration of all PLIC interrupt sources. The interrupt sources belonging to + * the same peripheral are guaranteed to be consecutive. + */ +typedef enum top_darjeeling_no_ibex_plic_irq_id { + kTopDarjeelingNoIbexPlicIrqIdNone = 0, /**< No Interrupt */ + kTopDarjeelingNoIbexPlicIrqIdUart0TxWatermark = 1, /**< uart0_tx_watermark */ + kTopDarjeelingNoIbexPlicIrqIdUart0RxWatermark = 2, /**< uart0_rx_watermark */ + kTopDarjeelingNoIbexPlicIrqIdUart0TxDone = 3, /**< uart0_tx_done */ + kTopDarjeelingNoIbexPlicIrqIdUart0RxOverflow = 4, /**< uart0_rx_overflow */ + kTopDarjeelingNoIbexPlicIrqIdUart0RxFrameErr = 5, /**< uart0_rx_frame_err */ + kTopDarjeelingNoIbexPlicIrqIdUart0RxBreakErr = 6, /**< uart0_rx_break_err */ + kTopDarjeelingNoIbexPlicIrqIdUart0RxTimeout = 7, /**< uart0_rx_timeout */ + kTopDarjeelingNoIbexPlicIrqIdUart0RxParityErr = 8, /**< uart0_rx_parity_err */ + kTopDarjeelingNoIbexPlicIrqIdUart0TxEmpty = 9, /**< uart0_tx_empty */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio0 = 10, /**< gpio_gpio 0 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio1 = 11, /**< gpio_gpio 1 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio2 = 12, /**< gpio_gpio 2 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio3 = 13, /**< gpio_gpio 3 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio4 = 14, /**< gpio_gpio 4 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio5 = 15, /**< gpio_gpio 5 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio6 = 16, /**< gpio_gpio 6 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio7 = 17, /**< gpio_gpio 7 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio8 = 18, /**< gpio_gpio 8 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio9 = 19, /**< gpio_gpio 9 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio10 = 20, /**< gpio_gpio 10 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio11 = 21, /**< gpio_gpio 11 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio12 = 22, /**< gpio_gpio 12 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio13 = 23, /**< gpio_gpio 13 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio14 = 24, /**< gpio_gpio 14 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio15 = 25, /**< gpio_gpio 15 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio16 = 26, /**< gpio_gpio 16 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio17 = 27, /**< gpio_gpio 17 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio18 = 28, /**< gpio_gpio 18 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio19 = 29, /**< gpio_gpio 19 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio20 = 30, /**< gpio_gpio 20 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio21 = 31, /**< gpio_gpio 21 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio22 = 32, /**< gpio_gpio 22 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio23 = 33, /**< gpio_gpio 23 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio24 = 34, /**< gpio_gpio 24 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio25 = 35, /**< gpio_gpio 25 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio26 = 36, /**< gpio_gpio 26 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio27 = 37, /**< gpio_gpio 27 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio28 = 38, /**< gpio_gpio 28 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio29 = 39, /**< gpio_gpio 29 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio30 = 40, /**< gpio_gpio 30 */ + kTopDarjeelingNoIbexPlicIrqIdGpioGpio31 = 41, /**< gpio_gpio 31 */ + kTopDarjeelingNoIbexPlicIrqIdSpiDeviceUploadCmdfifoNotEmpty = 42, /**< spi_device_upload_cmdfifo_not_empty */ + kTopDarjeelingNoIbexPlicIrqIdSpiDeviceUploadPayloadNotEmpty = 43, /**< spi_device_upload_payload_not_empty */ + kTopDarjeelingNoIbexPlicIrqIdSpiDeviceUploadPayloadOverflow = 44, /**< spi_device_upload_payload_overflow */ + kTopDarjeelingNoIbexPlicIrqIdSpiDeviceReadbufWatermark = 45, /**< spi_device_readbuf_watermark */ + kTopDarjeelingNoIbexPlicIrqIdSpiDeviceReadbufFlip = 46, /**< spi_device_readbuf_flip */ + kTopDarjeelingNoIbexPlicIrqIdSpiDeviceTpmHeaderNotEmpty = 47, /**< spi_device_tpm_header_not_empty */ + kTopDarjeelingNoIbexPlicIrqIdSpiDeviceTpmRdfifoCmdEnd = 48, /**< spi_device_tpm_rdfifo_cmd_end */ + kTopDarjeelingNoIbexPlicIrqIdSpiDeviceTpmRdfifoDrop = 49, /**< spi_device_tpm_rdfifo_drop */ + kTopDarjeelingNoIbexPlicIrqIdI2c0FmtThreshold = 50, /**< i2c0_fmt_threshold */ + kTopDarjeelingNoIbexPlicIrqIdI2c0RxThreshold = 51, /**< i2c0_rx_threshold */ + kTopDarjeelingNoIbexPlicIrqIdI2c0AcqThreshold = 52, /**< i2c0_acq_threshold */ + kTopDarjeelingNoIbexPlicIrqIdI2c0RxOverflow = 53, /**< i2c0_rx_overflow */ + kTopDarjeelingNoIbexPlicIrqIdI2c0ControllerHalt = 54, /**< i2c0_controller_halt */ + kTopDarjeelingNoIbexPlicIrqIdI2c0SclInterference = 55, /**< i2c0_scl_interference */ + kTopDarjeelingNoIbexPlicIrqIdI2c0SdaInterference = 56, /**< i2c0_sda_interference */ + kTopDarjeelingNoIbexPlicIrqIdI2c0StretchTimeout = 57, /**< i2c0_stretch_timeout */ + kTopDarjeelingNoIbexPlicIrqIdI2c0SdaUnstable = 58, /**< i2c0_sda_unstable */ + kTopDarjeelingNoIbexPlicIrqIdI2c0CmdComplete = 59, /**< i2c0_cmd_complete */ + kTopDarjeelingNoIbexPlicIrqIdI2c0TxStretch = 60, /**< i2c0_tx_stretch */ + kTopDarjeelingNoIbexPlicIrqIdI2c0TxThreshold = 61, /**< i2c0_tx_threshold */ + kTopDarjeelingNoIbexPlicIrqIdI2c0AcqStretch = 62, /**< i2c0_acq_stretch */ + kTopDarjeelingNoIbexPlicIrqIdI2c0UnexpStop = 63, /**< i2c0_unexp_stop */ + kTopDarjeelingNoIbexPlicIrqIdI2c0HostTimeout = 64, /**< i2c0_host_timeout */ + kTopDarjeelingNoIbexPlicIrqIdOtpCtrlOtpOperationDone = 65, /**< otp_ctrl_otp_operation_done */ + kTopDarjeelingNoIbexPlicIrqIdOtpCtrlOtpError = 66, /**< otp_ctrl_otp_error */ + kTopDarjeelingNoIbexPlicIrqIdAlertHandlerClassa = 67, /**< alert_handler_classa */ + kTopDarjeelingNoIbexPlicIrqIdAlertHandlerClassb = 68, /**< alert_handler_classb */ + kTopDarjeelingNoIbexPlicIrqIdAlertHandlerClassc = 69, /**< alert_handler_classc */ + kTopDarjeelingNoIbexPlicIrqIdAlertHandlerClassd = 70, /**< alert_handler_classd */ + kTopDarjeelingNoIbexPlicIrqIdSpiHost0Error = 71, /**< spi_host0_error */ + kTopDarjeelingNoIbexPlicIrqIdSpiHost0SpiEvent = 72, /**< spi_host0_spi_event */ + kTopDarjeelingNoIbexPlicIrqIdPwrmgrAonWakeup = 73, /**< pwrmgr_aon_wakeup */ + kTopDarjeelingNoIbexPlicIrqIdAonTimerAonWkupTimerExpired = 74, /**< aon_timer_aon_wkup_timer_expired */ + kTopDarjeelingNoIbexPlicIrqIdAonTimerAonWdogTimerBark = 75, /**< aon_timer_aon_wdog_timer_bark */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal0 = 76, /**< soc_proxy_external 0 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal1 = 77, /**< soc_proxy_external 1 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal2 = 78, /**< soc_proxy_external 2 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal3 = 79, /**< soc_proxy_external 3 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal4 = 80, /**< soc_proxy_external 4 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal5 = 81, /**< soc_proxy_external 5 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal6 = 82, /**< soc_proxy_external 6 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal7 = 83, /**< soc_proxy_external 7 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal8 = 84, /**< soc_proxy_external 8 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal9 = 85, /**< soc_proxy_external 9 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal10 = 86, /**< soc_proxy_external 10 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal11 = 87, /**< soc_proxy_external 11 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal12 = 88, /**< soc_proxy_external 12 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal13 = 89, /**< soc_proxy_external 13 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal14 = 90, /**< soc_proxy_external 14 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal15 = 91, /**< soc_proxy_external 15 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal16 = 92, /**< soc_proxy_external 16 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal17 = 93, /**< soc_proxy_external 17 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal18 = 94, /**< soc_proxy_external 18 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal19 = 95, /**< soc_proxy_external 19 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal20 = 96, /**< soc_proxy_external 20 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal21 = 97, /**< soc_proxy_external 21 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal22 = 98, /**< soc_proxy_external 22 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal23 = 99, /**< soc_proxy_external 23 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal24 = 100, /**< soc_proxy_external 24 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal25 = 101, /**< soc_proxy_external 25 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal26 = 102, /**< soc_proxy_external 26 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal27 = 103, /**< soc_proxy_external 27 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal28 = 104, /**< soc_proxy_external 28 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal29 = 105, /**< soc_proxy_external 29 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal30 = 106, /**< soc_proxy_external 30 */ + kTopDarjeelingNoIbexPlicIrqIdSocProxyExternal31 = 107, /**< soc_proxy_external 31 */ + kTopDarjeelingNoIbexPlicIrqIdHmacHmacDone = 108, /**< hmac_hmac_done */ + kTopDarjeelingNoIbexPlicIrqIdHmacFifoEmpty = 109, /**< hmac_fifo_empty */ + kTopDarjeelingNoIbexPlicIrqIdHmacHmacErr = 110, /**< hmac_hmac_err */ + kTopDarjeelingNoIbexPlicIrqIdKmacKmacDone = 111, /**< kmac_kmac_done */ + kTopDarjeelingNoIbexPlicIrqIdKmacFifoEmpty = 112, /**< kmac_fifo_empty */ + kTopDarjeelingNoIbexPlicIrqIdKmacKmacErr = 113, /**< kmac_kmac_err */ + kTopDarjeelingNoIbexPlicIrqIdOtbnDone = 114, /**< otbn_done */ + kTopDarjeelingNoIbexPlicIrqIdKeymgrDpeOpDone = 115, /**< keymgr_dpe_op_done */ + kTopDarjeelingNoIbexPlicIrqIdCsrngCsCmdReqDone = 116, /**< csrng_cs_cmd_req_done */ + kTopDarjeelingNoIbexPlicIrqIdCsrngCsEntropyReq = 117, /**< csrng_cs_entropy_req */ + kTopDarjeelingNoIbexPlicIrqIdCsrngCsHwInstExc = 118, /**< csrng_cs_hw_inst_exc */ + kTopDarjeelingNoIbexPlicIrqIdCsrngCsFatalErr = 119, /**< csrng_cs_fatal_err */ + kTopDarjeelingNoIbexPlicIrqIdEntropySrcEsEntropyValid = 120, /**< entropy_src_es_entropy_valid */ + kTopDarjeelingNoIbexPlicIrqIdEntropySrcEsHealthTestFailed = 121, /**< entropy_src_es_health_test_failed */ + kTopDarjeelingNoIbexPlicIrqIdEntropySrcEsObserveFifoReady = 122, /**< entropy_src_es_observe_fifo_ready */ + kTopDarjeelingNoIbexPlicIrqIdEntropySrcEsFatalErr = 123, /**< entropy_src_es_fatal_err */ + kTopDarjeelingNoIbexPlicIrqIdEdn0EdnCmdReqDone = 124, /**< edn0_edn_cmd_req_done */ + kTopDarjeelingNoIbexPlicIrqIdEdn0EdnFatalErr = 125, /**< edn0_edn_fatal_err */ + kTopDarjeelingNoIbexPlicIrqIdEdn1EdnCmdReqDone = 126, /**< edn1_edn_cmd_req_done */ + kTopDarjeelingNoIbexPlicIrqIdEdn1EdnFatalErr = 127, /**< edn1_edn_fatal_err */ + kTopDarjeelingNoIbexPlicIrqIdDmaDmaDone = 128, /**< dma_dma_done */ + kTopDarjeelingNoIbexPlicIrqIdDmaDmaChunkDone = 129, /**< dma_dma_chunk_done */ + kTopDarjeelingNoIbexPlicIrqIdDmaDmaError = 130, /**< dma_dma_error */ + kTopDarjeelingNoIbexPlicIrqIdMbx0MbxReady = 131, /**< mbx0_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbx0MbxAbort = 132, /**< mbx0_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbx0MbxError = 133, /**< mbx0_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdMbx1MbxReady = 134, /**< mbx1_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbx1MbxAbort = 135, /**< mbx1_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbx1MbxError = 136, /**< mbx1_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdMbx2MbxReady = 137, /**< mbx2_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbx2MbxAbort = 138, /**< mbx2_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbx2MbxError = 139, /**< mbx2_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdMbx3MbxReady = 140, /**< mbx3_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbx3MbxAbort = 141, /**< mbx3_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbx3MbxError = 142, /**< mbx3_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdMbx4MbxReady = 143, /**< mbx4_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbx4MbxAbort = 144, /**< mbx4_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbx4MbxError = 145, /**< mbx4_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdMbx5MbxReady = 146, /**< mbx5_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbx5MbxAbort = 147, /**< mbx5_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbx5MbxError = 148, /**< mbx5_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdMbx6MbxReady = 149, /**< mbx6_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbx6MbxAbort = 150, /**< mbx6_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbx6MbxError = 151, /**< mbx6_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdMbxJtagMbxReady = 152, /**< mbx_jtag_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbxJtagMbxAbort = 153, /**< mbx_jtag_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbxJtagMbxError = 154, /**< mbx_jtag_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdMbxPcie0MbxReady = 155, /**< mbx_pcie0_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbxPcie0MbxAbort = 156, /**< mbx_pcie0_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbxPcie0MbxError = 157, /**< mbx_pcie0_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdMbxPcie1MbxReady = 158, /**< mbx_pcie1_mbx_ready */ + kTopDarjeelingNoIbexPlicIrqIdMbxPcie1MbxAbort = 159, /**< mbx_pcie1_mbx_abort */ + kTopDarjeelingNoIbexPlicIrqIdMbxPcie1MbxError = 160, /**< mbx_pcie1_mbx_error */ + kTopDarjeelingNoIbexPlicIrqIdRaclCtrlRaclError = 161, /**< racl_ctrl_racl_error */ + kTopDarjeelingNoIbexPlicIrqIdAcRangeCheckDenyCntReached = 162, /**< ac_range_check_deny_cnt_reached */ + kTopDarjeelingNoIbexPlicIrqIdLast = 162, /**< \internal The Last Valid Interrupt ID. */ +} top_darjeeling_no_ibex_plic_irq_id_t; + +/** + * PLIC Interrupt Source to Peripheral Map + * + * This array is a mapping from `top_darjeeling_no_ibex_plic_irq_id_t` to + * `top_darjeeling_no_ibex_plic_peripheral_t`. + */ +extern const top_darjeeling_no_ibex_plic_peripheral_t + top_darjeeling_no_ibex_plic_interrupt_for_peripheral[163]; + +/** + * PLIC Interrupt Target. + * + * Enumeration used to determine which set of IE, CC, threshold registers to + * access for a given interrupt target. + */ +typedef enum top_darjeeling_no_ibex_plic_target { + kTopDarjeelingNoIbexPlicTargetIbex0 = 0, /**< Ibex Core 0 */ + kTopDarjeelingNoIbexPlicTargetLast = 0, /**< \internal Final PLIC target */ +} top_darjeeling_no_ibex_plic_target_t; + + +/** + * Alert Handler Source Peripheral. + * + * Enumeration used to determine which peripheral asserted the corresponding + * alert. + */ +typedef enum top_darjeeling_no_ibex_alert_peripheral { + kTopDarjeelingNoIbexAlertPeripheralExternal = 0, /**< External Peripheral */ + kTopDarjeelingNoIbexAlertPeripheralUart0 = 1, /**< uart0 */ + kTopDarjeelingNoIbexAlertPeripheralGpio = 2, /**< gpio */ + kTopDarjeelingNoIbexAlertPeripheralSpiDevice = 3, /**< spi_device */ + kTopDarjeelingNoIbexAlertPeripheralI2c0 = 4, /**< i2c0 */ + kTopDarjeelingNoIbexAlertPeripheralOtpCtrl = 5, /**< otp_ctrl */ + kTopDarjeelingNoIbexAlertPeripheralLcCtrl = 6, /**< lc_ctrl */ + kTopDarjeelingNoIbexAlertPeripheralSpiHost0 = 7, /**< spi_host0 */ + kTopDarjeelingNoIbexAlertPeripheralPwrmgrAon = 8, /**< pwrmgr_aon */ + kTopDarjeelingNoIbexAlertPeripheralRstmgrAon = 9, /**< rstmgr_aon */ + kTopDarjeelingNoIbexAlertPeripheralClkmgrAon = 10, /**< clkmgr_aon */ + kTopDarjeelingNoIbexAlertPeripheralPinmuxAon = 11, /**< pinmux_aon */ + kTopDarjeelingNoIbexAlertPeripheralAonTimerAon = 12, /**< aon_timer_aon */ + kTopDarjeelingNoIbexAlertPeripheralSocProxy = 13, /**< soc_proxy */ + kTopDarjeelingNoIbexAlertPeripheralSramCtrlRetAon = 14, /**< sram_ctrl_ret_aon */ + kTopDarjeelingNoIbexAlertPeripheralRvPlic = 15, /**< rv_plic */ + kTopDarjeelingNoIbexAlertPeripheralAes = 16, /**< aes */ + kTopDarjeelingNoIbexAlertPeripheralHmac = 17, /**< hmac */ + kTopDarjeelingNoIbexAlertPeripheralKmac = 18, /**< kmac */ + kTopDarjeelingNoIbexAlertPeripheralOtbn = 19, /**< otbn */ + kTopDarjeelingNoIbexAlertPeripheralKeymgrDpe = 20, /**< keymgr_dpe */ + kTopDarjeelingNoIbexAlertPeripheralCsrng = 21, /**< csrng */ + kTopDarjeelingNoIbexAlertPeripheralEntropySrc = 22, /**< entropy_src */ + kTopDarjeelingNoIbexAlertPeripheralEdn0 = 23, /**< edn0 */ + kTopDarjeelingNoIbexAlertPeripheralEdn1 = 24, /**< edn1 */ + kTopDarjeelingNoIbexAlertPeripheralSramCtrlMain = 25, /**< sram_ctrl_main */ + kTopDarjeelingNoIbexAlertPeripheralSramCtrlMbox = 26, /**< sram_ctrl_mbox */ + kTopDarjeelingNoIbexAlertPeripheralRomCtrl0 = 27, /**< rom_ctrl0 */ + kTopDarjeelingNoIbexAlertPeripheralRomCtrl1 = 28, /**< rom_ctrl1 */ + kTopDarjeelingNoIbexAlertPeripheralDma = 29, /**< dma */ + kTopDarjeelingNoIbexAlertPeripheralMbx0 = 30, /**< mbx0 */ + kTopDarjeelingNoIbexAlertPeripheralMbx1 = 31, /**< mbx1 */ + kTopDarjeelingNoIbexAlertPeripheralMbx2 = 32, /**< mbx2 */ + kTopDarjeelingNoIbexAlertPeripheralMbx3 = 33, /**< mbx3 */ + kTopDarjeelingNoIbexAlertPeripheralMbx4 = 34, /**< mbx4 */ + kTopDarjeelingNoIbexAlertPeripheralMbx5 = 35, /**< mbx5 */ + kTopDarjeelingNoIbexAlertPeripheralMbx6 = 36, /**< mbx6 */ + kTopDarjeelingNoIbexAlertPeripheralMbxJtag = 37, /**< mbx_jtag */ + kTopDarjeelingNoIbexAlertPeripheralMbxPcie0 = 38, /**< mbx_pcie0 */ + kTopDarjeelingNoIbexAlertPeripheralMbxPcie1 = 39, /**< mbx_pcie1 */ + kTopDarjeelingNoIbexAlertPeripheralSocDbgCtrl = 40, /**< soc_dbg_ctrl */ + kTopDarjeelingNoIbexAlertPeripheralRaclCtrl = 41, /**< racl_ctrl */ + kTopDarjeelingNoIbexAlertPeripheralAcRangeCheck = 42, /**< ac_range_check */ + kTopDarjeelingNoIbexAlertPeripheralLast = 42, /**< \internal Final Alert peripheral */ +} top_darjeeling_no_ibex_alert_peripheral_t; + +/** + * Alert Handler Alert Source. + * + * Enumeration of all Alert Handler Alert Sources. The alert sources belonging to + * the same peripheral are guaranteed to be consecutive. + */ +typedef enum top_darjeeling_no_ibex_alert_id { + kTopDarjeelingNoIbexAlertIdUart0FatalFault = 0, /**< uart0_fatal_fault */ + kTopDarjeelingNoIbexAlertIdGpioFatalFault = 1, /**< gpio_fatal_fault */ + kTopDarjeelingNoIbexAlertIdSpiDeviceFatalFault = 2, /**< spi_device_fatal_fault */ + kTopDarjeelingNoIbexAlertIdI2c0FatalFault = 3, /**< i2c0_fatal_fault */ + kTopDarjeelingNoIbexAlertIdOtpCtrlFatalMacroError = 4, /**< otp_ctrl_fatal_macro_error */ + kTopDarjeelingNoIbexAlertIdOtpCtrlFatalCheckError = 5, /**< otp_ctrl_fatal_check_error */ + kTopDarjeelingNoIbexAlertIdOtpCtrlFatalBusIntegError = 6, /**< otp_ctrl_fatal_bus_integ_error */ + kTopDarjeelingNoIbexAlertIdOtpCtrlFatalPrimOtpAlert = 7, /**< otp_ctrl_fatal_prim_otp_alert */ + kTopDarjeelingNoIbexAlertIdOtpCtrlRecovPrimOtpAlert = 8, /**< otp_ctrl_recov_prim_otp_alert */ + kTopDarjeelingNoIbexAlertIdLcCtrlFatalProgError = 9, /**< lc_ctrl_fatal_prog_error */ + kTopDarjeelingNoIbexAlertIdLcCtrlFatalStateError = 10, /**< lc_ctrl_fatal_state_error */ + kTopDarjeelingNoIbexAlertIdLcCtrlFatalBusIntegError = 11, /**< lc_ctrl_fatal_bus_integ_error */ + kTopDarjeelingNoIbexAlertIdSpiHost0FatalFault = 12, /**< spi_host0_fatal_fault */ + kTopDarjeelingNoIbexAlertIdPwrmgrAonFatalFault = 13, /**< pwrmgr_aon_fatal_fault */ + kTopDarjeelingNoIbexAlertIdRstmgrAonFatalFault = 14, /**< rstmgr_aon_fatal_fault */ + kTopDarjeelingNoIbexAlertIdRstmgrAonFatalCnstyFault = 15, /**< rstmgr_aon_fatal_cnsty_fault */ + kTopDarjeelingNoIbexAlertIdClkmgrAonRecovFault = 16, /**< clkmgr_aon_recov_fault */ + kTopDarjeelingNoIbexAlertIdClkmgrAonFatalFault = 17, /**< clkmgr_aon_fatal_fault */ + kTopDarjeelingNoIbexAlertIdPinmuxAonFatalFault = 18, /**< pinmux_aon_fatal_fault */ + kTopDarjeelingNoIbexAlertIdAonTimerAonFatalFault = 19, /**< aon_timer_aon_fatal_fault */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertIntg = 20, /**< soc_proxy_fatal_alert_intg */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal0 = 21, /**< soc_proxy_fatal_alert_external_0 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal1 = 22, /**< soc_proxy_fatal_alert_external_1 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal2 = 23, /**< soc_proxy_fatal_alert_external_2 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal3 = 24, /**< soc_proxy_fatal_alert_external_3 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal4 = 25, /**< soc_proxy_fatal_alert_external_4 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal5 = 26, /**< soc_proxy_fatal_alert_external_5 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal6 = 27, /**< soc_proxy_fatal_alert_external_6 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal7 = 28, /**< soc_proxy_fatal_alert_external_7 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal8 = 29, /**< soc_proxy_fatal_alert_external_8 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal9 = 30, /**< soc_proxy_fatal_alert_external_9 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal10 = 31, /**< soc_proxy_fatal_alert_external_10 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal11 = 32, /**< soc_proxy_fatal_alert_external_11 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal12 = 33, /**< soc_proxy_fatal_alert_external_12 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal13 = 34, /**< soc_proxy_fatal_alert_external_13 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal14 = 35, /**< soc_proxy_fatal_alert_external_14 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal15 = 36, /**< soc_proxy_fatal_alert_external_15 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal16 = 37, /**< soc_proxy_fatal_alert_external_16 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal17 = 38, /**< soc_proxy_fatal_alert_external_17 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal18 = 39, /**< soc_proxy_fatal_alert_external_18 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal19 = 40, /**< soc_proxy_fatal_alert_external_19 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal20 = 41, /**< soc_proxy_fatal_alert_external_20 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal21 = 42, /**< soc_proxy_fatal_alert_external_21 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal22 = 43, /**< soc_proxy_fatal_alert_external_22 */ + kTopDarjeelingNoIbexAlertIdSocProxyFatalAlertExternal23 = 44, /**< soc_proxy_fatal_alert_external_23 */ + kTopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal0 = 45, /**< soc_proxy_recov_alert_external_0 */ + kTopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal1 = 46, /**< soc_proxy_recov_alert_external_1 */ + kTopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal2 = 47, /**< soc_proxy_recov_alert_external_2 */ + kTopDarjeelingNoIbexAlertIdSocProxyRecovAlertExternal3 = 48, /**< soc_proxy_recov_alert_external_3 */ + kTopDarjeelingNoIbexAlertIdSramCtrlRetAonFatalError = 49, /**< sram_ctrl_ret_aon_fatal_error */ + kTopDarjeelingNoIbexAlertIdRvPlicFatalFault = 50, /**< rv_plic_fatal_fault */ + kTopDarjeelingNoIbexAlertIdAesRecovCtrlUpdateErr = 51, /**< aes_recov_ctrl_update_err */ + kTopDarjeelingNoIbexAlertIdAesFatalFault = 52, /**< aes_fatal_fault */ + kTopDarjeelingNoIbexAlertIdHmacFatalFault = 53, /**< hmac_fatal_fault */ + kTopDarjeelingNoIbexAlertIdKmacRecovOperationErr = 54, /**< kmac_recov_operation_err */ + kTopDarjeelingNoIbexAlertIdKmacFatalFaultErr = 55, /**< kmac_fatal_fault_err */ + kTopDarjeelingNoIbexAlertIdOtbnFatal = 56, /**< otbn_fatal */ + kTopDarjeelingNoIbexAlertIdOtbnRecov = 57, /**< otbn_recov */ + kTopDarjeelingNoIbexAlertIdKeymgrDpeRecovOperationErr = 58, /**< keymgr_dpe_recov_operation_err */ + kTopDarjeelingNoIbexAlertIdKeymgrDpeFatalFaultErr = 59, /**< keymgr_dpe_fatal_fault_err */ + kTopDarjeelingNoIbexAlertIdCsrngRecovAlert = 60, /**< csrng_recov_alert */ + kTopDarjeelingNoIbexAlertIdCsrngFatalAlert = 61, /**< csrng_fatal_alert */ + kTopDarjeelingNoIbexAlertIdEntropySrcRecovAlert = 62, /**< entropy_src_recov_alert */ + kTopDarjeelingNoIbexAlertIdEntropySrcFatalAlert = 63, /**< entropy_src_fatal_alert */ + kTopDarjeelingNoIbexAlertIdEdn0RecovAlert = 64, /**< edn0_recov_alert */ + kTopDarjeelingNoIbexAlertIdEdn0FatalAlert = 65, /**< edn0_fatal_alert */ + kTopDarjeelingNoIbexAlertIdEdn1RecovAlert = 66, /**< edn1_recov_alert */ + kTopDarjeelingNoIbexAlertIdEdn1FatalAlert = 67, /**< edn1_fatal_alert */ + kTopDarjeelingNoIbexAlertIdSramCtrlMainFatalError = 68, /**< sram_ctrl_main_fatal_error */ + kTopDarjeelingNoIbexAlertIdSramCtrlMboxFatalError = 69, /**< sram_ctrl_mbox_fatal_error */ + kTopDarjeelingNoIbexAlertIdRomCtrl0Fatal = 70, /**< rom_ctrl0_fatal */ + kTopDarjeelingNoIbexAlertIdRomCtrl1Fatal = 71, /**< rom_ctrl1_fatal */ + kTopDarjeelingNoIbexAlertIdDmaFatalFault = 72, /**< dma_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbx0FatalFault = 73, /**< mbx0_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbx0RecovFault = 74, /**< mbx0_recov_fault */ + kTopDarjeelingNoIbexAlertIdMbx1FatalFault = 75, /**< mbx1_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbx1RecovFault = 76, /**< mbx1_recov_fault */ + kTopDarjeelingNoIbexAlertIdMbx2FatalFault = 77, /**< mbx2_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbx2RecovFault = 78, /**< mbx2_recov_fault */ + kTopDarjeelingNoIbexAlertIdMbx3FatalFault = 79, /**< mbx3_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbx3RecovFault = 80, /**< mbx3_recov_fault */ + kTopDarjeelingNoIbexAlertIdMbx4FatalFault = 81, /**< mbx4_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbx4RecovFault = 82, /**< mbx4_recov_fault */ + kTopDarjeelingNoIbexAlertIdMbx5FatalFault = 83, /**< mbx5_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbx5RecovFault = 84, /**< mbx5_recov_fault */ + kTopDarjeelingNoIbexAlertIdMbx6FatalFault = 85, /**< mbx6_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbx6RecovFault = 86, /**< mbx6_recov_fault */ + kTopDarjeelingNoIbexAlertIdMbxJtagFatalFault = 87, /**< mbx_jtag_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbxJtagRecovFault = 88, /**< mbx_jtag_recov_fault */ + kTopDarjeelingNoIbexAlertIdMbxPcie0FatalFault = 89, /**< mbx_pcie0_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbxPcie0RecovFault = 90, /**< mbx_pcie0_recov_fault */ + kTopDarjeelingNoIbexAlertIdMbxPcie1FatalFault = 91, /**< mbx_pcie1_fatal_fault */ + kTopDarjeelingNoIbexAlertIdMbxPcie1RecovFault = 92, /**< mbx_pcie1_recov_fault */ + kTopDarjeelingNoIbexAlertIdSocDbgCtrlFatalFault = 93, /**< soc_dbg_ctrl_fatal_fault */ + kTopDarjeelingNoIbexAlertIdSocDbgCtrlRecovCtrlUpdateErr = 94, /**< soc_dbg_ctrl_recov_ctrl_update_err */ + kTopDarjeelingNoIbexAlertIdRaclCtrlFatalFault = 95, /**< racl_ctrl_fatal_fault */ + kTopDarjeelingNoIbexAlertIdRaclCtrlRecovCtrlUpdateErr = 96, /**< racl_ctrl_recov_ctrl_update_err */ + kTopDarjeelingNoIbexAlertIdAcRangeCheckRecovCtrlUpdateErr = 97, /**< ac_range_check_recov_ctrl_update_err */ + kTopDarjeelingNoIbexAlertIdAcRangeCheckFatalFault = 98, /**< ac_range_check_fatal_fault */ + kTopDarjeelingNoIbexAlertIdLast = 98, /**< \internal The Last Valid Alert ID. */ +} top_darjeeling_no_ibex_alert_id_t; + +/** + * Alert Handler Alert Source to Peripheral Map + * + * This array is a mapping from `top_darjeeling_no_ibex_alert_id_t` to + * `top_darjeeling_no_ibex_alert_peripheral_t`. + */ +extern const top_darjeeling_no_ibex_alert_peripheral_t + top_darjeeling_no_ibex_alert_for_peripheral[99]; + +#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2 + +// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1} +// 0 and 1 are tied to value 0 and 1 +#define NUM_MIO_PADS 12 +#define NUM_DIO_PADS 73 + +#define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3 + +/** + * Pinmux Peripheral Input. + */ +typedef enum top_darjeeling_no_ibex_pinmux_peripheral_in { + kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi12 = 0, /**< Peripheral Input 0 */ + kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi13 = 1, /**< Peripheral Input 1 */ + kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi14 = 2, /**< Peripheral Input 2 */ + kTopDarjeelingNoIbexPinmuxPeripheralInSocProxySocGpi15 = 3, /**< Peripheral Input 3 */ + kTopDarjeelingNoIbexPinmuxPeripheralInLast = 3, /**< \internal Last valid peripheral input */ +} top_darjeeling_no_ibex_pinmux_peripheral_in_t; + +/** + * Pinmux MIO Input Selector. + */ +typedef enum top_darjeeling_no_ibex_pinmux_insel { + kTopDarjeelingNoIbexPinmuxInselConstantZero = 0, /**< Tie constantly to zero */ + kTopDarjeelingNoIbexPinmuxInselConstantOne = 1, /**< Tie constantly to one */ + kTopDarjeelingNoIbexPinmuxInselMio0 = 2, /**< MIO Pad 0 */ + kTopDarjeelingNoIbexPinmuxInselMio1 = 3, /**< MIO Pad 1 */ + kTopDarjeelingNoIbexPinmuxInselMio2 = 4, /**< MIO Pad 2 */ + kTopDarjeelingNoIbexPinmuxInselMio3 = 5, /**< MIO Pad 3 */ + kTopDarjeelingNoIbexPinmuxInselMio4 = 6, /**< MIO Pad 4 */ + kTopDarjeelingNoIbexPinmuxInselMio5 = 7, /**< MIO Pad 5 */ + kTopDarjeelingNoIbexPinmuxInselMio6 = 8, /**< MIO Pad 6 */ + kTopDarjeelingNoIbexPinmuxInselMio7 = 9, /**< MIO Pad 7 */ + kTopDarjeelingNoIbexPinmuxInselMio8 = 10, /**< MIO Pad 8 */ + kTopDarjeelingNoIbexPinmuxInselMio9 = 11, /**< MIO Pad 9 */ + kTopDarjeelingNoIbexPinmuxInselMio10 = 12, /**< MIO Pad 10 */ + kTopDarjeelingNoIbexPinmuxInselMio11 = 13, /**< MIO Pad 11 */ + kTopDarjeelingNoIbexPinmuxInselLast = 13, /**< \internal Last valid insel value */ +} top_darjeeling_no_ibex_pinmux_insel_t; + +/** + * Pinmux MIO Output. + */ +typedef enum top_darjeeling_no_ibex_pinmux_mio_out { + kTopDarjeelingNoIbexPinmuxMioOutMio0 = 0, /**< MIO Pad 0 */ + kTopDarjeelingNoIbexPinmuxMioOutMio1 = 1, /**< MIO Pad 1 */ + kTopDarjeelingNoIbexPinmuxMioOutMio2 = 2, /**< MIO Pad 2 */ + kTopDarjeelingNoIbexPinmuxMioOutMio3 = 3, /**< MIO Pad 3 */ + kTopDarjeelingNoIbexPinmuxMioOutMio4 = 4, /**< MIO Pad 4 */ + kTopDarjeelingNoIbexPinmuxMioOutMio5 = 5, /**< MIO Pad 5 */ + kTopDarjeelingNoIbexPinmuxMioOutMio6 = 6, /**< MIO Pad 6 */ + kTopDarjeelingNoIbexPinmuxMioOutMio7 = 7, /**< MIO Pad 7 */ + kTopDarjeelingNoIbexPinmuxMioOutMio8 = 8, /**< MIO Pad 8 */ + kTopDarjeelingNoIbexPinmuxMioOutMio9 = 9, /**< MIO Pad 9 */ + kTopDarjeelingNoIbexPinmuxMioOutMio10 = 10, /**< MIO Pad 10 */ + kTopDarjeelingNoIbexPinmuxMioOutMio11 = 11, /**< MIO Pad 11 */ + kTopDarjeelingNoIbexPinmuxMioOutLast = 11, /**< \internal Last valid mio output */ +} top_darjeeling_no_ibex_pinmux_mio_out_t; + +/** + * Pinmux Peripheral Output Selector. + */ +typedef enum top_darjeeling_no_ibex_pinmux_outsel { + kTopDarjeelingNoIbexPinmuxOutselConstantZero = 0, /**< Tie constantly to zero */ + kTopDarjeelingNoIbexPinmuxOutselConstantOne = 1, /**< Tie constantly to one */ + kTopDarjeelingNoIbexPinmuxOutselConstantHighZ = 2, /**< Tie constantly to high-Z */ + kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo12 = 3, /**< Peripheral Output 0 */ + kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo13 = 4, /**< Peripheral Output 1 */ + kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo14 = 5, /**< Peripheral Output 2 */ + kTopDarjeelingNoIbexPinmuxOutselSocProxySocGpo15 = 6, /**< Peripheral Output 3 */ + kTopDarjeelingNoIbexPinmuxOutselOtpMacroTest0 = 7, /**< Peripheral Output 4 */ + kTopDarjeelingNoIbexPinmuxOutselLast = 7, /**< \internal Last valid outsel value */ +} top_darjeeling_no_ibex_pinmux_outsel_t; + +/** + * Dedicated Pad Selects + */ +typedef enum top_darjeeling_no_ibex_direct_pads { + kTopDarjeelingNoIbexDirectPadsSpiHost0Sd0 = 0, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiHost0Sd1 = 1, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiHost0Sd2 = 2, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiHost0Sd3 = 3, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiDeviceSd0 = 4, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiDeviceSd1 = 5, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiDeviceSd2 = 6, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiDeviceSd3 = 7, /**< */ + kTopDarjeelingNoIbexDirectPadsI2c0Scl = 8, /**< */ + kTopDarjeelingNoIbexDirectPadsI2c0Sda = 9, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio0 = 10, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio1 = 11, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio2 = 12, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio3 = 13, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio4 = 14, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio5 = 15, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio6 = 16, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio7 = 17, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio8 = 18, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio9 = 19, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio10 = 20, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio11 = 21, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio12 = 22, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio13 = 23, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio14 = 24, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio15 = 25, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio16 = 26, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio17 = 27, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio18 = 28, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio19 = 29, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio20 = 30, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio21 = 31, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio22 = 32, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio23 = 33, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio24 = 34, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio25 = 35, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio26 = 36, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio27 = 37, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio28 = 38, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio29 = 39, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio30 = 40, /**< */ + kTopDarjeelingNoIbexDirectPadsGpioGpio31 = 41, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiDeviceSck = 42, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiDeviceCsb = 43, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiDeviceTpmCsb = 44, /**< */ + kTopDarjeelingNoIbexDirectPadsUart0Rx = 45, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi0 = 46, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi1 = 47, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi2 = 48, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi3 = 49, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi4 = 50, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi5 = 51, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi6 = 52, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi7 = 53, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi8 = 54, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi9 = 55, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi10 = 56, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpi11 = 57, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiHost0Sck = 58, /**< */ + kTopDarjeelingNoIbexDirectPadsSpiHost0Csb = 59, /**< */ + kTopDarjeelingNoIbexDirectPadsUart0Tx = 60, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo0 = 61, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo1 = 62, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo2 = 63, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo3 = 64, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo4 = 65, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo5 = 66, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo6 = 67, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo7 = 68, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo8 = 69, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo9 = 70, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo10 = 71, /**< */ + kTopDarjeelingNoIbexDirectPadsSocProxySocGpo11 = 72, /**< */ + kTopDarjeelingNoIbexDirectPadsLast = 72, /**< \internal Last valid direct pad */ +} top_darjeeling_no_ibex_direct_pads_t; + +/** + * Muxed Pad Selects + */ +typedef enum top_darjeeling_no_ibex_muxed_pads { + kTopDarjeelingNoIbexMuxedPadsMio0 = 0, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio1 = 1, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio2 = 2, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio3 = 3, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio4 = 4, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio5 = 5, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio6 = 6, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio7 = 7, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio8 = 8, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio9 = 9, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio10 = 10, /**< */ + kTopDarjeelingNoIbexMuxedPadsMio11 = 11, /**< */ + kTopDarjeelingNoIbexMuxedPadsLast = 11, /**< \internal Last valid muxed pad */ +} top_darjeeling_no_ibex_muxed_pads_t; + +/** + * Power Manager Wakeup Signals + */ +typedef enum top_darjeeling_no_ibex_power_manager_wake_ups { + kTopDarjeelingNoIbexPowerManagerWakeUpsPinmuxAonPinWkupReq = 0, /**< */ + kTopDarjeelingNoIbexPowerManagerWakeUpsAonTimerAonWkupReq = 1, /**< */ + kTopDarjeelingNoIbexPowerManagerWakeUpsSocProxyWkupInternalReq = 2, /**< */ + kTopDarjeelingNoIbexPowerManagerWakeUpsSocProxyWkupExternalReq = 3, /**< */ + kTopDarjeelingNoIbexPowerManagerWakeUpsLast = 3, /**< \internal Last valid pwrmgr wakeup signal */ +} top_darjeeling_no_ibex_power_manager_wake_ups_t; + +/** + * Reset Manager Software Controlled Resets + */ +typedef enum top_darjeeling_no_ibex_reset_manager_sw_resets { + kTopDarjeelingNoIbexResetManagerSwResetsSpiDevice = 0, /**< */ + kTopDarjeelingNoIbexResetManagerSwResetsSpiHost0 = 1, /**< */ + kTopDarjeelingNoIbexResetManagerSwResetsI2c0 = 2, /**< */ + kTopDarjeelingNoIbexResetManagerSwResetsLast = 2, /**< \internal Last valid rstmgr software reset request */ +} top_darjeeling_no_ibex_reset_manager_sw_resets_t; + +/** + * Power Manager Reset Request Signals + */ +typedef enum top_darjeeling_no_ibex_power_manager_reset_requests { + kTopDarjeelingNoIbexPowerManagerResetRequestsAonTimerAonAonTimerRstReq = 0, /**< */ + kTopDarjeelingNoIbexPowerManagerResetRequestsSocProxyRstReqExternal = 1, /**< */ + kTopDarjeelingNoIbexPowerManagerResetRequestsLast = 1, /**< \internal Last valid pwrmgr reset_request signal */ +} top_darjeeling_no_ibex_power_manager_reset_requests_t; + +/** + * Clock Manager Software-Controlled ("Gated") Clocks. + * + * The Software has full control over these clocks. + */ +typedef enum top_darjeeling_no_ibex_gateable_clocks { + kTopDarjeelingNoIbexGateableClocksIoDiv4Peri = 0, /**< Clock clk_io_div4_peri in group peri */ + kTopDarjeelingNoIbexGateableClocksIoDiv2Peri = 1, /**< Clock clk_io_div2_peri in group peri */ + kTopDarjeelingNoIbexGateableClocksLast = 1, /**< \internal Last Valid Gateable Clock */ +} top_darjeeling_no_ibex_gateable_clocks_t; + +/** + * Clock Manager Software-Hinted Clocks. + * + * The Software has partial control over these clocks. It can ask them to stop, + * but the clock manager is in control of whether the clock actually is stopped. + */ +typedef enum top_darjeeling_no_ibex_hintable_clocks { + kTopDarjeelingNoIbexHintableClocksMainAes = 0, /**< Clock clk_main_aes in group trans */ + kTopDarjeelingNoIbexHintableClocksMainHmac = 1, /**< Clock clk_main_hmac in group trans */ + kTopDarjeelingNoIbexHintableClocksMainKmac = 2, /**< Clock clk_main_kmac in group trans */ + kTopDarjeelingNoIbexHintableClocksMainOtbn = 3, /**< Clock clk_main_otbn in group trans */ + kTopDarjeelingNoIbexHintableClocksLast = 3, /**< \internal Last Valid Hintable Clock */ +} top_darjeeling_no_ibex_hintable_clocks_t; + +/** + * MMIO Region + * + * MMIO region excludes any memory that is separate from the module + * configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but + * retention SRAM or spi_device are included. + */ +#define TOP_DARJEELING_NO_IBEX_MMIO_BASE_ADDR 0x21100000u +#define TOP_DARJEELING_NO_IBEX_MMIO_SIZE_BYTES 0xF501000u + +// Header Extern Guard +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_H_ diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_memory.h b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_memory.h new file mode 100644 index 00000000000..9ceae859551 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_memory.h @@ -0,0 +1,935 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex + +#ifndef OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_MEMORY_H_ +#define OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_MEMORY_H_ + +/** + * @file + * @brief Assembler-only Top-Specific Definitions. + * + * This file contains preprocessor definitions for use within assembly code. + * + * These are not shared with C/C++ code because these are only allowed to be + * preprocessor definitions, no data or type declarations are allowed. The + * assembler is also stricter about literals (not allowing suffixes for + * signed/unsigned which are sensible to use for unsigned values in C/C++). + */ + +// Include guard for assembler +#ifdef __ASSEMBLER__ +/** + * Memory base for soc_proxy_ctn in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_CTN_BASE_ADDR 0x40000000 + +/** + * Memory size for soc_proxy_ctn in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_CTN_SIZE_BYTES 0x40000000 + +/** + * Memory base for sram_ctrl_ret_aon_ram_ret_aon in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_RET_AON_BASE_ADDR 0x30600000 + +/** + * Memory size for sram_ctrl_ret_aon_ram_ret_aon in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_RET_AON_SIZE_BYTES 0x1000 + +/** + * Memory base for sram_ctrl_main_ram_main in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_MAIN_BASE_ADDR 0x10000000 + +/** + * Memory size for sram_ctrl_main_ram_main in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_MAIN_SIZE_BYTES 0x10000 + +/** + * Memory base for sram_ctrl_mbox_ram_mbox in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_MBOX_BASE_ADDR 0x11000000 + +/** + * Memory size for sram_ctrl_mbox_ram_mbox in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_RAM_MBOX_SIZE_BYTES 0x1000 + +/** + * Memory base for rom_ctrl0_rom0 in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_ROM0_BASE_ADDR 0x00008000 + +/** + * Memory size for rom_ctrl0_rom0 in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_ROM0_SIZE_BYTES 0x8000 + +/** + * Memory base for rom_ctrl1_rom1 in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_ROM1_BASE_ADDR 0x00020000 + +/** + * Memory size for rom_ctrl1_rom1 in top darjeeling_no_ibex. + */ +#define TOP_DARJEELING_NO_IBEX_ROM1_SIZE_BYTES 0x10000 + + + +/** + * Peripheral base address for uart0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_UART0_BASE_ADDR 0x30010000 + +/** + * Peripheral size for uart0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_UART0_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_UART0_BASE_ADDR + TOP_DARJEELING_NO_IBEX_UART0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_UART0_SIZE_BYTES 0x40 +/** + * Peripheral base address for gpio in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_GPIO_BASE_ADDR 0x30000000 + +/** + * Peripheral size for gpio in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_GPIO_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_GPIO_BASE_ADDR + TOP_DARJEELING_NO_IBEX_GPIO_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_GPIO_SIZE_BYTES 0x100 +/** + * Peripheral base address for spi_device in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SPI_DEVICE_BASE_ADDR 0x30310000 + +/** + * Peripheral size for spi_device in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SPI_DEVICE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SPI_DEVICE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SPI_DEVICE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SPI_DEVICE_SIZE_BYTES 0x2000 +/** + * Peripheral base address for i2c0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_I2C0_BASE_ADDR 0x30080000 + +/** + * Peripheral size for i2c0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_I2C0_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_I2C0_BASE_ADDR + TOP_DARJEELING_NO_IBEX_I2C0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_I2C0_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on otp_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_BASE_ADDR 0x30130000 + +/** + * Peripheral size for core device on otp_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_OTP_CTRL_CORE_SIZE_BYTES 0x8000 +/** + * Peripheral base address for prim device on otp_macro in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_BASE_ADDR 0x30140000 + +/** + * Peripheral size for prim device on otp_macro in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_OTP_MACRO_PRIM_SIZE_BYTES 0x20 +/** + * Peripheral base address for regs device on lc_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_BASE_ADDR 0x30150000 + +/** + * Peripheral size for regs device on lc_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_LC_CTRL_REGS_SIZE_BYTES 0x100 +/** + * Peripheral base address for alert_handler in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_BASE_ADDR 0x30160000 + +/** + * Peripheral size for alert_handler in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ALERT_HANDLER_SIZE_BYTES 0x800 +/** + * Peripheral base address for spi_host0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SPI_HOST0_BASE_ADDR 0x30300000 + +/** + * Peripheral size for spi_host0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SPI_HOST0_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SPI_HOST0_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SPI_HOST0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SPI_HOST0_SIZE_BYTES 0x40 +/** + * Peripheral base address for pwrmgr_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_PWRMGR_AON_BASE_ADDR 0x30400000 + +/** + * Peripheral size for pwrmgr_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_PWRMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_PWRMGR_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_PWRMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_PWRMGR_AON_SIZE_BYTES 0x80 +/** + * Peripheral base address for rstmgr_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_RSTMGR_AON_BASE_ADDR 0x30410000 + +/** + * Peripheral size for rstmgr_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_RSTMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_RSTMGR_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_RSTMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_RSTMGR_AON_SIZE_BYTES 0x80 +/** + * Peripheral base address for clkmgr_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_CLKMGR_AON_BASE_ADDR 0x30420000 + +/** + * Peripheral size for clkmgr_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_CLKMGR_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_CLKMGR_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_CLKMGR_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_CLKMGR_AON_SIZE_BYTES 0x40 +/** + * Peripheral base address for pinmux_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_PINMUX_AON_BASE_ADDR 0x30460000 + +/** + * Peripheral size for pinmux_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_PINMUX_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_PINMUX_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_PINMUX_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_PINMUX_AON_SIZE_BYTES 0x800 +/** + * Peripheral base address for aon_timer_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_BASE_ADDR 0x30470000 + +/** + * Peripheral size for aon_timer_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_BASE_ADDR + TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_AON_TIMER_AON_SIZE_BYTES 0x40 +/** + * Peripheral base address for ast in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_AST_BASE_ADDR 0x30480000 + +/** + * Peripheral size for ast in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_AST_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_AST_BASE_ADDR + TOP_DARJEELING_NO_IBEX_AST_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_AST_SIZE_BYTES 0x400 +/** + * Peripheral base address for core device on soc_proxy in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_BASE_ADDR 0x22030000 + +/** + * Peripheral size for core device on soc_proxy in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_PROXY_CORE_SIZE_BYTES 0x10 +/** + * Peripheral base address for ctn device on soc_proxy in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_BASE_ADDR 0x40000000 + +/** + * Peripheral size for ctn device on soc_proxy in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_PROXY_CTN_SIZE_BYTES 0x40000000 +/** + * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x30500000 + +/** + * Peripheral size for regs device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40 +/** + * Peripheral base address for ram device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x30600000 + +/** + * Peripheral size for ram device on sram_ctrl_ret_aon in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000 +/** + * Peripheral base address for rv_plic in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_RV_PLIC_BASE_ADDR 0x28000000 + +/** + * Peripheral size for rv_plic in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_RV_PLIC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_RV_PLIC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_RV_PLIC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_RV_PLIC_SIZE_BYTES 0x8000000 +/** + * Peripheral base address for aes in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_AES_BASE_ADDR 0x21100000 + +/** + * Peripheral size for aes in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_AES_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_AES_BASE_ADDR + TOP_DARJEELING_NO_IBEX_AES_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_AES_SIZE_BYTES 0x100 +/** + * Peripheral base address for hmac in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_HMAC_BASE_ADDR 0x21110000 + +/** + * Peripheral size for hmac in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_HMAC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_HMAC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_HMAC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_HMAC_SIZE_BYTES 0x2000 +/** + * Peripheral base address for kmac in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_KMAC_BASE_ADDR 0x21120000 + +/** + * Peripheral size for kmac in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_KMAC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_KMAC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_KMAC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_KMAC_SIZE_BYTES 0x1000 +/** + * Peripheral base address for otbn in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_OTBN_BASE_ADDR 0x21130000 + +/** + * Peripheral size for otbn in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_OTBN_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_OTBN_BASE_ADDR + TOP_DARJEELING_NO_IBEX_OTBN_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_OTBN_SIZE_BYTES 0x10000 +/** + * Peripheral base address for keymgr_dpe in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_BASE_ADDR 0x21140000 + +/** + * Peripheral size for keymgr_dpe in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_KEYMGR_DPE_SIZE_BYTES 0x100 +/** + * Peripheral base address for csrng in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_CSRNG_BASE_ADDR 0x21150000 + +/** + * Peripheral size for csrng in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_CSRNG_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_CSRNG_BASE_ADDR + TOP_DARJEELING_NO_IBEX_CSRNG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_CSRNG_SIZE_BYTES 0x80 +/** + * Peripheral base address for entropy_src in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_BASE_ADDR 0x21160000 + +/** + * Peripheral size for entropy_src in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ENTROPY_SRC_SIZE_BYTES 0x100 +/** + * Peripheral base address for edn0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_EDN0_BASE_ADDR 0x21170000 + +/** + * Peripheral size for edn0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_EDN0_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_EDN0_BASE_ADDR + TOP_DARJEELING_NO_IBEX_EDN0_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_EDN0_SIZE_BYTES 0x80 +/** + * Peripheral base address for edn1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_EDN1_BASE_ADDR 0x21180000 + +/** + * Peripheral size for edn1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_EDN1_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_EDN1_BASE_ADDR + TOP_DARJEELING_NO_IBEX_EDN1_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_EDN1_SIZE_BYTES 0x80 +/** + * Peripheral base address for regs device on sram_ctrl_main in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x211C0000 + +/** + * Peripheral size for regs device on sram_ctrl_main in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40 +/** + * Peripheral base address for ram device on sram_ctrl_main in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000 + +/** + * Peripheral size for ram device on sram_ctrl_main in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x10000 +/** + * Peripheral base address for regs device on sram_ctrl_mbox in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_BASE_ADDR 0x211D0000 + +/** + * Peripheral size for regs device on sram_ctrl_mbox in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_REGS_SIZE_BYTES 0x40 +/** + * Peripheral base address for ram device on sram_ctrl_mbox in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_BASE_ADDR 0x11000000 + +/** + * Peripheral size for ram device on sram_ctrl_mbox in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SRAM_CTRL_MBOX_RAM_SIZE_BYTES 0x1000 +/** + * Peripheral base address for regs device on rom_ctrl0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_BASE_ADDR 0x211E0000 + +/** + * Peripheral size for regs device on rom_ctrl0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL0_REGS_SIZE_BYTES 0x80 +/** + * Peripheral base address for rom device on rom_ctrl0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_BASE_ADDR 0x8000 + +/** + * Peripheral size for rom device on rom_ctrl0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL0_ROM_SIZE_BYTES 0x8000 +/** + * Peripheral base address for regs device on rom_ctrl1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_BASE_ADDR 0x211E1000 + +/** + * Peripheral size for regs device on rom_ctrl1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL1_REGS_SIZE_BYTES 0x80 +/** + * Peripheral base address for rom device on rom_ctrl1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_BASE_ADDR 0x20000 + +/** + * Peripheral size for rom device on rom_ctrl1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_BASE_ADDR + TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_ROM_CTRL1_ROM_SIZE_BYTES 0x10000 +/** + * Peripheral base address for dma in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_DMA_BASE_ADDR 0x22010000 + +/** + * Peripheral size for dma in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_DMA_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_DMA_BASE_ADDR + TOP_DARJEELING_NO_IBEX_DMA_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_DMA_SIZE_BYTES 0x200 +/** + * Peripheral base address for core device on mbx0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX0_CORE_BASE_ADDR 0x22000000 + +/** + * Peripheral size for core device on mbx0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX0_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX0_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX0_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX0_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX1_CORE_BASE_ADDR 0x22000100 + +/** + * Peripheral size for core device on mbx1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX1_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX1_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX1_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX1_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx2 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX2_CORE_BASE_ADDR 0x22000200 + +/** + * Peripheral size for core device on mbx2 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX2_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX2_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX2_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX2_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx3 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX3_CORE_BASE_ADDR 0x22000300 + +/** + * Peripheral size for core device on mbx3 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX3_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX3_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX3_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX3_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx4 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX4_CORE_BASE_ADDR 0x22000400 + +/** + * Peripheral size for core device on mbx4 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX4_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX4_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX4_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX4_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx5 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX5_CORE_BASE_ADDR 0x22000500 + +/** + * Peripheral size for core device on mbx5 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX5_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX5_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX5_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX5_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx6 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX6_CORE_BASE_ADDR 0x22000600 + +/** + * Peripheral size for core device on mbx6 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX6_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX6_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX6_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX6_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx_jtag in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_BASE_ADDR 0x22000800 + +/** + * Peripheral size for core device on mbx_jtag in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX_JTAG_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx_pcie0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_BASE_ADDR 0x22040000 + +/** + * Peripheral size for core device on mbx_pcie0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX_PCIE0_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on mbx_pcie1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_BASE_ADDR 0x22040100 + +/** + * Peripheral size for core device on mbx_pcie1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_MBX_PCIE1_CORE_SIZE_BYTES 0x80 +/** + * Peripheral base address for core device on soc_dbg_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_BASE_ADDR 0x30170000 + +/** + * Peripheral size for core device on soc_dbg_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_CTRL_CORE_SIZE_BYTES 0x20 + +/** + * MMIO Region + * + * MMIO region excludes any memory that is separate from the module + * configuration space, i.e. ROM, main SRAM, and mbx SRAM are excluded but + * retention SRAM or spi_device are included. + */ +#define TOP_DARJEELING_NO_IBEX_MMIO_BASE_ADDR 0x21100000 +#define TOP_DARJEELING_NO_IBEX_MMIO_SIZE_BYTES 0xF501000 + +#endif // __ASSEMBLER__ + +#endif // OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_MEMORY_H_ diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_memory.ld b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_memory.ld new file mode 100644 index 00000000000..5de0d0159c1 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_memory.ld @@ -0,0 +1,64 @@ +/* Copyright lowRISC contributors (OpenTitan project). */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ +/* + * ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! ------------------- * + * PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: + * util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson + * -o hw/top_darjeeling_no_ibex + */ + +/** + * Partial linker script for chip memory configuration. + * rom_ext_virtual and owner_virtual are address windows that provide a fixed translation + * address for whichever half of the flash contains the corresponding boot stage. + */ +MEMORY { + ctn(rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000 + ram_ret_aon(rwx) : ORIGIN = 0x30600000, LENGTH = 0x1000 + ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 + ram_mbox(rwx) : ORIGIN = 0x11000000, LENGTH = 0x1000 + rom0(rx) : ORIGIN = 0x00008000, LENGTH = 0x8000 + rom1(rx) : ORIGIN = 0x00020000, LENGTH = 0x10000 + rom_ext_virtual(rx) : ORIGIN = 0x90000000, LENGTH = 0x80000 + owner_virtual(rx) : ORIGIN = 0xa0000000, LENGTH = 0x80000 +} + +/** + * Exception frame at the top of main SRAM + */ +_exception_frame_size = 128; +_exception_frame_end = ORIGIN(ram_main) + LENGTH(ram_main); +_exception_frame_start = _exception_frame_end - _exception_frame_size; + + +/** + * Stack just below the exception frame. + */ +_stack_size = 16384 - _exception_frame_size; +_stack_end = _exception_frame_start; +_stack_start = _stack_end - _stack_size; + +/** + * Size of the `.static_critical` section at the bottom of the main SRAM (in + * bytes). + */ +_static_critical_size = 8168; + +/** + * `.chip_info` at the top of each ROM. + */ +_chip_info_size = 128; +_rom0_chip_info_end = ORIGIN(rom0) + LENGTH(rom0); +_rom0_chip_info_start = _rom0_chip_info_end - _chip_info_size; +_rom1_chip_info_end = ORIGIN(rom1) + LENGTH(rom1); +_rom1_chip_info_start = _rom1_chip_info_end - _chip_info_size; + +/** + * Size of the initial ePMP RX region at reset (in bytes). This region must be + * large enough to cover the .crt section. + * + * NOTE: This value must match the size of the RX region in + * hw/darjeeling_no_ibex/rtl/ibex_pmp_reset_pkg.sv. + */ +_epmp_reset_rx_size = 2048; diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg.c b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg.c new file mode 100644 index 00000000000..1798170f8f8 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg.c @@ -0,0 +1,10 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex + +#include "hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg.h" diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg.h b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg.h new file mode 100644 index 00000000000..fbc4191aa54 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg.h @@ -0,0 +1,90 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex + +#ifndef OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_DBG_H_ +#define OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_DBG_H_ + +/** + * @file + * @brief Top-specific Definitions + * + * This file contains preprocessor and type definitions for use within the + * device C/C++ codebase. + * + * These definitions are for information that depends on the top-specific chip + * configuration, which includes: + * - Device Memory Information (for Peripherals and Memory) + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Peripheral base address for dmi device on lc_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_BASE_ADDR 0x3000u + +/** + * Peripheral size for dmi device on lc_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_SIZE_BYTES 0x1000u + +/** + * Peripheral base address for soc device on mbx_jtag in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_BASE_ADDR 0x2200u + +/** + * Peripheral size for soc device on mbx_jtag in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for jtag device on soc_dbg_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_BASE_ADDR 0x2300u + +/** + * Peripheral size for jtag device on soc_dbg_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_SIZE_BYTES 0x20u + + + +// Header Extern Guard +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_DBG_H_ diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg_memory.h b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg_memory.h new file mode 100644 index 00000000000..a09cbd36ba0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_dbg_memory.h @@ -0,0 +1,84 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex + +#ifndef OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_DBG_MEMORY_H_ +#define OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_DBG_MEMORY_H_ + +/** + * @file + * @brief Assembler-only Top-Specific Definitions. + * + * This file contains preprocessor definitions for use within assembly code. + * + * These are not shared with C/C++ code because these are only allowed to be + * preprocessor definitions, no data or type declarations are allowed. The + * assembler is also stricter about literals (not allowing suffixes for + * signed/unsigned which are sensible to use for unsigned values in C/C++). + */ + +// Include guard for assembler +#ifdef __ASSEMBLER__ + + +/** + * Peripheral base address for dmi device on lc_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_BASE_ADDR 0x3000 + +/** + * Peripheral size for dmi device on lc_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_LC_CTRL_DMI_SIZE_BYTES 0x1000 +/** + * Peripheral base address for soc device on mbx_jtag in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_BASE_ADDR 0x2200 + +/** + * Peripheral size for soc device on mbx_jtag in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_MBX_JTAG_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for jtag device on soc_dbg_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_BASE_ADDR 0x2300 + +/** + * Peripheral size for jtag device on soc_dbg_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_DBG_SOC_DBG_CTRL_JTAG_SIZE_BYTES 0x20 + + +#endif // __ASSEMBLER__ + +#endif // OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_DBG_MEMORY_H_ diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx.c b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx.c new file mode 100644 index 00000000000..3280f552bfa --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx.c @@ -0,0 +1,10 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex + +#include "hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx.h" diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx.h b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx.h new file mode 100644 index 00000000000..0d9d98e9dd0 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx.h @@ -0,0 +1,234 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex + +#ifndef OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_MBX_H_ +#define OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_MBX_H_ + +/** + * @file + * @brief Top-specific Definitions + * + * This file contains preprocessor and type definitions for use within the + * device C/C++ codebase. + * + * These definitions are for information that depends on the top-specific chip + * configuration, which includes: + * - Device Memory Information (for Peripherals and Memory) + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Peripheral base address for soc device on mbx0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_BASE_ADDR 0x1465000u + +/** + * Peripheral size for soc device on mbx0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_BASE_ADDR 0x1465100u + +/** + * Peripheral size for soc device on mbx1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx2 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_BASE_ADDR 0x1465200u + +/** + * Peripheral size for soc device on mbx2 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx3 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_BASE_ADDR 0x1465300u + +/** + * Peripheral size for soc device on mbx3 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx4 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_BASE_ADDR 0x1465400u + +/** + * Peripheral size for soc device on mbx4 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx5 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_BASE_ADDR 0x1465500u + +/** + * Peripheral size for soc device on mbx5 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx6 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_BASE_ADDR 0x1496000u + +/** + * Peripheral size for soc device on mbx6 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx_pcie0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_BASE_ADDR 0x1460100u + +/** + * Peripheral size for soc device on mbx_pcie0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for soc device on mbx_pcie1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_BASE_ADDR 0x1460200u + +/** + * Peripheral size for soc device on mbx_pcie1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_SIZE_BYTES 0x20u + +/** + * Peripheral base address for racl_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_BASE_ADDR 0x1461F00u + +/** + * Peripheral size for racl_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_SIZE_BYTES 0x100u + +/** + * Peripheral base address for ac_range_check in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_BASE_ADDR 0x1464000u + +/** + * Peripheral size for ac_range_check in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_SIZE_BYTES 0x400u + + + +// Header Extern Guard +#ifdef __cplusplus +} // extern "C" +#endif + +#endif // OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_MBX_H_ diff --git a/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx_memory.h b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx_memory.h new file mode 100644 index 00000000000..acfc3f3fd56 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/sw/autogen/top_darjeeling_no_ibex_soc_mbx_memory.h @@ -0,0 +1,220 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// util/topgen.py -t hw/top_darjeeling_no_ibex/data/top_darjeeling_no_ibex.hjson +// -o hw/top_darjeeling_no_ibex + +#ifndef OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_MBX_MEMORY_H_ +#define OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_MBX_MEMORY_H_ + +/** + * @file + * @brief Assembler-only Top-Specific Definitions. + * + * This file contains preprocessor definitions for use within assembly code. + * + * These are not shared with C/C++ code because these are only allowed to be + * preprocessor definitions, no data or type declarations are allowed. The + * assembler is also stricter about literals (not allowing suffixes for + * signed/unsigned which are sensible to use for unsigned values in C/C++). + */ + +// Include guard for assembler +#ifdef __ASSEMBLER__ + + +/** + * Peripheral base address for soc device on mbx0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_BASE_ADDR 0x1465000 + +/** + * Peripheral size for soc device on mbx0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX0_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_BASE_ADDR 0x1465100 + +/** + * Peripheral size for soc device on mbx1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX1_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx2 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_BASE_ADDR 0x1465200 + +/** + * Peripheral size for soc device on mbx2 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX2_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx3 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_BASE_ADDR 0x1465300 + +/** + * Peripheral size for soc device on mbx3 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX3_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx4 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_BASE_ADDR 0x1465400 + +/** + * Peripheral size for soc device on mbx4 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX4_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx5 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_BASE_ADDR 0x1465500 + +/** + * Peripheral size for soc device on mbx5 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX5_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx6 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_BASE_ADDR 0x1496000 + +/** + * Peripheral size for soc device on mbx6 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX6_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx_pcie0 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_BASE_ADDR 0x1460100 + +/** + * Peripheral size for soc device on mbx_pcie0 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE0_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for soc device on mbx_pcie1 in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_BASE_ADDR 0x1460200 + +/** + * Peripheral size for soc device on mbx_pcie1 in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_MBX_PCIE1_SOC_SIZE_BYTES 0x20 +/** + * Peripheral base address for racl_ctrl in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_BASE_ADDR 0x1461F00 + +/** + * Peripheral size for racl_ctrl in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_RACL_CTRL_SIZE_BYTES 0x100 +/** + * Peripheral base address for ac_range_check in top darjeeling_no_ibex. + * + * This should be used with #mmio_region_from_addr to access the memory-mapped + * registers associated with the peripheral (usually via a DIF). + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_BASE_ADDR 0x1464000 + +/** + * Peripheral size for ac_range_check in top darjeeling_no_ibex. + * + * This is the size (in bytes) of the peripheral's reserved memory area. All + * memory-mapped registers associated with this peripheral should have an + * address between #TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_BASE_ADDR and + * `TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_BASE_ADDR + TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_SIZE_BYTES`. + */ +#define TOP_DARJEELING_NO_IBEX_SOC_MBX_AC_RANGE_CHECK_SIZE_BYTES 0x400 + + +#endif // __ASSEMBLER__ + +#endif // OPENTITAN_HW_TOP_DARJEELING_NO_IBEX_SW_AUTOGEN_TOP_DARJEELING_NO_IBEX_SOC_MBX_MEMORY_H_ diff --git a/hw/top_darjeeling_no_ibex/templates/chiplevel.sv.tpl b/hw/top_darjeeling_no_ibex/templates/chiplevel.sv.tpl new file mode 100644 index 00000000000..ebe112266a5 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/templates/chiplevel.sv.tpl @@ -0,0 +1,1514 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +${gencmd} +<% +import re +import topgen.lib as lib +from copy import deepcopy + +# Provide shortcuts for some commonly used variables +pinmux = top['pinmux'] +pinout = top['pinout'] + +num_mio_inputs = pinmux['io_counts']['muxed']['inouts'] + \ + pinmux['io_counts']['muxed']['inputs'] +num_mio_outputs = pinmux['io_counts']['muxed']['inouts'] + \ + pinmux['io_counts']['muxed']['outputs'] +num_mio_pads = pinmux['io_counts']['muxed']['pads'] + +num_dio_inputs = pinmux['io_counts']['dedicated']['inouts'] + \ + pinmux['io_counts']['dedicated']['inputs'] +num_dio_outputs = pinmux['io_counts']['dedicated']['inouts'] + \ + pinmux['io_counts']['dedicated']['outputs'] +num_dio_total = pinmux['io_counts']['dedicated']['inouts'] + \ + pinmux['io_counts']['dedicated']['inputs'] + \ + pinmux['io_counts']['dedicated']['outputs'] + +def get_dio_sig(pinmux: {}, pad: {}): + '''Get DIO signal associated with this pad or return None''' + for sig in pinmux["ios"]: + if sig["connection"] == "direct" and pad["name"] == sig["pad"]: + return sig + else: + return None + +# Modify the pad lists on the fly, based on target config +maxwidth = 0 +muxed_pads = [] +dedicated_pads = [] +k = 0 +for pad in pinout["pads"]: + if pad["connection"] == "muxed": + if pad["name"] not in target["pinout"]["remove_pads"]: + maxwidth = max(maxwidth, len(pad["name"])) + muxed_pads.append(pad) + else: + k = pad["idx"] + if pad["name"] not in target["pinout"]["remove_pads"]: + maxwidth = max(maxwidth, len(pad["name"])) + dedicated_pads.append(pad) + +for pad in target["pinout"]["add_pads"]: + # Since these additional pads have not been elaborated in the merge phase, + # we need to add their global index here. + amended_pad = deepcopy(pad) + amended_pad.update({"idx" : k}) + dedicated_pads.append(pad) + k += 1 +%>\ + +% if target["name"] != "asic": +module chip_${top["name"]}_${target["name"]} #( + // Path to a VMEM file containing the contents of the boot ROM, which will be + // baked into the FPGA bitstream. + parameter BootRomInitFile = "test_rom_fpga_${target["name"]}.32.vmem", + // Path to a VMEM file containing the contents of the emulated OTP, which will be + // baked into the FPGA bitstream. + parameter OtpMacroMemInitFile = "otp_img_fpga_${target["name"]}.vmem" +) ( +% else: +module chip_${top["name"]}_${target["name"]} #( + parameter bit SecRomCtrl0DisableScrambling = 1'b0, + parameter bit SecRomCtrl1DisableScrambling = 1'b0 +) ( +% endif +<% + removed_port_names = [] +%>\ + // Dedicated Pads +% for pad in dedicated_pads: +<% + sig = get_dio_sig(pinmux, pad) + if pad["name"] in target["pinout"]["remove_ports"]: + port_comment = "// Removed port: " + removed_port_names.append(pad["name"]) + else: + port_comment = "" + if sig is not None: + comment = "// Dedicated Pad for {}".format(sig["name"]) + else: + comment = "// Manual Pad" +%>\ + ${port_comment}${pad["port_type"]} ${pad["name"]}, ${comment} +% endfor + + // Muxed Pads +% for pad in muxed_pads: +<% + if pad["name"] in target["pinout"]["remove_ports"]: + port_comment = "// Removed port: " + removed_port_names.append(pad["name"]) + else: + port_comment = "" +%>\ + ${port_comment}${pad["port_type"]} ${pad["name"]}${" " if loop.last else ","} // MIO Pad ${pad["idx"]} +% endfor +); + + import top_${top["name"]}_pkg::*; + import prim_pad_wrapper_pkg::*; + +% if target["pinmux"]["special_signals"]: + //////////////////////////// + // Special Signal Indices // + //////////////////////////// + + % for entry in target["pinmux"]["special_signals"]: +<% param_name = (lib.Name.from_snake_case(entry["name"]) + + lib.Name(["pad", "idx"])).as_camel_case() +%>\ + localparam int ${param_name} = ${entry["idx"]}; + % endfor +% endif + + // DFT and Debug signal positions in the pinout. + localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{ + tck_idx: TckPadIdx, + tms_idx: TmsPadIdx, + trst_idx: TrstNPadIdx, + tdi_idx: TdiPadIdx, + tdo_idx: TdoPadIdx, + tap_strap0_idx: Tap0PadIdx, + tap_strap1_idx: Tap1PadIdx, + dft_strap0_idx: Dft0PadIdx, + dft_strap1_idx: Dft1PadIdx, + // TODO: check whether there is a better way to pass these USB-specific params + // The use of these indexes is gated behind a parameter, but to synthesize they + // need to exist even if the code-path is never used (pinmux.sv:UsbWkupModuleEn). + // Hence, set to zero. + usb_dp_idx: 0, + usb_dn_idx: 0, + usb_sense_idx: 0, + // Pad types for attribute WARL behavior + dio_pad_type: { +<% + pad_attr = [] + for sig in list(reversed(top["pinmux"]["ios"])): + if sig["connection"] != "muxed": + pad_attr.append((sig['name'], sig["attr"])) +%>\ +% for name, attr in pad_attr: + ${attr}${" " if loop.last else ","} // DIO ${name} +% endfor + }, + mio_pad_type: { +<% + pad_attr = [] + for pad in list(reversed(pinout["pads"])): + if pad["connection"] == "muxed": + pad_attr.append(pad["type"]) +%>\ +% for attr in pad_attr: + ${attr}${" " if loop.last else ","} // MIO Pad ${len(pad_attr) - loop.index - 1} +% endfor + }, + // Pad scan roles + dio_scan_role: { +<% + scan_roles = [] + for sig in list(reversed(top["pinmux"]["ios"])): + if sig["connection"] != "muxed": + if (len(sig['pad']) > 0) and (target["name"] != "cw305"): + scan_string = lib.Name.from_snake_case('dio_pad_' + sig['pad'] + '_scan_role') + scan_roles.append((f'scan_role_pkg::{scan_string.as_camel_case()}', sig['name'])) + else: + scan_roles.append(('NoScan', sig['name'])) +%>\ +% for scan_role, name in list(scan_roles): + ${scan_role}${"" if loop.last else ","} // DIO ${name} +% endfor + }, + mio_scan_role: { +<% + scan_roles = [] + for pad in list(reversed(pinout["pads"])): + if pad["connection"] == "muxed": + if target["name"] != "cw305": + scan_string = lib.Name.from_snake_case('mio_pad_' + pad['name'] + '_scan_role') + scan_roles.append(f'scan_role_pkg::{scan_string.as_camel_case()}') + else: + scan_roles.append('NoScan') +%>\ +% for scan_role in list(scan_roles): + ${scan_role}${"" if loop.last else ","} +% endfor + } + }; + + //////////////////////// + // Signal definitions // + //////////////////////// + + % if removed_port_names: + // Net definitions for removed ports + % endif + % for port in removed_port_names: + wire ${port}; + % endfor + + pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr; + pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_out; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in; + logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw; + logic [${len(dedicated_pads)}-1:0] dio_in_raw; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_out; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe; + logic [pinmux_reg_pkg::NDioPads-1:0] dio_in; + + logic unused_mio_in_raw; + logic unused_dio_in_raw; + assign unused_mio_in_raw = ^mio_in_raw; + assign unused_dio_in_raw = ^dio_in_raw; + + // Manual pads +% for pad in dedicated_pads: +<% + pad_prefix = pad["name"].lower() +%>\ +% if not get_dio_sig(pinmux, pad): + logic manual_in_${pad_prefix}, manual_out_${pad_prefix}, manual_oe_${pad_prefix}; +% endif +% endfor + +% for pad in dedicated_pads: +<% + pad_prefix = pad["name"].lower() +%>\ +% if not get_dio_sig(pinmux, pad): + pad_attr_t manual_attr_${pad_prefix}; +% endif +% endfor + +% if target["pinout"]["remove_pads"]: + ///////////////////////// + // Stubbed pad tie-off // + ///////////////////////// + + // Only signals going to non-custom pads need to be tied off. + logic [${len(pinout["pads"])-1}:0] unused_sig; +% for pad in pinout["pads"]: + % if pad["connection"] == 'muxed': + % if pad["name"] in target["pinout"]["remove_pads"]: + assign mio_in[${pad["idx"]}] = 1'b0; + assign mio_in_raw[${pad["idx"]}] = 1'b0; + assign unused_sig[${loop.index}] = mio_out[${pad["idx"]}] ^ mio_oe[${pad["idx"]}]; + % endif + % else: + % if pad["name"] in target["pinout"]["remove_pads"]: +<% + ## Only need to tie off if this is not a custom pad. + sig = get_dio_sig(pinmux, pad) + if sig is not None: + sig_index = lib.get_io_enum_literal(sig, 'dio') +%>\ + % if sig is not None: + assign dio_in[${lib.get_io_enum_literal(sig, 'dio')}] = 1'b0; + assign unused_sig[${loop.index}] = dio_out[${sig_index}] ^ dio_oe[${sig_index}]; + % endif + % endif + % endif +% endfor +%endif + + ////////////////////// + // Padring Instance // + ////////////////////// + + ast_pkg::ast_clks_t ast_base_clks; + +% if target["name"] == "asic": + // AST signals needed in padring + logic scan_rst_n; + prim_mubi_pkg::mubi4_t scanmode; +% endif + + padring #( + // Padring specific counts may differ from pinmux config due + // to custom, stubbed or added pads. + .NDioPads(${len(dedicated_pads)}), + .NMioPads(${len(muxed_pads)}), +% if target["name"] == "asic": + .PhysicalPads(1), + .NIoBanks(int'(IoBankCount)), + .DioScanRole ({ +% for pad in list(reversed(dedicated_pads)): + scan_role_pkg::${lib.Name.from_snake_case('dio_pad_' + pad["name"] + '_scan_role').as_camel_case()}${"" if loop.last else ","} +% endfor + }), + .MioScanRole ({ +% for pad in list(reversed(muxed_pads)): + scan_role_pkg::${lib.Name.from_snake_case('mio_pad_' + pad["name"] + '_scan_role').as_camel_case()}${"" if loop.last else ","} +% endfor + }), + .DioPadBank ({ +% for pad in list(reversed(dedicated_pads)): + ${lib.Name.from_snake_case('io_bank_' + pad["bank"]).as_camel_case()}${" " if loop.last else ","} // ${pad['name']} +% endfor + }), + .MioPadBank ({ +% for pad in list(reversed(muxed_pads)): + ${lib.Name.from_snake_case('io_bank_' + pad["bank"]).as_camel_case()}${" " if loop.last else ","} // ${pad['name']} +% endfor + }), +% endif +\ +\ + .DioPadType ({ +% for pad in list(reversed(dedicated_pads)): + ${pad["type"]}${" " if loop.last else ","} // ${pad['name']} +% endfor + }), + .MioPadType ({ +% for pad in list(reversed(muxed_pads)): + ${pad["type"]}${" " if loop.last else ","} // ${pad['name']} +% endfor + }) + ) u_padring ( + // This is only used for scan and DFT purposes +% if target["name"] == "asic": + .clk_scan_i ( ast_base_clks.clk_sys ), + .scanmode_i ( scanmode ), +% else: + .clk_scan_i ( 1'b0 ), + .scanmode_i ( prim_mubi_pkg::MuBi4False ), + % endif + .dio_in_raw_o ( dio_in_raw ), + // Chip IOs + .dio_pad_io ({ +% for pad in list(reversed(dedicated_pads)): + % if re.match(r"`INOUT_A?", pad["port_type"]): +`ifdef ANALOGSIM + '0, +`else + ${pad["name"]}${"" if loop.last else ","} +`endif + % else: + ${pad["name"]}${"" if loop.last else ","} + % endif +% endfor + }), + + .mio_pad_io ({ +% for pad in list(reversed(muxed_pads)): + % if re.match(r"`INOUT_A?", pad["port_type"]): +`ifdef ANALOGSIM + '0, +`else + ${pad["name"]}${"" if loop.last else ","} +`endif + % else: + ${pad["name"]}${"" if loop.last else ","} + % endif +% endfor + }), + + // Core-facing +% for port in ["in_o", "out_i", "oe_i", "attr_i"]: + .dio_${port} ({ + % for pad in list(reversed(dedicated_pads)): + <% + sig = get_dio_sig(pinmux, pad) + %>\ + % if sig is None: + manual_${port[:-2]}_${pad["name"].lower()}${"" if loop.last else ","} + % else: + dio_${port[:-2]}[${lib.get_io_enum_literal(sig, 'dio')}]${"" if loop.last else ","} + % endif + % endfor + }), +% endfor + +% for port in ["in_o", "out_i", "oe_i", "attr_i", "in_raw_o"]: +<% + sig_name = 'mio_' + port[:-2] + indices = list(reversed(list(pad['idx'] for pad in muxed_pads))) +%>\ + .mio_${port} (${lib.make_bit_concatenation(sig_name, indices, 6)})${"" if loop.last else ","} +% endfor + ); + + +################################################################### +## USB for CW305 ## +################################################################### +% if target["name"] == "cw305": + logic usb_dp_pullup_en; + logic usb_dn_pullup_en; + logic usb_rx_d; + logic usb_tx_d; + logic usb_tx_se0; + logic usb_tx_use_d_se0; + logic usb_rx_enable; + + // Connect the DP pad + assign dio_in[DioUsbdevUsbDp] = manual_in_usb_p; + assign manual_out_usb_p = dio_out[DioUsbdevUsbDp]; + assign manual_oe_usb_p = dio_oe[DioUsbdevUsbDp]; + assign manual_attr_usb_p = dio_attr[DioUsbdevUsbDp]; + + // Connect the DN pad + assign dio_in[DioUsbdevUsbDn] = manual_in_usb_n; + assign manual_out_usb_n = dio_out[DioUsbdevUsbDn]; + assign manual_oe_usb_n = dio_oe[DioUsbdevUsbDn]; + assign manual_attr_usb_n = dio_attr[DioUsbdevUsbDn]; + + // Connect DN pullup + assign manual_out_io_usb_dnpullup0 = usb_dn_pullup_en; + assign manual_oe_io_usb_dnpullup0 = 1'b1; + assign manual_attr_io_dnpullup0 = '0; + + // Connect DP pullup + assign manual_out_io_usb_dppullup0 = usb_dp_pullup_en; + assign manual_oe_io_usb_dppullup0 = 1'b1; + assign manual_attr_io_dppullup0 = '0; + + // Tie-off unused signals + assign usb_rx_d = 1'b0; + +% endif + +################################################################### +## AST For all targets ## +################################################################### + + ////////////////////////////////// + // AST - Common for all targets // + ////////////////////////////////// + + // pwrmgr interface + pwrmgr_pkg::pwr_ast_req_t base_ast_pwr; + pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr; + pwrmgr_pkg::pwr_boot_status_t pwrmgr_boot_status; + + // assorted ast status + ast_pkg::ast_pwst_t ast_pwst; + + // TLUL interface + tlul_pkg::tl_h2d_t base_ast_bus; + tlul_pkg::tl_d2h_t ast_base_bus; + + // synchronization clocks / rests + clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks; + rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets; + + // external clock + logic ext_clk; + + // monitored clock + logic sck_monitor; + + // debug policy bus + soc_dbg_ctrl_pkg::soc_dbg_policy_t soc_dbg_policy_bus; + + // observe interface + logic [7:0] otp_obs; + ast_pkg::ast_obs_ctrl_t obs_ctrl; + + // otp power sequence + otp_macro_pkg::otp_ast_req_t otp_macro_pwr_seq; + otp_macro_pkg::otp_ast_rsp_t otp_macro_pwr_seq_h; + + // OTP DFT configuration + otp_macro_pkg::otp_cfg_t otp_cfg; + assign otp_cfg = otp_macro_pkg::OTP_CFG_DEFAULT; + + // entropy source interface + logic es_rng_enable, es_rng_valid; + logic [ast_pkg::EntropyStreams-1:0] es_rng_bit; + + // alerts interface + ast_pkg::ast_alert_rsp_t ast_alert_rsp; + ast_pkg::ast_alert_req_t ast_alert_req; + assign ast_alert_rsp = '0; + + // clock bypass req/ack + prim_mubi_pkg::mubi4_t io_clk_byp_req; + prim_mubi_pkg::mubi4_t io_clk_byp_ack; + prim_mubi_pkg::mubi4_t all_clk_byp_req; + prim_mubi_pkg::mubi4_t all_clk_byp_ack; + prim_mubi_pkg::mubi4_t hi_speed_sel; + prim_mubi_pkg::mubi4_t div_step_down_req; + + // DFT connections + logic scan_en; + lc_ctrl_pkg::lc_tx_t lc_dft_en; + + // Jitter enable + prim_mubi_pkg::mubi4_t jen; + + // reset domain connections + import rstmgr_pkg::PowerDomains; + import rstmgr_pkg::DomainAonSel; + import rstmgr_pkg::Domain0Sel; + + // Memory configuration connections + ast_pkg::spm_rm_t ast_ram_1p_cfg; + ast_pkg::spm_rm_t ast_rf_cfg; + ast_pkg::spm_rm_t ast_rom_cfg; + ast_pkg::dpm_rm_t ast_ram_2p_fcfg; + ast_pkg::dpm_rm_t ast_ram_2p_lcfg; + + // conversion from ast structure to memory centric structures + prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg; + assign ram_1p_cfg = '{ + ram_cfg: '{ + test: ast_ram_1p_cfg.test, + cfg_en: ast_ram_1p_cfg.marg_en, + cfg: ast_ram_1p_cfg.marg + }, + rf_cfg: '{ + test: ast_rf_cfg.test, + cfg_en: ast_rf_cfg.marg_en, + cfg: ast_rf_cfg.marg + } + }; + + logic unused_usb_ram_2p_cfg; + assign unused_usb_ram_2p_cfg = ^{ast_ram_2p_fcfg.marg_en_a, + ast_ram_2p_fcfg.marg_a, + ast_ram_2p_fcfg.test_a, + ast_ram_2p_fcfg.marg_en_b, + ast_ram_2p_fcfg.marg_b, + ast_ram_2p_fcfg.test_b}; + + // this maps as follows: + // assign spi_ram_2p_cfg = {10'h000, ram_2p_cfg_i.a_ram_lcfg, ram_2p_cfg_i.b_ram_lcfg}; + prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg; + assign spi_ram_2p_cfg = '{ + a_ram_lcfg: '{ + test: ast_ram_2p_lcfg.test_a, + cfg_en: ast_ram_2p_lcfg.marg_en_a, + cfg: ast_ram_2p_lcfg.marg_a + }, + b_ram_lcfg: '{ + test: ast_ram_2p_lcfg.test_b, + cfg_en: ast_ram_2p_lcfg.marg_en_b, + cfg: ast_ram_2p_lcfg.marg_b + }, + default: '0 + }; + + prim_rom_pkg::rom_cfg_t rom_ctrl0_cfg; + prim_rom_pkg::rom_cfg_t rom_ctrl1_cfg; + + assign rom_ctrl0_cfg = '{ + test: ast_rom_cfg.test, + cfg_en: ast_rom_cfg.marg_en, + cfg: ast_rom_cfg.marg + }; + assign rom_ctrl1_cfg = '{ + test: ast_rom_cfg.test, + cfg_en: ast_rom_cfg.marg_en, + cfg: ast_rom_cfg.marg + }; + + ////////////////////////////////// + // AST - Custom for targets // + ////////////////////////////////// + +<% + ast = [m for m in top["module"] if m["name"] == "ast"] + assert(len(ast) == 1) + ast = ast[0] +%>\ + + assign ast_base_pwr.main_pok = ast_pwst.main_pok; + + logic [rstmgr_pkg::PowerDomains-1:0] por_n; + assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok}; + +% if target["name"] == "asic": + + // external clock comes in at a fixed position + assign ext_clk = mio_in_raw[MioPadMio11]; + + wire unused_t0, unused_t1; + assign unused_t0 = 1'b0; + assign unused_t1 = 1'b0; + + // AST does not use all clocks / resets forwarded to it + logic unused_slow_clk_en; + assign unused_slow_clk_en = base_ast_pwr.slow_clk_en; + + logic unused_pwr_clamp; + assign unused_pwr_clamp = base_ast_pwr.pwr_clamp; + +% else: + // TODO: Hook this up when FPGA pads are updated + assign ext_clk = '0; + assign pad2ast = '0; + + logic clk_main, clk_usb_48mhz, clk_aon, rst_n, srst_n; + clkgen_xil7series # ( + .AddClkBuf(0) + ) clkgen ( + .clk_i(manual_in_io_clk), + .rst_ni(manual_in_por_n), + .srst_ni(srst_n), + .clk_main_o(clk_main), + .clk_48MHz_o(clk_usb_48mhz), + .clk_aon_o(clk_aon), + .rst_no(rst_n) + ); + + logic [31:0] fpga_info; + usr_access_xil7series u_info ( + .info_o(fpga_info) + ); + + ast_pkg::clks_osc_byp_t clks_osc_byp; + assign clks_osc_byp = '{ + usb: clk_usb_48mhz, + sys: clk_main, + io: clk_main, + aon: clk_aon + }; + +% endif + + prim_mubi_pkg::mubi4_t ast_init_done; + + ast #( + .AdcChannels(ast_pkg::AdcChannels), + .AdcDataWidth(ast_pkg::AdcDataWidth), + .UsbCalibWidth(ast_pkg::UsbCalibWidth), + .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth), + .Pad2AstInWidth(ast_pkg::Pad2AstInWidth) + ) u_ast ( +% if target["name"] == "asic": + // external POR + .por_ni ( manual_in_por_n ), + + // USB IO Pull-up Calibration Setting + .usb_io_pu_cal_o ( ), + + // adc + .adc_a0_ai ( '0 ), + .adc_a1_ai ( '0 ), + + // Direct short to PAD + .ast2pad_t0_ao ( unused_t0 ), + .ast2pad_t1_ao ( unused_t1 ), +% else: + // external POR + .por_ni ( rst_n ), + + // USB IO Pull-up Calibration Setting + .usb_io_pu_cal_o ( ), + + // clocks' oschillator bypass for FPGA + .clk_osc_byp_i ( clks_osc_byp ), + + // adc + .adc_a0_ai ( '0 ), + .adc_a1_ai ( '0 ), + + // Direct short to PAD + .ast2pad_t0_ao ( ), + .ast2pad_t1_ao ( ), + +% endif + // clocks and resets supplied for detection + .sns_clks_i ( clkmgr_aon_clocks ), + .sns_rsts_i ( rstmgr_aon_resets ), + .sns_spi_ext_clk_i ( sck_monitor ), + // tlul + .tl_i ( base_ast_bus ), + .tl_o ( ast_base_bus ), + // init done indication + .ast_init_done_o ( ast_init_done ), + // buffered clocks & resets + % for port, clk in ast["clock_connections"].items(): + .${port} (${clk}), + % endfor + % for port, reset in ast["reset_connections"].items(): + .${port} (${lib.get_reset_path(top, reset)}), + % endfor + .clk_ast_ext_i ( ext_clk ), + + // pok test for FPGA + .vcc_supp_i ( 1'b1 ), + .vcaon_supp_i ( 1'b1 ), + .vcmain_supp_i ( 1'b1 ), + .vioa_supp_i ( 1'b1 ), + .viob_supp_i ( 1'b1 ), + // pok + .ast_pwst_o ( ast_pwst ), + .ast_pwst_h_o ( ), + // main regulator + .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ), + .main_pd_ni ( base_ast_pwr.main_pd_n ), + // pdm control (flash)/otp + .flash_power_down_h_o ( ), + .flash_power_ready_h_o ( ), + .otp_power_seq_i ( otp_macro_pwr_seq ), + .otp_power_seq_h_o ( otp_macro_pwr_seq_h ), + // system source clock + .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ), + // need to add function in clkmgr + .clk_src_sys_jen_i ( jen ), + .clk_src_sys_o ( ast_base_clks.clk_sys ), + .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ), + // aon source clock + .clk_src_aon_o ( ast_base_clks.clk_aon ), + .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ), + // io source clock + .clk_src_io_en_i ( base_ast_pwr.io_clk_en ), + .clk_src_io_o ( ast_base_clks.clk_io ), + .clk_src_io_val_o ( ast_base_pwr.io_clk_val ), + .clk_src_io_48m_o ( div_step_down_req ), + // usb source clock + .usb_ref_pulse_i ( '0 ), + .usb_ref_val_i ( '0 ), + .clk_src_usb_en_i ( '0 ), + .clk_src_usb_o ( ), + .clk_src_usb_val_o ( ), + // adc + .adc_pd_i ( '0 ), + .adc_chnsel_i ( '0 ), + .adc_d_o ( ), + .adc_d_val_o ( ), + // rng + .rng_en_i ( es_rng_enable ), + .rng_fips_i ( es_rng_fips ), + .rng_val_o ( es_rng_valid ), + .rng_b_o ( es_rng_bit ), + // alerts + .alert_rsp_i ( ast_alert_rsp ), + .alert_req_o ( ast_alert_req ), + // dft + .lc_dft_en_i ( lc_dft_en ), + .fla_obs_i ( '0 ), + .usb_obs_i ( '0 ), + .otp_obs_i ( otp_obs ), + .otm_obs_i ( '0 ), + .obs_ctrl_o ( obs_ctrl ), + // pinmux related + .padmux2ast_i ( '0 ), + .ast2padmux_o ( ), + .ext_freq_is_96m_i ( hi_speed_sel ), + .all_clk_byp_req_i ( all_clk_byp_req ), + .all_clk_byp_ack_o ( all_clk_byp_ack ), + .io_clk_byp_req_i ( io_clk_byp_req ), + .io_clk_byp_ack_o ( io_clk_byp_ack ), + .flash_bist_en_o ( ), + // Memory configuration connections + .dpram_rmf_o ( ast_ram_2p_fcfg ), + .dpram_rml_o ( ast_ram_2p_lcfg ), + .spram_rm_o ( ast_ram_1p_cfg ), + .sprgf_rm_o ( ast_rf_cfg ), + .sprom_rm_o ( ast_rom_cfg ), + // scan + .dft_scan_md_o ( scanmode ), + .scan_shift_en_o ( scan_en ), + .scan_reset_no ( scan_rst_n ) + ); + + ////////////////// + // TAP Instance // + ////////////////// + + tlul_pkg::tl_h2d_t dmi_h2d; + tlul_pkg::tl_d2h_t dmi_d2h; + jtag_pkg::jtag_req_t jtag_req; + jtag_pkg::jtag_rsp_t jtag_rsp; + + assign jtag_req.tck = manual_in_jtag_tck; + assign jtag_req.tms = manual_in_jtag_tms; + assign jtag_req.trst_n = manual_in_jtag_trst_n; + assign jtag_req.tdi = manual_in_jtag_tdi; + + assign manual_out_jtag_tck = '0; + assign manual_out_jtag_tms = '0; + assign manual_out_jtag_trst_n = '0; + assign manual_out_jtag_tdi = '0; + assign manual_oe_jtag_tck = '0; + assign manual_oe_jtag_tms = '0; + assign manual_oe_jtag_trst_n = '0; + assign manual_oe_jtag_tdi = '0; + assign manual_attr_jtag_tck = '0; + assign manual_attr_jtag_tms = '0; + assign manual_attr_jtag_trst_n = '0; + assign manual_attr_jtag_tdi = '0; + + assign manual_out_jtag_tdo = jtag_rsp.tdo; + assign manual_oe_jtag_tdo = jtag_rsp.tdo_oe; + assign manual_attr_jtag_tdo = '0; + + logic unused_manual_jtag_sigs; + assign unused_manual_jtag_sigs = ^{ + manual_in_jtag_tdo + }; + + tlul_jtag_dtm #( + .IdcodeValue(jtag_id_pkg::LC_DM_COMBINED_JTAG_IDCODE), + // Notes: + // - one RV_DM instance uses 9bits + // - our crossbar tooling expects individual IPs to be spaced apart by 12bits at the moment + // - the DMI address shifted through jtag is a word address and hence 2bits smaller than this + // - setting this to 18bits effectively gives us 2^6 = 64 addressable 12bit ranges + .NumDmiByteAbits(18) + ) u_tlul_jtag_dtm ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]), + .jtag_i (jtag_req), + .jtag_o (jtag_rsp), + .scan_rst_ni(scan_rst_n), + .scanmode_i (scanmode), + .tl_h2d_o (dmi_h2d), + .tl_d2h_i (dmi_d2h) + ); + + // TODO: Resolve this and wire it up. + tlul_pkg::tl_h2d_t ctn_misc_tl_h2d_i; + assign ctn_misc_tl_h2d_i = tlul_pkg::TL_H2D_DEFAULT; + tlul_pkg::tl_d2h_t ctn_misc_tl_d2h_o; + + // TODO: Over/ride/ all access range checks for now. + prim_mubi_pkg::mubi8_t ac_range_check_overwrite_i; + assign ac_range_check_overwrite_i = prim_mubi_pkg::MuBi8True; + + // TODO: External RACL error input. + top_racl_pkg::racl_error_log_t ext_racl_error; + assign ext_racl_error = '0; + + //////////////// + // CTN M-to-1 // + //////////////// + + tlul_pkg::tl_h2d_t ctn_tl_h2d[2]; + tlul_pkg::tl_d2h_t ctn_tl_d2h[2]; + //TODO: Resolve this and wire it up. + assign ctn_tl_h2d[1] = tlul_pkg::TL_H2D_DEFAULT; + + tlul_pkg::tl_h2d_t ctn_sm1_to_s1n_tl_h2d; + tlul_pkg::tl_d2h_t ctn_sm1_to_s1n_tl_d2h; + + tlul_socket_m1 #( + .M (2), + .HReqPass ({2{1'b1}}), + .HRspPass ({2{1'b1}}), + .HReqDepth ({2{4'd0}}), + .HRspDepth ({2{4'd0}}), + .DReqPass (1'b1), + .DRspPass (1'b1), + .DReqDepth (4'd0), + .DRspDepth (4'd0) + ) u_ctn_sm1 ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_tl_h2d), + .tl_h_o (ctn_tl_d2h), + .tl_d_o (ctn_sm1_to_s1n_tl_h2d), + .tl_d_i (ctn_sm1_to_s1n_tl_d2h) + ); + + //////////////////////////////////////////// + // CTN Address decoding and SRAM Instance // + //////////////////////////////////////////// + + localparam int CtnSramDw = top_pkg::TL_DW + tlul_pkg::DataIntgWidth; + + tlul_pkg::tl_h2d_t ctn_s1n_tl_h2d[1]; + tlul_pkg::tl_d2h_t ctn_s1n_tl_d2h[1]; + + // Steering signal for address decoding. + logic [0:0] ctn_dev_sel_s1n; + + logic sram_req, sram_we, sram_rvalid; + logic [top_pkg::CtnSramAw-1:0] sram_addr; + logic [CtnSramDw-1:0] sram_wdata, sram_wmask, sram_rdata; + + // Steering of requests. + // Addresses leaving the RoT through the CTN port are mapped to an internal 1G address space of + // 0x4000_0000 - 0x8000_0000. However, the CTN RAM only covers a 1MB region inside that space, + // and hence additional decoding and steering logic is needed here. + // TODO: this should in the future be replaced by an automatically generated crossbar. + always_comb begin + // Default steering to generate error response if address is not within the range + ctn_dev_sel_s1n = 1'b1; + // Steering to CTN SRAM. + if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_RAM_CTN_SIZE_BYTES-1)) == + (TOP_DARJEELING_RAM_CTN_BASE_ADDR - TOP_DARJEELING_CTN_BASE_ADDR)) begin + ctn_dev_sel_s1n = 1'd0; + end + end + + tlul_socket_1n #( + .HReqDepth (4'h0), + .HRspDepth (4'h0), + .DReqDepth (8'h0), + .DRspDepth (8'h0), + .N (1) + ) u_ctn_s1n ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_h_i (ctn_sm1_to_s1n_tl_h2d), + .tl_h_o (ctn_sm1_to_s1n_tl_d2h), + .tl_d_o (ctn_s1n_tl_h2d), + .tl_d_i (ctn_s1n_tl_d2h), + .dev_select_i (ctn_dev_sel_s1n) + ); + + tlul_adapter_sram #( + .SramAw(top_pkg::CtnSramAw), + .SramDw(CtnSramDw - tlul_pkg::DataIntgWidth), + .Outstanding(2), + .ByteAccess(1), + .CmdIntgCheck(1), + .EnableRspIntgGen(1), + .EnableDataIntgGen(0), + .EnableDataIntgPt(1), + .SecFifoPtr (0) + ) u_tlul_adapter_sram_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .tl_i (ctn_s1n_tl_h2d[0]), + .tl_o (ctn_s1n_tl_d2h[0]), + // Ifetch is explicitly allowed + .en_ifetch_i (prim_mubi_pkg::MuBi4True), + .req_o (sram_req), + .req_type_o (), + // SRAM can always accept a request. + .gnt_i (1'b1), + .we_o (sram_we), + .addr_o (sram_addr), + .wdata_o (sram_wdata), + .wmask_o (sram_wmask), + .intg_error_o(), + .user_rsvd_o (), + .rdata_i (sram_rdata), + .rvalid_i (sram_rvalid), + .rerror_i ('0), + .compound_txn_in_progress_o(), + .readback_en_i(prim_mubi_pkg::MuBi4False), + .readback_error_o(), + .wr_collision_i(1'b0), + .write_pending_i(1'b0) + ); + + prim_ram_1p_adv #( + .Depth(top_pkg::CtnSramDepth), + .Width(CtnSramDw), + .DataBitsPerMask(CtnSramDw), + .EnableECC(0), + .EnableParity(0), + .EnableInputPipeline(1), + .EnableOutputPipeline(1) + ) u_prim_ram_1p_adv_ctn ( + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), + .req_i (sram_req), + .write_i (sram_we), + .addr_i (sram_addr), + .wdata_i (sram_wdata), + .wmask_i (sram_wmask), + .rdata_o (sram_rdata), + .rvalid_o (sram_rvalid), + // No error detection is enabled inside SRAM. + // Bus ECC is checked at the consumer side. + .rerror_o (), + .cfg_i (ram_1p_cfg), + .cfg_rsp_o(), + .alert_o() + ); + +################################################################### +## ASIC ## +################################################################### + +% if target["name"] == "asic": + + ////////////////////////////////// + // Manual Pad / Signal Tie-offs // + ////////////////////////////////// + + assign manual_out_por_n = 1'b0; + assign manual_oe_por_n = 1'b0; + + assign manual_out_otp_ext_volt = 1'b0; + assign manual_oe_otp_ext_volt = 1'b0; + + // These pad attributes currently tied off permanently (these are all input-only pads). + assign manual_attr_por_n = '0; + assign manual_attr_otp_ext_volt = '0; + + logic unused_manual_sigs; + assign unused_manual_sigs = ^{ + manual_in_otp_ext_volt + }; + + soc_proxy_pkg::soc_alert_req_t [soc_proxy_pkg::NumFatalExternalAlerts-1:0] soc_fatal_alert_req; + soc_proxy_pkg::soc_alert_req_t [soc_proxy_pkg::NumRecovExternalAlerts-1:0] soc_recov_alert_req; + assign soc_fatal_alert_req = + {soc_proxy_pkg::NumFatalExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}}; + assign soc_recov_alert_req = + {soc_proxy_pkg::NumRecovExternalAlerts{soc_proxy_pkg::SOC_ALERT_REQ_DEFAULT}}; + + // The power manager waits until the external reset request is removed by the SoC before + // proceeding to boot after an internal reset request. DV may also drive this signal briefly and + // asynchronously to request a reset on behalf of the simulated SoC. + // + // Note that since the signal is filtered inside the SoC proxy it must be of at least 5 + // AON clock periods in duration. + logic soc_rst_req_async; + assign soc_rst_req_async = 1'b0; + + ////////////////////// + // Top-level design // + ////////////////////// + top_${top["name"]} #( + .PinmuxAonTargetCfg(PinmuxTargetCfg), + .SecAesAllowForcingMasks(1'b1), + .SecRomCtrl0DisableScrambling(SecRomCtrl0DisableScrambling), + .SecRomCtrl1DisableScrambling(SecRomCtrl1DisableScrambling) + ) top_${top["name"]} ( + // ast connections + .por_n_i ( por_n ), + .clk_main_i ( ast_base_clks.clk_sys ), + .clk_io_i ( ast_base_clks.clk_io ), + .clk_aon_i ( ast_base_clks.clk_aon ), + .clks_ast_o ( clkmgr_aon_clocks ), + .clk_main_jitter_en_o ( jen ), + .rsts_ast_o ( rstmgr_aon_resets ), + .integrator_id_i ( '0 ), + .sck_monitor_o ( sck_monitor ), + .pwrmgr_ast_req_o ( base_ast_pwr ), + .pwrmgr_ast_rsp_i ( ast_base_pwr ), + .ast_tl_req_o ( base_ast_bus ), + .ast_tl_rsp_i ( ast_base_bus ), + .obs_ctrl_i ( obs_ctrl ), + .otp_macro_pwr_seq_o ( otp_macro_pwr_seq ), + .otp_macro_pwr_seq_h_i ( otp_macro_pwr_seq_h ), + .otp_obs_o ( otp_obs ), + .otp_cfg_i ( otp_cfg ), + .otp_cfg_rsp_o ( otp_cfg_rsp ), + .ctn_tl_h2d_o ( ctn_tl_h2d[0] ), + .ctn_tl_d2h_i ( ctn_tl_d2h[0] ), + .ac_range_check_overwrite_i ( ac_range_check_overwrite_i ), + .racl_error_i ( ext_racl_error ), + .soc_gpi_async_o ( ), + .soc_gpo_async_i ( '0 ), + .soc_dbg_policy_bus_o ( soc_dbg_policy_bus ), + .debug_halt_cpu_boot_i ( '0 ), + .dma_sys_req_o ( ), + .dma_sys_rsp_i ( '0 ), + .mbx_tl_req_i ( tlul_pkg::TL_H2D_DEFAULT ), + .mbx_tl_rsp_o ( ), + .pwrmgr_boot_status_o ( pwrmgr_boot_status ), + .ctn_misc_tl_h2d_i ( ctn_misc_tl_h2d_i ), + .ctn_misc_tl_d2h_o ( ctn_misc_tl_d2h_o ), + .soc_fatal_alert_req_i ( soc_fatal_alert_req ), + .soc_fatal_alert_rsp_o ( ), + .soc_recov_alert_req_i ( soc_recov_alert_req ), + .soc_recov_alert_rsp_o ( ), + .soc_intr_async_i ( '0 ), + .soc_wkup_async_i ( 1'b0 ), + .soc_rst_req_async_i ( soc_rst_req_async ), + .soc_lsio_trigger_i ( '0 ), + .mbx0_doe_intr_en_o ( ), + .mbx0_doe_intr_o ( ), + .mbx0_doe_intr_support_o ( ), + .mbx0_doe_async_msg_support_o ( ), + .mbx1_doe_intr_en_o ( ), + .mbx1_doe_intr_o ( ), + .mbx1_doe_intr_support_o ( ), + .mbx1_doe_async_msg_support_o ( ), + .mbx2_doe_intr_en_o ( ), + .mbx2_doe_intr_o ( ), + .mbx2_doe_intr_support_o ( ), + .mbx2_doe_async_msg_support_o ( ), + .mbx3_doe_intr_en_o ( ), + .mbx3_doe_intr_o ( ), + .mbx3_doe_intr_support_o ( ), + .mbx3_doe_async_msg_support_o ( ), + .mbx4_doe_intr_en_o ( ), + .mbx4_doe_intr_o ( ), + .mbx4_doe_intr_support_o ( ), + .mbx4_doe_async_msg_support_o ( ), + .mbx5_doe_intr_en_o ( ), + .mbx5_doe_intr_o ( ), + .mbx5_doe_intr_support_o ( ), + .mbx5_doe_async_msg_support_o ( ), + .mbx6_doe_intr_en_o ( ), + .mbx6_doe_intr_o ( ), + .mbx6_doe_intr_support_o ( ), + .mbx6_doe_async_msg_support_o ( ), + .mbx_jtag_doe_intr_en_o ( ), + .mbx_jtag_doe_intr_o ( ), + .mbx_jtag_doe_intr_support_o ( ), + .mbx_jtag_doe_async_msg_support_o ( ), + .mbx_pcie0_doe_intr_en_o ( ), + .mbx_pcie0_doe_intr_o ( ), + .mbx_pcie0_doe_intr_support_o ( ), + .mbx_pcie0_doe_async_msg_support_o ( ), + .mbx_pcie1_doe_intr_en_o ( ), + .mbx_pcie1_doe_intr_o ( ), + .mbx_pcie1_doe_intr_support_o ( ), + .mbx_pcie1_doe_async_msg_support_o ( ), + .es_rng_enable_o ( es_rng_enable ), + .es_rng_valid_i ( es_rng_valid ), + .es_rng_bit_i ( es_rng_bit ), + .es_rng_fips_o ( es_rng_fips ), + .io_clk_byp_req_o ( io_clk_byp_req ), + .io_clk_byp_ack_i ( io_clk_byp_ack ), + .all_clk_byp_req_o ( all_clk_byp_req ), + .all_clk_byp_ack_i ( all_clk_byp_ack ), + .hi_speed_sel_o ( hi_speed_sel ), + .div_step_down_req_i ( div_step_down_req ), + .calib_rdy_i ( ast_init_done ), + + // OTP external voltage + .otp_ext_voltage_h_io ( OTP_EXT_VOLT ), + + // DMI TL-UL + .dbg_tl_req_i ( dmi_h2d ), + .dbg_tl_rsp_o ( dmi_d2h ), + // Quasi-static word address for next_dm register value. + .rv_dm_next_dm_addr_i ( '0 ), + // Multiplexed I/O + .mio_in_i ( mio_in ), + .mio_out_o ( mio_out ), + .mio_oe_o ( mio_oe ), + + // Dedicated I/O + .dio_in_i ( dio_in ), + .dio_out_o ( dio_out ), + .dio_oe_o ( dio_oe ), + + // Pad attributes + .mio_attr_o ( mio_attr ), + .dio_attr_o ( dio_attr ), + + // Memory attributes + .rom_ctrl0_cfg_i ( rom_ctrl0_cfg ), + .rom_ctrl1_cfg_i ( rom_ctrl1_cfg ), + .i2c_ram_1p_cfg_i ( ram_1p_cfg ), + .i2c_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_ret_aon_ram_1p_cfg_i ( ram_1p_cfg ), + .sram_ctrl_ret_aon_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_main_ram_1p_cfg_i ( ram_1p_cfg ), + .sram_ctrl_main_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_mbox_ram_1p_cfg_i ( ram_1p_cfg ), + .sram_ctrl_mbox_ram_1p_cfg_rsp_o ( ), + .otbn_imem_ram_1p_cfg_i ( ram_1p_cfg ), + .otbn_imem_ram_1p_cfg_rsp_o ( ), + .otbn_dmem_ram_1p_cfg_i ( ram_1p_cfg ), + .otbn_dmem_ram_1p_cfg_rsp_o ( ), + .rv_core_ibex_icache_tag_ram_1p_cfg_i ( ram_1p_cfg ), + .rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o ( ), + .rv_core_ibex_icache_data_ram_1p_cfg_i ( ram_1p_cfg ), + .rv_core_ibex_icache_data_ram_1p_cfg_rsp_o ( ), + .spi_device_ram_2p_cfg_sys2spi_i ( spi_ram_2p_cfg ), + .spi_device_ram_2p_cfg_spi2sys_i ( spi_ram_2p_cfg ), + .spi_device_ram_2p_cfg_rsp_sys2spi_o ( ), + .spi_device_ram_2p_cfg_rsp_spi2sys_o ( ), + + // DFT signals + .ast_lc_dft_en_o ( lc_dft_en ), + .ast_lc_hw_debug_en_o ( ), + .scan_rst_ni ( scan_rst_n ), + .scan_en_i ( scan_en ), + .scanmode_i ( scanmode ), + + // FPGA build info + .fpga_info_i ( '0 ) + ); +% endif + +logic unused_signals; +assign unused_signals = ^{pwrmgr_boot_status.clk_status, + pwrmgr_boot_status.cpu_fetch_en, + pwrmgr_boot_status.lc_done, + pwrmgr_boot_status.otp_done, + pwrmgr_boot_status.rom_ctrl_status, + pwrmgr_boot_status.strap_sampled}; + +################################################################### +## FPGA shared ## +################################################################### +% if target["name"] in ["cw310", "cw305"]: + ////////////////// + // PLL for FPGA // + ////////////////// + + assign manual_attr_io_clk = '0; + assign manual_out_io_clk = 1'b0; + assign manual_oe_io_clk = 1'b0; + assign manual_attr_por_n = '0; + assign manual_out_por_n = 1'b0; + assign manual_oe_por_n = 1'b0; + assign manual_attr_por_button_n = '0; + assign manual_out_por_button_n = 1'b0; + assign manual_oe_por_button_n = 1'b0; + + % if target["name"] in ["cw305", "cw310"]: + assign srst_n = manual_in_por_button_n; + % endif + + % if target["name"] == "cw305": + // TODO: follow-up later and hardwire all ast connects that do not + // exist for this target + assign otp_obs_o = '0; + % endif + // Extend the internal reset request from the power manager. + // + // TODO: To model the SoC within FPGA this logic is insufficient; its presence here + // is to avoid a design that locks up awaiting the deassertion of the signal + // `soc_rst_req_async_i` in response to an internal reset request. + logic internal_request_d, internal_request_q; + logic external_reset, count_up; + logic [3:0] count; + always_ff @(posedge ast_base_clks.clk_aon or negedge por_n[0]) begin + if (!por_n[0]) begin + external_reset <= 1'b0; + internal_request_q <= 1'b0; + count_up <= '0; + count <= '0; + end else begin + internal_request_q <= internal_request_d; + if (!internal_request_q && internal_request_d) begin + count_up <= 1'b1; + external_reset <= 1; + end else if (count == 'd8) begin + count_up <= 0; + external_reset <= 0; + count <= '0; + end else if (count_up) begin + count <= count + 1; + end + end + end + + ////////////////////// + // Top-level design // + ////////////////////// + + // the rst_ni pin only goes to AST + // the rest of the logic generates reset based on the 'pok' signal. + // for verilator purposes, make these two the same. + prim_mubi_pkg::mubi4_t lc_clk_bypass; // TODO Tim + +// TODO: align this with ASIC version to minimize the duplication. +// Also need to add AST simulation and FPGA emulation models for things like entropy source - +// otherwise Verilator / FPGA will hang. + top_${top["name"]} #( +% if target["name"] == "cw310": + .SecAesMasking(1'b1), + .SecAesSBoxImpl(aes_pkg::SBoxImplDom), + .SecAesStartTriggerDelay(320), + .SecAesAllowForcingMasks(1'b1), + .KmacEnMasking(0), + .KmacSwKeyMasked(1), + .SecKmacCmdDelay(320), + .SecKmacIdleAcceptSwMsg(1'b1), +% if top["name"] == "earlgrey": + .KeymgrKmacEnMasking(0), +% else: + .KeymgrDpeKmacEnMasking(0), +% endif + .CsrngSBoxImpl(aes_pkg::SBoxImplLut), + .OtbnRegFile(otbn_pkg::RegFileFPGA), + .SecOtbnMuteUrnd(1'b1), + .SecOtbnSkipUrndReseedAtStart(1'b1), + .OtpMacroMemInitFile(OtpMacroMemInitFile), + .RvCoreIbexPipeLine(1), + .SramCtrlRetAonInstrExec(0), + % if lib.num_rom_ctrl(top["module"]) > 1: + // TODO(opentitan-integrated/issues/251): + // Enable hashing below once the build infrastructure can + // load scrambled images on FPGA platforms. The DV can + // already partially handle it by initializing the 2nd ROM + // with random data via the backdoor loading interface - it + // can't load "real" SW images yet since that requires + // additional build infrastructure. + .SecRomCtrl1DisableScrambling(1), + % endif +% elif target["name"] == "cw305": + .RvCoreIbexPipeLine(0), + .SecAesMasking(1'b1), + .SecAesSBoxImpl(aes_pkg::SBoxImplDom), + .SecAesStartTriggerDelay(320), + .SecAesAllowForcingMasks(1'b1), + .SecAesSkipPRNGReseeding(1'b1), + .UsbdevStub(1'b1), +% else: + .SecAesMasking(1'b0), + .SecAesSBoxImpl(aes_pkg::SBoxImplLut), + .KmacEnMasking(1'b0), +% if top["name"] == "earlgrey": + .KeymgrKmacEnMasking(0), +% else: + .KeymgrDpeKmacEnMasking(0), +% endif + .SecAesStartTriggerDelay(0), + .SecAesAllowForcingMasks(1'b0), + .SecAesSkipPRNGReseeding(1'b0), + .SramCtrlRetAonInstrExec(0), + .EntropySrcStub(1'b1), + .CsrngSBoxImpl(aes_pkg::SBoxImplLut), + .OtbnRegFile(otbn_pkg::RegFileFPGA), + .OtbnStub(1'b1), + .OtpMacroMemInitFile(OtpMacroMemInitFile), + .RvCoreIbexPipeLine(1), +% endif + .RomCtrl0BootRomInitFile(BootRomInitFile), + .RvCoreIbexRegFile(ibex_pkg::RegFileFPGA), + .RvCoreIbexSecureIbex(0), + .SramCtrlMainInstrExec(1), + .PinmuxAonTargetCfg(PinmuxTargetCfg) + ) top_${top["name"]} ( + .por_n_i ( por_n ), + .clk_main_i ( ast_base_clks.clk_sys ), + .clk_io_i ( ast_base_clks.clk_io ), + .clk_aon_i ( ast_base_clks.clk_aon ), + .clks_ast_o ( clkmgr_aon_clocks ), + .clk_main_jitter_en_o ( jen ), + .rsts_ast_o ( rstmgr_aon_resets ), + .integrator_id_i ( '0 ), + .sck_monitor_o ( sck_monitor ), + .pwrmgr_ast_req_o ( base_ast_pwr ), + .pwrmgr_ast_rsp_i ( ast_base_pwr ), + .obs_ctrl_i ( obs_ctrl ), + .io_clk_byp_req_o ( io_clk_byp_req ), + .io_clk_byp_ack_i ( io_clk_byp_ack ), + .all_clk_byp_req_o ( all_clk_byp_req ), + .all_clk_byp_ack_i ( all_clk_byp_ack ), + .hi_speed_sel_o ( hi_speed_sel ), + .div_step_down_req_i ( div_step_down_req ), + .fpga_info_i ( fpga_info ), +% if target["name"] != "cw305": + .ast_tl_req_o ( base_ast_bus ), + .ast_tl_rsp_i ( ast_base_bus ), + .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ), + .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ), + .otp_obs_o ( otp_obs ), + .otp_cfg_i ( otp_cfg ), + .otp_cfg_rsp_o ( otp_cfg_rsp ), + .ctn_tl_h2d_o ( ctn_tl_h2d[0] ), + .ctn_tl_d2h_i ( ctn_tl_d2h[0] ), + .ac_range_check_overwrite_i ( ac_range_check_overwrite_i ), + .racl_error_i ( ext_racl_error ), + .soc_gpi_async_o ( ), + .soc_gpo_async_i ( '0 ), + .soc_dbg_policy_bus_o ( soc_dbg_policy_bus ), + .debug_halt_cpu_boot_i ( '0 ), + .dma_sys_req_o ( ), + .dma_sys_rsp_i ( '0 ), + .soc_rst_req_async_i ( external_reset ), + .soc_lsio_trigger_i ( '0 ), + .es_rng_enable_o ( es_rng_enable ), + .es_rng_valid_i ( es_rng_valid ), + .es_rng_bit_i ( es_rng_bit ), + .calib_rdy_i ( ast_init_done ), +% endif + + // DMI TL-UL + .dbg_tl_req_i ( dmi_h2d ), + .dbg_tl_rsp_o ( dmi_d2h ), + // Quasi-static word address for next_dm register value. + .rv_dm_next_dm_addr_i ( '0 ), + // Multiplexed I/O + .mio_in_i ( mio_in ), + .mio_out_o ( mio_out ), + .mio_oe_o ( mio_oe ), + + // Dedicated I/O + .dio_in_i ( dio_in ), + .dio_out_o ( dio_out ), + .dio_oe_o ( dio_oe ), + + // Pad attributes + .mio_attr_o ( mio_attr ), + .dio_attr_o ( dio_attr ), + + // Memory attributes + .rom_ctrl0_cfg_i ( '0 ), + .rom_ctrl1_cfg_i ( '0 ), + .i2c_ram_1p_cfg_i ( '0 ), + .i2c_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_ret_aon_ram_1p_cfg_i ( '0 ), + .sram_ctrl_ret_aon_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_main_ram_1p_cfg_i ( '0 ), + .sram_ctrl_main_ram_1p_cfg_rsp_o ( ), + .sram_ctrl_mbox_ram_1p_cfg_i ( '0 ), + .sram_ctrl_mbox_ram_1p_cfg_rsp_o ( ), + .otbn_imem_ram_1p_cfg_i ( '0 ), + .otbn_imem_ram_1p_cfg_rsp_o ( ), + .otbn_dmem_ram_1p_cfg_i ( '0 ), + .otbn_dmem_ram_1p_cfg_rsp_o ( ), + .rv_core_ibex_icache_tag_ram_1p_cfg_i ( '0 ), + .rv_core_ibex_icache_tag_ram_1p_cfg_rsp_o ( ), + .rv_core_ibex_icache_data_ram_1p_cfg_i ( '0 ), + .rv_core_ibex_icache_data_ram_1p_cfg_rsp_o ( ), + .spi_device_ram_2p_cfg_sys2spi_i ( '0 ), + .spi_device_ram_2p_cfg_spi2sys_i ( '0 ), + .spi_device_ram_2p_cfg_rsp_sys2spi_o ( ), + .spi_device_ram_2p_cfg_rsp_spi2sys_o ( ), + + // DFT signals + .ast_lc_dft_en_o ( lc_dft_en ), + .ast_lc_hw_debug_en_o ( ), + // DFT signals + .dft_hold_tap_sel_i ( '0 ), + .scan_rst_ni ( 1'b1 ), + .scan_en_i ( 1'b0 ), + .scanmode_i ( prim_mubi_pkg::MuBi4False ) + ); +% endif + +################################################################### +## CW310/305 capture board interface ## +################################################################### +% if target["name"] in ["cw340", "cw310", "cw305"]: + + ///////////////////////////////////////////////////// + // ChipWhisperer CW310/305 Capture Board Interface // + ///////////////////////////////////////////////////// + // This is used to interface OpenTitan as a target with a capture board trough the ChipWhisperer + // 20-pin connector. This is used for SCA/FI experiments only. + + logic unused_inputs; + assign unused_inputs = manual_in_io_clkout ^ manual_in_io_trigger; + + // Synchronous clock output to capture board. + assign manual_out_io_clkout = manual_in_io_clk; + assign manual_oe_io_clkout = 1'b1; + + // Capture trigger. + // We use the clkmgr_aon_idle signal of the IP of interest to form a precise capture trigger. + // GPIO[11:10] is used for selecting the IP of interest. The encoding is as follows (see + // hint_names_e enum in clkmgr_pkg.sv for details). + // + // IP - GPIO[11:10] - Index for clkmgr_aon_idle + // ------------------------------------------------------------- + // AES - 00 - 0 + // HMAC - 01 - 1 - not implemented on CW305 + // KMAC - 10 - 2 - not implemented on CW305 + // OTBN - 11 - 3 - not implemented on CW305 + // + // GPIO9 is used for gating the selected capture trigger in software. Alternatively, GPIO8 + // can be used to implement a less precise but fully software-controlled capture trigger + // similar to what can be done on ASIC. + // + // Note that on the CW305, GPIO[9,8] are connected to LED[5(Green),7(Red)]. + + prim_mubi_pkg::mubi4_t clk_trans_idle, manual_in_io_clk_idle; + + % if target["name"] == "cw305": + assign clk_trans_idle = top_${top["name"]}.clkmgr_aon_idle; + % else: + clkmgr_pkg::hint_names_e trigger_sel; + always_comb begin : trigger_sel_mux + unique case ({mio_out[MioOutGpioGpio11], mio_out[MioOutGpioGpio10]}) + 2'b00: trigger_sel = clkmgr_pkg::HintMainAes; + 2'b01: trigger_sel = clkmgr_pkg::HintMainHmac; + 2'b10: trigger_sel = clkmgr_pkg::HintMainKmac; + 2'b11: trigger_sel = clkmgr_pkg::HintMainOtbn; + default: trigger_sel = clkmgr_pkg::HintMainAes; + endcase; + end + assign clk_trans_idle = top_${top["name"]}.clkmgr_aon_idle[trigger_sel]; + % endif + + logic clk_io_div4_trigger_hw_en, manual_in_io_clk_trigger_hw_en; + logic clk_io_div4_trigger_hw_oe, manual_in_io_clk_trigger_hw_oe; + logic clk_io_div4_trigger_sw_en, manual_in_io_clk_trigger_sw_en; + logic clk_io_div4_trigger_sw_oe, manual_in_io_clk_trigger_sw_oe; + assign clk_io_div4_trigger_hw_en = mio_out[MioOutGpioGpio9]; + assign clk_io_div4_trigger_hw_oe = mio_oe[MioOutGpioGpio9]; + assign clk_io_div4_trigger_sw_en = mio_out[MioOutGpioGpio8]; + assign clk_io_div4_trigger_sw_oe = mio_oe[MioOutGpioGpio8]; + + // Synchronize signals to manual_in_io_clk. + prim_flop_2sync #( + .Width ($bits(clk_trans_idle) + 4) + ) u_sync_trigger ( + .clk_i (manual_in_io_clk), + .rst_ni(manual_in_por_n), + .d_i ({clk_trans_idle, + clk_io_div4_trigger_hw_en, + clk_io_div4_trigger_hw_oe, + clk_io_div4_trigger_sw_en, + clk_io_div4_trigger_sw_oe}), + .q_o ({manual_in_io_clk_idle, + manual_in_io_clk_trigger_hw_en, + manual_in_io_clk_trigger_hw_oe, + manual_in_io_clk_trigger_sw_en, + manual_in_io_clk_trigger_sw_oe}) + ); + + // Generate the actual trigger signal as trigger_sw OR trigger_hw. + assign manual_attr_io_trigger = '0; + assign manual_oe_io_trigger = + manual_in_io_clk_trigger_sw_oe | manual_in_io_clk_trigger_hw_oe; + assign manual_out_io_trigger = + manual_in_io_clk_trigger_sw_en | (manual_in_io_clk_trigger_hw_en & + prim_mubi_pkg::mubi4_test_false_strict(manual_in_io_clk_idle)); +% endif + +endmodule : chip_${top["name"]}_${target["name"]} diff --git a/hw/top_darjeeling_no_ibex/templates/toplevel.sv.tpl b/hw/top_darjeeling_no_ibex/templates/toplevel.sv.tpl new file mode 120000 index 00000000000..6e2cbdc59ba --- /dev/null +++ b/hw/top_darjeeling_no_ibex/templates/toplevel.sv.tpl @@ -0,0 +1 @@ +../../top_darjeeling/templates/toplevel.sv.tpl \ No newline at end of file diff --git a/hw/top_darjeeling_no_ibex/top_darjeeling_no_ibex.core b/hw/top_darjeeling_no_ibex/top_darjeeling_no_ibex.core new file mode 100644 index 00000000000..b664ea0bd18 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/top_darjeeling_no_ibex.core @@ -0,0 +1,154 @@ +CAPI=2: +# Copyright zeroRISC Inc. +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:top_darjeeling_no_ibex:0.1" +description: "Technology-independent Darjeeling (without Ibex) toplevel" +filesets: + files_rtl_generic: + depend: + # Place the autogen packages first to avoid conflicts + - lowrisc:darjeeling_constants:top_racl_pkg + - lowrisc:darjeeling_ip:alert_handler_reg + - lowrisc:darjeeling_ip:otp_ctrl_macro_pkg + - lowrisc:darjeeling_ip:otp_ctrl_top_specific_pkg + - lowrisc:darjeeling_ip:pwrmgr_pkg + - lowrisc:ip:uart:0.1 + - lowrisc:ip:rv_dm + - lowrisc:ip:rv_timer + - lowrisc:ip:tlul + - lowrisc:ip:spi_device + - lowrisc:ip:spi_host + - lowrisc:ip:i2c + - lowrisc:ip:pattgen + - lowrisc:ip:aes + - lowrisc:ip:entropy_src + - lowrisc:ip:csrng + - lowrisc:ip:edn + - lowrisc:ip:dma + - lowrisc:ip:hmac + - lowrisc:ip:kmac + - lowrisc:ip:otbn + - lowrisc:ip:otp_macro + - lowrisc:prim:ram_1p_scr + - lowrisc:ip:sram_ctrl + - lowrisc:ip:keymgr_dpe + - lowrisc:darjeeling_constants:top_pkg + - lowrisc:constants:top_darjeeling_jtag_id_pkg + - lowrisc:constants:top_darjeeling_ibex_pmp_reset_pkg + - lowrisc:ip:lc_ctrl + - lowrisc:ip:mbx + - lowrisc:top_darjeeling_no_ibex:xbar_dbg + - lowrisc:top_darjeeling_no_ibex:xbar_main + - lowrisc:top_darjeeling_no_ibex:xbar_mbx + - lowrisc:top_darjeeling_no_ibex:xbar_peri + - lowrisc:darjeeling_ip:ac_range_check + - lowrisc:darjeeling_ip:alert_handler + - lowrisc:darjeeling_ip:clkmgr + - lowrisc:darjeeling_ip:otp_ctrl + - lowrisc:darjeeling_ip:pinmux + - lowrisc:darjeeling_ip:pwrmgr + - lowrisc:darjeeling_ip:rstmgr + - lowrisc:darjeeling_ip:rv_plic + - lowrisc:darjeeling_ip:rv_core_ibex + - lowrisc:darjeeling_ip:racl_ctrl + - lowrisc:darjeeling_ip:gpio + - lowrisc:ip:aon_timer + - lowrisc:ip:adc_ctrl + - lowrisc:ip:sysrst_ctrl + - lowrisc:ip:rom_ctrl + - lowrisc:ip:soc_dbg_ctrl + - lowrisc:systems:soc_proxy + - lowrisc:tlul:headers + - lowrisc:prim:all + - lowrisc:prim:mubi + - lowrisc:systems:top_darjeeling_no_ibex_pkg + - "fileset_partner ? (partner:systems:top_darjeeling_ast_pkg)" + - "!fileset_partner ? (lowrisc:systems:top_darjeeling_ast_pkg)" + files: + - rtl/autogen/top_darjeeling_no_ibex_rnd_cnst_pkg.sv + - rtl/autogen/top_darjeeling_no_ibex_racl_pkg.sv + - rtl/autogen/top_darjeeling_no_ibex.sv + file_type: systemVerilogSource + + files_verilator_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/top_darjeeling_no_ibex.vlt + file_type: vlt + + files_ascentlint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/top_darjeeling.waiver + file_type: waiver + + files_veriblelint_waiver: + depend: + # common waivers + - lowrisc:lint:common + - lowrisc:lint:comportable + files: + - lint/top_darjeeling.vbl + file_type: veribleLintWaiver + +mapping: + "lowrisc:virtual_constants:top_pkg": "lowrisc:darjeeling_constants:top_pkg" + "lowrisc:virtual_constants:top_racl_pkg": "lowrisc:darjeeling_constants:top_racl_pkg" + "lowrisc:systems:ast_pkg": "lowrisc:systems:top_darjeeling_ast_pkg" + "lowrisc:dv:chip_env": "lowrisc:dv:top_darjeeling_chip_env" + # TODO(#27347): prim_legacy_pkg is deprecated + "lowrisc:prim:prim_pkg": "lowrisc:prim:prim_legacy_pkg" + +parameters: + SYNTHESIS: + datatype: bool + paramtype: vlogdefine + +targets: + default: &default_target + filesets: + - tool_verilator ? (files_verilator_waiver) + - tool_ascentlint ? (files_ascentlint_waiver) + - tool_veriblelint ? (files_veriblelint_waiver) + - files_rtl_generic + toplevel: top_darjeeling_no_ibex + + sim: + default_tool: icarus + filesets: + - files_rtl_generic + toplevel: top_darjeeling_no_ibex + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" + + syn: + <<: *default_target + # TODO: set default to DC once + # this option is available + # olofk/edalize#89 + default_tool: icarus + parameters: + - SYNTHESIS=true + toplevel: top_darjeeling_no_ibex + + formal: + <<: *default_target + toplevel: top_darjeeling_no_ibex + diff --git a/hw/top_darjeeling_no_ibex/top_darjeeling_no_ibex_pkg.core b/hw/top_darjeeling_no_ibex/top_darjeeling_no_ibex_pkg.core new file mode 100644 index 00000000000..480f7c65c84 --- /dev/null +++ b/hw/top_darjeeling_no_ibex/top_darjeeling_no_ibex_pkg.core @@ -0,0 +1,18 @@ +CAPI=2: +# Copyright zeroRISC Inc. +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:systems:top_darjeeling_no_ibex_pkg:0.1" +description: "Autogenerated top_darjeeling_no_ibex_pkg used in RTL and DV." +filesets: + files_rtl: + files: + - rtl/autogen/top_darjeeling_no_ibex_pkg.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - files_rtl + diff --git a/hw/top_earlgrey/data/autogen/BUILD b/hw/top_earlgrey/data/autogen/BUILD index e8ea69918aa..d3ce2c427c3 100644 --- a/hw/top_earlgrey/data/autogen/BUILD +++ b/hw/top_earlgrey/data/autogen/BUILD @@ -1,3 +1,4 @@ +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_earlgrey/data/autogen/defs.bzl b/hw/top_earlgrey/data/autogen/defs.bzl index 9a5028a769d..ba5c57f57d9 100644 --- a/hw/top_earlgrey/data/autogen/defs.bzl +++ b/hw/top_earlgrey/data/autogen/defs.bzl @@ -1,3 +1,4 @@ +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 9dc63587ed0..22af0a0d183 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index 6462e8d1293..44285a47b6c 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson index 6afee9b904e..3d049f8eea1 100644 --- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv b/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv index 0197fa02f93..4b8a3e050f4 100644 --- a/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/otp_ctrl/rtl/otp_ctrl_part_pkg.sv @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_englishbreakfast/data/autogen/BUILD b/hw/top_englishbreakfast/data/autogen/BUILD index c55f14ceea5..04e78df6957 100644 --- a/hw/top_englishbreakfast/data/autogen/BUILD +++ b/hw/top_englishbreakfast/data/autogen/BUILD @@ -1,3 +1,4 @@ +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_englishbreakfast/data/autogen/defs.bzl b/hw/top_englishbreakfast/data/autogen/defs.bzl index 6a245a735f1..b064465f8ea 100644 --- a/hw/top_englishbreakfast/data/autogen/defs.bzl +++ b/hw/top_englishbreakfast/data/autogen/defs.bzl @@ -1,3 +1,4 @@ +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson index 672466a2c23..352cf10f80d 100644 --- a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson +++ b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.gen.hjson index aede9f4ed0e..75c0bd6363d 100644 --- a/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson index 46ba5b06b05..e0601b8f2ae 100644 --- a/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson +++ b/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/sw/host/opentitanlib/src/chip/autogen/darjeeling.rs b/sw/host/opentitanlib/src/chip/autogen/darjeeling.rs index dc545aac177..a9373556bba 100644 --- a/sw/host/opentitanlib/src/chip/autogen/darjeeling.rs +++ b/sw/host/opentitanlib/src/chip/autogen/darjeeling.rs @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/sw/host/opentitanlib/src/chip/autogen/darjeeling_no_ibex.rs b/sw/host/opentitanlib/src/chip/autogen/darjeeling_no_ibex.rs new file mode 100644 index 00000000000..a9373556bba --- /dev/null +++ b/sw/host/opentitanlib/src/chip/autogen/darjeeling_no_ibex.rs @@ -0,0 +1,173 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "host_toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +use crate::with_unknown; + +with_unknown! { + pub enum PinmuxPeripheralIn: u32 [default = Self::End] { + SocProxySocGpi12 = 0, + SocProxySocGpi13 = 1, + SocProxySocGpi14 = 2, + SocProxySocGpi15 = 3, + End = 4, + } + + pub enum PinmuxInsel: u32 [default = Self::End] { + ConstantZero = 0, + ConstantOne = 1, + Mio0 = 2, + Mio1 = 3, + Mio2 = 4, + Mio3 = 5, + Mio4 = 6, + Mio5 = 7, + Mio6 = 8, + Mio7 = 9, + Mio8 = 10, + Mio9 = 11, + Mio10 = 12, + Mio11 = 13, + End = 14, + } + + pub enum PinmuxMioOut: u32 [default = Self::End] { + Mio0 = 0, + Mio1 = 1, + Mio2 = 2, + Mio3 = 3, + Mio4 = 4, + Mio5 = 5, + Mio6 = 6, + Mio7 = 7, + Mio8 = 8, + Mio9 = 9, + Mio10 = 10, + Mio11 = 11, + End = 12, + } + + pub enum PinmuxOutsel: u32 [default = Self::End] { + ConstantZero = 0, + ConstantOne = 1, + ConstantHighZ = 2, + SocProxySocGpo12 = 3, + SocProxySocGpo13 = 4, + SocProxySocGpo14 = 5, + SocProxySocGpo15 = 6, + OtpMacroTest0 = 7, + End = 8, + } + + pub enum DirectPads: u32 [default = Self::End] { + SpiHost0Sd0 = 0, + SpiHost0Sd1 = 1, + SpiHost0Sd2 = 2, + SpiHost0Sd3 = 3, + SpiDeviceSd0 = 4, + SpiDeviceSd1 = 5, + SpiDeviceSd2 = 6, + SpiDeviceSd3 = 7, + I2c0Scl = 8, + I2c0Sda = 9, + GpioGpio0 = 10, + GpioGpio1 = 11, + GpioGpio2 = 12, + GpioGpio3 = 13, + GpioGpio4 = 14, + GpioGpio5 = 15, + GpioGpio6 = 16, + GpioGpio7 = 17, + GpioGpio8 = 18, + GpioGpio9 = 19, + GpioGpio10 = 20, + GpioGpio11 = 21, + GpioGpio12 = 22, + GpioGpio13 = 23, + GpioGpio14 = 24, + GpioGpio15 = 25, + GpioGpio16 = 26, + GpioGpio17 = 27, + GpioGpio18 = 28, + GpioGpio19 = 29, + GpioGpio20 = 30, + GpioGpio21 = 31, + GpioGpio22 = 32, + GpioGpio23 = 33, + GpioGpio24 = 34, + GpioGpio25 = 35, + GpioGpio26 = 36, + GpioGpio27 = 37, + GpioGpio28 = 38, + GpioGpio29 = 39, + GpioGpio30 = 40, + GpioGpio31 = 41, + SpiDeviceSck = 42, + SpiDeviceCsb = 43, + SpiDeviceTpmCsb = 44, + Uart0Rx = 45, + SocProxySocGpi0 = 46, + SocProxySocGpi1 = 47, + SocProxySocGpi2 = 48, + SocProxySocGpi3 = 49, + SocProxySocGpi4 = 50, + SocProxySocGpi5 = 51, + SocProxySocGpi6 = 52, + SocProxySocGpi7 = 53, + SocProxySocGpi8 = 54, + SocProxySocGpi9 = 55, + SocProxySocGpi10 = 56, + SocProxySocGpi11 = 57, + SpiHost0Sck = 58, + SpiHost0Csb = 59, + Uart0Tx = 60, + SocProxySocGpo0 = 61, + SocProxySocGpo1 = 62, + SocProxySocGpo2 = 63, + SocProxySocGpo3 = 64, + SocProxySocGpo4 = 65, + SocProxySocGpo5 = 66, + SocProxySocGpo6 = 67, + SocProxySocGpo7 = 68, + SocProxySocGpo8 = 69, + SocProxySocGpo9 = 70, + SocProxySocGpo10 = 71, + SocProxySocGpo11 = 72, + End = 73, + } + + pub enum MuxedPads: u32 [default = Self::End] { + Mio0 = 0, + Mio1 = 1, + Mio2 = 2, + Mio3 = 3, + Mio4 = 4, + Mio5 = 5, + Mio6 = 6, + Mio7 = 7, + Mio8 = 8, + Mio9 = 9, + Mio10 = 10, + Mio11 = 11, + End = 12, + } +} + +#[allow(non_camel_case_types)] +pub mod ujson_alias { + use super::*; + // Create aliases for the C names of these types so that the ujson + // created structs can access these structures by their C names. + pub type pinmux_peripheral_in_t = PinmuxPeripheralIn; + pub type pinmux_insel_t = PinmuxInsel; + pub type pinmux_mio_out_t = PinmuxMioOut; + pub type pinmux_outsel_t = PinmuxOutsel; +} diff --git a/sw/host/opentitanlib/src/chip/autogen/darjeeling_no_ibex_soc_dbg.rs b/sw/host/opentitanlib/src/chip/autogen/darjeeling_no_ibex_soc_dbg.rs new file mode 100644 index 00000000000..c2d490f9d3a --- /dev/null +++ b/sw/host/opentitanlib/src/chip/autogen/darjeeling_no_ibex_soc_dbg.rs @@ -0,0 +1,13 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "host_toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +use crate::with_unknown; diff --git a/sw/host/opentitanlib/src/chip/autogen/darjeeling_no_ibex_soc_mbx.rs b/sw/host/opentitanlib/src/chip/autogen/darjeeling_no_ibex_soc_mbx.rs new file mode 100644 index 00000000000..c2d490f9d3a --- /dev/null +++ b/sw/host/opentitanlib/src/chip/autogen/darjeeling_no_ibex_soc_mbx.rs @@ -0,0 +1,13 @@ +// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. +// Please do not modify content of this file directly. +// File generated by using template: "host_toplevel.rs.tpl" +// To regenerate this file follow OpenTitan topgen documentations. + +#![allow(dead_code)] + +use crate::with_unknown; diff --git a/sw/host/opentitanlib/src/chip/autogen/darjeeling_soc_dbg.rs b/sw/host/opentitanlib/src/chip/autogen/darjeeling_soc_dbg.rs index 315e0b0de58..c2d490f9d3a 100644 --- a/sw/host/opentitanlib/src/chip/autogen/darjeeling_soc_dbg.rs +++ b/sw/host/opentitanlib/src/chip/autogen/darjeeling_soc_dbg.rs @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/sw/host/opentitanlib/src/chip/autogen/darjeeling_soc_mbx.rs b/sw/host/opentitanlib/src/chip/autogen/darjeeling_soc_mbx.rs index 315e0b0de58..c2d490f9d3a 100644 --- a/sw/host/opentitanlib/src/chip/autogen/darjeeling_soc_mbx.rs +++ b/sw/host/opentitanlib/src/chip/autogen/darjeeling_soc_mbx.rs @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs b/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs index d66d1d75361..16d3e9c4b9a 100644 --- a/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs +++ b/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/sw/host/opentitanlib/src/chip/autogen/englishbreakfast.rs b/sw/host/opentitanlib/src/chip/autogen/englishbreakfast.rs index f7a7c2ea637..2d5469422d9 100644 --- a/sw/host/opentitanlib/src/chip/autogen/englishbreakfast.rs +++ b/sw/host/opentitanlib/src/chip/autogen/englishbreakfast.rs @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/util/topgen.py b/util/topgen.py index e244727b8f4..689273cc4c5 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -1,4 +1,5 @@ #!/usr/bin/env python3 +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -54,7 +55,8 @@ // ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// // PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: """ -genhdr = """// Copyright lowRISC contributors (OpenTitan project). +genhdr = """// Copyright zeroRISC Inc. +// Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 """ + warnhdr diff --git a/util/topgen/templates/data_BUILD.tpl b/util/topgen/templates/data_BUILD.tpl index 456344d945c..0e365b2e930 100644 --- a/util/topgen/templates/data_BUILD.tpl +++ b/util/topgen/templates/data_BUILD.tpl @@ -1,3 +1,4 @@ +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 diff --git a/util/topgen/templates/data_defs.bzl.tpl b/util/topgen/templates/data_defs.bzl.tpl index 15b82d71787..3fc600aa003 100644 --- a/util/topgen/templates/data_defs.bzl.tpl +++ b/util/topgen/templates/data_defs.bzl.tpl @@ -1,3 +1,4 @@ +# Copyright zeroRISC Inc. # Copyright lowRISC contributors (OpenTitan project). # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 diff --git a/util/topgen/templates/host_toplevel.rs.tpl b/util/topgen/templates/host_toplevel.rs.tpl index 49d8ef72415..252a54c998e 100644 --- a/util/topgen/templates/host_toplevel.rs.tpl +++ b/util/topgen/templates/host_toplevel.rs.tpl @@ -1,3 +1,4 @@ +// Copyright zeroRISC Inc. // Copyright lowRISC contributors (OpenTitan project). // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0